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mtd: nand: atmel: Relax tADL_min constraint
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "i915_gem_clflush.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
51
52 static bool is_mmio_work(struct intel_flip_work *work)
53 {
54 return work->mmio_work.func;
55 }
56
57 /* Primary plane formats for gen <= 3 */
58 static const uint32_t i8xx_primary_formats[] = {
59 DRM_FORMAT_C8,
60 DRM_FORMAT_RGB565,
61 DRM_FORMAT_XRGB1555,
62 DRM_FORMAT_XRGB8888,
63 };
64
65 /* Primary plane formats for gen >= 4 */
66 static const uint32_t i965_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_XRGB2101010,
72 DRM_FORMAT_XBGR2101010,
73 };
74
75 static const uint32_t skl_primary_formats[] = {
76 DRM_FORMAT_C8,
77 DRM_FORMAT_RGB565,
78 DRM_FORMAT_XRGB8888,
79 DRM_FORMAT_XBGR8888,
80 DRM_FORMAT_ARGB8888,
81 DRM_FORMAT_ABGR8888,
82 DRM_FORMAT_XRGB2101010,
83 DRM_FORMAT_XBGR2101010,
84 DRM_FORMAT_YUYV,
85 DRM_FORMAT_YVYU,
86 DRM_FORMAT_UYVY,
87 DRM_FORMAT_VYUY,
88 };
89
90 /* Cursor formats */
91 static const uint32_t intel_cursor_formats[] = {
92 DRM_FORMAT_ARGB8888,
93 };
94
95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
96 struct intel_crtc_state *pipe_config);
97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
98 struct intel_crtc_state *pipe_config);
99
100 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
101 struct drm_i915_gem_object *obj,
102 struct drm_mode_fb_cmd2 *mode_cmd);
103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
107 struct intel_link_m_n *m_n,
108 struct intel_link_m_n *m2_n2);
109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
112 static void vlv_prepare_pll(struct intel_crtc *crtc,
113 const struct intel_crtc_state *pipe_config);
114 static void chv_prepare_pll(struct intel_crtc *crtc,
115 const struct intel_crtc_state *pipe_config);
116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
119 struct intel_crtc_state *crtc_state);
120 static void skylake_pfit_enable(struct intel_crtc *crtc);
121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
123 static void intel_modeset_setup_hw_state(struct drm_device *dev,
124 struct drm_modeset_acquire_ctx *ctx);
125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
126
127 struct intel_limit {
128 struct {
129 int min, max;
130 } dot, vco, n, m, m1, m2, p, p1;
131
132 struct {
133 int dot_limit;
134 int p2_slow, p2_fast;
135 } p2;
136 };
137
138 /* returns HPLL frequency in kHz */
139 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
140 {
141 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
142
143 /* Obtain SKU information */
144 mutex_lock(&dev_priv->sb_lock);
145 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
146 CCK_FUSE_HPLL_FREQ_MASK;
147 mutex_unlock(&dev_priv->sb_lock);
148
149 return vco_freq[hpll_freq] * 1000;
150 }
151
152 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
153 const char *name, u32 reg, int ref_freq)
154 {
155 u32 val;
156 int divider;
157
158 mutex_lock(&dev_priv->sb_lock);
159 val = vlv_cck_read(dev_priv, reg);
160 mutex_unlock(&dev_priv->sb_lock);
161
162 divider = val & CCK_FREQUENCY_VALUES;
163
164 WARN((val & CCK_FREQUENCY_STATUS) !=
165 (divider << CCK_FREQUENCY_STATUS_SHIFT),
166 "%s change in progress\n", name);
167
168 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
169 }
170
171 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
172 const char *name, u32 reg)
173 {
174 if (dev_priv->hpll_freq == 0)
175 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
176
177 return vlv_get_cck_clock(dev_priv, name, reg,
178 dev_priv->hpll_freq);
179 }
180
181 static void intel_update_czclk(struct drm_i915_private *dev_priv)
182 {
183 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
184 return;
185
186 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
187 CCK_CZ_CLOCK_CONTROL);
188
189 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
190 }
191
192 static inline u32 /* units of 100MHz */
193 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
194 const struct intel_crtc_state *pipe_config)
195 {
196 if (HAS_DDI(dev_priv))
197 return pipe_config->port_clock; /* SPLL */
198 else if (IS_GEN5(dev_priv))
199 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
200 else
201 return 270000;
202 }
203
204 static const struct intel_limit intel_limits_i8xx_dac = {
205 .dot = { .min = 25000, .max = 350000 },
206 .vco = { .min = 908000, .max = 1512000 },
207 .n = { .min = 2, .max = 16 },
208 .m = { .min = 96, .max = 140 },
209 .m1 = { .min = 18, .max = 26 },
210 .m2 = { .min = 6, .max = 16 },
211 .p = { .min = 4, .max = 128 },
212 .p1 = { .min = 2, .max = 33 },
213 .p2 = { .dot_limit = 165000,
214 .p2_slow = 4, .p2_fast = 2 },
215 };
216
217 static const struct intel_limit intel_limits_i8xx_dvo = {
218 .dot = { .min = 25000, .max = 350000 },
219 .vco = { .min = 908000, .max = 1512000 },
220 .n = { .min = 2, .max = 16 },
221 .m = { .min = 96, .max = 140 },
222 .m1 = { .min = 18, .max = 26 },
223 .m2 = { .min = 6, .max = 16 },
224 .p = { .min = 4, .max = 128 },
225 .p1 = { .min = 2, .max = 33 },
226 .p2 = { .dot_limit = 165000,
227 .p2_slow = 4, .p2_fast = 4 },
228 };
229
230 static const struct intel_limit intel_limits_i8xx_lvds = {
231 .dot = { .min = 25000, .max = 350000 },
232 .vco = { .min = 908000, .max = 1512000 },
233 .n = { .min = 2, .max = 16 },
234 .m = { .min = 96, .max = 140 },
235 .m1 = { .min = 18, .max = 26 },
236 .m2 = { .min = 6, .max = 16 },
237 .p = { .min = 4, .max = 128 },
238 .p1 = { .min = 1, .max = 6 },
239 .p2 = { .dot_limit = 165000,
240 .p2_slow = 14, .p2_fast = 7 },
241 };
242
243 static const struct intel_limit intel_limits_i9xx_sdvo = {
244 .dot = { .min = 20000, .max = 400000 },
245 .vco = { .min = 1400000, .max = 2800000 },
246 .n = { .min = 1, .max = 6 },
247 .m = { .min = 70, .max = 120 },
248 .m1 = { .min = 8, .max = 18 },
249 .m2 = { .min = 3, .max = 7 },
250 .p = { .min = 5, .max = 80 },
251 .p1 = { .min = 1, .max = 8 },
252 .p2 = { .dot_limit = 200000,
253 .p2_slow = 10, .p2_fast = 5 },
254 };
255
256 static const struct intel_limit intel_limits_i9xx_lvds = {
257 .dot = { .min = 20000, .max = 400000 },
258 .vco = { .min = 1400000, .max = 2800000 },
259 .n = { .min = 1, .max = 6 },
260 .m = { .min = 70, .max = 120 },
261 .m1 = { .min = 8, .max = 18 },
262 .m2 = { .min = 3, .max = 7 },
263 .p = { .min = 7, .max = 98 },
264 .p1 = { .min = 1, .max = 8 },
265 .p2 = { .dot_limit = 112000,
266 .p2_slow = 14, .p2_fast = 7 },
267 };
268
269
270 static const struct intel_limit intel_limits_g4x_sdvo = {
271 .dot = { .min = 25000, .max = 270000 },
272 .vco = { .min = 1750000, .max = 3500000},
273 .n = { .min = 1, .max = 4 },
274 .m = { .min = 104, .max = 138 },
275 .m1 = { .min = 17, .max = 23 },
276 .m2 = { .min = 5, .max = 11 },
277 .p = { .min = 10, .max = 30 },
278 .p1 = { .min = 1, .max = 3},
279 .p2 = { .dot_limit = 270000,
280 .p2_slow = 10,
281 .p2_fast = 10
282 },
283 };
284
285 static const struct intel_limit intel_limits_g4x_hdmi = {
286 .dot = { .min = 22000, .max = 400000 },
287 .vco = { .min = 1750000, .max = 3500000},
288 .n = { .min = 1, .max = 4 },
289 .m = { .min = 104, .max = 138 },
290 .m1 = { .min = 16, .max = 23 },
291 .m2 = { .min = 5, .max = 11 },
292 .p = { .min = 5, .max = 80 },
293 .p1 = { .min = 1, .max = 8},
294 .p2 = { .dot_limit = 165000,
295 .p2_slow = 10, .p2_fast = 5 },
296 };
297
298 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
299 .dot = { .min = 20000, .max = 115000 },
300 .vco = { .min = 1750000, .max = 3500000 },
301 .n = { .min = 1, .max = 3 },
302 .m = { .min = 104, .max = 138 },
303 .m1 = { .min = 17, .max = 23 },
304 .m2 = { .min = 5, .max = 11 },
305 .p = { .min = 28, .max = 112 },
306 .p1 = { .min = 2, .max = 8 },
307 .p2 = { .dot_limit = 0,
308 .p2_slow = 14, .p2_fast = 14
309 },
310 };
311
312 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
313 .dot = { .min = 80000, .max = 224000 },
314 .vco = { .min = 1750000, .max = 3500000 },
315 .n = { .min = 1, .max = 3 },
316 .m = { .min = 104, .max = 138 },
317 .m1 = { .min = 17, .max = 23 },
318 .m2 = { .min = 5, .max = 11 },
319 .p = { .min = 14, .max = 42 },
320 .p1 = { .min = 2, .max = 6 },
321 .p2 = { .dot_limit = 0,
322 .p2_slow = 7, .p2_fast = 7
323 },
324 };
325
326 static const struct intel_limit intel_limits_pineview_sdvo = {
327 .dot = { .min = 20000, .max = 400000},
328 .vco = { .min = 1700000, .max = 3500000 },
329 /* Pineview's Ncounter is a ring counter */
330 .n = { .min = 3, .max = 6 },
331 .m = { .min = 2, .max = 256 },
332 /* Pineview only has one combined m divider, which we treat as m2. */
333 .m1 = { .min = 0, .max = 0 },
334 .m2 = { .min = 0, .max = 254 },
335 .p = { .min = 5, .max = 80 },
336 .p1 = { .min = 1, .max = 8 },
337 .p2 = { .dot_limit = 200000,
338 .p2_slow = 10, .p2_fast = 5 },
339 };
340
341 static const struct intel_limit intel_limits_pineview_lvds = {
342 .dot = { .min = 20000, .max = 400000 },
343 .vco = { .min = 1700000, .max = 3500000 },
344 .n = { .min = 3, .max = 6 },
345 .m = { .min = 2, .max = 256 },
346 .m1 = { .min = 0, .max = 0 },
347 .m2 = { .min = 0, .max = 254 },
348 .p = { .min = 7, .max = 112 },
349 .p1 = { .min = 1, .max = 8 },
350 .p2 = { .dot_limit = 112000,
351 .p2_slow = 14, .p2_fast = 14 },
352 };
353
354 /* Ironlake / Sandybridge
355 *
356 * We calculate clock using (register_value + 2) for N/M1/M2, so here
357 * the range value for them is (actual_value - 2).
358 */
359 static const struct intel_limit intel_limits_ironlake_dac = {
360 .dot = { .min = 25000, .max = 350000 },
361 .vco = { .min = 1760000, .max = 3510000 },
362 .n = { .min = 1, .max = 5 },
363 .m = { .min = 79, .max = 127 },
364 .m1 = { .min = 12, .max = 22 },
365 .m2 = { .min = 5, .max = 9 },
366 .p = { .min = 5, .max = 80 },
367 .p1 = { .min = 1, .max = 8 },
368 .p2 = { .dot_limit = 225000,
369 .p2_slow = 10, .p2_fast = 5 },
370 };
371
372 static const struct intel_limit intel_limits_ironlake_single_lvds = {
373 .dot = { .min = 25000, .max = 350000 },
374 .vco = { .min = 1760000, .max = 3510000 },
375 .n = { .min = 1, .max = 3 },
376 .m = { .min = 79, .max = 118 },
377 .m1 = { .min = 12, .max = 22 },
378 .m2 = { .min = 5, .max = 9 },
379 .p = { .min = 28, .max = 112 },
380 .p1 = { .min = 2, .max = 8 },
381 .p2 = { .dot_limit = 225000,
382 .p2_slow = 14, .p2_fast = 14 },
383 };
384
385 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
386 .dot = { .min = 25000, .max = 350000 },
387 .vco = { .min = 1760000, .max = 3510000 },
388 .n = { .min = 1, .max = 3 },
389 .m = { .min = 79, .max = 127 },
390 .m1 = { .min = 12, .max = 22 },
391 .m2 = { .min = 5, .max = 9 },
392 .p = { .min = 14, .max = 56 },
393 .p1 = { .min = 2, .max = 8 },
394 .p2 = { .dot_limit = 225000,
395 .p2_slow = 7, .p2_fast = 7 },
396 };
397
398 /* LVDS 100mhz refclk limits. */
399 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
400 .dot = { .min = 25000, .max = 350000 },
401 .vco = { .min = 1760000, .max = 3510000 },
402 .n = { .min = 1, .max = 2 },
403 .m = { .min = 79, .max = 126 },
404 .m1 = { .min = 12, .max = 22 },
405 .m2 = { .min = 5, .max = 9 },
406 .p = { .min = 28, .max = 112 },
407 .p1 = { .min = 2, .max = 8 },
408 .p2 = { .dot_limit = 225000,
409 .p2_slow = 14, .p2_fast = 14 },
410 };
411
412 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
413 .dot = { .min = 25000, .max = 350000 },
414 .vco = { .min = 1760000, .max = 3510000 },
415 .n = { .min = 1, .max = 3 },
416 .m = { .min = 79, .max = 126 },
417 .m1 = { .min = 12, .max = 22 },
418 .m2 = { .min = 5, .max = 9 },
419 .p = { .min = 14, .max = 42 },
420 .p1 = { .min = 2, .max = 6 },
421 .p2 = { .dot_limit = 225000,
422 .p2_slow = 7, .p2_fast = 7 },
423 };
424
425 static const struct intel_limit intel_limits_vlv = {
426 /*
427 * These are the data rate limits (measured in fast clocks)
428 * since those are the strictest limits we have. The fast
429 * clock and actual rate limits are more relaxed, so checking
430 * them would make no difference.
431 */
432 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
433 .vco = { .min = 4000000, .max = 6000000 },
434 .n = { .min = 1, .max = 7 },
435 .m1 = { .min = 2, .max = 3 },
436 .m2 = { .min = 11, .max = 156 },
437 .p1 = { .min = 2, .max = 3 },
438 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
439 };
440
441 static const struct intel_limit intel_limits_chv = {
442 /*
443 * These are the data rate limits (measured in fast clocks)
444 * since those are the strictest limits we have. The fast
445 * clock and actual rate limits are more relaxed, so checking
446 * them would make no difference.
447 */
448 .dot = { .min = 25000 * 5, .max = 540000 * 5},
449 .vco = { .min = 4800000, .max = 6480000 },
450 .n = { .min = 1, .max = 1 },
451 .m1 = { .min = 2, .max = 2 },
452 .m2 = { .min = 24 << 22, .max = 175 << 22 },
453 .p1 = { .min = 2, .max = 4 },
454 .p2 = { .p2_slow = 1, .p2_fast = 14 },
455 };
456
457 static const struct intel_limit intel_limits_bxt = {
458 /* FIXME: find real dot limits */
459 .dot = { .min = 0, .max = INT_MAX },
460 .vco = { .min = 4800000, .max = 6700000 },
461 .n = { .min = 1, .max = 1 },
462 .m1 = { .min = 2, .max = 2 },
463 /* FIXME: find real m2 limits */
464 .m2 = { .min = 2 << 22, .max = 255 << 22 },
465 .p1 = { .min = 2, .max = 4 },
466 .p2 = { .p2_slow = 1, .p2_fast = 20 },
467 };
468
469 static bool
470 needs_modeset(struct drm_crtc_state *state)
471 {
472 return drm_atomic_crtc_needs_modeset(state);
473 }
474
475 /*
476 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
477 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
478 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
479 * The helpers' return value is the rate of the clock that is fed to the
480 * display engine's pipe which can be the above fast dot clock rate or a
481 * divided-down version of it.
482 */
483 /* m1 is reserved as 0 in Pineview, n is a ring counter */
484 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
485 {
486 clock->m = clock->m2 + 2;
487 clock->p = clock->p1 * clock->p2;
488 if (WARN_ON(clock->n == 0 || clock->p == 0))
489 return 0;
490 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
491 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
492
493 return clock->dot;
494 }
495
496 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
497 {
498 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
499 }
500
501 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
502 {
503 clock->m = i9xx_dpll_compute_m(clock);
504 clock->p = clock->p1 * clock->p2;
505 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
506 return 0;
507 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
508 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
509
510 return clock->dot;
511 }
512
513 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
514 {
515 clock->m = clock->m1 * clock->m2;
516 clock->p = clock->p1 * clock->p2;
517 if (WARN_ON(clock->n == 0 || clock->p == 0))
518 return 0;
519 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
520 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
521
522 return clock->dot / 5;
523 }
524
525 int chv_calc_dpll_params(int refclk, struct dpll *clock)
526 {
527 clock->m = clock->m1 * clock->m2;
528 clock->p = clock->p1 * clock->p2;
529 if (WARN_ON(clock->n == 0 || clock->p == 0))
530 return 0;
531 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
532 clock->n << 22);
533 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
534
535 return clock->dot / 5;
536 }
537
538 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
539 /**
540 * Returns whether the given set of divisors are valid for a given refclk with
541 * the given connectors.
542 */
543
544 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
545 const struct intel_limit *limit,
546 const struct dpll *clock)
547 {
548 if (clock->n < limit->n.min || limit->n.max < clock->n)
549 INTELPllInvalid("n out of range\n");
550 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
551 INTELPllInvalid("p1 out of range\n");
552 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
553 INTELPllInvalid("m2 out of range\n");
554 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
555 INTELPllInvalid("m1 out of range\n");
556
557 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
558 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
559 if (clock->m1 <= clock->m2)
560 INTELPllInvalid("m1 <= m2\n");
561
562 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
563 !IS_GEN9_LP(dev_priv)) {
564 if (clock->p < limit->p.min || limit->p.max < clock->p)
565 INTELPllInvalid("p out of range\n");
566 if (clock->m < limit->m.min || limit->m.max < clock->m)
567 INTELPllInvalid("m out of range\n");
568 }
569
570 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
571 INTELPllInvalid("vco out of range\n");
572 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
573 * connector, etc., rather than just a single range.
574 */
575 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
576 INTELPllInvalid("dot out of range\n");
577
578 return true;
579 }
580
581 static int
582 i9xx_select_p2_div(const struct intel_limit *limit,
583 const struct intel_crtc_state *crtc_state,
584 int target)
585 {
586 struct drm_device *dev = crtc_state->base.crtc->dev;
587
588 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
589 /*
590 * For LVDS just rely on its current settings for dual-channel.
591 * We haven't figured out how to reliably set up different
592 * single/dual channel state, if we even can.
593 */
594 if (intel_is_dual_link_lvds(dev))
595 return limit->p2.p2_fast;
596 else
597 return limit->p2.p2_slow;
598 } else {
599 if (target < limit->p2.dot_limit)
600 return limit->p2.p2_slow;
601 else
602 return limit->p2.p2_fast;
603 }
604 }
605
606 /*
607 * Returns a set of divisors for the desired target clock with the given
608 * refclk, or FALSE. The returned values represent the clock equation:
609 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
610 *
611 * Target and reference clocks are specified in kHz.
612 *
613 * If match_clock is provided, then best_clock P divider must match the P
614 * divider from @match_clock used for LVDS downclocking.
615 */
616 static bool
617 i9xx_find_best_dpll(const struct intel_limit *limit,
618 struct intel_crtc_state *crtc_state,
619 int target, int refclk, struct dpll *match_clock,
620 struct dpll *best_clock)
621 {
622 struct drm_device *dev = crtc_state->base.crtc->dev;
623 struct dpll clock;
624 int err = target;
625
626 memset(best_clock, 0, sizeof(*best_clock));
627
628 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
629
630 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
631 clock.m1++) {
632 for (clock.m2 = limit->m2.min;
633 clock.m2 <= limit->m2.max; clock.m2++) {
634 if (clock.m2 >= clock.m1)
635 break;
636 for (clock.n = limit->n.min;
637 clock.n <= limit->n.max; clock.n++) {
638 for (clock.p1 = limit->p1.min;
639 clock.p1 <= limit->p1.max; clock.p1++) {
640 int this_err;
641
642 i9xx_calc_dpll_params(refclk, &clock);
643 if (!intel_PLL_is_valid(to_i915(dev),
644 limit,
645 &clock))
646 continue;
647 if (match_clock &&
648 clock.p != match_clock->p)
649 continue;
650
651 this_err = abs(clock.dot - target);
652 if (this_err < err) {
653 *best_clock = clock;
654 err = this_err;
655 }
656 }
657 }
658 }
659 }
660
661 return (err != target);
662 }
663
664 /*
665 * Returns a set of divisors for the desired target clock with the given
666 * refclk, or FALSE. The returned values represent the clock equation:
667 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
668 *
669 * Target and reference clocks are specified in kHz.
670 *
671 * If match_clock is provided, then best_clock P divider must match the P
672 * divider from @match_clock used for LVDS downclocking.
673 */
674 static bool
675 pnv_find_best_dpll(const struct intel_limit *limit,
676 struct intel_crtc_state *crtc_state,
677 int target, int refclk, struct dpll *match_clock,
678 struct dpll *best_clock)
679 {
680 struct drm_device *dev = crtc_state->base.crtc->dev;
681 struct dpll clock;
682 int err = target;
683
684 memset(best_clock, 0, sizeof(*best_clock));
685
686 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
687
688 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
689 clock.m1++) {
690 for (clock.m2 = limit->m2.min;
691 clock.m2 <= limit->m2.max; clock.m2++) {
692 for (clock.n = limit->n.min;
693 clock.n <= limit->n.max; clock.n++) {
694 for (clock.p1 = limit->p1.min;
695 clock.p1 <= limit->p1.max; clock.p1++) {
696 int this_err;
697
698 pnv_calc_dpll_params(refclk, &clock);
699 if (!intel_PLL_is_valid(to_i915(dev),
700 limit,
701 &clock))
702 continue;
703 if (match_clock &&
704 clock.p != match_clock->p)
705 continue;
706
707 this_err = abs(clock.dot - target);
708 if (this_err < err) {
709 *best_clock = clock;
710 err = this_err;
711 }
712 }
713 }
714 }
715 }
716
717 return (err != target);
718 }
719
720 /*
721 * Returns a set of divisors for the desired target clock with the given
722 * refclk, or FALSE. The returned values represent the clock equation:
723 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
724 *
725 * Target and reference clocks are specified in kHz.
726 *
727 * If match_clock is provided, then best_clock P divider must match the P
728 * divider from @match_clock used for LVDS downclocking.
729 */
730 static bool
731 g4x_find_best_dpll(const struct intel_limit *limit,
732 struct intel_crtc_state *crtc_state,
733 int target, int refclk, struct dpll *match_clock,
734 struct dpll *best_clock)
735 {
736 struct drm_device *dev = crtc_state->base.crtc->dev;
737 struct dpll clock;
738 int max_n;
739 bool found = false;
740 /* approximately equals target * 0.00585 */
741 int err_most = (target >> 8) + (target >> 9);
742
743 memset(best_clock, 0, sizeof(*best_clock));
744
745 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
746
747 max_n = limit->n.max;
748 /* based on hardware requirement, prefer smaller n to precision */
749 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
750 /* based on hardware requirement, prefere larger m1,m2 */
751 for (clock.m1 = limit->m1.max;
752 clock.m1 >= limit->m1.min; clock.m1--) {
753 for (clock.m2 = limit->m2.max;
754 clock.m2 >= limit->m2.min; clock.m2--) {
755 for (clock.p1 = limit->p1.max;
756 clock.p1 >= limit->p1.min; clock.p1--) {
757 int this_err;
758
759 i9xx_calc_dpll_params(refclk, &clock);
760 if (!intel_PLL_is_valid(to_i915(dev),
761 limit,
762 &clock))
763 continue;
764
765 this_err = abs(clock.dot - target);
766 if (this_err < err_most) {
767 *best_clock = clock;
768 err_most = this_err;
769 max_n = clock.n;
770 found = true;
771 }
772 }
773 }
774 }
775 }
776 return found;
777 }
778
779 /*
780 * Check if the calculated PLL configuration is more optimal compared to the
781 * best configuration and error found so far. Return the calculated error.
782 */
783 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
784 const struct dpll *calculated_clock,
785 const struct dpll *best_clock,
786 unsigned int best_error_ppm,
787 unsigned int *error_ppm)
788 {
789 /*
790 * For CHV ignore the error and consider only the P value.
791 * Prefer a bigger P value based on HW requirements.
792 */
793 if (IS_CHERRYVIEW(to_i915(dev))) {
794 *error_ppm = 0;
795
796 return calculated_clock->p > best_clock->p;
797 }
798
799 if (WARN_ON_ONCE(!target_freq))
800 return false;
801
802 *error_ppm = div_u64(1000000ULL *
803 abs(target_freq - calculated_clock->dot),
804 target_freq);
805 /*
806 * Prefer a better P value over a better (smaller) error if the error
807 * is small. Ensure this preference for future configurations too by
808 * setting the error to 0.
809 */
810 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
811 *error_ppm = 0;
812
813 return true;
814 }
815
816 return *error_ppm + 10 < best_error_ppm;
817 }
818
819 /*
820 * Returns a set of divisors for the desired target clock with the given
821 * refclk, or FALSE. The returned values represent the clock equation:
822 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
823 */
824 static bool
825 vlv_find_best_dpll(const struct intel_limit *limit,
826 struct intel_crtc_state *crtc_state,
827 int target, int refclk, struct dpll *match_clock,
828 struct dpll *best_clock)
829 {
830 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
831 struct drm_device *dev = crtc->base.dev;
832 struct dpll clock;
833 unsigned int bestppm = 1000000;
834 /* min update 19.2 MHz */
835 int max_n = min(limit->n.max, refclk / 19200);
836 bool found = false;
837
838 target *= 5; /* fast clock */
839
840 memset(best_clock, 0, sizeof(*best_clock));
841
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
844 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
845 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
846 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
847 clock.p = clock.p1 * clock.p2;
848 /* based on hardware requirement, prefer bigger m1,m2 values */
849 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
850 unsigned int ppm;
851
852 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
853 refclk * clock.m1);
854
855 vlv_calc_dpll_params(refclk, &clock);
856
857 if (!intel_PLL_is_valid(to_i915(dev),
858 limit,
859 &clock))
860 continue;
861
862 if (!vlv_PLL_is_optimal(dev, target,
863 &clock,
864 best_clock,
865 bestppm, &ppm))
866 continue;
867
868 *best_clock = clock;
869 bestppm = ppm;
870 found = true;
871 }
872 }
873 }
874 }
875
876 return found;
877 }
878
879 /*
880 * Returns a set of divisors for the desired target clock with the given
881 * refclk, or FALSE. The returned values represent the clock equation:
882 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
883 */
884 static bool
885 chv_find_best_dpll(const struct intel_limit *limit,
886 struct intel_crtc_state *crtc_state,
887 int target, int refclk, struct dpll *match_clock,
888 struct dpll *best_clock)
889 {
890 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
891 struct drm_device *dev = crtc->base.dev;
892 unsigned int best_error_ppm;
893 struct dpll clock;
894 uint64_t m2;
895 int found = false;
896
897 memset(best_clock, 0, sizeof(*best_clock));
898 best_error_ppm = 1000000;
899
900 /*
901 * Based on hardware doc, the n always set to 1, and m1 always
902 * set to 2. If requires to support 200Mhz refclk, we need to
903 * revisit this because n may not 1 anymore.
904 */
905 clock.n = 1, clock.m1 = 2;
906 target *= 5; /* fast clock */
907
908 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
909 for (clock.p2 = limit->p2.p2_fast;
910 clock.p2 >= limit->p2.p2_slow;
911 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
912 unsigned int error_ppm;
913
914 clock.p = clock.p1 * clock.p2;
915
916 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
917 clock.n) << 22, refclk * clock.m1);
918
919 if (m2 > INT_MAX/clock.m1)
920 continue;
921
922 clock.m2 = m2;
923
924 chv_calc_dpll_params(refclk, &clock);
925
926 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
927 continue;
928
929 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
930 best_error_ppm, &error_ppm))
931 continue;
932
933 *best_clock = clock;
934 best_error_ppm = error_ppm;
935 found = true;
936 }
937 }
938
939 return found;
940 }
941
942 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
943 struct dpll *best_clock)
944 {
945 int refclk = 100000;
946 const struct intel_limit *limit = &intel_limits_bxt;
947
948 return chv_find_best_dpll(limit, crtc_state,
949 target_clock, refclk, NULL, best_clock);
950 }
951
952 bool intel_crtc_active(struct intel_crtc *crtc)
953 {
954 /* Be paranoid as we can arrive here with only partial
955 * state retrieved from the hardware during setup.
956 *
957 * We can ditch the adjusted_mode.crtc_clock check as soon
958 * as Haswell has gained clock readout/fastboot support.
959 *
960 * We can ditch the crtc->primary->fb check as soon as we can
961 * properly reconstruct framebuffers.
962 *
963 * FIXME: The intel_crtc->active here should be switched to
964 * crtc->state->active once we have proper CRTC states wired up
965 * for atomic.
966 */
967 return crtc->active && crtc->base.primary->state->fb &&
968 crtc->config->base.adjusted_mode.crtc_clock;
969 }
970
971 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
972 enum pipe pipe)
973 {
974 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
975
976 return crtc->config->cpu_transcoder;
977 }
978
979 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
980 {
981 i915_reg_t reg = PIPEDSL(pipe);
982 u32 line1, line2;
983 u32 line_mask;
984
985 if (IS_GEN2(dev_priv))
986 line_mask = DSL_LINEMASK_GEN2;
987 else
988 line_mask = DSL_LINEMASK_GEN3;
989
990 line1 = I915_READ(reg) & line_mask;
991 msleep(5);
992 line2 = I915_READ(reg) & line_mask;
993
994 return line1 == line2;
995 }
996
997 /*
998 * intel_wait_for_pipe_off - wait for pipe to turn off
999 * @crtc: crtc whose pipe to wait for
1000 *
1001 * After disabling a pipe, we can't wait for vblank in the usual way,
1002 * spinning on the vblank interrupt status bit, since we won't actually
1003 * see an interrupt when the pipe is disabled.
1004 *
1005 * On Gen4 and above:
1006 * wait for the pipe register state bit to turn off
1007 *
1008 * Otherwise:
1009 * wait for the display line value to settle (it usually
1010 * ends up stopping at the start of the next frame).
1011 *
1012 */
1013 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1014 {
1015 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1016 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1017 enum pipe pipe = crtc->pipe;
1018
1019 if (INTEL_GEN(dev_priv) >= 4) {
1020 i915_reg_t reg = PIPECONF(cpu_transcoder);
1021
1022 /* Wait for the Pipe State to go off */
1023 if (intel_wait_for_register(dev_priv,
1024 reg, I965_PIPECONF_ACTIVE, 0,
1025 100))
1026 WARN(1, "pipe_off wait timed out\n");
1027 } else {
1028 /* Wait for the display line to settle */
1029 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1030 WARN(1, "pipe_off wait timed out\n");
1031 }
1032 }
1033
1034 /* Only for pre-ILK configs */
1035 void assert_pll(struct drm_i915_private *dev_priv,
1036 enum pipe pipe, bool state)
1037 {
1038 u32 val;
1039 bool cur_state;
1040
1041 val = I915_READ(DPLL(pipe));
1042 cur_state = !!(val & DPLL_VCO_ENABLE);
1043 I915_STATE_WARN(cur_state != state,
1044 "PLL state assertion failure (expected %s, current %s)\n",
1045 onoff(state), onoff(cur_state));
1046 }
1047
1048 /* XXX: the dsi pll is shared between MIPI DSI ports */
1049 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1050 {
1051 u32 val;
1052 bool cur_state;
1053
1054 mutex_lock(&dev_priv->sb_lock);
1055 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1056 mutex_unlock(&dev_priv->sb_lock);
1057
1058 cur_state = val & DSI_PLL_VCO_EN;
1059 I915_STATE_WARN(cur_state != state,
1060 "DSI PLL state assertion failure (expected %s, current %s)\n",
1061 onoff(state), onoff(cur_state));
1062 }
1063
1064 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1065 enum pipe pipe, bool state)
1066 {
1067 bool cur_state;
1068 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1069 pipe);
1070
1071 if (HAS_DDI(dev_priv)) {
1072 /* DDI does not have a specific FDI_TX register */
1073 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1074 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1075 } else {
1076 u32 val = I915_READ(FDI_TX_CTL(pipe));
1077 cur_state = !!(val & FDI_TX_ENABLE);
1078 }
1079 I915_STATE_WARN(cur_state != state,
1080 "FDI TX state assertion failure (expected %s, current %s)\n",
1081 onoff(state), onoff(cur_state));
1082 }
1083 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1084 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1085
1086 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1087 enum pipe pipe, bool state)
1088 {
1089 u32 val;
1090 bool cur_state;
1091
1092 val = I915_READ(FDI_RX_CTL(pipe));
1093 cur_state = !!(val & FDI_RX_ENABLE);
1094 I915_STATE_WARN(cur_state != state,
1095 "FDI RX state assertion failure (expected %s, current %s)\n",
1096 onoff(state), onoff(cur_state));
1097 }
1098 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1099 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1100
1101 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1102 enum pipe pipe)
1103 {
1104 u32 val;
1105
1106 /* ILK FDI PLL is always enabled */
1107 if (IS_GEN5(dev_priv))
1108 return;
1109
1110 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1111 if (HAS_DDI(dev_priv))
1112 return;
1113
1114 val = I915_READ(FDI_TX_CTL(pipe));
1115 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1116 }
1117
1118 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1119 enum pipe pipe, bool state)
1120 {
1121 u32 val;
1122 bool cur_state;
1123
1124 val = I915_READ(FDI_RX_CTL(pipe));
1125 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1126 I915_STATE_WARN(cur_state != state,
1127 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1128 onoff(state), onoff(cur_state));
1129 }
1130
1131 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1132 {
1133 i915_reg_t pp_reg;
1134 u32 val;
1135 enum pipe panel_pipe = PIPE_A;
1136 bool locked = true;
1137
1138 if (WARN_ON(HAS_DDI(dev_priv)))
1139 return;
1140
1141 if (HAS_PCH_SPLIT(dev_priv)) {
1142 u32 port_sel;
1143
1144 pp_reg = PP_CONTROL(0);
1145 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1146
1147 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1148 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1149 panel_pipe = PIPE_B;
1150 /* XXX: else fix for eDP */
1151 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1152 /* presumably write lock depends on pipe, not port select */
1153 pp_reg = PP_CONTROL(pipe);
1154 panel_pipe = pipe;
1155 } else {
1156 pp_reg = PP_CONTROL(0);
1157 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1158 panel_pipe = PIPE_B;
1159 }
1160
1161 val = I915_READ(pp_reg);
1162 if (!(val & PANEL_POWER_ON) ||
1163 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1164 locked = false;
1165
1166 I915_STATE_WARN(panel_pipe == pipe && locked,
1167 "panel assertion failure, pipe %c regs locked\n",
1168 pipe_name(pipe));
1169 }
1170
1171 static void assert_cursor(struct drm_i915_private *dev_priv,
1172 enum pipe pipe, bool state)
1173 {
1174 bool cur_state;
1175
1176 if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1177 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1178 else
1179 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1180
1181 I915_STATE_WARN(cur_state != state,
1182 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1183 pipe_name(pipe), onoff(state), onoff(cur_state));
1184 }
1185 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1186 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1187
1188 void assert_pipe(struct drm_i915_private *dev_priv,
1189 enum pipe pipe, bool state)
1190 {
1191 bool cur_state;
1192 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1193 pipe);
1194 enum intel_display_power_domain power_domain;
1195
1196 /* we keep both pipes enabled on 830 */
1197 if (IS_I830(dev_priv))
1198 state = true;
1199
1200 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1201 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1202 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1203 cur_state = !!(val & PIPECONF_ENABLE);
1204
1205 intel_display_power_put(dev_priv, power_domain);
1206 } else {
1207 cur_state = false;
1208 }
1209
1210 I915_STATE_WARN(cur_state != state,
1211 "pipe %c assertion failure (expected %s, current %s)\n",
1212 pipe_name(pipe), onoff(state), onoff(cur_state));
1213 }
1214
1215 static void assert_plane(struct drm_i915_private *dev_priv,
1216 enum plane plane, bool state)
1217 {
1218 u32 val;
1219 bool cur_state;
1220
1221 val = I915_READ(DSPCNTR(plane));
1222 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1223 I915_STATE_WARN(cur_state != state,
1224 "plane %c assertion failure (expected %s, current %s)\n",
1225 plane_name(plane), onoff(state), onoff(cur_state));
1226 }
1227
1228 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1229 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1230
1231 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1232 enum pipe pipe)
1233 {
1234 int i;
1235
1236 /* Primary planes are fixed to pipes on gen4+ */
1237 if (INTEL_GEN(dev_priv) >= 4) {
1238 u32 val = I915_READ(DSPCNTR(pipe));
1239 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1240 "plane %c assertion failure, should be disabled but not\n",
1241 plane_name(pipe));
1242 return;
1243 }
1244
1245 /* Need to check both planes against the pipe */
1246 for_each_pipe(dev_priv, i) {
1247 u32 val = I915_READ(DSPCNTR(i));
1248 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1249 DISPPLANE_SEL_PIPE_SHIFT;
1250 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1251 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1252 plane_name(i), pipe_name(pipe));
1253 }
1254 }
1255
1256 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1257 enum pipe pipe)
1258 {
1259 int sprite;
1260
1261 if (INTEL_GEN(dev_priv) >= 9) {
1262 for_each_sprite(dev_priv, pipe, sprite) {
1263 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1264 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1265 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1266 sprite, pipe_name(pipe));
1267 }
1268 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1269 for_each_sprite(dev_priv, pipe, sprite) {
1270 u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1271 I915_STATE_WARN(val & SP_ENABLE,
1272 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1273 sprite_name(pipe, sprite), pipe_name(pipe));
1274 }
1275 } else if (INTEL_GEN(dev_priv) >= 7) {
1276 u32 val = I915_READ(SPRCTL(pipe));
1277 I915_STATE_WARN(val & SPRITE_ENABLE,
1278 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1279 plane_name(pipe), pipe_name(pipe));
1280 } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
1281 u32 val = I915_READ(DVSCNTR(pipe));
1282 I915_STATE_WARN(val & DVS_ENABLE,
1283 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1284 plane_name(pipe), pipe_name(pipe));
1285 }
1286 }
1287
1288 static void assert_vblank_disabled(struct drm_crtc *crtc)
1289 {
1290 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1291 drm_crtc_vblank_put(crtc);
1292 }
1293
1294 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1295 enum pipe pipe)
1296 {
1297 u32 val;
1298 bool enabled;
1299
1300 val = I915_READ(PCH_TRANSCONF(pipe));
1301 enabled = !!(val & TRANS_ENABLE);
1302 I915_STATE_WARN(enabled,
1303 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1304 pipe_name(pipe));
1305 }
1306
1307 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1308 enum pipe pipe, u32 port_sel, u32 val)
1309 {
1310 if ((val & DP_PORT_EN) == 0)
1311 return false;
1312
1313 if (HAS_PCH_CPT(dev_priv)) {
1314 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else if (IS_CHERRYVIEW(dev_priv)) {
1318 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1319 return false;
1320 } else {
1321 if ((val & DP_PIPE_MASK) != (pipe << 30))
1322 return false;
1323 }
1324 return true;
1325 }
1326
1327 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328 enum pipe pipe, u32 val)
1329 {
1330 if ((val & SDVO_ENABLE) == 0)
1331 return false;
1332
1333 if (HAS_PCH_CPT(dev_priv)) {
1334 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1335 return false;
1336 } else if (IS_CHERRYVIEW(dev_priv)) {
1337 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1338 return false;
1339 } else {
1340 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1341 return false;
1342 }
1343 return true;
1344 }
1345
1346 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1347 enum pipe pipe, u32 val)
1348 {
1349 if ((val & LVDS_PORT_EN) == 0)
1350 return false;
1351
1352 if (HAS_PCH_CPT(dev_priv)) {
1353 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1354 return false;
1355 } else {
1356 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1357 return false;
1358 }
1359 return true;
1360 }
1361
1362 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1363 enum pipe pipe, u32 val)
1364 {
1365 if ((val & ADPA_DAC_ENABLE) == 0)
1366 return false;
1367 if (HAS_PCH_CPT(dev_priv)) {
1368 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1369 return false;
1370 } else {
1371 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1372 return false;
1373 }
1374 return true;
1375 }
1376
1377 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1378 enum pipe pipe, i915_reg_t reg,
1379 u32 port_sel)
1380 {
1381 u32 val = I915_READ(reg);
1382 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1383 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1384 i915_mmio_reg_offset(reg), pipe_name(pipe));
1385
1386 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1387 && (val & DP_PIPEB_SELECT),
1388 "IBX PCH dp port still using transcoder B\n");
1389 }
1390
1391 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1392 enum pipe pipe, i915_reg_t reg)
1393 {
1394 u32 val = I915_READ(reg);
1395 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1396 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1397 i915_mmio_reg_offset(reg), pipe_name(pipe));
1398
1399 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1400 && (val & SDVO_PIPE_B_SELECT),
1401 "IBX PCH hdmi port still using transcoder B\n");
1402 }
1403
1404 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1405 enum pipe pipe)
1406 {
1407 u32 val;
1408
1409 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1410 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1411 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1412
1413 val = I915_READ(PCH_ADPA);
1414 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1415 "PCH VGA enabled on transcoder %c, should be disabled\n",
1416 pipe_name(pipe));
1417
1418 val = I915_READ(PCH_LVDS);
1419 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1420 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1421 pipe_name(pipe));
1422
1423 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1424 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1425 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1426 }
1427
1428 static void _vlv_enable_pll(struct intel_crtc *crtc,
1429 const struct intel_crtc_state *pipe_config)
1430 {
1431 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1432 enum pipe pipe = crtc->pipe;
1433
1434 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1435 POSTING_READ(DPLL(pipe));
1436 udelay(150);
1437
1438 if (intel_wait_for_register(dev_priv,
1439 DPLL(pipe),
1440 DPLL_LOCK_VLV,
1441 DPLL_LOCK_VLV,
1442 1))
1443 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1444 }
1445
1446 static void vlv_enable_pll(struct intel_crtc *crtc,
1447 const struct intel_crtc_state *pipe_config)
1448 {
1449 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1450 enum pipe pipe = crtc->pipe;
1451
1452 assert_pipe_disabled(dev_priv, pipe);
1453
1454 /* PLL is protected by panel, make sure we can write it */
1455 assert_panel_unlocked(dev_priv, pipe);
1456
1457 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1458 _vlv_enable_pll(crtc, pipe_config);
1459
1460 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1461 POSTING_READ(DPLL_MD(pipe));
1462 }
1463
1464
1465 static void _chv_enable_pll(struct intel_crtc *crtc,
1466 const struct intel_crtc_state *pipe_config)
1467 {
1468 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1469 enum pipe pipe = crtc->pipe;
1470 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1471 u32 tmp;
1472
1473 mutex_lock(&dev_priv->sb_lock);
1474
1475 /* Enable back the 10bit clock to display controller */
1476 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1477 tmp |= DPIO_DCLKP_EN;
1478 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1479
1480 mutex_unlock(&dev_priv->sb_lock);
1481
1482 /*
1483 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1484 */
1485 udelay(1);
1486
1487 /* Enable PLL */
1488 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1489
1490 /* Check PLL is locked */
1491 if (intel_wait_for_register(dev_priv,
1492 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1493 1))
1494 DRM_ERROR("PLL %d failed to lock\n", pipe);
1495 }
1496
1497 static void chv_enable_pll(struct intel_crtc *crtc,
1498 const struct intel_crtc_state *pipe_config)
1499 {
1500 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1501 enum pipe pipe = crtc->pipe;
1502
1503 assert_pipe_disabled(dev_priv, pipe);
1504
1505 /* PLL is protected by panel, make sure we can write it */
1506 assert_panel_unlocked(dev_priv, pipe);
1507
1508 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1509 _chv_enable_pll(crtc, pipe_config);
1510
1511 if (pipe != PIPE_A) {
1512 /*
1513 * WaPixelRepeatModeFixForC0:chv
1514 *
1515 * DPLLCMD is AWOL. Use chicken bits to propagate
1516 * the value from DPLLBMD to either pipe B or C.
1517 */
1518 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1519 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1520 I915_WRITE(CBR4_VLV, 0);
1521 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1522
1523 /*
1524 * DPLLB VGA mode also seems to cause problems.
1525 * We should always have it disabled.
1526 */
1527 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1528 } else {
1529 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1530 POSTING_READ(DPLL_MD(pipe));
1531 }
1532 }
1533
1534 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1535 {
1536 struct intel_crtc *crtc;
1537 int count = 0;
1538
1539 for_each_intel_crtc(&dev_priv->drm, crtc) {
1540 count += crtc->base.state->active &&
1541 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1542 }
1543
1544 return count;
1545 }
1546
1547 static void i9xx_enable_pll(struct intel_crtc *crtc)
1548 {
1549 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1550 i915_reg_t reg = DPLL(crtc->pipe);
1551 u32 dpll = crtc->config->dpll_hw_state.dpll;
1552 int i;
1553
1554 assert_pipe_disabled(dev_priv, crtc->pipe);
1555
1556 /* PLL is protected by panel, make sure we can write it */
1557 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1558 assert_panel_unlocked(dev_priv, crtc->pipe);
1559
1560 /* Enable DVO 2x clock on both PLLs if necessary */
1561 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1562 /*
1563 * It appears to be important that we don't enable this
1564 * for the current pipe before otherwise configuring the
1565 * PLL. No idea how this should be handled if multiple
1566 * DVO outputs are enabled simultaneosly.
1567 */
1568 dpll |= DPLL_DVO_2X_MODE;
1569 I915_WRITE(DPLL(!crtc->pipe),
1570 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1571 }
1572
1573 /*
1574 * Apparently we need to have VGA mode enabled prior to changing
1575 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1576 * dividers, even though the register value does change.
1577 */
1578 I915_WRITE(reg, 0);
1579
1580 I915_WRITE(reg, dpll);
1581
1582 /* Wait for the clocks to stabilize. */
1583 POSTING_READ(reg);
1584 udelay(150);
1585
1586 if (INTEL_GEN(dev_priv) >= 4) {
1587 I915_WRITE(DPLL_MD(crtc->pipe),
1588 crtc->config->dpll_hw_state.dpll_md);
1589 } else {
1590 /* The pixel multiplier can only be updated once the
1591 * DPLL is enabled and the clocks are stable.
1592 *
1593 * So write it again.
1594 */
1595 I915_WRITE(reg, dpll);
1596 }
1597
1598 /* We do this three times for luck */
1599 for (i = 0; i < 3; i++) {
1600 I915_WRITE(reg, dpll);
1601 POSTING_READ(reg);
1602 udelay(150); /* wait for warmup */
1603 }
1604 }
1605
1606 /**
1607 * i9xx_disable_pll - disable a PLL
1608 * @dev_priv: i915 private structure
1609 * @pipe: pipe PLL to disable
1610 *
1611 * Disable the PLL for @pipe, making sure the pipe is off first.
1612 *
1613 * Note! This is for pre-ILK only.
1614 */
1615 static void i9xx_disable_pll(struct intel_crtc *crtc)
1616 {
1617 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1618 enum pipe pipe = crtc->pipe;
1619
1620 /* Disable DVO 2x clock on both PLLs if necessary */
1621 if (IS_I830(dev_priv) &&
1622 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1623 !intel_num_dvo_pipes(dev_priv)) {
1624 I915_WRITE(DPLL(PIPE_B),
1625 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1626 I915_WRITE(DPLL(PIPE_A),
1627 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1628 }
1629
1630 /* Don't disable pipe or pipe PLLs if needed */
1631 if (IS_I830(dev_priv))
1632 return;
1633
1634 /* Make sure the pipe isn't still relying on us */
1635 assert_pipe_disabled(dev_priv, pipe);
1636
1637 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1638 POSTING_READ(DPLL(pipe));
1639 }
1640
1641 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1642 {
1643 u32 val;
1644
1645 /* Make sure the pipe isn't still relying on us */
1646 assert_pipe_disabled(dev_priv, pipe);
1647
1648 val = DPLL_INTEGRATED_REF_CLK_VLV |
1649 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1650 if (pipe != PIPE_A)
1651 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1652
1653 I915_WRITE(DPLL(pipe), val);
1654 POSTING_READ(DPLL(pipe));
1655 }
1656
1657 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1658 {
1659 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1660 u32 val;
1661
1662 /* Make sure the pipe isn't still relying on us */
1663 assert_pipe_disabled(dev_priv, pipe);
1664
1665 val = DPLL_SSC_REF_CLK_CHV |
1666 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1667 if (pipe != PIPE_A)
1668 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1669
1670 I915_WRITE(DPLL(pipe), val);
1671 POSTING_READ(DPLL(pipe));
1672
1673 mutex_lock(&dev_priv->sb_lock);
1674
1675 /* Disable 10bit clock to display controller */
1676 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1677 val &= ~DPIO_DCLKP_EN;
1678 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1679
1680 mutex_unlock(&dev_priv->sb_lock);
1681 }
1682
1683 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1684 struct intel_digital_port *dport,
1685 unsigned int expected_mask)
1686 {
1687 u32 port_mask;
1688 i915_reg_t dpll_reg;
1689
1690 switch (dport->port) {
1691 case PORT_B:
1692 port_mask = DPLL_PORTB_READY_MASK;
1693 dpll_reg = DPLL(0);
1694 break;
1695 case PORT_C:
1696 port_mask = DPLL_PORTC_READY_MASK;
1697 dpll_reg = DPLL(0);
1698 expected_mask <<= 4;
1699 break;
1700 case PORT_D:
1701 port_mask = DPLL_PORTD_READY_MASK;
1702 dpll_reg = DPIO_PHY_STATUS;
1703 break;
1704 default:
1705 BUG();
1706 }
1707
1708 if (intel_wait_for_register(dev_priv,
1709 dpll_reg, port_mask, expected_mask,
1710 1000))
1711 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1712 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1713 }
1714
1715 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1716 enum pipe pipe)
1717 {
1718 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1719 pipe);
1720 i915_reg_t reg;
1721 uint32_t val, pipeconf_val;
1722
1723 /* Make sure PCH DPLL is enabled */
1724 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1725
1726 /* FDI must be feeding us bits for PCH ports */
1727 assert_fdi_tx_enabled(dev_priv, pipe);
1728 assert_fdi_rx_enabled(dev_priv, pipe);
1729
1730 if (HAS_PCH_CPT(dev_priv)) {
1731 /* Workaround: Set the timing override bit before enabling the
1732 * pch transcoder. */
1733 reg = TRANS_CHICKEN2(pipe);
1734 val = I915_READ(reg);
1735 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1736 I915_WRITE(reg, val);
1737 }
1738
1739 reg = PCH_TRANSCONF(pipe);
1740 val = I915_READ(reg);
1741 pipeconf_val = I915_READ(PIPECONF(pipe));
1742
1743 if (HAS_PCH_IBX(dev_priv)) {
1744 /*
1745 * Make the BPC in transcoder be consistent with
1746 * that in pipeconf reg. For HDMI we must use 8bpc
1747 * here for both 8bpc and 12bpc.
1748 */
1749 val &= ~PIPECONF_BPC_MASK;
1750 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1751 val |= PIPECONF_8BPC;
1752 else
1753 val |= pipeconf_val & PIPECONF_BPC_MASK;
1754 }
1755
1756 val &= ~TRANS_INTERLACE_MASK;
1757 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1758 if (HAS_PCH_IBX(dev_priv) &&
1759 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1760 val |= TRANS_LEGACY_INTERLACED_ILK;
1761 else
1762 val |= TRANS_INTERLACED;
1763 else
1764 val |= TRANS_PROGRESSIVE;
1765
1766 I915_WRITE(reg, val | TRANS_ENABLE);
1767 if (intel_wait_for_register(dev_priv,
1768 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1769 100))
1770 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1771 }
1772
1773 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1774 enum transcoder cpu_transcoder)
1775 {
1776 u32 val, pipeconf_val;
1777
1778 /* FDI must be feeding us bits for PCH ports */
1779 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1780 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1781
1782 /* Workaround: set timing override bit. */
1783 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1784 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1785 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1786
1787 val = TRANS_ENABLE;
1788 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1789
1790 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1791 PIPECONF_INTERLACED_ILK)
1792 val |= TRANS_INTERLACED;
1793 else
1794 val |= TRANS_PROGRESSIVE;
1795
1796 I915_WRITE(LPT_TRANSCONF, val);
1797 if (intel_wait_for_register(dev_priv,
1798 LPT_TRANSCONF,
1799 TRANS_STATE_ENABLE,
1800 TRANS_STATE_ENABLE,
1801 100))
1802 DRM_ERROR("Failed to enable PCH transcoder\n");
1803 }
1804
1805 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1806 enum pipe pipe)
1807 {
1808 i915_reg_t reg;
1809 uint32_t val;
1810
1811 /* FDI relies on the transcoder */
1812 assert_fdi_tx_disabled(dev_priv, pipe);
1813 assert_fdi_rx_disabled(dev_priv, pipe);
1814
1815 /* Ports must be off as well */
1816 assert_pch_ports_disabled(dev_priv, pipe);
1817
1818 reg = PCH_TRANSCONF(pipe);
1819 val = I915_READ(reg);
1820 val &= ~TRANS_ENABLE;
1821 I915_WRITE(reg, val);
1822 /* wait for PCH transcoder off, transcoder state */
1823 if (intel_wait_for_register(dev_priv,
1824 reg, TRANS_STATE_ENABLE, 0,
1825 50))
1826 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1827
1828 if (HAS_PCH_CPT(dev_priv)) {
1829 /* Workaround: Clear the timing override chicken bit again. */
1830 reg = TRANS_CHICKEN2(pipe);
1831 val = I915_READ(reg);
1832 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1833 I915_WRITE(reg, val);
1834 }
1835 }
1836
1837 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1838 {
1839 u32 val;
1840
1841 val = I915_READ(LPT_TRANSCONF);
1842 val &= ~TRANS_ENABLE;
1843 I915_WRITE(LPT_TRANSCONF, val);
1844 /* wait for PCH transcoder off, transcoder state */
1845 if (intel_wait_for_register(dev_priv,
1846 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1847 50))
1848 DRM_ERROR("Failed to disable PCH transcoder\n");
1849
1850 /* Workaround: clear timing override bit. */
1851 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1852 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1853 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1854 }
1855
1856 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1857 {
1858 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1859
1860 WARN_ON(!crtc->config->has_pch_encoder);
1861
1862 if (HAS_PCH_LPT(dev_priv))
1863 return TRANSCODER_A;
1864 else
1865 return (enum transcoder) crtc->pipe;
1866 }
1867
1868 /**
1869 * intel_enable_pipe - enable a pipe, asserting requirements
1870 * @crtc: crtc responsible for the pipe
1871 *
1872 * Enable @crtc's pipe, making sure that various hardware specific requirements
1873 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1874 */
1875 static void intel_enable_pipe(struct intel_crtc *crtc)
1876 {
1877 struct drm_device *dev = crtc->base.dev;
1878 struct drm_i915_private *dev_priv = to_i915(dev);
1879 enum pipe pipe = crtc->pipe;
1880 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1881 i915_reg_t reg;
1882 u32 val;
1883
1884 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1885
1886 assert_planes_disabled(dev_priv, pipe);
1887 assert_cursor_disabled(dev_priv, pipe);
1888 assert_sprites_disabled(dev_priv, pipe);
1889
1890 /*
1891 * A pipe without a PLL won't actually be able to drive bits from
1892 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1893 * need the check.
1894 */
1895 if (HAS_GMCH_DISPLAY(dev_priv)) {
1896 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1897 assert_dsi_pll_enabled(dev_priv);
1898 else
1899 assert_pll_enabled(dev_priv, pipe);
1900 } else {
1901 if (crtc->config->has_pch_encoder) {
1902 /* if driving the PCH, we need FDI enabled */
1903 assert_fdi_rx_pll_enabled(dev_priv,
1904 (enum pipe) intel_crtc_pch_transcoder(crtc));
1905 assert_fdi_tx_pll_enabled(dev_priv,
1906 (enum pipe) cpu_transcoder);
1907 }
1908 /* FIXME: assert CPU port conditions for SNB+ */
1909 }
1910
1911 reg = PIPECONF(cpu_transcoder);
1912 val = I915_READ(reg);
1913 if (val & PIPECONF_ENABLE) {
1914 /* we keep both pipes enabled on 830 */
1915 WARN_ON(!IS_I830(dev_priv));
1916 return;
1917 }
1918
1919 I915_WRITE(reg, val | PIPECONF_ENABLE);
1920 POSTING_READ(reg);
1921
1922 /*
1923 * Until the pipe starts DSL will read as 0, which would cause
1924 * an apparent vblank timestamp jump, which messes up also the
1925 * frame count when it's derived from the timestamps. So let's
1926 * wait for the pipe to start properly before we call
1927 * drm_crtc_vblank_on()
1928 */
1929 if (dev->max_vblank_count == 0 &&
1930 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1931 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1932 }
1933
1934 /**
1935 * intel_disable_pipe - disable a pipe, asserting requirements
1936 * @crtc: crtc whose pipes is to be disabled
1937 *
1938 * Disable the pipe of @crtc, making sure that various hardware
1939 * specific requirements are met, if applicable, e.g. plane
1940 * disabled, panel fitter off, etc.
1941 *
1942 * Will wait until the pipe has shut down before returning.
1943 */
1944 static void intel_disable_pipe(struct intel_crtc *crtc)
1945 {
1946 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1947 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1948 enum pipe pipe = crtc->pipe;
1949 i915_reg_t reg;
1950 u32 val;
1951
1952 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1953
1954 /*
1955 * Make sure planes won't keep trying to pump pixels to us,
1956 * or we might hang the display.
1957 */
1958 assert_planes_disabled(dev_priv, pipe);
1959 assert_cursor_disabled(dev_priv, pipe);
1960 assert_sprites_disabled(dev_priv, pipe);
1961
1962 reg = PIPECONF(cpu_transcoder);
1963 val = I915_READ(reg);
1964 if ((val & PIPECONF_ENABLE) == 0)
1965 return;
1966
1967 /*
1968 * Double wide has implications for planes
1969 * so best keep it disabled when not needed.
1970 */
1971 if (crtc->config->double_wide)
1972 val &= ~PIPECONF_DOUBLE_WIDE;
1973
1974 /* Don't disable pipe or pipe PLLs if needed */
1975 if (!IS_I830(dev_priv))
1976 val &= ~PIPECONF_ENABLE;
1977
1978 I915_WRITE(reg, val);
1979 if ((val & PIPECONF_ENABLE) == 0)
1980 intel_wait_for_pipe_off(crtc);
1981 }
1982
1983 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1984 {
1985 return IS_GEN2(dev_priv) ? 2048 : 4096;
1986 }
1987
1988 static unsigned int
1989 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
1990 {
1991 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1992 unsigned int cpp = fb->format->cpp[plane];
1993
1994 switch (fb->modifier) {
1995 case DRM_FORMAT_MOD_LINEAR:
1996 return cpp;
1997 case I915_FORMAT_MOD_X_TILED:
1998 if (IS_GEN2(dev_priv))
1999 return 128;
2000 else
2001 return 512;
2002 case I915_FORMAT_MOD_Y_TILED:
2003 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2004 return 128;
2005 else
2006 return 512;
2007 case I915_FORMAT_MOD_Yf_TILED:
2008 switch (cpp) {
2009 case 1:
2010 return 64;
2011 case 2:
2012 case 4:
2013 return 128;
2014 case 8:
2015 case 16:
2016 return 256;
2017 default:
2018 MISSING_CASE(cpp);
2019 return cpp;
2020 }
2021 break;
2022 default:
2023 MISSING_CASE(fb->modifier);
2024 return cpp;
2025 }
2026 }
2027
2028 static unsigned int
2029 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2030 {
2031 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
2032 return 1;
2033 else
2034 return intel_tile_size(to_i915(fb->dev)) /
2035 intel_tile_width_bytes(fb, plane);
2036 }
2037
2038 /* Return the tile dimensions in pixel units */
2039 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2040 unsigned int *tile_width,
2041 unsigned int *tile_height)
2042 {
2043 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2044 unsigned int cpp = fb->format->cpp[plane];
2045
2046 *tile_width = tile_width_bytes / cpp;
2047 *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2048 }
2049
2050 unsigned int
2051 intel_fb_align_height(const struct drm_framebuffer *fb,
2052 int plane, unsigned int height)
2053 {
2054 unsigned int tile_height = intel_tile_height(fb, plane);
2055
2056 return ALIGN(height, tile_height);
2057 }
2058
2059 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2060 {
2061 unsigned int size = 0;
2062 int i;
2063
2064 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2065 size += rot_info->plane[i].width * rot_info->plane[i].height;
2066
2067 return size;
2068 }
2069
2070 static void
2071 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2072 const struct drm_framebuffer *fb,
2073 unsigned int rotation)
2074 {
2075 view->type = I915_GGTT_VIEW_NORMAL;
2076 if (drm_rotation_90_or_270(rotation)) {
2077 view->type = I915_GGTT_VIEW_ROTATED;
2078 view->rotated = to_intel_framebuffer(fb)->rot_info;
2079 }
2080 }
2081
2082 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2083 {
2084 if (IS_I830(dev_priv))
2085 return 16 * 1024;
2086 else if (IS_I85X(dev_priv))
2087 return 256;
2088 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2089 return 32;
2090 else
2091 return 4 * 1024;
2092 }
2093
2094 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2095 {
2096 if (INTEL_INFO(dev_priv)->gen >= 9)
2097 return 256 * 1024;
2098 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2099 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2100 return 128 * 1024;
2101 else if (INTEL_INFO(dev_priv)->gen >= 4)
2102 return 4 * 1024;
2103 else
2104 return 0;
2105 }
2106
2107 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2108 int plane)
2109 {
2110 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2111
2112 /* AUX_DIST needs only 4K alignment */
2113 if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
2114 return 4096;
2115
2116 switch (fb->modifier) {
2117 case DRM_FORMAT_MOD_LINEAR:
2118 return intel_linear_alignment(dev_priv);
2119 case I915_FORMAT_MOD_X_TILED:
2120 if (INTEL_GEN(dev_priv) >= 9)
2121 return 256 * 1024;
2122 return 0;
2123 case I915_FORMAT_MOD_Y_TILED:
2124 case I915_FORMAT_MOD_Yf_TILED:
2125 return 1 * 1024 * 1024;
2126 default:
2127 MISSING_CASE(fb->modifier);
2128 return 0;
2129 }
2130 }
2131
2132 struct i915_vma *
2133 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2134 {
2135 struct drm_device *dev = fb->dev;
2136 struct drm_i915_private *dev_priv = to_i915(dev);
2137 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2138 struct i915_ggtt_view view;
2139 struct i915_vma *vma;
2140 u32 alignment;
2141
2142 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2143
2144 alignment = intel_surf_alignment(fb, 0);
2145
2146 intel_fill_fb_ggtt_view(&view, fb, rotation);
2147
2148 /* Note that the w/a also requires 64 PTE of padding following the
2149 * bo. We currently fill all unused PTE with the shadow page and so
2150 * we should always have valid PTE following the scanout preventing
2151 * the VT-d warning.
2152 */
2153 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2154 alignment = 256 * 1024;
2155
2156 /*
2157 * Global gtt pte registers are special registers which actually forward
2158 * writes to a chunk of system memory. Which means that there is no risk
2159 * that the register values disappear as soon as we call
2160 * intel_runtime_pm_put(), so it is correct to wrap only the
2161 * pin/unpin/fence and not more.
2162 */
2163 intel_runtime_pm_get(dev_priv);
2164
2165 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2166 if (IS_ERR(vma))
2167 goto err;
2168
2169 if (i915_vma_is_map_and_fenceable(vma)) {
2170 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2171 * fence, whereas 965+ only requires a fence if using
2172 * framebuffer compression. For simplicity, we always, when
2173 * possible, install a fence as the cost is not that onerous.
2174 *
2175 * If we fail to fence the tiled scanout, then either the
2176 * modeset will reject the change (which is highly unlikely as
2177 * the affected systems, all but one, do not have unmappable
2178 * space) or we will not be able to enable full powersaving
2179 * techniques (also likely not to apply due to various limits
2180 * FBC and the like impose on the size of the buffer, which
2181 * presumably we violated anyway with this unmappable buffer).
2182 * Anyway, it is presumably better to stumble onwards with
2183 * something and try to run the system in a "less than optimal"
2184 * mode that matches the user configuration.
2185 */
2186 if (i915_vma_get_fence(vma) == 0)
2187 i915_vma_pin_fence(vma);
2188 }
2189
2190 i915_vma_get(vma);
2191 err:
2192 intel_runtime_pm_put(dev_priv);
2193 return vma;
2194 }
2195
2196 void intel_unpin_fb_vma(struct i915_vma *vma)
2197 {
2198 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2199
2200 i915_vma_unpin_fence(vma);
2201 i915_gem_object_unpin_from_display_plane(vma);
2202 i915_vma_put(vma);
2203 }
2204
2205 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2206 unsigned int rotation)
2207 {
2208 if (drm_rotation_90_or_270(rotation))
2209 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2210 else
2211 return fb->pitches[plane];
2212 }
2213
2214 /*
2215 * Convert the x/y offsets into a linear offset.
2216 * Only valid with 0/180 degree rotation, which is fine since linear
2217 * offset is only used with linear buffers on pre-hsw and tiled buffers
2218 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2219 */
2220 u32 intel_fb_xy_to_linear(int x, int y,
2221 const struct intel_plane_state *state,
2222 int plane)
2223 {
2224 const struct drm_framebuffer *fb = state->base.fb;
2225 unsigned int cpp = fb->format->cpp[plane];
2226 unsigned int pitch = fb->pitches[plane];
2227
2228 return y * pitch + x * cpp;
2229 }
2230
2231 /*
2232 * Add the x/y offsets derived from fb->offsets[] to the user
2233 * specified plane src x/y offsets. The resulting x/y offsets
2234 * specify the start of scanout from the beginning of the gtt mapping.
2235 */
2236 void intel_add_fb_offsets(int *x, int *y,
2237 const struct intel_plane_state *state,
2238 int plane)
2239
2240 {
2241 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2242 unsigned int rotation = state->base.rotation;
2243
2244 if (drm_rotation_90_or_270(rotation)) {
2245 *x += intel_fb->rotated[plane].x;
2246 *y += intel_fb->rotated[plane].y;
2247 } else {
2248 *x += intel_fb->normal[plane].x;
2249 *y += intel_fb->normal[plane].y;
2250 }
2251 }
2252
2253 /*
2254 * Input tile dimensions and pitch must already be
2255 * rotated to match x and y, and in pixel units.
2256 */
2257 static u32 _intel_adjust_tile_offset(int *x, int *y,
2258 unsigned int tile_width,
2259 unsigned int tile_height,
2260 unsigned int tile_size,
2261 unsigned int pitch_tiles,
2262 u32 old_offset,
2263 u32 new_offset)
2264 {
2265 unsigned int pitch_pixels = pitch_tiles * tile_width;
2266 unsigned int tiles;
2267
2268 WARN_ON(old_offset & (tile_size - 1));
2269 WARN_ON(new_offset & (tile_size - 1));
2270 WARN_ON(new_offset > old_offset);
2271
2272 tiles = (old_offset - new_offset) / tile_size;
2273
2274 *y += tiles / pitch_tiles * tile_height;
2275 *x += tiles % pitch_tiles * tile_width;
2276
2277 /* minimize x in case it got needlessly big */
2278 *y += *x / pitch_pixels * tile_height;
2279 *x %= pitch_pixels;
2280
2281 return new_offset;
2282 }
2283
2284 /*
2285 * Adjust the tile offset by moving the difference into
2286 * the x/y offsets.
2287 */
2288 static u32 intel_adjust_tile_offset(int *x, int *y,
2289 const struct intel_plane_state *state, int plane,
2290 u32 old_offset, u32 new_offset)
2291 {
2292 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2293 const struct drm_framebuffer *fb = state->base.fb;
2294 unsigned int cpp = fb->format->cpp[plane];
2295 unsigned int rotation = state->base.rotation;
2296 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2297
2298 WARN_ON(new_offset > old_offset);
2299
2300 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2301 unsigned int tile_size, tile_width, tile_height;
2302 unsigned int pitch_tiles;
2303
2304 tile_size = intel_tile_size(dev_priv);
2305 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2306
2307 if (drm_rotation_90_or_270(rotation)) {
2308 pitch_tiles = pitch / tile_height;
2309 swap(tile_width, tile_height);
2310 } else {
2311 pitch_tiles = pitch / (tile_width * cpp);
2312 }
2313
2314 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2315 tile_size, pitch_tiles,
2316 old_offset, new_offset);
2317 } else {
2318 old_offset += *y * pitch + *x * cpp;
2319
2320 *y = (old_offset - new_offset) / pitch;
2321 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2322 }
2323
2324 return new_offset;
2325 }
2326
2327 /*
2328 * Computes the linear offset to the base tile and adjusts
2329 * x, y. bytes per pixel is assumed to be a power-of-two.
2330 *
2331 * In the 90/270 rotated case, x and y are assumed
2332 * to be already rotated to match the rotated GTT view, and
2333 * pitch is the tile_height aligned framebuffer height.
2334 *
2335 * This function is used when computing the derived information
2336 * under intel_framebuffer, so using any of that information
2337 * here is not allowed. Anything under drm_framebuffer can be
2338 * used. This is why the user has to pass in the pitch since it
2339 * is specified in the rotated orientation.
2340 */
2341 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2342 int *x, int *y,
2343 const struct drm_framebuffer *fb, int plane,
2344 unsigned int pitch,
2345 unsigned int rotation,
2346 u32 alignment)
2347 {
2348 uint64_t fb_modifier = fb->modifier;
2349 unsigned int cpp = fb->format->cpp[plane];
2350 u32 offset, offset_aligned;
2351
2352 if (alignment)
2353 alignment--;
2354
2355 if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2356 unsigned int tile_size, tile_width, tile_height;
2357 unsigned int tile_rows, tiles, pitch_tiles;
2358
2359 tile_size = intel_tile_size(dev_priv);
2360 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2361
2362 if (drm_rotation_90_or_270(rotation)) {
2363 pitch_tiles = pitch / tile_height;
2364 swap(tile_width, tile_height);
2365 } else {
2366 pitch_tiles = pitch / (tile_width * cpp);
2367 }
2368
2369 tile_rows = *y / tile_height;
2370 *y %= tile_height;
2371
2372 tiles = *x / tile_width;
2373 *x %= tile_width;
2374
2375 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2376 offset_aligned = offset & ~alignment;
2377
2378 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2379 tile_size, pitch_tiles,
2380 offset, offset_aligned);
2381 } else {
2382 offset = *y * pitch + *x * cpp;
2383 offset_aligned = offset & ~alignment;
2384
2385 *y = (offset & alignment) / pitch;
2386 *x = ((offset & alignment) - *y * pitch) / cpp;
2387 }
2388
2389 return offset_aligned;
2390 }
2391
2392 u32 intel_compute_tile_offset(int *x, int *y,
2393 const struct intel_plane_state *state,
2394 int plane)
2395 {
2396 struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2397 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2398 const struct drm_framebuffer *fb = state->base.fb;
2399 unsigned int rotation = state->base.rotation;
2400 int pitch = intel_fb_pitch(fb, plane, rotation);
2401 u32 alignment;
2402
2403 if (intel_plane->id == PLANE_CURSOR)
2404 alignment = intel_cursor_alignment(dev_priv);
2405 else
2406 alignment = intel_surf_alignment(fb, plane);
2407
2408 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2409 rotation, alignment);
2410 }
2411
2412 /* Convert the fb->offset[] linear offset into x/y offsets */
2413 static void intel_fb_offset_to_xy(int *x, int *y,
2414 const struct drm_framebuffer *fb, int plane)
2415 {
2416 unsigned int cpp = fb->format->cpp[plane];
2417 unsigned int pitch = fb->pitches[plane];
2418 u32 linear_offset = fb->offsets[plane];
2419
2420 *y = linear_offset / pitch;
2421 *x = linear_offset % pitch / cpp;
2422 }
2423
2424 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2425 {
2426 switch (fb_modifier) {
2427 case I915_FORMAT_MOD_X_TILED:
2428 return I915_TILING_X;
2429 case I915_FORMAT_MOD_Y_TILED:
2430 return I915_TILING_Y;
2431 default:
2432 return I915_TILING_NONE;
2433 }
2434 }
2435
2436 static int
2437 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2438 struct drm_framebuffer *fb)
2439 {
2440 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2441 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2442 u32 gtt_offset_rotated = 0;
2443 unsigned int max_size = 0;
2444 int i, num_planes = fb->format->num_planes;
2445 unsigned int tile_size = intel_tile_size(dev_priv);
2446
2447 for (i = 0; i < num_planes; i++) {
2448 unsigned int width, height;
2449 unsigned int cpp, size;
2450 u32 offset;
2451 int x, y;
2452
2453 cpp = fb->format->cpp[i];
2454 width = drm_framebuffer_plane_width(fb->width, fb, i);
2455 height = drm_framebuffer_plane_height(fb->height, fb, i);
2456
2457 intel_fb_offset_to_xy(&x, &y, fb, i);
2458
2459 /*
2460 * The fence (if used) is aligned to the start of the object
2461 * so having the framebuffer wrap around across the edge of the
2462 * fenced region doesn't really work. We have no API to configure
2463 * the fence start offset within the object (nor could we probably
2464 * on gen2/3). So it's just easier if we just require that the
2465 * fb layout agrees with the fence layout. We already check that the
2466 * fb stride matches the fence stride elsewhere.
2467 */
2468 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2469 (x + width) * cpp > fb->pitches[i]) {
2470 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2471 i, fb->offsets[i]);
2472 return -EINVAL;
2473 }
2474
2475 /*
2476 * First pixel of the framebuffer from
2477 * the start of the normal gtt mapping.
2478 */
2479 intel_fb->normal[i].x = x;
2480 intel_fb->normal[i].y = y;
2481
2482 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2483 fb, i, fb->pitches[i],
2484 DRM_MODE_ROTATE_0, tile_size);
2485 offset /= tile_size;
2486
2487 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2488 unsigned int tile_width, tile_height;
2489 unsigned int pitch_tiles;
2490 struct drm_rect r;
2491
2492 intel_tile_dims(fb, i, &tile_width, &tile_height);
2493
2494 rot_info->plane[i].offset = offset;
2495 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2496 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2497 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2498
2499 intel_fb->rotated[i].pitch =
2500 rot_info->plane[i].height * tile_height;
2501
2502 /* how many tiles does this plane need */
2503 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2504 /*
2505 * If the plane isn't horizontally tile aligned,
2506 * we need one more tile.
2507 */
2508 if (x != 0)
2509 size++;
2510
2511 /* rotate the x/y offsets to match the GTT view */
2512 r.x1 = x;
2513 r.y1 = y;
2514 r.x2 = x + width;
2515 r.y2 = y + height;
2516 drm_rect_rotate(&r,
2517 rot_info->plane[i].width * tile_width,
2518 rot_info->plane[i].height * tile_height,
2519 DRM_MODE_ROTATE_270);
2520 x = r.x1;
2521 y = r.y1;
2522
2523 /* rotate the tile dimensions to match the GTT view */
2524 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2525 swap(tile_width, tile_height);
2526
2527 /*
2528 * We only keep the x/y offsets, so push all of the
2529 * gtt offset into the x/y offsets.
2530 */
2531 _intel_adjust_tile_offset(&x, &y,
2532 tile_width, tile_height,
2533 tile_size, pitch_tiles,
2534 gtt_offset_rotated * tile_size, 0);
2535
2536 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2537
2538 /*
2539 * First pixel of the framebuffer from
2540 * the start of the rotated gtt mapping.
2541 */
2542 intel_fb->rotated[i].x = x;
2543 intel_fb->rotated[i].y = y;
2544 } else {
2545 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2546 x * cpp, tile_size);
2547 }
2548
2549 /* how many tiles in total needed in the bo */
2550 max_size = max(max_size, offset + size);
2551 }
2552
2553 if (max_size * tile_size > intel_fb->obj->base.size) {
2554 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2555 max_size * tile_size, intel_fb->obj->base.size);
2556 return -EINVAL;
2557 }
2558
2559 return 0;
2560 }
2561
2562 static int i9xx_format_to_fourcc(int format)
2563 {
2564 switch (format) {
2565 case DISPPLANE_8BPP:
2566 return DRM_FORMAT_C8;
2567 case DISPPLANE_BGRX555:
2568 return DRM_FORMAT_XRGB1555;
2569 case DISPPLANE_BGRX565:
2570 return DRM_FORMAT_RGB565;
2571 default:
2572 case DISPPLANE_BGRX888:
2573 return DRM_FORMAT_XRGB8888;
2574 case DISPPLANE_RGBX888:
2575 return DRM_FORMAT_XBGR8888;
2576 case DISPPLANE_BGRX101010:
2577 return DRM_FORMAT_XRGB2101010;
2578 case DISPPLANE_RGBX101010:
2579 return DRM_FORMAT_XBGR2101010;
2580 }
2581 }
2582
2583 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2584 {
2585 switch (format) {
2586 case PLANE_CTL_FORMAT_RGB_565:
2587 return DRM_FORMAT_RGB565;
2588 default:
2589 case PLANE_CTL_FORMAT_XRGB_8888:
2590 if (rgb_order) {
2591 if (alpha)
2592 return DRM_FORMAT_ABGR8888;
2593 else
2594 return DRM_FORMAT_XBGR8888;
2595 } else {
2596 if (alpha)
2597 return DRM_FORMAT_ARGB8888;
2598 else
2599 return DRM_FORMAT_XRGB8888;
2600 }
2601 case PLANE_CTL_FORMAT_XRGB_2101010:
2602 if (rgb_order)
2603 return DRM_FORMAT_XBGR2101010;
2604 else
2605 return DRM_FORMAT_XRGB2101010;
2606 }
2607 }
2608
2609 static bool
2610 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2611 struct intel_initial_plane_config *plane_config)
2612 {
2613 struct drm_device *dev = crtc->base.dev;
2614 struct drm_i915_private *dev_priv = to_i915(dev);
2615 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2616 struct drm_i915_gem_object *obj = NULL;
2617 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2618 struct drm_framebuffer *fb = &plane_config->fb->base;
2619 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2620 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2621 PAGE_SIZE);
2622
2623 size_aligned -= base_aligned;
2624
2625 if (plane_config->size == 0)
2626 return false;
2627
2628 /* If the FB is too big, just don't use it since fbdev is not very
2629 * important and we should probably use that space with FBC or other
2630 * features. */
2631 if (size_aligned * 2 > ggtt->stolen_usable_size)
2632 return false;
2633
2634 mutex_lock(&dev->struct_mutex);
2635 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2636 base_aligned,
2637 base_aligned,
2638 size_aligned);
2639 mutex_unlock(&dev->struct_mutex);
2640 if (!obj)
2641 return false;
2642
2643 if (plane_config->tiling == I915_TILING_X)
2644 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2645
2646 mode_cmd.pixel_format = fb->format->format;
2647 mode_cmd.width = fb->width;
2648 mode_cmd.height = fb->height;
2649 mode_cmd.pitches[0] = fb->pitches[0];
2650 mode_cmd.modifier[0] = fb->modifier;
2651 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2652
2653 if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2654 DRM_DEBUG_KMS("intel fb init failed\n");
2655 goto out_unref_obj;
2656 }
2657
2658
2659 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2660 return true;
2661
2662 out_unref_obj:
2663 i915_gem_object_put(obj);
2664 return false;
2665 }
2666
2667 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2668 static void
2669 update_state_fb(struct drm_plane *plane)
2670 {
2671 if (plane->fb == plane->state->fb)
2672 return;
2673
2674 if (plane->state->fb)
2675 drm_framebuffer_unreference(plane->state->fb);
2676 plane->state->fb = plane->fb;
2677 if (plane->state->fb)
2678 drm_framebuffer_reference(plane->state->fb);
2679 }
2680
2681 static void
2682 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2683 struct intel_plane_state *plane_state,
2684 bool visible)
2685 {
2686 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2687
2688 plane_state->base.visible = visible;
2689
2690 /* FIXME pre-g4x don't work like this */
2691 if (visible) {
2692 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2693 crtc_state->active_planes |= BIT(plane->id);
2694 } else {
2695 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2696 crtc_state->active_planes &= ~BIT(plane->id);
2697 }
2698
2699 DRM_DEBUG_KMS("%s active planes 0x%x\n",
2700 crtc_state->base.crtc->name,
2701 crtc_state->active_planes);
2702 }
2703
2704 static void
2705 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2706 struct intel_initial_plane_config *plane_config)
2707 {
2708 struct drm_device *dev = intel_crtc->base.dev;
2709 struct drm_i915_private *dev_priv = to_i915(dev);
2710 struct drm_crtc *c;
2711 struct drm_i915_gem_object *obj;
2712 struct drm_plane *primary = intel_crtc->base.primary;
2713 struct drm_plane_state *plane_state = primary->state;
2714 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2715 struct intel_plane *intel_plane = to_intel_plane(primary);
2716 struct intel_plane_state *intel_state =
2717 to_intel_plane_state(plane_state);
2718 struct drm_framebuffer *fb;
2719
2720 if (!plane_config->fb)
2721 return;
2722
2723 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2724 fb = &plane_config->fb->base;
2725 goto valid_fb;
2726 }
2727
2728 kfree(plane_config->fb);
2729
2730 /*
2731 * Failed to alloc the obj, check to see if we should share
2732 * an fb with another CRTC instead
2733 */
2734 for_each_crtc(dev, c) {
2735 struct intel_plane_state *state;
2736
2737 if (c == &intel_crtc->base)
2738 continue;
2739
2740 if (!to_intel_crtc(c)->active)
2741 continue;
2742
2743 state = to_intel_plane_state(c->primary->state);
2744 if (!state->vma)
2745 continue;
2746
2747 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2748 fb = c->primary->fb;
2749 drm_framebuffer_reference(fb);
2750 goto valid_fb;
2751 }
2752 }
2753
2754 /*
2755 * We've failed to reconstruct the BIOS FB. Current display state
2756 * indicates that the primary plane is visible, but has a NULL FB,
2757 * which will lead to problems later if we don't fix it up. The
2758 * simplest solution is to just disable the primary plane now and
2759 * pretend the BIOS never had it enabled.
2760 */
2761 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2762 to_intel_plane_state(plane_state),
2763 false);
2764 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2765 trace_intel_disable_plane(primary, intel_crtc);
2766 intel_plane->disable_plane(intel_plane, intel_crtc);
2767
2768 return;
2769
2770 valid_fb:
2771 mutex_lock(&dev->struct_mutex);
2772 intel_state->vma =
2773 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2774 mutex_unlock(&dev->struct_mutex);
2775 if (IS_ERR(intel_state->vma)) {
2776 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2777 intel_crtc->pipe, PTR_ERR(intel_state->vma));
2778
2779 intel_state->vma = NULL;
2780 drm_framebuffer_unreference(fb);
2781 return;
2782 }
2783
2784 plane_state->src_x = 0;
2785 plane_state->src_y = 0;
2786 plane_state->src_w = fb->width << 16;
2787 plane_state->src_h = fb->height << 16;
2788
2789 plane_state->crtc_x = 0;
2790 plane_state->crtc_y = 0;
2791 plane_state->crtc_w = fb->width;
2792 plane_state->crtc_h = fb->height;
2793
2794 intel_state->base.src = drm_plane_state_src(plane_state);
2795 intel_state->base.dst = drm_plane_state_dest(plane_state);
2796
2797 obj = intel_fb_obj(fb);
2798 if (i915_gem_object_is_tiled(obj))
2799 dev_priv->preserve_bios_swizzle = true;
2800
2801 drm_framebuffer_reference(fb);
2802 primary->fb = primary->state->fb = fb;
2803 primary->crtc = primary->state->crtc = &intel_crtc->base;
2804
2805 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2806 to_intel_plane_state(plane_state),
2807 true);
2808
2809 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2810 &obj->frontbuffer_bits);
2811 }
2812
2813 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2814 unsigned int rotation)
2815 {
2816 int cpp = fb->format->cpp[plane];
2817
2818 switch (fb->modifier) {
2819 case DRM_FORMAT_MOD_LINEAR:
2820 case I915_FORMAT_MOD_X_TILED:
2821 switch (cpp) {
2822 case 8:
2823 return 4096;
2824 case 4:
2825 case 2:
2826 case 1:
2827 return 8192;
2828 default:
2829 MISSING_CASE(cpp);
2830 break;
2831 }
2832 break;
2833 case I915_FORMAT_MOD_Y_TILED:
2834 case I915_FORMAT_MOD_Yf_TILED:
2835 switch (cpp) {
2836 case 8:
2837 return 2048;
2838 case 4:
2839 return 4096;
2840 case 2:
2841 case 1:
2842 return 8192;
2843 default:
2844 MISSING_CASE(cpp);
2845 break;
2846 }
2847 break;
2848 default:
2849 MISSING_CASE(fb->modifier);
2850 }
2851
2852 return 2048;
2853 }
2854
2855 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2856 {
2857 const struct drm_framebuffer *fb = plane_state->base.fb;
2858 unsigned int rotation = plane_state->base.rotation;
2859 int x = plane_state->base.src.x1 >> 16;
2860 int y = plane_state->base.src.y1 >> 16;
2861 int w = drm_rect_width(&plane_state->base.src) >> 16;
2862 int h = drm_rect_height(&plane_state->base.src) >> 16;
2863 int max_width = skl_max_plane_width(fb, 0, rotation);
2864 int max_height = 4096;
2865 u32 alignment, offset, aux_offset = plane_state->aux.offset;
2866
2867 if (w > max_width || h > max_height) {
2868 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2869 w, h, max_width, max_height);
2870 return -EINVAL;
2871 }
2872
2873 intel_add_fb_offsets(&x, &y, plane_state, 0);
2874 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2875 alignment = intel_surf_alignment(fb, 0);
2876
2877 /*
2878 * AUX surface offset is specified as the distance from the
2879 * main surface offset, and it must be non-negative. Make
2880 * sure that is what we will get.
2881 */
2882 if (offset > aux_offset)
2883 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2884 offset, aux_offset & ~(alignment - 1));
2885
2886 /*
2887 * When using an X-tiled surface, the plane blows up
2888 * if the x offset + width exceed the stride.
2889 *
2890 * TODO: linear and Y-tiled seem fine, Yf untested,
2891 */
2892 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2893 int cpp = fb->format->cpp[0];
2894
2895 while ((x + w) * cpp > fb->pitches[0]) {
2896 if (offset == 0) {
2897 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2898 return -EINVAL;
2899 }
2900
2901 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2902 offset, offset - alignment);
2903 }
2904 }
2905
2906 plane_state->main.offset = offset;
2907 plane_state->main.x = x;
2908 plane_state->main.y = y;
2909
2910 return 0;
2911 }
2912
2913 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2914 {
2915 const struct drm_framebuffer *fb = plane_state->base.fb;
2916 unsigned int rotation = plane_state->base.rotation;
2917 int max_width = skl_max_plane_width(fb, 1, rotation);
2918 int max_height = 4096;
2919 int x = plane_state->base.src.x1 >> 17;
2920 int y = plane_state->base.src.y1 >> 17;
2921 int w = drm_rect_width(&plane_state->base.src) >> 17;
2922 int h = drm_rect_height(&plane_state->base.src) >> 17;
2923 u32 offset;
2924
2925 intel_add_fb_offsets(&x, &y, plane_state, 1);
2926 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2927
2928 /* FIXME not quite sure how/if these apply to the chroma plane */
2929 if (w > max_width || h > max_height) {
2930 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2931 w, h, max_width, max_height);
2932 return -EINVAL;
2933 }
2934
2935 plane_state->aux.offset = offset;
2936 plane_state->aux.x = x;
2937 plane_state->aux.y = y;
2938
2939 return 0;
2940 }
2941
2942 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2943 {
2944 const struct drm_framebuffer *fb = plane_state->base.fb;
2945 unsigned int rotation = plane_state->base.rotation;
2946 int ret;
2947
2948 if (!plane_state->base.visible)
2949 return 0;
2950
2951 /* Rotate src coordinates to match rotated GTT view */
2952 if (drm_rotation_90_or_270(rotation))
2953 drm_rect_rotate(&plane_state->base.src,
2954 fb->width << 16, fb->height << 16,
2955 DRM_MODE_ROTATE_270);
2956
2957 /*
2958 * Handle the AUX surface first since
2959 * the main surface setup depends on it.
2960 */
2961 if (fb->format->format == DRM_FORMAT_NV12) {
2962 ret = skl_check_nv12_aux_surface(plane_state);
2963 if (ret)
2964 return ret;
2965 } else {
2966 plane_state->aux.offset = ~0xfff;
2967 plane_state->aux.x = 0;
2968 plane_state->aux.y = 0;
2969 }
2970
2971 ret = skl_check_main_surface(plane_state);
2972 if (ret)
2973 return ret;
2974
2975 return 0;
2976 }
2977
2978 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
2979 const struct intel_plane_state *plane_state)
2980 {
2981 struct drm_i915_private *dev_priv =
2982 to_i915(plane_state->base.plane->dev);
2983 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2984 const struct drm_framebuffer *fb = plane_state->base.fb;
2985 unsigned int rotation = plane_state->base.rotation;
2986 u32 dspcntr;
2987
2988 dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
2989
2990 if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
2991 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
2992 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2993
2994 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2995 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2996
2997 if (INTEL_GEN(dev_priv) < 4)
2998 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
2999
3000 switch (fb->format->format) {
3001 case DRM_FORMAT_C8:
3002 dspcntr |= DISPPLANE_8BPP;
3003 break;
3004 case DRM_FORMAT_XRGB1555:
3005 dspcntr |= DISPPLANE_BGRX555;
3006 break;
3007 case DRM_FORMAT_RGB565:
3008 dspcntr |= DISPPLANE_BGRX565;
3009 break;
3010 case DRM_FORMAT_XRGB8888:
3011 dspcntr |= DISPPLANE_BGRX888;
3012 break;
3013 case DRM_FORMAT_XBGR8888:
3014 dspcntr |= DISPPLANE_RGBX888;
3015 break;
3016 case DRM_FORMAT_XRGB2101010:
3017 dspcntr |= DISPPLANE_BGRX101010;
3018 break;
3019 case DRM_FORMAT_XBGR2101010:
3020 dspcntr |= DISPPLANE_RGBX101010;
3021 break;
3022 default:
3023 MISSING_CASE(fb->format->format);
3024 return 0;
3025 }
3026
3027 if (INTEL_GEN(dev_priv) >= 4 &&
3028 fb->modifier == I915_FORMAT_MOD_X_TILED)
3029 dspcntr |= DISPPLANE_TILED;
3030
3031 if (rotation & DRM_MODE_ROTATE_180)
3032 dspcntr |= DISPPLANE_ROTATE_180;
3033
3034 if (rotation & DRM_MODE_REFLECT_X)
3035 dspcntr |= DISPPLANE_MIRROR;
3036
3037 return dspcntr;
3038 }
3039
3040 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3041 {
3042 struct drm_i915_private *dev_priv =
3043 to_i915(plane_state->base.plane->dev);
3044 int src_x = plane_state->base.src.x1 >> 16;
3045 int src_y = plane_state->base.src.y1 >> 16;
3046 u32 offset;
3047
3048 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3049
3050 if (INTEL_GEN(dev_priv) >= 4)
3051 offset = intel_compute_tile_offset(&src_x, &src_y,
3052 plane_state, 0);
3053 else
3054 offset = 0;
3055
3056 /* HSW/BDW do this automagically in hardware */
3057 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3058 unsigned int rotation = plane_state->base.rotation;
3059 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3060 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3061
3062 if (rotation & DRM_MODE_ROTATE_180) {
3063 src_x += src_w - 1;
3064 src_y += src_h - 1;
3065 } else if (rotation & DRM_MODE_REFLECT_X) {
3066 src_x += src_w - 1;
3067 }
3068 }
3069
3070 plane_state->main.offset = offset;
3071 plane_state->main.x = src_x;
3072 plane_state->main.y = src_y;
3073
3074 return 0;
3075 }
3076
3077 static void i9xx_update_primary_plane(struct intel_plane *primary,
3078 const struct intel_crtc_state *crtc_state,
3079 const struct intel_plane_state *plane_state)
3080 {
3081 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3082 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3083 const struct drm_framebuffer *fb = plane_state->base.fb;
3084 enum plane plane = primary->plane;
3085 u32 linear_offset;
3086 u32 dspcntr = plane_state->ctl;
3087 i915_reg_t reg = DSPCNTR(plane);
3088 int x = plane_state->main.x;
3089 int y = plane_state->main.y;
3090 unsigned long irqflags;
3091
3092 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3093
3094 if (INTEL_GEN(dev_priv) >= 4)
3095 crtc->dspaddr_offset = plane_state->main.offset;
3096 else
3097 crtc->dspaddr_offset = linear_offset;
3098
3099 crtc->adjusted_x = x;
3100 crtc->adjusted_y = y;
3101
3102 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3103
3104 if (INTEL_GEN(dev_priv) < 4) {
3105 /* pipesrc and dspsize control the size that is scaled from,
3106 * which should always be the user's requested size.
3107 */
3108 I915_WRITE_FW(DSPSIZE(plane),
3109 ((crtc_state->pipe_src_h - 1) << 16) |
3110 (crtc_state->pipe_src_w - 1));
3111 I915_WRITE_FW(DSPPOS(plane), 0);
3112 } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3113 I915_WRITE_FW(PRIMSIZE(plane),
3114 ((crtc_state->pipe_src_h - 1) << 16) |
3115 (crtc_state->pipe_src_w - 1));
3116 I915_WRITE_FW(PRIMPOS(plane), 0);
3117 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3118 }
3119
3120 I915_WRITE_FW(reg, dspcntr);
3121
3122 I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3123 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3124 I915_WRITE_FW(DSPSURF(plane),
3125 intel_plane_ggtt_offset(plane_state) +
3126 crtc->dspaddr_offset);
3127 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3128 } else if (INTEL_GEN(dev_priv) >= 4) {
3129 I915_WRITE_FW(DSPSURF(plane),
3130 intel_plane_ggtt_offset(plane_state) +
3131 crtc->dspaddr_offset);
3132 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3133 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3134 } else {
3135 I915_WRITE_FW(DSPADDR(plane),
3136 intel_plane_ggtt_offset(plane_state) +
3137 crtc->dspaddr_offset);
3138 }
3139 POSTING_READ_FW(reg);
3140
3141 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3142 }
3143
3144 static void i9xx_disable_primary_plane(struct intel_plane *primary,
3145 struct intel_crtc *crtc)
3146 {
3147 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3148 enum plane plane = primary->plane;
3149 unsigned long irqflags;
3150
3151 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3152
3153 I915_WRITE_FW(DSPCNTR(plane), 0);
3154 if (INTEL_INFO(dev_priv)->gen >= 4)
3155 I915_WRITE_FW(DSPSURF(plane), 0);
3156 else
3157 I915_WRITE_FW(DSPADDR(plane), 0);
3158 POSTING_READ_FW(DSPCNTR(plane));
3159
3160 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3161 }
3162
3163 static u32
3164 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3165 {
3166 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3167 return 64;
3168 else
3169 return intel_tile_width_bytes(fb, plane);
3170 }
3171
3172 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3173 {
3174 struct drm_device *dev = intel_crtc->base.dev;
3175 struct drm_i915_private *dev_priv = to_i915(dev);
3176
3177 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3178 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3179 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3180 }
3181
3182 /*
3183 * This function detaches (aka. unbinds) unused scalers in hardware
3184 */
3185 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3186 {
3187 struct intel_crtc_scaler_state *scaler_state;
3188 int i;
3189
3190 scaler_state = &intel_crtc->config->scaler_state;
3191
3192 /* loop through and disable scalers that aren't in use */
3193 for (i = 0; i < intel_crtc->num_scalers; i++) {
3194 if (!scaler_state->scalers[i].in_use)
3195 skl_detach_scaler(intel_crtc, i);
3196 }
3197 }
3198
3199 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3200 unsigned int rotation)
3201 {
3202 u32 stride;
3203
3204 if (plane >= fb->format->num_planes)
3205 return 0;
3206
3207 stride = intel_fb_pitch(fb, plane, rotation);
3208
3209 /*
3210 * The stride is either expressed as a multiple of 64 bytes chunks for
3211 * linear buffers or in number of tiles for tiled buffers.
3212 */
3213 if (drm_rotation_90_or_270(rotation))
3214 stride /= intel_tile_height(fb, plane);
3215 else
3216 stride /= intel_fb_stride_alignment(fb, plane);
3217
3218 return stride;
3219 }
3220
3221 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3222 {
3223 switch (pixel_format) {
3224 case DRM_FORMAT_C8:
3225 return PLANE_CTL_FORMAT_INDEXED;
3226 case DRM_FORMAT_RGB565:
3227 return PLANE_CTL_FORMAT_RGB_565;
3228 case DRM_FORMAT_XBGR8888:
3229 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3230 case DRM_FORMAT_XRGB8888:
3231 return PLANE_CTL_FORMAT_XRGB_8888;
3232 /*
3233 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3234 * to be already pre-multiplied. We need to add a knob (or a different
3235 * DRM_FORMAT) for user-space to configure that.
3236 */
3237 case DRM_FORMAT_ABGR8888:
3238 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3239 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3240 case DRM_FORMAT_ARGB8888:
3241 return PLANE_CTL_FORMAT_XRGB_8888 |
3242 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3243 case DRM_FORMAT_XRGB2101010:
3244 return PLANE_CTL_FORMAT_XRGB_2101010;
3245 case DRM_FORMAT_XBGR2101010:
3246 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3247 case DRM_FORMAT_YUYV:
3248 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3249 case DRM_FORMAT_YVYU:
3250 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3251 case DRM_FORMAT_UYVY:
3252 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3253 case DRM_FORMAT_VYUY:
3254 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3255 default:
3256 MISSING_CASE(pixel_format);
3257 }
3258
3259 return 0;
3260 }
3261
3262 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3263 {
3264 switch (fb_modifier) {
3265 case DRM_FORMAT_MOD_LINEAR:
3266 break;
3267 case I915_FORMAT_MOD_X_TILED:
3268 return PLANE_CTL_TILED_X;
3269 case I915_FORMAT_MOD_Y_TILED:
3270 return PLANE_CTL_TILED_Y;
3271 case I915_FORMAT_MOD_Yf_TILED:
3272 return PLANE_CTL_TILED_YF;
3273 default:
3274 MISSING_CASE(fb_modifier);
3275 }
3276
3277 return 0;
3278 }
3279
3280 static u32 skl_plane_ctl_rotation(unsigned int rotation)
3281 {
3282 switch (rotation) {
3283 case DRM_MODE_ROTATE_0:
3284 break;
3285 /*
3286 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3287 * while i915 HW rotation is clockwise, thats why this swapping.
3288 */
3289 case DRM_MODE_ROTATE_90:
3290 return PLANE_CTL_ROTATE_270;
3291 case DRM_MODE_ROTATE_180:
3292 return PLANE_CTL_ROTATE_180;
3293 case DRM_MODE_ROTATE_270:
3294 return PLANE_CTL_ROTATE_90;
3295 default:
3296 MISSING_CASE(rotation);
3297 }
3298
3299 return 0;
3300 }
3301
3302 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3303 const struct intel_plane_state *plane_state)
3304 {
3305 struct drm_i915_private *dev_priv =
3306 to_i915(plane_state->base.plane->dev);
3307 const struct drm_framebuffer *fb = plane_state->base.fb;
3308 unsigned int rotation = plane_state->base.rotation;
3309 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3310 u32 plane_ctl;
3311
3312 plane_ctl = PLANE_CTL_ENABLE;
3313
3314 if (!IS_GEMINILAKE(dev_priv)) {
3315 plane_ctl |=
3316 PLANE_CTL_PIPE_GAMMA_ENABLE |
3317 PLANE_CTL_PIPE_CSC_ENABLE |
3318 PLANE_CTL_PLANE_GAMMA_DISABLE;
3319 }
3320
3321 plane_ctl |= skl_plane_ctl_format(fb->format->format);
3322 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3323 plane_ctl |= skl_plane_ctl_rotation(rotation);
3324
3325 if (key->flags & I915_SET_COLORKEY_DESTINATION)
3326 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3327 else if (key->flags & I915_SET_COLORKEY_SOURCE)
3328 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3329
3330 return plane_ctl;
3331 }
3332
3333 static void skylake_update_primary_plane(struct intel_plane *plane,
3334 const struct intel_crtc_state *crtc_state,
3335 const struct intel_plane_state *plane_state)
3336 {
3337 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3338 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3339 const struct drm_framebuffer *fb = plane_state->base.fb;
3340 enum plane_id plane_id = plane->id;
3341 enum pipe pipe = plane->pipe;
3342 u32 plane_ctl = plane_state->ctl;
3343 unsigned int rotation = plane_state->base.rotation;
3344 u32 stride = skl_plane_stride(fb, 0, rotation);
3345 u32 surf_addr = plane_state->main.offset;
3346 int scaler_id = plane_state->scaler_id;
3347 int src_x = plane_state->main.x;
3348 int src_y = plane_state->main.y;
3349 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3350 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3351 int dst_x = plane_state->base.dst.x1;
3352 int dst_y = plane_state->base.dst.y1;
3353 int dst_w = drm_rect_width(&plane_state->base.dst);
3354 int dst_h = drm_rect_height(&plane_state->base.dst);
3355 unsigned long irqflags;
3356
3357 /* Sizes are 0 based */
3358 src_w--;
3359 src_h--;
3360 dst_w--;
3361 dst_h--;
3362
3363 crtc->dspaddr_offset = surf_addr;
3364
3365 crtc->adjusted_x = src_x;
3366 crtc->adjusted_y = src_y;
3367
3368 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3369
3370 if (IS_GEMINILAKE(dev_priv)) {
3371 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
3372 PLANE_COLOR_PIPE_GAMMA_ENABLE |
3373 PLANE_COLOR_PIPE_CSC_ENABLE |
3374 PLANE_COLOR_PLANE_GAMMA_DISABLE);
3375 }
3376
3377 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
3378 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3379 I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
3380 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3381
3382 if (scaler_id >= 0) {
3383 uint32_t ps_ctrl = 0;
3384
3385 WARN_ON(!dst_w || !dst_h);
3386 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3387 crtc_state->scaler_state.scalers[scaler_id].mode;
3388 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3389 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3390 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3391 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3392 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
3393 } else {
3394 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3395 }
3396
3397 I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
3398 intel_plane_ggtt_offset(plane_state) + surf_addr);
3399
3400 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3401
3402 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3403 }
3404
3405 static void skylake_disable_primary_plane(struct intel_plane *primary,
3406 struct intel_crtc *crtc)
3407 {
3408 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3409 enum plane_id plane_id = primary->id;
3410 enum pipe pipe = primary->pipe;
3411 unsigned long irqflags;
3412
3413 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3414
3415 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
3416 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
3417 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3418
3419 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3420 }
3421
3422 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3423 {
3424 struct intel_crtc *crtc;
3425
3426 for_each_intel_crtc(&dev_priv->drm, crtc)
3427 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3428 }
3429
3430 static void intel_update_primary_planes(struct drm_device *dev)
3431 {
3432 struct drm_crtc *crtc;
3433
3434 for_each_crtc(dev, crtc) {
3435 struct intel_plane *plane = to_intel_plane(crtc->primary);
3436 struct intel_plane_state *plane_state =
3437 to_intel_plane_state(plane->base.state);
3438
3439 if (plane_state->base.visible) {
3440 trace_intel_update_plane(&plane->base,
3441 to_intel_crtc(crtc));
3442
3443 plane->update_plane(plane,
3444 to_intel_crtc_state(crtc->state),
3445 plane_state);
3446 }
3447 }
3448 }
3449
3450 static int
3451 __intel_display_resume(struct drm_device *dev,
3452 struct drm_atomic_state *state,
3453 struct drm_modeset_acquire_ctx *ctx)
3454 {
3455 struct drm_crtc_state *crtc_state;
3456 struct drm_crtc *crtc;
3457 int i, ret;
3458
3459 intel_modeset_setup_hw_state(dev, ctx);
3460 i915_redisable_vga(to_i915(dev));
3461
3462 if (!state)
3463 return 0;
3464
3465 /*
3466 * We've duplicated the state, pointers to the old state are invalid.
3467 *
3468 * Don't attempt to use the old state until we commit the duplicated state.
3469 */
3470 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3471 /*
3472 * Force recalculation even if we restore
3473 * current state. With fast modeset this may not result
3474 * in a modeset when the state is compatible.
3475 */
3476 crtc_state->mode_changed = true;
3477 }
3478
3479 /* ignore any reset values/BIOS leftovers in the WM registers */
3480 if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3481 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3482
3483 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3484
3485 WARN_ON(ret == -EDEADLK);
3486 return ret;
3487 }
3488
3489 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3490 {
3491 return intel_has_gpu_reset(dev_priv) &&
3492 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3493 }
3494
3495 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3496 {
3497 struct drm_device *dev = &dev_priv->drm;
3498 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3499 struct drm_atomic_state *state;
3500 int ret;
3501
3502 /*
3503 * Need mode_config.mutex so that we don't
3504 * trample ongoing ->detect() and whatnot.
3505 */
3506 mutex_lock(&dev->mode_config.mutex);
3507 drm_modeset_acquire_init(ctx, 0);
3508 while (1) {
3509 ret = drm_modeset_lock_all_ctx(dev, ctx);
3510 if (ret != -EDEADLK)
3511 break;
3512
3513 drm_modeset_backoff(ctx);
3514 }
3515
3516 /* reset doesn't touch the display, but flips might get nuked anyway, */
3517 if (!i915.force_reset_modeset_test &&
3518 !gpu_reset_clobbers_display(dev_priv))
3519 return;
3520
3521 /*
3522 * Disabling the crtcs gracefully seems nicer. Also the
3523 * g33 docs say we should at least disable all the planes.
3524 */
3525 state = drm_atomic_helper_duplicate_state(dev, ctx);
3526 if (IS_ERR(state)) {
3527 ret = PTR_ERR(state);
3528 DRM_ERROR("Duplicating state failed with %i\n", ret);
3529 return;
3530 }
3531
3532 ret = drm_atomic_helper_disable_all(dev, ctx);
3533 if (ret) {
3534 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3535 drm_atomic_state_put(state);
3536 return;
3537 }
3538
3539 dev_priv->modeset_restore_state = state;
3540 state->acquire_ctx = ctx;
3541 }
3542
3543 void intel_finish_reset(struct drm_i915_private *dev_priv)
3544 {
3545 struct drm_device *dev = &dev_priv->drm;
3546 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3547 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3548 int ret;
3549
3550 /*
3551 * Flips in the rings will be nuked by the reset,
3552 * so complete all pending flips so that user space
3553 * will get its events and not get stuck.
3554 */
3555 intel_complete_page_flips(dev_priv);
3556
3557 dev_priv->modeset_restore_state = NULL;
3558
3559 /* reset doesn't touch the display */
3560 if (!gpu_reset_clobbers_display(dev_priv)) {
3561 if (!state) {
3562 /*
3563 * Flips in the rings have been nuked by the reset,
3564 * so update the base address of all primary
3565 * planes to the the last fb to make sure we're
3566 * showing the correct fb after a reset.
3567 *
3568 * FIXME: Atomic will make this obsolete since we won't schedule
3569 * CS-based flips (which might get lost in gpu resets) any more.
3570 */
3571 intel_update_primary_planes(dev);
3572 } else {
3573 ret = __intel_display_resume(dev, state, ctx);
3574 if (ret)
3575 DRM_ERROR("Restoring old state failed with %i\n", ret);
3576 }
3577 } else {
3578 /*
3579 * The display has been reset as well,
3580 * so need a full re-initialization.
3581 */
3582 intel_runtime_pm_disable_interrupts(dev_priv);
3583 intel_runtime_pm_enable_interrupts(dev_priv);
3584
3585 intel_pps_unlock_regs_wa(dev_priv);
3586 intel_modeset_init_hw(dev);
3587
3588 spin_lock_irq(&dev_priv->irq_lock);
3589 if (dev_priv->display.hpd_irq_setup)
3590 dev_priv->display.hpd_irq_setup(dev_priv);
3591 spin_unlock_irq(&dev_priv->irq_lock);
3592
3593 ret = __intel_display_resume(dev, state, ctx);
3594 if (ret)
3595 DRM_ERROR("Restoring old state failed with %i\n", ret);
3596
3597 intel_hpd_init(dev_priv);
3598 }
3599
3600 if (state)
3601 drm_atomic_state_put(state);
3602 drm_modeset_drop_locks(ctx);
3603 drm_modeset_acquire_fini(ctx);
3604 mutex_unlock(&dev->mode_config.mutex);
3605 }
3606
3607 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3608 {
3609 struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3610
3611 if (i915_reset_backoff(error))
3612 return true;
3613
3614 if (crtc->reset_count != i915_reset_count(error))
3615 return true;
3616
3617 return false;
3618 }
3619
3620 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3621 {
3622 struct drm_device *dev = crtc->dev;
3623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3624 bool pending;
3625
3626 if (abort_flip_on_reset(intel_crtc))
3627 return false;
3628
3629 spin_lock_irq(&dev->event_lock);
3630 pending = to_intel_crtc(crtc)->flip_work != NULL;
3631 spin_unlock_irq(&dev->event_lock);
3632
3633 return pending;
3634 }
3635
3636 static void intel_update_pipe_config(struct intel_crtc *crtc,
3637 struct intel_crtc_state *old_crtc_state)
3638 {
3639 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3640 struct intel_crtc_state *pipe_config =
3641 to_intel_crtc_state(crtc->base.state);
3642
3643 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3644 crtc->base.mode = crtc->base.state->mode;
3645
3646 /*
3647 * Update pipe size and adjust fitter if needed: the reason for this is
3648 * that in compute_mode_changes we check the native mode (not the pfit
3649 * mode) to see if we can flip rather than do a full mode set. In the
3650 * fastboot case, we'll flip, but if we don't update the pipesrc and
3651 * pfit state, we'll end up with a big fb scanned out into the wrong
3652 * sized surface.
3653 */
3654
3655 I915_WRITE(PIPESRC(crtc->pipe),
3656 ((pipe_config->pipe_src_w - 1) << 16) |
3657 (pipe_config->pipe_src_h - 1));
3658
3659 /* on skylake this is done by detaching scalers */
3660 if (INTEL_GEN(dev_priv) >= 9) {
3661 skl_detach_scalers(crtc);
3662
3663 if (pipe_config->pch_pfit.enabled)
3664 skylake_pfit_enable(crtc);
3665 } else if (HAS_PCH_SPLIT(dev_priv)) {
3666 if (pipe_config->pch_pfit.enabled)
3667 ironlake_pfit_enable(crtc);
3668 else if (old_crtc_state->pch_pfit.enabled)
3669 ironlake_pfit_disable(crtc, true);
3670 }
3671 }
3672
3673 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3674 {
3675 struct drm_device *dev = crtc->base.dev;
3676 struct drm_i915_private *dev_priv = to_i915(dev);
3677 int pipe = crtc->pipe;
3678 i915_reg_t reg;
3679 u32 temp;
3680
3681 /* enable normal train */
3682 reg = FDI_TX_CTL(pipe);
3683 temp = I915_READ(reg);
3684 if (IS_IVYBRIDGE(dev_priv)) {
3685 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3686 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3687 } else {
3688 temp &= ~FDI_LINK_TRAIN_NONE;
3689 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3690 }
3691 I915_WRITE(reg, temp);
3692
3693 reg = FDI_RX_CTL(pipe);
3694 temp = I915_READ(reg);
3695 if (HAS_PCH_CPT(dev_priv)) {
3696 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3697 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3698 } else {
3699 temp &= ~FDI_LINK_TRAIN_NONE;
3700 temp |= FDI_LINK_TRAIN_NONE;
3701 }
3702 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3703
3704 /* wait one idle pattern time */
3705 POSTING_READ(reg);
3706 udelay(1000);
3707
3708 /* IVB wants error correction enabled */
3709 if (IS_IVYBRIDGE(dev_priv))
3710 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3711 FDI_FE_ERRC_ENABLE);
3712 }
3713
3714 /* The FDI link training functions for ILK/Ibexpeak. */
3715 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3716 const struct intel_crtc_state *crtc_state)
3717 {
3718 struct drm_device *dev = crtc->base.dev;
3719 struct drm_i915_private *dev_priv = to_i915(dev);
3720 int pipe = crtc->pipe;
3721 i915_reg_t reg;
3722 u32 temp, tries;
3723
3724 /* FDI needs bits from pipe first */
3725 assert_pipe_enabled(dev_priv, pipe);
3726
3727 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3728 for train result */
3729 reg = FDI_RX_IMR(pipe);
3730 temp = I915_READ(reg);
3731 temp &= ~FDI_RX_SYMBOL_LOCK;
3732 temp &= ~FDI_RX_BIT_LOCK;
3733 I915_WRITE(reg, temp);
3734 I915_READ(reg);
3735 udelay(150);
3736
3737 /* enable CPU FDI TX and PCH FDI RX */
3738 reg = FDI_TX_CTL(pipe);
3739 temp = I915_READ(reg);
3740 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3741 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3742 temp &= ~FDI_LINK_TRAIN_NONE;
3743 temp |= FDI_LINK_TRAIN_PATTERN_1;
3744 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3745
3746 reg = FDI_RX_CTL(pipe);
3747 temp = I915_READ(reg);
3748 temp &= ~FDI_LINK_TRAIN_NONE;
3749 temp |= FDI_LINK_TRAIN_PATTERN_1;
3750 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3751
3752 POSTING_READ(reg);
3753 udelay(150);
3754
3755 /* Ironlake workaround, enable clock pointer after FDI enable*/
3756 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3757 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3758 FDI_RX_PHASE_SYNC_POINTER_EN);
3759
3760 reg = FDI_RX_IIR(pipe);
3761 for (tries = 0; tries < 5; tries++) {
3762 temp = I915_READ(reg);
3763 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3764
3765 if ((temp & FDI_RX_BIT_LOCK)) {
3766 DRM_DEBUG_KMS("FDI train 1 done.\n");
3767 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3768 break;
3769 }
3770 }
3771 if (tries == 5)
3772 DRM_ERROR("FDI train 1 fail!\n");
3773
3774 /* Train 2 */
3775 reg = FDI_TX_CTL(pipe);
3776 temp = I915_READ(reg);
3777 temp &= ~FDI_LINK_TRAIN_NONE;
3778 temp |= FDI_LINK_TRAIN_PATTERN_2;
3779 I915_WRITE(reg, temp);
3780
3781 reg = FDI_RX_CTL(pipe);
3782 temp = I915_READ(reg);
3783 temp &= ~FDI_LINK_TRAIN_NONE;
3784 temp |= FDI_LINK_TRAIN_PATTERN_2;
3785 I915_WRITE(reg, temp);
3786
3787 POSTING_READ(reg);
3788 udelay(150);
3789
3790 reg = FDI_RX_IIR(pipe);
3791 for (tries = 0; tries < 5; tries++) {
3792 temp = I915_READ(reg);
3793 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3794
3795 if (temp & FDI_RX_SYMBOL_LOCK) {
3796 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3797 DRM_DEBUG_KMS("FDI train 2 done.\n");
3798 break;
3799 }
3800 }
3801 if (tries == 5)
3802 DRM_ERROR("FDI train 2 fail!\n");
3803
3804 DRM_DEBUG_KMS("FDI train done\n");
3805
3806 }
3807
3808 static const int snb_b_fdi_train_param[] = {
3809 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3810 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3811 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3812 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3813 };
3814
3815 /* The FDI link training functions for SNB/Cougarpoint. */
3816 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3817 const struct intel_crtc_state *crtc_state)
3818 {
3819 struct drm_device *dev = crtc->base.dev;
3820 struct drm_i915_private *dev_priv = to_i915(dev);
3821 int pipe = crtc->pipe;
3822 i915_reg_t reg;
3823 u32 temp, i, retry;
3824
3825 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3826 for train result */
3827 reg = FDI_RX_IMR(pipe);
3828 temp = I915_READ(reg);
3829 temp &= ~FDI_RX_SYMBOL_LOCK;
3830 temp &= ~FDI_RX_BIT_LOCK;
3831 I915_WRITE(reg, temp);
3832
3833 POSTING_READ(reg);
3834 udelay(150);
3835
3836 /* enable CPU FDI TX and PCH FDI RX */
3837 reg = FDI_TX_CTL(pipe);
3838 temp = I915_READ(reg);
3839 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3840 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3841 temp &= ~FDI_LINK_TRAIN_NONE;
3842 temp |= FDI_LINK_TRAIN_PATTERN_1;
3843 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3844 /* SNB-B */
3845 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3846 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3847
3848 I915_WRITE(FDI_RX_MISC(pipe),
3849 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3850
3851 reg = FDI_RX_CTL(pipe);
3852 temp = I915_READ(reg);
3853 if (HAS_PCH_CPT(dev_priv)) {
3854 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3855 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3856 } else {
3857 temp &= ~FDI_LINK_TRAIN_NONE;
3858 temp |= FDI_LINK_TRAIN_PATTERN_1;
3859 }
3860 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3861
3862 POSTING_READ(reg);
3863 udelay(150);
3864
3865 for (i = 0; i < 4; i++) {
3866 reg = FDI_TX_CTL(pipe);
3867 temp = I915_READ(reg);
3868 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3869 temp |= snb_b_fdi_train_param[i];
3870 I915_WRITE(reg, temp);
3871
3872 POSTING_READ(reg);
3873 udelay(500);
3874
3875 for (retry = 0; retry < 5; retry++) {
3876 reg = FDI_RX_IIR(pipe);
3877 temp = I915_READ(reg);
3878 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3879 if (temp & FDI_RX_BIT_LOCK) {
3880 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3881 DRM_DEBUG_KMS("FDI train 1 done.\n");
3882 break;
3883 }
3884 udelay(50);
3885 }
3886 if (retry < 5)
3887 break;
3888 }
3889 if (i == 4)
3890 DRM_ERROR("FDI train 1 fail!\n");
3891
3892 /* Train 2 */
3893 reg = FDI_TX_CTL(pipe);
3894 temp = I915_READ(reg);
3895 temp &= ~FDI_LINK_TRAIN_NONE;
3896 temp |= FDI_LINK_TRAIN_PATTERN_2;
3897 if (IS_GEN6(dev_priv)) {
3898 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3899 /* SNB-B */
3900 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3901 }
3902 I915_WRITE(reg, temp);
3903
3904 reg = FDI_RX_CTL(pipe);
3905 temp = I915_READ(reg);
3906 if (HAS_PCH_CPT(dev_priv)) {
3907 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3908 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3909 } else {
3910 temp &= ~FDI_LINK_TRAIN_NONE;
3911 temp |= FDI_LINK_TRAIN_PATTERN_2;
3912 }
3913 I915_WRITE(reg, temp);
3914
3915 POSTING_READ(reg);
3916 udelay(150);
3917
3918 for (i = 0; i < 4; i++) {
3919 reg = FDI_TX_CTL(pipe);
3920 temp = I915_READ(reg);
3921 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3922 temp |= snb_b_fdi_train_param[i];
3923 I915_WRITE(reg, temp);
3924
3925 POSTING_READ(reg);
3926 udelay(500);
3927
3928 for (retry = 0; retry < 5; retry++) {
3929 reg = FDI_RX_IIR(pipe);
3930 temp = I915_READ(reg);
3931 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3932 if (temp & FDI_RX_SYMBOL_LOCK) {
3933 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3934 DRM_DEBUG_KMS("FDI train 2 done.\n");
3935 break;
3936 }
3937 udelay(50);
3938 }
3939 if (retry < 5)
3940 break;
3941 }
3942 if (i == 4)
3943 DRM_ERROR("FDI train 2 fail!\n");
3944
3945 DRM_DEBUG_KMS("FDI train done.\n");
3946 }
3947
3948 /* Manual link training for Ivy Bridge A0 parts */
3949 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
3950 const struct intel_crtc_state *crtc_state)
3951 {
3952 struct drm_device *dev = crtc->base.dev;
3953 struct drm_i915_private *dev_priv = to_i915(dev);
3954 int pipe = crtc->pipe;
3955 i915_reg_t reg;
3956 u32 temp, i, j;
3957
3958 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3959 for train result */
3960 reg = FDI_RX_IMR(pipe);
3961 temp = I915_READ(reg);
3962 temp &= ~FDI_RX_SYMBOL_LOCK;
3963 temp &= ~FDI_RX_BIT_LOCK;
3964 I915_WRITE(reg, temp);
3965
3966 POSTING_READ(reg);
3967 udelay(150);
3968
3969 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3970 I915_READ(FDI_RX_IIR(pipe)));
3971
3972 /* Try each vswing and preemphasis setting twice before moving on */
3973 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3974 /* disable first in case we need to retry */
3975 reg = FDI_TX_CTL(pipe);
3976 temp = I915_READ(reg);
3977 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3978 temp &= ~FDI_TX_ENABLE;
3979 I915_WRITE(reg, temp);
3980
3981 reg = FDI_RX_CTL(pipe);
3982 temp = I915_READ(reg);
3983 temp &= ~FDI_LINK_TRAIN_AUTO;
3984 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3985 temp &= ~FDI_RX_ENABLE;
3986 I915_WRITE(reg, temp);
3987
3988 /* enable CPU FDI TX and PCH FDI RX */
3989 reg = FDI_TX_CTL(pipe);
3990 temp = I915_READ(reg);
3991 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3992 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3993 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3994 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3995 temp |= snb_b_fdi_train_param[j/2];
3996 temp |= FDI_COMPOSITE_SYNC;
3997 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3998
3999 I915_WRITE(FDI_RX_MISC(pipe),
4000 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4001
4002 reg = FDI_RX_CTL(pipe);
4003 temp = I915_READ(reg);
4004 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4005 temp |= FDI_COMPOSITE_SYNC;
4006 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4007
4008 POSTING_READ(reg);
4009 udelay(1); /* should be 0.5us */
4010
4011 for (i = 0; i < 4; i++) {
4012 reg = FDI_RX_IIR(pipe);
4013 temp = I915_READ(reg);
4014 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4015
4016 if (temp & FDI_RX_BIT_LOCK ||
4017 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4018 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4019 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4020 i);
4021 break;
4022 }
4023 udelay(1); /* should be 0.5us */
4024 }
4025 if (i == 4) {
4026 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4027 continue;
4028 }
4029
4030 /* Train 2 */
4031 reg = FDI_TX_CTL(pipe);
4032 temp = I915_READ(reg);
4033 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4034 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4035 I915_WRITE(reg, temp);
4036
4037 reg = FDI_RX_CTL(pipe);
4038 temp = I915_READ(reg);
4039 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4040 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4041 I915_WRITE(reg, temp);
4042
4043 POSTING_READ(reg);
4044 udelay(2); /* should be 1.5us */
4045
4046 for (i = 0; i < 4; i++) {
4047 reg = FDI_RX_IIR(pipe);
4048 temp = I915_READ(reg);
4049 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4050
4051 if (temp & FDI_RX_SYMBOL_LOCK ||
4052 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4053 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4054 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4055 i);
4056 goto train_done;
4057 }
4058 udelay(2); /* should be 1.5us */
4059 }
4060 if (i == 4)
4061 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4062 }
4063
4064 train_done:
4065 DRM_DEBUG_KMS("FDI train done.\n");
4066 }
4067
4068 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4069 {
4070 struct drm_device *dev = intel_crtc->base.dev;
4071 struct drm_i915_private *dev_priv = to_i915(dev);
4072 int pipe = intel_crtc->pipe;
4073 i915_reg_t reg;
4074 u32 temp;
4075
4076 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4077 reg = FDI_RX_CTL(pipe);
4078 temp = I915_READ(reg);
4079 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4080 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4081 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4082 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4083
4084 POSTING_READ(reg);
4085 udelay(200);
4086
4087 /* Switch from Rawclk to PCDclk */
4088 temp = I915_READ(reg);
4089 I915_WRITE(reg, temp | FDI_PCDCLK);
4090
4091 POSTING_READ(reg);
4092 udelay(200);
4093
4094 /* Enable CPU FDI TX PLL, always on for Ironlake */
4095 reg = FDI_TX_CTL(pipe);
4096 temp = I915_READ(reg);
4097 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4098 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4099
4100 POSTING_READ(reg);
4101 udelay(100);
4102 }
4103 }
4104
4105 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4106 {
4107 struct drm_device *dev = intel_crtc->base.dev;
4108 struct drm_i915_private *dev_priv = to_i915(dev);
4109 int pipe = intel_crtc->pipe;
4110 i915_reg_t reg;
4111 u32 temp;
4112
4113 /* Switch from PCDclk to Rawclk */
4114 reg = FDI_RX_CTL(pipe);
4115 temp = I915_READ(reg);
4116 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4117
4118 /* Disable CPU FDI TX PLL */
4119 reg = FDI_TX_CTL(pipe);
4120 temp = I915_READ(reg);
4121 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4122
4123 POSTING_READ(reg);
4124 udelay(100);
4125
4126 reg = FDI_RX_CTL(pipe);
4127 temp = I915_READ(reg);
4128 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4129
4130 /* Wait for the clocks to turn off. */
4131 POSTING_READ(reg);
4132 udelay(100);
4133 }
4134
4135 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4136 {
4137 struct drm_device *dev = crtc->dev;
4138 struct drm_i915_private *dev_priv = to_i915(dev);
4139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4140 int pipe = intel_crtc->pipe;
4141 i915_reg_t reg;
4142 u32 temp;
4143
4144 /* disable CPU FDI tx and PCH FDI rx */
4145 reg = FDI_TX_CTL(pipe);
4146 temp = I915_READ(reg);
4147 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4148 POSTING_READ(reg);
4149
4150 reg = FDI_RX_CTL(pipe);
4151 temp = I915_READ(reg);
4152 temp &= ~(0x7 << 16);
4153 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4154 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4155
4156 POSTING_READ(reg);
4157 udelay(100);
4158
4159 /* Ironlake workaround, disable clock pointer after downing FDI */
4160 if (HAS_PCH_IBX(dev_priv))
4161 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4162
4163 /* still set train pattern 1 */
4164 reg = FDI_TX_CTL(pipe);
4165 temp = I915_READ(reg);
4166 temp &= ~FDI_LINK_TRAIN_NONE;
4167 temp |= FDI_LINK_TRAIN_PATTERN_1;
4168 I915_WRITE(reg, temp);
4169
4170 reg = FDI_RX_CTL(pipe);
4171 temp = I915_READ(reg);
4172 if (HAS_PCH_CPT(dev_priv)) {
4173 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4174 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4175 } else {
4176 temp &= ~FDI_LINK_TRAIN_NONE;
4177 temp |= FDI_LINK_TRAIN_PATTERN_1;
4178 }
4179 /* BPC in FDI rx is consistent with that in PIPECONF */
4180 temp &= ~(0x07 << 16);
4181 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4182 I915_WRITE(reg, temp);
4183
4184 POSTING_READ(reg);
4185 udelay(100);
4186 }
4187
4188 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4189 {
4190 struct intel_crtc *crtc;
4191
4192 /* Note that we don't need to be called with mode_config.lock here
4193 * as our list of CRTC objects is static for the lifetime of the
4194 * device and so cannot disappear as we iterate. Similarly, we can
4195 * happily treat the predicates as racy, atomic checks as userspace
4196 * cannot claim and pin a new fb without at least acquring the
4197 * struct_mutex and so serialising with us.
4198 */
4199 for_each_intel_crtc(&dev_priv->drm, crtc) {
4200 if (atomic_read(&crtc->unpin_work_count) == 0)
4201 continue;
4202
4203 if (crtc->flip_work)
4204 intel_wait_for_vblank(dev_priv, crtc->pipe);
4205
4206 return true;
4207 }
4208
4209 return false;
4210 }
4211
4212 static void page_flip_completed(struct intel_crtc *intel_crtc)
4213 {
4214 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4215 struct intel_flip_work *work = intel_crtc->flip_work;
4216
4217 intel_crtc->flip_work = NULL;
4218
4219 if (work->event)
4220 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4221
4222 drm_crtc_vblank_put(&intel_crtc->base);
4223
4224 wake_up_all(&dev_priv->pending_flip_queue);
4225 trace_i915_flip_complete(intel_crtc->plane,
4226 work->pending_flip_obj);
4227
4228 queue_work(dev_priv->wq, &work->unpin_work);
4229 }
4230
4231 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4232 {
4233 struct drm_device *dev = crtc->dev;
4234 struct drm_i915_private *dev_priv = to_i915(dev);
4235 long ret;
4236
4237 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4238
4239 ret = wait_event_interruptible_timeout(
4240 dev_priv->pending_flip_queue,
4241 !intel_crtc_has_pending_flip(crtc),
4242 60*HZ);
4243
4244 if (ret < 0)
4245 return ret;
4246
4247 if (ret == 0) {
4248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4249 struct intel_flip_work *work;
4250
4251 spin_lock_irq(&dev->event_lock);
4252 work = intel_crtc->flip_work;
4253 if (work && !is_mmio_work(work)) {
4254 WARN_ONCE(1, "Removing stuck page flip\n");
4255 page_flip_completed(intel_crtc);
4256 }
4257 spin_unlock_irq(&dev->event_lock);
4258 }
4259
4260 return 0;
4261 }
4262
4263 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4264 {
4265 u32 temp;
4266
4267 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4268
4269 mutex_lock(&dev_priv->sb_lock);
4270
4271 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4272 temp |= SBI_SSCCTL_DISABLE;
4273 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4274
4275 mutex_unlock(&dev_priv->sb_lock);
4276 }
4277
4278 /* Program iCLKIP clock to the desired frequency */
4279 static void lpt_program_iclkip(struct intel_crtc *crtc)
4280 {
4281 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4282 int clock = crtc->config->base.adjusted_mode.crtc_clock;
4283 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4284 u32 temp;
4285
4286 lpt_disable_iclkip(dev_priv);
4287
4288 /* The iCLK virtual clock root frequency is in MHz,
4289 * but the adjusted_mode->crtc_clock in in KHz. To get the
4290 * divisors, it is necessary to divide one by another, so we
4291 * convert the virtual clock precision to KHz here for higher
4292 * precision.
4293 */
4294 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4295 u32 iclk_virtual_root_freq = 172800 * 1000;
4296 u32 iclk_pi_range = 64;
4297 u32 desired_divisor;
4298
4299 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4300 clock << auxdiv);
4301 divsel = (desired_divisor / iclk_pi_range) - 2;
4302 phaseinc = desired_divisor % iclk_pi_range;
4303
4304 /*
4305 * Near 20MHz is a corner case which is
4306 * out of range for the 7-bit divisor
4307 */
4308 if (divsel <= 0x7f)
4309 break;
4310 }
4311
4312 /* This should not happen with any sane values */
4313 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4314 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4315 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4316 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4317
4318 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4319 clock,
4320 auxdiv,
4321 divsel,
4322 phasedir,
4323 phaseinc);
4324
4325 mutex_lock(&dev_priv->sb_lock);
4326
4327 /* Program SSCDIVINTPHASE6 */
4328 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4329 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4330 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4331 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4332 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4333 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4334 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4335 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4336
4337 /* Program SSCAUXDIV */
4338 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4339 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4340 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4341 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4342
4343 /* Enable modulator and associated divider */
4344 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4345 temp &= ~SBI_SSCCTL_DISABLE;
4346 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4347
4348 mutex_unlock(&dev_priv->sb_lock);
4349
4350 /* Wait for initialization time */
4351 udelay(24);
4352
4353 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4354 }
4355
4356 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4357 {
4358 u32 divsel, phaseinc, auxdiv;
4359 u32 iclk_virtual_root_freq = 172800 * 1000;
4360 u32 iclk_pi_range = 64;
4361 u32 desired_divisor;
4362 u32 temp;
4363
4364 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4365 return 0;
4366
4367 mutex_lock(&dev_priv->sb_lock);
4368
4369 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4370 if (temp & SBI_SSCCTL_DISABLE) {
4371 mutex_unlock(&dev_priv->sb_lock);
4372 return 0;
4373 }
4374
4375 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4376 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4377 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4378 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4379 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4380
4381 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4382 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4383 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4384
4385 mutex_unlock(&dev_priv->sb_lock);
4386
4387 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4388
4389 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4390 desired_divisor << auxdiv);
4391 }
4392
4393 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4394 enum pipe pch_transcoder)
4395 {
4396 struct drm_device *dev = crtc->base.dev;
4397 struct drm_i915_private *dev_priv = to_i915(dev);
4398 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4399
4400 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4401 I915_READ(HTOTAL(cpu_transcoder)));
4402 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4403 I915_READ(HBLANK(cpu_transcoder)));
4404 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4405 I915_READ(HSYNC(cpu_transcoder)));
4406
4407 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4408 I915_READ(VTOTAL(cpu_transcoder)));
4409 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4410 I915_READ(VBLANK(cpu_transcoder)));
4411 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4412 I915_READ(VSYNC(cpu_transcoder)));
4413 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4414 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4415 }
4416
4417 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4418 {
4419 struct drm_i915_private *dev_priv = to_i915(dev);
4420 uint32_t temp;
4421
4422 temp = I915_READ(SOUTH_CHICKEN1);
4423 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4424 return;
4425
4426 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4427 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4428
4429 temp &= ~FDI_BC_BIFURCATION_SELECT;
4430 if (enable)
4431 temp |= FDI_BC_BIFURCATION_SELECT;
4432
4433 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4434 I915_WRITE(SOUTH_CHICKEN1, temp);
4435 POSTING_READ(SOUTH_CHICKEN1);
4436 }
4437
4438 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4439 {
4440 struct drm_device *dev = intel_crtc->base.dev;
4441
4442 switch (intel_crtc->pipe) {
4443 case PIPE_A:
4444 break;
4445 case PIPE_B:
4446 if (intel_crtc->config->fdi_lanes > 2)
4447 cpt_set_fdi_bc_bifurcation(dev, false);
4448 else
4449 cpt_set_fdi_bc_bifurcation(dev, true);
4450
4451 break;
4452 case PIPE_C:
4453 cpt_set_fdi_bc_bifurcation(dev, true);
4454
4455 break;
4456 default:
4457 BUG();
4458 }
4459 }
4460
4461 /* Return which DP Port should be selected for Transcoder DP control */
4462 static enum port
4463 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4464 {
4465 struct drm_device *dev = crtc->base.dev;
4466 struct intel_encoder *encoder;
4467
4468 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4469 if (encoder->type == INTEL_OUTPUT_DP ||
4470 encoder->type == INTEL_OUTPUT_EDP)
4471 return enc_to_dig_port(&encoder->base)->port;
4472 }
4473
4474 return -1;
4475 }
4476
4477 /*
4478 * Enable PCH resources required for PCH ports:
4479 * - PCH PLLs
4480 * - FDI training & RX/TX
4481 * - update transcoder timings
4482 * - DP transcoding bits
4483 * - transcoder
4484 */
4485 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4486 {
4487 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4488 struct drm_device *dev = crtc->base.dev;
4489 struct drm_i915_private *dev_priv = to_i915(dev);
4490 int pipe = crtc->pipe;
4491 u32 temp;
4492
4493 assert_pch_transcoder_disabled(dev_priv, pipe);
4494
4495 if (IS_IVYBRIDGE(dev_priv))
4496 ivybridge_update_fdi_bc_bifurcation(crtc);
4497
4498 /* Write the TU size bits before fdi link training, so that error
4499 * detection works. */
4500 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4501 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4502
4503 /* For PCH output, training FDI link */
4504 dev_priv->display.fdi_link_train(crtc, crtc_state);
4505
4506 /* We need to program the right clock selection before writing the pixel
4507 * mutliplier into the DPLL. */
4508 if (HAS_PCH_CPT(dev_priv)) {
4509 u32 sel;
4510
4511 temp = I915_READ(PCH_DPLL_SEL);
4512 temp |= TRANS_DPLL_ENABLE(pipe);
4513 sel = TRANS_DPLLB_SEL(pipe);
4514 if (crtc_state->shared_dpll ==
4515 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4516 temp |= sel;
4517 else
4518 temp &= ~sel;
4519 I915_WRITE(PCH_DPLL_SEL, temp);
4520 }
4521
4522 /* XXX: pch pll's can be enabled any time before we enable the PCH
4523 * transcoder, and we actually should do this to not upset any PCH
4524 * transcoder that already use the clock when we share it.
4525 *
4526 * Note that enable_shared_dpll tries to do the right thing, but
4527 * get_shared_dpll unconditionally resets the pll - we need that to have
4528 * the right LVDS enable sequence. */
4529 intel_enable_shared_dpll(crtc);
4530
4531 /* set transcoder timing, panel must allow it */
4532 assert_panel_unlocked(dev_priv, pipe);
4533 ironlake_pch_transcoder_set_timings(crtc, pipe);
4534
4535 intel_fdi_normal_train(crtc);
4536
4537 /* For PCH DP, enable TRANS_DP_CTL */
4538 if (HAS_PCH_CPT(dev_priv) &&
4539 intel_crtc_has_dp_encoder(crtc_state)) {
4540 const struct drm_display_mode *adjusted_mode =
4541 &crtc_state->base.adjusted_mode;
4542 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4543 i915_reg_t reg = TRANS_DP_CTL(pipe);
4544 temp = I915_READ(reg);
4545 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4546 TRANS_DP_SYNC_MASK |
4547 TRANS_DP_BPC_MASK);
4548 temp |= TRANS_DP_OUTPUT_ENABLE;
4549 temp |= bpc << 9; /* same format but at 11:9 */
4550
4551 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4552 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4553 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4554 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4555
4556 switch (intel_trans_dp_port_sel(crtc)) {
4557 case PORT_B:
4558 temp |= TRANS_DP_PORT_SEL_B;
4559 break;
4560 case PORT_C:
4561 temp |= TRANS_DP_PORT_SEL_C;
4562 break;
4563 case PORT_D:
4564 temp |= TRANS_DP_PORT_SEL_D;
4565 break;
4566 default:
4567 BUG();
4568 }
4569
4570 I915_WRITE(reg, temp);
4571 }
4572
4573 ironlake_enable_pch_transcoder(dev_priv, pipe);
4574 }
4575
4576 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4577 {
4578 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4579 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4580 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4581
4582 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4583
4584 lpt_program_iclkip(crtc);
4585
4586 /* Set transcoder timing. */
4587 ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4588
4589 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4590 }
4591
4592 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4593 {
4594 struct drm_i915_private *dev_priv = to_i915(dev);
4595 i915_reg_t dslreg = PIPEDSL(pipe);
4596 u32 temp;
4597
4598 temp = I915_READ(dslreg);
4599 udelay(500);
4600 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4601 if (wait_for(I915_READ(dslreg) != temp, 5))
4602 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4603 }
4604 }
4605
4606 static int
4607 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4608 unsigned int scaler_user, int *scaler_id,
4609 int src_w, int src_h, int dst_w, int dst_h)
4610 {
4611 struct intel_crtc_scaler_state *scaler_state =
4612 &crtc_state->scaler_state;
4613 struct intel_crtc *intel_crtc =
4614 to_intel_crtc(crtc_state->base.crtc);
4615 int need_scaling;
4616
4617 /*
4618 * Src coordinates are already rotated by 270 degrees for
4619 * the 90/270 degree plane rotation cases (to match the
4620 * GTT mapping), hence no need to account for rotation here.
4621 */
4622 need_scaling = src_w != dst_w || src_h != dst_h;
4623
4624 /*
4625 * if plane is being disabled or scaler is no more required or force detach
4626 * - free scaler binded to this plane/crtc
4627 * - in order to do this, update crtc->scaler_usage
4628 *
4629 * Here scaler state in crtc_state is set free so that
4630 * scaler can be assigned to other user. Actual register
4631 * update to free the scaler is done in plane/panel-fit programming.
4632 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4633 */
4634 if (force_detach || !need_scaling) {
4635 if (*scaler_id >= 0) {
4636 scaler_state->scaler_users &= ~(1 << scaler_user);
4637 scaler_state->scalers[*scaler_id].in_use = 0;
4638
4639 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4640 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4641 intel_crtc->pipe, scaler_user, *scaler_id,
4642 scaler_state->scaler_users);
4643 *scaler_id = -1;
4644 }
4645 return 0;
4646 }
4647
4648 /* range checks */
4649 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4650 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4651
4652 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4653 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4654 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4655 "size is out of scaler range\n",
4656 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4657 return -EINVAL;
4658 }
4659
4660 /* mark this plane as a scaler user in crtc_state */
4661 scaler_state->scaler_users |= (1 << scaler_user);
4662 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4663 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4664 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4665 scaler_state->scaler_users);
4666
4667 return 0;
4668 }
4669
4670 /**
4671 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4672 *
4673 * @state: crtc's scaler state
4674 *
4675 * Return
4676 * 0 - scaler_usage updated successfully
4677 * error - requested scaling cannot be supported or other error condition
4678 */
4679 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4680 {
4681 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4682
4683 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4684 &state->scaler_state.scaler_id,
4685 state->pipe_src_w, state->pipe_src_h,
4686 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4687 }
4688
4689 /**
4690 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4691 *
4692 * @state: crtc's scaler state
4693 * @plane_state: atomic plane state to update
4694 *
4695 * Return
4696 * 0 - scaler_usage updated successfully
4697 * error - requested scaling cannot be supported or other error condition
4698 */
4699 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4700 struct intel_plane_state *plane_state)
4701 {
4702
4703 struct intel_plane *intel_plane =
4704 to_intel_plane(plane_state->base.plane);
4705 struct drm_framebuffer *fb = plane_state->base.fb;
4706 int ret;
4707
4708 bool force_detach = !fb || !plane_state->base.visible;
4709
4710 ret = skl_update_scaler(crtc_state, force_detach,
4711 drm_plane_index(&intel_plane->base),
4712 &plane_state->scaler_id,
4713 drm_rect_width(&plane_state->base.src) >> 16,
4714 drm_rect_height(&plane_state->base.src) >> 16,
4715 drm_rect_width(&plane_state->base.dst),
4716 drm_rect_height(&plane_state->base.dst));
4717
4718 if (ret || plane_state->scaler_id < 0)
4719 return ret;
4720
4721 /* check colorkey */
4722 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4723 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4724 intel_plane->base.base.id,
4725 intel_plane->base.name);
4726 return -EINVAL;
4727 }
4728
4729 /* Check src format */
4730 switch (fb->format->format) {
4731 case DRM_FORMAT_RGB565:
4732 case DRM_FORMAT_XBGR8888:
4733 case DRM_FORMAT_XRGB8888:
4734 case DRM_FORMAT_ABGR8888:
4735 case DRM_FORMAT_ARGB8888:
4736 case DRM_FORMAT_XRGB2101010:
4737 case DRM_FORMAT_XBGR2101010:
4738 case DRM_FORMAT_YUYV:
4739 case DRM_FORMAT_YVYU:
4740 case DRM_FORMAT_UYVY:
4741 case DRM_FORMAT_VYUY:
4742 break;
4743 default:
4744 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4745 intel_plane->base.base.id, intel_plane->base.name,
4746 fb->base.id, fb->format->format);
4747 return -EINVAL;
4748 }
4749
4750 return 0;
4751 }
4752
4753 static void skylake_scaler_disable(struct intel_crtc *crtc)
4754 {
4755 int i;
4756
4757 for (i = 0; i < crtc->num_scalers; i++)
4758 skl_detach_scaler(crtc, i);
4759 }
4760
4761 static void skylake_pfit_enable(struct intel_crtc *crtc)
4762 {
4763 struct drm_device *dev = crtc->base.dev;
4764 struct drm_i915_private *dev_priv = to_i915(dev);
4765 int pipe = crtc->pipe;
4766 struct intel_crtc_scaler_state *scaler_state =
4767 &crtc->config->scaler_state;
4768
4769 if (crtc->config->pch_pfit.enabled) {
4770 int id;
4771
4772 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4773 return;
4774
4775 id = scaler_state->scaler_id;
4776 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4777 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4778 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4779 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4780 }
4781 }
4782
4783 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4784 {
4785 struct drm_device *dev = crtc->base.dev;
4786 struct drm_i915_private *dev_priv = to_i915(dev);
4787 int pipe = crtc->pipe;
4788
4789 if (crtc->config->pch_pfit.enabled) {
4790 /* Force use of hard-coded filter coefficients
4791 * as some pre-programmed values are broken,
4792 * e.g. x201.
4793 */
4794 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4795 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4796 PF_PIPE_SEL_IVB(pipe));
4797 else
4798 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4799 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4800 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4801 }
4802 }
4803
4804 void hsw_enable_ips(struct intel_crtc *crtc)
4805 {
4806 struct drm_device *dev = crtc->base.dev;
4807 struct drm_i915_private *dev_priv = to_i915(dev);
4808
4809 if (!crtc->config->ips_enabled)
4810 return;
4811
4812 /*
4813 * We can only enable IPS after we enable a plane and wait for a vblank
4814 * This function is called from post_plane_update, which is run after
4815 * a vblank wait.
4816 */
4817
4818 assert_plane_enabled(dev_priv, crtc->plane);
4819 if (IS_BROADWELL(dev_priv)) {
4820 mutex_lock(&dev_priv->rps.hw_lock);
4821 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4822 mutex_unlock(&dev_priv->rps.hw_lock);
4823 /* Quoting Art Runyan: "its not safe to expect any particular
4824 * value in IPS_CTL bit 31 after enabling IPS through the
4825 * mailbox." Moreover, the mailbox may return a bogus state,
4826 * so we need to just enable it and continue on.
4827 */
4828 } else {
4829 I915_WRITE(IPS_CTL, IPS_ENABLE);
4830 /* The bit only becomes 1 in the next vblank, so this wait here
4831 * is essentially intel_wait_for_vblank. If we don't have this
4832 * and don't wait for vblanks until the end of crtc_enable, then
4833 * the HW state readout code will complain that the expected
4834 * IPS_CTL value is not the one we read. */
4835 if (intel_wait_for_register(dev_priv,
4836 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4837 50))
4838 DRM_ERROR("Timed out waiting for IPS enable\n");
4839 }
4840 }
4841
4842 void hsw_disable_ips(struct intel_crtc *crtc)
4843 {
4844 struct drm_device *dev = crtc->base.dev;
4845 struct drm_i915_private *dev_priv = to_i915(dev);
4846
4847 if (!crtc->config->ips_enabled)
4848 return;
4849
4850 assert_plane_enabled(dev_priv, crtc->plane);
4851 if (IS_BROADWELL(dev_priv)) {
4852 mutex_lock(&dev_priv->rps.hw_lock);
4853 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4854 mutex_unlock(&dev_priv->rps.hw_lock);
4855 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4856 if (intel_wait_for_register(dev_priv,
4857 IPS_CTL, IPS_ENABLE, 0,
4858 42))
4859 DRM_ERROR("Timed out waiting for IPS disable\n");
4860 } else {
4861 I915_WRITE(IPS_CTL, 0);
4862 POSTING_READ(IPS_CTL);
4863 }
4864
4865 /* We need to wait for a vblank before we can disable the plane. */
4866 intel_wait_for_vblank(dev_priv, crtc->pipe);
4867 }
4868
4869 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4870 {
4871 if (intel_crtc->overlay) {
4872 struct drm_device *dev = intel_crtc->base.dev;
4873
4874 mutex_lock(&dev->struct_mutex);
4875 (void) intel_overlay_switch_off(intel_crtc->overlay);
4876 mutex_unlock(&dev->struct_mutex);
4877 }
4878
4879 /* Let userspace switch the overlay on again. In most cases userspace
4880 * has to recompute where to put it anyway.
4881 */
4882 }
4883
4884 /**
4885 * intel_post_enable_primary - Perform operations after enabling primary plane
4886 * @crtc: the CRTC whose primary plane was just enabled
4887 *
4888 * Performs potentially sleeping operations that must be done after the primary
4889 * plane is enabled, such as updating FBC and IPS. Note that this may be
4890 * called due to an explicit primary plane update, or due to an implicit
4891 * re-enable that is caused when a sprite plane is updated to no longer
4892 * completely hide the primary plane.
4893 */
4894 static void
4895 intel_post_enable_primary(struct drm_crtc *crtc)
4896 {
4897 struct drm_device *dev = crtc->dev;
4898 struct drm_i915_private *dev_priv = to_i915(dev);
4899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4900 int pipe = intel_crtc->pipe;
4901
4902 /*
4903 * FIXME IPS should be fine as long as one plane is
4904 * enabled, but in practice it seems to have problems
4905 * when going from primary only to sprite only and vice
4906 * versa.
4907 */
4908 hsw_enable_ips(intel_crtc);
4909
4910 /*
4911 * Gen2 reports pipe underruns whenever all planes are disabled.
4912 * So don't enable underrun reporting before at least some planes
4913 * are enabled.
4914 * FIXME: Need to fix the logic to work when we turn off all planes
4915 * but leave the pipe running.
4916 */
4917 if (IS_GEN2(dev_priv))
4918 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4919
4920 /* Underruns don't always raise interrupts, so check manually. */
4921 intel_check_cpu_fifo_underruns(dev_priv);
4922 intel_check_pch_fifo_underruns(dev_priv);
4923 }
4924
4925 /* FIXME move all this to pre_plane_update() with proper state tracking */
4926 static void
4927 intel_pre_disable_primary(struct drm_crtc *crtc)
4928 {
4929 struct drm_device *dev = crtc->dev;
4930 struct drm_i915_private *dev_priv = to_i915(dev);
4931 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4932 int pipe = intel_crtc->pipe;
4933
4934 /*
4935 * Gen2 reports pipe underruns whenever all planes are disabled.
4936 * So diasble underrun reporting before all the planes get disabled.
4937 * FIXME: Need to fix the logic to work when we turn off all planes
4938 * but leave the pipe running.
4939 */
4940 if (IS_GEN2(dev_priv))
4941 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4942
4943 /*
4944 * FIXME IPS should be fine as long as one plane is
4945 * enabled, but in practice it seems to have problems
4946 * when going from primary only to sprite only and vice
4947 * versa.
4948 */
4949 hsw_disable_ips(intel_crtc);
4950 }
4951
4952 /* FIXME get rid of this and use pre_plane_update */
4953 static void
4954 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4955 {
4956 struct drm_device *dev = crtc->dev;
4957 struct drm_i915_private *dev_priv = to_i915(dev);
4958 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4959 int pipe = intel_crtc->pipe;
4960
4961 intel_pre_disable_primary(crtc);
4962
4963 /*
4964 * Vblank time updates from the shadow to live plane control register
4965 * are blocked if the memory self-refresh mode is active at that
4966 * moment. So to make sure the plane gets truly disabled, disable
4967 * first the self-refresh mode. The self-refresh enable bit in turn
4968 * will be checked/applied by the HW only at the next frame start
4969 * event which is after the vblank start event, so we need to have a
4970 * wait-for-vblank between disabling the plane and the pipe.
4971 */
4972 if (HAS_GMCH_DISPLAY(dev_priv) &&
4973 intel_set_memory_cxsr(dev_priv, false))
4974 intel_wait_for_vblank(dev_priv, pipe);
4975 }
4976
4977 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4978 {
4979 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4980 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4981 struct intel_crtc_state *pipe_config =
4982 to_intel_crtc_state(crtc->base.state);
4983 struct drm_plane *primary = crtc->base.primary;
4984 struct drm_plane_state *old_pri_state =
4985 drm_atomic_get_existing_plane_state(old_state, primary);
4986
4987 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
4988
4989 if (pipe_config->update_wm_post && pipe_config->base.active)
4990 intel_update_watermarks(crtc);
4991
4992 if (old_pri_state) {
4993 struct intel_plane_state *primary_state =
4994 to_intel_plane_state(primary->state);
4995 struct intel_plane_state *old_primary_state =
4996 to_intel_plane_state(old_pri_state);
4997
4998 intel_fbc_post_update(crtc);
4999
5000 if (primary_state->base.visible &&
5001 (needs_modeset(&pipe_config->base) ||
5002 !old_primary_state->base.visible))
5003 intel_post_enable_primary(&crtc->base);
5004 }
5005 }
5006
5007 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5008 struct intel_crtc_state *pipe_config)
5009 {
5010 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5011 struct drm_device *dev = crtc->base.dev;
5012 struct drm_i915_private *dev_priv = to_i915(dev);
5013 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5014 struct drm_plane *primary = crtc->base.primary;
5015 struct drm_plane_state *old_pri_state =
5016 drm_atomic_get_existing_plane_state(old_state, primary);
5017 bool modeset = needs_modeset(&pipe_config->base);
5018 struct intel_atomic_state *old_intel_state =
5019 to_intel_atomic_state(old_state);
5020
5021 if (old_pri_state) {
5022 struct intel_plane_state *primary_state =
5023 to_intel_plane_state(primary->state);
5024 struct intel_plane_state *old_primary_state =
5025 to_intel_plane_state(old_pri_state);
5026
5027 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5028
5029 if (old_primary_state->base.visible &&
5030 (modeset || !primary_state->base.visible))
5031 intel_pre_disable_primary(&crtc->base);
5032 }
5033
5034 /*
5035 * Vblank time updates from the shadow to live plane control register
5036 * are blocked if the memory self-refresh mode is active at that
5037 * moment. So to make sure the plane gets truly disabled, disable
5038 * first the self-refresh mode. The self-refresh enable bit in turn
5039 * will be checked/applied by the HW only at the next frame start
5040 * event which is after the vblank start event, so we need to have a
5041 * wait-for-vblank between disabling the plane and the pipe.
5042 */
5043 if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5044 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5045 intel_wait_for_vblank(dev_priv, crtc->pipe);
5046
5047 /*
5048 * IVB workaround: must disable low power watermarks for at least
5049 * one frame before enabling scaling. LP watermarks can be re-enabled
5050 * when scaling is disabled.
5051 *
5052 * WaCxSRDisabledForSpriteScaling:ivb
5053 */
5054 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5055 intel_wait_for_vblank(dev_priv, crtc->pipe);
5056
5057 /*
5058 * If we're doing a modeset, we're done. No need to do any pre-vblank
5059 * watermark programming here.
5060 */
5061 if (needs_modeset(&pipe_config->base))
5062 return;
5063
5064 /*
5065 * For platforms that support atomic watermarks, program the
5066 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5067 * will be the intermediate values that are safe for both pre- and
5068 * post- vblank; when vblank happens, the 'active' values will be set
5069 * to the final 'target' values and we'll do this again to get the
5070 * optimal watermarks. For gen9+ platforms, the values we program here
5071 * will be the final target values which will get automatically latched
5072 * at vblank time; no further programming will be necessary.
5073 *
5074 * If a platform hasn't been transitioned to atomic watermarks yet,
5075 * we'll continue to update watermarks the old way, if flags tell
5076 * us to.
5077 */
5078 if (dev_priv->display.initial_watermarks != NULL)
5079 dev_priv->display.initial_watermarks(old_intel_state,
5080 pipe_config);
5081 else if (pipe_config->update_wm_pre)
5082 intel_update_watermarks(crtc);
5083 }
5084
5085 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5086 {
5087 struct drm_device *dev = crtc->dev;
5088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5089 struct drm_plane *p;
5090 int pipe = intel_crtc->pipe;
5091
5092 intel_crtc_dpms_overlay_disable(intel_crtc);
5093
5094 drm_for_each_plane_mask(p, dev, plane_mask)
5095 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
5096
5097 /*
5098 * FIXME: Once we grow proper nuclear flip support out of this we need
5099 * to compute the mask of flip planes precisely. For the time being
5100 * consider this a flip to a NULL plane.
5101 */
5102 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5103 }
5104
5105 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5106 struct intel_crtc_state *crtc_state,
5107 struct drm_atomic_state *old_state)
5108 {
5109 struct drm_connector_state *conn_state;
5110 struct drm_connector *conn;
5111 int i;
5112
5113 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5114 struct intel_encoder *encoder =
5115 to_intel_encoder(conn_state->best_encoder);
5116
5117 if (conn_state->crtc != crtc)
5118 continue;
5119
5120 if (encoder->pre_pll_enable)
5121 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5122 }
5123 }
5124
5125 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5126 struct intel_crtc_state *crtc_state,
5127 struct drm_atomic_state *old_state)
5128 {
5129 struct drm_connector_state *conn_state;
5130 struct drm_connector *conn;
5131 int i;
5132
5133 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5134 struct intel_encoder *encoder =
5135 to_intel_encoder(conn_state->best_encoder);
5136
5137 if (conn_state->crtc != crtc)
5138 continue;
5139
5140 if (encoder->pre_enable)
5141 encoder->pre_enable(encoder, crtc_state, conn_state);
5142 }
5143 }
5144
5145 static void intel_encoders_enable(struct drm_crtc *crtc,
5146 struct intel_crtc_state *crtc_state,
5147 struct drm_atomic_state *old_state)
5148 {
5149 struct drm_connector_state *conn_state;
5150 struct drm_connector *conn;
5151 int i;
5152
5153 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5154 struct intel_encoder *encoder =
5155 to_intel_encoder(conn_state->best_encoder);
5156
5157 if (conn_state->crtc != crtc)
5158 continue;
5159
5160 encoder->enable(encoder, crtc_state, conn_state);
5161 intel_opregion_notify_encoder(encoder, true);
5162 }
5163 }
5164
5165 static void intel_encoders_disable(struct drm_crtc *crtc,
5166 struct intel_crtc_state *old_crtc_state,
5167 struct drm_atomic_state *old_state)
5168 {
5169 struct drm_connector_state *old_conn_state;
5170 struct drm_connector *conn;
5171 int i;
5172
5173 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5174 struct intel_encoder *encoder =
5175 to_intel_encoder(old_conn_state->best_encoder);
5176
5177 if (old_conn_state->crtc != crtc)
5178 continue;
5179
5180 intel_opregion_notify_encoder(encoder, false);
5181 encoder->disable(encoder, old_crtc_state, old_conn_state);
5182 }
5183 }
5184
5185 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5186 struct intel_crtc_state *old_crtc_state,
5187 struct drm_atomic_state *old_state)
5188 {
5189 struct drm_connector_state *old_conn_state;
5190 struct drm_connector *conn;
5191 int i;
5192
5193 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5194 struct intel_encoder *encoder =
5195 to_intel_encoder(old_conn_state->best_encoder);
5196
5197 if (old_conn_state->crtc != crtc)
5198 continue;
5199
5200 if (encoder->post_disable)
5201 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5202 }
5203 }
5204
5205 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5206 struct intel_crtc_state *old_crtc_state,
5207 struct drm_atomic_state *old_state)
5208 {
5209 struct drm_connector_state *old_conn_state;
5210 struct drm_connector *conn;
5211 int i;
5212
5213 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5214 struct intel_encoder *encoder =
5215 to_intel_encoder(old_conn_state->best_encoder);
5216
5217 if (old_conn_state->crtc != crtc)
5218 continue;
5219
5220 if (encoder->post_pll_disable)
5221 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5222 }
5223 }
5224
5225 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5226 struct drm_atomic_state *old_state)
5227 {
5228 struct drm_crtc *crtc = pipe_config->base.crtc;
5229 struct drm_device *dev = crtc->dev;
5230 struct drm_i915_private *dev_priv = to_i915(dev);
5231 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5232 int pipe = intel_crtc->pipe;
5233 struct intel_atomic_state *old_intel_state =
5234 to_intel_atomic_state(old_state);
5235
5236 if (WARN_ON(intel_crtc->active))
5237 return;
5238
5239 /*
5240 * Sometimes spurious CPU pipe underruns happen during FDI
5241 * training, at least with VGA+HDMI cloning. Suppress them.
5242 *
5243 * On ILK we get an occasional spurious CPU pipe underruns
5244 * between eDP port A enable and vdd enable. Also PCH port
5245 * enable seems to result in the occasional CPU pipe underrun.
5246 *
5247 * Spurious PCH underruns also occur during PCH enabling.
5248 */
5249 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5250 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5251 if (intel_crtc->config->has_pch_encoder)
5252 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5253
5254 if (intel_crtc->config->has_pch_encoder)
5255 intel_prepare_shared_dpll(intel_crtc);
5256
5257 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5258 intel_dp_set_m_n(intel_crtc, M1_N1);
5259
5260 intel_set_pipe_timings(intel_crtc);
5261 intel_set_pipe_src_size(intel_crtc);
5262
5263 if (intel_crtc->config->has_pch_encoder) {
5264 intel_cpu_transcoder_set_m_n(intel_crtc,
5265 &intel_crtc->config->fdi_m_n, NULL);
5266 }
5267
5268 ironlake_set_pipeconf(crtc);
5269
5270 intel_crtc->active = true;
5271
5272 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5273
5274 if (intel_crtc->config->has_pch_encoder) {
5275 /* Note: FDI PLL enabling _must_ be done before we enable the
5276 * cpu pipes, hence this is separate from all the other fdi/pch
5277 * enabling. */
5278 ironlake_fdi_pll_enable(intel_crtc);
5279 } else {
5280 assert_fdi_tx_disabled(dev_priv, pipe);
5281 assert_fdi_rx_disabled(dev_priv, pipe);
5282 }
5283
5284 ironlake_pfit_enable(intel_crtc);
5285
5286 /*
5287 * On ILK+ LUT must be loaded before the pipe is running but with
5288 * clocks enabled
5289 */
5290 intel_color_load_luts(&pipe_config->base);
5291
5292 if (dev_priv->display.initial_watermarks != NULL)
5293 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5294 intel_enable_pipe(intel_crtc);
5295
5296 if (intel_crtc->config->has_pch_encoder)
5297 ironlake_pch_enable(pipe_config);
5298
5299 assert_vblank_disabled(crtc);
5300 drm_crtc_vblank_on(crtc);
5301
5302 intel_encoders_enable(crtc, pipe_config, old_state);
5303
5304 if (HAS_PCH_CPT(dev_priv))
5305 cpt_verify_modeset(dev, intel_crtc->pipe);
5306
5307 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5308 if (intel_crtc->config->has_pch_encoder)
5309 intel_wait_for_vblank(dev_priv, pipe);
5310 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5311 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5312 }
5313
5314 /* IPS only exists on ULT machines and is tied to pipe A. */
5315 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5316 {
5317 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5318 }
5319
5320 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5321 struct drm_atomic_state *old_state)
5322 {
5323 struct drm_crtc *crtc = pipe_config->base.crtc;
5324 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5325 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5326 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5327 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5328 struct intel_atomic_state *old_intel_state =
5329 to_intel_atomic_state(old_state);
5330
5331 if (WARN_ON(intel_crtc->active))
5332 return;
5333
5334 if (intel_crtc->config->has_pch_encoder)
5335 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5336 false);
5337
5338 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5339
5340 if (intel_crtc->config->shared_dpll)
5341 intel_enable_shared_dpll(intel_crtc);
5342
5343 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5344 intel_dp_set_m_n(intel_crtc, M1_N1);
5345
5346 if (!transcoder_is_dsi(cpu_transcoder))
5347 intel_set_pipe_timings(intel_crtc);
5348
5349 intel_set_pipe_src_size(intel_crtc);
5350
5351 if (cpu_transcoder != TRANSCODER_EDP &&
5352 !transcoder_is_dsi(cpu_transcoder)) {
5353 I915_WRITE(PIPE_MULT(cpu_transcoder),
5354 intel_crtc->config->pixel_multiplier - 1);
5355 }
5356
5357 if (intel_crtc->config->has_pch_encoder) {
5358 intel_cpu_transcoder_set_m_n(intel_crtc,
5359 &intel_crtc->config->fdi_m_n, NULL);
5360 }
5361
5362 if (!transcoder_is_dsi(cpu_transcoder))
5363 haswell_set_pipeconf(crtc);
5364
5365 haswell_set_pipemisc(crtc);
5366
5367 intel_color_set_csc(&pipe_config->base);
5368
5369 intel_crtc->active = true;
5370
5371 if (intel_crtc->config->has_pch_encoder)
5372 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5373 else
5374 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5375
5376 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5377
5378 if (intel_crtc->config->has_pch_encoder)
5379 dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
5380
5381 if (!transcoder_is_dsi(cpu_transcoder))
5382 intel_ddi_enable_pipe_clock(pipe_config);
5383
5384 if (INTEL_GEN(dev_priv) >= 9)
5385 skylake_pfit_enable(intel_crtc);
5386 else
5387 ironlake_pfit_enable(intel_crtc);
5388
5389 /*
5390 * On ILK+ LUT must be loaded before the pipe is running but with
5391 * clocks enabled
5392 */
5393 intel_color_load_luts(&pipe_config->base);
5394
5395 intel_ddi_set_pipe_settings(pipe_config);
5396 if (!transcoder_is_dsi(cpu_transcoder))
5397 intel_ddi_enable_transcoder_func(pipe_config);
5398
5399 if (dev_priv->display.initial_watermarks != NULL)
5400 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5401
5402 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5403 if (!transcoder_is_dsi(cpu_transcoder))
5404 intel_enable_pipe(intel_crtc);
5405
5406 if (intel_crtc->config->has_pch_encoder)
5407 lpt_pch_enable(pipe_config);
5408
5409 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5410 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5411
5412 assert_vblank_disabled(crtc);
5413 drm_crtc_vblank_on(crtc);
5414
5415 intel_encoders_enable(crtc, pipe_config, old_state);
5416
5417 if (intel_crtc->config->has_pch_encoder) {
5418 intel_wait_for_vblank(dev_priv, pipe);
5419 intel_wait_for_vblank(dev_priv, pipe);
5420 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5421 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5422 true);
5423 }
5424
5425 /* If we change the relative order between pipe/planes enabling, we need
5426 * to change the workaround. */
5427 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5428 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5429 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5430 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5431 }
5432 }
5433
5434 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5435 {
5436 struct drm_device *dev = crtc->base.dev;
5437 struct drm_i915_private *dev_priv = to_i915(dev);
5438 int pipe = crtc->pipe;
5439
5440 /* To avoid upsetting the power well on haswell only disable the pfit if
5441 * it's in use. The hw state code will make sure we get this right. */
5442 if (force || crtc->config->pch_pfit.enabled) {
5443 I915_WRITE(PF_CTL(pipe), 0);
5444 I915_WRITE(PF_WIN_POS(pipe), 0);
5445 I915_WRITE(PF_WIN_SZ(pipe), 0);
5446 }
5447 }
5448
5449 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5450 struct drm_atomic_state *old_state)
5451 {
5452 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5453 struct drm_device *dev = crtc->dev;
5454 struct drm_i915_private *dev_priv = to_i915(dev);
5455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5456 int pipe = intel_crtc->pipe;
5457
5458 /*
5459 * Sometimes spurious CPU pipe underruns happen when the
5460 * pipe is already disabled, but FDI RX/TX is still enabled.
5461 * Happens at least with VGA+HDMI cloning. Suppress them.
5462 */
5463 if (intel_crtc->config->has_pch_encoder) {
5464 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5465 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5466 }
5467
5468 intel_encoders_disable(crtc, old_crtc_state, old_state);
5469
5470 drm_crtc_vblank_off(crtc);
5471 assert_vblank_disabled(crtc);
5472
5473 intel_disable_pipe(intel_crtc);
5474
5475 ironlake_pfit_disable(intel_crtc, false);
5476
5477 if (intel_crtc->config->has_pch_encoder)
5478 ironlake_fdi_disable(crtc);
5479
5480 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5481
5482 if (intel_crtc->config->has_pch_encoder) {
5483 ironlake_disable_pch_transcoder(dev_priv, pipe);
5484
5485 if (HAS_PCH_CPT(dev_priv)) {
5486 i915_reg_t reg;
5487 u32 temp;
5488
5489 /* disable TRANS_DP_CTL */
5490 reg = TRANS_DP_CTL(pipe);
5491 temp = I915_READ(reg);
5492 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5493 TRANS_DP_PORT_SEL_MASK);
5494 temp |= TRANS_DP_PORT_SEL_NONE;
5495 I915_WRITE(reg, temp);
5496
5497 /* disable DPLL_SEL */
5498 temp = I915_READ(PCH_DPLL_SEL);
5499 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5500 I915_WRITE(PCH_DPLL_SEL, temp);
5501 }
5502
5503 ironlake_fdi_pll_disable(intel_crtc);
5504 }
5505
5506 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5507 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5508 }
5509
5510 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5511 struct drm_atomic_state *old_state)
5512 {
5513 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5514 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5516 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5517
5518 if (intel_crtc->config->has_pch_encoder)
5519 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5520 false);
5521
5522 intel_encoders_disable(crtc, old_crtc_state, old_state);
5523
5524 drm_crtc_vblank_off(crtc);
5525 assert_vblank_disabled(crtc);
5526
5527 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5528 if (!transcoder_is_dsi(cpu_transcoder))
5529 intel_disable_pipe(intel_crtc);
5530
5531 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5532 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5533
5534 if (!transcoder_is_dsi(cpu_transcoder))
5535 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5536
5537 if (INTEL_GEN(dev_priv) >= 9)
5538 skylake_scaler_disable(intel_crtc);
5539 else
5540 ironlake_pfit_disable(intel_crtc, false);
5541
5542 if (!transcoder_is_dsi(cpu_transcoder))
5543 intel_ddi_disable_pipe_clock(intel_crtc->config);
5544
5545 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5546
5547 if (old_crtc_state->has_pch_encoder)
5548 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5549 true);
5550 }
5551
5552 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5553 {
5554 struct drm_device *dev = crtc->base.dev;
5555 struct drm_i915_private *dev_priv = to_i915(dev);
5556 struct intel_crtc_state *pipe_config = crtc->config;
5557
5558 if (!pipe_config->gmch_pfit.control)
5559 return;
5560
5561 /*
5562 * The panel fitter should only be adjusted whilst the pipe is disabled,
5563 * according to register description and PRM.
5564 */
5565 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5566 assert_pipe_disabled(dev_priv, crtc->pipe);
5567
5568 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5569 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5570
5571 /* Border color in case we don't scale up to the full screen. Black by
5572 * default, change to something else for debugging. */
5573 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5574 }
5575
5576 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5577 {
5578 switch (port) {
5579 case PORT_A:
5580 return POWER_DOMAIN_PORT_DDI_A_LANES;
5581 case PORT_B:
5582 return POWER_DOMAIN_PORT_DDI_B_LANES;
5583 case PORT_C:
5584 return POWER_DOMAIN_PORT_DDI_C_LANES;
5585 case PORT_D:
5586 return POWER_DOMAIN_PORT_DDI_D_LANES;
5587 case PORT_E:
5588 return POWER_DOMAIN_PORT_DDI_E_LANES;
5589 default:
5590 MISSING_CASE(port);
5591 return POWER_DOMAIN_PORT_OTHER;
5592 }
5593 }
5594
5595 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5596 struct intel_crtc_state *crtc_state)
5597 {
5598 struct drm_device *dev = crtc->dev;
5599 struct drm_i915_private *dev_priv = to_i915(dev);
5600 struct drm_encoder *encoder;
5601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5602 enum pipe pipe = intel_crtc->pipe;
5603 u64 mask;
5604 enum transcoder transcoder = crtc_state->cpu_transcoder;
5605
5606 if (!crtc_state->base.active)
5607 return 0;
5608
5609 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5610 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5611 if (crtc_state->pch_pfit.enabled ||
5612 crtc_state->pch_pfit.force_thru)
5613 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5614
5615 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5616 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5617
5618 mask |= BIT_ULL(intel_encoder->power_domain);
5619 }
5620
5621 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5622 mask |= BIT(POWER_DOMAIN_AUDIO);
5623
5624 if (crtc_state->shared_dpll)
5625 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5626
5627 return mask;
5628 }
5629
5630 static u64
5631 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5632 struct intel_crtc_state *crtc_state)
5633 {
5634 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5635 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5636 enum intel_display_power_domain domain;
5637 u64 domains, new_domains, old_domains;
5638
5639 old_domains = intel_crtc->enabled_power_domains;
5640 intel_crtc->enabled_power_domains = new_domains =
5641 get_crtc_power_domains(crtc, crtc_state);
5642
5643 domains = new_domains & ~old_domains;
5644
5645 for_each_power_domain(domain, domains)
5646 intel_display_power_get(dev_priv, domain);
5647
5648 return old_domains & ~new_domains;
5649 }
5650
5651 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5652 u64 domains)
5653 {
5654 enum intel_display_power_domain domain;
5655
5656 for_each_power_domain(domain, domains)
5657 intel_display_power_put(dev_priv, domain);
5658 }
5659
5660 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5661 struct drm_atomic_state *old_state)
5662 {
5663 struct intel_atomic_state *old_intel_state =
5664 to_intel_atomic_state(old_state);
5665 struct drm_crtc *crtc = pipe_config->base.crtc;
5666 struct drm_device *dev = crtc->dev;
5667 struct drm_i915_private *dev_priv = to_i915(dev);
5668 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5669 int pipe = intel_crtc->pipe;
5670
5671 if (WARN_ON(intel_crtc->active))
5672 return;
5673
5674 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5675 intel_dp_set_m_n(intel_crtc, M1_N1);
5676
5677 intel_set_pipe_timings(intel_crtc);
5678 intel_set_pipe_src_size(intel_crtc);
5679
5680 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5681 struct drm_i915_private *dev_priv = to_i915(dev);
5682
5683 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5684 I915_WRITE(CHV_CANVAS(pipe), 0);
5685 }
5686
5687 i9xx_set_pipeconf(intel_crtc);
5688
5689 intel_crtc->active = true;
5690
5691 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5692
5693 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5694
5695 if (IS_CHERRYVIEW(dev_priv)) {
5696 chv_prepare_pll(intel_crtc, intel_crtc->config);
5697 chv_enable_pll(intel_crtc, intel_crtc->config);
5698 } else {
5699 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5700 vlv_enable_pll(intel_crtc, intel_crtc->config);
5701 }
5702
5703 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5704
5705 i9xx_pfit_enable(intel_crtc);
5706
5707 intel_color_load_luts(&pipe_config->base);
5708
5709 dev_priv->display.initial_watermarks(old_intel_state,
5710 pipe_config);
5711 intel_enable_pipe(intel_crtc);
5712
5713 assert_vblank_disabled(crtc);
5714 drm_crtc_vblank_on(crtc);
5715
5716 intel_encoders_enable(crtc, pipe_config, old_state);
5717 }
5718
5719 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5720 {
5721 struct drm_device *dev = crtc->base.dev;
5722 struct drm_i915_private *dev_priv = to_i915(dev);
5723
5724 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5725 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5726 }
5727
5728 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5729 struct drm_atomic_state *old_state)
5730 {
5731 struct intel_atomic_state *old_intel_state =
5732 to_intel_atomic_state(old_state);
5733 struct drm_crtc *crtc = pipe_config->base.crtc;
5734 struct drm_device *dev = crtc->dev;
5735 struct drm_i915_private *dev_priv = to_i915(dev);
5736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5737 enum pipe pipe = intel_crtc->pipe;
5738
5739 if (WARN_ON(intel_crtc->active))
5740 return;
5741
5742 i9xx_set_pll_dividers(intel_crtc);
5743
5744 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5745 intel_dp_set_m_n(intel_crtc, M1_N1);
5746
5747 intel_set_pipe_timings(intel_crtc);
5748 intel_set_pipe_src_size(intel_crtc);
5749
5750 i9xx_set_pipeconf(intel_crtc);
5751
5752 intel_crtc->active = true;
5753
5754 if (!IS_GEN2(dev_priv))
5755 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5756
5757 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5758
5759 i9xx_enable_pll(intel_crtc);
5760
5761 i9xx_pfit_enable(intel_crtc);
5762
5763 intel_color_load_luts(&pipe_config->base);
5764
5765 if (dev_priv->display.initial_watermarks != NULL)
5766 dev_priv->display.initial_watermarks(old_intel_state,
5767 intel_crtc->config);
5768 else
5769 intel_update_watermarks(intel_crtc);
5770 intel_enable_pipe(intel_crtc);
5771
5772 assert_vblank_disabled(crtc);
5773 drm_crtc_vblank_on(crtc);
5774
5775 intel_encoders_enable(crtc, pipe_config, old_state);
5776 }
5777
5778 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5779 {
5780 struct drm_device *dev = crtc->base.dev;
5781 struct drm_i915_private *dev_priv = to_i915(dev);
5782
5783 if (!crtc->config->gmch_pfit.control)
5784 return;
5785
5786 assert_pipe_disabled(dev_priv, crtc->pipe);
5787
5788 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5789 I915_READ(PFIT_CONTROL));
5790 I915_WRITE(PFIT_CONTROL, 0);
5791 }
5792
5793 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5794 struct drm_atomic_state *old_state)
5795 {
5796 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5797 struct drm_device *dev = crtc->dev;
5798 struct drm_i915_private *dev_priv = to_i915(dev);
5799 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5800 int pipe = intel_crtc->pipe;
5801
5802 /*
5803 * On gen2 planes are double buffered but the pipe isn't, so we must
5804 * wait for planes to fully turn off before disabling the pipe.
5805 */
5806 if (IS_GEN2(dev_priv))
5807 intel_wait_for_vblank(dev_priv, pipe);
5808
5809 intel_encoders_disable(crtc, old_crtc_state, old_state);
5810
5811 drm_crtc_vblank_off(crtc);
5812 assert_vblank_disabled(crtc);
5813
5814 intel_disable_pipe(intel_crtc);
5815
5816 i9xx_pfit_disable(intel_crtc);
5817
5818 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5819
5820 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5821 if (IS_CHERRYVIEW(dev_priv))
5822 chv_disable_pll(dev_priv, pipe);
5823 else if (IS_VALLEYVIEW(dev_priv))
5824 vlv_disable_pll(dev_priv, pipe);
5825 else
5826 i9xx_disable_pll(intel_crtc);
5827 }
5828
5829 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5830
5831 if (!IS_GEN2(dev_priv))
5832 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5833
5834 if (!dev_priv->display.initial_watermarks)
5835 intel_update_watermarks(intel_crtc);
5836
5837 /* clock the pipe down to 640x480@60 to potentially save power */
5838 if (IS_I830(dev_priv))
5839 i830_enable_pipe(dev_priv, pipe);
5840 }
5841
5842 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
5843 struct drm_modeset_acquire_ctx *ctx)
5844 {
5845 struct intel_encoder *encoder;
5846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5847 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5848 enum intel_display_power_domain domain;
5849 u64 domains;
5850 struct drm_atomic_state *state;
5851 struct intel_crtc_state *crtc_state;
5852 int ret;
5853
5854 if (!intel_crtc->active)
5855 return;
5856
5857 if (crtc->primary->state->visible) {
5858 WARN_ON(intel_crtc->flip_work);
5859
5860 intel_pre_disable_primary_noatomic(crtc);
5861
5862 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5863 crtc->primary->state->visible = false;
5864 }
5865
5866 state = drm_atomic_state_alloc(crtc->dev);
5867 if (!state) {
5868 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5869 crtc->base.id, crtc->name);
5870 return;
5871 }
5872
5873 state->acquire_ctx = ctx;
5874
5875 /* Everything's already locked, -EDEADLK can't happen. */
5876 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5877 ret = drm_atomic_add_affected_connectors(state, crtc);
5878
5879 WARN_ON(IS_ERR(crtc_state) || ret);
5880
5881 dev_priv->display.crtc_disable(crtc_state, state);
5882
5883 drm_atomic_state_put(state);
5884
5885 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5886 crtc->base.id, crtc->name);
5887
5888 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5889 crtc->state->active = false;
5890 intel_crtc->active = false;
5891 crtc->enabled = false;
5892 crtc->state->connector_mask = 0;
5893 crtc->state->encoder_mask = 0;
5894
5895 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5896 encoder->base.crtc = NULL;
5897
5898 intel_fbc_disable(intel_crtc);
5899 intel_update_watermarks(intel_crtc);
5900 intel_disable_shared_dpll(intel_crtc);
5901
5902 domains = intel_crtc->enabled_power_domains;
5903 for_each_power_domain(domain, domains)
5904 intel_display_power_put(dev_priv, domain);
5905 intel_crtc->enabled_power_domains = 0;
5906
5907 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5908 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
5909 }
5910
5911 /*
5912 * turn all crtc's off, but do not adjust state
5913 * This has to be paired with a call to intel_modeset_setup_hw_state.
5914 */
5915 int intel_display_suspend(struct drm_device *dev)
5916 {
5917 struct drm_i915_private *dev_priv = to_i915(dev);
5918 struct drm_atomic_state *state;
5919 int ret;
5920
5921 state = drm_atomic_helper_suspend(dev);
5922 ret = PTR_ERR_OR_ZERO(state);
5923 if (ret)
5924 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5925 else
5926 dev_priv->modeset_restore_state = state;
5927 return ret;
5928 }
5929
5930 void intel_encoder_destroy(struct drm_encoder *encoder)
5931 {
5932 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5933
5934 drm_encoder_cleanup(encoder);
5935 kfree(intel_encoder);
5936 }
5937
5938 /* Cross check the actual hw state with our own modeset state tracking (and it's
5939 * internal consistency). */
5940 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
5941 struct drm_connector_state *conn_state)
5942 {
5943 struct intel_connector *connector = to_intel_connector(conn_state->connector);
5944
5945 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5946 connector->base.base.id,
5947 connector->base.name);
5948
5949 if (connector->get_hw_state(connector)) {
5950 struct intel_encoder *encoder = connector->encoder;
5951
5952 I915_STATE_WARN(!crtc_state,
5953 "connector enabled without attached crtc\n");
5954
5955 if (!crtc_state)
5956 return;
5957
5958 I915_STATE_WARN(!crtc_state->active,
5959 "connector is active, but attached crtc isn't\n");
5960
5961 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
5962 return;
5963
5964 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
5965 "atomic encoder doesn't match attached encoder\n");
5966
5967 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
5968 "attached encoder crtc differs from connector crtc\n");
5969 } else {
5970 I915_STATE_WARN(crtc_state && crtc_state->active,
5971 "attached crtc is active, but connector isn't\n");
5972 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
5973 "best encoder set without crtc!\n");
5974 }
5975 }
5976
5977 int intel_connector_init(struct intel_connector *connector)
5978 {
5979 struct intel_digital_connector_state *conn_state;
5980
5981 /*
5982 * Allocate enough memory to hold intel_digital_connector_state,
5983 * This might be a few bytes too many, but for connectors that don't
5984 * need it we'll free the state and allocate a smaller one on the first
5985 * succesful commit anyway.
5986 */
5987 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
5988 if (!conn_state)
5989 return -ENOMEM;
5990
5991 __drm_atomic_helper_connector_reset(&connector->base,
5992 &conn_state->base);
5993
5994 return 0;
5995 }
5996
5997 struct intel_connector *intel_connector_alloc(void)
5998 {
5999 struct intel_connector *connector;
6000
6001 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6002 if (!connector)
6003 return NULL;
6004
6005 if (intel_connector_init(connector) < 0) {
6006 kfree(connector);
6007 return NULL;
6008 }
6009
6010 return connector;
6011 }
6012
6013 /* Simple connector->get_hw_state implementation for encoders that support only
6014 * one connector and no cloning and hence the encoder state determines the state
6015 * of the connector. */
6016 bool intel_connector_get_hw_state(struct intel_connector *connector)
6017 {
6018 enum pipe pipe = 0;
6019 struct intel_encoder *encoder = connector->encoder;
6020
6021 return encoder->get_hw_state(encoder, &pipe);
6022 }
6023
6024 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6025 {
6026 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6027 return crtc_state->fdi_lanes;
6028
6029 return 0;
6030 }
6031
6032 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6033 struct intel_crtc_state *pipe_config)
6034 {
6035 struct drm_i915_private *dev_priv = to_i915(dev);
6036 struct drm_atomic_state *state = pipe_config->base.state;
6037 struct intel_crtc *other_crtc;
6038 struct intel_crtc_state *other_crtc_state;
6039
6040 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6041 pipe_name(pipe), pipe_config->fdi_lanes);
6042 if (pipe_config->fdi_lanes > 4) {
6043 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6044 pipe_name(pipe), pipe_config->fdi_lanes);
6045 return -EINVAL;
6046 }
6047
6048 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6049 if (pipe_config->fdi_lanes > 2) {
6050 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6051 pipe_config->fdi_lanes);
6052 return -EINVAL;
6053 } else {
6054 return 0;
6055 }
6056 }
6057
6058 if (INTEL_INFO(dev_priv)->num_pipes == 2)
6059 return 0;
6060
6061 /* Ivybridge 3 pipe is really complicated */
6062 switch (pipe) {
6063 case PIPE_A:
6064 return 0;
6065 case PIPE_B:
6066 if (pipe_config->fdi_lanes <= 2)
6067 return 0;
6068
6069 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6070 other_crtc_state =
6071 intel_atomic_get_crtc_state(state, other_crtc);
6072 if (IS_ERR(other_crtc_state))
6073 return PTR_ERR(other_crtc_state);
6074
6075 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6076 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6077 pipe_name(pipe), pipe_config->fdi_lanes);
6078 return -EINVAL;
6079 }
6080 return 0;
6081 case PIPE_C:
6082 if (pipe_config->fdi_lanes > 2) {
6083 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6084 pipe_name(pipe), pipe_config->fdi_lanes);
6085 return -EINVAL;
6086 }
6087
6088 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6089 other_crtc_state =
6090 intel_atomic_get_crtc_state(state, other_crtc);
6091 if (IS_ERR(other_crtc_state))
6092 return PTR_ERR(other_crtc_state);
6093
6094 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6095 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6096 return -EINVAL;
6097 }
6098 return 0;
6099 default:
6100 BUG();
6101 }
6102 }
6103
6104 #define RETRY 1
6105 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6106 struct intel_crtc_state *pipe_config)
6107 {
6108 struct drm_device *dev = intel_crtc->base.dev;
6109 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6110 int lane, link_bw, fdi_dotclock, ret;
6111 bool needs_recompute = false;
6112
6113 retry:
6114 /* FDI is a binary signal running at ~2.7GHz, encoding
6115 * each output octet as 10 bits. The actual frequency
6116 * is stored as a divider into a 100MHz clock, and the
6117 * mode pixel clock is stored in units of 1KHz.
6118 * Hence the bw of each lane in terms of the mode signal
6119 * is:
6120 */
6121 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6122
6123 fdi_dotclock = adjusted_mode->crtc_clock;
6124
6125 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6126 pipe_config->pipe_bpp);
6127
6128 pipe_config->fdi_lanes = lane;
6129
6130 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6131 link_bw, &pipe_config->fdi_m_n, false);
6132
6133 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6134 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6135 pipe_config->pipe_bpp -= 2*3;
6136 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6137 pipe_config->pipe_bpp);
6138 needs_recompute = true;
6139 pipe_config->bw_constrained = true;
6140
6141 goto retry;
6142 }
6143
6144 if (needs_recompute)
6145 return RETRY;
6146
6147 return ret;
6148 }
6149
6150 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6151 struct intel_crtc_state *pipe_config)
6152 {
6153 if (pipe_config->pipe_bpp > 24)
6154 return false;
6155
6156 /* HSW can handle pixel rate up to cdclk? */
6157 if (IS_HASWELL(dev_priv))
6158 return true;
6159
6160 /*
6161 * We compare against max which means we must take
6162 * the increased cdclk requirement into account when
6163 * calculating the new cdclk.
6164 *
6165 * Should measure whether using a lower cdclk w/o IPS
6166 */
6167 return pipe_config->pixel_rate <=
6168 dev_priv->max_cdclk_freq * 95 / 100;
6169 }
6170
6171 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6172 struct intel_crtc_state *pipe_config)
6173 {
6174 struct drm_device *dev = crtc->base.dev;
6175 struct drm_i915_private *dev_priv = to_i915(dev);
6176
6177 pipe_config->ips_enabled = i915.enable_ips &&
6178 hsw_crtc_supports_ips(crtc) &&
6179 pipe_config_supports_ips(dev_priv, pipe_config);
6180 }
6181
6182 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6183 {
6184 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6185
6186 /* GDG double wide on either pipe, otherwise pipe A only */
6187 return INTEL_INFO(dev_priv)->gen < 4 &&
6188 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6189 }
6190
6191 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6192 {
6193 uint32_t pixel_rate;
6194
6195 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6196
6197 /*
6198 * We only use IF-ID interlacing. If we ever use
6199 * PF-ID we'll need to adjust the pixel_rate here.
6200 */
6201
6202 if (pipe_config->pch_pfit.enabled) {
6203 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6204 uint32_t pfit_size = pipe_config->pch_pfit.size;
6205
6206 pipe_w = pipe_config->pipe_src_w;
6207 pipe_h = pipe_config->pipe_src_h;
6208
6209 pfit_w = (pfit_size >> 16) & 0xFFFF;
6210 pfit_h = pfit_size & 0xFFFF;
6211 if (pipe_w < pfit_w)
6212 pipe_w = pfit_w;
6213 if (pipe_h < pfit_h)
6214 pipe_h = pfit_h;
6215
6216 if (WARN_ON(!pfit_w || !pfit_h))
6217 return pixel_rate;
6218
6219 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6220 pfit_w * pfit_h);
6221 }
6222
6223 return pixel_rate;
6224 }
6225
6226 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6227 {
6228 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6229
6230 if (HAS_GMCH_DISPLAY(dev_priv))
6231 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6232 crtc_state->pixel_rate =
6233 crtc_state->base.adjusted_mode.crtc_clock;
6234 else
6235 crtc_state->pixel_rate =
6236 ilk_pipe_pixel_rate(crtc_state);
6237 }
6238
6239 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6240 struct intel_crtc_state *pipe_config)
6241 {
6242 struct drm_device *dev = crtc->base.dev;
6243 struct drm_i915_private *dev_priv = to_i915(dev);
6244 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6245 int clock_limit = dev_priv->max_dotclk_freq;
6246
6247 if (INTEL_GEN(dev_priv) < 4) {
6248 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6249
6250 /*
6251 * Enable double wide mode when the dot clock
6252 * is > 90% of the (display) core speed.
6253 */
6254 if (intel_crtc_supports_double_wide(crtc) &&
6255 adjusted_mode->crtc_clock > clock_limit) {
6256 clock_limit = dev_priv->max_dotclk_freq;
6257 pipe_config->double_wide = true;
6258 }
6259 }
6260
6261 if (adjusted_mode->crtc_clock > clock_limit) {
6262 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6263 adjusted_mode->crtc_clock, clock_limit,
6264 yesno(pipe_config->double_wide));
6265 return -EINVAL;
6266 }
6267
6268 /*
6269 * Pipe horizontal size must be even in:
6270 * - DVO ganged mode
6271 * - LVDS dual channel mode
6272 * - Double wide pipe
6273 */
6274 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6275 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6276 pipe_config->pipe_src_w &= ~1;
6277
6278 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6279 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6280 */
6281 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6282 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6283 return -EINVAL;
6284
6285 intel_crtc_compute_pixel_rate(pipe_config);
6286
6287 if (HAS_IPS(dev_priv))
6288 hsw_compute_ips_config(crtc, pipe_config);
6289
6290 if (pipe_config->has_pch_encoder)
6291 return ironlake_fdi_compute_config(crtc, pipe_config);
6292
6293 return 0;
6294 }
6295
6296 static void
6297 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6298 {
6299 while (*num > DATA_LINK_M_N_MASK ||
6300 *den > DATA_LINK_M_N_MASK) {
6301 *num >>= 1;
6302 *den >>= 1;
6303 }
6304 }
6305
6306 static void compute_m_n(unsigned int m, unsigned int n,
6307 uint32_t *ret_m, uint32_t *ret_n,
6308 bool reduce_m_n)
6309 {
6310 /*
6311 * Reduce M/N as much as possible without loss in precision. Several DP
6312 * dongles in particular seem to be fussy about too large *link* M/N
6313 * values. The passed in values are more likely to have the least
6314 * significant bits zero than M after rounding below, so do this first.
6315 */
6316 if (reduce_m_n) {
6317 while ((m & 1) == 0 && (n & 1) == 0) {
6318 m >>= 1;
6319 n >>= 1;
6320 }
6321 }
6322
6323 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6324 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6325 intel_reduce_m_n_ratio(ret_m, ret_n);
6326 }
6327
6328 void
6329 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6330 int pixel_clock, int link_clock,
6331 struct intel_link_m_n *m_n,
6332 bool reduce_m_n)
6333 {
6334 m_n->tu = 64;
6335
6336 compute_m_n(bits_per_pixel * pixel_clock,
6337 link_clock * nlanes * 8,
6338 &m_n->gmch_m, &m_n->gmch_n,
6339 reduce_m_n);
6340
6341 compute_m_n(pixel_clock, link_clock,
6342 &m_n->link_m, &m_n->link_n,
6343 reduce_m_n);
6344 }
6345
6346 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6347 {
6348 if (i915.panel_use_ssc >= 0)
6349 return i915.panel_use_ssc != 0;
6350 return dev_priv->vbt.lvds_use_ssc
6351 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6352 }
6353
6354 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6355 {
6356 return (1 << dpll->n) << 16 | dpll->m2;
6357 }
6358
6359 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6360 {
6361 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6362 }
6363
6364 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6365 struct intel_crtc_state *crtc_state,
6366 struct dpll *reduced_clock)
6367 {
6368 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6369 u32 fp, fp2 = 0;
6370
6371 if (IS_PINEVIEW(dev_priv)) {
6372 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6373 if (reduced_clock)
6374 fp2 = pnv_dpll_compute_fp(reduced_clock);
6375 } else {
6376 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6377 if (reduced_clock)
6378 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6379 }
6380
6381 crtc_state->dpll_hw_state.fp0 = fp;
6382
6383 crtc->lowfreq_avail = false;
6384 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6385 reduced_clock) {
6386 crtc_state->dpll_hw_state.fp1 = fp2;
6387 crtc->lowfreq_avail = true;
6388 } else {
6389 crtc_state->dpll_hw_state.fp1 = fp;
6390 }
6391 }
6392
6393 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6394 pipe)
6395 {
6396 u32 reg_val;
6397
6398 /*
6399 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6400 * and set it to a reasonable value instead.
6401 */
6402 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6403 reg_val &= 0xffffff00;
6404 reg_val |= 0x00000030;
6405 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6406
6407 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6408 reg_val &= 0x00ffffff;
6409 reg_val |= 0x8c000000;
6410 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6411
6412 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6413 reg_val &= 0xffffff00;
6414 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6415
6416 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6417 reg_val &= 0x00ffffff;
6418 reg_val |= 0xb0000000;
6419 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6420 }
6421
6422 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6423 struct intel_link_m_n *m_n)
6424 {
6425 struct drm_device *dev = crtc->base.dev;
6426 struct drm_i915_private *dev_priv = to_i915(dev);
6427 int pipe = crtc->pipe;
6428
6429 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6430 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6431 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6432 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6433 }
6434
6435 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6436 struct intel_link_m_n *m_n,
6437 struct intel_link_m_n *m2_n2)
6438 {
6439 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6440 int pipe = crtc->pipe;
6441 enum transcoder transcoder = crtc->config->cpu_transcoder;
6442
6443 if (INTEL_GEN(dev_priv) >= 5) {
6444 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6445 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6446 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6447 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6448 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6449 * for gen < 8) and if DRRS is supported (to make sure the
6450 * registers are not unnecessarily accessed).
6451 */
6452 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6453 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6454 I915_WRITE(PIPE_DATA_M2(transcoder),
6455 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6456 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6457 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6458 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6459 }
6460 } else {
6461 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6462 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6463 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6464 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6465 }
6466 }
6467
6468 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6469 {
6470 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6471
6472 if (m_n == M1_N1) {
6473 dp_m_n = &crtc->config->dp_m_n;
6474 dp_m2_n2 = &crtc->config->dp_m2_n2;
6475 } else if (m_n == M2_N2) {
6476
6477 /*
6478 * M2_N2 registers are not supported. Hence m2_n2 divider value
6479 * needs to be programmed into M1_N1.
6480 */
6481 dp_m_n = &crtc->config->dp_m2_n2;
6482 } else {
6483 DRM_ERROR("Unsupported divider value\n");
6484 return;
6485 }
6486
6487 if (crtc->config->has_pch_encoder)
6488 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6489 else
6490 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6491 }
6492
6493 static void vlv_compute_dpll(struct intel_crtc *crtc,
6494 struct intel_crtc_state *pipe_config)
6495 {
6496 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6497 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6498 if (crtc->pipe != PIPE_A)
6499 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6500
6501 /* DPLL not used with DSI, but still need the rest set up */
6502 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6503 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6504 DPLL_EXT_BUFFER_ENABLE_VLV;
6505
6506 pipe_config->dpll_hw_state.dpll_md =
6507 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6508 }
6509
6510 static void chv_compute_dpll(struct intel_crtc *crtc,
6511 struct intel_crtc_state *pipe_config)
6512 {
6513 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6514 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6515 if (crtc->pipe != PIPE_A)
6516 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6517
6518 /* DPLL not used with DSI, but still need the rest set up */
6519 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6520 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6521
6522 pipe_config->dpll_hw_state.dpll_md =
6523 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6524 }
6525
6526 static void vlv_prepare_pll(struct intel_crtc *crtc,
6527 const struct intel_crtc_state *pipe_config)
6528 {
6529 struct drm_device *dev = crtc->base.dev;
6530 struct drm_i915_private *dev_priv = to_i915(dev);
6531 enum pipe pipe = crtc->pipe;
6532 u32 mdiv;
6533 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6534 u32 coreclk, reg_val;
6535
6536 /* Enable Refclk */
6537 I915_WRITE(DPLL(pipe),
6538 pipe_config->dpll_hw_state.dpll &
6539 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6540
6541 /* No need to actually set up the DPLL with DSI */
6542 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6543 return;
6544
6545 mutex_lock(&dev_priv->sb_lock);
6546
6547 bestn = pipe_config->dpll.n;
6548 bestm1 = pipe_config->dpll.m1;
6549 bestm2 = pipe_config->dpll.m2;
6550 bestp1 = pipe_config->dpll.p1;
6551 bestp2 = pipe_config->dpll.p2;
6552
6553 /* See eDP HDMI DPIO driver vbios notes doc */
6554
6555 /* PLL B needs special handling */
6556 if (pipe == PIPE_B)
6557 vlv_pllb_recal_opamp(dev_priv, pipe);
6558
6559 /* Set up Tx target for periodic Rcomp update */
6560 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6561
6562 /* Disable target IRef on PLL */
6563 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6564 reg_val &= 0x00ffffff;
6565 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6566
6567 /* Disable fast lock */
6568 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6569
6570 /* Set idtafcrecal before PLL is enabled */
6571 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6572 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6573 mdiv |= ((bestn << DPIO_N_SHIFT));
6574 mdiv |= (1 << DPIO_K_SHIFT);
6575
6576 /*
6577 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6578 * but we don't support that).
6579 * Note: don't use the DAC post divider as it seems unstable.
6580 */
6581 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6582 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6583
6584 mdiv |= DPIO_ENABLE_CALIBRATION;
6585 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6586
6587 /* Set HBR and RBR LPF coefficients */
6588 if (pipe_config->port_clock == 162000 ||
6589 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6590 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6591 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6592 0x009f0003);
6593 else
6594 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6595 0x00d0000f);
6596
6597 if (intel_crtc_has_dp_encoder(pipe_config)) {
6598 /* Use SSC source */
6599 if (pipe == PIPE_A)
6600 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6601 0x0df40000);
6602 else
6603 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6604 0x0df70000);
6605 } else { /* HDMI or VGA */
6606 /* Use bend source */
6607 if (pipe == PIPE_A)
6608 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6609 0x0df70000);
6610 else
6611 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6612 0x0df40000);
6613 }
6614
6615 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6616 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6617 if (intel_crtc_has_dp_encoder(crtc->config))
6618 coreclk |= 0x01000000;
6619 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6620
6621 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6622 mutex_unlock(&dev_priv->sb_lock);
6623 }
6624
6625 static void chv_prepare_pll(struct intel_crtc *crtc,
6626 const struct intel_crtc_state *pipe_config)
6627 {
6628 struct drm_device *dev = crtc->base.dev;
6629 struct drm_i915_private *dev_priv = to_i915(dev);
6630 enum pipe pipe = crtc->pipe;
6631 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6632 u32 loopfilter, tribuf_calcntr;
6633 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6634 u32 dpio_val;
6635 int vco;
6636
6637 /* Enable Refclk and SSC */
6638 I915_WRITE(DPLL(pipe),
6639 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6640
6641 /* No need to actually set up the DPLL with DSI */
6642 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6643 return;
6644
6645 bestn = pipe_config->dpll.n;
6646 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6647 bestm1 = pipe_config->dpll.m1;
6648 bestm2 = pipe_config->dpll.m2 >> 22;
6649 bestp1 = pipe_config->dpll.p1;
6650 bestp2 = pipe_config->dpll.p2;
6651 vco = pipe_config->dpll.vco;
6652 dpio_val = 0;
6653 loopfilter = 0;
6654
6655 mutex_lock(&dev_priv->sb_lock);
6656
6657 /* p1 and p2 divider */
6658 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6659 5 << DPIO_CHV_S1_DIV_SHIFT |
6660 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6661 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6662 1 << DPIO_CHV_K_DIV_SHIFT);
6663
6664 /* Feedback post-divider - m2 */
6665 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6666
6667 /* Feedback refclk divider - n and m1 */
6668 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6669 DPIO_CHV_M1_DIV_BY_2 |
6670 1 << DPIO_CHV_N_DIV_SHIFT);
6671
6672 /* M2 fraction division */
6673 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6674
6675 /* M2 fraction division enable */
6676 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6677 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6678 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6679 if (bestm2_frac)
6680 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6681 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6682
6683 /* Program digital lock detect threshold */
6684 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6685 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6686 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6687 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6688 if (!bestm2_frac)
6689 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6690 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6691
6692 /* Loop filter */
6693 if (vco == 5400000) {
6694 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6695 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6696 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6697 tribuf_calcntr = 0x9;
6698 } else if (vco <= 6200000) {
6699 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6700 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6701 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6702 tribuf_calcntr = 0x9;
6703 } else if (vco <= 6480000) {
6704 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6705 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6706 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6707 tribuf_calcntr = 0x8;
6708 } else {
6709 /* Not supported. Apply the same limits as in the max case */
6710 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6711 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6712 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6713 tribuf_calcntr = 0;
6714 }
6715 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6716
6717 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6718 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6719 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6720 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6721
6722 /* AFC Recal */
6723 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6724 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6725 DPIO_AFC_RECAL);
6726
6727 mutex_unlock(&dev_priv->sb_lock);
6728 }
6729
6730 /**
6731 * vlv_force_pll_on - forcibly enable just the PLL
6732 * @dev_priv: i915 private structure
6733 * @pipe: pipe PLL to enable
6734 * @dpll: PLL configuration
6735 *
6736 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6737 * in cases where we need the PLL enabled even when @pipe is not going to
6738 * be enabled.
6739 */
6740 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6741 const struct dpll *dpll)
6742 {
6743 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6744 struct intel_crtc_state *pipe_config;
6745
6746 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6747 if (!pipe_config)
6748 return -ENOMEM;
6749
6750 pipe_config->base.crtc = &crtc->base;
6751 pipe_config->pixel_multiplier = 1;
6752 pipe_config->dpll = *dpll;
6753
6754 if (IS_CHERRYVIEW(dev_priv)) {
6755 chv_compute_dpll(crtc, pipe_config);
6756 chv_prepare_pll(crtc, pipe_config);
6757 chv_enable_pll(crtc, pipe_config);
6758 } else {
6759 vlv_compute_dpll(crtc, pipe_config);
6760 vlv_prepare_pll(crtc, pipe_config);
6761 vlv_enable_pll(crtc, pipe_config);
6762 }
6763
6764 kfree(pipe_config);
6765
6766 return 0;
6767 }
6768
6769 /**
6770 * vlv_force_pll_off - forcibly disable just the PLL
6771 * @dev_priv: i915 private structure
6772 * @pipe: pipe PLL to disable
6773 *
6774 * Disable the PLL for @pipe. To be used in cases where we need
6775 * the PLL enabled even when @pipe is not going to be enabled.
6776 */
6777 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6778 {
6779 if (IS_CHERRYVIEW(dev_priv))
6780 chv_disable_pll(dev_priv, pipe);
6781 else
6782 vlv_disable_pll(dev_priv, pipe);
6783 }
6784
6785 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6786 struct intel_crtc_state *crtc_state,
6787 struct dpll *reduced_clock)
6788 {
6789 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6790 u32 dpll;
6791 struct dpll *clock = &crtc_state->dpll;
6792
6793 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6794
6795 dpll = DPLL_VGA_MODE_DIS;
6796
6797 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6798 dpll |= DPLLB_MODE_LVDS;
6799 else
6800 dpll |= DPLLB_MODE_DAC_SERIAL;
6801
6802 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6803 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6804 dpll |= (crtc_state->pixel_multiplier - 1)
6805 << SDVO_MULTIPLIER_SHIFT_HIRES;
6806 }
6807
6808 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6809 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6810 dpll |= DPLL_SDVO_HIGH_SPEED;
6811
6812 if (intel_crtc_has_dp_encoder(crtc_state))
6813 dpll |= DPLL_SDVO_HIGH_SPEED;
6814
6815 /* compute bitmask from p1 value */
6816 if (IS_PINEVIEW(dev_priv))
6817 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6818 else {
6819 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6820 if (IS_G4X(dev_priv) && reduced_clock)
6821 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6822 }
6823 switch (clock->p2) {
6824 case 5:
6825 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6826 break;
6827 case 7:
6828 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6829 break;
6830 case 10:
6831 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6832 break;
6833 case 14:
6834 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6835 break;
6836 }
6837 if (INTEL_GEN(dev_priv) >= 4)
6838 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6839
6840 if (crtc_state->sdvo_tv_clock)
6841 dpll |= PLL_REF_INPUT_TVCLKINBC;
6842 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6843 intel_panel_use_ssc(dev_priv))
6844 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6845 else
6846 dpll |= PLL_REF_INPUT_DREFCLK;
6847
6848 dpll |= DPLL_VCO_ENABLE;
6849 crtc_state->dpll_hw_state.dpll = dpll;
6850
6851 if (INTEL_GEN(dev_priv) >= 4) {
6852 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6853 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6854 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6855 }
6856 }
6857
6858 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6859 struct intel_crtc_state *crtc_state,
6860 struct dpll *reduced_clock)
6861 {
6862 struct drm_device *dev = crtc->base.dev;
6863 struct drm_i915_private *dev_priv = to_i915(dev);
6864 u32 dpll;
6865 struct dpll *clock = &crtc_state->dpll;
6866
6867 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6868
6869 dpll = DPLL_VGA_MODE_DIS;
6870
6871 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6872 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6873 } else {
6874 if (clock->p1 == 2)
6875 dpll |= PLL_P1_DIVIDE_BY_TWO;
6876 else
6877 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6878 if (clock->p2 == 4)
6879 dpll |= PLL_P2_DIVIDE_BY_4;
6880 }
6881
6882 if (!IS_I830(dev_priv) &&
6883 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6884 dpll |= DPLL_DVO_2X_MODE;
6885
6886 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6887 intel_panel_use_ssc(dev_priv))
6888 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6889 else
6890 dpll |= PLL_REF_INPUT_DREFCLK;
6891
6892 dpll |= DPLL_VCO_ENABLE;
6893 crtc_state->dpll_hw_state.dpll = dpll;
6894 }
6895
6896 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6897 {
6898 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6899 enum pipe pipe = intel_crtc->pipe;
6900 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6901 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6902 uint32_t crtc_vtotal, crtc_vblank_end;
6903 int vsyncshift = 0;
6904
6905 /* We need to be careful not to changed the adjusted mode, for otherwise
6906 * the hw state checker will get angry at the mismatch. */
6907 crtc_vtotal = adjusted_mode->crtc_vtotal;
6908 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6909
6910 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6911 /* the chip adds 2 halflines automatically */
6912 crtc_vtotal -= 1;
6913 crtc_vblank_end -= 1;
6914
6915 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6916 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6917 else
6918 vsyncshift = adjusted_mode->crtc_hsync_start -
6919 adjusted_mode->crtc_htotal / 2;
6920 if (vsyncshift < 0)
6921 vsyncshift += adjusted_mode->crtc_htotal;
6922 }
6923
6924 if (INTEL_GEN(dev_priv) > 3)
6925 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6926
6927 I915_WRITE(HTOTAL(cpu_transcoder),
6928 (adjusted_mode->crtc_hdisplay - 1) |
6929 ((adjusted_mode->crtc_htotal - 1) << 16));
6930 I915_WRITE(HBLANK(cpu_transcoder),
6931 (adjusted_mode->crtc_hblank_start - 1) |
6932 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6933 I915_WRITE(HSYNC(cpu_transcoder),
6934 (adjusted_mode->crtc_hsync_start - 1) |
6935 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6936
6937 I915_WRITE(VTOTAL(cpu_transcoder),
6938 (adjusted_mode->crtc_vdisplay - 1) |
6939 ((crtc_vtotal - 1) << 16));
6940 I915_WRITE(VBLANK(cpu_transcoder),
6941 (adjusted_mode->crtc_vblank_start - 1) |
6942 ((crtc_vblank_end - 1) << 16));
6943 I915_WRITE(VSYNC(cpu_transcoder),
6944 (adjusted_mode->crtc_vsync_start - 1) |
6945 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6946
6947 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6948 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6949 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6950 * bits. */
6951 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
6952 (pipe == PIPE_B || pipe == PIPE_C))
6953 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6954
6955 }
6956
6957 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
6958 {
6959 struct drm_device *dev = intel_crtc->base.dev;
6960 struct drm_i915_private *dev_priv = to_i915(dev);
6961 enum pipe pipe = intel_crtc->pipe;
6962
6963 /* pipesrc controls the size that is scaled from, which should
6964 * always be the user's requested size.
6965 */
6966 I915_WRITE(PIPESRC(pipe),
6967 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6968 (intel_crtc->config->pipe_src_h - 1));
6969 }
6970
6971 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6972 struct intel_crtc_state *pipe_config)
6973 {
6974 struct drm_device *dev = crtc->base.dev;
6975 struct drm_i915_private *dev_priv = to_i915(dev);
6976 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6977 uint32_t tmp;
6978
6979 tmp = I915_READ(HTOTAL(cpu_transcoder));
6980 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6981 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6982 tmp = I915_READ(HBLANK(cpu_transcoder));
6983 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6984 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6985 tmp = I915_READ(HSYNC(cpu_transcoder));
6986 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6987 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6988
6989 tmp = I915_READ(VTOTAL(cpu_transcoder));
6990 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6991 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6992 tmp = I915_READ(VBLANK(cpu_transcoder));
6993 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6994 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6995 tmp = I915_READ(VSYNC(cpu_transcoder));
6996 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6997 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6998
6999 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7000 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7001 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7002 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7003 }
7004 }
7005
7006 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7007 struct intel_crtc_state *pipe_config)
7008 {
7009 struct drm_device *dev = crtc->base.dev;
7010 struct drm_i915_private *dev_priv = to_i915(dev);
7011 u32 tmp;
7012
7013 tmp = I915_READ(PIPESRC(crtc->pipe));
7014 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7015 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7016
7017 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7018 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7019 }
7020
7021 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7022 struct intel_crtc_state *pipe_config)
7023 {
7024 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7025 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7026 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7027 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7028
7029 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7030 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7031 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7032 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7033
7034 mode->flags = pipe_config->base.adjusted_mode.flags;
7035 mode->type = DRM_MODE_TYPE_DRIVER;
7036
7037 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7038
7039 mode->hsync = drm_mode_hsync(mode);
7040 mode->vrefresh = drm_mode_vrefresh(mode);
7041 drm_mode_set_name(mode);
7042 }
7043
7044 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7045 {
7046 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7047 uint32_t pipeconf;
7048
7049 pipeconf = 0;
7050
7051 /* we keep both pipes enabled on 830 */
7052 if (IS_I830(dev_priv))
7053 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7054
7055 if (intel_crtc->config->double_wide)
7056 pipeconf |= PIPECONF_DOUBLE_WIDE;
7057
7058 /* only g4x and later have fancy bpc/dither controls */
7059 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7060 IS_CHERRYVIEW(dev_priv)) {
7061 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7062 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7063 pipeconf |= PIPECONF_DITHER_EN |
7064 PIPECONF_DITHER_TYPE_SP;
7065
7066 switch (intel_crtc->config->pipe_bpp) {
7067 case 18:
7068 pipeconf |= PIPECONF_6BPC;
7069 break;
7070 case 24:
7071 pipeconf |= PIPECONF_8BPC;
7072 break;
7073 case 30:
7074 pipeconf |= PIPECONF_10BPC;
7075 break;
7076 default:
7077 /* Case prevented by intel_choose_pipe_bpp_dither. */
7078 BUG();
7079 }
7080 }
7081
7082 if (HAS_PIPE_CXSR(dev_priv)) {
7083 if (intel_crtc->lowfreq_avail) {
7084 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7085 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7086 } else {
7087 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7088 }
7089 }
7090
7091 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7092 if (INTEL_GEN(dev_priv) < 4 ||
7093 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7094 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7095 else
7096 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7097 } else
7098 pipeconf |= PIPECONF_PROGRESSIVE;
7099
7100 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7101 intel_crtc->config->limited_color_range)
7102 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7103
7104 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7105 POSTING_READ(PIPECONF(intel_crtc->pipe));
7106 }
7107
7108 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7109 struct intel_crtc_state *crtc_state)
7110 {
7111 struct drm_device *dev = crtc->base.dev;
7112 struct drm_i915_private *dev_priv = to_i915(dev);
7113 const struct intel_limit *limit;
7114 int refclk = 48000;
7115
7116 memset(&crtc_state->dpll_hw_state, 0,
7117 sizeof(crtc_state->dpll_hw_state));
7118
7119 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7120 if (intel_panel_use_ssc(dev_priv)) {
7121 refclk = dev_priv->vbt.lvds_ssc_freq;
7122 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7123 }
7124
7125 limit = &intel_limits_i8xx_lvds;
7126 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7127 limit = &intel_limits_i8xx_dvo;
7128 } else {
7129 limit = &intel_limits_i8xx_dac;
7130 }
7131
7132 if (!crtc_state->clock_set &&
7133 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7134 refclk, NULL, &crtc_state->dpll)) {
7135 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7136 return -EINVAL;
7137 }
7138
7139 i8xx_compute_dpll(crtc, crtc_state, NULL);
7140
7141 return 0;
7142 }
7143
7144 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7145 struct intel_crtc_state *crtc_state)
7146 {
7147 struct drm_device *dev = crtc->base.dev;
7148 struct drm_i915_private *dev_priv = to_i915(dev);
7149 const struct intel_limit *limit;
7150 int refclk = 96000;
7151
7152 memset(&crtc_state->dpll_hw_state, 0,
7153 sizeof(crtc_state->dpll_hw_state));
7154
7155 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7156 if (intel_panel_use_ssc(dev_priv)) {
7157 refclk = dev_priv->vbt.lvds_ssc_freq;
7158 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7159 }
7160
7161 if (intel_is_dual_link_lvds(dev))
7162 limit = &intel_limits_g4x_dual_channel_lvds;
7163 else
7164 limit = &intel_limits_g4x_single_channel_lvds;
7165 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7166 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7167 limit = &intel_limits_g4x_hdmi;
7168 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7169 limit = &intel_limits_g4x_sdvo;
7170 } else {
7171 /* The option is for other outputs */
7172 limit = &intel_limits_i9xx_sdvo;
7173 }
7174
7175 if (!crtc_state->clock_set &&
7176 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7177 refclk, NULL, &crtc_state->dpll)) {
7178 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7179 return -EINVAL;
7180 }
7181
7182 i9xx_compute_dpll(crtc, crtc_state, NULL);
7183
7184 return 0;
7185 }
7186
7187 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7188 struct intel_crtc_state *crtc_state)
7189 {
7190 struct drm_device *dev = crtc->base.dev;
7191 struct drm_i915_private *dev_priv = to_i915(dev);
7192 const struct intel_limit *limit;
7193 int refclk = 96000;
7194
7195 memset(&crtc_state->dpll_hw_state, 0,
7196 sizeof(crtc_state->dpll_hw_state));
7197
7198 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7199 if (intel_panel_use_ssc(dev_priv)) {
7200 refclk = dev_priv->vbt.lvds_ssc_freq;
7201 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7202 }
7203
7204 limit = &intel_limits_pineview_lvds;
7205 } else {
7206 limit = &intel_limits_pineview_sdvo;
7207 }
7208
7209 if (!crtc_state->clock_set &&
7210 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7211 refclk, NULL, &crtc_state->dpll)) {
7212 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7213 return -EINVAL;
7214 }
7215
7216 i9xx_compute_dpll(crtc, crtc_state, NULL);
7217
7218 return 0;
7219 }
7220
7221 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7222 struct intel_crtc_state *crtc_state)
7223 {
7224 struct drm_device *dev = crtc->base.dev;
7225 struct drm_i915_private *dev_priv = to_i915(dev);
7226 const struct intel_limit *limit;
7227 int refclk = 96000;
7228
7229 memset(&crtc_state->dpll_hw_state, 0,
7230 sizeof(crtc_state->dpll_hw_state));
7231
7232 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7233 if (intel_panel_use_ssc(dev_priv)) {
7234 refclk = dev_priv->vbt.lvds_ssc_freq;
7235 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7236 }
7237
7238 limit = &intel_limits_i9xx_lvds;
7239 } else {
7240 limit = &intel_limits_i9xx_sdvo;
7241 }
7242
7243 if (!crtc_state->clock_set &&
7244 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7245 refclk, NULL, &crtc_state->dpll)) {
7246 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7247 return -EINVAL;
7248 }
7249
7250 i9xx_compute_dpll(crtc, crtc_state, NULL);
7251
7252 return 0;
7253 }
7254
7255 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7256 struct intel_crtc_state *crtc_state)
7257 {
7258 int refclk = 100000;
7259 const struct intel_limit *limit = &intel_limits_chv;
7260
7261 memset(&crtc_state->dpll_hw_state, 0,
7262 sizeof(crtc_state->dpll_hw_state));
7263
7264 if (!crtc_state->clock_set &&
7265 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7266 refclk, NULL, &crtc_state->dpll)) {
7267 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7268 return -EINVAL;
7269 }
7270
7271 chv_compute_dpll(crtc, crtc_state);
7272
7273 return 0;
7274 }
7275
7276 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7277 struct intel_crtc_state *crtc_state)
7278 {
7279 int refclk = 100000;
7280 const struct intel_limit *limit = &intel_limits_vlv;
7281
7282 memset(&crtc_state->dpll_hw_state, 0,
7283 sizeof(crtc_state->dpll_hw_state));
7284
7285 if (!crtc_state->clock_set &&
7286 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7287 refclk, NULL, &crtc_state->dpll)) {
7288 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7289 return -EINVAL;
7290 }
7291
7292 vlv_compute_dpll(crtc, crtc_state);
7293
7294 return 0;
7295 }
7296
7297 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7298 struct intel_crtc_state *pipe_config)
7299 {
7300 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7301 uint32_t tmp;
7302
7303 if (INTEL_GEN(dev_priv) <= 3 &&
7304 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7305 return;
7306
7307 tmp = I915_READ(PFIT_CONTROL);
7308 if (!(tmp & PFIT_ENABLE))
7309 return;
7310
7311 /* Check whether the pfit is attached to our pipe. */
7312 if (INTEL_GEN(dev_priv) < 4) {
7313 if (crtc->pipe != PIPE_B)
7314 return;
7315 } else {
7316 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7317 return;
7318 }
7319
7320 pipe_config->gmch_pfit.control = tmp;
7321 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7322 }
7323
7324 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7325 struct intel_crtc_state *pipe_config)
7326 {
7327 struct drm_device *dev = crtc->base.dev;
7328 struct drm_i915_private *dev_priv = to_i915(dev);
7329 int pipe = pipe_config->cpu_transcoder;
7330 struct dpll clock;
7331 u32 mdiv;
7332 int refclk = 100000;
7333
7334 /* In case of DSI, DPLL will not be used */
7335 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7336 return;
7337
7338 mutex_lock(&dev_priv->sb_lock);
7339 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7340 mutex_unlock(&dev_priv->sb_lock);
7341
7342 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7343 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7344 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7345 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7346 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7347
7348 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7349 }
7350
7351 static void
7352 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7353 struct intel_initial_plane_config *plane_config)
7354 {
7355 struct drm_device *dev = crtc->base.dev;
7356 struct drm_i915_private *dev_priv = to_i915(dev);
7357 u32 val, base, offset;
7358 int pipe = crtc->pipe, plane = crtc->plane;
7359 int fourcc, pixel_format;
7360 unsigned int aligned_height;
7361 struct drm_framebuffer *fb;
7362 struct intel_framebuffer *intel_fb;
7363
7364 val = I915_READ(DSPCNTR(plane));
7365 if (!(val & DISPLAY_PLANE_ENABLE))
7366 return;
7367
7368 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7369 if (!intel_fb) {
7370 DRM_DEBUG_KMS("failed to alloc fb\n");
7371 return;
7372 }
7373
7374 fb = &intel_fb->base;
7375
7376 fb->dev = dev;
7377
7378 if (INTEL_GEN(dev_priv) >= 4) {
7379 if (val & DISPPLANE_TILED) {
7380 plane_config->tiling = I915_TILING_X;
7381 fb->modifier = I915_FORMAT_MOD_X_TILED;
7382 }
7383 }
7384
7385 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7386 fourcc = i9xx_format_to_fourcc(pixel_format);
7387 fb->format = drm_format_info(fourcc);
7388
7389 if (INTEL_GEN(dev_priv) >= 4) {
7390 if (plane_config->tiling)
7391 offset = I915_READ(DSPTILEOFF(plane));
7392 else
7393 offset = I915_READ(DSPLINOFF(plane));
7394 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7395 } else {
7396 base = I915_READ(DSPADDR(plane));
7397 }
7398 plane_config->base = base;
7399
7400 val = I915_READ(PIPESRC(pipe));
7401 fb->width = ((val >> 16) & 0xfff) + 1;
7402 fb->height = ((val >> 0) & 0xfff) + 1;
7403
7404 val = I915_READ(DSPSTRIDE(pipe));
7405 fb->pitches[0] = val & 0xffffffc0;
7406
7407 aligned_height = intel_fb_align_height(fb, 0, fb->height);
7408
7409 plane_config->size = fb->pitches[0] * aligned_height;
7410
7411 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7412 pipe_name(pipe), plane, fb->width, fb->height,
7413 fb->format->cpp[0] * 8, base, fb->pitches[0],
7414 plane_config->size);
7415
7416 plane_config->fb = intel_fb;
7417 }
7418
7419 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7420 struct intel_crtc_state *pipe_config)
7421 {
7422 struct drm_device *dev = crtc->base.dev;
7423 struct drm_i915_private *dev_priv = to_i915(dev);
7424 int pipe = pipe_config->cpu_transcoder;
7425 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7426 struct dpll clock;
7427 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7428 int refclk = 100000;
7429
7430 /* In case of DSI, DPLL will not be used */
7431 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7432 return;
7433
7434 mutex_lock(&dev_priv->sb_lock);
7435 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7436 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7437 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7438 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7439 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7440 mutex_unlock(&dev_priv->sb_lock);
7441
7442 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7443 clock.m2 = (pll_dw0 & 0xff) << 22;
7444 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7445 clock.m2 |= pll_dw2 & 0x3fffff;
7446 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7447 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7448 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7449
7450 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7451 }
7452
7453 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7454 struct intel_crtc_state *pipe_config)
7455 {
7456 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7457 enum intel_display_power_domain power_domain;
7458 uint32_t tmp;
7459 bool ret;
7460
7461 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7462 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7463 return false;
7464
7465 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7466 pipe_config->shared_dpll = NULL;
7467
7468 ret = false;
7469
7470 tmp = I915_READ(PIPECONF(crtc->pipe));
7471 if (!(tmp & PIPECONF_ENABLE))
7472 goto out;
7473
7474 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7475 IS_CHERRYVIEW(dev_priv)) {
7476 switch (tmp & PIPECONF_BPC_MASK) {
7477 case PIPECONF_6BPC:
7478 pipe_config->pipe_bpp = 18;
7479 break;
7480 case PIPECONF_8BPC:
7481 pipe_config->pipe_bpp = 24;
7482 break;
7483 case PIPECONF_10BPC:
7484 pipe_config->pipe_bpp = 30;
7485 break;
7486 default:
7487 break;
7488 }
7489 }
7490
7491 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7492 (tmp & PIPECONF_COLOR_RANGE_SELECT))
7493 pipe_config->limited_color_range = true;
7494
7495 if (INTEL_GEN(dev_priv) < 4)
7496 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7497
7498 intel_get_pipe_timings(crtc, pipe_config);
7499 intel_get_pipe_src_size(crtc, pipe_config);
7500
7501 i9xx_get_pfit_config(crtc, pipe_config);
7502
7503 if (INTEL_GEN(dev_priv) >= 4) {
7504 /* No way to read it out on pipes B and C */
7505 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7506 tmp = dev_priv->chv_dpll_md[crtc->pipe];
7507 else
7508 tmp = I915_READ(DPLL_MD(crtc->pipe));
7509 pipe_config->pixel_multiplier =
7510 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7511 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7512 pipe_config->dpll_hw_state.dpll_md = tmp;
7513 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7514 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7515 tmp = I915_READ(DPLL(crtc->pipe));
7516 pipe_config->pixel_multiplier =
7517 ((tmp & SDVO_MULTIPLIER_MASK)
7518 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7519 } else {
7520 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7521 * port and will be fixed up in the encoder->get_config
7522 * function. */
7523 pipe_config->pixel_multiplier = 1;
7524 }
7525 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7526 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7527 /*
7528 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7529 * on 830. Filter it out here so that we don't
7530 * report errors due to that.
7531 */
7532 if (IS_I830(dev_priv))
7533 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7534
7535 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7536 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7537 } else {
7538 /* Mask out read-only status bits. */
7539 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7540 DPLL_PORTC_READY_MASK |
7541 DPLL_PORTB_READY_MASK);
7542 }
7543
7544 if (IS_CHERRYVIEW(dev_priv))
7545 chv_crtc_clock_get(crtc, pipe_config);
7546 else if (IS_VALLEYVIEW(dev_priv))
7547 vlv_crtc_clock_get(crtc, pipe_config);
7548 else
7549 i9xx_crtc_clock_get(crtc, pipe_config);
7550
7551 /*
7552 * Normally the dotclock is filled in by the encoder .get_config()
7553 * but in case the pipe is enabled w/o any ports we need a sane
7554 * default.
7555 */
7556 pipe_config->base.adjusted_mode.crtc_clock =
7557 pipe_config->port_clock / pipe_config->pixel_multiplier;
7558
7559 ret = true;
7560
7561 out:
7562 intel_display_power_put(dev_priv, power_domain);
7563
7564 return ret;
7565 }
7566
7567 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7568 {
7569 struct intel_encoder *encoder;
7570 int i;
7571 u32 val, final;
7572 bool has_lvds = false;
7573 bool has_cpu_edp = false;
7574 bool has_panel = false;
7575 bool has_ck505 = false;
7576 bool can_ssc = false;
7577 bool using_ssc_source = false;
7578
7579 /* We need to take the global config into account */
7580 for_each_intel_encoder(&dev_priv->drm, encoder) {
7581 switch (encoder->type) {
7582 case INTEL_OUTPUT_LVDS:
7583 has_panel = true;
7584 has_lvds = true;
7585 break;
7586 case INTEL_OUTPUT_EDP:
7587 has_panel = true;
7588 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7589 has_cpu_edp = true;
7590 break;
7591 default:
7592 break;
7593 }
7594 }
7595
7596 if (HAS_PCH_IBX(dev_priv)) {
7597 has_ck505 = dev_priv->vbt.display_clock_mode;
7598 can_ssc = has_ck505;
7599 } else {
7600 has_ck505 = false;
7601 can_ssc = true;
7602 }
7603
7604 /* Check if any DPLLs are using the SSC source */
7605 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7606 u32 temp = I915_READ(PCH_DPLL(i));
7607
7608 if (!(temp & DPLL_VCO_ENABLE))
7609 continue;
7610
7611 if ((temp & PLL_REF_INPUT_MASK) ==
7612 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7613 using_ssc_source = true;
7614 break;
7615 }
7616 }
7617
7618 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7619 has_panel, has_lvds, has_ck505, using_ssc_source);
7620
7621 /* Ironlake: try to setup display ref clock before DPLL
7622 * enabling. This is only under driver's control after
7623 * PCH B stepping, previous chipset stepping should be
7624 * ignoring this setting.
7625 */
7626 val = I915_READ(PCH_DREF_CONTROL);
7627
7628 /* As we must carefully and slowly disable/enable each source in turn,
7629 * compute the final state we want first and check if we need to
7630 * make any changes at all.
7631 */
7632 final = val;
7633 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7634 if (has_ck505)
7635 final |= DREF_NONSPREAD_CK505_ENABLE;
7636 else
7637 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7638
7639 final &= ~DREF_SSC_SOURCE_MASK;
7640 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7641 final &= ~DREF_SSC1_ENABLE;
7642
7643 if (has_panel) {
7644 final |= DREF_SSC_SOURCE_ENABLE;
7645
7646 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7647 final |= DREF_SSC1_ENABLE;
7648
7649 if (has_cpu_edp) {
7650 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7651 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7652 else
7653 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7654 } else
7655 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7656 } else if (using_ssc_source) {
7657 final |= DREF_SSC_SOURCE_ENABLE;
7658 final |= DREF_SSC1_ENABLE;
7659 }
7660
7661 if (final == val)
7662 return;
7663
7664 /* Always enable nonspread source */
7665 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7666
7667 if (has_ck505)
7668 val |= DREF_NONSPREAD_CK505_ENABLE;
7669 else
7670 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7671
7672 if (has_panel) {
7673 val &= ~DREF_SSC_SOURCE_MASK;
7674 val |= DREF_SSC_SOURCE_ENABLE;
7675
7676 /* SSC must be turned on before enabling the CPU output */
7677 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7678 DRM_DEBUG_KMS("Using SSC on panel\n");
7679 val |= DREF_SSC1_ENABLE;
7680 } else
7681 val &= ~DREF_SSC1_ENABLE;
7682
7683 /* Get SSC going before enabling the outputs */
7684 I915_WRITE(PCH_DREF_CONTROL, val);
7685 POSTING_READ(PCH_DREF_CONTROL);
7686 udelay(200);
7687
7688 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7689
7690 /* Enable CPU source on CPU attached eDP */
7691 if (has_cpu_edp) {
7692 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7693 DRM_DEBUG_KMS("Using SSC on eDP\n");
7694 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7695 } else
7696 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7697 } else
7698 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7699
7700 I915_WRITE(PCH_DREF_CONTROL, val);
7701 POSTING_READ(PCH_DREF_CONTROL);
7702 udelay(200);
7703 } else {
7704 DRM_DEBUG_KMS("Disabling CPU source output\n");
7705
7706 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7707
7708 /* Turn off CPU output */
7709 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7710
7711 I915_WRITE(PCH_DREF_CONTROL, val);
7712 POSTING_READ(PCH_DREF_CONTROL);
7713 udelay(200);
7714
7715 if (!using_ssc_source) {
7716 DRM_DEBUG_KMS("Disabling SSC source\n");
7717
7718 /* Turn off the SSC source */
7719 val &= ~DREF_SSC_SOURCE_MASK;
7720 val |= DREF_SSC_SOURCE_DISABLE;
7721
7722 /* Turn off SSC1 */
7723 val &= ~DREF_SSC1_ENABLE;
7724
7725 I915_WRITE(PCH_DREF_CONTROL, val);
7726 POSTING_READ(PCH_DREF_CONTROL);
7727 udelay(200);
7728 }
7729 }
7730
7731 BUG_ON(val != final);
7732 }
7733
7734 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7735 {
7736 uint32_t tmp;
7737
7738 tmp = I915_READ(SOUTH_CHICKEN2);
7739 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7740 I915_WRITE(SOUTH_CHICKEN2, tmp);
7741
7742 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7743 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7744 DRM_ERROR("FDI mPHY reset assert timeout\n");
7745
7746 tmp = I915_READ(SOUTH_CHICKEN2);
7747 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7748 I915_WRITE(SOUTH_CHICKEN2, tmp);
7749
7750 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7751 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7752 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7753 }
7754
7755 /* WaMPhyProgramming:hsw */
7756 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7757 {
7758 uint32_t tmp;
7759
7760 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7761 tmp &= ~(0xFF << 24);
7762 tmp |= (0x12 << 24);
7763 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7764
7765 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7766 tmp |= (1 << 11);
7767 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7768
7769 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7770 tmp |= (1 << 11);
7771 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7772
7773 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7774 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7775 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7776
7777 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7778 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7779 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7780
7781 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7782 tmp &= ~(7 << 13);
7783 tmp |= (5 << 13);
7784 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7785
7786 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7787 tmp &= ~(7 << 13);
7788 tmp |= (5 << 13);
7789 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7790
7791 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7792 tmp &= ~0xFF;
7793 tmp |= 0x1C;
7794 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7795
7796 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7797 tmp &= ~0xFF;
7798 tmp |= 0x1C;
7799 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7800
7801 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7802 tmp &= ~(0xFF << 16);
7803 tmp |= (0x1C << 16);
7804 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7805
7806 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7807 tmp &= ~(0xFF << 16);
7808 tmp |= (0x1C << 16);
7809 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7810
7811 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7812 tmp |= (1 << 27);
7813 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7814
7815 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7816 tmp |= (1 << 27);
7817 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7818
7819 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7820 tmp &= ~(0xF << 28);
7821 tmp |= (4 << 28);
7822 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7823
7824 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7825 tmp &= ~(0xF << 28);
7826 tmp |= (4 << 28);
7827 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7828 }
7829
7830 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7831 * Programming" based on the parameters passed:
7832 * - Sequence to enable CLKOUT_DP
7833 * - Sequence to enable CLKOUT_DP without spread
7834 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7835 */
7836 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7837 bool with_spread, bool with_fdi)
7838 {
7839 uint32_t reg, tmp;
7840
7841 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7842 with_spread = true;
7843 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7844 with_fdi, "LP PCH doesn't have FDI\n"))
7845 with_fdi = false;
7846
7847 mutex_lock(&dev_priv->sb_lock);
7848
7849 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7850 tmp &= ~SBI_SSCCTL_DISABLE;
7851 tmp |= SBI_SSCCTL_PATHALT;
7852 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7853
7854 udelay(24);
7855
7856 if (with_spread) {
7857 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7858 tmp &= ~SBI_SSCCTL_PATHALT;
7859 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7860
7861 if (with_fdi) {
7862 lpt_reset_fdi_mphy(dev_priv);
7863 lpt_program_fdi_mphy(dev_priv);
7864 }
7865 }
7866
7867 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7868 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7869 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7870 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7871
7872 mutex_unlock(&dev_priv->sb_lock);
7873 }
7874
7875 /* Sequence to disable CLKOUT_DP */
7876 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7877 {
7878 uint32_t reg, tmp;
7879
7880 mutex_lock(&dev_priv->sb_lock);
7881
7882 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7883 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7884 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7885 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7886
7887 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7888 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7889 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7890 tmp |= SBI_SSCCTL_PATHALT;
7891 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7892 udelay(32);
7893 }
7894 tmp |= SBI_SSCCTL_DISABLE;
7895 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7896 }
7897
7898 mutex_unlock(&dev_priv->sb_lock);
7899 }
7900
7901 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7902
7903 static const uint16_t sscdivintphase[] = {
7904 [BEND_IDX( 50)] = 0x3B23,
7905 [BEND_IDX( 45)] = 0x3B23,
7906 [BEND_IDX( 40)] = 0x3C23,
7907 [BEND_IDX( 35)] = 0x3C23,
7908 [BEND_IDX( 30)] = 0x3D23,
7909 [BEND_IDX( 25)] = 0x3D23,
7910 [BEND_IDX( 20)] = 0x3E23,
7911 [BEND_IDX( 15)] = 0x3E23,
7912 [BEND_IDX( 10)] = 0x3F23,
7913 [BEND_IDX( 5)] = 0x3F23,
7914 [BEND_IDX( 0)] = 0x0025,
7915 [BEND_IDX( -5)] = 0x0025,
7916 [BEND_IDX(-10)] = 0x0125,
7917 [BEND_IDX(-15)] = 0x0125,
7918 [BEND_IDX(-20)] = 0x0225,
7919 [BEND_IDX(-25)] = 0x0225,
7920 [BEND_IDX(-30)] = 0x0325,
7921 [BEND_IDX(-35)] = 0x0325,
7922 [BEND_IDX(-40)] = 0x0425,
7923 [BEND_IDX(-45)] = 0x0425,
7924 [BEND_IDX(-50)] = 0x0525,
7925 };
7926
7927 /*
7928 * Bend CLKOUT_DP
7929 * steps -50 to 50 inclusive, in steps of 5
7930 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7931 * change in clock period = -(steps / 10) * 5.787 ps
7932 */
7933 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
7934 {
7935 uint32_t tmp;
7936 int idx = BEND_IDX(steps);
7937
7938 if (WARN_ON(steps % 5 != 0))
7939 return;
7940
7941 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
7942 return;
7943
7944 mutex_lock(&dev_priv->sb_lock);
7945
7946 if (steps % 10 != 0)
7947 tmp = 0xAAAAAAAB;
7948 else
7949 tmp = 0x00000000;
7950 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
7951
7952 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
7953 tmp &= 0xffff0000;
7954 tmp |= sscdivintphase[idx];
7955 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
7956
7957 mutex_unlock(&dev_priv->sb_lock);
7958 }
7959
7960 #undef BEND_IDX
7961
7962 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
7963 {
7964 struct intel_encoder *encoder;
7965 bool has_vga = false;
7966
7967 for_each_intel_encoder(&dev_priv->drm, encoder) {
7968 switch (encoder->type) {
7969 case INTEL_OUTPUT_ANALOG:
7970 has_vga = true;
7971 break;
7972 default:
7973 break;
7974 }
7975 }
7976
7977 if (has_vga) {
7978 lpt_bend_clkout_dp(dev_priv, 0);
7979 lpt_enable_clkout_dp(dev_priv, true, true);
7980 } else {
7981 lpt_disable_clkout_dp(dev_priv);
7982 }
7983 }
7984
7985 /*
7986 * Initialize reference clocks when the driver loads
7987 */
7988 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
7989 {
7990 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
7991 ironlake_init_pch_refclk(dev_priv);
7992 else if (HAS_PCH_LPT(dev_priv))
7993 lpt_init_pch_refclk(dev_priv);
7994 }
7995
7996 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7997 {
7998 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
7999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8000 int pipe = intel_crtc->pipe;
8001 uint32_t val;
8002
8003 val = 0;
8004
8005 switch (intel_crtc->config->pipe_bpp) {
8006 case 18:
8007 val |= PIPECONF_6BPC;
8008 break;
8009 case 24:
8010 val |= PIPECONF_8BPC;
8011 break;
8012 case 30:
8013 val |= PIPECONF_10BPC;
8014 break;
8015 case 36:
8016 val |= PIPECONF_12BPC;
8017 break;
8018 default:
8019 /* Case prevented by intel_choose_pipe_bpp_dither. */
8020 BUG();
8021 }
8022
8023 if (intel_crtc->config->dither)
8024 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8025
8026 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8027 val |= PIPECONF_INTERLACED_ILK;
8028 else
8029 val |= PIPECONF_PROGRESSIVE;
8030
8031 if (intel_crtc->config->limited_color_range)
8032 val |= PIPECONF_COLOR_RANGE_SELECT;
8033
8034 I915_WRITE(PIPECONF(pipe), val);
8035 POSTING_READ(PIPECONF(pipe));
8036 }
8037
8038 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8039 {
8040 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8042 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8043 u32 val = 0;
8044
8045 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8046 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8047
8048 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8049 val |= PIPECONF_INTERLACED_ILK;
8050 else
8051 val |= PIPECONF_PROGRESSIVE;
8052
8053 I915_WRITE(PIPECONF(cpu_transcoder), val);
8054 POSTING_READ(PIPECONF(cpu_transcoder));
8055 }
8056
8057 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8058 {
8059 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8061
8062 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8063 u32 val = 0;
8064
8065 switch (intel_crtc->config->pipe_bpp) {
8066 case 18:
8067 val |= PIPEMISC_DITHER_6_BPC;
8068 break;
8069 case 24:
8070 val |= PIPEMISC_DITHER_8_BPC;
8071 break;
8072 case 30:
8073 val |= PIPEMISC_DITHER_10_BPC;
8074 break;
8075 case 36:
8076 val |= PIPEMISC_DITHER_12_BPC;
8077 break;
8078 default:
8079 /* Case prevented by pipe_config_set_bpp. */
8080 BUG();
8081 }
8082
8083 if (intel_crtc->config->dither)
8084 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8085
8086 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8087 }
8088 }
8089
8090 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8091 {
8092 /*
8093 * Account for spread spectrum to avoid
8094 * oversubscribing the link. Max center spread
8095 * is 2.5%; use 5% for safety's sake.
8096 */
8097 u32 bps = target_clock * bpp * 21 / 20;
8098 return DIV_ROUND_UP(bps, link_bw * 8);
8099 }
8100
8101 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8102 {
8103 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8104 }
8105
8106 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8107 struct intel_crtc_state *crtc_state,
8108 struct dpll *reduced_clock)
8109 {
8110 struct drm_crtc *crtc = &intel_crtc->base;
8111 struct drm_device *dev = crtc->dev;
8112 struct drm_i915_private *dev_priv = to_i915(dev);
8113 u32 dpll, fp, fp2;
8114 int factor;
8115
8116 /* Enable autotuning of the PLL clock (if permissible) */
8117 factor = 21;
8118 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8119 if ((intel_panel_use_ssc(dev_priv) &&
8120 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8121 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8122 factor = 25;
8123 } else if (crtc_state->sdvo_tv_clock)
8124 factor = 20;
8125
8126 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8127
8128 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8129 fp |= FP_CB_TUNE;
8130
8131 if (reduced_clock) {
8132 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8133
8134 if (reduced_clock->m < factor * reduced_clock->n)
8135 fp2 |= FP_CB_TUNE;
8136 } else {
8137 fp2 = fp;
8138 }
8139
8140 dpll = 0;
8141
8142 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8143 dpll |= DPLLB_MODE_LVDS;
8144 else
8145 dpll |= DPLLB_MODE_DAC_SERIAL;
8146
8147 dpll |= (crtc_state->pixel_multiplier - 1)
8148 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8149
8150 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8151 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8152 dpll |= DPLL_SDVO_HIGH_SPEED;
8153
8154 if (intel_crtc_has_dp_encoder(crtc_state))
8155 dpll |= DPLL_SDVO_HIGH_SPEED;
8156
8157 /*
8158 * The high speed IO clock is only really required for
8159 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8160 * possible to share the DPLL between CRT and HDMI. Enabling
8161 * the clock needlessly does no real harm, except use up a
8162 * bit of power potentially.
8163 *
8164 * We'll limit this to IVB with 3 pipes, since it has only two
8165 * DPLLs and so DPLL sharing is the only way to get three pipes
8166 * driving PCH ports at the same time. On SNB we could do this,
8167 * and potentially avoid enabling the second DPLL, but it's not
8168 * clear if it''s a win or loss power wise. No point in doing
8169 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8170 */
8171 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8172 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8173 dpll |= DPLL_SDVO_HIGH_SPEED;
8174
8175 /* compute bitmask from p1 value */
8176 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8177 /* also FPA1 */
8178 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8179
8180 switch (crtc_state->dpll.p2) {
8181 case 5:
8182 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8183 break;
8184 case 7:
8185 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8186 break;
8187 case 10:
8188 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8189 break;
8190 case 14:
8191 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8192 break;
8193 }
8194
8195 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8196 intel_panel_use_ssc(dev_priv))
8197 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8198 else
8199 dpll |= PLL_REF_INPUT_DREFCLK;
8200
8201 dpll |= DPLL_VCO_ENABLE;
8202
8203 crtc_state->dpll_hw_state.dpll = dpll;
8204 crtc_state->dpll_hw_state.fp0 = fp;
8205 crtc_state->dpll_hw_state.fp1 = fp2;
8206 }
8207
8208 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8209 struct intel_crtc_state *crtc_state)
8210 {
8211 struct drm_device *dev = crtc->base.dev;
8212 struct drm_i915_private *dev_priv = to_i915(dev);
8213 const struct intel_limit *limit;
8214 int refclk = 120000;
8215
8216 memset(&crtc_state->dpll_hw_state, 0,
8217 sizeof(crtc_state->dpll_hw_state));
8218
8219 crtc->lowfreq_avail = false;
8220
8221 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8222 if (!crtc_state->has_pch_encoder)
8223 return 0;
8224
8225 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8226 if (intel_panel_use_ssc(dev_priv)) {
8227 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8228 dev_priv->vbt.lvds_ssc_freq);
8229 refclk = dev_priv->vbt.lvds_ssc_freq;
8230 }
8231
8232 if (intel_is_dual_link_lvds(dev)) {
8233 if (refclk == 100000)
8234 limit = &intel_limits_ironlake_dual_lvds_100m;
8235 else
8236 limit = &intel_limits_ironlake_dual_lvds;
8237 } else {
8238 if (refclk == 100000)
8239 limit = &intel_limits_ironlake_single_lvds_100m;
8240 else
8241 limit = &intel_limits_ironlake_single_lvds;
8242 }
8243 } else {
8244 limit = &intel_limits_ironlake_dac;
8245 }
8246
8247 if (!crtc_state->clock_set &&
8248 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8249 refclk, NULL, &crtc_state->dpll)) {
8250 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8251 return -EINVAL;
8252 }
8253
8254 ironlake_compute_dpll(crtc, crtc_state, NULL);
8255
8256 if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8257 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8258 pipe_name(crtc->pipe));
8259 return -EINVAL;
8260 }
8261
8262 return 0;
8263 }
8264
8265 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8266 struct intel_link_m_n *m_n)
8267 {
8268 struct drm_device *dev = crtc->base.dev;
8269 struct drm_i915_private *dev_priv = to_i915(dev);
8270 enum pipe pipe = crtc->pipe;
8271
8272 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8273 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8274 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8275 & ~TU_SIZE_MASK;
8276 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8277 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8278 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8279 }
8280
8281 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8282 enum transcoder transcoder,
8283 struct intel_link_m_n *m_n,
8284 struct intel_link_m_n *m2_n2)
8285 {
8286 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8287 enum pipe pipe = crtc->pipe;
8288
8289 if (INTEL_GEN(dev_priv) >= 5) {
8290 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8291 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8292 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8293 & ~TU_SIZE_MASK;
8294 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8295 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8296 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8297 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8298 * gen < 8) and if DRRS is supported (to make sure the
8299 * registers are not unnecessarily read).
8300 */
8301 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8302 crtc->config->has_drrs) {
8303 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8304 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8305 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8306 & ~TU_SIZE_MASK;
8307 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8308 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8309 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8310 }
8311 } else {
8312 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8313 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8314 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8315 & ~TU_SIZE_MASK;
8316 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8317 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8318 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8319 }
8320 }
8321
8322 void intel_dp_get_m_n(struct intel_crtc *crtc,
8323 struct intel_crtc_state *pipe_config)
8324 {
8325 if (pipe_config->has_pch_encoder)
8326 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8327 else
8328 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8329 &pipe_config->dp_m_n,
8330 &pipe_config->dp_m2_n2);
8331 }
8332
8333 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8334 struct intel_crtc_state *pipe_config)
8335 {
8336 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8337 &pipe_config->fdi_m_n, NULL);
8338 }
8339
8340 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8341 struct intel_crtc_state *pipe_config)
8342 {
8343 struct drm_device *dev = crtc->base.dev;
8344 struct drm_i915_private *dev_priv = to_i915(dev);
8345 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8346 uint32_t ps_ctrl = 0;
8347 int id = -1;
8348 int i;
8349
8350 /* find scaler attached to this pipe */
8351 for (i = 0; i < crtc->num_scalers; i++) {
8352 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8353 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8354 id = i;
8355 pipe_config->pch_pfit.enabled = true;
8356 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8357 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8358 break;
8359 }
8360 }
8361
8362 scaler_state->scaler_id = id;
8363 if (id >= 0) {
8364 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8365 } else {
8366 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8367 }
8368 }
8369
8370 static void
8371 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8372 struct intel_initial_plane_config *plane_config)
8373 {
8374 struct drm_device *dev = crtc->base.dev;
8375 struct drm_i915_private *dev_priv = to_i915(dev);
8376 u32 val, base, offset, stride_mult, tiling;
8377 int pipe = crtc->pipe;
8378 int fourcc, pixel_format;
8379 unsigned int aligned_height;
8380 struct drm_framebuffer *fb;
8381 struct intel_framebuffer *intel_fb;
8382
8383 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8384 if (!intel_fb) {
8385 DRM_DEBUG_KMS("failed to alloc fb\n");
8386 return;
8387 }
8388
8389 fb = &intel_fb->base;
8390
8391 fb->dev = dev;
8392
8393 val = I915_READ(PLANE_CTL(pipe, 0));
8394 if (!(val & PLANE_CTL_ENABLE))
8395 goto error;
8396
8397 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8398 fourcc = skl_format_to_fourcc(pixel_format,
8399 val & PLANE_CTL_ORDER_RGBX,
8400 val & PLANE_CTL_ALPHA_MASK);
8401 fb->format = drm_format_info(fourcc);
8402
8403 tiling = val & PLANE_CTL_TILED_MASK;
8404 switch (tiling) {
8405 case PLANE_CTL_TILED_LINEAR:
8406 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8407 break;
8408 case PLANE_CTL_TILED_X:
8409 plane_config->tiling = I915_TILING_X;
8410 fb->modifier = I915_FORMAT_MOD_X_TILED;
8411 break;
8412 case PLANE_CTL_TILED_Y:
8413 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8414 break;
8415 case PLANE_CTL_TILED_YF:
8416 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8417 break;
8418 default:
8419 MISSING_CASE(tiling);
8420 goto error;
8421 }
8422
8423 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8424 plane_config->base = base;
8425
8426 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8427
8428 val = I915_READ(PLANE_SIZE(pipe, 0));
8429 fb->height = ((val >> 16) & 0xfff) + 1;
8430 fb->width = ((val >> 0) & 0x1fff) + 1;
8431
8432 val = I915_READ(PLANE_STRIDE(pipe, 0));
8433 stride_mult = intel_fb_stride_alignment(fb, 0);
8434 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8435
8436 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8437
8438 plane_config->size = fb->pitches[0] * aligned_height;
8439
8440 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8441 pipe_name(pipe), fb->width, fb->height,
8442 fb->format->cpp[0] * 8, base, fb->pitches[0],
8443 plane_config->size);
8444
8445 plane_config->fb = intel_fb;
8446 return;
8447
8448 error:
8449 kfree(intel_fb);
8450 }
8451
8452 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8453 struct intel_crtc_state *pipe_config)
8454 {
8455 struct drm_device *dev = crtc->base.dev;
8456 struct drm_i915_private *dev_priv = to_i915(dev);
8457 uint32_t tmp;
8458
8459 tmp = I915_READ(PF_CTL(crtc->pipe));
8460
8461 if (tmp & PF_ENABLE) {
8462 pipe_config->pch_pfit.enabled = true;
8463 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8464 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8465
8466 /* We currently do not free assignements of panel fitters on
8467 * ivb/hsw (since we don't use the higher upscaling modes which
8468 * differentiates them) so just WARN about this case for now. */
8469 if (IS_GEN7(dev_priv)) {
8470 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8471 PF_PIPE_SEL_IVB(crtc->pipe));
8472 }
8473 }
8474 }
8475
8476 static void
8477 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8478 struct intel_initial_plane_config *plane_config)
8479 {
8480 struct drm_device *dev = crtc->base.dev;
8481 struct drm_i915_private *dev_priv = to_i915(dev);
8482 u32 val, base, offset;
8483 int pipe = crtc->pipe;
8484 int fourcc, pixel_format;
8485 unsigned int aligned_height;
8486 struct drm_framebuffer *fb;
8487 struct intel_framebuffer *intel_fb;
8488
8489 val = I915_READ(DSPCNTR(pipe));
8490 if (!(val & DISPLAY_PLANE_ENABLE))
8491 return;
8492
8493 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8494 if (!intel_fb) {
8495 DRM_DEBUG_KMS("failed to alloc fb\n");
8496 return;
8497 }
8498
8499 fb = &intel_fb->base;
8500
8501 fb->dev = dev;
8502
8503 if (INTEL_GEN(dev_priv) >= 4) {
8504 if (val & DISPPLANE_TILED) {
8505 plane_config->tiling = I915_TILING_X;
8506 fb->modifier = I915_FORMAT_MOD_X_TILED;
8507 }
8508 }
8509
8510 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8511 fourcc = i9xx_format_to_fourcc(pixel_format);
8512 fb->format = drm_format_info(fourcc);
8513
8514 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8515 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8516 offset = I915_READ(DSPOFFSET(pipe));
8517 } else {
8518 if (plane_config->tiling)
8519 offset = I915_READ(DSPTILEOFF(pipe));
8520 else
8521 offset = I915_READ(DSPLINOFF(pipe));
8522 }
8523 plane_config->base = base;
8524
8525 val = I915_READ(PIPESRC(pipe));
8526 fb->width = ((val >> 16) & 0xfff) + 1;
8527 fb->height = ((val >> 0) & 0xfff) + 1;
8528
8529 val = I915_READ(DSPSTRIDE(pipe));
8530 fb->pitches[0] = val & 0xffffffc0;
8531
8532 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8533
8534 plane_config->size = fb->pitches[0] * aligned_height;
8535
8536 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8537 pipe_name(pipe), fb->width, fb->height,
8538 fb->format->cpp[0] * 8, base, fb->pitches[0],
8539 plane_config->size);
8540
8541 plane_config->fb = intel_fb;
8542 }
8543
8544 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8545 struct intel_crtc_state *pipe_config)
8546 {
8547 struct drm_device *dev = crtc->base.dev;
8548 struct drm_i915_private *dev_priv = to_i915(dev);
8549 enum intel_display_power_domain power_domain;
8550 uint32_t tmp;
8551 bool ret;
8552
8553 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8554 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8555 return false;
8556
8557 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8558 pipe_config->shared_dpll = NULL;
8559
8560 ret = false;
8561 tmp = I915_READ(PIPECONF(crtc->pipe));
8562 if (!(tmp & PIPECONF_ENABLE))
8563 goto out;
8564
8565 switch (tmp & PIPECONF_BPC_MASK) {
8566 case PIPECONF_6BPC:
8567 pipe_config->pipe_bpp = 18;
8568 break;
8569 case PIPECONF_8BPC:
8570 pipe_config->pipe_bpp = 24;
8571 break;
8572 case PIPECONF_10BPC:
8573 pipe_config->pipe_bpp = 30;
8574 break;
8575 case PIPECONF_12BPC:
8576 pipe_config->pipe_bpp = 36;
8577 break;
8578 default:
8579 break;
8580 }
8581
8582 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8583 pipe_config->limited_color_range = true;
8584
8585 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8586 struct intel_shared_dpll *pll;
8587 enum intel_dpll_id pll_id;
8588
8589 pipe_config->has_pch_encoder = true;
8590
8591 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8592 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8593 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8594
8595 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8596
8597 if (HAS_PCH_IBX(dev_priv)) {
8598 /*
8599 * The pipe->pch transcoder and pch transcoder->pll
8600 * mapping is fixed.
8601 */
8602 pll_id = (enum intel_dpll_id) crtc->pipe;
8603 } else {
8604 tmp = I915_READ(PCH_DPLL_SEL);
8605 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8606 pll_id = DPLL_ID_PCH_PLL_B;
8607 else
8608 pll_id= DPLL_ID_PCH_PLL_A;
8609 }
8610
8611 pipe_config->shared_dpll =
8612 intel_get_shared_dpll_by_id(dev_priv, pll_id);
8613 pll = pipe_config->shared_dpll;
8614
8615 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8616 &pipe_config->dpll_hw_state));
8617
8618 tmp = pipe_config->dpll_hw_state.dpll;
8619 pipe_config->pixel_multiplier =
8620 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8621 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8622
8623 ironlake_pch_clock_get(crtc, pipe_config);
8624 } else {
8625 pipe_config->pixel_multiplier = 1;
8626 }
8627
8628 intel_get_pipe_timings(crtc, pipe_config);
8629 intel_get_pipe_src_size(crtc, pipe_config);
8630
8631 ironlake_get_pfit_config(crtc, pipe_config);
8632
8633 ret = true;
8634
8635 out:
8636 intel_display_power_put(dev_priv, power_domain);
8637
8638 return ret;
8639 }
8640
8641 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8642 {
8643 struct drm_device *dev = &dev_priv->drm;
8644 struct intel_crtc *crtc;
8645
8646 for_each_intel_crtc(dev, crtc)
8647 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8648 pipe_name(crtc->pipe));
8649
8650 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8651 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8652 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8653 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8654 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8655 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8656 "CPU PWM1 enabled\n");
8657 if (IS_HASWELL(dev_priv))
8658 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8659 "CPU PWM2 enabled\n");
8660 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8661 "PCH PWM1 enabled\n");
8662 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8663 "Utility pin enabled\n");
8664 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8665
8666 /*
8667 * In theory we can still leave IRQs enabled, as long as only the HPD
8668 * interrupts remain enabled. We used to check for that, but since it's
8669 * gen-specific and since we only disable LCPLL after we fully disable
8670 * the interrupts, the check below should be enough.
8671 */
8672 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8673 }
8674
8675 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8676 {
8677 if (IS_HASWELL(dev_priv))
8678 return I915_READ(D_COMP_HSW);
8679 else
8680 return I915_READ(D_COMP_BDW);
8681 }
8682
8683 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8684 {
8685 if (IS_HASWELL(dev_priv)) {
8686 mutex_lock(&dev_priv->rps.hw_lock);
8687 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8688 val))
8689 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8690 mutex_unlock(&dev_priv->rps.hw_lock);
8691 } else {
8692 I915_WRITE(D_COMP_BDW, val);
8693 POSTING_READ(D_COMP_BDW);
8694 }
8695 }
8696
8697 /*
8698 * This function implements pieces of two sequences from BSpec:
8699 * - Sequence for display software to disable LCPLL
8700 * - Sequence for display software to allow package C8+
8701 * The steps implemented here are just the steps that actually touch the LCPLL
8702 * register. Callers should take care of disabling all the display engine
8703 * functions, doing the mode unset, fixing interrupts, etc.
8704 */
8705 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8706 bool switch_to_fclk, bool allow_power_down)
8707 {
8708 uint32_t val;
8709
8710 assert_can_disable_lcpll(dev_priv);
8711
8712 val = I915_READ(LCPLL_CTL);
8713
8714 if (switch_to_fclk) {
8715 val |= LCPLL_CD_SOURCE_FCLK;
8716 I915_WRITE(LCPLL_CTL, val);
8717
8718 if (wait_for_us(I915_READ(LCPLL_CTL) &
8719 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8720 DRM_ERROR("Switching to FCLK failed\n");
8721
8722 val = I915_READ(LCPLL_CTL);
8723 }
8724
8725 val |= LCPLL_PLL_DISABLE;
8726 I915_WRITE(LCPLL_CTL, val);
8727 POSTING_READ(LCPLL_CTL);
8728
8729 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8730 DRM_ERROR("LCPLL still locked\n");
8731
8732 val = hsw_read_dcomp(dev_priv);
8733 val |= D_COMP_COMP_DISABLE;
8734 hsw_write_dcomp(dev_priv, val);
8735 ndelay(100);
8736
8737 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8738 1))
8739 DRM_ERROR("D_COMP RCOMP still in progress\n");
8740
8741 if (allow_power_down) {
8742 val = I915_READ(LCPLL_CTL);
8743 val |= LCPLL_POWER_DOWN_ALLOW;
8744 I915_WRITE(LCPLL_CTL, val);
8745 POSTING_READ(LCPLL_CTL);
8746 }
8747 }
8748
8749 /*
8750 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8751 * source.
8752 */
8753 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8754 {
8755 uint32_t val;
8756
8757 val = I915_READ(LCPLL_CTL);
8758
8759 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8760 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8761 return;
8762
8763 /*
8764 * Make sure we're not on PC8 state before disabling PC8, otherwise
8765 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8766 */
8767 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8768
8769 if (val & LCPLL_POWER_DOWN_ALLOW) {
8770 val &= ~LCPLL_POWER_DOWN_ALLOW;
8771 I915_WRITE(LCPLL_CTL, val);
8772 POSTING_READ(LCPLL_CTL);
8773 }
8774
8775 val = hsw_read_dcomp(dev_priv);
8776 val |= D_COMP_COMP_FORCE;
8777 val &= ~D_COMP_COMP_DISABLE;
8778 hsw_write_dcomp(dev_priv, val);
8779
8780 val = I915_READ(LCPLL_CTL);
8781 val &= ~LCPLL_PLL_DISABLE;
8782 I915_WRITE(LCPLL_CTL, val);
8783
8784 if (intel_wait_for_register(dev_priv,
8785 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8786 5))
8787 DRM_ERROR("LCPLL not locked yet\n");
8788
8789 if (val & LCPLL_CD_SOURCE_FCLK) {
8790 val = I915_READ(LCPLL_CTL);
8791 val &= ~LCPLL_CD_SOURCE_FCLK;
8792 I915_WRITE(LCPLL_CTL, val);
8793
8794 if (wait_for_us((I915_READ(LCPLL_CTL) &
8795 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8796 DRM_ERROR("Switching back to LCPLL failed\n");
8797 }
8798
8799 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8800 intel_update_cdclk(dev_priv);
8801 }
8802
8803 /*
8804 * Package states C8 and deeper are really deep PC states that can only be
8805 * reached when all the devices on the system allow it, so even if the graphics
8806 * device allows PC8+, it doesn't mean the system will actually get to these
8807 * states. Our driver only allows PC8+ when going into runtime PM.
8808 *
8809 * The requirements for PC8+ are that all the outputs are disabled, the power
8810 * well is disabled and most interrupts are disabled, and these are also
8811 * requirements for runtime PM. When these conditions are met, we manually do
8812 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8813 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8814 * hang the machine.
8815 *
8816 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8817 * the state of some registers, so when we come back from PC8+ we need to
8818 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8819 * need to take care of the registers kept by RC6. Notice that this happens even
8820 * if we don't put the device in PCI D3 state (which is what currently happens
8821 * because of the runtime PM support).
8822 *
8823 * For more, read "Display Sequences for Package C8" on the hardware
8824 * documentation.
8825 */
8826 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8827 {
8828 uint32_t val;
8829
8830 DRM_DEBUG_KMS("Enabling package C8+\n");
8831
8832 if (HAS_PCH_LPT_LP(dev_priv)) {
8833 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8834 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8835 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8836 }
8837
8838 lpt_disable_clkout_dp(dev_priv);
8839 hsw_disable_lcpll(dev_priv, true, true);
8840 }
8841
8842 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8843 {
8844 uint32_t val;
8845
8846 DRM_DEBUG_KMS("Disabling package C8+\n");
8847
8848 hsw_restore_lcpll(dev_priv);
8849 lpt_init_pch_refclk(dev_priv);
8850
8851 if (HAS_PCH_LPT_LP(dev_priv)) {
8852 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8853 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8854 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8855 }
8856 }
8857
8858 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8859 struct intel_crtc_state *crtc_state)
8860 {
8861 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8862 struct intel_encoder *encoder =
8863 intel_ddi_get_crtc_new_encoder(crtc_state);
8864
8865 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
8866 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8867 pipe_name(crtc->pipe));
8868 return -EINVAL;
8869 }
8870 }
8871
8872 crtc->lowfreq_avail = false;
8873
8874 return 0;
8875 }
8876
8877 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
8878 enum port port,
8879 struct intel_crtc_state *pipe_config)
8880 {
8881 enum intel_dpll_id id;
8882 u32 temp;
8883
8884 temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
8885 id = temp >> (port * 2);
8886
8887 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
8888 return;
8889
8890 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8891 }
8892
8893 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8894 enum port port,
8895 struct intel_crtc_state *pipe_config)
8896 {
8897 enum intel_dpll_id id;
8898
8899 switch (port) {
8900 case PORT_A:
8901 id = DPLL_ID_SKL_DPLL0;
8902 break;
8903 case PORT_B:
8904 id = DPLL_ID_SKL_DPLL1;
8905 break;
8906 case PORT_C:
8907 id = DPLL_ID_SKL_DPLL2;
8908 break;
8909 default:
8910 DRM_ERROR("Incorrect port type\n");
8911 return;
8912 }
8913
8914 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8915 }
8916
8917 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8918 enum port port,
8919 struct intel_crtc_state *pipe_config)
8920 {
8921 enum intel_dpll_id id;
8922 u32 temp;
8923
8924 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8925 id = temp >> (port * 3 + 1);
8926
8927 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
8928 return;
8929
8930 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8931 }
8932
8933 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8934 enum port port,
8935 struct intel_crtc_state *pipe_config)
8936 {
8937 enum intel_dpll_id id;
8938 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8939
8940 switch (ddi_pll_sel) {
8941 case PORT_CLK_SEL_WRPLL1:
8942 id = DPLL_ID_WRPLL1;
8943 break;
8944 case PORT_CLK_SEL_WRPLL2:
8945 id = DPLL_ID_WRPLL2;
8946 break;
8947 case PORT_CLK_SEL_SPLL:
8948 id = DPLL_ID_SPLL;
8949 break;
8950 case PORT_CLK_SEL_LCPLL_810:
8951 id = DPLL_ID_LCPLL_810;
8952 break;
8953 case PORT_CLK_SEL_LCPLL_1350:
8954 id = DPLL_ID_LCPLL_1350;
8955 break;
8956 case PORT_CLK_SEL_LCPLL_2700:
8957 id = DPLL_ID_LCPLL_2700;
8958 break;
8959 default:
8960 MISSING_CASE(ddi_pll_sel);
8961 /* fall through */
8962 case PORT_CLK_SEL_NONE:
8963 return;
8964 }
8965
8966 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8967 }
8968
8969 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
8970 struct intel_crtc_state *pipe_config,
8971 u64 *power_domain_mask)
8972 {
8973 struct drm_device *dev = crtc->base.dev;
8974 struct drm_i915_private *dev_priv = to_i915(dev);
8975 enum intel_display_power_domain power_domain;
8976 u32 tmp;
8977
8978 /*
8979 * The pipe->transcoder mapping is fixed with the exception of the eDP
8980 * transcoder handled below.
8981 */
8982 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8983
8984 /*
8985 * XXX: Do intel_display_power_get_if_enabled before reading this (for
8986 * consistency and less surprising code; it's in always on power).
8987 */
8988 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8989 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8990 enum pipe trans_edp_pipe;
8991 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8992 default:
8993 WARN(1, "unknown pipe linked to edp transcoder\n");
8994 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8995 case TRANS_DDI_EDP_INPUT_A_ON:
8996 trans_edp_pipe = PIPE_A;
8997 break;
8998 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8999 trans_edp_pipe = PIPE_B;
9000 break;
9001 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9002 trans_edp_pipe = PIPE_C;
9003 break;
9004 }
9005
9006 if (trans_edp_pipe == crtc->pipe)
9007 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9008 }
9009
9010 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9011 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9012 return false;
9013 *power_domain_mask |= BIT_ULL(power_domain);
9014
9015 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9016
9017 return tmp & PIPECONF_ENABLE;
9018 }
9019
9020 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9021 struct intel_crtc_state *pipe_config,
9022 u64 *power_domain_mask)
9023 {
9024 struct drm_device *dev = crtc->base.dev;
9025 struct drm_i915_private *dev_priv = to_i915(dev);
9026 enum intel_display_power_domain power_domain;
9027 enum port port;
9028 enum transcoder cpu_transcoder;
9029 u32 tmp;
9030
9031 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9032 if (port == PORT_A)
9033 cpu_transcoder = TRANSCODER_DSI_A;
9034 else
9035 cpu_transcoder = TRANSCODER_DSI_C;
9036
9037 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9038 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9039 continue;
9040 *power_domain_mask |= BIT_ULL(power_domain);
9041
9042 /*
9043 * The PLL needs to be enabled with a valid divider
9044 * configuration, otherwise accessing DSI registers will hang
9045 * the machine. See BSpec North Display Engine
9046 * registers/MIPI[BXT]. We can break out here early, since we
9047 * need the same DSI PLL to be enabled for both DSI ports.
9048 */
9049 if (!intel_dsi_pll_is_enabled(dev_priv))
9050 break;
9051
9052 /* XXX: this works for video mode only */
9053 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9054 if (!(tmp & DPI_ENABLE))
9055 continue;
9056
9057 tmp = I915_READ(MIPI_CTRL(port));
9058 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9059 continue;
9060
9061 pipe_config->cpu_transcoder = cpu_transcoder;
9062 break;
9063 }
9064
9065 return transcoder_is_dsi(pipe_config->cpu_transcoder);
9066 }
9067
9068 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9069 struct intel_crtc_state *pipe_config)
9070 {
9071 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9072 struct intel_shared_dpll *pll;
9073 enum port port;
9074 uint32_t tmp;
9075
9076 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9077
9078 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9079
9080 if (IS_CANNONLAKE(dev_priv))
9081 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9082 else if (IS_GEN9_BC(dev_priv))
9083 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9084 else if (IS_GEN9_LP(dev_priv))
9085 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9086 else
9087 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9088
9089 pll = pipe_config->shared_dpll;
9090 if (pll) {
9091 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9092 &pipe_config->dpll_hw_state));
9093 }
9094
9095 /*
9096 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9097 * DDI E. So just check whether this pipe is wired to DDI E and whether
9098 * the PCH transcoder is on.
9099 */
9100 if (INTEL_GEN(dev_priv) < 9 &&
9101 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9102 pipe_config->has_pch_encoder = true;
9103
9104 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9105 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9106 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9107
9108 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9109 }
9110 }
9111
9112 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9113 struct intel_crtc_state *pipe_config)
9114 {
9115 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9116 enum intel_display_power_domain power_domain;
9117 u64 power_domain_mask;
9118 bool active;
9119
9120 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9121 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9122 return false;
9123 power_domain_mask = BIT_ULL(power_domain);
9124
9125 pipe_config->shared_dpll = NULL;
9126
9127 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9128
9129 if (IS_GEN9_LP(dev_priv) &&
9130 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9131 WARN_ON(active);
9132 active = true;
9133 }
9134
9135 if (!active)
9136 goto out;
9137
9138 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9139 haswell_get_ddi_port_state(crtc, pipe_config);
9140 intel_get_pipe_timings(crtc, pipe_config);
9141 }
9142
9143 intel_get_pipe_src_size(crtc, pipe_config);
9144
9145 pipe_config->gamma_mode =
9146 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9147
9148 if (INTEL_GEN(dev_priv) >= 9) {
9149 intel_crtc_init_scalers(crtc, pipe_config);
9150
9151 pipe_config->scaler_state.scaler_id = -1;
9152 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9153 }
9154
9155 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9156 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9157 power_domain_mask |= BIT_ULL(power_domain);
9158 if (INTEL_GEN(dev_priv) >= 9)
9159 skylake_get_pfit_config(crtc, pipe_config);
9160 else
9161 ironlake_get_pfit_config(crtc, pipe_config);
9162 }
9163
9164 if (IS_HASWELL(dev_priv))
9165 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9166 (I915_READ(IPS_CTL) & IPS_ENABLE);
9167
9168 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9169 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9170 pipe_config->pixel_multiplier =
9171 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9172 } else {
9173 pipe_config->pixel_multiplier = 1;
9174 }
9175
9176 out:
9177 for_each_power_domain(power_domain, power_domain_mask)
9178 intel_display_power_put(dev_priv, power_domain);
9179
9180 return active;
9181 }
9182
9183 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9184 {
9185 struct drm_i915_private *dev_priv =
9186 to_i915(plane_state->base.plane->dev);
9187 const struct drm_framebuffer *fb = plane_state->base.fb;
9188 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9189 u32 base;
9190
9191 if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9192 base = obj->phys_handle->busaddr;
9193 else
9194 base = intel_plane_ggtt_offset(plane_state);
9195
9196 base += plane_state->main.offset;
9197
9198 /* ILK+ do this automagically */
9199 if (HAS_GMCH_DISPLAY(dev_priv) &&
9200 plane_state->base.rotation & DRM_MODE_ROTATE_180)
9201 base += (plane_state->base.crtc_h *
9202 plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9203
9204 return base;
9205 }
9206
9207 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9208 {
9209 int x = plane_state->base.crtc_x;
9210 int y = plane_state->base.crtc_y;
9211 u32 pos = 0;
9212
9213 if (x < 0) {
9214 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9215 x = -x;
9216 }
9217 pos |= x << CURSOR_X_SHIFT;
9218
9219 if (y < 0) {
9220 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9221 y = -y;
9222 }
9223 pos |= y << CURSOR_Y_SHIFT;
9224
9225 return pos;
9226 }
9227
9228 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9229 {
9230 const struct drm_mode_config *config =
9231 &plane_state->base.plane->dev->mode_config;
9232 int width = plane_state->base.crtc_w;
9233 int height = plane_state->base.crtc_h;
9234
9235 return width > 0 && width <= config->cursor_width &&
9236 height > 0 && height <= config->cursor_height;
9237 }
9238
9239 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9240 struct intel_plane_state *plane_state)
9241 {
9242 const struct drm_framebuffer *fb = plane_state->base.fb;
9243 int src_x, src_y;
9244 u32 offset;
9245 int ret;
9246
9247 ret = drm_plane_helper_check_state(&plane_state->base,
9248 &plane_state->clip,
9249 DRM_PLANE_HELPER_NO_SCALING,
9250 DRM_PLANE_HELPER_NO_SCALING,
9251 true, true);
9252 if (ret)
9253 return ret;
9254
9255 if (!fb)
9256 return 0;
9257
9258 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9259 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9260 return -EINVAL;
9261 }
9262
9263 src_x = plane_state->base.src_x >> 16;
9264 src_y = plane_state->base.src_y >> 16;
9265
9266 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9267 offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9268
9269 if (src_x != 0 || src_y != 0) {
9270 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9271 return -EINVAL;
9272 }
9273
9274 plane_state->main.offset = offset;
9275
9276 return 0;
9277 }
9278
9279 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9280 const struct intel_plane_state *plane_state)
9281 {
9282 const struct drm_framebuffer *fb = plane_state->base.fb;
9283
9284 return CURSOR_ENABLE |
9285 CURSOR_GAMMA_ENABLE |
9286 CURSOR_FORMAT_ARGB |
9287 CURSOR_STRIDE(fb->pitches[0]);
9288 }
9289
9290 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9291 {
9292 int width = plane_state->base.crtc_w;
9293
9294 /*
9295 * 845g/865g are only limited by the width of their cursors,
9296 * the height is arbitrary up to the precision of the register.
9297 */
9298 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9299 }
9300
9301 static int i845_check_cursor(struct intel_plane *plane,
9302 struct intel_crtc_state *crtc_state,
9303 struct intel_plane_state *plane_state)
9304 {
9305 const struct drm_framebuffer *fb = plane_state->base.fb;
9306 int ret;
9307
9308 ret = intel_check_cursor(crtc_state, plane_state);
9309 if (ret)
9310 return ret;
9311
9312 /* if we want to turn off the cursor ignore width and height */
9313 if (!fb)
9314 return 0;
9315
9316 /* Check for which cursor types we support */
9317 if (!i845_cursor_size_ok(plane_state)) {
9318 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9319 plane_state->base.crtc_w,
9320 plane_state->base.crtc_h);
9321 return -EINVAL;
9322 }
9323
9324 switch (fb->pitches[0]) {
9325 case 256:
9326 case 512:
9327 case 1024:
9328 case 2048:
9329 break;
9330 default:
9331 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9332 fb->pitches[0]);
9333 return -EINVAL;
9334 }
9335
9336 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9337
9338 return 0;
9339 }
9340
9341 static void i845_update_cursor(struct intel_plane *plane,
9342 const struct intel_crtc_state *crtc_state,
9343 const struct intel_plane_state *plane_state)
9344 {
9345 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9346 u32 cntl = 0, base = 0, pos = 0, size = 0;
9347 unsigned long irqflags;
9348
9349 if (plane_state && plane_state->base.visible) {
9350 unsigned int width = plane_state->base.crtc_w;
9351 unsigned int height = plane_state->base.crtc_h;
9352
9353 cntl = plane_state->ctl;
9354 size = (height << 12) | width;
9355
9356 base = intel_cursor_base(plane_state);
9357 pos = intel_cursor_position(plane_state);
9358 }
9359
9360 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9361
9362 /* On these chipsets we can only modify the base/size/stride
9363 * whilst the cursor is disabled.
9364 */
9365 if (plane->cursor.base != base ||
9366 plane->cursor.size != size ||
9367 plane->cursor.cntl != cntl) {
9368 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9369 I915_WRITE_FW(CURBASE(PIPE_A), base);
9370 I915_WRITE_FW(CURSIZE, size);
9371 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9372 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9373
9374 plane->cursor.base = base;
9375 plane->cursor.size = size;
9376 plane->cursor.cntl = cntl;
9377 } else {
9378 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9379 }
9380
9381 POSTING_READ_FW(CURCNTR(PIPE_A));
9382
9383 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9384 }
9385
9386 static void i845_disable_cursor(struct intel_plane *plane,
9387 struct intel_crtc *crtc)
9388 {
9389 i845_update_cursor(plane, NULL, NULL);
9390 }
9391
9392 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9393 const struct intel_plane_state *plane_state)
9394 {
9395 struct drm_i915_private *dev_priv =
9396 to_i915(plane_state->base.plane->dev);
9397 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9398 u32 cntl;
9399
9400 cntl = MCURSOR_GAMMA_ENABLE;
9401
9402 if (HAS_DDI(dev_priv))
9403 cntl |= CURSOR_PIPE_CSC_ENABLE;
9404
9405 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9406
9407 switch (plane_state->base.crtc_w) {
9408 case 64:
9409 cntl |= CURSOR_MODE_64_ARGB_AX;
9410 break;
9411 case 128:
9412 cntl |= CURSOR_MODE_128_ARGB_AX;
9413 break;
9414 case 256:
9415 cntl |= CURSOR_MODE_256_ARGB_AX;
9416 break;
9417 default:
9418 MISSING_CASE(plane_state->base.crtc_w);
9419 return 0;
9420 }
9421
9422 if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9423 cntl |= CURSOR_ROTATE_180;
9424
9425 return cntl;
9426 }
9427
9428 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9429 {
9430 struct drm_i915_private *dev_priv =
9431 to_i915(plane_state->base.plane->dev);
9432 int width = plane_state->base.crtc_w;
9433 int height = plane_state->base.crtc_h;
9434
9435 if (!intel_cursor_size_ok(plane_state))
9436 return false;
9437
9438 /* Cursor width is limited to a few power-of-two sizes */
9439 switch (width) {
9440 case 256:
9441 case 128:
9442 case 64:
9443 break;
9444 default:
9445 return false;
9446 }
9447
9448 /*
9449 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9450 * height from 8 lines up to the cursor width, when the
9451 * cursor is not rotated. Everything else requires square
9452 * cursors.
9453 */
9454 if (HAS_CUR_FBC(dev_priv) &&
9455 plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9456 if (height < 8 || height > width)
9457 return false;
9458 } else {
9459 if (height != width)
9460 return false;
9461 }
9462
9463 return true;
9464 }
9465
9466 static int i9xx_check_cursor(struct intel_plane *plane,
9467 struct intel_crtc_state *crtc_state,
9468 struct intel_plane_state *plane_state)
9469 {
9470 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9471 const struct drm_framebuffer *fb = plane_state->base.fb;
9472 enum pipe pipe = plane->pipe;
9473 int ret;
9474
9475 ret = intel_check_cursor(crtc_state, plane_state);
9476 if (ret)
9477 return ret;
9478
9479 /* if we want to turn off the cursor ignore width and height */
9480 if (!fb)
9481 return 0;
9482
9483 /* Check for which cursor types we support */
9484 if (!i9xx_cursor_size_ok(plane_state)) {
9485 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9486 plane_state->base.crtc_w,
9487 plane_state->base.crtc_h);
9488 return -EINVAL;
9489 }
9490
9491 if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9492 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9493 fb->pitches[0], plane_state->base.crtc_w);
9494 return -EINVAL;
9495 }
9496
9497 /*
9498 * There's something wrong with the cursor on CHV pipe C.
9499 * If it straddles the left edge of the screen then
9500 * moving it away from the edge or disabling it often
9501 * results in a pipe underrun, and often that can lead to
9502 * dead pipe (constant underrun reported, and it scans
9503 * out just a solid color). To recover from that, the
9504 * display power well must be turned off and on again.
9505 * Refuse the put the cursor into that compromised position.
9506 */
9507 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9508 plane_state->base.visible && plane_state->base.crtc_x < 0) {
9509 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9510 return -EINVAL;
9511 }
9512
9513 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9514
9515 return 0;
9516 }
9517
9518 static void i9xx_update_cursor(struct intel_plane *plane,
9519 const struct intel_crtc_state *crtc_state,
9520 const struct intel_plane_state *plane_state)
9521 {
9522 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9523 enum pipe pipe = plane->pipe;
9524 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9525 unsigned long irqflags;
9526
9527 if (plane_state && plane_state->base.visible) {
9528 cntl = plane_state->ctl;
9529
9530 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9531 fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9532
9533 base = intel_cursor_base(plane_state);
9534 pos = intel_cursor_position(plane_state);
9535 }
9536
9537 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9538
9539 /*
9540 * On some platforms writing CURCNTR first will also
9541 * cause CURPOS to be armed by the CURBASE write.
9542 * Without the CURCNTR write the CURPOS write would
9543 * arm itself.
9544 *
9545 * CURCNTR and CUR_FBC_CTL are always
9546 * armed by the CURBASE write only.
9547 */
9548 if (plane->cursor.base != base ||
9549 plane->cursor.size != fbc_ctl ||
9550 plane->cursor.cntl != cntl) {
9551 I915_WRITE_FW(CURCNTR(pipe), cntl);
9552 if (HAS_CUR_FBC(dev_priv))
9553 I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
9554 I915_WRITE_FW(CURPOS(pipe), pos);
9555 I915_WRITE_FW(CURBASE(pipe), base);
9556
9557 plane->cursor.base = base;
9558 plane->cursor.size = fbc_ctl;
9559 plane->cursor.cntl = cntl;
9560 } else {
9561 I915_WRITE_FW(CURPOS(pipe), pos);
9562 }
9563
9564 POSTING_READ_FW(CURBASE(pipe));
9565
9566 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9567 }
9568
9569 static void i9xx_disable_cursor(struct intel_plane *plane,
9570 struct intel_crtc *crtc)
9571 {
9572 i9xx_update_cursor(plane, NULL, NULL);
9573 }
9574
9575
9576 /* VESA 640x480x72Hz mode to set on the pipe */
9577 static struct drm_display_mode load_detect_mode = {
9578 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9579 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9580 };
9581
9582 struct drm_framebuffer *
9583 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9584 struct drm_mode_fb_cmd2 *mode_cmd)
9585 {
9586 struct intel_framebuffer *intel_fb;
9587 int ret;
9588
9589 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9590 if (!intel_fb)
9591 return ERR_PTR(-ENOMEM);
9592
9593 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9594 if (ret)
9595 goto err;
9596
9597 return &intel_fb->base;
9598
9599 err:
9600 kfree(intel_fb);
9601 return ERR_PTR(ret);
9602 }
9603
9604 static u32
9605 intel_framebuffer_pitch_for_width(int width, int bpp)
9606 {
9607 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9608 return ALIGN(pitch, 64);
9609 }
9610
9611 static u32
9612 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9613 {
9614 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9615 return PAGE_ALIGN(pitch * mode->vdisplay);
9616 }
9617
9618 static struct drm_framebuffer *
9619 intel_framebuffer_create_for_mode(struct drm_device *dev,
9620 struct drm_display_mode *mode,
9621 int depth, int bpp)
9622 {
9623 struct drm_framebuffer *fb;
9624 struct drm_i915_gem_object *obj;
9625 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9626
9627 obj = i915_gem_object_create(to_i915(dev),
9628 intel_framebuffer_size_for_mode(mode, bpp));
9629 if (IS_ERR(obj))
9630 return ERR_CAST(obj);
9631
9632 mode_cmd.width = mode->hdisplay;
9633 mode_cmd.height = mode->vdisplay;
9634 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9635 bpp);
9636 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9637
9638 fb = intel_framebuffer_create(obj, &mode_cmd);
9639 if (IS_ERR(fb))
9640 i915_gem_object_put(obj);
9641
9642 return fb;
9643 }
9644
9645 static struct drm_framebuffer *
9646 mode_fits_in_fbdev(struct drm_device *dev,
9647 struct drm_display_mode *mode)
9648 {
9649 #ifdef CONFIG_DRM_FBDEV_EMULATION
9650 struct drm_i915_private *dev_priv = to_i915(dev);
9651 struct drm_i915_gem_object *obj;
9652 struct drm_framebuffer *fb;
9653
9654 if (!dev_priv->fbdev)
9655 return NULL;
9656
9657 if (!dev_priv->fbdev->fb)
9658 return NULL;
9659
9660 obj = dev_priv->fbdev->fb->obj;
9661 BUG_ON(!obj);
9662
9663 fb = &dev_priv->fbdev->fb->base;
9664 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9665 fb->format->cpp[0] * 8))
9666 return NULL;
9667
9668 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9669 return NULL;
9670
9671 drm_framebuffer_reference(fb);
9672 return fb;
9673 #else
9674 return NULL;
9675 #endif
9676 }
9677
9678 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9679 struct drm_crtc *crtc,
9680 struct drm_display_mode *mode,
9681 struct drm_framebuffer *fb,
9682 int x, int y)
9683 {
9684 struct drm_plane_state *plane_state;
9685 int hdisplay, vdisplay;
9686 int ret;
9687
9688 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9689 if (IS_ERR(plane_state))
9690 return PTR_ERR(plane_state);
9691
9692 if (mode)
9693 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9694 else
9695 hdisplay = vdisplay = 0;
9696
9697 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9698 if (ret)
9699 return ret;
9700 drm_atomic_set_fb_for_plane(plane_state, fb);
9701 plane_state->crtc_x = 0;
9702 plane_state->crtc_y = 0;
9703 plane_state->crtc_w = hdisplay;
9704 plane_state->crtc_h = vdisplay;
9705 plane_state->src_x = x << 16;
9706 plane_state->src_y = y << 16;
9707 plane_state->src_w = hdisplay << 16;
9708 plane_state->src_h = vdisplay << 16;
9709
9710 return 0;
9711 }
9712
9713 int intel_get_load_detect_pipe(struct drm_connector *connector,
9714 struct drm_display_mode *mode,
9715 struct intel_load_detect_pipe *old,
9716 struct drm_modeset_acquire_ctx *ctx)
9717 {
9718 struct intel_crtc *intel_crtc;
9719 struct intel_encoder *intel_encoder =
9720 intel_attached_encoder(connector);
9721 struct drm_crtc *possible_crtc;
9722 struct drm_encoder *encoder = &intel_encoder->base;
9723 struct drm_crtc *crtc = NULL;
9724 struct drm_device *dev = encoder->dev;
9725 struct drm_i915_private *dev_priv = to_i915(dev);
9726 struct drm_framebuffer *fb;
9727 struct drm_mode_config *config = &dev->mode_config;
9728 struct drm_atomic_state *state = NULL, *restore_state = NULL;
9729 struct drm_connector_state *connector_state;
9730 struct intel_crtc_state *crtc_state;
9731 int ret, i = -1;
9732
9733 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9734 connector->base.id, connector->name,
9735 encoder->base.id, encoder->name);
9736
9737 old->restore_state = NULL;
9738
9739 WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
9740
9741 /*
9742 * Algorithm gets a little messy:
9743 *
9744 * - if the connector already has an assigned crtc, use it (but make
9745 * sure it's on first)
9746 *
9747 * - try to find the first unused crtc that can drive this connector,
9748 * and use that if we find one
9749 */
9750
9751 /* See if we already have a CRTC for this connector */
9752 if (connector->state->crtc) {
9753 crtc = connector->state->crtc;
9754
9755 ret = drm_modeset_lock(&crtc->mutex, ctx);
9756 if (ret)
9757 goto fail;
9758
9759 /* Make sure the crtc and connector are running */
9760 goto found;
9761 }
9762
9763 /* Find an unused one (if possible) */
9764 for_each_crtc(dev, possible_crtc) {
9765 i++;
9766 if (!(encoder->possible_crtcs & (1 << i)))
9767 continue;
9768
9769 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9770 if (ret)
9771 goto fail;
9772
9773 if (possible_crtc->state->enable) {
9774 drm_modeset_unlock(&possible_crtc->mutex);
9775 continue;
9776 }
9777
9778 crtc = possible_crtc;
9779 break;
9780 }
9781
9782 /*
9783 * If we didn't find an unused CRTC, don't use any.
9784 */
9785 if (!crtc) {
9786 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9787 ret = -ENODEV;
9788 goto fail;
9789 }
9790
9791 found:
9792 intel_crtc = to_intel_crtc(crtc);
9793
9794 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9795 if (ret)
9796 goto fail;
9797
9798 state = drm_atomic_state_alloc(dev);
9799 restore_state = drm_atomic_state_alloc(dev);
9800 if (!state || !restore_state) {
9801 ret = -ENOMEM;
9802 goto fail;
9803 }
9804
9805 state->acquire_ctx = ctx;
9806 restore_state->acquire_ctx = ctx;
9807
9808 connector_state = drm_atomic_get_connector_state(state, connector);
9809 if (IS_ERR(connector_state)) {
9810 ret = PTR_ERR(connector_state);
9811 goto fail;
9812 }
9813
9814 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9815 if (ret)
9816 goto fail;
9817
9818 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9819 if (IS_ERR(crtc_state)) {
9820 ret = PTR_ERR(crtc_state);
9821 goto fail;
9822 }
9823
9824 crtc_state->base.active = crtc_state->base.enable = true;
9825
9826 if (!mode)
9827 mode = &load_detect_mode;
9828
9829 /* We need a framebuffer large enough to accommodate all accesses
9830 * that the plane may generate whilst we perform load detection.
9831 * We can not rely on the fbcon either being present (we get called
9832 * during its initialisation to detect all boot displays, or it may
9833 * not even exist) or that it is large enough to satisfy the
9834 * requested mode.
9835 */
9836 fb = mode_fits_in_fbdev(dev, mode);
9837 if (fb == NULL) {
9838 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9839 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9840 } else
9841 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9842 if (IS_ERR(fb)) {
9843 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9844 ret = PTR_ERR(fb);
9845 goto fail;
9846 }
9847
9848 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9849 if (ret)
9850 goto fail;
9851
9852 drm_framebuffer_unreference(fb);
9853
9854 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9855 if (ret)
9856 goto fail;
9857
9858 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9859 if (!ret)
9860 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9861 if (!ret)
9862 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9863 if (ret) {
9864 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9865 goto fail;
9866 }
9867
9868 ret = drm_atomic_commit(state);
9869 if (ret) {
9870 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9871 goto fail;
9872 }
9873
9874 old->restore_state = restore_state;
9875 drm_atomic_state_put(state);
9876
9877 /* let the connector get through one full cycle before testing */
9878 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9879 return true;
9880
9881 fail:
9882 if (state) {
9883 drm_atomic_state_put(state);
9884 state = NULL;
9885 }
9886 if (restore_state) {
9887 drm_atomic_state_put(restore_state);
9888 restore_state = NULL;
9889 }
9890
9891 if (ret == -EDEADLK)
9892 return ret;
9893
9894 return false;
9895 }
9896
9897 void intel_release_load_detect_pipe(struct drm_connector *connector,
9898 struct intel_load_detect_pipe *old,
9899 struct drm_modeset_acquire_ctx *ctx)
9900 {
9901 struct intel_encoder *intel_encoder =
9902 intel_attached_encoder(connector);
9903 struct drm_encoder *encoder = &intel_encoder->base;
9904 struct drm_atomic_state *state = old->restore_state;
9905 int ret;
9906
9907 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9908 connector->base.id, connector->name,
9909 encoder->base.id, encoder->name);
9910
9911 if (!state)
9912 return;
9913
9914 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
9915 if (ret)
9916 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
9917 drm_atomic_state_put(state);
9918 }
9919
9920 static int i9xx_pll_refclk(struct drm_device *dev,
9921 const struct intel_crtc_state *pipe_config)
9922 {
9923 struct drm_i915_private *dev_priv = to_i915(dev);
9924 u32 dpll = pipe_config->dpll_hw_state.dpll;
9925
9926 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9927 return dev_priv->vbt.lvds_ssc_freq;
9928 else if (HAS_PCH_SPLIT(dev_priv))
9929 return 120000;
9930 else if (!IS_GEN2(dev_priv))
9931 return 96000;
9932 else
9933 return 48000;
9934 }
9935
9936 /* Returns the clock of the currently programmed mode of the given pipe. */
9937 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9938 struct intel_crtc_state *pipe_config)
9939 {
9940 struct drm_device *dev = crtc->base.dev;
9941 struct drm_i915_private *dev_priv = to_i915(dev);
9942 int pipe = pipe_config->cpu_transcoder;
9943 u32 dpll = pipe_config->dpll_hw_state.dpll;
9944 u32 fp;
9945 struct dpll clock;
9946 int port_clock;
9947 int refclk = i9xx_pll_refclk(dev, pipe_config);
9948
9949 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9950 fp = pipe_config->dpll_hw_state.fp0;
9951 else
9952 fp = pipe_config->dpll_hw_state.fp1;
9953
9954 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9955 if (IS_PINEVIEW(dev_priv)) {
9956 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9957 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9958 } else {
9959 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9960 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9961 }
9962
9963 if (!IS_GEN2(dev_priv)) {
9964 if (IS_PINEVIEW(dev_priv))
9965 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9966 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9967 else
9968 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9969 DPLL_FPA01_P1_POST_DIV_SHIFT);
9970
9971 switch (dpll & DPLL_MODE_MASK) {
9972 case DPLLB_MODE_DAC_SERIAL:
9973 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9974 5 : 10;
9975 break;
9976 case DPLLB_MODE_LVDS:
9977 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9978 7 : 14;
9979 break;
9980 default:
9981 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9982 "mode\n", (int)(dpll & DPLL_MODE_MASK));
9983 return;
9984 }
9985
9986 if (IS_PINEVIEW(dev_priv))
9987 port_clock = pnv_calc_dpll_params(refclk, &clock);
9988 else
9989 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9990 } else {
9991 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
9992 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9993
9994 if (is_lvds) {
9995 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9996 DPLL_FPA01_P1_POST_DIV_SHIFT);
9997
9998 if (lvds & LVDS_CLKB_POWER_UP)
9999 clock.p2 = 7;
10000 else
10001 clock.p2 = 14;
10002 } else {
10003 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10004 clock.p1 = 2;
10005 else {
10006 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10007 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10008 }
10009 if (dpll & PLL_P2_DIVIDE_BY_4)
10010 clock.p2 = 4;
10011 else
10012 clock.p2 = 2;
10013 }
10014
10015 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10016 }
10017
10018 /*
10019 * This value includes pixel_multiplier. We will use
10020 * port_clock to compute adjusted_mode.crtc_clock in the
10021 * encoder's get_config() function.
10022 */
10023 pipe_config->port_clock = port_clock;
10024 }
10025
10026 int intel_dotclock_calculate(int link_freq,
10027 const struct intel_link_m_n *m_n)
10028 {
10029 /*
10030 * The calculation for the data clock is:
10031 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10032 * But we want to avoid losing precison if possible, so:
10033 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10034 *
10035 * and the link clock is simpler:
10036 * link_clock = (m * link_clock) / n
10037 */
10038
10039 if (!m_n->link_n)
10040 return 0;
10041
10042 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10043 }
10044
10045 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10046 struct intel_crtc_state *pipe_config)
10047 {
10048 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10049
10050 /* read out port_clock from the DPLL */
10051 i9xx_crtc_clock_get(crtc, pipe_config);
10052
10053 /*
10054 * In case there is an active pipe without active ports,
10055 * we may need some idea for the dotclock anyway.
10056 * Calculate one based on the FDI configuration.
10057 */
10058 pipe_config->base.adjusted_mode.crtc_clock =
10059 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10060 &pipe_config->fdi_m_n);
10061 }
10062
10063 /** Returns the currently programmed mode of the given pipe. */
10064 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10065 struct drm_crtc *crtc)
10066 {
10067 struct drm_i915_private *dev_priv = to_i915(dev);
10068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10069 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10070 struct drm_display_mode *mode;
10071 struct intel_crtc_state *pipe_config;
10072 int htot = I915_READ(HTOTAL(cpu_transcoder));
10073 int hsync = I915_READ(HSYNC(cpu_transcoder));
10074 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10075 int vsync = I915_READ(VSYNC(cpu_transcoder));
10076 enum pipe pipe = intel_crtc->pipe;
10077
10078 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10079 if (!mode)
10080 return NULL;
10081
10082 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10083 if (!pipe_config) {
10084 kfree(mode);
10085 return NULL;
10086 }
10087
10088 /*
10089 * Construct a pipe_config sufficient for getting the clock info
10090 * back out of crtc_clock_get.
10091 *
10092 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10093 * to use a real value here instead.
10094 */
10095 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10096 pipe_config->pixel_multiplier = 1;
10097 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10098 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10099 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10100 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10101
10102 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10103 mode->hdisplay = (htot & 0xffff) + 1;
10104 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10105 mode->hsync_start = (hsync & 0xffff) + 1;
10106 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10107 mode->vdisplay = (vtot & 0xffff) + 1;
10108 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10109 mode->vsync_start = (vsync & 0xffff) + 1;
10110 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10111
10112 drm_mode_set_name(mode);
10113
10114 kfree(pipe_config);
10115
10116 return mode;
10117 }
10118
10119 static void intel_crtc_destroy(struct drm_crtc *crtc)
10120 {
10121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10122 struct drm_device *dev = crtc->dev;
10123 struct intel_flip_work *work;
10124
10125 spin_lock_irq(&dev->event_lock);
10126 work = intel_crtc->flip_work;
10127 intel_crtc->flip_work = NULL;
10128 spin_unlock_irq(&dev->event_lock);
10129
10130 if (work) {
10131 cancel_work_sync(&work->mmio_work);
10132 cancel_work_sync(&work->unpin_work);
10133 kfree(work);
10134 }
10135
10136 drm_crtc_cleanup(crtc);
10137
10138 kfree(intel_crtc);
10139 }
10140
10141 static void intel_unpin_work_fn(struct work_struct *__work)
10142 {
10143 struct intel_flip_work *work =
10144 container_of(__work, struct intel_flip_work, unpin_work);
10145 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10146 struct drm_device *dev = crtc->base.dev;
10147 struct drm_plane *primary = crtc->base.primary;
10148
10149 if (is_mmio_work(work))
10150 flush_work(&work->mmio_work);
10151
10152 mutex_lock(&dev->struct_mutex);
10153 intel_unpin_fb_vma(work->old_vma);
10154 i915_gem_object_put(work->pending_flip_obj);
10155 mutex_unlock(&dev->struct_mutex);
10156
10157 i915_gem_request_put(work->flip_queued_req);
10158
10159 intel_frontbuffer_flip_complete(to_i915(dev),
10160 to_intel_plane(primary)->frontbuffer_bit);
10161 intel_fbc_post_update(crtc);
10162 drm_framebuffer_unreference(work->old_fb);
10163
10164 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10165 atomic_dec(&crtc->unpin_work_count);
10166
10167 kfree(work);
10168 }
10169
10170 /* Is 'a' after or equal to 'b'? */
10171 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10172 {
10173 return !((a - b) & 0x80000000);
10174 }
10175
10176 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
10177 struct intel_flip_work *work)
10178 {
10179 struct drm_device *dev = crtc->base.dev;
10180 struct drm_i915_private *dev_priv = to_i915(dev);
10181
10182 if (abort_flip_on_reset(crtc))
10183 return true;
10184
10185 /*
10186 * The relevant registers doen't exist on pre-ctg.
10187 * As the flip done interrupt doesn't trigger for mmio
10188 * flips on gmch platforms, a flip count check isn't
10189 * really needed there. But since ctg has the registers,
10190 * include it in the check anyway.
10191 */
10192 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10193 return true;
10194
10195 /*
10196 * BDW signals flip done immediately if the plane
10197 * is disabled, even if the plane enable is already
10198 * armed to occur at the next vblank :(
10199 */
10200
10201 /*
10202 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10203 * used the same base address. In that case the mmio flip might
10204 * have completed, but the CS hasn't even executed the flip yet.
10205 *
10206 * A flip count check isn't enough as the CS might have updated
10207 * the base address just after start of vblank, but before we
10208 * managed to process the interrupt. This means we'd complete the
10209 * CS flip too soon.
10210 *
10211 * Combining both checks should get us a good enough result. It may
10212 * still happen that the CS flip has been executed, but has not
10213 * yet actually completed. But in case the base address is the same
10214 * anyway, we don't really care.
10215 */
10216 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10217 crtc->flip_work->gtt_offset &&
10218 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10219 crtc->flip_work->flip_count);
10220 }
10221
10222 static bool
10223 __pageflip_finished_mmio(struct intel_crtc *crtc,
10224 struct intel_flip_work *work)
10225 {
10226 /*
10227 * MMIO work completes when vblank is different from
10228 * flip_queued_vblank.
10229 *
10230 * Reset counter value doesn't matter, this is handled by
10231 * i915_wait_request finishing early, so no need to handle
10232 * reset here.
10233 */
10234 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
10235 }
10236
10237
10238 static bool pageflip_finished(struct intel_crtc *crtc,
10239 struct intel_flip_work *work)
10240 {
10241 if (!atomic_read(&work->pending))
10242 return false;
10243
10244 smp_rmb();
10245
10246 if (is_mmio_work(work))
10247 return __pageflip_finished_mmio(crtc, work);
10248 else
10249 return __pageflip_finished_cs(crtc, work);
10250 }
10251
10252 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
10253 {
10254 struct drm_device *dev = &dev_priv->drm;
10255 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10256 struct intel_flip_work *work;
10257 unsigned long flags;
10258
10259 /* Ignore early vblank irqs */
10260 if (!crtc)
10261 return;
10262
10263 /*
10264 * This is called both by irq handlers and the reset code (to complete
10265 * lost pageflips) so needs the full irqsave spinlocks.
10266 */
10267 spin_lock_irqsave(&dev->event_lock, flags);
10268 work = crtc->flip_work;
10269
10270 if (work != NULL &&
10271 !is_mmio_work(work) &&
10272 pageflip_finished(crtc, work))
10273 page_flip_completed(crtc);
10274
10275 spin_unlock_irqrestore(&dev->event_lock, flags);
10276 }
10277
10278 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
10279 {
10280 struct drm_device *dev = &dev_priv->drm;
10281 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10282 struct intel_flip_work *work;
10283 unsigned long flags;
10284
10285 /* Ignore early vblank irqs */
10286 if (!crtc)
10287 return;
10288
10289 /*
10290 * This is called both by irq handlers and the reset code (to complete
10291 * lost pageflips) so needs the full irqsave spinlocks.
10292 */
10293 spin_lock_irqsave(&dev->event_lock, flags);
10294 work = crtc->flip_work;
10295
10296 if (work != NULL &&
10297 is_mmio_work(work) &&
10298 pageflip_finished(crtc, work))
10299 page_flip_completed(crtc);
10300
10301 spin_unlock_irqrestore(&dev->event_lock, flags);
10302 }
10303
10304 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
10305 struct intel_flip_work *work)
10306 {
10307 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
10308
10309 /* Ensure that the work item is consistent when activating it ... */
10310 smp_mb__before_atomic();
10311 atomic_set(&work->pending, 1);
10312 }
10313
10314 static int intel_gen2_queue_flip(struct drm_device *dev,
10315 struct drm_crtc *crtc,
10316 struct drm_framebuffer *fb,
10317 struct drm_i915_gem_object *obj,
10318 struct drm_i915_gem_request *req,
10319 uint32_t flags)
10320 {
10321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10322 u32 flip_mask, *cs;
10323
10324 cs = intel_ring_begin(req, 6);
10325 if (IS_ERR(cs))
10326 return PTR_ERR(cs);
10327
10328 /* Can't queue multiple flips, so wait for the previous
10329 * one to finish before executing the next.
10330 */
10331 if (intel_crtc->plane)
10332 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10333 else
10334 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10335 *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10336 *cs++ = MI_NOOP;
10337 *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10338 *cs++ = fb->pitches[0];
10339 *cs++ = intel_crtc->flip_work->gtt_offset;
10340 *cs++ = 0; /* aux display base address, unused */
10341
10342 return 0;
10343 }
10344
10345 static int intel_gen3_queue_flip(struct drm_device *dev,
10346 struct drm_crtc *crtc,
10347 struct drm_framebuffer *fb,
10348 struct drm_i915_gem_object *obj,
10349 struct drm_i915_gem_request *req,
10350 uint32_t flags)
10351 {
10352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10353 u32 flip_mask, *cs;
10354
10355 cs = intel_ring_begin(req, 6);
10356 if (IS_ERR(cs))
10357 return PTR_ERR(cs);
10358
10359 if (intel_crtc->plane)
10360 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10361 else
10362 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10363 *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10364 *cs++ = MI_NOOP;
10365 *cs++ = MI_DISPLAY_FLIP_I915 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10366 *cs++ = fb->pitches[0];
10367 *cs++ = intel_crtc->flip_work->gtt_offset;
10368 *cs++ = MI_NOOP;
10369
10370 return 0;
10371 }
10372
10373 static int intel_gen4_queue_flip(struct drm_device *dev,
10374 struct drm_crtc *crtc,
10375 struct drm_framebuffer *fb,
10376 struct drm_i915_gem_object *obj,
10377 struct drm_i915_gem_request *req,
10378 uint32_t flags)
10379 {
10380 struct drm_i915_private *dev_priv = to_i915(dev);
10381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10382 u32 pf, pipesrc, *cs;
10383
10384 cs = intel_ring_begin(req, 4);
10385 if (IS_ERR(cs))
10386 return PTR_ERR(cs);
10387
10388 /* i965+ uses the linear or tiled offsets from the
10389 * Display Registers (which do not change across a page-flip)
10390 * so we need only reprogram the base address.
10391 */
10392 *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10393 *cs++ = fb->pitches[0];
10394 *cs++ = intel_crtc->flip_work->gtt_offset |
10395 intel_fb_modifier_to_tiling(fb->modifier);
10396
10397 /* XXX Enabling the panel-fitter across page-flip is so far
10398 * untested on non-native modes, so ignore it for now.
10399 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10400 */
10401 pf = 0;
10402 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10403 *cs++ = pf | pipesrc;
10404
10405 return 0;
10406 }
10407
10408 static int intel_gen6_queue_flip(struct drm_device *dev,
10409 struct drm_crtc *crtc,
10410 struct drm_framebuffer *fb,
10411 struct drm_i915_gem_object *obj,
10412 struct drm_i915_gem_request *req,
10413 uint32_t flags)
10414 {
10415 struct drm_i915_private *dev_priv = to_i915(dev);
10416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10417 u32 pf, pipesrc, *cs;
10418
10419 cs = intel_ring_begin(req, 4);
10420 if (IS_ERR(cs))
10421 return PTR_ERR(cs);
10422
10423 *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10424 *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10425 *cs++ = intel_crtc->flip_work->gtt_offset;
10426
10427 /* Contrary to the suggestions in the documentation,
10428 * "Enable Panel Fitter" does not seem to be required when page
10429 * flipping with a non-native mode, and worse causes a normal
10430 * modeset to fail.
10431 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10432 */
10433 pf = 0;
10434 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10435 *cs++ = pf | pipesrc;
10436
10437 return 0;
10438 }
10439
10440 static int intel_gen7_queue_flip(struct drm_device *dev,
10441 struct drm_crtc *crtc,
10442 struct drm_framebuffer *fb,
10443 struct drm_i915_gem_object *obj,
10444 struct drm_i915_gem_request *req,
10445 uint32_t flags)
10446 {
10447 struct drm_i915_private *dev_priv = to_i915(dev);
10448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10449 u32 *cs, plane_bit = 0;
10450 int len, ret;
10451
10452 switch (intel_crtc->plane) {
10453 case PLANE_A:
10454 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10455 break;
10456 case PLANE_B:
10457 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10458 break;
10459 case PLANE_C:
10460 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10461 break;
10462 default:
10463 WARN_ONCE(1, "unknown plane in flip command\n");
10464 return -ENODEV;
10465 }
10466
10467 len = 4;
10468 if (req->engine->id == RCS) {
10469 len += 6;
10470 /*
10471 * On Gen 8, SRM is now taking an extra dword to accommodate
10472 * 48bits addresses, and we need a NOOP for the batch size to
10473 * stay even.
10474 */
10475 if (IS_GEN8(dev_priv))
10476 len += 2;
10477 }
10478
10479 /*
10480 * BSpec MI_DISPLAY_FLIP for IVB:
10481 * "The full packet must be contained within the same cache line."
10482 *
10483 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10484 * cacheline, if we ever start emitting more commands before
10485 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10486 * then do the cacheline alignment, and finally emit the
10487 * MI_DISPLAY_FLIP.
10488 */
10489 ret = intel_ring_cacheline_align(req);
10490 if (ret)
10491 return ret;
10492
10493 cs = intel_ring_begin(req, len);
10494 if (IS_ERR(cs))
10495 return PTR_ERR(cs);
10496
10497 /* Unmask the flip-done completion message. Note that the bspec says that
10498 * we should do this for both the BCS and RCS, and that we must not unmask
10499 * more than one flip event at any time (or ensure that one flip message
10500 * can be sent by waiting for flip-done prior to queueing new flips).
10501 * Experimentation says that BCS works despite DERRMR masking all
10502 * flip-done completion events and that unmasking all planes at once
10503 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10504 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10505 */
10506 if (req->engine->id == RCS) {
10507 *cs++ = MI_LOAD_REGISTER_IMM(1);
10508 *cs++ = i915_mmio_reg_offset(DERRMR);
10509 *cs++ = ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10510 DERRMR_PIPEB_PRI_FLIP_DONE |
10511 DERRMR_PIPEC_PRI_FLIP_DONE);
10512 if (IS_GEN8(dev_priv))
10513 *cs++ = MI_STORE_REGISTER_MEM_GEN8 |
10514 MI_SRM_LRM_GLOBAL_GTT;
10515 else
10516 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
10517 *cs++ = i915_mmio_reg_offset(DERRMR);
10518 *cs++ = i915_ggtt_offset(req->engine->scratch) + 256;
10519 if (IS_GEN8(dev_priv)) {
10520 *cs++ = 0;
10521 *cs++ = MI_NOOP;
10522 }
10523 }
10524
10525 *cs++ = MI_DISPLAY_FLIP_I915 | plane_bit;
10526 *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10527 *cs++ = intel_crtc->flip_work->gtt_offset;
10528 *cs++ = MI_NOOP;
10529
10530 return 0;
10531 }
10532
10533 static bool use_mmio_flip(struct intel_engine_cs *engine,
10534 struct drm_i915_gem_object *obj)
10535 {
10536 /*
10537 * This is not being used for older platforms, because
10538 * non-availability of flip done interrupt forces us to use
10539 * CS flips. Older platforms derive flip done using some clever
10540 * tricks involving the flip_pending status bits and vblank irqs.
10541 * So using MMIO flips there would disrupt this mechanism.
10542 */
10543
10544 if (engine == NULL)
10545 return true;
10546
10547 if (INTEL_GEN(engine->i915) < 5)
10548 return false;
10549
10550 if (i915.use_mmio_flip < 0)
10551 return false;
10552 else if (i915.use_mmio_flip > 0)
10553 return true;
10554 else if (i915.enable_execlists)
10555 return true;
10556
10557 return engine != i915_gem_object_last_write_engine(obj);
10558 }
10559
10560 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
10561 unsigned int rotation,
10562 struct intel_flip_work *work)
10563 {
10564 struct drm_device *dev = intel_crtc->base.dev;
10565 struct drm_i915_private *dev_priv = to_i915(dev);
10566 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10567 const enum pipe pipe = intel_crtc->pipe;
10568 u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
10569
10570 ctl = I915_READ(PLANE_CTL(pipe, 0));
10571 ctl &= ~PLANE_CTL_TILED_MASK;
10572 switch (fb->modifier) {
10573 case DRM_FORMAT_MOD_LINEAR:
10574 break;
10575 case I915_FORMAT_MOD_X_TILED:
10576 ctl |= PLANE_CTL_TILED_X;
10577 break;
10578 case I915_FORMAT_MOD_Y_TILED:
10579 ctl |= PLANE_CTL_TILED_Y;
10580 break;
10581 case I915_FORMAT_MOD_Yf_TILED:
10582 ctl |= PLANE_CTL_TILED_YF;
10583 break;
10584 default:
10585 MISSING_CASE(fb->modifier);
10586 }
10587
10588 /*
10589 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10590 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10591 */
10592 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10593 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10594
10595 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
10596 POSTING_READ(PLANE_SURF(pipe, 0));
10597 }
10598
10599 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
10600 struct intel_flip_work *work)
10601 {
10602 struct drm_device *dev = intel_crtc->base.dev;
10603 struct drm_i915_private *dev_priv = to_i915(dev);
10604 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10605 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
10606 u32 dspcntr;
10607
10608 dspcntr = I915_READ(reg);
10609
10610 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
10611 dspcntr |= DISPPLANE_TILED;
10612 else
10613 dspcntr &= ~DISPPLANE_TILED;
10614
10615 I915_WRITE(reg, dspcntr);
10616
10617 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
10618 POSTING_READ(DSPSURF(intel_crtc->plane));
10619 }
10620
10621 static void intel_mmio_flip_work_func(struct work_struct *w)
10622 {
10623 struct intel_flip_work *work =
10624 container_of(w, struct intel_flip_work, mmio_work);
10625 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10626 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10627 struct intel_framebuffer *intel_fb =
10628 to_intel_framebuffer(crtc->base.primary->fb);
10629 struct drm_i915_gem_object *obj = intel_fb->obj;
10630
10631 WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
10632
10633 intel_pipe_update_start(crtc);
10634
10635 if (INTEL_GEN(dev_priv) >= 9)
10636 skl_do_mmio_flip(crtc, work->rotation, work);
10637 else
10638 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10639 ilk_do_mmio_flip(crtc, work);
10640
10641 intel_pipe_update_end(crtc, work);
10642 }
10643
10644 static int intel_default_queue_flip(struct drm_device *dev,
10645 struct drm_crtc *crtc,
10646 struct drm_framebuffer *fb,
10647 struct drm_i915_gem_object *obj,
10648 struct drm_i915_gem_request *req,
10649 uint32_t flags)
10650 {
10651 return -ENODEV;
10652 }
10653
10654 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
10655 struct intel_crtc *intel_crtc,
10656 struct intel_flip_work *work)
10657 {
10658 u32 addr, vblank;
10659
10660 if (!atomic_read(&work->pending))
10661 return false;
10662
10663 smp_rmb();
10664
10665 vblank = intel_crtc_get_vblank_counter(intel_crtc);
10666 if (work->flip_ready_vblank == 0) {
10667 if (work->flip_queued_req &&
10668 !i915_gem_request_completed(work->flip_queued_req))
10669 return false;
10670
10671 work->flip_ready_vblank = vblank;
10672 }
10673
10674 if (vblank - work->flip_ready_vblank < 3)
10675 return false;
10676
10677 /* Potential stall - if we see that the flip has happened,
10678 * assume a missed interrupt. */
10679 if (INTEL_GEN(dev_priv) >= 4)
10680 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10681 else
10682 addr = I915_READ(DSPADDR(intel_crtc->plane));
10683
10684 /* There is a potential issue here with a false positive after a flip
10685 * to the same address. We could address this by checking for a
10686 * non-incrementing frame counter.
10687 */
10688 return addr == work->gtt_offset;
10689 }
10690
10691 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
10692 {
10693 struct drm_device *dev = &dev_priv->drm;
10694 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10695 struct intel_flip_work *work;
10696
10697 WARN_ON(!in_interrupt());
10698
10699 if (crtc == NULL)
10700 return;
10701
10702 spin_lock(&dev->event_lock);
10703 work = crtc->flip_work;
10704
10705 if (work != NULL && !is_mmio_work(work) &&
10706 __pageflip_stall_check_cs(dev_priv, crtc, work)) {
10707 WARN_ONCE(1,
10708 "Kicking stuck page flip: queued at %d, now %d\n",
10709 work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
10710 page_flip_completed(crtc);
10711 work = NULL;
10712 }
10713
10714 if (work != NULL && !is_mmio_work(work) &&
10715 intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
10716 intel_queue_rps_boost_for_request(work->flip_queued_req);
10717 spin_unlock(&dev->event_lock);
10718 }
10719
10720 __maybe_unused
10721 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10722 struct drm_framebuffer *fb,
10723 struct drm_pending_vblank_event *event,
10724 uint32_t page_flip_flags)
10725 {
10726 struct drm_device *dev = crtc->dev;
10727 struct drm_i915_private *dev_priv = to_i915(dev);
10728 struct drm_framebuffer *old_fb = crtc->primary->fb;
10729 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10730 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10731 struct drm_plane *primary = crtc->primary;
10732 enum pipe pipe = intel_crtc->pipe;
10733 struct intel_flip_work *work;
10734 struct intel_engine_cs *engine;
10735 bool mmio_flip;
10736 struct drm_i915_gem_request *request;
10737 struct i915_vma *vma;
10738 int ret;
10739
10740 /*
10741 * drm_mode_page_flip_ioctl() should already catch this, but double
10742 * check to be safe. In the future we may enable pageflipping from
10743 * a disabled primary plane.
10744 */
10745 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10746 return -EBUSY;
10747
10748 /* Can't change pixel format via MI display flips. */
10749 if (fb->format != crtc->primary->fb->format)
10750 return -EINVAL;
10751
10752 /*
10753 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10754 * Note that pitch changes could also affect these register.
10755 */
10756 if (INTEL_GEN(dev_priv) > 3 &&
10757 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10758 fb->pitches[0] != crtc->primary->fb->pitches[0]))
10759 return -EINVAL;
10760
10761 if (i915_terminally_wedged(&dev_priv->gpu_error))
10762 goto out_hang;
10763
10764 work = kzalloc(sizeof(*work), GFP_KERNEL);
10765 if (work == NULL)
10766 return -ENOMEM;
10767
10768 work->event = event;
10769 work->crtc = crtc;
10770 work->old_fb = old_fb;
10771 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
10772
10773 ret = drm_crtc_vblank_get(crtc);
10774 if (ret)
10775 goto free_work;
10776
10777 /* We borrow the event spin lock for protecting flip_work */
10778 spin_lock_irq(&dev->event_lock);
10779 if (intel_crtc->flip_work) {
10780 /* Before declaring the flip queue wedged, check if
10781 * the hardware completed the operation behind our backs.
10782 */
10783 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
10784 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10785 page_flip_completed(intel_crtc);
10786 } else {
10787 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10788 spin_unlock_irq(&dev->event_lock);
10789
10790 drm_crtc_vblank_put(crtc);
10791 kfree(work);
10792 return -EBUSY;
10793 }
10794 }
10795 intel_crtc->flip_work = work;
10796 spin_unlock_irq(&dev->event_lock);
10797
10798 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10799 flush_workqueue(dev_priv->wq);
10800
10801 /* Reference the objects for the scheduled work. */
10802 drm_framebuffer_reference(work->old_fb);
10803
10804 crtc->primary->fb = fb;
10805 update_state_fb(crtc->primary);
10806
10807 work->pending_flip_obj = i915_gem_object_get(obj);
10808
10809 ret = i915_mutex_lock_interruptible(dev);
10810 if (ret)
10811 goto cleanup;
10812
10813 intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
10814 if (i915_reset_backoff_or_wedged(&dev_priv->gpu_error)) {
10815 ret = -EIO;
10816 goto unlock;
10817 }
10818
10819 atomic_inc(&intel_crtc->unpin_work_count);
10820
10821 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
10822 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
10823
10824 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
10825 engine = dev_priv->engine[BCS];
10826 if (fb->modifier != old_fb->modifier)
10827 /* vlv: DISPLAY_FLIP fails to change tiling */
10828 engine = NULL;
10829 } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
10830 engine = dev_priv->engine[BCS];
10831 } else if (INTEL_GEN(dev_priv) >= 7) {
10832 engine = i915_gem_object_last_write_engine(obj);
10833 if (engine == NULL || engine->id != RCS)
10834 engine = dev_priv->engine[BCS];
10835 } else {
10836 engine = dev_priv->engine[RCS];
10837 }
10838
10839 mmio_flip = use_mmio_flip(engine, obj);
10840
10841 vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
10842 if (IS_ERR(vma)) {
10843 ret = PTR_ERR(vma);
10844 goto cleanup_pending;
10845 }
10846
10847 work->old_vma = to_intel_plane_state(primary->state)->vma;
10848 to_intel_plane_state(primary->state)->vma = vma;
10849
10850 work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset;
10851 work->rotation = crtc->primary->state->rotation;
10852
10853 /*
10854 * There's the potential that the next frame will not be compatible with
10855 * FBC, so we want to call pre_update() before the actual page flip.
10856 * The problem is that pre_update() caches some information about the fb
10857 * object, so we want to do this only after the object is pinned. Let's
10858 * be on the safe side and do this immediately before scheduling the
10859 * flip.
10860 */
10861 intel_fbc_pre_update(intel_crtc, intel_crtc->config,
10862 to_intel_plane_state(primary->state));
10863
10864 if (mmio_flip) {
10865 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
10866 queue_work(system_unbound_wq, &work->mmio_work);
10867 } else {
10868 request = i915_gem_request_alloc(engine,
10869 dev_priv->kernel_context);
10870 if (IS_ERR(request)) {
10871 ret = PTR_ERR(request);
10872 goto cleanup_unpin;
10873 }
10874
10875 ret = i915_gem_request_await_object(request, obj, false);
10876 if (ret)
10877 goto cleanup_request;
10878
10879 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
10880 page_flip_flags);
10881 if (ret)
10882 goto cleanup_request;
10883
10884 intel_mark_page_flip_active(intel_crtc, work);
10885
10886 work->flip_queued_req = i915_gem_request_get(request);
10887 i915_add_request(request);
10888 }
10889
10890 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
10891 i915_gem_track_fb(intel_fb_obj(old_fb), obj,
10892 to_intel_plane(primary)->frontbuffer_bit);
10893 mutex_unlock(&dev->struct_mutex);
10894
10895 intel_frontbuffer_flip_prepare(to_i915(dev),
10896 to_intel_plane(primary)->frontbuffer_bit);
10897
10898 trace_i915_flip_request(intel_crtc->plane, obj);
10899
10900 return 0;
10901
10902 cleanup_request:
10903 i915_add_request(request);
10904 cleanup_unpin:
10905 to_intel_plane_state(primary->state)->vma = work->old_vma;
10906 intel_unpin_fb_vma(vma);
10907 cleanup_pending:
10908 atomic_dec(&intel_crtc->unpin_work_count);
10909 unlock:
10910 mutex_unlock(&dev->struct_mutex);
10911 cleanup:
10912 crtc->primary->fb = old_fb;
10913 update_state_fb(crtc->primary);
10914
10915 i915_gem_object_put(obj);
10916 drm_framebuffer_unreference(work->old_fb);
10917
10918 spin_lock_irq(&dev->event_lock);
10919 intel_crtc->flip_work = NULL;
10920 spin_unlock_irq(&dev->event_lock);
10921
10922 drm_crtc_vblank_put(crtc);
10923 free_work:
10924 kfree(work);
10925
10926 if (ret == -EIO) {
10927 struct drm_atomic_state *state;
10928 struct drm_plane_state *plane_state;
10929
10930 out_hang:
10931 state = drm_atomic_state_alloc(dev);
10932 if (!state)
10933 return -ENOMEM;
10934 state->acquire_ctx = dev->mode_config.acquire_ctx;
10935
10936 retry:
10937 plane_state = drm_atomic_get_plane_state(state, primary);
10938 ret = PTR_ERR_OR_ZERO(plane_state);
10939 if (!ret) {
10940 drm_atomic_set_fb_for_plane(plane_state, fb);
10941
10942 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
10943 if (!ret)
10944 ret = drm_atomic_commit(state);
10945 }
10946
10947 if (ret == -EDEADLK) {
10948 drm_modeset_backoff(state->acquire_ctx);
10949 drm_atomic_state_clear(state);
10950 goto retry;
10951 }
10952
10953 drm_atomic_state_put(state);
10954
10955 if (ret == 0 && event) {
10956 spin_lock_irq(&dev->event_lock);
10957 drm_crtc_send_vblank_event(crtc, event);
10958 spin_unlock_irq(&dev->event_lock);
10959 }
10960 }
10961 return ret;
10962 }
10963
10964
10965 /**
10966 * intel_wm_need_update - Check whether watermarks need updating
10967 * @plane: drm plane
10968 * @state: new plane state
10969 *
10970 * Check current plane state versus the new one to determine whether
10971 * watermarks need to be recalculated.
10972 *
10973 * Returns true or false.
10974 */
10975 static bool intel_wm_need_update(struct drm_plane *plane,
10976 struct drm_plane_state *state)
10977 {
10978 struct intel_plane_state *new = to_intel_plane_state(state);
10979 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10980
10981 /* Update watermarks on tiling or size changes. */
10982 if (new->base.visible != cur->base.visible)
10983 return true;
10984
10985 if (!cur->base.fb || !new->base.fb)
10986 return false;
10987
10988 if (cur->base.fb->modifier != new->base.fb->modifier ||
10989 cur->base.rotation != new->base.rotation ||
10990 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10991 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10992 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10993 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10994 return true;
10995
10996 return false;
10997 }
10998
10999 static bool needs_scaling(struct intel_plane_state *state)
11000 {
11001 int src_w = drm_rect_width(&state->base.src) >> 16;
11002 int src_h = drm_rect_height(&state->base.src) >> 16;
11003 int dst_w = drm_rect_width(&state->base.dst);
11004 int dst_h = drm_rect_height(&state->base.dst);
11005
11006 return (src_w != dst_w || src_h != dst_h);
11007 }
11008
11009 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11010 struct drm_plane_state *plane_state)
11011 {
11012 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11013 struct drm_crtc *crtc = crtc_state->crtc;
11014 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11015 struct intel_plane *plane = to_intel_plane(plane_state->plane);
11016 struct drm_device *dev = crtc->dev;
11017 struct drm_i915_private *dev_priv = to_i915(dev);
11018 struct intel_plane_state *old_plane_state =
11019 to_intel_plane_state(plane->base.state);
11020 bool mode_changed = needs_modeset(crtc_state);
11021 bool was_crtc_enabled = crtc->state->active;
11022 bool is_crtc_enabled = crtc_state->active;
11023 bool turn_off, turn_on, visible, was_visible;
11024 struct drm_framebuffer *fb = plane_state->fb;
11025 int ret;
11026
11027 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
11028 ret = skl_update_scaler_plane(
11029 to_intel_crtc_state(crtc_state),
11030 to_intel_plane_state(plane_state));
11031 if (ret)
11032 return ret;
11033 }
11034
11035 was_visible = old_plane_state->base.visible;
11036 visible = plane_state->visible;
11037
11038 if (!was_crtc_enabled && WARN_ON(was_visible))
11039 was_visible = false;
11040
11041 /*
11042 * Visibility is calculated as if the crtc was on, but
11043 * after scaler setup everything depends on it being off
11044 * when the crtc isn't active.
11045 *
11046 * FIXME this is wrong for watermarks. Watermarks should also
11047 * be computed as if the pipe would be active. Perhaps move
11048 * per-plane wm computation to the .check_plane() hook, and
11049 * only combine the results from all planes in the current place?
11050 */
11051 if (!is_crtc_enabled) {
11052 plane_state->visible = visible = false;
11053 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
11054 }
11055
11056 if (!was_visible && !visible)
11057 return 0;
11058
11059 if (fb != old_plane_state->base.fb)
11060 pipe_config->fb_changed = true;
11061
11062 turn_off = was_visible && (!visible || mode_changed);
11063 turn_on = visible && (!was_visible || mode_changed);
11064
11065 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
11066 intel_crtc->base.base.id, intel_crtc->base.name,
11067 plane->base.base.id, plane->base.name,
11068 fb ? fb->base.id : -1);
11069
11070 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11071 plane->base.base.id, plane->base.name,
11072 was_visible, visible,
11073 turn_off, turn_on, mode_changed);
11074
11075 if (turn_on) {
11076 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11077 pipe_config->update_wm_pre = true;
11078
11079 /* must disable cxsr around plane enable/disable */
11080 if (plane->id != PLANE_CURSOR)
11081 pipe_config->disable_cxsr = true;
11082 } else if (turn_off) {
11083 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11084 pipe_config->update_wm_post = true;
11085
11086 /* must disable cxsr around plane enable/disable */
11087 if (plane->id != PLANE_CURSOR)
11088 pipe_config->disable_cxsr = true;
11089 } else if (intel_wm_need_update(&plane->base, plane_state)) {
11090 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
11091 /* FIXME bollocks */
11092 pipe_config->update_wm_pre = true;
11093 pipe_config->update_wm_post = true;
11094 }
11095 }
11096
11097 if (visible || was_visible)
11098 pipe_config->fb_bits |= plane->frontbuffer_bit;
11099
11100 /*
11101 * WaCxSRDisabledForSpriteScaling:ivb
11102 *
11103 * cstate->update_wm was already set above, so this flag will
11104 * take effect when we commit and program watermarks.
11105 */
11106 if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
11107 needs_scaling(to_intel_plane_state(plane_state)) &&
11108 !needs_scaling(old_plane_state))
11109 pipe_config->disable_lp_wm = true;
11110
11111 return 0;
11112 }
11113
11114 static bool encoders_cloneable(const struct intel_encoder *a,
11115 const struct intel_encoder *b)
11116 {
11117 /* masks could be asymmetric, so check both ways */
11118 return a == b || (a->cloneable & (1 << b->type) &&
11119 b->cloneable & (1 << a->type));
11120 }
11121
11122 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11123 struct intel_crtc *crtc,
11124 struct intel_encoder *encoder)
11125 {
11126 struct intel_encoder *source_encoder;
11127 struct drm_connector *connector;
11128 struct drm_connector_state *connector_state;
11129 int i;
11130
11131 for_each_new_connector_in_state(state, connector, connector_state, i) {
11132 if (connector_state->crtc != &crtc->base)
11133 continue;
11134
11135 source_encoder =
11136 to_intel_encoder(connector_state->best_encoder);
11137 if (!encoders_cloneable(encoder, source_encoder))
11138 return false;
11139 }
11140
11141 return true;
11142 }
11143
11144 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11145 struct drm_crtc_state *crtc_state)
11146 {
11147 struct drm_device *dev = crtc->dev;
11148 struct drm_i915_private *dev_priv = to_i915(dev);
11149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11150 struct intel_crtc_state *pipe_config =
11151 to_intel_crtc_state(crtc_state);
11152 struct drm_atomic_state *state = crtc_state->state;
11153 int ret;
11154 bool mode_changed = needs_modeset(crtc_state);
11155
11156 if (mode_changed && !crtc_state->active)
11157 pipe_config->update_wm_post = true;
11158
11159 if (mode_changed && crtc_state->enable &&
11160 dev_priv->display.crtc_compute_clock &&
11161 !WARN_ON(pipe_config->shared_dpll)) {
11162 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11163 pipe_config);
11164 if (ret)
11165 return ret;
11166 }
11167
11168 if (crtc_state->color_mgmt_changed) {
11169 ret = intel_color_check(crtc, crtc_state);
11170 if (ret)
11171 return ret;
11172
11173 /*
11174 * Changing color management on Intel hardware is
11175 * handled as part of planes update.
11176 */
11177 crtc_state->planes_changed = true;
11178 }
11179
11180 ret = 0;
11181 if (dev_priv->display.compute_pipe_wm) {
11182 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11183 if (ret) {
11184 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11185 return ret;
11186 }
11187 }
11188
11189 if (dev_priv->display.compute_intermediate_wm &&
11190 !to_intel_atomic_state(state)->skip_intermediate_wm) {
11191 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11192 return 0;
11193
11194 /*
11195 * Calculate 'intermediate' watermarks that satisfy both the
11196 * old state and the new state. We can program these
11197 * immediately.
11198 */
11199 ret = dev_priv->display.compute_intermediate_wm(dev,
11200 intel_crtc,
11201 pipe_config);
11202 if (ret) {
11203 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11204 return ret;
11205 }
11206 } else if (dev_priv->display.compute_intermediate_wm) {
11207 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
11208 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
11209 }
11210
11211 if (INTEL_GEN(dev_priv) >= 9) {
11212 if (mode_changed)
11213 ret = skl_update_scaler_crtc(pipe_config);
11214
11215 if (!ret)
11216 ret = skl_check_pipe_max_pixel_rate(intel_crtc,
11217 pipe_config);
11218 if (!ret)
11219 ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
11220 pipe_config);
11221 }
11222
11223 return ret;
11224 }
11225
11226 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11227 .atomic_begin = intel_begin_crtc_commit,
11228 .atomic_flush = intel_finish_crtc_commit,
11229 .atomic_check = intel_crtc_atomic_check,
11230 };
11231
11232 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11233 {
11234 struct intel_connector *connector;
11235 struct drm_connector_list_iter conn_iter;
11236
11237 drm_connector_list_iter_begin(dev, &conn_iter);
11238 for_each_intel_connector_iter(connector, &conn_iter) {
11239 if (connector->base.state->crtc)
11240 drm_connector_unreference(&connector->base);
11241
11242 if (connector->base.encoder) {
11243 connector->base.state->best_encoder =
11244 connector->base.encoder;
11245 connector->base.state->crtc =
11246 connector->base.encoder->crtc;
11247
11248 drm_connector_reference(&connector->base);
11249 } else {
11250 connector->base.state->best_encoder = NULL;
11251 connector->base.state->crtc = NULL;
11252 }
11253 }
11254 drm_connector_list_iter_end(&conn_iter);
11255 }
11256
11257 static void
11258 connected_sink_compute_bpp(struct intel_connector *connector,
11259 struct intel_crtc_state *pipe_config)
11260 {
11261 const struct drm_display_info *info = &connector->base.display_info;
11262 int bpp = pipe_config->pipe_bpp;
11263
11264 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11265 connector->base.base.id,
11266 connector->base.name);
11267
11268 /* Don't use an invalid EDID bpc value */
11269 if (info->bpc != 0 && info->bpc * 3 < bpp) {
11270 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11271 bpp, info->bpc * 3);
11272 pipe_config->pipe_bpp = info->bpc * 3;
11273 }
11274
11275 /* Clamp bpp to 8 on screens without EDID 1.4 */
11276 if (info->bpc == 0 && bpp > 24) {
11277 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11278 bpp);
11279 pipe_config->pipe_bpp = 24;
11280 }
11281 }
11282
11283 static int
11284 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11285 struct intel_crtc_state *pipe_config)
11286 {
11287 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11288 struct drm_atomic_state *state;
11289 struct drm_connector *connector;
11290 struct drm_connector_state *connector_state;
11291 int bpp, i;
11292
11293 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
11294 IS_CHERRYVIEW(dev_priv)))
11295 bpp = 10*3;
11296 else if (INTEL_GEN(dev_priv) >= 5)
11297 bpp = 12*3;
11298 else
11299 bpp = 8*3;
11300
11301
11302 pipe_config->pipe_bpp = bpp;
11303
11304 state = pipe_config->base.state;
11305
11306 /* Clamp display bpp to EDID value */
11307 for_each_new_connector_in_state(state, connector, connector_state, i) {
11308 if (connector_state->crtc != &crtc->base)
11309 continue;
11310
11311 connected_sink_compute_bpp(to_intel_connector(connector),
11312 pipe_config);
11313 }
11314
11315 return bpp;
11316 }
11317
11318 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11319 {
11320 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11321 "type: 0x%x flags: 0x%x\n",
11322 mode->crtc_clock,
11323 mode->crtc_hdisplay, mode->crtc_hsync_start,
11324 mode->crtc_hsync_end, mode->crtc_htotal,
11325 mode->crtc_vdisplay, mode->crtc_vsync_start,
11326 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11327 }
11328
11329 static inline void
11330 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
11331 unsigned int lane_count, struct intel_link_m_n *m_n)
11332 {
11333 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11334 id, lane_count,
11335 m_n->gmch_m, m_n->gmch_n,
11336 m_n->link_m, m_n->link_n, m_n->tu);
11337 }
11338
11339 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11340 struct intel_crtc_state *pipe_config,
11341 const char *context)
11342 {
11343 struct drm_device *dev = crtc->base.dev;
11344 struct drm_i915_private *dev_priv = to_i915(dev);
11345 struct drm_plane *plane;
11346 struct intel_plane *intel_plane;
11347 struct intel_plane_state *state;
11348 struct drm_framebuffer *fb;
11349
11350 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
11351 crtc->base.base.id, crtc->base.name, context);
11352
11353 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
11354 transcoder_name(pipe_config->cpu_transcoder),
11355 pipe_config->pipe_bpp, pipe_config->dither);
11356
11357 if (pipe_config->has_pch_encoder)
11358 intel_dump_m_n_config(pipe_config, "fdi",
11359 pipe_config->fdi_lanes,
11360 &pipe_config->fdi_m_n);
11361
11362 if (intel_crtc_has_dp_encoder(pipe_config)) {
11363 intel_dump_m_n_config(pipe_config, "dp m_n",
11364 pipe_config->lane_count, &pipe_config->dp_m_n);
11365 if (pipe_config->has_drrs)
11366 intel_dump_m_n_config(pipe_config, "dp m2_n2",
11367 pipe_config->lane_count,
11368 &pipe_config->dp_m2_n2);
11369 }
11370
11371 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11372 pipe_config->has_audio, pipe_config->has_infoframe);
11373
11374 DRM_DEBUG_KMS("requested mode:\n");
11375 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11376 DRM_DEBUG_KMS("adjusted mode:\n");
11377 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11378 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11379 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
11380 pipe_config->port_clock,
11381 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
11382 pipe_config->pixel_rate);
11383
11384 if (INTEL_GEN(dev_priv) >= 9)
11385 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11386 crtc->num_scalers,
11387 pipe_config->scaler_state.scaler_users,
11388 pipe_config->scaler_state.scaler_id);
11389
11390 if (HAS_GMCH_DISPLAY(dev_priv))
11391 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11392 pipe_config->gmch_pfit.control,
11393 pipe_config->gmch_pfit.pgm_ratios,
11394 pipe_config->gmch_pfit.lvds_border_bits);
11395 else
11396 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11397 pipe_config->pch_pfit.pos,
11398 pipe_config->pch_pfit.size,
11399 enableddisabled(pipe_config->pch_pfit.enabled));
11400
11401 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
11402 pipe_config->ips_enabled, pipe_config->double_wide);
11403
11404 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
11405
11406 DRM_DEBUG_KMS("planes on this crtc\n");
11407 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11408 struct drm_format_name_buf format_name;
11409 intel_plane = to_intel_plane(plane);
11410 if (intel_plane->pipe != crtc->pipe)
11411 continue;
11412
11413 state = to_intel_plane_state(plane->state);
11414 fb = state->base.fb;
11415 if (!fb) {
11416 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
11417 plane->base.id, plane->name, state->scaler_id);
11418 continue;
11419 }
11420
11421 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
11422 plane->base.id, plane->name,
11423 fb->base.id, fb->width, fb->height,
11424 drm_get_format_name(fb->format->format, &format_name));
11425 if (INTEL_GEN(dev_priv) >= 9)
11426 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
11427 state->scaler_id,
11428 state->base.src.x1 >> 16,
11429 state->base.src.y1 >> 16,
11430 drm_rect_width(&state->base.src) >> 16,
11431 drm_rect_height(&state->base.src) >> 16,
11432 state->base.dst.x1, state->base.dst.y1,
11433 drm_rect_width(&state->base.dst),
11434 drm_rect_height(&state->base.dst));
11435 }
11436 }
11437
11438 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11439 {
11440 struct drm_device *dev = state->dev;
11441 struct drm_connector *connector;
11442 struct drm_connector_list_iter conn_iter;
11443 unsigned int used_ports = 0;
11444 unsigned int used_mst_ports = 0;
11445
11446 /*
11447 * Walk the connector list instead of the encoder
11448 * list to detect the problem on ddi platforms
11449 * where there's just one encoder per digital port.
11450 */
11451 drm_connector_list_iter_begin(dev, &conn_iter);
11452 drm_for_each_connector_iter(connector, &conn_iter) {
11453 struct drm_connector_state *connector_state;
11454 struct intel_encoder *encoder;
11455
11456 connector_state = drm_atomic_get_existing_connector_state(state, connector);
11457 if (!connector_state)
11458 connector_state = connector->state;
11459
11460 if (!connector_state->best_encoder)
11461 continue;
11462
11463 encoder = to_intel_encoder(connector_state->best_encoder);
11464
11465 WARN_ON(!connector_state->crtc);
11466
11467 switch (encoder->type) {
11468 unsigned int port_mask;
11469 case INTEL_OUTPUT_UNKNOWN:
11470 if (WARN_ON(!HAS_DDI(to_i915(dev))))
11471 break;
11472 case INTEL_OUTPUT_DP:
11473 case INTEL_OUTPUT_HDMI:
11474 case INTEL_OUTPUT_EDP:
11475 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11476
11477 /* the same port mustn't appear more than once */
11478 if (used_ports & port_mask)
11479 return false;
11480
11481 used_ports |= port_mask;
11482 break;
11483 case INTEL_OUTPUT_DP_MST:
11484 used_mst_ports |=
11485 1 << enc_to_mst(&encoder->base)->primary->port;
11486 break;
11487 default:
11488 break;
11489 }
11490 }
11491 drm_connector_list_iter_end(&conn_iter);
11492
11493 /* can't mix MST and SST/HDMI on the same port */
11494 if (used_ports & used_mst_ports)
11495 return false;
11496
11497 return true;
11498 }
11499
11500 static void
11501 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11502 {
11503 struct drm_i915_private *dev_priv =
11504 to_i915(crtc_state->base.crtc->dev);
11505 struct intel_crtc_scaler_state scaler_state;
11506 struct intel_dpll_hw_state dpll_hw_state;
11507 struct intel_shared_dpll *shared_dpll;
11508 struct intel_crtc_wm_state wm_state;
11509 bool force_thru;
11510
11511 /* FIXME: before the switch to atomic started, a new pipe_config was
11512 * kzalloc'd. Code that depends on any field being zero should be
11513 * fixed, so that the crtc_state can be safely duplicated. For now,
11514 * only fields that are know to not cause problems are preserved. */
11515
11516 scaler_state = crtc_state->scaler_state;
11517 shared_dpll = crtc_state->shared_dpll;
11518 dpll_hw_state = crtc_state->dpll_hw_state;
11519 force_thru = crtc_state->pch_pfit.force_thru;
11520 if (IS_G4X(dev_priv) ||
11521 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11522 wm_state = crtc_state->wm;
11523
11524 /* Keep base drm_crtc_state intact, only clear our extended struct */
11525 BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
11526 memset(&crtc_state->base + 1, 0,
11527 sizeof(*crtc_state) - sizeof(crtc_state->base));
11528
11529 crtc_state->scaler_state = scaler_state;
11530 crtc_state->shared_dpll = shared_dpll;
11531 crtc_state->dpll_hw_state = dpll_hw_state;
11532 crtc_state->pch_pfit.force_thru = force_thru;
11533 if (IS_G4X(dev_priv) ||
11534 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11535 crtc_state->wm = wm_state;
11536 }
11537
11538 static int
11539 intel_modeset_pipe_config(struct drm_crtc *crtc,
11540 struct intel_crtc_state *pipe_config)
11541 {
11542 struct drm_atomic_state *state = pipe_config->base.state;
11543 struct intel_encoder *encoder;
11544 struct drm_connector *connector;
11545 struct drm_connector_state *connector_state;
11546 int base_bpp, ret = -EINVAL;
11547 int i;
11548 bool retry = true;
11549
11550 clear_intel_crtc_state(pipe_config);
11551
11552 pipe_config->cpu_transcoder =
11553 (enum transcoder) to_intel_crtc(crtc)->pipe;
11554
11555 /*
11556 * Sanitize sync polarity flags based on requested ones. If neither
11557 * positive or negative polarity is requested, treat this as meaning
11558 * negative polarity.
11559 */
11560 if (!(pipe_config->base.adjusted_mode.flags &
11561 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11562 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11563
11564 if (!(pipe_config->base.adjusted_mode.flags &
11565 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11566 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11567
11568 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11569 pipe_config);
11570 if (base_bpp < 0)
11571 goto fail;
11572
11573 /*
11574 * Determine the real pipe dimensions. Note that stereo modes can
11575 * increase the actual pipe size due to the frame doubling and
11576 * insertion of additional space for blanks between the frame. This
11577 * is stored in the crtc timings. We use the requested mode to do this
11578 * computation to clearly distinguish it from the adjusted mode, which
11579 * can be changed by the connectors in the below retry loop.
11580 */
11581 drm_mode_get_hv_timing(&pipe_config->base.mode,
11582 &pipe_config->pipe_src_w,
11583 &pipe_config->pipe_src_h);
11584
11585 for_each_new_connector_in_state(state, connector, connector_state, i) {
11586 if (connector_state->crtc != crtc)
11587 continue;
11588
11589 encoder = to_intel_encoder(connector_state->best_encoder);
11590
11591 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11592 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11593 goto fail;
11594 }
11595
11596 /*
11597 * Determine output_types before calling the .compute_config()
11598 * hooks so that the hooks can use this information safely.
11599 */
11600 pipe_config->output_types |= 1 << encoder->type;
11601 }
11602
11603 encoder_retry:
11604 /* Ensure the port clock defaults are reset when retrying. */
11605 pipe_config->port_clock = 0;
11606 pipe_config->pixel_multiplier = 1;
11607
11608 /* Fill in default crtc timings, allow encoders to overwrite them. */
11609 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11610 CRTC_STEREO_DOUBLE);
11611
11612 /* Pass our mode to the connectors and the CRTC to give them a chance to
11613 * adjust it according to limitations or connector properties, and also
11614 * a chance to reject the mode entirely.
11615 */
11616 for_each_new_connector_in_state(state, connector, connector_state, i) {
11617 if (connector_state->crtc != crtc)
11618 continue;
11619
11620 encoder = to_intel_encoder(connector_state->best_encoder);
11621
11622 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
11623 DRM_DEBUG_KMS("Encoder config failure\n");
11624 goto fail;
11625 }
11626 }
11627
11628 /* Set default port clock if not overwritten by the encoder. Needs to be
11629 * done afterwards in case the encoder adjusts the mode. */
11630 if (!pipe_config->port_clock)
11631 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11632 * pipe_config->pixel_multiplier;
11633
11634 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11635 if (ret < 0) {
11636 DRM_DEBUG_KMS("CRTC fixup failed\n");
11637 goto fail;
11638 }
11639
11640 if (ret == RETRY) {
11641 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11642 ret = -EINVAL;
11643 goto fail;
11644 }
11645
11646 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11647 retry = false;
11648 goto encoder_retry;
11649 }
11650
11651 /* Dithering seems to not pass-through bits correctly when it should, so
11652 * only enable it on 6bpc panels and when its not a compliance
11653 * test requesting 6bpc video pattern.
11654 */
11655 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11656 !pipe_config->dither_force_disable;
11657 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11658 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11659
11660 fail:
11661 return ret;
11662 }
11663
11664 static void
11665 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
11666 {
11667 struct drm_crtc *crtc;
11668 struct drm_crtc_state *new_crtc_state;
11669 int i;
11670
11671 /* Double check state. */
11672 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
11673 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
11674
11675 /*
11676 * Update legacy state to satisfy fbc code. This can
11677 * be removed when fbc uses the atomic state.
11678 */
11679 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11680 struct drm_plane_state *plane_state = crtc->primary->state;
11681
11682 crtc->primary->fb = plane_state->fb;
11683 crtc->x = plane_state->src_x >> 16;
11684 crtc->y = plane_state->src_y >> 16;
11685 }
11686 }
11687 }
11688
11689 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11690 {
11691 int diff;
11692
11693 if (clock1 == clock2)
11694 return true;
11695
11696 if (!clock1 || !clock2)
11697 return false;
11698
11699 diff = abs(clock1 - clock2);
11700
11701 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11702 return true;
11703
11704 return false;
11705 }
11706
11707 static bool
11708 intel_compare_m_n(unsigned int m, unsigned int n,
11709 unsigned int m2, unsigned int n2,
11710 bool exact)
11711 {
11712 if (m == m2 && n == n2)
11713 return true;
11714
11715 if (exact || !m || !n || !m2 || !n2)
11716 return false;
11717
11718 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11719
11720 if (n > n2) {
11721 while (n > n2) {
11722 m2 <<= 1;
11723 n2 <<= 1;
11724 }
11725 } else if (n < n2) {
11726 while (n < n2) {
11727 m <<= 1;
11728 n <<= 1;
11729 }
11730 }
11731
11732 if (n != n2)
11733 return false;
11734
11735 return intel_fuzzy_clock_check(m, m2);
11736 }
11737
11738 static bool
11739 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11740 struct intel_link_m_n *m2_n2,
11741 bool adjust)
11742 {
11743 if (m_n->tu == m2_n2->tu &&
11744 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11745 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11746 intel_compare_m_n(m_n->link_m, m_n->link_n,
11747 m2_n2->link_m, m2_n2->link_n, !adjust)) {
11748 if (adjust)
11749 *m2_n2 = *m_n;
11750
11751 return true;
11752 }
11753
11754 return false;
11755 }
11756
11757 static void __printf(3, 4)
11758 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11759 {
11760 char *level;
11761 unsigned int category;
11762 struct va_format vaf;
11763 va_list args;
11764
11765 if (adjust) {
11766 level = KERN_DEBUG;
11767 category = DRM_UT_KMS;
11768 } else {
11769 level = KERN_ERR;
11770 category = DRM_UT_NONE;
11771 }
11772
11773 va_start(args, format);
11774 vaf.fmt = format;
11775 vaf.va = &args;
11776
11777 drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11778
11779 va_end(args);
11780 }
11781
11782 static bool
11783 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11784 struct intel_crtc_state *current_config,
11785 struct intel_crtc_state *pipe_config,
11786 bool adjust)
11787 {
11788 bool ret = true;
11789
11790 #define PIPE_CONF_CHECK_X(name) \
11791 if (current_config->name != pipe_config->name) { \
11792 pipe_config_err(adjust, __stringify(name), \
11793 "(expected 0x%08x, found 0x%08x)\n", \
11794 current_config->name, \
11795 pipe_config->name); \
11796 ret = false; \
11797 }
11798
11799 #define PIPE_CONF_CHECK_I(name) \
11800 if (current_config->name != pipe_config->name) { \
11801 pipe_config_err(adjust, __stringify(name), \
11802 "(expected %i, found %i)\n", \
11803 current_config->name, \
11804 pipe_config->name); \
11805 ret = false; \
11806 }
11807
11808 #define PIPE_CONF_CHECK_P(name) \
11809 if (current_config->name != pipe_config->name) { \
11810 pipe_config_err(adjust, __stringify(name), \
11811 "(expected %p, found %p)\n", \
11812 current_config->name, \
11813 pipe_config->name); \
11814 ret = false; \
11815 }
11816
11817 #define PIPE_CONF_CHECK_M_N(name) \
11818 if (!intel_compare_link_m_n(&current_config->name, \
11819 &pipe_config->name,\
11820 adjust)) { \
11821 pipe_config_err(adjust, __stringify(name), \
11822 "(expected tu %i gmch %i/%i link %i/%i, " \
11823 "found tu %i, gmch %i/%i link %i/%i)\n", \
11824 current_config->name.tu, \
11825 current_config->name.gmch_m, \
11826 current_config->name.gmch_n, \
11827 current_config->name.link_m, \
11828 current_config->name.link_n, \
11829 pipe_config->name.tu, \
11830 pipe_config->name.gmch_m, \
11831 pipe_config->name.gmch_n, \
11832 pipe_config->name.link_m, \
11833 pipe_config->name.link_n); \
11834 ret = false; \
11835 }
11836
11837 /* This is required for BDW+ where there is only one set of registers for
11838 * switching between high and low RR.
11839 * This macro can be used whenever a comparison has to be made between one
11840 * hw state and multiple sw state variables.
11841 */
11842 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11843 if (!intel_compare_link_m_n(&current_config->name, \
11844 &pipe_config->name, adjust) && \
11845 !intel_compare_link_m_n(&current_config->alt_name, \
11846 &pipe_config->name, adjust)) { \
11847 pipe_config_err(adjust, __stringify(name), \
11848 "(expected tu %i gmch %i/%i link %i/%i, " \
11849 "or tu %i gmch %i/%i link %i/%i, " \
11850 "found tu %i, gmch %i/%i link %i/%i)\n", \
11851 current_config->name.tu, \
11852 current_config->name.gmch_m, \
11853 current_config->name.gmch_n, \
11854 current_config->name.link_m, \
11855 current_config->name.link_n, \
11856 current_config->alt_name.tu, \
11857 current_config->alt_name.gmch_m, \
11858 current_config->alt_name.gmch_n, \
11859 current_config->alt_name.link_m, \
11860 current_config->alt_name.link_n, \
11861 pipe_config->name.tu, \
11862 pipe_config->name.gmch_m, \
11863 pipe_config->name.gmch_n, \
11864 pipe_config->name.link_m, \
11865 pipe_config->name.link_n); \
11866 ret = false; \
11867 }
11868
11869 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11870 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11871 pipe_config_err(adjust, __stringify(name), \
11872 "(%x) (expected %i, found %i)\n", \
11873 (mask), \
11874 current_config->name & (mask), \
11875 pipe_config->name & (mask)); \
11876 ret = false; \
11877 }
11878
11879 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11880 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11881 pipe_config_err(adjust, __stringify(name), \
11882 "(expected %i, found %i)\n", \
11883 current_config->name, \
11884 pipe_config->name); \
11885 ret = false; \
11886 }
11887
11888 #define PIPE_CONF_QUIRK(quirk) \
11889 ((current_config->quirks | pipe_config->quirks) & (quirk))
11890
11891 PIPE_CONF_CHECK_I(cpu_transcoder);
11892
11893 PIPE_CONF_CHECK_I(has_pch_encoder);
11894 PIPE_CONF_CHECK_I(fdi_lanes);
11895 PIPE_CONF_CHECK_M_N(fdi_m_n);
11896
11897 PIPE_CONF_CHECK_I(lane_count);
11898 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11899
11900 if (INTEL_GEN(dev_priv) < 8) {
11901 PIPE_CONF_CHECK_M_N(dp_m_n);
11902
11903 if (current_config->has_drrs)
11904 PIPE_CONF_CHECK_M_N(dp_m2_n2);
11905 } else
11906 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11907
11908 PIPE_CONF_CHECK_X(output_types);
11909
11910 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11911 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11912 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11913 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11914 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11915 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11916
11917 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11918 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11919 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11920 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11921 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11922 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11923
11924 PIPE_CONF_CHECK_I(pixel_multiplier);
11925 PIPE_CONF_CHECK_I(has_hdmi_sink);
11926 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11927 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11928 PIPE_CONF_CHECK_I(limited_color_range);
11929
11930 PIPE_CONF_CHECK_I(hdmi_scrambling);
11931 PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio);
11932 PIPE_CONF_CHECK_I(has_infoframe);
11933
11934 PIPE_CONF_CHECK_I(has_audio);
11935
11936 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11937 DRM_MODE_FLAG_INTERLACE);
11938
11939 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11940 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11941 DRM_MODE_FLAG_PHSYNC);
11942 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11943 DRM_MODE_FLAG_NHSYNC);
11944 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11945 DRM_MODE_FLAG_PVSYNC);
11946 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11947 DRM_MODE_FLAG_NVSYNC);
11948 }
11949
11950 PIPE_CONF_CHECK_X(gmch_pfit.control);
11951 /* pfit ratios are autocomputed by the hw on gen4+ */
11952 if (INTEL_GEN(dev_priv) < 4)
11953 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11954 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11955
11956 if (!adjust) {
11957 PIPE_CONF_CHECK_I(pipe_src_w);
11958 PIPE_CONF_CHECK_I(pipe_src_h);
11959
11960 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11961 if (current_config->pch_pfit.enabled) {
11962 PIPE_CONF_CHECK_X(pch_pfit.pos);
11963 PIPE_CONF_CHECK_X(pch_pfit.size);
11964 }
11965
11966 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11967 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11968 }
11969
11970 /* BDW+ don't expose a synchronous way to read the state */
11971 if (IS_HASWELL(dev_priv))
11972 PIPE_CONF_CHECK_I(ips_enabled);
11973
11974 PIPE_CONF_CHECK_I(double_wide);
11975
11976 PIPE_CONF_CHECK_P(shared_dpll);
11977 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11978 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11979 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11980 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11981 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11982 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11983 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11984 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11985 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11986
11987 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11988 PIPE_CONF_CHECK_X(dsi_pll.div);
11989
11990 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11991 PIPE_CONF_CHECK_I(pipe_bpp);
11992
11993 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11994 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11995
11996 #undef PIPE_CONF_CHECK_X
11997 #undef PIPE_CONF_CHECK_I
11998 #undef PIPE_CONF_CHECK_P
11999 #undef PIPE_CONF_CHECK_FLAGS
12000 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12001 #undef PIPE_CONF_QUIRK
12002
12003 return ret;
12004 }
12005
12006 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12007 const struct intel_crtc_state *pipe_config)
12008 {
12009 if (pipe_config->has_pch_encoder) {
12010 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12011 &pipe_config->fdi_m_n);
12012 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12013
12014 /*
12015 * FDI already provided one idea for the dotclock.
12016 * Yell if the encoder disagrees.
12017 */
12018 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12019 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12020 fdi_dotclock, dotclock);
12021 }
12022 }
12023
12024 static void verify_wm_state(struct drm_crtc *crtc,
12025 struct drm_crtc_state *new_state)
12026 {
12027 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
12028 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12029 struct skl_pipe_wm hw_wm, *sw_wm;
12030 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
12031 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
12032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12033 const enum pipe pipe = intel_crtc->pipe;
12034 int plane, level, max_level = ilk_wm_max_level(dev_priv);
12035
12036 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
12037 return;
12038
12039 skl_pipe_wm_get_hw_state(crtc, &hw_wm);
12040 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
12041
12042 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12043 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12044
12045 /* planes */
12046 for_each_universal_plane(dev_priv, pipe, plane) {
12047 hw_plane_wm = &hw_wm.planes[plane];
12048 sw_plane_wm = &sw_wm->planes[plane];
12049
12050 /* Watermarks */
12051 for (level = 0; level <= max_level; level++) {
12052 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
12053 &sw_plane_wm->wm[level]))
12054 continue;
12055
12056 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12057 pipe_name(pipe), plane + 1, level,
12058 sw_plane_wm->wm[level].plane_en,
12059 sw_plane_wm->wm[level].plane_res_b,
12060 sw_plane_wm->wm[level].plane_res_l,
12061 hw_plane_wm->wm[level].plane_en,
12062 hw_plane_wm->wm[level].plane_res_b,
12063 hw_plane_wm->wm[level].plane_res_l);
12064 }
12065
12066 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
12067 &sw_plane_wm->trans_wm)) {
12068 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12069 pipe_name(pipe), plane + 1,
12070 sw_plane_wm->trans_wm.plane_en,
12071 sw_plane_wm->trans_wm.plane_res_b,
12072 sw_plane_wm->trans_wm.plane_res_l,
12073 hw_plane_wm->trans_wm.plane_en,
12074 hw_plane_wm->trans_wm.plane_res_b,
12075 hw_plane_wm->trans_wm.plane_res_l);
12076 }
12077
12078 /* DDB */
12079 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
12080 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
12081
12082 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
12083 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
12084 pipe_name(pipe), plane + 1,
12085 sw_ddb_entry->start, sw_ddb_entry->end,
12086 hw_ddb_entry->start, hw_ddb_entry->end);
12087 }
12088 }
12089
12090 /*
12091 * cursor
12092 * If the cursor plane isn't active, we may not have updated it's ddb
12093 * allocation. In that case since the ddb allocation will be updated
12094 * once the plane becomes visible, we can skip this check
12095 */
12096 if (1) {
12097 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
12098 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
12099
12100 /* Watermarks */
12101 for (level = 0; level <= max_level; level++) {
12102 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
12103 &sw_plane_wm->wm[level]))
12104 continue;
12105
12106 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12107 pipe_name(pipe), level,
12108 sw_plane_wm->wm[level].plane_en,
12109 sw_plane_wm->wm[level].plane_res_b,
12110 sw_plane_wm->wm[level].plane_res_l,
12111 hw_plane_wm->wm[level].plane_en,
12112 hw_plane_wm->wm[level].plane_res_b,
12113 hw_plane_wm->wm[level].plane_res_l);
12114 }
12115
12116 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
12117 &sw_plane_wm->trans_wm)) {
12118 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12119 pipe_name(pipe),
12120 sw_plane_wm->trans_wm.plane_en,
12121 sw_plane_wm->trans_wm.plane_res_b,
12122 sw_plane_wm->trans_wm.plane_res_l,
12123 hw_plane_wm->trans_wm.plane_en,
12124 hw_plane_wm->trans_wm.plane_res_b,
12125 hw_plane_wm->trans_wm.plane_res_l);
12126 }
12127
12128 /* DDB */
12129 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12130 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12131
12132 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
12133 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
12134 pipe_name(pipe),
12135 sw_ddb_entry->start, sw_ddb_entry->end,
12136 hw_ddb_entry->start, hw_ddb_entry->end);
12137 }
12138 }
12139 }
12140
12141 static void
12142 verify_connector_state(struct drm_device *dev,
12143 struct drm_atomic_state *state,
12144 struct drm_crtc *crtc)
12145 {
12146 struct drm_connector *connector;
12147 struct drm_connector_state *new_conn_state;
12148 int i;
12149
12150 for_each_new_connector_in_state(state, connector, new_conn_state, i) {
12151 struct drm_encoder *encoder = connector->encoder;
12152 struct drm_crtc_state *crtc_state = NULL;
12153
12154 if (new_conn_state->crtc != crtc)
12155 continue;
12156
12157 if (crtc)
12158 crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
12159
12160 intel_connector_verify_state(crtc_state, new_conn_state);
12161
12162 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
12163 "connector's atomic encoder doesn't match legacy encoder\n");
12164 }
12165 }
12166
12167 static void
12168 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
12169 {
12170 struct intel_encoder *encoder;
12171 struct drm_connector *connector;
12172 struct drm_connector_state *old_conn_state, *new_conn_state;
12173 int i;
12174
12175 for_each_intel_encoder(dev, encoder) {
12176 bool enabled = false, found = false;
12177 enum pipe pipe;
12178
12179 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12180 encoder->base.base.id,
12181 encoder->base.name);
12182
12183 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
12184 new_conn_state, i) {
12185 if (old_conn_state->best_encoder == &encoder->base)
12186 found = true;
12187
12188 if (new_conn_state->best_encoder != &encoder->base)
12189 continue;
12190 found = enabled = true;
12191
12192 I915_STATE_WARN(new_conn_state->crtc !=
12193 encoder->base.crtc,
12194 "connector's crtc doesn't match encoder crtc\n");
12195 }
12196
12197 if (!found)
12198 continue;
12199
12200 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12201 "encoder's enabled state mismatch "
12202 "(expected %i, found %i)\n",
12203 !!encoder->base.crtc, enabled);
12204
12205 if (!encoder->base.crtc) {
12206 bool active;
12207
12208 active = encoder->get_hw_state(encoder, &pipe);
12209 I915_STATE_WARN(active,
12210 "encoder detached but still enabled on pipe %c.\n",
12211 pipe_name(pipe));
12212 }
12213 }
12214 }
12215
12216 static void
12217 verify_crtc_state(struct drm_crtc *crtc,
12218 struct drm_crtc_state *old_crtc_state,
12219 struct drm_crtc_state *new_crtc_state)
12220 {
12221 struct drm_device *dev = crtc->dev;
12222 struct drm_i915_private *dev_priv = to_i915(dev);
12223 struct intel_encoder *encoder;
12224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12225 struct intel_crtc_state *pipe_config, *sw_config;
12226 struct drm_atomic_state *old_state;
12227 bool active;
12228
12229 old_state = old_crtc_state->state;
12230 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
12231 pipe_config = to_intel_crtc_state(old_crtc_state);
12232 memset(pipe_config, 0, sizeof(*pipe_config));
12233 pipe_config->base.crtc = crtc;
12234 pipe_config->base.state = old_state;
12235
12236 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
12237
12238 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12239
12240 /* we keep both pipes enabled on 830 */
12241 if (IS_I830(dev_priv))
12242 active = new_crtc_state->active;
12243
12244 I915_STATE_WARN(new_crtc_state->active != active,
12245 "crtc active state doesn't match with hw state "
12246 "(expected %i, found %i)\n", new_crtc_state->active, active);
12247
12248 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12249 "transitional active state does not match atomic hw state "
12250 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12251
12252 for_each_encoder_on_crtc(dev, crtc, encoder) {
12253 enum pipe pipe;
12254
12255 active = encoder->get_hw_state(encoder, &pipe);
12256 I915_STATE_WARN(active != new_crtc_state->active,
12257 "[ENCODER:%i] active %i with crtc active %i\n",
12258 encoder->base.base.id, active, new_crtc_state->active);
12259
12260 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12261 "Encoder connected to wrong pipe %c\n",
12262 pipe_name(pipe));
12263
12264 if (active) {
12265 pipe_config->output_types |= 1 << encoder->type;
12266 encoder->get_config(encoder, pipe_config);
12267 }
12268 }
12269
12270 intel_crtc_compute_pixel_rate(pipe_config);
12271
12272 if (!new_crtc_state->active)
12273 return;
12274
12275 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12276
12277 sw_config = to_intel_crtc_state(new_crtc_state);
12278 if (!intel_pipe_config_compare(dev_priv, sw_config,
12279 pipe_config, false)) {
12280 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12281 intel_dump_pipe_config(intel_crtc, pipe_config,
12282 "[hw state]");
12283 intel_dump_pipe_config(intel_crtc, sw_config,
12284 "[sw state]");
12285 }
12286 }
12287
12288 static void
12289 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12290 struct intel_shared_dpll *pll,
12291 struct drm_crtc *crtc,
12292 struct drm_crtc_state *new_state)
12293 {
12294 struct intel_dpll_hw_state dpll_hw_state;
12295 unsigned crtc_mask;
12296 bool active;
12297
12298 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12299
12300 DRM_DEBUG_KMS("%s\n", pll->name);
12301
12302 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12303
12304 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12305 I915_STATE_WARN(!pll->on && pll->active_mask,
12306 "pll in active use but not on in sw tracking\n");
12307 I915_STATE_WARN(pll->on && !pll->active_mask,
12308 "pll is on but not used by any active crtc\n");
12309 I915_STATE_WARN(pll->on != active,
12310 "pll on state mismatch (expected %i, found %i)\n",
12311 pll->on, active);
12312 }
12313
12314 if (!crtc) {
12315 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
12316 "more active pll users than references: %x vs %x\n",
12317 pll->active_mask, pll->state.crtc_mask);
12318
12319 return;
12320 }
12321
12322 crtc_mask = 1 << drm_crtc_index(crtc);
12323
12324 if (new_state->active)
12325 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12326 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12327 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12328 else
12329 I915_STATE_WARN(pll->active_mask & crtc_mask,
12330 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12331 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12332
12333 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
12334 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12335 crtc_mask, pll->state.crtc_mask);
12336
12337 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
12338 &dpll_hw_state,
12339 sizeof(dpll_hw_state)),
12340 "pll hw state mismatch\n");
12341 }
12342
12343 static void
12344 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12345 struct drm_crtc_state *old_crtc_state,
12346 struct drm_crtc_state *new_crtc_state)
12347 {
12348 struct drm_i915_private *dev_priv = to_i915(dev);
12349 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12350 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12351
12352 if (new_state->shared_dpll)
12353 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
12354
12355 if (old_state->shared_dpll &&
12356 old_state->shared_dpll != new_state->shared_dpll) {
12357 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
12358 struct intel_shared_dpll *pll = old_state->shared_dpll;
12359
12360 I915_STATE_WARN(pll->active_mask & crtc_mask,
12361 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12362 pipe_name(drm_crtc_index(crtc)));
12363 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
12364 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12365 pipe_name(drm_crtc_index(crtc)));
12366 }
12367 }
12368
12369 static void
12370 intel_modeset_verify_crtc(struct drm_crtc *crtc,
12371 struct drm_atomic_state *state,
12372 struct drm_crtc_state *old_state,
12373 struct drm_crtc_state *new_state)
12374 {
12375 if (!needs_modeset(new_state) &&
12376 !to_intel_crtc_state(new_state)->update_pipe)
12377 return;
12378
12379 verify_wm_state(crtc, new_state);
12380 verify_connector_state(crtc->dev, state, crtc);
12381 verify_crtc_state(crtc, old_state, new_state);
12382 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
12383 }
12384
12385 static void
12386 verify_disabled_dpll_state(struct drm_device *dev)
12387 {
12388 struct drm_i915_private *dev_priv = to_i915(dev);
12389 int i;
12390
12391 for (i = 0; i < dev_priv->num_shared_dpll; i++)
12392 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12393 }
12394
12395 static void
12396 intel_modeset_verify_disabled(struct drm_device *dev,
12397 struct drm_atomic_state *state)
12398 {
12399 verify_encoder_state(dev, state);
12400 verify_connector_state(dev, state, NULL);
12401 verify_disabled_dpll_state(dev);
12402 }
12403
12404 static void update_scanline_offset(struct intel_crtc *crtc)
12405 {
12406 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12407
12408 /*
12409 * The scanline counter increments at the leading edge of hsync.
12410 *
12411 * On most platforms it starts counting from vtotal-1 on the
12412 * first active line. That means the scanline counter value is
12413 * always one less than what we would expect. Ie. just after
12414 * start of vblank, which also occurs at start of hsync (on the
12415 * last active line), the scanline counter will read vblank_start-1.
12416 *
12417 * On gen2 the scanline counter starts counting from 1 instead
12418 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12419 * to keep the value positive), instead of adding one.
12420 *
12421 * On HSW+ the behaviour of the scanline counter depends on the output
12422 * type. For DP ports it behaves like most other platforms, but on HDMI
12423 * there's an extra 1 line difference. So we need to add two instead of
12424 * one to the value.
12425 *
12426 * On VLV/CHV DSI the scanline counter would appear to increment
12427 * approx. 1/3 of a scanline before start of vblank. Unfortunately
12428 * that means we can't tell whether we're in vblank or not while
12429 * we're on that particular line. We must still set scanline_offset
12430 * to 1 so that the vblank timestamps come out correct when we query
12431 * the scanline counter from within the vblank interrupt handler.
12432 * However if queried just before the start of vblank we'll get an
12433 * answer that's slightly in the future.
12434 */
12435 if (IS_GEN2(dev_priv)) {
12436 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12437 int vtotal;
12438
12439 vtotal = adjusted_mode->crtc_vtotal;
12440 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12441 vtotal /= 2;
12442
12443 crtc->scanline_offset = vtotal - 1;
12444 } else if (HAS_DDI(dev_priv) &&
12445 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
12446 crtc->scanline_offset = 2;
12447 } else
12448 crtc->scanline_offset = 1;
12449 }
12450
12451 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12452 {
12453 struct drm_device *dev = state->dev;
12454 struct drm_i915_private *dev_priv = to_i915(dev);
12455 struct drm_crtc *crtc;
12456 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12457 int i;
12458
12459 if (!dev_priv->display.crtc_compute_clock)
12460 return;
12461
12462 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12464 struct intel_shared_dpll *old_dpll =
12465 to_intel_crtc_state(old_crtc_state)->shared_dpll;
12466
12467 if (!needs_modeset(new_crtc_state))
12468 continue;
12469
12470 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
12471
12472 if (!old_dpll)
12473 continue;
12474
12475 intel_release_shared_dpll(old_dpll, intel_crtc, state);
12476 }
12477 }
12478
12479 /*
12480 * This implements the workaround described in the "notes" section of the mode
12481 * set sequence documentation. When going from no pipes or single pipe to
12482 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12483 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12484 */
12485 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12486 {
12487 struct drm_crtc_state *crtc_state;
12488 struct intel_crtc *intel_crtc;
12489 struct drm_crtc *crtc;
12490 struct intel_crtc_state *first_crtc_state = NULL;
12491 struct intel_crtc_state *other_crtc_state = NULL;
12492 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12493 int i;
12494
12495 /* look at all crtc's that are going to be enabled in during modeset */
12496 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12497 intel_crtc = to_intel_crtc(crtc);
12498
12499 if (!crtc_state->active || !needs_modeset(crtc_state))
12500 continue;
12501
12502 if (first_crtc_state) {
12503 other_crtc_state = to_intel_crtc_state(crtc_state);
12504 break;
12505 } else {
12506 first_crtc_state = to_intel_crtc_state(crtc_state);
12507 first_pipe = intel_crtc->pipe;
12508 }
12509 }
12510
12511 /* No workaround needed? */
12512 if (!first_crtc_state)
12513 return 0;
12514
12515 /* w/a possibly needed, check how many crtc's are already enabled. */
12516 for_each_intel_crtc(state->dev, intel_crtc) {
12517 struct intel_crtc_state *pipe_config;
12518
12519 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12520 if (IS_ERR(pipe_config))
12521 return PTR_ERR(pipe_config);
12522
12523 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12524
12525 if (!pipe_config->base.active ||
12526 needs_modeset(&pipe_config->base))
12527 continue;
12528
12529 /* 2 or more enabled crtcs means no need for w/a */
12530 if (enabled_pipe != INVALID_PIPE)
12531 return 0;
12532
12533 enabled_pipe = intel_crtc->pipe;
12534 }
12535
12536 if (enabled_pipe != INVALID_PIPE)
12537 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12538 else if (other_crtc_state)
12539 other_crtc_state->hsw_workaround_pipe = first_pipe;
12540
12541 return 0;
12542 }
12543
12544 static int intel_lock_all_pipes(struct drm_atomic_state *state)
12545 {
12546 struct drm_crtc *crtc;
12547
12548 /* Add all pipes to the state */
12549 for_each_crtc(state->dev, crtc) {
12550 struct drm_crtc_state *crtc_state;
12551
12552 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12553 if (IS_ERR(crtc_state))
12554 return PTR_ERR(crtc_state);
12555 }
12556
12557 return 0;
12558 }
12559
12560 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12561 {
12562 struct drm_crtc *crtc;
12563
12564 /*
12565 * Add all pipes to the state, and force
12566 * a modeset on all the active ones.
12567 */
12568 for_each_crtc(state->dev, crtc) {
12569 struct drm_crtc_state *crtc_state;
12570 int ret;
12571
12572 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12573 if (IS_ERR(crtc_state))
12574 return PTR_ERR(crtc_state);
12575
12576 if (!crtc_state->active || needs_modeset(crtc_state))
12577 continue;
12578
12579 crtc_state->mode_changed = true;
12580
12581 ret = drm_atomic_add_affected_connectors(state, crtc);
12582 if (ret)
12583 return ret;
12584
12585 ret = drm_atomic_add_affected_planes(state, crtc);
12586 if (ret)
12587 return ret;
12588 }
12589
12590 return 0;
12591 }
12592
12593 static int intel_modeset_checks(struct drm_atomic_state *state)
12594 {
12595 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12596 struct drm_i915_private *dev_priv = to_i915(state->dev);
12597 struct drm_crtc *crtc;
12598 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12599 int ret = 0, i;
12600
12601 if (!check_digital_port_conflicts(state)) {
12602 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12603 return -EINVAL;
12604 }
12605
12606 intel_state->modeset = true;
12607 intel_state->active_crtcs = dev_priv->active_crtcs;
12608 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12609 intel_state->cdclk.actual = dev_priv->cdclk.actual;
12610
12611 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12612 if (new_crtc_state->active)
12613 intel_state->active_crtcs |= 1 << i;
12614 else
12615 intel_state->active_crtcs &= ~(1 << i);
12616
12617 if (old_crtc_state->active != new_crtc_state->active)
12618 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12619 }
12620
12621 /*
12622 * See if the config requires any additional preparation, e.g.
12623 * to adjust global state with pipes off. We need to do this
12624 * here so we can get the modeset_pipe updated config for the new
12625 * mode set on this crtc. For other crtcs we need to use the
12626 * adjusted_mode bits in the crtc directly.
12627 */
12628 if (dev_priv->display.modeset_calc_cdclk) {
12629 ret = dev_priv->display.modeset_calc_cdclk(state);
12630 if (ret < 0)
12631 return ret;
12632
12633 /*
12634 * Writes to dev_priv->cdclk.logical must protected by
12635 * holding all the crtc locks, even if we don't end up
12636 * touching the hardware
12637 */
12638 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
12639 &intel_state->cdclk.logical)) {
12640 ret = intel_lock_all_pipes(state);
12641 if (ret < 0)
12642 return ret;
12643 }
12644
12645 /* All pipes must be switched off while we change the cdclk. */
12646 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
12647 &intel_state->cdclk.actual)) {
12648 ret = intel_modeset_all_pipes(state);
12649 if (ret < 0)
12650 return ret;
12651 }
12652
12653 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12654 intel_state->cdclk.logical.cdclk,
12655 intel_state->cdclk.actual.cdclk);
12656 } else {
12657 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12658 }
12659
12660 intel_modeset_clear_plls(state);
12661
12662 if (IS_HASWELL(dev_priv))
12663 return haswell_mode_set_planes_workaround(state);
12664
12665 return 0;
12666 }
12667
12668 /*
12669 * Handle calculation of various watermark data at the end of the atomic check
12670 * phase. The code here should be run after the per-crtc and per-plane 'check'
12671 * handlers to ensure that all derived state has been updated.
12672 */
12673 static int calc_watermark_data(struct drm_atomic_state *state)
12674 {
12675 struct drm_device *dev = state->dev;
12676 struct drm_i915_private *dev_priv = to_i915(dev);
12677
12678 /* Is there platform-specific watermark information to calculate? */
12679 if (dev_priv->display.compute_global_watermarks)
12680 return dev_priv->display.compute_global_watermarks(state);
12681
12682 return 0;
12683 }
12684
12685 /**
12686 * intel_atomic_check - validate state object
12687 * @dev: drm device
12688 * @state: state to validate
12689 */
12690 static int intel_atomic_check(struct drm_device *dev,
12691 struct drm_atomic_state *state)
12692 {
12693 struct drm_i915_private *dev_priv = to_i915(dev);
12694 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12695 struct drm_crtc *crtc;
12696 struct drm_crtc_state *old_crtc_state, *crtc_state;
12697 int ret, i;
12698 bool any_ms = false;
12699
12700 ret = drm_atomic_helper_check_modeset(dev, state);
12701 if (ret)
12702 return ret;
12703
12704 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12705 struct intel_crtc_state *pipe_config =
12706 to_intel_crtc_state(crtc_state);
12707
12708 /* Catch I915_MODE_FLAG_INHERITED */
12709 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
12710 crtc_state->mode_changed = true;
12711
12712 if (!needs_modeset(crtc_state))
12713 continue;
12714
12715 if (!crtc_state->enable) {
12716 any_ms = true;
12717 continue;
12718 }
12719
12720 /* FIXME: For only active_changed we shouldn't need to do any
12721 * state recomputation at all. */
12722
12723 ret = drm_atomic_add_affected_connectors(state, crtc);
12724 if (ret)
12725 return ret;
12726
12727 ret = intel_modeset_pipe_config(crtc, pipe_config);
12728 if (ret) {
12729 intel_dump_pipe_config(to_intel_crtc(crtc),
12730 pipe_config, "[failed]");
12731 return ret;
12732 }
12733
12734 if (i915.fastboot &&
12735 intel_pipe_config_compare(dev_priv,
12736 to_intel_crtc_state(old_crtc_state),
12737 pipe_config, true)) {
12738 crtc_state->mode_changed = false;
12739 pipe_config->update_pipe = true;
12740 }
12741
12742 if (needs_modeset(crtc_state))
12743 any_ms = true;
12744
12745 ret = drm_atomic_add_affected_planes(state, crtc);
12746 if (ret)
12747 return ret;
12748
12749 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12750 needs_modeset(crtc_state) ?
12751 "[modeset]" : "[fastset]");
12752 }
12753
12754 if (any_ms) {
12755 ret = intel_modeset_checks(state);
12756
12757 if (ret)
12758 return ret;
12759 } else {
12760 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12761 }
12762
12763 ret = drm_atomic_helper_check_planes(dev, state);
12764 if (ret)
12765 return ret;
12766
12767 intel_fbc_choose_crtc(dev_priv, state);
12768 return calc_watermark_data(state);
12769 }
12770
12771 static int intel_atomic_prepare_commit(struct drm_device *dev,
12772 struct drm_atomic_state *state)
12773 {
12774 struct drm_i915_private *dev_priv = to_i915(dev);
12775 struct drm_crtc_state *crtc_state;
12776 struct drm_crtc *crtc;
12777 int i, ret;
12778
12779 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12780 if (state->legacy_cursor_update)
12781 continue;
12782
12783 ret = intel_crtc_wait_for_pending_flips(crtc);
12784 if (ret)
12785 return ret;
12786
12787 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
12788 flush_workqueue(dev_priv->wq);
12789 }
12790
12791 ret = mutex_lock_interruptible(&dev->struct_mutex);
12792 if (ret)
12793 return ret;
12794
12795 ret = drm_atomic_helper_prepare_planes(dev, state);
12796 mutex_unlock(&dev->struct_mutex);
12797
12798 return ret;
12799 }
12800
12801 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12802 {
12803 struct drm_device *dev = crtc->base.dev;
12804
12805 if (!dev->max_vblank_count)
12806 return drm_accurate_vblank_count(&crtc->base);
12807
12808 return dev->driver->get_vblank_counter(dev, crtc->pipe);
12809 }
12810
12811 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
12812 struct drm_i915_private *dev_priv,
12813 unsigned crtc_mask)
12814 {
12815 unsigned last_vblank_count[I915_MAX_PIPES];
12816 enum pipe pipe;
12817 int ret;
12818
12819 if (!crtc_mask)
12820 return;
12821
12822 for_each_pipe(dev_priv, pipe) {
12823 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12824 pipe);
12825
12826 if (!((1 << pipe) & crtc_mask))
12827 continue;
12828
12829 ret = drm_crtc_vblank_get(&crtc->base);
12830 if (WARN_ON(ret != 0)) {
12831 crtc_mask &= ~(1 << pipe);
12832 continue;
12833 }
12834
12835 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
12836 }
12837
12838 for_each_pipe(dev_priv, pipe) {
12839 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12840 pipe);
12841 long lret;
12842
12843 if (!((1 << pipe) & crtc_mask))
12844 continue;
12845
12846 lret = wait_event_timeout(dev->vblank[pipe].queue,
12847 last_vblank_count[pipe] !=
12848 drm_crtc_vblank_count(&crtc->base),
12849 msecs_to_jiffies(50));
12850
12851 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
12852
12853 drm_crtc_vblank_put(&crtc->base);
12854 }
12855 }
12856
12857 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
12858 {
12859 /* fb updated, need to unpin old fb */
12860 if (crtc_state->fb_changed)
12861 return true;
12862
12863 /* wm changes, need vblank before final wm's */
12864 if (crtc_state->update_wm_post)
12865 return true;
12866
12867 if (crtc_state->wm.need_postvbl_update)
12868 return true;
12869
12870 return false;
12871 }
12872
12873 static void intel_update_crtc(struct drm_crtc *crtc,
12874 struct drm_atomic_state *state,
12875 struct drm_crtc_state *old_crtc_state,
12876 struct drm_crtc_state *new_crtc_state,
12877 unsigned int *crtc_vblank_mask)
12878 {
12879 struct drm_device *dev = crtc->dev;
12880 struct drm_i915_private *dev_priv = to_i915(dev);
12881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12882 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12883 bool modeset = needs_modeset(new_crtc_state);
12884
12885 if (modeset) {
12886 update_scanline_offset(intel_crtc);
12887 dev_priv->display.crtc_enable(pipe_config, state);
12888 } else {
12889 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12890 pipe_config);
12891 }
12892
12893 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12894 intel_fbc_enable(
12895 intel_crtc, pipe_config,
12896 to_intel_plane_state(crtc->primary->state));
12897 }
12898
12899 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12900
12901 if (needs_vblank_wait(pipe_config))
12902 *crtc_vblank_mask |= drm_crtc_mask(crtc);
12903 }
12904
12905 static void intel_update_crtcs(struct drm_atomic_state *state,
12906 unsigned int *crtc_vblank_mask)
12907 {
12908 struct drm_crtc *crtc;
12909 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12910 int i;
12911
12912 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12913 if (!new_crtc_state->active)
12914 continue;
12915
12916 intel_update_crtc(crtc, state, old_crtc_state,
12917 new_crtc_state, crtc_vblank_mask);
12918 }
12919 }
12920
12921 static void skl_update_crtcs(struct drm_atomic_state *state,
12922 unsigned int *crtc_vblank_mask)
12923 {
12924 struct drm_i915_private *dev_priv = to_i915(state->dev);
12925 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12926 struct drm_crtc *crtc;
12927 struct intel_crtc *intel_crtc;
12928 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12929 struct intel_crtc_state *cstate;
12930 unsigned int updated = 0;
12931 bool progress;
12932 enum pipe pipe;
12933 int i;
12934
12935 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12936
12937 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12938 /* ignore allocations for crtc's that have been turned off. */
12939 if (new_crtc_state->active)
12940 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12941
12942 /*
12943 * Whenever the number of active pipes changes, we need to make sure we
12944 * update the pipes in the right order so that their ddb allocations
12945 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12946 * cause pipe underruns and other bad stuff.
12947 */
12948 do {
12949 progress = false;
12950
12951 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12952 bool vbl_wait = false;
12953 unsigned int cmask = drm_crtc_mask(crtc);
12954
12955 intel_crtc = to_intel_crtc(crtc);
12956 cstate = to_intel_crtc_state(crtc->state);
12957 pipe = intel_crtc->pipe;
12958
12959 if (updated & cmask || !cstate->base.active)
12960 continue;
12961
12962 if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
12963 continue;
12964
12965 updated |= cmask;
12966 entries[i] = &cstate->wm.skl.ddb;
12967
12968 /*
12969 * If this is an already active pipe, it's DDB changed,
12970 * and this isn't the last pipe that needs updating
12971 * then we need to wait for a vblank to pass for the
12972 * new ddb allocation to take effect.
12973 */
12974 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12975 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12976 !new_crtc_state->active_changed &&
12977 intel_state->wm_results.dirty_pipes != updated)
12978 vbl_wait = true;
12979
12980 intel_update_crtc(crtc, state, old_crtc_state,
12981 new_crtc_state, crtc_vblank_mask);
12982
12983 if (vbl_wait)
12984 intel_wait_for_vblank(dev_priv, pipe);
12985
12986 progress = true;
12987 }
12988 } while (progress);
12989 }
12990
12991 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12992 {
12993 struct intel_atomic_state *state, *next;
12994 struct llist_node *freed;
12995
12996 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12997 llist_for_each_entry_safe(state, next, freed, freed)
12998 drm_atomic_state_put(&state->base);
12999 }
13000
13001 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
13002 {
13003 struct drm_i915_private *dev_priv =
13004 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
13005
13006 intel_atomic_helper_free_state(dev_priv);
13007 }
13008
13009 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
13010 {
13011 struct drm_device *dev = state->dev;
13012 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13013 struct drm_i915_private *dev_priv = to_i915(dev);
13014 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
13015 struct drm_crtc *crtc;
13016 struct intel_crtc_state *intel_cstate;
13017 bool hw_check = intel_state->modeset;
13018 u64 put_domains[I915_MAX_PIPES] = {};
13019 unsigned crtc_vblank_mask = 0;
13020 int i;
13021
13022 drm_atomic_helper_wait_for_dependencies(state);
13023
13024 if (intel_state->modeset)
13025 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13026
13027 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13029
13030 if (needs_modeset(new_crtc_state) ||
13031 to_intel_crtc_state(new_crtc_state)->update_pipe) {
13032 hw_check = true;
13033
13034 put_domains[to_intel_crtc(crtc)->pipe] =
13035 modeset_get_crtc_power_domains(crtc,
13036 to_intel_crtc_state(new_crtc_state));
13037 }
13038
13039 if (!needs_modeset(new_crtc_state))
13040 continue;
13041
13042 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
13043 to_intel_crtc_state(new_crtc_state));
13044
13045 if (old_crtc_state->active) {
13046 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13047 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
13048 intel_crtc->active = false;
13049 intel_fbc_disable(intel_crtc);
13050 intel_disable_shared_dpll(intel_crtc);
13051
13052 /*
13053 * Underruns don't always raise
13054 * interrupts, so check manually.
13055 */
13056 intel_check_cpu_fifo_underruns(dev_priv);
13057 intel_check_pch_fifo_underruns(dev_priv);
13058
13059 if (!crtc->state->active) {
13060 /*
13061 * Make sure we don't call initial_watermarks
13062 * for ILK-style watermark updates.
13063 *
13064 * No clue what this is supposed to achieve.
13065 */
13066 if (INTEL_GEN(dev_priv) >= 9)
13067 dev_priv->display.initial_watermarks(intel_state,
13068 to_intel_crtc_state(crtc->state));
13069 }
13070 }
13071 }
13072
13073 /* Only after disabling all output pipelines that will be changed can we
13074 * update the the output configuration. */
13075 intel_modeset_update_crtc_state(state);
13076
13077 if (intel_state->modeset) {
13078 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13079
13080 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
13081
13082 /*
13083 * SKL workaround: bspec recommends we disable the SAGV when we
13084 * have more then one pipe enabled
13085 */
13086 if (!intel_can_enable_sagv(state))
13087 intel_disable_sagv(dev_priv);
13088
13089 intel_modeset_verify_disabled(dev, state);
13090 }
13091
13092 /* Complete the events for pipes that have now been disabled */
13093 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
13094 bool modeset = needs_modeset(new_crtc_state);
13095
13096 /* Complete events for now disable pipes here. */
13097 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
13098 spin_lock_irq(&dev->event_lock);
13099 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
13100 spin_unlock_irq(&dev->event_lock);
13101
13102 new_crtc_state->event = NULL;
13103 }
13104 }
13105
13106 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13107 dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
13108
13109 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
13110 * already, but still need the state for the delayed optimization. To
13111 * fix this:
13112 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
13113 * - schedule that vblank worker _before_ calling hw_done
13114 * - at the start of commit_tail, cancel it _synchrously
13115 * - switch over to the vblank wait helper in the core after that since
13116 * we don't need out special handling any more.
13117 */
13118 if (!state->legacy_cursor_update)
13119 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13120
13121 /*
13122 * Now that the vblank has passed, we can go ahead and program the
13123 * optimal watermarks on platforms that need two-step watermark
13124 * programming.
13125 *
13126 * TODO: Move this (and other cleanup) to an async worker eventually.
13127 */
13128 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
13129 intel_cstate = to_intel_crtc_state(new_crtc_state);
13130
13131 if (dev_priv->display.optimize_watermarks)
13132 dev_priv->display.optimize_watermarks(intel_state,
13133 intel_cstate);
13134 }
13135
13136 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13137 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13138
13139 if (put_domains[i])
13140 modeset_put_power_domains(dev_priv, put_domains[i]);
13141
13142 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
13143 }
13144
13145 if (intel_state->modeset && intel_can_enable_sagv(state))
13146 intel_enable_sagv(dev_priv);
13147
13148 drm_atomic_helper_commit_hw_done(state);
13149
13150 if (intel_state->modeset) {
13151 /* As one of the primary mmio accessors, KMS has a high
13152 * likelihood of triggering bugs in unclaimed access. After we
13153 * finish modesetting, see if an error has been flagged, and if
13154 * so enable debugging for the next modeset - and hope we catch
13155 * the culprit.
13156 */
13157 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13158 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13159 }
13160
13161 mutex_lock(&dev->struct_mutex);
13162 drm_atomic_helper_cleanup_planes(dev, state);
13163 mutex_unlock(&dev->struct_mutex);
13164
13165 drm_atomic_helper_commit_cleanup_done(state);
13166
13167 drm_atomic_state_put(state);
13168
13169 intel_atomic_helper_free_state(dev_priv);
13170 }
13171
13172 static void intel_atomic_commit_work(struct work_struct *work)
13173 {
13174 struct drm_atomic_state *state =
13175 container_of(work, struct drm_atomic_state, commit_work);
13176
13177 intel_atomic_commit_tail(state);
13178 }
13179
13180 static int __i915_sw_fence_call
13181 intel_atomic_commit_ready(struct i915_sw_fence *fence,
13182 enum i915_sw_fence_notify notify)
13183 {
13184 struct intel_atomic_state *state =
13185 container_of(fence, struct intel_atomic_state, commit_ready);
13186
13187 switch (notify) {
13188 case FENCE_COMPLETE:
13189 if (state->base.commit_work.func)
13190 queue_work(system_unbound_wq, &state->base.commit_work);
13191 break;
13192
13193 case FENCE_FREE:
13194 {
13195 struct intel_atomic_helper *helper =
13196 &to_i915(state->base.dev)->atomic_helper;
13197
13198 if (llist_add(&state->freed, &helper->free_list))
13199 schedule_work(&helper->free_work);
13200 break;
13201 }
13202 }
13203
13204 return NOTIFY_DONE;
13205 }
13206
13207 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
13208 {
13209 struct drm_plane_state *old_plane_state, *new_plane_state;
13210 struct drm_plane *plane;
13211 int i;
13212
13213 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
13214 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
13215 intel_fb_obj(new_plane_state->fb),
13216 to_intel_plane(plane)->frontbuffer_bit);
13217 }
13218
13219 /**
13220 * intel_atomic_commit - commit validated state object
13221 * @dev: DRM device
13222 * @state: the top-level driver state object
13223 * @nonblock: nonblocking commit
13224 *
13225 * This function commits a top-level state object that has been validated
13226 * with drm_atomic_helper_check().
13227 *
13228 * RETURNS
13229 * Zero for success or -errno.
13230 */
13231 static int intel_atomic_commit(struct drm_device *dev,
13232 struct drm_atomic_state *state,
13233 bool nonblock)
13234 {
13235 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13236 struct drm_i915_private *dev_priv = to_i915(dev);
13237 int ret = 0;
13238
13239 ret = drm_atomic_helper_setup_commit(state, nonblock);
13240 if (ret)
13241 return ret;
13242
13243 drm_atomic_state_get(state);
13244 i915_sw_fence_init(&intel_state->commit_ready,
13245 intel_atomic_commit_ready);
13246
13247 ret = intel_atomic_prepare_commit(dev, state);
13248 if (ret) {
13249 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13250 i915_sw_fence_commit(&intel_state->commit_ready);
13251 return ret;
13252 }
13253
13254 /*
13255 * The intel_legacy_cursor_update() fast path takes care
13256 * of avoiding the vblank waits for simple cursor
13257 * movement and flips. For cursor on/off and size changes,
13258 * we want to perform the vblank waits so that watermark
13259 * updates happen during the correct frames. Gen9+ have
13260 * double buffered watermarks and so shouldn't need this.
13261 *
13262 * Do this after drm_atomic_helper_setup_commit() and
13263 * intel_atomic_prepare_commit() because we still want
13264 * to skip the flip and fb cleanup waits. Although that
13265 * does risk yanking the mapping from under the display
13266 * engine.
13267 *
13268 * FIXME doing watermarks and fb cleanup from a vblank worker
13269 * (assuming we had any) would solve these problems.
13270 */
13271 if (INTEL_GEN(dev_priv) < 9)
13272 state->legacy_cursor_update = false;
13273
13274 drm_atomic_helper_swap_state(state, true);
13275 dev_priv->wm.distrust_bios_wm = false;
13276 intel_shared_dpll_swap_state(state);
13277 intel_atomic_track_fbs(state);
13278
13279 if (intel_state->modeset) {
13280 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13281 sizeof(intel_state->min_pixclk));
13282 dev_priv->active_crtcs = intel_state->active_crtcs;
13283 dev_priv->cdclk.logical = intel_state->cdclk.logical;
13284 dev_priv->cdclk.actual = intel_state->cdclk.actual;
13285 }
13286
13287 drm_atomic_state_get(state);
13288 INIT_WORK(&state->commit_work,
13289 nonblock ? intel_atomic_commit_work : NULL);
13290
13291 i915_sw_fence_commit(&intel_state->commit_ready);
13292 if (!nonblock) {
13293 i915_sw_fence_wait(&intel_state->commit_ready);
13294 intel_atomic_commit_tail(state);
13295 }
13296
13297 return 0;
13298 }
13299
13300 static const struct drm_crtc_funcs intel_crtc_funcs = {
13301 .gamma_set = drm_atomic_helper_legacy_gamma_set,
13302 .set_config = drm_atomic_helper_set_config,
13303 .set_property = drm_atomic_helper_crtc_set_property,
13304 .destroy = intel_crtc_destroy,
13305 .page_flip = drm_atomic_helper_page_flip,
13306 .atomic_duplicate_state = intel_crtc_duplicate_state,
13307 .atomic_destroy_state = intel_crtc_destroy_state,
13308 .set_crc_source = intel_crtc_set_crc_source,
13309 };
13310
13311 /**
13312 * intel_prepare_plane_fb - Prepare fb for usage on plane
13313 * @plane: drm plane to prepare for
13314 * @fb: framebuffer to prepare for presentation
13315 *
13316 * Prepares a framebuffer for usage on a display plane. Generally this
13317 * involves pinning the underlying object and updating the frontbuffer tracking
13318 * bits. Some older platforms need special physical address handling for
13319 * cursor planes.
13320 *
13321 * Must be called with struct_mutex held.
13322 *
13323 * Returns 0 on success, negative error code on failure.
13324 */
13325 int
13326 intel_prepare_plane_fb(struct drm_plane *plane,
13327 struct drm_plane_state *new_state)
13328 {
13329 struct intel_atomic_state *intel_state =
13330 to_intel_atomic_state(new_state->state);
13331 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13332 struct drm_framebuffer *fb = new_state->fb;
13333 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13334 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13335 int ret;
13336
13337 if (obj) {
13338 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13339 INTEL_INFO(dev_priv)->cursor_needs_physical) {
13340 const int align = intel_cursor_alignment(dev_priv);
13341
13342 ret = i915_gem_object_attach_phys(obj, align);
13343 if (ret) {
13344 DRM_DEBUG_KMS("failed to attach phys object\n");
13345 return ret;
13346 }
13347 } else {
13348 struct i915_vma *vma;
13349
13350 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13351 if (IS_ERR(vma)) {
13352 DRM_DEBUG_KMS("failed to pin object\n");
13353 return PTR_ERR(vma);
13354 }
13355
13356 to_intel_plane_state(new_state)->vma = vma;
13357 }
13358 }
13359
13360 if (!obj && !old_obj)
13361 return 0;
13362
13363 if (old_obj) {
13364 struct drm_crtc_state *crtc_state =
13365 drm_atomic_get_existing_crtc_state(new_state->state,
13366 plane->state->crtc);
13367
13368 /* Big Hammer, we also need to ensure that any pending
13369 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13370 * current scanout is retired before unpinning the old
13371 * framebuffer. Note that we rely on userspace rendering
13372 * into the buffer attached to the pipe they are waiting
13373 * on. If not, userspace generates a GPU hang with IPEHR
13374 * point to the MI_WAIT_FOR_EVENT.
13375 *
13376 * This should only fail upon a hung GPU, in which case we
13377 * can safely continue.
13378 */
13379 if (needs_modeset(crtc_state)) {
13380 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13381 old_obj->resv, NULL,
13382 false, 0,
13383 GFP_KERNEL);
13384 if (ret < 0)
13385 return ret;
13386 }
13387 }
13388
13389 if (new_state->fence) { /* explicit fencing */
13390 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
13391 new_state->fence,
13392 I915_FENCE_TIMEOUT,
13393 GFP_KERNEL);
13394 if (ret < 0)
13395 return ret;
13396 }
13397
13398 if (!obj)
13399 return 0;
13400
13401 if (!new_state->fence) { /* implicit fencing */
13402 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13403 obj->resv, NULL,
13404 false, I915_FENCE_TIMEOUT,
13405 GFP_KERNEL);
13406 if (ret < 0)
13407 return ret;
13408
13409 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
13410 }
13411
13412 return 0;
13413 }
13414
13415 /**
13416 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13417 * @plane: drm plane to clean up for
13418 * @fb: old framebuffer that was on plane
13419 *
13420 * Cleans up a framebuffer that has just been removed from a plane.
13421 *
13422 * Must be called with struct_mutex held.
13423 */
13424 void
13425 intel_cleanup_plane_fb(struct drm_plane *plane,
13426 struct drm_plane_state *old_state)
13427 {
13428 struct i915_vma *vma;
13429
13430 /* Should only be called after a successful intel_prepare_plane_fb()! */
13431 vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
13432 if (vma)
13433 intel_unpin_fb_vma(vma);
13434 }
13435
13436 int
13437 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13438 {
13439 struct drm_i915_private *dev_priv;
13440 int max_scale;
13441 int crtc_clock, max_dotclk;
13442
13443 if (!intel_crtc || !crtc_state->base.enable)
13444 return DRM_PLANE_HELPER_NO_SCALING;
13445
13446 dev_priv = to_i915(intel_crtc->base.dev);
13447
13448 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13449 max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
13450
13451 if (IS_GEMINILAKE(dev_priv))
13452 max_dotclk *= 2;
13453
13454 if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
13455 return DRM_PLANE_HELPER_NO_SCALING;
13456
13457 /*
13458 * skl max scale is lower of:
13459 * close to 3 but not 3, -1 is for that purpose
13460 * or
13461 * cdclk/crtc_clock
13462 */
13463 max_scale = min((1 << 16) * 3 - 1,
13464 (1 << 8) * ((max_dotclk << 8) / crtc_clock));
13465
13466 return max_scale;
13467 }
13468
13469 static int
13470 intel_check_primary_plane(struct intel_plane *plane,
13471 struct intel_crtc_state *crtc_state,
13472 struct intel_plane_state *state)
13473 {
13474 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
13475 struct drm_crtc *crtc = state->base.crtc;
13476 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13477 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13478 bool can_position = false;
13479 int ret;
13480
13481 if (INTEL_GEN(dev_priv) >= 9) {
13482 /* use scaler when colorkey is not required */
13483 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13484 min_scale = 1;
13485 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13486 }
13487 can_position = true;
13488 }
13489
13490 ret = drm_plane_helper_check_state(&state->base,
13491 &state->clip,
13492 min_scale, max_scale,
13493 can_position, true);
13494 if (ret)
13495 return ret;
13496
13497 if (!state->base.fb)
13498 return 0;
13499
13500 if (INTEL_GEN(dev_priv) >= 9) {
13501 ret = skl_check_plane_surface(state);
13502 if (ret)
13503 return ret;
13504
13505 state->ctl = skl_plane_ctl(crtc_state, state);
13506 } else {
13507 ret = i9xx_check_plane_surface(state);
13508 if (ret)
13509 return ret;
13510
13511 state->ctl = i9xx_plane_ctl(crtc_state, state);
13512 }
13513
13514 return 0;
13515 }
13516
13517 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13518 struct drm_crtc_state *old_crtc_state)
13519 {
13520 struct drm_device *dev = crtc->dev;
13521 struct drm_i915_private *dev_priv = to_i915(dev);
13522 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13523 struct intel_crtc_state *intel_cstate =
13524 to_intel_crtc_state(crtc->state);
13525 struct intel_crtc_state *old_intel_cstate =
13526 to_intel_crtc_state(old_crtc_state);
13527 struct intel_atomic_state *old_intel_state =
13528 to_intel_atomic_state(old_crtc_state->state);
13529 bool modeset = needs_modeset(crtc->state);
13530
13531 if (!modeset &&
13532 (intel_cstate->base.color_mgmt_changed ||
13533 intel_cstate->update_pipe)) {
13534 intel_color_set_csc(crtc->state);
13535 intel_color_load_luts(crtc->state);
13536 }
13537
13538 /* Perform vblank evasion around commit operation */
13539 intel_pipe_update_start(intel_crtc);
13540
13541 if (modeset)
13542 goto out;
13543
13544 if (intel_cstate->update_pipe)
13545 intel_update_pipe_config(intel_crtc, old_intel_cstate);
13546 else if (INTEL_GEN(dev_priv) >= 9)
13547 skl_detach_scalers(intel_crtc);
13548
13549 out:
13550 if (dev_priv->display.atomic_update_watermarks)
13551 dev_priv->display.atomic_update_watermarks(old_intel_state,
13552 intel_cstate);
13553 }
13554
13555 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13556 struct drm_crtc_state *old_crtc_state)
13557 {
13558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13559
13560 intel_pipe_update_end(intel_crtc, NULL);
13561 }
13562
13563 /**
13564 * intel_plane_destroy - destroy a plane
13565 * @plane: plane to destroy
13566 *
13567 * Common destruction function for all types of planes (primary, cursor,
13568 * sprite).
13569 */
13570 void intel_plane_destroy(struct drm_plane *plane)
13571 {
13572 drm_plane_cleanup(plane);
13573 kfree(to_intel_plane(plane));
13574 }
13575
13576 const struct drm_plane_funcs intel_plane_funcs = {
13577 .update_plane = drm_atomic_helper_update_plane,
13578 .disable_plane = drm_atomic_helper_disable_plane,
13579 .destroy = intel_plane_destroy,
13580 .set_property = drm_atomic_helper_plane_set_property,
13581 .atomic_get_property = intel_plane_atomic_get_property,
13582 .atomic_set_property = intel_plane_atomic_set_property,
13583 .atomic_duplicate_state = intel_plane_duplicate_state,
13584 .atomic_destroy_state = intel_plane_destroy_state,
13585 };
13586
13587 static int
13588 intel_legacy_cursor_update(struct drm_plane *plane,
13589 struct drm_crtc *crtc,
13590 struct drm_framebuffer *fb,
13591 int crtc_x, int crtc_y,
13592 unsigned int crtc_w, unsigned int crtc_h,
13593 uint32_t src_x, uint32_t src_y,
13594 uint32_t src_w, uint32_t src_h,
13595 struct drm_modeset_acquire_ctx *ctx)
13596 {
13597 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13598 int ret;
13599 struct drm_plane_state *old_plane_state, *new_plane_state;
13600 struct intel_plane *intel_plane = to_intel_plane(plane);
13601 struct drm_framebuffer *old_fb;
13602 struct drm_crtc_state *crtc_state = crtc->state;
13603 struct i915_vma *old_vma;
13604
13605 /*
13606 * When crtc is inactive or there is a modeset pending,
13607 * wait for it to complete in the slowpath
13608 */
13609 if (!crtc_state->active || needs_modeset(crtc_state) ||
13610 to_intel_crtc_state(crtc_state)->update_pipe)
13611 goto slow;
13612
13613 old_plane_state = plane->state;
13614
13615 /*
13616 * If any parameters change that may affect watermarks,
13617 * take the slowpath. Only changing fb or position should be
13618 * in the fastpath.
13619 */
13620 if (old_plane_state->crtc != crtc ||
13621 old_plane_state->src_w != src_w ||
13622 old_plane_state->src_h != src_h ||
13623 old_plane_state->crtc_w != crtc_w ||
13624 old_plane_state->crtc_h != crtc_h ||
13625 !old_plane_state->fb != !fb)
13626 goto slow;
13627
13628 new_plane_state = intel_plane_duplicate_state(plane);
13629 if (!new_plane_state)
13630 return -ENOMEM;
13631
13632 drm_atomic_set_fb_for_plane(new_plane_state, fb);
13633
13634 new_plane_state->src_x = src_x;
13635 new_plane_state->src_y = src_y;
13636 new_plane_state->src_w = src_w;
13637 new_plane_state->src_h = src_h;
13638 new_plane_state->crtc_x = crtc_x;
13639 new_plane_state->crtc_y = crtc_y;
13640 new_plane_state->crtc_w = crtc_w;
13641 new_plane_state->crtc_h = crtc_h;
13642
13643 ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13644 to_intel_plane_state(new_plane_state));
13645 if (ret)
13646 goto out_free;
13647
13648 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13649 if (ret)
13650 goto out_free;
13651
13652 if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13653 int align = intel_cursor_alignment(dev_priv);
13654
13655 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13656 if (ret) {
13657 DRM_DEBUG_KMS("failed to attach phys object\n");
13658 goto out_unlock;
13659 }
13660 } else {
13661 struct i915_vma *vma;
13662
13663 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13664 if (IS_ERR(vma)) {
13665 DRM_DEBUG_KMS("failed to pin object\n");
13666
13667 ret = PTR_ERR(vma);
13668 goto out_unlock;
13669 }
13670
13671 to_intel_plane_state(new_plane_state)->vma = vma;
13672 }
13673
13674 old_fb = old_plane_state->fb;
13675 old_vma = to_intel_plane_state(old_plane_state)->vma;
13676
13677 i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13678 intel_plane->frontbuffer_bit);
13679
13680 /* Swap plane state */
13681 new_plane_state->fence = old_plane_state->fence;
13682 *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state);
13683 new_plane_state->fence = NULL;
13684 new_plane_state->fb = old_fb;
13685 to_intel_plane_state(new_plane_state)->vma = old_vma;
13686
13687 if (plane->state->visible) {
13688 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13689 intel_plane->update_plane(intel_plane,
13690 to_intel_crtc_state(crtc->state),
13691 to_intel_plane_state(plane->state));
13692 } else {
13693 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13694 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
13695 }
13696
13697 intel_cleanup_plane_fb(plane, new_plane_state);
13698
13699 out_unlock:
13700 mutex_unlock(&dev_priv->drm.struct_mutex);
13701 out_free:
13702 intel_plane_destroy_state(plane, new_plane_state);
13703 return ret;
13704
13705 slow:
13706 return drm_atomic_helper_update_plane(plane, crtc, fb,
13707 crtc_x, crtc_y, crtc_w, crtc_h,
13708 src_x, src_y, src_w, src_h, ctx);
13709 }
13710
13711 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13712 .update_plane = intel_legacy_cursor_update,
13713 .disable_plane = drm_atomic_helper_disable_plane,
13714 .destroy = intel_plane_destroy,
13715 .set_property = drm_atomic_helper_plane_set_property,
13716 .atomic_get_property = intel_plane_atomic_get_property,
13717 .atomic_set_property = intel_plane_atomic_set_property,
13718 .atomic_duplicate_state = intel_plane_duplicate_state,
13719 .atomic_destroy_state = intel_plane_destroy_state,
13720 };
13721
13722 static struct intel_plane *
13723 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13724 {
13725 struct intel_plane *primary = NULL;
13726 struct intel_plane_state *state = NULL;
13727 const uint32_t *intel_primary_formats;
13728 unsigned int supported_rotations;
13729 unsigned int num_formats;
13730 int ret;
13731
13732 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13733 if (!primary) {
13734 ret = -ENOMEM;
13735 goto fail;
13736 }
13737
13738 state = intel_create_plane_state(&primary->base);
13739 if (!state) {
13740 ret = -ENOMEM;
13741 goto fail;
13742 }
13743
13744 primary->base.state = &state->base;
13745
13746 primary->can_scale = false;
13747 primary->max_downscale = 1;
13748 if (INTEL_GEN(dev_priv) >= 9) {
13749 primary->can_scale = true;
13750 state->scaler_id = -1;
13751 }
13752 primary->pipe = pipe;
13753 /*
13754 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13755 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13756 */
13757 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13758 primary->plane = (enum plane) !pipe;
13759 else
13760 primary->plane = (enum plane) pipe;
13761 primary->id = PLANE_PRIMARY;
13762 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13763 primary->check_plane = intel_check_primary_plane;
13764
13765 if (INTEL_GEN(dev_priv) >= 9) {
13766 intel_primary_formats = skl_primary_formats;
13767 num_formats = ARRAY_SIZE(skl_primary_formats);
13768
13769 primary->update_plane = skylake_update_primary_plane;
13770 primary->disable_plane = skylake_disable_primary_plane;
13771 } else if (INTEL_GEN(dev_priv) >= 4) {
13772 intel_primary_formats = i965_primary_formats;
13773 num_formats = ARRAY_SIZE(i965_primary_formats);
13774
13775 primary->update_plane = i9xx_update_primary_plane;
13776 primary->disable_plane = i9xx_disable_primary_plane;
13777 } else {
13778 intel_primary_formats = i8xx_primary_formats;
13779 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13780
13781 primary->update_plane = i9xx_update_primary_plane;
13782 primary->disable_plane = i9xx_disable_primary_plane;
13783 }
13784
13785 if (INTEL_GEN(dev_priv) >= 9)
13786 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13787 0, &intel_plane_funcs,
13788 intel_primary_formats, num_formats,
13789 DRM_PLANE_TYPE_PRIMARY,
13790 "plane 1%c", pipe_name(pipe));
13791 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13792 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13793 0, &intel_plane_funcs,
13794 intel_primary_formats, num_formats,
13795 DRM_PLANE_TYPE_PRIMARY,
13796 "primary %c", pipe_name(pipe));
13797 else
13798 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13799 0, &intel_plane_funcs,
13800 intel_primary_formats, num_formats,
13801 DRM_PLANE_TYPE_PRIMARY,
13802 "plane %c", plane_name(primary->plane));
13803 if (ret)
13804 goto fail;
13805
13806 if (INTEL_GEN(dev_priv) >= 9) {
13807 supported_rotations =
13808 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13809 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
13810 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13811 supported_rotations =
13812 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
13813 DRM_MODE_REFLECT_X;
13814 } else if (INTEL_GEN(dev_priv) >= 4) {
13815 supported_rotations =
13816 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
13817 } else {
13818 supported_rotations = DRM_MODE_ROTATE_0;
13819 }
13820
13821 if (INTEL_GEN(dev_priv) >= 4)
13822 drm_plane_create_rotation_property(&primary->base,
13823 DRM_MODE_ROTATE_0,
13824 supported_rotations);
13825
13826 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13827
13828 return primary;
13829
13830 fail:
13831 kfree(state);
13832 kfree(primary);
13833
13834 return ERR_PTR(ret);
13835 }
13836
13837 static struct intel_plane *
13838 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13839 enum pipe pipe)
13840 {
13841 struct intel_plane *cursor = NULL;
13842 struct intel_plane_state *state = NULL;
13843 int ret;
13844
13845 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13846 if (!cursor) {
13847 ret = -ENOMEM;
13848 goto fail;
13849 }
13850
13851 state = intel_create_plane_state(&cursor->base);
13852 if (!state) {
13853 ret = -ENOMEM;
13854 goto fail;
13855 }
13856
13857 cursor->base.state = &state->base;
13858
13859 cursor->can_scale = false;
13860 cursor->max_downscale = 1;
13861 cursor->pipe = pipe;
13862 cursor->plane = pipe;
13863 cursor->id = PLANE_CURSOR;
13864 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13865
13866 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
13867 cursor->update_plane = i845_update_cursor;
13868 cursor->disable_plane = i845_disable_cursor;
13869 cursor->check_plane = i845_check_cursor;
13870 } else {
13871 cursor->update_plane = i9xx_update_cursor;
13872 cursor->disable_plane = i9xx_disable_cursor;
13873 cursor->check_plane = i9xx_check_cursor;
13874 }
13875
13876 cursor->cursor.base = ~0;
13877 cursor->cursor.cntl = ~0;
13878
13879 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
13880 cursor->cursor.size = ~0;
13881
13882 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13883 0, &intel_cursor_plane_funcs,
13884 intel_cursor_formats,
13885 ARRAY_SIZE(intel_cursor_formats),
13886 DRM_PLANE_TYPE_CURSOR,
13887 "cursor %c", pipe_name(pipe));
13888 if (ret)
13889 goto fail;
13890
13891 if (INTEL_GEN(dev_priv) >= 4)
13892 drm_plane_create_rotation_property(&cursor->base,
13893 DRM_MODE_ROTATE_0,
13894 DRM_MODE_ROTATE_0 |
13895 DRM_MODE_ROTATE_180);
13896
13897 if (INTEL_GEN(dev_priv) >= 9)
13898 state->scaler_id = -1;
13899
13900 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13901
13902 return cursor;
13903
13904 fail:
13905 kfree(state);
13906 kfree(cursor);
13907
13908 return ERR_PTR(ret);
13909 }
13910
13911 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13912 struct intel_crtc_state *crtc_state)
13913 {
13914 struct intel_crtc_scaler_state *scaler_state =
13915 &crtc_state->scaler_state;
13916 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13917 int i;
13918
13919 crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13920 if (!crtc->num_scalers)
13921 return;
13922
13923 for (i = 0; i < crtc->num_scalers; i++) {
13924 struct intel_scaler *scaler = &scaler_state->scalers[i];
13925
13926 scaler->in_use = 0;
13927 scaler->mode = PS_SCALER_MODE_DYN;
13928 }
13929
13930 scaler_state->scaler_id = -1;
13931 }
13932
13933 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13934 {
13935 struct intel_crtc *intel_crtc;
13936 struct intel_crtc_state *crtc_state = NULL;
13937 struct intel_plane *primary = NULL;
13938 struct intel_plane *cursor = NULL;
13939 int sprite, ret;
13940
13941 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13942 if (!intel_crtc)
13943 return -ENOMEM;
13944
13945 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13946 if (!crtc_state) {
13947 ret = -ENOMEM;
13948 goto fail;
13949 }
13950 intel_crtc->config = crtc_state;
13951 intel_crtc->base.state = &crtc_state->base;
13952 crtc_state->base.crtc = &intel_crtc->base;
13953
13954 primary = intel_primary_plane_create(dev_priv, pipe);
13955 if (IS_ERR(primary)) {
13956 ret = PTR_ERR(primary);
13957 goto fail;
13958 }
13959 intel_crtc->plane_ids_mask |= BIT(primary->id);
13960
13961 for_each_sprite(dev_priv, pipe, sprite) {
13962 struct intel_plane *plane;
13963
13964 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13965 if (IS_ERR(plane)) {
13966 ret = PTR_ERR(plane);
13967 goto fail;
13968 }
13969 intel_crtc->plane_ids_mask |= BIT(plane->id);
13970 }
13971
13972 cursor = intel_cursor_plane_create(dev_priv, pipe);
13973 if (IS_ERR(cursor)) {
13974 ret = PTR_ERR(cursor);
13975 goto fail;
13976 }
13977 intel_crtc->plane_ids_mask |= BIT(cursor->id);
13978
13979 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13980 &primary->base, &cursor->base,
13981 &intel_crtc_funcs,
13982 "pipe %c", pipe_name(pipe));
13983 if (ret)
13984 goto fail;
13985
13986 intel_crtc->pipe = pipe;
13987 intel_crtc->plane = primary->plane;
13988
13989 /* initialize shared scalers */
13990 intel_crtc_init_scalers(intel_crtc, crtc_state);
13991
13992 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13993 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13994 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13995 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13996
13997 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13998
13999 intel_color_init(&intel_crtc->base);
14000
14001 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14002
14003 return 0;
14004
14005 fail:
14006 /*
14007 * drm_mode_config_cleanup() will free up any
14008 * crtcs/planes already initialized.
14009 */
14010 kfree(crtc_state);
14011 kfree(intel_crtc);
14012
14013 return ret;
14014 }
14015
14016 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14017 {
14018 struct drm_device *dev = connector->base.dev;
14019
14020 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14021
14022 if (!connector->base.state->crtc)
14023 return INVALID_PIPE;
14024
14025 return to_intel_crtc(connector->base.state->crtc)->pipe;
14026 }
14027
14028 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14029 struct drm_file *file)
14030 {
14031 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14032 struct drm_crtc *drmmode_crtc;
14033 struct intel_crtc *crtc;
14034
14035 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14036 if (!drmmode_crtc)
14037 return -ENOENT;
14038
14039 crtc = to_intel_crtc(drmmode_crtc);
14040 pipe_from_crtc_id->pipe = crtc->pipe;
14041
14042 return 0;
14043 }
14044
14045 static int intel_encoder_clones(struct intel_encoder *encoder)
14046 {
14047 struct drm_device *dev = encoder->base.dev;
14048 struct intel_encoder *source_encoder;
14049 int index_mask = 0;
14050 int entry = 0;
14051
14052 for_each_intel_encoder(dev, source_encoder) {
14053 if (encoders_cloneable(encoder, source_encoder))
14054 index_mask |= (1 << entry);
14055
14056 entry++;
14057 }
14058
14059 return index_mask;
14060 }
14061
14062 static bool has_edp_a(struct drm_i915_private *dev_priv)
14063 {
14064 if (!IS_MOBILE(dev_priv))
14065 return false;
14066
14067 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14068 return false;
14069
14070 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14071 return false;
14072
14073 return true;
14074 }
14075
14076 static bool intel_crt_present(struct drm_i915_private *dev_priv)
14077 {
14078 if (INTEL_GEN(dev_priv) >= 9)
14079 return false;
14080
14081 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
14082 return false;
14083
14084 if (IS_CHERRYVIEW(dev_priv))
14085 return false;
14086
14087 if (HAS_PCH_LPT_H(dev_priv) &&
14088 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14089 return false;
14090
14091 /* DDI E can't be used if DDI A requires 4 lanes */
14092 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14093 return false;
14094
14095 if (!dev_priv->vbt.int_crt_support)
14096 return false;
14097
14098 return true;
14099 }
14100
14101 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
14102 {
14103 int pps_num;
14104 int pps_idx;
14105
14106 if (HAS_DDI(dev_priv))
14107 return;
14108 /*
14109 * This w/a is needed at least on CPT/PPT, but to be sure apply it
14110 * everywhere where registers can be write protected.
14111 */
14112 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14113 pps_num = 2;
14114 else
14115 pps_num = 1;
14116
14117 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
14118 u32 val = I915_READ(PP_CONTROL(pps_idx));
14119
14120 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
14121 I915_WRITE(PP_CONTROL(pps_idx), val);
14122 }
14123 }
14124
14125 static void intel_pps_init(struct drm_i915_private *dev_priv)
14126 {
14127 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
14128 dev_priv->pps_mmio_base = PCH_PPS_BASE;
14129 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14130 dev_priv->pps_mmio_base = VLV_PPS_BASE;
14131 else
14132 dev_priv->pps_mmio_base = PPS_BASE;
14133
14134 intel_pps_unlock_regs_wa(dev_priv);
14135 }
14136
14137 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14138 {
14139 struct intel_encoder *encoder;
14140 bool dpd_is_edp = false;
14141
14142 intel_pps_init(dev_priv);
14143
14144 /*
14145 * intel_edp_init_connector() depends on this completing first, to
14146 * prevent the registeration of both eDP and LVDS and the incorrect
14147 * sharing of the PPS.
14148 */
14149 intel_lvds_init(dev_priv);
14150
14151 if (intel_crt_present(dev_priv))
14152 intel_crt_init(dev_priv);
14153
14154 if (IS_GEN9_LP(dev_priv)) {
14155 /*
14156 * FIXME: Broxton doesn't support port detection via the
14157 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14158 * detect the ports.
14159 */
14160 intel_ddi_init(dev_priv, PORT_A);
14161 intel_ddi_init(dev_priv, PORT_B);
14162 intel_ddi_init(dev_priv, PORT_C);
14163
14164 intel_dsi_init(dev_priv);
14165 } else if (HAS_DDI(dev_priv)) {
14166 int found;
14167
14168 /*
14169 * Haswell uses DDI functions to detect digital outputs.
14170 * On SKL pre-D0 the strap isn't connected, so we assume
14171 * it's there.
14172 */
14173 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14174 /* WaIgnoreDDIAStrap: skl */
14175 if (found || IS_GEN9_BC(dev_priv))
14176 intel_ddi_init(dev_priv, PORT_A);
14177
14178 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14179 * register */
14180 found = I915_READ(SFUSE_STRAP);
14181
14182 if (found & SFUSE_STRAP_DDIB_DETECTED)
14183 intel_ddi_init(dev_priv, PORT_B);
14184 if (found & SFUSE_STRAP_DDIC_DETECTED)
14185 intel_ddi_init(dev_priv, PORT_C);
14186 if (found & SFUSE_STRAP_DDID_DETECTED)
14187 intel_ddi_init(dev_priv, PORT_D);
14188 /*
14189 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14190 */
14191 if (IS_GEN9_BC(dev_priv) &&
14192 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14193 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14194 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14195 intel_ddi_init(dev_priv, PORT_E);
14196
14197 } else if (HAS_PCH_SPLIT(dev_priv)) {
14198 int found;
14199 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
14200
14201 if (has_edp_a(dev_priv))
14202 intel_dp_init(dev_priv, DP_A, PORT_A);
14203
14204 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14205 /* PCH SDVOB multiplex with HDMIB */
14206 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
14207 if (!found)
14208 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
14209 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14210 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
14211 }
14212
14213 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14214 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
14215
14216 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14217 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
14218
14219 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14220 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
14221
14222 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14223 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
14224 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14225 bool has_edp, has_port;
14226
14227 /*
14228 * The DP_DETECTED bit is the latched state of the DDC
14229 * SDA pin at boot. However since eDP doesn't require DDC
14230 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14231 * eDP ports may have been muxed to an alternate function.
14232 * Thus we can't rely on the DP_DETECTED bit alone to detect
14233 * eDP ports. Consult the VBT as well as DP_DETECTED to
14234 * detect eDP ports.
14235 *
14236 * Sadly the straps seem to be missing sometimes even for HDMI
14237 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14238 * and VBT for the presence of the port. Additionally we can't
14239 * trust the port type the VBT declares as we've seen at least
14240 * HDMI ports that the VBT claim are DP or eDP.
14241 */
14242 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
14243 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14244 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14245 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
14246 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14247 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
14248
14249 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
14250 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14251 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14252 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
14253 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14254 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
14255
14256 if (IS_CHERRYVIEW(dev_priv)) {
14257 /*
14258 * eDP not supported on port D,
14259 * so no need to worry about it
14260 */
14261 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14262 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14263 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
14264 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14265 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
14266 }
14267
14268 intel_dsi_init(dev_priv);
14269 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
14270 bool found = false;
14271
14272 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14273 DRM_DEBUG_KMS("probing SDVOB\n");
14274 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
14275 if (!found && IS_G4X(dev_priv)) {
14276 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14277 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
14278 }
14279
14280 if (!found && IS_G4X(dev_priv))
14281 intel_dp_init(dev_priv, DP_B, PORT_B);
14282 }
14283
14284 /* Before G4X SDVOC doesn't have its own detect register */
14285
14286 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14287 DRM_DEBUG_KMS("probing SDVOC\n");
14288 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
14289 }
14290
14291 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14292
14293 if (IS_G4X(dev_priv)) {
14294 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14295 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
14296 }
14297 if (IS_G4X(dev_priv))
14298 intel_dp_init(dev_priv, DP_C, PORT_C);
14299 }
14300
14301 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
14302 intel_dp_init(dev_priv, DP_D, PORT_D);
14303 } else if (IS_GEN2(dev_priv))
14304 intel_dvo_init(dev_priv);
14305
14306 if (SUPPORTS_TV(dev_priv))
14307 intel_tv_init(dev_priv);
14308
14309 intel_psr_init(dev_priv);
14310
14311 for_each_intel_encoder(&dev_priv->drm, encoder) {
14312 encoder->base.possible_crtcs = encoder->crtc_mask;
14313 encoder->base.possible_clones =
14314 intel_encoder_clones(encoder);
14315 }
14316
14317 intel_init_pch_refclk(dev_priv);
14318
14319 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
14320 }
14321
14322 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14323 {
14324 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14325
14326 drm_framebuffer_cleanup(fb);
14327
14328 i915_gem_object_lock(intel_fb->obj);
14329 WARN_ON(!intel_fb->obj->framebuffer_references--);
14330 i915_gem_object_unlock(intel_fb->obj);
14331
14332 i915_gem_object_put(intel_fb->obj);
14333
14334 kfree(intel_fb);
14335 }
14336
14337 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14338 struct drm_file *file,
14339 unsigned int *handle)
14340 {
14341 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14342 struct drm_i915_gem_object *obj = intel_fb->obj;
14343
14344 if (obj->userptr.mm) {
14345 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14346 return -EINVAL;
14347 }
14348
14349 return drm_gem_handle_create(file, &obj->base, handle);
14350 }
14351
14352 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14353 struct drm_file *file,
14354 unsigned flags, unsigned color,
14355 struct drm_clip_rect *clips,
14356 unsigned num_clips)
14357 {
14358 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14359
14360 i915_gem_object_flush_if_display(obj);
14361 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
14362
14363 return 0;
14364 }
14365
14366 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14367 .destroy = intel_user_framebuffer_destroy,
14368 .create_handle = intel_user_framebuffer_create_handle,
14369 .dirty = intel_user_framebuffer_dirty,
14370 };
14371
14372 static
14373 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
14374 uint64_t fb_modifier, uint32_t pixel_format)
14375 {
14376 u32 gen = INTEL_GEN(dev_priv);
14377
14378 if (gen >= 9) {
14379 int cpp = drm_format_plane_cpp(pixel_format, 0);
14380
14381 /* "The stride in bytes must not exceed the of the size of 8K
14382 * pixels and 32K bytes."
14383 */
14384 return min(8192 * cpp, 32768);
14385 } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
14386 return 32*1024;
14387 } else if (gen >= 4) {
14388 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14389 return 16*1024;
14390 else
14391 return 32*1024;
14392 } else if (gen >= 3) {
14393 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14394 return 8*1024;
14395 else
14396 return 16*1024;
14397 } else {
14398 /* XXX DSPC is limited to 4k tiled */
14399 return 8*1024;
14400 }
14401 }
14402
14403 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14404 struct drm_i915_gem_object *obj,
14405 struct drm_mode_fb_cmd2 *mode_cmd)
14406 {
14407 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14408 struct drm_format_name_buf format_name;
14409 u32 pitch_limit, stride_alignment;
14410 unsigned int tiling, stride;
14411 int ret = -EINVAL;
14412
14413 i915_gem_object_lock(obj);
14414 obj->framebuffer_references++;
14415 tiling = i915_gem_object_get_tiling(obj);
14416 stride = i915_gem_object_get_stride(obj);
14417 i915_gem_object_unlock(obj);
14418
14419 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14420 /*
14421 * If there's a fence, enforce that
14422 * the fb modifier and tiling mode match.
14423 */
14424 if (tiling != I915_TILING_NONE &&
14425 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14426 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
14427 goto err;
14428 }
14429 } else {
14430 if (tiling == I915_TILING_X) {
14431 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14432 } else if (tiling == I915_TILING_Y) {
14433 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
14434 goto err;
14435 }
14436 }
14437
14438 /* Passed in modifier sanity checking. */
14439 switch (mode_cmd->modifier[0]) {
14440 case I915_FORMAT_MOD_Y_TILED:
14441 case I915_FORMAT_MOD_Yf_TILED:
14442 if (INTEL_GEN(dev_priv) < 9) {
14443 DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
14444 mode_cmd->modifier[0]);
14445 goto err;
14446 }
14447 case DRM_FORMAT_MOD_LINEAR:
14448 case I915_FORMAT_MOD_X_TILED:
14449 break;
14450 default:
14451 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
14452 mode_cmd->modifier[0]);
14453 goto err;
14454 }
14455
14456 /*
14457 * gen2/3 display engine uses the fence if present,
14458 * so the tiling mode must match the fb modifier exactly.
14459 */
14460 if (INTEL_INFO(dev_priv)->gen < 4 &&
14461 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14462 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
14463 goto err;
14464 }
14465
14466 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14467 mode_cmd->pixel_format);
14468 if (mode_cmd->pitches[0] > pitch_limit) {
14469 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
14470 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
14471 "tiled" : "linear",
14472 mode_cmd->pitches[0], pitch_limit);
14473 goto err;
14474 }
14475
14476 /*
14477 * If there's a fence, enforce that
14478 * the fb pitch and fence stride match.
14479 */
14480 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14481 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
14482 mode_cmd->pitches[0], stride);
14483 goto err;
14484 }
14485
14486 /* Reject formats not supported by any plane early. */
14487 switch (mode_cmd->pixel_format) {
14488 case DRM_FORMAT_C8:
14489 case DRM_FORMAT_RGB565:
14490 case DRM_FORMAT_XRGB8888:
14491 case DRM_FORMAT_ARGB8888:
14492 break;
14493 case DRM_FORMAT_XRGB1555:
14494 if (INTEL_GEN(dev_priv) > 3) {
14495 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14496 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14497 goto err;
14498 }
14499 break;
14500 case DRM_FORMAT_ABGR8888:
14501 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14502 INTEL_GEN(dev_priv) < 9) {
14503 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14504 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14505 goto err;
14506 }
14507 break;
14508 case DRM_FORMAT_XBGR8888:
14509 case DRM_FORMAT_XRGB2101010:
14510 case DRM_FORMAT_XBGR2101010:
14511 if (INTEL_GEN(dev_priv) < 4) {
14512 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14513 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14514 goto err;
14515 }
14516 break;
14517 case DRM_FORMAT_ABGR2101010:
14518 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14519 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14520 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14521 goto err;
14522 }
14523 break;
14524 case DRM_FORMAT_YUYV:
14525 case DRM_FORMAT_UYVY:
14526 case DRM_FORMAT_YVYU:
14527 case DRM_FORMAT_VYUY:
14528 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
14529 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14530 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14531 goto err;
14532 }
14533 break;
14534 default:
14535 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14536 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14537 goto err;
14538 }
14539
14540 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14541 if (mode_cmd->offsets[0] != 0)
14542 goto err;
14543
14544 drm_helper_mode_fill_fb_struct(&dev_priv->drm,
14545 &intel_fb->base, mode_cmd);
14546
14547 stride_alignment = intel_fb_stride_alignment(&intel_fb->base, 0);
14548 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14549 DRM_DEBUG_KMS("pitch (%d) must be at least %u byte aligned\n",
14550 mode_cmd->pitches[0], stride_alignment);
14551 goto err;
14552 }
14553
14554 intel_fb->obj = obj;
14555
14556 ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
14557 if (ret)
14558 goto err;
14559
14560 ret = drm_framebuffer_init(obj->base.dev,
14561 &intel_fb->base,
14562 &intel_fb_funcs);
14563 if (ret) {
14564 DRM_ERROR("framebuffer init failed %d\n", ret);
14565 goto err;
14566 }
14567
14568 return 0;
14569
14570 err:
14571 i915_gem_object_lock(obj);
14572 obj->framebuffer_references--;
14573 i915_gem_object_unlock(obj);
14574 return ret;
14575 }
14576
14577 static struct drm_framebuffer *
14578 intel_user_framebuffer_create(struct drm_device *dev,
14579 struct drm_file *filp,
14580 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14581 {
14582 struct drm_framebuffer *fb;
14583 struct drm_i915_gem_object *obj;
14584 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14585
14586 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14587 if (!obj)
14588 return ERR_PTR(-ENOENT);
14589
14590 fb = intel_framebuffer_create(obj, &mode_cmd);
14591 if (IS_ERR(fb))
14592 i915_gem_object_put(obj);
14593
14594 return fb;
14595 }
14596
14597 static void intel_atomic_state_free(struct drm_atomic_state *state)
14598 {
14599 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14600
14601 drm_atomic_state_default_release(state);
14602
14603 i915_sw_fence_fini(&intel_state->commit_ready);
14604
14605 kfree(state);
14606 }
14607
14608 static const struct drm_mode_config_funcs intel_mode_funcs = {
14609 .fb_create = intel_user_framebuffer_create,
14610 .output_poll_changed = intel_fbdev_output_poll_changed,
14611 .atomic_check = intel_atomic_check,
14612 .atomic_commit = intel_atomic_commit,
14613 .atomic_state_alloc = intel_atomic_state_alloc,
14614 .atomic_state_clear = intel_atomic_state_clear,
14615 .atomic_state_free = intel_atomic_state_free,
14616 };
14617
14618 /**
14619 * intel_init_display_hooks - initialize the display modesetting hooks
14620 * @dev_priv: device private
14621 */
14622 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14623 {
14624 intel_init_cdclk_hooks(dev_priv);
14625
14626 if (INTEL_INFO(dev_priv)->gen >= 9) {
14627 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14628 dev_priv->display.get_initial_plane_config =
14629 skylake_get_initial_plane_config;
14630 dev_priv->display.crtc_compute_clock =
14631 haswell_crtc_compute_clock;
14632 dev_priv->display.crtc_enable = haswell_crtc_enable;
14633 dev_priv->display.crtc_disable = haswell_crtc_disable;
14634 } else if (HAS_DDI(dev_priv)) {
14635 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14636 dev_priv->display.get_initial_plane_config =
14637 ironlake_get_initial_plane_config;
14638 dev_priv->display.crtc_compute_clock =
14639 haswell_crtc_compute_clock;
14640 dev_priv->display.crtc_enable = haswell_crtc_enable;
14641 dev_priv->display.crtc_disable = haswell_crtc_disable;
14642 } else if (HAS_PCH_SPLIT(dev_priv)) {
14643 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14644 dev_priv->display.get_initial_plane_config =
14645 ironlake_get_initial_plane_config;
14646 dev_priv->display.crtc_compute_clock =
14647 ironlake_crtc_compute_clock;
14648 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14649 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14650 } else if (IS_CHERRYVIEW(dev_priv)) {
14651 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14652 dev_priv->display.get_initial_plane_config =
14653 i9xx_get_initial_plane_config;
14654 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14655 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14656 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14657 } else if (IS_VALLEYVIEW(dev_priv)) {
14658 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14659 dev_priv->display.get_initial_plane_config =
14660 i9xx_get_initial_plane_config;
14661 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14662 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14663 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14664 } else if (IS_G4X(dev_priv)) {
14665 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14666 dev_priv->display.get_initial_plane_config =
14667 i9xx_get_initial_plane_config;
14668 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14669 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14670 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14671 } else if (IS_PINEVIEW(dev_priv)) {
14672 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14673 dev_priv->display.get_initial_plane_config =
14674 i9xx_get_initial_plane_config;
14675 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14676 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14677 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14678 } else if (!IS_GEN2(dev_priv)) {
14679 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14680 dev_priv->display.get_initial_plane_config =
14681 i9xx_get_initial_plane_config;
14682 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14683 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14684 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14685 } else {
14686 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14687 dev_priv->display.get_initial_plane_config =
14688 i9xx_get_initial_plane_config;
14689 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14690 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14691 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14692 }
14693
14694 if (IS_GEN5(dev_priv)) {
14695 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14696 } else if (IS_GEN6(dev_priv)) {
14697 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14698 } else if (IS_IVYBRIDGE(dev_priv)) {
14699 /* FIXME: detect B0+ stepping and use auto training */
14700 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14701 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14702 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14703 }
14704
14705 if (dev_priv->info.gen >= 9)
14706 dev_priv->display.update_crtcs = skl_update_crtcs;
14707 else
14708 dev_priv->display.update_crtcs = intel_update_crtcs;
14709
14710 switch (INTEL_INFO(dev_priv)->gen) {
14711 case 2:
14712 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14713 break;
14714
14715 case 3:
14716 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14717 break;
14718
14719 case 4:
14720 case 5:
14721 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14722 break;
14723
14724 case 6:
14725 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14726 break;
14727 case 7:
14728 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14729 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14730 break;
14731 case 9:
14732 /* Drop through - unsupported since execlist only. */
14733 default:
14734 /* Default just returns -ENODEV to indicate unsupported */
14735 dev_priv->display.queue_flip = intel_default_queue_flip;
14736 }
14737 }
14738
14739 /*
14740 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14741 */
14742 static void quirk_ssc_force_disable(struct drm_device *dev)
14743 {
14744 struct drm_i915_private *dev_priv = to_i915(dev);
14745 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14746 DRM_INFO("applying lvds SSC disable quirk\n");
14747 }
14748
14749 /*
14750 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14751 * brightness value
14752 */
14753 static void quirk_invert_brightness(struct drm_device *dev)
14754 {
14755 struct drm_i915_private *dev_priv = to_i915(dev);
14756 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14757 DRM_INFO("applying inverted panel brightness quirk\n");
14758 }
14759
14760 /* Some VBT's incorrectly indicate no backlight is present */
14761 static void quirk_backlight_present(struct drm_device *dev)
14762 {
14763 struct drm_i915_private *dev_priv = to_i915(dev);
14764 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14765 DRM_INFO("applying backlight present quirk\n");
14766 }
14767
14768 struct intel_quirk {
14769 int device;
14770 int subsystem_vendor;
14771 int subsystem_device;
14772 void (*hook)(struct drm_device *dev);
14773 };
14774
14775 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14776 struct intel_dmi_quirk {
14777 void (*hook)(struct drm_device *dev);
14778 const struct dmi_system_id (*dmi_id_list)[];
14779 };
14780
14781 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14782 {
14783 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14784 return 1;
14785 }
14786
14787 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14788 {
14789 .dmi_id_list = &(const struct dmi_system_id[]) {
14790 {
14791 .callback = intel_dmi_reverse_brightness,
14792 .ident = "NCR Corporation",
14793 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14794 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14795 },
14796 },
14797 { } /* terminating entry */
14798 },
14799 .hook = quirk_invert_brightness,
14800 },
14801 };
14802
14803 static struct intel_quirk intel_quirks[] = {
14804 /* Lenovo U160 cannot use SSC on LVDS */
14805 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14806
14807 /* Sony Vaio Y cannot use SSC on LVDS */
14808 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14809
14810 /* Acer Aspire 5734Z must invert backlight brightness */
14811 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14812
14813 /* Acer/eMachines G725 */
14814 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14815
14816 /* Acer/eMachines e725 */
14817 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14818
14819 /* Acer/Packard Bell NCL20 */
14820 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14821
14822 /* Acer Aspire 4736Z */
14823 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14824
14825 /* Acer Aspire 5336 */
14826 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14827
14828 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14829 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14830
14831 /* Acer C720 Chromebook (Core i3 4005U) */
14832 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14833
14834 /* Apple Macbook 2,1 (Core 2 T7400) */
14835 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14836
14837 /* Apple Macbook 4,1 */
14838 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14839
14840 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14841 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14842
14843 /* HP Chromebook 14 (Celeron 2955U) */
14844 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14845
14846 /* Dell Chromebook 11 */
14847 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14848
14849 /* Dell Chromebook 11 (2015 version) */
14850 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14851 };
14852
14853 static void intel_init_quirks(struct drm_device *dev)
14854 {
14855 struct pci_dev *d = dev->pdev;
14856 int i;
14857
14858 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14859 struct intel_quirk *q = &intel_quirks[i];
14860
14861 if (d->device == q->device &&
14862 (d->subsystem_vendor == q->subsystem_vendor ||
14863 q->subsystem_vendor == PCI_ANY_ID) &&
14864 (d->subsystem_device == q->subsystem_device ||
14865 q->subsystem_device == PCI_ANY_ID))
14866 q->hook(dev);
14867 }
14868 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14869 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14870 intel_dmi_quirks[i].hook(dev);
14871 }
14872 }
14873
14874 /* Disable the VGA plane that we never use */
14875 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14876 {
14877 struct pci_dev *pdev = dev_priv->drm.pdev;
14878 u8 sr1;
14879 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14880
14881 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14882 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14883 outb(SR01, VGA_SR_INDEX);
14884 sr1 = inb(VGA_SR_DATA);
14885 outb(sr1 | 1<<5, VGA_SR_DATA);
14886 vga_put(pdev, VGA_RSRC_LEGACY_IO);
14887 udelay(300);
14888
14889 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14890 POSTING_READ(vga_reg);
14891 }
14892
14893 void intel_modeset_init_hw(struct drm_device *dev)
14894 {
14895 struct drm_i915_private *dev_priv = to_i915(dev);
14896
14897 intel_update_cdclk(dev_priv);
14898 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14899
14900 intel_init_clock_gating(dev_priv);
14901 }
14902
14903 /*
14904 * Calculate what we think the watermarks should be for the state we've read
14905 * out of the hardware and then immediately program those watermarks so that
14906 * we ensure the hardware settings match our internal state.
14907 *
14908 * We can calculate what we think WM's should be by creating a duplicate of the
14909 * current state (which was constructed during hardware readout) and running it
14910 * through the atomic check code to calculate new watermark values in the
14911 * state object.
14912 */
14913 static void sanitize_watermarks(struct drm_device *dev)
14914 {
14915 struct drm_i915_private *dev_priv = to_i915(dev);
14916 struct drm_atomic_state *state;
14917 struct intel_atomic_state *intel_state;
14918 struct drm_crtc *crtc;
14919 struct drm_crtc_state *cstate;
14920 struct drm_modeset_acquire_ctx ctx;
14921 int ret;
14922 int i;
14923
14924 /* Only supported on platforms that use atomic watermark design */
14925 if (!dev_priv->display.optimize_watermarks)
14926 return;
14927
14928 /*
14929 * We need to hold connection_mutex before calling duplicate_state so
14930 * that the connector loop is protected.
14931 */
14932 drm_modeset_acquire_init(&ctx, 0);
14933 retry:
14934 ret = drm_modeset_lock_all_ctx(dev, &ctx);
14935 if (ret == -EDEADLK) {
14936 drm_modeset_backoff(&ctx);
14937 goto retry;
14938 } else if (WARN_ON(ret)) {
14939 goto fail;
14940 }
14941
14942 state = drm_atomic_helper_duplicate_state(dev, &ctx);
14943 if (WARN_ON(IS_ERR(state)))
14944 goto fail;
14945
14946 intel_state = to_intel_atomic_state(state);
14947
14948 /*
14949 * Hardware readout is the only time we don't want to calculate
14950 * intermediate watermarks (since we don't trust the current
14951 * watermarks).
14952 */
14953 if (!HAS_GMCH_DISPLAY(dev_priv))
14954 intel_state->skip_intermediate_wm = true;
14955
14956 ret = intel_atomic_check(dev, state);
14957 if (ret) {
14958 /*
14959 * If we fail here, it means that the hardware appears to be
14960 * programmed in a way that shouldn't be possible, given our
14961 * understanding of watermark requirements. This might mean a
14962 * mistake in the hardware readout code or a mistake in the
14963 * watermark calculations for a given platform. Raise a WARN
14964 * so that this is noticeable.
14965 *
14966 * If this actually happens, we'll have to just leave the
14967 * BIOS-programmed watermarks untouched and hope for the best.
14968 */
14969 WARN(true, "Could not determine valid watermarks for inherited state\n");
14970 goto put_state;
14971 }
14972
14973 /* Write calculated watermark values back */
14974 for_each_new_crtc_in_state(state, crtc, cstate, i) {
14975 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14976
14977 cs->wm.need_postvbl_update = true;
14978 dev_priv->display.optimize_watermarks(intel_state, cs);
14979 }
14980
14981 put_state:
14982 drm_atomic_state_put(state);
14983 fail:
14984 drm_modeset_drop_locks(&ctx);
14985 drm_modeset_acquire_fini(&ctx);
14986 }
14987
14988 int intel_modeset_init(struct drm_device *dev)
14989 {
14990 struct drm_i915_private *dev_priv = to_i915(dev);
14991 struct i915_ggtt *ggtt = &dev_priv->ggtt;
14992 enum pipe pipe;
14993 struct intel_crtc *crtc;
14994
14995 drm_mode_config_init(dev);
14996
14997 dev->mode_config.min_width = 0;
14998 dev->mode_config.min_height = 0;
14999
15000 dev->mode_config.preferred_depth = 24;
15001 dev->mode_config.prefer_shadow = 1;
15002
15003 dev->mode_config.allow_fb_modifiers = true;
15004
15005 dev->mode_config.funcs = &intel_mode_funcs;
15006
15007 init_llist_head(&dev_priv->atomic_helper.free_list);
15008 INIT_WORK(&dev_priv->atomic_helper.free_work,
15009 intel_atomic_helper_free_state_worker);
15010
15011 intel_init_quirks(dev);
15012
15013 intel_init_pm(dev_priv);
15014
15015 if (INTEL_INFO(dev_priv)->num_pipes == 0)
15016 return 0;
15017
15018 /*
15019 * There may be no VBT; and if the BIOS enabled SSC we can
15020 * just keep using it to avoid unnecessary flicker. Whereas if the
15021 * BIOS isn't using it, don't assume it will work even if the VBT
15022 * indicates as much.
15023 */
15024 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
15025 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15026 DREF_SSC1_ENABLE);
15027
15028 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15029 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15030 bios_lvds_use_ssc ? "en" : "dis",
15031 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15032 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15033 }
15034 }
15035
15036 if (IS_GEN2(dev_priv)) {
15037 dev->mode_config.max_width = 2048;
15038 dev->mode_config.max_height = 2048;
15039 } else if (IS_GEN3(dev_priv)) {
15040 dev->mode_config.max_width = 4096;
15041 dev->mode_config.max_height = 4096;
15042 } else {
15043 dev->mode_config.max_width = 8192;
15044 dev->mode_config.max_height = 8192;
15045 }
15046
15047 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15048 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
15049 dev->mode_config.cursor_height = 1023;
15050 } else if (IS_GEN2(dev_priv)) {
15051 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15052 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15053 } else {
15054 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15055 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15056 }
15057
15058 dev->mode_config.fb_base = ggtt->mappable_base;
15059
15060 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15061 INTEL_INFO(dev_priv)->num_pipes,
15062 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
15063
15064 for_each_pipe(dev_priv, pipe) {
15065 int ret;
15066
15067 ret = intel_crtc_init(dev_priv, pipe);
15068 if (ret) {
15069 drm_mode_config_cleanup(dev);
15070 return ret;
15071 }
15072 }
15073
15074 intel_shared_dpll_init(dev);
15075
15076 intel_update_czclk(dev_priv);
15077 intel_modeset_init_hw(dev);
15078
15079 if (dev_priv->max_cdclk_freq == 0)
15080 intel_update_max_cdclk(dev_priv);
15081
15082 /* Just disable it once at startup */
15083 i915_disable_vga(dev_priv);
15084 intel_setup_outputs(dev_priv);
15085
15086 drm_modeset_lock_all(dev);
15087 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
15088 drm_modeset_unlock_all(dev);
15089
15090 for_each_intel_crtc(dev, crtc) {
15091 struct intel_initial_plane_config plane_config = {};
15092
15093 if (!crtc->active)
15094 continue;
15095
15096 /*
15097 * Note that reserving the BIOS fb up front prevents us
15098 * from stuffing other stolen allocations like the ring
15099 * on top. This prevents some ugliness at boot time, and
15100 * can even allow for smooth boot transitions if the BIOS
15101 * fb is large enough for the active pipe configuration.
15102 */
15103 dev_priv->display.get_initial_plane_config(crtc,
15104 &plane_config);
15105
15106 /*
15107 * If the fb is shared between multiple heads, we'll
15108 * just get the first one.
15109 */
15110 intel_find_initial_plane_obj(crtc, &plane_config);
15111 }
15112
15113 /*
15114 * Make sure hardware watermarks really match the state we read out.
15115 * Note that we need to do this after reconstructing the BIOS fb's
15116 * since the watermark calculation done here will use pstate->fb.
15117 */
15118 if (!HAS_GMCH_DISPLAY(dev_priv))
15119 sanitize_watermarks(dev);
15120
15121 return 0;
15122 }
15123
15124 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15125 {
15126 /* 640x480@60Hz, ~25175 kHz */
15127 struct dpll clock = {
15128 .m1 = 18,
15129 .m2 = 7,
15130 .p1 = 13,
15131 .p2 = 4,
15132 .n = 2,
15133 };
15134 u32 dpll, fp;
15135 int i;
15136
15137 WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
15138
15139 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
15140 pipe_name(pipe), clock.vco, clock.dot);
15141
15142 fp = i9xx_dpll_compute_fp(&clock);
15143 dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
15144 DPLL_VGA_MODE_DIS |
15145 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
15146 PLL_P2_DIVIDE_BY_4 |
15147 PLL_REF_INPUT_DREFCLK |
15148 DPLL_VCO_ENABLE;
15149
15150 I915_WRITE(FP0(pipe), fp);
15151 I915_WRITE(FP1(pipe), fp);
15152
15153 I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
15154 I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
15155 I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
15156 I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
15157 I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
15158 I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
15159 I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
15160
15161 /*
15162 * Apparently we need to have VGA mode enabled prior to changing
15163 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
15164 * dividers, even though the register value does change.
15165 */
15166 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
15167 I915_WRITE(DPLL(pipe), dpll);
15168
15169 /* Wait for the clocks to stabilize. */
15170 POSTING_READ(DPLL(pipe));
15171 udelay(150);
15172
15173 /* The pixel multiplier can only be updated once the
15174 * DPLL is enabled and the clocks are stable.
15175 *
15176 * So write it again.
15177 */
15178 I915_WRITE(DPLL(pipe), dpll);
15179
15180 /* We do this three times for luck */
15181 for (i = 0; i < 3 ; i++) {
15182 I915_WRITE(DPLL(pipe), dpll);
15183 POSTING_READ(DPLL(pipe));
15184 udelay(150); /* wait for warmup */
15185 }
15186
15187 I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
15188 POSTING_READ(PIPECONF(pipe));
15189 }
15190
15191 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15192 {
15193 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
15194 pipe_name(pipe));
15195
15196 assert_plane_disabled(dev_priv, PLANE_A);
15197 assert_plane_disabled(dev_priv, PLANE_B);
15198
15199 I915_WRITE(PIPECONF(pipe), 0);
15200 POSTING_READ(PIPECONF(pipe));
15201
15202 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
15203 DRM_ERROR("pipe %c off wait timed out\n", pipe_name(pipe));
15204
15205 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
15206 POSTING_READ(DPLL(pipe));
15207 }
15208
15209 static bool
15210 intel_check_plane_mapping(struct intel_crtc *crtc)
15211 {
15212 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15213 u32 val;
15214
15215 if (INTEL_INFO(dev_priv)->num_pipes == 1)
15216 return true;
15217
15218 val = I915_READ(DSPCNTR(!crtc->plane));
15219
15220 if ((val & DISPLAY_PLANE_ENABLE) &&
15221 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15222 return false;
15223
15224 return true;
15225 }
15226
15227 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15228 {
15229 struct drm_device *dev = crtc->base.dev;
15230 struct intel_encoder *encoder;
15231
15232 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15233 return true;
15234
15235 return false;
15236 }
15237
15238 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15239 {
15240 struct drm_device *dev = encoder->base.dev;
15241 struct intel_connector *connector;
15242
15243 for_each_connector_on_encoder(dev, &encoder->base, connector)
15244 return connector;
15245
15246 return NULL;
15247 }
15248
15249 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15250 enum transcoder pch_transcoder)
15251 {
15252 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15253 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
15254 }
15255
15256 static void intel_sanitize_crtc(struct intel_crtc *crtc,
15257 struct drm_modeset_acquire_ctx *ctx)
15258 {
15259 struct drm_device *dev = crtc->base.dev;
15260 struct drm_i915_private *dev_priv = to_i915(dev);
15261 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15262
15263 /* Clear any frame start delays used for debugging left by the BIOS */
15264 if (!transcoder_is_dsi(cpu_transcoder)) {
15265 i915_reg_t reg = PIPECONF(cpu_transcoder);
15266
15267 I915_WRITE(reg,
15268 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15269 }
15270
15271 /* restore vblank interrupts to correct state */
15272 drm_crtc_vblank_reset(&crtc->base);
15273 if (crtc->active) {
15274 struct intel_plane *plane;
15275
15276 drm_crtc_vblank_on(&crtc->base);
15277
15278 /* Disable everything but the primary plane */
15279 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15280 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15281 continue;
15282
15283 trace_intel_disable_plane(&plane->base, crtc);
15284 plane->disable_plane(plane, crtc);
15285 }
15286 }
15287
15288 /* We need to sanitize the plane -> pipe mapping first because this will
15289 * disable the crtc (and hence change the state) if it is wrong. Note
15290 * that gen4+ has a fixed plane -> pipe mapping. */
15291 if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
15292 bool plane;
15293
15294 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15295 crtc->base.base.id, crtc->base.name);
15296
15297 /* Pipe has the wrong plane attached and the plane is active.
15298 * Temporarily change the plane mapping and disable everything
15299 * ... */
15300 plane = crtc->plane;
15301 crtc->base.primary->state->visible = true;
15302 crtc->plane = !plane;
15303 intel_crtc_disable_noatomic(&crtc->base, ctx);
15304 crtc->plane = plane;
15305 }
15306
15307 /* Adjust the state of the output pipe according to whether we
15308 * have active connectors/encoders. */
15309 if (crtc->active && !intel_crtc_has_encoders(crtc))
15310 intel_crtc_disable_noatomic(&crtc->base, ctx);
15311
15312 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
15313 /*
15314 * We start out with underrun reporting disabled to avoid races.
15315 * For correct bookkeeping mark this on active crtcs.
15316 *
15317 * Also on gmch platforms we dont have any hardware bits to
15318 * disable the underrun reporting. Which means we need to start
15319 * out with underrun reporting disabled also on inactive pipes,
15320 * since otherwise we'll complain about the garbage we read when
15321 * e.g. coming up after runtime pm.
15322 *
15323 * No protection against concurrent access is required - at
15324 * worst a fifo underrun happens which also sets this to false.
15325 */
15326 crtc->cpu_fifo_underrun_disabled = true;
15327 /*
15328 * We track the PCH trancoder underrun reporting state
15329 * within the crtc. With crtc for pipe A housing the underrun
15330 * reporting state for PCH transcoder A, crtc for pipe B housing
15331 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15332 * and marking underrun reporting as disabled for the non-existing
15333 * PCH transcoders B and C would prevent enabling the south
15334 * error interrupt (see cpt_can_enable_serr_int()).
15335 */
15336 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
15337 crtc->pch_fifo_underrun_disabled = true;
15338 }
15339 }
15340
15341 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15342 {
15343 struct intel_connector *connector;
15344
15345 /* We need to check both for a crtc link (meaning that the
15346 * encoder is active and trying to read from a pipe) and the
15347 * pipe itself being active. */
15348 bool has_active_crtc = encoder->base.crtc &&
15349 to_intel_crtc(encoder->base.crtc)->active;
15350
15351 connector = intel_encoder_find_connector(encoder);
15352 if (connector && !has_active_crtc) {
15353 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15354 encoder->base.base.id,
15355 encoder->base.name);
15356
15357 /* Connector is active, but has no active pipe. This is
15358 * fallout from our resume register restoring. Disable
15359 * the encoder manually again. */
15360 if (encoder->base.crtc) {
15361 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
15362
15363 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15364 encoder->base.base.id,
15365 encoder->base.name);
15366 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15367 if (encoder->post_disable)
15368 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15369 }
15370 encoder->base.crtc = NULL;
15371
15372 /* Inconsistent output/port/pipe state happens presumably due to
15373 * a bug in one of the get_hw_state functions. Or someplace else
15374 * in our code, like the register restore mess on resume. Clamp
15375 * things to off as a safer default. */
15376
15377 connector->base.dpms = DRM_MODE_DPMS_OFF;
15378 connector->base.encoder = NULL;
15379 }
15380 /* Enabled encoders without active connectors will be fixed in
15381 * the crtc fixup. */
15382 }
15383
15384 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
15385 {
15386 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15387
15388 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15389 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15390 i915_disable_vga(dev_priv);
15391 }
15392 }
15393
15394 void i915_redisable_vga(struct drm_i915_private *dev_priv)
15395 {
15396 /* This function can be called both from intel_modeset_setup_hw_state or
15397 * at a very early point in our resume sequence, where the power well
15398 * structures are not yet restored. Since this function is at a very
15399 * paranoid "someone might have enabled VGA while we were not looking"
15400 * level, just check if the power well is enabled instead of trying to
15401 * follow the "don't touch the power well if we don't need it" policy
15402 * the rest of the driver uses. */
15403 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15404 return;
15405
15406 i915_redisable_vga_power_on(dev_priv);
15407
15408 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15409 }
15410
15411 static bool primary_get_hw_state(struct intel_plane *plane)
15412 {
15413 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15414
15415 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15416 }
15417
15418 /* FIXME read out full plane state for all planes */
15419 static void readout_plane_state(struct intel_crtc *crtc)
15420 {
15421 struct intel_plane *primary = to_intel_plane(crtc->base.primary);
15422 bool visible;
15423
15424 visible = crtc->active && primary_get_hw_state(primary);
15425
15426 intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
15427 to_intel_plane_state(primary->base.state),
15428 visible);
15429 }
15430
15431 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15432 {
15433 struct drm_i915_private *dev_priv = to_i915(dev);
15434 enum pipe pipe;
15435 struct intel_crtc *crtc;
15436 struct intel_encoder *encoder;
15437 struct intel_connector *connector;
15438 struct drm_connector_list_iter conn_iter;
15439 int i;
15440
15441 dev_priv->active_crtcs = 0;
15442
15443 for_each_intel_crtc(dev, crtc) {
15444 struct intel_crtc_state *crtc_state =
15445 to_intel_crtc_state(crtc->base.state);
15446
15447 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15448 memset(crtc_state, 0, sizeof(*crtc_state));
15449 crtc_state->base.crtc = &crtc->base;
15450
15451 crtc_state->base.active = crtc_state->base.enable =
15452 dev_priv->display.get_pipe_config(crtc, crtc_state);
15453
15454 crtc->base.enabled = crtc_state->base.enable;
15455 crtc->active = crtc_state->base.active;
15456
15457 if (crtc_state->base.active)
15458 dev_priv->active_crtcs |= 1 << crtc->pipe;
15459
15460 readout_plane_state(crtc);
15461
15462 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15463 crtc->base.base.id, crtc->base.name,
15464 enableddisabled(crtc_state->base.active));
15465 }
15466
15467 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15468 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15469
15470 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15471 &pll->state.hw_state);
15472 pll->state.crtc_mask = 0;
15473 for_each_intel_crtc(dev, crtc) {
15474 struct intel_crtc_state *crtc_state =
15475 to_intel_crtc_state(crtc->base.state);
15476
15477 if (crtc_state->base.active &&
15478 crtc_state->shared_dpll == pll)
15479 pll->state.crtc_mask |= 1 << crtc->pipe;
15480 }
15481 pll->active_mask = pll->state.crtc_mask;
15482
15483 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15484 pll->name, pll->state.crtc_mask, pll->on);
15485 }
15486
15487 for_each_intel_encoder(dev, encoder) {
15488 pipe = 0;
15489
15490 if (encoder->get_hw_state(encoder, &pipe)) {
15491 struct intel_crtc_state *crtc_state;
15492
15493 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15494 crtc_state = to_intel_crtc_state(crtc->base.state);
15495
15496 encoder->base.crtc = &crtc->base;
15497 crtc_state->output_types |= 1 << encoder->type;
15498 encoder->get_config(encoder, crtc_state);
15499 } else {
15500 encoder->base.crtc = NULL;
15501 }
15502
15503 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15504 encoder->base.base.id, encoder->base.name,
15505 enableddisabled(encoder->base.crtc),
15506 pipe_name(pipe));
15507 }
15508
15509 drm_connector_list_iter_begin(dev, &conn_iter);
15510 for_each_intel_connector_iter(connector, &conn_iter) {
15511 if (connector->get_hw_state(connector)) {
15512 connector->base.dpms = DRM_MODE_DPMS_ON;
15513
15514 encoder = connector->encoder;
15515 connector->base.encoder = &encoder->base;
15516
15517 if (encoder->base.crtc &&
15518 encoder->base.crtc->state->active) {
15519 /*
15520 * This has to be done during hardware readout
15521 * because anything calling .crtc_disable may
15522 * rely on the connector_mask being accurate.
15523 */
15524 encoder->base.crtc->state->connector_mask |=
15525 1 << drm_connector_index(&connector->base);
15526 encoder->base.crtc->state->encoder_mask |=
15527 1 << drm_encoder_index(&encoder->base);
15528 }
15529
15530 } else {
15531 connector->base.dpms = DRM_MODE_DPMS_OFF;
15532 connector->base.encoder = NULL;
15533 }
15534 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15535 connector->base.base.id, connector->base.name,
15536 enableddisabled(connector->base.encoder));
15537 }
15538 drm_connector_list_iter_end(&conn_iter);
15539
15540 for_each_intel_crtc(dev, crtc) {
15541 struct intel_crtc_state *crtc_state =
15542 to_intel_crtc_state(crtc->base.state);
15543 int pixclk = 0;
15544
15545 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15546 if (crtc_state->base.active) {
15547 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15548 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15549 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15550
15551 /*
15552 * The initial mode needs to be set in order to keep
15553 * the atomic core happy. It wants a valid mode if the
15554 * crtc's enabled, so we do the above call.
15555 *
15556 * But we don't set all the derived state fully, hence
15557 * set a flag to indicate that a full recalculation is
15558 * needed on the next commit.
15559 */
15560 crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15561
15562 intel_crtc_compute_pixel_rate(crtc_state);
15563
15564 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) ||
15565 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15566 pixclk = crtc_state->pixel_rate;
15567 else
15568 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15569
15570 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15571 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
15572 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15573
15574 drm_calc_timestamping_constants(&crtc->base,
15575 &crtc_state->base.adjusted_mode);
15576 update_scanline_offset(crtc);
15577 }
15578
15579 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15580
15581 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15582 }
15583 }
15584
15585 static void
15586 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15587 {
15588 struct intel_encoder *encoder;
15589
15590 for_each_intel_encoder(&dev_priv->drm, encoder) {
15591 u64 get_domains;
15592 enum intel_display_power_domain domain;
15593
15594 if (!encoder->get_power_domains)
15595 continue;
15596
15597 get_domains = encoder->get_power_domains(encoder);
15598 for_each_power_domain(domain, get_domains)
15599 intel_display_power_get(dev_priv, domain);
15600 }
15601 }
15602
15603 /* Scan out the current hw modeset state,
15604 * and sanitizes it to the current state
15605 */
15606 static void
15607 intel_modeset_setup_hw_state(struct drm_device *dev,
15608 struct drm_modeset_acquire_ctx *ctx)
15609 {
15610 struct drm_i915_private *dev_priv = to_i915(dev);
15611 enum pipe pipe;
15612 struct intel_crtc *crtc;
15613 struct intel_encoder *encoder;
15614 int i;
15615
15616 intel_modeset_readout_hw_state(dev);
15617
15618 /* HW state is read out, now we need to sanitize this mess. */
15619 get_encoder_power_domains(dev_priv);
15620
15621 for_each_intel_encoder(dev, encoder) {
15622 intel_sanitize_encoder(encoder);
15623 }
15624
15625 for_each_pipe(dev_priv, pipe) {
15626 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15627
15628 intel_sanitize_crtc(crtc, ctx);
15629 intel_dump_pipe_config(crtc, crtc->config,
15630 "[setup_hw_state]");
15631 }
15632
15633 intel_modeset_update_connector_atomic_state(dev);
15634
15635 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15636 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15637
15638 if (!pll->on || pll->active_mask)
15639 continue;
15640
15641 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15642
15643 pll->funcs.disable(dev_priv, pll);
15644 pll->on = false;
15645 }
15646
15647 if (IS_G4X(dev_priv)) {
15648 g4x_wm_get_hw_state(dev);
15649 g4x_wm_sanitize(dev_priv);
15650 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15651 vlv_wm_get_hw_state(dev);
15652 vlv_wm_sanitize(dev_priv);
15653 } else if (IS_GEN9(dev_priv)) {
15654 skl_wm_get_hw_state(dev);
15655 } else if (HAS_PCH_SPLIT(dev_priv)) {
15656 ilk_wm_get_hw_state(dev);
15657 }
15658
15659 for_each_intel_crtc(dev, crtc) {
15660 u64 put_domains;
15661
15662 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15663 if (WARN_ON(put_domains))
15664 modeset_put_power_domains(dev_priv, put_domains);
15665 }
15666 intel_display_set_init_power(dev_priv, false);
15667
15668 intel_power_domains_verify_state(dev_priv);
15669
15670 intel_fbc_init_pipe_state(dev_priv);
15671 }
15672
15673 void intel_display_resume(struct drm_device *dev)
15674 {
15675 struct drm_i915_private *dev_priv = to_i915(dev);
15676 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15677 struct drm_modeset_acquire_ctx ctx;
15678 int ret;
15679
15680 dev_priv->modeset_restore_state = NULL;
15681 if (state)
15682 state->acquire_ctx = &ctx;
15683
15684 drm_modeset_acquire_init(&ctx, 0);
15685
15686 while (1) {
15687 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15688 if (ret != -EDEADLK)
15689 break;
15690
15691 drm_modeset_backoff(&ctx);
15692 }
15693
15694 if (!ret)
15695 ret = __intel_display_resume(dev, state, &ctx);
15696
15697 drm_modeset_drop_locks(&ctx);
15698 drm_modeset_acquire_fini(&ctx);
15699
15700 if (ret)
15701 DRM_ERROR("Restoring old state failed with %i\n", ret);
15702 if (state)
15703 drm_atomic_state_put(state);
15704 }
15705
15706 void intel_modeset_gem_init(struct drm_device *dev)
15707 {
15708 struct drm_i915_private *dev_priv = to_i915(dev);
15709
15710 intel_init_gt_powersave(dev_priv);
15711
15712 intel_setup_overlay(dev_priv);
15713 }
15714
15715 int intel_connector_register(struct drm_connector *connector)
15716 {
15717 struct intel_connector *intel_connector = to_intel_connector(connector);
15718 int ret;
15719
15720 ret = intel_backlight_device_register(intel_connector);
15721 if (ret)
15722 goto err;
15723
15724 return 0;
15725
15726 err:
15727 return ret;
15728 }
15729
15730 void intel_connector_unregister(struct drm_connector *connector)
15731 {
15732 struct intel_connector *intel_connector = to_intel_connector(connector);
15733
15734 intel_backlight_device_unregister(intel_connector);
15735 intel_panel_destroy_backlight(connector);
15736 }
15737
15738 void intel_modeset_cleanup(struct drm_device *dev)
15739 {
15740 struct drm_i915_private *dev_priv = to_i915(dev);
15741
15742 flush_work(&dev_priv->atomic_helper.free_work);
15743 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15744
15745 intel_disable_gt_powersave(dev_priv);
15746
15747 /*
15748 * Interrupts and polling as the first thing to avoid creating havoc.
15749 * Too much stuff here (turning of connectors, ...) would
15750 * experience fancy races otherwise.
15751 */
15752 intel_irq_uninstall(dev_priv);
15753
15754 /*
15755 * Due to the hpd irq storm handling the hotplug work can re-arm the
15756 * poll handlers. Hence disable polling after hpd handling is shut down.
15757 */
15758 drm_kms_helper_poll_fini(dev);
15759
15760 intel_unregister_dsm_handler();
15761
15762 intel_fbc_global_disable(dev_priv);
15763
15764 /* flush any delayed tasks or pending work */
15765 flush_scheduled_work();
15766
15767 drm_mode_config_cleanup(dev);
15768
15769 intel_cleanup_overlay(dev_priv);
15770
15771 intel_cleanup_gt_powersave(dev_priv);
15772
15773 intel_teardown_gmbus(dev_priv);
15774 }
15775
15776 void intel_connector_attach_encoder(struct intel_connector *connector,
15777 struct intel_encoder *encoder)
15778 {
15779 connector->encoder = encoder;
15780 drm_mode_connector_attach_encoder(&connector->base,
15781 &encoder->base);
15782 }
15783
15784 /*
15785 * set vga decode state - true == enable VGA decode
15786 */
15787 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15788 {
15789 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15790 u16 gmch_ctrl;
15791
15792 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15793 DRM_ERROR("failed to read control word\n");
15794 return -EIO;
15795 }
15796
15797 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15798 return 0;
15799
15800 if (state)
15801 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15802 else
15803 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15804
15805 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15806 DRM_ERROR("failed to write control word\n");
15807 return -EIO;
15808 }
15809
15810 return 0;
15811 }
15812
15813 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15814
15815 struct intel_display_error_state {
15816
15817 u32 power_well_driver;
15818
15819 int num_transcoders;
15820
15821 struct intel_cursor_error_state {
15822 u32 control;
15823 u32 position;
15824 u32 base;
15825 u32 size;
15826 } cursor[I915_MAX_PIPES];
15827
15828 struct intel_pipe_error_state {
15829 bool power_domain_on;
15830 u32 source;
15831 u32 stat;
15832 } pipe[I915_MAX_PIPES];
15833
15834 struct intel_plane_error_state {
15835 u32 control;
15836 u32 stride;
15837 u32 size;
15838 u32 pos;
15839 u32 addr;
15840 u32 surface;
15841 u32 tile_offset;
15842 } plane[I915_MAX_PIPES];
15843
15844 struct intel_transcoder_error_state {
15845 bool power_domain_on;
15846 enum transcoder cpu_transcoder;
15847
15848 u32 conf;
15849
15850 u32 htotal;
15851 u32 hblank;
15852 u32 hsync;
15853 u32 vtotal;
15854 u32 vblank;
15855 u32 vsync;
15856 } transcoder[4];
15857 };
15858
15859 struct intel_display_error_state *
15860 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15861 {
15862 struct intel_display_error_state *error;
15863 int transcoders[] = {
15864 TRANSCODER_A,
15865 TRANSCODER_B,
15866 TRANSCODER_C,
15867 TRANSCODER_EDP,
15868 };
15869 int i;
15870
15871 if (INTEL_INFO(dev_priv)->num_pipes == 0)
15872 return NULL;
15873
15874 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15875 if (error == NULL)
15876 return NULL;
15877
15878 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15879 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15880
15881 for_each_pipe(dev_priv, i) {
15882 error->pipe[i].power_domain_on =
15883 __intel_display_power_is_enabled(dev_priv,
15884 POWER_DOMAIN_PIPE(i));
15885 if (!error->pipe[i].power_domain_on)
15886 continue;
15887
15888 error->cursor[i].control = I915_READ(CURCNTR(i));
15889 error->cursor[i].position = I915_READ(CURPOS(i));
15890 error->cursor[i].base = I915_READ(CURBASE(i));
15891
15892 error->plane[i].control = I915_READ(DSPCNTR(i));
15893 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15894 if (INTEL_GEN(dev_priv) <= 3) {
15895 error->plane[i].size = I915_READ(DSPSIZE(i));
15896 error->plane[i].pos = I915_READ(DSPPOS(i));
15897 }
15898 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15899 error->plane[i].addr = I915_READ(DSPADDR(i));
15900 if (INTEL_GEN(dev_priv) >= 4) {
15901 error->plane[i].surface = I915_READ(DSPSURF(i));
15902 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15903 }
15904
15905 error->pipe[i].source = I915_READ(PIPESRC(i));
15906
15907 if (HAS_GMCH_DISPLAY(dev_priv))
15908 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15909 }
15910
15911 /* Note: this does not include DSI transcoders. */
15912 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15913 if (HAS_DDI(dev_priv))
15914 error->num_transcoders++; /* Account for eDP. */
15915
15916 for (i = 0; i < error->num_transcoders; i++) {
15917 enum transcoder cpu_transcoder = transcoders[i];
15918
15919 error->transcoder[i].power_domain_on =
15920 __intel_display_power_is_enabled(dev_priv,
15921 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15922 if (!error->transcoder[i].power_domain_on)
15923 continue;
15924
15925 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15926
15927 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15928 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15929 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15930 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15931 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15932 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15933 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15934 }
15935
15936 return error;
15937 }
15938
15939 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15940
15941 void
15942 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15943 struct intel_display_error_state *error)
15944 {
15945 struct drm_i915_private *dev_priv = m->i915;
15946 int i;
15947
15948 if (!error)
15949 return;
15950
15951 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15952 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15953 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15954 error->power_well_driver);
15955 for_each_pipe(dev_priv, i) {
15956 err_printf(m, "Pipe [%d]:\n", i);
15957 err_printf(m, " Power: %s\n",
15958 onoff(error->pipe[i].power_domain_on));
15959 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15960 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15961
15962 err_printf(m, "Plane [%d]:\n", i);
15963 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15964 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15965 if (INTEL_GEN(dev_priv) <= 3) {
15966 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15967 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15968 }
15969 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15970 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15971 if (INTEL_GEN(dev_priv) >= 4) {
15972 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15973 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15974 }
15975
15976 err_printf(m, "Cursor [%d]:\n", i);
15977 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15978 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15979 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15980 }
15981
15982 for (i = 0; i < error->num_transcoders; i++) {
15983 err_printf(m, "CPU transcoder: %s\n",
15984 transcoder_name(error->transcoder[i].cpu_transcoder));
15985 err_printf(m, " Power: %s\n",
15986 onoff(error->transcoder[i].power_domain_on));
15987 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15988 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15989 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15990 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15991 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15992 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15993 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15994 }
15995 }
15996
15997 #endif
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