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drm/i915: Check hw state in assert_can_disable_lcpll
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
78
79 static void intel_increase_pllclock(struct drm_device *dev,
80 enum pipe pipe);
81 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
82
83 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
84 struct intel_crtc_config *pipe_config);
85 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
86 struct intel_crtc_config *pipe_config);
87
88 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
89 int x, int y, struct drm_framebuffer *old_fb);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void intel_dp_set_m_n(struct intel_crtc *crtc);
95 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
96 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
97 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
98 struct intel_link_m_n *m_n);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc);
103
104 typedef struct {
105 int min, max;
106 } intel_range_t;
107
108 typedef struct {
109 int dot_limit;
110 int p2_slow, p2_fast;
111 } intel_p2_t;
112
113 typedef struct intel_limit intel_limit_t;
114 struct intel_limit {
115 intel_range_t dot, vco, n, m, m1, m2, p, p1;
116 intel_p2_t p2;
117 };
118
119 int
120 intel_pch_rawclk(struct drm_device *dev)
121 {
122 struct drm_i915_private *dev_priv = dev->dev_private;
123
124 WARN_ON(!HAS_PCH_SPLIT(dev));
125
126 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
127 }
128
129 static inline u32 /* units of 100MHz */
130 intel_fdi_link_freq(struct drm_device *dev)
131 {
132 if (IS_GEN5(dev)) {
133 struct drm_i915_private *dev_priv = dev->dev_private;
134 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
135 } else
136 return 27;
137 }
138
139 static const intel_limit_t intel_limits_i8xx_dac = {
140 .dot = { .min = 25000, .max = 350000 },
141 .vco = { .min = 908000, .max = 1512000 },
142 .n = { .min = 2, .max = 16 },
143 .m = { .min = 96, .max = 140 },
144 .m1 = { .min = 18, .max = 26 },
145 .m2 = { .min = 6, .max = 16 },
146 .p = { .min = 4, .max = 128 },
147 .p1 = { .min = 2, .max = 33 },
148 .p2 = { .dot_limit = 165000,
149 .p2_slow = 4, .p2_fast = 2 },
150 };
151
152 static const intel_limit_t intel_limits_i8xx_dvo = {
153 .dot = { .min = 25000, .max = 350000 },
154 .vco = { .min = 908000, .max = 1512000 },
155 .n = { .min = 2, .max = 16 },
156 .m = { .min = 96, .max = 140 },
157 .m1 = { .min = 18, .max = 26 },
158 .m2 = { .min = 6, .max = 16 },
159 .p = { .min = 4, .max = 128 },
160 .p1 = { .min = 2, .max = 33 },
161 .p2 = { .dot_limit = 165000,
162 .p2_slow = 4, .p2_fast = 4 },
163 };
164
165 static const intel_limit_t intel_limits_i8xx_lvds = {
166 .dot = { .min = 25000, .max = 350000 },
167 .vco = { .min = 908000, .max = 1512000 },
168 .n = { .min = 2, .max = 16 },
169 .m = { .min = 96, .max = 140 },
170 .m1 = { .min = 18, .max = 26 },
171 .m2 = { .min = 6, .max = 16 },
172 .p = { .min = 4, .max = 128 },
173 .p1 = { .min = 1, .max = 6 },
174 .p2 = { .dot_limit = 165000,
175 .p2_slow = 14, .p2_fast = 7 },
176 };
177
178 static const intel_limit_t intel_limits_i9xx_sdvo = {
179 .dot = { .min = 20000, .max = 400000 },
180 .vco = { .min = 1400000, .max = 2800000 },
181 .n = { .min = 1, .max = 6 },
182 .m = { .min = 70, .max = 120 },
183 .m1 = { .min = 8, .max = 18 },
184 .m2 = { .min = 3, .max = 7 },
185 .p = { .min = 5, .max = 80 },
186 .p1 = { .min = 1, .max = 8 },
187 .p2 = { .dot_limit = 200000,
188 .p2_slow = 10, .p2_fast = 5 },
189 };
190
191 static const intel_limit_t intel_limits_i9xx_lvds = {
192 .dot = { .min = 20000, .max = 400000 },
193 .vco = { .min = 1400000, .max = 2800000 },
194 .n = { .min = 1, .max = 6 },
195 .m = { .min = 70, .max = 120 },
196 .m1 = { .min = 8, .max = 18 },
197 .m2 = { .min = 3, .max = 7 },
198 .p = { .min = 7, .max = 98 },
199 .p1 = { .min = 1, .max = 8 },
200 .p2 = { .dot_limit = 112000,
201 .p2_slow = 14, .p2_fast = 7 },
202 };
203
204
205 static const intel_limit_t intel_limits_g4x_sdvo = {
206 .dot = { .min = 25000, .max = 270000 },
207 .vco = { .min = 1750000, .max = 3500000},
208 .n = { .min = 1, .max = 4 },
209 .m = { .min = 104, .max = 138 },
210 .m1 = { .min = 17, .max = 23 },
211 .m2 = { .min = 5, .max = 11 },
212 .p = { .min = 10, .max = 30 },
213 .p1 = { .min = 1, .max = 3},
214 .p2 = { .dot_limit = 270000,
215 .p2_slow = 10,
216 .p2_fast = 10
217 },
218 };
219
220 static const intel_limit_t intel_limits_g4x_hdmi = {
221 .dot = { .min = 22000, .max = 400000 },
222 .vco = { .min = 1750000, .max = 3500000},
223 .n = { .min = 1, .max = 4 },
224 .m = { .min = 104, .max = 138 },
225 .m1 = { .min = 16, .max = 23 },
226 .m2 = { .min = 5, .max = 11 },
227 .p = { .min = 5, .max = 80 },
228 .p1 = { .min = 1, .max = 8},
229 .p2 = { .dot_limit = 165000,
230 .p2_slow = 10, .p2_fast = 5 },
231 };
232
233 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
234 .dot = { .min = 20000, .max = 115000 },
235 .vco = { .min = 1750000, .max = 3500000 },
236 .n = { .min = 1, .max = 3 },
237 .m = { .min = 104, .max = 138 },
238 .m1 = { .min = 17, .max = 23 },
239 .m2 = { .min = 5, .max = 11 },
240 .p = { .min = 28, .max = 112 },
241 .p1 = { .min = 2, .max = 8 },
242 .p2 = { .dot_limit = 0,
243 .p2_slow = 14, .p2_fast = 14
244 },
245 };
246
247 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
248 .dot = { .min = 80000, .max = 224000 },
249 .vco = { .min = 1750000, .max = 3500000 },
250 .n = { .min = 1, .max = 3 },
251 .m = { .min = 104, .max = 138 },
252 .m1 = { .min = 17, .max = 23 },
253 .m2 = { .min = 5, .max = 11 },
254 .p = { .min = 14, .max = 42 },
255 .p1 = { .min = 2, .max = 6 },
256 .p2 = { .dot_limit = 0,
257 .p2_slow = 7, .p2_fast = 7
258 },
259 };
260
261 static const intel_limit_t intel_limits_pineview_sdvo = {
262 .dot = { .min = 20000, .max = 400000},
263 .vco = { .min = 1700000, .max = 3500000 },
264 /* Pineview's Ncounter is a ring counter */
265 .n = { .min = 3, .max = 6 },
266 .m = { .min = 2, .max = 256 },
267 /* Pineview only has one combined m divider, which we treat as m2. */
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 5, .max = 80 },
271 .p1 = { .min = 1, .max = 8 },
272 .p2 = { .dot_limit = 200000,
273 .p2_slow = 10, .p2_fast = 5 },
274 };
275
276 static const intel_limit_t intel_limits_pineview_lvds = {
277 .dot = { .min = 20000, .max = 400000 },
278 .vco = { .min = 1700000, .max = 3500000 },
279 .n = { .min = 3, .max = 6 },
280 .m = { .min = 2, .max = 256 },
281 .m1 = { .min = 0, .max = 0 },
282 .m2 = { .min = 0, .max = 254 },
283 .p = { .min = 7, .max = 112 },
284 .p1 = { .min = 1, .max = 8 },
285 .p2 = { .dot_limit = 112000,
286 .p2_slow = 14, .p2_fast = 14 },
287 };
288
289 /* Ironlake / Sandybridge
290 *
291 * We calculate clock using (register_value + 2) for N/M1/M2, so here
292 * the range value for them is (actual_value - 2).
293 */
294 static const intel_limit_t intel_limits_ironlake_dac = {
295 .dot = { .min = 25000, .max = 350000 },
296 .vco = { .min = 1760000, .max = 3510000 },
297 .n = { .min = 1, .max = 5 },
298 .m = { .min = 79, .max = 127 },
299 .m1 = { .min = 12, .max = 22 },
300 .m2 = { .min = 5, .max = 9 },
301 .p = { .min = 5, .max = 80 },
302 .p1 = { .min = 1, .max = 8 },
303 .p2 = { .dot_limit = 225000,
304 .p2_slow = 10, .p2_fast = 5 },
305 };
306
307 static const intel_limit_t intel_limits_ironlake_single_lvds = {
308 .dot = { .min = 25000, .max = 350000 },
309 .vco = { .min = 1760000, .max = 3510000 },
310 .n = { .min = 1, .max = 3 },
311 .m = { .min = 79, .max = 118 },
312 .m1 = { .min = 12, .max = 22 },
313 .m2 = { .min = 5, .max = 9 },
314 .p = { .min = 28, .max = 112 },
315 .p1 = { .min = 2, .max = 8 },
316 .p2 = { .dot_limit = 225000,
317 .p2_slow = 14, .p2_fast = 14 },
318 };
319
320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 127 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 14, .max = 56 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 7, .p2_fast = 7 },
331 };
332
333 /* LVDS 100mhz refclk limits. */
334 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 2 },
338 .m = { .min = 79, .max = 126 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 28, .max = 112 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 14, .p2_fast = 14 },
345 };
346
347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
355 .p1 = { .min = 2, .max = 6 },
356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
358 };
359
360 static const intel_limit_t intel_limits_vlv = {
361 /*
362 * These are the data rate limits (measured in fast clocks)
363 * since those are the strictest limits we have. The fast
364 * clock and actual rate limits are more relaxed, so checking
365 * them would make no difference.
366 */
367 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
368 .vco = { .min = 4000000, .max = 6000000 },
369 .n = { .min = 1, .max = 7 },
370 .m1 = { .min = 2, .max = 3 },
371 .m2 = { .min = 11, .max = 156 },
372 .p1 = { .min = 2, .max = 3 },
373 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
374 };
375
376 static const intel_limit_t intel_limits_chv = {
377 /*
378 * These are the data rate limits (measured in fast clocks)
379 * since those are the strictest limits we have. The fast
380 * clock and actual rate limits are more relaxed, so checking
381 * them would make no difference.
382 */
383 .dot = { .min = 25000 * 5, .max = 540000 * 5},
384 .vco = { .min = 4860000, .max = 6700000 },
385 .n = { .min = 1, .max = 1 },
386 .m1 = { .min = 2, .max = 2 },
387 .m2 = { .min = 24 << 22, .max = 175 << 22 },
388 .p1 = { .min = 2, .max = 4 },
389 .p2 = { .p2_slow = 1, .p2_fast = 14 },
390 };
391
392 static void vlv_clock(int refclk, intel_clock_t *clock)
393 {
394 clock->m = clock->m1 * clock->m2;
395 clock->p = clock->p1 * clock->p2;
396 if (WARN_ON(clock->n == 0 || clock->p == 0))
397 return;
398 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
399 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
400 }
401
402 /**
403 * Returns whether any output on the specified pipe is of the specified type
404 */
405 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
406 {
407 struct drm_device *dev = crtc->dev;
408 struct intel_encoder *encoder;
409
410 for_each_encoder_on_crtc(dev, crtc, encoder)
411 if (encoder->type == type)
412 return true;
413
414 return false;
415 }
416
417 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
418 int refclk)
419 {
420 struct drm_device *dev = crtc->dev;
421 const intel_limit_t *limit;
422
423 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
424 if (intel_is_dual_link_lvds(dev)) {
425 if (refclk == 100000)
426 limit = &intel_limits_ironlake_dual_lvds_100m;
427 else
428 limit = &intel_limits_ironlake_dual_lvds;
429 } else {
430 if (refclk == 100000)
431 limit = &intel_limits_ironlake_single_lvds_100m;
432 else
433 limit = &intel_limits_ironlake_single_lvds;
434 }
435 } else
436 limit = &intel_limits_ironlake_dac;
437
438 return limit;
439 }
440
441 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
442 {
443 struct drm_device *dev = crtc->dev;
444 const intel_limit_t *limit;
445
446 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
447 if (intel_is_dual_link_lvds(dev))
448 limit = &intel_limits_g4x_dual_channel_lvds;
449 else
450 limit = &intel_limits_g4x_single_channel_lvds;
451 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
452 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
453 limit = &intel_limits_g4x_hdmi;
454 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
455 limit = &intel_limits_g4x_sdvo;
456 } else /* The option is for other outputs */
457 limit = &intel_limits_i9xx_sdvo;
458
459 return limit;
460 }
461
462 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
463 {
464 struct drm_device *dev = crtc->dev;
465 const intel_limit_t *limit;
466
467 if (HAS_PCH_SPLIT(dev))
468 limit = intel_ironlake_limit(crtc, refclk);
469 else if (IS_G4X(dev)) {
470 limit = intel_g4x_limit(crtc);
471 } else if (IS_PINEVIEW(dev)) {
472 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
473 limit = &intel_limits_pineview_lvds;
474 else
475 limit = &intel_limits_pineview_sdvo;
476 } else if (IS_CHERRYVIEW(dev)) {
477 limit = &intel_limits_chv;
478 } else if (IS_VALLEYVIEW(dev)) {
479 limit = &intel_limits_vlv;
480 } else if (!IS_GEN2(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
482 limit = &intel_limits_i9xx_lvds;
483 else
484 limit = &intel_limits_i9xx_sdvo;
485 } else {
486 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
487 limit = &intel_limits_i8xx_lvds;
488 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
489 limit = &intel_limits_i8xx_dvo;
490 else
491 limit = &intel_limits_i8xx_dac;
492 }
493 return limit;
494 }
495
496 /* m1 is reserved as 0 in Pineview, n is a ring counter */
497 static void pineview_clock(int refclk, intel_clock_t *clock)
498 {
499 clock->m = clock->m2 + 2;
500 clock->p = clock->p1 * clock->p2;
501 if (WARN_ON(clock->n == 0 || clock->p == 0))
502 return;
503 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
504 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
505 }
506
507 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
508 {
509 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
510 }
511
512 static void i9xx_clock(int refclk, intel_clock_t *clock)
513 {
514 clock->m = i9xx_dpll_compute_m(clock);
515 clock->p = clock->p1 * clock->p2;
516 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
517 return;
518 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
519 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
520 }
521
522 static void chv_clock(int refclk, intel_clock_t *clock)
523 {
524 clock->m = clock->m1 * clock->m2;
525 clock->p = clock->p1 * clock->p2;
526 if (WARN_ON(clock->n == 0 || clock->p == 0))
527 return;
528 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
529 clock->n << 22);
530 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
531 }
532
533 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
534 /**
535 * Returns whether the given set of divisors are valid for a given refclk with
536 * the given connectors.
537 */
538
539 static bool intel_PLL_is_valid(struct drm_device *dev,
540 const intel_limit_t *limit,
541 const intel_clock_t *clock)
542 {
543 if (clock->n < limit->n.min || limit->n.max < clock->n)
544 INTELPllInvalid("n out of range\n");
545 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
546 INTELPllInvalid("p1 out of range\n");
547 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
548 INTELPllInvalid("m2 out of range\n");
549 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
550 INTELPllInvalid("m1 out of range\n");
551
552 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
553 if (clock->m1 <= clock->m2)
554 INTELPllInvalid("m1 <= m2\n");
555
556 if (!IS_VALLEYVIEW(dev)) {
557 if (clock->p < limit->p.min || limit->p.max < clock->p)
558 INTELPllInvalid("p out of range\n");
559 if (clock->m < limit->m.min || limit->m.max < clock->m)
560 INTELPllInvalid("m out of range\n");
561 }
562
563 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
564 INTELPllInvalid("vco out of range\n");
565 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
566 * connector, etc., rather than just a single range.
567 */
568 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
569 INTELPllInvalid("dot out of range\n");
570
571 return true;
572 }
573
574 static bool
575 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
576 int target, int refclk, intel_clock_t *match_clock,
577 intel_clock_t *best_clock)
578 {
579 struct drm_device *dev = crtc->dev;
580 intel_clock_t clock;
581 int err = target;
582
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
584 /*
585 * For LVDS just rely on its current settings for dual-channel.
586 * We haven't figured out how to reliably set up different
587 * single/dual channel state, if we even can.
588 */
589 if (intel_is_dual_link_lvds(dev))
590 clock.p2 = limit->p2.p2_fast;
591 else
592 clock.p2 = limit->p2.p2_slow;
593 } else {
594 if (target < limit->p2.dot_limit)
595 clock.p2 = limit->p2.p2_slow;
596 else
597 clock.p2 = limit->p2.p2_fast;
598 }
599
600 memset(best_clock, 0, sizeof(*best_clock));
601
602 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
603 clock.m1++) {
604 for (clock.m2 = limit->m2.min;
605 clock.m2 <= limit->m2.max; clock.m2++) {
606 if (clock.m2 >= clock.m1)
607 break;
608 for (clock.n = limit->n.min;
609 clock.n <= limit->n.max; clock.n++) {
610 for (clock.p1 = limit->p1.min;
611 clock.p1 <= limit->p1.max; clock.p1++) {
612 int this_err;
613
614 i9xx_clock(refclk, &clock);
615 if (!intel_PLL_is_valid(dev, limit,
616 &clock))
617 continue;
618 if (match_clock &&
619 clock.p != match_clock->p)
620 continue;
621
622 this_err = abs(clock.dot - target);
623 if (this_err < err) {
624 *best_clock = clock;
625 err = this_err;
626 }
627 }
628 }
629 }
630 }
631
632 return (err != target);
633 }
634
635 static bool
636 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
637 int target, int refclk, intel_clock_t *match_clock,
638 intel_clock_t *best_clock)
639 {
640 struct drm_device *dev = crtc->dev;
641 intel_clock_t clock;
642 int err = target;
643
644 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
645 /*
646 * For LVDS just rely on its current settings for dual-channel.
647 * We haven't figured out how to reliably set up different
648 * single/dual channel state, if we even can.
649 */
650 if (intel_is_dual_link_lvds(dev))
651 clock.p2 = limit->p2.p2_fast;
652 else
653 clock.p2 = limit->p2.p2_slow;
654 } else {
655 if (target < limit->p2.dot_limit)
656 clock.p2 = limit->p2.p2_slow;
657 else
658 clock.p2 = limit->p2.p2_fast;
659 }
660
661 memset(best_clock, 0, sizeof(*best_clock));
662
663 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
664 clock.m1++) {
665 for (clock.m2 = limit->m2.min;
666 clock.m2 <= limit->m2.max; clock.m2++) {
667 for (clock.n = limit->n.min;
668 clock.n <= limit->n.max; clock.n++) {
669 for (clock.p1 = limit->p1.min;
670 clock.p1 <= limit->p1.max; clock.p1++) {
671 int this_err;
672
673 pineview_clock(refclk, &clock);
674 if (!intel_PLL_is_valid(dev, limit,
675 &clock))
676 continue;
677 if (match_clock &&
678 clock.p != match_clock->p)
679 continue;
680
681 this_err = abs(clock.dot - target);
682 if (this_err < err) {
683 *best_clock = clock;
684 err = this_err;
685 }
686 }
687 }
688 }
689 }
690
691 return (err != target);
692 }
693
694 static bool
695 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
696 int target, int refclk, intel_clock_t *match_clock,
697 intel_clock_t *best_clock)
698 {
699 struct drm_device *dev = crtc->dev;
700 intel_clock_t clock;
701 int max_n;
702 bool found;
703 /* approximately equals target * 0.00585 */
704 int err_most = (target >> 8) + (target >> 9);
705 found = false;
706
707 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
708 if (intel_is_dual_link_lvds(dev))
709 clock.p2 = limit->p2.p2_fast;
710 else
711 clock.p2 = limit->p2.p2_slow;
712 } else {
713 if (target < limit->p2.dot_limit)
714 clock.p2 = limit->p2.p2_slow;
715 else
716 clock.p2 = limit->p2.p2_fast;
717 }
718
719 memset(best_clock, 0, sizeof(*best_clock));
720 max_n = limit->n.max;
721 /* based on hardware requirement, prefer smaller n to precision */
722 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
723 /* based on hardware requirement, prefere larger m1,m2 */
724 for (clock.m1 = limit->m1.max;
725 clock.m1 >= limit->m1.min; clock.m1--) {
726 for (clock.m2 = limit->m2.max;
727 clock.m2 >= limit->m2.min; clock.m2--) {
728 for (clock.p1 = limit->p1.max;
729 clock.p1 >= limit->p1.min; clock.p1--) {
730 int this_err;
731
732 i9xx_clock(refclk, &clock);
733 if (!intel_PLL_is_valid(dev, limit,
734 &clock))
735 continue;
736
737 this_err = abs(clock.dot - target);
738 if (this_err < err_most) {
739 *best_clock = clock;
740 err_most = this_err;
741 max_n = clock.n;
742 found = true;
743 }
744 }
745 }
746 }
747 }
748 return found;
749 }
750
751 static bool
752 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
753 int target, int refclk, intel_clock_t *match_clock,
754 intel_clock_t *best_clock)
755 {
756 struct drm_device *dev = crtc->dev;
757 intel_clock_t clock;
758 unsigned int bestppm = 1000000;
759 /* min update 19.2 MHz */
760 int max_n = min(limit->n.max, refclk / 19200);
761 bool found = false;
762
763 target *= 5; /* fast clock */
764
765 memset(best_clock, 0, sizeof(*best_clock));
766
767 /* based on hardware requirement, prefer smaller n to precision */
768 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
769 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
770 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
771 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
772 clock.p = clock.p1 * clock.p2;
773 /* based on hardware requirement, prefer bigger m1,m2 values */
774 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
775 unsigned int ppm, diff;
776
777 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
778 refclk * clock.m1);
779
780 vlv_clock(refclk, &clock);
781
782 if (!intel_PLL_is_valid(dev, limit,
783 &clock))
784 continue;
785
786 diff = abs(clock.dot - target);
787 ppm = div_u64(1000000ULL * diff, target);
788
789 if (ppm < 100 && clock.p > best_clock->p) {
790 bestppm = 0;
791 *best_clock = clock;
792 found = true;
793 }
794
795 if (bestppm >= 10 && ppm < bestppm - 10) {
796 bestppm = ppm;
797 *best_clock = clock;
798 found = true;
799 }
800 }
801 }
802 }
803 }
804
805 return found;
806 }
807
808 static bool
809 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
812 {
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
815 uint64_t m2;
816 int found = false;
817
818 memset(best_clock, 0, sizeof(*best_clock));
819
820 /*
821 * Based on hardware doc, the n always set to 1, and m1 always
822 * set to 2. If requires to support 200Mhz refclk, we need to
823 * revisit this because n may not 1 anymore.
824 */
825 clock.n = 1, clock.m1 = 2;
826 target *= 5; /* fast clock */
827
828 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
829 for (clock.p2 = limit->p2.p2_fast;
830 clock.p2 >= limit->p2.p2_slow;
831 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
832
833 clock.p = clock.p1 * clock.p2;
834
835 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
836 clock.n) << 22, refclk * clock.m1);
837
838 if (m2 > INT_MAX/clock.m1)
839 continue;
840
841 clock.m2 = m2;
842
843 chv_clock(refclk, &clock);
844
845 if (!intel_PLL_is_valid(dev, limit, &clock))
846 continue;
847
848 /* based on hardware requirement, prefer bigger p
849 */
850 if (clock.p > best_clock->p) {
851 *best_clock = clock;
852 found = true;
853 }
854 }
855 }
856
857 return found;
858 }
859
860 bool intel_crtc_active(struct drm_crtc *crtc)
861 {
862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
863
864 /* Be paranoid as we can arrive here with only partial
865 * state retrieved from the hardware during setup.
866 *
867 * We can ditch the adjusted_mode.crtc_clock check as soon
868 * as Haswell has gained clock readout/fastboot support.
869 *
870 * We can ditch the crtc->primary->fb check as soon as we can
871 * properly reconstruct framebuffers.
872 */
873 return intel_crtc->active && crtc->primary->fb &&
874 intel_crtc->config.adjusted_mode.crtc_clock;
875 }
876
877 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
878 enum pipe pipe)
879 {
880 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
882
883 return intel_crtc->config.cpu_transcoder;
884 }
885
886 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
887 {
888 struct drm_i915_private *dev_priv = dev->dev_private;
889 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
890
891 frame = I915_READ(frame_reg);
892
893 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
894 WARN(1, "vblank wait timed out\n");
895 }
896
897 /**
898 * intel_wait_for_vblank - wait for vblank on a given pipe
899 * @dev: drm device
900 * @pipe: pipe to wait for
901 *
902 * Wait for vblank to occur on a given pipe. Needed for various bits of
903 * mode setting code.
904 */
905 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
906 {
907 struct drm_i915_private *dev_priv = dev->dev_private;
908 int pipestat_reg = PIPESTAT(pipe);
909
910 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
911 g4x_wait_for_vblank(dev, pipe);
912 return;
913 }
914
915 /* Clear existing vblank status. Note this will clear any other
916 * sticky status fields as well.
917 *
918 * This races with i915_driver_irq_handler() with the result
919 * that either function could miss a vblank event. Here it is not
920 * fatal, as we will either wait upon the next vblank interrupt or
921 * timeout. Generally speaking intel_wait_for_vblank() is only
922 * called during modeset at which time the GPU should be idle and
923 * should *not* be performing page flips and thus not waiting on
924 * vblanks...
925 * Currently, the result of us stealing a vblank from the irq
926 * handler is that a single frame will be skipped during swapbuffers.
927 */
928 I915_WRITE(pipestat_reg,
929 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
930
931 /* Wait for vblank interrupt bit to set */
932 if (wait_for(I915_READ(pipestat_reg) &
933 PIPE_VBLANK_INTERRUPT_STATUS,
934 50))
935 DRM_DEBUG_KMS("vblank wait timed out\n");
936 }
937
938 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
939 {
940 struct drm_i915_private *dev_priv = dev->dev_private;
941 u32 reg = PIPEDSL(pipe);
942 u32 line1, line2;
943 u32 line_mask;
944
945 if (IS_GEN2(dev))
946 line_mask = DSL_LINEMASK_GEN2;
947 else
948 line_mask = DSL_LINEMASK_GEN3;
949
950 line1 = I915_READ(reg) & line_mask;
951 mdelay(5);
952 line2 = I915_READ(reg) & line_mask;
953
954 return line1 == line2;
955 }
956
957 /*
958 * intel_wait_for_pipe_off - wait for pipe to turn off
959 * @dev: drm device
960 * @pipe: pipe to wait for
961 *
962 * After disabling a pipe, we can't wait for vblank in the usual way,
963 * spinning on the vblank interrupt status bit, since we won't actually
964 * see an interrupt when the pipe is disabled.
965 *
966 * On Gen4 and above:
967 * wait for the pipe register state bit to turn off
968 *
969 * Otherwise:
970 * wait for the display line value to settle (it usually
971 * ends up stopping at the start of the next frame).
972 *
973 */
974 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
975 {
976 struct drm_i915_private *dev_priv = dev->dev_private;
977 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
978 pipe);
979
980 if (INTEL_INFO(dev)->gen >= 4) {
981 int reg = PIPECONF(cpu_transcoder);
982
983 /* Wait for the Pipe State to go off */
984 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
985 100))
986 WARN(1, "pipe_off wait timed out\n");
987 } else {
988 /* Wait for the display line to settle */
989 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
990 WARN(1, "pipe_off wait timed out\n");
991 }
992 }
993
994 /*
995 * ibx_digital_port_connected - is the specified port connected?
996 * @dev_priv: i915 private structure
997 * @port: the port to test
998 *
999 * Returns true if @port is connected, false otherwise.
1000 */
1001 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1002 struct intel_digital_port *port)
1003 {
1004 u32 bit;
1005
1006 if (HAS_PCH_IBX(dev_priv->dev)) {
1007 switch (port->port) {
1008 case PORT_B:
1009 bit = SDE_PORTB_HOTPLUG;
1010 break;
1011 case PORT_C:
1012 bit = SDE_PORTC_HOTPLUG;
1013 break;
1014 case PORT_D:
1015 bit = SDE_PORTD_HOTPLUG;
1016 break;
1017 default:
1018 return true;
1019 }
1020 } else {
1021 switch (port->port) {
1022 case PORT_B:
1023 bit = SDE_PORTB_HOTPLUG_CPT;
1024 break;
1025 case PORT_C:
1026 bit = SDE_PORTC_HOTPLUG_CPT;
1027 break;
1028 case PORT_D:
1029 bit = SDE_PORTD_HOTPLUG_CPT;
1030 break;
1031 default:
1032 return true;
1033 }
1034 }
1035
1036 return I915_READ(SDEISR) & bit;
1037 }
1038
1039 static const char *state_string(bool enabled)
1040 {
1041 return enabled ? "on" : "off";
1042 }
1043
1044 /* Only for pre-ILK configs */
1045 void assert_pll(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, bool state)
1047 {
1048 int reg;
1049 u32 val;
1050 bool cur_state;
1051
1052 reg = DPLL(pipe);
1053 val = I915_READ(reg);
1054 cur_state = !!(val & DPLL_VCO_ENABLE);
1055 WARN(cur_state != state,
1056 "PLL state assertion failure (expected %s, current %s)\n",
1057 state_string(state), state_string(cur_state));
1058 }
1059
1060 /* XXX: the dsi pll is shared between MIPI DSI ports */
1061 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1062 {
1063 u32 val;
1064 bool cur_state;
1065
1066 mutex_lock(&dev_priv->dpio_lock);
1067 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1068 mutex_unlock(&dev_priv->dpio_lock);
1069
1070 cur_state = val & DSI_PLL_VCO_EN;
1071 WARN(cur_state != state,
1072 "DSI PLL state assertion failure (expected %s, current %s)\n",
1073 state_string(state), state_string(cur_state));
1074 }
1075 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1076 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1077
1078 struct intel_shared_dpll *
1079 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1080 {
1081 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1082
1083 if (crtc->config.shared_dpll < 0)
1084 return NULL;
1085
1086 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1087 }
1088
1089 /* For ILK+ */
1090 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1091 struct intel_shared_dpll *pll,
1092 bool state)
1093 {
1094 bool cur_state;
1095 struct intel_dpll_hw_state hw_state;
1096
1097 if (HAS_PCH_LPT(dev_priv->dev)) {
1098 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1099 return;
1100 }
1101
1102 if (WARN (!pll,
1103 "asserting DPLL %s with no DPLL\n", state_string(state)))
1104 return;
1105
1106 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1107 WARN(cur_state != state,
1108 "%s assertion failure (expected %s, current %s)\n",
1109 pll->name, state_string(state), state_string(cur_state));
1110 }
1111
1112 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1113 enum pipe pipe, bool state)
1114 {
1115 int reg;
1116 u32 val;
1117 bool cur_state;
1118 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1119 pipe);
1120
1121 if (HAS_DDI(dev_priv->dev)) {
1122 /* DDI does not have a specific FDI_TX register */
1123 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1124 val = I915_READ(reg);
1125 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1126 } else {
1127 reg = FDI_TX_CTL(pipe);
1128 val = I915_READ(reg);
1129 cur_state = !!(val & FDI_TX_ENABLE);
1130 }
1131 WARN(cur_state != state,
1132 "FDI TX state assertion failure (expected %s, current %s)\n",
1133 state_string(state), state_string(cur_state));
1134 }
1135 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1136 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1137
1138 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1139 enum pipe pipe, bool state)
1140 {
1141 int reg;
1142 u32 val;
1143 bool cur_state;
1144
1145 reg = FDI_RX_CTL(pipe);
1146 val = I915_READ(reg);
1147 cur_state = !!(val & FDI_RX_ENABLE);
1148 WARN(cur_state != state,
1149 "FDI RX state assertion failure (expected %s, current %s)\n",
1150 state_string(state), state_string(cur_state));
1151 }
1152 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1153 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1154
1155 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1156 enum pipe pipe)
1157 {
1158 int reg;
1159 u32 val;
1160
1161 /* ILK FDI PLL is always enabled */
1162 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1163 return;
1164
1165 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1166 if (HAS_DDI(dev_priv->dev))
1167 return;
1168
1169 reg = FDI_TX_CTL(pipe);
1170 val = I915_READ(reg);
1171 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1172 }
1173
1174 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1175 enum pipe pipe, bool state)
1176 {
1177 int reg;
1178 u32 val;
1179 bool cur_state;
1180
1181 reg = FDI_RX_CTL(pipe);
1182 val = I915_READ(reg);
1183 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1184 WARN(cur_state != state,
1185 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1186 state_string(state), state_string(cur_state));
1187 }
1188
1189 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1190 enum pipe pipe)
1191 {
1192 int pp_reg, lvds_reg;
1193 u32 val;
1194 enum pipe panel_pipe = PIPE_A;
1195 bool locked = true;
1196
1197 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1198 pp_reg = PCH_PP_CONTROL;
1199 lvds_reg = PCH_LVDS;
1200 } else {
1201 pp_reg = PP_CONTROL;
1202 lvds_reg = LVDS;
1203 }
1204
1205 val = I915_READ(pp_reg);
1206 if (!(val & PANEL_POWER_ON) ||
1207 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1208 locked = false;
1209
1210 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1211 panel_pipe = PIPE_B;
1212
1213 WARN(panel_pipe == pipe && locked,
1214 "panel assertion failure, pipe %c regs locked\n",
1215 pipe_name(pipe));
1216 }
1217
1218 static void assert_cursor(struct drm_i915_private *dev_priv,
1219 enum pipe pipe, bool state)
1220 {
1221 struct drm_device *dev = dev_priv->dev;
1222 bool cur_state;
1223
1224 if (IS_845G(dev) || IS_I865G(dev))
1225 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1226 else
1227 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1228
1229 WARN(cur_state != state,
1230 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1231 pipe_name(pipe), state_string(state), state_string(cur_state));
1232 }
1233 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1234 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1235
1236 void assert_pipe(struct drm_i915_private *dev_priv,
1237 enum pipe pipe, bool state)
1238 {
1239 int reg;
1240 u32 val;
1241 bool cur_state;
1242 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1243 pipe);
1244
1245 /* if we need the pipe A quirk it must be always on */
1246 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1247 state = true;
1248
1249 if (!intel_display_power_enabled(dev_priv,
1250 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1251 cur_state = false;
1252 } else {
1253 reg = PIPECONF(cpu_transcoder);
1254 val = I915_READ(reg);
1255 cur_state = !!(val & PIPECONF_ENABLE);
1256 }
1257
1258 WARN(cur_state != state,
1259 "pipe %c assertion failure (expected %s, current %s)\n",
1260 pipe_name(pipe), state_string(state), state_string(cur_state));
1261 }
1262
1263 static void assert_plane(struct drm_i915_private *dev_priv,
1264 enum plane plane, bool state)
1265 {
1266 int reg;
1267 u32 val;
1268 bool cur_state;
1269
1270 reg = DSPCNTR(plane);
1271 val = I915_READ(reg);
1272 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1273 WARN(cur_state != state,
1274 "plane %c assertion failure (expected %s, current %s)\n",
1275 plane_name(plane), state_string(state), state_string(cur_state));
1276 }
1277
1278 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1279 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1280
1281 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1282 enum pipe pipe)
1283 {
1284 struct drm_device *dev = dev_priv->dev;
1285 int reg, i;
1286 u32 val;
1287 int cur_pipe;
1288
1289 /* Primary planes are fixed to pipes on gen4+ */
1290 if (INTEL_INFO(dev)->gen >= 4) {
1291 reg = DSPCNTR(pipe);
1292 val = I915_READ(reg);
1293 WARN(val & DISPLAY_PLANE_ENABLE,
1294 "plane %c assertion failure, should be disabled but not\n",
1295 plane_name(pipe));
1296 return;
1297 }
1298
1299 /* Need to check both planes against the pipe */
1300 for_each_pipe(i) {
1301 reg = DSPCNTR(i);
1302 val = I915_READ(reg);
1303 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1304 DISPPLANE_SEL_PIPE_SHIFT;
1305 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1306 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1307 plane_name(i), pipe_name(pipe));
1308 }
1309 }
1310
1311 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1312 enum pipe pipe)
1313 {
1314 struct drm_device *dev = dev_priv->dev;
1315 int reg, sprite;
1316 u32 val;
1317
1318 if (IS_VALLEYVIEW(dev)) {
1319 for_each_sprite(pipe, sprite) {
1320 reg = SPCNTR(pipe, sprite);
1321 val = I915_READ(reg);
1322 WARN(val & SP_ENABLE,
1323 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1324 sprite_name(pipe, sprite), pipe_name(pipe));
1325 }
1326 } else if (INTEL_INFO(dev)->gen >= 7) {
1327 reg = SPRCTL(pipe);
1328 val = I915_READ(reg);
1329 WARN(val & SPRITE_ENABLE,
1330 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1331 plane_name(pipe), pipe_name(pipe));
1332 } else if (INTEL_INFO(dev)->gen >= 5) {
1333 reg = DVSCNTR(pipe);
1334 val = I915_READ(reg);
1335 WARN(val & DVS_ENABLE,
1336 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1337 plane_name(pipe), pipe_name(pipe));
1338 }
1339 }
1340
1341 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1342 {
1343 u32 val;
1344 bool enabled;
1345
1346 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1347
1348 val = I915_READ(PCH_DREF_CONTROL);
1349 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1350 DREF_SUPERSPREAD_SOURCE_MASK));
1351 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1352 }
1353
1354 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1355 enum pipe pipe)
1356 {
1357 int reg;
1358 u32 val;
1359 bool enabled;
1360
1361 reg = PCH_TRANSCONF(pipe);
1362 val = I915_READ(reg);
1363 enabled = !!(val & TRANS_ENABLE);
1364 WARN(enabled,
1365 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1366 pipe_name(pipe));
1367 }
1368
1369 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1370 enum pipe pipe, u32 port_sel, u32 val)
1371 {
1372 if ((val & DP_PORT_EN) == 0)
1373 return false;
1374
1375 if (HAS_PCH_CPT(dev_priv->dev)) {
1376 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1377 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1378 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1379 return false;
1380 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1381 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1382 return false;
1383 } else {
1384 if ((val & DP_PIPE_MASK) != (pipe << 30))
1385 return false;
1386 }
1387 return true;
1388 }
1389
1390 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1391 enum pipe pipe, u32 val)
1392 {
1393 if ((val & SDVO_ENABLE) == 0)
1394 return false;
1395
1396 if (HAS_PCH_CPT(dev_priv->dev)) {
1397 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1398 return false;
1399 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1400 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1401 return false;
1402 } else {
1403 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1404 return false;
1405 }
1406 return true;
1407 }
1408
1409 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1410 enum pipe pipe, u32 val)
1411 {
1412 if ((val & LVDS_PORT_EN) == 0)
1413 return false;
1414
1415 if (HAS_PCH_CPT(dev_priv->dev)) {
1416 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1417 return false;
1418 } else {
1419 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1420 return false;
1421 }
1422 return true;
1423 }
1424
1425 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1426 enum pipe pipe, u32 val)
1427 {
1428 if ((val & ADPA_DAC_ENABLE) == 0)
1429 return false;
1430 if (HAS_PCH_CPT(dev_priv->dev)) {
1431 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1432 return false;
1433 } else {
1434 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1435 return false;
1436 }
1437 return true;
1438 }
1439
1440 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1441 enum pipe pipe, int reg, u32 port_sel)
1442 {
1443 u32 val = I915_READ(reg);
1444 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1445 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1446 reg, pipe_name(pipe));
1447
1448 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1449 && (val & DP_PIPEB_SELECT),
1450 "IBX PCH dp port still using transcoder B\n");
1451 }
1452
1453 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1454 enum pipe pipe, int reg)
1455 {
1456 u32 val = I915_READ(reg);
1457 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1458 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1459 reg, pipe_name(pipe));
1460
1461 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1462 && (val & SDVO_PIPE_B_SELECT),
1463 "IBX PCH hdmi port still using transcoder B\n");
1464 }
1465
1466 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1467 enum pipe pipe)
1468 {
1469 int reg;
1470 u32 val;
1471
1472 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1473 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1474 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1475
1476 reg = PCH_ADPA;
1477 val = I915_READ(reg);
1478 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1479 "PCH VGA enabled on transcoder %c, should be disabled\n",
1480 pipe_name(pipe));
1481
1482 reg = PCH_LVDS;
1483 val = I915_READ(reg);
1484 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1485 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1486 pipe_name(pipe));
1487
1488 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1489 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1490 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1491 }
1492
1493 static void intel_init_dpio(struct drm_device *dev)
1494 {
1495 struct drm_i915_private *dev_priv = dev->dev_private;
1496
1497 if (!IS_VALLEYVIEW(dev))
1498 return;
1499
1500 /*
1501 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1502 * CHV x1 PHY (DP/HDMI D)
1503 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1504 */
1505 if (IS_CHERRYVIEW(dev)) {
1506 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1507 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1508 } else {
1509 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1510 }
1511 }
1512
1513 static void intel_reset_dpio(struct drm_device *dev)
1514 {
1515 struct drm_i915_private *dev_priv = dev->dev_private;
1516
1517 if (IS_CHERRYVIEW(dev)) {
1518 enum dpio_phy phy;
1519 u32 val;
1520
1521 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1522 /* Poll for phypwrgood signal */
1523 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1524 PHY_POWERGOOD(phy), 1))
1525 DRM_ERROR("Display PHY %d is not power up\n", phy);
1526
1527 /*
1528 * Deassert common lane reset for PHY.
1529 *
1530 * This should only be done on init and resume from S3
1531 * with both PLLs disabled, or we risk losing DPIO and
1532 * PLL synchronization.
1533 */
1534 val = I915_READ(DISPLAY_PHY_CONTROL);
1535 I915_WRITE(DISPLAY_PHY_CONTROL,
1536 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1537 }
1538 }
1539 }
1540
1541 static void vlv_enable_pll(struct intel_crtc *crtc)
1542 {
1543 struct drm_device *dev = crtc->base.dev;
1544 struct drm_i915_private *dev_priv = dev->dev_private;
1545 int reg = DPLL(crtc->pipe);
1546 u32 dpll = crtc->config.dpll_hw_state.dpll;
1547
1548 assert_pipe_disabled(dev_priv, crtc->pipe);
1549
1550 /* No really, not for ILK+ */
1551 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1552
1553 /* PLL is protected by panel, make sure we can write it */
1554 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1555 assert_panel_unlocked(dev_priv, crtc->pipe);
1556
1557 I915_WRITE(reg, dpll);
1558 POSTING_READ(reg);
1559 udelay(150);
1560
1561 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1562 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1563
1564 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1565 POSTING_READ(DPLL_MD(crtc->pipe));
1566
1567 /* We do this three times for luck */
1568 I915_WRITE(reg, dpll);
1569 POSTING_READ(reg);
1570 udelay(150); /* wait for warmup */
1571 I915_WRITE(reg, dpll);
1572 POSTING_READ(reg);
1573 udelay(150); /* wait for warmup */
1574 I915_WRITE(reg, dpll);
1575 POSTING_READ(reg);
1576 udelay(150); /* wait for warmup */
1577 }
1578
1579 static void chv_enable_pll(struct intel_crtc *crtc)
1580 {
1581 struct drm_device *dev = crtc->base.dev;
1582 struct drm_i915_private *dev_priv = dev->dev_private;
1583 int pipe = crtc->pipe;
1584 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1585 u32 tmp;
1586
1587 assert_pipe_disabled(dev_priv, crtc->pipe);
1588
1589 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1590
1591 mutex_lock(&dev_priv->dpio_lock);
1592
1593 /* Enable back the 10bit clock to display controller */
1594 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1595 tmp |= DPIO_DCLKP_EN;
1596 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1597
1598 /*
1599 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1600 */
1601 udelay(1);
1602
1603 /* Enable PLL */
1604 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1605
1606 /* Check PLL is locked */
1607 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1608 DRM_ERROR("PLL %d failed to lock\n", pipe);
1609
1610 /* not sure when this should be written */
1611 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1612 POSTING_READ(DPLL_MD(pipe));
1613
1614 mutex_unlock(&dev_priv->dpio_lock);
1615 }
1616
1617 static void i9xx_enable_pll(struct intel_crtc *crtc)
1618 {
1619 struct drm_device *dev = crtc->base.dev;
1620 struct drm_i915_private *dev_priv = dev->dev_private;
1621 int reg = DPLL(crtc->pipe);
1622 u32 dpll = crtc->config.dpll_hw_state.dpll;
1623
1624 assert_pipe_disabled(dev_priv, crtc->pipe);
1625
1626 /* No really, not for ILK+ */
1627 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1628
1629 /* PLL is protected by panel, make sure we can write it */
1630 if (IS_MOBILE(dev) && !IS_I830(dev))
1631 assert_panel_unlocked(dev_priv, crtc->pipe);
1632
1633 I915_WRITE(reg, dpll);
1634
1635 /* Wait for the clocks to stabilize. */
1636 POSTING_READ(reg);
1637 udelay(150);
1638
1639 if (INTEL_INFO(dev)->gen >= 4) {
1640 I915_WRITE(DPLL_MD(crtc->pipe),
1641 crtc->config.dpll_hw_state.dpll_md);
1642 } else {
1643 /* The pixel multiplier can only be updated once the
1644 * DPLL is enabled and the clocks are stable.
1645 *
1646 * So write it again.
1647 */
1648 I915_WRITE(reg, dpll);
1649 }
1650
1651 /* We do this three times for luck */
1652 I915_WRITE(reg, dpll);
1653 POSTING_READ(reg);
1654 udelay(150); /* wait for warmup */
1655 I915_WRITE(reg, dpll);
1656 POSTING_READ(reg);
1657 udelay(150); /* wait for warmup */
1658 I915_WRITE(reg, dpll);
1659 POSTING_READ(reg);
1660 udelay(150); /* wait for warmup */
1661 }
1662
1663 /**
1664 * i9xx_disable_pll - disable a PLL
1665 * @dev_priv: i915 private structure
1666 * @pipe: pipe PLL to disable
1667 *
1668 * Disable the PLL for @pipe, making sure the pipe is off first.
1669 *
1670 * Note! This is for pre-ILK only.
1671 */
1672 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1673 {
1674 /* Don't disable pipe A or pipe A PLLs if needed */
1675 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1676 return;
1677
1678 /* Make sure the pipe isn't still relying on us */
1679 assert_pipe_disabled(dev_priv, pipe);
1680
1681 I915_WRITE(DPLL(pipe), 0);
1682 POSTING_READ(DPLL(pipe));
1683 }
1684
1685 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1686 {
1687 u32 val = 0;
1688
1689 /* Make sure the pipe isn't still relying on us */
1690 assert_pipe_disabled(dev_priv, pipe);
1691
1692 /*
1693 * Leave integrated clock source and reference clock enabled for pipe B.
1694 * The latter is needed for VGA hotplug / manual detection.
1695 */
1696 if (pipe == PIPE_B)
1697 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1698 I915_WRITE(DPLL(pipe), val);
1699 POSTING_READ(DPLL(pipe));
1700
1701 }
1702
1703 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1704 {
1705 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1706 u32 val;
1707
1708 /* Make sure the pipe isn't still relying on us */
1709 assert_pipe_disabled(dev_priv, pipe);
1710
1711 /* Set PLL en = 0 */
1712 val = DPLL_SSC_REF_CLOCK_CHV;
1713 if (pipe != PIPE_A)
1714 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1715 I915_WRITE(DPLL(pipe), val);
1716 POSTING_READ(DPLL(pipe));
1717
1718 mutex_lock(&dev_priv->dpio_lock);
1719
1720 /* Disable 10bit clock to display controller */
1721 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1722 val &= ~DPIO_DCLKP_EN;
1723 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1724
1725 /* disable left/right clock distribution */
1726 if (pipe != PIPE_B) {
1727 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1728 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1729 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1730 } else {
1731 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1732 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1733 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1734 }
1735
1736 mutex_unlock(&dev_priv->dpio_lock);
1737 }
1738
1739 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1740 struct intel_digital_port *dport)
1741 {
1742 u32 port_mask;
1743 int dpll_reg;
1744
1745 switch (dport->port) {
1746 case PORT_B:
1747 port_mask = DPLL_PORTB_READY_MASK;
1748 dpll_reg = DPLL(0);
1749 break;
1750 case PORT_C:
1751 port_mask = DPLL_PORTC_READY_MASK;
1752 dpll_reg = DPLL(0);
1753 break;
1754 case PORT_D:
1755 port_mask = DPLL_PORTD_READY_MASK;
1756 dpll_reg = DPIO_PHY_STATUS;
1757 break;
1758 default:
1759 BUG();
1760 }
1761
1762 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1763 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1764 port_name(dport->port), I915_READ(dpll_reg));
1765 }
1766
1767 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1768 {
1769 struct drm_device *dev = crtc->base.dev;
1770 struct drm_i915_private *dev_priv = dev->dev_private;
1771 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1772
1773 if (WARN_ON(pll == NULL))
1774 return;
1775
1776 WARN_ON(!pll->refcount);
1777 if (pll->active == 0) {
1778 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1779 WARN_ON(pll->on);
1780 assert_shared_dpll_disabled(dev_priv, pll);
1781
1782 pll->mode_set(dev_priv, pll);
1783 }
1784 }
1785
1786 /**
1787 * intel_enable_shared_dpll - enable PCH PLL
1788 * @dev_priv: i915 private structure
1789 * @pipe: pipe PLL to enable
1790 *
1791 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1792 * drives the transcoder clock.
1793 */
1794 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1795 {
1796 struct drm_device *dev = crtc->base.dev;
1797 struct drm_i915_private *dev_priv = dev->dev_private;
1798 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1799
1800 if (WARN_ON(pll == NULL))
1801 return;
1802
1803 if (WARN_ON(pll->refcount == 0))
1804 return;
1805
1806 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1807 pll->name, pll->active, pll->on,
1808 crtc->base.base.id);
1809
1810 if (pll->active++) {
1811 WARN_ON(!pll->on);
1812 assert_shared_dpll_enabled(dev_priv, pll);
1813 return;
1814 }
1815 WARN_ON(pll->on);
1816
1817 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1818 pll->enable(dev_priv, pll);
1819 pll->on = true;
1820 }
1821
1822 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1823 {
1824 struct drm_device *dev = crtc->base.dev;
1825 struct drm_i915_private *dev_priv = dev->dev_private;
1826 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1827
1828 /* PCH only available on ILK+ */
1829 BUG_ON(INTEL_INFO(dev)->gen < 5);
1830 if (WARN_ON(pll == NULL))
1831 return;
1832
1833 if (WARN_ON(pll->refcount == 0))
1834 return;
1835
1836 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1837 pll->name, pll->active, pll->on,
1838 crtc->base.base.id);
1839
1840 if (WARN_ON(pll->active == 0)) {
1841 assert_shared_dpll_disabled(dev_priv, pll);
1842 return;
1843 }
1844
1845 assert_shared_dpll_enabled(dev_priv, pll);
1846 WARN_ON(!pll->on);
1847 if (--pll->active)
1848 return;
1849
1850 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1851 pll->disable(dev_priv, pll);
1852 pll->on = false;
1853 }
1854
1855 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1856 enum pipe pipe)
1857 {
1858 struct drm_device *dev = dev_priv->dev;
1859 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1860 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1861 uint32_t reg, val, pipeconf_val;
1862
1863 /* PCH only available on ILK+ */
1864 BUG_ON(INTEL_INFO(dev)->gen < 5);
1865
1866 /* Make sure PCH DPLL is enabled */
1867 assert_shared_dpll_enabled(dev_priv,
1868 intel_crtc_to_shared_dpll(intel_crtc));
1869
1870 /* FDI must be feeding us bits for PCH ports */
1871 assert_fdi_tx_enabled(dev_priv, pipe);
1872 assert_fdi_rx_enabled(dev_priv, pipe);
1873
1874 if (HAS_PCH_CPT(dev)) {
1875 /* Workaround: Set the timing override bit before enabling the
1876 * pch transcoder. */
1877 reg = TRANS_CHICKEN2(pipe);
1878 val = I915_READ(reg);
1879 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1880 I915_WRITE(reg, val);
1881 }
1882
1883 reg = PCH_TRANSCONF(pipe);
1884 val = I915_READ(reg);
1885 pipeconf_val = I915_READ(PIPECONF(pipe));
1886
1887 if (HAS_PCH_IBX(dev_priv->dev)) {
1888 /*
1889 * make the BPC in transcoder be consistent with
1890 * that in pipeconf reg.
1891 */
1892 val &= ~PIPECONF_BPC_MASK;
1893 val |= pipeconf_val & PIPECONF_BPC_MASK;
1894 }
1895
1896 val &= ~TRANS_INTERLACE_MASK;
1897 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1898 if (HAS_PCH_IBX(dev_priv->dev) &&
1899 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1900 val |= TRANS_LEGACY_INTERLACED_ILK;
1901 else
1902 val |= TRANS_INTERLACED;
1903 else
1904 val |= TRANS_PROGRESSIVE;
1905
1906 I915_WRITE(reg, val | TRANS_ENABLE);
1907 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1908 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1909 }
1910
1911 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1912 enum transcoder cpu_transcoder)
1913 {
1914 u32 val, pipeconf_val;
1915
1916 /* PCH only available on ILK+ */
1917 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1918
1919 /* FDI must be feeding us bits for PCH ports */
1920 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1921 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1922
1923 /* Workaround: set timing override bit. */
1924 val = I915_READ(_TRANSA_CHICKEN2);
1925 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1926 I915_WRITE(_TRANSA_CHICKEN2, val);
1927
1928 val = TRANS_ENABLE;
1929 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1930
1931 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1932 PIPECONF_INTERLACED_ILK)
1933 val |= TRANS_INTERLACED;
1934 else
1935 val |= TRANS_PROGRESSIVE;
1936
1937 I915_WRITE(LPT_TRANSCONF, val);
1938 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1939 DRM_ERROR("Failed to enable PCH transcoder\n");
1940 }
1941
1942 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1943 enum pipe pipe)
1944 {
1945 struct drm_device *dev = dev_priv->dev;
1946 uint32_t reg, val;
1947
1948 /* FDI relies on the transcoder */
1949 assert_fdi_tx_disabled(dev_priv, pipe);
1950 assert_fdi_rx_disabled(dev_priv, pipe);
1951
1952 /* Ports must be off as well */
1953 assert_pch_ports_disabled(dev_priv, pipe);
1954
1955 reg = PCH_TRANSCONF(pipe);
1956 val = I915_READ(reg);
1957 val &= ~TRANS_ENABLE;
1958 I915_WRITE(reg, val);
1959 /* wait for PCH transcoder off, transcoder state */
1960 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1961 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1962
1963 if (!HAS_PCH_IBX(dev)) {
1964 /* Workaround: Clear the timing override chicken bit again. */
1965 reg = TRANS_CHICKEN2(pipe);
1966 val = I915_READ(reg);
1967 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1968 I915_WRITE(reg, val);
1969 }
1970 }
1971
1972 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1973 {
1974 u32 val;
1975
1976 val = I915_READ(LPT_TRANSCONF);
1977 val &= ~TRANS_ENABLE;
1978 I915_WRITE(LPT_TRANSCONF, val);
1979 /* wait for PCH transcoder off, transcoder state */
1980 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1981 DRM_ERROR("Failed to disable PCH transcoder\n");
1982
1983 /* Workaround: clear timing override bit. */
1984 val = I915_READ(_TRANSA_CHICKEN2);
1985 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1986 I915_WRITE(_TRANSA_CHICKEN2, val);
1987 }
1988
1989 /**
1990 * intel_enable_pipe - enable a pipe, asserting requirements
1991 * @crtc: crtc responsible for the pipe
1992 *
1993 * Enable @crtc's pipe, making sure that various hardware specific requirements
1994 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1995 */
1996 static void intel_enable_pipe(struct intel_crtc *crtc)
1997 {
1998 struct drm_device *dev = crtc->base.dev;
1999 struct drm_i915_private *dev_priv = dev->dev_private;
2000 enum pipe pipe = crtc->pipe;
2001 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2002 pipe);
2003 enum pipe pch_transcoder;
2004 int reg;
2005 u32 val;
2006
2007 assert_planes_disabled(dev_priv, pipe);
2008 assert_cursor_disabled(dev_priv, pipe);
2009 assert_sprites_disabled(dev_priv, pipe);
2010
2011 if (HAS_PCH_LPT(dev_priv->dev))
2012 pch_transcoder = TRANSCODER_A;
2013 else
2014 pch_transcoder = pipe;
2015
2016 /*
2017 * A pipe without a PLL won't actually be able to drive bits from
2018 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2019 * need the check.
2020 */
2021 if (!HAS_PCH_SPLIT(dev_priv->dev))
2022 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2023 assert_dsi_pll_enabled(dev_priv);
2024 else
2025 assert_pll_enabled(dev_priv, pipe);
2026 else {
2027 if (crtc->config.has_pch_encoder) {
2028 /* if driving the PCH, we need FDI enabled */
2029 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2030 assert_fdi_tx_pll_enabled(dev_priv,
2031 (enum pipe) cpu_transcoder);
2032 }
2033 /* FIXME: assert CPU port conditions for SNB+ */
2034 }
2035
2036 reg = PIPECONF(cpu_transcoder);
2037 val = I915_READ(reg);
2038 if (val & PIPECONF_ENABLE) {
2039 WARN_ON(!(pipe == PIPE_A &&
2040 dev_priv->quirks & QUIRK_PIPEA_FORCE));
2041 return;
2042 }
2043
2044 I915_WRITE(reg, val | PIPECONF_ENABLE);
2045 POSTING_READ(reg);
2046 }
2047
2048 /**
2049 * intel_disable_pipe - disable a pipe, asserting requirements
2050 * @dev_priv: i915 private structure
2051 * @pipe: pipe to disable
2052 *
2053 * Disable @pipe, making sure that various hardware specific requirements
2054 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2055 *
2056 * @pipe should be %PIPE_A or %PIPE_B.
2057 *
2058 * Will wait until the pipe has shut down before returning.
2059 */
2060 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2061 enum pipe pipe)
2062 {
2063 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2064 pipe);
2065 int reg;
2066 u32 val;
2067
2068 /*
2069 * Make sure planes won't keep trying to pump pixels to us,
2070 * or we might hang the display.
2071 */
2072 assert_planes_disabled(dev_priv, pipe);
2073 assert_cursor_disabled(dev_priv, pipe);
2074 assert_sprites_disabled(dev_priv, pipe);
2075
2076 /* Don't disable pipe A or pipe A PLLs if needed */
2077 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2078 return;
2079
2080 reg = PIPECONF(cpu_transcoder);
2081 val = I915_READ(reg);
2082 if ((val & PIPECONF_ENABLE) == 0)
2083 return;
2084
2085 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2086 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2087 }
2088
2089 /*
2090 * Plane regs are double buffered, going from enabled->disabled needs a
2091 * trigger in order to latch. The display address reg provides this.
2092 */
2093 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2094 enum plane plane)
2095 {
2096 struct drm_device *dev = dev_priv->dev;
2097 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2098
2099 I915_WRITE(reg, I915_READ(reg));
2100 POSTING_READ(reg);
2101 }
2102
2103 /**
2104 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2105 * @dev_priv: i915 private structure
2106 * @plane: plane to enable
2107 * @pipe: pipe being fed
2108 *
2109 * Enable @plane on @pipe, making sure that @pipe is running first.
2110 */
2111 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2112 enum plane plane, enum pipe pipe)
2113 {
2114 struct drm_device *dev = dev_priv->dev;
2115 struct intel_crtc *intel_crtc =
2116 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2117 int reg;
2118 u32 val;
2119
2120 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2121 assert_pipe_enabled(dev_priv, pipe);
2122
2123 if (intel_crtc->primary_enabled)
2124 return;
2125
2126 intel_crtc->primary_enabled = true;
2127
2128 reg = DSPCNTR(plane);
2129 val = I915_READ(reg);
2130 WARN_ON(val & DISPLAY_PLANE_ENABLE);
2131
2132 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2133 intel_flush_primary_plane(dev_priv, plane);
2134
2135 /*
2136 * BDW signals flip done immediately if the plane
2137 * is disabled, even if the plane enable is already
2138 * armed to occur at the next vblank :(
2139 */
2140 if (IS_BROADWELL(dev))
2141 intel_wait_for_vblank(dev, intel_crtc->pipe);
2142 }
2143
2144 /**
2145 * intel_disable_primary_hw_plane - disable the primary hardware plane
2146 * @dev_priv: i915 private structure
2147 * @plane: plane to disable
2148 * @pipe: pipe consuming the data
2149 *
2150 * Disable @plane; should be an independent operation.
2151 */
2152 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2153 enum plane plane, enum pipe pipe)
2154 {
2155 struct intel_crtc *intel_crtc =
2156 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2157 int reg;
2158 u32 val;
2159
2160 if (!intel_crtc->primary_enabled)
2161 return;
2162
2163 intel_crtc->primary_enabled = false;
2164
2165 reg = DSPCNTR(plane);
2166 val = I915_READ(reg);
2167 WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2168
2169 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2170 intel_flush_primary_plane(dev_priv, plane);
2171 }
2172
2173 static bool need_vtd_wa(struct drm_device *dev)
2174 {
2175 #ifdef CONFIG_INTEL_IOMMU
2176 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2177 return true;
2178 #endif
2179 return false;
2180 }
2181
2182 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2183 {
2184 int tile_height;
2185
2186 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2187 return ALIGN(height, tile_height);
2188 }
2189
2190 int
2191 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2192 struct drm_i915_gem_object *obj,
2193 struct intel_engine_cs *pipelined)
2194 {
2195 struct drm_i915_private *dev_priv = dev->dev_private;
2196 u32 alignment;
2197 int ret;
2198
2199 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2200
2201 switch (obj->tiling_mode) {
2202 case I915_TILING_NONE:
2203 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2204 alignment = 128 * 1024;
2205 else if (INTEL_INFO(dev)->gen >= 4)
2206 alignment = 4 * 1024;
2207 else
2208 alignment = 64 * 1024;
2209 break;
2210 case I915_TILING_X:
2211 /* pin() will align the object as required by fence */
2212 alignment = 0;
2213 break;
2214 case I915_TILING_Y:
2215 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2216 return -EINVAL;
2217 default:
2218 BUG();
2219 }
2220
2221 /* Note that the w/a also requires 64 PTE of padding following the
2222 * bo. We currently fill all unused PTE with the shadow page and so
2223 * we should always have valid PTE following the scanout preventing
2224 * the VT-d warning.
2225 */
2226 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2227 alignment = 256 * 1024;
2228
2229 dev_priv->mm.interruptible = false;
2230 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2231 if (ret)
2232 goto err_interruptible;
2233
2234 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2235 * fence, whereas 965+ only requires a fence if using
2236 * framebuffer compression. For simplicity, we always install
2237 * a fence as the cost is not that onerous.
2238 */
2239 ret = i915_gem_object_get_fence(obj);
2240 if (ret)
2241 goto err_unpin;
2242
2243 i915_gem_object_pin_fence(obj);
2244
2245 dev_priv->mm.interruptible = true;
2246 return 0;
2247
2248 err_unpin:
2249 i915_gem_object_unpin_from_display_plane(obj);
2250 err_interruptible:
2251 dev_priv->mm.interruptible = true;
2252 return ret;
2253 }
2254
2255 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2256 {
2257 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2258
2259 i915_gem_object_unpin_fence(obj);
2260 i915_gem_object_unpin_from_display_plane(obj);
2261 }
2262
2263 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2264 * is assumed to be a power-of-two. */
2265 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2266 unsigned int tiling_mode,
2267 unsigned int cpp,
2268 unsigned int pitch)
2269 {
2270 if (tiling_mode != I915_TILING_NONE) {
2271 unsigned int tile_rows, tiles;
2272
2273 tile_rows = *y / 8;
2274 *y %= 8;
2275
2276 tiles = *x / (512/cpp);
2277 *x %= 512/cpp;
2278
2279 return tile_rows * pitch * 8 + tiles * 4096;
2280 } else {
2281 unsigned int offset;
2282
2283 offset = *y * pitch + *x * cpp;
2284 *y = 0;
2285 *x = (offset & 4095) / cpp;
2286 return offset & -4096;
2287 }
2288 }
2289
2290 int intel_format_to_fourcc(int format)
2291 {
2292 switch (format) {
2293 case DISPPLANE_8BPP:
2294 return DRM_FORMAT_C8;
2295 case DISPPLANE_BGRX555:
2296 return DRM_FORMAT_XRGB1555;
2297 case DISPPLANE_BGRX565:
2298 return DRM_FORMAT_RGB565;
2299 default:
2300 case DISPPLANE_BGRX888:
2301 return DRM_FORMAT_XRGB8888;
2302 case DISPPLANE_RGBX888:
2303 return DRM_FORMAT_XBGR8888;
2304 case DISPPLANE_BGRX101010:
2305 return DRM_FORMAT_XRGB2101010;
2306 case DISPPLANE_RGBX101010:
2307 return DRM_FORMAT_XBGR2101010;
2308 }
2309 }
2310
2311 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2312 struct intel_plane_config *plane_config)
2313 {
2314 struct drm_device *dev = crtc->base.dev;
2315 struct drm_i915_gem_object *obj = NULL;
2316 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2317 u32 base = plane_config->base;
2318
2319 if (plane_config->size == 0)
2320 return false;
2321
2322 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2323 plane_config->size);
2324 if (!obj)
2325 return false;
2326
2327 if (plane_config->tiled) {
2328 obj->tiling_mode = I915_TILING_X;
2329 obj->stride = crtc->base.primary->fb->pitches[0];
2330 }
2331
2332 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2333 mode_cmd.width = crtc->base.primary->fb->width;
2334 mode_cmd.height = crtc->base.primary->fb->height;
2335 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2336
2337 mutex_lock(&dev->struct_mutex);
2338
2339 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2340 &mode_cmd, obj)) {
2341 DRM_DEBUG_KMS("intel fb init failed\n");
2342 goto out_unref_obj;
2343 }
2344
2345 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2346 mutex_unlock(&dev->struct_mutex);
2347
2348 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2349 return true;
2350
2351 out_unref_obj:
2352 drm_gem_object_unreference(&obj->base);
2353 mutex_unlock(&dev->struct_mutex);
2354 return false;
2355 }
2356
2357 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2358 struct intel_plane_config *plane_config)
2359 {
2360 struct drm_device *dev = intel_crtc->base.dev;
2361 struct drm_crtc *c;
2362 struct intel_crtc *i;
2363 struct drm_i915_gem_object *obj;
2364
2365 if (!intel_crtc->base.primary->fb)
2366 return;
2367
2368 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2369 return;
2370
2371 kfree(intel_crtc->base.primary->fb);
2372 intel_crtc->base.primary->fb = NULL;
2373
2374 /*
2375 * Failed to alloc the obj, check to see if we should share
2376 * an fb with another CRTC instead
2377 */
2378 for_each_crtc(dev, c) {
2379 i = to_intel_crtc(c);
2380
2381 if (c == &intel_crtc->base)
2382 continue;
2383
2384 if (!i->active)
2385 continue;
2386
2387 obj = intel_fb_obj(c->primary->fb);
2388 if (obj == NULL)
2389 continue;
2390
2391 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2392 drm_framebuffer_reference(c->primary->fb);
2393 intel_crtc->base.primary->fb = c->primary->fb;
2394 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2395 break;
2396 }
2397 }
2398 }
2399
2400 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2401 struct drm_framebuffer *fb,
2402 int x, int y)
2403 {
2404 struct drm_device *dev = crtc->dev;
2405 struct drm_i915_private *dev_priv = dev->dev_private;
2406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2407 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2408 int plane = intel_crtc->plane;
2409 unsigned long linear_offset;
2410 u32 dspcntr;
2411 u32 reg;
2412
2413 reg = DSPCNTR(plane);
2414 dspcntr = I915_READ(reg);
2415 /* Mask out pixel format bits in case we change it */
2416 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2417 switch (fb->pixel_format) {
2418 case DRM_FORMAT_C8:
2419 dspcntr |= DISPPLANE_8BPP;
2420 break;
2421 case DRM_FORMAT_XRGB1555:
2422 case DRM_FORMAT_ARGB1555:
2423 dspcntr |= DISPPLANE_BGRX555;
2424 break;
2425 case DRM_FORMAT_RGB565:
2426 dspcntr |= DISPPLANE_BGRX565;
2427 break;
2428 case DRM_FORMAT_XRGB8888:
2429 case DRM_FORMAT_ARGB8888:
2430 dspcntr |= DISPPLANE_BGRX888;
2431 break;
2432 case DRM_FORMAT_XBGR8888:
2433 case DRM_FORMAT_ABGR8888:
2434 dspcntr |= DISPPLANE_RGBX888;
2435 break;
2436 case DRM_FORMAT_XRGB2101010:
2437 case DRM_FORMAT_ARGB2101010:
2438 dspcntr |= DISPPLANE_BGRX101010;
2439 break;
2440 case DRM_FORMAT_XBGR2101010:
2441 case DRM_FORMAT_ABGR2101010:
2442 dspcntr |= DISPPLANE_RGBX101010;
2443 break;
2444 default:
2445 BUG();
2446 }
2447
2448 if (INTEL_INFO(dev)->gen >= 4) {
2449 if (obj->tiling_mode != I915_TILING_NONE)
2450 dspcntr |= DISPPLANE_TILED;
2451 else
2452 dspcntr &= ~DISPPLANE_TILED;
2453 }
2454
2455 if (IS_G4X(dev))
2456 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2457
2458 I915_WRITE(reg, dspcntr);
2459
2460 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2461
2462 if (INTEL_INFO(dev)->gen >= 4) {
2463 intel_crtc->dspaddr_offset =
2464 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2465 fb->bits_per_pixel / 8,
2466 fb->pitches[0]);
2467 linear_offset -= intel_crtc->dspaddr_offset;
2468 } else {
2469 intel_crtc->dspaddr_offset = linear_offset;
2470 }
2471
2472 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2473 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2474 fb->pitches[0]);
2475 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2476 if (INTEL_INFO(dev)->gen >= 4) {
2477 I915_WRITE(DSPSURF(plane),
2478 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2479 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2480 I915_WRITE(DSPLINOFF(plane), linear_offset);
2481 } else
2482 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2483 POSTING_READ(reg);
2484 }
2485
2486 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2487 struct drm_framebuffer *fb,
2488 int x, int y)
2489 {
2490 struct drm_device *dev = crtc->dev;
2491 struct drm_i915_private *dev_priv = dev->dev_private;
2492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2493 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2494 int plane = intel_crtc->plane;
2495 unsigned long linear_offset;
2496 u32 dspcntr;
2497 u32 reg;
2498
2499 reg = DSPCNTR(plane);
2500 dspcntr = I915_READ(reg);
2501 /* Mask out pixel format bits in case we change it */
2502 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2503 switch (fb->pixel_format) {
2504 case DRM_FORMAT_C8:
2505 dspcntr |= DISPPLANE_8BPP;
2506 break;
2507 case DRM_FORMAT_RGB565:
2508 dspcntr |= DISPPLANE_BGRX565;
2509 break;
2510 case DRM_FORMAT_XRGB8888:
2511 case DRM_FORMAT_ARGB8888:
2512 dspcntr |= DISPPLANE_BGRX888;
2513 break;
2514 case DRM_FORMAT_XBGR8888:
2515 case DRM_FORMAT_ABGR8888:
2516 dspcntr |= DISPPLANE_RGBX888;
2517 break;
2518 case DRM_FORMAT_XRGB2101010:
2519 case DRM_FORMAT_ARGB2101010:
2520 dspcntr |= DISPPLANE_BGRX101010;
2521 break;
2522 case DRM_FORMAT_XBGR2101010:
2523 case DRM_FORMAT_ABGR2101010:
2524 dspcntr |= DISPPLANE_RGBX101010;
2525 break;
2526 default:
2527 BUG();
2528 }
2529
2530 if (obj->tiling_mode != I915_TILING_NONE)
2531 dspcntr |= DISPPLANE_TILED;
2532 else
2533 dspcntr &= ~DISPPLANE_TILED;
2534
2535 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2536 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2537 else
2538 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2539
2540 I915_WRITE(reg, dspcntr);
2541
2542 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2543 intel_crtc->dspaddr_offset =
2544 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2545 fb->bits_per_pixel / 8,
2546 fb->pitches[0]);
2547 linear_offset -= intel_crtc->dspaddr_offset;
2548
2549 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2550 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2551 fb->pitches[0]);
2552 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2553 I915_WRITE(DSPSURF(plane),
2554 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2555 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2556 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2557 } else {
2558 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2559 I915_WRITE(DSPLINOFF(plane), linear_offset);
2560 }
2561 POSTING_READ(reg);
2562 }
2563
2564 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2565 static int
2566 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2567 int x, int y, enum mode_set_atomic state)
2568 {
2569 struct drm_device *dev = crtc->dev;
2570 struct drm_i915_private *dev_priv = dev->dev_private;
2571
2572 if (dev_priv->display.disable_fbc)
2573 dev_priv->display.disable_fbc(dev);
2574 intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2575
2576 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2577
2578 return 0;
2579 }
2580
2581 void intel_display_handle_reset(struct drm_device *dev)
2582 {
2583 struct drm_i915_private *dev_priv = dev->dev_private;
2584 struct drm_crtc *crtc;
2585
2586 /*
2587 * Flips in the rings have been nuked by the reset,
2588 * so complete all pending flips so that user space
2589 * will get its events and not get stuck.
2590 *
2591 * Also update the base address of all primary
2592 * planes to the the last fb to make sure we're
2593 * showing the correct fb after a reset.
2594 *
2595 * Need to make two loops over the crtcs so that we
2596 * don't try to grab a crtc mutex before the
2597 * pending_flip_queue really got woken up.
2598 */
2599
2600 for_each_crtc(dev, crtc) {
2601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2602 enum plane plane = intel_crtc->plane;
2603
2604 intel_prepare_page_flip(dev, plane);
2605 intel_finish_page_flip_plane(dev, plane);
2606 }
2607
2608 for_each_crtc(dev, crtc) {
2609 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2610
2611 drm_modeset_lock(&crtc->mutex, NULL);
2612 /*
2613 * FIXME: Once we have proper support for primary planes (and
2614 * disabling them without disabling the entire crtc) allow again
2615 * a NULL crtc->primary->fb.
2616 */
2617 if (intel_crtc->active && crtc->primary->fb)
2618 dev_priv->display.update_primary_plane(crtc,
2619 crtc->primary->fb,
2620 crtc->x,
2621 crtc->y);
2622 drm_modeset_unlock(&crtc->mutex);
2623 }
2624 }
2625
2626 static int
2627 intel_finish_fb(struct drm_framebuffer *old_fb)
2628 {
2629 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2630 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2631 bool was_interruptible = dev_priv->mm.interruptible;
2632 int ret;
2633
2634 /* Big Hammer, we also need to ensure that any pending
2635 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2636 * current scanout is retired before unpinning the old
2637 * framebuffer.
2638 *
2639 * This should only fail upon a hung GPU, in which case we
2640 * can safely continue.
2641 */
2642 dev_priv->mm.interruptible = false;
2643 ret = i915_gem_object_finish_gpu(obj);
2644 dev_priv->mm.interruptible = was_interruptible;
2645
2646 return ret;
2647 }
2648
2649 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2650 {
2651 struct drm_device *dev = crtc->dev;
2652 struct drm_i915_private *dev_priv = dev->dev_private;
2653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2654 unsigned long flags;
2655 bool pending;
2656
2657 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2658 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2659 return false;
2660
2661 spin_lock_irqsave(&dev->event_lock, flags);
2662 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2663 spin_unlock_irqrestore(&dev->event_lock, flags);
2664
2665 return pending;
2666 }
2667
2668 static int
2669 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2670 struct drm_framebuffer *fb)
2671 {
2672 struct drm_device *dev = crtc->dev;
2673 struct drm_i915_private *dev_priv = dev->dev_private;
2674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2675 enum pipe pipe = intel_crtc->pipe;
2676 struct drm_framebuffer *old_fb = crtc->primary->fb;
2677 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2678 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2679 int ret;
2680
2681 if (intel_crtc_has_pending_flip(crtc)) {
2682 DRM_ERROR("pipe is still busy with an old pageflip\n");
2683 return -EBUSY;
2684 }
2685
2686 /* no fb bound */
2687 if (!fb) {
2688 DRM_ERROR("No FB bound\n");
2689 return 0;
2690 }
2691
2692 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2693 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2694 plane_name(intel_crtc->plane),
2695 INTEL_INFO(dev)->num_pipes);
2696 return -EINVAL;
2697 }
2698
2699 mutex_lock(&dev->struct_mutex);
2700 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2701 if (ret == 0)
2702 i915_gem_track_fb(old_obj, obj,
2703 INTEL_FRONTBUFFER_PRIMARY(pipe));
2704 mutex_unlock(&dev->struct_mutex);
2705 if (ret != 0) {
2706 DRM_ERROR("pin & fence failed\n");
2707 return ret;
2708 }
2709
2710 /*
2711 * Update pipe size and adjust fitter if needed: the reason for this is
2712 * that in compute_mode_changes we check the native mode (not the pfit
2713 * mode) to see if we can flip rather than do a full mode set. In the
2714 * fastboot case, we'll flip, but if we don't update the pipesrc and
2715 * pfit state, we'll end up with a big fb scanned out into the wrong
2716 * sized surface.
2717 *
2718 * To fix this properly, we need to hoist the checks up into
2719 * compute_mode_changes (or above), check the actual pfit state and
2720 * whether the platform allows pfit disable with pipe active, and only
2721 * then update the pipesrc and pfit state, even on the flip path.
2722 */
2723 if (i915.fastboot) {
2724 const struct drm_display_mode *adjusted_mode =
2725 &intel_crtc->config.adjusted_mode;
2726
2727 I915_WRITE(PIPESRC(intel_crtc->pipe),
2728 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2729 (adjusted_mode->crtc_vdisplay - 1));
2730 if (!intel_crtc->config.pch_pfit.enabled &&
2731 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2732 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2733 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2734 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2735 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2736 }
2737 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2738 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2739 }
2740
2741 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2742
2743 if (intel_crtc->active)
2744 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2745
2746 crtc->primary->fb = fb;
2747 crtc->x = x;
2748 crtc->y = y;
2749
2750 if (old_fb) {
2751 if (intel_crtc->active && old_fb != fb)
2752 intel_wait_for_vblank(dev, intel_crtc->pipe);
2753 mutex_lock(&dev->struct_mutex);
2754 intel_unpin_fb_obj(old_obj);
2755 mutex_unlock(&dev->struct_mutex);
2756 }
2757
2758 mutex_lock(&dev->struct_mutex);
2759 intel_update_fbc(dev);
2760 mutex_unlock(&dev->struct_mutex);
2761
2762 return 0;
2763 }
2764
2765 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2766 {
2767 struct drm_device *dev = crtc->dev;
2768 struct drm_i915_private *dev_priv = dev->dev_private;
2769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2770 int pipe = intel_crtc->pipe;
2771 u32 reg, temp;
2772
2773 /* enable normal train */
2774 reg = FDI_TX_CTL(pipe);
2775 temp = I915_READ(reg);
2776 if (IS_IVYBRIDGE(dev)) {
2777 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2778 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2779 } else {
2780 temp &= ~FDI_LINK_TRAIN_NONE;
2781 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2782 }
2783 I915_WRITE(reg, temp);
2784
2785 reg = FDI_RX_CTL(pipe);
2786 temp = I915_READ(reg);
2787 if (HAS_PCH_CPT(dev)) {
2788 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2789 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2790 } else {
2791 temp &= ~FDI_LINK_TRAIN_NONE;
2792 temp |= FDI_LINK_TRAIN_NONE;
2793 }
2794 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2795
2796 /* wait one idle pattern time */
2797 POSTING_READ(reg);
2798 udelay(1000);
2799
2800 /* IVB wants error correction enabled */
2801 if (IS_IVYBRIDGE(dev))
2802 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2803 FDI_FE_ERRC_ENABLE);
2804 }
2805
2806 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2807 {
2808 return crtc->base.enabled && crtc->active &&
2809 crtc->config.has_pch_encoder;
2810 }
2811
2812 static void ivb_modeset_global_resources(struct drm_device *dev)
2813 {
2814 struct drm_i915_private *dev_priv = dev->dev_private;
2815 struct intel_crtc *pipe_B_crtc =
2816 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2817 struct intel_crtc *pipe_C_crtc =
2818 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2819 uint32_t temp;
2820
2821 /*
2822 * When everything is off disable fdi C so that we could enable fdi B
2823 * with all lanes. Note that we don't care about enabled pipes without
2824 * an enabled pch encoder.
2825 */
2826 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2827 !pipe_has_enabled_pch(pipe_C_crtc)) {
2828 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2829 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2830
2831 temp = I915_READ(SOUTH_CHICKEN1);
2832 temp &= ~FDI_BC_BIFURCATION_SELECT;
2833 DRM_DEBUG_KMS("disabling fdi C rx\n");
2834 I915_WRITE(SOUTH_CHICKEN1, temp);
2835 }
2836 }
2837
2838 /* The FDI link training functions for ILK/Ibexpeak. */
2839 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2840 {
2841 struct drm_device *dev = crtc->dev;
2842 struct drm_i915_private *dev_priv = dev->dev_private;
2843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2844 int pipe = intel_crtc->pipe;
2845 u32 reg, temp, tries;
2846
2847 /* FDI needs bits from pipe first */
2848 assert_pipe_enabled(dev_priv, pipe);
2849
2850 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2851 for train result */
2852 reg = FDI_RX_IMR(pipe);
2853 temp = I915_READ(reg);
2854 temp &= ~FDI_RX_SYMBOL_LOCK;
2855 temp &= ~FDI_RX_BIT_LOCK;
2856 I915_WRITE(reg, temp);
2857 I915_READ(reg);
2858 udelay(150);
2859
2860 /* enable CPU FDI TX and PCH FDI RX */
2861 reg = FDI_TX_CTL(pipe);
2862 temp = I915_READ(reg);
2863 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2864 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2865 temp &= ~FDI_LINK_TRAIN_NONE;
2866 temp |= FDI_LINK_TRAIN_PATTERN_1;
2867 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2868
2869 reg = FDI_RX_CTL(pipe);
2870 temp = I915_READ(reg);
2871 temp &= ~FDI_LINK_TRAIN_NONE;
2872 temp |= FDI_LINK_TRAIN_PATTERN_1;
2873 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2874
2875 POSTING_READ(reg);
2876 udelay(150);
2877
2878 /* Ironlake workaround, enable clock pointer after FDI enable*/
2879 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2880 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2881 FDI_RX_PHASE_SYNC_POINTER_EN);
2882
2883 reg = FDI_RX_IIR(pipe);
2884 for (tries = 0; tries < 5; tries++) {
2885 temp = I915_READ(reg);
2886 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2887
2888 if ((temp & FDI_RX_BIT_LOCK)) {
2889 DRM_DEBUG_KMS("FDI train 1 done.\n");
2890 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2891 break;
2892 }
2893 }
2894 if (tries == 5)
2895 DRM_ERROR("FDI train 1 fail!\n");
2896
2897 /* Train 2 */
2898 reg = FDI_TX_CTL(pipe);
2899 temp = I915_READ(reg);
2900 temp &= ~FDI_LINK_TRAIN_NONE;
2901 temp |= FDI_LINK_TRAIN_PATTERN_2;
2902 I915_WRITE(reg, temp);
2903
2904 reg = FDI_RX_CTL(pipe);
2905 temp = I915_READ(reg);
2906 temp &= ~FDI_LINK_TRAIN_NONE;
2907 temp |= FDI_LINK_TRAIN_PATTERN_2;
2908 I915_WRITE(reg, temp);
2909
2910 POSTING_READ(reg);
2911 udelay(150);
2912
2913 reg = FDI_RX_IIR(pipe);
2914 for (tries = 0; tries < 5; tries++) {
2915 temp = I915_READ(reg);
2916 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2917
2918 if (temp & FDI_RX_SYMBOL_LOCK) {
2919 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2920 DRM_DEBUG_KMS("FDI train 2 done.\n");
2921 break;
2922 }
2923 }
2924 if (tries == 5)
2925 DRM_ERROR("FDI train 2 fail!\n");
2926
2927 DRM_DEBUG_KMS("FDI train done\n");
2928
2929 }
2930
2931 static const int snb_b_fdi_train_param[] = {
2932 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2933 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2934 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2935 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2936 };
2937
2938 /* The FDI link training functions for SNB/Cougarpoint. */
2939 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2940 {
2941 struct drm_device *dev = crtc->dev;
2942 struct drm_i915_private *dev_priv = dev->dev_private;
2943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2944 int pipe = intel_crtc->pipe;
2945 u32 reg, temp, i, retry;
2946
2947 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2948 for train result */
2949 reg = FDI_RX_IMR(pipe);
2950 temp = I915_READ(reg);
2951 temp &= ~FDI_RX_SYMBOL_LOCK;
2952 temp &= ~FDI_RX_BIT_LOCK;
2953 I915_WRITE(reg, temp);
2954
2955 POSTING_READ(reg);
2956 udelay(150);
2957
2958 /* enable CPU FDI TX and PCH FDI RX */
2959 reg = FDI_TX_CTL(pipe);
2960 temp = I915_READ(reg);
2961 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2962 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2963 temp &= ~FDI_LINK_TRAIN_NONE;
2964 temp |= FDI_LINK_TRAIN_PATTERN_1;
2965 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2966 /* SNB-B */
2967 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2968 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2969
2970 I915_WRITE(FDI_RX_MISC(pipe),
2971 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2972
2973 reg = FDI_RX_CTL(pipe);
2974 temp = I915_READ(reg);
2975 if (HAS_PCH_CPT(dev)) {
2976 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2977 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2978 } else {
2979 temp &= ~FDI_LINK_TRAIN_NONE;
2980 temp |= FDI_LINK_TRAIN_PATTERN_1;
2981 }
2982 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2983
2984 POSTING_READ(reg);
2985 udelay(150);
2986
2987 for (i = 0; i < 4; i++) {
2988 reg = FDI_TX_CTL(pipe);
2989 temp = I915_READ(reg);
2990 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2991 temp |= snb_b_fdi_train_param[i];
2992 I915_WRITE(reg, temp);
2993
2994 POSTING_READ(reg);
2995 udelay(500);
2996
2997 for (retry = 0; retry < 5; retry++) {
2998 reg = FDI_RX_IIR(pipe);
2999 temp = I915_READ(reg);
3000 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3001 if (temp & FDI_RX_BIT_LOCK) {
3002 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3003 DRM_DEBUG_KMS("FDI train 1 done.\n");
3004 break;
3005 }
3006 udelay(50);
3007 }
3008 if (retry < 5)
3009 break;
3010 }
3011 if (i == 4)
3012 DRM_ERROR("FDI train 1 fail!\n");
3013
3014 /* Train 2 */
3015 reg = FDI_TX_CTL(pipe);
3016 temp = I915_READ(reg);
3017 temp &= ~FDI_LINK_TRAIN_NONE;
3018 temp |= FDI_LINK_TRAIN_PATTERN_2;
3019 if (IS_GEN6(dev)) {
3020 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3021 /* SNB-B */
3022 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3023 }
3024 I915_WRITE(reg, temp);
3025
3026 reg = FDI_RX_CTL(pipe);
3027 temp = I915_READ(reg);
3028 if (HAS_PCH_CPT(dev)) {
3029 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3030 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3031 } else {
3032 temp &= ~FDI_LINK_TRAIN_NONE;
3033 temp |= FDI_LINK_TRAIN_PATTERN_2;
3034 }
3035 I915_WRITE(reg, temp);
3036
3037 POSTING_READ(reg);
3038 udelay(150);
3039
3040 for (i = 0; i < 4; i++) {
3041 reg = FDI_TX_CTL(pipe);
3042 temp = I915_READ(reg);
3043 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3044 temp |= snb_b_fdi_train_param[i];
3045 I915_WRITE(reg, temp);
3046
3047 POSTING_READ(reg);
3048 udelay(500);
3049
3050 for (retry = 0; retry < 5; retry++) {
3051 reg = FDI_RX_IIR(pipe);
3052 temp = I915_READ(reg);
3053 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3054 if (temp & FDI_RX_SYMBOL_LOCK) {
3055 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3056 DRM_DEBUG_KMS("FDI train 2 done.\n");
3057 break;
3058 }
3059 udelay(50);
3060 }
3061 if (retry < 5)
3062 break;
3063 }
3064 if (i == 4)
3065 DRM_ERROR("FDI train 2 fail!\n");
3066
3067 DRM_DEBUG_KMS("FDI train done.\n");
3068 }
3069
3070 /* Manual link training for Ivy Bridge A0 parts */
3071 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3072 {
3073 struct drm_device *dev = crtc->dev;
3074 struct drm_i915_private *dev_priv = dev->dev_private;
3075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3076 int pipe = intel_crtc->pipe;
3077 u32 reg, temp, i, j;
3078
3079 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3080 for train result */
3081 reg = FDI_RX_IMR(pipe);
3082 temp = I915_READ(reg);
3083 temp &= ~FDI_RX_SYMBOL_LOCK;
3084 temp &= ~FDI_RX_BIT_LOCK;
3085 I915_WRITE(reg, temp);
3086
3087 POSTING_READ(reg);
3088 udelay(150);
3089
3090 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3091 I915_READ(FDI_RX_IIR(pipe)));
3092
3093 /* Try each vswing and preemphasis setting twice before moving on */
3094 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3095 /* disable first in case we need to retry */
3096 reg = FDI_TX_CTL(pipe);
3097 temp = I915_READ(reg);
3098 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3099 temp &= ~FDI_TX_ENABLE;
3100 I915_WRITE(reg, temp);
3101
3102 reg = FDI_RX_CTL(pipe);
3103 temp = I915_READ(reg);
3104 temp &= ~FDI_LINK_TRAIN_AUTO;
3105 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3106 temp &= ~FDI_RX_ENABLE;
3107 I915_WRITE(reg, temp);
3108
3109 /* enable CPU FDI TX and PCH FDI RX */
3110 reg = FDI_TX_CTL(pipe);
3111 temp = I915_READ(reg);
3112 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3113 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3114 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3115 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3116 temp |= snb_b_fdi_train_param[j/2];
3117 temp |= FDI_COMPOSITE_SYNC;
3118 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3119
3120 I915_WRITE(FDI_RX_MISC(pipe),
3121 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3122
3123 reg = FDI_RX_CTL(pipe);
3124 temp = I915_READ(reg);
3125 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3126 temp |= FDI_COMPOSITE_SYNC;
3127 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3128
3129 POSTING_READ(reg);
3130 udelay(1); /* should be 0.5us */
3131
3132 for (i = 0; i < 4; i++) {
3133 reg = FDI_RX_IIR(pipe);
3134 temp = I915_READ(reg);
3135 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3136
3137 if (temp & FDI_RX_BIT_LOCK ||
3138 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3139 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3140 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3141 i);
3142 break;
3143 }
3144 udelay(1); /* should be 0.5us */
3145 }
3146 if (i == 4) {
3147 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3148 continue;
3149 }
3150
3151 /* Train 2 */
3152 reg = FDI_TX_CTL(pipe);
3153 temp = I915_READ(reg);
3154 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3155 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3156 I915_WRITE(reg, temp);
3157
3158 reg = FDI_RX_CTL(pipe);
3159 temp = I915_READ(reg);
3160 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3161 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3162 I915_WRITE(reg, temp);
3163
3164 POSTING_READ(reg);
3165 udelay(2); /* should be 1.5us */
3166
3167 for (i = 0; i < 4; i++) {
3168 reg = FDI_RX_IIR(pipe);
3169 temp = I915_READ(reg);
3170 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3171
3172 if (temp & FDI_RX_SYMBOL_LOCK ||
3173 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3174 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3175 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3176 i);
3177 goto train_done;
3178 }
3179 udelay(2); /* should be 1.5us */
3180 }
3181 if (i == 4)
3182 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3183 }
3184
3185 train_done:
3186 DRM_DEBUG_KMS("FDI train done.\n");
3187 }
3188
3189 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3190 {
3191 struct drm_device *dev = intel_crtc->base.dev;
3192 struct drm_i915_private *dev_priv = dev->dev_private;
3193 int pipe = intel_crtc->pipe;
3194 u32 reg, temp;
3195
3196
3197 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3198 reg = FDI_RX_CTL(pipe);
3199 temp = I915_READ(reg);
3200 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3201 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3202 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3203 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3204
3205 POSTING_READ(reg);
3206 udelay(200);
3207
3208 /* Switch from Rawclk to PCDclk */
3209 temp = I915_READ(reg);
3210 I915_WRITE(reg, temp | FDI_PCDCLK);
3211
3212 POSTING_READ(reg);
3213 udelay(200);
3214
3215 /* Enable CPU FDI TX PLL, always on for Ironlake */
3216 reg = FDI_TX_CTL(pipe);
3217 temp = I915_READ(reg);
3218 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3219 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3220
3221 POSTING_READ(reg);
3222 udelay(100);
3223 }
3224 }
3225
3226 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3227 {
3228 struct drm_device *dev = intel_crtc->base.dev;
3229 struct drm_i915_private *dev_priv = dev->dev_private;
3230 int pipe = intel_crtc->pipe;
3231 u32 reg, temp;
3232
3233 /* Switch from PCDclk to Rawclk */
3234 reg = FDI_RX_CTL(pipe);
3235 temp = I915_READ(reg);
3236 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3237
3238 /* Disable CPU FDI TX PLL */
3239 reg = FDI_TX_CTL(pipe);
3240 temp = I915_READ(reg);
3241 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3242
3243 POSTING_READ(reg);
3244 udelay(100);
3245
3246 reg = FDI_RX_CTL(pipe);
3247 temp = I915_READ(reg);
3248 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3249
3250 /* Wait for the clocks to turn off. */
3251 POSTING_READ(reg);
3252 udelay(100);
3253 }
3254
3255 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3256 {
3257 struct drm_device *dev = crtc->dev;
3258 struct drm_i915_private *dev_priv = dev->dev_private;
3259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3260 int pipe = intel_crtc->pipe;
3261 u32 reg, temp;
3262
3263 /* disable CPU FDI tx and PCH FDI rx */
3264 reg = FDI_TX_CTL(pipe);
3265 temp = I915_READ(reg);
3266 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3267 POSTING_READ(reg);
3268
3269 reg = FDI_RX_CTL(pipe);
3270 temp = I915_READ(reg);
3271 temp &= ~(0x7 << 16);
3272 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3273 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3274
3275 POSTING_READ(reg);
3276 udelay(100);
3277
3278 /* Ironlake workaround, disable clock pointer after downing FDI */
3279 if (HAS_PCH_IBX(dev))
3280 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3281
3282 /* still set train pattern 1 */
3283 reg = FDI_TX_CTL(pipe);
3284 temp = I915_READ(reg);
3285 temp &= ~FDI_LINK_TRAIN_NONE;
3286 temp |= FDI_LINK_TRAIN_PATTERN_1;
3287 I915_WRITE(reg, temp);
3288
3289 reg = FDI_RX_CTL(pipe);
3290 temp = I915_READ(reg);
3291 if (HAS_PCH_CPT(dev)) {
3292 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3293 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3294 } else {
3295 temp &= ~FDI_LINK_TRAIN_NONE;
3296 temp |= FDI_LINK_TRAIN_PATTERN_1;
3297 }
3298 /* BPC in FDI rx is consistent with that in PIPECONF */
3299 temp &= ~(0x07 << 16);
3300 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3301 I915_WRITE(reg, temp);
3302
3303 POSTING_READ(reg);
3304 udelay(100);
3305 }
3306
3307 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3308 {
3309 struct intel_crtc *crtc;
3310
3311 /* Note that we don't need to be called with mode_config.lock here
3312 * as our list of CRTC objects is static for the lifetime of the
3313 * device and so cannot disappear as we iterate. Similarly, we can
3314 * happily treat the predicates as racy, atomic checks as userspace
3315 * cannot claim and pin a new fb without at least acquring the
3316 * struct_mutex and so serialising with us.
3317 */
3318 for_each_intel_crtc(dev, crtc) {
3319 if (atomic_read(&crtc->unpin_work_count) == 0)
3320 continue;
3321
3322 if (crtc->unpin_work)
3323 intel_wait_for_vblank(dev, crtc->pipe);
3324
3325 return true;
3326 }
3327
3328 return false;
3329 }
3330
3331 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3332 {
3333 struct drm_device *dev = crtc->dev;
3334 struct drm_i915_private *dev_priv = dev->dev_private;
3335
3336 if (crtc->primary->fb == NULL)
3337 return;
3338
3339 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3340
3341 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3342 !intel_crtc_has_pending_flip(crtc),
3343 60*HZ) == 0);
3344
3345 mutex_lock(&dev->struct_mutex);
3346 intel_finish_fb(crtc->primary->fb);
3347 mutex_unlock(&dev->struct_mutex);
3348 }
3349
3350 /* Program iCLKIP clock to the desired frequency */
3351 static void lpt_program_iclkip(struct drm_crtc *crtc)
3352 {
3353 struct drm_device *dev = crtc->dev;
3354 struct drm_i915_private *dev_priv = dev->dev_private;
3355 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3356 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3357 u32 temp;
3358
3359 mutex_lock(&dev_priv->dpio_lock);
3360
3361 /* It is necessary to ungate the pixclk gate prior to programming
3362 * the divisors, and gate it back when it is done.
3363 */
3364 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3365
3366 /* Disable SSCCTL */
3367 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3368 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3369 SBI_SSCCTL_DISABLE,
3370 SBI_ICLK);
3371
3372 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3373 if (clock == 20000) {
3374 auxdiv = 1;
3375 divsel = 0x41;
3376 phaseinc = 0x20;
3377 } else {
3378 /* The iCLK virtual clock root frequency is in MHz,
3379 * but the adjusted_mode->crtc_clock in in KHz. To get the
3380 * divisors, it is necessary to divide one by another, so we
3381 * convert the virtual clock precision to KHz here for higher
3382 * precision.
3383 */
3384 u32 iclk_virtual_root_freq = 172800 * 1000;
3385 u32 iclk_pi_range = 64;
3386 u32 desired_divisor, msb_divisor_value, pi_value;
3387
3388 desired_divisor = (iclk_virtual_root_freq / clock);
3389 msb_divisor_value = desired_divisor / iclk_pi_range;
3390 pi_value = desired_divisor % iclk_pi_range;
3391
3392 auxdiv = 0;
3393 divsel = msb_divisor_value - 2;
3394 phaseinc = pi_value;
3395 }
3396
3397 /* This should not happen with any sane values */
3398 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3399 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3400 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3401 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3402
3403 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3404 clock,
3405 auxdiv,
3406 divsel,
3407 phasedir,
3408 phaseinc);
3409
3410 /* Program SSCDIVINTPHASE6 */
3411 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3412 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3413 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3414 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3415 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3416 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3417 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3418 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3419
3420 /* Program SSCAUXDIV */
3421 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3422 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3423 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3424 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3425
3426 /* Enable modulator and associated divider */
3427 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3428 temp &= ~SBI_SSCCTL_DISABLE;
3429 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3430
3431 /* Wait for initialization time */
3432 udelay(24);
3433
3434 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3435
3436 mutex_unlock(&dev_priv->dpio_lock);
3437 }
3438
3439 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3440 enum pipe pch_transcoder)
3441 {
3442 struct drm_device *dev = crtc->base.dev;
3443 struct drm_i915_private *dev_priv = dev->dev_private;
3444 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3445
3446 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3447 I915_READ(HTOTAL(cpu_transcoder)));
3448 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3449 I915_READ(HBLANK(cpu_transcoder)));
3450 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3451 I915_READ(HSYNC(cpu_transcoder)));
3452
3453 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3454 I915_READ(VTOTAL(cpu_transcoder)));
3455 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3456 I915_READ(VBLANK(cpu_transcoder)));
3457 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3458 I915_READ(VSYNC(cpu_transcoder)));
3459 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3460 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3461 }
3462
3463 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3464 {
3465 struct drm_i915_private *dev_priv = dev->dev_private;
3466 uint32_t temp;
3467
3468 temp = I915_READ(SOUTH_CHICKEN1);
3469 if (temp & FDI_BC_BIFURCATION_SELECT)
3470 return;
3471
3472 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3473 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3474
3475 temp |= FDI_BC_BIFURCATION_SELECT;
3476 DRM_DEBUG_KMS("enabling fdi C rx\n");
3477 I915_WRITE(SOUTH_CHICKEN1, temp);
3478 POSTING_READ(SOUTH_CHICKEN1);
3479 }
3480
3481 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3482 {
3483 struct drm_device *dev = intel_crtc->base.dev;
3484 struct drm_i915_private *dev_priv = dev->dev_private;
3485
3486 switch (intel_crtc->pipe) {
3487 case PIPE_A:
3488 break;
3489 case PIPE_B:
3490 if (intel_crtc->config.fdi_lanes > 2)
3491 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3492 else
3493 cpt_enable_fdi_bc_bifurcation(dev);
3494
3495 break;
3496 case PIPE_C:
3497 cpt_enable_fdi_bc_bifurcation(dev);
3498
3499 break;
3500 default:
3501 BUG();
3502 }
3503 }
3504
3505 /*
3506 * Enable PCH resources required for PCH ports:
3507 * - PCH PLLs
3508 * - FDI training & RX/TX
3509 * - update transcoder timings
3510 * - DP transcoding bits
3511 * - transcoder
3512 */
3513 static void ironlake_pch_enable(struct drm_crtc *crtc)
3514 {
3515 struct drm_device *dev = crtc->dev;
3516 struct drm_i915_private *dev_priv = dev->dev_private;
3517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3518 int pipe = intel_crtc->pipe;
3519 u32 reg, temp;
3520
3521 assert_pch_transcoder_disabled(dev_priv, pipe);
3522
3523 if (IS_IVYBRIDGE(dev))
3524 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3525
3526 /* Write the TU size bits before fdi link training, so that error
3527 * detection works. */
3528 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3529 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3530
3531 /* For PCH output, training FDI link */
3532 dev_priv->display.fdi_link_train(crtc);
3533
3534 /* We need to program the right clock selection before writing the pixel
3535 * mutliplier into the DPLL. */
3536 if (HAS_PCH_CPT(dev)) {
3537 u32 sel;
3538
3539 temp = I915_READ(PCH_DPLL_SEL);
3540 temp |= TRANS_DPLL_ENABLE(pipe);
3541 sel = TRANS_DPLLB_SEL(pipe);
3542 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3543 temp |= sel;
3544 else
3545 temp &= ~sel;
3546 I915_WRITE(PCH_DPLL_SEL, temp);
3547 }
3548
3549 /* XXX: pch pll's can be enabled any time before we enable the PCH
3550 * transcoder, and we actually should do this to not upset any PCH
3551 * transcoder that already use the clock when we share it.
3552 *
3553 * Note that enable_shared_dpll tries to do the right thing, but
3554 * get_shared_dpll unconditionally resets the pll - we need that to have
3555 * the right LVDS enable sequence. */
3556 intel_enable_shared_dpll(intel_crtc);
3557
3558 /* set transcoder timing, panel must allow it */
3559 assert_panel_unlocked(dev_priv, pipe);
3560 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3561
3562 intel_fdi_normal_train(crtc);
3563
3564 /* For PCH DP, enable TRANS_DP_CTL */
3565 if (HAS_PCH_CPT(dev) &&
3566 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3567 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3568 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3569 reg = TRANS_DP_CTL(pipe);
3570 temp = I915_READ(reg);
3571 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3572 TRANS_DP_SYNC_MASK |
3573 TRANS_DP_BPC_MASK);
3574 temp |= (TRANS_DP_OUTPUT_ENABLE |
3575 TRANS_DP_ENH_FRAMING);
3576 temp |= bpc << 9; /* same format but at 11:9 */
3577
3578 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3579 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3580 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3581 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3582
3583 switch (intel_trans_dp_port_sel(crtc)) {
3584 case PCH_DP_B:
3585 temp |= TRANS_DP_PORT_SEL_B;
3586 break;
3587 case PCH_DP_C:
3588 temp |= TRANS_DP_PORT_SEL_C;
3589 break;
3590 case PCH_DP_D:
3591 temp |= TRANS_DP_PORT_SEL_D;
3592 break;
3593 default:
3594 BUG();
3595 }
3596
3597 I915_WRITE(reg, temp);
3598 }
3599
3600 ironlake_enable_pch_transcoder(dev_priv, pipe);
3601 }
3602
3603 static void lpt_pch_enable(struct drm_crtc *crtc)
3604 {
3605 struct drm_device *dev = crtc->dev;
3606 struct drm_i915_private *dev_priv = dev->dev_private;
3607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3608 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3609
3610 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3611
3612 lpt_program_iclkip(crtc);
3613
3614 /* Set transcoder timing. */
3615 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3616
3617 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3618 }
3619
3620 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3621 {
3622 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3623
3624 if (pll == NULL)
3625 return;
3626
3627 if (pll->refcount == 0) {
3628 WARN(1, "bad %s refcount\n", pll->name);
3629 return;
3630 }
3631
3632 if (--pll->refcount == 0) {
3633 WARN_ON(pll->on);
3634 WARN_ON(pll->active);
3635 }
3636
3637 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3638 }
3639
3640 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3641 {
3642 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3643 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3644 enum intel_dpll_id i;
3645
3646 if (pll) {
3647 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3648 crtc->base.base.id, pll->name);
3649 intel_put_shared_dpll(crtc);
3650 }
3651
3652 if (HAS_PCH_IBX(dev_priv->dev)) {
3653 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3654 i = (enum intel_dpll_id) crtc->pipe;
3655 pll = &dev_priv->shared_dplls[i];
3656
3657 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3658 crtc->base.base.id, pll->name);
3659
3660 WARN_ON(pll->refcount);
3661
3662 goto found;
3663 }
3664
3665 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3666 pll = &dev_priv->shared_dplls[i];
3667
3668 /* Only want to check enabled timings first */
3669 if (pll->refcount == 0)
3670 continue;
3671
3672 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3673 sizeof(pll->hw_state)) == 0) {
3674 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3675 crtc->base.base.id,
3676 pll->name, pll->refcount, pll->active);
3677
3678 goto found;
3679 }
3680 }
3681
3682 /* Ok no matching timings, maybe there's a free one? */
3683 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3684 pll = &dev_priv->shared_dplls[i];
3685 if (pll->refcount == 0) {
3686 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3687 crtc->base.base.id, pll->name);
3688 goto found;
3689 }
3690 }
3691
3692 return NULL;
3693
3694 found:
3695 if (pll->refcount == 0)
3696 pll->hw_state = crtc->config.dpll_hw_state;
3697
3698 crtc->config.shared_dpll = i;
3699 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3700 pipe_name(crtc->pipe));
3701
3702 pll->refcount++;
3703
3704 return pll;
3705 }
3706
3707 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3708 {
3709 struct drm_i915_private *dev_priv = dev->dev_private;
3710 int dslreg = PIPEDSL(pipe);
3711 u32 temp;
3712
3713 temp = I915_READ(dslreg);
3714 udelay(500);
3715 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3716 if (wait_for(I915_READ(dslreg) != temp, 5))
3717 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3718 }
3719 }
3720
3721 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3722 {
3723 struct drm_device *dev = crtc->base.dev;
3724 struct drm_i915_private *dev_priv = dev->dev_private;
3725 int pipe = crtc->pipe;
3726
3727 if (crtc->config.pch_pfit.enabled) {
3728 /* Force use of hard-coded filter coefficients
3729 * as some pre-programmed values are broken,
3730 * e.g. x201.
3731 */
3732 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3733 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3734 PF_PIPE_SEL_IVB(pipe));
3735 else
3736 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3737 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3738 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3739 }
3740 }
3741
3742 static void intel_enable_planes(struct drm_crtc *crtc)
3743 {
3744 struct drm_device *dev = crtc->dev;
3745 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3746 struct drm_plane *plane;
3747 struct intel_plane *intel_plane;
3748
3749 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3750 intel_plane = to_intel_plane(plane);
3751 if (intel_plane->pipe == pipe)
3752 intel_plane_restore(&intel_plane->base);
3753 }
3754 }
3755
3756 static void intel_disable_planes(struct drm_crtc *crtc)
3757 {
3758 struct drm_device *dev = crtc->dev;
3759 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3760 struct drm_plane *plane;
3761 struct intel_plane *intel_plane;
3762
3763 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3764 intel_plane = to_intel_plane(plane);
3765 if (intel_plane->pipe == pipe)
3766 intel_plane_disable(&intel_plane->base);
3767 }
3768 }
3769
3770 void hsw_enable_ips(struct intel_crtc *crtc)
3771 {
3772 struct drm_device *dev = crtc->base.dev;
3773 struct drm_i915_private *dev_priv = dev->dev_private;
3774
3775 if (!crtc->config.ips_enabled)
3776 return;
3777
3778 /* We can only enable IPS after we enable a plane and wait for a vblank */
3779 intel_wait_for_vblank(dev, crtc->pipe);
3780
3781 assert_plane_enabled(dev_priv, crtc->plane);
3782 if (IS_BROADWELL(dev)) {
3783 mutex_lock(&dev_priv->rps.hw_lock);
3784 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3785 mutex_unlock(&dev_priv->rps.hw_lock);
3786 /* Quoting Art Runyan: "its not safe to expect any particular
3787 * value in IPS_CTL bit 31 after enabling IPS through the
3788 * mailbox." Moreover, the mailbox may return a bogus state,
3789 * so we need to just enable it and continue on.
3790 */
3791 } else {
3792 I915_WRITE(IPS_CTL, IPS_ENABLE);
3793 /* The bit only becomes 1 in the next vblank, so this wait here
3794 * is essentially intel_wait_for_vblank. If we don't have this
3795 * and don't wait for vblanks until the end of crtc_enable, then
3796 * the HW state readout code will complain that the expected
3797 * IPS_CTL value is not the one we read. */
3798 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3799 DRM_ERROR("Timed out waiting for IPS enable\n");
3800 }
3801 }
3802
3803 void hsw_disable_ips(struct intel_crtc *crtc)
3804 {
3805 struct drm_device *dev = crtc->base.dev;
3806 struct drm_i915_private *dev_priv = dev->dev_private;
3807
3808 if (!crtc->config.ips_enabled)
3809 return;
3810
3811 assert_plane_enabled(dev_priv, crtc->plane);
3812 if (IS_BROADWELL(dev)) {
3813 mutex_lock(&dev_priv->rps.hw_lock);
3814 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3815 mutex_unlock(&dev_priv->rps.hw_lock);
3816 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3817 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3818 DRM_ERROR("Timed out waiting for IPS disable\n");
3819 } else {
3820 I915_WRITE(IPS_CTL, 0);
3821 POSTING_READ(IPS_CTL);
3822 }
3823
3824 /* We need to wait for a vblank before we can disable the plane. */
3825 intel_wait_for_vblank(dev, crtc->pipe);
3826 }
3827
3828 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3829 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3830 {
3831 struct drm_device *dev = crtc->dev;
3832 struct drm_i915_private *dev_priv = dev->dev_private;
3833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3834 enum pipe pipe = intel_crtc->pipe;
3835 int palreg = PALETTE(pipe);
3836 int i;
3837 bool reenable_ips = false;
3838
3839 /* The clocks have to be on to load the palette. */
3840 if (!crtc->enabled || !intel_crtc->active)
3841 return;
3842
3843 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3844 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3845 assert_dsi_pll_enabled(dev_priv);
3846 else
3847 assert_pll_enabled(dev_priv, pipe);
3848 }
3849
3850 /* use legacy palette for Ironlake */
3851 if (HAS_PCH_SPLIT(dev))
3852 palreg = LGC_PALETTE(pipe);
3853
3854 /* Workaround : Do not read or write the pipe palette/gamma data while
3855 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3856 */
3857 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3858 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3859 GAMMA_MODE_MODE_SPLIT)) {
3860 hsw_disable_ips(intel_crtc);
3861 reenable_ips = true;
3862 }
3863
3864 for (i = 0; i < 256; i++) {
3865 I915_WRITE(palreg + 4 * i,
3866 (intel_crtc->lut_r[i] << 16) |
3867 (intel_crtc->lut_g[i] << 8) |
3868 intel_crtc->lut_b[i]);
3869 }
3870
3871 if (reenable_ips)
3872 hsw_enable_ips(intel_crtc);
3873 }
3874
3875 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3876 {
3877 if (!enable && intel_crtc->overlay) {
3878 struct drm_device *dev = intel_crtc->base.dev;
3879 struct drm_i915_private *dev_priv = dev->dev_private;
3880
3881 mutex_lock(&dev->struct_mutex);
3882 dev_priv->mm.interruptible = false;
3883 (void) intel_overlay_switch_off(intel_crtc->overlay);
3884 dev_priv->mm.interruptible = true;
3885 mutex_unlock(&dev->struct_mutex);
3886 }
3887
3888 /* Let userspace switch the overlay on again. In most cases userspace
3889 * has to recompute where to put it anyway.
3890 */
3891 }
3892
3893 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3894 {
3895 struct drm_device *dev = crtc->dev;
3896 struct drm_i915_private *dev_priv = dev->dev_private;
3897 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3898 int pipe = intel_crtc->pipe;
3899 int plane = intel_crtc->plane;
3900
3901 drm_vblank_on(dev, pipe);
3902
3903 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3904 intel_enable_planes(crtc);
3905 intel_crtc_update_cursor(crtc, true);
3906 intel_crtc_dpms_overlay(intel_crtc, true);
3907
3908 hsw_enable_ips(intel_crtc);
3909
3910 mutex_lock(&dev->struct_mutex);
3911 intel_update_fbc(dev);
3912 mutex_unlock(&dev->struct_mutex);
3913
3914 /*
3915 * FIXME: Once we grow proper nuclear flip support out of this we need
3916 * to compute the mask of flip planes precisely. For the time being
3917 * consider this a flip from a NULL plane.
3918 */
3919 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3920 }
3921
3922 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3923 {
3924 struct drm_device *dev = crtc->dev;
3925 struct drm_i915_private *dev_priv = dev->dev_private;
3926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3927 int pipe = intel_crtc->pipe;
3928 int plane = intel_crtc->plane;
3929
3930 intel_crtc_wait_for_pending_flips(crtc);
3931
3932 if (dev_priv->fbc.plane == plane)
3933 intel_disable_fbc(dev);
3934
3935 hsw_disable_ips(intel_crtc);
3936
3937 intel_crtc_dpms_overlay(intel_crtc, false);
3938 intel_crtc_update_cursor(crtc, false);
3939 intel_disable_planes(crtc);
3940 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3941
3942 /*
3943 * FIXME: Once we grow proper nuclear flip support out of this we need
3944 * to compute the mask of flip planes precisely. For the time being
3945 * consider this a flip to a NULL plane.
3946 */
3947 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3948
3949 drm_vblank_off(dev, pipe);
3950 }
3951
3952 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3953 {
3954 struct drm_device *dev = crtc->dev;
3955 struct drm_i915_private *dev_priv = dev->dev_private;
3956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3957 struct intel_encoder *encoder;
3958 int pipe = intel_crtc->pipe;
3959 enum plane plane = intel_crtc->plane;
3960
3961 WARN_ON(!crtc->enabled);
3962
3963 if (intel_crtc->active)
3964 return;
3965
3966 if (intel_crtc->config.has_pch_encoder)
3967 intel_prepare_shared_dpll(intel_crtc);
3968
3969 if (intel_crtc->config.has_dp_encoder)
3970 intel_dp_set_m_n(intel_crtc);
3971
3972 intel_set_pipe_timings(intel_crtc);
3973
3974 if (intel_crtc->config.has_pch_encoder) {
3975 intel_cpu_transcoder_set_m_n(intel_crtc,
3976 &intel_crtc->config.fdi_m_n);
3977 }
3978
3979 ironlake_set_pipeconf(crtc);
3980
3981 /* Set up the display plane register */
3982 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
3983 POSTING_READ(DSPCNTR(plane));
3984
3985 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
3986 crtc->x, crtc->y);
3987
3988 intel_crtc->active = true;
3989
3990 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3991 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3992
3993 for_each_encoder_on_crtc(dev, crtc, encoder)
3994 if (encoder->pre_enable)
3995 encoder->pre_enable(encoder);
3996
3997 if (intel_crtc->config.has_pch_encoder) {
3998 /* Note: FDI PLL enabling _must_ be done before we enable the
3999 * cpu pipes, hence this is separate from all the other fdi/pch
4000 * enabling. */
4001 ironlake_fdi_pll_enable(intel_crtc);
4002 } else {
4003 assert_fdi_tx_disabled(dev_priv, pipe);
4004 assert_fdi_rx_disabled(dev_priv, pipe);
4005 }
4006
4007 ironlake_pfit_enable(intel_crtc);
4008
4009 /*
4010 * On ILK+ LUT must be loaded before the pipe is running but with
4011 * clocks enabled
4012 */
4013 intel_crtc_load_lut(crtc);
4014
4015 intel_update_watermarks(crtc);
4016 intel_enable_pipe(intel_crtc);
4017
4018 if (intel_crtc->config.has_pch_encoder)
4019 ironlake_pch_enable(crtc);
4020
4021 for_each_encoder_on_crtc(dev, crtc, encoder)
4022 encoder->enable(encoder);
4023
4024 if (HAS_PCH_CPT(dev))
4025 cpt_verify_modeset(dev, intel_crtc->pipe);
4026
4027 intel_crtc_enable_planes(crtc);
4028 }
4029
4030 /* IPS only exists on ULT machines and is tied to pipe A. */
4031 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4032 {
4033 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4034 }
4035
4036 /*
4037 * This implements the workaround described in the "notes" section of the mode
4038 * set sequence documentation. When going from no pipes or single pipe to
4039 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4040 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4041 */
4042 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4043 {
4044 struct drm_device *dev = crtc->base.dev;
4045 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4046
4047 /* We want to get the other_active_crtc only if there's only 1 other
4048 * active crtc. */
4049 for_each_intel_crtc(dev, crtc_it) {
4050 if (!crtc_it->active || crtc_it == crtc)
4051 continue;
4052
4053 if (other_active_crtc)
4054 return;
4055
4056 other_active_crtc = crtc_it;
4057 }
4058 if (!other_active_crtc)
4059 return;
4060
4061 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4062 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4063 }
4064
4065 static void haswell_crtc_enable(struct drm_crtc *crtc)
4066 {
4067 struct drm_device *dev = crtc->dev;
4068 struct drm_i915_private *dev_priv = dev->dev_private;
4069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4070 struct intel_encoder *encoder;
4071 int pipe = intel_crtc->pipe;
4072 enum plane plane = intel_crtc->plane;
4073
4074 WARN_ON(!crtc->enabled);
4075
4076 if (intel_crtc->active)
4077 return;
4078
4079 if (intel_crtc->config.has_dp_encoder)
4080 intel_dp_set_m_n(intel_crtc);
4081
4082 intel_set_pipe_timings(intel_crtc);
4083
4084 if (intel_crtc->config.has_pch_encoder) {
4085 intel_cpu_transcoder_set_m_n(intel_crtc,
4086 &intel_crtc->config.fdi_m_n);
4087 }
4088
4089 haswell_set_pipeconf(crtc);
4090
4091 intel_set_pipe_csc(crtc);
4092
4093 /* Set up the display plane register */
4094 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
4095 POSTING_READ(DSPCNTR(plane));
4096
4097 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4098 crtc->x, crtc->y);
4099
4100 intel_crtc->active = true;
4101
4102 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4103 if (intel_crtc->config.has_pch_encoder)
4104 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4105
4106 if (intel_crtc->config.has_pch_encoder)
4107 dev_priv->display.fdi_link_train(crtc);
4108
4109 for_each_encoder_on_crtc(dev, crtc, encoder)
4110 if (encoder->pre_enable)
4111 encoder->pre_enable(encoder);
4112
4113 intel_ddi_enable_pipe_clock(intel_crtc);
4114
4115 ironlake_pfit_enable(intel_crtc);
4116
4117 /*
4118 * On ILK+ LUT must be loaded before the pipe is running but with
4119 * clocks enabled
4120 */
4121 intel_crtc_load_lut(crtc);
4122
4123 intel_ddi_set_pipe_settings(crtc);
4124 intel_ddi_enable_transcoder_func(crtc);
4125
4126 intel_update_watermarks(crtc);
4127 intel_enable_pipe(intel_crtc);
4128
4129 if (intel_crtc->config.has_pch_encoder)
4130 lpt_pch_enable(crtc);
4131
4132 for_each_encoder_on_crtc(dev, crtc, encoder) {
4133 encoder->enable(encoder);
4134 intel_opregion_notify_encoder(encoder, true);
4135 }
4136
4137 /* If we change the relative order between pipe/planes enabling, we need
4138 * to change the workaround. */
4139 haswell_mode_set_planes_workaround(intel_crtc);
4140 intel_crtc_enable_planes(crtc);
4141 }
4142
4143 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4144 {
4145 struct drm_device *dev = crtc->base.dev;
4146 struct drm_i915_private *dev_priv = dev->dev_private;
4147 int pipe = crtc->pipe;
4148
4149 /* To avoid upsetting the power well on haswell only disable the pfit if
4150 * it's in use. The hw state code will make sure we get this right. */
4151 if (crtc->config.pch_pfit.enabled) {
4152 I915_WRITE(PF_CTL(pipe), 0);
4153 I915_WRITE(PF_WIN_POS(pipe), 0);
4154 I915_WRITE(PF_WIN_SZ(pipe), 0);
4155 }
4156 }
4157
4158 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4159 {
4160 struct drm_device *dev = crtc->dev;
4161 struct drm_i915_private *dev_priv = dev->dev_private;
4162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4163 struct intel_encoder *encoder;
4164 int pipe = intel_crtc->pipe;
4165 u32 reg, temp;
4166
4167 if (!intel_crtc->active)
4168 return;
4169
4170 intel_crtc_disable_planes(crtc);
4171
4172 for_each_encoder_on_crtc(dev, crtc, encoder)
4173 encoder->disable(encoder);
4174
4175 if (intel_crtc->config.has_pch_encoder)
4176 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4177
4178 intel_disable_pipe(dev_priv, pipe);
4179
4180 ironlake_pfit_disable(intel_crtc);
4181
4182 for_each_encoder_on_crtc(dev, crtc, encoder)
4183 if (encoder->post_disable)
4184 encoder->post_disable(encoder);
4185
4186 if (intel_crtc->config.has_pch_encoder) {
4187 ironlake_fdi_disable(crtc);
4188
4189 ironlake_disable_pch_transcoder(dev_priv, pipe);
4190 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4191
4192 if (HAS_PCH_CPT(dev)) {
4193 /* disable TRANS_DP_CTL */
4194 reg = TRANS_DP_CTL(pipe);
4195 temp = I915_READ(reg);
4196 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4197 TRANS_DP_PORT_SEL_MASK);
4198 temp |= TRANS_DP_PORT_SEL_NONE;
4199 I915_WRITE(reg, temp);
4200
4201 /* disable DPLL_SEL */
4202 temp = I915_READ(PCH_DPLL_SEL);
4203 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4204 I915_WRITE(PCH_DPLL_SEL, temp);
4205 }
4206
4207 /* disable PCH DPLL */
4208 intel_disable_shared_dpll(intel_crtc);
4209
4210 ironlake_fdi_pll_disable(intel_crtc);
4211 }
4212
4213 intel_crtc->active = false;
4214 intel_update_watermarks(crtc);
4215
4216 mutex_lock(&dev->struct_mutex);
4217 intel_update_fbc(dev);
4218 mutex_unlock(&dev->struct_mutex);
4219 }
4220
4221 static void haswell_crtc_disable(struct drm_crtc *crtc)
4222 {
4223 struct drm_device *dev = crtc->dev;
4224 struct drm_i915_private *dev_priv = dev->dev_private;
4225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4226 struct intel_encoder *encoder;
4227 int pipe = intel_crtc->pipe;
4228 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4229
4230 if (!intel_crtc->active)
4231 return;
4232
4233 intel_crtc_disable_planes(crtc);
4234
4235 for_each_encoder_on_crtc(dev, crtc, encoder) {
4236 intel_opregion_notify_encoder(encoder, false);
4237 encoder->disable(encoder);
4238 }
4239
4240 if (intel_crtc->config.has_pch_encoder)
4241 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4242 intel_disable_pipe(dev_priv, pipe);
4243
4244 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4245
4246 ironlake_pfit_disable(intel_crtc);
4247
4248 intel_ddi_disable_pipe_clock(intel_crtc);
4249
4250 for_each_encoder_on_crtc(dev, crtc, encoder)
4251 if (encoder->post_disable)
4252 encoder->post_disable(encoder);
4253
4254 if (intel_crtc->config.has_pch_encoder) {
4255 lpt_disable_pch_transcoder(dev_priv);
4256 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4257 intel_ddi_fdi_disable(crtc);
4258 }
4259
4260 intel_crtc->active = false;
4261 intel_update_watermarks(crtc);
4262
4263 mutex_lock(&dev->struct_mutex);
4264 intel_update_fbc(dev);
4265 mutex_unlock(&dev->struct_mutex);
4266 }
4267
4268 static void ironlake_crtc_off(struct drm_crtc *crtc)
4269 {
4270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4271 intel_put_shared_dpll(intel_crtc);
4272 }
4273
4274 static void haswell_crtc_off(struct drm_crtc *crtc)
4275 {
4276 intel_ddi_put_crtc_pll(crtc);
4277 }
4278
4279 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4280 {
4281 struct drm_device *dev = crtc->base.dev;
4282 struct drm_i915_private *dev_priv = dev->dev_private;
4283 struct intel_crtc_config *pipe_config = &crtc->config;
4284
4285 if (!crtc->config.gmch_pfit.control)
4286 return;
4287
4288 /*
4289 * The panel fitter should only be adjusted whilst the pipe is disabled,
4290 * according to register description and PRM.
4291 */
4292 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4293 assert_pipe_disabled(dev_priv, crtc->pipe);
4294
4295 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4296 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4297
4298 /* Border color in case we don't scale up to the full screen. Black by
4299 * default, change to something else for debugging. */
4300 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4301 }
4302
4303 #define for_each_power_domain(domain, mask) \
4304 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4305 if ((1 << (domain)) & (mask))
4306
4307 enum intel_display_power_domain
4308 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4309 {
4310 struct drm_device *dev = intel_encoder->base.dev;
4311 struct intel_digital_port *intel_dig_port;
4312
4313 switch (intel_encoder->type) {
4314 case INTEL_OUTPUT_UNKNOWN:
4315 /* Only DDI platforms should ever use this output type */
4316 WARN_ON_ONCE(!HAS_DDI(dev));
4317 case INTEL_OUTPUT_DISPLAYPORT:
4318 case INTEL_OUTPUT_HDMI:
4319 case INTEL_OUTPUT_EDP:
4320 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4321 switch (intel_dig_port->port) {
4322 case PORT_A:
4323 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4324 case PORT_B:
4325 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4326 case PORT_C:
4327 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4328 case PORT_D:
4329 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4330 default:
4331 WARN_ON_ONCE(1);
4332 return POWER_DOMAIN_PORT_OTHER;
4333 }
4334 case INTEL_OUTPUT_ANALOG:
4335 return POWER_DOMAIN_PORT_CRT;
4336 case INTEL_OUTPUT_DSI:
4337 return POWER_DOMAIN_PORT_DSI;
4338 default:
4339 return POWER_DOMAIN_PORT_OTHER;
4340 }
4341 }
4342
4343 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4344 {
4345 struct drm_device *dev = crtc->dev;
4346 struct intel_encoder *intel_encoder;
4347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4348 enum pipe pipe = intel_crtc->pipe;
4349 unsigned long mask;
4350 enum transcoder transcoder;
4351
4352 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4353
4354 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4355 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4356 if (intel_crtc->config.pch_pfit.enabled ||
4357 intel_crtc->config.pch_pfit.force_thru)
4358 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4359
4360 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4361 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4362
4363 return mask;
4364 }
4365
4366 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4367 bool enable)
4368 {
4369 if (dev_priv->power_domains.init_power_on == enable)
4370 return;
4371
4372 if (enable)
4373 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4374 else
4375 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4376
4377 dev_priv->power_domains.init_power_on = enable;
4378 }
4379
4380 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4381 {
4382 struct drm_i915_private *dev_priv = dev->dev_private;
4383 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4384 struct intel_crtc *crtc;
4385
4386 /*
4387 * First get all needed power domains, then put all unneeded, to avoid
4388 * any unnecessary toggling of the power wells.
4389 */
4390 for_each_intel_crtc(dev, crtc) {
4391 enum intel_display_power_domain domain;
4392
4393 if (!crtc->base.enabled)
4394 continue;
4395
4396 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4397
4398 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4399 intel_display_power_get(dev_priv, domain);
4400 }
4401
4402 for_each_intel_crtc(dev, crtc) {
4403 enum intel_display_power_domain domain;
4404
4405 for_each_power_domain(domain, crtc->enabled_power_domains)
4406 intel_display_power_put(dev_priv, domain);
4407
4408 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4409 }
4410
4411 intel_display_set_init_power(dev_priv, false);
4412 }
4413
4414 /* returns HPLL frequency in kHz */
4415 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4416 {
4417 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4418
4419 /* Obtain SKU information */
4420 mutex_lock(&dev_priv->dpio_lock);
4421 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4422 CCK_FUSE_HPLL_FREQ_MASK;
4423 mutex_unlock(&dev_priv->dpio_lock);
4424
4425 return vco_freq[hpll_freq] * 1000;
4426 }
4427
4428 static void vlv_update_cdclk(struct drm_device *dev)
4429 {
4430 struct drm_i915_private *dev_priv = dev->dev_private;
4431
4432 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4433 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4434 dev_priv->vlv_cdclk_freq);
4435
4436 /*
4437 * Program the gmbus_freq based on the cdclk frequency.
4438 * BSpec erroneously claims we should aim for 4MHz, but
4439 * in fact 1MHz is the correct frequency.
4440 */
4441 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4442 }
4443
4444 /* Adjust CDclk dividers to allow high res or save power if possible */
4445 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4446 {
4447 struct drm_i915_private *dev_priv = dev->dev_private;
4448 u32 val, cmd;
4449
4450 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4451
4452 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4453 cmd = 2;
4454 else if (cdclk == 266667)
4455 cmd = 1;
4456 else
4457 cmd = 0;
4458
4459 mutex_lock(&dev_priv->rps.hw_lock);
4460 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4461 val &= ~DSPFREQGUAR_MASK;
4462 val |= (cmd << DSPFREQGUAR_SHIFT);
4463 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4464 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4465 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4466 50)) {
4467 DRM_ERROR("timed out waiting for CDclk change\n");
4468 }
4469 mutex_unlock(&dev_priv->rps.hw_lock);
4470
4471 if (cdclk == 400000) {
4472 u32 divider, vco;
4473
4474 vco = valleyview_get_vco(dev_priv);
4475 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4476
4477 mutex_lock(&dev_priv->dpio_lock);
4478 /* adjust cdclk divider */
4479 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4480 val &= ~DISPLAY_FREQUENCY_VALUES;
4481 val |= divider;
4482 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4483
4484 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4485 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4486 50))
4487 DRM_ERROR("timed out waiting for CDclk change\n");
4488 mutex_unlock(&dev_priv->dpio_lock);
4489 }
4490
4491 mutex_lock(&dev_priv->dpio_lock);
4492 /* adjust self-refresh exit latency value */
4493 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4494 val &= ~0x7f;
4495
4496 /*
4497 * For high bandwidth configs, we set a higher latency in the bunit
4498 * so that the core display fetch happens in time to avoid underruns.
4499 */
4500 if (cdclk == 400000)
4501 val |= 4500 / 250; /* 4.5 usec */
4502 else
4503 val |= 3000 / 250; /* 3.0 usec */
4504 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4505 mutex_unlock(&dev_priv->dpio_lock);
4506
4507 vlv_update_cdclk(dev);
4508 }
4509
4510 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4511 int max_pixclk)
4512 {
4513 int vco = valleyview_get_vco(dev_priv);
4514 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4515
4516 /*
4517 * Really only a few cases to deal with, as only 4 CDclks are supported:
4518 * 200MHz
4519 * 267MHz
4520 * 320/333MHz (depends on HPLL freq)
4521 * 400MHz
4522 * So we check to see whether we're above 90% of the lower bin and
4523 * adjust if needed.
4524 *
4525 * We seem to get an unstable or solid color picture at 200MHz.
4526 * Not sure what's wrong. For now use 200MHz only when all pipes
4527 * are off.
4528 */
4529 if (max_pixclk > freq_320*9/10)
4530 return 400000;
4531 else if (max_pixclk > 266667*9/10)
4532 return freq_320;
4533 else if (max_pixclk > 0)
4534 return 266667;
4535 else
4536 return 200000;
4537 }
4538
4539 /* compute the max pixel clock for new configuration */
4540 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4541 {
4542 struct drm_device *dev = dev_priv->dev;
4543 struct intel_crtc *intel_crtc;
4544 int max_pixclk = 0;
4545
4546 for_each_intel_crtc(dev, intel_crtc) {
4547 if (intel_crtc->new_enabled)
4548 max_pixclk = max(max_pixclk,
4549 intel_crtc->new_config->adjusted_mode.crtc_clock);
4550 }
4551
4552 return max_pixclk;
4553 }
4554
4555 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4556 unsigned *prepare_pipes)
4557 {
4558 struct drm_i915_private *dev_priv = dev->dev_private;
4559 struct intel_crtc *intel_crtc;
4560 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4561
4562 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4563 dev_priv->vlv_cdclk_freq)
4564 return;
4565
4566 /* disable/enable all currently active pipes while we change cdclk */
4567 for_each_intel_crtc(dev, intel_crtc)
4568 if (intel_crtc->base.enabled)
4569 *prepare_pipes |= (1 << intel_crtc->pipe);
4570 }
4571
4572 static void valleyview_modeset_global_resources(struct drm_device *dev)
4573 {
4574 struct drm_i915_private *dev_priv = dev->dev_private;
4575 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4576 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4577
4578 if (req_cdclk != dev_priv->vlv_cdclk_freq)
4579 valleyview_set_cdclk(dev, req_cdclk);
4580 modeset_update_crtc_power_domains(dev);
4581 }
4582
4583 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4584 {
4585 struct drm_device *dev = crtc->dev;
4586 struct drm_i915_private *dev_priv = dev->dev_private;
4587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4588 struct intel_encoder *encoder;
4589 int pipe = intel_crtc->pipe;
4590 int plane = intel_crtc->plane;
4591 bool is_dsi;
4592 u32 dspcntr;
4593
4594 WARN_ON(!crtc->enabled);
4595
4596 if (intel_crtc->active)
4597 return;
4598
4599 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4600
4601 if (!is_dsi && !IS_CHERRYVIEW(dev))
4602 vlv_prepare_pll(intel_crtc);
4603
4604 /* Set up the display plane register */
4605 dspcntr = DISPPLANE_GAMMA_ENABLE;
4606
4607 if (intel_crtc->config.has_dp_encoder)
4608 intel_dp_set_m_n(intel_crtc);
4609
4610 intel_set_pipe_timings(intel_crtc);
4611
4612 /* pipesrc and dspsize control the size that is scaled from,
4613 * which should always be the user's requested size.
4614 */
4615 I915_WRITE(DSPSIZE(plane),
4616 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4617 (intel_crtc->config.pipe_src_w - 1));
4618 I915_WRITE(DSPPOS(plane), 0);
4619
4620 i9xx_set_pipeconf(intel_crtc);
4621
4622 I915_WRITE(DSPCNTR(plane), dspcntr);
4623 POSTING_READ(DSPCNTR(plane));
4624
4625 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4626 crtc->x, crtc->y);
4627
4628 intel_crtc->active = true;
4629
4630 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4631
4632 for_each_encoder_on_crtc(dev, crtc, encoder)
4633 if (encoder->pre_pll_enable)
4634 encoder->pre_pll_enable(encoder);
4635
4636 if (!is_dsi) {
4637 if (IS_CHERRYVIEW(dev))
4638 chv_enable_pll(intel_crtc);
4639 else
4640 vlv_enable_pll(intel_crtc);
4641 }
4642
4643 for_each_encoder_on_crtc(dev, crtc, encoder)
4644 if (encoder->pre_enable)
4645 encoder->pre_enable(encoder);
4646
4647 i9xx_pfit_enable(intel_crtc);
4648
4649 intel_crtc_load_lut(crtc);
4650
4651 intel_update_watermarks(crtc);
4652 intel_enable_pipe(intel_crtc);
4653
4654 for_each_encoder_on_crtc(dev, crtc, encoder)
4655 encoder->enable(encoder);
4656
4657 intel_crtc_enable_planes(crtc);
4658
4659 /* Underruns don't raise interrupts, so check manually. */
4660 i9xx_check_fifo_underruns(dev);
4661 }
4662
4663 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4664 {
4665 struct drm_device *dev = crtc->base.dev;
4666 struct drm_i915_private *dev_priv = dev->dev_private;
4667
4668 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4669 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4670 }
4671
4672 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4673 {
4674 struct drm_device *dev = crtc->dev;
4675 struct drm_i915_private *dev_priv = dev->dev_private;
4676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4677 struct intel_encoder *encoder;
4678 int pipe = intel_crtc->pipe;
4679 int plane = intel_crtc->plane;
4680 u32 dspcntr;
4681
4682 WARN_ON(!crtc->enabled);
4683
4684 if (intel_crtc->active)
4685 return;
4686
4687 i9xx_set_pll_dividers(intel_crtc);
4688
4689 /* Set up the display plane register */
4690 dspcntr = DISPPLANE_GAMMA_ENABLE;
4691
4692 if (pipe == 0)
4693 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4694 else
4695 dspcntr |= DISPPLANE_SEL_PIPE_B;
4696
4697 if (intel_crtc->config.has_dp_encoder)
4698 intel_dp_set_m_n(intel_crtc);
4699
4700 intel_set_pipe_timings(intel_crtc);
4701
4702 /* pipesrc and dspsize control the size that is scaled from,
4703 * which should always be the user's requested size.
4704 */
4705 I915_WRITE(DSPSIZE(plane),
4706 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4707 (intel_crtc->config.pipe_src_w - 1));
4708 I915_WRITE(DSPPOS(plane), 0);
4709
4710 i9xx_set_pipeconf(intel_crtc);
4711
4712 I915_WRITE(DSPCNTR(plane), dspcntr);
4713 POSTING_READ(DSPCNTR(plane));
4714
4715 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4716 crtc->x, crtc->y);
4717
4718 intel_crtc->active = true;
4719
4720 if (!IS_GEN2(dev))
4721 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4722
4723 for_each_encoder_on_crtc(dev, crtc, encoder)
4724 if (encoder->pre_enable)
4725 encoder->pre_enable(encoder);
4726
4727 i9xx_enable_pll(intel_crtc);
4728
4729 i9xx_pfit_enable(intel_crtc);
4730
4731 intel_crtc_load_lut(crtc);
4732
4733 intel_update_watermarks(crtc);
4734 intel_enable_pipe(intel_crtc);
4735
4736 for_each_encoder_on_crtc(dev, crtc, encoder)
4737 encoder->enable(encoder);
4738
4739 intel_crtc_enable_planes(crtc);
4740
4741 /*
4742 * Gen2 reports pipe underruns whenever all planes are disabled.
4743 * So don't enable underrun reporting before at least some planes
4744 * are enabled.
4745 * FIXME: Need to fix the logic to work when we turn off all planes
4746 * but leave the pipe running.
4747 */
4748 if (IS_GEN2(dev))
4749 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4750
4751 /* Underruns don't raise interrupts, so check manually. */
4752 i9xx_check_fifo_underruns(dev);
4753 }
4754
4755 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4756 {
4757 struct drm_device *dev = crtc->base.dev;
4758 struct drm_i915_private *dev_priv = dev->dev_private;
4759
4760 if (!crtc->config.gmch_pfit.control)
4761 return;
4762
4763 assert_pipe_disabled(dev_priv, crtc->pipe);
4764
4765 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4766 I915_READ(PFIT_CONTROL));
4767 I915_WRITE(PFIT_CONTROL, 0);
4768 }
4769
4770 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4771 {
4772 struct drm_device *dev = crtc->dev;
4773 struct drm_i915_private *dev_priv = dev->dev_private;
4774 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4775 struct intel_encoder *encoder;
4776 int pipe = intel_crtc->pipe;
4777
4778 if (!intel_crtc->active)
4779 return;
4780
4781 /*
4782 * Gen2 reports pipe underruns whenever all planes are disabled.
4783 * So diasble underrun reporting before all the planes get disabled.
4784 * FIXME: Need to fix the logic to work when we turn off all planes
4785 * but leave the pipe running.
4786 */
4787 if (IS_GEN2(dev))
4788 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4789
4790 /*
4791 * Vblank time updates from the shadow to live plane control register
4792 * are blocked if the memory self-refresh mode is active at that
4793 * moment. So to make sure the plane gets truly disabled, disable
4794 * first the self-refresh mode. The self-refresh enable bit in turn
4795 * will be checked/applied by the HW only at the next frame start
4796 * event which is after the vblank start event, so we need to have a
4797 * wait-for-vblank between disabling the plane and the pipe.
4798 */
4799 intel_set_memory_cxsr(dev_priv, false);
4800 intel_crtc_disable_planes(crtc);
4801
4802 for_each_encoder_on_crtc(dev, crtc, encoder)
4803 encoder->disable(encoder);
4804
4805 /*
4806 * On gen2 planes are double buffered but the pipe isn't, so we must
4807 * wait for planes to fully turn off before disabling the pipe.
4808 * We also need to wait on all gmch platforms because of the
4809 * self-refresh mode constraint explained above.
4810 */
4811 intel_wait_for_vblank(dev, pipe);
4812
4813 intel_disable_pipe(dev_priv, pipe);
4814
4815 i9xx_pfit_disable(intel_crtc);
4816
4817 for_each_encoder_on_crtc(dev, crtc, encoder)
4818 if (encoder->post_disable)
4819 encoder->post_disable(encoder);
4820
4821 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4822 if (IS_CHERRYVIEW(dev))
4823 chv_disable_pll(dev_priv, pipe);
4824 else if (IS_VALLEYVIEW(dev))
4825 vlv_disable_pll(dev_priv, pipe);
4826 else
4827 i9xx_disable_pll(dev_priv, pipe);
4828 }
4829
4830 if (!IS_GEN2(dev))
4831 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4832
4833 intel_crtc->active = false;
4834 intel_update_watermarks(crtc);
4835
4836 mutex_lock(&dev->struct_mutex);
4837 intel_update_fbc(dev);
4838 mutex_unlock(&dev->struct_mutex);
4839 }
4840
4841 static void i9xx_crtc_off(struct drm_crtc *crtc)
4842 {
4843 }
4844
4845 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4846 bool enabled)
4847 {
4848 struct drm_device *dev = crtc->dev;
4849 struct drm_i915_master_private *master_priv;
4850 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4851 int pipe = intel_crtc->pipe;
4852
4853 if (!dev->primary->master)
4854 return;
4855
4856 master_priv = dev->primary->master->driver_priv;
4857 if (!master_priv->sarea_priv)
4858 return;
4859
4860 switch (pipe) {
4861 case 0:
4862 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4863 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4864 break;
4865 case 1:
4866 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4867 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4868 break;
4869 default:
4870 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4871 break;
4872 }
4873 }
4874
4875 /**
4876 * Sets the power management mode of the pipe and plane.
4877 */
4878 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4879 {
4880 struct drm_device *dev = crtc->dev;
4881 struct drm_i915_private *dev_priv = dev->dev_private;
4882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4883 struct intel_encoder *intel_encoder;
4884 enum intel_display_power_domain domain;
4885 unsigned long domains;
4886 bool enable = false;
4887
4888 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4889 enable |= intel_encoder->connectors_active;
4890
4891 if (enable) {
4892 if (!intel_crtc->active) {
4893 /*
4894 * FIXME: DDI plls and relevant code isn't converted
4895 * yet, so do runtime PM for DPMS only for all other
4896 * platforms for now.
4897 */
4898 if (!HAS_DDI(dev)) {
4899 domains = get_crtc_power_domains(crtc);
4900 for_each_power_domain(domain, domains)
4901 intel_display_power_get(dev_priv, domain);
4902 intel_crtc->enabled_power_domains = domains;
4903 }
4904
4905 dev_priv->display.crtc_enable(crtc);
4906 }
4907 } else {
4908 if (intel_crtc->active) {
4909 dev_priv->display.crtc_disable(crtc);
4910
4911 if (!HAS_DDI(dev)) {
4912 domains = intel_crtc->enabled_power_domains;
4913 for_each_power_domain(domain, domains)
4914 intel_display_power_put(dev_priv, domain);
4915 intel_crtc->enabled_power_domains = 0;
4916 }
4917 }
4918 }
4919
4920 intel_crtc_update_sarea(crtc, enable);
4921 }
4922
4923 static void intel_crtc_disable(struct drm_crtc *crtc)
4924 {
4925 struct drm_device *dev = crtc->dev;
4926 struct drm_connector *connector;
4927 struct drm_i915_private *dev_priv = dev->dev_private;
4928 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
4929 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4930
4931 /* crtc should still be enabled when we disable it. */
4932 WARN_ON(!crtc->enabled);
4933
4934 dev_priv->display.crtc_disable(crtc);
4935 intel_crtc_update_sarea(crtc, false);
4936 dev_priv->display.off(crtc);
4937
4938 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4939 assert_cursor_disabled(dev_priv, pipe);
4940 assert_pipe_disabled(dev->dev_private, pipe);
4941
4942 if (crtc->primary->fb) {
4943 mutex_lock(&dev->struct_mutex);
4944 intel_unpin_fb_obj(old_obj);
4945 i915_gem_track_fb(old_obj, NULL,
4946 INTEL_FRONTBUFFER_PRIMARY(pipe));
4947 mutex_unlock(&dev->struct_mutex);
4948 crtc->primary->fb = NULL;
4949 }
4950
4951 /* Update computed state. */
4952 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4953 if (!connector->encoder || !connector->encoder->crtc)
4954 continue;
4955
4956 if (connector->encoder->crtc != crtc)
4957 continue;
4958
4959 connector->dpms = DRM_MODE_DPMS_OFF;
4960 to_intel_encoder(connector->encoder)->connectors_active = false;
4961 }
4962 }
4963
4964 void intel_encoder_destroy(struct drm_encoder *encoder)
4965 {
4966 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4967
4968 drm_encoder_cleanup(encoder);
4969 kfree(intel_encoder);
4970 }
4971
4972 /* Simple dpms helper for encoders with just one connector, no cloning and only
4973 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4974 * state of the entire output pipe. */
4975 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4976 {
4977 if (mode == DRM_MODE_DPMS_ON) {
4978 encoder->connectors_active = true;
4979
4980 intel_crtc_update_dpms(encoder->base.crtc);
4981 } else {
4982 encoder->connectors_active = false;
4983
4984 intel_crtc_update_dpms(encoder->base.crtc);
4985 }
4986 }
4987
4988 /* Cross check the actual hw state with our own modeset state tracking (and it's
4989 * internal consistency). */
4990 static void intel_connector_check_state(struct intel_connector *connector)
4991 {
4992 if (connector->get_hw_state(connector)) {
4993 struct intel_encoder *encoder = connector->encoder;
4994 struct drm_crtc *crtc;
4995 bool encoder_enabled;
4996 enum pipe pipe;
4997
4998 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4999 connector->base.base.id,
5000 connector->base.name);
5001
5002 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5003 "wrong connector dpms state\n");
5004 WARN(connector->base.encoder != &encoder->base,
5005 "active connector not linked to encoder\n");
5006 WARN(!encoder->connectors_active,
5007 "encoder->connectors_active not set\n");
5008
5009 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5010 WARN(!encoder_enabled, "encoder not enabled\n");
5011 if (WARN_ON(!encoder->base.crtc))
5012 return;
5013
5014 crtc = encoder->base.crtc;
5015
5016 WARN(!crtc->enabled, "crtc not enabled\n");
5017 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5018 WARN(pipe != to_intel_crtc(crtc)->pipe,
5019 "encoder active on the wrong pipe\n");
5020 }
5021 }
5022
5023 /* Even simpler default implementation, if there's really no special case to
5024 * consider. */
5025 void intel_connector_dpms(struct drm_connector *connector, int mode)
5026 {
5027 /* All the simple cases only support two dpms states. */
5028 if (mode != DRM_MODE_DPMS_ON)
5029 mode = DRM_MODE_DPMS_OFF;
5030
5031 if (mode == connector->dpms)
5032 return;
5033
5034 connector->dpms = mode;
5035
5036 /* Only need to change hw state when actually enabled */
5037 if (connector->encoder)
5038 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5039
5040 intel_modeset_check_state(connector->dev);
5041 }
5042
5043 /* Simple connector->get_hw_state implementation for encoders that support only
5044 * one connector and no cloning and hence the encoder state determines the state
5045 * of the connector. */
5046 bool intel_connector_get_hw_state(struct intel_connector *connector)
5047 {
5048 enum pipe pipe = 0;
5049 struct intel_encoder *encoder = connector->encoder;
5050
5051 return encoder->get_hw_state(encoder, &pipe);
5052 }
5053
5054 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5055 struct intel_crtc_config *pipe_config)
5056 {
5057 struct drm_i915_private *dev_priv = dev->dev_private;
5058 struct intel_crtc *pipe_B_crtc =
5059 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5060
5061 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5062 pipe_name(pipe), pipe_config->fdi_lanes);
5063 if (pipe_config->fdi_lanes > 4) {
5064 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5065 pipe_name(pipe), pipe_config->fdi_lanes);
5066 return false;
5067 }
5068
5069 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5070 if (pipe_config->fdi_lanes > 2) {
5071 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5072 pipe_config->fdi_lanes);
5073 return false;
5074 } else {
5075 return true;
5076 }
5077 }
5078
5079 if (INTEL_INFO(dev)->num_pipes == 2)
5080 return true;
5081
5082 /* Ivybridge 3 pipe is really complicated */
5083 switch (pipe) {
5084 case PIPE_A:
5085 return true;
5086 case PIPE_B:
5087 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5088 pipe_config->fdi_lanes > 2) {
5089 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5090 pipe_name(pipe), pipe_config->fdi_lanes);
5091 return false;
5092 }
5093 return true;
5094 case PIPE_C:
5095 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5096 pipe_B_crtc->config.fdi_lanes <= 2) {
5097 if (pipe_config->fdi_lanes > 2) {
5098 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5099 pipe_name(pipe), pipe_config->fdi_lanes);
5100 return false;
5101 }
5102 } else {
5103 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5104 return false;
5105 }
5106 return true;
5107 default:
5108 BUG();
5109 }
5110 }
5111
5112 #define RETRY 1
5113 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5114 struct intel_crtc_config *pipe_config)
5115 {
5116 struct drm_device *dev = intel_crtc->base.dev;
5117 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5118 int lane, link_bw, fdi_dotclock;
5119 bool setup_ok, needs_recompute = false;
5120
5121 retry:
5122 /* FDI is a binary signal running at ~2.7GHz, encoding
5123 * each output octet as 10 bits. The actual frequency
5124 * is stored as a divider into a 100MHz clock, and the
5125 * mode pixel clock is stored in units of 1KHz.
5126 * Hence the bw of each lane in terms of the mode signal
5127 * is:
5128 */
5129 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5130
5131 fdi_dotclock = adjusted_mode->crtc_clock;
5132
5133 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5134 pipe_config->pipe_bpp);
5135
5136 pipe_config->fdi_lanes = lane;
5137
5138 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5139 link_bw, &pipe_config->fdi_m_n);
5140
5141 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5142 intel_crtc->pipe, pipe_config);
5143 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5144 pipe_config->pipe_bpp -= 2*3;
5145 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5146 pipe_config->pipe_bpp);
5147 needs_recompute = true;
5148 pipe_config->bw_constrained = true;
5149
5150 goto retry;
5151 }
5152
5153 if (needs_recompute)
5154 return RETRY;
5155
5156 return setup_ok ? 0 : -EINVAL;
5157 }
5158
5159 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5160 struct intel_crtc_config *pipe_config)
5161 {
5162 pipe_config->ips_enabled = i915.enable_ips &&
5163 hsw_crtc_supports_ips(crtc) &&
5164 pipe_config->pipe_bpp <= 24;
5165 }
5166
5167 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5168 struct intel_crtc_config *pipe_config)
5169 {
5170 struct drm_device *dev = crtc->base.dev;
5171 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5172
5173 /* FIXME should check pixel clock limits on all platforms */
5174 if (INTEL_INFO(dev)->gen < 4) {
5175 struct drm_i915_private *dev_priv = dev->dev_private;
5176 int clock_limit =
5177 dev_priv->display.get_display_clock_speed(dev);
5178
5179 /*
5180 * Enable pixel doubling when the dot clock
5181 * is > 90% of the (display) core speed.
5182 *
5183 * GDG double wide on either pipe,
5184 * otherwise pipe A only.
5185 */
5186 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5187 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5188 clock_limit *= 2;
5189 pipe_config->double_wide = true;
5190 }
5191
5192 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5193 return -EINVAL;
5194 }
5195
5196 /*
5197 * Pipe horizontal size must be even in:
5198 * - DVO ganged mode
5199 * - LVDS dual channel mode
5200 * - Double wide pipe
5201 */
5202 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5203 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5204 pipe_config->pipe_src_w &= ~1;
5205
5206 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5207 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5208 */
5209 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5210 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5211 return -EINVAL;
5212
5213 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5214 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5215 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5216 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5217 * for lvds. */
5218 pipe_config->pipe_bpp = 8*3;
5219 }
5220
5221 if (HAS_IPS(dev))
5222 hsw_compute_ips_config(crtc, pipe_config);
5223
5224 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
5225 * clock survives for now. */
5226 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5227 pipe_config->shared_dpll = crtc->config.shared_dpll;
5228
5229 if (pipe_config->has_pch_encoder)
5230 return ironlake_fdi_compute_config(crtc, pipe_config);
5231
5232 return 0;
5233 }
5234
5235 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5236 {
5237 struct drm_i915_private *dev_priv = dev->dev_private;
5238 int vco = valleyview_get_vco(dev_priv);
5239 u32 val;
5240 int divider;
5241
5242 mutex_lock(&dev_priv->dpio_lock);
5243 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5244 mutex_unlock(&dev_priv->dpio_lock);
5245
5246 divider = val & DISPLAY_FREQUENCY_VALUES;
5247
5248 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5249 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5250 "cdclk change in progress\n");
5251
5252 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5253 }
5254
5255 static int i945_get_display_clock_speed(struct drm_device *dev)
5256 {
5257 return 400000;
5258 }
5259
5260 static int i915_get_display_clock_speed(struct drm_device *dev)
5261 {
5262 return 333000;
5263 }
5264
5265 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5266 {
5267 return 200000;
5268 }
5269
5270 static int pnv_get_display_clock_speed(struct drm_device *dev)
5271 {
5272 u16 gcfgc = 0;
5273
5274 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5275
5276 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5277 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5278 return 267000;
5279 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5280 return 333000;
5281 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5282 return 444000;
5283 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5284 return 200000;
5285 default:
5286 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5287 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5288 return 133000;
5289 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5290 return 167000;
5291 }
5292 }
5293
5294 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5295 {
5296 u16 gcfgc = 0;
5297
5298 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5299
5300 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5301 return 133000;
5302 else {
5303 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5304 case GC_DISPLAY_CLOCK_333_MHZ:
5305 return 333000;
5306 default:
5307 case GC_DISPLAY_CLOCK_190_200_MHZ:
5308 return 190000;
5309 }
5310 }
5311 }
5312
5313 static int i865_get_display_clock_speed(struct drm_device *dev)
5314 {
5315 return 266000;
5316 }
5317
5318 static int i855_get_display_clock_speed(struct drm_device *dev)
5319 {
5320 u16 hpllcc = 0;
5321 /* Assume that the hardware is in the high speed state. This
5322 * should be the default.
5323 */
5324 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5325 case GC_CLOCK_133_200:
5326 case GC_CLOCK_100_200:
5327 return 200000;
5328 case GC_CLOCK_166_250:
5329 return 250000;
5330 case GC_CLOCK_100_133:
5331 return 133000;
5332 }
5333
5334 /* Shouldn't happen */
5335 return 0;
5336 }
5337
5338 static int i830_get_display_clock_speed(struct drm_device *dev)
5339 {
5340 return 133000;
5341 }
5342
5343 static void
5344 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5345 {
5346 while (*num > DATA_LINK_M_N_MASK ||
5347 *den > DATA_LINK_M_N_MASK) {
5348 *num >>= 1;
5349 *den >>= 1;
5350 }
5351 }
5352
5353 static void compute_m_n(unsigned int m, unsigned int n,
5354 uint32_t *ret_m, uint32_t *ret_n)
5355 {
5356 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5357 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5358 intel_reduce_m_n_ratio(ret_m, ret_n);
5359 }
5360
5361 void
5362 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5363 int pixel_clock, int link_clock,
5364 struct intel_link_m_n *m_n)
5365 {
5366 m_n->tu = 64;
5367
5368 compute_m_n(bits_per_pixel * pixel_clock,
5369 link_clock * nlanes * 8,
5370 &m_n->gmch_m, &m_n->gmch_n);
5371
5372 compute_m_n(pixel_clock, link_clock,
5373 &m_n->link_m, &m_n->link_n);
5374 }
5375
5376 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5377 {
5378 if (i915.panel_use_ssc >= 0)
5379 return i915.panel_use_ssc != 0;
5380 return dev_priv->vbt.lvds_use_ssc
5381 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5382 }
5383
5384 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5385 {
5386 struct drm_device *dev = crtc->dev;
5387 struct drm_i915_private *dev_priv = dev->dev_private;
5388 int refclk;
5389
5390 if (IS_VALLEYVIEW(dev)) {
5391 refclk = 100000;
5392 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5393 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5394 refclk = dev_priv->vbt.lvds_ssc_freq;
5395 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5396 } else if (!IS_GEN2(dev)) {
5397 refclk = 96000;
5398 } else {
5399 refclk = 48000;
5400 }
5401
5402 return refclk;
5403 }
5404
5405 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5406 {
5407 return (1 << dpll->n) << 16 | dpll->m2;
5408 }
5409
5410 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5411 {
5412 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5413 }
5414
5415 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5416 intel_clock_t *reduced_clock)
5417 {
5418 struct drm_device *dev = crtc->base.dev;
5419 u32 fp, fp2 = 0;
5420
5421 if (IS_PINEVIEW(dev)) {
5422 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5423 if (reduced_clock)
5424 fp2 = pnv_dpll_compute_fp(reduced_clock);
5425 } else {
5426 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5427 if (reduced_clock)
5428 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5429 }
5430
5431 crtc->config.dpll_hw_state.fp0 = fp;
5432
5433 crtc->lowfreq_avail = false;
5434 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5435 reduced_clock && i915.powersave) {
5436 crtc->config.dpll_hw_state.fp1 = fp2;
5437 crtc->lowfreq_avail = true;
5438 } else {
5439 crtc->config.dpll_hw_state.fp1 = fp;
5440 }
5441 }
5442
5443 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5444 pipe)
5445 {
5446 u32 reg_val;
5447
5448 /*
5449 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5450 * and set it to a reasonable value instead.
5451 */
5452 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5453 reg_val &= 0xffffff00;
5454 reg_val |= 0x00000030;
5455 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5456
5457 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5458 reg_val &= 0x8cffffff;
5459 reg_val = 0x8c000000;
5460 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5461
5462 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5463 reg_val &= 0xffffff00;
5464 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5465
5466 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5467 reg_val &= 0x00ffffff;
5468 reg_val |= 0xb0000000;
5469 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5470 }
5471
5472 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5473 struct intel_link_m_n *m_n)
5474 {
5475 struct drm_device *dev = crtc->base.dev;
5476 struct drm_i915_private *dev_priv = dev->dev_private;
5477 int pipe = crtc->pipe;
5478
5479 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5480 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5481 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5482 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5483 }
5484
5485 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5486 struct intel_link_m_n *m_n)
5487 {
5488 struct drm_device *dev = crtc->base.dev;
5489 struct drm_i915_private *dev_priv = dev->dev_private;
5490 int pipe = crtc->pipe;
5491 enum transcoder transcoder = crtc->config.cpu_transcoder;
5492
5493 if (INTEL_INFO(dev)->gen >= 5) {
5494 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5495 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5496 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5497 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5498 } else {
5499 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5500 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5501 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5502 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5503 }
5504 }
5505
5506 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5507 {
5508 if (crtc->config.has_pch_encoder)
5509 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5510 else
5511 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5512 }
5513
5514 static void vlv_update_pll(struct intel_crtc *crtc)
5515 {
5516 u32 dpll, dpll_md;
5517
5518 /*
5519 * Enable DPIO clock input. We should never disable the reference
5520 * clock for pipe B, since VGA hotplug / manual detection depends
5521 * on it.
5522 */
5523 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5524 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5525 /* We should never disable this, set it here for state tracking */
5526 if (crtc->pipe == PIPE_B)
5527 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5528 dpll |= DPLL_VCO_ENABLE;
5529 crtc->config.dpll_hw_state.dpll = dpll;
5530
5531 dpll_md = (crtc->config.pixel_multiplier - 1)
5532 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5533 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5534 }
5535
5536 static void vlv_prepare_pll(struct intel_crtc *crtc)
5537 {
5538 struct drm_device *dev = crtc->base.dev;
5539 struct drm_i915_private *dev_priv = dev->dev_private;
5540 int pipe = crtc->pipe;
5541 u32 mdiv;
5542 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5543 u32 coreclk, reg_val;
5544
5545 mutex_lock(&dev_priv->dpio_lock);
5546
5547 bestn = crtc->config.dpll.n;
5548 bestm1 = crtc->config.dpll.m1;
5549 bestm2 = crtc->config.dpll.m2;
5550 bestp1 = crtc->config.dpll.p1;
5551 bestp2 = crtc->config.dpll.p2;
5552
5553 /* See eDP HDMI DPIO driver vbios notes doc */
5554
5555 /* PLL B needs special handling */
5556 if (pipe == PIPE_B)
5557 vlv_pllb_recal_opamp(dev_priv, pipe);
5558
5559 /* Set up Tx target for periodic Rcomp update */
5560 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5561
5562 /* Disable target IRef on PLL */
5563 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5564 reg_val &= 0x00ffffff;
5565 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5566
5567 /* Disable fast lock */
5568 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5569
5570 /* Set idtafcrecal before PLL is enabled */
5571 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5572 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5573 mdiv |= ((bestn << DPIO_N_SHIFT));
5574 mdiv |= (1 << DPIO_K_SHIFT);
5575
5576 /*
5577 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5578 * but we don't support that).
5579 * Note: don't use the DAC post divider as it seems unstable.
5580 */
5581 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5582 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5583
5584 mdiv |= DPIO_ENABLE_CALIBRATION;
5585 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5586
5587 /* Set HBR and RBR LPF coefficients */
5588 if (crtc->config.port_clock == 162000 ||
5589 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5590 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5591 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5592 0x009f0003);
5593 else
5594 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5595 0x00d0000f);
5596
5597 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5598 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5599 /* Use SSC source */
5600 if (pipe == PIPE_A)
5601 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5602 0x0df40000);
5603 else
5604 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5605 0x0df70000);
5606 } else { /* HDMI or VGA */
5607 /* Use bend source */
5608 if (pipe == PIPE_A)
5609 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5610 0x0df70000);
5611 else
5612 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5613 0x0df40000);
5614 }
5615
5616 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5617 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5618 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5619 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5620 coreclk |= 0x01000000;
5621 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5622
5623 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5624 mutex_unlock(&dev_priv->dpio_lock);
5625 }
5626
5627 static void chv_update_pll(struct intel_crtc *crtc)
5628 {
5629 struct drm_device *dev = crtc->base.dev;
5630 struct drm_i915_private *dev_priv = dev->dev_private;
5631 int pipe = crtc->pipe;
5632 int dpll_reg = DPLL(crtc->pipe);
5633 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5634 u32 loopfilter, intcoeff;
5635 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5636 int refclk;
5637
5638 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5639 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5640 DPLL_VCO_ENABLE;
5641 if (pipe != PIPE_A)
5642 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5643
5644 crtc->config.dpll_hw_state.dpll_md =
5645 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5646
5647 bestn = crtc->config.dpll.n;
5648 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5649 bestm1 = crtc->config.dpll.m1;
5650 bestm2 = crtc->config.dpll.m2 >> 22;
5651 bestp1 = crtc->config.dpll.p1;
5652 bestp2 = crtc->config.dpll.p2;
5653
5654 /*
5655 * Enable Refclk and SSC
5656 */
5657 I915_WRITE(dpll_reg,
5658 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5659
5660 mutex_lock(&dev_priv->dpio_lock);
5661
5662 /* p1 and p2 divider */
5663 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5664 5 << DPIO_CHV_S1_DIV_SHIFT |
5665 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5666 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5667 1 << DPIO_CHV_K_DIV_SHIFT);
5668
5669 /* Feedback post-divider - m2 */
5670 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5671
5672 /* Feedback refclk divider - n and m1 */
5673 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5674 DPIO_CHV_M1_DIV_BY_2 |
5675 1 << DPIO_CHV_N_DIV_SHIFT);
5676
5677 /* M2 fraction division */
5678 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5679
5680 /* M2 fraction division enable */
5681 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5682 DPIO_CHV_FRAC_DIV_EN |
5683 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5684
5685 /* Loop filter */
5686 refclk = i9xx_get_refclk(&crtc->base, 0);
5687 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5688 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5689 if (refclk == 100000)
5690 intcoeff = 11;
5691 else if (refclk == 38400)
5692 intcoeff = 10;
5693 else
5694 intcoeff = 9;
5695 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5696 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5697
5698 /* AFC Recal */
5699 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5700 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5701 DPIO_AFC_RECAL);
5702
5703 mutex_unlock(&dev_priv->dpio_lock);
5704 }
5705
5706 static void i9xx_update_pll(struct intel_crtc *crtc,
5707 intel_clock_t *reduced_clock,
5708 int num_connectors)
5709 {
5710 struct drm_device *dev = crtc->base.dev;
5711 struct drm_i915_private *dev_priv = dev->dev_private;
5712 u32 dpll;
5713 bool is_sdvo;
5714 struct dpll *clock = &crtc->config.dpll;
5715
5716 i9xx_update_pll_dividers(crtc, reduced_clock);
5717
5718 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5719 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5720
5721 dpll = DPLL_VGA_MODE_DIS;
5722
5723 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5724 dpll |= DPLLB_MODE_LVDS;
5725 else
5726 dpll |= DPLLB_MODE_DAC_SERIAL;
5727
5728 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5729 dpll |= (crtc->config.pixel_multiplier - 1)
5730 << SDVO_MULTIPLIER_SHIFT_HIRES;
5731 }
5732
5733 if (is_sdvo)
5734 dpll |= DPLL_SDVO_HIGH_SPEED;
5735
5736 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5737 dpll |= DPLL_SDVO_HIGH_SPEED;
5738
5739 /* compute bitmask from p1 value */
5740 if (IS_PINEVIEW(dev))
5741 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5742 else {
5743 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5744 if (IS_G4X(dev) && reduced_clock)
5745 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5746 }
5747 switch (clock->p2) {
5748 case 5:
5749 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5750 break;
5751 case 7:
5752 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5753 break;
5754 case 10:
5755 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5756 break;
5757 case 14:
5758 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5759 break;
5760 }
5761 if (INTEL_INFO(dev)->gen >= 4)
5762 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5763
5764 if (crtc->config.sdvo_tv_clock)
5765 dpll |= PLL_REF_INPUT_TVCLKINBC;
5766 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5767 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5768 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5769 else
5770 dpll |= PLL_REF_INPUT_DREFCLK;
5771
5772 dpll |= DPLL_VCO_ENABLE;
5773 crtc->config.dpll_hw_state.dpll = dpll;
5774
5775 if (INTEL_INFO(dev)->gen >= 4) {
5776 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5777 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5778 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5779 }
5780 }
5781
5782 static void i8xx_update_pll(struct intel_crtc *crtc,
5783 intel_clock_t *reduced_clock,
5784 int num_connectors)
5785 {
5786 struct drm_device *dev = crtc->base.dev;
5787 struct drm_i915_private *dev_priv = dev->dev_private;
5788 u32 dpll;
5789 struct dpll *clock = &crtc->config.dpll;
5790
5791 i9xx_update_pll_dividers(crtc, reduced_clock);
5792
5793 dpll = DPLL_VGA_MODE_DIS;
5794
5795 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5796 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5797 } else {
5798 if (clock->p1 == 2)
5799 dpll |= PLL_P1_DIVIDE_BY_TWO;
5800 else
5801 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5802 if (clock->p2 == 4)
5803 dpll |= PLL_P2_DIVIDE_BY_4;
5804 }
5805
5806 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5807 dpll |= DPLL_DVO_2X_MODE;
5808
5809 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5810 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5811 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5812 else
5813 dpll |= PLL_REF_INPUT_DREFCLK;
5814
5815 dpll |= DPLL_VCO_ENABLE;
5816 crtc->config.dpll_hw_state.dpll = dpll;
5817 }
5818
5819 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5820 {
5821 struct drm_device *dev = intel_crtc->base.dev;
5822 struct drm_i915_private *dev_priv = dev->dev_private;
5823 enum pipe pipe = intel_crtc->pipe;
5824 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5825 struct drm_display_mode *adjusted_mode =
5826 &intel_crtc->config.adjusted_mode;
5827 uint32_t crtc_vtotal, crtc_vblank_end;
5828 int vsyncshift = 0;
5829
5830 /* We need to be careful not to changed the adjusted mode, for otherwise
5831 * the hw state checker will get angry at the mismatch. */
5832 crtc_vtotal = adjusted_mode->crtc_vtotal;
5833 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5834
5835 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5836 /* the chip adds 2 halflines automatically */
5837 crtc_vtotal -= 1;
5838 crtc_vblank_end -= 1;
5839
5840 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5841 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5842 else
5843 vsyncshift = adjusted_mode->crtc_hsync_start -
5844 adjusted_mode->crtc_htotal / 2;
5845 if (vsyncshift < 0)
5846 vsyncshift += adjusted_mode->crtc_htotal;
5847 }
5848
5849 if (INTEL_INFO(dev)->gen > 3)
5850 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5851
5852 I915_WRITE(HTOTAL(cpu_transcoder),
5853 (adjusted_mode->crtc_hdisplay - 1) |
5854 ((adjusted_mode->crtc_htotal - 1) << 16));
5855 I915_WRITE(HBLANK(cpu_transcoder),
5856 (adjusted_mode->crtc_hblank_start - 1) |
5857 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5858 I915_WRITE(HSYNC(cpu_transcoder),
5859 (adjusted_mode->crtc_hsync_start - 1) |
5860 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5861
5862 I915_WRITE(VTOTAL(cpu_transcoder),
5863 (adjusted_mode->crtc_vdisplay - 1) |
5864 ((crtc_vtotal - 1) << 16));
5865 I915_WRITE(VBLANK(cpu_transcoder),
5866 (adjusted_mode->crtc_vblank_start - 1) |
5867 ((crtc_vblank_end - 1) << 16));
5868 I915_WRITE(VSYNC(cpu_transcoder),
5869 (adjusted_mode->crtc_vsync_start - 1) |
5870 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5871
5872 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5873 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5874 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5875 * bits. */
5876 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5877 (pipe == PIPE_B || pipe == PIPE_C))
5878 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5879
5880 /* pipesrc controls the size that is scaled from, which should
5881 * always be the user's requested size.
5882 */
5883 I915_WRITE(PIPESRC(pipe),
5884 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5885 (intel_crtc->config.pipe_src_h - 1));
5886 }
5887
5888 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5889 struct intel_crtc_config *pipe_config)
5890 {
5891 struct drm_device *dev = crtc->base.dev;
5892 struct drm_i915_private *dev_priv = dev->dev_private;
5893 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5894 uint32_t tmp;
5895
5896 tmp = I915_READ(HTOTAL(cpu_transcoder));
5897 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5898 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5899 tmp = I915_READ(HBLANK(cpu_transcoder));
5900 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5901 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5902 tmp = I915_READ(HSYNC(cpu_transcoder));
5903 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5904 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5905
5906 tmp = I915_READ(VTOTAL(cpu_transcoder));
5907 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5908 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5909 tmp = I915_READ(VBLANK(cpu_transcoder));
5910 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5911 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5912 tmp = I915_READ(VSYNC(cpu_transcoder));
5913 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5914 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5915
5916 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5917 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5918 pipe_config->adjusted_mode.crtc_vtotal += 1;
5919 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5920 }
5921
5922 tmp = I915_READ(PIPESRC(crtc->pipe));
5923 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5924 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5925
5926 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5927 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5928 }
5929
5930 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5931 struct intel_crtc_config *pipe_config)
5932 {
5933 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5934 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5935 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5936 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5937
5938 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5939 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5940 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5941 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5942
5943 mode->flags = pipe_config->adjusted_mode.flags;
5944
5945 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5946 mode->flags |= pipe_config->adjusted_mode.flags;
5947 }
5948
5949 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5950 {
5951 struct drm_device *dev = intel_crtc->base.dev;
5952 struct drm_i915_private *dev_priv = dev->dev_private;
5953 uint32_t pipeconf;
5954
5955 pipeconf = 0;
5956
5957 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5958 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5959 pipeconf |= PIPECONF_ENABLE;
5960
5961 if (intel_crtc->config.double_wide)
5962 pipeconf |= PIPECONF_DOUBLE_WIDE;
5963
5964 /* only g4x and later have fancy bpc/dither controls */
5965 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5966 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5967 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5968 pipeconf |= PIPECONF_DITHER_EN |
5969 PIPECONF_DITHER_TYPE_SP;
5970
5971 switch (intel_crtc->config.pipe_bpp) {
5972 case 18:
5973 pipeconf |= PIPECONF_6BPC;
5974 break;
5975 case 24:
5976 pipeconf |= PIPECONF_8BPC;
5977 break;
5978 case 30:
5979 pipeconf |= PIPECONF_10BPC;
5980 break;
5981 default:
5982 /* Case prevented by intel_choose_pipe_bpp_dither. */
5983 BUG();
5984 }
5985 }
5986
5987 if (HAS_PIPE_CXSR(dev)) {
5988 if (intel_crtc->lowfreq_avail) {
5989 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5990 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5991 } else {
5992 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5993 }
5994 }
5995
5996 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5997 if (INTEL_INFO(dev)->gen < 4 ||
5998 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5999 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6000 else
6001 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6002 } else
6003 pipeconf |= PIPECONF_PROGRESSIVE;
6004
6005 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6006 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6007
6008 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6009 POSTING_READ(PIPECONF(intel_crtc->pipe));
6010 }
6011
6012 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6013 int x, int y,
6014 struct drm_framebuffer *fb)
6015 {
6016 struct drm_device *dev = crtc->dev;
6017 struct drm_i915_private *dev_priv = dev->dev_private;
6018 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6019 int refclk, num_connectors = 0;
6020 intel_clock_t clock, reduced_clock;
6021 bool ok, has_reduced_clock = false;
6022 bool is_lvds = false, is_dsi = false;
6023 struct intel_encoder *encoder;
6024 const intel_limit_t *limit;
6025
6026 for_each_encoder_on_crtc(dev, crtc, encoder) {
6027 switch (encoder->type) {
6028 case INTEL_OUTPUT_LVDS:
6029 is_lvds = true;
6030 break;
6031 case INTEL_OUTPUT_DSI:
6032 is_dsi = true;
6033 break;
6034 }
6035
6036 num_connectors++;
6037 }
6038
6039 if (is_dsi)
6040 return 0;
6041
6042 if (!intel_crtc->config.clock_set) {
6043 refclk = i9xx_get_refclk(crtc, num_connectors);
6044
6045 /*
6046 * Returns a set of divisors for the desired target clock with
6047 * the given refclk, or FALSE. The returned values represent
6048 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6049 * 2) / p1 / p2.
6050 */
6051 limit = intel_limit(crtc, refclk);
6052 ok = dev_priv->display.find_dpll(limit, crtc,
6053 intel_crtc->config.port_clock,
6054 refclk, NULL, &clock);
6055 if (!ok) {
6056 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6057 return -EINVAL;
6058 }
6059
6060 if (is_lvds && dev_priv->lvds_downclock_avail) {
6061 /*
6062 * Ensure we match the reduced clock's P to the target
6063 * clock. If the clocks don't match, we can't switch
6064 * the display clock by using the FP0/FP1. In such case
6065 * we will disable the LVDS downclock feature.
6066 */
6067 has_reduced_clock =
6068 dev_priv->display.find_dpll(limit, crtc,
6069 dev_priv->lvds_downclock,
6070 refclk, &clock,
6071 &reduced_clock);
6072 }
6073 /* Compat-code for transition, will disappear. */
6074 intel_crtc->config.dpll.n = clock.n;
6075 intel_crtc->config.dpll.m1 = clock.m1;
6076 intel_crtc->config.dpll.m2 = clock.m2;
6077 intel_crtc->config.dpll.p1 = clock.p1;
6078 intel_crtc->config.dpll.p2 = clock.p2;
6079 }
6080
6081 if (IS_GEN2(dev)) {
6082 i8xx_update_pll(intel_crtc,
6083 has_reduced_clock ? &reduced_clock : NULL,
6084 num_connectors);
6085 } else if (IS_CHERRYVIEW(dev)) {
6086 chv_update_pll(intel_crtc);
6087 } else if (IS_VALLEYVIEW(dev)) {
6088 vlv_update_pll(intel_crtc);
6089 } else {
6090 i9xx_update_pll(intel_crtc,
6091 has_reduced_clock ? &reduced_clock : NULL,
6092 num_connectors);
6093 }
6094
6095 return 0;
6096 }
6097
6098 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6099 struct intel_crtc_config *pipe_config)
6100 {
6101 struct drm_device *dev = crtc->base.dev;
6102 struct drm_i915_private *dev_priv = dev->dev_private;
6103 uint32_t tmp;
6104
6105 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6106 return;
6107
6108 tmp = I915_READ(PFIT_CONTROL);
6109 if (!(tmp & PFIT_ENABLE))
6110 return;
6111
6112 /* Check whether the pfit is attached to our pipe. */
6113 if (INTEL_INFO(dev)->gen < 4) {
6114 if (crtc->pipe != PIPE_B)
6115 return;
6116 } else {
6117 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6118 return;
6119 }
6120
6121 pipe_config->gmch_pfit.control = tmp;
6122 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6123 if (INTEL_INFO(dev)->gen < 5)
6124 pipe_config->gmch_pfit.lvds_border_bits =
6125 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6126 }
6127
6128 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6129 struct intel_crtc_config *pipe_config)
6130 {
6131 struct drm_device *dev = crtc->base.dev;
6132 struct drm_i915_private *dev_priv = dev->dev_private;
6133 int pipe = pipe_config->cpu_transcoder;
6134 intel_clock_t clock;
6135 u32 mdiv;
6136 int refclk = 100000;
6137
6138 mutex_lock(&dev_priv->dpio_lock);
6139 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6140 mutex_unlock(&dev_priv->dpio_lock);
6141
6142 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6143 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6144 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6145 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6146 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6147
6148 vlv_clock(refclk, &clock);
6149
6150 /* clock.dot is the fast clock */
6151 pipe_config->port_clock = clock.dot / 5;
6152 }
6153
6154 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6155 struct intel_plane_config *plane_config)
6156 {
6157 struct drm_device *dev = crtc->base.dev;
6158 struct drm_i915_private *dev_priv = dev->dev_private;
6159 u32 val, base, offset;
6160 int pipe = crtc->pipe, plane = crtc->plane;
6161 int fourcc, pixel_format;
6162 int aligned_height;
6163
6164 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6165 if (!crtc->base.primary->fb) {
6166 DRM_DEBUG_KMS("failed to alloc fb\n");
6167 return;
6168 }
6169
6170 val = I915_READ(DSPCNTR(plane));
6171
6172 if (INTEL_INFO(dev)->gen >= 4)
6173 if (val & DISPPLANE_TILED)
6174 plane_config->tiled = true;
6175
6176 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6177 fourcc = intel_format_to_fourcc(pixel_format);
6178 crtc->base.primary->fb->pixel_format = fourcc;
6179 crtc->base.primary->fb->bits_per_pixel =
6180 drm_format_plane_cpp(fourcc, 0) * 8;
6181
6182 if (INTEL_INFO(dev)->gen >= 4) {
6183 if (plane_config->tiled)
6184 offset = I915_READ(DSPTILEOFF(plane));
6185 else
6186 offset = I915_READ(DSPLINOFF(plane));
6187 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6188 } else {
6189 base = I915_READ(DSPADDR(plane));
6190 }
6191 plane_config->base = base;
6192
6193 val = I915_READ(PIPESRC(pipe));
6194 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6195 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6196
6197 val = I915_READ(DSPSTRIDE(pipe));
6198 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6199
6200 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6201 plane_config->tiled);
6202
6203 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6204 aligned_height);
6205
6206 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6207 pipe, plane, crtc->base.primary->fb->width,
6208 crtc->base.primary->fb->height,
6209 crtc->base.primary->fb->bits_per_pixel, base,
6210 crtc->base.primary->fb->pitches[0],
6211 plane_config->size);
6212
6213 }
6214
6215 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6216 struct intel_crtc_config *pipe_config)
6217 {
6218 struct drm_device *dev = crtc->base.dev;
6219 struct drm_i915_private *dev_priv = dev->dev_private;
6220 int pipe = pipe_config->cpu_transcoder;
6221 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6222 intel_clock_t clock;
6223 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6224 int refclk = 100000;
6225
6226 mutex_lock(&dev_priv->dpio_lock);
6227 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6228 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6229 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6230 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6231 mutex_unlock(&dev_priv->dpio_lock);
6232
6233 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6234 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6235 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6236 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6237 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6238
6239 chv_clock(refclk, &clock);
6240
6241 /* clock.dot is the fast clock */
6242 pipe_config->port_clock = clock.dot / 5;
6243 }
6244
6245 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6246 struct intel_crtc_config *pipe_config)
6247 {
6248 struct drm_device *dev = crtc->base.dev;
6249 struct drm_i915_private *dev_priv = dev->dev_private;
6250 uint32_t tmp;
6251
6252 if (!intel_display_power_enabled(dev_priv,
6253 POWER_DOMAIN_PIPE(crtc->pipe)))
6254 return false;
6255
6256 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6257 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6258
6259 tmp = I915_READ(PIPECONF(crtc->pipe));
6260 if (!(tmp & PIPECONF_ENABLE))
6261 return false;
6262
6263 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6264 switch (tmp & PIPECONF_BPC_MASK) {
6265 case PIPECONF_6BPC:
6266 pipe_config->pipe_bpp = 18;
6267 break;
6268 case PIPECONF_8BPC:
6269 pipe_config->pipe_bpp = 24;
6270 break;
6271 case PIPECONF_10BPC:
6272 pipe_config->pipe_bpp = 30;
6273 break;
6274 default:
6275 break;
6276 }
6277 }
6278
6279 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6280 pipe_config->limited_color_range = true;
6281
6282 if (INTEL_INFO(dev)->gen < 4)
6283 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6284
6285 intel_get_pipe_timings(crtc, pipe_config);
6286
6287 i9xx_get_pfit_config(crtc, pipe_config);
6288
6289 if (INTEL_INFO(dev)->gen >= 4) {
6290 tmp = I915_READ(DPLL_MD(crtc->pipe));
6291 pipe_config->pixel_multiplier =
6292 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6293 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6294 pipe_config->dpll_hw_state.dpll_md = tmp;
6295 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6296 tmp = I915_READ(DPLL(crtc->pipe));
6297 pipe_config->pixel_multiplier =
6298 ((tmp & SDVO_MULTIPLIER_MASK)
6299 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6300 } else {
6301 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6302 * port and will be fixed up in the encoder->get_config
6303 * function. */
6304 pipe_config->pixel_multiplier = 1;
6305 }
6306 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6307 if (!IS_VALLEYVIEW(dev)) {
6308 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6309 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6310 } else {
6311 /* Mask out read-only status bits. */
6312 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6313 DPLL_PORTC_READY_MASK |
6314 DPLL_PORTB_READY_MASK);
6315 }
6316
6317 if (IS_CHERRYVIEW(dev))
6318 chv_crtc_clock_get(crtc, pipe_config);
6319 else if (IS_VALLEYVIEW(dev))
6320 vlv_crtc_clock_get(crtc, pipe_config);
6321 else
6322 i9xx_crtc_clock_get(crtc, pipe_config);
6323
6324 return true;
6325 }
6326
6327 static void ironlake_init_pch_refclk(struct drm_device *dev)
6328 {
6329 struct drm_i915_private *dev_priv = dev->dev_private;
6330 struct drm_mode_config *mode_config = &dev->mode_config;
6331 struct intel_encoder *encoder;
6332 u32 val, final;
6333 bool has_lvds = false;
6334 bool has_cpu_edp = false;
6335 bool has_panel = false;
6336 bool has_ck505 = false;
6337 bool can_ssc = false;
6338
6339 /* We need to take the global config into account */
6340 list_for_each_entry(encoder, &mode_config->encoder_list,
6341 base.head) {
6342 switch (encoder->type) {
6343 case INTEL_OUTPUT_LVDS:
6344 has_panel = true;
6345 has_lvds = true;
6346 break;
6347 case INTEL_OUTPUT_EDP:
6348 has_panel = true;
6349 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6350 has_cpu_edp = true;
6351 break;
6352 }
6353 }
6354
6355 if (HAS_PCH_IBX(dev)) {
6356 has_ck505 = dev_priv->vbt.display_clock_mode;
6357 can_ssc = has_ck505;
6358 } else {
6359 has_ck505 = false;
6360 can_ssc = true;
6361 }
6362
6363 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6364 has_panel, has_lvds, has_ck505);
6365
6366 /* Ironlake: try to setup display ref clock before DPLL
6367 * enabling. This is only under driver's control after
6368 * PCH B stepping, previous chipset stepping should be
6369 * ignoring this setting.
6370 */
6371 val = I915_READ(PCH_DREF_CONTROL);
6372
6373 /* As we must carefully and slowly disable/enable each source in turn,
6374 * compute the final state we want first and check if we need to
6375 * make any changes at all.
6376 */
6377 final = val;
6378 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6379 if (has_ck505)
6380 final |= DREF_NONSPREAD_CK505_ENABLE;
6381 else
6382 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6383
6384 final &= ~DREF_SSC_SOURCE_MASK;
6385 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6386 final &= ~DREF_SSC1_ENABLE;
6387
6388 if (has_panel) {
6389 final |= DREF_SSC_SOURCE_ENABLE;
6390
6391 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6392 final |= DREF_SSC1_ENABLE;
6393
6394 if (has_cpu_edp) {
6395 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6396 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6397 else
6398 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6399 } else
6400 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6401 } else {
6402 final |= DREF_SSC_SOURCE_DISABLE;
6403 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6404 }
6405
6406 if (final == val)
6407 return;
6408
6409 /* Always enable nonspread source */
6410 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6411
6412 if (has_ck505)
6413 val |= DREF_NONSPREAD_CK505_ENABLE;
6414 else
6415 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6416
6417 if (has_panel) {
6418 val &= ~DREF_SSC_SOURCE_MASK;
6419 val |= DREF_SSC_SOURCE_ENABLE;
6420
6421 /* SSC must be turned on before enabling the CPU output */
6422 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6423 DRM_DEBUG_KMS("Using SSC on panel\n");
6424 val |= DREF_SSC1_ENABLE;
6425 } else
6426 val &= ~DREF_SSC1_ENABLE;
6427
6428 /* Get SSC going before enabling the outputs */
6429 I915_WRITE(PCH_DREF_CONTROL, val);
6430 POSTING_READ(PCH_DREF_CONTROL);
6431 udelay(200);
6432
6433 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6434
6435 /* Enable CPU source on CPU attached eDP */
6436 if (has_cpu_edp) {
6437 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6438 DRM_DEBUG_KMS("Using SSC on eDP\n");
6439 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6440 } else
6441 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6442 } else
6443 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6444
6445 I915_WRITE(PCH_DREF_CONTROL, val);
6446 POSTING_READ(PCH_DREF_CONTROL);
6447 udelay(200);
6448 } else {
6449 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6450
6451 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6452
6453 /* Turn off CPU output */
6454 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6455
6456 I915_WRITE(PCH_DREF_CONTROL, val);
6457 POSTING_READ(PCH_DREF_CONTROL);
6458 udelay(200);
6459
6460 /* Turn off the SSC source */
6461 val &= ~DREF_SSC_SOURCE_MASK;
6462 val |= DREF_SSC_SOURCE_DISABLE;
6463
6464 /* Turn off SSC1 */
6465 val &= ~DREF_SSC1_ENABLE;
6466
6467 I915_WRITE(PCH_DREF_CONTROL, val);
6468 POSTING_READ(PCH_DREF_CONTROL);
6469 udelay(200);
6470 }
6471
6472 BUG_ON(val != final);
6473 }
6474
6475 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6476 {
6477 uint32_t tmp;
6478
6479 tmp = I915_READ(SOUTH_CHICKEN2);
6480 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6481 I915_WRITE(SOUTH_CHICKEN2, tmp);
6482
6483 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6484 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6485 DRM_ERROR("FDI mPHY reset assert timeout\n");
6486
6487 tmp = I915_READ(SOUTH_CHICKEN2);
6488 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6489 I915_WRITE(SOUTH_CHICKEN2, tmp);
6490
6491 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6492 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6493 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6494 }
6495
6496 /* WaMPhyProgramming:hsw */
6497 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6498 {
6499 uint32_t tmp;
6500
6501 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6502 tmp &= ~(0xFF << 24);
6503 tmp |= (0x12 << 24);
6504 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6505
6506 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6507 tmp |= (1 << 11);
6508 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6509
6510 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6511 tmp |= (1 << 11);
6512 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6513
6514 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6515 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6516 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6517
6518 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6519 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6520 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6521
6522 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6523 tmp &= ~(7 << 13);
6524 tmp |= (5 << 13);
6525 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6526
6527 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6528 tmp &= ~(7 << 13);
6529 tmp |= (5 << 13);
6530 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6531
6532 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6533 tmp &= ~0xFF;
6534 tmp |= 0x1C;
6535 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6536
6537 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6538 tmp &= ~0xFF;
6539 tmp |= 0x1C;
6540 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6541
6542 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6543 tmp &= ~(0xFF << 16);
6544 tmp |= (0x1C << 16);
6545 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6546
6547 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6548 tmp &= ~(0xFF << 16);
6549 tmp |= (0x1C << 16);
6550 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6551
6552 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6553 tmp |= (1 << 27);
6554 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6555
6556 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6557 tmp |= (1 << 27);
6558 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6559
6560 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6561 tmp &= ~(0xF << 28);
6562 tmp |= (4 << 28);
6563 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6564
6565 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6566 tmp &= ~(0xF << 28);
6567 tmp |= (4 << 28);
6568 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6569 }
6570
6571 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6572 * Programming" based on the parameters passed:
6573 * - Sequence to enable CLKOUT_DP
6574 * - Sequence to enable CLKOUT_DP without spread
6575 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6576 */
6577 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6578 bool with_fdi)
6579 {
6580 struct drm_i915_private *dev_priv = dev->dev_private;
6581 uint32_t reg, tmp;
6582
6583 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6584 with_spread = true;
6585 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6586 with_fdi, "LP PCH doesn't have FDI\n"))
6587 with_fdi = false;
6588
6589 mutex_lock(&dev_priv->dpio_lock);
6590
6591 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6592 tmp &= ~SBI_SSCCTL_DISABLE;
6593 tmp |= SBI_SSCCTL_PATHALT;
6594 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6595
6596 udelay(24);
6597
6598 if (with_spread) {
6599 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6600 tmp &= ~SBI_SSCCTL_PATHALT;
6601 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6602
6603 if (with_fdi) {
6604 lpt_reset_fdi_mphy(dev_priv);
6605 lpt_program_fdi_mphy(dev_priv);
6606 }
6607 }
6608
6609 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6610 SBI_GEN0 : SBI_DBUFF0;
6611 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6612 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6613 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6614
6615 mutex_unlock(&dev_priv->dpio_lock);
6616 }
6617
6618 /* Sequence to disable CLKOUT_DP */
6619 static void lpt_disable_clkout_dp(struct drm_device *dev)
6620 {
6621 struct drm_i915_private *dev_priv = dev->dev_private;
6622 uint32_t reg, tmp;
6623
6624 mutex_lock(&dev_priv->dpio_lock);
6625
6626 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6627 SBI_GEN0 : SBI_DBUFF0;
6628 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6629 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6630 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6631
6632 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6633 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6634 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6635 tmp |= SBI_SSCCTL_PATHALT;
6636 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6637 udelay(32);
6638 }
6639 tmp |= SBI_SSCCTL_DISABLE;
6640 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6641 }
6642
6643 mutex_unlock(&dev_priv->dpio_lock);
6644 }
6645
6646 static void lpt_init_pch_refclk(struct drm_device *dev)
6647 {
6648 struct drm_mode_config *mode_config = &dev->mode_config;
6649 struct intel_encoder *encoder;
6650 bool has_vga = false;
6651
6652 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6653 switch (encoder->type) {
6654 case INTEL_OUTPUT_ANALOG:
6655 has_vga = true;
6656 break;
6657 }
6658 }
6659
6660 if (has_vga)
6661 lpt_enable_clkout_dp(dev, true, true);
6662 else
6663 lpt_disable_clkout_dp(dev);
6664 }
6665
6666 /*
6667 * Initialize reference clocks when the driver loads
6668 */
6669 void intel_init_pch_refclk(struct drm_device *dev)
6670 {
6671 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6672 ironlake_init_pch_refclk(dev);
6673 else if (HAS_PCH_LPT(dev))
6674 lpt_init_pch_refclk(dev);
6675 }
6676
6677 static int ironlake_get_refclk(struct drm_crtc *crtc)
6678 {
6679 struct drm_device *dev = crtc->dev;
6680 struct drm_i915_private *dev_priv = dev->dev_private;
6681 struct intel_encoder *encoder;
6682 int num_connectors = 0;
6683 bool is_lvds = false;
6684
6685 for_each_encoder_on_crtc(dev, crtc, encoder) {
6686 switch (encoder->type) {
6687 case INTEL_OUTPUT_LVDS:
6688 is_lvds = true;
6689 break;
6690 }
6691 num_connectors++;
6692 }
6693
6694 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6695 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6696 dev_priv->vbt.lvds_ssc_freq);
6697 return dev_priv->vbt.lvds_ssc_freq;
6698 }
6699
6700 return 120000;
6701 }
6702
6703 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6704 {
6705 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6707 int pipe = intel_crtc->pipe;
6708 uint32_t val;
6709
6710 val = 0;
6711
6712 switch (intel_crtc->config.pipe_bpp) {
6713 case 18:
6714 val |= PIPECONF_6BPC;
6715 break;
6716 case 24:
6717 val |= PIPECONF_8BPC;
6718 break;
6719 case 30:
6720 val |= PIPECONF_10BPC;
6721 break;
6722 case 36:
6723 val |= PIPECONF_12BPC;
6724 break;
6725 default:
6726 /* Case prevented by intel_choose_pipe_bpp_dither. */
6727 BUG();
6728 }
6729
6730 if (intel_crtc->config.dither)
6731 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6732
6733 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6734 val |= PIPECONF_INTERLACED_ILK;
6735 else
6736 val |= PIPECONF_PROGRESSIVE;
6737
6738 if (intel_crtc->config.limited_color_range)
6739 val |= PIPECONF_COLOR_RANGE_SELECT;
6740
6741 I915_WRITE(PIPECONF(pipe), val);
6742 POSTING_READ(PIPECONF(pipe));
6743 }
6744
6745 /*
6746 * Set up the pipe CSC unit.
6747 *
6748 * Currently only full range RGB to limited range RGB conversion
6749 * is supported, but eventually this should handle various
6750 * RGB<->YCbCr scenarios as well.
6751 */
6752 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6753 {
6754 struct drm_device *dev = crtc->dev;
6755 struct drm_i915_private *dev_priv = dev->dev_private;
6756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6757 int pipe = intel_crtc->pipe;
6758 uint16_t coeff = 0x7800; /* 1.0 */
6759
6760 /*
6761 * TODO: Check what kind of values actually come out of the pipe
6762 * with these coeff/postoff values and adjust to get the best
6763 * accuracy. Perhaps we even need to take the bpc value into
6764 * consideration.
6765 */
6766
6767 if (intel_crtc->config.limited_color_range)
6768 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6769
6770 /*
6771 * GY/GU and RY/RU should be the other way around according
6772 * to BSpec, but reality doesn't agree. Just set them up in
6773 * a way that results in the correct picture.
6774 */
6775 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6776 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6777
6778 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6779 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6780
6781 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6782 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6783
6784 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6785 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6786 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6787
6788 if (INTEL_INFO(dev)->gen > 6) {
6789 uint16_t postoff = 0;
6790
6791 if (intel_crtc->config.limited_color_range)
6792 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6793
6794 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6795 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6796 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6797
6798 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6799 } else {
6800 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6801
6802 if (intel_crtc->config.limited_color_range)
6803 mode |= CSC_BLACK_SCREEN_OFFSET;
6804
6805 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6806 }
6807 }
6808
6809 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6810 {
6811 struct drm_device *dev = crtc->dev;
6812 struct drm_i915_private *dev_priv = dev->dev_private;
6813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6814 enum pipe pipe = intel_crtc->pipe;
6815 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6816 uint32_t val;
6817
6818 val = 0;
6819
6820 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6821 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6822
6823 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6824 val |= PIPECONF_INTERLACED_ILK;
6825 else
6826 val |= PIPECONF_PROGRESSIVE;
6827
6828 I915_WRITE(PIPECONF(cpu_transcoder), val);
6829 POSTING_READ(PIPECONF(cpu_transcoder));
6830
6831 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6832 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6833
6834 if (IS_BROADWELL(dev)) {
6835 val = 0;
6836
6837 switch (intel_crtc->config.pipe_bpp) {
6838 case 18:
6839 val |= PIPEMISC_DITHER_6_BPC;
6840 break;
6841 case 24:
6842 val |= PIPEMISC_DITHER_8_BPC;
6843 break;
6844 case 30:
6845 val |= PIPEMISC_DITHER_10_BPC;
6846 break;
6847 case 36:
6848 val |= PIPEMISC_DITHER_12_BPC;
6849 break;
6850 default:
6851 /* Case prevented by pipe_config_set_bpp. */
6852 BUG();
6853 }
6854
6855 if (intel_crtc->config.dither)
6856 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6857
6858 I915_WRITE(PIPEMISC(pipe), val);
6859 }
6860 }
6861
6862 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6863 intel_clock_t *clock,
6864 bool *has_reduced_clock,
6865 intel_clock_t *reduced_clock)
6866 {
6867 struct drm_device *dev = crtc->dev;
6868 struct drm_i915_private *dev_priv = dev->dev_private;
6869 struct intel_encoder *intel_encoder;
6870 int refclk;
6871 const intel_limit_t *limit;
6872 bool ret, is_lvds = false;
6873
6874 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6875 switch (intel_encoder->type) {
6876 case INTEL_OUTPUT_LVDS:
6877 is_lvds = true;
6878 break;
6879 }
6880 }
6881
6882 refclk = ironlake_get_refclk(crtc);
6883
6884 /*
6885 * Returns a set of divisors for the desired target clock with the given
6886 * refclk, or FALSE. The returned values represent the clock equation:
6887 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6888 */
6889 limit = intel_limit(crtc, refclk);
6890 ret = dev_priv->display.find_dpll(limit, crtc,
6891 to_intel_crtc(crtc)->config.port_clock,
6892 refclk, NULL, clock);
6893 if (!ret)
6894 return false;
6895
6896 if (is_lvds && dev_priv->lvds_downclock_avail) {
6897 /*
6898 * Ensure we match the reduced clock's P to the target clock.
6899 * If the clocks don't match, we can't switch the display clock
6900 * by using the FP0/FP1. In such case we will disable the LVDS
6901 * downclock feature.
6902 */
6903 *has_reduced_clock =
6904 dev_priv->display.find_dpll(limit, crtc,
6905 dev_priv->lvds_downclock,
6906 refclk, clock,
6907 reduced_clock);
6908 }
6909
6910 return true;
6911 }
6912
6913 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6914 {
6915 /*
6916 * Account for spread spectrum to avoid
6917 * oversubscribing the link. Max center spread
6918 * is 2.5%; use 5% for safety's sake.
6919 */
6920 u32 bps = target_clock * bpp * 21 / 20;
6921 return DIV_ROUND_UP(bps, link_bw * 8);
6922 }
6923
6924 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6925 {
6926 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6927 }
6928
6929 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6930 u32 *fp,
6931 intel_clock_t *reduced_clock, u32 *fp2)
6932 {
6933 struct drm_crtc *crtc = &intel_crtc->base;
6934 struct drm_device *dev = crtc->dev;
6935 struct drm_i915_private *dev_priv = dev->dev_private;
6936 struct intel_encoder *intel_encoder;
6937 uint32_t dpll;
6938 int factor, num_connectors = 0;
6939 bool is_lvds = false, is_sdvo = false;
6940
6941 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6942 switch (intel_encoder->type) {
6943 case INTEL_OUTPUT_LVDS:
6944 is_lvds = true;
6945 break;
6946 case INTEL_OUTPUT_SDVO:
6947 case INTEL_OUTPUT_HDMI:
6948 is_sdvo = true;
6949 break;
6950 }
6951
6952 num_connectors++;
6953 }
6954
6955 /* Enable autotuning of the PLL clock (if permissible) */
6956 factor = 21;
6957 if (is_lvds) {
6958 if ((intel_panel_use_ssc(dev_priv) &&
6959 dev_priv->vbt.lvds_ssc_freq == 100000) ||
6960 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6961 factor = 25;
6962 } else if (intel_crtc->config.sdvo_tv_clock)
6963 factor = 20;
6964
6965 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6966 *fp |= FP_CB_TUNE;
6967
6968 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6969 *fp2 |= FP_CB_TUNE;
6970
6971 dpll = 0;
6972
6973 if (is_lvds)
6974 dpll |= DPLLB_MODE_LVDS;
6975 else
6976 dpll |= DPLLB_MODE_DAC_SERIAL;
6977
6978 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6979 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6980
6981 if (is_sdvo)
6982 dpll |= DPLL_SDVO_HIGH_SPEED;
6983 if (intel_crtc->config.has_dp_encoder)
6984 dpll |= DPLL_SDVO_HIGH_SPEED;
6985
6986 /* compute bitmask from p1 value */
6987 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6988 /* also FPA1 */
6989 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6990
6991 switch (intel_crtc->config.dpll.p2) {
6992 case 5:
6993 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6994 break;
6995 case 7:
6996 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6997 break;
6998 case 10:
6999 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7000 break;
7001 case 14:
7002 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7003 break;
7004 }
7005
7006 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7007 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7008 else
7009 dpll |= PLL_REF_INPUT_DREFCLK;
7010
7011 return dpll | DPLL_VCO_ENABLE;
7012 }
7013
7014 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7015 int x, int y,
7016 struct drm_framebuffer *fb)
7017 {
7018 struct drm_device *dev = crtc->dev;
7019 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7020 int num_connectors = 0;
7021 intel_clock_t clock, reduced_clock;
7022 u32 dpll = 0, fp = 0, fp2 = 0;
7023 bool ok, has_reduced_clock = false;
7024 bool is_lvds = false;
7025 struct intel_encoder *encoder;
7026 struct intel_shared_dpll *pll;
7027
7028 for_each_encoder_on_crtc(dev, crtc, encoder) {
7029 switch (encoder->type) {
7030 case INTEL_OUTPUT_LVDS:
7031 is_lvds = true;
7032 break;
7033 }
7034
7035 num_connectors++;
7036 }
7037
7038 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7039 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7040
7041 ok = ironlake_compute_clocks(crtc, &clock,
7042 &has_reduced_clock, &reduced_clock);
7043 if (!ok && !intel_crtc->config.clock_set) {
7044 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7045 return -EINVAL;
7046 }
7047 /* Compat-code for transition, will disappear. */
7048 if (!intel_crtc->config.clock_set) {
7049 intel_crtc->config.dpll.n = clock.n;
7050 intel_crtc->config.dpll.m1 = clock.m1;
7051 intel_crtc->config.dpll.m2 = clock.m2;
7052 intel_crtc->config.dpll.p1 = clock.p1;
7053 intel_crtc->config.dpll.p2 = clock.p2;
7054 }
7055
7056 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7057 if (intel_crtc->config.has_pch_encoder) {
7058 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7059 if (has_reduced_clock)
7060 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7061
7062 dpll = ironlake_compute_dpll(intel_crtc,
7063 &fp, &reduced_clock,
7064 has_reduced_clock ? &fp2 : NULL);
7065
7066 intel_crtc->config.dpll_hw_state.dpll = dpll;
7067 intel_crtc->config.dpll_hw_state.fp0 = fp;
7068 if (has_reduced_clock)
7069 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7070 else
7071 intel_crtc->config.dpll_hw_state.fp1 = fp;
7072
7073 pll = intel_get_shared_dpll(intel_crtc);
7074 if (pll == NULL) {
7075 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7076 pipe_name(intel_crtc->pipe));
7077 return -EINVAL;
7078 }
7079 } else
7080 intel_put_shared_dpll(intel_crtc);
7081
7082 if (is_lvds && has_reduced_clock && i915.powersave)
7083 intel_crtc->lowfreq_avail = true;
7084 else
7085 intel_crtc->lowfreq_avail = false;
7086
7087 return 0;
7088 }
7089
7090 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7091 struct intel_link_m_n *m_n)
7092 {
7093 struct drm_device *dev = crtc->base.dev;
7094 struct drm_i915_private *dev_priv = dev->dev_private;
7095 enum pipe pipe = crtc->pipe;
7096
7097 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7098 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7099 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7100 & ~TU_SIZE_MASK;
7101 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7102 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7103 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7104 }
7105
7106 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7107 enum transcoder transcoder,
7108 struct intel_link_m_n *m_n)
7109 {
7110 struct drm_device *dev = crtc->base.dev;
7111 struct drm_i915_private *dev_priv = dev->dev_private;
7112 enum pipe pipe = crtc->pipe;
7113
7114 if (INTEL_INFO(dev)->gen >= 5) {
7115 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7116 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7117 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7118 & ~TU_SIZE_MASK;
7119 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7120 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7121 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7122 } else {
7123 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7124 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7125 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7126 & ~TU_SIZE_MASK;
7127 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7128 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7129 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7130 }
7131 }
7132
7133 void intel_dp_get_m_n(struct intel_crtc *crtc,
7134 struct intel_crtc_config *pipe_config)
7135 {
7136 if (crtc->config.has_pch_encoder)
7137 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7138 else
7139 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7140 &pipe_config->dp_m_n);
7141 }
7142
7143 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7144 struct intel_crtc_config *pipe_config)
7145 {
7146 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7147 &pipe_config->fdi_m_n);
7148 }
7149
7150 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7151 struct intel_crtc_config *pipe_config)
7152 {
7153 struct drm_device *dev = crtc->base.dev;
7154 struct drm_i915_private *dev_priv = dev->dev_private;
7155 uint32_t tmp;
7156
7157 tmp = I915_READ(PF_CTL(crtc->pipe));
7158
7159 if (tmp & PF_ENABLE) {
7160 pipe_config->pch_pfit.enabled = true;
7161 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7162 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7163
7164 /* We currently do not free assignements of panel fitters on
7165 * ivb/hsw (since we don't use the higher upscaling modes which
7166 * differentiates them) so just WARN about this case for now. */
7167 if (IS_GEN7(dev)) {
7168 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7169 PF_PIPE_SEL_IVB(crtc->pipe));
7170 }
7171 }
7172 }
7173
7174 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7175 struct intel_plane_config *plane_config)
7176 {
7177 struct drm_device *dev = crtc->base.dev;
7178 struct drm_i915_private *dev_priv = dev->dev_private;
7179 u32 val, base, offset;
7180 int pipe = crtc->pipe, plane = crtc->plane;
7181 int fourcc, pixel_format;
7182 int aligned_height;
7183
7184 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7185 if (!crtc->base.primary->fb) {
7186 DRM_DEBUG_KMS("failed to alloc fb\n");
7187 return;
7188 }
7189
7190 val = I915_READ(DSPCNTR(plane));
7191
7192 if (INTEL_INFO(dev)->gen >= 4)
7193 if (val & DISPPLANE_TILED)
7194 plane_config->tiled = true;
7195
7196 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7197 fourcc = intel_format_to_fourcc(pixel_format);
7198 crtc->base.primary->fb->pixel_format = fourcc;
7199 crtc->base.primary->fb->bits_per_pixel =
7200 drm_format_plane_cpp(fourcc, 0) * 8;
7201
7202 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7203 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7204 offset = I915_READ(DSPOFFSET(plane));
7205 } else {
7206 if (plane_config->tiled)
7207 offset = I915_READ(DSPTILEOFF(plane));
7208 else
7209 offset = I915_READ(DSPLINOFF(plane));
7210 }
7211 plane_config->base = base;
7212
7213 val = I915_READ(PIPESRC(pipe));
7214 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7215 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7216
7217 val = I915_READ(DSPSTRIDE(pipe));
7218 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7219
7220 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7221 plane_config->tiled);
7222
7223 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7224 aligned_height);
7225
7226 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7227 pipe, plane, crtc->base.primary->fb->width,
7228 crtc->base.primary->fb->height,
7229 crtc->base.primary->fb->bits_per_pixel, base,
7230 crtc->base.primary->fb->pitches[0],
7231 plane_config->size);
7232 }
7233
7234 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7235 struct intel_crtc_config *pipe_config)
7236 {
7237 struct drm_device *dev = crtc->base.dev;
7238 struct drm_i915_private *dev_priv = dev->dev_private;
7239 uint32_t tmp;
7240
7241 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7242 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7243
7244 tmp = I915_READ(PIPECONF(crtc->pipe));
7245 if (!(tmp & PIPECONF_ENABLE))
7246 return false;
7247
7248 switch (tmp & PIPECONF_BPC_MASK) {
7249 case PIPECONF_6BPC:
7250 pipe_config->pipe_bpp = 18;
7251 break;
7252 case PIPECONF_8BPC:
7253 pipe_config->pipe_bpp = 24;
7254 break;
7255 case PIPECONF_10BPC:
7256 pipe_config->pipe_bpp = 30;
7257 break;
7258 case PIPECONF_12BPC:
7259 pipe_config->pipe_bpp = 36;
7260 break;
7261 default:
7262 break;
7263 }
7264
7265 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7266 pipe_config->limited_color_range = true;
7267
7268 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7269 struct intel_shared_dpll *pll;
7270
7271 pipe_config->has_pch_encoder = true;
7272
7273 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7274 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7275 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7276
7277 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7278
7279 if (HAS_PCH_IBX(dev_priv->dev)) {
7280 pipe_config->shared_dpll =
7281 (enum intel_dpll_id) crtc->pipe;
7282 } else {
7283 tmp = I915_READ(PCH_DPLL_SEL);
7284 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7285 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7286 else
7287 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7288 }
7289
7290 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7291
7292 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7293 &pipe_config->dpll_hw_state));
7294
7295 tmp = pipe_config->dpll_hw_state.dpll;
7296 pipe_config->pixel_multiplier =
7297 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7298 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7299
7300 ironlake_pch_clock_get(crtc, pipe_config);
7301 } else {
7302 pipe_config->pixel_multiplier = 1;
7303 }
7304
7305 intel_get_pipe_timings(crtc, pipe_config);
7306
7307 ironlake_get_pfit_config(crtc, pipe_config);
7308
7309 return true;
7310 }
7311
7312 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7313 {
7314 struct drm_device *dev = dev_priv->dev;
7315 struct intel_crtc *crtc;
7316
7317 for_each_intel_crtc(dev, crtc)
7318 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7319 pipe_name(crtc->pipe));
7320
7321 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7322 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7323 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7324 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7325 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7326 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7327 "CPU PWM1 enabled\n");
7328 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7329 "CPU PWM2 enabled\n");
7330 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7331 "PCH PWM1 enabled\n");
7332 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7333 "Utility pin enabled\n");
7334 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7335
7336 /*
7337 * In theory we can still leave IRQs enabled, as long as only the HPD
7338 * interrupts remain enabled. We used to check for that, but since it's
7339 * gen-specific and since we only disable LCPLL after we fully disable
7340 * the interrupts, the check below should be enough.
7341 */
7342 WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
7343 }
7344
7345 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7346 {
7347 struct drm_device *dev = dev_priv->dev;
7348
7349 if (IS_HASWELL(dev))
7350 return I915_READ(D_COMP_HSW);
7351 else
7352 return I915_READ(D_COMP_BDW);
7353 }
7354
7355 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7356 {
7357 struct drm_device *dev = dev_priv->dev;
7358
7359 if (IS_HASWELL(dev)) {
7360 mutex_lock(&dev_priv->rps.hw_lock);
7361 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7362 val))
7363 DRM_ERROR("Failed to write to D_COMP\n");
7364 mutex_unlock(&dev_priv->rps.hw_lock);
7365 } else {
7366 I915_WRITE(D_COMP_BDW, val);
7367 POSTING_READ(D_COMP_BDW);
7368 }
7369 }
7370
7371 /*
7372 * This function implements pieces of two sequences from BSpec:
7373 * - Sequence for display software to disable LCPLL
7374 * - Sequence for display software to allow package C8+
7375 * The steps implemented here are just the steps that actually touch the LCPLL
7376 * register. Callers should take care of disabling all the display engine
7377 * functions, doing the mode unset, fixing interrupts, etc.
7378 */
7379 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7380 bool switch_to_fclk, bool allow_power_down)
7381 {
7382 uint32_t val;
7383
7384 assert_can_disable_lcpll(dev_priv);
7385
7386 val = I915_READ(LCPLL_CTL);
7387
7388 if (switch_to_fclk) {
7389 val |= LCPLL_CD_SOURCE_FCLK;
7390 I915_WRITE(LCPLL_CTL, val);
7391
7392 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7393 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7394 DRM_ERROR("Switching to FCLK failed\n");
7395
7396 val = I915_READ(LCPLL_CTL);
7397 }
7398
7399 val |= LCPLL_PLL_DISABLE;
7400 I915_WRITE(LCPLL_CTL, val);
7401 POSTING_READ(LCPLL_CTL);
7402
7403 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7404 DRM_ERROR("LCPLL still locked\n");
7405
7406 val = hsw_read_dcomp(dev_priv);
7407 val |= D_COMP_COMP_DISABLE;
7408 hsw_write_dcomp(dev_priv, val);
7409 ndelay(100);
7410
7411 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7412 1))
7413 DRM_ERROR("D_COMP RCOMP still in progress\n");
7414
7415 if (allow_power_down) {
7416 val = I915_READ(LCPLL_CTL);
7417 val |= LCPLL_POWER_DOWN_ALLOW;
7418 I915_WRITE(LCPLL_CTL, val);
7419 POSTING_READ(LCPLL_CTL);
7420 }
7421 }
7422
7423 /*
7424 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7425 * source.
7426 */
7427 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7428 {
7429 uint32_t val;
7430 unsigned long irqflags;
7431
7432 val = I915_READ(LCPLL_CTL);
7433
7434 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7435 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7436 return;
7437
7438 /*
7439 * Make sure we're not on PC8 state before disabling PC8, otherwise
7440 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7441 *
7442 * The other problem is that hsw_restore_lcpll() is called as part of
7443 * the runtime PM resume sequence, so we can't just call
7444 * gen6_gt_force_wake_get() because that function calls
7445 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7446 * while we are on the resume sequence. So to solve this problem we have
7447 * to call special forcewake code that doesn't touch runtime PM and
7448 * doesn't enable the forcewake delayed work.
7449 */
7450 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7451 if (dev_priv->uncore.forcewake_count++ == 0)
7452 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7453 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7454
7455 if (val & LCPLL_POWER_DOWN_ALLOW) {
7456 val &= ~LCPLL_POWER_DOWN_ALLOW;
7457 I915_WRITE(LCPLL_CTL, val);
7458 POSTING_READ(LCPLL_CTL);
7459 }
7460
7461 val = hsw_read_dcomp(dev_priv);
7462 val |= D_COMP_COMP_FORCE;
7463 val &= ~D_COMP_COMP_DISABLE;
7464 hsw_write_dcomp(dev_priv, val);
7465
7466 val = I915_READ(LCPLL_CTL);
7467 val &= ~LCPLL_PLL_DISABLE;
7468 I915_WRITE(LCPLL_CTL, val);
7469
7470 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7471 DRM_ERROR("LCPLL not locked yet\n");
7472
7473 if (val & LCPLL_CD_SOURCE_FCLK) {
7474 val = I915_READ(LCPLL_CTL);
7475 val &= ~LCPLL_CD_SOURCE_FCLK;
7476 I915_WRITE(LCPLL_CTL, val);
7477
7478 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7479 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7480 DRM_ERROR("Switching back to LCPLL failed\n");
7481 }
7482
7483 /* See the big comment above. */
7484 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7485 if (--dev_priv->uncore.forcewake_count == 0)
7486 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7487 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7488 }
7489
7490 /*
7491 * Package states C8 and deeper are really deep PC states that can only be
7492 * reached when all the devices on the system allow it, so even if the graphics
7493 * device allows PC8+, it doesn't mean the system will actually get to these
7494 * states. Our driver only allows PC8+ when going into runtime PM.
7495 *
7496 * The requirements for PC8+ are that all the outputs are disabled, the power
7497 * well is disabled and most interrupts are disabled, and these are also
7498 * requirements for runtime PM. When these conditions are met, we manually do
7499 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7500 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7501 * hang the machine.
7502 *
7503 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7504 * the state of some registers, so when we come back from PC8+ we need to
7505 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7506 * need to take care of the registers kept by RC6. Notice that this happens even
7507 * if we don't put the device in PCI D3 state (which is what currently happens
7508 * because of the runtime PM support).
7509 *
7510 * For more, read "Display Sequences for Package C8" on the hardware
7511 * documentation.
7512 */
7513 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7514 {
7515 struct drm_device *dev = dev_priv->dev;
7516 uint32_t val;
7517
7518 DRM_DEBUG_KMS("Enabling package C8+\n");
7519
7520 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7521 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7522 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7523 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7524 }
7525
7526 lpt_disable_clkout_dp(dev);
7527 hsw_disable_lcpll(dev_priv, true, true);
7528 }
7529
7530 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7531 {
7532 struct drm_device *dev = dev_priv->dev;
7533 uint32_t val;
7534
7535 DRM_DEBUG_KMS("Disabling package C8+\n");
7536
7537 hsw_restore_lcpll(dev_priv);
7538 lpt_init_pch_refclk(dev);
7539
7540 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7541 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7542 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7543 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7544 }
7545
7546 intel_prepare_ddi(dev);
7547 }
7548
7549 static void snb_modeset_global_resources(struct drm_device *dev)
7550 {
7551 modeset_update_crtc_power_domains(dev);
7552 }
7553
7554 static void haswell_modeset_global_resources(struct drm_device *dev)
7555 {
7556 modeset_update_crtc_power_domains(dev);
7557 }
7558
7559 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7560 int x, int y,
7561 struct drm_framebuffer *fb)
7562 {
7563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7564
7565 if (!intel_ddi_pll_select(intel_crtc))
7566 return -EINVAL;
7567 intel_ddi_pll_enable(intel_crtc);
7568
7569 intel_crtc->lowfreq_avail = false;
7570
7571 return 0;
7572 }
7573
7574 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7575 struct intel_crtc_config *pipe_config)
7576 {
7577 struct drm_device *dev = crtc->base.dev;
7578 struct drm_i915_private *dev_priv = dev->dev_private;
7579 enum intel_display_power_domain pfit_domain;
7580 uint32_t tmp;
7581
7582 if (!intel_display_power_enabled(dev_priv,
7583 POWER_DOMAIN_PIPE(crtc->pipe)))
7584 return false;
7585
7586 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7587 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7588
7589 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7590 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7591 enum pipe trans_edp_pipe;
7592 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7593 default:
7594 WARN(1, "unknown pipe linked to edp transcoder\n");
7595 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7596 case TRANS_DDI_EDP_INPUT_A_ON:
7597 trans_edp_pipe = PIPE_A;
7598 break;
7599 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7600 trans_edp_pipe = PIPE_B;
7601 break;
7602 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7603 trans_edp_pipe = PIPE_C;
7604 break;
7605 }
7606
7607 if (trans_edp_pipe == crtc->pipe)
7608 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7609 }
7610
7611 if (!intel_display_power_enabled(dev_priv,
7612 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7613 return false;
7614
7615 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7616 if (!(tmp & PIPECONF_ENABLE))
7617 return false;
7618
7619 /*
7620 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7621 * DDI E. So just check whether this pipe is wired to DDI E and whether
7622 * the PCH transcoder is on.
7623 */
7624 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7625 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7626 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7627 pipe_config->has_pch_encoder = true;
7628
7629 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7630 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7631 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7632
7633 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7634 }
7635
7636 intel_get_pipe_timings(crtc, pipe_config);
7637
7638 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7639 if (intel_display_power_enabled(dev_priv, pfit_domain))
7640 ironlake_get_pfit_config(crtc, pipe_config);
7641
7642 if (IS_HASWELL(dev))
7643 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7644 (I915_READ(IPS_CTL) & IPS_ENABLE);
7645
7646 pipe_config->pixel_multiplier = 1;
7647
7648 return true;
7649 }
7650
7651 static struct {
7652 int clock;
7653 u32 config;
7654 } hdmi_audio_clock[] = {
7655 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7656 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7657 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7658 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7659 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7660 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7661 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7662 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7663 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7664 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7665 };
7666
7667 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7668 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7669 {
7670 int i;
7671
7672 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7673 if (mode->clock == hdmi_audio_clock[i].clock)
7674 break;
7675 }
7676
7677 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7678 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7679 i = 1;
7680 }
7681
7682 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7683 hdmi_audio_clock[i].clock,
7684 hdmi_audio_clock[i].config);
7685
7686 return hdmi_audio_clock[i].config;
7687 }
7688
7689 static bool intel_eld_uptodate(struct drm_connector *connector,
7690 int reg_eldv, uint32_t bits_eldv,
7691 int reg_elda, uint32_t bits_elda,
7692 int reg_edid)
7693 {
7694 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7695 uint8_t *eld = connector->eld;
7696 uint32_t i;
7697
7698 i = I915_READ(reg_eldv);
7699 i &= bits_eldv;
7700
7701 if (!eld[0])
7702 return !i;
7703
7704 if (!i)
7705 return false;
7706
7707 i = I915_READ(reg_elda);
7708 i &= ~bits_elda;
7709 I915_WRITE(reg_elda, i);
7710
7711 for (i = 0; i < eld[2]; i++)
7712 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7713 return false;
7714
7715 return true;
7716 }
7717
7718 static void g4x_write_eld(struct drm_connector *connector,
7719 struct drm_crtc *crtc,
7720 struct drm_display_mode *mode)
7721 {
7722 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7723 uint8_t *eld = connector->eld;
7724 uint32_t eldv;
7725 uint32_t len;
7726 uint32_t i;
7727
7728 i = I915_READ(G4X_AUD_VID_DID);
7729
7730 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7731 eldv = G4X_ELDV_DEVCL_DEVBLC;
7732 else
7733 eldv = G4X_ELDV_DEVCTG;
7734
7735 if (intel_eld_uptodate(connector,
7736 G4X_AUD_CNTL_ST, eldv,
7737 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7738 G4X_HDMIW_HDMIEDID))
7739 return;
7740
7741 i = I915_READ(G4X_AUD_CNTL_ST);
7742 i &= ~(eldv | G4X_ELD_ADDR);
7743 len = (i >> 9) & 0x1f; /* ELD buffer size */
7744 I915_WRITE(G4X_AUD_CNTL_ST, i);
7745
7746 if (!eld[0])
7747 return;
7748
7749 len = min_t(uint8_t, eld[2], len);
7750 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7751 for (i = 0; i < len; i++)
7752 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7753
7754 i = I915_READ(G4X_AUD_CNTL_ST);
7755 i |= eldv;
7756 I915_WRITE(G4X_AUD_CNTL_ST, i);
7757 }
7758
7759 static void haswell_write_eld(struct drm_connector *connector,
7760 struct drm_crtc *crtc,
7761 struct drm_display_mode *mode)
7762 {
7763 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7764 uint8_t *eld = connector->eld;
7765 uint32_t eldv;
7766 uint32_t i;
7767 int len;
7768 int pipe = to_intel_crtc(crtc)->pipe;
7769 int tmp;
7770
7771 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7772 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7773 int aud_config = HSW_AUD_CFG(pipe);
7774 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7775
7776 /* Audio output enable */
7777 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7778 tmp = I915_READ(aud_cntrl_st2);
7779 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7780 I915_WRITE(aud_cntrl_st2, tmp);
7781 POSTING_READ(aud_cntrl_st2);
7782
7783 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7784
7785 /* Set ELD valid state */
7786 tmp = I915_READ(aud_cntrl_st2);
7787 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7788 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7789 I915_WRITE(aud_cntrl_st2, tmp);
7790 tmp = I915_READ(aud_cntrl_st2);
7791 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7792
7793 /* Enable HDMI mode */
7794 tmp = I915_READ(aud_config);
7795 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7796 /* clear N_programing_enable and N_value_index */
7797 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7798 I915_WRITE(aud_config, tmp);
7799
7800 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7801
7802 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7803
7804 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7805 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7806 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7807 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7808 } else {
7809 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7810 }
7811
7812 if (intel_eld_uptodate(connector,
7813 aud_cntrl_st2, eldv,
7814 aud_cntl_st, IBX_ELD_ADDRESS,
7815 hdmiw_hdmiedid))
7816 return;
7817
7818 i = I915_READ(aud_cntrl_st2);
7819 i &= ~eldv;
7820 I915_WRITE(aud_cntrl_st2, i);
7821
7822 if (!eld[0])
7823 return;
7824
7825 i = I915_READ(aud_cntl_st);
7826 i &= ~IBX_ELD_ADDRESS;
7827 I915_WRITE(aud_cntl_st, i);
7828 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7829 DRM_DEBUG_DRIVER("port num:%d\n", i);
7830
7831 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7832 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7833 for (i = 0; i < len; i++)
7834 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7835
7836 i = I915_READ(aud_cntrl_st2);
7837 i |= eldv;
7838 I915_WRITE(aud_cntrl_st2, i);
7839
7840 }
7841
7842 static void ironlake_write_eld(struct drm_connector *connector,
7843 struct drm_crtc *crtc,
7844 struct drm_display_mode *mode)
7845 {
7846 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7847 uint8_t *eld = connector->eld;
7848 uint32_t eldv;
7849 uint32_t i;
7850 int len;
7851 int hdmiw_hdmiedid;
7852 int aud_config;
7853 int aud_cntl_st;
7854 int aud_cntrl_st2;
7855 int pipe = to_intel_crtc(crtc)->pipe;
7856
7857 if (HAS_PCH_IBX(connector->dev)) {
7858 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7859 aud_config = IBX_AUD_CFG(pipe);
7860 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7861 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7862 } else if (IS_VALLEYVIEW(connector->dev)) {
7863 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7864 aud_config = VLV_AUD_CFG(pipe);
7865 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7866 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7867 } else {
7868 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7869 aud_config = CPT_AUD_CFG(pipe);
7870 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7871 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7872 }
7873
7874 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7875
7876 if (IS_VALLEYVIEW(connector->dev)) {
7877 struct intel_encoder *intel_encoder;
7878 struct intel_digital_port *intel_dig_port;
7879
7880 intel_encoder = intel_attached_encoder(connector);
7881 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7882 i = intel_dig_port->port;
7883 } else {
7884 i = I915_READ(aud_cntl_st);
7885 i = (i >> 29) & DIP_PORT_SEL_MASK;
7886 /* DIP_Port_Select, 0x1 = PortB */
7887 }
7888
7889 if (!i) {
7890 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7891 /* operate blindly on all ports */
7892 eldv = IBX_ELD_VALIDB;
7893 eldv |= IBX_ELD_VALIDB << 4;
7894 eldv |= IBX_ELD_VALIDB << 8;
7895 } else {
7896 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7897 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7898 }
7899
7900 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7901 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7902 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7903 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7904 } else {
7905 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7906 }
7907
7908 if (intel_eld_uptodate(connector,
7909 aud_cntrl_st2, eldv,
7910 aud_cntl_st, IBX_ELD_ADDRESS,
7911 hdmiw_hdmiedid))
7912 return;
7913
7914 i = I915_READ(aud_cntrl_st2);
7915 i &= ~eldv;
7916 I915_WRITE(aud_cntrl_st2, i);
7917
7918 if (!eld[0])
7919 return;
7920
7921 i = I915_READ(aud_cntl_st);
7922 i &= ~IBX_ELD_ADDRESS;
7923 I915_WRITE(aud_cntl_st, i);
7924
7925 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7926 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7927 for (i = 0; i < len; i++)
7928 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7929
7930 i = I915_READ(aud_cntrl_st2);
7931 i |= eldv;
7932 I915_WRITE(aud_cntrl_st2, i);
7933 }
7934
7935 void intel_write_eld(struct drm_encoder *encoder,
7936 struct drm_display_mode *mode)
7937 {
7938 struct drm_crtc *crtc = encoder->crtc;
7939 struct drm_connector *connector;
7940 struct drm_device *dev = encoder->dev;
7941 struct drm_i915_private *dev_priv = dev->dev_private;
7942
7943 connector = drm_select_eld(encoder, mode);
7944 if (!connector)
7945 return;
7946
7947 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7948 connector->base.id,
7949 connector->name,
7950 connector->encoder->base.id,
7951 connector->encoder->name);
7952
7953 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7954
7955 if (dev_priv->display.write_eld)
7956 dev_priv->display.write_eld(connector, crtc, mode);
7957 }
7958
7959 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7960 {
7961 struct drm_device *dev = crtc->dev;
7962 struct drm_i915_private *dev_priv = dev->dev_private;
7963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7964 uint32_t cntl;
7965
7966 if (base != intel_crtc->cursor_base) {
7967 /* On these chipsets we can only modify the base whilst
7968 * the cursor is disabled.
7969 */
7970 if (intel_crtc->cursor_cntl) {
7971 I915_WRITE(_CURACNTR, 0);
7972 POSTING_READ(_CURACNTR);
7973 intel_crtc->cursor_cntl = 0;
7974 }
7975
7976 I915_WRITE(_CURABASE, base);
7977 POSTING_READ(_CURABASE);
7978 }
7979
7980 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7981 cntl = 0;
7982 if (base)
7983 cntl = (CURSOR_ENABLE |
7984 CURSOR_GAMMA_ENABLE |
7985 CURSOR_FORMAT_ARGB);
7986 if (intel_crtc->cursor_cntl != cntl) {
7987 I915_WRITE(_CURACNTR, cntl);
7988 POSTING_READ(_CURACNTR);
7989 intel_crtc->cursor_cntl = cntl;
7990 }
7991 }
7992
7993 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7994 {
7995 struct drm_device *dev = crtc->dev;
7996 struct drm_i915_private *dev_priv = dev->dev_private;
7997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7998 int pipe = intel_crtc->pipe;
7999 uint32_t cntl;
8000
8001 cntl = 0;
8002 if (base) {
8003 cntl = MCURSOR_GAMMA_ENABLE;
8004 switch (intel_crtc->cursor_width) {
8005 case 64:
8006 cntl |= CURSOR_MODE_64_ARGB_AX;
8007 break;
8008 case 128:
8009 cntl |= CURSOR_MODE_128_ARGB_AX;
8010 break;
8011 case 256:
8012 cntl |= CURSOR_MODE_256_ARGB_AX;
8013 break;
8014 default:
8015 WARN_ON(1);
8016 return;
8017 }
8018 cntl |= pipe << 28; /* Connect to correct pipe */
8019 }
8020 if (intel_crtc->cursor_cntl != cntl) {
8021 I915_WRITE(CURCNTR(pipe), cntl);
8022 POSTING_READ(CURCNTR(pipe));
8023 intel_crtc->cursor_cntl = cntl;
8024 }
8025
8026 /* and commit changes on next vblank */
8027 I915_WRITE(CURBASE(pipe), base);
8028 POSTING_READ(CURBASE(pipe));
8029 }
8030
8031 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
8032 {
8033 struct drm_device *dev = crtc->dev;
8034 struct drm_i915_private *dev_priv = dev->dev_private;
8035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8036 int pipe = intel_crtc->pipe;
8037 uint32_t cntl;
8038
8039 cntl = 0;
8040 if (base) {
8041 cntl = MCURSOR_GAMMA_ENABLE;
8042 switch (intel_crtc->cursor_width) {
8043 case 64:
8044 cntl |= CURSOR_MODE_64_ARGB_AX;
8045 break;
8046 case 128:
8047 cntl |= CURSOR_MODE_128_ARGB_AX;
8048 break;
8049 case 256:
8050 cntl |= CURSOR_MODE_256_ARGB_AX;
8051 break;
8052 default:
8053 WARN_ON(1);
8054 return;
8055 }
8056 }
8057 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8058 cntl |= CURSOR_PIPE_CSC_ENABLE;
8059
8060 if (intel_crtc->cursor_cntl != cntl) {
8061 I915_WRITE(CURCNTR(pipe), cntl);
8062 POSTING_READ(CURCNTR(pipe));
8063 intel_crtc->cursor_cntl = cntl;
8064 }
8065
8066 /* and commit changes on next vblank */
8067 I915_WRITE(CURBASE(pipe), base);
8068 POSTING_READ(CURBASE(pipe));
8069 }
8070
8071 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8072 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8073 bool on)
8074 {
8075 struct drm_device *dev = crtc->dev;
8076 struct drm_i915_private *dev_priv = dev->dev_private;
8077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8078 int pipe = intel_crtc->pipe;
8079 int x = crtc->cursor_x;
8080 int y = crtc->cursor_y;
8081 u32 base = 0, pos = 0;
8082
8083 if (on)
8084 base = intel_crtc->cursor_addr;
8085
8086 if (x >= intel_crtc->config.pipe_src_w)
8087 base = 0;
8088
8089 if (y >= intel_crtc->config.pipe_src_h)
8090 base = 0;
8091
8092 if (x < 0) {
8093 if (x + intel_crtc->cursor_width <= 0)
8094 base = 0;
8095
8096 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8097 x = -x;
8098 }
8099 pos |= x << CURSOR_X_SHIFT;
8100
8101 if (y < 0) {
8102 if (y + intel_crtc->cursor_height <= 0)
8103 base = 0;
8104
8105 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8106 y = -y;
8107 }
8108 pos |= y << CURSOR_Y_SHIFT;
8109
8110 if (base == 0 && intel_crtc->cursor_base == 0)
8111 return;
8112
8113 I915_WRITE(CURPOS(pipe), pos);
8114
8115 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
8116 ivb_update_cursor(crtc, base);
8117 else if (IS_845G(dev) || IS_I865G(dev))
8118 i845_update_cursor(crtc, base);
8119 else
8120 i9xx_update_cursor(crtc, base);
8121 intel_crtc->cursor_base = base;
8122 }
8123
8124 /*
8125 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8126 *
8127 * Note that the object's reference will be consumed if the update fails. If
8128 * the update succeeds, the reference of the old object (if any) will be
8129 * consumed.
8130 */
8131 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8132 struct drm_i915_gem_object *obj,
8133 uint32_t width, uint32_t height)
8134 {
8135 struct drm_device *dev = crtc->dev;
8136 struct drm_i915_private *dev_priv = dev->dev_private;
8137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8138 enum pipe pipe = intel_crtc->pipe;
8139 unsigned old_width;
8140 uint32_t addr;
8141 int ret;
8142
8143 /* if we want to turn off the cursor ignore width and height */
8144 if (!obj) {
8145 DRM_DEBUG_KMS("cursor off\n");
8146 addr = 0;
8147 obj = NULL;
8148 mutex_lock(&dev->struct_mutex);
8149 goto finish;
8150 }
8151
8152 /* Check for which cursor types we support */
8153 if (!((width == 64 && height == 64) ||
8154 (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8155 (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8156 DRM_DEBUG("Cursor dimension not supported\n");
8157 return -EINVAL;
8158 }
8159
8160 if (obj->base.size < width * height * 4) {
8161 DRM_DEBUG_KMS("buffer is too small\n");
8162 ret = -ENOMEM;
8163 goto fail;
8164 }
8165
8166 /* we only need to pin inside GTT if cursor is non-phy */
8167 mutex_lock(&dev->struct_mutex);
8168 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8169 unsigned alignment;
8170
8171 if (obj->tiling_mode) {
8172 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8173 ret = -EINVAL;
8174 goto fail_locked;
8175 }
8176
8177 /* Note that the w/a also requires 2 PTE of padding following
8178 * the bo. We currently fill all unused PTE with the shadow
8179 * page and so we should always have valid PTE following the
8180 * cursor preventing the VT-d warning.
8181 */
8182 alignment = 0;
8183 if (need_vtd_wa(dev))
8184 alignment = 64*1024;
8185
8186 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8187 if (ret) {
8188 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8189 goto fail_locked;
8190 }
8191
8192 ret = i915_gem_object_put_fence(obj);
8193 if (ret) {
8194 DRM_DEBUG_KMS("failed to release fence for cursor");
8195 goto fail_unpin;
8196 }
8197
8198 addr = i915_gem_obj_ggtt_offset(obj);
8199 } else {
8200 int align = IS_I830(dev) ? 16 * 1024 : 256;
8201 ret = i915_gem_object_attach_phys(obj, align);
8202 if (ret) {
8203 DRM_DEBUG_KMS("failed to attach phys object\n");
8204 goto fail_locked;
8205 }
8206 addr = obj->phys_handle->busaddr;
8207 }
8208
8209 if (IS_GEN2(dev))
8210 I915_WRITE(CURSIZE, (height << 12) | width);
8211
8212 finish:
8213 if (intel_crtc->cursor_bo) {
8214 if (!INTEL_INFO(dev)->cursor_needs_physical)
8215 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8216 }
8217
8218 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8219 INTEL_FRONTBUFFER_CURSOR(pipe));
8220 mutex_unlock(&dev->struct_mutex);
8221
8222 old_width = intel_crtc->cursor_width;
8223
8224 intel_crtc->cursor_addr = addr;
8225 intel_crtc->cursor_bo = obj;
8226 intel_crtc->cursor_width = width;
8227 intel_crtc->cursor_height = height;
8228
8229 if (intel_crtc->active) {
8230 if (old_width != width)
8231 intel_update_watermarks(crtc);
8232 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8233 }
8234
8235 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8236
8237 return 0;
8238 fail_unpin:
8239 i915_gem_object_unpin_from_display_plane(obj);
8240 fail_locked:
8241 mutex_unlock(&dev->struct_mutex);
8242 fail:
8243 drm_gem_object_unreference_unlocked(&obj->base);
8244 return ret;
8245 }
8246
8247 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8248 u16 *blue, uint32_t start, uint32_t size)
8249 {
8250 int end = (start + size > 256) ? 256 : start + size, i;
8251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8252
8253 for (i = start; i < end; i++) {
8254 intel_crtc->lut_r[i] = red[i] >> 8;
8255 intel_crtc->lut_g[i] = green[i] >> 8;
8256 intel_crtc->lut_b[i] = blue[i] >> 8;
8257 }
8258
8259 intel_crtc_load_lut(crtc);
8260 }
8261
8262 /* VESA 640x480x72Hz mode to set on the pipe */
8263 static struct drm_display_mode load_detect_mode = {
8264 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8265 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8266 };
8267
8268 struct drm_framebuffer *
8269 __intel_framebuffer_create(struct drm_device *dev,
8270 struct drm_mode_fb_cmd2 *mode_cmd,
8271 struct drm_i915_gem_object *obj)
8272 {
8273 struct intel_framebuffer *intel_fb;
8274 int ret;
8275
8276 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8277 if (!intel_fb) {
8278 drm_gem_object_unreference_unlocked(&obj->base);
8279 return ERR_PTR(-ENOMEM);
8280 }
8281
8282 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8283 if (ret)
8284 goto err;
8285
8286 return &intel_fb->base;
8287 err:
8288 drm_gem_object_unreference_unlocked(&obj->base);
8289 kfree(intel_fb);
8290
8291 return ERR_PTR(ret);
8292 }
8293
8294 static struct drm_framebuffer *
8295 intel_framebuffer_create(struct drm_device *dev,
8296 struct drm_mode_fb_cmd2 *mode_cmd,
8297 struct drm_i915_gem_object *obj)
8298 {
8299 struct drm_framebuffer *fb;
8300 int ret;
8301
8302 ret = i915_mutex_lock_interruptible(dev);
8303 if (ret)
8304 return ERR_PTR(ret);
8305 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8306 mutex_unlock(&dev->struct_mutex);
8307
8308 return fb;
8309 }
8310
8311 static u32
8312 intel_framebuffer_pitch_for_width(int width, int bpp)
8313 {
8314 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8315 return ALIGN(pitch, 64);
8316 }
8317
8318 static u32
8319 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8320 {
8321 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8322 return PAGE_ALIGN(pitch * mode->vdisplay);
8323 }
8324
8325 static struct drm_framebuffer *
8326 intel_framebuffer_create_for_mode(struct drm_device *dev,
8327 struct drm_display_mode *mode,
8328 int depth, int bpp)
8329 {
8330 struct drm_i915_gem_object *obj;
8331 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8332
8333 obj = i915_gem_alloc_object(dev,
8334 intel_framebuffer_size_for_mode(mode, bpp));
8335 if (obj == NULL)
8336 return ERR_PTR(-ENOMEM);
8337
8338 mode_cmd.width = mode->hdisplay;
8339 mode_cmd.height = mode->vdisplay;
8340 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8341 bpp);
8342 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8343
8344 return intel_framebuffer_create(dev, &mode_cmd, obj);
8345 }
8346
8347 static struct drm_framebuffer *
8348 mode_fits_in_fbdev(struct drm_device *dev,
8349 struct drm_display_mode *mode)
8350 {
8351 #ifdef CONFIG_DRM_I915_FBDEV
8352 struct drm_i915_private *dev_priv = dev->dev_private;
8353 struct drm_i915_gem_object *obj;
8354 struct drm_framebuffer *fb;
8355
8356 if (!dev_priv->fbdev)
8357 return NULL;
8358
8359 if (!dev_priv->fbdev->fb)
8360 return NULL;
8361
8362 obj = dev_priv->fbdev->fb->obj;
8363 BUG_ON(!obj);
8364
8365 fb = &dev_priv->fbdev->fb->base;
8366 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8367 fb->bits_per_pixel))
8368 return NULL;
8369
8370 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8371 return NULL;
8372
8373 return fb;
8374 #else
8375 return NULL;
8376 #endif
8377 }
8378
8379 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8380 struct drm_display_mode *mode,
8381 struct intel_load_detect_pipe *old,
8382 struct drm_modeset_acquire_ctx *ctx)
8383 {
8384 struct intel_crtc *intel_crtc;
8385 struct intel_encoder *intel_encoder =
8386 intel_attached_encoder(connector);
8387 struct drm_crtc *possible_crtc;
8388 struct drm_encoder *encoder = &intel_encoder->base;
8389 struct drm_crtc *crtc = NULL;
8390 struct drm_device *dev = encoder->dev;
8391 struct drm_framebuffer *fb;
8392 struct drm_mode_config *config = &dev->mode_config;
8393 int ret, i = -1;
8394
8395 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8396 connector->base.id, connector->name,
8397 encoder->base.id, encoder->name);
8398
8399 drm_modeset_acquire_init(ctx, 0);
8400
8401 retry:
8402 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8403 if (ret)
8404 goto fail_unlock;
8405
8406 /*
8407 * Algorithm gets a little messy:
8408 *
8409 * - if the connector already has an assigned crtc, use it (but make
8410 * sure it's on first)
8411 *
8412 * - try to find the first unused crtc that can drive this connector,
8413 * and use that if we find one
8414 */
8415
8416 /* See if we already have a CRTC for this connector */
8417 if (encoder->crtc) {
8418 crtc = encoder->crtc;
8419
8420 ret = drm_modeset_lock(&crtc->mutex, ctx);
8421 if (ret)
8422 goto fail_unlock;
8423
8424 old->dpms_mode = connector->dpms;
8425 old->load_detect_temp = false;
8426
8427 /* Make sure the crtc and connector are running */
8428 if (connector->dpms != DRM_MODE_DPMS_ON)
8429 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8430
8431 return true;
8432 }
8433
8434 /* Find an unused one (if possible) */
8435 for_each_crtc(dev, possible_crtc) {
8436 i++;
8437 if (!(encoder->possible_crtcs & (1 << i)))
8438 continue;
8439 if (!possible_crtc->enabled) {
8440 crtc = possible_crtc;
8441 break;
8442 }
8443 }
8444
8445 /*
8446 * If we didn't find an unused CRTC, don't use any.
8447 */
8448 if (!crtc) {
8449 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8450 goto fail_unlock;
8451 }
8452
8453 ret = drm_modeset_lock(&crtc->mutex, ctx);
8454 if (ret)
8455 goto fail_unlock;
8456 intel_encoder->new_crtc = to_intel_crtc(crtc);
8457 to_intel_connector(connector)->new_encoder = intel_encoder;
8458
8459 intel_crtc = to_intel_crtc(crtc);
8460 intel_crtc->new_enabled = true;
8461 intel_crtc->new_config = &intel_crtc->config;
8462 old->dpms_mode = connector->dpms;
8463 old->load_detect_temp = true;
8464 old->release_fb = NULL;
8465
8466 if (!mode)
8467 mode = &load_detect_mode;
8468
8469 /* We need a framebuffer large enough to accommodate all accesses
8470 * that the plane may generate whilst we perform load detection.
8471 * We can not rely on the fbcon either being present (we get called
8472 * during its initialisation to detect all boot displays, or it may
8473 * not even exist) or that it is large enough to satisfy the
8474 * requested mode.
8475 */
8476 fb = mode_fits_in_fbdev(dev, mode);
8477 if (fb == NULL) {
8478 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8479 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8480 old->release_fb = fb;
8481 } else
8482 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8483 if (IS_ERR(fb)) {
8484 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8485 goto fail;
8486 }
8487
8488 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8489 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8490 if (old->release_fb)
8491 old->release_fb->funcs->destroy(old->release_fb);
8492 goto fail;
8493 }
8494
8495 /* let the connector get through one full cycle before testing */
8496 intel_wait_for_vblank(dev, intel_crtc->pipe);
8497 return true;
8498
8499 fail:
8500 intel_crtc->new_enabled = crtc->enabled;
8501 if (intel_crtc->new_enabled)
8502 intel_crtc->new_config = &intel_crtc->config;
8503 else
8504 intel_crtc->new_config = NULL;
8505 fail_unlock:
8506 if (ret == -EDEADLK) {
8507 drm_modeset_backoff(ctx);
8508 goto retry;
8509 }
8510
8511 drm_modeset_drop_locks(ctx);
8512 drm_modeset_acquire_fini(ctx);
8513
8514 return false;
8515 }
8516
8517 void intel_release_load_detect_pipe(struct drm_connector *connector,
8518 struct intel_load_detect_pipe *old,
8519 struct drm_modeset_acquire_ctx *ctx)
8520 {
8521 struct intel_encoder *intel_encoder =
8522 intel_attached_encoder(connector);
8523 struct drm_encoder *encoder = &intel_encoder->base;
8524 struct drm_crtc *crtc = encoder->crtc;
8525 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8526
8527 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8528 connector->base.id, connector->name,
8529 encoder->base.id, encoder->name);
8530
8531 if (old->load_detect_temp) {
8532 to_intel_connector(connector)->new_encoder = NULL;
8533 intel_encoder->new_crtc = NULL;
8534 intel_crtc->new_enabled = false;
8535 intel_crtc->new_config = NULL;
8536 intel_set_mode(crtc, NULL, 0, 0, NULL);
8537
8538 if (old->release_fb) {
8539 drm_framebuffer_unregister_private(old->release_fb);
8540 drm_framebuffer_unreference(old->release_fb);
8541 }
8542
8543 goto unlock;
8544 return;
8545 }
8546
8547 /* Switch crtc and encoder back off if necessary */
8548 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8549 connector->funcs->dpms(connector, old->dpms_mode);
8550
8551 unlock:
8552 drm_modeset_drop_locks(ctx);
8553 drm_modeset_acquire_fini(ctx);
8554 }
8555
8556 static int i9xx_pll_refclk(struct drm_device *dev,
8557 const struct intel_crtc_config *pipe_config)
8558 {
8559 struct drm_i915_private *dev_priv = dev->dev_private;
8560 u32 dpll = pipe_config->dpll_hw_state.dpll;
8561
8562 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8563 return dev_priv->vbt.lvds_ssc_freq;
8564 else if (HAS_PCH_SPLIT(dev))
8565 return 120000;
8566 else if (!IS_GEN2(dev))
8567 return 96000;
8568 else
8569 return 48000;
8570 }
8571
8572 /* Returns the clock of the currently programmed mode of the given pipe. */
8573 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8574 struct intel_crtc_config *pipe_config)
8575 {
8576 struct drm_device *dev = crtc->base.dev;
8577 struct drm_i915_private *dev_priv = dev->dev_private;
8578 int pipe = pipe_config->cpu_transcoder;
8579 u32 dpll = pipe_config->dpll_hw_state.dpll;
8580 u32 fp;
8581 intel_clock_t clock;
8582 int refclk = i9xx_pll_refclk(dev, pipe_config);
8583
8584 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8585 fp = pipe_config->dpll_hw_state.fp0;
8586 else
8587 fp = pipe_config->dpll_hw_state.fp1;
8588
8589 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8590 if (IS_PINEVIEW(dev)) {
8591 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8592 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8593 } else {
8594 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8595 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8596 }
8597
8598 if (!IS_GEN2(dev)) {
8599 if (IS_PINEVIEW(dev))
8600 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8601 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8602 else
8603 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8604 DPLL_FPA01_P1_POST_DIV_SHIFT);
8605
8606 switch (dpll & DPLL_MODE_MASK) {
8607 case DPLLB_MODE_DAC_SERIAL:
8608 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8609 5 : 10;
8610 break;
8611 case DPLLB_MODE_LVDS:
8612 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8613 7 : 14;
8614 break;
8615 default:
8616 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8617 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8618 return;
8619 }
8620
8621 if (IS_PINEVIEW(dev))
8622 pineview_clock(refclk, &clock);
8623 else
8624 i9xx_clock(refclk, &clock);
8625 } else {
8626 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8627 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8628
8629 if (is_lvds) {
8630 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8631 DPLL_FPA01_P1_POST_DIV_SHIFT);
8632
8633 if (lvds & LVDS_CLKB_POWER_UP)
8634 clock.p2 = 7;
8635 else
8636 clock.p2 = 14;
8637 } else {
8638 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8639 clock.p1 = 2;
8640 else {
8641 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8642 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8643 }
8644 if (dpll & PLL_P2_DIVIDE_BY_4)
8645 clock.p2 = 4;
8646 else
8647 clock.p2 = 2;
8648 }
8649
8650 i9xx_clock(refclk, &clock);
8651 }
8652
8653 /*
8654 * This value includes pixel_multiplier. We will use
8655 * port_clock to compute adjusted_mode.crtc_clock in the
8656 * encoder's get_config() function.
8657 */
8658 pipe_config->port_clock = clock.dot;
8659 }
8660
8661 int intel_dotclock_calculate(int link_freq,
8662 const struct intel_link_m_n *m_n)
8663 {
8664 /*
8665 * The calculation for the data clock is:
8666 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8667 * But we want to avoid losing precison if possible, so:
8668 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8669 *
8670 * and the link clock is simpler:
8671 * link_clock = (m * link_clock) / n
8672 */
8673
8674 if (!m_n->link_n)
8675 return 0;
8676
8677 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8678 }
8679
8680 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8681 struct intel_crtc_config *pipe_config)
8682 {
8683 struct drm_device *dev = crtc->base.dev;
8684
8685 /* read out port_clock from the DPLL */
8686 i9xx_crtc_clock_get(crtc, pipe_config);
8687
8688 /*
8689 * This value does not include pixel_multiplier.
8690 * We will check that port_clock and adjusted_mode.crtc_clock
8691 * agree once we know their relationship in the encoder's
8692 * get_config() function.
8693 */
8694 pipe_config->adjusted_mode.crtc_clock =
8695 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8696 &pipe_config->fdi_m_n);
8697 }
8698
8699 /** Returns the currently programmed mode of the given pipe. */
8700 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8701 struct drm_crtc *crtc)
8702 {
8703 struct drm_i915_private *dev_priv = dev->dev_private;
8704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8705 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8706 struct drm_display_mode *mode;
8707 struct intel_crtc_config pipe_config;
8708 int htot = I915_READ(HTOTAL(cpu_transcoder));
8709 int hsync = I915_READ(HSYNC(cpu_transcoder));
8710 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8711 int vsync = I915_READ(VSYNC(cpu_transcoder));
8712 enum pipe pipe = intel_crtc->pipe;
8713
8714 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8715 if (!mode)
8716 return NULL;
8717
8718 /*
8719 * Construct a pipe_config sufficient for getting the clock info
8720 * back out of crtc_clock_get.
8721 *
8722 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8723 * to use a real value here instead.
8724 */
8725 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8726 pipe_config.pixel_multiplier = 1;
8727 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8728 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8729 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8730 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8731
8732 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8733 mode->hdisplay = (htot & 0xffff) + 1;
8734 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8735 mode->hsync_start = (hsync & 0xffff) + 1;
8736 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8737 mode->vdisplay = (vtot & 0xffff) + 1;
8738 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8739 mode->vsync_start = (vsync & 0xffff) + 1;
8740 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8741
8742 drm_mode_set_name(mode);
8743
8744 return mode;
8745 }
8746
8747 static void intel_increase_pllclock(struct drm_device *dev,
8748 enum pipe pipe)
8749 {
8750 struct drm_i915_private *dev_priv = dev->dev_private;
8751 int dpll_reg = DPLL(pipe);
8752 int dpll;
8753
8754 if (HAS_PCH_SPLIT(dev))
8755 return;
8756
8757 if (!dev_priv->lvds_downclock_avail)
8758 return;
8759
8760 dpll = I915_READ(dpll_reg);
8761 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8762 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8763
8764 assert_panel_unlocked(dev_priv, pipe);
8765
8766 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8767 I915_WRITE(dpll_reg, dpll);
8768 intel_wait_for_vblank(dev, pipe);
8769
8770 dpll = I915_READ(dpll_reg);
8771 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8772 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8773 }
8774 }
8775
8776 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8777 {
8778 struct drm_device *dev = crtc->dev;
8779 struct drm_i915_private *dev_priv = dev->dev_private;
8780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8781
8782 if (HAS_PCH_SPLIT(dev))
8783 return;
8784
8785 if (!dev_priv->lvds_downclock_avail)
8786 return;
8787
8788 /*
8789 * Since this is called by a timer, we should never get here in
8790 * the manual case.
8791 */
8792 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8793 int pipe = intel_crtc->pipe;
8794 int dpll_reg = DPLL(pipe);
8795 int dpll;
8796
8797 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8798
8799 assert_panel_unlocked(dev_priv, pipe);
8800
8801 dpll = I915_READ(dpll_reg);
8802 dpll |= DISPLAY_RATE_SELECT_FPA1;
8803 I915_WRITE(dpll_reg, dpll);
8804 intel_wait_for_vblank(dev, pipe);
8805 dpll = I915_READ(dpll_reg);
8806 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8807 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8808 }
8809
8810 }
8811
8812 void intel_mark_busy(struct drm_device *dev)
8813 {
8814 struct drm_i915_private *dev_priv = dev->dev_private;
8815
8816 if (dev_priv->mm.busy)
8817 return;
8818
8819 intel_runtime_pm_get(dev_priv);
8820 i915_update_gfx_val(dev_priv);
8821 dev_priv->mm.busy = true;
8822 }
8823
8824 void intel_mark_idle(struct drm_device *dev)
8825 {
8826 struct drm_i915_private *dev_priv = dev->dev_private;
8827 struct drm_crtc *crtc;
8828
8829 if (!dev_priv->mm.busy)
8830 return;
8831
8832 dev_priv->mm.busy = false;
8833
8834 if (!i915.powersave)
8835 goto out;
8836
8837 for_each_crtc(dev, crtc) {
8838 if (!crtc->primary->fb)
8839 continue;
8840
8841 intel_decrease_pllclock(crtc);
8842 }
8843
8844 if (INTEL_INFO(dev)->gen >= 6)
8845 gen6_rps_idle(dev->dev_private);
8846
8847 out:
8848 intel_runtime_pm_put(dev_priv);
8849 }
8850
8851
8852 /**
8853 * intel_mark_fb_busy - mark given planes as busy
8854 * @dev: DRM device
8855 * @frontbuffer_bits: bits for the affected planes
8856 * @ring: optional ring for asynchronous commands
8857 *
8858 * This function gets called every time the screen contents change. It can be
8859 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
8860 */
8861 static void intel_mark_fb_busy(struct drm_device *dev,
8862 unsigned frontbuffer_bits,
8863 struct intel_engine_cs *ring)
8864 {
8865 enum pipe pipe;
8866
8867 if (!i915.powersave)
8868 return;
8869
8870 for_each_pipe(pipe) {
8871 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
8872 continue;
8873
8874 intel_increase_pllclock(dev, pipe);
8875 if (ring && intel_fbc_enabled(dev))
8876 ring->fbc_dirty = true;
8877 }
8878 }
8879
8880 /**
8881 * intel_fb_obj_invalidate - invalidate frontbuffer object
8882 * @obj: GEM object to invalidate
8883 * @ring: set for asynchronous rendering
8884 *
8885 * This function gets called every time rendering on the given object starts and
8886 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
8887 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
8888 * until the rendering completes or a flip on this frontbuffer plane is
8889 * scheduled.
8890 */
8891 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
8892 struct intel_engine_cs *ring)
8893 {
8894 struct drm_device *dev = obj->base.dev;
8895 struct drm_i915_private *dev_priv = dev->dev_private;
8896
8897 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8898
8899 if (!obj->frontbuffer_bits)
8900 return;
8901
8902 if (ring) {
8903 mutex_lock(&dev_priv->fb_tracking.lock);
8904 dev_priv->fb_tracking.busy_bits
8905 |= obj->frontbuffer_bits;
8906 dev_priv->fb_tracking.flip_bits
8907 &= ~obj->frontbuffer_bits;
8908 mutex_unlock(&dev_priv->fb_tracking.lock);
8909 }
8910
8911 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
8912
8913 intel_edp_psr_exit(dev);
8914 }
8915
8916 /**
8917 * intel_frontbuffer_flush - flush frontbuffer
8918 * @dev: DRM device
8919 * @frontbuffer_bits: frontbuffer plane tracking bits
8920 *
8921 * This function gets called every time rendering on the given planes has
8922 * completed and frontbuffer caching can be started again. Flushes will get
8923 * delayed if they're blocked by some oustanding asynchronous rendering.
8924 *
8925 * Can be called without any locks held.
8926 */
8927 void intel_frontbuffer_flush(struct drm_device *dev,
8928 unsigned frontbuffer_bits)
8929 {
8930 struct drm_i915_private *dev_priv = dev->dev_private;
8931
8932 /* Delay flushing when rings are still busy.*/
8933 mutex_lock(&dev_priv->fb_tracking.lock);
8934 frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
8935 mutex_unlock(&dev_priv->fb_tracking.lock);
8936
8937 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
8938
8939 intel_edp_psr_exit(dev);
8940 }
8941
8942 /**
8943 * intel_fb_obj_flush - flush frontbuffer object
8944 * @obj: GEM object to flush
8945 * @retire: set when retiring asynchronous rendering
8946 *
8947 * This function gets called every time rendering on the given object has
8948 * completed and frontbuffer caching can be started again. If @retire is true
8949 * then any delayed flushes will be unblocked.
8950 */
8951 void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
8952 bool retire)
8953 {
8954 struct drm_device *dev = obj->base.dev;
8955 struct drm_i915_private *dev_priv = dev->dev_private;
8956 unsigned frontbuffer_bits;
8957
8958 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8959
8960 if (!obj->frontbuffer_bits)
8961 return;
8962
8963 frontbuffer_bits = obj->frontbuffer_bits;
8964
8965 if (retire) {
8966 mutex_lock(&dev_priv->fb_tracking.lock);
8967 /* Filter out new bits since rendering started. */
8968 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
8969
8970 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
8971 mutex_unlock(&dev_priv->fb_tracking.lock);
8972 }
8973
8974 intel_frontbuffer_flush(dev, frontbuffer_bits);
8975 }
8976
8977 /**
8978 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
8979 * @dev: DRM device
8980 * @frontbuffer_bits: frontbuffer plane tracking bits
8981 *
8982 * This function gets called after scheduling a flip on @obj. The actual
8983 * frontbuffer flushing will be delayed until completion is signalled with
8984 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
8985 * flush will be cancelled.
8986 *
8987 * Can be called without any locks held.
8988 */
8989 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
8990 unsigned frontbuffer_bits)
8991 {
8992 struct drm_i915_private *dev_priv = dev->dev_private;
8993
8994 mutex_lock(&dev_priv->fb_tracking.lock);
8995 dev_priv->fb_tracking.flip_bits
8996 |= frontbuffer_bits;
8997 mutex_unlock(&dev_priv->fb_tracking.lock);
8998 }
8999
9000 /**
9001 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9002 * @dev: DRM device
9003 * @frontbuffer_bits: frontbuffer plane tracking bits
9004 *
9005 * This function gets called after the flip has been latched and will complete
9006 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9007 *
9008 * Can be called without any locks held.
9009 */
9010 void intel_frontbuffer_flip_complete(struct drm_device *dev,
9011 unsigned frontbuffer_bits)
9012 {
9013 struct drm_i915_private *dev_priv = dev->dev_private;
9014
9015 mutex_lock(&dev_priv->fb_tracking.lock);
9016 /* Mask any cancelled flips. */
9017 frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9018 dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9019 mutex_unlock(&dev_priv->fb_tracking.lock);
9020
9021 intel_frontbuffer_flush(dev, frontbuffer_bits);
9022 }
9023
9024 static void intel_crtc_destroy(struct drm_crtc *crtc)
9025 {
9026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9027 struct drm_device *dev = crtc->dev;
9028 struct intel_unpin_work *work;
9029 unsigned long flags;
9030
9031 spin_lock_irqsave(&dev->event_lock, flags);
9032 work = intel_crtc->unpin_work;
9033 intel_crtc->unpin_work = NULL;
9034 spin_unlock_irqrestore(&dev->event_lock, flags);
9035
9036 if (work) {
9037 cancel_work_sync(&work->work);
9038 kfree(work);
9039 }
9040
9041 drm_crtc_cleanup(crtc);
9042
9043 kfree(intel_crtc);
9044 }
9045
9046 static void intel_unpin_work_fn(struct work_struct *__work)
9047 {
9048 struct intel_unpin_work *work =
9049 container_of(__work, struct intel_unpin_work, work);
9050 struct drm_device *dev = work->crtc->dev;
9051 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9052
9053 mutex_lock(&dev->struct_mutex);
9054 intel_unpin_fb_obj(work->old_fb_obj);
9055 drm_gem_object_unreference(&work->pending_flip_obj->base);
9056 drm_gem_object_unreference(&work->old_fb_obj->base);
9057
9058 intel_update_fbc(dev);
9059 mutex_unlock(&dev->struct_mutex);
9060
9061 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9062
9063 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9064 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9065
9066 kfree(work);
9067 }
9068
9069 static void do_intel_finish_page_flip(struct drm_device *dev,
9070 struct drm_crtc *crtc)
9071 {
9072 struct drm_i915_private *dev_priv = dev->dev_private;
9073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9074 struct intel_unpin_work *work;
9075 unsigned long flags;
9076
9077 /* Ignore early vblank irqs */
9078 if (intel_crtc == NULL)
9079 return;
9080
9081 spin_lock_irqsave(&dev->event_lock, flags);
9082 work = intel_crtc->unpin_work;
9083
9084 /* Ensure we don't miss a work->pending update ... */
9085 smp_rmb();
9086
9087 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9088 spin_unlock_irqrestore(&dev->event_lock, flags);
9089 return;
9090 }
9091
9092 /* and that the unpin work is consistent wrt ->pending. */
9093 smp_rmb();
9094
9095 intel_crtc->unpin_work = NULL;
9096
9097 if (work->event)
9098 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
9099
9100 drm_crtc_vblank_put(crtc);
9101
9102 spin_unlock_irqrestore(&dev->event_lock, flags);
9103
9104 wake_up_all(&dev_priv->pending_flip_queue);
9105
9106 queue_work(dev_priv->wq, &work->work);
9107
9108 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
9109 }
9110
9111 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9112 {
9113 struct drm_i915_private *dev_priv = dev->dev_private;
9114 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9115
9116 do_intel_finish_page_flip(dev, crtc);
9117 }
9118
9119 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9120 {
9121 struct drm_i915_private *dev_priv = dev->dev_private;
9122 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9123
9124 do_intel_finish_page_flip(dev, crtc);
9125 }
9126
9127 /* Is 'a' after or equal to 'b'? */
9128 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9129 {
9130 return !((a - b) & 0x80000000);
9131 }
9132
9133 static bool page_flip_finished(struct intel_crtc *crtc)
9134 {
9135 struct drm_device *dev = crtc->base.dev;
9136 struct drm_i915_private *dev_priv = dev->dev_private;
9137
9138 /*
9139 * The relevant registers doen't exist on pre-ctg.
9140 * As the flip done interrupt doesn't trigger for mmio
9141 * flips on gmch platforms, a flip count check isn't
9142 * really needed there. But since ctg has the registers,
9143 * include it in the check anyway.
9144 */
9145 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9146 return true;
9147
9148 /*
9149 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9150 * used the same base address. In that case the mmio flip might
9151 * have completed, but the CS hasn't even executed the flip yet.
9152 *
9153 * A flip count check isn't enough as the CS might have updated
9154 * the base address just after start of vblank, but before we
9155 * managed to process the interrupt. This means we'd complete the
9156 * CS flip too soon.
9157 *
9158 * Combining both checks should get us a good enough result. It may
9159 * still happen that the CS flip has been executed, but has not
9160 * yet actually completed. But in case the base address is the same
9161 * anyway, we don't really care.
9162 */
9163 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9164 crtc->unpin_work->gtt_offset &&
9165 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9166 crtc->unpin_work->flip_count);
9167 }
9168
9169 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9170 {
9171 struct drm_i915_private *dev_priv = dev->dev_private;
9172 struct intel_crtc *intel_crtc =
9173 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9174 unsigned long flags;
9175
9176 /* NB: An MMIO update of the plane base pointer will also
9177 * generate a page-flip completion irq, i.e. every modeset
9178 * is also accompanied by a spurious intel_prepare_page_flip().
9179 */
9180 spin_lock_irqsave(&dev->event_lock, flags);
9181 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9182 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9183 spin_unlock_irqrestore(&dev->event_lock, flags);
9184 }
9185
9186 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9187 {
9188 /* Ensure that the work item is consistent when activating it ... */
9189 smp_wmb();
9190 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9191 /* and that it is marked active as soon as the irq could fire. */
9192 smp_wmb();
9193 }
9194
9195 static int intel_gen2_queue_flip(struct drm_device *dev,
9196 struct drm_crtc *crtc,
9197 struct drm_framebuffer *fb,
9198 struct drm_i915_gem_object *obj,
9199 struct intel_engine_cs *ring,
9200 uint32_t flags)
9201 {
9202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9203 u32 flip_mask;
9204 int ret;
9205
9206 ret = intel_ring_begin(ring, 6);
9207 if (ret)
9208 return ret;
9209
9210 /* Can't queue multiple flips, so wait for the previous
9211 * one to finish before executing the next.
9212 */
9213 if (intel_crtc->plane)
9214 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9215 else
9216 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9217 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9218 intel_ring_emit(ring, MI_NOOP);
9219 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9220 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9221 intel_ring_emit(ring, fb->pitches[0]);
9222 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9223 intel_ring_emit(ring, 0); /* aux display base address, unused */
9224
9225 intel_mark_page_flip_active(intel_crtc);
9226 __intel_ring_advance(ring);
9227 return 0;
9228 }
9229
9230 static int intel_gen3_queue_flip(struct drm_device *dev,
9231 struct drm_crtc *crtc,
9232 struct drm_framebuffer *fb,
9233 struct drm_i915_gem_object *obj,
9234 struct intel_engine_cs *ring,
9235 uint32_t flags)
9236 {
9237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9238 u32 flip_mask;
9239 int ret;
9240
9241 ret = intel_ring_begin(ring, 6);
9242 if (ret)
9243 return ret;
9244
9245 if (intel_crtc->plane)
9246 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9247 else
9248 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9249 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9250 intel_ring_emit(ring, MI_NOOP);
9251 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9252 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9253 intel_ring_emit(ring, fb->pitches[0]);
9254 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9255 intel_ring_emit(ring, MI_NOOP);
9256
9257 intel_mark_page_flip_active(intel_crtc);
9258 __intel_ring_advance(ring);
9259 return 0;
9260 }
9261
9262 static int intel_gen4_queue_flip(struct drm_device *dev,
9263 struct drm_crtc *crtc,
9264 struct drm_framebuffer *fb,
9265 struct drm_i915_gem_object *obj,
9266 struct intel_engine_cs *ring,
9267 uint32_t flags)
9268 {
9269 struct drm_i915_private *dev_priv = dev->dev_private;
9270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9271 uint32_t pf, pipesrc;
9272 int ret;
9273
9274 ret = intel_ring_begin(ring, 4);
9275 if (ret)
9276 return ret;
9277
9278 /* i965+ uses the linear or tiled offsets from the
9279 * Display Registers (which do not change across a page-flip)
9280 * so we need only reprogram the base address.
9281 */
9282 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9283 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9284 intel_ring_emit(ring, fb->pitches[0]);
9285 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9286 obj->tiling_mode);
9287
9288 /* XXX Enabling the panel-fitter across page-flip is so far
9289 * untested on non-native modes, so ignore it for now.
9290 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9291 */
9292 pf = 0;
9293 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9294 intel_ring_emit(ring, pf | pipesrc);
9295
9296 intel_mark_page_flip_active(intel_crtc);
9297 __intel_ring_advance(ring);
9298 return 0;
9299 }
9300
9301 static int intel_gen6_queue_flip(struct drm_device *dev,
9302 struct drm_crtc *crtc,
9303 struct drm_framebuffer *fb,
9304 struct drm_i915_gem_object *obj,
9305 struct intel_engine_cs *ring,
9306 uint32_t flags)
9307 {
9308 struct drm_i915_private *dev_priv = dev->dev_private;
9309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9310 uint32_t pf, pipesrc;
9311 int ret;
9312
9313 ret = intel_ring_begin(ring, 4);
9314 if (ret)
9315 return ret;
9316
9317 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9318 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9319 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9320 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9321
9322 /* Contrary to the suggestions in the documentation,
9323 * "Enable Panel Fitter" does not seem to be required when page
9324 * flipping with a non-native mode, and worse causes a normal
9325 * modeset to fail.
9326 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9327 */
9328 pf = 0;
9329 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9330 intel_ring_emit(ring, pf | pipesrc);
9331
9332 intel_mark_page_flip_active(intel_crtc);
9333 __intel_ring_advance(ring);
9334 return 0;
9335 }
9336
9337 static int intel_gen7_queue_flip(struct drm_device *dev,
9338 struct drm_crtc *crtc,
9339 struct drm_framebuffer *fb,
9340 struct drm_i915_gem_object *obj,
9341 struct intel_engine_cs *ring,
9342 uint32_t flags)
9343 {
9344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9345 uint32_t plane_bit = 0;
9346 int len, ret;
9347
9348 switch (intel_crtc->plane) {
9349 case PLANE_A:
9350 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9351 break;
9352 case PLANE_B:
9353 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9354 break;
9355 case PLANE_C:
9356 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9357 break;
9358 default:
9359 WARN_ONCE(1, "unknown plane in flip command\n");
9360 return -ENODEV;
9361 }
9362
9363 len = 4;
9364 if (ring->id == RCS) {
9365 len += 6;
9366 /*
9367 * On Gen 8, SRM is now taking an extra dword to accommodate
9368 * 48bits addresses, and we need a NOOP for the batch size to
9369 * stay even.
9370 */
9371 if (IS_GEN8(dev))
9372 len += 2;
9373 }
9374
9375 /*
9376 * BSpec MI_DISPLAY_FLIP for IVB:
9377 * "The full packet must be contained within the same cache line."
9378 *
9379 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9380 * cacheline, if we ever start emitting more commands before
9381 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9382 * then do the cacheline alignment, and finally emit the
9383 * MI_DISPLAY_FLIP.
9384 */
9385 ret = intel_ring_cacheline_align(ring);
9386 if (ret)
9387 return ret;
9388
9389 ret = intel_ring_begin(ring, len);
9390 if (ret)
9391 return ret;
9392
9393 /* Unmask the flip-done completion message. Note that the bspec says that
9394 * we should do this for both the BCS and RCS, and that we must not unmask
9395 * more than one flip event at any time (or ensure that one flip message
9396 * can be sent by waiting for flip-done prior to queueing new flips).
9397 * Experimentation says that BCS works despite DERRMR masking all
9398 * flip-done completion events and that unmasking all planes at once
9399 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9400 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9401 */
9402 if (ring->id == RCS) {
9403 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9404 intel_ring_emit(ring, DERRMR);
9405 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9406 DERRMR_PIPEB_PRI_FLIP_DONE |
9407 DERRMR_PIPEC_PRI_FLIP_DONE));
9408 if (IS_GEN8(dev))
9409 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9410 MI_SRM_LRM_GLOBAL_GTT);
9411 else
9412 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9413 MI_SRM_LRM_GLOBAL_GTT);
9414 intel_ring_emit(ring, DERRMR);
9415 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9416 if (IS_GEN8(dev)) {
9417 intel_ring_emit(ring, 0);
9418 intel_ring_emit(ring, MI_NOOP);
9419 }
9420 }
9421
9422 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9423 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9424 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9425 intel_ring_emit(ring, (MI_NOOP));
9426
9427 intel_mark_page_flip_active(intel_crtc);
9428 __intel_ring_advance(ring);
9429 return 0;
9430 }
9431
9432 static bool use_mmio_flip(struct intel_engine_cs *ring,
9433 struct drm_i915_gem_object *obj)
9434 {
9435 /*
9436 * This is not being used for older platforms, because
9437 * non-availability of flip done interrupt forces us to use
9438 * CS flips. Older platforms derive flip done using some clever
9439 * tricks involving the flip_pending status bits and vblank irqs.
9440 * So using MMIO flips there would disrupt this mechanism.
9441 */
9442
9443 if (ring == NULL)
9444 return true;
9445
9446 if (INTEL_INFO(ring->dev)->gen < 5)
9447 return false;
9448
9449 if (i915.use_mmio_flip < 0)
9450 return false;
9451 else if (i915.use_mmio_flip > 0)
9452 return true;
9453 else
9454 return ring != obj->ring;
9455 }
9456
9457 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9458 {
9459 struct drm_device *dev = intel_crtc->base.dev;
9460 struct drm_i915_private *dev_priv = dev->dev_private;
9461 struct intel_framebuffer *intel_fb =
9462 to_intel_framebuffer(intel_crtc->base.primary->fb);
9463 struct drm_i915_gem_object *obj = intel_fb->obj;
9464 u32 dspcntr;
9465 u32 reg;
9466
9467 intel_mark_page_flip_active(intel_crtc);
9468
9469 reg = DSPCNTR(intel_crtc->plane);
9470 dspcntr = I915_READ(reg);
9471
9472 if (INTEL_INFO(dev)->gen >= 4) {
9473 if (obj->tiling_mode != I915_TILING_NONE)
9474 dspcntr |= DISPPLANE_TILED;
9475 else
9476 dspcntr &= ~DISPPLANE_TILED;
9477 }
9478 I915_WRITE(reg, dspcntr);
9479
9480 I915_WRITE(DSPSURF(intel_crtc->plane),
9481 intel_crtc->unpin_work->gtt_offset);
9482 POSTING_READ(DSPSURF(intel_crtc->plane));
9483 }
9484
9485 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9486 {
9487 struct intel_engine_cs *ring;
9488 int ret;
9489
9490 lockdep_assert_held(&obj->base.dev->struct_mutex);
9491
9492 if (!obj->last_write_seqno)
9493 return 0;
9494
9495 ring = obj->ring;
9496
9497 if (i915_seqno_passed(ring->get_seqno(ring, true),
9498 obj->last_write_seqno))
9499 return 0;
9500
9501 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9502 if (ret)
9503 return ret;
9504
9505 if (WARN_ON(!ring->irq_get(ring)))
9506 return 0;
9507
9508 return 1;
9509 }
9510
9511 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9512 {
9513 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9514 struct intel_crtc *intel_crtc;
9515 unsigned long irq_flags;
9516 u32 seqno;
9517
9518 seqno = ring->get_seqno(ring, false);
9519
9520 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9521 for_each_intel_crtc(ring->dev, intel_crtc) {
9522 struct intel_mmio_flip *mmio_flip;
9523
9524 mmio_flip = &intel_crtc->mmio_flip;
9525 if (mmio_flip->seqno == 0)
9526 continue;
9527
9528 if (ring->id != mmio_flip->ring_id)
9529 continue;
9530
9531 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9532 intel_do_mmio_flip(intel_crtc);
9533 mmio_flip->seqno = 0;
9534 ring->irq_put(ring);
9535 }
9536 }
9537 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9538 }
9539
9540 static int intel_queue_mmio_flip(struct drm_device *dev,
9541 struct drm_crtc *crtc,
9542 struct drm_framebuffer *fb,
9543 struct drm_i915_gem_object *obj,
9544 struct intel_engine_cs *ring,
9545 uint32_t flags)
9546 {
9547 struct drm_i915_private *dev_priv = dev->dev_private;
9548 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9549 unsigned long irq_flags;
9550 int ret;
9551
9552 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9553 return -EBUSY;
9554
9555 ret = intel_postpone_flip(obj);
9556 if (ret < 0)
9557 return ret;
9558 if (ret == 0) {
9559 intel_do_mmio_flip(intel_crtc);
9560 return 0;
9561 }
9562
9563 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9564 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9565 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9566 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9567
9568 /*
9569 * Double check to catch cases where irq fired before
9570 * mmio flip data was ready
9571 */
9572 intel_notify_mmio_flip(obj->ring);
9573 return 0;
9574 }
9575
9576 static int intel_default_queue_flip(struct drm_device *dev,
9577 struct drm_crtc *crtc,
9578 struct drm_framebuffer *fb,
9579 struct drm_i915_gem_object *obj,
9580 struct intel_engine_cs *ring,
9581 uint32_t flags)
9582 {
9583 return -ENODEV;
9584 }
9585
9586 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9587 struct drm_framebuffer *fb,
9588 struct drm_pending_vblank_event *event,
9589 uint32_t page_flip_flags)
9590 {
9591 struct drm_device *dev = crtc->dev;
9592 struct drm_i915_private *dev_priv = dev->dev_private;
9593 struct drm_framebuffer *old_fb = crtc->primary->fb;
9594 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9596 enum pipe pipe = intel_crtc->pipe;
9597 struct intel_unpin_work *work;
9598 struct intel_engine_cs *ring;
9599 unsigned long flags;
9600 int ret;
9601
9602 /*
9603 * drm_mode_page_flip_ioctl() should already catch this, but double
9604 * check to be safe. In the future we may enable pageflipping from
9605 * a disabled primary plane.
9606 */
9607 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9608 return -EBUSY;
9609
9610 /* Can't change pixel format via MI display flips. */
9611 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9612 return -EINVAL;
9613
9614 /*
9615 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9616 * Note that pitch changes could also affect these register.
9617 */
9618 if (INTEL_INFO(dev)->gen > 3 &&
9619 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9620 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9621 return -EINVAL;
9622
9623 if (i915_terminally_wedged(&dev_priv->gpu_error))
9624 goto out_hang;
9625
9626 work = kzalloc(sizeof(*work), GFP_KERNEL);
9627 if (work == NULL)
9628 return -ENOMEM;
9629
9630 work->event = event;
9631 work->crtc = crtc;
9632 work->old_fb_obj = intel_fb_obj(old_fb);
9633 INIT_WORK(&work->work, intel_unpin_work_fn);
9634
9635 ret = drm_crtc_vblank_get(crtc);
9636 if (ret)
9637 goto free_work;
9638
9639 /* We borrow the event spin lock for protecting unpin_work */
9640 spin_lock_irqsave(&dev->event_lock, flags);
9641 if (intel_crtc->unpin_work) {
9642 spin_unlock_irqrestore(&dev->event_lock, flags);
9643 kfree(work);
9644 drm_crtc_vblank_put(crtc);
9645
9646 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9647 return -EBUSY;
9648 }
9649 intel_crtc->unpin_work = work;
9650 spin_unlock_irqrestore(&dev->event_lock, flags);
9651
9652 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9653 flush_workqueue(dev_priv->wq);
9654
9655 ret = i915_mutex_lock_interruptible(dev);
9656 if (ret)
9657 goto cleanup;
9658
9659 /* Reference the objects for the scheduled work. */
9660 drm_gem_object_reference(&work->old_fb_obj->base);
9661 drm_gem_object_reference(&obj->base);
9662
9663 crtc->primary->fb = fb;
9664
9665 work->pending_flip_obj = obj;
9666
9667 work->enable_stall_check = true;
9668
9669 atomic_inc(&intel_crtc->unpin_work_count);
9670 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9671
9672 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9673 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9674
9675 if (IS_VALLEYVIEW(dev)) {
9676 ring = &dev_priv->ring[BCS];
9677 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9678 /* vlv: DISPLAY_FLIP fails to change tiling */
9679 ring = NULL;
9680 } else if (IS_IVYBRIDGE(dev)) {
9681 ring = &dev_priv->ring[BCS];
9682 } else if (INTEL_INFO(dev)->gen >= 7) {
9683 ring = obj->ring;
9684 if (ring == NULL || ring->id != RCS)
9685 ring = &dev_priv->ring[BCS];
9686 } else {
9687 ring = &dev_priv->ring[RCS];
9688 }
9689
9690 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9691 if (ret)
9692 goto cleanup_pending;
9693
9694 work->gtt_offset =
9695 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9696
9697 if (use_mmio_flip(ring, obj))
9698 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9699 page_flip_flags);
9700 else
9701 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9702 page_flip_flags);
9703 if (ret)
9704 goto cleanup_unpin;
9705
9706 i915_gem_track_fb(work->old_fb_obj, obj,
9707 INTEL_FRONTBUFFER_PRIMARY(pipe));
9708
9709 intel_disable_fbc(dev);
9710 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9711 mutex_unlock(&dev->struct_mutex);
9712
9713 trace_i915_flip_request(intel_crtc->plane, obj);
9714
9715 return 0;
9716
9717 cleanup_unpin:
9718 intel_unpin_fb_obj(obj);
9719 cleanup_pending:
9720 atomic_dec(&intel_crtc->unpin_work_count);
9721 crtc->primary->fb = old_fb;
9722 drm_gem_object_unreference(&work->old_fb_obj->base);
9723 drm_gem_object_unreference(&obj->base);
9724 mutex_unlock(&dev->struct_mutex);
9725
9726 cleanup:
9727 spin_lock_irqsave(&dev->event_lock, flags);
9728 intel_crtc->unpin_work = NULL;
9729 spin_unlock_irqrestore(&dev->event_lock, flags);
9730
9731 drm_crtc_vblank_put(crtc);
9732 free_work:
9733 kfree(work);
9734
9735 if (ret == -EIO) {
9736 out_hang:
9737 intel_crtc_wait_for_pending_flips(crtc);
9738 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9739 if (ret == 0 && event)
9740 drm_send_vblank_event(dev, pipe, event);
9741 }
9742 return ret;
9743 }
9744
9745 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9746 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9747 .load_lut = intel_crtc_load_lut,
9748 };
9749
9750 /**
9751 * intel_modeset_update_staged_output_state
9752 *
9753 * Updates the staged output configuration state, e.g. after we've read out the
9754 * current hw state.
9755 */
9756 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9757 {
9758 struct intel_crtc *crtc;
9759 struct intel_encoder *encoder;
9760 struct intel_connector *connector;
9761
9762 list_for_each_entry(connector, &dev->mode_config.connector_list,
9763 base.head) {
9764 connector->new_encoder =
9765 to_intel_encoder(connector->base.encoder);
9766 }
9767
9768 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9769 base.head) {
9770 encoder->new_crtc =
9771 to_intel_crtc(encoder->base.crtc);
9772 }
9773
9774 for_each_intel_crtc(dev, crtc) {
9775 crtc->new_enabled = crtc->base.enabled;
9776
9777 if (crtc->new_enabled)
9778 crtc->new_config = &crtc->config;
9779 else
9780 crtc->new_config = NULL;
9781 }
9782 }
9783
9784 /**
9785 * intel_modeset_commit_output_state
9786 *
9787 * This function copies the stage display pipe configuration to the real one.
9788 */
9789 static void intel_modeset_commit_output_state(struct drm_device *dev)
9790 {
9791 struct intel_crtc *crtc;
9792 struct intel_encoder *encoder;
9793 struct intel_connector *connector;
9794
9795 list_for_each_entry(connector, &dev->mode_config.connector_list,
9796 base.head) {
9797 connector->base.encoder = &connector->new_encoder->base;
9798 }
9799
9800 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9801 base.head) {
9802 encoder->base.crtc = &encoder->new_crtc->base;
9803 }
9804
9805 for_each_intel_crtc(dev, crtc) {
9806 crtc->base.enabled = crtc->new_enabled;
9807 }
9808 }
9809
9810 static void
9811 connected_sink_compute_bpp(struct intel_connector *connector,
9812 struct intel_crtc_config *pipe_config)
9813 {
9814 int bpp = pipe_config->pipe_bpp;
9815
9816 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9817 connector->base.base.id,
9818 connector->base.name);
9819
9820 /* Don't use an invalid EDID bpc value */
9821 if (connector->base.display_info.bpc &&
9822 connector->base.display_info.bpc * 3 < bpp) {
9823 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9824 bpp, connector->base.display_info.bpc*3);
9825 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9826 }
9827
9828 /* Clamp bpp to 8 on screens without EDID 1.4 */
9829 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9830 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9831 bpp);
9832 pipe_config->pipe_bpp = 24;
9833 }
9834 }
9835
9836 static int
9837 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9838 struct drm_framebuffer *fb,
9839 struct intel_crtc_config *pipe_config)
9840 {
9841 struct drm_device *dev = crtc->base.dev;
9842 struct intel_connector *connector;
9843 int bpp;
9844
9845 switch (fb->pixel_format) {
9846 case DRM_FORMAT_C8:
9847 bpp = 8*3; /* since we go through a colormap */
9848 break;
9849 case DRM_FORMAT_XRGB1555:
9850 case DRM_FORMAT_ARGB1555:
9851 /* checked in intel_framebuffer_init already */
9852 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9853 return -EINVAL;
9854 case DRM_FORMAT_RGB565:
9855 bpp = 6*3; /* min is 18bpp */
9856 break;
9857 case DRM_FORMAT_XBGR8888:
9858 case DRM_FORMAT_ABGR8888:
9859 /* checked in intel_framebuffer_init already */
9860 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9861 return -EINVAL;
9862 case DRM_FORMAT_XRGB8888:
9863 case DRM_FORMAT_ARGB8888:
9864 bpp = 8*3;
9865 break;
9866 case DRM_FORMAT_XRGB2101010:
9867 case DRM_FORMAT_ARGB2101010:
9868 case DRM_FORMAT_XBGR2101010:
9869 case DRM_FORMAT_ABGR2101010:
9870 /* checked in intel_framebuffer_init already */
9871 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9872 return -EINVAL;
9873 bpp = 10*3;
9874 break;
9875 /* TODO: gen4+ supports 16 bpc floating point, too. */
9876 default:
9877 DRM_DEBUG_KMS("unsupported depth\n");
9878 return -EINVAL;
9879 }
9880
9881 pipe_config->pipe_bpp = bpp;
9882
9883 /* Clamp display bpp to EDID value */
9884 list_for_each_entry(connector, &dev->mode_config.connector_list,
9885 base.head) {
9886 if (!connector->new_encoder ||
9887 connector->new_encoder->new_crtc != crtc)
9888 continue;
9889
9890 connected_sink_compute_bpp(connector, pipe_config);
9891 }
9892
9893 return bpp;
9894 }
9895
9896 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9897 {
9898 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9899 "type: 0x%x flags: 0x%x\n",
9900 mode->crtc_clock,
9901 mode->crtc_hdisplay, mode->crtc_hsync_start,
9902 mode->crtc_hsync_end, mode->crtc_htotal,
9903 mode->crtc_vdisplay, mode->crtc_vsync_start,
9904 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9905 }
9906
9907 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9908 struct intel_crtc_config *pipe_config,
9909 const char *context)
9910 {
9911 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9912 context, pipe_name(crtc->pipe));
9913
9914 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9915 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9916 pipe_config->pipe_bpp, pipe_config->dither);
9917 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9918 pipe_config->has_pch_encoder,
9919 pipe_config->fdi_lanes,
9920 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9921 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9922 pipe_config->fdi_m_n.tu);
9923 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9924 pipe_config->has_dp_encoder,
9925 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9926 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9927 pipe_config->dp_m_n.tu);
9928 DRM_DEBUG_KMS("requested mode:\n");
9929 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9930 DRM_DEBUG_KMS("adjusted mode:\n");
9931 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9932 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9933 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9934 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9935 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9936 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9937 pipe_config->gmch_pfit.control,
9938 pipe_config->gmch_pfit.pgm_ratios,
9939 pipe_config->gmch_pfit.lvds_border_bits);
9940 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9941 pipe_config->pch_pfit.pos,
9942 pipe_config->pch_pfit.size,
9943 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9944 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9945 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9946 }
9947
9948 static bool encoders_cloneable(const struct intel_encoder *a,
9949 const struct intel_encoder *b)
9950 {
9951 /* masks could be asymmetric, so check both ways */
9952 return a == b || (a->cloneable & (1 << b->type) &&
9953 b->cloneable & (1 << a->type));
9954 }
9955
9956 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9957 struct intel_encoder *encoder)
9958 {
9959 struct drm_device *dev = crtc->base.dev;
9960 struct intel_encoder *source_encoder;
9961
9962 list_for_each_entry(source_encoder,
9963 &dev->mode_config.encoder_list, base.head) {
9964 if (source_encoder->new_crtc != crtc)
9965 continue;
9966
9967 if (!encoders_cloneable(encoder, source_encoder))
9968 return false;
9969 }
9970
9971 return true;
9972 }
9973
9974 static bool check_encoder_cloning(struct intel_crtc *crtc)
9975 {
9976 struct drm_device *dev = crtc->base.dev;
9977 struct intel_encoder *encoder;
9978
9979 list_for_each_entry(encoder,
9980 &dev->mode_config.encoder_list, base.head) {
9981 if (encoder->new_crtc != crtc)
9982 continue;
9983
9984 if (!check_single_encoder_cloning(crtc, encoder))
9985 return false;
9986 }
9987
9988 return true;
9989 }
9990
9991 static struct intel_crtc_config *
9992 intel_modeset_pipe_config(struct drm_crtc *crtc,
9993 struct drm_framebuffer *fb,
9994 struct drm_display_mode *mode)
9995 {
9996 struct drm_device *dev = crtc->dev;
9997 struct intel_encoder *encoder;
9998 struct intel_crtc_config *pipe_config;
9999 int plane_bpp, ret = -EINVAL;
10000 bool retry = true;
10001
10002 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10003 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10004 return ERR_PTR(-EINVAL);
10005 }
10006
10007 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10008 if (!pipe_config)
10009 return ERR_PTR(-ENOMEM);
10010
10011 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10012 drm_mode_copy(&pipe_config->requested_mode, mode);
10013
10014 pipe_config->cpu_transcoder =
10015 (enum transcoder) to_intel_crtc(crtc)->pipe;
10016 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10017
10018 /*
10019 * Sanitize sync polarity flags based on requested ones. If neither
10020 * positive or negative polarity is requested, treat this as meaning
10021 * negative polarity.
10022 */
10023 if (!(pipe_config->adjusted_mode.flags &
10024 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10025 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10026
10027 if (!(pipe_config->adjusted_mode.flags &
10028 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10029 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10030
10031 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10032 * plane pixel format and any sink constraints into account. Returns the
10033 * source plane bpp so that dithering can be selected on mismatches
10034 * after encoders and crtc also have had their say. */
10035 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10036 fb, pipe_config);
10037 if (plane_bpp < 0)
10038 goto fail;
10039
10040 /*
10041 * Determine the real pipe dimensions. Note that stereo modes can
10042 * increase the actual pipe size due to the frame doubling and
10043 * insertion of additional space for blanks between the frame. This
10044 * is stored in the crtc timings. We use the requested mode to do this
10045 * computation to clearly distinguish it from the adjusted mode, which
10046 * can be changed by the connectors in the below retry loop.
10047 */
10048 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10049 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10050 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10051
10052 encoder_retry:
10053 /* Ensure the port clock defaults are reset when retrying. */
10054 pipe_config->port_clock = 0;
10055 pipe_config->pixel_multiplier = 1;
10056
10057 /* Fill in default crtc timings, allow encoders to overwrite them. */
10058 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10059
10060 /* Pass our mode to the connectors and the CRTC to give them a chance to
10061 * adjust it according to limitations or connector properties, and also
10062 * a chance to reject the mode entirely.
10063 */
10064 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10065 base.head) {
10066
10067 if (&encoder->new_crtc->base != crtc)
10068 continue;
10069
10070 if (!(encoder->compute_config(encoder, pipe_config))) {
10071 DRM_DEBUG_KMS("Encoder config failure\n");
10072 goto fail;
10073 }
10074 }
10075
10076 /* Set default port clock if not overwritten by the encoder. Needs to be
10077 * done afterwards in case the encoder adjusts the mode. */
10078 if (!pipe_config->port_clock)
10079 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10080 * pipe_config->pixel_multiplier;
10081
10082 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10083 if (ret < 0) {
10084 DRM_DEBUG_KMS("CRTC fixup failed\n");
10085 goto fail;
10086 }
10087
10088 if (ret == RETRY) {
10089 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10090 ret = -EINVAL;
10091 goto fail;
10092 }
10093
10094 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10095 retry = false;
10096 goto encoder_retry;
10097 }
10098
10099 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10100 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10101 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10102
10103 return pipe_config;
10104 fail:
10105 kfree(pipe_config);
10106 return ERR_PTR(ret);
10107 }
10108
10109 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10110 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10111 static void
10112 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10113 unsigned *prepare_pipes, unsigned *disable_pipes)
10114 {
10115 struct intel_crtc *intel_crtc;
10116 struct drm_device *dev = crtc->dev;
10117 struct intel_encoder *encoder;
10118 struct intel_connector *connector;
10119 struct drm_crtc *tmp_crtc;
10120
10121 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10122
10123 /* Check which crtcs have changed outputs connected to them, these need
10124 * to be part of the prepare_pipes mask. We don't (yet) support global
10125 * modeset across multiple crtcs, so modeset_pipes will only have one
10126 * bit set at most. */
10127 list_for_each_entry(connector, &dev->mode_config.connector_list,
10128 base.head) {
10129 if (connector->base.encoder == &connector->new_encoder->base)
10130 continue;
10131
10132 if (connector->base.encoder) {
10133 tmp_crtc = connector->base.encoder->crtc;
10134
10135 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10136 }
10137
10138 if (connector->new_encoder)
10139 *prepare_pipes |=
10140 1 << connector->new_encoder->new_crtc->pipe;
10141 }
10142
10143 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10144 base.head) {
10145 if (encoder->base.crtc == &encoder->new_crtc->base)
10146 continue;
10147
10148 if (encoder->base.crtc) {
10149 tmp_crtc = encoder->base.crtc;
10150
10151 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10152 }
10153
10154 if (encoder->new_crtc)
10155 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10156 }
10157
10158 /* Check for pipes that will be enabled/disabled ... */
10159 for_each_intel_crtc(dev, intel_crtc) {
10160 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10161 continue;
10162
10163 if (!intel_crtc->new_enabled)
10164 *disable_pipes |= 1 << intel_crtc->pipe;
10165 else
10166 *prepare_pipes |= 1 << intel_crtc->pipe;
10167 }
10168
10169
10170 /* set_mode is also used to update properties on life display pipes. */
10171 intel_crtc = to_intel_crtc(crtc);
10172 if (intel_crtc->new_enabled)
10173 *prepare_pipes |= 1 << intel_crtc->pipe;
10174
10175 /*
10176 * For simplicity do a full modeset on any pipe where the output routing
10177 * changed. We could be more clever, but that would require us to be
10178 * more careful with calling the relevant encoder->mode_set functions.
10179 */
10180 if (*prepare_pipes)
10181 *modeset_pipes = *prepare_pipes;
10182
10183 /* ... and mask these out. */
10184 *modeset_pipes &= ~(*disable_pipes);
10185 *prepare_pipes &= ~(*disable_pipes);
10186
10187 /*
10188 * HACK: We don't (yet) fully support global modesets. intel_set_config
10189 * obies this rule, but the modeset restore mode of
10190 * intel_modeset_setup_hw_state does not.
10191 */
10192 *modeset_pipes &= 1 << intel_crtc->pipe;
10193 *prepare_pipes &= 1 << intel_crtc->pipe;
10194
10195 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10196 *modeset_pipes, *prepare_pipes, *disable_pipes);
10197 }
10198
10199 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10200 {
10201 struct drm_encoder *encoder;
10202 struct drm_device *dev = crtc->dev;
10203
10204 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10205 if (encoder->crtc == crtc)
10206 return true;
10207
10208 return false;
10209 }
10210
10211 static void
10212 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10213 {
10214 struct intel_encoder *intel_encoder;
10215 struct intel_crtc *intel_crtc;
10216 struct drm_connector *connector;
10217
10218 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
10219 base.head) {
10220 if (!intel_encoder->base.crtc)
10221 continue;
10222
10223 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10224
10225 if (prepare_pipes & (1 << intel_crtc->pipe))
10226 intel_encoder->connectors_active = false;
10227 }
10228
10229 intel_modeset_commit_output_state(dev);
10230
10231 /* Double check state. */
10232 for_each_intel_crtc(dev, intel_crtc) {
10233 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10234 WARN_ON(intel_crtc->new_config &&
10235 intel_crtc->new_config != &intel_crtc->config);
10236 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10237 }
10238
10239 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10240 if (!connector->encoder || !connector->encoder->crtc)
10241 continue;
10242
10243 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10244
10245 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10246 struct drm_property *dpms_property =
10247 dev->mode_config.dpms_property;
10248
10249 connector->dpms = DRM_MODE_DPMS_ON;
10250 drm_object_property_set_value(&connector->base,
10251 dpms_property,
10252 DRM_MODE_DPMS_ON);
10253
10254 intel_encoder = to_intel_encoder(connector->encoder);
10255 intel_encoder->connectors_active = true;
10256 }
10257 }
10258
10259 }
10260
10261 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10262 {
10263 int diff;
10264
10265 if (clock1 == clock2)
10266 return true;
10267
10268 if (!clock1 || !clock2)
10269 return false;
10270
10271 diff = abs(clock1 - clock2);
10272
10273 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10274 return true;
10275
10276 return false;
10277 }
10278
10279 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10280 list_for_each_entry((intel_crtc), \
10281 &(dev)->mode_config.crtc_list, \
10282 base.head) \
10283 if (mask & (1 <<(intel_crtc)->pipe))
10284
10285 static bool
10286 intel_pipe_config_compare(struct drm_device *dev,
10287 struct intel_crtc_config *current_config,
10288 struct intel_crtc_config *pipe_config)
10289 {
10290 #define PIPE_CONF_CHECK_X(name) \
10291 if (current_config->name != pipe_config->name) { \
10292 DRM_ERROR("mismatch in " #name " " \
10293 "(expected 0x%08x, found 0x%08x)\n", \
10294 current_config->name, \
10295 pipe_config->name); \
10296 return false; \
10297 }
10298
10299 #define PIPE_CONF_CHECK_I(name) \
10300 if (current_config->name != pipe_config->name) { \
10301 DRM_ERROR("mismatch in " #name " " \
10302 "(expected %i, found %i)\n", \
10303 current_config->name, \
10304 pipe_config->name); \
10305 return false; \
10306 }
10307
10308 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10309 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10310 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10311 "(expected %i, found %i)\n", \
10312 current_config->name & (mask), \
10313 pipe_config->name & (mask)); \
10314 return false; \
10315 }
10316
10317 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10318 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10319 DRM_ERROR("mismatch in " #name " " \
10320 "(expected %i, found %i)\n", \
10321 current_config->name, \
10322 pipe_config->name); \
10323 return false; \
10324 }
10325
10326 #define PIPE_CONF_QUIRK(quirk) \
10327 ((current_config->quirks | pipe_config->quirks) & (quirk))
10328
10329 PIPE_CONF_CHECK_I(cpu_transcoder);
10330
10331 PIPE_CONF_CHECK_I(has_pch_encoder);
10332 PIPE_CONF_CHECK_I(fdi_lanes);
10333 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10334 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10335 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10336 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10337 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10338
10339 PIPE_CONF_CHECK_I(has_dp_encoder);
10340 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10341 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10342 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10343 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10344 PIPE_CONF_CHECK_I(dp_m_n.tu);
10345
10346 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10347 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10348 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10349 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10350 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10351 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10352
10353 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10354 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10355 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10356 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10357 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10358 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10359
10360 PIPE_CONF_CHECK_I(pixel_multiplier);
10361 PIPE_CONF_CHECK_I(has_hdmi_sink);
10362 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10363 IS_VALLEYVIEW(dev))
10364 PIPE_CONF_CHECK_I(limited_color_range);
10365
10366 PIPE_CONF_CHECK_I(has_audio);
10367
10368 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10369 DRM_MODE_FLAG_INTERLACE);
10370
10371 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10372 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10373 DRM_MODE_FLAG_PHSYNC);
10374 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10375 DRM_MODE_FLAG_NHSYNC);
10376 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10377 DRM_MODE_FLAG_PVSYNC);
10378 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10379 DRM_MODE_FLAG_NVSYNC);
10380 }
10381
10382 PIPE_CONF_CHECK_I(pipe_src_w);
10383 PIPE_CONF_CHECK_I(pipe_src_h);
10384
10385 /*
10386 * FIXME: BIOS likes to set up a cloned config with lvds+external
10387 * screen. Since we don't yet re-compute the pipe config when moving
10388 * just the lvds port away to another pipe the sw tracking won't match.
10389 *
10390 * Proper atomic modesets with recomputed global state will fix this.
10391 * Until then just don't check gmch state for inherited modes.
10392 */
10393 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10394 PIPE_CONF_CHECK_I(gmch_pfit.control);
10395 /* pfit ratios are autocomputed by the hw on gen4+ */
10396 if (INTEL_INFO(dev)->gen < 4)
10397 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10398 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10399 }
10400
10401 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10402 if (current_config->pch_pfit.enabled) {
10403 PIPE_CONF_CHECK_I(pch_pfit.pos);
10404 PIPE_CONF_CHECK_I(pch_pfit.size);
10405 }
10406
10407 /* BDW+ don't expose a synchronous way to read the state */
10408 if (IS_HASWELL(dev))
10409 PIPE_CONF_CHECK_I(ips_enabled);
10410
10411 PIPE_CONF_CHECK_I(double_wide);
10412
10413 PIPE_CONF_CHECK_I(shared_dpll);
10414 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10415 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10416 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10417 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10418
10419 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10420 PIPE_CONF_CHECK_I(pipe_bpp);
10421
10422 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10423 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10424
10425 #undef PIPE_CONF_CHECK_X
10426 #undef PIPE_CONF_CHECK_I
10427 #undef PIPE_CONF_CHECK_FLAGS
10428 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10429 #undef PIPE_CONF_QUIRK
10430
10431 return true;
10432 }
10433
10434 static void
10435 check_connector_state(struct drm_device *dev)
10436 {
10437 struct intel_connector *connector;
10438
10439 list_for_each_entry(connector, &dev->mode_config.connector_list,
10440 base.head) {
10441 /* This also checks the encoder/connector hw state with the
10442 * ->get_hw_state callbacks. */
10443 intel_connector_check_state(connector);
10444
10445 WARN(&connector->new_encoder->base != connector->base.encoder,
10446 "connector's staged encoder doesn't match current encoder\n");
10447 }
10448 }
10449
10450 static void
10451 check_encoder_state(struct drm_device *dev)
10452 {
10453 struct intel_encoder *encoder;
10454 struct intel_connector *connector;
10455
10456 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10457 base.head) {
10458 bool enabled = false;
10459 bool active = false;
10460 enum pipe pipe, tracked_pipe;
10461
10462 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10463 encoder->base.base.id,
10464 encoder->base.name);
10465
10466 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10467 "encoder's stage crtc doesn't match current crtc\n");
10468 WARN(encoder->connectors_active && !encoder->base.crtc,
10469 "encoder's active_connectors set, but no crtc\n");
10470
10471 list_for_each_entry(connector, &dev->mode_config.connector_list,
10472 base.head) {
10473 if (connector->base.encoder != &encoder->base)
10474 continue;
10475 enabled = true;
10476 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10477 active = true;
10478 }
10479 WARN(!!encoder->base.crtc != enabled,
10480 "encoder's enabled state mismatch "
10481 "(expected %i, found %i)\n",
10482 !!encoder->base.crtc, enabled);
10483 WARN(active && !encoder->base.crtc,
10484 "active encoder with no crtc\n");
10485
10486 WARN(encoder->connectors_active != active,
10487 "encoder's computed active state doesn't match tracked active state "
10488 "(expected %i, found %i)\n", active, encoder->connectors_active);
10489
10490 active = encoder->get_hw_state(encoder, &pipe);
10491 WARN(active != encoder->connectors_active,
10492 "encoder's hw state doesn't match sw tracking "
10493 "(expected %i, found %i)\n",
10494 encoder->connectors_active, active);
10495
10496 if (!encoder->base.crtc)
10497 continue;
10498
10499 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10500 WARN(active && pipe != tracked_pipe,
10501 "active encoder's pipe doesn't match"
10502 "(expected %i, found %i)\n",
10503 tracked_pipe, pipe);
10504
10505 }
10506 }
10507
10508 static void
10509 check_crtc_state(struct drm_device *dev)
10510 {
10511 struct drm_i915_private *dev_priv = dev->dev_private;
10512 struct intel_crtc *crtc;
10513 struct intel_encoder *encoder;
10514 struct intel_crtc_config pipe_config;
10515
10516 for_each_intel_crtc(dev, crtc) {
10517 bool enabled = false;
10518 bool active = false;
10519
10520 memset(&pipe_config, 0, sizeof(pipe_config));
10521
10522 DRM_DEBUG_KMS("[CRTC:%d]\n",
10523 crtc->base.base.id);
10524
10525 WARN(crtc->active && !crtc->base.enabled,
10526 "active crtc, but not enabled in sw tracking\n");
10527
10528 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10529 base.head) {
10530 if (encoder->base.crtc != &crtc->base)
10531 continue;
10532 enabled = true;
10533 if (encoder->connectors_active)
10534 active = true;
10535 }
10536
10537 WARN(active != crtc->active,
10538 "crtc's computed active state doesn't match tracked active state "
10539 "(expected %i, found %i)\n", active, crtc->active);
10540 WARN(enabled != crtc->base.enabled,
10541 "crtc's computed enabled state doesn't match tracked enabled state "
10542 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10543
10544 active = dev_priv->display.get_pipe_config(crtc,
10545 &pipe_config);
10546
10547 /* hw state is inconsistent with the pipe A quirk */
10548 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10549 active = crtc->active;
10550
10551 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10552 base.head) {
10553 enum pipe pipe;
10554 if (encoder->base.crtc != &crtc->base)
10555 continue;
10556 if (encoder->get_hw_state(encoder, &pipe))
10557 encoder->get_config(encoder, &pipe_config);
10558 }
10559
10560 WARN(crtc->active != active,
10561 "crtc active state doesn't match with hw state "
10562 "(expected %i, found %i)\n", crtc->active, active);
10563
10564 if (active &&
10565 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10566 WARN(1, "pipe state doesn't match!\n");
10567 intel_dump_pipe_config(crtc, &pipe_config,
10568 "[hw state]");
10569 intel_dump_pipe_config(crtc, &crtc->config,
10570 "[sw state]");
10571 }
10572 }
10573 }
10574
10575 static void
10576 check_shared_dpll_state(struct drm_device *dev)
10577 {
10578 struct drm_i915_private *dev_priv = dev->dev_private;
10579 struct intel_crtc *crtc;
10580 struct intel_dpll_hw_state dpll_hw_state;
10581 int i;
10582
10583 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10584 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10585 int enabled_crtcs = 0, active_crtcs = 0;
10586 bool active;
10587
10588 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10589
10590 DRM_DEBUG_KMS("%s\n", pll->name);
10591
10592 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10593
10594 WARN(pll->active > pll->refcount,
10595 "more active pll users than references: %i vs %i\n",
10596 pll->active, pll->refcount);
10597 WARN(pll->active && !pll->on,
10598 "pll in active use but not on in sw tracking\n");
10599 WARN(pll->on && !pll->active,
10600 "pll in on but not on in use in sw tracking\n");
10601 WARN(pll->on != active,
10602 "pll on state mismatch (expected %i, found %i)\n",
10603 pll->on, active);
10604
10605 for_each_intel_crtc(dev, crtc) {
10606 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10607 enabled_crtcs++;
10608 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10609 active_crtcs++;
10610 }
10611 WARN(pll->active != active_crtcs,
10612 "pll active crtcs mismatch (expected %i, found %i)\n",
10613 pll->active, active_crtcs);
10614 WARN(pll->refcount != enabled_crtcs,
10615 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10616 pll->refcount, enabled_crtcs);
10617
10618 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10619 sizeof(dpll_hw_state)),
10620 "pll hw state mismatch\n");
10621 }
10622 }
10623
10624 void
10625 intel_modeset_check_state(struct drm_device *dev)
10626 {
10627 check_connector_state(dev);
10628 check_encoder_state(dev);
10629 check_crtc_state(dev);
10630 check_shared_dpll_state(dev);
10631 }
10632
10633 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10634 int dotclock)
10635 {
10636 /*
10637 * FDI already provided one idea for the dotclock.
10638 * Yell if the encoder disagrees.
10639 */
10640 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10641 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10642 pipe_config->adjusted_mode.crtc_clock, dotclock);
10643 }
10644
10645 static void update_scanline_offset(struct intel_crtc *crtc)
10646 {
10647 struct drm_device *dev = crtc->base.dev;
10648
10649 /*
10650 * The scanline counter increments at the leading edge of hsync.
10651 *
10652 * On most platforms it starts counting from vtotal-1 on the
10653 * first active line. That means the scanline counter value is
10654 * always one less than what we would expect. Ie. just after
10655 * start of vblank, which also occurs at start of hsync (on the
10656 * last active line), the scanline counter will read vblank_start-1.
10657 *
10658 * On gen2 the scanline counter starts counting from 1 instead
10659 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10660 * to keep the value positive), instead of adding one.
10661 *
10662 * On HSW+ the behaviour of the scanline counter depends on the output
10663 * type. For DP ports it behaves like most other platforms, but on HDMI
10664 * there's an extra 1 line difference. So we need to add two instead of
10665 * one to the value.
10666 */
10667 if (IS_GEN2(dev)) {
10668 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10669 int vtotal;
10670
10671 vtotal = mode->crtc_vtotal;
10672 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10673 vtotal /= 2;
10674
10675 crtc->scanline_offset = vtotal - 1;
10676 } else if (HAS_DDI(dev) &&
10677 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10678 crtc->scanline_offset = 2;
10679 } else
10680 crtc->scanline_offset = 1;
10681 }
10682
10683 static int __intel_set_mode(struct drm_crtc *crtc,
10684 struct drm_display_mode *mode,
10685 int x, int y, struct drm_framebuffer *fb)
10686 {
10687 struct drm_device *dev = crtc->dev;
10688 struct drm_i915_private *dev_priv = dev->dev_private;
10689 struct drm_display_mode *saved_mode;
10690 struct intel_crtc_config *pipe_config = NULL;
10691 struct intel_crtc *intel_crtc;
10692 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10693 int ret = 0;
10694
10695 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10696 if (!saved_mode)
10697 return -ENOMEM;
10698
10699 intel_modeset_affected_pipes(crtc, &modeset_pipes,
10700 &prepare_pipes, &disable_pipes);
10701
10702 *saved_mode = crtc->mode;
10703
10704 /* Hack: Because we don't (yet) support global modeset on multiple
10705 * crtcs, we don't keep track of the new mode for more than one crtc.
10706 * Hence simply check whether any bit is set in modeset_pipes in all the
10707 * pieces of code that are not yet converted to deal with mutliple crtcs
10708 * changing their mode at the same time. */
10709 if (modeset_pipes) {
10710 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10711 if (IS_ERR(pipe_config)) {
10712 ret = PTR_ERR(pipe_config);
10713 pipe_config = NULL;
10714
10715 goto out;
10716 }
10717 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10718 "[modeset]");
10719 to_intel_crtc(crtc)->new_config = pipe_config;
10720 }
10721
10722 /*
10723 * See if the config requires any additional preparation, e.g.
10724 * to adjust global state with pipes off. We need to do this
10725 * here so we can get the modeset_pipe updated config for the new
10726 * mode set on this crtc. For other crtcs we need to use the
10727 * adjusted_mode bits in the crtc directly.
10728 */
10729 if (IS_VALLEYVIEW(dev)) {
10730 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10731
10732 /* may have added more to prepare_pipes than we should */
10733 prepare_pipes &= ~disable_pipes;
10734 }
10735
10736 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10737 intel_crtc_disable(&intel_crtc->base);
10738
10739 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10740 if (intel_crtc->base.enabled)
10741 dev_priv->display.crtc_disable(&intel_crtc->base);
10742 }
10743
10744 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10745 * to set it here already despite that we pass it down the callchain.
10746 */
10747 if (modeset_pipes) {
10748 crtc->mode = *mode;
10749 /* mode_set/enable/disable functions rely on a correct pipe
10750 * config. */
10751 to_intel_crtc(crtc)->config = *pipe_config;
10752 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10753
10754 /*
10755 * Calculate and store various constants which
10756 * are later needed by vblank and swap-completion
10757 * timestamping. They are derived from true hwmode.
10758 */
10759 drm_calc_timestamping_constants(crtc,
10760 &pipe_config->adjusted_mode);
10761 }
10762
10763 /* Only after disabling all output pipelines that will be changed can we
10764 * update the the output configuration. */
10765 intel_modeset_update_state(dev, prepare_pipes);
10766
10767 if (dev_priv->display.modeset_global_resources)
10768 dev_priv->display.modeset_global_resources(dev);
10769
10770 /* Set up the DPLL and any encoders state that needs to adjust or depend
10771 * on the DPLL.
10772 */
10773 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10774 struct drm_framebuffer *old_fb = crtc->primary->fb;
10775 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10776 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10777
10778 mutex_lock(&dev->struct_mutex);
10779 ret = intel_pin_and_fence_fb_obj(dev,
10780 obj,
10781 NULL);
10782 if (ret != 0) {
10783 DRM_ERROR("pin & fence failed\n");
10784 mutex_unlock(&dev->struct_mutex);
10785 goto done;
10786 }
10787 if (old_fb)
10788 intel_unpin_fb_obj(old_obj);
10789 i915_gem_track_fb(old_obj, obj,
10790 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10791 mutex_unlock(&dev->struct_mutex);
10792
10793 crtc->primary->fb = fb;
10794 crtc->x = x;
10795 crtc->y = y;
10796
10797 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10798 x, y, fb);
10799 if (ret)
10800 goto done;
10801 }
10802
10803 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10804 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10805 update_scanline_offset(intel_crtc);
10806
10807 dev_priv->display.crtc_enable(&intel_crtc->base);
10808 }
10809
10810 /* FIXME: add subpixel order */
10811 done:
10812 if (ret && crtc->enabled)
10813 crtc->mode = *saved_mode;
10814
10815 out:
10816 kfree(pipe_config);
10817 kfree(saved_mode);
10818 return ret;
10819 }
10820
10821 static int intel_set_mode(struct drm_crtc *crtc,
10822 struct drm_display_mode *mode,
10823 int x, int y, struct drm_framebuffer *fb)
10824 {
10825 int ret;
10826
10827 ret = __intel_set_mode(crtc, mode, x, y, fb);
10828
10829 if (ret == 0)
10830 intel_modeset_check_state(crtc->dev);
10831
10832 return ret;
10833 }
10834
10835 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10836 {
10837 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10838 }
10839
10840 #undef for_each_intel_crtc_masked
10841
10842 static void intel_set_config_free(struct intel_set_config *config)
10843 {
10844 if (!config)
10845 return;
10846
10847 kfree(config->save_connector_encoders);
10848 kfree(config->save_encoder_crtcs);
10849 kfree(config->save_crtc_enabled);
10850 kfree(config);
10851 }
10852
10853 static int intel_set_config_save_state(struct drm_device *dev,
10854 struct intel_set_config *config)
10855 {
10856 struct drm_crtc *crtc;
10857 struct drm_encoder *encoder;
10858 struct drm_connector *connector;
10859 int count;
10860
10861 config->save_crtc_enabled =
10862 kcalloc(dev->mode_config.num_crtc,
10863 sizeof(bool), GFP_KERNEL);
10864 if (!config->save_crtc_enabled)
10865 return -ENOMEM;
10866
10867 config->save_encoder_crtcs =
10868 kcalloc(dev->mode_config.num_encoder,
10869 sizeof(struct drm_crtc *), GFP_KERNEL);
10870 if (!config->save_encoder_crtcs)
10871 return -ENOMEM;
10872
10873 config->save_connector_encoders =
10874 kcalloc(dev->mode_config.num_connector,
10875 sizeof(struct drm_encoder *), GFP_KERNEL);
10876 if (!config->save_connector_encoders)
10877 return -ENOMEM;
10878
10879 /* Copy data. Note that driver private data is not affected.
10880 * Should anything bad happen only the expected state is
10881 * restored, not the drivers personal bookkeeping.
10882 */
10883 count = 0;
10884 for_each_crtc(dev, crtc) {
10885 config->save_crtc_enabled[count++] = crtc->enabled;
10886 }
10887
10888 count = 0;
10889 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10890 config->save_encoder_crtcs[count++] = encoder->crtc;
10891 }
10892
10893 count = 0;
10894 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10895 config->save_connector_encoders[count++] = connector->encoder;
10896 }
10897
10898 return 0;
10899 }
10900
10901 static void intel_set_config_restore_state(struct drm_device *dev,
10902 struct intel_set_config *config)
10903 {
10904 struct intel_crtc *crtc;
10905 struct intel_encoder *encoder;
10906 struct intel_connector *connector;
10907 int count;
10908
10909 count = 0;
10910 for_each_intel_crtc(dev, crtc) {
10911 crtc->new_enabled = config->save_crtc_enabled[count++];
10912
10913 if (crtc->new_enabled)
10914 crtc->new_config = &crtc->config;
10915 else
10916 crtc->new_config = NULL;
10917 }
10918
10919 count = 0;
10920 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10921 encoder->new_crtc =
10922 to_intel_crtc(config->save_encoder_crtcs[count++]);
10923 }
10924
10925 count = 0;
10926 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10927 connector->new_encoder =
10928 to_intel_encoder(config->save_connector_encoders[count++]);
10929 }
10930 }
10931
10932 static bool
10933 is_crtc_connector_off(struct drm_mode_set *set)
10934 {
10935 int i;
10936
10937 if (set->num_connectors == 0)
10938 return false;
10939
10940 if (WARN_ON(set->connectors == NULL))
10941 return false;
10942
10943 for (i = 0; i < set->num_connectors; i++)
10944 if (set->connectors[i]->encoder &&
10945 set->connectors[i]->encoder->crtc == set->crtc &&
10946 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10947 return true;
10948
10949 return false;
10950 }
10951
10952 static void
10953 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10954 struct intel_set_config *config)
10955 {
10956
10957 /* We should be able to check here if the fb has the same properties
10958 * and then just flip_or_move it */
10959 if (is_crtc_connector_off(set)) {
10960 config->mode_changed = true;
10961 } else if (set->crtc->primary->fb != set->fb) {
10962 /*
10963 * If we have no fb, we can only flip as long as the crtc is
10964 * active, otherwise we need a full mode set. The crtc may
10965 * be active if we've only disabled the primary plane, or
10966 * in fastboot situations.
10967 */
10968 if (set->crtc->primary->fb == NULL) {
10969 struct intel_crtc *intel_crtc =
10970 to_intel_crtc(set->crtc);
10971
10972 if (intel_crtc->active) {
10973 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10974 config->fb_changed = true;
10975 } else {
10976 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10977 config->mode_changed = true;
10978 }
10979 } else if (set->fb == NULL) {
10980 config->mode_changed = true;
10981 } else if (set->fb->pixel_format !=
10982 set->crtc->primary->fb->pixel_format) {
10983 config->mode_changed = true;
10984 } else {
10985 config->fb_changed = true;
10986 }
10987 }
10988
10989 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10990 config->fb_changed = true;
10991
10992 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10993 DRM_DEBUG_KMS("modes are different, full mode set\n");
10994 drm_mode_debug_printmodeline(&set->crtc->mode);
10995 drm_mode_debug_printmodeline(set->mode);
10996 config->mode_changed = true;
10997 }
10998
10999 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11000 set->crtc->base.id, config->mode_changed, config->fb_changed);
11001 }
11002
11003 static int
11004 intel_modeset_stage_output_state(struct drm_device *dev,
11005 struct drm_mode_set *set,
11006 struct intel_set_config *config)
11007 {
11008 struct intel_connector *connector;
11009 struct intel_encoder *encoder;
11010 struct intel_crtc *crtc;
11011 int ro;
11012
11013 /* The upper layers ensure that we either disable a crtc or have a list
11014 * of connectors. For paranoia, double-check this. */
11015 WARN_ON(!set->fb && (set->num_connectors != 0));
11016 WARN_ON(set->fb && (set->num_connectors == 0));
11017
11018 list_for_each_entry(connector, &dev->mode_config.connector_list,
11019 base.head) {
11020 /* Otherwise traverse passed in connector list and get encoders
11021 * for them. */
11022 for (ro = 0; ro < set->num_connectors; ro++) {
11023 if (set->connectors[ro] == &connector->base) {
11024 connector->new_encoder = connector->encoder;
11025 break;
11026 }
11027 }
11028
11029 /* If we disable the crtc, disable all its connectors. Also, if
11030 * the connector is on the changing crtc but not on the new
11031 * connector list, disable it. */
11032 if ((!set->fb || ro == set->num_connectors) &&
11033 connector->base.encoder &&
11034 connector->base.encoder->crtc == set->crtc) {
11035 connector->new_encoder = NULL;
11036
11037 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11038 connector->base.base.id,
11039 connector->base.name);
11040 }
11041
11042
11043 if (&connector->new_encoder->base != connector->base.encoder) {
11044 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11045 config->mode_changed = true;
11046 }
11047 }
11048 /* connector->new_encoder is now updated for all connectors. */
11049
11050 /* Update crtc of enabled connectors. */
11051 list_for_each_entry(connector, &dev->mode_config.connector_list,
11052 base.head) {
11053 struct drm_crtc *new_crtc;
11054
11055 if (!connector->new_encoder)
11056 continue;
11057
11058 new_crtc = connector->new_encoder->base.crtc;
11059
11060 for (ro = 0; ro < set->num_connectors; ro++) {
11061 if (set->connectors[ro] == &connector->base)
11062 new_crtc = set->crtc;
11063 }
11064
11065 /* Make sure the new CRTC will work with the encoder */
11066 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11067 new_crtc)) {
11068 return -EINVAL;
11069 }
11070 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
11071
11072 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11073 connector->base.base.id,
11074 connector->base.name,
11075 new_crtc->base.id);
11076 }
11077
11078 /* Check for any encoders that needs to be disabled. */
11079 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11080 base.head) {
11081 int num_connectors = 0;
11082 list_for_each_entry(connector,
11083 &dev->mode_config.connector_list,
11084 base.head) {
11085 if (connector->new_encoder == encoder) {
11086 WARN_ON(!connector->new_encoder->new_crtc);
11087 num_connectors++;
11088 }
11089 }
11090
11091 if (num_connectors == 0)
11092 encoder->new_crtc = NULL;
11093 else if (num_connectors > 1)
11094 return -EINVAL;
11095
11096 /* Only now check for crtc changes so we don't miss encoders
11097 * that will be disabled. */
11098 if (&encoder->new_crtc->base != encoder->base.crtc) {
11099 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11100 config->mode_changed = true;
11101 }
11102 }
11103 /* Now we've also updated encoder->new_crtc for all encoders. */
11104
11105 for_each_intel_crtc(dev, crtc) {
11106 crtc->new_enabled = false;
11107
11108 list_for_each_entry(encoder,
11109 &dev->mode_config.encoder_list,
11110 base.head) {
11111 if (encoder->new_crtc == crtc) {
11112 crtc->new_enabled = true;
11113 break;
11114 }
11115 }
11116
11117 if (crtc->new_enabled != crtc->base.enabled) {
11118 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11119 crtc->new_enabled ? "en" : "dis");
11120 config->mode_changed = true;
11121 }
11122
11123 if (crtc->new_enabled)
11124 crtc->new_config = &crtc->config;
11125 else
11126 crtc->new_config = NULL;
11127 }
11128
11129 return 0;
11130 }
11131
11132 static void disable_crtc_nofb(struct intel_crtc *crtc)
11133 {
11134 struct drm_device *dev = crtc->base.dev;
11135 struct intel_encoder *encoder;
11136 struct intel_connector *connector;
11137
11138 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11139 pipe_name(crtc->pipe));
11140
11141 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11142 if (connector->new_encoder &&
11143 connector->new_encoder->new_crtc == crtc)
11144 connector->new_encoder = NULL;
11145 }
11146
11147 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11148 if (encoder->new_crtc == crtc)
11149 encoder->new_crtc = NULL;
11150 }
11151
11152 crtc->new_enabled = false;
11153 crtc->new_config = NULL;
11154 }
11155
11156 static int intel_crtc_set_config(struct drm_mode_set *set)
11157 {
11158 struct drm_device *dev;
11159 struct drm_mode_set save_set;
11160 struct intel_set_config *config;
11161 int ret;
11162
11163 BUG_ON(!set);
11164 BUG_ON(!set->crtc);
11165 BUG_ON(!set->crtc->helper_private);
11166
11167 /* Enforce sane interface api - has been abused by the fb helper. */
11168 BUG_ON(!set->mode && set->fb);
11169 BUG_ON(set->fb && set->num_connectors == 0);
11170
11171 if (set->fb) {
11172 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11173 set->crtc->base.id, set->fb->base.id,
11174 (int)set->num_connectors, set->x, set->y);
11175 } else {
11176 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11177 }
11178
11179 dev = set->crtc->dev;
11180
11181 ret = -ENOMEM;
11182 config = kzalloc(sizeof(*config), GFP_KERNEL);
11183 if (!config)
11184 goto out_config;
11185
11186 ret = intel_set_config_save_state(dev, config);
11187 if (ret)
11188 goto out_config;
11189
11190 save_set.crtc = set->crtc;
11191 save_set.mode = &set->crtc->mode;
11192 save_set.x = set->crtc->x;
11193 save_set.y = set->crtc->y;
11194 save_set.fb = set->crtc->primary->fb;
11195
11196 /* Compute whether we need a full modeset, only an fb base update or no
11197 * change at all. In the future we might also check whether only the
11198 * mode changed, e.g. for LVDS where we only change the panel fitter in
11199 * such cases. */
11200 intel_set_config_compute_mode_changes(set, config);
11201
11202 ret = intel_modeset_stage_output_state(dev, set, config);
11203 if (ret)
11204 goto fail;
11205
11206 if (config->mode_changed) {
11207 ret = intel_set_mode(set->crtc, set->mode,
11208 set->x, set->y, set->fb);
11209 } else if (config->fb_changed) {
11210 struct drm_i915_private *dev_priv = dev->dev_private;
11211 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11212
11213 intel_crtc_wait_for_pending_flips(set->crtc);
11214
11215 ret = intel_pipe_set_base(set->crtc,
11216 set->x, set->y, set->fb);
11217
11218 /*
11219 * We need to make sure the primary plane is re-enabled if it
11220 * has previously been turned off.
11221 */
11222 if (!intel_crtc->primary_enabled && ret == 0) {
11223 WARN_ON(!intel_crtc->active);
11224 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11225 intel_crtc->pipe);
11226 }
11227
11228 /*
11229 * In the fastboot case this may be our only check of the
11230 * state after boot. It would be better to only do it on
11231 * the first update, but we don't have a nice way of doing that
11232 * (and really, set_config isn't used much for high freq page
11233 * flipping, so increasing its cost here shouldn't be a big
11234 * deal).
11235 */
11236 if (i915.fastboot && ret == 0)
11237 intel_modeset_check_state(set->crtc->dev);
11238 }
11239
11240 if (ret) {
11241 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11242 set->crtc->base.id, ret);
11243 fail:
11244 intel_set_config_restore_state(dev, config);
11245
11246 /*
11247 * HACK: if the pipe was on, but we didn't have a framebuffer,
11248 * force the pipe off to avoid oopsing in the modeset code
11249 * due to fb==NULL. This should only happen during boot since
11250 * we don't yet reconstruct the FB from the hardware state.
11251 */
11252 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11253 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11254
11255 /* Try to restore the config */
11256 if (config->mode_changed &&
11257 intel_set_mode(save_set.crtc, save_set.mode,
11258 save_set.x, save_set.y, save_set.fb))
11259 DRM_ERROR("failed to restore config after modeset failure\n");
11260 }
11261
11262 out_config:
11263 intel_set_config_free(config);
11264 return ret;
11265 }
11266
11267 static const struct drm_crtc_funcs intel_crtc_funcs = {
11268 .gamma_set = intel_crtc_gamma_set,
11269 .set_config = intel_crtc_set_config,
11270 .destroy = intel_crtc_destroy,
11271 .page_flip = intel_crtc_page_flip,
11272 };
11273
11274 static void intel_cpu_pll_init(struct drm_device *dev)
11275 {
11276 if (HAS_DDI(dev))
11277 intel_ddi_pll_init(dev);
11278 }
11279
11280 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11281 struct intel_shared_dpll *pll,
11282 struct intel_dpll_hw_state *hw_state)
11283 {
11284 uint32_t val;
11285
11286 val = I915_READ(PCH_DPLL(pll->id));
11287 hw_state->dpll = val;
11288 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11289 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11290
11291 return val & DPLL_VCO_ENABLE;
11292 }
11293
11294 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11295 struct intel_shared_dpll *pll)
11296 {
11297 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11298 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11299 }
11300
11301 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11302 struct intel_shared_dpll *pll)
11303 {
11304 /* PCH refclock must be enabled first */
11305 ibx_assert_pch_refclk_enabled(dev_priv);
11306
11307 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11308
11309 /* Wait for the clocks to stabilize. */
11310 POSTING_READ(PCH_DPLL(pll->id));
11311 udelay(150);
11312
11313 /* The pixel multiplier can only be updated once the
11314 * DPLL is enabled and the clocks are stable.
11315 *
11316 * So write it again.
11317 */
11318 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11319 POSTING_READ(PCH_DPLL(pll->id));
11320 udelay(200);
11321 }
11322
11323 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11324 struct intel_shared_dpll *pll)
11325 {
11326 struct drm_device *dev = dev_priv->dev;
11327 struct intel_crtc *crtc;
11328
11329 /* Make sure no transcoder isn't still depending on us. */
11330 for_each_intel_crtc(dev, crtc) {
11331 if (intel_crtc_to_shared_dpll(crtc) == pll)
11332 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11333 }
11334
11335 I915_WRITE(PCH_DPLL(pll->id), 0);
11336 POSTING_READ(PCH_DPLL(pll->id));
11337 udelay(200);
11338 }
11339
11340 static char *ibx_pch_dpll_names[] = {
11341 "PCH DPLL A",
11342 "PCH DPLL B",
11343 };
11344
11345 static void ibx_pch_dpll_init(struct drm_device *dev)
11346 {
11347 struct drm_i915_private *dev_priv = dev->dev_private;
11348 int i;
11349
11350 dev_priv->num_shared_dpll = 2;
11351
11352 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11353 dev_priv->shared_dplls[i].id = i;
11354 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11355 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11356 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11357 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11358 dev_priv->shared_dplls[i].get_hw_state =
11359 ibx_pch_dpll_get_hw_state;
11360 }
11361 }
11362
11363 static void intel_shared_dpll_init(struct drm_device *dev)
11364 {
11365 struct drm_i915_private *dev_priv = dev->dev_private;
11366
11367 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11368 ibx_pch_dpll_init(dev);
11369 else
11370 dev_priv->num_shared_dpll = 0;
11371
11372 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11373 }
11374
11375 static int
11376 intel_primary_plane_disable(struct drm_plane *plane)
11377 {
11378 struct drm_device *dev = plane->dev;
11379 struct drm_i915_private *dev_priv = dev->dev_private;
11380 struct intel_plane *intel_plane = to_intel_plane(plane);
11381 struct intel_crtc *intel_crtc;
11382
11383 if (!plane->fb)
11384 return 0;
11385
11386 BUG_ON(!plane->crtc);
11387
11388 intel_crtc = to_intel_crtc(plane->crtc);
11389
11390 /*
11391 * Even though we checked plane->fb above, it's still possible that
11392 * the primary plane has been implicitly disabled because the crtc
11393 * coordinates given weren't visible, or because we detected
11394 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11395 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11396 * In either case, we need to unpin the FB and let the fb pointer get
11397 * updated, but otherwise we don't need to touch the hardware.
11398 */
11399 if (!intel_crtc->primary_enabled)
11400 goto disable_unpin;
11401
11402 intel_crtc_wait_for_pending_flips(plane->crtc);
11403 intel_disable_primary_hw_plane(dev_priv, intel_plane->plane,
11404 intel_plane->pipe);
11405 disable_unpin:
11406 mutex_lock(&dev->struct_mutex);
11407 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11408 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11409 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11410 mutex_unlock(&dev->struct_mutex);
11411 plane->fb = NULL;
11412
11413 return 0;
11414 }
11415
11416 static int
11417 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11418 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11419 unsigned int crtc_w, unsigned int crtc_h,
11420 uint32_t src_x, uint32_t src_y,
11421 uint32_t src_w, uint32_t src_h)
11422 {
11423 struct drm_device *dev = crtc->dev;
11424 struct drm_i915_private *dev_priv = dev->dev_private;
11425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11426 struct intel_plane *intel_plane = to_intel_plane(plane);
11427 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11428 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11429 struct drm_rect dest = {
11430 /* integer pixels */
11431 .x1 = crtc_x,
11432 .y1 = crtc_y,
11433 .x2 = crtc_x + crtc_w,
11434 .y2 = crtc_y + crtc_h,
11435 };
11436 struct drm_rect src = {
11437 /* 16.16 fixed point */
11438 .x1 = src_x,
11439 .y1 = src_y,
11440 .x2 = src_x + src_w,
11441 .y2 = src_y + src_h,
11442 };
11443 const struct drm_rect clip = {
11444 /* integer pixels */
11445 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11446 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11447 };
11448 bool visible;
11449 int ret;
11450
11451 ret = drm_plane_helper_check_update(plane, crtc, fb,
11452 &src, &dest, &clip,
11453 DRM_PLANE_HELPER_NO_SCALING,
11454 DRM_PLANE_HELPER_NO_SCALING,
11455 false, true, &visible);
11456
11457 if (ret)
11458 return ret;
11459
11460 /*
11461 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11462 * updating the fb pointer, and returning without touching the
11463 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11464 * turn on the display with all planes setup as desired.
11465 */
11466 if (!crtc->enabled) {
11467 mutex_lock(&dev->struct_mutex);
11468
11469 /*
11470 * If we already called setplane while the crtc was disabled,
11471 * we may have an fb pinned; unpin it.
11472 */
11473 if (plane->fb)
11474 intel_unpin_fb_obj(old_obj);
11475
11476 i915_gem_track_fb(old_obj, obj,
11477 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11478
11479 /* Pin and return without programming hardware */
11480 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11481 mutex_unlock(&dev->struct_mutex);
11482
11483 return ret;
11484 }
11485
11486 intel_crtc_wait_for_pending_flips(crtc);
11487
11488 /*
11489 * If clipping results in a non-visible primary plane, we'll disable
11490 * the primary plane. Note that this is a bit different than what
11491 * happens if userspace explicitly disables the plane by passing fb=0
11492 * because plane->fb still gets set and pinned.
11493 */
11494 if (!visible) {
11495 mutex_lock(&dev->struct_mutex);
11496
11497 /*
11498 * Try to pin the new fb first so that we can bail out if we
11499 * fail.
11500 */
11501 if (plane->fb != fb) {
11502 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11503 if (ret) {
11504 mutex_unlock(&dev->struct_mutex);
11505 return ret;
11506 }
11507 }
11508
11509 i915_gem_track_fb(old_obj, obj,
11510 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11511
11512 if (intel_crtc->primary_enabled)
11513 intel_disable_primary_hw_plane(dev_priv,
11514 intel_plane->plane,
11515 intel_plane->pipe);
11516
11517
11518 if (plane->fb != fb)
11519 if (plane->fb)
11520 intel_unpin_fb_obj(old_obj);
11521
11522 mutex_unlock(&dev->struct_mutex);
11523
11524 return 0;
11525 }
11526
11527 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11528 if (ret)
11529 return ret;
11530
11531 if (!intel_crtc->primary_enabled)
11532 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11533 intel_crtc->pipe);
11534
11535 return 0;
11536 }
11537
11538 /* Common destruction function for both primary and cursor planes */
11539 static void intel_plane_destroy(struct drm_plane *plane)
11540 {
11541 struct intel_plane *intel_plane = to_intel_plane(plane);
11542 drm_plane_cleanup(plane);
11543 kfree(intel_plane);
11544 }
11545
11546 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11547 .update_plane = intel_primary_plane_setplane,
11548 .disable_plane = intel_primary_plane_disable,
11549 .destroy = intel_plane_destroy,
11550 };
11551
11552 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11553 int pipe)
11554 {
11555 struct intel_plane *primary;
11556 const uint32_t *intel_primary_formats;
11557 int num_formats;
11558
11559 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11560 if (primary == NULL)
11561 return NULL;
11562
11563 primary->can_scale = false;
11564 primary->max_downscale = 1;
11565 primary->pipe = pipe;
11566 primary->plane = pipe;
11567 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11568 primary->plane = !pipe;
11569
11570 if (INTEL_INFO(dev)->gen <= 3) {
11571 intel_primary_formats = intel_primary_formats_gen2;
11572 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11573 } else {
11574 intel_primary_formats = intel_primary_formats_gen4;
11575 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11576 }
11577
11578 drm_universal_plane_init(dev, &primary->base, 0,
11579 &intel_primary_plane_funcs,
11580 intel_primary_formats, num_formats,
11581 DRM_PLANE_TYPE_PRIMARY);
11582 return &primary->base;
11583 }
11584
11585 static int
11586 intel_cursor_plane_disable(struct drm_plane *plane)
11587 {
11588 if (!plane->fb)
11589 return 0;
11590
11591 BUG_ON(!plane->crtc);
11592
11593 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11594 }
11595
11596 static int
11597 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11598 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11599 unsigned int crtc_w, unsigned int crtc_h,
11600 uint32_t src_x, uint32_t src_y,
11601 uint32_t src_w, uint32_t src_h)
11602 {
11603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11604 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11605 struct drm_i915_gem_object *obj = intel_fb->obj;
11606 struct drm_rect dest = {
11607 /* integer pixels */
11608 .x1 = crtc_x,
11609 .y1 = crtc_y,
11610 .x2 = crtc_x + crtc_w,
11611 .y2 = crtc_y + crtc_h,
11612 };
11613 struct drm_rect src = {
11614 /* 16.16 fixed point */
11615 .x1 = src_x,
11616 .y1 = src_y,
11617 .x2 = src_x + src_w,
11618 .y2 = src_y + src_h,
11619 };
11620 const struct drm_rect clip = {
11621 /* integer pixels */
11622 .x2 = intel_crtc->config.pipe_src_w,
11623 .y2 = intel_crtc->config.pipe_src_h,
11624 };
11625 bool visible;
11626 int ret;
11627
11628 ret = drm_plane_helper_check_update(plane, crtc, fb,
11629 &src, &dest, &clip,
11630 DRM_PLANE_HELPER_NO_SCALING,
11631 DRM_PLANE_HELPER_NO_SCALING,
11632 true, true, &visible);
11633 if (ret)
11634 return ret;
11635
11636 crtc->cursor_x = crtc_x;
11637 crtc->cursor_y = crtc_y;
11638 if (fb != crtc->cursor->fb) {
11639 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11640 } else {
11641 intel_crtc_update_cursor(crtc, visible);
11642 return 0;
11643 }
11644 }
11645 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11646 .update_plane = intel_cursor_plane_update,
11647 .disable_plane = intel_cursor_plane_disable,
11648 .destroy = intel_plane_destroy,
11649 };
11650
11651 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11652 int pipe)
11653 {
11654 struct intel_plane *cursor;
11655
11656 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11657 if (cursor == NULL)
11658 return NULL;
11659
11660 cursor->can_scale = false;
11661 cursor->max_downscale = 1;
11662 cursor->pipe = pipe;
11663 cursor->plane = pipe;
11664
11665 drm_universal_plane_init(dev, &cursor->base, 0,
11666 &intel_cursor_plane_funcs,
11667 intel_cursor_formats,
11668 ARRAY_SIZE(intel_cursor_formats),
11669 DRM_PLANE_TYPE_CURSOR);
11670 return &cursor->base;
11671 }
11672
11673 static void intel_crtc_init(struct drm_device *dev, int pipe)
11674 {
11675 struct drm_i915_private *dev_priv = dev->dev_private;
11676 struct intel_crtc *intel_crtc;
11677 struct drm_plane *primary = NULL;
11678 struct drm_plane *cursor = NULL;
11679 int i, ret;
11680
11681 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11682 if (intel_crtc == NULL)
11683 return;
11684
11685 primary = intel_primary_plane_create(dev, pipe);
11686 if (!primary)
11687 goto fail;
11688
11689 cursor = intel_cursor_plane_create(dev, pipe);
11690 if (!cursor)
11691 goto fail;
11692
11693 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11694 cursor, &intel_crtc_funcs);
11695 if (ret)
11696 goto fail;
11697
11698 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11699 for (i = 0; i < 256; i++) {
11700 intel_crtc->lut_r[i] = i;
11701 intel_crtc->lut_g[i] = i;
11702 intel_crtc->lut_b[i] = i;
11703 }
11704
11705 /*
11706 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11707 * is hooked to pipe B. Hence we want plane A feeding pipe B.
11708 */
11709 intel_crtc->pipe = pipe;
11710 intel_crtc->plane = pipe;
11711 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11712 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11713 intel_crtc->plane = !pipe;
11714 }
11715
11716 intel_crtc->cursor_base = ~0;
11717 intel_crtc->cursor_cntl = ~0;
11718
11719 init_waitqueue_head(&intel_crtc->vbl_wait);
11720
11721 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11722 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11723 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11724 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11725
11726 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11727
11728 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11729 return;
11730
11731 fail:
11732 if (primary)
11733 drm_plane_cleanup(primary);
11734 if (cursor)
11735 drm_plane_cleanup(cursor);
11736 kfree(intel_crtc);
11737 }
11738
11739 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11740 {
11741 struct drm_encoder *encoder = connector->base.encoder;
11742 struct drm_device *dev = connector->base.dev;
11743
11744 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11745
11746 if (!encoder)
11747 return INVALID_PIPE;
11748
11749 return to_intel_crtc(encoder->crtc)->pipe;
11750 }
11751
11752 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
11753 struct drm_file *file)
11754 {
11755 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11756 struct drm_mode_object *drmmode_obj;
11757 struct intel_crtc *crtc;
11758
11759 if (!drm_core_check_feature(dev, DRIVER_MODESET))
11760 return -ENODEV;
11761
11762 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
11763 DRM_MODE_OBJECT_CRTC);
11764
11765 if (!drmmode_obj) {
11766 DRM_ERROR("no such CRTC id\n");
11767 return -ENOENT;
11768 }
11769
11770 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
11771 pipe_from_crtc_id->pipe = crtc->pipe;
11772
11773 return 0;
11774 }
11775
11776 static int intel_encoder_clones(struct intel_encoder *encoder)
11777 {
11778 struct drm_device *dev = encoder->base.dev;
11779 struct intel_encoder *source_encoder;
11780 int index_mask = 0;
11781 int entry = 0;
11782
11783 list_for_each_entry(source_encoder,
11784 &dev->mode_config.encoder_list, base.head) {
11785 if (encoders_cloneable(encoder, source_encoder))
11786 index_mask |= (1 << entry);
11787
11788 entry++;
11789 }
11790
11791 return index_mask;
11792 }
11793
11794 static bool has_edp_a(struct drm_device *dev)
11795 {
11796 struct drm_i915_private *dev_priv = dev->dev_private;
11797
11798 if (!IS_MOBILE(dev))
11799 return false;
11800
11801 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11802 return false;
11803
11804 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
11805 return false;
11806
11807 return true;
11808 }
11809
11810 const char *intel_output_name(int output)
11811 {
11812 static const char *names[] = {
11813 [INTEL_OUTPUT_UNUSED] = "Unused",
11814 [INTEL_OUTPUT_ANALOG] = "Analog",
11815 [INTEL_OUTPUT_DVO] = "DVO",
11816 [INTEL_OUTPUT_SDVO] = "SDVO",
11817 [INTEL_OUTPUT_LVDS] = "LVDS",
11818 [INTEL_OUTPUT_TVOUT] = "TV",
11819 [INTEL_OUTPUT_HDMI] = "HDMI",
11820 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
11821 [INTEL_OUTPUT_EDP] = "eDP",
11822 [INTEL_OUTPUT_DSI] = "DSI",
11823 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
11824 };
11825
11826 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11827 return "Invalid";
11828
11829 return names[output];
11830 }
11831
11832 static bool intel_crt_present(struct drm_device *dev)
11833 {
11834 struct drm_i915_private *dev_priv = dev->dev_private;
11835
11836 if (IS_ULT(dev))
11837 return false;
11838
11839 if (IS_CHERRYVIEW(dev))
11840 return false;
11841
11842 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
11843 return false;
11844
11845 return true;
11846 }
11847
11848 static void intel_setup_outputs(struct drm_device *dev)
11849 {
11850 struct drm_i915_private *dev_priv = dev->dev_private;
11851 struct intel_encoder *encoder;
11852 bool dpd_is_edp = false;
11853
11854 intel_lvds_init(dev);
11855
11856 if (intel_crt_present(dev))
11857 intel_crt_init(dev);
11858
11859 if (HAS_DDI(dev)) {
11860 int found;
11861
11862 /* Haswell uses DDI functions to detect digital outputs */
11863 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
11864 /* DDI A only supports eDP */
11865 if (found)
11866 intel_ddi_init(dev, PORT_A);
11867
11868 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11869 * register */
11870 found = I915_READ(SFUSE_STRAP);
11871
11872 if (found & SFUSE_STRAP_DDIB_DETECTED)
11873 intel_ddi_init(dev, PORT_B);
11874 if (found & SFUSE_STRAP_DDIC_DETECTED)
11875 intel_ddi_init(dev, PORT_C);
11876 if (found & SFUSE_STRAP_DDID_DETECTED)
11877 intel_ddi_init(dev, PORT_D);
11878 } else if (HAS_PCH_SPLIT(dev)) {
11879 int found;
11880 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
11881
11882 if (has_edp_a(dev))
11883 intel_dp_init(dev, DP_A, PORT_A);
11884
11885 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
11886 /* PCH SDVOB multiplex with HDMIB */
11887 found = intel_sdvo_init(dev, PCH_SDVOB, true);
11888 if (!found)
11889 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
11890 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
11891 intel_dp_init(dev, PCH_DP_B, PORT_B);
11892 }
11893
11894 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
11895 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
11896
11897 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
11898 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
11899
11900 if (I915_READ(PCH_DP_C) & DP_DETECTED)
11901 intel_dp_init(dev, PCH_DP_C, PORT_C);
11902
11903 if (I915_READ(PCH_DP_D) & DP_DETECTED)
11904 intel_dp_init(dev, PCH_DP_D, PORT_D);
11905 } else if (IS_VALLEYVIEW(dev)) {
11906 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11907 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11908 PORT_B);
11909 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11910 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11911 }
11912
11913 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11914 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11915 PORT_C);
11916 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
11917 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
11918 }
11919
11920 if (IS_CHERRYVIEW(dev)) {
11921 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
11922 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
11923 PORT_D);
11924 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
11925 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
11926 }
11927 }
11928
11929 intel_dsi_init(dev);
11930 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
11931 bool found = false;
11932
11933 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11934 DRM_DEBUG_KMS("probing SDVOB\n");
11935 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
11936 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
11937 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
11938 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
11939 }
11940
11941 if (!found && SUPPORTS_INTEGRATED_DP(dev))
11942 intel_dp_init(dev, DP_B, PORT_B);
11943 }
11944
11945 /* Before G4X SDVOC doesn't have its own detect register */
11946
11947 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11948 DRM_DEBUG_KMS("probing SDVOC\n");
11949 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
11950 }
11951
11952 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
11953
11954 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11955 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
11956 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
11957 }
11958 if (SUPPORTS_INTEGRATED_DP(dev))
11959 intel_dp_init(dev, DP_C, PORT_C);
11960 }
11961
11962 if (SUPPORTS_INTEGRATED_DP(dev) &&
11963 (I915_READ(DP_D) & DP_DETECTED))
11964 intel_dp_init(dev, DP_D, PORT_D);
11965 } else if (IS_GEN2(dev))
11966 intel_dvo_init(dev);
11967
11968 if (SUPPORTS_TV(dev))
11969 intel_tv_init(dev);
11970
11971 intel_edp_psr_init(dev);
11972
11973 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11974 encoder->base.possible_crtcs = encoder->crtc_mask;
11975 encoder->base.possible_clones =
11976 intel_encoder_clones(encoder);
11977 }
11978
11979 intel_init_pch_refclk(dev);
11980
11981 drm_helper_move_panel_connectors_to_head(dev);
11982 }
11983
11984 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11985 {
11986 struct drm_device *dev = fb->dev;
11987 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11988
11989 drm_framebuffer_cleanup(fb);
11990 mutex_lock(&dev->struct_mutex);
11991 WARN_ON(!intel_fb->obj->framebuffer_references--);
11992 drm_gem_object_unreference(&intel_fb->obj->base);
11993 mutex_unlock(&dev->struct_mutex);
11994 kfree(intel_fb);
11995 }
11996
11997 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
11998 struct drm_file *file,
11999 unsigned int *handle)
12000 {
12001 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12002 struct drm_i915_gem_object *obj = intel_fb->obj;
12003
12004 return drm_gem_handle_create(file, &obj->base, handle);
12005 }
12006
12007 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12008 .destroy = intel_user_framebuffer_destroy,
12009 .create_handle = intel_user_framebuffer_create_handle,
12010 };
12011
12012 static int intel_framebuffer_init(struct drm_device *dev,
12013 struct intel_framebuffer *intel_fb,
12014 struct drm_mode_fb_cmd2 *mode_cmd,
12015 struct drm_i915_gem_object *obj)
12016 {
12017 int aligned_height;
12018 int pitch_limit;
12019 int ret;
12020
12021 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12022
12023 if (obj->tiling_mode == I915_TILING_Y) {
12024 DRM_DEBUG("hardware does not support tiling Y\n");
12025 return -EINVAL;
12026 }
12027
12028 if (mode_cmd->pitches[0] & 63) {
12029 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12030 mode_cmd->pitches[0]);
12031 return -EINVAL;
12032 }
12033
12034 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12035 pitch_limit = 32*1024;
12036 } else if (INTEL_INFO(dev)->gen >= 4) {
12037 if (obj->tiling_mode)
12038 pitch_limit = 16*1024;
12039 else
12040 pitch_limit = 32*1024;
12041 } else if (INTEL_INFO(dev)->gen >= 3) {
12042 if (obj->tiling_mode)
12043 pitch_limit = 8*1024;
12044 else
12045 pitch_limit = 16*1024;
12046 } else
12047 /* XXX DSPC is limited to 4k tiled */
12048 pitch_limit = 8*1024;
12049
12050 if (mode_cmd->pitches[0] > pitch_limit) {
12051 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12052 obj->tiling_mode ? "tiled" : "linear",
12053 mode_cmd->pitches[0], pitch_limit);
12054 return -EINVAL;
12055 }
12056
12057 if (obj->tiling_mode != I915_TILING_NONE &&
12058 mode_cmd->pitches[0] != obj->stride) {
12059 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12060 mode_cmd->pitches[0], obj->stride);
12061 return -EINVAL;
12062 }
12063
12064 /* Reject formats not supported by any plane early. */
12065 switch (mode_cmd->pixel_format) {
12066 case DRM_FORMAT_C8:
12067 case DRM_FORMAT_RGB565:
12068 case DRM_FORMAT_XRGB8888:
12069 case DRM_FORMAT_ARGB8888:
12070 break;
12071 case DRM_FORMAT_XRGB1555:
12072 case DRM_FORMAT_ARGB1555:
12073 if (INTEL_INFO(dev)->gen > 3) {
12074 DRM_DEBUG("unsupported pixel format: %s\n",
12075 drm_get_format_name(mode_cmd->pixel_format));
12076 return -EINVAL;
12077 }
12078 break;
12079 case DRM_FORMAT_XBGR8888:
12080 case DRM_FORMAT_ABGR8888:
12081 case DRM_FORMAT_XRGB2101010:
12082 case DRM_FORMAT_ARGB2101010:
12083 case DRM_FORMAT_XBGR2101010:
12084 case DRM_FORMAT_ABGR2101010:
12085 if (INTEL_INFO(dev)->gen < 4) {
12086 DRM_DEBUG("unsupported pixel format: %s\n",
12087 drm_get_format_name(mode_cmd->pixel_format));
12088 return -EINVAL;
12089 }
12090 break;
12091 case DRM_FORMAT_YUYV:
12092 case DRM_FORMAT_UYVY:
12093 case DRM_FORMAT_YVYU:
12094 case DRM_FORMAT_VYUY:
12095 if (INTEL_INFO(dev)->gen < 5) {
12096 DRM_DEBUG("unsupported pixel format: %s\n",
12097 drm_get_format_name(mode_cmd->pixel_format));
12098 return -EINVAL;
12099 }
12100 break;
12101 default:
12102 DRM_DEBUG("unsupported pixel format: %s\n",
12103 drm_get_format_name(mode_cmd->pixel_format));
12104 return -EINVAL;
12105 }
12106
12107 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12108 if (mode_cmd->offsets[0] != 0)
12109 return -EINVAL;
12110
12111 aligned_height = intel_align_height(dev, mode_cmd->height,
12112 obj->tiling_mode);
12113 /* FIXME drm helper for size checks (especially planar formats)? */
12114 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12115 return -EINVAL;
12116
12117 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12118 intel_fb->obj = obj;
12119 intel_fb->obj->framebuffer_references++;
12120
12121 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12122 if (ret) {
12123 DRM_ERROR("framebuffer init failed %d\n", ret);
12124 return ret;
12125 }
12126
12127 return 0;
12128 }
12129
12130 static struct drm_framebuffer *
12131 intel_user_framebuffer_create(struct drm_device *dev,
12132 struct drm_file *filp,
12133 struct drm_mode_fb_cmd2 *mode_cmd)
12134 {
12135 struct drm_i915_gem_object *obj;
12136
12137 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12138 mode_cmd->handles[0]));
12139 if (&obj->base == NULL)
12140 return ERR_PTR(-ENOENT);
12141
12142 return intel_framebuffer_create(dev, mode_cmd, obj);
12143 }
12144
12145 #ifndef CONFIG_DRM_I915_FBDEV
12146 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12147 {
12148 }
12149 #endif
12150
12151 static const struct drm_mode_config_funcs intel_mode_funcs = {
12152 .fb_create = intel_user_framebuffer_create,
12153 .output_poll_changed = intel_fbdev_output_poll_changed,
12154 };
12155
12156 /* Set up chip specific display functions */
12157 static void intel_init_display(struct drm_device *dev)
12158 {
12159 struct drm_i915_private *dev_priv = dev->dev_private;
12160
12161 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12162 dev_priv->display.find_dpll = g4x_find_best_dpll;
12163 else if (IS_CHERRYVIEW(dev))
12164 dev_priv->display.find_dpll = chv_find_best_dpll;
12165 else if (IS_VALLEYVIEW(dev))
12166 dev_priv->display.find_dpll = vlv_find_best_dpll;
12167 else if (IS_PINEVIEW(dev))
12168 dev_priv->display.find_dpll = pnv_find_best_dpll;
12169 else
12170 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12171
12172 if (HAS_DDI(dev)) {
12173 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12174 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12175 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12176 dev_priv->display.crtc_enable = haswell_crtc_enable;
12177 dev_priv->display.crtc_disable = haswell_crtc_disable;
12178 dev_priv->display.off = haswell_crtc_off;
12179 dev_priv->display.update_primary_plane =
12180 ironlake_update_primary_plane;
12181 } else if (HAS_PCH_SPLIT(dev)) {
12182 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12183 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12184 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12185 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12186 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12187 dev_priv->display.off = ironlake_crtc_off;
12188 dev_priv->display.update_primary_plane =
12189 ironlake_update_primary_plane;
12190 } else if (IS_VALLEYVIEW(dev)) {
12191 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12192 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12193 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12194 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12195 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12196 dev_priv->display.off = i9xx_crtc_off;
12197 dev_priv->display.update_primary_plane =
12198 i9xx_update_primary_plane;
12199 } else {
12200 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12201 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12202 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12203 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12204 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12205 dev_priv->display.off = i9xx_crtc_off;
12206 dev_priv->display.update_primary_plane =
12207 i9xx_update_primary_plane;
12208 }
12209
12210 /* Returns the core display clock speed */
12211 if (IS_VALLEYVIEW(dev))
12212 dev_priv->display.get_display_clock_speed =
12213 valleyview_get_display_clock_speed;
12214 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12215 dev_priv->display.get_display_clock_speed =
12216 i945_get_display_clock_speed;
12217 else if (IS_I915G(dev))
12218 dev_priv->display.get_display_clock_speed =
12219 i915_get_display_clock_speed;
12220 else if (IS_I945GM(dev) || IS_845G(dev))
12221 dev_priv->display.get_display_clock_speed =
12222 i9xx_misc_get_display_clock_speed;
12223 else if (IS_PINEVIEW(dev))
12224 dev_priv->display.get_display_clock_speed =
12225 pnv_get_display_clock_speed;
12226 else if (IS_I915GM(dev))
12227 dev_priv->display.get_display_clock_speed =
12228 i915gm_get_display_clock_speed;
12229 else if (IS_I865G(dev))
12230 dev_priv->display.get_display_clock_speed =
12231 i865_get_display_clock_speed;
12232 else if (IS_I85X(dev))
12233 dev_priv->display.get_display_clock_speed =
12234 i855_get_display_clock_speed;
12235 else /* 852, 830 */
12236 dev_priv->display.get_display_clock_speed =
12237 i830_get_display_clock_speed;
12238
12239 if (HAS_PCH_SPLIT(dev)) {
12240 if (IS_GEN5(dev)) {
12241 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12242 dev_priv->display.write_eld = ironlake_write_eld;
12243 } else if (IS_GEN6(dev)) {
12244 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12245 dev_priv->display.write_eld = ironlake_write_eld;
12246 dev_priv->display.modeset_global_resources =
12247 snb_modeset_global_resources;
12248 } else if (IS_IVYBRIDGE(dev)) {
12249 /* FIXME: detect B0+ stepping and use auto training */
12250 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12251 dev_priv->display.write_eld = ironlake_write_eld;
12252 dev_priv->display.modeset_global_resources =
12253 ivb_modeset_global_resources;
12254 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
12255 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12256 dev_priv->display.write_eld = haswell_write_eld;
12257 dev_priv->display.modeset_global_resources =
12258 haswell_modeset_global_resources;
12259 }
12260 } else if (IS_G4X(dev)) {
12261 dev_priv->display.write_eld = g4x_write_eld;
12262 } else if (IS_VALLEYVIEW(dev)) {
12263 dev_priv->display.modeset_global_resources =
12264 valleyview_modeset_global_resources;
12265 dev_priv->display.write_eld = ironlake_write_eld;
12266 }
12267
12268 /* Default just returns -ENODEV to indicate unsupported */
12269 dev_priv->display.queue_flip = intel_default_queue_flip;
12270
12271 switch (INTEL_INFO(dev)->gen) {
12272 case 2:
12273 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12274 break;
12275
12276 case 3:
12277 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12278 break;
12279
12280 case 4:
12281 case 5:
12282 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12283 break;
12284
12285 case 6:
12286 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12287 break;
12288 case 7:
12289 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12290 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12291 break;
12292 }
12293
12294 intel_panel_init_backlight_funcs(dev);
12295 }
12296
12297 /*
12298 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12299 * resume, or other times. This quirk makes sure that's the case for
12300 * affected systems.
12301 */
12302 static void quirk_pipea_force(struct drm_device *dev)
12303 {
12304 struct drm_i915_private *dev_priv = dev->dev_private;
12305
12306 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12307 DRM_INFO("applying pipe a force quirk\n");
12308 }
12309
12310 /*
12311 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12312 */
12313 static void quirk_ssc_force_disable(struct drm_device *dev)
12314 {
12315 struct drm_i915_private *dev_priv = dev->dev_private;
12316 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12317 DRM_INFO("applying lvds SSC disable quirk\n");
12318 }
12319
12320 /*
12321 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12322 * brightness value
12323 */
12324 static void quirk_invert_brightness(struct drm_device *dev)
12325 {
12326 struct drm_i915_private *dev_priv = dev->dev_private;
12327 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12328 DRM_INFO("applying inverted panel brightness quirk\n");
12329 }
12330
12331 struct intel_quirk {
12332 int device;
12333 int subsystem_vendor;
12334 int subsystem_device;
12335 void (*hook)(struct drm_device *dev);
12336 };
12337
12338 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12339 struct intel_dmi_quirk {
12340 void (*hook)(struct drm_device *dev);
12341 const struct dmi_system_id (*dmi_id_list)[];
12342 };
12343
12344 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12345 {
12346 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12347 return 1;
12348 }
12349
12350 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12351 {
12352 .dmi_id_list = &(const struct dmi_system_id[]) {
12353 {
12354 .callback = intel_dmi_reverse_brightness,
12355 .ident = "NCR Corporation",
12356 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12357 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12358 },
12359 },
12360 { } /* terminating entry */
12361 },
12362 .hook = quirk_invert_brightness,
12363 },
12364 };
12365
12366 static struct intel_quirk intel_quirks[] = {
12367 /* HP Mini needs pipe A force quirk (LP: #322104) */
12368 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12369
12370 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12371 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12372
12373 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12374 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12375
12376 /* Lenovo U160 cannot use SSC on LVDS */
12377 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12378
12379 /* Sony Vaio Y cannot use SSC on LVDS */
12380 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12381
12382 /* Acer Aspire 5734Z must invert backlight brightness */
12383 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12384
12385 /* Acer/eMachines G725 */
12386 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12387
12388 /* Acer/eMachines e725 */
12389 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12390
12391 /* Acer/Packard Bell NCL20 */
12392 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12393
12394 /* Acer Aspire 4736Z */
12395 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12396
12397 /* Acer Aspire 5336 */
12398 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12399 };
12400
12401 static void intel_init_quirks(struct drm_device *dev)
12402 {
12403 struct pci_dev *d = dev->pdev;
12404 int i;
12405
12406 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12407 struct intel_quirk *q = &intel_quirks[i];
12408
12409 if (d->device == q->device &&
12410 (d->subsystem_vendor == q->subsystem_vendor ||
12411 q->subsystem_vendor == PCI_ANY_ID) &&
12412 (d->subsystem_device == q->subsystem_device ||
12413 q->subsystem_device == PCI_ANY_ID))
12414 q->hook(dev);
12415 }
12416 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12417 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12418 intel_dmi_quirks[i].hook(dev);
12419 }
12420 }
12421
12422 /* Disable the VGA plane that we never use */
12423 static void i915_disable_vga(struct drm_device *dev)
12424 {
12425 struct drm_i915_private *dev_priv = dev->dev_private;
12426 u8 sr1;
12427 u32 vga_reg = i915_vgacntrl_reg(dev);
12428
12429 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12430 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12431 outb(SR01, VGA_SR_INDEX);
12432 sr1 = inb(VGA_SR_DATA);
12433 outb(sr1 | 1<<5, VGA_SR_DATA);
12434 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12435 udelay(300);
12436
12437 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
12438 POSTING_READ(vga_reg);
12439 }
12440
12441 void intel_modeset_init_hw(struct drm_device *dev)
12442 {
12443 intel_prepare_ddi(dev);
12444
12445 if (IS_VALLEYVIEW(dev))
12446 vlv_update_cdclk(dev);
12447
12448 intel_init_clock_gating(dev);
12449
12450 intel_reset_dpio(dev);
12451
12452 intel_enable_gt_powersave(dev);
12453 }
12454
12455 void intel_modeset_suspend_hw(struct drm_device *dev)
12456 {
12457 intel_suspend_hw(dev);
12458 }
12459
12460 void intel_modeset_init(struct drm_device *dev)
12461 {
12462 struct drm_i915_private *dev_priv = dev->dev_private;
12463 int sprite, ret;
12464 enum pipe pipe;
12465 struct intel_crtc *crtc;
12466
12467 drm_mode_config_init(dev);
12468
12469 dev->mode_config.min_width = 0;
12470 dev->mode_config.min_height = 0;
12471
12472 dev->mode_config.preferred_depth = 24;
12473 dev->mode_config.prefer_shadow = 1;
12474
12475 dev->mode_config.funcs = &intel_mode_funcs;
12476
12477 intel_init_quirks(dev);
12478
12479 intel_init_pm(dev);
12480
12481 if (INTEL_INFO(dev)->num_pipes == 0)
12482 return;
12483
12484 intel_init_display(dev);
12485
12486 if (IS_GEN2(dev)) {
12487 dev->mode_config.max_width = 2048;
12488 dev->mode_config.max_height = 2048;
12489 } else if (IS_GEN3(dev)) {
12490 dev->mode_config.max_width = 4096;
12491 dev->mode_config.max_height = 4096;
12492 } else {
12493 dev->mode_config.max_width = 8192;
12494 dev->mode_config.max_height = 8192;
12495 }
12496
12497 if (IS_GEN2(dev)) {
12498 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12499 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12500 } else {
12501 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12502 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12503 }
12504
12505 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12506
12507 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12508 INTEL_INFO(dev)->num_pipes,
12509 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12510
12511 for_each_pipe(pipe) {
12512 intel_crtc_init(dev, pipe);
12513 for_each_sprite(pipe, sprite) {
12514 ret = intel_plane_init(dev, pipe, sprite);
12515 if (ret)
12516 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12517 pipe_name(pipe), sprite_name(pipe, sprite), ret);
12518 }
12519 }
12520
12521 intel_init_dpio(dev);
12522 intel_reset_dpio(dev);
12523
12524 intel_cpu_pll_init(dev);
12525 intel_shared_dpll_init(dev);
12526
12527 /* Just disable it once at startup */
12528 i915_disable_vga(dev);
12529 intel_setup_outputs(dev);
12530
12531 /* Just in case the BIOS is doing something questionable. */
12532 intel_disable_fbc(dev);
12533
12534 drm_modeset_lock_all(dev);
12535 intel_modeset_setup_hw_state(dev, false);
12536 drm_modeset_unlock_all(dev);
12537
12538 for_each_intel_crtc(dev, crtc) {
12539 if (!crtc->active)
12540 continue;
12541
12542 /*
12543 * Note that reserving the BIOS fb up front prevents us
12544 * from stuffing other stolen allocations like the ring
12545 * on top. This prevents some ugliness at boot time, and
12546 * can even allow for smooth boot transitions if the BIOS
12547 * fb is large enough for the active pipe configuration.
12548 */
12549 if (dev_priv->display.get_plane_config) {
12550 dev_priv->display.get_plane_config(crtc,
12551 &crtc->plane_config);
12552 /*
12553 * If the fb is shared between multiple heads, we'll
12554 * just get the first one.
12555 */
12556 intel_find_plane_obj(crtc, &crtc->plane_config);
12557 }
12558 }
12559 }
12560
12561 static void intel_enable_pipe_a(struct drm_device *dev)
12562 {
12563 struct intel_connector *connector;
12564 struct drm_connector *crt = NULL;
12565 struct intel_load_detect_pipe load_detect_temp;
12566 struct drm_modeset_acquire_ctx ctx;
12567
12568 /* We can't just switch on the pipe A, we need to set things up with a
12569 * proper mode and output configuration. As a gross hack, enable pipe A
12570 * by enabling the load detect pipe once. */
12571 list_for_each_entry(connector,
12572 &dev->mode_config.connector_list,
12573 base.head) {
12574 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12575 crt = &connector->base;
12576 break;
12577 }
12578 }
12579
12580 if (!crt)
12581 return;
12582
12583 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx))
12584 intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx);
12585
12586
12587 }
12588
12589 static bool
12590 intel_check_plane_mapping(struct intel_crtc *crtc)
12591 {
12592 struct drm_device *dev = crtc->base.dev;
12593 struct drm_i915_private *dev_priv = dev->dev_private;
12594 u32 reg, val;
12595
12596 if (INTEL_INFO(dev)->num_pipes == 1)
12597 return true;
12598
12599 reg = DSPCNTR(!crtc->plane);
12600 val = I915_READ(reg);
12601
12602 if ((val & DISPLAY_PLANE_ENABLE) &&
12603 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12604 return false;
12605
12606 return true;
12607 }
12608
12609 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12610 {
12611 struct drm_device *dev = crtc->base.dev;
12612 struct drm_i915_private *dev_priv = dev->dev_private;
12613 u32 reg;
12614
12615 /* Clear any frame start delays used for debugging left by the BIOS */
12616 reg = PIPECONF(crtc->config.cpu_transcoder);
12617 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12618
12619 /* restore vblank interrupts to correct state */
12620 if (crtc->active)
12621 drm_vblank_on(dev, crtc->pipe);
12622 else
12623 drm_vblank_off(dev, crtc->pipe);
12624
12625 /* We need to sanitize the plane -> pipe mapping first because this will
12626 * disable the crtc (and hence change the state) if it is wrong. Note
12627 * that gen4+ has a fixed plane -> pipe mapping. */
12628 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12629 struct intel_connector *connector;
12630 bool plane;
12631
12632 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12633 crtc->base.base.id);
12634
12635 /* Pipe has the wrong plane attached and the plane is active.
12636 * Temporarily change the plane mapping and disable everything
12637 * ... */
12638 plane = crtc->plane;
12639 crtc->plane = !plane;
12640 dev_priv->display.crtc_disable(&crtc->base);
12641 crtc->plane = plane;
12642
12643 /* ... and break all links. */
12644 list_for_each_entry(connector, &dev->mode_config.connector_list,
12645 base.head) {
12646 if (connector->encoder->base.crtc != &crtc->base)
12647 continue;
12648
12649 connector->base.dpms = DRM_MODE_DPMS_OFF;
12650 connector->base.encoder = NULL;
12651 }
12652 /* multiple connectors may have the same encoder:
12653 * handle them and break crtc link separately */
12654 list_for_each_entry(connector, &dev->mode_config.connector_list,
12655 base.head)
12656 if (connector->encoder->base.crtc == &crtc->base) {
12657 connector->encoder->base.crtc = NULL;
12658 connector->encoder->connectors_active = false;
12659 }
12660
12661 WARN_ON(crtc->active);
12662 crtc->base.enabled = false;
12663 }
12664
12665 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12666 crtc->pipe == PIPE_A && !crtc->active) {
12667 /* BIOS forgot to enable pipe A, this mostly happens after
12668 * resume. Force-enable the pipe to fix this, the update_dpms
12669 * call below we restore the pipe to the right state, but leave
12670 * the required bits on. */
12671 intel_enable_pipe_a(dev);
12672 }
12673
12674 /* Adjust the state of the output pipe according to whether we
12675 * have active connectors/encoders. */
12676 intel_crtc_update_dpms(&crtc->base);
12677
12678 if (crtc->active != crtc->base.enabled) {
12679 struct intel_encoder *encoder;
12680
12681 /* This can happen either due to bugs in the get_hw_state
12682 * functions or because the pipe is force-enabled due to the
12683 * pipe A quirk. */
12684 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12685 crtc->base.base.id,
12686 crtc->base.enabled ? "enabled" : "disabled",
12687 crtc->active ? "enabled" : "disabled");
12688
12689 crtc->base.enabled = crtc->active;
12690
12691 /* Because we only establish the connector -> encoder ->
12692 * crtc links if something is active, this means the
12693 * crtc is now deactivated. Break the links. connector
12694 * -> encoder links are only establish when things are
12695 * actually up, hence no need to break them. */
12696 WARN_ON(crtc->active);
12697
12698 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12699 WARN_ON(encoder->connectors_active);
12700 encoder->base.crtc = NULL;
12701 }
12702 }
12703
12704 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
12705 /*
12706 * We start out with underrun reporting disabled to avoid races.
12707 * For correct bookkeeping mark this on active crtcs.
12708 *
12709 * Also on gmch platforms we dont have any hardware bits to
12710 * disable the underrun reporting. Which means we need to start
12711 * out with underrun reporting disabled also on inactive pipes,
12712 * since otherwise we'll complain about the garbage we read when
12713 * e.g. coming up after runtime pm.
12714 *
12715 * No protection against concurrent access is required - at
12716 * worst a fifo underrun happens which also sets this to false.
12717 */
12718 crtc->cpu_fifo_underrun_disabled = true;
12719 crtc->pch_fifo_underrun_disabled = true;
12720
12721 update_scanline_offset(crtc);
12722 }
12723 }
12724
12725 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12726 {
12727 struct intel_connector *connector;
12728 struct drm_device *dev = encoder->base.dev;
12729
12730 /* We need to check both for a crtc link (meaning that the
12731 * encoder is active and trying to read from a pipe) and the
12732 * pipe itself being active. */
12733 bool has_active_crtc = encoder->base.crtc &&
12734 to_intel_crtc(encoder->base.crtc)->active;
12735
12736 if (encoder->connectors_active && !has_active_crtc) {
12737 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12738 encoder->base.base.id,
12739 encoder->base.name);
12740
12741 /* Connector is active, but has no active pipe. This is
12742 * fallout from our resume register restoring. Disable
12743 * the encoder manually again. */
12744 if (encoder->base.crtc) {
12745 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12746 encoder->base.base.id,
12747 encoder->base.name);
12748 encoder->disable(encoder);
12749 }
12750 encoder->base.crtc = NULL;
12751 encoder->connectors_active = false;
12752
12753 /* Inconsistent output/port/pipe state happens presumably due to
12754 * a bug in one of the get_hw_state functions. Or someplace else
12755 * in our code, like the register restore mess on resume. Clamp
12756 * things to off as a safer default. */
12757 list_for_each_entry(connector,
12758 &dev->mode_config.connector_list,
12759 base.head) {
12760 if (connector->encoder != encoder)
12761 continue;
12762 connector->base.dpms = DRM_MODE_DPMS_OFF;
12763 connector->base.encoder = NULL;
12764 }
12765 }
12766 /* Enabled encoders without active connectors will be fixed in
12767 * the crtc fixup. */
12768 }
12769
12770 void i915_redisable_vga_power_on(struct drm_device *dev)
12771 {
12772 struct drm_i915_private *dev_priv = dev->dev_private;
12773 u32 vga_reg = i915_vgacntrl_reg(dev);
12774
12775 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
12776 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12777 i915_disable_vga(dev);
12778 }
12779 }
12780
12781 void i915_redisable_vga(struct drm_device *dev)
12782 {
12783 struct drm_i915_private *dev_priv = dev->dev_private;
12784
12785 /* This function can be called both from intel_modeset_setup_hw_state or
12786 * at a very early point in our resume sequence, where the power well
12787 * structures are not yet restored. Since this function is at a very
12788 * paranoid "someone might have enabled VGA while we were not looking"
12789 * level, just check if the power well is enabled instead of trying to
12790 * follow the "don't touch the power well if we don't need it" policy
12791 * the rest of the driver uses. */
12792 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
12793 return;
12794
12795 i915_redisable_vga_power_on(dev);
12796 }
12797
12798 static bool primary_get_hw_state(struct intel_crtc *crtc)
12799 {
12800 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
12801
12802 if (!crtc->active)
12803 return false;
12804
12805 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
12806 }
12807
12808 static void intel_modeset_readout_hw_state(struct drm_device *dev)
12809 {
12810 struct drm_i915_private *dev_priv = dev->dev_private;
12811 enum pipe pipe;
12812 struct intel_crtc *crtc;
12813 struct intel_encoder *encoder;
12814 struct intel_connector *connector;
12815 int i;
12816
12817 for_each_intel_crtc(dev, crtc) {
12818 memset(&crtc->config, 0, sizeof(crtc->config));
12819
12820 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
12821
12822 crtc->active = dev_priv->display.get_pipe_config(crtc,
12823 &crtc->config);
12824
12825 crtc->base.enabled = crtc->active;
12826 crtc->primary_enabled = primary_get_hw_state(crtc);
12827
12828 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
12829 crtc->base.base.id,
12830 crtc->active ? "enabled" : "disabled");
12831 }
12832
12833 /* FIXME: Smash this into the new shared dpll infrastructure. */
12834 if (HAS_DDI(dev))
12835 intel_ddi_setup_hw_pll_state(dev);
12836
12837 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12838 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12839
12840 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
12841 pll->active = 0;
12842 for_each_intel_crtc(dev, crtc) {
12843 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12844 pll->active++;
12845 }
12846 pll->refcount = pll->active;
12847
12848 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
12849 pll->name, pll->refcount, pll->on);
12850 }
12851
12852 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12853 base.head) {
12854 pipe = 0;
12855
12856 if (encoder->get_hw_state(encoder, &pipe)) {
12857 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12858 encoder->base.crtc = &crtc->base;
12859 encoder->get_config(encoder, &crtc->config);
12860 } else {
12861 encoder->base.crtc = NULL;
12862 }
12863
12864 encoder->connectors_active = false;
12865 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
12866 encoder->base.base.id,
12867 encoder->base.name,
12868 encoder->base.crtc ? "enabled" : "disabled",
12869 pipe_name(pipe));
12870 }
12871
12872 list_for_each_entry(connector, &dev->mode_config.connector_list,
12873 base.head) {
12874 if (connector->get_hw_state(connector)) {
12875 connector->base.dpms = DRM_MODE_DPMS_ON;
12876 connector->encoder->connectors_active = true;
12877 connector->base.encoder = &connector->encoder->base;
12878 } else {
12879 connector->base.dpms = DRM_MODE_DPMS_OFF;
12880 connector->base.encoder = NULL;
12881 }
12882 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
12883 connector->base.base.id,
12884 connector->base.name,
12885 connector->base.encoder ? "enabled" : "disabled");
12886 }
12887 }
12888
12889 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
12890 * and i915 state tracking structures. */
12891 void intel_modeset_setup_hw_state(struct drm_device *dev,
12892 bool force_restore)
12893 {
12894 struct drm_i915_private *dev_priv = dev->dev_private;
12895 enum pipe pipe;
12896 struct intel_crtc *crtc;
12897 struct intel_encoder *encoder;
12898 int i;
12899
12900 intel_modeset_readout_hw_state(dev);
12901
12902 /*
12903 * Now that we have the config, copy it to each CRTC struct
12904 * Note that this could go away if we move to using crtc_config
12905 * checking everywhere.
12906 */
12907 for_each_intel_crtc(dev, crtc) {
12908 if (crtc->active && i915.fastboot) {
12909 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
12910 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
12911 crtc->base.base.id);
12912 drm_mode_debug_printmodeline(&crtc->base.mode);
12913 }
12914 }
12915
12916 /* HW state is read out, now we need to sanitize this mess. */
12917 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12918 base.head) {
12919 intel_sanitize_encoder(encoder);
12920 }
12921
12922 for_each_pipe(pipe) {
12923 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12924 intel_sanitize_crtc(crtc);
12925 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
12926 }
12927
12928 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12929 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12930
12931 if (!pll->on || pll->active)
12932 continue;
12933
12934 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
12935
12936 pll->disable(dev_priv, pll);
12937 pll->on = false;
12938 }
12939
12940 if (HAS_PCH_SPLIT(dev))
12941 ilk_wm_get_hw_state(dev);
12942
12943 if (force_restore) {
12944 i915_redisable_vga(dev);
12945
12946 /*
12947 * We need to use raw interfaces for restoring state to avoid
12948 * checking (bogus) intermediate states.
12949 */
12950 for_each_pipe(pipe) {
12951 struct drm_crtc *crtc =
12952 dev_priv->pipe_to_crtc_mapping[pipe];
12953
12954 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
12955 crtc->primary->fb);
12956 }
12957 } else {
12958 intel_modeset_update_staged_output_state(dev);
12959 }
12960
12961 intel_modeset_check_state(dev);
12962 }
12963
12964 void intel_modeset_gem_init(struct drm_device *dev)
12965 {
12966 struct drm_crtc *c;
12967 struct drm_i915_gem_object *obj;
12968
12969 mutex_lock(&dev->struct_mutex);
12970 intel_init_gt_powersave(dev);
12971 mutex_unlock(&dev->struct_mutex);
12972
12973 intel_modeset_init_hw(dev);
12974
12975 intel_setup_overlay(dev);
12976
12977 /*
12978 * Make sure any fbs we allocated at startup are properly
12979 * pinned & fenced. When we do the allocation it's too early
12980 * for this.
12981 */
12982 mutex_lock(&dev->struct_mutex);
12983 for_each_crtc(dev, c) {
12984 obj = intel_fb_obj(c->primary->fb);
12985 if (obj == NULL)
12986 continue;
12987
12988 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
12989 DRM_ERROR("failed to pin boot fb on pipe %d\n",
12990 to_intel_crtc(c)->pipe);
12991 drm_framebuffer_unreference(c->primary->fb);
12992 c->primary->fb = NULL;
12993 }
12994 }
12995 mutex_unlock(&dev->struct_mutex);
12996 }
12997
12998 void intel_connector_unregister(struct intel_connector *intel_connector)
12999 {
13000 struct drm_connector *connector = &intel_connector->base;
13001
13002 intel_panel_destroy_backlight(connector);
13003 drm_sysfs_connector_remove(connector);
13004 }
13005
13006 void intel_modeset_cleanup(struct drm_device *dev)
13007 {
13008 struct drm_i915_private *dev_priv = dev->dev_private;
13009 struct drm_connector *connector;
13010
13011 /*
13012 * Interrupts and polling as the first thing to avoid creating havoc.
13013 * Too much stuff here (turning of rps, connectors, ...) would
13014 * experience fancy races otherwise.
13015 */
13016 drm_irq_uninstall(dev);
13017 cancel_work_sync(&dev_priv->hotplug_work);
13018 /*
13019 * Due to the hpd irq storm handling the hotplug work can re-arm the
13020 * poll handlers. Hence disable polling after hpd handling is shut down.
13021 */
13022 drm_kms_helper_poll_fini(dev);
13023
13024 mutex_lock(&dev->struct_mutex);
13025
13026 intel_unregister_dsm_handler();
13027
13028 intel_disable_fbc(dev);
13029
13030 intel_disable_gt_powersave(dev);
13031
13032 ironlake_teardown_rc6(dev);
13033
13034 mutex_unlock(&dev->struct_mutex);
13035
13036 /* flush any delayed tasks or pending work */
13037 flush_scheduled_work();
13038
13039 /* destroy the backlight and sysfs files before encoders/connectors */
13040 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13041 struct intel_connector *intel_connector;
13042
13043 intel_connector = to_intel_connector(connector);
13044 intel_connector->unregister(intel_connector);
13045 }
13046
13047 drm_mode_config_cleanup(dev);
13048
13049 intel_cleanup_overlay(dev);
13050
13051 mutex_lock(&dev->struct_mutex);
13052 intel_cleanup_gt_powersave(dev);
13053 mutex_unlock(&dev->struct_mutex);
13054 }
13055
13056 /*
13057 * Return which encoder is currently attached for connector.
13058 */
13059 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13060 {
13061 return &intel_attached_encoder(connector)->base;
13062 }
13063
13064 void intel_connector_attach_encoder(struct intel_connector *connector,
13065 struct intel_encoder *encoder)
13066 {
13067 connector->encoder = encoder;
13068 drm_mode_connector_attach_encoder(&connector->base,
13069 &encoder->base);
13070 }
13071
13072 /*
13073 * set vga decode state - true == enable VGA decode
13074 */
13075 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13076 {
13077 struct drm_i915_private *dev_priv = dev->dev_private;
13078 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13079 u16 gmch_ctrl;
13080
13081 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13082 DRM_ERROR("failed to read control word\n");
13083 return -EIO;
13084 }
13085
13086 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13087 return 0;
13088
13089 if (state)
13090 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13091 else
13092 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13093
13094 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13095 DRM_ERROR("failed to write control word\n");
13096 return -EIO;
13097 }
13098
13099 return 0;
13100 }
13101
13102 struct intel_display_error_state {
13103
13104 u32 power_well_driver;
13105
13106 int num_transcoders;
13107
13108 struct intel_cursor_error_state {
13109 u32 control;
13110 u32 position;
13111 u32 base;
13112 u32 size;
13113 } cursor[I915_MAX_PIPES];
13114
13115 struct intel_pipe_error_state {
13116 bool power_domain_on;
13117 u32 source;
13118 u32 stat;
13119 } pipe[I915_MAX_PIPES];
13120
13121 struct intel_plane_error_state {
13122 u32 control;
13123 u32 stride;
13124 u32 size;
13125 u32 pos;
13126 u32 addr;
13127 u32 surface;
13128 u32 tile_offset;
13129 } plane[I915_MAX_PIPES];
13130
13131 struct intel_transcoder_error_state {
13132 bool power_domain_on;
13133 enum transcoder cpu_transcoder;
13134
13135 u32 conf;
13136
13137 u32 htotal;
13138 u32 hblank;
13139 u32 hsync;
13140 u32 vtotal;
13141 u32 vblank;
13142 u32 vsync;
13143 } transcoder[4];
13144 };
13145
13146 struct intel_display_error_state *
13147 intel_display_capture_error_state(struct drm_device *dev)
13148 {
13149 struct drm_i915_private *dev_priv = dev->dev_private;
13150 struct intel_display_error_state *error;
13151 int transcoders[] = {
13152 TRANSCODER_A,
13153 TRANSCODER_B,
13154 TRANSCODER_C,
13155 TRANSCODER_EDP,
13156 };
13157 int i;
13158
13159 if (INTEL_INFO(dev)->num_pipes == 0)
13160 return NULL;
13161
13162 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13163 if (error == NULL)
13164 return NULL;
13165
13166 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13167 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13168
13169 for_each_pipe(i) {
13170 error->pipe[i].power_domain_on =
13171 intel_display_power_enabled_unlocked(dev_priv,
13172 POWER_DOMAIN_PIPE(i));
13173 if (!error->pipe[i].power_domain_on)
13174 continue;
13175
13176 error->cursor[i].control = I915_READ(CURCNTR(i));
13177 error->cursor[i].position = I915_READ(CURPOS(i));
13178 error->cursor[i].base = I915_READ(CURBASE(i));
13179
13180 error->plane[i].control = I915_READ(DSPCNTR(i));
13181 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13182 if (INTEL_INFO(dev)->gen <= 3) {
13183 error->plane[i].size = I915_READ(DSPSIZE(i));
13184 error->plane[i].pos = I915_READ(DSPPOS(i));
13185 }
13186 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13187 error->plane[i].addr = I915_READ(DSPADDR(i));
13188 if (INTEL_INFO(dev)->gen >= 4) {
13189 error->plane[i].surface = I915_READ(DSPSURF(i));
13190 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13191 }
13192
13193 error->pipe[i].source = I915_READ(PIPESRC(i));
13194
13195 if (!HAS_PCH_SPLIT(dev))
13196 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13197 }
13198
13199 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13200 if (HAS_DDI(dev_priv->dev))
13201 error->num_transcoders++; /* Account for eDP. */
13202
13203 for (i = 0; i < error->num_transcoders; i++) {
13204 enum transcoder cpu_transcoder = transcoders[i];
13205
13206 error->transcoder[i].power_domain_on =
13207 intel_display_power_enabled_unlocked(dev_priv,
13208 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13209 if (!error->transcoder[i].power_domain_on)
13210 continue;
13211
13212 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13213
13214 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13215 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13216 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13217 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13218 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13219 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13220 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13221 }
13222
13223 return error;
13224 }
13225
13226 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13227
13228 void
13229 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13230 struct drm_device *dev,
13231 struct intel_display_error_state *error)
13232 {
13233 int i;
13234
13235 if (!error)
13236 return;
13237
13238 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13239 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13240 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13241 error->power_well_driver);
13242 for_each_pipe(i) {
13243 err_printf(m, "Pipe [%d]:\n", i);
13244 err_printf(m, " Power: %s\n",
13245 error->pipe[i].power_domain_on ? "on" : "off");
13246 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13247 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13248
13249 err_printf(m, "Plane [%d]:\n", i);
13250 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13251 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13252 if (INTEL_INFO(dev)->gen <= 3) {
13253 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13254 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13255 }
13256 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13257 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13258 if (INTEL_INFO(dev)->gen >= 4) {
13259 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13260 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13261 }
13262
13263 err_printf(m, "Cursor [%d]:\n", i);
13264 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13265 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13266 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13267 }
13268
13269 for (i = 0; i < error->num_transcoders; i++) {
13270 err_printf(m, "CPU transcoder: %c\n",
13271 transcoder_name(error->transcoder[i].cpu_transcoder));
13272 err_printf(m, " Power: %s\n",
13273 error->transcoder[i].power_domain_on ? "on" : "off");
13274 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13275 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13276 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13277 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13278 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13279 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13280 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13281 }
13282 }
Ubuntu Artful kernel mirror