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Merge airlied/drm-next into drm-intel-next-queued
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "i915_gem_clflush.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
51
52 /* Primary plane formats for gen <= 3 */
53 static const uint32_t i8xx_primary_formats[] = {
54 DRM_FORMAT_C8,
55 DRM_FORMAT_RGB565,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_XRGB8888,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t i965_primary_formats[] = {
62 DRM_FORMAT_C8,
63 DRM_FORMAT_RGB565,
64 DRM_FORMAT_XRGB8888,
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_XRGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 };
69
70 static const uint32_t skl_primary_formats[] = {
71 DRM_FORMAT_C8,
72 DRM_FORMAT_RGB565,
73 DRM_FORMAT_XRGB8888,
74 DRM_FORMAT_XBGR8888,
75 DRM_FORMAT_ARGB8888,
76 DRM_FORMAT_ABGR8888,
77 DRM_FORMAT_XRGB2101010,
78 DRM_FORMAT_XBGR2101010,
79 DRM_FORMAT_YUYV,
80 DRM_FORMAT_YVYU,
81 DRM_FORMAT_UYVY,
82 DRM_FORMAT_VYUY,
83 };
84
85 /* Cursor formats */
86 static const uint32_t intel_cursor_formats[] = {
87 DRM_FORMAT_ARGB8888,
88 };
89
90 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
91 struct intel_crtc_state *pipe_config);
92 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
93 struct intel_crtc_state *pipe_config);
94
95 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
96 struct drm_i915_gem_object *obj,
97 struct drm_mode_fb_cmd2 *mode_cmd);
98 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
99 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
100 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
101 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
102 struct intel_link_m_n *m_n,
103 struct intel_link_m_n *m2_n2);
104 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
105 static void haswell_set_pipeconf(struct drm_crtc *crtc);
106 static void haswell_set_pipemisc(struct drm_crtc *crtc);
107 static void vlv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void chv_prepare_pll(struct intel_crtc *crtc,
110 const struct intel_crtc_state *pipe_config);
111 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
112 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
113 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
114 struct intel_crtc_state *crtc_state);
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
118 static void intel_modeset_setup_hw_state(struct drm_device *dev,
119 struct drm_modeset_acquire_ctx *ctx);
120 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
121
122 struct intel_limit {
123 struct {
124 int min, max;
125 } dot, vco, n, m, m1, m2, p, p1;
126
127 struct {
128 int dot_limit;
129 int p2_slow, p2_fast;
130 } p2;
131 };
132
133 /* returns HPLL frequency in kHz */
134 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
135 {
136 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
137
138 /* Obtain SKU information */
139 mutex_lock(&dev_priv->sb_lock);
140 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
141 CCK_FUSE_HPLL_FREQ_MASK;
142 mutex_unlock(&dev_priv->sb_lock);
143
144 return vco_freq[hpll_freq] * 1000;
145 }
146
147 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
148 const char *name, u32 reg, int ref_freq)
149 {
150 u32 val;
151 int divider;
152
153 mutex_lock(&dev_priv->sb_lock);
154 val = vlv_cck_read(dev_priv, reg);
155 mutex_unlock(&dev_priv->sb_lock);
156
157 divider = val & CCK_FREQUENCY_VALUES;
158
159 WARN((val & CCK_FREQUENCY_STATUS) !=
160 (divider << CCK_FREQUENCY_STATUS_SHIFT),
161 "%s change in progress\n", name);
162
163 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
164 }
165
166 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
167 const char *name, u32 reg)
168 {
169 if (dev_priv->hpll_freq == 0)
170 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
171
172 return vlv_get_cck_clock(dev_priv, name, reg,
173 dev_priv->hpll_freq);
174 }
175
176 static void intel_update_czclk(struct drm_i915_private *dev_priv)
177 {
178 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
179 return;
180
181 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
182 CCK_CZ_CLOCK_CONTROL);
183
184 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
185 }
186
187 static inline u32 /* units of 100MHz */
188 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
189 const struct intel_crtc_state *pipe_config)
190 {
191 if (HAS_DDI(dev_priv))
192 return pipe_config->port_clock; /* SPLL */
193 else if (IS_GEN5(dev_priv))
194 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
195 else
196 return 270000;
197 }
198
199 static const struct intel_limit intel_limits_i8xx_dac = {
200 .dot = { .min = 25000, .max = 350000 },
201 .vco = { .min = 908000, .max = 1512000 },
202 .n = { .min = 2, .max = 16 },
203 .m = { .min = 96, .max = 140 },
204 .m1 = { .min = 18, .max = 26 },
205 .m2 = { .min = 6, .max = 16 },
206 .p = { .min = 4, .max = 128 },
207 .p1 = { .min = 2, .max = 33 },
208 .p2 = { .dot_limit = 165000,
209 .p2_slow = 4, .p2_fast = 2 },
210 };
211
212 static const struct intel_limit intel_limits_i8xx_dvo = {
213 .dot = { .min = 25000, .max = 350000 },
214 .vco = { .min = 908000, .max = 1512000 },
215 .n = { .min = 2, .max = 16 },
216 .m = { .min = 96, .max = 140 },
217 .m1 = { .min = 18, .max = 26 },
218 .m2 = { .min = 6, .max = 16 },
219 .p = { .min = 4, .max = 128 },
220 .p1 = { .min = 2, .max = 33 },
221 .p2 = { .dot_limit = 165000,
222 .p2_slow = 4, .p2_fast = 4 },
223 };
224
225 static const struct intel_limit intel_limits_i8xx_lvds = {
226 .dot = { .min = 25000, .max = 350000 },
227 .vco = { .min = 908000, .max = 1512000 },
228 .n = { .min = 2, .max = 16 },
229 .m = { .min = 96, .max = 140 },
230 .m1 = { .min = 18, .max = 26 },
231 .m2 = { .min = 6, .max = 16 },
232 .p = { .min = 4, .max = 128 },
233 .p1 = { .min = 1, .max = 6 },
234 .p2 = { .dot_limit = 165000,
235 .p2_slow = 14, .p2_fast = 7 },
236 };
237
238 static const struct intel_limit intel_limits_i9xx_sdvo = {
239 .dot = { .min = 20000, .max = 400000 },
240 .vco = { .min = 1400000, .max = 2800000 },
241 .n = { .min = 1, .max = 6 },
242 .m = { .min = 70, .max = 120 },
243 .m1 = { .min = 8, .max = 18 },
244 .m2 = { .min = 3, .max = 7 },
245 .p = { .min = 5, .max = 80 },
246 .p1 = { .min = 1, .max = 8 },
247 .p2 = { .dot_limit = 200000,
248 .p2_slow = 10, .p2_fast = 5 },
249 };
250
251 static const struct intel_limit intel_limits_i9xx_lvds = {
252 .dot = { .min = 20000, .max = 400000 },
253 .vco = { .min = 1400000, .max = 2800000 },
254 .n = { .min = 1, .max = 6 },
255 .m = { .min = 70, .max = 120 },
256 .m1 = { .min = 8, .max = 18 },
257 .m2 = { .min = 3, .max = 7 },
258 .p = { .min = 7, .max = 98 },
259 .p1 = { .min = 1, .max = 8 },
260 .p2 = { .dot_limit = 112000,
261 .p2_slow = 14, .p2_fast = 7 },
262 };
263
264
265 static const struct intel_limit intel_limits_g4x_sdvo = {
266 .dot = { .min = 25000, .max = 270000 },
267 .vco = { .min = 1750000, .max = 3500000},
268 .n = { .min = 1, .max = 4 },
269 .m = { .min = 104, .max = 138 },
270 .m1 = { .min = 17, .max = 23 },
271 .m2 = { .min = 5, .max = 11 },
272 .p = { .min = 10, .max = 30 },
273 .p1 = { .min = 1, .max = 3},
274 .p2 = { .dot_limit = 270000,
275 .p2_slow = 10,
276 .p2_fast = 10
277 },
278 };
279
280 static const struct intel_limit intel_limits_g4x_hdmi = {
281 .dot = { .min = 22000, .max = 400000 },
282 .vco = { .min = 1750000, .max = 3500000},
283 .n = { .min = 1, .max = 4 },
284 .m = { .min = 104, .max = 138 },
285 .m1 = { .min = 16, .max = 23 },
286 .m2 = { .min = 5, .max = 11 },
287 .p = { .min = 5, .max = 80 },
288 .p1 = { .min = 1, .max = 8},
289 .p2 = { .dot_limit = 165000,
290 .p2_slow = 10, .p2_fast = 5 },
291 };
292
293 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
294 .dot = { .min = 20000, .max = 115000 },
295 .vco = { .min = 1750000, .max = 3500000 },
296 .n = { .min = 1, .max = 3 },
297 .m = { .min = 104, .max = 138 },
298 .m1 = { .min = 17, .max = 23 },
299 .m2 = { .min = 5, .max = 11 },
300 .p = { .min = 28, .max = 112 },
301 .p1 = { .min = 2, .max = 8 },
302 .p2 = { .dot_limit = 0,
303 .p2_slow = 14, .p2_fast = 14
304 },
305 };
306
307 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
308 .dot = { .min = 80000, .max = 224000 },
309 .vco = { .min = 1750000, .max = 3500000 },
310 .n = { .min = 1, .max = 3 },
311 .m = { .min = 104, .max = 138 },
312 .m1 = { .min = 17, .max = 23 },
313 .m2 = { .min = 5, .max = 11 },
314 .p = { .min = 14, .max = 42 },
315 .p1 = { .min = 2, .max = 6 },
316 .p2 = { .dot_limit = 0,
317 .p2_slow = 7, .p2_fast = 7
318 },
319 };
320
321 static const struct intel_limit intel_limits_pineview_sdvo = {
322 .dot = { .min = 20000, .max = 400000},
323 .vco = { .min = 1700000, .max = 3500000 },
324 /* Pineview's Ncounter is a ring counter */
325 .n = { .min = 3, .max = 6 },
326 .m = { .min = 2, .max = 256 },
327 /* Pineview only has one combined m divider, which we treat as m2. */
328 .m1 = { .min = 0, .max = 0 },
329 .m2 = { .min = 0, .max = 254 },
330 .p = { .min = 5, .max = 80 },
331 .p1 = { .min = 1, .max = 8 },
332 .p2 = { .dot_limit = 200000,
333 .p2_slow = 10, .p2_fast = 5 },
334 };
335
336 static const struct intel_limit intel_limits_pineview_lvds = {
337 .dot = { .min = 20000, .max = 400000 },
338 .vco = { .min = 1700000, .max = 3500000 },
339 .n = { .min = 3, .max = 6 },
340 .m = { .min = 2, .max = 256 },
341 .m1 = { .min = 0, .max = 0 },
342 .m2 = { .min = 0, .max = 254 },
343 .p = { .min = 7, .max = 112 },
344 .p1 = { .min = 1, .max = 8 },
345 .p2 = { .dot_limit = 112000,
346 .p2_slow = 14, .p2_fast = 14 },
347 };
348
349 /* Ironlake / Sandybridge
350 *
351 * We calculate clock using (register_value + 2) for N/M1/M2, so here
352 * the range value for them is (actual_value - 2).
353 */
354 static const struct intel_limit intel_limits_ironlake_dac = {
355 .dot = { .min = 25000, .max = 350000 },
356 .vco = { .min = 1760000, .max = 3510000 },
357 .n = { .min = 1, .max = 5 },
358 .m = { .min = 79, .max = 127 },
359 .m1 = { .min = 12, .max = 22 },
360 .m2 = { .min = 5, .max = 9 },
361 .p = { .min = 5, .max = 80 },
362 .p1 = { .min = 1, .max = 8 },
363 .p2 = { .dot_limit = 225000,
364 .p2_slow = 10, .p2_fast = 5 },
365 };
366
367 static const struct intel_limit intel_limits_ironlake_single_lvds = {
368 .dot = { .min = 25000, .max = 350000 },
369 .vco = { .min = 1760000, .max = 3510000 },
370 .n = { .min = 1, .max = 3 },
371 .m = { .min = 79, .max = 118 },
372 .m1 = { .min = 12, .max = 22 },
373 .m2 = { .min = 5, .max = 9 },
374 .p = { .min = 28, .max = 112 },
375 .p1 = { .min = 2, .max = 8 },
376 .p2 = { .dot_limit = 225000,
377 .p2_slow = 14, .p2_fast = 14 },
378 };
379
380 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
381 .dot = { .min = 25000, .max = 350000 },
382 .vco = { .min = 1760000, .max = 3510000 },
383 .n = { .min = 1, .max = 3 },
384 .m = { .min = 79, .max = 127 },
385 .m1 = { .min = 12, .max = 22 },
386 .m2 = { .min = 5, .max = 9 },
387 .p = { .min = 14, .max = 56 },
388 .p1 = { .min = 2, .max = 8 },
389 .p2 = { .dot_limit = 225000,
390 .p2_slow = 7, .p2_fast = 7 },
391 };
392
393 /* LVDS 100mhz refclk limits. */
394 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
395 .dot = { .min = 25000, .max = 350000 },
396 .vco = { .min = 1760000, .max = 3510000 },
397 .n = { .min = 1, .max = 2 },
398 .m = { .min = 79, .max = 126 },
399 .m1 = { .min = 12, .max = 22 },
400 .m2 = { .min = 5, .max = 9 },
401 .p = { .min = 28, .max = 112 },
402 .p1 = { .min = 2, .max = 8 },
403 .p2 = { .dot_limit = 225000,
404 .p2_slow = 14, .p2_fast = 14 },
405 };
406
407 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
408 .dot = { .min = 25000, .max = 350000 },
409 .vco = { .min = 1760000, .max = 3510000 },
410 .n = { .min = 1, .max = 3 },
411 .m = { .min = 79, .max = 126 },
412 .m1 = { .min = 12, .max = 22 },
413 .m2 = { .min = 5, .max = 9 },
414 .p = { .min = 14, .max = 42 },
415 .p1 = { .min = 2, .max = 6 },
416 .p2 = { .dot_limit = 225000,
417 .p2_slow = 7, .p2_fast = 7 },
418 };
419
420 static const struct intel_limit intel_limits_vlv = {
421 /*
422 * These are the data rate limits (measured in fast clocks)
423 * since those are the strictest limits we have. The fast
424 * clock and actual rate limits are more relaxed, so checking
425 * them would make no difference.
426 */
427 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
428 .vco = { .min = 4000000, .max = 6000000 },
429 .n = { .min = 1, .max = 7 },
430 .m1 = { .min = 2, .max = 3 },
431 .m2 = { .min = 11, .max = 156 },
432 .p1 = { .min = 2, .max = 3 },
433 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
434 };
435
436 static const struct intel_limit intel_limits_chv = {
437 /*
438 * These are the data rate limits (measured in fast clocks)
439 * since those are the strictest limits we have. The fast
440 * clock and actual rate limits are more relaxed, so checking
441 * them would make no difference.
442 */
443 .dot = { .min = 25000 * 5, .max = 540000 * 5},
444 .vco = { .min = 4800000, .max = 6480000 },
445 .n = { .min = 1, .max = 1 },
446 .m1 = { .min = 2, .max = 2 },
447 .m2 = { .min = 24 << 22, .max = 175 << 22 },
448 .p1 = { .min = 2, .max = 4 },
449 .p2 = { .p2_slow = 1, .p2_fast = 14 },
450 };
451
452 static const struct intel_limit intel_limits_bxt = {
453 /* FIXME: find real dot limits */
454 .dot = { .min = 0, .max = INT_MAX },
455 .vco = { .min = 4800000, .max = 6700000 },
456 .n = { .min = 1, .max = 1 },
457 .m1 = { .min = 2, .max = 2 },
458 /* FIXME: find real m2 limits */
459 .m2 = { .min = 2 << 22, .max = 255 << 22 },
460 .p1 = { .min = 2, .max = 4 },
461 .p2 = { .p2_slow = 1, .p2_fast = 20 },
462 };
463
464 static bool
465 needs_modeset(struct drm_crtc_state *state)
466 {
467 return drm_atomic_crtc_needs_modeset(state);
468 }
469
470 /*
471 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
472 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
473 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
474 * The helpers' return value is the rate of the clock that is fed to the
475 * display engine's pipe which can be the above fast dot clock rate or a
476 * divided-down version of it.
477 */
478 /* m1 is reserved as 0 in Pineview, n is a ring counter */
479 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
480 {
481 clock->m = clock->m2 + 2;
482 clock->p = clock->p1 * clock->p2;
483 if (WARN_ON(clock->n == 0 || clock->p == 0))
484 return 0;
485 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
486 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
487
488 return clock->dot;
489 }
490
491 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
492 {
493 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
494 }
495
496 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
497 {
498 clock->m = i9xx_dpll_compute_m(clock);
499 clock->p = clock->p1 * clock->p2;
500 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
501 return 0;
502 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
503 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
504
505 return clock->dot;
506 }
507
508 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
509 {
510 clock->m = clock->m1 * clock->m2;
511 clock->p = clock->p1 * clock->p2;
512 if (WARN_ON(clock->n == 0 || clock->p == 0))
513 return 0;
514 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
515 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
516
517 return clock->dot / 5;
518 }
519
520 int chv_calc_dpll_params(int refclk, struct dpll *clock)
521 {
522 clock->m = clock->m1 * clock->m2;
523 clock->p = clock->p1 * clock->p2;
524 if (WARN_ON(clock->n == 0 || clock->p == 0))
525 return 0;
526 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
527 clock->n << 22);
528 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
529
530 return clock->dot / 5;
531 }
532
533 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
534 /**
535 * Returns whether the given set of divisors are valid for a given refclk with
536 * the given connectors.
537 */
538
539 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
540 const struct intel_limit *limit,
541 const struct dpll *clock)
542 {
543 if (clock->n < limit->n.min || limit->n.max < clock->n)
544 INTELPllInvalid("n out of range\n");
545 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
546 INTELPllInvalid("p1 out of range\n");
547 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
548 INTELPllInvalid("m2 out of range\n");
549 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
550 INTELPllInvalid("m1 out of range\n");
551
552 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
553 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
554 if (clock->m1 <= clock->m2)
555 INTELPllInvalid("m1 <= m2\n");
556
557 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
558 !IS_GEN9_LP(dev_priv)) {
559 if (clock->p < limit->p.min || limit->p.max < clock->p)
560 INTELPllInvalid("p out of range\n");
561 if (clock->m < limit->m.min || limit->m.max < clock->m)
562 INTELPllInvalid("m out of range\n");
563 }
564
565 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
566 INTELPllInvalid("vco out of range\n");
567 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
568 * connector, etc., rather than just a single range.
569 */
570 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
571 INTELPllInvalid("dot out of range\n");
572
573 return true;
574 }
575
576 static int
577 i9xx_select_p2_div(const struct intel_limit *limit,
578 const struct intel_crtc_state *crtc_state,
579 int target)
580 {
581 struct drm_device *dev = crtc_state->base.crtc->dev;
582
583 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
584 /*
585 * For LVDS just rely on its current settings for dual-channel.
586 * We haven't figured out how to reliably set up different
587 * single/dual channel state, if we even can.
588 */
589 if (intel_is_dual_link_lvds(dev))
590 return limit->p2.p2_fast;
591 else
592 return limit->p2.p2_slow;
593 } else {
594 if (target < limit->p2.dot_limit)
595 return limit->p2.p2_slow;
596 else
597 return limit->p2.p2_fast;
598 }
599 }
600
601 /*
602 * Returns a set of divisors for the desired target clock with the given
603 * refclk, or FALSE. The returned values represent the clock equation:
604 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
605 *
606 * Target and reference clocks are specified in kHz.
607 *
608 * If match_clock is provided, then best_clock P divider must match the P
609 * divider from @match_clock used for LVDS downclocking.
610 */
611 static bool
612 i9xx_find_best_dpll(const struct intel_limit *limit,
613 struct intel_crtc_state *crtc_state,
614 int target, int refclk, struct dpll *match_clock,
615 struct dpll *best_clock)
616 {
617 struct drm_device *dev = crtc_state->base.crtc->dev;
618 struct dpll clock;
619 int err = target;
620
621 memset(best_clock, 0, sizeof(*best_clock));
622
623 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
624
625 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
626 clock.m1++) {
627 for (clock.m2 = limit->m2.min;
628 clock.m2 <= limit->m2.max; clock.m2++) {
629 if (clock.m2 >= clock.m1)
630 break;
631 for (clock.n = limit->n.min;
632 clock.n <= limit->n.max; clock.n++) {
633 for (clock.p1 = limit->p1.min;
634 clock.p1 <= limit->p1.max; clock.p1++) {
635 int this_err;
636
637 i9xx_calc_dpll_params(refclk, &clock);
638 if (!intel_PLL_is_valid(to_i915(dev),
639 limit,
640 &clock))
641 continue;
642 if (match_clock &&
643 clock.p != match_clock->p)
644 continue;
645
646 this_err = abs(clock.dot - target);
647 if (this_err < err) {
648 *best_clock = clock;
649 err = this_err;
650 }
651 }
652 }
653 }
654 }
655
656 return (err != target);
657 }
658
659 /*
660 * Returns a set of divisors for the desired target clock with the given
661 * refclk, or FALSE. The returned values represent the clock equation:
662 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
663 *
664 * Target and reference clocks are specified in kHz.
665 *
666 * If match_clock is provided, then best_clock P divider must match the P
667 * divider from @match_clock used for LVDS downclocking.
668 */
669 static bool
670 pnv_find_best_dpll(const struct intel_limit *limit,
671 struct intel_crtc_state *crtc_state,
672 int target, int refclk, struct dpll *match_clock,
673 struct dpll *best_clock)
674 {
675 struct drm_device *dev = crtc_state->base.crtc->dev;
676 struct dpll clock;
677 int err = target;
678
679 memset(best_clock, 0, sizeof(*best_clock));
680
681 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
682
683 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
684 clock.m1++) {
685 for (clock.m2 = limit->m2.min;
686 clock.m2 <= limit->m2.max; clock.m2++) {
687 for (clock.n = limit->n.min;
688 clock.n <= limit->n.max; clock.n++) {
689 for (clock.p1 = limit->p1.min;
690 clock.p1 <= limit->p1.max; clock.p1++) {
691 int this_err;
692
693 pnv_calc_dpll_params(refclk, &clock);
694 if (!intel_PLL_is_valid(to_i915(dev),
695 limit,
696 &clock))
697 continue;
698 if (match_clock &&
699 clock.p != match_clock->p)
700 continue;
701
702 this_err = abs(clock.dot - target);
703 if (this_err < err) {
704 *best_clock = clock;
705 err = this_err;
706 }
707 }
708 }
709 }
710 }
711
712 return (err != target);
713 }
714
715 /*
716 * Returns a set of divisors for the desired target clock with the given
717 * refclk, or FALSE. The returned values represent the clock equation:
718 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
719 *
720 * Target and reference clocks are specified in kHz.
721 *
722 * If match_clock is provided, then best_clock P divider must match the P
723 * divider from @match_clock used for LVDS downclocking.
724 */
725 static bool
726 g4x_find_best_dpll(const struct intel_limit *limit,
727 struct intel_crtc_state *crtc_state,
728 int target, int refclk, struct dpll *match_clock,
729 struct dpll *best_clock)
730 {
731 struct drm_device *dev = crtc_state->base.crtc->dev;
732 struct dpll clock;
733 int max_n;
734 bool found = false;
735 /* approximately equals target * 0.00585 */
736 int err_most = (target >> 8) + (target >> 9);
737
738 memset(best_clock, 0, sizeof(*best_clock));
739
740 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
741
742 max_n = limit->n.max;
743 /* based on hardware requirement, prefer smaller n to precision */
744 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
745 /* based on hardware requirement, prefere larger m1,m2 */
746 for (clock.m1 = limit->m1.max;
747 clock.m1 >= limit->m1.min; clock.m1--) {
748 for (clock.m2 = limit->m2.max;
749 clock.m2 >= limit->m2.min; clock.m2--) {
750 for (clock.p1 = limit->p1.max;
751 clock.p1 >= limit->p1.min; clock.p1--) {
752 int this_err;
753
754 i9xx_calc_dpll_params(refclk, &clock);
755 if (!intel_PLL_is_valid(to_i915(dev),
756 limit,
757 &clock))
758 continue;
759
760 this_err = abs(clock.dot - target);
761 if (this_err < err_most) {
762 *best_clock = clock;
763 err_most = this_err;
764 max_n = clock.n;
765 found = true;
766 }
767 }
768 }
769 }
770 }
771 return found;
772 }
773
774 /*
775 * Check if the calculated PLL configuration is more optimal compared to the
776 * best configuration and error found so far. Return the calculated error.
777 */
778 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
779 const struct dpll *calculated_clock,
780 const struct dpll *best_clock,
781 unsigned int best_error_ppm,
782 unsigned int *error_ppm)
783 {
784 /*
785 * For CHV ignore the error and consider only the P value.
786 * Prefer a bigger P value based on HW requirements.
787 */
788 if (IS_CHERRYVIEW(to_i915(dev))) {
789 *error_ppm = 0;
790
791 return calculated_clock->p > best_clock->p;
792 }
793
794 if (WARN_ON_ONCE(!target_freq))
795 return false;
796
797 *error_ppm = div_u64(1000000ULL *
798 abs(target_freq - calculated_clock->dot),
799 target_freq);
800 /*
801 * Prefer a better P value over a better (smaller) error if the error
802 * is small. Ensure this preference for future configurations too by
803 * setting the error to 0.
804 */
805 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
806 *error_ppm = 0;
807
808 return true;
809 }
810
811 return *error_ppm + 10 < best_error_ppm;
812 }
813
814 /*
815 * Returns a set of divisors for the desired target clock with the given
816 * refclk, or FALSE. The returned values represent the clock equation:
817 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
818 */
819 static bool
820 vlv_find_best_dpll(const struct intel_limit *limit,
821 struct intel_crtc_state *crtc_state,
822 int target, int refclk, struct dpll *match_clock,
823 struct dpll *best_clock)
824 {
825 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
826 struct drm_device *dev = crtc->base.dev;
827 struct dpll clock;
828 unsigned int bestppm = 1000000;
829 /* min update 19.2 MHz */
830 int max_n = min(limit->n.max, refclk / 19200);
831 bool found = false;
832
833 target *= 5; /* fast clock */
834
835 memset(best_clock, 0, sizeof(*best_clock));
836
837 /* based on hardware requirement, prefer smaller n to precision */
838 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
839 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
840 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
841 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
842 clock.p = clock.p1 * clock.p2;
843 /* based on hardware requirement, prefer bigger m1,m2 values */
844 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
845 unsigned int ppm;
846
847 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
848 refclk * clock.m1);
849
850 vlv_calc_dpll_params(refclk, &clock);
851
852 if (!intel_PLL_is_valid(to_i915(dev),
853 limit,
854 &clock))
855 continue;
856
857 if (!vlv_PLL_is_optimal(dev, target,
858 &clock,
859 best_clock,
860 bestppm, &ppm))
861 continue;
862
863 *best_clock = clock;
864 bestppm = ppm;
865 found = true;
866 }
867 }
868 }
869 }
870
871 return found;
872 }
873
874 /*
875 * Returns a set of divisors for the desired target clock with the given
876 * refclk, or FALSE. The returned values represent the clock equation:
877 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
878 */
879 static bool
880 chv_find_best_dpll(const struct intel_limit *limit,
881 struct intel_crtc_state *crtc_state,
882 int target, int refclk, struct dpll *match_clock,
883 struct dpll *best_clock)
884 {
885 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
886 struct drm_device *dev = crtc->base.dev;
887 unsigned int best_error_ppm;
888 struct dpll clock;
889 uint64_t m2;
890 int found = false;
891
892 memset(best_clock, 0, sizeof(*best_clock));
893 best_error_ppm = 1000000;
894
895 /*
896 * Based on hardware doc, the n always set to 1, and m1 always
897 * set to 2. If requires to support 200Mhz refclk, we need to
898 * revisit this because n may not 1 anymore.
899 */
900 clock.n = 1, clock.m1 = 2;
901 target *= 5; /* fast clock */
902
903 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
904 for (clock.p2 = limit->p2.p2_fast;
905 clock.p2 >= limit->p2.p2_slow;
906 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
907 unsigned int error_ppm;
908
909 clock.p = clock.p1 * clock.p2;
910
911 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
912 clock.n) << 22, refclk * clock.m1);
913
914 if (m2 > INT_MAX/clock.m1)
915 continue;
916
917 clock.m2 = m2;
918
919 chv_calc_dpll_params(refclk, &clock);
920
921 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
922 continue;
923
924 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
925 best_error_ppm, &error_ppm))
926 continue;
927
928 *best_clock = clock;
929 best_error_ppm = error_ppm;
930 found = true;
931 }
932 }
933
934 return found;
935 }
936
937 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
938 struct dpll *best_clock)
939 {
940 int refclk = 100000;
941 const struct intel_limit *limit = &intel_limits_bxt;
942
943 return chv_find_best_dpll(limit, crtc_state,
944 target_clock, refclk, NULL, best_clock);
945 }
946
947 bool intel_crtc_active(struct intel_crtc *crtc)
948 {
949 /* Be paranoid as we can arrive here with only partial
950 * state retrieved from the hardware during setup.
951 *
952 * We can ditch the adjusted_mode.crtc_clock check as soon
953 * as Haswell has gained clock readout/fastboot support.
954 *
955 * We can ditch the crtc->primary->fb check as soon as we can
956 * properly reconstruct framebuffers.
957 *
958 * FIXME: The intel_crtc->active here should be switched to
959 * crtc->state->active once we have proper CRTC states wired up
960 * for atomic.
961 */
962 return crtc->active && crtc->base.primary->state->fb &&
963 crtc->config->base.adjusted_mode.crtc_clock;
964 }
965
966 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
967 enum pipe pipe)
968 {
969 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
970
971 return crtc->config->cpu_transcoder;
972 }
973
974 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
975 {
976 i915_reg_t reg = PIPEDSL(pipe);
977 u32 line1, line2;
978 u32 line_mask;
979
980 if (IS_GEN2(dev_priv))
981 line_mask = DSL_LINEMASK_GEN2;
982 else
983 line_mask = DSL_LINEMASK_GEN3;
984
985 line1 = I915_READ(reg) & line_mask;
986 msleep(5);
987 line2 = I915_READ(reg) & line_mask;
988
989 return line1 == line2;
990 }
991
992 /*
993 * intel_wait_for_pipe_off - wait for pipe to turn off
994 * @crtc: crtc whose pipe to wait for
995 *
996 * After disabling a pipe, we can't wait for vblank in the usual way,
997 * spinning on the vblank interrupt status bit, since we won't actually
998 * see an interrupt when the pipe is disabled.
999 *
1000 * On Gen4 and above:
1001 * wait for the pipe register state bit to turn off
1002 *
1003 * Otherwise:
1004 * wait for the display line value to settle (it usually
1005 * ends up stopping at the start of the next frame).
1006 *
1007 */
1008 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1009 {
1010 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1011 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1012 enum pipe pipe = crtc->pipe;
1013
1014 if (INTEL_GEN(dev_priv) >= 4) {
1015 i915_reg_t reg = PIPECONF(cpu_transcoder);
1016
1017 /* Wait for the Pipe State to go off */
1018 if (intel_wait_for_register(dev_priv,
1019 reg, I965_PIPECONF_ACTIVE, 0,
1020 100))
1021 WARN(1, "pipe_off wait timed out\n");
1022 } else {
1023 /* Wait for the display line to settle */
1024 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1025 WARN(1, "pipe_off wait timed out\n");
1026 }
1027 }
1028
1029 /* Only for pre-ILK configs */
1030 void assert_pll(struct drm_i915_private *dev_priv,
1031 enum pipe pipe, bool state)
1032 {
1033 u32 val;
1034 bool cur_state;
1035
1036 val = I915_READ(DPLL(pipe));
1037 cur_state = !!(val & DPLL_VCO_ENABLE);
1038 I915_STATE_WARN(cur_state != state,
1039 "PLL state assertion failure (expected %s, current %s)\n",
1040 onoff(state), onoff(cur_state));
1041 }
1042
1043 /* XXX: the dsi pll is shared between MIPI DSI ports */
1044 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1045 {
1046 u32 val;
1047 bool cur_state;
1048
1049 mutex_lock(&dev_priv->sb_lock);
1050 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1051 mutex_unlock(&dev_priv->sb_lock);
1052
1053 cur_state = val & DSI_PLL_VCO_EN;
1054 I915_STATE_WARN(cur_state != state,
1055 "DSI PLL state assertion failure (expected %s, current %s)\n",
1056 onoff(state), onoff(cur_state));
1057 }
1058
1059 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1060 enum pipe pipe, bool state)
1061 {
1062 bool cur_state;
1063 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1064 pipe);
1065
1066 if (HAS_DDI(dev_priv)) {
1067 /* DDI does not have a specific FDI_TX register */
1068 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1069 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1070 } else {
1071 u32 val = I915_READ(FDI_TX_CTL(pipe));
1072 cur_state = !!(val & FDI_TX_ENABLE);
1073 }
1074 I915_STATE_WARN(cur_state != state,
1075 "FDI TX state assertion failure (expected %s, current %s)\n",
1076 onoff(state), onoff(cur_state));
1077 }
1078 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1079 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1080
1081 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1082 enum pipe pipe, bool state)
1083 {
1084 u32 val;
1085 bool cur_state;
1086
1087 val = I915_READ(FDI_RX_CTL(pipe));
1088 cur_state = !!(val & FDI_RX_ENABLE);
1089 I915_STATE_WARN(cur_state != state,
1090 "FDI RX state assertion failure (expected %s, current %s)\n",
1091 onoff(state), onoff(cur_state));
1092 }
1093 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1094 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1095
1096 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1097 enum pipe pipe)
1098 {
1099 u32 val;
1100
1101 /* ILK FDI PLL is always enabled */
1102 if (IS_GEN5(dev_priv))
1103 return;
1104
1105 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1106 if (HAS_DDI(dev_priv))
1107 return;
1108
1109 val = I915_READ(FDI_TX_CTL(pipe));
1110 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1111 }
1112
1113 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1114 enum pipe pipe, bool state)
1115 {
1116 u32 val;
1117 bool cur_state;
1118
1119 val = I915_READ(FDI_RX_CTL(pipe));
1120 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1121 I915_STATE_WARN(cur_state != state,
1122 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1123 onoff(state), onoff(cur_state));
1124 }
1125
1126 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1127 {
1128 i915_reg_t pp_reg;
1129 u32 val;
1130 enum pipe panel_pipe = PIPE_A;
1131 bool locked = true;
1132
1133 if (WARN_ON(HAS_DDI(dev_priv)))
1134 return;
1135
1136 if (HAS_PCH_SPLIT(dev_priv)) {
1137 u32 port_sel;
1138
1139 pp_reg = PP_CONTROL(0);
1140 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1141
1142 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1143 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1144 panel_pipe = PIPE_B;
1145 /* XXX: else fix for eDP */
1146 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1147 /* presumably write lock depends on pipe, not port select */
1148 pp_reg = PP_CONTROL(pipe);
1149 panel_pipe = pipe;
1150 } else {
1151 pp_reg = PP_CONTROL(0);
1152 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1153 panel_pipe = PIPE_B;
1154 }
1155
1156 val = I915_READ(pp_reg);
1157 if (!(val & PANEL_POWER_ON) ||
1158 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1159 locked = false;
1160
1161 I915_STATE_WARN(panel_pipe == pipe && locked,
1162 "panel assertion failure, pipe %c regs locked\n",
1163 pipe_name(pipe));
1164 }
1165
1166 static void assert_cursor(struct drm_i915_private *dev_priv,
1167 enum pipe pipe, bool state)
1168 {
1169 bool cur_state;
1170
1171 if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1172 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1173 else
1174 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1175
1176 I915_STATE_WARN(cur_state != state,
1177 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1178 pipe_name(pipe), onoff(state), onoff(cur_state));
1179 }
1180 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1181 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1182
1183 void assert_pipe(struct drm_i915_private *dev_priv,
1184 enum pipe pipe, bool state)
1185 {
1186 bool cur_state;
1187 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1188 pipe);
1189 enum intel_display_power_domain power_domain;
1190
1191 /* we keep both pipes enabled on 830 */
1192 if (IS_I830(dev_priv))
1193 state = true;
1194
1195 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1196 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1197 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1198 cur_state = !!(val & PIPECONF_ENABLE);
1199
1200 intel_display_power_put(dev_priv, power_domain);
1201 } else {
1202 cur_state = false;
1203 }
1204
1205 I915_STATE_WARN(cur_state != state,
1206 "pipe %c assertion failure (expected %s, current %s)\n",
1207 pipe_name(pipe), onoff(state), onoff(cur_state));
1208 }
1209
1210 static void assert_plane(struct drm_i915_private *dev_priv,
1211 enum plane plane, bool state)
1212 {
1213 u32 val;
1214 bool cur_state;
1215
1216 val = I915_READ(DSPCNTR(plane));
1217 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1218 I915_STATE_WARN(cur_state != state,
1219 "plane %c assertion failure (expected %s, current %s)\n",
1220 plane_name(plane), onoff(state), onoff(cur_state));
1221 }
1222
1223 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1224 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1225
1226 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1227 enum pipe pipe)
1228 {
1229 int i;
1230
1231 /* Primary planes are fixed to pipes on gen4+ */
1232 if (INTEL_GEN(dev_priv) >= 4) {
1233 u32 val = I915_READ(DSPCNTR(pipe));
1234 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1235 "plane %c assertion failure, should be disabled but not\n",
1236 plane_name(pipe));
1237 return;
1238 }
1239
1240 /* Need to check both planes against the pipe */
1241 for_each_pipe(dev_priv, i) {
1242 u32 val = I915_READ(DSPCNTR(i));
1243 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1244 DISPPLANE_SEL_PIPE_SHIFT;
1245 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1246 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1247 plane_name(i), pipe_name(pipe));
1248 }
1249 }
1250
1251 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1252 enum pipe pipe)
1253 {
1254 int sprite;
1255
1256 if (INTEL_GEN(dev_priv) >= 9) {
1257 for_each_sprite(dev_priv, pipe, sprite) {
1258 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1259 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1260 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1261 sprite, pipe_name(pipe));
1262 }
1263 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1264 for_each_sprite(dev_priv, pipe, sprite) {
1265 u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1266 I915_STATE_WARN(val & SP_ENABLE,
1267 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1268 sprite_name(pipe, sprite), pipe_name(pipe));
1269 }
1270 } else if (INTEL_GEN(dev_priv) >= 7) {
1271 u32 val = I915_READ(SPRCTL(pipe));
1272 I915_STATE_WARN(val & SPRITE_ENABLE,
1273 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1274 plane_name(pipe), pipe_name(pipe));
1275 } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
1276 u32 val = I915_READ(DVSCNTR(pipe));
1277 I915_STATE_WARN(val & DVS_ENABLE,
1278 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1279 plane_name(pipe), pipe_name(pipe));
1280 }
1281 }
1282
1283 static void assert_vblank_disabled(struct drm_crtc *crtc)
1284 {
1285 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1286 drm_crtc_vblank_put(crtc);
1287 }
1288
1289 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1290 enum pipe pipe)
1291 {
1292 u32 val;
1293 bool enabled;
1294
1295 val = I915_READ(PCH_TRANSCONF(pipe));
1296 enabled = !!(val & TRANS_ENABLE);
1297 I915_STATE_WARN(enabled,
1298 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1299 pipe_name(pipe));
1300 }
1301
1302 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1303 enum pipe pipe, u32 port_sel, u32 val)
1304 {
1305 if ((val & DP_PORT_EN) == 0)
1306 return false;
1307
1308 if (HAS_PCH_CPT(dev_priv)) {
1309 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1310 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1311 return false;
1312 } else if (IS_CHERRYVIEW(dev_priv)) {
1313 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1314 return false;
1315 } else {
1316 if ((val & DP_PIPE_MASK) != (pipe << 30))
1317 return false;
1318 }
1319 return true;
1320 }
1321
1322 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1323 enum pipe pipe, u32 val)
1324 {
1325 if ((val & SDVO_ENABLE) == 0)
1326 return false;
1327
1328 if (HAS_PCH_CPT(dev_priv)) {
1329 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1330 return false;
1331 } else if (IS_CHERRYVIEW(dev_priv)) {
1332 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1333 return false;
1334 } else {
1335 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1336 return false;
1337 }
1338 return true;
1339 }
1340
1341 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1342 enum pipe pipe, u32 val)
1343 {
1344 if ((val & LVDS_PORT_EN) == 0)
1345 return false;
1346
1347 if (HAS_PCH_CPT(dev_priv)) {
1348 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1349 return false;
1350 } else {
1351 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1352 return false;
1353 }
1354 return true;
1355 }
1356
1357 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1358 enum pipe pipe, u32 val)
1359 {
1360 if ((val & ADPA_DAC_ENABLE) == 0)
1361 return false;
1362 if (HAS_PCH_CPT(dev_priv)) {
1363 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1364 return false;
1365 } else {
1366 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1367 return false;
1368 }
1369 return true;
1370 }
1371
1372 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe, i915_reg_t reg,
1374 u32 port_sel)
1375 {
1376 u32 val = I915_READ(reg);
1377 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1378 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1379 i915_mmio_reg_offset(reg), pipe_name(pipe));
1380
1381 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1382 && (val & DP_PIPEB_SELECT),
1383 "IBX PCH dp port still using transcoder B\n");
1384 }
1385
1386 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1387 enum pipe pipe, i915_reg_t reg)
1388 {
1389 u32 val = I915_READ(reg);
1390 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1391 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1392 i915_mmio_reg_offset(reg), pipe_name(pipe));
1393
1394 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1395 && (val & SDVO_PIPE_B_SELECT),
1396 "IBX PCH hdmi port still using transcoder B\n");
1397 }
1398
1399 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1400 enum pipe pipe)
1401 {
1402 u32 val;
1403
1404 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1405 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1406 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1407
1408 val = I915_READ(PCH_ADPA);
1409 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1410 "PCH VGA enabled on transcoder %c, should be disabled\n",
1411 pipe_name(pipe));
1412
1413 val = I915_READ(PCH_LVDS);
1414 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1415 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1416 pipe_name(pipe));
1417
1418 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1419 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1420 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1421 }
1422
1423 static void _vlv_enable_pll(struct intel_crtc *crtc,
1424 const struct intel_crtc_state *pipe_config)
1425 {
1426 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1427 enum pipe pipe = crtc->pipe;
1428
1429 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1430 POSTING_READ(DPLL(pipe));
1431 udelay(150);
1432
1433 if (intel_wait_for_register(dev_priv,
1434 DPLL(pipe),
1435 DPLL_LOCK_VLV,
1436 DPLL_LOCK_VLV,
1437 1))
1438 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1439 }
1440
1441 static void vlv_enable_pll(struct intel_crtc *crtc,
1442 const struct intel_crtc_state *pipe_config)
1443 {
1444 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1445 enum pipe pipe = crtc->pipe;
1446
1447 assert_pipe_disabled(dev_priv, pipe);
1448
1449 /* PLL is protected by panel, make sure we can write it */
1450 assert_panel_unlocked(dev_priv, pipe);
1451
1452 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1453 _vlv_enable_pll(crtc, pipe_config);
1454
1455 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1456 POSTING_READ(DPLL_MD(pipe));
1457 }
1458
1459
1460 static void _chv_enable_pll(struct intel_crtc *crtc,
1461 const struct intel_crtc_state *pipe_config)
1462 {
1463 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1464 enum pipe pipe = crtc->pipe;
1465 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1466 u32 tmp;
1467
1468 mutex_lock(&dev_priv->sb_lock);
1469
1470 /* Enable back the 10bit clock to display controller */
1471 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1472 tmp |= DPIO_DCLKP_EN;
1473 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1474
1475 mutex_unlock(&dev_priv->sb_lock);
1476
1477 /*
1478 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1479 */
1480 udelay(1);
1481
1482 /* Enable PLL */
1483 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1484
1485 /* Check PLL is locked */
1486 if (intel_wait_for_register(dev_priv,
1487 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1488 1))
1489 DRM_ERROR("PLL %d failed to lock\n", pipe);
1490 }
1491
1492 static void chv_enable_pll(struct intel_crtc *crtc,
1493 const struct intel_crtc_state *pipe_config)
1494 {
1495 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1496 enum pipe pipe = crtc->pipe;
1497
1498 assert_pipe_disabled(dev_priv, pipe);
1499
1500 /* PLL is protected by panel, make sure we can write it */
1501 assert_panel_unlocked(dev_priv, pipe);
1502
1503 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1504 _chv_enable_pll(crtc, pipe_config);
1505
1506 if (pipe != PIPE_A) {
1507 /*
1508 * WaPixelRepeatModeFixForC0:chv
1509 *
1510 * DPLLCMD is AWOL. Use chicken bits to propagate
1511 * the value from DPLLBMD to either pipe B or C.
1512 */
1513 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1514 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1515 I915_WRITE(CBR4_VLV, 0);
1516 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1517
1518 /*
1519 * DPLLB VGA mode also seems to cause problems.
1520 * We should always have it disabled.
1521 */
1522 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1523 } else {
1524 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1525 POSTING_READ(DPLL_MD(pipe));
1526 }
1527 }
1528
1529 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1530 {
1531 struct intel_crtc *crtc;
1532 int count = 0;
1533
1534 for_each_intel_crtc(&dev_priv->drm, crtc) {
1535 count += crtc->base.state->active &&
1536 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1537 }
1538
1539 return count;
1540 }
1541
1542 static void i9xx_enable_pll(struct intel_crtc *crtc)
1543 {
1544 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1545 i915_reg_t reg = DPLL(crtc->pipe);
1546 u32 dpll = crtc->config->dpll_hw_state.dpll;
1547 int i;
1548
1549 assert_pipe_disabled(dev_priv, crtc->pipe);
1550
1551 /* PLL is protected by panel, make sure we can write it */
1552 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1553 assert_panel_unlocked(dev_priv, crtc->pipe);
1554
1555 /* Enable DVO 2x clock on both PLLs if necessary */
1556 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1557 /*
1558 * It appears to be important that we don't enable this
1559 * for the current pipe before otherwise configuring the
1560 * PLL. No idea how this should be handled if multiple
1561 * DVO outputs are enabled simultaneosly.
1562 */
1563 dpll |= DPLL_DVO_2X_MODE;
1564 I915_WRITE(DPLL(!crtc->pipe),
1565 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1566 }
1567
1568 /*
1569 * Apparently we need to have VGA mode enabled prior to changing
1570 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1571 * dividers, even though the register value does change.
1572 */
1573 I915_WRITE(reg, 0);
1574
1575 I915_WRITE(reg, dpll);
1576
1577 /* Wait for the clocks to stabilize. */
1578 POSTING_READ(reg);
1579 udelay(150);
1580
1581 if (INTEL_GEN(dev_priv) >= 4) {
1582 I915_WRITE(DPLL_MD(crtc->pipe),
1583 crtc->config->dpll_hw_state.dpll_md);
1584 } else {
1585 /* The pixel multiplier can only be updated once the
1586 * DPLL is enabled and the clocks are stable.
1587 *
1588 * So write it again.
1589 */
1590 I915_WRITE(reg, dpll);
1591 }
1592
1593 /* We do this three times for luck */
1594 for (i = 0; i < 3; i++) {
1595 I915_WRITE(reg, dpll);
1596 POSTING_READ(reg);
1597 udelay(150); /* wait for warmup */
1598 }
1599 }
1600
1601 /**
1602 * i9xx_disable_pll - disable a PLL
1603 * @dev_priv: i915 private structure
1604 * @pipe: pipe PLL to disable
1605 *
1606 * Disable the PLL for @pipe, making sure the pipe is off first.
1607 *
1608 * Note! This is for pre-ILK only.
1609 */
1610 static void i9xx_disable_pll(struct intel_crtc *crtc)
1611 {
1612 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1613 enum pipe pipe = crtc->pipe;
1614
1615 /* Disable DVO 2x clock on both PLLs if necessary */
1616 if (IS_I830(dev_priv) &&
1617 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1618 !intel_num_dvo_pipes(dev_priv)) {
1619 I915_WRITE(DPLL(PIPE_B),
1620 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1621 I915_WRITE(DPLL(PIPE_A),
1622 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1623 }
1624
1625 /* Don't disable pipe or pipe PLLs if needed */
1626 if (IS_I830(dev_priv))
1627 return;
1628
1629 /* Make sure the pipe isn't still relying on us */
1630 assert_pipe_disabled(dev_priv, pipe);
1631
1632 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1633 POSTING_READ(DPLL(pipe));
1634 }
1635
1636 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1637 {
1638 u32 val;
1639
1640 /* Make sure the pipe isn't still relying on us */
1641 assert_pipe_disabled(dev_priv, pipe);
1642
1643 val = DPLL_INTEGRATED_REF_CLK_VLV |
1644 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1645 if (pipe != PIPE_A)
1646 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1647
1648 I915_WRITE(DPLL(pipe), val);
1649 POSTING_READ(DPLL(pipe));
1650 }
1651
1652 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1653 {
1654 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1655 u32 val;
1656
1657 /* Make sure the pipe isn't still relying on us */
1658 assert_pipe_disabled(dev_priv, pipe);
1659
1660 val = DPLL_SSC_REF_CLK_CHV |
1661 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1662 if (pipe != PIPE_A)
1663 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1664
1665 I915_WRITE(DPLL(pipe), val);
1666 POSTING_READ(DPLL(pipe));
1667
1668 mutex_lock(&dev_priv->sb_lock);
1669
1670 /* Disable 10bit clock to display controller */
1671 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1672 val &= ~DPIO_DCLKP_EN;
1673 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1674
1675 mutex_unlock(&dev_priv->sb_lock);
1676 }
1677
1678 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1679 struct intel_digital_port *dport,
1680 unsigned int expected_mask)
1681 {
1682 u32 port_mask;
1683 i915_reg_t dpll_reg;
1684
1685 switch (dport->port) {
1686 case PORT_B:
1687 port_mask = DPLL_PORTB_READY_MASK;
1688 dpll_reg = DPLL(0);
1689 break;
1690 case PORT_C:
1691 port_mask = DPLL_PORTC_READY_MASK;
1692 dpll_reg = DPLL(0);
1693 expected_mask <<= 4;
1694 break;
1695 case PORT_D:
1696 port_mask = DPLL_PORTD_READY_MASK;
1697 dpll_reg = DPIO_PHY_STATUS;
1698 break;
1699 default:
1700 BUG();
1701 }
1702
1703 if (intel_wait_for_register(dev_priv,
1704 dpll_reg, port_mask, expected_mask,
1705 1000))
1706 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1707 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1708 }
1709
1710 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1711 enum pipe pipe)
1712 {
1713 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1714 pipe);
1715 i915_reg_t reg;
1716 uint32_t val, pipeconf_val;
1717
1718 /* Make sure PCH DPLL is enabled */
1719 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1720
1721 /* FDI must be feeding us bits for PCH ports */
1722 assert_fdi_tx_enabled(dev_priv, pipe);
1723 assert_fdi_rx_enabled(dev_priv, pipe);
1724
1725 if (HAS_PCH_CPT(dev_priv)) {
1726 /* Workaround: Set the timing override bit before enabling the
1727 * pch transcoder. */
1728 reg = TRANS_CHICKEN2(pipe);
1729 val = I915_READ(reg);
1730 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1731 I915_WRITE(reg, val);
1732 }
1733
1734 reg = PCH_TRANSCONF(pipe);
1735 val = I915_READ(reg);
1736 pipeconf_val = I915_READ(PIPECONF(pipe));
1737
1738 if (HAS_PCH_IBX(dev_priv)) {
1739 /*
1740 * Make the BPC in transcoder be consistent with
1741 * that in pipeconf reg. For HDMI we must use 8bpc
1742 * here for both 8bpc and 12bpc.
1743 */
1744 val &= ~PIPECONF_BPC_MASK;
1745 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1746 val |= PIPECONF_8BPC;
1747 else
1748 val |= pipeconf_val & PIPECONF_BPC_MASK;
1749 }
1750
1751 val &= ~TRANS_INTERLACE_MASK;
1752 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1753 if (HAS_PCH_IBX(dev_priv) &&
1754 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1755 val |= TRANS_LEGACY_INTERLACED_ILK;
1756 else
1757 val |= TRANS_INTERLACED;
1758 else
1759 val |= TRANS_PROGRESSIVE;
1760
1761 I915_WRITE(reg, val | TRANS_ENABLE);
1762 if (intel_wait_for_register(dev_priv,
1763 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1764 100))
1765 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1766 }
1767
1768 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1769 enum transcoder cpu_transcoder)
1770 {
1771 u32 val, pipeconf_val;
1772
1773 /* FDI must be feeding us bits for PCH ports */
1774 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1775 assert_fdi_rx_enabled(dev_priv, PIPE_A);
1776
1777 /* Workaround: set timing override bit. */
1778 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1779 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1780 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1781
1782 val = TRANS_ENABLE;
1783 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1784
1785 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1786 PIPECONF_INTERLACED_ILK)
1787 val |= TRANS_INTERLACED;
1788 else
1789 val |= TRANS_PROGRESSIVE;
1790
1791 I915_WRITE(LPT_TRANSCONF, val);
1792 if (intel_wait_for_register(dev_priv,
1793 LPT_TRANSCONF,
1794 TRANS_STATE_ENABLE,
1795 TRANS_STATE_ENABLE,
1796 100))
1797 DRM_ERROR("Failed to enable PCH transcoder\n");
1798 }
1799
1800 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1801 enum pipe pipe)
1802 {
1803 i915_reg_t reg;
1804 uint32_t val;
1805
1806 /* FDI relies on the transcoder */
1807 assert_fdi_tx_disabled(dev_priv, pipe);
1808 assert_fdi_rx_disabled(dev_priv, pipe);
1809
1810 /* Ports must be off as well */
1811 assert_pch_ports_disabled(dev_priv, pipe);
1812
1813 reg = PCH_TRANSCONF(pipe);
1814 val = I915_READ(reg);
1815 val &= ~TRANS_ENABLE;
1816 I915_WRITE(reg, val);
1817 /* wait for PCH transcoder off, transcoder state */
1818 if (intel_wait_for_register(dev_priv,
1819 reg, TRANS_STATE_ENABLE, 0,
1820 50))
1821 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1822
1823 if (HAS_PCH_CPT(dev_priv)) {
1824 /* Workaround: Clear the timing override chicken bit again. */
1825 reg = TRANS_CHICKEN2(pipe);
1826 val = I915_READ(reg);
1827 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1828 I915_WRITE(reg, val);
1829 }
1830 }
1831
1832 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1833 {
1834 u32 val;
1835
1836 val = I915_READ(LPT_TRANSCONF);
1837 val &= ~TRANS_ENABLE;
1838 I915_WRITE(LPT_TRANSCONF, val);
1839 /* wait for PCH transcoder off, transcoder state */
1840 if (intel_wait_for_register(dev_priv,
1841 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1842 50))
1843 DRM_ERROR("Failed to disable PCH transcoder\n");
1844
1845 /* Workaround: clear timing override bit. */
1846 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1847 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1848 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1849 }
1850
1851 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1852 {
1853 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1854
1855 WARN_ON(!crtc->config->has_pch_encoder);
1856
1857 if (HAS_PCH_LPT(dev_priv))
1858 return PIPE_A;
1859 else
1860 return crtc->pipe;
1861 }
1862
1863 /**
1864 * intel_enable_pipe - enable a pipe, asserting requirements
1865 * @crtc: crtc responsible for the pipe
1866 *
1867 * Enable @crtc's pipe, making sure that various hardware specific requirements
1868 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1869 */
1870 static void intel_enable_pipe(struct intel_crtc *crtc)
1871 {
1872 struct drm_device *dev = crtc->base.dev;
1873 struct drm_i915_private *dev_priv = to_i915(dev);
1874 enum pipe pipe = crtc->pipe;
1875 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1876 i915_reg_t reg;
1877 u32 val;
1878
1879 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1880
1881 assert_planes_disabled(dev_priv, pipe);
1882 assert_cursor_disabled(dev_priv, pipe);
1883 assert_sprites_disabled(dev_priv, pipe);
1884
1885 /*
1886 * A pipe without a PLL won't actually be able to drive bits from
1887 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1888 * need the check.
1889 */
1890 if (HAS_GMCH_DISPLAY(dev_priv)) {
1891 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1892 assert_dsi_pll_enabled(dev_priv);
1893 else
1894 assert_pll_enabled(dev_priv, pipe);
1895 } else {
1896 if (crtc->config->has_pch_encoder) {
1897 /* if driving the PCH, we need FDI enabled */
1898 assert_fdi_rx_pll_enabled(dev_priv,
1899 intel_crtc_pch_transcoder(crtc));
1900 assert_fdi_tx_pll_enabled(dev_priv,
1901 (enum pipe) cpu_transcoder);
1902 }
1903 /* FIXME: assert CPU port conditions for SNB+ */
1904 }
1905
1906 reg = PIPECONF(cpu_transcoder);
1907 val = I915_READ(reg);
1908 if (val & PIPECONF_ENABLE) {
1909 /* we keep both pipes enabled on 830 */
1910 WARN_ON(!IS_I830(dev_priv));
1911 return;
1912 }
1913
1914 I915_WRITE(reg, val | PIPECONF_ENABLE);
1915 POSTING_READ(reg);
1916
1917 /*
1918 * Until the pipe starts DSL will read as 0, which would cause
1919 * an apparent vblank timestamp jump, which messes up also the
1920 * frame count when it's derived from the timestamps. So let's
1921 * wait for the pipe to start properly before we call
1922 * drm_crtc_vblank_on()
1923 */
1924 if (dev->max_vblank_count == 0 &&
1925 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1926 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1927 }
1928
1929 /**
1930 * intel_disable_pipe - disable a pipe, asserting requirements
1931 * @crtc: crtc whose pipes is to be disabled
1932 *
1933 * Disable the pipe of @crtc, making sure that various hardware
1934 * specific requirements are met, if applicable, e.g. plane
1935 * disabled, panel fitter off, etc.
1936 *
1937 * Will wait until the pipe has shut down before returning.
1938 */
1939 static void intel_disable_pipe(struct intel_crtc *crtc)
1940 {
1941 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1942 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1943 enum pipe pipe = crtc->pipe;
1944 i915_reg_t reg;
1945 u32 val;
1946
1947 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1948
1949 /*
1950 * Make sure planes won't keep trying to pump pixels to us,
1951 * or we might hang the display.
1952 */
1953 assert_planes_disabled(dev_priv, pipe);
1954 assert_cursor_disabled(dev_priv, pipe);
1955 assert_sprites_disabled(dev_priv, pipe);
1956
1957 reg = PIPECONF(cpu_transcoder);
1958 val = I915_READ(reg);
1959 if ((val & PIPECONF_ENABLE) == 0)
1960 return;
1961
1962 /*
1963 * Double wide has implications for planes
1964 * so best keep it disabled when not needed.
1965 */
1966 if (crtc->config->double_wide)
1967 val &= ~PIPECONF_DOUBLE_WIDE;
1968
1969 /* Don't disable pipe or pipe PLLs if needed */
1970 if (!IS_I830(dev_priv))
1971 val &= ~PIPECONF_ENABLE;
1972
1973 I915_WRITE(reg, val);
1974 if ((val & PIPECONF_ENABLE) == 0)
1975 intel_wait_for_pipe_off(crtc);
1976 }
1977
1978 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1979 {
1980 return IS_GEN2(dev_priv) ? 2048 : 4096;
1981 }
1982
1983 static unsigned int
1984 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
1985 {
1986 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1987 unsigned int cpp = fb->format->cpp[plane];
1988
1989 switch (fb->modifier) {
1990 case DRM_FORMAT_MOD_LINEAR:
1991 return cpp;
1992 case I915_FORMAT_MOD_X_TILED:
1993 if (IS_GEN2(dev_priv))
1994 return 128;
1995 else
1996 return 512;
1997 case I915_FORMAT_MOD_Y_TILED:
1998 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
1999 return 128;
2000 else
2001 return 512;
2002 case I915_FORMAT_MOD_Yf_TILED:
2003 switch (cpp) {
2004 case 1:
2005 return 64;
2006 case 2:
2007 case 4:
2008 return 128;
2009 case 8:
2010 case 16:
2011 return 256;
2012 default:
2013 MISSING_CASE(cpp);
2014 return cpp;
2015 }
2016 break;
2017 default:
2018 MISSING_CASE(fb->modifier);
2019 return cpp;
2020 }
2021 }
2022
2023 static unsigned int
2024 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2025 {
2026 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
2027 return 1;
2028 else
2029 return intel_tile_size(to_i915(fb->dev)) /
2030 intel_tile_width_bytes(fb, plane);
2031 }
2032
2033 /* Return the tile dimensions in pixel units */
2034 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2035 unsigned int *tile_width,
2036 unsigned int *tile_height)
2037 {
2038 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2039 unsigned int cpp = fb->format->cpp[plane];
2040
2041 *tile_width = tile_width_bytes / cpp;
2042 *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2043 }
2044
2045 unsigned int
2046 intel_fb_align_height(const struct drm_framebuffer *fb,
2047 int plane, unsigned int height)
2048 {
2049 unsigned int tile_height = intel_tile_height(fb, plane);
2050
2051 return ALIGN(height, tile_height);
2052 }
2053
2054 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2055 {
2056 unsigned int size = 0;
2057 int i;
2058
2059 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2060 size += rot_info->plane[i].width * rot_info->plane[i].height;
2061
2062 return size;
2063 }
2064
2065 static void
2066 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2067 const struct drm_framebuffer *fb,
2068 unsigned int rotation)
2069 {
2070 view->type = I915_GGTT_VIEW_NORMAL;
2071 if (drm_rotation_90_or_270(rotation)) {
2072 view->type = I915_GGTT_VIEW_ROTATED;
2073 view->rotated = to_intel_framebuffer(fb)->rot_info;
2074 }
2075 }
2076
2077 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2078 {
2079 if (IS_I830(dev_priv))
2080 return 16 * 1024;
2081 else if (IS_I85X(dev_priv))
2082 return 256;
2083 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2084 return 32;
2085 else
2086 return 4 * 1024;
2087 }
2088
2089 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2090 {
2091 if (INTEL_INFO(dev_priv)->gen >= 9)
2092 return 256 * 1024;
2093 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2094 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2095 return 128 * 1024;
2096 else if (INTEL_INFO(dev_priv)->gen >= 4)
2097 return 4 * 1024;
2098 else
2099 return 0;
2100 }
2101
2102 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2103 int plane)
2104 {
2105 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2106
2107 /* AUX_DIST needs only 4K alignment */
2108 if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
2109 return 4096;
2110
2111 switch (fb->modifier) {
2112 case DRM_FORMAT_MOD_LINEAR:
2113 return intel_linear_alignment(dev_priv);
2114 case I915_FORMAT_MOD_X_TILED:
2115 if (INTEL_GEN(dev_priv) >= 9)
2116 return 256 * 1024;
2117 return 0;
2118 case I915_FORMAT_MOD_Y_TILED:
2119 case I915_FORMAT_MOD_Yf_TILED:
2120 return 1 * 1024 * 1024;
2121 default:
2122 MISSING_CASE(fb->modifier);
2123 return 0;
2124 }
2125 }
2126
2127 struct i915_vma *
2128 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2129 {
2130 struct drm_device *dev = fb->dev;
2131 struct drm_i915_private *dev_priv = to_i915(dev);
2132 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2133 struct i915_ggtt_view view;
2134 struct i915_vma *vma;
2135 u32 alignment;
2136
2137 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2138
2139 alignment = intel_surf_alignment(fb, 0);
2140
2141 intel_fill_fb_ggtt_view(&view, fb, rotation);
2142
2143 /* Note that the w/a also requires 64 PTE of padding following the
2144 * bo. We currently fill all unused PTE with the shadow page and so
2145 * we should always have valid PTE following the scanout preventing
2146 * the VT-d warning.
2147 */
2148 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2149 alignment = 256 * 1024;
2150
2151 /*
2152 * Global gtt pte registers are special registers which actually forward
2153 * writes to a chunk of system memory. Which means that there is no risk
2154 * that the register values disappear as soon as we call
2155 * intel_runtime_pm_put(), so it is correct to wrap only the
2156 * pin/unpin/fence and not more.
2157 */
2158 intel_runtime_pm_get(dev_priv);
2159
2160 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2161 if (IS_ERR(vma))
2162 goto err;
2163
2164 if (i915_vma_is_map_and_fenceable(vma)) {
2165 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2166 * fence, whereas 965+ only requires a fence if using
2167 * framebuffer compression. For simplicity, we always, when
2168 * possible, install a fence as the cost is not that onerous.
2169 *
2170 * If we fail to fence the tiled scanout, then either the
2171 * modeset will reject the change (which is highly unlikely as
2172 * the affected systems, all but one, do not have unmappable
2173 * space) or we will not be able to enable full powersaving
2174 * techniques (also likely not to apply due to various limits
2175 * FBC and the like impose on the size of the buffer, which
2176 * presumably we violated anyway with this unmappable buffer).
2177 * Anyway, it is presumably better to stumble onwards with
2178 * something and try to run the system in a "less than optimal"
2179 * mode that matches the user configuration.
2180 */
2181 if (i915_vma_get_fence(vma) == 0)
2182 i915_vma_pin_fence(vma);
2183 }
2184
2185 i915_vma_get(vma);
2186 err:
2187 intel_runtime_pm_put(dev_priv);
2188 return vma;
2189 }
2190
2191 void intel_unpin_fb_vma(struct i915_vma *vma)
2192 {
2193 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2194
2195 i915_vma_unpin_fence(vma);
2196 i915_gem_object_unpin_from_display_plane(vma);
2197 i915_vma_put(vma);
2198 }
2199
2200 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2201 unsigned int rotation)
2202 {
2203 if (drm_rotation_90_or_270(rotation))
2204 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2205 else
2206 return fb->pitches[plane];
2207 }
2208
2209 /*
2210 * Convert the x/y offsets into a linear offset.
2211 * Only valid with 0/180 degree rotation, which is fine since linear
2212 * offset is only used with linear buffers on pre-hsw and tiled buffers
2213 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2214 */
2215 u32 intel_fb_xy_to_linear(int x, int y,
2216 const struct intel_plane_state *state,
2217 int plane)
2218 {
2219 const struct drm_framebuffer *fb = state->base.fb;
2220 unsigned int cpp = fb->format->cpp[plane];
2221 unsigned int pitch = fb->pitches[plane];
2222
2223 return y * pitch + x * cpp;
2224 }
2225
2226 /*
2227 * Add the x/y offsets derived from fb->offsets[] to the user
2228 * specified plane src x/y offsets. The resulting x/y offsets
2229 * specify the start of scanout from the beginning of the gtt mapping.
2230 */
2231 void intel_add_fb_offsets(int *x, int *y,
2232 const struct intel_plane_state *state,
2233 int plane)
2234
2235 {
2236 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2237 unsigned int rotation = state->base.rotation;
2238
2239 if (drm_rotation_90_or_270(rotation)) {
2240 *x += intel_fb->rotated[plane].x;
2241 *y += intel_fb->rotated[plane].y;
2242 } else {
2243 *x += intel_fb->normal[plane].x;
2244 *y += intel_fb->normal[plane].y;
2245 }
2246 }
2247
2248 /*
2249 * Input tile dimensions and pitch must already be
2250 * rotated to match x and y, and in pixel units.
2251 */
2252 static u32 _intel_adjust_tile_offset(int *x, int *y,
2253 unsigned int tile_width,
2254 unsigned int tile_height,
2255 unsigned int tile_size,
2256 unsigned int pitch_tiles,
2257 u32 old_offset,
2258 u32 new_offset)
2259 {
2260 unsigned int pitch_pixels = pitch_tiles * tile_width;
2261 unsigned int tiles;
2262
2263 WARN_ON(old_offset & (tile_size - 1));
2264 WARN_ON(new_offset & (tile_size - 1));
2265 WARN_ON(new_offset > old_offset);
2266
2267 tiles = (old_offset - new_offset) / tile_size;
2268
2269 *y += tiles / pitch_tiles * tile_height;
2270 *x += tiles % pitch_tiles * tile_width;
2271
2272 /* minimize x in case it got needlessly big */
2273 *y += *x / pitch_pixels * tile_height;
2274 *x %= pitch_pixels;
2275
2276 return new_offset;
2277 }
2278
2279 /*
2280 * Adjust the tile offset by moving the difference into
2281 * the x/y offsets.
2282 */
2283 static u32 intel_adjust_tile_offset(int *x, int *y,
2284 const struct intel_plane_state *state, int plane,
2285 u32 old_offset, u32 new_offset)
2286 {
2287 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2288 const struct drm_framebuffer *fb = state->base.fb;
2289 unsigned int cpp = fb->format->cpp[plane];
2290 unsigned int rotation = state->base.rotation;
2291 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2292
2293 WARN_ON(new_offset > old_offset);
2294
2295 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2296 unsigned int tile_size, tile_width, tile_height;
2297 unsigned int pitch_tiles;
2298
2299 tile_size = intel_tile_size(dev_priv);
2300 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2301
2302 if (drm_rotation_90_or_270(rotation)) {
2303 pitch_tiles = pitch / tile_height;
2304 swap(tile_width, tile_height);
2305 } else {
2306 pitch_tiles = pitch / (tile_width * cpp);
2307 }
2308
2309 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2310 tile_size, pitch_tiles,
2311 old_offset, new_offset);
2312 } else {
2313 old_offset += *y * pitch + *x * cpp;
2314
2315 *y = (old_offset - new_offset) / pitch;
2316 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2317 }
2318
2319 return new_offset;
2320 }
2321
2322 /*
2323 * Computes the linear offset to the base tile and adjusts
2324 * x, y. bytes per pixel is assumed to be a power-of-two.
2325 *
2326 * In the 90/270 rotated case, x and y are assumed
2327 * to be already rotated to match the rotated GTT view, and
2328 * pitch is the tile_height aligned framebuffer height.
2329 *
2330 * This function is used when computing the derived information
2331 * under intel_framebuffer, so using any of that information
2332 * here is not allowed. Anything under drm_framebuffer can be
2333 * used. This is why the user has to pass in the pitch since it
2334 * is specified in the rotated orientation.
2335 */
2336 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2337 int *x, int *y,
2338 const struct drm_framebuffer *fb, int plane,
2339 unsigned int pitch,
2340 unsigned int rotation,
2341 u32 alignment)
2342 {
2343 uint64_t fb_modifier = fb->modifier;
2344 unsigned int cpp = fb->format->cpp[plane];
2345 u32 offset, offset_aligned;
2346
2347 if (alignment)
2348 alignment--;
2349
2350 if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2351 unsigned int tile_size, tile_width, tile_height;
2352 unsigned int tile_rows, tiles, pitch_tiles;
2353
2354 tile_size = intel_tile_size(dev_priv);
2355 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2356
2357 if (drm_rotation_90_or_270(rotation)) {
2358 pitch_tiles = pitch / tile_height;
2359 swap(tile_width, tile_height);
2360 } else {
2361 pitch_tiles = pitch / (tile_width * cpp);
2362 }
2363
2364 tile_rows = *y / tile_height;
2365 *y %= tile_height;
2366
2367 tiles = *x / tile_width;
2368 *x %= tile_width;
2369
2370 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2371 offset_aligned = offset & ~alignment;
2372
2373 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2374 tile_size, pitch_tiles,
2375 offset, offset_aligned);
2376 } else {
2377 offset = *y * pitch + *x * cpp;
2378 offset_aligned = offset & ~alignment;
2379
2380 *y = (offset & alignment) / pitch;
2381 *x = ((offset & alignment) - *y * pitch) / cpp;
2382 }
2383
2384 return offset_aligned;
2385 }
2386
2387 u32 intel_compute_tile_offset(int *x, int *y,
2388 const struct intel_plane_state *state,
2389 int plane)
2390 {
2391 struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2392 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2393 const struct drm_framebuffer *fb = state->base.fb;
2394 unsigned int rotation = state->base.rotation;
2395 int pitch = intel_fb_pitch(fb, plane, rotation);
2396 u32 alignment;
2397
2398 if (intel_plane->id == PLANE_CURSOR)
2399 alignment = intel_cursor_alignment(dev_priv);
2400 else
2401 alignment = intel_surf_alignment(fb, plane);
2402
2403 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2404 rotation, alignment);
2405 }
2406
2407 /* Convert the fb->offset[] linear offset into x/y offsets */
2408 static void intel_fb_offset_to_xy(int *x, int *y,
2409 const struct drm_framebuffer *fb, int plane)
2410 {
2411 unsigned int cpp = fb->format->cpp[plane];
2412 unsigned int pitch = fb->pitches[plane];
2413 u32 linear_offset = fb->offsets[plane];
2414
2415 *y = linear_offset / pitch;
2416 *x = linear_offset % pitch / cpp;
2417 }
2418
2419 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2420 {
2421 switch (fb_modifier) {
2422 case I915_FORMAT_MOD_X_TILED:
2423 return I915_TILING_X;
2424 case I915_FORMAT_MOD_Y_TILED:
2425 return I915_TILING_Y;
2426 default:
2427 return I915_TILING_NONE;
2428 }
2429 }
2430
2431 static int
2432 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2433 struct drm_framebuffer *fb)
2434 {
2435 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2436 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2437 u32 gtt_offset_rotated = 0;
2438 unsigned int max_size = 0;
2439 int i, num_planes = fb->format->num_planes;
2440 unsigned int tile_size = intel_tile_size(dev_priv);
2441
2442 for (i = 0; i < num_planes; i++) {
2443 unsigned int width, height;
2444 unsigned int cpp, size;
2445 u32 offset;
2446 int x, y;
2447
2448 cpp = fb->format->cpp[i];
2449 width = drm_framebuffer_plane_width(fb->width, fb, i);
2450 height = drm_framebuffer_plane_height(fb->height, fb, i);
2451
2452 intel_fb_offset_to_xy(&x, &y, fb, i);
2453
2454 /*
2455 * The fence (if used) is aligned to the start of the object
2456 * so having the framebuffer wrap around across the edge of the
2457 * fenced region doesn't really work. We have no API to configure
2458 * the fence start offset within the object (nor could we probably
2459 * on gen2/3). So it's just easier if we just require that the
2460 * fb layout agrees with the fence layout. We already check that the
2461 * fb stride matches the fence stride elsewhere.
2462 */
2463 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2464 (x + width) * cpp > fb->pitches[i]) {
2465 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2466 i, fb->offsets[i]);
2467 return -EINVAL;
2468 }
2469
2470 /*
2471 * First pixel of the framebuffer from
2472 * the start of the normal gtt mapping.
2473 */
2474 intel_fb->normal[i].x = x;
2475 intel_fb->normal[i].y = y;
2476
2477 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2478 fb, i, fb->pitches[i],
2479 DRM_MODE_ROTATE_0, tile_size);
2480 offset /= tile_size;
2481
2482 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2483 unsigned int tile_width, tile_height;
2484 unsigned int pitch_tiles;
2485 struct drm_rect r;
2486
2487 intel_tile_dims(fb, i, &tile_width, &tile_height);
2488
2489 rot_info->plane[i].offset = offset;
2490 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2491 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2492 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2493
2494 intel_fb->rotated[i].pitch =
2495 rot_info->plane[i].height * tile_height;
2496
2497 /* how many tiles does this plane need */
2498 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2499 /*
2500 * If the plane isn't horizontally tile aligned,
2501 * we need one more tile.
2502 */
2503 if (x != 0)
2504 size++;
2505
2506 /* rotate the x/y offsets to match the GTT view */
2507 r.x1 = x;
2508 r.y1 = y;
2509 r.x2 = x + width;
2510 r.y2 = y + height;
2511 drm_rect_rotate(&r,
2512 rot_info->plane[i].width * tile_width,
2513 rot_info->plane[i].height * tile_height,
2514 DRM_MODE_ROTATE_270);
2515 x = r.x1;
2516 y = r.y1;
2517
2518 /* rotate the tile dimensions to match the GTT view */
2519 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2520 swap(tile_width, tile_height);
2521
2522 /*
2523 * We only keep the x/y offsets, so push all of the
2524 * gtt offset into the x/y offsets.
2525 */
2526 _intel_adjust_tile_offset(&x, &y,
2527 tile_width, tile_height,
2528 tile_size, pitch_tiles,
2529 gtt_offset_rotated * tile_size, 0);
2530
2531 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2532
2533 /*
2534 * First pixel of the framebuffer from
2535 * the start of the rotated gtt mapping.
2536 */
2537 intel_fb->rotated[i].x = x;
2538 intel_fb->rotated[i].y = y;
2539 } else {
2540 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2541 x * cpp, tile_size);
2542 }
2543
2544 /* how many tiles in total needed in the bo */
2545 max_size = max(max_size, offset + size);
2546 }
2547
2548 if (max_size * tile_size > intel_fb->obj->base.size) {
2549 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2550 max_size * tile_size, intel_fb->obj->base.size);
2551 return -EINVAL;
2552 }
2553
2554 return 0;
2555 }
2556
2557 static int i9xx_format_to_fourcc(int format)
2558 {
2559 switch (format) {
2560 case DISPPLANE_8BPP:
2561 return DRM_FORMAT_C8;
2562 case DISPPLANE_BGRX555:
2563 return DRM_FORMAT_XRGB1555;
2564 case DISPPLANE_BGRX565:
2565 return DRM_FORMAT_RGB565;
2566 default:
2567 case DISPPLANE_BGRX888:
2568 return DRM_FORMAT_XRGB8888;
2569 case DISPPLANE_RGBX888:
2570 return DRM_FORMAT_XBGR8888;
2571 case DISPPLANE_BGRX101010:
2572 return DRM_FORMAT_XRGB2101010;
2573 case DISPPLANE_RGBX101010:
2574 return DRM_FORMAT_XBGR2101010;
2575 }
2576 }
2577
2578 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2579 {
2580 switch (format) {
2581 case PLANE_CTL_FORMAT_RGB_565:
2582 return DRM_FORMAT_RGB565;
2583 default:
2584 case PLANE_CTL_FORMAT_XRGB_8888:
2585 if (rgb_order) {
2586 if (alpha)
2587 return DRM_FORMAT_ABGR8888;
2588 else
2589 return DRM_FORMAT_XBGR8888;
2590 } else {
2591 if (alpha)
2592 return DRM_FORMAT_ARGB8888;
2593 else
2594 return DRM_FORMAT_XRGB8888;
2595 }
2596 case PLANE_CTL_FORMAT_XRGB_2101010:
2597 if (rgb_order)
2598 return DRM_FORMAT_XBGR2101010;
2599 else
2600 return DRM_FORMAT_XRGB2101010;
2601 }
2602 }
2603
2604 static bool
2605 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2606 struct intel_initial_plane_config *plane_config)
2607 {
2608 struct drm_device *dev = crtc->base.dev;
2609 struct drm_i915_private *dev_priv = to_i915(dev);
2610 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2611 struct drm_i915_gem_object *obj = NULL;
2612 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2613 struct drm_framebuffer *fb = &plane_config->fb->base;
2614 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2615 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2616 PAGE_SIZE);
2617
2618 size_aligned -= base_aligned;
2619
2620 if (plane_config->size == 0)
2621 return false;
2622
2623 /* If the FB is too big, just don't use it since fbdev is not very
2624 * important and we should probably use that space with FBC or other
2625 * features. */
2626 if (size_aligned * 2 > ggtt->stolen_usable_size)
2627 return false;
2628
2629 mutex_lock(&dev->struct_mutex);
2630 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2631 base_aligned,
2632 base_aligned,
2633 size_aligned);
2634 mutex_unlock(&dev->struct_mutex);
2635 if (!obj)
2636 return false;
2637
2638 if (plane_config->tiling == I915_TILING_X)
2639 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2640
2641 mode_cmd.pixel_format = fb->format->format;
2642 mode_cmd.width = fb->width;
2643 mode_cmd.height = fb->height;
2644 mode_cmd.pitches[0] = fb->pitches[0];
2645 mode_cmd.modifier[0] = fb->modifier;
2646 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2647
2648 if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2649 DRM_DEBUG_KMS("intel fb init failed\n");
2650 goto out_unref_obj;
2651 }
2652
2653
2654 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2655 return true;
2656
2657 out_unref_obj:
2658 i915_gem_object_put(obj);
2659 return false;
2660 }
2661
2662 static void
2663 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2664 struct intel_plane_state *plane_state,
2665 bool visible)
2666 {
2667 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2668
2669 plane_state->base.visible = visible;
2670
2671 /* FIXME pre-g4x don't work like this */
2672 if (visible) {
2673 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2674 crtc_state->active_planes |= BIT(plane->id);
2675 } else {
2676 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2677 crtc_state->active_planes &= ~BIT(plane->id);
2678 }
2679
2680 DRM_DEBUG_KMS("%s active planes 0x%x\n",
2681 crtc_state->base.crtc->name,
2682 crtc_state->active_planes);
2683 }
2684
2685 static void
2686 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2687 struct intel_initial_plane_config *plane_config)
2688 {
2689 struct drm_device *dev = intel_crtc->base.dev;
2690 struct drm_i915_private *dev_priv = to_i915(dev);
2691 struct drm_crtc *c;
2692 struct drm_i915_gem_object *obj;
2693 struct drm_plane *primary = intel_crtc->base.primary;
2694 struct drm_plane_state *plane_state = primary->state;
2695 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2696 struct intel_plane *intel_plane = to_intel_plane(primary);
2697 struct intel_plane_state *intel_state =
2698 to_intel_plane_state(plane_state);
2699 struct drm_framebuffer *fb;
2700
2701 if (!plane_config->fb)
2702 return;
2703
2704 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2705 fb = &plane_config->fb->base;
2706 goto valid_fb;
2707 }
2708
2709 kfree(plane_config->fb);
2710
2711 /*
2712 * Failed to alloc the obj, check to see if we should share
2713 * an fb with another CRTC instead
2714 */
2715 for_each_crtc(dev, c) {
2716 struct intel_plane_state *state;
2717
2718 if (c == &intel_crtc->base)
2719 continue;
2720
2721 if (!to_intel_crtc(c)->active)
2722 continue;
2723
2724 state = to_intel_plane_state(c->primary->state);
2725 if (!state->vma)
2726 continue;
2727
2728 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2729 fb = c->primary->fb;
2730 drm_framebuffer_reference(fb);
2731 goto valid_fb;
2732 }
2733 }
2734
2735 /*
2736 * We've failed to reconstruct the BIOS FB. Current display state
2737 * indicates that the primary plane is visible, but has a NULL FB,
2738 * which will lead to problems later if we don't fix it up. The
2739 * simplest solution is to just disable the primary plane now and
2740 * pretend the BIOS never had it enabled.
2741 */
2742 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2743 to_intel_plane_state(plane_state),
2744 false);
2745 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2746 trace_intel_disable_plane(primary, intel_crtc);
2747 intel_plane->disable_plane(intel_plane, intel_crtc);
2748
2749 return;
2750
2751 valid_fb:
2752 mutex_lock(&dev->struct_mutex);
2753 intel_state->vma =
2754 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2755 mutex_unlock(&dev->struct_mutex);
2756 if (IS_ERR(intel_state->vma)) {
2757 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2758 intel_crtc->pipe, PTR_ERR(intel_state->vma));
2759
2760 intel_state->vma = NULL;
2761 drm_framebuffer_unreference(fb);
2762 return;
2763 }
2764
2765 plane_state->src_x = 0;
2766 plane_state->src_y = 0;
2767 plane_state->src_w = fb->width << 16;
2768 plane_state->src_h = fb->height << 16;
2769
2770 plane_state->crtc_x = 0;
2771 plane_state->crtc_y = 0;
2772 plane_state->crtc_w = fb->width;
2773 plane_state->crtc_h = fb->height;
2774
2775 intel_state->base.src = drm_plane_state_src(plane_state);
2776 intel_state->base.dst = drm_plane_state_dest(plane_state);
2777
2778 obj = intel_fb_obj(fb);
2779 if (i915_gem_object_is_tiled(obj))
2780 dev_priv->preserve_bios_swizzle = true;
2781
2782 drm_framebuffer_reference(fb);
2783 primary->fb = primary->state->fb = fb;
2784 primary->crtc = primary->state->crtc = &intel_crtc->base;
2785
2786 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2787 to_intel_plane_state(plane_state),
2788 true);
2789
2790 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2791 &obj->frontbuffer_bits);
2792 }
2793
2794 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2795 unsigned int rotation)
2796 {
2797 int cpp = fb->format->cpp[plane];
2798
2799 switch (fb->modifier) {
2800 case DRM_FORMAT_MOD_LINEAR:
2801 case I915_FORMAT_MOD_X_TILED:
2802 switch (cpp) {
2803 case 8:
2804 return 4096;
2805 case 4:
2806 case 2:
2807 case 1:
2808 return 8192;
2809 default:
2810 MISSING_CASE(cpp);
2811 break;
2812 }
2813 break;
2814 case I915_FORMAT_MOD_Y_TILED:
2815 case I915_FORMAT_MOD_Yf_TILED:
2816 switch (cpp) {
2817 case 8:
2818 return 2048;
2819 case 4:
2820 return 4096;
2821 case 2:
2822 case 1:
2823 return 8192;
2824 default:
2825 MISSING_CASE(cpp);
2826 break;
2827 }
2828 break;
2829 default:
2830 MISSING_CASE(fb->modifier);
2831 }
2832
2833 return 2048;
2834 }
2835
2836 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2837 {
2838 const struct drm_framebuffer *fb = plane_state->base.fb;
2839 unsigned int rotation = plane_state->base.rotation;
2840 int x = plane_state->base.src.x1 >> 16;
2841 int y = plane_state->base.src.y1 >> 16;
2842 int w = drm_rect_width(&plane_state->base.src) >> 16;
2843 int h = drm_rect_height(&plane_state->base.src) >> 16;
2844 int max_width = skl_max_plane_width(fb, 0, rotation);
2845 int max_height = 4096;
2846 u32 alignment, offset, aux_offset = plane_state->aux.offset;
2847
2848 if (w > max_width || h > max_height) {
2849 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2850 w, h, max_width, max_height);
2851 return -EINVAL;
2852 }
2853
2854 intel_add_fb_offsets(&x, &y, plane_state, 0);
2855 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2856 alignment = intel_surf_alignment(fb, 0);
2857
2858 /*
2859 * AUX surface offset is specified as the distance from the
2860 * main surface offset, and it must be non-negative. Make
2861 * sure that is what we will get.
2862 */
2863 if (offset > aux_offset)
2864 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2865 offset, aux_offset & ~(alignment - 1));
2866
2867 /*
2868 * When using an X-tiled surface, the plane blows up
2869 * if the x offset + width exceed the stride.
2870 *
2871 * TODO: linear and Y-tiled seem fine, Yf untested,
2872 */
2873 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2874 int cpp = fb->format->cpp[0];
2875
2876 while ((x + w) * cpp > fb->pitches[0]) {
2877 if (offset == 0) {
2878 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2879 return -EINVAL;
2880 }
2881
2882 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2883 offset, offset - alignment);
2884 }
2885 }
2886
2887 plane_state->main.offset = offset;
2888 plane_state->main.x = x;
2889 plane_state->main.y = y;
2890
2891 return 0;
2892 }
2893
2894 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2895 {
2896 const struct drm_framebuffer *fb = plane_state->base.fb;
2897 unsigned int rotation = plane_state->base.rotation;
2898 int max_width = skl_max_plane_width(fb, 1, rotation);
2899 int max_height = 4096;
2900 int x = plane_state->base.src.x1 >> 17;
2901 int y = plane_state->base.src.y1 >> 17;
2902 int w = drm_rect_width(&plane_state->base.src) >> 17;
2903 int h = drm_rect_height(&plane_state->base.src) >> 17;
2904 u32 offset;
2905
2906 intel_add_fb_offsets(&x, &y, plane_state, 1);
2907 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2908
2909 /* FIXME not quite sure how/if these apply to the chroma plane */
2910 if (w > max_width || h > max_height) {
2911 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2912 w, h, max_width, max_height);
2913 return -EINVAL;
2914 }
2915
2916 plane_state->aux.offset = offset;
2917 plane_state->aux.x = x;
2918 plane_state->aux.y = y;
2919
2920 return 0;
2921 }
2922
2923 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2924 {
2925 const struct drm_framebuffer *fb = plane_state->base.fb;
2926 unsigned int rotation = plane_state->base.rotation;
2927 int ret;
2928
2929 if (!plane_state->base.visible)
2930 return 0;
2931
2932 /* Rotate src coordinates to match rotated GTT view */
2933 if (drm_rotation_90_or_270(rotation))
2934 drm_rect_rotate(&plane_state->base.src,
2935 fb->width << 16, fb->height << 16,
2936 DRM_MODE_ROTATE_270);
2937
2938 /*
2939 * Handle the AUX surface first since
2940 * the main surface setup depends on it.
2941 */
2942 if (fb->format->format == DRM_FORMAT_NV12) {
2943 ret = skl_check_nv12_aux_surface(plane_state);
2944 if (ret)
2945 return ret;
2946 } else {
2947 plane_state->aux.offset = ~0xfff;
2948 plane_state->aux.x = 0;
2949 plane_state->aux.y = 0;
2950 }
2951
2952 ret = skl_check_main_surface(plane_state);
2953 if (ret)
2954 return ret;
2955
2956 return 0;
2957 }
2958
2959 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
2960 const struct intel_plane_state *plane_state)
2961 {
2962 struct drm_i915_private *dev_priv =
2963 to_i915(plane_state->base.plane->dev);
2964 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2965 const struct drm_framebuffer *fb = plane_state->base.fb;
2966 unsigned int rotation = plane_state->base.rotation;
2967 u32 dspcntr;
2968
2969 dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
2970
2971 if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
2972 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
2973 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2974
2975 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2976 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2977
2978 if (INTEL_GEN(dev_priv) < 4)
2979 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
2980
2981 switch (fb->format->format) {
2982 case DRM_FORMAT_C8:
2983 dspcntr |= DISPPLANE_8BPP;
2984 break;
2985 case DRM_FORMAT_XRGB1555:
2986 dspcntr |= DISPPLANE_BGRX555;
2987 break;
2988 case DRM_FORMAT_RGB565:
2989 dspcntr |= DISPPLANE_BGRX565;
2990 break;
2991 case DRM_FORMAT_XRGB8888:
2992 dspcntr |= DISPPLANE_BGRX888;
2993 break;
2994 case DRM_FORMAT_XBGR8888:
2995 dspcntr |= DISPPLANE_RGBX888;
2996 break;
2997 case DRM_FORMAT_XRGB2101010:
2998 dspcntr |= DISPPLANE_BGRX101010;
2999 break;
3000 case DRM_FORMAT_XBGR2101010:
3001 dspcntr |= DISPPLANE_RGBX101010;
3002 break;
3003 default:
3004 MISSING_CASE(fb->format->format);
3005 return 0;
3006 }
3007
3008 if (INTEL_GEN(dev_priv) >= 4 &&
3009 fb->modifier == I915_FORMAT_MOD_X_TILED)
3010 dspcntr |= DISPPLANE_TILED;
3011
3012 if (rotation & DRM_MODE_ROTATE_180)
3013 dspcntr |= DISPPLANE_ROTATE_180;
3014
3015 if (rotation & DRM_MODE_REFLECT_X)
3016 dspcntr |= DISPPLANE_MIRROR;
3017
3018 return dspcntr;
3019 }
3020
3021 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3022 {
3023 struct drm_i915_private *dev_priv =
3024 to_i915(plane_state->base.plane->dev);
3025 int src_x = plane_state->base.src.x1 >> 16;
3026 int src_y = plane_state->base.src.y1 >> 16;
3027 u32 offset;
3028
3029 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3030
3031 if (INTEL_GEN(dev_priv) >= 4)
3032 offset = intel_compute_tile_offset(&src_x, &src_y,
3033 plane_state, 0);
3034 else
3035 offset = 0;
3036
3037 /* HSW/BDW do this automagically in hardware */
3038 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3039 unsigned int rotation = plane_state->base.rotation;
3040 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3041 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3042
3043 if (rotation & DRM_MODE_ROTATE_180) {
3044 src_x += src_w - 1;
3045 src_y += src_h - 1;
3046 } else if (rotation & DRM_MODE_REFLECT_X) {
3047 src_x += src_w - 1;
3048 }
3049 }
3050
3051 plane_state->main.offset = offset;
3052 plane_state->main.x = src_x;
3053 plane_state->main.y = src_y;
3054
3055 return 0;
3056 }
3057
3058 static void i9xx_update_primary_plane(struct intel_plane *primary,
3059 const struct intel_crtc_state *crtc_state,
3060 const struct intel_plane_state *plane_state)
3061 {
3062 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3063 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3064 const struct drm_framebuffer *fb = plane_state->base.fb;
3065 enum plane plane = primary->plane;
3066 u32 linear_offset;
3067 u32 dspcntr = plane_state->ctl;
3068 i915_reg_t reg = DSPCNTR(plane);
3069 int x = plane_state->main.x;
3070 int y = plane_state->main.y;
3071 unsigned long irqflags;
3072
3073 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3074
3075 if (INTEL_GEN(dev_priv) >= 4)
3076 crtc->dspaddr_offset = plane_state->main.offset;
3077 else
3078 crtc->dspaddr_offset = linear_offset;
3079
3080 crtc->adjusted_x = x;
3081 crtc->adjusted_y = y;
3082
3083 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3084
3085 if (INTEL_GEN(dev_priv) < 4) {
3086 /* pipesrc and dspsize control the size that is scaled from,
3087 * which should always be the user's requested size.
3088 */
3089 I915_WRITE_FW(DSPSIZE(plane),
3090 ((crtc_state->pipe_src_h - 1) << 16) |
3091 (crtc_state->pipe_src_w - 1));
3092 I915_WRITE_FW(DSPPOS(plane), 0);
3093 } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3094 I915_WRITE_FW(PRIMSIZE(plane),
3095 ((crtc_state->pipe_src_h - 1) << 16) |
3096 (crtc_state->pipe_src_w - 1));
3097 I915_WRITE_FW(PRIMPOS(plane), 0);
3098 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3099 }
3100
3101 I915_WRITE_FW(reg, dspcntr);
3102
3103 I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3104 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3105 I915_WRITE_FW(DSPSURF(plane),
3106 intel_plane_ggtt_offset(plane_state) +
3107 crtc->dspaddr_offset);
3108 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3109 } else if (INTEL_GEN(dev_priv) >= 4) {
3110 I915_WRITE_FW(DSPSURF(plane),
3111 intel_plane_ggtt_offset(plane_state) +
3112 crtc->dspaddr_offset);
3113 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3114 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3115 } else {
3116 I915_WRITE_FW(DSPADDR(plane),
3117 intel_plane_ggtt_offset(plane_state) +
3118 crtc->dspaddr_offset);
3119 }
3120 POSTING_READ_FW(reg);
3121
3122 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3123 }
3124
3125 static void i9xx_disable_primary_plane(struct intel_plane *primary,
3126 struct intel_crtc *crtc)
3127 {
3128 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3129 enum plane plane = primary->plane;
3130 unsigned long irqflags;
3131
3132 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3133
3134 I915_WRITE_FW(DSPCNTR(plane), 0);
3135 if (INTEL_INFO(dev_priv)->gen >= 4)
3136 I915_WRITE_FW(DSPSURF(plane), 0);
3137 else
3138 I915_WRITE_FW(DSPADDR(plane), 0);
3139 POSTING_READ_FW(DSPCNTR(plane));
3140
3141 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3142 }
3143
3144 static u32
3145 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3146 {
3147 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3148 return 64;
3149 else
3150 return intel_tile_width_bytes(fb, plane);
3151 }
3152
3153 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3154 {
3155 struct drm_device *dev = intel_crtc->base.dev;
3156 struct drm_i915_private *dev_priv = to_i915(dev);
3157
3158 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3159 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3160 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3161 }
3162
3163 /*
3164 * This function detaches (aka. unbinds) unused scalers in hardware
3165 */
3166 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3167 {
3168 struct intel_crtc_scaler_state *scaler_state;
3169 int i;
3170
3171 scaler_state = &intel_crtc->config->scaler_state;
3172
3173 /* loop through and disable scalers that aren't in use */
3174 for (i = 0; i < intel_crtc->num_scalers; i++) {
3175 if (!scaler_state->scalers[i].in_use)
3176 skl_detach_scaler(intel_crtc, i);
3177 }
3178 }
3179
3180 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3181 unsigned int rotation)
3182 {
3183 u32 stride;
3184
3185 if (plane >= fb->format->num_planes)
3186 return 0;
3187
3188 stride = intel_fb_pitch(fb, plane, rotation);
3189
3190 /*
3191 * The stride is either expressed as a multiple of 64 bytes chunks for
3192 * linear buffers or in number of tiles for tiled buffers.
3193 */
3194 if (drm_rotation_90_or_270(rotation))
3195 stride /= intel_tile_height(fb, plane);
3196 else
3197 stride /= intel_fb_stride_alignment(fb, plane);
3198
3199 return stride;
3200 }
3201
3202 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3203 {
3204 switch (pixel_format) {
3205 case DRM_FORMAT_C8:
3206 return PLANE_CTL_FORMAT_INDEXED;
3207 case DRM_FORMAT_RGB565:
3208 return PLANE_CTL_FORMAT_RGB_565;
3209 case DRM_FORMAT_XBGR8888:
3210 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3211 case DRM_FORMAT_XRGB8888:
3212 return PLANE_CTL_FORMAT_XRGB_8888;
3213 /*
3214 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3215 * to be already pre-multiplied. We need to add a knob (or a different
3216 * DRM_FORMAT) for user-space to configure that.
3217 */
3218 case DRM_FORMAT_ABGR8888:
3219 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3220 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3221 case DRM_FORMAT_ARGB8888:
3222 return PLANE_CTL_FORMAT_XRGB_8888 |
3223 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3224 case DRM_FORMAT_XRGB2101010:
3225 return PLANE_CTL_FORMAT_XRGB_2101010;
3226 case DRM_FORMAT_XBGR2101010:
3227 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3228 case DRM_FORMAT_YUYV:
3229 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3230 case DRM_FORMAT_YVYU:
3231 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3232 case DRM_FORMAT_UYVY:
3233 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3234 case DRM_FORMAT_VYUY:
3235 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3236 default:
3237 MISSING_CASE(pixel_format);
3238 }
3239
3240 return 0;
3241 }
3242
3243 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3244 {
3245 switch (fb_modifier) {
3246 case DRM_FORMAT_MOD_LINEAR:
3247 break;
3248 case I915_FORMAT_MOD_X_TILED:
3249 return PLANE_CTL_TILED_X;
3250 case I915_FORMAT_MOD_Y_TILED:
3251 return PLANE_CTL_TILED_Y;
3252 case I915_FORMAT_MOD_Yf_TILED:
3253 return PLANE_CTL_TILED_YF;
3254 default:
3255 MISSING_CASE(fb_modifier);
3256 }
3257
3258 return 0;
3259 }
3260
3261 static u32 skl_plane_ctl_rotation(unsigned int rotation)
3262 {
3263 switch (rotation) {
3264 case DRM_MODE_ROTATE_0:
3265 break;
3266 /*
3267 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3268 * while i915 HW rotation is clockwise, thats why this swapping.
3269 */
3270 case DRM_MODE_ROTATE_90:
3271 return PLANE_CTL_ROTATE_270;
3272 case DRM_MODE_ROTATE_180:
3273 return PLANE_CTL_ROTATE_180;
3274 case DRM_MODE_ROTATE_270:
3275 return PLANE_CTL_ROTATE_90;
3276 default:
3277 MISSING_CASE(rotation);
3278 }
3279
3280 return 0;
3281 }
3282
3283 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3284 const struct intel_plane_state *plane_state)
3285 {
3286 struct drm_i915_private *dev_priv =
3287 to_i915(plane_state->base.plane->dev);
3288 const struct drm_framebuffer *fb = plane_state->base.fb;
3289 unsigned int rotation = plane_state->base.rotation;
3290 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3291 u32 plane_ctl;
3292
3293 plane_ctl = PLANE_CTL_ENABLE;
3294
3295 if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
3296 plane_ctl |=
3297 PLANE_CTL_PIPE_GAMMA_ENABLE |
3298 PLANE_CTL_PIPE_CSC_ENABLE |
3299 PLANE_CTL_PLANE_GAMMA_DISABLE;
3300 }
3301
3302 plane_ctl |= skl_plane_ctl_format(fb->format->format);
3303 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3304 plane_ctl |= skl_plane_ctl_rotation(rotation);
3305
3306 if (key->flags & I915_SET_COLORKEY_DESTINATION)
3307 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3308 else if (key->flags & I915_SET_COLORKEY_SOURCE)
3309 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3310
3311 return plane_ctl;
3312 }
3313
3314 static void skylake_update_primary_plane(struct intel_plane *plane,
3315 const struct intel_crtc_state *crtc_state,
3316 const struct intel_plane_state *plane_state)
3317 {
3318 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3319 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3320 const struct drm_framebuffer *fb = plane_state->base.fb;
3321 enum plane_id plane_id = plane->id;
3322 enum pipe pipe = plane->pipe;
3323 u32 plane_ctl = plane_state->ctl;
3324 unsigned int rotation = plane_state->base.rotation;
3325 u32 stride = skl_plane_stride(fb, 0, rotation);
3326 u32 surf_addr = plane_state->main.offset;
3327 int scaler_id = plane_state->scaler_id;
3328 int src_x = plane_state->main.x;
3329 int src_y = plane_state->main.y;
3330 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3331 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3332 int dst_x = plane_state->base.dst.x1;
3333 int dst_y = plane_state->base.dst.y1;
3334 int dst_w = drm_rect_width(&plane_state->base.dst);
3335 int dst_h = drm_rect_height(&plane_state->base.dst);
3336 unsigned long irqflags;
3337
3338 /* Sizes are 0 based */
3339 src_w--;
3340 src_h--;
3341 dst_w--;
3342 dst_h--;
3343
3344 crtc->dspaddr_offset = surf_addr;
3345
3346 crtc->adjusted_x = src_x;
3347 crtc->adjusted_y = src_y;
3348
3349 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3350
3351 if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
3352 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
3353 PLANE_COLOR_PIPE_GAMMA_ENABLE |
3354 PLANE_COLOR_PIPE_CSC_ENABLE |
3355 PLANE_COLOR_PLANE_GAMMA_DISABLE);
3356 }
3357
3358 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
3359 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3360 I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
3361 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3362
3363 if (scaler_id >= 0) {
3364 uint32_t ps_ctrl = 0;
3365
3366 WARN_ON(!dst_w || !dst_h);
3367 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3368 crtc_state->scaler_state.scalers[scaler_id].mode;
3369 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3370 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3371 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3372 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3373 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
3374 } else {
3375 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3376 }
3377
3378 I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
3379 intel_plane_ggtt_offset(plane_state) + surf_addr);
3380
3381 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3382
3383 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3384 }
3385
3386 static void skylake_disable_primary_plane(struct intel_plane *primary,
3387 struct intel_crtc *crtc)
3388 {
3389 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3390 enum plane_id plane_id = primary->id;
3391 enum pipe pipe = primary->pipe;
3392 unsigned long irqflags;
3393
3394 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3395
3396 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
3397 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
3398 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3399
3400 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3401 }
3402
3403 static int
3404 __intel_display_resume(struct drm_device *dev,
3405 struct drm_atomic_state *state,
3406 struct drm_modeset_acquire_ctx *ctx)
3407 {
3408 struct drm_crtc_state *crtc_state;
3409 struct drm_crtc *crtc;
3410 int i, ret;
3411
3412 intel_modeset_setup_hw_state(dev, ctx);
3413 i915_redisable_vga(to_i915(dev));
3414
3415 if (!state)
3416 return 0;
3417
3418 /*
3419 * We've duplicated the state, pointers to the old state are invalid.
3420 *
3421 * Don't attempt to use the old state until we commit the duplicated state.
3422 */
3423 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3424 /*
3425 * Force recalculation even if we restore
3426 * current state. With fast modeset this may not result
3427 * in a modeset when the state is compatible.
3428 */
3429 crtc_state->mode_changed = true;
3430 }
3431
3432 /* ignore any reset values/BIOS leftovers in the WM registers */
3433 if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3434 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3435
3436 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3437
3438 WARN_ON(ret == -EDEADLK);
3439 return ret;
3440 }
3441
3442 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3443 {
3444 return intel_has_gpu_reset(dev_priv) &&
3445 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3446 }
3447
3448 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3449 {
3450 struct drm_device *dev = &dev_priv->drm;
3451 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3452 struct drm_atomic_state *state;
3453 int ret;
3454
3455
3456 /* reset doesn't touch the display */
3457 if (!i915.force_reset_modeset_test &&
3458 !gpu_reset_clobbers_display(dev_priv))
3459 return;
3460
3461 /*
3462 * Need mode_config.mutex so that we don't
3463 * trample ongoing ->detect() and whatnot.
3464 */
3465 mutex_lock(&dev->mode_config.mutex);
3466 drm_modeset_acquire_init(ctx, 0);
3467 while (1) {
3468 ret = drm_modeset_lock_all_ctx(dev, ctx);
3469 if (ret != -EDEADLK)
3470 break;
3471
3472 drm_modeset_backoff(ctx);
3473 }
3474 /*
3475 * Disabling the crtcs gracefully seems nicer. Also the
3476 * g33 docs say we should at least disable all the planes.
3477 */
3478 state = drm_atomic_helper_duplicate_state(dev, ctx);
3479 if (IS_ERR(state)) {
3480 ret = PTR_ERR(state);
3481 DRM_ERROR("Duplicating state failed with %i\n", ret);
3482 return;
3483 }
3484
3485 ret = drm_atomic_helper_disable_all(dev, ctx);
3486 if (ret) {
3487 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3488 drm_atomic_state_put(state);
3489 return;
3490 }
3491
3492 dev_priv->modeset_restore_state = state;
3493 state->acquire_ctx = ctx;
3494 }
3495
3496 void intel_finish_reset(struct drm_i915_private *dev_priv)
3497 {
3498 struct drm_device *dev = &dev_priv->drm;
3499 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3500 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3501 int ret;
3502
3503 /* reset doesn't touch the display */
3504 if (!i915.force_reset_modeset_test &&
3505 !gpu_reset_clobbers_display(dev_priv))
3506 return;
3507
3508 if (!state)
3509 goto unlock;
3510
3511 dev_priv->modeset_restore_state = NULL;
3512
3513 /* reset doesn't touch the display */
3514 if (!gpu_reset_clobbers_display(dev_priv)) {
3515 /* for testing only restore the display */
3516 ret = __intel_display_resume(dev, state, ctx);
3517 if (ret)
3518 DRM_ERROR("Restoring old state failed with %i\n", ret);
3519 } else {
3520 /*
3521 * The display has been reset as well,
3522 * so need a full re-initialization.
3523 */
3524 intel_runtime_pm_disable_interrupts(dev_priv);
3525 intel_runtime_pm_enable_interrupts(dev_priv);
3526
3527 intel_pps_unlock_regs_wa(dev_priv);
3528 intel_modeset_init_hw(dev);
3529
3530 spin_lock_irq(&dev_priv->irq_lock);
3531 if (dev_priv->display.hpd_irq_setup)
3532 dev_priv->display.hpd_irq_setup(dev_priv);
3533 spin_unlock_irq(&dev_priv->irq_lock);
3534
3535 ret = __intel_display_resume(dev, state, ctx);
3536 if (ret)
3537 DRM_ERROR("Restoring old state failed with %i\n", ret);
3538
3539 intel_hpd_init(dev_priv);
3540 }
3541
3542 drm_atomic_state_put(state);
3543 unlock:
3544 drm_modeset_drop_locks(ctx);
3545 drm_modeset_acquire_fini(ctx);
3546 mutex_unlock(&dev->mode_config.mutex);
3547 }
3548
3549 static void intel_update_pipe_config(struct intel_crtc *crtc,
3550 struct intel_crtc_state *old_crtc_state)
3551 {
3552 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3553 struct intel_crtc_state *pipe_config =
3554 to_intel_crtc_state(crtc->base.state);
3555
3556 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3557 crtc->base.mode = crtc->base.state->mode;
3558
3559 /*
3560 * Update pipe size and adjust fitter if needed: the reason for this is
3561 * that in compute_mode_changes we check the native mode (not the pfit
3562 * mode) to see if we can flip rather than do a full mode set. In the
3563 * fastboot case, we'll flip, but if we don't update the pipesrc and
3564 * pfit state, we'll end up with a big fb scanned out into the wrong
3565 * sized surface.
3566 */
3567
3568 I915_WRITE(PIPESRC(crtc->pipe),
3569 ((pipe_config->pipe_src_w - 1) << 16) |
3570 (pipe_config->pipe_src_h - 1));
3571
3572 /* on skylake this is done by detaching scalers */
3573 if (INTEL_GEN(dev_priv) >= 9) {
3574 skl_detach_scalers(crtc);
3575
3576 if (pipe_config->pch_pfit.enabled)
3577 skylake_pfit_enable(crtc);
3578 } else if (HAS_PCH_SPLIT(dev_priv)) {
3579 if (pipe_config->pch_pfit.enabled)
3580 ironlake_pfit_enable(crtc);
3581 else if (old_crtc_state->pch_pfit.enabled)
3582 ironlake_pfit_disable(crtc, true);
3583 }
3584 }
3585
3586 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3587 {
3588 struct drm_device *dev = crtc->base.dev;
3589 struct drm_i915_private *dev_priv = to_i915(dev);
3590 int pipe = crtc->pipe;
3591 i915_reg_t reg;
3592 u32 temp;
3593
3594 /* enable normal train */
3595 reg = FDI_TX_CTL(pipe);
3596 temp = I915_READ(reg);
3597 if (IS_IVYBRIDGE(dev_priv)) {
3598 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3599 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3600 } else {
3601 temp &= ~FDI_LINK_TRAIN_NONE;
3602 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3603 }
3604 I915_WRITE(reg, temp);
3605
3606 reg = FDI_RX_CTL(pipe);
3607 temp = I915_READ(reg);
3608 if (HAS_PCH_CPT(dev_priv)) {
3609 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3610 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3611 } else {
3612 temp &= ~FDI_LINK_TRAIN_NONE;
3613 temp |= FDI_LINK_TRAIN_NONE;
3614 }
3615 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3616
3617 /* wait one idle pattern time */
3618 POSTING_READ(reg);
3619 udelay(1000);
3620
3621 /* IVB wants error correction enabled */
3622 if (IS_IVYBRIDGE(dev_priv))
3623 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3624 FDI_FE_ERRC_ENABLE);
3625 }
3626
3627 /* The FDI link training functions for ILK/Ibexpeak. */
3628 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3629 const struct intel_crtc_state *crtc_state)
3630 {
3631 struct drm_device *dev = crtc->base.dev;
3632 struct drm_i915_private *dev_priv = to_i915(dev);
3633 int pipe = crtc->pipe;
3634 i915_reg_t reg;
3635 u32 temp, tries;
3636
3637 /* FDI needs bits from pipe first */
3638 assert_pipe_enabled(dev_priv, pipe);
3639
3640 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3641 for train result */
3642 reg = FDI_RX_IMR(pipe);
3643 temp = I915_READ(reg);
3644 temp &= ~FDI_RX_SYMBOL_LOCK;
3645 temp &= ~FDI_RX_BIT_LOCK;
3646 I915_WRITE(reg, temp);
3647 I915_READ(reg);
3648 udelay(150);
3649
3650 /* enable CPU FDI TX and PCH FDI RX */
3651 reg = FDI_TX_CTL(pipe);
3652 temp = I915_READ(reg);
3653 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3654 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3655 temp &= ~FDI_LINK_TRAIN_NONE;
3656 temp |= FDI_LINK_TRAIN_PATTERN_1;
3657 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3658
3659 reg = FDI_RX_CTL(pipe);
3660 temp = I915_READ(reg);
3661 temp &= ~FDI_LINK_TRAIN_NONE;
3662 temp |= FDI_LINK_TRAIN_PATTERN_1;
3663 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3664
3665 POSTING_READ(reg);
3666 udelay(150);
3667
3668 /* Ironlake workaround, enable clock pointer after FDI enable*/
3669 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3670 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3671 FDI_RX_PHASE_SYNC_POINTER_EN);
3672
3673 reg = FDI_RX_IIR(pipe);
3674 for (tries = 0; tries < 5; tries++) {
3675 temp = I915_READ(reg);
3676 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3677
3678 if ((temp & FDI_RX_BIT_LOCK)) {
3679 DRM_DEBUG_KMS("FDI train 1 done.\n");
3680 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3681 break;
3682 }
3683 }
3684 if (tries == 5)
3685 DRM_ERROR("FDI train 1 fail!\n");
3686
3687 /* Train 2 */
3688 reg = FDI_TX_CTL(pipe);
3689 temp = I915_READ(reg);
3690 temp &= ~FDI_LINK_TRAIN_NONE;
3691 temp |= FDI_LINK_TRAIN_PATTERN_2;
3692 I915_WRITE(reg, temp);
3693
3694 reg = FDI_RX_CTL(pipe);
3695 temp = I915_READ(reg);
3696 temp &= ~FDI_LINK_TRAIN_NONE;
3697 temp |= FDI_LINK_TRAIN_PATTERN_2;
3698 I915_WRITE(reg, temp);
3699
3700 POSTING_READ(reg);
3701 udelay(150);
3702
3703 reg = FDI_RX_IIR(pipe);
3704 for (tries = 0; tries < 5; tries++) {
3705 temp = I915_READ(reg);
3706 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3707
3708 if (temp & FDI_RX_SYMBOL_LOCK) {
3709 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3710 DRM_DEBUG_KMS("FDI train 2 done.\n");
3711 break;
3712 }
3713 }
3714 if (tries == 5)
3715 DRM_ERROR("FDI train 2 fail!\n");
3716
3717 DRM_DEBUG_KMS("FDI train done\n");
3718
3719 }
3720
3721 static const int snb_b_fdi_train_param[] = {
3722 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3723 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3724 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3725 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3726 };
3727
3728 /* The FDI link training functions for SNB/Cougarpoint. */
3729 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3730 const struct intel_crtc_state *crtc_state)
3731 {
3732 struct drm_device *dev = crtc->base.dev;
3733 struct drm_i915_private *dev_priv = to_i915(dev);
3734 int pipe = crtc->pipe;
3735 i915_reg_t reg;
3736 u32 temp, i, retry;
3737
3738 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3739 for train result */
3740 reg = FDI_RX_IMR(pipe);
3741 temp = I915_READ(reg);
3742 temp &= ~FDI_RX_SYMBOL_LOCK;
3743 temp &= ~FDI_RX_BIT_LOCK;
3744 I915_WRITE(reg, temp);
3745
3746 POSTING_READ(reg);
3747 udelay(150);
3748
3749 /* enable CPU FDI TX and PCH FDI RX */
3750 reg = FDI_TX_CTL(pipe);
3751 temp = I915_READ(reg);
3752 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3753 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3754 temp &= ~FDI_LINK_TRAIN_NONE;
3755 temp |= FDI_LINK_TRAIN_PATTERN_1;
3756 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3757 /* SNB-B */
3758 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3759 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3760
3761 I915_WRITE(FDI_RX_MISC(pipe),
3762 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3763
3764 reg = FDI_RX_CTL(pipe);
3765 temp = I915_READ(reg);
3766 if (HAS_PCH_CPT(dev_priv)) {
3767 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3768 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3769 } else {
3770 temp &= ~FDI_LINK_TRAIN_NONE;
3771 temp |= FDI_LINK_TRAIN_PATTERN_1;
3772 }
3773 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3774
3775 POSTING_READ(reg);
3776 udelay(150);
3777
3778 for (i = 0; i < 4; i++) {
3779 reg = FDI_TX_CTL(pipe);
3780 temp = I915_READ(reg);
3781 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3782 temp |= snb_b_fdi_train_param[i];
3783 I915_WRITE(reg, temp);
3784
3785 POSTING_READ(reg);
3786 udelay(500);
3787
3788 for (retry = 0; retry < 5; retry++) {
3789 reg = FDI_RX_IIR(pipe);
3790 temp = I915_READ(reg);
3791 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3792 if (temp & FDI_RX_BIT_LOCK) {
3793 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3794 DRM_DEBUG_KMS("FDI train 1 done.\n");
3795 break;
3796 }
3797 udelay(50);
3798 }
3799 if (retry < 5)
3800 break;
3801 }
3802 if (i == 4)
3803 DRM_ERROR("FDI train 1 fail!\n");
3804
3805 /* Train 2 */
3806 reg = FDI_TX_CTL(pipe);
3807 temp = I915_READ(reg);
3808 temp &= ~FDI_LINK_TRAIN_NONE;
3809 temp |= FDI_LINK_TRAIN_PATTERN_2;
3810 if (IS_GEN6(dev_priv)) {
3811 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3812 /* SNB-B */
3813 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3814 }
3815 I915_WRITE(reg, temp);
3816
3817 reg = FDI_RX_CTL(pipe);
3818 temp = I915_READ(reg);
3819 if (HAS_PCH_CPT(dev_priv)) {
3820 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3821 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3822 } else {
3823 temp &= ~FDI_LINK_TRAIN_NONE;
3824 temp |= FDI_LINK_TRAIN_PATTERN_2;
3825 }
3826 I915_WRITE(reg, temp);
3827
3828 POSTING_READ(reg);
3829 udelay(150);
3830
3831 for (i = 0; i < 4; i++) {
3832 reg = FDI_TX_CTL(pipe);
3833 temp = I915_READ(reg);
3834 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3835 temp |= snb_b_fdi_train_param[i];
3836 I915_WRITE(reg, temp);
3837
3838 POSTING_READ(reg);
3839 udelay(500);
3840
3841 for (retry = 0; retry < 5; retry++) {
3842 reg = FDI_RX_IIR(pipe);
3843 temp = I915_READ(reg);
3844 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3845 if (temp & FDI_RX_SYMBOL_LOCK) {
3846 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3847 DRM_DEBUG_KMS("FDI train 2 done.\n");
3848 break;
3849 }
3850 udelay(50);
3851 }
3852 if (retry < 5)
3853 break;
3854 }
3855 if (i == 4)
3856 DRM_ERROR("FDI train 2 fail!\n");
3857
3858 DRM_DEBUG_KMS("FDI train done.\n");
3859 }
3860
3861 /* Manual link training for Ivy Bridge A0 parts */
3862 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
3863 const struct intel_crtc_state *crtc_state)
3864 {
3865 struct drm_device *dev = crtc->base.dev;
3866 struct drm_i915_private *dev_priv = to_i915(dev);
3867 int pipe = crtc->pipe;
3868 i915_reg_t reg;
3869 u32 temp, i, j;
3870
3871 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3872 for train result */
3873 reg = FDI_RX_IMR(pipe);
3874 temp = I915_READ(reg);
3875 temp &= ~FDI_RX_SYMBOL_LOCK;
3876 temp &= ~FDI_RX_BIT_LOCK;
3877 I915_WRITE(reg, temp);
3878
3879 POSTING_READ(reg);
3880 udelay(150);
3881
3882 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3883 I915_READ(FDI_RX_IIR(pipe)));
3884
3885 /* Try each vswing and preemphasis setting twice before moving on */
3886 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3887 /* disable first in case we need to retry */
3888 reg = FDI_TX_CTL(pipe);
3889 temp = I915_READ(reg);
3890 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3891 temp &= ~FDI_TX_ENABLE;
3892 I915_WRITE(reg, temp);
3893
3894 reg = FDI_RX_CTL(pipe);
3895 temp = I915_READ(reg);
3896 temp &= ~FDI_LINK_TRAIN_AUTO;
3897 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3898 temp &= ~FDI_RX_ENABLE;
3899 I915_WRITE(reg, temp);
3900
3901 /* enable CPU FDI TX and PCH FDI RX */
3902 reg = FDI_TX_CTL(pipe);
3903 temp = I915_READ(reg);
3904 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3905 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3906 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3907 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3908 temp |= snb_b_fdi_train_param[j/2];
3909 temp |= FDI_COMPOSITE_SYNC;
3910 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3911
3912 I915_WRITE(FDI_RX_MISC(pipe),
3913 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3914
3915 reg = FDI_RX_CTL(pipe);
3916 temp = I915_READ(reg);
3917 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3918 temp |= FDI_COMPOSITE_SYNC;
3919 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3920
3921 POSTING_READ(reg);
3922 udelay(1); /* should be 0.5us */
3923
3924 for (i = 0; i < 4; i++) {
3925 reg = FDI_RX_IIR(pipe);
3926 temp = I915_READ(reg);
3927 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3928
3929 if (temp & FDI_RX_BIT_LOCK ||
3930 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3931 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3932 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3933 i);
3934 break;
3935 }
3936 udelay(1); /* should be 0.5us */
3937 }
3938 if (i == 4) {
3939 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3940 continue;
3941 }
3942
3943 /* Train 2 */
3944 reg = FDI_TX_CTL(pipe);
3945 temp = I915_READ(reg);
3946 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3947 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3948 I915_WRITE(reg, temp);
3949
3950 reg = FDI_RX_CTL(pipe);
3951 temp = I915_READ(reg);
3952 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3953 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3954 I915_WRITE(reg, temp);
3955
3956 POSTING_READ(reg);
3957 udelay(2); /* should be 1.5us */
3958
3959 for (i = 0; i < 4; i++) {
3960 reg = FDI_RX_IIR(pipe);
3961 temp = I915_READ(reg);
3962 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3963
3964 if (temp & FDI_RX_SYMBOL_LOCK ||
3965 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3966 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3967 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3968 i);
3969 goto train_done;
3970 }
3971 udelay(2); /* should be 1.5us */
3972 }
3973 if (i == 4)
3974 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3975 }
3976
3977 train_done:
3978 DRM_DEBUG_KMS("FDI train done.\n");
3979 }
3980
3981 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3982 {
3983 struct drm_device *dev = intel_crtc->base.dev;
3984 struct drm_i915_private *dev_priv = to_i915(dev);
3985 int pipe = intel_crtc->pipe;
3986 i915_reg_t reg;
3987 u32 temp;
3988
3989 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3990 reg = FDI_RX_CTL(pipe);
3991 temp = I915_READ(reg);
3992 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3993 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3994 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3995 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3996
3997 POSTING_READ(reg);
3998 udelay(200);
3999
4000 /* Switch from Rawclk to PCDclk */
4001 temp = I915_READ(reg);
4002 I915_WRITE(reg, temp | FDI_PCDCLK);
4003
4004 POSTING_READ(reg);
4005 udelay(200);
4006
4007 /* Enable CPU FDI TX PLL, always on for Ironlake */
4008 reg = FDI_TX_CTL(pipe);
4009 temp = I915_READ(reg);
4010 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4011 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4012
4013 POSTING_READ(reg);
4014 udelay(100);
4015 }
4016 }
4017
4018 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4019 {
4020 struct drm_device *dev = intel_crtc->base.dev;
4021 struct drm_i915_private *dev_priv = to_i915(dev);
4022 int pipe = intel_crtc->pipe;
4023 i915_reg_t reg;
4024 u32 temp;
4025
4026 /* Switch from PCDclk to Rawclk */
4027 reg = FDI_RX_CTL(pipe);
4028 temp = I915_READ(reg);
4029 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4030
4031 /* Disable CPU FDI TX PLL */
4032 reg = FDI_TX_CTL(pipe);
4033 temp = I915_READ(reg);
4034 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4035
4036 POSTING_READ(reg);
4037 udelay(100);
4038
4039 reg = FDI_RX_CTL(pipe);
4040 temp = I915_READ(reg);
4041 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4042
4043 /* Wait for the clocks to turn off. */
4044 POSTING_READ(reg);
4045 udelay(100);
4046 }
4047
4048 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4049 {
4050 struct drm_device *dev = crtc->dev;
4051 struct drm_i915_private *dev_priv = to_i915(dev);
4052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4053 int pipe = intel_crtc->pipe;
4054 i915_reg_t reg;
4055 u32 temp;
4056
4057 /* disable CPU FDI tx and PCH FDI rx */
4058 reg = FDI_TX_CTL(pipe);
4059 temp = I915_READ(reg);
4060 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4061 POSTING_READ(reg);
4062
4063 reg = FDI_RX_CTL(pipe);
4064 temp = I915_READ(reg);
4065 temp &= ~(0x7 << 16);
4066 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4067 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4068
4069 POSTING_READ(reg);
4070 udelay(100);
4071
4072 /* Ironlake workaround, disable clock pointer after downing FDI */
4073 if (HAS_PCH_IBX(dev_priv))
4074 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4075
4076 /* still set train pattern 1 */
4077 reg = FDI_TX_CTL(pipe);
4078 temp = I915_READ(reg);
4079 temp &= ~FDI_LINK_TRAIN_NONE;
4080 temp |= FDI_LINK_TRAIN_PATTERN_1;
4081 I915_WRITE(reg, temp);
4082
4083 reg = FDI_RX_CTL(pipe);
4084 temp = I915_READ(reg);
4085 if (HAS_PCH_CPT(dev_priv)) {
4086 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4087 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4088 } else {
4089 temp &= ~FDI_LINK_TRAIN_NONE;
4090 temp |= FDI_LINK_TRAIN_PATTERN_1;
4091 }
4092 /* BPC in FDI rx is consistent with that in PIPECONF */
4093 temp &= ~(0x07 << 16);
4094 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4095 I915_WRITE(reg, temp);
4096
4097 POSTING_READ(reg);
4098 udelay(100);
4099 }
4100
4101 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4102 {
4103 struct drm_crtc *crtc;
4104 bool cleanup_done;
4105
4106 drm_for_each_crtc(crtc, &dev_priv->drm) {
4107 struct drm_crtc_commit *commit;
4108 spin_lock(&crtc->commit_lock);
4109 commit = list_first_entry_or_null(&crtc->commit_list,
4110 struct drm_crtc_commit, commit_entry);
4111 cleanup_done = commit ?
4112 try_wait_for_completion(&commit->cleanup_done) : true;
4113 spin_unlock(&crtc->commit_lock);
4114
4115 if (cleanup_done)
4116 continue;
4117
4118 drm_crtc_wait_one_vblank(crtc);
4119
4120 return true;
4121 }
4122
4123 return false;
4124 }
4125
4126 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4127 {
4128 u32 temp;
4129
4130 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4131
4132 mutex_lock(&dev_priv->sb_lock);
4133
4134 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4135 temp |= SBI_SSCCTL_DISABLE;
4136 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4137
4138 mutex_unlock(&dev_priv->sb_lock);
4139 }
4140
4141 /* Program iCLKIP clock to the desired frequency */
4142 static void lpt_program_iclkip(struct intel_crtc *crtc)
4143 {
4144 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4145 int clock = crtc->config->base.adjusted_mode.crtc_clock;
4146 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4147 u32 temp;
4148
4149 lpt_disable_iclkip(dev_priv);
4150
4151 /* The iCLK virtual clock root frequency is in MHz,
4152 * but the adjusted_mode->crtc_clock in in KHz. To get the
4153 * divisors, it is necessary to divide one by another, so we
4154 * convert the virtual clock precision to KHz here for higher
4155 * precision.
4156 */
4157 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4158 u32 iclk_virtual_root_freq = 172800 * 1000;
4159 u32 iclk_pi_range = 64;
4160 u32 desired_divisor;
4161
4162 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4163 clock << auxdiv);
4164 divsel = (desired_divisor / iclk_pi_range) - 2;
4165 phaseinc = desired_divisor % iclk_pi_range;
4166
4167 /*
4168 * Near 20MHz is a corner case which is
4169 * out of range for the 7-bit divisor
4170 */
4171 if (divsel <= 0x7f)
4172 break;
4173 }
4174
4175 /* This should not happen with any sane values */
4176 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4177 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4178 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4179 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4180
4181 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4182 clock,
4183 auxdiv,
4184 divsel,
4185 phasedir,
4186 phaseinc);
4187
4188 mutex_lock(&dev_priv->sb_lock);
4189
4190 /* Program SSCDIVINTPHASE6 */
4191 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4192 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4193 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4194 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4195 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4196 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4197 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4198 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4199
4200 /* Program SSCAUXDIV */
4201 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4202 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4203 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4204 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4205
4206 /* Enable modulator and associated divider */
4207 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4208 temp &= ~SBI_SSCCTL_DISABLE;
4209 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4210
4211 mutex_unlock(&dev_priv->sb_lock);
4212
4213 /* Wait for initialization time */
4214 udelay(24);
4215
4216 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4217 }
4218
4219 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4220 {
4221 u32 divsel, phaseinc, auxdiv;
4222 u32 iclk_virtual_root_freq = 172800 * 1000;
4223 u32 iclk_pi_range = 64;
4224 u32 desired_divisor;
4225 u32 temp;
4226
4227 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4228 return 0;
4229
4230 mutex_lock(&dev_priv->sb_lock);
4231
4232 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4233 if (temp & SBI_SSCCTL_DISABLE) {
4234 mutex_unlock(&dev_priv->sb_lock);
4235 return 0;
4236 }
4237
4238 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4239 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4240 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4241 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4242 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4243
4244 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4245 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4246 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4247
4248 mutex_unlock(&dev_priv->sb_lock);
4249
4250 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4251
4252 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4253 desired_divisor << auxdiv);
4254 }
4255
4256 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4257 enum pipe pch_transcoder)
4258 {
4259 struct drm_device *dev = crtc->base.dev;
4260 struct drm_i915_private *dev_priv = to_i915(dev);
4261 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4262
4263 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4264 I915_READ(HTOTAL(cpu_transcoder)));
4265 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4266 I915_READ(HBLANK(cpu_transcoder)));
4267 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4268 I915_READ(HSYNC(cpu_transcoder)));
4269
4270 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4271 I915_READ(VTOTAL(cpu_transcoder)));
4272 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4273 I915_READ(VBLANK(cpu_transcoder)));
4274 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4275 I915_READ(VSYNC(cpu_transcoder)));
4276 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4277 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4278 }
4279
4280 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4281 {
4282 struct drm_i915_private *dev_priv = to_i915(dev);
4283 uint32_t temp;
4284
4285 temp = I915_READ(SOUTH_CHICKEN1);
4286 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4287 return;
4288
4289 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4290 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4291
4292 temp &= ~FDI_BC_BIFURCATION_SELECT;
4293 if (enable)
4294 temp |= FDI_BC_BIFURCATION_SELECT;
4295
4296 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4297 I915_WRITE(SOUTH_CHICKEN1, temp);
4298 POSTING_READ(SOUTH_CHICKEN1);
4299 }
4300
4301 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4302 {
4303 struct drm_device *dev = intel_crtc->base.dev;
4304
4305 switch (intel_crtc->pipe) {
4306 case PIPE_A:
4307 break;
4308 case PIPE_B:
4309 if (intel_crtc->config->fdi_lanes > 2)
4310 cpt_set_fdi_bc_bifurcation(dev, false);
4311 else
4312 cpt_set_fdi_bc_bifurcation(dev, true);
4313
4314 break;
4315 case PIPE_C:
4316 cpt_set_fdi_bc_bifurcation(dev, true);
4317
4318 break;
4319 default:
4320 BUG();
4321 }
4322 }
4323
4324 /* Return which DP Port should be selected for Transcoder DP control */
4325 static enum port
4326 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4327 {
4328 struct drm_device *dev = crtc->base.dev;
4329 struct intel_encoder *encoder;
4330
4331 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4332 if (encoder->type == INTEL_OUTPUT_DP ||
4333 encoder->type == INTEL_OUTPUT_EDP)
4334 return enc_to_dig_port(&encoder->base)->port;
4335 }
4336
4337 return -1;
4338 }
4339
4340 /*
4341 * Enable PCH resources required for PCH ports:
4342 * - PCH PLLs
4343 * - FDI training & RX/TX
4344 * - update transcoder timings
4345 * - DP transcoding bits
4346 * - transcoder
4347 */
4348 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4349 {
4350 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4351 struct drm_device *dev = crtc->base.dev;
4352 struct drm_i915_private *dev_priv = to_i915(dev);
4353 int pipe = crtc->pipe;
4354 u32 temp;
4355
4356 assert_pch_transcoder_disabled(dev_priv, pipe);
4357
4358 if (IS_IVYBRIDGE(dev_priv))
4359 ivybridge_update_fdi_bc_bifurcation(crtc);
4360
4361 /* Write the TU size bits before fdi link training, so that error
4362 * detection works. */
4363 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4364 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4365
4366 /* For PCH output, training FDI link */
4367 dev_priv->display.fdi_link_train(crtc, crtc_state);
4368
4369 /* We need to program the right clock selection before writing the pixel
4370 * mutliplier into the DPLL. */
4371 if (HAS_PCH_CPT(dev_priv)) {
4372 u32 sel;
4373
4374 temp = I915_READ(PCH_DPLL_SEL);
4375 temp |= TRANS_DPLL_ENABLE(pipe);
4376 sel = TRANS_DPLLB_SEL(pipe);
4377 if (crtc_state->shared_dpll ==
4378 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4379 temp |= sel;
4380 else
4381 temp &= ~sel;
4382 I915_WRITE(PCH_DPLL_SEL, temp);
4383 }
4384
4385 /* XXX: pch pll's can be enabled any time before we enable the PCH
4386 * transcoder, and we actually should do this to not upset any PCH
4387 * transcoder that already use the clock when we share it.
4388 *
4389 * Note that enable_shared_dpll tries to do the right thing, but
4390 * get_shared_dpll unconditionally resets the pll - we need that to have
4391 * the right LVDS enable sequence. */
4392 intel_enable_shared_dpll(crtc);
4393
4394 /* set transcoder timing, panel must allow it */
4395 assert_panel_unlocked(dev_priv, pipe);
4396 ironlake_pch_transcoder_set_timings(crtc, pipe);
4397
4398 intel_fdi_normal_train(crtc);
4399
4400 /* For PCH DP, enable TRANS_DP_CTL */
4401 if (HAS_PCH_CPT(dev_priv) &&
4402 intel_crtc_has_dp_encoder(crtc_state)) {
4403 const struct drm_display_mode *adjusted_mode =
4404 &crtc_state->base.adjusted_mode;
4405 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4406 i915_reg_t reg = TRANS_DP_CTL(pipe);
4407 temp = I915_READ(reg);
4408 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4409 TRANS_DP_SYNC_MASK |
4410 TRANS_DP_BPC_MASK);
4411 temp |= TRANS_DP_OUTPUT_ENABLE;
4412 temp |= bpc << 9; /* same format but at 11:9 */
4413
4414 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4415 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4416 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4417 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4418
4419 switch (intel_trans_dp_port_sel(crtc)) {
4420 case PORT_B:
4421 temp |= TRANS_DP_PORT_SEL_B;
4422 break;
4423 case PORT_C:
4424 temp |= TRANS_DP_PORT_SEL_C;
4425 break;
4426 case PORT_D:
4427 temp |= TRANS_DP_PORT_SEL_D;
4428 break;
4429 default:
4430 BUG();
4431 }
4432
4433 I915_WRITE(reg, temp);
4434 }
4435
4436 ironlake_enable_pch_transcoder(dev_priv, pipe);
4437 }
4438
4439 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4440 {
4441 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4442 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4443 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4444
4445 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4446
4447 lpt_program_iclkip(crtc);
4448
4449 /* Set transcoder timing. */
4450 ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4451
4452 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4453 }
4454
4455 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4456 {
4457 struct drm_i915_private *dev_priv = to_i915(dev);
4458 i915_reg_t dslreg = PIPEDSL(pipe);
4459 u32 temp;
4460
4461 temp = I915_READ(dslreg);
4462 udelay(500);
4463 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4464 if (wait_for(I915_READ(dslreg) != temp, 5))
4465 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4466 }
4467 }
4468
4469 static int
4470 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4471 unsigned int scaler_user, int *scaler_id,
4472 int src_w, int src_h, int dst_w, int dst_h)
4473 {
4474 struct intel_crtc_scaler_state *scaler_state =
4475 &crtc_state->scaler_state;
4476 struct intel_crtc *intel_crtc =
4477 to_intel_crtc(crtc_state->base.crtc);
4478 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4479 const struct drm_display_mode *adjusted_mode =
4480 &crtc_state->base.adjusted_mode;
4481 int need_scaling;
4482
4483 /*
4484 * Src coordinates are already rotated by 270 degrees for
4485 * the 90/270 degree plane rotation cases (to match the
4486 * GTT mapping), hence no need to account for rotation here.
4487 */
4488 need_scaling = src_w != dst_w || src_h != dst_h;
4489
4490 if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
4491 need_scaling = true;
4492
4493 /*
4494 * Scaling/fitting not supported in IF-ID mode in GEN9+
4495 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4496 * Once NV12 is enabled, handle it here while allocating scaler
4497 * for NV12.
4498 */
4499 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
4500 need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4501 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4502 return -EINVAL;
4503 }
4504
4505 /*
4506 * if plane is being disabled or scaler is no more required or force detach
4507 * - free scaler binded to this plane/crtc
4508 * - in order to do this, update crtc->scaler_usage
4509 *
4510 * Here scaler state in crtc_state is set free so that
4511 * scaler can be assigned to other user. Actual register
4512 * update to free the scaler is done in plane/panel-fit programming.
4513 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4514 */
4515 if (force_detach || !need_scaling) {
4516 if (*scaler_id >= 0) {
4517 scaler_state->scaler_users &= ~(1 << scaler_user);
4518 scaler_state->scalers[*scaler_id].in_use = 0;
4519
4520 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4521 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4522 intel_crtc->pipe, scaler_user, *scaler_id,
4523 scaler_state->scaler_users);
4524 *scaler_id = -1;
4525 }
4526 return 0;
4527 }
4528
4529 /* range checks */
4530 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4531 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4532
4533 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4534 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4535 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4536 "size is out of scaler range\n",
4537 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4538 return -EINVAL;
4539 }
4540
4541 /* mark this plane as a scaler user in crtc_state */
4542 scaler_state->scaler_users |= (1 << scaler_user);
4543 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4544 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4545 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4546 scaler_state->scaler_users);
4547
4548 return 0;
4549 }
4550
4551 /**
4552 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4553 *
4554 * @state: crtc's scaler state
4555 *
4556 * Return
4557 * 0 - scaler_usage updated successfully
4558 * error - requested scaling cannot be supported or other error condition
4559 */
4560 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4561 {
4562 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4563
4564 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4565 &state->scaler_state.scaler_id,
4566 state->pipe_src_w, state->pipe_src_h,
4567 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4568 }
4569
4570 /**
4571 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4572 *
4573 * @state: crtc's scaler state
4574 * @plane_state: atomic plane state to update
4575 *
4576 * Return
4577 * 0 - scaler_usage updated successfully
4578 * error - requested scaling cannot be supported or other error condition
4579 */
4580 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4581 struct intel_plane_state *plane_state)
4582 {
4583
4584 struct intel_plane *intel_plane =
4585 to_intel_plane(plane_state->base.plane);
4586 struct drm_framebuffer *fb = plane_state->base.fb;
4587 int ret;
4588
4589 bool force_detach = !fb || !plane_state->base.visible;
4590
4591 ret = skl_update_scaler(crtc_state, force_detach,
4592 drm_plane_index(&intel_plane->base),
4593 &plane_state->scaler_id,
4594 drm_rect_width(&plane_state->base.src) >> 16,
4595 drm_rect_height(&plane_state->base.src) >> 16,
4596 drm_rect_width(&plane_state->base.dst),
4597 drm_rect_height(&plane_state->base.dst));
4598
4599 if (ret || plane_state->scaler_id < 0)
4600 return ret;
4601
4602 /* check colorkey */
4603 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4604 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4605 intel_plane->base.base.id,
4606 intel_plane->base.name);
4607 return -EINVAL;
4608 }
4609
4610 /* Check src format */
4611 switch (fb->format->format) {
4612 case DRM_FORMAT_RGB565:
4613 case DRM_FORMAT_XBGR8888:
4614 case DRM_FORMAT_XRGB8888:
4615 case DRM_FORMAT_ABGR8888:
4616 case DRM_FORMAT_ARGB8888:
4617 case DRM_FORMAT_XRGB2101010:
4618 case DRM_FORMAT_XBGR2101010:
4619 case DRM_FORMAT_YUYV:
4620 case DRM_FORMAT_YVYU:
4621 case DRM_FORMAT_UYVY:
4622 case DRM_FORMAT_VYUY:
4623 break;
4624 default:
4625 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4626 intel_plane->base.base.id, intel_plane->base.name,
4627 fb->base.id, fb->format->format);
4628 return -EINVAL;
4629 }
4630
4631 return 0;
4632 }
4633
4634 static void skylake_scaler_disable(struct intel_crtc *crtc)
4635 {
4636 int i;
4637
4638 for (i = 0; i < crtc->num_scalers; i++)
4639 skl_detach_scaler(crtc, i);
4640 }
4641
4642 static void skylake_pfit_enable(struct intel_crtc *crtc)
4643 {
4644 struct drm_device *dev = crtc->base.dev;
4645 struct drm_i915_private *dev_priv = to_i915(dev);
4646 int pipe = crtc->pipe;
4647 struct intel_crtc_scaler_state *scaler_state =
4648 &crtc->config->scaler_state;
4649
4650 if (crtc->config->pch_pfit.enabled) {
4651 int id;
4652
4653 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4654 return;
4655
4656 id = scaler_state->scaler_id;
4657 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4658 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4659 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4660 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4661 }
4662 }
4663
4664 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4665 {
4666 struct drm_device *dev = crtc->base.dev;
4667 struct drm_i915_private *dev_priv = to_i915(dev);
4668 int pipe = crtc->pipe;
4669
4670 if (crtc->config->pch_pfit.enabled) {
4671 /* Force use of hard-coded filter coefficients
4672 * as some pre-programmed values are broken,
4673 * e.g. x201.
4674 */
4675 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4676 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4677 PF_PIPE_SEL_IVB(pipe));
4678 else
4679 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4680 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4681 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4682 }
4683 }
4684
4685 void hsw_enable_ips(struct intel_crtc *crtc)
4686 {
4687 struct drm_device *dev = crtc->base.dev;
4688 struct drm_i915_private *dev_priv = to_i915(dev);
4689
4690 if (!crtc->config->ips_enabled)
4691 return;
4692
4693 /*
4694 * We can only enable IPS after we enable a plane and wait for a vblank
4695 * This function is called from post_plane_update, which is run after
4696 * a vblank wait.
4697 */
4698
4699 assert_plane_enabled(dev_priv, crtc->plane);
4700 if (IS_BROADWELL(dev_priv)) {
4701 mutex_lock(&dev_priv->rps.hw_lock);
4702 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4703 mutex_unlock(&dev_priv->rps.hw_lock);
4704 /* Quoting Art Runyan: "its not safe to expect any particular
4705 * value in IPS_CTL bit 31 after enabling IPS through the
4706 * mailbox." Moreover, the mailbox may return a bogus state,
4707 * so we need to just enable it and continue on.
4708 */
4709 } else {
4710 I915_WRITE(IPS_CTL, IPS_ENABLE);
4711 /* The bit only becomes 1 in the next vblank, so this wait here
4712 * is essentially intel_wait_for_vblank. If we don't have this
4713 * and don't wait for vblanks until the end of crtc_enable, then
4714 * the HW state readout code will complain that the expected
4715 * IPS_CTL value is not the one we read. */
4716 if (intel_wait_for_register(dev_priv,
4717 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4718 50))
4719 DRM_ERROR("Timed out waiting for IPS enable\n");
4720 }
4721 }
4722
4723 void hsw_disable_ips(struct intel_crtc *crtc)
4724 {
4725 struct drm_device *dev = crtc->base.dev;
4726 struct drm_i915_private *dev_priv = to_i915(dev);
4727
4728 if (!crtc->config->ips_enabled)
4729 return;
4730
4731 assert_plane_enabled(dev_priv, crtc->plane);
4732 if (IS_BROADWELL(dev_priv)) {
4733 mutex_lock(&dev_priv->rps.hw_lock);
4734 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4735 mutex_unlock(&dev_priv->rps.hw_lock);
4736 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4737 if (intel_wait_for_register(dev_priv,
4738 IPS_CTL, IPS_ENABLE, 0,
4739 42))
4740 DRM_ERROR("Timed out waiting for IPS disable\n");
4741 } else {
4742 I915_WRITE(IPS_CTL, 0);
4743 POSTING_READ(IPS_CTL);
4744 }
4745
4746 /* We need to wait for a vblank before we can disable the plane. */
4747 intel_wait_for_vblank(dev_priv, crtc->pipe);
4748 }
4749
4750 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4751 {
4752 if (intel_crtc->overlay) {
4753 struct drm_device *dev = intel_crtc->base.dev;
4754
4755 mutex_lock(&dev->struct_mutex);
4756 (void) intel_overlay_switch_off(intel_crtc->overlay);
4757 mutex_unlock(&dev->struct_mutex);
4758 }
4759
4760 /* Let userspace switch the overlay on again. In most cases userspace
4761 * has to recompute where to put it anyway.
4762 */
4763 }
4764
4765 /**
4766 * intel_post_enable_primary - Perform operations after enabling primary plane
4767 * @crtc: the CRTC whose primary plane was just enabled
4768 *
4769 * Performs potentially sleeping operations that must be done after the primary
4770 * plane is enabled, such as updating FBC and IPS. Note that this may be
4771 * called due to an explicit primary plane update, or due to an implicit
4772 * re-enable that is caused when a sprite plane is updated to no longer
4773 * completely hide the primary plane.
4774 */
4775 static void
4776 intel_post_enable_primary(struct drm_crtc *crtc)
4777 {
4778 struct drm_device *dev = crtc->dev;
4779 struct drm_i915_private *dev_priv = to_i915(dev);
4780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4781 int pipe = intel_crtc->pipe;
4782
4783 /*
4784 * FIXME IPS should be fine as long as one plane is
4785 * enabled, but in practice it seems to have problems
4786 * when going from primary only to sprite only and vice
4787 * versa.
4788 */
4789 hsw_enable_ips(intel_crtc);
4790
4791 /*
4792 * Gen2 reports pipe underruns whenever all planes are disabled.
4793 * So don't enable underrun reporting before at least some planes
4794 * are enabled.
4795 * FIXME: Need to fix the logic to work when we turn off all planes
4796 * but leave the pipe running.
4797 */
4798 if (IS_GEN2(dev_priv))
4799 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4800
4801 /* Underruns don't always raise interrupts, so check manually. */
4802 intel_check_cpu_fifo_underruns(dev_priv);
4803 intel_check_pch_fifo_underruns(dev_priv);
4804 }
4805
4806 /* FIXME move all this to pre_plane_update() with proper state tracking */
4807 static void
4808 intel_pre_disable_primary(struct drm_crtc *crtc)
4809 {
4810 struct drm_device *dev = crtc->dev;
4811 struct drm_i915_private *dev_priv = to_i915(dev);
4812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4813 int pipe = intel_crtc->pipe;
4814
4815 /*
4816 * Gen2 reports pipe underruns whenever all planes are disabled.
4817 * So diasble underrun reporting before all the planes get disabled.
4818 * FIXME: Need to fix the logic to work when we turn off all planes
4819 * but leave the pipe running.
4820 */
4821 if (IS_GEN2(dev_priv))
4822 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4823
4824 /*
4825 * FIXME IPS should be fine as long as one plane is
4826 * enabled, but in practice it seems to have problems
4827 * when going from primary only to sprite only and vice
4828 * versa.
4829 */
4830 hsw_disable_ips(intel_crtc);
4831 }
4832
4833 /* FIXME get rid of this and use pre_plane_update */
4834 static void
4835 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4836 {
4837 struct drm_device *dev = crtc->dev;
4838 struct drm_i915_private *dev_priv = to_i915(dev);
4839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4840 int pipe = intel_crtc->pipe;
4841
4842 intel_pre_disable_primary(crtc);
4843
4844 /*
4845 * Vblank time updates from the shadow to live plane control register
4846 * are blocked if the memory self-refresh mode is active at that
4847 * moment. So to make sure the plane gets truly disabled, disable
4848 * first the self-refresh mode. The self-refresh enable bit in turn
4849 * will be checked/applied by the HW only at the next frame start
4850 * event which is after the vblank start event, so we need to have a
4851 * wait-for-vblank between disabling the plane and the pipe.
4852 */
4853 if (HAS_GMCH_DISPLAY(dev_priv) &&
4854 intel_set_memory_cxsr(dev_priv, false))
4855 intel_wait_for_vblank(dev_priv, pipe);
4856 }
4857
4858 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4859 {
4860 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4861 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4862 struct intel_crtc_state *pipe_config =
4863 to_intel_crtc_state(crtc->base.state);
4864 struct drm_plane *primary = crtc->base.primary;
4865 struct drm_plane_state *old_pri_state =
4866 drm_atomic_get_existing_plane_state(old_state, primary);
4867
4868 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
4869
4870 if (pipe_config->update_wm_post && pipe_config->base.active)
4871 intel_update_watermarks(crtc);
4872
4873 if (old_pri_state) {
4874 struct intel_plane_state *primary_state =
4875 to_intel_plane_state(primary->state);
4876 struct intel_plane_state *old_primary_state =
4877 to_intel_plane_state(old_pri_state);
4878
4879 intel_fbc_post_update(crtc);
4880
4881 if (primary_state->base.visible &&
4882 (needs_modeset(&pipe_config->base) ||
4883 !old_primary_state->base.visible))
4884 intel_post_enable_primary(&crtc->base);
4885 }
4886 }
4887
4888 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
4889 struct intel_crtc_state *pipe_config)
4890 {
4891 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4892 struct drm_device *dev = crtc->base.dev;
4893 struct drm_i915_private *dev_priv = to_i915(dev);
4894 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4895 struct drm_plane *primary = crtc->base.primary;
4896 struct drm_plane_state *old_pri_state =
4897 drm_atomic_get_existing_plane_state(old_state, primary);
4898 bool modeset = needs_modeset(&pipe_config->base);
4899 struct intel_atomic_state *old_intel_state =
4900 to_intel_atomic_state(old_state);
4901
4902 if (old_pri_state) {
4903 struct intel_plane_state *primary_state =
4904 to_intel_plane_state(primary->state);
4905 struct intel_plane_state *old_primary_state =
4906 to_intel_plane_state(old_pri_state);
4907
4908 intel_fbc_pre_update(crtc, pipe_config, primary_state);
4909
4910 if (old_primary_state->base.visible &&
4911 (modeset || !primary_state->base.visible))
4912 intel_pre_disable_primary(&crtc->base);
4913 }
4914
4915 /*
4916 * Vblank time updates from the shadow to live plane control register
4917 * are blocked if the memory self-refresh mode is active at that
4918 * moment. So to make sure the plane gets truly disabled, disable
4919 * first the self-refresh mode. The self-refresh enable bit in turn
4920 * will be checked/applied by the HW only at the next frame start
4921 * event which is after the vblank start event, so we need to have a
4922 * wait-for-vblank between disabling the plane and the pipe.
4923 */
4924 if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
4925 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
4926 intel_wait_for_vblank(dev_priv, crtc->pipe);
4927
4928 /*
4929 * IVB workaround: must disable low power watermarks for at least
4930 * one frame before enabling scaling. LP watermarks can be re-enabled
4931 * when scaling is disabled.
4932 *
4933 * WaCxSRDisabledForSpriteScaling:ivb
4934 */
4935 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
4936 intel_wait_for_vblank(dev_priv, crtc->pipe);
4937
4938 /*
4939 * If we're doing a modeset, we're done. No need to do any pre-vblank
4940 * watermark programming here.
4941 */
4942 if (needs_modeset(&pipe_config->base))
4943 return;
4944
4945 /*
4946 * For platforms that support atomic watermarks, program the
4947 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4948 * will be the intermediate values that are safe for both pre- and
4949 * post- vblank; when vblank happens, the 'active' values will be set
4950 * to the final 'target' values and we'll do this again to get the
4951 * optimal watermarks. For gen9+ platforms, the values we program here
4952 * will be the final target values which will get automatically latched
4953 * at vblank time; no further programming will be necessary.
4954 *
4955 * If a platform hasn't been transitioned to atomic watermarks yet,
4956 * we'll continue to update watermarks the old way, if flags tell
4957 * us to.
4958 */
4959 if (dev_priv->display.initial_watermarks != NULL)
4960 dev_priv->display.initial_watermarks(old_intel_state,
4961 pipe_config);
4962 else if (pipe_config->update_wm_pre)
4963 intel_update_watermarks(crtc);
4964 }
4965
4966 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4967 {
4968 struct drm_device *dev = crtc->dev;
4969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4970 struct drm_plane *p;
4971 int pipe = intel_crtc->pipe;
4972
4973 intel_crtc_dpms_overlay_disable(intel_crtc);
4974
4975 drm_for_each_plane_mask(p, dev, plane_mask)
4976 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
4977
4978 /*
4979 * FIXME: Once we grow proper nuclear flip support out of this we need
4980 * to compute the mask of flip planes precisely. For the time being
4981 * consider this a flip to a NULL plane.
4982 */
4983 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
4984 }
4985
4986 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
4987 struct intel_crtc_state *crtc_state,
4988 struct drm_atomic_state *old_state)
4989 {
4990 struct drm_connector_state *conn_state;
4991 struct drm_connector *conn;
4992 int i;
4993
4994 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
4995 struct intel_encoder *encoder =
4996 to_intel_encoder(conn_state->best_encoder);
4997
4998 if (conn_state->crtc != crtc)
4999 continue;
5000
5001 if (encoder->pre_pll_enable)
5002 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5003 }
5004 }
5005
5006 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5007 struct intel_crtc_state *crtc_state,
5008 struct drm_atomic_state *old_state)
5009 {
5010 struct drm_connector_state *conn_state;
5011 struct drm_connector *conn;
5012 int i;
5013
5014 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5015 struct intel_encoder *encoder =
5016 to_intel_encoder(conn_state->best_encoder);
5017
5018 if (conn_state->crtc != crtc)
5019 continue;
5020
5021 if (encoder->pre_enable)
5022 encoder->pre_enable(encoder, crtc_state, conn_state);
5023 }
5024 }
5025
5026 static void intel_encoders_enable(struct drm_crtc *crtc,
5027 struct intel_crtc_state *crtc_state,
5028 struct drm_atomic_state *old_state)
5029 {
5030 struct drm_connector_state *conn_state;
5031 struct drm_connector *conn;
5032 int i;
5033
5034 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5035 struct intel_encoder *encoder =
5036 to_intel_encoder(conn_state->best_encoder);
5037
5038 if (conn_state->crtc != crtc)
5039 continue;
5040
5041 encoder->enable(encoder, crtc_state, conn_state);
5042 intel_opregion_notify_encoder(encoder, true);
5043 }
5044 }
5045
5046 static void intel_encoders_disable(struct drm_crtc *crtc,
5047 struct intel_crtc_state *old_crtc_state,
5048 struct drm_atomic_state *old_state)
5049 {
5050 struct drm_connector_state *old_conn_state;
5051 struct drm_connector *conn;
5052 int i;
5053
5054 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5055 struct intel_encoder *encoder =
5056 to_intel_encoder(old_conn_state->best_encoder);
5057
5058 if (old_conn_state->crtc != crtc)
5059 continue;
5060
5061 intel_opregion_notify_encoder(encoder, false);
5062 encoder->disable(encoder, old_crtc_state, old_conn_state);
5063 }
5064 }
5065
5066 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5067 struct intel_crtc_state *old_crtc_state,
5068 struct drm_atomic_state *old_state)
5069 {
5070 struct drm_connector_state *old_conn_state;
5071 struct drm_connector *conn;
5072 int i;
5073
5074 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5075 struct intel_encoder *encoder =
5076 to_intel_encoder(old_conn_state->best_encoder);
5077
5078 if (old_conn_state->crtc != crtc)
5079 continue;
5080
5081 if (encoder->post_disable)
5082 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5083 }
5084 }
5085
5086 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5087 struct intel_crtc_state *old_crtc_state,
5088 struct drm_atomic_state *old_state)
5089 {
5090 struct drm_connector_state *old_conn_state;
5091 struct drm_connector *conn;
5092 int i;
5093
5094 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5095 struct intel_encoder *encoder =
5096 to_intel_encoder(old_conn_state->best_encoder);
5097
5098 if (old_conn_state->crtc != crtc)
5099 continue;
5100
5101 if (encoder->post_pll_disable)
5102 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5103 }
5104 }
5105
5106 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5107 struct drm_atomic_state *old_state)
5108 {
5109 struct drm_crtc *crtc = pipe_config->base.crtc;
5110 struct drm_device *dev = crtc->dev;
5111 struct drm_i915_private *dev_priv = to_i915(dev);
5112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5113 int pipe = intel_crtc->pipe;
5114 struct intel_atomic_state *old_intel_state =
5115 to_intel_atomic_state(old_state);
5116
5117 if (WARN_ON(intel_crtc->active))
5118 return;
5119
5120 /*
5121 * Sometimes spurious CPU pipe underruns happen during FDI
5122 * training, at least with VGA+HDMI cloning. Suppress them.
5123 *
5124 * On ILK we get an occasional spurious CPU pipe underruns
5125 * between eDP port A enable and vdd enable. Also PCH port
5126 * enable seems to result in the occasional CPU pipe underrun.
5127 *
5128 * Spurious PCH underruns also occur during PCH enabling.
5129 */
5130 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5131 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5132 if (intel_crtc->config->has_pch_encoder)
5133 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5134
5135 if (intel_crtc->config->has_pch_encoder)
5136 intel_prepare_shared_dpll(intel_crtc);
5137
5138 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5139 intel_dp_set_m_n(intel_crtc, M1_N1);
5140
5141 intel_set_pipe_timings(intel_crtc);
5142 intel_set_pipe_src_size(intel_crtc);
5143
5144 if (intel_crtc->config->has_pch_encoder) {
5145 intel_cpu_transcoder_set_m_n(intel_crtc,
5146 &intel_crtc->config->fdi_m_n, NULL);
5147 }
5148
5149 ironlake_set_pipeconf(crtc);
5150
5151 intel_crtc->active = true;
5152
5153 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5154
5155 if (intel_crtc->config->has_pch_encoder) {
5156 /* Note: FDI PLL enabling _must_ be done before we enable the
5157 * cpu pipes, hence this is separate from all the other fdi/pch
5158 * enabling. */
5159 ironlake_fdi_pll_enable(intel_crtc);
5160 } else {
5161 assert_fdi_tx_disabled(dev_priv, pipe);
5162 assert_fdi_rx_disabled(dev_priv, pipe);
5163 }
5164
5165 ironlake_pfit_enable(intel_crtc);
5166
5167 /*
5168 * On ILK+ LUT must be loaded before the pipe is running but with
5169 * clocks enabled
5170 */
5171 intel_color_load_luts(&pipe_config->base);
5172
5173 if (dev_priv->display.initial_watermarks != NULL)
5174 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5175 intel_enable_pipe(intel_crtc);
5176
5177 if (intel_crtc->config->has_pch_encoder)
5178 ironlake_pch_enable(pipe_config);
5179
5180 assert_vblank_disabled(crtc);
5181 drm_crtc_vblank_on(crtc);
5182
5183 intel_encoders_enable(crtc, pipe_config, old_state);
5184
5185 if (HAS_PCH_CPT(dev_priv))
5186 cpt_verify_modeset(dev, intel_crtc->pipe);
5187
5188 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5189 if (intel_crtc->config->has_pch_encoder)
5190 intel_wait_for_vblank(dev_priv, pipe);
5191 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5192 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5193 }
5194
5195 /* IPS only exists on ULT machines and is tied to pipe A. */
5196 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5197 {
5198 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5199 }
5200
5201 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5202 struct drm_atomic_state *old_state)
5203 {
5204 struct drm_crtc *crtc = pipe_config->base.crtc;
5205 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5207 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5208 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5209 struct intel_atomic_state *old_intel_state =
5210 to_intel_atomic_state(old_state);
5211
5212 if (WARN_ON(intel_crtc->active))
5213 return;
5214
5215 if (intel_crtc->config->has_pch_encoder)
5216 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
5217
5218 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5219
5220 if (intel_crtc->config->shared_dpll)
5221 intel_enable_shared_dpll(intel_crtc);
5222
5223 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5224 intel_dp_set_m_n(intel_crtc, M1_N1);
5225
5226 if (!transcoder_is_dsi(cpu_transcoder))
5227 intel_set_pipe_timings(intel_crtc);
5228
5229 intel_set_pipe_src_size(intel_crtc);
5230
5231 if (cpu_transcoder != TRANSCODER_EDP &&
5232 !transcoder_is_dsi(cpu_transcoder)) {
5233 I915_WRITE(PIPE_MULT(cpu_transcoder),
5234 intel_crtc->config->pixel_multiplier - 1);
5235 }
5236
5237 if (intel_crtc->config->has_pch_encoder) {
5238 intel_cpu_transcoder_set_m_n(intel_crtc,
5239 &intel_crtc->config->fdi_m_n, NULL);
5240 }
5241
5242 if (!transcoder_is_dsi(cpu_transcoder))
5243 haswell_set_pipeconf(crtc);
5244
5245 haswell_set_pipemisc(crtc);
5246
5247 intel_color_set_csc(&pipe_config->base);
5248
5249 intel_crtc->active = true;
5250
5251 if (intel_crtc->config->has_pch_encoder)
5252 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5253 else
5254 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5255
5256 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5257
5258 if (intel_crtc->config->has_pch_encoder)
5259 dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
5260
5261 if (!transcoder_is_dsi(cpu_transcoder))
5262 intel_ddi_enable_pipe_clock(pipe_config);
5263
5264 if (INTEL_GEN(dev_priv) >= 9)
5265 skylake_pfit_enable(intel_crtc);
5266 else
5267 ironlake_pfit_enable(intel_crtc);
5268
5269 /*
5270 * On ILK+ LUT must be loaded before the pipe is running but with
5271 * clocks enabled
5272 */
5273 intel_color_load_luts(&pipe_config->base);
5274
5275 intel_ddi_set_pipe_settings(pipe_config);
5276 if (!transcoder_is_dsi(cpu_transcoder))
5277 intel_ddi_enable_transcoder_func(pipe_config);
5278
5279 if (dev_priv->display.initial_watermarks != NULL)
5280 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5281
5282 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5283 if (!transcoder_is_dsi(cpu_transcoder))
5284 intel_enable_pipe(intel_crtc);
5285
5286 if (intel_crtc->config->has_pch_encoder)
5287 lpt_pch_enable(pipe_config);
5288
5289 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5290 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5291
5292 assert_vblank_disabled(crtc);
5293 drm_crtc_vblank_on(crtc);
5294
5295 intel_encoders_enable(crtc, pipe_config, old_state);
5296
5297 if (intel_crtc->config->has_pch_encoder) {
5298 intel_wait_for_vblank(dev_priv, pipe);
5299 intel_wait_for_vblank(dev_priv, pipe);
5300 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5301 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5302 }
5303
5304 /* If we change the relative order between pipe/planes enabling, we need
5305 * to change the workaround. */
5306 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5307 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5308 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5309 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5310 }
5311 }
5312
5313 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5314 {
5315 struct drm_device *dev = crtc->base.dev;
5316 struct drm_i915_private *dev_priv = to_i915(dev);
5317 int pipe = crtc->pipe;
5318
5319 /* To avoid upsetting the power well on haswell only disable the pfit if
5320 * it's in use. The hw state code will make sure we get this right. */
5321 if (force || crtc->config->pch_pfit.enabled) {
5322 I915_WRITE(PF_CTL(pipe), 0);
5323 I915_WRITE(PF_WIN_POS(pipe), 0);
5324 I915_WRITE(PF_WIN_SZ(pipe), 0);
5325 }
5326 }
5327
5328 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5329 struct drm_atomic_state *old_state)
5330 {
5331 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5332 struct drm_device *dev = crtc->dev;
5333 struct drm_i915_private *dev_priv = to_i915(dev);
5334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5335 int pipe = intel_crtc->pipe;
5336
5337 /*
5338 * Sometimes spurious CPU pipe underruns happen when the
5339 * pipe is already disabled, but FDI RX/TX is still enabled.
5340 * Happens at least with VGA+HDMI cloning. Suppress them.
5341 */
5342 if (intel_crtc->config->has_pch_encoder) {
5343 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5344 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5345 }
5346
5347 intel_encoders_disable(crtc, old_crtc_state, old_state);
5348
5349 drm_crtc_vblank_off(crtc);
5350 assert_vblank_disabled(crtc);
5351
5352 intel_disable_pipe(intel_crtc);
5353
5354 ironlake_pfit_disable(intel_crtc, false);
5355
5356 if (intel_crtc->config->has_pch_encoder)
5357 ironlake_fdi_disable(crtc);
5358
5359 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5360
5361 if (intel_crtc->config->has_pch_encoder) {
5362 ironlake_disable_pch_transcoder(dev_priv, pipe);
5363
5364 if (HAS_PCH_CPT(dev_priv)) {
5365 i915_reg_t reg;
5366 u32 temp;
5367
5368 /* disable TRANS_DP_CTL */
5369 reg = TRANS_DP_CTL(pipe);
5370 temp = I915_READ(reg);
5371 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5372 TRANS_DP_PORT_SEL_MASK);
5373 temp |= TRANS_DP_PORT_SEL_NONE;
5374 I915_WRITE(reg, temp);
5375
5376 /* disable DPLL_SEL */
5377 temp = I915_READ(PCH_DPLL_SEL);
5378 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5379 I915_WRITE(PCH_DPLL_SEL, temp);
5380 }
5381
5382 ironlake_fdi_pll_disable(intel_crtc);
5383 }
5384
5385 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5386 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5387 }
5388
5389 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5390 struct drm_atomic_state *old_state)
5391 {
5392 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5393 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5394 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5395 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5396
5397 if (intel_crtc->config->has_pch_encoder)
5398 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
5399
5400 intel_encoders_disable(crtc, old_crtc_state, old_state);
5401
5402 drm_crtc_vblank_off(crtc);
5403 assert_vblank_disabled(crtc);
5404
5405 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5406 if (!transcoder_is_dsi(cpu_transcoder))
5407 intel_disable_pipe(intel_crtc);
5408
5409 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5410 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5411
5412 if (!transcoder_is_dsi(cpu_transcoder))
5413 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5414
5415 if (INTEL_GEN(dev_priv) >= 9)
5416 skylake_scaler_disable(intel_crtc);
5417 else
5418 ironlake_pfit_disable(intel_crtc, false);
5419
5420 if (!transcoder_is_dsi(cpu_transcoder))
5421 intel_ddi_disable_pipe_clock(intel_crtc->config);
5422
5423 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5424
5425 if (old_crtc_state->has_pch_encoder)
5426 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5427 }
5428
5429 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5430 {
5431 struct drm_device *dev = crtc->base.dev;
5432 struct drm_i915_private *dev_priv = to_i915(dev);
5433 struct intel_crtc_state *pipe_config = crtc->config;
5434
5435 if (!pipe_config->gmch_pfit.control)
5436 return;
5437
5438 /*
5439 * The panel fitter should only be adjusted whilst the pipe is disabled,
5440 * according to register description and PRM.
5441 */
5442 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5443 assert_pipe_disabled(dev_priv, crtc->pipe);
5444
5445 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5446 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5447
5448 /* Border color in case we don't scale up to the full screen. Black by
5449 * default, change to something else for debugging. */
5450 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5451 }
5452
5453 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5454 {
5455 switch (port) {
5456 case PORT_A:
5457 return POWER_DOMAIN_PORT_DDI_A_LANES;
5458 case PORT_B:
5459 return POWER_DOMAIN_PORT_DDI_B_LANES;
5460 case PORT_C:
5461 return POWER_DOMAIN_PORT_DDI_C_LANES;
5462 case PORT_D:
5463 return POWER_DOMAIN_PORT_DDI_D_LANES;
5464 case PORT_E:
5465 return POWER_DOMAIN_PORT_DDI_E_LANES;
5466 default:
5467 MISSING_CASE(port);
5468 return POWER_DOMAIN_PORT_OTHER;
5469 }
5470 }
5471
5472 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5473 struct intel_crtc_state *crtc_state)
5474 {
5475 struct drm_device *dev = crtc->dev;
5476 struct drm_i915_private *dev_priv = to_i915(dev);
5477 struct drm_encoder *encoder;
5478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5479 enum pipe pipe = intel_crtc->pipe;
5480 u64 mask;
5481 enum transcoder transcoder = crtc_state->cpu_transcoder;
5482
5483 if (!crtc_state->base.active)
5484 return 0;
5485
5486 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5487 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5488 if (crtc_state->pch_pfit.enabled ||
5489 crtc_state->pch_pfit.force_thru)
5490 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5491
5492 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5493 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5494
5495 mask |= BIT_ULL(intel_encoder->power_domain);
5496 }
5497
5498 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5499 mask |= BIT(POWER_DOMAIN_AUDIO);
5500
5501 if (crtc_state->shared_dpll)
5502 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5503
5504 return mask;
5505 }
5506
5507 static u64
5508 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5509 struct intel_crtc_state *crtc_state)
5510 {
5511 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5513 enum intel_display_power_domain domain;
5514 u64 domains, new_domains, old_domains;
5515
5516 old_domains = intel_crtc->enabled_power_domains;
5517 intel_crtc->enabled_power_domains = new_domains =
5518 get_crtc_power_domains(crtc, crtc_state);
5519
5520 domains = new_domains & ~old_domains;
5521
5522 for_each_power_domain(domain, domains)
5523 intel_display_power_get(dev_priv, domain);
5524
5525 return old_domains & ~new_domains;
5526 }
5527
5528 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5529 u64 domains)
5530 {
5531 enum intel_display_power_domain domain;
5532
5533 for_each_power_domain(domain, domains)
5534 intel_display_power_put(dev_priv, domain);
5535 }
5536
5537 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5538 struct drm_atomic_state *old_state)
5539 {
5540 struct intel_atomic_state *old_intel_state =
5541 to_intel_atomic_state(old_state);
5542 struct drm_crtc *crtc = pipe_config->base.crtc;
5543 struct drm_device *dev = crtc->dev;
5544 struct drm_i915_private *dev_priv = to_i915(dev);
5545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5546 int pipe = intel_crtc->pipe;
5547
5548 if (WARN_ON(intel_crtc->active))
5549 return;
5550
5551 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5552 intel_dp_set_m_n(intel_crtc, M1_N1);
5553
5554 intel_set_pipe_timings(intel_crtc);
5555 intel_set_pipe_src_size(intel_crtc);
5556
5557 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5558 struct drm_i915_private *dev_priv = to_i915(dev);
5559
5560 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5561 I915_WRITE(CHV_CANVAS(pipe), 0);
5562 }
5563
5564 i9xx_set_pipeconf(intel_crtc);
5565
5566 intel_crtc->active = true;
5567
5568 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5569
5570 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5571
5572 if (IS_CHERRYVIEW(dev_priv)) {
5573 chv_prepare_pll(intel_crtc, intel_crtc->config);
5574 chv_enable_pll(intel_crtc, intel_crtc->config);
5575 } else {
5576 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5577 vlv_enable_pll(intel_crtc, intel_crtc->config);
5578 }
5579
5580 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5581
5582 i9xx_pfit_enable(intel_crtc);
5583
5584 intel_color_load_luts(&pipe_config->base);
5585
5586 dev_priv->display.initial_watermarks(old_intel_state,
5587 pipe_config);
5588 intel_enable_pipe(intel_crtc);
5589
5590 assert_vblank_disabled(crtc);
5591 drm_crtc_vblank_on(crtc);
5592
5593 intel_encoders_enable(crtc, pipe_config, old_state);
5594 }
5595
5596 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5597 {
5598 struct drm_device *dev = crtc->base.dev;
5599 struct drm_i915_private *dev_priv = to_i915(dev);
5600
5601 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5602 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5603 }
5604
5605 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5606 struct drm_atomic_state *old_state)
5607 {
5608 struct intel_atomic_state *old_intel_state =
5609 to_intel_atomic_state(old_state);
5610 struct drm_crtc *crtc = pipe_config->base.crtc;
5611 struct drm_device *dev = crtc->dev;
5612 struct drm_i915_private *dev_priv = to_i915(dev);
5613 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5614 enum pipe pipe = intel_crtc->pipe;
5615
5616 if (WARN_ON(intel_crtc->active))
5617 return;
5618
5619 i9xx_set_pll_dividers(intel_crtc);
5620
5621 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5622 intel_dp_set_m_n(intel_crtc, M1_N1);
5623
5624 intel_set_pipe_timings(intel_crtc);
5625 intel_set_pipe_src_size(intel_crtc);
5626
5627 i9xx_set_pipeconf(intel_crtc);
5628
5629 intel_crtc->active = true;
5630
5631 if (!IS_GEN2(dev_priv))
5632 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5633
5634 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5635
5636 i9xx_enable_pll(intel_crtc);
5637
5638 i9xx_pfit_enable(intel_crtc);
5639
5640 intel_color_load_luts(&pipe_config->base);
5641
5642 if (dev_priv->display.initial_watermarks != NULL)
5643 dev_priv->display.initial_watermarks(old_intel_state,
5644 intel_crtc->config);
5645 else
5646 intel_update_watermarks(intel_crtc);
5647 intel_enable_pipe(intel_crtc);
5648
5649 assert_vblank_disabled(crtc);
5650 drm_crtc_vblank_on(crtc);
5651
5652 intel_encoders_enable(crtc, pipe_config, old_state);
5653 }
5654
5655 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5656 {
5657 struct drm_device *dev = crtc->base.dev;
5658 struct drm_i915_private *dev_priv = to_i915(dev);
5659
5660 if (!crtc->config->gmch_pfit.control)
5661 return;
5662
5663 assert_pipe_disabled(dev_priv, crtc->pipe);
5664
5665 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5666 I915_READ(PFIT_CONTROL));
5667 I915_WRITE(PFIT_CONTROL, 0);
5668 }
5669
5670 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5671 struct drm_atomic_state *old_state)
5672 {
5673 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5674 struct drm_device *dev = crtc->dev;
5675 struct drm_i915_private *dev_priv = to_i915(dev);
5676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5677 int pipe = intel_crtc->pipe;
5678
5679 /*
5680 * On gen2 planes are double buffered but the pipe isn't, so we must
5681 * wait for planes to fully turn off before disabling the pipe.
5682 */
5683 if (IS_GEN2(dev_priv))
5684 intel_wait_for_vblank(dev_priv, pipe);
5685
5686 intel_encoders_disable(crtc, old_crtc_state, old_state);
5687
5688 drm_crtc_vblank_off(crtc);
5689 assert_vblank_disabled(crtc);
5690
5691 intel_disable_pipe(intel_crtc);
5692
5693 i9xx_pfit_disable(intel_crtc);
5694
5695 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5696
5697 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5698 if (IS_CHERRYVIEW(dev_priv))
5699 chv_disable_pll(dev_priv, pipe);
5700 else if (IS_VALLEYVIEW(dev_priv))
5701 vlv_disable_pll(dev_priv, pipe);
5702 else
5703 i9xx_disable_pll(intel_crtc);
5704 }
5705
5706 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5707
5708 if (!IS_GEN2(dev_priv))
5709 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5710
5711 if (!dev_priv->display.initial_watermarks)
5712 intel_update_watermarks(intel_crtc);
5713
5714 /* clock the pipe down to 640x480@60 to potentially save power */
5715 if (IS_I830(dev_priv))
5716 i830_enable_pipe(dev_priv, pipe);
5717 }
5718
5719 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
5720 struct drm_modeset_acquire_ctx *ctx)
5721 {
5722 struct intel_encoder *encoder;
5723 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5724 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5725 enum intel_display_power_domain domain;
5726 u64 domains;
5727 struct drm_atomic_state *state;
5728 struct intel_crtc_state *crtc_state;
5729 int ret;
5730
5731 if (!intel_crtc->active)
5732 return;
5733
5734 if (crtc->primary->state->visible) {
5735 intel_pre_disable_primary_noatomic(crtc);
5736
5737 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5738 crtc->primary->state->visible = false;
5739 }
5740
5741 state = drm_atomic_state_alloc(crtc->dev);
5742 if (!state) {
5743 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5744 crtc->base.id, crtc->name);
5745 return;
5746 }
5747
5748 state->acquire_ctx = ctx;
5749
5750 /* Everything's already locked, -EDEADLK can't happen. */
5751 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5752 ret = drm_atomic_add_affected_connectors(state, crtc);
5753
5754 WARN_ON(IS_ERR(crtc_state) || ret);
5755
5756 dev_priv->display.crtc_disable(crtc_state, state);
5757
5758 drm_atomic_state_put(state);
5759
5760 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5761 crtc->base.id, crtc->name);
5762
5763 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5764 crtc->state->active = false;
5765 intel_crtc->active = false;
5766 crtc->enabled = false;
5767 crtc->state->connector_mask = 0;
5768 crtc->state->encoder_mask = 0;
5769
5770 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5771 encoder->base.crtc = NULL;
5772
5773 intel_fbc_disable(intel_crtc);
5774 intel_update_watermarks(intel_crtc);
5775 intel_disable_shared_dpll(intel_crtc);
5776
5777 domains = intel_crtc->enabled_power_domains;
5778 for_each_power_domain(domain, domains)
5779 intel_display_power_put(dev_priv, domain);
5780 intel_crtc->enabled_power_domains = 0;
5781
5782 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5783 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
5784 }
5785
5786 /*
5787 * turn all crtc's off, but do not adjust state
5788 * This has to be paired with a call to intel_modeset_setup_hw_state.
5789 */
5790 int intel_display_suspend(struct drm_device *dev)
5791 {
5792 struct drm_i915_private *dev_priv = to_i915(dev);
5793 struct drm_atomic_state *state;
5794 int ret;
5795
5796 state = drm_atomic_helper_suspend(dev);
5797 ret = PTR_ERR_OR_ZERO(state);
5798 if (ret)
5799 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5800 else
5801 dev_priv->modeset_restore_state = state;
5802 return ret;
5803 }
5804
5805 void intel_encoder_destroy(struct drm_encoder *encoder)
5806 {
5807 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5808
5809 drm_encoder_cleanup(encoder);
5810 kfree(intel_encoder);
5811 }
5812
5813 /* Cross check the actual hw state with our own modeset state tracking (and it's
5814 * internal consistency). */
5815 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
5816 struct drm_connector_state *conn_state)
5817 {
5818 struct intel_connector *connector = to_intel_connector(conn_state->connector);
5819
5820 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5821 connector->base.base.id,
5822 connector->base.name);
5823
5824 if (connector->get_hw_state(connector)) {
5825 struct intel_encoder *encoder = connector->encoder;
5826
5827 I915_STATE_WARN(!crtc_state,
5828 "connector enabled without attached crtc\n");
5829
5830 if (!crtc_state)
5831 return;
5832
5833 I915_STATE_WARN(!crtc_state->active,
5834 "connector is active, but attached crtc isn't\n");
5835
5836 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
5837 return;
5838
5839 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
5840 "atomic encoder doesn't match attached encoder\n");
5841
5842 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
5843 "attached encoder crtc differs from connector crtc\n");
5844 } else {
5845 I915_STATE_WARN(crtc_state && crtc_state->active,
5846 "attached crtc is active, but connector isn't\n");
5847 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
5848 "best encoder set without crtc!\n");
5849 }
5850 }
5851
5852 int intel_connector_init(struct intel_connector *connector)
5853 {
5854 struct intel_digital_connector_state *conn_state;
5855
5856 /*
5857 * Allocate enough memory to hold intel_digital_connector_state,
5858 * This might be a few bytes too many, but for connectors that don't
5859 * need it we'll free the state and allocate a smaller one on the first
5860 * succesful commit anyway.
5861 */
5862 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
5863 if (!conn_state)
5864 return -ENOMEM;
5865
5866 __drm_atomic_helper_connector_reset(&connector->base,
5867 &conn_state->base);
5868
5869 return 0;
5870 }
5871
5872 struct intel_connector *intel_connector_alloc(void)
5873 {
5874 struct intel_connector *connector;
5875
5876 connector = kzalloc(sizeof *connector, GFP_KERNEL);
5877 if (!connector)
5878 return NULL;
5879
5880 if (intel_connector_init(connector) < 0) {
5881 kfree(connector);
5882 return NULL;
5883 }
5884
5885 return connector;
5886 }
5887
5888 /* Simple connector->get_hw_state implementation for encoders that support only
5889 * one connector and no cloning and hence the encoder state determines the state
5890 * of the connector. */
5891 bool intel_connector_get_hw_state(struct intel_connector *connector)
5892 {
5893 enum pipe pipe = 0;
5894 struct intel_encoder *encoder = connector->encoder;
5895
5896 return encoder->get_hw_state(encoder, &pipe);
5897 }
5898
5899 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
5900 {
5901 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
5902 return crtc_state->fdi_lanes;
5903
5904 return 0;
5905 }
5906
5907 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5908 struct intel_crtc_state *pipe_config)
5909 {
5910 struct drm_i915_private *dev_priv = to_i915(dev);
5911 struct drm_atomic_state *state = pipe_config->base.state;
5912 struct intel_crtc *other_crtc;
5913 struct intel_crtc_state *other_crtc_state;
5914
5915 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5916 pipe_name(pipe), pipe_config->fdi_lanes);
5917 if (pipe_config->fdi_lanes > 4) {
5918 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5919 pipe_name(pipe), pipe_config->fdi_lanes);
5920 return -EINVAL;
5921 }
5922
5923 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
5924 if (pipe_config->fdi_lanes > 2) {
5925 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5926 pipe_config->fdi_lanes);
5927 return -EINVAL;
5928 } else {
5929 return 0;
5930 }
5931 }
5932
5933 if (INTEL_INFO(dev_priv)->num_pipes == 2)
5934 return 0;
5935
5936 /* Ivybridge 3 pipe is really complicated */
5937 switch (pipe) {
5938 case PIPE_A:
5939 return 0;
5940 case PIPE_B:
5941 if (pipe_config->fdi_lanes <= 2)
5942 return 0;
5943
5944 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
5945 other_crtc_state =
5946 intel_atomic_get_crtc_state(state, other_crtc);
5947 if (IS_ERR(other_crtc_state))
5948 return PTR_ERR(other_crtc_state);
5949
5950 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
5951 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5952 pipe_name(pipe), pipe_config->fdi_lanes);
5953 return -EINVAL;
5954 }
5955 return 0;
5956 case PIPE_C:
5957 if (pipe_config->fdi_lanes > 2) {
5958 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
5959 pipe_name(pipe), pipe_config->fdi_lanes);
5960 return -EINVAL;
5961 }
5962
5963 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
5964 other_crtc_state =
5965 intel_atomic_get_crtc_state(state, other_crtc);
5966 if (IS_ERR(other_crtc_state))
5967 return PTR_ERR(other_crtc_state);
5968
5969 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
5970 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5971 return -EINVAL;
5972 }
5973 return 0;
5974 default:
5975 BUG();
5976 }
5977 }
5978
5979 #define RETRY 1
5980 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5981 struct intel_crtc_state *pipe_config)
5982 {
5983 struct drm_device *dev = intel_crtc->base.dev;
5984 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5985 int lane, link_bw, fdi_dotclock, ret;
5986 bool needs_recompute = false;
5987
5988 retry:
5989 /* FDI is a binary signal running at ~2.7GHz, encoding
5990 * each output octet as 10 bits. The actual frequency
5991 * is stored as a divider into a 100MHz clock, and the
5992 * mode pixel clock is stored in units of 1KHz.
5993 * Hence the bw of each lane in terms of the mode signal
5994 * is:
5995 */
5996 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
5997
5998 fdi_dotclock = adjusted_mode->crtc_clock;
5999
6000 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6001 pipe_config->pipe_bpp);
6002
6003 pipe_config->fdi_lanes = lane;
6004
6005 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6006 link_bw, &pipe_config->fdi_m_n, false);
6007
6008 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6009 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6010 pipe_config->pipe_bpp -= 2*3;
6011 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6012 pipe_config->pipe_bpp);
6013 needs_recompute = true;
6014 pipe_config->bw_constrained = true;
6015
6016 goto retry;
6017 }
6018
6019 if (needs_recompute)
6020 return RETRY;
6021
6022 return ret;
6023 }
6024
6025 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6026 struct intel_crtc_state *pipe_config)
6027 {
6028 if (pipe_config->pipe_bpp > 24)
6029 return false;
6030
6031 /* HSW can handle pixel rate up to cdclk? */
6032 if (IS_HASWELL(dev_priv))
6033 return true;
6034
6035 /*
6036 * We compare against max which means we must take
6037 * the increased cdclk requirement into account when
6038 * calculating the new cdclk.
6039 *
6040 * Should measure whether using a lower cdclk w/o IPS
6041 */
6042 return pipe_config->pixel_rate <=
6043 dev_priv->max_cdclk_freq * 95 / 100;
6044 }
6045
6046 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6047 struct intel_crtc_state *pipe_config)
6048 {
6049 struct drm_device *dev = crtc->base.dev;
6050 struct drm_i915_private *dev_priv = to_i915(dev);
6051
6052 pipe_config->ips_enabled = i915.enable_ips &&
6053 hsw_crtc_supports_ips(crtc) &&
6054 pipe_config_supports_ips(dev_priv, pipe_config);
6055 }
6056
6057 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6058 {
6059 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6060
6061 /* GDG double wide on either pipe, otherwise pipe A only */
6062 return INTEL_INFO(dev_priv)->gen < 4 &&
6063 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6064 }
6065
6066 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6067 {
6068 uint32_t pixel_rate;
6069
6070 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6071
6072 /*
6073 * We only use IF-ID interlacing. If we ever use
6074 * PF-ID we'll need to adjust the pixel_rate here.
6075 */
6076
6077 if (pipe_config->pch_pfit.enabled) {
6078 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6079 uint32_t pfit_size = pipe_config->pch_pfit.size;
6080
6081 pipe_w = pipe_config->pipe_src_w;
6082 pipe_h = pipe_config->pipe_src_h;
6083
6084 pfit_w = (pfit_size >> 16) & 0xFFFF;
6085 pfit_h = pfit_size & 0xFFFF;
6086 if (pipe_w < pfit_w)
6087 pipe_w = pfit_w;
6088 if (pipe_h < pfit_h)
6089 pipe_h = pfit_h;
6090
6091 if (WARN_ON(!pfit_w || !pfit_h))
6092 return pixel_rate;
6093
6094 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6095 pfit_w * pfit_h);
6096 }
6097
6098 return pixel_rate;
6099 }
6100
6101 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6102 {
6103 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6104
6105 if (HAS_GMCH_DISPLAY(dev_priv))
6106 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6107 crtc_state->pixel_rate =
6108 crtc_state->base.adjusted_mode.crtc_clock;
6109 else
6110 crtc_state->pixel_rate =
6111 ilk_pipe_pixel_rate(crtc_state);
6112 }
6113
6114 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6115 struct intel_crtc_state *pipe_config)
6116 {
6117 struct drm_device *dev = crtc->base.dev;
6118 struct drm_i915_private *dev_priv = to_i915(dev);
6119 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6120 int clock_limit = dev_priv->max_dotclk_freq;
6121
6122 if (INTEL_GEN(dev_priv) < 4) {
6123 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6124
6125 /*
6126 * Enable double wide mode when the dot clock
6127 * is > 90% of the (display) core speed.
6128 */
6129 if (intel_crtc_supports_double_wide(crtc) &&
6130 adjusted_mode->crtc_clock > clock_limit) {
6131 clock_limit = dev_priv->max_dotclk_freq;
6132 pipe_config->double_wide = true;
6133 }
6134 }
6135
6136 if (adjusted_mode->crtc_clock > clock_limit) {
6137 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6138 adjusted_mode->crtc_clock, clock_limit,
6139 yesno(pipe_config->double_wide));
6140 return -EINVAL;
6141 }
6142
6143 if (pipe_config->ycbcr420 && pipe_config->base.ctm) {
6144 /*
6145 * There is only one pipe CSC unit per pipe, and we need that
6146 * for output conversion from RGB->YCBCR. So if CTM is already
6147 * applied we can't support YCBCR420 output.
6148 */
6149 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
6150 return -EINVAL;
6151 }
6152
6153 /*
6154 * Pipe horizontal size must be even in:
6155 * - DVO ganged mode
6156 * - LVDS dual channel mode
6157 * - Double wide pipe
6158 */
6159 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6160 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6161 pipe_config->pipe_src_w &= ~1;
6162
6163 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6164 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6165 */
6166 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6167 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6168 return -EINVAL;
6169
6170 intel_crtc_compute_pixel_rate(pipe_config);
6171
6172 if (HAS_IPS(dev_priv))
6173 hsw_compute_ips_config(crtc, pipe_config);
6174
6175 if (pipe_config->has_pch_encoder)
6176 return ironlake_fdi_compute_config(crtc, pipe_config);
6177
6178 return 0;
6179 }
6180
6181 static void
6182 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6183 {
6184 while (*num > DATA_LINK_M_N_MASK ||
6185 *den > DATA_LINK_M_N_MASK) {
6186 *num >>= 1;
6187 *den >>= 1;
6188 }
6189 }
6190
6191 static void compute_m_n(unsigned int m, unsigned int n,
6192 uint32_t *ret_m, uint32_t *ret_n,
6193 bool reduce_m_n)
6194 {
6195 /*
6196 * Reduce M/N as much as possible without loss in precision. Several DP
6197 * dongles in particular seem to be fussy about too large *link* M/N
6198 * values. The passed in values are more likely to have the least
6199 * significant bits zero than M after rounding below, so do this first.
6200 */
6201 if (reduce_m_n) {
6202 while ((m & 1) == 0 && (n & 1) == 0) {
6203 m >>= 1;
6204 n >>= 1;
6205 }
6206 }
6207
6208 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6209 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6210 intel_reduce_m_n_ratio(ret_m, ret_n);
6211 }
6212
6213 void
6214 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6215 int pixel_clock, int link_clock,
6216 struct intel_link_m_n *m_n,
6217 bool reduce_m_n)
6218 {
6219 m_n->tu = 64;
6220
6221 compute_m_n(bits_per_pixel * pixel_clock,
6222 link_clock * nlanes * 8,
6223 &m_n->gmch_m, &m_n->gmch_n,
6224 reduce_m_n);
6225
6226 compute_m_n(pixel_clock, link_clock,
6227 &m_n->link_m, &m_n->link_n,
6228 reduce_m_n);
6229 }
6230
6231 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6232 {
6233 if (i915.panel_use_ssc >= 0)
6234 return i915.panel_use_ssc != 0;
6235 return dev_priv->vbt.lvds_use_ssc
6236 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6237 }
6238
6239 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6240 {
6241 return (1 << dpll->n) << 16 | dpll->m2;
6242 }
6243
6244 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6245 {
6246 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6247 }
6248
6249 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6250 struct intel_crtc_state *crtc_state,
6251 struct dpll *reduced_clock)
6252 {
6253 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6254 u32 fp, fp2 = 0;
6255
6256 if (IS_PINEVIEW(dev_priv)) {
6257 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6258 if (reduced_clock)
6259 fp2 = pnv_dpll_compute_fp(reduced_clock);
6260 } else {
6261 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6262 if (reduced_clock)
6263 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6264 }
6265
6266 crtc_state->dpll_hw_state.fp0 = fp;
6267
6268 crtc->lowfreq_avail = false;
6269 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6270 reduced_clock) {
6271 crtc_state->dpll_hw_state.fp1 = fp2;
6272 crtc->lowfreq_avail = true;
6273 } else {
6274 crtc_state->dpll_hw_state.fp1 = fp;
6275 }
6276 }
6277
6278 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6279 pipe)
6280 {
6281 u32 reg_val;
6282
6283 /*
6284 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6285 * and set it to a reasonable value instead.
6286 */
6287 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6288 reg_val &= 0xffffff00;
6289 reg_val |= 0x00000030;
6290 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6291
6292 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6293 reg_val &= 0x00ffffff;
6294 reg_val |= 0x8c000000;
6295 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6296
6297 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6298 reg_val &= 0xffffff00;
6299 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6300
6301 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6302 reg_val &= 0x00ffffff;
6303 reg_val |= 0xb0000000;
6304 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6305 }
6306
6307 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6308 struct intel_link_m_n *m_n)
6309 {
6310 struct drm_device *dev = crtc->base.dev;
6311 struct drm_i915_private *dev_priv = to_i915(dev);
6312 int pipe = crtc->pipe;
6313
6314 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6315 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6316 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6317 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6318 }
6319
6320 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6321 struct intel_link_m_n *m_n,
6322 struct intel_link_m_n *m2_n2)
6323 {
6324 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6325 int pipe = crtc->pipe;
6326 enum transcoder transcoder = crtc->config->cpu_transcoder;
6327
6328 if (INTEL_GEN(dev_priv) >= 5) {
6329 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6330 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6331 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6332 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6333 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6334 * for gen < 8) and if DRRS is supported (to make sure the
6335 * registers are not unnecessarily accessed).
6336 */
6337 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6338 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6339 I915_WRITE(PIPE_DATA_M2(transcoder),
6340 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6341 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6342 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6343 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6344 }
6345 } else {
6346 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6347 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6348 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6349 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6350 }
6351 }
6352
6353 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6354 {
6355 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6356
6357 if (m_n == M1_N1) {
6358 dp_m_n = &crtc->config->dp_m_n;
6359 dp_m2_n2 = &crtc->config->dp_m2_n2;
6360 } else if (m_n == M2_N2) {
6361
6362 /*
6363 * M2_N2 registers are not supported. Hence m2_n2 divider value
6364 * needs to be programmed into M1_N1.
6365 */
6366 dp_m_n = &crtc->config->dp_m2_n2;
6367 } else {
6368 DRM_ERROR("Unsupported divider value\n");
6369 return;
6370 }
6371
6372 if (crtc->config->has_pch_encoder)
6373 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6374 else
6375 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6376 }
6377
6378 static void vlv_compute_dpll(struct intel_crtc *crtc,
6379 struct intel_crtc_state *pipe_config)
6380 {
6381 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6382 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6383 if (crtc->pipe != PIPE_A)
6384 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6385
6386 /* DPLL not used with DSI, but still need the rest set up */
6387 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6388 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6389 DPLL_EXT_BUFFER_ENABLE_VLV;
6390
6391 pipe_config->dpll_hw_state.dpll_md =
6392 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6393 }
6394
6395 static void chv_compute_dpll(struct intel_crtc *crtc,
6396 struct intel_crtc_state *pipe_config)
6397 {
6398 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6399 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6400 if (crtc->pipe != PIPE_A)
6401 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6402
6403 /* DPLL not used with DSI, but still need the rest set up */
6404 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6405 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6406
6407 pipe_config->dpll_hw_state.dpll_md =
6408 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6409 }
6410
6411 static void vlv_prepare_pll(struct intel_crtc *crtc,
6412 const struct intel_crtc_state *pipe_config)
6413 {
6414 struct drm_device *dev = crtc->base.dev;
6415 struct drm_i915_private *dev_priv = to_i915(dev);
6416 enum pipe pipe = crtc->pipe;
6417 u32 mdiv;
6418 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6419 u32 coreclk, reg_val;
6420
6421 /* Enable Refclk */
6422 I915_WRITE(DPLL(pipe),
6423 pipe_config->dpll_hw_state.dpll &
6424 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6425
6426 /* No need to actually set up the DPLL with DSI */
6427 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6428 return;
6429
6430 mutex_lock(&dev_priv->sb_lock);
6431
6432 bestn = pipe_config->dpll.n;
6433 bestm1 = pipe_config->dpll.m1;
6434 bestm2 = pipe_config->dpll.m2;
6435 bestp1 = pipe_config->dpll.p1;
6436 bestp2 = pipe_config->dpll.p2;
6437
6438 /* See eDP HDMI DPIO driver vbios notes doc */
6439
6440 /* PLL B needs special handling */
6441 if (pipe == PIPE_B)
6442 vlv_pllb_recal_opamp(dev_priv, pipe);
6443
6444 /* Set up Tx target for periodic Rcomp update */
6445 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6446
6447 /* Disable target IRef on PLL */
6448 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6449 reg_val &= 0x00ffffff;
6450 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6451
6452 /* Disable fast lock */
6453 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6454
6455 /* Set idtafcrecal before PLL is enabled */
6456 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6457 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6458 mdiv |= ((bestn << DPIO_N_SHIFT));
6459 mdiv |= (1 << DPIO_K_SHIFT);
6460
6461 /*
6462 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6463 * but we don't support that).
6464 * Note: don't use the DAC post divider as it seems unstable.
6465 */
6466 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6467 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6468
6469 mdiv |= DPIO_ENABLE_CALIBRATION;
6470 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6471
6472 /* Set HBR and RBR LPF coefficients */
6473 if (pipe_config->port_clock == 162000 ||
6474 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6475 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6476 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6477 0x009f0003);
6478 else
6479 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6480 0x00d0000f);
6481
6482 if (intel_crtc_has_dp_encoder(pipe_config)) {
6483 /* Use SSC source */
6484 if (pipe == PIPE_A)
6485 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6486 0x0df40000);
6487 else
6488 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6489 0x0df70000);
6490 } else { /* HDMI or VGA */
6491 /* Use bend source */
6492 if (pipe == PIPE_A)
6493 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6494 0x0df70000);
6495 else
6496 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6497 0x0df40000);
6498 }
6499
6500 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6501 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6502 if (intel_crtc_has_dp_encoder(crtc->config))
6503 coreclk |= 0x01000000;
6504 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6505
6506 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6507 mutex_unlock(&dev_priv->sb_lock);
6508 }
6509
6510 static void chv_prepare_pll(struct intel_crtc *crtc,
6511 const struct intel_crtc_state *pipe_config)
6512 {
6513 struct drm_device *dev = crtc->base.dev;
6514 struct drm_i915_private *dev_priv = to_i915(dev);
6515 enum pipe pipe = crtc->pipe;
6516 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6517 u32 loopfilter, tribuf_calcntr;
6518 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6519 u32 dpio_val;
6520 int vco;
6521
6522 /* Enable Refclk and SSC */
6523 I915_WRITE(DPLL(pipe),
6524 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6525
6526 /* No need to actually set up the DPLL with DSI */
6527 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6528 return;
6529
6530 bestn = pipe_config->dpll.n;
6531 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6532 bestm1 = pipe_config->dpll.m1;
6533 bestm2 = pipe_config->dpll.m2 >> 22;
6534 bestp1 = pipe_config->dpll.p1;
6535 bestp2 = pipe_config->dpll.p2;
6536 vco = pipe_config->dpll.vco;
6537 dpio_val = 0;
6538 loopfilter = 0;
6539
6540 mutex_lock(&dev_priv->sb_lock);
6541
6542 /* p1 and p2 divider */
6543 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6544 5 << DPIO_CHV_S1_DIV_SHIFT |
6545 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6546 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6547 1 << DPIO_CHV_K_DIV_SHIFT);
6548
6549 /* Feedback post-divider - m2 */
6550 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6551
6552 /* Feedback refclk divider - n and m1 */
6553 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6554 DPIO_CHV_M1_DIV_BY_2 |
6555 1 << DPIO_CHV_N_DIV_SHIFT);
6556
6557 /* M2 fraction division */
6558 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6559
6560 /* M2 fraction division enable */
6561 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6562 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6563 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6564 if (bestm2_frac)
6565 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6566 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6567
6568 /* Program digital lock detect threshold */
6569 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6570 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6571 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6572 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6573 if (!bestm2_frac)
6574 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6575 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6576
6577 /* Loop filter */
6578 if (vco == 5400000) {
6579 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6580 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6581 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6582 tribuf_calcntr = 0x9;
6583 } else if (vco <= 6200000) {
6584 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6585 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6586 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6587 tribuf_calcntr = 0x9;
6588 } else if (vco <= 6480000) {
6589 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6590 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6591 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6592 tribuf_calcntr = 0x8;
6593 } else {
6594 /* Not supported. Apply the same limits as in the max case */
6595 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6596 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6597 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6598 tribuf_calcntr = 0;
6599 }
6600 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6601
6602 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6603 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6604 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6605 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6606
6607 /* AFC Recal */
6608 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6609 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6610 DPIO_AFC_RECAL);
6611
6612 mutex_unlock(&dev_priv->sb_lock);
6613 }
6614
6615 /**
6616 * vlv_force_pll_on - forcibly enable just the PLL
6617 * @dev_priv: i915 private structure
6618 * @pipe: pipe PLL to enable
6619 * @dpll: PLL configuration
6620 *
6621 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6622 * in cases where we need the PLL enabled even when @pipe is not going to
6623 * be enabled.
6624 */
6625 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6626 const struct dpll *dpll)
6627 {
6628 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6629 struct intel_crtc_state *pipe_config;
6630
6631 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6632 if (!pipe_config)
6633 return -ENOMEM;
6634
6635 pipe_config->base.crtc = &crtc->base;
6636 pipe_config->pixel_multiplier = 1;
6637 pipe_config->dpll = *dpll;
6638
6639 if (IS_CHERRYVIEW(dev_priv)) {
6640 chv_compute_dpll(crtc, pipe_config);
6641 chv_prepare_pll(crtc, pipe_config);
6642 chv_enable_pll(crtc, pipe_config);
6643 } else {
6644 vlv_compute_dpll(crtc, pipe_config);
6645 vlv_prepare_pll(crtc, pipe_config);
6646 vlv_enable_pll(crtc, pipe_config);
6647 }
6648
6649 kfree(pipe_config);
6650
6651 return 0;
6652 }
6653
6654 /**
6655 * vlv_force_pll_off - forcibly disable just the PLL
6656 * @dev_priv: i915 private structure
6657 * @pipe: pipe PLL to disable
6658 *
6659 * Disable the PLL for @pipe. To be used in cases where we need
6660 * the PLL enabled even when @pipe is not going to be enabled.
6661 */
6662 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6663 {
6664 if (IS_CHERRYVIEW(dev_priv))
6665 chv_disable_pll(dev_priv, pipe);
6666 else
6667 vlv_disable_pll(dev_priv, pipe);
6668 }
6669
6670 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6671 struct intel_crtc_state *crtc_state,
6672 struct dpll *reduced_clock)
6673 {
6674 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6675 u32 dpll;
6676 struct dpll *clock = &crtc_state->dpll;
6677
6678 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6679
6680 dpll = DPLL_VGA_MODE_DIS;
6681
6682 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6683 dpll |= DPLLB_MODE_LVDS;
6684 else
6685 dpll |= DPLLB_MODE_DAC_SERIAL;
6686
6687 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6688 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6689 dpll |= (crtc_state->pixel_multiplier - 1)
6690 << SDVO_MULTIPLIER_SHIFT_HIRES;
6691 }
6692
6693 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6694 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6695 dpll |= DPLL_SDVO_HIGH_SPEED;
6696
6697 if (intel_crtc_has_dp_encoder(crtc_state))
6698 dpll |= DPLL_SDVO_HIGH_SPEED;
6699
6700 /* compute bitmask from p1 value */
6701 if (IS_PINEVIEW(dev_priv))
6702 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6703 else {
6704 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6705 if (IS_G4X(dev_priv) && reduced_clock)
6706 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6707 }
6708 switch (clock->p2) {
6709 case 5:
6710 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6711 break;
6712 case 7:
6713 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6714 break;
6715 case 10:
6716 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6717 break;
6718 case 14:
6719 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6720 break;
6721 }
6722 if (INTEL_GEN(dev_priv) >= 4)
6723 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6724
6725 if (crtc_state->sdvo_tv_clock)
6726 dpll |= PLL_REF_INPUT_TVCLKINBC;
6727 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6728 intel_panel_use_ssc(dev_priv))
6729 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6730 else
6731 dpll |= PLL_REF_INPUT_DREFCLK;
6732
6733 dpll |= DPLL_VCO_ENABLE;
6734 crtc_state->dpll_hw_state.dpll = dpll;
6735
6736 if (INTEL_GEN(dev_priv) >= 4) {
6737 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6738 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6739 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6740 }
6741 }
6742
6743 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6744 struct intel_crtc_state *crtc_state,
6745 struct dpll *reduced_clock)
6746 {
6747 struct drm_device *dev = crtc->base.dev;
6748 struct drm_i915_private *dev_priv = to_i915(dev);
6749 u32 dpll;
6750 struct dpll *clock = &crtc_state->dpll;
6751
6752 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6753
6754 dpll = DPLL_VGA_MODE_DIS;
6755
6756 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6757 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6758 } else {
6759 if (clock->p1 == 2)
6760 dpll |= PLL_P1_DIVIDE_BY_TWO;
6761 else
6762 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6763 if (clock->p2 == 4)
6764 dpll |= PLL_P2_DIVIDE_BY_4;
6765 }
6766
6767 if (!IS_I830(dev_priv) &&
6768 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6769 dpll |= DPLL_DVO_2X_MODE;
6770
6771 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6772 intel_panel_use_ssc(dev_priv))
6773 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6774 else
6775 dpll |= PLL_REF_INPUT_DREFCLK;
6776
6777 dpll |= DPLL_VCO_ENABLE;
6778 crtc_state->dpll_hw_state.dpll = dpll;
6779 }
6780
6781 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6782 {
6783 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6784 enum pipe pipe = intel_crtc->pipe;
6785 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6786 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6787 uint32_t crtc_vtotal, crtc_vblank_end;
6788 int vsyncshift = 0;
6789
6790 /* We need to be careful not to changed the adjusted mode, for otherwise
6791 * the hw state checker will get angry at the mismatch. */
6792 crtc_vtotal = adjusted_mode->crtc_vtotal;
6793 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6794
6795 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6796 /* the chip adds 2 halflines automatically */
6797 crtc_vtotal -= 1;
6798 crtc_vblank_end -= 1;
6799
6800 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6801 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6802 else
6803 vsyncshift = adjusted_mode->crtc_hsync_start -
6804 adjusted_mode->crtc_htotal / 2;
6805 if (vsyncshift < 0)
6806 vsyncshift += adjusted_mode->crtc_htotal;
6807 }
6808
6809 if (INTEL_GEN(dev_priv) > 3)
6810 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6811
6812 I915_WRITE(HTOTAL(cpu_transcoder),
6813 (adjusted_mode->crtc_hdisplay - 1) |
6814 ((adjusted_mode->crtc_htotal - 1) << 16));
6815 I915_WRITE(HBLANK(cpu_transcoder),
6816 (adjusted_mode->crtc_hblank_start - 1) |
6817 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6818 I915_WRITE(HSYNC(cpu_transcoder),
6819 (adjusted_mode->crtc_hsync_start - 1) |
6820 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6821
6822 I915_WRITE(VTOTAL(cpu_transcoder),
6823 (adjusted_mode->crtc_vdisplay - 1) |
6824 ((crtc_vtotal - 1) << 16));
6825 I915_WRITE(VBLANK(cpu_transcoder),
6826 (adjusted_mode->crtc_vblank_start - 1) |
6827 ((crtc_vblank_end - 1) << 16));
6828 I915_WRITE(VSYNC(cpu_transcoder),
6829 (adjusted_mode->crtc_vsync_start - 1) |
6830 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6831
6832 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6833 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6834 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6835 * bits. */
6836 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
6837 (pipe == PIPE_B || pipe == PIPE_C))
6838 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6839
6840 }
6841
6842 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
6843 {
6844 struct drm_device *dev = intel_crtc->base.dev;
6845 struct drm_i915_private *dev_priv = to_i915(dev);
6846 enum pipe pipe = intel_crtc->pipe;
6847
6848 /* pipesrc controls the size that is scaled from, which should
6849 * always be the user's requested size.
6850 */
6851 I915_WRITE(PIPESRC(pipe),
6852 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6853 (intel_crtc->config->pipe_src_h - 1));
6854 }
6855
6856 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6857 struct intel_crtc_state *pipe_config)
6858 {
6859 struct drm_device *dev = crtc->base.dev;
6860 struct drm_i915_private *dev_priv = to_i915(dev);
6861 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6862 uint32_t tmp;
6863
6864 tmp = I915_READ(HTOTAL(cpu_transcoder));
6865 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6866 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6867 tmp = I915_READ(HBLANK(cpu_transcoder));
6868 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6869 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6870 tmp = I915_READ(HSYNC(cpu_transcoder));
6871 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6872 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6873
6874 tmp = I915_READ(VTOTAL(cpu_transcoder));
6875 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6876 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6877 tmp = I915_READ(VBLANK(cpu_transcoder));
6878 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6879 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6880 tmp = I915_READ(VSYNC(cpu_transcoder));
6881 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6882 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6883
6884 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6885 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6886 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6887 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6888 }
6889 }
6890
6891 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
6892 struct intel_crtc_state *pipe_config)
6893 {
6894 struct drm_device *dev = crtc->base.dev;
6895 struct drm_i915_private *dev_priv = to_i915(dev);
6896 u32 tmp;
6897
6898 tmp = I915_READ(PIPESRC(crtc->pipe));
6899 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6900 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6901
6902 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6903 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6904 }
6905
6906 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6907 struct intel_crtc_state *pipe_config)
6908 {
6909 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6910 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6911 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6912 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6913
6914 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6915 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6916 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6917 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6918
6919 mode->flags = pipe_config->base.adjusted_mode.flags;
6920 mode->type = DRM_MODE_TYPE_DRIVER;
6921
6922 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6923
6924 mode->hsync = drm_mode_hsync(mode);
6925 mode->vrefresh = drm_mode_vrefresh(mode);
6926 drm_mode_set_name(mode);
6927 }
6928
6929 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6930 {
6931 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6932 uint32_t pipeconf;
6933
6934 pipeconf = 0;
6935
6936 /* we keep both pipes enabled on 830 */
6937 if (IS_I830(dev_priv))
6938 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6939
6940 if (intel_crtc->config->double_wide)
6941 pipeconf |= PIPECONF_DOUBLE_WIDE;
6942
6943 /* only g4x and later have fancy bpc/dither controls */
6944 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
6945 IS_CHERRYVIEW(dev_priv)) {
6946 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6947 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6948 pipeconf |= PIPECONF_DITHER_EN |
6949 PIPECONF_DITHER_TYPE_SP;
6950
6951 switch (intel_crtc->config->pipe_bpp) {
6952 case 18:
6953 pipeconf |= PIPECONF_6BPC;
6954 break;
6955 case 24:
6956 pipeconf |= PIPECONF_8BPC;
6957 break;
6958 case 30:
6959 pipeconf |= PIPECONF_10BPC;
6960 break;
6961 default:
6962 /* Case prevented by intel_choose_pipe_bpp_dither. */
6963 BUG();
6964 }
6965 }
6966
6967 if (HAS_PIPE_CXSR(dev_priv)) {
6968 if (intel_crtc->lowfreq_avail) {
6969 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6970 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6971 } else {
6972 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6973 }
6974 }
6975
6976 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6977 if (INTEL_GEN(dev_priv) < 4 ||
6978 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6979 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6980 else
6981 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6982 } else
6983 pipeconf |= PIPECONF_PROGRESSIVE;
6984
6985 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
6986 intel_crtc->config->limited_color_range)
6987 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6988
6989 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6990 POSTING_READ(PIPECONF(intel_crtc->pipe));
6991 }
6992
6993 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
6994 struct intel_crtc_state *crtc_state)
6995 {
6996 struct drm_device *dev = crtc->base.dev;
6997 struct drm_i915_private *dev_priv = to_i915(dev);
6998 const struct intel_limit *limit;
6999 int refclk = 48000;
7000
7001 memset(&crtc_state->dpll_hw_state, 0,
7002 sizeof(crtc_state->dpll_hw_state));
7003
7004 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7005 if (intel_panel_use_ssc(dev_priv)) {
7006 refclk = dev_priv->vbt.lvds_ssc_freq;
7007 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7008 }
7009
7010 limit = &intel_limits_i8xx_lvds;
7011 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7012 limit = &intel_limits_i8xx_dvo;
7013 } else {
7014 limit = &intel_limits_i8xx_dac;
7015 }
7016
7017 if (!crtc_state->clock_set &&
7018 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7019 refclk, NULL, &crtc_state->dpll)) {
7020 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7021 return -EINVAL;
7022 }
7023
7024 i8xx_compute_dpll(crtc, crtc_state, NULL);
7025
7026 return 0;
7027 }
7028
7029 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7030 struct intel_crtc_state *crtc_state)
7031 {
7032 struct drm_device *dev = crtc->base.dev;
7033 struct drm_i915_private *dev_priv = to_i915(dev);
7034 const struct intel_limit *limit;
7035 int refclk = 96000;
7036
7037 memset(&crtc_state->dpll_hw_state, 0,
7038 sizeof(crtc_state->dpll_hw_state));
7039
7040 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7041 if (intel_panel_use_ssc(dev_priv)) {
7042 refclk = dev_priv->vbt.lvds_ssc_freq;
7043 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7044 }
7045
7046 if (intel_is_dual_link_lvds(dev))
7047 limit = &intel_limits_g4x_dual_channel_lvds;
7048 else
7049 limit = &intel_limits_g4x_single_channel_lvds;
7050 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7051 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7052 limit = &intel_limits_g4x_hdmi;
7053 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7054 limit = &intel_limits_g4x_sdvo;
7055 } else {
7056 /* The option is for other outputs */
7057 limit = &intel_limits_i9xx_sdvo;
7058 }
7059
7060 if (!crtc_state->clock_set &&
7061 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7062 refclk, NULL, &crtc_state->dpll)) {
7063 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7064 return -EINVAL;
7065 }
7066
7067 i9xx_compute_dpll(crtc, crtc_state, NULL);
7068
7069 return 0;
7070 }
7071
7072 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7073 struct intel_crtc_state *crtc_state)
7074 {
7075 struct drm_device *dev = crtc->base.dev;
7076 struct drm_i915_private *dev_priv = to_i915(dev);
7077 const struct intel_limit *limit;
7078 int refclk = 96000;
7079
7080 memset(&crtc_state->dpll_hw_state, 0,
7081 sizeof(crtc_state->dpll_hw_state));
7082
7083 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7084 if (intel_panel_use_ssc(dev_priv)) {
7085 refclk = dev_priv->vbt.lvds_ssc_freq;
7086 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7087 }
7088
7089 limit = &intel_limits_pineview_lvds;
7090 } else {
7091 limit = &intel_limits_pineview_sdvo;
7092 }
7093
7094 if (!crtc_state->clock_set &&
7095 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7096 refclk, NULL, &crtc_state->dpll)) {
7097 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7098 return -EINVAL;
7099 }
7100
7101 i9xx_compute_dpll(crtc, crtc_state, NULL);
7102
7103 return 0;
7104 }
7105
7106 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7107 struct intel_crtc_state *crtc_state)
7108 {
7109 struct drm_device *dev = crtc->base.dev;
7110 struct drm_i915_private *dev_priv = to_i915(dev);
7111 const struct intel_limit *limit;
7112 int refclk = 96000;
7113
7114 memset(&crtc_state->dpll_hw_state, 0,
7115 sizeof(crtc_state->dpll_hw_state));
7116
7117 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7118 if (intel_panel_use_ssc(dev_priv)) {
7119 refclk = dev_priv->vbt.lvds_ssc_freq;
7120 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7121 }
7122
7123 limit = &intel_limits_i9xx_lvds;
7124 } else {
7125 limit = &intel_limits_i9xx_sdvo;
7126 }
7127
7128 if (!crtc_state->clock_set &&
7129 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7130 refclk, NULL, &crtc_state->dpll)) {
7131 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7132 return -EINVAL;
7133 }
7134
7135 i9xx_compute_dpll(crtc, crtc_state, NULL);
7136
7137 return 0;
7138 }
7139
7140 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7141 struct intel_crtc_state *crtc_state)
7142 {
7143 int refclk = 100000;
7144 const struct intel_limit *limit = &intel_limits_chv;
7145
7146 memset(&crtc_state->dpll_hw_state, 0,
7147 sizeof(crtc_state->dpll_hw_state));
7148
7149 if (!crtc_state->clock_set &&
7150 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7151 refclk, NULL, &crtc_state->dpll)) {
7152 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7153 return -EINVAL;
7154 }
7155
7156 chv_compute_dpll(crtc, crtc_state);
7157
7158 return 0;
7159 }
7160
7161 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7162 struct intel_crtc_state *crtc_state)
7163 {
7164 int refclk = 100000;
7165 const struct intel_limit *limit = &intel_limits_vlv;
7166
7167 memset(&crtc_state->dpll_hw_state, 0,
7168 sizeof(crtc_state->dpll_hw_state));
7169
7170 if (!crtc_state->clock_set &&
7171 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7172 refclk, NULL, &crtc_state->dpll)) {
7173 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7174 return -EINVAL;
7175 }
7176
7177 vlv_compute_dpll(crtc, crtc_state);
7178
7179 return 0;
7180 }
7181
7182 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7183 struct intel_crtc_state *pipe_config)
7184 {
7185 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7186 uint32_t tmp;
7187
7188 if (INTEL_GEN(dev_priv) <= 3 &&
7189 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7190 return;
7191
7192 tmp = I915_READ(PFIT_CONTROL);
7193 if (!(tmp & PFIT_ENABLE))
7194 return;
7195
7196 /* Check whether the pfit is attached to our pipe. */
7197 if (INTEL_GEN(dev_priv) < 4) {
7198 if (crtc->pipe != PIPE_B)
7199 return;
7200 } else {
7201 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7202 return;
7203 }
7204
7205 pipe_config->gmch_pfit.control = tmp;
7206 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7207 }
7208
7209 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7210 struct intel_crtc_state *pipe_config)
7211 {
7212 struct drm_device *dev = crtc->base.dev;
7213 struct drm_i915_private *dev_priv = to_i915(dev);
7214 int pipe = pipe_config->cpu_transcoder;
7215 struct dpll clock;
7216 u32 mdiv;
7217 int refclk = 100000;
7218
7219 /* In case of DSI, DPLL will not be used */
7220 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7221 return;
7222
7223 mutex_lock(&dev_priv->sb_lock);
7224 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7225 mutex_unlock(&dev_priv->sb_lock);
7226
7227 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7228 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7229 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7230 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7231 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7232
7233 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7234 }
7235
7236 static void
7237 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7238 struct intel_initial_plane_config *plane_config)
7239 {
7240 struct drm_device *dev = crtc->base.dev;
7241 struct drm_i915_private *dev_priv = to_i915(dev);
7242 u32 val, base, offset;
7243 int pipe = crtc->pipe, plane = crtc->plane;
7244 int fourcc, pixel_format;
7245 unsigned int aligned_height;
7246 struct drm_framebuffer *fb;
7247 struct intel_framebuffer *intel_fb;
7248
7249 val = I915_READ(DSPCNTR(plane));
7250 if (!(val & DISPLAY_PLANE_ENABLE))
7251 return;
7252
7253 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7254 if (!intel_fb) {
7255 DRM_DEBUG_KMS("failed to alloc fb\n");
7256 return;
7257 }
7258
7259 fb = &intel_fb->base;
7260
7261 fb->dev = dev;
7262
7263 if (INTEL_GEN(dev_priv) >= 4) {
7264 if (val & DISPPLANE_TILED) {
7265 plane_config->tiling = I915_TILING_X;
7266 fb->modifier = I915_FORMAT_MOD_X_TILED;
7267 }
7268 }
7269
7270 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7271 fourcc = i9xx_format_to_fourcc(pixel_format);
7272 fb->format = drm_format_info(fourcc);
7273
7274 if (INTEL_GEN(dev_priv) >= 4) {
7275 if (plane_config->tiling)
7276 offset = I915_READ(DSPTILEOFF(plane));
7277 else
7278 offset = I915_READ(DSPLINOFF(plane));
7279 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7280 } else {
7281 base = I915_READ(DSPADDR(plane));
7282 }
7283 plane_config->base = base;
7284
7285 val = I915_READ(PIPESRC(pipe));
7286 fb->width = ((val >> 16) & 0xfff) + 1;
7287 fb->height = ((val >> 0) & 0xfff) + 1;
7288
7289 val = I915_READ(DSPSTRIDE(pipe));
7290 fb->pitches[0] = val & 0xffffffc0;
7291
7292 aligned_height = intel_fb_align_height(fb, 0, fb->height);
7293
7294 plane_config->size = fb->pitches[0] * aligned_height;
7295
7296 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7297 pipe_name(pipe), plane, fb->width, fb->height,
7298 fb->format->cpp[0] * 8, base, fb->pitches[0],
7299 plane_config->size);
7300
7301 plane_config->fb = intel_fb;
7302 }
7303
7304 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7305 struct intel_crtc_state *pipe_config)
7306 {
7307 struct drm_device *dev = crtc->base.dev;
7308 struct drm_i915_private *dev_priv = to_i915(dev);
7309 int pipe = pipe_config->cpu_transcoder;
7310 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7311 struct dpll clock;
7312 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7313 int refclk = 100000;
7314
7315 /* In case of DSI, DPLL will not be used */
7316 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7317 return;
7318
7319 mutex_lock(&dev_priv->sb_lock);
7320 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7321 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7322 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7323 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7324 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7325 mutex_unlock(&dev_priv->sb_lock);
7326
7327 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7328 clock.m2 = (pll_dw0 & 0xff) << 22;
7329 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7330 clock.m2 |= pll_dw2 & 0x3fffff;
7331 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7332 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7333 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7334
7335 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7336 }
7337
7338 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7339 struct intel_crtc_state *pipe_config)
7340 {
7341 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7342 enum intel_display_power_domain power_domain;
7343 uint32_t tmp;
7344 bool ret;
7345
7346 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7347 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7348 return false;
7349
7350 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7351 pipe_config->shared_dpll = NULL;
7352
7353 ret = false;
7354
7355 tmp = I915_READ(PIPECONF(crtc->pipe));
7356 if (!(tmp & PIPECONF_ENABLE))
7357 goto out;
7358
7359 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7360 IS_CHERRYVIEW(dev_priv)) {
7361 switch (tmp & PIPECONF_BPC_MASK) {
7362 case PIPECONF_6BPC:
7363 pipe_config->pipe_bpp = 18;
7364 break;
7365 case PIPECONF_8BPC:
7366 pipe_config->pipe_bpp = 24;
7367 break;
7368 case PIPECONF_10BPC:
7369 pipe_config->pipe_bpp = 30;
7370 break;
7371 default:
7372 break;
7373 }
7374 }
7375
7376 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7377 (tmp & PIPECONF_COLOR_RANGE_SELECT))
7378 pipe_config->limited_color_range = true;
7379
7380 if (INTEL_GEN(dev_priv) < 4)
7381 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7382
7383 intel_get_pipe_timings(crtc, pipe_config);
7384 intel_get_pipe_src_size(crtc, pipe_config);
7385
7386 i9xx_get_pfit_config(crtc, pipe_config);
7387
7388 if (INTEL_GEN(dev_priv) >= 4) {
7389 /* No way to read it out on pipes B and C */
7390 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7391 tmp = dev_priv->chv_dpll_md[crtc->pipe];
7392 else
7393 tmp = I915_READ(DPLL_MD(crtc->pipe));
7394 pipe_config->pixel_multiplier =
7395 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7396 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7397 pipe_config->dpll_hw_state.dpll_md = tmp;
7398 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7399 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7400 tmp = I915_READ(DPLL(crtc->pipe));
7401 pipe_config->pixel_multiplier =
7402 ((tmp & SDVO_MULTIPLIER_MASK)
7403 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7404 } else {
7405 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7406 * port and will be fixed up in the encoder->get_config
7407 * function. */
7408 pipe_config->pixel_multiplier = 1;
7409 }
7410 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7411 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7412 /*
7413 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7414 * on 830. Filter it out here so that we don't
7415 * report errors due to that.
7416 */
7417 if (IS_I830(dev_priv))
7418 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7419
7420 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7421 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7422 } else {
7423 /* Mask out read-only status bits. */
7424 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7425 DPLL_PORTC_READY_MASK |
7426 DPLL_PORTB_READY_MASK);
7427 }
7428
7429 if (IS_CHERRYVIEW(dev_priv))
7430 chv_crtc_clock_get(crtc, pipe_config);
7431 else if (IS_VALLEYVIEW(dev_priv))
7432 vlv_crtc_clock_get(crtc, pipe_config);
7433 else
7434 i9xx_crtc_clock_get(crtc, pipe_config);
7435
7436 /*
7437 * Normally the dotclock is filled in by the encoder .get_config()
7438 * but in case the pipe is enabled w/o any ports we need a sane
7439 * default.
7440 */
7441 pipe_config->base.adjusted_mode.crtc_clock =
7442 pipe_config->port_clock / pipe_config->pixel_multiplier;
7443
7444 ret = true;
7445
7446 out:
7447 intel_display_power_put(dev_priv, power_domain);
7448
7449 return ret;
7450 }
7451
7452 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7453 {
7454 struct intel_encoder *encoder;
7455 int i;
7456 u32 val, final;
7457 bool has_lvds = false;
7458 bool has_cpu_edp = false;
7459 bool has_panel = false;
7460 bool has_ck505 = false;
7461 bool can_ssc = false;
7462 bool using_ssc_source = false;
7463
7464 /* We need to take the global config into account */
7465 for_each_intel_encoder(&dev_priv->drm, encoder) {
7466 switch (encoder->type) {
7467 case INTEL_OUTPUT_LVDS:
7468 has_panel = true;
7469 has_lvds = true;
7470 break;
7471 case INTEL_OUTPUT_EDP:
7472 has_panel = true;
7473 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7474 has_cpu_edp = true;
7475 break;
7476 default:
7477 break;
7478 }
7479 }
7480
7481 if (HAS_PCH_IBX(dev_priv)) {
7482 has_ck505 = dev_priv->vbt.display_clock_mode;
7483 can_ssc = has_ck505;
7484 } else {
7485 has_ck505 = false;
7486 can_ssc = true;
7487 }
7488
7489 /* Check if any DPLLs are using the SSC source */
7490 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7491 u32 temp = I915_READ(PCH_DPLL(i));
7492
7493 if (!(temp & DPLL_VCO_ENABLE))
7494 continue;
7495
7496 if ((temp & PLL_REF_INPUT_MASK) ==
7497 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7498 using_ssc_source = true;
7499 break;
7500 }
7501 }
7502
7503 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7504 has_panel, has_lvds, has_ck505, using_ssc_source);
7505
7506 /* Ironlake: try to setup display ref clock before DPLL
7507 * enabling. This is only under driver's control after
7508 * PCH B stepping, previous chipset stepping should be
7509 * ignoring this setting.
7510 */
7511 val = I915_READ(PCH_DREF_CONTROL);
7512
7513 /* As we must carefully and slowly disable/enable each source in turn,
7514 * compute the final state we want first and check if we need to
7515 * make any changes at all.
7516 */
7517 final = val;
7518 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7519 if (has_ck505)
7520 final |= DREF_NONSPREAD_CK505_ENABLE;
7521 else
7522 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7523
7524 final &= ~DREF_SSC_SOURCE_MASK;
7525 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7526 final &= ~DREF_SSC1_ENABLE;
7527
7528 if (has_panel) {
7529 final |= DREF_SSC_SOURCE_ENABLE;
7530
7531 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7532 final |= DREF_SSC1_ENABLE;
7533
7534 if (has_cpu_edp) {
7535 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7536 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7537 else
7538 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7539 } else
7540 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7541 } else if (using_ssc_source) {
7542 final |= DREF_SSC_SOURCE_ENABLE;
7543 final |= DREF_SSC1_ENABLE;
7544 }
7545
7546 if (final == val)
7547 return;
7548
7549 /* Always enable nonspread source */
7550 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7551
7552 if (has_ck505)
7553 val |= DREF_NONSPREAD_CK505_ENABLE;
7554 else
7555 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7556
7557 if (has_panel) {
7558 val &= ~DREF_SSC_SOURCE_MASK;
7559 val |= DREF_SSC_SOURCE_ENABLE;
7560
7561 /* SSC must be turned on before enabling the CPU output */
7562 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7563 DRM_DEBUG_KMS("Using SSC on panel\n");
7564 val |= DREF_SSC1_ENABLE;
7565 } else
7566 val &= ~DREF_SSC1_ENABLE;
7567
7568 /* Get SSC going before enabling the outputs */
7569 I915_WRITE(PCH_DREF_CONTROL, val);
7570 POSTING_READ(PCH_DREF_CONTROL);
7571 udelay(200);
7572
7573 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7574
7575 /* Enable CPU source on CPU attached eDP */
7576 if (has_cpu_edp) {
7577 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7578 DRM_DEBUG_KMS("Using SSC on eDP\n");
7579 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7580 } else
7581 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7582 } else
7583 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7584
7585 I915_WRITE(PCH_DREF_CONTROL, val);
7586 POSTING_READ(PCH_DREF_CONTROL);
7587 udelay(200);
7588 } else {
7589 DRM_DEBUG_KMS("Disabling CPU source output\n");
7590
7591 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7592
7593 /* Turn off CPU output */
7594 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7595
7596 I915_WRITE(PCH_DREF_CONTROL, val);
7597 POSTING_READ(PCH_DREF_CONTROL);
7598 udelay(200);
7599
7600 if (!using_ssc_source) {
7601 DRM_DEBUG_KMS("Disabling SSC source\n");
7602
7603 /* Turn off the SSC source */
7604 val &= ~DREF_SSC_SOURCE_MASK;
7605 val |= DREF_SSC_SOURCE_DISABLE;
7606
7607 /* Turn off SSC1 */
7608 val &= ~DREF_SSC1_ENABLE;
7609
7610 I915_WRITE(PCH_DREF_CONTROL, val);
7611 POSTING_READ(PCH_DREF_CONTROL);
7612 udelay(200);
7613 }
7614 }
7615
7616 BUG_ON(val != final);
7617 }
7618
7619 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7620 {
7621 uint32_t tmp;
7622
7623 tmp = I915_READ(SOUTH_CHICKEN2);
7624 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7625 I915_WRITE(SOUTH_CHICKEN2, tmp);
7626
7627 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7628 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7629 DRM_ERROR("FDI mPHY reset assert timeout\n");
7630
7631 tmp = I915_READ(SOUTH_CHICKEN2);
7632 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7633 I915_WRITE(SOUTH_CHICKEN2, tmp);
7634
7635 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7636 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7637 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7638 }
7639
7640 /* WaMPhyProgramming:hsw */
7641 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7642 {
7643 uint32_t tmp;
7644
7645 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7646 tmp &= ~(0xFF << 24);
7647 tmp |= (0x12 << 24);
7648 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7649
7650 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7651 tmp |= (1 << 11);
7652 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7653
7654 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7655 tmp |= (1 << 11);
7656 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7657
7658 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7659 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7660 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7661
7662 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7663 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7664 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7665
7666 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7667 tmp &= ~(7 << 13);
7668 tmp |= (5 << 13);
7669 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7670
7671 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7672 tmp &= ~(7 << 13);
7673 tmp |= (5 << 13);
7674 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7675
7676 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7677 tmp &= ~0xFF;
7678 tmp |= 0x1C;
7679 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7680
7681 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7682 tmp &= ~0xFF;
7683 tmp |= 0x1C;
7684 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7685
7686 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7687 tmp &= ~(0xFF << 16);
7688 tmp |= (0x1C << 16);
7689 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7690
7691 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7692 tmp &= ~(0xFF << 16);
7693 tmp |= (0x1C << 16);
7694 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7695
7696 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7697 tmp |= (1 << 27);
7698 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7699
7700 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7701 tmp |= (1 << 27);
7702 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7703
7704 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7705 tmp &= ~(0xF << 28);
7706 tmp |= (4 << 28);
7707 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7708
7709 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7710 tmp &= ~(0xF << 28);
7711 tmp |= (4 << 28);
7712 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7713 }
7714
7715 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7716 * Programming" based on the parameters passed:
7717 * - Sequence to enable CLKOUT_DP
7718 * - Sequence to enable CLKOUT_DP without spread
7719 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7720 */
7721 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7722 bool with_spread, bool with_fdi)
7723 {
7724 uint32_t reg, tmp;
7725
7726 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7727 with_spread = true;
7728 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7729 with_fdi, "LP PCH doesn't have FDI\n"))
7730 with_fdi = false;
7731
7732 mutex_lock(&dev_priv->sb_lock);
7733
7734 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7735 tmp &= ~SBI_SSCCTL_DISABLE;
7736 tmp |= SBI_SSCCTL_PATHALT;
7737 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7738
7739 udelay(24);
7740
7741 if (with_spread) {
7742 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7743 tmp &= ~SBI_SSCCTL_PATHALT;
7744 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7745
7746 if (with_fdi) {
7747 lpt_reset_fdi_mphy(dev_priv);
7748 lpt_program_fdi_mphy(dev_priv);
7749 }
7750 }
7751
7752 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7753 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7754 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7755 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7756
7757 mutex_unlock(&dev_priv->sb_lock);
7758 }
7759
7760 /* Sequence to disable CLKOUT_DP */
7761 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7762 {
7763 uint32_t reg, tmp;
7764
7765 mutex_lock(&dev_priv->sb_lock);
7766
7767 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7768 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7769 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7770 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7771
7772 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7773 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7774 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7775 tmp |= SBI_SSCCTL_PATHALT;
7776 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7777 udelay(32);
7778 }
7779 tmp |= SBI_SSCCTL_DISABLE;
7780 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7781 }
7782
7783 mutex_unlock(&dev_priv->sb_lock);
7784 }
7785
7786 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7787
7788 static const uint16_t sscdivintphase[] = {
7789 [BEND_IDX( 50)] = 0x3B23,
7790 [BEND_IDX( 45)] = 0x3B23,
7791 [BEND_IDX( 40)] = 0x3C23,
7792 [BEND_IDX( 35)] = 0x3C23,
7793 [BEND_IDX( 30)] = 0x3D23,
7794 [BEND_IDX( 25)] = 0x3D23,
7795 [BEND_IDX( 20)] = 0x3E23,
7796 [BEND_IDX( 15)] = 0x3E23,
7797 [BEND_IDX( 10)] = 0x3F23,
7798 [BEND_IDX( 5)] = 0x3F23,
7799 [BEND_IDX( 0)] = 0x0025,
7800 [BEND_IDX( -5)] = 0x0025,
7801 [BEND_IDX(-10)] = 0x0125,
7802 [BEND_IDX(-15)] = 0x0125,
7803 [BEND_IDX(-20)] = 0x0225,
7804 [BEND_IDX(-25)] = 0x0225,
7805 [BEND_IDX(-30)] = 0x0325,
7806 [BEND_IDX(-35)] = 0x0325,
7807 [BEND_IDX(-40)] = 0x0425,
7808 [BEND_IDX(-45)] = 0x0425,
7809 [BEND_IDX(-50)] = 0x0525,
7810 };
7811
7812 /*
7813 * Bend CLKOUT_DP
7814 * steps -50 to 50 inclusive, in steps of 5
7815 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7816 * change in clock period = -(steps / 10) * 5.787 ps
7817 */
7818 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
7819 {
7820 uint32_t tmp;
7821 int idx = BEND_IDX(steps);
7822
7823 if (WARN_ON(steps % 5 != 0))
7824 return;
7825
7826 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
7827 return;
7828
7829 mutex_lock(&dev_priv->sb_lock);
7830
7831 if (steps % 10 != 0)
7832 tmp = 0xAAAAAAAB;
7833 else
7834 tmp = 0x00000000;
7835 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
7836
7837 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
7838 tmp &= 0xffff0000;
7839 tmp |= sscdivintphase[idx];
7840 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
7841
7842 mutex_unlock(&dev_priv->sb_lock);
7843 }
7844
7845 #undef BEND_IDX
7846
7847 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
7848 {
7849 struct intel_encoder *encoder;
7850 bool has_vga = false;
7851
7852 for_each_intel_encoder(&dev_priv->drm, encoder) {
7853 switch (encoder->type) {
7854 case INTEL_OUTPUT_ANALOG:
7855 has_vga = true;
7856 break;
7857 default:
7858 break;
7859 }
7860 }
7861
7862 if (has_vga) {
7863 lpt_bend_clkout_dp(dev_priv, 0);
7864 lpt_enable_clkout_dp(dev_priv, true, true);
7865 } else {
7866 lpt_disable_clkout_dp(dev_priv);
7867 }
7868 }
7869
7870 /*
7871 * Initialize reference clocks when the driver loads
7872 */
7873 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
7874 {
7875 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
7876 ironlake_init_pch_refclk(dev_priv);
7877 else if (HAS_PCH_LPT(dev_priv))
7878 lpt_init_pch_refclk(dev_priv);
7879 }
7880
7881 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7882 {
7883 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
7884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7885 int pipe = intel_crtc->pipe;
7886 uint32_t val;
7887
7888 val = 0;
7889
7890 switch (intel_crtc->config->pipe_bpp) {
7891 case 18:
7892 val |= PIPECONF_6BPC;
7893 break;
7894 case 24:
7895 val |= PIPECONF_8BPC;
7896 break;
7897 case 30:
7898 val |= PIPECONF_10BPC;
7899 break;
7900 case 36:
7901 val |= PIPECONF_12BPC;
7902 break;
7903 default:
7904 /* Case prevented by intel_choose_pipe_bpp_dither. */
7905 BUG();
7906 }
7907
7908 if (intel_crtc->config->dither)
7909 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7910
7911 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7912 val |= PIPECONF_INTERLACED_ILK;
7913 else
7914 val |= PIPECONF_PROGRESSIVE;
7915
7916 if (intel_crtc->config->limited_color_range)
7917 val |= PIPECONF_COLOR_RANGE_SELECT;
7918
7919 I915_WRITE(PIPECONF(pipe), val);
7920 POSTING_READ(PIPECONF(pipe));
7921 }
7922
7923 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7924 {
7925 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
7926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7927 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7928 u32 val = 0;
7929
7930 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
7931 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7932
7933 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7934 val |= PIPECONF_INTERLACED_ILK;
7935 else
7936 val |= PIPECONF_PROGRESSIVE;
7937
7938 I915_WRITE(PIPECONF(cpu_transcoder), val);
7939 POSTING_READ(PIPECONF(cpu_transcoder));
7940 }
7941
7942 static void haswell_set_pipemisc(struct drm_crtc *crtc)
7943 {
7944 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
7945 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7946 struct intel_crtc_state *config = intel_crtc->config;
7947
7948 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
7949 u32 val = 0;
7950
7951 switch (intel_crtc->config->pipe_bpp) {
7952 case 18:
7953 val |= PIPEMISC_DITHER_6_BPC;
7954 break;
7955 case 24:
7956 val |= PIPEMISC_DITHER_8_BPC;
7957 break;
7958 case 30:
7959 val |= PIPEMISC_DITHER_10_BPC;
7960 break;
7961 case 36:
7962 val |= PIPEMISC_DITHER_12_BPC;
7963 break;
7964 default:
7965 /* Case prevented by pipe_config_set_bpp. */
7966 BUG();
7967 }
7968
7969 if (intel_crtc->config->dither)
7970 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7971
7972 if (config->ycbcr420) {
7973 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV |
7974 PIPEMISC_YUV420_ENABLE |
7975 PIPEMISC_YUV420_MODE_FULL_BLEND;
7976 }
7977
7978 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
7979 }
7980 }
7981
7982 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7983 {
7984 /*
7985 * Account for spread spectrum to avoid
7986 * oversubscribing the link. Max center spread
7987 * is 2.5%; use 5% for safety's sake.
7988 */
7989 u32 bps = target_clock * bpp * 21 / 20;
7990 return DIV_ROUND_UP(bps, link_bw * 8);
7991 }
7992
7993 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7994 {
7995 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7996 }
7997
7998 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7999 struct intel_crtc_state *crtc_state,
8000 struct dpll *reduced_clock)
8001 {
8002 struct drm_crtc *crtc = &intel_crtc->base;
8003 struct drm_device *dev = crtc->dev;
8004 struct drm_i915_private *dev_priv = to_i915(dev);
8005 u32 dpll, fp, fp2;
8006 int factor;
8007
8008 /* Enable autotuning of the PLL clock (if permissible) */
8009 factor = 21;
8010 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8011 if ((intel_panel_use_ssc(dev_priv) &&
8012 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8013 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8014 factor = 25;
8015 } else if (crtc_state->sdvo_tv_clock)
8016 factor = 20;
8017
8018 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8019
8020 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8021 fp |= FP_CB_TUNE;
8022
8023 if (reduced_clock) {
8024 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8025
8026 if (reduced_clock->m < factor * reduced_clock->n)
8027 fp2 |= FP_CB_TUNE;
8028 } else {
8029 fp2 = fp;
8030 }
8031
8032 dpll = 0;
8033
8034 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8035 dpll |= DPLLB_MODE_LVDS;
8036 else
8037 dpll |= DPLLB_MODE_DAC_SERIAL;
8038
8039 dpll |= (crtc_state->pixel_multiplier - 1)
8040 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8041
8042 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8043 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8044 dpll |= DPLL_SDVO_HIGH_SPEED;
8045
8046 if (intel_crtc_has_dp_encoder(crtc_state))
8047 dpll |= DPLL_SDVO_HIGH_SPEED;
8048
8049 /*
8050 * The high speed IO clock is only really required for
8051 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8052 * possible to share the DPLL between CRT and HDMI. Enabling
8053 * the clock needlessly does no real harm, except use up a
8054 * bit of power potentially.
8055 *
8056 * We'll limit this to IVB with 3 pipes, since it has only two
8057 * DPLLs and so DPLL sharing is the only way to get three pipes
8058 * driving PCH ports at the same time. On SNB we could do this,
8059 * and potentially avoid enabling the second DPLL, but it's not
8060 * clear if it''s a win or loss power wise. No point in doing
8061 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8062 */
8063 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8064 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8065 dpll |= DPLL_SDVO_HIGH_SPEED;
8066
8067 /* compute bitmask from p1 value */
8068 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8069 /* also FPA1 */
8070 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8071
8072 switch (crtc_state->dpll.p2) {
8073 case 5:
8074 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8075 break;
8076 case 7:
8077 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8078 break;
8079 case 10:
8080 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8081 break;
8082 case 14:
8083 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8084 break;
8085 }
8086
8087 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8088 intel_panel_use_ssc(dev_priv))
8089 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8090 else
8091 dpll |= PLL_REF_INPUT_DREFCLK;
8092
8093 dpll |= DPLL_VCO_ENABLE;
8094
8095 crtc_state->dpll_hw_state.dpll = dpll;
8096 crtc_state->dpll_hw_state.fp0 = fp;
8097 crtc_state->dpll_hw_state.fp1 = fp2;
8098 }
8099
8100 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8101 struct intel_crtc_state *crtc_state)
8102 {
8103 struct drm_device *dev = crtc->base.dev;
8104 struct drm_i915_private *dev_priv = to_i915(dev);
8105 const struct intel_limit *limit;
8106 int refclk = 120000;
8107
8108 memset(&crtc_state->dpll_hw_state, 0,
8109 sizeof(crtc_state->dpll_hw_state));
8110
8111 crtc->lowfreq_avail = false;
8112
8113 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8114 if (!crtc_state->has_pch_encoder)
8115 return 0;
8116
8117 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8118 if (intel_panel_use_ssc(dev_priv)) {
8119 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8120 dev_priv->vbt.lvds_ssc_freq);
8121 refclk = dev_priv->vbt.lvds_ssc_freq;
8122 }
8123
8124 if (intel_is_dual_link_lvds(dev)) {
8125 if (refclk == 100000)
8126 limit = &intel_limits_ironlake_dual_lvds_100m;
8127 else
8128 limit = &intel_limits_ironlake_dual_lvds;
8129 } else {
8130 if (refclk == 100000)
8131 limit = &intel_limits_ironlake_single_lvds_100m;
8132 else
8133 limit = &intel_limits_ironlake_single_lvds;
8134 }
8135 } else {
8136 limit = &intel_limits_ironlake_dac;
8137 }
8138
8139 if (!crtc_state->clock_set &&
8140 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8141 refclk, NULL, &crtc_state->dpll)) {
8142 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8143 return -EINVAL;
8144 }
8145
8146 ironlake_compute_dpll(crtc, crtc_state, NULL);
8147
8148 if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8149 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8150 pipe_name(crtc->pipe));
8151 return -EINVAL;
8152 }
8153
8154 return 0;
8155 }
8156
8157 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8158 struct intel_link_m_n *m_n)
8159 {
8160 struct drm_device *dev = crtc->base.dev;
8161 struct drm_i915_private *dev_priv = to_i915(dev);
8162 enum pipe pipe = crtc->pipe;
8163
8164 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8165 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8166 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8167 & ~TU_SIZE_MASK;
8168 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8169 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8170 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8171 }
8172
8173 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8174 enum transcoder transcoder,
8175 struct intel_link_m_n *m_n,
8176 struct intel_link_m_n *m2_n2)
8177 {
8178 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8179 enum pipe pipe = crtc->pipe;
8180
8181 if (INTEL_GEN(dev_priv) >= 5) {
8182 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8183 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8184 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8185 & ~TU_SIZE_MASK;
8186 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8187 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8188 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8189 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8190 * gen < 8) and if DRRS is supported (to make sure the
8191 * registers are not unnecessarily read).
8192 */
8193 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8194 crtc->config->has_drrs) {
8195 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8196 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8197 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8198 & ~TU_SIZE_MASK;
8199 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8200 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8201 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8202 }
8203 } else {
8204 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8205 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8206 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8207 & ~TU_SIZE_MASK;
8208 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8209 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8210 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8211 }
8212 }
8213
8214 void intel_dp_get_m_n(struct intel_crtc *crtc,
8215 struct intel_crtc_state *pipe_config)
8216 {
8217 if (pipe_config->has_pch_encoder)
8218 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8219 else
8220 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8221 &pipe_config->dp_m_n,
8222 &pipe_config->dp_m2_n2);
8223 }
8224
8225 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8226 struct intel_crtc_state *pipe_config)
8227 {
8228 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8229 &pipe_config->fdi_m_n, NULL);
8230 }
8231
8232 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8233 struct intel_crtc_state *pipe_config)
8234 {
8235 struct drm_device *dev = crtc->base.dev;
8236 struct drm_i915_private *dev_priv = to_i915(dev);
8237 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8238 uint32_t ps_ctrl = 0;
8239 int id = -1;
8240 int i;
8241
8242 /* find scaler attached to this pipe */
8243 for (i = 0; i < crtc->num_scalers; i++) {
8244 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8245 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8246 id = i;
8247 pipe_config->pch_pfit.enabled = true;
8248 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8249 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8250 break;
8251 }
8252 }
8253
8254 scaler_state->scaler_id = id;
8255 if (id >= 0) {
8256 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8257 } else {
8258 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8259 }
8260 }
8261
8262 static void
8263 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8264 struct intel_initial_plane_config *plane_config)
8265 {
8266 struct drm_device *dev = crtc->base.dev;
8267 struct drm_i915_private *dev_priv = to_i915(dev);
8268 u32 val, base, offset, stride_mult, tiling;
8269 int pipe = crtc->pipe;
8270 int fourcc, pixel_format;
8271 unsigned int aligned_height;
8272 struct drm_framebuffer *fb;
8273 struct intel_framebuffer *intel_fb;
8274
8275 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8276 if (!intel_fb) {
8277 DRM_DEBUG_KMS("failed to alloc fb\n");
8278 return;
8279 }
8280
8281 fb = &intel_fb->base;
8282
8283 fb->dev = dev;
8284
8285 val = I915_READ(PLANE_CTL(pipe, 0));
8286 if (!(val & PLANE_CTL_ENABLE))
8287 goto error;
8288
8289 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8290 fourcc = skl_format_to_fourcc(pixel_format,
8291 val & PLANE_CTL_ORDER_RGBX,
8292 val & PLANE_CTL_ALPHA_MASK);
8293 fb->format = drm_format_info(fourcc);
8294
8295 tiling = val & PLANE_CTL_TILED_MASK;
8296 switch (tiling) {
8297 case PLANE_CTL_TILED_LINEAR:
8298 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8299 break;
8300 case PLANE_CTL_TILED_X:
8301 plane_config->tiling = I915_TILING_X;
8302 fb->modifier = I915_FORMAT_MOD_X_TILED;
8303 break;
8304 case PLANE_CTL_TILED_Y:
8305 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8306 break;
8307 case PLANE_CTL_TILED_YF:
8308 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8309 break;
8310 default:
8311 MISSING_CASE(tiling);
8312 goto error;
8313 }
8314
8315 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8316 plane_config->base = base;
8317
8318 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8319
8320 val = I915_READ(PLANE_SIZE(pipe, 0));
8321 fb->height = ((val >> 16) & 0xfff) + 1;
8322 fb->width = ((val >> 0) & 0x1fff) + 1;
8323
8324 val = I915_READ(PLANE_STRIDE(pipe, 0));
8325 stride_mult = intel_fb_stride_alignment(fb, 0);
8326 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8327
8328 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8329
8330 plane_config->size = fb->pitches[0] * aligned_height;
8331
8332 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8333 pipe_name(pipe), fb->width, fb->height,
8334 fb->format->cpp[0] * 8, base, fb->pitches[0],
8335 plane_config->size);
8336
8337 plane_config->fb = intel_fb;
8338 return;
8339
8340 error:
8341 kfree(intel_fb);
8342 }
8343
8344 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8345 struct intel_crtc_state *pipe_config)
8346 {
8347 struct drm_device *dev = crtc->base.dev;
8348 struct drm_i915_private *dev_priv = to_i915(dev);
8349 uint32_t tmp;
8350
8351 tmp = I915_READ(PF_CTL(crtc->pipe));
8352
8353 if (tmp & PF_ENABLE) {
8354 pipe_config->pch_pfit.enabled = true;
8355 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8356 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8357
8358 /* We currently do not free assignements of panel fitters on
8359 * ivb/hsw (since we don't use the higher upscaling modes which
8360 * differentiates them) so just WARN about this case for now. */
8361 if (IS_GEN7(dev_priv)) {
8362 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8363 PF_PIPE_SEL_IVB(crtc->pipe));
8364 }
8365 }
8366 }
8367
8368 static void
8369 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8370 struct intel_initial_plane_config *plane_config)
8371 {
8372 struct drm_device *dev = crtc->base.dev;
8373 struct drm_i915_private *dev_priv = to_i915(dev);
8374 u32 val, base, offset;
8375 int pipe = crtc->pipe;
8376 int fourcc, pixel_format;
8377 unsigned int aligned_height;
8378 struct drm_framebuffer *fb;
8379 struct intel_framebuffer *intel_fb;
8380
8381 val = I915_READ(DSPCNTR(pipe));
8382 if (!(val & DISPLAY_PLANE_ENABLE))
8383 return;
8384
8385 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8386 if (!intel_fb) {
8387 DRM_DEBUG_KMS("failed to alloc fb\n");
8388 return;
8389 }
8390
8391 fb = &intel_fb->base;
8392
8393 fb->dev = dev;
8394
8395 if (INTEL_GEN(dev_priv) >= 4) {
8396 if (val & DISPPLANE_TILED) {
8397 plane_config->tiling = I915_TILING_X;
8398 fb->modifier = I915_FORMAT_MOD_X_TILED;
8399 }
8400 }
8401
8402 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8403 fourcc = i9xx_format_to_fourcc(pixel_format);
8404 fb->format = drm_format_info(fourcc);
8405
8406 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8407 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8408 offset = I915_READ(DSPOFFSET(pipe));
8409 } else {
8410 if (plane_config->tiling)
8411 offset = I915_READ(DSPTILEOFF(pipe));
8412 else
8413 offset = I915_READ(DSPLINOFF(pipe));
8414 }
8415 plane_config->base = base;
8416
8417 val = I915_READ(PIPESRC(pipe));
8418 fb->width = ((val >> 16) & 0xfff) + 1;
8419 fb->height = ((val >> 0) & 0xfff) + 1;
8420
8421 val = I915_READ(DSPSTRIDE(pipe));
8422 fb->pitches[0] = val & 0xffffffc0;
8423
8424 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8425
8426 plane_config->size = fb->pitches[0] * aligned_height;
8427
8428 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8429 pipe_name(pipe), fb->width, fb->height,
8430 fb->format->cpp[0] * 8, base, fb->pitches[0],
8431 plane_config->size);
8432
8433 plane_config->fb = intel_fb;
8434 }
8435
8436 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8437 struct intel_crtc_state *pipe_config)
8438 {
8439 struct drm_device *dev = crtc->base.dev;
8440 struct drm_i915_private *dev_priv = to_i915(dev);
8441 enum intel_display_power_domain power_domain;
8442 uint32_t tmp;
8443 bool ret;
8444
8445 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8446 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8447 return false;
8448
8449 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8450 pipe_config->shared_dpll = NULL;
8451
8452 ret = false;
8453 tmp = I915_READ(PIPECONF(crtc->pipe));
8454 if (!(tmp & PIPECONF_ENABLE))
8455 goto out;
8456
8457 switch (tmp & PIPECONF_BPC_MASK) {
8458 case PIPECONF_6BPC:
8459 pipe_config->pipe_bpp = 18;
8460 break;
8461 case PIPECONF_8BPC:
8462 pipe_config->pipe_bpp = 24;
8463 break;
8464 case PIPECONF_10BPC:
8465 pipe_config->pipe_bpp = 30;
8466 break;
8467 case PIPECONF_12BPC:
8468 pipe_config->pipe_bpp = 36;
8469 break;
8470 default:
8471 break;
8472 }
8473
8474 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8475 pipe_config->limited_color_range = true;
8476
8477 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8478 struct intel_shared_dpll *pll;
8479 enum intel_dpll_id pll_id;
8480
8481 pipe_config->has_pch_encoder = true;
8482
8483 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8484 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8485 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8486
8487 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8488
8489 if (HAS_PCH_IBX(dev_priv)) {
8490 /*
8491 * The pipe->pch transcoder and pch transcoder->pll
8492 * mapping is fixed.
8493 */
8494 pll_id = (enum intel_dpll_id) crtc->pipe;
8495 } else {
8496 tmp = I915_READ(PCH_DPLL_SEL);
8497 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8498 pll_id = DPLL_ID_PCH_PLL_B;
8499 else
8500 pll_id= DPLL_ID_PCH_PLL_A;
8501 }
8502
8503 pipe_config->shared_dpll =
8504 intel_get_shared_dpll_by_id(dev_priv, pll_id);
8505 pll = pipe_config->shared_dpll;
8506
8507 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8508 &pipe_config->dpll_hw_state));
8509
8510 tmp = pipe_config->dpll_hw_state.dpll;
8511 pipe_config->pixel_multiplier =
8512 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8513 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8514
8515 ironlake_pch_clock_get(crtc, pipe_config);
8516 } else {
8517 pipe_config->pixel_multiplier = 1;
8518 }
8519
8520 intel_get_pipe_timings(crtc, pipe_config);
8521 intel_get_pipe_src_size(crtc, pipe_config);
8522
8523 ironlake_get_pfit_config(crtc, pipe_config);
8524
8525 ret = true;
8526
8527 out:
8528 intel_display_power_put(dev_priv, power_domain);
8529
8530 return ret;
8531 }
8532
8533 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8534 {
8535 struct drm_device *dev = &dev_priv->drm;
8536 struct intel_crtc *crtc;
8537
8538 for_each_intel_crtc(dev, crtc)
8539 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8540 pipe_name(crtc->pipe));
8541
8542 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8543 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8544 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8545 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8546 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8547 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8548 "CPU PWM1 enabled\n");
8549 if (IS_HASWELL(dev_priv))
8550 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8551 "CPU PWM2 enabled\n");
8552 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8553 "PCH PWM1 enabled\n");
8554 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8555 "Utility pin enabled\n");
8556 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8557
8558 /*
8559 * In theory we can still leave IRQs enabled, as long as only the HPD
8560 * interrupts remain enabled. We used to check for that, but since it's
8561 * gen-specific and since we only disable LCPLL after we fully disable
8562 * the interrupts, the check below should be enough.
8563 */
8564 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8565 }
8566
8567 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8568 {
8569 if (IS_HASWELL(dev_priv))
8570 return I915_READ(D_COMP_HSW);
8571 else
8572 return I915_READ(D_COMP_BDW);
8573 }
8574
8575 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8576 {
8577 if (IS_HASWELL(dev_priv)) {
8578 mutex_lock(&dev_priv->rps.hw_lock);
8579 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8580 val))
8581 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8582 mutex_unlock(&dev_priv->rps.hw_lock);
8583 } else {
8584 I915_WRITE(D_COMP_BDW, val);
8585 POSTING_READ(D_COMP_BDW);
8586 }
8587 }
8588
8589 /*
8590 * This function implements pieces of two sequences from BSpec:
8591 * - Sequence for display software to disable LCPLL
8592 * - Sequence for display software to allow package C8+
8593 * The steps implemented here are just the steps that actually touch the LCPLL
8594 * register. Callers should take care of disabling all the display engine
8595 * functions, doing the mode unset, fixing interrupts, etc.
8596 */
8597 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8598 bool switch_to_fclk, bool allow_power_down)
8599 {
8600 uint32_t val;
8601
8602 assert_can_disable_lcpll(dev_priv);
8603
8604 val = I915_READ(LCPLL_CTL);
8605
8606 if (switch_to_fclk) {
8607 val |= LCPLL_CD_SOURCE_FCLK;
8608 I915_WRITE(LCPLL_CTL, val);
8609
8610 if (wait_for_us(I915_READ(LCPLL_CTL) &
8611 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8612 DRM_ERROR("Switching to FCLK failed\n");
8613
8614 val = I915_READ(LCPLL_CTL);
8615 }
8616
8617 val |= LCPLL_PLL_DISABLE;
8618 I915_WRITE(LCPLL_CTL, val);
8619 POSTING_READ(LCPLL_CTL);
8620
8621 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8622 DRM_ERROR("LCPLL still locked\n");
8623
8624 val = hsw_read_dcomp(dev_priv);
8625 val |= D_COMP_COMP_DISABLE;
8626 hsw_write_dcomp(dev_priv, val);
8627 ndelay(100);
8628
8629 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8630 1))
8631 DRM_ERROR("D_COMP RCOMP still in progress\n");
8632
8633 if (allow_power_down) {
8634 val = I915_READ(LCPLL_CTL);
8635 val |= LCPLL_POWER_DOWN_ALLOW;
8636 I915_WRITE(LCPLL_CTL, val);
8637 POSTING_READ(LCPLL_CTL);
8638 }
8639 }
8640
8641 /*
8642 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8643 * source.
8644 */
8645 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8646 {
8647 uint32_t val;
8648
8649 val = I915_READ(LCPLL_CTL);
8650
8651 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8652 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8653 return;
8654
8655 /*
8656 * Make sure we're not on PC8 state before disabling PC8, otherwise
8657 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8658 */
8659 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8660
8661 if (val & LCPLL_POWER_DOWN_ALLOW) {
8662 val &= ~LCPLL_POWER_DOWN_ALLOW;
8663 I915_WRITE(LCPLL_CTL, val);
8664 POSTING_READ(LCPLL_CTL);
8665 }
8666
8667 val = hsw_read_dcomp(dev_priv);
8668 val |= D_COMP_COMP_FORCE;
8669 val &= ~D_COMP_COMP_DISABLE;
8670 hsw_write_dcomp(dev_priv, val);
8671
8672 val = I915_READ(LCPLL_CTL);
8673 val &= ~LCPLL_PLL_DISABLE;
8674 I915_WRITE(LCPLL_CTL, val);
8675
8676 if (intel_wait_for_register(dev_priv,
8677 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8678 5))
8679 DRM_ERROR("LCPLL not locked yet\n");
8680
8681 if (val & LCPLL_CD_SOURCE_FCLK) {
8682 val = I915_READ(LCPLL_CTL);
8683 val &= ~LCPLL_CD_SOURCE_FCLK;
8684 I915_WRITE(LCPLL_CTL, val);
8685
8686 if (wait_for_us((I915_READ(LCPLL_CTL) &
8687 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8688 DRM_ERROR("Switching back to LCPLL failed\n");
8689 }
8690
8691 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8692 intel_update_cdclk(dev_priv);
8693 }
8694
8695 /*
8696 * Package states C8 and deeper are really deep PC states that can only be
8697 * reached when all the devices on the system allow it, so even if the graphics
8698 * device allows PC8+, it doesn't mean the system will actually get to these
8699 * states. Our driver only allows PC8+ when going into runtime PM.
8700 *
8701 * The requirements for PC8+ are that all the outputs are disabled, the power
8702 * well is disabled and most interrupts are disabled, and these are also
8703 * requirements for runtime PM. When these conditions are met, we manually do
8704 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8705 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8706 * hang the machine.
8707 *
8708 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8709 * the state of some registers, so when we come back from PC8+ we need to
8710 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8711 * need to take care of the registers kept by RC6. Notice that this happens even
8712 * if we don't put the device in PCI D3 state (which is what currently happens
8713 * because of the runtime PM support).
8714 *
8715 * For more, read "Display Sequences for Package C8" on the hardware
8716 * documentation.
8717 */
8718 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8719 {
8720 uint32_t val;
8721
8722 DRM_DEBUG_KMS("Enabling package C8+\n");
8723
8724 if (HAS_PCH_LPT_LP(dev_priv)) {
8725 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8726 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8727 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8728 }
8729
8730 lpt_disable_clkout_dp(dev_priv);
8731 hsw_disable_lcpll(dev_priv, true, true);
8732 }
8733
8734 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8735 {
8736 uint32_t val;
8737
8738 DRM_DEBUG_KMS("Disabling package C8+\n");
8739
8740 hsw_restore_lcpll(dev_priv);
8741 lpt_init_pch_refclk(dev_priv);
8742
8743 if (HAS_PCH_LPT_LP(dev_priv)) {
8744 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8745 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8746 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8747 }
8748 }
8749
8750 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8751 struct intel_crtc_state *crtc_state)
8752 {
8753 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8754 struct intel_encoder *encoder =
8755 intel_ddi_get_crtc_new_encoder(crtc_state);
8756
8757 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
8758 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8759 pipe_name(crtc->pipe));
8760 return -EINVAL;
8761 }
8762 }
8763
8764 crtc->lowfreq_avail = false;
8765
8766 return 0;
8767 }
8768
8769 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
8770 enum port port,
8771 struct intel_crtc_state *pipe_config)
8772 {
8773 enum intel_dpll_id id;
8774 u32 temp;
8775
8776 temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
8777 id = temp >> (port * 2);
8778
8779 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
8780 return;
8781
8782 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8783 }
8784
8785 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8786 enum port port,
8787 struct intel_crtc_state *pipe_config)
8788 {
8789 enum intel_dpll_id id;
8790
8791 switch (port) {
8792 case PORT_A:
8793 id = DPLL_ID_SKL_DPLL0;
8794 break;
8795 case PORT_B:
8796 id = DPLL_ID_SKL_DPLL1;
8797 break;
8798 case PORT_C:
8799 id = DPLL_ID_SKL_DPLL2;
8800 break;
8801 default:
8802 DRM_ERROR("Incorrect port type\n");
8803 return;
8804 }
8805
8806 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8807 }
8808
8809 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8810 enum port port,
8811 struct intel_crtc_state *pipe_config)
8812 {
8813 enum intel_dpll_id id;
8814 u32 temp;
8815
8816 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8817 id = temp >> (port * 3 + 1);
8818
8819 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
8820 return;
8821
8822 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8823 }
8824
8825 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8826 enum port port,
8827 struct intel_crtc_state *pipe_config)
8828 {
8829 enum intel_dpll_id id;
8830 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8831
8832 switch (ddi_pll_sel) {
8833 case PORT_CLK_SEL_WRPLL1:
8834 id = DPLL_ID_WRPLL1;
8835 break;
8836 case PORT_CLK_SEL_WRPLL2:
8837 id = DPLL_ID_WRPLL2;
8838 break;
8839 case PORT_CLK_SEL_SPLL:
8840 id = DPLL_ID_SPLL;
8841 break;
8842 case PORT_CLK_SEL_LCPLL_810:
8843 id = DPLL_ID_LCPLL_810;
8844 break;
8845 case PORT_CLK_SEL_LCPLL_1350:
8846 id = DPLL_ID_LCPLL_1350;
8847 break;
8848 case PORT_CLK_SEL_LCPLL_2700:
8849 id = DPLL_ID_LCPLL_2700;
8850 break;
8851 default:
8852 MISSING_CASE(ddi_pll_sel);
8853 /* fall through */
8854 case PORT_CLK_SEL_NONE:
8855 return;
8856 }
8857
8858 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8859 }
8860
8861 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
8862 struct intel_crtc_state *pipe_config,
8863 u64 *power_domain_mask)
8864 {
8865 struct drm_device *dev = crtc->base.dev;
8866 struct drm_i915_private *dev_priv = to_i915(dev);
8867 enum intel_display_power_domain power_domain;
8868 u32 tmp;
8869
8870 /*
8871 * The pipe->transcoder mapping is fixed with the exception of the eDP
8872 * transcoder handled below.
8873 */
8874 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8875
8876 /*
8877 * XXX: Do intel_display_power_get_if_enabled before reading this (for
8878 * consistency and less surprising code; it's in always on power).
8879 */
8880 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8881 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8882 enum pipe trans_edp_pipe;
8883 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8884 default:
8885 WARN(1, "unknown pipe linked to edp transcoder\n");
8886 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8887 case TRANS_DDI_EDP_INPUT_A_ON:
8888 trans_edp_pipe = PIPE_A;
8889 break;
8890 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8891 trans_edp_pipe = PIPE_B;
8892 break;
8893 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8894 trans_edp_pipe = PIPE_C;
8895 break;
8896 }
8897
8898 if (trans_edp_pipe == crtc->pipe)
8899 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8900 }
8901
8902 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
8903 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8904 return false;
8905 *power_domain_mask |= BIT_ULL(power_domain);
8906
8907 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8908
8909 return tmp & PIPECONF_ENABLE;
8910 }
8911
8912 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
8913 struct intel_crtc_state *pipe_config,
8914 u64 *power_domain_mask)
8915 {
8916 struct drm_device *dev = crtc->base.dev;
8917 struct drm_i915_private *dev_priv = to_i915(dev);
8918 enum intel_display_power_domain power_domain;
8919 enum port port;
8920 enum transcoder cpu_transcoder;
8921 u32 tmp;
8922
8923 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
8924 if (port == PORT_A)
8925 cpu_transcoder = TRANSCODER_DSI_A;
8926 else
8927 cpu_transcoder = TRANSCODER_DSI_C;
8928
8929 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
8930 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8931 continue;
8932 *power_domain_mask |= BIT_ULL(power_domain);
8933
8934 /*
8935 * The PLL needs to be enabled with a valid divider
8936 * configuration, otherwise accessing DSI registers will hang
8937 * the machine. See BSpec North Display Engine
8938 * registers/MIPI[BXT]. We can break out here early, since we
8939 * need the same DSI PLL to be enabled for both DSI ports.
8940 */
8941 if (!intel_dsi_pll_is_enabled(dev_priv))
8942 break;
8943
8944 /* XXX: this works for video mode only */
8945 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
8946 if (!(tmp & DPI_ENABLE))
8947 continue;
8948
8949 tmp = I915_READ(MIPI_CTRL(port));
8950 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
8951 continue;
8952
8953 pipe_config->cpu_transcoder = cpu_transcoder;
8954 break;
8955 }
8956
8957 return transcoder_is_dsi(pipe_config->cpu_transcoder);
8958 }
8959
8960 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8961 struct intel_crtc_state *pipe_config)
8962 {
8963 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8964 struct intel_shared_dpll *pll;
8965 enum port port;
8966 uint32_t tmp;
8967
8968 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8969
8970 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8971
8972 if (IS_CANNONLAKE(dev_priv))
8973 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
8974 else if (IS_GEN9_BC(dev_priv))
8975 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8976 else if (IS_GEN9_LP(dev_priv))
8977 bxt_get_ddi_pll(dev_priv, port, pipe_config);
8978 else
8979 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8980
8981 pll = pipe_config->shared_dpll;
8982 if (pll) {
8983 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8984 &pipe_config->dpll_hw_state));
8985 }
8986
8987 /*
8988 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8989 * DDI E. So just check whether this pipe is wired to DDI E and whether
8990 * the PCH transcoder is on.
8991 */
8992 if (INTEL_GEN(dev_priv) < 9 &&
8993 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8994 pipe_config->has_pch_encoder = true;
8995
8996 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8997 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8998 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8999
9000 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9001 }
9002 }
9003
9004 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9005 struct intel_crtc_state *pipe_config)
9006 {
9007 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9008 enum intel_display_power_domain power_domain;
9009 u64 power_domain_mask;
9010 bool active;
9011
9012 intel_crtc_init_scalers(crtc, pipe_config);
9013
9014 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9015 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9016 return false;
9017 power_domain_mask = BIT_ULL(power_domain);
9018
9019 pipe_config->shared_dpll = NULL;
9020
9021 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9022
9023 if (IS_GEN9_LP(dev_priv) &&
9024 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9025 WARN_ON(active);
9026 active = true;
9027 }
9028
9029 if (!active)
9030 goto out;
9031
9032 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9033 haswell_get_ddi_port_state(crtc, pipe_config);
9034 intel_get_pipe_timings(crtc, pipe_config);
9035 }
9036
9037 intel_get_pipe_src_size(crtc, pipe_config);
9038
9039 pipe_config->gamma_mode =
9040 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9041
9042 if (IS_BROADWELL(dev_priv) || dev_priv->info.gen >= 9) {
9043 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
9044 bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
9045
9046 if (IS_GEMINILAKE(dev_priv) || dev_priv->info.gen >= 10) {
9047 bool blend_mode_420 = tmp &
9048 PIPEMISC_YUV420_MODE_FULL_BLEND;
9049
9050 pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE;
9051 if (pipe_config->ycbcr420 != clrspace_yuv ||
9052 pipe_config->ycbcr420 != blend_mode_420)
9053 DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp);
9054 } else if (clrspace_yuv) {
9055 DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n");
9056 }
9057 }
9058
9059 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9060 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9061 power_domain_mask |= BIT_ULL(power_domain);
9062 if (INTEL_GEN(dev_priv) >= 9)
9063 skylake_get_pfit_config(crtc, pipe_config);
9064 else
9065 ironlake_get_pfit_config(crtc, pipe_config);
9066 }
9067
9068 if (IS_HASWELL(dev_priv))
9069 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9070 (I915_READ(IPS_CTL) & IPS_ENABLE);
9071
9072 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9073 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9074 pipe_config->pixel_multiplier =
9075 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9076 } else {
9077 pipe_config->pixel_multiplier = 1;
9078 }
9079
9080 out:
9081 for_each_power_domain(power_domain, power_domain_mask)
9082 intel_display_power_put(dev_priv, power_domain);
9083
9084 return active;
9085 }
9086
9087 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9088 {
9089 struct drm_i915_private *dev_priv =
9090 to_i915(plane_state->base.plane->dev);
9091 const struct drm_framebuffer *fb = plane_state->base.fb;
9092 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9093 u32 base;
9094
9095 if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9096 base = obj->phys_handle->busaddr;
9097 else
9098 base = intel_plane_ggtt_offset(plane_state);
9099
9100 base += plane_state->main.offset;
9101
9102 /* ILK+ do this automagically */
9103 if (HAS_GMCH_DISPLAY(dev_priv) &&
9104 plane_state->base.rotation & DRM_MODE_ROTATE_180)
9105 base += (plane_state->base.crtc_h *
9106 plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9107
9108 return base;
9109 }
9110
9111 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9112 {
9113 int x = plane_state->base.crtc_x;
9114 int y = plane_state->base.crtc_y;
9115 u32 pos = 0;
9116
9117 if (x < 0) {
9118 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9119 x = -x;
9120 }
9121 pos |= x << CURSOR_X_SHIFT;
9122
9123 if (y < 0) {
9124 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9125 y = -y;
9126 }
9127 pos |= y << CURSOR_Y_SHIFT;
9128
9129 return pos;
9130 }
9131
9132 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9133 {
9134 const struct drm_mode_config *config =
9135 &plane_state->base.plane->dev->mode_config;
9136 int width = plane_state->base.crtc_w;
9137 int height = plane_state->base.crtc_h;
9138
9139 return width > 0 && width <= config->cursor_width &&
9140 height > 0 && height <= config->cursor_height;
9141 }
9142
9143 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9144 struct intel_plane_state *plane_state)
9145 {
9146 const struct drm_framebuffer *fb = plane_state->base.fb;
9147 int src_x, src_y;
9148 u32 offset;
9149 int ret;
9150
9151 ret = drm_plane_helper_check_state(&plane_state->base,
9152 &plane_state->clip,
9153 DRM_PLANE_HELPER_NO_SCALING,
9154 DRM_PLANE_HELPER_NO_SCALING,
9155 true, true);
9156 if (ret)
9157 return ret;
9158
9159 if (!fb)
9160 return 0;
9161
9162 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9163 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9164 return -EINVAL;
9165 }
9166
9167 src_x = plane_state->base.src_x >> 16;
9168 src_y = plane_state->base.src_y >> 16;
9169
9170 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9171 offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9172
9173 if (src_x != 0 || src_y != 0) {
9174 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9175 return -EINVAL;
9176 }
9177
9178 plane_state->main.offset = offset;
9179
9180 return 0;
9181 }
9182
9183 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9184 const struct intel_plane_state *plane_state)
9185 {
9186 const struct drm_framebuffer *fb = plane_state->base.fb;
9187
9188 return CURSOR_ENABLE |
9189 CURSOR_GAMMA_ENABLE |
9190 CURSOR_FORMAT_ARGB |
9191 CURSOR_STRIDE(fb->pitches[0]);
9192 }
9193
9194 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9195 {
9196 int width = plane_state->base.crtc_w;
9197
9198 /*
9199 * 845g/865g are only limited by the width of their cursors,
9200 * the height is arbitrary up to the precision of the register.
9201 */
9202 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9203 }
9204
9205 static int i845_check_cursor(struct intel_plane *plane,
9206 struct intel_crtc_state *crtc_state,
9207 struct intel_plane_state *plane_state)
9208 {
9209 const struct drm_framebuffer *fb = plane_state->base.fb;
9210 int ret;
9211
9212 ret = intel_check_cursor(crtc_state, plane_state);
9213 if (ret)
9214 return ret;
9215
9216 /* if we want to turn off the cursor ignore width and height */
9217 if (!fb)
9218 return 0;
9219
9220 /* Check for which cursor types we support */
9221 if (!i845_cursor_size_ok(plane_state)) {
9222 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9223 plane_state->base.crtc_w,
9224 plane_state->base.crtc_h);
9225 return -EINVAL;
9226 }
9227
9228 switch (fb->pitches[0]) {
9229 case 256:
9230 case 512:
9231 case 1024:
9232 case 2048:
9233 break;
9234 default:
9235 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9236 fb->pitches[0]);
9237 return -EINVAL;
9238 }
9239
9240 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9241
9242 return 0;
9243 }
9244
9245 static void i845_update_cursor(struct intel_plane *plane,
9246 const struct intel_crtc_state *crtc_state,
9247 const struct intel_plane_state *plane_state)
9248 {
9249 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9250 u32 cntl = 0, base = 0, pos = 0, size = 0;
9251 unsigned long irqflags;
9252
9253 if (plane_state && plane_state->base.visible) {
9254 unsigned int width = plane_state->base.crtc_w;
9255 unsigned int height = plane_state->base.crtc_h;
9256
9257 cntl = plane_state->ctl;
9258 size = (height << 12) | width;
9259
9260 base = intel_cursor_base(plane_state);
9261 pos = intel_cursor_position(plane_state);
9262 }
9263
9264 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9265
9266 /* On these chipsets we can only modify the base/size/stride
9267 * whilst the cursor is disabled.
9268 */
9269 if (plane->cursor.base != base ||
9270 plane->cursor.size != size ||
9271 plane->cursor.cntl != cntl) {
9272 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9273 I915_WRITE_FW(CURBASE(PIPE_A), base);
9274 I915_WRITE_FW(CURSIZE, size);
9275 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9276 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9277
9278 plane->cursor.base = base;
9279 plane->cursor.size = size;
9280 plane->cursor.cntl = cntl;
9281 } else {
9282 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9283 }
9284
9285 POSTING_READ_FW(CURCNTR(PIPE_A));
9286
9287 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9288 }
9289
9290 static void i845_disable_cursor(struct intel_plane *plane,
9291 struct intel_crtc *crtc)
9292 {
9293 i845_update_cursor(plane, NULL, NULL);
9294 }
9295
9296 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9297 const struct intel_plane_state *plane_state)
9298 {
9299 struct drm_i915_private *dev_priv =
9300 to_i915(plane_state->base.plane->dev);
9301 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9302 u32 cntl;
9303
9304 cntl = MCURSOR_GAMMA_ENABLE;
9305
9306 if (HAS_DDI(dev_priv))
9307 cntl |= CURSOR_PIPE_CSC_ENABLE;
9308
9309 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9310
9311 switch (plane_state->base.crtc_w) {
9312 case 64:
9313 cntl |= CURSOR_MODE_64_ARGB_AX;
9314 break;
9315 case 128:
9316 cntl |= CURSOR_MODE_128_ARGB_AX;
9317 break;
9318 case 256:
9319 cntl |= CURSOR_MODE_256_ARGB_AX;
9320 break;
9321 default:
9322 MISSING_CASE(plane_state->base.crtc_w);
9323 return 0;
9324 }
9325
9326 if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9327 cntl |= CURSOR_ROTATE_180;
9328
9329 return cntl;
9330 }
9331
9332 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9333 {
9334 struct drm_i915_private *dev_priv =
9335 to_i915(plane_state->base.plane->dev);
9336 int width = plane_state->base.crtc_w;
9337 int height = plane_state->base.crtc_h;
9338
9339 if (!intel_cursor_size_ok(plane_state))
9340 return false;
9341
9342 /* Cursor width is limited to a few power-of-two sizes */
9343 switch (width) {
9344 case 256:
9345 case 128:
9346 case 64:
9347 break;
9348 default:
9349 return false;
9350 }
9351
9352 /*
9353 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9354 * height from 8 lines up to the cursor width, when the
9355 * cursor is not rotated. Everything else requires square
9356 * cursors.
9357 */
9358 if (HAS_CUR_FBC(dev_priv) &&
9359 plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9360 if (height < 8 || height > width)
9361 return false;
9362 } else {
9363 if (height != width)
9364 return false;
9365 }
9366
9367 return true;
9368 }
9369
9370 static int i9xx_check_cursor(struct intel_plane *plane,
9371 struct intel_crtc_state *crtc_state,
9372 struct intel_plane_state *plane_state)
9373 {
9374 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9375 const struct drm_framebuffer *fb = plane_state->base.fb;
9376 enum pipe pipe = plane->pipe;
9377 int ret;
9378
9379 ret = intel_check_cursor(crtc_state, plane_state);
9380 if (ret)
9381 return ret;
9382
9383 /* if we want to turn off the cursor ignore width and height */
9384 if (!fb)
9385 return 0;
9386
9387 /* Check for which cursor types we support */
9388 if (!i9xx_cursor_size_ok(plane_state)) {
9389 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9390 plane_state->base.crtc_w,
9391 plane_state->base.crtc_h);
9392 return -EINVAL;
9393 }
9394
9395 if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9396 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9397 fb->pitches[0], plane_state->base.crtc_w);
9398 return -EINVAL;
9399 }
9400
9401 /*
9402 * There's something wrong with the cursor on CHV pipe C.
9403 * If it straddles the left edge of the screen then
9404 * moving it away from the edge or disabling it often
9405 * results in a pipe underrun, and often that can lead to
9406 * dead pipe (constant underrun reported, and it scans
9407 * out just a solid color). To recover from that, the
9408 * display power well must be turned off and on again.
9409 * Refuse the put the cursor into that compromised position.
9410 */
9411 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9412 plane_state->base.visible && plane_state->base.crtc_x < 0) {
9413 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9414 return -EINVAL;
9415 }
9416
9417 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9418
9419 return 0;
9420 }
9421
9422 static void i9xx_update_cursor(struct intel_plane *plane,
9423 const struct intel_crtc_state *crtc_state,
9424 const struct intel_plane_state *plane_state)
9425 {
9426 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9427 enum pipe pipe = plane->pipe;
9428 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9429 unsigned long irqflags;
9430
9431 if (plane_state && plane_state->base.visible) {
9432 cntl = plane_state->ctl;
9433
9434 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9435 fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9436
9437 base = intel_cursor_base(plane_state);
9438 pos = intel_cursor_position(plane_state);
9439 }
9440
9441 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9442
9443 /*
9444 * On some platforms writing CURCNTR first will also
9445 * cause CURPOS to be armed by the CURBASE write.
9446 * Without the CURCNTR write the CURPOS write would
9447 * arm itself. Thus we always start the full update
9448 * with a CURCNTR write.
9449 *
9450 * On other platforms CURPOS always requires the
9451 * CURBASE write to arm the update. Additonally
9452 * a write to any of the cursor register will cancel
9453 * an already armed cursor update. Thus leaving out
9454 * the CURBASE write after CURPOS could lead to a
9455 * cursor that doesn't appear to move, or even change
9456 * shape. Thus we always write CURBASE.
9457 *
9458 * CURCNTR and CUR_FBC_CTL are always
9459 * armed by the CURBASE write only.
9460 */
9461 if (plane->cursor.base != base ||
9462 plane->cursor.size != fbc_ctl ||
9463 plane->cursor.cntl != cntl) {
9464 I915_WRITE_FW(CURCNTR(pipe), cntl);
9465 if (HAS_CUR_FBC(dev_priv))
9466 I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
9467 I915_WRITE_FW(CURPOS(pipe), pos);
9468 I915_WRITE_FW(CURBASE(pipe), base);
9469
9470 plane->cursor.base = base;
9471 plane->cursor.size = fbc_ctl;
9472 plane->cursor.cntl = cntl;
9473 } else {
9474 I915_WRITE_FW(CURPOS(pipe), pos);
9475 I915_WRITE_FW(CURBASE(pipe), base);
9476 }
9477
9478 POSTING_READ_FW(CURBASE(pipe));
9479
9480 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9481 }
9482
9483 static void i9xx_disable_cursor(struct intel_plane *plane,
9484 struct intel_crtc *crtc)
9485 {
9486 i9xx_update_cursor(plane, NULL, NULL);
9487 }
9488
9489
9490 /* VESA 640x480x72Hz mode to set on the pipe */
9491 static struct drm_display_mode load_detect_mode = {
9492 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9493 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9494 };
9495
9496 struct drm_framebuffer *
9497 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9498 struct drm_mode_fb_cmd2 *mode_cmd)
9499 {
9500 struct intel_framebuffer *intel_fb;
9501 int ret;
9502
9503 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9504 if (!intel_fb)
9505 return ERR_PTR(-ENOMEM);
9506
9507 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9508 if (ret)
9509 goto err;
9510
9511 return &intel_fb->base;
9512
9513 err:
9514 kfree(intel_fb);
9515 return ERR_PTR(ret);
9516 }
9517
9518 static u32
9519 intel_framebuffer_pitch_for_width(int width, int bpp)
9520 {
9521 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9522 return ALIGN(pitch, 64);
9523 }
9524
9525 static u32
9526 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9527 {
9528 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9529 return PAGE_ALIGN(pitch * mode->vdisplay);
9530 }
9531
9532 static struct drm_framebuffer *
9533 intel_framebuffer_create_for_mode(struct drm_device *dev,
9534 struct drm_display_mode *mode,
9535 int depth, int bpp)
9536 {
9537 struct drm_framebuffer *fb;
9538 struct drm_i915_gem_object *obj;
9539 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9540
9541 obj = i915_gem_object_create(to_i915(dev),
9542 intel_framebuffer_size_for_mode(mode, bpp));
9543 if (IS_ERR(obj))
9544 return ERR_CAST(obj);
9545
9546 mode_cmd.width = mode->hdisplay;
9547 mode_cmd.height = mode->vdisplay;
9548 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9549 bpp);
9550 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9551
9552 fb = intel_framebuffer_create(obj, &mode_cmd);
9553 if (IS_ERR(fb))
9554 i915_gem_object_put(obj);
9555
9556 return fb;
9557 }
9558
9559 static struct drm_framebuffer *
9560 mode_fits_in_fbdev(struct drm_device *dev,
9561 struct drm_display_mode *mode)
9562 {
9563 #ifdef CONFIG_DRM_FBDEV_EMULATION
9564 struct drm_i915_private *dev_priv = to_i915(dev);
9565 struct drm_i915_gem_object *obj;
9566 struct drm_framebuffer *fb;
9567
9568 if (!dev_priv->fbdev)
9569 return NULL;
9570
9571 if (!dev_priv->fbdev->fb)
9572 return NULL;
9573
9574 obj = dev_priv->fbdev->fb->obj;
9575 BUG_ON(!obj);
9576
9577 fb = &dev_priv->fbdev->fb->base;
9578 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9579 fb->format->cpp[0] * 8))
9580 return NULL;
9581
9582 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9583 return NULL;
9584
9585 drm_framebuffer_reference(fb);
9586 return fb;
9587 #else
9588 return NULL;
9589 #endif
9590 }
9591
9592 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9593 struct drm_crtc *crtc,
9594 struct drm_display_mode *mode,
9595 struct drm_framebuffer *fb,
9596 int x, int y)
9597 {
9598 struct drm_plane_state *plane_state;
9599 int hdisplay, vdisplay;
9600 int ret;
9601
9602 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9603 if (IS_ERR(plane_state))
9604 return PTR_ERR(plane_state);
9605
9606 if (mode)
9607 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9608 else
9609 hdisplay = vdisplay = 0;
9610
9611 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9612 if (ret)
9613 return ret;
9614 drm_atomic_set_fb_for_plane(plane_state, fb);
9615 plane_state->crtc_x = 0;
9616 plane_state->crtc_y = 0;
9617 plane_state->crtc_w = hdisplay;
9618 plane_state->crtc_h = vdisplay;
9619 plane_state->src_x = x << 16;
9620 plane_state->src_y = y << 16;
9621 plane_state->src_w = hdisplay << 16;
9622 plane_state->src_h = vdisplay << 16;
9623
9624 return 0;
9625 }
9626
9627 int intel_get_load_detect_pipe(struct drm_connector *connector,
9628 struct drm_display_mode *mode,
9629 struct intel_load_detect_pipe *old,
9630 struct drm_modeset_acquire_ctx *ctx)
9631 {
9632 struct intel_crtc *intel_crtc;
9633 struct intel_encoder *intel_encoder =
9634 intel_attached_encoder(connector);
9635 struct drm_crtc *possible_crtc;
9636 struct drm_encoder *encoder = &intel_encoder->base;
9637 struct drm_crtc *crtc = NULL;
9638 struct drm_device *dev = encoder->dev;
9639 struct drm_i915_private *dev_priv = to_i915(dev);
9640 struct drm_framebuffer *fb;
9641 struct drm_mode_config *config = &dev->mode_config;
9642 struct drm_atomic_state *state = NULL, *restore_state = NULL;
9643 struct drm_connector_state *connector_state;
9644 struct intel_crtc_state *crtc_state;
9645 int ret, i = -1;
9646
9647 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9648 connector->base.id, connector->name,
9649 encoder->base.id, encoder->name);
9650
9651 old->restore_state = NULL;
9652
9653 WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
9654
9655 /*
9656 * Algorithm gets a little messy:
9657 *
9658 * - if the connector already has an assigned crtc, use it (but make
9659 * sure it's on first)
9660 *
9661 * - try to find the first unused crtc that can drive this connector,
9662 * and use that if we find one
9663 */
9664
9665 /* See if we already have a CRTC for this connector */
9666 if (connector->state->crtc) {
9667 crtc = connector->state->crtc;
9668
9669 ret = drm_modeset_lock(&crtc->mutex, ctx);
9670 if (ret)
9671 goto fail;
9672
9673 /* Make sure the crtc and connector are running */
9674 goto found;
9675 }
9676
9677 /* Find an unused one (if possible) */
9678 for_each_crtc(dev, possible_crtc) {
9679 i++;
9680 if (!(encoder->possible_crtcs & (1 << i)))
9681 continue;
9682
9683 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9684 if (ret)
9685 goto fail;
9686
9687 if (possible_crtc->state->enable) {
9688 drm_modeset_unlock(&possible_crtc->mutex);
9689 continue;
9690 }
9691
9692 crtc = possible_crtc;
9693 break;
9694 }
9695
9696 /*
9697 * If we didn't find an unused CRTC, don't use any.
9698 */
9699 if (!crtc) {
9700 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9701 ret = -ENODEV;
9702 goto fail;
9703 }
9704
9705 found:
9706 intel_crtc = to_intel_crtc(crtc);
9707
9708 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9709 if (ret)
9710 goto fail;
9711
9712 state = drm_atomic_state_alloc(dev);
9713 restore_state = drm_atomic_state_alloc(dev);
9714 if (!state || !restore_state) {
9715 ret = -ENOMEM;
9716 goto fail;
9717 }
9718
9719 state->acquire_ctx = ctx;
9720 restore_state->acquire_ctx = ctx;
9721
9722 connector_state = drm_atomic_get_connector_state(state, connector);
9723 if (IS_ERR(connector_state)) {
9724 ret = PTR_ERR(connector_state);
9725 goto fail;
9726 }
9727
9728 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9729 if (ret)
9730 goto fail;
9731
9732 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9733 if (IS_ERR(crtc_state)) {
9734 ret = PTR_ERR(crtc_state);
9735 goto fail;
9736 }
9737
9738 crtc_state->base.active = crtc_state->base.enable = true;
9739
9740 if (!mode)
9741 mode = &load_detect_mode;
9742
9743 /* We need a framebuffer large enough to accommodate all accesses
9744 * that the plane may generate whilst we perform load detection.
9745 * We can not rely on the fbcon either being present (we get called
9746 * during its initialisation to detect all boot displays, or it may
9747 * not even exist) or that it is large enough to satisfy the
9748 * requested mode.
9749 */
9750 fb = mode_fits_in_fbdev(dev, mode);
9751 if (fb == NULL) {
9752 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9753 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9754 } else
9755 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9756 if (IS_ERR(fb)) {
9757 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9758 ret = PTR_ERR(fb);
9759 goto fail;
9760 }
9761
9762 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9763 if (ret)
9764 goto fail;
9765
9766 drm_framebuffer_unreference(fb);
9767
9768 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9769 if (ret)
9770 goto fail;
9771
9772 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9773 if (!ret)
9774 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9775 if (!ret)
9776 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9777 if (ret) {
9778 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9779 goto fail;
9780 }
9781
9782 ret = drm_atomic_commit(state);
9783 if (ret) {
9784 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9785 goto fail;
9786 }
9787
9788 old->restore_state = restore_state;
9789 drm_atomic_state_put(state);
9790
9791 /* let the connector get through one full cycle before testing */
9792 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9793 return true;
9794
9795 fail:
9796 if (state) {
9797 drm_atomic_state_put(state);
9798 state = NULL;
9799 }
9800 if (restore_state) {
9801 drm_atomic_state_put(restore_state);
9802 restore_state = NULL;
9803 }
9804
9805 if (ret == -EDEADLK)
9806 return ret;
9807
9808 return false;
9809 }
9810
9811 void intel_release_load_detect_pipe(struct drm_connector *connector,
9812 struct intel_load_detect_pipe *old,
9813 struct drm_modeset_acquire_ctx *ctx)
9814 {
9815 struct intel_encoder *intel_encoder =
9816 intel_attached_encoder(connector);
9817 struct drm_encoder *encoder = &intel_encoder->base;
9818 struct drm_atomic_state *state = old->restore_state;
9819 int ret;
9820
9821 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9822 connector->base.id, connector->name,
9823 encoder->base.id, encoder->name);
9824
9825 if (!state)
9826 return;
9827
9828 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
9829 if (ret)
9830 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
9831 drm_atomic_state_put(state);
9832 }
9833
9834 static int i9xx_pll_refclk(struct drm_device *dev,
9835 const struct intel_crtc_state *pipe_config)
9836 {
9837 struct drm_i915_private *dev_priv = to_i915(dev);
9838 u32 dpll = pipe_config->dpll_hw_state.dpll;
9839
9840 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9841 return dev_priv->vbt.lvds_ssc_freq;
9842 else if (HAS_PCH_SPLIT(dev_priv))
9843 return 120000;
9844 else if (!IS_GEN2(dev_priv))
9845 return 96000;
9846 else
9847 return 48000;
9848 }
9849
9850 /* Returns the clock of the currently programmed mode of the given pipe. */
9851 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9852 struct intel_crtc_state *pipe_config)
9853 {
9854 struct drm_device *dev = crtc->base.dev;
9855 struct drm_i915_private *dev_priv = to_i915(dev);
9856 int pipe = pipe_config->cpu_transcoder;
9857 u32 dpll = pipe_config->dpll_hw_state.dpll;
9858 u32 fp;
9859 struct dpll clock;
9860 int port_clock;
9861 int refclk = i9xx_pll_refclk(dev, pipe_config);
9862
9863 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9864 fp = pipe_config->dpll_hw_state.fp0;
9865 else
9866 fp = pipe_config->dpll_hw_state.fp1;
9867
9868 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9869 if (IS_PINEVIEW(dev_priv)) {
9870 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9871 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9872 } else {
9873 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9874 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9875 }
9876
9877 if (!IS_GEN2(dev_priv)) {
9878 if (IS_PINEVIEW(dev_priv))
9879 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9880 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9881 else
9882 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9883 DPLL_FPA01_P1_POST_DIV_SHIFT);
9884
9885 switch (dpll & DPLL_MODE_MASK) {
9886 case DPLLB_MODE_DAC_SERIAL:
9887 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9888 5 : 10;
9889 break;
9890 case DPLLB_MODE_LVDS:
9891 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9892 7 : 14;
9893 break;
9894 default:
9895 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9896 "mode\n", (int)(dpll & DPLL_MODE_MASK));
9897 return;
9898 }
9899
9900 if (IS_PINEVIEW(dev_priv))
9901 port_clock = pnv_calc_dpll_params(refclk, &clock);
9902 else
9903 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9904 } else {
9905 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
9906 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9907
9908 if (is_lvds) {
9909 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9910 DPLL_FPA01_P1_POST_DIV_SHIFT);
9911
9912 if (lvds & LVDS_CLKB_POWER_UP)
9913 clock.p2 = 7;
9914 else
9915 clock.p2 = 14;
9916 } else {
9917 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9918 clock.p1 = 2;
9919 else {
9920 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9921 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9922 }
9923 if (dpll & PLL_P2_DIVIDE_BY_4)
9924 clock.p2 = 4;
9925 else
9926 clock.p2 = 2;
9927 }
9928
9929 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9930 }
9931
9932 /*
9933 * This value includes pixel_multiplier. We will use
9934 * port_clock to compute adjusted_mode.crtc_clock in the
9935 * encoder's get_config() function.
9936 */
9937 pipe_config->port_clock = port_clock;
9938 }
9939
9940 int intel_dotclock_calculate(int link_freq,
9941 const struct intel_link_m_n *m_n)
9942 {
9943 /*
9944 * The calculation for the data clock is:
9945 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9946 * But we want to avoid losing precison if possible, so:
9947 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9948 *
9949 * and the link clock is simpler:
9950 * link_clock = (m * link_clock) / n
9951 */
9952
9953 if (!m_n->link_n)
9954 return 0;
9955
9956 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9957 }
9958
9959 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9960 struct intel_crtc_state *pipe_config)
9961 {
9962 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9963
9964 /* read out port_clock from the DPLL */
9965 i9xx_crtc_clock_get(crtc, pipe_config);
9966
9967 /*
9968 * In case there is an active pipe without active ports,
9969 * we may need some idea for the dotclock anyway.
9970 * Calculate one based on the FDI configuration.
9971 */
9972 pipe_config->base.adjusted_mode.crtc_clock =
9973 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
9974 &pipe_config->fdi_m_n);
9975 }
9976
9977 /** Returns the currently programmed mode of the given pipe. */
9978 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9979 struct drm_crtc *crtc)
9980 {
9981 struct drm_i915_private *dev_priv = to_i915(dev);
9982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9983 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9984 struct drm_display_mode *mode;
9985 struct intel_crtc_state *pipe_config;
9986 int htot = I915_READ(HTOTAL(cpu_transcoder));
9987 int hsync = I915_READ(HSYNC(cpu_transcoder));
9988 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9989 int vsync = I915_READ(VSYNC(cpu_transcoder));
9990 enum pipe pipe = intel_crtc->pipe;
9991
9992 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9993 if (!mode)
9994 return NULL;
9995
9996 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9997 if (!pipe_config) {
9998 kfree(mode);
9999 return NULL;
10000 }
10001
10002 /*
10003 * Construct a pipe_config sufficient for getting the clock info
10004 * back out of crtc_clock_get.
10005 *
10006 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10007 * to use a real value here instead.
10008 */
10009 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10010 pipe_config->pixel_multiplier = 1;
10011 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10012 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10013 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10014 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10015
10016 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10017 mode->hdisplay = (htot & 0xffff) + 1;
10018 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10019 mode->hsync_start = (hsync & 0xffff) + 1;
10020 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10021 mode->vdisplay = (vtot & 0xffff) + 1;
10022 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10023 mode->vsync_start = (vsync & 0xffff) + 1;
10024 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10025
10026 drm_mode_set_name(mode);
10027
10028 kfree(pipe_config);
10029
10030 return mode;
10031 }
10032
10033 static void intel_crtc_destroy(struct drm_crtc *crtc)
10034 {
10035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10036
10037 drm_crtc_cleanup(crtc);
10038 kfree(intel_crtc);
10039 }
10040
10041 /**
10042 * intel_wm_need_update - Check whether watermarks need updating
10043 * @plane: drm plane
10044 * @state: new plane state
10045 *
10046 * Check current plane state versus the new one to determine whether
10047 * watermarks need to be recalculated.
10048 *
10049 * Returns true or false.
10050 */
10051 static bool intel_wm_need_update(struct drm_plane *plane,
10052 struct drm_plane_state *state)
10053 {
10054 struct intel_plane_state *new = to_intel_plane_state(state);
10055 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10056
10057 /* Update watermarks on tiling or size changes. */
10058 if (new->base.visible != cur->base.visible)
10059 return true;
10060
10061 if (!cur->base.fb || !new->base.fb)
10062 return false;
10063
10064 if (cur->base.fb->modifier != new->base.fb->modifier ||
10065 cur->base.rotation != new->base.rotation ||
10066 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10067 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10068 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10069 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10070 return true;
10071
10072 return false;
10073 }
10074
10075 static bool needs_scaling(struct intel_plane_state *state)
10076 {
10077 int src_w = drm_rect_width(&state->base.src) >> 16;
10078 int src_h = drm_rect_height(&state->base.src) >> 16;
10079 int dst_w = drm_rect_width(&state->base.dst);
10080 int dst_h = drm_rect_height(&state->base.dst);
10081
10082 return (src_w != dst_w || src_h != dst_h);
10083 }
10084
10085 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
10086 struct drm_plane_state *plane_state)
10087 {
10088 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10089 struct drm_crtc *crtc = crtc_state->crtc;
10090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10091 struct intel_plane *plane = to_intel_plane(plane_state->plane);
10092 struct drm_device *dev = crtc->dev;
10093 struct drm_i915_private *dev_priv = to_i915(dev);
10094 struct intel_plane_state *old_plane_state =
10095 to_intel_plane_state(plane->base.state);
10096 bool mode_changed = needs_modeset(crtc_state);
10097 bool was_crtc_enabled = crtc->state->active;
10098 bool is_crtc_enabled = crtc_state->active;
10099 bool turn_off, turn_on, visible, was_visible;
10100 struct drm_framebuffer *fb = plane_state->fb;
10101 int ret;
10102
10103 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10104 ret = skl_update_scaler_plane(
10105 to_intel_crtc_state(crtc_state),
10106 to_intel_plane_state(plane_state));
10107 if (ret)
10108 return ret;
10109 }
10110
10111 was_visible = old_plane_state->base.visible;
10112 visible = plane_state->visible;
10113
10114 if (!was_crtc_enabled && WARN_ON(was_visible))
10115 was_visible = false;
10116
10117 /*
10118 * Visibility is calculated as if the crtc was on, but
10119 * after scaler setup everything depends on it being off
10120 * when the crtc isn't active.
10121 *
10122 * FIXME this is wrong for watermarks. Watermarks should also
10123 * be computed as if the pipe would be active. Perhaps move
10124 * per-plane wm computation to the .check_plane() hook, and
10125 * only combine the results from all planes in the current place?
10126 */
10127 if (!is_crtc_enabled) {
10128 plane_state->visible = visible = false;
10129 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10130 }
10131
10132 if (!was_visible && !visible)
10133 return 0;
10134
10135 if (fb != old_plane_state->base.fb)
10136 pipe_config->fb_changed = true;
10137
10138 turn_off = was_visible && (!visible || mode_changed);
10139 turn_on = visible && (!was_visible || mode_changed);
10140
10141 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10142 intel_crtc->base.base.id, intel_crtc->base.name,
10143 plane->base.base.id, plane->base.name,
10144 fb ? fb->base.id : -1);
10145
10146 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10147 plane->base.base.id, plane->base.name,
10148 was_visible, visible,
10149 turn_off, turn_on, mode_changed);
10150
10151 if (turn_on) {
10152 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10153 pipe_config->update_wm_pre = true;
10154
10155 /* must disable cxsr around plane enable/disable */
10156 if (plane->id != PLANE_CURSOR)
10157 pipe_config->disable_cxsr = true;
10158 } else if (turn_off) {
10159 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10160 pipe_config->update_wm_post = true;
10161
10162 /* must disable cxsr around plane enable/disable */
10163 if (plane->id != PLANE_CURSOR)
10164 pipe_config->disable_cxsr = true;
10165 } else if (intel_wm_need_update(&plane->base, plane_state)) {
10166 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
10167 /* FIXME bollocks */
10168 pipe_config->update_wm_pre = true;
10169 pipe_config->update_wm_post = true;
10170 }
10171 }
10172
10173 if (visible || was_visible)
10174 pipe_config->fb_bits |= plane->frontbuffer_bit;
10175
10176 /*
10177 * WaCxSRDisabledForSpriteScaling:ivb
10178 *
10179 * cstate->update_wm was already set above, so this flag will
10180 * take effect when we commit and program watermarks.
10181 */
10182 if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10183 needs_scaling(to_intel_plane_state(plane_state)) &&
10184 !needs_scaling(old_plane_state))
10185 pipe_config->disable_lp_wm = true;
10186
10187 return 0;
10188 }
10189
10190 static bool encoders_cloneable(const struct intel_encoder *a,
10191 const struct intel_encoder *b)
10192 {
10193 /* masks could be asymmetric, so check both ways */
10194 return a == b || (a->cloneable & (1 << b->type) &&
10195 b->cloneable & (1 << a->type));
10196 }
10197
10198 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10199 struct intel_crtc *crtc,
10200 struct intel_encoder *encoder)
10201 {
10202 struct intel_encoder *source_encoder;
10203 struct drm_connector *connector;
10204 struct drm_connector_state *connector_state;
10205 int i;
10206
10207 for_each_new_connector_in_state(state, connector, connector_state, i) {
10208 if (connector_state->crtc != &crtc->base)
10209 continue;
10210
10211 source_encoder =
10212 to_intel_encoder(connector_state->best_encoder);
10213 if (!encoders_cloneable(encoder, source_encoder))
10214 return false;
10215 }
10216
10217 return true;
10218 }
10219
10220 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10221 struct drm_crtc_state *crtc_state)
10222 {
10223 struct drm_device *dev = crtc->dev;
10224 struct drm_i915_private *dev_priv = to_i915(dev);
10225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10226 struct intel_crtc_state *pipe_config =
10227 to_intel_crtc_state(crtc_state);
10228 struct drm_atomic_state *state = crtc_state->state;
10229 int ret;
10230 bool mode_changed = needs_modeset(crtc_state);
10231
10232 if (mode_changed && !crtc_state->active)
10233 pipe_config->update_wm_post = true;
10234
10235 if (mode_changed && crtc_state->enable &&
10236 dev_priv->display.crtc_compute_clock &&
10237 !WARN_ON(pipe_config->shared_dpll)) {
10238 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10239 pipe_config);
10240 if (ret)
10241 return ret;
10242 }
10243
10244 if (crtc_state->color_mgmt_changed) {
10245 ret = intel_color_check(crtc, crtc_state);
10246 if (ret)
10247 return ret;
10248
10249 /*
10250 * Changing color management on Intel hardware is
10251 * handled as part of planes update.
10252 */
10253 crtc_state->planes_changed = true;
10254 }
10255
10256 ret = 0;
10257 if (dev_priv->display.compute_pipe_wm) {
10258 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10259 if (ret) {
10260 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10261 return ret;
10262 }
10263 }
10264
10265 if (dev_priv->display.compute_intermediate_wm &&
10266 !to_intel_atomic_state(state)->skip_intermediate_wm) {
10267 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10268 return 0;
10269
10270 /*
10271 * Calculate 'intermediate' watermarks that satisfy both the
10272 * old state and the new state. We can program these
10273 * immediately.
10274 */
10275 ret = dev_priv->display.compute_intermediate_wm(dev,
10276 intel_crtc,
10277 pipe_config);
10278 if (ret) {
10279 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10280 return ret;
10281 }
10282 } else if (dev_priv->display.compute_intermediate_wm) {
10283 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10284 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10285 }
10286
10287 if (INTEL_GEN(dev_priv) >= 9) {
10288 if (mode_changed)
10289 ret = skl_update_scaler_crtc(pipe_config);
10290
10291 if (!ret)
10292 ret = skl_check_pipe_max_pixel_rate(intel_crtc,
10293 pipe_config);
10294 if (!ret)
10295 ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
10296 pipe_config);
10297 }
10298
10299 return ret;
10300 }
10301
10302 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
10303 .atomic_begin = intel_begin_crtc_commit,
10304 .atomic_flush = intel_finish_crtc_commit,
10305 .atomic_check = intel_crtc_atomic_check,
10306 };
10307
10308 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10309 {
10310 struct intel_connector *connector;
10311 struct drm_connector_list_iter conn_iter;
10312
10313 drm_connector_list_iter_begin(dev, &conn_iter);
10314 for_each_intel_connector_iter(connector, &conn_iter) {
10315 if (connector->base.state->crtc)
10316 drm_connector_unreference(&connector->base);
10317
10318 if (connector->base.encoder) {
10319 connector->base.state->best_encoder =
10320 connector->base.encoder;
10321 connector->base.state->crtc =
10322 connector->base.encoder->crtc;
10323
10324 drm_connector_reference(&connector->base);
10325 } else {
10326 connector->base.state->best_encoder = NULL;
10327 connector->base.state->crtc = NULL;
10328 }
10329 }
10330 drm_connector_list_iter_end(&conn_iter);
10331 }
10332
10333 static void
10334 connected_sink_compute_bpp(struct intel_connector *connector,
10335 struct intel_crtc_state *pipe_config)
10336 {
10337 const struct drm_display_info *info = &connector->base.display_info;
10338 int bpp = pipe_config->pipe_bpp;
10339
10340 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10341 connector->base.base.id,
10342 connector->base.name);
10343
10344 /* Don't use an invalid EDID bpc value */
10345 if (info->bpc != 0 && info->bpc * 3 < bpp) {
10346 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10347 bpp, info->bpc * 3);
10348 pipe_config->pipe_bpp = info->bpc * 3;
10349 }
10350
10351 /* Clamp bpp to 8 on screens without EDID 1.4 */
10352 if (info->bpc == 0 && bpp > 24) {
10353 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10354 bpp);
10355 pipe_config->pipe_bpp = 24;
10356 }
10357 }
10358
10359 static int
10360 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10361 struct intel_crtc_state *pipe_config)
10362 {
10363 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10364 struct drm_atomic_state *state;
10365 struct drm_connector *connector;
10366 struct drm_connector_state *connector_state;
10367 int bpp, i;
10368
10369 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
10370 IS_CHERRYVIEW(dev_priv)))
10371 bpp = 10*3;
10372 else if (INTEL_GEN(dev_priv) >= 5)
10373 bpp = 12*3;
10374 else
10375 bpp = 8*3;
10376
10377
10378 pipe_config->pipe_bpp = bpp;
10379
10380 state = pipe_config->base.state;
10381
10382 /* Clamp display bpp to EDID value */
10383 for_each_new_connector_in_state(state, connector, connector_state, i) {
10384 if (connector_state->crtc != &crtc->base)
10385 continue;
10386
10387 connected_sink_compute_bpp(to_intel_connector(connector),
10388 pipe_config);
10389 }
10390
10391 return bpp;
10392 }
10393
10394 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10395 {
10396 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10397 "type: 0x%x flags: 0x%x\n",
10398 mode->crtc_clock,
10399 mode->crtc_hdisplay, mode->crtc_hsync_start,
10400 mode->crtc_hsync_end, mode->crtc_htotal,
10401 mode->crtc_vdisplay, mode->crtc_vsync_start,
10402 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10403 }
10404
10405 static inline void
10406 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
10407 unsigned int lane_count, struct intel_link_m_n *m_n)
10408 {
10409 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10410 id, lane_count,
10411 m_n->gmch_m, m_n->gmch_n,
10412 m_n->link_m, m_n->link_n, m_n->tu);
10413 }
10414
10415 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10416 struct intel_crtc_state *pipe_config,
10417 const char *context)
10418 {
10419 struct drm_device *dev = crtc->base.dev;
10420 struct drm_i915_private *dev_priv = to_i915(dev);
10421 struct drm_plane *plane;
10422 struct intel_plane *intel_plane;
10423 struct intel_plane_state *state;
10424 struct drm_framebuffer *fb;
10425
10426 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
10427 crtc->base.base.id, crtc->base.name, context);
10428
10429 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
10430 transcoder_name(pipe_config->cpu_transcoder),
10431 pipe_config->pipe_bpp, pipe_config->dither);
10432
10433 if (pipe_config->has_pch_encoder)
10434 intel_dump_m_n_config(pipe_config, "fdi",
10435 pipe_config->fdi_lanes,
10436 &pipe_config->fdi_m_n);
10437
10438 if (pipe_config->ycbcr420)
10439 DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n");
10440
10441 if (intel_crtc_has_dp_encoder(pipe_config)) {
10442 intel_dump_m_n_config(pipe_config, "dp m_n",
10443 pipe_config->lane_count, &pipe_config->dp_m_n);
10444 if (pipe_config->has_drrs)
10445 intel_dump_m_n_config(pipe_config, "dp m2_n2",
10446 pipe_config->lane_count,
10447 &pipe_config->dp_m2_n2);
10448 }
10449
10450 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10451 pipe_config->has_audio, pipe_config->has_infoframe);
10452
10453 DRM_DEBUG_KMS("requested mode:\n");
10454 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10455 DRM_DEBUG_KMS("adjusted mode:\n");
10456 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10457 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10458 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
10459 pipe_config->port_clock,
10460 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
10461 pipe_config->pixel_rate);
10462
10463 if (INTEL_GEN(dev_priv) >= 9)
10464 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
10465 crtc->num_scalers,
10466 pipe_config->scaler_state.scaler_users,
10467 pipe_config->scaler_state.scaler_id);
10468
10469 if (HAS_GMCH_DISPLAY(dev_priv))
10470 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10471 pipe_config->gmch_pfit.control,
10472 pipe_config->gmch_pfit.pgm_ratios,
10473 pipe_config->gmch_pfit.lvds_border_bits);
10474 else
10475 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10476 pipe_config->pch_pfit.pos,
10477 pipe_config->pch_pfit.size,
10478 enableddisabled(pipe_config->pch_pfit.enabled));
10479
10480 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
10481 pipe_config->ips_enabled, pipe_config->double_wide);
10482
10483 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
10484
10485 DRM_DEBUG_KMS("planes on this crtc\n");
10486 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
10487 struct drm_format_name_buf format_name;
10488 intel_plane = to_intel_plane(plane);
10489 if (intel_plane->pipe != crtc->pipe)
10490 continue;
10491
10492 state = to_intel_plane_state(plane->state);
10493 fb = state->base.fb;
10494 if (!fb) {
10495 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
10496 plane->base.id, plane->name, state->scaler_id);
10497 continue;
10498 }
10499
10500 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
10501 plane->base.id, plane->name,
10502 fb->base.id, fb->width, fb->height,
10503 drm_get_format_name(fb->format->format, &format_name));
10504 if (INTEL_GEN(dev_priv) >= 9)
10505 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
10506 state->scaler_id,
10507 state->base.src.x1 >> 16,
10508 state->base.src.y1 >> 16,
10509 drm_rect_width(&state->base.src) >> 16,
10510 drm_rect_height(&state->base.src) >> 16,
10511 state->base.dst.x1, state->base.dst.y1,
10512 drm_rect_width(&state->base.dst),
10513 drm_rect_height(&state->base.dst));
10514 }
10515 }
10516
10517 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
10518 {
10519 struct drm_device *dev = state->dev;
10520 struct drm_connector *connector;
10521 struct drm_connector_list_iter conn_iter;
10522 unsigned int used_ports = 0;
10523 unsigned int used_mst_ports = 0;
10524
10525 /*
10526 * Walk the connector list instead of the encoder
10527 * list to detect the problem on ddi platforms
10528 * where there's just one encoder per digital port.
10529 */
10530 drm_connector_list_iter_begin(dev, &conn_iter);
10531 drm_for_each_connector_iter(connector, &conn_iter) {
10532 struct drm_connector_state *connector_state;
10533 struct intel_encoder *encoder;
10534
10535 connector_state = drm_atomic_get_existing_connector_state(state, connector);
10536 if (!connector_state)
10537 connector_state = connector->state;
10538
10539 if (!connector_state->best_encoder)
10540 continue;
10541
10542 encoder = to_intel_encoder(connector_state->best_encoder);
10543
10544 WARN_ON(!connector_state->crtc);
10545
10546 switch (encoder->type) {
10547 unsigned int port_mask;
10548 case INTEL_OUTPUT_UNKNOWN:
10549 if (WARN_ON(!HAS_DDI(to_i915(dev))))
10550 break;
10551 case INTEL_OUTPUT_DP:
10552 case INTEL_OUTPUT_HDMI:
10553 case INTEL_OUTPUT_EDP:
10554 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10555
10556 /* the same port mustn't appear more than once */
10557 if (used_ports & port_mask)
10558 return false;
10559
10560 used_ports |= port_mask;
10561 break;
10562 case INTEL_OUTPUT_DP_MST:
10563 used_mst_ports |=
10564 1 << enc_to_mst(&encoder->base)->primary->port;
10565 break;
10566 default:
10567 break;
10568 }
10569 }
10570 drm_connector_list_iter_end(&conn_iter);
10571
10572 /* can't mix MST and SST/HDMI on the same port */
10573 if (used_ports & used_mst_ports)
10574 return false;
10575
10576 return true;
10577 }
10578
10579 static void
10580 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10581 {
10582 struct drm_i915_private *dev_priv =
10583 to_i915(crtc_state->base.crtc->dev);
10584 struct intel_crtc_scaler_state scaler_state;
10585 struct intel_dpll_hw_state dpll_hw_state;
10586 struct intel_shared_dpll *shared_dpll;
10587 struct intel_crtc_wm_state wm_state;
10588 bool force_thru;
10589
10590 /* FIXME: before the switch to atomic started, a new pipe_config was
10591 * kzalloc'd. Code that depends on any field being zero should be
10592 * fixed, so that the crtc_state can be safely duplicated. For now,
10593 * only fields that are know to not cause problems are preserved. */
10594
10595 scaler_state = crtc_state->scaler_state;
10596 shared_dpll = crtc_state->shared_dpll;
10597 dpll_hw_state = crtc_state->dpll_hw_state;
10598 force_thru = crtc_state->pch_pfit.force_thru;
10599 if (IS_G4X(dev_priv) ||
10600 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10601 wm_state = crtc_state->wm;
10602
10603 /* Keep base drm_crtc_state intact, only clear our extended struct */
10604 BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
10605 memset(&crtc_state->base + 1, 0,
10606 sizeof(*crtc_state) - sizeof(crtc_state->base));
10607
10608 crtc_state->scaler_state = scaler_state;
10609 crtc_state->shared_dpll = shared_dpll;
10610 crtc_state->dpll_hw_state = dpll_hw_state;
10611 crtc_state->pch_pfit.force_thru = force_thru;
10612 if (IS_G4X(dev_priv) ||
10613 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10614 crtc_state->wm = wm_state;
10615 }
10616
10617 static int
10618 intel_modeset_pipe_config(struct drm_crtc *crtc,
10619 struct intel_crtc_state *pipe_config)
10620 {
10621 struct drm_atomic_state *state = pipe_config->base.state;
10622 struct intel_encoder *encoder;
10623 struct drm_connector *connector;
10624 struct drm_connector_state *connector_state;
10625 int base_bpp, ret = -EINVAL;
10626 int i;
10627 bool retry = true;
10628
10629 clear_intel_crtc_state(pipe_config);
10630
10631 pipe_config->cpu_transcoder =
10632 (enum transcoder) to_intel_crtc(crtc)->pipe;
10633
10634 /*
10635 * Sanitize sync polarity flags based on requested ones. If neither
10636 * positive or negative polarity is requested, treat this as meaning
10637 * negative polarity.
10638 */
10639 if (!(pipe_config->base.adjusted_mode.flags &
10640 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10641 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10642
10643 if (!(pipe_config->base.adjusted_mode.flags &
10644 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10645 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10646
10647 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10648 pipe_config);
10649 if (base_bpp < 0)
10650 goto fail;
10651
10652 /*
10653 * Determine the real pipe dimensions. Note that stereo modes can
10654 * increase the actual pipe size due to the frame doubling and
10655 * insertion of additional space for blanks between the frame. This
10656 * is stored in the crtc timings. We use the requested mode to do this
10657 * computation to clearly distinguish it from the adjusted mode, which
10658 * can be changed by the connectors in the below retry loop.
10659 */
10660 drm_mode_get_hv_timing(&pipe_config->base.mode,
10661 &pipe_config->pipe_src_w,
10662 &pipe_config->pipe_src_h);
10663
10664 for_each_new_connector_in_state(state, connector, connector_state, i) {
10665 if (connector_state->crtc != crtc)
10666 continue;
10667
10668 encoder = to_intel_encoder(connector_state->best_encoder);
10669
10670 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
10671 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10672 goto fail;
10673 }
10674
10675 /*
10676 * Determine output_types before calling the .compute_config()
10677 * hooks so that the hooks can use this information safely.
10678 */
10679 pipe_config->output_types |= 1 << encoder->type;
10680 }
10681
10682 encoder_retry:
10683 /* Ensure the port clock defaults are reset when retrying. */
10684 pipe_config->port_clock = 0;
10685 pipe_config->pixel_multiplier = 1;
10686
10687 /* Fill in default crtc timings, allow encoders to overwrite them. */
10688 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10689 CRTC_STEREO_DOUBLE);
10690
10691 /* Pass our mode to the connectors and the CRTC to give them a chance to
10692 * adjust it according to limitations or connector properties, and also
10693 * a chance to reject the mode entirely.
10694 */
10695 for_each_new_connector_in_state(state, connector, connector_state, i) {
10696 if (connector_state->crtc != crtc)
10697 continue;
10698
10699 encoder = to_intel_encoder(connector_state->best_encoder);
10700
10701 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
10702 DRM_DEBUG_KMS("Encoder config failure\n");
10703 goto fail;
10704 }
10705 }
10706
10707 /* Set default port clock if not overwritten by the encoder. Needs to be
10708 * done afterwards in case the encoder adjusts the mode. */
10709 if (!pipe_config->port_clock)
10710 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10711 * pipe_config->pixel_multiplier;
10712
10713 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10714 if (ret < 0) {
10715 DRM_DEBUG_KMS("CRTC fixup failed\n");
10716 goto fail;
10717 }
10718
10719 if (ret == RETRY) {
10720 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10721 ret = -EINVAL;
10722 goto fail;
10723 }
10724
10725 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10726 retry = false;
10727 goto encoder_retry;
10728 }
10729
10730 /* Dithering seems to not pass-through bits correctly when it should, so
10731 * only enable it on 6bpc panels and when its not a compliance
10732 * test requesting 6bpc video pattern.
10733 */
10734 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
10735 !pipe_config->dither_force_disable;
10736 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
10737 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10738
10739 fail:
10740 return ret;
10741 }
10742
10743 static void
10744 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
10745 {
10746 struct drm_crtc *crtc;
10747 struct drm_crtc_state *new_crtc_state;
10748 int i;
10749
10750 /* Double check state. */
10751 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10752 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
10753
10754 /*
10755 * Update legacy state to satisfy fbc code. This can
10756 * be removed when fbc uses the atomic state.
10757 */
10758 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
10759 struct drm_plane_state *plane_state = crtc->primary->state;
10760
10761 crtc->primary->fb = plane_state->fb;
10762 crtc->x = plane_state->src_x >> 16;
10763 crtc->y = plane_state->src_y >> 16;
10764 }
10765 }
10766 }
10767
10768 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10769 {
10770 int diff;
10771
10772 if (clock1 == clock2)
10773 return true;
10774
10775 if (!clock1 || !clock2)
10776 return false;
10777
10778 diff = abs(clock1 - clock2);
10779
10780 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10781 return true;
10782
10783 return false;
10784 }
10785
10786 static bool
10787 intel_compare_m_n(unsigned int m, unsigned int n,
10788 unsigned int m2, unsigned int n2,
10789 bool exact)
10790 {
10791 if (m == m2 && n == n2)
10792 return true;
10793
10794 if (exact || !m || !n || !m2 || !n2)
10795 return false;
10796
10797 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
10798
10799 if (n > n2) {
10800 while (n > n2) {
10801 m2 <<= 1;
10802 n2 <<= 1;
10803 }
10804 } else if (n < n2) {
10805 while (n < n2) {
10806 m <<= 1;
10807 n <<= 1;
10808 }
10809 }
10810
10811 if (n != n2)
10812 return false;
10813
10814 return intel_fuzzy_clock_check(m, m2);
10815 }
10816
10817 static bool
10818 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
10819 struct intel_link_m_n *m2_n2,
10820 bool adjust)
10821 {
10822 if (m_n->tu == m2_n2->tu &&
10823 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
10824 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
10825 intel_compare_m_n(m_n->link_m, m_n->link_n,
10826 m2_n2->link_m, m2_n2->link_n, !adjust)) {
10827 if (adjust)
10828 *m2_n2 = *m_n;
10829
10830 return true;
10831 }
10832
10833 return false;
10834 }
10835
10836 static void __printf(3, 4)
10837 pipe_config_err(bool adjust, const char *name, const char *format, ...)
10838 {
10839 char *level;
10840 unsigned int category;
10841 struct va_format vaf;
10842 va_list args;
10843
10844 if (adjust) {
10845 level = KERN_DEBUG;
10846 category = DRM_UT_KMS;
10847 } else {
10848 level = KERN_ERR;
10849 category = DRM_UT_NONE;
10850 }
10851
10852 va_start(args, format);
10853 vaf.fmt = format;
10854 vaf.va = &args;
10855
10856 drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
10857
10858 va_end(args);
10859 }
10860
10861 static bool
10862 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
10863 struct intel_crtc_state *current_config,
10864 struct intel_crtc_state *pipe_config,
10865 bool adjust)
10866 {
10867 bool ret = true;
10868
10869 #define PIPE_CONF_CHECK_X(name) \
10870 if (current_config->name != pipe_config->name) { \
10871 pipe_config_err(adjust, __stringify(name), \
10872 "(expected 0x%08x, found 0x%08x)\n", \
10873 current_config->name, \
10874 pipe_config->name); \
10875 ret = false; \
10876 }
10877
10878 #define PIPE_CONF_CHECK_I(name) \
10879 if (current_config->name != pipe_config->name) { \
10880 pipe_config_err(adjust, __stringify(name), \
10881 "(expected %i, found %i)\n", \
10882 current_config->name, \
10883 pipe_config->name); \
10884 ret = false; \
10885 }
10886
10887 #define PIPE_CONF_CHECK_P(name) \
10888 if (current_config->name != pipe_config->name) { \
10889 pipe_config_err(adjust, __stringify(name), \
10890 "(expected %p, found %p)\n", \
10891 current_config->name, \
10892 pipe_config->name); \
10893 ret = false; \
10894 }
10895
10896 #define PIPE_CONF_CHECK_M_N(name) \
10897 if (!intel_compare_link_m_n(&current_config->name, \
10898 &pipe_config->name,\
10899 adjust)) { \
10900 pipe_config_err(adjust, __stringify(name), \
10901 "(expected tu %i gmch %i/%i link %i/%i, " \
10902 "found tu %i, gmch %i/%i link %i/%i)\n", \
10903 current_config->name.tu, \
10904 current_config->name.gmch_m, \
10905 current_config->name.gmch_n, \
10906 current_config->name.link_m, \
10907 current_config->name.link_n, \
10908 pipe_config->name.tu, \
10909 pipe_config->name.gmch_m, \
10910 pipe_config->name.gmch_n, \
10911 pipe_config->name.link_m, \
10912 pipe_config->name.link_n); \
10913 ret = false; \
10914 }
10915
10916 /* This is required for BDW+ where there is only one set of registers for
10917 * switching between high and low RR.
10918 * This macro can be used whenever a comparison has to be made between one
10919 * hw state and multiple sw state variables.
10920 */
10921 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
10922 if (!intel_compare_link_m_n(&current_config->name, \
10923 &pipe_config->name, adjust) && \
10924 !intel_compare_link_m_n(&current_config->alt_name, \
10925 &pipe_config->name, adjust)) { \
10926 pipe_config_err(adjust, __stringify(name), \
10927 "(expected tu %i gmch %i/%i link %i/%i, " \
10928 "or tu %i gmch %i/%i link %i/%i, " \
10929 "found tu %i, gmch %i/%i link %i/%i)\n", \
10930 current_config->name.tu, \
10931 current_config->name.gmch_m, \
10932 current_config->name.gmch_n, \
10933 current_config->name.link_m, \
10934 current_config->name.link_n, \
10935 current_config->alt_name.tu, \
10936 current_config->alt_name.gmch_m, \
10937 current_config->alt_name.gmch_n, \
10938 current_config->alt_name.link_m, \
10939 current_config->alt_name.link_n, \
10940 pipe_config->name.tu, \
10941 pipe_config->name.gmch_m, \
10942 pipe_config->name.gmch_n, \
10943 pipe_config->name.link_m, \
10944 pipe_config->name.link_n); \
10945 ret = false; \
10946 }
10947
10948 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10949 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10950 pipe_config_err(adjust, __stringify(name), \
10951 "(%x) (expected %i, found %i)\n", \
10952 (mask), \
10953 current_config->name & (mask), \
10954 pipe_config->name & (mask)); \
10955 ret = false; \
10956 }
10957
10958 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10959 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10960 pipe_config_err(adjust, __stringify(name), \
10961 "(expected %i, found %i)\n", \
10962 current_config->name, \
10963 pipe_config->name); \
10964 ret = false; \
10965 }
10966
10967 #define PIPE_CONF_QUIRK(quirk) \
10968 ((current_config->quirks | pipe_config->quirks) & (quirk))
10969
10970 PIPE_CONF_CHECK_I(cpu_transcoder);
10971
10972 PIPE_CONF_CHECK_I(has_pch_encoder);
10973 PIPE_CONF_CHECK_I(fdi_lanes);
10974 PIPE_CONF_CHECK_M_N(fdi_m_n);
10975
10976 PIPE_CONF_CHECK_I(lane_count);
10977 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
10978
10979 if (INTEL_GEN(dev_priv) < 8) {
10980 PIPE_CONF_CHECK_M_N(dp_m_n);
10981
10982 if (current_config->has_drrs)
10983 PIPE_CONF_CHECK_M_N(dp_m2_n2);
10984 } else
10985 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
10986
10987 PIPE_CONF_CHECK_X(output_types);
10988
10989 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10990 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10991 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10992 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10993 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10994 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10995
10996 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10997 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10998 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10999 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11000 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11001 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11002
11003 PIPE_CONF_CHECK_I(pixel_multiplier);
11004 PIPE_CONF_CHECK_I(has_hdmi_sink);
11005 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11006 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11007 PIPE_CONF_CHECK_I(limited_color_range);
11008
11009 PIPE_CONF_CHECK_I(hdmi_scrambling);
11010 PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio);
11011 PIPE_CONF_CHECK_I(has_infoframe);
11012 PIPE_CONF_CHECK_I(ycbcr420);
11013
11014 PIPE_CONF_CHECK_I(has_audio);
11015
11016 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11017 DRM_MODE_FLAG_INTERLACE);
11018
11019 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11020 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11021 DRM_MODE_FLAG_PHSYNC);
11022 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11023 DRM_MODE_FLAG_NHSYNC);
11024 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11025 DRM_MODE_FLAG_PVSYNC);
11026 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11027 DRM_MODE_FLAG_NVSYNC);
11028 }
11029
11030 PIPE_CONF_CHECK_X(gmch_pfit.control);
11031 /* pfit ratios are autocomputed by the hw on gen4+ */
11032 if (INTEL_GEN(dev_priv) < 4)
11033 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11034 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11035
11036 if (!adjust) {
11037 PIPE_CONF_CHECK_I(pipe_src_w);
11038 PIPE_CONF_CHECK_I(pipe_src_h);
11039
11040 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11041 if (current_config->pch_pfit.enabled) {
11042 PIPE_CONF_CHECK_X(pch_pfit.pos);
11043 PIPE_CONF_CHECK_X(pch_pfit.size);
11044 }
11045
11046 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11047 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11048 }
11049
11050 /* BDW+ don't expose a synchronous way to read the state */
11051 if (IS_HASWELL(dev_priv))
11052 PIPE_CONF_CHECK_I(ips_enabled);
11053
11054 PIPE_CONF_CHECK_I(double_wide);
11055
11056 PIPE_CONF_CHECK_P(shared_dpll);
11057 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11058 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11059 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11060 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11061 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11062 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11063 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11064 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11065 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11066
11067 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11068 PIPE_CONF_CHECK_X(dsi_pll.div);
11069
11070 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11071 PIPE_CONF_CHECK_I(pipe_bpp);
11072
11073 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11074 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11075
11076 #undef PIPE_CONF_CHECK_X
11077 #undef PIPE_CONF_CHECK_I
11078 #undef PIPE_CONF_CHECK_P
11079 #undef PIPE_CONF_CHECK_FLAGS
11080 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11081 #undef PIPE_CONF_QUIRK
11082
11083 return ret;
11084 }
11085
11086 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11087 const struct intel_crtc_state *pipe_config)
11088 {
11089 if (pipe_config->has_pch_encoder) {
11090 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11091 &pipe_config->fdi_m_n);
11092 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11093
11094 /*
11095 * FDI already provided one idea for the dotclock.
11096 * Yell if the encoder disagrees.
11097 */
11098 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11099 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11100 fdi_dotclock, dotclock);
11101 }
11102 }
11103
11104 static void verify_wm_state(struct drm_crtc *crtc,
11105 struct drm_crtc_state *new_state)
11106 {
11107 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11108 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11109 struct skl_pipe_wm hw_wm, *sw_wm;
11110 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11111 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11113 const enum pipe pipe = intel_crtc->pipe;
11114 int plane, level, max_level = ilk_wm_max_level(dev_priv);
11115
11116 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11117 return;
11118
11119 skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11120 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11121
11122 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11123 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11124
11125 /* planes */
11126 for_each_universal_plane(dev_priv, pipe, plane) {
11127 hw_plane_wm = &hw_wm.planes[plane];
11128 sw_plane_wm = &sw_wm->planes[plane];
11129
11130 /* Watermarks */
11131 for (level = 0; level <= max_level; level++) {
11132 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11133 &sw_plane_wm->wm[level]))
11134 continue;
11135
11136 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11137 pipe_name(pipe), plane + 1, level,
11138 sw_plane_wm->wm[level].plane_en,
11139 sw_plane_wm->wm[level].plane_res_b,
11140 sw_plane_wm->wm[level].plane_res_l,
11141 hw_plane_wm->wm[level].plane_en,
11142 hw_plane_wm->wm[level].plane_res_b,
11143 hw_plane_wm->wm[level].plane_res_l);
11144 }
11145
11146 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11147 &sw_plane_wm->trans_wm)) {
11148 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11149 pipe_name(pipe), plane + 1,
11150 sw_plane_wm->trans_wm.plane_en,
11151 sw_plane_wm->trans_wm.plane_res_b,
11152 sw_plane_wm->trans_wm.plane_res_l,
11153 hw_plane_wm->trans_wm.plane_en,
11154 hw_plane_wm->trans_wm.plane_res_b,
11155 hw_plane_wm->trans_wm.plane_res_l);
11156 }
11157
11158 /* DDB */
11159 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11160 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11161
11162 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11163 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11164 pipe_name(pipe), plane + 1,
11165 sw_ddb_entry->start, sw_ddb_entry->end,
11166 hw_ddb_entry->start, hw_ddb_entry->end);
11167 }
11168 }
11169
11170 /*
11171 * cursor
11172 * If the cursor plane isn't active, we may not have updated it's ddb
11173 * allocation. In that case since the ddb allocation will be updated
11174 * once the plane becomes visible, we can skip this check
11175 */
11176 if (1) {
11177 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11178 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11179
11180 /* Watermarks */
11181 for (level = 0; level <= max_level; level++) {
11182 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11183 &sw_plane_wm->wm[level]))
11184 continue;
11185
11186 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11187 pipe_name(pipe), level,
11188 sw_plane_wm->wm[level].plane_en,
11189 sw_plane_wm->wm[level].plane_res_b,
11190 sw_plane_wm->wm[level].plane_res_l,
11191 hw_plane_wm->wm[level].plane_en,
11192 hw_plane_wm->wm[level].plane_res_b,
11193 hw_plane_wm->wm[level].plane_res_l);
11194 }
11195
11196 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11197 &sw_plane_wm->trans_wm)) {
11198 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11199 pipe_name(pipe),
11200 sw_plane_wm->trans_wm.plane_en,
11201 sw_plane_wm->trans_wm.plane_res_b,
11202 sw_plane_wm->trans_wm.plane_res_l,
11203 hw_plane_wm->trans_wm.plane_en,
11204 hw_plane_wm->trans_wm.plane_res_b,
11205 hw_plane_wm->trans_wm.plane_res_l);
11206 }
11207
11208 /* DDB */
11209 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11210 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11211
11212 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11213 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11214 pipe_name(pipe),
11215 sw_ddb_entry->start, sw_ddb_entry->end,
11216 hw_ddb_entry->start, hw_ddb_entry->end);
11217 }
11218 }
11219 }
11220
11221 static void
11222 verify_connector_state(struct drm_device *dev,
11223 struct drm_atomic_state *state,
11224 struct drm_crtc *crtc)
11225 {
11226 struct drm_connector *connector;
11227 struct drm_connector_state *new_conn_state;
11228 int i;
11229
11230 for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11231 struct drm_encoder *encoder = connector->encoder;
11232 struct drm_crtc_state *crtc_state = NULL;
11233
11234 if (new_conn_state->crtc != crtc)
11235 continue;
11236
11237 if (crtc)
11238 crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
11239
11240 intel_connector_verify_state(crtc_state, new_conn_state);
11241
11242 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11243 "connector's atomic encoder doesn't match legacy encoder\n");
11244 }
11245 }
11246
11247 static void
11248 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11249 {
11250 struct intel_encoder *encoder;
11251 struct drm_connector *connector;
11252 struct drm_connector_state *old_conn_state, *new_conn_state;
11253 int i;
11254
11255 for_each_intel_encoder(dev, encoder) {
11256 bool enabled = false, found = false;
11257 enum pipe pipe;
11258
11259 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11260 encoder->base.base.id,
11261 encoder->base.name);
11262
11263 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11264 new_conn_state, i) {
11265 if (old_conn_state->best_encoder == &encoder->base)
11266 found = true;
11267
11268 if (new_conn_state->best_encoder != &encoder->base)
11269 continue;
11270 found = enabled = true;
11271
11272 I915_STATE_WARN(new_conn_state->crtc !=
11273 encoder->base.crtc,
11274 "connector's crtc doesn't match encoder crtc\n");
11275 }
11276
11277 if (!found)
11278 continue;
11279
11280 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11281 "encoder's enabled state mismatch "
11282 "(expected %i, found %i)\n",
11283 !!encoder->base.crtc, enabled);
11284
11285 if (!encoder->base.crtc) {
11286 bool active;
11287
11288 active = encoder->get_hw_state(encoder, &pipe);
11289 I915_STATE_WARN(active,
11290 "encoder detached but still enabled on pipe %c.\n",
11291 pipe_name(pipe));
11292 }
11293 }
11294 }
11295
11296 static void
11297 verify_crtc_state(struct drm_crtc *crtc,
11298 struct drm_crtc_state *old_crtc_state,
11299 struct drm_crtc_state *new_crtc_state)
11300 {
11301 struct drm_device *dev = crtc->dev;
11302 struct drm_i915_private *dev_priv = to_i915(dev);
11303 struct intel_encoder *encoder;
11304 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11305 struct intel_crtc_state *pipe_config, *sw_config;
11306 struct drm_atomic_state *old_state;
11307 bool active;
11308
11309 old_state = old_crtc_state->state;
11310 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
11311 pipe_config = to_intel_crtc_state(old_crtc_state);
11312 memset(pipe_config, 0, sizeof(*pipe_config));
11313 pipe_config->base.crtc = crtc;
11314 pipe_config->base.state = old_state;
11315
11316 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
11317
11318 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
11319
11320 /* we keep both pipes enabled on 830 */
11321 if (IS_I830(dev_priv))
11322 active = new_crtc_state->active;
11323
11324 I915_STATE_WARN(new_crtc_state->active != active,
11325 "crtc active state doesn't match with hw state "
11326 "(expected %i, found %i)\n", new_crtc_state->active, active);
11327
11328 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
11329 "transitional active state does not match atomic hw state "
11330 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
11331
11332 for_each_encoder_on_crtc(dev, crtc, encoder) {
11333 enum pipe pipe;
11334
11335 active = encoder->get_hw_state(encoder, &pipe);
11336 I915_STATE_WARN(active != new_crtc_state->active,
11337 "[ENCODER:%i] active %i with crtc active %i\n",
11338 encoder->base.base.id, active, new_crtc_state->active);
11339
11340 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
11341 "Encoder connected to wrong pipe %c\n",
11342 pipe_name(pipe));
11343
11344 if (active) {
11345 pipe_config->output_types |= 1 << encoder->type;
11346 encoder->get_config(encoder, pipe_config);
11347 }
11348 }
11349
11350 intel_crtc_compute_pixel_rate(pipe_config);
11351
11352 if (!new_crtc_state->active)
11353 return;
11354
11355 intel_pipe_config_sanity_check(dev_priv, pipe_config);
11356
11357 sw_config = to_intel_crtc_state(new_crtc_state);
11358 if (!intel_pipe_config_compare(dev_priv, sw_config,
11359 pipe_config, false)) {
11360 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11361 intel_dump_pipe_config(intel_crtc, pipe_config,
11362 "[hw state]");
11363 intel_dump_pipe_config(intel_crtc, sw_config,
11364 "[sw state]");
11365 }
11366 }
11367
11368 static void
11369 verify_single_dpll_state(struct drm_i915_private *dev_priv,
11370 struct intel_shared_dpll *pll,
11371 struct drm_crtc *crtc,
11372 struct drm_crtc_state *new_state)
11373 {
11374 struct intel_dpll_hw_state dpll_hw_state;
11375 unsigned crtc_mask;
11376 bool active;
11377
11378 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11379
11380 DRM_DEBUG_KMS("%s\n", pll->name);
11381
11382 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
11383
11384 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
11385 I915_STATE_WARN(!pll->on && pll->active_mask,
11386 "pll in active use but not on in sw tracking\n");
11387 I915_STATE_WARN(pll->on && !pll->active_mask,
11388 "pll is on but not used by any active crtc\n");
11389 I915_STATE_WARN(pll->on != active,
11390 "pll on state mismatch (expected %i, found %i)\n",
11391 pll->on, active);
11392 }
11393
11394 if (!crtc) {
11395 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
11396 "more active pll users than references: %x vs %x\n",
11397 pll->active_mask, pll->state.crtc_mask);
11398
11399 return;
11400 }
11401
11402 crtc_mask = 1 << drm_crtc_index(crtc);
11403
11404 if (new_state->active)
11405 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
11406 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
11407 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11408 else
11409 I915_STATE_WARN(pll->active_mask & crtc_mask,
11410 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
11411 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11412
11413 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
11414 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
11415 crtc_mask, pll->state.crtc_mask);
11416
11417 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
11418 &dpll_hw_state,
11419 sizeof(dpll_hw_state)),
11420 "pll hw state mismatch\n");
11421 }
11422
11423 static void
11424 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
11425 struct drm_crtc_state *old_crtc_state,
11426 struct drm_crtc_state *new_crtc_state)
11427 {
11428 struct drm_i915_private *dev_priv = to_i915(dev);
11429 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
11430 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
11431
11432 if (new_state->shared_dpll)
11433 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
11434
11435 if (old_state->shared_dpll &&
11436 old_state->shared_dpll != new_state->shared_dpll) {
11437 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
11438 struct intel_shared_dpll *pll = old_state->shared_dpll;
11439
11440 I915_STATE_WARN(pll->active_mask & crtc_mask,
11441 "pll active mismatch (didn't expect pipe %c in active mask)\n",
11442 pipe_name(drm_crtc_index(crtc)));
11443 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
11444 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
11445 pipe_name(drm_crtc_index(crtc)));
11446 }
11447 }
11448
11449 static void
11450 intel_modeset_verify_crtc(struct drm_crtc *crtc,
11451 struct drm_atomic_state *state,
11452 struct drm_crtc_state *old_state,
11453 struct drm_crtc_state *new_state)
11454 {
11455 if (!needs_modeset(new_state) &&
11456 !to_intel_crtc_state(new_state)->update_pipe)
11457 return;
11458
11459 verify_wm_state(crtc, new_state);
11460 verify_connector_state(crtc->dev, state, crtc);
11461 verify_crtc_state(crtc, old_state, new_state);
11462 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
11463 }
11464
11465 static void
11466 verify_disabled_dpll_state(struct drm_device *dev)
11467 {
11468 struct drm_i915_private *dev_priv = to_i915(dev);
11469 int i;
11470
11471 for (i = 0; i < dev_priv->num_shared_dpll; i++)
11472 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
11473 }
11474
11475 static void
11476 intel_modeset_verify_disabled(struct drm_device *dev,
11477 struct drm_atomic_state *state)
11478 {
11479 verify_encoder_state(dev, state);
11480 verify_connector_state(dev, state, NULL);
11481 verify_disabled_dpll_state(dev);
11482 }
11483
11484 static void update_scanline_offset(struct intel_crtc *crtc)
11485 {
11486 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11487
11488 /*
11489 * The scanline counter increments at the leading edge of hsync.
11490 *
11491 * On most platforms it starts counting from vtotal-1 on the
11492 * first active line. That means the scanline counter value is
11493 * always one less than what we would expect. Ie. just after
11494 * start of vblank, which also occurs at start of hsync (on the
11495 * last active line), the scanline counter will read vblank_start-1.
11496 *
11497 * On gen2 the scanline counter starts counting from 1 instead
11498 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11499 * to keep the value positive), instead of adding one.
11500 *
11501 * On HSW+ the behaviour of the scanline counter depends on the output
11502 * type. For DP ports it behaves like most other platforms, but on HDMI
11503 * there's an extra 1 line difference. So we need to add two instead of
11504 * one to the value.
11505 *
11506 * On VLV/CHV DSI the scanline counter would appear to increment
11507 * approx. 1/3 of a scanline before start of vblank. Unfortunately
11508 * that means we can't tell whether we're in vblank or not while
11509 * we're on that particular line. We must still set scanline_offset
11510 * to 1 so that the vblank timestamps come out correct when we query
11511 * the scanline counter from within the vblank interrupt handler.
11512 * However if queried just before the start of vblank we'll get an
11513 * answer that's slightly in the future.
11514 */
11515 if (IS_GEN2(dev_priv)) {
11516 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
11517 int vtotal;
11518
11519 vtotal = adjusted_mode->crtc_vtotal;
11520 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
11521 vtotal /= 2;
11522
11523 crtc->scanline_offset = vtotal - 1;
11524 } else if (HAS_DDI(dev_priv) &&
11525 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
11526 crtc->scanline_offset = 2;
11527 } else
11528 crtc->scanline_offset = 1;
11529 }
11530
11531 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
11532 {
11533 struct drm_device *dev = state->dev;
11534 struct drm_i915_private *dev_priv = to_i915(dev);
11535 struct drm_crtc *crtc;
11536 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11537 int i;
11538
11539 if (!dev_priv->display.crtc_compute_clock)
11540 return;
11541
11542 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11543 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11544 struct intel_shared_dpll *old_dpll =
11545 to_intel_crtc_state(old_crtc_state)->shared_dpll;
11546
11547 if (!needs_modeset(new_crtc_state))
11548 continue;
11549
11550 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
11551
11552 if (!old_dpll)
11553 continue;
11554
11555 intel_release_shared_dpll(old_dpll, intel_crtc, state);
11556 }
11557 }
11558
11559 /*
11560 * This implements the workaround described in the "notes" section of the mode
11561 * set sequence documentation. When going from no pipes or single pipe to
11562 * multiple pipes, and planes are enabled after the pipe, we need to wait at
11563 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
11564 */
11565 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
11566 {
11567 struct drm_crtc_state *crtc_state;
11568 struct intel_crtc *intel_crtc;
11569 struct drm_crtc *crtc;
11570 struct intel_crtc_state *first_crtc_state = NULL;
11571 struct intel_crtc_state *other_crtc_state = NULL;
11572 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
11573 int i;
11574
11575 /* look at all crtc's that are going to be enabled in during modeset */
11576 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
11577 intel_crtc = to_intel_crtc(crtc);
11578
11579 if (!crtc_state->active || !needs_modeset(crtc_state))
11580 continue;
11581
11582 if (first_crtc_state) {
11583 other_crtc_state = to_intel_crtc_state(crtc_state);
11584 break;
11585 } else {
11586 first_crtc_state = to_intel_crtc_state(crtc_state);
11587 first_pipe = intel_crtc->pipe;
11588 }
11589 }
11590
11591 /* No workaround needed? */
11592 if (!first_crtc_state)
11593 return 0;
11594
11595 /* w/a possibly needed, check how many crtc's are already enabled. */
11596 for_each_intel_crtc(state->dev, intel_crtc) {
11597 struct intel_crtc_state *pipe_config;
11598
11599 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
11600 if (IS_ERR(pipe_config))
11601 return PTR_ERR(pipe_config);
11602
11603 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
11604
11605 if (!pipe_config->base.active ||
11606 needs_modeset(&pipe_config->base))
11607 continue;
11608
11609 /* 2 or more enabled crtcs means no need for w/a */
11610 if (enabled_pipe != INVALID_PIPE)
11611 return 0;
11612
11613 enabled_pipe = intel_crtc->pipe;
11614 }
11615
11616 if (enabled_pipe != INVALID_PIPE)
11617 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
11618 else if (other_crtc_state)
11619 other_crtc_state->hsw_workaround_pipe = first_pipe;
11620
11621 return 0;
11622 }
11623
11624 static int intel_lock_all_pipes(struct drm_atomic_state *state)
11625 {
11626 struct drm_crtc *crtc;
11627
11628 /* Add all pipes to the state */
11629 for_each_crtc(state->dev, crtc) {
11630 struct drm_crtc_state *crtc_state;
11631
11632 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11633 if (IS_ERR(crtc_state))
11634 return PTR_ERR(crtc_state);
11635 }
11636
11637 return 0;
11638 }
11639
11640 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
11641 {
11642 struct drm_crtc *crtc;
11643
11644 /*
11645 * Add all pipes to the state, and force
11646 * a modeset on all the active ones.
11647 */
11648 for_each_crtc(state->dev, crtc) {
11649 struct drm_crtc_state *crtc_state;
11650 int ret;
11651
11652 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11653 if (IS_ERR(crtc_state))
11654 return PTR_ERR(crtc_state);
11655
11656 if (!crtc_state->active || needs_modeset(crtc_state))
11657 continue;
11658
11659 crtc_state->mode_changed = true;
11660
11661 ret = drm_atomic_add_affected_connectors(state, crtc);
11662 if (ret)
11663 return ret;
11664
11665 ret = drm_atomic_add_affected_planes(state, crtc);
11666 if (ret)
11667 return ret;
11668 }
11669
11670 return 0;
11671 }
11672
11673 static int intel_modeset_checks(struct drm_atomic_state *state)
11674 {
11675 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
11676 struct drm_i915_private *dev_priv = to_i915(state->dev);
11677 struct drm_crtc *crtc;
11678 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11679 int ret = 0, i;
11680
11681 if (!check_digital_port_conflicts(state)) {
11682 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11683 return -EINVAL;
11684 }
11685
11686 intel_state->modeset = true;
11687 intel_state->active_crtcs = dev_priv->active_crtcs;
11688 intel_state->cdclk.logical = dev_priv->cdclk.logical;
11689 intel_state->cdclk.actual = dev_priv->cdclk.actual;
11690
11691 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11692 if (new_crtc_state->active)
11693 intel_state->active_crtcs |= 1 << i;
11694 else
11695 intel_state->active_crtcs &= ~(1 << i);
11696
11697 if (old_crtc_state->active != new_crtc_state->active)
11698 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
11699 }
11700
11701 /*
11702 * See if the config requires any additional preparation, e.g.
11703 * to adjust global state with pipes off. We need to do this
11704 * here so we can get the modeset_pipe updated config for the new
11705 * mode set on this crtc. For other crtcs we need to use the
11706 * adjusted_mode bits in the crtc directly.
11707 */
11708 if (dev_priv->display.modeset_calc_cdclk) {
11709 ret = dev_priv->display.modeset_calc_cdclk(state);
11710 if (ret < 0)
11711 return ret;
11712
11713 /*
11714 * Writes to dev_priv->cdclk.logical must protected by
11715 * holding all the crtc locks, even if we don't end up
11716 * touching the hardware
11717 */
11718 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
11719 &intel_state->cdclk.logical)) {
11720 ret = intel_lock_all_pipes(state);
11721 if (ret < 0)
11722 return ret;
11723 }
11724
11725 /* All pipes must be switched off while we change the cdclk. */
11726 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
11727 &intel_state->cdclk.actual)) {
11728 ret = intel_modeset_all_pipes(state);
11729 if (ret < 0)
11730 return ret;
11731 }
11732
11733 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
11734 intel_state->cdclk.logical.cdclk,
11735 intel_state->cdclk.actual.cdclk);
11736 } else {
11737 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
11738 }
11739
11740 intel_modeset_clear_plls(state);
11741
11742 if (IS_HASWELL(dev_priv))
11743 return haswell_mode_set_planes_workaround(state);
11744
11745 return 0;
11746 }
11747
11748 /*
11749 * Handle calculation of various watermark data at the end of the atomic check
11750 * phase. The code here should be run after the per-crtc and per-plane 'check'
11751 * handlers to ensure that all derived state has been updated.
11752 */
11753 static int calc_watermark_data(struct drm_atomic_state *state)
11754 {
11755 struct drm_device *dev = state->dev;
11756 struct drm_i915_private *dev_priv = to_i915(dev);
11757
11758 /* Is there platform-specific watermark information to calculate? */
11759 if (dev_priv->display.compute_global_watermarks)
11760 return dev_priv->display.compute_global_watermarks(state);
11761
11762 return 0;
11763 }
11764
11765 /**
11766 * intel_atomic_check - validate state object
11767 * @dev: drm device
11768 * @state: state to validate
11769 */
11770 static int intel_atomic_check(struct drm_device *dev,
11771 struct drm_atomic_state *state)
11772 {
11773 struct drm_i915_private *dev_priv = to_i915(dev);
11774 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
11775 struct drm_crtc *crtc;
11776 struct drm_crtc_state *old_crtc_state, *crtc_state;
11777 int ret, i;
11778 bool any_ms = false;
11779
11780 ret = drm_atomic_helper_check_modeset(dev, state);
11781 if (ret)
11782 return ret;
11783
11784 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
11785 struct intel_crtc_state *pipe_config =
11786 to_intel_crtc_state(crtc_state);
11787
11788 /* Catch I915_MODE_FLAG_INHERITED */
11789 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
11790 crtc_state->mode_changed = true;
11791
11792 if (!needs_modeset(crtc_state))
11793 continue;
11794
11795 if (!crtc_state->enable) {
11796 any_ms = true;
11797 continue;
11798 }
11799
11800 /* FIXME: For only active_changed we shouldn't need to do any
11801 * state recomputation at all. */
11802
11803 ret = drm_atomic_add_affected_connectors(state, crtc);
11804 if (ret)
11805 return ret;
11806
11807 ret = intel_modeset_pipe_config(crtc, pipe_config);
11808 if (ret) {
11809 intel_dump_pipe_config(to_intel_crtc(crtc),
11810 pipe_config, "[failed]");
11811 return ret;
11812 }
11813
11814 if (i915.fastboot &&
11815 intel_pipe_config_compare(dev_priv,
11816 to_intel_crtc_state(old_crtc_state),
11817 pipe_config, true)) {
11818 crtc_state->mode_changed = false;
11819 pipe_config->update_pipe = true;
11820 }
11821
11822 if (needs_modeset(crtc_state))
11823 any_ms = true;
11824
11825 ret = drm_atomic_add_affected_planes(state, crtc);
11826 if (ret)
11827 return ret;
11828
11829 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11830 needs_modeset(crtc_state) ?
11831 "[modeset]" : "[fastset]");
11832 }
11833
11834 if (any_ms) {
11835 ret = intel_modeset_checks(state);
11836
11837 if (ret)
11838 return ret;
11839 } else {
11840 intel_state->cdclk.logical = dev_priv->cdclk.logical;
11841 }
11842
11843 ret = drm_atomic_helper_check_planes(dev, state);
11844 if (ret)
11845 return ret;
11846
11847 intel_fbc_choose_crtc(dev_priv, state);
11848 return calc_watermark_data(state);
11849 }
11850
11851 static int intel_atomic_prepare_commit(struct drm_device *dev,
11852 struct drm_atomic_state *state)
11853 {
11854 return drm_atomic_helper_prepare_planes(dev, state);
11855 }
11856
11857 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
11858 {
11859 struct drm_device *dev = crtc->base.dev;
11860
11861 if (!dev->max_vblank_count)
11862 return drm_crtc_accurate_vblank_count(&crtc->base);
11863
11864 return dev->driver->get_vblank_counter(dev, crtc->pipe);
11865 }
11866
11867 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
11868 struct drm_i915_private *dev_priv,
11869 unsigned crtc_mask)
11870 {
11871 unsigned last_vblank_count[I915_MAX_PIPES];
11872 enum pipe pipe;
11873 int ret;
11874
11875 if (!crtc_mask)
11876 return;
11877
11878 for_each_pipe(dev_priv, pipe) {
11879 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
11880 pipe);
11881
11882 if (!((1 << pipe) & crtc_mask))
11883 continue;
11884
11885 ret = drm_crtc_vblank_get(&crtc->base);
11886 if (WARN_ON(ret != 0)) {
11887 crtc_mask &= ~(1 << pipe);
11888 continue;
11889 }
11890
11891 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
11892 }
11893
11894 for_each_pipe(dev_priv, pipe) {
11895 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
11896 pipe);
11897 long lret;
11898
11899 if (!((1 << pipe) & crtc_mask))
11900 continue;
11901
11902 lret = wait_event_timeout(dev->vblank[pipe].queue,
11903 last_vblank_count[pipe] !=
11904 drm_crtc_vblank_count(&crtc->base),
11905 msecs_to_jiffies(50));
11906
11907 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
11908
11909 drm_crtc_vblank_put(&crtc->base);
11910 }
11911 }
11912
11913 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
11914 {
11915 /* fb updated, need to unpin old fb */
11916 if (crtc_state->fb_changed)
11917 return true;
11918
11919 /* wm changes, need vblank before final wm's */
11920 if (crtc_state->update_wm_post)
11921 return true;
11922
11923 if (crtc_state->wm.need_postvbl_update)
11924 return true;
11925
11926 return false;
11927 }
11928
11929 static void intel_update_crtc(struct drm_crtc *crtc,
11930 struct drm_atomic_state *state,
11931 struct drm_crtc_state *old_crtc_state,
11932 struct drm_crtc_state *new_crtc_state,
11933 unsigned int *crtc_vblank_mask)
11934 {
11935 struct drm_device *dev = crtc->dev;
11936 struct drm_i915_private *dev_priv = to_i915(dev);
11937 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11938 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
11939 bool modeset = needs_modeset(new_crtc_state);
11940
11941 if (modeset) {
11942 update_scanline_offset(intel_crtc);
11943 dev_priv->display.crtc_enable(pipe_config, state);
11944 } else {
11945 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
11946 pipe_config);
11947 }
11948
11949 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11950 intel_fbc_enable(
11951 intel_crtc, pipe_config,
11952 to_intel_plane_state(crtc->primary->state));
11953 }
11954
11955 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
11956
11957 if (needs_vblank_wait(pipe_config))
11958 *crtc_vblank_mask |= drm_crtc_mask(crtc);
11959 }
11960
11961 static void intel_update_crtcs(struct drm_atomic_state *state,
11962 unsigned int *crtc_vblank_mask)
11963 {
11964 struct drm_crtc *crtc;
11965 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11966 int i;
11967
11968 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11969 if (!new_crtc_state->active)
11970 continue;
11971
11972 intel_update_crtc(crtc, state, old_crtc_state,
11973 new_crtc_state, crtc_vblank_mask);
11974 }
11975 }
11976
11977 static void skl_update_crtcs(struct drm_atomic_state *state,
11978 unsigned int *crtc_vblank_mask)
11979 {
11980 struct drm_i915_private *dev_priv = to_i915(state->dev);
11981 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
11982 struct drm_crtc *crtc;
11983 struct intel_crtc *intel_crtc;
11984 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11985 struct intel_crtc_state *cstate;
11986 unsigned int updated = 0;
11987 bool progress;
11988 enum pipe pipe;
11989 int i;
11990
11991 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
11992
11993 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
11994 /* ignore allocations for crtc's that have been turned off. */
11995 if (new_crtc_state->active)
11996 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
11997
11998 /*
11999 * Whenever the number of active pipes changes, we need to make sure we
12000 * update the pipes in the right order so that their ddb allocations
12001 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12002 * cause pipe underruns and other bad stuff.
12003 */
12004 do {
12005 progress = false;
12006
12007 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12008 bool vbl_wait = false;
12009 unsigned int cmask = drm_crtc_mask(crtc);
12010
12011 intel_crtc = to_intel_crtc(crtc);
12012 cstate = to_intel_crtc_state(crtc->state);
12013 pipe = intel_crtc->pipe;
12014
12015 if (updated & cmask || !cstate->base.active)
12016 continue;
12017
12018 if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
12019 continue;
12020
12021 updated |= cmask;
12022 entries[i] = &cstate->wm.skl.ddb;
12023
12024 /*
12025 * If this is an already active pipe, it's DDB changed,
12026 * and this isn't the last pipe that needs updating
12027 * then we need to wait for a vblank to pass for the
12028 * new ddb allocation to take effect.
12029 */
12030 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12031 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12032 !new_crtc_state->active_changed &&
12033 intel_state->wm_results.dirty_pipes != updated)
12034 vbl_wait = true;
12035
12036 intel_update_crtc(crtc, state, old_crtc_state,
12037 new_crtc_state, crtc_vblank_mask);
12038
12039 if (vbl_wait)
12040 intel_wait_for_vblank(dev_priv, pipe);
12041
12042 progress = true;
12043 }
12044 } while (progress);
12045 }
12046
12047 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12048 {
12049 struct intel_atomic_state *state, *next;
12050 struct llist_node *freed;
12051
12052 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12053 llist_for_each_entry_safe(state, next, freed, freed)
12054 drm_atomic_state_put(&state->base);
12055 }
12056
12057 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12058 {
12059 struct drm_i915_private *dev_priv =
12060 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12061
12062 intel_atomic_helper_free_state(dev_priv);
12063 }
12064
12065 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12066 {
12067 struct drm_device *dev = state->dev;
12068 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12069 struct drm_i915_private *dev_priv = to_i915(dev);
12070 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12071 struct drm_crtc *crtc;
12072 struct intel_crtc_state *intel_cstate;
12073 bool hw_check = intel_state->modeset;
12074 u64 put_domains[I915_MAX_PIPES] = {};
12075 unsigned crtc_vblank_mask = 0;
12076 int i;
12077
12078 drm_atomic_helper_wait_for_dependencies(state);
12079
12080 if (intel_state->modeset)
12081 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12082
12083 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12085
12086 if (needs_modeset(new_crtc_state) ||
12087 to_intel_crtc_state(new_crtc_state)->update_pipe) {
12088 hw_check = true;
12089
12090 put_domains[to_intel_crtc(crtc)->pipe] =
12091 modeset_get_crtc_power_domains(crtc,
12092 to_intel_crtc_state(new_crtc_state));
12093 }
12094
12095 if (!needs_modeset(new_crtc_state))
12096 continue;
12097
12098 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12099 to_intel_crtc_state(new_crtc_state));
12100
12101 if (old_crtc_state->active) {
12102 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12103 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12104 intel_crtc->active = false;
12105 intel_fbc_disable(intel_crtc);
12106 intel_disable_shared_dpll(intel_crtc);
12107
12108 /*
12109 * Underruns don't always raise
12110 * interrupts, so check manually.
12111 */
12112 intel_check_cpu_fifo_underruns(dev_priv);
12113 intel_check_pch_fifo_underruns(dev_priv);
12114
12115 if (!crtc->state->active) {
12116 /*
12117 * Make sure we don't call initial_watermarks
12118 * for ILK-style watermark updates.
12119 *
12120 * No clue what this is supposed to achieve.
12121 */
12122 if (INTEL_GEN(dev_priv) >= 9)
12123 dev_priv->display.initial_watermarks(intel_state,
12124 to_intel_crtc_state(crtc->state));
12125 }
12126 }
12127 }
12128
12129 /* Only after disabling all output pipelines that will be changed can we
12130 * update the the output configuration. */
12131 intel_modeset_update_crtc_state(state);
12132
12133 if (intel_state->modeset) {
12134 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12135
12136 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12137
12138 /*
12139 * SKL workaround: bspec recommends we disable the SAGV when we
12140 * have more then one pipe enabled
12141 */
12142 if (!intel_can_enable_sagv(state))
12143 intel_disable_sagv(dev_priv);
12144
12145 intel_modeset_verify_disabled(dev, state);
12146 }
12147
12148 /* Complete the events for pipes that have now been disabled */
12149 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12150 bool modeset = needs_modeset(new_crtc_state);
12151
12152 /* Complete events for now disable pipes here. */
12153 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12154 spin_lock_irq(&dev->event_lock);
12155 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12156 spin_unlock_irq(&dev->event_lock);
12157
12158 new_crtc_state->event = NULL;
12159 }
12160 }
12161
12162 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12163 dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
12164
12165 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12166 * already, but still need the state for the delayed optimization. To
12167 * fix this:
12168 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12169 * - schedule that vblank worker _before_ calling hw_done
12170 * - at the start of commit_tail, cancel it _synchrously
12171 * - switch over to the vblank wait helper in the core after that since
12172 * we don't need out special handling any more.
12173 */
12174 if (!state->legacy_cursor_update)
12175 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
12176
12177 /*
12178 * Now that the vblank has passed, we can go ahead and program the
12179 * optimal watermarks on platforms that need two-step watermark
12180 * programming.
12181 *
12182 * TODO: Move this (and other cleanup) to an async worker eventually.
12183 */
12184 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12185 intel_cstate = to_intel_crtc_state(new_crtc_state);
12186
12187 if (dev_priv->display.optimize_watermarks)
12188 dev_priv->display.optimize_watermarks(intel_state,
12189 intel_cstate);
12190 }
12191
12192 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12193 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12194
12195 if (put_domains[i])
12196 modeset_put_power_domains(dev_priv, put_domains[i]);
12197
12198 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12199 }
12200
12201 if (intel_state->modeset && intel_can_enable_sagv(state))
12202 intel_enable_sagv(dev_priv);
12203
12204 drm_atomic_helper_commit_hw_done(state);
12205
12206 if (intel_state->modeset) {
12207 /* As one of the primary mmio accessors, KMS has a high
12208 * likelihood of triggering bugs in unclaimed access. After we
12209 * finish modesetting, see if an error has been flagged, and if
12210 * so enable debugging for the next modeset - and hope we catch
12211 * the culprit.
12212 */
12213 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12214 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12215 }
12216
12217 drm_atomic_helper_cleanup_planes(dev, state);
12218
12219 drm_atomic_helper_commit_cleanup_done(state);
12220
12221 drm_atomic_state_put(state);
12222
12223 intel_atomic_helper_free_state(dev_priv);
12224 }
12225
12226 static void intel_atomic_commit_work(struct work_struct *work)
12227 {
12228 struct drm_atomic_state *state =
12229 container_of(work, struct drm_atomic_state, commit_work);
12230
12231 intel_atomic_commit_tail(state);
12232 }
12233
12234 static int __i915_sw_fence_call
12235 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12236 enum i915_sw_fence_notify notify)
12237 {
12238 struct intel_atomic_state *state =
12239 container_of(fence, struct intel_atomic_state, commit_ready);
12240
12241 switch (notify) {
12242 case FENCE_COMPLETE:
12243 if (state->base.commit_work.func)
12244 queue_work(system_unbound_wq, &state->base.commit_work);
12245 break;
12246
12247 case FENCE_FREE:
12248 {
12249 struct intel_atomic_helper *helper =
12250 &to_i915(state->base.dev)->atomic_helper;
12251
12252 if (llist_add(&state->freed, &helper->free_list))
12253 schedule_work(&helper->free_work);
12254 break;
12255 }
12256 }
12257
12258 return NOTIFY_DONE;
12259 }
12260
12261 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12262 {
12263 struct drm_plane_state *old_plane_state, *new_plane_state;
12264 struct drm_plane *plane;
12265 int i;
12266
12267 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
12268 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
12269 intel_fb_obj(new_plane_state->fb),
12270 to_intel_plane(plane)->frontbuffer_bit);
12271 }
12272
12273 /**
12274 * intel_atomic_commit - commit validated state object
12275 * @dev: DRM device
12276 * @state: the top-level driver state object
12277 * @nonblock: nonblocking commit
12278 *
12279 * This function commits a top-level state object that has been validated
12280 * with drm_atomic_helper_check().
12281 *
12282 * RETURNS
12283 * Zero for success or -errno.
12284 */
12285 static int intel_atomic_commit(struct drm_device *dev,
12286 struct drm_atomic_state *state,
12287 bool nonblock)
12288 {
12289 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12290 struct drm_i915_private *dev_priv = to_i915(dev);
12291 int ret = 0;
12292
12293 ret = drm_atomic_helper_setup_commit(state, nonblock);
12294 if (ret)
12295 return ret;
12296
12297 drm_atomic_state_get(state);
12298 i915_sw_fence_init(&intel_state->commit_ready,
12299 intel_atomic_commit_ready);
12300
12301 ret = intel_atomic_prepare_commit(dev, state);
12302 if (ret) {
12303 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
12304 i915_sw_fence_commit(&intel_state->commit_ready);
12305 return ret;
12306 }
12307
12308 /*
12309 * The intel_legacy_cursor_update() fast path takes care
12310 * of avoiding the vblank waits for simple cursor
12311 * movement and flips. For cursor on/off and size changes,
12312 * we want to perform the vblank waits so that watermark
12313 * updates happen during the correct frames. Gen9+ have
12314 * double buffered watermarks and so shouldn't need this.
12315 *
12316 * Do this after drm_atomic_helper_setup_commit() and
12317 * intel_atomic_prepare_commit() because we still want
12318 * to skip the flip and fb cleanup waits. Although that
12319 * does risk yanking the mapping from under the display
12320 * engine.
12321 *
12322 * FIXME doing watermarks and fb cleanup from a vblank worker
12323 * (assuming we had any) would solve these problems.
12324 */
12325 if (INTEL_GEN(dev_priv) < 9)
12326 state->legacy_cursor_update = false;
12327
12328 ret = drm_atomic_helper_swap_state(state, true);
12329 if (ret) {
12330 i915_sw_fence_commit(&intel_state->commit_ready);
12331
12332 drm_atomic_helper_cleanup_planes(dev, state);
12333 return ret;
12334 }
12335 dev_priv->wm.distrust_bios_wm = false;
12336 intel_shared_dpll_swap_state(state);
12337 intel_atomic_track_fbs(state);
12338
12339 if (intel_state->modeset) {
12340 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
12341 sizeof(intel_state->min_pixclk));
12342 dev_priv->active_crtcs = intel_state->active_crtcs;
12343 dev_priv->cdclk.logical = intel_state->cdclk.logical;
12344 dev_priv->cdclk.actual = intel_state->cdclk.actual;
12345 }
12346
12347 drm_atomic_state_get(state);
12348 INIT_WORK(&state->commit_work,
12349 nonblock ? intel_atomic_commit_work : NULL);
12350
12351 i915_sw_fence_commit(&intel_state->commit_ready);
12352 if (!nonblock) {
12353 i915_sw_fence_wait(&intel_state->commit_ready);
12354 intel_atomic_commit_tail(state);
12355 }
12356
12357 return 0;
12358 }
12359
12360 static const struct drm_crtc_funcs intel_crtc_funcs = {
12361 .gamma_set = drm_atomic_helper_legacy_gamma_set,
12362 .set_config = drm_atomic_helper_set_config,
12363 .destroy = intel_crtc_destroy,
12364 .page_flip = drm_atomic_helper_page_flip,
12365 .atomic_duplicate_state = intel_crtc_duplicate_state,
12366 .atomic_destroy_state = intel_crtc_destroy_state,
12367 .set_crc_source = intel_crtc_set_crc_source,
12368 };
12369
12370 /**
12371 * intel_prepare_plane_fb - Prepare fb for usage on plane
12372 * @plane: drm plane to prepare for
12373 * @fb: framebuffer to prepare for presentation
12374 *
12375 * Prepares a framebuffer for usage on a display plane. Generally this
12376 * involves pinning the underlying object and updating the frontbuffer tracking
12377 * bits. Some older platforms need special physical address handling for
12378 * cursor planes.
12379 *
12380 * Must be called with struct_mutex held.
12381 *
12382 * Returns 0 on success, negative error code on failure.
12383 */
12384 int
12385 intel_prepare_plane_fb(struct drm_plane *plane,
12386 struct drm_plane_state *new_state)
12387 {
12388 struct intel_atomic_state *intel_state =
12389 to_intel_atomic_state(new_state->state);
12390 struct drm_i915_private *dev_priv = to_i915(plane->dev);
12391 struct drm_framebuffer *fb = new_state->fb;
12392 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12393 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
12394 int ret;
12395
12396 if (old_obj) {
12397 struct drm_crtc_state *crtc_state =
12398 drm_atomic_get_existing_crtc_state(new_state->state,
12399 plane->state->crtc);
12400
12401 /* Big Hammer, we also need to ensure that any pending
12402 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
12403 * current scanout is retired before unpinning the old
12404 * framebuffer. Note that we rely on userspace rendering
12405 * into the buffer attached to the pipe they are waiting
12406 * on. If not, userspace generates a GPU hang with IPEHR
12407 * point to the MI_WAIT_FOR_EVENT.
12408 *
12409 * This should only fail upon a hung GPU, in which case we
12410 * can safely continue.
12411 */
12412 if (needs_modeset(crtc_state)) {
12413 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12414 old_obj->resv, NULL,
12415 false, 0,
12416 GFP_KERNEL);
12417 if (ret < 0)
12418 return ret;
12419 }
12420 }
12421
12422 if (new_state->fence) { /* explicit fencing */
12423 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
12424 new_state->fence,
12425 I915_FENCE_TIMEOUT,
12426 GFP_KERNEL);
12427 if (ret < 0)
12428 return ret;
12429 }
12430
12431 if (!obj)
12432 return 0;
12433
12434 ret = i915_gem_object_pin_pages(obj);
12435 if (ret)
12436 return ret;
12437
12438 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
12439 if (ret) {
12440 i915_gem_object_unpin_pages(obj);
12441 return ret;
12442 }
12443
12444 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12445 INTEL_INFO(dev_priv)->cursor_needs_physical) {
12446 const int align = intel_cursor_alignment(dev_priv);
12447
12448 ret = i915_gem_object_attach_phys(obj, align);
12449 } else {
12450 struct i915_vma *vma;
12451
12452 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
12453 if (!IS_ERR(vma))
12454 to_intel_plane_state(new_state)->vma = vma;
12455 else
12456 ret = PTR_ERR(vma);
12457 }
12458
12459 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
12460
12461 mutex_unlock(&dev_priv->drm.struct_mutex);
12462 i915_gem_object_unpin_pages(obj);
12463 if (ret)
12464 return ret;
12465
12466 if (!new_state->fence) { /* implicit fencing */
12467 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12468 obj->resv, NULL,
12469 false, I915_FENCE_TIMEOUT,
12470 GFP_KERNEL);
12471 if (ret < 0)
12472 return ret;
12473 }
12474
12475 return 0;
12476 }
12477
12478 /**
12479 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12480 * @plane: drm plane to clean up for
12481 * @fb: old framebuffer that was on plane
12482 *
12483 * Cleans up a framebuffer that has just been removed from a plane.
12484 *
12485 * Must be called with struct_mutex held.
12486 */
12487 void
12488 intel_cleanup_plane_fb(struct drm_plane *plane,
12489 struct drm_plane_state *old_state)
12490 {
12491 struct i915_vma *vma;
12492
12493 /* Should only be called after a successful intel_prepare_plane_fb()! */
12494 vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
12495 if (vma) {
12496 mutex_lock(&plane->dev->struct_mutex);
12497 intel_unpin_fb_vma(vma);
12498 mutex_unlock(&plane->dev->struct_mutex);
12499 }
12500 }
12501
12502 int
12503 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
12504 {
12505 struct drm_i915_private *dev_priv;
12506 int max_scale;
12507 int crtc_clock, max_dotclk;
12508
12509 if (!intel_crtc || !crtc_state->base.enable)
12510 return DRM_PLANE_HELPER_NO_SCALING;
12511
12512 dev_priv = to_i915(intel_crtc->base.dev);
12513
12514 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
12515 max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
12516
12517 if (IS_GEMINILAKE(dev_priv))
12518 max_dotclk *= 2;
12519
12520 if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
12521 return DRM_PLANE_HELPER_NO_SCALING;
12522
12523 /*
12524 * skl max scale is lower of:
12525 * close to 3 but not 3, -1 is for that purpose
12526 * or
12527 * cdclk/crtc_clock
12528 */
12529 max_scale = min((1 << 16) * 3 - 1,
12530 (1 << 8) * ((max_dotclk << 8) / crtc_clock));
12531
12532 return max_scale;
12533 }
12534
12535 static int
12536 intel_check_primary_plane(struct intel_plane *plane,
12537 struct intel_crtc_state *crtc_state,
12538 struct intel_plane_state *state)
12539 {
12540 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
12541 struct drm_crtc *crtc = state->base.crtc;
12542 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
12543 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
12544 bool can_position = false;
12545 int ret;
12546
12547 if (INTEL_GEN(dev_priv) >= 9) {
12548 /* use scaler when colorkey is not required */
12549 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
12550 min_scale = 1;
12551 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
12552 }
12553 can_position = true;
12554 }
12555
12556 ret = drm_plane_helper_check_state(&state->base,
12557 &state->clip,
12558 min_scale, max_scale,
12559 can_position, true);
12560 if (ret)
12561 return ret;
12562
12563 if (!state->base.fb)
12564 return 0;
12565
12566 if (INTEL_GEN(dev_priv) >= 9) {
12567 ret = skl_check_plane_surface(state);
12568 if (ret)
12569 return ret;
12570
12571 state->ctl = skl_plane_ctl(crtc_state, state);
12572 } else {
12573 ret = i9xx_check_plane_surface(state);
12574 if (ret)
12575 return ret;
12576
12577 state->ctl = i9xx_plane_ctl(crtc_state, state);
12578 }
12579
12580 return 0;
12581 }
12582
12583 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
12584 struct drm_crtc_state *old_crtc_state)
12585 {
12586 struct drm_device *dev = crtc->dev;
12587 struct drm_i915_private *dev_priv = to_i915(dev);
12588 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12589 struct intel_crtc_state *intel_cstate =
12590 to_intel_crtc_state(crtc->state);
12591 struct intel_crtc_state *old_intel_cstate =
12592 to_intel_crtc_state(old_crtc_state);
12593 struct intel_atomic_state *old_intel_state =
12594 to_intel_atomic_state(old_crtc_state->state);
12595 bool modeset = needs_modeset(crtc->state);
12596
12597 if (!modeset &&
12598 (intel_cstate->base.color_mgmt_changed ||
12599 intel_cstate->update_pipe)) {
12600 intel_color_set_csc(crtc->state);
12601 intel_color_load_luts(crtc->state);
12602 }
12603
12604 /* Perform vblank evasion around commit operation */
12605 intel_pipe_update_start(intel_crtc);
12606
12607 if (modeset)
12608 goto out;
12609
12610 if (intel_cstate->update_pipe)
12611 intel_update_pipe_config(intel_crtc, old_intel_cstate);
12612 else if (INTEL_GEN(dev_priv) >= 9)
12613 skl_detach_scalers(intel_crtc);
12614
12615 out:
12616 if (dev_priv->display.atomic_update_watermarks)
12617 dev_priv->display.atomic_update_watermarks(old_intel_state,
12618 intel_cstate);
12619 }
12620
12621 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
12622 struct drm_crtc_state *old_crtc_state)
12623 {
12624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12625
12626 intel_pipe_update_end(intel_crtc);
12627 }
12628
12629 /**
12630 * intel_plane_destroy - destroy a plane
12631 * @plane: plane to destroy
12632 *
12633 * Common destruction function for all types of planes (primary, cursor,
12634 * sprite).
12635 */
12636 void intel_plane_destroy(struct drm_plane *plane)
12637 {
12638 drm_plane_cleanup(plane);
12639 kfree(to_intel_plane(plane));
12640 }
12641
12642 const struct drm_plane_funcs intel_plane_funcs = {
12643 .update_plane = drm_atomic_helper_update_plane,
12644 .disable_plane = drm_atomic_helper_disable_plane,
12645 .destroy = intel_plane_destroy,
12646 .atomic_get_property = intel_plane_atomic_get_property,
12647 .atomic_set_property = intel_plane_atomic_set_property,
12648 .atomic_duplicate_state = intel_plane_duplicate_state,
12649 .atomic_destroy_state = intel_plane_destroy_state,
12650 };
12651
12652 static int
12653 intel_legacy_cursor_update(struct drm_plane *plane,
12654 struct drm_crtc *crtc,
12655 struct drm_framebuffer *fb,
12656 int crtc_x, int crtc_y,
12657 unsigned int crtc_w, unsigned int crtc_h,
12658 uint32_t src_x, uint32_t src_y,
12659 uint32_t src_w, uint32_t src_h,
12660 struct drm_modeset_acquire_ctx *ctx)
12661 {
12662 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
12663 int ret;
12664 struct drm_plane_state *old_plane_state, *new_plane_state;
12665 struct intel_plane *intel_plane = to_intel_plane(plane);
12666 struct drm_framebuffer *old_fb;
12667 struct drm_crtc_state *crtc_state = crtc->state;
12668 struct i915_vma *old_vma, *vma;
12669
12670 /*
12671 * When crtc is inactive or there is a modeset pending,
12672 * wait for it to complete in the slowpath
12673 */
12674 if (!crtc_state->active || needs_modeset(crtc_state) ||
12675 to_intel_crtc_state(crtc_state)->update_pipe)
12676 goto slow;
12677
12678 old_plane_state = plane->state;
12679
12680 /*
12681 * If any parameters change that may affect watermarks,
12682 * take the slowpath. Only changing fb or position should be
12683 * in the fastpath.
12684 */
12685 if (old_plane_state->crtc != crtc ||
12686 old_plane_state->src_w != src_w ||
12687 old_plane_state->src_h != src_h ||
12688 old_plane_state->crtc_w != crtc_w ||
12689 old_plane_state->crtc_h != crtc_h ||
12690 !old_plane_state->fb != !fb)
12691 goto slow;
12692
12693 new_plane_state = intel_plane_duplicate_state(plane);
12694 if (!new_plane_state)
12695 return -ENOMEM;
12696
12697 drm_atomic_set_fb_for_plane(new_plane_state, fb);
12698
12699 new_plane_state->src_x = src_x;
12700 new_plane_state->src_y = src_y;
12701 new_plane_state->src_w = src_w;
12702 new_plane_state->src_h = src_h;
12703 new_plane_state->crtc_x = crtc_x;
12704 new_plane_state->crtc_y = crtc_y;
12705 new_plane_state->crtc_w = crtc_w;
12706 new_plane_state->crtc_h = crtc_h;
12707
12708 ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
12709 to_intel_plane_state(new_plane_state));
12710 if (ret)
12711 goto out_free;
12712
12713 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
12714 if (ret)
12715 goto out_free;
12716
12717 if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
12718 int align = intel_cursor_alignment(dev_priv);
12719
12720 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
12721 if (ret) {
12722 DRM_DEBUG_KMS("failed to attach phys object\n");
12723 goto out_unlock;
12724 }
12725 } else {
12726 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
12727 if (IS_ERR(vma)) {
12728 DRM_DEBUG_KMS("failed to pin object\n");
12729
12730 ret = PTR_ERR(vma);
12731 goto out_unlock;
12732 }
12733
12734 to_intel_plane_state(new_plane_state)->vma = vma;
12735 }
12736
12737 old_fb = old_plane_state->fb;
12738 old_vma = to_intel_plane_state(old_plane_state)->vma;
12739
12740 i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
12741 intel_plane->frontbuffer_bit);
12742
12743 /* Swap plane state */
12744 new_plane_state->fence = old_plane_state->fence;
12745 *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state);
12746 new_plane_state->fence = NULL;
12747 new_plane_state->fb = old_fb;
12748 to_intel_plane_state(new_plane_state)->vma = NULL;
12749
12750 if (plane->state->visible) {
12751 trace_intel_update_plane(plane, to_intel_crtc(crtc));
12752 intel_plane->update_plane(intel_plane,
12753 to_intel_crtc_state(crtc->state),
12754 to_intel_plane_state(plane->state));
12755 } else {
12756 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
12757 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
12758 }
12759
12760 if (old_vma)
12761 intel_unpin_fb_vma(old_vma);
12762
12763 out_unlock:
12764 mutex_unlock(&dev_priv->drm.struct_mutex);
12765 out_free:
12766 intel_plane_destroy_state(plane, new_plane_state);
12767 return ret;
12768
12769 slow:
12770 return drm_atomic_helper_update_plane(plane, crtc, fb,
12771 crtc_x, crtc_y, crtc_w, crtc_h,
12772 src_x, src_y, src_w, src_h, ctx);
12773 }
12774
12775 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
12776 .update_plane = intel_legacy_cursor_update,
12777 .disable_plane = drm_atomic_helper_disable_plane,
12778 .destroy = intel_plane_destroy,
12779 .atomic_get_property = intel_plane_atomic_get_property,
12780 .atomic_set_property = intel_plane_atomic_set_property,
12781 .atomic_duplicate_state = intel_plane_duplicate_state,
12782 .atomic_destroy_state = intel_plane_destroy_state,
12783 };
12784
12785 static struct intel_plane *
12786 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
12787 {
12788 struct intel_plane *primary = NULL;
12789 struct intel_plane_state *state = NULL;
12790 const uint32_t *intel_primary_formats;
12791 unsigned int supported_rotations;
12792 unsigned int num_formats;
12793 int ret;
12794
12795 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12796 if (!primary) {
12797 ret = -ENOMEM;
12798 goto fail;
12799 }
12800
12801 state = intel_create_plane_state(&primary->base);
12802 if (!state) {
12803 ret = -ENOMEM;
12804 goto fail;
12805 }
12806
12807 primary->base.state = &state->base;
12808
12809 primary->can_scale = false;
12810 primary->max_downscale = 1;
12811 if (INTEL_GEN(dev_priv) >= 9) {
12812 primary->can_scale = true;
12813 state->scaler_id = -1;
12814 }
12815 primary->pipe = pipe;
12816 /*
12817 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
12818 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
12819 */
12820 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
12821 primary->plane = (enum plane) !pipe;
12822 else
12823 primary->plane = (enum plane) pipe;
12824 primary->id = PLANE_PRIMARY;
12825 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
12826 primary->check_plane = intel_check_primary_plane;
12827
12828 if (INTEL_GEN(dev_priv) >= 9) {
12829 intel_primary_formats = skl_primary_formats;
12830 num_formats = ARRAY_SIZE(skl_primary_formats);
12831
12832 primary->update_plane = skylake_update_primary_plane;
12833 primary->disable_plane = skylake_disable_primary_plane;
12834 } else if (INTEL_GEN(dev_priv) >= 4) {
12835 intel_primary_formats = i965_primary_formats;
12836 num_formats = ARRAY_SIZE(i965_primary_formats);
12837
12838 primary->update_plane = i9xx_update_primary_plane;
12839 primary->disable_plane = i9xx_disable_primary_plane;
12840 } else {
12841 intel_primary_formats = i8xx_primary_formats;
12842 num_formats = ARRAY_SIZE(i8xx_primary_formats);
12843
12844 primary->update_plane = i9xx_update_primary_plane;
12845 primary->disable_plane = i9xx_disable_primary_plane;
12846 }
12847
12848 if (INTEL_GEN(dev_priv) >= 9)
12849 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
12850 0, &intel_plane_funcs,
12851 intel_primary_formats, num_formats,
12852 NULL,
12853 DRM_PLANE_TYPE_PRIMARY,
12854 "plane 1%c", pipe_name(pipe));
12855 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
12856 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
12857 0, &intel_plane_funcs,
12858 intel_primary_formats, num_formats,
12859 NULL,
12860 DRM_PLANE_TYPE_PRIMARY,
12861 "primary %c", pipe_name(pipe));
12862 else
12863 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
12864 0, &intel_plane_funcs,
12865 intel_primary_formats, num_formats,
12866 NULL,
12867 DRM_PLANE_TYPE_PRIMARY,
12868 "plane %c", plane_name(primary->plane));
12869 if (ret)
12870 goto fail;
12871
12872 if (INTEL_GEN(dev_priv) >= 9) {
12873 supported_rotations =
12874 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
12875 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
12876 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
12877 supported_rotations =
12878 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
12879 DRM_MODE_REFLECT_X;
12880 } else if (INTEL_GEN(dev_priv) >= 4) {
12881 supported_rotations =
12882 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
12883 } else {
12884 supported_rotations = DRM_MODE_ROTATE_0;
12885 }
12886
12887 if (INTEL_GEN(dev_priv) >= 4)
12888 drm_plane_create_rotation_property(&primary->base,
12889 DRM_MODE_ROTATE_0,
12890 supported_rotations);
12891
12892 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12893
12894 return primary;
12895
12896 fail:
12897 kfree(state);
12898 kfree(primary);
12899
12900 return ERR_PTR(ret);
12901 }
12902
12903 static struct intel_plane *
12904 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
12905 enum pipe pipe)
12906 {
12907 struct intel_plane *cursor = NULL;
12908 struct intel_plane_state *state = NULL;
12909 int ret;
12910
12911 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12912 if (!cursor) {
12913 ret = -ENOMEM;
12914 goto fail;
12915 }
12916
12917 state = intel_create_plane_state(&cursor->base);
12918 if (!state) {
12919 ret = -ENOMEM;
12920 goto fail;
12921 }
12922
12923 cursor->base.state = &state->base;
12924
12925 cursor->can_scale = false;
12926 cursor->max_downscale = 1;
12927 cursor->pipe = pipe;
12928 cursor->plane = pipe;
12929 cursor->id = PLANE_CURSOR;
12930 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
12931
12932 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
12933 cursor->update_plane = i845_update_cursor;
12934 cursor->disable_plane = i845_disable_cursor;
12935 cursor->check_plane = i845_check_cursor;
12936 } else {
12937 cursor->update_plane = i9xx_update_cursor;
12938 cursor->disable_plane = i9xx_disable_cursor;
12939 cursor->check_plane = i9xx_check_cursor;
12940 }
12941
12942 cursor->cursor.base = ~0;
12943 cursor->cursor.cntl = ~0;
12944
12945 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
12946 cursor->cursor.size = ~0;
12947
12948 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
12949 0, &intel_cursor_plane_funcs,
12950 intel_cursor_formats,
12951 ARRAY_SIZE(intel_cursor_formats),
12952 NULL, DRM_PLANE_TYPE_CURSOR,
12953 "cursor %c", pipe_name(pipe));
12954 if (ret)
12955 goto fail;
12956
12957 if (INTEL_GEN(dev_priv) >= 4)
12958 drm_plane_create_rotation_property(&cursor->base,
12959 DRM_MODE_ROTATE_0,
12960 DRM_MODE_ROTATE_0 |
12961 DRM_MODE_ROTATE_180);
12962
12963 if (INTEL_GEN(dev_priv) >= 9)
12964 state->scaler_id = -1;
12965
12966 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12967
12968 return cursor;
12969
12970 fail:
12971 kfree(state);
12972 kfree(cursor);
12973
12974 return ERR_PTR(ret);
12975 }
12976
12977 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
12978 struct intel_crtc_state *crtc_state)
12979 {
12980 struct intel_crtc_scaler_state *scaler_state =
12981 &crtc_state->scaler_state;
12982 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12983 int i;
12984
12985 crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
12986 if (!crtc->num_scalers)
12987 return;
12988
12989 for (i = 0; i < crtc->num_scalers; i++) {
12990 struct intel_scaler *scaler = &scaler_state->scalers[i];
12991
12992 scaler->in_use = 0;
12993 scaler->mode = PS_SCALER_MODE_DYN;
12994 }
12995
12996 scaler_state->scaler_id = -1;
12997 }
12998
12999 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13000 {
13001 struct intel_crtc *intel_crtc;
13002 struct intel_crtc_state *crtc_state = NULL;
13003 struct intel_plane *primary = NULL;
13004 struct intel_plane *cursor = NULL;
13005 int sprite, ret;
13006
13007 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13008 if (!intel_crtc)
13009 return -ENOMEM;
13010
13011 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13012 if (!crtc_state) {
13013 ret = -ENOMEM;
13014 goto fail;
13015 }
13016 intel_crtc->config = crtc_state;
13017 intel_crtc->base.state = &crtc_state->base;
13018 crtc_state->base.crtc = &intel_crtc->base;
13019
13020 primary = intel_primary_plane_create(dev_priv, pipe);
13021 if (IS_ERR(primary)) {
13022 ret = PTR_ERR(primary);
13023 goto fail;
13024 }
13025 intel_crtc->plane_ids_mask |= BIT(primary->id);
13026
13027 for_each_sprite(dev_priv, pipe, sprite) {
13028 struct intel_plane *plane;
13029
13030 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13031 if (IS_ERR(plane)) {
13032 ret = PTR_ERR(plane);
13033 goto fail;
13034 }
13035 intel_crtc->plane_ids_mask |= BIT(plane->id);
13036 }
13037
13038 cursor = intel_cursor_plane_create(dev_priv, pipe);
13039 if (IS_ERR(cursor)) {
13040 ret = PTR_ERR(cursor);
13041 goto fail;
13042 }
13043 intel_crtc->plane_ids_mask |= BIT(cursor->id);
13044
13045 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13046 &primary->base, &cursor->base,
13047 &intel_crtc_funcs,
13048 "pipe %c", pipe_name(pipe));
13049 if (ret)
13050 goto fail;
13051
13052 intel_crtc->pipe = pipe;
13053 intel_crtc->plane = primary->plane;
13054
13055 /* initialize shared scalers */
13056 intel_crtc_init_scalers(intel_crtc, crtc_state);
13057
13058 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13059 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13060 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13061 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13062
13063 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13064
13065 intel_color_init(&intel_crtc->base);
13066
13067 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13068
13069 return 0;
13070
13071 fail:
13072 /*
13073 * drm_mode_config_cleanup() will free up any
13074 * crtcs/planes already initialized.
13075 */
13076 kfree(crtc_state);
13077 kfree(intel_crtc);
13078
13079 return ret;
13080 }
13081
13082 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13083 {
13084 struct drm_device *dev = connector->base.dev;
13085
13086 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13087
13088 if (!connector->base.state->crtc)
13089 return INVALID_PIPE;
13090
13091 return to_intel_crtc(connector->base.state->crtc)->pipe;
13092 }
13093
13094 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13095 struct drm_file *file)
13096 {
13097 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13098 struct drm_crtc *drmmode_crtc;
13099 struct intel_crtc *crtc;
13100
13101 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13102 if (!drmmode_crtc)
13103 return -ENOENT;
13104
13105 crtc = to_intel_crtc(drmmode_crtc);
13106 pipe_from_crtc_id->pipe = crtc->pipe;
13107
13108 return 0;
13109 }
13110
13111 static int intel_encoder_clones(struct intel_encoder *encoder)
13112 {
13113 struct drm_device *dev = encoder->base.dev;
13114 struct intel_encoder *source_encoder;
13115 int index_mask = 0;
13116 int entry = 0;
13117
13118 for_each_intel_encoder(dev, source_encoder) {
13119 if (encoders_cloneable(encoder, source_encoder))
13120 index_mask |= (1 << entry);
13121
13122 entry++;
13123 }
13124
13125 return index_mask;
13126 }
13127
13128 static bool has_edp_a(struct drm_i915_private *dev_priv)
13129 {
13130 if (!IS_MOBILE(dev_priv))
13131 return false;
13132
13133 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13134 return false;
13135
13136 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13137 return false;
13138
13139 return true;
13140 }
13141
13142 static bool intel_crt_present(struct drm_i915_private *dev_priv)
13143 {
13144 if (INTEL_GEN(dev_priv) >= 9)
13145 return false;
13146
13147 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
13148 return false;
13149
13150 if (IS_CHERRYVIEW(dev_priv))
13151 return false;
13152
13153 if (HAS_PCH_LPT_H(dev_priv) &&
13154 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
13155 return false;
13156
13157 /* DDI E can't be used if DDI A requires 4 lanes */
13158 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
13159 return false;
13160
13161 if (!dev_priv->vbt.int_crt_support)
13162 return false;
13163
13164 return true;
13165 }
13166
13167 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
13168 {
13169 int pps_num;
13170 int pps_idx;
13171
13172 if (HAS_DDI(dev_priv))
13173 return;
13174 /*
13175 * This w/a is needed at least on CPT/PPT, but to be sure apply it
13176 * everywhere where registers can be write protected.
13177 */
13178 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13179 pps_num = 2;
13180 else
13181 pps_num = 1;
13182
13183 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
13184 u32 val = I915_READ(PP_CONTROL(pps_idx));
13185
13186 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
13187 I915_WRITE(PP_CONTROL(pps_idx), val);
13188 }
13189 }
13190
13191 static void intel_pps_init(struct drm_i915_private *dev_priv)
13192 {
13193 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
13194 dev_priv->pps_mmio_base = PCH_PPS_BASE;
13195 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13196 dev_priv->pps_mmio_base = VLV_PPS_BASE;
13197 else
13198 dev_priv->pps_mmio_base = PPS_BASE;
13199
13200 intel_pps_unlock_regs_wa(dev_priv);
13201 }
13202
13203 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
13204 {
13205 struct intel_encoder *encoder;
13206 bool dpd_is_edp = false;
13207
13208 intel_pps_init(dev_priv);
13209
13210 /*
13211 * intel_edp_init_connector() depends on this completing first, to
13212 * prevent the registeration of both eDP and LVDS and the incorrect
13213 * sharing of the PPS.
13214 */
13215 intel_lvds_init(dev_priv);
13216
13217 if (intel_crt_present(dev_priv))
13218 intel_crt_init(dev_priv);
13219
13220 if (IS_GEN9_LP(dev_priv)) {
13221 /*
13222 * FIXME: Broxton doesn't support port detection via the
13223 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13224 * detect the ports.
13225 */
13226 intel_ddi_init(dev_priv, PORT_A);
13227 intel_ddi_init(dev_priv, PORT_B);
13228 intel_ddi_init(dev_priv, PORT_C);
13229
13230 intel_dsi_init(dev_priv);
13231 } else if (HAS_DDI(dev_priv)) {
13232 int found;
13233
13234 /*
13235 * Haswell uses DDI functions to detect digital outputs.
13236 * On SKL pre-D0 the strap isn't connected, so we assume
13237 * it's there.
13238 */
13239 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13240 /* WaIgnoreDDIAStrap: skl */
13241 if (found || IS_GEN9_BC(dev_priv))
13242 intel_ddi_init(dev_priv, PORT_A);
13243
13244 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13245 * register */
13246 found = I915_READ(SFUSE_STRAP);
13247
13248 if (found & SFUSE_STRAP_DDIB_DETECTED)
13249 intel_ddi_init(dev_priv, PORT_B);
13250 if (found & SFUSE_STRAP_DDIC_DETECTED)
13251 intel_ddi_init(dev_priv, PORT_C);
13252 if (found & SFUSE_STRAP_DDID_DETECTED)
13253 intel_ddi_init(dev_priv, PORT_D);
13254 /*
13255 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13256 */
13257 if (IS_GEN9_BC(dev_priv) &&
13258 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13259 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13260 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13261 intel_ddi_init(dev_priv, PORT_E);
13262
13263 } else if (HAS_PCH_SPLIT(dev_priv)) {
13264 int found;
13265 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
13266
13267 if (has_edp_a(dev_priv))
13268 intel_dp_init(dev_priv, DP_A, PORT_A);
13269
13270 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13271 /* PCH SDVOB multiplex with HDMIB */
13272 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
13273 if (!found)
13274 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
13275 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13276 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
13277 }
13278
13279 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13280 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
13281
13282 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13283 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
13284
13285 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13286 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
13287
13288 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13289 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
13290 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
13291 bool has_edp, has_port;
13292
13293 /*
13294 * The DP_DETECTED bit is the latched state of the DDC
13295 * SDA pin at boot. However since eDP doesn't require DDC
13296 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13297 * eDP ports may have been muxed to an alternate function.
13298 * Thus we can't rely on the DP_DETECTED bit alone to detect
13299 * eDP ports. Consult the VBT as well as DP_DETECTED to
13300 * detect eDP ports.
13301 *
13302 * Sadly the straps seem to be missing sometimes even for HDMI
13303 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
13304 * and VBT for the presence of the port. Additionally we can't
13305 * trust the port type the VBT declares as we've seen at least
13306 * HDMI ports that the VBT claim are DP or eDP.
13307 */
13308 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
13309 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
13310 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
13311 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
13312 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
13313 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
13314
13315 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
13316 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
13317 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
13318 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
13319 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
13320 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
13321
13322 if (IS_CHERRYVIEW(dev_priv)) {
13323 /*
13324 * eDP not supported on port D,
13325 * so no need to worry about it
13326 */
13327 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
13328 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
13329 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
13330 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
13331 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
13332 }
13333
13334 intel_dsi_init(dev_priv);
13335 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
13336 bool found = false;
13337
13338 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13339 DRM_DEBUG_KMS("probing SDVOB\n");
13340 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
13341 if (!found && IS_G4X(dev_priv)) {
13342 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13343 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
13344 }
13345
13346 if (!found && IS_G4X(dev_priv))
13347 intel_dp_init(dev_priv, DP_B, PORT_B);
13348 }
13349
13350 /* Before G4X SDVOC doesn't have its own detect register */
13351
13352 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13353 DRM_DEBUG_KMS("probing SDVOC\n");
13354 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
13355 }
13356
13357 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13358
13359 if (IS_G4X(dev_priv)) {
13360 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13361 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
13362 }
13363 if (IS_G4X(dev_priv))
13364 intel_dp_init(dev_priv, DP_C, PORT_C);
13365 }
13366
13367 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
13368 intel_dp_init(dev_priv, DP_D, PORT_D);
13369 } else if (IS_GEN2(dev_priv))
13370 intel_dvo_init(dev_priv);
13371
13372 if (SUPPORTS_TV(dev_priv))
13373 intel_tv_init(dev_priv);
13374
13375 intel_psr_init(dev_priv);
13376
13377 for_each_intel_encoder(&dev_priv->drm, encoder) {
13378 encoder->base.possible_crtcs = encoder->crtc_mask;
13379 encoder->base.possible_clones =
13380 intel_encoder_clones(encoder);
13381 }
13382
13383 intel_init_pch_refclk(dev_priv);
13384
13385 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
13386 }
13387
13388 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13389 {
13390 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13391
13392 drm_framebuffer_cleanup(fb);
13393
13394 i915_gem_object_lock(intel_fb->obj);
13395 WARN_ON(!intel_fb->obj->framebuffer_references--);
13396 i915_gem_object_unlock(intel_fb->obj);
13397
13398 i915_gem_object_put(intel_fb->obj);
13399
13400 kfree(intel_fb);
13401 }
13402
13403 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13404 struct drm_file *file,
13405 unsigned int *handle)
13406 {
13407 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13408 struct drm_i915_gem_object *obj = intel_fb->obj;
13409
13410 if (obj->userptr.mm) {
13411 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
13412 return -EINVAL;
13413 }
13414
13415 return drm_gem_handle_create(file, &obj->base, handle);
13416 }
13417
13418 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
13419 struct drm_file *file,
13420 unsigned flags, unsigned color,
13421 struct drm_clip_rect *clips,
13422 unsigned num_clips)
13423 {
13424 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13425
13426 i915_gem_object_flush_if_display(obj);
13427 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
13428
13429 return 0;
13430 }
13431
13432 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13433 .destroy = intel_user_framebuffer_destroy,
13434 .create_handle = intel_user_framebuffer_create_handle,
13435 .dirty = intel_user_framebuffer_dirty,
13436 };
13437
13438 static
13439 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
13440 uint64_t fb_modifier, uint32_t pixel_format)
13441 {
13442 u32 gen = INTEL_GEN(dev_priv);
13443
13444 if (gen >= 9) {
13445 int cpp = drm_format_plane_cpp(pixel_format, 0);
13446
13447 /* "The stride in bytes must not exceed the of the size of 8K
13448 * pixels and 32K bytes."
13449 */
13450 return min(8192 * cpp, 32768);
13451 } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
13452 return 32*1024;
13453 } else if (gen >= 4) {
13454 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13455 return 16*1024;
13456 else
13457 return 32*1024;
13458 } else if (gen >= 3) {
13459 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13460 return 8*1024;
13461 else
13462 return 16*1024;
13463 } else {
13464 /* XXX DSPC is limited to 4k tiled */
13465 return 8*1024;
13466 }
13467 }
13468
13469 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
13470 struct drm_i915_gem_object *obj,
13471 struct drm_mode_fb_cmd2 *mode_cmd)
13472 {
13473 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
13474 struct drm_format_name_buf format_name;
13475 u32 pitch_limit, stride_alignment;
13476 unsigned int tiling, stride;
13477 int ret = -EINVAL;
13478
13479 i915_gem_object_lock(obj);
13480 obj->framebuffer_references++;
13481 tiling = i915_gem_object_get_tiling(obj);
13482 stride = i915_gem_object_get_stride(obj);
13483 i915_gem_object_unlock(obj);
13484
13485 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13486 /*
13487 * If there's a fence, enforce that
13488 * the fb modifier and tiling mode match.
13489 */
13490 if (tiling != I915_TILING_NONE &&
13491 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13492 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
13493 goto err;
13494 }
13495 } else {
13496 if (tiling == I915_TILING_X) {
13497 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13498 } else if (tiling == I915_TILING_Y) {
13499 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
13500 goto err;
13501 }
13502 }
13503
13504 /* Passed in modifier sanity checking. */
13505 switch (mode_cmd->modifier[0]) {
13506 case I915_FORMAT_MOD_Y_TILED:
13507 case I915_FORMAT_MOD_Yf_TILED:
13508 if (INTEL_GEN(dev_priv) < 9) {
13509 DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
13510 mode_cmd->modifier[0]);
13511 goto err;
13512 }
13513 case DRM_FORMAT_MOD_LINEAR:
13514 case I915_FORMAT_MOD_X_TILED:
13515 break;
13516 default:
13517 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
13518 mode_cmd->modifier[0]);
13519 goto err;
13520 }
13521
13522 /*
13523 * gen2/3 display engine uses the fence if present,
13524 * so the tiling mode must match the fb modifier exactly.
13525 */
13526 if (INTEL_INFO(dev_priv)->gen < 4 &&
13527 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13528 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
13529 goto err;
13530 }
13531
13532 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
13533 mode_cmd->pixel_format);
13534 if (mode_cmd->pitches[0] > pitch_limit) {
13535 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
13536 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
13537 "tiled" : "linear",
13538 mode_cmd->pitches[0], pitch_limit);
13539 goto err;
13540 }
13541
13542 /*
13543 * If there's a fence, enforce that
13544 * the fb pitch and fence stride match.
13545 */
13546 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
13547 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
13548 mode_cmd->pitches[0], stride);
13549 goto err;
13550 }
13551
13552 /* Reject formats not supported by any plane early. */
13553 switch (mode_cmd->pixel_format) {
13554 case DRM_FORMAT_C8:
13555 case DRM_FORMAT_RGB565:
13556 case DRM_FORMAT_XRGB8888:
13557 case DRM_FORMAT_ARGB8888:
13558 break;
13559 case DRM_FORMAT_XRGB1555:
13560 if (INTEL_GEN(dev_priv) > 3) {
13561 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13562 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13563 goto err;
13564 }
13565 break;
13566 case DRM_FORMAT_ABGR8888:
13567 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
13568 INTEL_GEN(dev_priv) < 9) {
13569 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13570 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13571 goto err;
13572 }
13573 break;
13574 case DRM_FORMAT_XBGR8888:
13575 case DRM_FORMAT_XRGB2101010:
13576 case DRM_FORMAT_XBGR2101010:
13577 if (INTEL_GEN(dev_priv) < 4) {
13578 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13579 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13580 goto err;
13581 }
13582 break;
13583 case DRM_FORMAT_ABGR2101010:
13584 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
13585 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13586 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13587 goto err;
13588 }
13589 break;
13590 case DRM_FORMAT_YUYV:
13591 case DRM_FORMAT_UYVY:
13592 case DRM_FORMAT_YVYU:
13593 case DRM_FORMAT_VYUY:
13594 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
13595 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13596 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13597 goto err;
13598 }
13599 break;
13600 default:
13601 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13602 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13603 goto err;
13604 }
13605
13606 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13607 if (mode_cmd->offsets[0] != 0)
13608 goto err;
13609
13610 drm_helper_mode_fill_fb_struct(&dev_priv->drm,
13611 &intel_fb->base, mode_cmd);
13612
13613 stride_alignment = intel_fb_stride_alignment(&intel_fb->base, 0);
13614 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13615 DRM_DEBUG_KMS("pitch (%d) must be at least %u byte aligned\n",
13616 mode_cmd->pitches[0], stride_alignment);
13617 goto err;
13618 }
13619
13620 intel_fb->obj = obj;
13621
13622 ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
13623 if (ret)
13624 goto err;
13625
13626 ret = drm_framebuffer_init(obj->base.dev,
13627 &intel_fb->base,
13628 &intel_fb_funcs);
13629 if (ret) {
13630 DRM_ERROR("framebuffer init failed %d\n", ret);
13631 goto err;
13632 }
13633
13634 return 0;
13635
13636 err:
13637 i915_gem_object_lock(obj);
13638 obj->framebuffer_references--;
13639 i915_gem_object_unlock(obj);
13640 return ret;
13641 }
13642
13643 static struct drm_framebuffer *
13644 intel_user_framebuffer_create(struct drm_device *dev,
13645 struct drm_file *filp,
13646 const struct drm_mode_fb_cmd2 *user_mode_cmd)
13647 {
13648 struct drm_framebuffer *fb;
13649 struct drm_i915_gem_object *obj;
13650 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
13651
13652 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
13653 if (!obj)
13654 return ERR_PTR(-ENOENT);
13655
13656 fb = intel_framebuffer_create(obj, &mode_cmd);
13657 if (IS_ERR(fb))
13658 i915_gem_object_put(obj);
13659
13660 return fb;
13661 }
13662
13663 static void intel_atomic_state_free(struct drm_atomic_state *state)
13664 {
13665 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13666
13667 drm_atomic_state_default_release(state);
13668
13669 i915_sw_fence_fini(&intel_state->commit_ready);
13670
13671 kfree(state);
13672 }
13673
13674 static const struct drm_mode_config_funcs intel_mode_funcs = {
13675 .fb_create = intel_user_framebuffer_create,
13676 .output_poll_changed = intel_fbdev_output_poll_changed,
13677 .atomic_check = intel_atomic_check,
13678 .atomic_commit = intel_atomic_commit,
13679 .atomic_state_alloc = intel_atomic_state_alloc,
13680 .atomic_state_clear = intel_atomic_state_clear,
13681 .atomic_state_free = intel_atomic_state_free,
13682 };
13683
13684 /**
13685 * intel_init_display_hooks - initialize the display modesetting hooks
13686 * @dev_priv: device private
13687 */
13688 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
13689 {
13690 intel_init_cdclk_hooks(dev_priv);
13691
13692 if (INTEL_INFO(dev_priv)->gen >= 9) {
13693 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13694 dev_priv->display.get_initial_plane_config =
13695 skylake_get_initial_plane_config;
13696 dev_priv->display.crtc_compute_clock =
13697 haswell_crtc_compute_clock;
13698 dev_priv->display.crtc_enable = haswell_crtc_enable;
13699 dev_priv->display.crtc_disable = haswell_crtc_disable;
13700 } else if (HAS_DDI(dev_priv)) {
13701 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13702 dev_priv->display.get_initial_plane_config =
13703 ironlake_get_initial_plane_config;
13704 dev_priv->display.crtc_compute_clock =
13705 haswell_crtc_compute_clock;
13706 dev_priv->display.crtc_enable = haswell_crtc_enable;
13707 dev_priv->display.crtc_disable = haswell_crtc_disable;
13708 } else if (HAS_PCH_SPLIT(dev_priv)) {
13709 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
13710 dev_priv->display.get_initial_plane_config =
13711 ironlake_get_initial_plane_config;
13712 dev_priv->display.crtc_compute_clock =
13713 ironlake_crtc_compute_clock;
13714 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13715 dev_priv->display.crtc_disable = ironlake_crtc_disable;
13716 } else if (IS_CHERRYVIEW(dev_priv)) {
13717 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13718 dev_priv->display.get_initial_plane_config =
13719 i9xx_get_initial_plane_config;
13720 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
13721 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13722 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13723 } else if (IS_VALLEYVIEW(dev_priv)) {
13724 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13725 dev_priv->display.get_initial_plane_config =
13726 i9xx_get_initial_plane_config;
13727 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
13728 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13729 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13730 } else if (IS_G4X(dev_priv)) {
13731 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13732 dev_priv->display.get_initial_plane_config =
13733 i9xx_get_initial_plane_config;
13734 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
13735 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13736 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13737 } else if (IS_PINEVIEW(dev_priv)) {
13738 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13739 dev_priv->display.get_initial_plane_config =
13740 i9xx_get_initial_plane_config;
13741 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
13742 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13743 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13744 } else if (!IS_GEN2(dev_priv)) {
13745 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13746 dev_priv->display.get_initial_plane_config =
13747 i9xx_get_initial_plane_config;
13748 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13749 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13750 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13751 } else {
13752 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13753 dev_priv->display.get_initial_plane_config =
13754 i9xx_get_initial_plane_config;
13755 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
13756 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13757 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13758 }
13759
13760 if (IS_GEN5(dev_priv)) {
13761 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
13762 } else if (IS_GEN6(dev_priv)) {
13763 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
13764 } else if (IS_IVYBRIDGE(dev_priv)) {
13765 /* FIXME: detect B0+ stepping and use auto training */
13766 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
13767 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
13768 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
13769 }
13770
13771 if (dev_priv->info.gen >= 9)
13772 dev_priv->display.update_crtcs = skl_update_crtcs;
13773 else
13774 dev_priv->display.update_crtcs = intel_update_crtcs;
13775 }
13776
13777 /*
13778 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13779 */
13780 static void quirk_ssc_force_disable(struct drm_device *dev)
13781 {
13782 struct drm_i915_private *dev_priv = to_i915(dev);
13783 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13784 DRM_INFO("applying lvds SSC disable quirk\n");
13785 }
13786
13787 /*
13788 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13789 * brightness value
13790 */
13791 static void quirk_invert_brightness(struct drm_device *dev)
13792 {
13793 struct drm_i915_private *dev_priv = to_i915(dev);
13794 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13795 DRM_INFO("applying inverted panel brightness quirk\n");
13796 }
13797
13798 /* Some VBT's incorrectly indicate no backlight is present */
13799 static void quirk_backlight_present(struct drm_device *dev)
13800 {
13801 struct drm_i915_private *dev_priv = to_i915(dev);
13802 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13803 DRM_INFO("applying backlight present quirk\n");
13804 }
13805
13806 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
13807 * which is 300 ms greater than eDP spec T12 min.
13808 */
13809 static void quirk_increase_t12_delay(struct drm_device *dev)
13810 {
13811 struct drm_i915_private *dev_priv = to_i915(dev);
13812
13813 dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY;
13814 DRM_INFO("Applying T12 delay quirk\n");
13815 }
13816
13817 struct intel_quirk {
13818 int device;
13819 int subsystem_vendor;
13820 int subsystem_device;
13821 void (*hook)(struct drm_device *dev);
13822 };
13823
13824 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13825 struct intel_dmi_quirk {
13826 void (*hook)(struct drm_device *dev);
13827 const struct dmi_system_id (*dmi_id_list)[];
13828 };
13829
13830 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13831 {
13832 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13833 return 1;
13834 }
13835
13836 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13837 {
13838 .dmi_id_list = &(const struct dmi_system_id[]) {
13839 {
13840 .callback = intel_dmi_reverse_brightness,
13841 .ident = "NCR Corporation",
13842 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13843 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13844 },
13845 },
13846 { } /* terminating entry */
13847 },
13848 .hook = quirk_invert_brightness,
13849 },
13850 };
13851
13852 static struct intel_quirk intel_quirks[] = {
13853 /* Lenovo U160 cannot use SSC on LVDS */
13854 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13855
13856 /* Sony Vaio Y cannot use SSC on LVDS */
13857 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13858
13859 /* Acer Aspire 5734Z must invert backlight brightness */
13860 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13861
13862 /* Acer/eMachines G725 */
13863 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13864
13865 /* Acer/eMachines e725 */
13866 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13867
13868 /* Acer/Packard Bell NCL20 */
13869 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13870
13871 /* Acer Aspire 4736Z */
13872 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13873
13874 /* Acer Aspire 5336 */
13875 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13876
13877 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13878 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13879
13880 /* Acer C720 Chromebook (Core i3 4005U) */
13881 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13882
13883 /* Apple Macbook 2,1 (Core 2 T7400) */
13884 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13885
13886 /* Apple Macbook 4,1 */
13887 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
13888
13889 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13890 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13891
13892 /* HP Chromebook 14 (Celeron 2955U) */
13893 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13894
13895 /* Dell Chromebook 11 */
13896 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13897
13898 /* Dell Chromebook 11 (2015 version) */
13899 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
13900
13901 /* Toshiba Satellite P50-C-18C */
13902 { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
13903 };
13904
13905 static void intel_init_quirks(struct drm_device *dev)
13906 {
13907 struct pci_dev *d = dev->pdev;
13908 int i;
13909
13910 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13911 struct intel_quirk *q = &intel_quirks[i];
13912
13913 if (d->device == q->device &&
13914 (d->subsystem_vendor == q->subsystem_vendor ||
13915 q->subsystem_vendor == PCI_ANY_ID) &&
13916 (d->subsystem_device == q->subsystem_device ||
13917 q->subsystem_device == PCI_ANY_ID))
13918 q->hook(dev);
13919 }
13920 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13921 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13922 intel_dmi_quirks[i].hook(dev);
13923 }
13924 }
13925
13926 /* Disable the VGA plane that we never use */
13927 static void i915_disable_vga(struct drm_i915_private *dev_priv)
13928 {
13929 struct pci_dev *pdev = dev_priv->drm.pdev;
13930 u8 sr1;
13931 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
13932
13933 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13934 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
13935 outb(SR01, VGA_SR_INDEX);
13936 sr1 = inb(VGA_SR_DATA);
13937 outb(sr1 | 1<<5, VGA_SR_DATA);
13938 vga_put(pdev, VGA_RSRC_LEGACY_IO);
13939 udelay(300);
13940
13941 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13942 POSTING_READ(vga_reg);
13943 }
13944
13945 void intel_modeset_init_hw(struct drm_device *dev)
13946 {
13947 struct drm_i915_private *dev_priv = to_i915(dev);
13948
13949 intel_update_cdclk(dev_priv);
13950 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
13951
13952 intel_init_clock_gating(dev_priv);
13953 }
13954
13955 /*
13956 * Calculate what we think the watermarks should be for the state we've read
13957 * out of the hardware and then immediately program those watermarks so that
13958 * we ensure the hardware settings match our internal state.
13959 *
13960 * We can calculate what we think WM's should be by creating a duplicate of the
13961 * current state (which was constructed during hardware readout) and running it
13962 * through the atomic check code to calculate new watermark values in the
13963 * state object.
13964 */
13965 static void sanitize_watermarks(struct drm_device *dev)
13966 {
13967 struct drm_i915_private *dev_priv = to_i915(dev);
13968 struct drm_atomic_state *state;
13969 struct intel_atomic_state *intel_state;
13970 struct drm_crtc *crtc;
13971 struct drm_crtc_state *cstate;
13972 struct drm_modeset_acquire_ctx ctx;
13973 int ret;
13974 int i;
13975
13976 /* Only supported on platforms that use atomic watermark design */
13977 if (!dev_priv->display.optimize_watermarks)
13978 return;
13979
13980 /*
13981 * We need to hold connection_mutex before calling duplicate_state so
13982 * that the connector loop is protected.
13983 */
13984 drm_modeset_acquire_init(&ctx, 0);
13985 retry:
13986 ret = drm_modeset_lock_all_ctx(dev, &ctx);
13987 if (ret == -EDEADLK) {
13988 drm_modeset_backoff(&ctx);
13989 goto retry;
13990 } else if (WARN_ON(ret)) {
13991 goto fail;
13992 }
13993
13994 state = drm_atomic_helper_duplicate_state(dev, &ctx);
13995 if (WARN_ON(IS_ERR(state)))
13996 goto fail;
13997
13998 intel_state = to_intel_atomic_state(state);
13999
14000 /*
14001 * Hardware readout is the only time we don't want to calculate
14002 * intermediate watermarks (since we don't trust the current
14003 * watermarks).
14004 */
14005 if (!HAS_GMCH_DISPLAY(dev_priv))
14006 intel_state->skip_intermediate_wm = true;
14007
14008 ret = intel_atomic_check(dev, state);
14009 if (ret) {
14010 /*
14011 * If we fail here, it means that the hardware appears to be
14012 * programmed in a way that shouldn't be possible, given our
14013 * understanding of watermark requirements. This might mean a
14014 * mistake in the hardware readout code or a mistake in the
14015 * watermark calculations for a given platform. Raise a WARN
14016 * so that this is noticeable.
14017 *
14018 * If this actually happens, we'll have to just leave the
14019 * BIOS-programmed watermarks untouched and hope for the best.
14020 */
14021 WARN(true, "Could not determine valid watermarks for inherited state\n");
14022 goto put_state;
14023 }
14024
14025 /* Write calculated watermark values back */
14026 for_each_new_crtc_in_state(state, crtc, cstate, i) {
14027 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14028
14029 cs->wm.need_postvbl_update = true;
14030 dev_priv->display.optimize_watermarks(intel_state, cs);
14031 }
14032
14033 put_state:
14034 drm_atomic_state_put(state);
14035 fail:
14036 drm_modeset_drop_locks(&ctx);
14037 drm_modeset_acquire_fini(&ctx);
14038 }
14039
14040 int intel_modeset_init(struct drm_device *dev)
14041 {
14042 struct drm_i915_private *dev_priv = to_i915(dev);
14043 struct i915_ggtt *ggtt = &dev_priv->ggtt;
14044 enum pipe pipe;
14045 struct intel_crtc *crtc;
14046
14047 drm_mode_config_init(dev);
14048
14049 dev->mode_config.min_width = 0;
14050 dev->mode_config.min_height = 0;
14051
14052 dev->mode_config.preferred_depth = 24;
14053 dev->mode_config.prefer_shadow = 1;
14054
14055 dev->mode_config.allow_fb_modifiers = true;
14056
14057 dev->mode_config.funcs = &intel_mode_funcs;
14058
14059 init_llist_head(&dev_priv->atomic_helper.free_list);
14060 INIT_WORK(&dev_priv->atomic_helper.free_work,
14061 intel_atomic_helper_free_state_worker);
14062
14063 intel_init_quirks(dev);
14064
14065 intel_init_pm(dev_priv);
14066
14067 if (INTEL_INFO(dev_priv)->num_pipes == 0)
14068 return 0;
14069
14070 /*
14071 * There may be no VBT; and if the BIOS enabled SSC we can
14072 * just keep using it to avoid unnecessary flicker. Whereas if the
14073 * BIOS isn't using it, don't assume it will work even if the VBT
14074 * indicates as much.
14075 */
14076 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
14077 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14078 DREF_SSC1_ENABLE);
14079
14080 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14081 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14082 bios_lvds_use_ssc ? "en" : "dis",
14083 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14084 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14085 }
14086 }
14087
14088 if (IS_GEN2(dev_priv)) {
14089 dev->mode_config.max_width = 2048;
14090 dev->mode_config.max_height = 2048;
14091 } else if (IS_GEN3(dev_priv)) {
14092 dev->mode_config.max_width = 4096;
14093 dev->mode_config.max_height = 4096;
14094 } else {
14095 dev->mode_config.max_width = 8192;
14096 dev->mode_config.max_height = 8192;
14097 }
14098
14099 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14100 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
14101 dev->mode_config.cursor_height = 1023;
14102 } else if (IS_GEN2(dev_priv)) {
14103 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14104 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14105 } else {
14106 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14107 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14108 }
14109
14110 dev->mode_config.fb_base = ggtt->mappable_base;
14111
14112 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14113 INTEL_INFO(dev_priv)->num_pipes,
14114 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
14115
14116 for_each_pipe(dev_priv, pipe) {
14117 int ret;
14118
14119 ret = intel_crtc_init(dev_priv, pipe);
14120 if (ret) {
14121 drm_mode_config_cleanup(dev);
14122 return ret;
14123 }
14124 }
14125
14126 intel_shared_dpll_init(dev);
14127
14128 intel_update_czclk(dev_priv);
14129 intel_modeset_init_hw(dev);
14130
14131 if (dev_priv->max_cdclk_freq == 0)
14132 intel_update_max_cdclk(dev_priv);
14133
14134 /* Just disable it once at startup */
14135 i915_disable_vga(dev_priv);
14136 intel_setup_outputs(dev_priv);
14137
14138 drm_modeset_lock_all(dev);
14139 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
14140 drm_modeset_unlock_all(dev);
14141
14142 for_each_intel_crtc(dev, crtc) {
14143 struct intel_initial_plane_config plane_config = {};
14144
14145 if (!crtc->active)
14146 continue;
14147
14148 /*
14149 * Note that reserving the BIOS fb up front prevents us
14150 * from stuffing other stolen allocations like the ring
14151 * on top. This prevents some ugliness at boot time, and
14152 * can even allow for smooth boot transitions if the BIOS
14153 * fb is large enough for the active pipe configuration.
14154 */
14155 dev_priv->display.get_initial_plane_config(crtc,
14156 &plane_config);
14157
14158 /*
14159 * If the fb is shared between multiple heads, we'll
14160 * just get the first one.
14161 */
14162 intel_find_initial_plane_obj(crtc, &plane_config);
14163 }
14164
14165 /*
14166 * Make sure hardware watermarks really match the state we read out.
14167 * Note that we need to do this after reconstructing the BIOS fb's
14168 * since the watermark calculation done here will use pstate->fb.
14169 */
14170 if (!HAS_GMCH_DISPLAY(dev_priv))
14171 sanitize_watermarks(dev);
14172
14173 return 0;
14174 }
14175
14176 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14177 {
14178 /* 640x480@60Hz, ~25175 kHz */
14179 struct dpll clock = {
14180 .m1 = 18,
14181 .m2 = 7,
14182 .p1 = 13,
14183 .p2 = 4,
14184 .n = 2,
14185 };
14186 u32 dpll, fp;
14187 int i;
14188
14189 WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
14190
14191 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
14192 pipe_name(pipe), clock.vco, clock.dot);
14193
14194 fp = i9xx_dpll_compute_fp(&clock);
14195 dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
14196 DPLL_VGA_MODE_DIS |
14197 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
14198 PLL_P2_DIVIDE_BY_4 |
14199 PLL_REF_INPUT_DREFCLK |
14200 DPLL_VCO_ENABLE;
14201
14202 I915_WRITE(FP0(pipe), fp);
14203 I915_WRITE(FP1(pipe), fp);
14204
14205 I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
14206 I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
14207 I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
14208 I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
14209 I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
14210 I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
14211 I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
14212
14213 /*
14214 * Apparently we need to have VGA mode enabled prior to changing
14215 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
14216 * dividers, even though the register value does change.
14217 */
14218 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
14219 I915_WRITE(DPLL(pipe), dpll);
14220
14221 /* Wait for the clocks to stabilize. */
14222 POSTING_READ(DPLL(pipe));
14223 udelay(150);
14224
14225 /* The pixel multiplier can only be updated once the
14226 * DPLL is enabled and the clocks are stable.
14227 *
14228 * So write it again.
14229 */
14230 I915_WRITE(DPLL(pipe), dpll);
14231
14232 /* We do this three times for luck */
14233 for (i = 0; i < 3 ; i++) {
14234 I915_WRITE(DPLL(pipe), dpll);
14235 POSTING_READ(DPLL(pipe));
14236 udelay(150); /* wait for warmup */
14237 }
14238
14239 I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
14240 POSTING_READ(PIPECONF(pipe));
14241 }
14242
14243 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14244 {
14245 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
14246 pipe_name(pipe));
14247
14248 assert_plane_disabled(dev_priv, PLANE_A);
14249 assert_plane_disabled(dev_priv, PLANE_B);
14250
14251 I915_WRITE(PIPECONF(pipe), 0);
14252 POSTING_READ(PIPECONF(pipe));
14253
14254 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
14255 DRM_ERROR("pipe %c off wait timed out\n", pipe_name(pipe));
14256
14257 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
14258 POSTING_READ(DPLL(pipe));
14259 }
14260
14261 static bool
14262 intel_check_plane_mapping(struct intel_crtc *crtc)
14263 {
14264 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14265 u32 val;
14266
14267 if (INTEL_INFO(dev_priv)->num_pipes == 1)
14268 return true;
14269
14270 val = I915_READ(DSPCNTR(!crtc->plane));
14271
14272 if ((val & DISPLAY_PLANE_ENABLE) &&
14273 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14274 return false;
14275
14276 return true;
14277 }
14278
14279 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14280 {
14281 struct drm_device *dev = crtc->base.dev;
14282 struct intel_encoder *encoder;
14283
14284 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14285 return true;
14286
14287 return false;
14288 }
14289
14290 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
14291 {
14292 struct drm_device *dev = encoder->base.dev;
14293 struct intel_connector *connector;
14294
14295 for_each_connector_on_encoder(dev, &encoder->base, connector)
14296 return connector;
14297
14298 return NULL;
14299 }
14300
14301 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
14302 enum transcoder pch_transcoder)
14303 {
14304 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
14305 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
14306 }
14307
14308 static void intel_sanitize_crtc(struct intel_crtc *crtc,
14309 struct drm_modeset_acquire_ctx *ctx)
14310 {
14311 struct drm_device *dev = crtc->base.dev;
14312 struct drm_i915_private *dev_priv = to_i915(dev);
14313 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
14314
14315 /* Clear any frame start delays used for debugging left by the BIOS */
14316 if (!transcoder_is_dsi(cpu_transcoder)) {
14317 i915_reg_t reg = PIPECONF(cpu_transcoder);
14318
14319 I915_WRITE(reg,
14320 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14321 }
14322
14323 /* restore vblank interrupts to correct state */
14324 drm_crtc_vblank_reset(&crtc->base);
14325 if (crtc->active) {
14326 struct intel_plane *plane;
14327
14328 drm_crtc_vblank_on(&crtc->base);
14329
14330 /* Disable everything but the primary plane */
14331 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14332 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14333 continue;
14334
14335 trace_intel_disable_plane(&plane->base, crtc);
14336 plane->disable_plane(plane, crtc);
14337 }
14338 }
14339
14340 /* We need to sanitize the plane -> pipe mapping first because this will
14341 * disable the crtc (and hence change the state) if it is wrong. Note
14342 * that gen4+ has a fixed plane -> pipe mapping. */
14343 if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
14344 bool plane;
14345
14346 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
14347 crtc->base.base.id, crtc->base.name);
14348
14349 /* Pipe has the wrong plane attached and the plane is active.
14350 * Temporarily change the plane mapping and disable everything
14351 * ... */
14352 plane = crtc->plane;
14353 crtc->base.primary->state->visible = true;
14354 crtc->plane = !plane;
14355 intel_crtc_disable_noatomic(&crtc->base, ctx);
14356 crtc->plane = plane;
14357 }
14358
14359 /* Adjust the state of the output pipe according to whether we
14360 * have active connectors/encoders. */
14361 if (crtc->active && !intel_crtc_has_encoders(crtc))
14362 intel_crtc_disable_noatomic(&crtc->base, ctx);
14363
14364 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
14365 /*
14366 * We start out with underrun reporting disabled to avoid races.
14367 * For correct bookkeeping mark this on active crtcs.
14368 *
14369 * Also on gmch platforms we dont have any hardware bits to
14370 * disable the underrun reporting. Which means we need to start
14371 * out with underrun reporting disabled also on inactive pipes,
14372 * since otherwise we'll complain about the garbage we read when
14373 * e.g. coming up after runtime pm.
14374 *
14375 * No protection against concurrent access is required - at
14376 * worst a fifo underrun happens which also sets this to false.
14377 */
14378 crtc->cpu_fifo_underrun_disabled = true;
14379 /*
14380 * We track the PCH trancoder underrun reporting state
14381 * within the crtc. With crtc for pipe A housing the underrun
14382 * reporting state for PCH transcoder A, crtc for pipe B housing
14383 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
14384 * and marking underrun reporting as disabled for the non-existing
14385 * PCH transcoders B and C would prevent enabling the south
14386 * error interrupt (see cpt_can_enable_serr_int()).
14387 */
14388 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
14389 crtc->pch_fifo_underrun_disabled = true;
14390 }
14391 }
14392
14393 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14394 {
14395 struct intel_connector *connector;
14396
14397 /* We need to check both for a crtc link (meaning that the
14398 * encoder is active and trying to read from a pipe) and the
14399 * pipe itself being active. */
14400 bool has_active_crtc = encoder->base.crtc &&
14401 to_intel_crtc(encoder->base.crtc)->active;
14402
14403 connector = intel_encoder_find_connector(encoder);
14404 if (connector && !has_active_crtc) {
14405 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14406 encoder->base.base.id,
14407 encoder->base.name);
14408
14409 /* Connector is active, but has no active pipe. This is
14410 * fallout from our resume register restoring. Disable
14411 * the encoder manually again. */
14412 if (encoder->base.crtc) {
14413 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
14414
14415 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14416 encoder->base.base.id,
14417 encoder->base.name);
14418 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14419 if (encoder->post_disable)
14420 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14421 }
14422 encoder->base.crtc = NULL;
14423
14424 /* Inconsistent output/port/pipe state happens presumably due to
14425 * a bug in one of the get_hw_state functions. Or someplace else
14426 * in our code, like the register restore mess on resume. Clamp
14427 * things to off as a safer default. */
14428
14429 connector->base.dpms = DRM_MODE_DPMS_OFF;
14430 connector->base.encoder = NULL;
14431 }
14432 /* Enabled encoders without active connectors will be fixed in
14433 * the crtc fixup. */
14434 }
14435
14436 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
14437 {
14438 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14439
14440 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14441 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14442 i915_disable_vga(dev_priv);
14443 }
14444 }
14445
14446 void i915_redisable_vga(struct drm_i915_private *dev_priv)
14447 {
14448 /* This function can be called both from intel_modeset_setup_hw_state or
14449 * at a very early point in our resume sequence, where the power well
14450 * structures are not yet restored. Since this function is at a very
14451 * paranoid "someone might have enabled VGA while we were not looking"
14452 * level, just check if the power well is enabled instead of trying to
14453 * follow the "don't touch the power well if we don't need it" policy
14454 * the rest of the driver uses. */
14455 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
14456 return;
14457
14458 i915_redisable_vga_power_on(dev_priv);
14459
14460 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
14461 }
14462
14463 static bool primary_get_hw_state(struct intel_plane *plane)
14464 {
14465 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
14466
14467 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
14468 }
14469
14470 /* FIXME read out full plane state for all planes */
14471 static void readout_plane_state(struct intel_crtc *crtc)
14472 {
14473 struct intel_plane *primary = to_intel_plane(crtc->base.primary);
14474 bool visible;
14475
14476 visible = crtc->active && primary_get_hw_state(primary);
14477
14478 intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
14479 to_intel_plane_state(primary->base.state),
14480 visible);
14481 }
14482
14483 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14484 {
14485 struct drm_i915_private *dev_priv = to_i915(dev);
14486 enum pipe pipe;
14487 struct intel_crtc *crtc;
14488 struct intel_encoder *encoder;
14489 struct intel_connector *connector;
14490 struct drm_connector_list_iter conn_iter;
14491 int i;
14492
14493 dev_priv->active_crtcs = 0;
14494
14495 for_each_intel_crtc(dev, crtc) {
14496 struct intel_crtc_state *crtc_state =
14497 to_intel_crtc_state(crtc->base.state);
14498
14499 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
14500 memset(crtc_state, 0, sizeof(*crtc_state));
14501 crtc_state->base.crtc = &crtc->base;
14502
14503 crtc_state->base.active = crtc_state->base.enable =
14504 dev_priv->display.get_pipe_config(crtc, crtc_state);
14505
14506 crtc->base.enabled = crtc_state->base.enable;
14507 crtc->active = crtc_state->base.active;
14508
14509 if (crtc_state->base.active)
14510 dev_priv->active_crtcs |= 1 << crtc->pipe;
14511
14512 readout_plane_state(crtc);
14513
14514 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
14515 crtc->base.base.id, crtc->base.name,
14516 enableddisabled(crtc_state->base.active));
14517 }
14518
14519 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14520 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14521
14522 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
14523 &pll->state.hw_state);
14524 pll->state.crtc_mask = 0;
14525 for_each_intel_crtc(dev, crtc) {
14526 struct intel_crtc_state *crtc_state =
14527 to_intel_crtc_state(crtc->base.state);
14528
14529 if (crtc_state->base.active &&
14530 crtc_state->shared_dpll == pll)
14531 pll->state.crtc_mask |= 1 << crtc->pipe;
14532 }
14533 pll->active_mask = pll->state.crtc_mask;
14534
14535 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14536 pll->name, pll->state.crtc_mask, pll->on);
14537 }
14538
14539 for_each_intel_encoder(dev, encoder) {
14540 pipe = 0;
14541
14542 if (encoder->get_hw_state(encoder, &pipe)) {
14543 struct intel_crtc_state *crtc_state;
14544
14545 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
14546 crtc_state = to_intel_crtc_state(crtc->base.state);
14547
14548 encoder->base.crtc = &crtc->base;
14549 crtc_state->output_types |= 1 << encoder->type;
14550 encoder->get_config(encoder, crtc_state);
14551 } else {
14552 encoder->base.crtc = NULL;
14553 }
14554
14555 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14556 encoder->base.base.id, encoder->base.name,
14557 enableddisabled(encoder->base.crtc),
14558 pipe_name(pipe));
14559 }
14560
14561 drm_connector_list_iter_begin(dev, &conn_iter);
14562 for_each_intel_connector_iter(connector, &conn_iter) {
14563 if (connector->get_hw_state(connector)) {
14564 connector->base.dpms = DRM_MODE_DPMS_ON;
14565
14566 encoder = connector->encoder;
14567 connector->base.encoder = &encoder->base;
14568
14569 if (encoder->base.crtc &&
14570 encoder->base.crtc->state->active) {
14571 /*
14572 * This has to be done during hardware readout
14573 * because anything calling .crtc_disable may
14574 * rely on the connector_mask being accurate.
14575 */
14576 encoder->base.crtc->state->connector_mask |=
14577 1 << drm_connector_index(&connector->base);
14578 encoder->base.crtc->state->encoder_mask |=
14579 1 << drm_encoder_index(&encoder->base);
14580 }
14581
14582 } else {
14583 connector->base.dpms = DRM_MODE_DPMS_OFF;
14584 connector->base.encoder = NULL;
14585 }
14586 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14587 connector->base.base.id, connector->base.name,
14588 enableddisabled(connector->base.encoder));
14589 }
14590 drm_connector_list_iter_end(&conn_iter);
14591
14592 for_each_intel_crtc(dev, crtc) {
14593 struct intel_crtc_state *crtc_state =
14594 to_intel_crtc_state(crtc->base.state);
14595 int pixclk = 0;
14596
14597 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
14598 if (crtc_state->base.active) {
14599 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
14600 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
14601 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
14602
14603 /*
14604 * The initial mode needs to be set in order to keep
14605 * the atomic core happy. It wants a valid mode if the
14606 * crtc's enabled, so we do the above call.
14607 *
14608 * But we don't set all the derived state fully, hence
14609 * set a flag to indicate that a full recalculation is
14610 * needed on the next commit.
14611 */
14612 crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
14613
14614 intel_crtc_compute_pixel_rate(crtc_state);
14615
14616 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) ||
14617 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14618 pixclk = crtc_state->pixel_rate;
14619 else
14620 WARN_ON(dev_priv->display.modeset_calc_cdclk);
14621
14622 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
14623 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
14624 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
14625
14626 drm_calc_timestamping_constants(&crtc->base,
14627 &crtc_state->base.adjusted_mode);
14628 update_scanline_offset(crtc);
14629 }
14630
14631 dev_priv->min_pixclk[crtc->pipe] = pixclk;
14632
14633 intel_pipe_config_sanity_check(dev_priv, crtc_state);
14634 }
14635 }
14636
14637 static void
14638 get_encoder_power_domains(struct drm_i915_private *dev_priv)
14639 {
14640 struct intel_encoder *encoder;
14641
14642 for_each_intel_encoder(&dev_priv->drm, encoder) {
14643 u64 get_domains;
14644 enum intel_display_power_domain domain;
14645
14646 if (!encoder->get_power_domains)
14647 continue;
14648
14649 get_domains = encoder->get_power_domains(encoder);
14650 for_each_power_domain(domain, get_domains)
14651 intel_display_power_get(dev_priv, domain);
14652 }
14653 }
14654
14655 /* Scan out the current hw modeset state,
14656 * and sanitizes it to the current state
14657 */
14658 static void
14659 intel_modeset_setup_hw_state(struct drm_device *dev,
14660 struct drm_modeset_acquire_ctx *ctx)
14661 {
14662 struct drm_i915_private *dev_priv = to_i915(dev);
14663 enum pipe pipe;
14664 struct intel_crtc *crtc;
14665 struct intel_encoder *encoder;
14666 int i;
14667
14668 intel_modeset_readout_hw_state(dev);
14669
14670 /* HW state is read out, now we need to sanitize this mess. */
14671 get_encoder_power_domains(dev_priv);
14672
14673 for_each_intel_encoder(dev, encoder) {
14674 intel_sanitize_encoder(encoder);
14675 }
14676
14677 for_each_pipe(dev_priv, pipe) {
14678 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
14679
14680 intel_sanitize_crtc(crtc, ctx);
14681 intel_dump_pipe_config(crtc, crtc->config,
14682 "[setup_hw_state]");
14683 }
14684
14685 intel_modeset_update_connector_atomic_state(dev);
14686
14687 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14688 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14689
14690 if (!pll->on || pll->active_mask)
14691 continue;
14692
14693 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14694
14695 pll->funcs.disable(dev_priv, pll);
14696 pll->on = false;
14697 }
14698
14699 if (IS_G4X(dev_priv)) {
14700 g4x_wm_get_hw_state(dev);
14701 g4x_wm_sanitize(dev_priv);
14702 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14703 vlv_wm_get_hw_state(dev);
14704 vlv_wm_sanitize(dev_priv);
14705 } else if (IS_GEN9(dev_priv)) {
14706 skl_wm_get_hw_state(dev);
14707 } else if (HAS_PCH_SPLIT(dev_priv)) {
14708 ilk_wm_get_hw_state(dev);
14709 }
14710
14711 for_each_intel_crtc(dev, crtc) {
14712 u64 put_domains;
14713
14714 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
14715 if (WARN_ON(put_domains))
14716 modeset_put_power_domains(dev_priv, put_domains);
14717 }
14718 intel_display_set_init_power(dev_priv, false);
14719
14720 intel_power_domains_verify_state(dev_priv);
14721
14722 intel_fbc_init_pipe_state(dev_priv);
14723 }
14724
14725 void intel_display_resume(struct drm_device *dev)
14726 {
14727 struct drm_i915_private *dev_priv = to_i915(dev);
14728 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
14729 struct drm_modeset_acquire_ctx ctx;
14730 int ret;
14731
14732 dev_priv->modeset_restore_state = NULL;
14733 if (state)
14734 state->acquire_ctx = &ctx;
14735
14736 drm_modeset_acquire_init(&ctx, 0);
14737
14738 while (1) {
14739 ret = drm_modeset_lock_all_ctx(dev, &ctx);
14740 if (ret != -EDEADLK)
14741 break;
14742
14743 drm_modeset_backoff(&ctx);
14744 }
14745
14746 if (!ret)
14747 ret = __intel_display_resume(dev, state, &ctx);
14748
14749 drm_modeset_drop_locks(&ctx);
14750 drm_modeset_acquire_fini(&ctx);
14751
14752 if (ret)
14753 DRM_ERROR("Restoring old state failed with %i\n", ret);
14754 if (state)
14755 drm_atomic_state_put(state);
14756 }
14757
14758 void intel_modeset_gem_init(struct drm_device *dev)
14759 {
14760 struct drm_i915_private *dev_priv = to_i915(dev);
14761
14762 intel_init_gt_powersave(dev_priv);
14763
14764 intel_setup_overlay(dev_priv);
14765 }
14766
14767 int intel_connector_register(struct drm_connector *connector)
14768 {
14769 struct intel_connector *intel_connector = to_intel_connector(connector);
14770 int ret;
14771
14772 ret = intel_backlight_device_register(intel_connector);
14773 if (ret)
14774 goto err;
14775
14776 return 0;
14777
14778 err:
14779 return ret;
14780 }
14781
14782 void intel_connector_unregister(struct drm_connector *connector)
14783 {
14784 struct intel_connector *intel_connector = to_intel_connector(connector);
14785
14786 intel_backlight_device_unregister(intel_connector);
14787 intel_panel_destroy_backlight(connector);
14788 }
14789
14790 void intel_modeset_cleanup(struct drm_device *dev)
14791 {
14792 struct drm_i915_private *dev_priv = to_i915(dev);
14793
14794 flush_work(&dev_priv->atomic_helper.free_work);
14795 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
14796
14797 intel_disable_gt_powersave(dev_priv);
14798
14799 /*
14800 * Interrupts and polling as the first thing to avoid creating havoc.
14801 * Too much stuff here (turning of connectors, ...) would
14802 * experience fancy races otherwise.
14803 */
14804 intel_irq_uninstall(dev_priv);
14805
14806 /*
14807 * Due to the hpd irq storm handling the hotplug work can re-arm the
14808 * poll handlers. Hence disable polling after hpd handling is shut down.
14809 */
14810 drm_kms_helper_poll_fini(dev);
14811
14812 /* poll work can call into fbdev, hence clean that up afterwards */
14813 intel_fbdev_fini(dev_priv);
14814
14815 intel_unregister_dsm_handler();
14816
14817 intel_fbc_global_disable(dev_priv);
14818
14819 /* flush any delayed tasks or pending work */
14820 flush_scheduled_work();
14821
14822 drm_mode_config_cleanup(dev);
14823
14824 intel_cleanup_overlay(dev_priv);
14825
14826 intel_cleanup_gt_powersave(dev_priv);
14827
14828 intel_teardown_gmbus(dev_priv);
14829 }
14830
14831 void intel_connector_attach_encoder(struct intel_connector *connector,
14832 struct intel_encoder *encoder)
14833 {
14834 connector->encoder = encoder;
14835 drm_mode_connector_attach_encoder(&connector->base,
14836 &encoder->base);
14837 }
14838
14839 /*
14840 * set vga decode state - true == enable VGA decode
14841 */
14842 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
14843 {
14844 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
14845 u16 gmch_ctrl;
14846
14847 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
14848 DRM_ERROR("failed to read control word\n");
14849 return -EIO;
14850 }
14851
14852 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
14853 return 0;
14854
14855 if (state)
14856 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
14857 else
14858 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
14859
14860 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
14861 DRM_ERROR("failed to write control word\n");
14862 return -EIO;
14863 }
14864
14865 return 0;
14866 }
14867
14868 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
14869
14870 struct intel_display_error_state {
14871
14872 u32 power_well_driver;
14873
14874 int num_transcoders;
14875
14876 struct intel_cursor_error_state {
14877 u32 control;
14878 u32 position;
14879 u32 base;
14880 u32 size;
14881 } cursor[I915_MAX_PIPES];
14882
14883 struct intel_pipe_error_state {
14884 bool power_domain_on;
14885 u32 source;
14886 u32 stat;
14887 } pipe[I915_MAX_PIPES];
14888
14889 struct intel_plane_error_state {
14890 u32 control;
14891 u32 stride;
14892 u32 size;
14893 u32 pos;
14894 u32 addr;
14895 u32 surface;
14896 u32 tile_offset;
14897 } plane[I915_MAX_PIPES];
14898
14899 struct intel_transcoder_error_state {
14900 bool power_domain_on;
14901 enum transcoder cpu_transcoder;
14902
14903 u32 conf;
14904
14905 u32 htotal;
14906 u32 hblank;
14907 u32 hsync;
14908 u32 vtotal;
14909 u32 vblank;
14910 u32 vsync;
14911 } transcoder[4];
14912 };
14913
14914 struct intel_display_error_state *
14915 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
14916 {
14917 struct intel_display_error_state *error;
14918 int transcoders[] = {
14919 TRANSCODER_A,
14920 TRANSCODER_B,
14921 TRANSCODER_C,
14922 TRANSCODER_EDP,
14923 };
14924 int i;
14925
14926 if (INTEL_INFO(dev_priv)->num_pipes == 0)
14927 return NULL;
14928
14929 error = kzalloc(sizeof(*error), GFP_ATOMIC);
14930 if (error == NULL)
14931 return NULL;
14932
14933 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
14934 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14935
14936 for_each_pipe(dev_priv, i) {
14937 error->pipe[i].power_domain_on =
14938 __intel_display_power_is_enabled(dev_priv,
14939 POWER_DOMAIN_PIPE(i));
14940 if (!error->pipe[i].power_domain_on)
14941 continue;
14942
14943 error->cursor[i].control = I915_READ(CURCNTR(i));
14944 error->cursor[i].position = I915_READ(CURPOS(i));
14945 error->cursor[i].base = I915_READ(CURBASE(i));
14946
14947 error->plane[i].control = I915_READ(DSPCNTR(i));
14948 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
14949 if (INTEL_GEN(dev_priv) <= 3) {
14950 error->plane[i].size = I915_READ(DSPSIZE(i));
14951 error->plane[i].pos = I915_READ(DSPPOS(i));
14952 }
14953 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
14954 error->plane[i].addr = I915_READ(DSPADDR(i));
14955 if (INTEL_GEN(dev_priv) >= 4) {
14956 error->plane[i].surface = I915_READ(DSPSURF(i));
14957 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14958 }
14959
14960 error->pipe[i].source = I915_READ(PIPESRC(i));
14961
14962 if (HAS_GMCH_DISPLAY(dev_priv))
14963 error->pipe[i].stat = I915_READ(PIPESTAT(i));
14964 }
14965
14966 /* Note: this does not include DSI transcoders. */
14967 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
14968 if (HAS_DDI(dev_priv))
14969 error->num_transcoders++; /* Account for eDP. */
14970
14971 for (i = 0; i < error->num_transcoders; i++) {
14972 enum transcoder cpu_transcoder = transcoders[i];
14973
14974 error->transcoder[i].power_domain_on =
14975 __intel_display_power_is_enabled(dev_priv,
14976 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
14977 if (!error->transcoder[i].power_domain_on)
14978 continue;
14979
14980 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14981
14982 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14983 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14984 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14985 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14986 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14987 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14988 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14989 }
14990
14991 return error;
14992 }
14993
14994 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14995
14996 void
14997 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
14998 struct intel_display_error_state *error)
14999 {
15000 struct drm_i915_private *dev_priv = m->i915;
15001 int i;
15002
15003 if (!error)
15004 return;
15005
15006 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15007 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15008 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15009 error->power_well_driver);
15010 for_each_pipe(dev_priv, i) {
15011 err_printf(m, "Pipe [%d]:\n", i);
15012 err_printf(m, " Power: %s\n",
15013 onoff(error->pipe[i].power_domain_on));
15014 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15015 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15016
15017 err_printf(m, "Plane [%d]:\n", i);
15018 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15019 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15020 if (INTEL_GEN(dev_priv) <= 3) {
15021 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15022 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15023 }
15024 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15025 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15026 if (INTEL_GEN(dev_priv) >= 4) {
15027 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15028 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15029 }
15030
15031 err_printf(m, "Cursor [%d]:\n", i);
15032 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15033 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15034 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15035 }
15036
15037 for (i = 0; i < error->num_transcoders; i++) {
15038 err_printf(m, "CPU transcoder: %s\n",
15039 transcoder_name(error->transcoder[i].cpu_transcoder));
15040 err_printf(m, " Power: %s\n",
15041 onoff(error->transcoder[i].power_domain_on));
15042 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15043 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15044 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15045 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15046 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15047 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15048 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15049 }
15050 }
15051
15052 #endif
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