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drm/i915: dev_priv cleanup in intel_display.c
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "intel_dsi.h"
41 #include "i915_trace.h"
42 #include <drm/drm_atomic.h>
43 #include <drm/drm_atomic_helper.h>
44 #include <drm/drm_dp_helper.h>
45 #include <drm/drm_crtc_helper.h>
46 #include <drm/drm_plane_helper.h>
47 #include <drm/drm_rect.h>
48 #include <linux/dma_remapping.h>
49 #include <linux/reservation.h>
50
51 static bool is_mmio_work(struct intel_flip_work *work)
52 {
53 return work->mmio_work.func;
54 }
55
56 /* Primary plane formats for gen <= 3 */
57 static const uint32_t i8xx_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB1555,
61 DRM_FORMAT_XRGB8888,
62 };
63
64 /* Primary plane formats for gen >= 4 */
65 static const uint32_t i965_primary_formats[] = {
66 DRM_FORMAT_C8,
67 DRM_FORMAT_RGB565,
68 DRM_FORMAT_XRGB8888,
69 DRM_FORMAT_XBGR8888,
70 DRM_FORMAT_XRGB2101010,
71 DRM_FORMAT_XBGR2101010,
72 };
73
74 static const uint32_t skl_primary_formats[] = {
75 DRM_FORMAT_C8,
76 DRM_FORMAT_RGB565,
77 DRM_FORMAT_XRGB8888,
78 DRM_FORMAT_XBGR8888,
79 DRM_FORMAT_ARGB8888,
80 DRM_FORMAT_ABGR8888,
81 DRM_FORMAT_XRGB2101010,
82 DRM_FORMAT_XBGR2101010,
83 DRM_FORMAT_YUYV,
84 DRM_FORMAT_YVYU,
85 DRM_FORMAT_UYVY,
86 DRM_FORMAT_VYUY,
87 };
88
89 /* Cursor formats */
90 static const uint32_t intel_cursor_formats[] = {
91 DRM_FORMAT_ARGB8888,
92 };
93
94 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
95 struct intel_crtc_state *pipe_config);
96 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
97 struct intel_crtc_state *pipe_config);
98
99 static int intel_framebuffer_init(struct drm_device *dev,
100 struct intel_framebuffer *ifb,
101 struct drm_mode_fb_cmd2 *mode_cmd,
102 struct drm_i915_gem_object *obj);
103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
107 struct intel_link_m_n *m_n,
108 struct intel_link_m_n *m2_n2);
109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
112 static void vlv_prepare_pll(struct intel_crtc *crtc,
113 const struct intel_crtc_state *pipe_config);
114 static void chv_prepare_pll(struct intel_crtc *crtc,
115 const struct intel_crtc_state *pipe_config);
116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void skl_init_scalers(struct drm_i915_private *dev_priv,
119 struct intel_crtc *crtc,
120 struct intel_crtc_state *crtc_state);
121 static void skylake_pfit_enable(struct intel_crtc *crtc);
122 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
123 static void ironlake_pfit_enable(struct intel_crtc *crtc);
124 static void intel_modeset_setup_hw_state(struct drm_device *dev);
125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
126 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
127 static int bxt_calc_cdclk(int max_pixclk);
128
129 struct intel_limit {
130 struct {
131 int min, max;
132 } dot, vco, n, m, m1, m2, p, p1;
133
134 struct {
135 int dot_limit;
136 int p2_slow, p2_fast;
137 } p2;
138 };
139
140 /* returns HPLL frequency in kHz */
141 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
142 {
143 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
144
145 /* Obtain SKU information */
146 mutex_lock(&dev_priv->sb_lock);
147 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
148 CCK_FUSE_HPLL_FREQ_MASK;
149 mutex_unlock(&dev_priv->sb_lock);
150
151 return vco_freq[hpll_freq] * 1000;
152 }
153
154 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
155 const char *name, u32 reg, int ref_freq)
156 {
157 u32 val;
158 int divider;
159
160 mutex_lock(&dev_priv->sb_lock);
161 val = vlv_cck_read(dev_priv, reg);
162 mutex_unlock(&dev_priv->sb_lock);
163
164 divider = val & CCK_FREQUENCY_VALUES;
165
166 WARN((val & CCK_FREQUENCY_STATUS) !=
167 (divider << CCK_FREQUENCY_STATUS_SHIFT),
168 "%s change in progress\n", name);
169
170 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
171 }
172
173 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
174 const char *name, u32 reg)
175 {
176 if (dev_priv->hpll_freq == 0)
177 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
178
179 return vlv_get_cck_clock(dev_priv, name, reg,
180 dev_priv->hpll_freq);
181 }
182
183 static int
184 intel_pch_rawclk(struct drm_i915_private *dev_priv)
185 {
186 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
187 }
188
189 static int
190 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
191 {
192 /* RAWCLK_FREQ_VLV register updated from power well code */
193 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
194 CCK_DISPLAY_REF_CLOCK_CONTROL);
195 }
196
197 static int
198 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
199 {
200 uint32_t clkcfg;
201
202 /* hrawclock is 1/4 the FSB frequency */
203 clkcfg = I915_READ(CLKCFG);
204 switch (clkcfg & CLKCFG_FSB_MASK) {
205 case CLKCFG_FSB_400:
206 return 100000;
207 case CLKCFG_FSB_533:
208 return 133333;
209 case CLKCFG_FSB_667:
210 return 166667;
211 case CLKCFG_FSB_800:
212 return 200000;
213 case CLKCFG_FSB_1067:
214 return 266667;
215 case CLKCFG_FSB_1333:
216 return 333333;
217 /* these two are just a guess; one of them might be right */
218 case CLKCFG_FSB_1600:
219 case CLKCFG_FSB_1600_ALT:
220 return 400000;
221 default:
222 return 133333;
223 }
224 }
225
226 void intel_update_rawclk(struct drm_i915_private *dev_priv)
227 {
228 if (HAS_PCH_SPLIT(dev_priv))
229 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
230 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
231 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
232 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
233 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
234 else
235 return; /* no rawclk on other platforms, or no need to know it */
236
237 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
238 }
239
240 static void intel_update_czclk(struct drm_i915_private *dev_priv)
241 {
242 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
243 return;
244
245 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
246 CCK_CZ_CLOCK_CONTROL);
247
248 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
249 }
250
251 static inline u32 /* units of 100MHz */
252 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
253 const struct intel_crtc_state *pipe_config)
254 {
255 if (HAS_DDI(dev_priv))
256 return pipe_config->port_clock; /* SPLL */
257 else if (IS_GEN5(dev_priv))
258 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
259 else
260 return 270000;
261 }
262
263 static const struct intel_limit intel_limits_i8xx_dac = {
264 .dot = { .min = 25000, .max = 350000 },
265 .vco = { .min = 908000, .max = 1512000 },
266 .n = { .min = 2, .max = 16 },
267 .m = { .min = 96, .max = 140 },
268 .m1 = { .min = 18, .max = 26 },
269 .m2 = { .min = 6, .max = 16 },
270 .p = { .min = 4, .max = 128 },
271 .p1 = { .min = 2, .max = 33 },
272 .p2 = { .dot_limit = 165000,
273 .p2_slow = 4, .p2_fast = 2 },
274 };
275
276 static const struct intel_limit intel_limits_i8xx_dvo = {
277 .dot = { .min = 25000, .max = 350000 },
278 .vco = { .min = 908000, .max = 1512000 },
279 .n = { .min = 2, .max = 16 },
280 .m = { .min = 96, .max = 140 },
281 .m1 = { .min = 18, .max = 26 },
282 .m2 = { .min = 6, .max = 16 },
283 .p = { .min = 4, .max = 128 },
284 .p1 = { .min = 2, .max = 33 },
285 .p2 = { .dot_limit = 165000,
286 .p2_slow = 4, .p2_fast = 4 },
287 };
288
289 static const struct intel_limit intel_limits_i8xx_lvds = {
290 .dot = { .min = 25000, .max = 350000 },
291 .vco = { .min = 908000, .max = 1512000 },
292 .n = { .min = 2, .max = 16 },
293 .m = { .min = 96, .max = 140 },
294 .m1 = { .min = 18, .max = 26 },
295 .m2 = { .min = 6, .max = 16 },
296 .p = { .min = 4, .max = 128 },
297 .p1 = { .min = 1, .max = 6 },
298 .p2 = { .dot_limit = 165000,
299 .p2_slow = 14, .p2_fast = 7 },
300 };
301
302 static const struct intel_limit intel_limits_i9xx_sdvo = {
303 .dot = { .min = 20000, .max = 400000 },
304 .vco = { .min = 1400000, .max = 2800000 },
305 .n = { .min = 1, .max = 6 },
306 .m = { .min = 70, .max = 120 },
307 .m1 = { .min = 8, .max = 18 },
308 .m2 = { .min = 3, .max = 7 },
309 .p = { .min = 5, .max = 80 },
310 .p1 = { .min = 1, .max = 8 },
311 .p2 = { .dot_limit = 200000,
312 .p2_slow = 10, .p2_fast = 5 },
313 };
314
315 static const struct intel_limit intel_limits_i9xx_lvds = {
316 .dot = { .min = 20000, .max = 400000 },
317 .vco = { .min = 1400000, .max = 2800000 },
318 .n = { .min = 1, .max = 6 },
319 .m = { .min = 70, .max = 120 },
320 .m1 = { .min = 8, .max = 18 },
321 .m2 = { .min = 3, .max = 7 },
322 .p = { .min = 7, .max = 98 },
323 .p1 = { .min = 1, .max = 8 },
324 .p2 = { .dot_limit = 112000,
325 .p2_slow = 14, .p2_fast = 7 },
326 };
327
328
329 static const struct intel_limit intel_limits_g4x_sdvo = {
330 .dot = { .min = 25000, .max = 270000 },
331 .vco = { .min = 1750000, .max = 3500000},
332 .n = { .min = 1, .max = 4 },
333 .m = { .min = 104, .max = 138 },
334 .m1 = { .min = 17, .max = 23 },
335 .m2 = { .min = 5, .max = 11 },
336 .p = { .min = 10, .max = 30 },
337 .p1 = { .min = 1, .max = 3},
338 .p2 = { .dot_limit = 270000,
339 .p2_slow = 10,
340 .p2_fast = 10
341 },
342 };
343
344 static const struct intel_limit intel_limits_g4x_hdmi = {
345 .dot = { .min = 22000, .max = 400000 },
346 .vco = { .min = 1750000, .max = 3500000},
347 .n = { .min = 1, .max = 4 },
348 .m = { .min = 104, .max = 138 },
349 .m1 = { .min = 16, .max = 23 },
350 .m2 = { .min = 5, .max = 11 },
351 .p = { .min = 5, .max = 80 },
352 .p1 = { .min = 1, .max = 8},
353 .p2 = { .dot_limit = 165000,
354 .p2_slow = 10, .p2_fast = 5 },
355 };
356
357 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
358 .dot = { .min = 20000, .max = 115000 },
359 .vco = { .min = 1750000, .max = 3500000 },
360 .n = { .min = 1, .max = 3 },
361 .m = { .min = 104, .max = 138 },
362 .m1 = { .min = 17, .max = 23 },
363 .m2 = { .min = 5, .max = 11 },
364 .p = { .min = 28, .max = 112 },
365 .p1 = { .min = 2, .max = 8 },
366 .p2 = { .dot_limit = 0,
367 .p2_slow = 14, .p2_fast = 14
368 },
369 };
370
371 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
372 .dot = { .min = 80000, .max = 224000 },
373 .vco = { .min = 1750000, .max = 3500000 },
374 .n = { .min = 1, .max = 3 },
375 .m = { .min = 104, .max = 138 },
376 .m1 = { .min = 17, .max = 23 },
377 .m2 = { .min = 5, .max = 11 },
378 .p = { .min = 14, .max = 42 },
379 .p1 = { .min = 2, .max = 6 },
380 .p2 = { .dot_limit = 0,
381 .p2_slow = 7, .p2_fast = 7
382 },
383 };
384
385 static const struct intel_limit intel_limits_pineview_sdvo = {
386 .dot = { .min = 20000, .max = 400000},
387 .vco = { .min = 1700000, .max = 3500000 },
388 /* Pineview's Ncounter is a ring counter */
389 .n = { .min = 3, .max = 6 },
390 .m = { .min = 2, .max = 256 },
391 /* Pineview only has one combined m divider, which we treat as m2. */
392 .m1 = { .min = 0, .max = 0 },
393 .m2 = { .min = 0, .max = 254 },
394 .p = { .min = 5, .max = 80 },
395 .p1 = { .min = 1, .max = 8 },
396 .p2 = { .dot_limit = 200000,
397 .p2_slow = 10, .p2_fast = 5 },
398 };
399
400 static const struct intel_limit intel_limits_pineview_lvds = {
401 .dot = { .min = 20000, .max = 400000 },
402 .vco = { .min = 1700000, .max = 3500000 },
403 .n = { .min = 3, .max = 6 },
404 .m = { .min = 2, .max = 256 },
405 .m1 = { .min = 0, .max = 0 },
406 .m2 = { .min = 0, .max = 254 },
407 .p = { .min = 7, .max = 112 },
408 .p1 = { .min = 1, .max = 8 },
409 .p2 = { .dot_limit = 112000,
410 .p2_slow = 14, .p2_fast = 14 },
411 };
412
413 /* Ironlake / Sandybridge
414 *
415 * We calculate clock using (register_value + 2) for N/M1/M2, so here
416 * the range value for them is (actual_value - 2).
417 */
418 static const struct intel_limit intel_limits_ironlake_dac = {
419 .dot = { .min = 25000, .max = 350000 },
420 .vco = { .min = 1760000, .max = 3510000 },
421 .n = { .min = 1, .max = 5 },
422 .m = { .min = 79, .max = 127 },
423 .m1 = { .min = 12, .max = 22 },
424 .m2 = { .min = 5, .max = 9 },
425 .p = { .min = 5, .max = 80 },
426 .p1 = { .min = 1, .max = 8 },
427 .p2 = { .dot_limit = 225000,
428 .p2_slow = 10, .p2_fast = 5 },
429 };
430
431 static const struct intel_limit intel_limits_ironlake_single_lvds = {
432 .dot = { .min = 25000, .max = 350000 },
433 .vco = { .min = 1760000, .max = 3510000 },
434 .n = { .min = 1, .max = 3 },
435 .m = { .min = 79, .max = 118 },
436 .m1 = { .min = 12, .max = 22 },
437 .m2 = { .min = 5, .max = 9 },
438 .p = { .min = 28, .max = 112 },
439 .p1 = { .min = 2, .max = 8 },
440 .p2 = { .dot_limit = 225000,
441 .p2_slow = 14, .p2_fast = 14 },
442 };
443
444 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
445 .dot = { .min = 25000, .max = 350000 },
446 .vco = { .min = 1760000, .max = 3510000 },
447 .n = { .min = 1, .max = 3 },
448 .m = { .min = 79, .max = 127 },
449 .m1 = { .min = 12, .max = 22 },
450 .m2 = { .min = 5, .max = 9 },
451 .p = { .min = 14, .max = 56 },
452 .p1 = { .min = 2, .max = 8 },
453 .p2 = { .dot_limit = 225000,
454 .p2_slow = 7, .p2_fast = 7 },
455 };
456
457 /* LVDS 100mhz refclk limits. */
458 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
459 .dot = { .min = 25000, .max = 350000 },
460 .vco = { .min = 1760000, .max = 3510000 },
461 .n = { .min = 1, .max = 2 },
462 .m = { .min = 79, .max = 126 },
463 .m1 = { .min = 12, .max = 22 },
464 .m2 = { .min = 5, .max = 9 },
465 .p = { .min = 28, .max = 112 },
466 .p1 = { .min = 2, .max = 8 },
467 .p2 = { .dot_limit = 225000,
468 .p2_slow = 14, .p2_fast = 14 },
469 };
470
471 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
472 .dot = { .min = 25000, .max = 350000 },
473 .vco = { .min = 1760000, .max = 3510000 },
474 .n = { .min = 1, .max = 3 },
475 .m = { .min = 79, .max = 126 },
476 .m1 = { .min = 12, .max = 22 },
477 .m2 = { .min = 5, .max = 9 },
478 .p = { .min = 14, .max = 42 },
479 .p1 = { .min = 2, .max = 6 },
480 .p2 = { .dot_limit = 225000,
481 .p2_slow = 7, .p2_fast = 7 },
482 };
483
484 static const struct intel_limit intel_limits_vlv = {
485 /*
486 * These are the data rate limits (measured in fast clocks)
487 * since those are the strictest limits we have. The fast
488 * clock and actual rate limits are more relaxed, so checking
489 * them would make no difference.
490 */
491 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
492 .vco = { .min = 4000000, .max = 6000000 },
493 .n = { .min = 1, .max = 7 },
494 .m1 = { .min = 2, .max = 3 },
495 .m2 = { .min = 11, .max = 156 },
496 .p1 = { .min = 2, .max = 3 },
497 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
498 };
499
500 static const struct intel_limit intel_limits_chv = {
501 /*
502 * These are the data rate limits (measured in fast clocks)
503 * since those are the strictest limits we have. The fast
504 * clock and actual rate limits are more relaxed, so checking
505 * them would make no difference.
506 */
507 .dot = { .min = 25000 * 5, .max = 540000 * 5},
508 .vco = { .min = 4800000, .max = 6480000 },
509 .n = { .min = 1, .max = 1 },
510 .m1 = { .min = 2, .max = 2 },
511 .m2 = { .min = 24 << 22, .max = 175 << 22 },
512 .p1 = { .min = 2, .max = 4 },
513 .p2 = { .p2_slow = 1, .p2_fast = 14 },
514 };
515
516 static const struct intel_limit intel_limits_bxt = {
517 /* FIXME: find real dot limits */
518 .dot = { .min = 0, .max = INT_MAX },
519 .vco = { .min = 4800000, .max = 6700000 },
520 .n = { .min = 1, .max = 1 },
521 .m1 = { .min = 2, .max = 2 },
522 /* FIXME: find real m2 limits */
523 .m2 = { .min = 2 << 22, .max = 255 << 22 },
524 .p1 = { .min = 2, .max = 4 },
525 .p2 = { .p2_slow = 1, .p2_fast = 20 },
526 };
527
528 static bool
529 needs_modeset(struct drm_crtc_state *state)
530 {
531 return drm_atomic_crtc_needs_modeset(state);
532 }
533
534 /*
535 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
536 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
537 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
538 * The helpers' return value is the rate of the clock that is fed to the
539 * display engine's pipe which can be the above fast dot clock rate or a
540 * divided-down version of it.
541 */
542 /* m1 is reserved as 0 in Pineview, n is a ring counter */
543 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
544 {
545 clock->m = clock->m2 + 2;
546 clock->p = clock->p1 * clock->p2;
547 if (WARN_ON(clock->n == 0 || clock->p == 0))
548 return 0;
549 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
550 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
551
552 return clock->dot;
553 }
554
555 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
556 {
557 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
558 }
559
560 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
561 {
562 clock->m = i9xx_dpll_compute_m(clock);
563 clock->p = clock->p1 * clock->p2;
564 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
565 return 0;
566 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
567 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
568
569 return clock->dot;
570 }
571
572 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
573 {
574 clock->m = clock->m1 * clock->m2;
575 clock->p = clock->p1 * clock->p2;
576 if (WARN_ON(clock->n == 0 || clock->p == 0))
577 return 0;
578 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
579 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
580
581 return clock->dot / 5;
582 }
583
584 int chv_calc_dpll_params(int refclk, struct dpll *clock)
585 {
586 clock->m = clock->m1 * clock->m2;
587 clock->p = clock->p1 * clock->p2;
588 if (WARN_ON(clock->n == 0 || clock->p == 0))
589 return 0;
590 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
591 clock->n << 22);
592 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
593
594 return clock->dot / 5;
595 }
596
597 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
598 /**
599 * Returns whether the given set of divisors are valid for a given refclk with
600 * the given connectors.
601 */
602
603 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
604 const struct intel_limit *limit,
605 const struct dpll *clock)
606 {
607 if (clock->n < limit->n.min || limit->n.max < clock->n)
608 INTELPllInvalid("n out of range\n");
609 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
610 INTELPllInvalid("p1 out of range\n");
611 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
612 INTELPllInvalid("m2 out of range\n");
613 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
614 INTELPllInvalid("m1 out of range\n");
615
616 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
617 !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv))
618 if (clock->m1 <= clock->m2)
619 INTELPllInvalid("m1 <= m2\n");
620
621 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
622 !IS_BROXTON(dev_priv)) {
623 if (clock->p < limit->p.min || limit->p.max < clock->p)
624 INTELPllInvalid("p out of range\n");
625 if (clock->m < limit->m.min || limit->m.max < clock->m)
626 INTELPllInvalid("m out of range\n");
627 }
628
629 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
630 INTELPllInvalid("vco out of range\n");
631 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
632 * connector, etc., rather than just a single range.
633 */
634 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
635 INTELPllInvalid("dot out of range\n");
636
637 return true;
638 }
639
640 static int
641 i9xx_select_p2_div(const struct intel_limit *limit,
642 const struct intel_crtc_state *crtc_state,
643 int target)
644 {
645 struct drm_device *dev = crtc_state->base.crtc->dev;
646
647 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
648 /*
649 * For LVDS just rely on its current settings for dual-channel.
650 * We haven't figured out how to reliably set up different
651 * single/dual channel state, if we even can.
652 */
653 if (intel_is_dual_link_lvds(dev))
654 return limit->p2.p2_fast;
655 else
656 return limit->p2.p2_slow;
657 } else {
658 if (target < limit->p2.dot_limit)
659 return limit->p2.p2_slow;
660 else
661 return limit->p2.p2_fast;
662 }
663 }
664
665 /*
666 * Returns a set of divisors for the desired target clock with the given
667 * refclk, or FALSE. The returned values represent the clock equation:
668 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
669 *
670 * Target and reference clocks are specified in kHz.
671 *
672 * If match_clock is provided, then best_clock P divider must match the P
673 * divider from @match_clock used for LVDS downclocking.
674 */
675 static bool
676 i9xx_find_best_dpll(const struct intel_limit *limit,
677 struct intel_crtc_state *crtc_state,
678 int target, int refclk, struct dpll *match_clock,
679 struct dpll *best_clock)
680 {
681 struct drm_device *dev = crtc_state->base.crtc->dev;
682 struct dpll clock;
683 int err = target;
684
685 memset(best_clock, 0, sizeof(*best_clock));
686
687 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
688
689 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
690 clock.m1++) {
691 for (clock.m2 = limit->m2.min;
692 clock.m2 <= limit->m2.max; clock.m2++) {
693 if (clock.m2 >= clock.m1)
694 break;
695 for (clock.n = limit->n.min;
696 clock.n <= limit->n.max; clock.n++) {
697 for (clock.p1 = limit->p1.min;
698 clock.p1 <= limit->p1.max; clock.p1++) {
699 int this_err;
700
701 i9xx_calc_dpll_params(refclk, &clock);
702 if (!intel_PLL_is_valid(to_i915(dev),
703 limit,
704 &clock))
705 continue;
706 if (match_clock &&
707 clock.p != match_clock->p)
708 continue;
709
710 this_err = abs(clock.dot - target);
711 if (this_err < err) {
712 *best_clock = clock;
713 err = this_err;
714 }
715 }
716 }
717 }
718 }
719
720 return (err != target);
721 }
722
723 /*
724 * Returns a set of divisors for the desired target clock with the given
725 * refclk, or FALSE. The returned values represent the clock equation:
726 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
727 *
728 * Target and reference clocks are specified in kHz.
729 *
730 * If match_clock is provided, then best_clock P divider must match the P
731 * divider from @match_clock used for LVDS downclocking.
732 */
733 static bool
734 pnv_find_best_dpll(const struct intel_limit *limit,
735 struct intel_crtc_state *crtc_state,
736 int target, int refclk, struct dpll *match_clock,
737 struct dpll *best_clock)
738 {
739 struct drm_device *dev = crtc_state->base.crtc->dev;
740 struct dpll clock;
741 int err = target;
742
743 memset(best_clock, 0, sizeof(*best_clock));
744
745 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
746
747 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
748 clock.m1++) {
749 for (clock.m2 = limit->m2.min;
750 clock.m2 <= limit->m2.max; clock.m2++) {
751 for (clock.n = limit->n.min;
752 clock.n <= limit->n.max; clock.n++) {
753 for (clock.p1 = limit->p1.min;
754 clock.p1 <= limit->p1.max; clock.p1++) {
755 int this_err;
756
757 pnv_calc_dpll_params(refclk, &clock);
758 if (!intel_PLL_is_valid(to_i915(dev),
759 limit,
760 &clock))
761 continue;
762 if (match_clock &&
763 clock.p != match_clock->p)
764 continue;
765
766 this_err = abs(clock.dot - target);
767 if (this_err < err) {
768 *best_clock = clock;
769 err = this_err;
770 }
771 }
772 }
773 }
774 }
775
776 return (err != target);
777 }
778
779 /*
780 * Returns a set of divisors for the desired target clock with the given
781 * refclk, or FALSE. The returned values represent the clock equation:
782 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
783 *
784 * Target and reference clocks are specified in kHz.
785 *
786 * If match_clock is provided, then best_clock P divider must match the P
787 * divider from @match_clock used for LVDS downclocking.
788 */
789 static bool
790 g4x_find_best_dpll(const struct intel_limit *limit,
791 struct intel_crtc_state *crtc_state,
792 int target, int refclk, struct dpll *match_clock,
793 struct dpll *best_clock)
794 {
795 struct drm_device *dev = crtc_state->base.crtc->dev;
796 struct dpll clock;
797 int max_n;
798 bool found = false;
799 /* approximately equals target * 0.00585 */
800 int err_most = (target >> 8) + (target >> 9);
801
802 memset(best_clock, 0, sizeof(*best_clock));
803
804 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
805
806 max_n = limit->n.max;
807 /* based on hardware requirement, prefer smaller n to precision */
808 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
809 /* based on hardware requirement, prefere larger m1,m2 */
810 for (clock.m1 = limit->m1.max;
811 clock.m1 >= limit->m1.min; clock.m1--) {
812 for (clock.m2 = limit->m2.max;
813 clock.m2 >= limit->m2.min; clock.m2--) {
814 for (clock.p1 = limit->p1.max;
815 clock.p1 >= limit->p1.min; clock.p1--) {
816 int this_err;
817
818 i9xx_calc_dpll_params(refclk, &clock);
819 if (!intel_PLL_is_valid(to_i915(dev),
820 limit,
821 &clock))
822 continue;
823
824 this_err = abs(clock.dot - target);
825 if (this_err < err_most) {
826 *best_clock = clock;
827 err_most = this_err;
828 max_n = clock.n;
829 found = true;
830 }
831 }
832 }
833 }
834 }
835 return found;
836 }
837
838 /*
839 * Check if the calculated PLL configuration is more optimal compared to the
840 * best configuration and error found so far. Return the calculated error.
841 */
842 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
843 const struct dpll *calculated_clock,
844 const struct dpll *best_clock,
845 unsigned int best_error_ppm,
846 unsigned int *error_ppm)
847 {
848 /*
849 * For CHV ignore the error and consider only the P value.
850 * Prefer a bigger P value based on HW requirements.
851 */
852 if (IS_CHERRYVIEW(to_i915(dev))) {
853 *error_ppm = 0;
854
855 return calculated_clock->p > best_clock->p;
856 }
857
858 if (WARN_ON_ONCE(!target_freq))
859 return false;
860
861 *error_ppm = div_u64(1000000ULL *
862 abs(target_freq - calculated_clock->dot),
863 target_freq);
864 /*
865 * Prefer a better P value over a better (smaller) error if the error
866 * is small. Ensure this preference for future configurations too by
867 * setting the error to 0.
868 */
869 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
870 *error_ppm = 0;
871
872 return true;
873 }
874
875 return *error_ppm + 10 < best_error_ppm;
876 }
877
878 /*
879 * Returns a set of divisors for the desired target clock with the given
880 * refclk, or FALSE. The returned values represent the clock equation:
881 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
882 */
883 static bool
884 vlv_find_best_dpll(const struct intel_limit *limit,
885 struct intel_crtc_state *crtc_state,
886 int target, int refclk, struct dpll *match_clock,
887 struct dpll *best_clock)
888 {
889 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
890 struct drm_device *dev = crtc->base.dev;
891 struct dpll clock;
892 unsigned int bestppm = 1000000;
893 /* min update 19.2 MHz */
894 int max_n = min(limit->n.max, refclk / 19200);
895 bool found = false;
896
897 target *= 5; /* fast clock */
898
899 memset(best_clock, 0, sizeof(*best_clock));
900
901 /* based on hardware requirement, prefer smaller n to precision */
902 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
903 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
904 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
905 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
906 clock.p = clock.p1 * clock.p2;
907 /* based on hardware requirement, prefer bigger m1,m2 values */
908 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
909 unsigned int ppm;
910
911 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
912 refclk * clock.m1);
913
914 vlv_calc_dpll_params(refclk, &clock);
915
916 if (!intel_PLL_is_valid(to_i915(dev),
917 limit,
918 &clock))
919 continue;
920
921 if (!vlv_PLL_is_optimal(dev, target,
922 &clock,
923 best_clock,
924 bestppm, &ppm))
925 continue;
926
927 *best_clock = clock;
928 bestppm = ppm;
929 found = true;
930 }
931 }
932 }
933 }
934
935 return found;
936 }
937
938 /*
939 * Returns a set of divisors for the desired target clock with the given
940 * refclk, or FALSE. The returned values represent the clock equation:
941 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
942 */
943 static bool
944 chv_find_best_dpll(const struct intel_limit *limit,
945 struct intel_crtc_state *crtc_state,
946 int target, int refclk, struct dpll *match_clock,
947 struct dpll *best_clock)
948 {
949 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
950 struct drm_device *dev = crtc->base.dev;
951 unsigned int best_error_ppm;
952 struct dpll clock;
953 uint64_t m2;
954 int found = false;
955
956 memset(best_clock, 0, sizeof(*best_clock));
957 best_error_ppm = 1000000;
958
959 /*
960 * Based on hardware doc, the n always set to 1, and m1 always
961 * set to 2. If requires to support 200Mhz refclk, we need to
962 * revisit this because n may not 1 anymore.
963 */
964 clock.n = 1, clock.m1 = 2;
965 target *= 5; /* fast clock */
966
967 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
968 for (clock.p2 = limit->p2.p2_fast;
969 clock.p2 >= limit->p2.p2_slow;
970 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
971 unsigned int error_ppm;
972
973 clock.p = clock.p1 * clock.p2;
974
975 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
976 clock.n) << 22, refclk * clock.m1);
977
978 if (m2 > INT_MAX/clock.m1)
979 continue;
980
981 clock.m2 = m2;
982
983 chv_calc_dpll_params(refclk, &clock);
984
985 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
986 continue;
987
988 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
989 best_error_ppm, &error_ppm))
990 continue;
991
992 *best_clock = clock;
993 best_error_ppm = error_ppm;
994 found = true;
995 }
996 }
997
998 return found;
999 }
1000
1001 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1002 struct dpll *best_clock)
1003 {
1004 int refclk = 100000;
1005 const struct intel_limit *limit = &intel_limits_bxt;
1006
1007 return chv_find_best_dpll(limit, crtc_state,
1008 target_clock, refclk, NULL, best_clock);
1009 }
1010
1011 bool intel_crtc_active(struct intel_crtc *crtc)
1012 {
1013 /* Be paranoid as we can arrive here with only partial
1014 * state retrieved from the hardware during setup.
1015 *
1016 * We can ditch the adjusted_mode.crtc_clock check as soon
1017 * as Haswell has gained clock readout/fastboot support.
1018 *
1019 * We can ditch the crtc->primary->fb check as soon as we can
1020 * properly reconstruct framebuffers.
1021 *
1022 * FIXME: The intel_crtc->active here should be switched to
1023 * crtc->state->active once we have proper CRTC states wired up
1024 * for atomic.
1025 */
1026 return crtc->active && crtc->base.primary->state->fb &&
1027 crtc->config->base.adjusted_mode.crtc_clock;
1028 }
1029
1030 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1031 enum pipe pipe)
1032 {
1033 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1034
1035 return crtc->config->cpu_transcoder;
1036 }
1037
1038 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
1039 {
1040 i915_reg_t reg = PIPEDSL(pipe);
1041 u32 line1, line2;
1042 u32 line_mask;
1043
1044 if (IS_GEN2(dev_priv))
1045 line_mask = DSL_LINEMASK_GEN2;
1046 else
1047 line_mask = DSL_LINEMASK_GEN3;
1048
1049 line1 = I915_READ(reg) & line_mask;
1050 msleep(5);
1051 line2 = I915_READ(reg) & line_mask;
1052
1053 return line1 == line2;
1054 }
1055
1056 /*
1057 * intel_wait_for_pipe_off - wait for pipe to turn off
1058 * @crtc: crtc whose pipe to wait for
1059 *
1060 * After disabling a pipe, we can't wait for vblank in the usual way,
1061 * spinning on the vblank interrupt status bit, since we won't actually
1062 * see an interrupt when the pipe is disabled.
1063 *
1064 * On Gen4 and above:
1065 * wait for the pipe register state bit to turn off
1066 *
1067 * Otherwise:
1068 * wait for the display line value to settle (it usually
1069 * ends up stopping at the start of the next frame).
1070 *
1071 */
1072 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1073 {
1074 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1075 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1076 enum pipe pipe = crtc->pipe;
1077
1078 if (INTEL_GEN(dev_priv) >= 4) {
1079 i915_reg_t reg = PIPECONF(cpu_transcoder);
1080
1081 /* Wait for the Pipe State to go off */
1082 if (intel_wait_for_register(dev_priv,
1083 reg, I965_PIPECONF_ACTIVE, 0,
1084 100))
1085 WARN(1, "pipe_off wait timed out\n");
1086 } else {
1087 /* Wait for the display line to settle */
1088 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1089 WARN(1, "pipe_off wait timed out\n");
1090 }
1091 }
1092
1093 /* Only for pre-ILK configs */
1094 void assert_pll(struct drm_i915_private *dev_priv,
1095 enum pipe pipe, bool state)
1096 {
1097 u32 val;
1098 bool cur_state;
1099
1100 val = I915_READ(DPLL(pipe));
1101 cur_state = !!(val & DPLL_VCO_ENABLE);
1102 I915_STATE_WARN(cur_state != state,
1103 "PLL state assertion failure (expected %s, current %s)\n",
1104 onoff(state), onoff(cur_state));
1105 }
1106
1107 /* XXX: the dsi pll is shared between MIPI DSI ports */
1108 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1109 {
1110 u32 val;
1111 bool cur_state;
1112
1113 mutex_lock(&dev_priv->sb_lock);
1114 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1115 mutex_unlock(&dev_priv->sb_lock);
1116
1117 cur_state = val & DSI_PLL_VCO_EN;
1118 I915_STATE_WARN(cur_state != state,
1119 "DSI PLL state assertion failure (expected %s, current %s)\n",
1120 onoff(state), onoff(cur_state));
1121 }
1122
1123 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1124 enum pipe pipe, bool state)
1125 {
1126 bool cur_state;
1127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128 pipe);
1129
1130 if (HAS_DDI(dev_priv)) {
1131 /* DDI does not have a specific FDI_TX register */
1132 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1133 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1134 } else {
1135 u32 val = I915_READ(FDI_TX_CTL(pipe));
1136 cur_state = !!(val & FDI_TX_ENABLE);
1137 }
1138 I915_STATE_WARN(cur_state != state,
1139 "FDI TX state assertion failure (expected %s, current %s)\n",
1140 onoff(state), onoff(cur_state));
1141 }
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146 enum pipe pipe, bool state)
1147 {
1148 u32 val;
1149 bool cur_state;
1150
1151 val = I915_READ(FDI_RX_CTL(pipe));
1152 cur_state = !!(val & FDI_RX_ENABLE);
1153 I915_STATE_WARN(cur_state != state,
1154 "FDI RX state assertion failure (expected %s, current %s)\n",
1155 onoff(state), onoff(cur_state));
1156 }
1157 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1158 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1159
1160 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1161 enum pipe pipe)
1162 {
1163 u32 val;
1164
1165 /* ILK FDI PLL is always enabled */
1166 if (IS_GEN5(dev_priv))
1167 return;
1168
1169 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1170 if (HAS_DDI(dev_priv))
1171 return;
1172
1173 val = I915_READ(FDI_TX_CTL(pipe));
1174 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178 enum pipe pipe, bool state)
1179 {
1180 u32 val;
1181 bool cur_state;
1182
1183 val = I915_READ(FDI_RX_CTL(pipe));
1184 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1185 I915_STATE_WARN(cur_state != state,
1186 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1187 onoff(state), onoff(cur_state));
1188 }
1189
1190 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1191 {
1192 i915_reg_t pp_reg;
1193 u32 val;
1194 enum pipe panel_pipe = PIPE_A;
1195 bool locked = true;
1196
1197 if (WARN_ON(HAS_DDI(dev_priv)))
1198 return;
1199
1200 if (HAS_PCH_SPLIT(dev_priv)) {
1201 u32 port_sel;
1202
1203 pp_reg = PP_CONTROL(0);
1204 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1205
1206 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1207 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1208 panel_pipe = PIPE_B;
1209 /* XXX: else fix for eDP */
1210 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1211 /* presumably write lock depends on pipe, not port select */
1212 pp_reg = PP_CONTROL(pipe);
1213 panel_pipe = pipe;
1214 } else {
1215 pp_reg = PP_CONTROL(0);
1216 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1217 panel_pipe = PIPE_B;
1218 }
1219
1220 val = I915_READ(pp_reg);
1221 if (!(val & PANEL_POWER_ON) ||
1222 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1223 locked = false;
1224
1225 I915_STATE_WARN(panel_pipe == pipe && locked,
1226 "panel assertion failure, pipe %c regs locked\n",
1227 pipe_name(pipe));
1228 }
1229
1230 static void assert_cursor(struct drm_i915_private *dev_priv,
1231 enum pipe pipe, bool state)
1232 {
1233 bool cur_state;
1234
1235 if (IS_845G(dev_priv) || IS_I865G(dev_priv))
1236 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1237 else
1238 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1239
1240 I915_STATE_WARN(cur_state != state,
1241 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1242 pipe_name(pipe), onoff(state), onoff(cur_state));
1243 }
1244 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1245 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1246
1247 void assert_pipe(struct drm_i915_private *dev_priv,
1248 enum pipe pipe, bool state)
1249 {
1250 bool cur_state;
1251 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1252 pipe);
1253 enum intel_display_power_domain power_domain;
1254
1255 /* if we need the pipe quirk it must be always on */
1256 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1257 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1258 state = true;
1259
1260 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1261 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1262 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1263 cur_state = !!(val & PIPECONF_ENABLE);
1264
1265 intel_display_power_put(dev_priv, power_domain);
1266 } else {
1267 cur_state = false;
1268 }
1269
1270 I915_STATE_WARN(cur_state != state,
1271 "pipe %c assertion failure (expected %s, current %s)\n",
1272 pipe_name(pipe), onoff(state), onoff(cur_state));
1273 }
1274
1275 static void assert_plane(struct drm_i915_private *dev_priv,
1276 enum plane plane, bool state)
1277 {
1278 u32 val;
1279 bool cur_state;
1280
1281 val = I915_READ(DSPCNTR(plane));
1282 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1283 I915_STATE_WARN(cur_state != state,
1284 "plane %c assertion failure (expected %s, current %s)\n",
1285 plane_name(plane), onoff(state), onoff(cur_state));
1286 }
1287
1288 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1289 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1290
1291 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293 {
1294 int i;
1295
1296 /* Primary planes are fixed to pipes on gen4+ */
1297 if (INTEL_GEN(dev_priv) >= 4) {
1298 u32 val = I915_READ(DSPCNTR(pipe));
1299 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1300 "plane %c assertion failure, should be disabled but not\n",
1301 plane_name(pipe));
1302 return;
1303 }
1304
1305 /* Need to check both planes against the pipe */
1306 for_each_pipe(dev_priv, i) {
1307 u32 val = I915_READ(DSPCNTR(i));
1308 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1309 DISPPLANE_SEL_PIPE_SHIFT;
1310 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1311 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1312 plane_name(i), pipe_name(pipe));
1313 }
1314 }
1315
1316 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1317 enum pipe pipe)
1318 {
1319 int sprite;
1320
1321 if (INTEL_GEN(dev_priv) >= 9) {
1322 for_each_sprite(dev_priv, pipe, sprite) {
1323 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1324 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1325 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1326 sprite, pipe_name(pipe));
1327 }
1328 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1329 for_each_sprite(dev_priv, pipe, sprite) {
1330 u32 val = I915_READ(SPCNTR(pipe, sprite));
1331 I915_STATE_WARN(val & SP_ENABLE,
1332 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1333 sprite_name(pipe, sprite), pipe_name(pipe));
1334 }
1335 } else if (INTEL_GEN(dev_priv) >= 7) {
1336 u32 val = I915_READ(SPRCTL(pipe));
1337 I915_STATE_WARN(val & SPRITE_ENABLE,
1338 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1339 plane_name(pipe), pipe_name(pipe));
1340 } else if (INTEL_GEN(dev_priv) >= 5) {
1341 u32 val = I915_READ(DVSCNTR(pipe));
1342 I915_STATE_WARN(val & DVS_ENABLE,
1343 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344 plane_name(pipe), pipe_name(pipe));
1345 }
1346 }
1347
1348 static void assert_vblank_disabled(struct drm_crtc *crtc)
1349 {
1350 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1351 drm_crtc_vblank_put(crtc);
1352 }
1353
1354 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1355 enum pipe pipe)
1356 {
1357 u32 val;
1358 bool enabled;
1359
1360 val = I915_READ(PCH_TRANSCONF(pipe));
1361 enabled = !!(val & TRANS_ENABLE);
1362 I915_STATE_WARN(enabled,
1363 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1364 pipe_name(pipe));
1365 }
1366
1367 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1368 enum pipe pipe, u32 port_sel, u32 val)
1369 {
1370 if ((val & DP_PORT_EN) == 0)
1371 return false;
1372
1373 if (HAS_PCH_CPT(dev_priv)) {
1374 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1375 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1376 return false;
1377 } else if (IS_CHERRYVIEW(dev_priv)) {
1378 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1379 return false;
1380 } else {
1381 if ((val & DP_PIPE_MASK) != (pipe << 30))
1382 return false;
1383 }
1384 return true;
1385 }
1386
1387 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1388 enum pipe pipe, u32 val)
1389 {
1390 if ((val & SDVO_ENABLE) == 0)
1391 return false;
1392
1393 if (HAS_PCH_CPT(dev_priv)) {
1394 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1395 return false;
1396 } else if (IS_CHERRYVIEW(dev_priv)) {
1397 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1398 return false;
1399 } else {
1400 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1401 return false;
1402 }
1403 return true;
1404 }
1405
1406 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1407 enum pipe pipe, u32 val)
1408 {
1409 if ((val & LVDS_PORT_EN) == 0)
1410 return false;
1411
1412 if (HAS_PCH_CPT(dev_priv)) {
1413 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1414 return false;
1415 } else {
1416 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1417 return false;
1418 }
1419 return true;
1420 }
1421
1422 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1423 enum pipe pipe, u32 val)
1424 {
1425 if ((val & ADPA_DAC_ENABLE) == 0)
1426 return false;
1427 if (HAS_PCH_CPT(dev_priv)) {
1428 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1429 return false;
1430 } else {
1431 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1432 return false;
1433 }
1434 return true;
1435 }
1436
1437 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1438 enum pipe pipe, i915_reg_t reg,
1439 u32 port_sel)
1440 {
1441 u32 val = I915_READ(reg);
1442 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1443 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1444 i915_mmio_reg_offset(reg), pipe_name(pipe));
1445
1446 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1447 && (val & DP_PIPEB_SELECT),
1448 "IBX PCH dp port still using transcoder B\n");
1449 }
1450
1451 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1452 enum pipe pipe, i915_reg_t reg)
1453 {
1454 u32 val = I915_READ(reg);
1455 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1456 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1457 i915_mmio_reg_offset(reg), pipe_name(pipe));
1458
1459 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1460 && (val & SDVO_PIPE_B_SELECT),
1461 "IBX PCH hdmi port still using transcoder B\n");
1462 }
1463
1464 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1465 enum pipe pipe)
1466 {
1467 u32 val;
1468
1469 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1470 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1471 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1472
1473 val = I915_READ(PCH_ADPA);
1474 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1475 "PCH VGA enabled on transcoder %c, should be disabled\n",
1476 pipe_name(pipe));
1477
1478 val = I915_READ(PCH_LVDS);
1479 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1480 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1481 pipe_name(pipe));
1482
1483 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1484 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1485 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1486 }
1487
1488 static void _vlv_enable_pll(struct intel_crtc *crtc,
1489 const struct intel_crtc_state *pipe_config)
1490 {
1491 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1492 enum pipe pipe = crtc->pipe;
1493
1494 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1495 POSTING_READ(DPLL(pipe));
1496 udelay(150);
1497
1498 if (intel_wait_for_register(dev_priv,
1499 DPLL(pipe),
1500 DPLL_LOCK_VLV,
1501 DPLL_LOCK_VLV,
1502 1))
1503 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1504 }
1505
1506 static void vlv_enable_pll(struct intel_crtc *crtc,
1507 const struct intel_crtc_state *pipe_config)
1508 {
1509 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1510 enum pipe pipe = crtc->pipe;
1511
1512 assert_pipe_disabled(dev_priv, pipe);
1513
1514 /* PLL is protected by panel, make sure we can write it */
1515 assert_panel_unlocked(dev_priv, pipe);
1516
1517 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1518 _vlv_enable_pll(crtc, pipe_config);
1519
1520 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1521 POSTING_READ(DPLL_MD(pipe));
1522 }
1523
1524
1525 static void _chv_enable_pll(struct intel_crtc *crtc,
1526 const struct intel_crtc_state *pipe_config)
1527 {
1528 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1529 enum pipe pipe = crtc->pipe;
1530 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1531 u32 tmp;
1532
1533 mutex_lock(&dev_priv->sb_lock);
1534
1535 /* Enable back the 10bit clock to display controller */
1536 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1537 tmp |= DPIO_DCLKP_EN;
1538 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1539
1540 mutex_unlock(&dev_priv->sb_lock);
1541
1542 /*
1543 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1544 */
1545 udelay(1);
1546
1547 /* Enable PLL */
1548 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1549
1550 /* Check PLL is locked */
1551 if (intel_wait_for_register(dev_priv,
1552 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1553 1))
1554 DRM_ERROR("PLL %d failed to lock\n", pipe);
1555 }
1556
1557 static void chv_enable_pll(struct intel_crtc *crtc,
1558 const struct intel_crtc_state *pipe_config)
1559 {
1560 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1561 enum pipe pipe = crtc->pipe;
1562
1563 assert_pipe_disabled(dev_priv, pipe);
1564
1565 /* PLL is protected by panel, make sure we can write it */
1566 assert_panel_unlocked(dev_priv, pipe);
1567
1568 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1569 _chv_enable_pll(crtc, pipe_config);
1570
1571 if (pipe != PIPE_A) {
1572 /*
1573 * WaPixelRepeatModeFixForC0:chv
1574 *
1575 * DPLLCMD is AWOL. Use chicken bits to propagate
1576 * the value from DPLLBMD to either pipe B or C.
1577 */
1578 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1579 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1580 I915_WRITE(CBR4_VLV, 0);
1581 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1582
1583 /*
1584 * DPLLB VGA mode also seems to cause problems.
1585 * We should always have it disabled.
1586 */
1587 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1588 } else {
1589 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1590 POSTING_READ(DPLL_MD(pipe));
1591 }
1592 }
1593
1594 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1595 {
1596 struct intel_crtc *crtc;
1597 int count = 0;
1598
1599 for_each_intel_crtc(&dev_priv->drm, crtc) {
1600 count += crtc->base.state->active &&
1601 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1602 }
1603
1604 return count;
1605 }
1606
1607 static void i9xx_enable_pll(struct intel_crtc *crtc)
1608 {
1609 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1610 i915_reg_t reg = DPLL(crtc->pipe);
1611 u32 dpll = crtc->config->dpll_hw_state.dpll;
1612
1613 assert_pipe_disabled(dev_priv, crtc->pipe);
1614
1615 /* PLL is protected by panel, make sure we can write it */
1616 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1617 assert_panel_unlocked(dev_priv, crtc->pipe);
1618
1619 /* Enable DVO 2x clock on both PLLs if necessary */
1620 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1621 /*
1622 * It appears to be important that we don't enable this
1623 * for the current pipe before otherwise configuring the
1624 * PLL. No idea how this should be handled if multiple
1625 * DVO outputs are enabled simultaneosly.
1626 */
1627 dpll |= DPLL_DVO_2X_MODE;
1628 I915_WRITE(DPLL(!crtc->pipe),
1629 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1630 }
1631
1632 /*
1633 * Apparently we need to have VGA mode enabled prior to changing
1634 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1635 * dividers, even though the register value does change.
1636 */
1637 I915_WRITE(reg, 0);
1638
1639 I915_WRITE(reg, dpll);
1640
1641 /* Wait for the clocks to stabilize. */
1642 POSTING_READ(reg);
1643 udelay(150);
1644
1645 if (INTEL_GEN(dev_priv) >= 4) {
1646 I915_WRITE(DPLL_MD(crtc->pipe),
1647 crtc->config->dpll_hw_state.dpll_md);
1648 } else {
1649 /* The pixel multiplier can only be updated once the
1650 * DPLL is enabled and the clocks are stable.
1651 *
1652 * So write it again.
1653 */
1654 I915_WRITE(reg, dpll);
1655 }
1656
1657 /* We do this three times for luck */
1658 I915_WRITE(reg, dpll);
1659 POSTING_READ(reg);
1660 udelay(150); /* wait for warmup */
1661 I915_WRITE(reg, dpll);
1662 POSTING_READ(reg);
1663 udelay(150); /* wait for warmup */
1664 I915_WRITE(reg, dpll);
1665 POSTING_READ(reg);
1666 udelay(150); /* wait for warmup */
1667 }
1668
1669 /**
1670 * i9xx_disable_pll - disable a PLL
1671 * @dev_priv: i915 private structure
1672 * @pipe: pipe PLL to disable
1673 *
1674 * Disable the PLL for @pipe, making sure the pipe is off first.
1675 *
1676 * Note! This is for pre-ILK only.
1677 */
1678 static void i9xx_disable_pll(struct intel_crtc *crtc)
1679 {
1680 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1681 enum pipe pipe = crtc->pipe;
1682
1683 /* Disable DVO 2x clock on both PLLs if necessary */
1684 if (IS_I830(dev_priv) &&
1685 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1686 !intel_num_dvo_pipes(dev_priv)) {
1687 I915_WRITE(DPLL(PIPE_B),
1688 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1689 I915_WRITE(DPLL(PIPE_A),
1690 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1691 }
1692
1693 /* Don't disable pipe or pipe PLLs if needed */
1694 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1695 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1696 return;
1697
1698 /* Make sure the pipe isn't still relying on us */
1699 assert_pipe_disabled(dev_priv, pipe);
1700
1701 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1702 POSTING_READ(DPLL(pipe));
1703 }
1704
1705 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1706 {
1707 u32 val;
1708
1709 /* Make sure the pipe isn't still relying on us */
1710 assert_pipe_disabled(dev_priv, pipe);
1711
1712 val = DPLL_INTEGRATED_REF_CLK_VLV |
1713 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1714 if (pipe != PIPE_A)
1715 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1716
1717 I915_WRITE(DPLL(pipe), val);
1718 POSTING_READ(DPLL(pipe));
1719 }
1720
1721 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1722 {
1723 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1724 u32 val;
1725
1726 /* Make sure the pipe isn't still relying on us */
1727 assert_pipe_disabled(dev_priv, pipe);
1728
1729 val = DPLL_SSC_REF_CLK_CHV |
1730 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1731 if (pipe != PIPE_A)
1732 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1733
1734 I915_WRITE(DPLL(pipe), val);
1735 POSTING_READ(DPLL(pipe));
1736
1737 mutex_lock(&dev_priv->sb_lock);
1738
1739 /* Disable 10bit clock to display controller */
1740 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1741 val &= ~DPIO_DCLKP_EN;
1742 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1743
1744 mutex_unlock(&dev_priv->sb_lock);
1745 }
1746
1747 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1748 struct intel_digital_port *dport,
1749 unsigned int expected_mask)
1750 {
1751 u32 port_mask;
1752 i915_reg_t dpll_reg;
1753
1754 switch (dport->port) {
1755 case PORT_B:
1756 port_mask = DPLL_PORTB_READY_MASK;
1757 dpll_reg = DPLL(0);
1758 break;
1759 case PORT_C:
1760 port_mask = DPLL_PORTC_READY_MASK;
1761 dpll_reg = DPLL(0);
1762 expected_mask <<= 4;
1763 break;
1764 case PORT_D:
1765 port_mask = DPLL_PORTD_READY_MASK;
1766 dpll_reg = DPIO_PHY_STATUS;
1767 break;
1768 default:
1769 BUG();
1770 }
1771
1772 if (intel_wait_for_register(dev_priv,
1773 dpll_reg, port_mask, expected_mask,
1774 1000))
1775 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1776 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1777 }
1778
1779 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1780 enum pipe pipe)
1781 {
1782 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1783 pipe);
1784 i915_reg_t reg;
1785 uint32_t val, pipeconf_val;
1786
1787 /* Make sure PCH DPLL is enabled */
1788 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1789
1790 /* FDI must be feeding us bits for PCH ports */
1791 assert_fdi_tx_enabled(dev_priv, pipe);
1792 assert_fdi_rx_enabled(dev_priv, pipe);
1793
1794 if (HAS_PCH_CPT(dev_priv)) {
1795 /* Workaround: Set the timing override bit before enabling the
1796 * pch transcoder. */
1797 reg = TRANS_CHICKEN2(pipe);
1798 val = I915_READ(reg);
1799 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1800 I915_WRITE(reg, val);
1801 }
1802
1803 reg = PCH_TRANSCONF(pipe);
1804 val = I915_READ(reg);
1805 pipeconf_val = I915_READ(PIPECONF(pipe));
1806
1807 if (HAS_PCH_IBX(dev_priv)) {
1808 /*
1809 * Make the BPC in transcoder be consistent with
1810 * that in pipeconf reg. For HDMI we must use 8bpc
1811 * here for both 8bpc and 12bpc.
1812 */
1813 val &= ~PIPECONF_BPC_MASK;
1814 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1815 val |= PIPECONF_8BPC;
1816 else
1817 val |= pipeconf_val & PIPECONF_BPC_MASK;
1818 }
1819
1820 val &= ~TRANS_INTERLACE_MASK;
1821 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1822 if (HAS_PCH_IBX(dev_priv) &&
1823 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1824 val |= TRANS_LEGACY_INTERLACED_ILK;
1825 else
1826 val |= TRANS_INTERLACED;
1827 else
1828 val |= TRANS_PROGRESSIVE;
1829
1830 I915_WRITE(reg, val | TRANS_ENABLE);
1831 if (intel_wait_for_register(dev_priv,
1832 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1833 100))
1834 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1835 }
1836
1837 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1838 enum transcoder cpu_transcoder)
1839 {
1840 u32 val, pipeconf_val;
1841
1842 /* FDI must be feeding us bits for PCH ports */
1843 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1844 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1845
1846 /* Workaround: set timing override bit. */
1847 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1848 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1849 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1850
1851 val = TRANS_ENABLE;
1852 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1853
1854 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1855 PIPECONF_INTERLACED_ILK)
1856 val |= TRANS_INTERLACED;
1857 else
1858 val |= TRANS_PROGRESSIVE;
1859
1860 I915_WRITE(LPT_TRANSCONF, val);
1861 if (intel_wait_for_register(dev_priv,
1862 LPT_TRANSCONF,
1863 TRANS_STATE_ENABLE,
1864 TRANS_STATE_ENABLE,
1865 100))
1866 DRM_ERROR("Failed to enable PCH transcoder\n");
1867 }
1868
1869 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1870 enum pipe pipe)
1871 {
1872 i915_reg_t reg;
1873 uint32_t val;
1874
1875 /* FDI relies on the transcoder */
1876 assert_fdi_tx_disabled(dev_priv, pipe);
1877 assert_fdi_rx_disabled(dev_priv, pipe);
1878
1879 /* Ports must be off as well */
1880 assert_pch_ports_disabled(dev_priv, pipe);
1881
1882 reg = PCH_TRANSCONF(pipe);
1883 val = I915_READ(reg);
1884 val &= ~TRANS_ENABLE;
1885 I915_WRITE(reg, val);
1886 /* wait for PCH transcoder off, transcoder state */
1887 if (intel_wait_for_register(dev_priv,
1888 reg, TRANS_STATE_ENABLE, 0,
1889 50))
1890 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1891
1892 if (HAS_PCH_CPT(dev_priv)) {
1893 /* Workaround: Clear the timing override chicken bit again. */
1894 reg = TRANS_CHICKEN2(pipe);
1895 val = I915_READ(reg);
1896 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1897 I915_WRITE(reg, val);
1898 }
1899 }
1900
1901 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1902 {
1903 u32 val;
1904
1905 val = I915_READ(LPT_TRANSCONF);
1906 val &= ~TRANS_ENABLE;
1907 I915_WRITE(LPT_TRANSCONF, val);
1908 /* wait for PCH transcoder off, transcoder state */
1909 if (intel_wait_for_register(dev_priv,
1910 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1911 50))
1912 DRM_ERROR("Failed to disable PCH transcoder\n");
1913
1914 /* Workaround: clear timing override bit. */
1915 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1916 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1917 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1918 }
1919
1920 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1921 {
1922 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1923
1924 WARN_ON(!crtc->config->has_pch_encoder);
1925
1926 if (HAS_PCH_LPT(dev_priv))
1927 return TRANSCODER_A;
1928 else
1929 return (enum transcoder) crtc->pipe;
1930 }
1931
1932 /**
1933 * intel_enable_pipe - enable a pipe, asserting requirements
1934 * @crtc: crtc responsible for the pipe
1935 *
1936 * Enable @crtc's pipe, making sure that various hardware specific requirements
1937 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1938 */
1939 static void intel_enable_pipe(struct intel_crtc *crtc)
1940 {
1941 struct drm_device *dev = crtc->base.dev;
1942 struct drm_i915_private *dev_priv = to_i915(dev);
1943 enum pipe pipe = crtc->pipe;
1944 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1945 i915_reg_t reg;
1946 u32 val;
1947
1948 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1949
1950 assert_planes_disabled(dev_priv, pipe);
1951 assert_cursor_disabled(dev_priv, pipe);
1952 assert_sprites_disabled(dev_priv, pipe);
1953
1954 /*
1955 * A pipe without a PLL won't actually be able to drive bits from
1956 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1957 * need the check.
1958 */
1959 if (HAS_GMCH_DISPLAY(dev_priv)) {
1960 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1961 assert_dsi_pll_enabled(dev_priv);
1962 else
1963 assert_pll_enabled(dev_priv, pipe);
1964 } else {
1965 if (crtc->config->has_pch_encoder) {
1966 /* if driving the PCH, we need FDI enabled */
1967 assert_fdi_rx_pll_enabled(dev_priv,
1968 (enum pipe) intel_crtc_pch_transcoder(crtc));
1969 assert_fdi_tx_pll_enabled(dev_priv,
1970 (enum pipe) cpu_transcoder);
1971 }
1972 /* FIXME: assert CPU port conditions for SNB+ */
1973 }
1974
1975 reg = PIPECONF(cpu_transcoder);
1976 val = I915_READ(reg);
1977 if (val & PIPECONF_ENABLE) {
1978 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1979 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1980 return;
1981 }
1982
1983 I915_WRITE(reg, val | PIPECONF_ENABLE);
1984 POSTING_READ(reg);
1985
1986 /*
1987 * Until the pipe starts DSL will read as 0, which would cause
1988 * an apparent vblank timestamp jump, which messes up also the
1989 * frame count when it's derived from the timestamps. So let's
1990 * wait for the pipe to start properly before we call
1991 * drm_crtc_vblank_on()
1992 */
1993 if (dev->max_vblank_count == 0 &&
1994 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1995 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1996 }
1997
1998 /**
1999 * intel_disable_pipe - disable a pipe, asserting requirements
2000 * @crtc: crtc whose pipes is to be disabled
2001 *
2002 * Disable the pipe of @crtc, making sure that various hardware
2003 * specific requirements are met, if applicable, e.g. plane
2004 * disabled, panel fitter off, etc.
2005 *
2006 * Will wait until the pipe has shut down before returning.
2007 */
2008 static void intel_disable_pipe(struct intel_crtc *crtc)
2009 {
2010 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2011 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2012 enum pipe pipe = crtc->pipe;
2013 i915_reg_t reg;
2014 u32 val;
2015
2016 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2017
2018 /*
2019 * Make sure planes won't keep trying to pump pixels to us,
2020 * or we might hang the display.
2021 */
2022 assert_planes_disabled(dev_priv, pipe);
2023 assert_cursor_disabled(dev_priv, pipe);
2024 assert_sprites_disabled(dev_priv, pipe);
2025
2026 reg = PIPECONF(cpu_transcoder);
2027 val = I915_READ(reg);
2028 if ((val & PIPECONF_ENABLE) == 0)
2029 return;
2030
2031 /*
2032 * Double wide has implications for planes
2033 * so best keep it disabled when not needed.
2034 */
2035 if (crtc->config->double_wide)
2036 val &= ~PIPECONF_DOUBLE_WIDE;
2037
2038 /* Don't disable pipe or pipe PLLs if needed */
2039 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2040 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2041 val &= ~PIPECONF_ENABLE;
2042
2043 I915_WRITE(reg, val);
2044 if ((val & PIPECONF_ENABLE) == 0)
2045 intel_wait_for_pipe_off(crtc);
2046 }
2047
2048 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2049 {
2050 return IS_GEN2(dev_priv) ? 2048 : 4096;
2051 }
2052
2053 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2054 uint64_t fb_modifier, unsigned int cpp)
2055 {
2056 switch (fb_modifier) {
2057 case DRM_FORMAT_MOD_NONE:
2058 return cpp;
2059 case I915_FORMAT_MOD_X_TILED:
2060 if (IS_GEN2(dev_priv))
2061 return 128;
2062 else
2063 return 512;
2064 case I915_FORMAT_MOD_Y_TILED:
2065 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2066 return 128;
2067 else
2068 return 512;
2069 case I915_FORMAT_MOD_Yf_TILED:
2070 switch (cpp) {
2071 case 1:
2072 return 64;
2073 case 2:
2074 case 4:
2075 return 128;
2076 case 8:
2077 case 16:
2078 return 256;
2079 default:
2080 MISSING_CASE(cpp);
2081 return cpp;
2082 }
2083 break;
2084 default:
2085 MISSING_CASE(fb_modifier);
2086 return cpp;
2087 }
2088 }
2089
2090 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2091 uint64_t fb_modifier, unsigned int cpp)
2092 {
2093 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2094 return 1;
2095 else
2096 return intel_tile_size(dev_priv) /
2097 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2098 }
2099
2100 /* Return the tile dimensions in pixel units */
2101 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2102 unsigned int *tile_width,
2103 unsigned int *tile_height,
2104 uint64_t fb_modifier,
2105 unsigned int cpp)
2106 {
2107 unsigned int tile_width_bytes =
2108 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2109
2110 *tile_width = tile_width_bytes / cpp;
2111 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2112 }
2113
2114 unsigned int
2115 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2116 uint32_t pixel_format, uint64_t fb_modifier)
2117 {
2118 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2119 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2120
2121 return ALIGN(height, tile_height);
2122 }
2123
2124 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2125 {
2126 unsigned int size = 0;
2127 int i;
2128
2129 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2130 size += rot_info->plane[i].width * rot_info->plane[i].height;
2131
2132 return size;
2133 }
2134
2135 static void
2136 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2137 const struct drm_framebuffer *fb,
2138 unsigned int rotation)
2139 {
2140 if (drm_rotation_90_or_270(rotation)) {
2141 *view = i915_ggtt_view_rotated;
2142 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2143 } else {
2144 *view = i915_ggtt_view_normal;
2145 }
2146 }
2147
2148 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2149 {
2150 if (INTEL_INFO(dev_priv)->gen >= 9)
2151 return 256 * 1024;
2152 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2153 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2154 return 128 * 1024;
2155 else if (INTEL_INFO(dev_priv)->gen >= 4)
2156 return 4 * 1024;
2157 else
2158 return 0;
2159 }
2160
2161 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2162 uint64_t fb_modifier)
2163 {
2164 switch (fb_modifier) {
2165 case DRM_FORMAT_MOD_NONE:
2166 return intel_linear_alignment(dev_priv);
2167 case I915_FORMAT_MOD_X_TILED:
2168 if (INTEL_INFO(dev_priv)->gen >= 9)
2169 return 256 * 1024;
2170 return 0;
2171 case I915_FORMAT_MOD_Y_TILED:
2172 case I915_FORMAT_MOD_Yf_TILED:
2173 return 1 * 1024 * 1024;
2174 default:
2175 MISSING_CASE(fb_modifier);
2176 return 0;
2177 }
2178 }
2179
2180 struct i915_vma *
2181 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2182 {
2183 struct drm_device *dev = fb->dev;
2184 struct drm_i915_private *dev_priv = to_i915(dev);
2185 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2186 struct i915_ggtt_view view;
2187 struct i915_vma *vma;
2188 u32 alignment;
2189
2190 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2191
2192 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2193
2194 intel_fill_fb_ggtt_view(&view, fb, rotation);
2195
2196 /* Note that the w/a also requires 64 PTE of padding following the
2197 * bo. We currently fill all unused PTE with the shadow page and so
2198 * we should always have valid PTE following the scanout preventing
2199 * the VT-d warning.
2200 */
2201 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2202 alignment = 256 * 1024;
2203
2204 /*
2205 * Global gtt pte registers are special registers which actually forward
2206 * writes to a chunk of system memory. Which means that there is no risk
2207 * that the register values disappear as soon as we call
2208 * intel_runtime_pm_put(), so it is correct to wrap only the
2209 * pin/unpin/fence and not more.
2210 */
2211 intel_runtime_pm_get(dev_priv);
2212
2213 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2214 if (IS_ERR(vma))
2215 goto err;
2216
2217 if (i915_vma_is_map_and_fenceable(vma)) {
2218 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2219 * fence, whereas 965+ only requires a fence if using
2220 * framebuffer compression. For simplicity, we always, when
2221 * possible, install a fence as the cost is not that onerous.
2222 *
2223 * If we fail to fence the tiled scanout, then either the
2224 * modeset will reject the change (which is highly unlikely as
2225 * the affected systems, all but one, do not have unmappable
2226 * space) or we will not be able to enable full powersaving
2227 * techniques (also likely not to apply due to various limits
2228 * FBC and the like impose on the size of the buffer, which
2229 * presumably we violated anyway with this unmappable buffer).
2230 * Anyway, it is presumably better to stumble onwards with
2231 * something and try to run the system in a "less than optimal"
2232 * mode that matches the user configuration.
2233 */
2234 if (i915_vma_get_fence(vma) == 0)
2235 i915_vma_pin_fence(vma);
2236 }
2237
2238 err:
2239 intel_runtime_pm_put(dev_priv);
2240 return vma;
2241 }
2242
2243 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2244 {
2245 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2246 struct i915_ggtt_view view;
2247 struct i915_vma *vma;
2248
2249 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2250
2251 intel_fill_fb_ggtt_view(&view, fb, rotation);
2252 vma = i915_gem_object_to_ggtt(obj, &view);
2253
2254 i915_vma_unpin_fence(vma);
2255 i915_gem_object_unpin_from_display_plane(vma);
2256 }
2257
2258 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2259 unsigned int rotation)
2260 {
2261 if (drm_rotation_90_or_270(rotation))
2262 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2263 else
2264 return fb->pitches[plane];
2265 }
2266
2267 /*
2268 * Convert the x/y offsets into a linear offset.
2269 * Only valid with 0/180 degree rotation, which is fine since linear
2270 * offset is only used with linear buffers on pre-hsw and tiled buffers
2271 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2272 */
2273 u32 intel_fb_xy_to_linear(int x, int y,
2274 const struct intel_plane_state *state,
2275 int plane)
2276 {
2277 const struct drm_framebuffer *fb = state->base.fb;
2278 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2279 unsigned int pitch = fb->pitches[plane];
2280
2281 return y * pitch + x * cpp;
2282 }
2283
2284 /*
2285 * Add the x/y offsets derived from fb->offsets[] to the user
2286 * specified plane src x/y offsets. The resulting x/y offsets
2287 * specify the start of scanout from the beginning of the gtt mapping.
2288 */
2289 void intel_add_fb_offsets(int *x, int *y,
2290 const struct intel_plane_state *state,
2291 int plane)
2292
2293 {
2294 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2295 unsigned int rotation = state->base.rotation;
2296
2297 if (drm_rotation_90_or_270(rotation)) {
2298 *x += intel_fb->rotated[plane].x;
2299 *y += intel_fb->rotated[plane].y;
2300 } else {
2301 *x += intel_fb->normal[plane].x;
2302 *y += intel_fb->normal[plane].y;
2303 }
2304 }
2305
2306 /*
2307 * Input tile dimensions and pitch must already be
2308 * rotated to match x and y, and in pixel units.
2309 */
2310 static u32 _intel_adjust_tile_offset(int *x, int *y,
2311 unsigned int tile_width,
2312 unsigned int tile_height,
2313 unsigned int tile_size,
2314 unsigned int pitch_tiles,
2315 u32 old_offset,
2316 u32 new_offset)
2317 {
2318 unsigned int pitch_pixels = pitch_tiles * tile_width;
2319 unsigned int tiles;
2320
2321 WARN_ON(old_offset & (tile_size - 1));
2322 WARN_ON(new_offset & (tile_size - 1));
2323 WARN_ON(new_offset > old_offset);
2324
2325 tiles = (old_offset - new_offset) / tile_size;
2326
2327 *y += tiles / pitch_tiles * tile_height;
2328 *x += tiles % pitch_tiles * tile_width;
2329
2330 /* minimize x in case it got needlessly big */
2331 *y += *x / pitch_pixels * tile_height;
2332 *x %= pitch_pixels;
2333
2334 return new_offset;
2335 }
2336
2337 /*
2338 * Adjust the tile offset by moving the difference into
2339 * the x/y offsets.
2340 */
2341 static u32 intel_adjust_tile_offset(int *x, int *y,
2342 const struct intel_plane_state *state, int plane,
2343 u32 old_offset, u32 new_offset)
2344 {
2345 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2346 const struct drm_framebuffer *fb = state->base.fb;
2347 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2348 unsigned int rotation = state->base.rotation;
2349 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2350
2351 WARN_ON(new_offset > old_offset);
2352
2353 if (fb->modifier[plane] != DRM_FORMAT_MOD_NONE) {
2354 unsigned int tile_size, tile_width, tile_height;
2355 unsigned int pitch_tiles;
2356
2357 tile_size = intel_tile_size(dev_priv);
2358 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2359 fb->modifier[plane], cpp);
2360
2361 if (drm_rotation_90_or_270(rotation)) {
2362 pitch_tiles = pitch / tile_height;
2363 swap(tile_width, tile_height);
2364 } else {
2365 pitch_tiles = pitch / (tile_width * cpp);
2366 }
2367
2368 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2369 tile_size, pitch_tiles,
2370 old_offset, new_offset);
2371 } else {
2372 old_offset += *y * pitch + *x * cpp;
2373
2374 *y = (old_offset - new_offset) / pitch;
2375 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2376 }
2377
2378 return new_offset;
2379 }
2380
2381 /*
2382 * Computes the linear offset to the base tile and adjusts
2383 * x, y. bytes per pixel is assumed to be a power-of-two.
2384 *
2385 * In the 90/270 rotated case, x and y are assumed
2386 * to be already rotated to match the rotated GTT view, and
2387 * pitch is the tile_height aligned framebuffer height.
2388 *
2389 * This function is used when computing the derived information
2390 * under intel_framebuffer, so using any of that information
2391 * here is not allowed. Anything under drm_framebuffer can be
2392 * used. This is why the user has to pass in the pitch since it
2393 * is specified in the rotated orientation.
2394 */
2395 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2396 int *x, int *y,
2397 const struct drm_framebuffer *fb, int plane,
2398 unsigned int pitch,
2399 unsigned int rotation,
2400 u32 alignment)
2401 {
2402 uint64_t fb_modifier = fb->modifier[plane];
2403 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2404 u32 offset, offset_aligned;
2405
2406 if (alignment)
2407 alignment--;
2408
2409 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2410 unsigned int tile_size, tile_width, tile_height;
2411 unsigned int tile_rows, tiles, pitch_tiles;
2412
2413 tile_size = intel_tile_size(dev_priv);
2414 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2415 fb_modifier, cpp);
2416
2417 if (drm_rotation_90_or_270(rotation)) {
2418 pitch_tiles = pitch / tile_height;
2419 swap(tile_width, tile_height);
2420 } else {
2421 pitch_tiles = pitch / (tile_width * cpp);
2422 }
2423
2424 tile_rows = *y / tile_height;
2425 *y %= tile_height;
2426
2427 tiles = *x / tile_width;
2428 *x %= tile_width;
2429
2430 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2431 offset_aligned = offset & ~alignment;
2432
2433 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2434 tile_size, pitch_tiles,
2435 offset, offset_aligned);
2436 } else {
2437 offset = *y * pitch + *x * cpp;
2438 offset_aligned = offset & ~alignment;
2439
2440 *y = (offset & alignment) / pitch;
2441 *x = ((offset & alignment) - *y * pitch) / cpp;
2442 }
2443
2444 return offset_aligned;
2445 }
2446
2447 u32 intel_compute_tile_offset(int *x, int *y,
2448 const struct intel_plane_state *state,
2449 int plane)
2450 {
2451 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2452 const struct drm_framebuffer *fb = state->base.fb;
2453 unsigned int rotation = state->base.rotation;
2454 int pitch = intel_fb_pitch(fb, plane, rotation);
2455 u32 alignment;
2456
2457 /* AUX_DIST needs only 4K alignment */
2458 if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1)
2459 alignment = 4096;
2460 else
2461 alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]);
2462
2463 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2464 rotation, alignment);
2465 }
2466
2467 /* Convert the fb->offset[] linear offset into x/y offsets */
2468 static void intel_fb_offset_to_xy(int *x, int *y,
2469 const struct drm_framebuffer *fb, int plane)
2470 {
2471 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2472 unsigned int pitch = fb->pitches[plane];
2473 u32 linear_offset = fb->offsets[plane];
2474
2475 *y = linear_offset / pitch;
2476 *x = linear_offset % pitch / cpp;
2477 }
2478
2479 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2480 {
2481 switch (fb_modifier) {
2482 case I915_FORMAT_MOD_X_TILED:
2483 return I915_TILING_X;
2484 case I915_FORMAT_MOD_Y_TILED:
2485 return I915_TILING_Y;
2486 default:
2487 return I915_TILING_NONE;
2488 }
2489 }
2490
2491 static int
2492 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2493 struct drm_framebuffer *fb)
2494 {
2495 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2496 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2497 u32 gtt_offset_rotated = 0;
2498 unsigned int max_size = 0;
2499 uint32_t format = fb->pixel_format;
2500 int i, num_planes = drm_format_num_planes(format);
2501 unsigned int tile_size = intel_tile_size(dev_priv);
2502
2503 for (i = 0; i < num_planes; i++) {
2504 unsigned int width, height;
2505 unsigned int cpp, size;
2506 u32 offset;
2507 int x, y;
2508
2509 cpp = drm_format_plane_cpp(format, i);
2510 width = drm_format_plane_width(fb->width, format, i);
2511 height = drm_format_plane_height(fb->height, format, i);
2512
2513 intel_fb_offset_to_xy(&x, &y, fb, i);
2514
2515 /*
2516 * The fence (if used) is aligned to the start of the object
2517 * so having the framebuffer wrap around across the edge of the
2518 * fenced region doesn't really work. We have no API to configure
2519 * the fence start offset within the object (nor could we probably
2520 * on gen2/3). So it's just easier if we just require that the
2521 * fb layout agrees with the fence layout. We already check that the
2522 * fb stride matches the fence stride elsewhere.
2523 */
2524 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2525 (x + width) * cpp > fb->pitches[i]) {
2526 DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2527 i, fb->offsets[i]);
2528 return -EINVAL;
2529 }
2530
2531 /*
2532 * First pixel of the framebuffer from
2533 * the start of the normal gtt mapping.
2534 */
2535 intel_fb->normal[i].x = x;
2536 intel_fb->normal[i].y = y;
2537
2538 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2539 fb, 0, fb->pitches[i],
2540 DRM_ROTATE_0, tile_size);
2541 offset /= tile_size;
2542
2543 if (fb->modifier[i] != DRM_FORMAT_MOD_NONE) {
2544 unsigned int tile_width, tile_height;
2545 unsigned int pitch_tiles;
2546 struct drm_rect r;
2547
2548 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2549 fb->modifier[i], cpp);
2550
2551 rot_info->plane[i].offset = offset;
2552 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2553 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2554 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2555
2556 intel_fb->rotated[i].pitch =
2557 rot_info->plane[i].height * tile_height;
2558
2559 /* how many tiles does this plane need */
2560 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2561 /*
2562 * If the plane isn't horizontally tile aligned,
2563 * we need one more tile.
2564 */
2565 if (x != 0)
2566 size++;
2567
2568 /* rotate the x/y offsets to match the GTT view */
2569 r.x1 = x;
2570 r.y1 = y;
2571 r.x2 = x + width;
2572 r.y2 = y + height;
2573 drm_rect_rotate(&r,
2574 rot_info->plane[i].width * tile_width,
2575 rot_info->plane[i].height * tile_height,
2576 DRM_ROTATE_270);
2577 x = r.x1;
2578 y = r.y1;
2579
2580 /* rotate the tile dimensions to match the GTT view */
2581 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2582 swap(tile_width, tile_height);
2583
2584 /*
2585 * We only keep the x/y offsets, so push all of the
2586 * gtt offset into the x/y offsets.
2587 */
2588 _intel_adjust_tile_offset(&x, &y, tile_size,
2589 tile_width, tile_height, pitch_tiles,
2590 gtt_offset_rotated * tile_size, 0);
2591
2592 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2593
2594 /*
2595 * First pixel of the framebuffer from
2596 * the start of the rotated gtt mapping.
2597 */
2598 intel_fb->rotated[i].x = x;
2599 intel_fb->rotated[i].y = y;
2600 } else {
2601 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2602 x * cpp, tile_size);
2603 }
2604
2605 /* how many tiles in total needed in the bo */
2606 max_size = max(max_size, offset + size);
2607 }
2608
2609 if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2610 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2611 max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2612 return -EINVAL;
2613 }
2614
2615 return 0;
2616 }
2617
2618 static int i9xx_format_to_fourcc(int format)
2619 {
2620 switch (format) {
2621 case DISPPLANE_8BPP:
2622 return DRM_FORMAT_C8;
2623 case DISPPLANE_BGRX555:
2624 return DRM_FORMAT_XRGB1555;
2625 case DISPPLANE_BGRX565:
2626 return DRM_FORMAT_RGB565;
2627 default:
2628 case DISPPLANE_BGRX888:
2629 return DRM_FORMAT_XRGB8888;
2630 case DISPPLANE_RGBX888:
2631 return DRM_FORMAT_XBGR8888;
2632 case DISPPLANE_BGRX101010:
2633 return DRM_FORMAT_XRGB2101010;
2634 case DISPPLANE_RGBX101010:
2635 return DRM_FORMAT_XBGR2101010;
2636 }
2637 }
2638
2639 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2640 {
2641 switch (format) {
2642 case PLANE_CTL_FORMAT_RGB_565:
2643 return DRM_FORMAT_RGB565;
2644 default:
2645 case PLANE_CTL_FORMAT_XRGB_8888:
2646 if (rgb_order) {
2647 if (alpha)
2648 return DRM_FORMAT_ABGR8888;
2649 else
2650 return DRM_FORMAT_XBGR8888;
2651 } else {
2652 if (alpha)
2653 return DRM_FORMAT_ARGB8888;
2654 else
2655 return DRM_FORMAT_XRGB8888;
2656 }
2657 case PLANE_CTL_FORMAT_XRGB_2101010:
2658 if (rgb_order)
2659 return DRM_FORMAT_XBGR2101010;
2660 else
2661 return DRM_FORMAT_XRGB2101010;
2662 }
2663 }
2664
2665 static bool
2666 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2667 struct intel_initial_plane_config *plane_config)
2668 {
2669 struct drm_device *dev = crtc->base.dev;
2670 struct drm_i915_private *dev_priv = to_i915(dev);
2671 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2672 struct drm_i915_gem_object *obj = NULL;
2673 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2674 struct drm_framebuffer *fb = &plane_config->fb->base;
2675 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2676 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2677 PAGE_SIZE);
2678
2679 size_aligned -= base_aligned;
2680
2681 if (plane_config->size == 0)
2682 return false;
2683
2684 /* If the FB is too big, just don't use it since fbdev is not very
2685 * important and we should probably use that space with FBC or other
2686 * features. */
2687 if (size_aligned * 2 > ggtt->stolen_usable_size)
2688 return false;
2689
2690 mutex_lock(&dev->struct_mutex);
2691
2692 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2693 base_aligned,
2694 base_aligned,
2695 size_aligned);
2696 if (!obj) {
2697 mutex_unlock(&dev->struct_mutex);
2698 return false;
2699 }
2700
2701 if (plane_config->tiling == I915_TILING_X)
2702 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2703
2704 mode_cmd.pixel_format = fb->pixel_format;
2705 mode_cmd.width = fb->width;
2706 mode_cmd.height = fb->height;
2707 mode_cmd.pitches[0] = fb->pitches[0];
2708 mode_cmd.modifier[0] = fb->modifier[0];
2709 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2710
2711 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2712 &mode_cmd, obj)) {
2713 DRM_DEBUG_KMS("intel fb init failed\n");
2714 goto out_unref_obj;
2715 }
2716
2717 mutex_unlock(&dev->struct_mutex);
2718
2719 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2720 return true;
2721
2722 out_unref_obj:
2723 i915_gem_object_put(obj);
2724 mutex_unlock(&dev->struct_mutex);
2725 return false;
2726 }
2727
2728 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2729 static void
2730 update_state_fb(struct drm_plane *plane)
2731 {
2732 if (plane->fb == plane->state->fb)
2733 return;
2734
2735 if (plane->state->fb)
2736 drm_framebuffer_unreference(plane->state->fb);
2737 plane->state->fb = plane->fb;
2738 if (plane->state->fb)
2739 drm_framebuffer_reference(plane->state->fb);
2740 }
2741
2742 static void
2743 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2744 struct intel_initial_plane_config *plane_config)
2745 {
2746 struct drm_device *dev = intel_crtc->base.dev;
2747 struct drm_i915_private *dev_priv = to_i915(dev);
2748 struct drm_crtc *c;
2749 struct intel_crtc *i;
2750 struct drm_i915_gem_object *obj;
2751 struct drm_plane *primary = intel_crtc->base.primary;
2752 struct drm_plane_state *plane_state = primary->state;
2753 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2754 struct intel_plane *intel_plane = to_intel_plane(primary);
2755 struct intel_plane_state *intel_state =
2756 to_intel_plane_state(plane_state);
2757 struct drm_framebuffer *fb;
2758
2759 if (!plane_config->fb)
2760 return;
2761
2762 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2763 fb = &plane_config->fb->base;
2764 goto valid_fb;
2765 }
2766
2767 kfree(plane_config->fb);
2768
2769 /*
2770 * Failed to alloc the obj, check to see if we should share
2771 * an fb with another CRTC instead
2772 */
2773 for_each_crtc(dev, c) {
2774 i = to_intel_crtc(c);
2775
2776 if (c == &intel_crtc->base)
2777 continue;
2778
2779 if (!i->active)
2780 continue;
2781
2782 fb = c->primary->fb;
2783 if (!fb)
2784 continue;
2785
2786 obj = intel_fb_obj(fb);
2787 if (i915_gem_object_ggtt_offset(obj, NULL) == plane_config->base) {
2788 drm_framebuffer_reference(fb);
2789 goto valid_fb;
2790 }
2791 }
2792
2793 /*
2794 * We've failed to reconstruct the BIOS FB. Current display state
2795 * indicates that the primary plane is visible, but has a NULL FB,
2796 * which will lead to problems later if we don't fix it up. The
2797 * simplest solution is to just disable the primary plane now and
2798 * pretend the BIOS never had it enabled.
2799 */
2800 to_intel_plane_state(plane_state)->base.visible = false;
2801 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2802 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2803 intel_plane->disable_plane(primary, &intel_crtc->base);
2804
2805 return;
2806
2807 valid_fb:
2808 plane_state->src_x = 0;
2809 plane_state->src_y = 0;
2810 plane_state->src_w = fb->width << 16;
2811 plane_state->src_h = fb->height << 16;
2812
2813 plane_state->crtc_x = 0;
2814 plane_state->crtc_y = 0;
2815 plane_state->crtc_w = fb->width;
2816 plane_state->crtc_h = fb->height;
2817
2818 intel_state->base.src = drm_plane_state_src(plane_state);
2819 intel_state->base.dst = drm_plane_state_dest(plane_state);
2820
2821 obj = intel_fb_obj(fb);
2822 if (i915_gem_object_is_tiled(obj))
2823 dev_priv->preserve_bios_swizzle = true;
2824
2825 drm_framebuffer_reference(fb);
2826 primary->fb = primary->state->fb = fb;
2827 primary->crtc = primary->state->crtc = &intel_crtc->base;
2828 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2829 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2830 &obj->frontbuffer_bits);
2831 }
2832
2833 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2834 unsigned int rotation)
2835 {
2836 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2837
2838 switch (fb->modifier[plane]) {
2839 case DRM_FORMAT_MOD_NONE:
2840 case I915_FORMAT_MOD_X_TILED:
2841 switch (cpp) {
2842 case 8:
2843 return 4096;
2844 case 4:
2845 case 2:
2846 case 1:
2847 return 8192;
2848 default:
2849 MISSING_CASE(cpp);
2850 break;
2851 }
2852 break;
2853 case I915_FORMAT_MOD_Y_TILED:
2854 case I915_FORMAT_MOD_Yf_TILED:
2855 switch (cpp) {
2856 case 8:
2857 return 2048;
2858 case 4:
2859 return 4096;
2860 case 2:
2861 case 1:
2862 return 8192;
2863 default:
2864 MISSING_CASE(cpp);
2865 break;
2866 }
2867 break;
2868 default:
2869 MISSING_CASE(fb->modifier[plane]);
2870 }
2871
2872 return 2048;
2873 }
2874
2875 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2876 {
2877 const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2878 const struct drm_framebuffer *fb = plane_state->base.fb;
2879 unsigned int rotation = plane_state->base.rotation;
2880 int x = plane_state->base.src.x1 >> 16;
2881 int y = plane_state->base.src.y1 >> 16;
2882 int w = drm_rect_width(&plane_state->base.src) >> 16;
2883 int h = drm_rect_height(&plane_state->base.src) >> 16;
2884 int max_width = skl_max_plane_width(fb, 0, rotation);
2885 int max_height = 4096;
2886 u32 alignment, offset, aux_offset = plane_state->aux.offset;
2887
2888 if (w > max_width || h > max_height) {
2889 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2890 w, h, max_width, max_height);
2891 return -EINVAL;
2892 }
2893
2894 intel_add_fb_offsets(&x, &y, plane_state, 0);
2895 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2896
2897 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2898
2899 /*
2900 * AUX surface offset is specified as the distance from the
2901 * main surface offset, and it must be non-negative. Make
2902 * sure that is what we will get.
2903 */
2904 if (offset > aux_offset)
2905 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2906 offset, aux_offset & ~(alignment - 1));
2907
2908 /*
2909 * When using an X-tiled surface, the plane blows up
2910 * if the x offset + width exceed the stride.
2911 *
2912 * TODO: linear and Y-tiled seem fine, Yf untested,
2913 */
2914 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) {
2915 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2916
2917 while ((x + w) * cpp > fb->pitches[0]) {
2918 if (offset == 0) {
2919 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2920 return -EINVAL;
2921 }
2922
2923 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2924 offset, offset - alignment);
2925 }
2926 }
2927
2928 plane_state->main.offset = offset;
2929 plane_state->main.x = x;
2930 plane_state->main.y = y;
2931
2932 return 0;
2933 }
2934
2935 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2936 {
2937 const struct drm_framebuffer *fb = plane_state->base.fb;
2938 unsigned int rotation = plane_state->base.rotation;
2939 int max_width = skl_max_plane_width(fb, 1, rotation);
2940 int max_height = 4096;
2941 int x = plane_state->base.src.x1 >> 17;
2942 int y = plane_state->base.src.y1 >> 17;
2943 int w = drm_rect_width(&plane_state->base.src) >> 17;
2944 int h = drm_rect_height(&plane_state->base.src) >> 17;
2945 u32 offset;
2946
2947 intel_add_fb_offsets(&x, &y, plane_state, 1);
2948 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2949
2950 /* FIXME not quite sure how/if these apply to the chroma plane */
2951 if (w > max_width || h > max_height) {
2952 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2953 w, h, max_width, max_height);
2954 return -EINVAL;
2955 }
2956
2957 plane_state->aux.offset = offset;
2958 plane_state->aux.x = x;
2959 plane_state->aux.y = y;
2960
2961 return 0;
2962 }
2963
2964 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2965 {
2966 const struct drm_framebuffer *fb = plane_state->base.fb;
2967 unsigned int rotation = plane_state->base.rotation;
2968 int ret;
2969
2970 /* Rotate src coordinates to match rotated GTT view */
2971 if (drm_rotation_90_or_270(rotation))
2972 drm_rect_rotate(&plane_state->base.src,
2973 fb->width << 16, fb->height << 16,
2974 DRM_ROTATE_270);
2975
2976 /*
2977 * Handle the AUX surface first since
2978 * the main surface setup depends on it.
2979 */
2980 if (fb->pixel_format == DRM_FORMAT_NV12) {
2981 ret = skl_check_nv12_aux_surface(plane_state);
2982 if (ret)
2983 return ret;
2984 } else {
2985 plane_state->aux.offset = ~0xfff;
2986 plane_state->aux.x = 0;
2987 plane_state->aux.y = 0;
2988 }
2989
2990 ret = skl_check_main_surface(plane_state);
2991 if (ret)
2992 return ret;
2993
2994 return 0;
2995 }
2996
2997 static void i9xx_update_primary_plane(struct drm_plane *primary,
2998 const struct intel_crtc_state *crtc_state,
2999 const struct intel_plane_state *plane_state)
3000 {
3001 struct drm_i915_private *dev_priv = to_i915(primary->dev);
3002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3003 struct drm_framebuffer *fb = plane_state->base.fb;
3004 int plane = intel_crtc->plane;
3005 u32 linear_offset;
3006 u32 dspcntr;
3007 i915_reg_t reg = DSPCNTR(plane);
3008 unsigned int rotation = plane_state->base.rotation;
3009 int x = plane_state->base.src.x1 >> 16;
3010 int y = plane_state->base.src.y1 >> 16;
3011
3012 dspcntr = DISPPLANE_GAMMA_ENABLE;
3013
3014 dspcntr |= DISPLAY_PLANE_ENABLE;
3015
3016 if (INTEL_GEN(dev_priv) < 4) {
3017 if (intel_crtc->pipe == PIPE_B)
3018 dspcntr |= DISPPLANE_SEL_PIPE_B;
3019
3020 /* pipesrc and dspsize control the size that is scaled from,
3021 * which should always be the user's requested size.
3022 */
3023 I915_WRITE(DSPSIZE(plane),
3024 ((crtc_state->pipe_src_h - 1) << 16) |
3025 (crtc_state->pipe_src_w - 1));
3026 I915_WRITE(DSPPOS(plane), 0);
3027 } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3028 I915_WRITE(PRIMSIZE(plane),
3029 ((crtc_state->pipe_src_h - 1) << 16) |
3030 (crtc_state->pipe_src_w - 1));
3031 I915_WRITE(PRIMPOS(plane), 0);
3032 I915_WRITE(PRIMCNSTALPHA(plane), 0);
3033 }
3034
3035 switch (fb->pixel_format) {
3036 case DRM_FORMAT_C8:
3037 dspcntr |= DISPPLANE_8BPP;
3038 break;
3039 case DRM_FORMAT_XRGB1555:
3040 dspcntr |= DISPPLANE_BGRX555;
3041 break;
3042 case DRM_FORMAT_RGB565:
3043 dspcntr |= DISPPLANE_BGRX565;
3044 break;
3045 case DRM_FORMAT_XRGB8888:
3046 dspcntr |= DISPPLANE_BGRX888;
3047 break;
3048 case DRM_FORMAT_XBGR8888:
3049 dspcntr |= DISPPLANE_RGBX888;
3050 break;
3051 case DRM_FORMAT_XRGB2101010:
3052 dspcntr |= DISPPLANE_BGRX101010;
3053 break;
3054 case DRM_FORMAT_XBGR2101010:
3055 dspcntr |= DISPPLANE_RGBX101010;
3056 break;
3057 default:
3058 BUG();
3059 }
3060
3061 if (INTEL_GEN(dev_priv) >= 4 &&
3062 fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3063 dspcntr |= DISPPLANE_TILED;
3064
3065 if (rotation & DRM_ROTATE_180)
3066 dspcntr |= DISPPLANE_ROTATE_180;
3067
3068 if (rotation & DRM_REFLECT_X)
3069 dspcntr |= DISPPLANE_MIRROR;
3070
3071 if (IS_G4X(dev_priv))
3072 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3073
3074 intel_add_fb_offsets(&x, &y, plane_state, 0);
3075
3076 if (INTEL_GEN(dev_priv) >= 4)
3077 intel_crtc->dspaddr_offset =
3078 intel_compute_tile_offset(&x, &y, plane_state, 0);
3079
3080 if (rotation & DRM_ROTATE_180) {
3081 x += crtc_state->pipe_src_w - 1;
3082 y += crtc_state->pipe_src_h - 1;
3083 } else if (rotation & DRM_REFLECT_X) {
3084 x += crtc_state->pipe_src_w - 1;
3085 }
3086
3087 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3088
3089 if (INTEL_GEN(dev_priv) < 4)
3090 intel_crtc->dspaddr_offset = linear_offset;
3091
3092 intel_crtc->adjusted_x = x;
3093 intel_crtc->adjusted_y = y;
3094
3095 I915_WRITE(reg, dspcntr);
3096
3097 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3098 if (INTEL_GEN(dev_priv) >= 4) {
3099 I915_WRITE(DSPSURF(plane),
3100 intel_fb_gtt_offset(fb, rotation) +
3101 intel_crtc->dspaddr_offset);
3102 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3103 I915_WRITE(DSPLINOFF(plane), linear_offset);
3104 } else {
3105 I915_WRITE(DSPADDR(plane),
3106 intel_fb_gtt_offset(fb, rotation) +
3107 intel_crtc->dspaddr_offset);
3108 }
3109 POSTING_READ(reg);
3110 }
3111
3112 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3113 struct drm_crtc *crtc)
3114 {
3115 struct drm_device *dev = crtc->dev;
3116 struct drm_i915_private *dev_priv = to_i915(dev);
3117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3118 int plane = intel_crtc->plane;
3119
3120 I915_WRITE(DSPCNTR(plane), 0);
3121 if (INTEL_INFO(dev_priv)->gen >= 4)
3122 I915_WRITE(DSPSURF(plane), 0);
3123 else
3124 I915_WRITE(DSPADDR(plane), 0);
3125 POSTING_READ(DSPCNTR(plane));
3126 }
3127
3128 static void ironlake_update_primary_plane(struct drm_plane *primary,
3129 const struct intel_crtc_state *crtc_state,
3130 const struct intel_plane_state *plane_state)
3131 {
3132 struct drm_device *dev = primary->dev;
3133 struct drm_i915_private *dev_priv = to_i915(dev);
3134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3135 struct drm_framebuffer *fb = plane_state->base.fb;
3136 int plane = intel_crtc->plane;
3137 u32 linear_offset;
3138 u32 dspcntr;
3139 i915_reg_t reg = DSPCNTR(plane);
3140 unsigned int rotation = plane_state->base.rotation;
3141 int x = plane_state->base.src.x1 >> 16;
3142 int y = plane_state->base.src.y1 >> 16;
3143
3144 dspcntr = DISPPLANE_GAMMA_ENABLE;
3145 dspcntr |= DISPLAY_PLANE_ENABLE;
3146
3147 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3148 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3149
3150 switch (fb->pixel_format) {
3151 case DRM_FORMAT_C8:
3152 dspcntr |= DISPPLANE_8BPP;
3153 break;
3154 case DRM_FORMAT_RGB565:
3155 dspcntr |= DISPPLANE_BGRX565;
3156 break;
3157 case DRM_FORMAT_XRGB8888:
3158 dspcntr |= DISPPLANE_BGRX888;
3159 break;
3160 case DRM_FORMAT_XBGR8888:
3161 dspcntr |= DISPPLANE_RGBX888;
3162 break;
3163 case DRM_FORMAT_XRGB2101010:
3164 dspcntr |= DISPPLANE_BGRX101010;
3165 break;
3166 case DRM_FORMAT_XBGR2101010:
3167 dspcntr |= DISPPLANE_RGBX101010;
3168 break;
3169 default:
3170 BUG();
3171 }
3172
3173 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3174 dspcntr |= DISPPLANE_TILED;
3175
3176 if (rotation & DRM_ROTATE_180)
3177 dspcntr |= DISPPLANE_ROTATE_180;
3178
3179 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv))
3180 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3181
3182 intel_add_fb_offsets(&x, &y, plane_state, 0);
3183
3184 intel_crtc->dspaddr_offset =
3185 intel_compute_tile_offset(&x, &y, plane_state, 0);
3186
3187 /* HSW+ does this automagically in hardware */
3188 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) &&
3189 rotation & DRM_ROTATE_180) {
3190 x += crtc_state->pipe_src_w - 1;
3191 y += crtc_state->pipe_src_h - 1;
3192 }
3193
3194 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3195
3196 intel_crtc->adjusted_x = x;
3197 intel_crtc->adjusted_y = y;
3198
3199 I915_WRITE(reg, dspcntr);
3200
3201 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3202 I915_WRITE(DSPSURF(plane),
3203 intel_fb_gtt_offset(fb, rotation) +
3204 intel_crtc->dspaddr_offset);
3205 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3206 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3207 } else {
3208 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3209 I915_WRITE(DSPLINOFF(plane), linear_offset);
3210 }
3211 POSTING_READ(reg);
3212 }
3213
3214 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3215 uint64_t fb_modifier, uint32_t pixel_format)
3216 {
3217 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3218 return 64;
3219 } else {
3220 int cpp = drm_format_plane_cpp(pixel_format, 0);
3221
3222 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3223 }
3224 }
3225
3226 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb,
3227 unsigned int rotation)
3228 {
3229 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3230 struct i915_ggtt_view view;
3231 struct i915_vma *vma;
3232
3233 intel_fill_fb_ggtt_view(&view, fb, rotation);
3234
3235 vma = i915_gem_object_to_ggtt(obj, &view);
3236 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
3237 view.type))
3238 return -1;
3239
3240 return i915_ggtt_offset(vma);
3241 }
3242
3243 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3244 {
3245 struct drm_device *dev = intel_crtc->base.dev;
3246 struct drm_i915_private *dev_priv = to_i915(dev);
3247
3248 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3249 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3250 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3251 }
3252
3253 /*
3254 * This function detaches (aka. unbinds) unused scalers in hardware
3255 */
3256 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3257 {
3258 struct intel_crtc_scaler_state *scaler_state;
3259 int i;
3260
3261 scaler_state = &intel_crtc->config->scaler_state;
3262
3263 /* loop through and disable scalers that aren't in use */
3264 for (i = 0; i < intel_crtc->num_scalers; i++) {
3265 if (!scaler_state->scalers[i].in_use)
3266 skl_detach_scaler(intel_crtc, i);
3267 }
3268 }
3269
3270 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3271 unsigned int rotation)
3272 {
3273 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3274 u32 stride = intel_fb_pitch(fb, plane, rotation);
3275
3276 /*
3277 * The stride is either expressed as a multiple of 64 bytes chunks for
3278 * linear buffers or in number of tiles for tiled buffers.
3279 */
3280 if (drm_rotation_90_or_270(rotation)) {
3281 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
3282
3283 stride /= intel_tile_height(dev_priv, fb->modifier[0], cpp);
3284 } else {
3285 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3286 fb->pixel_format);
3287 }
3288
3289 return stride;
3290 }
3291
3292 u32 skl_plane_ctl_format(uint32_t pixel_format)
3293 {
3294 switch (pixel_format) {
3295 case DRM_FORMAT_C8:
3296 return PLANE_CTL_FORMAT_INDEXED;
3297 case DRM_FORMAT_RGB565:
3298 return PLANE_CTL_FORMAT_RGB_565;
3299 case DRM_FORMAT_XBGR8888:
3300 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3301 case DRM_FORMAT_XRGB8888:
3302 return PLANE_CTL_FORMAT_XRGB_8888;
3303 /*
3304 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3305 * to be already pre-multiplied. We need to add a knob (or a different
3306 * DRM_FORMAT) for user-space to configure that.
3307 */
3308 case DRM_FORMAT_ABGR8888:
3309 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3310 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3311 case DRM_FORMAT_ARGB8888:
3312 return PLANE_CTL_FORMAT_XRGB_8888 |
3313 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3314 case DRM_FORMAT_XRGB2101010:
3315 return PLANE_CTL_FORMAT_XRGB_2101010;
3316 case DRM_FORMAT_XBGR2101010:
3317 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3318 case DRM_FORMAT_YUYV:
3319 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3320 case DRM_FORMAT_YVYU:
3321 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3322 case DRM_FORMAT_UYVY:
3323 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3324 case DRM_FORMAT_VYUY:
3325 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3326 default:
3327 MISSING_CASE(pixel_format);
3328 }
3329
3330 return 0;
3331 }
3332
3333 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3334 {
3335 switch (fb_modifier) {
3336 case DRM_FORMAT_MOD_NONE:
3337 break;
3338 case I915_FORMAT_MOD_X_TILED:
3339 return PLANE_CTL_TILED_X;
3340 case I915_FORMAT_MOD_Y_TILED:
3341 return PLANE_CTL_TILED_Y;
3342 case I915_FORMAT_MOD_Yf_TILED:
3343 return PLANE_CTL_TILED_YF;
3344 default:
3345 MISSING_CASE(fb_modifier);
3346 }
3347
3348 return 0;
3349 }
3350
3351 u32 skl_plane_ctl_rotation(unsigned int rotation)
3352 {
3353 switch (rotation) {
3354 case DRM_ROTATE_0:
3355 break;
3356 /*
3357 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3358 * while i915 HW rotation is clockwise, thats why this swapping.
3359 */
3360 case DRM_ROTATE_90:
3361 return PLANE_CTL_ROTATE_270;
3362 case DRM_ROTATE_180:
3363 return PLANE_CTL_ROTATE_180;
3364 case DRM_ROTATE_270:
3365 return PLANE_CTL_ROTATE_90;
3366 default:
3367 MISSING_CASE(rotation);
3368 }
3369
3370 return 0;
3371 }
3372
3373 static void skylake_update_primary_plane(struct drm_plane *plane,
3374 const struct intel_crtc_state *crtc_state,
3375 const struct intel_plane_state *plane_state)
3376 {
3377 struct drm_device *dev = plane->dev;
3378 struct drm_i915_private *dev_priv = to_i915(dev);
3379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3380 struct drm_framebuffer *fb = plane_state->base.fb;
3381 int pipe = intel_crtc->pipe;
3382 u32 plane_ctl;
3383 unsigned int rotation = plane_state->base.rotation;
3384 u32 stride = skl_plane_stride(fb, 0, rotation);
3385 u32 surf_addr = plane_state->main.offset;
3386 int scaler_id = plane_state->scaler_id;
3387 int src_x = plane_state->main.x;
3388 int src_y = plane_state->main.y;
3389 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3390 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3391 int dst_x = plane_state->base.dst.x1;
3392 int dst_y = plane_state->base.dst.y1;
3393 int dst_w = drm_rect_width(&plane_state->base.dst);
3394 int dst_h = drm_rect_height(&plane_state->base.dst);
3395
3396 plane_ctl = PLANE_CTL_ENABLE |
3397 PLANE_CTL_PIPE_GAMMA_ENABLE |
3398 PLANE_CTL_PIPE_CSC_ENABLE;
3399
3400 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3401 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3402 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3403 plane_ctl |= skl_plane_ctl_rotation(rotation);
3404
3405 /* Sizes are 0 based */
3406 src_w--;
3407 src_h--;
3408 dst_w--;
3409 dst_h--;
3410
3411 intel_crtc->dspaddr_offset = surf_addr;
3412
3413 intel_crtc->adjusted_x = src_x;
3414 intel_crtc->adjusted_y = src_y;
3415
3416 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3417 I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
3418 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3419 I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w);
3420
3421 if (scaler_id >= 0) {
3422 uint32_t ps_ctrl = 0;
3423
3424 WARN_ON(!dst_w || !dst_h);
3425 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3426 crtc_state->scaler_state.scalers[scaler_id].mode;
3427 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3428 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3429 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3430 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3431 I915_WRITE(PLANE_POS(pipe, 0), 0);
3432 } else {
3433 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3434 }
3435
3436 I915_WRITE(PLANE_SURF(pipe, 0),
3437 intel_fb_gtt_offset(fb, rotation) + surf_addr);
3438
3439 POSTING_READ(PLANE_SURF(pipe, 0));
3440 }
3441
3442 static void skylake_disable_primary_plane(struct drm_plane *primary,
3443 struct drm_crtc *crtc)
3444 {
3445 struct drm_device *dev = crtc->dev;
3446 struct drm_i915_private *dev_priv = to_i915(dev);
3447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3448 int pipe = intel_crtc->pipe;
3449
3450 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3451 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3452 POSTING_READ(PLANE_SURF(pipe, 0));
3453 }
3454
3455 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3456 static int
3457 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3458 int x, int y, enum mode_set_atomic state)
3459 {
3460 /* Support for kgdboc is disabled, this needs a major rework. */
3461 DRM_ERROR("legacy panic handler not supported any more.\n");
3462
3463 return -ENODEV;
3464 }
3465
3466 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3467 {
3468 struct intel_crtc *crtc;
3469
3470 for_each_intel_crtc(&dev_priv->drm, crtc)
3471 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3472 }
3473
3474 static void intel_update_primary_planes(struct drm_device *dev)
3475 {
3476 struct drm_crtc *crtc;
3477
3478 for_each_crtc(dev, crtc) {
3479 struct intel_plane *plane = to_intel_plane(crtc->primary);
3480 struct intel_plane_state *plane_state =
3481 to_intel_plane_state(plane->base.state);
3482
3483 if (plane_state->base.visible)
3484 plane->update_plane(&plane->base,
3485 to_intel_crtc_state(crtc->state),
3486 plane_state);
3487 }
3488 }
3489
3490 static int
3491 __intel_display_resume(struct drm_device *dev,
3492 struct drm_atomic_state *state)
3493 {
3494 struct drm_crtc_state *crtc_state;
3495 struct drm_crtc *crtc;
3496 int i, ret;
3497
3498 intel_modeset_setup_hw_state(dev);
3499 i915_redisable_vga(to_i915(dev));
3500
3501 if (!state)
3502 return 0;
3503
3504 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3505 /*
3506 * Force recalculation even if we restore
3507 * current state. With fast modeset this may not result
3508 * in a modeset when the state is compatible.
3509 */
3510 crtc_state->mode_changed = true;
3511 }
3512
3513 /* ignore any reset values/BIOS leftovers in the WM registers */
3514 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3515
3516 ret = drm_atomic_commit(state);
3517
3518 WARN_ON(ret == -EDEADLK);
3519 return ret;
3520 }
3521
3522 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3523 {
3524 return intel_has_gpu_reset(dev_priv) &&
3525 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3526 }
3527
3528 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3529 {
3530 struct drm_device *dev = &dev_priv->drm;
3531 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3532 struct drm_atomic_state *state;
3533 int ret;
3534
3535 /*
3536 * Need mode_config.mutex so that we don't
3537 * trample ongoing ->detect() and whatnot.
3538 */
3539 mutex_lock(&dev->mode_config.mutex);
3540 drm_modeset_acquire_init(ctx, 0);
3541 while (1) {
3542 ret = drm_modeset_lock_all_ctx(dev, ctx);
3543 if (ret != -EDEADLK)
3544 break;
3545
3546 drm_modeset_backoff(ctx);
3547 }
3548
3549 /* reset doesn't touch the display, but flips might get nuked anyway, */
3550 if (!i915.force_reset_modeset_test &&
3551 !gpu_reset_clobbers_display(dev_priv))
3552 return;
3553
3554 /*
3555 * Disabling the crtcs gracefully seems nicer. Also the
3556 * g33 docs say we should at least disable all the planes.
3557 */
3558 state = drm_atomic_helper_duplicate_state(dev, ctx);
3559 if (IS_ERR(state)) {
3560 ret = PTR_ERR(state);
3561 state = NULL;
3562 DRM_ERROR("Duplicating state failed with %i\n", ret);
3563 goto err;
3564 }
3565
3566 ret = drm_atomic_helper_disable_all(dev, ctx);
3567 if (ret) {
3568 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3569 goto err;
3570 }
3571
3572 dev_priv->modeset_restore_state = state;
3573 state->acquire_ctx = ctx;
3574 return;
3575
3576 err:
3577 drm_atomic_state_put(state);
3578 }
3579
3580 void intel_finish_reset(struct drm_i915_private *dev_priv)
3581 {
3582 struct drm_device *dev = &dev_priv->drm;
3583 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3584 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3585 int ret;
3586
3587 /*
3588 * Flips in the rings will be nuked by the reset,
3589 * so complete all pending flips so that user space
3590 * will get its events and not get stuck.
3591 */
3592 intel_complete_page_flips(dev_priv);
3593
3594 dev_priv->modeset_restore_state = NULL;
3595
3596 /* reset doesn't touch the display */
3597 if (!gpu_reset_clobbers_display(dev_priv)) {
3598 if (!state) {
3599 /*
3600 * Flips in the rings have been nuked by the reset,
3601 * so update the base address of all primary
3602 * planes to the the last fb to make sure we're
3603 * showing the correct fb after a reset.
3604 *
3605 * FIXME: Atomic will make this obsolete since we won't schedule
3606 * CS-based flips (which might get lost in gpu resets) any more.
3607 */
3608 intel_update_primary_planes(dev);
3609 } else {
3610 ret = __intel_display_resume(dev, state);
3611 if (ret)
3612 DRM_ERROR("Restoring old state failed with %i\n", ret);
3613 }
3614 } else {
3615 /*
3616 * The display has been reset as well,
3617 * so need a full re-initialization.
3618 */
3619 intel_runtime_pm_disable_interrupts(dev_priv);
3620 intel_runtime_pm_enable_interrupts(dev_priv);
3621
3622 intel_pps_unlock_regs_wa(dev_priv);
3623 intel_modeset_init_hw(dev);
3624
3625 spin_lock_irq(&dev_priv->irq_lock);
3626 if (dev_priv->display.hpd_irq_setup)
3627 dev_priv->display.hpd_irq_setup(dev_priv);
3628 spin_unlock_irq(&dev_priv->irq_lock);
3629
3630 ret = __intel_display_resume(dev, state);
3631 if (ret)
3632 DRM_ERROR("Restoring old state failed with %i\n", ret);
3633
3634 intel_hpd_init(dev_priv);
3635 }
3636
3637 if (state)
3638 drm_atomic_state_put(state);
3639 drm_modeset_drop_locks(ctx);
3640 drm_modeset_acquire_fini(ctx);
3641 mutex_unlock(&dev->mode_config.mutex);
3642 }
3643
3644 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3645 {
3646 struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3647
3648 if (i915_reset_in_progress(error))
3649 return true;
3650
3651 if (crtc->reset_count != i915_reset_count(error))
3652 return true;
3653
3654 return false;
3655 }
3656
3657 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3658 {
3659 struct drm_device *dev = crtc->dev;
3660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3661 bool pending;
3662
3663 if (abort_flip_on_reset(intel_crtc))
3664 return false;
3665
3666 spin_lock_irq(&dev->event_lock);
3667 pending = to_intel_crtc(crtc)->flip_work != NULL;
3668 spin_unlock_irq(&dev->event_lock);
3669
3670 return pending;
3671 }
3672
3673 static void intel_update_pipe_config(struct intel_crtc *crtc,
3674 struct intel_crtc_state *old_crtc_state)
3675 {
3676 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3677 struct intel_crtc_state *pipe_config =
3678 to_intel_crtc_state(crtc->base.state);
3679
3680 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3681 crtc->base.mode = crtc->base.state->mode;
3682
3683 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3684 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3685 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3686
3687 /*
3688 * Update pipe size and adjust fitter if needed: the reason for this is
3689 * that in compute_mode_changes we check the native mode (not the pfit
3690 * mode) to see if we can flip rather than do a full mode set. In the
3691 * fastboot case, we'll flip, but if we don't update the pipesrc and
3692 * pfit state, we'll end up with a big fb scanned out into the wrong
3693 * sized surface.
3694 */
3695
3696 I915_WRITE(PIPESRC(crtc->pipe),
3697 ((pipe_config->pipe_src_w - 1) << 16) |
3698 (pipe_config->pipe_src_h - 1));
3699
3700 /* on skylake this is done by detaching scalers */
3701 if (INTEL_GEN(dev_priv) >= 9) {
3702 skl_detach_scalers(crtc);
3703
3704 if (pipe_config->pch_pfit.enabled)
3705 skylake_pfit_enable(crtc);
3706 } else if (HAS_PCH_SPLIT(dev_priv)) {
3707 if (pipe_config->pch_pfit.enabled)
3708 ironlake_pfit_enable(crtc);
3709 else if (old_crtc_state->pch_pfit.enabled)
3710 ironlake_pfit_disable(crtc, true);
3711 }
3712 }
3713
3714 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3715 {
3716 struct drm_device *dev = crtc->dev;
3717 struct drm_i915_private *dev_priv = to_i915(dev);
3718 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3719 int pipe = intel_crtc->pipe;
3720 i915_reg_t reg;
3721 u32 temp;
3722
3723 /* enable normal train */
3724 reg = FDI_TX_CTL(pipe);
3725 temp = I915_READ(reg);
3726 if (IS_IVYBRIDGE(dev_priv)) {
3727 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3728 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3729 } else {
3730 temp &= ~FDI_LINK_TRAIN_NONE;
3731 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3732 }
3733 I915_WRITE(reg, temp);
3734
3735 reg = FDI_RX_CTL(pipe);
3736 temp = I915_READ(reg);
3737 if (HAS_PCH_CPT(dev_priv)) {
3738 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3739 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3740 } else {
3741 temp &= ~FDI_LINK_TRAIN_NONE;
3742 temp |= FDI_LINK_TRAIN_NONE;
3743 }
3744 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3745
3746 /* wait one idle pattern time */
3747 POSTING_READ(reg);
3748 udelay(1000);
3749
3750 /* IVB wants error correction enabled */
3751 if (IS_IVYBRIDGE(dev_priv))
3752 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3753 FDI_FE_ERRC_ENABLE);
3754 }
3755
3756 /* The FDI link training functions for ILK/Ibexpeak. */
3757 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3758 {
3759 struct drm_device *dev = crtc->dev;
3760 struct drm_i915_private *dev_priv = to_i915(dev);
3761 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3762 int pipe = intel_crtc->pipe;
3763 i915_reg_t reg;
3764 u32 temp, tries;
3765
3766 /* FDI needs bits from pipe first */
3767 assert_pipe_enabled(dev_priv, pipe);
3768
3769 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3770 for train result */
3771 reg = FDI_RX_IMR(pipe);
3772 temp = I915_READ(reg);
3773 temp &= ~FDI_RX_SYMBOL_LOCK;
3774 temp &= ~FDI_RX_BIT_LOCK;
3775 I915_WRITE(reg, temp);
3776 I915_READ(reg);
3777 udelay(150);
3778
3779 /* enable CPU FDI TX and PCH FDI RX */
3780 reg = FDI_TX_CTL(pipe);
3781 temp = I915_READ(reg);
3782 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3783 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3784 temp &= ~FDI_LINK_TRAIN_NONE;
3785 temp |= FDI_LINK_TRAIN_PATTERN_1;
3786 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3787
3788 reg = FDI_RX_CTL(pipe);
3789 temp = I915_READ(reg);
3790 temp &= ~FDI_LINK_TRAIN_NONE;
3791 temp |= FDI_LINK_TRAIN_PATTERN_1;
3792 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3793
3794 POSTING_READ(reg);
3795 udelay(150);
3796
3797 /* Ironlake workaround, enable clock pointer after FDI enable*/
3798 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3799 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3800 FDI_RX_PHASE_SYNC_POINTER_EN);
3801
3802 reg = FDI_RX_IIR(pipe);
3803 for (tries = 0; tries < 5; tries++) {
3804 temp = I915_READ(reg);
3805 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3806
3807 if ((temp & FDI_RX_BIT_LOCK)) {
3808 DRM_DEBUG_KMS("FDI train 1 done.\n");
3809 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3810 break;
3811 }
3812 }
3813 if (tries == 5)
3814 DRM_ERROR("FDI train 1 fail!\n");
3815
3816 /* Train 2 */
3817 reg = FDI_TX_CTL(pipe);
3818 temp = I915_READ(reg);
3819 temp &= ~FDI_LINK_TRAIN_NONE;
3820 temp |= FDI_LINK_TRAIN_PATTERN_2;
3821 I915_WRITE(reg, temp);
3822
3823 reg = FDI_RX_CTL(pipe);
3824 temp = I915_READ(reg);
3825 temp &= ~FDI_LINK_TRAIN_NONE;
3826 temp |= FDI_LINK_TRAIN_PATTERN_2;
3827 I915_WRITE(reg, temp);
3828
3829 POSTING_READ(reg);
3830 udelay(150);
3831
3832 reg = FDI_RX_IIR(pipe);
3833 for (tries = 0; tries < 5; tries++) {
3834 temp = I915_READ(reg);
3835 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3836
3837 if (temp & FDI_RX_SYMBOL_LOCK) {
3838 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3839 DRM_DEBUG_KMS("FDI train 2 done.\n");
3840 break;
3841 }
3842 }
3843 if (tries == 5)
3844 DRM_ERROR("FDI train 2 fail!\n");
3845
3846 DRM_DEBUG_KMS("FDI train done\n");
3847
3848 }
3849
3850 static const int snb_b_fdi_train_param[] = {
3851 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3852 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3853 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3854 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3855 };
3856
3857 /* The FDI link training functions for SNB/Cougarpoint. */
3858 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3859 {
3860 struct drm_device *dev = crtc->dev;
3861 struct drm_i915_private *dev_priv = to_i915(dev);
3862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3863 int pipe = intel_crtc->pipe;
3864 i915_reg_t reg;
3865 u32 temp, i, retry;
3866
3867 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3868 for train result */
3869 reg = FDI_RX_IMR(pipe);
3870 temp = I915_READ(reg);
3871 temp &= ~FDI_RX_SYMBOL_LOCK;
3872 temp &= ~FDI_RX_BIT_LOCK;
3873 I915_WRITE(reg, temp);
3874
3875 POSTING_READ(reg);
3876 udelay(150);
3877
3878 /* enable CPU FDI TX and PCH FDI RX */
3879 reg = FDI_TX_CTL(pipe);
3880 temp = I915_READ(reg);
3881 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3882 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3883 temp &= ~FDI_LINK_TRAIN_NONE;
3884 temp |= FDI_LINK_TRAIN_PATTERN_1;
3885 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3886 /* SNB-B */
3887 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3888 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3889
3890 I915_WRITE(FDI_RX_MISC(pipe),
3891 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3892
3893 reg = FDI_RX_CTL(pipe);
3894 temp = I915_READ(reg);
3895 if (HAS_PCH_CPT(dev_priv)) {
3896 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3897 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3898 } else {
3899 temp &= ~FDI_LINK_TRAIN_NONE;
3900 temp |= FDI_LINK_TRAIN_PATTERN_1;
3901 }
3902 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3903
3904 POSTING_READ(reg);
3905 udelay(150);
3906
3907 for (i = 0; i < 4; i++) {
3908 reg = FDI_TX_CTL(pipe);
3909 temp = I915_READ(reg);
3910 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3911 temp |= snb_b_fdi_train_param[i];
3912 I915_WRITE(reg, temp);
3913
3914 POSTING_READ(reg);
3915 udelay(500);
3916
3917 for (retry = 0; retry < 5; retry++) {
3918 reg = FDI_RX_IIR(pipe);
3919 temp = I915_READ(reg);
3920 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3921 if (temp & FDI_RX_BIT_LOCK) {
3922 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3923 DRM_DEBUG_KMS("FDI train 1 done.\n");
3924 break;
3925 }
3926 udelay(50);
3927 }
3928 if (retry < 5)
3929 break;
3930 }
3931 if (i == 4)
3932 DRM_ERROR("FDI train 1 fail!\n");
3933
3934 /* Train 2 */
3935 reg = FDI_TX_CTL(pipe);
3936 temp = I915_READ(reg);
3937 temp &= ~FDI_LINK_TRAIN_NONE;
3938 temp |= FDI_LINK_TRAIN_PATTERN_2;
3939 if (IS_GEN6(dev_priv)) {
3940 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3941 /* SNB-B */
3942 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3943 }
3944 I915_WRITE(reg, temp);
3945
3946 reg = FDI_RX_CTL(pipe);
3947 temp = I915_READ(reg);
3948 if (HAS_PCH_CPT(dev_priv)) {
3949 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3950 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3951 } else {
3952 temp &= ~FDI_LINK_TRAIN_NONE;
3953 temp |= FDI_LINK_TRAIN_PATTERN_2;
3954 }
3955 I915_WRITE(reg, temp);
3956
3957 POSTING_READ(reg);
3958 udelay(150);
3959
3960 for (i = 0; i < 4; i++) {
3961 reg = FDI_TX_CTL(pipe);
3962 temp = I915_READ(reg);
3963 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3964 temp |= snb_b_fdi_train_param[i];
3965 I915_WRITE(reg, temp);
3966
3967 POSTING_READ(reg);
3968 udelay(500);
3969
3970 for (retry = 0; retry < 5; retry++) {
3971 reg = FDI_RX_IIR(pipe);
3972 temp = I915_READ(reg);
3973 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3974 if (temp & FDI_RX_SYMBOL_LOCK) {
3975 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3976 DRM_DEBUG_KMS("FDI train 2 done.\n");
3977 break;
3978 }
3979 udelay(50);
3980 }
3981 if (retry < 5)
3982 break;
3983 }
3984 if (i == 4)
3985 DRM_ERROR("FDI train 2 fail!\n");
3986
3987 DRM_DEBUG_KMS("FDI train done.\n");
3988 }
3989
3990 /* Manual link training for Ivy Bridge A0 parts */
3991 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3992 {
3993 struct drm_device *dev = crtc->dev;
3994 struct drm_i915_private *dev_priv = to_i915(dev);
3995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3996 int pipe = intel_crtc->pipe;
3997 i915_reg_t reg;
3998 u32 temp, i, j;
3999
4000 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4001 for train result */
4002 reg = FDI_RX_IMR(pipe);
4003 temp = I915_READ(reg);
4004 temp &= ~FDI_RX_SYMBOL_LOCK;
4005 temp &= ~FDI_RX_BIT_LOCK;
4006 I915_WRITE(reg, temp);
4007
4008 POSTING_READ(reg);
4009 udelay(150);
4010
4011 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4012 I915_READ(FDI_RX_IIR(pipe)));
4013
4014 /* Try each vswing and preemphasis setting twice before moving on */
4015 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4016 /* disable first in case we need to retry */
4017 reg = FDI_TX_CTL(pipe);
4018 temp = I915_READ(reg);
4019 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4020 temp &= ~FDI_TX_ENABLE;
4021 I915_WRITE(reg, temp);
4022
4023 reg = FDI_RX_CTL(pipe);
4024 temp = I915_READ(reg);
4025 temp &= ~FDI_LINK_TRAIN_AUTO;
4026 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4027 temp &= ~FDI_RX_ENABLE;
4028 I915_WRITE(reg, temp);
4029
4030 /* enable CPU FDI TX and PCH FDI RX */
4031 reg = FDI_TX_CTL(pipe);
4032 temp = I915_READ(reg);
4033 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4034 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4035 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4036 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4037 temp |= snb_b_fdi_train_param[j/2];
4038 temp |= FDI_COMPOSITE_SYNC;
4039 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4040
4041 I915_WRITE(FDI_RX_MISC(pipe),
4042 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4043
4044 reg = FDI_RX_CTL(pipe);
4045 temp = I915_READ(reg);
4046 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4047 temp |= FDI_COMPOSITE_SYNC;
4048 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4049
4050 POSTING_READ(reg);
4051 udelay(1); /* should be 0.5us */
4052
4053 for (i = 0; i < 4; i++) {
4054 reg = FDI_RX_IIR(pipe);
4055 temp = I915_READ(reg);
4056 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4057
4058 if (temp & FDI_RX_BIT_LOCK ||
4059 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4060 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4061 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4062 i);
4063 break;
4064 }
4065 udelay(1); /* should be 0.5us */
4066 }
4067 if (i == 4) {
4068 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4069 continue;
4070 }
4071
4072 /* Train 2 */
4073 reg = FDI_TX_CTL(pipe);
4074 temp = I915_READ(reg);
4075 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4076 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4077 I915_WRITE(reg, temp);
4078
4079 reg = FDI_RX_CTL(pipe);
4080 temp = I915_READ(reg);
4081 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4082 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4083 I915_WRITE(reg, temp);
4084
4085 POSTING_READ(reg);
4086 udelay(2); /* should be 1.5us */
4087
4088 for (i = 0; i < 4; i++) {
4089 reg = FDI_RX_IIR(pipe);
4090 temp = I915_READ(reg);
4091 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4092
4093 if (temp & FDI_RX_SYMBOL_LOCK ||
4094 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4095 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4096 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4097 i);
4098 goto train_done;
4099 }
4100 udelay(2); /* should be 1.5us */
4101 }
4102 if (i == 4)
4103 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4104 }
4105
4106 train_done:
4107 DRM_DEBUG_KMS("FDI train done.\n");
4108 }
4109
4110 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4111 {
4112 struct drm_device *dev = intel_crtc->base.dev;
4113 struct drm_i915_private *dev_priv = to_i915(dev);
4114 int pipe = intel_crtc->pipe;
4115 i915_reg_t reg;
4116 u32 temp;
4117
4118 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4119 reg = FDI_RX_CTL(pipe);
4120 temp = I915_READ(reg);
4121 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4122 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4123 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4124 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4125
4126 POSTING_READ(reg);
4127 udelay(200);
4128
4129 /* Switch from Rawclk to PCDclk */
4130 temp = I915_READ(reg);
4131 I915_WRITE(reg, temp | FDI_PCDCLK);
4132
4133 POSTING_READ(reg);
4134 udelay(200);
4135
4136 /* Enable CPU FDI TX PLL, always on for Ironlake */
4137 reg = FDI_TX_CTL(pipe);
4138 temp = I915_READ(reg);
4139 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4140 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4141
4142 POSTING_READ(reg);
4143 udelay(100);
4144 }
4145 }
4146
4147 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4148 {
4149 struct drm_device *dev = intel_crtc->base.dev;
4150 struct drm_i915_private *dev_priv = to_i915(dev);
4151 int pipe = intel_crtc->pipe;
4152 i915_reg_t reg;
4153 u32 temp;
4154
4155 /* Switch from PCDclk to Rawclk */
4156 reg = FDI_RX_CTL(pipe);
4157 temp = I915_READ(reg);
4158 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4159
4160 /* Disable CPU FDI TX PLL */
4161 reg = FDI_TX_CTL(pipe);
4162 temp = I915_READ(reg);
4163 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4164
4165 POSTING_READ(reg);
4166 udelay(100);
4167
4168 reg = FDI_RX_CTL(pipe);
4169 temp = I915_READ(reg);
4170 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4171
4172 /* Wait for the clocks to turn off. */
4173 POSTING_READ(reg);
4174 udelay(100);
4175 }
4176
4177 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4178 {
4179 struct drm_device *dev = crtc->dev;
4180 struct drm_i915_private *dev_priv = to_i915(dev);
4181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4182 int pipe = intel_crtc->pipe;
4183 i915_reg_t reg;
4184 u32 temp;
4185
4186 /* disable CPU FDI tx and PCH FDI rx */
4187 reg = FDI_TX_CTL(pipe);
4188 temp = I915_READ(reg);
4189 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4190 POSTING_READ(reg);
4191
4192 reg = FDI_RX_CTL(pipe);
4193 temp = I915_READ(reg);
4194 temp &= ~(0x7 << 16);
4195 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4196 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4197
4198 POSTING_READ(reg);
4199 udelay(100);
4200
4201 /* Ironlake workaround, disable clock pointer after downing FDI */
4202 if (HAS_PCH_IBX(dev_priv))
4203 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4204
4205 /* still set train pattern 1 */
4206 reg = FDI_TX_CTL(pipe);
4207 temp = I915_READ(reg);
4208 temp &= ~FDI_LINK_TRAIN_NONE;
4209 temp |= FDI_LINK_TRAIN_PATTERN_1;
4210 I915_WRITE(reg, temp);
4211
4212 reg = FDI_RX_CTL(pipe);
4213 temp = I915_READ(reg);
4214 if (HAS_PCH_CPT(dev_priv)) {
4215 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4216 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4217 } else {
4218 temp &= ~FDI_LINK_TRAIN_NONE;
4219 temp |= FDI_LINK_TRAIN_PATTERN_1;
4220 }
4221 /* BPC in FDI rx is consistent with that in PIPECONF */
4222 temp &= ~(0x07 << 16);
4223 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4224 I915_WRITE(reg, temp);
4225
4226 POSTING_READ(reg);
4227 udelay(100);
4228 }
4229
4230 bool intel_has_pending_fb_unpin(struct drm_device *dev)
4231 {
4232 struct drm_i915_private *dev_priv = to_i915(dev);
4233 struct intel_crtc *crtc;
4234
4235 /* Note that we don't need to be called with mode_config.lock here
4236 * as our list of CRTC objects is static for the lifetime of the
4237 * device and so cannot disappear as we iterate. Similarly, we can
4238 * happily treat the predicates as racy, atomic checks as userspace
4239 * cannot claim and pin a new fb without at least acquring the
4240 * struct_mutex and so serialising with us.
4241 */
4242 for_each_intel_crtc(dev, crtc) {
4243 if (atomic_read(&crtc->unpin_work_count) == 0)
4244 continue;
4245
4246 if (crtc->flip_work)
4247 intel_wait_for_vblank(dev_priv, crtc->pipe);
4248
4249 return true;
4250 }
4251
4252 return false;
4253 }
4254
4255 static void page_flip_completed(struct intel_crtc *intel_crtc)
4256 {
4257 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4258 struct intel_flip_work *work = intel_crtc->flip_work;
4259
4260 intel_crtc->flip_work = NULL;
4261
4262 if (work->event)
4263 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4264
4265 drm_crtc_vblank_put(&intel_crtc->base);
4266
4267 wake_up_all(&dev_priv->pending_flip_queue);
4268 queue_work(dev_priv->wq, &work->unpin_work);
4269
4270 trace_i915_flip_complete(intel_crtc->plane,
4271 work->pending_flip_obj);
4272 }
4273
4274 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4275 {
4276 struct drm_device *dev = crtc->dev;
4277 struct drm_i915_private *dev_priv = to_i915(dev);
4278 long ret;
4279
4280 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4281
4282 ret = wait_event_interruptible_timeout(
4283 dev_priv->pending_flip_queue,
4284 !intel_crtc_has_pending_flip(crtc),
4285 60*HZ);
4286
4287 if (ret < 0)
4288 return ret;
4289
4290 if (ret == 0) {
4291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4292 struct intel_flip_work *work;
4293
4294 spin_lock_irq(&dev->event_lock);
4295 work = intel_crtc->flip_work;
4296 if (work && !is_mmio_work(work)) {
4297 WARN_ONCE(1, "Removing stuck page flip\n");
4298 page_flip_completed(intel_crtc);
4299 }
4300 spin_unlock_irq(&dev->event_lock);
4301 }
4302
4303 return 0;
4304 }
4305
4306 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4307 {
4308 u32 temp;
4309
4310 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4311
4312 mutex_lock(&dev_priv->sb_lock);
4313
4314 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4315 temp |= SBI_SSCCTL_DISABLE;
4316 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4317
4318 mutex_unlock(&dev_priv->sb_lock);
4319 }
4320
4321 /* Program iCLKIP clock to the desired frequency */
4322 static void lpt_program_iclkip(struct drm_crtc *crtc)
4323 {
4324 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4325 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
4326 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4327 u32 temp;
4328
4329 lpt_disable_iclkip(dev_priv);
4330
4331 /* The iCLK virtual clock root frequency is in MHz,
4332 * but the adjusted_mode->crtc_clock in in KHz. To get the
4333 * divisors, it is necessary to divide one by another, so we
4334 * convert the virtual clock precision to KHz here for higher
4335 * precision.
4336 */
4337 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4338 u32 iclk_virtual_root_freq = 172800 * 1000;
4339 u32 iclk_pi_range = 64;
4340 u32 desired_divisor;
4341
4342 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4343 clock << auxdiv);
4344 divsel = (desired_divisor / iclk_pi_range) - 2;
4345 phaseinc = desired_divisor % iclk_pi_range;
4346
4347 /*
4348 * Near 20MHz is a corner case which is
4349 * out of range for the 7-bit divisor
4350 */
4351 if (divsel <= 0x7f)
4352 break;
4353 }
4354
4355 /* This should not happen with any sane values */
4356 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4357 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4358 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4359 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4360
4361 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4362 clock,
4363 auxdiv,
4364 divsel,
4365 phasedir,
4366 phaseinc);
4367
4368 mutex_lock(&dev_priv->sb_lock);
4369
4370 /* Program SSCDIVINTPHASE6 */
4371 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4372 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4373 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4374 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4375 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4376 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4377 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4378 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4379
4380 /* Program SSCAUXDIV */
4381 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4382 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4383 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4384 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4385
4386 /* Enable modulator and associated divider */
4387 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4388 temp &= ~SBI_SSCCTL_DISABLE;
4389 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4390
4391 mutex_unlock(&dev_priv->sb_lock);
4392
4393 /* Wait for initialization time */
4394 udelay(24);
4395
4396 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4397 }
4398
4399 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4400 {
4401 u32 divsel, phaseinc, auxdiv;
4402 u32 iclk_virtual_root_freq = 172800 * 1000;
4403 u32 iclk_pi_range = 64;
4404 u32 desired_divisor;
4405 u32 temp;
4406
4407 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4408 return 0;
4409
4410 mutex_lock(&dev_priv->sb_lock);
4411
4412 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4413 if (temp & SBI_SSCCTL_DISABLE) {
4414 mutex_unlock(&dev_priv->sb_lock);
4415 return 0;
4416 }
4417
4418 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4419 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4420 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4421 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4422 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4423
4424 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4425 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4426 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4427
4428 mutex_unlock(&dev_priv->sb_lock);
4429
4430 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4431
4432 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4433 desired_divisor << auxdiv);
4434 }
4435
4436 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4437 enum pipe pch_transcoder)
4438 {
4439 struct drm_device *dev = crtc->base.dev;
4440 struct drm_i915_private *dev_priv = to_i915(dev);
4441 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4442
4443 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4444 I915_READ(HTOTAL(cpu_transcoder)));
4445 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4446 I915_READ(HBLANK(cpu_transcoder)));
4447 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4448 I915_READ(HSYNC(cpu_transcoder)));
4449
4450 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4451 I915_READ(VTOTAL(cpu_transcoder)));
4452 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4453 I915_READ(VBLANK(cpu_transcoder)));
4454 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4455 I915_READ(VSYNC(cpu_transcoder)));
4456 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4457 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4458 }
4459
4460 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4461 {
4462 struct drm_i915_private *dev_priv = to_i915(dev);
4463 uint32_t temp;
4464
4465 temp = I915_READ(SOUTH_CHICKEN1);
4466 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4467 return;
4468
4469 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4470 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4471
4472 temp &= ~FDI_BC_BIFURCATION_SELECT;
4473 if (enable)
4474 temp |= FDI_BC_BIFURCATION_SELECT;
4475
4476 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4477 I915_WRITE(SOUTH_CHICKEN1, temp);
4478 POSTING_READ(SOUTH_CHICKEN1);
4479 }
4480
4481 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4482 {
4483 struct drm_device *dev = intel_crtc->base.dev;
4484
4485 switch (intel_crtc->pipe) {
4486 case PIPE_A:
4487 break;
4488 case PIPE_B:
4489 if (intel_crtc->config->fdi_lanes > 2)
4490 cpt_set_fdi_bc_bifurcation(dev, false);
4491 else
4492 cpt_set_fdi_bc_bifurcation(dev, true);
4493
4494 break;
4495 case PIPE_C:
4496 cpt_set_fdi_bc_bifurcation(dev, true);
4497
4498 break;
4499 default:
4500 BUG();
4501 }
4502 }
4503
4504 /* Return which DP Port should be selected for Transcoder DP control */
4505 static enum port
4506 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4507 {
4508 struct drm_device *dev = crtc->dev;
4509 struct intel_encoder *encoder;
4510
4511 for_each_encoder_on_crtc(dev, crtc, encoder) {
4512 if (encoder->type == INTEL_OUTPUT_DP ||
4513 encoder->type == INTEL_OUTPUT_EDP)
4514 return enc_to_dig_port(&encoder->base)->port;
4515 }
4516
4517 return -1;
4518 }
4519
4520 /*
4521 * Enable PCH resources required for PCH ports:
4522 * - PCH PLLs
4523 * - FDI training & RX/TX
4524 * - update transcoder timings
4525 * - DP transcoding bits
4526 * - transcoder
4527 */
4528 static void ironlake_pch_enable(struct drm_crtc *crtc)
4529 {
4530 struct drm_device *dev = crtc->dev;
4531 struct drm_i915_private *dev_priv = to_i915(dev);
4532 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4533 int pipe = intel_crtc->pipe;
4534 u32 temp;
4535
4536 assert_pch_transcoder_disabled(dev_priv, pipe);
4537
4538 if (IS_IVYBRIDGE(dev_priv))
4539 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4540
4541 /* Write the TU size bits before fdi link training, so that error
4542 * detection works. */
4543 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4544 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4545
4546 /* For PCH output, training FDI link */
4547 dev_priv->display.fdi_link_train(crtc);
4548
4549 /* We need to program the right clock selection before writing the pixel
4550 * mutliplier into the DPLL. */
4551 if (HAS_PCH_CPT(dev_priv)) {
4552 u32 sel;
4553
4554 temp = I915_READ(PCH_DPLL_SEL);
4555 temp |= TRANS_DPLL_ENABLE(pipe);
4556 sel = TRANS_DPLLB_SEL(pipe);
4557 if (intel_crtc->config->shared_dpll ==
4558 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4559 temp |= sel;
4560 else
4561 temp &= ~sel;
4562 I915_WRITE(PCH_DPLL_SEL, temp);
4563 }
4564
4565 /* XXX: pch pll's can be enabled any time before we enable the PCH
4566 * transcoder, and we actually should do this to not upset any PCH
4567 * transcoder that already use the clock when we share it.
4568 *
4569 * Note that enable_shared_dpll tries to do the right thing, but
4570 * get_shared_dpll unconditionally resets the pll - we need that to have
4571 * the right LVDS enable sequence. */
4572 intel_enable_shared_dpll(intel_crtc);
4573
4574 /* set transcoder timing, panel must allow it */
4575 assert_panel_unlocked(dev_priv, pipe);
4576 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4577
4578 intel_fdi_normal_train(crtc);
4579
4580 /* For PCH DP, enable TRANS_DP_CTL */
4581 if (HAS_PCH_CPT(dev_priv) &&
4582 intel_crtc_has_dp_encoder(intel_crtc->config)) {
4583 const struct drm_display_mode *adjusted_mode =
4584 &intel_crtc->config->base.adjusted_mode;
4585 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4586 i915_reg_t reg = TRANS_DP_CTL(pipe);
4587 temp = I915_READ(reg);
4588 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4589 TRANS_DP_SYNC_MASK |
4590 TRANS_DP_BPC_MASK);
4591 temp |= TRANS_DP_OUTPUT_ENABLE;
4592 temp |= bpc << 9; /* same format but at 11:9 */
4593
4594 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4595 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4596 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4597 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4598
4599 switch (intel_trans_dp_port_sel(crtc)) {
4600 case PORT_B:
4601 temp |= TRANS_DP_PORT_SEL_B;
4602 break;
4603 case PORT_C:
4604 temp |= TRANS_DP_PORT_SEL_C;
4605 break;
4606 case PORT_D:
4607 temp |= TRANS_DP_PORT_SEL_D;
4608 break;
4609 default:
4610 BUG();
4611 }
4612
4613 I915_WRITE(reg, temp);
4614 }
4615
4616 ironlake_enable_pch_transcoder(dev_priv, pipe);
4617 }
4618
4619 static void lpt_pch_enable(struct drm_crtc *crtc)
4620 {
4621 struct drm_device *dev = crtc->dev;
4622 struct drm_i915_private *dev_priv = to_i915(dev);
4623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4624 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4625
4626 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4627
4628 lpt_program_iclkip(crtc);
4629
4630 /* Set transcoder timing. */
4631 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4632
4633 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4634 }
4635
4636 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4637 {
4638 struct drm_i915_private *dev_priv = to_i915(dev);
4639 i915_reg_t dslreg = PIPEDSL(pipe);
4640 u32 temp;
4641
4642 temp = I915_READ(dslreg);
4643 udelay(500);
4644 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4645 if (wait_for(I915_READ(dslreg) != temp, 5))
4646 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4647 }
4648 }
4649
4650 static int
4651 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4652 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4653 int src_w, int src_h, int dst_w, int dst_h)
4654 {
4655 struct intel_crtc_scaler_state *scaler_state =
4656 &crtc_state->scaler_state;
4657 struct intel_crtc *intel_crtc =
4658 to_intel_crtc(crtc_state->base.crtc);
4659 int need_scaling;
4660
4661 need_scaling = drm_rotation_90_or_270(rotation) ?
4662 (src_h != dst_w || src_w != dst_h):
4663 (src_w != dst_w || src_h != dst_h);
4664
4665 /*
4666 * if plane is being disabled or scaler is no more required or force detach
4667 * - free scaler binded to this plane/crtc
4668 * - in order to do this, update crtc->scaler_usage
4669 *
4670 * Here scaler state in crtc_state is set free so that
4671 * scaler can be assigned to other user. Actual register
4672 * update to free the scaler is done in plane/panel-fit programming.
4673 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4674 */
4675 if (force_detach || !need_scaling) {
4676 if (*scaler_id >= 0) {
4677 scaler_state->scaler_users &= ~(1 << scaler_user);
4678 scaler_state->scalers[*scaler_id].in_use = 0;
4679
4680 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4681 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4682 intel_crtc->pipe, scaler_user, *scaler_id,
4683 scaler_state->scaler_users);
4684 *scaler_id = -1;
4685 }
4686 return 0;
4687 }
4688
4689 /* range checks */
4690 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4691 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4692
4693 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4694 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4695 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4696 "size is out of scaler range\n",
4697 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4698 return -EINVAL;
4699 }
4700
4701 /* mark this plane as a scaler user in crtc_state */
4702 scaler_state->scaler_users |= (1 << scaler_user);
4703 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4704 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4705 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4706 scaler_state->scaler_users);
4707
4708 return 0;
4709 }
4710
4711 /**
4712 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4713 *
4714 * @state: crtc's scaler state
4715 *
4716 * Return
4717 * 0 - scaler_usage updated successfully
4718 * error - requested scaling cannot be supported or other error condition
4719 */
4720 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4721 {
4722 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4723 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4724
4725 DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4726 intel_crtc->base.base.id, intel_crtc->base.name,
4727 intel_crtc->pipe, SKL_CRTC_INDEX);
4728
4729 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4730 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4731 state->pipe_src_w, state->pipe_src_h,
4732 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4733 }
4734
4735 /**
4736 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4737 *
4738 * @state: crtc's scaler state
4739 * @plane_state: atomic plane state to update
4740 *
4741 * Return
4742 * 0 - scaler_usage updated successfully
4743 * error - requested scaling cannot be supported or other error condition
4744 */
4745 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4746 struct intel_plane_state *plane_state)
4747 {
4748
4749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4750 struct intel_plane *intel_plane =
4751 to_intel_plane(plane_state->base.plane);
4752 struct drm_framebuffer *fb = plane_state->base.fb;
4753 int ret;
4754
4755 bool force_detach = !fb || !plane_state->base.visible;
4756
4757 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4758 intel_plane->base.base.id, intel_plane->base.name,
4759 intel_crtc->pipe, drm_plane_index(&intel_plane->base));
4760
4761 ret = skl_update_scaler(crtc_state, force_detach,
4762 drm_plane_index(&intel_plane->base),
4763 &plane_state->scaler_id,
4764 plane_state->base.rotation,
4765 drm_rect_width(&plane_state->base.src) >> 16,
4766 drm_rect_height(&plane_state->base.src) >> 16,
4767 drm_rect_width(&plane_state->base.dst),
4768 drm_rect_height(&plane_state->base.dst));
4769
4770 if (ret || plane_state->scaler_id < 0)
4771 return ret;
4772
4773 /* check colorkey */
4774 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4775 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4776 intel_plane->base.base.id,
4777 intel_plane->base.name);
4778 return -EINVAL;
4779 }
4780
4781 /* Check src format */
4782 switch (fb->pixel_format) {
4783 case DRM_FORMAT_RGB565:
4784 case DRM_FORMAT_XBGR8888:
4785 case DRM_FORMAT_XRGB8888:
4786 case DRM_FORMAT_ABGR8888:
4787 case DRM_FORMAT_ARGB8888:
4788 case DRM_FORMAT_XRGB2101010:
4789 case DRM_FORMAT_XBGR2101010:
4790 case DRM_FORMAT_YUYV:
4791 case DRM_FORMAT_YVYU:
4792 case DRM_FORMAT_UYVY:
4793 case DRM_FORMAT_VYUY:
4794 break;
4795 default:
4796 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4797 intel_plane->base.base.id, intel_plane->base.name,
4798 fb->base.id, fb->pixel_format);
4799 return -EINVAL;
4800 }
4801
4802 return 0;
4803 }
4804
4805 static void skylake_scaler_disable(struct intel_crtc *crtc)
4806 {
4807 int i;
4808
4809 for (i = 0; i < crtc->num_scalers; i++)
4810 skl_detach_scaler(crtc, i);
4811 }
4812
4813 static void skylake_pfit_enable(struct intel_crtc *crtc)
4814 {
4815 struct drm_device *dev = crtc->base.dev;
4816 struct drm_i915_private *dev_priv = to_i915(dev);
4817 int pipe = crtc->pipe;
4818 struct intel_crtc_scaler_state *scaler_state =
4819 &crtc->config->scaler_state;
4820
4821 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4822
4823 if (crtc->config->pch_pfit.enabled) {
4824 int id;
4825
4826 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4827 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4828 return;
4829 }
4830
4831 id = scaler_state->scaler_id;
4832 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4833 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4834 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4835 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4836
4837 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4838 }
4839 }
4840
4841 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4842 {
4843 struct drm_device *dev = crtc->base.dev;
4844 struct drm_i915_private *dev_priv = to_i915(dev);
4845 int pipe = crtc->pipe;
4846
4847 if (crtc->config->pch_pfit.enabled) {
4848 /* Force use of hard-coded filter coefficients
4849 * as some pre-programmed values are broken,
4850 * e.g. x201.
4851 */
4852 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4853 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4854 PF_PIPE_SEL_IVB(pipe));
4855 else
4856 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4857 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4858 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4859 }
4860 }
4861
4862 void hsw_enable_ips(struct intel_crtc *crtc)
4863 {
4864 struct drm_device *dev = crtc->base.dev;
4865 struct drm_i915_private *dev_priv = to_i915(dev);
4866
4867 if (!crtc->config->ips_enabled)
4868 return;
4869
4870 /*
4871 * We can only enable IPS after we enable a plane and wait for a vblank
4872 * This function is called from post_plane_update, which is run after
4873 * a vblank wait.
4874 */
4875
4876 assert_plane_enabled(dev_priv, crtc->plane);
4877 if (IS_BROADWELL(dev_priv)) {
4878 mutex_lock(&dev_priv->rps.hw_lock);
4879 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4880 mutex_unlock(&dev_priv->rps.hw_lock);
4881 /* Quoting Art Runyan: "its not safe to expect any particular
4882 * value in IPS_CTL bit 31 after enabling IPS through the
4883 * mailbox." Moreover, the mailbox may return a bogus state,
4884 * so we need to just enable it and continue on.
4885 */
4886 } else {
4887 I915_WRITE(IPS_CTL, IPS_ENABLE);
4888 /* The bit only becomes 1 in the next vblank, so this wait here
4889 * is essentially intel_wait_for_vblank. If we don't have this
4890 * and don't wait for vblanks until the end of crtc_enable, then
4891 * the HW state readout code will complain that the expected
4892 * IPS_CTL value is not the one we read. */
4893 if (intel_wait_for_register(dev_priv,
4894 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4895 50))
4896 DRM_ERROR("Timed out waiting for IPS enable\n");
4897 }
4898 }
4899
4900 void hsw_disable_ips(struct intel_crtc *crtc)
4901 {
4902 struct drm_device *dev = crtc->base.dev;
4903 struct drm_i915_private *dev_priv = to_i915(dev);
4904
4905 if (!crtc->config->ips_enabled)
4906 return;
4907
4908 assert_plane_enabled(dev_priv, crtc->plane);
4909 if (IS_BROADWELL(dev_priv)) {
4910 mutex_lock(&dev_priv->rps.hw_lock);
4911 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4912 mutex_unlock(&dev_priv->rps.hw_lock);
4913 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4914 if (intel_wait_for_register(dev_priv,
4915 IPS_CTL, IPS_ENABLE, 0,
4916 42))
4917 DRM_ERROR("Timed out waiting for IPS disable\n");
4918 } else {
4919 I915_WRITE(IPS_CTL, 0);
4920 POSTING_READ(IPS_CTL);
4921 }
4922
4923 /* We need to wait for a vblank before we can disable the plane. */
4924 intel_wait_for_vblank(dev_priv, crtc->pipe);
4925 }
4926
4927 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4928 {
4929 if (intel_crtc->overlay) {
4930 struct drm_device *dev = intel_crtc->base.dev;
4931 struct drm_i915_private *dev_priv = to_i915(dev);
4932
4933 mutex_lock(&dev->struct_mutex);
4934 dev_priv->mm.interruptible = false;
4935 (void) intel_overlay_switch_off(intel_crtc->overlay);
4936 dev_priv->mm.interruptible = true;
4937 mutex_unlock(&dev->struct_mutex);
4938 }
4939
4940 /* Let userspace switch the overlay on again. In most cases userspace
4941 * has to recompute where to put it anyway.
4942 */
4943 }
4944
4945 /**
4946 * intel_post_enable_primary - Perform operations after enabling primary plane
4947 * @crtc: the CRTC whose primary plane was just enabled
4948 *
4949 * Performs potentially sleeping operations that must be done after the primary
4950 * plane is enabled, such as updating FBC and IPS. Note that this may be
4951 * called due to an explicit primary plane update, or due to an implicit
4952 * re-enable that is caused when a sprite plane is updated to no longer
4953 * completely hide the primary plane.
4954 */
4955 static void
4956 intel_post_enable_primary(struct drm_crtc *crtc)
4957 {
4958 struct drm_device *dev = crtc->dev;
4959 struct drm_i915_private *dev_priv = to_i915(dev);
4960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4961 int pipe = intel_crtc->pipe;
4962
4963 /*
4964 * FIXME IPS should be fine as long as one plane is
4965 * enabled, but in practice it seems to have problems
4966 * when going from primary only to sprite only and vice
4967 * versa.
4968 */
4969 hsw_enable_ips(intel_crtc);
4970
4971 /*
4972 * Gen2 reports pipe underruns whenever all planes are disabled.
4973 * So don't enable underrun reporting before at least some planes
4974 * are enabled.
4975 * FIXME: Need to fix the logic to work when we turn off all planes
4976 * but leave the pipe running.
4977 */
4978 if (IS_GEN2(dev_priv))
4979 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4980
4981 /* Underruns don't always raise interrupts, so check manually. */
4982 intel_check_cpu_fifo_underruns(dev_priv);
4983 intel_check_pch_fifo_underruns(dev_priv);
4984 }
4985
4986 /* FIXME move all this to pre_plane_update() with proper state tracking */
4987 static void
4988 intel_pre_disable_primary(struct drm_crtc *crtc)
4989 {
4990 struct drm_device *dev = crtc->dev;
4991 struct drm_i915_private *dev_priv = to_i915(dev);
4992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4993 int pipe = intel_crtc->pipe;
4994
4995 /*
4996 * Gen2 reports pipe underruns whenever all planes are disabled.
4997 * So diasble underrun reporting before all the planes get disabled.
4998 * FIXME: Need to fix the logic to work when we turn off all planes
4999 * but leave the pipe running.
5000 */
5001 if (IS_GEN2(dev_priv))
5002 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5003
5004 /*
5005 * FIXME IPS should be fine as long as one plane is
5006 * enabled, but in practice it seems to have problems
5007 * when going from primary only to sprite only and vice
5008 * versa.
5009 */
5010 hsw_disable_ips(intel_crtc);
5011 }
5012
5013 /* FIXME get rid of this and use pre_plane_update */
5014 static void
5015 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5016 {
5017 struct drm_device *dev = crtc->dev;
5018 struct drm_i915_private *dev_priv = to_i915(dev);
5019 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5020 int pipe = intel_crtc->pipe;
5021
5022 intel_pre_disable_primary(crtc);
5023
5024 /*
5025 * Vblank time updates from the shadow to live plane control register
5026 * are blocked if the memory self-refresh mode is active at that
5027 * moment. So to make sure the plane gets truly disabled, disable
5028 * first the self-refresh mode. The self-refresh enable bit in turn
5029 * will be checked/applied by the HW only at the next frame start
5030 * event which is after the vblank start event, so we need to have a
5031 * wait-for-vblank between disabling the plane and the pipe.
5032 */
5033 if (HAS_GMCH_DISPLAY(dev_priv)) {
5034 intel_set_memory_cxsr(dev_priv, false);
5035 dev_priv->wm.vlv.cxsr = false;
5036 intel_wait_for_vblank(dev_priv, pipe);
5037 }
5038 }
5039
5040 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5041 {
5042 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5043 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5044 struct intel_crtc_state *pipe_config =
5045 to_intel_crtc_state(crtc->base.state);
5046 struct drm_plane *primary = crtc->base.primary;
5047 struct drm_plane_state *old_pri_state =
5048 drm_atomic_get_existing_plane_state(old_state, primary);
5049
5050 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5051
5052 crtc->wm.cxsr_allowed = true;
5053
5054 if (pipe_config->update_wm_post && pipe_config->base.active)
5055 intel_update_watermarks(crtc);
5056
5057 if (old_pri_state) {
5058 struct intel_plane_state *primary_state =
5059 to_intel_plane_state(primary->state);
5060 struct intel_plane_state *old_primary_state =
5061 to_intel_plane_state(old_pri_state);
5062
5063 intel_fbc_post_update(crtc);
5064
5065 if (primary_state->base.visible &&
5066 (needs_modeset(&pipe_config->base) ||
5067 !old_primary_state->base.visible))
5068 intel_post_enable_primary(&crtc->base);
5069 }
5070 }
5071
5072 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
5073 {
5074 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5075 struct drm_device *dev = crtc->base.dev;
5076 struct drm_i915_private *dev_priv = to_i915(dev);
5077 struct intel_crtc_state *pipe_config =
5078 to_intel_crtc_state(crtc->base.state);
5079 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5080 struct drm_plane *primary = crtc->base.primary;
5081 struct drm_plane_state *old_pri_state =
5082 drm_atomic_get_existing_plane_state(old_state, primary);
5083 bool modeset = needs_modeset(&pipe_config->base);
5084 struct intel_atomic_state *old_intel_state =
5085 to_intel_atomic_state(old_state);
5086
5087 if (old_pri_state) {
5088 struct intel_plane_state *primary_state =
5089 to_intel_plane_state(primary->state);
5090 struct intel_plane_state *old_primary_state =
5091 to_intel_plane_state(old_pri_state);
5092
5093 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5094
5095 if (old_primary_state->base.visible &&
5096 (modeset || !primary_state->base.visible))
5097 intel_pre_disable_primary(&crtc->base);
5098 }
5099
5100 if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) {
5101 crtc->wm.cxsr_allowed = false;
5102
5103 /*
5104 * Vblank time updates from the shadow to live plane control register
5105 * are blocked if the memory self-refresh mode is active at that
5106 * moment. So to make sure the plane gets truly disabled, disable
5107 * first the self-refresh mode. The self-refresh enable bit in turn
5108 * will be checked/applied by the HW only at the next frame start
5109 * event which is after the vblank start event, so we need to have a
5110 * wait-for-vblank between disabling the plane and the pipe.
5111 */
5112 if (old_crtc_state->base.active) {
5113 intel_set_memory_cxsr(dev_priv, false);
5114 dev_priv->wm.vlv.cxsr = false;
5115 intel_wait_for_vblank(dev_priv, crtc->pipe);
5116 }
5117 }
5118
5119 /*
5120 * IVB workaround: must disable low power watermarks for at least
5121 * one frame before enabling scaling. LP watermarks can be re-enabled
5122 * when scaling is disabled.
5123 *
5124 * WaCxSRDisabledForSpriteScaling:ivb
5125 */
5126 if (pipe_config->disable_lp_wm) {
5127 ilk_disable_lp_wm(dev);
5128 intel_wait_for_vblank(dev_priv, crtc->pipe);
5129 }
5130
5131 /*
5132 * If we're doing a modeset, we're done. No need to do any pre-vblank
5133 * watermark programming here.
5134 */
5135 if (needs_modeset(&pipe_config->base))
5136 return;
5137
5138 /*
5139 * For platforms that support atomic watermarks, program the
5140 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5141 * will be the intermediate values that are safe for both pre- and
5142 * post- vblank; when vblank happens, the 'active' values will be set
5143 * to the final 'target' values and we'll do this again to get the
5144 * optimal watermarks. For gen9+ platforms, the values we program here
5145 * will be the final target values which will get automatically latched
5146 * at vblank time; no further programming will be necessary.
5147 *
5148 * If a platform hasn't been transitioned to atomic watermarks yet,
5149 * we'll continue to update watermarks the old way, if flags tell
5150 * us to.
5151 */
5152 if (dev_priv->display.initial_watermarks != NULL)
5153 dev_priv->display.initial_watermarks(old_intel_state,
5154 pipe_config);
5155 else if (pipe_config->update_wm_pre)
5156 intel_update_watermarks(crtc);
5157 }
5158
5159 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5160 {
5161 struct drm_device *dev = crtc->dev;
5162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5163 struct drm_plane *p;
5164 int pipe = intel_crtc->pipe;
5165
5166 intel_crtc_dpms_overlay_disable(intel_crtc);
5167
5168 drm_for_each_plane_mask(p, dev, plane_mask)
5169 to_intel_plane(p)->disable_plane(p, crtc);
5170
5171 /*
5172 * FIXME: Once we grow proper nuclear flip support out of this we need
5173 * to compute the mask of flip planes precisely. For the time being
5174 * consider this a flip to a NULL plane.
5175 */
5176 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5177 }
5178
5179 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5180 struct intel_crtc_state *crtc_state,
5181 struct drm_atomic_state *old_state)
5182 {
5183 struct drm_connector_state *old_conn_state;
5184 struct drm_connector *conn;
5185 int i;
5186
5187 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5188 struct drm_connector_state *conn_state = conn->state;
5189 struct intel_encoder *encoder =
5190 to_intel_encoder(conn_state->best_encoder);
5191
5192 if (conn_state->crtc != crtc)
5193 continue;
5194
5195 if (encoder->pre_pll_enable)
5196 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5197 }
5198 }
5199
5200 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5201 struct intel_crtc_state *crtc_state,
5202 struct drm_atomic_state *old_state)
5203 {
5204 struct drm_connector_state *old_conn_state;
5205 struct drm_connector *conn;
5206 int i;
5207
5208 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5209 struct drm_connector_state *conn_state = conn->state;
5210 struct intel_encoder *encoder =
5211 to_intel_encoder(conn_state->best_encoder);
5212
5213 if (conn_state->crtc != crtc)
5214 continue;
5215
5216 if (encoder->pre_enable)
5217 encoder->pre_enable(encoder, crtc_state, conn_state);
5218 }
5219 }
5220
5221 static void intel_encoders_enable(struct drm_crtc *crtc,
5222 struct intel_crtc_state *crtc_state,
5223 struct drm_atomic_state *old_state)
5224 {
5225 struct drm_connector_state *old_conn_state;
5226 struct drm_connector *conn;
5227 int i;
5228
5229 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5230 struct drm_connector_state *conn_state = conn->state;
5231 struct intel_encoder *encoder =
5232 to_intel_encoder(conn_state->best_encoder);
5233
5234 if (conn_state->crtc != crtc)
5235 continue;
5236
5237 encoder->enable(encoder, crtc_state, conn_state);
5238 intel_opregion_notify_encoder(encoder, true);
5239 }
5240 }
5241
5242 static void intel_encoders_disable(struct drm_crtc *crtc,
5243 struct intel_crtc_state *old_crtc_state,
5244 struct drm_atomic_state *old_state)
5245 {
5246 struct drm_connector_state *old_conn_state;
5247 struct drm_connector *conn;
5248 int i;
5249
5250 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5251 struct intel_encoder *encoder =
5252 to_intel_encoder(old_conn_state->best_encoder);
5253
5254 if (old_conn_state->crtc != crtc)
5255 continue;
5256
5257 intel_opregion_notify_encoder(encoder, false);
5258 encoder->disable(encoder, old_crtc_state, old_conn_state);
5259 }
5260 }
5261
5262 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5263 struct intel_crtc_state *old_crtc_state,
5264 struct drm_atomic_state *old_state)
5265 {
5266 struct drm_connector_state *old_conn_state;
5267 struct drm_connector *conn;
5268 int i;
5269
5270 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5271 struct intel_encoder *encoder =
5272 to_intel_encoder(old_conn_state->best_encoder);
5273
5274 if (old_conn_state->crtc != crtc)
5275 continue;
5276
5277 if (encoder->post_disable)
5278 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5279 }
5280 }
5281
5282 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5283 struct intel_crtc_state *old_crtc_state,
5284 struct drm_atomic_state *old_state)
5285 {
5286 struct drm_connector_state *old_conn_state;
5287 struct drm_connector *conn;
5288 int i;
5289
5290 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5291 struct intel_encoder *encoder =
5292 to_intel_encoder(old_conn_state->best_encoder);
5293
5294 if (old_conn_state->crtc != crtc)
5295 continue;
5296
5297 if (encoder->post_pll_disable)
5298 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5299 }
5300 }
5301
5302 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5303 struct drm_atomic_state *old_state)
5304 {
5305 struct drm_crtc *crtc = pipe_config->base.crtc;
5306 struct drm_device *dev = crtc->dev;
5307 struct drm_i915_private *dev_priv = to_i915(dev);
5308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5309 int pipe = intel_crtc->pipe;
5310 struct intel_atomic_state *old_intel_state =
5311 to_intel_atomic_state(old_state);
5312
5313 if (WARN_ON(intel_crtc->active))
5314 return;
5315
5316 /*
5317 * Sometimes spurious CPU pipe underruns happen during FDI
5318 * training, at least with VGA+HDMI cloning. Suppress them.
5319 *
5320 * On ILK we get an occasional spurious CPU pipe underruns
5321 * between eDP port A enable and vdd enable. Also PCH port
5322 * enable seems to result in the occasional CPU pipe underrun.
5323 *
5324 * Spurious PCH underruns also occur during PCH enabling.
5325 */
5326 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5327 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5328 if (intel_crtc->config->has_pch_encoder)
5329 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5330
5331 if (intel_crtc->config->has_pch_encoder)
5332 intel_prepare_shared_dpll(intel_crtc);
5333
5334 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5335 intel_dp_set_m_n(intel_crtc, M1_N1);
5336
5337 intel_set_pipe_timings(intel_crtc);
5338 intel_set_pipe_src_size(intel_crtc);
5339
5340 if (intel_crtc->config->has_pch_encoder) {
5341 intel_cpu_transcoder_set_m_n(intel_crtc,
5342 &intel_crtc->config->fdi_m_n, NULL);
5343 }
5344
5345 ironlake_set_pipeconf(crtc);
5346
5347 intel_crtc->active = true;
5348
5349 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5350
5351 if (intel_crtc->config->has_pch_encoder) {
5352 /* Note: FDI PLL enabling _must_ be done before we enable the
5353 * cpu pipes, hence this is separate from all the other fdi/pch
5354 * enabling. */
5355 ironlake_fdi_pll_enable(intel_crtc);
5356 } else {
5357 assert_fdi_tx_disabled(dev_priv, pipe);
5358 assert_fdi_rx_disabled(dev_priv, pipe);
5359 }
5360
5361 ironlake_pfit_enable(intel_crtc);
5362
5363 /*
5364 * On ILK+ LUT must be loaded before the pipe is running but with
5365 * clocks enabled
5366 */
5367 intel_color_load_luts(&pipe_config->base);
5368
5369 if (dev_priv->display.initial_watermarks != NULL)
5370 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5371 intel_enable_pipe(intel_crtc);
5372
5373 if (intel_crtc->config->has_pch_encoder)
5374 ironlake_pch_enable(crtc);
5375
5376 assert_vblank_disabled(crtc);
5377 drm_crtc_vblank_on(crtc);
5378
5379 intel_encoders_enable(crtc, pipe_config, old_state);
5380
5381 if (HAS_PCH_CPT(dev_priv))
5382 cpt_verify_modeset(dev, intel_crtc->pipe);
5383
5384 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5385 if (intel_crtc->config->has_pch_encoder)
5386 intel_wait_for_vblank(dev_priv, pipe);
5387 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5388 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5389 }
5390
5391 /* IPS only exists on ULT machines and is tied to pipe A. */
5392 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5393 {
5394 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5395 }
5396
5397 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5398 struct drm_atomic_state *old_state)
5399 {
5400 struct drm_crtc *crtc = pipe_config->base.crtc;
5401 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5403 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5404 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5405 struct intel_atomic_state *old_intel_state =
5406 to_intel_atomic_state(old_state);
5407
5408 if (WARN_ON(intel_crtc->active))
5409 return;
5410
5411 if (intel_crtc->config->has_pch_encoder)
5412 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5413 false);
5414
5415 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5416
5417 if (intel_crtc->config->shared_dpll)
5418 intel_enable_shared_dpll(intel_crtc);
5419
5420 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5421 intel_dp_set_m_n(intel_crtc, M1_N1);
5422
5423 if (!transcoder_is_dsi(cpu_transcoder))
5424 intel_set_pipe_timings(intel_crtc);
5425
5426 intel_set_pipe_src_size(intel_crtc);
5427
5428 if (cpu_transcoder != TRANSCODER_EDP &&
5429 !transcoder_is_dsi(cpu_transcoder)) {
5430 I915_WRITE(PIPE_MULT(cpu_transcoder),
5431 intel_crtc->config->pixel_multiplier - 1);
5432 }
5433
5434 if (intel_crtc->config->has_pch_encoder) {
5435 intel_cpu_transcoder_set_m_n(intel_crtc,
5436 &intel_crtc->config->fdi_m_n, NULL);
5437 }
5438
5439 if (!transcoder_is_dsi(cpu_transcoder))
5440 haswell_set_pipeconf(crtc);
5441
5442 haswell_set_pipemisc(crtc);
5443
5444 intel_color_set_csc(&pipe_config->base);
5445
5446 intel_crtc->active = true;
5447
5448 if (intel_crtc->config->has_pch_encoder)
5449 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5450 else
5451 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5452
5453 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5454
5455 if (intel_crtc->config->has_pch_encoder)
5456 dev_priv->display.fdi_link_train(crtc);
5457
5458 if (!transcoder_is_dsi(cpu_transcoder))
5459 intel_ddi_enable_pipe_clock(intel_crtc);
5460
5461 if (INTEL_GEN(dev_priv) >= 9)
5462 skylake_pfit_enable(intel_crtc);
5463 else
5464 ironlake_pfit_enable(intel_crtc);
5465
5466 /*
5467 * On ILK+ LUT must be loaded before the pipe is running but with
5468 * clocks enabled
5469 */
5470 intel_color_load_luts(&pipe_config->base);
5471
5472 intel_ddi_set_pipe_settings(crtc);
5473 if (!transcoder_is_dsi(cpu_transcoder))
5474 intel_ddi_enable_transcoder_func(crtc);
5475
5476 if (dev_priv->display.initial_watermarks != NULL)
5477 dev_priv->display.initial_watermarks(old_intel_state,
5478 pipe_config);
5479 else
5480 intel_update_watermarks(intel_crtc);
5481
5482 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5483 if (!transcoder_is_dsi(cpu_transcoder))
5484 intel_enable_pipe(intel_crtc);
5485
5486 if (intel_crtc->config->has_pch_encoder)
5487 lpt_pch_enable(crtc);
5488
5489 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5490 intel_ddi_set_vc_payload_alloc(crtc, true);
5491
5492 assert_vblank_disabled(crtc);
5493 drm_crtc_vblank_on(crtc);
5494
5495 intel_encoders_enable(crtc, pipe_config, old_state);
5496
5497 if (intel_crtc->config->has_pch_encoder) {
5498 intel_wait_for_vblank(dev_priv, pipe);
5499 intel_wait_for_vblank(dev_priv, pipe);
5500 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5501 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5502 true);
5503 }
5504
5505 /* If we change the relative order between pipe/planes enabling, we need
5506 * to change the workaround. */
5507 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5508 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5509 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5510 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5511 }
5512 }
5513
5514 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5515 {
5516 struct drm_device *dev = crtc->base.dev;
5517 struct drm_i915_private *dev_priv = to_i915(dev);
5518 int pipe = crtc->pipe;
5519
5520 /* To avoid upsetting the power well on haswell only disable the pfit if
5521 * it's in use. The hw state code will make sure we get this right. */
5522 if (force || crtc->config->pch_pfit.enabled) {
5523 I915_WRITE(PF_CTL(pipe), 0);
5524 I915_WRITE(PF_WIN_POS(pipe), 0);
5525 I915_WRITE(PF_WIN_SZ(pipe), 0);
5526 }
5527 }
5528
5529 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5530 struct drm_atomic_state *old_state)
5531 {
5532 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5533 struct drm_device *dev = crtc->dev;
5534 struct drm_i915_private *dev_priv = to_i915(dev);
5535 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5536 int pipe = intel_crtc->pipe;
5537
5538 /*
5539 * Sometimes spurious CPU pipe underruns happen when the
5540 * pipe is already disabled, but FDI RX/TX is still enabled.
5541 * Happens at least with VGA+HDMI cloning. Suppress them.
5542 */
5543 if (intel_crtc->config->has_pch_encoder) {
5544 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5545 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5546 }
5547
5548 intel_encoders_disable(crtc, old_crtc_state, old_state);
5549
5550 drm_crtc_vblank_off(crtc);
5551 assert_vblank_disabled(crtc);
5552
5553 intel_disable_pipe(intel_crtc);
5554
5555 ironlake_pfit_disable(intel_crtc, false);
5556
5557 if (intel_crtc->config->has_pch_encoder)
5558 ironlake_fdi_disable(crtc);
5559
5560 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5561
5562 if (intel_crtc->config->has_pch_encoder) {
5563 ironlake_disable_pch_transcoder(dev_priv, pipe);
5564
5565 if (HAS_PCH_CPT(dev_priv)) {
5566 i915_reg_t reg;
5567 u32 temp;
5568
5569 /* disable TRANS_DP_CTL */
5570 reg = TRANS_DP_CTL(pipe);
5571 temp = I915_READ(reg);
5572 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5573 TRANS_DP_PORT_SEL_MASK);
5574 temp |= TRANS_DP_PORT_SEL_NONE;
5575 I915_WRITE(reg, temp);
5576
5577 /* disable DPLL_SEL */
5578 temp = I915_READ(PCH_DPLL_SEL);
5579 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5580 I915_WRITE(PCH_DPLL_SEL, temp);
5581 }
5582
5583 ironlake_fdi_pll_disable(intel_crtc);
5584 }
5585
5586 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5587 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5588 }
5589
5590 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5591 struct drm_atomic_state *old_state)
5592 {
5593 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5594 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5596 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5597
5598 if (intel_crtc->config->has_pch_encoder)
5599 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5600 false);
5601
5602 intel_encoders_disable(crtc, old_crtc_state, old_state);
5603
5604 drm_crtc_vblank_off(crtc);
5605 assert_vblank_disabled(crtc);
5606
5607 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5608 if (!transcoder_is_dsi(cpu_transcoder))
5609 intel_disable_pipe(intel_crtc);
5610
5611 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5612 intel_ddi_set_vc_payload_alloc(crtc, false);
5613
5614 if (!transcoder_is_dsi(cpu_transcoder))
5615 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5616
5617 if (INTEL_GEN(dev_priv) >= 9)
5618 skylake_scaler_disable(intel_crtc);
5619 else
5620 ironlake_pfit_disable(intel_crtc, false);
5621
5622 if (!transcoder_is_dsi(cpu_transcoder))
5623 intel_ddi_disable_pipe_clock(intel_crtc);
5624
5625 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5626
5627 if (old_crtc_state->has_pch_encoder)
5628 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5629 true);
5630 }
5631
5632 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5633 {
5634 struct drm_device *dev = crtc->base.dev;
5635 struct drm_i915_private *dev_priv = to_i915(dev);
5636 struct intel_crtc_state *pipe_config = crtc->config;
5637
5638 if (!pipe_config->gmch_pfit.control)
5639 return;
5640
5641 /*
5642 * The panel fitter should only be adjusted whilst the pipe is disabled,
5643 * according to register description and PRM.
5644 */
5645 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5646 assert_pipe_disabled(dev_priv, crtc->pipe);
5647
5648 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5649 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5650
5651 /* Border color in case we don't scale up to the full screen. Black by
5652 * default, change to something else for debugging. */
5653 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5654 }
5655
5656 static enum intel_display_power_domain port_to_power_domain(enum port port)
5657 {
5658 switch (port) {
5659 case PORT_A:
5660 return POWER_DOMAIN_PORT_DDI_A_LANES;
5661 case PORT_B:
5662 return POWER_DOMAIN_PORT_DDI_B_LANES;
5663 case PORT_C:
5664 return POWER_DOMAIN_PORT_DDI_C_LANES;
5665 case PORT_D:
5666 return POWER_DOMAIN_PORT_DDI_D_LANES;
5667 case PORT_E:
5668 return POWER_DOMAIN_PORT_DDI_E_LANES;
5669 default:
5670 MISSING_CASE(port);
5671 return POWER_DOMAIN_PORT_OTHER;
5672 }
5673 }
5674
5675 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5676 {
5677 switch (port) {
5678 case PORT_A:
5679 return POWER_DOMAIN_AUX_A;
5680 case PORT_B:
5681 return POWER_DOMAIN_AUX_B;
5682 case PORT_C:
5683 return POWER_DOMAIN_AUX_C;
5684 case PORT_D:
5685 return POWER_DOMAIN_AUX_D;
5686 case PORT_E:
5687 /* FIXME: Check VBT for actual wiring of PORT E */
5688 return POWER_DOMAIN_AUX_D;
5689 default:
5690 MISSING_CASE(port);
5691 return POWER_DOMAIN_AUX_A;
5692 }
5693 }
5694
5695 enum intel_display_power_domain
5696 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5697 {
5698 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5699 struct intel_digital_port *intel_dig_port;
5700
5701 switch (intel_encoder->type) {
5702 case INTEL_OUTPUT_UNKNOWN:
5703 /* Only DDI platforms should ever use this output type */
5704 WARN_ON_ONCE(!HAS_DDI(dev_priv));
5705 case INTEL_OUTPUT_DP:
5706 case INTEL_OUTPUT_HDMI:
5707 case INTEL_OUTPUT_EDP:
5708 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5709 return port_to_power_domain(intel_dig_port->port);
5710 case INTEL_OUTPUT_DP_MST:
5711 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5712 return port_to_power_domain(intel_dig_port->port);
5713 case INTEL_OUTPUT_ANALOG:
5714 return POWER_DOMAIN_PORT_CRT;
5715 case INTEL_OUTPUT_DSI:
5716 return POWER_DOMAIN_PORT_DSI;
5717 default:
5718 return POWER_DOMAIN_PORT_OTHER;
5719 }
5720 }
5721
5722 enum intel_display_power_domain
5723 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5724 {
5725 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5726 struct intel_digital_port *intel_dig_port;
5727
5728 switch (intel_encoder->type) {
5729 case INTEL_OUTPUT_UNKNOWN:
5730 case INTEL_OUTPUT_HDMI:
5731 /*
5732 * Only DDI platforms should ever use these output types.
5733 * We can get here after the HDMI detect code has already set
5734 * the type of the shared encoder. Since we can't be sure
5735 * what's the status of the given connectors, play safe and
5736 * run the DP detection too.
5737 */
5738 WARN_ON_ONCE(!HAS_DDI(dev_priv));
5739 case INTEL_OUTPUT_DP:
5740 case INTEL_OUTPUT_EDP:
5741 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5742 return port_to_aux_power_domain(intel_dig_port->port);
5743 case INTEL_OUTPUT_DP_MST:
5744 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5745 return port_to_aux_power_domain(intel_dig_port->port);
5746 default:
5747 MISSING_CASE(intel_encoder->type);
5748 return POWER_DOMAIN_AUX_A;
5749 }
5750 }
5751
5752 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5753 struct intel_crtc_state *crtc_state)
5754 {
5755 struct drm_device *dev = crtc->dev;
5756 struct drm_encoder *encoder;
5757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5758 enum pipe pipe = intel_crtc->pipe;
5759 unsigned long mask;
5760 enum transcoder transcoder = crtc_state->cpu_transcoder;
5761
5762 if (!crtc_state->base.active)
5763 return 0;
5764
5765 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5766 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5767 if (crtc_state->pch_pfit.enabled ||
5768 crtc_state->pch_pfit.force_thru)
5769 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5770
5771 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5772 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5773
5774 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5775 }
5776
5777 if (crtc_state->shared_dpll)
5778 mask |= BIT(POWER_DOMAIN_PLLS);
5779
5780 return mask;
5781 }
5782
5783 static unsigned long
5784 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5785 struct intel_crtc_state *crtc_state)
5786 {
5787 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5789 enum intel_display_power_domain domain;
5790 unsigned long domains, new_domains, old_domains;
5791
5792 old_domains = intel_crtc->enabled_power_domains;
5793 intel_crtc->enabled_power_domains = new_domains =
5794 get_crtc_power_domains(crtc, crtc_state);
5795
5796 domains = new_domains & ~old_domains;
5797
5798 for_each_power_domain(domain, domains)
5799 intel_display_power_get(dev_priv, domain);
5800
5801 return old_domains & ~new_domains;
5802 }
5803
5804 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5805 unsigned long domains)
5806 {
5807 enum intel_display_power_domain domain;
5808
5809 for_each_power_domain(domain, domains)
5810 intel_display_power_put(dev_priv, domain);
5811 }
5812
5813 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5814 {
5815 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5816
5817 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5818 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5819 return max_cdclk_freq;
5820 else if (IS_CHERRYVIEW(dev_priv))
5821 return max_cdclk_freq*95/100;
5822 else if (INTEL_INFO(dev_priv)->gen < 4)
5823 return 2*max_cdclk_freq*90/100;
5824 else
5825 return max_cdclk_freq*90/100;
5826 }
5827
5828 static int skl_calc_cdclk(int max_pixclk, int vco);
5829
5830 static void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
5831 {
5832 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5833 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5834 int max_cdclk, vco;
5835
5836 vco = dev_priv->skl_preferred_vco_freq;
5837 WARN_ON(vco != 8100000 && vco != 8640000);
5838
5839 /*
5840 * Use the lower (vco 8640) cdclk values as a
5841 * first guess. skl_calc_cdclk() will correct it
5842 * if the preferred vco is 8100 instead.
5843 */
5844 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5845 max_cdclk = 617143;
5846 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5847 max_cdclk = 540000;
5848 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5849 max_cdclk = 432000;
5850 else
5851 max_cdclk = 308571;
5852
5853 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5854 } else if (IS_BROXTON(dev_priv)) {
5855 dev_priv->max_cdclk_freq = 624000;
5856 } else if (IS_BROADWELL(dev_priv)) {
5857 /*
5858 * FIXME with extra cooling we can allow
5859 * 540 MHz for ULX and 675 Mhz for ULT.
5860 * How can we know if extra cooling is
5861 * available? PCI ID, VTB, something else?
5862 */
5863 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5864 dev_priv->max_cdclk_freq = 450000;
5865 else if (IS_BDW_ULX(dev_priv))
5866 dev_priv->max_cdclk_freq = 450000;
5867 else if (IS_BDW_ULT(dev_priv))
5868 dev_priv->max_cdclk_freq = 540000;
5869 else
5870 dev_priv->max_cdclk_freq = 675000;
5871 } else if (IS_CHERRYVIEW(dev_priv)) {
5872 dev_priv->max_cdclk_freq = 320000;
5873 } else if (IS_VALLEYVIEW(dev_priv)) {
5874 dev_priv->max_cdclk_freq = 400000;
5875 } else {
5876 /* otherwise assume cdclk is fixed */
5877 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5878 }
5879
5880 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5881
5882 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5883 dev_priv->max_cdclk_freq);
5884
5885 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5886 dev_priv->max_dotclk_freq);
5887 }
5888
5889 static void intel_update_cdclk(struct drm_i915_private *dev_priv)
5890 {
5891 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev_priv);
5892
5893 if (INTEL_GEN(dev_priv) >= 9)
5894 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5895 dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5896 dev_priv->cdclk_pll.ref);
5897 else
5898 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5899 dev_priv->cdclk_freq);
5900
5901 /*
5902 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5903 * Programmng [sic] note: bit[9:2] should be programmed to the number
5904 * of cdclk that generates 4MHz reference clock freq which is used to
5905 * generate GMBus clock. This will vary with the cdclk freq.
5906 */
5907 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5908 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5909 }
5910
5911 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5912 static int skl_cdclk_decimal(int cdclk)
5913 {
5914 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5915 }
5916
5917 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5918 {
5919 int ratio;
5920
5921 if (cdclk == dev_priv->cdclk_pll.ref)
5922 return 0;
5923
5924 switch (cdclk) {
5925 default:
5926 MISSING_CASE(cdclk);
5927 case 144000:
5928 case 288000:
5929 case 384000:
5930 case 576000:
5931 ratio = 60;
5932 break;
5933 case 624000:
5934 ratio = 65;
5935 break;
5936 }
5937
5938 return dev_priv->cdclk_pll.ref * ratio;
5939 }
5940
5941 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5942 {
5943 I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5944
5945 /* Timeout 200us */
5946 if (intel_wait_for_register(dev_priv,
5947 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5948 1))
5949 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5950
5951 dev_priv->cdclk_pll.vco = 0;
5952 }
5953
5954 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5955 {
5956 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5957 u32 val;
5958
5959 val = I915_READ(BXT_DE_PLL_CTL);
5960 val &= ~BXT_DE_PLL_RATIO_MASK;
5961 val |= BXT_DE_PLL_RATIO(ratio);
5962 I915_WRITE(BXT_DE_PLL_CTL, val);
5963
5964 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5965
5966 /* Timeout 200us */
5967 if (intel_wait_for_register(dev_priv,
5968 BXT_DE_PLL_ENABLE,
5969 BXT_DE_PLL_LOCK,
5970 BXT_DE_PLL_LOCK,
5971 1))
5972 DRM_ERROR("timeout waiting for DE PLL lock\n");
5973
5974 dev_priv->cdclk_pll.vco = vco;
5975 }
5976
5977 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5978 {
5979 u32 val, divider;
5980 int vco, ret;
5981
5982 vco = bxt_de_pll_vco(dev_priv, cdclk);
5983
5984 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5985
5986 /* cdclk = vco / 2 / div{1,1.5,2,4} */
5987 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5988 case 8:
5989 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5990 break;
5991 case 4:
5992 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5993 break;
5994 case 3:
5995 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5996 break;
5997 case 2:
5998 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5999 break;
6000 default:
6001 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
6002 WARN_ON(vco != 0);
6003
6004 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6005 break;
6006 }
6007
6008 /* Inform power controller of upcoming frequency change */
6009 mutex_lock(&dev_priv->rps.hw_lock);
6010 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6011 0x80000000);
6012 mutex_unlock(&dev_priv->rps.hw_lock);
6013
6014 if (ret) {
6015 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
6016 ret, cdclk);
6017 return;
6018 }
6019
6020 if (dev_priv->cdclk_pll.vco != 0 &&
6021 dev_priv->cdclk_pll.vco != vco)
6022 bxt_de_pll_disable(dev_priv);
6023
6024 if (dev_priv->cdclk_pll.vco != vco)
6025 bxt_de_pll_enable(dev_priv, vco);
6026
6027 val = divider | skl_cdclk_decimal(cdclk);
6028 /*
6029 * FIXME if only the cd2x divider needs changing, it could be done
6030 * without shutting off the pipe (if only one pipe is active).
6031 */
6032 val |= BXT_CDCLK_CD2X_PIPE_NONE;
6033 /*
6034 * Disable SSA Precharge when CD clock frequency < 500 MHz,
6035 * enable otherwise.
6036 */
6037 if (cdclk >= 500000)
6038 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6039 I915_WRITE(CDCLK_CTL, val);
6040
6041 mutex_lock(&dev_priv->rps.hw_lock);
6042 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6043 DIV_ROUND_UP(cdclk, 25000));
6044 mutex_unlock(&dev_priv->rps.hw_lock);
6045
6046 if (ret) {
6047 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
6048 ret, cdclk);
6049 return;
6050 }
6051
6052 intel_update_cdclk(dev_priv);
6053 }
6054
6055 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
6056 {
6057 u32 cdctl, expected;
6058
6059 intel_update_cdclk(dev_priv);
6060
6061 if (dev_priv->cdclk_pll.vco == 0 ||
6062 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6063 goto sanitize;
6064
6065 /* DPLL okay; verify the cdclock
6066 *
6067 * Some BIOS versions leave an incorrect decimal frequency value and
6068 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
6069 * so sanitize this register.
6070 */
6071 cdctl = I915_READ(CDCLK_CTL);
6072 /*
6073 * Let's ignore the pipe field, since BIOS could have configured the
6074 * dividers both synching to an active pipe, or asynchronously
6075 * (PIPE_NONE).
6076 */
6077 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
6078
6079 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
6080 skl_cdclk_decimal(dev_priv->cdclk_freq);
6081 /*
6082 * Disable SSA Precharge when CD clock frequency < 500 MHz,
6083 * enable otherwise.
6084 */
6085 if (dev_priv->cdclk_freq >= 500000)
6086 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6087
6088 if (cdctl == expected)
6089 /* All well; nothing to sanitize */
6090 return;
6091
6092 sanitize:
6093 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6094
6095 /* force cdclk programming */
6096 dev_priv->cdclk_freq = 0;
6097
6098 /* force full PLL disable + enable */
6099 dev_priv->cdclk_pll.vco = -1;
6100 }
6101
6102 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
6103 {
6104 bxt_sanitize_cdclk(dev_priv);
6105
6106 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
6107 return;
6108
6109 /*
6110 * FIXME:
6111 * - The initial CDCLK needs to be read from VBT.
6112 * Need to make this change after VBT has changes for BXT.
6113 */
6114 bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
6115 }
6116
6117 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
6118 {
6119 bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
6120 }
6121
6122 static int skl_calc_cdclk(int max_pixclk, int vco)
6123 {
6124 if (vco == 8640000) {
6125 if (max_pixclk > 540000)
6126 return 617143;
6127 else if (max_pixclk > 432000)
6128 return 540000;
6129 else if (max_pixclk > 308571)
6130 return 432000;
6131 else
6132 return 308571;
6133 } else {
6134 if (max_pixclk > 540000)
6135 return 675000;
6136 else if (max_pixclk > 450000)
6137 return 540000;
6138 else if (max_pixclk > 337500)
6139 return 450000;
6140 else
6141 return 337500;
6142 }
6143 }
6144
6145 static void
6146 skl_dpll0_update(struct drm_i915_private *dev_priv)
6147 {
6148 u32 val;
6149
6150 dev_priv->cdclk_pll.ref = 24000;
6151 dev_priv->cdclk_pll.vco = 0;
6152
6153 val = I915_READ(LCPLL1_CTL);
6154 if ((val & LCPLL_PLL_ENABLE) == 0)
6155 return;
6156
6157 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
6158 return;
6159
6160 val = I915_READ(DPLL_CTRL1);
6161
6162 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
6163 DPLL_CTRL1_SSC(SKL_DPLL0) |
6164 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
6165 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
6166 return;
6167
6168 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
6169 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
6170 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
6171 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
6172 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
6173 dev_priv->cdclk_pll.vco = 8100000;
6174 break;
6175 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
6176 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
6177 dev_priv->cdclk_pll.vco = 8640000;
6178 break;
6179 default:
6180 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6181 break;
6182 }
6183 }
6184
6185 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
6186 {
6187 bool changed = dev_priv->skl_preferred_vco_freq != vco;
6188
6189 dev_priv->skl_preferred_vco_freq = vco;
6190
6191 if (changed)
6192 intel_update_max_cdclk(dev_priv);
6193 }
6194
6195 static void
6196 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
6197 {
6198 int min_cdclk = skl_calc_cdclk(0, vco);
6199 u32 val;
6200
6201 WARN_ON(vco != 8100000 && vco != 8640000);
6202
6203 /* select the minimum CDCLK before enabling DPLL 0 */
6204 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
6205 I915_WRITE(CDCLK_CTL, val);
6206 POSTING_READ(CDCLK_CTL);
6207
6208 /*
6209 * We always enable DPLL0 with the lowest link rate possible, but still
6210 * taking into account the VCO required to operate the eDP panel at the
6211 * desired frequency. The usual DP link rates operate with a VCO of
6212 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
6213 * The modeset code is responsible for the selection of the exact link
6214 * rate later on, with the constraint of choosing a frequency that
6215 * works with vco.
6216 */
6217 val = I915_READ(DPLL_CTRL1);
6218
6219 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
6220 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6221 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
6222 if (vco == 8640000)
6223 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
6224 SKL_DPLL0);
6225 else
6226 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
6227 SKL_DPLL0);
6228
6229 I915_WRITE(DPLL_CTRL1, val);
6230 POSTING_READ(DPLL_CTRL1);
6231
6232 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
6233
6234 if (intel_wait_for_register(dev_priv,
6235 LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
6236 5))
6237 DRM_ERROR("DPLL0 not locked\n");
6238
6239 dev_priv->cdclk_pll.vco = vco;
6240
6241 /* We'll want to keep using the current vco from now on. */
6242 skl_set_preferred_cdclk_vco(dev_priv, vco);
6243 }
6244
6245 static void
6246 skl_dpll0_disable(struct drm_i915_private *dev_priv)
6247 {
6248 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
6249 if (intel_wait_for_register(dev_priv,
6250 LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
6251 1))
6252 DRM_ERROR("Couldn't disable DPLL0\n");
6253
6254 dev_priv->cdclk_pll.vco = 0;
6255 }
6256
6257 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
6258 {
6259 int ret;
6260 u32 val;
6261
6262 /* inform PCU we want to change CDCLK */
6263 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
6264 mutex_lock(&dev_priv->rps.hw_lock);
6265 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
6266 mutex_unlock(&dev_priv->rps.hw_lock);
6267
6268 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
6269 }
6270
6271 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
6272 {
6273 return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0;
6274 }
6275
6276 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
6277 {
6278 u32 freq_select, pcu_ack;
6279
6280 WARN_ON((cdclk == 24000) != (vco == 0));
6281
6282 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
6283
6284 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
6285 DRM_ERROR("failed to inform PCU about cdclk change\n");
6286 return;
6287 }
6288
6289 /* set CDCLK_CTL */
6290 switch (cdclk) {
6291 case 450000:
6292 case 432000:
6293 freq_select = CDCLK_FREQ_450_432;
6294 pcu_ack = 1;
6295 break;
6296 case 540000:
6297 freq_select = CDCLK_FREQ_540;
6298 pcu_ack = 2;
6299 break;
6300 case 308571:
6301 case 337500:
6302 default:
6303 freq_select = CDCLK_FREQ_337_308;
6304 pcu_ack = 0;
6305 break;
6306 case 617143:
6307 case 675000:
6308 freq_select = CDCLK_FREQ_675_617;
6309 pcu_ack = 3;
6310 break;
6311 }
6312
6313 if (dev_priv->cdclk_pll.vco != 0 &&
6314 dev_priv->cdclk_pll.vco != vco)
6315 skl_dpll0_disable(dev_priv);
6316
6317 if (dev_priv->cdclk_pll.vco != vco)
6318 skl_dpll0_enable(dev_priv, vco);
6319
6320 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
6321 POSTING_READ(CDCLK_CTL);
6322
6323 /* inform PCU of the change */
6324 mutex_lock(&dev_priv->rps.hw_lock);
6325 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
6326 mutex_unlock(&dev_priv->rps.hw_lock);
6327
6328 intel_update_cdclk(dev_priv);
6329 }
6330
6331 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
6332
6333 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
6334 {
6335 skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
6336 }
6337
6338 void skl_init_cdclk(struct drm_i915_private *dev_priv)
6339 {
6340 int cdclk, vco;
6341
6342 skl_sanitize_cdclk(dev_priv);
6343
6344 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
6345 /*
6346 * Use the current vco as our initial
6347 * guess as to what the preferred vco is.
6348 */
6349 if (dev_priv->skl_preferred_vco_freq == 0)
6350 skl_set_preferred_cdclk_vco(dev_priv,
6351 dev_priv->cdclk_pll.vco);
6352 return;
6353 }
6354
6355 vco = dev_priv->skl_preferred_vco_freq;
6356 if (vco == 0)
6357 vco = 8100000;
6358 cdclk = skl_calc_cdclk(0, vco);
6359
6360 skl_set_cdclk(dev_priv, cdclk, vco);
6361 }
6362
6363 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
6364 {
6365 uint32_t cdctl, expected;
6366
6367 /*
6368 * check if the pre-os intialized the display
6369 * There is SWF18 scratchpad register defined which is set by the
6370 * pre-os which can be used by the OS drivers to check the status
6371 */
6372 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
6373 goto sanitize;
6374
6375 intel_update_cdclk(dev_priv);
6376 /* Is PLL enabled and locked ? */
6377 if (dev_priv->cdclk_pll.vco == 0 ||
6378 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6379 goto sanitize;
6380
6381 /* DPLL okay; verify the cdclock
6382 *
6383 * Noticed in some instances that the freq selection is correct but
6384 * decimal part is programmed wrong from BIOS where pre-os does not
6385 * enable display. Verify the same as well.
6386 */
6387 cdctl = I915_READ(CDCLK_CTL);
6388 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
6389 skl_cdclk_decimal(dev_priv->cdclk_freq);
6390 if (cdctl == expected)
6391 /* All well; nothing to sanitize */
6392 return;
6393
6394 sanitize:
6395 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6396
6397 /* force cdclk programming */
6398 dev_priv->cdclk_freq = 0;
6399 /* force full PLL disable + enable */
6400 dev_priv->cdclk_pll.vco = -1;
6401 }
6402
6403 /* Adjust CDclk dividers to allow high res or save power if possible */
6404 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
6405 {
6406 struct drm_i915_private *dev_priv = to_i915(dev);
6407 u32 val, cmd;
6408
6409 WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv)
6410 != dev_priv->cdclk_freq);
6411
6412 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
6413 cmd = 2;
6414 else if (cdclk == 266667)
6415 cmd = 1;
6416 else
6417 cmd = 0;
6418
6419 mutex_lock(&dev_priv->rps.hw_lock);
6420 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6421 val &= ~DSPFREQGUAR_MASK;
6422 val |= (cmd << DSPFREQGUAR_SHIFT);
6423 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6424 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6425 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
6426 50)) {
6427 DRM_ERROR("timed out waiting for CDclk change\n");
6428 }
6429 mutex_unlock(&dev_priv->rps.hw_lock);
6430
6431 mutex_lock(&dev_priv->sb_lock);
6432
6433 if (cdclk == 400000) {
6434 u32 divider;
6435
6436 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6437
6438 /* adjust cdclk divider */
6439 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6440 val &= ~CCK_FREQUENCY_VALUES;
6441 val |= divider;
6442 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
6443
6444 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
6445 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
6446 50))
6447 DRM_ERROR("timed out waiting for CDclk change\n");
6448 }
6449
6450 /* adjust self-refresh exit latency value */
6451 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
6452 val &= ~0x7f;
6453
6454 /*
6455 * For high bandwidth configs, we set a higher latency in the bunit
6456 * so that the core display fetch happens in time to avoid underruns.
6457 */
6458 if (cdclk == 400000)
6459 val |= 4500 / 250; /* 4.5 usec */
6460 else
6461 val |= 3000 / 250; /* 3.0 usec */
6462 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
6463
6464 mutex_unlock(&dev_priv->sb_lock);
6465
6466 intel_update_cdclk(dev_priv);
6467 }
6468
6469 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
6470 {
6471 struct drm_i915_private *dev_priv = to_i915(dev);
6472 u32 val, cmd;
6473
6474 WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv)
6475 != dev_priv->cdclk_freq);
6476
6477 switch (cdclk) {
6478 case 333333:
6479 case 320000:
6480 case 266667:
6481 case 200000:
6482 break;
6483 default:
6484 MISSING_CASE(cdclk);
6485 return;
6486 }
6487
6488 /*
6489 * Specs are full of misinformation, but testing on actual
6490 * hardware has shown that we just need to write the desired
6491 * CCK divider into the Punit register.
6492 */
6493 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6494
6495 mutex_lock(&dev_priv->rps.hw_lock);
6496 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6497 val &= ~DSPFREQGUAR_MASK_CHV;
6498 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6499 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6500 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6501 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6502 50)) {
6503 DRM_ERROR("timed out waiting for CDclk change\n");
6504 }
6505 mutex_unlock(&dev_priv->rps.hw_lock);
6506
6507 intel_update_cdclk(dev_priv);
6508 }
6509
6510 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6511 int max_pixclk)
6512 {
6513 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6514 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6515
6516 /*
6517 * Really only a few cases to deal with, as only 4 CDclks are supported:
6518 * 200MHz
6519 * 267MHz
6520 * 320/333MHz (depends on HPLL freq)
6521 * 400MHz (VLV only)
6522 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6523 * of the lower bin and adjust if needed.
6524 *
6525 * We seem to get an unstable or solid color picture at 200MHz.
6526 * Not sure what's wrong. For now use 200MHz only when all pipes
6527 * are off.
6528 */
6529 if (!IS_CHERRYVIEW(dev_priv) &&
6530 max_pixclk > freq_320*limit/100)
6531 return 400000;
6532 else if (max_pixclk > 266667*limit/100)
6533 return freq_320;
6534 else if (max_pixclk > 0)
6535 return 266667;
6536 else
6537 return 200000;
6538 }
6539
6540 static int bxt_calc_cdclk(int max_pixclk)
6541 {
6542 if (max_pixclk > 576000)
6543 return 624000;
6544 else if (max_pixclk > 384000)
6545 return 576000;
6546 else if (max_pixclk > 288000)
6547 return 384000;
6548 else if (max_pixclk > 144000)
6549 return 288000;
6550 else
6551 return 144000;
6552 }
6553
6554 /* Compute the max pixel clock for new configuration. */
6555 static int intel_mode_max_pixclk(struct drm_device *dev,
6556 struct drm_atomic_state *state)
6557 {
6558 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6559 struct drm_i915_private *dev_priv = to_i915(dev);
6560 struct drm_crtc *crtc;
6561 struct drm_crtc_state *crtc_state;
6562 unsigned max_pixclk = 0, i;
6563 enum pipe pipe;
6564
6565 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6566 sizeof(intel_state->min_pixclk));
6567
6568 for_each_crtc_in_state(state, crtc, crtc_state, i) {
6569 int pixclk = 0;
6570
6571 if (crtc_state->enable)
6572 pixclk = crtc_state->adjusted_mode.crtc_clock;
6573
6574 intel_state->min_pixclk[i] = pixclk;
6575 }
6576
6577 for_each_pipe(dev_priv, pipe)
6578 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6579
6580 return max_pixclk;
6581 }
6582
6583 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6584 {
6585 struct drm_device *dev = state->dev;
6586 struct drm_i915_private *dev_priv = to_i915(dev);
6587 int max_pixclk = intel_mode_max_pixclk(dev, state);
6588 struct intel_atomic_state *intel_state =
6589 to_intel_atomic_state(state);
6590
6591 intel_state->cdclk = intel_state->dev_cdclk =
6592 valleyview_calc_cdclk(dev_priv, max_pixclk);
6593
6594 if (!intel_state->active_crtcs)
6595 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6596
6597 return 0;
6598 }
6599
6600 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6601 {
6602 int max_pixclk = ilk_max_pixel_rate(state);
6603 struct intel_atomic_state *intel_state =
6604 to_intel_atomic_state(state);
6605
6606 intel_state->cdclk = intel_state->dev_cdclk =
6607 bxt_calc_cdclk(max_pixclk);
6608
6609 if (!intel_state->active_crtcs)
6610 intel_state->dev_cdclk = bxt_calc_cdclk(0);
6611
6612 return 0;
6613 }
6614
6615 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6616 {
6617 unsigned int credits, default_credits;
6618
6619 if (IS_CHERRYVIEW(dev_priv))
6620 default_credits = PFI_CREDIT(12);
6621 else
6622 default_credits = PFI_CREDIT(8);
6623
6624 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6625 /* CHV suggested value is 31 or 63 */
6626 if (IS_CHERRYVIEW(dev_priv))
6627 credits = PFI_CREDIT_63;
6628 else
6629 credits = PFI_CREDIT(15);
6630 } else {
6631 credits = default_credits;
6632 }
6633
6634 /*
6635 * WA - write default credits before re-programming
6636 * FIXME: should we also set the resend bit here?
6637 */
6638 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6639 default_credits);
6640
6641 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6642 credits | PFI_CREDIT_RESEND);
6643
6644 /*
6645 * FIXME is this guaranteed to clear
6646 * immediately or should we poll for it?
6647 */
6648 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6649 }
6650
6651 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6652 {
6653 struct drm_device *dev = old_state->dev;
6654 struct drm_i915_private *dev_priv = to_i915(dev);
6655 struct intel_atomic_state *old_intel_state =
6656 to_intel_atomic_state(old_state);
6657 unsigned req_cdclk = old_intel_state->dev_cdclk;
6658
6659 /*
6660 * FIXME: We can end up here with all power domains off, yet
6661 * with a CDCLK frequency other than the minimum. To account
6662 * for this take the PIPE-A power domain, which covers the HW
6663 * blocks needed for the following programming. This can be
6664 * removed once it's guaranteed that we get here either with
6665 * the minimum CDCLK set, or the required power domains
6666 * enabled.
6667 */
6668 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6669
6670 if (IS_CHERRYVIEW(dev_priv))
6671 cherryview_set_cdclk(dev, req_cdclk);
6672 else
6673 valleyview_set_cdclk(dev, req_cdclk);
6674
6675 vlv_program_pfi_credits(dev_priv);
6676
6677 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6678 }
6679
6680 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6681 struct drm_atomic_state *old_state)
6682 {
6683 struct drm_crtc *crtc = pipe_config->base.crtc;
6684 struct drm_device *dev = crtc->dev;
6685 struct drm_i915_private *dev_priv = to_i915(dev);
6686 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6687 int pipe = intel_crtc->pipe;
6688
6689 if (WARN_ON(intel_crtc->active))
6690 return;
6691
6692 if (intel_crtc_has_dp_encoder(intel_crtc->config))
6693 intel_dp_set_m_n(intel_crtc, M1_N1);
6694
6695 intel_set_pipe_timings(intel_crtc);
6696 intel_set_pipe_src_size(intel_crtc);
6697
6698 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
6699 struct drm_i915_private *dev_priv = to_i915(dev);
6700
6701 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6702 I915_WRITE(CHV_CANVAS(pipe), 0);
6703 }
6704
6705 i9xx_set_pipeconf(intel_crtc);
6706
6707 intel_crtc->active = true;
6708
6709 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6710
6711 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6712
6713 if (IS_CHERRYVIEW(dev_priv)) {
6714 chv_prepare_pll(intel_crtc, intel_crtc->config);
6715 chv_enable_pll(intel_crtc, intel_crtc->config);
6716 } else {
6717 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6718 vlv_enable_pll(intel_crtc, intel_crtc->config);
6719 }
6720
6721 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6722
6723 i9xx_pfit_enable(intel_crtc);
6724
6725 intel_color_load_luts(&pipe_config->base);
6726
6727 intel_update_watermarks(intel_crtc);
6728 intel_enable_pipe(intel_crtc);
6729
6730 assert_vblank_disabled(crtc);
6731 drm_crtc_vblank_on(crtc);
6732
6733 intel_encoders_enable(crtc, pipe_config, old_state);
6734 }
6735
6736 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6737 {
6738 struct drm_device *dev = crtc->base.dev;
6739 struct drm_i915_private *dev_priv = to_i915(dev);
6740
6741 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6742 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6743 }
6744
6745 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6746 struct drm_atomic_state *old_state)
6747 {
6748 struct drm_crtc *crtc = pipe_config->base.crtc;
6749 struct drm_device *dev = crtc->dev;
6750 struct drm_i915_private *dev_priv = to_i915(dev);
6751 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6752 enum pipe pipe = intel_crtc->pipe;
6753
6754 if (WARN_ON(intel_crtc->active))
6755 return;
6756
6757 i9xx_set_pll_dividers(intel_crtc);
6758
6759 if (intel_crtc_has_dp_encoder(intel_crtc->config))
6760 intel_dp_set_m_n(intel_crtc, M1_N1);
6761
6762 intel_set_pipe_timings(intel_crtc);
6763 intel_set_pipe_src_size(intel_crtc);
6764
6765 i9xx_set_pipeconf(intel_crtc);
6766
6767 intel_crtc->active = true;
6768
6769 if (!IS_GEN2(dev_priv))
6770 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6771
6772 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6773
6774 i9xx_enable_pll(intel_crtc);
6775
6776 i9xx_pfit_enable(intel_crtc);
6777
6778 intel_color_load_luts(&pipe_config->base);
6779
6780 intel_update_watermarks(intel_crtc);
6781 intel_enable_pipe(intel_crtc);
6782
6783 assert_vblank_disabled(crtc);
6784 drm_crtc_vblank_on(crtc);
6785
6786 intel_encoders_enable(crtc, pipe_config, old_state);
6787 }
6788
6789 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6790 {
6791 struct drm_device *dev = crtc->base.dev;
6792 struct drm_i915_private *dev_priv = to_i915(dev);
6793
6794 if (!crtc->config->gmch_pfit.control)
6795 return;
6796
6797 assert_pipe_disabled(dev_priv, crtc->pipe);
6798
6799 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6800 I915_READ(PFIT_CONTROL));
6801 I915_WRITE(PFIT_CONTROL, 0);
6802 }
6803
6804 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6805 struct drm_atomic_state *old_state)
6806 {
6807 struct drm_crtc *crtc = old_crtc_state->base.crtc;
6808 struct drm_device *dev = crtc->dev;
6809 struct drm_i915_private *dev_priv = to_i915(dev);
6810 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6811 int pipe = intel_crtc->pipe;
6812
6813 /*
6814 * On gen2 planes are double buffered but the pipe isn't, so we must
6815 * wait for planes to fully turn off before disabling the pipe.
6816 */
6817 if (IS_GEN2(dev_priv))
6818 intel_wait_for_vblank(dev_priv, pipe);
6819
6820 intel_encoders_disable(crtc, old_crtc_state, old_state);
6821
6822 drm_crtc_vblank_off(crtc);
6823 assert_vblank_disabled(crtc);
6824
6825 intel_disable_pipe(intel_crtc);
6826
6827 i9xx_pfit_disable(intel_crtc);
6828
6829 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6830
6831 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6832 if (IS_CHERRYVIEW(dev_priv))
6833 chv_disable_pll(dev_priv, pipe);
6834 else if (IS_VALLEYVIEW(dev_priv))
6835 vlv_disable_pll(dev_priv, pipe);
6836 else
6837 i9xx_disable_pll(intel_crtc);
6838 }
6839
6840 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6841
6842 if (!IS_GEN2(dev_priv))
6843 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6844 }
6845
6846 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6847 {
6848 struct intel_encoder *encoder;
6849 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6850 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6851 enum intel_display_power_domain domain;
6852 unsigned long domains;
6853 struct drm_atomic_state *state;
6854 struct intel_crtc_state *crtc_state;
6855 int ret;
6856
6857 if (!intel_crtc->active)
6858 return;
6859
6860 if (to_intel_plane_state(crtc->primary->state)->base.visible) {
6861 WARN_ON(intel_crtc->flip_work);
6862
6863 intel_pre_disable_primary_noatomic(crtc);
6864
6865 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6866 to_intel_plane_state(crtc->primary->state)->base.visible = false;
6867 }
6868
6869 state = drm_atomic_state_alloc(crtc->dev);
6870 state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
6871
6872 /* Everything's already locked, -EDEADLK can't happen. */
6873 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6874 ret = drm_atomic_add_affected_connectors(state, crtc);
6875
6876 WARN_ON(IS_ERR(crtc_state) || ret);
6877
6878 dev_priv->display.crtc_disable(crtc_state, state);
6879
6880 drm_atomic_state_put(state);
6881
6882 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6883 crtc->base.id, crtc->name);
6884
6885 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6886 crtc->state->active = false;
6887 intel_crtc->active = false;
6888 crtc->enabled = false;
6889 crtc->state->connector_mask = 0;
6890 crtc->state->encoder_mask = 0;
6891
6892 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6893 encoder->base.crtc = NULL;
6894
6895 intel_fbc_disable(intel_crtc);
6896 intel_update_watermarks(intel_crtc);
6897 intel_disable_shared_dpll(intel_crtc);
6898
6899 domains = intel_crtc->enabled_power_domains;
6900 for_each_power_domain(domain, domains)
6901 intel_display_power_put(dev_priv, domain);
6902 intel_crtc->enabled_power_domains = 0;
6903
6904 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6905 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6906 }
6907
6908 /*
6909 * turn all crtc's off, but do not adjust state
6910 * This has to be paired with a call to intel_modeset_setup_hw_state.
6911 */
6912 int intel_display_suspend(struct drm_device *dev)
6913 {
6914 struct drm_i915_private *dev_priv = to_i915(dev);
6915 struct drm_atomic_state *state;
6916 int ret;
6917
6918 state = drm_atomic_helper_suspend(dev);
6919 ret = PTR_ERR_OR_ZERO(state);
6920 if (ret)
6921 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6922 else
6923 dev_priv->modeset_restore_state = state;
6924 return ret;
6925 }
6926
6927 void intel_encoder_destroy(struct drm_encoder *encoder)
6928 {
6929 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6930
6931 drm_encoder_cleanup(encoder);
6932 kfree(intel_encoder);
6933 }
6934
6935 /* Cross check the actual hw state with our own modeset state tracking (and it's
6936 * internal consistency). */
6937 static void intel_connector_verify_state(struct intel_connector *connector)
6938 {
6939 struct drm_crtc *crtc = connector->base.state->crtc;
6940
6941 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6942 connector->base.base.id,
6943 connector->base.name);
6944
6945 if (connector->get_hw_state(connector)) {
6946 struct intel_encoder *encoder = connector->encoder;
6947 struct drm_connector_state *conn_state = connector->base.state;
6948
6949 I915_STATE_WARN(!crtc,
6950 "connector enabled without attached crtc\n");
6951
6952 if (!crtc)
6953 return;
6954
6955 I915_STATE_WARN(!crtc->state->active,
6956 "connector is active, but attached crtc isn't\n");
6957
6958 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6959 return;
6960
6961 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6962 "atomic encoder doesn't match attached encoder\n");
6963
6964 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6965 "attached encoder crtc differs from connector crtc\n");
6966 } else {
6967 I915_STATE_WARN(crtc && crtc->state->active,
6968 "attached crtc is active, but connector isn't\n");
6969 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6970 "best encoder set without crtc!\n");
6971 }
6972 }
6973
6974 int intel_connector_init(struct intel_connector *connector)
6975 {
6976 drm_atomic_helper_connector_reset(&connector->base);
6977
6978 if (!connector->base.state)
6979 return -ENOMEM;
6980
6981 return 0;
6982 }
6983
6984 struct intel_connector *intel_connector_alloc(void)
6985 {
6986 struct intel_connector *connector;
6987
6988 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6989 if (!connector)
6990 return NULL;
6991
6992 if (intel_connector_init(connector) < 0) {
6993 kfree(connector);
6994 return NULL;
6995 }
6996
6997 return connector;
6998 }
6999
7000 /* Simple connector->get_hw_state implementation for encoders that support only
7001 * one connector and no cloning and hence the encoder state determines the state
7002 * of the connector. */
7003 bool intel_connector_get_hw_state(struct intel_connector *connector)
7004 {
7005 enum pipe pipe = 0;
7006 struct intel_encoder *encoder = connector->encoder;
7007
7008 return encoder->get_hw_state(encoder, &pipe);
7009 }
7010
7011 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7012 {
7013 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
7014 return crtc_state->fdi_lanes;
7015
7016 return 0;
7017 }
7018
7019 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7020 struct intel_crtc_state *pipe_config)
7021 {
7022 struct drm_i915_private *dev_priv = to_i915(dev);
7023 struct drm_atomic_state *state = pipe_config->base.state;
7024 struct intel_crtc *other_crtc;
7025 struct intel_crtc_state *other_crtc_state;
7026
7027 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7028 pipe_name(pipe), pipe_config->fdi_lanes);
7029 if (pipe_config->fdi_lanes > 4) {
7030 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7031 pipe_name(pipe), pipe_config->fdi_lanes);
7032 return -EINVAL;
7033 }
7034
7035 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7036 if (pipe_config->fdi_lanes > 2) {
7037 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7038 pipe_config->fdi_lanes);
7039 return -EINVAL;
7040 } else {
7041 return 0;
7042 }
7043 }
7044
7045 if (INTEL_INFO(dev_priv)->num_pipes == 2)
7046 return 0;
7047
7048 /* Ivybridge 3 pipe is really complicated */
7049 switch (pipe) {
7050 case PIPE_A:
7051 return 0;
7052 case PIPE_B:
7053 if (pipe_config->fdi_lanes <= 2)
7054 return 0;
7055
7056 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
7057 other_crtc_state =
7058 intel_atomic_get_crtc_state(state, other_crtc);
7059 if (IS_ERR(other_crtc_state))
7060 return PTR_ERR(other_crtc_state);
7061
7062 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7063 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7064 pipe_name(pipe), pipe_config->fdi_lanes);
7065 return -EINVAL;
7066 }
7067 return 0;
7068 case PIPE_C:
7069 if (pipe_config->fdi_lanes > 2) {
7070 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7071 pipe_name(pipe), pipe_config->fdi_lanes);
7072 return -EINVAL;
7073 }
7074
7075 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
7076 other_crtc_state =
7077 intel_atomic_get_crtc_state(state, other_crtc);
7078 if (IS_ERR(other_crtc_state))
7079 return PTR_ERR(other_crtc_state);
7080
7081 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7082 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7083 return -EINVAL;
7084 }
7085 return 0;
7086 default:
7087 BUG();
7088 }
7089 }
7090
7091 #define RETRY 1
7092 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
7093 struct intel_crtc_state *pipe_config)
7094 {
7095 struct drm_device *dev = intel_crtc->base.dev;
7096 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7097 int lane, link_bw, fdi_dotclock, ret;
7098 bool needs_recompute = false;
7099
7100 retry:
7101 /* FDI is a binary signal running at ~2.7GHz, encoding
7102 * each output octet as 10 bits. The actual frequency
7103 * is stored as a divider into a 100MHz clock, and the
7104 * mode pixel clock is stored in units of 1KHz.
7105 * Hence the bw of each lane in terms of the mode signal
7106 * is:
7107 */
7108 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
7109
7110 fdi_dotclock = adjusted_mode->crtc_clock;
7111
7112 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7113 pipe_config->pipe_bpp);
7114
7115 pipe_config->fdi_lanes = lane;
7116
7117 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7118 link_bw, &pipe_config->fdi_m_n);
7119
7120 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7121 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7122 pipe_config->pipe_bpp -= 2*3;
7123 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7124 pipe_config->pipe_bpp);
7125 needs_recompute = true;
7126 pipe_config->bw_constrained = true;
7127
7128 goto retry;
7129 }
7130
7131 if (needs_recompute)
7132 return RETRY;
7133
7134 return ret;
7135 }
7136
7137 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
7138 struct intel_crtc_state *pipe_config)
7139 {
7140 if (pipe_config->pipe_bpp > 24)
7141 return false;
7142
7143 /* HSW can handle pixel rate up to cdclk? */
7144 if (IS_HASWELL(dev_priv))
7145 return true;
7146
7147 /*
7148 * We compare against max which means we must take
7149 * the increased cdclk requirement into account when
7150 * calculating the new cdclk.
7151 *
7152 * Should measure whether using a lower cdclk w/o IPS
7153 */
7154 return ilk_pipe_pixel_rate(pipe_config) <=
7155 dev_priv->max_cdclk_freq * 95 / 100;
7156 }
7157
7158 static void hsw_compute_ips_config(struct intel_crtc *crtc,
7159 struct intel_crtc_state *pipe_config)
7160 {
7161 struct drm_device *dev = crtc->base.dev;
7162 struct drm_i915_private *dev_priv = to_i915(dev);
7163
7164 pipe_config->ips_enabled = i915.enable_ips &&
7165 hsw_crtc_supports_ips(crtc) &&
7166 pipe_config_supports_ips(dev_priv, pipe_config);
7167 }
7168
7169 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7170 {
7171 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7172
7173 /* GDG double wide on either pipe, otherwise pipe A only */
7174 return INTEL_INFO(dev_priv)->gen < 4 &&
7175 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7176 }
7177
7178 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7179 struct intel_crtc_state *pipe_config)
7180 {
7181 struct drm_device *dev = crtc->base.dev;
7182 struct drm_i915_private *dev_priv = to_i915(dev);
7183 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7184 int clock_limit = dev_priv->max_dotclk_freq;
7185
7186 if (INTEL_GEN(dev_priv) < 4) {
7187 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7188
7189 /*
7190 * Enable double wide mode when the dot clock
7191 * is > 90% of the (display) core speed.
7192 */
7193 if (intel_crtc_supports_double_wide(crtc) &&
7194 adjusted_mode->crtc_clock > clock_limit) {
7195 clock_limit = dev_priv->max_dotclk_freq;
7196 pipe_config->double_wide = true;
7197 }
7198 }
7199
7200 if (adjusted_mode->crtc_clock > clock_limit) {
7201 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7202 adjusted_mode->crtc_clock, clock_limit,
7203 yesno(pipe_config->double_wide));
7204 return -EINVAL;
7205 }
7206
7207 /*
7208 * Pipe horizontal size must be even in:
7209 * - DVO ganged mode
7210 * - LVDS dual channel mode
7211 * - Double wide pipe
7212 */
7213 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7214 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
7215 pipe_config->pipe_src_w &= ~1;
7216
7217 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7218 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7219 */
7220 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
7221 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7222 return -EINVAL;
7223
7224 if (HAS_IPS(dev_priv))
7225 hsw_compute_ips_config(crtc, pipe_config);
7226
7227 if (pipe_config->has_pch_encoder)
7228 return ironlake_fdi_compute_config(crtc, pipe_config);
7229
7230 return 0;
7231 }
7232
7233 static int skylake_get_display_clock_speed(struct drm_i915_private *dev_priv)
7234 {
7235 u32 cdctl;
7236
7237 skl_dpll0_update(dev_priv);
7238
7239 if (dev_priv->cdclk_pll.vco == 0)
7240 return dev_priv->cdclk_pll.ref;
7241
7242 cdctl = I915_READ(CDCLK_CTL);
7243
7244 if (dev_priv->cdclk_pll.vco == 8640000) {
7245 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7246 case CDCLK_FREQ_450_432:
7247 return 432000;
7248 case CDCLK_FREQ_337_308:
7249 return 308571;
7250 case CDCLK_FREQ_540:
7251 return 540000;
7252 case CDCLK_FREQ_675_617:
7253 return 617143;
7254 default:
7255 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7256 }
7257 } else {
7258 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7259 case CDCLK_FREQ_450_432:
7260 return 450000;
7261 case CDCLK_FREQ_337_308:
7262 return 337500;
7263 case CDCLK_FREQ_540:
7264 return 540000;
7265 case CDCLK_FREQ_675_617:
7266 return 675000;
7267 default:
7268 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7269 }
7270 }
7271
7272 return dev_priv->cdclk_pll.ref;
7273 }
7274
7275 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
7276 {
7277 u32 val;
7278
7279 dev_priv->cdclk_pll.ref = 19200;
7280 dev_priv->cdclk_pll.vco = 0;
7281
7282 val = I915_READ(BXT_DE_PLL_ENABLE);
7283 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
7284 return;
7285
7286 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
7287 return;
7288
7289 val = I915_READ(BXT_DE_PLL_CTL);
7290 dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
7291 dev_priv->cdclk_pll.ref;
7292 }
7293
7294 static int broxton_get_display_clock_speed(struct drm_i915_private *dev_priv)
7295 {
7296 u32 divider;
7297 int div, vco;
7298
7299 bxt_de_pll_update(dev_priv);
7300
7301 vco = dev_priv->cdclk_pll.vco;
7302 if (vco == 0)
7303 return dev_priv->cdclk_pll.ref;
7304
7305 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
7306
7307 switch (divider) {
7308 case BXT_CDCLK_CD2X_DIV_SEL_1:
7309 div = 2;
7310 break;
7311 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
7312 div = 3;
7313 break;
7314 case BXT_CDCLK_CD2X_DIV_SEL_2:
7315 div = 4;
7316 break;
7317 case BXT_CDCLK_CD2X_DIV_SEL_4:
7318 div = 8;
7319 break;
7320 default:
7321 MISSING_CASE(divider);
7322 return dev_priv->cdclk_pll.ref;
7323 }
7324
7325 return DIV_ROUND_CLOSEST(vco, div);
7326 }
7327
7328 static int broadwell_get_display_clock_speed(struct drm_i915_private *dev_priv)
7329 {
7330 uint32_t lcpll = I915_READ(LCPLL_CTL);
7331 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7332
7333 if (lcpll & LCPLL_CD_SOURCE_FCLK)
7334 return 800000;
7335 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7336 return 450000;
7337 else if (freq == LCPLL_CLK_FREQ_450)
7338 return 450000;
7339 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
7340 return 540000;
7341 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
7342 return 337500;
7343 else
7344 return 675000;
7345 }
7346
7347 static int haswell_get_display_clock_speed(struct drm_i915_private *dev_priv)
7348 {
7349 uint32_t lcpll = I915_READ(LCPLL_CTL);
7350 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7351
7352 if (lcpll & LCPLL_CD_SOURCE_FCLK)
7353 return 800000;
7354 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7355 return 450000;
7356 else if (freq == LCPLL_CLK_FREQ_450)
7357 return 450000;
7358 else if (IS_HSW_ULT(dev_priv))
7359 return 337500;
7360 else
7361 return 540000;
7362 }
7363
7364 static int valleyview_get_display_clock_speed(struct drm_i915_private *dev_priv)
7365 {
7366 return vlv_get_cck_clock_hpll(dev_priv, "cdclk",
7367 CCK_DISPLAY_CLOCK_CONTROL);
7368 }
7369
7370 static int ilk_get_display_clock_speed(struct drm_i915_private *dev_priv)
7371 {
7372 return 450000;
7373 }
7374
7375 static int i945_get_display_clock_speed(struct drm_i915_private *dev_priv)
7376 {
7377 return 400000;
7378 }
7379
7380 static int i915_get_display_clock_speed(struct drm_i915_private *dev_priv)
7381 {
7382 return 333333;
7383 }
7384
7385 static int i9xx_misc_get_display_clock_speed(struct drm_i915_private *dev_priv)
7386 {
7387 return 200000;
7388 }
7389
7390 static int pnv_get_display_clock_speed(struct drm_i915_private *dev_priv)
7391 {
7392 struct pci_dev *pdev = dev_priv->drm.pdev;
7393 u16 gcfgc = 0;
7394
7395 pci_read_config_word(pdev, GCFGC, &gcfgc);
7396
7397 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7398 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
7399 return 266667;
7400 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
7401 return 333333;
7402 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
7403 return 444444;
7404 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
7405 return 200000;
7406 default:
7407 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
7408 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
7409 return 133333;
7410 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
7411 return 166667;
7412 }
7413 }
7414
7415 static int i915gm_get_display_clock_speed(struct drm_i915_private *dev_priv)
7416 {
7417 struct pci_dev *pdev = dev_priv->drm.pdev;
7418 u16 gcfgc = 0;
7419
7420 pci_read_config_word(pdev, GCFGC, &gcfgc);
7421
7422 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
7423 return 133333;
7424 else {
7425 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7426 case GC_DISPLAY_CLOCK_333_MHZ:
7427 return 333333;
7428 default:
7429 case GC_DISPLAY_CLOCK_190_200_MHZ:
7430 return 190000;
7431 }
7432 }
7433 }
7434
7435 static int i865_get_display_clock_speed(struct drm_i915_private *dev_priv)
7436 {
7437 return 266667;
7438 }
7439
7440 static int i85x_get_display_clock_speed(struct drm_i915_private *dev_priv)
7441 {
7442 struct pci_dev *pdev = dev_priv->drm.pdev;
7443 u16 hpllcc = 0;
7444
7445 /*
7446 * 852GM/852GMV only supports 133 MHz and the HPLLCC
7447 * encoding is different :(
7448 * FIXME is this the right way to detect 852GM/852GMV?
7449 */
7450 if (pdev->revision == 0x1)
7451 return 133333;
7452
7453 pci_bus_read_config_word(pdev->bus,
7454 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
7455
7456 /* Assume that the hardware is in the high speed state. This
7457 * should be the default.
7458 */
7459 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
7460 case GC_CLOCK_133_200:
7461 case GC_CLOCK_133_200_2:
7462 case GC_CLOCK_100_200:
7463 return 200000;
7464 case GC_CLOCK_166_250:
7465 return 250000;
7466 case GC_CLOCK_100_133:
7467 return 133333;
7468 case GC_CLOCK_133_266:
7469 case GC_CLOCK_133_266_2:
7470 case GC_CLOCK_166_266:
7471 return 266667;
7472 }
7473
7474 /* Shouldn't happen */
7475 return 0;
7476 }
7477
7478 static int i830_get_display_clock_speed(struct drm_i915_private *dev_priv)
7479 {
7480 return 133333;
7481 }
7482
7483 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
7484 {
7485 static const unsigned int blb_vco[8] = {
7486 [0] = 3200000,
7487 [1] = 4000000,
7488 [2] = 5333333,
7489 [3] = 4800000,
7490 [4] = 6400000,
7491 };
7492 static const unsigned int pnv_vco[8] = {
7493 [0] = 3200000,
7494 [1] = 4000000,
7495 [2] = 5333333,
7496 [3] = 4800000,
7497 [4] = 2666667,
7498 };
7499 static const unsigned int cl_vco[8] = {
7500 [0] = 3200000,
7501 [1] = 4000000,
7502 [2] = 5333333,
7503 [3] = 6400000,
7504 [4] = 3333333,
7505 [5] = 3566667,
7506 [6] = 4266667,
7507 };
7508 static const unsigned int elk_vco[8] = {
7509 [0] = 3200000,
7510 [1] = 4000000,
7511 [2] = 5333333,
7512 [3] = 4800000,
7513 };
7514 static const unsigned int ctg_vco[8] = {
7515 [0] = 3200000,
7516 [1] = 4000000,
7517 [2] = 5333333,
7518 [3] = 6400000,
7519 [4] = 2666667,
7520 [5] = 4266667,
7521 };
7522 const unsigned int *vco_table;
7523 unsigned int vco;
7524 uint8_t tmp = 0;
7525
7526 /* FIXME other chipsets? */
7527 if (IS_GM45(dev_priv))
7528 vco_table = ctg_vco;
7529 else if (IS_G4X(dev_priv))
7530 vco_table = elk_vco;
7531 else if (IS_CRESTLINE(dev_priv))
7532 vco_table = cl_vco;
7533 else if (IS_PINEVIEW(dev_priv))
7534 vco_table = pnv_vco;
7535 else if (IS_G33(dev_priv))
7536 vco_table = blb_vco;
7537 else
7538 return 0;
7539
7540 tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
7541
7542 vco = vco_table[tmp & 0x7];
7543 if (vco == 0)
7544 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7545 else
7546 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7547
7548 return vco;
7549 }
7550
7551 static int gm45_get_display_clock_speed(struct drm_i915_private *dev_priv)
7552 {
7553 struct pci_dev *pdev = dev_priv->drm.pdev;
7554 unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7555 uint16_t tmp = 0;
7556
7557 pci_read_config_word(pdev, GCFGC, &tmp);
7558
7559 cdclk_sel = (tmp >> 12) & 0x1;
7560
7561 switch (vco) {
7562 case 2666667:
7563 case 4000000:
7564 case 5333333:
7565 return cdclk_sel ? 333333 : 222222;
7566 case 3200000:
7567 return cdclk_sel ? 320000 : 228571;
7568 default:
7569 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7570 return 222222;
7571 }
7572 }
7573
7574 static int i965gm_get_display_clock_speed(struct drm_i915_private *dev_priv)
7575 {
7576 struct pci_dev *pdev = dev_priv->drm.pdev;
7577 static const uint8_t div_3200[] = { 16, 10, 8 };
7578 static const uint8_t div_4000[] = { 20, 12, 10 };
7579 static const uint8_t div_5333[] = { 24, 16, 14 };
7580 const uint8_t *div_table;
7581 unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7582 uint16_t tmp = 0;
7583
7584 pci_read_config_word(pdev, GCFGC, &tmp);
7585
7586 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7587
7588 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7589 goto fail;
7590
7591 switch (vco) {
7592 case 3200000:
7593 div_table = div_3200;
7594 break;
7595 case 4000000:
7596 div_table = div_4000;
7597 break;
7598 case 5333333:
7599 div_table = div_5333;
7600 break;
7601 default:
7602 goto fail;
7603 }
7604
7605 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7606
7607 fail:
7608 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7609 return 200000;
7610 }
7611
7612 static int g33_get_display_clock_speed(struct drm_i915_private *dev_priv)
7613 {
7614 struct pci_dev *pdev = dev_priv->drm.pdev;
7615 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7616 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7617 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7618 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7619 const uint8_t *div_table;
7620 unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7621 uint16_t tmp = 0;
7622
7623 pci_read_config_word(pdev, GCFGC, &tmp);
7624
7625 cdclk_sel = (tmp >> 4) & 0x7;
7626
7627 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7628 goto fail;
7629
7630 switch (vco) {
7631 case 3200000:
7632 div_table = div_3200;
7633 break;
7634 case 4000000:
7635 div_table = div_4000;
7636 break;
7637 case 4800000:
7638 div_table = div_4800;
7639 break;
7640 case 5333333:
7641 div_table = div_5333;
7642 break;
7643 default:
7644 goto fail;
7645 }
7646
7647 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7648
7649 fail:
7650 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7651 return 190476;
7652 }
7653
7654 static void
7655 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7656 {
7657 while (*num > DATA_LINK_M_N_MASK ||
7658 *den > DATA_LINK_M_N_MASK) {
7659 *num >>= 1;
7660 *den >>= 1;
7661 }
7662 }
7663
7664 static void compute_m_n(unsigned int m, unsigned int n,
7665 uint32_t *ret_m, uint32_t *ret_n)
7666 {
7667 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7668 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7669 intel_reduce_m_n_ratio(ret_m, ret_n);
7670 }
7671
7672 void
7673 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7674 int pixel_clock, int link_clock,
7675 struct intel_link_m_n *m_n)
7676 {
7677 m_n->tu = 64;
7678
7679 compute_m_n(bits_per_pixel * pixel_clock,
7680 link_clock * nlanes * 8,
7681 &m_n->gmch_m, &m_n->gmch_n);
7682
7683 compute_m_n(pixel_clock, link_clock,
7684 &m_n->link_m, &m_n->link_n);
7685 }
7686
7687 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7688 {
7689 if (i915.panel_use_ssc >= 0)
7690 return i915.panel_use_ssc != 0;
7691 return dev_priv->vbt.lvds_use_ssc
7692 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7693 }
7694
7695 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7696 {
7697 return (1 << dpll->n) << 16 | dpll->m2;
7698 }
7699
7700 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7701 {
7702 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7703 }
7704
7705 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7706 struct intel_crtc_state *crtc_state,
7707 struct dpll *reduced_clock)
7708 {
7709 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7710 u32 fp, fp2 = 0;
7711
7712 if (IS_PINEVIEW(dev_priv)) {
7713 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7714 if (reduced_clock)
7715 fp2 = pnv_dpll_compute_fp(reduced_clock);
7716 } else {
7717 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7718 if (reduced_clock)
7719 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7720 }
7721
7722 crtc_state->dpll_hw_state.fp0 = fp;
7723
7724 crtc->lowfreq_avail = false;
7725 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7726 reduced_clock) {
7727 crtc_state->dpll_hw_state.fp1 = fp2;
7728 crtc->lowfreq_avail = true;
7729 } else {
7730 crtc_state->dpll_hw_state.fp1 = fp;
7731 }
7732 }
7733
7734 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7735 pipe)
7736 {
7737 u32 reg_val;
7738
7739 /*
7740 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7741 * and set it to a reasonable value instead.
7742 */
7743 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7744 reg_val &= 0xffffff00;
7745 reg_val |= 0x00000030;
7746 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7747
7748 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7749 reg_val &= 0x8cffffff;
7750 reg_val = 0x8c000000;
7751 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7752
7753 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7754 reg_val &= 0xffffff00;
7755 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7756
7757 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7758 reg_val &= 0x00ffffff;
7759 reg_val |= 0xb0000000;
7760 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7761 }
7762
7763 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7764 struct intel_link_m_n *m_n)
7765 {
7766 struct drm_device *dev = crtc->base.dev;
7767 struct drm_i915_private *dev_priv = to_i915(dev);
7768 int pipe = crtc->pipe;
7769
7770 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7771 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7772 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7773 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7774 }
7775
7776 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7777 struct intel_link_m_n *m_n,
7778 struct intel_link_m_n *m2_n2)
7779 {
7780 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7781 int pipe = crtc->pipe;
7782 enum transcoder transcoder = crtc->config->cpu_transcoder;
7783
7784 if (INTEL_GEN(dev_priv) >= 5) {
7785 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7786 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7787 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7788 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7789 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7790 * for gen < 8) and if DRRS is supported (to make sure the
7791 * registers are not unnecessarily accessed).
7792 */
7793 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
7794 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
7795 I915_WRITE(PIPE_DATA_M2(transcoder),
7796 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7797 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7798 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7799 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7800 }
7801 } else {
7802 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7803 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7804 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7805 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7806 }
7807 }
7808
7809 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7810 {
7811 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7812
7813 if (m_n == M1_N1) {
7814 dp_m_n = &crtc->config->dp_m_n;
7815 dp_m2_n2 = &crtc->config->dp_m2_n2;
7816 } else if (m_n == M2_N2) {
7817
7818 /*
7819 * M2_N2 registers are not supported. Hence m2_n2 divider value
7820 * needs to be programmed into M1_N1.
7821 */
7822 dp_m_n = &crtc->config->dp_m2_n2;
7823 } else {
7824 DRM_ERROR("Unsupported divider value\n");
7825 return;
7826 }
7827
7828 if (crtc->config->has_pch_encoder)
7829 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7830 else
7831 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7832 }
7833
7834 static void vlv_compute_dpll(struct intel_crtc *crtc,
7835 struct intel_crtc_state *pipe_config)
7836 {
7837 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7838 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7839 if (crtc->pipe != PIPE_A)
7840 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7841
7842 /* DPLL not used with DSI, but still need the rest set up */
7843 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7844 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7845 DPLL_EXT_BUFFER_ENABLE_VLV;
7846
7847 pipe_config->dpll_hw_state.dpll_md =
7848 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7849 }
7850
7851 static void chv_compute_dpll(struct intel_crtc *crtc,
7852 struct intel_crtc_state *pipe_config)
7853 {
7854 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7855 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7856 if (crtc->pipe != PIPE_A)
7857 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7858
7859 /* DPLL not used with DSI, but still need the rest set up */
7860 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7861 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7862
7863 pipe_config->dpll_hw_state.dpll_md =
7864 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7865 }
7866
7867 static void vlv_prepare_pll(struct intel_crtc *crtc,
7868 const struct intel_crtc_state *pipe_config)
7869 {
7870 struct drm_device *dev = crtc->base.dev;
7871 struct drm_i915_private *dev_priv = to_i915(dev);
7872 enum pipe pipe = crtc->pipe;
7873 u32 mdiv;
7874 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7875 u32 coreclk, reg_val;
7876
7877 /* Enable Refclk */
7878 I915_WRITE(DPLL(pipe),
7879 pipe_config->dpll_hw_state.dpll &
7880 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7881
7882 /* No need to actually set up the DPLL with DSI */
7883 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7884 return;
7885
7886 mutex_lock(&dev_priv->sb_lock);
7887
7888 bestn = pipe_config->dpll.n;
7889 bestm1 = pipe_config->dpll.m1;
7890 bestm2 = pipe_config->dpll.m2;
7891 bestp1 = pipe_config->dpll.p1;
7892 bestp2 = pipe_config->dpll.p2;
7893
7894 /* See eDP HDMI DPIO driver vbios notes doc */
7895
7896 /* PLL B needs special handling */
7897 if (pipe == PIPE_B)
7898 vlv_pllb_recal_opamp(dev_priv, pipe);
7899
7900 /* Set up Tx target for periodic Rcomp update */
7901 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7902
7903 /* Disable target IRef on PLL */
7904 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7905 reg_val &= 0x00ffffff;
7906 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7907
7908 /* Disable fast lock */
7909 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7910
7911 /* Set idtafcrecal before PLL is enabled */
7912 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7913 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7914 mdiv |= ((bestn << DPIO_N_SHIFT));
7915 mdiv |= (1 << DPIO_K_SHIFT);
7916
7917 /*
7918 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7919 * but we don't support that).
7920 * Note: don't use the DAC post divider as it seems unstable.
7921 */
7922 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7923 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7924
7925 mdiv |= DPIO_ENABLE_CALIBRATION;
7926 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7927
7928 /* Set HBR and RBR LPF coefficients */
7929 if (pipe_config->port_clock == 162000 ||
7930 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
7931 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
7932 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7933 0x009f0003);
7934 else
7935 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7936 0x00d0000f);
7937
7938 if (intel_crtc_has_dp_encoder(pipe_config)) {
7939 /* Use SSC source */
7940 if (pipe == PIPE_A)
7941 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7942 0x0df40000);
7943 else
7944 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7945 0x0df70000);
7946 } else { /* HDMI or VGA */
7947 /* Use bend source */
7948 if (pipe == PIPE_A)
7949 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7950 0x0df70000);
7951 else
7952 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7953 0x0df40000);
7954 }
7955
7956 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7957 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7958 if (intel_crtc_has_dp_encoder(crtc->config))
7959 coreclk |= 0x01000000;
7960 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7961
7962 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7963 mutex_unlock(&dev_priv->sb_lock);
7964 }
7965
7966 static void chv_prepare_pll(struct intel_crtc *crtc,
7967 const struct intel_crtc_state *pipe_config)
7968 {
7969 struct drm_device *dev = crtc->base.dev;
7970 struct drm_i915_private *dev_priv = to_i915(dev);
7971 enum pipe pipe = crtc->pipe;
7972 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7973 u32 loopfilter, tribuf_calcntr;
7974 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7975 u32 dpio_val;
7976 int vco;
7977
7978 /* Enable Refclk and SSC */
7979 I915_WRITE(DPLL(pipe),
7980 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7981
7982 /* No need to actually set up the DPLL with DSI */
7983 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7984 return;
7985
7986 bestn = pipe_config->dpll.n;
7987 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7988 bestm1 = pipe_config->dpll.m1;
7989 bestm2 = pipe_config->dpll.m2 >> 22;
7990 bestp1 = pipe_config->dpll.p1;
7991 bestp2 = pipe_config->dpll.p2;
7992 vco = pipe_config->dpll.vco;
7993 dpio_val = 0;
7994 loopfilter = 0;
7995
7996 mutex_lock(&dev_priv->sb_lock);
7997
7998 /* p1 and p2 divider */
7999 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8000 5 << DPIO_CHV_S1_DIV_SHIFT |
8001 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8002 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8003 1 << DPIO_CHV_K_DIV_SHIFT);
8004
8005 /* Feedback post-divider - m2 */
8006 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8007
8008 /* Feedback refclk divider - n and m1 */
8009 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8010 DPIO_CHV_M1_DIV_BY_2 |
8011 1 << DPIO_CHV_N_DIV_SHIFT);
8012
8013 /* M2 fraction division */
8014 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8015
8016 /* M2 fraction division enable */
8017 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8018 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8019 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8020 if (bestm2_frac)
8021 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8022 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8023
8024 /* Program digital lock detect threshold */
8025 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8026 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8027 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8028 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8029 if (!bestm2_frac)
8030 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8031 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8032
8033 /* Loop filter */
8034 if (vco == 5400000) {
8035 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8036 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8037 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8038 tribuf_calcntr = 0x9;
8039 } else if (vco <= 6200000) {
8040 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8041 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8042 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8043 tribuf_calcntr = 0x9;
8044 } else if (vco <= 6480000) {
8045 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8046 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8047 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8048 tribuf_calcntr = 0x8;
8049 } else {
8050 /* Not supported. Apply the same limits as in the max case */
8051 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8052 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8053 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8054 tribuf_calcntr = 0;
8055 }
8056 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8057
8058 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8059 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8060 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8061 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8062
8063 /* AFC Recal */
8064 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8065 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8066 DPIO_AFC_RECAL);
8067
8068 mutex_unlock(&dev_priv->sb_lock);
8069 }
8070
8071 /**
8072 * vlv_force_pll_on - forcibly enable just the PLL
8073 * @dev_priv: i915 private structure
8074 * @pipe: pipe PLL to enable
8075 * @dpll: PLL configuration
8076 *
8077 * Enable the PLL for @pipe using the supplied @dpll config. To be used
8078 * in cases where we need the PLL enabled even when @pipe is not going to
8079 * be enabled.
8080 */
8081 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
8082 const struct dpll *dpll)
8083 {
8084 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
8085 struct intel_crtc_state *pipe_config;
8086
8087 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8088 if (!pipe_config)
8089 return -ENOMEM;
8090
8091 pipe_config->base.crtc = &crtc->base;
8092 pipe_config->pixel_multiplier = 1;
8093 pipe_config->dpll = *dpll;
8094
8095 if (IS_CHERRYVIEW(dev_priv)) {
8096 chv_compute_dpll(crtc, pipe_config);
8097 chv_prepare_pll(crtc, pipe_config);
8098 chv_enable_pll(crtc, pipe_config);
8099 } else {
8100 vlv_compute_dpll(crtc, pipe_config);
8101 vlv_prepare_pll(crtc, pipe_config);
8102 vlv_enable_pll(crtc, pipe_config);
8103 }
8104
8105 kfree(pipe_config);
8106
8107 return 0;
8108 }
8109
8110 /**
8111 * vlv_force_pll_off - forcibly disable just the PLL
8112 * @dev_priv: i915 private structure
8113 * @pipe: pipe PLL to disable
8114 *
8115 * Disable the PLL for @pipe. To be used in cases where we need
8116 * the PLL enabled even when @pipe is not going to be enabled.
8117 */
8118 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
8119 {
8120 if (IS_CHERRYVIEW(dev_priv))
8121 chv_disable_pll(dev_priv, pipe);
8122 else
8123 vlv_disable_pll(dev_priv, pipe);
8124 }
8125
8126 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8127 struct intel_crtc_state *crtc_state,
8128 struct dpll *reduced_clock)
8129 {
8130 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8131 u32 dpll;
8132 struct dpll *clock = &crtc_state->dpll;
8133
8134 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8135
8136 dpll = DPLL_VGA_MODE_DIS;
8137
8138 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8139 dpll |= DPLLB_MODE_LVDS;
8140 else
8141 dpll |= DPLLB_MODE_DAC_SERIAL;
8142
8143 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || IS_G33(dev_priv)) {
8144 dpll |= (crtc_state->pixel_multiplier - 1)
8145 << SDVO_MULTIPLIER_SHIFT_HIRES;
8146 }
8147
8148 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8149 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8150 dpll |= DPLL_SDVO_HIGH_SPEED;
8151
8152 if (intel_crtc_has_dp_encoder(crtc_state))
8153 dpll |= DPLL_SDVO_HIGH_SPEED;
8154
8155 /* compute bitmask from p1 value */
8156 if (IS_PINEVIEW(dev_priv))
8157 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8158 else {
8159 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8160 if (IS_G4X(dev_priv) && reduced_clock)
8161 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8162 }
8163 switch (clock->p2) {
8164 case 5:
8165 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8166 break;
8167 case 7:
8168 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8169 break;
8170 case 10:
8171 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8172 break;
8173 case 14:
8174 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8175 break;
8176 }
8177 if (INTEL_GEN(dev_priv) >= 4)
8178 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8179
8180 if (crtc_state->sdvo_tv_clock)
8181 dpll |= PLL_REF_INPUT_TVCLKINBC;
8182 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8183 intel_panel_use_ssc(dev_priv))
8184 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8185 else
8186 dpll |= PLL_REF_INPUT_DREFCLK;
8187
8188 dpll |= DPLL_VCO_ENABLE;
8189 crtc_state->dpll_hw_state.dpll = dpll;
8190
8191 if (INTEL_GEN(dev_priv) >= 4) {
8192 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8193 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8194 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8195 }
8196 }
8197
8198 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8199 struct intel_crtc_state *crtc_state,
8200 struct dpll *reduced_clock)
8201 {
8202 struct drm_device *dev = crtc->base.dev;
8203 struct drm_i915_private *dev_priv = to_i915(dev);
8204 u32 dpll;
8205 struct dpll *clock = &crtc_state->dpll;
8206
8207 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8208
8209 dpll = DPLL_VGA_MODE_DIS;
8210
8211 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8212 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8213 } else {
8214 if (clock->p1 == 2)
8215 dpll |= PLL_P1_DIVIDE_BY_TWO;
8216 else
8217 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8218 if (clock->p2 == 4)
8219 dpll |= PLL_P2_DIVIDE_BY_4;
8220 }
8221
8222 if (!IS_I830(dev_priv) &&
8223 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8224 dpll |= DPLL_DVO_2X_MODE;
8225
8226 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8227 intel_panel_use_ssc(dev_priv))
8228 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8229 else
8230 dpll |= PLL_REF_INPUT_DREFCLK;
8231
8232 dpll |= DPLL_VCO_ENABLE;
8233 crtc_state->dpll_hw_state.dpll = dpll;
8234 }
8235
8236 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
8237 {
8238 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
8239 enum pipe pipe = intel_crtc->pipe;
8240 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8241 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
8242 uint32_t crtc_vtotal, crtc_vblank_end;
8243 int vsyncshift = 0;
8244
8245 /* We need to be careful not to changed the adjusted mode, for otherwise
8246 * the hw state checker will get angry at the mismatch. */
8247 crtc_vtotal = adjusted_mode->crtc_vtotal;
8248 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8249
8250 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8251 /* the chip adds 2 halflines automatically */
8252 crtc_vtotal -= 1;
8253 crtc_vblank_end -= 1;
8254
8255 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8256 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8257 else
8258 vsyncshift = adjusted_mode->crtc_hsync_start -
8259 adjusted_mode->crtc_htotal / 2;
8260 if (vsyncshift < 0)
8261 vsyncshift += adjusted_mode->crtc_htotal;
8262 }
8263
8264 if (INTEL_GEN(dev_priv) > 3)
8265 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8266
8267 I915_WRITE(HTOTAL(cpu_transcoder),
8268 (adjusted_mode->crtc_hdisplay - 1) |
8269 ((adjusted_mode->crtc_htotal - 1) << 16));
8270 I915_WRITE(HBLANK(cpu_transcoder),
8271 (adjusted_mode->crtc_hblank_start - 1) |
8272 ((adjusted_mode->crtc_hblank_end - 1) << 16));
8273 I915_WRITE(HSYNC(cpu_transcoder),
8274 (adjusted_mode->crtc_hsync_start - 1) |
8275 ((adjusted_mode->crtc_hsync_end - 1) << 16));
8276
8277 I915_WRITE(VTOTAL(cpu_transcoder),
8278 (adjusted_mode->crtc_vdisplay - 1) |
8279 ((crtc_vtotal - 1) << 16));
8280 I915_WRITE(VBLANK(cpu_transcoder),
8281 (adjusted_mode->crtc_vblank_start - 1) |
8282 ((crtc_vblank_end - 1) << 16));
8283 I915_WRITE(VSYNC(cpu_transcoder),
8284 (adjusted_mode->crtc_vsync_start - 1) |
8285 ((adjusted_mode->crtc_vsync_end - 1) << 16));
8286
8287 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8288 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8289 * documented on the DDI_FUNC_CTL register description, EDP Input Select
8290 * bits. */
8291 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8292 (pipe == PIPE_B || pipe == PIPE_C))
8293 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8294
8295 }
8296
8297 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
8298 {
8299 struct drm_device *dev = intel_crtc->base.dev;
8300 struct drm_i915_private *dev_priv = to_i915(dev);
8301 enum pipe pipe = intel_crtc->pipe;
8302
8303 /* pipesrc controls the size that is scaled from, which should
8304 * always be the user's requested size.
8305 */
8306 I915_WRITE(PIPESRC(pipe),
8307 ((intel_crtc->config->pipe_src_w - 1) << 16) |
8308 (intel_crtc->config->pipe_src_h - 1));
8309 }
8310
8311 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8312 struct intel_crtc_state *pipe_config)
8313 {
8314 struct drm_device *dev = crtc->base.dev;
8315 struct drm_i915_private *dev_priv = to_i915(dev);
8316 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8317 uint32_t tmp;
8318
8319 tmp = I915_READ(HTOTAL(cpu_transcoder));
8320 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8321 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8322 tmp = I915_READ(HBLANK(cpu_transcoder));
8323 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
8324 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
8325 tmp = I915_READ(HSYNC(cpu_transcoder));
8326 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8327 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8328
8329 tmp = I915_READ(VTOTAL(cpu_transcoder));
8330 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8331 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8332 tmp = I915_READ(VBLANK(cpu_transcoder));
8333 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
8334 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
8335 tmp = I915_READ(VSYNC(cpu_transcoder));
8336 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8337 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8338
8339 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
8340 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8341 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
8342 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
8343 }
8344 }
8345
8346 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8347 struct intel_crtc_state *pipe_config)
8348 {
8349 struct drm_device *dev = crtc->base.dev;
8350 struct drm_i915_private *dev_priv = to_i915(dev);
8351 u32 tmp;
8352
8353 tmp = I915_READ(PIPESRC(crtc->pipe));
8354 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8355 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8356
8357 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
8358 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
8359 }
8360
8361 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8362 struct intel_crtc_state *pipe_config)
8363 {
8364 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
8365 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
8366 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
8367 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
8368
8369 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
8370 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
8371 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
8372 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
8373
8374 mode->flags = pipe_config->base.adjusted_mode.flags;
8375 mode->type = DRM_MODE_TYPE_DRIVER;
8376
8377 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
8378 mode->flags |= pipe_config->base.adjusted_mode.flags;
8379
8380 mode->hsync = drm_mode_hsync(mode);
8381 mode->vrefresh = drm_mode_vrefresh(mode);
8382 drm_mode_set_name(mode);
8383 }
8384
8385 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
8386 {
8387 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
8388 uint32_t pipeconf;
8389
8390 pipeconf = 0;
8391
8392 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
8393 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8394 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
8395
8396 if (intel_crtc->config->double_wide)
8397 pipeconf |= PIPECONF_DOUBLE_WIDE;
8398
8399 /* only g4x and later have fancy bpc/dither controls */
8400 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8401 IS_CHERRYVIEW(dev_priv)) {
8402 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8403 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
8404 pipeconf |= PIPECONF_DITHER_EN |
8405 PIPECONF_DITHER_TYPE_SP;
8406
8407 switch (intel_crtc->config->pipe_bpp) {
8408 case 18:
8409 pipeconf |= PIPECONF_6BPC;
8410 break;
8411 case 24:
8412 pipeconf |= PIPECONF_8BPC;
8413 break;
8414 case 30:
8415 pipeconf |= PIPECONF_10BPC;
8416 break;
8417 default:
8418 /* Case prevented by intel_choose_pipe_bpp_dither. */
8419 BUG();
8420 }
8421 }
8422
8423 if (HAS_PIPE_CXSR(dev_priv)) {
8424 if (intel_crtc->lowfreq_avail) {
8425 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
8426 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
8427 } else {
8428 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
8429 }
8430 }
8431
8432 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8433 if (INTEL_GEN(dev_priv) < 4 ||
8434 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8435 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8436 else
8437 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8438 } else
8439 pipeconf |= PIPECONF_PROGRESSIVE;
8440
8441 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8442 intel_crtc->config->limited_color_range)
8443 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8444
8445 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
8446 POSTING_READ(PIPECONF(intel_crtc->pipe));
8447 }
8448
8449 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8450 struct intel_crtc_state *crtc_state)
8451 {
8452 struct drm_device *dev = crtc->base.dev;
8453 struct drm_i915_private *dev_priv = to_i915(dev);
8454 const struct intel_limit *limit;
8455 int refclk = 48000;
8456
8457 memset(&crtc_state->dpll_hw_state, 0,
8458 sizeof(crtc_state->dpll_hw_state));
8459
8460 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8461 if (intel_panel_use_ssc(dev_priv)) {
8462 refclk = dev_priv->vbt.lvds_ssc_freq;
8463 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8464 }
8465
8466 limit = &intel_limits_i8xx_lvds;
8467 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8468 limit = &intel_limits_i8xx_dvo;
8469 } else {
8470 limit = &intel_limits_i8xx_dac;
8471 }
8472
8473 if (!crtc_state->clock_set &&
8474 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8475 refclk, NULL, &crtc_state->dpll)) {
8476 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8477 return -EINVAL;
8478 }
8479
8480 i8xx_compute_dpll(crtc, crtc_state, NULL);
8481
8482 return 0;
8483 }
8484
8485 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8486 struct intel_crtc_state *crtc_state)
8487 {
8488 struct drm_device *dev = crtc->base.dev;
8489 struct drm_i915_private *dev_priv = to_i915(dev);
8490 const struct intel_limit *limit;
8491 int refclk = 96000;
8492
8493 memset(&crtc_state->dpll_hw_state, 0,
8494 sizeof(crtc_state->dpll_hw_state));
8495
8496 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8497 if (intel_panel_use_ssc(dev_priv)) {
8498 refclk = dev_priv->vbt.lvds_ssc_freq;
8499 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8500 }
8501
8502 if (intel_is_dual_link_lvds(dev))
8503 limit = &intel_limits_g4x_dual_channel_lvds;
8504 else
8505 limit = &intel_limits_g4x_single_channel_lvds;
8506 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8507 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8508 limit = &intel_limits_g4x_hdmi;
8509 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8510 limit = &intel_limits_g4x_sdvo;
8511 } else {
8512 /* The option is for other outputs */
8513 limit = &intel_limits_i9xx_sdvo;
8514 }
8515
8516 if (!crtc_state->clock_set &&
8517 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8518 refclk, NULL, &crtc_state->dpll)) {
8519 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8520 return -EINVAL;
8521 }
8522
8523 i9xx_compute_dpll(crtc, crtc_state, NULL);
8524
8525 return 0;
8526 }
8527
8528 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8529 struct intel_crtc_state *crtc_state)
8530 {
8531 struct drm_device *dev = crtc->base.dev;
8532 struct drm_i915_private *dev_priv = to_i915(dev);
8533 const struct intel_limit *limit;
8534 int refclk = 96000;
8535
8536 memset(&crtc_state->dpll_hw_state, 0,
8537 sizeof(crtc_state->dpll_hw_state));
8538
8539 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8540 if (intel_panel_use_ssc(dev_priv)) {
8541 refclk = dev_priv->vbt.lvds_ssc_freq;
8542 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8543 }
8544
8545 limit = &intel_limits_pineview_lvds;
8546 } else {
8547 limit = &intel_limits_pineview_sdvo;
8548 }
8549
8550 if (!crtc_state->clock_set &&
8551 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8552 refclk, NULL, &crtc_state->dpll)) {
8553 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8554 return -EINVAL;
8555 }
8556
8557 i9xx_compute_dpll(crtc, crtc_state, NULL);
8558
8559 return 0;
8560 }
8561
8562 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8563 struct intel_crtc_state *crtc_state)
8564 {
8565 struct drm_device *dev = crtc->base.dev;
8566 struct drm_i915_private *dev_priv = to_i915(dev);
8567 const struct intel_limit *limit;
8568 int refclk = 96000;
8569
8570 memset(&crtc_state->dpll_hw_state, 0,
8571 sizeof(crtc_state->dpll_hw_state));
8572
8573 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8574 if (intel_panel_use_ssc(dev_priv)) {
8575 refclk = dev_priv->vbt.lvds_ssc_freq;
8576 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8577 }
8578
8579 limit = &intel_limits_i9xx_lvds;
8580 } else {
8581 limit = &intel_limits_i9xx_sdvo;
8582 }
8583
8584 if (!crtc_state->clock_set &&
8585 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8586 refclk, NULL, &crtc_state->dpll)) {
8587 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8588 return -EINVAL;
8589 }
8590
8591 i9xx_compute_dpll(crtc, crtc_state, NULL);
8592
8593 return 0;
8594 }
8595
8596 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8597 struct intel_crtc_state *crtc_state)
8598 {
8599 int refclk = 100000;
8600 const struct intel_limit *limit = &intel_limits_chv;
8601
8602 memset(&crtc_state->dpll_hw_state, 0,
8603 sizeof(crtc_state->dpll_hw_state));
8604
8605 if (!crtc_state->clock_set &&
8606 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8607 refclk, NULL, &crtc_state->dpll)) {
8608 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8609 return -EINVAL;
8610 }
8611
8612 chv_compute_dpll(crtc, crtc_state);
8613
8614 return 0;
8615 }
8616
8617 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8618 struct intel_crtc_state *crtc_state)
8619 {
8620 int refclk = 100000;
8621 const struct intel_limit *limit = &intel_limits_vlv;
8622
8623 memset(&crtc_state->dpll_hw_state, 0,
8624 sizeof(crtc_state->dpll_hw_state));
8625
8626 if (!crtc_state->clock_set &&
8627 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8628 refclk, NULL, &crtc_state->dpll)) {
8629 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8630 return -EINVAL;
8631 }
8632
8633 vlv_compute_dpll(crtc, crtc_state);
8634
8635 return 0;
8636 }
8637
8638 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8639 struct intel_crtc_state *pipe_config)
8640 {
8641 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8642 uint32_t tmp;
8643
8644 if (INTEL_GEN(dev_priv) <= 3 &&
8645 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
8646 return;
8647
8648 tmp = I915_READ(PFIT_CONTROL);
8649 if (!(tmp & PFIT_ENABLE))
8650 return;
8651
8652 /* Check whether the pfit is attached to our pipe. */
8653 if (INTEL_GEN(dev_priv) < 4) {
8654 if (crtc->pipe != PIPE_B)
8655 return;
8656 } else {
8657 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8658 return;
8659 }
8660
8661 pipe_config->gmch_pfit.control = tmp;
8662 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8663 }
8664
8665 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8666 struct intel_crtc_state *pipe_config)
8667 {
8668 struct drm_device *dev = crtc->base.dev;
8669 struct drm_i915_private *dev_priv = to_i915(dev);
8670 int pipe = pipe_config->cpu_transcoder;
8671 struct dpll clock;
8672 u32 mdiv;
8673 int refclk = 100000;
8674
8675 /* In case of DSI, DPLL will not be used */
8676 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8677 return;
8678
8679 mutex_lock(&dev_priv->sb_lock);
8680 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8681 mutex_unlock(&dev_priv->sb_lock);
8682
8683 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8684 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8685 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8686 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8687 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8688
8689 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8690 }
8691
8692 static void
8693 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8694 struct intel_initial_plane_config *plane_config)
8695 {
8696 struct drm_device *dev = crtc->base.dev;
8697 struct drm_i915_private *dev_priv = to_i915(dev);
8698 u32 val, base, offset;
8699 int pipe = crtc->pipe, plane = crtc->plane;
8700 int fourcc, pixel_format;
8701 unsigned int aligned_height;
8702 struct drm_framebuffer *fb;
8703 struct intel_framebuffer *intel_fb;
8704
8705 val = I915_READ(DSPCNTR(plane));
8706 if (!(val & DISPLAY_PLANE_ENABLE))
8707 return;
8708
8709 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8710 if (!intel_fb) {
8711 DRM_DEBUG_KMS("failed to alloc fb\n");
8712 return;
8713 }
8714
8715 fb = &intel_fb->base;
8716
8717 if (INTEL_GEN(dev_priv) >= 4) {
8718 if (val & DISPPLANE_TILED) {
8719 plane_config->tiling = I915_TILING_X;
8720 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8721 }
8722 }
8723
8724 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8725 fourcc = i9xx_format_to_fourcc(pixel_format);
8726 fb->pixel_format = fourcc;
8727 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8728
8729 if (INTEL_GEN(dev_priv) >= 4) {
8730 if (plane_config->tiling)
8731 offset = I915_READ(DSPTILEOFF(plane));
8732 else
8733 offset = I915_READ(DSPLINOFF(plane));
8734 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8735 } else {
8736 base = I915_READ(DSPADDR(plane));
8737 }
8738 plane_config->base = base;
8739
8740 val = I915_READ(PIPESRC(pipe));
8741 fb->width = ((val >> 16) & 0xfff) + 1;
8742 fb->height = ((val >> 0) & 0xfff) + 1;
8743
8744 val = I915_READ(DSPSTRIDE(pipe));
8745 fb->pitches[0] = val & 0xffffffc0;
8746
8747 aligned_height = intel_fb_align_height(dev, fb->height,
8748 fb->pixel_format,
8749 fb->modifier[0]);
8750
8751 plane_config->size = fb->pitches[0] * aligned_height;
8752
8753 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8754 pipe_name(pipe), plane, fb->width, fb->height,
8755 fb->bits_per_pixel, base, fb->pitches[0],
8756 plane_config->size);
8757
8758 plane_config->fb = intel_fb;
8759 }
8760
8761 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8762 struct intel_crtc_state *pipe_config)
8763 {
8764 struct drm_device *dev = crtc->base.dev;
8765 struct drm_i915_private *dev_priv = to_i915(dev);
8766 int pipe = pipe_config->cpu_transcoder;
8767 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8768 struct dpll clock;
8769 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8770 int refclk = 100000;
8771
8772 /* In case of DSI, DPLL will not be used */
8773 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8774 return;
8775
8776 mutex_lock(&dev_priv->sb_lock);
8777 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8778 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8779 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8780 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8781 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8782 mutex_unlock(&dev_priv->sb_lock);
8783
8784 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8785 clock.m2 = (pll_dw0 & 0xff) << 22;
8786 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8787 clock.m2 |= pll_dw2 & 0x3fffff;
8788 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8789 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8790 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8791
8792 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8793 }
8794
8795 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8796 struct intel_crtc_state *pipe_config)
8797 {
8798 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8799 enum intel_display_power_domain power_domain;
8800 uint32_t tmp;
8801 bool ret;
8802
8803 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8804 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8805 return false;
8806
8807 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8808 pipe_config->shared_dpll = NULL;
8809
8810 ret = false;
8811
8812 tmp = I915_READ(PIPECONF(crtc->pipe));
8813 if (!(tmp & PIPECONF_ENABLE))
8814 goto out;
8815
8816 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8817 IS_CHERRYVIEW(dev_priv)) {
8818 switch (tmp & PIPECONF_BPC_MASK) {
8819 case PIPECONF_6BPC:
8820 pipe_config->pipe_bpp = 18;
8821 break;
8822 case PIPECONF_8BPC:
8823 pipe_config->pipe_bpp = 24;
8824 break;
8825 case PIPECONF_10BPC:
8826 pipe_config->pipe_bpp = 30;
8827 break;
8828 default:
8829 break;
8830 }
8831 }
8832
8833 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8834 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8835 pipe_config->limited_color_range = true;
8836
8837 if (INTEL_GEN(dev_priv) < 4)
8838 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8839
8840 intel_get_pipe_timings(crtc, pipe_config);
8841 intel_get_pipe_src_size(crtc, pipe_config);
8842
8843 i9xx_get_pfit_config(crtc, pipe_config);
8844
8845 if (INTEL_GEN(dev_priv) >= 4) {
8846 /* No way to read it out on pipes B and C */
8847 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
8848 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8849 else
8850 tmp = I915_READ(DPLL_MD(crtc->pipe));
8851 pipe_config->pixel_multiplier =
8852 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8853 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8854 pipe_config->dpll_hw_state.dpll_md = tmp;
8855 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8856 IS_G33(dev_priv)) {
8857 tmp = I915_READ(DPLL(crtc->pipe));
8858 pipe_config->pixel_multiplier =
8859 ((tmp & SDVO_MULTIPLIER_MASK)
8860 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8861 } else {
8862 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8863 * port and will be fixed up in the encoder->get_config
8864 * function. */
8865 pipe_config->pixel_multiplier = 1;
8866 }
8867 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8868 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
8869 /*
8870 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8871 * on 830. Filter it out here so that we don't
8872 * report errors due to that.
8873 */
8874 if (IS_I830(dev_priv))
8875 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8876
8877 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8878 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8879 } else {
8880 /* Mask out read-only status bits. */
8881 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8882 DPLL_PORTC_READY_MASK |
8883 DPLL_PORTB_READY_MASK);
8884 }
8885
8886 if (IS_CHERRYVIEW(dev_priv))
8887 chv_crtc_clock_get(crtc, pipe_config);
8888 else if (IS_VALLEYVIEW(dev_priv))
8889 vlv_crtc_clock_get(crtc, pipe_config);
8890 else
8891 i9xx_crtc_clock_get(crtc, pipe_config);
8892
8893 /*
8894 * Normally the dotclock is filled in by the encoder .get_config()
8895 * but in case the pipe is enabled w/o any ports we need a sane
8896 * default.
8897 */
8898 pipe_config->base.adjusted_mode.crtc_clock =
8899 pipe_config->port_clock / pipe_config->pixel_multiplier;
8900
8901 ret = true;
8902
8903 out:
8904 intel_display_power_put(dev_priv, power_domain);
8905
8906 return ret;
8907 }
8908
8909 static void ironlake_init_pch_refclk(struct drm_device *dev)
8910 {
8911 struct drm_i915_private *dev_priv = to_i915(dev);
8912 struct intel_encoder *encoder;
8913 int i;
8914 u32 val, final;
8915 bool has_lvds = false;
8916 bool has_cpu_edp = false;
8917 bool has_panel = false;
8918 bool has_ck505 = false;
8919 bool can_ssc = false;
8920 bool using_ssc_source = false;
8921
8922 /* We need to take the global config into account */
8923 for_each_intel_encoder(dev, encoder) {
8924 switch (encoder->type) {
8925 case INTEL_OUTPUT_LVDS:
8926 has_panel = true;
8927 has_lvds = true;
8928 break;
8929 case INTEL_OUTPUT_EDP:
8930 has_panel = true;
8931 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8932 has_cpu_edp = true;
8933 break;
8934 default:
8935 break;
8936 }
8937 }
8938
8939 if (HAS_PCH_IBX(dev_priv)) {
8940 has_ck505 = dev_priv->vbt.display_clock_mode;
8941 can_ssc = has_ck505;
8942 } else {
8943 has_ck505 = false;
8944 can_ssc = true;
8945 }
8946
8947 /* Check if any DPLLs are using the SSC source */
8948 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8949 u32 temp = I915_READ(PCH_DPLL(i));
8950
8951 if (!(temp & DPLL_VCO_ENABLE))
8952 continue;
8953
8954 if ((temp & PLL_REF_INPUT_MASK) ==
8955 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8956 using_ssc_source = true;
8957 break;
8958 }
8959 }
8960
8961 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8962 has_panel, has_lvds, has_ck505, using_ssc_source);
8963
8964 /* Ironlake: try to setup display ref clock before DPLL
8965 * enabling. This is only under driver's control after
8966 * PCH B stepping, previous chipset stepping should be
8967 * ignoring this setting.
8968 */
8969 val = I915_READ(PCH_DREF_CONTROL);
8970
8971 /* As we must carefully and slowly disable/enable each source in turn,
8972 * compute the final state we want first and check if we need to
8973 * make any changes at all.
8974 */
8975 final = val;
8976 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8977 if (has_ck505)
8978 final |= DREF_NONSPREAD_CK505_ENABLE;
8979 else
8980 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8981
8982 final &= ~DREF_SSC_SOURCE_MASK;
8983 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8984 final &= ~DREF_SSC1_ENABLE;
8985
8986 if (has_panel) {
8987 final |= DREF_SSC_SOURCE_ENABLE;
8988
8989 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8990 final |= DREF_SSC1_ENABLE;
8991
8992 if (has_cpu_edp) {
8993 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8994 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8995 else
8996 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8997 } else
8998 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8999 } else if (using_ssc_source) {
9000 final |= DREF_SSC_SOURCE_ENABLE;
9001 final |= DREF_SSC1_ENABLE;
9002 }
9003
9004 if (final == val)
9005 return;
9006
9007 /* Always enable nonspread source */
9008 val &= ~DREF_NONSPREAD_SOURCE_MASK;
9009
9010 if (has_ck505)
9011 val |= DREF_NONSPREAD_CK505_ENABLE;
9012 else
9013 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9014
9015 if (has_panel) {
9016 val &= ~DREF_SSC_SOURCE_MASK;
9017 val |= DREF_SSC_SOURCE_ENABLE;
9018
9019 /* SSC must be turned on before enabling the CPU output */
9020 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9021 DRM_DEBUG_KMS("Using SSC on panel\n");
9022 val |= DREF_SSC1_ENABLE;
9023 } else
9024 val &= ~DREF_SSC1_ENABLE;
9025
9026 /* Get SSC going before enabling the outputs */
9027 I915_WRITE(PCH_DREF_CONTROL, val);
9028 POSTING_READ(PCH_DREF_CONTROL);
9029 udelay(200);
9030
9031 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9032
9033 /* Enable CPU source on CPU attached eDP */
9034 if (has_cpu_edp) {
9035 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9036 DRM_DEBUG_KMS("Using SSC on eDP\n");
9037 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9038 } else
9039 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9040 } else
9041 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9042
9043 I915_WRITE(PCH_DREF_CONTROL, val);
9044 POSTING_READ(PCH_DREF_CONTROL);
9045 udelay(200);
9046 } else {
9047 DRM_DEBUG_KMS("Disabling CPU source output\n");
9048
9049 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9050
9051 /* Turn off CPU output */
9052 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9053
9054 I915_WRITE(PCH_DREF_CONTROL, val);
9055 POSTING_READ(PCH_DREF_CONTROL);
9056 udelay(200);
9057
9058 if (!using_ssc_source) {
9059 DRM_DEBUG_KMS("Disabling SSC source\n");
9060
9061 /* Turn off the SSC source */
9062 val &= ~DREF_SSC_SOURCE_MASK;
9063 val |= DREF_SSC_SOURCE_DISABLE;
9064
9065 /* Turn off SSC1 */
9066 val &= ~DREF_SSC1_ENABLE;
9067
9068 I915_WRITE(PCH_DREF_CONTROL, val);
9069 POSTING_READ(PCH_DREF_CONTROL);
9070 udelay(200);
9071 }
9072 }
9073
9074 BUG_ON(val != final);
9075 }
9076
9077 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9078 {
9079 uint32_t tmp;
9080
9081 tmp = I915_READ(SOUTH_CHICKEN2);
9082 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9083 I915_WRITE(SOUTH_CHICKEN2, tmp);
9084
9085 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
9086 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9087 DRM_ERROR("FDI mPHY reset assert timeout\n");
9088
9089 tmp = I915_READ(SOUTH_CHICKEN2);
9090 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9091 I915_WRITE(SOUTH_CHICKEN2, tmp);
9092
9093 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
9094 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9095 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9096 }
9097
9098 /* WaMPhyProgramming:hsw */
9099 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9100 {
9101 uint32_t tmp;
9102
9103 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9104 tmp &= ~(0xFF << 24);
9105 tmp |= (0x12 << 24);
9106 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9107
9108 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9109 tmp |= (1 << 11);
9110 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9111
9112 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9113 tmp |= (1 << 11);
9114 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9115
9116 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9117 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9118 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9119
9120 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9121 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9122 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9123
9124 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9125 tmp &= ~(7 << 13);
9126 tmp |= (5 << 13);
9127 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9128
9129 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9130 tmp &= ~(7 << 13);
9131 tmp |= (5 << 13);
9132 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9133
9134 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9135 tmp &= ~0xFF;
9136 tmp |= 0x1C;
9137 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9138
9139 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9140 tmp &= ~0xFF;
9141 tmp |= 0x1C;
9142 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9143
9144 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9145 tmp &= ~(0xFF << 16);
9146 tmp |= (0x1C << 16);
9147 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9148
9149 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9150 tmp &= ~(0xFF << 16);
9151 tmp |= (0x1C << 16);
9152 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9153
9154 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9155 tmp |= (1 << 27);
9156 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9157
9158 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9159 tmp |= (1 << 27);
9160 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9161
9162 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9163 tmp &= ~(0xF << 28);
9164 tmp |= (4 << 28);
9165 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9166
9167 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9168 tmp &= ~(0xF << 28);
9169 tmp |= (4 << 28);
9170 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9171 }
9172
9173 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9174 * Programming" based on the parameters passed:
9175 * - Sequence to enable CLKOUT_DP
9176 * - Sequence to enable CLKOUT_DP without spread
9177 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9178 */
9179 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
9180 bool with_fdi)
9181 {
9182 struct drm_i915_private *dev_priv = to_i915(dev);
9183 uint32_t reg, tmp;
9184
9185 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9186 with_spread = true;
9187 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
9188 with_fdi, "LP PCH doesn't have FDI\n"))
9189 with_fdi = false;
9190
9191 mutex_lock(&dev_priv->sb_lock);
9192
9193 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9194 tmp &= ~SBI_SSCCTL_DISABLE;
9195 tmp |= SBI_SSCCTL_PATHALT;
9196 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9197
9198 udelay(24);
9199
9200 if (with_spread) {
9201 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9202 tmp &= ~SBI_SSCCTL_PATHALT;
9203 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9204
9205 if (with_fdi) {
9206 lpt_reset_fdi_mphy(dev_priv);
9207 lpt_program_fdi_mphy(dev_priv);
9208 }
9209 }
9210
9211 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9212 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9213 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9214 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9215
9216 mutex_unlock(&dev_priv->sb_lock);
9217 }
9218
9219 /* Sequence to disable CLKOUT_DP */
9220 static void lpt_disable_clkout_dp(struct drm_device *dev)
9221 {
9222 struct drm_i915_private *dev_priv = to_i915(dev);
9223 uint32_t reg, tmp;
9224
9225 mutex_lock(&dev_priv->sb_lock);
9226
9227 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9228 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9229 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9230 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9231
9232 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9233 if (!(tmp & SBI_SSCCTL_DISABLE)) {
9234 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9235 tmp |= SBI_SSCCTL_PATHALT;
9236 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9237 udelay(32);
9238 }
9239 tmp |= SBI_SSCCTL_DISABLE;
9240 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9241 }
9242
9243 mutex_unlock(&dev_priv->sb_lock);
9244 }
9245
9246 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9247
9248 static const uint16_t sscdivintphase[] = {
9249 [BEND_IDX( 50)] = 0x3B23,
9250 [BEND_IDX( 45)] = 0x3B23,
9251 [BEND_IDX( 40)] = 0x3C23,
9252 [BEND_IDX( 35)] = 0x3C23,
9253 [BEND_IDX( 30)] = 0x3D23,
9254 [BEND_IDX( 25)] = 0x3D23,
9255 [BEND_IDX( 20)] = 0x3E23,
9256 [BEND_IDX( 15)] = 0x3E23,
9257 [BEND_IDX( 10)] = 0x3F23,
9258 [BEND_IDX( 5)] = 0x3F23,
9259 [BEND_IDX( 0)] = 0x0025,
9260 [BEND_IDX( -5)] = 0x0025,
9261 [BEND_IDX(-10)] = 0x0125,
9262 [BEND_IDX(-15)] = 0x0125,
9263 [BEND_IDX(-20)] = 0x0225,
9264 [BEND_IDX(-25)] = 0x0225,
9265 [BEND_IDX(-30)] = 0x0325,
9266 [BEND_IDX(-35)] = 0x0325,
9267 [BEND_IDX(-40)] = 0x0425,
9268 [BEND_IDX(-45)] = 0x0425,
9269 [BEND_IDX(-50)] = 0x0525,
9270 };
9271
9272 /*
9273 * Bend CLKOUT_DP
9274 * steps -50 to 50 inclusive, in steps of 5
9275 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9276 * change in clock period = -(steps / 10) * 5.787 ps
9277 */
9278 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9279 {
9280 uint32_t tmp;
9281 int idx = BEND_IDX(steps);
9282
9283 if (WARN_ON(steps % 5 != 0))
9284 return;
9285
9286 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9287 return;
9288
9289 mutex_lock(&dev_priv->sb_lock);
9290
9291 if (steps % 10 != 0)
9292 tmp = 0xAAAAAAAB;
9293 else
9294 tmp = 0x00000000;
9295 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9296
9297 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9298 tmp &= 0xffff0000;
9299 tmp |= sscdivintphase[idx];
9300 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9301
9302 mutex_unlock(&dev_priv->sb_lock);
9303 }
9304
9305 #undef BEND_IDX
9306
9307 static void lpt_init_pch_refclk(struct drm_device *dev)
9308 {
9309 struct intel_encoder *encoder;
9310 bool has_vga = false;
9311
9312 for_each_intel_encoder(dev, encoder) {
9313 switch (encoder->type) {
9314 case INTEL_OUTPUT_ANALOG:
9315 has_vga = true;
9316 break;
9317 default:
9318 break;
9319 }
9320 }
9321
9322 if (has_vga) {
9323 lpt_bend_clkout_dp(to_i915(dev), 0);
9324 lpt_enable_clkout_dp(dev, true, true);
9325 } else {
9326 lpt_disable_clkout_dp(dev);
9327 }
9328 }
9329
9330 /*
9331 * Initialize reference clocks when the driver loads
9332 */
9333 void intel_init_pch_refclk(struct drm_device *dev)
9334 {
9335 struct drm_i915_private *dev_priv = to_i915(dev);
9336
9337 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
9338 ironlake_init_pch_refclk(dev);
9339 else if (HAS_PCH_LPT(dev_priv))
9340 lpt_init_pch_refclk(dev);
9341 }
9342
9343 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
9344 {
9345 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9347 int pipe = intel_crtc->pipe;
9348 uint32_t val;
9349
9350 val = 0;
9351
9352 switch (intel_crtc->config->pipe_bpp) {
9353 case 18:
9354 val |= PIPECONF_6BPC;
9355 break;
9356 case 24:
9357 val |= PIPECONF_8BPC;
9358 break;
9359 case 30:
9360 val |= PIPECONF_10BPC;
9361 break;
9362 case 36:
9363 val |= PIPECONF_12BPC;
9364 break;
9365 default:
9366 /* Case prevented by intel_choose_pipe_bpp_dither. */
9367 BUG();
9368 }
9369
9370 if (intel_crtc->config->dither)
9371 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9372
9373 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9374 val |= PIPECONF_INTERLACED_ILK;
9375 else
9376 val |= PIPECONF_PROGRESSIVE;
9377
9378 if (intel_crtc->config->limited_color_range)
9379 val |= PIPECONF_COLOR_RANGE_SELECT;
9380
9381 I915_WRITE(PIPECONF(pipe), val);
9382 POSTING_READ(PIPECONF(pipe));
9383 }
9384
9385 static void haswell_set_pipeconf(struct drm_crtc *crtc)
9386 {
9387 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9389 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9390 u32 val = 0;
9391
9392 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
9393 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9394
9395 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9396 val |= PIPECONF_INTERLACED_ILK;
9397 else
9398 val |= PIPECONF_PROGRESSIVE;
9399
9400 I915_WRITE(PIPECONF(cpu_transcoder), val);
9401 POSTING_READ(PIPECONF(cpu_transcoder));
9402 }
9403
9404 static void haswell_set_pipemisc(struct drm_crtc *crtc)
9405 {
9406 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9408
9409 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
9410 u32 val = 0;
9411
9412 switch (intel_crtc->config->pipe_bpp) {
9413 case 18:
9414 val |= PIPEMISC_DITHER_6_BPC;
9415 break;
9416 case 24:
9417 val |= PIPEMISC_DITHER_8_BPC;
9418 break;
9419 case 30:
9420 val |= PIPEMISC_DITHER_10_BPC;
9421 break;
9422 case 36:
9423 val |= PIPEMISC_DITHER_12_BPC;
9424 break;
9425 default:
9426 /* Case prevented by pipe_config_set_bpp. */
9427 BUG();
9428 }
9429
9430 if (intel_crtc->config->dither)
9431 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9432
9433 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
9434 }
9435 }
9436
9437 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9438 {
9439 /*
9440 * Account for spread spectrum to avoid
9441 * oversubscribing the link. Max center spread
9442 * is 2.5%; use 5% for safety's sake.
9443 */
9444 u32 bps = target_clock * bpp * 21 / 20;
9445 return DIV_ROUND_UP(bps, link_bw * 8);
9446 }
9447
9448 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9449 {
9450 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9451 }
9452
9453 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
9454 struct intel_crtc_state *crtc_state,
9455 struct dpll *reduced_clock)
9456 {
9457 struct drm_crtc *crtc = &intel_crtc->base;
9458 struct drm_device *dev = crtc->dev;
9459 struct drm_i915_private *dev_priv = to_i915(dev);
9460 u32 dpll, fp, fp2;
9461 int factor;
9462
9463 /* Enable autotuning of the PLL clock (if permissible) */
9464 factor = 21;
9465 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9466 if ((intel_panel_use_ssc(dev_priv) &&
9467 dev_priv->vbt.lvds_ssc_freq == 100000) ||
9468 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
9469 factor = 25;
9470 } else if (crtc_state->sdvo_tv_clock)
9471 factor = 20;
9472
9473 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9474
9475 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9476 fp |= FP_CB_TUNE;
9477
9478 if (reduced_clock) {
9479 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9480
9481 if (reduced_clock->m < factor * reduced_clock->n)
9482 fp2 |= FP_CB_TUNE;
9483 } else {
9484 fp2 = fp;
9485 }
9486
9487 dpll = 0;
9488
9489 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9490 dpll |= DPLLB_MODE_LVDS;
9491 else
9492 dpll |= DPLLB_MODE_DAC_SERIAL;
9493
9494 dpll |= (crtc_state->pixel_multiplier - 1)
9495 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9496
9497 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9498 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9499 dpll |= DPLL_SDVO_HIGH_SPEED;
9500
9501 if (intel_crtc_has_dp_encoder(crtc_state))
9502 dpll |= DPLL_SDVO_HIGH_SPEED;
9503
9504 /*
9505 * The high speed IO clock is only really required for
9506 * SDVO/HDMI/DP, but we also enable it for CRT to make it
9507 * possible to share the DPLL between CRT and HDMI. Enabling
9508 * the clock needlessly does no real harm, except use up a
9509 * bit of power potentially.
9510 *
9511 * We'll limit this to IVB with 3 pipes, since it has only two
9512 * DPLLs and so DPLL sharing is the only way to get three pipes
9513 * driving PCH ports at the same time. On SNB we could do this,
9514 * and potentially avoid enabling the second DPLL, but it's not
9515 * clear if it''s a win or loss power wise. No point in doing
9516 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9517 */
9518 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
9519 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
9520 dpll |= DPLL_SDVO_HIGH_SPEED;
9521
9522 /* compute bitmask from p1 value */
9523 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9524 /* also FPA1 */
9525 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9526
9527 switch (crtc_state->dpll.p2) {
9528 case 5:
9529 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9530 break;
9531 case 7:
9532 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9533 break;
9534 case 10:
9535 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9536 break;
9537 case 14:
9538 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9539 break;
9540 }
9541
9542 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9543 intel_panel_use_ssc(dev_priv))
9544 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9545 else
9546 dpll |= PLL_REF_INPUT_DREFCLK;
9547
9548 dpll |= DPLL_VCO_ENABLE;
9549
9550 crtc_state->dpll_hw_state.dpll = dpll;
9551 crtc_state->dpll_hw_state.fp0 = fp;
9552 crtc_state->dpll_hw_state.fp1 = fp2;
9553 }
9554
9555 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9556 struct intel_crtc_state *crtc_state)
9557 {
9558 struct drm_device *dev = crtc->base.dev;
9559 struct drm_i915_private *dev_priv = to_i915(dev);
9560 struct dpll reduced_clock;
9561 bool has_reduced_clock = false;
9562 struct intel_shared_dpll *pll;
9563 const struct intel_limit *limit;
9564 int refclk = 120000;
9565
9566 memset(&crtc_state->dpll_hw_state, 0,
9567 sizeof(crtc_state->dpll_hw_state));
9568
9569 crtc->lowfreq_avail = false;
9570
9571 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9572 if (!crtc_state->has_pch_encoder)
9573 return 0;
9574
9575 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9576 if (intel_panel_use_ssc(dev_priv)) {
9577 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9578 dev_priv->vbt.lvds_ssc_freq);
9579 refclk = dev_priv->vbt.lvds_ssc_freq;
9580 }
9581
9582 if (intel_is_dual_link_lvds(dev)) {
9583 if (refclk == 100000)
9584 limit = &intel_limits_ironlake_dual_lvds_100m;
9585 else
9586 limit = &intel_limits_ironlake_dual_lvds;
9587 } else {
9588 if (refclk == 100000)
9589 limit = &intel_limits_ironlake_single_lvds_100m;
9590 else
9591 limit = &intel_limits_ironlake_single_lvds;
9592 }
9593 } else {
9594 limit = &intel_limits_ironlake_dac;
9595 }
9596
9597 if (!crtc_state->clock_set &&
9598 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9599 refclk, NULL, &crtc_state->dpll)) {
9600 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9601 return -EINVAL;
9602 }
9603
9604 ironlake_compute_dpll(crtc, crtc_state,
9605 has_reduced_clock ? &reduced_clock : NULL);
9606
9607 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9608 if (pll == NULL) {
9609 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9610 pipe_name(crtc->pipe));
9611 return -EINVAL;
9612 }
9613
9614 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9615 has_reduced_clock)
9616 crtc->lowfreq_avail = true;
9617
9618 return 0;
9619 }
9620
9621 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9622 struct intel_link_m_n *m_n)
9623 {
9624 struct drm_device *dev = crtc->base.dev;
9625 struct drm_i915_private *dev_priv = to_i915(dev);
9626 enum pipe pipe = crtc->pipe;
9627
9628 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9629 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9630 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9631 & ~TU_SIZE_MASK;
9632 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9633 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9634 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9635 }
9636
9637 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9638 enum transcoder transcoder,
9639 struct intel_link_m_n *m_n,
9640 struct intel_link_m_n *m2_n2)
9641 {
9642 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9643 enum pipe pipe = crtc->pipe;
9644
9645 if (INTEL_GEN(dev_priv) >= 5) {
9646 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9647 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9648 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9649 & ~TU_SIZE_MASK;
9650 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9651 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9652 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9653 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9654 * gen < 8) and if DRRS is supported (to make sure the
9655 * registers are not unnecessarily read).
9656 */
9657 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
9658 crtc->config->has_drrs) {
9659 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9660 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9661 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9662 & ~TU_SIZE_MASK;
9663 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9664 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9665 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9666 }
9667 } else {
9668 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9669 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9670 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9671 & ~TU_SIZE_MASK;
9672 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9673 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9674 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9675 }
9676 }
9677
9678 void intel_dp_get_m_n(struct intel_crtc *crtc,
9679 struct intel_crtc_state *pipe_config)
9680 {
9681 if (pipe_config->has_pch_encoder)
9682 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9683 else
9684 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9685 &pipe_config->dp_m_n,
9686 &pipe_config->dp_m2_n2);
9687 }
9688
9689 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9690 struct intel_crtc_state *pipe_config)
9691 {
9692 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9693 &pipe_config->fdi_m_n, NULL);
9694 }
9695
9696 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9697 struct intel_crtc_state *pipe_config)
9698 {
9699 struct drm_device *dev = crtc->base.dev;
9700 struct drm_i915_private *dev_priv = to_i915(dev);
9701 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9702 uint32_t ps_ctrl = 0;
9703 int id = -1;
9704 int i;
9705
9706 /* find scaler attached to this pipe */
9707 for (i = 0; i < crtc->num_scalers; i++) {
9708 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9709 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9710 id = i;
9711 pipe_config->pch_pfit.enabled = true;
9712 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9713 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9714 break;
9715 }
9716 }
9717
9718 scaler_state->scaler_id = id;
9719 if (id >= 0) {
9720 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9721 } else {
9722 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9723 }
9724 }
9725
9726 static void
9727 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9728 struct intel_initial_plane_config *plane_config)
9729 {
9730 struct drm_device *dev = crtc->base.dev;
9731 struct drm_i915_private *dev_priv = to_i915(dev);
9732 u32 val, base, offset, stride_mult, tiling;
9733 int pipe = crtc->pipe;
9734 int fourcc, pixel_format;
9735 unsigned int aligned_height;
9736 struct drm_framebuffer *fb;
9737 struct intel_framebuffer *intel_fb;
9738
9739 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9740 if (!intel_fb) {
9741 DRM_DEBUG_KMS("failed to alloc fb\n");
9742 return;
9743 }
9744
9745 fb = &intel_fb->base;
9746
9747 val = I915_READ(PLANE_CTL(pipe, 0));
9748 if (!(val & PLANE_CTL_ENABLE))
9749 goto error;
9750
9751 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9752 fourcc = skl_format_to_fourcc(pixel_format,
9753 val & PLANE_CTL_ORDER_RGBX,
9754 val & PLANE_CTL_ALPHA_MASK);
9755 fb->pixel_format = fourcc;
9756 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9757
9758 tiling = val & PLANE_CTL_TILED_MASK;
9759 switch (tiling) {
9760 case PLANE_CTL_TILED_LINEAR:
9761 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9762 break;
9763 case PLANE_CTL_TILED_X:
9764 plane_config->tiling = I915_TILING_X;
9765 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9766 break;
9767 case PLANE_CTL_TILED_Y:
9768 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9769 break;
9770 case PLANE_CTL_TILED_YF:
9771 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9772 break;
9773 default:
9774 MISSING_CASE(tiling);
9775 goto error;
9776 }
9777
9778 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9779 plane_config->base = base;
9780
9781 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9782
9783 val = I915_READ(PLANE_SIZE(pipe, 0));
9784 fb->height = ((val >> 16) & 0xfff) + 1;
9785 fb->width = ((val >> 0) & 0x1fff) + 1;
9786
9787 val = I915_READ(PLANE_STRIDE(pipe, 0));
9788 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9789 fb->pixel_format);
9790 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9791
9792 aligned_height = intel_fb_align_height(dev, fb->height,
9793 fb->pixel_format,
9794 fb->modifier[0]);
9795
9796 plane_config->size = fb->pitches[0] * aligned_height;
9797
9798 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9799 pipe_name(pipe), fb->width, fb->height,
9800 fb->bits_per_pixel, base, fb->pitches[0],
9801 plane_config->size);
9802
9803 plane_config->fb = intel_fb;
9804 return;
9805
9806 error:
9807 kfree(intel_fb);
9808 }
9809
9810 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9811 struct intel_crtc_state *pipe_config)
9812 {
9813 struct drm_device *dev = crtc->base.dev;
9814 struct drm_i915_private *dev_priv = to_i915(dev);
9815 uint32_t tmp;
9816
9817 tmp = I915_READ(PF_CTL(crtc->pipe));
9818
9819 if (tmp & PF_ENABLE) {
9820 pipe_config->pch_pfit.enabled = true;
9821 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9822 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9823
9824 /* We currently do not free assignements of panel fitters on
9825 * ivb/hsw (since we don't use the higher upscaling modes which
9826 * differentiates them) so just WARN about this case for now. */
9827 if (IS_GEN7(dev_priv)) {
9828 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9829 PF_PIPE_SEL_IVB(crtc->pipe));
9830 }
9831 }
9832 }
9833
9834 static void
9835 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9836 struct intel_initial_plane_config *plane_config)
9837 {
9838 struct drm_device *dev = crtc->base.dev;
9839 struct drm_i915_private *dev_priv = to_i915(dev);
9840 u32 val, base, offset;
9841 int pipe = crtc->pipe;
9842 int fourcc, pixel_format;
9843 unsigned int aligned_height;
9844 struct drm_framebuffer *fb;
9845 struct intel_framebuffer *intel_fb;
9846
9847 val = I915_READ(DSPCNTR(pipe));
9848 if (!(val & DISPLAY_PLANE_ENABLE))
9849 return;
9850
9851 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9852 if (!intel_fb) {
9853 DRM_DEBUG_KMS("failed to alloc fb\n");
9854 return;
9855 }
9856
9857 fb = &intel_fb->base;
9858
9859 if (INTEL_GEN(dev_priv) >= 4) {
9860 if (val & DISPPLANE_TILED) {
9861 plane_config->tiling = I915_TILING_X;
9862 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9863 }
9864 }
9865
9866 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9867 fourcc = i9xx_format_to_fourcc(pixel_format);
9868 fb->pixel_format = fourcc;
9869 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9870
9871 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9872 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
9873 offset = I915_READ(DSPOFFSET(pipe));
9874 } else {
9875 if (plane_config->tiling)
9876 offset = I915_READ(DSPTILEOFF(pipe));
9877 else
9878 offset = I915_READ(DSPLINOFF(pipe));
9879 }
9880 plane_config->base = base;
9881
9882 val = I915_READ(PIPESRC(pipe));
9883 fb->width = ((val >> 16) & 0xfff) + 1;
9884 fb->height = ((val >> 0) & 0xfff) + 1;
9885
9886 val = I915_READ(DSPSTRIDE(pipe));
9887 fb->pitches[0] = val & 0xffffffc0;
9888
9889 aligned_height = intel_fb_align_height(dev, fb->height,
9890 fb->pixel_format,
9891 fb->modifier[0]);
9892
9893 plane_config->size = fb->pitches[0] * aligned_height;
9894
9895 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9896 pipe_name(pipe), fb->width, fb->height,
9897 fb->bits_per_pixel, base, fb->pitches[0],
9898 plane_config->size);
9899
9900 plane_config->fb = intel_fb;
9901 }
9902
9903 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9904 struct intel_crtc_state *pipe_config)
9905 {
9906 struct drm_device *dev = crtc->base.dev;
9907 struct drm_i915_private *dev_priv = to_i915(dev);
9908 enum intel_display_power_domain power_domain;
9909 uint32_t tmp;
9910 bool ret;
9911
9912 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9913 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9914 return false;
9915
9916 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9917 pipe_config->shared_dpll = NULL;
9918
9919 ret = false;
9920 tmp = I915_READ(PIPECONF(crtc->pipe));
9921 if (!(tmp & PIPECONF_ENABLE))
9922 goto out;
9923
9924 switch (tmp & PIPECONF_BPC_MASK) {
9925 case PIPECONF_6BPC:
9926 pipe_config->pipe_bpp = 18;
9927 break;
9928 case PIPECONF_8BPC:
9929 pipe_config->pipe_bpp = 24;
9930 break;
9931 case PIPECONF_10BPC:
9932 pipe_config->pipe_bpp = 30;
9933 break;
9934 case PIPECONF_12BPC:
9935 pipe_config->pipe_bpp = 36;
9936 break;
9937 default:
9938 break;
9939 }
9940
9941 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9942 pipe_config->limited_color_range = true;
9943
9944 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9945 struct intel_shared_dpll *pll;
9946 enum intel_dpll_id pll_id;
9947
9948 pipe_config->has_pch_encoder = true;
9949
9950 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9951 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9952 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9953
9954 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9955
9956 if (HAS_PCH_IBX(dev_priv)) {
9957 /*
9958 * The pipe->pch transcoder and pch transcoder->pll
9959 * mapping is fixed.
9960 */
9961 pll_id = (enum intel_dpll_id) crtc->pipe;
9962 } else {
9963 tmp = I915_READ(PCH_DPLL_SEL);
9964 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9965 pll_id = DPLL_ID_PCH_PLL_B;
9966 else
9967 pll_id= DPLL_ID_PCH_PLL_A;
9968 }
9969
9970 pipe_config->shared_dpll =
9971 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9972 pll = pipe_config->shared_dpll;
9973
9974 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9975 &pipe_config->dpll_hw_state));
9976
9977 tmp = pipe_config->dpll_hw_state.dpll;
9978 pipe_config->pixel_multiplier =
9979 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9980 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9981
9982 ironlake_pch_clock_get(crtc, pipe_config);
9983 } else {
9984 pipe_config->pixel_multiplier = 1;
9985 }
9986
9987 intel_get_pipe_timings(crtc, pipe_config);
9988 intel_get_pipe_src_size(crtc, pipe_config);
9989
9990 ironlake_get_pfit_config(crtc, pipe_config);
9991
9992 ret = true;
9993
9994 out:
9995 intel_display_power_put(dev_priv, power_domain);
9996
9997 return ret;
9998 }
9999
10000 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
10001 {
10002 struct drm_device *dev = &dev_priv->drm;
10003 struct intel_crtc *crtc;
10004
10005 for_each_intel_crtc(dev, crtc)
10006 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
10007 pipe_name(crtc->pipe));
10008
10009 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
10010 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
10011 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
10012 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
10013 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
10014 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
10015 "CPU PWM1 enabled\n");
10016 if (IS_HASWELL(dev_priv))
10017 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
10018 "CPU PWM2 enabled\n");
10019 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
10020 "PCH PWM1 enabled\n");
10021 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
10022 "Utility pin enabled\n");
10023 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
10024
10025 /*
10026 * In theory we can still leave IRQs enabled, as long as only the HPD
10027 * interrupts remain enabled. We used to check for that, but since it's
10028 * gen-specific and since we only disable LCPLL after we fully disable
10029 * the interrupts, the check below should be enough.
10030 */
10031 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
10032 }
10033
10034 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
10035 {
10036 if (IS_HASWELL(dev_priv))
10037 return I915_READ(D_COMP_HSW);
10038 else
10039 return I915_READ(D_COMP_BDW);
10040 }
10041
10042 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
10043 {
10044 if (IS_HASWELL(dev_priv)) {
10045 mutex_lock(&dev_priv->rps.hw_lock);
10046 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
10047 val))
10048 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
10049 mutex_unlock(&dev_priv->rps.hw_lock);
10050 } else {
10051 I915_WRITE(D_COMP_BDW, val);
10052 POSTING_READ(D_COMP_BDW);
10053 }
10054 }
10055
10056 /*
10057 * This function implements pieces of two sequences from BSpec:
10058 * - Sequence for display software to disable LCPLL
10059 * - Sequence for display software to allow package C8+
10060 * The steps implemented here are just the steps that actually touch the LCPLL
10061 * register. Callers should take care of disabling all the display engine
10062 * functions, doing the mode unset, fixing interrupts, etc.
10063 */
10064 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
10065 bool switch_to_fclk, bool allow_power_down)
10066 {
10067 uint32_t val;
10068
10069 assert_can_disable_lcpll(dev_priv);
10070
10071 val = I915_READ(LCPLL_CTL);
10072
10073 if (switch_to_fclk) {
10074 val |= LCPLL_CD_SOURCE_FCLK;
10075 I915_WRITE(LCPLL_CTL, val);
10076
10077 if (wait_for_us(I915_READ(LCPLL_CTL) &
10078 LCPLL_CD_SOURCE_FCLK_DONE, 1))
10079 DRM_ERROR("Switching to FCLK failed\n");
10080
10081 val = I915_READ(LCPLL_CTL);
10082 }
10083
10084 val |= LCPLL_PLL_DISABLE;
10085 I915_WRITE(LCPLL_CTL, val);
10086 POSTING_READ(LCPLL_CTL);
10087
10088 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
10089 DRM_ERROR("LCPLL still locked\n");
10090
10091 val = hsw_read_dcomp(dev_priv);
10092 val |= D_COMP_COMP_DISABLE;
10093 hsw_write_dcomp(dev_priv, val);
10094 ndelay(100);
10095
10096 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
10097 1))
10098 DRM_ERROR("D_COMP RCOMP still in progress\n");
10099
10100 if (allow_power_down) {
10101 val = I915_READ(LCPLL_CTL);
10102 val |= LCPLL_POWER_DOWN_ALLOW;
10103 I915_WRITE(LCPLL_CTL, val);
10104 POSTING_READ(LCPLL_CTL);
10105 }
10106 }
10107
10108 /*
10109 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
10110 * source.
10111 */
10112 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
10113 {
10114 uint32_t val;
10115
10116 val = I915_READ(LCPLL_CTL);
10117
10118 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
10119 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
10120 return;
10121
10122 /*
10123 * Make sure we're not on PC8 state before disabling PC8, otherwise
10124 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
10125 */
10126 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
10127
10128 if (val & LCPLL_POWER_DOWN_ALLOW) {
10129 val &= ~LCPLL_POWER_DOWN_ALLOW;
10130 I915_WRITE(LCPLL_CTL, val);
10131 POSTING_READ(LCPLL_CTL);
10132 }
10133
10134 val = hsw_read_dcomp(dev_priv);
10135 val |= D_COMP_COMP_FORCE;
10136 val &= ~D_COMP_COMP_DISABLE;
10137 hsw_write_dcomp(dev_priv, val);
10138
10139 val = I915_READ(LCPLL_CTL);
10140 val &= ~LCPLL_PLL_DISABLE;
10141 I915_WRITE(LCPLL_CTL, val);
10142
10143 if (intel_wait_for_register(dev_priv,
10144 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
10145 5))
10146 DRM_ERROR("LCPLL not locked yet\n");
10147
10148 if (val & LCPLL_CD_SOURCE_FCLK) {
10149 val = I915_READ(LCPLL_CTL);
10150 val &= ~LCPLL_CD_SOURCE_FCLK;
10151 I915_WRITE(LCPLL_CTL, val);
10152
10153 if (wait_for_us((I915_READ(LCPLL_CTL) &
10154 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10155 DRM_ERROR("Switching back to LCPLL failed\n");
10156 }
10157
10158 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
10159 intel_update_cdclk(dev_priv);
10160 }
10161
10162 /*
10163 * Package states C8 and deeper are really deep PC states that can only be
10164 * reached when all the devices on the system allow it, so even if the graphics
10165 * device allows PC8+, it doesn't mean the system will actually get to these
10166 * states. Our driver only allows PC8+ when going into runtime PM.
10167 *
10168 * The requirements for PC8+ are that all the outputs are disabled, the power
10169 * well is disabled and most interrupts are disabled, and these are also
10170 * requirements for runtime PM. When these conditions are met, we manually do
10171 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
10172 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
10173 * hang the machine.
10174 *
10175 * When we really reach PC8 or deeper states (not just when we allow it) we lose
10176 * the state of some registers, so when we come back from PC8+ we need to
10177 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
10178 * need to take care of the registers kept by RC6. Notice that this happens even
10179 * if we don't put the device in PCI D3 state (which is what currently happens
10180 * because of the runtime PM support).
10181 *
10182 * For more, read "Display Sequences for Package C8" on the hardware
10183 * documentation.
10184 */
10185 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
10186 {
10187 struct drm_device *dev = &dev_priv->drm;
10188 uint32_t val;
10189
10190 DRM_DEBUG_KMS("Enabling package C8+\n");
10191
10192 if (HAS_PCH_LPT_LP(dev_priv)) {
10193 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10194 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
10195 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10196 }
10197
10198 lpt_disable_clkout_dp(dev);
10199 hsw_disable_lcpll(dev_priv, true, true);
10200 }
10201
10202 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
10203 {
10204 struct drm_device *dev = &dev_priv->drm;
10205 uint32_t val;
10206
10207 DRM_DEBUG_KMS("Disabling package C8+\n");
10208
10209 hsw_restore_lcpll(dev_priv);
10210 lpt_init_pch_refclk(dev);
10211
10212 if (HAS_PCH_LPT_LP(dev_priv)) {
10213 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10214 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
10215 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10216 }
10217 }
10218
10219 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10220 {
10221 struct drm_device *dev = old_state->dev;
10222 struct intel_atomic_state *old_intel_state =
10223 to_intel_atomic_state(old_state);
10224 unsigned int req_cdclk = old_intel_state->dev_cdclk;
10225
10226 bxt_set_cdclk(to_i915(dev), req_cdclk);
10227 }
10228
10229 static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
10230 int pixel_rate)
10231 {
10232 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
10233
10234 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
10235 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
10236 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
10237
10238 /* BSpec says "Do not use DisplayPort with CDCLK less than
10239 * 432 MHz, audio enabled, port width x4, and link rate
10240 * HBR2 (5.4 GHz), or else there may be audio corruption or
10241 * screen corruption."
10242 */
10243 if (intel_crtc_has_dp_encoder(crtc_state) &&
10244 crtc_state->has_audio &&
10245 crtc_state->port_clock >= 540000 &&
10246 crtc_state->lane_count == 4)
10247 pixel_rate = max(432000, pixel_rate);
10248
10249 return pixel_rate;
10250 }
10251
10252 /* compute the max rate for new configuration */
10253 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
10254 {
10255 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10256 struct drm_i915_private *dev_priv = to_i915(state->dev);
10257 struct drm_crtc *crtc;
10258 struct drm_crtc_state *cstate;
10259 struct intel_crtc_state *crtc_state;
10260 unsigned max_pixel_rate = 0, i;
10261 enum pipe pipe;
10262
10263 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
10264 sizeof(intel_state->min_pixclk));
10265
10266 for_each_crtc_in_state(state, crtc, cstate, i) {
10267 int pixel_rate;
10268
10269 crtc_state = to_intel_crtc_state(cstate);
10270 if (!crtc_state->base.enable) {
10271 intel_state->min_pixclk[i] = 0;
10272 continue;
10273 }
10274
10275 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
10276
10277 if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
10278 pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
10279 pixel_rate);
10280
10281 intel_state->min_pixclk[i] = pixel_rate;
10282 }
10283
10284 for_each_pipe(dev_priv, pipe)
10285 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
10286
10287 return max_pixel_rate;
10288 }
10289
10290 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
10291 {
10292 struct drm_i915_private *dev_priv = to_i915(dev);
10293 uint32_t val, data;
10294 int ret;
10295
10296 if (WARN((I915_READ(LCPLL_CTL) &
10297 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
10298 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
10299 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
10300 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
10301 "trying to change cdclk frequency with cdclk not enabled\n"))
10302 return;
10303
10304 mutex_lock(&dev_priv->rps.hw_lock);
10305 ret = sandybridge_pcode_write(dev_priv,
10306 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
10307 mutex_unlock(&dev_priv->rps.hw_lock);
10308 if (ret) {
10309 DRM_ERROR("failed to inform pcode about cdclk change\n");
10310 return;
10311 }
10312
10313 val = I915_READ(LCPLL_CTL);
10314 val |= LCPLL_CD_SOURCE_FCLK;
10315 I915_WRITE(LCPLL_CTL, val);
10316
10317 if (wait_for_us(I915_READ(LCPLL_CTL) &
10318 LCPLL_CD_SOURCE_FCLK_DONE, 1))
10319 DRM_ERROR("Switching to FCLK failed\n");
10320
10321 val = I915_READ(LCPLL_CTL);
10322 val &= ~LCPLL_CLK_FREQ_MASK;
10323
10324 switch (cdclk) {
10325 case 450000:
10326 val |= LCPLL_CLK_FREQ_450;
10327 data = 0;
10328 break;
10329 case 540000:
10330 val |= LCPLL_CLK_FREQ_54O_BDW;
10331 data = 1;
10332 break;
10333 case 337500:
10334 val |= LCPLL_CLK_FREQ_337_5_BDW;
10335 data = 2;
10336 break;
10337 case 675000:
10338 val |= LCPLL_CLK_FREQ_675_BDW;
10339 data = 3;
10340 break;
10341 default:
10342 WARN(1, "invalid cdclk frequency\n");
10343 return;
10344 }
10345
10346 I915_WRITE(LCPLL_CTL, val);
10347
10348 val = I915_READ(LCPLL_CTL);
10349 val &= ~LCPLL_CD_SOURCE_FCLK;
10350 I915_WRITE(LCPLL_CTL, val);
10351
10352 if (wait_for_us((I915_READ(LCPLL_CTL) &
10353 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10354 DRM_ERROR("Switching back to LCPLL failed\n");
10355
10356 mutex_lock(&dev_priv->rps.hw_lock);
10357 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
10358 mutex_unlock(&dev_priv->rps.hw_lock);
10359
10360 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
10361
10362 intel_update_cdclk(dev_priv);
10363
10364 WARN(cdclk != dev_priv->cdclk_freq,
10365 "cdclk requested %d kHz but got %d kHz\n",
10366 cdclk, dev_priv->cdclk_freq);
10367 }
10368
10369 static int broadwell_calc_cdclk(int max_pixclk)
10370 {
10371 if (max_pixclk > 540000)
10372 return 675000;
10373 else if (max_pixclk > 450000)
10374 return 540000;
10375 else if (max_pixclk > 337500)
10376 return 450000;
10377 else
10378 return 337500;
10379 }
10380
10381 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
10382 {
10383 struct drm_i915_private *dev_priv = to_i915(state->dev);
10384 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10385 int max_pixclk = ilk_max_pixel_rate(state);
10386 int cdclk;
10387
10388 /*
10389 * FIXME should also account for plane ratio
10390 * once 64bpp pixel formats are supported.
10391 */
10392 cdclk = broadwell_calc_cdclk(max_pixclk);
10393
10394 if (cdclk > dev_priv->max_cdclk_freq) {
10395 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10396 cdclk, dev_priv->max_cdclk_freq);
10397 return -EINVAL;
10398 }
10399
10400 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10401 if (!intel_state->active_crtcs)
10402 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
10403
10404 return 0;
10405 }
10406
10407 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10408 {
10409 struct drm_device *dev = old_state->dev;
10410 struct intel_atomic_state *old_intel_state =
10411 to_intel_atomic_state(old_state);
10412 unsigned req_cdclk = old_intel_state->dev_cdclk;
10413
10414 broadwell_set_cdclk(dev, req_cdclk);
10415 }
10416
10417 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
10418 {
10419 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10420 struct drm_i915_private *dev_priv = to_i915(state->dev);
10421 const int max_pixclk = ilk_max_pixel_rate(state);
10422 int vco = intel_state->cdclk_pll_vco;
10423 int cdclk;
10424
10425 /*
10426 * FIXME should also account for plane ratio
10427 * once 64bpp pixel formats are supported.
10428 */
10429 cdclk = skl_calc_cdclk(max_pixclk, vco);
10430
10431 /*
10432 * FIXME move the cdclk caclulation to
10433 * compute_config() so we can fail gracegully.
10434 */
10435 if (cdclk > dev_priv->max_cdclk_freq) {
10436 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10437 cdclk, dev_priv->max_cdclk_freq);
10438 cdclk = dev_priv->max_cdclk_freq;
10439 }
10440
10441 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10442 if (!intel_state->active_crtcs)
10443 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
10444
10445 return 0;
10446 }
10447
10448 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10449 {
10450 struct drm_i915_private *dev_priv = to_i915(old_state->dev);
10451 struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
10452 unsigned int req_cdclk = intel_state->dev_cdclk;
10453 unsigned int req_vco = intel_state->cdclk_pll_vco;
10454
10455 skl_set_cdclk(dev_priv, req_cdclk, req_vco);
10456 }
10457
10458 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10459 struct intel_crtc_state *crtc_state)
10460 {
10461 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
10462 if (!intel_ddi_pll_select(crtc, crtc_state))
10463 return -EINVAL;
10464 }
10465
10466 crtc->lowfreq_avail = false;
10467
10468 return 0;
10469 }
10470
10471 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10472 enum port port,
10473 struct intel_crtc_state *pipe_config)
10474 {
10475 enum intel_dpll_id id;
10476
10477 switch (port) {
10478 case PORT_A:
10479 id = DPLL_ID_SKL_DPLL0;
10480 break;
10481 case PORT_B:
10482 id = DPLL_ID_SKL_DPLL1;
10483 break;
10484 case PORT_C:
10485 id = DPLL_ID_SKL_DPLL2;
10486 break;
10487 default:
10488 DRM_ERROR("Incorrect port type\n");
10489 return;
10490 }
10491
10492 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10493 }
10494
10495 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10496 enum port port,
10497 struct intel_crtc_state *pipe_config)
10498 {
10499 enum intel_dpll_id id;
10500 u32 temp;
10501
10502 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10503 id = temp >> (port * 3 + 1);
10504
10505 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
10506 return;
10507
10508 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10509 }
10510
10511 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10512 enum port port,
10513 struct intel_crtc_state *pipe_config)
10514 {
10515 enum intel_dpll_id id;
10516 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10517
10518 switch (ddi_pll_sel) {
10519 case PORT_CLK_SEL_WRPLL1:
10520 id = DPLL_ID_WRPLL1;
10521 break;
10522 case PORT_CLK_SEL_WRPLL2:
10523 id = DPLL_ID_WRPLL2;
10524 break;
10525 case PORT_CLK_SEL_SPLL:
10526 id = DPLL_ID_SPLL;
10527 break;
10528 case PORT_CLK_SEL_LCPLL_810:
10529 id = DPLL_ID_LCPLL_810;
10530 break;
10531 case PORT_CLK_SEL_LCPLL_1350:
10532 id = DPLL_ID_LCPLL_1350;
10533 break;
10534 case PORT_CLK_SEL_LCPLL_2700:
10535 id = DPLL_ID_LCPLL_2700;
10536 break;
10537 default:
10538 MISSING_CASE(ddi_pll_sel);
10539 /* fall through */
10540 case PORT_CLK_SEL_NONE:
10541 return;
10542 }
10543
10544 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10545 }
10546
10547 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10548 struct intel_crtc_state *pipe_config,
10549 unsigned long *power_domain_mask)
10550 {
10551 struct drm_device *dev = crtc->base.dev;
10552 struct drm_i915_private *dev_priv = to_i915(dev);
10553 enum intel_display_power_domain power_domain;
10554 u32 tmp;
10555
10556 /*
10557 * The pipe->transcoder mapping is fixed with the exception of the eDP
10558 * transcoder handled below.
10559 */
10560 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10561
10562 /*
10563 * XXX: Do intel_display_power_get_if_enabled before reading this (for
10564 * consistency and less surprising code; it's in always on power).
10565 */
10566 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10567 if (tmp & TRANS_DDI_FUNC_ENABLE) {
10568 enum pipe trans_edp_pipe;
10569 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10570 default:
10571 WARN(1, "unknown pipe linked to edp transcoder\n");
10572 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10573 case TRANS_DDI_EDP_INPUT_A_ON:
10574 trans_edp_pipe = PIPE_A;
10575 break;
10576 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10577 trans_edp_pipe = PIPE_B;
10578 break;
10579 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10580 trans_edp_pipe = PIPE_C;
10581 break;
10582 }
10583
10584 if (trans_edp_pipe == crtc->pipe)
10585 pipe_config->cpu_transcoder = TRANSCODER_EDP;
10586 }
10587
10588 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10589 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10590 return false;
10591 *power_domain_mask |= BIT(power_domain);
10592
10593 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10594
10595 return tmp & PIPECONF_ENABLE;
10596 }
10597
10598 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10599 struct intel_crtc_state *pipe_config,
10600 unsigned long *power_domain_mask)
10601 {
10602 struct drm_device *dev = crtc->base.dev;
10603 struct drm_i915_private *dev_priv = to_i915(dev);
10604 enum intel_display_power_domain power_domain;
10605 enum port port;
10606 enum transcoder cpu_transcoder;
10607 u32 tmp;
10608
10609 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10610 if (port == PORT_A)
10611 cpu_transcoder = TRANSCODER_DSI_A;
10612 else
10613 cpu_transcoder = TRANSCODER_DSI_C;
10614
10615 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10616 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10617 continue;
10618 *power_domain_mask |= BIT(power_domain);
10619
10620 /*
10621 * The PLL needs to be enabled with a valid divider
10622 * configuration, otherwise accessing DSI registers will hang
10623 * the machine. See BSpec North Display Engine
10624 * registers/MIPI[BXT]. We can break out here early, since we
10625 * need the same DSI PLL to be enabled for both DSI ports.
10626 */
10627 if (!intel_dsi_pll_is_enabled(dev_priv))
10628 break;
10629
10630 /* XXX: this works for video mode only */
10631 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10632 if (!(tmp & DPI_ENABLE))
10633 continue;
10634
10635 tmp = I915_READ(MIPI_CTRL(port));
10636 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10637 continue;
10638
10639 pipe_config->cpu_transcoder = cpu_transcoder;
10640 break;
10641 }
10642
10643 return transcoder_is_dsi(pipe_config->cpu_transcoder);
10644 }
10645
10646 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10647 struct intel_crtc_state *pipe_config)
10648 {
10649 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10650 struct intel_shared_dpll *pll;
10651 enum port port;
10652 uint32_t tmp;
10653
10654 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10655
10656 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10657
10658 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
10659 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10660 else if (IS_BROXTON(dev_priv))
10661 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10662 else
10663 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10664
10665 pll = pipe_config->shared_dpll;
10666 if (pll) {
10667 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10668 &pipe_config->dpll_hw_state));
10669 }
10670
10671 /*
10672 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10673 * DDI E. So just check whether this pipe is wired to DDI E and whether
10674 * the PCH transcoder is on.
10675 */
10676 if (INTEL_GEN(dev_priv) < 9 &&
10677 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10678 pipe_config->has_pch_encoder = true;
10679
10680 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10681 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10682 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10683
10684 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10685 }
10686 }
10687
10688 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10689 struct intel_crtc_state *pipe_config)
10690 {
10691 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10692 enum intel_display_power_domain power_domain;
10693 unsigned long power_domain_mask;
10694 bool active;
10695
10696 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10697 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10698 return false;
10699 power_domain_mask = BIT(power_domain);
10700
10701 pipe_config->shared_dpll = NULL;
10702
10703 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10704
10705 if (IS_BROXTON(dev_priv) &&
10706 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
10707 WARN_ON(active);
10708 active = true;
10709 }
10710
10711 if (!active)
10712 goto out;
10713
10714 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10715 haswell_get_ddi_port_state(crtc, pipe_config);
10716 intel_get_pipe_timings(crtc, pipe_config);
10717 }
10718
10719 intel_get_pipe_src_size(crtc, pipe_config);
10720
10721 pipe_config->gamma_mode =
10722 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10723
10724 if (INTEL_GEN(dev_priv) >= 9) {
10725 skl_init_scalers(dev_priv, crtc, pipe_config);
10726
10727 pipe_config->scaler_state.scaler_id = -1;
10728 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10729 }
10730
10731 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10732 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10733 power_domain_mask |= BIT(power_domain);
10734 if (INTEL_GEN(dev_priv) >= 9)
10735 skylake_get_pfit_config(crtc, pipe_config);
10736 else
10737 ironlake_get_pfit_config(crtc, pipe_config);
10738 }
10739
10740 if (IS_HASWELL(dev_priv))
10741 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10742 (I915_READ(IPS_CTL) & IPS_ENABLE);
10743
10744 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10745 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10746 pipe_config->pixel_multiplier =
10747 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10748 } else {
10749 pipe_config->pixel_multiplier = 1;
10750 }
10751
10752 out:
10753 for_each_power_domain(power_domain, power_domain_mask)
10754 intel_display_power_put(dev_priv, power_domain);
10755
10756 return active;
10757 }
10758
10759 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10760 const struct intel_plane_state *plane_state)
10761 {
10762 struct drm_device *dev = crtc->dev;
10763 struct drm_i915_private *dev_priv = to_i915(dev);
10764 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10765 uint32_t cntl = 0, size = 0;
10766
10767 if (plane_state && plane_state->base.visible) {
10768 unsigned int width = plane_state->base.crtc_w;
10769 unsigned int height = plane_state->base.crtc_h;
10770 unsigned int stride = roundup_pow_of_two(width) * 4;
10771
10772 switch (stride) {
10773 default:
10774 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10775 width, stride);
10776 stride = 256;
10777 /* fallthrough */
10778 case 256:
10779 case 512:
10780 case 1024:
10781 case 2048:
10782 break;
10783 }
10784
10785 cntl |= CURSOR_ENABLE |
10786 CURSOR_GAMMA_ENABLE |
10787 CURSOR_FORMAT_ARGB |
10788 CURSOR_STRIDE(stride);
10789
10790 size = (height << 12) | width;
10791 }
10792
10793 if (intel_crtc->cursor_cntl != 0 &&
10794 (intel_crtc->cursor_base != base ||
10795 intel_crtc->cursor_size != size ||
10796 intel_crtc->cursor_cntl != cntl)) {
10797 /* On these chipsets we can only modify the base/size/stride
10798 * whilst the cursor is disabled.
10799 */
10800 I915_WRITE(CURCNTR(PIPE_A), 0);
10801 POSTING_READ(CURCNTR(PIPE_A));
10802 intel_crtc->cursor_cntl = 0;
10803 }
10804
10805 if (intel_crtc->cursor_base != base) {
10806 I915_WRITE(CURBASE(PIPE_A), base);
10807 intel_crtc->cursor_base = base;
10808 }
10809
10810 if (intel_crtc->cursor_size != size) {
10811 I915_WRITE(CURSIZE, size);
10812 intel_crtc->cursor_size = size;
10813 }
10814
10815 if (intel_crtc->cursor_cntl != cntl) {
10816 I915_WRITE(CURCNTR(PIPE_A), cntl);
10817 POSTING_READ(CURCNTR(PIPE_A));
10818 intel_crtc->cursor_cntl = cntl;
10819 }
10820 }
10821
10822 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10823 const struct intel_plane_state *plane_state)
10824 {
10825 struct drm_device *dev = crtc->dev;
10826 struct drm_i915_private *dev_priv = to_i915(dev);
10827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10828 int pipe = intel_crtc->pipe;
10829 uint32_t cntl = 0;
10830
10831 if (plane_state && plane_state->base.visible) {
10832 cntl = MCURSOR_GAMMA_ENABLE;
10833 switch (plane_state->base.crtc_w) {
10834 case 64:
10835 cntl |= CURSOR_MODE_64_ARGB_AX;
10836 break;
10837 case 128:
10838 cntl |= CURSOR_MODE_128_ARGB_AX;
10839 break;
10840 case 256:
10841 cntl |= CURSOR_MODE_256_ARGB_AX;
10842 break;
10843 default:
10844 MISSING_CASE(plane_state->base.crtc_w);
10845 return;
10846 }
10847 cntl |= pipe << 28; /* Connect to correct pipe */
10848
10849 if (HAS_DDI(dev_priv))
10850 cntl |= CURSOR_PIPE_CSC_ENABLE;
10851
10852 if (plane_state->base.rotation & DRM_ROTATE_180)
10853 cntl |= CURSOR_ROTATE_180;
10854 }
10855
10856 if (intel_crtc->cursor_cntl != cntl) {
10857 I915_WRITE(CURCNTR(pipe), cntl);
10858 POSTING_READ(CURCNTR(pipe));
10859 intel_crtc->cursor_cntl = cntl;
10860 }
10861
10862 /* and commit changes on next vblank */
10863 I915_WRITE(CURBASE(pipe), base);
10864 POSTING_READ(CURBASE(pipe));
10865
10866 intel_crtc->cursor_base = base;
10867 }
10868
10869 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10870 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10871 const struct intel_plane_state *plane_state)
10872 {
10873 struct drm_device *dev = crtc->dev;
10874 struct drm_i915_private *dev_priv = to_i915(dev);
10875 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10876 int pipe = intel_crtc->pipe;
10877 u32 base = intel_crtc->cursor_addr;
10878 u32 pos = 0;
10879
10880 if (plane_state) {
10881 int x = plane_state->base.crtc_x;
10882 int y = plane_state->base.crtc_y;
10883
10884 if (x < 0) {
10885 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10886 x = -x;
10887 }
10888 pos |= x << CURSOR_X_SHIFT;
10889
10890 if (y < 0) {
10891 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10892 y = -y;
10893 }
10894 pos |= y << CURSOR_Y_SHIFT;
10895
10896 /* ILK+ do this automagically */
10897 if (HAS_GMCH_DISPLAY(dev_priv) &&
10898 plane_state->base.rotation & DRM_ROTATE_180) {
10899 base += (plane_state->base.crtc_h *
10900 plane_state->base.crtc_w - 1) * 4;
10901 }
10902 }
10903
10904 I915_WRITE(CURPOS(pipe), pos);
10905
10906 if (IS_845G(dev_priv) || IS_I865G(dev_priv))
10907 i845_update_cursor(crtc, base, plane_state);
10908 else
10909 i9xx_update_cursor(crtc, base, plane_state);
10910 }
10911
10912 static bool cursor_size_ok(struct drm_i915_private *dev_priv,
10913 uint32_t width, uint32_t height)
10914 {
10915 if (width == 0 || height == 0)
10916 return false;
10917
10918 /*
10919 * 845g/865g are special in that they are only limited by
10920 * the width of their cursors, the height is arbitrary up to
10921 * the precision of the register. Everything else requires
10922 * square cursors, limited to a few power-of-two sizes.
10923 */
10924 if (IS_845G(dev_priv) || IS_I865G(dev_priv)) {
10925 if ((width & 63) != 0)
10926 return false;
10927
10928 if (width > (IS_845G(dev_priv) ? 64 : 512))
10929 return false;
10930
10931 if (height > 1023)
10932 return false;
10933 } else {
10934 switch (width | height) {
10935 case 256:
10936 case 128:
10937 if (IS_GEN2(dev_priv))
10938 return false;
10939 case 64:
10940 break;
10941 default:
10942 return false;
10943 }
10944 }
10945
10946 return true;
10947 }
10948
10949 /* VESA 640x480x72Hz mode to set on the pipe */
10950 static struct drm_display_mode load_detect_mode = {
10951 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10952 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10953 };
10954
10955 struct drm_framebuffer *
10956 __intel_framebuffer_create(struct drm_device *dev,
10957 struct drm_mode_fb_cmd2 *mode_cmd,
10958 struct drm_i915_gem_object *obj)
10959 {
10960 struct intel_framebuffer *intel_fb;
10961 int ret;
10962
10963 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10964 if (!intel_fb)
10965 return ERR_PTR(-ENOMEM);
10966
10967 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10968 if (ret)
10969 goto err;
10970
10971 return &intel_fb->base;
10972
10973 err:
10974 kfree(intel_fb);
10975 return ERR_PTR(ret);
10976 }
10977
10978 static struct drm_framebuffer *
10979 intel_framebuffer_create(struct drm_device *dev,
10980 struct drm_mode_fb_cmd2 *mode_cmd,
10981 struct drm_i915_gem_object *obj)
10982 {
10983 struct drm_framebuffer *fb;
10984 int ret;
10985
10986 ret = i915_mutex_lock_interruptible(dev);
10987 if (ret)
10988 return ERR_PTR(ret);
10989 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10990 mutex_unlock(&dev->struct_mutex);
10991
10992 return fb;
10993 }
10994
10995 static u32
10996 intel_framebuffer_pitch_for_width(int width, int bpp)
10997 {
10998 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10999 return ALIGN(pitch, 64);
11000 }
11001
11002 static u32
11003 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
11004 {
11005 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
11006 return PAGE_ALIGN(pitch * mode->vdisplay);
11007 }
11008
11009 static struct drm_framebuffer *
11010 intel_framebuffer_create_for_mode(struct drm_device *dev,
11011 struct drm_display_mode *mode,
11012 int depth, int bpp)
11013 {
11014 struct drm_framebuffer *fb;
11015 struct drm_i915_gem_object *obj;
11016 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
11017
11018 obj = i915_gem_object_create(dev,
11019 intel_framebuffer_size_for_mode(mode, bpp));
11020 if (IS_ERR(obj))
11021 return ERR_CAST(obj);
11022
11023 mode_cmd.width = mode->hdisplay;
11024 mode_cmd.height = mode->vdisplay;
11025 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
11026 bpp);
11027 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
11028
11029 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
11030 if (IS_ERR(fb))
11031 i915_gem_object_put(obj);
11032
11033 return fb;
11034 }
11035
11036 static struct drm_framebuffer *
11037 mode_fits_in_fbdev(struct drm_device *dev,
11038 struct drm_display_mode *mode)
11039 {
11040 #ifdef CONFIG_DRM_FBDEV_EMULATION
11041 struct drm_i915_private *dev_priv = to_i915(dev);
11042 struct drm_i915_gem_object *obj;
11043 struct drm_framebuffer *fb;
11044
11045 if (!dev_priv->fbdev)
11046 return NULL;
11047
11048 if (!dev_priv->fbdev->fb)
11049 return NULL;
11050
11051 obj = dev_priv->fbdev->fb->obj;
11052 BUG_ON(!obj);
11053
11054 fb = &dev_priv->fbdev->fb->base;
11055 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
11056 fb->bits_per_pixel))
11057 return NULL;
11058
11059 if (obj->base.size < mode->vdisplay * fb->pitches[0])
11060 return NULL;
11061
11062 drm_framebuffer_reference(fb);
11063 return fb;
11064 #else
11065 return NULL;
11066 #endif
11067 }
11068
11069 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
11070 struct drm_crtc *crtc,
11071 struct drm_display_mode *mode,
11072 struct drm_framebuffer *fb,
11073 int x, int y)
11074 {
11075 struct drm_plane_state *plane_state;
11076 int hdisplay, vdisplay;
11077 int ret;
11078
11079 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
11080 if (IS_ERR(plane_state))
11081 return PTR_ERR(plane_state);
11082
11083 if (mode)
11084 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11085 else
11086 hdisplay = vdisplay = 0;
11087
11088 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
11089 if (ret)
11090 return ret;
11091 drm_atomic_set_fb_for_plane(plane_state, fb);
11092 plane_state->crtc_x = 0;
11093 plane_state->crtc_y = 0;
11094 plane_state->crtc_w = hdisplay;
11095 plane_state->crtc_h = vdisplay;
11096 plane_state->src_x = x << 16;
11097 plane_state->src_y = y << 16;
11098 plane_state->src_w = hdisplay << 16;
11099 plane_state->src_h = vdisplay << 16;
11100
11101 return 0;
11102 }
11103
11104 bool intel_get_load_detect_pipe(struct drm_connector *connector,
11105 struct drm_display_mode *mode,
11106 struct intel_load_detect_pipe *old,
11107 struct drm_modeset_acquire_ctx *ctx)
11108 {
11109 struct intel_crtc *intel_crtc;
11110 struct intel_encoder *intel_encoder =
11111 intel_attached_encoder(connector);
11112 struct drm_crtc *possible_crtc;
11113 struct drm_encoder *encoder = &intel_encoder->base;
11114 struct drm_crtc *crtc = NULL;
11115 struct drm_device *dev = encoder->dev;
11116 struct drm_i915_private *dev_priv = to_i915(dev);
11117 struct drm_framebuffer *fb;
11118 struct drm_mode_config *config = &dev->mode_config;
11119 struct drm_atomic_state *state = NULL, *restore_state = NULL;
11120 struct drm_connector_state *connector_state;
11121 struct intel_crtc_state *crtc_state;
11122 int ret, i = -1;
11123
11124 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11125 connector->base.id, connector->name,
11126 encoder->base.id, encoder->name);
11127
11128 old->restore_state = NULL;
11129
11130 retry:
11131 ret = drm_modeset_lock(&config->connection_mutex, ctx);
11132 if (ret)
11133 goto fail;
11134
11135 /*
11136 * Algorithm gets a little messy:
11137 *
11138 * - if the connector already has an assigned crtc, use it (but make
11139 * sure it's on first)
11140 *
11141 * - try to find the first unused crtc that can drive this connector,
11142 * and use that if we find one
11143 */
11144
11145 /* See if we already have a CRTC for this connector */
11146 if (connector->state->crtc) {
11147 crtc = connector->state->crtc;
11148
11149 ret = drm_modeset_lock(&crtc->mutex, ctx);
11150 if (ret)
11151 goto fail;
11152
11153 /* Make sure the crtc and connector are running */
11154 goto found;
11155 }
11156
11157 /* Find an unused one (if possible) */
11158 for_each_crtc(dev, possible_crtc) {
11159 i++;
11160 if (!(encoder->possible_crtcs & (1 << i)))
11161 continue;
11162
11163 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11164 if (ret)
11165 goto fail;
11166
11167 if (possible_crtc->state->enable) {
11168 drm_modeset_unlock(&possible_crtc->mutex);
11169 continue;
11170 }
11171
11172 crtc = possible_crtc;
11173 break;
11174 }
11175
11176 /*
11177 * If we didn't find an unused CRTC, don't use any.
11178 */
11179 if (!crtc) {
11180 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11181 goto fail;
11182 }
11183
11184 found:
11185 intel_crtc = to_intel_crtc(crtc);
11186
11187 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
11188 if (ret)
11189 goto fail;
11190
11191 state = drm_atomic_state_alloc(dev);
11192 restore_state = drm_atomic_state_alloc(dev);
11193 if (!state || !restore_state) {
11194 ret = -ENOMEM;
11195 goto fail;
11196 }
11197
11198 state->acquire_ctx = ctx;
11199 restore_state->acquire_ctx = ctx;
11200
11201 connector_state = drm_atomic_get_connector_state(state, connector);
11202 if (IS_ERR(connector_state)) {
11203 ret = PTR_ERR(connector_state);
11204 goto fail;
11205 }
11206
11207 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11208 if (ret)
11209 goto fail;
11210
11211 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11212 if (IS_ERR(crtc_state)) {
11213 ret = PTR_ERR(crtc_state);
11214 goto fail;
11215 }
11216
11217 crtc_state->base.active = crtc_state->base.enable = true;
11218
11219 if (!mode)
11220 mode = &load_detect_mode;
11221
11222 /* We need a framebuffer large enough to accommodate all accesses
11223 * that the plane may generate whilst we perform load detection.
11224 * We can not rely on the fbcon either being present (we get called
11225 * during its initialisation to detect all boot displays, or it may
11226 * not even exist) or that it is large enough to satisfy the
11227 * requested mode.
11228 */
11229 fb = mode_fits_in_fbdev(dev, mode);
11230 if (fb == NULL) {
11231 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
11232 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
11233 } else
11234 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
11235 if (IS_ERR(fb)) {
11236 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
11237 goto fail;
11238 }
11239
11240 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
11241 if (ret)
11242 goto fail;
11243
11244 drm_framebuffer_unreference(fb);
11245
11246 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
11247 if (ret)
11248 goto fail;
11249
11250 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11251 if (!ret)
11252 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11253 if (!ret)
11254 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
11255 if (ret) {
11256 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11257 goto fail;
11258 }
11259
11260 ret = drm_atomic_commit(state);
11261 if (ret) {
11262 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11263 goto fail;
11264 }
11265
11266 old->restore_state = restore_state;
11267
11268 /* let the connector get through one full cycle before testing */
11269 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
11270 return true;
11271
11272 fail:
11273 if (state) {
11274 drm_atomic_state_put(state);
11275 state = NULL;
11276 }
11277 if (restore_state) {
11278 drm_atomic_state_put(restore_state);
11279 restore_state = NULL;
11280 }
11281
11282 if (ret == -EDEADLK) {
11283 drm_modeset_backoff(ctx);
11284 goto retry;
11285 }
11286
11287 return false;
11288 }
11289
11290 void intel_release_load_detect_pipe(struct drm_connector *connector,
11291 struct intel_load_detect_pipe *old,
11292 struct drm_modeset_acquire_ctx *ctx)
11293 {
11294 struct intel_encoder *intel_encoder =
11295 intel_attached_encoder(connector);
11296 struct drm_encoder *encoder = &intel_encoder->base;
11297 struct drm_atomic_state *state = old->restore_state;
11298 int ret;
11299
11300 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11301 connector->base.id, connector->name,
11302 encoder->base.id, encoder->name);
11303
11304 if (!state)
11305 return;
11306
11307 ret = drm_atomic_commit(state);
11308 if (ret)
11309 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11310 drm_atomic_state_put(state);
11311 }
11312
11313 static int i9xx_pll_refclk(struct drm_device *dev,
11314 const struct intel_crtc_state *pipe_config)
11315 {
11316 struct drm_i915_private *dev_priv = to_i915(dev);
11317 u32 dpll = pipe_config->dpll_hw_state.dpll;
11318
11319 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11320 return dev_priv->vbt.lvds_ssc_freq;
11321 else if (HAS_PCH_SPLIT(dev_priv))
11322 return 120000;
11323 else if (!IS_GEN2(dev_priv))
11324 return 96000;
11325 else
11326 return 48000;
11327 }
11328
11329 /* Returns the clock of the currently programmed mode of the given pipe. */
11330 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11331 struct intel_crtc_state *pipe_config)
11332 {
11333 struct drm_device *dev = crtc->base.dev;
11334 struct drm_i915_private *dev_priv = to_i915(dev);
11335 int pipe = pipe_config->cpu_transcoder;
11336 u32 dpll = pipe_config->dpll_hw_state.dpll;
11337 u32 fp;
11338 struct dpll clock;
11339 int port_clock;
11340 int refclk = i9xx_pll_refclk(dev, pipe_config);
11341
11342 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11343 fp = pipe_config->dpll_hw_state.fp0;
11344 else
11345 fp = pipe_config->dpll_hw_state.fp1;
11346
11347 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11348 if (IS_PINEVIEW(dev_priv)) {
11349 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11350 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11351 } else {
11352 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11353 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11354 }
11355
11356 if (!IS_GEN2(dev_priv)) {
11357 if (IS_PINEVIEW(dev_priv))
11358 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11359 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11360 else
11361 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11362 DPLL_FPA01_P1_POST_DIV_SHIFT);
11363
11364 switch (dpll & DPLL_MODE_MASK) {
11365 case DPLLB_MODE_DAC_SERIAL:
11366 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11367 5 : 10;
11368 break;
11369 case DPLLB_MODE_LVDS:
11370 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11371 7 : 14;
11372 break;
11373 default:
11374 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11375 "mode\n", (int)(dpll & DPLL_MODE_MASK));
11376 return;
11377 }
11378
11379 if (IS_PINEVIEW(dev_priv))
11380 port_clock = pnv_calc_dpll_params(refclk, &clock);
11381 else
11382 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11383 } else {
11384 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
11385 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11386
11387 if (is_lvds) {
11388 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11389 DPLL_FPA01_P1_POST_DIV_SHIFT);
11390
11391 if (lvds & LVDS_CLKB_POWER_UP)
11392 clock.p2 = 7;
11393 else
11394 clock.p2 = 14;
11395 } else {
11396 if (dpll & PLL_P1_DIVIDE_BY_TWO)
11397 clock.p1 = 2;
11398 else {
11399 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11400 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11401 }
11402 if (dpll & PLL_P2_DIVIDE_BY_4)
11403 clock.p2 = 4;
11404 else
11405 clock.p2 = 2;
11406 }
11407
11408 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11409 }
11410
11411 /*
11412 * This value includes pixel_multiplier. We will use
11413 * port_clock to compute adjusted_mode.crtc_clock in the
11414 * encoder's get_config() function.
11415 */
11416 pipe_config->port_clock = port_clock;
11417 }
11418
11419 int intel_dotclock_calculate(int link_freq,
11420 const struct intel_link_m_n *m_n)
11421 {
11422 /*
11423 * The calculation for the data clock is:
11424 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11425 * But we want to avoid losing precison if possible, so:
11426 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11427 *
11428 * and the link clock is simpler:
11429 * link_clock = (m * link_clock) / n
11430 */
11431
11432 if (!m_n->link_n)
11433 return 0;
11434
11435 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
11436 }
11437
11438 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11439 struct intel_crtc_state *pipe_config)
11440 {
11441 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11442
11443 /* read out port_clock from the DPLL */
11444 i9xx_crtc_clock_get(crtc, pipe_config);
11445
11446 /*
11447 * In case there is an active pipe without active ports,
11448 * we may need some idea for the dotclock anyway.
11449 * Calculate one based on the FDI configuration.
11450 */
11451 pipe_config->base.adjusted_mode.crtc_clock =
11452 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11453 &pipe_config->fdi_m_n);
11454 }
11455
11456 /** Returns the currently programmed mode of the given pipe. */
11457 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
11458 struct drm_crtc *crtc)
11459 {
11460 struct drm_i915_private *dev_priv = to_i915(dev);
11461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11462 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
11463 struct drm_display_mode *mode;
11464 struct intel_crtc_state *pipe_config;
11465 int htot = I915_READ(HTOTAL(cpu_transcoder));
11466 int hsync = I915_READ(HSYNC(cpu_transcoder));
11467 int vtot = I915_READ(VTOTAL(cpu_transcoder));
11468 int vsync = I915_READ(VSYNC(cpu_transcoder));
11469 enum pipe pipe = intel_crtc->pipe;
11470
11471 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11472 if (!mode)
11473 return NULL;
11474
11475 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
11476 if (!pipe_config) {
11477 kfree(mode);
11478 return NULL;
11479 }
11480
11481 /*
11482 * Construct a pipe_config sufficient for getting the clock info
11483 * back out of crtc_clock_get.
11484 *
11485 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
11486 * to use a real value here instead.
11487 */
11488 pipe_config->cpu_transcoder = (enum transcoder) pipe;
11489 pipe_config->pixel_multiplier = 1;
11490 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
11491 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
11492 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
11493 i9xx_crtc_clock_get(intel_crtc, pipe_config);
11494
11495 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
11496 mode->hdisplay = (htot & 0xffff) + 1;
11497 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
11498 mode->hsync_start = (hsync & 0xffff) + 1;
11499 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
11500 mode->vdisplay = (vtot & 0xffff) + 1;
11501 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
11502 mode->vsync_start = (vsync & 0xffff) + 1;
11503 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
11504
11505 drm_mode_set_name(mode);
11506
11507 kfree(pipe_config);
11508
11509 return mode;
11510 }
11511
11512 static void intel_crtc_destroy(struct drm_crtc *crtc)
11513 {
11514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11515 struct drm_device *dev = crtc->dev;
11516 struct intel_flip_work *work;
11517
11518 spin_lock_irq(&dev->event_lock);
11519 work = intel_crtc->flip_work;
11520 intel_crtc->flip_work = NULL;
11521 spin_unlock_irq(&dev->event_lock);
11522
11523 if (work) {
11524 cancel_work_sync(&work->mmio_work);
11525 cancel_work_sync(&work->unpin_work);
11526 kfree(work);
11527 }
11528
11529 drm_crtc_cleanup(crtc);
11530
11531 kfree(intel_crtc);
11532 }
11533
11534 static void intel_unpin_work_fn(struct work_struct *__work)
11535 {
11536 struct intel_flip_work *work =
11537 container_of(__work, struct intel_flip_work, unpin_work);
11538 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11539 struct drm_device *dev = crtc->base.dev;
11540 struct drm_plane *primary = crtc->base.primary;
11541
11542 if (is_mmio_work(work))
11543 flush_work(&work->mmio_work);
11544
11545 mutex_lock(&dev->struct_mutex);
11546 intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
11547 i915_gem_object_put(work->pending_flip_obj);
11548 mutex_unlock(&dev->struct_mutex);
11549
11550 i915_gem_request_put(work->flip_queued_req);
11551
11552 intel_frontbuffer_flip_complete(to_i915(dev),
11553 to_intel_plane(primary)->frontbuffer_bit);
11554 intel_fbc_post_update(crtc);
11555 drm_framebuffer_unreference(work->old_fb);
11556
11557 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11558 atomic_dec(&crtc->unpin_work_count);
11559
11560 kfree(work);
11561 }
11562
11563 /* Is 'a' after or equal to 'b'? */
11564 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11565 {
11566 return !((a - b) & 0x80000000);
11567 }
11568
11569 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11570 struct intel_flip_work *work)
11571 {
11572 struct drm_device *dev = crtc->base.dev;
11573 struct drm_i915_private *dev_priv = to_i915(dev);
11574
11575 if (abort_flip_on_reset(crtc))
11576 return true;
11577
11578 /*
11579 * The relevant registers doen't exist on pre-ctg.
11580 * As the flip done interrupt doesn't trigger for mmio
11581 * flips on gmch platforms, a flip count check isn't
11582 * really needed there. But since ctg has the registers,
11583 * include it in the check anyway.
11584 */
11585 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11586 return true;
11587
11588 /*
11589 * BDW signals flip done immediately if the plane
11590 * is disabled, even if the plane enable is already
11591 * armed to occur at the next vblank :(
11592 */
11593
11594 /*
11595 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11596 * used the same base address. In that case the mmio flip might
11597 * have completed, but the CS hasn't even executed the flip yet.
11598 *
11599 * A flip count check isn't enough as the CS might have updated
11600 * the base address just after start of vblank, but before we
11601 * managed to process the interrupt. This means we'd complete the
11602 * CS flip too soon.
11603 *
11604 * Combining both checks should get us a good enough result. It may
11605 * still happen that the CS flip has been executed, but has not
11606 * yet actually completed. But in case the base address is the same
11607 * anyway, we don't really care.
11608 */
11609 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11610 crtc->flip_work->gtt_offset &&
11611 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11612 crtc->flip_work->flip_count);
11613 }
11614
11615 static bool
11616 __pageflip_finished_mmio(struct intel_crtc *crtc,
11617 struct intel_flip_work *work)
11618 {
11619 /*
11620 * MMIO work completes when vblank is different from
11621 * flip_queued_vblank.
11622 *
11623 * Reset counter value doesn't matter, this is handled by
11624 * i915_wait_request finishing early, so no need to handle
11625 * reset here.
11626 */
11627 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11628 }
11629
11630
11631 static bool pageflip_finished(struct intel_crtc *crtc,
11632 struct intel_flip_work *work)
11633 {
11634 if (!atomic_read(&work->pending))
11635 return false;
11636
11637 smp_rmb();
11638
11639 if (is_mmio_work(work))
11640 return __pageflip_finished_mmio(crtc, work);
11641 else
11642 return __pageflip_finished_cs(crtc, work);
11643 }
11644
11645 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11646 {
11647 struct drm_device *dev = &dev_priv->drm;
11648 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
11649 struct intel_flip_work *work;
11650 unsigned long flags;
11651
11652 /* Ignore early vblank irqs */
11653 if (!crtc)
11654 return;
11655
11656 /*
11657 * This is called both by irq handlers and the reset code (to complete
11658 * lost pageflips) so needs the full irqsave spinlocks.
11659 */
11660 spin_lock_irqsave(&dev->event_lock, flags);
11661 work = crtc->flip_work;
11662
11663 if (work != NULL &&
11664 !is_mmio_work(work) &&
11665 pageflip_finished(crtc, work))
11666 page_flip_completed(crtc);
11667
11668 spin_unlock_irqrestore(&dev->event_lock, flags);
11669 }
11670
11671 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11672 {
11673 struct drm_device *dev = &dev_priv->drm;
11674 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
11675 struct intel_flip_work *work;
11676 unsigned long flags;
11677
11678 /* Ignore early vblank irqs */
11679 if (!crtc)
11680 return;
11681
11682 /*
11683 * This is called both by irq handlers and the reset code (to complete
11684 * lost pageflips) so needs the full irqsave spinlocks.
11685 */
11686 spin_lock_irqsave(&dev->event_lock, flags);
11687 work = crtc->flip_work;
11688
11689 if (work != NULL &&
11690 is_mmio_work(work) &&
11691 pageflip_finished(crtc, work))
11692 page_flip_completed(crtc);
11693
11694 spin_unlock_irqrestore(&dev->event_lock, flags);
11695 }
11696
11697 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11698 struct intel_flip_work *work)
11699 {
11700 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11701
11702 /* Ensure that the work item is consistent when activating it ... */
11703 smp_mb__before_atomic();
11704 atomic_set(&work->pending, 1);
11705 }
11706
11707 static int intel_gen2_queue_flip(struct drm_device *dev,
11708 struct drm_crtc *crtc,
11709 struct drm_framebuffer *fb,
11710 struct drm_i915_gem_object *obj,
11711 struct drm_i915_gem_request *req,
11712 uint32_t flags)
11713 {
11714 struct intel_ring *ring = req->ring;
11715 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11716 u32 flip_mask;
11717 int ret;
11718
11719 ret = intel_ring_begin(req, 6);
11720 if (ret)
11721 return ret;
11722
11723 /* Can't queue multiple flips, so wait for the previous
11724 * one to finish before executing the next.
11725 */
11726 if (intel_crtc->plane)
11727 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11728 else
11729 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11730 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11731 intel_ring_emit(ring, MI_NOOP);
11732 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11733 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11734 intel_ring_emit(ring, fb->pitches[0]);
11735 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11736 intel_ring_emit(ring, 0); /* aux display base address, unused */
11737
11738 return 0;
11739 }
11740
11741 static int intel_gen3_queue_flip(struct drm_device *dev,
11742 struct drm_crtc *crtc,
11743 struct drm_framebuffer *fb,
11744 struct drm_i915_gem_object *obj,
11745 struct drm_i915_gem_request *req,
11746 uint32_t flags)
11747 {
11748 struct intel_ring *ring = req->ring;
11749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11750 u32 flip_mask;
11751 int ret;
11752
11753 ret = intel_ring_begin(req, 6);
11754 if (ret)
11755 return ret;
11756
11757 if (intel_crtc->plane)
11758 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11759 else
11760 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11761 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11762 intel_ring_emit(ring, MI_NOOP);
11763 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11764 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11765 intel_ring_emit(ring, fb->pitches[0]);
11766 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11767 intel_ring_emit(ring, MI_NOOP);
11768
11769 return 0;
11770 }
11771
11772 static int intel_gen4_queue_flip(struct drm_device *dev,
11773 struct drm_crtc *crtc,
11774 struct drm_framebuffer *fb,
11775 struct drm_i915_gem_object *obj,
11776 struct drm_i915_gem_request *req,
11777 uint32_t flags)
11778 {
11779 struct intel_ring *ring = req->ring;
11780 struct drm_i915_private *dev_priv = to_i915(dev);
11781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11782 uint32_t pf, pipesrc;
11783 int ret;
11784
11785 ret = intel_ring_begin(req, 4);
11786 if (ret)
11787 return ret;
11788
11789 /* i965+ uses the linear or tiled offsets from the
11790 * Display Registers (which do not change across a page-flip)
11791 * so we need only reprogram the base address.
11792 */
11793 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11794 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11795 intel_ring_emit(ring, fb->pitches[0]);
11796 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset |
11797 intel_fb_modifier_to_tiling(fb->modifier[0]));
11798
11799 /* XXX Enabling the panel-fitter across page-flip is so far
11800 * untested on non-native modes, so ignore it for now.
11801 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11802 */
11803 pf = 0;
11804 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11805 intel_ring_emit(ring, pf | pipesrc);
11806
11807 return 0;
11808 }
11809
11810 static int intel_gen6_queue_flip(struct drm_device *dev,
11811 struct drm_crtc *crtc,
11812 struct drm_framebuffer *fb,
11813 struct drm_i915_gem_object *obj,
11814 struct drm_i915_gem_request *req,
11815 uint32_t flags)
11816 {
11817 struct intel_ring *ring = req->ring;
11818 struct drm_i915_private *dev_priv = to_i915(dev);
11819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11820 uint32_t pf, pipesrc;
11821 int ret;
11822
11823 ret = intel_ring_begin(req, 4);
11824 if (ret)
11825 return ret;
11826
11827 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11828 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11829 intel_ring_emit(ring, fb->pitches[0] |
11830 intel_fb_modifier_to_tiling(fb->modifier[0]));
11831 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11832
11833 /* Contrary to the suggestions in the documentation,
11834 * "Enable Panel Fitter" does not seem to be required when page
11835 * flipping with a non-native mode, and worse causes a normal
11836 * modeset to fail.
11837 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11838 */
11839 pf = 0;
11840 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11841 intel_ring_emit(ring, pf | pipesrc);
11842
11843 return 0;
11844 }
11845
11846 static int intel_gen7_queue_flip(struct drm_device *dev,
11847 struct drm_crtc *crtc,
11848 struct drm_framebuffer *fb,
11849 struct drm_i915_gem_object *obj,
11850 struct drm_i915_gem_request *req,
11851 uint32_t flags)
11852 {
11853 struct drm_i915_private *dev_priv = to_i915(dev);
11854 struct intel_ring *ring = req->ring;
11855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11856 uint32_t plane_bit = 0;
11857 int len, ret;
11858
11859 switch (intel_crtc->plane) {
11860 case PLANE_A:
11861 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11862 break;
11863 case PLANE_B:
11864 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11865 break;
11866 case PLANE_C:
11867 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11868 break;
11869 default:
11870 WARN_ONCE(1, "unknown plane in flip command\n");
11871 return -ENODEV;
11872 }
11873
11874 len = 4;
11875 if (req->engine->id == RCS) {
11876 len += 6;
11877 /*
11878 * On Gen 8, SRM is now taking an extra dword to accommodate
11879 * 48bits addresses, and we need a NOOP for the batch size to
11880 * stay even.
11881 */
11882 if (IS_GEN8(dev_priv))
11883 len += 2;
11884 }
11885
11886 /*
11887 * BSpec MI_DISPLAY_FLIP for IVB:
11888 * "The full packet must be contained within the same cache line."
11889 *
11890 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11891 * cacheline, if we ever start emitting more commands before
11892 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11893 * then do the cacheline alignment, and finally emit the
11894 * MI_DISPLAY_FLIP.
11895 */
11896 ret = intel_ring_cacheline_align(req);
11897 if (ret)
11898 return ret;
11899
11900 ret = intel_ring_begin(req, len);
11901 if (ret)
11902 return ret;
11903
11904 /* Unmask the flip-done completion message. Note that the bspec says that
11905 * we should do this for both the BCS and RCS, and that we must not unmask
11906 * more than one flip event at any time (or ensure that one flip message
11907 * can be sent by waiting for flip-done prior to queueing new flips).
11908 * Experimentation says that BCS works despite DERRMR masking all
11909 * flip-done completion events and that unmasking all planes at once
11910 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11911 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11912 */
11913 if (req->engine->id == RCS) {
11914 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11915 intel_ring_emit_reg(ring, DERRMR);
11916 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11917 DERRMR_PIPEB_PRI_FLIP_DONE |
11918 DERRMR_PIPEC_PRI_FLIP_DONE));
11919 if (IS_GEN8(dev_priv))
11920 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11921 MI_SRM_LRM_GLOBAL_GTT);
11922 else
11923 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11924 MI_SRM_LRM_GLOBAL_GTT);
11925 intel_ring_emit_reg(ring, DERRMR);
11926 intel_ring_emit(ring,
11927 i915_ggtt_offset(req->engine->scratch) + 256);
11928 if (IS_GEN8(dev_priv)) {
11929 intel_ring_emit(ring, 0);
11930 intel_ring_emit(ring, MI_NOOP);
11931 }
11932 }
11933
11934 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11935 intel_ring_emit(ring, fb->pitches[0] |
11936 intel_fb_modifier_to_tiling(fb->modifier[0]));
11937 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11938 intel_ring_emit(ring, (MI_NOOP));
11939
11940 return 0;
11941 }
11942
11943 static bool use_mmio_flip(struct intel_engine_cs *engine,
11944 struct drm_i915_gem_object *obj)
11945 {
11946 /*
11947 * This is not being used for older platforms, because
11948 * non-availability of flip done interrupt forces us to use
11949 * CS flips. Older platforms derive flip done using some clever
11950 * tricks involving the flip_pending status bits and vblank irqs.
11951 * So using MMIO flips there would disrupt this mechanism.
11952 */
11953
11954 if (engine == NULL)
11955 return true;
11956
11957 if (INTEL_GEN(engine->i915) < 5)
11958 return false;
11959
11960 if (i915.use_mmio_flip < 0)
11961 return false;
11962 else if (i915.use_mmio_flip > 0)
11963 return true;
11964 else if (i915.enable_execlists)
11965 return true;
11966
11967 return engine != i915_gem_object_last_write_engine(obj);
11968 }
11969
11970 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11971 unsigned int rotation,
11972 struct intel_flip_work *work)
11973 {
11974 struct drm_device *dev = intel_crtc->base.dev;
11975 struct drm_i915_private *dev_priv = to_i915(dev);
11976 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11977 const enum pipe pipe = intel_crtc->pipe;
11978 u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
11979
11980 ctl = I915_READ(PLANE_CTL(pipe, 0));
11981 ctl &= ~PLANE_CTL_TILED_MASK;
11982 switch (fb->modifier[0]) {
11983 case DRM_FORMAT_MOD_NONE:
11984 break;
11985 case I915_FORMAT_MOD_X_TILED:
11986 ctl |= PLANE_CTL_TILED_X;
11987 break;
11988 case I915_FORMAT_MOD_Y_TILED:
11989 ctl |= PLANE_CTL_TILED_Y;
11990 break;
11991 case I915_FORMAT_MOD_Yf_TILED:
11992 ctl |= PLANE_CTL_TILED_YF;
11993 break;
11994 default:
11995 MISSING_CASE(fb->modifier[0]);
11996 }
11997
11998 /*
11999 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
12000 * PLANE_SURF updates, the update is then guaranteed to be atomic.
12001 */
12002 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
12003 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
12004
12005 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
12006 POSTING_READ(PLANE_SURF(pipe, 0));
12007 }
12008
12009 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
12010 struct intel_flip_work *work)
12011 {
12012 struct drm_device *dev = intel_crtc->base.dev;
12013 struct drm_i915_private *dev_priv = to_i915(dev);
12014 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
12015 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
12016 u32 dspcntr;
12017
12018 dspcntr = I915_READ(reg);
12019
12020 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
12021 dspcntr |= DISPPLANE_TILED;
12022 else
12023 dspcntr &= ~DISPPLANE_TILED;
12024
12025 I915_WRITE(reg, dspcntr);
12026
12027 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
12028 POSTING_READ(DSPSURF(intel_crtc->plane));
12029 }
12030
12031 static void intel_mmio_flip_work_func(struct work_struct *w)
12032 {
12033 struct intel_flip_work *work =
12034 container_of(w, struct intel_flip_work, mmio_work);
12035 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
12036 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12037 struct intel_framebuffer *intel_fb =
12038 to_intel_framebuffer(crtc->base.primary->fb);
12039 struct drm_i915_gem_object *obj = intel_fb->obj;
12040
12041 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
12042 WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
12043
12044 intel_pipe_update_start(crtc);
12045
12046 if (INTEL_GEN(dev_priv) >= 9)
12047 skl_do_mmio_flip(crtc, work->rotation, work);
12048 else
12049 /* use_mmio_flip() retricts MMIO flips to ilk+ */
12050 ilk_do_mmio_flip(crtc, work);
12051
12052 intel_pipe_update_end(crtc, work);
12053 }
12054
12055 static int intel_default_queue_flip(struct drm_device *dev,
12056 struct drm_crtc *crtc,
12057 struct drm_framebuffer *fb,
12058 struct drm_i915_gem_object *obj,
12059 struct drm_i915_gem_request *req,
12060 uint32_t flags)
12061 {
12062 return -ENODEV;
12063 }
12064
12065 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
12066 struct intel_crtc *intel_crtc,
12067 struct intel_flip_work *work)
12068 {
12069 u32 addr, vblank;
12070
12071 if (!atomic_read(&work->pending))
12072 return false;
12073
12074 smp_rmb();
12075
12076 vblank = intel_crtc_get_vblank_counter(intel_crtc);
12077 if (work->flip_ready_vblank == 0) {
12078 if (work->flip_queued_req &&
12079 !i915_gem_request_completed(work->flip_queued_req))
12080 return false;
12081
12082 work->flip_ready_vblank = vblank;
12083 }
12084
12085 if (vblank - work->flip_ready_vblank < 3)
12086 return false;
12087
12088 /* Potential stall - if we see that the flip has happened,
12089 * assume a missed interrupt. */
12090 if (INTEL_GEN(dev_priv) >= 4)
12091 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
12092 else
12093 addr = I915_READ(DSPADDR(intel_crtc->plane));
12094
12095 /* There is a potential issue here with a false positive after a flip
12096 * to the same address. We could address this by checking for a
12097 * non-incrementing frame counter.
12098 */
12099 return addr == work->gtt_offset;
12100 }
12101
12102 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
12103 {
12104 struct drm_device *dev = &dev_priv->drm;
12105 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12106 struct intel_flip_work *work;
12107
12108 WARN_ON(!in_interrupt());
12109
12110 if (crtc == NULL)
12111 return;
12112
12113 spin_lock(&dev->event_lock);
12114 work = crtc->flip_work;
12115
12116 if (work != NULL && !is_mmio_work(work) &&
12117 __pageflip_stall_check_cs(dev_priv, crtc, work)) {
12118 WARN_ONCE(1,
12119 "Kicking stuck page flip: queued at %d, now %d\n",
12120 work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
12121 page_flip_completed(crtc);
12122 work = NULL;
12123 }
12124
12125 if (work != NULL && !is_mmio_work(work) &&
12126 intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
12127 intel_queue_rps_boost_for_request(work->flip_queued_req);
12128 spin_unlock(&dev->event_lock);
12129 }
12130
12131 static int intel_crtc_page_flip(struct drm_crtc *crtc,
12132 struct drm_framebuffer *fb,
12133 struct drm_pending_vblank_event *event,
12134 uint32_t page_flip_flags)
12135 {
12136 struct drm_device *dev = crtc->dev;
12137 struct drm_i915_private *dev_priv = to_i915(dev);
12138 struct drm_framebuffer *old_fb = crtc->primary->fb;
12139 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12141 struct drm_plane *primary = crtc->primary;
12142 enum pipe pipe = intel_crtc->pipe;
12143 struct intel_flip_work *work;
12144 struct intel_engine_cs *engine;
12145 bool mmio_flip;
12146 struct drm_i915_gem_request *request;
12147 struct i915_vma *vma;
12148 int ret;
12149
12150 /*
12151 * drm_mode_page_flip_ioctl() should already catch this, but double
12152 * check to be safe. In the future we may enable pageflipping from
12153 * a disabled primary plane.
12154 */
12155 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
12156 return -EBUSY;
12157
12158 /* Can't change pixel format via MI display flips. */
12159 if (fb->pixel_format != crtc->primary->fb->pixel_format)
12160 return -EINVAL;
12161
12162 /*
12163 * TILEOFF/LINOFF registers can't be changed via MI display flips.
12164 * Note that pitch changes could also affect these register.
12165 */
12166 if (INTEL_GEN(dev_priv) > 3 &&
12167 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
12168 fb->pitches[0] != crtc->primary->fb->pitches[0]))
12169 return -EINVAL;
12170
12171 if (i915_terminally_wedged(&dev_priv->gpu_error))
12172 goto out_hang;
12173
12174 work = kzalloc(sizeof(*work), GFP_KERNEL);
12175 if (work == NULL)
12176 return -ENOMEM;
12177
12178 work->event = event;
12179 work->crtc = crtc;
12180 work->old_fb = old_fb;
12181 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
12182
12183 ret = drm_crtc_vblank_get(crtc);
12184 if (ret)
12185 goto free_work;
12186
12187 /* We borrow the event spin lock for protecting flip_work */
12188 spin_lock_irq(&dev->event_lock);
12189 if (intel_crtc->flip_work) {
12190 /* Before declaring the flip queue wedged, check if
12191 * the hardware completed the operation behind our backs.
12192 */
12193 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
12194 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
12195 page_flip_completed(intel_crtc);
12196 } else {
12197 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
12198 spin_unlock_irq(&dev->event_lock);
12199
12200 drm_crtc_vblank_put(crtc);
12201 kfree(work);
12202 return -EBUSY;
12203 }
12204 }
12205 intel_crtc->flip_work = work;
12206 spin_unlock_irq(&dev->event_lock);
12207
12208 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
12209 flush_workqueue(dev_priv->wq);
12210
12211 /* Reference the objects for the scheduled work. */
12212 drm_framebuffer_reference(work->old_fb);
12213
12214 crtc->primary->fb = fb;
12215 update_state_fb(crtc->primary);
12216
12217 work->pending_flip_obj = i915_gem_object_get(obj);
12218
12219 ret = i915_mutex_lock_interruptible(dev);
12220 if (ret)
12221 goto cleanup;
12222
12223 intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
12224 if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) {
12225 ret = -EIO;
12226 goto cleanup;
12227 }
12228
12229 atomic_inc(&intel_crtc->unpin_work_count);
12230
12231 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
12232 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
12233
12234 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
12235 engine = dev_priv->engine[BCS];
12236 if (fb->modifier[0] != old_fb->modifier[0])
12237 /* vlv: DISPLAY_FLIP fails to change tiling */
12238 engine = NULL;
12239 } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
12240 engine = dev_priv->engine[BCS];
12241 } else if (INTEL_GEN(dev_priv) >= 7) {
12242 engine = i915_gem_object_last_write_engine(obj);
12243 if (engine == NULL || engine->id != RCS)
12244 engine = dev_priv->engine[BCS];
12245 } else {
12246 engine = dev_priv->engine[RCS];
12247 }
12248
12249 mmio_flip = use_mmio_flip(engine, obj);
12250
12251 vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
12252 if (IS_ERR(vma)) {
12253 ret = PTR_ERR(vma);
12254 goto cleanup_pending;
12255 }
12256
12257 work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation);
12258 work->gtt_offset += intel_crtc->dspaddr_offset;
12259 work->rotation = crtc->primary->state->rotation;
12260
12261 /*
12262 * There's the potential that the next frame will not be compatible with
12263 * FBC, so we want to call pre_update() before the actual page flip.
12264 * The problem is that pre_update() caches some information about the fb
12265 * object, so we want to do this only after the object is pinned. Let's
12266 * be on the safe side and do this immediately before scheduling the
12267 * flip.
12268 */
12269 intel_fbc_pre_update(intel_crtc, intel_crtc->config,
12270 to_intel_plane_state(primary->state));
12271
12272 if (mmio_flip) {
12273 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
12274 queue_work(system_unbound_wq, &work->mmio_work);
12275 } else {
12276 request = i915_gem_request_alloc(engine, engine->last_context);
12277 if (IS_ERR(request)) {
12278 ret = PTR_ERR(request);
12279 goto cleanup_unpin;
12280 }
12281
12282 ret = i915_gem_request_await_object(request, obj, false);
12283 if (ret)
12284 goto cleanup_request;
12285
12286 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
12287 page_flip_flags);
12288 if (ret)
12289 goto cleanup_request;
12290
12291 intel_mark_page_flip_active(intel_crtc, work);
12292
12293 work->flip_queued_req = i915_gem_request_get(request);
12294 i915_add_request_no_flush(request);
12295 }
12296
12297 i915_gem_track_fb(intel_fb_obj(old_fb), obj,
12298 to_intel_plane(primary)->frontbuffer_bit);
12299 mutex_unlock(&dev->struct_mutex);
12300
12301 intel_frontbuffer_flip_prepare(to_i915(dev),
12302 to_intel_plane(primary)->frontbuffer_bit);
12303
12304 trace_i915_flip_request(intel_crtc->plane, obj);
12305
12306 return 0;
12307
12308 cleanup_request:
12309 i915_add_request_no_flush(request);
12310 cleanup_unpin:
12311 intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
12312 cleanup_pending:
12313 atomic_dec(&intel_crtc->unpin_work_count);
12314 mutex_unlock(&dev->struct_mutex);
12315 cleanup:
12316 crtc->primary->fb = old_fb;
12317 update_state_fb(crtc->primary);
12318
12319 i915_gem_object_put(obj);
12320 drm_framebuffer_unreference(work->old_fb);
12321
12322 spin_lock_irq(&dev->event_lock);
12323 intel_crtc->flip_work = NULL;
12324 spin_unlock_irq(&dev->event_lock);
12325
12326 drm_crtc_vblank_put(crtc);
12327 free_work:
12328 kfree(work);
12329
12330 if (ret == -EIO) {
12331 struct drm_atomic_state *state;
12332 struct drm_plane_state *plane_state;
12333
12334 out_hang:
12335 state = drm_atomic_state_alloc(dev);
12336 if (!state)
12337 return -ENOMEM;
12338 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
12339
12340 retry:
12341 plane_state = drm_atomic_get_plane_state(state, primary);
12342 ret = PTR_ERR_OR_ZERO(plane_state);
12343 if (!ret) {
12344 drm_atomic_set_fb_for_plane(plane_state, fb);
12345
12346 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
12347 if (!ret)
12348 ret = drm_atomic_commit(state);
12349 }
12350
12351 if (ret == -EDEADLK) {
12352 drm_modeset_backoff(state->acquire_ctx);
12353 drm_atomic_state_clear(state);
12354 goto retry;
12355 }
12356
12357 drm_atomic_state_put(state);
12358
12359 if (ret == 0 && event) {
12360 spin_lock_irq(&dev->event_lock);
12361 drm_crtc_send_vblank_event(crtc, event);
12362 spin_unlock_irq(&dev->event_lock);
12363 }
12364 }
12365 return ret;
12366 }
12367
12368
12369 /**
12370 * intel_wm_need_update - Check whether watermarks need updating
12371 * @plane: drm plane
12372 * @state: new plane state
12373 *
12374 * Check current plane state versus the new one to determine whether
12375 * watermarks need to be recalculated.
12376 *
12377 * Returns true or false.
12378 */
12379 static bool intel_wm_need_update(struct drm_plane *plane,
12380 struct drm_plane_state *state)
12381 {
12382 struct intel_plane_state *new = to_intel_plane_state(state);
12383 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
12384
12385 /* Update watermarks on tiling or size changes. */
12386 if (new->base.visible != cur->base.visible)
12387 return true;
12388
12389 if (!cur->base.fb || !new->base.fb)
12390 return false;
12391
12392 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
12393 cur->base.rotation != new->base.rotation ||
12394 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
12395 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
12396 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
12397 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
12398 return true;
12399
12400 return false;
12401 }
12402
12403 static bool needs_scaling(struct intel_plane_state *state)
12404 {
12405 int src_w = drm_rect_width(&state->base.src) >> 16;
12406 int src_h = drm_rect_height(&state->base.src) >> 16;
12407 int dst_w = drm_rect_width(&state->base.dst);
12408 int dst_h = drm_rect_height(&state->base.dst);
12409
12410 return (src_w != dst_w || src_h != dst_h);
12411 }
12412
12413 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
12414 struct drm_plane_state *plane_state)
12415 {
12416 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
12417 struct drm_crtc *crtc = crtc_state->crtc;
12418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12419 struct drm_plane *plane = plane_state->plane;
12420 struct drm_device *dev = crtc->dev;
12421 struct drm_i915_private *dev_priv = to_i915(dev);
12422 struct intel_plane_state *old_plane_state =
12423 to_intel_plane_state(plane->state);
12424 bool mode_changed = needs_modeset(crtc_state);
12425 bool was_crtc_enabled = crtc->state->active;
12426 bool is_crtc_enabled = crtc_state->active;
12427 bool turn_off, turn_on, visible, was_visible;
12428 struct drm_framebuffer *fb = plane_state->fb;
12429 int ret;
12430
12431 if (INTEL_GEN(dev_priv) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
12432 ret = skl_update_scaler_plane(
12433 to_intel_crtc_state(crtc_state),
12434 to_intel_plane_state(plane_state));
12435 if (ret)
12436 return ret;
12437 }
12438
12439 was_visible = old_plane_state->base.visible;
12440 visible = to_intel_plane_state(plane_state)->base.visible;
12441
12442 if (!was_crtc_enabled && WARN_ON(was_visible))
12443 was_visible = false;
12444
12445 /*
12446 * Visibility is calculated as if the crtc was on, but
12447 * after scaler setup everything depends on it being off
12448 * when the crtc isn't active.
12449 *
12450 * FIXME this is wrong for watermarks. Watermarks should also
12451 * be computed as if the pipe would be active. Perhaps move
12452 * per-plane wm computation to the .check_plane() hook, and
12453 * only combine the results from all planes in the current place?
12454 */
12455 if (!is_crtc_enabled)
12456 to_intel_plane_state(plane_state)->base.visible = visible = false;
12457
12458 if (!was_visible && !visible)
12459 return 0;
12460
12461 if (fb != old_plane_state->base.fb)
12462 pipe_config->fb_changed = true;
12463
12464 turn_off = was_visible && (!visible || mode_changed);
12465 turn_on = visible && (!was_visible || mode_changed);
12466
12467 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
12468 intel_crtc->base.base.id,
12469 intel_crtc->base.name,
12470 plane->base.id, plane->name,
12471 fb ? fb->base.id : -1);
12472
12473 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12474 plane->base.id, plane->name,
12475 was_visible, visible,
12476 turn_off, turn_on, mode_changed);
12477
12478 if (turn_on) {
12479 pipe_config->update_wm_pre = true;
12480
12481 /* must disable cxsr around plane enable/disable */
12482 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12483 pipe_config->disable_cxsr = true;
12484 } else if (turn_off) {
12485 pipe_config->update_wm_post = true;
12486
12487 /* must disable cxsr around plane enable/disable */
12488 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12489 pipe_config->disable_cxsr = true;
12490 } else if (intel_wm_need_update(plane, plane_state)) {
12491 /* FIXME bollocks */
12492 pipe_config->update_wm_pre = true;
12493 pipe_config->update_wm_post = true;
12494 }
12495
12496 /* Pre-gen9 platforms need two-step watermark updates */
12497 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12498 INTEL_GEN(dev_priv) < 9 && dev_priv->display.optimize_watermarks)
12499 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12500
12501 if (visible || was_visible)
12502 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
12503
12504 /*
12505 * WaCxSRDisabledForSpriteScaling:ivb
12506 *
12507 * cstate->update_wm was already set above, so this flag will
12508 * take effect when we commit and program watermarks.
12509 */
12510 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev_priv) &&
12511 needs_scaling(to_intel_plane_state(plane_state)) &&
12512 !needs_scaling(old_plane_state))
12513 pipe_config->disable_lp_wm = true;
12514
12515 return 0;
12516 }
12517
12518 static bool encoders_cloneable(const struct intel_encoder *a,
12519 const struct intel_encoder *b)
12520 {
12521 /* masks could be asymmetric, so check both ways */
12522 return a == b || (a->cloneable & (1 << b->type) &&
12523 b->cloneable & (1 << a->type));
12524 }
12525
12526 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12527 struct intel_crtc *crtc,
12528 struct intel_encoder *encoder)
12529 {
12530 struct intel_encoder *source_encoder;
12531 struct drm_connector *connector;
12532 struct drm_connector_state *connector_state;
12533 int i;
12534
12535 for_each_connector_in_state(state, connector, connector_state, i) {
12536 if (connector_state->crtc != &crtc->base)
12537 continue;
12538
12539 source_encoder =
12540 to_intel_encoder(connector_state->best_encoder);
12541 if (!encoders_cloneable(encoder, source_encoder))
12542 return false;
12543 }
12544
12545 return true;
12546 }
12547
12548 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12549 struct drm_crtc_state *crtc_state)
12550 {
12551 struct drm_device *dev = crtc->dev;
12552 struct drm_i915_private *dev_priv = to_i915(dev);
12553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12554 struct intel_crtc_state *pipe_config =
12555 to_intel_crtc_state(crtc_state);
12556 struct drm_atomic_state *state = crtc_state->state;
12557 int ret;
12558 bool mode_changed = needs_modeset(crtc_state);
12559
12560 if (mode_changed && !crtc_state->active)
12561 pipe_config->update_wm_post = true;
12562
12563 if (mode_changed && crtc_state->enable &&
12564 dev_priv->display.crtc_compute_clock &&
12565 !WARN_ON(pipe_config->shared_dpll)) {
12566 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12567 pipe_config);
12568 if (ret)
12569 return ret;
12570 }
12571
12572 if (crtc_state->color_mgmt_changed) {
12573 ret = intel_color_check(crtc, crtc_state);
12574 if (ret)
12575 return ret;
12576
12577 /*
12578 * Changing color management on Intel hardware is
12579 * handled as part of planes update.
12580 */
12581 crtc_state->planes_changed = true;
12582 }
12583
12584 ret = 0;
12585 if (dev_priv->display.compute_pipe_wm) {
12586 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12587 if (ret) {
12588 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12589 return ret;
12590 }
12591 }
12592
12593 if (dev_priv->display.compute_intermediate_wm &&
12594 !to_intel_atomic_state(state)->skip_intermediate_wm) {
12595 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12596 return 0;
12597
12598 /*
12599 * Calculate 'intermediate' watermarks that satisfy both the
12600 * old state and the new state. We can program these
12601 * immediately.
12602 */
12603 ret = dev_priv->display.compute_intermediate_wm(dev,
12604 intel_crtc,
12605 pipe_config);
12606 if (ret) {
12607 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12608 return ret;
12609 }
12610 } else if (dev_priv->display.compute_intermediate_wm) {
12611 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12612 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12613 }
12614
12615 if (INTEL_GEN(dev_priv) >= 9) {
12616 if (mode_changed)
12617 ret = skl_update_scaler_crtc(pipe_config);
12618
12619 if (!ret)
12620 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12621 pipe_config);
12622 }
12623
12624 return ret;
12625 }
12626
12627 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12628 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12629 .atomic_begin = intel_begin_crtc_commit,
12630 .atomic_flush = intel_finish_crtc_commit,
12631 .atomic_check = intel_crtc_atomic_check,
12632 };
12633
12634 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12635 {
12636 struct intel_connector *connector;
12637
12638 for_each_intel_connector(dev, connector) {
12639 if (connector->base.state->crtc)
12640 drm_connector_unreference(&connector->base);
12641
12642 if (connector->base.encoder) {
12643 connector->base.state->best_encoder =
12644 connector->base.encoder;
12645 connector->base.state->crtc =
12646 connector->base.encoder->crtc;
12647
12648 drm_connector_reference(&connector->base);
12649 } else {
12650 connector->base.state->best_encoder = NULL;
12651 connector->base.state->crtc = NULL;
12652 }
12653 }
12654 }
12655
12656 static void
12657 connected_sink_compute_bpp(struct intel_connector *connector,
12658 struct intel_crtc_state *pipe_config)
12659 {
12660 const struct drm_display_info *info = &connector->base.display_info;
12661 int bpp = pipe_config->pipe_bpp;
12662
12663 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12664 connector->base.base.id,
12665 connector->base.name);
12666
12667 /* Don't use an invalid EDID bpc value */
12668 if (info->bpc != 0 && info->bpc * 3 < bpp) {
12669 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12670 bpp, info->bpc * 3);
12671 pipe_config->pipe_bpp = info->bpc * 3;
12672 }
12673
12674 /* Clamp bpp to 8 on screens without EDID 1.4 */
12675 if (info->bpc == 0 && bpp > 24) {
12676 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12677 bpp);
12678 pipe_config->pipe_bpp = 24;
12679 }
12680 }
12681
12682 static int
12683 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12684 struct intel_crtc_state *pipe_config)
12685 {
12686 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12687 struct drm_atomic_state *state;
12688 struct drm_connector *connector;
12689 struct drm_connector_state *connector_state;
12690 int bpp, i;
12691
12692 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
12693 IS_CHERRYVIEW(dev_priv)))
12694 bpp = 10*3;
12695 else if (INTEL_GEN(dev_priv) >= 5)
12696 bpp = 12*3;
12697 else
12698 bpp = 8*3;
12699
12700
12701 pipe_config->pipe_bpp = bpp;
12702
12703 state = pipe_config->base.state;
12704
12705 /* Clamp display bpp to EDID value */
12706 for_each_connector_in_state(state, connector, connector_state, i) {
12707 if (connector_state->crtc != &crtc->base)
12708 continue;
12709
12710 connected_sink_compute_bpp(to_intel_connector(connector),
12711 pipe_config);
12712 }
12713
12714 return bpp;
12715 }
12716
12717 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12718 {
12719 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12720 "type: 0x%x flags: 0x%x\n",
12721 mode->crtc_clock,
12722 mode->crtc_hdisplay, mode->crtc_hsync_start,
12723 mode->crtc_hsync_end, mode->crtc_htotal,
12724 mode->crtc_vdisplay, mode->crtc_vsync_start,
12725 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12726 }
12727
12728 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12729 struct intel_crtc_state *pipe_config,
12730 const char *context)
12731 {
12732 struct drm_device *dev = crtc->base.dev;
12733 struct drm_i915_private *dev_priv = to_i915(dev);
12734 struct drm_plane *plane;
12735 struct intel_plane *intel_plane;
12736 struct intel_plane_state *state;
12737 struct drm_framebuffer *fb;
12738
12739 DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n",
12740 crtc->base.base.id, crtc->base.name,
12741 context, pipe_config, pipe_name(crtc->pipe));
12742
12743 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12744 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12745 pipe_config->pipe_bpp, pipe_config->dither);
12746 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12747 pipe_config->has_pch_encoder,
12748 pipe_config->fdi_lanes,
12749 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12750 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12751 pipe_config->fdi_m_n.tu);
12752 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12753 intel_crtc_has_dp_encoder(pipe_config),
12754 pipe_config->lane_count,
12755 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12756 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12757 pipe_config->dp_m_n.tu);
12758
12759 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12760 intel_crtc_has_dp_encoder(pipe_config),
12761 pipe_config->lane_count,
12762 pipe_config->dp_m2_n2.gmch_m,
12763 pipe_config->dp_m2_n2.gmch_n,
12764 pipe_config->dp_m2_n2.link_m,
12765 pipe_config->dp_m2_n2.link_n,
12766 pipe_config->dp_m2_n2.tu);
12767
12768 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12769 pipe_config->has_audio,
12770 pipe_config->has_infoframe);
12771
12772 DRM_DEBUG_KMS("requested mode:\n");
12773 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12774 DRM_DEBUG_KMS("adjusted mode:\n");
12775 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12776 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12777 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12778 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12779 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12780 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12781 crtc->num_scalers,
12782 pipe_config->scaler_state.scaler_users,
12783 pipe_config->scaler_state.scaler_id);
12784 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12785 pipe_config->gmch_pfit.control,
12786 pipe_config->gmch_pfit.pgm_ratios,
12787 pipe_config->gmch_pfit.lvds_border_bits);
12788 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12789 pipe_config->pch_pfit.pos,
12790 pipe_config->pch_pfit.size,
12791 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12792 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12793 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12794
12795 if (IS_BROXTON(dev_priv)) {
12796 DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12797 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12798 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12799 pipe_config->dpll_hw_state.ebb0,
12800 pipe_config->dpll_hw_state.ebb4,
12801 pipe_config->dpll_hw_state.pll0,
12802 pipe_config->dpll_hw_state.pll1,
12803 pipe_config->dpll_hw_state.pll2,
12804 pipe_config->dpll_hw_state.pll3,
12805 pipe_config->dpll_hw_state.pll6,
12806 pipe_config->dpll_hw_state.pll8,
12807 pipe_config->dpll_hw_state.pll9,
12808 pipe_config->dpll_hw_state.pll10,
12809 pipe_config->dpll_hw_state.pcsdw12);
12810 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
12811 DRM_DEBUG_KMS("dpll_hw_state: "
12812 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12813 pipe_config->dpll_hw_state.ctrl1,
12814 pipe_config->dpll_hw_state.cfgcr1,
12815 pipe_config->dpll_hw_state.cfgcr2);
12816 } else if (HAS_DDI(dev_priv)) {
12817 DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12818 pipe_config->dpll_hw_state.wrpll,
12819 pipe_config->dpll_hw_state.spll);
12820 } else {
12821 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12822 "fp0: 0x%x, fp1: 0x%x\n",
12823 pipe_config->dpll_hw_state.dpll,
12824 pipe_config->dpll_hw_state.dpll_md,
12825 pipe_config->dpll_hw_state.fp0,
12826 pipe_config->dpll_hw_state.fp1);
12827 }
12828
12829 DRM_DEBUG_KMS("planes on this crtc\n");
12830 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12831 struct drm_format_name_buf format_name;
12832 intel_plane = to_intel_plane(plane);
12833 if (intel_plane->pipe != crtc->pipe)
12834 continue;
12835
12836 state = to_intel_plane_state(plane->state);
12837 fb = state->base.fb;
12838 if (!fb) {
12839 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12840 plane->base.id, plane->name, state->scaler_id);
12841 continue;
12842 }
12843
12844 DRM_DEBUG_KMS("[PLANE:%d:%s] enabled",
12845 plane->base.id, plane->name);
12846 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s",
12847 fb->base.id, fb->width, fb->height,
12848 drm_get_format_name(fb->pixel_format, &format_name));
12849 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12850 state->scaler_id,
12851 state->base.src.x1 >> 16,
12852 state->base.src.y1 >> 16,
12853 drm_rect_width(&state->base.src) >> 16,
12854 drm_rect_height(&state->base.src) >> 16,
12855 state->base.dst.x1, state->base.dst.y1,
12856 drm_rect_width(&state->base.dst),
12857 drm_rect_height(&state->base.dst));
12858 }
12859 }
12860
12861 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12862 {
12863 struct drm_device *dev = state->dev;
12864 struct drm_connector *connector;
12865 unsigned int used_ports = 0;
12866 unsigned int used_mst_ports = 0;
12867
12868 /*
12869 * Walk the connector list instead of the encoder
12870 * list to detect the problem on ddi platforms
12871 * where there's just one encoder per digital port.
12872 */
12873 drm_for_each_connector(connector, dev) {
12874 struct drm_connector_state *connector_state;
12875 struct intel_encoder *encoder;
12876
12877 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12878 if (!connector_state)
12879 connector_state = connector->state;
12880
12881 if (!connector_state->best_encoder)
12882 continue;
12883
12884 encoder = to_intel_encoder(connector_state->best_encoder);
12885
12886 WARN_ON(!connector_state->crtc);
12887
12888 switch (encoder->type) {
12889 unsigned int port_mask;
12890 case INTEL_OUTPUT_UNKNOWN:
12891 if (WARN_ON(!HAS_DDI(to_i915(dev))))
12892 break;
12893 case INTEL_OUTPUT_DP:
12894 case INTEL_OUTPUT_HDMI:
12895 case INTEL_OUTPUT_EDP:
12896 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12897
12898 /* the same port mustn't appear more than once */
12899 if (used_ports & port_mask)
12900 return false;
12901
12902 used_ports |= port_mask;
12903 break;
12904 case INTEL_OUTPUT_DP_MST:
12905 used_mst_ports |=
12906 1 << enc_to_mst(&encoder->base)->primary->port;
12907 break;
12908 default:
12909 break;
12910 }
12911 }
12912
12913 /* can't mix MST and SST/HDMI on the same port */
12914 if (used_ports & used_mst_ports)
12915 return false;
12916
12917 return true;
12918 }
12919
12920 static void
12921 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12922 {
12923 struct drm_crtc_state tmp_state;
12924 struct intel_crtc_scaler_state scaler_state;
12925 struct intel_dpll_hw_state dpll_hw_state;
12926 struct intel_shared_dpll *shared_dpll;
12927 bool force_thru;
12928
12929 /* FIXME: before the switch to atomic started, a new pipe_config was
12930 * kzalloc'd. Code that depends on any field being zero should be
12931 * fixed, so that the crtc_state can be safely duplicated. For now,
12932 * only fields that are know to not cause problems are preserved. */
12933
12934 tmp_state = crtc_state->base;
12935 scaler_state = crtc_state->scaler_state;
12936 shared_dpll = crtc_state->shared_dpll;
12937 dpll_hw_state = crtc_state->dpll_hw_state;
12938 force_thru = crtc_state->pch_pfit.force_thru;
12939
12940 memset(crtc_state, 0, sizeof *crtc_state);
12941
12942 crtc_state->base = tmp_state;
12943 crtc_state->scaler_state = scaler_state;
12944 crtc_state->shared_dpll = shared_dpll;
12945 crtc_state->dpll_hw_state = dpll_hw_state;
12946 crtc_state->pch_pfit.force_thru = force_thru;
12947 }
12948
12949 static int
12950 intel_modeset_pipe_config(struct drm_crtc *crtc,
12951 struct intel_crtc_state *pipe_config)
12952 {
12953 struct drm_atomic_state *state = pipe_config->base.state;
12954 struct intel_encoder *encoder;
12955 struct drm_connector *connector;
12956 struct drm_connector_state *connector_state;
12957 int base_bpp, ret = -EINVAL;
12958 int i;
12959 bool retry = true;
12960
12961 clear_intel_crtc_state(pipe_config);
12962
12963 pipe_config->cpu_transcoder =
12964 (enum transcoder) to_intel_crtc(crtc)->pipe;
12965
12966 /*
12967 * Sanitize sync polarity flags based on requested ones. If neither
12968 * positive or negative polarity is requested, treat this as meaning
12969 * negative polarity.
12970 */
12971 if (!(pipe_config->base.adjusted_mode.flags &
12972 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12973 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12974
12975 if (!(pipe_config->base.adjusted_mode.flags &
12976 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12977 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12978
12979 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12980 pipe_config);
12981 if (base_bpp < 0)
12982 goto fail;
12983
12984 /*
12985 * Determine the real pipe dimensions. Note that stereo modes can
12986 * increase the actual pipe size due to the frame doubling and
12987 * insertion of additional space for blanks between the frame. This
12988 * is stored in the crtc timings. We use the requested mode to do this
12989 * computation to clearly distinguish it from the adjusted mode, which
12990 * can be changed by the connectors in the below retry loop.
12991 */
12992 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12993 &pipe_config->pipe_src_w,
12994 &pipe_config->pipe_src_h);
12995
12996 for_each_connector_in_state(state, connector, connector_state, i) {
12997 if (connector_state->crtc != crtc)
12998 continue;
12999
13000 encoder = to_intel_encoder(connector_state->best_encoder);
13001
13002 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
13003 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
13004 goto fail;
13005 }
13006
13007 /*
13008 * Determine output_types before calling the .compute_config()
13009 * hooks so that the hooks can use this information safely.
13010 */
13011 pipe_config->output_types |= 1 << encoder->type;
13012 }
13013
13014 encoder_retry:
13015 /* Ensure the port clock defaults are reset when retrying. */
13016 pipe_config->port_clock = 0;
13017 pipe_config->pixel_multiplier = 1;
13018
13019 /* Fill in default crtc timings, allow encoders to overwrite them. */
13020 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
13021 CRTC_STEREO_DOUBLE);
13022
13023 /* Pass our mode to the connectors and the CRTC to give them a chance to
13024 * adjust it according to limitations or connector properties, and also
13025 * a chance to reject the mode entirely.
13026 */
13027 for_each_connector_in_state(state, connector, connector_state, i) {
13028 if (connector_state->crtc != crtc)
13029 continue;
13030
13031 encoder = to_intel_encoder(connector_state->best_encoder);
13032
13033 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
13034 DRM_DEBUG_KMS("Encoder config failure\n");
13035 goto fail;
13036 }
13037 }
13038
13039 /* Set default port clock if not overwritten by the encoder. Needs to be
13040 * done afterwards in case the encoder adjusts the mode. */
13041 if (!pipe_config->port_clock)
13042 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
13043 * pipe_config->pixel_multiplier;
13044
13045 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13046 if (ret < 0) {
13047 DRM_DEBUG_KMS("CRTC fixup failed\n");
13048 goto fail;
13049 }
13050
13051 if (ret == RETRY) {
13052 if (WARN(!retry, "loop in pipe configuration computation\n")) {
13053 ret = -EINVAL;
13054 goto fail;
13055 }
13056
13057 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
13058 retry = false;
13059 goto encoder_retry;
13060 }
13061
13062 /* Dithering seems to not pass-through bits correctly when it should, so
13063 * only enable it on 6bpc panels. */
13064 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
13065 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13066 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13067
13068 fail:
13069 return ret;
13070 }
13071
13072 static void
13073 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
13074 {
13075 struct drm_crtc *crtc;
13076 struct drm_crtc_state *crtc_state;
13077 int i;
13078
13079 /* Double check state. */
13080 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13081 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
13082
13083 /* Update hwmode for vblank functions */
13084 if (crtc->state->active)
13085 crtc->hwmode = crtc->state->adjusted_mode;
13086 else
13087 crtc->hwmode.crtc_clock = 0;
13088
13089 /*
13090 * Update legacy state to satisfy fbc code. This can
13091 * be removed when fbc uses the atomic state.
13092 */
13093 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
13094 struct drm_plane_state *plane_state = crtc->primary->state;
13095
13096 crtc->primary->fb = plane_state->fb;
13097 crtc->x = plane_state->src_x >> 16;
13098 crtc->y = plane_state->src_y >> 16;
13099 }
13100 }
13101 }
13102
13103 static bool intel_fuzzy_clock_check(int clock1, int clock2)
13104 {
13105 int diff;
13106
13107 if (clock1 == clock2)
13108 return true;
13109
13110 if (!clock1 || !clock2)
13111 return false;
13112
13113 diff = abs(clock1 - clock2);
13114
13115 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13116 return true;
13117
13118 return false;
13119 }
13120
13121 static bool
13122 intel_compare_m_n(unsigned int m, unsigned int n,
13123 unsigned int m2, unsigned int n2,
13124 bool exact)
13125 {
13126 if (m == m2 && n == n2)
13127 return true;
13128
13129 if (exact || !m || !n || !m2 || !n2)
13130 return false;
13131
13132 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13133
13134 if (n > n2) {
13135 while (n > n2) {
13136 m2 <<= 1;
13137 n2 <<= 1;
13138 }
13139 } else if (n < n2) {
13140 while (n < n2) {
13141 m <<= 1;
13142 n <<= 1;
13143 }
13144 }
13145
13146 if (n != n2)
13147 return false;
13148
13149 return intel_fuzzy_clock_check(m, m2);
13150 }
13151
13152 static bool
13153 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13154 struct intel_link_m_n *m2_n2,
13155 bool adjust)
13156 {
13157 if (m_n->tu == m2_n2->tu &&
13158 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13159 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
13160 intel_compare_m_n(m_n->link_m, m_n->link_n,
13161 m2_n2->link_m, m2_n2->link_n, !adjust)) {
13162 if (adjust)
13163 *m2_n2 = *m_n;
13164
13165 return true;
13166 }
13167
13168 return false;
13169 }
13170
13171 static bool
13172 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
13173 struct intel_crtc_state *current_config,
13174 struct intel_crtc_state *pipe_config,
13175 bool adjust)
13176 {
13177 bool ret = true;
13178
13179 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
13180 do { \
13181 if (!adjust) \
13182 DRM_ERROR(fmt, ##__VA_ARGS__); \
13183 else \
13184 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
13185 } while (0)
13186
13187 #define PIPE_CONF_CHECK_X(name) \
13188 if (current_config->name != pipe_config->name) { \
13189 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13190 "(expected 0x%08x, found 0x%08x)\n", \
13191 current_config->name, \
13192 pipe_config->name); \
13193 ret = false; \
13194 }
13195
13196 #define PIPE_CONF_CHECK_I(name) \
13197 if (current_config->name != pipe_config->name) { \
13198 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13199 "(expected %i, found %i)\n", \
13200 current_config->name, \
13201 pipe_config->name); \
13202 ret = false; \
13203 }
13204
13205 #define PIPE_CONF_CHECK_P(name) \
13206 if (current_config->name != pipe_config->name) { \
13207 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13208 "(expected %p, found %p)\n", \
13209 current_config->name, \
13210 pipe_config->name); \
13211 ret = false; \
13212 }
13213
13214 #define PIPE_CONF_CHECK_M_N(name) \
13215 if (!intel_compare_link_m_n(&current_config->name, \
13216 &pipe_config->name,\
13217 adjust)) { \
13218 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13219 "(expected tu %i gmch %i/%i link %i/%i, " \
13220 "found tu %i, gmch %i/%i link %i/%i)\n", \
13221 current_config->name.tu, \
13222 current_config->name.gmch_m, \
13223 current_config->name.gmch_n, \
13224 current_config->name.link_m, \
13225 current_config->name.link_n, \
13226 pipe_config->name.tu, \
13227 pipe_config->name.gmch_m, \
13228 pipe_config->name.gmch_n, \
13229 pipe_config->name.link_m, \
13230 pipe_config->name.link_n); \
13231 ret = false; \
13232 }
13233
13234 /* This is required for BDW+ where there is only one set of registers for
13235 * switching between high and low RR.
13236 * This macro can be used whenever a comparison has to be made between one
13237 * hw state and multiple sw state variables.
13238 */
13239 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
13240 if (!intel_compare_link_m_n(&current_config->name, \
13241 &pipe_config->name, adjust) && \
13242 !intel_compare_link_m_n(&current_config->alt_name, \
13243 &pipe_config->name, adjust)) { \
13244 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13245 "(expected tu %i gmch %i/%i link %i/%i, " \
13246 "or tu %i gmch %i/%i link %i/%i, " \
13247 "found tu %i, gmch %i/%i link %i/%i)\n", \
13248 current_config->name.tu, \
13249 current_config->name.gmch_m, \
13250 current_config->name.gmch_n, \
13251 current_config->name.link_m, \
13252 current_config->name.link_n, \
13253 current_config->alt_name.tu, \
13254 current_config->alt_name.gmch_m, \
13255 current_config->alt_name.gmch_n, \
13256 current_config->alt_name.link_m, \
13257 current_config->alt_name.link_n, \
13258 pipe_config->name.tu, \
13259 pipe_config->name.gmch_m, \
13260 pipe_config->name.gmch_n, \
13261 pipe_config->name.link_m, \
13262 pipe_config->name.link_n); \
13263 ret = false; \
13264 }
13265
13266 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
13267 if ((current_config->name ^ pipe_config->name) & (mask)) { \
13268 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
13269 "(expected %i, found %i)\n", \
13270 current_config->name & (mask), \
13271 pipe_config->name & (mask)); \
13272 ret = false; \
13273 }
13274
13275 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
13276 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13277 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13278 "(expected %i, found %i)\n", \
13279 current_config->name, \
13280 pipe_config->name); \
13281 ret = false; \
13282 }
13283
13284 #define PIPE_CONF_QUIRK(quirk) \
13285 ((current_config->quirks | pipe_config->quirks) & (quirk))
13286
13287 PIPE_CONF_CHECK_I(cpu_transcoder);
13288
13289 PIPE_CONF_CHECK_I(has_pch_encoder);
13290 PIPE_CONF_CHECK_I(fdi_lanes);
13291 PIPE_CONF_CHECK_M_N(fdi_m_n);
13292
13293 PIPE_CONF_CHECK_I(lane_count);
13294 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13295
13296 if (INTEL_GEN(dev_priv) < 8) {
13297 PIPE_CONF_CHECK_M_N(dp_m_n);
13298
13299 if (current_config->has_drrs)
13300 PIPE_CONF_CHECK_M_N(dp_m2_n2);
13301 } else
13302 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13303
13304 PIPE_CONF_CHECK_X(output_types);
13305
13306 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
13307 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
13308 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
13309 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
13310 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
13311 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
13312
13313 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
13314 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
13315 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
13316 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
13317 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
13318 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
13319
13320 PIPE_CONF_CHECK_I(pixel_multiplier);
13321 PIPE_CONF_CHECK_I(has_hdmi_sink);
13322 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
13323 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13324 PIPE_CONF_CHECK_I(limited_color_range);
13325 PIPE_CONF_CHECK_I(has_infoframe);
13326
13327 PIPE_CONF_CHECK_I(has_audio);
13328
13329 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13330 DRM_MODE_FLAG_INTERLACE);
13331
13332 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13333 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13334 DRM_MODE_FLAG_PHSYNC);
13335 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13336 DRM_MODE_FLAG_NHSYNC);
13337 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13338 DRM_MODE_FLAG_PVSYNC);
13339 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13340 DRM_MODE_FLAG_NVSYNC);
13341 }
13342
13343 PIPE_CONF_CHECK_X(gmch_pfit.control);
13344 /* pfit ratios are autocomputed by the hw on gen4+ */
13345 if (INTEL_GEN(dev_priv) < 4)
13346 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13347 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13348
13349 if (!adjust) {
13350 PIPE_CONF_CHECK_I(pipe_src_w);
13351 PIPE_CONF_CHECK_I(pipe_src_h);
13352
13353 PIPE_CONF_CHECK_I(pch_pfit.enabled);
13354 if (current_config->pch_pfit.enabled) {
13355 PIPE_CONF_CHECK_X(pch_pfit.pos);
13356 PIPE_CONF_CHECK_X(pch_pfit.size);
13357 }
13358
13359 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13360 }
13361
13362 /* BDW+ don't expose a synchronous way to read the state */
13363 if (IS_HASWELL(dev_priv))
13364 PIPE_CONF_CHECK_I(ips_enabled);
13365
13366 PIPE_CONF_CHECK_I(double_wide);
13367
13368 PIPE_CONF_CHECK_P(shared_dpll);
13369 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13370 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13371 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13372 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13373 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13374 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13375 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13376 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13377 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13378
13379 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13380 PIPE_CONF_CHECK_X(dsi_pll.div);
13381
13382 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
13383 PIPE_CONF_CHECK_I(pipe_bpp);
13384
13385 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
13386 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13387
13388 #undef PIPE_CONF_CHECK_X
13389 #undef PIPE_CONF_CHECK_I
13390 #undef PIPE_CONF_CHECK_P
13391 #undef PIPE_CONF_CHECK_FLAGS
13392 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13393 #undef PIPE_CONF_QUIRK
13394 #undef INTEL_ERR_OR_DBG_KMS
13395
13396 return ret;
13397 }
13398
13399 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13400 const struct intel_crtc_state *pipe_config)
13401 {
13402 if (pipe_config->has_pch_encoder) {
13403 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13404 &pipe_config->fdi_m_n);
13405 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
13406
13407 /*
13408 * FDI already provided one idea for the dotclock.
13409 * Yell if the encoder disagrees.
13410 */
13411 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13412 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13413 fdi_dotclock, dotclock);
13414 }
13415 }
13416
13417 static void verify_wm_state(struct drm_crtc *crtc,
13418 struct drm_crtc_state *new_state)
13419 {
13420 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13421 struct skl_ddb_allocation hw_ddb, *sw_ddb;
13422 struct skl_pipe_wm hw_wm, *sw_wm;
13423 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
13424 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
13425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13426 const enum pipe pipe = intel_crtc->pipe;
13427 int plane, level, max_level = ilk_wm_max_level(dev_priv);
13428
13429 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
13430 return;
13431
13432 skl_pipe_wm_get_hw_state(crtc, &hw_wm);
13433 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
13434
13435 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
13436 sw_ddb = &dev_priv->wm.skl_hw.ddb;
13437
13438 /* planes */
13439 for_each_universal_plane(dev_priv, pipe, plane) {
13440 hw_plane_wm = &hw_wm.planes[plane];
13441 sw_plane_wm = &sw_wm->planes[plane];
13442
13443 /* Watermarks */
13444 for (level = 0; level <= max_level; level++) {
13445 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13446 &sw_plane_wm->wm[level]))
13447 continue;
13448
13449 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13450 pipe_name(pipe), plane + 1, level,
13451 sw_plane_wm->wm[level].plane_en,
13452 sw_plane_wm->wm[level].plane_res_b,
13453 sw_plane_wm->wm[level].plane_res_l,
13454 hw_plane_wm->wm[level].plane_en,
13455 hw_plane_wm->wm[level].plane_res_b,
13456 hw_plane_wm->wm[level].plane_res_l);
13457 }
13458
13459 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13460 &sw_plane_wm->trans_wm)) {
13461 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13462 pipe_name(pipe), plane + 1,
13463 sw_plane_wm->trans_wm.plane_en,
13464 sw_plane_wm->trans_wm.plane_res_b,
13465 sw_plane_wm->trans_wm.plane_res_l,
13466 hw_plane_wm->trans_wm.plane_en,
13467 hw_plane_wm->trans_wm.plane_res_b,
13468 hw_plane_wm->trans_wm.plane_res_l);
13469 }
13470
13471 /* DDB */
13472 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
13473 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
13474
13475 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13476 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
13477 pipe_name(pipe), plane + 1,
13478 sw_ddb_entry->start, sw_ddb_entry->end,
13479 hw_ddb_entry->start, hw_ddb_entry->end);
13480 }
13481 }
13482
13483 /*
13484 * cursor
13485 * If the cursor plane isn't active, we may not have updated it's ddb
13486 * allocation. In that case since the ddb allocation will be updated
13487 * once the plane becomes visible, we can skip this check
13488 */
13489 if (intel_crtc->cursor_addr) {
13490 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
13491 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
13492
13493 /* Watermarks */
13494 for (level = 0; level <= max_level; level++) {
13495 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13496 &sw_plane_wm->wm[level]))
13497 continue;
13498
13499 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13500 pipe_name(pipe), level,
13501 sw_plane_wm->wm[level].plane_en,
13502 sw_plane_wm->wm[level].plane_res_b,
13503 sw_plane_wm->wm[level].plane_res_l,
13504 hw_plane_wm->wm[level].plane_en,
13505 hw_plane_wm->wm[level].plane_res_b,
13506 hw_plane_wm->wm[level].plane_res_l);
13507 }
13508
13509 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13510 &sw_plane_wm->trans_wm)) {
13511 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13512 pipe_name(pipe),
13513 sw_plane_wm->trans_wm.plane_en,
13514 sw_plane_wm->trans_wm.plane_res_b,
13515 sw_plane_wm->trans_wm.plane_res_l,
13516 hw_plane_wm->trans_wm.plane_en,
13517 hw_plane_wm->trans_wm.plane_res_b,
13518 hw_plane_wm->trans_wm.plane_res_l);
13519 }
13520
13521 /* DDB */
13522 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
13523 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
13524
13525 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13526 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
13527 pipe_name(pipe),
13528 sw_ddb_entry->start, sw_ddb_entry->end,
13529 hw_ddb_entry->start, hw_ddb_entry->end);
13530 }
13531 }
13532 }
13533
13534 static void
13535 verify_connector_state(struct drm_device *dev,
13536 struct drm_atomic_state *state,
13537 struct drm_crtc *crtc)
13538 {
13539 struct drm_connector *connector;
13540 struct drm_connector_state *old_conn_state;
13541 int i;
13542
13543 for_each_connector_in_state(state, connector, old_conn_state, i) {
13544 struct drm_encoder *encoder = connector->encoder;
13545 struct drm_connector_state *state = connector->state;
13546
13547 if (state->crtc != crtc)
13548 continue;
13549
13550 intel_connector_verify_state(to_intel_connector(connector));
13551
13552 I915_STATE_WARN(state->best_encoder != encoder,
13553 "connector's atomic encoder doesn't match legacy encoder\n");
13554 }
13555 }
13556
13557 static void
13558 verify_encoder_state(struct drm_device *dev)
13559 {
13560 struct intel_encoder *encoder;
13561 struct intel_connector *connector;
13562
13563 for_each_intel_encoder(dev, encoder) {
13564 bool enabled = false;
13565 enum pipe pipe;
13566
13567 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13568 encoder->base.base.id,
13569 encoder->base.name);
13570
13571 for_each_intel_connector(dev, connector) {
13572 if (connector->base.state->best_encoder != &encoder->base)
13573 continue;
13574 enabled = true;
13575
13576 I915_STATE_WARN(connector->base.state->crtc !=
13577 encoder->base.crtc,
13578 "connector's crtc doesn't match encoder crtc\n");
13579 }
13580
13581 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13582 "encoder's enabled state mismatch "
13583 "(expected %i, found %i)\n",
13584 !!encoder->base.crtc, enabled);
13585
13586 if (!encoder->base.crtc) {
13587 bool active;
13588
13589 active = encoder->get_hw_state(encoder, &pipe);
13590 I915_STATE_WARN(active,
13591 "encoder detached but still enabled on pipe %c.\n",
13592 pipe_name(pipe));
13593 }
13594 }
13595 }
13596
13597 static void
13598 verify_crtc_state(struct drm_crtc *crtc,
13599 struct drm_crtc_state *old_crtc_state,
13600 struct drm_crtc_state *new_crtc_state)
13601 {
13602 struct drm_device *dev = crtc->dev;
13603 struct drm_i915_private *dev_priv = to_i915(dev);
13604 struct intel_encoder *encoder;
13605 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13606 struct intel_crtc_state *pipe_config, *sw_config;
13607 struct drm_atomic_state *old_state;
13608 bool active;
13609
13610 old_state = old_crtc_state->state;
13611 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
13612 pipe_config = to_intel_crtc_state(old_crtc_state);
13613 memset(pipe_config, 0, sizeof(*pipe_config));
13614 pipe_config->base.crtc = crtc;
13615 pipe_config->base.state = old_state;
13616
13617 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
13618
13619 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
13620
13621 /* hw state is inconsistent with the pipe quirk */
13622 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13623 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13624 active = new_crtc_state->active;
13625
13626 I915_STATE_WARN(new_crtc_state->active != active,
13627 "crtc active state doesn't match with hw state "
13628 "(expected %i, found %i)\n", new_crtc_state->active, active);
13629
13630 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13631 "transitional active state does not match atomic hw state "
13632 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13633
13634 for_each_encoder_on_crtc(dev, crtc, encoder) {
13635 enum pipe pipe;
13636
13637 active = encoder->get_hw_state(encoder, &pipe);
13638 I915_STATE_WARN(active != new_crtc_state->active,
13639 "[ENCODER:%i] active %i with crtc active %i\n",
13640 encoder->base.base.id, active, new_crtc_state->active);
13641
13642 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13643 "Encoder connected to wrong pipe %c\n",
13644 pipe_name(pipe));
13645
13646 if (active) {
13647 pipe_config->output_types |= 1 << encoder->type;
13648 encoder->get_config(encoder, pipe_config);
13649 }
13650 }
13651
13652 if (!new_crtc_state->active)
13653 return;
13654
13655 intel_pipe_config_sanity_check(dev_priv, pipe_config);
13656
13657 sw_config = to_intel_crtc_state(crtc->state);
13658 if (!intel_pipe_config_compare(dev_priv, sw_config,
13659 pipe_config, false)) {
13660 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13661 intel_dump_pipe_config(intel_crtc, pipe_config,
13662 "[hw state]");
13663 intel_dump_pipe_config(intel_crtc, sw_config,
13664 "[sw state]");
13665 }
13666 }
13667
13668 static void
13669 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13670 struct intel_shared_dpll *pll,
13671 struct drm_crtc *crtc,
13672 struct drm_crtc_state *new_state)
13673 {
13674 struct intel_dpll_hw_state dpll_hw_state;
13675 unsigned crtc_mask;
13676 bool active;
13677
13678 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13679
13680 DRM_DEBUG_KMS("%s\n", pll->name);
13681
13682 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13683
13684 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13685 I915_STATE_WARN(!pll->on && pll->active_mask,
13686 "pll in active use but not on in sw tracking\n");
13687 I915_STATE_WARN(pll->on && !pll->active_mask,
13688 "pll is on but not used by any active crtc\n");
13689 I915_STATE_WARN(pll->on != active,
13690 "pll on state mismatch (expected %i, found %i)\n",
13691 pll->on, active);
13692 }
13693
13694 if (!crtc) {
13695 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13696 "more active pll users than references: %x vs %x\n",
13697 pll->active_mask, pll->config.crtc_mask);
13698
13699 return;
13700 }
13701
13702 crtc_mask = 1 << drm_crtc_index(crtc);
13703
13704 if (new_state->active)
13705 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13706 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13707 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13708 else
13709 I915_STATE_WARN(pll->active_mask & crtc_mask,
13710 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13711 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13712
13713 I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13714 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13715 crtc_mask, pll->config.crtc_mask);
13716
13717 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13718 &dpll_hw_state,
13719 sizeof(dpll_hw_state)),
13720 "pll hw state mismatch\n");
13721 }
13722
13723 static void
13724 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13725 struct drm_crtc_state *old_crtc_state,
13726 struct drm_crtc_state *new_crtc_state)
13727 {
13728 struct drm_i915_private *dev_priv = to_i915(dev);
13729 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13730 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13731
13732 if (new_state->shared_dpll)
13733 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13734
13735 if (old_state->shared_dpll &&
13736 old_state->shared_dpll != new_state->shared_dpll) {
13737 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13738 struct intel_shared_dpll *pll = old_state->shared_dpll;
13739
13740 I915_STATE_WARN(pll->active_mask & crtc_mask,
13741 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13742 pipe_name(drm_crtc_index(crtc)));
13743 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13744 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13745 pipe_name(drm_crtc_index(crtc)));
13746 }
13747 }
13748
13749 static void
13750 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13751 struct drm_atomic_state *state,
13752 struct drm_crtc_state *old_state,
13753 struct drm_crtc_state *new_state)
13754 {
13755 if (!needs_modeset(new_state) &&
13756 !to_intel_crtc_state(new_state)->update_pipe)
13757 return;
13758
13759 verify_wm_state(crtc, new_state);
13760 verify_connector_state(crtc->dev, state, crtc);
13761 verify_crtc_state(crtc, old_state, new_state);
13762 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13763 }
13764
13765 static void
13766 verify_disabled_dpll_state(struct drm_device *dev)
13767 {
13768 struct drm_i915_private *dev_priv = to_i915(dev);
13769 int i;
13770
13771 for (i = 0; i < dev_priv->num_shared_dpll; i++)
13772 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13773 }
13774
13775 static void
13776 intel_modeset_verify_disabled(struct drm_device *dev,
13777 struct drm_atomic_state *state)
13778 {
13779 verify_encoder_state(dev);
13780 verify_connector_state(dev, state, NULL);
13781 verify_disabled_dpll_state(dev);
13782 }
13783
13784 static void update_scanline_offset(struct intel_crtc *crtc)
13785 {
13786 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13787
13788 /*
13789 * The scanline counter increments at the leading edge of hsync.
13790 *
13791 * On most platforms it starts counting from vtotal-1 on the
13792 * first active line. That means the scanline counter value is
13793 * always one less than what we would expect. Ie. just after
13794 * start of vblank, which also occurs at start of hsync (on the
13795 * last active line), the scanline counter will read vblank_start-1.
13796 *
13797 * On gen2 the scanline counter starts counting from 1 instead
13798 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13799 * to keep the value positive), instead of adding one.
13800 *
13801 * On HSW+ the behaviour of the scanline counter depends on the output
13802 * type. For DP ports it behaves like most other platforms, but on HDMI
13803 * there's an extra 1 line difference. So we need to add two instead of
13804 * one to the value.
13805 */
13806 if (IS_GEN2(dev_priv)) {
13807 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13808 int vtotal;
13809
13810 vtotal = adjusted_mode->crtc_vtotal;
13811 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13812 vtotal /= 2;
13813
13814 crtc->scanline_offset = vtotal - 1;
13815 } else if (HAS_DDI(dev_priv) &&
13816 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
13817 crtc->scanline_offset = 2;
13818 } else
13819 crtc->scanline_offset = 1;
13820 }
13821
13822 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13823 {
13824 struct drm_device *dev = state->dev;
13825 struct drm_i915_private *dev_priv = to_i915(dev);
13826 struct intel_shared_dpll_config *shared_dpll = NULL;
13827 struct drm_crtc *crtc;
13828 struct drm_crtc_state *crtc_state;
13829 int i;
13830
13831 if (!dev_priv->display.crtc_compute_clock)
13832 return;
13833
13834 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13836 struct intel_shared_dpll *old_dpll =
13837 to_intel_crtc_state(crtc->state)->shared_dpll;
13838
13839 if (!needs_modeset(crtc_state))
13840 continue;
13841
13842 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13843
13844 if (!old_dpll)
13845 continue;
13846
13847 if (!shared_dpll)
13848 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13849
13850 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13851 }
13852 }
13853
13854 /*
13855 * This implements the workaround described in the "notes" section of the mode
13856 * set sequence documentation. When going from no pipes or single pipe to
13857 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13858 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13859 */
13860 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13861 {
13862 struct drm_crtc_state *crtc_state;
13863 struct intel_crtc *intel_crtc;
13864 struct drm_crtc *crtc;
13865 struct intel_crtc_state *first_crtc_state = NULL;
13866 struct intel_crtc_state *other_crtc_state = NULL;
13867 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13868 int i;
13869
13870 /* look at all crtc's that are going to be enabled in during modeset */
13871 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13872 intel_crtc = to_intel_crtc(crtc);
13873
13874 if (!crtc_state->active || !needs_modeset(crtc_state))
13875 continue;
13876
13877 if (first_crtc_state) {
13878 other_crtc_state = to_intel_crtc_state(crtc_state);
13879 break;
13880 } else {
13881 first_crtc_state = to_intel_crtc_state(crtc_state);
13882 first_pipe = intel_crtc->pipe;
13883 }
13884 }
13885
13886 /* No workaround needed? */
13887 if (!first_crtc_state)
13888 return 0;
13889
13890 /* w/a possibly needed, check how many crtc's are already enabled. */
13891 for_each_intel_crtc(state->dev, intel_crtc) {
13892 struct intel_crtc_state *pipe_config;
13893
13894 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13895 if (IS_ERR(pipe_config))
13896 return PTR_ERR(pipe_config);
13897
13898 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13899
13900 if (!pipe_config->base.active ||
13901 needs_modeset(&pipe_config->base))
13902 continue;
13903
13904 /* 2 or more enabled crtcs means no need for w/a */
13905 if (enabled_pipe != INVALID_PIPE)
13906 return 0;
13907
13908 enabled_pipe = intel_crtc->pipe;
13909 }
13910
13911 if (enabled_pipe != INVALID_PIPE)
13912 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13913 else if (other_crtc_state)
13914 other_crtc_state->hsw_workaround_pipe = first_pipe;
13915
13916 return 0;
13917 }
13918
13919 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13920 {
13921 struct drm_crtc *crtc;
13922 struct drm_crtc_state *crtc_state;
13923 int ret = 0;
13924
13925 /* add all active pipes to the state */
13926 for_each_crtc(state->dev, crtc) {
13927 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13928 if (IS_ERR(crtc_state))
13929 return PTR_ERR(crtc_state);
13930
13931 if (!crtc_state->active || needs_modeset(crtc_state))
13932 continue;
13933
13934 crtc_state->mode_changed = true;
13935
13936 ret = drm_atomic_add_affected_connectors(state, crtc);
13937 if (ret)
13938 break;
13939
13940 ret = drm_atomic_add_affected_planes(state, crtc);
13941 if (ret)
13942 break;
13943 }
13944
13945 return ret;
13946 }
13947
13948 static int intel_modeset_checks(struct drm_atomic_state *state)
13949 {
13950 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13951 struct drm_i915_private *dev_priv = to_i915(state->dev);
13952 struct drm_crtc *crtc;
13953 struct drm_crtc_state *crtc_state;
13954 int ret = 0, i;
13955
13956 if (!check_digital_port_conflicts(state)) {
13957 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13958 return -EINVAL;
13959 }
13960
13961 intel_state->modeset = true;
13962 intel_state->active_crtcs = dev_priv->active_crtcs;
13963
13964 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13965 if (crtc_state->active)
13966 intel_state->active_crtcs |= 1 << i;
13967 else
13968 intel_state->active_crtcs &= ~(1 << i);
13969
13970 if (crtc_state->active != crtc->state->active)
13971 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13972 }
13973
13974 /*
13975 * See if the config requires any additional preparation, e.g.
13976 * to adjust global state with pipes off. We need to do this
13977 * here so we can get the modeset_pipe updated config for the new
13978 * mode set on this crtc. For other crtcs we need to use the
13979 * adjusted_mode bits in the crtc directly.
13980 */
13981 if (dev_priv->display.modeset_calc_cdclk) {
13982 if (!intel_state->cdclk_pll_vco)
13983 intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
13984 if (!intel_state->cdclk_pll_vco)
13985 intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
13986
13987 ret = dev_priv->display.modeset_calc_cdclk(state);
13988 if (ret < 0)
13989 return ret;
13990
13991 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13992 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
13993 ret = intel_modeset_all_pipes(state);
13994
13995 if (ret < 0)
13996 return ret;
13997
13998 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13999 intel_state->cdclk, intel_state->dev_cdclk);
14000 } else
14001 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
14002
14003 intel_modeset_clear_plls(state);
14004
14005 if (IS_HASWELL(dev_priv))
14006 return haswell_mode_set_planes_workaround(state);
14007
14008 return 0;
14009 }
14010
14011 /*
14012 * Handle calculation of various watermark data at the end of the atomic check
14013 * phase. The code here should be run after the per-crtc and per-plane 'check'
14014 * handlers to ensure that all derived state has been updated.
14015 */
14016 static int calc_watermark_data(struct drm_atomic_state *state)
14017 {
14018 struct drm_device *dev = state->dev;
14019 struct drm_i915_private *dev_priv = to_i915(dev);
14020
14021 /* Is there platform-specific watermark information to calculate? */
14022 if (dev_priv->display.compute_global_watermarks)
14023 return dev_priv->display.compute_global_watermarks(state);
14024
14025 return 0;
14026 }
14027
14028 /**
14029 * intel_atomic_check - validate state object
14030 * @dev: drm device
14031 * @state: state to validate
14032 */
14033 static int intel_atomic_check(struct drm_device *dev,
14034 struct drm_atomic_state *state)
14035 {
14036 struct drm_i915_private *dev_priv = to_i915(dev);
14037 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14038 struct drm_crtc *crtc;
14039 struct drm_crtc_state *crtc_state;
14040 int ret, i;
14041 bool any_ms = false;
14042
14043 ret = drm_atomic_helper_check_modeset(dev, state);
14044 if (ret)
14045 return ret;
14046
14047 for_each_crtc_in_state(state, crtc, crtc_state, i) {
14048 struct intel_crtc_state *pipe_config =
14049 to_intel_crtc_state(crtc_state);
14050
14051 /* Catch I915_MODE_FLAG_INHERITED */
14052 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
14053 crtc_state->mode_changed = true;
14054
14055 if (!needs_modeset(crtc_state))
14056 continue;
14057
14058 if (!crtc_state->enable) {
14059 any_ms = true;
14060 continue;
14061 }
14062
14063 /* FIXME: For only active_changed we shouldn't need to do any
14064 * state recomputation at all. */
14065
14066 ret = drm_atomic_add_affected_connectors(state, crtc);
14067 if (ret)
14068 return ret;
14069
14070 ret = intel_modeset_pipe_config(crtc, pipe_config);
14071 if (ret) {
14072 intel_dump_pipe_config(to_intel_crtc(crtc),
14073 pipe_config, "[failed]");
14074 return ret;
14075 }
14076
14077 if (i915.fastboot &&
14078 intel_pipe_config_compare(dev_priv,
14079 to_intel_crtc_state(crtc->state),
14080 pipe_config, true)) {
14081 crtc_state->mode_changed = false;
14082 to_intel_crtc_state(crtc_state)->update_pipe = true;
14083 }
14084
14085 if (needs_modeset(crtc_state))
14086 any_ms = true;
14087
14088 ret = drm_atomic_add_affected_planes(state, crtc);
14089 if (ret)
14090 return ret;
14091
14092 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
14093 needs_modeset(crtc_state) ?
14094 "[modeset]" : "[fastset]");
14095 }
14096
14097 if (any_ms) {
14098 ret = intel_modeset_checks(state);
14099
14100 if (ret)
14101 return ret;
14102 } else
14103 intel_state->cdclk = dev_priv->cdclk_freq;
14104
14105 ret = drm_atomic_helper_check_planes(dev, state);
14106 if (ret)
14107 return ret;
14108
14109 intel_fbc_choose_crtc(dev_priv, state);
14110 return calc_watermark_data(state);
14111 }
14112
14113 static int intel_atomic_prepare_commit(struct drm_device *dev,
14114 struct drm_atomic_state *state)
14115 {
14116 struct drm_i915_private *dev_priv = to_i915(dev);
14117 struct drm_crtc_state *crtc_state;
14118 struct drm_crtc *crtc;
14119 int i, ret;
14120
14121 for_each_crtc_in_state(state, crtc, crtc_state, i) {
14122 if (state->legacy_cursor_update)
14123 continue;
14124
14125 ret = intel_crtc_wait_for_pending_flips(crtc);
14126 if (ret)
14127 return ret;
14128
14129 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
14130 flush_workqueue(dev_priv->wq);
14131 }
14132
14133 ret = mutex_lock_interruptible(&dev->struct_mutex);
14134 if (ret)
14135 return ret;
14136
14137 ret = drm_atomic_helper_prepare_planes(dev, state);
14138 mutex_unlock(&dev->struct_mutex);
14139
14140 return ret;
14141 }
14142
14143 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14144 {
14145 struct drm_device *dev = crtc->base.dev;
14146
14147 if (!dev->max_vblank_count)
14148 return drm_accurate_vblank_count(&crtc->base);
14149
14150 return dev->driver->get_vblank_counter(dev, crtc->pipe);
14151 }
14152
14153 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
14154 struct drm_i915_private *dev_priv,
14155 unsigned crtc_mask)
14156 {
14157 unsigned last_vblank_count[I915_MAX_PIPES];
14158 enum pipe pipe;
14159 int ret;
14160
14161 if (!crtc_mask)
14162 return;
14163
14164 for_each_pipe(dev_priv, pipe) {
14165 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
14166 pipe);
14167
14168 if (!((1 << pipe) & crtc_mask))
14169 continue;
14170
14171 ret = drm_crtc_vblank_get(&crtc->base);
14172 if (WARN_ON(ret != 0)) {
14173 crtc_mask &= ~(1 << pipe);
14174 continue;
14175 }
14176
14177 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
14178 }
14179
14180 for_each_pipe(dev_priv, pipe) {
14181 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
14182 pipe);
14183 long lret;
14184
14185 if (!((1 << pipe) & crtc_mask))
14186 continue;
14187
14188 lret = wait_event_timeout(dev->vblank[pipe].queue,
14189 last_vblank_count[pipe] !=
14190 drm_crtc_vblank_count(&crtc->base),
14191 msecs_to_jiffies(50));
14192
14193 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
14194
14195 drm_crtc_vblank_put(&crtc->base);
14196 }
14197 }
14198
14199 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
14200 {
14201 /* fb updated, need to unpin old fb */
14202 if (crtc_state->fb_changed)
14203 return true;
14204
14205 /* wm changes, need vblank before final wm's */
14206 if (crtc_state->update_wm_post)
14207 return true;
14208
14209 /*
14210 * cxsr is re-enabled after vblank.
14211 * This is already handled by crtc_state->update_wm_post,
14212 * but added for clarity.
14213 */
14214 if (crtc_state->disable_cxsr)
14215 return true;
14216
14217 return false;
14218 }
14219
14220 static void intel_update_crtc(struct drm_crtc *crtc,
14221 struct drm_atomic_state *state,
14222 struct drm_crtc_state *old_crtc_state,
14223 unsigned int *crtc_vblank_mask)
14224 {
14225 struct drm_device *dev = crtc->dev;
14226 struct drm_i915_private *dev_priv = to_i915(dev);
14227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14228 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state);
14229 bool modeset = needs_modeset(crtc->state);
14230
14231 if (modeset) {
14232 update_scanline_offset(intel_crtc);
14233 dev_priv->display.crtc_enable(pipe_config, state);
14234 } else {
14235 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14236 }
14237
14238 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
14239 intel_fbc_enable(
14240 intel_crtc, pipe_config,
14241 to_intel_plane_state(crtc->primary->state));
14242 }
14243
14244 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
14245
14246 if (needs_vblank_wait(pipe_config))
14247 *crtc_vblank_mask |= drm_crtc_mask(crtc);
14248 }
14249
14250 static void intel_update_crtcs(struct drm_atomic_state *state,
14251 unsigned int *crtc_vblank_mask)
14252 {
14253 struct drm_crtc *crtc;
14254 struct drm_crtc_state *old_crtc_state;
14255 int i;
14256
14257 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14258 if (!crtc->state->active)
14259 continue;
14260
14261 intel_update_crtc(crtc, state, old_crtc_state,
14262 crtc_vblank_mask);
14263 }
14264 }
14265
14266 static void skl_update_crtcs(struct drm_atomic_state *state,
14267 unsigned int *crtc_vblank_mask)
14268 {
14269 struct drm_i915_private *dev_priv = to_i915(state->dev);
14270 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14271 struct drm_crtc *crtc;
14272 struct intel_crtc *intel_crtc;
14273 struct drm_crtc_state *old_crtc_state;
14274 struct intel_crtc_state *cstate;
14275 unsigned int updated = 0;
14276 bool progress;
14277 enum pipe pipe;
14278 int i;
14279
14280 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
14281
14282 for_each_crtc_in_state(state, crtc, old_crtc_state, i)
14283 /* ignore allocations for crtc's that have been turned off. */
14284 if (crtc->state->active)
14285 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
14286
14287 /*
14288 * Whenever the number of active pipes changes, we need to make sure we
14289 * update the pipes in the right order so that their ddb allocations
14290 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14291 * cause pipe underruns and other bad stuff.
14292 */
14293 do {
14294 progress = false;
14295
14296 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14297 bool vbl_wait = false;
14298 unsigned int cmask = drm_crtc_mask(crtc);
14299
14300 intel_crtc = to_intel_crtc(crtc);
14301 cstate = to_intel_crtc_state(crtc->state);
14302 pipe = intel_crtc->pipe;
14303
14304 if (updated & cmask || !cstate->base.active)
14305 continue;
14306
14307 if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
14308 continue;
14309
14310 updated |= cmask;
14311 entries[i] = &cstate->wm.skl.ddb;
14312
14313 /*
14314 * If this is an already active pipe, it's DDB changed,
14315 * and this isn't the last pipe that needs updating
14316 * then we need to wait for a vblank to pass for the
14317 * new ddb allocation to take effect.
14318 */
14319 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
14320 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
14321 !crtc->state->active_changed &&
14322 intel_state->wm_results.dirty_pipes != updated)
14323 vbl_wait = true;
14324
14325 intel_update_crtc(crtc, state, old_crtc_state,
14326 crtc_vblank_mask);
14327
14328 if (vbl_wait)
14329 intel_wait_for_vblank(dev_priv, pipe);
14330
14331 progress = true;
14332 }
14333 } while (progress);
14334 }
14335
14336 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
14337 {
14338 struct drm_device *dev = state->dev;
14339 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14340 struct drm_i915_private *dev_priv = to_i915(dev);
14341 struct drm_crtc_state *old_crtc_state;
14342 struct drm_crtc *crtc;
14343 struct intel_crtc_state *intel_cstate;
14344 bool hw_check = intel_state->modeset;
14345 unsigned long put_domains[I915_MAX_PIPES] = {};
14346 unsigned crtc_vblank_mask = 0;
14347 int i;
14348
14349 drm_atomic_helper_wait_for_dependencies(state);
14350
14351 if (intel_state->modeset)
14352 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14353
14354 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14355 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14356
14357 if (needs_modeset(crtc->state) ||
14358 to_intel_crtc_state(crtc->state)->update_pipe) {
14359 hw_check = true;
14360
14361 put_domains[to_intel_crtc(crtc)->pipe] =
14362 modeset_get_crtc_power_domains(crtc,
14363 to_intel_crtc_state(crtc->state));
14364 }
14365
14366 if (!needs_modeset(crtc->state))
14367 continue;
14368
14369 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14370
14371 if (old_crtc_state->active) {
14372 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
14373 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
14374 intel_crtc->active = false;
14375 intel_fbc_disable(intel_crtc);
14376 intel_disable_shared_dpll(intel_crtc);
14377
14378 /*
14379 * Underruns don't always raise
14380 * interrupts, so check manually.
14381 */
14382 intel_check_cpu_fifo_underruns(dev_priv);
14383 intel_check_pch_fifo_underruns(dev_priv);
14384
14385 if (!crtc->state->active) {
14386 /*
14387 * Make sure we don't call initial_watermarks
14388 * for ILK-style watermark updates.
14389 */
14390 if (dev_priv->display.atomic_update_watermarks)
14391 dev_priv->display.initial_watermarks(intel_state,
14392 to_intel_crtc_state(crtc->state));
14393 else
14394 intel_update_watermarks(intel_crtc);
14395 }
14396 }
14397 }
14398
14399 /* Only after disabling all output pipelines that will be changed can we
14400 * update the the output configuration. */
14401 intel_modeset_update_crtc_state(state);
14402
14403 if (intel_state->modeset) {
14404 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
14405
14406 if (dev_priv->display.modeset_commit_cdclk &&
14407 (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
14408 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
14409 dev_priv->display.modeset_commit_cdclk(state);
14410
14411 /*
14412 * SKL workaround: bspec recommends we disable the SAGV when we
14413 * have more then one pipe enabled
14414 */
14415 if (!intel_can_enable_sagv(state))
14416 intel_disable_sagv(dev_priv);
14417
14418 intel_modeset_verify_disabled(dev, state);
14419 }
14420
14421 /* Complete the events for pipes that have now been disabled */
14422 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14423 bool modeset = needs_modeset(crtc->state);
14424
14425 /* Complete events for now disable pipes here. */
14426 if (modeset && !crtc->state->active && crtc->state->event) {
14427 spin_lock_irq(&dev->event_lock);
14428 drm_crtc_send_vblank_event(crtc, crtc->state->event);
14429 spin_unlock_irq(&dev->event_lock);
14430
14431 crtc->state->event = NULL;
14432 }
14433 }
14434
14435 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14436 dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
14437
14438 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14439 * already, but still need the state for the delayed optimization. To
14440 * fix this:
14441 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14442 * - schedule that vblank worker _before_ calling hw_done
14443 * - at the start of commit_tail, cancel it _synchrously
14444 * - switch over to the vblank wait helper in the core after that since
14445 * we don't need out special handling any more.
14446 */
14447 if (!state->legacy_cursor_update)
14448 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
14449
14450 /*
14451 * Now that the vblank has passed, we can go ahead and program the
14452 * optimal watermarks on platforms that need two-step watermark
14453 * programming.
14454 *
14455 * TODO: Move this (and other cleanup) to an async worker eventually.
14456 */
14457 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14458 intel_cstate = to_intel_crtc_state(crtc->state);
14459
14460 if (dev_priv->display.optimize_watermarks)
14461 dev_priv->display.optimize_watermarks(intel_state,
14462 intel_cstate);
14463 }
14464
14465 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14466 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
14467
14468 if (put_domains[i])
14469 modeset_put_power_domains(dev_priv, put_domains[i]);
14470
14471 intel_modeset_verify_crtc(crtc, state, old_crtc_state, crtc->state);
14472 }
14473
14474 if (intel_state->modeset && intel_can_enable_sagv(state))
14475 intel_enable_sagv(dev_priv);
14476
14477 drm_atomic_helper_commit_hw_done(state);
14478
14479 if (intel_state->modeset)
14480 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
14481
14482 mutex_lock(&dev->struct_mutex);
14483 drm_atomic_helper_cleanup_planes(dev, state);
14484 mutex_unlock(&dev->struct_mutex);
14485
14486 drm_atomic_helper_commit_cleanup_done(state);
14487
14488 drm_atomic_state_put(state);
14489
14490 /* As one of the primary mmio accessors, KMS has a high likelihood
14491 * of triggering bugs in unclaimed access. After we finish
14492 * modesetting, see if an error has been flagged, and if so
14493 * enable debugging for the next modeset - and hope we catch
14494 * the culprit.
14495 *
14496 * XXX note that we assume display power is on at this point.
14497 * This might hold true now but we need to add pm helper to check
14498 * unclaimed only when the hardware is on, as atomic commits
14499 * can happen also when the device is completely off.
14500 */
14501 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
14502 }
14503
14504 static void intel_atomic_commit_work(struct work_struct *work)
14505 {
14506 struct drm_atomic_state *state =
14507 container_of(work, struct drm_atomic_state, commit_work);
14508
14509 intel_atomic_commit_tail(state);
14510 }
14511
14512 static int __i915_sw_fence_call
14513 intel_atomic_commit_ready(struct i915_sw_fence *fence,
14514 enum i915_sw_fence_notify notify)
14515 {
14516 struct intel_atomic_state *state =
14517 container_of(fence, struct intel_atomic_state, commit_ready);
14518
14519 switch (notify) {
14520 case FENCE_COMPLETE:
14521 if (state->base.commit_work.func)
14522 queue_work(system_unbound_wq, &state->base.commit_work);
14523 break;
14524
14525 case FENCE_FREE:
14526 drm_atomic_state_put(&state->base);
14527 break;
14528 }
14529
14530 return NOTIFY_DONE;
14531 }
14532
14533 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
14534 {
14535 struct drm_plane_state *old_plane_state;
14536 struct drm_plane *plane;
14537 int i;
14538
14539 for_each_plane_in_state(state, plane, old_plane_state, i)
14540 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
14541 intel_fb_obj(plane->state->fb),
14542 to_intel_plane(plane)->frontbuffer_bit);
14543 }
14544
14545 /**
14546 * intel_atomic_commit - commit validated state object
14547 * @dev: DRM device
14548 * @state: the top-level driver state object
14549 * @nonblock: nonblocking commit
14550 *
14551 * This function commits a top-level state object that has been validated
14552 * with drm_atomic_helper_check().
14553 *
14554 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
14555 * nonblocking commits are only safe for pure plane updates. Everything else
14556 * should work though.
14557 *
14558 * RETURNS
14559 * Zero for success or -errno.
14560 */
14561 static int intel_atomic_commit(struct drm_device *dev,
14562 struct drm_atomic_state *state,
14563 bool nonblock)
14564 {
14565 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14566 struct drm_i915_private *dev_priv = to_i915(dev);
14567 int ret = 0;
14568
14569 if (intel_state->modeset && nonblock) {
14570 DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n");
14571 return -EINVAL;
14572 }
14573
14574 ret = drm_atomic_helper_setup_commit(state, nonblock);
14575 if (ret)
14576 return ret;
14577
14578 drm_atomic_state_get(state);
14579 i915_sw_fence_init(&intel_state->commit_ready,
14580 intel_atomic_commit_ready);
14581
14582 ret = intel_atomic_prepare_commit(dev, state);
14583 if (ret) {
14584 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14585 i915_sw_fence_commit(&intel_state->commit_ready);
14586 return ret;
14587 }
14588
14589 drm_atomic_helper_swap_state(state, true);
14590 dev_priv->wm.distrust_bios_wm = false;
14591 intel_shared_dpll_commit(state);
14592 intel_atomic_track_fbs(state);
14593
14594 if (intel_state->modeset) {
14595 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
14596 sizeof(intel_state->min_pixclk));
14597 dev_priv->active_crtcs = intel_state->active_crtcs;
14598 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
14599 }
14600
14601 drm_atomic_state_get(state);
14602 INIT_WORK(&state->commit_work,
14603 nonblock ? intel_atomic_commit_work : NULL);
14604
14605 i915_sw_fence_commit(&intel_state->commit_ready);
14606 if (!nonblock) {
14607 i915_sw_fence_wait(&intel_state->commit_ready);
14608 intel_atomic_commit_tail(state);
14609 }
14610
14611 return 0;
14612 }
14613
14614 void intel_crtc_restore_mode(struct drm_crtc *crtc)
14615 {
14616 struct drm_device *dev = crtc->dev;
14617 struct drm_atomic_state *state;
14618 struct drm_crtc_state *crtc_state;
14619 int ret;
14620
14621 state = drm_atomic_state_alloc(dev);
14622 if (!state) {
14623 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
14624 crtc->base.id, crtc->name);
14625 return;
14626 }
14627
14628 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
14629
14630 retry:
14631 crtc_state = drm_atomic_get_crtc_state(state, crtc);
14632 ret = PTR_ERR_OR_ZERO(crtc_state);
14633 if (!ret) {
14634 if (!crtc_state->active)
14635 goto out;
14636
14637 crtc_state->mode_changed = true;
14638 ret = drm_atomic_commit(state);
14639 }
14640
14641 if (ret == -EDEADLK) {
14642 drm_atomic_state_clear(state);
14643 drm_modeset_backoff(state->acquire_ctx);
14644 goto retry;
14645 }
14646
14647 out:
14648 drm_atomic_state_put(state);
14649 }
14650
14651 /*
14652 * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
14653 * drm_atomic_helper_legacy_gamma_set() directly.
14654 */
14655 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
14656 u16 *red, u16 *green, u16 *blue,
14657 uint32_t size)
14658 {
14659 struct drm_device *dev = crtc->dev;
14660 struct drm_mode_config *config = &dev->mode_config;
14661 struct drm_crtc_state *state;
14662 int ret;
14663
14664 ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
14665 if (ret)
14666 return ret;
14667
14668 /*
14669 * Make sure we update the legacy properties so this works when
14670 * atomic is not enabled.
14671 */
14672
14673 state = crtc->state;
14674
14675 drm_object_property_set_value(&crtc->base,
14676 config->degamma_lut_property,
14677 (state->degamma_lut) ?
14678 state->degamma_lut->base.id : 0);
14679
14680 drm_object_property_set_value(&crtc->base,
14681 config->ctm_property,
14682 (state->ctm) ?
14683 state->ctm->base.id : 0);
14684
14685 drm_object_property_set_value(&crtc->base,
14686 config->gamma_lut_property,
14687 (state->gamma_lut) ?
14688 state->gamma_lut->base.id : 0);
14689
14690 return 0;
14691 }
14692
14693 static const struct drm_crtc_funcs intel_crtc_funcs = {
14694 .gamma_set = intel_atomic_legacy_gamma_set,
14695 .set_config = drm_atomic_helper_set_config,
14696 .set_property = drm_atomic_helper_crtc_set_property,
14697 .destroy = intel_crtc_destroy,
14698 .page_flip = intel_crtc_page_flip,
14699 .atomic_duplicate_state = intel_crtc_duplicate_state,
14700 .atomic_destroy_state = intel_crtc_destroy_state,
14701 };
14702
14703 /**
14704 * intel_prepare_plane_fb - Prepare fb for usage on plane
14705 * @plane: drm plane to prepare for
14706 * @fb: framebuffer to prepare for presentation
14707 *
14708 * Prepares a framebuffer for usage on a display plane. Generally this
14709 * involves pinning the underlying object and updating the frontbuffer tracking
14710 * bits. Some older platforms need special physical address handling for
14711 * cursor planes.
14712 *
14713 * Must be called with struct_mutex held.
14714 *
14715 * Returns 0 on success, negative error code on failure.
14716 */
14717 int
14718 intel_prepare_plane_fb(struct drm_plane *plane,
14719 struct drm_plane_state *new_state)
14720 {
14721 struct intel_atomic_state *intel_state =
14722 to_intel_atomic_state(new_state->state);
14723 struct drm_i915_private *dev_priv = to_i915(plane->dev);
14724 struct drm_framebuffer *fb = new_state->fb;
14725 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14726 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
14727 int ret;
14728
14729 if (!obj && !old_obj)
14730 return 0;
14731
14732 if (old_obj) {
14733 struct drm_crtc_state *crtc_state =
14734 drm_atomic_get_existing_crtc_state(new_state->state,
14735 plane->state->crtc);
14736
14737 /* Big Hammer, we also need to ensure that any pending
14738 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14739 * current scanout is retired before unpinning the old
14740 * framebuffer. Note that we rely on userspace rendering
14741 * into the buffer attached to the pipe they are waiting
14742 * on. If not, userspace generates a GPU hang with IPEHR
14743 * point to the MI_WAIT_FOR_EVENT.
14744 *
14745 * This should only fail upon a hung GPU, in which case we
14746 * can safely continue.
14747 */
14748 if (needs_modeset(crtc_state)) {
14749 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
14750 old_obj->resv, NULL,
14751 false, 0,
14752 GFP_KERNEL);
14753 if (ret < 0)
14754 return ret;
14755 }
14756 }
14757
14758 if (new_state->fence) { /* explicit fencing */
14759 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
14760 new_state->fence,
14761 I915_FENCE_TIMEOUT,
14762 GFP_KERNEL);
14763 if (ret < 0)
14764 return ret;
14765 }
14766
14767 if (!obj)
14768 return 0;
14769
14770 if (!new_state->fence) { /* implicit fencing */
14771 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
14772 obj->resv, NULL,
14773 false, I915_FENCE_TIMEOUT,
14774 GFP_KERNEL);
14775 if (ret < 0)
14776 return ret;
14777
14778 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
14779 }
14780
14781 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14782 INTEL_INFO(dev_priv)->cursor_needs_physical) {
14783 int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
14784 ret = i915_gem_object_attach_phys(obj, align);
14785 if (ret) {
14786 DRM_DEBUG_KMS("failed to attach phys object\n");
14787 return ret;
14788 }
14789 } else {
14790 struct i915_vma *vma;
14791
14792 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14793 if (IS_ERR(vma)) {
14794 DRM_DEBUG_KMS("failed to pin object\n");
14795 return PTR_ERR(vma);
14796 }
14797 }
14798
14799 return 0;
14800 }
14801
14802 /**
14803 * intel_cleanup_plane_fb - Cleans up an fb after plane use
14804 * @plane: drm plane to clean up for
14805 * @fb: old framebuffer that was on plane
14806 *
14807 * Cleans up a framebuffer that has just been removed from a plane.
14808 *
14809 * Must be called with struct_mutex held.
14810 */
14811 void
14812 intel_cleanup_plane_fb(struct drm_plane *plane,
14813 struct drm_plane_state *old_state)
14814 {
14815 struct drm_i915_private *dev_priv = to_i915(plane->dev);
14816 struct intel_plane_state *old_intel_state;
14817 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14818 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14819
14820 old_intel_state = to_intel_plane_state(old_state);
14821
14822 if (!obj && !old_obj)
14823 return;
14824
14825 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14826 !INTEL_INFO(dev_priv)->cursor_needs_physical))
14827 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14828 }
14829
14830 int
14831 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14832 {
14833 int max_scale;
14834 int crtc_clock, cdclk;
14835
14836 if (!intel_crtc || !crtc_state->base.enable)
14837 return DRM_PLANE_HELPER_NO_SCALING;
14838
14839 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14840 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14841
14842 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14843 return DRM_PLANE_HELPER_NO_SCALING;
14844
14845 /*
14846 * skl max scale is lower of:
14847 * close to 3 but not 3, -1 is for that purpose
14848 * or
14849 * cdclk/crtc_clock
14850 */
14851 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14852
14853 return max_scale;
14854 }
14855
14856 static int
14857 intel_check_primary_plane(struct drm_plane *plane,
14858 struct intel_crtc_state *crtc_state,
14859 struct intel_plane_state *state)
14860 {
14861 struct drm_i915_private *dev_priv = to_i915(plane->dev);
14862 struct drm_crtc *crtc = state->base.crtc;
14863 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14864 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14865 bool can_position = false;
14866 int ret;
14867
14868 if (INTEL_GEN(dev_priv) >= 9) {
14869 /* use scaler when colorkey is not required */
14870 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14871 min_scale = 1;
14872 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14873 }
14874 can_position = true;
14875 }
14876
14877 ret = drm_plane_helper_check_state(&state->base,
14878 &state->clip,
14879 min_scale, max_scale,
14880 can_position, true);
14881 if (ret)
14882 return ret;
14883
14884 if (!state->base.fb)
14885 return 0;
14886
14887 if (INTEL_GEN(dev_priv) >= 9) {
14888 ret = skl_check_plane_surface(state);
14889 if (ret)
14890 return ret;
14891 }
14892
14893 return 0;
14894 }
14895
14896 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14897 struct drm_crtc_state *old_crtc_state)
14898 {
14899 struct drm_device *dev = crtc->dev;
14900 struct drm_i915_private *dev_priv = to_i915(dev);
14901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14902 struct intel_crtc_state *intel_cstate =
14903 to_intel_crtc_state(crtc->state);
14904 struct intel_crtc_state *old_intel_cstate =
14905 to_intel_crtc_state(old_crtc_state);
14906 struct intel_atomic_state *old_intel_state =
14907 to_intel_atomic_state(old_crtc_state->state);
14908 bool modeset = needs_modeset(crtc->state);
14909
14910 /* Perform vblank evasion around commit operation */
14911 intel_pipe_update_start(intel_crtc);
14912
14913 if (modeset)
14914 goto out;
14915
14916 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14917 intel_color_set_csc(crtc->state);
14918 intel_color_load_luts(crtc->state);
14919 }
14920
14921 if (intel_cstate->update_pipe)
14922 intel_update_pipe_config(intel_crtc, old_intel_cstate);
14923 else if (INTEL_GEN(dev_priv) >= 9)
14924 skl_detach_scalers(intel_crtc);
14925
14926 out:
14927 if (dev_priv->display.atomic_update_watermarks)
14928 dev_priv->display.atomic_update_watermarks(old_intel_state,
14929 intel_cstate);
14930 }
14931
14932 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14933 struct drm_crtc_state *old_crtc_state)
14934 {
14935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14936
14937 intel_pipe_update_end(intel_crtc, NULL);
14938 }
14939
14940 /**
14941 * intel_plane_destroy - destroy a plane
14942 * @plane: plane to destroy
14943 *
14944 * Common destruction function for all types of planes (primary, cursor,
14945 * sprite).
14946 */
14947 void intel_plane_destroy(struct drm_plane *plane)
14948 {
14949 drm_plane_cleanup(plane);
14950 kfree(to_intel_plane(plane));
14951 }
14952
14953 const struct drm_plane_funcs intel_plane_funcs = {
14954 .update_plane = drm_atomic_helper_update_plane,
14955 .disable_plane = drm_atomic_helper_disable_plane,
14956 .destroy = intel_plane_destroy,
14957 .set_property = drm_atomic_helper_plane_set_property,
14958 .atomic_get_property = intel_plane_atomic_get_property,
14959 .atomic_set_property = intel_plane_atomic_set_property,
14960 .atomic_duplicate_state = intel_plane_duplicate_state,
14961 .atomic_destroy_state = intel_plane_destroy_state,
14962 };
14963
14964 static struct intel_plane *
14965 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
14966 {
14967 struct intel_plane *primary = NULL;
14968 struct intel_plane_state *state = NULL;
14969 const uint32_t *intel_primary_formats;
14970 unsigned int supported_rotations;
14971 unsigned int num_formats;
14972 int ret;
14973
14974 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14975 if (!primary) {
14976 ret = -ENOMEM;
14977 goto fail;
14978 }
14979
14980 state = intel_create_plane_state(&primary->base);
14981 if (!state) {
14982 ret = -ENOMEM;
14983 goto fail;
14984 }
14985
14986 primary->base.state = &state->base;
14987
14988 primary->can_scale = false;
14989 primary->max_downscale = 1;
14990 if (INTEL_GEN(dev_priv) >= 9) {
14991 primary->can_scale = true;
14992 state->scaler_id = -1;
14993 }
14994 primary->pipe = pipe;
14995 /*
14996 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
14997 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
14998 */
14999 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
15000 primary->plane = (enum plane) !pipe;
15001 else
15002 primary->plane = (enum plane) pipe;
15003 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
15004 primary->check_plane = intel_check_primary_plane;
15005
15006 if (INTEL_GEN(dev_priv) >= 9) {
15007 intel_primary_formats = skl_primary_formats;
15008 num_formats = ARRAY_SIZE(skl_primary_formats);
15009
15010 primary->update_plane = skylake_update_primary_plane;
15011 primary->disable_plane = skylake_disable_primary_plane;
15012 } else if (HAS_PCH_SPLIT(dev_priv)) {
15013 intel_primary_formats = i965_primary_formats;
15014 num_formats = ARRAY_SIZE(i965_primary_formats);
15015
15016 primary->update_plane = ironlake_update_primary_plane;
15017 primary->disable_plane = i9xx_disable_primary_plane;
15018 } else if (INTEL_GEN(dev_priv) >= 4) {
15019 intel_primary_formats = i965_primary_formats;
15020 num_formats = ARRAY_SIZE(i965_primary_formats);
15021
15022 primary->update_plane = i9xx_update_primary_plane;
15023 primary->disable_plane = i9xx_disable_primary_plane;
15024 } else {
15025 intel_primary_formats = i8xx_primary_formats;
15026 num_formats = ARRAY_SIZE(i8xx_primary_formats);
15027
15028 primary->update_plane = i9xx_update_primary_plane;
15029 primary->disable_plane = i9xx_disable_primary_plane;
15030 }
15031
15032 if (INTEL_GEN(dev_priv) >= 9)
15033 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
15034 0, &intel_plane_funcs,
15035 intel_primary_formats, num_formats,
15036 DRM_PLANE_TYPE_PRIMARY,
15037 "plane 1%c", pipe_name(pipe));
15038 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
15039 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
15040 0, &intel_plane_funcs,
15041 intel_primary_formats, num_formats,
15042 DRM_PLANE_TYPE_PRIMARY,
15043 "primary %c", pipe_name(pipe));
15044 else
15045 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
15046 0, &intel_plane_funcs,
15047 intel_primary_formats, num_formats,
15048 DRM_PLANE_TYPE_PRIMARY,
15049 "plane %c", plane_name(primary->plane));
15050 if (ret)
15051 goto fail;
15052
15053 if (INTEL_GEN(dev_priv) >= 9) {
15054 supported_rotations =
15055 DRM_ROTATE_0 | DRM_ROTATE_90 |
15056 DRM_ROTATE_180 | DRM_ROTATE_270;
15057 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
15058 supported_rotations =
15059 DRM_ROTATE_0 | DRM_ROTATE_180 |
15060 DRM_REFLECT_X;
15061 } else if (INTEL_GEN(dev_priv) >= 4) {
15062 supported_rotations =
15063 DRM_ROTATE_0 | DRM_ROTATE_180;
15064 } else {
15065 supported_rotations = DRM_ROTATE_0;
15066 }
15067
15068 if (INTEL_GEN(dev_priv) >= 4)
15069 drm_plane_create_rotation_property(&primary->base,
15070 DRM_ROTATE_0,
15071 supported_rotations);
15072
15073 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
15074
15075 return primary;
15076
15077 fail:
15078 kfree(state);
15079 kfree(primary);
15080
15081 return ERR_PTR(ret);
15082 }
15083
15084 static int
15085 intel_check_cursor_plane(struct drm_plane *plane,
15086 struct intel_crtc_state *crtc_state,
15087 struct intel_plane_state *state)
15088 {
15089 struct drm_framebuffer *fb = state->base.fb;
15090 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15091 enum pipe pipe = to_intel_plane(plane)->pipe;
15092 unsigned stride;
15093 int ret;
15094
15095 ret = drm_plane_helper_check_state(&state->base,
15096 &state->clip,
15097 DRM_PLANE_HELPER_NO_SCALING,
15098 DRM_PLANE_HELPER_NO_SCALING,
15099 true, true);
15100 if (ret)
15101 return ret;
15102
15103 /* if we want to turn off the cursor ignore width and height */
15104 if (!obj)
15105 return 0;
15106
15107 /* Check for which cursor types we support */
15108 if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w,
15109 state->base.crtc_h)) {
15110 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
15111 state->base.crtc_w, state->base.crtc_h);
15112 return -EINVAL;
15113 }
15114
15115 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
15116 if (obj->base.size < stride * state->base.crtc_h) {
15117 DRM_DEBUG_KMS("buffer is too small\n");
15118 return -ENOMEM;
15119 }
15120
15121 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
15122 DRM_DEBUG_KMS("cursor cannot be tiled\n");
15123 return -EINVAL;
15124 }
15125
15126 /*
15127 * There's something wrong with the cursor on CHV pipe C.
15128 * If it straddles the left edge of the screen then
15129 * moving it away from the edge or disabling it often
15130 * results in a pipe underrun, and often that can lead to
15131 * dead pipe (constant underrun reported, and it scans
15132 * out just a solid color). To recover from that, the
15133 * display power well must be turned off and on again.
15134 * Refuse the put the cursor into that compromised position.
15135 */
15136 if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C &&
15137 state->base.visible && state->base.crtc_x < 0) {
15138 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
15139 return -EINVAL;
15140 }
15141
15142 return 0;
15143 }
15144
15145 static void
15146 intel_disable_cursor_plane(struct drm_plane *plane,
15147 struct drm_crtc *crtc)
15148 {
15149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15150
15151 intel_crtc->cursor_addr = 0;
15152 intel_crtc_update_cursor(crtc, NULL);
15153 }
15154
15155 static void
15156 intel_update_cursor_plane(struct drm_plane *plane,
15157 const struct intel_crtc_state *crtc_state,
15158 const struct intel_plane_state *state)
15159 {
15160 struct drm_crtc *crtc = crtc_state->base.crtc;
15161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15162 struct drm_i915_private *dev_priv = to_i915(plane->dev);
15163 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
15164 uint32_t addr;
15165
15166 if (!obj)
15167 addr = 0;
15168 else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
15169 addr = i915_gem_object_ggtt_offset(obj, NULL);
15170 else
15171 addr = obj->phys_handle->busaddr;
15172
15173 intel_crtc->cursor_addr = addr;
15174 intel_crtc_update_cursor(crtc, state);
15175 }
15176
15177 static struct intel_plane *
15178 intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
15179 {
15180 struct intel_plane *cursor = NULL;
15181 struct intel_plane_state *state = NULL;
15182 int ret;
15183
15184 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
15185 if (!cursor) {
15186 ret = -ENOMEM;
15187 goto fail;
15188 }
15189
15190 state = intel_create_plane_state(&cursor->base);
15191 if (!state) {
15192 ret = -ENOMEM;
15193 goto fail;
15194 }
15195
15196 cursor->base.state = &state->base;
15197
15198 cursor->can_scale = false;
15199 cursor->max_downscale = 1;
15200 cursor->pipe = pipe;
15201 cursor->plane = pipe;
15202 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
15203 cursor->check_plane = intel_check_cursor_plane;
15204 cursor->update_plane = intel_update_cursor_plane;
15205 cursor->disable_plane = intel_disable_cursor_plane;
15206
15207 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
15208 0, &intel_plane_funcs,
15209 intel_cursor_formats,
15210 ARRAY_SIZE(intel_cursor_formats),
15211 DRM_PLANE_TYPE_CURSOR,
15212 "cursor %c", pipe_name(pipe));
15213 if (ret)
15214 goto fail;
15215
15216 if (INTEL_GEN(dev_priv) >= 4)
15217 drm_plane_create_rotation_property(&cursor->base,
15218 DRM_ROTATE_0,
15219 DRM_ROTATE_0 |
15220 DRM_ROTATE_180);
15221
15222 if (INTEL_GEN(dev_priv) >= 9)
15223 state->scaler_id = -1;
15224
15225 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
15226
15227 return cursor;
15228
15229 fail:
15230 kfree(state);
15231 kfree(cursor);
15232
15233 return ERR_PTR(ret);
15234 }
15235
15236 static void skl_init_scalers(struct drm_i915_private *dev_priv,
15237 struct intel_crtc *crtc,
15238 struct intel_crtc_state *crtc_state)
15239 {
15240 struct intel_crtc_scaler_state *scaler_state =
15241 &crtc_state->scaler_state;
15242 int i;
15243
15244 for (i = 0; i < crtc->num_scalers; i++) {
15245 struct intel_scaler *scaler = &scaler_state->scalers[i];
15246
15247 scaler->in_use = 0;
15248 scaler->mode = PS_SCALER_MODE_DYN;
15249 }
15250
15251 scaler_state->scaler_id = -1;
15252 }
15253
15254 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
15255 {
15256 struct intel_crtc *intel_crtc;
15257 struct intel_crtc_state *crtc_state = NULL;
15258 struct intel_plane *primary = NULL;
15259 struct intel_plane *cursor = NULL;
15260 int sprite, ret;
15261
15262 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
15263 if (!intel_crtc)
15264 return -ENOMEM;
15265
15266 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
15267 if (!crtc_state) {
15268 ret = -ENOMEM;
15269 goto fail;
15270 }
15271 intel_crtc->config = crtc_state;
15272 intel_crtc->base.state = &crtc_state->base;
15273 crtc_state->base.crtc = &intel_crtc->base;
15274
15275 /* initialize shared scalers */
15276 if (INTEL_GEN(dev_priv) >= 9) {
15277 if (pipe == PIPE_C)
15278 intel_crtc->num_scalers = 1;
15279 else
15280 intel_crtc->num_scalers = SKL_NUM_SCALERS;
15281
15282 skl_init_scalers(dev_priv, intel_crtc, crtc_state);
15283 }
15284
15285 primary = intel_primary_plane_create(dev_priv, pipe);
15286 if (IS_ERR(primary)) {
15287 ret = PTR_ERR(primary);
15288 goto fail;
15289 }
15290
15291 for_each_sprite(dev_priv, pipe, sprite) {
15292 struct intel_plane *plane;
15293
15294 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
15295 if (IS_ERR(plane)) {
15296 ret = PTR_ERR(plane);
15297 goto fail;
15298 }
15299 }
15300
15301 cursor = intel_cursor_plane_create(dev_priv, pipe);
15302 if (IS_ERR(cursor)) {
15303 ret = PTR_ERR(cursor);
15304 goto fail;
15305 }
15306
15307 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
15308 &primary->base, &cursor->base,
15309 &intel_crtc_funcs,
15310 "pipe %c", pipe_name(pipe));
15311 if (ret)
15312 goto fail;
15313
15314 intel_crtc->pipe = pipe;
15315 intel_crtc->plane = primary->plane;
15316
15317 intel_crtc->cursor_base = ~0;
15318 intel_crtc->cursor_cntl = ~0;
15319 intel_crtc->cursor_size = ~0;
15320
15321 intel_crtc->wm.cxsr_allowed = true;
15322
15323 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15324 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
15325 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
15326 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
15327
15328 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
15329
15330 intel_color_init(&intel_crtc->base);
15331
15332 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15333
15334 return 0;
15335
15336 fail:
15337 /*
15338 * drm_mode_config_cleanup() will free up any
15339 * crtcs/planes already initialized.
15340 */
15341 kfree(crtc_state);
15342 kfree(intel_crtc);
15343
15344 return ret;
15345 }
15346
15347 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
15348 {
15349 struct drm_encoder *encoder = connector->base.encoder;
15350 struct drm_device *dev = connector->base.dev;
15351
15352 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
15353
15354 if (!encoder || WARN_ON(!encoder->crtc))
15355 return INVALID_PIPE;
15356
15357 return to_intel_crtc(encoder->crtc)->pipe;
15358 }
15359
15360 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
15361 struct drm_file *file)
15362 {
15363 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15364 struct drm_crtc *drmmode_crtc;
15365 struct intel_crtc *crtc;
15366
15367 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
15368 if (!drmmode_crtc)
15369 return -ENOENT;
15370
15371 crtc = to_intel_crtc(drmmode_crtc);
15372 pipe_from_crtc_id->pipe = crtc->pipe;
15373
15374 return 0;
15375 }
15376
15377 static int intel_encoder_clones(struct intel_encoder *encoder)
15378 {
15379 struct drm_device *dev = encoder->base.dev;
15380 struct intel_encoder *source_encoder;
15381 int index_mask = 0;
15382 int entry = 0;
15383
15384 for_each_intel_encoder(dev, source_encoder) {
15385 if (encoders_cloneable(encoder, source_encoder))
15386 index_mask |= (1 << entry);
15387
15388 entry++;
15389 }
15390
15391 return index_mask;
15392 }
15393
15394 static bool has_edp_a(struct drm_i915_private *dev_priv)
15395 {
15396 if (!IS_MOBILE(dev_priv))
15397 return false;
15398
15399 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15400 return false;
15401
15402 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
15403 return false;
15404
15405 return true;
15406 }
15407
15408 static bool intel_crt_present(struct drm_i915_private *dev_priv)
15409 {
15410 if (INTEL_GEN(dev_priv) >= 9)
15411 return false;
15412
15413 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
15414 return false;
15415
15416 if (IS_CHERRYVIEW(dev_priv))
15417 return false;
15418
15419 if (HAS_PCH_LPT_H(dev_priv) &&
15420 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15421 return false;
15422
15423 /* DDI E can't be used if DDI A requires 4 lanes */
15424 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15425 return false;
15426
15427 if (!dev_priv->vbt.int_crt_support)
15428 return false;
15429
15430 return true;
15431 }
15432
15433 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15434 {
15435 int pps_num;
15436 int pps_idx;
15437
15438 if (HAS_DDI(dev_priv))
15439 return;
15440 /*
15441 * This w/a is needed at least on CPT/PPT, but to be sure apply it
15442 * everywhere where registers can be write protected.
15443 */
15444 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15445 pps_num = 2;
15446 else
15447 pps_num = 1;
15448
15449 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
15450 u32 val = I915_READ(PP_CONTROL(pps_idx));
15451
15452 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
15453 I915_WRITE(PP_CONTROL(pps_idx), val);
15454 }
15455 }
15456
15457 static void intel_pps_init(struct drm_i915_private *dev_priv)
15458 {
15459 if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv))
15460 dev_priv->pps_mmio_base = PCH_PPS_BASE;
15461 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15462 dev_priv->pps_mmio_base = VLV_PPS_BASE;
15463 else
15464 dev_priv->pps_mmio_base = PPS_BASE;
15465
15466 intel_pps_unlock_regs_wa(dev_priv);
15467 }
15468
15469 static void intel_setup_outputs(struct drm_device *dev)
15470 {
15471 struct drm_i915_private *dev_priv = to_i915(dev);
15472 struct intel_encoder *encoder;
15473 bool dpd_is_edp = false;
15474
15475 intel_pps_init(dev_priv);
15476
15477 /*
15478 * intel_edp_init_connector() depends on this completing first, to
15479 * prevent the registeration of both eDP and LVDS and the incorrect
15480 * sharing of the PPS.
15481 */
15482 intel_lvds_init(dev);
15483
15484 if (intel_crt_present(dev_priv))
15485 intel_crt_init(dev);
15486
15487 if (IS_BROXTON(dev_priv)) {
15488 /*
15489 * FIXME: Broxton doesn't support port detection via the
15490 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
15491 * detect the ports.
15492 */
15493 intel_ddi_init(dev, PORT_A);
15494 intel_ddi_init(dev, PORT_B);
15495 intel_ddi_init(dev, PORT_C);
15496
15497 intel_dsi_init(dev);
15498 } else if (HAS_DDI(dev_priv)) {
15499 int found;
15500
15501 /*
15502 * Haswell uses DDI functions to detect digital outputs.
15503 * On SKL pre-D0 the strap isn't connected, so we assume
15504 * it's there.
15505 */
15506 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
15507 /* WaIgnoreDDIAStrap: skl */
15508 if (found || IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15509 intel_ddi_init(dev, PORT_A);
15510
15511 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
15512 * register */
15513 found = I915_READ(SFUSE_STRAP);
15514
15515 if (found & SFUSE_STRAP_DDIB_DETECTED)
15516 intel_ddi_init(dev, PORT_B);
15517 if (found & SFUSE_STRAP_DDIC_DETECTED)
15518 intel_ddi_init(dev, PORT_C);
15519 if (found & SFUSE_STRAP_DDID_DETECTED)
15520 intel_ddi_init(dev, PORT_D);
15521 /*
15522 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
15523 */
15524 if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
15525 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
15526 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
15527 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
15528 intel_ddi_init(dev, PORT_E);
15529
15530 } else if (HAS_PCH_SPLIT(dev_priv)) {
15531 int found;
15532 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
15533
15534 if (has_edp_a(dev_priv))
15535 intel_dp_init(dev, DP_A, PORT_A);
15536
15537 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
15538 /* PCH SDVOB multiplex with HDMIB */
15539 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
15540 if (!found)
15541 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
15542 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
15543 intel_dp_init(dev, PCH_DP_B, PORT_B);
15544 }
15545
15546 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
15547 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
15548
15549 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
15550 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
15551
15552 if (I915_READ(PCH_DP_C) & DP_DETECTED)
15553 intel_dp_init(dev, PCH_DP_C, PORT_C);
15554
15555 if (I915_READ(PCH_DP_D) & DP_DETECTED)
15556 intel_dp_init(dev, PCH_DP_D, PORT_D);
15557 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15558 bool has_edp, has_port;
15559
15560 /*
15561 * The DP_DETECTED bit is the latched state of the DDC
15562 * SDA pin at boot. However since eDP doesn't require DDC
15563 * (no way to plug in a DP->HDMI dongle) the DDC pins for
15564 * eDP ports may have been muxed to an alternate function.
15565 * Thus we can't rely on the DP_DETECTED bit alone to detect
15566 * eDP ports. Consult the VBT as well as DP_DETECTED to
15567 * detect eDP ports.
15568 *
15569 * Sadly the straps seem to be missing sometimes even for HDMI
15570 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
15571 * and VBT for the presence of the port. Additionally we can't
15572 * trust the port type the VBT declares as we've seen at least
15573 * HDMI ports that the VBT claim are DP or eDP.
15574 */
15575 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
15576 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
15577 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
15578 has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
15579 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
15580 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
15581
15582 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
15583 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
15584 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
15585 has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
15586 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
15587 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
15588
15589 if (IS_CHERRYVIEW(dev_priv)) {
15590 /*
15591 * eDP not supported on port D,
15592 * so no need to worry about it
15593 */
15594 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
15595 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
15596 intel_dp_init(dev, CHV_DP_D, PORT_D);
15597 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
15598 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
15599 }
15600
15601 intel_dsi_init(dev);
15602 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
15603 bool found = false;
15604
15605 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15606 DRM_DEBUG_KMS("probing SDVOB\n");
15607 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
15608 if (!found && IS_G4X(dev_priv)) {
15609 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
15610 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
15611 }
15612
15613 if (!found && IS_G4X(dev_priv))
15614 intel_dp_init(dev, DP_B, PORT_B);
15615 }
15616
15617 /* Before G4X SDVOC doesn't have its own detect register */
15618
15619 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15620 DRM_DEBUG_KMS("probing SDVOC\n");
15621 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
15622 }
15623
15624 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
15625
15626 if (IS_G4X(dev_priv)) {
15627 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
15628 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
15629 }
15630 if (IS_G4X(dev_priv))
15631 intel_dp_init(dev, DP_C, PORT_C);
15632 }
15633
15634 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
15635 intel_dp_init(dev, DP_D, PORT_D);
15636 } else if (IS_GEN2(dev_priv))
15637 intel_dvo_init(dev);
15638
15639 if (SUPPORTS_TV(dev_priv))
15640 intel_tv_init(dev);
15641
15642 intel_psr_init(dev);
15643
15644 for_each_intel_encoder(dev, encoder) {
15645 encoder->base.possible_crtcs = encoder->crtc_mask;
15646 encoder->base.possible_clones =
15647 intel_encoder_clones(encoder);
15648 }
15649
15650 intel_init_pch_refclk(dev);
15651
15652 drm_helper_move_panel_connectors_to_head(dev);
15653 }
15654
15655 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
15656 {
15657 struct drm_device *dev = fb->dev;
15658 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15659
15660 drm_framebuffer_cleanup(fb);
15661 mutex_lock(&dev->struct_mutex);
15662 WARN_ON(!intel_fb->obj->framebuffer_references--);
15663 i915_gem_object_put(intel_fb->obj);
15664 mutex_unlock(&dev->struct_mutex);
15665 kfree(intel_fb);
15666 }
15667
15668 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
15669 struct drm_file *file,
15670 unsigned int *handle)
15671 {
15672 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15673 struct drm_i915_gem_object *obj = intel_fb->obj;
15674
15675 if (obj->userptr.mm) {
15676 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15677 return -EINVAL;
15678 }
15679
15680 return drm_gem_handle_create(file, &obj->base, handle);
15681 }
15682
15683 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
15684 struct drm_file *file,
15685 unsigned flags, unsigned color,
15686 struct drm_clip_rect *clips,
15687 unsigned num_clips)
15688 {
15689 struct drm_device *dev = fb->dev;
15690 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15691 struct drm_i915_gem_object *obj = intel_fb->obj;
15692
15693 mutex_lock(&dev->struct_mutex);
15694 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
15695 mutex_unlock(&dev->struct_mutex);
15696
15697 return 0;
15698 }
15699
15700 static const struct drm_framebuffer_funcs intel_fb_funcs = {
15701 .destroy = intel_user_framebuffer_destroy,
15702 .create_handle = intel_user_framebuffer_create_handle,
15703 .dirty = intel_user_framebuffer_dirty,
15704 };
15705
15706 static
15707 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
15708 uint64_t fb_modifier, uint32_t pixel_format)
15709 {
15710 u32 gen = INTEL_INFO(dev_priv)->gen;
15711
15712 if (gen >= 9) {
15713 int cpp = drm_format_plane_cpp(pixel_format, 0);
15714
15715 /* "The stride in bytes must not exceed the of the size of 8K
15716 * pixels and 32K bytes."
15717 */
15718 return min(8192 * cpp, 32768);
15719 } else if (gen >= 5 && !IS_VALLEYVIEW(dev_priv) &&
15720 !IS_CHERRYVIEW(dev_priv)) {
15721 return 32*1024;
15722 } else if (gen >= 4) {
15723 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15724 return 16*1024;
15725 else
15726 return 32*1024;
15727 } else if (gen >= 3) {
15728 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15729 return 8*1024;
15730 else
15731 return 16*1024;
15732 } else {
15733 /* XXX DSPC is limited to 4k tiled */
15734 return 8*1024;
15735 }
15736 }
15737
15738 static int intel_framebuffer_init(struct drm_device *dev,
15739 struct intel_framebuffer *intel_fb,
15740 struct drm_mode_fb_cmd2 *mode_cmd,
15741 struct drm_i915_gem_object *obj)
15742 {
15743 struct drm_i915_private *dev_priv = to_i915(dev);
15744 unsigned int tiling = i915_gem_object_get_tiling(obj);
15745 int ret;
15746 u32 pitch_limit, stride_alignment;
15747 struct drm_format_name_buf format_name;
15748
15749 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
15750
15751 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
15752 /*
15753 * If there's a fence, enforce that
15754 * the fb modifier and tiling mode match.
15755 */
15756 if (tiling != I915_TILING_NONE &&
15757 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15758 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
15759 return -EINVAL;
15760 }
15761 } else {
15762 if (tiling == I915_TILING_X) {
15763 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15764 } else if (tiling == I915_TILING_Y) {
15765 DRM_DEBUG("No Y tiling for legacy addfb\n");
15766 return -EINVAL;
15767 }
15768 }
15769
15770 /* Passed in modifier sanity checking. */
15771 switch (mode_cmd->modifier[0]) {
15772 case I915_FORMAT_MOD_Y_TILED:
15773 case I915_FORMAT_MOD_Yf_TILED:
15774 if (INTEL_GEN(dev_priv) < 9) {
15775 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15776 mode_cmd->modifier[0]);
15777 return -EINVAL;
15778 }
15779 case DRM_FORMAT_MOD_NONE:
15780 case I915_FORMAT_MOD_X_TILED:
15781 break;
15782 default:
15783 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15784 mode_cmd->modifier[0]);
15785 return -EINVAL;
15786 }
15787
15788 /*
15789 * gen2/3 display engine uses the fence if present,
15790 * so the tiling mode must match the fb modifier exactly.
15791 */
15792 if (INTEL_INFO(dev_priv)->gen < 4 &&
15793 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15794 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
15795 return -EINVAL;
15796 }
15797
15798 stride_alignment = intel_fb_stride_alignment(dev_priv,
15799 mode_cmd->modifier[0],
15800 mode_cmd->pixel_format);
15801 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
15802 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15803 mode_cmd->pitches[0], stride_alignment);
15804 return -EINVAL;
15805 }
15806
15807 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
15808 mode_cmd->pixel_format);
15809 if (mode_cmd->pitches[0] > pitch_limit) {
15810 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15811 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
15812 "tiled" : "linear",
15813 mode_cmd->pitches[0], pitch_limit);
15814 return -EINVAL;
15815 }
15816
15817 /*
15818 * If there's a fence, enforce that
15819 * the fb pitch and fence stride match.
15820 */
15821 if (tiling != I915_TILING_NONE &&
15822 mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) {
15823 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
15824 mode_cmd->pitches[0],
15825 i915_gem_object_get_stride(obj));
15826 return -EINVAL;
15827 }
15828
15829 /* Reject formats not supported by any plane early. */
15830 switch (mode_cmd->pixel_format) {
15831 case DRM_FORMAT_C8:
15832 case DRM_FORMAT_RGB565:
15833 case DRM_FORMAT_XRGB8888:
15834 case DRM_FORMAT_ARGB8888:
15835 break;
15836 case DRM_FORMAT_XRGB1555:
15837 if (INTEL_GEN(dev_priv) > 3) {
15838 DRM_DEBUG("unsupported pixel format: %s\n",
15839 drm_get_format_name(mode_cmd->pixel_format, &format_name));
15840 return -EINVAL;
15841 }
15842 break;
15843 case DRM_FORMAT_ABGR8888:
15844 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
15845 INTEL_GEN(dev_priv) < 9) {
15846 DRM_DEBUG("unsupported pixel format: %s\n",
15847 drm_get_format_name(mode_cmd->pixel_format, &format_name));
15848 return -EINVAL;
15849 }
15850 break;
15851 case DRM_FORMAT_XBGR8888:
15852 case DRM_FORMAT_XRGB2101010:
15853 case DRM_FORMAT_XBGR2101010:
15854 if (INTEL_GEN(dev_priv) < 4) {
15855 DRM_DEBUG("unsupported pixel format: %s\n",
15856 drm_get_format_name(mode_cmd->pixel_format, &format_name));
15857 return -EINVAL;
15858 }
15859 break;
15860 case DRM_FORMAT_ABGR2101010:
15861 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
15862 DRM_DEBUG("unsupported pixel format: %s\n",
15863 drm_get_format_name(mode_cmd->pixel_format, &format_name));
15864 return -EINVAL;
15865 }
15866 break;
15867 case DRM_FORMAT_YUYV:
15868 case DRM_FORMAT_UYVY:
15869 case DRM_FORMAT_YVYU:
15870 case DRM_FORMAT_VYUY:
15871 if (INTEL_GEN(dev_priv) < 5) {
15872 DRM_DEBUG("unsupported pixel format: %s\n",
15873 drm_get_format_name(mode_cmd->pixel_format, &format_name));
15874 return -EINVAL;
15875 }
15876 break;
15877 default:
15878 DRM_DEBUG("unsupported pixel format: %s\n",
15879 drm_get_format_name(mode_cmd->pixel_format, &format_name));
15880 return -EINVAL;
15881 }
15882
15883 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15884 if (mode_cmd->offsets[0] != 0)
15885 return -EINVAL;
15886
15887 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15888 intel_fb->obj = obj;
15889
15890 ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
15891 if (ret)
15892 return ret;
15893
15894 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15895 if (ret) {
15896 DRM_ERROR("framebuffer init failed %d\n", ret);
15897 return ret;
15898 }
15899
15900 intel_fb->obj->framebuffer_references++;
15901
15902 return 0;
15903 }
15904
15905 static struct drm_framebuffer *
15906 intel_user_framebuffer_create(struct drm_device *dev,
15907 struct drm_file *filp,
15908 const struct drm_mode_fb_cmd2 *user_mode_cmd)
15909 {
15910 struct drm_framebuffer *fb;
15911 struct drm_i915_gem_object *obj;
15912 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15913
15914 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
15915 if (!obj)
15916 return ERR_PTR(-ENOENT);
15917
15918 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15919 if (IS_ERR(fb))
15920 i915_gem_object_put(obj);
15921
15922 return fb;
15923 }
15924
15925 static const struct drm_mode_config_funcs intel_mode_funcs = {
15926 .fb_create = intel_user_framebuffer_create,
15927 .output_poll_changed = intel_fbdev_output_poll_changed,
15928 .atomic_check = intel_atomic_check,
15929 .atomic_commit = intel_atomic_commit,
15930 .atomic_state_alloc = intel_atomic_state_alloc,
15931 .atomic_state_clear = intel_atomic_state_clear,
15932 };
15933
15934 /**
15935 * intel_init_display_hooks - initialize the display modesetting hooks
15936 * @dev_priv: device private
15937 */
15938 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15939 {
15940 if (INTEL_INFO(dev_priv)->gen >= 9) {
15941 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15942 dev_priv->display.get_initial_plane_config =
15943 skylake_get_initial_plane_config;
15944 dev_priv->display.crtc_compute_clock =
15945 haswell_crtc_compute_clock;
15946 dev_priv->display.crtc_enable = haswell_crtc_enable;
15947 dev_priv->display.crtc_disable = haswell_crtc_disable;
15948 } else if (HAS_DDI(dev_priv)) {
15949 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15950 dev_priv->display.get_initial_plane_config =
15951 ironlake_get_initial_plane_config;
15952 dev_priv->display.crtc_compute_clock =
15953 haswell_crtc_compute_clock;
15954 dev_priv->display.crtc_enable = haswell_crtc_enable;
15955 dev_priv->display.crtc_disable = haswell_crtc_disable;
15956 } else if (HAS_PCH_SPLIT(dev_priv)) {
15957 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15958 dev_priv->display.get_initial_plane_config =
15959 ironlake_get_initial_plane_config;
15960 dev_priv->display.crtc_compute_clock =
15961 ironlake_crtc_compute_clock;
15962 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15963 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15964 } else if (IS_CHERRYVIEW(dev_priv)) {
15965 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15966 dev_priv->display.get_initial_plane_config =
15967 i9xx_get_initial_plane_config;
15968 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15969 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15970 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15971 } else if (IS_VALLEYVIEW(dev_priv)) {
15972 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15973 dev_priv->display.get_initial_plane_config =
15974 i9xx_get_initial_plane_config;
15975 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15976 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15977 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15978 } else if (IS_G4X(dev_priv)) {
15979 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15980 dev_priv->display.get_initial_plane_config =
15981 i9xx_get_initial_plane_config;
15982 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15983 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15984 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15985 } else if (IS_PINEVIEW(dev_priv)) {
15986 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15987 dev_priv->display.get_initial_plane_config =
15988 i9xx_get_initial_plane_config;
15989 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15990 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15991 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15992 } else if (!IS_GEN2(dev_priv)) {
15993 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15994 dev_priv->display.get_initial_plane_config =
15995 i9xx_get_initial_plane_config;
15996 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15997 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15998 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15999 } else {
16000 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16001 dev_priv->display.get_initial_plane_config =
16002 i9xx_get_initial_plane_config;
16003 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
16004 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16005 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16006 }
16007
16008 /* Returns the core display clock speed */
16009 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
16010 dev_priv->display.get_display_clock_speed =
16011 skylake_get_display_clock_speed;
16012 else if (IS_BROXTON(dev_priv))
16013 dev_priv->display.get_display_clock_speed =
16014 broxton_get_display_clock_speed;
16015 else if (IS_BROADWELL(dev_priv))
16016 dev_priv->display.get_display_clock_speed =
16017 broadwell_get_display_clock_speed;
16018 else if (IS_HASWELL(dev_priv))
16019 dev_priv->display.get_display_clock_speed =
16020 haswell_get_display_clock_speed;
16021 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16022 dev_priv->display.get_display_clock_speed =
16023 valleyview_get_display_clock_speed;
16024 else if (IS_GEN5(dev_priv))
16025 dev_priv->display.get_display_clock_speed =
16026 ilk_get_display_clock_speed;
16027 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
16028 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
16029 dev_priv->display.get_display_clock_speed =
16030 i945_get_display_clock_speed;
16031 else if (IS_GM45(dev_priv))
16032 dev_priv->display.get_display_clock_speed =
16033 gm45_get_display_clock_speed;
16034 else if (IS_CRESTLINE(dev_priv))
16035 dev_priv->display.get_display_clock_speed =
16036 i965gm_get_display_clock_speed;
16037 else if (IS_PINEVIEW(dev_priv))
16038 dev_priv->display.get_display_clock_speed =
16039 pnv_get_display_clock_speed;
16040 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
16041 dev_priv->display.get_display_clock_speed =
16042 g33_get_display_clock_speed;
16043 else if (IS_I915G(dev_priv))
16044 dev_priv->display.get_display_clock_speed =
16045 i915_get_display_clock_speed;
16046 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
16047 dev_priv->display.get_display_clock_speed =
16048 i9xx_misc_get_display_clock_speed;
16049 else if (IS_I915GM(dev_priv))
16050 dev_priv->display.get_display_clock_speed =
16051 i915gm_get_display_clock_speed;
16052 else if (IS_I865G(dev_priv))
16053 dev_priv->display.get_display_clock_speed =
16054 i865_get_display_clock_speed;
16055 else if (IS_I85X(dev_priv))
16056 dev_priv->display.get_display_clock_speed =
16057 i85x_get_display_clock_speed;
16058 else { /* 830 */
16059 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
16060 dev_priv->display.get_display_clock_speed =
16061 i830_get_display_clock_speed;
16062 }
16063
16064 if (IS_GEN5(dev_priv)) {
16065 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
16066 } else if (IS_GEN6(dev_priv)) {
16067 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
16068 } else if (IS_IVYBRIDGE(dev_priv)) {
16069 /* FIXME: detect B0+ stepping and use auto training */
16070 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
16071 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
16072 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
16073 }
16074
16075 if (IS_BROADWELL(dev_priv)) {
16076 dev_priv->display.modeset_commit_cdclk =
16077 broadwell_modeset_commit_cdclk;
16078 dev_priv->display.modeset_calc_cdclk =
16079 broadwell_modeset_calc_cdclk;
16080 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16081 dev_priv->display.modeset_commit_cdclk =
16082 valleyview_modeset_commit_cdclk;
16083 dev_priv->display.modeset_calc_cdclk =
16084 valleyview_modeset_calc_cdclk;
16085 } else if (IS_BROXTON(dev_priv)) {
16086 dev_priv->display.modeset_commit_cdclk =
16087 bxt_modeset_commit_cdclk;
16088 dev_priv->display.modeset_calc_cdclk =
16089 bxt_modeset_calc_cdclk;
16090 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
16091 dev_priv->display.modeset_commit_cdclk =
16092 skl_modeset_commit_cdclk;
16093 dev_priv->display.modeset_calc_cdclk =
16094 skl_modeset_calc_cdclk;
16095 }
16096
16097 if (dev_priv->info.gen >= 9)
16098 dev_priv->display.update_crtcs = skl_update_crtcs;
16099 else
16100 dev_priv->display.update_crtcs = intel_update_crtcs;
16101
16102 switch (INTEL_INFO(dev_priv)->gen) {
16103 case 2:
16104 dev_priv->display.queue_flip = intel_gen2_queue_flip;
16105 break;
16106
16107 case 3:
16108 dev_priv->display.queue_flip = intel_gen3_queue_flip;
16109 break;
16110
16111 case 4:
16112 case 5:
16113 dev_priv->display.queue_flip = intel_gen4_queue_flip;
16114 break;
16115
16116 case 6:
16117 dev_priv->display.queue_flip = intel_gen6_queue_flip;
16118 break;
16119 case 7:
16120 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
16121 dev_priv->display.queue_flip = intel_gen7_queue_flip;
16122 break;
16123 case 9:
16124 /* Drop through - unsupported since execlist only. */
16125 default:
16126 /* Default just returns -ENODEV to indicate unsupported */
16127 dev_priv->display.queue_flip = intel_default_queue_flip;
16128 }
16129 }
16130
16131 /*
16132 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
16133 * resume, or other times. This quirk makes sure that's the case for
16134 * affected systems.
16135 */
16136 static void quirk_pipea_force(struct drm_device *dev)
16137 {
16138 struct drm_i915_private *dev_priv = to_i915(dev);
16139
16140 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
16141 DRM_INFO("applying pipe a force quirk\n");
16142 }
16143
16144 static void quirk_pipeb_force(struct drm_device *dev)
16145 {
16146 struct drm_i915_private *dev_priv = to_i915(dev);
16147
16148 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
16149 DRM_INFO("applying pipe b force quirk\n");
16150 }
16151
16152 /*
16153 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
16154 */
16155 static void quirk_ssc_force_disable(struct drm_device *dev)
16156 {
16157 struct drm_i915_private *dev_priv = to_i915(dev);
16158 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
16159 DRM_INFO("applying lvds SSC disable quirk\n");
16160 }
16161
16162 /*
16163 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
16164 * brightness value
16165 */
16166 static void quirk_invert_brightness(struct drm_device *dev)
16167 {
16168 struct drm_i915_private *dev_priv = to_i915(dev);
16169 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
16170 DRM_INFO("applying inverted panel brightness quirk\n");
16171 }
16172
16173 /* Some VBT's incorrectly indicate no backlight is present */
16174 static void quirk_backlight_present(struct drm_device *dev)
16175 {
16176 struct drm_i915_private *dev_priv = to_i915(dev);
16177 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
16178 DRM_INFO("applying backlight present quirk\n");
16179 }
16180
16181 struct intel_quirk {
16182 int device;
16183 int subsystem_vendor;
16184 int subsystem_device;
16185 void (*hook)(struct drm_device *dev);
16186 };
16187
16188 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
16189 struct intel_dmi_quirk {
16190 void (*hook)(struct drm_device *dev);
16191 const struct dmi_system_id (*dmi_id_list)[];
16192 };
16193
16194 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
16195 {
16196 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
16197 return 1;
16198 }
16199
16200 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
16201 {
16202 .dmi_id_list = &(const struct dmi_system_id[]) {
16203 {
16204 .callback = intel_dmi_reverse_brightness,
16205 .ident = "NCR Corporation",
16206 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
16207 DMI_MATCH(DMI_PRODUCT_NAME, ""),
16208 },
16209 },
16210 { } /* terminating entry */
16211 },
16212 .hook = quirk_invert_brightness,
16213 },
16214 };
16215
16216 static struct intel_quirk intel_quirks[] = {
16217 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
16218 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
16219
16220 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
16221 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
16222
16223 /* 830 needs to leave pipe A & dpll A up */
16224 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
16225
16226 /* 830 needs to leave pipe B & dpll B up */
16227 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
16228
16229 /* Lenovo U160 cannot use SSC on LVDS */
16230 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
16231
16232 /* Sony Vaio Y cannot use SSC on LVDS */
16233 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
16234
16235 /* Acer Aspire 5734Z must invert backlight brightness */
16236 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
16237
16238 /* Acer/eMachines G725 */
16239 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
16240
16241 /* Acer/eMachines e725 */
16242 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
16243
16244 /* Acer/Packard Bell NCL20 */
16245 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
16246
16247 /* Acer Aspire 4736Z */
16248 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
16249
16250 /* Acer Aspire 5336 */
16251 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
16252
16253 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
16254 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
16255
16256 /* Acer C720 Chromebook (Core i3 4005U) */
16257 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
16258
16259 /* Apple Macbook 2,1 (Core 2 T7400) */
16260 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
16261
16262 /* Apple Macbook 4,1 */
16263 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
16264
16265 /* Toshiba CB35 Chromebook (Celeron 2955U) */
16266 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
16267
16268 /* HP Chromebook 14 (Celeron 2955U) */
16269 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
16270
16271 /* Dell Chromebook 11 */
16272 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
16273
16274 /* Dell Chromebook 11 (2015 version) */
16275 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
16276 };
16277
16278 static void intel_init_quirks(struct drm_device *dev)
16279 {
16280 struct pci_dev *d = dev->pdev;
16281 int i;
16282
16283 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
16284 struct intel_quirk *q = &intel_quirks[i];
16285
16286 if (d->device == q->device &&
16287 (d->subsystem_vendor == q->subsystem_vendor ||
16288 q->subsystem_vendor == PCI_ANY_ID) &&
16289 (d->subsystem_device == q->subsystem_device ||
16290 q->subsystem_device == PCI_ANY_ID))
16291 q->hook(dev);
16292 }
16293 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
16294 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
16295 intel_dmi_quirks[i].hook(dev);
16296 }
16297 }
16298
16299 /* Disable the VGA plane that we never use */
16300 static void i915_disable_vga(struct drm_i915_private *dev_priv)
16301 {
16302 struct pci_dev *pdev = dev_priv->drm.pdev;
16303 u8 sr1;
16304 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
16305
16306 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
16307 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
16308 outb(SR01, VGA_SR_INDEX);
16309 sr1 = inb(VGA_SR_DATA);
16310 outb(sr1 | 1<<5, VGA_SR_DATA);
16311 vga_put(pdev, VGA_RSRC_LEGACY_IO);
16312 udelay(300);
16313
16314 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
16315 POSTING_READ(vga_reg);
16316 }
16317
16318 void intel_modeset_init_hw(struct drm_device *dev)
16319 {
16320 struct drm_i915_private *dev_priv = to_i915(dev);
16321
16322 intel_update_cdclk(dev_priv);
16323
16324 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16325
16326 intel_init_clock_gating(dev_priv);
16327 }
16328
16329 /*
16330 * Calculate what we think the watermarks should be for the state we've read
16331 * out of the hardware and then immediately program those watermarks so that
16332 * we ensure the hardware settings match our internal state.
16333 *
16334 * We can calculate what we think WM's should be by creating a duplicate of the
16335 * current state (which was constructed during hardware readout) and running it
16336 * through the atomic check code to calculate new watermark values in the
16337 * state object.
16338 */
16339 static void sanitize_watermarks(struct drm_device *dev)
16340 {
16341 struct drm_i915_private *dev_priv = to_i915(dev);
16342 struct drm_atomic_state *state;
16343 struct intel_atomic_state *intel_state;
16344 struct drm_crtc *crtc;
16345 struct drm_crtc_state *cstate;
16346 struct drm_modeset_acquire_ctx ctx;
16347 int ret;
16348 int i;
16349
16350 /* Only supported on platforms that use atomic watermark design */
16351 if (!dev_priv->display.optimize_watermarks)
16352 return;
16353
16354 /*
16355 * We need to hold connection_mutex before calling duplicate_state so
16356 * that the connector loop is protected.
16357 */
16358 drm_modeset_acquire_init(&ctx, 0);
16359 retry:
16360 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16361 if (ret == -EDEADLK) {
16362 drm_modeset_backoff(&ctx);
16363 goto retry;
16364 } else if (WARN_ON(ret)) {
16365 goto fail;
16366 }
16367
16368 state = drm_atomic_helper_duplicate_state(dev, &ctx);
16369 if (WARN_ON(IS_ERR(state)))
16370 goto fail;
16371
16372 intel_state = to_intel_atomic_state(state);
16373
16374 /*
16375 * Hardware readout is the only time we don't want to calculate
16376 * intermediate watermarks (since we don't trust the current
16377 * watermarks).
16378 */
16379 intel_state->skip_intermediate_wm = true;
16380
16381 ret = intel_atomic_check(dev, state);
16382 if (ret) {
16383 /*
16384 * If we fail here, it means that the hardware appears to be
16385 * programmed in a way that shouldn't be possible, given our
16386 * understanding of watermark requirements. This might mean a
16387 * mistake in the hardware readout code or a mistake in the
16388 * watermark calculations for a given platform. Raise a WARN
16389 * so that this is noticeable.
16390 *
16391 * If this actually happens, we'll have to just leave the
16392 * BIOS-programmed watermarks untouched and hope for the best.
16393 */
16394 WARN(true, "Could not determine valid watermarks for inherited state\n");
16395 goto put_state;
16396 }
16397
16398 /* Write calculated watermark values back */
16399 for_each_crtc_in_state(state, crtc, cstate, i) {
16400 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
16401
16402 cs->wm.need_postvbl_update = true;
16403 dev_priv->display.optimize_watermarks(intel_state, cs);
16404 }
16405
16406 put_state:
16407 drm_atomic_state_put(state);
16408 fail:
16409 drm_modeset_drop_locks(&ctx);
16410 drm_modeset_acquire_fini(&ctx);
16411 }
16412
16413 int intel_modeset_init(struct drm_device *dev)
16414 {
16415 struct drm_i915_private *dev_priv = to_i915(dev);
16416 struct i915_ggtt *ggtt = &dev_priv->ggtt;
16417 enum pipe pipe;
16418 struct intel_crtc *crtc;
16419
16420 drm_mode_config_init(dev);
16421
16422 dev->mode_config.min_width = 0;
16423 dev->mode_config.min_height = 0;
16424
16425 dev->mode_config.preferred_depth = 24;
16426 dev->mode_config.prefer_shadow = 1;
16427
16428 dev->mode_config.allow_fb_modifiers = true;
16429
16430 dev->mode_config.funcs = &intel_mode_funcs;
16431
16432 intel_init_quirks(dev);
16433
16434 intel_init_pm(dev_priv);
16435
16436 if (INTEL_INFO(dev_priv)->num_pipes == 0)
16437 return 0;
16438
16439 /*
16440 * There may be no VBT; and if the BIOS enabled SSC we can
16441 * just keep using it to avoid unnecessary flicker. Whereas if the
16442 * BIOS isn't using it, don't assume it will work even if the VBT
16443 * indicates as much.
16444 */
16445 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
16446 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
16447 DREF_SSC1_ENABLE);
16448
16449 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
16450 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
16451 bios_lvds_use_ssc ? "en" : "dis",
16452 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
16453 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
16454 }
16455 }
16456
16457 if (IS_GEN2(dev_priv)) {
16458 dev->mode_config.max_width = 2048;
16459 dev->mode_config.max_height = 2048;
16460 } else if (IS_GEN3(dev_priv)) {
16461 dev->mode_config.max_width = 4096;
16462 dev->mode_config.max_height = 4096;
16463 } else {
16464 dev->mode_config.max_width = 8192;
16465 dev->mode_config.max_height = 8192;
16466 }
16467
16468 if (IS_845G(dev_priv) || IS_I865G(dev_priv)) {
16469 dev->mode_config.cursor_width = IS_845G(dev_priv) ? 64 : 512;
16470 dev->mode_config.cursor_height = 1023;
16471 } else if (IS_GEN2(dev_priv)) {
16472 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
16473 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
16474 } else {
16475 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
16476 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
16477 }
16478
16479 dev->mode_config.fb_base = ggtt->mappable_base;
16480
16481 DRM_DEBUG_KMS("%d display pipe%s available.\n",
16482 INTEL_INFO(dev_priv)->num_pipes,
16483 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
16484
16485 for_each_pipe(dev_priv, pipe) {
16486 int ret;
16487
16488 ret = intel_crtc_init(dev_priv, pipe);
16489 if (ret) {
16490 drm_mode_config_cleanup(dev);
16491 return ret;
16492 }
16493 }
16494
16495 intel_update_czclk(dev_priv);
16496 intel_update_cdclk(dev_priv);
16497
16498 intel_shared_dpll_init(dev);
16499
16500 if (dev_priv->max_cdclk_freq == 0)
16501 intel_update_max_cdclk(dev_priv);
16502
16503 /* Just disable it once at startup */
16504 i915_disable_vga(dev_priv);
16505 intel_setup_outputs(dev);
16506
16507 drm_modeset_lock_all(dev);
16508 intel_modeset_setup_hw_state(dev);
16509 drm_modeset_unlock_all(dev);
16510
16511 for_each_intel_crtc(dev, crtc) {
16512 struct intel_initial_plane_config plane_config = {};
16513
16514 if (!crtc->active)
16515 continue;
16516
16517 /*
16518 * Note that reserving the BIOS fb up front prevents us
16519 * from stuffing other stolen allocations like the ring
16520 * on top. This prevents some ugliness at boot time, and
16521 * can even allow for smooth boot transitions if the BIOS
16522 * fb is large enough for the active pipe configuration.
16523 */
16524 dev_priv->display.get_initial_plane_config(crtc,
16525 &plane_config);
16526
16527 /*
16528 * If the fb is shared between multiple heads, we'll
16529 * just get the first one.
16530 */
16531 intel_find_initial_plane_obj(crtc, &plane_config);
16532 }
16533
16534 /*
16535 * Make sure hardware watermarks really match the state we read out.
16536 * Note that we need to do this after reconstructing the BIOS fb's
16537 * since the watermark calculation done here will use pstate->fb.
16538 */
16539 sanitize_watermarks(dev);
16540
16541 return 0;
16542 }
16543
16544 static void intel_enable_pipe_a(struct drm_device *dev)
16545 {
16546 struct intel_connector *connector;
16547 struct drm_connector *crt = NULL;
16548 struct intel_load_detect_pipe load_detect_temp;
16549 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
16550
16551 /* We can't just switch on the pipe A, we need to set things up with a
16552 * proper mode and output configuration. As a gross hack, enable pipe A
16553 * by enabling the load detect pipe once. */
16554 for_each_intel_connector(dev, connector) {
16555 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
16556 crt = &connector->base;
16557 break;
16558 }
16559 }
16560
16561 if (!crt)
16562 return;
16563
16564 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
16565 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
16566 }
16567
16568 static bool
16569 intel_check_plane_mapping(struct intel_crtc *crtc)
16570 {
16571 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
16572 u32 val;
16573
16574 if (INTEL_INFO(dev_priv)->num_pipes == 1)
16575 return true;
16576
16577 val = I915_READ(DSPCNTR(!crtc->plane));
16578
16579 if ((val & DISPLAY_PLANE_ENABLE) &&
16580 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
16581 return false;
16582
16583 return true;
16584 }
16585
16586 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
16587 {
16588 struct drm_device *dev = crtc->base.dev;
16589 struct intel_encoder *encoder;
16590
16591 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
16592 return true;
16593
16594 return false;
16595 }
16596
16597 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
16598 {
16599 struct drm_device *dev = encoder->base.dev;
16600 struct intel_connector *connector;
16601
16602 for_each_connector_on_encoder(dev, &encoder->base, connector)
16603 return connector;
16604
16605 return NULL;
16606 }
16607
16608 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
16609 enum transcoder pch_transcoder)
16610 {
16611 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
16612 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
16613 }
16614
16615 static void intel_sanitize_crtc(struct intel_crtc *crtc)
16616 {
16617 struct drm_device *dev = crtc->base.dev;
16618 struct drm_i915_private *dev_priv = to_i915(dev);
16619 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
16620
16621 /* Clear any frame start delays used for debugging left by the BIOS */
16622 if (!transcoder_is_dsi(cpu_transcoder)) {
16623 i915_reg_t reg = PIPECONF(cpu_transcoder);
16624
16625 I915_WRITE(reg,
16626 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
16627 }
16628
16629 /* restore vblank interrupts to correct state */
16630 drm_crtc_vblank_reset(&crtc->base);
16631 if (crtc->active) {
16632 struct intel_plane *plane;
16633
16634 drm_crtc_vblank_on(&crtc->base);
16635
16636 /* Disable everything but the primary plane */
16637 for_each_intel_plane_on_crtc(dev, crtc, plane) {
16638 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
16639 continue;
16640
16641 plane->disable_plane(&plane->base, &crtc->base);
16642 }
16643 }
16644
16645 /* We need to sanitize the plane -> pipe mapping first because this will
16646 * disable the crtc (and hence change the state) if it is wrong. Note
16647 * that gen4+ has a fixed plane -> pipe mapping. */
16648 if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
16649 bool plane;
16650
16651 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
16652 crtc->base.base.id, crtc->base.name);
16653
16654 /* Pipe has the wrong plane attached and the plane is active.
16655 * Temporarily change the plane mapping and disable everything
16656 * ... */
16657 plane = crtc->plane;
16658 to_intel_plane_state(crtc->base.primary->state)->base.visible = true;
16659 crtc->plane = !plane;
16660 intel_crtc_disable_noatomic(&crtc->base);
16661 crtc->plane = plane;
16662 }
16663
16664 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
16665 crtc->pipe == PIPE_A && !crtc->active) {
16666 /* BIOS forgot to enable pipe A, this mostly happens after
16667 * resume. Force-enable the pipe to fix this, the update_dpms
16668 * call below we restore the pipe to the right state, but leave
16669 * the required bits on. */
16670 intel_enable_pipe_a(dev);
16671 }
16672
16673 /* Adjust the state of the output pipe according to whether we
16674 * have active connectors/encoders. */
16675 if (crtc->active && !intel_crtc_has_encoders(crtc))
16676 intel_crtc_disable_noatomic(&crtc->base);
16677
16678 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
16679 /*
16680 * We start out with underrun reporting disabled to avoid races.
16681 * For correct bookkeeping mark this on active crtcs.
16682 *
16683 * Also on gmch platforms we dont have any hardware bits to
16684 * disable the underrun reporting. Which means we need to start
16685 * out with underrun reporting disabled also on inactive pipes,
16686 * since otherwise we'll complain about the garbage we read when
16687 * e.g. coming up after runtime pm.
16688 *
16689 * No protection against concurrent access is required - at
16690 * worst a fifo underrun happens which also sets this to false.
16691 */
16692 crtc->cpu_fifo_underrun_disabled = true;
16693 /*
16694 * We track the PCH trancoder underrun reporting state
16695 * within the crtc. With crtc for pipe A housing the underrun
16696 * reporting state for PCH transcoder A, crtc for pipe B housing
16697 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16698 * and marking underrun reporting as disabled for the non-existing
16699 * PCH transcoders B and C would prevent enabling the south
16700 * error interrupt (see cpt_can_enable_serr_int()).
16701 */
16702 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
16703 crtc->pch_fifo_underrun_disabled = true;
16704 }
16705 }
16706
16707 static void intel_sanitize_encoder(struct intel_encoder *encoder)
16708 {
16709 struct intel_connector *connector;
16710
16711 /* We need to check both for a crtc link (meaning that the
16712 * encoder is active and trying to read from a pipe) and the
16713 * pipe itself being active. */
16714 bool has_active_crtc = encoder->base.crtc &&
16715 to_intel_crtc(encoder->base.crtc)->active;
16716
16717 connector = intel_encoder_find_connector(encoder);
16718 if (connector && !has_active_crtc) {
16719 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16720 encoder->base.base.id,
16721 encoder->base.name);
16722
16723 /* Connector is active, but has no active pipe. This is
16724 * fallout from our resume register restoring. Disable
16725 * the encoder manually again. */
16726 if (encoder->base.crtc) {
16727 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
16728
16729 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16730 encoder->base.base.id,
16731 encoder->base.name);
16732 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16733 if (encoder->post_disable)
16734 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16735 }
16736 encoder->base.crtc = NULL;
16737
16738 /* Inconsistent output/port/pipe state happens presumably due to
16739 * a bug in one of the get_hw_state functions. Or someplace else
16740 * in our code, like the register restore mess on resume. Clamp
16741 * things to off as a safer default. */
16742
16743 connector->base.dpms = DRM_MODE_DPMS_OFF;
16744 connector->base.encoder = NULL;
16745 }
16746 /* Enabled encoders without active connectors will be fixed in
16747 * the crtc fixup. */
16748 }
16749
16750 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
16751 {
16752 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
16753
16754 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
16755 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16756 i915_disable_vga(dev_priv);
16757 }
16758 }
16759
16760 void i915_redisable_vga(struct drm_i915_private *dev_priv)
16761 {
16762 /* This function can be called both from intel_modeset_setup_hw_state or
16763 * at a very early point in our resume sequence, where the power well
16764 * structures are not yet restored. Since this function is at a very
16765 * paranoid "someone might have enabled VGA while we were not looking"
16766 * level, just check if the power well is enabled instead of trying to
16767 * follow the "don't touch the power well if we don't need it" policy
16768 * the rest of the driver uses. */
16769 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
16770 return;
16771
16772 i915_redisable_vga_power_on(dev_priv);
16773
16774 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
16775 }
16776
16777 static bool primary_get_hw_state(struct intel_plane *plane)
16778 {
16779 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16780
16781 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
16782 }
16783
16784 /* FIXME read out full plane state for all planes */
16785 static void readout_plane_state(struct intel_crtc *crtc)
16786 {
16787 struct drm_plane *primary = crtc->base.primary;
16788 struct intel_plane_state *plane_state =
16789 to_intel_plane_state(primary->state);
16790
16791 plane_state->base.visible = crtc->active &&
16792 primary_get_hw_state(to_intel_plane(primary));
16793
16794 if (plane_state->base.visible)
16795 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
16796 }
16797
16798 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16799 {
16800 struct drm_i915_private *dev_priv = to_i915(dev);
16801 enum pipe pipe;
16802 struct intel_crtc *crtc;
16803 struct intel_encoder *encoder;
16804 struct intel_connector *connector;
16805 int i;
16806
16807 dev_priv->active_crtcs = 0;
16808
16809 for_each_intel_crtc(dev, crtc) {
16810 struct intel_crtc_state *crtc_state = crtc->config;
16811 int pixclk = 0;
16812
16813 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16814 memset(crtc_state, 0, sizeof(*crtc_state));
16815 crtc_state->base.crtc = &crtc->base;
16816
16817 crtc_state->base.active = crtc_state->base.enable =
16818 dev_priv->display.get_pipe_config(crtc, crtc_state);
16819
16820 crtc->base.enabled = crtc_state->base.enable;
16821 crtc->active = crtc_state->base.active;
16822
16823 if (crtc_state->base.active) {
16824 dev_priv->active_crtcs |= 1 << crtc->pipe;
16825
16826 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
16827 pixclk = ilk_pipe_pixel_rate(crtc_state);
16828 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16829 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
16830 else
16831 WARN_ON(dev_priv->display.modeset_calc_cdclk);
16832
16833 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
16834 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
16835 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
16836 }
16837
16838 dev_priv->min_pixclk[crtc->pipe] = pixclk;
16839
16840 readout_plane_state(crtc);
16841
16842 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16843 crtc->base.base.id, crtc->base.name,
16844 crtc->active ? "enabled" : "disabled");
16845 }
16846
16847 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16848 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16849
16850 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16851 &pll->config.hw_state);
16852 pll->config.crtc_mask = 0;
16853 for_each_intel_crtc(dev, crtc) {
16854 if (crtc->active && crtc->config->shared_dpll == pll)
16855 pll->config.crtc_mask |= 1 << crtc->pipe;
16856 }
16857 pll->active_mask = pll->config.crtc_mask;
16858
16859 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16860 pll->name, pll->config.crtc_mask, pll->on);
16861 }
16862
16863 for_each_intel_encoder(dev, encoder) {
16864 pipe = 0;
16865
16866 if (encoder->get_hw_state(encoder, &pipe)) {
16867 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
16868
16869 encoder->base.crtc = &crtc->base;
16870 crtc->config->output_types |= 1 << encoder->type;
16871 encoder->get_config(encoder, crtc->config);
16872 } else {
16873 encoder->base.crtc = NULL;
16874 }
16875
16876 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16877 encoder->base.base.id,
16878 encoder->base.name,
16879 encoder->base.crtc ? "enabled" : "disabled",
16880 pipe_name(pipe));
16881 }
16882
16883 for_each_intel_connector(dev, connector) {
16884 if (connector->get_hw_state(connector)) {
16885 connector->base.dpms = DRM_MODE_DPMS_ON;
16886
16887 encoder = connector->encoder;
16888 connector->base.encoder = &encoder->base;
16889
16890 if (encoder->base.crtc &&
16891 encoder->base.crtc->state->active) {
16892 /*
16893 * This has to be done during hardware readout
16894 * because anything calling .crtc_disable may
16895 * rely on the connector_mask being accurate.
16896 */
16897 encoder->base.crtc->state->connector_mask |=
16898 1 << drm_connector_index(&connector->base);
16899 encoder->base.crtc->state->encoder_mask |=
16900 1 << drm_encoder_index(&encoder->base);
16901 }
16902
16903 } else {
16904 connector->base.dpms = DRM_MODE_DPMS_OFF;
16905 connector->base.encoder = NULL;
16906 }
16907 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16908 connector->base.base.id,
16909 connector->base.name,
16910 connector->base.encoder ? "enabled" : "disabled");
16911 }
16912
16913 for_each_intel_crtc(dev, crtc) {
16914 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16915
16916 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16917 if (crtc->base.state->active) {
16918 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16919 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16920 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16921
16922 /*
16923 * The initial mode needs to be set in order to keep
16924 * the atomic core happy. It wants a valid mode if the
16925 * crtc's enabled, so we do the above call.
16926 *
16927 * At this point some state updated by the connectors
16928 * in their ->detect() callback has not run yet, so
16929 * no recalculation can be done yet.
16930 *
16931 * Even if we could do a recalculation and modeset
16932 * right now it would cause a double modeset if
16933 * fbdev or userspace chooses a different initial mode.
16934 *
16935 * If that happens, someone indicated they wanted a
16936 * mode change, which means it's safe to do a full
16937 * recalculation.
16938 */
16939 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16940
16941 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16942 update_scanline_offset(crtc);
16943 }
16944
16945 intel_pipe_config_sanity_check(dev_priv, crtc->config);
16946 }
16947 }
16948
16949 /* Scan out the current hw modeset state,
16950 * and sanitizes it to the current state
16951 */
16952 static void
16953 intel_modeset_setup_hw_state(struct drm_device *dev)
16954 {
16955 struct drm_i915_private *dev_priv = to_i915(dev);
16956 enum pipe pipe;
16957 struct intel_crtc *crtc;
16958 struct intel_encoder *encoder;
16959 int i;
16960
16961 intel_modeset_readout_hw_state(dev);
16962
16963 /* HW state is read out, now we need to sanitize this mess. */
16964 for_each_intel_encoder(dev, encoder) {
16965 intel_sanitize_encoder(encoder);
16966 }
16967
16968 for_each_pipe(dev_priv, pipe) {
16969 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
16970
16971 intel_sanitize_crtc(crtc);
16972 intel_dump_pipe_config(crtc, crtc->config,
16973 "[setup_hw_state]");
16974 }
16975
16976 intel_modeset_update_connector_atomic_state(dev);
16977
16978 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16979 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16980
16981 if (!pll->on || pll->active_mask)
16982 continue;
16983
16984 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16985
16986 pll->funcs.disable(dev_priv, pll);
16987 pll->on = false;
16988 }
16989
16990 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16991 vlv_wm_get_hw_state(dev);
16992 else if (IS_GEN9(dev_priv))
16993 skl_wm_get_hw_state(dev);
16994 else if (HAS_PCH_SPLIT(dev_priv))
16995 ilk_wm_get_hw_state(dev);
16996
16997 for_each_intel_crtc(dev, crtc) {
16998 unsigned long put_domains;
16999
17000 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
17001 if (WARN_ON(put_domains))
17002 modeset_put_power_domains(dev_priv, put_domains);
17003 }
17004 intel_display_set_init_power(dev_priv, false);
17005
17006 intel_fbc_init_pipe_state(dev_priv);
17007 }
17008
17009 void intel_display_resume(struct drm_device *dev)
17010 {
17011 struct drm_i915_private *dev_priv = to_i915(dev);
17012 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
17013 struct drm_modeset_acquire_ctx ctx;
17014 int ret;
17015
17016 dev_priv->modeset_restore_state = NULL;
17017 if (state)
17018 state->acquire_ctx = &ctx;
17019
17020 /*
17021 * This is a cludge because with real atomic modeset mode_config.mutex
17022 * won't be taken. Unfortunately some probed state like
17023 * audio_codec_enable is still protected by mode_config.mutex, so lock
17024 * it here for now.
17025 */
17026 mutex_lock(&dev->mode_config.mutex);
17027 drm_modeset_acquire_init(&ctx, 0);
17028
17029 while (1) {
17030 ret = drm_modeset_lock_all_ctx(dev, &ctx);
17031 if (ret != -EDEADLK)
17032 break;
17033
17034 drm_modeset_backoff(&ctx);
17035 }
17036
17037 if (!ret)
17038 ret = __intel_display_resume(dev, state);
17039
17040 drm_modeset_drop_locks(&ctx);
17041 drm_modeset_acquire_fini(&ctx);
17042 mutex_unlock(&dev->mode_config.mutex);
17043
17044 if (ret)
17045 DRM_ERROR("Restoring old state failed with %i\n", ret);
17046 drm_atomic_state_put(state);
17047 }
17048
17049 void intel_modeset_gem_init(struct drm_device *dev)
17050 {
17051 struct drm_i915_private *dev_priv = to_i915(dev);
17052 struct drm_crtc *c;
17053 struct drm_i915_gem_object *obj;
17054
17055 intel_init_gt_powersave(dev_priv);
17056
17057 intel_modeset_init_hw(dev);
17058
17059 intel_setup_overlay(dev_priv);
17060
17061 /*
17062 * Make sure any fbs we allocated at startup are properly
17063 * pinned & fenced. When we do the allocation it's too early
17064 * for this.
17065 */
17066 for_each_crtc(dev, c) {
17067 struct i915_vma *vma;
17068
17069 obj = intel_fb_obj(c->primary->fb);
17070 if (obj == NULL)
17071 continue;
17072
17073 mutex_lock(&dev->struct_mutex);
17074 vma = intel_pin_and_fence_fb_obj(c->primary->fb,
17075 c->primary->state->rotation);
17076 mutex_unlock(&dev->struct_mutex);
17077 if (IS_ERR(vma)) {
17078 DRM_ERROR("failed to pin boot fb on pipe %d\n",
17079 to_intel_crtc(c)->pipe);
17080 drm_framebuffer_unreference(c->primary->fb);
17081 c->primary->fb = NULL;
17082 c->primary->crtc = c->primary->state->crtc = NULL;
17083 update_state_fb(c->primary);
17084 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
17085 }
17086 }
17087 }
17088
17089 int intel_connector_register(struct drm_connector *connector)
17090 {
17091 struct intel_connector *intel_connector = to_intel_connector(connector);
17092 int ret;
17093
17094 ret = intel_backlight_device_register(intel_connector);
17095 if (ret)
17096 goto err;
17097
17098 return 0;
17099
17100 err:
17101 return ret;
17102 }
17103
17104 void intel_connector_unregister(struct drm_connector *connector)
17105 {
17106 struct intel_connector *intel_connector = to_intel_connector(connector);
17107
17108 intel_backlight_device_unregister(intel_connector);
17109 intel_panel_destroy_backlight(connector);
17110 }
17111
17112 void intel_modeset_cleanup(struct drm_device *dev)
17113 {
17114 struct drm_i915_private *dev_priv = to_i915(dev);
17115
17116 intel_disable_gt_powersave(dev_priv);
17117
17118 /*
17119 * Interrupts and polling as the first thing to avoid creating havoc.
17120 * Too much stuff here (turning of connectors, ...) would
17121 * experience fancy races otherwise.
17122 */
17123 intel_irq_uninstall(dev_priv);
17124
17125 /*
17126 * Due to the hpd irq storm handling the hotplug work can re-arm the
17127 * poll handlers. Hence disable polling after hpd handling is shut down.
17128 */
17129 drm_kms_helper_poll_fini(dev);
17130
17131 intel_unregister_dsm_handler();
17132
17133 intel_fbc_global_disable(dev_priv);
17134
17135 /* flush any delayed tasks or pending work */
17136 flush_scheduled_work();
17137
17138 drm_mode_config_cleanup(dev);
17139
17140 intel_cleanup_overlay(dev_priv);
17141
17142 intel_cleanup_gt_powersave(dev_priv);
17143
17144 intel_teardown_gmbus(dev);
17145 }
17146
17147 void intel_connector_attach_encoder(struct intel_connector *connector,
17148 struct intel_encoder *encoder)
17149 {
17150 connector->encoder = encoder;
17151 drm_mode_connector_attach_encoder(&connector->base,
17152 &encoder->base);
17153 }
17154
17155 /*
17156 * set vga decode state - true == enable VGA decode
17157 */
17158 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
17159 {
17160 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
17161 u16 gmch_ctrl;
17162
17163 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
17164 DRM_ERROR("failed to read control word\n");
17165 return -EIO;
17166 }
17167
17168 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
17169 return 0;
17170
17171 if (state)
17172 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
17173 else
17174 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
17175
17176 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
17177 DRM_ERROR("failed to write control word\n");
17178 return -EIO;
17179 }
17180
17181 return 0;
17182 }
17183
17184 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
17185
17186 struct intel_display_error_state {
17187
17188 u32 power_well_driver;
17189
17190 int num_transcoders;
17191
17192 struct intel_cursor_error_state {
17193 u32 control;
17194 u32 position;
17195 u32 base;
17196 u32 size;
17197 } cursor[I915_MAX_PIPES];
17198
17199 struct intel_pipe_error_state {
17200 bool power_domain_on;
17201 u32 source;
17202 u32 stat;
17203 } pipe[I915_MAX_PIPES];
17204
17205 struct intel_plane_error_state {
17206 u32 control;
17207 u32 stride;
17208 u32 size;
17209 u32 pos;
17210 u32 addr;
17211 u32 surface;
17212 u32 tile_offset;
17213 } plane[I915_MAX_PIPES];
17214
17215 struct intel_transcoder_error_state {
17216 bool power_domain_on;
17217 enum transcoder cpu_transcoder;
17218
17219 u32 conf;
17220
17221 u32 htotal;
17222 u32 hblank;
17223 u32 hsync;
17224 u32 vtotal;
17225 u32 vblank;
17226 u32 vsync;
17227 } transcoder[4];
17228 };
17229
17230 struct intel_display_error_state *
17231 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
17232 {
17233 struct intel_display_error_state *error;
17234 int transcoders[] = {
17235 TRANSCODER_A,
17236 TRANSCODER_B,
17237 TRANSCODER_C,
17238 TRANSCODER_EDP,
17239 };
17240 int i;
17241
17242 if (INTEL_INFO(dev_priv)->num_pipes == 0)
17243 return NULL;
17244
17245 error = kzalloc(sizeof(*error), GFP_ATOMIC);
17246 if (error == NULL)
17247 return NULL;
17248
17249 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17250 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
17251
17252 for_each_pipe(dev_priv, i) {
17253 error->pipe[i].power_domain_on =
17254 __intel_display_power_is_enabled(dev_priv,
17255 POWER_DOMAIN_PIPE(i));
17256 if (!error->pipe[i].power_domain_on)
17257 continue;
17258
17259 error->cursor[i].control = I915_READ(CURCNTR(i));
17260 error->cursor[i].position = I915_READ(CURPOS(i));
17261 error->cursor[i].base = I915_READ(CURBASE(i));
17262
17263 error->plane[i].control = I915_READ(DSPCNTR(i));
17264 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
17265 if (INTEL_GEN(dev_priv) <= 3) {
17266 error->plane[i].size = I915_READ(DSPSIZE(i));
17267 error->plane[i].pos = I915_READ(DSPPOS(i));
17268 }
17269 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17270 error->plane[i].addr = I915_READ(DSPADDR(i));
17271 if (INTEL_GEN(dev_priv) >= 4) {
17272 error->plane[i].surface = I915_READ(DSPSURF(i));
17273 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
17274 }
17275
17276 error->pipe[i].source = I915_READ(PIPESRC(i));
17277
17278 if (HAS_GMCH_DISPLAY(dev_priv))
17279 error->pipe[i].stat = I915_READ(PIPESTAT(i));
17280 }
17281
17282 /* Note: this does not include DSI transcoders. */
17283 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
17284 if (HAS_DDI(dev_priv))
17285 error->num_transcoders++; /* Account for eDP. */
17286
17287 for (i = 0; i < error->num_transcoders; i++) {
17288 enum transcoder cpu_transcoder = transcoders[i];
17289
17290 error->transcoder[i].power_domain_on =
17291 __intel_display_power_is_enabled(dev_priv,
17292 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
17293 if (!error->transcoder[i].power_domain_on)
17294 continue;
17295
17296 error->transcoder[i].cpu_transcoder = cpu_transcoder;
17297
17298 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
17299 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
17300 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
17301 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
17302 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
17303 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
17304 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
17305 }
17306
17307 return error;
17308 }
17309
17310 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
17311
17312 void
17313 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
17314 struct drm_i915_private *dev_priv,
17315 struct intel_display_error_state *error)
17316 {
17317 int i;
17318
17319 if (!error)
17320 return;
17321
17322 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
17323 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17324 err_printf(m, "PWR_WELL_CTL2: %08x\n",
17325 error->power_well_driver);
17326 for_each_pipe(dev_priv, i) {
17327 err_printf(m, "Pipe [%d]:\n", i);
17328 err_printf(m, " Power: %s\n",
17329 onoff(error->pipe[i].power_domain_on));
17330 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
17331 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
17332
17333 err_printf(m, "Plane [%d]:\n", i);
17334 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
17335 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
17336 if (INTEL_GEN(dev_priv) <= 3) {
17337 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
17338 err_printf(m, " POS: %08x\n", error->plane[i].pos);
17339 }
17340 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17341 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
17342 if (INTEL_GEN(dev_priv) >= 4) {
17343 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
17344 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
17345 }
17346
17347 err_printf(m, "Cursor [%d]:\n", i);
17348 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
17349 err_printf(m, " POS: %08x\n", error->cursor[i].position);
17350 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
17351 }
17352
17353 for (i = 0; i < error->num_transcoders; i++) {
17354 err_printf(m, "CPU transcoder: %s\n",
17355 transcoder_name(error->transcoder[i].cpu_transcoder));
17356 err_printf(m, " Power: %s\n",
17357 onoff(error->transcoder[i].power_domain_on));
17358 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
17359 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
17360 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
17361 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
17362 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
17363 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
17364 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
17365 }
17366 }
17367
17368 #endif
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