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[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "i915_gem_clflush.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
51
52 static bool is_mmio_work(struct intel_flip_work *work)
53 {
54 return work->mmio_work.func;
55 }
56
57 /* Primary plane formats for gen <= 3 */
58 static const uint32_t i8xx_primary_formats[] = {
59 DRM_FORMAT_C8,
60 DRM_FORMAT_RGB565,
61 DRM_FORMAT_XRGB1555,
62 DRM_FORMAT_XRGB8888,
63 };
64
65 /* Primary plane formats for gen >= 4 */
66 static const uint32_t i965_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_XRGB2101010,
72 DRM_FORMAT_XBGR2101010,
73 };
74
75 static const uint32_t skl_primary_formats[] = {
76 DRM_FORMAT_C8,
77 DRM_FORMAT_RGB565,
78 DRM_FORMAT_XRGB8888,
79 DRM_FORMAT_XBGR8888,
80 DRM_FORMAT_ARGB8888,
81 DRM_FORMAT_ABGR8888,
82 DRM_FORMAT_XRGB2101010,
83 DRM_FORMAT_XBGR2101010,
84 DRM_FORMAT_YUYV,
85 DRM_FORMAT_YVYU,
86 DRM_FORMAT_UYVY,
87 DRM_FORMAT_VYUY,
88 };
89
90 /* Cursor formats */
91 static const uint32_t intel_cursor_formats[] = {
92 DRM_FORMAT_ARGB8888,
93 };
94
95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
96 struct intel_crtc_state *pipe_config);
97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
98 struct intel_crtc_state *pipe_config);
99
100 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
101 struct drm_i915_gem_object *obj,
102 struct drm_mode_fb_cmd2 *mode_cmd);
103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
107 struct intel_link_m_n *m_n,
108 struct intel_link_m_n *m2_n2);
109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
112 static void vlv_prepare_pll(struct intel_crtc *crtc,
113 const struct intel_crtc_state *pipe_config);
114 static void chv_prepare_pll(struct intel_crtc *crtc,
115 const struct intel_crtc_state *pipe_config);
116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
119 struct intel_crtc_state *crtc_state);
120 static void skylake_pfit_enable(struct intel_crtc *crtc);
121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
123 static void intel_modeset_setup_hw_state(struct drm_device *dev);
124 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
125
126 struct intel_limit {
127 struct {
128 int min, max;
129 } dot, vco, n, m, m1, m2, p, p1;
130
131 struct {
132 int dot_limit;
133 int p2_slow, p2_fast;
134 } p2;
135 };
136
137 /* returns HPLL frequency in kHz */
138 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
139 {
140 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
141
142 /* Obtain SKU information */
143 mutex_lock(&dev_priv->sb_lock);
144 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
145 CCK_FUSE_HPLL_FREQ_MASK;
146 mutex_unlock(&dev_priv->sb_lock);
147
148 return vco_freq[hpll_freq] * 1000;
149 }
150
151 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
152 const char *name, u32 reg, int ref_freq)
153 {
154 u32 val;
155 int divider;
156
157 mutex_lock(&dev_priv->sb_lock);
158 val = vlv_cck_read(dev_priv, reg);
159 mutex_unlock(&dev_priv->sb_lock);
160
161 divider = val & CCK_FREQUENCY_VALUES;
162
163 WARN((val & CCK_FREQUENCY_STATUS) !=
164 (divider << CCK_FREQUENCY_STATUS_SHIFT),
165 "%s change in progress\n", name);
166
167 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
168 }
169
170 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
171 const char *name, u32 reg)
172 {
173 if (dev_priv->hpll_freq == 0)
174 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
175
176 return vlv_get_cck_clock(dev_priv, name, reg,
177 dev_priv->hpll_freq);
178 }
179
180 static void intel_update_czclk(struct drm_i915_private *dev_priv)
181 {
182 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
183 return;
184
185 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
186 CCK_CZ_CLOCK_CONTROL);
187
188 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
189 }
190
191 static inline u32 /* units of 100MHz */
192 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
193 const struct intel_crtc_state *pipe_config)
194 {
195 if (HAS_DDI(dev_priv))
196 return pipe_config->port_clock; /* SPLL */
197 else if (IS_GEN5(dev_priv))
198 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
199 else
200 return 270000;
201 }
202
203 static const struct intel_limit intel_limits_i8xx_dac = {
204 .dot = { .min = 25000, .max = 350000 },
205 .vco = { .min = 908000, .max = 1512000 },
206 .n = { .min = 2, .max = 16 },
207 .m = { .min = 96, .max = 140 },
208 .m1 = { .min = 18, .max = 26 },
209 .m2 = { .min = 6, .max = 16 },
210 .p = { .min = 4, .max = 128 },
211 .p1 = { .min = 2, .max = 33 },
212 .p2 = { .dot_limit = 165000,
213 .p2_slow = 4, .p2_fast = 2 },
214 };
215
216 static const struct intel_limit intel_limits_i8xx_dvo = {
217 .dot = { .min = 25000, .max = 350000 },
218 .vco = { .min = 908000, .max = 1512000 },
219 .n = { .min = 2, .max = 16 },
220 .m = { .min = 96, .max = 140 },
221 .m1 = { .min = 18, .max = 26 },
222 .m2 = { .min = 6, .max = 16 },
223 .p = { .min = 4, .max = 128 },
224 .p1 = { .min = 2, .max = 33 },
225 .p2 = { .dot_limit = 165000,
226 .p2_slow = 4, .p2_fast = 4 },
227 };
228
229 static const struct intel_limit intel_limits_i8xx_lvds = {
230 .dot = { .min = 25000, .max = 350000 },
231 .vco = { .min = 908000, .max = 1512000 },
232 .n = { .min = 2, .max = 16 },
233 .m = { .min = 96, .max = 140 },
234 .m1 = { .min = 18, .max = 26 },
235 .m2 = { .min = 6, .max = 16 },
236 .p = { .min = 4, .max = 128 },
237 .p1 = { .min = 1, .max = 6 },
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 14, .p2_fast = 7 },
240 };
241
242 static const struct intel_limit intel_limits_i9xx_sdvo = {
243 .dot = { .min = 20000, .max = 400000 },
244 .vco = { .min = 1400000, .max = 2800000 },
245 .n = { .min = 1, .max = 6 },
246 .m = { .min = 70, .max = 120 },
247 .m1 = { .min = 8, .max = 18 },
248 .m2 = { .min = 3, .max = 7 },
249 .p = { .min = 5, .max = 80 },
250 .p1 = { .min = 1, .max = 8 },
251 .p2 = { .dot_limit = 200000,
252 .p2_slow = 10, .p2_fast = 5 },
253 };
254
255 static const struct intel_limit intel_limits_i9xx_lvds = {
256 .dot = { .min = 20000, .max = 400000 },
257 .vco = { .min = 1400000, .max = 2800000 },
258 .n = { .min = 1, .max = 6 },
259 .m = { .min = 70, .max = 120 },
260 .m1 = { .min = 8, .max = 18 },
261 .m2 = { .min = 3, .max = 7 },
262 .p = { .min = 7, .max = 98 },
263 .p1 = { .min = 1, .max = 8 },
264 .p2 = { .dot_limit = 112000,
265 .p2_slow = 14, .p2_fast = 7 },
266 };
267
268
269 static const struct intel_limit intel_limits_g4x_sdvo = {
270 .dot = { .min = 25000, .max = 270000 },
271 .vco = { .min = 1750000, .max = 3500000},
272 .n = { .min = 1, .max = 4 },
273 .m = { .min = 104, .max = 138 },
274 .m1 = { .min = 17, .max = 23 },
275 .m2 = { .min = 5, .max = 11 },
276 .p = { .min = 10, .max = 30 },
277 .p1 = { .min = 1, .max = 3},
278 .p2 = { .dot_limit = 270000,
279 .p2_slow = 10,
280 .p2_fast = 10
281 },
282 };
283
284 static const struct intel_limit intel_limits_g4x_hdmi = {
285 .dot = { .min = 22000, .max = 400000 },
286 .vco = { .min = 1750000, .max = 3500000},
287 .n = { .min = 1, .max = 4 },
288 .m = { .min = 104, .max = 138 },
289 .m1 = { .min = 16, .max = 23 },
290 .m2 = { .min = 5, .max = 11 },
291 .p = { .min = 5, .max = 80 },
292 .p1 = { .min = 1, .max = 8},
293 .p2 = { .dot_limit = 165000,
294 .p2_slow = 10, .p2_fast = 5 },
295 };
296
297 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
298 .dot = { .min = 20000, .max = 115000 },
299 .vco = { .min = 1750000, .max = 3500000 },
300 .n = { .min = 1, .max = 3 },
301 .m = { .min = 104, .max = 138 },
302 .m1 = { .min = 17, .max = 23 },
303 .m2 = { .min = 5, .max = 11 },
304 .p = { .min = 28, .max = 112 },
305 .p1 = { .min = 2, .max = 8 },
306 .p2 = { .dot_limit = 0,
307 .p2_slow = 14, .p2_fast = 14
308 },
309 };
310
311 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
312 .dot = { .min = 80000, .max = 224000 },
313 .vco = { .min = 1750000, .max = 3500000 },
314 .n = { .min = 1, .max = 3 },
315 .m = { .min = 104, .max = 138 },
316 .m1 = { .min = 17, .max = 23 },
317 .m2 = { .min = 5, .max = 11 },
318 .p = { .min = 14, .max = 42 },
319 .p1 = { .min = 2, .max = 6 },
320 .p2 = { .dot_limit = 0,
321 .p2_slow = 7, .p2_fast = 7
322 },
323 };
324
325 static const struct intel_limit intel_limits_pineview_sdvo = {
326 .dot = { .min = 20000, .max = 400000},
327 .vco = { .min = 1700000, .max = 3500000 },
328 /* Pineview's Ncounter is a ring counter */
329 .n = { .min = 3, .max = 6 },
330 .m = { .min = 2, .max = 256 },
331 /* Pineview only has one combined m divider, which we treat as m2. */
332 .m1 = { .min = 0, .max = 0 },
333 .m2 = { .min = 0, .max = 254 },
334 .p = { .min = 5, .max = 80 },
335 .p1 = { .min = 1, .max = 8 },
336 .p2 = { .dot_limit = 200000,
337 .p2_slow = 10, .p2_fast = 5 },
338 };
339
340 static const struct intel_limit intel_limits_pineview_lvds = {
341 .dot = { .min = 20000, .max = 400000 },
342 .vco = { .min = 1700000, .max = 3500000 },
343 .n = { .min = 3, .max = 6 },
344 .m = { .min = 2, .max = 256 },
345 .m1 = { .min = 0, .max = 0 },
346 .m2 = { .min = 0, .max = 254 },
347 .p = { .min = 7, .max = 112 },
348 .p1 = { .min = 1, .max = 8 },
349 .p2 = { .dot_limit = 112000,
350 .p2_slow = 14, .p2_fast = 14 },
351 };
352
353 /* Ironlake / Sandybridge
354 *
355 * We calculate clock using (register_value + 2) for N/M1/M2, so here
356 * the range value for them is (actual_value - 2).
357 */
358 static const struct intel_limit intel_limits_ironlake_dac = {
359 .dot = { .min = 25000, .max = 350000 },
360 .vco = { .min = 1760000, .max = 3510000 },
361 .n = { .min = 1, .max = 5 },
362 .m = { .min = 79, .max = 127 },
363 .m1 = { .min = 12, .max = 22 },
364 .m2 = { .min = 5, .max = 9 },
365 .p = { .min = 5, .max = 80 },
366 .p1 = { .min = 1, .max = 8 },
367 .p2 = { .dot_limit = 225000,
368 .p2_slow = 10, .p2_fast = 5 },
369 };
370
371 static const struct intel_limit intel_limits_ironlake_single_lvds = {
372 .dot = { .min = 25000, .max = 350000 },
373 .vco = { .min = 1760000, .max = 3510000 },
374 .n = { .min = 1, .max = 3 },
375 .m = { .min = 79, .max = 118 },
376 .m1 = { .min = 12, .max = 22 },
377 .m2 = { .min = 5, .max = 9 },
378 .p = { .min = 28, .max = 112 },
379 .p1 = { .min = 2, .max = 8 },
380 .p2 = { .dot_limit = 225000,
381 .p2_slow = 14, .p2_fast = 14 },
382 };
383
384 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
385 .dot = { .min = 25000, .max = 350000 },
386 .vco = { .min = 1760000, .max = 3510000 },
387 .n = { .min = 1, .max = 3 },
388 .m = { .min = 79, .max = 127 },
389 .m1 = { .min = 12, .max = 22 },
390 .m2 = { .min = 5, .max = 9 },
391 .p = { .min = 14, .max = 56 },
392 .p1 = { .min = 2, .max = 8 },
393 .p2 = { .dot_limit = 225000,
394 .p2_slow = 7, .p2_fast = 7 },
395 };
396
397 /* LVDS 100mhz refclk limits. */
398 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
399 .dot = { .min = 25000, .max = 350000 },
400 .vco = { .min = 1760000, .max = 3510000 },
401 .n = { .min = 1, .max = 2 },
402 .m = { .min = 79, .max = 126 },
403 .m1 = { .min = 12, .max = 22 },
404 .m2 = { .min = 5, .max = 9 },
405 .p = { .min = 28, .max = 112 },
406 .p1 = { .min = 2, .max = 8 },
407 .p2 = { .dot_limit = 225000,
408 .p2_slow = 14, .p2_fast = 14 },
409 };
410
411 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
412 .dot = { .min = 25000, .max = 350000 },
413 .vco = { .min = 1760000, .max = 3510000 },
414 .n = { .min = 1, .max = 3 },
415 .m = { .min = 79, .max = 126 },
416 .m1 = { .min = 12, .max = 22 },
417 .m2 = { .min = 5, .max = 9 },
418 .p = { .min = 14, .max = 42 },
419 .p1 = { .min = 2, .max = 6 },
420 .p2 = { .dot_limit = 225000,
421 .p2_slow = 7, .p2_fast = 7 },
422 };
423
424 static const struct intel_limit intel_limits_vlv = {
425 /*
426 * These are the data rate limits (measured in fast clocks)
427 * since those are the strictest limits we have. The fast
428 * clock and actual rate limits are more relaxed, so checking
429 * them would make no difference.
430 */
431 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
432 .vco = { .min = 4000000, .max = 6000000 },
433 .n = { .min = 1, .max = 7 },
434 .m1 = { .min = 2, .max = 3 },
435 .m2 = { .min = 11, .max = 156 },
436 .p1 = { .min = 2, .max = 3 },
437 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
438 };
439
440 static const struct intel_limit intel_limits_chv = {
441 /*
442 * These are the data rate limits (measured in fast clocks)
443 * since those are the strictest limits we have. The fast
444 * clock and actual rate limits are more relaxed, so checking
445 * them would make no difference.
446 */
447 .dot = { .min = 25000 * 5, .max = 540000 * 5},
448 .vco = { .min = 4800000, .max = 6480000 },
449 .n = { .min = 1, .max = 1 },
450 .m1 = { .min = 2, .max = 2 },
451 .m2 = { .min = 24 << 22, .max = 175 << 22 },
452 .p1 = { .min = 2, .max = 4 },
453 .p2 = { .p2_slow = 1, .p2_fast = 14 },
454 };
455
456 static const struct intel_limit intel_limits_bxt = {
457 /* FIXME: find real dot limits */
458 .dot = { .min = 0, .max = INT_MAX },
459 .vco = { .min = 4800000, .max = 6700000 },
460 .n = { .min = 1, .max = 1 },
461 .m1 = { .min = 2, .max = 2 },
462 /* FIXME: find real m2 limits */
463 .m2 = { .min = 2 << 22, .max = 255 << 22 },
464 .p1 = { .min = 2, .max = 4 },
465 .p2 = { .p2_slow = 1, .p2_fast = 20 },
466 };
467
468 static bool
469 needs_modeset(struct drm_crtc_state *state)
470 {
471 return drm_atomic_crtc_needs_modeset(state);
472 }
473
474 /*
475 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
476 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
477 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
478 * The helpers' return value is the rate of the clock that is fed to the
479 * display engine's pipe which can be the above fast dot clock rate or a
480 * divided-down version of it.
481 */
482 /* m1 is reserved as 0 in Pineview, n is a ring counter */
483 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
484 {
485 clock->m = clock->m2 + 2;
486 clock->p = clock->p1 * clock->p2;
487 if (WARN_ON(clock->n == 0 || clock->p == 0))
488 return 0;
489 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
490 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
491
492 return clock->dot;
493 }
494
495 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
496 {
497 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
498 }
499
500 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
501 {
502 clock->m = i9xx_dpll_compute_m(clock);
503 clock->p = clock->p1 * clock->p2;
504 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
505 return 0;
506 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
507 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
508
509 return clock->dot;
510 }
511
512 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
513 {
514 clock->m = clock->m1 * clock->m2;
515 clock->p = clock->p1 * clock->p2;
516 if (WARN_ON(clock->n == 0 || clock->p == 0))
517 return 0;
518 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
519 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
520
521 return clock->dot / 5;
522 }
523
524 int chv_calc_dpll_params(int refclk, struct dpll *clock)
525 {
526 clock->m = clock->m1 * clock->m2;
527 clock->p = clock->p1 * clock->p2;
528 if (WARN_ON(clock->n == 0 || clock->p == 0))
529 return 0;
530 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
531 clock->n << 22);
532 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
533
534 return clock->dot / 5;
535 }
536
537 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
538 /**
539 * Returns whether the given set of divisors are valid for a given refclk with
540 * the given connectors.
541 */
542
543 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
544 const struct intel_limit *limit,
545 const struct dpll *clock)
546 {
547 if (clock->n < limit->n.min || limit->n.max < clock->n)
548 INTELPllInvalid("n out of range\n");
549 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
550 INTELPllInvalid("p1 out of range\n");
551 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
552 INTELPllInvalid("m2 out of range\n");
553 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
554 INTELPllInvalid("m1 out of range\n");
555
556 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
557 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
558 if (clock->m1 <= clock->m2)
559 INTELPllInvalid("m1 <= m2\n");
560
561 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
562 !IS_GEN9_LP(dev_priv)) {
563 if (clock->p < limit->p.min || limit->p.max < clock->p)
564 INTELPllInvalid("p out of range\n");
565 if (clock->m < limit->m.min || limit->m.max < clock->m)
566 INTELPllInvalid("m out of range\n");
567 }
568
569 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
570 INTELPllInvalid("vco out of range\n");
571 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
572 * connector, etc., rather than just a single range.
573 */
574 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
575 INTELPllInvalid("dot out of range\n");
576
577 return true;
578 }
579
580 static int
581 i9xx_select_p2_div(const struct intel_limit *limit,
582 const struct intel_crtc_state *crtc_state,
583 int target)
584 {
585 struct drm_device *dev = crtc_state->base.crtc->dev;
586
587 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
588 /*
589 * For LVDS just rely on its current settings for dual-channel.
590 * We haven't figured out how to reliably set up different
591 * single/dual channel state, if we even can.
592 */
593 if (intel_is_dual_link_lvds(dev))
594 return limit->p2.p2_fast;
595 else
596 return limit->p2.p2_slow;
597 } else {
598 if (target < limit->p2.dot_limit)
599 return limit->p2.p2_slow;
600 else
601 return limit->p2.p2_fast;
602 }
603 }
604
605 /*
606 * Returns a set of divisors for the desired target clock with the given
607 * refclk, or FALSE. The returned values represent the clock equation:
608 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
609 *
610 * Target and reference clocks are specified in kHz.
611 *
612 * If match_clock is provided, then best_clock P divider must match the P
613 * divider from @match_clock used for LVDS downclocking.
614 */
615 static bool
616 i9xx_find_best_dpll(const struct intel_limit *limit,
617 struct intel_crtc_state *crtc_state,
618 int target, int refclk, struct dpll *match_clock,
619 struct dpll *best_clock)
620 {
621 struct drm_device *dev = crtc_state->base.crtc->dev;
622 struct dpll clock;
623 int err = target;
624
625 memset(best_clock, 0, sizeof(*best_clock));
626
627 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
628
629 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
630 clock.m1++) {
631 for (clock.m2 = limit->m2.min;
632 clock.m2 <= limit->m2.max; clock.m2++) {
633 if (clock.m2 >= clock.m1)
634 break;
635 for (clock.n = limit->n.min;
636 clock.n <= limit->n.max; clock.n++) {
637 for (clock.p1 = limit->p1.min;
638 clock.p1 <= limit->p1.max; clock.p1++) {
639 int this_err;
640
641 i9xx_calc_dpll_params(refclk, &clock);
642 if (!intel_PLL_is_valid(to_i915(dev),
643 limit,
644 &clock))
645 continue;
646 if (match_clock &&
647 clock.p != match_clock->p)
648 continue;
649
650 this_err = abs(clock.dot - target);
651 if (this_err < err) {
652 *best_clock = clock;
653 err = this_err;
654 }
655 }
656 }
657 }
658 }
659
660 return (err != target);
661 }
662
663 /*
664 * Returns a set of divisors for the desired target clock with the given
665 * refclk, or FALSE. The returned values represent the clock equation:
666 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
667 *
668 * Target and reference clocks are specified in kHz.
669 *
670 * If match_clock is provided, then best_clock P divider must match the P
671 * divider from @match_clock used for LVDS downclocking.
672 */
673 static bool
674 pnv_find_best_dpll(const struct intel_limit *limit,
675 struct intel_crtc_state *crtc_state,
676 int target, int refclk, struct dpll *match_clock,
677 struct dpll *best_clock)
678 {
679 struct drm_device *dev = crtc_state->base.crtc->dev;
680 struct dpll clock;
681 int err = target;
682
683 memset(best_clock, 0, sizeof(*best_clock));
684
685 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
686
687 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
688 clock.m1++) {
689 for (clock.m2 = limit->m2.min;
690 clock.m2 <= limit->m2.max; clock.m2++) {
691 for (clock.n = limit->n.min;
692 clock.n <= limit->n.max; clock.n++) {
693 for (clock.p1 = limit->p1.min;
694 clock.p1 <= limit->p1.max; clock.p1++) {
695 int this_err;
696
697 pnv_calc_dpll_params(refclk, &clock);
698 if (!intel_PLL_is_valid(to_i915(dev),
699 limit,
700 &clock))
701 continue;
702 if (match_clock &&
703 clock.p != match_clock->p)
704 continue;
705
706 this_err = abs(clock.dot - target);
707 if (this_err < err) {
708 *best_clock = clock;
709 err = this_err;
710 }
711 }
712 }
713 }
714 }
715
716 return (err != target);
717 }
718
719 /*
720 * Returns a set of divisors for the desired target clock with the given
721 * refclk, or FALSE. The returned values represent the clock equation:
722 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
723 *
724 * Target and reference clocks are specified in kHz.
725 *
726 * If match_clock is provided, then best_clock P divider must match the P
727 * divider from @match_clock used for LVDS downclocking.
728 */
729 static bool
730 g4x_find_best_dpll(const struct intel_limit *limit,
731 struct intel_crtc_state *crtc_state,
732 int target, int refclk, struct dpll *match_clock,
733 struct dpll *best_clock)
734 {
735 struct drm_device *dev = crtc_state->base.crtc->dev;
736 struct dpll clock;
737 int max_n;
738 bool found = false;
739 /* approximately equals target * 0.00585 */
740 int err_most = (target >> 8) + (target >> 9);
741
742 memset(best_clock, 0, sizeof(*best_clock));
743
744 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
745
746 max_n = limit->n.max;
747 /* based on hardware requirement, prefer smaller n to precision */
748 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
749 /* based on hardware requirement, prefere larger m1,m2 */
750 for (clock.m1 = limit->m1.max;
751 clock.m1 >= limit->m1.min; clock.m1--) {
752 for (clock.m2 = limit->m2.max;
753 clock.m2 >= limit->m2.min; clock.m2--) {
754 for (clock.p1 = limit->p1.max;
755 clock.p1 >= limit->p1.min; clock.p1--) {
756 int this_err;
757
758 i9xx_calc_dpll_params(refclk, &clock);
759 if (!intel_PLL_is_valid(to_i915(dev),
760 limit,
761 &clock))
762 continue;
763
764 this_err = abs(clock.dot - target);
765 if (this_err < err_most) {
766 *best_clock = clock;
767 err_most = this_err;
768 max_n = clock.n;
769 found = true;
770 }
771 }
772 }
773 }
774 }
775 return found;
776 }
777
778 /*
779 * Check if the calculated PLL configuration is more optimal compared to the
780 * best configuration and error found so far. Return the calculated error.
781 */
782 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
783 const struct dpll *calculated_clock,
784 const struct dpll *best_clock,
785 unsigned int best_error_ppm,
786 unsigned int *error_ppm)
787 {
788 /*
789 * For CHV ignore the error and consider only the P value.
790 * Prefer a bigger P value based on HW requirements.
791 */
792 if (IS_CHERRYVIEW(to_i915(dev))) {
793 *error_ppm = 0;
794
795 return calculated_clock->p > best_clock->p;
796 }
797
798 if (WARN_ON_ONCE(!target_freq))
799 return false;
800
801 *error_ppm = div_u64(1000000ULL *
802 abs(target_freq - calculated_clock->dot),
803 target_freq);
804 /*
805 * Prefer a better P value over a better (smaller) error if the error
806 * is small. Ensure this preference for future configurations too by
807 * setting the error to 0.
808 */
809 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
810 *error_ppm = 0;
811
812 return true;
813 }
814
815 return *error_ppm + 10 < best_error_ppm;
816 }
817
818 /*
819 * Returns a set of divisors for the desired target clock with the given
820 * refclk, or FALSE. The returned values represent the clock equation:
821 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
822 */
823 static bool
824 vlv_find_best_dpll(const struct intel_limit *limit,
825 struct intel_crtc_state *crtc_state,
826 int target, int refclk, struct dpll *match_clock,
827 struct dpll *best_clock)
828 {
829 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
830 struct drm_device *dev = crtc->base.dev;
831 struct dpll clock;
832 unsigned int bestppm = 1000000;
833 /* min update 19.2 MHz */
834 int max_n = min(limit->n.max, refclk / 19200);
835 bool found = false;
836
837 target *= 5; /* fast clock */
838
839 memset(best_clock, 0, sizeof(*best_clock));
840
841 /* based on hardware requirement, prefer smaller n to precision */
842 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
843 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
844 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
845 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
846 clock.p = clock.p1 * clock.p2;
847 /* based on hardware requirement, prefer bigger m1,m2 values */
848 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
849 unsigned int ppm;
850
851 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
852 refclk * clock.m1);
853
854 vlv_calc_dpll_params(refclk, &clock);
855
856 if (!intel_PLL_is_valid(to_i915(dev),
857 limit,
858 &clock))
859 continue;
860
861 if (!vlv_PLL_is_optimal(dev, target,
862 &clock,
863 best_clock,
864 bestppm, &ppm))
865 continue;
866
867 *best_clock = clock;
868 bestppm = ppm;
869 found = true;
870 }
871 }
872 }
873 }
874
875 return found;
876 }
877
878 /*
879 * Returns a set of divisors for the desired target clock with the given
880 * refclk, or FALSE. The returned values represent the clock equation:
881 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
882 */
883 static bool
884 chv_find_best_dpll(const struct intel_limit *limit,
885 struct intel_crtc_state *crtc_state,
886 int target, int refclk, struct dpll *match_clock,
887 struct dpll *best_clock)
888 {
889 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
890 struct drm_device *dev = crtc->base.dev;
891 unsigned int best_error_ppm;
892 struct dpll clock;
893 uint64_t m2;
894 int found = false;
895
896 memset(best_clock, 0, sizeof(*best_clock));
897 best_error_ppm = 1000000;
898
899 /*
900 * Based on hardware doc, the n always set to 1, and m1 always
901 * set to 2. If requires to support 200Mhz refclk, we need to
902 * revisit this because n may not 1 anymore.
903 */
904 clock.n = 1, clock.m1 = 2;
905 target *= 5; /* fast clock */
906
907 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
908 for (clock.p2 = limit->p2.p2_fast;
909 clock.p2 >= limit->p2.p2_slow;
910 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
911 unsigned int error_ppm;
912
913 clock.p = clock.p1 * clock.p2;
914
915 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
916 clock.n) << 22, refclk * clock.m1);
917
918 if (m2 > INT_MAX/clock.m1)
919 continue;
920
921 clock.m2 = m2;
922
923 chv_calc_dpll_params(refclk, &clock);
924
925 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
926 continue;
927
928 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
929 best_error_ppm, &error_ppm))
930 continue;
931
932 *best_clock = clock;
933 best_error_ppm = error_ppm;
934 found = true;
935 }
936 }
937
938 return found;
939 }
940
941 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
942 struct dpll *best_clock)
943 {
944 int refclk = 100000;
945 const struct intel_limit *limit = &intel_limits_bxt;
946
947 return chv_find_best_dpll(limit, crtc_state,
948 target_clock, refclk, NULL, best_clock);
949 }
950
951 bool intel_crtc_active(struct intel_crtc *crtc)
952 {
953 /* Be paranoid as we can arrive here with only partial
954 * state retrieved from the hardware during setup.
955 *
956 * We can ditch the adjusted_mode.crtc_clock check as soon
957 * as Haswell has gained clock readout/fastboot support.
958 *
959 * We can ditch the crtc->primary->fb check as soon as we can
960 * properly reconstruct framebuffers.
961 *
962 * FIXME: The intel_crtc->active here should be switched to
963 * crtc->state->active once we have proper CRTC states wired up
964 * for atomic.
965 */
966 return crtc->active && crtc->base.primary->state->fb &&
967 crtc->config->base.adjusted_mode.crtc_clock;
968 }
969
970 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
971 enum pipe pipe)
972 {
973 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
974
975 return crtc->config->cpu_transcoder;
976 }
977
978 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
979 {
980 i915_reg_t reg = PIPEDSL(pipe);
981 u32 line1, line2;
982 u32 line_mask;
983
984 if (IS_GEN2(dev_priv))
985 line_mask = DSL_LINEMASK_GEN2;
986 else
987 line_mask = DSL_LINEMASK_GEN3;
988
989 line1 = I915_READ(reg) & line_mask;
990 msleep(5);
991 line2 = I915_READ(reg) & line_mask;
992
993 return line1 == line2;
994 }
995
996 /*
997 * intel_wait_for_pipe_off - wait for pipe to turn off
998 * @crtc: crtc whose pipe to wait for
999 *
1000 * After disabling a pipe, we can't wait for vblank in the usual way,
1001 * spinning on the vblank interrupt status bit, since we won't actually
1002 * see an interrupt when the pipe is disabled.
1003 *
1004 * On Gen4 and above:
1005 * wait for the pipe register state bit to turn off
1006 *
1007 * Otherwise:
1008 * wait for the display line value to settle (it usually
1009 * ends up stopping at the start of the next frame).
1010 *
1011 */
1012 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1013 {
1014 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1015 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1016 enum pipe pipe = crtc->pipe;
1017
1018 if (INTEL_GEN(dev_priv) >= 4) {
1019 i915_reg_t reg = PIPECONF(cpu_transcoder);
1020
1021 /* Wait for the Pipe State to go off */
1022 if (intel_wait_for_register(dev_priv,
1023 reg, I965_PIPECONF_ACTIVE, 0,
1024 100))
1025 WARN(1, "pipe_off wait timed out\n");
1026 } else {
1027 /* Wait for the display line to settle */
1028 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1029 WARN(1, "pipe_off wait timed out\n");
1030 }
1031 }
1032
1033 /* Only for pre-ILK configs */
1034 void assert_pll(struct drm_i915_private *dev_priv,
1035 enum pipe pipe, bool state)
1036 {
1037 u32 val;
1038 bool cur_state;
1039
1040 val = I915_READ(DPLL(pipe));
1041 cur_state = !!(val & DPLL_VCO_ENABLE);
1042 I915_STATE_WARN(cur_state != state,
1043 "PLL state assertion failure (expected %s, current %s)\n",
1044 onoff(state), onoff(cur_state));
1045 }
1046
1047 /* XXX: the dsi pll is shared between MIPI DSI ports */
1048 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1049 {
1050 u32 val;
1051 bool cur_state;
1052
1053 mutex_lock(&dev_priv->sb_lock);
1054 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1055 mutex_unlock(&dev_priv->sb_lock);
1056
1057 cur_state = val & DSI_PLL_VCO_EN;
1058 I915_STATE_WARN(cur_state != state,
1059 "DSI PLL state assertion failure (expected %s, current %s)\n",
1060 onoff(state), onoff(cur_state));
1061 }
1062
1063 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1064 enum pipe pipe, bool state)
1065 {
1066 bool cur_state;
1067 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1068 pipe);
1069
1070 if (HAS_DDI(dev_priv)) {
1071 /* DDI does not have a specific FDI_TX register */
1072 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1073 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1074 } else {
1075 u32 val = I915_READ(FDI_TX_CTL(pipe));
1076 cur_state = !!(val & FDI_TX_ENABLE);
1077 }
1078 I915_STATE_WARN(cur_state != state,
1079 "FDI TX state assertion failure (expected %s, current %s)\n",
1080 onoff(state), onoff(cur_state));
1081 }
1082 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1083 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1084
1085 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1086 enum pipe pipe, bool state)
1087 {
1088 u32 val;
1089 bool cur_state;
1090
1091 val = I915_READ(FDI_RX_CTL(pipe));
1092 cur_state = !!(val & FDI_RX_ENABLE);
1093 I915_STATE_WARN(cur_state != state,
1094 "FDI RX state assertion failure (expected %s, current %s)\n",
1095 onoff(state), onoff(cur_state));
1096 }
1097 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1098 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1099
1100 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1101 enum pipe pipe)
1102 {
1103 u32 val;
1104
1105 /* ILK FDI PLL is always enabled */
1106 if (IS_GEN5(dev_priv))
1107 return;
1108
1109 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1110 if (HAS_DDI(dev_priv))
1111 return;
1112
1113 val = I915_READ(FDI_TX_CTL(pipe));
1114 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1115 }
1116
1117 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1118 enum pipe pipe, bool state)
1119 {
1120 u32 val;
1121 bool cur_state;
1122
1123 val = I915_READ(FDI_RX_CTL(pipe));
1124 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1125 I915_STATE_WARN(cur_state != state,
1126 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1127 onoff(state), onoff(cur_state));
1128 }
1129
1130 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1131 {
1132 i915_reg_t pp_reg;
1133 u32 val;
1134 enum pipe panel_pipe = PIPE_A;
1135 bool locked = true;
1136
1137 if (WARN_ON(HAS_DDI(dev_priv)))
1138 return;
1139
1140 if (HAS_PCH_SPLIT(dev_priv)) {
1141 u32 port_sel;
1142
1143 pp_reg = PP_CONTROL(0);
1144 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1145
1146 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1147 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1148 panel_pipe = PIPE_B;
1149 /* XXX: else fix for eDP */
1150 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1151 /* presumably write lock depends on pipe, not port select */
1152 pp_reg = PP_CONTROL(pipe);
1153 panel_pipe = pipe;
1154 } else {
1155 pp_reg = PP_CONTROL(0);
1156 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1157 panel_pipe = PIPE_B;
1158 }
1159
1160 val = I915_READ(pp_reg);
1161 if (!(val & PANEL_POWER_ON) ||
1162 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1163 locked = false;
1164
1165 I915_STATE_WARN(panel_pipe == pipe && locked,
1166 "panel assertion failure, pipe %c regs locked\n",
1167 pipe_name(pipe));
1168 }
1169
1170 static void assert_cursor(struct drm_i915_private *dev_priv,
1171 enum pipe pipe, bool state)
1172 {
1173 bool cur_state;
1174
1175 if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1176 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1177 else
1178 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1179
1180 I915_STATE_WARN(cur_state != state,
1181 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1182 pipe_name(pipe), onoff(state), onoff(cur_state));
1183 }
1184 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1185 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1186
1187 void assert_pipe(struct drm_i915_private *dev_priv,
1188 enum pipe pipe, bool state)
1189 {
1190 bool cur_state;
1191 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1192 pipe);
1193 enum intel_display_power_domain power_domain;
1194
1195 /* if we need the pipe quirk it must be always on */
1196 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1197 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1198 state = true;
1199
1200 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1201 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1202 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1203 cur_state = !!(val & PIPECONF_ENABLE);
1204
1205 intel_display_power_put(dev_priv, power_domain);
1206 } else {
1207 cur_state = false;
1208 }
1209
1210 I915_STATE_WARN(cur_state != state,
1211 "pipe %c assertion failure (expected %s, current %s)\n",
1212 pipe_name(pipe), onoff(state), onoff(cur_state));
1213 }
1214
1215 static void assert_plane(struct drm_i915_private *dev_priv,
1216 enum plane plane, bool state)
1217 {
1218 u32 val;
1219 bool cur_state;
1220
1221 val = I915_READ(DSPCNTR(plane));
1222 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1223 I915_STATE_WARN(cur_state != state,
1224 "plane %c assertion failure (expected %s, current %s)\n",
1225 plane_name(plane), onoff(state), onoff(cur_state));
1226 }
1227
1228 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1229 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1230
1231 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1232 enum pipe pipe)
1233 {
1234 int i;
1235
1236 /* Primary planes are fixed to pipes on gen4+ */
1237 if (INTEL_GEN(dev_priv) >= 4) {
1238 u32 val = I915_READ(DSPCNTR(pipe));
1239 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1240 "plane %c assertion failure, should be disabled but not\n",
1241 plane_name(pipe));
1242 return;
1243 }
1244
1245 /* Need to check both planes against the pipe */
1246 for_each_pipe(dev_priv, i) {
1247 u32 val = I915_READ(DSPCNTR(i));
1248 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1249 DISPPLANE_SEL_PIPE_SHIFT;
1250 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1251 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1252 plane_name(i), pipe_name(pipe));
1253 }
1254 }
1255
1256 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1257 enum pipe pipe)
1258 {
1259 int sprite;
1260
1261 if (INTEL_GEN(dev_priv) >= 9) {
1262 for_each_sprite(dev_priv, pipe, sprite) {
1263 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1264 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1265 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1266 sprite, pipe_name(pipe));
1267 }
1268 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1269 for_each_sprite(dev_priv, pipe, sprite) {
1270 u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1271 I915_STATE_WARN(val & SP_ENABLE,
1272 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1273 sprite_name(pipe, sprite), pipe_name(pipe));
1274 }
1275 } else if (INTEL_GEN(dev_priv) >= 7) {
1276 u32 val = I915_READ(SPRCTL(pipe));
1277 I915_STATE_WARN(val & SPRITE_ENABLE,
1278 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1279 plane_name(pipe), pipe_name(pipe));
1280 } else if (INTEL_GEN(dev_priv) >= 5) {
1281 u32 val = I915_READ(DVSCNTR(pipe));
1282 I915_STATE_WARN(val & DVS_ENABLE,
1283 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1284 plane_name(pipe), pipe_name(pipe));
1285 }
1286 }
1287
1288 static void assert_vblank_disabled(struct drm_crtc *crtc)
1289 {
1290 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1291 drm_crtc_vblank_put(crtc);
1292 }
1293
1294 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1295 enum pipe pipe)
1296 {
1297 u32 val;
1298 bool enabled;
1299
1300 val = I915_READ(PCH_TRANSCONF(pipe));
1301 enabled = !!(val & TRANS_ENABLE);
1302 I915_STATE_WARN(enabled,
1303 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1304 pipe_name(pipe));
1305 }
1306
1307 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1308 enum pipe pipe, u32 port_sel, u32 val)
1309 {
1310 if ((val & DP_PORT_EN) == 0)
1311 return false;
1312
1313 if (HAS_PCH_CPT(dev_priv)) {
1314 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else if (IS_CHERRYVIEW(dev_priv)) {
1318 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1319 return false;
1320 } else {
1321 if ((val & DP_PIPE_MASK) != (pipe << 30))
1322 return false;
1323 }
1324 return true;
1325 }
1326
1327 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328 enum pipe pipe, u32 val)
1329 {
1330 if ((val & SDVO_ENABLE) == 0)
1331 return false;
1332
1333 if (HAS_PCH_CPT(dev_priv)) {
1334 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1335 return false;
1336 } else if (IS_CHERRYVIEW(dev_priv)) {
1337 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1338 return false;
1339 } else {
1340 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1341 return false;
1342 }
1343 return true;
1344 }
1345
1346 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1347 enum pipe pipe, u32 val)
1348 {
1349 if ((val & LVDS_PORT_EN) == 0)
1350 return false;
1351
1352 if (HAS_PCH_CPT(dev_priv)) {
1353 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1354 return false;
1355 } else {
1356 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1357 return false;
1358 }
1359 return true;
1360 }
1361
1362 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1363 enum pipe pipe, u32 val)
1364 {
1365 if ((val & ADPA_DAC_ENABLE) == 0)
1366 return false;
1367 if (HAS_PCH_CPT(dev_priv)) {
1368 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1369 return false;
1370 } else {
1371 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1372 return false;
1373 }
1374 return true;
1375 }
1376
1377 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1378 enum pipe pipe, i915_reg_t reg,
1379 u32 port_sel)
1380 {
1381 u32 val = I915_READ(reg);
1382 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1383 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1384 i915_mmio_reg_offset(reg), pipe_name(pipe));
1385
1386 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1387 && (val & DP_PIPEB_SELECT),
1388 "IBX PCH dp port still using transcoder B\n");
1389 }
1390
1391 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1392 enum pipe pipe, i915_reg_t reg)
1393 {
1394 u32 val = I915_READ(reg);
1395 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1396 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1397 i915_mmio_reg_offset(reg), pipe_name(pipe));
1398
1399 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1400 && (val & SDVO_PIPE_B_SELECT),
1401 "IBX PCH hdmi port still using transcoder B\n");
1402 }
1403
1404 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1405 enum pipe pipe)
1406 {
1407 u32 val;
1408
1409 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1410 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1411 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1412
1413 val = I915_READ(PCH_ADPA);
1414 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1415 "PCH VGA enabled on transcoder %c, should be disabled\n",
1416 pipe_name(pipe));
1417
1418 val = I915_READ(PCH_LVDS);
1419 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1420 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1421 pipe_name(pipe));
1422
1423 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1424 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1425 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1426 }
1427
1428 static void _vlv_enable_pll(struct intel_crtc *crtc,
1429 const struct intel_crtc_state *pipe_config)
1430 {
1431 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1432 enum pipe pipe = crtc->pipe;
1433
1434 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1435 POSTING_READ(DPLL(pipe));
1436 udelay(150);
1437
1438 if (intel_wait_for_register(dev_priv,
1439 DPLL(pipe),
1440 DPLL_LOCK_VLV,
1441 DPLL_LOCK_VLV,
1442 1))
1443 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1444 }
1445
1446 static void vlv_enable_pll(struct intel_crtc *crtc,
1447 const struct intel_crtc_state *pipe_config)
1448 {
1449 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1450 enum pipe pipe = crtc->pipe;
1451
1452 assert_pipe_disabled(dev_priv, pipe);
1453
1454 /* PLL is protected by panel, make sure we can write it */
1455 assert_panel_unlocked(dev_priv, pipe);
1456
1457 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1458 _vlv_enable_pll(crtc, pipe_config);
1459
1460 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1461 POSTING_READ(DPLL_MD(pipe));
1462 }
1463
1464
1465 static void _chv_enable_pll(struct intel_crtc *crtc,
1466 const struct intel_crtc_state *pipe_config)
1467 {
1468 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1469 enum pipe pipe = crtc->pipe;
1470 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1471 u32 tmp;
1472
1473 mutex_lock(&dev_priv->sb_lock);
1474
1475 /* Enable back the 10bit clock to display controller */
1476 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1477 tmp |= DPIO_DCLKP_EN;
1478 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1479
1480 mutex_unlock(&dev_priv->sb_lock);
1481
1482 /*
1483 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1484 */
1485 udelay(1);
1486
1487 /* Enable PLL */
1488 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1489
1490 /* Check PLL is locked */
1491 if (intel_wait_for_register(dev_priv,
1492 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1493 1))
1494 DRM_ERROR("PLL %d failed to lock\n", pipe);
1495 }
1496
1497 static void chv_enable_pll(struct intel_crtc *crtc,
1498 const struct intel_crtc_state *pipe_config)
1499 {
1500 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1501 enum pipe pipe = crtc->pipe;
1502
1503 assert_pipe_disabled(dev_priv, pipe);
1504
1505 /* PLL is protected by panel, make sure we can write it */
1506 assert_panel_unlocked(dev_priv, pipe);
1507
1508 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1509 _chv_enable_pll(crtc, pipe_config);
1510
1511 if (pipe != PIPE_A) {
1512 /*
1513 * WaPixelRepeatModeFixForC0:chv
1514 *
1515 * DPLLCMD is AWOL. Use chicken bits to propagate
1516 * the value from DPLLBMD to either pipe B or C.
1517 */
1518 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1519 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1520 I915_WRITE(CBR4_VLV, 0);
1521 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1522
1523 /*
1524 * DPLLB VGA mode also seems to cause problems.
1525 * We should always have it disabled.
1526 */
1527 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1528 } else {
1529 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1530 POSTING_READ(DPLL_MD(pipe));
1531 }
1532 }
1533
1534 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1535 {
1536 struct intel_crtc *crtc;
1537 int count = 0;
1538
1539 for_each_intel_crtc(&dev_priv->drm, crtc) {
1540 count += crtc->base.state->active &&
1541 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1542 }
1543
1544 return count;
1545 }
1546
1547 static void i9xx_enable_pll(struct intel_crtc *crtc)
1548 {
1549 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1550 i915_reg_t reg = DPLL(crtc->pipe);
1551 u32 dpll = crtc->config->dpll_hw_state.dpll;
1552
1553 assert_pipe_disabled(dev_priv, crtc->pipe);
1554
1555 /* PLL is protected by panel, make sure we can write it */
1556 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1557 assert_panel_unlocked(dev_priv, crtc->pipe);
1558
1559 /* Enable DVO 2x clock on both PLLs if necessary */
1560 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1561 /*
1562 * It appears to be important that we don't enable this
1563 * for the current pipe before otherwise configuring the
1564 * PLL. No idea how this should be handled if multiple
1565 * DVO outputs are enabled simultaneosly.
1566 */
1567 dpll |= DPLL_DVO_2X_MODE;
1568 I915_WRITE(DPLL(!crtc->pipe),
1569 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1570 }
1571
1572 /*
1573 * Apparently we need to have VGA mode enabled prior to changing
1574 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1575 * dividers, even though the register value does change.
1576 */
1577 I915_WRITE(reg, 0);
1578
1579 I915_WRITE(reg, dpll);
1580
1581 /* Wait for the clocks to stabilize. */
1582 POSTING_READ(reg);
1583 udelay(150);
1584
1585 if (INTEL_GEN(dev_priv) >= 4) {
1586 I915_WRITE(DPLL_MD(crtc->pipe),
1587 crtc->config->dpll_hw_state.dpll_md);
1588 } else {
1589 /* The pixel multiplier can only be updated once the
1590 * DPLL is enabled and the clocks are stable.
1591 *
1592 * So write it again.
1593 */
1594 I915_WRITE(reg, dpll);
1595 }
1596
1597 /* We do this three times for luck */
1598 I915_WRITE(reg, dpll);
1599 POSTING_READ(reg);
1600 udelay(150); /* wait for warmup */
1601 I915_WRITE(reg, dpll);
1602 POSTING_READ(reg);
1603 udelay(150); /* wait for warmup */
1604 I915_WRITE(reg, dpll);
1605 POSTING_READ(reg);
1606 udelay(150); /* wait for warmup */
1607 }
1608
1609 /**
1610 * i9xx_disable_pll - disable a PLL
1611 * @dev_priv: i915 private structure
1612 * @pipe: pipe PLL to disable
1613 *
1614 * Disable the PLL for @pipe, making sure the pipe is off first.
1615 *
1616 * Note! This is for pre-ILK only.
1617 */
1618 static void i9xx_disable_pll(struct intel_crtc *crtc)
1619 {
1620 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1621 enum pipe pipe = crtc->pipe;
1622
1623 /* Disable DVO 2x clock on both PLLs if necessary */
1624 if (IS_I830(dev_priv) &&
1625 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1626 !intel_num_dvo_pipes(dev_priv)) {
1627 I915_WRITE(DPLL(PIPE_B),
1628 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1629 I915_WRITE(DPLL(PIPE_A),
1630 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1631 }
1632
1633 /* Don't disable pipe or pipe PLLs if needed */
1634 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1635 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1636 return;
1637
1638 /* Make sure the pipe isn't still relying on us */
1639 assert_pipe_disabled(dev_priv, pipe);
1640
1641 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1642 POSTING_READ(DPLL(pipe));
1643 }
1644
1645 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1646 {
1647 u32 val;
1648
1649 /* Make sure the pipe isn't still relying on us */
1650 assert_pipe_disabled(dev_priv, pipe);
1651
1652 val = DPLL_INTEGRATED_REF_CLK_VLV |
1653 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1654 if (pipe != PIPE_A)
1655 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1656
1657 I915_WRITE(DPLL(pipe), val);
1658 POSTING_READ(DPLL(pipe));
1659 }
1660
1661 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1662 {
1663 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1664 u32 val;
1665
1666 /* Make sure the pipe isn't still relying on us */
1667 assert_pipe_disabled(dev_priv, pipe);
1668
1669 val = DPLL_SSC_REF_CLK_CHV |
1670 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1671 if (pipe != PIPE_A)
1672 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1673
1674 I915_WRITE(DPLL(pipe), val);
1675 POSTING_READ(DPLL(pipe));
1676
1677 mutex_lock(&dev_priv->sb_lock);
1678
1679 /* Disable 10bit clock to display controller */
1680 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1681 val &= ~DPIO_DCLKP_EN;
1682 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1683
1684 mutex_unlock(&dev_priv->sb_lock);
1685 }
1686
1687 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1688 struct intel_digital_port *dport,
1689 unsigned int expected_mask)
1690 {
1691 u32 port_mask;
1692 i915_reg_t dpll_reg;
1693
1694 switch (dport->port) {
1695 case PORT_B:
1696 port_mask = DPLL_PORTB_READY_MASK;
1697 dpll_reg = DPLL(0);
1698 break;
1699 case PORT_C:
1700 port_mask = DPLL_PORTC_READY_MASK;
1701 dpll_reg = DPLL(0);
1702 expected_mask <<= 4;
1703 break;
1704 case PORT_D:
1705 port_mask = DPLL_PORTD_READY_MASK;
1706 dpll_reg = DPIO_PHY_STATUS;
1707 break;
1708 default:
1709 BUG();
1710 }
1711
1712 if (intel_wait_for_register(dev_priv,
1713 dpll_reg, port_mask, expected_mask,
1714 1000))
1715 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1716 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1717 }
1718
1719 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1720 enum pipe pipe)
1721 {
1722 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1723 pipe);
1724 i915_reg_t reg;
1725 uint32_t val, pipeconf_val;
1726
1727 /* Make sure PCH DPLL is enabled */
1728 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1729
1730 /* FDI must be feeding us bits for PCH ports */
1731 assert_fdi_tx_enabled(dev_priv, pipe);
1732 assert_fdi_rx_enabled(dev_priv, pipe);
1733
1734 if (HAS_PCH_CPT(dev_priv)) {
1735 /* Workaround: Set the timing override bit before enabling the
1736 * pch transcoder. */
1737 reg = TRANS_CHICKEN2(pipe);
1738 val = I915_READ(reg);
1739 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1740 I915_WRITE(reg, val);
1741 }
1742
1743 reg = PCH_TRANSCONF(pipe);
1744 val = I915_READ(reg);
1745 pipeconf_val = I915_READ(PIPECONF(pipe));
1746
1747 if (HAS_PCH_IBX(dev_priv)) {
1748 /*
1749 * Make the BPC in transcoder be consistent with
1750 * that in pipeconf reg. For HDMI we must use 8bpc
1751 * here for both 8bpc and 12bpc.
1752 */
1753 val &= ~PIPECONF_BPC_MASK;
1754 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1755 val |= PIPECONF_8BPC;
1756 else
1757 val |= pipeconf_val & PIPECONF_BPC_MASK;
1758 }
1759
1760 val &= ~TRANS_INTERLACE_MASK;
1761 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1762 if (HAS_PCH_IBX(dev_priv) &&
1763 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1764 val |= TRANS_LEGACY_INTERLACED_ILK;
1765 else
1766 val |= TRANS_INTERLACED;
1767 else
1768 val |= TRANS_PROGRESSIVE;
1769
1770 I915_WRITE(reg, val | TRANS_ENABLE);
1771 if (intel_wait_for_register(dev_priv,
1772 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1773 100))
1774 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1775 }
1776
1777 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1778 enum transcoder cpu_transcoder)
1779 {
1780 u32 val, pipeconf_val;
1781
1782 /* FDI must be feeding us bits for PCH ports */
1783 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1784 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1785
1786 /* Workaround: set timing override bit. */
1787 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1788 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1789 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1790
1791 val = TRANS_ENABLE;
1792 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1793
1794 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1795 PIPECONF_INTERLACED_ILK)
1796 val |= TRANS_INTERLACED;
1797 else
1798 val |= TRANS_PROGRESSIVE;
1799
1800 I915_WRITE(LPT_TRANSCONF, val);
1801 if (intel_wait_for_register(dev_priv,
1802 LPT_TRANSCONF,
1803 TRANS_STATE_ENABLE,
1804 TRANS_STATE_ENABLE,
1805 100))
1806 DRM_ERROR("Failed to enable PCH transcoder\n");
1807 }
1808
1809 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1810 enum pipe pipe)
1811 {
1812 i915_reg_t reg;
1813 uint32_t val;
1814
1815 /* FDI relies on the transcoder */
1816 assert_fdi_tx_disabled(dev_priv, pipe);
1817 assert_fdi_rx_disabled(dev_priv, pipe);
1818
1819 /* Ports must be off as well */
1820 assert_pch_ports_disabled(dev_priv, pipe);
1821
1822 reg = PCH_TRANSCONF(pipe);
1823 val = I915_READ(reg);
1824 val &= ~TRANS_ENABLE;
1825 I915_WRITE(reg, val);
1826 /* wait for PCH transcoder off, transcoder state */
1827 if (intel_wait_for_register(dev_priv,
1828 reg, TRANS_STATE_ENABLE, 0,
1829 50))
1830 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1831
1832 if (HAS_PCH_CPT(dev_priv)) {
1833 /* Workaround: Clear the timing override chicken bit again. */
1834 reg = TRANS_CHICKEN2(pipe);
1835 val = I915_READ(reg);
1836 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1837 I915_WRITE(reg, val);
1838 }
1839 }
1840
1841 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1842 {
1843 u32 val;
1844
1845 val = I915_READ(LPT_TRANSCONF);
1846 val &= ~TRANS_ENABLE;
1847 I915_WRITE(LPT_TRANSCONF, val);
1848 /* wait for PCH transcoder off, transcoder state */
1849 if (intel_wait_for_register(dev_priv,
1850 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1851 50))
1852 DRM_ERROR("Failed to disable PCH transcoder\n");
1853
1854 /* Workaround: clear timing override bit. */
1855 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1856 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1857 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1858 }
1859
1860 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1861 {
1862 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1863
1864 WARN_ON(!crtc->config->has_pch_encoder);
1865
1866 if (HAS_PCH_LPT(dev_priv))
1867 return TRANSCODER_A;
1868 else
1869 return (enum transcoder) crtc->pipe;
1870 }
1871
1872 /**
1873 * intel_enable_pipe - enable a pipe, asserting requirements
1874 * @crtc: crtc responsible for the pipe
1875 *
1876 * Enable @crtc's pipe, making sure that various hardware specific requirements
1877 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1878 */
1879 static void intel_enable_pipe(struct intel_crtc *crtc)
1880 {
1881 struct drm_device *dev = crtc->base.dev;
1882 struct drm_i915_private *dev_priv = to_i915(dev);
1883 enum pipe pipe = crtc->pipe;
1884 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1885 i915_reg_t reg;
1886 u32 val;
1887
1888 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1889
1890 assert_planes_disabled(dev_priv, pipe);
1891 assert_cursor_disabled(dev_priv, pipe);
1892 assert_sprites_disabled(dev_priv, pipe);
1893
1894 /*
1895 * A pipe without a PLL won't actually be able to drive bits from
1896 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1897 * need the check.
1898 */
1899 if (HAS_GMCH_DISPLAY(dev_priv)) {
1900 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1901 assert_dsi_pll_enabled(dev_priv);
1902 else
1903 assert_pll_enabled(dev_priv, pipe);
1904 } else {
1905 if (crtc->config->has_pch_encoder) {
1906 /* if driving the PCH, we need FDI enabled */
1907 assert_fdi_rx_pll_enabled(dev_priv,
1908 (enum pipe) intel_crtc_pch_transcoder(crtc));
1909 assert_fdi_tx_pll_enabled(dev_priv,
1910 (enum pipe) cpu_transcoder);
1911 }
1912 /* FIXME: assert CPU port conditions for SNB+ */
1913 }
1914
1915 reg = PIPECONF(cpu_transcoder);
1916 val = I915_READ(reg);
1917 if (val & PIPECONF_ENABLE) {
1918 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1919 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1920 return;
1921 }
1922
1923 I915_WRITE(reg, val | PIPECONF_ENABLE);
1924 POSTING_READ(reg);
1925
1926 /*
1927 * Until the pipe starts DSL will read as 0, which would cause
1928 * an apparent vblank timestamp jump, which messes up also the
1929 * frame count when it's derived from the timestamps. So let's
1930 * wait for the pipe to start properly before we call
1931 * drm_crtc_vblank_on()
1932 */
1933 if (dev->max_vblank_count == 0 &&
1934 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1935 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1936 }
1937
1938 /**
1939 * intel_disable_pipe - disable a pipe, asserting requirements
1940 * @crtc: crtc whose pipes is to be disabled
1941 *
1942 * Disable the pipe of @crtc, making sure that various hardware
1943 * specific requirements are met, if applicable, e.g. plane
1944 * disabled, panel fitter off, etc.
1945 *
1946 * Will wait until the pipe has shut down before returning.
1947 */
1948 static void intel_disable_pipe(struct intel_crtc *crtc)
1949 {
1950 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1951 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1952 enum pipe pipe = crtc->pipe;
1953 i915_reg_t reg;
1954 u32 val;
1955
1956 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1957
1958 /*
1959 * Make sure planes won't keep trying to pump pixels to us,
1960 * or we might hang the display.
1961 */
1962 assert_planes_disabled(dev_priv, pipe);
1963 assert_cursor_disabled(dev_priv, pipe);
1964 assert_sprites_disabled(dev_priv, pipe);
1965
1966 reg = PIPECONF(cpu_transcoder);
1967 val = I915_READ(reg);
1968 if ((val & PIPECONF_ENABLE) == 0)
1969 return;
1970
1971 /*
1972 * Double wide has implications for planes
1973 * so best keep it disabled when not needed.
1974 */
1975 if (crtc->config->double_wide)
1976 val &= ~PIPECONF_DOUBLE_WIDE;
1977
1978 /* Don't disable pipe or pipe PLLs if needed */
1979 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
1980 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1981 val &= ~PIPECONF_ENABLE;
1982
1983 I915_WRITE(reg, val);
1984 if ((val & PIPECONF_ENABLE) == 0)
1985 intel_wait_for_pipe_off(crtc);
1986 }
1987
1988 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1989 {
1990 return IS_GEN2(dev_priv) ? 2048 : 4096;
1991 }
1992
1993 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
1994 uint64_t fb_modifier, unsigned int cpp)
1995 {
1996 switch (fb_modifier) {
1997 case DRM_FORMAT_MOD_NONE:
1998 return cpp;
1999 case I915_FORMAT_MOD_X_TILED:
2000 if (IS_GEN2(dev_priv))
2001 return 128;
2002 else
2003 return 512;
2004 case I915_FORMAT_MOD_Y_TILED:
2005 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2006 return 128;
2007 else
2008 return 512;
2009 case I915_FORMAT_MOD_Yf_TILED:
2010 switch (cpp) {
2011 case 1:
2012 return 64;
2013 case 2:
2014 case 4:
2015 return 128;
2016 case 8:
2017 case 16:
2018 return 256;
2019 default:
2020 MISSING_CASE(cpp);
2021 return cpp;
2022 }
2023 break;
2024 default:
2025 MISSING_CASE(fb_modifier);
2026 return cpp;
2027 }
2028 }
2029
2030 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2031 uint64_t fb_modifier, unsigned int cpp)
2032 {
2033 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2034 return 1;
2035 else
2036 return intel_tile_size(dev_priv) /
2037 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2038 }
2039
2040 /* Return the tile dimensions in pixel units */
2041 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2042 unsigned int *tile_width,
2043 unsigned int *tile_height,
2044 uint64_t fb_modifier,
2045 unsigned int cpp)
2046 {
2047 unsigned int tile_width_bytes =
2048 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2049
2050 *tile_width = tile_width_bytes / cpp;
2051 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2052 }
2053
2054 unsigned int
2055 intel_fb_align_height(struct drm_i915_private *dev_priv,
2056 unsigned int height,
2057 uint32_t pixel_format,
2058 uint64_t fb_modifier)
2059 {
2060 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2061 unsigned int tile_height = intel_tile_height(dev_priv, fb_modifier, cpp);
2062
2063 return ALIGN(height, tile_height);
2064 }
2065
2066 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2067 {
2068 unsigned int size = 0;
2069 int i;
2070
2071 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2072 size += rot_info->plane[i].width * rot_info->plane[i].height;
2073
2074 return size;
2075 }
2076
2077 static void
2078 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2079 const struct drm_framebuffer *fb,
2080 unsigned int rotation)
2081 {
2082 view->type = I915_GGTT_VIEW_NORMAL;
2083 if (drm_rotation_90_or_270(rotation)) {
2084 view->type = I915_GGTT_VIEW_ROTATED;
2085 view->rotated = to_intel_framebuffer(fb)->rot_info;
2086 }
2087 }
2088
2089 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2090 {
2091 if (INTEL_INFO(dev_priv)->gen >= 9)
2092 return 256 * 1024;
2093 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2094 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2095 return 128 * 1024;
2096 else if (INTEL_INFO(dev_priv)->gen >= 4)
2097 return 4 * 1024;
2098 else
2099 return 0;
2100 }
2101
2102 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2103 uint64_t fb_modifier)
2104 {
2105 switch (fb_modifier) {
2106 case DRM_FORMAT_MOD_NONE:
2107 return intel_linear_alignment(dev_priv);
2108 case I915_FORMAT_MOD_X_TILED:
2109 if (INTEL_INFO(dev_priv)->gen >= 9)
2110 return 256 * 1024;
2111 return 0;
2112 case I915_FORMAT_MOD_Y_TILED:
2113 case I915_FORMAT_MOD_Yf_TILED:
2114 return 1 * 1024 * 1024;
2115 default:
2116 MISSING_CASE(fb_modifier);
2117 return 0;
2118 }
2119 }
2120
2121 struct i915_vma *
2122 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2123 {
2124 struct drm_device *dev = fb->dev;
2125 struct drm_i915_private *dev_priv = to_i915(dev);
2126 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2127 struct i915_ggtt_view view;
2128 struct i915_vma *vma;
2129 u32 alignment;
2130
2131 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2132
2133 alignment = intel_surf_alignment(dev_priv, fb->modifier);
2134
2135 intel_fill_fb_ggtt_view(&view, fb, rotation);
2136
2137 /* Note that the w/a also requires 64 PTE of padding following the
2138 * bo. We currently fill all unused PTE with the shadow page and so
2139 * we should always have valid PTE following the scanout preventing
2140 * the VT-d warning.
2141 */
2142 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2143 alignment = 256 * 1024;
2144
2145 /*
2146 * Global gtt pte registers are special registers which actually forward
2147 * writes to a chunk of system memory. Which means that there is no risk
2148 * that the register values disappear as soon as we call
2149 * intel_runtime_pm_put(), so it is correct to wrap only the
2150 * pin/unpin/fence and not more.
2151 */
2152 intel_runtime_pm_get(dev_priv);
2153
2154 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2155 if (IS_ERR(vma))
2156 goto err;
2157
2158 if (i915_vma_is_map_and_fenceable(vma)) {
2159 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2160 * fence, whereas 965+ only requires a fence if using
2161 * framebuffer compression. For simplicity, we always, when
2162 * possible, install a fence as the cost is not that onerous.
2163 *
2164 * If we fail to fence the tiled scanout, then either the
2165 * modeset will reject the change (which is highly unlikely as
2166 * the affected systems, all but one, do not have unmappable
2167 * space) or we will not be able to enable full powersaving
2168 * techniques (also likely not to apply due to various limits
2169 * FBC and the like impose on the size of the buffer, which
2170 * presumably we violated anyway with this unmappable buffer).
2171 * Anyway, it is presumably better to stumble onwards with
2172 * something and try to run the system in a "less than optimal"
2173 * mode that matches the user configuration.
2174 */
2175 if (i915_vma_get_fence(vma) == 0)
2176 i915_vma_pin_fence(vma);
2177 }
2178
2179 i915_vma_get(vma);
2180 err:
2181 intel_runtime_pm_put(dev_priv);
2182 return vma;
2183 }
2184
2185 void intel_unpin_fb_vma(struct i915_vma *vma)
2186 {
2187 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2188
2189 i915_vma_unpin_fence(vma);
2190 i915_gem_object_unpin_from_display_plane(vma);
2191 i915_vma_put(vma);
2192 }
2193
2194 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2195 unsigned int rotation)
2196 {
2197 if (drm_rotation_90_or_270(rotation))
2198 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2199 else
2200 return fb->pitches[plane];
2201 }
2202
2203 /*
2204 * Convert the x/y offsets into a linear offset.
2205 * Only valid with 0/180 degree rotation, which is fine since linear
2206 * offset is only used with linear buffers on pre-hsw and tiled buffers
2207 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2208 */
2209 u32 intel_fb_xy_to_linear(int x, int y,
2210 const struct intel_plane_state *state,
2211 int plane)
2212 {
2213 const struct drm_framebuffer *fb = state->base.fb;
2214 unsigned int cpp = fb->format->cpp[plane];
2215 unsigned int pitch = fb->pitches[plane];
2216
2217 return y * pitch + x * cpp;
2218 }
2219
2220 /*
2221 * Add the x/y offsets derived from fb->offsets[] to the user
2222 * specified plane src x/y offsets. The resulting x/y offsets
2223 * specify the start of scanout from the beginning of the gtt mapping.
2224 */
2225 void intel_add_fb_offsets(int *x, int *y,
2226 const struct intel_plane_state *state,
2227 int plane)
2228
2229 {
2230 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2231 unsigned int rotation = state->base.rotation;
2232
2233 if (drm_rotation_90_or_270(rotation)) {
2234 *x += intel_fb->rotated[plane].x;
2235 *y += intel_fb->rotated[plane].y;
2236 } else {
2237 *x += intel_fb->normal[plane].x;
2238 *y += intel_fb->normal[plane].y;
2239 }
2240 }
2241
2242 /*
2243 * Input tile dimensions and pitch must already be
2244 * rotated to match x and y, and in pixel units.
2245 */
2246 static u32 _intel_adjust_tile_offset(int *x, int *y,
2247 unsigned int tile_width,
2248 unsigned int tile_height,
2249 unsigned int tile_size,
2250 unsigned int pitch_tiles,
2251 u32 old_offset,
2252 u32 new_offset)
2253 {
2254 unsigned int pitch_pixels = pitch_tiles * tile_width;
2255 unsigned int tiles;
2256
2257 WARN_ON(old_offset & (tile_size - 1));
2258 WARN_ON(new_offset & (tile_size - 1));
2259 WARN_ON(new_offset > old_offset);
2260
2261 tiles = (old_offset - new_offset) / tile_size;
2262
2263 *y += tiles / pitch_tiles * tile_height;
2264 *x += tiles % pitch_tiles * tile_width;
2265
2266 /* minimize x in case it got needlessly big */
2267 *y += *x / pitch_pixels * tile_height;
2268 *x %= pitch_pixels;
2269
2270 return new_offset;
2271 }
2272
2273 /*
2274 * Adjust the tile offset by moving the difference into
2275 * the x/y offsets.
2276 */
2277 static u32 intel_adjust_tile_offset(int *x, int *y,
2278 const struct intel_plane_state *state, int plane,
2279 u32 old_offset, u32 new_offset)
2280 {
2281 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2282 const struct drm_framebuffer *fb = state->base.fb;
2283 unsigned int cpp = fb->format->cpp[plane];
2284 unsigned int rotation = state->base.rotation;
2285 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2286
2287 WARN_ON(new_offset > old_offset);
2288
2289 if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2290 unsigned int tile_size, tile_width, tile_height;
2291 unsigned int pitch_tiles;
2292
2293 tile_size = intel_tile_size(dev_priv);
2294 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2295 fb->modifier, cpp);
2296
2297 if (drm_rotation_90_or_270(rotation)) {
2298 pitch_tiles = pitch / tile_height;
2299 swap(tile_width, tile_height);
2300 } else {
2301 pitch_tiles = pitch / (tile_width * cpp);
2302 }
2303
2304 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2305 tile_size, pitch_tiles,
2306 old_offset, new_offset);
2307 } else {
2308 old_offset += *y * pitch + *x * cpp;
2309
2310 *y = (old_offset - new_offset) / pitch;
2311 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2312 }
2313
2314 return new_offset;
2315 }
2316
2317 /*
2318 * Computes the linear offset to the base tile and adjusts
2319 * x, y. bytes per pixel is assumed to be a power-of-two.
2320 *
2321 * In the 90/270 rotated case, x and y are assumed
2322 * to be already rotated to match the rotated GTT view, and
2323 * pitch is the tile_height aligned framebuffer height.
2324 *
2325 * This function is used when computing the derived information
2326 * under intel_framebuffer, so using any of that information
2327 * here is not allowed. Anything under drm_framebuffer can be
2328 * used. This is why the user has to pass in the pitch since it
2329 * is specified in the rotated orientation.
2330 */
2331 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2332 int *x, int *y,
2333 const struct drm_framebuffer *fb, int plane,
2334 unsigned int pitch,
2335 unsigned int rotation,
2336 u32 alignment)
2337 {
2338 uint64_t fb_modifier = fb->modifier;
2339 unsigned int cpp = fb->format->cpp[plane];
2340 u32 offset, offset_aligned;
2341
2342 if (alignment)
2343 alignment--;
2344
2345 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2346 unsigned int tile_size, tile_width, tile_height;
2347 unsigned int tile_rows, tiles, pitch_tiles;
2348
2349 tile_size = intel_tile_size(dev_priv);
2350 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2351 fb_modifier, cpp);
2352
2353 if (drm_rotation_90_or_270(rotation)) {
2354 pitch_tiles = pitch / tile_height;
2355 swap(tile_width, tile_height);
2356 } else {
2357 pitch_tiles = pitch / (tile_width * cpp);
2358 }
2359
2360 tile_rows = *y / tile_height;
2361 *y %= tile_height;
2362
2363 tiles = *x / tile_width;
2364 *x %= tile_width;
2365
2366 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2367 offset_aligned = offset & ~alignment;
2368
2369 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2370 tile_size, pitch_tiles,
2371 offset, offset_aligned);
2372 } else {
2373 offset = *y * pitch + *x * cpp;
2374 offset_aligned = offset & ~alignment;
2375
2376 *y = (offset & alignment) / pitch;
2377 *x = ((offset & alignment) - *y * pitch) / cpp;
2378 }
2379
2380 return offset_aligned;
2381 }
2382
2383 u32 intel_compute_tile_offset(int *x, int *y,
2384 const struct intel_plane_state *state,
2385 int plane)
2386 {
2387 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2388 const struct drm_framebuffer *fb = state->base.fb;
2389 unsigned int rotation = state->base.rotation;
2390 int pitch = intel_fb_pitch(fb, plane, rotation);
2391 u32 alignment;
2392
2393 /* AUX_DIST needs only 4K alignment */
2394 if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
2395 alignment = 4096;
2396 else
2397 alignment = intel_surf_alignment(dev_priv, fb->modifier);
2398
2399 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2400 rotation, alignment);
2401 }
2402
2403 /* Convert the fb->offset[] linear offset into x/y offsets */
2404 static void intel_fb_offset_to_xy(int *x, int *y,
2405 const struct drm_framebuffer *fb, int plane)
2406 {
2407 unsigned int cpp = fb->format->cpp[plane];
2408 unsigned int pitch = fb->pitches[plane];
2409 u32 linear_offset = fb->offsets[plane];
2410
2411 *y = linear_offset / pitch;
2412 *x = linear_offset % pitch / cpp;
2413 }
2414
2415 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2416 {
2417 switch (fb_modifier) {
2418 case I915_FORMAT_MOD_X_TILED:
2419 return I915_TILING_X;
2420 case I915_FORMAT_MOD_Y_TILED:
2421 return I915_TILING_Y;
2422 default:
2423 return I915_TILING_NONE;
2424 }
2425 }
2426
2427 static int
2428 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2429 struct drm_framebuffer *fb)
2430 {
2431 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2432 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2433 u32 gtt_offset_rotated = 0;
2434 unsigned int max_size = 0;
2435 int i, num_planes = fb->format->num_planes;
2436 unsigned int tile_size = intel_tile_size(dev_priv);
2437
2438 for (i = 0; i < num_planes; i++) {
2439 unsigned int width, height;
2440 unsigned int cpp, size;
2441 u32 offset;
2442 int x, y;
2443
2444 cpp = fb->format->cpp[i];
2445 width = drm_framebuffer_plane_width(fb->width, fb, i);
2446 height = drm_framebuffer_plane_height(fb->height, fb, i);
2447
2448 intel_fb_offset_to_xy(&x, &y, fb, i);
2449
2450 /*
2451 * The fence (if used) is aligned to the start of the object
2452 * so having the framebuffer wrap around across the edge of the
2453 * fenced region doesn't really work. We have no API to configure
2454 * the fence start offset within the object (nor could we probably
2455 * on gen2/3). So it's just easier if we just require that the
2456 * fb layout agrees with the fence layout. We already check that the
2457 * fb stride matches the fence stride elsewhere.
2458 */
2459 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2460 (x + width) * cpp > fb->pitches[i]) {
2461 DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2462 i, fb->offsets[i]);
2463 return -EINVAL;
2464 }
2465
2466 /*
2467 * First pixel of the framebuffer from
2468 * the start of the normal gtt mapping.
2469 */
2470 intel_fb->normal[i].x = x;
2471 intel_fb->normal[i].y = y;
2472
2473 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2474 fb, 0, fb->pitches[i],
2475 DRM_ROTATE_0, tile_size);
2476 offset /= tile_size;
2477
2478 if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2479 unsigned int tile_width, tile_height;
2480 unsigned int pitch_tiles;
2481 struct drm_rect r;
2482
2483 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2484 fb->modifier, cpp);
2485
2486 rot_info->plane[i].offset = offset;
2487 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2488 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2489 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2490
2491 intel_fb->rotated[i].pitch =
2492 rot_info->plane[i].height * tile_height;
2493
2494 /* how many tiles does this plane need */
2495 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2496 /*
2497 * If the plane isn't horizontally tile aligned,
2498 * we need one more tile.
2499 */
2500 if (x != 0)
2501 size++;
2502
2503 /* rotate the x/y offsets to match the GTT view */
2504 r.x1 = x;
2505 r.y1 = y;
2506 r.x2 = x + width;
2507 r.y2 = y + height;
2508 drm_rect_rotate(&r,
2509 rot_info->plane[i].width * tile_width,
2510 rot_info->plane[i].height * tile_height,
2511 DRM_ROTATE_270);
2512 x = r.x1;
2513 y = r.y1;
2514
2515 /* rotate the tile dimensions to match the GTT view */
2516 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2517 swap(tile_width, tile_height);
2518
2519 /*
2520 * We only keep the x/y offsets, so push all of the
2521 * gtt offset into the x/y offsets.
2522 */
2523 _intel_adjust_tile_offset(&x, &y,
2524 tile_width, tile_height,
2525 tile_size, pitch_tiles,
2526 gtt_offset_rotated * tile_size, 0);
2527
2528 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2529
2530 /*
2531 * First pixel of the framebuffer from
2532 * the start of the rotated gtt mapping.
2533 */
2534 intel_fb->rotated[i].x = x;
2535 intel_fb->rotated[i].y = y;
2536 } else {
2537 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2538 x * cpp, tile_size);
2539 }
2540
2541 /* how many tiles in total needed in the bo */
2542 max_size = max(max_size, offset + size);
2543 }
2544
2545 if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2546 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2547 max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2548 return -EINVAL;
2549 }
2550
2551 return 0;
2552 }
2553
2554 static int i9xx_format_to_fourcc(int format)
2555 {
2556 switch (format) {
2557 case DISPPLANE_8BPP:
2558 return DRM_FORMAT_C8;
2559 case DISPPLANE_BGRX555:
2560 return DRM_FORMAT_XRGB1555;
2561 case DISPPLANE_BGRX565:
2562 return DRM_FORMAT_RGB565;
2563 default:
2564 case DISPPLANE_BGRX888:
2565 return DRM_FORMAT_XRGB8888;
2566 case DISPPLANE_RGBX888:
2567 return DRM_FORMAT_XBGR8888;
2568 case DISPPLANE_BGRX101010:
2569 return DRM_FORMAT_XRGB2101010;
2570 case DISPPLANE_RGBX101010:
2571 return DRM_FORMAT_XBGR2101010;
2572 }
2573 }
2574
2575 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2576 {
2577 switch (format) {
2578 case PLANE_CTL_FORMAT_RGB_565:
2579 return DRM_FORMAT_RGB565;
2580 default:
2581 case PLANE_CTL_FORMAT_XRGB_8888:
2582 if (rgb_order) {
2583 if (alpha)
2584 return DRM_FORMAT_ABGR8888;
2585 else
2586 return DRM_FORMAT_XBGR8888;
2587 } else {
2588 if (alpha)
2589 return DRM_FORMAT_ARGB8888;
2590 else
2591 return DRM_FORMAT_XRGB8888;
2592 }
2593 case PLANE_CTL_FORMAT_XRGB_2101010:
2594 if (rgb_order)
2595 return DRM_FORMAT_XBGR2101010;
2596 else
2597 return DRM_FORMAT_XRGB2101010;
2598 }
2599 }
2600
2601 static bool
2602 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2603 struct intel_initial_plane_config *plane_config)
2604 {
2605 struct drm_device *dev = crtc->base.dev;
2606 struct drm_i915_private *dev_priv = to_i915(dev);
2607 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2608 struct drm_i915_gem_object *obj = NULL;
2609 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2610 struct drm_framebuffer *fb = &plane_config->fb->base;
2611 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2612 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2613 PAGE_SIZE);
2614
2615 size_aligned -= base_aligned;
2616
2617 if (plane_config->size == 0)
2618 return false;
2619
2620 /* If the FB is too big, just don't use it since fbdev is not very
2621 * important and we should probably use that space with FBC or other
2622 * features. */
2623 if (size_aligned * 2 > ggtt->stolen_usable_size)
2624 return false;
2625
2626 mutex_lock(&dev->struct_mutex);
2627 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2628 base_aligned,
2629 base_aligned,
2630 size_aligned);
2631 mutex_unlock(&dev->struct_mutex);
2632 if (!obj)
2633 return false;
2634
2635 if (plane_config->tiling == I915_TILING_X)
2636 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2637
2638 mode_cmd.pixel_format = fb->format->format;
2639 mode_cmd.width = fb->width;
2640 mode_cmd.height = fb->height;
2641 mode_cmd.pitches[0] = fb->pitches[0];
2642 mode_cmd.modifier[0] = fb->modifier;
2643 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2644
2645 if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2646 DRM_DEBUG_KMS("intel fb init failed\n");
2647 goto out_unref_obj;
2648 }
2649
2650
2651 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2652 return true;
2653
2654 out_unref_obj:
2655 i915_gem_object_put(obj);
2656 return false;
2657 }
2658
2659 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2660 static void
2661 update_state_fb(struct drm_plane *plane)
2662 {
2663 if (plane->fb == plane->state->fb)
2664 return;
2665
2666 if (plane->state->fb)
2667 drm_framebuffer_unreference(plane->state->fb);
2668 plane->state->fb = plane->fb;
2669 if (plane->state->fb)
2670 drm_framebuffer_reference(plane->state->fb);
2671 }
2672
2673 static void
2674 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2675 struct intel_plane_state *plane_state,
2676 bool visible)
2677 {
2678 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2679
2680 plane_state->base.visible = visible;
2681
2682 /* FIXME pre-g4x don't work like this */
2683 if (visible) {
2684 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2685 crtc_state->active_planes |= BIT(plane->id);
2686 } else {
2687 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2688 crtc_state->active_planes &= ~BIT(plane->id);
2689 }
2690
2691 DRM_DEBUG_KMS("%s active planes 0x%x\n",
2692 crtc_state->base.crtc->name,
2693 crtc_state->active_planes);
2694 }
2695
2696 static void
2697 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2698 struct intel_initial_plane_config *plane_config)
2699 {
2700 struct drm_device *dev = intel_crtc->base.dev;
2701 struct drm_i915_private *dev_priv = to_i915(dev);
2702 struct drm_crtc *c;
2703 struct drm_i915_gem_object *obj;
2704 struct drm_plane *primary = intel_crtc->base.primary;
2705 struct drm_plane_state *plane_state = primary->state;
2706 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2707 struct intel_plane *intel_plane = to_intel_plane(primary);
2708 struct intel_plane_state *intel_state =
2709 to_intel_plane_state(plane_state);
2710 struct drm_framebuffer *fb;
2711
2712 if (!plane_config->fb)
2713 return;
2714
2715 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2716 fb = &plane_config->fb->base;
2717 goto valid_fb;
2718 }
2719
2720 kfree(plane_config->fb);
2721
2722 /*
2723 * Failed to alloc the obj, check to see if we should share
2724 * an fb with another CRTC instead
2725 */
2726 for_each_crtc(dev, c) {
2727 struct intel_plane_state *state;
2728
2729 if (c == &intel_crtc->base)
2730 continue;
2731
2732 if (!to_intel_crtc(c)->active)
2733 continue;
2734
2735 state = to_intel_plane_state(c->primary->state);
2736 if (!state->vma)
2737 continue;
2738
2739 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2740 fb = c->primary->fb;
2741 drm_framebuffer_reference(fb);
2742 goto valid_fb;
2743 }
2744 }
2745
2746 /*
2747 * We've failed to reconstruct the BIOS FB. Current display state
2748 * indicates that the primary plane is visible, but has a NULL FB,
2749 * which will lead to problems later if we don't fix it up. The
2750 * simplest solution is to just disable the primary plane now and
2751 * pretend the BIOS never had it enabled.
2752 */
2753 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2754 to_intel_plane_state(plane_state),
2755 false);
2756 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2757 trace_intel_disable_plane(primary, intel_crtc);
2758 intel_plane->disable_plane(primary, &intel_crtc->base);
2759
2760 return;
2761
2762 valid_fb:
2763 mutex_lock(&dev->struct_mutex);
2764 intel_state->vma =
2765 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2766 mutex_unlock(&dev->struct_mutex);
2767 if (IS_ERR(intel_state->vma)) {
2768 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2769 intel_crtc->pipe, PTR_ERR(intel_state->vma));
2770
2771 intel_state->vma = NULL;
2772 drm_framebuffer_unreference(fb);
2773 return;
2774 }
2775
2776 plane_state->src_x = 0;
2777 plane_state->src_y = 0;
2778 plane_state->src_w = fb->width << 16;
2779 plane_state->src_h = fb->height << 16;
2780
2781 plane_state->crtc_x = 0;
2782 plane_state->crtc_y = 0;
2783 plane_state->crtc_w = fb->width;
2784 plane_state->crtc_h = fb->height;
2785
2786 intel_state->base.src = drm_plane_state_src(plane_state);
2787 intel_state->base.dst = drm_plane_state_dest(plane_state);
2788
2789 obj = intel_fb_obj(fb);
2790 if (i915_gem_object_is_tiled(obj))
2791 dev_priv->preserve_bios_swizzle = true;
2792
2793 drm_framebuffer_reference(fb);
2794 primary->fb = primary->state->fb = fb;
2795 primary->crtc = primary->state->crtc = &intel_crtc->base;
2796
2797 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2798 to_intel_plane_state(plane_state),
2799 true);
2800
2801 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2802 &obj->frontbuffer_bits);
2803 }
2804
2805 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2806 unsigned int rotation)
2807 {
2808 int cpp = fb->format->cpp[plane];
2809
2810 switch (fb->modifier) {
2811 case DRM_FORMAT_MOD_NONE:
2812 case I915_FORMAT_MOD_X_TILED:
2813 switch (cpp) {
2814 case 8:
2815 return 4096;
2816 case 4:
2817 case 2:
2818 case 1:
2819 return 8192;
2820 default:
2821 MISSING_CASE(cpp);
2822 break;
2823 }
2824 break;
2825 case I915_FORMAT_MOD_Y_TILED:
2826 case I915_FORMAT_MOD_Yf_TILED:
2827 switch (cpp) {
2828 case 8:
2829 return 2048;
2830 case 4:
2831 return 4096;
2832 case 2:
2833 case 1:
2834 return 8192;
2835 default:
2836 MISSING_CASE(cpp);
2837 break;
2838 }
2839 break;
2840 default:
2841 MISSING_CASE(fb->modifier);
2842 }
2843
2844 return 2048;
2845 }
2846
2847 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2848 {
2849 const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2850 const struct drm_framebuffer *fb = plane_state->base.fb;
2851 unsigned int rotation = plane_state->base.rotation;
2852 int x = plane_state->base.src.x1 >> 16;
2853 int y = plane_state->base.src.y1 >> 16;
2854 int w = drm_rect_width(&plane_state->base.src) >> 16;
2855 int h = drm_rect_height(&plane_state->base.src) >> 16;
2856 int max_width = skl_max_plane_width(fb, 0, rotation);
2857 int max_height = 4096;
2858 u32 alignment, offset, aux_offset = plane_state->aux.offset;
2859
2860 if (w > max_width || h > max_height) {
2861 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2862 w, h, max_width, max_height);
2863 return -EINVAL;
2864 }
2865
2866 intel_add_fb_offsets(&x, &y, plane_state, 0);
2867 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2868
2869 alignment = intel_surf_alignment(dev_priv, fb->modifier);
2870
2871 /*
2872 * AUX surface offset is specified as the distance from the
2873 * main surface offset, and it must be non-negative. Make
2874 * sure that is what we will get.
2875 */
2876 if (offset > aux_offset)
2877 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2878 offset, aux_offset & ~(alignment - 1));
2879
2880 /*
2881 * When using an X-tiled surface, the plane blows up
2882 * if the x offset + width exceed the stride.
2883 *
2884 * TODO: linear and Y-tiled seem fine, Yf untested,
2885 */
2886 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2887 int cpp = fb->format->cpp[0];
2888
2889 while ((x + w) * cpp > fb->pitches[0]) {
2890 if (offset == 0) {
2891 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2892 return -EINVAL;
2893 }
2894
2895 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2896 offset, offset - alignment);
2897 }
2898 }
2899
2900 plane_state->main.offset = offset;
2901 plane_state->main.x = x;
2902 plane_state->main.y = y;
2903
2904 return 0;
2905 }
2906
2907 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2908 {
2909 const struct drm_framebuffer *fb = plane_state->base.fb;
2910 unsigned int rotation = plane_state->base.rotation;
2911 int max_width = skl_max_plane_width(fb, 1, rotation);
2912 int max_height = 4096;
2913 int x = plane_state->base.src.x1 >> 17;
2914 int y = plane_state->base.src.y1 >> 17;
2915 int w = drm_rect_width(&plane_state->base.src) >> 17;
2916 int h = drm_rect_height(&plane_state->base.src) >> 17;
2917 u32 offset;
2918
2919 intel_add_fb_offsets(&x, &y, plane_state, 1);
2920 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2921
2922 /* FIXME not quite sure how/if these apply to the chroma plane */
2923 if (w > max_width || h > max_height) {
2924 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2925 w, h, max_width, max_height);
2926 return -EINVAL;
2927 }
2928
2929 plane_state->aux.offset = offset;
2930 plane_state->aux.x = x;
2931 plane_state->aux.y = y;
2932
2933 return 0;
2934 }
2935
2936 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2937 {
2938 const struct drm_framebuffer *fb = plane_state->base.fb;
2939 unsigned int rotation = plane_state->base.rotation;
2940 int ret;
2941
2942 if (!plane_state->base.visible)
2943 return 0;
2944
2945 /* Rotate src coordinates to match rotated GTT view */
2946 if (drm_rotation_90_or_270(rotation))
2947 drm_rect_rotate(&plane_state->base.src,
2948 fb->width << 16, fb->height << 16,
2949 DRM_ROTATE_270);
2950
2951 /*
2952 * Handle the AUX surface first since
2953 * the main surface setup depends on it.
2954 */
2955 if (fb->format->format == DRM_FORMAT_NV12) {
2956 ret = skl_check_nv12_aux_surface(plane_state);
2957 if (ret)
2958 return ret;
2959 } else {
2960 plane_state->aux.offset = ~0xfff;
2961 plane_state->aux.x = 0;
2962 plane_state->aux.y = 0;
2963 }
2964
2965 ret = skl_check_main_surface(plane_state);
2966 if (ret)
2967 return ret;
2968
2969 return 0;
2970 }
2971
2972 static void i9xx_update_primary_plane(struct drm_plane *primary,
2973 const struct intel_crtc_state *crtc_state,
2974 const struct intel_plane_state *plane_state)
2975 {
2976 struct drm_i915_private *dev_priv = to_i915(primary->dev);
2977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2978 struct drm_framebuffer *fb = plane_state->base.fb;
2979 int plane = intel_crtc->plane;
2980 u32 linear_offset;
2981 u32 dspcntr;
2982 i915_reg_t reg = DSPCNTR(plane);
2983 unsigned int rotation = plane_state->base.rotation;
2984 int x = plane_state->base.src.x1 >> 16;
2985 int y = plane_state->base.src.y1 >> 16;
2986
2987 dspcntr = DISPPLANE_GAMMA_ENABLE;
2988
2989 dspcntr |= DISPLAY_PLANE_ENABLE;
2990
2991 if (INTEL_GEN(dev_priv) < 4) {
2992 if (intel_crtc->pipe == PIPE_B)
2993 dspcntr |= DISPPLANE_SEL_PIPE_B;
2994
2995 /* pipesrc and dspsize control the size that is scaled from,
2996 * which should always be the user's requested size.
2997 */
2998 I915_WRITE(DSPSIZE(plane),
2999 ((crtc_state->pipe_src_h - 1) << 16) |
3000 (crtc_state->pipe_src_w - 1));
3001 I915_WRITE(DSPPOS(plane), 0);
3002 } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3003 I915_WRITE(PRIMSIZE(plane),
3004 ((crtc_state->pipe_src_h - 1) << 16) |
3005 (crtc_state->pipe_src_w - 1));
3006 I915_WRITE(PRIMPOS(plane), 0);
3007 I915_WRITE(PRIMCNSTALPHA(plane), 0);
3008 }
3009
3010 switch (fb->format->format) {
3011 case DRM_FORMAT_C8:
3012 dspcntr |= DISPPLANE_8BPP;
3013 break;
3014 case DRM_FORMAT_XRGB1555:
3015 dspcntr |= DISPPLANE_BGRX555;
3016 break;
3017 case DRM_FORMAT_RGB565:
3018 dspcntr |= DISPPLANE_BGRX565;
3019 break;
3020 case DRM_FORMAT_XRGB8888:
3021 dspcntr |= DISPPLANE_BGRX888;
3022 break;
3023 case DRM_FORMAT_XBGR8888:
3024 dspcntr |= DISPPLANE_RGBX888;
3025 break;
3026 case DRM_FORMAT_XRGB2101010:
3027 dspcntr |= DISPPLANE_BGRX101010;
3028 break;
3029 case DRM_FORMAT_XBGR2101010:
3030 dspcntr |= DISPPLANE_RGBX101010;
3031 break;
3032 default:
3033 BUG();
3034 }
3035
3036 if (INTEL_GEN(dev_priv) >= 4 &&
3037 fb->modifier == I915_FORMAT_MOD_X_TILED)
3038 dspcntr |= DISPPLANE_TILED;
3039
3040 if (rotation & DRM_ROTATE_180)
3041 dspcntr |= DISPPLANE_ROTATE_180;
3042
3043 if (rotation & DRM_REFLECT_X)
3044 dspcntr |= DISPPLANE_MIRROR;
3045
3046 if (IS_G4X(dev_priv))
3047 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3048
3049 intel_add_fb_offsets(&x, &y, plane_state, 0);
3050
3051 if (INTEL_GEN(dev_priv) >= 4)
3052 intel_crtc->dspaddr_offset =
3053 intel_compute_tile_offset(&x, &y, plane_state, 0);
3054
3055 if (rotation & DRM_ROTATE_180) {
3056 x += crtc_state->pipe_src_w - 1;
3057 y += crtc_state->pipe_src_h - 1;
3058 } else if (rotation & DRM_REFLECT_X) {
3059 x += crtc_state->pipe_src_w - 1;
3060 }
3061
3062 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3063
3064 if (INTEL_GEN(dev_priv) < 4)
3065 intel_crtc->dspaddr_offset = linear_offset;
3066
3067 intel_crtc->adjusted_x = x;
3068 intel_crtc->adjusted_y = y;
3069
3070 I915_WRITE(reg, dspcntr);
3071
3072 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3073 if (INTEL_GEN(dev_priv) >= 4) {
3074 I915_WRITE(DSPSURF(plane),
3075 intel_plane_ggtt_offset(plane_state) +
3076 intel_crtc->dspaddr_offset);
3077 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3078 I915_WRITE(DSPLINOFF(plane), linear_offset);
3079 } else {
3080 I915_WRITE(DSPADDR(plane),
3081 intel_plane_ggtt_offset(plane_state) +
3082 intel_crtc->dspaddr_offset);
3083 }
3084 POSTING_READ(reg);
3085 }
3086
3087 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3088 struct drm_crtc *crtc)
3089 {
3090 struct drm_device *dev = crtc->dev;
3091 struct drm_i915_private *dev_priv = to_i915(dev);
3092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3093 int plane = intel_crtc->plane;
3094
3095 I915_WRITE(DSPCNTR(plane), 0);
3096 if (INTEL_INFO(dev_priv)->gen >= 4)
3097 I915_WRITE(DSPSURF(plane), 0);
3098 else
3099 I915_WRITE(DSPADDR(plane), 0);
3100 POSTING_READ(DSPCNTR(plane));
3101 }
3102
3103 static void ironlake_update_primary_plane(struct drm_plane *primary,
3104 const struct intel_crtc_state *crtc_state,
3105 const struct intel_plane_state *plane_state)
3106 {
3107 struct drm_device *dev = primary->dev;
3108 struct drm_i915_private *dev_priv = to_i915(dev);
3109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3110 struct drm_framebuffer *fb = plane_state->base.fb;
3111 int plane = intel_crtc->plane;
3112 u32 linear_offset;
3113 u32 dspcntr;
3114 i915_reg_t reg = DSPCNTR(plane);
3115 unsigned int rotation = plane_state->base.rotation;
3116 int x = plane_state->base.src.x1 >> 16;
3117 int y = plane_state->base.src.y1 >> 16;
3118
3119 dspcntr = DISPPLANE_GAMMA_ENABLE;
3120 dspcntr |= DISPLAY_PLANE_ENABLE;
3121
3122 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3123 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3124
3125 switch (fb->format->format) {
3126 case DRM_FORMAT_C8:
3127 dspcntr |= DISPPLANE_8BPP;
3128 break;
3129 case DRM_FORMAT_RGB565:
3130 dspcntr |= DISPPLANE_BGRX565;
3131 break;
3132 case DRM_FORMAT_XRGB8888:
3133 dspcntr |= DISPPLANE_BGRX888;
3134 break;
3135 case DRM_FORMAT_XBGR8888:
3136 dspcntr |= DISPPLANE_RGBX888;
3137 break;
3138 case DRM_FORMAT_XRGB2101010:
3139 dspcntr |= DISPPLANE_BGRX101010;
3140 break;
3141 case DRM_FORMAT_XBGR2101010:
3142 dspcntr |= DISPPLANE_RGBX101010;
3143 break;
3144 default:
3145 BUG();
3146 }
3147
3148 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
3149 dspcntr |= DISPPLANE_TILED;
3150
3151 if (rotation & DRM_ROTATE_180)
3152 dspcntr |= DISPPLANE_ROTATE_180;
3153
3154 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv))
3155 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3156
3157 intel_add_fb_offsets(&x, &y, plane_state, 0);
3158
3159 intel_crtc->dspaddr_offset =
3160 intel_compute_tile_offset(&x, &y, plane_state, 0);
3161
3162 /* HSW+ does this automagically in hardware */
3163 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) &&
3164 rotation & DRM_ROTATE_180) {
3165 x += crtc_state->pipe_src_w - 1;
3166 y += crtc_state->pipe_src_h - 1;
3167 }
3168
3169 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3170
3171 intel_crtc->adjusted_x = x;
3172 intel_crtc->adjusted_y = y;
3173
3174 I915_WRITE(reg, dspcntr);
3175
3176 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3177 I915_WRITE(DSPSURF(plane),
3178 intel_plane_ggtt_offset(plane_state) +
3179 intel_crtc->dspaddr_offset);
3180 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3181 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3182 } else {
3183 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3184 I915_WRITE(DSPLINOFF(plane), linear_offset);
3185 }
3186 POSTING_READ(reg);
3187 }
3188
3189 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3190 uint64_t fb_modifier, uint32_t pixel_format)
3191 {
3192 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3193 return 64;
3194 } else {
3195 int cpp = drm_format_plane_cpp(pixel_format, 0);
3196
3197 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3198 }
3199 }
3200
3201 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3202 {
3203 struct drm_device *dev = intel_crtc->base.dev;
3204 struct drm_i915_private *dev_priv = to_i915(dev);
3205
3206 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3207 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3208 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3209 }
3210
3211 /*
3212 * This function detaches (aka. unbinds) unused scalers in hardware
3213 */
3214 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3215 {
3216 struct intel_crtc_scaler_state *scaler_state;
3217 int i;
3218
3219 scaler_state = &intel_crtc->config->scaler_state;
3220
3221 /* loop through and disable scalers that aren't in use */
3222 for (i = 0; i < intel_crtc->num_scalers; i++) {
3223 if (!scaler_state->scalers[i].in_use)
3224 skl_detach_scaler(intel_crtc, i);
3225 }
3226 }
3227
3228 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3229 unsigned int rotation)
3230 {
3231 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3232 u32 stride = intel_fb_pitch(fb, plane, rotation);
3233
3234 /*
3235 * The stride is either expressed as a multiple of 64 bytes chunks for
3236 * linear buffers or in number of tiles for tiled buffers.
3237 */
3238 if (drm_rotation_90_or_270(rotation)) {
3239 int cpp = fb->format->cpp[plane];
3240
3241 stride /= intel_tile_height(dev_priv, fb->modifier, cpp);
3242 } else {
3243 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier,
3244 fb->format->format);
3245 }
3246
3247 return stride;
3248 }
3249
3250 u32 skl_plane_ctl_format(uint32_t pixel_format)
3251 {
3252 switch (pixel_format) {
3253 case DRM_FORMAT_C8:
3254 return PLANE_CTL_FORMAT_INDEXED;
3255 case DRM_FORMAT_RGB565:
3256 return PLANE_CTL_FORMAT_RGB_565;
3257 case DRM_FORMAT_XBGR8888:
3258 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3259 case DRM_FORMAT_XRGB8888:
3260 return PLANE_CTL_FORMAT_XRGB_8888;
3261 /*
3262 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3263 * to be already pre-multiplied. We need to add a knob (or a different
3264 * DRM_FORMAT) for user-space to configure that.
3265 */
3266 case DRM_FORMAT_ABGR8888:
3267 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3268 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3269 case DRM_FORMAT_ARGB8888:
3270 return PLANE_CTL_FORMAT_XRGB_8888 |
3271 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3272 case DRM_FORMAT_XRGB2101010:
3273 return PLANE_CTL_FORMAT_XRGB_2101010;
3274 case DRM_FORMAT_XBGR2101010:
3275 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3276 case DRM_FORMAT_YUYV:
3277 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3278 case DRM_FORMAT_YVYU:
3279 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3280 case DRM_FORMAT_UYVY:
3281 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3282 case DRM_FORMAT_VYUY:
3283 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3284 default:
3285 MISSING_CASE(pixel_format);
3286 }
3287
3288 return 0;
3289 }
3290
3291 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3292 {
3293 switch (fb_modifier) {
3294 case DRM_FORMAT_MOD_NONE:
3295 break;
3296 case I915_FORMAT_MOD_X_TILED:
3297 return PLANE_CTL_TILED_X;
3298 case I915_FORMAT_MOD_Y_TILED:
3299 return PLANE_CTL_TILED_Y;
3300 case I915_FORMAT_MOD_Yf_TILED:
3301 return PLANE_CTL_TILED_YF;
3302 default:
3303 MISSING_CASE(fb_modifier);
3304 }
3305
3306 return 0;
3307 }
3308
3309 u32 skl_plane_ctl_rotation(unsigned int rotation)
3310 {
3311 switch (rotation) {
3312 case DRM_ROTATE_0:
3313 break;
3314 /*
3315 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3316 * while i915 HW rotation is clockwise, thats why this swapping.
3317 */
3318 case DRM_ROTATE_90:
3319 return PLANE_CTL_ROTATE_270;
3320 case DRM_ROTATE_180:
3321 return PLANE_CTL_ROTATE_180;
3322 case DRM_ROTATE_270:
3323 return PLANE_CTL_ROTATE_90;
3324 default:
3325 MISSING_CASE(rotation);
3326 }
3327
3328 return 0;
3329 }
3330
3331 static void skylake_update_primary_plane(struct drm_plane *plane,
3332 const struct intel_crtc_state *crtc_state,
3333 const struct intel_plane_state *plane_state)
3334 {
3335 struct drm_device *dev = plane->dev;
3336 struct drm_i915_private *dev_priv = to_i915(dev);
3337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3338 struct drm_framebuffer *fb = plane_state->base.fb;
3339 enum plane_id plane_id = to_intel_plane(plane)->id;
3340 enum pipe pipe = to_intel_plane(plane)->pipe;
3341 u32 plane_ctl;
3342 unsigned int rotation = plane_state->base.rotation;
3343 u32 stride = skl_plane_stride(fb, 0, rotation);
3344 u32 surf_addr = plane_state->main.offset;
3345 int scaler_id = plane_state->scaler_id;
3346 int src_x = plane_state->main.x;
3347 int src_y = plane_state->main.y;
3348 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3349 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3350 int dst_x = plane_state->base.dst.x1;
3351 int dst_y = plane_state->base.dst.y1;
3352 int dst_w = drm_rect_width(&plane_state->base.dst);
3353 int dst_h = drm_rect_height(&plane_state->base.dst);
3354
3355 plane_ctl = PLANE_CTL_ENABLE;
3356
3357 if (IS_GEMINILAKE(dev_priv)) {
3358 I915_WRITE(PLANE_COLOR_CTL(pipe, plane_id),
3359 PLANE_COLOR_PIPE_GAMMA_ENABLE |
3360 PLANE_COLOR_PIPE_CSC_ENABLE |
3361 PLANE_COLOR_PLANE_GAMMA_DISABLE);
3362 } else {
3363 plane_ctl |=
3364 PLANE_CTL_PIPE_GAMMA_ENABLE |
3365 PLANE_CTL_PIPE_CSC_ENABLE |
3366 PLANE_CTL_PLANE_GAMMA_DISABLE;
3367 }
3368
3369 plane_ctl |= skl_plane_ctl_format(fb->format->format);
3370 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3371 plane_ctl |= skl_plane_ctl_rotation(rotation);
3372
3373 /* Sizes are 0 based */
3374 src_w--;
3375 src_h--;
3376 dst_w--;
3377 dst_h--;
3378
3379 intel_crtc->dspaddr_offset = surf_addr;
3380
3381 intel_crtc->adjusted_x = src_x;
3382 intel_crtc->adjusted_y = src_y;
3383
3384 I915_WRITE(PLANE_CTL(pipe, plane_id), plane_ctl);
3385 I915_WRITE(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3386 I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride);
3387 I915_WRITE(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3388
3389 if (scaler_id >= 0) {
3390 uint32_t ps_ctrl = 0;
3391
3392 WARN_ON(!dst_w || !dst_h);
3393 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3394 crtc_state->scaler_state.scalers[scaler_id].mode;
3395 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3396 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3397 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3398 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3399 I915_WRITE(PLANE_POS(pipe, plane_id), 0);
3400 } else {
3401 I915_WRITE(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3402 }
3403
3404 I915_WRITE(PLANE_SURF(pipe, plane_id),
3405 intel_plane_ggtt_offset(plane_state) + surf_addr);
3406
3407 POSTING_READ(PLANE_SURF(pipe, plane_id));
3408 }
3409
3410 static void skylake_disable_primary_plane(struct drm_plane *primary,
3411 struct drm_crtc *crtc)
3412 {
3413 struct drm_device *dev = crtc->dev;
3414 struct drm_i915_private *dev_priv = to_i915(dev);
3415 enum plane_id plane_id = to_intel_plane(primary)->id;
3416 enum pipe pipe = to_intel_plane(primary)->pipe;
3417
3418 I915_WRITE(PLANE_CTL(pipe, plane_id), 0);
3419 I915_WRITE(PLANE_SURF(pipe, plane_id), 0);
3420 POSTING_READ(PLANE_SURF(pipe, plane_id));
3421 }
3422
3423 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3424 static int
3425 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3426 int x, int y, enum mode_set_atomic state)
3427 {
3428 /* Support for kgdboc is disabled, this needs a major rework. */
3429 DRM_ERROR("legacy panic handler not supported any more.\n");
3430
3431 return -ENODEV;
3432 }
3433
3434 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3435 {
3436 struct intel_crtc *crtc;
3437
3438 for_each_intel_crtc(&dev_priv->drm, crtc)
3439 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3440 }
3441
3442 static void intel_update_primary_planes(struct drm_device *dev)
3443 {
3444 struct drm_crtc *crtc;
3445
3446 for_each_crtc(dev, crtc) {
3447 struct intel_plane *plane = to_intel_plane(crtc->primary);
3448 struct intel_plane_state *plane_state =
3449 to_intel_plane_state(plane->base.state);
3450
3451 if (plane_state->base.visible) {
3452 trace_intel_update_plane(&plane->base,
3453 to_intel_crtc(crtc));
3454
3455 plane->update_plane(&plane->base,
3456 to_intel_crtc_state(crtc->state),
3457 plane_state);
3458 }
3459 }
3460 }
3461
3462 static int
3463 __intel_display_resume(struct drm_device *dev,
3464 struct drm_atomic_state *state,
3465 struct drm_modeset_acquire_ctx *ctx)
3466 {
3467 struct drm_crtc_state *crtc_state;
3468 struct drm_crtc *crtc;
3469 int i, ret;
3470
3471 intel_modeset_setup_hw_state(dev);
3472 i915_redisable_vga(to_i915(dev));
3473
3474 if (!state)
3475 return 0;
3476
3477 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3478 /*
3479 * Force recalculation even if we restore
3480 * current state. With fast modeset this may not result
3481 * in a modeset when the state is compatible.
3482 */
3483 crtc_state->mode_changed = true;
3484 }
3485
3486 /* ignore any reset values/BIOS leftovers in the WM registers */
3487 if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3488 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3489
3490 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3491
3492 WARN_ON(ret == -EDEADLK);
3493 return ret;
3494 }
3495
3496 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3497 {
3498 return intel_has_gpu_reset(dev_priv) &&
3499 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3500 }
3501
3502 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3503 {
3504 struct drm_device *dev = &dev_priv->drm;
3505 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3506 struct drm_atomic_state *state;
3507 int ret;
3508
3509 /*
3510 * Need mode_config.mutex so that we don't
3511 * trample ongoing ->detect() and whatnot.
3512 */
3513 mutex_lock(&dev->mode_config.mutex);
3514 drm_modeset_acquire_init(ctx, 0);
3515 while (1) {
3516 ret = drm_modeset_lock_all_ctx(dev, ctx);
3517 if (ret != -EDEADLK)
3518 break;
3519
3520 drm_modeset_backoff(ctx);
3521 }
3522
3523 /* reset doesn't touch the display, but flips might get nuked anyway, */
3524 if (!i915.force_reset_modeset_test &&
3525 !gpu_reset_clobbers_display(dev_priv))
3526 return;
3527
3528 /*
3529 * Disabling the crtcs gracefully seems nicer. Also the
3530 * g33 docs say we should at least disable all the planes.
3531 */
3532 state = drm_atomic_helper_duplicate_state(dev, ctx);
3533 if (IS_ERR(state)) {
3534 ret = PTR_ERR(state);
3535 DRM_ERROR("Duplicating state failed with %i\n", ret);
3536 return;
3537 }
3538
3539 ret = drm_atomic_helper_disable_all(dev, ctx);
3540 if (ret) {
3541 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3542 drm_atomic_state_put(state);
3543 return;
3544 }
3545
3546 dev_priv->modeset_restore_state = state;
3547 state->acquire_ctx = ctx;
3548 }
3549
3550 void intel_finish_reset(struct drm_i915_private *dev_priv)
3551 {
3552 struct drm_device *dev = &dev_priv->drm;
3553 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3554 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3555 int ret;
3556
3557 /*
3558 * Flips in the rings will be nuked by the reset,
3559 * so complete all pending flips so that user space
3560 * will get its events and not get stuck.
3561 */
3562 intel_complete_page_flips(dev_priv);
3563
3564 dev_priv->modeset_restore_state = NULL;
3565
3566 /* reset doesn't touch the display */
3567 if (!gpu_reset_clobbers_display(dev_priv)) {
3568 if (!state) {
3569 /*
3570 * Flips in the rings have been nuked by the reset,
3571 * so update the base address of all primary
3572 * planes to the the last fb to make sure we're
3573 * showing the correct fb after a reset.
3574 *
3575 * FIXME: Atomic will make this obsolete since we won't schedule
3576 * CS-based flips (which might get lost in gpu resets) any more.
3577 */
3578 intel_update_primary_planes(dev);
3579 } else {
3580 ret = __intel_display_resume(dev, state, ctx);
3581 if (ret)
3582 DRM_ERROR("Restoring old state failed with %i\n", ret);
3583 }
3584 } else {
3585 /*
3586 * The display has been reset as well,
3587 * so need a full re-initialization.
3588 */
3589 intel_runtime_pm_disable_interrupts(dev_priv);
3590 intel_runtime_pm_enable_interrupts(dev_priv);
3591
3592 intel_pps_unlock_regs_wa(dev_priv);
3593 intel_modeset_init_hw(dev);
3594
3595 spin_lock_irq(&dev_priv->irq_lock);
3596 if (dev_priv->display.hpd_irq_setup)
3597 dev_priv->display.hpd_irq_setup(dev_priv);
3598 spin_unlock_irq(&dev_priv->irq_lock);
3599
3600 ret = __intel_display_resume(dev, state, ctx);
3601 if (ret)
3602 DRM_ERROR("Restoring old state failed with %i\n", ret);
3603
3604 intel_hpd_init(dev_priv);
3605 }
3606
3607 if (state)
3608 drm_atomic_state_put(state);
3609 drm_modeset_drop_locks(ctx);
3610 drm_modeset_acquire_fini(ctx);
3611 mutex_unlock(&dev->mode_config.mutex);
3612 }
3613
3614 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3615 {
3616 struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3617
3618 if (i915_reset_in_progress(error))
3619 return true;
3620
3621 if (crtc->reset_count != i915_reset_count(error))
3622 return true;
3623
3624 return false;
3625 }
3626
3627 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3628 {
3629 struct drm_device *dev = crtc->dev;
3630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3631 bool pending;
3632
3633 if (abort_flip_on_reset(intel_crtc))
3634 return false;
3635
3636 spin_lock_irq(&dev->event_lock);
3637 pending = to_intel_crtc(crtc)->flip_work != NULL;
3638 spin_unlock_irq(&dev->event_lock);
3639
3640 return pending;
3641 }
3642
3643 static void intel_update_pipe_config(struct intel_crtc *crtc,
3644 struct intel_crtc_state *old_crtc_state)
3645 {
3646 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3647 struct intel_crtc_state *pipe_config =
3648 to_intel_crtc_state(crtc->base.state);
3649
3650 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3651 crtc->base.mode = crtc->base.state->mode;
3652
3653 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3654 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3655 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3656
3657 /*
3658 * Update pipe size and adjust fitter if needed: the reason for this is
3659 * that in compute_mode_changes we check the native mode (not the pfit
3660 * mode) to see if we can flip rather than do a full mode set. In the
3661 * fastboot case, we'll flip, but if we don't update the pipesrc and
3662 * pfit state, we'll end up with a big fb scanned out into the wrong
3663 * sized surface.
3664 */
3665
3666 I915_WRITE(PIPESRC(crtc->pipe),
3667 ((pipe_config->pipe_src_w - 1) << 16) |
3668 (pipe_config->pipe_src_h - 1));
3669
3670 /* on skylake this is done by detaching scalers */
3671 if (INTEL_GEN(dev_priv) >= 9) {
3672 skl_detach_scalers(crtc);
3673
3674 if (pipe_config->pch_pfit.enabled)
3675 skylake_pfit_enable(crtc);
3676 } else if (HAS_PCH_SPLIT(dev_priv)) {
3677 if (pipe_config->pch_pfit.enabled)
3678 ironlake_pfit_enable(crtc);
3679 else if (old_crtc_state->pch_pfit.enabled)
3680 ironlake_pfit_disable(crtc, true);
3681 }
3682 }
3683
3684 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3685 {
3686 struct drm_device *dev = crtc->base.dev;
3687 struct drm_i915_private *dev_priv = to_i915(dev);
3688 int pipe = crtc->pipe;
3689 i915_reg_t reg;
3690 u32 temp;
3691
3692 /* enable normal train */
3693 reg = FDI_TX_CTL(pipe);
3694 temp = I915_READ(reg);
3695 if (IS_IVYBRIDGE(dev_priv)) {
3696 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3697 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3698 } else {
3699 temp &= ~FDI_LINK_TRAIN_NONE;
3700 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3701 }
3702 I915_WRITE(reg, temp);
3703
3704 reg = FDI_RX_CTL(pipe);
3705 temp = I915_READ(reg);
3706 if (HAS_PCH_CPT(dev_priv)) {
3707 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3708 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3709 } else {
3710 temp &= ~FDI_LINK_TRAIN_NONE;
3711 temp |= FDI_LINK_TRAIN_NONE;
3712 }
3713 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3714
3715 /* wait one idle pattern time */
3716 POSTING_READ(reg);
3717 udelay(1000);
3718
3719 /* IVB wants error correction enabled */
3720 if (IS_IVYBRIDGE(dev_priv))
3721 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3722 FDI_FE_ERRC_ENABLE);
3723 }
3724
3725 /* The FDI link training functions for ILK/Ibexpeak. */
3726 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3727 const struct intel_crtc_state *crtc_state)
3728 {
3729 struct drm_device *dev = crtc->base.dev;
3730 struct drm_i915_private *dev_priv = to_i915(dev);
3731 int pipe = crtc->pipe;
3732 i915_reg_t reg;
3733 u32 temp, tries;
3734
3735 /* FDI needs bits from pipe first */
3736 assert_pipe_enabled(dev_priv, pipe);
3737
3738 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3739 for train result */
3740 reg = FDI_RX_IMR(pipe);
3741 temp = I915_READ(reg);
3742 temp &= ~FDI_RX_SYMBOL_LOCK;
3743 temp &= ~FDI_RX_BIT_LOCK;
3744 I915_WRITE(reg, temp);
3745 I915_READ(reg);
3746 udelay(150);
3747
3748 /* enable CPU FDI TX and PCH FDI RX */
3749 reg = FDI_TX_CTL(pipe);
3750 temp = I915_READ(reg);
3751 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3752 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3753 temp &= ~FDI_LINK_TRAIN_NONE;
3754 temp |= FDI_LINK_TRAIN_PATTERN_1;
3755 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3756
3757 reg = FDI_RX_CTL(pipe);
3758 temp = I915_READ(reg);
3759 temp &= ~FDI_LINK_TRAIN_NONE;
3760 temp |= FDI_LINK_TRAIN_PATTERN_1;
3761 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3762
3763 POSTING_READ(reg);
3764 udelay(150);
3765
3766 /* Ironlake workaround, enable clock pointer after FDI enable*/
3767 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3768 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3769 FDI_RX_PHASE_SYNC_POINTER_EN);
3770
3771 reg = FDI_RX_IIR(pipe);
3772 for (tries = 0; tries < 5; tries++) {
3773 temp = I915_READ(reg);
3774 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3775
3776 if ((temp & FDI_RX_BIT_LOCK)) {
3777 DRM_DEBUG_KMS("FDI train 1 done.\n");
3778 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3779 break;
3780 }
3781 }
3782 if (tries == 5)
3783 DRM_ERROR("FDI train 1 fail!\n");
3784
3785 /* Train 2 */
3786 reg = FDI_TX_CTL(pipe);
3787 temp = I915_READ(reg);
3788 temp &= ~FDI_LINK_TRAIN_NONE;
3789 temp |= FDI_LINK_TRAIN_PATTERN_2;
3790 I915_WRITE(reg, temp);
3791
3792 reg = FDI_RX_CTL(pipe);
3793 temp = I915_READ(reg);
3794 temp &= ~FDI_LINK_TRAIN_NONE;
3795 temp |= FDI_LINK_TRAIN_PATTERN_2;
3796 I915_WRITE(reg, temp);
3797
3798 POSTING_READ(reg);
3799 udelay(150);
3800
3801 reg = FDI_RX_IIR(pipe);
3802 for (tries = 0; tries < 5; tries++) {
3803 temp = I915_READ(reg);
3804 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3805
3806 if (temp & FDI_RX_SYMBOL_LOCK) {
3807 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3808 DRM_DEBUG_KMS("FDI train 2 done.\n");
3809 break;
3810 }
3811 }
3812 if (tries == 5)
3813 DRM_ERROR("FDI train 2 fail!\n");
3814
3815 DRM_DEBUG_KMS("FDI train done\n");
3816
3817 }
3818
3819 static const int snb_b_fdi_train_param[] = {
3820 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3821 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3822 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3823 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3824 };
3825
3826 /* The FDI link training functions for SNB/Cougarpoint. */
3827 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3828 const struct intel_crtc_state *crtc_state)
3829 {
3830 struct drm_device *dev = crtc->base.dev;
3831 struct drm_i915_private *dev_priv = to_i915(dev);
3832 int pipe = crtc->pipe;
3833 i915_reg_t reg;
3834 u32 temp, i, retry;
3835
3836 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3837 for train result */
3838 reg = FDI_RX_IMR(pipe);
3839 temp = I915_READ(reg);
3840 temp &= ~FDI_RX_SYMBOL_LOCK;
3841 temp &= ~FDI_RX_BIT_LOCK;
3842 I915_WRITE(reg, temp);
3843
3844 POSTING_READ(reg);
3845 udelay(150);
3846
3847 /* enable CPU FDI TX and PCH FDI RX */
3848 reg = FDI_TX_CTL(pipe);
3849 temp = I915_READ(reg);
3850 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3851 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3852 temp &= ~FDI_LINK_TRAIN_NONE;
3853 temp |= FDI_LINK_TRAIN_PATTERN_1;
3854 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3855 /* SNB-B */
3856 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3857 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3858
3859 I915_WRITE(FDI_RX_MISC(pipe),
3860 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3861
3862 reg = FDI_RX_CTL(pipe);
3863 temp = I915_READ(reg);
3864 if (HAS_PCH_CPT(dev_priv)) {
3865 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3866 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3867 } else {
3868 temp &= ~FDI_LINK_TRAIN_NONE;
3869 temp |= FDI_LINK_TRAIN_PATTERN_1;
3870 }
3871 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3872
3873 POSTING_READ(reg);
3874 udelay(150);
3875
3876 for (i = 0; i < 4; i++) {
3877 reg = FDI_TX_CTL(pipe);
3878 temp = I915_READ(reg);
3879 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3880 temp |= snb_b_fdi_train_param[i];
3881 I915_WRITE(reg, temp);
3882
3883 POSTING_READ(reg);
3884 udelay(500);
3885
3886 for (retry = 0; retry < 5; retry++) {
3887 reg = FDI_RX_IIR(pipe);
3888 temp = I915_READ(reg);
3889 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3890 if (temp & FDI_RX_BIT_LOCK) {
3891 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3892 DRM_DEBUG_KMS("FDI train 1 done.\n");
3893 break;
3894 }
3895 udelay(50);
3896 }
3897 if (retry < 5)
3898 break;
3899 }
3900 if (i == 4)
3901 DRM_ERROR("FDI train 1 fail!\n");
3902
3903 /* Train 2 */
3904 reg = FDI_TX_CTL(pipe);
3905 temp = I915_READ(reg);
3906 temp &= ~FDI_LINK_TRAIN_NONE;
3907 temp |= FDI_LINK_TRAIN_PATTERN_2;
3908 if (IS_GEN6(dev_priv)) {
3909 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3910 /* SNB-B */
3911 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3912 }
3913 I915_WRITE(reg, temp);
3914
3915 reg = FDI_RX_CTL(pipe);
3916 temp = I915_READ(reg);
3917 if (HAS_PCH_CPT(dev_priv)) {
3918 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3919 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3920 } else {
3921 temp &= ~FDI_LINK_TRAIN_NONE;
3922 temp |= FDI_LINK_TRAIN_PATTERN_2;
3923 }
3924 I915_WRITE(reg, temp);
3925
3926 POSTING_READ(reg);
3927 udelay(150);
3928
3929 for (i = 0; i < 4; i++) {
3930 reg = FDI_TX_CTL(pipe);
3931 temp = I915_READ(reg);
3932 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3933 temp |= snb_b_fdi_train_param[i];
3934 I915_WRITE(reg, temp);
3935
3936 POSTING_READ(reg);
3937 udelay(500);
3938
3939 for (retry = 0; retry < 5; retry++) {
3940 reg = FDI_RX_IIR(pipe);
3941 temp = I915_READ(reg);
3942 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3943 if (temp & FDI_RX_SYMBOL_LOCK) {
3944 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3945 DRM_DEBUG_KMS("FDI train 2 done.\n");
3946 break;
3947 }
3948 udelay(50);
3949 }
3950 if (retry < 5)
3951 break;
3952 }
3953 if (i == 4)
3954 DRM_ERROR("FDI train 2 fail!\n");
3955
3956 DRM_DEBUG_KMS("FDI train done.\n");
3957 }
3958
3959 /* Manual link training for Ivy Bridge A0 parts */
3960 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
3961 const struct intel_crtc_state *crtc_state)
3962 {
3963 struct drm_device *dev = crtc->base.dev;
3964 struct drm_i915_private *dev_priv = to_i915(dev);
3965 int pipe = crtc->pipe;
3966 i915_reg_t reg;
3967 u32 temp, i, j;
3968
3969 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3970 for train result */
3971 reg = FDI_RX_IMR(pipe);
3972 temp = I915_READ(reg);
3973 temp &= ~FDI_RX_SYMBOL_LOCK;
3974 temp &= ~FDI_RX_BIT_LOCK;
3975 I915_WRITE(reg, temp);
3976
3977 POSTING_READ(reg);
3978 udelay(150);
3979
3980 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3981 I915_READ(FDI_RX_IIR(pipe)));
3982
3983 /* Try each vswing and preemphasis setting twice before moving on */
3984 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3985 /* disable first in case we need to retry */
3986 reg = FDI_TX_CTL(pipe);
3987 temp = I915_READ(reg);
3988 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3989 temp &= ~FDI_TX_ENABLE;
3990 I915_WRITE(reg, temp);
3991
3992 reg = FDI_RX_CTL(pipe);
3993 temp = I915_READ(reg);
3994 temp &= ~FDI_LINK_TRAIN_AUTO;
3995 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3996 temp &= ~FDI_RX_ENABLE;
3997 I915_WRITE(reg, temp);
3998
3999 /* enable CPU FDI TX and PCH FDI RX */
4000 reg = FDI_TX_CTL(pipe);
4001 temp = I915_READ(reg);
4002 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4003 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4004 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4005 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4006 temp |= snb_b_fdi_train_param[j/2];
4007 temp |= FDI_COMPOSITE_SYNC;
4008 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4009
4010 I915_WRITE(FDI_RX_MISC(pipe),
4011 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4012
4013 reg = FDI_RX_CTL(pipe);
4014 temp = I915_READ(reg);
4015 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4016 temp |= FDI_COMPOSITE_SYNC;
4017 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4018
4019 POSTING_READ(reg);
4020 udelay(1); /* should be 0.5us */
4021
4022 for (i = 0; i < 4; i++) {
4023 reg = FDI_RX_IIR(pipe);
4024 temp = I915_READ(reg);
4025 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4026
4027 if (temp & FDI_RX_BIT_LOCK ||
4028 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4029 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4030 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4031 i);
4032 break;
4033 }
4034 udelay(1); /* should be 0.5us */
4035 }
4036 if (i == 4) {
4037 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4038 continue;
4039 }
4040
4041 /* Train 2 */
4042 reg = FDI_TX_CTL(pipe);
4043 temp = I915_READ(reg);
4044 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4045 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4046 I915_WRITE(reg, temp);
4047
4048 reg = FDI_RX_CTL(pipe);
4049 temp = I915_READ(reg);
4050 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4051 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4052 I915_WRITE(reg, temp);
4053
4054 POSTING_READ(reg);
4055 udelay(2); /* should be 1.5us */
4056
4057 for (i = 0; i < 4; i++) {
4058 reg = FDI_RX_IIR(pipe);
4059 temp = I915_READ(reg);
4060 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4061
4062 if (temp & FDI_RX_SYMBOL_LOCK ||
4063 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4064 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4065 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4066 i);
4067 goto train_done;
4068 }
4069 udelay(2); /* should be 1.5us */
4070 }
4071 if (i == 4)
4072 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4073 }
4074
4075 train_done:
4076 DRM_DEBUG_KMS("FDI train done.\n");
4077 }
4078
4079 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4080 {
4081 struct drm_device *dev = intel_crtc->base.dev;
4082 struct drm_i915_private *dev_priv = to_i915(dev);
4083 int pipe = intel_crtc->pipe;
4084 i915_reg_t reg;
4085 u32 temp;
4086
4087 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4088 reg = FDI_RX_CTL(pipe);
4089 temp = I915_READ(reg);
4090 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4091 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4092 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4093 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4094
4095 POSTING_READ(reg);
4096 udelay(200);
4097
4098 /* Switch from Rawclk to PCDclk */
4099 temp = I915_READ(reg);
4100 I915_WRITE(reg, temp | FDI_PCDCLK);
4101
4102 POSTING_READ(reg);
4103 udelay(200);
4104
4105 /* Enable CPU FDI TX PLL, always on for Ironlake */
4106 reg = FDI_TX_CTL(pipe);
4107 temp = I915_READ(reg);
4108 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4109 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4110
4111 POSTING_READ(reg);
4112 udelay(100);
4113 }
4114 }
4115
4116 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4117 {
4118 struct drm_device *dev = intel_crtc->base.dev;
4119 struct drm_i915_private *dev_priv = to_i915(dev);
4120 int pipe = intel_crtc->pipe;
4121 i915_reg_t reg;
4122 u32 temp;
4123
4124 /* Switch from PCDclk to Rawclk */
4125 reg = FDI_RX_CTL(pipe);
4126 temp = I915_READ(reg);
4127 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4128
4129 /* Disable CPU FDI TX PLL */
4130 reg = FDI_TX_CTL(pipe);
4131 temp = I915_READ(reg);
4132 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4133
4134 POSTING_READ(reg);
4135 udelay(100);
4136
4137 reg = FDI_RX_CTL(pipe);
4138 temp = I915_READ(reg);
4139 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4140
4141 /* Wait for the clocks to turn off. */
4142 POSTING_READ(reg);
4143 udelay(100);
4144 }
4145
4146 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4147 {
4148 struct drm_device *dev = crtc->dev;
4149 struct drm_i915_private *dev_priv = to_i915(dev);
4150 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4151 int pipe = intel_crtc->pipe;
4152 i915_reg_t reg;
4153 u32 temp;
4154
4155 /* disable CPU FDI tx and PCH FDI rx */
4156 reg = FDI_TX_CTL(pipe);
4157 temp = I915_READ(reg);
4158 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4159 POSTING_READ(reg);
4160
4161 reg = FDI_RX_CTL(pipe);
4162 temp = I915_READ(reg);
4163 temp &= ~(0x7 << 16);
4164 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4165 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4166
4167 POSTING_READ(reg);
4168 udelay(100);
4169
4170 /* Ironlake workaround, disable clock pointer after downing FDI */
4171 if (HAS_PCH_IBX(dev_priv))
4172 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4173
4174 /* still set train pattern 1 */
4175 reg = FDI_TX_CTL(pipe);
4176 temp = I915_READ(reg);
4177 temp &= ~FDI_LINK_TRAIN_NONE;
4178 temp |= FDI_LINK_TRAIN_PATTERN_1;
4179 I915_WRITE(reg, temp);
4180
4181 reg = FDI_RX_CTL(pipe);
4182 temp = I915_READ(reg);
4183 if (HAS_PCH_CPT(dev_priv)) {
4184 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4185 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4186 } else {
4187 temp &= ~FDI_LINK_TRAIN_NONE;
4188 temp |= FDI_LINK_TRAIN_PATTERN_1;
4189 }
4190 /* BPC in FDI rx is consistent with that in PIPECONF */
4191 temp &= ~(0x07 << 16);
4192 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4193 I915_WRITE(reg, temp);
4194
4195 POSTING_READ(reg);
4196 udelay(100);
4197 }
4198
4199 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4200 {
4201 struct intel_crtc *crtc;
4202
4203 /* Note that we don't need to be called with mode_config.lock here
4204 * as our list of CRTC objects is static for the lifetime of the
4205 * device and so cannot disappear as we iterate. Similarly, we can
4206 * happily treat the predicates as racy, atomic checks as userspace
4207 * cannot claim and pin a new fb without at least acquring the
4208 * struct_mutex and so serialising with us.
4209 */
4210 for_each_intel_crtc(&dev_priv->drm, crtc) {
4211 if (atomic_read(&crtc->unpin_work_count) == 0)
4212 continue;
4213
4214 if (crtc->flip_work)
4215 intel_wait_for_vblank(dev_priv, crtc->pipe);
4216
4217 return true;
4218 }
4219
4220 return false;
4221 }
4222
4223 static void page_flip_completed(struct intel_crtc *intel_crtc)
4224 {
4225 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4226 struct intel_flip_work *work = intel_crtc->flip_work;
4227
4228 intel_crtc->flip_work = NULL;
4229
4230 if (work->event)
4231 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4232
4233 drm_crtc_vblank_put(&intel_crtc->base);
4234
4235 wake_up_all(&dev_priv->pending_flip_queue);
4236 trace_i915_flip_complete(intel_crtc->plane,
4237 work->pending_flip_obj);
4238
4239 queue_work(dev_priv->wq, &work->unpin_work);
4240 }
4241
4242 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4243 {
4244 struct drm_device *dev = crtc->dev;
4245 struct drm_i915_private *dev_priv = to_i915(dev);
4246 long ret;
4247
4248 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4249
4250 ret = wait_event_interruptible_timeout(
4251 dev_priv->pending_flip_queue,
4252 !intel_crtc_has_pending_flip(crtc),
4253 60*HZ);
4254
4255 if (ret < 0)
4256 return ret;
4257
4258 if (ret == 0) {
4259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4260 struct intel_flip_work *work;
4261
4262 spin_lock_irq(&dev->event_lock);
4263 work = intel_crtc->flip_work;
4264 if (work && !is_mmio_work(work)) {
4265 WARN_ONCE(1, "Removing stuck page flip\n");
4266 page_flip_completed(intel_crtc);
4267 }
4268 spin_unlock_irq(&dev->event_lock);
4269 }
4270
4271 return 0;
4272 }
4273
4274 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4275 {
4276 u32 temp;
4277
4278 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4279
4280 mutex_lock(&dev_priv->sb_lock);
4281
4282 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4283 temp |= SBI_SSCCTL_DISABLE;
4284 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4285
4286 mutex_unlock(&dev_priv->sb_lock);
4287 }
4288
4289 /* Program iCLKIP clock to the desired frequency */
4290 static void lpt_program_iclkip(struct intel_crtc *crtc)
4291 {
4292 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4293 int clock = crtc->config->base.adjusted_mode.crtc_clock;
4294 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4295 u32 temp;
4296
4297 lpt_disable_iclkip(dev_priv);
4298
4299 /* The iCLK virtual clock root frequency is in MHz,
4300 * but the adjusted_mode->crtc_clock in in KHz. To get the
4301 * divisors, it is necessary to divide one by another, so we
4302 * convert the virtual clock precision to KHz here for higher
4303 * precision.
4304 */
4305 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4306 u32 iclk_virtual_root_freq = 172800 * 1000;
4307 u32 iclk_pi_range = 64;
4308 u32 desired_divisor;
4309
4310 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4311 clock << auxdiv);
4312 divsel = (desired_divisor / iclk_pi_range) - 2;
4313 phaseinc = desired_divisor % iclk_pi_range;
4314
4315 /*
4316 * Near 20MHz is a corner case which is
4317 * out of range for the 7-bit divisor
4318 */
4319 if (divsel <= 0x7f)
4320 break;
4321 }
4322
4323 /* This should not happen with any sane values */
4324 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4325 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4326 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4327 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4328
4329 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4330 clock,
4331 auxdiv,
4332 divsel,
4333 phasedir,
4334 phaseinc);
4335
4336 mutex_lock(&dev_priv->sb_lock);
4337
4338 /* Program SSCDIVINTPHASE6 */
4339 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4340 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4341 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4342 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4343 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4344 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4345 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4346 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4347
4348 /* Program SSCAUXDIV */
4349 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4350 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4351 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4352 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4353
4354 /* Enable modulator and associated divider */
4355 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4356 temp &= ~SBI_SSCCTL_DISABLE;
4357 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4358
4359 mutex_unlock(&dev_priv->sb_lock);
4360
4361 /* Wait for initialization time */
4362 udelay(24);
4363
4364 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4365 }
4366
4367 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4368 {
4369 u32 divsel, phaseinc, auxdiv;
4370 u32 iclk_virtual_root_freq = 172800 * 1000;
4371 u32 iclk_pi_range = 64;
4372 u32 desired_divisor;
4373 u32 temp;
4374
4375 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4376 return 0;
4377
4378 mutex_lock(&dev_priv->sb_lock);
4379
4380 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4381 if (temp & SBI_SSCCTL_DISABLE) {
4382 mutex_unlock(&dev_priv->sb_lock);
4383 return 0;
4384 }
4385
4386 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4387 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4388 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4389 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4390 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4391
4392 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4393 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4394 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4395
4396 mutex_unlock(&dev_priv->sb_lock);
4397
4398 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4399
4400 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4401 desired_divisor << auxdiv);
4402 }
4403
4404 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4405 enum pipe pch_transcoder)
4406 {
4407 struct drm_device *dev = crtc->base.dev;
4408 struct drm_i915_private *dev_priv = to_i915(dev);
4409 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4410
4411 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4412 I915_READ(HTOTAL(cpu_transcoder)));
4413 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4414 I915_READ(HBLANK(cpu_transcoder)));
4415 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4416 I915_READ(HSYNC(cpu_transcoder)));
4417
4418 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4419 I915_READ(VTOTAL(cpu_transcoder)));
4420 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4421 I915_READ(VBLANK(cpu_transcoder)));
4422 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4423 I915_READ(VSYNC(cpu_transcoder)));
4424 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4425 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4426 }
4427
4428 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4429 {
4430 struct drm_i915_private *dev_priv = to_i915(dev);
4431 uint32_t temp;
4432
4433 temp = I915_READ(SOUTH_CHICKEN1);
4434 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4435 return;
4436
4437 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4438 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4439
4440 temp &= ~FDI_BC_BIFURCATION_SELECT;
4441 if (enable)
4442 temp |= FDI_BC_BIFURCATION_SELECT;
4443
4444 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4445 I915_WRITE(SOUTH_CHICKEN1, temp);
4446 POSTING_READ(SOUTH_CHICKEN1);
4447 }
4448
4449 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4450 {
4451 struct drm_device *dev = intel_crtc->base.dev;
4452
4453 switch (intel_crtc->pipe) {
4454 case PIPE_A:
4455 break;
4456 case PIPE_B:
4457 if (intel_crtc->config->fdi_lanes > 2)
4458 cpt_set_fdi_bc_bifurcation(dev, false);
4459 else
4460 cpt_set_fdi_bc_bifurcation(dev, true);
4461
4462 break;
4463 case PIPE_C:
4464 cpt_set_fdi_bc_bifurcation(dev, true);
4465
4466 break;
4467 default:
4468 BUG();
4469 }
4470 }
4471
4472 /* Return which DP Port should be selected for Transcoder DP control */
4473 static enum port
4474 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4475 {
4476 struct drm_device *dev = crtc->base.dev;
4477 struct intel_encoder *encoder;
4478
4479 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4480 if (encoder->type == INTEL_OUTPUT_DP ||
4481 encoder->type == INTEL_OUTPUT_EDP)
4482 return enc_to_dig_port(&encoder->base)->port;
4483 }
4484
4485 return -1;
4486 }
4487
4488 /*
4489 * Enable PCH resources required for PCH ports:
4490 * - PCH PLLs
4491 * - FDI training & RX/TX
4492 * - update transcoder timings
4493 * - DP transcoding bits
4494 * - transcoder
4495 */
4496 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4497 {
4498 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4499 struct drm_device *dev = crtc->base.dev;
4500 struct drm_i915_private *dev_priv = to_i915(dev);
4501 int pipe = crtc->pipe;
4502 u32 temp;
4503
4504 assert_pch_transcoder_disabled(dev_priv, pipe);
4505
4506 if (IS_IVYBRIDGE(dev_priv))
4507 ivybridge_update_fdi_bc_bifurcation(crtc);
4508
4509 /* Write the TU size bits before fdi link training, so that error
4510 * detection works. */
4511 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4512 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4513
4514 /* For PCH output, training FDI link */
4515 dev_priv->display.fdi_link_train(crtc, crtc_state);
4516
4517 /* We need to program the right clock selection before writing the pixel
4518 * mutliplier into the DPLL. */
4519 if (HAS_PCH_CPT(dev_priv)) {
4520 u32 sel;
4521
4522 temp = I915_READ(PCH_DPLL_SEL);
4523 temp |= TRANS_DPLL_ENABLE(pipe);
4524 sel = TRANS_DPLLB_SEL(pipe);
4525 if (crtc_state->shared_dpll ==
4526 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4527 temp |= sel;
4528 else
4529 temp &= ~sel;
4530 I915_WRITE(PCH_DPLL_SEL, temp);
4531 }
4532
4533 /* XXX: pch pll's can be enabled any time before we enable the PCH
4534 * transcoder, and we actually should do this to not upset any PCH
4535 * transcoder that already use the clock when we share it.
4536 *
4537 * Note that enable_shared_dpll tries to do the right thing, but
4538 * get_shared_dpll unconditionally resets the pll - we need that to have
4539 * the right LVDS enable sequence. */
4540 intel_enable_shared_dpll(crtc);
4541
4542 /* set transcoder timing, panel must allow it */
4543 assert_panel_unlocked(dev_priv, pipe);
4544 ironlake_pch_transcoder_set_timings(crtc, pipe);
4545
4546 intel_fdi_normal_train(crtc);
4547
4548 /* For PCH DP, enable TRANS_DP_CTL */
4549 if (HAS_PCH_CPT(dev_priv) &&
4550 intel_crtc_has_dp_encoder(crtc_state)) {
4551 const struct drm_display_mode *adjusted_mode =
4552 &crtc_state->base.adjusted_mode;
4553 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4554 i915_reg_t reg = TRANS_DP_CTL(pipe);
4555 temp = I915_READ(reg);
4556 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4557 TRANS_DP_SYNC_MASK |
4558 TRANS_DP_BPC_MASK);
4559 temp |= TRANS_DP_OUTPUT_ENABLE;
4560 temp |= bpc << 9; /* same format but at 11:9 */
4561
4562 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4563 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4564 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4565 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4566
4567 switch (intel_trans_dp_port_sel(crtc)) {
4568 case PORT_B:
4569 temp |= TRANS_DP_PORT_SEL_B;
4570 break;
4571 case PORT_C:
4572 temp |= TRANS_DP_PORT_SEL_C;
4573 break;
4574 case PORT_D:
4575 temp |= TRANS_DP_PORT_SEL_D;
4576 break;
4577 default:
4578 BUG();
4579 }
4580
4581 I915_WRITE(reg, temp);
4582 }
4583
4584 ironlake_enable_pch_transcoder(dev_priv, pipe);
4585 }
4586
4587 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4588 {
4589 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4590 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4591 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4592
4593 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4594
4595 lpt_program_iclkip(crtc);
4596
4597 /* Set transcoder timing. */
4598 ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4599
4600 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4601 }
4602
4603 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4604 {
4605 struct drm_i915_private *dev_priv = to_i915(dev);
4606 i915_reg_t dslreg = PIPEDSL(pipe);
4607 u32 temp;
4608
4609 temp = I915_READ(dslreg);
4610 udelay(500);
4611 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4612 if (wait_for(I915_READ(dslreg) != temp, 5))
4613 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4614 }
4615 }
4616
4617 static int
4618 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4619 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4620 int src_w, int src_h, int dst_w, int dst_h)
4621 {
4622 struct intel_crtc_scaler_state *scaler_state =
4623 &crtc_state->scaler_state;
4624 struct intel_crtc *intel_crtc =
4625 to_intel_crtc(crtc_state->base.crtc);
4626 int need_scaling;
4627
4628 need_scaling = drm_rotation_90_or_270(rotation) ?
4629 (src_h != dst_w || src_w != dst_h):
4630 (src_w != dst_w || src_h != dst_h);
4631
4632 /*
4633 * if plane is being disabled or scaler is no more required or force detach
4634 * - free scaler binded to this plane/crtc
4635 * - in order to do this, update crtc->scaler_usage
4636 *
4637 * Here scaler state in crtc_state is set free so that
4638 * scaler can be assigned to other user. Actual register
4639 * update to free the scaler is done in plane/panel-fit programming.
4640 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4641 */
4642 if (force_detach || !need_scaling) {
4643 if (*scaler_id >= 0) {
4644 scaler_state->scaler_users &= ~(1 << scaler_user);
4645 scaler_state->scalers[*scaler_id].in_use = 0;
4646
4647 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4648 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4649 intel_crtc->pipe, scaler_user, *scaler_id,
4650 scaler_state->scaler_users);
4651 *scaler_id = -1;
4652 }
4653 return 0;
4654 }
4655
4656 /* range checks */
4657 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4658 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4659
4660 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4661 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4662 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4663 "size is out of scaler range\n",
4664 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4665 return -EINVAL;
4666 }
4667
4668 /* mark this plane as a scaler user in crtc_state */
4669 scaler_state->scaler_users |= (1 << scaler_user);
4670 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4671 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4672 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4673 scaler_state->scaler_users);
4674
4675 return 0;
4676 }
4677
4678 /**
4679 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4680 *
4681 * @state: crtc's scaler state
4682 *
4683 * Return
4684 * 0 - scaler_usage updated successfully
4685 * error - requested scaling cannot be supported or other error condition
4686 */
4687 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4688 {
4689 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4690
4691 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4692 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4693 state->pipe_src_w, state->pipe_src_h,
4694 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4695 }
4696
4697 /**
4698 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4699 *
4700 * @state: crtc's scaler state
4701 * @plane_state: atomic plane state to update
4702 *
4703 * Return
4704 * 0 - scaler_usage updated successfully
4705 * error - requested scaling cannot be supported or other error condition
4706 */
4707 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4708 struct intel_plane_state *plane_state)
4709 {
4710
4711 struct intel_plane *intel_plane =
4712 to_intel_plane(plane_state->base.plane);
4713 struct drm_framebuffer *fb = plane_state->base.fb;
4714 int ret;
4715
4716 bool force_detach = !fb || !plane_state->base.visible;
4717
4718 ret = skl_update_scaler(crtc_state, force_detach,
4719 drm_plane_index(&intel_plane->base),
4720 &plane_state->scaler_id,
4721 plane_state->base.rotation,
4722 drm_rect_width(&plane_state->base.src) >> 16,
4723 drm_rect_height(&plane_state->base.src) >> 16,
4724 drm_rect_width(&plane_state->base.dst),
4725 drm_rect_height(&plane_state->base.dst));
4726
4727 if (ret || plane_state->scaler_id < 0)
4728 return ret;
4729
4730 /* check colorkey */
4731 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4732 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4733 intel_plane->base.base.id,
4734 intel_plane->base.name);
4735 return -EINVAL;
4736 }
4737
4738 /* Check src format */
4739 switch (fb->format->format) {
4740 case DRM_FORMAT_RGB565:
4741 case DRM_FORMAT_XBGR8888:
4742 case DRM_FORMAT_XRGB8888:
4743 case DRM_FORMAT_ABGR8888:
4744 case DRM_FORMAT_ARGB8888:
4745 case DRM_FORMAT_XRGB2101010:
4746 case DRM_FORMAT_XBGR2101010:
4747 case DRM_FORMAT_YUYV:
4748 case DRM_FORMAT_YVYU:
4749 case DRM_FORMAT_UYVY:
4750 case DRM_FORMAT_VYUY:
4751 break;
4752 default:
4753 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4754 intel_plane->base.base.id, intel_plane->base.name,
4755 fb->base.id, fb->format->format);
4756 return -EINVAL;
4757 }
4758
4759 return 0;
4760 }
4761
4762 static void skylake_scaler_disable(struct intel_crtc *crtc)
4763 {
4764 int i;
4765
4766 for (i = 0; i < crtc->num_scalers; i++)
4767 skl_detach_scaler(crtc, i);
4768 }
4769
4770 static void skylake_pfit_enable(struct intel_crtc *crtc)
4771 {
4772 struct drm_device *dev = crtc->base.dev;
4773 struct drm_i915_private *dev_priv = to_i915(dev);
4774 int pipe = crtc->pipe;
4775 struct intel_crtc_scaler_state *scaler_state =
4776 &crtc->config->scaler_state;
4777
4778 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4779
4780 if (crtc->config->pch_pfit.enabled) {
4781 int id;
4782
4783 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4784 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4785 return;
4786 }
4787
4788 id = scaler_state->scaler_id;
4789 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4790 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4791 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4792 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4793
4794 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4795 }
4796 }
4797
4798 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4799 {
4800 struct drm_device *dev = crtc->base.dev;
4801 struct drm_i915_private *dev_priv = to_i915(dev);
4802 int pipe = crtc->pipe;
4803
4804 if (crtc->config->pch_pfit.enabled) {
4805 /* Force use of hard-coded filter coefficients
4806 * as some pre-programmed values are broken,
4807 * e.g. x201.
4808 */
4809 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4810 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4811 PF_PIPE_SEL_IVB(pipe));
4812 else
4813 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4814 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4815 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4816 }
4817 }
4818
4819 void hsw_enable_ips(struct intel_crtc *crtc)
4820 {
4821 struct drm_device *dev = crtc->base.dev;
4822 struct drm_i915_private *dev_priv = to_i915(dev);
4823
4824 if (!crtc->config->ips_enabled)
4825 return;
4826
4827 /*
4828 * We can only enable IPS after we enable a plane and wait for a vblank
4829 * This function is called from post_plane_update, which is run after
4830 * a vblank wait.
4831 */
4832
4833 assert_plane_enabled(dev_priv, crtc->plane);
4834 if (IS_BROADWELL(dev_priv)) {
4835 mutex_lock(&dev_priv->rps.hw_lock);
4836 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4837 mutex_unlock(&dev_priv->rps.hw_lock);
4838 /* Quoting Art Runyan: "its not safe to expect any particular
4839 * value in IPS_CTL bit 31 after enabling IPS through the
4840 * mailbox." Moreover, the mailbox may return a bogus state,
4841 * so we need to just enable it and continue on.
4842 */
4843 } else {
4844 I915_WRITE(IPS_CTL, IPS_ENABLE);
4845 /* The bit only becomes 1 in the next vblank, so this wait here
4846 * is essentially intel_wait_for_vblank. If we don't have this
4847 * and don't wait for vblanks until the end of crtc_enable, then
4848 * the HW state readout code will complain that the expected
4849 * IPS_CTL value is not the one we read. */
4850 if (intel_wait_for_register(dev_priv,
4851 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4852 50))
4853 DRM_ERROR("Timed out waiting for IPS enable\n");
4854 }
4855 }
4856
4857 void hsw_disable_ips(struct intel_crtc *crtc)
4858 {
4859 struct drm_device *dev = crtc->base.dev;
4860 struct drm_i915_private *dev_priv = to_i915(dev);
4861
4862 if (!crtc->config->ips_enabled)
4863 return;
4864
4865 assert_plane_enabled(dev_priv, crtc->plane);
4866 if (IS_BROADWELL(dev_priv)) {
4867 mutex_lock(&dev_priv->rps.hw_lock);
4868 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4869 mutex_unlock(&dev_priv->rps.hw_lock);
4870 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4871 if (intel_wait_for_register(dev_priv,
4872 IPS_CTL, IPS_ENABLE, 0,
4873 42))
4874 DRM_ERROR("Timed out waiting for IPS disable\n");
4875 } else {
4876 I915_WRITE(IPS_CTL, 0);
4877 POSTING_READ(IPS_CTL);
4878 }
4879
4880 /* We need to wait for a vblank before we can disable the plane. */
4881 intel_wait_for_vblank(dev_priv, crtc->pipe);
4882 }
4883
4884 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4885 {
4886 if (intel_crtc->overlay) {
4887 struct drm_device *dev = intel_crtc->base.dev;
4888 struct drm_i915_private *dev_priv = to_i915(dev);
4889
4890 mutex_lock(&dev->struct_mutex);
4891 dev_priv->mm.interruptible = false;
4892 (void) intel_overlay_switch_off(intel_crtc->overlay);
4893 dev_priv->mm.interruptible = true;
4894 mutex_unlock(&dev->struct_mutex);
4895 }
4896
4897 /* Let userspace switch the overlay on again. In most cases userspace
4898 * has to recompute where to put it anyway.
4899 */
4900 }
4901
4902 /**
4903 * intel_post_enable_primary - Perform operations after enabling primary plane
4904 * @crtc: the CRTC whose primary plane was just enabled
4905 *
4906 * Performs potentially sleeping operations that must be done after the primary
4907 * plane is enabled, such as updating FBC and IPS. Note that this may be
4908 * called due to an explicit primary plane update, or due to an implicit
4909 * re-enable that is caused when a sprite plane is updated to no longer
4910 * completely hide the primary plane.
4911 */
4912 static void
4913 intel_post_enable_primary(struct drm_crtc *crtc)
4914 {
4915 struct drm_device *dev = crtc->dev;
4916 struct drm_i915_private *dev_priv = to_i915(dev);
4917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4918 int pipe = intel_crtc->pipe;
4919
4920 /*
4921 * FIXME IPS should be fine as long as one plane is
4922 * enabled, but in practice it seems to have problems
4923 * when going from primary only to sprite only and vice
4924 * versa.
4925 */
4926 hsw_enable_ips(intel_crtc);
4927
4928 /*
4929 * Gen2 reports pipe underruns whenever all planes are disabled.
4930 * So don't enable underrun reporting before at least some planes
4931 * are enabled.
4932 * FIXME: Need to fix the logic to work when we turn off all planes
4933 * but leave the pipe running.
4934 */
4935 if (IS_GEN2(dev_priv))
4936 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4937
4938 /* Underruns don't always raise interrupts, so check manually. */
4939 intel_check_cpu_fifo_underruns(dev_priv);
4940 intel_check_pch_fifo_underruns(dev_priv);
4941 }
4942
4943 /* FIXME move all this to pre_plane_update() with proper state tracking */
4944 static void
4945 intel_pre_disable_primary(struct drm_crtc *crtc)
4946 {
4947 struct drm_device *dev = crtc->dev;
4948 struct drm_i915_private *dev_priv = to_i915(dev);
4949 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4950 int pipe = intel_crtc->pipe;
4951
4952 /*
4953 * Gen2 reports pipe underruns whenever all planes are disabled.
4954 * So diasble underrun reporting before all the planes get disabled.
4955 * FIXME: Need to fix the logic to work when we turn off all planes
4956 * but leave the pipe running.
4957 */
4958 if (IS_GEN2(dev_priv))
4959 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4960
4961 /*
4962 * FIXME IPS should be fine as long as one plane is
4963 * enabled, but in practice it seems to have problems
4964 * when going from primary only to sprite only and vice
4965 * versa.
4966 */
4967 hsw_disable_ips(intel_crtc);
4968 }
4969
4970 /* FIXME get rid of this and use pre_plane_update */
4971 static void
4972 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4973 {
4974 struct drm_device *dev = crtc->dev;
4975 struct drm_i915_private *dev_priv = to_i915(dev);
4976 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4977 int pipe = intel_crtc->pipe;
4978
4979 intel_pre_disable_primary(crtc);
4980
4981 /*
4982 * Vblank time updates from the shadow to live plane control register
4983 * are blocked if the memory self-refresh mode is active at that
4984 * moment. So to make sure the plane gets truly disabled, disable
4985 * first the self-refresh mode. The self-refresh enable bit in turn
4986 * will be checked/applied by the HW only at the next frame start
4987 * event which is after the vblank start event, so we need to have a
4988 * wait-for-vblank between disabling the plane and the pipe.
4989 */
4990 if (HAS_GMCH_DISPLAY(dev_priv) &&
4991 intel_set_memory_cxsr(dev_priv, false))
4992 intel_wait_for_vblank(dev_priv, pipe);
4993 }
4994
4995 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4996 {
4997 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4998 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4999 struct intel_crtc_state *pipe_config =
5000 to_intel_crtc_state(crtc->base.state);
5001 struct drm_plane *primary = crtc->base.primary;
5002 struct drm_plane_state *old_pri_state =
5003 drm_atomic_get_existing_plane_state(old_state, primary);
5004
5005 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5006
5007 if (pipe_config->update_wm_post && pipe_config->base.active)
5008 intel_update_watermarks(crtc);
5009
5010 if (old_pri_state) {
5011 struct intel_plane_state *primary_state =
5012 to_intel_plane_state(primary->state);
5013 struct intel_plane_state *old_primary_state =
5014 to_intel_plane_state(old_pri_state);
5015
5016 intel_fbc_post_update(crtc);
5017
5018 if (primary_state->base.visible &&
5019 (needs_modeset(&pipe_config->base) ||
5020 !old_primary_state->base.visible))
5021 intel_post_enable_primary(&crtc->base);
5022 }
5023 }
5024
5025 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
5026 {
5027 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5028 struct drm_device *dev = crtc->base.dev;
5029 struct drm_i915_private *dev_priv = to_i915(dev);
5030 struct intel_crtc_state *pipe_config =
5031 to_intel_crtc_state(crtc->base.state);
5032 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5033 struct drm_plane *primary = crtc->base.primary;
5034 struct drm_plane_state *old_pri_state =
5035 drm_atomic_get_existing_plane_state(old_state, primary);
5036 bool modeset = needs_modeset(&pipe_config->base);
5037 struct intel_atomic_state *old_intel_state =
5038 to_intel_atomic_state(old_state);
5039
5040 if (old_pri_state) {
5041 struct intel_plane_state *primary_state =
5042 to_intel_plane_state(primary->state);
5043 struct intel_plane_state *old_primary_state =
5044 to_intel_plane_state(old_pri_state);
5045
5046 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5047
5048 if (old_primary_state->base.visible &&
5049 (modeset || !primary_state->base.visible))
5050 intel_pre_disable_primary(&crtc->base);
5051 }
5052
5053 /*
5054 * Vblank time updates from the shadow to live plane control register
5055 * are blocked if the memory self-refresh mode is active at that
5056 * moment. So to make sure the plane gets truly disabled, disable
5057 * first the self-refresh mode. The self-refresh enable bit in turn
5058 * will be checked/applied by the HW only at the next frame start
5059 * event which is after the vblank start event, so we need to have a
5060 * wait-for-vblank between disabling the plane and the pipe.
5061 */
5062 if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5063 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5064 intel_wait_for_vblank(dev_priv, crtc->pipe);
5065
5066 /*
5067 * IVB workaround: must disable low power watermarks for at least
5068 * one frame before enabling scaling. LP watermarks can be re-enabled
5069 * when scaling is disabled.
5070 *
5071 * WaCxSRDisabledForSpriteScaling:ivb
5072 */
5073 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5074 intel_wait_for_vblank(dev_priv, crtc->pipe);
5075
5076 /*
5077 * If we're doing a modeset, we're done. No need to do any pre-vblank
5078 * watermark programming here.
5079 */
5080 if (needs_modeset(&pipe_config->base))
5081 return;
5082
5083 /*
5084 * For platforms that support atomic watermarks, program the
5085 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5086 * will be the intermediate values that are safe for both pre- and
5087 * post- vblank; when vblank happens, the 'active' values will be set
5088 * to the final 'target' values and we'll do this again to get the
5089 * optimal watermarks. For gen9+ platforms, the values we program here
5090 * will be the final target values which will get automatically latched
5091 * at vblank time; no further programming will be necessary.
5092 *
5093 * If a platform hasn't been transitioned to atomic watermarks yet,
5094 * we'll continue to update watermarks the old way, if flags tell
5095 * us to.
5096 */
5097 if (dev_priv->display.initial_watermarks != NULL)
5098 dev_priv->display.initial_watermarks(old_intel_state,
5099 pipe_config);
5100 else if (pipe_config->update_wm_pre)
5101 intel_update_watermarks(crtc);
5102 }
5103
5104 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5105 {
5106 struct drm_device *dev = crtc->dev;
5107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5108 struct drm_plane *p;
5109 int pipe = intel_crtc->pipe;
5110
5111 intel_crtc_dpms_overlay_disable(intel_crtc);
5112
5113 drm_for_each_plane_mask(p, dev, plane_mask)
5114 to_intel_plane(p)->disable_plane(p, crtc);
5115
5116 /*
5117 * FIXME: Once we grow proper nuclear flip support out of this we need
5118 * to compute the mask of flip planes precisely. For the time being
5119 * consider this a flip to a NULL plane.
5120 */
5121 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5122 }
5123
5124 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5125 struct intel_crtc_state *crtc_state,
5126 struct drm_atomic_state *old_state)
5127 {
5128 struct drm_connector_state *old_conn_state;
5129 struct drm_connector *conn;
5130 int i;
5131
5132 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5133 struct drm_connector_state *conn_state = conn->state;
5134 struct intel_encoder *encoder =
5135 to_intel_encoder(conn_state->best_encoder);
5136
5137 if (conn_state->crtc != crtc)
5138 continue;
5139
5140 if (encoder->pre_pll_enable)
5141 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5142 }
5143 }
5144
5145 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5146 struct intel_crtc_state *crtc_state,
5147 struct drm_atomic_state *old_state)
5148 {
5149 struct drm_connector_state *old_conn_state;
5150 struct drm_connector *conn;
5151 int i;
5152
5153 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5154 struct drm_connector_state *conn_state = conn->state;
5155 struct intel_encoder *encoder =
5156 to_intel_encoder(conn_state->best_encoder);
5157
5158 if (conn_state->crtc != crtc)
5159 continue;
5160
5161 if (encoder->pre_enable)
5162 encoder->pre_enable(encoder, crtc_state, conn_state);
5163 }
5164 }
5165
5166 static void intel_encoders_enable(struct drm_crtc *crtc,
5167 struct intel_crtc_state *crtc_state,
5168 struct drm_atomic_state *old_state)
5169 {
5170 struct drm_connector_state *old_conn_state;
5171 struct drm_connector *conn;
5172 int i;
5173
5174 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5175 struct drm_connector_state *conn_state = conn->state;
5176 struct intel_encoder *encoder =
5177 to_intel_encoder(conn_state->best_encoder);
5178
5179 if (conn_state->crtc != crtc)
5180 continue;
5181
5182 encoder->enable(encoder, crtc_state, conn_state);
5183 intel_opregion_notify_encoder(encoder, true);
5184 }
5185 }
5186
5187 static void intel_encoders_disable(struct drm_crtc *crtc,
5188 struct intel_crtc_state *old_crtc_state,
5189 struct drm_atomic_state *old_state)
5190 {
5191 struct drm_connector_state *old_conn_state;
5192 struct drm_connector *conn;
5193 int i;
5194
5195 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5196 struct intel_encoder *encoder =
5197 to_intel_encoder(old_conn_state->best_encoder);
5198
5199 if (old_conn_state->crtc != crtc)
5200 continue;
5201
5202 intel_opregion_notify_encoder(encoder, false);
5203 encoder->disable(encoder, old_crtc_state, old_conn_state);
5204 }
5205 }
5206
5207 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5208 struct intel_crtc_state *old_crtc_state,
5209 struct drm_atomic_state *old_state)
5210 {
5211 struct drm_connector_state *old_conn_state;
5212 struct drm_connector *conn;
5213 int i;
5214
5215 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5216 struct intel_encoder *encoder =
5217 to_intel_encoder(old_conn_state->best_encoder);
5218
5219 if (old_conn_state->crtc != crtc)
5220 continue;
5221
5222 if (encoder->post_disable)
5223 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5224 }
5225 }
5226
5227 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5228 struct intel_crtc_state *old_crtc_state,
5229 struct drm_atomic_state *old_state)
5230 {
5231 struct drm_connector_state *old_conn_state;
5232 struct drm_connector *conn;
5233 int i;
5234
5235 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5236 struct intel_encoder *encoder =
5237 to_intel_encoder(old_conn_state->best_encoder);
5238
5239 if (old_conn_state->crtc != crtc)
5240 continue;
5241
5242 if (encoder->post_pll_disable)
5243 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5244 }
5245 }
5246
5247 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5248 struct drm_atomic_state *old_state)
5249 {
5250 struct drm_crtc *crtc = pipe_config->base.crtc;
5251 struct drm_device *dev = crtc->dev;
5252 struct drm_i915_private *dev_priv = to_i915(dev);
5253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5254 int pipe = intel_crtc->pipe;
5255 struct intel_atomic_state *old_intel_state =
5256 to_intel_atomic_state(old_state);
5257
5258 if (WARN_ON(intel_crtc->active))
5259 return;
5260
5261 /*
5262 * Sometimes spurious CPU pipe underruns happen during FDI
5263 * training, at least with VGA+HDMI cloning. Suppress them.
5264 *
5265 * On ILK we get an occasional spurious CPU pipe underruns
5266 * between eDP port A enable and vdd enable. Also PCH port
5267 * enable seems to result in the occasional CPU pipe underrun.
5268 *
5269 * Spurious PCH underruns also occur during PCH enabling.
5270 */
5271 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5272 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5273 if (intel_crtc->config->has_pch_encoder)
5274 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5275
5276 if (intel_crtc->config->has_pch_encoder)
5277 intel_prepare_shared_dpll(intel_crtc);
5278
5279 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5280 intel_dp_set_m_n(intel_crtc, M1_N1);
5281
5282 intel_set_pipe_timings(intel_crtc);
5283 intel_set_pipe_src_size(intel_crtc);
5284
5285 if (intel_crtc->config->has_pch_encoder) {
5286 intel_cpu_transcoder_set_m_n(intel_crtc,
5287 &intel_crtc->config->fdi_m_n, NULL);
5288 }
5289
5290 ironlake_set_pipeconf(crtc);
5291
5292 intel_crtc->active = true;
5293
5294 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5295
5296 if (intel_crtc->config->has_pch_encoder) {
5297 /* Note: FDI PLL enabling _must_ be done before we enable the
5298 * cpu pipes, hence this is separate from all the other fdi/pch
5299 * enabling. */
5300 ironlake_fdi_pll_enable(intel_crtc);
5301 } else {
5302 assert_fdi_tx_disabled(dev_priv, pipe);
5303 assert_fdi_rx_disabled(dev_priv, pipe);
5304 }
5305
5306 ironlake_pfit_enable(intel_crtc);
5307
5308 /*
5309 * On ILK+ LUT must be loaded before the pipe is running but with
5310 * clocks enabled
5311 */
5312 intel_color_load_luts(&pipe_config->base);
5313
5314 if (dev_priv->display.initial_watermarks != NULL)
5315 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5316 intel_enable_pipe(intel_crtc);
5317
5318 if (intel_crtc->config->has_pch_encoder)
5319 ironlake_pch_enable(pipe_config);
5320
5321 assert_vblank_disabled(crtc);
5322 drm_crtc_vblank_on(crtc);
5323
5324 intel_encoders_enable(crtc, pipe_config, old_state);
5325
5326 if (HAS_PCH_CPT(dev_priv))
5327 cpt_verify_modeset(dev, intel_crtc->pipe);
5328
5329 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5330 if (intel_crtc->config->has_pch_encoder)
5331 intel_wait_for_vblank(dev_priv, pipe);
5332 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5333 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5334 }
5335
5336 /* IPS only exists on ULT machines and is tied to pipe A. */
5337 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5338 {
5339 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5340 }
5341
5342 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5343 struct drm_atomic_state *old_state)
5344 {
5345 struct drm_crtc *crtc = pipe_config->base.crtc;
5346 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5348 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5349 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5350 struct intel_atomic_state *old_intel_state =
5351 to_intel_atomic_state(old_state);
5352
5353 if (WARN_ON(intel_crtc->active))
5354 return;
5355
5356 if (intel_crtc->config->has_pch_encoder)
5357 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5358 false);
5359
5360 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5361
5362 if (intel_crtc->config->shared_dpll)
5363 intel_enable_shared_dpll(intel_crtc);
5364
5365 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5366 intel_dp_set_m_n(intel_crtc, M1_N1);
5367
5368 if (!transcoder_is_dsi(cpu_transcoder))
5369 intel_set_pipe_timings(intel_crtc);
5370
5371 intel_set_pipe_src_size(intel_crtc);
5372
5373 if (cpu_transcoder != TRANSCODER_EDP &&
5374 !transcoder_is_dsi(cpu_transcoder)) {
5375 I915_WRITE(PIPE_MULT(cpu_transcoder),
5376 intel_crtc->config->pixel_multiplier - 1);
5377 }
5378
5379 if (intel_crtc->config->has_pch_encoder) {
5380 intel_cpu_transcoder_set_m_n(intel_crtc,
5381 &intel_crtc->config->fdi_m_n, NULL);
5382 }
5383
5384 if (!transcoder_is_dsi(cpu_transcoder))
5385 haswell_set_pipeconf(crtc);
5386
5387 haswell_set_pipemisc(crtc);
5388
5389 intel_color_set_csc(&pipe_config->base);
5390
5391 intel_crtc->active = true;
5392
5393 if (intel_crtc->config->has_pch_encoder)
5394 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5395 else
5396 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5397
5398 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5399
5400 if (intel_crtc->config->has_pch_encoder)
5401 dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
5402
5403 if (!transcoder_is_dsi(cpu_transcoder))
5404 intel_ddi_enable_pipe_clock(pipe_config);
5405
5406 if (INTEL_GEN(dev_priv) >= 9)
5407 skylake_pfit_enable(intel_crtc);
5408 else
5409 ironlake_pfit_enable(intel_crtc);
5410
5411 /*
5412 * On ILK+ LUT must be loaded before the pipe is running but with
5413 * clocks enabled
5414 */
5415 intel_color_load_luts(&pipe_config->base);
5416
5417 intel_ddi_set_pipe_settings(pipe_config);
5418 if (!transcoder_is_dsi(cpu_transcoder))
5419 intel_ddi_enable_transcoder_func(pipe_config);
5420
5421 if (dev_priv->display.initial_watermarks != NULL)
5422 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5423
5424 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5425 if (!transcoder_is_dsi(cpu_transcoder))
5426 intel_enable_pipe(intel_crtc);
5427
5428 if (intel_crtc->config->has_pch_encoder)
5429 lpt_pch_enable(pipe_config);
5430
5431 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5432 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5433
5434 assert_vblank_disabled(crtc);
5435 drm_crtc_vblank_on(crtc);
5436
5437 intel_encoders_enable(crtc, pipe_config, old_state);
5438
5439 if (intel_crtc->config->has_pch_encoder) {
5440 intel_wait_for_vblank(dev_priv, pipe);
5441 intel_wait_for_vblank(dev_priv, pipe);
5442 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5443 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5444 true);
5445 }
5446
5447 /* If we change the relative order between pipe/planes enabling, we need
5448 * to change the workaround. */
5449 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5450 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5451 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5452 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5453 }
5454 }
5455
5456 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5457 {
5458 struct drm_device *dev = crtc->base.dev;
5459 struct drm_i915_private *dev_priv = to_i915(dev);
5460 int pipe = crtc->pipe;
5461
5462 /* To avoid upsetting the power well on haswell only disable the pfit if
5463 * it's in use. The hw state code will make sure we get this right. */
5464 if (force || crtc->config->pch_pfit.enabled) {
5465 I915_WRITE(PF_CTL(pipe), 0);
5466 I915_WRITE(PF_WIN_POS(pipe), 0);
5467 I915_WRITE(PF_WIN_SZ(pipe), 0);
5468 }
5469 }
5470
5471 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5472 struct drm_atomic_state *old_state)
5473 {
5474 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5475 struct drm_device *dev = crtc->dev;
5476 struct drm_i915_private *dev_priv = to_i915(dev);
5477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5478 int pipe = intel_crtc->pipe;
5479
5480 /*
5481 * Sometimes spurious CPU pipe underruns happen when the
5482 * pipe is already disabled, but FDI RX/TX is still enabled.
5483 * Happens at least with VGA+HDMI cloning. Suppress them.
5484 */
5485 if (intel_crtc->config->has_pch_encoder) {
5486 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5487 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5488 }
5489
5490 intel_encoders_disable(crtc, old_crtc_state, old_state);
5491
5492 drm_crtc_vblank_off(crtc);
5493 assert_vblank_disabled(crtc);
5494
5495 intel_disable_pipe(intel_crtc);
5496
5497 ironlake_pfit_disable(intel_crtc, false);
5498
5499 if (intel_crtc->config->has_pch_encoder)
5500 ironlake_fdi_disable(crtc);
5501
5502 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5503
5504 if (intel_crtc->config->has_pch_encoder) {
5505 ironlake_disable_pch_transcoder(dev_priv, pipe);
5506
5507 if (HAS_PCH_CPT(dev_priv)) {
5508 i915_reg_t reg;
5509 u32 temp;
5510
5511 /* disable TRANS_DP_CTL */
5512 reg = TRANS_DP_CTL(pipe);
5513 temp = I915_READ(reg);
5514 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5515 TRANS_DP_PORT_SEL_MASK);
5516 temp |= TRANS_DP_PORT_SEL_NONE;
5517 I915_WRITE(reg, temp);
5518
5519 /* disable DPLL_SEL */
5520 temp = I915_READ(PCH_DPLL_SEL);
5521 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5522 I915_WRITE(PCH_DPLL_SEL, temp);
5523 }
5524
5525 ironlake_fdi_pll_disable(intel_crtc);
5526 }
5527
5528 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5529 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5530 }
5531
5532 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5533 struct drm_atomic_state *old_state)
5534 {
5535 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5536 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5538 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5539
5540 if (intel_crtc->config->has_pch_encoder)
5541 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5542 false);
5543
5544 intel_encoders_disable(crtc, old_crtc_state, old_state);
5545
5546 drm_crtc_vblank_off(crtc);
5547 assert_vblank_disabled(crtc);
5548
5549 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5550 if (!transcoder_is_dsi(cpu_transcoder))
5551 intel_disable_pipe(intel_crtc);
5552
5553 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5554 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5555
5556 if (!transcoder_is_dsi(cpu_transcoder))
5557 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5558
5559 if (INTEL_GEN(dev_priv) >= 9)
5560 skylake_scaler_disable(intel_crtc);
5561 else
5562 ironlake_pfit_disable(intel_crtc, false);
5563
5564 if (!transcoder_is_dsi(cpu_transcoder))
5565 intel_ddi_disable_pipe_clock(intel_crtc->config);
5566
5567 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5568
5569 if (old_crtc_state->has_pch_encoder)
5570 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5571 true);
5572 }
5573
5574 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5575 {
5576 struct drm_device *dev = crtc->base.dev;
5577 struct drm_i915_private *dev_priv = to_i915(dev);
5578 struct intel_crtc_state *pipe_config = crtc->config;
5579
5580 if (!pipe_config->gmch_pfit.control)
5581 return;
5582
5583 /*
5584 * The panel fitter should only be adjusted whilst the pipe is disabled,
5585 * according to register description and PRM.
5586 */
5587 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5588 assert_pipe_disabled(dev_priv, crtc->pipe);
5589
5590 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5591 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5592
5593 /* Border color in case we don't scale up to the full screen. Black by
5594 * default, change to something else for debugging. */
5595 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5596 }
5597
5598 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5599 {
5600 switch (port) {
5601 case PORT_A:
5602 return POWER_DOMAIN_PORT_DDI_A_LANES;
5603 case PORT_B:
5604 return POWER_DOMAIN_PORT_DDI_B_LANES;
5605 case PORT_C:
5606 return POWER_DOMAIN_PORT_DDI_C_LANES;
5607 case PORT_D:
5608 return POWER_DOMAIN_PORT_DDI_D_LANES;
5609 case PORT_E:
5610 return POWER_DOMAIN_PORT_DDI_E_LANES;
5611 default:
5612 MISSING_CASE(port);
5613 return POWER_DOMAIN_PORT_OTHER;
5614 }
5615 }
5616
5617 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5618 struct intel_crtc_state *crtc_state)
5619 {
5620 struct drm_device *dev = crtc->dev;
5621 struct drm_i915_private *dev_priv = to_i915(dev);
5622 struct drm_encoder *encoder;
5623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5624 enum pipe pipe = intel_crtc->pipe;
5625 u64 mask;
5626 enum transcoder transcoder = crtc_state->cpu_transcoder;
5627
5628 if (!crtc_state->base.active)
5629 return 0;
5630
5631 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5632 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5633 if (crtc_state->pch_pfit.enabled ||
5634 crtc_state->pch_pfit.force_thru)
5635 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5636
5637 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5638 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5639
5640 mask |= BIT_ULL(intel_encoder->power_domain);
5641 }
5642
5643 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5644 mask |= BIT(POWER_DOMAIN_AUDIO);
5645
5646 if (crtc_state->shared_dpll)
5647 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5648
5649 return mask;
5650 }
5651
5652 static u64
5653 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5654 struct intel_crtc_state *crtc_state)
5655 {
5656 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5657 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5658 enum intel_display_power_domain domain;
5659 u64 domains, new_domains, old_domains;
5660
5661 old_domains = intel_crtc->enabled_power_domains;
5662 intel_crtc->enabled_power_domains = new_domains =
5663 get_crtc_power_domains(crtc, crtc_state);
5664
5665 domains = new_domains & ~old_domains;
5666
5667 for_each_power_domain(domain, domains)
5668 intel_display_power_get(dev_priv, domain);
5669
5670 return old_domains & ~new_domains;
5671 }
5672
5673 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5674 u64 domains)
5675 {
5676 enum intel_display_power_domain domain;
5677
5678 for_each_power_domain(domain, domains)
5679 intel_display_power_put(dev_priv, domain);
5680 }
5681
5682 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5683 struct drm_atomic_state *old_state)
5684 {
5685 struct intel_atomic_state *old_intel_state =
5686 to_intel_atomic_state(old_state);
5687 struct drm_crtc *crtc = pipe_config->base.crtc;
5688 struct drm_device *dev = crtc->dev;
5689 struct drm_i915_private *dev_priv = to_i915(dev);
5690 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5691 int pipe = intel_crtc->pipe;
5692
5693 if (WARN_ON(intel_crtc->active))
5694 return;
5695
5696 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5697 intel_dp_set_m_n(intel_crtc, M1_N1);
5698
5699 intel_set_pipe_timings(intel_crtc);
5700 intel_set_pipe_src_size(intel_crtc);
5701
5702 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5703 struct drm_i915_private *dev_priv = to_i915(dev);
5704
5705 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5706 I915_WRITE(CHV_CANVAS(pipe), 0);
5707 }
5708
5709 i9xx_set_pipeconf(intel_crtc);
5710
5711 intel_crtc->active = true;
5712
5713 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5714
5715 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5716
5717 if (IS_CHERRYVIEW(dev_priv)) {
5718 chv_prepare_pll(intel_crtc, intel_crtc->config);
5719 chv_enable_pll(intel_crtc, intel_crtc->config);
5720 } else {
5721 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5722 vlv_enable_pll(intel_crtc, intel_crtc->config);
5723 }
5724
5725 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5726
5727 i9xx_pfit_enable(intel_crtc);
5728
5729 intel_color_load_luts(&pipe_config->base);
5730
5731 dev_priv->display.initial_watermarks(old_intel_state,
5732 pipe_config);
5733 intel_enable_pipe(intel_crtc);
5734
5735 assert_vblank_disabled(crtc);
5736 drm_crtc_vblank_on(crtc);
5737
5738 intel_encoders_enable(crtc, pipe_config, old_state);
5739 }
5740
5741 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5742 {
5743 struct drm_device *dev = crtc->base.dev;
5744 struct drm_i915_private *dev_priv = to_i915(dev);
5745
5746 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5747 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5748 }
5749
5750 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5751 struct drm_atomic_state *old_state)
5752 {
5753 struct drm_crtc *crtc = pipe_config->base.crtc;
5754 struct drm_device *dev = crtc->dev;
5755 struct drm_i915_private *dev_priv = to_i915(dev);
5756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5757 enum pipe pipe = intel_crtc->pipe;
5758
5759 if (WARN_ON(intel_crtc->active))
5760 return;
5761
5762 i9xx_set_pll_dividers(intel_crtc);
5763
5764 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5765 intel_dp_set_m_n(intel_crtc, M1_N1);
5766
5767 intel_set_pipe_timings(intel_crtc);
5768 intel_set_pipe_src_size(intel_crtc);
5769
5770 i9xx_set_pipeconf(intel_crtc);
5771
5772 intel_crtc->active = true;
5773
5774 if (!IS_GEN2(dev_priv))
5775 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5776
5777 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5778
5779 i9xx_enable_pll(intel_crtc);
5780
5781 i9xx_pfit_enable(intel_crtc);
5782
5783 intel_color_load_luts(&pipe_config->base);
5784
5785 intel_update_watermarks(intel_crtc);
5786 intel_enable_pipe(intel_crtc);
5787
5788 assert_vblank_disabled(crtc);
5789 drm_crtc_vblank_on(crtc);
5790
5791 intel_encoders_enable(crtc, pipe_config, old_state);
5792 }
5793
5794 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5795 {
5796 struct drm_device *dev = crtc->base.dev;
5797 struct drm_i915_private *dev_priv = to_i915(dev);
5798
5799 if (!crtc->config->gmch_pfit.control)
5800 return;
5801
5802 assert_pipe_disabled(dev_priv, crtc->pipe);
5803
5804 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5805 I915_READ(PFIT_CONTROL));
5806 I915_WRITE(PFIT_CONTROL, 0);
5807 }
5808
5809 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5810 struct drm_atomic_state *old_state)
5811 {
5812 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5813 struct drm_device *dev = crtc->dev;
5814 struct drm_i915_private *dev_priv = to_i915(dev);
5815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5816 int pipe = intel_crtc->pipe;
5817
5818 /*
5819 * On gen2 planes are double buffered but the pipe isn't, so we must
5820 * wait for planes to fully turn off before disabling the pipe.
5821 */
5822 if (IS_GEN2(dev_priv))
5823 intel_wait_for_vblank(dev_priv, pipe);
5824
5825 intel_encoders_disable(crtc, old_crtc_state, old_state);
5826
5827 drm_crtc_vblank_off(crtc);
5828 assert_vblank_disabled(crtc);
5829
5830 intel_disable_pipe(intel_crtc);
5831
5832 i9xx_pfit_disable(intel_crtc);
5833
5834 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5835
5836 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5837 if (IS_CHERRYVIEW(dev_priv))
5838 chv_disable_pll(dev_priv, pipe);
5839 else if (IS_VALLEYVIEW(dev_priv))
5840 vlv_disable_pll(dev_priv, pipe);
5841 else
5842 i9xx_disable_pll(intel_crtc);
5843 }
5844
5845 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5846
5847 if (!IS_GEN2(dev_priv))
5848 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5849
5850 if (!dev_priv->display.initial_watermarks)
5851 intel_update_watermarks(intel_crtc);
5852 }
5853
5854 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
5855 {
5856 struct intel_encoder *encoder;
5857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5858 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5859 enum intel_display_power_domain domain;
5860 u64 domains;
5861 struct drm_atomic_state *state;
5862 struct intel_crtc_state *crtc_state;
5863 int ret;
5864
5865 if (!intel_crtc->active)
5866 return;
5867
5868 if (crtc->primary->state->visible) {
5869 WARN_ON(intel_crtc->flip_work);
5870
5871 intel_pre_disable_primary_noatomic(crtc);
5872
5873 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5874 crtc->primary->state->visible = false;
5875 }
5876
5877 state = drm_atomic_state_alloc(crtc->dev);
5878 if (!state) {
5879 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5880 crtc->base.id, crtc->name);
5881 return;
5882 }
5883
5884 state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
5885
5886 /* Everything's already locked, -EDEADLK can't happen. */
5887 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5888 ret = drm_atomic_add_affected_connectors(state, crtc);
5889
5890 WARN_ON(IS_ERR(crtc_state) || ret);
5891
5892 dev_priv->display.crtc_disable(crtc_state, state);
5893
5894 drm_atomic_state_put(state);
5895
5896 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5897 crtc->base.id, crtc->name);
5898
5899 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5900 crtc->state->active = false;
5901 intel_crtc->active = false;
5902 crtc->enabled = false;
5903 crtc->state->connector_mask = 0;
5904 crtc->state->encoder_mask = 0;
5905
5906 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5907 encoder->base.crtc = NULL;
5908
5909 intel_fbc_disable(intel_crtc);
5910 intel_update_watermarks(intel_crtc);
5911 intel_disable_shared_dpll(intel_crtc);
5912
5913 domains = intel_crtc->enabled_power_domains;
5914 for_each_power_domain(domain, domains)
5915 intel_display_power_put(dev_priv, domain);
5916 intel_crtc->enabled_power_domains = 0;
5917
5918 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5919 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
5920 }
5921
5922 /*
5923 * turn all crtc's off, but do not adjust state
5924 * This has to be paired with a call to intel_modeset_setup_hw_state.
5925 */
5926 int intel_display_suspend(struct drm_device *dev)
5927 {
5928 struct drm_i915_private *dev_priv = to_i915(dev);
5929 struct drm_atomic_state *state;
5930 int ret;
5931
5932 state = drm_atomic_helper_suspend(dev);
5933 ret = PTR_ERR_OR_ZERO(state);
5934 if (ret)
5935 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5936 else
5937 dev_priv->modeset_restore_state = state;
5938 return ret;
5939 }
5940
5941 void intel_encoder_destroy(struct drm_encoder *encoder)
5942 {
5943 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5944
5945 drm_encoder_cleanup(encoder);
5946 kfree(intel_encoder);
5947 }
5948
5949 /* Cross check the actual hw state with our own modeset state tracking (and it's
5950 * internal consistency). */
5951 static void intel_connector_verify_state(struct intel_connector *connector)
5952 {
5953 struct drm_crtc *crtc = connector->base.state->crtc;
5954
5955 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5956 connector->base.base.id,
5957 connector->base.name);
5958
5959 if (connector->get_hw_state(connector)) {
5960 struct intel_encoder *encoder = connector->encoder;
5961 struct drm_connector_state *conn_state = connector->base.state;
5962
5963 I915_STATE_WARN(!crtc,
5964 "connector enabled without attached crtc\n");
5965
5966 if (!crtc)
5967 return;
5968
5969 I915_STATE_WARN(!crtc->state->active,
5970 "connector is active, but attached crtc isn't\n");
5971
5972 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
5973 return;
5974
5975 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
5976 "atomic encoder doesn't match attached encoder\n");
5977
5978 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
5979 "attached encoder crtc differs from connector crtc\n");
5980 } else {
5981 I915_STATE_WARN(crtc && crtc->state->active,
5982 "attached crtc is active, but connector isn't\n");
5983 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
5984 "best encoder set without crtc!\n");
5985 }
5986 }
5987
5988 int intel_connector_init(struct intel_connector *connector)
5989 {
5990 drm_atomic_helper_connector_reset(&connector->base);
5991
5992 if (!connector->base.state)
5993 return -ENOMEM;
5994
5995 return 0;
5996 }
5997
5998 struct intel_connector *intel_connector_alloc(void)
5999 {
6000 struct intel_connector *connector;
6001
6002 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6003 if (!connector)
6004 return NULL;
6005
6006 if (intel_connector_init(connector) < 0) {
6007 kfree(connector);
6008 return NULL;
6009 }
6010
6011 return connector;
6012 }
6013
6014 /* Simple connector->get_hw_state implementation for encoders that support only
6015 * one connector and no cloning and hence the encoder state determines the state
6016 * of the connector. */
6017 bool intel_connector_get_hw_state(struct intel_connector *connector)
6018 {
6019 enum pipe pipe = 0;
6020 struct intel_encoder *encoder = connector->encoder;
6021
6022 return encoder->get_hw_state(encoder, &pipe);
6023 }
6024
6025 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6026 {
6027 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6028 return crtc_state->fdi_lanes;
6029
6030 return 0;
6031 }
6032
6033 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6034 struct intel_crtc_state *pipe_config)
6035 {
6036 struct drm_i915_private *dev_priv = to_i915(dev);
6037 struct drm_atomic_state *state = pipe_config->base.state;
6038 struct intel_crtc *other_crtc;
6039 struct intel_crtc_state *other_crtc_state;
6040
6041 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6042 pipe_name(pipe), pipe_config->fdi_lanes);
6043 if (pipe_config->fdi_lanes > 4) {
6044 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6045 pipe_name(pipe), pipe_config->fdi_lanes);
6046 return -EINVAL;
6047 }
6048
6049 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6050 if (pipe_config->fdi_lanes > 2) {
6051 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6052 pipe_config->fdi_lanes);
6053 return -EINVAL;
6054 } else {
6055 return 0;
6056 }
6057 }
6058
6059 if (INTEL_INFO(dev_priv)->num_pipes == 2)
6060 return 0;
6061
6062 /* Ivybridge 3 pipe is really complicated */
6063 switch (pipe) {
6064 case PIPE_A:
6065 return 0;
6066 case PIPE_B:
6067 if (pipe_config->fdi_lanes <= 2)
6068 return 0;
6069
6070 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6071 other_crtc_state =
6072 intel_atomic_get_crtc_state(state, other_crtc);
6073 if (IS_ERR(other_crtc_state))
6074 return PTR_ERR(other_crtc_state);
6075
6076 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6077 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6078 pipe_name(pipe), pipe_config->fdi_lanes);
6079 return -EINVAL;
6080 }
6081 return 0;
6082 case PIPE_C:
6083 if (pipe_config->fdi_lanes > 2) {
6084 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6085 pipe_name(pipe), pipe_config->fdi_lanes);
6086 return -EINVAL;
6087 }
6088
6089 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6090 other_crtc_state =
6091 intel_atomic_get_crtc_state(state, other_crtc);
6092 if (IS_ERR(other_crtc_state))
6093 return PTR_ERR(other_crtc_state);
6094
6095 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6096 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6097 return -EINVAL;
6098 }
6099 return 0;
6100 default:
6101 BUG();
6102 }
6103 }
6104
6105 #define RETRY 1
6106 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6107 struct intel_crtc_state *pipe_config)
6108 {
6109 struct drm_device *dev = intel_crtc->base.dev;
6110 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6111 int lane, link_bw, fdi_dotclock, ret;
6112 bool needs_recompute = false;
6113
6114 retry:
6115 /* FDI is a binary signal running at ~2.7GHz, encoding
6116 * each output octet as 10 bits. The actual frequency
6117 * is stored as a divider into a 100MHz clock, and the
6118 * mode pixel clock is stored in units of 1KHz.
6119 * Hence the bw of each lane in terms of the mode signal
6120 * is:
6121 */
6122 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6123
6124 fdi_dotclock = adjusted_mode->crtc_clock;
6125
6126 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6127 pipe_config->pipe_bpp);
6128
6129 pipe_config->fdi_lanes = lane;
6130
6131 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6132 link_bw, &pipe_config->fdi_m_n);
6133
6134 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6135 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6136 pipe_config->pipe_bpp -= 2*3;
6137 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6138 pipe_config->pipe_bpp);
6139 needs_recompute = true;
6140 pipe_config->bw_constrained = true;
6141
6142 goto retry;
6143 }
6144
6145 if (needs_recompute)
6146 return RETRY;
6147
6148 return ret;
6149 }
6150
6151 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6152 struct intel_crtc_state *pipe_config)
6153 {
6154 if (pipe_config->pipe_bpp > 24)
6155 return false;
6156
6157 /* HSW can handle pixel rate up to cdclk? */
6158 if (IS_HASWELL(dev_priv))
6159 return true;
6160
6161 /*
6162 * We compare against max which means we must take
6163 * the increased cdclk requirement into account when
6164 * calculating the new cdclk.
6165 *
6166 * Should measure whether using a lower cdclk w/o IPS
6167 */
6168 return pipe_config->pixel_rate <=
6169 dev_priv->max_cdclk_freq * 95 / 100;
6170 }
6171
6172 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6173 struct intel_crtc_state *pipe_config)
6174 {
6175 struct drm_device *dev = crtc->base.dev;
6176 struct drm_i915_private *dev_priv = to_i915(dev);
6177
6178 pipe_config->ips_enabled = i915.enable_ips &&
6179 hsw_crtc_supports_ips(crtc) &&
6180 pipe_config_supports_ips(dev_priv, pipe_config);
6181 }
6182
6183 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6184 {
6185 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6186
6187 /* GDG double wide on either pipe, otherwise pipe A only */
6188 return INTEL_INFO(dev_priv)->gen < 4 &&
6189 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6190 }
6191
6192 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6193 {
6194 uint32_t pixel_rate;
6195
6196 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6197
6198 /*
6199 * We only use IF-ID interlacing. If we ever use
6200 * PF-ID we'll need to adjust the pixel_rate here.
6201 */
6202
6203 if (pipe_config->pch_pfit.enabled) {
6204 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6205 uint32_t pfit_size = pipe_config->pch_pfit.size;
6206
6207 pipe_w = pipe_config->pipe_src_w;
6208 pipe_h = pipe_config->pipe_src_h;
6209
6210 pfit_w = (pfit_size >> 16) & 0xFFFF;
6211 pfit_h = pfit_size & 0xFFFF;
6212 if (pipe_w < pfit_w)
6213 pipe_w = pfit_w;
6214 if (pipe_h < pfit_h)
6215 pipe_h = pfit_h;
6216
6217 if (WARN_ON(!pfit_w || !pfit_h))
6218 return pixel_rate;
6219
6220 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6221 pfit_w * pfit_h);
6222 }
6223
6224 return pixel_rate;
6225 }
6226
6227 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6228 {
6229 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6230
6231 if (HAS_GMCH_DISPLAY(dev_priv))
6232 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6233 crtc_state->pixel_rate =
6234 crtc_state->base.adjusted_mode.crtc_clock;
6235 else
6236 crtc_state->pixel_rate =
6237 ilk_pipe_pixel_rate(crtc_state);
6238 }
6239
6240 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6241 struct intel_crtc_state *pipe_config)
6242 {
6243 struct drm_device *dev = crtc->base.dev;
6244 struct drm_i915_private *dev_priv = to_i915(dev);
6245 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6246 int clock_limit = dev_priv->max_dotclk_freq;
6247
6248 if (INTEL_GEN(dev_priv) < 4) {
6249 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6250
6251 /*
6252 * Enable double wide mode when the dot clock
6253 * is > 90% of the (display) core speed.
6254 */
6255 if (intel_crtc_supports_double_wide(crtc) &&
6256 adjusted_mode->crtc_clock > clock_limit) {
6257 clock_limit = dev_priv->max_dotclk_freq;
6258 pipe_config->double_wide = true;
6259 }
6260 }
6261
6262 if (adjusted_mode->crtc_clock > clock_limit) {
6263 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6264 adjusted_mode->crtc_clock, clock_limit,
6265 yesno(pipe_config->double_wide));
6266 return -EINVAL;
6267 }
6268
6269 /*
6270 * Pipe horizontal size must be even in:
6271 * - DVO ganged mode
6272 * - LVDS dual channel mode
6273 * - Double wide pipe
6274 */
6275 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6276 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6277 pipe_config->pipe_src_w &= ~1;
6278
6279 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6280 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6281 */
6282 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6283 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6284 return -EINVAL;
6285
6286 intel_crtc_compute_pixel_rate(pipe_config);
6287
6288 if (HAS_IPS(dev_priv))
6289 hsw_compute_ips_config(crtc, pipe_config);
6290
6291 if (pipe_config->has_pch_encoder)
6292 return ironlake_fdi_compute_config(crtc, pipe_config);
6293
6294 return 0;
6295 }
6296
6297 static void
6298 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6299 {
6300 while (*num > DATA_LINK_M_N_MASK ||
6301 *den > DATA_LINK_M_N_MASK) {
6302 *num >>= 1;
6303 *den >>= 1;
6304 }
6305 }
6306
6307 static void compute_m_n(unsigned int m, unsigned int n,
6308 uint32_t *ret_m, uint32_t *ret_n)
6309 {
6310 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6311 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6312 intel_reduce_m_n_ratio(ret_m, ret_n);
6313 }
6314
6315 void
6316 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6317 int pixel_clock, int link_clock,
6318 struct intel_link_m_n *m_n)
6319 {
6320 m_n->tu = 64;
6321
6322 compute_m_n(bits_per_pixel * pixel_clock,
6323 link_clock * nlanes * 8,
6324 &m_n->gmch_m, &m_n->gmch_n);
6325
6326 compute_m_n(pixel_clock, link_clock,
6327 &m_n->link_m, &m_n->link_n);
6328 }
6329
6330 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6331 {
6332 if (i915.panel_use_ssc >= 0)
6333 return i915.panel_use_ssc != 0;
6334 return dev_priv->vbt.lvds_use_ssc
6335 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6336 }
6337
6338 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6339 {
6340 return (1 << dpll->n) << 16 | dpll->m2;
6341 }
6342
6343 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6344 {
6345 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6346 }
6347
6348 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6349 struct intel_crtc_state *crtc_state,
6350 struct dpll *reduced_clock)
6351 {
6352 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6353 u32 fp, fp2 = 0;
6354
6355 if (IS_PINEVIEW(dev_priv)) {
6356 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6357 if (reduced_clock)
6358 fp2 = pnv_dpll_compute_fp(reduced_clock);
6359 } else {
6360 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6361 if (reduced_clock)
6362 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6363 }
6364
6365 crtc_state->dpll_hw_state.fp0 = fp;
6366
6367 crtc->lowfreq_avail = false;
6368 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6369 reduced_clock) {
6370 crtc_state->dpll_hw_state.fp1 = fp2;
6371 crtc->lowfreq_avail = true;
6372 } else {
6373 crtc_state->dpll_hw_state.fp1 = fp;
6374 }
6375 }
6376
6377 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6378 pipe)
6379 {
6380 u32 reg_val;
6381
6382 /*
6383 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6384 * and set it to a reasonable value instead.
6385 */
6386 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6387 reg_val &= 0xffffff00;
6388 reg_val |= 0x00000030;
6389 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6390
6391 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6392 reg_val &= 0x8cffffff;
6393 reg_val = 0x8c000000;
6394 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6395
6396 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6397 reg_val &= 0xffffff00;
6398 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6399
6400 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6401 reg_val &= 0x00ffffff;
6402 reg_val |= 0xb0000000;
6403 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6404 }
6405
6406 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6407 struct intel_link_m_n *m_n)
6408 {
6409 struct drm_device *dev = crtc->base.dev;
6410 struct drm_i915_private *dev_priv = to_i915(dev);
6411 int pipe = crtc->pipe;
6412
6413 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6414 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6415 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6416 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6417 }
6418
6419 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6420 struct intel_link_m_n *m_n,
6421 struct intel_link_m_n *m2_n2)
6422 {
6423 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6424 int pipe = crtc->pipe;
6425 enum transcoder transcoder = crtc->config->cpu_transcoder;
6426
6427 if (INTEL_GEN(dev_priv) >= 5) {
6428 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6429 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6430 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6431 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6432 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6433 * for gen < 8) and if DRRS is supported (to make sure the
6434 * registers are not unnecessarily accessed).
6435 */
6436 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6437 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6438 I915_WRITE(PIPE_DATA_M2(transcoder),
6439 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6440 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6441 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6442 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6443 }
6444 } else {
6445 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6446 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6447 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6448 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6449 }
6450 }
6451
6452 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6453 {
6454 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6455
6456 if (m_n == M1_N1) {
6457 dp_m_n = &crtc->config->dp_m_n;
6458 dp_m2_n2 = &crtc->config->dp_m2_n2;
6459 } else if (m_n == M2_N2) {
6460
6461 /*
6462 * M2_N2 registers are not supported. Hence m2_n2 divider value
6463 * needs to be programmed into M1_N1.
6464 */
6465 dp_m_n = &crtc->config->dp_m2_n2;
6466 } else {
6467 DRM_ERROR("Unsupported divider value\n");
6468 return;
6469 }
6470
6471 if (crtc->config->has_pch_encoder)
6472 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6473 else
6474 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6475 }
6476
6477 static void vlv_compute_dpll(struct intel_crtc *crtc,
6478 struct intel_crtc_state *pipe_config)
6479 {
6480 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6481 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6482 if (crtc->pipe != PIPE_A)
6483 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6484
6485 /* DPLL not used with DSI, but still need the rest set up */
6486 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6487 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6488 DPLL_EXT_BUFFER_ENABLE_VLV;
6489
6490 pipe_config->dpll_hw_state.dpll_md =
6491 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6492 }
6493
6494 static void chv_compute_dpll(struct intel_crtc *crtc,
6495 struct intel_crtc_state *pipe_config)
6496 {
6497 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6498 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6499 if (crtc->pipe != PIPE_A)
6500 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6501
6502 /* DPLL not used with DSI, but still need the rest set up */
6503 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6504 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6505
6506 pipe_config->dpll_hw_state.dpll_md =
6507 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6508 }
6509
6510 static void vlv_prepare_pll(struct intel_crtc *crtc,
6511 const struct intel_crtc_state *pipe_config)
6512 {
6513 struct drm_device *dev = crtc->base.dev;
6514 struct drm_i915_private *dev_priv = to_i915(dev);
6515 enum pipe pipe = crtc->pipe;
6516 u32 mdiv;
6517 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6518 u32 coreclk, reg_val;
6519
6520 /* Enable Refclk */
6521 I915_WRITE(DPLL(pipe),
6522 pipe_config->dpll_hw_state.dpll &
6523 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6524
6525 /* No need to actually set up the DPLL with DSI */
6526 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6527 return;
6528
6529 mutex_lock(&dev_priv->sb_lock);
6530
6531 bestn = pipe_config->dpll.n;
6532 bestm1 = pipe_config->dpll.m1;
6533 bestm2 = pipe_config->dpll.m2;
6534 bestp1 = pipe_config->dpll.p1;
6535 bestp2 = pipe_config->dpll.p2;
6536
6537 /* See eDP HDMI DPIO driver vbios notes doc */
6538
6539 /* PLL B needs special handling */
6540 if (pipe == PIPE_B)
6541 vlv_pllb_recal_opamp(dev_priv, pipe);
6542
6543 /* Set up Tx target for periodic Rcomp update */
6544 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6545
6546 /* Disable target IRef on PLL */
6547 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6548 reg_val &= 0x00ffffff;
6549 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6550
6551 /* Disable fast lock */
6552 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6553
6554 /* Set idtafcrecal before PLL is enabled */
6555 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6556 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6557 mdiv |= ((bestn << DPIO_N_SHIFT));
6558 mdiv |= (1 << DPIO_K_SHIFT);
6559
6560 /*
6561 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6562 * but we don't support that).
6563 * Note: don't use the DAC post divider as it seems unstable.
6564 */
6565 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6566 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6567
6568 mdiv |= DPIO_ENABLE_CALIBRATION;
6569 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6570
6571 /* Set HBR and RBR LPF coefficients */
6572 if (pipe_config->port_clock == 162000 ||
6573 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6574 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6575 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6576 0x009f0003);
6577 else
6578 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6579 0x00d0000f);
6580
6581 if (intel_crtc_has_dp_encoder(pipe_config)) {
6582 /* Use SSC source */
6583 if (pipe == PIPE_A)
6584 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6585 0x0df40000);
6586 else
6587 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6588 0x0df70000);
6589 } else { /* HDMI or VGA */
6590 /* Use bend source */
6591 if (pipe == PIPE_A)
6592 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6593 0x0df70000);
6594 else
6595 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6596 0x0df40000);
6597 }
6598
6599 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6600 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6601 if (intel_crtc_has_dp_encoder(crtc->config))
6602 coreclk |= 0x01000000;
6603 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6604
6605 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6606 mutex_unlock(&dev_priv->sb_lock);
6607 }
6608
6609 static void chv_prepare_pll(struct intel_crtc *crtc,
6610 const struct intel_crtc_state *pipe_config)
6611 {
6612 struct drm_device *dev = crtc->base.dev;
6613 struct drm_i915_private *dev_priv = to_i915(dev);
6614 enum pipe pipe = crtc->pipe;
6615 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6616 u32 loopfilter, tribuf_calcntr;
6617 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6618 u32 dpio_val;
6619 int vco;
6620
6621 /* Enable Refclk and SSC */
6622 I915_WRITE(DPLL(pipe),
6623 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6624
6625 /* No need to actually set up the DPLL with DSI */
6626 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6627 return;
6628
6629 bestn = pipe_config->dpll.n;
6630 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6631 bestm1 = pipe_config->dpll.m1;
6632 bestm2 = pipe_config->dpll.m2 >> 22;
6633 bestp1 = pipe_config->dpll.p1;
6634 bestp2 = pipe_config->dpll.p2;
6635 vco = pipe_config->dpll.vco;
6636 dpio_val = 0;
6637 loopfilter = 0;
6638
6639 mutex_lock(&dev_priv->sb_lock);
6640
6641 /* p1 and p2 divider */
6642 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6643 5 << DPIO_CHV_S1_DIV_SHIFT |
6644 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6645 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6646 1 << DPIO_CHV_K_DIV_SHIFT);
6647
6648 /* Feedback post-divider - m2 */
6649 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6650
6651 /* Feedback refclk divider - n and m1 */
6652 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6653 DPIO_CHV_M1_DIV_BY_2 |
6654 1 << DPIO_CHV_N_DIV_SHIFT);
6655
6656 /* M2 fraction division */
6657 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6658
6659 /* M2 fraction division enable */
6660 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6661 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6662 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6663 if (bestm2_frac)
6664 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6665 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6666
6667 /* Program digital lock detect threshold */
6668 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6669 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6670 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6671 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6672 if (!bestm2_frac)
6673 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6674 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6675
6676 /* Loop filter */
6677 if (vco == 5400000) {
6678 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6679 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6680 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6681 tribuf_calcntr = 0x9;
6682 } else if (vco <= 6200000) {
6683 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6684 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6685 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6686 tribuf_calcntr = 0x9;
6687 } else if (vco <= 6480000) {
6688 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6689 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6690 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6691 tribuf_calcntr = 0x8;
6692 } else {
6693 /* Not supported. Apply the same limits as in the max case */
6694 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6695 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6696 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6697 tribuf_calcntr = 0;
6698 }
6699 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6700
6701 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6702 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6703 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6704 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6705
6706 /* AFC Recal */
6707 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6708 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6709 DPIO_AFC_RECAL);
6710
6711 mutex_unlock(&dev_priv->sb_lock);
6712 }
6713
6714 /**
6715 * vlv_force_pll_on - forcibly enable just the PLL
6716 * @dev_priv: i915 private structure
6717 * @pipe: pipe PLL to enable
6718 * @dpll: PLL configuration
6719 *
6720 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6721 * in cases where we need the PLL enabled even when @pipe is not going to
6722 * be enabled.
6723 */
6724 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6725 const struct dpll *dpll)
6726 {
6727 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6728 struct intel_crtc_state *pipe_config;
6729
6730 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6731 if (!pipe_config)
6732 return -ENOMEM;
6733
6734 pipe_config->base.crtc = &crtc->base;
6735 pipe_config->pixel_multiplier = 1;
6736 pipe_config->dpll = *dpll;
6737
6738 if (IS_CHERRYVIEW(dev_priv)) {
6739 chv_compute_dpll(crtc, pipe_config);
6740 chv_prepare_pll(crtc, pipe_config);
6741 chv_enable_pll(crtc, pipe_config);
6742 } else {
6743 vlv_compute_dpll(crtc, pipe_config);
6744 vlv_prepare_pll(crtc, pipe_config);
6745 vlv_enable_pll(crtc, pipe_config);
6746 }
6747
6748 kfree(pipe_config);
6749
6750 return 0;
6751 }
6752
6753 /**
6754 * vlv_force_pll_off - forcibly disable just the PLL
6755 * @dev_priv: i915 private structure
6756 * @pipe: pipe PLL to disable
6757 *
6758 * Disable the PLL for @pipe. To be used in cases where we need
6759 * the PLL enabled even when @pipe is not going to be enabled.
6760 */
6761 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6762 {
6763 if (IS_CHERRYVIEW(dev_priv))
6764 chv_disable_pll(dev_priv, pipe);
6765 else
6766 vlv_disable_pll(dev_priv, pipe);
6767 }
6768
6769 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6770 struct intel_crtc_state *crtc_state,
6771 struct dpll *reduced_clock)
6772 {
6773 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6774 u32 dpll;
6775 struct dpll *clock = &crtc_state->dpll;
6776
6777 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6778
6779 dpll = DPLL_VGA_MODE_DIS;
6780
6781 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6782 dpll |= DPLLB_MODE_LVDS;
6783 else
6784 dpll |= DPLLB_MODE_DAC_SERIAL;
6785
6786 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6787 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6788 dpll |= (crtc_state->pixel_multiplier - 1)
6789 << SDVO_MULTIPLIER_SHIFT_HIRES;
6790 }
6791
6792 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6793 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6794 dpll |= DPLL_SDVO_HIGH_SPEED;
6795
6796 if (intel_crtc_has_dp_encoder(crtc_state))
6797 dpll |= DPLL_SDVO_HIGH_SPEED;
6798
6799 /* compute bitmask from p1 value */
6800 if (IS_PINEVIEW(dev_priv))
6801 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6802 else {
6803 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6804 if (IS_G4X(dev_priv) && reduced_clock)
6805 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6806 }
6807 switch (clock->p2) {
6808 case 5:
6809 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6810 break;
6811 case 7:
6812 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6813 break;
6814 case 10:
6815 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6816 break;
6817 case 14:
6818 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6819 break;
6820 }
6821 if (INTEL_GEN(dev_priv) >= 4)
6822 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6823
6824 if (crtc_state->sdvo_tv_clock)
6825 dpll |= PLL_REF_INPUT_TVCLKINBC;
6826 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6827 intel_panel_use_ssc(dev_priv))
6828 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6829 else
6830 dpll |= PLL_REF_INPUT_DREFCLK;
6831
6832 dpll |= DPLL_VCO_ENABLE;
6833 crtc_state->dpll_hw_state.dpll = dpll;
6834
6835 if (INTEL_GEN(dev_priv) >= 4) {
6836 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6837 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6838 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6839 }
6840 }
6841
6842 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6843 struct intel_crtc_state *crtc_state,
6844 struct dpll *reduced_clock)
6845 {
6846 struct drm_device *dev = crtc->base.dev;
6847 struct drm_i915_private *dev_priv = to_i915(dev);
6848 u32 dpll;
6849 struct dpll *clock = &crtc_state->dpll;
6850
6851 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6852
6853 dpll = DPLL_VGA_MODE_DIS;
6854
6855 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6856 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6857 } else {
6858 if (clock->p1 == 2)
6859 dpll |= PLL_P1_DIVIDE_BY_TWO;
6860 else
6861 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6862 if (clock->p2 == 4)
6863 dpll |= PLL_P2_DIVIDE_BY_4;
6864 }
6865
6866 if (!IS_I830(dev_priv) &&
6867 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6868 dpll |= DPLL_DVO_2X_MODE;
6869
6870 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6871 intel_panel_use_ssc(dev_priv))
6872 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6873 else
6874 dpll |= PLL_REF_INPUT_DREFCLK;
6875
6876 dpll |= DPLL_VCO_ENABLE;
6877 crtc_state->dpll_hw_state.dpll = dpll;
6878 }
6879
6880 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6881 {
6882 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6883 enum pipe pipe = intel_crtc->pipe;
6884 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6885 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6886 uint32_t crtc_vtotal, crtc_vblank_end;
6887 int vsyncshift = 0;
6888
6889 /* We need to be careful not to changed the adjusted mode, for otherwise
6890 * the hw state checker will get angry at the mismatch. */
6891 crtc_vtotal = adjusted_mode->crtc_vtotal;
6892 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6893
6894 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6895 /* the chip adds 2 halflines automatically */
6896 crtc_vtotal -= 1;
6897 crtc_vblank_end -= 1;
6898
6899 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6900 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6901 else
6902 vsyncshift = adjusted_mode->crtc_hsync_start -
6903 adjusted_mode->crtc_htotal / 2;
6904 if (vsyncshift < 0)
6905 vsyncshift += adjusted_mode->crtc_htotal;
6906 }
6907
6908 if (INTEL_GEN(dev_priv) > 3)
6909 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6910
6911 I915_WRITE(HTOTAL(cpu_transcoder),
6912 (adjusted_mode->crtc_hdisplay - 1) |
6913 ((adjusted_mode->crtc_htotal - 1) << 16));
6914 I915_WRITE(HBLANK(cpu_transcoder),
6915 (adjusted_mode->crtc_hblank_start - 1) |
6916 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6917 I915_WRITE(HSYNC(cpu_transcoder),
6918 (adjusted_mode->crtc_hsync_start - 1) |
6919 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6920
6921 I915_WRITE(VTOTAL(cpu_transcoder),
6922 (adjusted_mode->crtc_vdisplay - 1) |
6923 ((crtc_vtotal - 1) << 16));
6924 I915_WRITE(VBLANK(cpu_transcoder),
6925 (adjusted_mode->crtc_vblank_start - 1) |
6926 ((crtc_vblank_end - 1) << 16));
6927 I915_WRITE(VSYNC(cpu_transcoder),
6928 (adjusted_mode->crtc_vsync_start - 1) |
6929 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6930
6931 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6932 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6933 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6934 * bits. */
6935 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
6936 (pipe == PIPE_B || pipe == PIPE_C))
6937 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6938
6939 }
6940
6941 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
6942 {
6943 struct drm_device *dev = intel_crtc->base.dev;
6944 struct drm_i915_private *dev_priv = to_i915(dev);
6945 enum pipe pipe = intel_crtc->pipe;
6946
6947 /* pipesrc controls the size that is scaled from, which should
6948 * always be the user's requested size.
6949 */
6950 I915_WRITE(PIPESRC(pipe),
6951 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6952 (intel_crtc->config->pipe_src_h - 1));
6953 }
6954
6955 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6956 struct intel_crtc_state *pipe_config)
6957 {
6958 struct drm_device *dev = crtc->base.dev;
6959 struct drm_i915_private *dev_priv = to_i915(dev);
6960 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6961 uint32_t tmp;
6962
6963 tmp = I915_READ(HTOTAL(cpu_transcoder));
6964 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6965 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6966 tmp = I915_READ(HBLANK(cpu_transcoder));
6967 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6968 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6969 tmp = I915_READ(HSYNC(cpu_transcoder));
6970 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6971 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6972
6973 tmp = I915_READ(VTOTAL(cpu_transcoder));
6974 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6975 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6976 tmp = I915_READ(VBLANK(cpu_transcoder));
6977 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6978 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6979 tmp = I915_READ(VSYNC(cpu_transcoder));
6980 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6981 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6982
6983 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6984 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6985 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6986 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6987 }
6988 }
6989
6990 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
6991 struct intel_crtc_state *pipe_config)
6992 {
6993 struct drm_device *dev = crtc->base.dev;
6994 struct drm_i915_private *dev_priv = to_i915(dev);
6995 u32 tmp;
6996
6997 tmp = I915_READ(PIPESRC(crtc->pipe));
6998 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6999 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7000
7001 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7002 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7003 }
7004
7005 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7006 struct intel_crtc_state *pipe_config)
7007 {
7008 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7009 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7010 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7011 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7012
7013 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7014 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7015 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7016 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7017
7018 mode->flags = pipe_config->base.adjusted_mode.flags;
7019 mode->type = DRM_MODE_TYPE_DRIVER;
7020
7021 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7022
7023 mode->hsync = drm_mode_hsync(mode);
7024 mode->vrefresh = drm_mode_vrefresh(mode);
7025 drm_mode_set_name(mode);
7026 }
7027
7028 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7029 {
7030 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7031 uint32_t pipeconf;
7032
7033 pipeconf = 0;
7034
7035 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7036 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7037 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7038
7039 if (intel_crtc->config->double_wide)
7040 pipeconf |= PIPECONF_DOUBLE_WIDE;
7041
7042 /* only g4x and later have fancy bpc/dither controls */
7043 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7044 IS_CHERRYVIEW(dev_priv)) {
7045 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7046 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7047 pipeconf |= PIPECONF_DITHER_EN |
7048 PIPECONF_DITHER_TYPE_SP;
7049
7050 switch (intel_crtc->config->pipe_bpp) {
7051 case 18:
7052 pipeconf |= PIPECONF_6BPC;
7053 break;
7054 case 24:
7055 pipeconf |= PIPECONF_8BPC;
7056 break;
7057 case 30:
7058 pipeconf |= PIPECONF_10BPC;
7059 break;
7060 default:
7061 /* Case prevented by intel_choose_pipe_bpp_dither. */
7062 BUG();
7063 }
7064 }
7065
7066 if (HAS_PIPE_CXSR(dev_priv)) {
7067 if (intel_crtc->lowfreq_avail) {
7068 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7069 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7070 } else {
7071 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7072 }
7073 }
7074
7075 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7076 if (INTEL_GEN(dev_priv) < 4 ||
7077 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7078 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7079 else
7080 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7081 } else
7082 pipeconf |= PIPECONF_PROGRESSIVE;
7083
7084 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7085 intel_crtc->config->limited_color_range)
7086 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7087
7088 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7089 POSTING_READ(PIPECONF(intel_crtc->pipe));
7090 }
7091
7092 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7093 struct intel_crtc_state *crtc_state)
7094 {
7095 struct drm_device *dev = crtc->base.dev;
7096 struct drm_i915_private *dev_priv = to_i915(dev);
7097 const struct intel_limit *limit;
7098 int refclk = 48000;
7099
7100 memset(&crtc_state->dpll_hw_state, 0,
7101 sizeof(crtc_state->dpll_hw_state));
7102
7103 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7104 if (intel_panel_use_ssc(dev_priv)) {
7105 refclk = dev_priv->vbt.lvds_ssc_freq;
7106 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7107 }
7108
7109 limit = &intel_limits_i8xx_lvds;
7110 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7111 limit = &intel_limits_i8xx_dvo;
7112 } else {
7113 limit = &intel_limits_i8xx_dac;
7114 }
7115
7116 if (!crtc_state->clock_set &&
7117 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7118 refclk, NULL, &crtc_state->dpll)) {
7119 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7120 return -EINVAL;
7121 }
7122
7123 i8xx_compute_dpll(crtc, crtc_state, NULL);
7124
7125 return 0;
7126 }
7127
7128 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7129 struct intel_crtc_state *crtc_state)
7130 {
7131 struct drm_device *dev = crtc->base.dev;
7132 struct drm_i915_private *dev_priv = to_i915(dev);
7133 const struct intel_limit *limit;
7134 int refclk = 96000;
7135
7136 memset(&crtc_state->dpll_hw_state, 0,
7137 sizeof(crtc_state->dpll_hw_state));
7138
7139 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7140 if (intel_panel_use_ssc(dev_priv)) {
7141 refclk = dev_priv->vbt.lvds_ssc_freq;
7142 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7143 }
7144
7145 if (intel_is_dual_link_lvds(dev))
7146 limit = &intel_limits_g4x_dual_channel_lvds;
7147 else
7148 limit = &intel_limits_g4x_single_channel_lvds;
7149 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7150 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7151 limit = &intel_limits_g4x_hdmi;
7152 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7153 limit = &intel_limits_g4x_sdvo;
7154 } else {
7155 /* The option is for other outputs */
7156 limit = &intel_limits_i9xx_sdvo;
7157 }
7158
7159 if (!crtc_state->clock_set &&
7160 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7161 refclk, NULL, &crtc_state->dpll)) {
7162 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7163 return -EINVAL;
7164 }
7165
7166 i9xx_compute_dpll(crtc, crtc_state, NULL);
7167
7168 return 0;
7169 }
7170
7171 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7172 struct intel_crtc_state *crtc_state)
7173 {
7174 struct drm_device *dev = crtc->base.dev;
7175 struct drm_i915_private *dev_priv = to_i915(dev);
7176 const struct intel_limit *limit;
7177 int refclk = 96000;
7178
7179 memset(&crtc_state->dpll_hw_state, 0,
7180 sizeof(crtc_state->dpll_hw_state));
7181
7182 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7183 if (intel_panel_use_ssc(dev_priv)) {
7184 refclk = dev_priv->vbt.lvds_ssc_freq;
7185 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7186 }
7187
7188 limit = &intel_limits_pineview_lvds;
7189 } else {
7190 limit = &intel_limits_pineview_sdvo;
7191 }
7192
7193 if (!crtc_state->clock_set &&
7194 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7195 refclk, NULL, &crtc_state->dpll)) {
7196 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7197 return -EINVAL;
7198 }
7199
7200 i9xx_compute_dpll(crtc, crtc_state, NULL);
7201
7202 return 0;
7203 }
7204
7205 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7206 struct intel_crtc_state *crtc_state)
7207 {
7208 struct drm_device *dev = crtc->base.dev;
7209 struct drm_i915_private *dev_priv = to_i915(dev);
7210 const struct intel_limit *limit;
7211 int refclk = 96000;
7212
7213 memset(&crtc_state->dpll_hw_state, 0,
7214 sizeof(crtc_state->dpll_hw_state));
7215
7216 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7217 if (intel_panel_use_ssc(dev_priv)) {
7218 refclk = dev_priv->vbt.lvds_ssc_freq;
7219 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7220 }
7221
7222 limit = &intel_limits_i9xx_lvds;
7223 } else {
7224 limit = &intel_limits_i9xx_sdvo;
7225 }
7226
7227 if (!crtc_state->clock_set &&
7228 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7229 refclk, NULL, &crtc_state->dpll)) {
7230 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7231 return -EINVAL;
7232 }
7233
7234 i9xx_compute_dpll(crtc, crtc_state, NULL);
7235
7236 return 0;
7237 }
7238
7239 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7240 struct intel_crtc_state *crtc_state)
7241 {
7242 int refclk = 100000;
7243 const struct intel_limit *limit = &intel_limits_chv;
7244
7245 memset(&crtc_state->dpll_hw_state, 0,
7246 sizeof(crtc_state->dpll_hw_state));
7247
7248 if (!crtc_state->clock_set &&
7249 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7250 refclk, NULL, &crtc_state->dpll)) {
7251 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7252 return -EINVAL;
7253 }
7254
7255 chv_compute_dpll(crtc, crtc_state);
7256
7257 return 0;
7258 }
7259
7260 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7261 struct intel_crtc_state *crtc_state)
7262 {
7263 int refclk = 100000;
7264 const struct intel_limit *limit = &intel_limits_vlv;
7265
7266 memset(&crtc_state->dpll_hw_state, 0,
7267 sizeof(crtc_state->dpll_hw_state));
7268
7269 if (!crtc_state->clock_set &&
7270 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7271 refclk, NULL, &crtc_state->dpll)) {
7272 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7273 return -EINVAL;
7274 }
7275
7276 vlv_compute_dpll(crtc, crtc_state);
7277
7278 return 0;
7279 }
7280
7281 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7282 struct intel_crtc_state *pipe_config)
7283 {
7284 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7285 uint32_t tmp;
7286
7287 if (INTEL_GEN(dev_priv) <= 3 &&
7288 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7289 return;
7290
7291 tmp = I915_READ(PFIT_CONTROL);
7292 if (!(tmp & PFIT_ENABLE))
7293 return;
7294
7295 /* Check whether the pfit is attached to our pipe. */
7296 if (INTEL_GEN(dev_priv) < 4) {
7297 if (crtc->pipe != PIPE_B)
7298 return;
7299 } else {
7300 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7301 return;
7302 }
7303
7304 pipe_config->gmch_pfit.control = tmp;
7305 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7306 }
7307
7308 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7309 struct intel_crtc_state *pipe_config)
7310 {
7311 struct drm_device *dev = crtc->base.dev;
7312 struct drm_i915_private *dev_priv = to_i915(dev);
7313 int pipe = pipe_config->cpu_transcoder;
7314 struct dpll clock;
7315 u32 mdiv;
7316 int refclk = 100000;
7317
7318 /* In case of DSI, DPLL will not be used */
7319 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7320 return;
7321
7322 mutex_lock(&dev_priv->sb_lock);
7323 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7324 mutex_unlock(&dev_priv->sb_lock);
7325
7326 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7327 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7328 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7329 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7330 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7331
7332 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7333 }
7334
7335 static void
7336 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7337 struct intel_initial_plane_config *plane_config)
7338 {
7339 struct drm_device *dev = crtc->base.dev;
7340 struct drm_i915_private *dev_priv = to_i915(dev);
7341 u32 val, base, offset;
7342 int pipe = crtc->pipe, plane = crtc->plane;
7343 int fourcc, pixel_format;
7344 unsigned int aligned_height;
7345 struct drm_framebuffer *fb;
7346 struct intel_framebuffer *intel_fb;
7347
7348 val = I915_READ(DSPCNTR(plane));
7349 if (!(val & DISPLAY_PLANE_ENABLE))
7350 return;
7351
7352 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7353 if (!intel_fb) {
7354 DRM_DEBUG_KMS("failed to alloc fb\n");
7355 return;
7356 }
7357
7358 fb = &intel_fb->base;
7359
7360 fb->dev = dev;
7361
7362 if (INTEL_GEN(dev_priv) >= 4) {
7363 if (val & DISPPLANE_TILED) {
7364 plane_config->tiling = I915_TILING_X;
7365 fb->modifier = I915_FORMAT_MOD_X_TILED;
7366 }
7367 }
7368
7369 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7370 fourcc = i9xx_format_to_fourcc(pixel_format);
7371 fb->format = drm_format_info(fourcc);
7372
7373 if (INTEL_GEN(dev_priv) >= 4) {
7374 if (plane_config->tiling)
7375 offset = I915_READ(DSPTILEOFF(plane));
7376 else
7377 offset = I915_READ(DSPLINOFF(plane));
7378 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7379 } else {
7380 base = I915_READ(DSPADDR(plane));
7381 }
7382 plane_config->base = base;
7383
7384 val = I915_READ(PIPESRC(pipe));
7385 fb->width = ((val >> 16) & 0xfff) + 1;
7386 fb->height = ((val >> 0) & 0xfff) + 1;
7387
7388 val = I915_READ(DSPSTRIDE(pipe));
7389 fb->pitches[0] = val & 0xffffffc0;
7390
7391 aligned_height = intel_fb_align_height(dev_priv,
7392 fb->height,
7393 fb->format->format,
7394 fb->modifier);
7395
7396 plane_config->size = fb->pitches[0] * aligned_height;
7397
7398 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7399 pipe_name(pipe), plane, fb->width, fb->height,
7400 fb->format->cpp[0] * 8, base, fb->pitches[0],
7401 plane_config->size);
7402
7403 plane_config->fb = intel_fb;
7404 }
7405
7406 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7407 struct intel_crtc_state *pipe_config)
7408 {
7409 struct drm_device *dev = crtc->base.dev;
7410 struct drm_i915_private *dev_priv = to_i915(dev);
7411 int pipe = pipe_config->cpu_transcoder;
7412 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7413 struct dpll clock;
7414 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7415 int refclk = 100000;
7416
7417 /* In case of DSI, DPLL will not be used */
7418 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7419 return;
7420
7421 mutex_lock(&dev_priv->sb_lock);
7422 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7423 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7424 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7425 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7426 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7427 mutex_unlock(&dev_priv->sb_lock);
7428
7429 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7430 clock.m2 = (pll_dw0 & 0xff) << 22;
7431 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7432 clock.m2 |= pll_dw2 & 0x3fffff;
7433 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7434 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7435 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7436
7437 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7438 }
7439
7440 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7441 struct intel_crtc_state *pipe_config)
7442 {
7443 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7444 enum intel_display_power_domain power_domain;
7445 uint32_t tmp;
7446 bool ret;
7447
7448 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7449 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7450 return false;
7451
7452 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7453 pipe_config->shared_dpll = NULL;
7454
7455 ret = false;
7456
7457 tmp = I915_READ(PIPECONF(crtc->pipe));
7458 if (!(tmp & PIPECONF_ENABLE))
7459 goto out;
7460
7461 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7462 IS_CHERRYVIEW(dev_priv)) {
7463 switch (tmp & PIPECONF_BPC_MASK) {
7464 case PIPECONF_6BPC:
7465 pipe_config->pipe_bpp = 18;
7466 break;
7467 case PIPECONF_8BPC:
7468 pipe_config->pipe_bpp = 24;
7469 break;
7470 case PIPECONF_10BPC:
7471 pipe_config->pipe_bpp = 30;
7472 break;
7473 default:
7474 break;
7475 }
7476 }
7477
7478 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7479 (tmp & PIPECONF_COLOR_RANGE_SELECT))
7480 pipe_config->limited_color_range = true;
7481
7482 if (INTEL_GEN(dev_priv) < 4)
7483 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7484
7485 intel_get_pipe_timings(crtc, pipe_config);
7486 intel_get_pipe_src_size(crtc, pipe_config);
7487
7488 i9xx_get_pfit_config(crtc, pipe_config);
7489
7490 if (INTEL_GEN(dev_priv) >= 4) {
7491 /* No way to read it out on pipes B and C */
7492 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7493 tmp = dev_priv->chv_dpll_md[crtc->pipe];
7494 else
7495 tmp = I915_READ(DPLL_MD(crtc->pipe));
7496 pipe_config->pixel_multiplier =
7497 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7498 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7499 pipe_config->dpll_hw_state.dpll_md = tmp;
7500 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7501 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7502 tmp = I915_READ(DPLL(crtc->pipe));
7503 pipe_config->pixel_multiplier =
7504 ((tmp & SDVO_MULTIPLIER_MASK)
7505 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7506 } else {
7507 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7508 * port and will be fixed up in the encoder->get_config
7509 * function. */
7510 pipe_config->pixel_multiplier = 1;
7511 }
7512 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7513 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7514 /*
7515 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7516 * on 830. Filter it out here so that we don't
7517 * report errors due to that.
7518 */
7519 if (IS_I830(dev_priv))
7520 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7521
7522 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7523 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7524 } else {
7525 /* Mask out read-only status bits. */
7526 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7527 DPLL_PORTC_READY_MASK |
7528 DPLL_PORTB_READY_MASK);
7529 }
7530
7531 if (IS_CHERRYVIEW(dev_priv))
7532 chv_crtc_clock_get(crtc, pipe_config);
7533 else if (IS_VALLEYVIEW(dev_priv))
7534 vlv_crtc_clock_get(crtc, pipe_config);
7535 else
7536 i9xx_crtc_clock_get(crtc, pipe_config);
7537
7538 /*
7539 * Normally the dotclock is filled in by the encoder .get_config()
7540 * but in case the pipe is enabled w/o any ports we need a sane
7541 * default.
7542 */
7543 pipe_config->base.adjusted_mode.crtc_clock =
7544 pipe_config->port_clock / pipe_config->pixel_multiplier;
7545
7546 ret = true;
7547
7548 out:
7549 intel_display_power_put(dev_priv, power_domain);
7550
7551 return ret;
7552 }
7553
7554 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7555 {
7556 struct intel_encoder *encoder;
7557 int i;
7558 u32 val, final;
7559 bool has_lvds = false;
7560 bool has_cpu_edp = false;
7561 bool has_panel = false;
7562 bool has_ck505 = false;
7563 bool can_ssc = false;
7564 bool using_ssc_source = false;
7565
7566 /* We need to take the global config into account */
7567 for_each_intel_encoder(&dev_priv->drm, encoder) {
7568 switch (encoder->type) {
7569 case INTEL_OUTPUT_LVDS:
7570 has_panel = true;
7571 has_lvds = true;
7572 break;
7573 case INTEL_OUTPUT_EDP:
7574 has_panel = true;
7575 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7576 has_cpu_edp = true;
7577 break;
7578 default:
7579 break;
7580 }
7581 }
7582
7583 if (HAS_PCH_IBX(dev_priv)) {
7584 has_ck505 = dev_priv->vbt.display_clock_mode;
7585 can_ssc = has_ck505;
7586 } else {
7587 has_ck505 = false;
7588 can_ssc = true;
7589 }
7590
7591 /* Check if any DPLLs are using the SSC source */
7592 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7593 u32 temp = I915_READ(PCH_DPLL(i));
7594
7595 if (!(temp & DPLL_VCO_ENABLE))
7596 continue;
7597
7598 if ((temp & PLL_REF_INPUT_MASK) ==
7599 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7600 using_ssc_source = true;
7601 break;
7602 }
7603 }
7604
7605 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7606 has_panel, has_lvds, has_ck505, using_ssc_source);
7607
7608 /* Ironlake: try to setup display ref clock before DPLL
7609 * enabling. This is only under driver's control after
7610 * PCH B stepping, previous chipset stepping should be
7611 * ignoring this setting.
7612 */
7613 val = I915_READ(PCH_DREF_CONTROL);
7614
7615 /* As we must carefully and slowly disable/enable each source in turn,
7616 * compute the final state we want first and check if we need to
7617 * make any changes at all.
7618 */
7619 final = val;
7620 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7621 if (has_ck505)
7622 final |= DREF_NONSPREAD_CK505_ENABLE;
7623 else
7624 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7625
7626 final &= ~DREF_SSC_SOURCE_MASK;
7627 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7628 final &= ~DREF_SSC1_ENABLE;
7629
7630 if (has_panel) {
7631 final |= DREF_SSC_SOURCE_ENABLE;
7632
7633 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7634 final |= DREF_SSC1_ENABLE;
7635
7636 if (has_cpu_edp) {
7637 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7638 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7639 else
7640 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7641 } else
7642 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7643 } else if (using_ssc_source) {
7644 final |= DREF_SSC_SOURCE_ENABLE;
7645 final |= DREF_SSC1_ENABLE;
7646 }
7647
7648 if (final == val)
7649 return;
7650
7651 /* Always enable nonspread source */
7652 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7653
7654 if (has_ck505)
7655 val |= DREF_NONSPREAD_CK505_ENABLE;
7656 else
7657 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7658
7659 if (has_panel) {
7660 val &= ~DREF_SSC_SOURCE_MASK;
7661 val |= DREF_SSC_SOURCE_ENABLE;
7662
7663 /* SSC must be turned on before enabling the CPU output */
7664 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7665 DRM_DEBUG_KMS("Using SSC on panel\n");
7666 val |= DREF_SSC1_ENABLE;
7667 } else
7668 val &= ~DREF_SSC1_ENABLE;
7669
7670 /* Get SSC going before enabling the outputs */
7671 I915_WRITE(PCH_DREF_CONTROL, val);
7672 POSTING_READ(PCH_DREF_CONTROL);
7673 udelay(200);
7674
7675 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7676
7677 /* Enable CPU source on CPU attached eDP */
7678 if (has_cpu_edp) {
7679 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7680 DRM_DEBUG_KMS("Using SSC on eDP\n");
7681 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7682 } else
7683 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7684 } else
7685 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7686
7687 I915_WRITE(PCH_DREF_CONTROL, val);
7688 POSTING_READ(PCH_DREF_CONTROL);
7689 udelay(200);
7690 } else {
7691 DRM_DEBUG_KMS("Disabling CPU source output\n");
7692
7693 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7694
7695 /* Turn off CPU output */
7696 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7697
7698 I915_WRITE(PCH_DREF_CONTROL, val);
7699 POSTING_READ(PCH_DREF_CONTROL);
7700 udelay(200);
7701
7702 if (!using_ssc_source) {
7703 DRM_DEBUG_KMS("Disabling SSC source\n");
7704
7705 /* Turn off the SSC source */
7706 val &= ~DREF_SSC_SOURCE_MASK;
7707 val |= DREF_SSC_SOURCE_DISABLE;
7708
7709 /* Turn off SSC1 */
7710 val &= ~DREF_SSC1_ENABLE;
7711
7712 I915_WRITE(PCH_DREF_CONTROL, val);
7713 POSTING_READ(PCH_DREF_CONTROL);
7714 udelay(200);
7715 }
7716 }
7717
7718 BUG_ON(val != final);
7719 }
7720
7721 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7722 {
7723 uint32_t tmp;
7724
7725 tmp = I915_READ(SOUTH_CHICKEN2);
7726 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7727 I915_WRITE(SOUTH_CHICKEN2, tmp);
7728
7729 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7730 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7731 DRM_ERROR("FDI mPHY reset assert timeout\n");
7732
7733 tmp = I915_READ(SOUTH_CHICKEN2);
7734 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7735 I915_WRITE(SOUTH_CHICKEN2, tmp);
7736
7737 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7738 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7739 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7740 }
7741
7742 /* WaMPhyProgramming:hsw */
7743 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7744 {
7745 uint32_t tmp;
7746
7747 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7748 tmp &= ~(0xFF << 24);
7749 tmp |= (0x12 << 24);
7750 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7751
7752 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7753 tmp |= (1 << 11);
7754 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7755
7756 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7757 tmp |= (1 << 11);
7758 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7759
7760 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7761 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7762 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7763
7764 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7765 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7766 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7767
7768 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7769 tmp &= ~(7 << 13);
7770 tmp |= (5 << 13);
7771 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7772
7773 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7774 tmp &= ~(7 << 13);
7775 tmp |= (5 << 13);
7776 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7777
7778 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7779 tmp &= ~0xFF;
7780 tmp |= 0x1C;
7781 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7782
7783 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7784 tmp &= ~0xFF;
7785 tmp |= 0x1C;
7786 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7787
7788 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7789 tmp &= ~(0xFF << 16);
7790 tmp |= (0x1C << 16);
7791 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7792
7793 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7794 tmp &= ~(0xFF << 16);
7795 tmp |= (0x1C << 16);
7796 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7797
7798 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7799 tmp |= (1 << 27);
7800 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7801
7802 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7803 tmp |= (1 << 27);
7804 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7805
7806 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7807 tmp &= ~(0xF << 28);
7808 tmp |= (4 << 28);
7809 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7810
7811 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7812 tmp &= ~(0xF << 28);
7813 tmp |= (4 << 28);
7814 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7815 }
7816
7817 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7818 * Programming" based on the parameters passed:
7819 * - Sequence to enable CLKOUT_DP
7820 * - Sequence to enable CLKOUT_DP without spread
7821 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7822 */
7823 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7824 bool with_spread, bool with_fdi)
7825 {
7826 uint32_t reg, tmp;
7827
7828 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7829 with_spread = true;
7830 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7831 with_fdi, "LP PCH doesn't have FDI\n"))
7832 with_fdi = false;
7833
7834 mutex_lock(&dev_priv->sb_lock);
7835
7836 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7837 tmp &= ~SBI_SSCCTL_DISABLE;
7838 tmp |= SBI_SSCCTL_PATHALT;
7839 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7840
7841 udelay(24);
7842
7843 if (with_spread) {
7844 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7845 tmp &= ~SBI_SSCCTL_PATHALT;
7846 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7847
7848 if (with_fdi) {
7849 lpt_reset_fdi_mphy(dev_priv);
7850 lpt_program_fdi_mphy(dev_priv);
7851 }
7852 }
7853
7854 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7855 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7856 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7857 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7858
7859 mutex_unlock(&dev_priv->sb_lock);
7860 }
7861
7862 /* Sequence to disable CLKOUT_DP */
7863 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7864 {
7865 uint32_t reg, tmp;
7866
7867 mutex_lock(&dev_priv->sb_lock);
7868
7869 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7870 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7871 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7872 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7873
7874 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7875 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7876 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7877 tmp |= SBI_SSCCTL_PATHALT;
7878 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7879 udelay(32);
7880 }
7881 tmp |= SBI_SSCCTL_DISABLE;
7882 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7883 }
7884
7885 mutex_unlock(&dev_priv->sb_lock);
7886 }
7887
7888 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7889
7890 static const uint16_t sscdivintphase[] = {
7891 [BEND_IDX( 50)] = 0x3B23,
7892 [BEND_IDX( 45)] = 0x3B23,
7893 [BEND_IDX( 40)] = 0x3C23,
7894 [BEND_IDX( 35)] = 0x3C23,
7895 [BEND_IDX( 30)] = 0x3D23,
7896 [BEND_IDX( 25)] = 0x3D23,
7897 [BEND_IDX( 20)] = 0x3E23,
7898 [BEND_IDX( 15)] = 0x3E23,
7899 [BEND_IDX( 10)] = 0x3F23,
7900 [BEND_IDX( 5)] = 0x3F23,
7901 [BEND_IDX( 0)] = 0x0025,
7902 [BEND_IDX( -5)] = 0x0025,
7903 [BEND_IDX(-10)] = 0x0125,
7904 [BEND_IDX(-15)] = 0x0125,
7905 [BEND_IDX(-20)] = 0x0225,
7906 [BEND_IDX(-25)] = 0x0225,
7907 [BEND_IDX(-30)] = 0x0325,
7908 [BEND_IDX(-35)] = 0x0325,
7909 [BEND_IDX(-40)] = 0x0425,
7910 [BEND_IDX(-45)] = 0x0425,
7911 [BEND_IDX(-50)] = 0x0525,
7912 };
7913
7914 /*
7915 * Bend CLKOUT_DP
7916 * steps -50 to 50 inclusive, in steps of 5
7917 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7918 * change in clock period = -(steps / 10) * 5.787 ps
7919 */
7920 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
7921 {
7922 uint32_t tmp;
7923 int idx = BEND_IDX(steps);
7924
7925 if (WARN_ON(steps % 5 != 0))
7926 return;
7927
7928 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
7929 return;
7930
7931 mutex_lock(&dev_priv->sb_lock);
7932
7933 if (steps % 10 != 0)
7934 tmp = 0xAAAAAAAB;
7935 else
7936 tmp = 0x00000000;
7937 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
7938
7939 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
7940 tmp &= 0xffff0000;
7941 tmp |= sscdivintphase[idx];
7942 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
7943
7944 mutex_unlock(&dev_priv->sb_lock);
7945 }
7946
7947 #undef BEND_IDX
7948
7949 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
7950 {
7951 struct intel_encoder *encoder;
7952 bool has_vga = false;
7953
7954 for_each_intel_encoder(&dev_priv->drm, encoder) {
7955 switch (encoder->type) {
7956 case INTEL_OUTPUT_ANALOG:
7957 has_vga = true;
7958 break;
7959 default:
7960 break;
7961 }
7962 }
7963
7964 if (has_vga) {
7965 lpt_bend_clkout_dp(dev_priv, 0);
7966 lpt_enable_clkout_dp(dev_priv, true, true);
7967 } else {
7968 lpt_disable_clkout_dp(dev_priv);
7969 }
7970 }
7971
7972 /*
7973 * Initialize reference clocks when the driver loads
7974 */
7975 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
7976 {
7977 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
7978 ironlake_init_pch_refclk(dev_priv);
7979 else if (HAS_PCH_LPT(dev_priv))
7980 lpt_init_pch_refclk(dev_priv);
7981 }
7982
7983 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7984 {
7985 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
7986 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7987 int pipe = intel_crtc->pipe;
7988 uint32_t val;
7989
7990 val = 0;
7991
7992 switch (intel_crtc->config->pipe_bpp) {
7993 case 18:
7994 val |= PIPECONF_6BPC;
7995 break;
7996 case 24:
7997 val |= PIPECONF_8BPC;
7998 break;
7999 case 30:
8000 val |= PIPECONF_10BPC;
8001 break;
8002 case 36:
8003 val |= PIPECONF_12BPC;
8004 break;
8005 default:
8006 /* Case prevented by intel_choose_pipe_bpp_dither. */
8007 BUG();
8008 }
8009
8010 if (intel_crtc->config->dither)
8011 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8012
8013 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8014 val |= PIPECONF_INTERLACED_ILK;
8015 else
8016 val |= PIPECONF_PROGRESSIVE;
8017
8018 if (intel_crtc->config->limited_color_range)
8019 val |= PIPECONF_COLOR_RANGE_SELECT;
8020
8021 I915_WRITE(PIPECONF(pipe), val);
8022 POSTING_READ(PIPECONF(pipe));
8023 }
8024
8025 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8026 {
8027 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8029 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8030 u32 val = 0;
8031
8032 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8033 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8034
8035 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8036 val |= PIPECONF_INTERLACED_ILK;
8037 else
8038 val |= PIPECONF_PROGRESSIVE;
8039
8040 I915_WRITE(PIPECONF(cpu_transcoder), val);
8041 POSTING_READ(PIPECONF(cpu_transcoder));
8042 }
8043
8044 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8045 {
8046 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8048
8049 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8050 u32 val = 0;
8051
8052 switch (intel_crtc->config->pipe_bpp) {
8053 case 18:
8054 val |= PIPEMISC_DITHER_6_BPC;
8055 break;
8056 case 24:
8057 val |= PIPEMISC_DITHER_8_BPC;
8058 break;
8059 case 30:
8060 val |= PIPEMISC_DITHER_10_BPC;
8061 break;
8062 case 36:
8063 val |= PIPEMISC_DITHER_12_BPC;
8064 break;
8065 default:
8066 /* Case prevented by pipe_config_set_bpp. */
8067 BUG();
8068 }
8069
8070 if (intel_crtc->config->dither)
8071 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8072
8073 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8074 }
8075 }
8076
8077 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8078 {
8079 /*
8080 * Account for spread spectrum to avoid
8081 * oversubscribing the link. Max center spread
8082 * is 2.5%; use 5% for safety's sake.
8083 */
8084 u32 bps = target_clock * bpp * 21 / 20;
8085 return DIV_ROUND_UP(bps, link_bw * 8);
8086 }
8087
8088 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8089 {
8090 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8091 }
8092
8093 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8094 struct intel_crtc_state *crtc_state,
8095 struct dpll *reduced_clock)
8096 {
8097 struct drm_crtc *crtc = &intel_crtc->base;
8098 struct drm_device *dev = crtc->dev;
8099 struct drm_i915_private *dev_priv = to_i915(dev);
8100 u32 dpll, fp, fp2;
8101 int factor;
8102
8103 /* Enable autotuning of the PLL clock (if permissible) */
8104 factor = 21;
8105 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8106 if ((intel_panel_use_ssc(dev_priv) &&
8107 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8108 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8109 factor = 25;
8110 } else if (crtc_state->sdvo_tv_clock)
8111 factor = 20;
8112
8113 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8114
8115 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8116 fp |= FP_CB_TUNE;
8117
8118 if (reduced_clock) {
8119 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8120
8121 if (reduced_clock->m < factor * reduced_clock->n)
8122 fp2 |= FP_CB_TUNE;
8123 } else {
8124 fp2 = fp;
8125 }
8126
8127 dpll = 0;
8128
8129 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8130 dpll |= DPLLB_MODE_LVDS;
8131 else
8132 dpll |= DPLLB_MODE_DAC_SERIAL;
8133
8134 dpll |= (crtc_state->pixel_multiplier - 1)
8135 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8136
8137 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8138 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8139 dpll |= DPLL_SDVO_HIGH_SPEED;
8140
8141 if (intel_crtc_has_dp_encoder(crtc_state))
8142 dpll |= DPLL_SDVO_HIGH_SPEED;
8143
8144 /*
8145 * The high speed IO clock is only really required for
8146 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8147 * possible to share the DPLL between CRT and HDMI. Enabling
8148 * the clock needlessly does no real harm, except use up a
8149 * bit of power potentially.
8150 *
8151 * We'll limit this to IVB with 3 pipes, since it has only two
8152 * DPLLs and so DPLL sharing is the only way to get three pipes
8153 * driving PCH ports at the same time. On SNB we could do this,
8154 * and potentially avoid enabling the second DPLL, but it's not
8155 * clear if it''s a win or loss power wise. No point in doing
8156 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8157 */
8158 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8159 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8160 dpll |= DPLL_SDVO_HIGH_SPEED;
8161
8162 /* compute bitmask from p1 value */
8163 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8164 /* also FPA1 */
8165 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8166
8167 switch (crtc_state->dpll.p2) {
8168 case 5:
8169 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8170 break;
8171 case 7:
8172 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8173 break;
8174 case 10:
8175 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8176 break;
8177 case 14:
8178 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8179 break;
8180 }
8181
8182 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8183 intel_panel_use_ssc(dev_priv))
8184 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8185 else
8186 dpll |= PLL_REF_INPUT_DREFCLK;
8187
8188 dpll |= DPLL_VCO_ENABLE;
8189
8190 crtc_state->dpll_hw_state.dpll = dpll;
8191 crtc_state->dpll_hw_state.fp0 = fp;
8192 crtc_state->dpll_hw_state.fp1 = fp2;
8193 }
8194
8195 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8196 struct intel_crtc_state *crtc_state)
8197 {
8198 struct drm_device *dev = crtc->base.dev;
8199 struct drm_i915_private *dev_priv = to_i915(dev);
8200 struct dpll reduced_clock;
8201 bool has_reduced_clock = false;
8202 struct intel_shared_dpll *pll;
8203 const struct intel_limit *limit;
8204 int refclk = 120000;
8205
8206 memset(&crtc_state->dpll_hw_state, 0,
8207 sizeof(crtc_state->dpll_hw_state));
8208
8209 crtc->lowfreq_avail = false;
8210
8211 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8212 if (!crtc_state->has_pch_encoder)
8213 return 0;
8214
8215 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8216 if (intel_panel_use_ssc(dev_priv)) {
8217 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8218 dev_priv->vbt.lvds_ssc_freq);
8219 refclk = dev_priv->vbt.lvds_ssc_freq;
8220 }
8221
8222 if (intel_is_dual_link_lvds(dev)) {
8223 if (refclk == 100000)
8224 limit = &intel_limits_ironlake_dual_lvds_100m;
8225 else
8226 limit = &intel_limits_ironlake_dual_lvds;
8227 } else {
8228 if (refclk == 100000)
8229 limit = &intel_limits_ironlake_single_lvds_100m;
8230 else
8231 limit = &intel_limits_ironlake_single_lvds;
8232 }
8233 } else {
8234 limit = &intel_limits_ironlake_dac;
8235 }
8236
8237 if (!crtc_state->clock_set &&
8238 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8239 refclk, NULL, &crtc_state->dpll)) {
8240 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8241 return -EINVAL;
8242 }
8243
8244 ironlake_compute_dpll(crtc, crtc_state,
8245 has_reduced_clock ? &reduced_clock : NULL);
8246
8247 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8248 if (pll == NULL) {
8249 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8250 pipe_name(crtc->pipe));
8251 return -EINVAL;
8252 }
8253
8254 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8255 has_reduced_clock)
8256 crtc->lowfreq_avail = true;
8257
8258 return 0;
8259 }
8260
8261 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8262 struct intel_link_m_n *m_n)
8263 {
8264 struct drm_device *dev = crtc->base.dev;
8265 struct drm_i915_private *dev_priv = to_i915(dev);
8266 enum pipe pipe = crtc->pipe;
8267
8268 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8269 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8270 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8271 & ~TU_SIZE_MASK;
8272 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8273 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8274 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8275 }
8276
8277 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8278 enum transcoder transcoder,
8279 struct intel_link_m_n *m_n,
8280 struct intel_link_m_n *m2_n2)
8281 {
8282 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8283 enum pipe pipe = crtc->pipe;
8284
8285 if (INTEL_GEN(dev_priv) >= 5) {
8286 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8287 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8288 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8289 & ~TU_SIZE_MASK;
8290 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8291 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8292 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8293 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8294 * gen < 8) and if DRRS is supported (to make sure the
8295 * registers are not unnecessarily read).
8296 */
8297 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8298 crtc->config->has_drrs) {
8299 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8300 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8301 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8302 & ~TU_SIZE_MASK;
8303 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8304 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8305 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8306 }
8307 } else {
8308 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8309 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8310 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8311 & ~TU_SIZE_MASK;
8312 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8313 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8314 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8315 }
8316 }
8317
8318 void intel_dp_get_m_n(struct intel_crtc *crtc,
8319 struct intel_crtc_state *pipe_config)
8320 {
8321 if (pipe_config->has_pch_encoder)
8322 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8323 else
8324 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8325 &pipe_config->dp_m_n,
8326 &pipe_config->dp_m2_n2);
8327 }
8328
8329 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8330 struct intel_crtc_state *pipe_config)
8331 {
8332 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8333 &pipe_config->fdi_m_n, NULL);
8334 }
8335
8336 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8337 struct intel_crtc_state *pipe_config)
8338 {
8339 struct drm_device *dev = crtc->base.dev;
8340 struct drm_i915_private *dev_priv = to_i915(dev);
8341 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8342 uint32_t ps_ctrl = 0;
8343 int id = -1;
8344 int i;
8345
8346 /* find scaler attached to this pipe */
8347 for (i = 0; i < crtc->num_scalers; i++) {
8348 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8349 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8350 id = i;
8351 pipe_config->pch_pfit.enabled = true;
8352 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8353 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8354 break;
8355 }
8356 }
8357
8358 scaler_state->scaler_id = id;
8359 if (id >= 0) {
8360 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8361 } else {
8362 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8363 }
8364 }
8365
8366 static void
8367 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8368 struct intel_initial_plane_config *plane_config)
8369 {
8370 struct drm_device *dev = crtc->base.dev;
8371 struct drm_i915_private *dev_priv = to_i915(dev);
8372 u32 val, base, offset, stride_mult, tiling;
8373 int pipe = crtc->pipe;
8374 int fourcc, pixel_format;
8375 unsigned int aligned_height;
8376 struct drm_framebuffer *fb;
8377 struct intel_framebuffer *intel_fb;
8378
8379 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8380 if (!intel_fb) {
8381 DRM_DEBUG_KMS("failed to alloc fb\n");
8382 return;
8383 }
8384
8385 fb = &intel_fb->base;
8386
8387 fb->dev = dev;
8388
8389 val = I915_READ(PLANE_CTL(pipe, 0));
8390 if (!(val & PLANE_CTL_ENABLE))
8391 goto error;
8392
8393 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8394 fourcc = skl_format_to_fourcc(pixel_format,
8395 val & PLANE_CTL_ORDER_RGBX,
8396 val & PLANE_CTL_ALPHA_MASK);
8397 fb->format = drm_format_info(fourcc);
8398
8399 tiling = val & PLANE_CTL_TILED_MASK;
8400 switch (tiling) {
8401 case PLANE_CTL_TILED_LINEAR:
8402 fb->modifier = DRM_FORMAT_MOD_NONE;
8403 break;
8404 case PLANE_CTL_TILED_X:
8405 plane_config->tiling = I915_TILING_X;
8406 fb->modifier = I915_FORMAT_MOD_X_TILED;
8407 break;
8408 case PLANE_CTL_TILED_Y:
8409 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8410 break;
8411 case PLANE_CTL_TILED_YF:
8412 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8413 break;
8414 default:
8415 MISSING_CASE(tiling);
8416 goto error;
8417 }
8418
8419 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8420 plane_config->base = base;
8421
8422 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8423
8424 val = I915_READ(PLANE_SIZE(pipe, 0));
8425 fb->height = ((val >> 16) & 0xfff) + 1;
8426 fb->width = ((val >> 0) & 0x1fff) + 1;
8427
8428 val = I915_READ(PLANE_STRIDE(pipe, 0));
8429 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier,
8430 fb->format->format);
8431 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8432
8433 aligned_height = intel_fb_align_height(dev_priv,
8434 fb->height,
8435 fb->format->format,
8436 fb->modifier);
8437
8438 plane_config->size = fb->pitches[0] * aligned_height;
8439
8440 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8441 pipe_name(pipe), fb->width, fb->height,
8442 fb->format->cpp[0] * 8, base, fb->pitches[0],
8443 plane_config->size);
8444
8445 plane_config->fb = intel_fb;
8446 return;
8447
8448 error:
8449 kfree(intel_fb);
8450 }
8451
8452 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8453 struct intel_crtc_state *pipe_config)
8454 {
8455 struct drm_device *dev = crtc->base.dev;
8456 struct drm_i915_private *dev_priv = to_i915(dev);
8457 uint32_t tmp;
8458
8459 tmp = I915_READ(PF_CTL(crtc->pipe));
8460
8461 if (tmp & PF_ENABLE) {
8462 pipe_config->pch_pfit.enabled = true;
8463 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8464 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8465
8466 /* We currently do not free assignements of panel fitters on
8467 * ivb/hsw (since we don't use the higher upscaling modes which
8468 * differentiates them) so just WARN about this case for now. */
8469 if (IS_GEN7(dev_priv)) {
8470 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8471 PF_PIPE_SEL_IVB(crtc->pipe));
8472 }
8473 }
8474 }
8475
8476 static void
8477 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8478 struct intel_initial_plane_config *plane_config)
8479 {
8480 struct drm_device *dev = crtc->base.dev;
8481 struct drm_i915_private *dev_priv = to_i915(dev);
8482 u32 val, base, offset;
8483 int pipe = crtc->pipe;
8484 int fourcc, pixel_format;
8485 unsigned int aligned_height;
8486 struct drm_framebuffer *fb;
8487 struct intel_framebuffer *intel_fb;
8488
8489 val = I915_READ(DSPCNTR(pipe));
8490 if (!(val & DISPLAY_PLANE_ENABLE))
8491 return;
8492
8493 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8494 if (!intel_fb) {
8495 DRM_DEBUG_KMS("failed to alloc fb\n");
8496 return;
8497 }
8498
8499 fb = &intel_fb->base;
8500
8501 fb->dev = dev;
8502
8503 if (INTEL_GEN(dev_priv) >= 4) {
8504 if (val & DISPPLANE_TILED) {
8505 plane_config->tiling = I915_TILING_X;
8506 fb->modifier = I915_FORMAT_MOD_X_TILED;
8507 }
8508 }
8509
8510 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8511 fourcc = i9xx_format_to_fourcc(pixel_format);
8512 fb->format = drm_format_info(fourcc);
8513
8514 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8515 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8516 offset = I915_READ(DSPOFFSET(pipe));
8517 } else {
8518 if (plane_config->tiling)
8519 offset = I915_READ(DSPTILEOFF(pipe));
8520 else
8521 offset = I915_READ(DSPLINOFF(pipe));
8522 }
8523 plane_config->base = base;
8524
8525 val = I915_READ(PIPESRC(pipe));
8526 fb->width = ((val >> 16) & 0xfff) + 1;
8527 fb->height = ((val >> 0) & 0xfff) + 1;
8528
8529 val = I915_READ(DSPSTRIDE(pipe));
8530 fb->pitches[0] = val & 0xffffffc0;
8531
8532 aligned_height = intel_fb_align_height(dev_priv,
8533 fb->height,
8534 fb->format->format,
8535 fb->modifier);
8536
8537 plane_config->size = fb->pitches[0] * aligned_height;
8538
8539 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8540 pipe_name(pipe), fb->width, fb->height,
8541 fb->format->cpp[0] * 8, base, fb->pitches[0],
8542 plane_config->size);
8543
8544 plane_config->fb = intel_fb;
8545 }
8546
8547 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8548 struct intel_crtc_state *pipe_config)
8549 {
8550 struct drm_device *dev = crtc->base.dev;
8551 struct drm_i915_private *dev_priv = to_i915(dev);
8552 enum intel_display_power_domain power_domain;
8553 uint32_t tmp;
8554 bool ret;
8555
8556 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8557 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8558 return false;
8559
8560 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8561 pipe_config->shared_dpll = NULL;
8562
8563 ret = false;
8564 tmp = I915_READ(PIPECONF(crtc->pipe));
8565 if (!(tmp & PIPECONF_ENABLE))
8566 goto out;
8567
8568 switch (tmp & PIPECONF_BPC_MASK) {
8569 case PIPECONF_6BPC:
8570 pipe_config->pipe_bpp = 18;
8571 break;
8572 case PIPECONF_8BPC:
8573 pipe_config->pipe_bpp = 24;
8574 break;
8575 case PIPECONF_10BPC:
8576 pipe_config->pipe_bpp = 30;
8577 break;
8578 case PIPECONF_12BPC:
8579 pipe_config->pipe_bpp = 36;
8580 break;
8581 default:
8582 break;
8583 }
8584
8585 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8586 pipe_config->limited_color_range = true;
8587
8588 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8589 struct intel_shared_dpll *pll;
8590 enum intel_dpll_id pll_id;
8591
8592 pipe_config->has_pch_encoder = true;
8593
8594 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8595 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8596 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8597
8598 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8599
8600 if (HAS_PCH_IBX(dev_priv)) {
8601 /*
8602 * The pipe->pch transcoder and pch transcoder->pll
8603 * mapping is fixed.
8604 */
8605 pll_id = (enum intel_dpll_id) crtc->pipe;
8606 } else {
8607 tmp = I915_READ(PCH_DPLL_SEL);
8608 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8609 pll_id = DPLL_ID_PCH_PLL_B;
8610 else
8611 pll_id= DPLL_ID_PCH_PLL_A;
8612 }
8613
8614 pipe_config->shared_dpll =
8615 intel_get_shared_dpll_by_id(dev_priv, pll_id);
8616 pll = pipe_config->shared_dpll;
8617
8618 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8619 &pipe_config->dpll_hw_state));
8620
8621 tmp = pipe_config->dpll_hw_state.dpll;
8622 pipe_config->pixel_multiplier =
8623 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8624 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8625
8626 ironlake_pch_clock_get(crtc, pipe_config);
8627 } else {
8628 pipe_config->pixel_multiplier = 1;
8629 }
8630
8631 intel_get_pipe_timings(crtc, pipe_config);
8632 intel_get_pipe_src_size(crtc, pipe_config);
8633
8634 ironlake_get_pfit_config(crtc, pipe_config);
8635
8636 ret = true;
8637
8638 out:
8639 intel_display_power_put(dev_priv, power_domain);
8640
8641 return ret;
8642 }
8643
8644 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8645 {
8646 struct drm_device *dev = &dev_priv->drm;
8647 struct intel_crtc *crtc;
8648
8649 for_each_intel_crtc(dev, crtc)
8650 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8651 pipe_name(crtc->pipe));
8652
8653 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8654 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8655 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8656 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8657 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8658 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8659 "CPU PWM1 enabled\n");
8660 if (IS_HASWELL(dev_priv))
8661 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8662 "CPU PWM2 enabled\n");
8663 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8664 "PCH PWM1 enabled\n");
8665 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8666 "Utility pin enabled\n");
8667 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8668
8669 /*
8670 * In theory we can still leave IRQs enabled, as long as only the HPD
8671 * interrupts remain enabled. We used to check for that, but since it's
8672 * gen-specific and since we only disable LCPLL after we fully disable
8673 * the interrupts, the check below should be enough.
8674 */
8675 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8676 }
8677
8678 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8679 {
8680 if (IS_HASWELL(dev_priv))
8681 return I915_READ(D_COMP_HSW);
8682 else
8683 return I915_READ(D_COMP_BDW);
8684 }
8685
8686 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8687 {
8688 if (IS_HASWELL(dev_priv)) {
8689 mutex_lock(&dev_priv->rps.hw_lock);
8690 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8691 val))
8692 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8693 mutex_unlock(&dev_priv->rps.hw_lock);
8694 } else {
8695 I915_WRITE(D_COMP_BDW, val);
8696 POSTING_READ(D_COMP_BDW);
8697 }
8698 }
8699
8700 /*
8701 * This function implements pieces of two sequences from BSpec:
8702 * - Sequence for display software to disable LCPLL
8703 * - Sequence for display software to allow package C8+
8704 * The steps implemented here are just the steps that actually touch the LCPLL
8705 * register. Callers should take care of disabling all the display engine
8706 * functions, doing the mode unset, fixing interrupts, etc.
8707 */
8708 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8709 bool switch_to_fclk, bool allow_power_down)
8710 {
8711 uint32_t val;
8712
8713 assert_can_disable_lcpll(dev_priv);
8714
8715 val = I915_READ(LCPLL_CTL);
8716
8717 if (switch_to_fclk) {
8718 val |= LCPLL_CD_SOURCE_FCLK;
8719 I915_WRITE(LCPLL_CTL, val);
8720
8721 if (wait_for_us(I915_READ(LCPLL_CTL) &
8722 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8723 DRM_ERROR("Switching to FCLK failed\n");
8724
8725 val = I915_READ(LCPLL_CTL);
8726 }
8727
8728 val |= LCPLL_PLL_DISABLE;
8729 I915_WRITE(LCPLL_CTL, val);
8730 POSTING_READ(LCPLL_CTL);
8731
8732 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8733 DRM_ERROR("LCPLL still locked\n");
8734
8735 val = hsw_read_dcomp(dev_priv);
8736 val |= D_COMP_COMP_DISABLE;
8737 hsw_write_dcomp(dev_priv, val);
8738 ndelay(100);
8739
8740 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8741 1))
8742 DRM_ERROR("D_COMP RCOMP still in progress\n");
8743
8744 if (allow_power_down) {
8745 val = I915_READ(LCPLL_CTL);
8746 val |= LCPLL_POWER_DOWN_ALLOW;
8747 I915_WRITE(LCPLL_CTL, val);
8748 POSTING_READ(LCPLL_CTL);
8749 }
8750 }
8751
8752 /*
8753 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8754 * source.
8755 */
8756 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8757 {
8758 uint32_t val;
8759
8760 val = I915_READ(LCPLL_CTL);
8761
8762 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8763 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8764 return;
8765
8766 /*
8767 * Make sure we're not on PC8 state before disabling PC8, otherwise
8768 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8769 */
8770 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8771
8772 if (val & LCPLL_POWER_DOWN_ALLOW) {
8773 val &= ~LCPLL_POWER_DOWN_ALLOW;
8774 I915_WRITE(LCPLL_CTL, val);
8775 POSTING_READ(LCPLL_CTL);
8776 }
8777
8778 val = hsw_read_dcomp(dev_priv);
8779 val |= D_COMP_COMP_FORCE;
8780 val &= ~D_COMP_COMP_DISABLE;
8781 hsw_write_dcomp(dev_priv, val);
8782
8783 val = I915_READ(LCPLL_CTL);
8784 val &= ~LCPLL_PLL_DISABLE;
8785 I915_WRITE(LCPLL_CTL, val);
8786
8787 if (intel_wait_for_register(dev_priv,
8788 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8789 5))
8790 DRM_ERROR("LCPLL not locked yet\n");
8791
8792 if (val & LCPLL_CD_SOURCE_FCLK) {
8793 val = I915_READ(LCPLL_CTL);
8794 val &= ~LCPLL_CD_SOURCE_FCLK;
8795 I915_WRITE(LCPLL_CTL, val);
8796
8797 if (wait_for_us((I915_READ(LCPLL_CTL) &
8798 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8799 DRM_ERROR("Switching back to LCPLL failed\n");
8800 }
8801
8802 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8803 intel_update_cdclk(dev_priv);
8804 }
8805
8806 /*
8807 * Package states C8 and deeper are really deep PC states that can only be
8808 * reached when all the devices on the system allow it, so even if the graphics
8809 * device allows PC8+, it doesn't mean the system will actually get to these
8810 * states. Our driver only allows PC8+ when going into runtime PM.
8811 *
8812 * The requirements for PC8+ are that all the outputs are disabled, the power
8813 * well is disabled and most interrupts are disabled, and these are also
8814 * requirements for runtime PM. When these conditions are met, we manually do
8815 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8816 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8817 * hang the machine.
8818 *
8819 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8820 * the state of some registers, so when we come back from PC8+ we need to
8821 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8822 * need to take care of the registers kept by RC6. Notice that this happens even
8823 * if we don't put the device in PCI D3 state (which is what currently happens
8824 * because of the runtime PM support).
8825 *
8826 * For more, read "Display Sequences for Package C8" on the hardware
8827 * documentation.
8828 */
8829 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8830 {
8831 uint32_t val;
8832
8833 DRM_DEBUG_KMS("Enabling package C8+\n");
8834
8835 if (HAS_PCH_LPT_LP(dev_priv)) {
8836 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8837 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8838 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8839 }
8840
8841 lpt_disable_clkout_dp(dev_priv);
8842 hsw_disable_lcpll(dev_priv, true, true);
8843 }
8844
8845 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8846 {
8847 uint32_t val;
8848
8849 DRM_DEBUG_KMS("Disabling package C8+\n");
8850
8851 hsw_restore_lcpll(dev_priv);
8852 lpt_init_pch_refclk(dev_priv);
8853
8854 if (HAS_PCH_LPT_LP(dev_priv)) {
8855 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8856 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8857 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8858 }
8859 }
8860
8861 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8862 struct intel_crtc_state *crtc_state)
8863 {
8864 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8865 if (!intel_ddi_pll_select(crtc, crtc_state))
8866 return -EINVAL;
8867 }
8868
8869 crtc->lowfreq_avail = false;
8870
8871 return 0;
8872 }
8873
8874 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8875 enum port port,
8876 struct intel_crtc_state *pipe_config)
8877 {
8878 enum intel_dpll_id id;
8879
8880 switch (port) {
8881 case PORT_A:
8882 id = DPLL_ID_SKL_DPLL0;
8883 break;
8884 case PORT_B:
8885 id = DPLL_ID_SKL_DPLL1;
8886 break;
8887 case PORT_C:
8888 id = DPLL_ID_SKL_DPLL2;
8889 break;
8890 default:
8891 DRM_ERROR("Incorrect port type\n");
8892 return;
8893 }
8894
8895 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8896 }
8897
8898 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8899 enum port port,
8900 struct intel_crtc_state *pipe_config)
8901 {
8902 enum intel_dpll_id id;
8903 u32 temp;
8904
8905 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8906 id = temp >> (port * 3 + 1);
8907
8908 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
8909 return;
8910
8911 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8912 }
8913
8914 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8915 enum port port,
8916 struct intel_crtc_state *pipe_config)
8917 {
8918 enum intel_dpll_id id;
8919 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8920
8921 switch (ddi_pll_sel) {
8922 case PORT_CLK_SEL_WRPLL1:
8923 id = DPLL_ID_WRPLL1;
8924 break;
8925 case PORT_CLK_SEL_WRPLL2:
8926 id = DPLL_ID_WRPLL2;
8927 break;
8928 case PORT_CLK_SEL_SPLL:
8929 id = DPLL_ID_SPLL;
8930 break;
8931 case PORT_CLK_SEL_LCPLL_810:
8932 id = DPLL_ID_LCPLL_810;
8933 break;
8934 case PORT_CLK_SEL_LCPLL_1350:
8935 id = DPLL_ID_LCPLL_1350;
8936 break;
8937 case PORT_CLK_SEL_LCPLL_2700:
8938 id = DPLL_ID_LCPLL_2700;
8939 break;
8940 default:
8941 MISSING_CASE(ddi_pll_sel);
8942 /* fall through */
8943 case PORT_CLK_SEL_NONE:
8944 return;
8945 }
8946
8947 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8948 }
8949
8950 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
8951 struct intel_crtc_state *pipe_config,
8952 u64 *power_domain_mask)
8953 {
8954 struct drm_device *dev = crtc->base.dev;
8955 struct drm_i915_private *dev_priv = to_i915(dev);
8956 enum intel_display_power_domain power_domain;
8957 u32 tmp;
8958
8959 /*
8960 * The pipe->transcoder mapping is fixed with the exception of the eDP
8961 * transcoder handled below.
8962 */
8963 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8964
8965 /*
8966 * XXX: Do intel_display_power_get_if_enabled before reading this (for
8967 * consistency and less surprising code; it's in always on power).
8968 */
8969 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8970 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8971 enum pipe trans_edp_pipe;
8972 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8973 default:
8974 WARN(1, "unknown pipe linked to edp transcoder\n");
8975 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8976 case TRANS_DDI_EDP_INPUT_A_ON:
8977 trans_edp_pipe = PIPE_A;
8978 break;
8979 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8980 trans_edp_pipe = PIPE_B;
8981 break;
8982 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8983 trans_edp_pipe = PIPE_C;
8984 break;
8985 }
8986
8987 if (trans_edp_pipe == crtc->pipe)
8988 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8989 }
8990
8991 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
8992 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8993 return false;
8994 *power_domain_mask |= BIT_ULL(power_domain);
8995
8996 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8997
8998 return tmp & PIPECONF_ENABLE;
8999 }
9000
9001 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9002 struct intel_crtc_state *pipe_config,
9003 u64 *power_domain_mask)
9004 {
9005 struct drm_device *dev = crtc->base.dev;
9006 struct drm_i915_private *dev_priv = to_i915(dev);
9007 enum intel_display_power_domain power_domain;
9008 enum port port;
9009 enum transcoder cpu_transcoder;
9010 u32 tmp;
9011
9012 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9013 if (port == PORT_A)
9014 cpu_transcoder = TRANSCODER_DSI_A;
9015 else
9016 cpu_transcoder = TRANSCODER_DSI_C;
9017
9018 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9019 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9020 continue;
9021 *power_domain_mask |= BIT_ULL(power_domain);
9022
9023 /*
9024 * The PLL needs to be enabled with a valid divider
9025 * configuration, otherwise accessing DSI registers will hang
9026 * the machine. See BSpec North Display Engine
9027 * registers/MIPI[BXT]. We can break out here early, since we
9028 * need the same DSI PLL to be enabled for both DSI ports.
9029 */
9030 if (!intel_dsi_pll_is_enabled(dev_priv))
9031 break;
9032
9033 /* XXX: this works for video mode only */
9034 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9035 if (!(tmp & DPI_ENABLE))
9036 continue;
9037
9038 tmp = I915_READ(MIPI_CTRL(port));
9039 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9040 continue;
9041
9042 pipe_config->cpu_transcoder = cpu_transcoder;
9043 break;
9044 }
9045
9046 return transcoder_is_dsi(pipe_config->cpu_transcoder);
9047 }
9048
9049 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9050 struct intel_crtc_state *pipe_config)
9051 {
9052 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9053 struct intel_shared_dpll *pll;
9054 enum port port;
9055 uint32_t tmp;
9056
9057 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9058
9059 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9060
9061 if (IS_GEN9_BC(dev_priv))
9062 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9063 else if (IS_GEN9_LP(dev_priv))
9064 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9065 else
9066 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9067
9068 pll = pipe_config->shared_dpll;
9069 if (pll) {
9070 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9071 &pipe_config->dpll_hw_state));
9072 }
9073
9074 /*
9075 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9076 * DDI E. So just check whether this pipe is wired to DDI E and whether
9077 * the PCH transcoder is on.
9078 */
9079 if (INTEL_GEN(dev_priv) < 9 &&
9080 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9081 pipe_config->has_pch_encoder = true;
9082
9083 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9084 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9085 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9086
9087 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9088 }
9089 }
9090
9091 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9092 struct intel_crtc_state *pipe_config)
9093 {
9094 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9095 enum intel_display_power_domain power_domain;
9096 u64 power_domain_mask;
9097 bool active;
9098
9099 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9100 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9101 return false;
9102 power_domain_mask = BIT_ULL(power_domain);
9103
9104 pipe_config->shared_dpll = NULL;
9105
9106 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9107
9108 if (IS_GEN9_LP(dev_priv) &&
9109 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9110 WARN_ON(active);
9111 active = true;
9112 }
9113
9114 if (!active)
9115 goto out;
9116
9117 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9118 haswell_get_ddi_port_state(crtc, pipe_config);
9119 intel_get_pipe_timings(crtc, pipe_config);
9120 }
9121
9122 intel_get_pipe_src_size(crtc, pipe_config);
9123
9124 pipe_config->gamma_mode =
9125 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9126
9127 if (INTEL_GEN(dev_priv) >= 9) {
9128 intel_crtc_init_scalers(crtc, pipe_config);
9129
9130 pipe_config->scaler_state.scaler_id = -1;
9131 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9132 }
9133
9134 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9135 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9136 power_domain_mask |= BIT_ULL(power_domain);
9137 if (INTEL_GEN(dev_priv) >= 9)
9138 skylake_get_pfit_config(crtc, pipe_config);
9139 else
9140 ironlake_get_pfit_config(crtc, pipe_config);
9141 }
9142
9143 if (IS_HASWELL(dev_priv))
9144 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9145 (I915_READ(IPS_CTL) & IPS_ENABLE);
9146
9147 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9148 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9149 pipe_config->pixel_multiplier =
9150 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9151 } else {
9152 pipe_config->pixel_multiplier = 1;
9153 }
9154
9155 out:
9156 for_each_power_domain(power_domain, power_domain_mask)
9157 intel_display_power_put(dev_priv, power_domain);
9158
9159 return active;
9160 }
9161
9162 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
9163 const struct intel_plane_state *plane_state)
9164 {
9165 struct drm_device *dev = crtc->dev;
9166 struct drm_i915_private *dev_priv = to_i915(dev);
9167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9168 uint32_t cntl = 0, size = 0;
9169
9170 if (plane_state && plane_state->base.visible) {
9171 unsigned int width = plane_state->base.crtc_w;
9172 unsigned int height = plane_state->base.crtc_h;
9173 unsigned int stride = roundup_pow_of_two(width) * 4;
9174
9175 switch (stride) {
9176 default:
9177 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9178 width, stride);
9179 stride = 256;
9180 /* fallthrough */
9181 case 256:
9182 case 512:
9183 case 1024:
9184 case 2048:
9185 break;
9186 }
9187
9188 cntl |= CURSOR_ENABLE |
9189 CURSOR_GAMMA_ENABLE |
9190 CURSOR_FORMAT_ARGB |
9191 CURSOR_STRIDE(stride);
9192
9193 size = (height << 12) | width;
9194 }
9195
9196 if (intel_crtc->cursor_cntl != 0 &&
9197 (intel_crtc->cursor_base != base ||
9198 intel_crtc->cursor_size != size ||
9199 intel_crtc->cursor_cntl != cntl)) {
9200 /* On these chipsets we can only modify the base/size/stride
9201 * whilst the cursor is disabled.
9202 */
9203 I915_WRITE(CURCNTR(PIPE_A), 0);
9204 POSTING_READ(CURCNTR(PIPE_A));
9205 intel_crtc->cursor_cntl = 0;
9206 }
9207
9208 if (intel_crtc->cursor_base != base) {
9209 I915_WRITE(CURBASE(PIPE_A), base);
9210 intel_crtc->cursor_base = base;
9211 }
9212
9213 if (intel_crtc->cursor_size != size) {
9214 I915_WRITE(CURSIZE, size);
9215 intel_crtc->cursor_size = size;
9216 }
9217
9218 if (intel_crtc->cursor_cntl != cntl) {
9219 I915_WRITE(CURCNTR(PIPE_A), cntl);
9220 POSTING_READ(CURCNTR(PIPE_A));
9221 intel_crtc->cursor_cntl = cntl;
9222 }
9223 }
9224
9225 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
9226 const struct intel_plane_state *plane_state)
9227 {
9228 struct drm_device *dev = crtc->dev;
9229 struct drm_i915_private *dev_priv = to_i915(dev);
9230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9231 int pipe = intel_crtc->pipe;
9232 uint32_t cntl = 0;
9233
9234 if (plane_state && plane_state->base.visible) {
9235 cntl = MCURSOR_GAMMA_ENABLE;
9236 switch (plane_state->base.crtc_w) {
9237 case 64:
9238 cntl |= CURSOR_MODE_64_ARGB_AX;
9239 break;
9240 case 128:
9241 cntl |= CURSOR_MODE_128_ARGB_AX;
9242 break;
9243 case 256:
9244 cntl |= CURSOR_MODE_256_ARGB_AX;
9245 break;
9246 default:
9247 MISSING_CASE(plane_state->base.crtc_w);
9248 return;
9249 }
9250 cntl |= pipe << 28; /* Connect to correct pipe */
9251
9252 if (HAS_DDI(dev_priv))
9253 cntl |= CURSOR_PIPE_CSC_ENABLE;
9254
9255 if (plane_state->base.rotation & DRM_ROTATE_180)
9256 cntl |= CURSOR_ROTATE_180;
9257 }
9258
9259 if (intel_crtc->cursor_cntl != cntl) {
9260 I915_WRITE(CURCNTR(pipe), cntl);
9261 POSTING_READ(CURCNTR(pipe));
9262 intel_crtc->cursor_cntl = cntl;
9263 }
9264
9265 /* and commit changes on next vblank */
9266 I915_WRITE(CURBASE(pipe), base);
9267 POSTING_READ(CURBASE(pipe));
9268
9269 intel_crtc->cursor_base = base;
9270 }
9271
9272 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9273 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9274 const struct intel_plane_state *plane_state)
9275 {
9276 struct drm_device *dev = crtc->dev;
9277 struct drm_i915_private *dev_priv = to_i915(dev);
9278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9279 int pipe = intel_crtc->pipe;
9280 u32 base = intel_crtc->cursor_addr;
9281 u32 pos = 0;
9282
9283 if (plane_state) {
9284 int x = plane_state->base.crtc_x;
9285 int y = plane_state->base.crtc_y;
9286
9287 if (x < 0) {
9288 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9289 x = -x;
9290 }
9291 pos |= x << CURSOR_X_SHIFT;
9292
9293 if (y < 0) {
9294 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9295 y = -y;
9296 }
9297 pos |= y << CURSOR_Y_SHIFT;
9298
9299 /* ILK+ do this automagically */
9300 if (HAS_GMCH_DISPLAY(dev_priv) &&
9301 plane_state->base.rotation & DRM_ROTATE_180) {
9302 base += (plane_state->base.crtc_h *
9303 plane_state->base.crtc_w - 1) * 4;
9304 }
9305 }
9306
9307 I915_WRITE(CURPOS(pipe), pos);
9308
9309 if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
9310 i845_update_cursor(crtc, base, plane_state);
9311 else
9312 i9xx_update_cursor(crtc, base, plane_state);
9313 }
9314
9315 static bool cursor_size_ok(struct drm_i915_private *dev_priv,
9316 uint32_t width, uint32_t height)
9317 {
9318 if (width == 0 || height == 0)
9319 return false;
9320
9321 /*
9322 * 845g/865g are special in that they are only limited by
9323 * the width of their cursors, the height is arbitrary up to
9324 * the precision of the register. Everything else requires
9325 * square cursors, limited to a few power-of-two sizes.
9326 */
9327 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
9328 if ((width & 63) != 0)
9329 return false;
9330
9331 if (width > (IS_I845G(dev_priv) ? 64 : 512))
9332 return false;
9333
9334 if (height > 1023)
9335 return false;
9336 } else {
9337 switch (width | height) {
9338 case 256:
9339 case 128:
9340 if (IS_GEN2(dev_priv))
9341 return false;
9342 case 64:
9343 break;
9344 default:
9345 return false;
9346 }
9347 }
9348
9349 return true;
9350 }
9351
9352 /* VESA 640x480x72Hz mode to set on the pipe */
9353 static struct drm_display_mode load_detect_mode = {
9354 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9355 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9356 };
9357
9358 struct drm_framebuffer *
9359 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9360 struct drm_mode_fb_cmd2 *mode_cmd)
9361 {
9362 struct intel_framebuffer *intel_fb;
9363 int ret;
9364
9365 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9366 if (!intel_fb)
9367 return ERR_PTR(-ENOMEM);
9368
9369 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9370 if (ret)
9371 goto err;
9372
9373 return &intel_fb->base;
9374
9375 err:
9376 kfree(intel_fb);
9377 return ERR_PTR(ret);
9378 }
9379
9380 static u32
9381 intel_framebuffer_pitch_for_width(int width, int bpp)
9382 {
9383 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9384 return ALIGN(pitch, 64);
9385 }
9386
9387 static u32
9388 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9389 {
9390 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9391 return PAGE_ALIGN(pitch * mode->vdisplay);
9392 }
9393
9394 static struct drm_framebuffer *
9395 intel_framebuffer_create_for_mode(struct drm_device *dev,
9396 struct drm_display_mode *mode,
9397 int depth, int bpp)
9398 {
9399 struct drm_framebuffer *fb;
9400 struct drm_i915_gem_object *obj;
9401 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9402
9403 obj = i915_gem_object_create(to_i915(dev),
9404 intel_framebuffer_size_for_mode(mode, bpp));
9405 if (IS_ERR(obj))
9406 return ERR_CAST(obj);
9407
9408 mode_cmd.width = mode->hdisplay;
9409 mode_cmd.height = mode->vdisplay;
9410 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9411 bpp);
9412 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9413
9414 fb = intel_framebuffer_create(obj, &mode_cmd);
9415 if (IS_ERR(fb))
9416 i915_gem_object_put(obj);
9417
9418 return fb;
9419 }
9420
9421 static struct drm_framebuffer *
9422 mode_fits_in_fbdev(struct drm_device *dev,
9423 struct drm_display_mode *mode)
9424 {
9425 #ifdef CONFIG_DRM_FBDEV_EMULATION
9426 struct drm_i915_private *dev_priv = to_i915(dev);
9427 struct drm_i915_gem_object *obj;
9428 struct drm_framebuffer *fb;
9429
9430 if (!dev_priv->fbdev)
9431 return NULL;
9432
9433 if (!dev_priv->fbdev->fb)
9434 return NULL;
9435
9436 obj = dev_priv->fbdev->fb->obj;
9437 BUG_ON(!obj);
9438
9439 fb = &dev_priv->fbdev->fb->base;
9440 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9441 fb->format->cpp[0] * 8))
9442 return NULL;
9443
9444 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9445 return NULL;
9446
9447 drm_framebuffer_reference(fb);
9448 return fb;
9449 #else
9450 return NULL;
9451 #endif
9452 }
9453
9454 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9455 struct drm_crtc *crtc,
9456 struct drm_display_mode *mode,
9457 struct drm_framebuffer *fb,
9458 int x, int y)
9459 {
9460 struct drm_plane_state *plane_state;
9461 int hdisplay, vdisplay;
9462 int ret;
9463
9464 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9465 if (IS_ERR(plane_state))
9466 return PTR_ERR(plane_state);
9467
9468 if (mode)
9469 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9470 else
9471 hdisplay = vdisplay = 0;
9472
9473 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9474 if (ret)
9475 return ret;
9476 drm_atomic_set_fb_for_plane(plane_state, fb);
9477 plane_state->crtc_x = 0;
9478 plane_state->crtc_y = 0;
9479 plane_state->crtc_w = hdisplay;
9480 plane_state->crtc_h = vdisplay;
9481 plane_state->src_x = x << 16;
9482 plane_state->src_y = y << 16;
9483 plane_state->src_w = hdisplay << 16;
9484 plane_state->src_h = vdisplay << 16;
9485
9486 return 0;
9487 }
9488
9489 bool intel_get_load_detect_pipe(struct drm_connector *connector,
9490 struct drm_display_mode *mode,
9491 struct intel_load_detect_pipe *old,
9492 struct drm_modeset_acquire_ctx *ctx)
9493 {
9494 struct intel_crtc *intel_crtc;
9495 struct intel_encoder *intel_encoder =
9496 intel_attached_encoder(connector);
9497 struct drm_crtc *possible_crtc;
9498 struct drm_encoder *encoder = &intel_encoder->base;
9499 struct drm_crtc *crtc = NULL;
9500 struct drm_device *dev = encoder->dev;
9501 struct drm_i915_private *dev_priv = to_i915(dev);
9502 struct drm_framebuffer *fb;
9503 struct drm_mode_config *config = &dev->mode_config;
9504 struct drm_atomic_state *state = NULL, *restore_state = NULL;
9505 struct drm_connector_state *connector_state;
9506 struct intel_crtc_state *crtc_state;
9507 int ret, i = -1;
9508
9509 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9510 connector->base.id, connector->name,
9511 encoder->base.id, encoder->name);
9512
9513 old->restore_state = NULL;
9514
9515 retry:
9516 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9517 if (ret)
9518 goto fail;
9519
9520 /*
9521 * Algorithm gets a little messy:
9522 *
9523 * - if the connector already has an assigned crtc, use it (but make
9524 * sure it's on first)
9525 *
9526 * - try to find the first unused crtc that can drive this connector,
9527 * and use that if we find one
9528 */
9529
9530 /* See if we already have a CRTC for this connector */
9531 if (connector->state->crtc) {
9532 crtc = connector->state->crtc;
9533
9534 ret = drm_modeset_lock(&crtc->mutex, ctx);
9535 if (ret)
9536 goto fail;
9537
9538 /* Make sure the crtc and connector are running */
9539 goto found;
9540 }
9541
9542 /* Find an unused one (if possible) */
9543 for_each_crtc(dev, possible_crtc) {
9544 i++;
9545 if (!(encoder->possible_crtcs & (1 << i)))
9546 continue;
9547
9548 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9549 if (ret)
9550 goto fail;
9551
9552 if (possible_crtc->state->enable) {
9553 drm_modeset_unlock(&possible_crtc->mutex);
9554 continue;
9555 }
9556
9557 crtc = possible_crtc;
9558 break;
9559 }
9560
9561 /*
9562 * If we didn't find an unused CRTC, don't use any.
9563 */
9564 if (!crtc) {
9565 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9566 goto fail;
9567 }
9568
9569 found:
9570 intel_crtc = to_intel_crtc(crtc);
9571
9572 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9573 if (ret)
9574 goto fail;
9575
9576 state = drm_atomic_state_alloc(dev);
9577 restore_state = drm_atomic_state_alloc(dev);
9578 if (!state || !restore_state) {
9579 ret = -ENOMEM;
9580 goto fail;
9581 }
9582
9583 state->acquire_ctx = ctx;
9584 restore_state->acquire_ctx = ctx;
9585
9586 connector_state = drm_atomic_get_connector_state(state, connector);
9587 if (IS_ERR(connector_state)) {
9588 ret = PTR_ERR(connector_state);
9589 goto fail;
9590 }
9591
9592 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9593 if (ret)
9594 goto fail;
9595
9596 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9597 if (IS_ERR(crtc_state)) {
9598 ret = PTR_ERR(crtc_state);
9599 goto fail;
9600 }
9601
9602 crtc_state->base.active = crtc_state->base.enable = true;
9603
9604 if (!mode)
9605 mode = &load_detect_mode;
9606
9607 /* We need a framebuffer large enough to accommodate all accesses
9608 * that the plane may generate whilst we perform load detection.
9609 * We can not rely on the fbcon either being present (we get called
9610 * during its initialisation to detect all boot displays, or it may
9611 * not even exist) or that it is large enough to satisfy the
9612 * requested mode.
9613 */
9614 fb = mode_fits_in_fbdev(dev, mode);
9615 if (fb == NULL) {
9616 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9617 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9618 } else
9619 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9620 if (IS_ERR(fb)) {
9621 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9622 goto fail;
9623 }
9624
9625 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9626 if (ret)
9627 goto fail;
9628
9629 drm_framebuffer_unreference(fb);
9630
9631 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9632 if (ret)
9633 goto fail;
9634
9635 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9636 if (!ret)
9637 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9638 if (!ret)
9639 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9640 if (ret) {
9641 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9642 goto fail;
9643 }
9644
9645 ret = drm_atomic_commit(state);
9646 if (ret) {
9647 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9648 goto fail;
9649 }
9650
9651 old->restore_state = restore_state;
9652 drm_atomic_state_put(state);
9653
9654 /* let the connector get through one full cycle before testing */
9655 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9656 return true;
9657
9658 fail:
9659 if (state) {
9660 drm_atomic_state_put(state);
9661 state = NULL;
9662 }
9663 if (restore_state) {
9664 drm_atomic_state_put(restore_state);
9665 restore_state = NULL;
9666 }
9667
9668 if (ret == -EDEADLK) {
9669 drm_modeset_backoff(ctx);
9670 goto retry;
9671 }
9672
9673 return false;
9674 }
9675
9676 void intel_release_load_detect_pipe(struct drm_connector *connector,
9677 struct intel_load_detect_pipe *old,
9678 struct drm_modeset_acquire_ctx *ctx)
9679 {
9680 struct intel_encoder *intel_encoder =
9681 intel_attached_encoder(connector);
9682 struct drm_encoder *encoder = &intel_encoder->base;
9683 struct drm_atomic_state *state = old->restore_state;
9684 int ret;
9685
9686 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9687 connector->base.id, connector->name,
9688 encoder->base.id, encoder->name);
9689
9690 if (!state)
9691 return;
9692
9693 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
9694 if (ret)
9695 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
9696 drm_atomic_state_put(state);
9697 }
9698
9699 static int i9xx_pll_refclk(struct drm_device *dev,
9700 const struct intel_crtc_state *pipe_config)
9701 {
9702 struct drm_i915_private *dev_priv = to_i915(dev);
9703 u32 dpll = pipe_config->dpll_hw_state.dpll;
9704
9705 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9706 return dev_priv->vbt.lvds_ssc_freq;
9707 else if (HAS_PCH_SPLIT(dev_priv))
9708 return 120000;
9709 else if (!IS_GEN2(dev_priv))
9710 return 96000;
9711 else
9712 return 48000;
9713 }
9714
9715 /* Returns the clock of the currently programmed mode of the given pipe. */
9716 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9717 struct intel_crtc_state *pipe_config)
9718 {
9719 struct drm_device *dev = crtc->base.dev;
9720 struct drm_i915_private *dev_priv = to_i915(dev);
9721 int pipe = pipe_config->cpu_transcoder;
9722 u32 dpll = pipe_config->dpll_hw_state.dpll;
9723 u32 fp;
9724 struct dpll clock;
9725 int port_clock;
9726 int refclk = i9xx_pll_refclk(dev, pipe_config);
9727
9728 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9729 fp = pipe_config->dpll_hw_state.fp0;
9730 else
9731 fp = pipe_config->dpll_hw_state.fp1;
9732
9733 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9734 if (IS_PINEVIEW(dev_priv)) {
9735 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9736 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9737 } else {
9738 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9739 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9740 }
9741
9742 if (!IS_GEN2(dev_priv)) {
9743 if (IS_PINEVIEW(dev_priv))
9744 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9745 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9746 else
9747 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9748 DPLL_FPA01_P1_POST_DIV_SHIFT);
9749
9750 switch (dpll & DPLL_MODE_MASK) {
9751 case DPLLB_MODE_DAC_SERIAL:
9752 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9753 5 : 10;
9754 break;
9755 case DPLLB_MODE_LVDS:
9756 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9757 7 : 14;
9758 break;
9759 default:
9760 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9761 "mode\n", (int)(dpll & DPLL_MODE_MASK));
9762 return;
9763 }
9764
9765 if (IS_PINEVIEW(dev_priv))
9766 port_clock = pnv_calc_dpll_params(refclk, &clock);
9767 else
9768 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9769 } else {
9770 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
9771 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9772
9773 if (is_lvds) {
9774 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9775 DPLL_FPA01_P1_POST_DIV_SHIFT);
9776
9777 if (lvds & LVDS_CLKB_POWER_UP)
9778 clock.p2 = 7;
9779 else
9780 clock.p2 = 14;
9781 } else {
9782 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9783 clock.p1 = 2;
9784 else {
9785 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9786 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9787 }
9788 if (dpll & PLL_P2_DIVIDE_BY_4)
9789 clock.p2 = 4;
9790 else
9791 clock.p2 = 2;
9792 }
9793
9794 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9795 }
9796
9797 /*
9798 * This value includes pixel_multiplier. We will use
9799 * port_clock to compute adjusted_mode.crtc_clock in the
9800 * encoder's get_config() function.
9801 */
9802 pipe_config->port_clock = port_clock;
9803 }
9804
9805 int intel_dotclock_calculate(int link_freq,
9806 const struct intel_link_m_n *m_n)
9807 {
9808 /*
9809 * The calculation for the data clock is:
9810 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9811 * But we want to avoid losing precison if possible, so:
9812 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9813 *
9814 * and the link clock is simpler:
9815 * link_clock = (m * link_clock) / n
9816 */
9817
9818 if (!m_n->link_n)
9819 return 0;
9820
9821 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9822 }
9823
9824 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9825 struct intel_crtc_state *pipe_config)
9826 {
9827 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9828
9829 /* read out port_clock from the DPLL */
9830 i9xx_crtc_clock_get(crtc, pipe_config);
9831
9832 /*
9833 * In case there is an active pipe without active ports,
9834 * we may need some idea for the dotclock anyway.
9835 * Calculate one based on the FDI configuration.
9836 */
9837 pipe_config->base.adjusted_mode.crtc_clock =
9838 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
9839 &pipe_config->fdi_m_n);
9840 }
9841
9842 /** Returns the currently programmed mode of the given pipe. */
9843 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9844 struct drm_crtc *crtc)
9845 {
9846 struct drm_i915_private *dev_priv = to_i915(dev);
9847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9848 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9849 struct drm_display_mode *mode;
9850 struct intel_crtc_state *pipe_config;
9851 int htot = I915_READ(HTOTAL(cpu_transcoder));
9852 int hsync = I915_READ(HSYNC(cpu_transcoder));
9853 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9854 int vsync = I915_READ(VSYNC(cpu_transcoder));
9855 enum pipe pipe = intel_crtc->pipe;
9856
9857 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9858 if (!mode)
9859 return NULL;
9860
9861 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9862 if (!pipe_config) {
9863 kfree(mode);
9864 return NULL;
9865 }
9866
9867 /*
9868 * Construct a pipe_config sufficient for getting the clock info
9869 * back out of crtc_clock_get.
9870 *
9871 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9872 * to use a real value here instead.
9873 */
9874 pipe_config->cpu_transcoder = (enum transcoder) pipe;
9875 pipe_config->pixel_multiplier = 1;
9876 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9877 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9878 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9879 i9xx_crtc_clock_get(intel_crtc, pipe_config);
9880
9881 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
9882 mode->hdisplay = (htot & 0xffff) + 1;
9883 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9884 mode->hsync_start = (hsync & 0xffff) + 1;
9885 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9886 mode->vdisplay = (vtot & 0xffff) + 1;
9887 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9888 mode->vsync_start = (vsync & 0xffff) + 1;
9889 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9890
9891 drm_mode_set_name(mode);
9892
9893 kfree(pipe_config);
9894
9895 return mode;
9896 }
9897
9898 static void intel_crtc_destroy(struct drm_crtc *crtc)
9899 {
9900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9901 struct drm_device *dev = crtc->dev;
9902 struct intel_flip_work *work;
9903
9904 spin_lock_irq(&dev->event_lock);
9905 work = intel_crtc->flip_work;
9906 intel_crtc->flip_work = NULL;
9907 spin_unlock_irq(&dev->event_lock);
9908
9909 if (work) {
9910 cancel_work_sync(&work->mmio_work);
9911 cancel_work_sync(&work->unpin_work);
9912 kfree(work);
9913 }
9914
9915 drm_crtc_cleanup(crtc);
9916
9917 kfree(intel_crtc);
9918 }
9919
9920 static void intel_unpin_work_fn(struct work_struct *__work)
9921 {
9922 struct intel_flip_work *work =
9923 container_of(__work, struct intel_flip_work, unpin_work);
9924 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
9925 struct drm_device *dev = crtc->base.dev;
9926 struct drm_plane *primary = crtc->base.primary;
9927
9928 if (is_mmio_work(work))
9929 flush_work(&work->mmio_work);
9930
9931 mutex_lock(&dev->struct_mutex);
9932 intel_unpin_fb_vma(work->old_vma);
9933 i915_gem_object_put(work->pending_flip_obj);
9934 mutex_unlock(&dev->struct_mutex);
9935
9936 i915_gem_request_put(work->flip_queued_req);
9937
9938 intel_frontbuffer_flip_complete(to_i915(dev),
9939 to_intel_plane(primary)->frontbuffer_bit);
9940 intel_fbc_post_update(crtc);
9941 drm_framebuffer_unreference(work->old_fb);
9942
9943 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
9944 atomic_dec(&crtc->unpin_work_count);
9945
9946 kfree(work);
9947 }
9948
9949 /* Is 'a' after or equal to 'b'? */
9950 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9951 {
9952 return !((a - b) & 0x80000000);
9953 }
9954
9955 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
9956 struct intel_flip_work *work)
9957 {
9958 struct drm_device *dev = crtc->base.dev;
9959 struct drm_i915_private *dev_priv = to_i915(dev);
9960
9961 if (abort_flip_on_reset(crtc))
9962 return true;
9963
9964 /*
9965 * The relevant registers doen't exist on pre-ctg.
9966 * As the flip done interrupt doesn't trigger for mmio
9967 * flips on gmch platforms, a flip count check isn't
9968 * really needed there. But since ctg has the registers,
9969 * include it in the check anyway.
9970 */
9971 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
9972 return true;
9973
9974 /*
9975 * BDW signals flip done immediately if the plane
9976 * is disabled, even if the plane enable is already
9977 * armed to occur at the next vblank :(
9978 */
9979
9980 /*
9981 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9982 * used the same base address. In that case the mmio flip might
9983 * have completed, but the CS hasn't even executed the flip yet.
9984 *
9985 * A flip count check isn't enough as the CS might have updated
9986 * the base address just after start of vblank, but before we
9987 * managed to process the interrupt. This means we'd complete the
9988 * CS flip too soon.
9989 *
9990 * Combining both checks should get us a good enough result. It may
9991 * still happen that the CS flip has been executed, but has not
9992 * yet actually completed. But in case the base address is the same
9993 * anyway, we don't really care.
9994 */
9995 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9996 crtc->flip_work->gtt_offset &&
9997 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
9998 crtc->flip_work->flip_count);
9999 }
10000
10001 static bool
10002 __pageflip_finished_mmio(struct intel_crtc *crtc,
10003 struct intel_flip_work *work)
10004 {
10005 /*
10006 * MMIO work completes when vblank is different from
10007 * flip_queued_vblank.
10008 *
10009 * Reset counter value doesn't matter, this is handled by
10010 * i915_wait_request finishing early, so no need to handle
10011 * reset here.
10012 */
10013 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
10014 }
10015
10016
10017 static bool pageflip_finished(struct intel_crtc *crtc,
10018 struct intel_flip_work *work)
10019 {
10020 if (!atomic_read(&work->pending))
10021 return false;
10022
10023 smp_rmb();
10024
10025 if (is_mmio_work(work))
10026 return __pageflip_finished_mmio(crtc, work);
10027 else
10028 return __pageflip_finished_cs(crtc, work);
10029 }
10030
10031 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
10032 {
10033 struct drm_device *dev = &dev_priv->drm;
10034 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10035 struct intel_flip_work *work;
10036 unsigned long flags;
10037
10038 /* Ignore early vblank irqs */
10039 if (!crtc)
10040 return;
10041
10042 /*
10043 * This is called both by irq handlers and the reset code (to complete
10044 * lost pageflips) so needs the full irqsave spinlocks.
10045 */
10046 spin_lock_irqsave(&dev->event_lock, flags);
10047 work = crtc->flip_work;
10048
10049 if (work != NULL &&
10050 !is_mmio_work(work) &&
10051 pageflip_finished(crtc, work))
10052 page_flip_completed(crtc);
10053
10054 spin_unlock_irqrestore(&dev->event_lock, flags);
10055 }
10056
10057 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
10058 {
10059 struct drm_device *dev = &dev_priv->drm;
10060 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10061 struct intel_flip_work *work;
10062 unsigned long flags;
10063
10064 /* Ignore early vblank irqs */
10065 if (!crtc)
10066 return;
10067
10068 /*
10069 * This is called both by irq handlers and the reset code (to complete
10070 * lost pageflips) so needs the full irqsave spinlocks.
10071 */
10072 spin_lock_irqsave(&dev->event_lock, flags);
10073 work = crtc->flip_work;
10074
10075 if (work != NULL &&
10076 is_mmio_work(work) &&
10077 pageflip_finished(crtc, work))
10078 page_flip_completed(crtc);
10079
10080 spin_unlock_irqrestore(&dev->event_lock, flags);
10081 }
10082
10083 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
10084 struct intel_flip_work *work)
10085 {
10086 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
10087
10088 /* Ensure that the work item is consistent when activating it ... */
10089 smp_mb__before_atomic();
10090 atomic_set(&work->pending, 1);
10091 }
10092
10093 static int intel_gen2_queue_flip(struct drm_device *dev,
10094 struct drm_crtc *crtc,
10095 struct drm_framebuffer *fb,
10096 struct drm_i915_gem_object *obj,
10097 struct drm_i915_gem_request *req,
10098 uint32_t flags)
10099 {
10100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10101 u32 flip_mask, *cs;
10102
10103 cs = intel_ring_begin(req, 6);
10104 if (IS_ERR(cs))
10105 return PTR_ERR(cs);
10106
10107 /* Can't queue multiple flips, so wait for the previous
10108 * one to finish before executing the next.
10109 */
10110 if (intel_crtc->plane)
10111 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10112 else
10113 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10114 *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10115 *cs++ = MI_NOOP;
10116 *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10117 *cs++ = fb->pitches[0];
10118 *cs++ = intel_crtc->flip_work->gtt_offset;
10119 *cs++ = 0; /* aux display base address, unused */
10120
10121 return 0;
10122 }
10123
10124 static int intel_gen3_queue_flip(struct drm_device *dev,
10125 struct drm_crtc *crtc,
10126 struct drm_framebuffer *fb,
10127 struct drm_i915_gem_object *obj,
10128 struct drm_i915_gem_request *req,
10129 uint32_t flags)
10130 {
10131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10132 u32 flip_mask, *cs;
10133
10134 cs = intel_ring_begin(req, 6);
10135 if (IS_ERR(cs))
10136 return PTR_ERR(cs);
10137
10138 if (intel_crtc->plane)
10139 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10140 else
10141 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10142 *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10143 *cs++ = MI_NOOP;
10144 *cs++ = MI_DISPLAY_FLIP_I915 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10145 *cs++ = fb->pitches[0];
10146 *cs++ = intel_crtc->flip_work->gtt_offset;
10147 *cs++ = MI_NOOP;
10148
10149 return 0;
10150 }
10151
10152 static int intel_gen4_queue_flip(struct drm_device *dev,
10153 struct drm_crtc *crtc,
10154 struct drm_framebuffer *fb,
10155 struct drm_i915_gem_object *obj,
10156 struct drm_i915_gem_request *req,
10157 uint32_t flags)
10158 {
10159 struct drm_i915_private *dev_priv = to_i915(dev);
10160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10161 u32 pf, pipesrc, *cs;
10162
10163 cs = intel_ring_begin(req, 4);
10164 if (IS_ERR(cs))
10165 return PTR_ERR(cs);
10166
10167 /* i965+ uses the linear or tiled offsets from the
10168 * Display Registers (which do not change across a page-flip)
10169 * so we need only reprogram the base address.
10170 */
10171 *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10172 *cs++ = fb->pitches[0];
10173 *cs++ = intel_crtc->flip_work->gtt_offset |
10174 intel_fb_modifier_to_tiling(fb->modifier);
10175
10176 /* XXX Enabling the panel-fitter across page-flip is so far
10177 * untested on non-native modes, so ignore it for now.
10178 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10179 */
10180 pf = 0;
10181 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10182 *cs++ = pf | pipesrc;
10183
10184 return 0;
10185 }
10186
10187 static int intel_gen6_queue_flip(struct drm_device *dev,
10188 struct drm_crtc *crtc,
10189 struct drm_framebuffer *fb,
10190 struct drm_i915_gem_object *obj,
10191 struct drm_i915_gem_request *req,
10192 uint32_t flags)
10193 {
10194 struct drm_i915_private *dev_priv = to_i915(dev);
10195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10196 u32 pf, pipesrc, *cs;
10197
10198 cs = intel_ring_begin(req, 4);
10199 if (IS_ERR(cs))
10200 return PTR_ERR(cs);
10201
10202 *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10203 *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10204 *cs++ = intel_crtc->flip_work->gtt_offset;
10205
10206 /* Contrary to the suggestions in the documentation,
10207 * "Enable Panel Fitter" does not seem to be required when page
10208 * flipping with a non-native mode, and worse causes a normal
10209 * modeset to fail.
10210 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10211 */
10212 pf = 0;
10213 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10214 *cs++ = pf | pipesrc;
10215
10216 return 0;
10217 }
10218
10219 static int intel_gen7_queue_flip(struct drm_device *dev,
10220 struct drm_crtc *crtc,
10221 struct drm_framebuffer *fb,
10222 struct drm_i915_gem_object *obj,
10223 struct drm_i915_gem_request *req,
10224 uint32_t flags)
10225 {
10226 struct drm_i915_private *dev_priv = to_i915(dev);
10227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10228 u32 *cs, plane_bit = 0;
10229 int len, ret;
10230
10231 switch (intel_crtc->plane) {
10232 case PLANE_A:
10233 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10234 break;
10235 case PLANE_B:
10236 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10237 break;
10238 case PLANE_C:
10239 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10240 break;
10241 default:
10242 WARN_ONCE(1, "unknown plane in flip command\n");
10243 return -ENODEV;
10244 }
10245
10246 len = 4;
10247 if (req->engine->id == RCS) {
10248 len += 6;
10249 /*
10250 * On Gen 8, SRM is now taking an extra dword to accommodate
10251 * 48bits addresses, and we need a NOOP for the batch size to
10252 * stay even.
10253 */
10254 if (IS_GEN8(dev_priv))
10255 len += 2;
10256 }
10257
10258 /*
10259 * BSpec MI_DISPLAY_FLIP for IVB:
10260 * "The full packet must be contained within the same cache line."
10261 *
10262 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10263 * cacheline, if we ever start emitting more commands before
10264 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10265 * then do the cacheline alignment, and finally emit the
10266 * MI_DISPLAY_FLIP.
10267 */
10268 ret = intel_ring_cacheline_align(req);
10269 if (ret)
10270 return ret;
10271
10272 cs = intel_ring_begin(req, len);
10273 if (IS_ERR(cs))
10274 return PTR_ERR(cs);
10275
10276 /* Unmask the flip-done completion message. Note that the bspec says that
10277 * we should do this for both the BCS and RCS, and that we must not unmask
10278 * more than one flip event at any time (or ensure that one flip message
10279 * can be sent by waiting for flip-done prior to queueing new flips).
10280 * Experimentation says that BCS works despite DERRMR masking all
10281 * flip-done completion events and that unmasking all planes at once
10282 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10283 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10284 */
10285 if (req->engine->id == RCS) {
10286 *cs++ = MI_LOAD_REGISTER_IMM(1);
10287 *cs++ = i915_mmio_reg_offset(DERRMR);
10288 *cs++ = ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10289 DERRMR_PIPEB_PRI_FLIP_DONE |
10290 DERRMR_PIPEC_PRI_FLIP_DONE);
10291 if (IS_GEN8(dev_priv))
10292 *cs++ = MI_STORE_REGISTER_MEM_GEN8 |
10293 MI_SRM_LRM_GLOBAL_GTT;
10294 else
10295 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
10296 *cs++ = i915_mmio_reg_offset(DERRMR);
10297 *cs++ = i915_ggtt_offset(req->engine->scratch) + 256;
10298 if (IS_GEN8(dev_priv)) {
10299 *cs++ = 0;
10300 *cs++ = MI_NOOP;
10301 }
10302 }
10303
10304 *cs++ = MI_DISPLAY_FLIP_I915 | plane_bit;
10305 *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10306 *cs++ = intel_crtc->flip_work->gtt_offset;
10307 *cs++ = MI_NOOP;
10308
10309 return 0;
10310 }
10311
10312 static bool use_mmio_flip(struct intel_engine_cs *engine,
10313 struct drm_i915_gem_object *obj)
10314 {
10315 /*
10316 * This is not being used for older platforms, because
10317 * non-availability of flip done interrupt forces us to use
10318 * CS flips. Older platforms derive flip done using some clever
10319 * tricks involving the flip_pending status bits and vblank irqs.
10320 * So using MMIO flips there would disrupt this mechanism.
10321 */
10322
10323 if (engine == NULL)
10324 return true;
10325
10326 if (INTEL_GEN(engine->i915) < 5)
10327 return false;
10328
10329 if (i915.use_mmio_flip < 0)
10330 return false;
10331 else if (i915.use_mmio_flip > 0)
10332 return true;
10333 else if (i915.enable_execlists)
10334 return true;
10335
10336 return engine != i915_gem_object_last_write_engine(obj);
10337 }
10338
10339 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
10340 unsigned int rotation,
10341 struct intel_flip_work *work)
10342 {
10343 struct drm_device *dev = intel_crtc->base.dev;
10344 struct drm_i915_private *dev_priv = to_i915(dev);
10345 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10346 const enum pipe pipe = intel_crtc->pipe;
10347 u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
10348
10349 ctl = I915_READ(PLANE_CTL(pipe, 0));
10350 ctl &= ~PLANE_CTL_TILED_MASK;
10351 switch (fb->modifier) {
10352 case DRM_FORMAT_MOD_NONE:
10353 break;
10354 case I915_FORMAT_MOD_X_TILED:
10355 ctl |= PLANE_CTL_TILED_X;
10356 break;
10357 case I915_FORMAT_MOD_Y_TILED:
10358 ctl |= PLANE_CTL_TILED_Y;
10359 break;
10360 case I915_FORMAT_MOD_Yf_TILED:
10361 ctl |= PLANE_CTL_TILED_YF;
10362 break;
10363 default:
10364 MISSING_CASE(fb->modifier);
10365 }
10366
10367 /*
10368 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10369 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10370 */
10371 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10372 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10373
10374 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
10375 POSTING_READ(PLANE_SURF(pipe, 0));
10376 }
10377
10378 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
10379 struct intel_flip_work *work)
10380 {
10381 struct drm_device *dev = intel_crtc->base.dev;
10382 struct drm_i915_private *dev_priv = to_i915(dev);
10383 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10384 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
10385 u32 dspcntr;
10386
10387 dspcntr = I915_READ(reg);
10388
10389 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
10390 dspcntr |= DISPPLANE_TILED;
10391 else
10392 dspcntr &= ~DISPPLANE_TILED;
10393
10394 I915_WRITE(reg, dspcntr);
10395
10396 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
10397 POSTING_READ(DSPSURF(intel_crtc->plane));
10398 }
10399
10400 static void intel_mmio_flip_work_func(struct work_struct *w)
10401 {
10402 struct intel_flip_work *work =
10403 container_of(w, struct intel_flip_work, mmio_work);
10404 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10405 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10406 struct intel_framebuffer *intel_fb =
10407 to_intel_framebuffer(crtc->base.primary->fb);
10408 struct drm_i915_gem_object *obj = intel_fb->obj;
10409
10410 WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
10411
10412 intel_pipe_update_start(crtc);
10413
10414 if (INTEL_GEN(dev_priv) >= 9)
10415 skl_do_mmio_flip(crtc, work->rotation, work);
10416 else
10417 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10418 ilk_do_mmio_flip(crtc, work);
10419
10420 intel_pipe_update_end(crtc, work);
10421 }
10422
10423 static int intel_default_queue_flip(struct drm_device *dev,
10424 struct drm_crtc *crtc,
10425 struct drm_framebuffer *fb,
10426 struct drm_i915_gem_object *obj,
10427 struct drm_i915_gem_request *req,
10428 uint32_t flags)
10429 {
10430 return -ENODEV;
10431 }
10432
10433 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
10434 struct intel_crtc *intel_crtc,
10435 struct intel_flip_work *work)
10436 {
10437 u32 addr, vblank;
10438
10439 if (!atomic_read(&work->pending))
10440 return false;
10441
10442 smp_rmb();
10443
10444 vblank = intel_crtc_get_vblank_counter(intel_crtc);
10445 if (work->flip_ready_vblank == 0) {
10446 if (work->flip_queued_req &&
10447 !i915_gem_request_completed(work->flip_queued_req))
10448 return false;
10449
10450 work->flip_ready_vblank = vblank;
10451 }
10452
10453 if (vblank - work->flip_ready_vblank < 3)
10454 return false;
10455
10456 /* Potential stall - if we see that the flip has happened,
10457 * assume a missed interrupt. */
10458 if (INTEL_GEN(dev_priv) >= 4)
10459 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10460 else
10461 addr = I915_READ(DSPADDR(intel_crtc->plane));
10462
10463 /* There is a potential issue here with a false positive after a flip
10464 * to the same address. We could address this by checking for a
10465 * non-incrementing frame counter.
10466 */
10467 return addr == work->gtt_offset;
10468 }
10469
10470 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
10471 {
10472 struct drm_device *dev = &dev_priv->drm;
10473 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10474 struct intel_flip_work *work;
10475
10476 WARN_ON(!in_interrupt());
10477
10478 if (crtc == NULL)
10479 return;
10480
10481 spin_lock(&dev->event_lock);
10482 work = crtc->flip_work;
10483
10484 if (work != NULL && !is_mmio_work(work) &&
10485 __pageflip_stall_check_cs(dev_priv, crtc, work)) {
10486 WARN_ONCE(1,
10487 "Kicking stuck page flip: queued at %d, now %d\n",
10488 work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
10489 page_flip_completed(crtc);
10490 work = NULL;
10491 }
10492
10493 if (work != NULL && !is_mmio_work(work) &&
10494 intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
10495 intel_queue_rps_boost_for_request(work->flip_queued_req);
10496 spin_unlock(&dev->event_lock);
10497 }
10498
10499 __maybe_unused
10500 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10501 struct drm_framebuffer *fb,
10502 struct drm_pending_vblank_event *event,
10503 uint32_t page_flip_flags)
10504 {
10505 struct drm_device *dev = crtc->dev;
10506 struct drm_i915_private *dev_priv = to_i915(dev);
10507 struct drm_framebuffer *old_fb = crtc->primary->fb;
10508 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10510 struct drm_plane *primary = crtc->primary;
10511 enum pipe pipe = intel_crtc->pipe;
10512 struct intel_flip_work *work;
10513 struct intel_engine_cs *engine;
10514 bool mmio_flip;
10515 struct drm_i915_gem_request *request;
10516 struct i915_vma *vma;
10517 int ret;
10518
10519 /*
10520 * drm_mode_page_flip_ioctl() should already catch this, but double
10521 * check to be safe. In the future we may enable pageflipping from
10522 * a disabled primary plane.
10523 */
10524 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10525 return -EBUSY;
10526
10527 /* Can't change pixel format via MI display flips. */
10528 if (fb->format != crtc->primary->fb->format)
10529 return -EINVAL;
10530
10531 /*
10532 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10533 * Note that pitch changes could also affect these register.
10534 */
10535 if (INTEL_GEN(dev_priv) > 3 &&
10536 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10537 fb->pitches[0] != crtc->primary->fb->pitches[0]))
10538 return -EINVAL;
10539
10540 if (i915_terminally_wedged(&dev_priv->gpu_error))
10541 goto out_hang;
10542
10543 work = kzalloc(sizeof(*work), GFP_KERNEL);
10544 if (work == NULL)
10545 return -ENOMEM;
10546
10547 work->event = event;
10548 work->crtc = crtc;
10549 work->old_fb = old_fb;
10550 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
10551
10552 ret = drm_crtc_vblank_get(crtc);
10553 if (ret)
10554 goto free_work;
10555
10556 /* We borrow the event spin lock for protecting flip_work */
10557 spin_lock_irq(&dev->event_lock);
10558 if (intel_crtc->flip_work) {
10559 /* Before declaring the flip queue wedged, check if
10560 * the hardware completed the operation behind our backs.
10561 */
10562 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
10563 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10564 page_flip_completed(intel_crtc);
10565 } else {
10566 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10567 spin_unlock_irq(&dev->event_lock);
10568
10569 drm_crtc_vblank_put(crtc);
10570 kfree(work);
10571 return -EBUSY;
10572 }
10573 }
10574 intel_crtc->flip_work = work;
10575 spin_unlock_irq(&dev->event_lock);
10576
10577 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10578 flush_workqueue(dev_priv->wq);
10579
10580 /* Reference the objects for the scheduled work. */
10581 drm_framebuffer_reference(work->old_fb);
10582
10583 crtc->primary->fb = fb;
10584 update_state_fb(crtc->primary);
10585
10586 work->pending_flip_obj = i915_gem_object_get(obj);
10587
10588 ret = i915_mutex_lock_interruptible(dev);
10589 if (ret)
10590 goto cleanup;
10591
10592 intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
10593 if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) {
10594 ret = -EIO;
10595 goto unlock;
10596 }
10597
10598 atomic_inc(&intel_crtc->unpin_work_count);
10599
10600 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
10601 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
10602
10603 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
10604 engine = dev_priv->engine[BCS];
10605 if (fb->modifier != old_fb->modifier)
10606 /* vlv: DISPLAY_FLIP fails to change tiling */
10607 engine = NULL;
10608 } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
10609 engine = dev_priv->engine[BCS];
10610 } else if (INTEL_GEN(dev_priv) >= 7) {
10611 engine = i915_gem_object_last_write_engine(obj);
10612 if (engine == NULL || engine->id != RCS)
10613 engine = dev_priv->engine[BCS];
10614 } else {
10615 engine = dev_priv->engine[RCS];
10616 }
10617
10618 mmio_flip = use_mmio_flip(engine, obj);
10619
10620 vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
10621 if (IS_ERR(vma)) {
10622 ret = PTR_ERR(vma);
10623 goto cleanup_pending;
10624 }
10625
10626 work->old_vma = to_intel_plane_state(primary->state)->vma;
10627 to_intel_plane_state(primary->state)->vma = vma;
10628
10629 work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset;
10630 work->rotation = crtc->primary->state->rotation;
10631
10632 /*
10633 * There's the potential that the next frame will not be compatible with
10634 * FBC, so we want to call pre_update() before the actual page flip.
10635 * The problem is that pre_update() caches some information about the fb
10636 * object, so we want to do this only after the object is pinned. Let's
10637 * be on the safe side and do this immediately before scheduling the
10638 * flip.
10639 */
10640 intel_fbc_pre_update(intel_crtc, intel_crtc->config,
10641 to_intel_plane_state(primary->state));
10642
10643 if (mmio_flip) {
10644 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
10645 queue_work(system_unbound_wq, &work->mmio_work);
10646 } else {
10647 request = i915_gem_request_alloc(engine,
10648 dev_priv->kernel_context);
10649 if (IS_ERR(request)) {
10650 ret = PTR_ERR(request);
10651 goto cleanup_unpin;
10652 }
10653
10654 ret = i915_gem_request_await_object(request, obj, false);
10655 if (ret)
10656 goto cleanup_request;
10657
10658 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
10659 page_flip_flags);
10660 if (ret)
10661 goto cleanup_request;
10662
10663 intel_mark_page_flip_active(intel_crtc, work);
10664
10665 work->flip_queued_req = i915_gem_request_get(request);
10666 i915_add_request_no_flush(request);
10667 }
10668
10669 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
10670 i915_gem_track_fb(intel_fb_obj(old_fb), obj,
10671 to_intel_plane(primary)->frontbuffer_bit);
10672 mutex_unlock(&dev->struct_mutex);
10673
10674 intel_frontbuffer_flip_prepare(to_i915(dev),
10675 to_intel_plane(primary)->frontbuffer_bit);
10676
10677 trace_i915_flip_request(intel_crtc->plane, obj);
10678
10679 return 0;
10680
10681 cleanup_request:
10682 i915_add_request_no_flush(request);
10683 cleanup_unpin:
10684 to_intel_plane_state(primary->state)->vma = work->old_vma;
10685 intel_unpin_fb_vma(vma);
10686 cleanup_pending:
10687 atomic_dec(&intel_crtc->unpin_work_count);
10688 unlock:
10689 mutex_unlock(&dev->struct_mutex);
10690 cleanup:
10691 crtc->primary->fb = old_fb;
10692 update_state_fb(crtc->primary);
10693
10694 i915_gem_object_put(obj);
10695 drm_framebuffer_unreference(work->old_fb);
10696
10697 spin_lock_irq(&dev->event_lock);
10698 intel_crtc->flip_work = NULL;
10699 spin_unlock_irq(&dev->event_lock);
10700
10701 drm_crtc_vblank_put(crtc);
10702 free_work:
10703 kfree(work);
10704
10705 if (ret == -EIO) {
10706 struct drm_atomic_state *state;
10707 struct drm_plane_state *plane_state;
10708
10709 out_hang:
10710 state = drm_atomic_state_alloc(dev);
10711 if (!state)
10712 return -ENOMEM;
10713 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
10714
10715 retry:
10716 plane_state = drm_atomic_get_plane_state(state, primary);
10717 ret = PTR_ERR_OR_ZERO(plane_state);
10718 if (!ret) {
10719 drm_atomic_set_fb_for_plane(plane_state, fb);
10720
10721 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
10722 if (!ret)
10723 ret = drm_atomic_commit(state);
10724 }
10725
10726 if (ret == -EDEADLK) {
10727 drm_modeset_backoff(state->acquire_ctx);
10728 drm_atomic_state_clear(state);
10729 goto retry;
10730 }
10731
10732 drm_atomic_state_put(state);
10733
10734 if (ret == 0 && event) {
10735 spin_lock_irq(&dev->event_lock);
10736 drm_crtc_send_vblank_event(crtc, event);
10737 spin_unlock_irq(&dev->event_lock);
10738 }
10739 }
10740 return ret;
10741 }
10742
10743
10744 /**
10745 * intel_wm_need_update - Check whether watermarks need updating
10746 * @plane: drm plane
10747 * @state: new plane state
10748 *
10749 * Check current plane state versus the new one to determine whether
10750 * watermarks need to be recalculated.
10751 *
10752 * Returns true or false.
10753 */
10754 static bool intel_wm_need_update(struct drm_plane *plane,
10755 struct drm_plane_state *state)
10756 {
10757 struct intel_plane_state *new = to_intel_plane_state(state);
10758 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10759
10760 /* Update watermarks on tiling or size changes. */
10761 if (new->base.visible != cur->base.visible)
10762 return true;
10763
10764 if (!cur->base.fb || !new->base.fb)
10765 return false;
10766
10767 if (cur->base.fb->modifier != new->base.fb->modifier ||
10768 cur->base.rotation != new->base.rotation ||
10769 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10770 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10771 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10772 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10773 return true;
10774
10775 return false;
10776 }
10777
10778 static bool needs_scaling(struct intel_plane_state *state)
10779 {
10780 int src_w = drm_rect_width(&state->base.src) >> 16;
10781 int src_h = drm_rect_height(&state->base.src) >> 16;
10782 int dst_w = drm_rect_width(&state->base.dst);
10783 int dst_h = drm_rect_height(&state->base.dst);
10784
10785 return (src_w != dst_w || src_h != dst_h);
10786 }
10787
10788 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
10789 struct drm_plane_state *plane_state)
10790 {
10791 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10792 struct drm_crtc *crtc = crtc_state->crtc;
10793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10794 struct intel_plane *plane = to_intel_plane(plane_state->plane);
10795 struct drm_device *dev = crtc->dev;
10796 struct drm_i915_private *dev_priv = to_i915(dev);
10797 struct intel_plane_state *old_plane_state =
10798 to_intel_plane_state(plane->base.state);
10799 bool mode_changed = needs_modeset(crtc_state);
10800 bool was_crtc_enabled = crtc->state->active;
10801 bool is_crtc_enabled = crtc_state->active;
10802 bool turn_off, turn_on, visible, was_visible;
10803 struct drm_framebuffer *fb = plane_state->fb;
10804 int ret;
10805
10806 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10807 ret = skl_update_scaler_plane(
10808 to_intel_crtc_state(crtc_state),
10809 to_intel_plane_state(plane_state));
10810 if (ret)
10811 return ret;
10812 }
10813
10814 was_visible = old_plane_state->base.visible;
10815 visible = plane_state->visible;
10816
10817 if (!was_crtc_enabled && WARN_ON(was_visible))
10818 was_visible = false;
10819
10820 /*
10821 * Visibility is calculated as if the crtc was on, but
10822 * after scaler setup everything depends on it being off
10823 * when the crtc isn't active.
10824 *
10825 * FIXME this is wrong for watermarks. Watermarks should also
10826 * be computed as if the pipe would be active. Perhaps move
10827 * per-plane wm computation to the .check_plane() hook, and
10828 * only combine the results from all planes in the current place?
10829 */
10830 if (!is_crtc_enabled) {
10831 plane_state->visible = visible = false;
10832 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10833 }
10834
10835 if (!was_visible && !visible)
10836 return 0;
10837
10838 if (fb != old_plane_state->base.fb)
10839 pipe_config->fb_changed = true;
10840
10841 turn_off = was_visible && (!visible || mode_changed);
10842 turn_on = visible && (!was_visible || mode_changed);
10843
10844 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10845 intel_crtc->base.base.id, intel_crtc->base.name,
10846 plane->base.base.id, plane->base.name,
10847 fb ? fb->base.id : -1);
10848
10849 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10850 plane->base.base.id, plane->base.name,
10851 was_visible, visible,
10852 turn_off, turn_on, mode_changed);
10853
10854 if (turn_on) {
10855 if (INTEL_GEN(dev_priv) < 5)
10856 pipe_config->update_wm_pre = true;
10857
10858 /* must disable cxsr around plane enable/disable */
10859 if (plane->id != PLANE_CURSOR)
10860 pipe_config->disable_cxsr = true;
10861 } else if (turn_off) {
10862 if (INTEL_GEN(dev_priv) < 5)
10863 pipe_config->update_wm_post = true;
10864
10865 /* must disable cxsr around plane enable/disable */
10866 if (plane->id != PLANE_CURSOR)
10867 pipe_config->disable_cxsr = true;
10868 } else if (intel_wm_need_update(&plane->base, plane_state)) {
10869 if (INTEL_GEN(dev_priv) < 5) {
10870 /* FIXME bollocks */
10871 pipe_config->update_wm_pre = true;
10872 pipe_config->update_wm_post = true;
10873 }
10874 }
10875
10876 if (visible || was_visible)
10877 pipe_config->fb_bits |= plane->frontbuffer_bit;
10878
10879 /*
10880 * WaCxSRDisabledForSpriteScaling:ivb
10881 *
10882 * cstate->update_wm was already set above, so this flag will
10883 * take effect when we commit and program watermarks.
10884 */
10885 if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10886 needs_scaling(to_intel_plane_state(plane_state)) &&
10887 !needs_scaling(old_plane_state))
10888 pipe_config->disable_lp_wm = true;
10889
10890 return 0;
10891 }
10892
10893 static bool encoders_cloneable(const struct intel_encoder *a,
10894 const struct intel_encoder *b)
10895 {
10896 /* masks could be asymmetric, so check both ways */
10897 return a == b || (a->cloneable & (1 << b->type) &&
10898 b->cloneable & (1 << a->type));
10899 }
10900
10901 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10902 struct intel_crtc *crtc,
10903 struct intel_encoder *encoder)
10904 {
10905 struct intel_encoder *source_encoder;
10906 struct drm_connector *connector;
10907 struct drm_connector_state *connector_state;
10908 int i;
10909
10910 for_each_connector_in_state(state, connector, connector_state, i) {
10911 if (connector_state->crtc != &crtc->base)
10912 continue;
10913
10914 source_encoder =
10915 to_intel_encoder(connector_state->best_encoder);
10916 if (!encoders_cloneable(encoder, source_encoder))
10917 return false;
10918 }
10919
10920 return true;
10921 }
10922
10923 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10924 struct drm_crtc_state *crtc_state)
10925 {
10926 struct drm_device *dev = crtc->dev;
10927 struct drm_i915_private *dev_priv = to_i915(dev);
10928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10929 struct intel_crtc_state *pipe_config =
10930 to_intel_crtc_state(crtc_state);
10931 struct drm_atomic_state *state = crtc_state->state;
10932 int ret;
10933 bool mode_changed = needs_modeset(crtc_state);
10934
10935 if (mode_changed && !crtc_state->active)
10936 pipe_config->update_wm_post = true;
10937
10938 if (mode_changed && crtc_state->enable &&
10939 dev_priv->display.crtc_compute_clock &&
10940 !WARN_ON(pipe_config->shared_dpll)) {
10941 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10942 pipe_config);
10943 if (ret)
10944 return ret;
10945 }
10946
10947 if (crtc_state->color_mgmt_changed) {
10948 ret = intel_color_check(crtc, crtc_state);
10949 if (ret)
10950 return ret;
10951
10952 /*
10953 * Changing color management on Intel hardware is
10954 * handled as part of planes update.
10955 */
10956 crtc_state->planes_changed = true;
10957 }
10958
10959 ret = 0;
10960 if (dev_priv->display.compute_pipe_wm) {
10961 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10962 if (ret) {
10963 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10964 return ret;
10965 }
10966 }
10967
10968 if (dev_priv->display.compute_intermediate_wm &&
10969 !to_intel_atomic_state(state)->skip_intermediate_wm) {
10970 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10971 return 0;
10972
10973 /*
10974 * Calculate 'intermediate' watermarks that satisfy both the
10975 * old state and the new state. We can program these
10976 * immediately.
10977 */
10978 ret = dev_priv->display.compute_intermediate_wm(dev,
10979 intel_crtc,
10980 pipe_config);
10981 if (ret) {
10982 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10983 return ret;
10984 }
10985 } else if (dev_priv->display.compute_intermediate_wm) {
10986 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10987 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10988 }
10989
10990 if (INTEL_GEN(dev_priv) >= 9) {
10991 if (mode_changed)
10992 ret = skl_update_scaler_crtc(pipe_config);
10993
10994 if (!ret)
10995 ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
10996 pipe_config);
10997 }
10998
10999 return ret;
11000 }
11001
11002 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11003 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11004 .atomic_begin = intel_begin_crtc_commit,
11005 .atomic_flush = intel_finish_crtc_commit,
11006 .atomic_check = intel_crtc_atomic_check,
11007 };
11008
11009 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11010 {
11011 struct intel_connector *connector;
11012
11013 for_each_intel_connector(dev, connector) {
11014 if (connector->base.state->crtc)
11015 drm_connector_unreference(&connector->base);
11016
11017 if (connector->base.encoder) {
11018 connector->base.state->best_encoder =
11019 connector->base.encoder;
11020 connector->base.state->crtc =
11021 connector->base.encoder->crtc;
11022
11023 drm_connector_reference(&connector->base);
11024 } else {
11025 connector->base.state->best_encoder = NULL;
11026 connector->base.state->crtc = NULL;
11027 }
11028 }
11029 }
11030
11031 static void
11032 connected_sink_compute_bpp(struct intel_connector *connector,
11033 struct intel_crtc_state *pipe_config)
11034 {
11035 const struct drm_display_info *info = &connector->base.display_info;
11036 int bpp = pipe_config->pipe_bpp;
11037
11038 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11039 connector->base.base.id,
11040 connector->base.name);
11041
11042 /* Don't use an invalid EDID bpc value */
11043 if (info->bpc != 0 && info->bpc * 3 < bpp) {
11044 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11045 bpp, info->bpc * 3);
11046 pipe_config->pipe_bpp = info->bpc * 3;
11047 }
11048
11049 /* Clamp bpp to 8 on screens without EDID 1.4 */
11050 if (info->bpc == 0 && bpp > 24) {
11051 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11052 bpp);
11053 pipe_config->pipe_bpp = 24;
11054 }
11055 }
11056
11057 static int
11058 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11059 struct intel_crtc_state *pipe_config)
11060 {
11061 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11062 struct drm_atomic_state *state;
11063 struct drm_connector *connector;
11064 struct drm_connector_state *connector_state;
11065 int bpp, i;
11066
11067 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
11068 IS_CHERRYVIEW(dev_priv)))
11069 bpp = 10*3;
11070 else if (INTEL_GEN(dev_priv) >= 5)
11071 bpp = 12*3;
11072 else
11073 bpp = 8*3;
11074
11075
11076 pipe_config->pipe_bpp = bpp;
11077
11078 state = pipe_config->base.state;
11079
11080 /* Clamp display bpp to EDID value */
11081 for_each_connector_in_state(state, connector, connector_state, i) {
11082 if (connector_state->crtc != &crtc->base)
11083 continue;
11084
11085 connected_sink_compute_bpp(to_intel_connector(connector),
11086 pipe_config);
11087 }
11088
11089 return bpp;
11090 }
11091
11092 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11093 {
11094 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11095 "type: 0x%x flags: 0x%x\n",
11096 mode->crtc_clock,
11097 mode->crtc_hdisplay, mode->crtc_hsync_start,
11098 mode->crtc_hsync_end, mode->crtc_htotal,
11099 mode->crtc_vdisplay, mode->crtc_vsync_start,
11100 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11101 }
11102
11103 static inline void
11104 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
11105 unsigned int lane_count, struct intel_link_m_n *m_n)
11106 {
11107 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11108 id, lane_count,
11109 m_n->gmch_m, m_n->gmch_n,
11110 m_n->link_m, m_n->link_n, m_n->tu);
11111 }
11112
11113 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11114 struct intel_crtc_state *pipe_config,
11115 const char *context)
11116 {
11117 struct drm_device *dev = crtc->base.dev;
11118 struct drm_i915_private *dev_priv = to_i915(dev);
11119 struct drm_plane *plane;
11120 struct intel_plane *intel_plane;
11121 struct intel_plane_state *state;
11122 struct drm_framebuffer *fb;
11123
11124 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
11125 crtc->base.base.id, crtc->base.name, context);
11126
11127 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
11128 transcoder_name(pipe_config->cpu_transcoder),
11129 pipe_config->pipe_bpp, pipe_config->dither);
11130
11131 if (pipe_config->has_pch_encoder)
11132 intel_dump_m_n_config(pipe_config, "fdi",
11133 pipe_config->fdi_lanes,
11134 &pipe_config->fdi_m_n);
11135
11136 if (intel_crtc_has_dp_encoder(pipe_config)) {
11137 intel_dump_m_n_config(pipe_config, "dp m_n",
11138 pipe_config->lane_count, &pipe_config->dp_m_n);
11139 if (pipe_config->has_drrs)
11140 intel_dump_m_n_config(pipe_config, "dp m2_n2",
11141 pipe_config->lane_count,
11142 &pipe_config->dp_m2_n2);
11143 }
11144
11145 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11146 pipe_config->has_audio, pipe_config->has_infoframe);
11147
11148 DRM_DEBUG_KMS("requested mode:\n");
11149 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11150 DRM_DEBUG_KMS("adjusted mode:\n");
11151 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11152 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11153 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
11154 pipe_config->port_clock,
11155 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
11156 pipe_config->pixel_rate);
11157
11158 if (INTEL_GEN(dev_priv) >= 9)
11159 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11160 crtc->num_scalers,
11161 pipe_config->scaler_state.scaler_users,
11162 pipe_config->scaler_state.scaler_id);
11163
11164 if (HAS_GMCH_DISPLAY(dev_priv))
11165 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11166 pipe_config->gmch_pfit.control,
11167 pipe_config->gmch_pfit.pgm_ratios,
11168 pipe_config->gmch_pfit.lvds_border_bits);
11169 else
11170 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11171 pipe_config->pch_pfit.pos,
11172 pipe_config->pch_pfit.size,
11173 enableddisabled(pipe_config->pch_pfit.enabled));
11174
11175 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
11176 pipe_config->ips_enabled, pipe_config->double_wide);
11177
11178 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
11179
11180 DRM_DEBUG_KMS("planes on this crtc\n");
11181 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11182 struct drm_format_name_buf format_name;
11183 intel_plane = to_intel_plane(plane);
11184 if (intel_plane->pipe != crtc->pipe)
11185 continue;
11186
11187 state = to_intel_plane_state(plane->state);
11188 fb = state->base.fb;
11189 if (!fb) {
11190 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
11191 plane->base.id, plane->name, state->scaler_id);
11192 continue;
11193 }
11194
11195 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
11196 plane->base.id, plane->name,
11197 fb->base.id, fb->width, fb->height,
11198 drm_get_format_name(fb->format->format, &format_name));
11199 if (INTEL_GEN(dev_priv) >= 9)
11200 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
11201 state->scaler_id,
11202 state->base.src.x1 >> 16,
11203 state->base.src.y1 >> 16,
11204 drm_rect_width(&state->base.src) >> 16,
11205 drm_rect_height(&state->base.src) >> 16,
11206 state->base.dst.x1, state->base.dst.y1,
11207 drm_rect_width(&state->base.dst),
11208 drm_rect_height(&state->base.dst));
11209 }
11210 }
11211
11212 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11213 {
11214 struct drm_device *dev = state->dev;
11215 struct drm_connector *connector;
11216 unsigned int used_ports = 0;
11217 unsigned int used_mst_ports = 0;
11218
11219 /*
11220 * Walk the connector list instead of the encoder
11221 * list to detect the problem on ddi platforms
11222 * where there's just one encoder per digital port.
11223 */
11224 drm_for_each_connector(connector, dev) {
11225 struct drm_connector_state *connector_state;
11226 struct intel_encoder *encoder;
11227
11228 connector_state = drm_atomic_get_existing_connector_state(state, connector);
11229 if (!connector_state)
11230 connector_state = connector->state;
11231
11232 if (!connector_state->best_encoder)
11233 continue;
11234
11235 encoder = to_intel_encoder(connector_state->best_encoder);
11236
11237 WARN_ON(!connector_state->crtc);
11238
11239 switch (encoder->type) {
11240 unsigned int port_mask;
11241 case INTEL_OUTPUT_UNKNOWN:
11242 if (WARN_ON(!HAS_DDI(to_i915(dev))))
11243 break;
11244 case INTEL_OUTPUT_DP:
11245 case INTEL_OUTPUT_HDMI:
11246 case INTEL_OUTPUT_EDP:
11247 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11248
11249 /* the same port mustn't appear more than once */
11250 if (used_ports & port_mask)
11251 return false;
11252
11253 used_ports |= port_mask;
11254 break;
11255 case INTEL_OUTPUT_DP_MST:
11256 used_mst_ports |=
11257 1 << enc_to_mst(&encoder->base)->primary->port;
11258 break;
11259 default:
11260 break;
11261 }
11262 }
11263
11264 /* can't mix MST and SST/HDMI on the same port */
11265 if (used_ports & used_mst_ports)
11266 return false;
11267
11268 return true;
11269 }
11270
11271 static void
11272 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11273 {
11274 struct drm_i915_private *dev_priv =
11275 to_i915(crtc_state->base.crtc->dev);
11276 struct intel_crtc_scaler_state scaler_state;
11277 struct intel_dpll_hw_state dpll_hw_state;
11278 struct intel_shared_dpll *shared_dpll;
11279 struct intel_crtc_wm_state wm_state;
11280 bool force_thru;
11281
11282 /* FIXME: before the switch to atomic started, a new pipe_config was
11283 * kzalloc'd. Code that depends on any field being zero should be
11284 * fixed, so that the crtc_state can be safely duplicated. For now,
11285 * only fields that are know to not cause problems are preserved. */
11286
11287 scaler_state = crtc_state->scaler_state;
11288 shared_dpll = crtc_state->shared_dpll;
11289 dpll_hw_state = crtc_state->dpll_hw_state;
11290 force_thru = crtc_state->pch_pfit.force_thru;
11291 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11292 wm_state = crtc_state->wm;
11293
11294 /* Keep base drm_crtc_state intact, only clear our extended struct */
11295 BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
11296 memset(&crtc_state->base + 1, 0,
11297 sizeof(*crtc_state) - sizeof(crtc_state->base));
11298
11299 crtc_state->scaler_state = scaler_state;
11300 crtc_state->shared_dpll = shared_dpll;
11301 crtc_state->dpll_hw_state = dpll_hw_state;
11302 crtc_state->pch_pfit.force_thru = force_thru;
11303 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11304 crtc_state->wm = wm_state;
11305 }
11306
11307 static int
11308 intel_modeset_pipe_config(struct drm_crtc *crtc,
11309 struct intel_crtc_state *pipe_config)
11310 {
11311 struct drm_atomic_state *state = pipe_config->base.state;
11312 struct intel_encoder *encoder;
11313 struct drm_connector *connector;
11314 struct drm_connector_state *connector_state;
11315 int base_bpp, ret = -EINVAL;
11316 int i;
11317 bool retry = true;
11318
11319 clear_intel_crtc_state(pipe_config);
11320
11321 pipe_config->cpu_transcoder =
11322 (enum transcoder) to_intel_crtc(crtc)->pipe;
11323
11324 /*
11325 * Sanitize sync polarity flags based on requested ones. If neither
11326 * positive or negative polarity is requested, treat this as meaning
11327 * negative polarity.
11328 */
11329 if (!(pipe_config->base.adjusted_mode.flags &
11330 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11331 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11332
11333 if (!(pipe_config->base.adjusted_mode.flags &
11334 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11335 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11336
11337 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11338 pipe_config);
11339 if (base_bpp < 0)
11340 goto fail;
11341
11342 /*
11343 * Determine the real pipe dimensions. Note that stereo modes can
11344 * increase the actual pipe size due to the frame doubling and
11345 * insertion of additional space for blanks between the frame. This
11346 * is stored in the crtc timings. We use the requested mode to do this
11347 * computation to clearly distinguish it from the adjusted mode, which
11348 * can be changed by the connectors in the below retry loop.
11349 */
11350 drm_mode_get_hv_timing(&pipe_config->base.mode,
11351 &pipe_config->pipe_src_w,
11352 &pipe_config->pipe_src_h);
11353
11354 for_each_connector_in_state(state, connector, connector_state, i) {
11355 if (connector_state->crtc != crtc)
11356 continue;
11357
11358 encoder = to_intel_encoder(connector_state->best_encoder);
11359
11360 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11361 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11362 goto fail;
11363 }
11364
11365 /*
11366 * Determine output_types before calling the .compute_config()
11367 * hooks so that the hooks can use this information safely.
11368 */
11369 pipe_config->output_types |= 1 << encoder->type;
11370 }
11371
11372 encoder_retry:
11373 /* Ensure the port clock defaults are reset when retrying. */
11374 pipe_config->port_clock = 0;
11375 pipe_config->pixel_multiplier = 1;
11376
11377 /* Fill in default crtc timings, allow encoders to overwrite them. */
11378 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11379 CRTC_STEREO_DOUBLE);
11380
11381 /* Pass our mode to the connectors and the CRTC to give them a chance to
11382 * adjust it according to limitations or connector properties, and also
11383 * a chance to reject the mode entirely.
11384 */
11385 for_each_connector_in_state(state, connector, connector_state, i) {
11386 if (connector_state->crtc != crtc)
11387 continue;
11388
11389 encoder = to_intel_encoder(connector_state->best_encoder);
11390
11391 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
11392 DRM_DEBUG_KMS("Encoder config failure\n");
11393 goto fail;
11394 }
11395 }
11396
11397 /* Set default port clock if not overwritten by the encoder. Needs to be
11398 * done afterwards in case the encoder adjusts the mode. */
11399 if (!pipe_config->port_clock)
11400 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11401 * pipe_config->pixel_multiplier;
11402
11403 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11404 if (ret < 0) {
11405 DRM_DEBUG_KMS("CRTC fixup failed\n");
11406 goto fail;
11407 }
11408
11409 if (ret == RETRY) {
11410 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11411 ret = -EINVAL;
11412 goto fail;
11413 }
11414
11415 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11416 retry = false;
11417 goto encoder_retry;
11418 }
11419
11420 /* Dithering seems to not pass-through bits correctly when it should, so
11421 * only enable it on 6bpc panels and when its not a compliance
11422 * test requesting 6bpc video pattern.
11423 */
11424 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11425 !pipe_config->dither_force_disable;
11426 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11427 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11428
11429 fail:
11430 return ret;
11431 }
11432
11433 static void
11434 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
11435 {
11436 struct drm_crtc *crtc;
11437 struct drm_crtc_state *crtc_state;
11438 int i;
11439
11440 /* Double check state. */
11441 for_each_crtc_in_state(state, crtc, crtc_state, i) {
11442 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
11443
11444 /* Update hwmode for vblank functions */
11445 if (crtc->state->active)
11446 crtc->hwmode = crtc->state->adjusted_mode;
11447 else
11448 crtc->hwmode.crtc_clock = 0;
11449
11450 /*
11451 * Update legacy state to satisfy fbc code. This can
11452 * be removed when fbc uses the atomic state.
11453 */
11454 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11455 struct drm_plane_state *plane_state = crtc->primary->state;
11456
11457 crtc->primary->fb = plane_state->fb;
11458 crtc->x = plane_state->src_x >> 16;
11459 crtc->y = plane_state->src_y >> 16;
11460 }
11461 }
11462 }
11463
11464 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11465 {
11466 int diff;
11467
11468 if (clock1 == clock2)
11469 return true;
11470
11471 if (!clock1 || !clock2)
11472 return false;
11473
11474 diff = abs(clock1 - clock2);
11475
11476 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11477 return true;
11478
11479 return false;
11480 }
11481
11482 static bool
11483 intel_compare_m_n(unsigned int m, unsigned int n,
11484 unsigned int m2, unsigned int n2,
11485 bool exact)
11486 {
11487 if (m == m2 && n == n2)
11488 return true;
11489
11490 if (exact || !m || !n || !m2 || !n2)
11491 return false;
11492
11493 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11494
11495 if (n > n2) {
11496 while (n > n2) {
11497 m2 <<= 1;
11498 n2 <<= 1;
11499 }
11500 } else if (n < n2) {
11501 while (n < n2) {
11502 m <<= 1;
11503 n <<= 1;
11504 }
11505 }
11506
11507 if (n != n2)
11508 return false;
11509
11510 return intel_fuzzy_clock_check(m, m2);
11511 }
11512
11513 static bool
11514 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11515 struct intel_link_m_n *m2_n2,
11516 bool adjust)
11517 {
11518 if (m_n->tu == m2_n2->tu &&
11519 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11520 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11521 intel_compare_m_n(m_n->link_m, m_n->link_n,
11522 m2_n2->link_m, m2_n2->link_n, !adjust)) {
11523 if (adjust)
11524 *m2_n2 = *m_n;
11525
11526 return true;
11527 }
11528
11529 return false;
11530 }
11531
11532 static void __printf(3, 4)
11533 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11534 {
11535 char *level;
11536 unsigned int category;
11537 struct va_format vaf;
11538 va_list args;
11539
11540 if (adjust) {
11541 level = KERN_DEBUG;
11542 category = DRM_UT_KMS;
11543 } else {
11544 level = KERN_ERR;
11545 category = DRM_UT_NONE;
11546 }
11547
11548 va_start(args, format);
11549 vaf.fmt = format;
11550 vaf.va = &args;
11551
11552 drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11553
11554 va_end(args);
11555 }
11556
11557 static bool
11558 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11559 struct intel_crtc_state *current_config,
11560 struct intel_crtc_state *pipe_config,
11561 bool adjust)
11562 {
11563 bool ret = true;
11564
11565 #define PIPE_CONF_CHECK_X(name) \
11566 if (current_config->name != pipe_config->name) { \
11567 pipe_config_err(adjust, __stringify(name), \
11568 "(expected 0x%08x, found 0x%08x)\n", \
11569 current_config->name, \
11570 pipe_config->name); \
11571 ret = false; \
11572 }
11573
11574 #define PIPE_CONF_CHECK_I(name) \
11575 if (current_config->name != pipe_config->name) { \
11576 pipe_config_err(adjust, __stringify(name), \
11577 "(expected %i, found %i)\n", \
11578 current_config->name, \
11579 pipe_config->name); \
11580 ret = false; \
11581 }
11582
11583 #define PIPE_CONF_CHECK_P(name) \
11584 if (current_config->name != pipe_config->name) { \
11585 pipe_config_err(adjust, __stringify(name), \
11586 "(expected %p, found %p)\n", \
11587 current_config->name, \
11588 pipe_config->name); \
11589 ret = false; \
11590 }
11591
11592 #define PIPE_CONF_CHECK_M_N(name) \
11593 if (!intel_compare_link_m_n(&current_config->name, \
11594 &pipe_config->name,\
11595 adjust)) { \
11596 pipe_config_err(adjust, __stringify(name), \
11597 "(expected tu %i gmch %i/%i link %i/%i, " \
11598 "found tu %i, gmch %i/%i link %i/%i)\n", \
11599 current_config->name.tu, \
11600 current_config->name.gmch_m, \
11601 current_config->name.gmch_n, \
11602 current_config->name.link_m, \
11603 current_config->name.link_n, \
11604 pipe_config->name.tu, \
11605 pipe_config->name.gmch_m, \
11606 pipe_config->name.gmch_n, \
11607 pipe_config->name.link_m, \
11608 pipe_config->name.link_n); \
11609 ret = false; \
11610 }
11611
11612 /* This is required for BDW+ where there is only one set of registers for
11613 * switching between high and low RR.
11614 * This macro can be used whenever a comparison has to be made between one
11615 * hw state and multiple sw state variables.
11616 */
11617 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11618 if (!intel_compare_link_m_n(&current_config->name, \
11619 &pipe_config->name, adjust) && \
11620 !intel_compare_link_m_n(&current_config->alt_name, \
11621 &pipe_config->name, adjust)) { \
11622 pipe_config_err(adjust, __stringify(name), \
11623 "(expected tu %i gmch %i/%i link %i/%i, " \
11624 "or tu %i gmch %i/%i link %i/%i, " \
11625 "found tu %i, gmch %i/%i link %i/%i)\n", \
11626 current_config->name.tu, \
11627 current_config->name.gmch_m, \
11628 current_config->name.gmch_n, \
11629 current_config->name.link_m, \
11630 current_config->name.link_n, \
11631 current_config->alt_name.tu, \
11632 current_config->alt_name.gmch_m, \
11633 current_config->alt_name.gmch_n, \
11634 current_config->alt_name.link_m, \
11635 current_config->alt_name.link_n, \
11636 pipe_config->name.tu, \
11637 pipe_config->name.gmch_m, \
11638 pipe_config->name.gmch_n, \
11639 pipe_config->name.link_m, \
11640 pipe_config->name.link_n); \
11641 ret = false; \
11642 }
11643
11644 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11645 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11646 pipe_config_err(adjust, __stringify(name), \
11647 "(%x) (expected %i, found %i)\n", \
11648 (mask), \
11649 current_config->name & (mask), \
11650 pipe_config->name & (mask)); \
11651 ret = false; \
11652 }
11653
11654 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11655 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11656 pipe_config_err(adjust, __stringify(name), \
11657 "(expected %i, found %i)\n", \
11658 current_config->name, \
11659 pipe_config->name); \
11660 ret = false; \
11661 }
11662
11663 #define PIPE_CONF_QUIRK(quirk) \
11664 ((current_config->quirks | pipe_config->quirks) & (quirk))
11665
11666 PIPE_CONF_CHECK_I(cpu_transcoder);
11667
11668 PIPE_CONF_CHECK_I(has_pch_encoder);
11669 PIPE_CONF_CHECK_I(fdi_lanes);
11670 PIPE_CONF_CHECK_M_N(fdi_m_n);
11671
11672 PIPE_CONF_CHECK_I(lane_count);
11673 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11674
11675 if (INTEL_GEN(dev_priv) < 8) {
11676 PIPE_CONF_CHECK_M_N(dp_m_n);
11677
11678 if (current_config->has_drrs)
11679 PIPE_CONF_CHECK_M_N(dp_m2_n2);
11680 } else
11681 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11682
11683 PIPE_CONF_CHECK_X(output_types);
11684
11685 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11686 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11687 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11688 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11689 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11690 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11691
11692 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11693 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11694 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11695 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11696 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11697 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11698
11699 PIPE_CONF_CHECK_I(pixel_multiplier);
11700 PIPE_CONF_CHECK_I(has_hdmi_sink);
11701 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11702 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11703 PIPE_CONF_CHECK_I(limited_color_range);
11704 PIPE_CONF_CHECK_I(has_infoframe);
11705
11706 PIPE_CONF_CHECK_I(has_audio);
11707
11708 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11709 DRM_MODE_FLAG_INTERLACE);
11710
11711 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11712 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11713 DRM_MODE_FLAG_PHSYNC);
11714 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11715 DRM_MODE_FLAG_NHSYNC);
11716 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11717 DRM_MODE_FLAG_PVSYNC);
11718 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11719 DRM_MODE_FLAG_NVSYNC);
11720 }
11721
11722 PIPE_CONF_CHECK_X(gmch_pfit.control);
11723 /* pfit ratios are autocomputed by the hw on gen4+ */
11724 if (INTEL_GEN(dev_priv) < 4)
11725 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11726 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11727
11728 if (!adjust) {
11729 PIPE_CONF_CHECK_I(pipe_src_w);
11730 PIPE_CONF_CHECK_I(pipe_src_h);
11731
11732 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11733 if (current_config->pch_pfit.enabled) {
11734 PIPE_CONF_CHECK_X(pch_pfit.pos);
11735 PIPE_CONF_CHECK_X(pch_pfit.size);
11736 }
11737
11738 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11739 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11740 }
11741
11742 /* BDW+ don't expose a synchronous way to read the state */
11743 if (IS_HASWELL(dev_priv))
11744 PIPE_CONF_CHECK_I(ips_enabled);
11745
11746 PIPE_CONF_CHECK_I(double_wide);
11747
11748 PIPE_CONF_CHECK_P(shared_dpll);
11749 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11750 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11751 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11752 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11753 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11754 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11755 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11756 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11757 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11758
11759 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11760 PIPE_CONF_CHECK_X(dsi_pll.div);
11761
11762 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11763 PIPE_CONF_CHECK_I(pipe_bpp);
11764
11765 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11766 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11767
11768 #undef PIPE_CONF_CHECK_X
11769 #undef PIPE_CONF_CHECK_I
11770 #undef PIPE_CONF_CHECK_P
11771 #undef PIPE_CONF_CHECK_FLAGS
11772 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11773 #undef PIPE_CONF_QUIRK
11774
11775 return ret;
11776 }
11777
11778 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11779 const struct intel_crtc_state *pipe_config)
11780 {
11781 if (pipe_config->has_pch_encoder) {
11782 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11783 &pipe_config->fdi_m_n);
11784 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11785
11786 /*
11787 * FDI already provided one idea for the dotclock.
11788 * Yell if the encoder disagrees.
11789 */
11790 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11791 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11792 fdi_dotclock, dotclock);
11793 }
11794 }
11795
11796 static void verify_wm_state(struct drm_crtc *crtc,
11797 struct drm_crtc_state *new_state)
11798 {
11799 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11800 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11801 struct skl_pipe_wm hw_wm, *sw_wm;
11802 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11803 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11805 const enum pipe pipe = intel_crtc->pipe;
11806 int plane, level, max_level = ilk_wm_max_level(dev_priv);
11807
11808 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11809 return;
11810
11811 skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11812 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11813
11814 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11815 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11816
11817 /* planes */
11818 for_each_universal_plane(dev_priv, pipe, plane) {
11819 hw_plane_wm = &hw_wm.planes[plane];
11820 sw_plane_wm = &sw_wm->planes[plane];
11821
11822 /* Watermarks */
11823 for (level = 0; level <= max_level; level++) {
11824 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11825 &sw_plane_wm->wm[level]))
11826 continue;
11827
11828 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11829 pipe_name(pipe), plane + 1, level,
11830 sw_plane_wm->wm[level].plane_en,
11831 sw_plane_wm->wm[level].plane_res_b,
11832 sw_plane_wm->wm[level].plane_res_l,
11833 hw_plane_wm->wm[level].plane_en,
11834 hw_plane_wm->wm[level].plane_res_b,
11835 hw_plane_wm->wm[level].plane_res_l);
11836 }
11837
11838 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11839 &sw_plane_wm->trans_wm)) {
11840 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11841 pipe_name(pipe), plane + 1,
11842 sw_plane_wm->trans_wm.plane_en,
11843 sw_plane_wm->trans_wm.plane_res_b,
11844 sw_plane_wm->trans_wm.plane_res_l,
11845 hw_plane_wm->trans_wm.plane_en,
11846 hw_plane_wm->trans_wm.plane_res_b,
11847 hw_plane_wm->trans_wm.plane_res_l);
11848 }
11849
11850 /* DDB */
11851 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11852 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11853
11854 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11855 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11856 pipe_name(pipe), plane + 1,
11857 sw_ddb_entry->start, sw_ddb_entry->end,
11858 hw_ddb_entry->start, hw_ddb_entry->end);
11859 }
11860 }
11861
11862 /*
11863 * cursor
11864 * If the cursor plane isn't active, we may not have updated it's ddb
11865 * allocation. In that case since the ddb allocation will be updated
11866 * once the plane becomes visible, we can skip this check
11867 */
11868 if (intel_crtc->cursor_addr) {
11869 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11870 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11871
11872 /* Watermarks */
11873 for (level = 0; level <= max_level; level++) {
11874 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11875 &sw_plane_wm->wm[level]))
11876 continue;
11877
11878 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11879 pipe_name(pipe), level,
11880 sw_plane_wm->wm[level].plane_en,
11881 sw_plane_wm->wm[level].plane_res_b,
11882 sw_plane_wm->wm[level].plane_res_l,
11883 hw_plane_wm->wm[level].plane_en,
11884 hw_plane_wm->wm[level].plane_res_b,
11885 hw_plane_wm->wm[level].plane_res_l);
11886 }
11887
11888 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11889 &sw_plane_wm->trans_wm)) {
11890 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11891 pipe_name(pipe),
11892 sw_plane_wm->trans_wm.plane_en,
11893 sw_plane_wm->trans_wm.plane_res_b,
11894 sw_plane_wm->trans_wm.plane_res_l,
11895 hw_plane_wm->trans_wm.plane_en,
11896 hw_plane_wm->trans_wm.plane_res_b,
11897 hw_plane_wm->trans_wm.plane_res_l);
11898 }
11899
11900 /* DDB */
11901 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11902 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11903
11904 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11905 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11906 pipe_name(pipe),
11907 sw_ddb_entry->start, sw_ddb_entry->end,
11908 hw_ddb_entry->start, hw_ddb_entry->end);
11909 }
11910 }
11911 }
11912
11913 static void
11914 verify_connector_state(struct drm_device *dev,
11915 struct drm_atomic_state *state,
11916 struct drm_crtc *crtc)
11917 {
11918 struct drm_connector *connector;
11919 struct drm_connector_state *old_conn_state;
11920 int i;
11921
11922 for_each_connector_in_state(state, connector, old_conn_state, i) {
11923 struct drm_encoder *encoder = connector->encoder;
11924 struct drm_connector_state *state = connector->state;
11925
11926 if (state->crtc != crtc)
11927 continue;
11928
11929 intel_connector_verify_state(to_intel_connector(connector));
11930
11931 I915_STATE_WARN(state->best_encoder != encoder,
11932 "connector's atomic encoder doesn't match legacy encoder\n");
11933 }
11934 }
11935
11936 static void
11937 verify_encoder_state(struct drm_device *dev)
11938 {
11939 struct intel_encoder *encoder;
11940 struct intel_connector *connector;
11941
11942 for_each_intel_encoder(dev, encoder) {
11943 bool enabled = false;
11944 enum pipe pipe;
11945
11946 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11947 encoder->base.base.id,
11948 encoder->base.name);
11949
11950 for_each_intel_connector(dev, connector) {
11951 if (connector->base.state->best_encoder != &encoder->base)
11952 continue;
11953 enabled = true;
11954
11955 I915_STATE_WARN(connector->base.state->crtc !=
11956 encoder->base.crtc,
11957 "connector's crtc doesn't match encoder crtc\n");
11958 }
11959
11960 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11961 "encoder's enabled state mismatch "
11962 "(expected %i, found %i)\n",
11963 !!encoder->base.crtc, enabled);
11964
11965 if (!encoder->base.crtc) {
11966 bool active;
11967
11968 active = encoder->get_hw_state(encoder, &pipe);
11969 I915_STATE_WARN(active,
11970 "encoder detached but still enabled on pipe %c.\n",
11971 pipe_name(pipe));
11972 }
11973 }
11974 }
11975
11976 static void
11977 verify_crtc_state(struct drm_crtc *crtc,
11978 struct drm_crtc_state *old_crtc_state,
11979 struct drm_crtc_state *new_crtc_state)
11980 {
11981 struct drm_device *dev = crtc->dev;
11982 struct drm_i915_private *dev_priv = to_i915(dev);
11983 struct intel_encoder *encoder;
11984 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11985 struct intel_crtc_state *pipe_config, *sw_config;
11986 struct drm_atomic_state *old_state;
11987 bool active;
11988
11989 old_state = old_crtc_state->state;
11990 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
11991 pipe_config = to_intel_crtc_state(old_crtc_state);
11992 memset(pipe_config, 0, sizeof(*pipe_config));
11993 pipe_config->base.crtc = crtc;
11994 pipe_config->base.state = old_state;
11995
11996 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
11997
11998 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
11999
12000 /* hw state is inconsistent with the pipe quirk */
12001 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12002 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12003 active = new_crtc_state->active;
12004
12005 I915_STATE_WARN(new_crtc_state->active != active,
12006 "crtc active state doesn't match with hw state "
12007 "(expected %i, found %i)\n", new_crtc_state->active, active);
12008
12009 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12010 "transitional active state does not match atomic hw state "
12011 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12012
12013 for_each_encoder_on_crtc(dev, crtc, encoder) {
12014 enum pipe pipe;
12015
12016 active = encoder->get_hw_state(encoder, &pipe);
12017 I915_STATE_WARN(active != new_crtc_state->active,
12018 "[ENCODER:%i] active %i with crtc active %i\n",
12019 encoder->base.base.id, active, new_crtc_state->active);
12020
12021 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12022 "Encoder connected to wrong pipe %c\n",
12023 pipe_name(pipe));
12024
12025 if (active) {
12026 pipe_config->output_types |= 1 << encoder->type;
12027 encoder->get_config(encoder, pipe_config);
12028 }
12029 }
12030
12031 intel_crtc_compute_pixel_rate(pipe_config);
12032
12033 if (!new_crtc_state->active)
12034 return;
12035
12036 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12037
12038 sw_config = to_intel_crtc_state(crtc->state);
12039 if (!intel_pipe_config_compare(dev_priv, sw_config,
12040 pipe_config, false)) {
12041 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12042 intel_dump_pipe_config(intel_crtc, pipe_config,
12043 "[hw state]");
12044 intel_dump_pipe_config(intel_crtc, sw_config,
12045 "[sw state]");
12046 }
12047 }
12048
12049 static void
12050 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12051 struct intel_shared_dpll *pll,
12052 struct drm_crtc *crtc,
12053 struct drm_crtc_state *new_state)
12054 {
12055 struct intel_dpll_hw_state dpll_hw_state;
12056 unsigned crtc_mask;
12057 bool active;
12058
12059 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12060
12061 DRM_DEBUG_KMS("%s\n", pll->name);
12062
12063 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12064
12065 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12066 I915_STATE_WARN(!pll->on && pll->active_mask,
12067 "pll in active use but not on in sw tracking\n");
12068 I915_STATE_WARN(pll->on && !pll->active_mask,
12069 "pll is on but not used by any active crtc\n");
12070 I915_STATE_WARN(pll->on != active,
12071 "pll on state mismatch (expected %i, found %i)\n",
12072 pll->on, active);
12073 }
12074
12075 if (!crtc) {
12076 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
12077 "more active pll users than references: %x vs %x\n",
12078 pll->active_mask, pll->state.crtc_mask);
12079
12080 return;
12081 }
12082
12083 crtc_mask = 1 << drm_crtc_index(crtc);
12084
12085 if (new_state->active)
12086 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12087 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12088 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12089 else
12090 I915_STATE_WARN(pll->active_mask & crtc_mask,
12091 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12092 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12093
12094 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
12095 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12096 crtc_mask, pll->state.crtc_mask);
12097
12098 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
12099 &dpll_hw_state,
12100 sizeof(dpll_hw_state)),
12101 "pll hw state mismatch\n");
12102 }
12103
12104 static void
12105 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12106 struct drm_crtc_state *old_crtc_state,
12107 struct drm_crtc_state *new_crtc_state)
12108 {
12109 struct drm_i915_private *dev_priv = to_i915(dev);
12110 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12111 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12112
12113 if (new_state->shared_dpll)
12114 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
12115
12116 if (old_state->shared_dpll &&
12117 old_state->shared_dpll != new_state->shared_dpll) {
12118 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
12119 struct intel_shared_dpll *pll = old_state->shared_dpll;
12120
12121 I915_STATE_WARN(pll->active_mask & crtc_mask,
12122 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12123 pipe_name(drm_crtc_index(crtc)));
12124 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
12125 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12126 pipe_name(drm_crtc_index(crtc)));
12127 }
12128 }
12129
12130 static void
12131 intel_modeset_verify_crtc(struct drm_crtc *crtc,
12132 struct drm_atomic_state *state,
12133 struct drm_crtc_state *old_state,
12134 struct drm_crtc_state *new_state)
12135 {
12136 if (!needs_modeset(new_state) &&
12137 !to_intel_crtc_state(new_state)->update_pipe)
12138 return;
12139
12140 verify_wm_state(crtc, new_state);
12141 verify_connector_state(crtc->dev, state, crtc);
12142 verify_crtc_state(crtc, old_state, new_state);
12143 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
12144 }
12145
12146 static void
12147 verify_disabled_dpll_state(struct drm_device *dev)
12148 {
12149 struct drm_i915_private *dev_priv = to_i915(dev);
12150 int i;
12151
12152 for (i = 0; i < dev_priv->num_shared_dpll; i++)
12153 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12154 }
12155
12156 static void
12157 intel_modeset_verify_disabled(struct drm_device *dev,
12158 struct drm_atomic_state *state)
12159 {
12160 verify_encoder_state(dev);
12161 verify_connector_state(dev, state, NULL);
12162 verify_disabled_dpll_state(dev);
12163 }
12164
12165 static void update_scanline_offset(struct intel_crtc *crtc)
12166 {
12167 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12168
12169 /*
12170 * The scanline counter increments at the leading edge of hsync.
12171 *
12172 * On most platforms it starts counting from vtotal-1 on the
12173 * first active line. That means the scanline counter value is
12174 * always one less than what we would expect. Ie. just after
12175 * start of vblank, which also occurs at start of hsync (on the
12176 * last active line), the scanline counter will read vblank_start-1.
12177 *
12178 * On gen2 the scanline counter starts counting from 1 instead
12179 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12180 * to keep the value positive), instead of adding one.
12181 *
12182 * On HSW+ the behaviour of the scanline counter depends on the output
12183 * type. For DP ports it behaves like most other platforms, but on HDMI
12184 * there's an extra 1 line difference. So we need to add two instead of
12185 * one to the value.
12186 */
12187 if (IS_GEN2(dev_priv)) {
12188 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12189 int vtotal;
12190
12191 vtotal = adjusted_mode->crtc_vtotal;
12192 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12193 vtotal /= 2;
12194
12195 crtc->scanline_offset = vtotal - 1;
12196 } else if (HAS_DDI(dev_priv) &&
12197 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
12198 crtc->scanline_offset = 2;
12199 } else
12200 crtc->scanline_offset = 1;
12201 }
12202
12203 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12204 {
12205 struct drm_device *dev = state->dev;
12206 struct drm_i915_private *dev_priv = to_i915(dev);
12207 struct drm_crtc *crtc;
12208 struct drm_crtc_state *crtc_state;
12209 int i;
12210
12211 if (!dev_priv->display.crtc_compute_clock)
12212 return;
12213
12214 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12216 struct intel_shared_dpll *old_dpll =
12217 to_intel_crtc_state(crtc->state)->shared_dpll;
12218
12219 if (!needs_modeset(crtc_state))
12220 continue;
12221
12222 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
12223
12224 if (!old_dpll)
12225 continue;
12226
12227 intel_release_shared_dpll(old_dpll, intel_crtc, state);
12228 }
12229 }
12230
12231 /*
12232 * This implements the workaround described in the "notes" section of the mode
12233 * set sequence documentation. When going from no pipes or single pipe to
12234 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12235 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12236 */
12237 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12238 {
12239 struct drm_crtc_state *crtc_state;
12240 struct intel_crtc *intel_crtc;
12241 struct drm_crtc *crtc;
12242 struct intel_crtc_state *first_crtc_state = NULL;
12243 struct intel_crtc_state *other_crtc_state = NULL;
12244 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12245 int i;
12246
12247 /* look at all crtc's that are going to be enabled in during modeset */
12248 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12249 intel_crtc = to_intel_crtc(crtc);
12250
12251 if (!crtc_state->active || !needs_modeset(crtc_state))
12252 continue;
12253
12254 if (first_crtc_state) {
12255 other_crtc_state = to_intel_crtc_state(crtc_state);
12256 break;
12257 } else {
12258 first_crtc_state = to_intel_crtc_state(crtc_state);
12259 first_pipe = intel_crtc->pipe;
12260 }
12261 }
12262
12263 /* No workaround needed? */
12264 if (!first_crtc_state)
12265 return 0;
12266
12267 /* w/a possibly needed, check how many crtc's are already enabled. */
12268 for_each_intel_crtc(state->dev, intel_crtc) {
12269 struct intel_crtc_state *pipe_config;
12270
12271 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12272 if (IS_ERR(pipe_config))
12273 return PTR_ERR(pipe_config);
12274
12275 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12276
12277 if (!pipe_config->base.active ||
12278 needs_modeset(&pipe_config->base))
12279 continue;
12280
12281 /* 2 or more enabled crtcs means no need for w/a */
12282 if (enabled_pipe != INVALID_PIPE)
12283 return 0;
12284
12285 enabled_pipe = intel_crtc->pipe;
12286 }
12287
12288 if (enabled_pipe != INVALID_PIPE)
12289 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12290 else if (other_crtc_state)
12291 other_crtc_state->hsw_workaround_pipe = first_pipe;
12292
12293 return 0;
12294 }
12295
12296 static int intel_lock_all_pipes(struct drm_atomic_state *state)
12297 {
12298 struct drm_crtc *crtc;
12299
12300 /* Add all pipes to the state */
12301 for_each_crtc(state->dev, crtc) {
12302 struct drm_crtc_state *crtc_state;
12303
12304 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12305 if (IS_ERR(crtc_state))
12306 return PTR_ERR(crtc_state);
12307 }
12308
12309 return 0;
12310 }
12311
12312 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12313 {
12314 struct drm_crtc *crtc;
12315
12316 /*
12317 * Add all pipes to the state, and force
12318 * a modeset on all the active ones.
12319 */
12320 for_each_crtc(state->dev, crtc) {
12321 struct drm_crtc_state *crtc_state;
12322 int ret;
12323
12324 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12325 if (IS_ERR(crtc_state))
12326 return PTR_ERR(crtc_state);
12327
12328 if (!crtc_state->active || needs_modeset(crtc_state))
12329 continue;
12330
12331 crtc_state->mode_changed = true;
12332
12333 ret = drm_atomic_add_affected_connectors(state, crtc);
12334 if (ret)
12335 return ret;
12336
12337 ret = drm_atomic_add_affected_planes(state, crtc);
12338 if (ret)
12339 return ret;
12340 }
12341
12342 return 0;
12343 }
12344
12345 static int intel_modeset_checks(struct drm_atomic_state *state)
12346 {
12347 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12348 struct drm_i915_private *dev_priv = to_i915(state->dev);
12349 struct drm_crtc *crtc;
12350 struct drm_crtc_state *crtc_state;
12351 int ret = 0, i;
12352
12353 if (!check_digital_port_conflicts(state)) {
12354 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12355 return -EINVAL;
12356 }
12357
12358 intel_state->modeset = true;
12359 intel_state->active_crtcs = dev_priv->active_crtcs;
12360 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12361 intel_state->cdclk.actual = dev_priv->cdclk.actual;
12362
12363 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12364 if (crtc_state->active)
12365 intel_state->active_crtcs |= 1 << i;
12366 else
12367 intel_state->active_crtcs &= ~(1 << i);
12368
12369 if (crtc_state->active != crtc->state->active)
12370 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12371 }
12372
12373 /*
12374 * See if the config requires any additional preparation, e.g.
12375 * to adjust global state with pipes off. We need to do this
12376 * here so we can get the modeset_pipe updated config for the new
12377 * mode set on this crtc. For other crtcs we need to use the
12378 * adjusted_mode bits in the crtc directly.
12379 */
12380 if (dev_priv->display.modeset_calc_cdclk) {
12381 ret = dev_priv->display.modeset_calc_cdclk(state);
12382 if (ret < 0)
12383 return ret;
12384
12385 /*
12386 * Writes to dev_priv->cdclk.logical must protected by
12387 * holding all the crtc locks, even if we don't end up
12388 * touching the hardware
12389 */
12390 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
12391 &intel_state->cdclk.logical)) {
12392 ret = intel_lock_all_pipes(state);
12393 if (ret < 0)
12394 return ret;
12395 }
12396
12397 /* All pipes must be switched off while we change the cdclk. */
12398 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
12399 &intel_state->cdclk.actual)) {
12400 ret = intel_modeset_all_pipes(state);
12401 if (ret < 0)
12402 return ret;
12403 }
12404
12405 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12406 intel_state->cdclk.logical.cdclk,
12407 intel_state->cdclk.actual.cdclk);
12408 } else {
12409 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12410 }
12411
12412 intel_modeset_clear_plls(state);
12413
12414 if (IS_HASWELL(dev_priv))
12415 return haswell_mode_set_planes_workaround(state);
12416
12417 return 0;
12418 }
12419
12420 /*
12421 * Handle calculation of various watermark data at the end of the atomic check
12422 * phase. The code here should be run after the per-crtc and per-plane 'check'
12423 * handlers to ensure that all derived state has been updated.
12424 */
12425 static int calc_watermark_data(struct drm_atomic_state *state)
12426 {
12427 struct drm_device *dev = state->dev;
12428 struct drm_i915_private *dev_priv = to_i915(dev);
12429
12430 /* Is there platform-specific watermark information to calculate? */
12431 if (dev_priv->display.compute_global_watermarks)
12432 return dev_priv->display.compute_global_watermarks(state);
12433
12434 return 0;
12435 }
12436
12437 /**
12438 * intel_atomic_check - validate state object
12439 * @dev: drm device
12440 * @state: state to validate
12441 */
12442 static int intel_atomic_check(struct drm_device *dev,
12443 struct drm_atomic_state *state)
12444 {
12445 struct drm_i915_private *dev_priv = to_i915(dev);
12446 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12447 struct drm_crtc *crtc;
12448 struct drm_crtc_state *crtc_state;
12449 int ret, i;
12450 bool any_ms = false;
12451
12452 ret = drm_atomic_helper_check_modeset(dev, state);
12453 if (ret)
12454 return ret;
12455
12456 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12457 struct intel_crtc_state *pipe_config =
12458 to_intel_crtc_state(crtc_state);
12459
12460 /* Catch I915_MODE_FLAG_INHERITED */
12461 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
12462 crtc_state->mode_changed = true;
12463
12464 if (!needs_modeset(crtc_state))
12465 continue;
12466
12467 if (!crtc_state->enable) {
12468 any_ms = true;
12469 continue;
12470 }
12471
12472 /* FIXME: For only active_changed we shouldn't need to do any
12473 * state recomputation at all. */
12474
12475 ret = drm_atomic_add_affected_connectors(state, crtc);
12476 if (ret)
12477 return ret;
12478
12479 ret = intel_modeset_pipe_config(crtc, pipe_config);
12480 if (ret) {
12481 intel_dump_pipe_config(to_intel_crtc(crtc),
12482 pipe_config, "[failed]");
12483 return ret;
12484 }
12485
12486 if (i915.fastboot &&
12487 intel_pipe_config_compare(dev_priv,
12488 to_intel_crtc_state(crtc->state),
12489 pipe_config, true)) {
12490 crtc_state->mode_changed = false;
12491 to_intel_crtc_state(crtc_state)->update_pipe = true;
12492 }
12493
12494 if (needs_modeset(crtc_state))
12495 any_ms = true;
12496
12497 ret = drm_atomic_add_affected_planes(state, crtc);
12498 if (ret)
12499 return ret;
12500
12501 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12502 needs_modeset(crtc_state) ?
12503 "[modeset]" : "[fastset]");
12504 }
12505
12506 if (any_ms) {
12507 ret = intel_modeset_checks(state);
12508
12509 if (ret)
12510 return ret;
12511 } else {
12512 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12513 }
12514
12515 ret = drm_atomic_helper_check_planes(dev, state);
12516 if (ret)
12517 return ret;
12518
12519 intel_fbc_choose_crtc(dev_priv, state);
12520 return calc_watermark_data(state);
12521 }
12522
12523 static int intel_atomic_prepare_commit(struct drm_device *dev,
12524 struct drm_atomic_state *state)
12525 {
12526 struct drm_i915_private *dev_priv = to_i915(dev);
12527 struct drm_crtc_state *crtc_state;
12528 struct drm_crtc *crtc;
12529 int i, ret;
12530
12531 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12532 if (state->legacy_cursor_update)
12533 continue;
12534
12535 ret = intel_crtc_wait_for_pending_flips(crtc);
12536 if (ret)
12537 return ret;
12538
12539 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
12540 flush_workqueue(dev_priv->wq);
12541 }
12542
12543 ret = mutex_lock_interruptible(&dev->struct_mutex);
12544 if (ret)
12545 return ret;
12546
12547 ret = drm_atomic_helper_prepare_planes(dev, state);
12548 mutex_unlock(&dev->struct_mutex);
12549
12550 return ret;
12551 }
12552
12553 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12554 {
12555 struct drm_device *dev = crtc->base.dev;
12556
12557 if (!dev->max_vblank_count)
12558 return drm_accurate_vblank_count(&crtc->base);
12559
12560 return dev->driver->get_vblank_counter(dev, crtc->pipe);
12561 }
12562
12563 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
12564 struct drm_i915_private *dev_priv,
12565 unsigned crtc_mask)
12566 {
12567 unsigned last_vblank_count[I915_MAX_PIPES];
12568 enum pipe pipe;
12569 int ret;
12570
12571 if (!crtc_mask)
12572 return;
12573
12574 for_each_pipe(dev_priv, pipe) {
12575 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12576 pipe);
12577
12578 if (!((1 << pipe) & crtc_mask))
12579 continue;
12580
12581 ret = drm_crtc_vblank_get(&crtc->base);
12582 if (WARN_ON(ret != 0)) {
12583 crtc_mask &= ~(1 << pipe);
12584 continue;
12585 }
12586
12587 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
12588 }
12589
12590 for_each_pipe(dev_priv, pipe) {
12591 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12592 pipe);
12593 long lret;
12594
12595 if (!((1 << pipe) & crtc_mask))
12596 continue;
12597
12598 lret = wait_event_timeout(dev->vblank[pipe].queue,
12599 last_vblank_count[pipe] !=
12600 drm_crtc_vblank_count(&crtc->base),
12601 msecs_to_jiffies(50));
12602
12603 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
12604
12605 drm_crtc_vblank_put(&crtc->base);
12606 }
12607 }
12608
12609 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
12610 {
12611 /* fb updated, need to unpin old fb */
12612 if (crtc_state->fb_changed)
12613 return true;
12614
12615 /* wm changes, need vblank before final wm's */
12616 if (crtc_state->update_wm_post)
12617 return true;
12618
12619 if (crtc_state->wm.need_postvbl_update)
12620 return true;
12621
12622 return false;
12623 }
12624
12625 static void intel_update_crtc(struct drm_crtc *crtc,
12626 struct drm_atomic_state *state,
12627 struct drm_crtc_state *old_crtc_state,
12628 unsigned int *crtc_vblank_mask)
12629 {
12630 struct drm_device *dev = crtc->dev;
12631 struct drm_i915_private *dev_priv = to_i915(dev);
12632 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12633 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state);
12634 bool modeset = needs_modeset(crtc->state);
12635
12636 if (modeset) {
12637 update_scanline_offset(intel_crtc);
12638 dev_priv->display.crtc_enable(pipe_config, state);
12639 } else {
12640 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
12641 }
12642
12643 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12644 intel_fbc_enable(
12645 intel_crtc, pipe_config,
12646 to_intel_plane_state(crtc->primary->state));
12647 }
12648
12649 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12650
12651 if (needs_vblank_wait(pipe_config))
12652 *crtc_vblank_mask |= drm_crtc_mask(crtc);
12653 }
12654
12655 static void intel_update_crtcs(struct drm_atomic_state *state,
12656 unsigned int *crtc_vblank_mask)
12657 {
12658 struct drm_crtc *crtc;
12659 struct drm_crtc_state *old_crtc_state;
12660 int i;
12661
12662 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
12663 if (!crtc->state->active)
12664 continue;
12665
12666 intel_update_crtc(crtc, state, old_crtc_state,
12667 crtc_vblank_mask);
12668 }
12669 }
12670
12671 static void skl_update_crtcs(struct drm_atomic_state *state,
12672 unsigned int *crtc_vblank_mask)
12673 {
12674 struct drm_i915_private *dev_priv = to_i915(state->dev);
12675 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12676 struct drm_crtc *crtc;
12677 struct intel_crtc *intel_crtc;
12678 struct drm_crtc_state *old_crtc_state;
12679 struct intel_crtc_state *cstate;
12680 unsigned int updated = 0;
12681 bool progress;
12682 enum pipe pipe;
12683 int i;
12684
12685 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12686
12687 for_each_crtc_in_state(state, crtc, old_crtc_state, i)
12688 /* ignore allocations for crtc's that have been turned off. */
12689 if (crtc->state->active)
12690 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12691
12692 /*
12693 * Whenever the number of active pipes changes, we need to make sure we
12694 * update the pipes in the right order so that their ddb allocations
12695 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12696 * cause pipe underruns and other bad stuff.
12697 */
12698 do {
12699 progress = false;
12700
12701 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
12702 bool vbl_wait = false;
12703 unsigned int cmask = drm_crtc_mask(crtc);
12704
12705 intel_crtc = to_intel_crtc(crtc);
12706 cstate = to_intel_crtc_state(crtc->state);
12707 pipe = intel_crtc->pipe;
12708
12709 if (updated & cmask || !cstate->base.active)
12710 continue;
12711
12712 if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
12713 continue;
12714
12715 updated |= cmask;
12716 entries[i] = &cstate->wm.skl.ddb;
12717
12718 /*
12719 * If this is an already active pipe, it's DDB changed,
12720 * and this isn't the last pipe that needs updating
12721 * then we need to wait for a vblank to pass for the
12722 * new ddb allocation to take effect.
12723 */
12724 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12725 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12726 !crtc->state->active_changed &&
12727 intel_state->wm_results.dirty_pipes != updated)
12728 vbl_wait = true;
12729
12730 intel_update_crtc(crtc, state, old_crtc_state,
12731 crtc_vblank_mask);
12732
12733 if (vbl_wait)
12734 intel_wait_for_vblank(dev_priv, pipe);
12735
12736 progress = true;
12737 }
12738 } while (progress);
12739 }
12740
12741 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12742 {
12743 struct intel_atomic_state *state, *next;
12744 struct llist_node *freed;
12745
12746 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12747 llist_for_each_entry_safe(state, next, freed, freed)
12748 drm_atomic_state_put(&state->base);
12749 }
12750
12751 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12752 {
12753 struct drm_i915_private *dev_priv =
12754 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12755
12756 intel_atomic_helper_free_state(dev_priv);
12757 }
12758
12759 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12760 {
12761 struct drm_device *dev = state->dev;
12762 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12763 struct drm_i915_private *dev_priv = to_i915(dev);
12764 struct drm_crtc_state *old_crtc_state;
12765 struct drm_crtc *crtc;
12766 struct intel_crtc_state *intel_cstate;
12767 bool hw_check = intel_state->modeset;
12768 u64 put_domains[I915_MAX_PIPES] = {};
12769 unsigned crtc_vblank_mask = 0;
12770 int i;
12771
12772 drm_atomic_helper_wait_for_dependencies(state);
12773
12774 if (intel_state->modeset)
12775 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12776
12777 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
12778 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12779
12780 if (needs_modeset(crtc->state) ||
12781 to_intel_crtc_state(crtc->state)->update_pipe) {
12782 hw_check = true;
12783
12784 put_domains[to_intel_crtc(crtc)->pipe] =
12785 modeset_get_crtc_power_domains(crtc,
12786 to_intel_crtc_state(crtc->state));
12787 }
12788
12789 if (!needs_modeset(crtc->state))
12790 continue;
12791
12792 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
12793
12794 if (old_crtc_state->active) {
12795 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12796 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12797 intel_crtc->active = false;
12798 intel_fbc_disable(intel_crtc);
12799 intel_disable_shared_dpll(intel_crtc);
12800
12801 /*
12802 * Underruns don't always raise
12803 * interrupts, so check manually.
12804 */
12805 intel_check_cpu_fifo_underruns(dev_priv);
12806 intel_check_pch_fifo_underruns(dev_priv);
12807
12808 if (!crtc->state->active) {
12809 /*
12810 * Make sure we don't call initial_watermarks
12811 * for ILK-style watermark updates.
12812 *
12813 * No clue what this is supposed to achieve.
12814 */
12815 if (INTEL_GEN(dev_priv) >= 9)
12816 dev_priv->display.initial_watermarks(intel_state,
12817 to_intel_crtc_state(crtc->state));
12818 }
12819 }
12820 }
12821
12822 /* Only after disabling all output pipelines that will be changed can we
12823 * update the the output configuration. */
12824 intel_modeset_update_crtc_state(state);
12825
12826 if (intel_state->modeset) {
12827 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12828
12829 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12830
12831 /*
12832 * SKL workaround: bspec recommends we disable the SAGV when we
12833 * have more then one pipe enabled
12834 */
12835 if (!intel_can_enable_sagv(state))
12836 intel_disable_sagv(dev_priv);
12837
12838 intel_modeset_verify_disabled(dev, state);
12839 }
12840
12841 /* Complete the events for pipes that have now been disabled */
12842 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
12843 bool modeset = needs_modeset(crtc->state);
12844
12845 /* Complete events for now disable pipes here. */
12846 if (modeset && !crtc->state->active && crtc->state->event) {
12847 spin_lock_irq(&dev->event_lock);
12848 drm_crtc_send_vblank_event(crtc, crtc->state->event);
12849 spin_unlock_irq(&dev->event_lock);
12850
12851 crtc->state->event = NULL;
12852 }
12853 }
12854
12855 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12856 dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
12857
12858 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12859 * already, but still need the state for the delayed optimization. To
12860 * fix this:
12861 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12862 * - schedule that vblank worker _before_ calling hw_done
12863 * - at the start of commit_tail, cancel it _synchrously
12864 * - switch over to the vblank wait helper in the core after that since
12865 * we don't need out special handling any more.
12866 */
12867 if (!state->legacy_cursor_update)
12868 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
12869
12870 /*
12871 * Now that the vblank has passed, we can go ahead and program the
12872 * optimal watermarks on platforms that need two-step watermark
12873 * programming.
12874 *
12875 * TODO: Move this (and other cleanup) to an async worker eventually.
12876 */
12877 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
12878 intel_cstate = to_intel_crtc_state(crtc->state);
12879
12880 if (dev_priv->display.optimize_watermarks)
12881 dev_priv->display.optimize_watermarks(intel_state,
12882 intel_cstate);
12883 }
12884
12885 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
12886 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12887
12888 if (put_domains[i])
12889 modeset_put_power_domains(dev_priv, put_domains[i]);
12890
12891 intel_modeset_verify_crtc(crtc, state, old_crtc_state, crtc->state);
12892 }
12893
12894 if (intel_state->modeset && intel_can_enable_sagv(state))
12895 intel_enable_sagv(dev_priv);
12896
12897 drm_atomic_helper_commit_hw_done(state);
12898
12899 if (intel_state->modeset)
12900 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12901
12902 mutex_lock(&dev->struct_mutex);
12903 drm_atomic_helper_cleanup_planes(dev, state);
12904 mutex_unlock(&dev->struct_mutex);
12905
12906 drm_atomic_helper_commit_cleanup_done(state);
12907
12908 drm_atomic_state_put(state);
12909
12910 /* As one of the primary mmio accessors, KMS has a high likelihood
12911 * of triggering bugs in unclaimed access. After we finish
12912 * modesetting, see if an error has been flagged, and if so
12913 * enable debugging for the next modeset - and hope we catch
12914 * the culprit.
12915 *
12916 * XXX note that we assume display power is on at this point.
12917 * This might hold true now but we need to add pm helper to check
12918 * unclaimed only when the hardware is on, as atomic commits
12919 * can happen also when the device is completely off.
12920 */
12921 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12922
12923 intel_atomic_helper_free_state(dev_priv);
12924 }
12925
12926 static void intel_atomic_commit_work(struct work_struct *work)
12927 {
12928 struct drm_atomic_state *state =
12929 container_of(work, struct drm_atomic_state, commit_work);
12930
12931 intel_atomic_commit_tail(state);
12932 }
12933
12934 static int __i915_sw_fence_call
12935 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12936 enum i915_sw_fence_notify notify)
12937 {
12938 struct intel_atomic_state *state =
12939 container_of(fence, struct intel_atomic_state, commit_ready);
12940
12941 switch (notify) {
12942 case FENCE_COMPLETE:
12943 if (state->base.commit_work.func)
12944 queue_work(system_unbound_wq, &state->base.commit_work);
12945 break;
12946
12947 case FENCE_FREE:
12948 {
12949 struct intel_atomic_helper *helper =
12950 &to_i915(state->base.dev)->atomic_helper;
12951
12952 if (llist_add(&state->freed, &helper->free_list))
12953 schedule_work(&helper->free_work);
12954 break;
12955 }
12956 }
12957
12958 return NOTIFY_DONE;
12959 }
12960
12961 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12962 {
12963 struct drm_plane_state *old_plane_state;
12964 struct drm_plane *plane;
12965 int i;
12966
12967 for_each_plane_in_state(state, plane, old_plane_state, i)
12968 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
12969 intel_fb_obj(plane->state->fb),
12970 to_intel_plane(plane)->frontbuffer_bit);
12971 }
12972
12973 /**
12974 * intel_atomic_commit - commit validated state object
12975 * @dev: DRM device
12976 * @state: the top-level driver state object
12977 * @nonblock: nonblocking commit
12978 *
12979 * This function commits a top-level state object that has been validated
12980 * with drm_atomic_helper_check().
12981 *
12982 * RETURNS
12983 * Zero for success or -errno.
12984 */
12985 static int intel_atomic_commit(struct drm_device *dev,
12986 struct drm_atomic_state *state,
12987 bool nonblock)
12988 {
12989 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12990 struct drm_i915_private *dev_priv = to_i915(dev);
12991 int ret = 0;
12992
12993 /*
12994 * The intel_legacy_cursor_update() fast path takes care
12995 * of avoiding the vblank waits for simple cursor
12996 * movement and flips. For cursor on/off and size changes,
12997 * we want to perform the vblank waits so that watermark
12998 * updates happen during the correct frames. Gen9+ have
12999 * double buffered watermarks and so shouldn't need this.
13000 */
13001 if (INTEL_GEN(dev_priv) < 9)
13002 state->legacy_cursor_update = false;
13003
13004 ret = drm_atomic_helper_setup_commit(state, nonblock);
13005 if (ret)
13006 return ret;
13007
13008 drm_atomic_state_get(state);
13009 i915_sw_fence_init(&intel_state->commit_ready,
13010 intel_atomic_commit_ready);
13011
13012 ret = intel_atomic_prepare_commit(dev, state);
13013 if (ret) {
13014 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13015 i915_sw_fence_commit(&intel_state->commit_ready);
13016 return ret;
13017 }
13018
13019 drm_atomic_helper_swap_state(state, true);
13020 dev_priv->wm.distrust_bios_wm = false;
13021 intel_shared_dpll_swap_state(state);
13022 intel_atomic_track_fbs(state);
13023
13024 if (intel_state->modeset) {
13025 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13026 sizeof(intel_state->min_pixclk));
13027 dev_priv->active_crtcs = intel_state->active_crtcs;
13028 dev_priv->cdclk.logical = intel_state->cdclk.logical;
13029 dev_priv->cdclk.actual = intel_state->cdclk.actual;
13030 }
13031
13032 drm_atomic_state_get(state);
13033 INIT_WORK(&state->commit_work,
13034 nonblock ? intel_atomic_commit_work : NULL);
13035
13036 i915_sw_fence_commit(&intel_state->commit_ready);
13037 if (!nonblock) {
13038 i915_sw_fence_wait(&intel_state->commit_ready);
13039 intel_atomic_commit_tail(state);
13040 }
13041
13042 return 0;
13043 }
13044
13045 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13046 {
13047 struct drm_device *dev = crtc->dev;
13048 struct drm_atomic_state *state;
13049 struct drm_crtc_state *crtc_state;
13050 int ret;
13051
13052 state = drm_atomic_state_alloc(dev);
13053 if (!state) {
13054 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
13055 crtc->base.id, crtc->name);
13056 return;
13057 }
13058
13059 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13060
13061 retry:
13062 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13063 ret = PTR_ERR_OR_ZERO(crtc_state);
13064 if (!ret) {
13065 if (!crtc_state->active)
13066 goto out;
13067
13068 crtc_state->mode_changed = true;
13069 ret = drm_atomic_commit(state);
13070 }
13071
13072 if (ret == -EDEADLK) {
13073 drm_atomic_state_clear(state);
13074 drm_modeset_backoff(state->acquire_ctx);
13075 goto retry;
13076 }
13077
13078 out:
13079 drm_atomic_state_put(state);
13080 }
13081
13082 /*
13083 * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
13084 * drm_atomic_helper_legacy_gamma_set() directly.
13085 */
13086 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
13087 u16 *red, u16 *green, u16 *blue,
13088 uint32_t size)
13089 {
13090 struct drm_device *dev = crtc->dev;
13091 struct drm_mode_config *config = &dev->mode_config;
13092 struct drm_crtc_state *state;
13093 int ret;
13094
13095 ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
13096 if (ret)
13097 return ret;
13098
13099 /*
13100 * Make sure we update the legacy properties so this works when
13101 * atomic is not enabled.
13102 */
13103
13104 state = crtc->state;
13105
13106 drm_object_property_set_value(&crtc->base,
13107 config->degamma_lut_property,
13108 (state->degamma_lut) ?
13109 state->degamma_lut->base.id : 0);
13110
13111 drm_object_property_set_value(&crtc->base,
13112 config->ctm_property,
13113 (state->ctm) ?
13114 state->ctm->base.id : 0);
13115
13116 drm_object_property_set_value(&crtc->base,
13117 config->gamma_lut_property,
13118 (state->gamma_lut) ?
13119 state->gamma_lut->base.id : 0);
13120
13121 return 0;
13122 }
13123
13124 static const struct drm_crtc_funcs intel_crtc_funcs = {
13125 .gamma_set = intel_atomic_legacy_gamma_set,
13126 .set_config = drm_atomic_helper_set_config,
13127 .set_property = drm_atomic_helper_crtc_set_property,
13128 .destroy = intel_crtc_destroy,
13129 .page_flip = drm_atomic_helper_page_flip,
13130 .atomic_duplicate_state = intel_crtc_duplicate_state,
13131 .atomic_destroy_state = intel_crtc_destroy_state,
13132 .set_crc_source = intel_crtc_set_crc_source,
13133 };
13134
13135 /**
13136 * intel_prepare_plane_fb - Prepare fb for usage on plane
13137 * @plane: drm plane to prepare for
13138 * @fb: framebuffer to prepare for presentation
13139 *
13140 * Prepares a framebuffer for usage on a display plane. Generally this
13141 * involves pinning the underlying object and updating the frontbuffer tracking
13142 * bits. Some older platforms need special physical address handling for
13143 * cursor planes.
13144 *
13145 * Must be called with struct_mutex held.
13146 *
13147 * Returns 0 on success, negative error code on failure.
13148 */
13149 int
13150 intel_prepare_plane_fb(struct drm_plane *plane,
13151 struct drm_plane_state *new_state)
13152 {
13153 struct intel_atomic_state *intel_state =
13154 to_intel_atomic_state(new_state->state);
13155 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13156 struct drm_framebuffer *fb = new_state->fb;
13157 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13158 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13159 int ret;
13160
13161 if (obj) {
13162 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13163 INTEL_INFO(dev_priv)->cursor_needs_physical) {
13164 const int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
13165
13166 ret = i915_gem_object_attach_phys(obj, align);
13167 if (ret) {
13168 DRM_DEBUG_KMS("failed to attach phys object\n");
13169 return ret;
13170 }
13171 } else {
13172 struct i915_vma *vma;
13173
13174 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13175 if (IS_ERR(vma)) {
13176 DRM_DEBUG_KMS("failed to pin object\n");
13177 return PTR_ERR(vma);
13178 }
13179
13180 to_intel_plane_state(new_state)->vma = vma;
13181 }
13182 }
13183
13184 if (!obj && !old_obj)
13185 return 0;
13186
13187 if (old_obj) {
13188 struct drm_crtc_state *crtc_state =
13189 drm_atomic_get_existing_crtc_state(new_state->state,
13190 plane->state->crtc);
13191
13192 /* Big Hammer, we also need to ensure that any pending
13193 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13194 * current scanout is retired before unpinning the old
13195 * framebuffer. Note that we rely on userspace rendering
13196 * into the buffer attached to the pipe they are waiting
13197 * on. If not, userspace generates a GPU hang with IPEHR
13198 * point to the MI_WAIT_FOR_EVENT.
13199 *
13200 * This should only fail upon a hung GPU, in which case we
13201 * can safely continue.
13202 */
13203 if (needs_modeset(crtc_state)) {
13204 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13205 old_obj->resv, NULL,
13206 false, 0,
13207 GFP_KERNEL);
13208 if (ret < 0)
13209 return ret;
13210 }
13211 }
13212
13213 if (new_state->fence) { /* explicit fencing */
13214 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
13215 new_state->fence,
13216 I915_FENCE_TIMEOUT,
13217 GFP_KERNEL);
13218 if (ret < 0)
13219 return ret;
13220 }
13221
13222 if (!obj)
13223 return 0;
13224
13225 if (!new_state->fence) { /* implicit fencing */
13226 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13227 obj->resv, NULL,
13228 false, I915_FENCE_TIMEOUT,
13229 GFP_KERNEL);
13230 if (ret < 0)
13231 return ret;
13232
13233 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
13234 }
13235
13236 return 0;
13237 }
13238
13239 /**
13240 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13241 * @plane: drm plane to clean up for
13242 * @fb: old framebuffer that was on plane
13243 *
13244 * Cleans up a framebuffer that has just been removed from a plane.
13245 *
13246 * Must be called with struct_mutex held.
13247 */
13248 void
13249 intel_cleanup_plane_fb(struct drm_plane *plane,
13250 struct drm_plane_state *old_state)
13251 {
13252 struct i915_vma *vma;
13253
13254 /* Should only be called after a successful intel_prepare_plane_fb()! */
13255 vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
13256 if (vma)
13257 intel_unpin_fb_vma(vma);
13258 }
13259
13260 int
13261 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13262 {
13263 struct drm_i915_private *dev_priv;
13264 int max_scale;
13265 int crtc_clock, max_dotclk;
13266
13267 if (!intel_crtc || !crtc_state->base.enable)
13268 return DRM_PLANE_HELPER_NO_SCALING;
13269
13270 dev_priv = to_i915(intel_crtc->base.dev);
13271
13272 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13273 max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
13274
13275 if (IS_GEMINILAKE(dev_priv))
13276 max_dotclk *= 2;
13277
13278 if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
13279 return DRM_PLANE_HELPER_NO_SCALING;
13280
13281 /*
13282 * skl max scale is lower of:
13283 * close to 3 but not 3, -1 is for that purpose
13284 * or
13285 * cdclk/crtc_clock
13286 */
13287 max_scale = min((1 << 16) * 3 - 1,
13288 (1 << 8) * ((max_dotclk << 8) / crtc_clock));
13289
13290 return max_scale;
13291 }
13292
13293 static int
13294 intel_check_primary_plane(struct drm_plane *plane,
13295 struct intel_crtc_state *crtc_state,
13296 struct intel_plane_state *state)
13297 {
13298 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13299 struct drm_crtc *crtc = state->base.crtc;
13300 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13301 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13302 bool can_position = false;
13303 int ret;
13304
13305 if (INTEL_GEN(dev_priv) >= 9) {
13306 /* use scaler when colorkey is not required */
13307 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13308 min_scale = 1;
13309 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13310 }
13311 can_position = true;
13312 }
13313
13314 ret = drm_plane_helper_check_state(&state->base,
13315 &state->clip,
13316 min_scale, max_scale,
13317 can_position, true);
13318 if (ret)
13319 return ret;
13320
13321 if (!state->base.fb)
13322 return 0;
13323
13324 if (INTEL_GEN(dev_priv) >= 9) {
13325 ret = skl_check_plane_surface(state);
13326 if (ret)
13327 return ret;
13328 }
13329
13330 return 0;
13331 }
13332
13333 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13334 struct drm_crtc_state *old_crtc_state)
13335 {
13336 struct drm_device *dev = crtc->dev;
13337 struct drm_i915_private *dev_priv = to_i915(dev);
13338 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13339 struct intel_crtc_state *intel_cstate =
13340 to_intel_crtc_state(crtc->state);
13341 struct intel_crtc_state *old_intel_cstate =
13342 to_intel_crtc_state(old_crtc_state);
13343 struct intel_atomic_state *old_intel_state =
13344 to_intel_atomic_state(old_crtc_state->state);
13345 bool modeset = needs_modeset(crtc->state);
13346
13347 if (!modeset &&
13348 (intel_cstate->base.color_mgmt_changed ||
13349 intel_cstate->update_pipe)) {
13350 intel_color_set_csc(crtc->state);
13351 intel_color_load_luts(crtc->state);
13352 }
13353
13354 /* Perform vblank evasion around commit operation */
13355 intel_pipe_update_start(intel_crtc);
13356
13357 if (modeset)
13358 goto out;
13359
13360 if (intel_cstate->update_pipe)
13361 intel_update_pipe_config(intel_crtc, old_intel_cstate);
13362 else if (INTEL_GEN(dev_priv) >= 9)
13363 skl_detach_scalers(intel_crtc);
13364
13365 out:
13366 if (dev_priv->display.atomic_update_watermarks)
13367 dev_priv->display.atomic_update_watermarks(old_intel_state,
13368 intel_cstate);
13369 }
13370
13371 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13372 struct drm_crtc_state *old_crtc_state)
13373 {
13374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13375
13376 intel_pipe_update_end(intel_crtc, NULL);
13377 }
13378
13379 /**
13380 * intel_plane_destroy - destroy a plane
13381 * @plane: plane to destroy
13382 *
13383 * Common destruction function for all types of planes (primary, cursor,
13384 * sprite).
13385 */
13386 void intel_plane_destroy(struct drm_plane *plane)
13387 {
13388 drm_plane_cleanup(plane);
13389 kfree(to_intel_plane(plane));
13390 }
13391
13392 const struct drm_plane_funcs intel_plane_funcs = {
13393 .update_plane = drm_atomic_helper_update_plane,
13394 .disable_plane = drm_atomic_helper_disable_plane,
13395 .destroy = intel_plane_destroy,
13396 .set_property = drm_atomic_helper_plane_set_property,
13397 .atomic_get_property = intel_plane_atomic_get_property,
13398 .atomic_set_property = intel_plane_atomic_set_property,
13399 .atomic_duplicate_state = intel_plane_duplicate_state,
13400 .atomic_destroy_state = intel_plane_destroy_state,
13401 };
13402
13403 static int
13404 intel_legacy_cursor_update(struct drm_plane *plane,
13405 struct drm_crtc *crtc,
13406 struct drm_framebuffer *fb,
13407 int crtc_x, int crtc_y,
13408 unsigned int crtc_w, unsigned int crtc_h,
13409 uint32_t src_x, uint32_t src_y,
13410 uint32_t src_w, uint32_t src_h)
13411 {
13412 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13413 int ret;
13414 struct drm_plane_state *old_plane_state, *new_plane_state;
13415 struct intel_plane *intel_plane = to_intel_plane(plane);
13416 struct drm_framebuffer *old_fb;
13417 struct drm_crtc_state *crtc_state = crtc->state;
13418 struct i915_vma *old_vma;
13419
13420 /*
13421 * When crtc is inactive or there is a modeset pending,
13422 * wait for it to complete in the slowpath
13423 */
13424 if (!crtc_state->active || needs_modeset(crtc_state) ||
13425 to_intel_crtc_state(crtc_state)->update_pipe)
13426 goto slow;
13427
13428 old_plane_state = plane->state;
13429
13430 /*
13431 * If any parameters change that may affect watermarks,
13432 * take the slowpath. Only changing fb or position should be
13433 * in the fastpath.
13434 */
13435 if (old_plane_state->crtc != crtc ||
13436 old_plane_state->src_w != src_w ||
13437 old_plane_state->src_h != src_h ||
13438 old_plane_state->crtc_w != crtc_w ||
13439 old_plane_state->crtc_h != crtc_h ||
13440 !old_plane_state->fb != !fb)
13441 goto slow;
13442
13443 new_plane_state = intel_plane_duplicate_state(plane);
13444 if (!new_plane_state)
13445 return -ENOMEM;
13446
13447 drm_atomic_set_fb_for_plane(new_plane_state, fb);
13448
13449 new_plane_state->src_x = src_x;
13450 new_plane_state->src_y = src_y;
13451 new_plane_state->src_w = src_w;
13452 new_plane_state->src_h = src_h;
13453 new_plane_state->crtc_x = crtc_x;
13454 new_plane_state->crtc_y = crtc_y;
13455 new_plane_state->crtc_w = crtc_w;
13456 new_plane_state->crtc_h = crtc_h;
13457
13458 ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13459 to_intel_plane_state(new_plane_state));
13460 if (ret)
13461 goto out_free;
13462
13463 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13464 if (ret)
13465 goto out_free;
13466
13467 if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13468 int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
13469
13470 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13471 if (ret) {
13472 DRM_DEBUG_KMS("failed to attach phys object\n");
13473 goto out_unlock;
13474 }
13475 } else {
13476 struct i915_vma *vma;
13477
13478 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13479 if (IS_ERR(vma)) {
13480 DRM_DEBUG_KMS("failed to pin object\n");
13481
13482 ret = PTR_ERR(vma);
13483 goto out_unlock;
13484 }
13485
13486 to_intel_plane_state(new_plane_state)->vma = vma;
13487 }
13488
13489 old_fb = old_plane_state->fb;
13490 old_vma = to_intel_plane_state(old_plane_state)->vma;
13491
13492 i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13493 intel_plane->frontbuffer_bit);
13494
13495 /* Swap plane state */
13496 new_plane_state->fence = old_plane_state->fence;
13497 *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state);
13498 new_plane_state->fence = NULL;
13499 new_plane_state->fb = old_fb;
13500 to_intel_plane_state(new_plane_state)->vma = old_vma;
13501
13502 if (plane->state->visible) {
13503 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13504 intel_plane->update_plane(plane,
13505 to_intel_crtc_state(crtc->state),
13506 to_intel_plane_state(plane->state));
13507 } else {
13508 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13509 intel_plane->disable_plane(plane, crtc);
13510 }
13511
13512 intel_cleanup_plane_fb(plane, new_plane_state);
13513
13514 out_unlock:
13515 mutex_unlock(&dev_priv->drm.struct_mutex);
13516 out_free:
13517 intel_plane_destroy_state(plane, new_plane_state);
13518 return ret;
13519
13520 slow:
13521 return drm_atomic_helper_update_plane(plane, crtc, fb,
13522 crtc_x, crtc_y, crtc_w, crtc_h,
13523 src_x, src_y, src_w, src_h);
13524 }
13525
13526 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13527 .update_plane = intel_legacy_cursor_update,
13528 .disable_plane = drm_atomic_helper_disable_plane,
13529 .destroy = intel_plane_destroy,
13530 .set_property = drm_atomic_helper_plane_set_property,
13531 .atomic_get_property = intel_plane_atomic_get_property,
13532 .atomic_set_property = intel_plane_atomic_set_property,
13533 .atomic_duplicate_state = intel_plane_duplicate_state,
13534 .atomic_destroy_state = intel_plane_destroy_state,
13535 };
13536
13537 static struct intel_plane *
13538 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13539 {
13540 struct intel_plane *primary = NULL;
13541 struct intel_plane_state *state = NULL;
13542 const uint32_t *intel_primary_formats;
13543 unsigned int supported_rotations;
13544 unsigned int num_formats;
13545 int ret;
13546
13547 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13548 if (!primary) {
13549 ret = -ENOMEM;
13550 goto fail;
13551 }
13552
13553 state = intel_create_plane_state(&primary->base);
13554 if (!state) {
13555 ret = -ENOMEM;
13556 goto fail;
13557 }
13558
13559 primary->base.state = &state->base;
13560
13561 primary->can_scale = false;
13562 primary->max_downscale = 1;
13563 if (INTEL_GEN(dev_priv) >= 9) {
13564 primary->can_scale = true;
13565 state->scaler_id = -1;
13566 }
13567 primary->pipe = pipe;
13568 /*
13569 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13570 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13571 */
13572 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13573 primary->plane = (enum plane) !pipe;
13574 else
13575 primary->plane = (enum plane) pipe;
13576 primary->id = PLANE_PRIMARY;
13577 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13578 primary->check_plane = intel_check_primary_plane;
13579
13580 if (INTEL_GEN(dev_priv) >= 9) {
13581 intel_primary_formats = skl_primary_formats;
13582 num_formats = ARRAY_SIZE(skl_primary_formats);
13583
13584 primary->update_plane = skylake_update_primary_plane;
13585 primary->disable_plane = skylake_disable_primary_plane;
13586 } else if (HAS_PCH_SPLIT(dev_priv)) {
13587 intel_primary_formats = i965_primary_formats;
13588 num_formats = ARRAY_SIZE(i965_primary_formats);
13589
13590 primary->update_plane = ironlake_update_primary_plane;
13591 primary->disable_plane = i9xx_disable_primary_plane;
13592 } else if (INTEL_GEN(dev_priv) >= 4) {
13593 intel_primary_formats = i965_primary_formats;
13594 num_formats = ARRAY_SIZE(i965_primary_formats);
13595
13596 primary->update_plane = i9xx_update_primary_plane;
13597 primary->disable_plane = i9xx_disable_primary_plane;
13598 } else {
13599 intel_primary_formats = i8xx_primary_formats;
13600 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13601
13602 primary->update_plane = i9xx_update_primary_plane;
13603 primary->disable_plane = i9xx_disable_primary_plane;
13604 }
13605
13606 if (INTEL_GEN(dev_priv) >= 9)
13607 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13608 0, &intel_plane_funcs,
13609 intel_primary_formats, num_formats,
13610 DRM_PLANE_TYPE_PRIMARY,
13611 "plane 1%c", pipe_name(pipe));
13612 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13613 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13614 0, &intel_plane_funcs,
13615 intel_primary_formats, num_formats,
13616 DRM_PLANE_TYPE_PRIMARY,
13617 "primary %c", pipe_name(pipe));
13618 else
13619 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13620 0, &intel_plane_funcs,
13621 intel_primary_formats, num_formats,
13622 DRM_PLANE_TYPE_PRIMARY,
13623 "plane %c", plane_name(primary->plane));
13624 if (ret)
13625 goto fail;
13626
13627 if (INTEL_GEN(dev_priv) >= 9) {
13628 supported_rotations =
13629 DRM_ROTATE_0 | DRM_ROTATE_90 |
13630 DRM_ROTATE_180 | DRM_ROTATE_270;
13631 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13632 supported_rotations =
13633 DRM_ROTATE_0 | DRM_ROTATE_180 |
13634 DRM_REFLECT_X;
13635 } else if (INTEL_GEN(dev_priv) >= 4) {
13636 supported_rotations =
13637 DRM_ROTATE_0 | DRM_ROTATE_180;
13638 } else {
13639 supported_rotations = DRM_ROTATE_0;
13640 }
13641
13642 if (INTEL_GEN(dev_priv) >= 4)
13643 drm_plane_create_rotation_property(&primary->base,
13644 DRM_ROTATE_0,
13645 supported_rotations);
13646
13647 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13648
13649 return primary;
13650
13651 fail:
13652 kfree(state);
13653 kfree(primary);
13654
13655 return ERR_PTR(ret);
13656 }
13657
13658 static int
13659 intel_check_cursor_plane(struct drm_plane *plane,
13660 struct intel_crtc_state *crtc_state,
13661 struct intel_plane_state *state)
13662 {
13663 struct drm_framebuffer *fb = state->base.fb;
13664 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13665 enum pipe pipe = to_intel_plane(plane)->pipe;
13666 unsigned stride;
13667 int ret;
13668
13669 ret = drm_plane_helper_check_state(&state->base,
13670 &state->clip,
13671 DRM_PLANE_HELPER_NO_SCALING,
13672 DRM_PLANE_HELPER_NO_SCALING,
13673 true, true);
13674 if (ret)
13675 return ret;
13676
13677 /* if we want to turn off the cursor ignore width and height */
13678 if (!obj)
13679 return 0;
13680
13681 /* Check for which cursor types we support */
13682 if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w,
13683 state->base.crtc_h)) {
13684 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13685 state->base.crtc_w, state->base.crtc_h);
13686 return -EINVAL;
13687 }
13688
13689 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13690 if (obj->base.size < stride * state->base.crtc_h) {
13691 DRM_DEBUG_KMS("buffer is too small\n");
13692 return -ENOMEM;
13693 }
13694
13695 if (fb->modifier != DRM_FORMAT_MOD_NONE) {
13696 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13697 return -EINVAL;
13698 }
13699
13700 /*
13701 * There's something wrong with the cursor on CHV pipe C.
13702 * If it straddles the left edge of the screen then
13703 * moving it away from the edge or disabling it often
13704 * results in a pipe underrun, and often that can lead to
13705 * dead pipe (constant underrun reported, and it scans
13706 * out just a solid color). To recover from that, the
13707 * display power well must be turned off and on again.
13708 * Refuse the put the cursor into that compromised position.
13709 */
13710 if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C &&
13711 state->base.visible && state->base.crtc_x < 0) {
13712 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
13713 return -EINVAL;
13714 }
13715
13716 return 0;
13717 }
13718
13719 static void
13720 intel_disable_cursor_plane(struct drm_plane *plane,
13721 struct drm_crtc *crtc)
13722 {
13723 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13724
13725 intel_crtc->cursor_addr = 0;
13726 intel_crtc_update_cursor(crtc, NULL);
13727 }
13728
13729 static void
13730 intel_update_cursor_plane(struct drm_plane *plane,
13731 const struct intel_crtc_state *crtc_state,
13732 const struct intel_plane_state *state)
13733 {
13734 struct drm_crtc *crtc = crtc_state->base.crtc;
13735 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13736 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13737 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13738 uint32_t addr;
13739
13740 if (!obj)
13741 addr = 0;
13742 else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
13743 addr = intel_plane_ggtt_offset(state);
13744 else
13745 addr = obj->phys_handle->busaddr;
13746
13747 intel_crtc->cursor_addr = addr;
13748 intel_crtc_update_cursor(crtc, state);
13749 }
13750
13751 static struct intel_plane *
13752 intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13753 {
13754 struct intel_plane *cursor = NULL;
13755 struct intel_plane_state *state = NULL;
13756 int ret;
13757
13758 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13759 if (!cursor) {
13760 ret = -ENOMEM;
13761 goto fail;
13762 }
13763
13764 state = intel_create_plane_state(&cursor->base);
13765 if (!state) {
13766 ret = -ENOMEM;
13767 goto fail;
13768 }
13769
13770 cursor->base.state = &state->base;
13771
13772 cursor->can_scale = false;
13773 cursor->max_downscale = 1;
13774 cursor->pipe = pipe;
13775 cursor->plane = pipe;
13776 cursor->id = PLANE_CURSOR;
13777 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13778 cursor->check_plane = intel_check_cursor_plane;
13779 cursor->update_plane = intel_update_cursor_plane;
13780 cursor->disable_plane = intel_disable_cursor_plane;
13781
13782 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13783 0, &intel_cursor_plane_funcs,
13784 intel_cursor_formats,
13785 ARRAY_SIZE(intel_cursor_formats),
13786 DRM_PLANE_TYPE_CURSOR,
13787 "cursor %c", pipe_name(pipe));
13788 if (ret)
13789 goto fail;
13790
13791 if (INTEL_GEN(dev_priv) >= 4)
13792 drm_plane_create_rotation_property(&cursor->base,
13793 DRM_ROTATE_0,
13794 DRM_ROTATE_0 |
13795 DRM_ROTATE_180);
13796
13797 if (INTEL_GEN(dev_priv) >= 9)
13798 state->scaler_id = -1;
13799
13800 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13801
13802 return cursor;
13803
13804 fail:
13805 kfree(state);
13806 kfree(cursor);
13807
13808 return ERR_PTR(ret);
13809 }
13810
13811 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13812 struct intel_crtc_state *crtc_state)
13813 {
13814 struct intel_crtc_scaler_state *scaler_state =
13815 &crtc_state->scaler_state;
13816 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13817 int i;
13818
13819 crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13820 if (!crtc->num_scalers)
13821 return;
13822
13823 for (i = 0; i < crtc->num_scalers; i++) {
13824 struct intel_scaler *scaler = &scaler_state->scalers[i];
13825
13826 scaler->in_use = 0;
13827 scaler->mode = PS_SCALER_MODE_DYN;
13828 }
13829
13830 scaler_state->scaler_id = -1;
13831 }
13832
13833 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13834 {
13835 struct intel_crtc *intel_crtc;
13836 struct intel_crtc_state *crtc_state = NULL;
13837 struct intel_plane *primary = NULL;
13838 struct intel_plane *cursor = NULL;
13839 int sprite, ret;
13840
13841 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13842 if (!intel_crtc)
13843 return -ENOMEM;
13844
13845 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13846 if (!crtc_state) {
13847 ret = -ENOMEM;
13848 goto fail;
13849 }
13850 intel_crtc->config = crtc_state;
13851 intel_crtc->base.state = &crtc_state->base;
13852 crtc_state->base.crtc = &intel_crtc->base;
13853
13854 primary = intel_primary_plane_create(dev_priv, pipe);
13855 if (IS_ERR(primary)) {
13856 ret = PTR_ERR(primary);
13857 goto fail;
13858 }
13859 intel_crtc->plane_ids_mask |= BIT(primary->id);
13860
13861 for_each_sprite(dev_priv, pipe, sprite) {
13862 struct intel_plane *plane;
13863
13864 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13865 if (IS_ERR(plane)) {
13866 ret = PTR_ERR(plane);
13867 goto fail;
13868 }
13869 intel_crtc->plane_ids_mask |= BIT(plane->id);
13870 }
13871
13872 cursor = intel_cursor_plane_create(dev_priv, pipe);
13873 if (IS_ERR(cursor)) {
13874 ret = PTR_ERR(cursor);
13875 goto fail;
13876 }
13877 intel_crtc->plane_ids_mask |= BIT(cursor->id);
13878
13879 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13880 &primary->base, &cursor->base,
13881 &intel_crtc_funcs,
13882 "pipe %c", pipe_name(pipe));
13883 if (ret)
13884 goto fail;
13885
13886 intel_crtc->pipe = pipe;
13887 intel_crtc->plane = primary->plane;
13888
13889 intel_crtc->cursor_base = ~0;
13890 intel_crtc->cursor_cntl = ~0;
13891 intel_crtc->cursor_size = ~0;
13892
13893 /* initialize shared scalers */
13894 intel_crtc_init_scalers(intel_crtc, crtc_state);
13895
13896 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13897 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13898 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13899 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13900
13901 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13902
13903 intel_color_init(&intel_crtc->base);
13904
13905 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13906
13907 return 0;
13908
13909 fail:
13910 /*
13911 * drm_mode_config_cleanup() will free up any
13912 * crtcs/planes already initialized.
13913 */
13914 kfree(crtc_state);
13915 kfree(intel_crtc);
13916
13917 return ret;
13918 }
13919
13920 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13921 {
13922 struct drm_encoder *encoder = connector->base.encoder;
13923 struct drm_device *dev = connector->base.dev;
13924
13925 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13926
13927 if (!encoder || WARN_ON(!encoder->crtc))
13928 return INVALID_PIPE;
13929
13930 return to_intel_crtc(encoder->crtc)->pipe;
13931 }
13932
13933 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13934 struct drm_file *file)
13935 {
13936 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13937 struct drm_crtc *drmmode_crtc;
13938 struct intel_crtc *crtc;
13939
13940 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13941 if (!drmmode_crtc)
13942 return -ENOENT;
13943
13944 crtc = to_intel_crtc(drmmode_crtc);
13945 pipe_from_crtc_id->pipe = crtc->pipe;
13946
13947 return 0;
13948 }
13949
13950 static int intel_encoder_clones(struct intel_encoder *encoder)
13951 {
13952 struct drm_device *dev = encoder->base.dev;
13953 struct intel_encoder *source_encoder;
13954 int index_mask = 0;
13955 int entry = 0;
13956
13957 for_each_intel_encoder(dev, source_encoder) {
13958 if (encoders_cloneable(encoder, source_encoder))
13959 index_mask |= (1 << entry);
13960
13961 entry++;
13962 }
13963
13964 return index_mask;
13965 }
13966
13967 static bool has_edp_a(struct drm_i915_private *dev_priv)
13968 {
13969 if (!IS_MOBILE(dev_priv))
13970 return false;
13971
13972 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13973 return false;
13974
13975 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13976 return false;
13977
13978 return true;
13979 }
13980
13981 static bool intel_crt_present(struct drm_i915_private *dev_priv)
13982 {
13983 if (INTEL_GEN(dev_priv) >= 9)
13984 return false;
13985
13986 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
13987 return false;
13988
13989 if (IS_CHERRYVIEW(dev_priv))
13990 return false;
13991
13992 if (HAS_PCH_LPT_H(dev_priv) &&
13993 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
13994 return false;
13995
13996 /* DDI E can't be used if DDI A requires 4 lanes */
13997 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
13998 return false;
13999
14000 if (!dev_priv->vbt.int_crt_support)
14001 return false;
14002
14003 return true;
14004 }
14005
14006 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
14007 {
14008 int pps_num;
14009 int pps_idx;
14010
14011 if (HAS_DDI(dev_priv))
14012 return;
14013 /*
14014 * This w/a is needed at least on CPT/PPT, but to be sure apply it
14015 * everywhere where registers can be write protected.
14016 */
14017 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14018 pps_num = 2;
14019 else
14020 pps_num = 1;
14021
14022 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
14023 u32 val = I915_READ(PP_CONTROL(pps_idx));
14024
14025 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
14026 I915_WRITE(PP_CONTROL(pps_idx), val);
14027 }
14028 }
14029
14030 static void intel_pps_init(struct drm_i915_private *dev_priv)
14031 {
14032 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
14033 dev_priv->pps_mmio_base = PCH_PPS_BASE;
14034 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14035 dev_priv->pps_mmio_base = VLV_PPS_BASE;
14036 else
14037 dev_priv->pps_mmio_base = PPS_BASE;
14038
14039 intel_pps_unlock_regs_wa(dev_priv);
14040 }
14041
14042 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14043 {
14044 struct intel_encoder *encoder;
14045 bool dpd_is_edp = false;
14046
14047 intel_pps_init(dev_priv);
14048
14049 /*
14050 * intel_edp_init_connector() depends on this completing first, to
14051 * prevent the registeration of both eDP and LVDS and the incorrect
14052 * sharing of the PPS.
14053 */
14054 intel_lvds_init(dev_priv);
14055
14056 if (intel_crt_present(dev_priv))
14057 intel_crt_init(dev_priv);
14058
14059 if (IS_GEN9_LP(dev_priv)) {
14060 /*
14061 * FIXME: Broxton doesn't support port detection via the
14062 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14063 * detect the ports.
14064 */
14065 intel_ddi_init(dev_priv, PORT_A);
14066 intel_ddi_init(dev_priv, PORT_B);
14067 intel_ddi_init(dev_priv, PORT_C);
14068
14069 intel_dsi_init(dev_priv);
14070 } else if (HAS_DDI(dev_priv)) {
14071 int found;
14072
14073 /*
14074 * Haswell uses DDI functions to detect digital outputs.
14075 * On SKL pre-D0 the strap isn't connected, so we assume
14076 * it's there.
14077 */
14078 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14079 /* WaIgnoreDDIAStrap: skl */
14080 if (found || IS_GEN9_BC(dev_priv))
14081 intel_ddi_init(dev_priv, PORT_A);
14082
14083 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14084 * register */
14085 found = I915_READ(SFUSE_STRAP);
14086
14087 if (found & SFUSE_STRAP_DDIB_DETECTED)
14088 intel_ddi_init(dev_priv, PORT_B);
14089 if (found & SFUSE_STRAP_DDIC_DETECTED)
14090 intel_ddi_init(dev_priv, PORT_C);
14091 if (found & SFUSE_STRAP_DDID_DETECTED)
14092 intel_ddi_init(dev_priv, PORT_D);
14093 /*
14094 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14095 */
14096 if (IS_GEN9_BC(dev_priv) &&
14097 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14098 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14099 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14100 intel_ddi_init(dev_priv, PORT_E);
14101
14102 } else if (HAS_PCH_SPLIT(dev_priv)) {
14103 int found;
14104 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
14105
14106 if (has_edp_a(dev_priv))
14107 intel_dp_init(dev_priv, DP_A, PORT_A);
14108
14109 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14110 /* PCH SDVOB multiplex with HDMIB */
14111 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
14112 if (!found)
14113 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
14114 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14115 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
14116 }
14117
14118 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14119 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
14120
14121 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14122 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
14123
14124 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14125 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
14126
14127 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14128 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
14129 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14130 bool has_edp, has_port;
14131
14132 /*
14133 * The DP_DETECTED bit is the latched state of the DDC
14134 * SDA pin at boot. However since eDP doesn't require DDC
14135 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14136 * eDP ports may have been muxed to an alternate function.
14137 * Thus we can't rely on the DP_DETECTED bit alone to detect
14138 * eDP ports. Consult the VBT as well as DP_DETECTED to
14139 * detect eDP ports.
14140 *
14141 * Sadly the straps seem to be missing sometimes even for HDMI
14142 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14143 * and VBT for the presence of the port. Additionally we can't
14144 * trust the port type the VBT declares as we've seen at least
14145 * HDMI ports that the VBT claim are DP or eDP.
14146 */
14147 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
14148 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14149 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14150 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
14151 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14152 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
14153
14154 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
14155 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14156 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14157 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
14158 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14159 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
14160
14161 if (IS_CHERRYVIEW(dev_priv)) {
14162 /*
14163 * eDP not supported on port D,
14164 * so no need to worry about it
14165 */
14166 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14167 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14168 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
14169 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14170 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
14171 }
14172
14173 intel_dsi_init(dev_priv);
14174 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
14175 bool found = false;
14176
14177 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14178 DRM_DEBUG_KMS("probing SDVOB\n");
14179 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
14180 if (!found && IS_G4X(dev_priv)) {
14181 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14182 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
14183 }
14184
14185 if (!found && IS_G4X(dev_priv))
14186 intel_dp_init(dev_priv, DP_B, PORT_B);
14187 }
14188
14189 /* Before G4X SDVOC doesn't have its own detect register */
14190
14191 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14192 DRM_DEBUG_KMS("probing SDVOC\n");
14193 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
14194 }
14195
14196 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14197
14198 if (IS_G4X(dev_priv)) {
14199 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14200 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
14201 }
14202 if (IS_G4X(dev_priv))
14203 intel_dp_init(dev_priv, DP_C, PORT_C);
14204 }
14205
14206 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
14207 intel_dp_init(dev_priv, DP_D, PORT_D);
14208 } else if (IS_GEN2(dev_priv))
14209 intel_dvo_init(dev_priv);
14210
14211 if (SUPPORTS_TV(dev_priv))
14212 intel_tv_init(dev_priv);
14213
14214 intel_psr_init(dev_priv);
14215
14216 for_each_intel_encoder(&dev_priv->drm, encoder) {
14217 encoder->base.possible_crtcs = encoder->crtc_mask;
14218 encoder->base.possible_clones =
14219 intel_encoder_clones(encoder);
14220 }
14221
14222 intel_init_pch_refclk(dev_priv);
14223
14224 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
14225 }
14226
14227 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14228 {
14229 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14230
14231 drm_framebuffer_cleanup(fb);
14232
14233 i915_gem_object_lock(intel_fb->obj);
14234 WARN_ON(!intel_fb->obj->framebuffer_references--);
14235 i915_gem_object_unlock(intel_fb->obj);
14236
14237 i915_gem_object_put(intel_fb->obj);
14238
14239 kfree(intel_fb);
14240 }
14241
14242 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14243 struct drm_file *file,
14244 unsigned int *handle)
14245 {
14246 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14247 struct drm_i915_gem_object *obj = intel_fb->obj;
14248
14249 if (obj->userptr.mm) {
14250 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14251 return -EINVAL;
14252 }
14253
14254 return drm_gem_handle_create(file, &obj->base, handle);
14255 }
14256
14257 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14258 struct drm_file *file,
14259 unsigned flags, unsigned color,
14260 struct drm_clip_rect *clips,
14261 unsigned num_clips)
14262 {
14263 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14264
14265 i915_gem_object_flush_if_display(obj);
14266 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
14267
14268 return 0;
14269 }
14270
14271 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14272 .destroy = intel_user_framebuffer_destroy,
14273 .create_handle = intel_user_framebuffer_create_handle,
14274 .dirty = intel_user_framebuffer_dirty,
14275 };
14276
14277 static
14278 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
14279 uint64_t fb_modifier, uint32_t pixel_format)
14280 {
14281 u32 gen = INTEL_GEN(dev_priv);
14282
14283 if (gen >= 9) {
14284 int cpp = drm_format_plane_cpp(pixel_format, 0);
14285
14286 /* "The stride in bytes must not exceed the of the size of 8K
14287 * pixels and 32K bytes."
14288 */
14289 return min(8192 * cpp, 32768);
14290 } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
14291 return 32*1024;
14292 } else if (gen >= 4) {
14293 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14294 return 16*1024;
14295 else
14296 return 32*1024;
14297 } else if (gen >= 3) {
14298 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14299 return 8*1024;
14300 else
14301 return 16*1024;
14302 } else {
14303 /* XXX DSPC is limited to 4k tiled */
14304 return 8*1024;
14305 }
14306 }
14307
14308 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14309 struct drm_i915_gem_object *obj,
14310 struct drm_mode_fb_cmd2 *mode_cmd)
14311 {
14312 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14313 struct drm_format_name_buf format_name;
14314 u32 pitch_limit, stride_alignment;
14315 unsigned int tiling, stride;
14316 int ret = -EINVAL;
14317
14318 i915_gem_object_lock(obj);
14319 obj->framebuffer_references++;
14320 tiling = i915_gem_object_get_tiling(obj);
14321 stride = i915_gem_object_get_stride(obj);
14322 i915_gem_object_unlock(obj);
14323
14324 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14325 /*
14326 * If there's a fence, enforce that
14327 * the fb modifier and tiling mode match.
14328 */
14329 if (tiling != I915_TILING_NONE &&
14330 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14331 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14332 goto err;
14333 }
14334 } else {
14335 if (tiling == I915_TILING_X) {
14336 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14337 } else if (tiling == I915_TILING_Y) {
14338 DRM_DEBUG("No Y tiling for legacy addfb\n");
14339 goto err;
14340 }
14341 }
14342
14343 /* Passed in modifier sanity checking. */
14344 switch (mode_cmd->modifier[0]) {
14345 case I915_FORMAT_MOD_Y_TILED:
14346 case I915_FORMAT_MOD_Yf_TILED:
14347 if (INTEL_GEN(dev_priv) < 9) {
14348 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14349 mode_cmd->modifier[0]);
14350 goto err;
14351 }
14352 case DRM_FORMAT_MOD_NONE:
14353 case I915_FORMAT_MOD_X_TILED:
14354 break;
14355 default:
14356 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14357 mode_cmd->modifier[0]);
14358 goto err;
14359 }
14360
14361 /*
14362 * gen2/3 display engine uses the fence if present,
14363 * so the tiling mode must match the fb modifier exactly.
14364 */
14365 if (INTEL_INFO(dev_priv)->gen < 4 &&
14366 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14367 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
14368 goto err;
14369 }
14370
14371 stride_alignment = intel_fb_stride_alignment(dev_priv,
14372 mode_cmd->modifier[0],
14373 mode_cmd->pixel_format);
14374 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14375 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14376 mode_cmd->pitches[0], stride_alignment);
14377 goto err;
14378 }
14379
14380 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14381 mode_cmd->pixel_format);
14382 if (mode_cmd->pitches[0] > pitch_limit) {
14383 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14384 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14385 "tiled" : "linear",
14386 mode_cmd->pitches[0], pitch_limit);
14387 goto err;
14388 }
14389
14390 /*
14391 * If there's a fence, enforce that
14392 * the fb pitch and fence stride match.
14393 */
14394 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14395 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14396 mode_cmd->pitches[0], stride);
14397 goto err;
14398 }
14399
14400 /* Reject formats not supported by any plane early. */
14401 switch (mode_cmd->pixel_format) {
14402 case DRM_FORMAT_C8:
14403 case DRM_FORMAT_RGB565:
14404 case DRM_FORMAT_XRGB8888:
14405 case DRM_FORMAT_ARGB8888:
14406 break;
14407 case DRM_FORMAT_XRGB1555:
14408 if (INTEL_GEN(dev_priv) > 3) {
14409 DRM_DEBUG("unsupported pixel format: %s\n",
14410 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14411 goto err;
14412 }
14413 break;
14414 case DRM_FORMAT_ABGR8888:
14415 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14416 INTEL_GEN(dev_priv) < 9) {
14417 DRM_DEBUG("unsupported pixel format: %s\n",
14418 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14419 goto err;
14420 }
14421 break;
14422 case DRM_FORMAT_XBGR8888:
14423 case DRM_FORMAT_XRGB2101010:
14424 case DRM_FORMAT_XBGR2101010:
14425 if (INTEL_GEN(dev_priv) < 4) {
14426 DRM_DEBUG("unsupported pixel format: %s\n",
14427 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14428 goto err;
14429 }
14430 break;
14431 case DRM_FORMAT_ABGR2101010:
14432 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14433 DRM_DEBUG("unsupported pixel format: %s\n",
14434 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14435 goto err;
14436 }
14437 break;
14438 case DRM_FORMAT_YUYV:
14439 case DRM_FORMAT_UYVY:
14440 case DRM_FORMAT_YVYU:
14441 case DRM_FORMAT_VYUY:
14442 if (INTEL_GEN(dev_priv) < 5) {
14443 DRM_DEBUG("unsupported pixel format: %s\n",
14444 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14445 goto err;
14446 }
14447 break;
14448 default:
14449 DRM_DEBUG("unsupported pixel format: %s\n",
14450 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14451 goto err;
14452 }
14453
14454 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14455 if (mode_cmd->offsets[0] != 0)
14456 goto err;
14457
14458 drm_helper_mode_fill_fb_struct(&dev_priv->drm,
14459 &intel_fb->base, mode_cmd);
14460 intel_fb->obj = obj;
14461
14462 ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
14463 if (ret)
14464 goto err;
14465
14466 ret = drm_framebuffer_init(obj->base.dev,
14467 &intel_fb->base,
14468 &intel_fb_funcs);
14469 if (ret) {
14470 DRM_ERROR("framebuffer init failed %d\n", ret);
14471 goto err;
14472 }
14473
14474 return 0;
14475
14476 err:
14477 i915_gem_object_lock(obj);
14478 obj->framebuffer_references--;
14479 i915_gem_object_unlock(obj);
14480 return ret;
14481 }
14482
14483 static struct drm_framebuffer *
14484 intel_user_framebuffer_create(struct drm_device *dev,
14485 struct drm_file *filp,
14486 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14487 {
14488 struct drm_framebuffer *fb;
14489 struct drm_i915_gem_object *obj;
14490 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14491
14492 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14493 if (!obj)
14494 return ERR_PTR(-ENOENT);
14495
14496 fb = intel_framebuffer_create(obj, &mode_cmd);
14497 if (IS_ERR(fb))
14498 i915_gem_object_put(obj);
14499
14500 return fb;
14501 }
14502
14503 static void intel_atomic_state_free(struct drm_atomic_state *state)
14504 {
14505 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14506
14507 drm_atomic_state_default_release(state);
14508
14509 i915_sw_fence_fini(&intel_state->commit_ready);
14510
14511 kfree(state);
14512 }
14513
14514 static const struct drm_mode_config_funcs intel_mode_funcs = {
14515 .fb_create = intel_user_framebuffer_create,
14516 .output_poll_changed = intel_fbdev_output_poll_changed,
14517 .atomic_check = intel_atomic_check,
14518 .atomic_commit = intel_atomic_commit,
14519 .atomic_state_alloc = intel_atomic_state_alloc,
14520 .atomic_state_clear = intel_atomic_state_clear,
14521 .atomic_state_free = intel_atomic_state_free,
14522 };
14523
14524 /**
14525 * intel_init_display_hooks - initialize the display modesetting hooks
14526 * @dev_priv: device private
14527 */
14528 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14529 {
14530 intel_init_cdclk_hooks(dev_priv);
14531
14532 if (INTEL_INFO(dev_priv)->gen >= 9) {
14533 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14534 dev_priv->display.get_initial_plane_config =
14535 skylake_get_initial_plane_config;
14536 dev_priv->display.crtc_compute_clock =
14537 haswell_crtc_compute_clock;
14538 dev_priv->display.crtc_enable = haswell_crtc_enable;
14539 dev_priv->display.crtc_disable = haswell_crtc_disable;
14540 } else if (HAS_DDI(dev_priv)) {
14541 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14542 dev_priv->display.get_initial_plane_config =
14543 ironlake_get_initial_plane_config;
14544 dev_priv->display.crtc_compute_clock =
14545 haswell_crtc_compute_clock;
14546 dev_priv->display.crtc_enable = haswell_crtc_enable;
14547 dev_priv->display.crtc_disable = haswell_crtc_disable;
14548 } else if (HAS_PCH_SPLIT(dev_priv)) {
14549 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14550 dev_priv->display.get_initial_plane_config =
14551 ironlake_get_initial_plane_config;
14552 dev_priv->display.crtc_compute_clock =
14553 ironlake_crtc_compute_clock;
14554 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14555 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14556 } else if (IS_CHERRYVIEW(dev_priv)) {
14557 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14558 dev_priv->display.get_initial_plane_config =
14559 i9xx_get_initial_plane_config;
14560 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14561 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14562 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14563 } else if (IS_VALLEYVIEW(dev_priv)) {
14564 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14565 dev_priv->display.get_initial_plane_config =
14566 i9xx_get_initial_plane_config;
14567 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14568 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14569 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14570 } else if (IS_G4X(dev_priv)) {
14571 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14572 dev_priv->display.get_initial_plane_config =
14573 i9xx_get_initial_plane_config;
14574 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14575 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14576 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14577 } else if (IS_PINEVIEW(dev_priv)) {
14578 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14579 dev_priv->display.get_initial_plane_config =
14580 i9xx_get_initial_plane_config;
14581 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14582 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14583 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14584 } else if (!IS_GEN2(dev_priv)) {
14585 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14586 dev_priv->display.get_initial_plane_config =
14587 i9xx_get_initial_plane_config;
14588 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14589 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14590 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14591 } else {
14592 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14593 dev_priv->display.get_initial_plane_config =
14594 i9xx_get_initial_plane_config;
14595 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14596 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14597 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14598 }
14599
14600 if (IS_GEN5(dev_priv)) {
14601 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14602 } else if (IS_GEN6(dev_priv)) {
14603 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14604 } else if (IS_IVYBRIDGE(dev_priv)) {
14605 /* FIXME: detect B0+ stepping and use auto training */
14606 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14607 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14608 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14609 }
14610
14611 if (dev_priv->info.gen >= 9)
14612 dev_priv->display.update_crtcs = skl_update_crtcs;
14613 else
14614 dev_priv->display.update_crtcs = intel_update_crtcs;
14615
14616 switch (INTEL_INFO(dev_priv)->gen) {
14617 case 2:
14618 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14619 break;
14620
14621 case 3:
14622 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14623 break;
14624
14625 case 4:
14626 case 5:
14627 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14628 break;
14629
14630 case 6:
14631 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14632 break;
14633 case 7:
14634 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14635 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14636 break;
14637 case 9:
14638 /* Drop through - unsupported since execlist only. */
14639 default:
14640 /* Default just returns -ENODEV to indicate unsupported */
14641 dev_priv->display.queue_flip = intel_default_queue_flip;
14642 }
14643 }
14644
14645 /*
14646 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14647 * resume, or other times. This quirk makes sure that's the case for
14648 * affected systems.
14649 */
14650 static void quirk_pipea_force(struct drm_device *dev)
14651 {
14652 struct drm_i915_private *dev_priv = to_i915(dev);
14653
14654 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14655 DRM_INFO("applying pipe a force quirk\n");
14656 }
14657
14658 static void quirk_pipeb_force(struct drm_device *dev)
14659 {
14660 struct drm_i915_private *dev_priv = to_i915(dev);
14661
14662 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14663 DRM_INFO("applying pipe b force quirk\n");
14664 }
14665
14666 /*
14667 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14668 */
14669 static void quirk_ssc_force_disable(struct drm_device *dev)
14670 {
14671 struct drm_i915_private *dev_priv = to_i915(dev);
14672 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14673 DRM_INFO("applying lvds SSC disable quirk\n");
14674 }
14675
14676 /*
14677 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14678 * brightness value
14679 */
14680 static void quirk_invert_brightness(struct drm_device *dev)
14681 {
14682 struct drm_i915_private *dev_priv = to_i915(dev);
14683 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14684 DRM_INFO("applying inverted panel brightness quirk\n");
14685 }
14686
14687 /* Some VBT's incorrectly indicate no backlight is present */
14688 static void quirk_backlight_present(struct drm_device *dev)
14689 {
14690 struct drm_i915_private *dev_priv = to_i915(dev);
14691 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14692 DRM_INFO("applying backlight present quirk\n");
14693 }
14694
14695 struct intel_quirk {
14696 int device;
14697 int subsystem_vendor;
14698 int subsystem_device;
14699 void (*hook)(struct drm_device *dev);
14700 };
14701
14702 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14703 struct intel_dmi_quirk {
14704 void (*hook)(struct drm_device *dev);
14705 const struct dmi_system_id (*dmi_id_list)[];
14706 };
14707
14708 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14709 {
14710 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14711 return 1;
14712 }
14713
14714 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14715 {
14716 .dmi_id_list = &(const struct dmi_system_id[]) {
14717 {
14718 .callback = intel_dmi_reverse_brightness,
14719 .ident = "NCR Corporation",
14720 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14721 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14722 },
14723 },
14724 { } /* terminating entry */
14725 },
14726 .hook = quirk_invert_brightness,
14727 },
14728 };
14729
14730 static struct intel_quirk intel_quirks[] = {
14731 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14732 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14733
14734 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14735 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14736
14737 /* 830 needs to leave pipe A & dpll A up */
14738 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14739
14740 /* 830 needs to leave pipe B & dpll B up */
14741 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14742
14743 /* Lenovo U160 cannot use SSC on LVDS */
14744 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14745
14746 /* Sony Vaio Y cannot use SSC on LVDS */
14747 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14748
14749 /* Acer Aspire 5734Z must invert backlight brightness */
14750 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14751
14752 /* Acer/eMachines G725 */
14753 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14754
14755 /* Acer/eMachines e725 */
14756 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14757
14758 /* Acer/Packard Bell NCL20 */
14759 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14760
14761 /* Acer Aspire 4736Z */
14762 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14763
14764 /* Acer Aspire 5336 */
14765 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14766
14767 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14768 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14769
14770 /* Acer C720 Chromebook (Core i3 4005U) */
14771 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14772
14773 /* Apple Macbook 2,1 (Core 2 T7400) */
14774 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14775
14776 /* Apple Macbook 4,1 */
14777 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14778
14779 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14780 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14781
14782 /* HP Chromebook 14 (Celeron 2955U) */
14783 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14784
14785 /* Dell Chromebook 11 */
14786 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14787
14788 /* Dell Chromebook 11 (2015 version) */
14789 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14790 };
14791
14792 static void intel_init_quirks(struct drm_device *dev)
14793 {
14794 struct pci_dev *d = dev->pdev;
14795 int i;
14796
14797 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14798 struct intel_quirk *q = &intel_quirks[i];
14799
14800 if (d->device == q->device &&
14801 (d->subsystem_vendor == q->subsystem_vendor ||
14802 q->subsystem_vendor == PCI_ANY_ID) &&
14803 (d->subsystem_device == q->subsystem_device ||
14804 q->subsystem_device == PCI_ANY_ID))
14805 q->hook(dev);
14806 }
14807 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14808 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14809 intel_dmi_quirks[i].hook(dev);
14810 }
14811 }
14812
14813 /* Disable the VGA plane that we never use */
14814 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14815 {
14816 struct pci_dev *pdev = dev_priv->drm.pdev;
14817 u8 sr1;
14818 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14819
14820 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14821 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14822 outb(SR01, VGA_SR_INDEX);
14823 sr1 = inb(VGA_SR_DATA);
14824 outb(sr1 | 1<<5, VGA_SR_DATA);
14825 vga_put(pdev, VGA_RSRC_LEGACY_IO);
14826 udelay(300);
14827
14828 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14829 POSTING_READ(vga_reg);
14830 }
14831
14832 void intel_modeset_init_hw(struct drm_device *dev)
14833 {
14834 struct drm_i915_private *dev_priv = to_i915(dev);
14835
14836 intel_update_cdclk(dev_priv);
14837 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14838
14839 intel_init_clock_gating(dev_priv);
14840 }
14841
14842 /*
14843 * Calculate what we think the watermarks should be for the state we've read
14844 * out of the hardware and then immediately program those watermarks so that
14845 * we ensure the hardware settings match our internal state.
14846 *
14847 * We can calculate what we think WM's should be by creating a duplicate of the
14848 * current state (which was constructed during hardware readout) and running it
14849 * through the atomic check code to calculate new watermark values in the
14850 * state object.
14851 */
14852 static void sanitize_watermarks(struct drm_device *dev)
14853 {
14854 struct drm_i915_private *dev_priv = to_i915(dev);
14855 struct drm_atomic_state *state;
14856 struct intel_atomic_state *intel_state;
14857 struct drm_crtc *crtc;
14858 struct drm_crtc_state *cstate;
14859 struct drm_modeset_acquire_ctx ctx;
14860 int ret;
14861 int i;
14862
14863 /* Only supported on platforms that use atomic watermark design */
14864 if (!dev_priv->display.optimize_watermarks)
14865 return;
14866
14867 /*
14868 * We need to hold connection_mutex before calling duplicate_state so
14869 * that the connector loop is protected.
14870 */
14871 drm_modeset_acquire_init(&ctx, 0);
14872 retry:
14873 ret = drm_modeset_lock_all_ctx(dev, &ctx);
14874 if (ret == -EDEADLK) {
14875 drm_modeset_backoff(&ctx);
14876 goto retry;
14877 } else if (WARN_ON(ret)) {
14878 goto fail;
14879 }
14880
14881 state = drm_atomic_helper_duplicate_state(dev, &ctx);
14882 if (WARN_ON(IS_ERR(state)))
14883 goto fail;
14884
14885 intel_state = to_intel_atomic_state(state);
14886
14887 /*
14888 * Hardware readout is the only time we don't want to calculate
14889 * intermediate watermarks (since we don't trust the current
14890 * watermarks).
14891 */
14892 if (!HAS_GMCH_DISPLAY(dev_priv))
14893 intel_state->skip_intermediate_wm = true;
14894
14895 ret = intel_atomic_check(dev, state);
14896 if (ret) {
14897 /*
14898 * If we fail here, it means that the hardware appears to be
14899 * programmed in a way that shouldn't be possible, given our
14900 * understanding of watermark requirements. This might mean a
14901 * mistake in the hardware readout code or a mistake in the
14902 * watermark calculations for a given platform. Raise a WARN
14903 * so that this is noticeable.
14904 *
14905 * If this actually happens, we'll have to just leave the
14906 * BIOS-programmed watermarks untouched and hope for the best.
14907 */
14908 WARN(true, "Could not determine valid watermarks for inherited state\n");
14909 goto put_state;
14910 }
14911
14912 /* Write calculated watermark values back */
14913 for_each_crtc_in_state(state, crtc, cstate, i) {
14914 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14915
14916 cs->wm.need_postvbl_update = true;
14917 dev_priv->display.optimize_watermarks(intel_state, cs);
14918 }
14919
14920 put_state:
14921 drm_atomic_state_put(state);
14922 fail:
14923 drm_modeset_drop_locks(&ctx);
14924 drm_modeset_acquire_fini(&ctx);
14925 }
14926
14927 int intel_modeset_init(struct drm_device *dev)
14928 {
14929 struct drm_i915_private *dev_priv = to_i915(dev);
14930 struct i915_ggtt *ggtt = &dev_priv->ggtt;
14931 enum pipe pipe;
14932 struct intel_crtc *crtc;
14933
14934 drm_mode_config_init(dev);
14935
14936 dev->mode_config.min_width = 0;
14937 dev->mode_config.min_height = 0;
14938
14939 dev->mode_config.preferred_depth = 24;
14940 dev->mode_config.prefer_shadow = 1;
14941
14942 dev->mode_config.allow_fb_modifiers = true;
14943
14944 dev->mode_config.funcs = &intel_mode_funcs;
14945
14946 INIT_WORK(&dev_priv->atomic_helper.free_work,
14947 intel_atomic_helper_free_state_worker);
14948
14949 intel_init_quirks(dev);
14950
14951 intel_init_pm(dev_priv);
14952
14953 if (INTEL_INFO(dev_priv)->num_pipes == 0)
14954 return 0;
14955
14956 /*
14957 * There may be no VBT; and if the BIOS enabled SSC we can
14958 * just keep using it to avoid unnecessary flicker. Whereas if the
14959 * BIOS isn't using it, don't assume it will work even if the VBT
14960 * indicates as much.
14961 */
14962 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
14963 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14964 DREF_SSC1_ENABLE);
14965
14966 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14967 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14968 bios_lvds_use_ssc ? "en" : "dis",
14969 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14970 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14971 }
14972 }
14973
14974 if (IS_GEN2(dev_priv)) {
14975 dev->mode_config.max_width = 2048;
14976 dev->mode_config.max_height = 2048;
14977 } else if (IS_GEN3(dev_priv)) {
14978 dev->mode_config.max_width = 4096;
14979 dev->mode_config.max_height = 4096;
14980 } else {
14981 dev->mode_config.max_width = 8192;
14982 dev->mode_config.max_height = 8192;
14983 }
14984
14985 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14986 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
14987 dev->mode_config.cursor_height = 1023;
14988 } else if (IS_GEN2(dev_priv)) {
14989 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14990 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14991 } else {
14992 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14993 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14994 }
14995
14996 dev->mode_config.fb_base = ggtt->mappable_base;
14997
14998 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14999 INTEL_INFO(dev_priv)->num_pipes,
15000 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
15001
15002 for_each_pipe(dev_priv, pipe) {
15003 int ret;
15004
15005 ret = intel_crtc_init(dev_priv, pipe);
15006 if (ret) {
15007 drm_mode_config_cleanup(dev);
15008 return ret;
15009 }
15010 }
15011
15012 intel_shared_dpll_init(dev);
15013
15014 intel_update_czclk(dev_priv);
15015 intel_modeset_init_hw(dev);
15016
15017 if (dev_priv->max_cdclk_freq == 0)
15018 intel_update_max_cdclk(dev_priv);
15019
15020 /* Just disable it once at startup */
15021 i915_disable_vga(dev_priv);
15022 intel_setup_outputs(dev_priv);
15023
15024 drm_modeset_lock_all(dev);
15025 intel_modeset_setup_hw_state(dev);
15026 drm_modeset_unlock_all(dev);
15027
15028 for_each_intel_crtc(dev, crtc) {
15029 struct intel_initial_plane_config plane_config = {};
15030
15031 if (!crtc->active)
15032 continue;
15033
15034 /*
15035 * Note that reserving the BIOS fb up front prevents us
15036 * from stuffing other stolen allocations like the ring
15037 * on top. This prevents some ugliness at boot time, and
15038 * can even allow for smooth boot transitions if the BIOS
15039 * fb is large enough for the active pipe configuration.
15040 */
15041 dev_priv->display.get_initial_plane_config(crtc,
15042 &plane_config);
15043
15044 /*
15045 * If the fb is shared between multiple heads, we'll
15046 * just get the first one.
15047 */
15048 intel_find_initial_plane_obj(crtc, &plane_config);
15049 }
15050
15051 /*
15052 * Make sure hardware watermarks really match the state we read out.
15053 * Note that we need to do this after reconstructing the BIOS fb's
15054 * since the watermark calculation done here will use pstate->fb.
15055 */
15056 if (!HAS_GMCH_DISPLAY(dev_priv))
15057 sanitize_watermarks(dev);
15058
15059 return 0;
15060 }
15061
15062 static void intel_enable_pipe_a(struct drm_device *dev)
15063 {
15064 struct intel_connector *connector;
15065 struct drm_connector *crt = NULL;
15066 struct intel_load_detect_pipe load_detect_temp;
15067 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15068
15069 /* We can't just switch on the pipe A, we need to set things up with a
15070 * proper mode and output configuration. As a gross hack, enable pipe A
15071 * by enabling the load detect pipe once. */
15072 for_each_intel_connector(dev, connector) {
15073 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15074 crt = &connector->base;
15075 break;
15076 }
15077 }
15078
15079 if (!crt)
15080 return;
15081
15082 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15083 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15084 }
15085
15086 static bool
15087 intel_check_plane_mapping(struct intel_crtc *crtc)
15088 {
15089 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15090 u32 val;
15091
15092 if (INTEL_INFO(dev_priv)->num_pipes == 1)
15093 return true;
15094
15095 val = I915_READ(DSPCNTR(!crtc->plane));
15096
15097 if ((val & DISPLAY_PLANE_ENABLE) &&
15098 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15099 return false;
15100
15101 return true;
15102 }
15103
15104 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15105 {
15106 struct drm_device *dev = crtc->base.dev;
15107 struct intel_encoder *encoder;
15108
15109 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15110 return true;
15111
15112 return false;
15113 }
15114
15115 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15116 {
15117 struct drm_device *dev = encoder->base.dev;
15118 struct intel_connector *connector;
15119
15120 for_each_connector_on_encoder(dev, &encoder->base, connector)
15121 return connector;
15122
15123 return NULL;
15124 }
15125
15126 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15127 enum transcoder pch_transcoder)
15128 {
15129 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15130 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
15131 }
15132
15133 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15134 {
15135 struct drm_device *dev = crtc->base.dev;
15136 struct drm_i915_private *dev_priv = to_i915(dev);
15137 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15138
15139 /* Clear any frame start delays used for debugging left by the BIOS */
15140 if (!transcoder_is_dsi(cpu_transcoder)) {
15141 i915_reg_t reg = PIPECONF(cpu_transcoder);
15142
15143 I915_WRITE(reg,
15144 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15145 }
15146
15147 /* restore vblank interrupts to correct state */
15148 drm_crtc_vblank_reset(&crtc->base);
15149 if (crtc->active) {
15150 struct intel_plane *plane;
15151
15152 drm_crtc_vblank_on(&crtc->base);
15153
15154 /* Disable everything but the primary plane */
15155 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15156 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15157 continue;
15158
15159 trace_intel_disable_plane(&plane->base, crtc);
15160 plane->disable_plane(&plane->base, &crtc->base);
15161 }
15162 }
15163
15164 /* We need to sanitize the plane -> pipe mapping first because this will
15165 * disable the crtc (and hence change the state) if it is wrong. Note
15166 * that gen4+ has a fixed plane -> pipe mapping. */
15167 if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
15168 bool plane;
15169
15170 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15171 crtc->base.base.id, crtc->base.name);
15172
15173 /* Pipe has the wrong plane attached and the plane is active.
15174 * Temporarily change the plane mapping and disable everything
15175 * ... */
15176 plane = crtc->plane;
15177 crtc->base.primary->state->visible = true;
15178 crtc->plane = !plane;
15179 intel_crtc_disable_noatomic(&crtc->base);
15180 crtc->plane = plane;
15181 }
15182
15183 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15184 crtc->pipe == PIPE_A && !crtc->active) {
15185 /* BIOS forgot to enable pipe A, this mostly happens after
15186 * resume. Force-enable the pipe to fix this, the update_dpms
15187 * call below we restore the pipe to the right state, but leave
15188 * the required bits on. */
15189 intel_enable_pipe_a(dev);
15190 }
15191
15192 /* Adjust the state of the output pipe according to whether we
15193 * have active connectors/encoders. */
15194 if (crtc->active && !intel_crtc_has_encoders(crtc))
15195 intel_crtc_disable_noatomic(&crtc->base);
15196
15197 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
15198 /*
15199 * We start out with underrun reporting disabled to avoid races.
15200 * For correct bookkeeping mark this on active crtcs.
15201 *
15202 * Also on gmch platforms we dont have any hardware bits to
15203 * disable the underrun reporting. Which means we need to start
15204 * out with underrun reporting disabled also on inactive pipes,
15205 * since otherwise we'll complain about the garbage we read when
15206 * e.g. coming up after runtime pm.
15207 *
15208 * No protection against concurrent access is required - at
15209 * worst a fifo underrun happens which also sets this to false.
15210 */
15211 crtc->cpu_fifo_underrun_disabled = true;
15212 /*
15213 * We track the PCH trancoder underrun reporting state
15214 * within the crtc. With crtc for pipe A housing the underrun
15215 * reporting state for PCH transcoder A, crtc for pipe B housing
15216 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15217 * and marking underrun reporting as disabled for the non-existing
15218 * PCH transcoders B and C would prevent enabling the south
15219 * error interrupt (see cpt_can_enable_serr_int()).
15220 */
15221 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
15222 crtc->pch_fifo_underrun_disabled = true;
15223 }
15224 }
15225
15226 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15227 {
15228 struct intel_connector *connector;
15229
15230 /* We need to check both for a crtc link (meaning that the
15231 * encoder is active and trying to read from a pipe) and the
15232 * pipe itself being active. */
15233 bool has_active_crtc = encoder->base.crtc &&
15234 to_intel_crtc(encoder->base.crtc)->active;
15235
15236 connector = intel_encoder_find_connector(encoder);
15237 if (connector && !has_active_crtc) {
15238 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15239 encoder->base.base.id,
15240 encoder->base.name);
15241
15242 /* Connector is active, but has no active pipe. This is
15243 * fallout from our resume register restoring. Disable
15244 * the encoder manually again. */
15245 if (encoder->base.crtc) {
15246 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
15247
15248 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15249 encoder->base.base.id,
15250 encoder->base.name);
15251 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15252 if (encoder->post_disable)
15253 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15254 }
15255 encoder->base.crtc = NULL;
15256
15257 /* Inconsistent output/port/pipe state happens presumably due to
15258 * a bug in one of the get_hw_state functions. Or someplace else
15259 * in our code, like the register restore mess on resume. Clamp
15260 * things to off as a safer default. */
15261
15262 connector->base.dpms = DRM_MODE_DPMS_OFF;
15263 connector->base.encoder = NULL;
15264 }
15265 /* Enabled encoders without active connectors will be fixed in
15266 * the crtc fixup. */
15267 }
15268
15269 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
15270 {
15271 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15272
15273 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15274 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15275 i915_disable_vga(dev_priv);
15276 }
15277 }
15278
15279 void i915_redisable_vga(struct drm_i915_private *dev_priv)
15280 {
15281 /* This function can be called both from intel_modeset_setup_hw_state or
15282 * at a very early point in our resume sequence, where the power well
15283 * structures are not yet restored. Since this function is at a very
15284 * paranoid "someone might have enabled VGA while we were not looking"
15285 * level, just check if the power well is enabled instead of trying to
15286 * follow the "don't touch the power well if we don't need it" policy
15287 * the rest of the driver uses. */
15288 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15289 return;
15290
15291 i915_redisable_vga_power_on(dev_priv);
15292
15293 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15294 }
15295
15296 static bool primary_get_hw_state(struct intel_plane *plane)
15297 {
15298 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15299
15300 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15301 }
15302
15303 /* FIXME read out full plane state for all planes */
15304 static void readout_plane_state(struct intel_crtc *crtc)
15305 {
15306 struct intel_plane *primary = to_intel_plane(crtc->base.primary);
15307 bool visible;
15308
15309 visible = crtc->active && primary_get_hw_state(primary);
15310
15311 intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
15312 to_intel_plane_state(primary->base.state),
15313 visible);
15314 }
15315
15316 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15317 {
15318 struct drm_i915_private *dev_priv = to_i915(dev);
15319 enum pipe pipe;
15320 struct intel_crtc *crtc;
15321 struct intel_encoder *encoder;
15322 struct intel_connector *connector;
15323 int i;
15324
15325 dev_priv->active_crtcs = 0;
15326
15327 for_each_intel_crtc(dev, crtc) {
15328 struct intel_crtc_state *crtc_state =
15329 to_intel_crtc_state(crtc->base.state);
15330
15331 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15332 memset(crtc_state, 0, sizeof(*crtc_state));
15333 crtc_state->base.crtc = &crtc->base;
15334
15335 crtc_state->base.active = crtc_state->base.enable =
15336 dev_priv->display.get_pipe_config(crtc, crtc_state);
15337
15338 crtc->base.enabled = crtc_state->base.enable;
15339 crtc->active = crtc_state->base.active;
15340
15341 if (crtc_state->base.active)
15342 dev_priv->active_crtcs |= 1 << crtc->pipe;
15343
15344 readout_plane_state(crtc);
15345
15346 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15347 crtc->base.base.id, crtc->base.name,
15348 enableddisabled(crtc_state->base.active));
15349 }
15350
15351 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15352 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15353
15354 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15355 &pll->state.hw_state);
15356 pll->state.crtc_mask = 0;
15357 for_each_intel_crtc(dev, crtc) {
15358 struct intel_crtc_state *crtc_state =
15359 to_intel_crtc_state(crtc->base.state);
15360
15361 if (crtc_state->base.active &&
15362 crtc_state->shared_dpll == pll)
15363 pll->state.crtc_mask |= 1 << crtc->pipe;
15364 }
15365 pll->active_mask = pll->state.crtc_mask;
15366
15367 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15368 pll->name, pll->state.crtc_mask, pll->on);
15369 }
15370
15371 for_each_intel_encoder(dev, encoder) {
15372 pipe = 0;
15373
15374 if (encoder->get_hw_state(encoder, &pipe)) {
15375 struct intel_crtc_state *crtc_state;
15376
15377 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15378 crtc_state = to_intel_crtc_state(crtc->base.state);
15379
15380 encoder->base.crtc = &crtc->base;
15381 crtc_state->output_types |= 1 << encoder->type;
15382 encoder->get_config(encoder, crtc_state);
15383 } else {
15384 encoder->base.crtc = NULL;
15385 }
15386
15387 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15388 encoder->base.base.id, encoder->base.name,
15389 enableddisabled(encoder->base.crtc),
15390 pipe_name(pipe));
15391 }
15392
15393 for_each_intel_connector(dev, connector) {
15394 if (connector->get_hw_state(connector)) {
15395 connector->base.dpms = DRM_MODE_DPMS_ON;
15396
15397 encoder = connector->encoder;
15398 connector->base.encoder = &encoder->base;
15399
15400 if (encoder->base.crtc &&
15401 encoder->base.crtc->state->active) {
15402 /*
15403 * This has to be done during hardware readout
15404 * because anything calling .crtc_disable may
15405 * rely on the connector_mask being accurate.
15406 */
15407 encoder->base.crtc->state->connector_mask |=
15408 1 << drm_connector_index(&connector->base);
15409 encoder->base.crtc->state->encoder_mask |=
15410 1 << drm_encoder_index(&encoder->base);
15411 }
15412
15413 } else {
15414 connector->base.dpms = DRM_MODE_DPMS_OFF;
15415 connector->base.encoder = NULL;
15416 }
15417 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15418 connector->base.base.id, connector->base.name,
15419 enableddisabled(connector->base.encoder));
15420 }
15421
15422 for_each_intel_crtc(dev, crtc) {
15423 struct intel_crtc_state *crtc_state =
15424 to_intel_crtc_state(crtc->base.state);
15425 int pixclk = 0;
15426
15427 crtc->base.hwmode = crtc_state->base.adjusted_mode;
15428
15429 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15430 if (crtc_state->base.active) {
15431 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15432 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15433 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15434
15435 /*
15436 * The initial mode needs to be set in order to keep
15437 * the atomic core happy. It wants a valid mode if the
15438 * crtc's enabled, so we do the above call.
15439 *
15440 * But we don't set all the derived state fully, hence
15441 * set a flag to indicate that a full recalculation is
15442 * needed on the next commit.
15443 */
15444 crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15445
15446 intel_crtc_compute_pixel_rate(crtc_state);
15447
15448 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) ||
15449 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15450 pixclk = crtc_state->pixel_rate;
15451 else
15452 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15453
15454 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15455 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
15456 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15457
15458 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15459 update_scanline_offset(crtc);
15460 }
15461
15462 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15463
15464 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15465 }
15466 }
15467
15468 static void
15469 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15470 {
15471 struct intel_encoder *encoder;
15472
15473 for_each_intel_encoder(&dev_priv->drm, encoder) {
15474 u64 get_domains;
15475 enum intel_display_power_domain domain;
15476
15477 if (!encoder->get_power_domains)
15478 continue;
15479
15480 get_domains = encoder->get_power_domains(encoder);
15481 for_each_power_domain(domain, get_domains)
15482 intel_display_power_get(dev_priv, domain);
15483 }
15484 }
15485
15486 /* Scan out the current hw modeset state,
15487 * and sanitizes it to the current state
15488 */
15489 static void
15490 intel_modeset_setup_hw_state(struct drm_device *dev)
15491 {
15492 struct drm_i915_private *dev_priv = to_i915(dev);
15493 enum pipe pipe;
15494 struct intel_crtc *crtc;
15495 struct intel_encoder *encoder;
15496 int i;
15497
15498 intel_modeset_readout_hw_state(dev);
15499
15500 /* HW state is read out, now we need to sanitize this mess. */
15501 get_encoder_power_domains(dev_priv);
15502
15503 for_each_intel_encoder(dev, encoder) {
15504 intel_sanitize_encoder(encoder);
15505 }
15506
15507 for_each_pipe(dev_priv, pipe) {
15508 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15509
15510 intel_sanitize_crtc(crtc);
15511 intel_dump_pipe_config(crtc, crtc->config,
15512 "[setup_hw_state]");
15513 }
15514
15515 intel_modeset_update_connector_atomic_state(dev);
15516
15517 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15518 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15519
15520 if (!pll->on || pll->active_mask)
15521 continue;
15522
15523 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15524
15525 pll->funcs.disable(dev_priv, pll);
15526 pll->on = false;
15527 }
15528
15529 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15530 vlv_wm_get_hw_state(dev);
15531 vlv_wm_sanitize(dev_priv);
15532 } else if (IS_GEN9(dev_priv)) {
15533 skl_wm_get_hw_state(dev);
15534 } else if (HAS_PCH_SPLIT(dev_priv)) {
15535 ilk_wm_get_hw_state(dev);
15536 }
15537
15538 for_each_intel_crtc(dev, crtc) {
15539 u64 put_domains;
15540
15541 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15542 if (WARN_ON(put_domains))
15543 modeset_put_power_domains(dev_priv, put_domains);
15544 }
15545 intel_display_set_init_power(dev_priv, false);
15546
15547 intel_power_domains_verify_state(dev_priv);
15548
15549 intel_fbc_init_pipe_state(dev_priv);
15550 }
15551
15552 void intel_display_resume(struct drm_device *dev)
15553 {
15554 struct drm_i915_private *dev_priv = to_i915(dev);
15555 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15556 struct drm_modeset_acquire_ctx ctx;
15557 int ret;
15558
15559 dev_priv->modeset_restore_state = NULL;
15560 if (state)
15561 state->acquire_ctx = &ctx;
15562
15563 /*
15564 * This is a cludge because with real atomic modeset mode_config.mutex
15565 * won't be taken. Unfortunately some probed state like
15566 * audio_codec_enable is still protected by mode_config.mutex, so lock
15567 * it here for now.
15568 */
15569 mutex_lock(&dev->mode_config.mutex);
15570 drm_modeset_acquire_init(&ctx, 0);
15571
15572 while (1) {
15573 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15574 if (ret != -EDEADLK)
15575 break;
15576
15577 drm_modeset_backoff(&ctx);
15578 }
15579
15580 if (!ret)
15581 ret = __intel_display_resume(dev, state, &ctx);
15582
15583 drm_modeset_drop_locks(&ctx);
15584 drm_modeset_acquire_fini(&ctx);
15585 mutex_unlock(&dev->mode_config.mutex);
15586
15587 if (ret)
15588 DRM_ERROR("Restoring old state failed with %i\n", ret);
15589 if (state)
15590 drm_atomic_state_put(state);
15591 }
15592
15593 void intel_modeset_gem_init(struct drm_device *dev)
15594 {
15595 struct drm_i915_private *dev_priv = to_i915(dev);
15596
15597 intel_init_gt_powersave(dev_priv);
15598
15599 intel_setup_overlay(dev_priv);
15600 }
15601
15602 int intel_connector_register(struct drm_connector *connector)
15603 {
15604 struct intel_connector *intel_connector = to_intel_connector(connector);
15605 int ret;
15606
15607 ret = intel_backlight_device_register(intel_connector);
15608 if (ret)
15609 goto err;
15610
15611 return 0;
15612
15613 err:
15614 return ret;
15615 }
15616
15617 void intel_connector_unregister(struct drm_connector *connector)
15618 {
15619 struct intel_connector *intel_connector = to_intel_connector(connector);
15620
15621 intel_backlight_device_unregister(intel_connector);
15622 intel_panel_destroy_backlight(connector);
15623 }
15624
15625 void intel_modeset_cleanup(struct drm_device *dev)
15626 {
15627 struct drm_i915_private *dev_priv = to_i915(dev);
15628
15629 flush_work(&dev_priv->atomic_helper.free_work);
15630 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15631
15632 intel_disable_gt_powersave(dev_priv);
15633
15634 /*
15635 * Interrupts and polling as the first thing to avoid creating havoc.
15636 * Too much stuff here (turning of connectors, ...) would
15637 * experience fancy races otherwise.
15638 */
15639 intel_irq_uninstall(dev_priv);
15640
15641 /*
15642 * Due to the hpd irq storm handling the hotplug work can re-arm the
15643 * poll handlers. Hence disable polling after hpd handling is shut down.
15644 */
15645 drm_kms_helper_poll_fini(dev);
15646
15647 intel_unregister_dsm_handler();
15648
15649 intel_fbc_global_disable(dev_priv);
15650
15651 /* flush any delayed tasks or pending work */
15652 flush_scheduled_work();
15653
15654 drm_mode_config_cleanup(dev);
15655
15656 intel_cleanup_overlay(dev_priv);
15657
15658 intel_cleanup_gt_powersave(dev_priv);
15659
15660 intel_teardown_gmbus(dev_priv);
15661 }
15662
15663 void intel_connector_attach_encoder(struct intel_connector *connector,
15664 struct intel_encoder *encoder)
15665 {
15666 connector->encoder = encoder;
15667 drm_mode_connector_attach_encoder(&connector->base,
15668 &encoder->base);
15669 }
15670
15671 /*
15672 * set vga decode state - true == enable VGA decode
15673 */
15674 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15675 {
15676 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15677 u16 gmch_ctrl;
15678
15679 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15680 DRM_ERROR("failed to read control word\n");
15681 return -EIO;
15682 }
15683
15684 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15685 return 0;
15686
15687 if (state)
15688 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15689 else
15690 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15691
15692 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15693 DRM_ERROR("failed to write control word\n");
15694 return -EIO;
15695 }
15696
15697 return 0;
15698 }
15699
15700 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15701
15702 struct intel_display_error_state {
15703
15704 u32 power_well_driver;
15705
15706 int num_transcoders;
15707
15708 struct intel_cursor_error_state {
15709 u32 control;
15710 u32 position;
15711 u32 base;
15712 u32 size;
15713 } cursor[I915_MAX_PIPES];
15714
15715 struct intel_pipe_error_state {
15716 bool power_domain_on;
15717 u32 source;
15718 u32 stat;
15719 } pipe[I915_MAX_PIPES];
15720
15721 struct intel_plane_error_state {
15722 u32 control;
15723 u32 stride;
15724 u32 size;
15725 u32 pos;
15726 u32 addr;
15727 u32 surface;
15728 u32 tile_offset;
15729 } plane[I915_MAX_PIPES];
15730
15731 struct intel_transcoder_error_state {
15732 bool power_domain_on;
15733 enum transcoder cpu_transcoder;
15734
15735 u32 conf;
15736
15737 u32 htotal;
15738 u32 hblank;
15739 u32 hsync;
15740 u32 vtotal;
15741 u32 vblank;
15742 u32 vsync;
15743 } transcoder[4];
15744 };
15745
15746 struct intel_display_error_state *
15747 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15748 {
15749 struct intel_display_error_state *error;
15750 int transcoders[] = {
15751 TRANSCODER_A,
15752 TRANSCODER_B,
15753 TRANSCODER_C,
15754 TRANSCODER_EDP,
15755 };
15756 int i;
15757
15758 if (INTEL_INFO(dev_priv)->num_pipes == 0)
15759 return NULL;
15760
15761 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15762 if (error == NULL)
15763 return NULL;
15764
15765 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15766 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15767
15768 for_each_pipe(dev_priv, i) {
15769 error->pipe[i].power_domain_on =
15770 __intel_display_power_is_enabled(dev_priv,
15771 POWER_DOMAIN_PIPE(i));
15772 if (!error->pipe[i].power_domain_on)
15773 continue;
15774
15775 error->cursor[i].control = I915_READ(CURCNTR(i));
15776 error->cursor[i].position = I915_READ(CURPOS(i));
15777 error->cursor[i].base = I915_READ(CURBASE(i));
15778
15779 error->plane[i].control = I915_READ(DSPCNTR(i));
15780 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15781 if (INTEL_GEN(dev_priv) <= 3) {
15782 error->plane[i].size = I915_READ(DSPSIZE(i));
15783 error->plane[i].pos = I915_READ(DSPPOS(i));
15784 }
15785 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15786 error->plane[i].addr = I915_READ(DSPADDR(i));
15787 if (INTEL_GEN(dev_priv) >= 4) {
15788 error->plane[i].surface = I915_READ(DSPSURF(i));
15789 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15790 }
15791
15792 error->pipe[i].source = I915_READ(PIPESRC(i));
15793
15794 if (HAS_GMCH_DISPLAY(dev_priv))
15795 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15796 }
15797
15798 /* Note: this does not include DSI transcoders. */
15799 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15800 if (HAS_DDI(dev_priv))
15801 error->num_transcoders++; /* Account for eDP. */
15802
15803 for (i = 0; i < error->num_transcoders; i++) {
15804 enum transcoder cpu_transcoder = transcoders[i];
15805
15806 error->transcoder[i].power_domain_on =
15807 __intel_display_power_is_enabled(dev_priv,
15808 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15809 if (!error->transcoder[i].power_domain_on)
15810 continue;
15811
15812 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15813
15814 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15815 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15816 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15817 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15818 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15819 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15820 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15821 }
15822
15823 return error;
15824 }
15825
15826 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15827
15828 void
15829 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15830 struct intel_display_error_state *error)
15831 {
15832 struct drm_i915_private *dev_priv = m->i915;
15833 int i;
15834
15835 if (!error)
15836 return;
15837
15838 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15839 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15840 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15841 error->power_well_driver);
15842 for_each_pipe(dev_priv, i) {
15843 err_printf(m, "Pipe [%d]:\n", i);
15844 err_printf(m, " Power: %s\n",
15845 onoff(error->pipe[i].power_domain_on));
15846 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15847 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15848
15849 err_printf(m, "Plane [%d]:\n", i);
15850 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15851 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15852 if (INTEL_GEN(dev_priv) <= 3) {
15853 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15854 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15855 }
15856 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15857 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15858 if (INTEL_GEN(dev_priv) >= 4) {
15859 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15860 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15861 }
15862
15863 err_printf(m, "Cursor [%d]:\n", i);
15864 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15865 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15866 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15867 }
15868
15869 for (i = 0; i < error->num_transcoders; i++) {
15870 err_printf(m, "CPU transcoder: %s\n",
15871 transcoder_name(error->transcoder[i].cpu_transcoder));
15872 err_printf(m, " Power: %s\n",
15873 onoff(error->transcoder[i].power_domain_on));
15874 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15875 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15876 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15877 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15878 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15879 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15880 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15881 }
15882 }
15883
15884 #endif
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