2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
40 #include "i915_gem_clflush.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
52 /* Primary plane formats for gen <= 3 */
53 static const uint32_t i8xx_primary_formats
[] = {
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t i965_primary_formats
[] = {
66 DRM_FORMAT_XRGB2101010
,
67 DRM_FORMAT_XBGR2101010
,
70 static const uint64_t i9xx_format_modifiers
[] = {
71 I915_FORMAT_MOD_X_TILED
,
72 DRM_FORMAT_MOD_LINEAR
,
73 DRM_FORMAT_MOD_INVALID
76 static const uint32_t skl_primary_formats
[] = {
83 DRM_FORMAT_XRGB2101010
,
84 DRM_FORMAT_XBGR2101010
,
91 static const uint64_t skl_format_modifiers_noccs
[] = {
92 I915_FORMAT_MOD_Yf_TILED
,
93 I915_FORMAT_MOD_Y_TILED
,
94 I915_FORMAT_MOD_X_TILED
,
95 DRM_FORMAT_MOD_LINEAR
,
96 DRM_FORMAT_MOD_INVALID
99 static const uint64_t skl_format_modifiers_ccs
[] = {
100 I915_FORMAT_MOD_Yf_TILED_CCS
,
101 I915_FORMAT_MOD_Y_TILED_CCS
,
102 I915_FORMAT_MOD_Yf_TILED
,
103 I915_FORMAT_MOD_Y_TILED
,
104 I915_FORMAT_MOD_X_TILED
,
105 DRM_FORMAT_MOD_LINEAR
,
106 DRM_FORMAT_MOD_INVALID
110 static const uint32_t intel_cursor_formats
[] = {
114 static const uint64_t cursor_format_modifiers
[] = {
115 DRM_FORMAT_MOD_LINEAR
,
116 DRM_FORMAT_MOD_INVALID
119 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
120 struct intel_crtc_state
*pipe_config
);
121 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
122 struct intel_crtc_state
*pipe_config
);
124 static int intel_framebuffer_init(struct intel_framebuffer
*ifb
,
125 struct drm_i915_gem_object
*obj
,
126 struct drm_mode_fb_cmd2
*mode_cmd
);
127 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
128 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
129 static void intel_set_pipe_src_size(struct intel_crtc
*intel_crtc
);
130 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
131 struct intel_link_m_n
*m_n
,
132 struct intel_link_m_n
*m2_n2
);
133 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
134 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
135 static void haswell_set_pipemisc(struct drm_crtc
*crtc
);
136 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
137 const struct intel_crtc_state
*pipe_config
);
138 static void chv_prepare_pll(struct intel_crtc
*crtc
,
139 const struct intel_crtc_state
*pipe_config
);
140 static void intel_begin_crtc_commit(struct drm_crtc
*, struct drm_crtc_state
*);
141 static void intel_finish_crtc_commit(struct drm_crtc
*, struct drm_crtc_state
*);
142 static void intel_crtc_init_scalers(struct intel_crtc
*crtc
,
143 struct intel_crtc_state
*crtc_state
);
144 static void skylake_pfit_enable(struct intel_crtc
*crtc
);
145 static void ironlake_pfit_disable(struct intel_crtc
*crtc
, bool force
);
146 static void ironlake_pfit_enable(struct intel_crtc
*crtc
);
147 static void intel_modeset_setup_hw_state(struct drm_device
*dev
,
148 struct drm_modeset_acquire_ctx
*ctx
);
149 static void intel_pre_disable_primary_noatomic(struct drm_crtc
*crtc
);
154 } dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
158 int p2_slow
, p2_fast
;
162 /* returns HPLL frequency in kHz */
163 int vlv_get_hpll_vco(struct drm_i915_private
*dev_priv
)
165 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
167 /* Obtain SKU information */
168 mutex_lock(&dev_priv
->sb_lock
);
169 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
170 CCK_FUSE_HPLL_FREQ_MASK
;
171 mutex_unlock(&dev_priv
->sb_lock
);
173 return vco_freq
[hpll_freq
] * 1000;
176 int vlv_get_cck_clock(struct drm_i915_private
*dev_priv
,
177 const char *name
, u32 reg
, int ref_freq
)
182 mutex_lock(&dev_priv
->sb_lock
);
183 val
= vlv_cck_read(dev_priv
, reg
);
184 mutex_unlock(&dev_priv
->sb_lock
);
186 divider
= val
& CCK_FREQUENCY_VALUES
;
188 WARN((val
& CCK_FREQUENCY_STATUS
) !=
189 (divider
<< CCK_FREQUENCY_STATUS_SHIFT
),
190 "%s change in progress\n", name
);
192 return DIV_ROUND_CLOSEST(ref_freq
<< 1, divider
+ 1);
195 int vlv_get_cck_clock_hpll(struct drm_i915_private
*dev_priv
,
196 const char *name
, u32 reg
)
198 if (dev_priv
->hpll_freq
== 0)
199 dev_priv
->hpll_freq
= vlv_get_hpll_vco(dev_priv
);
201 return vlv_get_cck_clock(dev_priv
, name
, reg
,
202 dev_priv
->hpll_freq
);
205 static void intel_update_czclk(struct drm_i915_private
*dev_priv
)
207 if (!(IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)))
210 dev_priv
->czclk_freq
= vlv_get_cck_clock_hpll(dev_priv
, "czclk",
211 CCK_CZ_CLOCK_CONTROL
);
213 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv
->czclk_freq
);
216 static inline u32
/* units of 100MHz */
217 intel_fdi_link_freq(struct drm_i915_private
*dev_priv
,
218 const struct intel_crtc_state
*pipe_config
)
220 if (HAS_DDI(dev_priv
))
221 return pipe_config
->port_clock
; /* SPLL */
222 else if (IS_GEN5(dev_priv
))
223 return ((I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2) * 10000;
228 static const struct intel_limit intel_limits_i8xx_dac
= {
229 .dot
= { .min
= 25000, .max
= 350000 },
230 .vco
= { .min
= 908000, .max
= 1512000 },
231 .n
= { .min
= 2, .max
= 16 },
232 .m
= { .min
= 96, .max
= 140 },
233 .m1
= { .min
= 18, .max
= 26 },
234 .m2
= { .min
= 6, .max
= 16 },
235 .p
= { .min
= 4, .max
= 128 },
236 .p1
= { .min
= 2, .max
= 33 },
237 .p2
= { .dot_limit
= 165000,
238 .p2_slow
= 4, .p2_fast
= 2 },
241 static const struct intel_limit intel_limits_i8xx_dvo
= {
242 .dot
= { .min
= 25000, .max
= 350000 },
243 .vco
= { .min
= 908000, .max
= 1512000 },
244 .n
= { .min
= 2, .max
= 16 },
245 .m
= { .min
= 96, .max
= 140 },
246 .m1
= { .min
= 18, .max
= 26 },
247 .m2
= { .min
= 6, .max
= 16 },
248 .p
= { .min
= 4, .max
= 128 },
249 .p1
= { .min
= 2, .max
= 33 },
250 .p2
= { .dot_limit
= 165000,
251 .p2_slow
= 4, .p2_fast
= 4 },
254 static const struct intel_limit intel_limits_i8xx_lvds
= {
255 .dot
= { .min
= 25000, .max
= 350000 },
256 .vco
= { .min
= 908000, .max
= 1512000 },
257 .n
= { .min
= 2, .max
= 16 },
258 .m
= { .min
= 96, .max
= 140 },
259 .m1
= { .min
= 18, .max
= 26 },
260 .m2
= { .min
= 6, .max
= 16 },
261 .p
= { .min
= 4, .max
= 128 },
262 .p1
= { .min
= 1, .max
= 6 },
263 .p2
= { .dot_limit
= 165000,
264 .p2_slow
= 14, .p2_fast
= 7 },
267 static const struct intel_limit intel_limits_i9xx_sdvo
= {
268 .dot
= { .min
= 20000, .max
= 400000 },
269 .vco
= { .min
= 1400000, .max
= 2800000 },
270 .n
= { .min
= 1, .max
= 6 },
271 .m
= { .min
= 70, .max
= 120 },
272 .m1
= { .min
= 8, .max
= 18 },
273 .m2
= { .min
= 3, .max
= 7 },
274 .p
= { .min
= 5, .max
= 80 },
275 .p1
= { .min
= 1, .max
= 8 },
276 .p2
= { .dot_limit
= 200000,
277 .p2_slow
= 10, .p2_fast
= 5 },
280 static const struct intel_limit intel_limits_i9xx_lvds
= {
281 .dot
= { .min
= 20000, .max
= 400000 },
282 .vco
= { .min
= 1400000, .max
= 2800000 },
283 .n
= { .min
= 1, .max
= 6 },
284 .m
= { .min
= 70, .max
= 120 },
285 .m1
= { .min
= 8, .max
= 18 },
286 .m2
= { .min
= 3, .max
= 7 },
287 .p
= { .min
= 7, .max
= 98 },
288 .p1
= { .min
= 1, .max
= 8 },
289 .p2
= { .dot_limit
= 112000,
290 .p2_slow
= 14, .p2_fast
= 7 },
294 static const struct intel_limit intel_limits_g4x_sdvo
= {
295 .dot
= { .min
= 25000, .max
= 270000 },
296 .vco
= { .min
= 1750000, .max
= 3500000},
297 .n
= { .min
= 1, .max
= 4 },
298 .m
= { .min
= 104, .max
= 138 },
299 .m1
= { .min
= 17, .max
= 23 },
300 .m2
= { .min
= 5, .max
= 11 },
301 .p
= { .min
= 10, .max
= 30 },
302 .p1
= { .min
= 1, .max
= 3},
303 .p2
= { .dot_limit
= 270000,
309 static const struct intel_limit intel_limits_g4x_hdmi
= {
310 .dot
= { .min
= 22000, .max
= 400000 },
311 .vco
= { .min
= 1750000, .max
= 3500000},
312 .n
= { .min
= 1, .max
= 4 },
313 .m
= { .min
= 104, .max
= 138 },
314 .m1
= { .min
= 16, .max
= 23 },
315 .m2
= { .min
= 5, .max
= 11 },
316 .p
= { .min
= 5, .max
= 80 },
317 .p1
= { .min
= 1, .max
= 8},
318 .p2
= { .dot_limit
= 165000,
319 .p2_slow
= 10, .p2_fast
= 5 },
322 static const struct intel_limit intel_limits_g4x_single_channel_lvds
= {
323 .dot
= { .min
= 20000, .max
= 115000 },
324 .vco
= { .min
= 1750000, .max
= 3500000 },
325 .n
= { .min
= 1, .max
= 3 },
326 .m
= { .min
= 104, .max
= 138 },
327 .m1
= { .min
= 17, .max
= 23 },
328 .m2
= { .min
= 5, .max
= 11 },
329 .p
= { .min
= 28, .max
= 112 },
330 .p1
= { .min
= 2, .max
= 8 },
331 .p2
= { .dot_limit
= 0,
332 .p2_slow
= 14, .p2_fast
= 14
336 static const struct intel_limit intel_limits_g4x_dual_channel_lvds
= {
337 .dot
= { .min
= 80000, .max
= 224000 },
338 .vco
= { .min
= 1750000, .max
= 3500000 },
339 .n
= { .min
= 1, .max
= 3 },
340 .m
= { .min
= 104, .max
= 138 },
341 .m1
= { .min
= 17, .max
= 23 },
342 .m2
= { .min
= 5, .max
= 11 },
343 .p
= { .min
= 14, .max
= 42 },
344 .p1
= { .min
= 2, .max
= 6 },
345 .p2
= { .dot_limit
= 0,
346 .p2_slow
= 7, .p2_fast
= 7
350 static const struct intel_limit intel_limits_pineview_sdvo
= {
351 .dot
= { .min
= 20000, .max
= 400000},
352 .vco
= { .min
= 1700000, .max
= 3500000 },
353 /* Pineview's Ncounter is a ring counter */
354 .n
= { .min
= 3, .max
= 6 },
355 .m
= { .min
= 2, .max
= 256 },
356 /* Pineview only has one combined m divider, which we treat as m2. */
357 .m1
= { .min
= 0, .max
= 0 },
358 .m2
= { .min
= 0, .max
= 254 },
359 .p
= { .min
= 5, .max
= 80 },
360 .p1
= { .min
= 1, .max
= 8 },
361 .p2
= { .dot_limit
= 200000,
362 .p2_slow
= 10, .p2_fast
= 5 },
365 static const struct intel_limit intel_limits_pineview_lvds
= {
366 .dot
= { .min
= 20000, .max
= 400000 },
367 .vco
= { .min
= 1700000, .max
= 3500000 },
368 .n
= { .min
= 3, .max
= 6 },
369 .m
= { .min
= 2, .max
= 256 },
370 .m1
= { .min
= 0, .max
= 0 },
371 .m2
= { .min
= 0, .max
= 254 },
372 .p
= { .min
= 7, .max
= 112 },
373 .p1
= { .min
= 1, .max
= 8 },
374 .p2
= { .dot_limit
= 112000,
375 .p2_slow
= 14, .p2_fast
= 14 },
378 /* Ironlake / Sandybridge
380 * We calculate clock using (register_value + 2) for N/M1/M2, so here
381 * the range value for them is (actual_value - 2).
383 static const struct intel_limit intel_limits_ironlake_dac
= {
384 .dot
= { .min
= 25000, .max
= 350000 },
385 .vco
= { .min
= 1760000, .max
= 3510000 },
386 .n
= { .min
= 1, .max
= 5 },
387 .m
= { .min
= 79, .max
= 127 },
388 .m1
= { .min
= 12, .max
= 22 },
389 .m2
= { .min
= 5, .max
= 9 },
390 .p
= { .min
= 5, .max
= 80 },
391 .p1
= { .min
= 1, .max
= 8 },
392 .p2
= { .dot_limit
= 225000,
393 .p2_slow
= 10, .p2_fast
= 5 },
396 static const struct intel_limit intel_limits_ironlake_single_lvds
= {
397 .dot
= { .min
= 25000, .max
= 350000 },
398 .vco
= { .min
= 1760000, .max
= 3510000 },
399 .n
= { .min
= 1, .max
= 3 },
400 .m
= { .min
= 79, .max
= 118 },
401 .m1
= { .min
= 12, .max
= 22 },
402 .m2
= { .min
= 5, .max
= 9 },
403 .p
= { .min
= 28, .max
= 112 },
404 .p1
= { .min
= 2, .max
= 8 },
405 .p2
= { .dot_limit
= 225000,
406 .p2_slow
= 14, .p2_fast
= 14 },
409 static const struct intel_limit intel_limits_ironlake_dual_lvds
= {
410 .dot
= { .min
= 25000, .max
= 350000 },
411 .vco
= { .min
= 1760000, .max
= 3510000 },
412 .n
= { .min
= 1, .max
= 3 },
413 .m
= { .min
= 79, .max
= 127 },
414 .m1
= { .min
= 12, .max
= 22 },
415 .m2
= { .min
= 5, .max
= 9 },
416 .p
= { .min
= 14, .max
= 56 },
417 .p1
= { .min
= 2, .max
= 8 },
418 .p2
= { .dot_limit
= 225000,
419 .p2_slow
= 7, .p2_fast
= 7 },
422 /* LVDS 100mhz refclk limits. */
423 static const struct intel_limit intel_limits_ironlake_single_lvds_100m
= {
424 .dot
= { .min
= 25000, .max
= 350000 },
425 .vco
= { .min
= 1760000, .max
= 3510000 },
426 .n
= { .min
= 1, .max
= 2 },
427 .m
= { .min
= 79, .max
= 126 },
428 .m1
= { .min
= 12, .max
= 22 },
429 .m2
= { .min
= 5, .max
= 9 },
430 .p
= { .min
= 28, .max
= 112 },
431 .p1
= { .min
= 2, .max
= 8 },
432 .p2
= { .dot_limit
= 225000,
433 .p2_slow
= 14, .p2_fast
= 14 },
436 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m
= {
437 .dot
= { .min
= 25000, .max
= 350000 },
438 .vco
= { .min
= 1760000, .max
= 3510000 },
439 .n
= { .min
= 1, .max
= 3 },
440 .m
= { .min
= 79, .max
= 126 },
441 .m1
= { .min
= 12, .max
= 22 },
442 .m2
= { .min
= 5, .max
= 9 },
443 .p
= { .min
= 14, .max
= 42 },
444 .p1
= { .min
= 2, .max
= 6 },
445 .p2
= { .dot_limit
= 225000,
446 .p2_slow
= 7, .p2_fast
= 7 },
449 static const struct intel_limit intel_limits_vlv
= {
451 * These are the data rate limits (measured in fast clocks)
452 * since those are the strictest limits we have. The fast
453 * clock and actual rate limits are more relaxed, so checking
454 * them would make no difference.
456 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
457 .vco
= { .min
= 4000000, .max
= 6000000 },
458 .n
= { .min
= 1, .max
= 7 },
459 .m1
= { .min
= 2, .max
= 3 },
460 .m2
= { .min
= 11, .max
= 156 },
461 .p1
= { .min
= 2, .max
= 3 },
462 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
465 static const struct intel_limit intel_limits_chv
= {
467 * These are the data rate limits (measured in fast clocks)
468 * since those are the strictest limits we have. The fast
469 * clock and actual rate limits are more relaxed, so checking
470 * them would make no difference.
472 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
473 .vco
= { .min
= 4800000, .max
= 6480000 },
474 .n
= { .min
= 1, .max
= 1 },
475 .m1
= { .min
= 2, .max
= 2 },
476 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
477 .p1
= { .min
= 2, .max
= 4 },
478 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
481 static const struct intel_limit intel_limits_bxt
= {
482 /* FIXME: find real dot limits */
483 .dot
= { .min
= 0, .max
= INT_MAX
},
484 .vco
= { .min
= 4800000, .max
= 6700000 },
485 .n
= { .min
= 1, .max
= 1 },
486 .m1
= { .min
= 2, .max
= 2 },
487 /* FIXME: find real m2 limits */
488 .m2
= { .min
= 2 << 22, .max
= 255 << 22 },
489 .p1
= { .min
= 2, .max
= 4 },
490 .p2
= { .p2_slow
= 1, .p2_fast
= 20 },
494 needs_modeset(struct drm_crtc_state
*state
)
496 return drm_atomic_crtc_needs_modeset(state
);
500 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
501 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
502 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
503 * The helpers' return value is the rate of the clock that is fed to the
504 * display engine's pipe which can be the above fast dot clock rate or a
505 * divided-down version of it.
507 /* m1 is reserved as 0 in Pineview, n is a ring counter */
508 static int pnv_calc_dpll_params(int refclk
, struct dpll
*clock
)
510 clock
->m
= clock
->m2
+ 2;
511 clock
->p
= clock
->p1
* clock
->p2
;
512 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
514 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
515 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
520 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
522 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
525 static int i9xx_calc_dpll_params(int refclk
, struct dpll
*clock
)
527 clock
->m
= i9xx_dpll_compute_m(clock
);
528 clock
->p
= clock
->p1
* clock
->p2
;
529 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
531 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
532 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
537 static int vlv_calc_dpll_params(int refclk
, struct dpll
*clock
)
539 clock
->m
= clock
->m1
* clock
->m2
;
540 clock
->p
= clock
->p1
* clock
->p2
;
541 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
543 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
544 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
546 return clock
->dot
/ 5;
549 int chv_calc_dpll_params(int refclk
, struct dpll
*clock
)
551 clock
->m
= clock
->m1
* clock
->m2
;
552 clock
->p
= clock
->p1
* clock
->p2
;
553 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
555 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
557 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
559 return clock
->dot
/ 5;
562 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
564 * Returns whether the given set of divisors are valid for a given refclk with
565 * the given connectors.
568 static bool intel_PLL_is_valid(struct drm_i915_private
*dev_priv
,
569 const struct intel_limit
*limit
,
570 const struct dpll
*clock
)
572 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
573 INTELPllInvalid("n out of range\n");
574 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
575 INTELPllInvalid("p1 out of range\n");
576 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
577 INTELPllInvalid("m2 out of range\n");
578 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
579 INTELPllInvalid("m1 out of range\n");
581 if (!IS_PINEVIEW(dev_priv
) && !IS_VALLEYVIEW(dev_priv
) &&
582 !IS_CHERRYVIEW(dev_priv
) && !IS_GEN9_LP(dev_priv
))
583 if (clock
->m1
<= clock
->m2
)
584 INTELPllInvalid("m1 <= m2\n");
586 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
) &&
587 !IS_GEN9_LP(dev_priv
)) {
588 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
589 INTELPllInvalid("p out of range\n");
590 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
591 INTELPllInvalid("m out of range\n");
594 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
595 INTELPllInvalid("vco out of range\n");
596 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
597 * connector, etc., rather than just a single range.
599 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
600 INTELPllInvalid("dot out of range\n");
606 i9xx_select_p2_div(const struct intel_limit
*limit
,
607 const struct intel_crtc_state
*crtc_state
,
610 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
612 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
614 * For LVDS just rely on its current settings for dual-channel.
615 * We haven't figured out how to reliably set up different
616 * single/dual channel state, if we even can.
618 if (intel_is_dual_link_lvds(dev
))
619 return limit
->p2
.p2_fast
;
621 return limit
->p2
.p2_slow
;
623 if (target
< limit
->p2
.dot_limit
)
624 return limit
->p2
.p2_slow
;
626 return limit
->p2
.p2_fast
;
631 * Returns a set of divisors for the desired target clock with the given
632 * refclk, or FALSE. The returned values represent the clock equation:
633 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
635 * Target and reference clocks are specified in kHz.
637 * If match_clock is provided, then best_clock P divider must match the P
638 * divider from @match_clock used for LVDS downclocking.
641 i9xx_find_best_dpll(const struct intel_limit
*limit
,
642 struct intel_crtc_state
*crtc_state
,
643 int target
, int refclk
, struct dpll
*match_clock
,
644 struct dpll
*best_clock
)
646 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
650 memset(best_clock
, 0, sizeof(*best_clock
));
652 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
654 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
656 for (clock
.m2
= limit
->m2
.min
;
657 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
658 if (clock
.m2
>= clock
.m1
)
660 for (clock
.n
= limit
->n
.min
;
661 clock
.n
<= limit
->n
.max
; clock
.n
++) {
662 for (clock
.p1
= limit
->p1
.min
;
663 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
666 i9xx_calc_dpll_params(refclk
, &clock
);
667 if (!intel_PLL_is_valid(to_i915(dev
),
672 clock
.p
!= match_clock
->p
)
675 this_err
= abs(clock
.dot
- target
);
676 if (this_err
< err
) {
685 return (err
!= target
);
689 * Returns a set of divisors for the desired target clock with the given
690 * refclk, or FALSE. The returned values represent the clock equation:
691 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
693 * Target and reference clocks are specified in kHz.
695 * If match_clock is provided, then best_clock P divider must match the P
696 * divider from @match_clock used for LVDS downclocking.
699 pnv_find_best_dpll(const struct intel_limit
*limit
,
700 struct intel_crtc_state
*crtc_state
,
701 int target
, int refclk
, struct dpll
*match_clock
,
702 struct dpll
*best_clock
)
704 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
708 memset(best_clock
, 0, sizeof(*best_clock
));
710 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
712 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
714 for (clock
.m2
= limit
->m2
.min
;
715 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
716 for (clock
.n
= limit
->n
.min
;
717 clock
.n
<= limit
->n
.max
; clock
.n
++) {
718 for (clock
.p1
= limit
->p1
.min
;
719 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
722 pnv_calc_dpll_params(refclk
, &clock
);
723 if (!intel_PLL_is_valid(to_i915(dev
),
728 clock
.p
!= match_clock
->p
)
731 this_err
= abs(clock
.dot
- target
);
732 if (this_err
< err
) {
741 return (err
!= target
);
745 * Returns a set of divisors for the desired target clock with the given
746 * refclk, or FALSE. The returned values represent the clock equation:
747 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
749 * Target and reference clocks are specified in kHz.
751 * If match_clock is provided, then best_clock P divider must match the P
752 * divider from @match_clock used for LVDS downclocking.
755 g4x_find_best_dpll(const struct intel_limit
*limit
,
756 struct intel_crtc_state
*crtc_state
,
757 int target
, int refclk
, struct dpll
*match_clock
,
758 struct dpll
*best_clock
)
760 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
764 /* approximately equals target * 0.00585 */
765 int err_most
= (target
>> 8) + (target
>> 9);
767 memset(best_clock
, 0, sizeof(*best_clock
));
769 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
771 max_n
= limit
->n
.max
;
772 /* based on hardware requirement, prefer smaller n to precision */
773 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
774 /* based on hardware requirement, prefere larger m1,m2 */
775 for (clock
.m1
= limit
->m1
.max
;
776 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
777 for (clock
.m2
= limit
->m2
.max
;
778 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
779 for (clock
.p1
= limit
->p1
.max
;
780 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
783 i9xx_calc_dpll_params(refclk
, &clock
);
784 if (!intel_PLL_is_valid(to_i915(dev
),
789 this_err
= abs(clock
.dot
- target
);
790 if (this_err
< err_most
) {
804 * Check if the calculated PLL configuration is more optimal compared to the
805 * best configuration and error found so far. Return the calculated error.
807 static bool vlv_PLL_is_optimal(struct drm_device
*dev
, int target_freq
,
808 const struct dpll
*calculated_clock
,
809 const struct dpll
*best_clock
,
810 unsigned int best_error_ppm
,
811 unsigned int *error_ppm
)
814 * For CHV ignore the error and consider only the P value.
815 * Prefer a bigger P value based on HW requirements.
817 if (IS_CHERRYVIEW(to_i915(dev
))) {
820 return calculated_clock
->p
> best_clock
->p
;
823 if (WARN_ON_ONCE(!target_freq
))
826 *error_ppm
= div_u64(1000000ULL *
827 abs(target_freq
- calculated_clock
->dot
),
830 * Prefer a better P value over a better (smaller) error if the error
831 * is small. Ensure this preference for future configurations too by
832 * setting the error to 0.
834 if (*error_ppm
< 100 && calculated_clock
->p
> best_clock
->p
) {
840 return *error_ppm
+ 10 < best_error_ppm
;
844 * Returns a set of divisors for the desired target clock with the given
845 * refclk, or FALSE. The returned values represent the clock equation:
846 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
849 vlv_find_best_dpll(const struct intel_limit
*limit
,
850 struct intel_crtc_state
*crtc_state
,
851 int target
, int refclk
, struct dpll
*match_clock
,
852 struct dpll
*best_clock
)
854 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
855 struct drm_device
*dev
= crtc
->base
.dev
;
857 unsigned int bestppm
= 1000000;
858 /* min update 19.2 MHz */
859 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
862 target
*= 5; /* fast clock */
864 memset(best_clock
, 0, sizeof(*best_clock
));
866 /* based on hardware requirement, prefer smaller n to precision */
867 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
868 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
869 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
870 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
871 clock
.p
= clock
.p1
* clock
.p2
;
872 /* based on hardware requirement, prefer bigger m1,m2 values */
873 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
876 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
879 vlv_calc_dpll_params(refclk
, &clock
);
881 if (!intel_PLL_is_valid(to_i915(dev
),
886 if (!vlv_PLL_is_optimal(dev
, target
,
904 * Returns a set of divisors for the desired target clock with the given
905 * refclk, or FALSE. The returned values represent the clock equation:
906 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
909 chv_find_best_dpll(const struct intel_limit
*limit
,
910 struct intel_crtc_state
*crtc_state
,
911 int target
, int refclk
, struct dpll
*match_clock
,
912 struct dpll
*best_clock
)
914 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
915 struct drm_device
*dev
= crtc
->base
.dev
;
916 unsigned int best_error_ppm
;
921 memset(best_clock
, 0, sizeof(*best_clock
));
922 best_error_ppm
= 1000000;
925 * Based on hardware doc, the n always set to 1, and m1 always
926 * set to 2. If requires to support 200Mhz refclk, we need to
927 * revisit this because n may not 1 anymore.
929 clock
.n
= 1, clock
.m1
= 2;
930 target
*= 5; /* fast clock */
932 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
933 for (clock
.p2
= limit
->p2
.p2_fast
;
934 clock
.p2
>= limit
->p2
.p2_slow
;
935 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
936 unsigned int error_ppm
;
938 clock
.p
= clock
.p1
* clock
.p2
;
940 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
941 clock
.n
) << 22, refclk
* clock
.m1
);
943 if (m2
> INT_MAX
/clock
.m1
)
948 chv_calc_dpll_params(refclk
, &clock
);
950 if (!intel_PLL_is_valid(to_i915(dev
), limit
, &clock
))
953 if (!vlv_PLL_is_optimal(dev
, target
, &clock
, best_clock
,
954 best_error_ppm
, &error_ppm
))
958 best_error_ppm
= error_ppm
;
966 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
967 struct dpll
*best_clock
)
970 const struct intel_limit
*limit
= &intel_limits_bxt
;
972 return chv_find_best_dpll(limit
, crtc_state
,
973 target_clock
, refclk
, NULL
, best_clock
);
976 bool intel_crtc_active(struct intel_crtc
*crtc
)
978 /* Be paranoid as we can arrive here with only partial
979 * state retrieved from the hardware during setup.
981 * We can ditch the adjusted_mode.crtc_clock check as soon
982 * as Haswell has gained clock readout/fastboot support.
984 * We can ditch the crtc->primary->fb check as soon as we can
985 * properly reconstruct framebuffers.
987 * FIXME: The intel_crtc->active here should be switched to
988 * crtc->state->active once we have proper CRTC states wired up
991 return crtc
->active
&& crtc
->base
.primary
->state
->fb
&&
992 crtc
->config
->base
.adjusted_mode
.crtc_clock
;
995 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
998 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
1000 return crtc
->config
->cpu_transcoder
;
1003 static bool pipe_scanline_is_moving(struct drm_i915_private
*dev_priv
,
1006 i915_reg_t reg
= PIPEDSL(pipe
);
1010 if (IS_GEN2(dev_priv
))
1011 line_mask
= DSL_LINEMASK_GEN2
;
1013 line_mask
= DSL_LINEMASK_GEN3
;
1015 line1
= I915_READ(reg
) & line_mask
;
1017 line2
= I915_READ(reg
) & line_mask
;
1019 return line1
!= line2
;
1022 static void wait_for_pipe_scanline_moving(struct intel_crtc
*crtc
, bool state
)
1024 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1025 enum pipe pipe
= crtc
->pipe
;
1027 /* Wait for the display line to settle/start moving */
1028 if (wait_for(pipe_scanline_is_moving(dev_priv
, pipe
) == state
, 100))
1029 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1030 pipe_name(pipe
), onoff(state
));
1033 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc
*crtc
)
1035 wait_for_pipe_scanline_moving(crtc
, false);
1038 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc
*crtc
)
1040 wait_for_pipe_scanline_moving(crtc
, true);
1044 * intel_wait_for_pipe_off - wait for pipe to turn off
1045 * @crtc: crtc whose pipe to wait for
1047 * After disabling a pipe, we can't wait for vblank in the usual way,
1048 * spinning on the vblank interrupt status bit, since we won't actually
1049 * see an interrupt when the pipe is disabled.
1051 * On Gen4 and above:
1052 * wait for the pipe register state bit to turn off
1055 * wait for the display line value to settle (it usually
1056 * ends up stopping at the start of the next frame).
1059 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
1061 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1062 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1064 if (INTEL_GEN(dev_priv
) >= 4) {
1065 i915_reg_t reg
= PIPECONF(cpu_transcoder
);
1067 /* Wait for the Pipe State to go off */
1068 if (intel_wait_for_register(dev_priv
,
1069 reg
, I965_PIPECONF_ACTIVE
, 0,
1071 WARN(1, "pipe_off wait timed out\n");
1073 intel_wait_for_pipe_scanline_stopped(crtc
);
1077 /* Only for pre-ILK configs */
1078 void assert_pll(struct drm_i915_private
*dev_priv
,
1079 enum pipe pipe
, bool state
)
1084 val
= I915_READ(DPLL(pipe
));
1085 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1086 I915_STATE_WARN(cur_state
!= state
,
1087 "PLL state assertion failure (expected %s, current %s)\n",
1088 onoff(state
), onoff(cur_state
));
1091 /* XXX: the dsi pll is shared between MIPI DSI ports */
1092 void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1097 mutex_lock(&dev_priv
->sb_lock
);
1098 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1099 mutex_unlock(&dev_priv
->sb_lock
);
1101 cur_state
= val
& DSI_PLL_VCO_EN
;
1102 I915_STATE_WARN(cur_state
!= state
,
1103 "DSI PLL state assertion failure (expected %s, current %s)\n",
1104 onoff(state
), onoff(cur_state
));
1107 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1108 enum pipe pipe
, bool state
)
1111 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1114 if (HAS_DDI(dev_priv
)) {
1115 /* DDI does not have a specific FDI_TX register */
1116 u32 val
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1117 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1119 u32 val
= I915_READ(FDI_TX_CTL(pipe
));
1120 cur_state
= !!(val
& FDI_TX_ENABLE
);
1122 I915_STATE_WARN(cur_state
!= state
,
1123 "FDI TX state assertion failure (expected %s, current %s)\n",
1124 onoff(state
), onoff(cur_state
));
1126 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1127 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1129 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1130 enum pipe pipe
, bool state
)
1135 val
= I915_READ(FDI_RX_CTL(pipe
));
1136 cur_state
= !!(val
& FDI_RX_ENABLE
);
1137 I915_STATE_WARN(cur_state
!= state
,
1138 "FDI RX state assertion failure (expected %s, current %s)\n",
1139 onoff(state
), onoff(cur_state
));
1141 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1142 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1144 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1149 /* ILK FDI PLL is always enabled */
1150 if (IS_GEN5(dev_priv
))
1153 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1154 if (HAS_DDI(dev_priv
))
1157 val
= I915_READ(FDI_TX_CTL(pipe
));
1158 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1161 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1162 enum pipe pipe
, bool state
)
1167 val
= I915_READ(FDI_RX_CTL(pipe
));
1168 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1169 I915_STATE_WARN(cur_state
!= state
,
1170 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1171 onoff(state
), onoff(cur_state
));
1174 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1178 enum pipe panel_pipe
= PIPE_A
;
1181 if (WARN_ON(HAS_DDI(dev_priv
)))
1184 if (HAS_PCH_SPLIT(dev_priv
)) {
1187 pp_reg
= PP_CONTROL(0);
1188 port_sel
= I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK
;
1190 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1191 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1192 panel_pipe
= PIPE_B
;
1193 /* XXX: else fix for eDP */
1194 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
1195 /* presumably write lock depends on pipe, not port select */
1196 pp_reg
= PP_CONTROL(pipe
);
1199 pp_reg
= PP_CONTROL(0);
1200 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1201 panel_pipe
= PIPE_B
;
1204 val
= I915_READ(pp_reg
);
1205 if (!(val
& PANEL_POWER_ON
) ||
1206 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1209 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1210 "panel assertion failure, pipe %c regs locked\n",
1214 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1215 enum pipe pipe
, bool state
)
1219 if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
))
1220 cur_state
= I915_READ(CURCNTR(PIPE_A
)) & CURSOR_ENABLE
;
1222 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1224 I915_STATE_WARN(cur_state
!= state
,
1225 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1226 pipe_name(pipe
), onoff(state
), onoff(cur_state
));
1228 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1229 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1231 void assert_pipe(struct drm_i915_private
*dev_priv
,
1232 enum pipe pipe
, bool state
)
1235 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1237 enum intel_display_power_domain power_domain
;
1239 /* we keep both pipes enabled on 830 */
1240 if (IS_I830(dev_priv
))
1243 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
1244 if (intel_display_power_get_if_enabled(dev_priv
, power_domain
)) {
1245 u32 val
= I915_READ(PIPECONF(cpu_transcoder
));
1246 cur_state
= !!(val
& PIPECONF_ENABLE
);
1248 intel_display_power_put(dev_priv
, power_domain
);
1253 I915_STATE_WARN(cur_state
!= state
,
1254 "pipe %c assertion failure (expected %s, current %s)\n",
1255 pipe_name(pipe
), onoff(state
), onoff(cur_state
));
1258 static void assert_plane(struct drm_i915_private
*dev_priv
,
1259 enum plane plane
, bool state
)
1264 val
= I915_READ(DSPCNTR(plane
));
1265 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1266 I915_STATE_WARN(cur_state
!= state
,
1267 "plane %c assertion failure (expected %s, current %s)\n",
1268 plane_name(plane
), onoff(state
), onoff(cur_state
));
1271 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1272 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1274 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1279 /* Primary planes are fixed to pipes on gen4+ */
1280 if (INTEL_GEN(dev_priv
) >= 4) {
1281 u32 val
= I915_READ(DSPCNTR(pipe
));
1282 I915_STATE_WARN(val
& DISPLAY_PLANE_ENABLE
,
1283 "plane %c assertion failure, should be disabled but not\n",
1288 /* Need to check both planes against the pipe */
1289 for_each_pipe(dev_priv
, i
) {
1290 u32 val
= I915_READ(DSPCNTR(i
));
1291 enum pipe cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1292 DISPPLANE_SEL_PIPE_SHIFT
;
1293 I915_STATE_WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1294 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1295 plane_name(i
), pipe_name(pipe
));
1299 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1304 if (INTEL_GEN(dev_priv
) >= 9) {
1305 for_each_sprite(dev_priv
, pipe
, sprite
) {
1306 u32 val
= I915_READ(PLANE_CTL(pipe
, sprite
));
1307 I915_STATE_WARN(val
& PLANE_CTL_ENABLE
,
1308 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1309 sprite
, pipe_name(pipe
));
1311 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
1312 for_each_sprite(dev_priv
, pipe
, sprite
) {
1313 u32 val
= I915_READ(SPCNTR(pipe
, PLANE_SPRITE0
+ sprite
));
1314 I915_STATE_WARN(val
& SP_ENABLE
,
1315 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1316 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1318 } else if (INTEL_GEN(dev_priv
) >= 7) {
1319 u32 val
= I915_READ(SPRCTL(pipe
));
1320 I915_STATE_WARN(val
& SPRITE_ENABLE
,
1321 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1322 plane_name(pipe
), pipe_name(pipe
));
1323 } else if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
)) {
1324 u32 val
= I915_READ(DVSCNTR(pipe
));
1325 I915_STATE_WARN(val
& DVS_ENABLE
,
1326 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1327 plane_name(pipe
), pipe_name(pipe
));
1331 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1333 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1334 drm_crtc_vblank_put(crtc
);
1337 void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1343 val
= I915_READ(PCH_TRANSCONF(pipe
));
1344 enabled
= !!(val
& TRANS_ENABLE
);
1345 I915_STATE_WARN(enabled
,
1346 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1350 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1351 enum pipe pipe
, u32 port_sel
, u32 val
)
1353 if ((val
& DP_PORT_EN
) == 0)
1356 if (HAS_PCH_CPT(dev_priv
)) {
1357 u32 trans_dp_ctl
= I915_READ(TRANS_DP_CTL(pipe
));
1358 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1360 } else if (IS_CHERRYVIEW(dev_priv
)) {
1361 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1364 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1370 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1371 enum pipe pipe
, u32 val
)
1373 if ((val
& SDVO_ENABLE
) == 0)
1376 if (HAS_PCH_CPT(dev_priv
)) {
1377 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1379 } else if (IS_CHERRYVIEW(dev_priv
)) {
1380 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1383 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1389 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1390 enum pipe pipe
, u32 val
)
1392 if ((val
& LVDS_PORT_EN
) == 0)
1395 if (HAS_PCH_CPT(dev_priv
)) {
1396 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1399 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1405 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1406 enum pipe pipe
, u32 val
)
1408 if ((val
& ADPA_DAC_ENABLE
) == 0)
1410 if (HAS_PCH_CPT(dev_priv
)) {
1411 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1414 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1420 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1421 enum pipe pipe
, i915_reg_t reg
,
1424 u32 val
= I915_READ(reg
);
1425 I915_STATE_WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1426 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1427 i915_mmio_reg_offset(reg
), pipe_name(pipe
));
1429 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
) && (val
& DP_PORT_EN
) == 0
1430 && (val
& DP_PIPEB_SELECT
),
1431 "IBX PCH dp port still using transcoder B\n");
1434 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1435 enum pipe pipe
, i915_reg_t reg
)
1437 u32 val
= I915_READ(reg
);
1438 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1439 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1440 i915_mmio_reg_offset(reg
), pipe_name(pipe
));
1442 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
) && (val
& SDVO_ENABLE
) == 0
1443 && (val
& SDVO_PIPE_B_SELECT
),
1444 "IBX PCH hdmi port still using transcoder B\n");
1447 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1452 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1453 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1454 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1456 val
= I915_READ(PCH_ADPA
);
1457 I915_STATE_WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1458 "PCH VGA enabled on transcoder %c, should be disabled\n",
1461 val
= I915_READ(PCH_LVDS
);
1462 I915_STATE_WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1463 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1466 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1467 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1468 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1471 static void _vlv_enable_pll(struct intel_crtc
*crtc
,
1472 const struct intel_crtc_state
*pipe_config
)
1474 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1475 enum pipe pipe
= crtc
->pipe
;
1477 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1478 POSTING_READ(DPLL(pipe
));
1481 if (intel_wait_for_register(dev_priv
,
1486 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
1489 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1490 const struct intel_crtc_state
*pipe_config
)
1492 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1493 enum pipe pipe
= crtc
->pipe
;
1495 assert_pipe_disabled(dev_priv
, pipe
);
1497 /* PLL is protected by panel, make sure we can write it */
1498 assert_panel_unlocked(dev_priv
, pipe
);
1500 if (pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
)
1501 _vlv_enable_pll(crtc
, pipe_config
);
1503 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1504 POSTING_READ(DPLL_MD(pipe
));
1508 static void _chv_enable_pll(struct intel_crtc
*crtc
,
1509 const struct intel_crtc_state
*pipe_config
)
1511 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1512 enum pipe pipe
= crtc
->pipe
;
1513 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1516 mutex_lock(&dev_priv
->sb_lock
);
1518 /* Enable back the 10bit clock to display controller */
1519 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1520 tmp
|= DPIO_DCLKP_EN
;
1521 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1523 mutex_unlock(&dev_priv
->sb_lock
);
1526 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1531 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1533 /* Check PLL is locked */
1534 if (intel_wait_for_register(dev_priv
,
1535 DPLL(pipe
), DPLL_LOCK_VLV
, DPLL_LOCK_VLV
,
1537 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1540 static void chv_enable_pll(struct intel_crtc
*crtc
,
1541 const struct intel_crtc_state
*pipe_config
)
1543 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1544 enum pipe pipe
= crtc
->pipe
;
1546 assert_pipe_disabled(dev_priv
, pipe
);
1548 /* PLL is protected by panel, make sure we can write it */
1549 assert_panel_unlocked(dev_priv
, pipe
);
1551 if (pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
)
1552 _chv_enable_pll(crtc
, pipe_config
);
1554 if (pipe
!= PIPE_A
) {
1556 * WaPixelRepeatModeFixForC0:chv
1558 * DPLLCMD is AWOL. Use chicken bits to propagate
1559 * the value from DPLLBMD to either pipe B or C.
1561 I915_WRITE(CBR4_VLV
, CBR_DPLLBMD_PIPE(pipe
));
1562 I915_WRITE(DPLL_MD(PIPE_B
), pipe_config
->dpll_hw_state
.dpll_md
);
1563 I915_WRITE(CBR4_VLV
, 0);
1564 dev_priv
->chv_dpll_md
[pipe
] = pipe_config
->dpll_hw_state
.dpll_md
;
1567 * DPLLB VGA mode also seems to cause problems.
1568 * We should always have it disabled.
1570 WARN_ON((I915_READ(DPLL(PIPE_B
)) & DPLL_VGA_MODE_DIS
) == 0);
1572 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1573 POSTING_READ(DPLL_MD(pipe
));
1577 static int intel_num_dvo_pipes(struct drm_i915_private
*dev_priv
)
1579 struct intel_crtc
*crtc
;
1582 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
1583 count
+= crtc
->base
.state
->active
&&
1584 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_DVO
);
1590 static void i9xx_enable_pll(struct intel_crtc
*crtc
,
1591 const struct intel_crtc_state
*crtc_state
)
1593 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1594 i915_reg_t reg
= DPLL(crtc
->pipe
);
1595 u32 dpll
= crtc_state
->dpll_hw_state
.dpll
;
1598 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1600 /* PLL is protected by panel, make sure we can write it */
1601 if (IS_MOBILE(dev_priv
) && !IS_I830(dev_priv
))
1602 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1604 /* Enable DVO 2x clock on both PLLs if necessary */
1605 if (IS_I830(dev_priv
) && intel_num_dvo_pipes(dev_priv
) > 0) {
1607 * It appears to be important that we don't enable this
1608 * for the current pipe before otherwise configuring the
1609 * PLL. No idea how this should be handled if multiple
1610 * DVO outputs are enabled simultaneosly.
1612 dpll
|= DPLL_DVO_2X_MODE
;
1613 I915_WRITE(DPLL(!crtc
->pipe
),
1614 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1618 * Apparently we need to have VGA mode enabled prior to changing
1619 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1620 * dividers, even though the register value does change.
1624 I915_WRITE(reg
, dpll
);
1626 /* Wait for the clocks to stabilize. */
1630 if (INTEL_GEN(dev_priv
) >= 4) {
1631 I915_WRITE(DPLL_MD(crtc
->pipe
),
1632 crtc_state
->dpll_hw_state
.dpll_md
);
1634 /* The pixel multiplier can only be updated once the
1635 * DPLL is enabled and the clocks are stable.
1637 * So write it again.
1639 I915_WRITE(reg
, dpll
);
1642 /* We do this three times for luck */
1643 for (i
= 0; i
< 3; i
++) {
1644 I915_WRITE(reg
, dpll
);
1646 udelay(150); /* wait for warmup */
1650 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1652 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1653 enum pipe pipe
= crtc
->pipe
;
1655 /* Disable DVO 2x clock on both PLLs if necessary */
1656 if (IS_I830(dev_priv
) &&
1657 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_DVO
) &&
1658 !intel_num_dvo_pipes(dev_priv
)) {
1659 I915_WRITE(DPLL(PIPE_B
),
1660 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1661 I915_WRITE(DPLL(PIPE_A
),
1662 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1665 /* Don't disable pipe or pipe PLLs if needed */
1666 if (IS_I830(dev_priv
))
1669 /* Make sure the pipe isn't still relying on us */
1670 assert_pipe_disabled(dev_priv
, pipe
);
1672 I915_WRITE(DPLL(pipe
), DPLL_VGA_MODE_DIS
);
1673 POSTING_READ(DPLL(pipe
));
1676 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1680 /* Make sure the pipe isn't still relying on us */
1681 assert_pipe_disabled(dev_priv
, pipe
);
1683 val
= DPLL_INTEGRATED_REF_CLK_VLV
|
1684 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1686 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1688 I915_WRITE(DPLL(pipe
), val
);
1689 POSTING_READ(DPLL(pipe
));
1692 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1694 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1697 /* Make sure the pipe isn't still relying on us */
1698 assert_pipe_disabled(dev_priv
, pipe
);
1700 val
= DPLL_SSC_REF_CLK_CHV
|
1701 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1703 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1705 I915_WRITE(DPLL(pipe
), val
);
1706 POSTING_READ(DPLL(pipe
));
1708 mutex_lock(&dev_priv
->sb_lock
);
1710 /* Disable 10bit clock to display controller */
1711 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1712 val
&= ~DPIO_DCLKP_EN
;
1713 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1715 mutex_unlock(&dev_priv
->sb_lock
);
1718 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1719 struct intel_digital_port
*dport
,
1720 unsigned int expected_mask
)
1723 i915_reg_t dpll_reg
;
1725 switch (dport
->port
) {
1727 port_mask
= DPLL_PORTB_READY_MASK
;
1731 port_mask
= DPLL_PORTC_READY_MASK
;
1733 expected_mask
<<= 4;
1736 port_mask
= DPLL_PORTD_READY_MASK
;
1737 dpll_reg
= DPIO_PHY_STATUS
;
1743 if (intel_wait_for_register(dev_priv
,
1744 dpll_reg
, port_mask
, expected_mask
,
1746 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1747 port_name(dport
->port
), I915_READ(dpll_reg
) & port_mask
, expected_mask
);
1750 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1753 struct intel_crtc
*intel_crtc
= intel_get_crtc_for_pipe(dev_priv
,
1756 uint32_t val
, pipeconf_val
;
1758 /* Make sure PCH DPLL is enabled */
1759 assert_shared_dpll_enabled(dev_priv
, intel_crtc
->config
->shared_dpll
);
1761 /* FDI must be feeding us bits for PCH ports */
1762 assert_fdi_tx_enabled(dev_priv
, pipe
);
1763 assert_fdi_rx_enabled(dev_priv
, pipe
);
1765 if (HAS_PCH_CPT(dev_priv
)) {
1766 /* Workaround: Set the timing override bit before enabling the
1767 * pch transcoder. */
1768 reg
= TRANS_CHICKEN2(pipe
);
1769 val
= I915_READ(reg
);
1770 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1771 I915_WRITE(reg
, val
);
1774 reg
= PCH_TRANSCONF(pipe
);
1775 val
= I915_READ(reg
);
1776 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1778 if (HAS_PCH_IBX(dev_priv
)) {
1780 * Make the BPC in transcoder be consistent with
1781 * that in pipeconf reg. For HDMI we must use 8bpc
1782 * here for both 8bpc and 12bpc.
1784 val
&= ~PIPECONF_BPC_MASK
;
1785 if (intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_HDMI
))
1786 val
|= PIPECONF_8BPC
;
1788 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1791 val
&= ~TRANS_INTERLACE_MASK
;
1792 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1793 if (HAS_PCH_IBX(dev_priv
) &&
1794 intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_SDVO
))
1795 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1797 val
|= TRANS_INTERLACED
;
1799 val
|= TRANS_PROGRESSIVE
;
1801 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1802 if (intel_wait_for_register(dev_priv
,
1803 reg
, TRANS_STATE_ENABLE
, TRANS_STATE_ENABLE
,
1805 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1808 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1809 enum transcoder cpu_transcoder
)
1811 u32 val
, pipeconf_val
;
1813 /* FDI must be feeding us bits for PCH ports */
1814 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1815 assert_fdi_rx_enabled(dev_priv
, PIPE_A
);
1817 /* Workaround: set timing override bit. */
1818 val
= I915_READ(TRANS_CHICKEN2(PIPE_A
));
1819 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1820 I915_WRITE(TRANS_CHICKEN2(PIPE_A
), val
);
1823 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1825 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1826 PIPECONF_INTERLACED_ILK
)
1827 val
|= TRANS_INTERLACED
;
1829 val
|= TRANS_PROGRESSIVE
;
1831 I915_WRITE(LPT_TRANSCONF
, val
);
1832 if (intel_wait_for_register(dev_priv
,
1837 DRM_ERROR("Failed to enable PCH transcoder\n");
1840 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1846 /* FDI relies on the transcoder */
1847 assert_fdi_tx_disabled(dev_priv
, pipe
);
1848 assert_fdi_rx_disabled(dev_priv
, pipe
);
1850 /* Ports must be off as well */
1851 assert_pch_ports_disabled(dev_priv
, pipe
);
1853 reg
= PCH_TRANSCONF(pipe
);
1854 val
= I915_READ(reg
);
1855 val
&= ~TRANS_ENABLE
;
1856 I915_WRITE(reg
, val
);
1857 /* wait for PCH transcoder off, transcoder state */
1858 if (intel_wait_for_register(dev_priv
,
1859 reg
, TRANS_STATE_ENABLE
, 0,
1861 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1863 if (HAS_PCH_CPT(dev_priv
)) {
1864 /* Workaround: Clear the timing override chicken bit again. */
1865 reg
= TRANS_CHICKEN2(pipe
);
1866 val
= I915_READ(reg
);
1867 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1868 I915_WRITE(reg
, val
);
1872 void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1876 val
= I915_READ(LPT_TRANSCONF
);
1877 val
&= ~TRANS_ENABLE
;
1878 I915_WRITE(LPT_TRANSCONF
, val
);
1879 /* wait for PCH transcoder off, transcoder state */
1880 if (intel_wait_for_register(dev_priv
,
1881 LPT_TRANSCONF
, TRANS_STATE_ENABLE
, 0,
1883 DRM_ERROR("Failed to disable PCH transcoder\n");
1885 /* Workaround: clear timing override bit. */
1886 val
= I915_READ(TRANS_CHICKEN2(PIPE_A
));
1887 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1888 I915_WRITE(TRANS_CHICKEN2(PIPE_A
), val
);
1891 enum pipe
intel_crtc_pch_transcoder(struct intel_crtc
*crtc
)
1893 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1895 WARN_ON(!crtc
->config
->has_pch_encoder
);
1897 if (HAS_PCH_LPT(dev_priv
))
1904 * intel_enable_pipe - enable a pipe, asserting requirements
1905 * @crtc: crtc responsible for the pipe
1907 * Enable @crtc's pipe, making sure that various hardware specific requirements
1908 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1910 static void intel_enable_pipe(struct intel_crtc
*crtc
)
1912 struct drm_device
*dev
= crtc
->base
.dev
;
1913 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1914 enum pipe pipe
= crtc
->pipe
;
1915 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1919 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe
));
1921 assert_planes_disabled(dev_priv
, pipe
);
1922 assert_cursor_disabled(dev_priv
, pipe
);
1923 assert_sprites_disabled(dev_priv
, pipe
);
1926 * A pipe without a PLL won't actually be able to drive bits from
1927 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1930 if (HAS_GMCH_DISPLAY(dev_priv
)) {
1931 if (intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_DSI
))
1932 assert_dsi_pll_enabled(dev_priv
);
1934 assert_pll_enabled(dev_priv
, pipe
);
1936 if (crtc
->config
->has_pch_encoder
) {
1937 /* if driving the PCH, we need FDI enabled */
1938 assert_fdi_rx_pll_enabled(dev_priv
,
1939 intel_crtc_pch_transcoder(crtc
));
1940 assert_fdi_tx_pll_enabled(dev_priv
,
1941 (enum pipe
) cpu_transcoder
);
1943 /* FIXME: assert CPU port conditions for SNB+ */
1946 reg
= PIPECONF(cpu_transcoder
);
1947 val
= I915_READ(reg
);
1948 if (val
& PIPECONF_ENABLE
) {
1949 /* we keep both pipes enabled on 830 */
1950 WARN_ON(!IS_I830(dev_priv
));
1954 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1958 * Until the pipe starts PIPEDSL reads will return a stale value,
1959 * which causes an apparent vblank timestamp jump when PIPEDSL
1960 * resets to its proper value. That also messes up the frame count
1961 * when it's derived from the timestamps. So let's wait for the
1962 * pipe to start properly before we call drm_crtc_vblank_on()
1964 if (dev
->max_vblank_count
== 0)
1965 intel_wait_for_pipe_scanline_moving(crtc
);
1969 * intel_disable_pipe - disable a pipe, asserting requirements
1970 * @crtc: crtc whose pipes is to be disabled
1972 * Disable the pipe of @crtc, making sure that various hardware
1973 * specific requirements are met, if applicable, e.g. plane
1974 * disabled, panel fitter off, etc.
1976 * Will wait until the pipe has shut down before returning.
1978 static void intel_disable_pipe(struct intel_crtc
*crtc
)
1980 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1981 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1982 enum pipe pipe
= crtc
->pipe
;
1986 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe
));
1989 * Make sure planes won't keep trying to pump pixels to us,
1990 * or we might hang the display.
1992 assert_planes_disabled(dev_priv
, pipe
);
1993 assert_cursor_disabled(dev_priv
, pipe
);
1994 assert_sprites_disabled(dev_priv
, pipe
);
1996 reg
= PIPECONF(cpu_transcoder
);
1997 val
= I915_READ(reg
);
1998 if ((val
& PIPECONF_ENABLE
) == 0)
2002 * Double wide has implications for planes
2003 * so best keep it disabled when not needed.
2005 if (crtc
->config
->double_wide
)
2006 val
&= ~PIPECONF_DOUBLE_WIDE
;
2008 /* Don't disable pipe or pipe PLLs if needed */
2009 if (!IS_I830(dev_priv
))
2010 val
&= ~PIPECONF_ENABLE
;
2012 I915_WRITE(reg
, val
);
2013 if ((val
& PIPECONF_ENABLE
) == 0)
2014 intel_wait_for_pipe_off(crtc
);
2017 static unsigned int intel_tile_size(const struct drm_i915_private
*dev_priv
)
2019 return IS_GEN2(dev_priv
) ? 2048 : 4096;
2023 intel_tile_width_bytes(const struct drm_framebuffer
*fb
, int plane
)
2025 struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
2026 unsigned int cpp
= fb
->format
->cpp
[plane
];
2028 switch (fb
->modifier
) {
2029 case DRM_FORMAT_MOD_LINEAR
:
2031 case I915_FORMAT_MOD_X_TILED
:
2032 if (IS_GEN2(dev_priv
))
2036 case I915_FORMAT_MOD_Y_TILED_CCS
:
2040 case I915_FORMAT_MOD_Y_TILED
:
2041 if (IS_GEN2(dev_priv
) || HAS_128_BYTE_Y_TILING(dev_priv
))
2045 case I915_FORMAT_MOD_Yf_TILED_CCS
:
2049 case I915_FORMAT_MOD_Yf_TILED
:
2065 MISSING_CASE(fb
->modifier
);
2071 intel_tile_height(const struct drm_framebuffer
*fb
, int plane
)
2073 if (fb
->modifier
== DRM_FORMAT_MOD_LINEAR
)
2076 return intel_tile_size(to_i915(fb
->dev
)) /
2077 intel_tile_width_bytes(fb
, plane
);
2080 /* Return the tile dimensions in pixel units */
2081 static void intel_tile_dims(const struct drm_framebuffer
*fb
, int plane
,
2082 unsigned int *tile_width
,
2083 unsigned int *tile_height
)
2085 unsigned int tile_width_bytes
= intel_tile_width_bytes(fb
, plane
);
2086 unsigned int cpp
= fb
->format
->cpp
[plane
];
2088 *tile_width
= tile_width_bytes
/ cpp
;
2089 *tile_height
= intel_tile_size(to_i915(fb
->dev
)) / tile_width_bytes
;
2093 intel_fb_align_height(const struct drm_framebuffer
*fb
,
2094 int plane
, unsigned int height
)
2096 unsigned int tile_height
= intel_tile_height(fb
, plane
);
2098 return ALIGN(height
, tile_height
);
2101 unsigned int intel_rotation_info_size(const struct intel_rotation_info
*rot_info
)
2103 unsigned int size
= 0;
2106 for (i
= 0 ; i
< ARRAY_SIZE(rot_info
->plane
); i
++)
2107 size
+= rot_info
->plane
[i
].width
* rot_info
->plane
[i
].height
;
2113 intel_fill_fb_ggtt_view(struct i915_ggtt_view
*view
,
2114 const struct drm_framebuffer
*fb
,
2115 unsigned int rotation
)
2117 view
->type
= I915_GGTT_VIEW_NORMAL
;
2118 if (drm_rotation_90_or_270(rotation
)) {
2119 view
->type
= I915_GGTT_VIEW_ROTATED
;
2120 view
->rotated
= to_intel_framebuffer(fb
)->rot_info
;
2124 static unsigned int intel_cursor_alignment(const struct drm_i915_private
*dev_priv
)
2126 if (IS_I830(dev_priv
))
2128 else if (IS_I85X(dev_priv
))
2130 else if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
))
2136 static unsigned int intel_linear_alignment(const struct drm_i915_private
*dev_priv
)
2138 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2140 else if (IS_I965G(dev_priv
) || IS_I965GM(dev_priv
) ||
2141 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2143 else if (INTEL_INFO(dev_priv
)->gen
>= 4)
2149 static unsigned int intel_surf_alignment(const struct drm_framebuffer
*fb
,
2152 struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
2154 /* AUX_DIST needs only 4K alignment */
2158 switch (fb
->modifier
) {
2159 case DRM_FORMAT_MOD_LINEAR
:
2160 return intel_linear_alignment(dev_priv
);
2161 case I915_FORMAT_MOD_X_TILED
:
2162 if (INTEL_GEN(dev_priv
) >= 9)
2165 case I915_FORMAT_MOD_Y_TILED_CCS
:
2166 case I915_FORMAT_MOD_Yf_TILED_CCS
:
2167 case I915_FORMAT_MOD_Y_TILED
:
2168 case I915_FORMAT_MOD_Yf_TILED
:
2169 return 1 * 1024 * 1024;
2171 MISSING_CASE(fb
->modifier
);
2177 intel_pin_and_fence_fb_obj(struct drm_framebuffer
*fb
, unsigned int rotation
)
2179 struct drm_device
*dev
= fb
->dev
;
2180 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2181 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2182 struct i915_ggtt_view view
;
2183 struct i915_vma
*vma
;
2186 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2188 alignment
= intel_surf_alignment(fb
, 0);
2190 intel_fill_fb_ggtt_view(&view
, fb
, rotation
);
2192 /* Note that the w/a also requires 64 PTE of padding following the
2193 * bo. We currently fill all unused PTE with the shadow page and so
2194 * we should always have valid PTE following the scanout preventing
2197 if (intel_scanout_needs_vtd_wa(dev_priv
) && alignment
< 256 * 1024)
2198 alignment
= 256 * 1024;
2201 * Global gtt pte registers are special registers which actually forward
2202 * writes to a chunk of system memory. Which means that there is no risk
2203 * that the register values disappear as soon as we call
2204 * intel_runtime_pm_put(), so it is correct to wrap only the
2205 * pin/unpin/fence and not more.
2207 intel_runtime_pm_get(dev_priv
);
2209 atomic_inc(&dev_priv
->gpu_error
.pending_fb_pin
);
2211 vma
= i915_gem_object_pin_to_display_plane(obj
, alignment
, &view
);
2215 if (i915_vma_is_map_and_fenceable(vma
)) {
2216 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2217 * fence, whereas 965+ only requires a fence if using
2218 * framebuffer compression. For simplicity, we always, when
2219 * possible, install a fence as the cost is not that onerous.
2221 * If we fail to fence the tiled scanout, then either the
2222 * modeset will reject the change (which is highly unlikely as
2223 * the affected systems, all but one, do not have unmappable
2224 * space) or we will not be able to enable full powersaving
2225 * techniques (also likely not to apply due to various limits
2226 * FBC and the like impose on the size of the buffer, which
2227 * presumably we violated anyway with this unmappable buffer).
2228 * Anyway, it is presumably better to stumble onwards with
2229 * something and try to run the system in a "less than optimal"
2230 * mode that matches the user configuration.
2232 i915_vma_pin_fence(vma
);
2237 atomic_dec(&dev_priv
->gpu_error
.pending_fb_pin
);
2239 intel_runtime_pm_put(dev_priv
);
2243 void intel_unpin_fb_vma(struct i915_vma
*vma
)
2245 lockdep_assert_held(&vma
->vm
->i915
->drm
.struct_mutex
);
2247 i915_vma_unpin_fence(vma
);
2248 i915_gem_object_unpin_from_display_plane(vma
);
2252 static int intel_fb_pitch(const struct drm_framebuffer
*fb
, int plane
,
2253 unsigned int rotation
)
2255 if (drm_rotation_90_or_270(rotation
))
2256 return to_intel_framebuffer(fb
)->rotated
[plane
].pitch
;
2258 return fb
->pitches
[plane
];
2262 * Convert the x/y offsets into a linear offset.
2263 * Only valid with 0/180 degree rotation, which is fine since linear
2264 * offset is only used with linear buffers on pre-hsw and tiled buffers
2265 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2267 u32
intel_fb_xy_to_linear(int x
, int y
,
2268 const struct intel_plane_state
*state
,
2271 const struct drm_framebuffer
*fb
= state
->base
.fb
;
2272 unsigned int cpp
= fb
->format
->cpp
[plane
];
2273 unsigned int pitch
= fb
->pitches
[plane
];
2275 return y
* pitch
+ x
* cpp
;
2279 * Add the x/y offsets derived from fb->offsets[] to the user
2280 * specified plane src x/y offsets. The resulting x/y offsets
2281 * specify the start of scanout from the beginning of the gtt mapping.
2283 void intel_add_fb_offsets(int *x
, int *y
,
2284 const struct intel_plane_state
*state
,
2288 const struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(state
->base
.fb
);
2289 unsigned int rotation
= state
->base
.rotation
;
2291 if (drm_rotation_90_or_270(rotation
)) {
2292 *x
+= intel_fb
->rotated
[plane
].x
;
2293 *y
+= intel_fb
->rotated
[plane
].y
;
2295 *x
+= intel_fb
->normal
[plane
].x
;
2296 *y
+= intel_fb
->normal
[plane
].y
;
2300 static u32
__intel_adjust_tile_offset(int *x
, int *y
,
2301 unsigned int tile_width
,
2302 unsigned int tile_height
,
2303 unsigned int tile_size
,
2304 unsigned int pitch_tiles
,
2308 unsigned int pitch_pixels
= pitch_tiles
* tile_width
;
2311 WARN_ON(old_offset
& (tile_size
- 1));
2312 WARN_ON(new_offset
& (tile_size
- 1));
2313 WARN_ON(new_offset
> old_offset
);
2315 tiles
= (old_offset
- new_offset
) / tile_size
;
2317 *y
+= tiles
/ pitch_tiles
* tile_height
;
2318 *x
+= tiles
% pitch_tiles
* tile_width
;
2320 /* minimize x in case it got needlessly big */
2321 *y
+= *x
/ pitch_pixels
* tile_height
;
2327 static u32
_intel_adjust_tile_offset(int *x
, int *y
,
2328 const struct drm_framebuffer
*fb
, int plane
,
2329 unsigned int rotation
,
2330 u32 old_offset
, u32 new_offset
)
2332 const struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
2333 unsigned int cpp
= fb
->format
->cpp
[plane
];
2334 unsigned int pitch
= intel_fb_pitch(fb
, plane
, rotation
);
2336 WARN_ON(new_offset
> old_offset
);
2338 if (fb
->modifier
!= DRM_FORMAT_MOD_LINEAR
) {
2339 unsigned int tile_size
, tile_width
, tile_height
;
2340 unsigned int pitch_tiles
;
2342 tile_size
= intel_tile_size(dev_priv
);
2343 intel_tile_dims(fb
, plane
, &tile_width
, &tile_height
);
2345 if (drm_rotation_90_or_270(rotation
)) {
2346 pitch_tiles
= pitch
/ tile_height
;
2347 swap(tile_width
, tile_height
);
2349 pitch_tiles
= pitch
/ (tile_width
* cpp
);
2352 __intel_adjust_tile_offset(x
, y
, tile_width
, tile_height
,
2353 tile_size
, pitch_tiles
,
2354 old_offset
, new_offset
);
2356 old_offset
+= *y
* pitch
+ *x
* cpp
;
2358 *y
= (old_offset
- new_offset
) / pitch
;
2359 *x
= ((old_offset
- new_offset
) - *y
* pitch
) / cpp
;
2366 * Adjust the tile offset by moving the difference into
2369 static u32
intel_adjust_tile_offset(int *x
, int *y
,
2370 const struct intel_plane_state
*state
, int plane
,
2371 u32 old_offset
, u32 new_offset
)
2373 return _intel_adjust_tile_offset(x
, y
, state
->base
.fb
, plane
,
2374 state
->base
.rotation
,
2375 old_offset
, new_offset
);
2379 * Computes the linear offset to the base tile and adjusts
2380 * x, y. bytes per pixel is assumed to be a power-of-two.
2382 * In the 90/270 rotated case, x and y are assumed
2383 * to be already rotated to match the rotated GTT view, and
2384 * pitch is the tile_height aligned framebuffer height.
2386 * This function is used when computing the derived information
2387 * under intel_framebuffer, so using any of that information
2388 * here is not allowed. Anything under drm_framebuffer can be
2389 * used. This is why the user has to pass in the pitch since it
2390 * is specified in the rotated orientation.
2392 static u32
_intel_compute_tile_offset(const struct drm_i915_private
*dev_priv
,
2394 const struct drm_framebuffer
*fb
, int plane
,
2396 unsigned int rotation
,
2399 uint64_t fb_modifier
= fb
->modifier
;
2400 unsigned int cpp
= fb
->format
->cpp
[plane
];
2401 u32 offset
, offset_aligned
;
2406 if (fb_modifier
!= DRM_FORMAT_MOD_LINEAR
) {
2407 unsigned int tile_size
, tile_width
, tile_height
;
2408 unsigned int tile_rows
, tiles
, pitch_tiles
;
2410 tile_size
= intel_tile_size(dev_priv
);
2411 intel_tile_dims(fb
, plane
, &tile_width
, &tile_height
);
2413 if (drm_rotation_90_or_270(rotation
)) {
2414 pitch_tiles
= pitch
/ tile_height
;
2415 swap(tile_width
, tile_height
);
2417 pitch_tiles
= pitch
/ (tile_width
* cpp
);
2420 tile_rows
= *y
/ tile_height
;
2423 tiles
= *x
/ tile_width
;
2426 offset
= (tile_rows
* pitch_tiles
+ tiles
) * tile_size
;
2427 offset_aligned
= offset
& ~alignment
;
2429 __intel_adjust_tile_offset(x
, y
, tile_width
, tile_height
,
2430 tile_size
, pitch_tiles
,
2431 offset
, offset_aligned
);
2433 offset
= *y
* pitch
+ *x
* cpp
;
2434 offset_aligned
= offset
& ~alignment
;
2436 *y
= (offset
& alignment
) / pitch
;
2437 *x
= ((offset
& alignment
) - *y
* pitch
) / cpp
;
2440 return offset_aligned
;
2443 u32
intel_compute_tile_offset(int *x
, int *y
,
2444 const struct intel_plane_state
*state
,
2447 struct intel_plane
*intel_plane
= to_intel_plane(state
->base
.plane
);
2448 struct drm_i915_private
*dev_priv
= to_i915(intel_plane
->base
.dev
);
2449 const struct drm_framebuffer
*fb
= state
->base
.fb
;
2450 unsigned int rotation
= state
->base
.rotation
;
2451 int pitch
= intel_fb_pitch(fb
, plane
, rotation
);
2454 if (intel_plane
->id
== PLANE_CURSOR
)
2455 alignment
= intel_cursor_alignment(dev_priv
);
2457 alignment
= intel_surf_alignment(fb
, plane
);
2459 return _intel_compute_tile_offset(dev_priv
, x
, y
, fb
, plane
, pitch
,
2460 rotation
, alignment
);
2463 /* Convert the fb->offset[] into x/y offsets */
2464 static int intel_fb_offset_to_xy(int *x
, int *y
,
2465 const struct drm_framebuffer
*fb
, int plane
)
2467 struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
2469 if (fb
->modifier
!= DRM_FORMAT_MOD_LINEAR
&&
2470 fb
->offsets
[plane
] % intel_tile_size(dev_priv
))
2476 _intel_adjust_tile_offset(x
, y
,
2477 fb
, plane
, DRM_MODE_ROTATE_0
,
2478 fb
->offsets
[plane
], 0);
2483 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier
)
2485 switch (fb_modifier
) {
2486 case I915_FORMAT_MOD_X_TILED
:
2487 return I915_TILING_X
;
2488 case I915_FORMAT_MOD_Y_TILED
:
2489 case I915_FORMAT_MOD_Y_TILED_CCS
:
2490 return I915_TILING_Y
;
2492 return I915_TILING_NONE
;
2496 static const struct drm_format_info ccs_formats
[] = {
2497 { .format
= DRM_FORMAT_XRGB8888
, .depth
= 24, .num_planes
= 2, .cpp
= { 4, 1, }, .hsub
= 8, .vsub
= 16, },
2498 { .format
= DRM_FORMAT_XBGR8888
, .depth
= 24, .num_planes
= 2, .cpp
= { 4, 1, }, .hsub
= 8, .vsub
= 16, },
2499 { .format
= DRM_FORMAT_ARGB8888
, .depth
= 32, .num_planes
= 2, .cpp
= { 4, 1, }, .hsub
= 8, .vsub
= 16, },
2500 { .format
= DRM_FORMAT_ABGR8888
, .depth
= 32, .num_planes
= 2, .cpp
= { 4, 1, }, .hsub
= 8, .vsub
= 16, },
2503 static const struct drm_format_info
*
2504 lookup_format_info(const struct drm_format_info formats
[],
2505 int num_formats
, u32 format
)
2509 for (i
= 0; i
< num_formats
; i
++) {
2510 if (formats
[i
].format
== format
)
2517 static const struct drm_format_info
*
2518 intel_get_format_info(const struct drm_mode_fb_cmd2
*cmd
)
2520 switch (cmd
->modifier
[0]) {
2521 case I915_FORMAT_MOD_Y_TILED_CCS
:
2522 case I915_FORMAT_MOD_Yf_TILED_CCS
:
2523 return lookup_format_info(ccs_formats
,
2524 ARRAY_SIZE(ccs_formats
),
2532 intel_fill_fb_info(struct drm_i915_private
*dev_priv
,
2533 struct drm_framebuffer
*fb
)
2535 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
2536 struct intel_rotation_info
*rot_info
= &intel_fb
->rot_info
;
2537 u32 gtt_offset_rotated
= 0;
2538 unsigned int max_size
= 0;
2539 int i
, num_planes
= fb
->format
->num_planes
;
2540 unsigned int tile_size
= intel_tile_size(dev_priv
);
2542 for (i
= 0; i
< num_planes
; i
++) {
2543 unsigned int width
, height
;
2544 unsigned int cpp
, size
;
2549 cpp
= fb
->format
->cpp
[i
];
2550 width
= drm_framebuffer_plane_width(fb
->width
, fb
, i
);
2551 height
= drm_framebuffer_plane_height(fb
->height
, fb
, i
);
2553 ret
= intel_fb_offset_to_xy(&x
, &y
, fb
, i
);
2555 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2560 if ((fb
->modifier
== I915_FORMAT_MOD_Y_TILED_CCS
||
2561 fb
->modifier
== I915_FORMAT_MOD_Yf_TILED_CCS
) && i
== 1) {
2562 int hsub
= fb
->format
->hsub
;
2563 int vsub
= fb
->format
->vsub
;
2564 int tile_width
, tile_height
;
2568 intel_tile_dims(fb
, i
, &tile_width
, &tile_height
);
2570 tile_height
*= vsub
;
2572 ccs_x
= (x
* hsub
) % tile_width
;
2573 ccs_y
= (y
* vsub
) % tile_height
;
2574 main_x
= intel_fb
->normal
[0].x
% tile_width
;
2575 main_y
= intel_fb
->normal
[0].y
% tile_height
;
2578 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2579 * x/y offsets must match between CCS and the main surface.
2581 if (main_x
!= ccs_x
|| main_y
!= ccs_y
) {
2582 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2585 intel_fb
->normal
[0].x
,
2586 intel_fb
->normal
[0].y
,
2593 * The fence (if used) is aligned to the start of the object
2594 * so having the framebuffer wrap around across the edge of the
2595 * fenced region doesn't really work. We have no API to configure
2596 * the fence start offset within the object (nor could we probably
2597 * on gen2/3). So it's just easier if we just require that the
2598 * fb layout agrees with the fence layout. We already check that the
2599 * fb stride matches the fence stride elsewhere.
2601 if (i
== 0 && i915_gem_object_is_tiled(intel_fb
->obj
) &&
2602 (x
+ width
) * cpp
> fb
->pitches
[i
]) {
2603 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2609 * First pixel of the framebuffer from
2610 * the start of the normal gtt mapping.
2612 intel_fb
->normal
[i
].x
= x
;
2613 intel_fb
->normal
[i
].y
= y
;
2615 offset
= _intel_compute_tile_offset(dev_priv
, &x
, &y
,
2616 fb
, i
, fb
->pitches
[i
],
2617 DRM_MODE_ROTATE_0
, tile_size
);
2618 offset
/= tile_size
;
2620 if (fb
->modifier
!= DRM_FORMAT_MOD_LINEAR
) {
2621 unsigned int tile_width
, tile_height
;
2622 unsigned int pitch_tiles
;
2625 intel_tile_dims(fb
, i
, &tile_width
, &tile_height
);
2627 rot_info
->plane
[i
].offset
= offset
;
2628 rot_info
->plane
[i
].stride
= DIV_ROUND_UP(fb
->pitches
[i
], tile_width
* cpp
);
2629 rot_info
->plane
[i
].width
= DIV_ROUND_UP(x
+ width
, tile_width
);
2630 rot_info
->plane
[i
].height
= DIV_ROUND_UP(y
+ height
, tile_height
);
2632 intel_fb
->rotated
[i
].pitch
=
2633 rot_info
->plane
[i
].height
* tile_height
;
2635 /* how many tiles does this plane need */
2636 size
= rot_info
->plane
[i
].stride
* rot_info
->plane
[i
].height
;
2638 * If the plane isn't horizontally tile aligned,
2639 * we need one more tile.
2644 /* rotate the x/y offsets to match the GTT view */
2650 rot_info
->plane
[i
].width
* tile_width
,
2651 rot_info
->plane
[i
].height
* tile_height
,
2652 DRM_MODE_ROTATE_270
);
2656 /* rotate the tile dimensions to match the GTT view */
2657 pitch_tiles
= intel_fb
->rotated
[i
].pitch
/ tile_height
;
2658 swap(tile_width
, tile_height
);
2661 * We only keep the x/y offsets, so push all of the
2662 * gtt offset into the x/y offsets.
2664 __intel_adjust_tile_offset(&x
, &y
,
2665 tile_width
, tile_height
,
2666 tile_size
, pitch_tiles
,
2667 gtt_offset_rotated
* tile_size
, 0);
2669 gtt_offset_rotated
+= rot_info
->plane
[i
].width
* rot_info
->plane
[i
].height
;
2672 * First pixel of the framebuffer from
2673 * the start of the rotated gtt mapping.
2675 intel_fb
->rotated
[i
].x
= x
;
2676 intel_fb
->rotated
[i
].y
= y
;
2678 size
= DIV_ROUND_UP((y
+ height
) * fb
->pitches
[i
] +
2679 x
* cpp
, tile_size
);
2682 /* how many tiles in total needed in the bo */
2683 max_size
= max(max_size
, offset
+ size
);
2686 if (max_size
* tile_size
> intel_fb
->obj
->base
.size
) {
2687 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2688 max_size
* tile_size
, intel_fb
->obj
->base
.size
);
2695 static int i9xx_format_to_fourcc(int format
)
2698 case DISPPLANE_8BPP
:
2699 return DRM_FORMAT_C8
;
2700 case DISPPLANE_BGRX555
:
2701 return DRM_FORMAT_XRGB1555
;
2702 case DISPPLANE_BGRX565
:
2703 return DRM_FORMAT_RGB565
;
2705 case DISPPLANE_BGRX888
:
2706 return DRM_FORMAT_XRGB8888
;
2707 case DISPPLANE_RGBX888
:
2708 return DRM_FORMAT_XBGR8888
;
2709 case DISPPLANE_BGRX101010
:
2710 return DRM_FORMAT_XRGB2101010
;
2711 case DISPPLANE_RGBX101010
:
2712 return DRM_FORMAT_XBGR2101010
;
2716 static int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
)
2719 case PLANE_CTL_FORMAT_RGB_565
:
2720 return DRM_FORMAT_RGB565
;
2722 case PLANE_CTL_FORMAT_XRGB_8888
:
2725 return DRM_FORMAT_ABGR8888
;
2727 return DRM_FORMAT_XBGR8888
;
2730 return DRM_FORMAT_ARGB8888
;
2732 return DRM_FORMAT_XRGB8888
;
2734 case PLANE_CTL_FORMAT_XRGB_2101010
:
2736 return DRM_FORMAT_XBGR2101010
;
2738 return DRM_FORMAT_XRGB2101010
;
2743 intel_alloc_initial_plane_obj(struct intel_crtc
*crtc
,
2744 struct intel_initial_plane_config
*plane_config
)
2746 struct drm_device
*dev
= crtc
->base
.dev
;
2747 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2748 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2749 struct drm_i915_gem_object
*obj
= NULL
;
2750 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2751 struct drm_framebuffer
*fb
= &plane_config
->fb
->base
;
2752 u32 base_aligned
= round_down(plane_config
->base
, PAGE_SIZE
);
2753 u32 size_aligned
= round_up(plane_config
->base
+ plane_config
->size
,
2756 size_aligned
-= base_aligned
;
2758 if (plane_config
->size
== 0)
2761 /* If the FB is too big, just don't use it since fbdev is not very
2762 * important and we should probably use that space with FBC or other
2764 if (size_aligned
* 2 > ggtt
->stolen_usable_size
)
2767 mutex_lock(&dev
->struct_mutex
);
2768 obj
= i915_gem_object_create_stolen_for_preallocated(dev_priv
,
2772 mutex_unlock(&dev
->struct_mutex
);
2776 if (plane_config
->tiling
== I915_TILING_X
)
2777 obj
->tiling_and_stride
= fb
->pitches
[0] | I915_TILING_X
;
2779 mode_cmd
.pixel_format
= fb
->format
->format
;
2780 mode_cmd
.width
= fb
->width
;
2781 mode_cmd
.height
= fb
->height
;
2782 mode_cmd
.pitches
[0] = fb
->pitches
[0];
2783 mode_cmd
.modifier
[0] = fb
->modifier
;
2784 mode_cmd
.flags
= DRM_MODE_FB_MODIFIERS
;
2786 if (intel_framebuffer_init(to_intel_framebuffer(fb
), obj
, &mode_cmd
)) {
2787 DRM_DEBUG_KMS("intel fb init failed\n");
2792 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj
);
2796 i915_gem_object_put(obj
);
2801 intel_set_plane_visible(struct intel_crtc_state
*crtc_state
,
2802 struct intel_plane_state
*plane_state
,
2805 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
2807 plane_state
->base
.visible
= visible
;
2809 /* FIXME pre-g4x don't work like this */
2811 crtc_state
->base
.plane_mask
|= BIT(drm_plane_index(&plane
->base
));
2812 crtc_state
->active_planes
|= BIT(plane
->id
);
2814 crtc_state
->base
.plane_mask
&= ~BIT(drm_plane_index(&plane
->base
));
2815 crtc_state
->active_planes
&= ~BIT(plane
->id
);
2818 DRM_DEBUG_KMS("%s active planes 0x%x\n",
2819 crtc_state
->base
.crtc
->name
,
2820 crtc_state
->active_planes
);
2824 intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc
,
2825 struct intel_initial_plane_config
*plane_config
)
2827 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2828 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2830 struct drm_i915_gem_object
*obj
;
2831 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
2832 struct drm_plane_state
*plane_state
= primary
->state
;
2833 struct drm_crtc_state
*crtc_state
= intel_crtc
->base
.state
;
2834 struct intel_plane
*intel_plane
= to_intel_plane(primary
);
2835 struct intel_plane_state
*intel_state
=
2836 to_intel_plane_state(plane_state
);
2837 struct drm_framebuffer
*fb
;
2839 if (!plane_config
->fb
)
2842 if (intel_alloc_initial_plane_obj(intel_crtc
, plane_config
)) {
2843 fb
= &plane_config
->fb
->base
;
2847 kfree(plane_config
->fb
);
2850 * Failed to alloc the obj, check to see if we should share
2851 * an fb with another CRTC instead
2853 for_each_crtc(dev
, c
) {
2854 struct intel_plane_state
*state
;
2856 if (c
== &intel_crtc
->base
)
2859 if (!to_intel_crtc(c
)->active
)
2862 state
= to_intel_plane_state(c
->primary
->state
);
2866 if (intel_plane_ggtt_offset(state
) == plane_config
->base
) {
2867 fb
= c
->primary
->fb
;
2868 drm_framebuffer_get(fb
);
2874 * We've failed to reconstruct the BIOS FB. Current display state
2875 * indicates that the primary plane is visible, but has a NULL FB,
2876 * which will lead to problems later if we don't fix it up. The
2877 * simplest solution is to just disable the primary plane now and
2878 * pretend the BIOS never had it enabled.
2880 intel_set_plane_visible(to_intel_crtc_state(crtc_state
),
2881 to_intel_plane_state(plane_state
),
2883 intel_pre_disable_primary_noatomic(&intel_crtc
->base
);
2884 trace_intel_disable_plane(primary
, intel_crtc
);
2885 intel_plane
->disable_plane(intel_plane
, intel_crtc
);
2890 mutex_lock(&dev
->struct_mutex
);
2892 intel_pin_and_fence_fb_obj(fb
, primary
->state
->rotation
);
2893 mutex_unlock(&dev
->struct_mutex
);
2894 if (IS_ERR(intel_state
->vma
)) {
2895 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2896 intel_crtc
->pipe
, PTR_ERR(intel_state
->vma
));
2898 intel_state
->vma
= NULL
;
2899 drm_framebuffer_put(fb
);
2903 plane_state
->src_x
= 0;
2904 plane_state
->src_y
= 0;
2905 plane_state
->src_w
= fb
->width
<< 16;
2906 plane_state
->src_h
= fb
->height
<< 16;
2908 plane_state
->crtc_x
= 0;
2909 plane_state
->crtc_y
= 0;
2910 plane_state
->crtc_w
= fb
->width
;
2911 plane_state
->crtc_h
= fb
->height
;
2913 intel_state
->base
.src
= drm_plane_state_src(plane_state
);
2914 intel_state
->base
.dst
= drm_plane_state_dest(plane_state
);
2916 obj
= intel_fb_obj(fb
);
2917 if (i915_gem_object_is_tiled(obj
))
2918 dev_priv
->preserve_bios_swizzle
= true;
2920 drm_framebuffer_get(fb
);
2921 primary
->fb
= primary
->state
->fb
= fb
;
2922 primary
->crtc
= primary
->state
->crtc
= &intel_crtc
->base
;
2924 intel_set_plane_visible(to_intel_crtc_state(crtc_state
),
2925 to_intel_plane_state(plane_state
),
2928 atomic_or(to_intel_plane(primary
)->frontbuffer_bit
,
2929 &obj
->frontbuffer_bits
);
2932 static int skl_max_plane_width(const struct drm_framebuffer
*fb
, int plane
,
2933 unsigned int rotation
)
2935 int cpp
= fb
->format
->cpp
[plane
];
2937 switch (fb
->modifier
) {
2938 case DRM_FORMAT_MOD_LINEAR
:
2939 case I915_FORMAT_MOD_X_TILED
:
2952 case I915_FORMAT_MOD_Y_TILED_CCS
:
2953 case I915_FORMAT_MOD_Yf_TILED_CCS
:
2954 /* FIXME AUX plane? */
2955 case I915_FORMAT_MOD_Y_TILED
:
2956 case I915_FORMAT_MOD_Yf_TILED
:
2971 MISSING_CASE(fb
->modifier
);
2977 static bool skl_check_main_ccs_coordinates(struct intel_plane_state
*plane_state
,
2978 int main_x
, int main_y
, u32 main_offset
)
2980 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
2981 int hsub
= fb
->format
->hsub
;
2982 int vsub
= fb
->format
->vsub
;
2983 int aux_x
= plane_state
->aux
.x
;
2984 int aux_y
= plane_state
->aux
.y
;
2985 u32 aux_offset
= plane_state
->aux
.offset
;
2986 u32 alignment
= intel_surf_alignment(fb
, 1);
2988 while (aux_offset
>= main_offset
&& aux_y
<= main_y
) {
2991 if (aux_x
== main_x
&& aux_y
== main_y
)
2994 if (aux_offset
== 0)
2999 aux_offset
= intel_adjust_tile_offset(&x
, &y
, plane_state
, 1,
3000 aux_offset
, aux_offset
- alignment
);
3001 aux_x
= x
* hsub
+ aux_x
% hsub
;
3002 aux_y
= y
* vsub
+ aux_y
% vsub
;
3005 if (aux_x
!= main_x
|| aux_y
!= main_y
)
3008 plane_state
->aux
.offset
= aux_offset
;
3009 plane_state
->aux
.x
= aux_x
;
3010 plane_state
->aux
.y
= aux_y
;
3015 static int skl_check_main_surface(struct intel_plane_state
*plane_state
)
3017 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3018 unsigned int rotation
= plane_state
->base
.rotation
;
3019 int x
= plane_state
->base
.src
.x1
>> 16;
3020 int y
= plane_state
->base
.src
.y1
>> 16;
3021 int w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
3022 int h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
3023 int max_width
= skl_max_plane_width(fb
, 0, rotation
);
3024 int max_height
= 4096;
3025 u32 alignment
, offset
, aux_offset
= plane_state
->aux
.offset
;
3027 if (w
> max_width
|| h
> max_height
) {
3028 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3029 w
, h
, max_width
, max_height
);
3033 intel_add_fb_offsets(&x
, &y
, plane_state
, 0);
3034 offset
= intel_compute_tile_offset(&x
, &y
, plane_state
, 0);
3035 alignment
= intel_surf_alignment(fb
, 0);
3038 * AUX surface offset is specified as the distance from the
3039 * main surface offset, and it must be non-negative. Make
3040 * sure that is what we will get.
3042 if (offset
> aux_offset
)
3043 offset
= intel_adjust_tile_offset(&x
, &y
, plane_state
, 0,
3044 offset
, aux_offset
& ~(alignment
- 1));
3047 * When using an X-tiled surface, the plane blows up
3048 * if the x offset + width exceed the stride.
3050 * TODO: linear and Y-tiled seem fine, Yf untested,
3052 if (fb
->modifier
== I915_FORMAT_MOD_X_TILED
) {
3053 int cpp
= fb
->format
->cpp
[0];
3055 while ((x
+ w
) * cpp
> fb
->pitches
[0]) {
3057 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3061 offset
= intel_adjust_tile_offset(&x
, &y
, plane_state
, 0,
3062 offset
, offset
- alignment
);
3067 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3068 * they match with the main surface x/y offsets.
3070 if (fb
->modifier
== I915_FORMAT_MOD_Y_TILED_CCS
||
3071 fb
->modifier
== I915_FORMAT_MOD_Yf_TILED_CCS
) {
3072 while (!skl_check_main_ccs_coordinates(plane_state
, x
, y
, offset
)) {
3076 offset
= intel_adjust_tile_offset(&x
, &y
, plane_state
, 0,
3077 offset
, offset
- alignment
);
3080 if (x
!= plane_state
->aux
.x
|| y
!= plane_state
->aux
.y
) {
3081 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3086 plane_state
->main
.offset
= offset
;
3087 plane_state
->main
.x
= x
;
3088 plane_state
->main
.y
= y
;
3093 static int skl_check_nv12_aux_surface(struct intel_plane_state
*plane_state
)
3095 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3096 unsigned int rotation
= plane_state
->base
.rotation
;
3097 int max_width
= skl_max_plane_width(fb
, 1, rotation
);
3098 int max_height
= 4096;
3099 int x
= plane_state
->base
.src
.x1
>> 17;
3100 int y
= plane_state
->base
.src
.y1
>> 17;
3101 int w
= drm_rect_width(&plane_state
->base
.src
) >> 17;
3102 int h
= drm_rect_height(&plane_state
->base
.src
) >> 17;
3105 intel_add_fb_offsets(&x
, &y
, plane_state
, 1);
3106 offset
= intel_compute_tile_offset(&x
, &y
, plane_state
, 1);
3108 /* FIXME not quite sure how/if these apply to the chroma plane */
3109 if (w
> max_width
|| h
> max_height
) {
3110 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3111 w
, h
, max_width
, max_height
);
3115 plane_state
->aux
.offset
= offset
;
3116 plane_state
->aux
.x
= x
;
3117 plane_state
->aux
.y
= y
;
3122 static int skl_check_ccs_aux_surface(struct intel_plane_state
*plane_state
)
3124 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
3125 struct intel_crtc
*crtc
= to_intel_crtc(plane_state
->base
.crtc
);
3126 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3127 int src_x
= plane_state
->base
.src
.x1
>> 16;
3128 int src_y
= plane_state
->base
.src
.y1
>> 16;
3129 int hsub
= fb
->format
->hsub
;
3130 int vsub
= fb
->format
->vsub
;
3131 int x
= src_x
/ hsub
;
3132 int y
= src_y
/ vsub
;
3135 switch (plane
->id
) {
3140 DRM_DEBUG_KMS("RC support only on plane 1 and 2\n");
3144 if (crtc
->pipe
== PIPE_C
) {
3145 DRM_DEBUG_KMS("No RC support on pipe C\n");
3149 if (plane_state
->base
.rotation
& ~(DRM_MODE_ROTATE_0
| DRM_MODE_ROTATE_180
)) {
3150 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n",
3151 plane_state
->base
.rotation
);
3155 intel_add_fb_offsets(&x
, &y
, plane_state
, 1);
3156 offset
= intel_compute_tile_offset(&x
, &y
, plane_state
, 1);
3158 plane_state
->aux
.offset
= offset
;
3159 plane_state
->aux
.x
= x
* hsub
+ src_x
% hsub
;
3160 plane_state
->aux
.y
= y
* vsub
+ src_y
% vsub
;
3165 int skl_check_plane_surface(struct intel_plane_state
*plane_state
)
3167 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3168 unsigned int rotation
= plane_state
->base
.rotation
;
3171 if (!plane_state
->base
.visible
)
3174 /* Rotate src coordinates to match rotated GTT view */
3175 if (drm_rotation_90_or_270(rotation
))
3176 drm_rect_rotate(&plane_state
->base
.src
,
3177 fb
->width
<< 16, fb
->height
<< 16,
3178 DRM_MODE_ROTATE_270
);
3181 * Handle the AUX surface first since
3182 * the main surface setup depends on it.
3184 if (fb
->format
->format
== DRM_FORMAT_NV12
) {
3185 ret
= skl_check_nv12_aux_surface(plane_state
);
3188 } else if (fb
->modifier
== I915_FORMAT_MOD_Y_TILED_CCS
||
3189 fb
->modifier
== I915_FORMAT_MOD_Yf_TILED_CCS
) {
3190 ret
= skl_check_ccs_aux_surface(plane_state
);
3194 plane_state
->aux
.offset
= ~0xfff;
3195 plane_state
->aux
.x
= 0;
3196 plane_state
->aux
.y
= 0;
3199 ret
= skl_check_main_surface(plane_state
);
3206 static u32
i9xx_plane_ctl(const struct intel_crtc_state
*crtc_state
,
3207 const struct intel_plane_state
*plane_state
)
3209 struct drm_i915_private
*dev_priv
=
3210 to_i915(plane_state
->base
.plane
->dev
);
3211 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3212 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3213 unsigned int rotation
= plane_state
->base
.rotation
;
3216 dspcntr
= DISPLAY_PLANE_ENABLE
| DISPPLANE_GAMMA_ENABLE
;
3218 if (IS_G4X(dev_priv
) || IS_GEN5(dev_priv
) ||
3219 IS_GEN6(dev_priv
) || IS_IVYBRIDGE(dev_priv
))
3220 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
3222 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
3223 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
3225 if (INTEL_GEN(dev_priv
) < 4)
3226 dspcntr
|= DISPPLANE_SEL_PIPE(crtc
->pipe
);
3228 switch (fb
->format
->format
) {
3230 dspcntr
|= DISPPLANE_8BPP
;
3232 case DRM_FORMAT_XRGB1555
:
3233 dspcntr
|= DISPPLANE_BGRX555
;
3235 case DRM_FORMAT_RGB565
:
3236 dspcntr
|= DISPPLANE_BGRX565
;
3238 case DRM_FORMAT_XRGB8888
:
3239 dspcntr
|= DISPPLANE_BGRX888
;
3241 case DRM_FORMAT_XBGR8888
:
3242 dspcntr
|= DISPPLANE_RGBX888
;
3244 case DRM_FORMAT_XRGB2101010
:
3245 dspcntr
|= DISPPLANE_BGRX101010
;
3247 case DRM_FORMAT_XBGR2101010
:
3248 dspcntr
|= DISPPLANE_RGBX101010
;
3251 MISSING_CASE(fb
->format
->format
);
3255 if (INTEL_GEN(dev_priv
) >= 4 &&
3256 fb
->modifier
== I915_FORMAT_MOD_X_TILED
)
3257 dspcntr
|= DISPPLANE_TILED
;
3259 if (rotation
& DRM_MODE_ROTATE_180
)
3260 dspcntr
|= DISPPLANE_ROTATE_180
;
3262 if (rotation
& DRM_MODE_REFLECT_X
)
3263 dspcntr
|= DISPPLANE_MIRROR
;
3268 int i9xx_check_plane_surface(struct intel_plane_state
*plane_state
)
3270 struct drm_i915_private
*dev_priv
=
3271 to_i915(plane_state
->base
.plane
->dev
);
3272 int src_x
= plane_state
->base
.src
.x1
>> 16;
3273 int src_y
= plane_state
->base
.src
.y1
>> 16;
3276 intel_add_fb_offsets(&src_x
, &src_y
, plane_state
, 0);
3278 if (INTEL_GEN(dev_priv
) >= 4)
3279 offset
= intel_compute_tile_offset(&src_x
, &src_y
,
3284 /* HSW/BDW do this automagically in hardware */
3285 if (!IS_HASWELL(dev_priv
) && !IS_BROADWELL(dev_priv
)) {
3286 unsigned int rotation
= plane_state
->base
.rotation
;
3287 int src_w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
3288 int src_h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
3290 if (rotation
& DRM_MODE_ROTATE_180
) {
3293 } else if (rotation
& DRM_MODE_REFLECT_X
) {
3298 plane_state
->main
.offset
= offset
;
3299 plane_state
->main
.x
= src_x
;
3300 plane_state
->main
.y
= src_y
;
3305 static void i9xx_update_primary_plane(struct intel_plane
*primary
,
3306 const struct intel_crtc_state
*crtc_state
,
3307 const struct intel_plane_state
*plane_state
)
3309 struct drm_i915_private
*dev_priv
= to_i915(primary
->base
.dev
);
3310 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3311 enum plane plane
= primary
->plane
;
3313 u32 dspcntr
= plane_state
->ctl
;
3314 i915_reg_t reg
= DSPCNTR(plane
);
3315 int x
= plane_state
->main
.x
;
3316 int y
= plane_state
->main
.y
;
3317 unsigned long irqflags
;
3320 linear_offset
= intel_fb_xy_to_linear(x
, y
, plane_state
, 0);
3322 if (INTEL_GEN(dev_priv
) >= 4)
3323 dspaddr_offset
= plane_state
->main
.offset
;
3325 dspaddr_offset
= linear_offset
;
3327 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
3329 if (INTEL_GEN(dev_priv
) < 4) {
3330 /* pipesrc and dspsize control the size that is scaled from,
3331 * which should always be the user's requested size.
3333 I915_WRITE_FW(DSPSIZE(plane
),
3334 ((crtc_state
->pipe_src_h
- 1) << 16) |
3335 (crtc_state
->pipe_src_w
- 1));
3336 I915_WRITE_FW(DSPPOS(plane
), 0);
3337 } else if (IS_CHERRYVIEW(dev_priv
) && plane
== PLANE_B
) {
3338 I915_WRITE_FW(PRIMSIZE(plane
),
3339 ((crtc_state
->pipe_src_h
- 1) << 16) |
3340 (crtc_state
->pipe_src_w
- 1));
3341 I915_WRITE_FW(PRIMPOS(plane
), 0);
3342 I915_WRITE_FW(PRIMCNSTALPHA(plane
), 0);
3345 I915_WRITE_FW(reg
, dspcntr
);
3347 I915_WRITE_FW(DSPSTRIDE(plane
), fb
->pitches
[0]);
3348 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
3349 I915_WRITE_FW(DSPSURF(plane
),
3350 intel_plane_ggtt_offset(plane_state
) +
3352 I915_WRITE_FW(DSPOFFSET(plane
), (y
<< 16) | x
);
3353 } else if (INTEL_GEN(dev_priv
) >= 4) {
3354 I915_WRITE_FW(DSPSURF(plane
),
3355 intel_plane_ggtt_offset(plane_state
) +
3357 I915_WRITE_FW(DSPTILEOFF(plane
), (y
<< 16) | x
);
3358 I915_WRITE_FW(DSPLINOFF(plane
), linear_offset
);
3360 I915_WRITE_FW(DSPADDR(plane
),
3361 intel_plane_ggtt_offset(plane_state
) +
3364 POSTING_READ_FW(reg
);
3366 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
3369 static void i9xx_disable_primary_plane(struct intel_plane
*primary
,
3370 struct intel_crtc
*crtc
)
3372 struct drm_i915_private
*dev_priv
= to_i915(primary
->base
.dev
);
3373 enum plane plane
= primary
->plane
;
3374 unsigned long irqflags
;
3376 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
3378 I915_WRITE_FW(DSPCNTR(plane
), 0);
3379 if (INTEL_INFO(dev_priv
)->gen
>= 4)
3380 I915_WRITE_FW(DSPSURF(plane
), 0);
3382 I915_WRITE_FW(DSPADDR(plane
), 0);
3383 POSTING_READ_FW(DSPCNTR(plane
));
3385 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
3389 intel_fb_stride_alignment(const struct drm_framebuffer
*fb
, int plane
)
3391 if (fb
->modifier
== DRM_FORMAT_MOD_LINEAR
)
3394 return intel_tile_width_bytes(fb
, plane
);
3397 static void skl_detach_scaler(struct intel_crtc
*intel_crtc
, int id
)
3399 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3400 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3402 I915_WRITE(SKL_PS_CTRL(intel_crtc
->pipe
, id
), 0);
3403 I915_WRITE(SKL_PS_WIN_POS(intel_crtc
->pipe
, id
), 0);
3404 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc
->pipe
, id
), 0);
3408 * This function detaches (aka. unbinds) unused scalers in hardware
3410 static void skl_detach_scalers(struct intel_crtc
*intel_crtc
)
3412 struct intel_crtc_scaler_state
*scaler_state
;
3415 scaler_state
= &intel_crtc
->config
->scaler_state
;
3417 /* loop through and disable scalers that aren't in use */
3418 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
3419 if (!scaler_state
->scalers
[i
].in_use
)
3420 skl_detach_scaler(intel_crtc
, i
);
3424 u32
skl_plane_stride(const struct drm_framebuffer
*fb
, int plane
,
3425 unsigned int rotation
)
3429 if (plane
>= fb
->format
->num_planes
)
3432 stride
= intel_fb_pitch(fb
, plane
, rotation
);
3435 * The stride is either expressed as a multiple of 64 bytes chunks for
3436 * linear buffers or in number of tiles for tiled buffers.
3438 if (drm_rotation_90_or_270(rotation
))
3439 stride
/= intel_tile_height(fb
, plane
);
3441 stride
/= intel_fb_stride_alignment(fb
, plane
);
3446 static u32
skl_plane_ctl_format(uint32_t pixel_format
)
3448 switch (pixel_format
) {
3450 return PLANE_CTL_FORMAT_INDEXED
;
3451 case DRM_FORMAT_RGB565
:
3452 return PLANE_CTL_FORMAT_RGB_565
;
3453 case DRM_FORMAT_XBGR8888
:
3454 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
;
3455 case DRM_FORMAT_XRGB8888
:
3456 return PLANE_CTL_FORMAT_XRGB_8888
;
3458 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3459 * to be already pre-multiplied. We need to add a knob (or a different
3460 * DRM_FORMAT) for user-space to configure that.
3462 case DRM_FORMAT_ABGR8888
:
3463 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
|
3464 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
3465 case DRM_FORMAT_ARGB8888
:
3466 return PLANE_CTL_FORMAT_XRGB_8888
|
3467 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
3468 case DRM_FORMAT_XRGB2101010
:
3469 return PLANE_CTL_FORMAT_XRGB_2101010
;
3470 case DRM_FORMAT_XBGR2101010
:
3471 return PLANE_CTL_ORDER_RGBX
| PLANE_CTL_FORMAT_XRGB_2101010
;
3472 case DRM_FORMAT_YUYV
:
3473 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YUYV
;
3474 case DRM_FORMAT_YVYU
:
3475 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YVYU
;
3476 case DRM_FORMAT_UYVY
:
3477 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_UYVY
;
3478 case DRM_FORMAT_VYUY
:
3479 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_VYUY
;
3481 MISSING_CASE(pixel_format
);
3487 static u32
skl_plane_ctl_tiling(uint64_t fb_modifier
)
3489 switch (fb_modifier
) {
3490 case DRM_FORMAT_MOD_LINEAR
:
3492 case I915_FORMAT_MOD_X_TILED
:
3493 return PLANE_CTL_TILED_X
;
3494 case I915_FORMAT_MOD_Y_TILED
:
3495 return PLANE_CTL_TILED_Y
;
3496 case I915_FORMAT_MOD_Y_TILED_CCS
:
3497 return PLANE_CTL_TILED_Y
| PLANE_CTL_DECOMPRESSION_ENABLE
;
3498 case I915_FORMAT_MOD_Yf_TILED
:
3499 return PLANE_CTL_TILED_YF
;
3500 case I915_FORMAT_MOD_Yf_TILED_CCS
:
3501 return PLANE_CTL_TILED_YF
| PLANE_CTL_DECOMPRESSION_ENABLE
;
3503 MISSING_CASE(fb_modifier
);
3509 static u32
skl_plane_ctl_rotation(unsigned int rotation
)
3512 case DRM_MODE_ROTATE_0
:
3515 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3516 * while i915 HW rotation is clockwise, thats why this swapping.
3518 case DRM_MODE_ROTATE_90
:
3519 return PLANE_CTL_ROTATE_270
;
3520 case DRM_MODE_ROTATE_180
:
3521 return PLANE_CTL_ROTATE_180
;
3522 case DRM_MODE_ROTATE_270
:
3523 return PLANE_CTL_ROTATE_90
;
3525 MISSING_CASE(rotation
);
3531 u32
skl_plane_ctl(const struct intel_crtc_state
*crtc_state
,
3532 const struct intel_plane_state
*plane_state
)
3534 struct drm_i915_private
*dev_priv
=
3535 to_i915(plane_state
->base
.plane
->dev
);
3536 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3537 unsigned int rotation
= plane_state
->base
.rotation
;
3538 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
3541 plane_ctl
= PLANE_CTL_ENABLE
;
3543 if (!IS_GEMINILAKE(dev_priv
) && !IS_CANNONLAKE(dev_priv
)) {
3545 PLANE_CTL_PIPE_GAMMA_ENABLE
|
3546 PLANE_CTL_PIPE_CSC_ENABLE
|
3547 PLANE_CTL_PLANE_GAMMA_DISABLE
;
3550 plane_ctl
|= skl_plane_ctl_format(fb
->format
->format
);
3551 plane_ctl
|= skl_plane_ctl_tiling(fb
->modifier
);
3552 plane_ctl
|= skl_plane_ctl_rotation(rotation
);
3554 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
3555 plane_ctl
|= PLANE_CTL_KEY_ENABLE_DESTINATION
;
3556 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
3557 plane_ctl
|= PLANE_CTL_KEY_ENABLE_SOURCE
;
3563 __intel_display_resume(struct drm_device
*dev
,
3564 struct drm_atomic_state
*state
,
3565 struct drm_modeset_acquire_ctx
*ctx
)
3567 struct drm_crtc_state
*crtc_state
;
3568 struct drm_crtc
*crtc
;
3571 intel_modeset_setup_hw_state(dev
, ctx
);
3572 i915_redisable_vga(to_i915(dev
));
3578 * We've duplicated the state, pointers to the old state are invalid.
3580 * Don't attempt to use the old state until we commit the duplicated state.
3582 for_each_new_crtc_in_state(state
, crtc
, crtc_state
, i
) {
3584 * Force recalculation even if we restore
3585 * current state. With fast modeset this may not result
3586 * in a modeset when the state is compatible.
3588 crtc_state
->mode_changed
= true;
3591 /* ignore any reset values/BIOS leftovers in the WM registers */
3592 if (!HAS_GMCH_DISPLAY(to_i915(dev
)))
3593 to_intel_atomic_state(state
)->skip_intermediate_wm
= true;
3595 ret
= drm_atomic_helper_commit_duplicated_state(state
, ctx
);
3597 WARN_ON(ret
== -EDEADLK
);
3601 static bool gpu_reset_clobbers_display(struct drm_i915_private
*dev_priv
)
3603 return intel_has_gpu_reset(dev_priv
) &&
3604 INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
);
3607 void intel_prepare_reset(struct drm_i915_private
*dev_priv
)
3609 struct drm_device
*dev
= &dev_priv
->drm
;
3610 struct drm_modeset_acquire_ctx
*ctx
= &dev_priv
->reset_ctx
;
3611 struct drm_atomic_state
*state
;
3615 /* reset doesn't touch the display */
3616 if (!i915_modparams
.force_reset_modeset_test
&&
3617 !gpu_reset_clobbers_display(dev_priv
))
3620 /* We have a modeset vs reset deadlock, defensively unbreak it. */
3621 set_bit(I915_RESET_MODESET
, &dev_priv
->gpu_error
.flags
);
3622 wake_up_all(&dev_priv
->gpu_error
.wait_queue
);
3624 if (atomic_read(&dev_priv
->gpu_error
.pending_fb_pin
)) {
3625 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
3626 i915_gem_set_wedged(dev_priv
);
3630 * Need mode_config.mutex so that we don't
3631 * trample ongoing ->detect() and whatnot.
3633 mutex_lock(&dev
->mode_config
.mutex
);
3634 drm_modeset_acquire_init(ctx
, 0);
3636 ret
= drm_modeset_lock_all_ctx(dev
, ctx
);
3637 if (ret
!= -EDEADLK
)
3640 drm_modeset_backoff(ctx
);
3643 * Disabling the crtcs gracefully seems nicer. Also the
3644 * g33 docs say we should at least disable all the planes.
3646 state
= drm_atomic_helper_duplicate_state(dev
, ctx
);
3647 if (IS_ERR(state
)) {
3648 ret
= PTR_ERR(state
);
3649 DRM_ERROR("Duplicating state failed with %i\n", ret
);
3653 ret
= drm_atomic_helper_disable_all(dev
, ctx
);
3655 DRM_ERROR("Suspending crtc's failed with %i\n", ret
);
3656 drm_atomic_state_put(state
);
3660 dev_priv
->modeset_restore_state
= state
;
3661 state
->acquire_ctx
= ctx
;
3664 void intel_finish_reset(struct drm_i915_private
*dev_priv
)
3666 struct drm_device
*dev
= &dev_priv
->drm
;
3667 struct drm_modeset_acquire_ctx
*ctx
= &dev_priv
->reset_ctx
;
3668 struct drm_atomic_state
*state
= dev_priv
->modeset_restore_state
;
3671 /* reset doesn't touch the display */
3672 if (!i915_modparams
.force_reset_modeset_test
&&
3673 !gpu_reset_clobbers_display(dev_priv
))
3679 dev_priv
->modeset_restore_state
= NULL
;
3681 /* reset doesn't touch the display */
3682 if (!gpu_reset_clobbers_display(dev_priv
)) {
3683 /* for testing only restore the display */
3684 ret
= __intel_display_resume(dev
, state
, ctx
);
3686 DRM_ERROR("Restoring old state failed with %i\n", ret
);
3689 * The display has been reset as well,
3690 * so need a full re-initialization.
3692 intel_runtime_pm_disable_interrupts(dev_priv
);
3693 intel_runtime_pm_enable_interrupts(dev_priv
);
3695 intel_pps_unlock_regs_wa(dev_priv
);
3696 intel_modeset_init_hw(dev
);
3697 intel_init_clock_gating(dev_priv
);
3699 spin_lock_irq(&dev_priv
->irq_lock
);
3700 if (dev_priv
->display
.hpd_irq_setup
)
3701 dev_priv
->display
.hpd_irq_setup(dev_priv
);
3702 spin_unlock_irq(&dev_priv
->irq_lock
);
3704 ret
= __intel_display_resume(dev
, state
, ctx
);
3706 DRM_ERROR("Restoring old state failed with %i\n", ret
);
3708 intel_hpd_init(dev_priv
);
3711 drm_atomic_state_put(state
);
3713 drm_modeset_drop_locks(ctx
);
3714 drm_modeset_acquire_fini(ctx
);
3715 mutex_unlock(&dev
->mode_config
.mutex
);
3717 clear_bit(I915_RESET_MODESET
, &dev_priv
->gpu_error
.flags
);
3720 static void intel_update_pipe_config(const struct intel_crtc_state
*old_crtc_state
,
3721 const struct intel_crtc_state
*new_crtc_state
)
3723 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->base
.crtc
);
3724 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3726 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3727 crtc
->base
.mode
= new_crtc_state
->base
.mode
;
3730 * Update pipe size and adjust fitter if needed: the reason for this is
3731 * that in compute_mode_changes we check the native mode (not the pfit
3732 * mode) to see if we can flip rather than do a full mode set. In the
3733 * fastboot case, we'll flip, but if we don't update the pipesrc and
3734 * pfit state, we'll end up with a big fb scanned out into the wrong
3738 I915_WRITE(PIPESRC(crtc
->pipe
),
3739 ((new_crtc_state
->pipe_src_w
- 1) << 16) |
3740 (new_crtc_state
->pipe_src_h
- 1));
3742 /* on skylake this is done by detaching scalers */
3743 if (INTEL_GEN(dev_priv
) >= 9) {
3744 skl_detach_scalers(crtc
);
3746 if (new_crtc_state
->pch_pfit
.enabled
)
3747 skylake_pfit_enable(crtc
);
3748 } else if (HAS_PCH_SPLIT(dev_priv
)) {
3749 if (new_crtc_state
->pch_pfit
.enabled
)
3750 ironlake_pfit_enable(crtc
);
3751 else if (old_crtc_state
->pch_pfit
.enabled
)
3752 ironlake_pfit_disable(crtc
, true);
3756 static void intel_fdi_normal_train(struct intel_crtc
*crtc
)
3758 struct drm_device
*dev
= crtc
->base
.dev
;
3759 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3760 int pipe
= crtc
->pipe
;
3764 /* enable normal train */
3765 reg
= FDI_TX_CTL(pipe
);
3766 temp
= I915_READ(reg
);
3767 if (IS_IVYBRIDGE(dev_priv
)) {
3768 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3769 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3771 temp
&= ~FDI_LINK_TRAIN_NONE
;
3772 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3774 I915_WRITE(reg
, temp
);
3776 reg
= FDI_RX_CTL(pipe
);
3777 temp
= I915_READ(reg
);
3778 if (HAS_PCH_CPT(dev_priv
)) {
3779 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3780 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
3782 temp
&= ~FDI_LINK_TRAIN_NONE
;
3783 temp
|= FDI_LINK_TRAIN_NONE
;
3785 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
3787 /* wait one idle pattern time */
3791 /* IVB wants error correction enabled */
3792 if (IS_IVYBRIDGE(dev_priv
))
3793 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
3794 FDI_FE_ERRC_ENABLE
);
3797 /* The FDI link training functions for ILK/Ibexpeak. */
3798 static void ironlake_fdi_link_train(struct intel_crtc
*crtc
,
3799 const struct intel_crtc_state
*crtc_state
)
3801 struct drm_device
*dev
= crtc
->base
.dev
;
3802 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3803 int pipe
= crtc
->pipe
;
3807 /* FDI needs bits from pipe first */
3808 assert_pipe_enabled(dev_priv
, pipe
);
3810 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3812 reg
= FDI_RX_IMR(pipe
);
3813 temp
= I915_READ(reg
);
3814 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3815 temp
&= ~FDI_RX_BIT_LOCK
;
3816 I915_WRITE(reg
, temp
);
3820 /* enable CPU FDI TX and PCH FDI RX */
3821 reg
= FDI_TX_CTL(pipe
);
3822 temp
= I915_READ(reg
);
3823 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3824 temp
|= FDI_DP_PORT_WIDTH(crtc_state
->fdi_lanes
);
3825 temp
&= ~FDI_LINK_TRAIN_NONE
;
3826 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3827 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3829 reg
= FDI_RX_CTL(pipe
);
3830 temp
= I915_READ(reg
);
3831 temp
&= ~FDI_LINK_TRAIN_NONE
;
3832 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3833 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3838 /* Ironlake workaround, enable clock pointer after FDI enable*/
3839 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3840 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3841 FDI_RX_PHASE_SYNC_POINTER_EN
);
3843 reg
= FDI_RX_IIR(pipe
);
3844 for (tries
= 0; tries
< 5; tries
++) {
3845 temp
= I915_READ(reg
);
3846 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3848 if ((temp
& FDI_RX_BIT_LOCK
)) {
3849 DRM_DEBUG_KMS("FDI train 1 done.\n");
3850 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3855 DRM_ERROR("FDI train 1 fail!\n");
3858 reg
= FDI_TX_CTL(pipe
);
3859 temp
= I915_READ(reg
);
3860 temp
&= ~FDI_LINK_TRAIN_NONE
;
3861 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3862 I915_WRITE(reg
, temp
);
3864 reg
= FDI_RX_CTL(pipe
);
3865 temp
= I915_READ(reg
);
3866 temp
&= ~FDI_LINK_TRAIN_NONE
;
3867 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3868 I915_WRITE(reg
, temp
);
3873 reg
= FDI_RX_IIR(pipe
);
3874 for (tries
= 0; tries
< 5; tries
++) {
3875 temp
= I915_READ(reg
);
3876 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3878 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3879 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3880 DRM_DEBUG_KMS("FDI train 2 done.\n");
3885 DRM_ERROR("FDI train 2 fail!\n");
3887 DRM_DEBUG_KMS("FDI train done\n");
3891 static const int snb_b_fdi_train_param
[] = {
3892 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3893 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3894 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3895 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3898 /* The FDI link training functions for SNB/Cougarpoint. */
3899 static void gen6_fdi_link_train(struct intel_crtc
*crtc
,
3900 const struct intel_crtc_state
*crtc_state
)
3902 struct drm_device
*dev
= crtc
->base
.dev
;
3903 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3904 int pipe
= crtc
->pipe
;
3908 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3910 reg
= FDI_RX_IMR(pipe
);
3911 temp
= I915_READ(reg
);
3912 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3913 temp
&= ~FDI_RX_BIT_LOCK
;
3914 I915_WRITE(reg
, temp
);
3919 /* enable CPU FDI TX and PCH FDI RX */
3920 reg
= FDI_TX_CTL(pipe
);
3921 temp
= I915_READ(reg
);
3922 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3923 temp
|= FDI_DP_PORT_WIDTH(crtc_state
->fdi_lanes
);
3924 temp
&= ~FDI_LINK_TRAIN_NONE
;
3925 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3926 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3928 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3929 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3931 I915_WRITE(FDI_RX_MISC(pipe
),
3932 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3934 reg
= FDI_RX_CTL(pipe
);
3935 temp
= I915_READ(reg
);
3936 if (HAS_PCH_CPT(dev_priv
)) {
3937 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3938 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3940 temp
&= ~FDI_LINK_TRAIN_NONE
;
3941 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3943 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3948 for (i
= 0; i
< 4; i
++) {
3949 reg
= FDI_TX_CTL(pipe
);
3950 temp
= I915_READ(reg
);
3951 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3952 temp
|= snb_b_fdi_train_param
[i
];
3953 I915_WRITE(reg
, temp
);
3958 for (retry
= 0; retry
< 5; retry
++) {
3959 reg
= FDI_RX_IIR(pipe
);
3960 temp
= I915_READ(reg
);
3961 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3962 if (temp
& FDI_RX_BIT_LOCK
) {
3963 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3964 DRM_DEBUG_KMS("FDI train 1 done.\n");
3973 DRM_ERROR("FDI train 1 fail!\n");
3976 reg
= FDI_TX_CTL(pipe
);
3977 temp
= I915_READ(reg
);
3978 temp
&= ~FDI_LINK_TRAIN_NONE
;
3979 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3980 if (IS_GEN6(dev_priv
)) {
3981 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3983 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3985 I915_WRITE(reg
, temp
);
3987 reg
= FDI_RX_CTL(pipe
);
3988 temp
= I915_READ(reg
);
3989 if (HAS_PCH_CPT(dev_priv
)) {
3990 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3991 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3993 temp
&= ~FDI_LINK_TRAIN_NONE
;
3994 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3996 I915_WRITE(reg
, temp
);
4001 for (i
= 0; i
< 4; i
++) {
4002 reg
= FDI_TX_CTL(pipe
);
4003 temp
= I915_READ(reg
);
4004 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4005 temp
|= snb_b_fdi_train_param
[i
];
4006 I915_WRITE(reg
, temp
);
4011 for (retry
= 0; retry
< 5; retry
++) {
4012 reg
= FDI_RX_IIR(pipe
);
4013 temp
= I915_READ(reg
);
4014 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4015 if (temp
& FDI_RX_SYMBOL_LOCK
) {
4016 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
4017 DRM_DEBUG_KMS("FDI train 2 done.\n");
4026 DRM_ERROR("FDI train 2 fail!\n");
4028 DRM_DEBUG_KMS("FDI train done.\n");
4031 /* Manual link training for Ivy Bridge A0 parts */
4032 static void ivb_manual_fdi_link_train(struct intel_crtc
*crtc
,
4033 const struct intel_crtc_state
*crtc_state
)
4035 struct drm_device
*dev
= crtc
->base
.dev
;
4036 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4037 int pipe
= crtc
->pipe
;
4041 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4043 reg
= FDI_RX_IMR(pipe
);
4044 temp
= I915_READ(reg
);
4045 temp
&= ~FDI_RX_SYMBOL_LOCK
;
4046 temp
&= ~FDI_RX_BIT_LOCK
;
4047 I915_WRITE(reg
, temp
);
4052 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4053 I915_READ(FDI_RX_IIR(pipe
)));
4055 /* Try each vswing and preemphasis setting twice before moving on */
4056 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
4057 /* disable first in case we need to retry */
4058 reg
= FDI_TX_CTL(pipe
);
4059 temp
= I915_READ(reg
);
4060 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
4061 temp
&= ~FDI_TX_ENABLE
;
4062 I915_WRITE(reg
, temp
);
4064 reg
= FDI_RX_CTL(pipe
);
4065 temp
= I915_READ(reg
);
4066 temp
&= ~FDI_LINK_TRAIN_AUTO
;
4067 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4068 temp
&= ~FDI_RX_ENABLE
;
4069 I915_WRITE(reg
, temp
);
4071 /* enable CPU FDI TX and PCH FDI RX */
4072 reg
= FDI_TX_CTL(pipe
);
4073 temp
= I915_READ(reg
);
4074 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
4075 temp
|= FDI_DP_PORT_WIDTH(crtc_state
->fdi_lanes
);
4076 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
4077 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4078 temp
|= snb_b_fdi_train_param
[j
/2];
4079 temp
|= FDI_COMPOSITE_SYNC
;
4080 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
4082 I915_WRITE(FDI_RX_MISC(pipe
),
4083 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
4085 reg
= FDI_RX_CTL(pipe
);
4086 temp
= I915_READ(reg
);
4087 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
4088 temp
|= FDI_COMPOSITE_SYNC
;
4089 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
4092 udelay(1); /* should be 0.5us */
4094 for (i
= 0; i
< 4; i
++) {
4095 reg
= FDI_RX_IIR(pipe
);
4096 temp
= I915_READ(reg
);
4097 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4099 if (temp
& FDI_RX_BIT_LOCK
||
4100 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
4101 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
4102 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4106 udelay(1); /* should be 0.5us */
4109 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
4114 reg
= FDI_TX_CTL(pipe
);
4115 temp
= I915_READ(reg
);
4116 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
4117 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
4118 I915_WRITE(reg
, temp
);
4120 reg
= FDI_RX_CTL(pipe
);
4121 temp
= I915_READ(reg
);
4122 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4123 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
4124 I915_WRITE(reg
, temp
);
4127 udelay(2); /* should be 1.5us */
4129 for (i
= 0; i
< 4; i
++) {
4130 reg
= FDI_RX_IIR(pipe
);
4131 temp
= I915_READ(reg
);
4132 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4134 if (temp
& FDI_RX_SYMBOL_LOCK
||
4135 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
4136 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
4137 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4141 udelay(2); /* should be 1.5us */
4144 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
4148 DRM_DEBUG_KMS("FDI train done.\n");
4151 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
4153 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4154 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4155 int pipe
= intel_crtc
->pipe
;
4159 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4160 reg
= FDI_RX_CTL(pipe
);
4161 temp
= I915_READ(reg
);
4162 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
4163 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
4164 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
4165 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
4170 /* Switch from Rawclk to PCDclk */
4171 temp
= I915_READ(reg
);
4172 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
4177 /* Enable CPU FDI TX PLL, always on for Ironlake */
4178 reg
= FDI_TX_CTL(pipe
);
4179 temp
= I915_READ(reg
);
4180 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
4181 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
4188 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
4190 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4191 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4192 int pipe
= intel_crtc
->pipe
;
4196 /* Switch from PCDclk to Rawclk */
4197 reg
= FDI_RX_CTL(pipe
);
4198 temp
= I915_READ(reg
);
4199 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
4201 /* Disable CPU FDI TX PLL */
4202 reg
= FDI_TX_CTL(pipe
);
4203 temp
= I915_READ(reg
);
4204 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
4209 reg
= FDI_RX_CTL(pipe
);
4210 temp
= I915_READ(reg
);
4211 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
4213 /* Wait for the clocks to turn off. */
4218 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
4220 struct drm_device
*dev
= crtc
->dev
;
4221 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4222 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4223 int pipe
= intel_crtc
->pipe
;
4227 /* disable CPU FDI tx and PCH FDI rx */
4228 reg
= FDI_TX_CTL(pipe
);
4229 temp
= I915_READ(reg
);
4230 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
4233 reg
= FDI_RX_CTL(pipe
);
4234 temp
= I915_READ(reg
);
4235 temp
&= ~(0x7 << 16);
4236 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
4237 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
4242 /* Ironlake workaround, disable clock pointer after downing FDI */
4243 if (HAS_PCH_IBX(dev_priv
))
4244 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
4246 /* still set train pattern 1 */
4247 reg
= FDI_TX_CTL(pipe
);
4248 temp
= I915_READ(reg
);
4249 temp
&= ~FDI_LINK_TRAIN_NONE
;
4250 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4251 I915_WRITE(reg
, temp
);
4253 reg
= FDI_RX_CTL(pipe
);
4254 temp
= I915_READ(reg
);
4255 if (HAS_PCH_CPT(dev_priv
)) {
4256 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4257 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
4259 temp
&= ~FDI_LINK_TRAIN_NONE
;
4260 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4262 /* BPC in FDI rx is consistent with that in PIPECONF */
4263 temp
&= ~(0x07 << 16);
4264 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
4265 I915_WRITE(reg
, temp
);
4271 bool intel_has_pending_fb_unpin(struct drm_i915_private
*dev_priv
)
4273 struct drm_crtc
*crtc
;
4276 drm_for_each_crtc(crtc
, &dev_priv
->drm
) {
4277 struct drm_crtc_commit
*commit
;
4278 spin_lock(&crtc
->commit_lock
);
4279 commit
= list_first_entry_or_null(&crtc
->commit_list
,
4280 struct drm_crtc_commit
, commit_entry
);
4281 cleanup_done
= commit
?
4282 try_wait_for_completion(&commit
->cleanup_done
) : true;
4283 spin_unlock(&crtc
->commit_lock
);
4288 drm_crtc_wait_one_vblank(crtc
);
4296 void lpt_disable_iclkip(struct drm_i915_private
*dev_priv
)
4300 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
4302 mutex_lock(&dev_priv
->sb_lock
);
4304 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4305 temp
|= SBI_SSCCTL_DISABLE
;
4306 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
4308 mutex_unlock(&dev_priv
->sb_lock
);
4311 /* Program iCLKIP clock to the desired frequency */
4312 static void lpt_program_iclkip(struct intel_crtc
*crtc
)
4314 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4315 int clock
= crtc
->config
->base
.adjusted_mode
.crtc_clock
;
4316 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
4319 lpt_disable_iclkip(dev_priv
);
4321 /* The iCLK virtual clock root frequency is in MHz,
4322 * but the adjusted_mode->crtc_clock in in KHz. To get the
4323 * divisors, it is necessary to divide one by another, so we
4324 * convert the virtual clock precision to KHz here for higher
4327 for (auxdiv
= 0; auxdiv
< 2; auxdiv
++) {
4328 u32 iclk_virtual_root_freq
= 172800 * 1000;
4329 u32 iclk_pi_range
= 64;
4330 u32 desired_divisor
;
4332 desired_divisor
= DIV_ROUND_CLOSEST(iclk_virtual_root_freq
,
4334 divsel
= (desired_divisor
/ iclk_pi_range
) - 2;
4335 phaseinc
= desired_divisor
% iclk_pi_range
;
4338 * Near 20MHz is a corner case which is
4339 * out of range for the 7-bit divisor
4345 /* This should not happen with any sane values */
4346 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
4347 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
4348 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
4349 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
4351 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4358 mutex_lock(&dev_priv
->sb_lock
);
4360 /* Program SSCDIVINTPHASE6 */
4361 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
4362 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
4363 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
4364 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
4365 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
4366 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
4367 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
4368 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
4370 /* Program SSCAUXDIV */
4371 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
4372 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4373 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
4374 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
4376 /* Enable modulator and associated divider */
4377 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4378 temp
&= ~SBI_SSCCTL_DISABLE
;
4379 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
4381 mutex_unlock(&dev_priv
->sb_lock
);
4383 /* Wait for initialization time */
4386 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
4389 int lpt_get_iclkip(struct drm_i915_private
*dev_priv
)
4391 u32 divsel
, phaseinc
, auxdiv
;
4392 u32 iclk_virtual_root_freq
= 172800 * 1000;
4393 u32 iclk_pi_range
= 64;
4394 u32 desired_divisor
;
4397 if ((I915_READ(PIXCLK_GATE
) & PIXCLK_GATE_UNGATE
) == 0)
4400 mutex_lock(&dev_priv
->sb_lock
);
4402 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4403 if (temp
& SBI_SSCCTL_DISABLE
) {
4404 mutex_unlock(&dev_priv
->sb_lock
);
4408 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
4409 divsel
= (temp
& SBI_SSCDIVINTPHASE_DIVSEL_MASK
) >>
4410 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT
;
4411 phaseinc
= (temp
& SBI_SSCDIVINTPHASE_INCVAL_MASK
) >>
4412 SBI_SSCDIVINTPHASE_INCVAL_SHIFT
;
4414 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
4415 auxdiv
= (temp
& SBI_SSCAUXDIV_FINALDIV2SEL_MASK
) >>
4416 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT
;
4418 mutex_unlock(&dev_priv
->sb_lock
);
4420 desired_divisor
= (divsel
+ 2) * iclk_pi_range
+ phaseinc
;
4422 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq
,
4423 desired_divisor
<< auxdiv
);
4426 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
4427 enum pipe pch_transcoder
)
4429 struct drm_device
*dev
= crtc
->base
.dev
;
4430 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4431 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
4433 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
4434 I915_READ(HTOTAL(cpu_transcoder
)));
4435 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
4436 I915_READ(HBLANK(cpu_transcoder
)));
4437 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
4438 I915_READ(HSYNC(cpu_transcoder
)));
4440 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
4441 I915_READ(VTOTAL(cpu_transcoder
)));
4442 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
4443 I915_READ(VBLANK(cpu_transcoder
)));
4444 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
4445 I915_READ(VSYNC(cpu_transcoder
)));
4446 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
4447 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
4450 static void cpt_set_fdi_bc_bifurcation(struct drm_device
*dev
, bool enable
)
4452 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4455 temp
= I915_READ(SOUTH_CHICKEN1
);
4456 if (!!(temp
& FDI_BC_BIFURCATION_SELECT
) == enable
)
4459 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
4460 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
4462 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
4464 temp
|= FDI_BC_BIFURCATION_SELECT
;
4466 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable
? "en" : "dis");
4467 I915_WRITE(SOUTH_CHICKEN1
, temp
);
4468 POSTING_READ(SOUTH_CHICKEN1
);
4471 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
4473 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4475 switch (intel_crtc
->pipe
) {
4479 if (intel_crtc
->config
->fdi_lanes
> 2)
4480 cpt_set_fdi_bc_bifurcation(dev
, false);
4482 cpt_set_fdi_bc_bifurcation(dev
, true);
4486 cpt_set_fdi_bc_bifurcation(dev
, true);
4494 /* Return which DP Port should be selected for Transcoder DP control */
4496 intel_trans_dp_port_sel(struct intel_crtc
*crtc
)
4498 struct drm_device
*dev
= crtc
->base
.dev
;
4499 struct intel_encoder
*encoder
;
4501 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
4502 if (encoder
->type
== INTEL_OUTPUT_DP
||
4503 encoder
->type
== INTEL_OUTPUT_EDP
)
4504 return enc_to_dig_port(&encoder
->base
)->port
;
4511 * Enable PCH resources required for PCH ports:
4513 * - FDI training & RX/TX
4514 * - update transcoder timings
4515 * - DP transcoding bits
4518 static void ironlake_pch_enable(const struct intel_crtc_state
*crtc_state
)
4520 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4521 struct drm_device
*dev
= crtc
->base
.dev
;
4522 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4523 int pipe
= crtc
->pipe
;
4526 assert_pch_transcoder_disabled(dev_priv
, pipe
);
4528 if (IS_IVYBRIDGE(dev_priv
))
4529 ivybridge_update_fdi_bc_bifurcation(crtc
);
4531 /* Write the TU size bits before fdi link training, so that error
4532 * detection works. */
4533 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
4534 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
4536 /* For PCH output, training FDI link */
4537 dev_priv
->display
.fdi_link_train(crtc
, crtc_state
);
4539 /* We need to program the right clock selection before writing the pixel
4540 * mutliplier into the DPLL. */
4541 if (HAS_PCH_CPT(dev_priv
)) {
4544 temp
= I915_READ(PCH_DPLL_SEL
);
4545 temp
|= TRANS_DPLL_ENABLE(pipe
);
4546 sel
= TRANS_DPLLB_SEL(pipe
);
4547 if (crtc_state
->shared_dpll
==
4548 intel_get_shared_dpll_by_id(dev_priv
, DPLL_ID_PCH_PLL_B
))
4552 I915_WRITE(PCH_DPLL_SEL
, temp
);
4555 /* XXX: pch pll's can be enabled any time before we enable the PCH
4556 * transcoder, and we actually should do this to not upset any PCH
4557 * transcoder that already use the clock when we share it.
4559 * Note that enable_shared_dpll tries to do the right thing, but
4560 * get_shared_dpll unconditionally resets the pll - we need that to have
4561 * the right LVDS enable sequence. */
4562 intel_enable_shared_dpll(crtc
);
4564 /* set transcoder timing, panel must allow it */
4565 assert_panel_unlocked(dev_priv
, pipe
);
4566 ironlake_pch_transcoder_set_timings(crtc
, pipe
);
4568 intel_fdi_normal_train(crtc
);
4570 /* For PCH DP, enable TRANS_DP_CTL */
4571 if (HAS_PCH_CPT(dev_priv
) &&
4572 intel_crtc_has_dp_encoder(crtc_state
)) {
4573 const struct drm_display_mode
*adjusted_mode
=
4574 &crtc_state
->base
.adjusted_mode
;
4575 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
4576 i915_reg_t reg
= TRANS_DP_CTL(pipe
);
4577 temp
= I915_READ(reg
);
4578 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
4579 TRANS_DP_SYNC_MASK
|
4581 temp
|= TRANS_DP_OUTPUT_ENABLE
;
4582 temp
|= bpc
<< 9; /* same format but at 11:9 */
4584 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
4585 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
4586 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
4587 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
4589 switch (intel_trans_dp_port_sel(crtc
)) {
4591 temp
|= TRANS_DP_PORT_SEL_B
;
4594 temp
|= TRANS_DP_PORT_SEL_C
;
4597 temp
|= TRANS_DP_PORT_SEL_D
;
4603 I915_WRITE(reg
, temp
);
4606 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
4609 static void lpt_pch_enable(const struct intel_crtc_state
*crtc_state
)
4611 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4612 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4613 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
4615 assert_pch_transcoder_disabled(dev_priv
, PIPE_A
);
4617 lpt_program_iclkip(crtc
);
4619 /* Set transcoder timing. */
4620 ironlake_pch_transcoder_set_timings(crtc
, PIPE_A
);
4622 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
4625 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
4627 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4628 i915_reg_t dslreg
= PIPEDSL(pipe
);
4631 temp
= I915_READ(dslreg
);
4633 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4634 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4635 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4640 skl_update_scaler(struct intel_crtc_state
*crtc_state
, bool force_detach
,
4641 unsigned int scaler_user
, int *scaler_id
,
4642 int src_w
, int src_h
, int dst_w
, int dst_h
)
4644 struct intel_crtc_scaler_state
*scaler_state
=
4645 &crtc_state
->scaler_state
;
4646 struct intel_crtc
*intel_crtc
=
4647 to_intel_crtc(crtc_state
->base
.crtc
);
4648 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
4649 const struct drm_display_mode
*adjusted_mode
=
4650 &crtc_state
->base
.adjusted_mode
;
4654 * Src coordinates are already rotated by 270 degrees for
4655 * the 90/270 degree plane rotation cases (to match the
4656 * GTT mapping), hence no need to account for rotation here.
4658 need_scaling
= src_w
!= dst_w
|| src_h
!= dst_h
;
4660 if (crtc_state
->ycbcr420
&& scaler_user
== SKL_CRTC_INDEX
)
4661 need_scaling
= true;
4664 * Scaling/fitting not supported in IF-ID mode in GEN9+
4665 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4666 * Once NV12 is enabled, handle it here while allocating scaler
4669 if (INTEL_GEN(dev_priv
) >= 9 && crtc_state
->base
.enable
&&
4670 need_scaling
&& adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4671 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4676 * if plane is being disabled or scaler is no more required or force detach
4677 * - free scaler binded to this plane/crtc
4678 * - in order to do this, update crtc->scaler_usage
4680 * Here scaler state in crtc_state is set free so that
4681 * scaler can be assigned to other user. Actual register
4682 * update to free the scaler is done in plane/panel-fit programming.
4683 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4685 if (force_detach
|| !need_scaling
) {
4686 if (*scaler_id
>= 0) {
4687 scaler_state
->scaler_users
&= ~(1 << scaler_user
);
4688 scaler_state
->scalers
[*scaler_id
].in_use
= 0;
4690 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4691 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4692 intel_crtc
->pipe
, scaler_user
, *scaler_id
,
4693 scaler_state
->scaler_users
);
4700 if (src_w
< SKL_MIN_SRC_W
|| src_h
< SKL_MIN_SRC_H
||
4701 dst_w
< SKL_MIN_DST_W
|| dst_h
< SKL_MIN_DST_H
||
4703 src_w
> SKL_MAX_SRC_W
|| src_h
> SKL_MAX_SRC_H
||
4704 dst_w
> SKL_MAX_DST_W
|| dst_h
> SKL_MAX_DST_H
) {
4705 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4706 "size is out of scaler range\n",
4707 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
);
4711 /* mark this plane as a scaler user in crtc_state */
4712 scaler_state
->scaler_users
|= (1 << scaler_user
);
4713 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4714 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4715 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
,
4716 scaler_state
->scaler_users
);
4722 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4724 * @state: crtc's scaler state
4727 * 0 - scaler_usage updated successfully
4728 * error - requested scaling cannot be supported or other error condition
4730 int skl_update_scaler_crtc(struct intel_crtc_state
*state
)
4732 const struct drm_display_mode
*adjusted_mode
= &state
->base
.adjusted_mode
;
4734 return skl_update_scaler(state
, !state
->base
.active
, SKL_CRTC_INDEX
,
4735 &state
->scaler_state
.scaler_id
,
4736 state
->pipe_src_w
, state
->pipe_src_h
,
4737 adjusted_mode
->crtc_hdisplay
, adjusted_mode
->crtc_vdisplay
);
4741 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4743 * @state: crtc's scaler state
4744 * @plane_state: atomic plane state to update
4747 * 0 - scaler_usage updated successfully
4748 * error - requested scaling cannot be supported or other error condition
4750 static int skl_update_scaler_plane(struct intel_crtc_state
*crtc_state
,
4751 struct intel_plane_state
*plane_state
)
4754 struct intel_plane
*intel_plane
=
4755 to_intel_plane(plane_state
->base
.plane
);
4756 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
4759 bool force_detach
= !fb
|| !plane_state
->base
.visible
;
4761 ret
= skl_update_scaler(crtc_state
, force_detach
,
4762 drm_plane_index(&intel_plane
->base
),
4763 &plane_state
->scaler_id
,
4764 drm_rect_width(&plane_state
->base
.src
) >> 16,
4765 drm_rect_height(&plane_state
->base
.src
) >> 16,
4766 drm_rect_width(&plane_state
->base
.dst
),
4767 drm_rect_height(&plane_state
->base
.dst
));
4769 if (ret
|| plane_state
->scaler_id
< 0)
4772 /* check colorkey */
4773 if (plane_state
->ckey
.flags
!= I915_SET_COLORKEY_NONE
) {
4774 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4775 intel_plane
->base
.base
.id
,
4776 intel_plane
->base
.name
);
4780 /* Check src format */
4781 switch (fb
->format
->format
) {
4782 case DRM_FORMAT_RGB565
:
4783 case DRM_FORMAT_XBGR8888
:
4784 case DRM_FORMAT_XRGB8888
:
4785 case DRM_FORMAT_ABGR8888
:
4786 case DRM_FORMAT_ARGB8888
:
4787 case DRM_FORMAT_XRGB2101010
:
4788 case DRM_FORMAT_XBGR2101010
:
4789 case DRM_FORMAT_YUYV
:
4790 case DRM_FORMAT_YVYU
:
4791 case DRM_FORMAT_UYVY
:
4792 case DRM_FORMAT_VYUY
:
4795 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4796 intel_plane
->base
.base
.id
, intel_plane
->base
.name
,
4797 fb
->base
.id
, fb
->format
->format
);
4804 static void skylake_scaler_disable(struct intel_crtc
*crtc
)
4808 for (i
= 0; i
< crtc
->num_scalers
; i
++)
4809 skl_detach_scaler(crtc
, i
);
4812 static void skylake_pfit_enable(struct intel_crtc
*crtc
)
4814 struct drm_device
*dev
= crtc
->base
.dev
;
4815 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4816 int pipe
= crtc
->pipe
;
4817 struct intel_crtc_scaler_state
*scaler_state
=
4818 &crtc
->config
->scaler_state
;
4820 if (crtc
->config
->pch_pfit
.enabled
) {
4823 if (WARN_ON(crtc
->config
->scaler_state
.scaler_id
< 0))
4826 id
= scaler_state
->scaler_id
;
4827 I915_WRITE(SKL_PS_CTRL(pipe
, id
), PS_SCALER_EN
|
4828 PS_FILTER_MEDIUM
| scaler_state
->scalers
[id
].mode
);
4829 I915_WRITE(SKL_PS_WIN_POS(pipe
, id
), crtc
->config
->pch_pfit
.pos
);
4830 I915_WRITE(SKL_PS_WIN_SZ(pipe
, id
), crtc
->config
->pch_pfit
.size
);
4834 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
4836 struct drm_device
*dev
= crtc
->base
.dev
;
4837 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4838 int pipe
= crtc
->pipe
;
4840 if (crtc
->config
->pch_pfit
.enabled
) {
4841 /* Force use of hard-coded filter coefficients
4842 * as some pre-programmed values are broken,
4845 if (IS_IVYBRIDGE(dev_priv
) || IS_HASWELL(dev_priv
))
4846 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
4847 PF_PIPE_SEL_IVB(pipe
));
4849 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
4850 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4851 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4855 void hsw_enable_ips(struct intel_crtc
*crtc
)
4857 struct drm_device
*dev
= crtc
->base
.dev
;
4858 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4860 if (!crtc
->config
->ips_enabled
)
4864 * We can only enable IPS after we enable a plane and wait for a vblank
4865 * This function is called from post_plane_update, which is run after
4869 assert_plane_enabled(dev_priv
, crtc
->plane
);
4870 if (IS_BROADWELL(dev_priv
)) {
4871 mutex_lock(&dev_priv
->pcu_lock
);
4872 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
,
4873 IPS_ENABLE
| IPS_PCODE_CONTROL
));
4874 mutex_unlock(&dev_priv
->pcu_lock
);
4875 /* Quoting Art Runyan: "its not safe to expect any particular
4876 * value in IPS_CTL bit 31 after enabling IPS through the
4877 * mailbox." Moreover, the mailbox may return a bogus state,
4878 * so we need to just enable it and continue on.
4881 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
4882 /* The bit only becomes 1 in the next vblank, so this wait here
4883 * is essentially intel_wait_for_vblank. If we don't have this
4884 * and don't wait for vblanks until the end of crtc_enable, then
4885 * the HW state readout code will complain that the expected
4886 * IPS_CTL value is not the one we read. */
4887 if (intel_wait_for_register(dev_priv
,
4888 IPS_CTL
, IPS_ENABLE
, IPS_ENABLE
,
4890 DRM_ERROR("Timed out waiting for IPS enable\n");
4894 void hsw_disable_ips(struct intel_crtc
*crtc
)
4896 struct drm_device
*dev
= crtc
->base
.dev
;
4897 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4899 if (!crtc
->config
->ips_enabled
)
4902 assert_plane_enabled(dev_priv
, crtc
->plane
);
4903 if (IS_BROADWELL(dev_priv
)) {
4904 mutex_lock(&dev_priv
->pcu_lock
);
4905 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4906 mutex_unlock(&dev_priv
->pcu_lock
);
4907 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4908 if (intel_wait_for_register(dev_priv
,
4909 IPS_CTL
, IPS_ENABLE
, 0,
4911 DRM_ERROR("Timed out waiting for IPS disable\n");
4913 I915_WRITE(IPS_CTL
, 0);
4914 POSTING_READ(IPS_CTL
);
4917 /* We need to wait for a vblank before we can disable the plane. */
4918 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
4921 static void intel_crtc_dpms_overlay_disable(struct intel_crtc
*intel_crtc
)
4923 if (intel_crtc
->overlay
) {
4924 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4926 mutex_lock(&dev
->struct_mutex
);
4927 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4928 mutex_unlock(&dev
->struct_mutex
);
4931 /* Let userspace switch the overlay on again. In most cases userspace
4932 * has to recompute where to put it anyway.
4937 * intel_post_enable_primary - Perform operations after enabling primary plane
4938 * @crtc: the CRTC whose primary plane was just enabled
4940 * Performs potentially sleeping operations that must be done after the primary
4941 * plane is enabled, such as updating FBC and IPS. Note that this may be
4942 * called due to an explicit primary plane update, or due to an implicit
4943 * re-enable that is caused when a sprite plane is updated to no longer
4944 * completely hide the primary plane.
4947 intel_post_enable_primary(struct drm_crtc
*crtc
)
4949 struct drm_device
*dev
= crtc
->dev
;
4950 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4951 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4952 int pipe
= intel_crtc
->pipe
;
4955 * FIXME IPS should be fine as long as one plane is
4956 * enabled, but in practice it seems to have problems
4957 * when going from primary only to sprite only and vice
4960 hsw_enable_ips(intel_crtc
);
4963 * Gen2 reports pipe underruns whenever all planes are disabled.
4964 * So don't enable underrun reporting before at least some planes
4966 * FIXME: Need to fix the logic to work when we turn off all planes
4967 * but leave the pipe running.
4969 if (IS_GEN2(dev_priv
))
4970 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4972 /* Underruns don't always raise interrupts, so check manually. */
4973 intel_check_cpu_fifo_underruns(dev_priv
);
4974 intel_check_pch_fifo_underruns(dev_priv
);
4977 /* FIXME move all this to pre_plane_update() with proper state tracking */
4979 intel_pre_disable_primary(struct drm_crtc
*crtc
)
4981 struct drm_device
*dev
= crtc
->dev
;
4982 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4983 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4984 int pipe
= intel_crtc
->pipe
;
4987 * Gen2 reports pipe underruns whenever all planes are disabled.
4988 * So diasble underrun reporting before all the planes get disabled.
4989 * FIXME: Need to fix the logic to work when we turn off all planes
4990 * but leave the pipe running.
4992 if (IS_GEN2(dev_priv
))
4993 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4996 * FIXME IPS should be fine as long as one plane is
4997 * enabled, but in practice it seems to have problems
4998 * when going from primary only to sprite only and vice
5001 hsw_disable_ips(intel_crtc
);
5004 /* FIXME get rid of this and use pre_plane_update */
5006 intel_pre_disable_primary_noatomic(struct drm_crtc
*crtc
)
5008 struct drm_device
*dev
= crtc
->dev
;
5009 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5010 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5011 int pipe
= intel_crtc
->pipe
;
5013 intel_pre_disable_primary(crtc
);
5016 * Vblank time updates from the shadow to live plane control register
5017 * are blocked if the memory self-refresh mode is active at that
5018 * moment. So to make sure the plane gets truly disabled, disable
5019 * first the self-refresh mode. The self-refresh enable bit in turn
5020 * will be checked/applied by the HW only at the next frame start
5021 * event which is after the vblank start event, so we need to have a
5022 * wait-for-vblank between disabling the plane and the pipe.
5024 if (HAS_GMCH_DISPLAY(dev_priv
) &&
5025 intel_set_memory_cxsr(dev_priv
, false))
5026 intel_wait_for_vblank(dev_priv
, pipe
);
5029 static void intel_post_plane_update(struct intel_crtc_state
*old_crtc_state
)
5031 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
5032 struct drm_atomic_state
*old_state
= old_crtc_state
->base
.state
;
5033 struct intel_crtc_state
*pipe_config
=
5034 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state
),
5036 struct drm_plane
*primary
= crtc
->base
.primary
;
5037 struct drm_plane_state
*old_pri_state
=
5038 drm_atomic_get_existing_plane_state(old_state
, primary
);
5040 intel_frontbuffer_flip(to_i915(crtc
->base
.dev
), pipe_config
->fb_bits
);
5042 if (pipe_config
->update_wm_post
&& pipe_config
->base
.active
)
5043 intel_update_watermarks(crtc
);
5045 if (old_pri_state
) {
5046 struct intel_plane_state
*primary_state
=
5047 intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state
),
5048 to_intel_plane(primary
));
5049 struct intel_plane_state
*old_primary_state
=
5050 to_intel_plane_state(old_pri_state
);
5052 intel_fbc_post_update(crtc
);
5054 if (primary_state
->base
.visible
&&
5055 (needs_modeset(&pipe_config
->base
) ||
5056 !old_primary_state
->base
.visible
))
5057 intel_post_enable_primary(&crtc
->base
);
5061 static void intel_pre_plane_update(struct intel_crtc_state
*old_crtc_state
,
5062 struct intel_crtc_state
*pipe_config
)
5064 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
5065 struct drm_device
*dev
= crtc
->base
.dev
;
5066 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5067 struct drm_atomic_state
*old_state
= old_crtc_state
->base
.state
;
5068 struct drm_plane
*primary
= crtc
->base
.primary
;
5069 struct drm_plane_state
*old_pri_state
=
5070 drm_atomic_get_existing_plane_state(old_state
, primary
);
5071 bool modeset
= needs_modeset(&pipe_config
->base
);
5072 struct intel_atomic_state
*old_intel_state
=
5073 to_intel_atomic_state(old_state
);
5075 if (old_pri_state
) {
5076 struct intel_plane_state
*primary_state
=
5077 intel_atomic_get_new_plane_state(old_intel_state
,
5078 to_intel_plane(primary
));
5079 struct intel_plane_state
*old_primary_state
=
5080 to_intel_plane_state(old_pri_state
);
5082 intel_fbc_pre_update(crtc
, pipe_config
, primary_state
);
5084 if (old_primary_state
->base
.visible
&&
5085 (modeset
|| !primary_state
->base
.visible
))
5086 intel_pre_disable_primary(&crtc
->base
);
5090 * Vblank time updates from the shadow to live plane control register
5091 * are blocked if the memory self-refresh mode is active at that
5092 * moment. So to make sure the plane gets truly disabled, disable
5093 * first the self-refresh mode. The self-refresh enable bit in turn
5094 * will be checked/applied by the HW only at the next frame start
5095 * event which is after the vblank start event, so we need to have a
5096 * wait-for-vblank between disabling the plane and the pipe.
5098 if (HAS_GMCH_DISPLAY(dev_priv
) && old_crtc_state
->base
.active
&&
5099 pipe_config
->disable_cxsr
&& intel_set_memory_cxsr(dev_priv
, false))
5100 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
5103 * IVB workaround: must disable low power watermarks for at least
5104 * one frame before enabling scaling. LP watermarks can be re-enabled
5105 * when scaling is disabled.
5107 * WaCxSRDisabledForSpriteScaling:ivb
5109 if (pipe_config
->disable_lp_wm
&& ilk_disable_lp_wm(dev
))
5110 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
5113 * If we're doing a modeset, we're done. No need to do any pre-vblank
5114 * watermark programming here.
5116 if (needs_modeset(&pipe_config
->base
))
5120 * For platforms that support atomic watermarks, program the
5121 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5122 * will be the intermediate values that are safe for both pre- and
5123 * post- vblank; when vblank happens, the 'active' values will be set
5124 * to the final 'target' values and we'll do this again to get the
5125 * optimal watermarks. For gen9+ platforms, the values we program here
5126 * will be the final target values which will get automatically latched
5127 * at vblank time; no further programming will be necessary.
5129 * If a platform hasn't been transitioned to atomic watermarks yet,
5130 * we'll continue to update watermarks the old way, if flags tell
5133 if (dev_priv
->display
.initial_watermarks
!= NULL
)
5134 dev_priv
->display
.initial_watermarks(old_intel_state
,
5136 else if (pipe_config
->update_wm_pre
)
5137 intel_update_watermarks(crtc
);
5140 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
, unsigned plane_mask
)
5142 struct drm_device
*dev
= crtc
->dev
;
5143 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5144 struct drm_plane
*p
;
5145 int pipe
= intel_crtc
->pipe
;
5147 intel_crtc_dpms_overlay_disable(intel_crtc
);
5149 drm_for_each_plane_mask(p
, dev
, plane_mask
)
5150 to_intel_plane(p
)->disable_plane(to_intel_plane(p
), intel_crtc
);
5153 * FIXME: Once we grow proper nuclear flip support out of this we need
5154 * to compute the mask of flip planes precisely. For the time being
5155 * consider this a flip to a NULL plane.
5157 intel_frontbuffer_flip(to_i915(dev
), INTEL_FRONTBUFFER_ALL_MASK(pipe
));
5160 static void intel_encoders_pre_pll_enable(struct drm_crtc
*crtc
,
5161 struct intel_crtc_state
*crtc_state
,
5162 struct drm_atomic_state
*old_state
)
5164 struct drm_connector_state
*conn_state
;
5165 struct drm_connector
*conn
;
5168 for_each_new_connector_in_state(old_state
, conn
, conn_state
, i
) {
5169 struct intel_encoder
*encoder
=
5170 to_intel_encoder(conn_state
->best_encoder
);
5172 if (conn_state
->crtc
!= crtc
)
5175 if (encoder
->pre_pll_enable
)
5176 encoder
->pre_pll_enable(encoder
, crtc_state
, conn_state
);
5180 static void intel_encoders_pre_enable(struct drm_crtc
*crtc
,
5181 struct intel_crtc_state
*crtc_state
,
5182 struct drm_atomic_state
*old_state
)
5184 struct drm_connector_state
*conn_state
;
5185 struct drm_connector
*conn
;
5188 for_each_new_connector_in_state(old_state
, conn
, conn_state
, i
) {
5189 struct intel_encoder
*encoder
=
5190 to_intel_encoder(conn_state
->best_encoder
);
5192 if (conn_state
->crtc
!= crtc
)
5195 if (encoder
->pre_enable
)
5196 encoder
->pre_enable(encoder
, crtc_state
, conn_state
);
5200 static void intel_encoders_enable(struct drm_crtc
*crtc
,
5201 struct intel_crtc_state
*crtc_state
,
5202 struct drm_atomic_state
*old_state
)
5204 struct drm_connector_state
*conn_state
;
5205 struct drm_connector
*conn
;
5208 for_each_new_connector_in_state(old_state
, conn
, conn_state
, i
) {
5209 struct intel_encoder
*encoder
=
5210 to_intel_encoder(conn_state
->best_encoder
);
5212 if (conn_state
->crtc
!= crtc
)
5215 encoder
->enable(encoder
, crtc_state
, conn_state
);
5216 intel_opregion_notify_encoder(encoder
, true);
5220 static void intel_encoders_disable(struct drm_crtc
*crtc
,
5221 struct intel_crtc_state
*old_crtc_state
,
5222 struct drm_atomic_state
*old_state
)
5224 struct drm_connector_state
*old_conn_state
;
5225 struct drm_connector
*conn
;
5228 for_each_old_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
5229 struct intel_encoder
*encoder
=
5230 to_intel_encoder(old_conn_state
->best_encoder
);
5232 if (old_conn_state
->crtc
!= crtc
)
5235 intel_opregion_notify_encoder(encoder
, false);
5236 encoder
->disable(encoder
, old_crtc_state
, old_conn_state
);
5240 static void intel_encoders_post_disable(struct drm_crtc
*crtc
,
5241 struct intel_crtc_state
*old_crtc_state
,
5242 struct drm_atomic_state
*old_state
)
5244 struct drm_connector_state
*old_conn_state
;
5245 struct drm_connector
*conn
;
5248 for_each_old_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
5249 struct intel_encoder
*encoder
=
5250 to_intel_encoder(old_conn_state
->best_encoder
);
5252 if (old_conn_state
->crtc
!= crtc
)
5255 if (encoder
->post_disable
)
5256 encoder
->post_disable(encoder
, old_crtc_state
, old_conn_state
);
5260 static void intel_encoders_post_pll_disable(struct drm_crtc
*crtc
,
5261 struct intel_crtc_state
*old_crtc_state
,
5262 struct drm_atomic_state
*old_state
)
5264 struct drm_connector_state
*old_conn_state
;
5265 struct drm_connector
*conn
;
5268 for_each_old_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
5269 struct intel_encoder
*encoder
=
5270 to_intel_encoder(old_conn_state
->best_encoder
);
5272 if (old_conn_state
->crtc
!= crtc
)
5275 if (encoder
->post_pll_disable
)
5276 encoder
->post_pll_disable(encoder
, old_crtc_state
, old_conn_state
);
5280 static void ironlake_crtc_enable(struct intel_crtc_state
*pipe_config
,
5281 struct drm_atomic_state
*old_state
)
5283 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
5284 struct drm_device
*dev
= crtc
->dev
;
5285 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5286 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5287 int pipe
= intel_crtc
->pipe
;
5288 struct intel_atomic_state
*old_intel_state
=
5289 to_intel_atomic_state(old_state
);
5291 if (WARN_ON(intel_crtc
->active
))
5295 * Sometimes spurious CPU pipe underruns happen during FDI
5296 * training, at least with VGA+HDMI cloning. Suppress them.
5298 * On ILK we get an occasional spurious CPU pipe underruns
5299 * between eDP port A enable and vdd enable. Also PCH port
5300 * enable seems to result in the occasional CPU pipe underrun.
5302 * Spurious PCH underruns also occur during PCH enabling.
5304 if (intel_crtc
->config
->has_pch_encoder
|| IS_GEN5(dev_priv
))
5305 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5306 if (intel_crtc
->config
->has_pch_encoder
)
5307 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
5309 if (intel_crtc
->config
->has_pch_encoder
)
5310 intel_prepare_shared_dpll(intel_crtc
);
5312 if (intel_crtc_has_dp_encoder(intel_crtc
->config
))
5313 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5315 intel_set_pipe_timings(intel_crtc
);
5316 intel_set_pipe_src_size(intel_crtc
);
5318 if (intel_crtc
->config
->has_pch_encoder
) {
5319 intel_cpu_transcoder_set_m_n(intel_crtc
,
5320 &intel_crtc
->config
->fdi_m_n
, NULL
);
5323 ironlake_set_pipeconf(crtc
);
5325 intel_crtc
->active
= true;
5327 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
5329 if (intel_crtc
->config
->has_pch_encoder
) {
5330 /* Note: FDI PLL enabling _must_ be done before we enable the
5331 * cpu pipes, hence this is separate from all the other fdi/pch
5333 ironlake_fdi_pll_enable(intel_crtc
);
5335 assert_fdi_tx_disabled(dev_priv
, pipe
);
5336 assert_fdi_rx_disabled(dev_priv
, pipe
);
5339 ironlake_pfit_enable(intel_crtc
);
5342 * On ILK+ LUT must be loaded before the pipe is running but with
5345 intel_color_load_luts(&pipe_config
->base
);
5347 if (dev_priv
->display
.initial_watermarks
!= NULL
)
5348 dev_priv
->display
.initial_watermarks(old_intel_state
, intel_crtc
->config
);
5349 intel_enable_pipe(intel_crtc
);
5351 if (intel_crtc
->config
->has_pch_encoder
)
5352 ironlake_pch_enable(pipe_config
);
5354 assert_vblank_disabled(crtc
);
5355 drm_crtc_vblank_on(crtc
);
5357 intel_encoders_enable(crtc
, pipe_config
, old_state
);
5359 if (HAS_PCH_CPT(dev_priv
))
5360 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
5362 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5363 if (intel_crtc
->config
->has_pch_encoder
)
5364 intel_wait_for_vblank(dev_priv
, pipe
);
5365 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5366 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
5369 /* IPS only exists on ULT machines and is tied to pipe A. */
5370 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
5372 return HAS_IPS(to_i915(crtc
->base
.dev
)) && crtc
->pipe
== PIPE_A
;
5375 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private
*dev_priv
,
5376 enum pipe pipe
, bool apply
)
5378 u32 val
= I915_READ(CLKGATE_DIS_PSL(pipe
));
5379 u32 mask
= DPF_GATING_DIS
| DPF_RAM_GATING_DIS
| DPFR_GATING_DIS
;
5386 I915_WRITE(CLKGATE_DIS_PSL(pipe
), val
);
5389 static void haswell_crtc_enable(struct intel_crtc_state
*pipe_config
,
5390 struct drm_atomic_state
*old_state
)
5392 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
5393 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
5394 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5395 int pipe
= intel_crtc
->pipe
, hsw_workaround_pipe
;
5396 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
5397 struct intel_atomic_state
*old_intel_state
=
5398 to_intel_atomic_state(old_state
);
5399 bool psl_clkgate_wa
;
5401 if (WARN_ON(intel_crtc
->active
))
5404 intel_encoders_pre_pll_enable(crtc
, pipe_config
, old_state
);
5406 if (intel_crtc
->config
->shared_dpll
)
5407 intel_enable_shared_dpll(intel_crtc
);
5409 if (intel_crtc_has_dp_encoder(intel_crtc
->config
))
5410 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5412 if (!transcoder_is_dsi(cpu_transcoder
))
5413 intel_set_pipe_timings(intel_crtc
);
5415 intel_set_pipe_src_size(intel_crtc
);
5417 if (cpu_transcoder
!= TRANSCODER_EDP
&&
5418 !transcoder_is_dsi(cpu_transcoder
)) {
5419 I915_WRITE(PIPE_MULT(cpu_transcoder
),
5420 intel_crtc
->config
->pixel_multiplier
- 1);
5423 if (intel_crtc
->config
->has_pch_encoder
) {
5424 intel_cpu_transcoder_set_m_n(intel_crtc
,
5425 &intel_crtc
->config
->fdi_m_n
, NULL
);
5428 if (!transcoder_is_dsi(cpu_transcoder
))
5429 haswell_set_pipeconf(crtc
);
5431 haswell_set_pipemisc(crtc
);
5433 intel_color_set_csc(&pipe_config
->base
);
5435 intel_crtc
->active
= true;
5437 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
5439 if (!transcoder_is_dsi(cpu_transcoder
))
5440 intel_ddi_enable_pipe_clock(pipe_config
);
5442 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
5443 psl_clkgate_wa
= (IS_GEMINILAKE(dev_priv
) || IS_CANNONLAKE(dev_priv
)) &&
5444 intel_crtc
->config
->pch_pfit
.enabled
;
5446 glk_pipe_scaler_clock_gating_wa(dev_priv
, pipe
, true);
5448 if (INTEL_GEN(dev_priv
) >= 9)
5449 skylake_pfit_enable(intel_crtc
);
5451 ironlake_pfit_enable(intel_crtc
);
5454 * On ILK+ LUT must be loaded before the pipe is running but with
5457 intel_color_load_luts(&pipe_config
->base
);
5459 intel_ddi_set_pipe_settings(pipe_config
);
5460 if (!transcoder_is_dsi(cpu_transcoder
))
5461 intel_ddi_enable_transcoder_func(pipe_config
);
5463 if (dev_priv
->display
.initial_watermarks
!= NULL
)
5464 dev_priv
->display
.initial_watermarks(old_intel_state
, pipe_config
);
5466 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5467 if (!transcoder_is_dsi(cpu_transcoder
))
5468 intel_enable_pipe(intel_crtc
);
5470 if (intel_crtc
->config
->has_pch_encoder
)
5471 lpt_pch_enable(pipe_config
);
5473 if (intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_DP_MST
))
5474 intel_ddi_set_vc_payload_alloc(pipe_config
, true);
5476 assert_vblank_disabled(crtc
);
5477 drm_crtc_vblank_on(crtc
);
5479 intel_encoders_enable(crtc
, pipe_config
, old_state
);
5481 if (psl_clkgate_wa
) {
5482 intel_wait_for_vblank(dev_priv
, pipe
);
5483 glk_pipe_scaler_clock_gating_wa(dev_priv
, pipe
, false);
5486 /* If we change the relative order between pipe/planes enabling, we need
5487 * to change the workaround. */
5488 hsw_workaround_pipe
= pipe_config
->hsw_workaround_pipe
;
5489 if (IS_HASWELL(dev_priv
) && hsw_workaround_pipe
!= INVALID_PIPE
) {
5490 intel_wait_for_vblank(dev_priv
, hsw_workaround_pipe
);
5491 intel_wait_for_vblank(dev_priv
, hsw_workaround_pipe
);
5495 static void ironlake_pfit_disable(struct intel_crtc
*crtc
, bool force
)
5497 struct drm_device
*dev
= crtc
->base
.dev
;
5498 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5499 int pipe
= crtc
->pipe
;
5501 /* To avoid upsetting the power well on haswell only disable the pfit if
5502 * it's in use. The hw state code will make sure we get this right. */
5503 if (force
|| crtc
->config
->pch_pfit
.enabled
) {
5504 I915_WRITE(PF_CTL(pipe
), 0);
5505 I915_WRITE(PF_WIN_POS(pipe
), 0);
5506 I915_WRITE(PF_WIN_SZ(pipe
), 0);
5510 static void ironlake_crtc_disable(struct intel_crtc_state
*old_crtc_state
,
5511 struct drm_atomic_state
*old_state
)
5513 struct drm_crtc
*crtc
= old_crtc_state
->base
.crtc
;
5514 struct drm_device
*dev
= crtc
->dev
;
5515 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5516 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5517 int pipe
= intel_crtc
->pipe
;
5520 * Sometimes spurious CPU pipe underruns happen when the
5521 * pipe is already disabled, but FDI RX/TX is still enabled.
5522 * Happens at least with VGA+HDMI cloning. Suppress them.
5524 if (intel_crtc
->config
->has_pch_encoder
) {
5525 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5526 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
5529 intel_encoders_disable(crtc
, old_crtc_state
, old_state
);
5531 drm_crtc_vblank_off(crtc
);
5532 assert_vblank_disabled(crtc
);
5534 intel_disable_pipe(intel_crtc
);
5536 ironlake_pfit_disable(intel_crtc
, false);
5538 if (intel_crtc
->config
->has_pch_encoder
)
5539 ironlake_fdi_disable(crtc
);
5541 intel_encoders_post_disable(crtc
, old_crtc_state
, old_state
);
5543 if (intel_crtc
->config
->has_pch_encoder
) {
5544 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
5546 if (HAS_PCH_CPT(dev_priv
)) {
5550 /* disable TRANS_DP_CTL */
5551 reg
= TRANS_DP_CTL(pipe
);
5552 temp
= I915_READ(reg
);
5553 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
5554 TRANS_DP_PORT_SEL_MASK
);
5555 temp
|= TRANS_DP_PORT_SEL_NONE
;
5556 I915_WRITE(reg
, temp
);
5558 /* disable DPLL_SEL */
5559 temp
= I915_READ(PCH_DPLL_SEL
);
5560 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
5561 I915_WRITE(PCH_DPLL_SEL
, temp
);
5564 ironlake_fdi_pll_disable(intel_crtc
);
5567 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5568 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
5571 static void haswell_crtc_disable(struct intel_crtc_state
*old_crtc_state
,
5572 struct drm_atomic_state
*old_state
)
5574 struct drm_crtc
*crtc
= old_crtc_state
->base
.crtc
;
5575 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
5576 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5577 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
5579 intel_encoders_disable(crtc
, old_crtc_state
, old_state
);
5581 drm_crtc_vblank_off(crtc
);
5582 assert_vblank_disabled(crtc
);
5584 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5585 if (!transcoder_is_dsi(cpu_transcoder
))
5586 intel_disable_pipe(intel_crtc
);
5588 if (intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_DP_MST
))
5589 intel_ddi_set_vc_payload_alloc(intel_crtc
->config
, false);
5591 if (!transcoder_is_dsi(cpu_transcoder
))
5592 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
5594 if (INTEL_GEN(dev_priv
) >= 9)
5595 skylake_scaler_disable(intel_crtc
);
5597 ironlake_pfit_disable(intel_crtc
, false);
5599 if (!transcoder_is_dsi(cpu_transcoder
))
5600 intel_ddi_disable_pipe_clock(intel_crtc
->config
);
5602 intel_encoders_post_disable(crtc
, old_crtc_state
, old_state
);
5605 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
5607 struct drm_device
*dev
= crtc
->base
.dev
;
5608 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5609 struct intel_crtc_state
*pipe_config
= crtc
->config
;
5611 if (!pipe_config
->gmch_pfit
.control
)
5615 * The panel fitter should only be adjusted whilst the pipe is disabled,
5616 * according to register description and PRM.
5618 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
5619 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5621 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
5622 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
5624 /* Border color in case we don't scale up to the full screen. Black by
5625 * default, change to something else for debugging. */
5626 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
5629 enum intel_display_power_domain
intel_port_to_power_domain(enum port port
)
5633 return POWER_DOMAIN_PORT_DDI_A_LANES
;
5635 return POWER_DOMAIN_PORT_DDI_B_LANES
;
5637 return POWER_DOMAIN_PORT_DDI_C_LANES
;
5639 return POWER_DOMAIN_PORT_DDI_D_LANES
;
5641 return POWER_DOMAIN_PORT_DDI_E_LANES
;
5644 return POWER_DOMAIN_PORT_OTHER
;
5648 static u64
get_crtc_power_domains(struct drm_crtc
*crtc
,
5649 struct intel_crtc_state
*crtc_state
)
5651 struct drm_device
*dev
= crtc
->dev
;
5652 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5653 struct drm_encoder
*encoder
;
5654 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5655 enum pipe pipe
= intel_crtc
->pipe
;
5657 enum transcoder transcoder
= crtc_state
->cpu_transcoder
;
5659 if (!crtc_state
->base
.active
)
5662 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
5663 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
5664 if (crtc_state
->pch_pfit
.enabled
||
5665 crtc_state
->pch_pfit
.force_thru
)
5666 mask
|= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
5668 drm_for_each_encoder_mask(encoder
, dev
, crtc_state
->base
.encoder_mask
) {
5669 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
5671 mask
|= BIT_ULL(intel_encoder
->power_domain
);
5674 if (HAS_DDI(dev_priv
) && crtc_state
->has_audio
)
5675 mask
|= BIT(POWER_DOMAIN_AUDIO
);
5677 if (crtc_state
->shared_dpll
)
5678 mask
|= BIT_ULL(POWER_DOMAIN_PLLS
);
5684 modeset_get_crtc_power_domains(struct drm_crtc
*crtc
,
5685 struct intel_crtc_state
*crtc_state
)
5687 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
5688 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5689 enum intel_display_power_domain domain
;
5690 u64 domains
, new_domains
, old_domains
;
5692 old_domains
= intel_crtc
->enabled_power_domains
;
5693 intel_crtc
->enabled_power_domains
= new_domains
=
5694 get_crtc_power_domains(crtc
, crtc_state
);
5696 domains
= new_domains
& ~old_domains
;
5698 for_each_power_domain(domain
, domains
)
5699 intel_display_power_get(dev_priv
, domain
);
5701 return old_domains
& ~new_domains
;
5704 static void modeset_put_power_domains(struct drm_i915_private
*dev_priv
,
5707 enum intel_display_power_domain domain
;
5709 for_each_power_domain(domain
, domains
)
5710 intel_display_power_put(dev_priv
, domain
);
5713 static void valleyview_crtc_enable(struct intel_crtc_state
*pipe_config
,
5714 struct drm_atomic_state
*old_state
)
5716 struct intel_atomic_state
*old_intel_state
=
5717 to_intel_atomic_state(old_state
);
5718 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
5719 struct drm_device
*dev
= crtc
->dev
;
5720 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5721 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5722 int pipe
= intel_crtc
->pipe
;
5724 if (WARN_ON(intel_crtc
->active
))
5727 if (intel_crtc_has_dp_encoder(intel_crtc
->config
))
5728 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5730 intel_set_pipe_timings(intel_crtc
);
5731 intel_set_pipe_src_size(intel_crtc
);
5733 if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_B
) {
5734 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5736 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
5737 I915_WRITE(CHV_CANVAS(pipe
), 0);
5740 i9xx_set_pipeconf(intel_crtc
);
5742 intel_crtc
->active
= true;
5744 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5746 intel_encoders_pre_pll_enable(crtc
, pipe_config
, old_state
);
5748 if (IS_CHERRYVIEW(dev_priv
)) {
5749 chv_prepare_pll(intel_crtc
, intel_crtc
->config
);
5750 chv_enable_pll(intel_crtc
, intel_crtc
->config
);
5752 vlv_prepare_pll(intel_crtc
, intel_crtc
->config
);
5753 vlv_enable_pll(intel_crtc
, intel_crtc
->config
);
5756 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
5758 i9xx_pfit_enable(intel_crtc
);
5760 intel_color_load_luts(&pipe_config
->base
);
5762 dev_priv
->display
.initial_watermarks(old_intel_state
,
5764 intel_enable_pipe(intel_crtc
);
5766 assert_vblank_disabled(crtc
);
5767 drm_crtc_vblank_on(crtc
);
5769 intel_encoders_enable(crtc
, pipe_config
, old_state
);
5772 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
5774 struct drm_device
*dev
= crtc
->base
.dev
;
5775 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5777 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp0
);
5778 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp1
);
5781 static void i9xx_crtc_enable(struct intel_crtc_state
*pipe_config
,
5782 struct drm_atomic_state
*old_state
)
5784 struct intel_atomic_state
*old_intel_state
=
5785 to_intel_atomic_state(old_state
);
5786 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
5787 struct drm_device
*dev
= crtc
->dev
;
5788 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5789 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5790 enum pipe pipe
= intel_crtc
->pipe
;
5792 if (WARN_ON(intel_crtc
->active
))
5795 i9xx_set_pll_dividers(intel_crtc
);
5797 if (intel_crtc_has_dp_encoder(intel_crtc
->config
))
5798 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5800 intel_set_pipe_timings(intel_crtc
);
5801 intel_set_pipe_src_size(intel_crtc
);
5803 i9xx_set_pipeconf(intel_crtc
);
5805 intel_crtc
->active
= true;
5807 if (!IS_GEN2(dev_priv
))
5808 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5810 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
5812 i9xx_enable_pll(intel_crtc
, pipe_config
);
5814 i9xx_pfit_enable(intel_crtc
);
5816 intel_color_load_luts(&pipe_config
->base
);
5818 if (dev_priv
->display
.initial_watermarks
!= NULL
)
5819 dev_priv
->display
.initial_watermarks(old_intel_state
,
5820 intel_crtc
->config
);
5822 intel_update_watermarks(intel_crtc
);
5823 intel_enable_pipe(intel_crtc
);
5825 assert_vblank_disabled(crtc
);
5826 drm_crtc_vblank_on(crtc
);
5828 intel_encoders_enable(crtc
, pipe_config
, old_state
);
5831 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
5833 struct drm_device
*dev
= crtc
->base
.dev
;
5834 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5836 if (!crtc
->config
->gmch_pfit
.control
)
5839 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5841 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5842 I915_READ(PFIT_CONTROL
));
5843 I915_WRITE(PFIT_CONTROL
, 0);
5846 static void i9xx_crtc_disable(struct intel_crtc_state
*old_crtc_state
,
5847 struct drm_atomic_state
*old_state
)
5849 struct drm_crtc
*crtc
= old_crtc_state
->base
.crtc
;
5850 struct drm_device
*dev
= crtc
->dev
;
5851 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5852 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5853 int pipe
= intel_crtc
->pipe
;
5856 * On gen2 planes are double buffered but the pipe isn't, so we must
5857 * wait for planes to fully turn off before disabling the pipe.
5859 if (IS_GEN2(dev_priv
))
5860 intel_wait_for_vblank(dev_priv
, pipe
);
5862 intel_encoders_disable(crtc
, old_crtc_state
, old_state
);
5864 drm_crtc_vblank_off(crtc
);
5865 assert_vblank_disabled(crtc
);
5867 intel_disable_pipe(intel_crtc
);
5869 i9xx_pfit_disable(intel_crtc
);
5871 intel_encoders_post_disable(crtc
, old_crtc_state
, old_state
);
5873 if (!intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_DSI
)) {
5874 if (IS_CHERRYVIEW(dev_priv
))
5875 chv_disable_pll(dev_priv
, pipe
);
5876 else if (IS_VALLEYVIEW(dev_priv
))
5877 vlv_disable_pll(dev_priv
, pipe
);
5879 i9xx_disable_pll(intel_crtc
);
5882 intel_encoders_post_pll_disable(crtc
, old_crtc_state
, old_state
);
5884 if (!IS_GEN2(dev_priv
))
5885 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5887 if (!dev_priv
->display
.initial_watermarks
)
5888 intel_update_watermarks(intel_crtc
);
5890 /* clock the pipe down to 640x480@60 to potentially save power */
5891 if (IS_I830(dev_priv
))
5892 i830_enable_pipe(dev_priv
, pipe
);
5895 static void intel_crtc_disable_noatomic(struct drm_crtc
*crtc
,
5896 struct drm_modeset_acquire_ctx
*ctx
)
5898 struct intel_encoder
*encoder
;
5899 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5900 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
5901 enum intel_display_power_domain domain
;
5903 struct drm_atomic_state
*state
;
5904 struct intel_crtc_state
*crtc_state
;
5907 if (!intel_crtc
->active
)
5910 if (crtc
->primary
->state
->visible
) {
5911 intel_pre_disable_primary_noatomic(crtc
);
5913 intel_crtc_disable_planes(crtc
, 1 << drm_plane_index(crtc
->primary
));
5914 crtc
->primary
->state
->visible
= false;
5917 state
= drm_atomic_state_alloc(crtc
->dev
);
5919 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5920 crtc
->base
.id
, crtc
->name
);
5924 state
->acquire_ctx
= ctx
;
5926 /* Everything's already locked, -EDEADLK can't happen. */
5927 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
5928 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
5930 WARN_ON(IS_ERR(crtc_state
) || ret
);
5932 dev_priv
->display
.crtc_disable(crtc_state
, state
);
5934 drm_atomic_state_put(state
);
5936 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5937 crtc
->base
.id
, crtc
->name
);
5939 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->state
, NULL
) < 0);
5940 crtc
->state
->active
= false;
5941 intel_crtc
->active
= false;
5942 crtc
->enabled
= false;
5943 crtc
->state
->connector_mask
= 0;
5944 crtc
->state
->encoder_mask
= 0;
5946 for_each_encoder_on_crtc(crtc
->dev
, crtc
, encoder
)
5947 encoder
->base
.crtc
= NULL
;
5949 intel_fbc_disable(intel_crtc
);
5950 intel_update_watermarks(intel_crtc
);
5951 intel_disable_shared_dpll(intel_crtc
);
5953 domains
= intel_crtc
->enabled_power_domains
;
5954 for_each_power_domain(domain
, domains
)
5955 intel_display_power_put(dev_priv
, domain
);
5956 intel_crtc
->enabled_power_domains
= 0;
5958 dev_priv
->active_crtcs
&= ~(1 << intel_crtc
->pipe
);
5959 dev_priv
->min_cdclk
[intel_crtc
->pipe
] = 0;
5963 * turn all crtc's off, but do not adjust state
5964 * This has to be paired with a call to intel_modeset_setup_hw_state.
5966 int intel_display_suspend(struct drm_device
*dev
)
5968 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5969 struct drm_atomic_state
*state
;
5972 state
= drm_atomic_helper_suspend(dev
);
5973 ret
= PTR_ERR_OR_ZERO(state
);
5975 DRM_ERROR("Suspending crtc's failed with %i\n", ret
);
5977 dev_priv
->modeset_restore_state
= state
;
5981 void intel_encoder_destroy(struct drm_encoder
*encoder
)
5983 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
5985 drm_encoder_cleanup(encoder
);
5986 kfree(intel_encoder
);
5989 /* Cross check the actual hw state with our own modeset state tracking (and it's
5990 * internal consistency). */
5991 static void intel_connector_verify_state(struct drm_crtc_state
*crtc_state
,
5992 struct drm_connector_state
*conn_state
)
5994 struct intel_connector
*connector
= to_intel_connector(conn_state
->connector
);
5996 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5997 connector
->base
.base
.id
,
5998 connector
->base
.name
);
6000 if (connector
->get_hw_state(connector
)) {
6001 struct intel_encoder
*encoder
= connector
->encoder
;
6003 I915_STATE_WARN(!crtc_state
,
6004 "connector enabled without attached crtc\n");
6009 I915_STATE_WARN(!crtc_state
->active
,
6010 "connector is active, but attached crtc isn't\n");
6012 if (!encoder
|| encoder
->type
== INTEL_OUTPUT_DP_MST
)
6015 I915_STATE_WARN(conn_state
->best_encoder
!= &encoder
->base
,
6016 "atomic encoder doesn't match attached encoder\n");
6018 I915_STATE_WARN(conn_state
->crtc
!= encoder
->base
.crtc
,
6019 "attached encoder crtc differs from connector crtc\n");
6021 I915_STATE_WARN(crtc_state
&& crtc_state
->active
,
6022 "attached crtc is active, but connector isn't\n");
6023 I915_STATE_WARN(!crtc_state
&& conn_state
->best_encoder
,
6024 "best encoder set without crtc!\n");
6028 int intel_connector_init(struct intel_connector
*connector
)
6030 struct intel_digital_connector_state
*conn_state
;
6033 * Allocate enough memory to hold intel_digital_connector_state,
6034 * This might be a few bytes too many, but for connectors that don't
6035 * need it we'll free the state and allocate a smaller one on the first
6036 * succesful commit anyway.
6038 conn_state
= kzalloc(sizeof(*conn_state
), GFP_KERNEL
);
6042 __drm_atomic_helper_connector_reset(&connector
->base
,
6048 struct intel_connector
*intel_connector_alloc(void)
6050 struct intel_connector
*connector
;
6052 connector
= kzalloc(sizeof *connector
, GFP_KERNEL
);
6056 if (intel_connector_init(connector
) < 0) {
6065 * Free the bits allocated by intel_connector_alloc.
6066 * This should only be used after intel_connector_alloc has returned
6067 * successfully, and before drm_connector_init returns successfully.
6068 * Otherwise the destroy callbacks for the connector and the state should
6069 * take care of proper cleanup/free
6071 void intel_connector_free(struct intel_connector
*connector
)
6073 kfree(to_intel_digital_connector_state(connector
->base
.state
));
6077 /* Simple connector->get_hw_state implementation for encoders that support only
6078 * one connector and no cloning and hence the encoder state determines the state
6079 * of the connector. */
6080 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
6083 struct intel_encoder
*encoder
= connector
->encoder
;
6085 return encoder
->get_hw_state(encoder
, &pipe
);
6088 static int pipe_required_fdi_lanes(struct intel_crtc_state
*crtc_state
)
6090 if (crtc_state
->base
.enable
&& crtc_state
->has_pch_encoder
)
6091 return crtc_state
->fdi_lanes
;
6096 static int ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
6097 struct intel_crtc_state
*pipe_config
)
6099 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6100 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
6101 struct intel_crtc
*other_crtc
;
6102 struct intel_crtc_state
*other_crtc_state
;
6104 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6105 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6106 if (pipe_config
->fdi_lanes
> 4) {
6107 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6108 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6112 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
6113 if (pipe_config
->fdi_lanes
> 2) {
6114 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6115 pipe_config
->fdi_lanes
);
6122 if (INTEL_INFO(dev_priv
)->num_pipes
== 2)
6125 /* Ivybridge 3 pipe is really complicated */
6130 if (pipe_config
->fdi_lanes
<= 2)
6133 other_crtc
= intel_get_crtc_for_pipe(dev_priv
, PIPE_C
);
6135 intel_atomic_get_crtc_state(state
, other_crtc
);
6136 if (IS_ERR(other_crtc_state
))
6137 return PTR_ERR(other_crtc_state
);
6139 if (pipe_required_fdi_lanes(other_crtc_state
) > 0) {
6140 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6141 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6146 if (pipe_config
->fdi_lanes
> 2) {
6147 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6148 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6152 other_crtc
= intel_get_crtc_for_pipe(dev_priv
, PIPE_B
);
6154 intel_atomic_get_crtc_state(state
, other_crtc
);
6155 if (IS_ERR(other_crtc_state
))
6156 return PTR_ERR(other_crtc_state
);
6158 if (pipe_required_fdi_lanes(other_crtc_state
) > 2) {
6159 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6169 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
6170 struct intel_crtc_state
*pipe_config
)
6172 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6173 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6174 int lane
, link_bw
, fdi_dotclock
, ret
;
6175 bool needs_recompute
= false;
6178 /* FDI is a binary signal running at ~2.7GHz, encoding
6179 * each output octet as 10 bits. The actual frequency
6180 * is stored as a divider into a 100MHz clock, and the
6181 * mode pixel clock is stored in units of 1KHz.
6182 * Hence the bw of each lane in terms of the mode signal
6185 link_bw
= intel_fdi_link_freq(to_i915(dev
), pipe_config
);
6187 fdi_dotclock
= adjusted_mode
->crtc_clock
;
6189 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
6190 pipe_config
->pipe_bpp
);
6192 pipe_config
->fdi_lanes
= lane
;
6194 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
6195 link_bw
, &pipe_config
->fdi_m_n
, false);
6197 ret
= ironlake_check_fdi_lanes(dev
, intel_crtc
->pipe
, pipe_config
);
6198 if (ret
== -EINVAL
&& pipe_config
->pipe_bpp
> 6*3) {
6199 pipe_config
->pipe_bpp
-= 2*3;
6200 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6201 pipe_config
->pipe_bpp
);
6202 needs_recompute
= true;
6203 pipe_config
->bw_constrained
= true;
6208 if (needs_recompute
)
6214 static bool pipe_config_supports_ips(struct drm_i915_private
*dev_priv
,
6215 struct intel_crtc_state
*pipe_config
)
6217 if (pipe_config
->ips_force_disable
)
6220 if (pipe_config
->pipe_bpp
> 24)
6223 /* HSW can handle pixel rate up to cdclk? */
6224 if (IS_HASWELL(dev_priv
))
6228 * We compare against max which means we must take
6229 * the increased cdclk requirement into account when
6230 * calculating the new cdclk.
6232 * Should measure whether using a lower cdclk w/o IPS
6234 return pipe_config
->pixel_rate
<=
6235 dev_priv
->max_cdclk_freq
* 95 / 100;
6238 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
6239 struct intel_crtc_state
*pipe_config
)
6241 struct drm_device
*dev
= crtc
->base
.dev
;
6242 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6244 pipe_config
->ips_enabled
= i915_modparams
.enable_ips
&&
6245 hsw_crtc_supports_ips(crtc
) &&
6246 pipe_config_supports_ips(dev_priv
, pipe_config
);
6249 static bool intel_crtc_supports_double_wide(const struct intel_crtc
*crtc
)
6251 const struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6253 /* GDG double wide on either pipe, otherwise pipe A only */
6254 return INTEL_INFO(dev_priv
)->gen
< 4 &&
6255 (crtc
->pipe
== PIPE_A
|| IS_I915G(dev_priv
));
6258 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state
*pipe_config
)
6260 uint32_t pixel_rate
;
6262 pixel_rate
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
6265 * We only use IF-ID interlacing. If we ever use
6266 * PF-ID we'll need to adjust the pixel_rate here.
6269 if (pipe_config
->pch_pfit
.enabled
) {
6270 uint64_t pipe_w
, pipe_h
, pfit_w
, pfit_h
;
6271 uint32_t pfit_size
= pipe_config
->pch_pfit
.size
;
6273 pipe_w
= pipe_config
->pipe_src_w
;
6274 pipe_h
= pipe_config
->pipe_src_h
;
6276 pfit_w
= (pfit_size
>> 16) & 0xFFFF;
6277 pfit_h
= pfit_size
& 0xFFFF;
6278 if (pipe_w
< pfit_w
)
6280 if (pipe_h
< pfit_h
)
6283 if (WARN_ON(!pfit_w
|| !pfit_h
))
6286 pixel_rate
= div_u64((uint64_t) pixel_rate
* pipe_w
* pipe_h
,
6293 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state
*crtc_state
)
6295 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
6297 if (HAS_GMCH_DISPLAY(dev_priv
))
6298 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6299 crtc_state
->pixel_rate
=
6300 crtc_state
->base
.adjusted_mode
.crtc_clock
;
6302 crtc_state
->pixel_rate
=
6303 ilk_pipe_pixel_rate(crtc_state
);
6306 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
6307 struct intel_crtc_state
*pipe_config
)
6309 struct drm_device
*dev
= crtc
->base
.dev
;
6310 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6311 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6312 int clock_limit
= dev_priv
->max_dotclk_freq
;
6314 if (INTEL_GEN(dev_priv
) < 4) {
6315 clock_limit
= dev_priv
->max_cdclk_freq
* 9 / 10;
6318 * Enable double wide mode when the dot clock
6319 * is > 90% of the (display) core speed.
6321 if (intel_crtc_supports_double_wide(crtc
) &&
6322 adjusted_mode
->crtc_clock
> clock_limit
) {
6323 clock_limit
= dev_priv
->max_dotclk_freq
;
6324 pipe_config
->double_wide
= true;
6328 if (adjusted_mode
->crtc_clock
> clock_limit
) {
6329 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6330 adjusted_mode
->crtc_clock
, clock_limit
,
6331 yesno(pipe_config
->double_wide
));
6335 if (pipe_config
->ycbcr420
&& pipe_config
->base
.ctm
) {
6337 * There is only one pipe CSC unit per pipe, and we need that
6338 * for output conversion from RGB->YCBCR. So if CTM is already
6339 * applied we can't support YCBCR420 output.
6341 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
6346 * Pipe horizontal size must be even in:
6348 * - LVDS dual channel mode
6349 * - Double wide pipe
6351 if ((intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_LVDS
) &&
6352 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
6353 pipe_config
->pipe_src_w
&= ~1;
6355 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6356 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6358 if ((INTEL_GEN(dev_priv
) > 4 || IS_G4X(dev_priv
)) &&
6359 adjusted_mode
->crtc_hsync_start
== adjusted_mode
->crtc_hdisplay
)
6362 intel_crtc_compute_pixel_rate(pipe_config
);
6364 if (HAS_IPS(dev_priv
))
6365 hsw_compute_ips_config(crtc
, pipe_config
);
6367 if (pipe_config
->has_pch_encoder
)
6368 return ironlake_fdi_compute_config(crtc
, pipe_config
);
6374 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
6376 while (*num
> DATA_LINK_M_N_MASK
||
6377 *den
> DATA_LINK_M_N_MASK
) {
6383 static void compute_m_n(unsigned int m
, unsigned int n
,
6384 uint32_t *ret_m
, uint32_t *ret_n
,
6388 * Reduce M/N as much as possible without loss in precision. Several DP
6389 * dongles in particular seem to be fussy about too large *link* M/N
6390 * values. The passed in values are more likely to have the least
6391 * significant bits zero than M after rounding below, so do this first.
6394 while ((m
& 1) == 0 && (n
& 1) == 0) {
6400 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
6401 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
6402 intel_reduce_m_n_ratio(ret_m
, ret_n
);
6406 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
6407 int pixel_clock
, int link_clock
,
6408 struct intel_link_m_n
*m_n
,
6413 compute_m_n(bits_per_pixel
* pixel_clock
,
6414 link_clock
* nlanes
* 8,
6415 &m_n
->gmch_m
, &m_n
->gmch_n
,
6418 compute_m_n(pixel_clock
, link_clock
,
6419 &m_n
->link_m
, &m_n
->link_n
,
6423 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
6425 if (i915_modparams
.panel_use_ssc
>= 0)
6426 return i915_modparams
.panel_use_ssc
!= 0;
6427 return dev_priv
->vbt
.lvds_use_ssc
6428 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
6431 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
6433 return (1 << dpll
->n
) << 16 | dpll
->m2
;
6436 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
6438 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
6441 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
6442 struct intel_crtc_state
*crtc_state
,
6443 struct dpll
*reduced_clock
)
6445 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6448 if (IS_PINEVIEW(dev_priv
)) {
6449 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
6451 fp2
= pnv_dpll_compute_fp(reduced_clock
);
6453 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
6455 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
6458 crtc_state
->dpll_hw_state
.fp0
= fp
;
6460 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
6462 crtc_state
->dpll_hw_state
.fp1
= fp2
;
6464 crtc_state
->dpll_hw_state
.fp1
= fp
;
6468 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
6474 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6475 * and set it to a reasonable value instead.
6477 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
6478 reg_val
&= 0xffffff00;
6479 reg_val
|= 0x00000030;
6480 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
6482 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
6483 reg_val
&= 0x00ffffff;
6484 reg_val
|= 0x8c000000;
6485 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
6487 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
6488 reg_val
&= 0xffffff00;
6489 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
6491 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
6492 reg_val
&= 0x00ffffff;
6493 reg_val
|= 0xb0000000;
6494 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
6497 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
6498 struct intel_link_m_n
*m_n
)
6500 struct drm_device
*dev
= crtc
->base
.dev
;
6501 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6502 int pipe
= crtc
->pipe
;
6504 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
6505 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
6506 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
6507 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
6510 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
6511 struct intel_link_m_n
*m_n
,
6512 struct intel_link_m_n
*m2_n2
)
6514 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6515 int pipe
= crtc
->pipe
;
6516 enum transcoder transcoder
= crtc
->config
->cpu_transcoder
;
6518 if (INTEL_GEN(dev_priv
) >= 5) {
6519 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
6520 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
6521 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
6522 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
6523 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6524 * for gen < 8) and if DRRS is supported (to make sure the
6525 * registers are not unnecessarily accessed).
6527 if (m2_n2
&& (IS_CHERRYVIEW(dev_priv
) ||
6528 INTEL_GEN(dev_priv
) < 8) && crtc
->config
->has_drrs
) {
6529 I915_WRITE(PIPE_DATA_M2(transcoder
),
6530 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
6531 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
6532 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
6533 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
6536 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
6537 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
6538 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
6539 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
6543 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
)
6545 struct intel_link_m_n
*dp_m_n
, *dp_m2_n2
= NULL
;
6548 dp_m_n
= &crtc
->config
->dp_m_n
;
6549 dp_m2_n2
= &crtc
->config
->dp_m2_n2
;
6550 } else if (m_n
== M2_N2
) {
6553 * M2_N2 registers are not supported. Hence m2_n2 divider value
6554 * needs to be programmed into M1_N1.
6556 dp_m_n
= &crtc
->config
->dp_m2_n2
;
6558 DRM_ERROR("Unsupported divider value\n");
6562 if (crtc
->config
->has_pch_encoder
)
6563 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
->dp_m_n
);
6565 intel_cpu_transcoder_set_m_n(crtc
, dp_m_n
, dp_m2_n2
);
6568 static void vlv_compute_dpll(struct intel_crtc
*crtc
,
6569 struct intel_crtc_state
*pipe_config
)
6571 pipe_config
->dpll_hw_state
.dpll
= DPLL_INTEGRATED_REF_CLK_VLV
|
6572 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
6573 if (crtc
->pipe
!= PIPE_A
)
6574 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
6576 /* DPLL not used with DSI, but still need the rest set up */
6577 if (!intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_DSI
))
6578 pipe_config
->dpll_hw_state
.dpll
|= DPLL_VCO_ENABLE
|
6579 DPLL_EXT_BUFFER_ENABLE_VLV
;
6581 pipe_config
->dpll_hw_state
.dpll_md
=
6582 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6585 static void chv_compute_dpll(struct intel_crtc
*crtc
,
6586 struct intel_crtc_state
*pipe_config
)
6588 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLK_CHV
|
6589 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
6590 if (crtc
->pipe
!= PIPE_A
)
6591 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
6593 /* DPLL not used with DSI, but still need the rest set up */
6594 if (!intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_DSI
))
6595 pipe_config
->dpll_hw_state
.dpll
|= DPLL_VCO_ENABLE
;
6597 pipe_config
->dpll_hw_state
.dpll_md
=
6598 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6601 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
6602 const struct intel_crtc_state
*pipe_config
)
6604 struct drm_device
*dev
= crtc
->base
.dev
;
6605 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6606 enum pipe pipe
= crtc
->pipe
;
6608 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
6609 u32 coreclk
, reg_val
;
6612 I915_WRITE(DPLL(pipe
),
6613 pipe_config
->dpll_hw_state
.dpll
&
6614 ~(DPLL_VCO_ENABLE
| DPLL_EXT_BUFFER_ENABLE_VLV
));
6616 /* No need to actually set up the DPLL with DSI */
6617 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
6620 mutex_lock(&dev_priv
->sb_lock
);
6622 bestn
= pipe_config
->dpll
.n
;
6623 bestm1
= pipe_config
->dpll
.m1
;
6624 bestm2
= pipe_config
->dpll
.m2
;
6625 bestp1
= pipe_config
->dpll
.p1
;
6626 bestp2
= pipe_config
->dpll
.p2
;
6628 /* See eDP HDMI DPIO driver vbios notes doc */
6630 /* PLL B needs special handling */
6632 vlv_pllb_recal_opamp(dev_priv
, pipe
);
6634 /* Set up Tx target for periodic Rcomp update */
6635 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
6637 /* Disable target IRef on PLL */
6638 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
6639 reg_val
&= 0x00ffffff;
6640 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
6642 /* Disable fast lock */
6643 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
6645 /* Set idtafcrecal before PLL is enabled */
6646 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
6647 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
6648 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
6649 mdiv
|= (1 << DPIO_K_SHIFT
);
6652 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6653 * but we don't support that).
6654 * Note: don't use the DAC post divider as it seems unstable.
6656 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
6657 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
6659 mdiv
|= DPIO_ENABLE_CALIBRATION
;
6660 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
6662 /* Set HBR and RBR LPF coefficients */
6663 if (pipe_config
->port_clock
== 162000 ||
6664 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_ANALOG
) ||
6665 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_HDMI
))
6666 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
6669 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
6672 if (intel_crtc_has_dp_encoder(pipe_config
)) {
6673 /* Use SSC source */
6675 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6678 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6680 } else { /* HDMI or VGA */
6681 /* Use bend source */
6683 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6686 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6690 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
6691 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
6692 if (intel_crtc_has_dp_encoder(crtc
->config
))
6693 coreclk
|= 0x01000000;
6694 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
6696 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
6697 mutex_unlock(&dev_priv
->sb_lock
);
6700 static void chv_prepare_pll(struct intel_crtc
*crtc
,
6701 const struct intel_crtc_state
*pipe_config
)
6703 struct drm_device
*dev
= crtc
->base
.dev
;
6704 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6705 enum pipe pipe
= crtc
->pipe
;
6706 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
6707 u32 loopfilter
, tribuf_calcntr
;
6708 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
6712 /* Enable Refclk and SSC */
6713 I915_WRITE(DPLL(pipe
),
6714 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
6716 /* No need to actually set up the DPLL with DSI */
6717 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
6720 bestn
= pipe_config
->dpll
.n
;
6721 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
6722 bestm1
= pipe_config
->dpll
.m1
;
6723 bestm2
= pipe_config
->dpll
.m2
>> 22;
6724 bestp1
= pipe_config
->dpll
.p1
;
6725 bestp2
= pipe_config
->dpll
.p2
;
6726 vco
= pipe_config
->dpll
.vco
;
6730 mutex_lock(&dev_priv
->sb_lock
);
6732 /* p1 and p2 divider */
6733 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
6734 5 << DPIO_CHV_S1_DIV_SHIFT
|
6735 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
6736 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
6737 1 << DPIO_CHV_K_DIV_SHIFT
);
6739 /* Feedback post-divider - m2 */
6740 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
6742 /* Feedback refclk divider - n and m1 */
6743 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
6744 DPIO_CHV_M1_DIV_BY_2
|
6745 1 << DPIO_CHV_N_DIV_SHIFT
);
6747 /* M2 fraction division */
6748 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
6750 /* M2 fraction division enable */
6751 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
6752 dpio_val
&= ~(DPIO_CHV_FEEDFWD_GAIN_MASK
| DPIO_CHV_FRAC_DIV_EN
);
6753 dpio_val
|= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
);
6755 dpio_val
|= DPIO_CHV_FRAC_DIV_EN
;
6756 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
), dpio_val
);
6758 /* Program digital lock detect threshold */
6759 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW9(port
));
6760 dpio_val
&= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK
|
6761 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
);
6762 dpio_val
|= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT
);
6764 dpio_val
|= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
;
6765 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW9(port
), dpio_val
);
6768 if (vco
== 5400000) {
6769 loopfilter
|= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT
);
6770 loopfilter
|= (0x8 << DPIO_CHV_INT_COEFF_SHIFT
);
6771 loopfilter
|= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT
);
6772 tribuf_calcntr
= 0x9;
6773 } else if (vco
<= 6200000) {
6774 loopfilter
|= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT
);
6775 loopfilter
|= (0xB << DPIO_CHV_INT_COEFF_SHIFT
);
6776 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
6777 tribuf_calcntr
= 0x9;
6778 } else if (vco
<= 6480000) {
6779 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
6780 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
6781 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
6782 tribuf_calcntr
= 0x8;
6784 /* Not supported. Apply the same limits as in the max case */
6785 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
6786 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
6787 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
6790 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
6792 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW8(port
));
6793 dpio_val
&= ~DPIO_CHV_TDC_TARGET_CNT_MASK
;
6794 dpio_val
|= (tribuf_calcntr
<< DPIO_CHV_TDC_TARGET_CNT_SHIFT
);
6795 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW8(port
), dpio_val
);
6798 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
6799 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
6802 mutex_unlock(&dev_priv
->sb_lock
);
6806 * vlv_force_pll_on - forcibly enable just the PLL
6807 * @dev_priv: i915 private structure
6808 * @pipe: pipe PLL to enable
6809 * @dpll: PLL configuration
6811 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6812 * in cases where we need the PLL enabled even when @pipe is not going to
6815 int vlv_force_pll_on(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
6816 const struct dpll
*dpll
)
6818 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
6819 struct intel_crtc_state
*pipe_config
;
6821 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
6825 pipe_config
->base
.crtc
= &crtc
->base
;
6826 pipe_config
->pixel_multiplier
= 1;
6827 pipe_config
->dpll
= *dpll
;
6829 if (IS_CHERRYVIEW(dev_priv
)) {
6830 chv_compute_dpll(crtc
, pipe_config
);
6831 chv_prepare_pll(crtc
, pipe_config
);
6832 chv_enable_pll(crtc
, pipe_config
);
6834 vlv_compute_dpll(crtc
, pipe_config
);
6835 vlv_prepare_pll(crtc
, pipe_config
);
6836 vlv_enable_pll(crtc
, pipe_config
);
6845 * vlv_force_pll_off - forcibly disable just the PLL
6846 * @dev_priv: i915 private structure
6847 * @pipe: pipe PLL to disable
6849 * Disable the PLL for @pipe. To be used in cases where we need
6850 * the PLL enabled even when @pipe is not going to be enabled.
6852 void vlv_force_pll_off(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
6854 if (IS_CHERRYVIEW(dev_priv
))
6855 chv_disable_pll(dev_priv
, pipe
);
6857 vlv_disable_pll(dev_priv
, pipe
);
6860 static void i9xx_compute_dpll(struct intel_crtc
*crtc
,
6861 struct intel_crtc_state
*crtc_state
,
6862 struct dpll
*reduced_clock
)
6864 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6866 struct dpll
*clock
= &crtc_state
->dpll
;
6868 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
6870 dpll
= DPLL_VGA_MODE_DIS
;
6872 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
))
6873 dpll
|= DPLLB_MODE_LVDS
;
6875 dpll
|= DPLLB_MODE_DAC_SERIAL
;
6877 if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
) ||
6878 IS_G33(dev_priv
) || IS_PINEVIEW(dev_priv
)) {
6879 dpll
|= (crtc_state
->pixel_multiplier
- 1)
6880 << SDVO_MULTIPLIER_SHIFT_HIRES
;
6883 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
6884 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
))
6885 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6887 if (intel_crtc_has_dp_encoder(crtc_state
))
6888 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6890 /* compute bitmask from p1 value */
6891 if (IS_PINEVIEW(dev_priv
))
6892 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
6894 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6895 if (IS_G4X(dev_priv
) && reduced_clock
)
6896 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
6898 switch (clock
->p2
) {
6900 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
6903 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
6906 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
6909 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
6912 if (INTEL_GEN(dev_priv
) >= 4)
6913 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
6915 if (crtc_state
->sdvo_tv_clock
)
6916 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
6917 else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
6918 intel_panel_use_ssc(dev_priv
))
6919 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6921 dpll
|= PLL_REF_INPUT_DREFCLK
;
6923 dpll
|= DPLL_VCO_ENABLE
;
6924 crtc_state
->dpll_hw_state
.dpll
= dpll
;
6926 if (INTEL_GEN(dev_priv
) >= 4) {
6927 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
6928 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6929 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
6933 static void i8xx_compute_dpll(struct intel_crtc
*crtc
,
6934 struct intel_crtc_state
*crtc_state
,
6935 struct dpll
*reduced_clock
)
6937 struct drm_device
*dev
= crtc
->base
.dev
;
6938 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6940 struct dpll
*clock
= &crtc_state
->dpll
;
6942 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
6944 dpll
= DPLL_VGA_MODE_DIS
;
6946 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
6947 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6950 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
6952 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6954 dpll
|= PLL_P2_DIVIDE_BY_4
;
6957 if (!IS_I830(dev_priv
) &&
6958 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DVO
))
6959 dpll
|= DPLL_DVO_2X_MODE
;
6961 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
6962 intel_panel_use_ssc(dev_priv
))
6963 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6965 dpll
|= PLL_REF_INPUT_DREFCLK
;
6967 dpll
|= DPLL_VCO_ENABLE
;
6968 crtc_state
->dpll_hw_state
.dpll
= dpll
;
6971 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
6973 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
6974 enum pipe pipe
= intel_crtc
->pipe
;
6975 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
6976 const struct drm_display_mode
*adjusted_mode
= &intel_crtc
->config
->base
.adjusted_mode
;
6977 uint32_t crtc_vtotal
, crtc_vblank_end
;
6980 /* We need to be careful not to changed the adjusted mode, for otherwise
6981 * the hw state checker will get angry at the mismatch. */
6982 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
6983 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
6985 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
6986 /* the chip adds 2 halflines automatically */
6988 crtc_vblank_end
-= 1;
6990 if (intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_SDVO
))
6991 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
6993 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
6994 adjusted_mode
->crtc_htotal
/ 2;
6996 vsyncshift
+= adjusted_mode
->crtc_htotal
;
6999 if (INTEL_GEN(dev_priv
) > 3)
7000 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
7002 I915_WRITE(HTOTAL(cpu_transcoder
),
7003 (adjusted_mode
->crtc_hdisplay
- 1) |
7004 ((adjusted_mode
->crtc_htotal
- 1) << 16));
7005 I915_WRITE(HBLANK(cpu_transcoder
),
7006 (adjusted_mode
->crtc_hblank_start
- 1) |
7007 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
7008 I915_WRITE(HSYNC(cpu_transcoder
),
7009 (adjusted_mode
->crtc_hsync_start
- 1) |
7010 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
7012 I915_WRITE(VTOTAL(cpu_transcoder
),
7013 (adjusted_mode
->crtc_vdisplay
- 1) |
7014 ((crtc_vtotal
- 1) << 16));
7015 I915_WRITE(VBLANK(cpu_transcoder
),
7016 (adjusted_mode
->crtc_vblank_start
- 1) |
7017 ((crtc_vblank_end
- 1) << 16));
7018 I915_WRITE(VSYNC(cpu_transcoder
),
7019 (adjusted_mode
->crtc_vsync_start
- 1) |
7020 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
7022 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7023 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7024 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7026 if (IS_HASWELL(dev_priv
) && cpu_transcoder
== TRANSCODER_EDP
&&
7027 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
7028 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
7032 static void intel_set_pipe_src_size(struct intel_crtc
*intel_crtc
)
7034 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7035 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7036 enum pipe pipe
= intel_crtc
->pipe
;
7038 /* pipesrc controls the size that is scaled from, which should
7039 * always be the user's requested size.
7041 I915_WRITE(PIPESRC(pipe
),
7042 ((intel_crtc
->config
->pipe_src_w
- 1) << 16) |
7043 (intel_crtc
->config
->pipe_src_h
- 1));
7046 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
7047 struct intel_crtc_state
*pipe_config
)
7049 struct drm_device
*dev
= crtc
->base
.dev
;
7050 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7051 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
7054 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
7055 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
7056 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
7057 tmp
= I915_READ(HBLANK(cpu_transcoder
));
7058 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
7059 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7060 tmp
= I915_READ(HSYNC(cpu_transcoder
));
7061 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
7062 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7064 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
7065 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
7066 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
7067 tmp
= I915_READ(VBLANK(cpu_transcoder
));
7068 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
7069 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7070 tmp
= I915_READ(VSYNC(cpu_transcoder
));
7071 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
7072 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7074 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
7075 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
7076 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
7077 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
7081 static void intel_get_pipe_src_size(struct intel_crtc
*crtc
,
7082 struct intel_crtc_state
*pipe_config
)
7084 struct drm_device
*dev
= crtc
->base
.dev
;
7085 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7088 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
7089 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
7090 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
7092 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
7093 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
7096 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
7097 struct intel_crtc_state
*pipe_config
)
7099 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
7100 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
7101 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
7102 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
7104 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
7105 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
7106 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
7107 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
7109 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
7110 mode
->type
= DRM_MODE_TYPE_DRIVER
;
7112 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
7114 mode
->hsync
= drm_mode_hsync(mode
);
7115 mode
->vrefresh
= drm_mode_vrefresh(mode
);
7116 drm_mode_set_name(mode
);
7119 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
7121 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
7126 /* we keep both pipes enabled on 830 */
7127 if (IS_I830(dev_priv
))
7128 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
7130 if (intel_crtc
->config
->double_wide
)
7131 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
7133 /* only g4x and later have fancy bpc/dither controls */
7134 if (IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
7135 IS_CHERRYVIEW(dev_priv
)) {
7136 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7137 if (intel_crtc
->config
->dither
&& intel_crtc
->config
->pipe_bpp
!= 30)
7138 pipeconf
|= PIPECONF_DITHER_EN
|
7139 PIPECONF_DITHER_TYPE_SP
;
7141 switch (intel_crtc
->config
->pipe_bpp
) {
7143 pipeconf
|= PIPECONF_6BPC
;
7146 pipeconf
|= PIPECONF_8BPC
;
7149 pipeconf
|= PIPECONF_10BPC
;
7152 /* Case prevented by intel_choose_pipe_bpp_dither. */
7157 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
7158 if (INTEL_GEN(dev_priv
) < 4 ||
7159 intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_SDVO
))
7160 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
7162 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
7164 pipeconf
|= PIPECONF_PROGRESSIVE
;
7166 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
7167 intel_crtc
->config
->limited_color_range
)
7168 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
7170 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
7171 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
7174 static int i8xx_crtc_compute_clock(struct intel_crtc
*crtc
,
7175 struct intel_crtc_state
*crtc_state
)
7177 struct drm_device
*dev
= crtc
->base
.dev
;
7178 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7179 const struct intel_limit
*limit
;
7182 memset(&crtc_state
->dpll_hw_state
, 0,
7183 sizeof(crtc_state
->dpll_hw_state
));
7185 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7186 if (intel_panel_use_ssc(dev_priv
)) {
7187 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7188 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7191 limit
= &intel_limits_i8xx_lvds
;
7192 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DVO
)) {
7193 limit
= &intel_limits_i8xx_dvo
;
7195 limit
= &intel_limits_i8xx_dac
;
7198 if (!crtc_state
->clock_set
&&
7199 !i9xx_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7200 refclk
, NULL
, &crtc_state
->dpll
)) {
7201 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7205 i8xx_compute_dpll(crtc
, crtc_state
, NULL
);
7210 static int g4x_crtc_compute_clock(struct intel_crtc
*crtc
,
7211 struct intel_crtc_state
*crtc_state
)
7213 struct drm_device
*dev
= crtc
->base
.dev
;
7214 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7215 const struct intel_limit
*limit
;
7218 memset(&crtc_state
->dpll_hw_state
, 0,
7219 sizeof(crtc_state
->dpll_hw_state
));
7221 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7222 if (intel_panel_use_ssc(dev_priv
)) {
7223 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7224 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7227 if (intel_is_dual_link_lvds(dev
))
7228 limit
= &intel_limits_g4x_dual_channel_lvds
;
7230 limit
= &intel_limits_g4x_single_channel_lvds
;
7231 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
) ||
7232 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_ANALOG
)) {
7233 limit
= &intel_limits_g4x_hdmi
;
7234 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
)) {
7235 limit
= &intel_limits_g4x_sdvo
;
7237 /* The option is for other outputs */
7238 limit
= &intel_limits_i9xx_sdvo
;
7241 if (!crtc_state
->clock_set
&&
7242 !g4x_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7243 refclk
, NULL
, &crtc_state
->dpll
)) {
7244 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7248 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
7253 static int pnv_crtc_compute_clock(struct intel_crtc
*crtc
,
7254 struct intel_crtc_state
*crtc_state
)
7256 struct drm_device
*dev
= crtc
->base
.dev
;
7257 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7258 const struct intel_limit
*limit
;
7261 memset(&crtc_state
->dpll_hw_state
, 0,
7262 sizeof(crtc_state
->dpll_hw_state
));
7264 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7265 if (intel_panel_use_ssc(dev_priv
)) {
7266 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7267 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7270 limit
= &intel_limits_pineview_lvds
;
7272 limit
= &intel_limits_pineview_sdvo
;
7275 if (!crtc_state
->clock_set
&&
7276 !pnv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7277 refclk
, NULL
, &crtc_state
->dpll
)) {
7278 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7282 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
7287 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
7288 struct intel_crtc_state
*crtc_state
)
7290 struct drm_device
*dev
= crtc
->base
.dev
;
7291 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7292 const struct intel_limit
*limit
;
7295 memset(&crtc_state
->dpll_hw_state
, 0,
7296 sizeof(crtc_state
->dpll_hw_state
));
7298 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7299 if (intel_panel_use_ssc(dev_priv
)) {
7300 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7301 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7304 limit
= &intel_limits_i9xx_lvds
;
7306 limit
= &intel_limits_i9xx_sdvo
;
7309 if (!crtc_state
->clock_set
&&
7310 !i9xx_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7311 refclk
, NULL
, &crtc_state
->dpll
)) {
7312 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7316 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
7321 static int chv_crtc_compute_clock(struct intel_crtc
*crtc
,
7322 struct intel_crtc_state
*crtc_state
)
7324 int refclk
= 100000;
7325 const struct intel_limit
*limit
= &intel_limits_chv
;
7327 memset(&crtc_state
->dpll_hw_state
, 0,
7328 sizeof(crtc_state
->dpll_hw_state
));
7330 if (!crtc_state
->clock_set
&&
7331 !chv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7332 refclk
, NULL
, &crtc_state
->dpll
)) {
7333 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7337 chv_compute_dpll(crtc
, crtc_state
);
7342 static int vlv_crtc_compute_clock(struct intel_crtc
*crtc
,
7343 struct intel_crtc_state
*crtc_state
)
7345 int refclk
= 100000;
7346 const struct intel_limit
*limit
= &intel_limits_vlv
;
7348 memset(&crtc_state
->dpll_hw_state
, 0,
7349 sizeof(crtc_state
->dpll_hw_state
));
7351 if (!crtc_state
->clock_set
&&
7352 !vlv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7353 refclk
, NULL
, &crtc_state
->dpll
)) {
7354 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7358 vlv_compute_dpll(crtc
, crtc_state
);
7363 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
7364 struct intel_crtc_state
*pipe_config
)
7366 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7369 if (INTEL_GEN(dev_priv
) <= 3 &&
7370 (IS_I830(dev_priv
) || !IS_MOBILE(dev_priv
)))
7373 tmp
= I915_READ(PFIT_CONTROL
);
7374 if (!(tmp
& PFIT_ENABLE
))
7377 /* Check whether the pfit is attached to our pipe. */
7378 if (INTEL_GEN(dev_priv
) < 4) {
7379 if (crtc
->pipe
!= PIPE_B
)
7382 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
7386 pipe_config
->gmch_pfit
.control
= tmp
;
7387 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
7390 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
7391 struct intel_crtc_state
*pipe_config
)
7393 struct drm_device
*dev
= crtc
->base
.dev
;
7394 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7395 int pipe
= pipe_config
->cpu_transcoder
;
7398 int refclk
= 100000;
7400 /* In case of DSI, DPLL will not be used */
7401 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
7404 mutex_lock(&dev_priv
->sb_lock
);
7405 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
7406 mutex_unlock(&dev_priv
->sb_lock
);
7408 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
7409 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
7410 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
7411 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
7412 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
7414 pipe_config
->port_clock
= vlv_calc_dpll_params(refclk
, &clock
);
7418 i9xx_get_initial_plane_config(struct intel_crtc
*crtc
,
7419 struct intel_initial_plane_config
*plane_config
)
7421 struct drm_device
*dev
= crtc
->base
.dev
;
7422 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7423 u32 val
, base
, offset
;
7424 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
7425 int fourcc
, pixel_format
;
7426 unsigned int aligned_height
;
7427 struct drm_framebuffer
*fb
;
7428 struct intel_framebuffer
*intel_fb
;
7430 val
= I915_READ(DSPCNTR(plane
));
7431 if (!(val
& DISPLAY_PLANE_ENABLE
))
7434 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
7436 DRM_DEBUG_KMS("failed to alloc fb\n");
7440 fb
= &intel_fb
->base
;
7444 if (INTEL_GEN(dev_priv
) >= 4) {
7445 if (val
& DISPPLANE_TILED
) {
7446 plane_config
->tiling
= I915_TILING_X
;
7447 fb
->modifier
= I915_FORMAT_MOD_X_TILED
;
7451 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
7452 fourcc
= i9xx_format_to_fourcc(pixel_format
);
7453 fb
->format
= drm_format_info(fourcc
);
7455 if (INTEL_GEN(dev_priv
) >= 4) {
7456 if (plane_config
->tiling
)
7457 offset
= I915_READ(DSPTILEOFF(plane
));
7459 offset
= I915_READ(DSPLINOFF(plane
));
7460 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
7462 base
= I915_READ(DSPADDR(plane
));
7464 plane_config
->base
= base
;
7466 val
= I915_READ(PIPESRC(pipe
));
7467 fb
->width
= ((val
>> 16) & 0xfff) + 1;
7468 fb
->height
= ((val
>> 0) & 0xfff) + 1;
7470 val
= I915_READ(DSPSTRIDE(pipe
));
7471 fb
->pitches
[0] = val
& 0xffffffc0;
7473 aligned_height
= intel_fb_align_height(fb
, 0, fb
->height
);
7475 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
7477 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7478 pipe_name(pipe
), plane
, fb
->width
, fb
->height
,
7479 fb
->format
->cpp
[0] * 8, base
, fb
->pitches
[0],
7480 plane_config
->size
);
7482 plane_config
->fb
= intel_fb
;
7485 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
7486 struct intel_crtc_state
*pipe_config
)
7488 struct drm_device
*dev
= crtc
->base
.dev
;
7489 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7490 int pipe
= pipe_config
->cpu_transcoder
;
7491 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7493 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
, pll_dw3
;
7494 int refclk
= 100000;
7496 /* In case of DSI, DPLL will not be used */
7497 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
7500 mutex_lock(&dev_priv
->sb_lock
);
7501 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
7502 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
7503 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
7504 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
7505 pll_dw3
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
7506 mutex_unlock(&dev_priv
->sb_lock
);
7508 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
7509 clock
.m2
= (pll_dw0
& 0xff) << 22;
7510 if (pll_dw3
& DPIO_CHV_FRAC_DIV_EN
)
7511 clock
.m2
|= pll_dw2
& 0x3fffff;
7512 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
7513 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
7514 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
7516 pipe_config
->port_clock
= chv_calc_dpll_params(refclk
, &clock
);
7519 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
7520 struct intel_crtc_state
*pipe_config
)
7522 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7523 enum intel_display_power_domain power_domain
;
7527 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
7528 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
7531 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7532 pipe_config
->shared_dpll
= NULL
;
7536 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
7537 if (!(tmp
& PIPECONF_ENABLE
))
7540 if (IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
7541 IS_CHERRYVIEW(dev_priv
)) {
7542 switch (tmp
& PIPECONF_BPC_MASK
) {
7544 pipe_config
->pipe_bpp
= 18;
7547 pipe_config
->pipe_bpp
= 24;
7549 case PIPECONF_10BPC
:
7550 pipe_config
->pipe_bpp
= 30;
7557 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
7558 (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
7559 pipe_config
->limited_color_range
= true;
7561 if (INTEL_GEN(dev_priv
) < 4)
7562 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
7564 intel_get_pipe_timings(crtc
, pipe_config
);
7565 intel_get_pipe_src_size(crtc
, pipe_config
);
7567 i9xx_get_pfit_config(crtc
, pipe_config
);
7569 if (INTEL_GEN(dev_priv
) >= 4) {
7570 /* No way to read it out on pipes B and C */
7571 if (IS_CHERRYVIEW(dev_priv
) && crtc
->pipe
!= PIPE_A
)
7572 tmp
= dev_priv
->chv_dpll_md
[crtc
->pipe
];
7574 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
7575 pipe_config
->pixel_multiplier
=
7576 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
7577 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
7578 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
7579 } else if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
) ||
7580 IS_G33(dev_priv
) || IS_PINEVIEW(dev_priv
)) {
7581 tmp
= I915_READ(DPLL(crtc
->pipe
));
7582 pipe_config
->pixel_multiplier
=
7583 ((tmp
& SDVO_MULTIPLIER_MASK
)
7584 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
7586 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7587 * port and will be fixed up in the encoder->get_config
7589 pipe_config
->pixel_multiplier
= 1;
7591 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
7592 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
)) {
7594 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7595 * on 830. Filter it out here so that we don't
7596 * report errors due to that.
7598 if (IS_I830(dev_priv
))
7599 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
7601 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
7602 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
7604 /* Mask out read-only status bits. */
7605 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
7606 DPLL_PORTC_READY_MASK
|
7607 DPLL_PORTB_READY_MASK
);
7610 if (IS_CHERRYVIEW(dev_priv
))
7611 chv_crtc_clock_get(crtc
, pipe_config
);
7612 else if (IS_VALLEYVIEW(dev_priv
))
7613 vlv_crtc_clock_get(crtc
, pipe_config
);
7615 i9xx_crtc_clock_get(crtc
, pipe_config
);
7618 * Normally the dotclock is filled in by the encoder .get_config()
7619 * but in case the pipe is enabled w/o any ports we need a sane
7622 pipe_config
->base
.adjusted_mode
.crtc_clock
=
7623 pipe_config
->port_clock
/ pipe_config
->pixel_multiplier
;
7628 intel_display_power_put(dev_priv
, power_domain
);
7633 static void ironlake_init_pch_refclk(struct drm_i915_private
*dev_priv
)
7635 struct intel_encoder
*encoder
;
7638 bool has_lvds
= false;
7639 bool has_cpu_edp
= false;
7640 bool has_panel
= false;
7641 bool has_ck505
= false;
7642 bool can_ssc
= false;
7643 bool using_ssc_source
= false;
7645 /* We need to take the global config into account */
7646 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
7647 switch (encoder
->type
) {
7648 case INTEL_OUTPUT_LVDS
:
7652 case INTEL_OUTPUT_EDP
:
7654 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
7662 if (HAS_PCH_IBX(dev_priv
)) {
7663 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
7664 can_ssc
= has_ck505
;
7670 /* Check if any DPLLs are using the SSC source */
7671 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
7672 u32 temp
= I915_READ(PCH_DPLL(i
));
7674 if (!(temp
& DPLL_VCO_ENABLE
))
7677 if ((temp
& PLL_REF_INPUT_MASK
) ==
7678 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
7679 using_ssc_source
= true;
7684 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7685 has_panel
, has_lvds
, has_ck505
, using_ssc_source
);
7687 /* Ironlake: try to setup display ref clock before DPLL
7688 * enabling. This is only under driver's control after
7689 * PCH B stepping, previous chipset stepping should be
7690 * ignoring this setting.
7692 val
= I915_READ(PCH_DREF_CONTROL
);
7694 /* As we must carefully and slowly disable/enable each source in turn,
7695 * compute the final state we want first and check if we need to
7696 * make any changes at all.
7699 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
7701 final
|= DREF_NONSPREAD_CK505_ENABLE
;
7703 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
7705 final
&= ~DREF_SSC_SOURCE_MASK
;
7706 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
7707 final
&= ~DREF_SSC1_ENABLE
;
7710 final
|= DREF_SSC_SOURCE_ENABLE
;
7712 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
7713 final
|= DREF_SSC1_ENABLE
;
7716 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
7717 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
7719 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
7721 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7722 } else if (using_ssc_source
) {
7723 final
|= DREF_SSC_SOURCE_ENABLE
;
7724 final
|= DREF_SSC1_ENABLE
;
7730 /* Always enable nonspread source */
7731 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
7734 val
|= DREF_NONSPREAD_CK505_ENABLE
;
7736 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
7739 val
&= ~DREF_SSC_SOURCE_MASK
;
7740 val
|= DREF_SSC_SOURCE_ENABLE
;
7742 /* SSC must be turned on before enabling the CPU output */
7743 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
7744 DRM_DEBUG_KMS("Using SSC on panel\n");
7745 val
|= DREF_SSC1_ENABLE
;
7747 val
&= ~DREF_SSC1_ENABLE
;
7749 /* Get SSC going before enabling the outputs */
7750 I915_WRITE(PCH_DREF_CONTROL
, val
);
7751 POSTING_READ(PCH_DREF_CONTROL
);
7754 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
7756 /* Enable CPU source on CPU attached eDP */
7758 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
7759 DRM_DEBUG_KMS("Using SSC on eDP\n");
7760 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
7762 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
7764 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7766 I915_WRITE(PCH_DREF_CONTROL
, val
);
7767 POSTING_READ(PCH_DREF_CONTROL
);
7770 DRM_DEBUG_KMS("Disabling CPU source output\n");
7772 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
7774 /* Turn off CPU output */
7775 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7777 I915_WRITE(PCH_DREF_CONTROL
, val
);
7778 POSTING_READ(PCH_DREF_CONTROL
);
7781 if (!using_ssc_source
) {
7782 DRM_DEBUG_KMS("Disabling SSC source\n");
7784 /* Turn off the SSC source */
7785 val
&= ~DREF_SSC_SOURCE_MASK
;
7786 val
|= DREF_SSC_SOURCE_DISABLE
;
7789 val
&= ~DREF_SSC1_ENABLE
;
7791 I915_WRITE(PCH_DREF_CONTROL
, val
);
7792 POSTING_READ(PCH_DREF_CONTROL
);
7797 BUG_ON(val
!= final
);
7800 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
7804 tmp
= I915_READ(SOUTH_CHICKEN2
);
7805 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
7806 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
7808 if (wait_for_us(I915_READ(SOUTH_CHICKEN2
) &
7809 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
7810 DRM_ERROR("FDI mPHY reset assert timeout\n");
7812 tmp
= I915_READ(SOUTH_CHICKEN2
);
7813 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
7814 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
7816 if (wait_for_us((I915_READ(SOUTH_CHICKEN2
) &
7817 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
7818 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7821 /* WaMPhyProgramming:hsw */
7822 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
7826 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
7827 tmp
&= ~(0xFF << 24);
7828 tmp
|= (0x12 << 24);
7829 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
7831 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
7833 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
7835 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
7837 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
7839 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
7840 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
7841 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
7843 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
7844 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
7845 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
7847 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
7850 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
7852 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
7855 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
7857 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
7860 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
7862 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
7865 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
7867 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
7868 tmp
&= ~(0xFF << 16);
7869 tmp
|= (0x1C << 16);
7870 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
7872 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
7873 tmp
&= ~(0xFF << 16);
7874 tmp
|= (0x1C << 16);
7875 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
7877 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
7879 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
7881 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
7883 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
7885 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
7886 tmp
&= ~(0xF << 28);
7888 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
7890 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
7891 tmp
&= ~(0xF << 28);
7893 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
7896 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7897 * Programming" based on the parameters passed:
7898 * - Sequence to enable CLKOUT_DP
7899 * - Sequence to enable CLKOUT_DP without spread
7900 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7902 static void lpt_enable_clkout_dp(struct drm_i915_private
*dev_priv
,
7903 bool with_spread
, bool with_fdi
)
7907 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
7909 if (WARN(HAS_PCH_LPT_LP(dev_priv
) &&
7910 with_fdi
, "LP PCH doesn't have FDI\n"))
7913 mutex_lock(&dev_priv
->sb_lock
);
7915 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
7916 tmp
&= ~SBI_SSCCTL_DISABLE
;
7917 tmp
|= SBI_SSCCTL_PATHALT
;
7918 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7923 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
7924 tmp
&= ~SBI_SSCCTL_PATHALT
;
7925 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7928 lpt_reset_fdi_mphy(dev_priv
);
7929 lpt_program_fdi_mphy(dev_priv
);
7933 reg
= HAS_PCH_LPT_LP(dev_priv
) ? SBI_GEN0
: SBI_DBUFF0
;
7934 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
7935 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
7936 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
7938 mutex_unlock(&dev_priv
->sb_lock
);
7941 /* Sequence to disable CLKOUT_DP */
7942 static void lpt_disable_clkout_dp(struct drm_i915_private
*dev_priv
)
7946 mutex_lock(&dev_priv
->sb_lock
);
7948 reg
= HAS_PCH_LPT_LP(dev_priv
) ? SBI_GEN0
: SBI_DBUFF0
;
7949 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
7950 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
7951 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
7953 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
7954 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
7955 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
7956 tmp
|= SBI_SSCCTL_PATHALT
;
7957 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7960 tmp
|= SBI_SSCCTL_DISABLE
;
7961 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7964 mutex_unlock(&dev_priv
->sb_lock
);
7967 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7969 static const uint16_t sscdivintphase
[] = {
7970 [BEND_IDX( 50)] = 0x3B23,
7971 [BEND_IDX( 45)] = 0x3B23,
7972 [BEND_IDX( 40)] = 0x3C23,
7973 [BEND_IDX( 35)] = 0x3C23,
7974 [BEND_IDX( 30)] = 0x3D23,
7975 [BEND_IDX( 25)] = 0x3D23,
7976 [BEND_IDX( 20)] = 0x3E23,
7977 [BEND_IDX( 15)] = 0x3E23,
7978 [BEND_IDX( 10)] = 0x3F23,
7979 [BEND_IDX( 5)] = 0x3F23,
7980 [BEND_IDX( 0)] = 0x0025,
7981 [BEND_IDX( -5)] = 0x0025,
7982 [BEND_IDX(-10)] = 0x0125,
7983 [BEND_IDX(-15)] = 0x0125,
7984 [BEND_IDX(-20)] = 0x0225,
7985 [BEND_IDX(-25)] = 0x0225,
7986 [BEND_IDX(-30)] = 0x0325,
7987 [BEND_IDX(-35)] = 0x0325,
7988 [BEND_IDX(-40)] = 0x0425,
7989 [BEND_IDX(-45)] = 0x0425,
7990 [BEND_IDX(-50)] = 0x0525,
7995 * steps -50 to 50 inclusive, in steps of 5
7996 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7997 * change in clock period = -(steps / 10) * 5.787 ps
7999 static void lpt_bend_clkout_dp(struct drm_i915_private
*dev_priv
, int steps
)
8002 int idx
= BEND_IDX(steps
);
8004 if (WARN_ON(steps
% 5 != 0))
8007 if (WARN_ON(idx
>= ARRAY_SIZE(sscdivintphase
)))
8010 mutex_lock(&dev_priv
->sb_lock
);
8012 if (steps
% 10 != 0)
8016 intel_sbi_write(dev_priv
, SBI_SSCDITHPHASE
, tmp
, SBI_ICLK
);
8018 tmp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE
, SBI_ICLK
);
8020 tmp
|= sscdivintphase
[idx
];
8021 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE
, tmp
, SBI_ICLK
);
8023 mutex_unlock(&dev_priv
->sb_lock
);
8028 static void lpt_init_pch_refclk(struct drm_i915_private
*dev_priv
)
8030 struct intel_encoder
*encoder
;
8031 bool has_vga
= false;
8033 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
8034 switch (encoder
->type
) {
8035 case INTEL_OUTPUT_ANALOG
:
8044 lpt_bend_clkout_dp(dev_priv
, 0);
8045 lpt_enable_clkout_dp(dev_priv
, true, true);
8047 lpt_disable_clkout_dp(dev_priv
);
8052 * Initialize reference clocks when the driver loads
8054 void intel_init_pch_refclk(struct drm_i915_private
*dev_priv
)
8056 if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
))
8057 ironlake_init_pch_refclk(dev_priv
);
8058 else if (HAS_PCH_LPT(dev_priv
))
8059 lpt_init_pch_refclk(dev_priv
);
8062 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
8064 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
8065 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8066 int pipe
= intel_crtc
->pipe
;
8071 switch (intel_crtc
->config
->pipe_bpp
) {
8073 val
|= PIPECONF_6BPC
;
8076 val
|= PIPECONF_8BPC
;
8079 val
|= PIPECONF_10BPC
;
8082 val
|= PIPECONF_12BPC
;
8085 /* Case prevented by intel_choose_pipe_bpp_dither. */
8089 if (intel_crtc
->config
->dither
)
8090 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8092 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8093 val
|= PIPECONF_INTERLACED_ILK
;
8095 val
|= PIPECONF_PROGRESSIVE
;
8097 if (intel_crtc
->config
->limited_color_range
)
8098 val
|= PIPECONF_COLOR_RANGE_SELECT
;
8100 I915_WRITE(PIPECONF(pipe
), val
);
8101 POSTING_READ(PIPECONF(pipe
));
8104 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
8106 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
8107 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8108 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
8111 if (IS_HASWELL(dev_priv
) && intel_crtc
->config
->dither
)
8112 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8114 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8115 val
|= PIPECONF_INTERLACED_ILK
;
8117 val
|= PIPECONF_PROGRESSIVE
;
8119 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
8120 POSTING_READ(PIPECONF(cpu_transcoder
));
8123 static void haswell_set_pipemisc(struct drm_crtc
*crtc
)
8125 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
8126 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8127 struct intel_crtc_state
*config
= intel_crtc
->config
;
8129 if (IS_BROADWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 9) {
8132 switch (intel_crtc
->config
->pipe_bpp
) {
8134 val
|= PIPEMISC_DITHER_6_BPC
;
8137 val
|= PIPEMISC_DITHER_8_BPC
;
8140 val
|= PIPEMISC_DITHER_10_BPC
;
8143 val
|= PIPEMISC_DITHER_12_BPC
;
8146 /* Case prevented by pipe_config_set_bpp. */
8150 if (intel_crtc
->config
->dither
)
8151 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
8153 if (config
->ycbcr420
) {
8154 val
|= PIPEMISC_OUTPUT_COLORSPACE_YUV
|
8155 PIPEMISC_YUV420_ENABLE
|
8156 PIPEMISC_YUV420_MODE_FULL_BLEND
;
8159 I915_WRITE(PIPEMISC(intel_crtc
->pipe
), val
);
8163 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
8166 * Account for spread spectrum to avoid
8167 * oversubscribing the link. Max center spread
8168 * is 2.5%; use 5% for safety's sake.
8170 u32 bps
= target_clock
* bpp
* 21 / 20;
8171 return DIV_ROUND_UP(bps
, link_bw
* 8);
8174 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
8176 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
8179 static void ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
8180 struct intel_crtc_state
*crtc_state
,
8181 struct dpll
*reduced_clock
)
8183 struct drm_crtc
*crtc
= &intel_crtc
->base
;
8184 struct drm_device
*dev
= crtc
->dev
;
8185 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8189 /* Enable autotuning of the PLL clock (if permissible) */
8191 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8192 if ((intel_panel_use_ssc(dev_priv
) &&
8193 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
8194 (HAS_PCH_IBX(dev_priv
) && intel_is_dual_link_lvds(dev
)))
8196 } else if (crtc_state
->sdvo_tv_clock
)
8199 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
8201 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
8204 if (reduced_clock
) {
8205 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
8207 if (reduced_clock
->m
< factor
* reduced_clock
->n
)
8215 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
))
8216 dpll
|= DPLLB_MODE_LVDS
;
8218 dpll
|= DPLLB_MODE_DAC_SERIAL
;
8220 dpll
|= (crtc_state
->pixel_multiplier
- 1)
8221 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
8223 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
8224 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
))
8225 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8227 if (intel_crtc_has_dp_encoder(crtc_state
))
8228 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8231 * The high speed IO clock is only really required for
8232 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8233 * possible to share the DPLL between CRT and HDMI. Enabling
8234 * the clock needlessly does no real harm, except use up a
8235 * bit of power potentially.
8237 * We'll limit this to IVB with 3 pipes, since it has only two
8238 * DPLLs and so DPLL sharing is the only way to get three pipes
8239 * driving PCH ports at the same time. On SNB we could do this,
8240 * and potentially avoid enabling the second DPLL, but it's not
8241 * clear if it''s a win or loss power wise. No point in doing
8242 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8244 if (INTEL_INFO(dev_priv
)->num_pipes
== 3 &&
8245 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_ANALOG
))
8246 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8248 /* compute bitmask from p1 value */
8249 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
8251 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
8253 switch (crtc_state
->dpll
.p2
) {
8255 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
8258 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
8261 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
8264 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
8268 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
8269 intel_panel_use_ssc(dev_priv
))
8270 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
8272 dpll
|= PLL_REF_INPUT_DREFCLK
;
8274 dpll
|= DPLL_VCO_ENABLE
;
8276 crtc_state
->dpll_hw_state
.dpll
= dpll
;
8277 crtc_state
->dpll_hw_state
.fp0
= fp
;
8278 crtc_state
->dpll_hw_state
.fp1
= fp2
;
8281 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
8282 struct intel_crtc_state
*crtc_state
)
8284 struct drm_device
*dev
= crtc
->base
.dev
;
8285 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8286 const struct intel_limit
*limit
;
8287 int refclk
= 120000;
8289 memset(&crtc_state
->dpll_hw_state
, 0,
8290 sizeof(crtc_state
->dpll_hw_state
));
8292 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8293 if (!crtc_state
->has_pch_encoder
)
8296 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8297 if (intel_panel_use_ssc(dev_priv
)) {
8298 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8299 dev_priv
->vbt
.lvds_ssc_freq
);
8300 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
8303 if (intel_is_dual_link_lvds(dev
)) {
8304 if (refclk
== 100000)
8305 limit
= &intel_limits_ironlake_dual_lvds_100m
;
8307 limit
= &intel_limits_ironlake_dual_lvds
;
8309 if (refclk
== 100000)
8310 limit
= &intel_limits_ironlake_single_lvds_100m
;
8312 limit
= &intel_limits_ironlake_single_lvds
;
8315 limit
= &intel_limits_ironlake_dac
;
8318 if (!crtc_state
->clock_set
&&
8319 !g4x_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8320 refclk
, NULL
, &crtc_state
->dpll
)) {
8321 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8325 ironlake_compute_dpll(crtc
, crtc_state
, NULL
);
8327 if (!intel_get_shared_dpll(crtc
, crtc_state
, NULL
)) {
8328 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8329 pipe_name(crtc
->pipe
));
8336 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
8337 struct intel_link_m_n
*m_n
)
8339 struct drm_device
*dev
= crtc
->base
.dev
;
8340 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8341 enum pipe pipe
= crtc
->pipe
;
8343 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
8344 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
8345 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
8347 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
8348 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
8349 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8352 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
8353 enum transcoder transcoder
,
8354 struct intel_link_m_n
*m_n
,
8355 struct intel_link_m_n
*m2_n2
)
8357 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8358 enum pipe pipe
= crtc
->pipe
;
8360 if (INTEL_GEN(dev_priv
) >= 5) {
8361 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
8362 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
8363 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
8365 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
8366 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
8367 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8368 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8369 * gen < 8) and if DRRS is supported (to make sure the
8370 * registers are not unnecessarily read).
8372 if (m2_n2
&& INTEL_GEN(dev_priv
) < 8 &&
8373 crtc
->config
->has_drrs
) {
8374 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
8375 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
8376 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
8378 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
8379 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
8380 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8383 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
8384 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
8385 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
8387 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
8388 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
8389 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8393 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
8394 struct intel_crtc_state
*pipe_config
)
8396 if (pipe_config
->has_pch_encoder
)
8397 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
8399 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
8400 &pipe_config
->dp_m_n
,
8401 &pipe_config
->dp_m2_n2
);
8404 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
8405 struct intel_crtc_state
*pipe_config
)
8407 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
8408 &pipe_config
->fdi_m_n
, NULL
);
8411 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
8412 struct intel_crtc_state
*pipe_config
)
8414 struct drm_device
*dev
= crtc
->base
.dev
;
8415 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8416 struct intel_crtc_scaler_state
*scaler_state
= &pipe_config
->scaler_state
;
8417 uint32_t ps_ctrl
= 0;
8421 /* find scaler attached to this pipe */
8422 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
8423 ps_ctrl
= I915_READ(SKL_PS_CTRL(crtc
->pipe
, i
));
8424 if (ps_ctrl
& PS_SCALER_EN
&& !(ps_ctrl
& PS_PLANE_SEL_MASK
)) {
8426 pipe_config
->pch_pfit
.enabled
= true;
8427 pipe_config
->pch_pfit
.pos
= I915_READ(SKL_PS_WIN_POS(crtc
->pipe
, i
));
8428 pipe_config
->pch_pfit
.size
= I915_READ(SKL_PS_WIN_SZ(crtc
->pipe
, i
));
8433 scaler_state
->scaler_id
= id
;
8435 scaler_state
->scaler_users
|= (1 << SKL_CRTC_INDEX
);
8437 scaler_state
->scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
8442 skylake_get_initial_plane_config(struct intel_crtc
*crtc
,
8443 struct intel_initial_plane_config
*plane_config
)
8445 struct drm_device
*dev
= crtc
->base
.dev
;
8446 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8447 u32 val
, base
, offset
, stride_mult
, tiling
;
8448 int pipe
= crtc
->pipe
;
8449 int fourcc
, pixel_format
;
8450 unsigned int aligned_height
;
8451 struct drm_framebuffer
*fb
;
8452 struct intel_framebuffer
*intel_fb
;
8454 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8456 DRM_DEBUG_KMS("failed to alloc fb\n");
8460 fb
= &intel_fb
->base
;
8464 val
= I915_READ(PLANE_CTL(pipe
, 0));
8465 if (!(val
& PLANE_CTL_ENABLE
))
8468 pixel_format
= val
& PLANE_CTL_FORMAT_MASK
;
8469 fourcc
= skl_format_to_fourcc(pixel_format
,
8470 val
& PLANE_CTL_ORDER_RGBX
,
8471 val
& PLANE_CTL_ALPHA_MASK
);
8472 fb
->format
= drm_format_info(fourcc
);
8474 tiling
= val
& PLANE_CTL_TILED_MASK
;
8476 case PLANE_CTL_TILED_LINEAR
:
8477 fb
->modifier
= DRM_FORMAT_MOD_LINEAR
;
8479 case PLANE_CTL_TILED_X
:
8480 plane_config
->tiling
= I915_TILING_X
;
8481 fb
->modifier
= I915_FORMAT_MOD_X_TILED
;
8483 case PLANE_CTL_TILED_Y
:
8484 if (val
& PLANE_CTL_DECOMPRESSION_ENABLE
)
8485 fb
->modifier
= I915_FORMAT_MOD_Y_TILED_CCS
;
8487 fb
->modifier
= I915_FORMAT_MOD_Y_TILED
;
8489 case PLANE_CTL_TILED_YF
:
8490 if (val
& PLANE_CTL_DECOMPRESSION_ENABLE
)
8491 fb
->modifier
= I915_FORMAT_MOD_Yf_TILED_CCS
;
8493 fb
->modifier
= I915_FORMAT_MOD_Yf_TILED
;
8496 MISSING_CASE(tiling
);
8500 base
= I915_READ(PLANE_SURF(pipe
, 0)) & 0xfffff000;
8501 plane_config
->base
= base
;
8503 offset
= I915_READ(PLANE_OFFSET(pipe
, 0));
8505 val
= I915_READ(PLANE_SIZE(pipe
, 0));
8506 fb
->height
= ((val
>> 16) & 0xfff) + 1;
8507 fb
->width
= ((val
>> 0) & 0x1fff) + 1;
8509 val
= I915_READ(PLANE_STRIDE(pipe
, 0));
8510 stride_mult
= intel_fb_stride_alignment(fb
, 0);
8511 fb
->pitches
[0] = (val
& 0x3ff) * stride_mult
;
8513 aligned_height
= intel_fb_align_height(fb
, 0, fb
->height
);
8515 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8517 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8518 pipe_name(pipe
), fb
->width
, fb
->height
,
8519 fb
->format
->cpp
[0] * 8, base
, fb
->pitches
[0],
8520 plane_config
->size
);
8522 plane_config
->fb
= intel_fb
;
8529 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
8530 struct intel_crtc_state
*pipe_config
)
8532 struct drm_device
*dev
= crtc
->base
.dev
;
8533 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8536 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
8538 if (tmp
& PF_ENABLE
) {
8539 pipe_config
->pch_pfit
.enabled
= true;
8540 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
8541 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
8543 /* We currently do not free assignements of panel fitters on
8544 * ivb/hsw (since we don't use the higher upscaling modes which
8545 * differentiates them) so just WARN about this case for now. */
8546 if (IS_GEN7(dev_priv
)) {
8547 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
8548 PF_PIPE_SEL_IVB(crtc
->pipe
));
8554 ironlake_get_initial_plane_config(struct intel_crtc
*crtc
,
8555 struct intel_initial_plane_config
*plane_config
)
8557 struct drm_device
*dev
= crtc
->base
.dev
;
8558 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8559 u32 val
, base
, offset
;
8560 int pipe
= crtc
->pipe
;
8561 int fourcc
, pixel_format
;
8562 unsigned int aligned_height
;
8563 struct drm_framebuffer
*fb
;
8564 struct intel_framebuffer
*intel_fb
;
8566 val
= I915_READ(DSPCNTR(pipe
));
8567 if (!(val
& DISPLAY_PLANE_ENABLE
))
8570 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8572 DRM_DEBUG_KMS("failed to alloc fb\n");
8576 fb
= &intel_fb
->base
;
8580 if (INTEL_GEN(dev_priv
) >= 4) {
8581 if (val
& DISPPLANE_TILED
) {
8582 plane_config
->tiling
= I915_TILING_X
;
8583 fb
->modifier
= I915_FORMAT_MOD_X_TILED
;
8587 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
8588 fourcc
= i9xx_format_to_fourcc(pixel_format
);
8589 fb
->format
= drm_format_info(fourcc
);
8591 base
= I915_READ(DSPSURF(pipe
)) & 0xfffff000;
8592 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
8593 offset
= I915_READ(DSPOFFSET(pipe
));
8595 if (plane_config
->tiling
)
8596 offset
= I915_READ(DSPTILEOFF(pipe
));
8598 offset
= I915_READ(DSPLINOFF(pipe
));
8600 plane_config
->base
= base
;
8602 val
= I915_READ(PIPESRC(pipe
));
8603 fb
->width
= ((val
>> 16) & 0xfff) + 1;
8604 fb
->height
= ((val
>> 0) & 0xfff) + 1;
8606 val
= I915_READ(DSPSTRIDE(pipe
));
8607 fb
->pitches
[0] = val
& 0xffffffc0;
8609 aligned_height
= intel_fb_align_height(fb
, 0, fb
->height
);
8611 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8613 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8614 pipe_name(pipe
), fb
->width
, fb
->height
,
8615 fb
->format
->cpp
[0] * 8, base
, fb
->pitches
[0],
8616 plane_config
->size
);
8618 plane_config
->fb
= intel_fb
;
8621 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
8622 struct intel_crtc_state
*pipe_config
)
8624 struct drm_device
*dev
= crtc
->base
.dev
;
8625 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8626 enum intel_display_power_domain power_domain
;
8630 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
8631 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
8634 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8635 pipe_config
->shared_dpll
= NULL
;
8638 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
8639 if (!(tmp
& PIPECONF_ENABLE
))
8642 switch (tmp
& PIPECONF_BPC_MASK
) {
8644 pipe_config
->pipe_bpp
= 18;
8647 pipe_config
->pipe_bpp
= 24;
8649 case PIPECONF_10BPC
:
8650 pipe_config
->pipe_bpp
= 30;
8652 case PIPECONF_12BPC
:
8653 pipe_config
->pipe_bpp
= 36;
8659 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
8660 pipe_config
->limited_color_range
= true;
8662 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
8663 struct intel_shared_dpll
*pll
;
8664 enum intel_dpll_id pll_id
;
8666 pipe_config
->has_pch_encoder
= true;
8668 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
8669 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
8670 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
8672 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
8674 if (HAS_PCH_IBX(dev_priv
)) {
8676 * The pipe->pch transcoder and pch transcoder->pll
8679 pll_id
= (enum intel_dpll_id
) crtc
->pipe
;
8681 tmp
= I915_READ(PCH_DPLL_SEL
);
8682 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
8683 pll_id
= DPLL_ID_PCH_PLL_B
;
8685 pll_id
= DPLL_ID_PCH_PLL_A
;
8688 pipe_config
->shared_dpll
=
8689 intel_get_shared_dpll_by_id(dev_priv
, pll_id
);
8690 pll
= pipe_config
->shared_dpll
;
8692 WARN_ON(!pll
->funcs
.get_hw_state(dev_priv
, pll
,
8693 &pipe_config
->dpll_hw_state
));
8695 tmp
= pipe_config
->dpll_hw_state
.dpll
;
8696 pipe_config
->pixel_multiplier
=
8697 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
8698 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
8700 ironlake_pch_clock_get(crtc
, pipe_config
);
8702 pipe_config
->pixel_multiplier
= 1;
8705 intel_get_pipe_timings(crtc
, pipe_config
);
8706 intel_get_pipe_src_size(crtc
, pipe_config
);
8708 ironlake_get_pfit_config(crtc
, pipe_config
);
8713 intel_display_power_put(dev_priv
, power_domain
);
8718 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
8720 struct drm_device
*dev
= &dev_priv
->drm
;
8721 struct intel_crtc
*crtc
;
8723 for_each_intel_crtc(dev
, crtc
)
8724 I915_STATE_WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
8725 pipe_name(crtc
->pipe
));
8727 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL
)),
8728 "Display power well on\n");
8729 I915_STATE_WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
8730 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
8731 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
8732 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON
, "Panel power on\n");
8733 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
8734 "CPU PWM1 enabled\n");
8735 if (IS_HASWELL(dev_priv
))
8736 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
8737 "CPU PWM2 enabled\n");
8738 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
8739 "PCH PWM1 enabled\n");
8740 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
8741 "Utility pin enabled\n");
8742 I915_STATE_WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
8745 * In theory we can still leave IRQs enabled, as long as only the HPD
8746 * interrupts remain enabled. We used to check for that, but since it's
8747 * gen-specific and since we only disable LCPLL after we fully disable
8748 * the interrupts, the check below should be enough.
8750 I915_STATE_WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
8753 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
8755 if (IS_HASWELL(dev_priv
))
8756 return I915_READ(D_COMP_HSW
);
8758 return I915_READ(D_COMP_BDW
);
8761 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
8763 if (IS_HASWELL(dev_priv
)) {
8764 mutex_lock(&dev_priv
->pcu_lock
);
8765 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
8767 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8768 mutex_unlock(&dev_priv
->pcu_lock
);
8770 I915_WRITE(D_COMP_BDW
, val
);
8771 POSTING_READ(D_COMP_BDW
);
8776 * This function implements pieces of two sequences from BSpec:
8777 * - Sequence for display software to disable LCPLL
8778 * - Sequence for display software to allow package C8+
8779 * The steps implemented here are just the steps that actually touch the LCPLL
8780 * register. Callers should take care of disabling all the display engine
8781 * functions, doing the mode unset, fixing interrupts, etc.
8783 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
8784 bool switch_to_fclk
, bool allow_power_down
)
8788 assert_can_disable_lcpll(dev_priv
);
8790 val
= I915_READ(LCPLL_CTL
);
8792 if (switch_to_fclk
) {
8793 val
|= LCPLL_CD_SOURCE_FCLK
;
8794 I915_WRITE(LCPLL_CTL
, val
);
8796 if (wait_for_us(I915_READ(LCPLL_CTL
) &
8797 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
8798 DRM_ERROR("Switching to FCLK failed\n");
8800 val
= I915_READ(LCPLL_CTL
);
8803 val
|= LCPLL_PLL_DISABLE
;
8804 I915_WRITE(LCPLL_CTL
, val
);
8805 POSTING_READ(LCPLL_CTL
);
8807 if (intel_wait_for_register(dev_priv
, LCPLL_CTL
, LCPLL_PLL_LOCK
, 0, 1))
8808 DRM_ERROR("LCPLL still locked\n");
8810 val
= hsw_read_dcomp(dev_priv
);
8811 val
|= D_COMP_COMP_DISABLE
;
8812 hsw_write_dcomp(dev_priv
, val
);
8815 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
8817 DRM_ERROR("D_COMP RCOMP still in progress\n");
8819 if (allow_power_down
) {
8820 val
= I915_READ(LCPLL_CTL
);
8821 val
|= LCPLL_POWER_DOWN_ALLOW
;
8822 I915_WRITE(LCPLL_CTL
, val
);
8823 POSTING_READ(LCPLL_CTL
);
8828 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8831 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
8835 val
= I915_READ(LCPLL_CTL
);
8837 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
8838 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
8842 * Make sure we're not on PC8 state before disabling PC8, otherwise
8843 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8845 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
8847 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
8848 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
8849 I915_WRITE(LCPLL_CTL
, val
);
8850 POSTING_READ(LCPLL_CTL
);
8853 val
= hsw_read_dcomp(dev_priv
);
8854 val
|= D_COMP_COMP_FORCE
;
8855 val
&= ~D_COMP_COMP_DISABLE
;
8856 hsw_write_dcomp(dev_priv
, val
);
8858 val
= I915_READ(LCPLL_CTL
);
8859 val
&= ~LCPLL_PLL_DISABLE
;
8860 I915_WRITE(LCPLL_CTL
, val
);
8862 if (intel_wait_for_register(dev_priv
,
8863 LCPLL_CTL
, LCPLL_PLL_LOCK
, LCPLL_PLL_LOCK
,
8865 DRM_ERROR("LCPLL not locked yet\n");
8867 if (val
& LCPLL_CD_SOURCE_FCLK
) {
8868 val
= I915_READ(LCPLL_CTL
);
8869 val
&= ~LCPLL_CD_SOURCE_FCLK
;
8870 I915_WRITE(LCPLL_CTL
, val
);
8872 if (wait_for_us((I915_READ(LCPLL_CTL
) &
8873 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
8874 DRM_ERROR("Switching back to LCPLL failed\n");
8877 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
8878 intel_update_cdclk(dev_priv
);
8882 * Package states C8 and deeper are really deep PC states that can only be
8883 * reached when all the devices on the system allow it, so even if the graphics
8884 * device allows PC8+, it doesn't mean the system will actually get to these
8885 * states. Our driver only allows PC8+ when going into runtime PM.
8887 * The requirements for PC8+ are that all the outputs are disabled, the power
8888 * well is disabled and most interrupts are disabled, and these are also
8889 * requirements for runtime PM. When these conditions are met, we manually do
8890 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8891 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8894 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8895 * the state of some registers, so when we come back from PC8+ we need to
8896 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8897 * need to take care of the registers kept by RC6. Notice that this happens even
8898 * if we don't put the device in PCI D3 state (which is what currently happens
8899 * because of the runtime PM support).
8901 * For more, read "Display Sequences for Package C8" on the hardware
8904 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
8908 DRM_DEBUG_KMS("Enabling package C8+\n");
8910 if (HAS_PCH_LPT_LP(dev_priv
)) {
8911 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
8912 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
8913 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
8916 lpt_disable_clkout_dp(dev_priv
);
8917 hsw_disable_lcpll(dev_priv
, true, true);
8920 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
8924 DRM_DEBUG_KMS("Disabling package C8+\n");
8926 hsw_restore_lcpll(dev_priv
);
8927 lpt_init_pch_refclk(dev_priv
);
8929 if (HAS_PCH_LPT_LP(dev_priv
)) {
8930 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
8931 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
8932 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
8936 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
8937 struct intel_crtc_state
*crtc_state
)
8939 if (!intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DSI
)) {
8940 struct intel_encoder
*encoder
=
8941 intel_ddi_get_crtc_new_encoder(crtc_state
);
8943 if (!intel_get_shared_dpll(crtc
, crtc_state
, encoder
)) {
8944 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8945 pipe_name(crtc
->pipe
));
8953 static void cannonlake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
8955 struct intel_crtc_state
*pipe_config
)
8957 enum intel_dpll_id id
;
8960 temp
= I915_READ(DPCLKA_CFGCR0
) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port
);
8961 id
= temp
>> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port
);
8963 if (WARN_ON(id
< SKL_DPLL0
|| id
> SKL_DPLL2
))
8966 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
8969 static void bxt_get_ddi_pll(struct drm_i915_private
*dev_priv
,
8971 struct intel_crtc_state
*pipe_config
)
8973 enum intel_dpll_id id
;
8977 id
= DPLL_ID_SKL_DPLL0
;
8980 id
= DPLL_ID_SKL_DPLL1
;
8983 id
= DPLL_ID_SKL_DPLL2
;
8986 DRM_ERROR("Incorrect port type\n");
8990 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
8993 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
8995 struct intel_crtc_state
*pipe_config
)
8997 enum intel_dpll_id id
;
9000 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
9001 id
= temp
>> (port
* 3 + 1);
9003 if (WARN_ON(id
< SKL_DPLL0
|| id
> SKL_DPLL3
))
9006 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9009 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9011 struct intel_crtc_state
*pipe_config
)
9013 enum intel_dpll_id id
;
9014 uint32_t ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
9016 switch (ddi_pll_sel
) {
9017 case PORT_CLK_SEL_WRPLL1
:
9018 id
= DPLL_ID_WRPLL1
;
9020 case PORT_CLK_SEL_WRPLL2
:
9021 id
= DPLL_ID_WRPLL2
;
9023 case PORT_CLK_SEL_SPLL
:
9026 case PORT_CLK_SEL_LCPLL_810
:
9027 id
= DPLL_ID_LCPLL_810
;
9029 case PORT_CLK_SEL_LCPLL_1350
:
9030 id
= DPLL_ID_LCPLL_1350
;
9032 case PORT_CLK_SEL_LCPLL_2700
:
9033 id
= DPLL_ID_LCPLL_2700
;
9036 MISSING_CASE(ddi_pll_sel
);
9038 case PORT_CLK_SEL_NONE
:
9042 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9045 static bool hsw_get_transcoder_state(struct intel_crtc
*crtc
,
9046 struct intel_crtc_state
*pipe_config
,
9047 u64
*power_domain_mask
)
9049 struct drm_device
*dev
= crtc
->base
.dev
;
9050 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9051 enum intel_display_power_domain power_domain
;
9055 * The pipe->transcoder mapping is fixed with the exception of the eDP
9056 * transcoder handled below.
9058 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9061 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9062 * consistency and less surprising code; it's in always on power).
9064 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
9065 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
9066 enum pipe trans_edp_pipe
;
9067 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
9069 WARN(1, "unknown pipe linked to edp transcoder\n");
9070 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
9071 case TRANS_DDI_EDP_INPUT_A_ON
:
9072 trans_edp_pipe
= PIPE_A
;
9074 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
9075 trans_edp_pipe
= PIPE_B
;
9077 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
9078 trans_edp_pipe
= PIPE_C
;
9082 if (trans_edp_pipe
== crtc
->pipe
)
9083 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
9086 power_domain
= POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
);
9087 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
9089 *power_domain_mask
|= BIT_ULL(power_domain
);
9091 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
9093 return tmp
& PIPECONF_ENABLE
;
9096 static bool bxt_get_dsi_transcoder_state(struct intel_crtc
*crtc
,
9097 struct intel_crtc_state
*pipe_config
,
9098 u64
*power_domain_mask
)
9100 struct drm_device
*dev
= crtc
->base
.dev
;
9101 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9102 enum intel_display_power_domain power_domain
;
9104 enum transcoder cpu_transcoder
;
9107 for_each_port_masked(port
, BIT(PORT_A
) | BIT(PORT_C
)) {
9109 cpu_transcoder
= TRANSCODER_DSI_A
;
9111 cpu_transcoder
= TRANSCODER_DSI_C
;
9113 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
9114 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
9116 *power_domain_mask
|= BIT_ULL(power_domain
);
9119 * The PLL needs to be enabled with a valid divider
9120 * configuration, otherwise accessing DSI registers will hang
9121 * the machine. See BSpec North Display Engine
9122 * registers/MIPI[BXT]. We can break out here early, since we
9123 * need the same DSI PLL to be enabled for both DSI ports.
9125 if (!intel_dsi_pll_is_enabled(dev_priv
))
9128 /* XXX: this works for video mode only */
9129 tmp
= I915_READ(BXT_MIPI_PORT_CTRL(port
));
9130 if (!(tmp
& DPI_ENABLE
))
9133 tmp
= I915_READ(MIPI_CTRL(port
));
9134 if ((tmp
& BXT_PIPE_SELECT_MASK
) != BXT_PIPE_SELECT(crtc
->pipe
))
9137 pipe_config
->cpu_transcoder
= cpu_transcoder
;
9141 return transcoder_is_dsi(pipe_config
->cpu_transcoder
);
9144 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
9145 struct intel_crtc_state
*pipe_config
)
9147 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9148 struct intel_shared_dpll
*pll
;
9152 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
9154 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
9156 if (IS_CANNONLAKE(dev_priv
))
9157 cannonlake_get_ddi_pll(dev_priv
, port
, pipe_config
);
9158 else if (IS_GEN9_BC(dev_priv
))
9159 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
9160 else if (IS_GEN9_LP(dev_priv
))
9161 bxt_get_ddi_pll(dev_priv
, port
, pipe_config
);
9163 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
9165 pll
= pipe_config
->shared_dpll
;
9167 WARN_ON(!pll
->funcs
.get_hw_state(dev_priv
, pll
,
9168 &pipe_config
->dpll_hw_state
));
9172 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9173 * DDI E. So just check whether this pipe is wired to DDI E and whether
9174 * the PCH transcoder is on.
9176 if (INTEL_GEN(dev_priv
) < 9 &&
9177 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
9178 pipe_config
->has_pch_encoder
= true;
9180 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
9181 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9182 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9184 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9188 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
9189 struct intel_crtc_state
*pipe_config
)
9191 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9192 enum intel_display_power_domain power_domain
;
9193 u64 power_domain_mask
;
9196 intel_crtc_init_scalers(crtc
, pipe_config
);
9198 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
9199 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
9201 power_domain_mask
= BIT_ULL(power_domain
);
9203 pipe_config
->shared_dpll
= NULL
;
9205 active
= hsw_get_transcoder_state(crtc
, pipe_config
, &power_domain_mask
);
9207 if (IS_GEN9_LP(dev_priv
) &&
9208 bxt_get_dsi_transcoder_state(crtc
, pipe_config
, &power_domain_mask
)) {
9216 if (!transcoder_is_dsi(pipe_config
->cpu_transcoder
)) {
9217 haswell_get_ddi_port_state(crtc
, pipe_config
);
9218 intel_get_pipe_timings(crtc
, pipe_config
);
9221 intel_get_pipe_src_size(crtc
, pipe_config
);
9223 pipe_config
->gamma_mode
=
9224 I915_READ(GAMMA_MODE(crtc
->pipe
)) & GAMMA_MODE_MODE_MASK
;
9226 if (IS_BROADWELL(dev_priv
) || INTEL_GEN(dev_priv
) >= 9) {
9227 u32 tmp
= I915_READ(PIPEMISC(crtc
->pipe
));
9228 bool clrspace_yuv
= tmp
& PIPEMISC_OUTPUT_COLORSPACE_YUV
;
9230 if (IS_GEMINILAKE(dev_priv
) || INTEL_GEN(dev_priv
) >= 10) {
9231 bool blend_mode_420
= tmp
&
9232 PIPEMISC_YUV420_MODE_FULL_BLEND
;
9234 pipe_config
->ycbcr420
= tmp
& PIPEMISC_YUV420_ENABLE
;
9235 if (pipe_config
->ycbcr420
!= clrspace_yuv
||
9236 pipe_config
->ycbcr420
!= blend_mode_420
)
9237 DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp
);
9238 } else if (clrspace_yuv
) {
9239 DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n");
9243 power_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
9244 if (intel_display_power_get_if_enabled(dev_priv
, power_domain
)) {
9245 power_domain_mask
|= BIT_ULL(power_domain
);
9246 if (INTEL_GEN(dev_priv
) >= 9)
9247 skylake_get_pfit_config(crtc
, pipe_config
);
9249 ironlake_get_pfit_config(crtc
, pipe_config
);
9252 if (IS_HASWELL(dev_priv
))
9253 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
9254 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
9256 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
&&
9257 !transcoder_is_dsi(pipe_config
->cpu_transcoder
)) {
9258 pipe_config
->pixel_multiplier
=
9259 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
9261 pipe_config
->pixel_multiplier
= 1;
9265 for_each_power_domain(power_domain
, power_domain_mask
)
9266 intel_display_power_put(dev_priv
, power_domain
);
9271 static u32
intel_cursor_base(const struct intel_plane_state
*plane_state
)
9273 struct drm_i915_private
*dev_priv
=
9274 to_i915(plane_state
->base
.plane
->dev
);
9275 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
9276 const struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
9279 if (INTEL_INFO(dev_priv
)->cursor_needs_physical
)
9280 base
= obj
->phys_handle
->busaddr
;
9282 base
= intel_plane_ggtt_offset(plane_state
);
9284 base
+= plane_state
->main
.offset
;
9286 /* ILK+ do this automagically */
9287 if (HAS_GMCH_DISPLAY(dev_priv
) &&
9288 plane_state
->base
.rotation
& DRM_MODE_ROTATE_180
)
9289 base
+= (plane_state
->base
.crtc_h
*
9290 plane_state
->base
.crtc_w
- 1) * fb
->format
->cpp
[0];
9295 static u32
intel_cursor_position(const struct intel_plane_state
*plane_state
)
9297 int x
= plane_state
->base
.crtc_x
;
9298 int y
= plane_state
->base
.crtc_y
;
9302 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
9305 pos
|= x
<< CURSOR_X_SHIFT
;
9308 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
9311 pos
|= y
<< CURSOR_Y_SHIFT
;
9316 static bool intel_cursor_size_ok(const struct intel_plane_state
*plane_state
)
9318 const struct drm_mode_config
*config
=
9319 &plane_state
->base
.plane
->dev
->mode_config
;
9320 int width
= plane_state
->base
.crtc_w
;
9321 int height
= plane_state
->base
.crtc_h
;
9323 return width
> 0 && width
<= config
->cursor_width
&&
9324 height
> 0 && height
<= config
->cursor_height
;
9327 static int intel_check_cursor(struct intel_crtc_state
*crtc_state
,
9328 struct intel_plane_state
*plane_state
)
9330 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
9335 ret
= drm_plane_helper_check_state(&plane_state
->base
,
9337 DRM_PLANE_HELPER_NO_SCALING
,
9338 DRM_PLANE_HELPER_NO_SCALING
,
9346 if (fb
->modifier
!= DRM_FORMAT_MOD_LINEAR
) {
9347 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9351 src_x
= plane_state
->base
.src_x
>> 16;
9352 src_y
= plane_state
->base
.src_y
>> 16;
9354 intel_add_fb_offsets(&src_x
, &src_y
, plane_state
, 0);
9355 offset
= intel_compute_tile_offset(&src_x
, &src_y
, plane_state
, 0);
9357 if (src_x
!= 0 || src_y
!= 0) {
9358 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9362 plane_state
->main
.offset
= offset
;
9367 static u32
i845_cursor_ctl(const struct intel_crtc_state
*crtc_state
,
9368 const struct intel_plane_state
*plane_state
)
9370 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
9372 return CURSOR_ENABLE
|
9373 CURSOR_GAMMA_ENABLE
|
9374 CURSOR_FORMAT_ARGB
|
9375 CURSOR_STRIDE(fb
->pitches
[0]);
9378 static bool i845_cursor_size_ok(const struct intel_plane_state
*plane_state
)
9380 int width
= plane_state
->base
.crtc_w
;
9383 * 845g/865g are only limited by the width of their cursors,
9384 * the height is arbitrary up to the precision of the register.
9386 return intel_cursor_size_ok(plane_state
) && IS_ALIGNED(width
, 64);
9389 static int i845_check_cursor(struct intel_plane
*plane
,
9390 struct intel_crtc_state
*crtc_state
,
9391 struct intel_plane_state
*plane_state
)
9393 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
9396 ret
= intel_check_cursor(crtc_state
, plane_state
);
9400 /* if we want to turn off the cursor ignore width and height */
9404 /* Check for which cursor types we support */
9405 if (!i845_cursor_size_ok(plane_state
)) {
9406 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9407 plane_state
->base
.crtc_w
,
9408 plane_state
->base
.crtc_h
);
9412 switch (fb
->pitches
[0]) {
9419 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9424 plane_state
->ctl
= i845_cursor_ctl(crtc_state
, plane_state
);
9429 static void i845_update_cursor(struct intel_plane
*plane
,
9430 const struct intel_crtc_state
*crtc_state
,
9431 const struct intel_plane_state
*plane_state
)
9433 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
9434 u32 cntl
= 0, base
= 0, pos
= 0, size
= 0;
9435 unsigned long irqflags
;
9437 if (plane_state
&& plane_state
->base
.visible
) {
9438 unsigned int width
= plane_state
->base
.crtc_w
;
9439 unsigned int height
= plane_state
->base
.crtc_h
;
9441 cntl
= plane_state
->ctl
;
9442 size
= (height
<< 12) | width
;
9444 base
= intel_cursor_base(plane_state
);
9445 pos
= intel_cursor_position(plane_state
);
9448 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
9450 /* On these chipsets we can only modify the base/size/stride
9451 * whilst the cursor is disabled.
9453 if (plane
->cursor
.base
!= base
||
9454 plane
->cursor
.size
!= size
||
9455 plane
->cursor
.cntl
!= cntl
) {
9456 I915_WRITE_FW(CURCNTR(PIPE_A
), 0);
9457 I915_WRITE_FW(CURBASE(PIPE_A
), base
);
9458 I915_WRITE_FW(CURSIZE
, size
);
9459 I915_WRITE_FW(CURPOS(PIPE_A
), pos
);
9460 I915_WRITE_FW(CURCNTR(PIPE_A
), cntl
);
9462 plane
->cursor
.base
= base
;
9463 plane
->cursor
.size
= size
;
9464 plane
->cursor
.cntl
= cntl
;
9466 I915_WRITE_FW(CURPOS(PIPE_A
), pos
);
9469 POSTING_READ_FW(CURCNTR(PIPE_A
));
9471 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
9474 static void i845_disable_cursor(struct intel_plane
*plane
,
9475 struct intel_crtc
*crtc
)
9477 i845_update_cursor(plane
, NULL
, NULL
);
9480 static u32
i9xx_cursor_ctl(const struct intel_crtc_state
*crtc_state
,
9481 const struct intel_plane_state
*plane_state
)
9483 struct drm_i915_private
*dev_priv
=
9484 to_i915(plane_state
->base
.plane
->dev
);
9485 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
9488 cntl
= MCURSOR_GAMMA_ENABLE
;
9490 if (HAS_DDI(dev_priv
))
9491 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
9493 cntl
|= MCURSOR_PIPE_SELECT(crtc
->pipe
);
9495 switch (plane_state
->base
.crtc_w
) {
9497 cntl
|= CURSOR_MODE_64_ARGB_AX
;
9500 cntl
|= CURSOR_MODE_128_ARGB_AX
;
9503 cntl
|= CURSOR_MODE_256_ARGB_AX
;
9506 MISSING_CASE(plane_state
->base
.crtc_w
);
9510 if (plane_state
->base
.rotation
& DRM_MODE_ROTATE_180
)
9511 cntl
|= CURSOR_ROTATE_180
;
9516 static bool i9xx_cursor_size_ok(const struct intel_plane_state
*plane_state
)
9518 struct drm_i915_private
*dev_priv
=
9519 to_i915(plane_state
->base
.plane
->dev
);
9520 int width
= plane_state
->base
.crtc_w
;
9521 int height
= plane_state
->base
.crtc_h
;
9523 if (!intel_cursor_size_ok(plane_state
))
9526 /* Cursor width is limited to a few power-of-two sizes */
9537 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9538 * height from 8 lines up to the cursor width, when the
9539 * cursor is not rotated. Everything else requires square
9542 if (HAS_CUR_FBC(dev_priv
) &&
9543 plane_state
->base
.rotation
& DRM_MODE_ROTATE_0
) {
9544 if (height
< 8 || height
> width
)
9547 if (height
!= width
)
9554 static int i9xx_check_cursor(struct intel_plane
*plane
,
9555 struct intel_crtc_state
*crtc_state
,
9556 struct intel_plane_state
*plane_state
)
9558 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
9559 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
9560 enum pipe pipe
= plane
->pipe
;
9563 ret
= intel_check_cursor(crtc_state
, plane_state
);
9567 /* if we want to turn off the cursor ignore width and height */
9571 /* Check for which cursor types we support */
9572 if (!i9xx_cursor_size_ok(plane_state
)) {
9573 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9574 plane_state
->base
.crtc_w
,
9575 plane_state
->base
.crtc_h
);
9579 if (fb
->pitches
[0] != plane_state
->base
.crtc_w
* fb
->format
->cpp
[0]) {
9580 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9581 fb
->pitches
[0], plane_state
->base
.crtc_w
);
9586 * There's something wrong with the cursor on CHV pipe C.
9587 * If it straddles the left edge of the screen then
9588 * moving it away from the edge or disabling it often
9589 * results in a pipe underrun, and often that can lead to
9590 * dead pipe (constant underrun reported, and it scans
9591 * out just a solid color). To recover from that, the
9592 * display power well must be turned off and on again.
9593 * Refuse the put the cursor into that compromised position.
9595 if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_C
&&
9596 plane_state
->base
.visible
&& plane_state
->base
.crtc_x
< 0) {
9597 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9601 plane_state
->ctl
= i9xx_cursor_ctl(crtc_state
, plane_state
);
9606 static void i9xx_update_cursor(struct intel_plane
*plane
,
9607 const struct intel_crtc_state
*crtc_state
,
9608 const struct intel_plane_state
*plane_state
)
9610 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
9611 enum pipe pipe
= plane
->pipe
;
9612 u32 cntl
= 0, base
= 0, pos
= 0, fbc_ctl
= 0;
9613 unsigned long irqflags
;
9615 if (plane_state
&& plane_state
->base
.visible
) {
9616 cntl
= plane_state
->ctl
;
9618 if (plane_state
->base
.crtc_h
!= plane_state
->base
.crtc_w
)
9619 fbc_ctl
= CUR_FBC_CTL_EN
| (plane_state
->base
.crtc_h
- 1);
9621 base
= intel_cursor_base(plane_state
);
9622 pos
= intel_cursor_position(plane_state
);
9625 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
9628 * On some platforms writing CURCNTR first will also
9629 * cause CURPOS to be armed by the CURBASE write.
9630 * Without the CURCNTR write the CURPOS write would
9631 * arm itself. Thus we always start the full update
9632 * with a CURCNTR write.
9634 * On other platforms CURPOS always requires the
9635 * CURBASE write to arm the update. Additonally
9636 * a write to any of the cursor register will cancel
9637 * an already armed cursor update. Thus leaving out
9638 * the CURBASE write after CURPOS could lead to a
9639 * cursor that doesn't appear to move, or even change
9640 * shape. Thus we always write CURBASE.
9642 * CURCNTR and CUR_FBC_CTL are always
9643 * armed by the CURBASE write only.
9645 if (plane
->cursor
.base
!= base
||
9646 plane
->cursor
.size
!= fbc_ctl
||
9647 plane
->cursor
.cntl
!= cntl
) {
9648 I915_WRITE_FW(CURCNTR(pipe
), cntl
);
9649 if (HAS_CUR_FBC(dev_priv
))
9650 I915_WRITE_FW(CUR_FBC_CTL(pipe
), fbc_ctl
);
9651 I915_WRITE_FW(CURPOS(pipe
), pos
);
9652 I915_WRITE_FW(CURBASE(pipe
), base
);
9654 plane
->cursor
.base
= base
;
9655 plane
->cursor
.size
= fbc_ctl
;
9656 plane
->cursor
.cntl
= cntl
;
9658 I915_WRITE_FW(CURPOS(pipe
), pos
);
9659 I915_WRITE_FW(CURBASE(pipe
), base
);
9662 POSTING_READ_FW(CURBASE(pipe
));
9664 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
9667 static void i9xx_disable_cursor(struct intel_plane
*plane
,
9668 struct intel_crtc
*crtc
)
9670 i9xx_update_cursor(plane
, NULL
, NULL
);
9674 /* VESA 640x480x72Hz mode to set on the pipe */
9675 static const struct drm_display_mode load_detect_mode
= {
9676 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
9677 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
9680 struct drm_framebuffer
*
9681 intel_framebuffer_create(struct drm_i915_gem_object
*obj
,
9682 struct drm_mode_fb_cmd2
*mode_cmd
)
9684 struct intel_framebuffer
*intel_fb
;
9687 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9689 return ERR_PTR(-ENOMEM
);
9691 ret
= intel_framebuffer_init(intel_fb
, obj
, mode_cmd
);
9695 return &intel_fb
->base
;
9699 return ERR_PTR(ret
);
9703 intel_framebuffer_pitch_for_width(int width
, int bpp
)
9705 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
9706 return ALIGN(pitch
, 64);
9710 intel_framebuffer_size_for_mode(const struct drm_display_mode
*mode
, int bpp
)
9712 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
9713 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
9716 static struct drm_framebuffer
*
9717 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
9718 const struct drm_display_mode
*mode
,
9721 struct drm_framebuffer
*fb
;
9722 struct drm_i915_gem_object
*obj
;
9723 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
9725 obj
= i915_gem_object_create(to_i915(dev
),
9726 intel_framebuffer_size_for_mode(mode
, bpp
));
9728 return ERR_CAST(obj
);
9730 mode_cmd
.width
= mode
->hdisplay
;
9731 mode_cmd
.height
= mode
->vdisplay
;
9732 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
9734 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
9736 fb
= intel_framebuffer_create(obj
, &mode_cmd
);
9738 i915_gem_object_put(obj
);
9743 static struct drm_framebuffer
*
9744 mode_fits_in_fbdev(struct drm_device
*dev
,
9745 const struct drm_display_mode
*mode
)
9747 #ifdef CONFIG_DRM_FBDEV_EMULATION
9748 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9749 struct drm_i915_gem_object
*obj
;
9750 struct drm_framebuffer
*fb
;
9752 if (!dev_priv
->fbdev
)
9755 if (!dev_priv
->fbdev
->fb
)
9758 obj
= dev_priv
->fbdev
->fb
->obj
;
9761 fb
= &dev_priv
->fbdev
->fb
->base
;
9762 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
9763 fb
->format
->cpp
[0] * 8))
9766 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
9769 drm_framebuffer_get(fb
);
9776 static int intel_modeset_setup_plane_state(struct drm_atomic_state
*state
,
9777 struct drm_crtc
*crtc
,
9778 const struct drm_display_mode
*mode
,
9779 struct drm_framebuffer
*fb
,
9782 struct drm_plane_state
*plane_state
;
9783 int hdisplay
, vdisplay
;
9786 plane_state
= drm_atomic_get_plane_state(state
, crtc
->primary
);
9787 if (IS_ERR(plane_state
))
9788 return PTR_ERR(plane_state
);
9791 drm_mode_get_hv_timing(mode
, &hdisplay
, &vdisplay
);
9793 hdisplay
= vdisplay
= 0;
9795 ret
= drm_atomic_set_crtc_for_plane(plane_state
, fb
? crtc
: NULL
);
9798 drm_atomic_set_fb_for_plane(plane_state
, fb
);
9799 plane_state
->crtc_x
= 0;
9800 plane_state
->crtc_y
= 0;
9801 plane_state
->crtc_w
= hdisplay
;
9802 plane_state
->crtc_h
= vdisplay
;
9803 plane_state
->src_x
= x
<< 16;
9804 plane_state
->src_y
= y
<< 16;
9805 plane_state
->src_w
= hdisplay
<< 16;
9806 plane_state
->src_h
= vdisplay
<< 16;
9811 int intel_get_load_detect_pipe(struct drm_connector
*connector
,
9812 const struct drm_display_mode
*mode
,
9813 struct intel_load_detect_pipe
*old
,
9814 struct drm_modeset_acquire_ctx
*ctx
)
9816 struct intel_crtc
*intel_crtc
;
9817 struct intel_encoder
*intel_encoder
=
9818 intel_attached_encoder(connector
);
9819 struct drm_crtc
*possible_crtc
;
9820 struct drm_encoder
*encoder
= &intel_encoder
->base
;
9821 struct drm_crtc
*crtc
= NULL
;
9822 struct drm_device
*dev
= encoder
->dev
;
9823 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9824 struct drm_framebuffer
*fb
;
9825 struct drm_mode_config
*config
= &dev
->mode_config
;
9826 struct drm_atomic_state
*state
= NULL
, *restore_state
= NULL
;
9827 struct drm_connector_state
*connector_state
;
9828 struct intel_crtc_state
*crtc_state
;
9831 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9832 connector
->base
.id
, connector
->name
,
9833 encoder
->base
.id
, encoder
->name
);
9835 old
->restore_state
= NULL
;
9837 WARN_ON(!drm_modeset_is_locked(&config
->connection_mutex
));
9840 * Algorithm gets a little messy:
9842 * - if the connector already has an assigned crtc, use it (but make
9843 * sure it's on first)
9845 * - try to find the first unused crtc that can drive this connector,
9846 * and use that if we find one
9849 /* See if we already have a CRTC for this connector */
9850 if (connector
->state
->crtc
) {
9851 crtc
= connector
->state
->crtc
;
9853 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
9857 /* Make sure the crtc and connector are running */
9861 /* Find an unused one (if possible) */
9862 for_each_crtc(dev
, possible_crtc
) {
9864 if (!(encoder
->possible_crtcs
& (1 << i
)))
9867 ret
= drm_modeset_lock(&possible_crtc
->mutex
, ctx
);
9871 if (possible_crtc
->state
->enable
) {
9872 drm_modeset_unlock(&possible_crtc
->mutex
);
9876 crtc
= possible_crtc
;
9881 * If we didn't find an unused CRTC, don't use any.
9884 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9890 intel_crtc
= to_intel_crtc(crtc
);
9892 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
9896 state
= drm_atomic_state_alloc(dev
);
9897 restore_state
= drm_atomic_state_alloc(dev
);
9898 if (!state
|| !restore_state
) {
9903 state
->acquire_ctx
= ctx
;
9904 restore_state
->acquire_ctx
= ctx
;
9906 connector_state
= drm_atomic_get_connector_state(state
, connector
);
9907 if (IS_ERR(connector_state
)) {
9908 ret
= PTR_ERR(connector_state
);
9912 ret
= drm_atomic_set_crtc_for_connector(connector_state
, crtc
);
9916 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
9917 if (IS_ERR(crtc_state
)) {
9918 ret
= PTR_ERR(crtc_state
);
9922 crtc_state
->base
.active
= crtc_state
->base
.enable
= true;
9925 mode
= &load_detect_mode
;
9927 /* We need a framebuffer large enough to accommodate all accesses
9928 * that the plane may generate whilst we perform load detection.
9929 * We can not rely on the fbcon either being present (we get called
9930 * during its initialisation to detect all boot displays, or it may
9931 * not even exist) or that it is large enough to satisfy the
9934 fb
= mode_fits_in_fbdev(dev
, mode
);
9936 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9937 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
9939 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9941 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9946 ret
= intel_modeset_setup_plane_state(state
, crtc
, mode
, fb
, 0, 0);
9950 drm_framebuffer_put(fb
);
9952 ret
= drm_atomic_set_mode_for_crtc(&crtc_state
->base
, mode
);
9956 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state
, connector
));
9958 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state
, crtc
));
9960 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state
, crtc
->primary
));
9962 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret
);
9966 ret
= drm_atomic_commit(state
);
9968 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9972 old
->restore_state
= restore_state
;
9973 drm_atomic_state_put(state
);
9975 /* let the connector get through one full cycle before testing */
9976 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
9981 drm_atomic_state_put(state
);
9984 if (restore_state
) {
9985 drm_atomic_state_put(restore_state
);
9986 restore_state
= NULL
;
9989 if (ret
== -EDEADLK
)
9995 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
9996 struct intel_load_detect_pipe
*old
,
9997 struct drm_modeset_acquire_ctx
*ctx
)
9999 struct intel_encoder
*intel_encoder
=
10000 intel_attached_encoder(connector
);
10001 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10002 struct drm_atomic_state
*state
= old
->restore_state
;
10005 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10006 connector
->base
.id
, connector
->name
,
10007 encoder
->base
.id
, encoder
->name
);
10012 ret
= drm_atomic_helper_commit_duplicated_state(state
, ctx
);
10014 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret
);
10015 drm_atomic_state_put(state
);
10018 static int i9xx_pll_refclk(struct drm_device
*dev
,
10019 const struct intel_crtc_state
*pipe_config
)
10021 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10022 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10024 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
10025 return dev_priv
->vbt
.lvds_ssc_freq
;
10026 else if (HAS_PCH_SPLIT(dev_priv
))
10028 else if (!IS_GEN2(dev_priv
))
10034 /* Returns the clock of the currently programmed mode of the given pipe. */
10035 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
10036 struct intel_crtc_state
*pipe_config
)
10038 struct drm_device
*dev
= crtc
->base
.dev
;
10039 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10040 int pipe
= pipe_config
->cpu_transcoder
;
10041 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10045 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
10047 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
10048 fp
= pipe_config
->dpll_hw_state
.fp0
;
10050 fp
= pipe_config
->dpll_hw_state
.fp1
;
10052 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
10053 if (IS_PINEVIEW(dev_priv
)) {
10054 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
10055 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10057 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
10058 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10061 if (!IS_GEN2(dev_priv
)) {
10062 if (IS_PINEVIEW(dev_priv
))
10063 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
10064 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
10066 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
10067 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10069 switch (dpll
& DPLL_MODE_MASK
) {
10070 case DPLLB_MODE_DAC_SERIAL
:
10071 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
10074 case DPLLB_MODE_LVDS
:
10075 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
10079 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10080 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
10084 if (IS_PINEVIEW(dev_priv
))
10085 port_clock
= pnv_calc_dpll_params(refclk
, &clock
);
10087 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
10089 u32 lvds
= IS_I830(dev_priv
) ? 0 : I915_READ(LVDS
);
10090 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
10093 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
10094 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10096 if (lvds
& LVDS_CLKB_POWER_UP
)
10101 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
10104 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
10105 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
10107 if (dpll
& PLL_P2_DIVIDE_BY_4
)
10113 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
10117 * This value includes pixel_multiplier. We will use
10118 * port_clock to compute adjusted_mode.crtc_clock in the
10119 * encoder's get_config() function.
10121 pipe_config
->port_clock
= port_clock
;
10124 int intel_dotclock_calculate(int link_freq
,
10125 const struct intel_link_m_n
*m_n
)
10128 * The calculation for the data clock is:
10129 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10130 * But we want to avoid losing precison if possible, so:
10131 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10133 * and the link clock is simpler:
10134 * link_clock = (m * link_clock) / n
10140 return div_u64(mul_u32_u32(m_n
->link_m
, link_freq
), m_n
->link_n
);
10143 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
10144 struct intel_crtc_state
*pipe_config
)
10146 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
10148 /* read out port_clock from the DPLL */
10149 i9xx_crtc_clock_get(crtc
, pipe_config
);
10152 * In case there is an active pipe without active ports,
10153 * we may need some idea for the dotclock anyway.
10154 * Calculate one based on the FDI configuration.
10156 pipe_config
->base
.adjusted_mode
.crtc_clock
=
10157 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv
, pipe_config
),
10158 &pipe_config
->fdi_m_n
);
10161 /* Returns the currently programmed mode of the given encoder. */
10162 struct drm_display_mode
*
10163 intel_encoder_current_mode(struct intel_encoder
*encoder
)
10165 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
10166 struct intel_crtc_state
*crtc_state
;
10167 struct drm_display_mode
*mode
;
10168 struct intel_crtc
*crtc
;
10171 if (!encoder
->get_hw_state(encoder
, &pipe
))
10174 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
10176 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
10180 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
10186 crtc_state
->base
.crtc
= &crtc
->base
;
10188 if (!dev_priv
->display
.get_pipe_config(crtc
, crtc_state
)) {
10194 encoder
->get_config(encoder
, crtc_state
);
10196 intel_mode_from_pipe_config(mode
, crtc_state
);
10203 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
10205 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10207 drm_crtc_cleanup(crtc
);
10212 * intel_wm_need_update - Check whether watermarks need updating
10213 * @plane: drm plane
10214 * @state: new plane state
10216 * Check current plane state versus the new one to determine whether
10217 * watermarks need to be recalculated.
10219 * Returns true or false.
10221 static bool intel_wm_need_update(struct drm_plane
*plane
,
10222 struct drm_plane_state
*state
)
10224 struct intel_plane_state
*new = to_intel_plane_state(state
);
10225 struct intel_plane_state
*cur
= to_intel_plane_state(plane
->state
);
10227 /* Update watermarks on tiling or size changes. */
10228 if (new->base
.visible
!= cur
->base
.visible
)
10231 if (!cur
->base
.fb
|| !new->base
.fb
)
10234 if (cur
->base
.fb
->modifier
!= new->base
.fb
->modifier
||
10235 cur
->base
.rotation
!= new->base
.rotation
||
10236 drm_rect_width(&new->base
.src
) != drm_rect_width(&cur
->base
.src
) ||
10237 drm_rect_height(&new->base
.src
) != drm_rect_height(&cur
->base
.src
) ||
10238 drm_rect_width(&new->base
.dst
) != drm_rect_width(&cur
->base
.dst
) ||
10239 drm_rect_height(&new->base
.dst
) != drm_rect_height(&cur
->base
.dst
))
10245 static bool needs_scaling(const struct intel_plane_state
*state
)
10247 int src_w
= drm_rect_width(&state
->base
.src
) >> 16;
10248 int src_h
= drm_rect_height(&state
->base
.src
) >> 16;
10249 int dst_w
= drm_rect_width(&state
->base
.dst
);
10250 int dst_h
= drm_rect_height(&state
->base
.dst
);
10252 return (src_w
!= dst_w
|| src_h
!= dst_h
);
10255 int intel_plane_atomic_calc_changes(const struct intel_crtc_state
*old_crtc_state
,
10256 struct drm_crtc_state
*crtc_state
,
10257 const struct intel_plane_state
*old_plane_state
,
10258 struct drm_plane_state
*plane_state
)
10260 struct intel_crtc_state
*pipe_config
= to_intel_crtc_state(crtc_state
);
10261 struct drm_crtc
*crtc
= crtc_state
->crtc
;
10262 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10263 struct intel_plane
*plane
= to_intel_plane(plane_state
->plane
);
10264 struct drm_device
*dev
= crtc
->dev
;
10265 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10266 bool mode_changed
= needs_modeset(crtc_state
);
10267 bool was_crtc_enabled
= old_crtc_state
->base
.active
;
10268 bool is_crtc_enabled
= crtc_state
->active
;
10269 bool turn_off
, turn_on
, visible
, was_visible
;
10270 struct drm_framebuffer
*fb
= plane_state
->fb
;
10273 if (INTEL_GEN(dev_priv
) >= 9 && plane
->id
!= PLANE_CURSOR
) {
10274 ret
= skl_update_scaler_plane(
10275 to_intel_crtc_state(crtc_state
),
10276 to_intel_plane_state(plane_state
));
10281 was_visible
= old_plane_state
->base
.visible
;
10282 visible
= plane_state
->visible
;
10284 if (!was_crtc_enabled
&& WARN_ON(was_visible
))
10285 was_visible
= false;
10288 * Visibility is calculated as if the crtc was on, but
10289 * after scaler setup everything depends on it being off
10290 * when the crtc isn't active.
10292 * FIXME this is wrong for watermarks. Watermarks should also
10293 * be computed as if the pipe would be active. Perhaps move
10294 * per-plane wm computation to the .check_plane() hook, and
10295 * only combine the results from all planes in the current place?
10297 if (!is_crtc_enabled
) {
10298 plane_state
->visible
= visible
= false;
10299 to_intel_crtc_state(crtc_state
)->active_planes
&= ~BIT(plane
->id
);
10302 if (!was_visible
&& !visible
)
10305 if (fb
!= old_plane_state
->base
.fb
)
10306 pipe_config
->fb_changed
= true;
10308 turn_off
= was_visible
&& (!visible
|| mode_changed
);
10309 turn_on
= visible
&& (!was_visible
|| mode_changed
);
10311 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10312 intel_crtc
->base
.base
.id
, intel_crtc
->base
.name
,
10313 plane
->base
.base
.id
, plane
->base
.name
,
10314 fb
? fb
->base
.id
: -1);
10316 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10317 plane
->base
.base
.id
, plane
->base
.name
,
10318 was_visible
, visible
,
10319 turn_off
, turn_on
, mode_changed
);
10322 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
))
10323 pipe_config
->update_wm_pre
= true;
10325 /* must disable cxsr around plane enable/disable */
10326 if (plane
->id
!= PLANE_CURSOR
)
10327 pipe_config
->disable_cxsr
= true;
10328 } else if (turn_off
) {
10329 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
))
10330 pipe_config
->update_wm_post
= true;
10332 /* must disable cxsr around plane enable/disable */
10333 if (plane
->id
!= PLANE_CURSOR
)
10334 pipe_config
->disable_cxsr
= true;
10335 } else if (intel_wm_need_update(&plane
->base
, plane_state
)) {
10336 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
)) {
10337 /* FIXME bollocks */
10338 pipe_config
->update_wm_pre
= true;
10339 pipe_config
->update_wm_post
= true;
10343 if (visible
|| was_visible
)
10344 pipe_config
->fb_bits
|= plane
->frontbuffer_bit
;
10347 * WaCxSRDisabledForSpriteScaling:ivb
10349 * cstate->update_wm was already set above, so this flag will
10350 * take effect when we commit and program watermarks.
10352 if (plane
->id
== PLANE_SPRITE0
&& IS_IVYBRIDGE(dev_priv
) &&
10353 needs_scaling(to_intel_plane_state(plane_state
)) &&
10354 !needs_scaling(old_plane_state
))
10355 pipe_config
->disable_lp_wm
= true;
10360 static bool encoders_cloneable(const struct intel_encoder
*a
,
10361 const struct intel_encoder
*b
)
10363 /* masks could be asymmetric, so check both ways */
10364 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
10365 b
->cloneable
& (1 << a
->type
));
10368 static bool check_single_encoder_cloning(struct drm_atomic_state
*state
,
10369 struct intel_crtc
*crtc
,
10370 struct intel_encoder
*encoder
)
10372 struct intel_encoder
*source_encoder
;
10373 struct drm_connector
*connector
;
10374 struct drm_connector_state
*connector_state
;
10377 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
10378 if (connector_state
->crtc
!= &crtc
->base
)
10382 to_intel_encoder(connector_state
->best_encoder
);
10383 if (!encoders_cloneable(encoder
, source_encoder
))
10390 static int intel_crtc_atomic_check(struct drm_crtc
*crtc
,
10391 struct drm_crtc_state
*crtc_state
)
10393 struct drm_device
*dev
= crtc
->dev
;
10394 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10395 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10396 struct intel_crtc_state
*pipe_config
=
10397 to_intel_crtc_state(crtc_state
);
10398 struct drm_atomic_state
*state
= crtc_state
->state
;
10400 bool mode_changed
= needs_modeset(crtc_state
);
10402 if (mode_changed
&& !crtc_state
->active
)
10403 pipe_config
->update_wm_post
= true;
10405 if (mode_changed
&& crtc_state
->enable
&&
10406 dev_priv
->display
.crtc_compute_clock
&&
10407 !WARN_ON(pipe_config
->shared_dpll
)) {
10408 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
10414 if (crtc_state
->color_mgmt_changed
) {
10415 ret
= intel_color_check(crtc
, crtc_state
);
10420 * Changing color management on Intel hardware is
10421 * handled as part of planes update.
10423 crtc_state
->planes_changed
= true;
10427 if (dev_priv
->display
.compute_pipe_wm
) {
10428 ret
= dev_priv
->display
.compute_pipe_wm(pipe_config
);
10430 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10435 if (dev_priv
->display
.compute_intermediate_wm
&&
10436 !to_intel_atomic_state(state
)->skip_intermediate_wm
) {
10437 if (WARN_ON(!dev_priv
->display
.compute_pipe_wm
))
10441 * Calculate 'intermediate' watermarks that satisfy both the
10442 * old state and the new state. We can program these
10445 ret
= dev_priv
->display
.compute_intermediate_wm(dev
,
10449 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10452 } else if (dev_priv
->display
.compute_intermediate_wm
) {
10453 if (HAS_PCH_SPLIT(dev_priv
) && INTEL_GEN(dev_priv
) < 9)
10454 pipe_config
->wm
.ilk
.intermediate
= pipe_config
->wm
.ilk
.optimal
;
10457 if (INTEL_GEN(dev_priv
) >= 9) {
10459 ret
= skl_update_scaler_crtc(pipe_config
);
10462 ret
= skl_check_pipe_max_pixel_rate(intel_crtc
,
10465 ret
= intel_atomic_setup_scalers(dev_priv
, intel_crtc
,
10472 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
10473 .atomic_begin
= intel_begin_crtc_commit
,
10474 .atomic_flush
= intel_finish_crtc_commit
,
10475 .atomic_check
= intel_crtc_atomic_check
,
10478 static void intel_modeset_update_connector_atomic_state(struct drm_device
*dev
)
10480 struct intel_connector
*connector
;
10481 struct drm_connector_list_iter conn_iter
;
10483 drm_connector_list_iter_begin(dev
, &conn_iter
);
10484 for_each_intel_connector_iter(connector
, &conn_iter
) {
10485 if (connector
->base
.state
->crtc
)
10486 drm_connector_unreference(&connector
->base
);
10488 if (connector
->base
.encoder
) {
10489 connector
->base
.state
->best_encoder
=
10490 connector
->base
.encoder
;
10491 connector
->base
.state
->crtc
=
10492 connector
->base
.encoder
->crtc
;
10494 drm_connector_reference(&connector
->base
);
10496 connector
->base
.state
->best_encoder
= NULL
;
10497 connector
->base
.state
->crtc
= NULL
;
10500 drm_connector_list_iter_end(&conn_iter
);
10504 connected_sink_compute_bpp(struct intel_connector
*connector
,
10505 struct intel_crtc_state
*pipe_config
)
10507 const struct drm_display_info
*info
= &connector
->base
.display_info
;
10508 int bpp
= pipe_config
->pipe_bpp
;
10510 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10511 connector
->base
.base
.id
,
10512 connector
->base
.name
);
10514 /* Don't use an invalid EDID bpc value */
10515 if (info
->bpc
!= 0 && info
->bpc
* 3 < bpp
) {
10516 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10517 bpp
, info
->bpc
* 3);
10518 pipe_config
->pipe_bpp
= info
->bpc
* 3;
10521 /* Clamp bpp to 8 on screens without EDID 1.4 */
10522 if (info
->bpc
== 0 && bpp
> 24) {
10523 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10525 pipe_config
->pipe_bpp
= 24;
10530 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
10531 struct intel_crtc_state
*pipe_config
)
10533 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
10534 struct drm_atomic_state
*state
;
10535 struct drm_connector
*connector
;
10536 struct drm_connector_state
*connector_state
;
10539 if ((IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
10540 IS_CHERRYVIEW(dev_priv
)))
10542 else if (INTEL_GEN(dev_priv
) >= 5)
10548 pipe_config
->pipe_bpp
= bpp
;
10550 state
= pipe_config
->base
.state
;
10552 /* Clamp display bpp to EDID value */
10553 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
10554 if (connector_state
->crtc
!= &crtc
->base
)
10557 connected_sink_compute_bpp(to_intel_connector(connector
),
10564 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
10566 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10567 "type: 0x%x flags: 0x%x\n",
10569 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
10570 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
10571 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
10572 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
10576 intel_dump_m_n_config(struct intel_crtc_state
*pipe_config
, char *id
,
10577 unsigned int lane_count
, struct intel_link_m_n
*m_n
)
10579 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10581 m_n
->gmch_m
, m_n
->gmch_n
,
10582 m_n
->link_m
, m_n
->link_n
, m_n
->tu
);
10585 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
10587 static const char * const output_type_str
[] = {
10588 OUTPUT_TYPE(UNUSED
),
10589 OUTPUT_TYPE(ANALOG
),
10593 OUTPUT_TYPE(TVOUT
),
10598 OUTPUT_TYPE(UNKNOWN
),
10599 OUTPUT_TYPE(DP_MST
),
10604 static void snprintf_output_types(char *buf
, size_t len
,
10605 unsigned int output_types
)
10612 for (i
= 0; i
< ARRAY_SIZE(output_type_str
); i
++) {
10615 if ((output_types
& BIT(i
)) == 0)
10618 r
= snprintf(str
, len
, "%s%s",
10619 str
!= buf
? "," : "", output_type_str
[i
]);
10625 output_types
&= ~BIT(i
);
10628 WARN_ON_ONCE(output_types
!= 0);
10631 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
10632 struct intel_crtc_state
*pipe_config
,
10633 const char *context
)
10635 struct drm_device
*dev
= crtc
->base
.dev
;
10636 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10637 struct drm_plane
*plane
;
10638 struct intel_plane
*intel_plane
;
10639 struct intel_plane_state
*state
;
10640 struct drm_framebuffer
*fb
;
10643 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
10644 crtc
->base
.base
.id
, crtc
->base
.name
, context
);
10646 snprintf_output_types(buf
, sizeof(buf
), pipe_config
->output_types
);
10647 DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
10648 buf
, pipe_config
->output_types
);
10650 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
10651 transcoder_name(pipe_config
->cpu_transcoder
),
10652 pipe_config
->pipe_bpp
, pipe_config
->dither
);
10654 if (pipe_config
->has_pch_encoder
)
10655 intel_dump_m_n_config(pipe_config
, "fdi",
10656 pipe_config
->fdi_lanes
,
10657 &pipe_config
->fdi_m_n
);
10659 if (pipe_config
->ycbcr420
)
10660 DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n");
10662 if (intel_crtc_has_dp_encoder(pipe_config
)) {
10663 intel_dump_m_n_config(pipe_config
, "dp m_n",
10664 pipe_config
->lane_count
, &pipe_config
->dp_m_n
);
10665 if (pipe_config
->has_drrs
)
10666 intel_dump_m_n_config(pipe_config
, "dp m2_n2",
10667 pipe_config
->lane_count
,
10668 &pipe_config
->dp_m2_n2
);
10671 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10672 pipe_config
->has_audio
, pipe_config
->has_infoframe
);
10674 DRM_DEBUG_KMS("requested mode:\n");
10675 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
10676 DRM_DEBUG_KMS("adjusted mode:\n");
10677 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
10678 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
10679 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
10680 pipe_config
->port_clock
,
10681 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
,
10682 pipe_config
->pixel_rate
);
10684 if (INTEL_GEN(dev_priv
) >= 9)
10685 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
10687 pipe_config
->scaler_state
.scaler_users
,
10688 pipe_config
->scaler_state
.scaler_id
);
10690 if (HAS_GMCH_DISPLAY(dev_priv
))
10691 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10692 pipe_config
->gmch_pfit
.control
,
10693 pipe_config
->gmch_pfit
.pgm_ratios
,
10694 pipe_config
->gmch_pfit
.lvds_border_bits
);
10696 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10697 pipe_config
->pch_pfit
.pos
,
10698 pipe_config
->pch_pfit
.size
,
10699 enableddisabled(pipe_config
->pch_pfit
.enabled
));
10701 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
10702 pipe_config
->ips_enabled
, pipe_config
->double_wide
);
10704 intel_dpll_dump_hw_state(dev_priv
, &pipe_config
->dpll_hw_state
);
10706 DRM_DEBUG_KMS("planes on this crtc\n");
10707 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
10708 struct drm_format_name_buf format_name
;
10709 intel_plane
= to_intel_plane(plane
);
10710 if (intel_plane
->pipe
!= crtc
->pipe
)
10713 state
= to_intel_plane_state(plane
->state
);
10714 fb
= state
->base
.fb
;
10716 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
10717 plane
->base
.id
, plane
->name
, state
->scaler_id
);
10721 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
10722 plane
->base
.id
, plane
->name
,
10723 fb
->base
.id
, fb
->width
, fb
->height
,
10724 drm_get_format_name(fb
->format
->format
, &format_name
));
10725 if (INTEL_GEN(dev_priv
) >= 9)
10726 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
10728 state
->base
.src
.x1
>> 16,
10729 state
->base
.src
.y1
>> 16,
10730 drm_rect_width(&state
->base
.src
) >> 16,
10731 drm_rect_height(&state
->base
.src
) >> 16,
10732 state
->base
.dst
.x1
, state
->base
.dst
.y1
,
10733 drm_rect_width(&state
->base
.dst
),
10734 drm_rect_height(&state
->base
.dst
));
10738 static bool check_digital_port_conflicts(struct drm_atomic_state
*state
)
10740 struct drm_device
*dev
= state
->dev
;
10741 struct drm_connector
*connector
;
10742 struct drm_connector_list_iter conn_iter
;
10743 unsigned int used_ports
= 0;
10744 unsigned int used_mst_ports
= 0;
10747 * Walk the connector list instead of the encoder
10748 * list to detect the problem on ddi platforms
10749 * where there's just one encoder per digital port.
10751 drm_connector_list_iter_begin(dev
, &conn_iter
);
10752 drm_for_each_connector_iter(connector
, &conn_iter
) {
10753 struct drm_connector_state
*connector_state
;
10754 struct intel_encoder
*encoder
;
10756 connector_state
= drm_atomic_get_existing_connector_state(state
, connector
);
10757 if (!connector_state
)
10758 connector_state
= connector
->state
;
10760 if (!connector_state
->best_encoder
)
10763 encoder
= to_intel_encoder(connector_state
->best_encoder
);
10765 WARN_ON(!connector_state
->crtc
);
10767 switch (encoder
->type
) {
10768 unsigned int port_mask
;
10769 case INTEL_OUTPUT_UNKNOWN
:
10770 if (WARN_ON(!HAS_DDI(to_i915(dev
))))
10772 case INTEL_OUTPUT_DP
:
10773 case INTEL_OUTPUT_HDMI
:
10774 case INTEL_OUTPUT_EDP
:
10775 port_mask
= 1 << enc_to_dig_port(&encoder
->base
)->port
;
10777 /* the same port mustn't appear more than once */
10778 if (used_ports
& port_mask
)
10781 used_ports
|= port_mask
;
10783 case INTEL_OUTPUT_DP_MST
:
10785 1 << enc_to_mst(&encoder
->base
)->primary
->port
;
10791 drm_connector_list_iter_end(&conn_iter
);
10793 /* can't mix MST and SST/HDMI on the same port */
10794 if (used_ports
& used_mst_ports
)
10801 clear_intel_crtc_state(struct intel_crtc_state
*crtc_state
)
10803 struct drm_i915_private
*dev_priv
=
10804 to_i915(crtc_state
->base
.crtc
->dev
);
10805 struct intel_crtc_scaler_state scaler_state
;
10806 struct intel_dpll_hw_state dpll_hw_state
;
10807 struct intel_shared_dpll
*shared_dpll
;
10808 struct intel_crtc_wm_state wm_state
;
10809 bool force_thru
, ips_force_disable
;
10811 /* FIXME: before the switch to atomic started, a new pipe_config was
10812 * kzalloc'd. Code that depends on any field being zero should be
10813 * fixed, so that the crtc_state can be safely duplicated. For now,
10814 * only fields that are know to not cause problems are preserved. */
10816 scaler_state
= crtc_state
->scaler_state
;
10817 shared_dpll
= crtc_state
->shared_dpll
;
10818 dpll_hw_state
= crtc_state
->dpll_hw_state
;
10819 force_thru
= crtc_state
->pch_pfit
.force_thru
;
10820 ips_force_disable
= crtc_state
->ips_force_disable
;
10821 if (IS_G4X(dev_priv
) ||
10822 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
10823 wm_state
= crtc_state
->wm
;
10825 /* Keep base drm_crtc_state intact, only clear our extended struct */
10826 BUILD_BUG_ON(offsetof(struct intel_crtc_state
, base
));
10827 memset(&crtc_state
->base
+ 1, 0,
10828 sizeof(*crtc_state
) - sizeof(crtc_state
->base
));
10830 crtc_state
->scaler_state
= scaler_state
;
10831 crtc_state
->shared_dpll
= shared_dpll
;
10832 crtc_state
->dpll_hw_state
= dpll_hw_state
;
10833 crtc_state
->pch_pfit
.force_thru
= force_thru
;
10834 crtc_state
->ips_force_disable
= ips_force_disable
;
10835 if (IS_G4X(dev_priv
) ||
10836 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
10837 crtc_state
->wm
= wm_state
;
10841 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
10842 struct intel_crtc_state
*pipe_config
)
10844 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
10845 struct intel_encoder
*encoder
;
10846 struct drm_connector
*connector
;
10847 struct drm_connector_state
*connector_state
;
10848 int base_bpp
, ret
= -EINVAL
;
10852 clear_intel_crtc_state(pipe_config
);
10854 pipe_config
->cpu_transcoder
=
10855 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
10858 * Sanitize sync polarity flags based on requested ones. If neither
10859 * positive or negative polarity is requested, treat this as meaning
10860 * negative polarity.
10862 if (!(pipe_config
->base
.adjusted_mode
.flags
&
10863 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
10864 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
10866 if (!(pipe_config
->base
.adjusted_mode
.flags
&
10867 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
10868 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
10870 base_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
10876 * Determine the real pipe dimensions. Note that stereo modes can
10877 * increase the actual pipe size due to the frame doubling and
10878 * insertion of additional space for blanks between the frame. This
10879 * is stored in the crtc timings. We use the requested mode to do this
10880 * computation to clearly distinguish it from the adjusted mode, which
10881 * can be changed by the connectors in the below retry loop.
10883 drm_mode_get_hv_timing(&pipe_config
->base
.mode
,
10884 &pipe_config
->pipe_src_w
,
10885 &pipe_config
->pipe_src_h
);
10887 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
10888 if (connector_state
->crtc
!= crtc
)
10891 encoder
= to_intel_encoder(connector_state
->best_encoder
);
10893 if (!check_single_encoder_cloning(state
, to_intel_crtc(crtc
), encoder
)) {
10894 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10899 * Determine output_types before calling the .compute_config()
10900 * hooks so that the hooks can use this information safely.
10902 pipe_config
->output_types
|= 1 << encoder
->type
;
10906 /* Ensure the port clock defaults are reset when retrying. */
10907 pipe_config
->port_clock
= 0;
10908 pipe_config
->pixel_multiplier
= 1;
10910 /* Fill in default crtc timings, allow encoders to overwrite them. */
10911 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
10912 CRTC_STEREO_DOUBLE
);
10914 /* Pass our mode to the connectors and the CRTC to give them a chance to
10915 * adjust it according to limitations or connector properties, and also
10916 * a chance to reject the mode entirely.
10918 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
10919 if (connector_state
->crtc
!= crtc
)
10922 encoder
= to_intel_encoder(connector_state
->best_encoder
);
10924 if (!(encoder
->compute_config(encoder
, pipe_config
, connector_state
))) {
10925 DRM_DEBUG_KMS("Encoder config failure\n");
10930 /* Set default port clock if not overwritten by the encoder. Needs to be
10931 * done afterwards in case the encoder adjusts the mode. */
10932 if (!pipe_config
->port_clock
)
10933 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
10934 * pipe_config
->pixel_multiplier
;
10936 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
10938 DRM_DEBUG_KMS("CRTC fixup failed\n");
10942 if (ret
== RETRY
) {
10943 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
10948 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10950 goto encoder_retry
;
10953 /* Dithering seems to not pass-through bits correctly when it should, so
10954 * only enable it on 6bpc panels and when its not a compliance
10955 * test requesting 6bpc video pattern.
10957 pipe_config
->dither
= (pipe_config
->pipe_bpp
== 6*3) &&
10958 !pipe_config
->dither_force_disable
;
10959 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
10960 base_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
10967 intel_modeset_update_crtc_state(struct drm_atomic_state
*state
)
10969 struct drm_crtc
*crtc
;
10970 struct drm_crtc_state
*new_crtc_state
;
10973 /* Double check state. */
10974 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
10975 to_intel_crtc(crtc
)->config
= to_intel_crtc_state(new_crtc_state
);
10978 * Update legacy state to satisfy fbc code. This can
10979 * be removed when fbc uses the atomic state.
10981 if (drm_atomic_get_existing_plane_state(state
, crtc
->primary
)) {
10982 struct drm_plane_state
*plane_state
= crtc
->primary
->state
;
10984 crtc
->primary
->fb
= plane_state
->fb
;
10985 crtc
->x
= plane_state
->src_x
>> 16;
10986 crtc
->y
= plane_state
->src_y
>> 16;
10991 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
10995 if (clock1
== clock2
)
10998 if (!clock1
|| !clock2
)
11001 diff
= abs(clock1
- clock2
);
11003 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
11010 intel_compare_m_n(unsigned int m
, unsigned int n
,
11011 unsigned int m2
, unsigned int n2
,
11014 if (m
== m2
&& n
== n2
)
11017 if (exact
|| !m
|| !n
|| !m2
|| !n2
)
11020 BUILD_BUG_ON(DATA_LINK_M_N_MASK
> INT_MAX
);
11027 } else if (n
< n2
) {
11037 return intel_fuzzy_clock_check(m
, m2
);
11041 intel_compare_link_m_n(const struct intel_link_m_n
*m_n
,
11042 struct intel_link_m_n
*m2_n2
,
11045 if (m_n
->tu
== m2_n2
->tu
&&
11046 intel_compare_m_n(m_n
->gmch_m
, m_n
->gmch_n
,
11047 m2_n2
->gmch_m
, m2_n2
->gmch_n
, !adjust
) &&
11048 intel_compare_m_n(m_n
->link_m
, m_n
->link_n
,
11049 m2_n2
->link_m
, m2_n2
->link_n
, !adjust
)) {
11059 static void __printf(3, 4)
11060 pipe_config_err(bool adjust
, const char *name
, const char *format
, ...)
11063 unsigned int category
;
11064 struct va_format vaf
;
11068 level
= KERN_DEBUG
;
11069 category
= DRM_UT_KMS
;
11072 category
= DRM_UT_NONE
;
11075 va_start(args
, format
);
11079 drm_printk(level
, category
, "mismatch in %s %pV", name
, &vaf
);
11085 intel_pipe_config_compare(struct drm_i915_private
*dev_priv
,
11086 struct intel_crtc_state
*current_config
,
11087 struct intel_crtc_state
*pipe_config
,
11092 #define PIPE_CONF_CHECK_X(name) \
11093 if (current_config->name != pipe_config->name) { \
11094 pipe_config_err(adjust, __stringify(name), \
11095 "(expected 0x%08x, found 0x%08x)\n", \
11096 current_config->name, \
11097 pipe_config->name); \
11101 #define PIPE_CONF_CHECK_I(name) \
11102 if (current_config->name != pipe_config->name) { \
11103 pipe_config_err(adjust, __stringify(name), \
11104 "(expected %i, found %i)\n", \
11105 current_config->name, \
11106 pipe_config->name); \
11110 #define PIPE_CONF_CHECK_P(name) \
11111 if (current_config->name != pipe_config->name) { \
11112 pipe_config_err(adjust, __stringify(name), \
11113 "(expected %p, found %p)\n", \
11114 current_config->name, \
11115 pipe_config->name); \
11119 #define PIPE_CONF_CHECK_M_N(name) \
11120 if (!intel_compare_link_m_n(¤t_config->name, \
11121 &pipe_config->name,\
11123 pipe_config_err(adjust, __stringify(name), \
11124 "(expected tu %i gmch %i/%i link %i/%i, " \
11125 "found tu %i, gmch %i/%i link %i/%i)\n", \
11126 current_config->name.tu, \
11127 current_config->name.gmch_m, \
11128 current_config->name.gmch_n, \
11129 current_config->name.link_m, \
11130 current_config->name.link_n, \
11131 pipe_config->name.tu, \
11132 pipe_config->name.gmch_m, \
11133 pipe_config->name.gmch_n, \
11134 pipe_config->name.link_m, \
11135 pipe_config->name.link_n); \
11139 /* This is required for BDW+ where there is only one set of registers for
11140 * switching between high and low RR.
11141 * This macro can be used whenever a comparison has to be made between one
11142 * hw state and multiple sw state variables.
11144 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11145 if (!intel_compare_link_m_n(¤t_config->name, \
11146 &pipe_config->name, adjust) && \
11147 !intel_compare_link_m_n(¤t_config->alt_name, \
11148 &pipe_config->name, adjust)) { \
11149 pipe_config_err(adjust, __stringify(name), \
11150 "(expected tu %i gmch %i/%i link %i/%i, " \
11151 "or tu %i gmch %i/%i link %i/%i, " \
11152 "found tu %i, gmch %i/%i link %i/%i)\n", \
11153 current_config->name.tu, \
11154 current_config->name.gmch_m, \
11155 current_config->name.gmch_n, \
11156 current_config->name.link_m, \
11157 current_config->name.link_n, \
11158 current_config->alt_name.tu, \
11159 current_config->alt_name.gmch_m, \
11160 current_config->alt_name.gmch_n, \
11161 current_config->alt_name.link_m, \
11162 current_config->alt_name.link_n, \
11163 pipe_config->name.tu, \
11164 pipe_config->name.gmch_m, \
11165 pipe_config->name.gmch_n, \
11166 pipe_config->name.link_m, \
11167 pipe_config->name.link_n); \
11171 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11172 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11173 pipe_config_err(adjust, __stringify(name), \
11174 "(%x) (expected %i, found %i)\n", \
11176 current_config->name & (mask), \
11177 pipe_config->name & (mask)); \
11181 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11182 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11183 pipe_config_err(adjust, __stringify(name), \
11184 "(expected %i, found %i)\n", \
11185 current_config->name, \
11186 pipe_config->name); \
11190 #define PIPE_CONF_QUIRK(quirk) \
11191 ((current_config->quirks | pipe_config->quirks) & (quirk))
11193 PIPE_CONF_CHECK_I(cpu_transcoder
);
11195 PIPE_CONF_CHECK_I(has_pch_encoder
);
11196 PIPE_CONF_CHECK_I(fdi_lanes
);
11197 PIPE_CONF_CHECK_M_N(fdi_m_n
);
11199 PIPE_CONF_CHECK_I(lane_count
);
11200 PIPE_CONF_CHECK_X(lane_lat_optim_mask
);
11202 if (INTEL_GEN(dev_priv
) < 8) {
11203 PIPE_CONF_CHECK_M_N(dp_m_n
);
11205 if (current_config
->has_drrs
)
11206 PIPE_CONF_CHECK_M_N(dp_m2_n2
);
11208 PIPE_CONF_CHECK_M_N_ALT(dp_m_n
, dp_m2_n2
);
11210 PIPE_CONF_CHECK_X(output_types
);
11212 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
11213 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
11214 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
11215 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
11216 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
11217 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
11219 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
11220 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
11221 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
11222 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
11223 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
11224 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
11226 PIPE_CONF_CHECK_I(pixel_multiplier
);
11227 PIPE_CONF_CHECK_I(has_hdmi_sink
);
11228 if ((INTEL_GEN(dev_priv
) < 8 && !IS_HASWELL(dev_priv
)) ||
11229 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
11230 PIPE_CONF_CHECK_I(limited_color_range
);
11232 PIPE_CONF_CHECK_I(hdmi_scrambling
);
11233 PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio
);
11234 PIPE_CONF_CHECK_I(has_infoframe
);
11235 PIPE_CONF_CHECK_I(ycbcr420
);
11237 PIPE_CONF_CHECK_I(has_audio
);
11239 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11240 DRM_MODE_FLAG_INTERLACE
);
11242 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
11243 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11244 DRM_MODE_FLAG_PHSYNC
);
11245 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11246 DRM_MODE_FLAG_NHSYNC
);
11247 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11248 DRM_MODE_FLAG_PVSYNC
);
11249 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11250 DRM_MODE_FLAG_NVSYNC
);
11253 PIPE_CONF_CHECK_X(gmch_pfit
.control
);
11254 /* pfit ratios are autocomputed by the hw on gen4+ */
11255 if (INTEL_GEN(dev_priv
) < 4)
11256 PIPE_CONF_CHECK_X(gmch_pfit
.pgm_ratios
);
11257 PIPE_CONF_CHECK_X(gmch_pfit
.lvds_border_bits
);
11260 PIPE_CONF_CHECK_I(pipe_src_w
);
11261 PIPE_CONF_CHECK_I(pipe_src_h
);
11263 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
11264 if (current_config
->pch_pfit
.enabled
) {
11265 PIPE_CONF_CHECK_X(pch_pfit
.pos
);
11266 PIPE_CONF_CHECK_X(pch_pfit
.size
);
11269 PIPE_CONF_CHECK_I(scaler_state
.scaler_id
);
11270 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate
);
11273 /* BDW+ don't expose a synchronous way to read the state */
11274 if (IS_HASWELL(dev_priv
))
11275 PIPE_CONF_CHECK_I(ips_enabled
);
11277 PIPE_CONF_CHECK_I(double_wide
);
11279 PIPE_CONF_CHECK_P(shared_dpll
);
11280 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
11281 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
11282 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
11283 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
11284 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
11285 PIPE_CONF_CHECK_X(dpll_hw_state
.spll
);
11286 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
11287 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
11288 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
11289 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr0
);
11290 PIPE_CONF_CHECK_X(dpll_hw_state
.ebb0
);
11291 PIPE_CONF_CHECK_X(dpll_hw_state
.ebb4
);
11292 PIPE_CONF_CHECK_X(dpll_hw_state
.pll0
);
11293 PIPE_CONF_CHECK_X(dpll_hw_state
.pll1
);
11294 PIPE_CONF_CHECK_X(dpll_hw_state
.pll2
);
11295 PIPE_CONF_CHECK_X(dpll_hw_state
.pll3
);
11296 PIPE_CONF_CHECK_X(dpll_hw_state
.pll6
);
11297 PIPE_CONF_CHECK_X(dpll_hw_state
.pll8
);
11298 PIPE_CONF_CHECK_X(dpll_hw_state
.pll9
);
11299 PIPE_CONF_CHECK_X(dpll_hw_state
.pll10
);
11300 PIPE_CONF_CHECK_X(dpll_hw_state
.pcsdw12
);
11302 PIPE_CONF_CHECK_X(dsi_pll
.ctrl
);
11303 PIPE_CONF_CHECK_X(dsi_pll
.div
);
11305 if (IS_G4X(dev_priv
) || INTEL_GEN(dev_priv
) >= 5)
11306 PIPE_CONF_CHECK_I(pipe_bpp
);
11308 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
11309 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
11311 #undef PIPE_CONF_CHECK_X
11312 #undef PIPE_CONF_CHECK_I
11313 #undef PIPE_CONF_CHECK_P
11314 #undef PIPE_CONF_CHECK_FLAGS
11315 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11316 #undef PIPE_CONF_QUIRK
11321 static void intel_pipe_config_sanity_check(struct drm_i915_private
*dev_priv
,
11322 const struct intel_crtc_state
*pipe_config
)
11324 if (pipe_config
->has_pch_encoder
) {
11325 int fdi_dotclock
= intel_dotclock_calculate(intel_fdi_link_freq(dev_priv
, pipe_config
),
11326 &pipe_config
->fdi_m_n
);
11327 int dotclock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
11330 * FDI already provided one idea for the dotclock.
11331 * Yell if the encoder disagrees.
11333 WARN(!intel_fuzzy_clock_check(fdi_dotclock
, dotclock
),
11334 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11335 fdi_dotclock
, dotclock
);
11339 static void verify_wm_state(struct drm_crtc
*crtc
,
11340 struct drm_crtc_state
*new_state
)
11342 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
11343 struct skl_ddb_allocation hw_ddb
, *sw_ddb
;
11344 struct skl_pipe_wm hw_wm
, *sw_wm
;
11345 struct skl_plane_wm
*hw_plane_wm
, *sw_plane_wm
;
11346 struct skl_ddb_entry
*hw_ddb_entry
, *sw_ddb_entry
;
11347 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11348 const enum pipe pipe
= intel_crtc
->pipe
;
11349 int plane
, level
, max_level
= ilk_wm_max_level(dev_priv
);
11351 if (INTEL_GEN(dev_priv
) < 9 || !new_state
->active
)
11354 skl_pipe_wm_get_hw_state(crtc
, &hw_wm
);
11355 sw_wm
= &to_intel_crtc_state(new_state
)->wm
.skl
.optimal
;
11357 skl_ddb_get_hw_state(dev_priv
, &hw_ddb
);
11358 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
11361 for_each_universal_plane(dev_priv
, pipe
, plane
) {
11362 hw_plane_wm
= &hw_wm
.planes
[plane
];
11363 sw_plane_wm
= &sw_wm
->planes
[plane
];
11366 for (level
= 0; level
<= max_level
; level
++) {
11367 if (skl_wm_level_equals(&hw_plane_wm
->wm
[level
],
11368 &sw_plane_wm
->wm
[level
]))
11371 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11372 pipe_name(pipe
), plane
+ 1, level
,
11373 sw_plane_wm
->wm
[level
].plane_en
,
11374 sw_plane_wm
->wm
[level
].plane_res_b
,
11375 sw_plane_wm
->wm
[level
].plane_res_l
,
11376 hw_plane_wm
->wm
[level
].plane_en
,
11377 hw_plane_wm
->wm
[level
].plane_res_b
,
11378 hw_plane_wm
->wm
[level
].plane_res_l
);
11381 if (!skl_wm_level_equals(&hw_plane_wm
->trans_wm
,
11382 &sw_plane_wm
->trans_wm
)) {
11383 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11384 pipe_name(pipe
), plane
+ 1,
11385 sw_plane_wm
->trans_wm
.plane_en
,
11386 sw_plane_wm
->trans_wm
.plane_res_b
,
11387 sw_plane_wm
->trans_wm
.plane_res_l
,
11388 hw_plane_wm
->trans_wm
.plane_en
,
11389 hw_plane_wm
->trans_wm
.plane_res_b
,
11390 hw_plane_wm
->trans_wm
.plane_res_l
);
11394 hw_ddb_entry
= &hw_ddb
.plane
[pipe
][plane
];
11395 sw_ddb_entry
= &sw_ddb
->plane
[pipe
][plane
];
11397 if (!skl_ddb_entry_equal(hw_ddb_entry
, sw_ddb_entry
)) {
11398 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11399 pipe_name(pipe
), plane
+ 1,
11400 sw_ddb_entry
->start
, sw_ddb_entry
->end
,
11401 hw_ddb_entry
->start
, hw_ddb_entry
->end
);
11407 * If the cursor plane isn't active, we may not have updated it's ddb
11408 * allocation. In that case since the ddb allocation will be updated
11409 * once the plane becomes visible, we can skip this check
11412 hw_plane_wm
= &hw_wm
.planes
[PLANE_CURSOR
];
11413 sw_plane_wm
= &sw_wm
->planes
[PLANE_CURSOR
];
11416 for (level
= 0; level
<= max_level
; level
++) {
11417 if (skl_wm_level_equals(&hw_plane_wm
->wm
[level
],
11418 &sw_plane_wm
->wm
[level
]))
11421 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11422 pipe_name(pipe
), level
,
11423 sw_plane_wm
->wm
[level
].plane_en
,
11424 sw_plane_wm
->wm
[level
].plane_res_b
,
11425 sw_plane_wm
->wm
[level
].plane_res_l
,
11426 hw_plane_wm
->wm
[level
].plane_en
,
11427 hw_plane_wm
->wm
[level
].plane_res_b
,
11428 hw_plane_wm
->wm
[level
].plane_res_l
);
11431 if (!skl_wm_level_equals(&hw_plane_wm
->trans_wm
,
11432 &sw_plane_wm
->trans_wm
)) {
11433 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11435 sw_plane_wm
->trans_wm
.plane_en
,
11436 sw_plane_wm
->trans_wm
.plane_res_b
,
11437 sw_plane_wm
->trans_wm
.plane_res_l
,
11438 hw_plane_wm
->trans_wm
.plane_en
,
11439 hw_plane_wm
->trans_wm
.plane_res_b
,
11440 hw_plane_wm
->trans_wm
.plane_res_l
);
11444 hw_ddb_entry
= &hw_ddb
.plane
[pipe
][PLANE_CURSOR
];
11445 sw_ddb_entry
= &sw_ddb
->plane
[pipe
][PLANE_CURSOR
];
11447 if (!skl_ddb_entry_equal(hw_ddb_entry
, sw_ddb_entry
)) {
11448 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11450 sw_ddb_entry
->start
, sw_ddb_entry
->end
,
11451 hw_ddb_entry
->start
, hw_ddb_entry
->end
);
11457 verify_connector_state(struct drm_device
*dev
,
11458 struct drm_atomic_state
*state
,
11459 struct drm_crtc
*crtc
)
11461 struct drm_connector
*connector
;
11462 struct drm_connector_state
*new_conn_state
;
11465 for_each_new_connector_in_state(state
, connector
, new_conn_state
, i
) {
11466 struct drm_encoder
*encoder
= connector
->encoder
;
11467 struct drm_crtc_state
*crtc_state
= NULL
;
11469 if (new_conn_state
->crtc
!= crtc
)
11473 crtc_state
= drm_atomic_get_new_crtc_state(state
, new_conn_state
->crtc
);
11475 intel_connector_verify_state(crtc_state
, new_conn_state
);
11477 I915_STATE_WARN(new_conn_state
->best_encoder
!= encoder
,
11478 "connector's atomic encoder doesn't match legacy encoder\n");
11483 verify_encoder_state(struct drm_device
*dev
, struct drm_atomic_state
*state
)
11485 struct intel_encoder
*encoder
;
11486 struct drm_connector
*connector
;
11487 struct drm_connector_state
*old_conn_state
, *new_conn_state
;
11490 for_each_intel_encoder(dev
, encoder
) {
11491 bool enabled
= false, found
= false;
11494 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11495 encoder
->base
.base
.id
,
11496 encoder
->base
.name
);
11498 for_each_oldnew_connector_in_state(state
, connector
, old_conn_state
,
11499 new_conn_state
, i
) {
11500 if (old_conn_state
->best_encoder
== &encoder
->base
)
11503 if (new_conn_state
->best_encoder
!= &encoder
->base
)
11505 found
= enabled
= true;
11507 I915_STATE_WARN(new_conn_state
->crtc
!=
11508 encoder
->base
.crtc
,
11509 "connector's crtc doesn't match encoder crtc\n");
11515 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
11516 "encoder's enabled state mismatch "
11517 "(expected %i, found %i)\n",
11518 !!encoder
->base
.crtc
, enabled
);
11520 if (!encoder
->base
.crtc
) {
11523 active
= encoder
->get_hw_state(encoder
, &pipe
);
11524 I915_STATE_WARN(active
,
11525 "encoder detached but still enabled on pipe %c.\n",
11532 verify_crtc_state(struct drm_crtc
*crtc
,
11533 struct drm_crtc_state
*old_crtc_state
,
11534 struct drm_crtc_state
*new_crtc_state
)
11536 struct drm_device
*dev
= crtc
->dev
;
11537 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11538 struct intel_encoder
*encoder
;
11539 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11540 struct intel_crtc_state
*pipe_config
, *sw_config
;
11541 struct drm_atomic_state
*old_state
;
11544 old_state
= old_crtc_state
->state
;
11545 __drm_atomic_helper_crtc_destroy_state(old_crtc_state
);
11546 pipe_config
= to_intel_crtc_state(old_crtc_state
);
11547 memset(pipe_config
, 0, sizeof(*pipe_config
));
11548 pipe_config
->base
.crtc
= crtc
;
11549 pipe_config
->base
.state
= old_state
;
11551 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc
->base
.id
, crtc
->name
);
11553 active
= dev_priv
->display
.get_pipe_config(intel_crtc
, pipe_config
);
11555 /* we keep both pipes enabled on 830 */
11556 if (IS_I830(dev_priv
))
11557 active
= new_crtc_state
->active
;
11559 I915_STATE_WARN(new_crtc_state
->active
!= active
,
11560 "crtc active state doesn't match with hw state "
11561 "(expected %i, found %i)\n", new_crtc_state
->active
, active
);
11563 I915_STATE_WARN(intel_crtc
->active
!= new_crtc_state
->active
,
11564 "transitional active state does not match atomic hw state "
11565 "(expected %i, found %i)\n", new_crtc_state
->active
, intel_crtc
->active
);
11567 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
11570 active
= encoder
->get_hw_state(encoder
, &pipe
);
11571 I915_STATE_WARN(active
!= new_crtc_state
->active
,
11572 "[ENCODER:%i] active %i with crtc active %i\n",
11573 encoder
->base
.base
.id
, active
, new_crtc_state
->active
);
11575 I915_STATE_WARN(active
&& intel_crtc
->pipe
!= pipe
,
11576 "Encoder connected to wrong pipe %c\n",
11580 pipe_config
->output_types
|= 1 << encoder
->type
;
11581 encoder
->get_config(encoder
, pipe_config
);
11585 intel_crtc_compute_pixel_rate(pipe_config
);
11587 if (!new_crtc_state
->active
)
11590 intel_pipe_config_sanity_check(dev_priv
, pipe_config
);
11592 sw_config
= to_intel_crtc_state(new_crtc_state
);
11593 if (!intel_pipe_config_compare(dev_priv
, sw_config
,
11594 pipe_config
, false)) {
11595 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11596 intel_dump_pipe_config(intel_crtc
, pipe_config
,
11598 intel_dump_pipe_config(intel_crtc
, sw_config
,
11604 verify_single_dpll_state(struct drm_i915_private
*dev_priv
,
11605 struct intel_shared_dpll
*pll
,
11606 struct drm_crtc
*crtc
,
11607 struct drm_crtc_state
*new_state
)
11609 struct intel_dpll_hw_state dpll_hw_state
;
11610 unsigned crtc_mask
;
11613 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
11615 DRM_DEBUG_KMS("%s\n", pll
->name
);
11617 active
= pll
->funcs
.get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
11619 if (!(pll
->flags
& INTEL_DPLL_ALWAYS_ON
)) {
11620 I915_STATE_WARN(!pll
->on
&& pll
->active_mask
,
11621 "pll in active use but not on in sw tracking\n");
11622 I915_STATE_WARN(pll
->on
&& !pll
->active_mask
,
11623 "pll is on but not used by any active crtc\n");
11624 I915_STATE_WARN(pll
->on
!= active
,
11625 "pll on state mismatch (expected %i, found %i)\n",
11630 I915_STATE_WARN(pll
->active_mask
& ~pll
->state
.crtc_mask
,
11631 "more active pll users than references: %x vs %x\n",
11632 pll
->active_mask
, pll
->state
.crtc_mask
);
11637 crtc_mask
= 1 << drm_crtc_index(crtc
);
11639 if (new_state
->active
)
11640 I915_STATE_WARN(!(pll
->active_mask
& crtc_mask
),
11641 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
11642 pipe_name(drm_crtc_index(crtc
)), pll
->active_mask
);
11644 I915_STATE_WARN(pll
->active_mask
& crtc_mask
,
11645 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
11646 pipe_name(drm_crtc_index(crtc
)), pll
->active_mask
);
11648 I915_STATE_WARN(!(pll
->state
.crtc_mask
& crtc_mask
),
11649 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
11650 crtc_mask
, pll
->state
.crtc_mask
);
11652 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->state
.hw_state
,
11654 sizeof(dpll_hw_state
)),
11655 "pll hw state mismatch\n");
11659 verify_shared_dpll_state(struct drm_device
*dev
, struct drm_crtc
*crtc
,
11660 struct drm_crtc_state
*old_crtc_state
,
11661 struct drm_crtc_state
*new_crtc_state
)
11663 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11664 struct intel_crtc_state
*old_state
= to_intel_crtc_state(old_crtc_state
);
11665 struct intel_crtc_state
*new_state
= to_intel_crtc_state(new_crtc_state
);
11667 if (new_state
->shared_dpll
)
11668 verify_single_dpll_state(dev_priv
, new_state
->shared_dpll
, crtc
, new_crtc_state
);
11670 if (old_state
->shared_dpll
&&
11671 old_state
->shared_dpll
!= new_state
->shared_dpll
) {
11672 unsigned crtc_mask
= 1 << drm_crtc_index(crtc
);
11673 struct intel_shared_dpll
*pll
= old_state
->shared_dpll
;
11675 I915_STATE_WARN(pll
->active_mask
& crtc_mask
,
11676 "pll active mismatch (didn't expect pipe %c in active mask)\n",
11677 pipe_name(drm_crtc_index(crtc
)));
11678 I915_STATE_WARN(pll
->state
.crtc_mask
& crtc_mask
,
11679 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
11680 pipe_name(drm_crtc_index(crtc
)));
11685 intel_modeset_verify_crtc(struct drm_crtc
*crtc
,
11686 struct drm_atomic_state
*state
,
11687 struct drm_crtc_state
*old_state
,
11688 struct drm_crtc_state
*new_state
)
11690 if (!needs_modeset(new_state
) &&
11691 !to_intel_crtc_state(new_state
)->update_pipe
)
11694 verify_wm_state(crtc
, new_state
);
11695 verify_connector_state(crtc
->dev
, state
, crtc
);
11696 verify_crtc_state(crtc
, old_state
, new_state
);
11697 verify_shared_dpll_state(crtc
->dev
, crtc
, old_state
, new_state
);
11701 verify_disabled_dpll_state(struct drm_device
*dev
)
11703 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11706 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++)
11707 verify_single_dpll_state(dev_priv
, &dev_priv
->shared_dplls
[i
], NULL
, NULL
);
11711 intel_modeset_verify_disabled(struct drm_device
*dev
,
11712 struct drm_atomic_state
*state
)
11714 verify_encoder_state(dev
, state
);
11715 verify_connector_state(dev
, state
, NULL
);
11716 verify_disabled_dpll_state(dev
);
11719 static void update_scanline_offset(struct intel_crtc
*crtc
)
11721 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
11724 * The scanline counter increments at the leading edge of hsync.
11726 * On most platforms it starts counting from vtotal-1 on the
11727 * first active line. That means the scanline counter value is
11728 * always one less than what we would expect. Ie. just after
11729 * start of vblank, which also occurs at start of hsync (on the
11730 * last active line), the scanline counter will read vblank_start-1.
11732 * On gen2 the scanline counter starts counting from 1 instead
11733 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11734 * to keep the value positive), instead of adding one.
11736 * On HSW+ the behaviour of the scanline counter depends on the output
11737 * type. For DP ports it behaves like most other platforms, but on HDMI
11738 * there's an extra 1 line difference. So we need to add two instead of
11739 * one to the value.
11741 * On VLV/CHV DSI the scanline counter would appear to increment
11742 * approx. 1/3 of a scanline before start of vblank. Unfortunately
11743 * that means we can't tell whether we're in vblank or not while
11744 * we're on that particular line. We must still set scanline_offset
11745 * to 1 so that the vblank timestamps come out correct when we query
11746 * the scanline counter from within the vblank interrupt handler.
11747 * However if queried just before the start of vblank we'll get an
11748 * answer that's slightly in the future.
11750 if (IS_GEN2(dev_priv
)) {
11751 const struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
11754 vtotal
= adjusted_mode
->crtc_vtotal
;
11755 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
11758 crtc
->scanline_offset
= vtotal
- 1;
11759 } else if (HAS_DDI(dev_priv
) &&
11760 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_HDMI
)) {
11761 crtc
->scanline_offset
= 2;
11763 crtc
->scanline_offset
= 1;
11766 static void intel_modeset_clear_plls(struct drm_atomic_state
*state
)
11768 struct drm_device
*dev
= state
->dev
;
11769 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11770 struct drm_crtc
*crtc
;
11771 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
11774 if (!dev_priv
->display
.crtc_compute_clock
)
11777 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
11778 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11779 struct intel_shared_dpll
*old_dpll
=
11780 to_intel_crtc_state(old_crtc_state
)->shared_dpll
;
11782 if (!needs_modeset(new_crtc_state
))
11785 to_intel_crtc_state(new_crtc_state
)->shared_dpll
= NULL
;
11790 intel_release_shared_dpll(old_dpll
, intel_crtc
, state
);
11795 * This implements the workaround described in the "notes" section of the mode
11796 * set sequence documentation. When going from no pipes or single pipe to
11797 * multiple pipes, and planes are enabled after the pipe, we need to wait at
11798 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
11800 static int haswell_mode_set_planes_workaround(struct drm_atomic_state
*state
)
11802 struct drm_crtc_state
*crtc_state
;
11803 struct intel_crtc
*intel_crtc
;
11804 struct drm_crtc
*crtc
;
11805 struct intel_crtc_state
*first_crtc_state
= NULL
;
11806 struct intel_crtc_state
*other_crtc_state
= NULL
;
11807 enum pipe first_pipe
= INVALID_PIPE
, enabled_pipe
= INVALID_PIPE
;
11810 /* look at all crtc's that are going to be enabled in during modeset */
11811 for_each_new_crtc_in_state(state
, crtc
, crtc_state
, i
) {
11812 intel_crtc
= to_intel_crtc(crtc
);
11814 if (!crtc_state
->active
|| !needs_modeset(crtc_state
))
11817 if (first_crtc_state
) {
11818 other_crtc_state
= to_intel_crtc_state(crtc_state
);
11821 first_crtc_state
= to_intel_crtc_state(crtc_state
);
11822 first_pipe
= intel_crtc
->pipe
;
11826 /* No workaround needed? */
11827 if (!first_crtc_state
)
11830 /* w/a possibly needed, check how many crtc's are already enabled. */
11831 for_each_intel_crtc(state
->dev
, intel_crtc
) {
11832 struct intel_crtc_state
*pipe_config
;
11834 pipe_config
= intel_atomic_get_crtc_state(state
, intel_crtc
);
11835 if (IS_ERR(pipe_config
))
11836 return PTR_ERR(pipe_config
);
11838 pipe_config
->hsw_workaround_pipe
= INVALID_PIPE
;
11840 if (!pipe_config
->base
.active
||
11841 needs_modeset(&pipe_config
->base
))
11844 /* 2 or more enabled crtcs means no need for w/a */
11845 if (enabled_pipe
!= INVALID_PIPE
)
11848 enabled_pipe
= intel_crtc
->pipe
;
11851 if (enabled_pipe
!= INVALID_PIPE
)
11852 first_crtc_state
->hsw_workaround_pipe
= enabled_pipe
;
11853 else if (other_crtc_state
)
11854 other_crtc_state
->hsw_workaround_pipe
= first_pipe
;
11859 static int intel_lock_all_pipes(struct drm_atomic_state
*state
)
11861 struct drm_crtc
*crtc
;
11863 /* Add all pipes to the state */
11864 for_each_crtc(state
->dev
, crtc
) {
11865 struct drm_crtc_state
*crtc_state
;
11867 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
11868 if (IS_ERR(crtc_state
))
11869 return PTR_ERR(crtc_state
);
11875 static int intel_modeset_all_pipes(struct drm_atomic_state
*state
)
11877 struct drm_crtc
*crtc
;
11880 * Add all pipes to the state, and force
11881 * a modeset on all the active ones.
11883 for_each_crtc(state
->dev
, crtc
) {
11884 struct drm_crtc_state
*crtc_state
;
11887 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
11888 if (IS_ERR(crtc_state
))
11889 return PTR_ERR(crtc_state
);
11891 if (!crtc_state
->active
|| needs_modeset(crtc_state
))
11894 crtc_state
->mode_changed
= true;
11896 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
11900 ret
= drm_atomic_add_affected_planes(state
, crtc
);
11908 static int intel_modeset_checks(struct drm_atomic_state
*state
)
11910 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
11911 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
11912 struct drm_crtc
*crtc
;
11913 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
11916 if (!check_digital_port_conflicts(state
)) {
11917 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11921 intel_state
->modeset
= true;
11922 intel_state
->active_crtcs
= dev_priv
->active_crtcs
;
11923 intel_state
->cdclk
.logical
= dev_priv
->cdclk
.logical
;
11924 intel_state
->cdclk
.actual
= dev_priv
->cdclk
.actual
;
11926 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
11927 if (new_crtc_state
->active
)
11928 intel_state
->active_crtcs
|= 1 << i
;
11930 intel_state
->active_crtcs
&= ~(1 << i
);
11932 if (old_crtc_state
->active
!= new_crtc_state
->active
)
11933 intel_state
->active_pipe_changes
|= drm_crtc_mask(crtc
);
11937 * See if the config requires any additional preparation, e.g.
11938 * to adjust global state with pipes off. We need to do this
11939 * here so we can get the modeset_pipe updated config for the new
11940 * mode set on this crtc. For other crtcs we need to use the
11941 * adjusted_mode bits in the crtc directly.
11943 if (dev_priv
->display
.modeset_calc_cdclk
) {
11944 ret
= dev_priv
->display
.modeset_calc_cdclk(state
);
11949 * Writes to dev_priv->cdclk.logical must protected by
11950 * holding all the crtc locks, even if we don't end up
11951 * touching the hardware
11953 if (!intel_cdclk_state_compare(&dev_priv
->cdclk
.logical
,
11954 &intel_state
->cdclk
.logical
)) {
11955 ret
= intel_lock_all_pipes(state
);
11960 /* All pipes must be switched off while we change the cdclk. */
11961 if (!intel_cdclk_state_compare(&dev_priv
->cdclk
.actual
,
11962 &intel_state
->cdclk
.actual
)) {
11963 ret
= intel_modeset_all_pipes(state
);
11968 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
11969 intel_state
->cdclk
.logical
.cdclk
,
11970 intel_state
->cdclk
.actual
.cdclk
);
11972 to_intel_atomic_state(state
)->cdclk
.logical
= dev_priv
->cdclk
.logical
;
11975 intel_modeset_clear_plls(state
);
11977 if (IS_HASWELL(dev_priv
))
11978 return haswell_mode_set_planes_workaround(state
);
11984 * Handle calculation of various watermark data at the end of the atomic check
11985 * phase. The code here should be run after the per-crtc and per-plane 'check'
11986 * handlers to ensure that all derived state has been updated.
11988 static int calc_watermark_data(struct drm_atomic_state
*state
)
11990 struct drm_device
*dev
= state
->dev
;
11991 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11993 /* Is there platform-specific watermark information to calculate? */
11994 if (dev_priv
->display
.compute_global_watermarks
)
11995 return dev_priv
->display
.compute_global_watermarks(state
);
12001 * intel_atomic_check - validate state object
12003 * @state: state to validate
12005 static int intel_atomic_check(struct drm_device
*dev
,
12006 struct drm_atomic_state
*state
)
12008 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12009 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
12010 struct drm_crtc
*crtc
;
12011 struct drm_crtc_state
*old_crtc_state
, *crtc_state
;
12013 bool any_ms
= false;
12015 ret
= drm_atomic_helper_check_modeset(dev
, state
);
12019 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, crtc_state
, i
) {
12020 struct intel_crtc_state
*pipe_config
=
12021 to_intel_crtc_state(crtc_state
);
12023 /* Catch I915_MODE_FLAG_INHERITED */
12024 if (crtc_state
->mode
.private_flags
!= old_crtc_state
->mode
.private_flags
)
12025 crtc_state
->mode_changed
= true;
12027 if (!needs_modeset(crtc_state
))
12030 if (!crtc_state
->enable
) {
12035 /* FIXME: For only active_changed we shouldn't need to do any
12036 * state recomputation at all. */
12038 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
12042 ret
= intel_modeset_pipe_config(crtc
, pipe_config
);
12044 intel_dump_pipe_config(to_intel_crtc(crtc
),
12045 pipe_config
, "[failed]");
12049 if (i915_modparams
.fastboot
&&
12050 intel_pipe_config_compare(dev_priv
,
12051 to_intel_crtc_state(old_crtc_state
),
12052 pipe_config
, true)) {
12053 crtc_state
->mode_changed
= false;
12054 pipe_config
->update_pipe
= true;
12057 if (needs_modeset(crtc_state
))
12060 ret
= drm_atomic_add_affected_planes(state
, crtc
);
12064 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
12065 needs_modeset(crtc_state
) ?
12066 "[modeset]" : "[fastset]");
12070 ret
= intel_modeset_checks(state
);
12075 intel_state
->cdclk
.logical
= dev_priv
->cdclk
.logical
;
12078 ret
= drm_atomic_helper_check_planes(dev
, state
);
12082 intel_fbc_choose_crtc(dev_priv
, state
);
12083 return calc_watermark_data(state
);
12086 static int intel_atomic_prepare_commit(struct drm_device
*dev
,
12087 struct drm_atomic_state
*state
)
12089 return drm_atomic_helper_prepare_planes(dev
, state
);
12092 u32
intel_crtc_get_vblank_counter(struct intel_crtc
*crtc
)
12094 struct drm_device
*dev
= crtc
->base
.dev
;
12096 if (!dev
->max_vblank_count
)
12097 return drm_crtc_accurate_vblank_count(&crtc
->base
);
12099 return dev
->driver
->get_vblank_counter(dev
, crtc
->pipe
);
12102 static void intel_update_crtc(struct drm_crtc
*crtc
,
12103 struct drm_atomic_state
*state
,
12104 struct drm_crtc_state
*old_crtc_state
,
12105 struct drm_crtc_state
*new_crtc_state
)
12107 struct drm_device
*dev
= crtc
->dev
;
12108 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12109 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12110 struct intel_crtc_state
*pipe_config
= to_intel_crtc_state(new_crtc_state
);
12111 bool modeset
= needs_modeset(new_crtc_state
);
12114 update_scanline_offset(intel_crtc
);
12115 dev_priv
->display
.crtc_enable(pipe_config
, state
);
12117 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state
),
12121 if (drm_atomic_get_existing_plane_state(state
, crtc
->primary
)) {
12123 intel_crtc
, pipe_config
,
12124 to_intel_plane_state(crtc
->primary
->state
));
12127 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state
);
12130 static void intel_update_crtcs(struct drm_atomic_state
*state
)
12132 struct drm_crtc
*crtc
;
12133 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
12136 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
12137 if (!new_crtc_state
->active
)
12140 intel_update_crtc(crtc
, state
, old_crtc_state
,
12145 static void skl_update_crtcs(struct drm_atomic_state
*state
)
12147 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
12148 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
12149 struct drm_crtc
*crtc
;
12150 struct intel_crtc
*intel_crtc
;
12151 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
12152 struct intel_crtc_state
*cstate
;
12153 unsigned int updated
= 0;
12158 const struct skl_ddb_entry
*entries
[I915_MAX_PIPES
] = {};
12160 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
)
12161 /* ignore allocations for crtc's that have been turned off. */
12162 if (new_crtc_state
->active
)
12163 entries
[i
] = &to_intel_crtc_state(old_crtc_state
)->wm
.skl
.ddb
;
12166 * Whenever the number of active pipes changes, we need to make sure we
12167 * update the pipes in the right order so that their ddb allocations
12168 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12169 * cause pipe underruns and other bad stuff.
12174 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
12175 bool vbl_wait
= false;
12176 unsigned int cmask
= drm_crtc_mask(crtc
);
12178 intel_crtc
= to_intel_crtc(crtc
);
12179 cstate
= to_intel_crtc_state(new_crtc_state
);
12180 pipe
= intel_crtc
->pipe
;
12182 if (updated
& cmask
|| !cstate
->base
.active
)
12185 if (skl_ddb_allocation_overlaps(dev_priv
,
12187 &cstate
->wm
.skl
.ddb
,
12192 entries
[i
] = &cstate
->wm
.skl
.ddb
;
12195 * If this is an already active pipe, it's DDB changed,
12196 * and this isn't the last pipe that needs updating
12197 * then we need to wait for a vblank to pass for the
12198 * new ddb allocation to take effect.
12200 if (!skl_ddb_entry_equal(&cstate
->wm
.skl
.ddb
,
12201 &to_intel_crtc_state(old_crtc_state
)->wm
.skl
.ddb
) &&
12202 !new_crtc_state
->active_changed
&&
12203 intel_state
->wm_results
.dirty_pipes
!= updated
)
12206 intel_update_crtc(crtc
, state
, old_crtc_state
,
12210 intel_wait_for_vblank(dev_priv
, pipe
);
12214 } while (progress
);
12217 static void intel_atomic_helper_free_state(struct drm_i915_private
*dev_priv
)
12219 struct intel_atomic_state
*state
, *next
;
12220 struct llist_node
*freed
;
12222 freed
= llist_del_all(&dev_priv
->atomic_helper
.free_list
);
12223 llist_for_each_entry_safe(state
, next
, freed
, freed
)
12224 drm_atomic_state_put(&state
->base
);
12227 static void intel_atomic_helper_free_state_worker(struct work_struct
*work
)
12229 struct drm_i915_private
*dev_priv
=
12230 container_of(work
, typeof(*dev_priv
), atomic_helper
.free_work
);
12232 intel_atomic_helper_free_state(dev_priv
);
12235 static void intel_atomic_commit_fence_wait(struct intel_atomic_state
*intel_state
)
12237 struct wait_queue_entry wait_fence
, wait_reset
;
12238 struct drm_i915_private
*dev_priv
= to_i915(intel_state
->base
.dev
);
12240 init_wait_entry(&wait_fence
, 0);
12241 init_wait_entry(&wait_reset
, 0);
12243 prepare_to_wait(&intel_state
->commit_ready
.wait
,
12244 &wait_fence
, TASK_UNINTERRUPTIBLE
);
12245 prepare_to_wait(&dev_priv
->gpu_error
.wait_queue
,
12246 &wait_reset
, TASK_UNINTERRUPTIBLE
);
12249 if (i915_sw_fence_done(&intel_state
->commit_ready
)
12250 || test_bit(I915_RESET_MODESET
, &dev_priv
->gpu_error
.flags
))
12255 finish_wait(&intel_state
->commit_ready
.wait
, &wait_fence
);
12256 finish_wait(&dev_priv
->gpu_error
.wait_queue
, &wait_reset
);
12259 static void intel_atomic_commit_tail(struct drm_atomic_state
*state
)
12261 struct drm_device
*dev
= state
->dev
;
12262 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
12263 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12264 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
12265 struct drm_crtc
*crtc
;
12266 struct intel_crtc_state
*intel_cstate
;
12267 u64 put_domains
[I915_MAX_PIPES
] = {};
12270 intel_atomic_commit_fence_wait(intel_state
);
12272 drm_atomic_helper_wait_for_dependencies(state
);
12274 if (intel_state
->modeset
)
12275 intel_display_power_get(dev_priv
, POWER_DOMAIN_MODESET
);
12277 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
12278 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12280 if (needs_modeset(new_crtc_state
) ||
12281 to_intel_crtc_state(new_crtc_state
)->update_pipe
) {
12283 put_domains
[to_intel_crtc(crtc
)->pipe
] =
12284 modeset_get_crtc_power_domains(crtc
,
12285 to_intel_crtc_state(new_crtc_state
));
12288 if (!needs_modeset(new_crtc_state
))
12291 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state
),
12292 to_intel_crtc_state(new_crtc_state
));
12294 if (old_crtc_state
->active
) {
12295 intel_crtc_disable_planes(crtc
, old_crtc_state
->plane_mask
);
12296 dev_priv
->display
.crtc_disable(to_intel_crtc_state(old_crtc_state
), state
);
12297 intel_crtc
->active
= false;
12298 intel_fbc_disable(intel_crtc
);
12299 intel_disable_shared_dpll(intel_crtc
);
12302 * Underruns don't always raise
12303 * interrupts, so check manually.
12305 intel_check_cpu_fifo_underruns(dev_priv
);
12306 intel_check_pch_fifo_underruns(dev_priv
);
12308 if (!new_crtc_state
->active
) {
12310 * Make sure we don't call initial_watermarks
12311 * for ILK-style watermark updates.
12313 * No clue what this is supposed to achieve.
12315 if (INTEL_GEN(dev_priv
) >= 9)
12316 dev_priv
->display
.initial_watermarks(intel_state
,
12317 to_intel_crtc_state(new_crtc_state
));
12322 /* Only after disabling all output pipelines that will be changed can we
12323 * update the the output configuration. */
12324 intel_modeset_update_crtc_state(state
);
12326 if (intel_state
->modeset
) {
12327 drm_atomic_helper_update_legacy_modeset_state(state
->dev
, state
);
12329 intel_set_cdclk(dev_priv
, &dev_priv
->cdclk
.actual
);
12332 * SKL workaround: bspec recommends we disable the SAGV when we
12333 * have more then one pipe enabled
12335 if (!intel_can_enable_sagv(state
))
12336 intel_disable_sagv(dev_priv
);
12338 intel_modeset_verify_disabled(dev
, state
);
12341 /* Complete the events for pipes that have now been disabled */
12342 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
12343 bool modeset
= needs_modeset(new_crtc_state
);
12345 /* Complete events for now disable pipes here. */
12346 if (modeset
&& !new_crtc_state
->active
&& new_crtc_state
->event
) {
12347 spin_lock_irq(&dev
->event_lock
);
12348 drm_crtc_send_vblank_event(crtc
, new_crtc_state
->event
);
12349 spin_unlock_irq(&dev
->event_lock
);
12351 new_crtc_state
->event
= NULL
;
12355 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12356 dev_priv
->display
.update_crtcs(state
);
12358 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12359 * already, but still need the state for the delayed optimization. To
12361 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12362 * - schedule that vblank worker _before_ calling hw_done
12363 * - at the start of commit_tail, cancel it _synchrously
12364 * - switch over to the vblank wait helper in the core after that since
12365 * we don't need out special handling any more.
12367 drm_atomic_helper_wait_for_flip_done(dev
, state
);
12370 * Now that the vblank has passed, we can go ahead and program the
12371 * optimal watermarks on platforms that need two-step watermark
12374 * TODO: Move this (and other cleanup) to an async worker eventually.
12376 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
12377 intel_cstate
= to_intel_crtc_state(new_crtc_state
);
12379 if (dev_priv
->display
.optimize_watermarks
)
12380 dev_priv
->display
.optimize_watermarks(intel_state
,
12384 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
12385 intel_post_plane_update(to_intel_crtc_state(old_crtc_state
));
12387 if (put_domains
[i
])
12388 modeset_put_power_domains(dev_priv
, put_domains
[i
]);
12390 intel_modeset_verify_crtc(crtc
, state
, old_crtc_state
, new_crtc_state
);
12393 if (intel_state
->modeset
&& intel_can_enable_sagv(state
))
12394 intel_enable_sagv(dev_priv
);
12396 drm_atomic_helper_commit_hw_done(state
);
12398 if (intel_state
->modeset
) {
12399 /* As one of the primary mmio accessors, KMS has a high
12400 * likelihood of triggering bugs in unclaimed access. After we
12401 * finish modesetting, see if an error has been flagged, and if
12402 * so enable debugging for the next modeset - and hope we catch
12405 intel_uncore_arm_unclaimed_mmio_detection(dev_priv
);
12406 intel_display_power_put(dev_priv
, POWER_DOMAIN_MODESET
);
12409 drm_atomic_helper_cleanup_planes(dev
, state
);
12411 drm_atomic_helper_commit_cleanup_done(state
);
12413 drm_atomic_state_put(state
);
12415 intel_atomic_helper_free_state(dev_priv
);
12418 static void intel_atomic_commit_work(struct work_struct
*work
)
12420 struct drm_atomic_state
*state
=
12421 container_of(work
, struct drm_atomic_state
, commit_work
);
12423 intel_atomic_commit_tail(state
);
12426 static int __i915_sw_fence_call
12427 intel_atomic_commit_ready(struct i915_sw_fence
*fence
,
12428 enum i915_sw_fence_notify notify
)
12430 struct intel_atomic_state
*state
=
12431 container_of(fence
, struct intel_atomic_state
, commit_ready
);
12434 case FENCE_COMPLETE
:
12435 /* we do blocking waits in the worker, nothing to do here */
12439 struct intel_atomic_helper
*helper
=
12440 &to_i915(state
->base
.dev
)->atomic_helper
;
12442 if (llist_add(&state
->freed
, &helper
->free_list
))
12443 schedule_work(&helper
->free_work
);
12448 return NOTIFY_DONE
;
12451 static void intel_atomic_track_fbs(struct drm_atomic_state
*state
)
12453 struct drm_plane_state
*old_plane_state
, *new_plane_state
;
12454 struct drm_plane
*plane
;
12457 for_each_oldnew_plane_in_state(state
, plane
, old_plane_state
, new_plane_state
, i
)
12458 i915_gem_track_fb(intel_fb_obj(old_plane_state
->fb
),
12459 intel_fb_obj(new_plane_state
->fb
),
12460 to_intel_plane(plane
)->frontbuffer_bit
);
12464 * intel_atomic_commit - commit validated state object
12466 * @state: the top-level driver state object
12467 * @nonblock: nonblocking commit
12469 * This function commits a top-level state object that has been validated
12470 * with drm_atomic_helper_check().
12473 * Zero for success or -errno.
12475 static int intel_atomic_commit(struct drm_device
*dev
,
12476 struct drm_atomic_state
*state
,
12479 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
12480 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12483 drm_atomic_state_get(state
);
12484 i915_sw_fence_init(&intel_state
->commit_ready
,
12485 intel_atomic_commit_ready
);
12488 * The intel_legacy_cursor_update() fast path takes care
12489 * of avoiding the vblank waits for simple cursor
12490 * movement and flips. For cursor on/off and size changes,
12491 * we want to perform the vblank waits so that watermark
12492 * updates happen during the correct frames. Gen9+ have
12493 * double buffered watermarks and so shouldn't need this.
12495 * Unset state->legacy_cursor_update before the call to
12496 * drm_atomic_helper_setup_commit() because otherwise
12497 * drm_atomic_helper_wait_for_flip_done() is a noop and
12498 * we get FIFO underruns because we didn't wait
12501 * FIXME doing watermarks and fb cleanup from a vblank worker
12502 * (assuming we had any) would solve these problems.
12504 if (INTEL_GEN(dev_priv
) < 9 && state
->legacy_cursor_update
) {
12505 struct intel_crtc_state
*new_crtc_state
;
12506 struct intel_crtc
*crtc
;
12509 for_each_new_intel_crtc_in_state(intel_state
, crtc
, new_crtc_state
, i
)
12510 if (new_crtc_state
->wm
.need_postvbl_update
||
12511 new_crtc_state
->update_wm_post
)
12512 state
->legacy_cursor_update
= false;
12515 ret
= intel_atomic_prepare_commit(dev
, state
);
12517 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret
);
12518 i915_sw_fence_commit(&intel_state
->commit_ready
);
12522 ret
= drm_atomic_helper_setup_commit(state
, nonblock
);
12524 ret
= drm_atomic_helper_swap_state(state
, true);
12527 i915_sw_fence_commit(&intel_state
->commit_ready
);
12529 drm_atomic_helper_cleanup_planes(dev
, state
);
12532 dev_priv
->wm
.distrust_bios_wm
= false;
12533 intel_shared_dpll_swap_state(state
);
12534 intel_atomic_track_fbs(state
);
12536 if (intel_state
->modeset
) {
12537 memcpy(dev_priv
->min_cdclk
, intel_state
->min_cdclk
,
12538 sizeof(intel_state
->min_cdclk
));
12539 dev_priv
->active_crtcs
= intel_state
->active_crtcs
;
12540 dev_priv
->cdclk
.logical
= intel_state
->cdclk
.logical
;
12541 dev_priv
->cdclk
.actual
= intel_state
->cdclk
.actual
;
12544 drm_atomic_state_get(state
);
12545 INIT_WORK(&state
->commit_work
, intel_atomic_commit_work
);
12547 i915_sw_fence_commit(&intel_state
->commit_ready
);
12549 queue_work(system_unbound_wq
, &state
->commit_work
);
12551 intel_atomic_commit_tail(state
);
12557 static const struct drm_crtc_funcs intel_crtc_funcs
= {
12558 .gamma_set
= drm_atomic_helper_legacy_gamma_set
,
12559 .set_config
= drm_atomic_helper_set_config
,
12560 .destroy
= intel_crtc_destroy
,
12561 .page_flip
= drm_atomic_helper_page_flip
,
12562 .atomic_duplicate_state
= intel_crtc_duplicate_state
,
12563 .atomic_destroy_state
= intel_crtc_destroy_state
,
12564 .set_crc_source
= intel_crtc_set_crc_source
,
12567 struct wait_rps_boost
{
12568 struct wait_queue_entry wait
;
12570 struct drm_crtc
*crtc
;
12571 struct drm_i915_gem_request
*request
;
12574 static int do_rps_boost(struct wait_queue_entry
*_wait
,
12575 unsigned mode
, int sync
, void *key
)
12577 struct wait_rps_boost
*wait
= container_of(_wait
, typeof(*wait
), wait
);
12578 struct drm_i915_gem_request
*rq
= wait
->request
;
12580 gen6_rps_boost(rq
, NULL
);
12581 i915_gem_request_put(rq
);
12583 drm_crtc_vblank_put(wait
->crtc
);
12585 list_del(&wait
->wait
.entry
);
12590 static void add_rps_boost_after_vblank(struct drm_crtc
*crtc
,
12591 struct dma_fence
*fence
)
12593 struct wait_rps_boost
*wait
;
12595 if (!dma_fence_is_i915(fence
))
12598 if (INTEL_GEN(to_i915(crtc
->dev
)) < 6)
12601 if (drm_crtc_vblank_get(crtc
))
12604 wait
= kmalloc(sizeof(*wait
), GFP_KERNEL
);
12606 drm_crtc_vblank_put(crtc
);
12610 wait
->request
= to_request(dma_fence_get(fence
));
12613 wait
->wait
.func
= do_rps_boost
;
12614 wait
->wait
.flags
= 0;
12616 add_wait_queue(drm_crtc_vblank_waitqueue(crtc
), &wait
->wait
);
12620 * intel_prepare_plane_fb - Prepare fb for usage on plane
12621 * @plane: drm plane to prepare for
12622 * @fb: framebuffer to prepare for presentation
12624 * Prepares a framebuffer for usage on a display plane. Generally this
12625 * involves pinning the underlying object and updating the frontbuffer tracking
12626 * bits. Some older platforms need special physical address handling for
12629 * Must be called with struct_mutex held.
12631 * Returns 0 on success, negative error code on failure.
12634 intel_prepare_plane_fb(struct drm_plane
*plane
,
12635 struct drm_plane_state
*new_state
)
12637 struct intel_atomic_state
*intel_state
=
12638 to_intel_atomic_state(new_state
->state
);
12639 struct drm_i915_private
*dev_priv
= to_i915(plane
->dev
);
12640 struct drm_framebuffer
*fb
= new_state
->fb
;
12641 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
12642 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->state
->fb
);
12646 struct drm_crtc_state
*crtc_state
=
12647 drm_atomic_get_existing_crtc_state(new_state
->state
,
12648 plane
->state
->crtc
);
12650 /* Big Hammer, we also need to ensure that any pending
12651 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
12652 * current scanout is retired before unpinning the old
12653 * framebuffer. Note that we rely on userspace rendering
12654 * into the buffer attached to the pipe they are waiting
12655 * on. If not, userspace generates a GPU hang with IPEHR
12656 * point to the MI_WAIT_FOR_EVENT.
12658 * This should only fail upon a hung GPU, in which case we
12659 * can safely continue.
12661 if (needs_modeset(crtc_state
)) {
12662 ret
= i915_sw_fence_await_reservation(&intel_state
->commit_ready
,
12663 old_obj
->resv
, NULL
,
12671 if (new_state
->fence
) { /* explicit fencing */
12672 ret
= i915_sw_fence_await_dma_fence(&intel_state
->commit_ready
,
12674 I915_FENCE_TIMEOUT
,
12683 ret
= i915_gem_object_pin_pages(obj
);
12687 ret
= mutex_lock_interruptible(&dev_priv
->drm
.struct_mutex
);
12689 i915_gem_object_unpin_pages(obj
);
12693 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
&&
12694 INTEL_INFO(dev_priv
)->cursor_needs_physical
) {
12695 const int align
= intel_cursor_alignment(dev_priv
);
12697 ret
= i915_gem_object_attach_phys(obj
, align
);
12699 struct i915_vma
*vma
;
12701 vma
= intel_pin_and_fence_fb_obj(fb
, new_state
->rotation
);
12703 to_intel_plane_state(new_state
)->vma
= vma
;
12705 ret
= PTR_ERR(vma
);
12708 i915_gem_object_wait_priority(obj
, 0, I915_PRIORITY_DISPLAY
);
12710 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
12711 i915_gem_object_unpin_pages(obj
);
12715 if (!new_state
->fence
) { /* implicit fencing */
12716 struct dma_fence
*fence
;
12718 ret
= i915_sw_fence_await_reservation(&intel_state
->commit_ready
,
12720 false, I915_FENCE_TIMEOUT
,
12725 fence
= reservation_object_get_excl_rcu(obj
->resv
);
12727 add_rps_boost_after_vblank(new_state
->crtc
, fence
);
12728 dma_fence_put(fence
);
12731 add_rps_boost_after_vblank(new_state
->crtc
, new_state
->fence
);
12738 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12739 * @plane: drm plane to clean up for
12740 * @fb: old framebuffer that was on plane
12742 * Cleans up a framebuffer that has just been removed from a plane.
12744 * Must be called with struct_mutex held.
12747 intel_cleanup_plane_fb(struct drm_plane
*plane
,
12748 struct drm_plane_state
*old_state
)
12750 struct i915_vma
*vma
;
12752 /* Should only be called after a successful intel_prepare_plane_fb()! */
12753 vma
= fetch_and_zero(&to_intel_plane_state(old_state
)->vma
);
12755 mutex_lock(&plane
->dev
->struct_mutex
);
12756 intel_unpin_fb_vma(vma
);
12757 mutex_unlock(&plane
->dev
->struct_mutex
);
12762 skl_max_scale(struct intel_crtc
*intel_crtc
, struct intel_crtc_state
*crtc_state
)
12764 struct drm_i915_private
*dev_priv
;
12766 int crtc_clock
, max_dotclk
;
12768 if (!intel_crtc
|| !crtc_state
->base
.enable
)
12769 return DRM_PLANE_HELPER_NO_SCALING
;
12771 dev_priv
= to_i915(intel_crtc
->base
.dev
);
12773 crtc_clock
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
12774 max_dotclk
= to_intel_atomic_state(crtc_state
->base
.state
)->cdclk
.logical
.cdclk
;
12776 if (IS_GEMINILAKE(dev_priv
))
12779 if (WARN_ON_ONCE(!crtc_clock
|| max_dotclk
< crtc_clock
))
12780 return DRM_PLANE_HELPER_NO_SCALING
;
12783 * skl max scale is lower of:
12784 * close to 3 but not 3, -1 is for that purpose
12788 max_scale
= min((1 << 16) * 3 - 1,
12789 (1 << 8) * ((max_dotclk
<< 8) / crtc_clock
));
12795 intel_check_primary_plane(struct intel_plane
*plane
,
12796 struct intel_crtc_state
*crtc_state
,
12797 struct intel_plane_state
*state
)
12799 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
12800 struct drm_crtc
*crtc
= state
->base
.crtc
;
12801 int min_scale
= DRM_PLANE_HELPER_NO_SCALING
;
12802 int max_scale
= DRM_PLANE_HELPER_NO_SCALING
;
12803 bool can_position
= false;
12806 if (INTEL_GEN(dev_priv
) >= 9) {
12807 /* use scaler when colorkey is not required */
12808 if (state
->ckey
.flags
== I915_SET_COLORKEY_NONE
) {
12810 max_scale
= skl_max_scale(to_intel_crtc(crtc
), crtc_state
);
12812 can_position
= true;
12815 ret
= drm_plane_helper_check_state(&state
->base
,
12817 min_scale
, max_scale
,
12818 can_position
, true);
12822 if (!state
->base
.fb
)
12825 if (INTEL_GEN(dev_priv
) >= 9) {
12826 ret
= skl_check_plane_surface(state
);
12830 state
->ctl
= skl_plane_ctl(crtc_state
, state
);
12832 ret
= i9xx_check_plane_surface(state
);
12836 state
->ctl
= i9xx_plane_ctl(crtc_state
, state
);
12842 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
,
12843 struct drm_crtc_state
*old_crtc_state
)
12845 struct drm_device
*dev
= crtc
->dev
;
12846 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12847 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12848 struct intel_crtc_state
*old_intel_cstate
=
12849 to_intel_crtc_state(old_crtc_state
);
12850 struct intel_atomic_state
*old_intel_state
=
12851 to_intel_atomic_state(old_crtc_state
->state
);
12852 struct intel_crtc_state
*intel_cstate
=
12853 intel_atomic_get_new_crtc_state(old_intel_state
, intel_crtc
);
12854 bool modeset
= needs_modeset(&intel_cstate
->base
);
12857 (intel_cstate
->base
.color_mgmt_changed
||
12858 intel_cstate
->update_pipe
)) {
12859 intel_color_set_csc(&intel_cstate
->base
);
12860 intel_color_load_luts(&intel_cstate
->base
);
12863 /* Perform vblank evasion around commit operation */
12864 intel_pipe_update_start(intel_cstate
);
12869 if (intel_cstate
->update_pipe
)
12870 intel_update_pipe_config(old_intel_cstate
, intel_cstate
);
12871 else if (INTEL_GEN(dev_priv
) >= 9)
12872 skl_detach_scalers(intel_crtc
);
12875 if (dev_priv
->display
.atomic_update_watermarks
)
12876 dev_priv
->display
.atomic_update_watermarks(old_intel_state
,
12880 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
,
12881 struct drm_crtc_state
*old_crtc_state
)
12883 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12884 struct intel_atomic_state
*old_intel_state
=
12885 to_intel_atomic_state(old_crtc_state
->state
);
12886 struct intel_crtc_state
*new_crtc_state
=
12887 intel_atomic_get_new_crtc_state(old_intel_state
, intel_crtc
);
12889 intel_pipe_update_end(new_crtc_state
);
12893 * intel_plane_destroy - destroy a plane
12894 * @plane: plane to destroy
12896 * Common destruction function for all types of planes (primary, cursor,
12899 void intel_plane_destroy(struct drm_plane
*plane
)
12901 drm_plane_cleanup(plane
);
12902 kfree(to_intel_plane(plane
));
12905 static bool i8xx_mod_supported(uint32_t format
, uint64_t modifier
)
12908 case DRM_FORMAT_C8
:
12909 case DRM_FORMAT_RGB565
:
12910 case DRM_FORMAT_XRGB1555
:
12911 case DRM_FORMAT_XRGB8888
:
12912 return modifier
== DRM_FORMAT_MOD_LINEAR
||
12913 modifier
== I915_FORMAT_MOD_X_TILED
;
12919 static bool i965_mod_supported(uint32_t format
, uint64_t modifier
)
12922 case DRM_FORMAT_C8
:
12923 case DRM_FORMAT_RGB565
:
12924 case DRM_FORMAT_XRGB8888
:
12925 case DRM_FORMAT_XBGR8888
:
12926 case DRM_FORMAT_XRGB2101010
:
12927 case DRM_FORMAT_XBGR2101010
:
12928 return modifier
== DRM_FORMAT_MOD_LINEAR
||
12929 modifier
== I915_FORMAT_MOD_X_TILED
;
12935 static bool skl_mod_supported(uint32_t format
, uint64_t modifier
)
12938 case DRM_FORMAT_XRGB8888
:
12939 case DRM_FORMAT_XBGR8888
:
12940 case DRM_FORMAT_ARGB8888
:
12941 case DRM_FORMAT_ABGR8888
:
12942 if (modifier
== I915_FORMAT_MOD_Yf_TILED_CCS
||
12943 modifier
== I915_FORMAT_MOD_Y_TILED_CCS
)
12946 case DRM_FORMAT_RGB565
:
12947 case DRM_FORMAT_XRGB2101010
:
12948 case DRM_FORMAT_XBGR2101010
:
12949 case DRM_FORMAT_YUYV
:
12950 case DRM_FORMAT_YVYU
:
12951 case DRM_FORMAT_UYVY
:
12952 case DRM_FORMAT_VYUY
:
12953 if (modifier
== I915_FORMAT_MOD_Yf_TILED
)
12956 case DRM_FORMAT_C8
:
12957 if (modifier
== DRM_FORMAT_MOD_LINEAR
||
12958 modifier
== I915_FORMAT_MOD_X_TILED
||
12959 modifier
== I915_FORMAT_MOD_Y_TILED
)
12967 static bool intel_primary_plane_format_mod_supported(struct drm_plane
*plane
,
12971 struct drm_i915_private
*dev_priv
= to_i915(plane
->dev
);
12973 if (WARN_ON(modifier
== DRM_FORMAT_MOD_INVALID
))
12976 if ((modifier
>> 56) != DRM_FORMAT_MOD_VENDOR_INTEL
&&
12977 modifier
!= DRM_FORMAT_MOD_LINEAR
)
12980 if (INTEL_GEN(dev_priv
) >= 9)
12981 return skl_mod_supported(format
, modifier
);
12982 else if (INTEL_GEN(dev_priv
) >= 4)
12983 return i965_mod_supported(format
, modifier
);
12985 return i8xx_mod_supported(format
, modifier
);
12990 static bool intel_cursor_plane_format_mod_supported(struct drm_plane
*plane
,
12994 if (WARN_ON(modifier
== DRM_FORMAT_MOD_INVALID
))
12997 return modifier
== DRM_FORMAT_MOD_LINEAR
&& format
== DRM_FORMAT_ARGB8888
;
13000 static struct drm_plane_funcs intel_plane_funcs
= {
13001 .update_plane
= drm_atomic_helper_update_plane
,
13002 .disable_plane
= drm_atomic_helper_disable_plane
,
13003 .destroy
= intel_plane_destroy
,
13004 .atomic_get_property
= intel_plane_atomic_get_property
,
13005 .atomic_set_property
= intel_plane_atomic_set_property
,
13006 .atomic_duplicate_state
= intel_plane_duplicate_state
,
13007 .atomic_destroy_state
= intel_plane_destroy_state
,
13008 .format_mod_supported
= intel_primary_plane_format_mod_supported
,
13012 intel_legacy_cursor_update(struct drm_plane
*plane
,
13013 struct drm_crtc
*crtc
,
13014 struct drm_framebuffer
*fb
,
13015 int crtc_x
, int crtc_y
,
13016 unsigned int crtc_w
, unsigned int crtc_h
,
13017 uint32_t src_x
, uint32_t src_y
,
13018 uint32_t src_w
, uint32_t src_h
,
13019 struct drm_modeset_acquire_ctx
*ctx
)
13021 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
13023 struct drm_plane_state
*old_plane_state
, *new_plane_state
;
13024 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
13025 struct drm_framebuffer
*old_fb
;
13026 struct drm_crtc_state
*crtc_state
= crtc
->state
;
13027 struct i915_vma
*old_vma
, *vma
;
13030 * When crtc is inactive or there is a modeset pending,
13031 * wait for it to complete in the slowpath
13033 if (!crtc_state
->active
|| needs_modeset(crtc_state
) ||
13034 to_intel_crtc_state(crtc_state
)->update_pipe
)
13037 old_plane_state
= plane
->state
;
13039 * Don't do an async update if there is an outstanding commit modifying
13040 * the plane. This prevents our async update's changes from getting
13041 * overridden by a previous synchronous update's state.
13043 if (old_plane_state
->commit
&&
13044 !try_wait_for_completion(&old_plane_state
->commit
->hw_done
))
13048 * If any parameters change that may affect watermarks,
13049 * take the slowpath. Only changing fb or position should be
13052 if (old_plane_state
->crtc
!= crtc
||
13053 old_plane_state
->src_w
!= src_w
||
13054 old_plane_state
->src_h
!= src_h
||
13055 old_plane_state
->crtc_w
!= crtc_w
||
13056 old_plane_state
->crtc_h
!= crtc_h
||
13057 !old_plane_state
->fb
!= !fb
)
13060 new_plane_state
= intel_plane_duplicate_state(plane
);
13061 if (!new_plane_state
)
13064 drm_atomic_set_fb_for_plane(new_plane_state
, fb
);
13066 new_plane_state
->src_x
= src_x
;
13067 new_plane_state
->src_y
= src_y
;
13068 new_plane_state
->src_w
= src_w
;
13069 new_plane_state
->src_h
= src_h
;
13070 new_plane_state
->crtc_x
= crtc_x
;
13071 new_plane_state
->crtc_y
= crtc_y
;
13072 new_plane_state
->crtc_w
= crtc_w
;
13073 new_plane_state
->crtc_h
= crtc_h
;
13075 ret
= intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc
->state
),
13076 to_intel_crtc_state(crtc
->state
), /* FIXME need a new crtc state? */
13077 to_intel_plane_state(plane
->state
),
13078 to_intel_plane_state(new_plane_state
));
13082 ret
= mutex_lock_interruptible(&dev_priv
->drm
.struct_mutex
);
13086 if (INTEL_INFO(dev_priv
)->cursor_needs_physical
) {
13087 int align
= intel_cursor_alignment(dev_priv
);
13089 ret
= i915_gem_object_attach_phys(intel_fb_obj(fb
), align
);
13091 DRM_DEBUG_KMS("failed to attach phys object\n");
13095 vma
= intel_pin_and_fence_fb_obj(fb
, new_plane_state
->rotation
);
13097 DRM_DEBUG_KMS("failed to pin object\n");
13099 ret
= PTR_ERR(vma
);
13103 to_intel_plane_state(new_plane_state
)->vma
= vma
;
13106 old_fb
= old_plane_state
->fb
;
13108 i915_gem_track_fb(intel_fb_obj(old_fb
), intel_fb_obj(fb
),
13109 intel_plane
->frontbuffer_bit
);
13111 /* Swap plane state */
13112 plane
->state
= new_plane_state
;
13114 if (plane
->state
->visible
) {
13115 trace_intel_update_plane(plane
, to_intel_crtc(crtc
));
13116 intel_plane
->update_plane(intel_plane
,
13117 to_intel_crtc_state(crtc
->state
),
13118 to_intel_plane_state(plane
->state
));
13120 trace_intel_disable_plane(plane
, to_intel_crtc(crtc
));
13121 intel_plane
->disable_plane(intel_plane
, to_intel_crtc(crtc
));
13124 old_vma
= fetch_and_zero(&to_intel_plane_state(old_plane_state
)->vma
);
13126 intel_unpin_fb_vma(old_vma
);
13129 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
13132 intel_plane_destroy_state(plane
, new_plane_state
);
13134 intel_plane_destroy_state(plane
, old_plane_state
);
13138 return drm_atomic_helper_update_plane(plane
, crtc
, fb
,
13139 crtc_x
, crtc_y
, crtc_w
, crtc_h
,
13140 src_x
, src_y
, src_w
, src_h
, ctx
);
13143 static const struct drm_plane_funcs intel_cursor_plane_funcs
= {
13144 .update_plane
= intel_legacy_cursor_update
,
13145 .disable_plane
= drm_atomic_helper_disable_plane
,
13146 .destroy
= intel_plane_destroy
,
13147 .atomic_get_property
= intel_plane_atomic_get_property
,
13148 .atomic_set_property
= intel_plane_atomic_set_property
,
13149 .atomic_duplicate_state
= intel_plane_duplicate_state
,
13150 .atomic_destroy_state
= intel_plane_destroy_state
,
13151 .format_mod_supported
= intel_cursor_plane_format_mod_supported
,
13154 static struct intel_plane
*
13155 intel_primary_plane_create(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
13157 struct intel_plane
*primary
= NULL
;
13158 struct intel_plane_state
*state
= NULL
;
13159 const uint32_t *intel_primary_formats
;
13160 unsigned int supported_rotations
;
13161 unsigned int num_formats
;
13162 const uint64_t *modifiers
;
13165 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
13171 state
= intel_create_plane_state(&primary
->base
);
13177 primary
->base
.state
= &state
->base
;
13179 primary
->can_scale
= false;
13180 primary
->max_downscale
= 1;
13181 if (INTEL_GEN(dev_priv
) >= 9) {
13182 primary
->can_scale
= true;
13183 state
->scaler_id
= -1;
13185 primary
->pipe
= pipe
;
13187 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13188 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13190 if (HAS_FBC(dev_priv
) && INTEL_GEN(dev_priv
) < 4)
13191 primary
->plane
= (enum plane
) !pipe
;
13193 primary
->plane
= (enum plane
) pipe
;
13194 primary
->id
= PLANE_PRIMARY
;
13195 primary
->frontbuffer_bit
= INTEL_FRONTBUFFER_PRIMARY(pipe
);
13196 primary
->check_plane
= intel_check_primary_plane
;
13198 if (INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
)) {
13199 intel_primary_formats
= skl_primary_formats
;
13200 num_formats
= ARRAY_SIZE(skl_primary_formats
);
13201 modifiers
= skl_format_modifiers_ccs
;
13203 primary
->update_plane
= skl_update_plane
;
13204 primary
->disable_plane
= skl_disable_plane
;
13205 } else if (INTEL_GEN(dev_priv
) >= 9) {
13206 intel_primary_formats
= skl_primary_formats
;
13207 num_formats
= ARRAY_SIZE(skl_primary_formats
);
13209 modifiers
= skl_format_modifiers_ccs
;
13211 modifiers
= skl_format_modifiers_noccs
;
13213 primary
->update_plane
= skl_update_plane
;
13214 primary
->disable_plane
= skl_disable_plane
;
13215 } else if (INTEL_GEN(dev_priv
) >= 4) {
13216 intel_primary_formats
= i965_primary_formats
;
13217 num_formats
= ARRAY_SIZE(i965_primary_formats
);
13218 modifiers
= i9xx_format_modifiers
;
13220 primary
->update_plane
= i9xx_update_primary_plane
;
13221 primary
->disable_plane
= i9xx_disable_primary_plane
;
13223 intel_primary_formats
= i8xx_primary_formats
;
13224 num_formats
= ARRAY_SIZE(i8xx_primary_formats
);
13225 modifiers
= i9xx_format_modifiers
;
13227 primary
->update_plane
= i9xx_update_primary_plane
;
13228 primary
->disable_plane
= i9xx_disable_primary_plane
;
13231 if (INTEL_GEN(dev_priv
) >= 9)
13232 ret
= drm_universal_plane_init(&dev_priv
->drm
, &primary
->base
,
13233 0, &intel_plane_funcs
,
13234 intel_primary_formats
, num_formats
,
13236 DRM_PLANE_TYPE_PRIMARY
,
13237 "plane 1%c", pipe_name(pipe
));
13238 else if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
13239 ret
= drm_universal_plane_init(&dev_priv
->drm
, &primary
->base
,
13240 0, &intel_plane_funcs
,
13241 intel_primary_formats
, num_formats
,
13243 DRM_PLANE_TYPE_PRIMARY
,
13244 "primary %c", pipe_name(pipe
));
13246 ret
= drm_universal_plane_init(&dev_priv
->drm
, &primary
->base
,
13247 0, &intel_plane_funcs
,
13248 intel_primary_formats
, num_formats
,
13250 DRM_PLANE_TYPE_PRIMARY
,
13251 "plane %c", plane_name(primary
->plane
));
13255 if (INTEL_GEN(dev_priv
) >= 9) {
13256 supported_rotations
=
13257 DRM_MODE_ROTATE_0
| DRM_MODE_ROTATE_90
|
13258 DRM_MODE_ROTATE_180
| DRM_MODE_ROTATE_270
;
13259 } else if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_B
) {
13260 supported_rotations
=
13261 DRM_MODE_ROTATE_0
| DRM_MODE_ROTATE_180
|
13262 DRM_MODE_REFLECT_X
;
13263 } else if (INTEL_GEN(dev_priv
) >= 4) {
13264 supported_rotations
=
13265 DRM_MODE_ROTATE_0
| DRM_MODE_ROTATE_180
;
13267 supported_rotations
= DRM_MODE_ROTATE_0
;
13270 if (INTEL_GEN(dev_priv
) >= 4)
13271 drm_plane_create_rotation_property(&primary
->base
,
13273 supported_rotations
);
13275 drm_plane_helper_add(&primary
->base
, &intel_plane_helper_funcs
);
13283 return ERR_PTR(ret
);
13286 static struct intel_plane
*
13287 intel_cursor_plane_create(struct drm_i915_private
*dev_priv
,
13290 struct intel_plane
*cursor
= NULL
;
13291 struct intel_plane_state
*state
= NULL
;
13294 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
13300 state
= intel_create_plane_state(&cursor
->base
);
13306 cursor
->base
.state
= &state
->base
;
13308 cursor
->can_scale
= false;
13309 cursor
->max_downscale
= 1;
13310 cursor
->pipe
= pipe
;
13311 cursor
->plane
= pipe
;
13312 cursor
->id
= PLANE_CURSOR
;
13313 cursor
->frontbuffer_bit
= INTEL_FRONTBUFFER_CURSOR(pipe
);
13315 if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
)) {
13316 cursor
->update_plane
= i845_update_cursor
;
13317 cursor
->disable_plane
= i845_disable_cursor
;
13318 cursor
->check_plane
= i845_check_cursor
;
13320 cursor
->update_plane
= i9xx_update_cursor
;
13321 cursor
->disable_plane
= i9xx_disable_cursor
;
13322 cursor
->check_plane
= i9xx_check_cursor
;
13325 cursor
->cursor
.base
= ~0;
13326 cursor
->cursor
.cntl
= ~0;
13328 if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
) || HAS_CUR_FBC(dev_priv
))
13329 cursor
->cursor
.size
= ~0;
13331 ret
= drm_universal_plane_init(&dev_priv
->drm
, &cursor
->base
,
13332 0, &intel_cursor_plane_funcs
,
13333 intel_cursor_formats
,
13334 ARRAY_SIZE(intel_cursor_formats
),
13335 cursor_format_modifiers
,
13336 DRM_PLANE_TYPE_CURSOR
,
13337 "cursor %c", pipe_name(pipe
));
13341 if (INTEL_GEN(dev_priv
) >= 4)
13342 drm_plane_create_rotation_property(&cursor
->base
,
13344 DRM_MODE_ROTATE_0
|
13345 DRM_MODE_ROTATE_180
);
13347 if (INTEL_GEN(dev_priv
) >= 9)
13348 state
->scaler_id
= -1;
13350 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
13358 return ERR_PTR(ret
);
13361 static void intel_crtc_init_scalers(struct intel_crtc
*crtc
,
13362 struct intel_crtc_state
*crtc_state
)
13364 struct intel_crtc_scaler_state
*scaler_state
=
13365 &crtc_state
->scaler_state
;
13366 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
13369 crtc
->num_scalers
= dev_priv
->info
.num_scalers
[crtc
->pipe
];
13370 if (!crtc
->num_scalers
)
13373 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
13374 struct intel_scaler
*scaler
= &scaler_state
->scalers
[i
];
13376 scaler
->in_use
= 0;
13377 scaler
->mode
= PS_SCALER_MODE_DYN
;
13380 scaler_state
->scaler_id
= -1;
13383 static int intel_crtc_init(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
13385 struct intel_crtc
*intel_crtc
;
13386 struct intel_crtc_state
*crtc_state
= NULL
;
13387 struct intel_plane
*primary
= NULL
;
13388 struct intel_plane
*cursor
= NULL
;
13391 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
13395 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
13400 intel_crtc
->config
= crtc_state
;
13401 intel_crtc
->base
.state
= &crtc_state
->base
;
13402 crtc_state
->base
.crtc
= &intel_crtc
->base
;
13404 primary
= intel_primary_plane_create(dev_priv
, pipe
);
13405 if (IS_ERR(primary
)) {
13406 ret
= PTR_ERR(primary
);
13409 intel_crtc
->plane_ids_mask
|= BIT(primary
->id
);
13411 for_each_sprite(dev_priv
, pipe
, sprite
) {
13412 struct intel_plane
*plane
;
13414 plane
= intel_sprite_plane_create(dev_priv
, pipe
, sprite
);
13415 if (IS_ERR(plane
)) {
13416 ret
= PTR_ERR(plane
);
13419 intel_crtc
->plane_ids_mask
|= BIT(plane
->id
);
13422 cursor
= intel_cursor_plane_create(dev_priv
, pipe
);
13423 if (IS_ERR(cursor
)) {
13424 ret
= PTR_ERR(cursor
);
13427 intel_crtc
->plane_ids_mask
|= BIT(cursor
->id
);
13429 ret
= drm_crtc_init_with_planes(&dev_priv
->drm
, &intel_crtc
->base
,
13430 &primary
->base
, &cursor
->base
,
13432 "pipe %c", pipe_name(pipe
));
13436 intel_crtc
->pipe
= pipe
;
13437 intel_crtc
->plane
= primary
->plane
;
13439 /* initialize shared scalers */
13440 intel_crtc_init_scalers(intel_crtc
, crtc_state
);
13442 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
13443 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
13444 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = intel_crtc
;
13445 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = intel_crtc
;
13447 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
13449 intel_color_init(&intel_crtc
->base
);
13451 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
13457 * drm_mode_config_cleanup() will free up any
13458 * crtcs/planes already initialized.
13466 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
13468 struct drm_device
*dev
= connector
->base
.dev
;
13470 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
13472 if (!connector
->base
.state
->crtc
)
13473 return INVALID_PIPE
;
13475 return to_intel_crtc(connector
->base
.state
->crtc
)->pipe
;
13478 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
13479 struct drm_file
*file
)
13481 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
13482 struct drm_crtc
*drmmode_crtc
;
13483 struct intel_crtc
*crtc
;
13485 drmmode_crtc
= drm_crtc_find(dev
, file
, pipe_from_crtc_id
->crtc_id
);
13489 crtc
= to_intel_crtc(drmmode_crtc
);
13490 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
13495 static int intel_encoder_clones(struct intel_encoder
*encoder
)
13497 struct drm_device
*dev
= encoder
->base
.dev
;
13498 struct intel_encoder
*source_encoder
;
13499 int index_mask
= 0;
13502 for_each_intel_encoder(dev
, source_encoder
) {
13503 if (encoders_cloneable(encoder
, source_encoder
))
13504 index_mask
|= (1 << entry
);
13512 static bool has_edp_a(struct drm_i915_private
*dev_priv
)
13514 if (!IS_MOBILE(dev_priv
))
13517 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
13520 if (IS_GEN5(dev_priv
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
13526 static bool intel_crt_present(struct drm_i915_private
*dev_priv
)
13528 if (INTEL_GEN(dev_priv
) >= 9)
13531 if (IS_HSW_ULT(dev_priv
) || IS_BDW_ULT(dev_priv
))
13534 if (IS_CHERRYVIEW(dev_priv
))
13537 if (HAS_PCH_LPT_H(dev_priv
) &&
13538 I915_READ(SFUSE_STRAP
) & SFUSE_STRAP_CRT_DISABLED
)
13541 /* DDI E can't be used if DDI A requires 4 lanes */
13542 if (HAS_DDI(dev_priv
) && I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_A_4_LANES
)
13545 if (!dev_priv
->vbt
.int_crt_support
)
13551 void intel_pps_unlock_regs_wa(struct drm_i915_private
*dev_priv
)
13556 if (HAS_DDI(dev_priv
))
13559 * This w/a is needed at least on CPT/PPT, but to be sure apply it
13560 * everywhere where registers can be write protected.
13562 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
13567 for (pps_idx
= 0; pps_idx
< pps_num
; pps_idx
++) {
13568 u32 val
= I915_READ(PP_CONTROL(pps_idx
));
13570 val
= (val
& ~PANEL_UNLOCK_MASK
) | PANEL_UNLOCK_REGS
;
13571 I915_WRITE(PP_CONTROL(pps_idx
), val
);
13575 static void intel_pps_init(struct drm_i915_private
*dev_priv
)
13577 if (HAS_PCH_SPLIT(dev_priv
) || IS_GEN9_LP(dev_priv
))
13578 dev_priv
->pps_mmio_base
= PCH_PPS_BASE
;
13579 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
13580 dev_priv
->pps_mmio_base
= VLV_PPS_BASE
;
13582 dev_priv
->pps_mmio_base
= PPS_BASE
;
13584 intel_pps_unlock_regs_wa(dev_priv
);
13587 static void intel_setup_outputs(struct drm_i915_private
*dev_priv
)
13589 struct intel_encoder
*encoder
;
13590 bool dpd_is_edp
= false;
13592 intel_pps_init(dev_priv
);
13595 * intel_edp_init_connector() depends on this completing first, to
13596 * prevent the registeration of both eDP and LVDS and the incorrect
13597 * sharing of the PPS.
13599 intel_lvds_init(dev_priv
);
13601 if (intel_crt_present(dev_priv
))
13602 intel_crt_init(dev_priv
);
13604 if (IS_GEN9_LP(dev_priv
)) {
13606 * FIXME: Broxton doesn't support port detection via the
13607 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13608 * detect the ports.
13610 intel_ddi_init(dev_priv
, PORT_A
);
13611 intel_ddi_init(dev_priv
, PORT_B
);
13612 intel_ddi_init(dev_priv
, PORT_C
);
13614 intel_dsi_init(dev_priv
);
13615 } else if (HAS_DDI(dev_priv
)) {
13619 * Haswell uses DDI functions to detect digital outputs.
13620 * On SKL pre-D0 the strap isn't connected, so we assume
13623 found
= I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_INIT_DISPLAY_DETECTED
;
13624 /* WaIgnoreDDIAStrap: skl */
13625 if (found
|| IS_GEN9_BC(dev_priv
))
13626 intel_ddi_init(dev_priv
, PORT_A
);
13628 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13630 found
= I915_READ(SFUSE_STRAP
);
13632 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
13633 intel_ddi_init(dev_priv
, PORT_B
);
13634 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
13635 intel_ddi_init(dev_priv
, PORT_C
);
13636 if (found
& SFUSE_STRAP_DDID_DETECTED
)
13637 intel_ddi_init(dev_priv
, PORT_D
);
13639 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13641 if (IS_GEN9_BC(dev_priv
) &&
13642 (dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_dp
||
13643 dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_dvi
||
13644 dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_hdmi
))
13645 intel_ddi_init(dev_priv
, PORT_E
);
13647 } else if (HAS_PCH_SPLIT(dev_priv
)) {
13649 dpd_is_edp
= intel_dp_is_port_edp(dev_priv
, PORT_D
);
13651 if (has_edp_a(dev_priv
))
13652 intel_dp_init(dev_priv
, DP_A
, PORT_A
);
13654 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
13655 /* PCH SDVOB multiplex with HDMIB */
13656 found
= intel_sdvo_init(dev_priv
, PCH_SDVOB
, PORT_B
);
13658 intel_hdmi_init(dev_priv
, PCH_HDMIB
, PORT_B
);
13659 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
13660 intel_dp_init(dev_priv
, PCH_DP_B
, PORT_B
);
13663 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
13664 intel_hdmi_init(dev_priv
, PCH_HDMIC
, PORT_C
);
13666 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
13667 intel_hdmi_init(dev_priv
, PCH_HDMID
, PORT_D
);
13669 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
13670 intel_dp_init(dev_priv
, PCH_DP_C
, PORT_C
);
13672 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
13673 intel_dp_init(dev_priv
, PCH_DP_D
, PORT_D
);
13674 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
13675 bool has_edp
, has_port
;
13678 * The DP_DETECTED bit is the latched state of the DDC
13679 * SDA pin at boot. However since eDP doesn't require DDC
13680 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13681 * eDP ports may have been muxed to an alternate function.
13682 * Thus we can't rely on the DP_DETECTED bit alone to detect
13683 * eDP ports. Consult the VBT as well as DP_DETECTED to
13684 * detect eDP ports.
13686 * Sadly the straps seem to be missing sometimes even for HDMI
13687 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
13688 * and VBT for the presence of the port. Additionally we can't
13689 * trust the port type the VBT declares as we've seen at least
13690 * HDMI ports that the VBT claim are DP or eDP.
13692 has_edp
= intel_dp_is_port_edp(dev_priv
, PORT_B
);
13693 has_port
= intel_bios_is_port_present(dev_priv
, PORT_B
);
13694 if (I915_READ(VLV_DP_B
) & DP_DETECTED
|| has_port
)
13695 has_edp
&= intel_dp_init(dev_priv
, VLV_DP_B
, PORT_B
);
13696 if ((I915_READ(VLV_HDMIB
) & SDVO_DETECTED
|| has_port
) && !has_edp
)
13697 intel_hdmi_init(dev_priv
, VLV_HDMIB
, PORT_B
);
13699 has_edp
= intel_dp_is_port_edp(dev_priv
, PORT_C
);
13700 has_port
= intel_bios_is_port_present(dev_priv
, PORT_C
);
13701 if (I915_READ(VLV_DP_C
) & DP_DETECTED
|| has_port
)
13702 has_edp
&= intel_dp_init(dev_priv
, VLV_DP_C
, PORT_C
);
13703 if ((I915_READ(VLV_HDMIC
) & SDVO_DETECTED
|| has_port
) && !has_edp
)
13704 intel_hdmi_init(dev_priv
, VLV_HDMIC
, PORT_C
);
13706 if (IS_CHERRYVIEW(dev_priv
)) {
13708 * eDP not supported on port D,
13709 * so no need to worry about it
13711 has_port
= intel_bios_is_port_present(dev_priv
, PORT_D
);
13712 if (I915_READ(CHV_DP_D
) & DP_DETECTED
|| has_port
)
13713 intel_dp_init(dev_priv
, CHV_DP_D
, PORT_D
);
13714 if (I915_READ(CHV_HDMID
) & SDVO_DETECTED
|| has_port
)
13715 intel_hdmi_init(dev_priv
, CHV_HDMID
, PORT_D
);
13718 intel_dsi_init(dev_priv
);
13719 } else if (!IS_GEN2(dev_priv
) && !IS_PINEVIEW(dev_priv
)) {
13720 bool found
= false;
13722 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
13723 DRM_DEBUG_KMS("probing SDVOB\n");
13724 found
= intel_sdvo_init(dev_priv
, GEN3_SDVOB
, PORT_B
);
13725 if (!found
&& IS_G4X(dev_priv
)) {
13726 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13727 intel_hdmi_init(dev_priv
, GEN4_HDMIB
, PORT_B
);
13730 if (!found
&& IS_G4X(dev_priv
))
13731 intel_dp_init(dev_priv
, DP_B
, PORT_B
);
13734 /* Before G4X SDVOC doesn't have its own detect register */
13736 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
13737 DRM_DEBUG_KMS("probing SDVOC\n");
13738 found
= intel_sdvo_init(dev_priv
, GEN3_SDVOC
, PORT_C
);
13741 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
13743 if (IS_G4X(dev_priv
)) {
13744 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13745 intel_hdmi_init(dev_priv
, GEN4_HDMIC
, PORT_C
);
13747 if (IS_G4X(dev_priv
))
13748 intel_dp_init(dev_priv
, DP_C
, PORT_C
);
13751 if (IS_G4X(dev_priv
) && (I915_READ(DP_D
) & DP_DETECTED
))
13752 intel_dp_init(dev_priv
, DP_D
, PORT_D
);
13753 } else if (IS_GEN2(dev_priv
))
13754 intel_dvo_init(dev_priv
);
13756 if (SUPPORTS_TV(dev_priv
))
13757 intel_tv_init(dev_priv
);
13759 intel_psr_init(dev_priv
);
13761 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
13762 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
13763 encoder
->base
.possible_clones
=
13764 intel_encoder_clones(encoder
);
13767 intel_init_pch_refclk(dev_priv
);
13769 drm_helper_move_panel_connectors_to_head(&dev_priv
->drm
);
13772 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
13774 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
13776 drm_framebuffer_cleanup(fb
);
13778 i915_gem_object_lock(intel_fb
->obj
);
13779 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
13780 i915_gem_object_unlock(intel_fb
->obj
);
13782 i915_gem_object_put(intel_fb
->obj
);
13787 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
13788 struct drm_file
*file
,
13789 unsigned int *handle
)
13791 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
13792 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
13794 if (obj
->userptr
.mm
) {
13795 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
13799 return drm_gem_handle_create(file
, &obj
->base
, handle
);
13802 static int intel_user_framebuffer_dirty(struct drm_framebuffer
*fb
,
13803 struct drm_file
*file
,
13804 unsigned flags
, unsigned color
,
13805 struct drm_clip_rect
*clips
,
13806 unsigned num_clips
)
13808 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13810 i915_gem_object_flush_if_display(obj
);
13811 intel_fb_obj_flush(obj
, ORIGIN_DIRTYFB
);
13816 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
13817 .destroy
= intel_user_framebuffer_destroy
,
13818 .create_handle
= intel_user_framebuffer_create_handle
,
13819 .dirty
= intel_user_framebuffer_dirty
,
13823 u32
intel_fb_pitch_limit(struct drm_i915_private
*dev_priv
,
13824 uint64_t fb_modifier
, uint32_t pixel_format
)
13826 u32 gen
= INTEL_GEN(dev_priv
);
13829 int cpp
= drm_format_plane_cpp(pixel_format
, 0);
13831 /* "The stride in bytes must not exceed the of the size of 8K
13832 * pixels and 32K bytes."
13834 return min(8192 * cpp
, 32768);
13835 } else if (gen
>= 5 && !HAS_GMCH_DISPLAY(dev_priv
)) {
13837 } else if (gen
>= 4) {
13838 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
13842 } else if (gen
>= 3) {
13843 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
13848 /* XXX DSPC is limited to 4k tiled */
13853 static int intel_framebuffer_init(struct intel_framebuffer
*intel_fb
,
13854 struct drm_i915_gem_object
*obj
,
13855 struct drm_mode_fb_cmd2
*mode_cmd
)
13857 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
13858 struct drm_framebuffer
*fb
= &intel_fb
->base
;
13859 struct drm_format_name_buf format_name
;
13861 unsigned int tiling
, stride
;
13865 i915_gem_object_lock(obj
);
13866 obj
->framebuffer_references
++;
13867 tiling
= i915_gem_object_get_tiling(obj
);
13868 stride
= i915_gem_object_get_stride(obj
);
13869 i915_gem_object_unlock(obj
);
13871 if (mode_cmd
->flags
& DRM_MODE_FB_MODIFIERS
) {
13873 * If there's a fence, enforce that
13874 * the fb modifier and tiling mode match.
13876 if (tiling
!= I915_TILING_NONE
&&
13877 tiling
!= intel_fb_modifier_to_tiling(mode_cmd
->modifier
[0])) {
13878 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
13882 if (tiling
== I915_TILING_X
) {
13883 mode_cmd
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
13884 } else if (tiling
== I915_TILING_Y
) {
13885 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
13890 /* Passed in modifier sanity checking. */
13891 switch (mode_cmd
->modifier
[0]) {
13892 case I915_FORMAT_MOD_Y_TILED_CCS
:
13893 case I915_FORMAT_MOD_Yf_TILED_CCS
:
13894 switch (mode_cmd
->pixel_format
) {
13895 case DRM_FORMAT_XBGR8888
:
13896 case DRM_FORMAT_ABGR8888
:
13897 case DRM_FORMAT_XRGB8888
:
13898 case DRM_FORMAT_ARGB8888
:
13901 DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n");
13905 case I915_FORMAT_MOD_Y_TILED
:
13906 case I915_FORMAT_MOD_Yf_TILED
:
13907 if (INTEL_GEN(dev_priv
) < 9) {
13908 DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
13909 mode_cmd
->modifier
[0]);
13912 case DRM_FORMAT_MOD_LINEAR
:
13913 case I915_FORMAT_MOD_X_TILED
:
13916 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
13917 mode_cmd
->modifier
[0]);
13922 * gen2/3 display engine uses the fence if present,
13923 * so the tiling mode must match the fb modifier exactly.
13925 if (INTEL_INFO(dev_priv
)->gen
< 4 &&
13926 tiling
!= intel_fb_modifier_to_tiling(mode_cmd
->modifier
[0])) {
13927 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
13931 pitch_limit
= intel_fb_pitch_limit(dev_priv
, mode_cmd
->modifier
[0],
13932 mode_cmd
->pixel_format
);
13933 if (mode_cmd
->pitches
[0] > pitch_limit
) {
13934 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
13935 mode_cmd
->modifier
[0] != DRM_FORMAT_MOD_LINEAR
?
13936 "tiled" : "linear",
13937 mode_cmd
->pitches
[0], pitch_limit
);
13942 * If there's a fence, enforce that
13943 * the fb pitch and fence stride match.
13945 if (tiling
!= I915_TILING_NONE
&& mode_cmd
->pitches
[0] != stride
) {
13946 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
13947 mode_cmd
->pitches
[0], stride
);
13951 /* Reject formats not supported by any plane early. */
13952 switch (mode_cmd
->pixel_format
) {
13953 case DRM_FORMAT_C8
:
13954 case DRM_FORMAT_RGB565
:
13955 case DRM_FORMAT_XRGB8888
:
13956 case DRM_FORMAT_ARGB8888
:
13958 case DRM_FORMAT_XRGB1555
:
13959 if (INTEL_GEN(dev_priv
) > 3) {
13960 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13961 drm_get_format_name(mode_cmd
->pixel_format
, &format_name
));
13965 case DRM_FORMAT_ABGR8888
:
13966 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
) &&
13967 INTEL_GEN(dev_priv
) < 9) {
13968 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13969 drm_get_format_name(mode_cmd
->pixel_format
, &format_name
));
13973 case DRM_FORMAT_XBGR8888
:
13974 case DRM_FORMAT_XRGB2101010
:
13975 case DRM_FORMAT_XBGR2101010
:
13976 if (INTEL_GEN(dev_priv
) < 4) {
13977 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13978 drm_get_format_name(mode_cmd
->pixel_format
, &format_name
));
13982 case DRM_FORMAT_ABGR2101010
:
13983 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
)) {
13984 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13985 drm_get_format_name(mode_cmd
->pixel_format
, &format_name
));
13989 case DRM_FORMAT_YUYV
:
13990 case DRM_FORMAT_UYVY
:
13991 case DRM_FORMAT_YVYU
:
13992 case DRM_FORMAT_VYUY
:
13993 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
)) {
13994 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13995 drm_get_format_name(mode_cmd
->pixel_format
, &format_name
));
14000 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14001 drm_get_format_name(mode_cmd
->pixel_format
, &format_name
));
14005 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14006 if (mode_cmd
->offsets
[0] != 0)
14009 drm_helper_mode_fill_fb_struct(&dev_priv
->drm
, fb
, mode_cmd
);
14011 for (i
= 0; i
< fb
->format
->num_planes
; i
++) {
14012 u32 stride_alignment
;
14014 if (mode_cmd
->handles
[i
] != mode_cmd
->handles
[0]) {
14015 DRM_DEBUG_KMS("bad plane %d handle\n", i
);
14019 stride_alignment
= intel_fb_stride_alignment(fb
, i
);
14022 * Display WA #0531: skl,bxt,kbl,glk
14024 * Render decompression and plane width > 3840
14025 * combined with horizontal panning requires the
14026 * plane stride to be a multiple of 4. We'll just
14027 * require the entire fb to accommodate that to avoid
14028 * potential runtime errors at plane configuration time.
14030 if (IS_GEN9(dev_priv
) && i
== 0 && fb
->width
> 3840 &&
14031 (fb
->modifier
== I915_FORMAT_MOD_Y_TILED_CCS
||
14032 fb
->modifier
== I915_FORMAT_MOD_Yf_TILED_CCS
))
14033 stride_alignment
*= 4;
14035 if (fb
->pitches
[i
] & (stride_alignment
- 1)) {
14036 DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
14037 i
, fb
->pitches
[i
], stride_alignment
);
14042 intel_fb
->obj
= obj
;
14044 ret
= intel_fill_fb_info(dev_priv
, fb
);
14048 ret
= drm_framebuffer_init(&dev_priv
->drm
, fb
, &intel_fb_funcs
);
14050 DRM_ERROR("framebuffer init failed %d\n", ret
);
14057 i915_gem_object_lock(obj
);
14058 obj
->framebuffer_references
--;
14059 i915_gem_object_unlock(obj
);
14063 static struct drm_framebuffer
*
14064 intel_user_framebuffer_create(struct drm_device
*dev
,
14065 struct drm_file
*filp
,
14066 const struct drm_mode_fb_cmd2
*user_mode_cmd
)
14068 struct drm_framebuffer
*fb
;
14069 struct drm_i915_gem_object
*obj
;
14070 struct drm_mode_fb_cmd2 mode_cmd
= *user_mode_cmd
;
14072 obj
= i915_gem_object_lookup(filp
, mode_cmd
.handles
[0]);
14074 return ERR_PTR(-ENOENT
);
14076 fb
= intel_framebuffer_create(obj
, &mode_cmd
);
14078 i915_gem_object_put(obj
);
14083 static void intel_atomic_state_free(struct drm_atomic_state
*state
)
14085 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
14087 drm_atomic_state_default_release(state
);
14089 i915_sw_fence_fini(&intel_state
->commit_ready
);
14094 static const struct drm_mode_config_funcs intel_mode_funcs
= {
14095 .fb_create
= intel_user_framebuffer_create
,
14096 .get_format_info
= intel_get_format_info
,
14097 .output_poll_changed
= intel_fbdev_output_poll_changed
,
14098 .atomic_check
= intel_atomic_check
,
14099 .atomic_commit
= intel_atomic_commit
,
14100 .atomic_state_alloc
= intel_atomic_state_alloc
,
14101 .atomic_state_clear
= intel_atomic_state_clear
,
14102 .atomic_state_free
= intel_atomic_state_free
,
14106 * intel_init_display_hooks - initialize the display modesetting hooks
14107 * @dev_priv: device private
14109 void intel_init_display_hooks(struct drm_i915_private
*dev_priv
)
14111 intel_init_cdclk_hooks(dev_priv
);
14113 if (INTEL_INFO(dev_priv
)->gen
>= 9) {
14114 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
14115 dev_priv
->display
.get_initial_plane_config
=
14116 skylake_get_initial_plane_config
;
14117 dev_priv
->display
.crtc_compute_clock
=
14118 haswell_crtc_compute_clock
;
14119 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
14120 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
14121 } else if (HAS_DDI(dev_priv
)) {
14122 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
14123 dev_priv
->display
.get_initial_plane_config
=
14124 ironlake_get_initial_plane_config
;
14125 dev_priv
->display
.crtc_compute_clock
=
14126 haswell_crtc_compute_clock
;
14127 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
14128 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
14129 } else if (HAS_PCH_SPLIT(dev_priv
)) {
14130 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
14131 dev_priv
->display
.get_initial_plane_config
=
14132 ironlake_get_initial_plane_config
;
14133 dev_priv
->display
.crtc_compute_clock
=
14134 ironlake_crtc_compute_clock
;
14135 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
14136 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
14137 } else if (IS_CHERRYVIEW(dev_priv
)) {
14138 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14139 dev_priv
->display
.get_initial_plane_config
=
14140 i9xx_get_initial_plane_config
;
14141 dev_priv
->display
.crtc_compute_clock
= chv_crtc_compute_clock
;
14142 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
14143 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14144 } else if (IS_VALLEYVIEW(dev_priv
)) {
14145 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14146 dev_priv
->display
.get_initial_plane_config
=
14147 i9xx_get_initial_plane_config
;
14148 dev_priv
->display
.crtc_compute_clock
= vlv_crtc_compute_clock
;
14149 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
14150 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14151 } else if (IS_G4X(dev_priv
)) {
14152 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14153 dev_priv
->display
.get_initial_plane_config
=
14154 i9xx_get_initial_plane_config
;
14155 dev_priv
->display
.crtc_compute_clock
= g4x_crtc_compute_clock
;
14156 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
14157 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14158 } else if (IS_PINEVIEW(dev_priv
)) {
14159 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14160 dev_priv
->display
.get_initial_plane_config
=
14161 i9xx_get_initial_plane_config
;
14162 dev_priv
->display
.crtc_compute_clock
= pnv_crtc_compute_clock
;
14163 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
14164 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14165 } else if (!IS_GEN2(dev_priv
)) {
14166 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14167 dev_priv
->display
.get_initial_plane_config
=
14168 i9xx_get_initial_plane_config
;
14169 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
14170 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
14171 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14173 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14174 dev_priv
->display
.get_initial_plane_config
=
14175 i9xx_get_initial_plane_config
;
14176 dev_priv
->display
.crtc_compute_clock
= i8xx_crtc_compute_clock
;
14177 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
14178 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14181 if (IS_GEN5(dev_priv
)) {
14182 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
14183 } else if (IS_GEN6(dev_priv
)) {
14184 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
14185 } else if (IS_IVYBRIDGE(dev_priv
)) {
14186 /* FIXME: detect B0+ stepping and use auto training */
14187 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
14188 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
14189 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
14192 if (INTEL_GEN(dev_priv
) >= 9)
14193 dev_priv
->display
.update_crtcs
= skl_update_crtcs
;
14195 dev_priv
->display
.update_crtcs
= intel_update_crtcs
;
14199 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14201 static void quirk_ssc_force_disable(struct drm_device
*dev
)
14203 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14204 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
14205 DRM_INFO("applying lvds SSC disable quirk\n");
14209 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14212 static void quirk_invert_brightness(struct drm_device
*dev
)
14214 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14215 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
14216 DRM_INFO("applying inverted panel brightness quirk\n");
14219 /* Some VBT's incorrectly indicate no backlight is present */
14220 static void quirk_backlight_present(struct drm_device
*dev
)
14222 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14223 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
14224 DRM_INFO("applying backlight present quirk\n");
14227 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
14228 * which is 300 ms greater than eDP spec T12 min.
14230 static void quirk_increase_t12_delay(struct drm_device
*dev
)
14232 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14234 dev_priv
->quirks
|= QUIRK_INCREASE_T12_DELAY
;
14235 DRM_INFO("Applying T12 delay quirk\n");
14238 struct intel_quirk
{
14240 int subsystem_vendor
;
14241 int subsystem_device
;
14242 void (*hook
)(struct drm_device
*dev
);
14245 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14246 struct intel_dmi_quirk
{
14247 void (*hook
)(struct drm_device
*dev
);
14248 const struct dmi_system_id (*dmi_id_list
)[];
14251 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
14253 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
14257 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
14259 .dmi_id_list
= &(const struct dmi_system_id
[]) {
14261 .callback
= intel_dmi_reverse_brightness
,
14262 .ident
= "NCR Corporation",
14263 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
14264 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
14267 { } /* terminating entry */
14269 .hook
= quirk_invert_brightness
,
14273 static struct intel_quirk intel_quirks
[] = {
14274 /* Lenovo U160 cannot use SSC on LVDS */
14275 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
14277 /* Sony Vaio Y cannot use SSC on LVDS */
14278 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
14280 /* Acer Aspire 5734Z must invert backlight brightness */
14281 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
14283 /* Acer/eMachines G725 */
14284 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
14286 /* Acer/eMachines e725 */
14287 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
14289 /* Acer/Packard Bell NCL20 */
14290 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
14292 /* Acer Aspire 4736Z */
14293 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
14295 /* Acer Aspire 5336 */
14296 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
14298 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14299 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
14301 /* Acer C720 Chromebook (Core i3 4005U) */
14302 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
14304 /* Apple Macbook 2,1 (Core 2 T7400) */
14305 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present
},
14307 /* Apple Macbook 4,1 */
14308 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present
},
14310 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14311 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
14313 /* HP Chromebook 14 (Celeron 2955U) */
14314 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
14316 /* Dell Chromebook 11 */
14317 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present
},
14319 /* Dell Chromebook 11 (2015 version) */
14320 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present
},
14322 /* Toshiba Satellite P50-C-18C */
14323 { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay
},
14326 static void intel_init_quirks(struct drm_device
*dev
)
14328 struct pci_dev
*d
= dev
->pdev
;
14331 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
14332 struct intel_quirk
*q
= &intel_quirks
[i
];
14334 if (d
->device
== q
->device
&&
14335 (d
->subsystem_vendor
== q
->subsystem_vendor
||
14336 q
->subsystem_vendor
== PCI_ANY_ID
) &&
14337 (d
->subsystem_device
== q
->subsystem_device
||
14338 q
->subsystem_device
== PCI_ANY_ID
))
14341 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
14342 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
14343 intel_dmi_quirks
[i
].hook(dev
);
14347 /* Disable the VGA plane that we never use */
14348 static void i915_disable_vga(struct drm_i915_private
*dev_priv
)
14350 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
14352 i915_reg_t vga_reg
= i915_vgacntrl_reg(dev_priv
);
14354 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14355 vga_get_uninterruptible(pdev
, VGA_RSRC_LEGACY_IO
);
14356 outb(SR01
, VGA_SR_INDEX
);
14357 sr1
= inb(VGA_SR_DATA
);
14358 outb(sr1
| 1<<5, VGA_SR_DATA
);
14359 vga_put(pdev
, VGA_RSRC_LEGACY_IO
);
14362 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
14363 POSTING_READ(vga_reg
);
14366 void intel_modeset_init_hw(struct drm_device
*dev
)
14368 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14370 intel_update_cdclk(dev_priv
);
14371 dev_priv
->cdclk
.logical
= dev_priv
->cdclk
.actual
= dev_priv
->cdclk
.hw
;
14375 * Calculate what we think the watermarks should be for the state we've read
14376 * out of the hardware and then immediately program those watermarks so that
14377 * we ensure the hardware settings match our internal state.
14379 * We can calculate what we think WM's should be by creating a duplicate of the
14380 * current state (which was constructed during hardware readout) and running it
14381 * through the atomic check code to calculate new watermark values in the
14384 static void sanitize_watermarks(struct drm_device
*dev
)
14386 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14387 struct drm_atomic_state
*state
;
14388 struct intel_atomic_state
*intel_state
;
14389 struct drm_crtc
*crtc
;
14390 struct drm_crtc_state
*cstate
;
14391 struct drm_modeset_acquire_ctx ctx
;
14395 /* Only supported on platforms that use atomic watermark design */
14396 if (!dev_priv
->display
.optimize_watermarks
)
14400 * We need to hold connection_mutex before calling duplicate_state so
14401 * that the connector loop is protected.
14403 drm_modeset_acquire_init(&ctx
, 0);
14405 ret
= drm_modeset_lock_all_ctx(dev
, &ctx
);
14406 if (ret
== -EDEADLK
) {
14407 drm_modeset_backoff(&ctx
);
14409 } else if (WARN_ON(ret
)) {
14413 state
= drm_atomic_helper_duplicate_state(dev
, &ctx
);
14414 if (WARN_ON(IS_ERR(state
)))
14417 intel_state
= to_intel_atomic_state(state
);
14420 * Hardware readout is the only time we don't want to calculate
14421 * intermediate watermarks (since we don't trust the current
14424 if (!HAS_GMCH_DISPLAY(dev_priv
))
14425 intel_state
->skip_intermediate_wm
= true;
14427 ret
= intel_atomic_check(dev
, state
);
14430 * If we fail here, it means that the hardware appears to be
14431 * programmed in a way that shouldn't be possible, given our
14432 * understanding of watermark requirements. This might mean a
14433 * mistake in the hardware readout code or a mistake in the
14434 * watermark calculations for a given platform. Raise a WARN
14435 * so that this is noticeable.
14437 * If this actually happens, we'll have to just leave the
14438 * BIOS-programmed watermarks untouched and hope for the best.
14440 WARN(true, "Could not determine valid watermarks for inherited state\n");
14444 /* Write calculated watermark values back */
14445 for_each_new_crtc_in_state(state
, crtc
, cstate
, i
) {
14446 struct intel_crtc_state
*cs
= to_intel_crtc_state(cstate
);
14448 cs
->wm
.need_postvbl_update
= true;
14449 dev_priv
->display
.optimize_watermarks(intel_state
, cs
);
14453 drm_atomic_state_put(state
);
14455 drm_modeset_drop_locks(&ctx
);
14456 drm_modeset_acquire_fini(&ctx
);
14459 int intel_modeset_init(struct drm_device
*dev
)
14461 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14462 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
14464 struct intel_crtc
*crtc
;
14466 drm_mode_config_init(dev
);
14468 dev
->mode_config
.min_width
= 0;
14469 dev
->mode_config
.min_height
= 0;
14471 dev
->mode_config
.preferred_depth
= 24;
14472 dev
->mode_config
.prefer_shadow
= 1;
14474 dev
->mode_config
.allow_fb_modifiers
= true;
14476 dev
->mode_config
.funcs
= &intel_mode_funcs
;
14478 init_llist_head(&dev_priv
->atomic_helper
.free_list
);
14479 INIT_WORK(&dev_priv
->atomic_helper
.free_work
,
14480 intel_atomic_helper_free_state_worker
);
14482 intel_init_quirks(dev
);
14484 intel_init_pm(dev_priv
);
14486 if (INTEL_INFO(dev_priv
)->num_pipes
== 0)
14490 * There may be no VBT; and if the BIOS enabled SSC we can
14491 * just keep using it to avoid unnecessary flicker. Whereas if the
14492 * BIOS isn't using it, don't assume it will work even if the VBT
14493 * indicates as much.
14495 if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)) {
14496 bool bios_lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
14499 if (dev_priv
->vbt
.lvds_use_ssc
!= bios_lvds_use_ssc
) {
14500 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14501 bios_lvds_use_ssc
? "en" : "dis",
14502 dev_priv
->vbt
.lvds_use_ssc
? "en" : "dis");
14503 dev_priv
->vbt
.lvds_use_ssc
= bios_lvds_use_ssc
;
14507 if (IS_GEN2(dev_priv
)) {
14508 dev
->mode_config
.max_width
= 2048;
14509 dev
->mode_config
.max_height
= 2048;
14510 } else if (IS_GEN3(dev_priv
)) {
14511 dev
->mode_config
.max_width
= 4096;
14512 dev
->mode_config
.max_height
= 4096;
14514 dev
->mode_config
.max_width
= 8192;
14515 dev
->mode_config
.max_height
= 8192;
14518 if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
)) {
14519 dev
->mode_config
.cursor_width
= IS_I845G(dev_priv
) ? 64 : 512;
14520 dev
->mode_config
.cursor_height
= 1023;
14521 } else if (IS_GEN2(dev_priv
)) {
14522 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
14523 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
14525 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
14526 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
14529 dev
->mode_config
.fb_base
= ggtt
->mappable_base
;
14531 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14532 INTEL_INFO(dev_priv
)->num_pipes
,
14533 INTEL_INFO(dev_priv
)->num_pipes
> 1 ? "s" : "");
14535 for_each_pipe(dev_priv
, pipe
) {
14538 ret
= intel_crtc_init(dev_priv
, pipe
);
14540 drm_mode_config_cleanup(dev
);
14545 intel_shared_dpll_init(dev
);
14547 intel_update_czclk(dev_priv
);
14548 intel_modeset_init_hw(dev
);
14550 if (dev_priv
->max_cdclk_freq
== 0)
14551 intel_update_max_cdclk(dev_priv
);
14553 /* Just disable it once at startup */
14554 i915_disable_vga(dev_priv
);
14555 intel_setup_outputs(dev_priv
);
14557 drm_modeset_lock_all(dev
);
14558 intel_modeset_setup_hw_state(dev
, dev
->mode_config
.acquire_ctx
);
14559 drm_modeset_unlock_all(dev
);
14561 for_each_intel_crtc(dev
, crtc
) {
14562 struct intel_initial_plane_config plane_config
= {};
14568 * Note that reserving the BIOS fb up front prevents us
14569 * from stuffing other stolen allocations like the ring
14570 * on top. This prevents some ugliness at boot time, and
14571 * can even allow for smooth boot transitions if the BIOS
14572 * fb is large enough for the active pipe configuration.
14574 dev_priv
->display
.get_initial_plane_config(crtc
,
14578 * If the fb is shared between multiple heads, we'll
14579 * just get the first one.
14581 intel_find_initial_plane_obj(crtc
, &plane_config
);
14585 * Make sure hardware watermarks really match the state we read out.
14586 * Note that we need to do this after reconstructing the BIOS fb's
14587 * since the watermark calculation done here will use pstate->fb.
14589 if (!HAS_GMCH_DISPLAY(dev_priv
))
14590 sanitize_watermarks(dev
);
14595 void i830_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
14597 /* 640x480@60Hz, ~25175 kHz */
14598 struct dpll clock
= {
14608 WARN_ON(i9xx_calc_dpll_params(48000, &clock
) != 25154);
14610 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
14611 pipe_name(pipe
), clock
.vco
, clock
.dot
);
14613 fp
= i9xx_dpll_compute_fp(&clock
);
14614 dpll
= (I915_READ(DPLL(pipe
)) & DPLL_DVO_2X_MODE
) |
14615 DPLL_VGA_MODE_DIS
|
14616 ((clock
.p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
) |
14617 PLL_P2_DIVIDE_BY_4
|
14618 PLL_REF_INPUT_DREFCLK
|
14621 I915_WRITE(FP0(pipe
), fp
);
14622 I915_WRITE(FP1(pipe
), fp
);
14624 I915_WRITE(HTOTAL(pipe
), (640 - 1) | ((800 - 1) << 16));
14625 I915_WRITE(HBLANK(pipe
), (640 - 1) | ((800 - 1) << 16));
14626 I915_WRITE(HSYNC(pipe
), (656 - 1) | ((752 - 1) << 16));
14627 I915_WRITE(VTOTAL(pipe
), (480 - 1) | ((525 - 1) << 16));
14628 I915_WRITE(VBLANK(pipe
), (480 - 1) | ((525 - 1) << 16));
14629 I915_WRITE(VSYNC(pipe
), (490 - 1) | ((492 - 1) << 16));
14630 I915_WRITE(PIPESRC(pipe
), ((640 - 1) << 16) | (480 - 1));
14633 * Apparently we need to have VGA mode enabled prior to changing
14634 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
14635 * dividers, even though the register value does change.
14637 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VGA_MODE_DIS
);
14638 I915_WRITE(DPLL(pipe
), dpll
);
14640 /* Wait for the clocks to stabilize. */
14641 POSTING_READ(DPLL(pipe
));
14644 /* The pixel multiplier can only be updated once the
14645 * DPLL is enabled and the clocks are stable.
14647 * So write it again.
14649 I915_WRITE(DPLL(pipe
), dpll
);
14651 /* We do this three times for luck */
14652 for (i
= 0; i
< 3 ; i
++) {
14653 I915_WRITE(DPLL(pipe
), dpll
);
14654 POSTING_READ(DPLL(pipe
));
14655 udelay(150); /* wait for warmup */
14658 I915_WRITE(PIPECONF(pipe
), PIPECONF_ENABLE
| PIPECONF_PROGRESSIVE
);
14659 POSTING_READ(PIPECONF(pipe
));
14662 void i830_disable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
14664 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
14666 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
14669 assert_plane_disabled(dev_priv
, PLANE_A
);
14670 assert_plane_disabled(dev_priv
, PLANE_B
);
14672 I915_WRITE(PIPECONF(pipe
), 0);
14673 POSTING_READ(PIPECONF(pipe
));
14675 intel_wait_for_pipe_scanline_stopped(crtc
);
14677 I915_WRITE(DPLL(pipe
), DPLL_VGA_MODE_DIS
);
14678 POSTING_READ(DPLL(pipe
));
14682 intel_check_plane_mapping(struct intel_crtc
*crtc
)
14684 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
14687 if (INTEL_INFO(dev_priv
)->num_pipes
== 1)
14690 val
= I915_READ(DSPCNTR(!crtc
->plane
));
14692 if ((val
& DISPLAY_PLANE_ENABLE
) &&
14693 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
14699 static bool intel_crtc_has_encoders(struct intel_crtc
*crtc
)
14701 struct drm_device
*dev
= crtc
->base
.dev
;
14702 struct intel_encoder
*encoder
;
14704 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
14710 static struct intel_connector
*intel_encoder_find_connector(struct intel_encoder
*encoder
)
14712 struct drm_device
*dev
= encoder
->base
.dev
;
14713 struct intel_connector
*connector
;
14715 for_each_connector_on_encoder(dev
, &encoder
->base
, connector
)
14721 static bool has_pch_trancoder(struct drm_i915_private
*dev_priv
,
14722 enum pipe pch_transcoder
)
14724 return HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
) ||
14725 (HAS_PCH_LPT_H(dev_priv
) && pch_transcoder
== PIPE_A
);
14728 static void intel_sanitize_crtc(struct intel_crtc
*crtc
,
14729 struct drm_modeset_acquire_ctx
*ctx
)
14731 struct drm_device
*dev
= crtc
->base
.dev
;
14732 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14733 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
14735 /* Clear any frame start delays used for debugging left by the BIOS */
14736 if (!transcoder_is_dsi(cpu_transcoder
)) {
14737 i915_reg_t reg
= PIPECONF(cpu_transcoder
);
14740 I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
14743 /* restore vblank interrupts to correct state */
14744 drm_crtc_vblank_reset(&crtc
->base
);
14745 if (crtc
->active
) {
14746 struct intel_plane
*plane
;
14748 drm_crtc_vblank_on(&crtc
->base
);
14750 /* Disable everything but the primary plane */
14751 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
14752 if (plane
->base
.type
== DRM_PLANE_TYPE_PRIMARY
)
14755 trace_intel_disable_plane(&plane
->base
, crtc
);
14756 plane
->disable_plane(plane
, crtc
);
14760 /* We need to sanitize the plane -> pipe mapping first because this will
14761 * disable the crtc (and hence change the state) if it is wrong. Note
14762 * that gen4+ has a fixed plane -> pipe mapping. */
14763 if (INTEL_GEN(dev_priv
) < 4 && !intel_check_plane_mapping(crtc
)) {
14766 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
14767 crtc
->base
.base
.id
, crtc
->base
.name
);
14769 /* Pipe has the wrong plane attached and the plane is active.
14770 * Temporarily change the plane mapping and disable everything
14772 plane
= crtc
->plane
;
14773 crtc
->base
.primary
->state
->visible
= true;
14774 crtc
->plane
= !plane
;
14775 intel_crtc_disable_noatomic(&crtc
->base
, ctx
);
14776 crtc
->plane
= plane
;
14779 /* Adjust the state of the output pipe according to whether we
14780 * have active connectors/encoders. */
14781 if (crtc
->active
&& !intel_crtc_has_encoders(crtc
))
14782 intel_crtc_disable_noatomic(&crtc
->base
, ctx
);
14784 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev_priv
)) {
14786 * We start out with underrun reporting disabled to avoid races.
14787 * For correct bookkeeping mark this on active crtcs.
14789 * Also on gmch platforms we dont have any hardware bits to
14790 * disable the underrun reporting. Which means we need to start
14791 * out with underrun reporting disabled also on inactive pipes,
14792 * since otherwise we'll complain about the garbage we read when
14793 * e.g. coming up after runtime pm.
14795 * No protection against concurrent access is required - at
14796 * worst a fifo underrun happens which also sets this to false.
14798 crtc
->cpu_fifo_underrun_disabled
= true;
14800 * We track the PCH trancoder underrun reporting state
14801 * within the crtc. With crtc for pipe A housing the underrun
14802 * reporting state for PCH transcoder A, crtc for pipe B housing
14803 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
14804 * and marking underrun reporting as disabled for the non-existing
14805 * PCH transcoders B and C would prevent enabling the south
14806 * error interrupt (see cpt_can_enable_serr_int()).
14808 if (has_pch_trancoder(dev_priv
, crtc
->pipe
))
14809 crtc
->pch_fifo_underrun_disabled
= true;
14813 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
14815 struct intel_connector
*connector
;
14817 /* We need to check both for a crtc link (meaning that the
14818 * encoder is active and trying to read from a pipe) and the
14819 * pipe itself being active. */
14820 bool has_active_crtc
= encoder
->base
.crtc
&&
14821 to_intel_crtc(encoder
->base
.crtc
)->active
;
14823 connector
= intel_encoder_find_connector(encoder
);
14824 if (connector
&& !has_active_crtc
) {
14825 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14826 encoder
->base
.base
.id
,
14827 encoder
->base
.name
);
14829 /* Connector is active, but has no active pipe. This is
14830 * fallout from our resume register restoring. Disable
14831 * the encoder manually again. */
14832 if (encoder
->base
.crtc
) {
14833 struct drm_crtc_state
*crtc_state
= encoder
->base
.crtc
->state
;
14835 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14836 encoder
->base
.base
.id
,
14837 encoder
->base
.name
);
14838 encoder
->disable(encoder
, to_intel_crtc_state(crtc_state
), connector
->base
.state
);
14839 if (encoder
->post_disable
)
14840 encoder
->post_disable(encoder
, to_intel_crtc_state(crtc_state
), connector
->base
.state
);
14842 encoder
->base
.crtc
= NULL
;
14844 /* Inconsistent output/port/pipe state happens presumably due to
14845 * a bug in one of the get_hw_state functions. Or someplace else
14846 * in our code, like the register restore mess on resume. Clamp
14847 * things to off as a safer default. */
14849 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
14850 connector
->base
.encoder
= NULL
;
14852 /* Enabled encoders without active connectors will be fixed in
14853 * the crtc fixup. */
14856 void i915_redisable_vga_power_on(struct drm_i915_private
*dev_priv
)
14858 i915_reg_t vga_reg
= i915_vgacntrl_reg(dev_priv
);
14860 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
14861 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14862 i915_disable_vga(dev_priv
);
14866 void i915_redisable_vga(struct drm_i915_private
*dev_priv
)
14868 /* This function can be called both from intel_modeset_setup_hw_state or
14869 * at a very early point in our resume sequence, where the power well
14870 * structures are not yet restored. Since this function is at a very
14871 * paranoid "someone might have enabled VGA while we were not looking"
14872 * level, just check if the power well is enabled instead of trying to
14873 * follow the "don't touch the power well if we don't need it" policy
14874 * the rest of the driver uses. */
14875 if (!intel_display_power_get_if_enabled(dev_priv
, POWER_DOMAIN_VGA
))
14878 i915_redisable_vga_power_on(dev_priv
);
14880 intel_display_power_put(dev_priv
, POWER_DOMAIN_VGA
);
14883 static bool primary_get_hw_state(struct intel_plane
*plane
)
14885 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
14887 return I915_READ(DSPCNTR(plane
->plane
)) & DISPLAY_PLANE_ENABLE
;
14890 /* FIXME read out full plane state for all planes */
14891 static void readout_plane_state(struct intel_crtc
*crtc
)
14893 struct intel_plane
*primary
= to_intel_plane(crtc
->base
.primary
);
14896 visible
= crtc
->active
&& primary_get_hw_state(primary
);
14898 intel_set_plane_visible(to_intel_crtc_state(crtc
->base
.state
),
14899 to_intel_plane_state(primary
->base
.state
),
14903 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
14905 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14907 struct intel_crtc
*crtc
;
14908 struct intel_encoder
*encoder
;
14909 struct intel_connector
*connector
;
14910 struct drm_connector_list_iter conn_iter
;
14913 dev_priv
->active_crtcs
= 0;
14915 for_each_intel_crtc(dev
, crtc
) {
14916 struct intel_crtc_state
*crtc_state
=
14917 to_intel_crtc_state(crtc
->base
.state
);
14919 __drm_atomic_helper_crtc_destroy_state(&crtc_state
->base
);
14920 memset(crtc_state
, 0, sizeof(*crtc_state
));
14921 crtc_state
->base
.crtc
= &crtc
->base
;
14923 crtc_state
->base
.active
= crtc_state
->base
.enable
=
14924 dev_priv
->display
.get_pipe_config(crtc
, crtc_state
);
14926 crtc
->base
.enabled
= crtc_state
->base
.enable
;
14927 crtc
->active
= crtc_state
->base
.active
;
14929 if (crtc_state
->base
.active
)
14930 dev_priv
->active_crtcs
|= 1 << crtc
->pipe
;
14932 readout_plane_state(crtc
);
14934 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
14935 crtc
->base
.base
.id
, crtc
->base
.name
,
14936 enableddisabled(crtc_state
->base
.active
));
14939 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
14940 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
14942 pll
->on
= pll
->funcs
.get_hw_state(dev_priv
, pll
,
14943 &pll
->state
.hw_state
);
14944 pll
->state
.crtc_mask
= 0;
14945 for_each_intel_crtc(dev
, crtc
) {
14946 struct intel_crtc_state
*crtc_state
=
14947 to_intel_crtc_state(crtc
->base
.state
);
14949 if (crtc_state
->base
.active
&&
14950 crtc_state
->shared_dpll
== pll
)
14951 pll
->state
.crtc_mask
|= 1 << crtc
->pipe
;
14953 pll
->active_mask
= pll
->state
.crtc_mask
;
14955 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14956 pll
->name
, pll
->state
.crtc_mask
, pll
->on
);
14959 for_each_intel_encoder(dev
, encoder
) {
14962 if (encoder
->get_hw_state(encoder
, &pipe
)) {
14963 struct intel_crtc_state
*crtc_state
;
14965 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
14966 crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
14968 encoder
->base
.crtc
= &crtc
->base
;
14969 crtc_state
->output_types
|= 1 << encoder
->type
;
14970 encoder
->get_config(encoder
, crtc_state
);
14972 encoder
->base
.crtc
= NULL
;
14975 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14976 encoder
->base
.base
.id
, encoder
->base
.name
,
14977 enableddisabled(encoder
->base
.crtc
),
14981 drm_connector_list_iter_begin(dev
, &conn_iter
);
14982 for_each_intel_connector_iter(connector
, &conn_iter
) {
14983 if (connector
->get_hw_state(connector
)) {
14984 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
14986 encoder
= connector
->encoder
;
14987 connector
->base
.encoder
= &encoder
->base
;
14989 if (encoder
->base
.crtc
&&
14990 encoder
->base
.crtc
->state
->active
) {
14992 * This has to be done during hardware readout
14993 * because anything calling .crtc_disable may
14994 * rely on the connector_mask being accurate.
14996 encoder
->base
.crtc
->state
->connector_mask
|=
14997 1 << drm_connector_index(&connector
->base
);
14998 encoder
->base
.crtc
->state
->encoder_mask
|=
14999 1 << drm_encoder_index(&encoder
->base
);
15003 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
15004 connector
->base
.encoder
= NULL
;
15006 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15007 connector
->base
.base
.id
, connector
->base
.name
,
15008 enableddisabled(connector
->base
.encoder
));
15010 drm_connector_list_iter_end(&conn_iter
);
15012 for_each_intel_crtc(dev
, crtc
) {
15013 struct intel_crtc_state
*crtc_state
=
15014 to_intel_crtc_state(crtc
->base
.state
);
15017 memset(&crtc
->base
.mode
, 0, sizeof(crtc
->base
.mode
));
15018 if (crtc_state
->base
.active
) {
15019 intel_mode_from_pipe_config(&crtc
->base
.mode
, crtc_state
);
15020 intel_mode_from_pipe_config(&crtc_state
->base
.adjusted_mode
, crtc_state
);
15021 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->base
.state
, &crtc
->base
.mode
));
15024 * The initial mode needs to be set in order to keep
15025 * the atomic core happy. It wants a valid mode if the
15026 * crtc's enabled, so we do the above call.
15028 * But we don't set all the derived state fully, hence
15029 * set a flag to indicate that a full recalculation is
15030 * needed on the next commit.
15032 crtc_state
->base
.mode
.private_flags
= I915_MODE_FLAG_INHERITED
;
15034 intel_crtc_compute_pixel_rate(crtc_state
);
15036 if (dev_priv
->display
.modeset_calc_cdclk
) {
15037 min_cdclk
= intel_crtc_compute_min_cdclk(crtc_state
);
15038 if (WARN_ON(min_cdclk
< 0))
15042 drm_calc_timestamping_constants(&crtc
->base
,
15043 &crtc_state
->base
.adjusted_mode
);
15044 update_scanline_offset(crtc
);
15047 dev_priv
->min_cdclk
[crtc
->pipe
] = min_cdclk
;
15049 intel_pipe_config_sanity_check(dev_priv
, crtc_state
);
15054 get_encoder_power_domains(struct drm_i915_private
*dev_priv
)
15056 struct intel_encoder
*encoder
;
15058 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
15060 enum intel_display_power_domain domain
;
15062 if (!encoder
->get_power_domains
)
15065 get_domains
= encoder
->get_power_domains(encoder
);
15066 for_each_power_domain(domain
, get_domains
)
15067 intel_display_power_get(dev_priv
, domain
);
15071 /* Scan out the current hw modeset state,
15072 * and sanitizes it to the current state
15075 intel_modeset_setup_hw_state(struct drm_device
*dev
,
15076 struct drm_modeset_acquire_ctx
*ctx
)
15078 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15080 struct intel_crtc
*crtc
;
15081 struct intel_encoder
*encoder
;
15084 if (IS_HASWELL(dev_priv
)) {
15086 * WaRsPkgCStateDisplayPMReq:hsw
15087 * System hang if this isn't done before disabling all planes!
15089 I915_WRITE(CHICKEN_PAR1_1
,
15090 I915_READ(CHICKEN_PAR1_1
) | FORCE_ARB_IDLE_PLANES
);
15093 intel_modeset_readout_hw_state(dev
);
15095 /* HW state is read out, now we need to sanitize this mess. */
15096 get_encoder_power_domains(dev_priv
);
15098 for_each_intel_encoder(dev
, encoder
) {
15099 intel_sanitize_encoder(encoder
);
15102 for_each_pipe(dev_priv
, pipe
) {
15103 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
15105 intel_sanitize_crtc(crtc
, ctx
);
15106 intel_dump_pipe_config(crtc
, crtc
->config
,
15107 "[setup_hw_state]");
15110 intel_modeset_update_connector_atomic_state(dev
);
15112 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
15113 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
15115 if (!pll
->on
|| pll
->active_mask
)
15118 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
15120 pll
->funcs
.disable(dev_priv
, pll
);
15124 if (IS_G4X(dev_priv
)) {
15125 g4x_wm_get_hw_state(dev
);
15126 g4x_wm_sanitize(dev_priv
);
15127 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
15128 vlv_wm_get_hw_state(dev
);
15129 vlv_wm_sanitize(dev_priv
);
15130 } else if (INTEL_GEN(dev_priv
) >= 9) {
15131 skl_wm_get_hw_state(dev
);
15132 } else if (HAS_PCH_SPLIT(dev_priv
)) {
15133 ilk_wm_get_hw_state(dev
);
15136 for_each_intel_crtc(dev
, crtc
) {
15139 put_domains
= modeset_get_crtc_power_domains(&crtc
->base
, crtc
->config
);
15140 if (WARN_ON(put_domains
))
15141 modeset_put_power_domains(dev_priv
, put_domains
);
15143 intel_display_set_init_power(dev_priv
, false);
15145 intel_power_domains_verify_state(dev_priv
);
15147 intel_fbc_init_pipe_state(dev_priv
);
15150 void intel_display_resume(struct drm_device
*dev
)
15152 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15153 struct drm_atomic_state
*state
= dev_priv
->modeset_restore_state
;
15154 struct drm_modeset_acquire_ctx ctx
;
15157 dev_priv
->modeset_restore_state
= NULL
;
15159 state
->acquire_ctx
= &ctx
;
15161 drm_modeset_acquire_init(&ctx
, 0);
15164 ret
= drm_modeset_lock_all_ctx(dev
, &ctx
);
15165 if (ret
!= -EDEADLK
)
15168 drm_modeset_backoff(&ctx
);
15172 ret
= __intel_display_resume(dev
, state
, &ctx
);
15174 intel_enable_ipc(dev_priv
);
15175 drm_modeset_drop_locks(&ctx
);
15176 drm_modeset_acquire_fini(&ctx
);
15179 DRM_ERROR("Restoring old state failed with %i\n", ret
);
15181 drm_atomic_state_put(state
);
15184 void intel_modeset_gem_init(struct drm_device
*dev
)
15186 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15188 intel_init_gt_powersave(dev_priv
);
15190 intel_init_clock_gating(dev_priv
);
15192 intel_setup_overlay(dev_priv
);
15195 int intel_connector_register(struct drm_connector
*connector
)
15197 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
15200 ret
= intel_backlight_device_register(intel_connector
);
15210 void intel_connector_unregister(struct drm_connector
*connector
)
15212 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
15214 intel_backlight_device_unregister(intel_connector
);
15215 intel_panel_destroy_backlight(connector
);
15218 static void intel_hpd_poll_fini(struct drm_device
*dev
)
15220 struct intel_connector
*connector
;
15221 struct drm_connector_list_iter conn_iter
;
15223 /* First disable polling... */
15224 drm_kms_helper_poll_fini(dev
);
15226 /* Then kill the work that may have been queued by hpd. */
15227 drm_connector_list_iter_begin(dev
, &conn_iter
);
15228 for_each_intel_connector_iter(connector
, &conn_iter
) {
15229 if (connector
->modeset_retry_work
.func
)
15230 cancel_work_sync(&connector
->modeset_retry_work
);
15232 drm_connector_list_iter_end(&conn_iter
);
15235 void intel_modeset_cleanup(struct drm_device
*dev
)
15237 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15239 flush_work(&dev_priv
->atomic_helper
.free_work
);
15240 WARN_ON(!llist_empty(&dev_priv
->atomic_helper
.free_list
));
15242 intel_disable_gt_powersave(dev_priv
);
15245 * Interrupts and polling as the first thing to avoid creating havoc.
15246 * Too much stuff here (turning of connectors, ...) would
15247 * experience fancy races otherwise.
15249 intel_irq_uninstall(dev_priv
);
15252 * Due to the hpd irq storm handling the hotplug work can re-arm the
15253 * poll handlers. Hence disable polling after hpd handling is shut down.
15255 intel_hpd_poll_fini(dev
);
15257 /* poll work can call into fbdev, hence clean that up afterwards */
15258 intel_fbdev_fini(dev_priv
);
15260 intel_unregister_dsm_handler();
15262 intel_fbc_global_disable(dev_priv
);
15264 /* flush any delayed tasks or pending work */
15265 flush_scheduled_work();
15267 drm_mode_config_cleanup(dev
);
15269 intel_cleanup_overlay(dev_priv
);
15271 intel_cleanup_gt_powersave(dev_priv
);
15273 intel_teardown_gmbus(dev_priv
);
15276 void intel_connector_attach_encoder(struct intel_connector
*connector
,
15277 struct intel_encoder
*encoder
)
15279 connector
->encoder
= encoder
;
15280 drm_mode_connector_attach_encoder(&connector
->base
,
15285 * set vga decode state - true == enable VGA decode
15287 int intel_modeset_vga_set_state(struct drm_i915_private
*dev_priv
, bool state
)
15289 unsigned reg
= INTEL_GEN(dev_priv
) >= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
15292 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
15293 DRM_ERROR("failed to read control word\n");
15297 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
15301 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
15303 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
15305 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
15306 DRM_ERROR("failed to write control word\n");
15313 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15315 struct intel_display_error_state
{
15317 u32 power_well_driver
;
15319 int num_transcoders
;
15321 struct intel_cursor_error_state
{
15326 } cursor
[I915_MAX_PIPES
];
15328 struct intel_pipe_error_state
{
15329 bool power_domain_on
;
15332 } pipe
[I915_MAX_PIPES
];
15334 struct intel_plane_error_state
{
15342 } plane
[I915_MAX_PIPES
];
15344 struct intel_transcoder_error_state
{
15345 bool power_domain_on
;
15346 enum transcoder cpu_transcoder
;
15359 struct intel_display_error_state
*
15360 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
)
15362 struct intel_display_error_state
*error
;
15363 int transcoders
[] = {
15371 if (INTEL_INFO(dev_priv
)->num_pipes
== 0)
15374 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
15378 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
15379 error
->power_well_driver
=
15380 I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL
));
15382 for_each_pipe(dev_priv
, i
) {
15383 error
->pipe
[i
].power_domain_on
=
15384 __intel_display_power_is_enabled(dev_priv
,
15385 POWER_DOMAIN_PIPE(i
));
15386 if (!error
->pipe
[i
].power_domain_on
)
15389 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
15390 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
15391 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
15393 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
15394 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
15395 if (INTEL_GEN(dev_priv
) <= 3) {
15396 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
15397 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
15399 if (INTEL_GEN(dev_priv
) <= 7 && !IS_HASWELL(dev_priv
))
15400 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
15401 if (INTEL_GEN(dev_priv
) >= 4) {
15402 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
15403 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
15406 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
15408 if (HAS_GMCH_DISPLAY(dev_priv
))
15409 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
15412 /* Note: this does not include DSI transcoders. */
15413 error
->num_transcoders
= INTEL_INFO(dev_priv
)->num_pipes
;
15414 if (HAS_DDI(dev_priv
))
15415 error
->num_transcoders
++; /* Account for eDP. */
15417 for (i
= 0; i
< error
->num_transcoders
; i
++) {
15418 enum transcoder cpu_transcoder
= transcoders
[i
];
15420 error
->transcoder
[i
].power_domain_on
=
15421 __intel_display_power_is_enabled(dev_priv
,
15422 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
15423 if (!error
->transcoder
[i
].power_domain_on
)
15426 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
15428 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
15429 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
15430 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
15431 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
15432 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
15433 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
15434 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
15440 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15443 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
15444 struct intel_display_error_state
*error
)
15446 struct drm_i915_private
*dev_priv
= m
->i915
;
15452 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev_priv
)->num_pipes
);
15453 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
15454 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
15455 error
->power_well_driver
);
15456 for_each_pipe(dev_priv
, i
) {
15457 err_printf(m
, "Pipe [%d]:\n", i
);
15458 err_printf(m
, " Power: %s\n",
15459 onoff(error
->pipe
[i
].power_domain_on
));
15460 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
15461 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
15463 err_printf(m
, "Plane [%d]:\n", i
);
15464 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
15465 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
15466 if (INTEL_GEN(dev_priv
) <= 3) {
15467 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
15468 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
15470 if (INTEL_GEN(dev_priv
) <= 7 && !IS_HASWELL(dev_priv
))
15471 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
15472 if (INTEL_GEN(dev_priv
) >= 4) {
15473 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
15474 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
15477 err_printf(m
, "Cursor [%d]:\n", i
);
15478 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
15479 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
15480 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
15483 for (i
= 0; i
< error
->num_transcoders
; i
++) {
15484 err_printf(m
, "CPU transcoder: %s\n",
15485 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
15486 err_printf(m
, " Power: %s\n",
15487 onoff(error
->transcoder
[i
].power_domain_on
));
15488 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
15489 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
15490 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
15491 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
15492 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
15493 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
15494 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);