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Merge remote-tracking branch 'airlied/drm-fixes' into drm-intel-next-queued
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/cpufreq.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include "drmP.h"
36 #include "intel_drv.h"
37 #include "i915_drm.h"
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
43
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_update_watermarks(struct drm_device *dev);
48 static void intel_increase_pllclock(struct drm_crtc *crtc);
49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
50
51 typedef struct {
52 /* given values */
53 int n;
54 int m1, m2;
55 int p1, p2;
56 /* derived values */
57 int dot;
58 int vco;
59 int m;
60 int p;
61 } intel_clock_t;
62
63 typedef struct {
64 int min, max;
65 } intel_range_t;
66
67 typedef struct {
68 int dot_limit;
69 int p2_slow, p2_fast;
70 } intel_p2_t;
71
72 #define INTEL_P2_NUM 2
73 typedef struct intel_limit intel_limit_t;
74 struct intel_limit {
75 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 intel_p2_t p2;
77 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
78 int, int, intel_clock_t *, intel_clock_t *);
79 };
80
81 /* FDI */
82 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
83
84 static bool
85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
86 int target, int refclk, intel_clock_t *match_clock,
87 intel_clock_t *best_clock);
88 static bool
89 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
90 int target, int refclk, intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
92
93 static bool
94 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
97 static bool
98 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
101
102 static inline u32 /* units of 100MHz */
103 intel_fdi_link_freq(struct drm_device *dev)
104 {
105 if (IS_GEN5(dev)) {
106 struct drm_i915_private *dev_priv = dev->dev_private;
107 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
108 } else
109 return 27;
110 }
111
112 static const intel_limit_t intel_limits_i8xx_dvo = {
113 .dot = { .min = 25000, .max = 350000 },
114 .vco = { .min = 930000, .max = 1400000 },
115 .n = { .min = 3, .max = 16 },
116 .m = { .min = 96, .max = 140 },
117 .m1 = { .min = 18, .max = 26 },
118 .m2 = { .min = 6, .max = 16 },
119 .p = { .min = 4, .max = 128 },
120 .p1 = { .min = 2, .max = 33 },
121 .p2 = { .dot_limit = 165000,
122 .p2_slow = 4, .p2_fast = 2 },
123 .find_pll = intel_find_best_PLL,
124 };
125
126 static const intel_limit_t intel_limits_i8xx_lvds = {
127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 1, .max = 6 },
135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 14, .p2_fast = 7 },
137 .find_pll = intel_find_best_PLL,
138 };
139
140 static const intel_limit_t intel_limits_i9xx_sdvo = {
141 .dot = { .min = 20000, .max = 400000 },
142 .vco = { .min = 1400000, .max = 2800000 },
143 .n = { .min = 1, .max = 6 },
144 .m = { .min = 70, .max = 120 },
145 .m1 = { .min = 10, .max = 22 },
146 .m2 = { .min = 5, .max = 9 },
147 .p = { .min = 5, .max = 80 },
148 .p1 = { .min = 1, .max = 8 },
149 .p2 = { .dot_limit = 200000,
150 .p2_slow = 10, .p2_fast = 5 },
151 .find_pll = intel_find_best_PLL,
152 };
153
154 static const intel_limit_t intel_limits_i9xx_lvds = {
155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 7, .max = 98 },
162 .p1 = { .min = 1, .max = 8 },
163 .p2 = { .dot_limit = 112000,
164 .p2_slow = 14, .p2_fast = 7 },
165 .find_pll = intel_find_best_PLL,
166 };
167
168
169 static const intel_limit_t intel_limits_g4x_sdvo = {
170 .dot = { .min = 25000, .max = 270000 },
171 .vco = { .min = 1750000, .max = 3500000},
172 .n = { .min = 1, .max = 4 },
173 .m = { .min = 104, .max = 138 },
174 .m1 = { .min = 17, .max = 23 },
175 .m2 = { .min = 5, .max = 11 },
176 .p = { .min = 10, .max = 30 },
177 .p1 = { .min = 1, .max = 3},
178 .p2 = { .dot_limit = 270000,
179 .p2_slow = 10,
180 .p2_fast = 10
181 },
182 .find_pll = intel_g4x_find_best_PLL,
183 };
184
185 static const intel_limit_t intel_limits_g4x_hdmi = {
186 .dot = { .min = 22000, .max = 400000 },
187 .vco = { .min = 1750000, .max = 3500000},
188 .n = { .min = 1, .max = 4 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 16, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 5, .max = 80 },
193 .p1 = { .min = 1, .max = 8},
194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 10, .p2_fast = 5 },
196 .find_pll = intel_g4x_find_best_PLL,
197 };
198
199 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
200 .dot = { .min = 20000, .max = 115000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 28, .max = 112 },
207 .p1 = { .min = 2, .max = 8 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 14, .p2_fast = 14
210 },
211 .find_pll = intel_g4x_find_best_PLL,
212 };
213
214 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
215 .dot = { .min = 80000, .max = 224000 },
216 .vco = { .min = 1750000, .max = 3500000 },
217 .n = { .min = 1, .max = 3 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 14, .max = 42 },
222 .p1 = { .min = 2, .max = 6 },
223 .p2 = { .dot_limit = 0,
224 .p2_slow = 7, .p2_fast = 7
225 },
226 .find_pll = intel_g4x_find_best_PLL,
227 };
228
229 static const intel_limit_t intel_limits_g4x_display_port = {
230 .dot = { .min = 161670, .max = 227000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 2 },
233 .m = { .min = 97, .max = 108 },
234 .m1 = { .min = 0x10, .max = 0x12 },
235 .m2 = { .min = 0x05, .max = 0x06 },
236 .p = { .min = 10, .max = 20 },
237 .p1 = { .min = 1, .max = 2},
238 .p2 = { .dot_limit = 0,
239 .p2_slow = 10, .p2_fast = 10 },
240 .find_pll = intel_find_pll_g4x_dp,
241 };
242
243 static const intel_limit_t intel_limits_pineview_sdvo = {
244 .dot = { .min = 20000, .max = 400000},
245 .vco = { .min = 1700000, .max = 3500000 },
246 /* Pineview's Ncounter is a ring counter */
247 .n = { .min = 3, .max = 6 },
248 .m = { .min = 2, .max = 256 },
249 /* Pineview only has one combined m divider, which we treat as m2. */
250 .m1 = { .min = 0, .max = 0 },
251 .m2 = { .min = 0, .max = 254 },
252 .p = { .min = 5, .max = 80 },
253 .p1 = { .min = 1, .max = 8 },
254 .p2 = { .dot_limit = 200000,
255 .p2_slow = 10, .p2_fast = 5 },
256 .find_pll = intel_find_best_PLL,
257 };
258
259 static const intel_limit_t intel_limits_pineview_lvds = {
260 .dot = { .min = 20000, .max = 400000 },
261 .vco = { .min = 1700000, .max = 3500000 },
262 .n = { .min = 3, .max = 6 },
263 .m = { .min = 2, .max = 256 },
264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 7, .max = 112 },
267 .p1 = { .min = 1, .max = 8 },
268 .p2 = { .dot_limit = 112000,
269 .p2_slow = 14, .p2_fast = 14 },
270 .find_pll = intel_find_best_PLL,
271 };
272
273 /* Ironlake / Sandybridge
274 *
275 * We calculate clock using (register_value + 2) for N/M1/M2, so here
276 * the range value for them is (actual_value - 2).
277 */
278 static const intel_limit_t intel_limits_ironlake_dac = {
279 .dot = { .min = 25000, .max = 350000 },
280 .vco = { .min = 1760000, .max = 3510000 },
281 .n = { .min = 1, .max = 5 },
282 .m = { .min = 79, .max = 127 },
283 .m1 = { .min = 12, .max = 22 },
284 .m2 = { .min = 5, .max = 9 },
285 .p = { .min = 5, .max = 80 },
286 .p1 = { .min = 1, .max = 8 },
287 .p2 = { .dot_limit = 225000,
288 .p2_slow = 10, .p2_fast = 5 },
289 .find_pll = intel_g4x_find_best_PLL,
290 };
291
292 static const intel_limit_t intel_limits_ironlake_single_lvds = {
293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 3 },
296 .m = { .min = 79, .max = 118 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 28, .max = 112 },
300 .p1 = { .min = 2, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 14, .p2_fast = 14 },
303 .find_pll = intel_g4x_find_best_PLL,
304 };
305
306 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 14, .max = 56 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 7, .p2_fast = 7 },
317 .find_pll = intel_g4x_find_best_PLL,
318 };
319
320 /* LVDS 100mhz refclk limits. */
321 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
322 .dot = { .min = 25000, .max = 350000 },
323 .vco = { .min = 1760000, .max = 3510000 },
324 .n = { .min = 1, .max = 2 },
325 .m = { .min = 79, .max = 126 },
326 .m1 = { .min = 12, .max = 22 },
327 .m2 = { .min = 5, .max = 9 },
328 .p = { .min = 28, .max = 112 },
329 .p1 = { .min = 2, .max = 8 },
330 .p2 = { .dot_limit = 225000,
331 .p2_slow = 14, .p2_fast = 14 },
332 .find_pll = intel_g4x_find_best_PLL,
333 };
334
335 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 3 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 14, .max = 42 },
343 .p1 = { .min = 2, .max = 6 },
344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 7, .p2_fast = 7 },
346 .find_pll = intel_g4x_find_best_PLL,
347 };
348
349 static const intel_limit_t intel_limits_ironlake_display_port = {
350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000},
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 81, .max = 90 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 10, .max = 20 },
357 .p1 = { .min = 1, .max = 2},
358 .p2 = { .dot_limit = 0,
359 .p2_slow = 10, .p2_fast = 10 },
360 .find_pll = intel_find_pll_ironlake_dp,
361 };
362
363 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
364 int refclk)
365 {
366 struct drm_device *dev = crtc->dev;
367 struct drm_i915_private *dev_priv = dev->dev_private;
368 const intel_limit_t *limit;
369
370 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
371 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
372 LVDS_CLKB_POWER_UP) {
373 /* LVDS dual channel */
374 if (refclk == 100000)
375 limit = &intel_limits_ironlake_dual_lvds_100m;
376 else
377 limit = &intel_limits_ironlake_dual_lvds;
378 } else {
379 if (refclk == 100000)
380 limit = &intel_limits_ironlake_single_lvds_100m;
381 else
382 limit = &intel_limits_ironlake_single_lvds;
383 }
384 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
385 HAS_eDP)
386 limit = &intel_limits_ironlake_display_port;
387 else
388 limit = &intel_limits_ironlake_dac;
389
390 return limit;
391 }
392
393 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
394 {
395 struct drm_device *dev = crtc->dev;
396 struct drm_i915_private *dev_priv = dev->dev_private;
397 const intel_limit_t *limit;
398
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
400 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
401 LVDS_CLKB_POWER_UP)
402 /* LVDS with dual channel */
403 limit = &intel_limits_g4x_dual_channel_lvds;
404 else
405 /* LVDS with dual channel */
406 limit = &intel_limits_g4x_single_channel_lvds;
407 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
408 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
409 limit = &intel_limits_g4x_hdmi;
410 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
411 limit = &intel_limits_g4x_sdvo;
412 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
413 limit = &intel_limits_g4x_display_port;
414 } else /* The option is for other outputs */
415 limit = &intel_limits_i9xx_sdvo;
416
417 return limit;
418 }
419
420 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
421 {
422 struct drm_device *dev = crtc->dev;
423 const intel_limit_t *limit;
424
425 if (HAS_PCH_SPLIT(dev))
426 limit = intel_ironlake_limit(crtc, refclk);
427 else if (IS_G4X(dev)) {
428 limit = intel_g4x_limit(crtc);
429 } else if (IS_PINEVIEW(dev)) {
430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
431 limit = &intel_limits_pineview_lvds;
432 else
433 limit = &intel_limits_pineview_sdvo;
434 } else if (!IS_GEN2(dev)) {
435 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
436 limit = &intel_limits_i9xx_lvds;
437 else
438 limit = &intel_limits_i9xx_sdvo;
439 } else {
440 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
441 limit = &intel_limits_i8xx_lvds;
442 else
443 limit = &intel_limits_i8xx_dvo;
444 }
445 return limit;
446 }
447
448 /* m1 is reserved as 0 in Pineview, n is a ring counter */
449 static void pineview_clock(int refclk, intel_clock_t *clock)
450 {
451 clock->m = clock->m2 + 2;
452 clock->p = clock->p1 * clock->p2;
453 clock->vco = refclk * clock->m / clock->n;
454 clock->dot = clock->vco / clock->p;
455 }
456
457 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
458 {
459 if (IS_PINEVIEW(dev)) {
460 pineview_clock(refclk, clock);
461 return;
462 }
463 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
464 clock->p = clock->p1 * clock->p2;
465 clock->vco = refclk * clock->m / (clock->n + 2);
466 clock->dot = clock->vco / clock->p;
467 }
468
469 /**
470 * Returns whether any output on the specified pipe is of the specified type
471 */
472 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
473 {
474 struct drm_device *dev = crtc->dev;
475 struct drm_mode_config *mode_config = &dev->mode_config;
476 struct intel_encoder *encoder;
477
478 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
479 if (encoder->base.crtc == crtc && encoder->type == type)
480 return true;
481
482 return false;
483 }
484
485 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
486 /**
487 * Returns whether the given set of divisors are valid for a given refclk with
488 * the given connectors.
489 */
490
491 static bool intel_PLL_is_valid(struct drm_device *dev,
492 const intel_limit_t *limit,
493 const intel_clock_t *clock)
494 {
495 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
496 INTELPllInvalid("p1 out of range\n");
497 if (clock->p < limit->p.min || limit->p.max < clock->p)
498 INTELPllInvalid("p out of range\n");
499 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
500 INTELPllInvalid("m2 out of range\n");
501 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
502 INTELPllInvalid("m1 out of range\n");
503 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
504 INTELPllInvalid("m1 <= m2\n");
505 if (clock->m < limit->m.min || limit->m.max < clock->m)
506 INTELPllInvalid("m out of range\n");
507 if (clock->n < limit->n.min || limit->n.max < clock->n)
508 INTELPllInvalid("n out of range\n");
509 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
510 INTELPllInvalid("vco out of range\n");
511 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
512 * connector, etc., rather than just a single range.
513 */
514 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
515 INTELPllInvalid("dot out of range\n");
516
517 return true;
518 }
519
520 static bool
521 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
522 int target, int refclk, intel_clock_t *match_clock,
523 intel_clock_t *best_clock)
524
525 {
526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
528 intel_clock_t clock;
529 int err = target;
530
531 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
532 (I915_READ(LVDS)) != 0) {
533 /*
534 * For LVDS, if the panel is on, just rely on its current
535 * settings for dual-channel. We haven't figured out how to
536 * reliably set up different single/dual channel state, if we
537 * even can.
538 */
539 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
540 LVDS_CLKB_POWER_UP)
541 clock.p2 = limit->p2.p2_fast;
542 else
543 clock.p2 = limit->p2.p2_slow;
544 } else {
545 if (target < limit->p2.dot_limit)
546 clock.p2 = limit->p2.p2_slow;
547 else
548 clock.p2 = limit->p2.p2_fast;
549 }
550
551 memset(best_clock, 0, sizeof(*best_clock));
552
553 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
554 clock.m1++) {
555 for (clock.m2 = limit->m2.min;
556 clock.m2 <= limit->m2.max; clock.m2++) {
557 /* m1 is always 0 in Pineview */
558 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
559 break;
560 for (clock.n = limit->n.min;
561 clock.n <= limit->n.max; clock.n++) {
562 for (clock.p1 = limit->p1.min;
563 clock.p1 <= limit->p1.max; clock.p1++) {
564 int this_err;
565
566 intel_clock(dev, refclk, &clock);
567 if (!intel_PLL_is_valid(dev, limit,
568 &clock))
569 continue;
570 if (match_clock &&
571 clock.p != match_clock->p)
572 continue;
573
574 this_err = abs(clock.dot - target);
575 if (this_err < err) {
576 *best_clock = clock;
577 err = this_err;
578 }
579 }
580 }
581 }
582 }
583
584 return (err != target);
585 }
586
587 static bool
588 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
589 int target, int refclk, intel_clock_t *match_clock,
590 intel_clock_t *best_clock)
591 {
592 struct drm_device *dev = crtc->dev;
593 struct drm_i915_private *dev_priv = dev->dev_private;
594 intel_clock_t clock;
595 int max_n;
596 bool found;
597 /* approximately equals target * 0.00585 */
598 int err_most = (target >> 8) + (target >> 9);
599 found = false;
600
601 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
602 int lvds_reg;
603
604 if (HAS_PCH_SPLIT(dev))
605 lvds_reg = PCH_LVDS;
606 else
607 lvds_reg = LVDS;
608 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
609 LVDS_CLKB_POWER_UP)
610 clock.p2 = limit->p2.p2_fast;
611 else
612 clock.p2 = limit->p2.p2_slow;
613 } else {
614 if (target < limit->p2.dot_limit)
615 clock.p2 = limit->p2.p2_slow;
616 else
617 clock.p2 = limit->p2.p2_fast;
618 }
619
620 memset(best_clock, 0, sizeof(*best_clock));
621 max_n = limit->n.max;
622 /* based on hardware requirement, prefer smaller n to precision */
623 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
624 /* based on hardware requirement, prefere larger m1,m2 */
625 for (clock.m1 = limit->m1.max;
626 clock.m1 >= limit->m1.min; clock.m1--) {
627 for (clock.m2 = limit->m2.max;
628 clock.m2 >= limit->m2.min; clock.m2--) {
629 for (clock.p1 = limit->p1.max;
630 clock.p1 >= limit->p1.min; clock.p1--) {
631 int this_err;
632
633 intel_clock(dev, refclk, &clock);
634 if (!intel_PLL_is_valid(dev, limit,
635 &clock))
636 continue;
637 if (match_clock &&
638 clock.p != match_clock->p)
639 continue;
640
641 this_err = abs(clock.dot - target);
642 if (this_err < err_most) {
643 *best_clock = clock;
644 err_most = this_err;
645 max_n = clock.n;
646 found = true;
647 }
648 }
649 }
650 }
651 }
652 return found;
653 }
654
655 static bool
656 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
657 int target, int refclk, intel_clock_t *match_clock,
658 intel_clock_t *best_clock)
659 {
660 struct drm_device *dev = crtc->dev;
661 intel_clock_t clock;
662
663 if (target < 200000) {
664 clock.n = 1;
665 clock.p1 = 2;
666 clock.p2 = 10;
667 clock.m1 = 12;
668 clock.m2 = 9;
669 } else {
670 clock.n = 2;
671 clock.p1 = 1;
672 clock.p2 = 10;
673 clock.m1 = 14;
674 clock.m2 = 8;
675 }
676 intel_clock(dev, refclk, &clock);
677 memcpy(best_clock, &clock, sizeof(intel_clock_t));
678 return true;
679 }
680
681 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
682 static bool
683 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
684 int target, int refclk, intel_clock_t *match_clock,
685 intel_clock_t *best_clock)
686 {
687 intel_clock_t clock;
688 if (target < 200000) {
689 clock.p1 = 2;
690 clock.p2 = 10;
691 clock.n = 2;
692 clock.m1 = 23;
693 clock.m2 = 8;
694 } else {
695 clock.p1 = 1;
696 clock.p2 = 10;
697 clock.n = 1;
698 clock.m1 = 14;
699 clock.m2 = 2;
700 }
701 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
702 clock.p = (clock.p1 * clock.p2);
703 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
704 clock.vco = 0;
705 memcpy(best_clock, &clock, sizeof(intel_clock_t));
706 return true;
707 }
708
709 /**
710 * intel_wait_for_vblank - wait for vblank on a given pipe
711 * @dev: drm device
712 * @pipe: pipe to wait for
713 *
714 * Wait for vblank to occur on a given pipe. Needed for various bits of
715 * mode setting code.
716 */
717 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
718 {
719 struct drm_i915_private *dev_priv = dev->dev_private;
720 int pipestat_reg = PIPESTAT(pipe);
721
722 /* Clear existing vblank status. Note this will clear any other
723 * sticky status fields as well.
724 *
725 * This races with i915_driver_irq_handler() with the result
726 * that either function could miss a vblank event. Here it is not
727 * fatal, as we will either wait upon the next vblank interrupt or
728 * timeout. Generally speaking intel_wait_for_vblank() is only
729 * called during modeset at which time the GPU should be idle and
730 * should *not* be performing page flips and thus not waiting on
731 * vblanks...
732 * Currently, the result of us stealing a vblank from the irq
733 * handler is that a single frame will be skipped during swapbuffers.
734 */
735 I915_WRITE(pipestat_reg,
736 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
737
738 /* Wait for vblank interrupt bit to set */
739 if (wait_for(I915_READ(pipestat_reg) &
740 PIPE_VBLANK_INTERRUPT_STATUS,
741 50))
742 DRM_DEBUG_KMS("vblank wait timed out\n");
743 }
744
745 /*
746 * intel_wait_for_pipe_off - wait for pipe to turn off
747 * @dev: drm device
748 * @pipe: pipe to wait for
749 *
750 * After disabling a pipe, we can't wait for vblank in the usual way,
751 * spinning on the vblank interrupt status bit, since we won't actually
752 * see an interrupt when the pipe is disabled.
753 *
754 * On Gen4 and above:
755 * wait for the pipe register state bit to turn off
756 *
757 * Otherwise:
758 * wait for the display line value to settle (it usually
759 * ends up stopping at the start of the next frame).
760 *
761 */
762 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
763 {
764 struct drm_i915_private *dev_priv = dev->dev_private;
765
766 if (INTEL_INFO(dev)->gen >= 4) {
767 int reg = PIPECONF(pipe);
768
769 /* Wait for the Pipe State to go off */
770 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
771 100))
772 DRM_DEBUG_KMS("pipe_off wait timed out\n");
773 } else {
774 u32 last_line;
775 int reg = PIPEDSL(pipe);
776 unsigned long timeout = jiffies + msecs_to_jiffies(100);
777
778 /* Wait for the display line to settle */
779 do {
780 last_line = I915_READ(reg) & DSL_LINEMASK;
781 mdelay(5);
782 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
783 time_after(timeout, jiffies));
784 if (time_after(jiffies, timeout))
785 DRM_DEBUG_KMS("pipe_off wait timed out\n");
786 }
787 }
788
789 static const char *state_string(bool enabled)
790 {
791 return enabled ? "on" : "off";
792 }
793
794 /* Only for pre-ILK configs */
795 static void assert_pll(struct drm_i915_private *dev_priv,
796 enum pipe pipe, bool state)
797 {
798 int reg;
799 u32 val;
800 bool cur_state;
801
802 reg = DPLL(pipe);
803 val = I915_READ(reg);
804 cur_state = !!(val & DPLL_VCO_ENABLE);
805 WARN(cur_state != state,
806 "PLL state assertion failure (expected %s, current %s)\n",
807 state_string(state), state_string(cur_state));
808 }
809 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
810 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
811
812 /* For ILK+ */
813 static void assert_pch_pll(struct drm_i915_private *dev_priv,
814 enum pipe pipe, bool state)
815 {
816 int reg;
817 u32 val;
818 bool cur_state;
819
820 if (HAS_PCH_CPT(dev_priv->dev)) {
821 u32 pch_dpll;
822
823 pch_dpll = I915_READ(PCH_DPLL_SEL);
824
825 /* Make sure the selected PLL is enabled to the transcoder */
826 WARN(!((pch_dpll >> (4 * pipe)) & 8),
827 "transcoder %d PLL not enabled\n", pipe);
828
829 /* Convert the transcoder pipe number to a pll pipe number */
830 pipe = (pch_dpll >> (4 * pipe)) & 1;
831 }
832
833 reg = PCH_DPLL(pipe);
834 val = I915_READ(reg);
835 cur_state = !!(val & DPLL_VCO_ENABLE);
836 WARN(cur_state != state,
837 "PCH PLL state assertion failure (expected %s, current %s)\n",
838 state_string(state), state_string(cur_state));
839 }
840 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
841 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
842
843 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
844 enum pipe pipe, bool state)
845 {
846 int reg;
847 u32 val;
848 bool cur_state;
849
850 reg = FDI_TX_CTL(pipe);
851 val = I915_READ(reg);
852 cur_state = !!(val & FDI_TX_ENABLE);
853 WARN(cur_state != state,
854 "FDI TX state assertion failure (expected %s, current %s)\n",
855 state_string(state), state_string(cur_state));
856 }
857 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
858 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
859
860 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
861 enum pipe pipe, bool state)
862 {
863 int reg;
864 u32 val;
865 bool cur_state;
866
867 reg = FDI_RX_CTL(pipe);
868 val = I915_READ(reg);
869 cur_state = !!(val & FDI_RX_ENABLE);
870 WARN(cur_state != state,
871 "FDI RX state assertion failure (expected %s, current %s)\n",
872 state_string(state), state_string(cur_state));
873 }
874 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
875 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
876
877 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
878 enum pipe pipe)
879 {
880 int reg;
881 u32 val;
882
883 /* ILK FDI PLL is always enabled */
884 if (dev_priv->info->gen == 5)
885 return;
886
887 reg = FDI_TX_CTL(pipe);
888 val = I915_READ(reg);
889 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
890 }
891
892 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
893 enum pipe pipe)
894 {
895 int reg;
896 u32 val;
897
898 reg = FDI_RX_CTL(pipe);
899 val = I915_READ(reg);
900 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
901 }
902
903 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
904 enum pipe pipe)
905 {
906 int pp_reg, lvds_reg;
907 u32 val;
908 enum pipe panel_pipe = PIPE_A;
909 bool locked = true;
910
911 if (HAS_PCH_SPLIT(dev_priv->dev)) {
912 pp_reg = PCH_PP_CONTROL;
913 lvds_reg = PCH_LVDS;
914 } else {
915 pp_reg = PP_CONTROL;
916 lvds_reg = LVDS;
917 }
918
919 val = I915_READ(pp_reg);
920 if (!(val & PANEL_POWER_ON) ||
921 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
922 locked = false;
923
924 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
925 panel_pipe = PIPE_B;
926
927 WARN(panel_pipe == pipe && locked,
928 "panel assertion failure, pipe %c regs locked\n",
929 pipe_name(pipe));
930 }
931
932 void assert_pipe(struct drm_i915_private *dev_priv,
933 enum pipe pipe, bool state)
934 {
935 int reg;
936 u32 val;
937 bool cur_state;
938
939 /* if we need the pipe A quirk it must be always on */
940 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
941 state = true;
942
943 reg = PIPECONF(pipe);
944 val = I915_READ(reg);
945 cur_state = !!(val & PIPECONF_ENABLE);
946 WARN(cur_state != state,
947 "pipe %c assertion failure (expected %s, current %s)\n",
948 pipe_name(pipe), state_string(state), state_string(cur_state));
949 }
950
951 static void assert_plane(struct drm_i915_private *dev_priv,
952 enum plane plane, bool state)
953 {
954 int reg;
955 u32 val;
956 bool cur_state;
957
958 reg = DSPCNTR(plane);
959 val = I915_READ(reg);
960 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
961 WARN(cur_state != state,
962 "plane %c assertion failure (expected %s, current %s)\n",
963 plane_name(plane), state_string(state), state_string(cur_state));
964 }
965
966 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
967 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
968
969 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
970 enum pipe pipe)
971 {
972 int reg, i;
973 u32 val;
974 int cur_pipe;
975
976 /* Planes are fixed to pipes on ILK+ */
977 if (HAS_PCH_SPLIT(dev_priv->dev)) {
978 reg = DSPCNTR(pipe);
979 val = I915_READ(reg);
980 WARN((val & DISPLAY_PLANE_ENABLE),
981 "plane %c assertion failure, should be disabled but not\n",
982 plane_name(pipe));
983 return;
984 }
985
986 /* Need to check both planes against the pipe */
987 for (i = 0; i < 2; i++) {
988 reg = DSPCNTR(i);
989 val = I915_READ(reg);
990 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
991 DISPPLANE_SEL_PIPE_SHIFT;
992 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
993 "plane %c assertion failure, should be off on pipe %c but is still active\n",
994 plane_name(i), pipe_name(pipe));
995 }
996 }
997
998 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
999 {
1000 u32 val;
1001 bool enabled;
1002
1003 val = I915_READ(PCH_DREF_CONTROL);
1004 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1005 DREF_SUPERSPREAD_SOURCE_MASK));
1006 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1007 }
1008
1009 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1010 enum pipe pipe)
1011 {
1012 int reg;
1013 u32 val;
1014 bool enabled;
1015
1016 reg = TRANSCONF(pipe);
1017 val = I915_READ(reg);
1018 enabled = !!(val & TRANS_ENABLE);
1019 WARN(enabled,
1020 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1021 pipe_name(pipe));
1022 }
1023
1024 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1025 enum pipe pipe, u32 port_sel, u32 val)
1026 {
1027 if ((val & DP_PORT_EN) == 0)
1028 return false;
1029
1030 if (HAS_PCH_CPT(dev_priv->dev)) {
1031 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1032 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1033 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1034 return false;
1035 } else {
1036 if ((val & DP_PIPE_MASK) != (pipe << 30))
1037 return false;
1038 }
1039 return true;
1040 }
1041
1042 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1043 enum pipe pipe, u32 val)
1044 {
1045 if ((val & PORT_ENABLE) == 0)
1046 return false;
1047
1048 if (HAS_PCH_CPT(dev_priv->dev)) {
1049 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1050 return false;
1051 } else {
1052 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1053 return false;
1054 }
1055 return true;
1056 }
1057
1058 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, u32 val)
1060 {
1061 if ((val & LVDS_PORT_EN) == 0)
1062 return false;
1063
1064 if (HAS_PCH_CPT(dev_priv->dev)) {
1065 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1066 return false;
1067 } else {
1068 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1069 return false;
1070 }
1071 return true;
1072 }
1073
1074 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1075 enum pipe pipe, u32 val)
1076 {
1077 if ((val & ADPA_DAC_ENABLE) == 0)
1078 return false;
1079 if (HAS_PCH_CPT(dev_priv->dev)) {
1080 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1081 return false;
1082 } else {
1083 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1084 return false;
1085 }
1086 return true;
1087 }
1088
1089 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1090 enum pipe pipe, int reg, u32 port_sel)
1091 {
1092 u32 val = I915_READ(reg);
1093 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1094 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1095 reg, pipe_name(pipe));
1096 }
1097
1098 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1099 enum pipe pipe, int reg)
1100 {
1101 u32 val = I915_READ(reg);
1102 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1103 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1104 reg, pipe_name(pipe));
1105 }
1106
1107 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1108 enum pipe pipe)
1109 {
1110 int reg;
1111 u32 val;
1112
1113 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1114 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1115 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1116
1117 reg = PCH_ADPA;
1118 val = I915_READ(reg);
1119 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1120 "PCH VGA enabled on transcoder %c, should be disabled\n",
1121 pipe_name(pipe));
1122
1123 reg = PCH_LVDS;
1124 val = I915_READ(reg);
1125 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1126 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1127 pipe_name(pipe));
1128
1129 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1130 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1131 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1132 }
1133
1134 /**
1135 * intel_enable_pll - enable a PLL
1136 * @dev_priv: i915 private structure
1137 * @pipe: pipe PLL to enable
1138 *
1139 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1140 * make sure the PLL reg is writable first though, since the panel write
1141 * protect mechanism may be enabled.
1142 *
1143 * Note! This is for pre-ILK only.
1144 */
1145 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1146 {
1147 int reg;
1148 u32 val;
1149
1150 /* No really, not for ILK+ */
1151 BUG_ON(dev_priv->info->gen >= 5);
1152
1153 /* PLL is protected by panel, make sure we can write it */
1154 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1155 assert_panel_unlocked(dev_priv, pipe);
1156
1157 reg = DPLL(pipe);
1158 val = I915_READ(reg);
1159 val |= DPLL_VCO_ENABLE;
1160
1161 /* We do this three times for luck */
1162 I915_WRITE(reg, val);
1163 POSTING_READ(reg);
1164 udelay(150); /* wait for warmup */
1165 I915_WRITE(reg, val);
1166 POSTING_READ(reg);
1167 udelay(150); /* wait for warmup */
1168 I915_WRITE(reg, val);
1169 POSTING_READ(reg);
1170 udelay(150); /* wait for warmup */
1171 }
1172
1173 /**
1174 * intel_disable_pll - disable a PLL
1175 * @dev_priv: i915 private structure
1176 * @pipe: pipe PLL to disable
1177 *
1178 * Disable the PLL for @pipe, making sure the pipe is off first.
1179 *
1180 * Note! This is for pre-ILK only.
1181 */
1182 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1183 {
1184 int reg;
1185 u32 val;
1186
1187 /* Don't disable pipe A or pipe A PLLs if needed */
1188 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1189 return;
1190
1191 /* Make sure the pipe isn't still relying on us */
1192 assert_pipe_disabled(dev_priv, pipe);
1193
1194 reg = DPLL(pipe);
1195 val = I915_READ(reg);
1196 val &= ~DPLL_VCO_ENABLE;
1197 I915_WRITE(reg, val);
1198 POSTING_READ(reg);
1199 }
1200
1201 /**
1202 * intel_enable_pch_pll - enable PCH PLL
1203 * @dev_priv: i915 private structure
1204 * @pipe: pipe PLL to enable
1205 *
1206 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1207 * drives the transcoder clock.
1208 */
1209 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1210 enum pipe pipe)
1211 {
1212 int reg;
1213 u32 val;
1214
1215 if (pipe > 1)
1216 return;
1217
1218 /* PCH only available on ILK+ */
1219 BUG_ON(dev_priv->info->gen < 5);
1220
1221 /* PCH refclock must be enabled first */
1222 assert_pch_refclk_enabled(dev_priv);
1223
1224 reg = PCH_DPLL(pipe);
1225 val = I915_READ(reg);
1226 val |= DPLL_VCO_ENABLE;
1227 I915_WRITE(reg, val);
1228 POSTING_READ(reg);
1229 udelay(200);
1230 }
1231
1232 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1233 enum pipe pipe)
1234 {
1235 int reg;
1236 u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1237 pll_sel = TRANSC_DPLL_ENABLE;
1238
1239 if (pipe > 1)
1240 return;
1241
1242 /* PCH only available on ILK+ */
1243 BUG_ON(dev_priv->info->gen < 5);
1244
1245 /* Make sure transcoder isn't still depending on us */
1246 assert_transcoder_disabled(dev_priv, pipe);
1247
1248 if (pipe == 0)
1249 pll_sel |= TRANSC_DPLLA_SEL;
1250 else if (pipe == 1)
1251 pll_sel |= TRANSC_DPLLB_SEL;
1252
1253
1254 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1255 return;
1256
1257 reg = PCH_DPLL(pipe);
1258 val = I915_READ(reg);
1259 val &= ~DPLL_VCO_ENABLE;
1260 I915_WRITE(reg, val);
1261 POSTING_READ(reg);
1262 udelay(200);
1263 }
1264
1265 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1266 enum pipe pipe)
1267 {
1268 int reg;
1269 u32 val;
1270
1271 /* PCH only available on ILK+ */
1272 BUG_ON(dev_priv->info->gen < 5);
1273
1274 /* Make sure PCH DPLL is enabled */
1275 assert_pch_pll_enabled(dev_priv, pipe);
1276
1277 /* FDI must be feeding us bits for PCH ports */
1278 assert_fdi_tx_enabled(dev_priv, pipe);
1279 assert_fdi_rx_enabled(dev_priv, pipe);
1280
1281 reg = TRANSCONF(pipe);
1282 val = I915_READ(reg);
1283
1284 if (HAS_PCH_IBX(dev_priv->dev)) {
1285 /*
1286 * make the BPC in transcoder be consistent with
1287 * that in pipeconf reg.
1288 */
1289 val &= ~PIPE_BPC_MASK;
1290 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1291 }
1292 I915_WRITE(reg, val | TRANS_ENABLE);
1293 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1294 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1295 }
1296
1297 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1298 enum pipe pipe)
1299 {
1300 int reg;
1301 u32 val;
1302
1303 /* FDI relies on the transcoder */
1304 assert_fdi_tx_disabled(dev_priv, pipe);
1305 assert_fdi_rx_disabled(dev_priv, pipe);
1306
1307 /* Ports must be off as well */
1308 assert_pch_ports_disabled(dev_priv, pipe);
1309
1310 reg = TRANSCONF(pipe);
1311 val = I915_READ(reg);
1312 val &= ~TRANS_ENABLE;
1313 I915_WRITE(reg, val);
1314 /* wait for PCH transcoder off, transcoder state */
1315 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1316 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1317 }
1318
1319 /**
1320 * intel_enable_pipe - enable a pipe, asserting requirements
1321 * @dev_priv: i915 private structure
1322 * @pipe: pipe to enable
1323 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1324 *
1325 * Enable @pipe, making sure that various hardware specific requirements
1326 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1327 *
1328 * @pipe should be %PIPE_A or %PIPE_B.
1329 *
1330 * Will wait until the pipe is actually running (i.e. first vblank) before
1331 * returning.
1332 */
1333 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1334 bool pch_port)
1335 {
1336 int reg;
1337 u32 val;
1338
1339 /*
1340 * A pipe without a PLL won't actually be able to drive bits from
1341 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1342 * need the check.
1343 */
1344 if (!HAS_PCH_SPLIT(dev_priv->dev))
1345 assert_pll_enabled(dev_priv, pipe);
1346 else {
1347 if (pch_port) {
1348 /* if driving the PCH, we need FDI enabled */
1349 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1350 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1351 }
1352 /* FIXME: assert CPU port conditions for SNB+ */
1353 }
1354
1355 reg = PIPECONF(pipe);
1356 val = I915_READ(reg);
1357 if (val & PIPECONF_ENABLE)
1358 return;
1359
1360 I915_WRITE(reg, val | PIPECONF_ENABLE);
1361 intel_wait_for_vblank(dev_priv->dev, pipe);
1362 }
1363
1364 /**
1365 * intel_disable_pipe - disable a pipe, asserting requirements
1366 * @dev_priv: i915 private structure
1367 * @pipe: pipe to disable
1368 *
1369 * Disable @pipe, making sure that various hardware specific requirements
1370 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1371 *
1372 * @pipe should be %PIPE_A or %PIPE_B.
1373 *
1374 * Will wait until the pipe has shut down before returning.
1375 */
1376 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1377 enum pipe pipe)
1378 {
1379 int reg;
1380 u32 val;
1381
1382 /*
1383 * Make sure planes won't keep trying to pump pixels to us,
1384 * or we might hang the display.
1385 */
1386 assert_planes_disabled(dev_priv, pipe);
1387
1388 /* Don't disable pipe A or pipe A PLLs if needed */
1389 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1390 return;
1391
1392 reg = PIPECONF(pipe);
1393 val = I915_READ(reg);
1394 if ((val & PIPECONF_ENABLE) == 0)
1395 return;
1396
1397 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1398 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1399 }
1400
1401 /*
1402 * Plane regs are double buffered, going from enabled->disabled needs a
1403 * trigger in order to latch. The display address reg provides this.
1404 */
1405 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1406 enum plane plane)
1407 {
1408 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1409 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1410 }
1411
1412 /**
1413 * intel_enable_plane - enable a display plane on a given pipe
1414 * @dev_priv: i915 private structure
1415 * @plane: plane to enable
1416 * @pipe: pipe being fed
1417 *
1418 * Enable @plane on @pipe, making sure that @pipe is running first.
1419 */
1420 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1421 enum plane plane, enum pipe pipe)
1422 {
1423 int reg;
1424 u32 val;
1425
1426 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1427 assert_pipe_enabled(dev_priv, pipe);
1428
1429 reg = DSPCNTR(plane);
1430 val = I915_READ(reg);
1431 if (val & DISPLAY_PLANE_ENABLE)
1432 return;
1433
1434 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1435 intel_flush_display_plane(dev_priv, plane);
1436 intel_wait_for_vblank(dev_priv->dev, pipe);
1437 }
1438
1439 /**
1440 * intel_disable_plane - disable a display plane
1441 * @dev_priv: i915 private structure
1442 * @plane: plane to disable
1443 * @pipe: pipe consuming the data
1444 *
1445 * Disable @plane; should be an independent operation.
1446 */
1447 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1448 enum plane plane, enum pipe pipe)
1449 {
1450 int reg;
1451 u32 val;
1452
1453 reg = DSPCNTR(plane);
1454 val = I915_READ(reg);
1455 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1456 return;
1457
1458 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1459 intel_flush_display_plane(dev_priv, plane);
1460 intel_wait_for_vblank(dev_priv->dev, pipe);
1461 }
1462
1463 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1464 enum pipe pipe, int reg, u32 port_sel)
1465 {
1466 u32 val = I915_READ(reg);
1467 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1468 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1469 I915_WRITE(reg, val & ~DP_PORT_EN);
1470 }
1471 }
1472
1473 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1474 enum pipe pipe, int reg)
1475 {
1476 u32 val = I915_READ(reg);
1477 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1478 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1479 reg, pipe);
1480 I915_WRITE(reg, val & ~PORT_ENABLE);
1481 }
1482 }
1483
1484 /* Disable any ports connected to this transcoder */
1485 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1486 enum pipe pipe)
1487 {
1488 u32 reg, val;
1489
1490 val = I915_READ(PCH_PP_CONTROL);
1491 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1492
1493 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1494 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1495 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1496
1497 reg = PCH_ADPA;
1498 val = I915_READ(reg);
1499 if (adpa_pipe_enabled(dev_priv, val, pipe))
1500 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1501
1502 reg = PCH_LVDS;
1503 val = I915_READ(reg);
1504 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1505 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1506 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1507 POSTING_READ(reg);
1508 udelay(100);
1509 }
1510
1511 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1512 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1513 disable_pch_hdmi(dev_priv, pipe, HDMID);
1514 }
1515
1516 static void i8xx_disable_fbc(struct drm_device *dev)
1517 {
1518 struct drm_i915_private *dev_priv = dev->dev_private;
1519 u32 fbc_ctl;
1520
1521 /* Disable compression */
1522 fbc_ctl = I915_READ(FBC_CONTROL);
1523 if ((fbc_ctl & FBC_CTL_EN) == 0)
1524 return;
1525
1526 fbc_ctl &= ~FBC_CTL_EN;
1527 I915_WRITE(FBC_CONTROL, fbc_ctl);
1528
1529 /* Wait for compressing bit to clear */
1530 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1531 DRM_DEBUG_KMS("FBC idle timed out\n");
1532 return;
1533 }
1534
1535 DRM_DEBUG_KMS("disabled FBC\n");
1536 }
1537
1538 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1539 {
1540 struct drm_device *dev = crtc->dev;
1541 struct drm_i915_private *dev_priv = dev->dev_private;
1542 struct drm_framebuffer *fb = crtc->fb;
1543 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1544 struct drm_i915_gem_object *obj = intel_fb->obj;
1545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1546 int cfb_pitch;
1547 int plane, i;
1548 u32 fbc_ctl, fbc_ctl2;
1549
1550 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1551 if (fb->pitches[0] < cfb_pitch)
1552 cfb_pitch = fb->pitches[0];
1553
1554 /* FBC_CTL wants 64B units */
1555 cfb_pitch = (cfb_pitch / 64) - 1;
1556 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1557
1558 /* Clear old tags */
1559 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1560 I915_WRITE(FBC_TAG + (i * 4), 0);
1561
1562 /* Set it up... */
1563 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1564 fbc_ctl2 |= plane;
1565 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1566 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1567
1568 /* enable it... */
1569 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1570 if (IS_I945GM(dev))
1571 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1572 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1573 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1574 fbc_ctl |= obj->fence_reg;
1575 I915_WRITE(FBC_CONTROL, fbc_ctl);
1576
1577 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1578 cfb_pitch, crtc->y, intel_crtc->plane);
1579 }
1580
1581 static bool i8xx_fbc_enabled(struct drm_device *dev)
1582 {
1583 struct drm_i915_private *dev_priv = dev->dev_private;
1584
1585 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1586 }
1587
1588 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1589 {
1590 struct drm_device *dev = crtc->dev;
1591 struct drm_i915_private *dev_priv = dev->dev_private;
1592 struct drm_framebuffer *fb = crtc->fb;
1593 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1594 struct drm_i915_gem_object *obj = intel_fb->obj;
1595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1596 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1597 unsigned long stall_watermark = 200;
1598 u32 dpfc_ctl;
1599
1600 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1601 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1602 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1603
1604 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1605 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1606 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1607 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1608
1609 /* enable it... */
1610 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1611
1612 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1613 }
1614
1615 static void g4x_disable_fbc(struct drm_device *dev)
1616 {
1617 struct drm_i915_private *dev_priv = dev->dev_private;
1618 u32 dpfc_ctl;
1619
1620 /* Disable compression */
1621 dpfc_ctl = I915_READ(DPFC_CONTROL);
1622 if (dpfc_ctl & DPFC_CTL_EN) {
1623 dpfc_ctl &= ~DPFC_CTL_EN;
1624 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1625
1626 DRM_DEBUG_KMS("disabled FBC\n");
1627 }
1628 }
1629
1630 static bool g4x_fbc_enabled(struct drm_device *dev)
1631 {
1632 struct drm_i915_private *dev_priv = dev->dev_private;
1633
1634 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1635 }
1636
1637 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1638 {
1639 struct drm_i915_private *dev_priv = dev->dev_private;
1640 u32 blt_ecoskpd;
1641
1642 /* Make sure blitter notifies FBC of writes */
1643 gen6_gt_force_wake_get(dev_priv);
1644 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1645 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1646 GEN6_BLITTER_LOCK_SHIFT;
1647 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1648 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1649 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1650 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1651 GEN6_BLITTER_LOCK_SHIFT);
1652 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1653 POSTING_READ(GEN6_BLITTER_ECOSKPD);
1654 gen6_gt_force_wake_put(dev_priv);
1655 }
1656
1657 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1658 {
1659 struct drm_device *dev = crtc->dev;
1660 struct drm_i915_private *dev_priv = dev->dev_private;
1661 struct drm_framebuffer *fb = crtc->fb;
1662 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1663 struct drm_i915_gem_object *obj = intel_fb->obj;
1664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1665 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1666 unsigned long stall_watermark = 200;
1667 u32 dpfc_ctl;
1668
1669 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1670 dpfc_ctl &= DPFC_RESERVED;
1671 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1672 /* Set persistent mode for front-buffer rendering, ala X. */
1673 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1674 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1675 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1676
1677 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1678 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1679 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1680 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1681 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1682 /* enable it... */
1683 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1684
1685 if (IS_GEN6(dev)) {
1686 I915_WRITE(SNB_DPFC_CTL_SA,
1687 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1688 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1689 sandybridge_blit_fbc_update(dev);
1690 }
1691
1692 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1693 }
1694
1695 static void ironlake_disable_fbc(struct drm_device *dev)
1696 {
1697 struct drm_i915_private *dev_priv = dev->dev_private;
1698 u32 dpfc_ctl;
1699
1700 /* Disable compression */
1701 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1702 if (dpfc_ctl & DPFC_CTL_EN) {
1703 dpfc_ctl &= ~DPFC_CTL_EN;
1704 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1705
1706 DRM_DEBUG_KMS("disabled FBC\n");
1707 }
1708 }
1709
1710 static bool ironlake_fbc_enabled(struct drm_device *dev)
1711 {
1712 struct drm_i915_private *dev_priv = dev->dev_private;
1713
1714 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1715 }
1716
1717 bool intel_fbc_enabled(struct drm_device *dev)
1718 {
1719 struct drm_i915_private *dev_priv = dev->dev_private;
1720
1721 if (!dev_priv->display.fbc_enabled)
1722 return false;
1723
1724 return dev_priv->display.fbc_enabled(dev);
1725 }
1726
1727 static void intel_fbc_work_fn(struct work_struct *__work)
1728 {
1729 struct intel_fbc_work *work =
1730 container_of(to_delayed_work(__work),
1731 struct intel_fbc_work, work);
1732 struct drm_device *dev = work->crtc->dev;
1733 struct drm_i915_private *dev_priv = dev->dev_private;
1734
1735 mutex_lock(&dev->struct_mutex);
1736 if (work == dev_priv->fbc_work) {
1737 /* Double check that we haven't switched fb without cancelling
1738 * the prior work.
1739 */
1740 if (work->crtc->fb == work->fb) {
1741 dev_priv->display.enable_fbc(work->crtc,
1742 work->interval);
1743
1744 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1745 dev_priv->cfb_fb = work->crtc->fb->base.id;
1746 dev_priv->cfb_y = work->crtc->y;
1747 }
1748
1749 dev_priv->fbc_work = NULL;
1750 }
1751 mutex_unlock(&dev->struct_mutex);
1752
1753 kfree(work);
1754 }
1755
1756 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1757 {
1758 if (dev_priv->fbc_work == NULL)
1759 return;
1760
1761 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1762
1763 /* Synchronisation is provided by struct_mutex and checking of
1764 * dev_priv->fbc_work, so we can perform the cancellation
1765 * entirely asynchronously.
1766 */
1767 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1768 /* tasklet was killed before being run, clean up */
1769 kfree(dev_priv->fbc_work);
1770
1771 /* Mark the work as no longer wanted so that if it does
1772 * wake-up (because the work was already running and waiting
1773 * for our mutex), it will discover that is no longer
1774 * necessary to run.
1775 */
1776 dev_priv->fbc_work = NULL;
1777 }
1778
1779 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1780 {
1781 struct intel_fbc_work *work;
1782 struct drm_device *dev = crtc->dev;
1783 struct drm_i915_private *dev_priv = dev->dev_private;
1784
1785 if (!dev_priv->display.enable_fbc)
1786 return;
1787
1788 intel_cancel_fbc_work(dev_priv);
1789
1790 work = kzalloc(sizeof *work, GFP_KERNEL);
1791 if (work == NULL) {
1792 dev_priv->display.enable_fbc(crtc, interval);
1793 return;
1794 }
1795
1796 work->crtc = crtc;
1797 work->fb = crtc->fb;
1798 work->interval = interval;
1799 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1800
1801 dev_priv->fbc_work = work;
1802
1803 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1804
1805 /* Delay the actual enabling to let pageflipping cease and the
1806 * display to settle before starting the compression. Note that
1807 * this delay also serves a second purpose: it allows for a
1808 * vblank to pass after disabling the FBC before we attempt
1809 * to modify the control registers.
1810 *
1811 * A more complicated solution would involve tracking vblanks
1812 * following the termination of the page-flipping sequence
1813 * and indeed performing the enable as a co-routine and not
1814 * waiting synchronously upon the vblank.
1815 */
1816 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1817 }
1818
1819 void intel_disable_fbc(struct drm_device *dev)
1820 {
1821 struct drm_i915_private *dev_priv = dev->dev_private;
1822
1823 intel_cancel_fbc_work(dev_priv);
1824
1825 if (!dev_priv->display.disable_fbc)
1826 return;
1827
1828 dev_priv->display.disable_fbc(dev);
1829 dev_priv->cfb_plane = -1;
1830 }
1831
1832 /**
1833 * intel_update_fbc - enable/disable FBC as needed
1834 * @dev: the drm_device
1835 *
1836 * Set up the framebuffer compression hardware at mode set time. We
1837 * enable it if possible:
1838 * - plane A only (on pre-965)
1839 * - no pixel mulitply/line duplication
1840 * - no alpha buffer discard
1841 * - no dual wide
1842 * - framebuffer <= 2048 in width, 1536 in height
1843 *
1844 * We can't assume that any compression will take place (worst case),
1845 * so the compressed buffer has to be the same size as the uncompressed
1846 * one. It also must reside (along with the line length buffer) in
1847 * stolen memory.
1848 *
1849 * We need to enable/disable FBC on a global basis.
1850 */
1851 static void intel_update_fbc(struct drm_device *dev)
1852 {
1853 struct drm_i915_private *dev_priv = dev->dev_private;
1854 struct drm_crtc *crtc = NULL, *tmp_crtc;
1855 struct intel_crtc *intel_crtc;
1856 struct drm_framebuffer *fb;
1857 struct intel_framebuffer *intel_fb;
1858 struct drm_i915_gem_object *obj;
1859 int enable_fbc;
1860
1861 DRM_DEBUG_KMS("\n");
1862
1863 if (!i915_powersave)
1864 return;
1865
1866 if (!I915_HAS_FBC(dev))
1867 return;
1868
1869 /*
1870 * If FBC is already on, we just have to verify that we can
1871 * keep it that way...
1872 * Need to disable if:
1873 * - more than one pipe is active
1874 * - changing FBC params (stride, fence, mode)
1875 * - new fb is too large to fit in compressed buffer
1876 * - going to an unsupported config (interlace, pixel multiply, etc.)
1877 */
1878 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1879 if (tmp_crtc->enabled && tmp_crtc->fb) {
1880 if (crtc) {
1881 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1882 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1883 goto out_disable;
1884 }
1885 crtc = tmp_crtc;
1886 }
1887 }
1888
1889 if (!crtc || crtc->fb == NULL) {
1890 DRM_DEBUG_KMS("no output, disabling\n");
1891 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1892 goto out_disable;
1893 }
1894
1895 intel_crtc = to_intel_crtc(crtc);
1896 fb = crtc->fb;
1897 intel_fb = to_intel_framebuffer(fb);
1898 obj = intel_fb->obj;
1899
1900 enable_fbc = i915_enable_fbc;
1901 if (enable_fbc < 0) {
1902 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1903 enable_fbc = 1;
1904 if (INTEL_INFO(dev)->gen <= 6)
1905 enable_fbc = 0;
1906 }
1907 if (!enable_fbc) {
1908 DRM_DEBUG_KMS("fbc disabled per module param\n");
1909 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1910 goto out_disable;
1911 }
1912 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1913 DRM_DEBUG_KMS("framebuffer too large, disabling "
1914 "compression\n");
1915 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1916 goto out_disable;
1917 }
1918 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1919 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1920 DRM_DEBUG_KMS("mode incompatible with compression, "
1921 "disabling\n");
1922 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1923 goto out_disable;
1924 }
1925 if ((crtc->mode.hdisplay > 2048) ||
1926 (crtc->mode.vdisplay > 1536)) {
1927 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1928 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1929 goto out_disable;
1930 }
1931 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1932 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1933 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1934 goto out_disable;
1935 }
1936
1937 /* The use of a CPU fence is mandatory in order to detect writes
1938 * by the CPU to the scanout and trigger updates to the FBC.
1939 */
1940 if (obj->tiling_mode != I915_TILING_X ||
1941 obj->fence_reg == I915_FENCE_REG_NONE) {
1942 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1943 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1944 goto out_disable;
1945 }
1946
1947 /* If the kernel debugger is active, always disable compression */
1948 if (in_dbg_master())
1949 goto out_disable;
1950
1951 /* If the scanout has not changed, don't modify the FBC settings.
1952 * Note that we make the fundamental assumption that the fb->obj
1953 * cannot be unpinned (and have its GTT offset and fence revoked)
1954 * without first being decoupled from the scanout and FBC disabled.
1955 */
1956 if (dev_priv->cfb_plane == intel_crtc->plane &&
1957 dev_priv->cfb_fb == fb->base.id &&
1958 dev_priv->cfb_y == crtc->y)
1959 return;
1960
1961 if (intel_fbc_enabled(dev)) {
1962 /* We update FBC along two paths, after changing fb/crtc
1963 * configuration (modeswitching) and after page-flipping
1964 * finishes. For the latter, we know that not only did
1965 * we disable the FBC at the start of the page-flip
1966 * sequence, but also more than one vblank has passed.
1967 *
1968 * For the former case of modeswitching, it is possible
1969 * to switch between two FBC valid configurations
1970 * instantaneously so we do need to disable the FBC
1971 * before we can modify its control registers. We also
1972 * have to wait for the next vblank for that to take
1973 * effect. However, since we delay enabling FBC we can
1974 * assume that a vblank has passed since disabling and
1975 * that we can safely alter the registers in the deferred
1976 * callback.
1977 *
1978 * In the scenario that we go from a valid to invalid
1979 * and then back to valid FBC configuration we have
1980 * no strict enforcement that a vblank occurred since
1981 * disabling the FBC. However, along all current pipe
1982 * disabling paths we do need to wait for a vblank at
1983 * some point. And we wait before enabling FBC anyway.
1984 */
1985 DRM_DEBUG_KMS("disabling active FBC for update\n");
1986 intel_disable_fbc(dev);
1987 }
1988
1989 intel_enable_fbc(crtc, 500);
1990 return;
1991
1992 out_disable:
1993 /* Multiple disables should be harmless */
1994 if (intel_fbc_enabled(dev)) {
1995 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1996 intel_disable_fbc(dev);
1997 }
1998 }
1999
2000 int
2001 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2002 struct drm_i915_gem_object *obj,
2003 struct intel_ring_buffer *pipelined)
2004 {
2005 struct drm_i915_private *dev_priv = dev->dev_private;
2006 u32 alignment;
2007 int ret;
2008
2009 switch (obj->tiling_mode) {
2010 case I915_TILING_NONE:
2011 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2012 alignment = 128 * 1024;
2013 else if (INTEL_INFO(dev)->gen >= 4)
2014 alignment = 4 * 1024;
2015 else
2016 alignment = 64 * 1024;
2017 break;
2018 case I915_TILING_X:
2019 /* pin() will align the object as required by fence */
2020 alignment = 0;
2021 break;
2022 case I915_TILING_Y:
2023 /* FIXME: Is this true? */
2024 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2025 return -EINVAL;
2026 default:
2027 BUG();
2028 }
2029
2030 dev_priv->mm.interruptible = false;
2031 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2032 if (ret)
2033 goto err_interruptible;
2034
2035 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2036 * fence, whereas 965+ only requires a fence if using
2037 * framebuffer compression. For simplicity, we always install
2038 * a fence as the cost is not that onerous.
2039 */
2040 if (obj->tiling_mode != I915_TILING_NONE) {
2041 ret = i915_gem_object_get_fence(obj, pipelined);
2042 if (ret)
2043 goto err_unpin;
2044
2045 i915_gem_object_pin_fence(obj);
2046 }
2047
2048 dev_priv->mm.interruptible = true;
2049 return 0;
2050
2051 err_unpin:
2052 i915_gem_object_unpin(obj);
2053 err_interruptible:
2054 dev_priv->mm.interruptible = true;
2055 return ret;
2056 }
2057
2058 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2059 {
2060 i915_gem_object_unpin_fence(obj);
2061 i915_gem_object_unpin(obj);
2062 }
2063
2064 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2065 int x, int y)
2066 {
2067 struct drm_device *dev = crtc->dev;
2068 struct drm_i915_private *dev_priv = dev->dev_private;
2069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2070 struct intel_framebuffer *intel_fb;
2071 struct drm_i915_gem_object *obj;
2072 int plane = intel_crtc->plane;
2073 unsigned long Start, Offset;
2074 u32 dspcntr;
2075 u32 reg;
2076
2077 switch (plane) {
2078 case 0:
2079 case 1:
2080 break;
2081 default:
2082 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2083 return -EINVAL;
2084 }
2085
2086 intel_fb = to_intel_framebuffer(fb);
2087 obj = intel_fb->obj;
2088
2089 reg = DSPCNTR(plane);
2090 dspcntr = I915_READ(reg);
2091 /* Mask out pixel format bits in case we change it */
2092 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2093 switch (fb->bits_per_pixel) {
2094 case 8:
2095 dspcntr |= DISPPLANE_8BPP;
2096 break;
2097 case 16:
2098 if (fb->depth == 15)
2099 dspcntr |= DISPPLANE_15_16BPP;
2100 else
2101 dspcntr |= DISPPLANE_16BPP;
2102 break;
2103 case 24:
2104 case 32:
2105 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2106 break;
2107 default:
2108 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2109 return -EINVAL;
2110 }
2111 if (INTEL_INFO(dev)->gen >= 4) {
2112 if (obj->tiling_mode != I915_TILING_NONE)
2113 dspcntr |= DISPPLANE_TILED;
2114 else
2115 dspcntr &= ~DISPPLANE_TILED;
2116 }
2117
2118 I915_WRITE(reg, dspcntr);
2119
2120 Start = obj->gtt_offset;
2121 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2122
2123 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2124 Start, Offset, x, y, fb->pitches[0]);
2125 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2126 if (INTEL_INFO(dev)->gen >= 4) {
2127 I915_WRITE(DSPSURF(plane), Start);
2128 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2129 I915_WRITE(DSPADDR(plane), Offset);
2130 } else
2131 I915_WRITE(DSPADDR(plane), Start + Offset);
2132 POSTING_READ(reg);
2133
2134 return 0;
2135 }
2136
2137 static int ironlake_update_plane(struct drm_crtc *crtc,
2138 struct drm_framebuffer *fb, int x, int y)
2139 {
2140 struct drm_device *dev = crtc->dev;
2141 struct drm_i915_private *dev_priv = dev->dev_private;
2142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2143 struct intel_framebuffer *intel_fb;
2144 struct drm_i915_gem_object *obj;
2145 int plane = intel_crtc->plane;
2146 unsigned long Start, Offset;
2147 u32 dspcntr;
2148 u32 reg;
2149
2150 switch (plane) {
2151 case 0:
2152 case 1:
2153 case 2:
2154 break;
2155 default:
2156 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2157 return -EINVAL;
2158 }
2159
2160 intel_fb = to_intel_framebuffer(fb);
2161 obj = intel_fb->obj;
2162
2163 reg = DSPCNTR(plane);
2164 dspcntr = I915_READ(reg);
2165 /* Mask out pixel format bits in case we change it */
2166 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2167 switch (fb->bits_per_pixel) {
2168 case 8:
2169 dspcntr |= DISPPLANE_8BPP;
2170 break;
2171 case 16:
2172 if (fb->depth != 16)
2173 return -EINVAL;
2174
2175 dspcntr |= DISPPLANE_16BPP;
2176 break;
2177 case 24:
2178 case 32:
2179 if (fb->depth == 24)
2180 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2181 else if (fb->depth == 30)
2182 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2183 else
2184 return -EINVAL;
2185 break;
2186 default:
2187 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2188 return -EINVAL;
2189 }
2190
2191 if (obj->tiling_mode != I915_TILING_NONE)
2192 dspcntr |= DISPPLANE_TILED;
2193 else
2194 dspcntr &= ~DISPPLANE_TILED;
2195
2196 /* must disable */
2197 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2198
2199 I915_WRITE(reg, dspcntr);
2200
2201 Start = obj->gtt_offset;
2202 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2203
2204 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2205 Start, Offset, x, y, fb->pitches[0]);
2206 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2207 I915_WRITE(DSPSURF(plane), Start);
2208 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2209 I915_WRITE(DSPADDR(plane), Offset);
2210 POSTING_READ(reg);
2211
2212 return 0;
2213 }
2214
2215 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2216 static int
2217 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2218 int x, int y, enum mode_set_atomic state)
2219 {
2220 struct drm_device *dev = crtc->dev;
2221 struct drm_i915_private *dev_priv = dev->dev_private;
2222 int ret;
2223
2224 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2225 if (ret)
2226 return ret;
2227
2228 intel_update_fbc(dev);
2229 intel_increase_pllclock(crtc);
2230
2231 return 0;
2232 }
2233
2234 static int
2235 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2236 struct drm_framebuffer *old_fb)
2237 {
2238 struct drm_device *dev = crtc->dev;
2239 struct drm_i915_master_private *master_priv;
2240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2241 int ret;
2242
2243 /* no fb bound */
2244 if (!crtc->fb) {
2245 DRM_ERROR("No FB bound\n");
2246 return 0;
2247 }
2248
2249 switch (intel_crtc->plane) {
2250 case 0:
2251 case 1:
2252 break;
2253 case 2:
2254 if (IS_IVYBRIDGE(dev))
2255 break;
2256 /* fall through otherwise */
2257 default:
2258 DRM_ERROR("no plane for crtc\n");
2259 return -EINVAL;
2260 }
2261
2262 mutex_lock(&dev->struct_mutex);
2263 ret = intel_pin_and_fence_fb_obj(dev,
2264 to_intel_framebuffer(crtc->fb)->obj,
2265 NULL);
2266 if (ret != 0) {
2267 mutex_unlock(&dev->struct_mutex);
2268 DRM_ERROR("pin & fence failed\n");
2269 return ret;
2270 }
2271
2272 if (old_fb) {
2273 struct drm_i915_private *dev_priv = dev->dev_private;
2274 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2275
2276 wait_event(dev_priv->pending_flip_queue,
2277 atomic_read(&dev_priv->mm.wedged) ||
2278 atomic_read(&obj->pending_flip) == 0);
2279
2280 /* Big Hammer, we also need to ensure that any pending
2281 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2282 * current scanout is retired before unpinning the old
2283 * framebuffer.
2284 *
2285 * This should only fail upon a hung GPU, in which case we
2286 * can safely continue.
2287 */
2288 ret = i915_gem_object_finish_gpu(obj);
2289 (void) ret;
2290 }
2291
2292 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2293 LEAVE_ATOMIC_MODE_SET);
2294 if (ret) {
2295 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2296 mutex_unlock(&dev->struct_mutex);
2297 DRM_ERROR("failed to update base address\n");
2298 return ret;
2299 }
2300
2301 if (old_fb) {
2302 intel_wait_for_vblank(dev, intel_crtc->pipe);
2303 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2304 }
2305
2306 mutex_unlock(&dev->struct_mutex);
2307
2308 if (!dev->primary->master)
2309 return 0;
2310
2311 master_priv = dev->primary->master->driver_priv;
2312 if (!master_priv->sarea_priv)
2313 return 0;
2314
2315 if (intel_crtc->pipe) {
2316 master_priv->sarea_priv->pipeB_x = x;
2317 master_priv->sarea_priv->pipeB_y = y;
2318 } else {
2319 master_priv->sarea_priv->pipeA_x = x;
2320 master_priv->sarea_priv->pipeA_y = y;
2321 }
2322
2323 return 0;
2324 }
2325
2326 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2327 {
2328 struct drm_device *dev = crtc->dev;
2329 struct drm_i915_private *dev_priv = dev->dev_private;
2330 u32 dpa_ctl;
2331
2332 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2333 dpa_ctl = I915_READ(DP_A);
2334 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2335
2336 if (clock < 200000) {
2337 u32 temp;
2338 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2339 /* workaround for 160Mhz:
2340 1) program 0x4600c bits 15:0 = 0x8124
2341 2) program 0x46010 bit 0 = 1
2342 3) program 0x46034 bit 24 = 1
2343 4) program 0x64000 bit 14 = 1
2344 */
2345 temp = I915_READ(0x4600c);
2346 temp &= 0xffff0000;
2347 I915_WRITE(0x4600c, temp | 0x8124);
2348
2349 temp = I915_READ(0x46010);
2350 I915_WRITE(0x46010, temp | 1);
2351
2352 temp = I915_READ(0x46034);
2353 I915_WRITE(0x46034, temp | (1 << 24));
2354 } else {
2355 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2356 }
2357 I915_WRITE(DP_A, dpa_ctl);
2358
2359 POSTING_READ(DP_A);
2360 udelay(500);
2361 }
2362
2363 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2364 {
2365 struct drm_device *dev = crtc->dev;
2366 struct drm_i915_private *dev_priv = dev->dev_private;
2367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2368 int pipe = intel_crtc->pipe;
2369 u32 reg, temp;
2370
2371 /* enable normal train */
2372 reg = FDI_TX_CTL(pipe);
2373 temp = I915_READ(reg);
2374 if (IS_IVYBRIDGE(dev)) {
2375 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2376 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2377 } else {
2378 temp &= ~FDI_LINK_TRAIN_NONE;
2379 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2380 }
2381 I915_WRITE(reg, temp);
2382
2383 reg = FDI_RX_CTL(pipe);
2384 temp = I915_READ(reg);
2385 if (HAS_PCH_CPT(dev)) {
2386 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2387 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2388 } else {
2389 temp &= ~FDI_LINK_TRAIN_NONE;
2390 temp |= FDI_LINK_TRAIN_NONE;
2391 }
2392 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2393
2394 /* wait one idle pattern time */
2395 POSTING_READ(reg);
2396 udelay(1000);
2397
2398 /* IVB wants error correction enabled */
2399 if (IS_IVYBRIDGE(dev))
2400 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2401 FDI_FE_ERRC_ENABLE);
2402 }
2403
2404 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2405 {
2406 struct drm_i915_private *dev_priv = dev->dev_private;
2407 u32 flags = I915_READ(SOUTH_CHICKEN1);
2408
2409 flags |= FDI_PHASE_SYNC_OVR(pipe);
2410 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2411 flags |= FDI_PHASE_SYNC_EN(pipe);
2412 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2413 POSTING_READ(SOUTH_CHICKEN1);
2414 }
2415
2416 /* The FDI link training functions for ILK/Ibexpeak. */
2417 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2418 {
2419 struct drm_device *dev = crtc->dev;
2420 struct drm_i915_private *dev_priv = dev->dev_private;
2421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2422 int pipe = intel_crtc->pipe;
2423 int plane = intel_crtc->plane;
2424 u32 reg, temp, tries;
2425
2426 /* FDI needs bits from pipe & plane first */
2427 assert_pipe_enabled(dev_priv, pipe);
2428 assert_plane_enabled(dev_priv, plane);
2429
2430 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2431 for train result */
2432 reg = FDI_RX_IMR(pipe);
2433 temp = I915_READ(reg);
2434 temp &= ~FDI_RX_SYMBOL_LOCK;
2435 temp &= ~FDI_RX_BIT_LOCK;
2436 I915_WRITE(reg, temp);
2437 I915_READ(reg);
2438 udelay(150);
2439
2440 /* enable CPU FDI TX and PCH FDI RX */
2441 reg = FDI_TX_CTL(pipe);
2442 temp = I915_READ(reg);
2443 temp &= ~(7 << 19);
2444 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2445 temp &= ~FDI_LINK_TRAIN_NONE;
2446 temp |= FDI_LINK_TRAIN_PATTERN_1;
2447 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2448
2449 reg = FDI_RX_CTL(pipe);
2450 temp = I915_READ(reg);
2451 temp &= ~FDI_LINK_TRAIN_NONE;
2452 temp |= FDI_LINK_TRAIN_PATTERN_1;
2453 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2454
2455 POSTING_READ(reg);
2456 udelay(150);
2457
2458 /* Ironlake workaround, enable clock pointer after FDI enable*/
2459 if (HAS_PCH_IBX(dev)) {
2460 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2461 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2462 FDI_RX_PHASE_SYNC_POINTER_EN);
2463 }
2464
2465 reg = FDI_RX_IIR(pipe);
2466 for (tries = 0; tries < 5; tries++) {
2467 temp = I915_READ(reg);
2468 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2469
2470 if ((temp & FDI_RX_BIT_LOCK)) {
2471 DRM_DEBUG_KMS("FDI train 1 done.\n");
2472 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2473 break;
2474 }
2475 }
2476 if (tries == 5)
2477 DRM_ERROR("FDI train 1 fail!\n");
2478
2479 /* Train 2 */
2480 reg = FDI_TX_CTL(pipe);
2481 temp = I915_READ(reg);
2482 temp &= ~FDI_LINK_TRAIN_NONE;
2483 temp |= FDI_LINK_TRAIN_PATTERN_2;
2484 I915_WRITE(reg, temp);
2485
2486 reg = FDI_RX_CTL(pipe);
2487 temp = I915_READ(reg);
2488 temp &= ~FDI_LINK_TRAIN_NONE;
2489 temp |= FDI_LINK_TRAIN_PATTERN_2;
2490 I915_WRITE(reg, temp);
2491
2492 POSTING_READ(reg);
2493 udelay(150);
2494
2495 reg = FDI_RX_IIR(pipe);
2496 for (tries = 0; tries < 5; tries++) {
2497 temp = I915_READ(reg);
2498 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2499
2500 if (temp & FDI_RX_SYMBOL_LOCK) {
2501 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2502 DRM_DEBUG_KMS("FDI train 2 done.\n");
2503 break;
2504 }
2505 }
2506 if (tries == 5)
2507 DRM_ERROR("FDI train 2 fail!\n");
2508
2509 DRM_DEBUG_KMS("FDI train done\n");
2510
2511 }
2512
2513 static const int snb_b_fdi_train_param[] = {
2514 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2515 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2516 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2517 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2518 };
2519
2520 /* The FDI link training functions for SNB/Cougarpoint. */
2521 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2522 {
2523 struct drm_device *dev = crtc->dev;
2524 struct drm_i915_private *dev_priv = dev->dev_private;
2525 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2526 int pipe = intel_crtc->pipe;
2527 u32 reg, temp, i;
2528
2529 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2530 for train result */
2531 reg = FDI_RX_IMR(pipe);
2532 temp = I915_READ(reg);
2533 temp &= ~FDI_RX_SYMBOL_LOCK;
2534 temp &= ~FDI_RX_BIT_LOCK;
2535 I915_WRITE(reg, temp);
2536
2537 POSTING_READ(reg);
2538 udelay(150);
2539
2540 /* enable CPU FDI TX and PCH FDI RX */
2541 reg = FDI_TX_CTL(pipe);
2542 temp = I915_READ(reg);
2543 temp &= ~(7 << 19);
2544 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2545 temp &= ~FDI_LINK_TRAIN_NONE;
2546 temp |= FDI_LINK_TRAIN_PATTERN_1;
2547 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2548 /* SNB-B */
2549 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2550 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2551
2552 reg = FDI_RX_CTL(pipe);
2553 temp = I915_READ(reg);
2554 if (HAS_PCH_CPT(dev)) {
2555 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2556 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2557 } else {
2558 temp &= ~FDI_LINK_TRAIN_NONE;
2559 temp |= FDI_LINK_TRAIN_PATTERN_1;
2560 }
2561 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2562
2563 POSTING_READ(reg);
2564 udelay(150);
2565
2566 if (HAS_PCH_CPT(dev))
2567 cpt_phase_pointer_enable(dev, pipe);
2568
2569 for (i = 0; i < 4; i++) {
2570 reg = FDI_TX_CTL(pipe);
2571 temp = I915_READ(reg);
2572 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2573 temp |= snb_b_fdi_train_param[i];
2574 I915_WRITE(reg, temp);
2575
2576 POSTING_READ(reg);
2577 udelay(500);
2578
2579 reg = FDI_RX_IIR(pipe);
2580 temp = I915_READ(reg);
2581 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2582
2583 if (temp & FDI_RX_BIT_LOCK) {
2584 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2585 DRM_DEBUG_KMS("FDI train 1 done.\n");
2586 break;
2587 }
2588 }
2589 if (i == 4)
2590 DRM_ERROR("FDI train 1 fail!\n");
2591
2592 /* Train 2 */
2593 reg = FDI_TX_CTL(pipe);
2594 temp = I915_READ(reg);
2595 temp &= ~FDI_LINK_TRAIN_NONE;
2596 temp |= FDI_LINK_TRAIN_PATTERN_2;
2597 if (IS_GEN6(dev)) {
2598 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2599 /* SNB-B */
2600 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2601 }
2602 I915_WRITE(reg, temp);
2603
2604 reg = FDI_RX_CTL(pipe);
2605 temp = I915_READ(reg);
2606 if (HAS_PCH_CPT(dev)) {
2607 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2608 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2609 } else {
2610 temp &= ~FDI_LINK_TRAIN_NONE;
2611 temp |= FDI_LINK_TRAIN_PATTERN_2;
2612 }
2613 I915_WRITE(reg, temp);
2614
2615 POSTING_READ(reg);
2616 udelay(150);
2617
2618 for (i = 0; i < 4; i++) {
2619 reg = FDI_TX_CTL(pipe);
2620 temp = I915_READ(reg);
2621 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2622 temp |= snb_b_fdi_train_param[i];
2623 I915_WRITE(reg, temp);
2624
2625 POSTING_READ(reg);
2626 udelay(500);
2627
2628 reg = FDI_RX_IIR(pipe);
2629 temp = I915_READ(reg);
2630 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2631
2632 if (temp & FDI_RX_SYMBOL_LOCK) {
2633 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2634 DRM_DEBUG_KMS("FDI train 2 done.\n");
2635 break;
2636 }
2637 }
2638 if (i == 4)
2639 DRM_ERROR("FDI train 2 fail!\n");
2640
2641 DRM_DEBUG_KMS("FDI train done.\n");
2642 }
2643
2644 /* Manual link training for Ivy Bridge A0 parts */
2645 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2646 {
2647 struct drm_device *dev = crtc->dev;
2648 struct drm_i915_private *dev_priv = dev->dev_private;
2649 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2650 int pipe = intel_crtc->pipe;
2651 u32 reg, temp, i;
2652
2653 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2654 for train result */
2655 reg = FDI_RX_IMR(pipe);
2656 temp = I915_READ(reg);
2657 temp &= ~FDI_RX_SYMBOL_LOCK;
2658 temp &= ~FDI_RX_BIT_LOCK;
2659 I915_WRITE(reg, temp);
2660
2661 POSTING_READ(reg);
2662 udelay(150);
2663
2664 /* enable CPU FDI TX and PCH FDI RX */
2665 reg = FDI_TX_CTL(pipe);
2666 temp = I915_READ(reg);
2667 temp &= ~(7 << 19);
2668 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2669 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2670 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2671 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2672 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2673 temp |= FDI_COMPOSITE_SYNC;
2674 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2675
2676 reg = FDI_RX_CTL(pipe);
2677 temp = I915_READ(reg);
2678 temp &= ~FDI_LINK_TRAIN_AUTO;
2679 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2680 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2681 temp |= FDI_COMPOSITE_SYNC;
2682 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2683
2684 POSTING_READ(reg);
2685 udelay(150);
2686
2687 if (HAS_PCH_CPT(dev))
2688 cpt_phase_pointer_enable(dev, pipe);
2689
2690 for (i = 0; i < 4; i++) {
2691 reg = FDI_TX_CTL(pipe);
2692 temp = I915_READ(reg);
2693 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2694 temp |= snb_b_fdi_train_param[i];
2695 I915_WRITE(reg, temp);
2696
2697 POSTING_READ(reg);
2698 udelay(500);
2699
2700 reg = FDI_RX_IIR(pipe);
2701 temp = I915_READ(reg);
2702 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2703
2704 if (temp & FDI_RX_BIT_LOCK ||
2705 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2706 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2707 DRM_DEBUG_KMS("FDI train 1 done.\n");
2708 break;
2709 }
2710 }
2711 if (i == 4)
2712 DRM_ERROR("FDI train 1 fail!\n");
2713
2714 /* Train 2 */
2715 reg = FDI_TX_CTL(pipe);
2716 temp = I915_READ(reg);
2717 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2718 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2719 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2720 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2721 I915_WRITE(reg, temp);
2722
2723 reg = FDI_RX_CTL(pipe);
2724 temp = I915_READ(reg);
2725 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2726 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2727 I915_WRITE(reg, temp);
2728
2729 POSTING_READ(reg);
2730 udelay(150);
2731
2732 for (i = 0; i < 4; i++) {
2733 reg = FDI_TX_CTL(pipe);
2734 temp = I915_READ(reg);
2735 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2736 temp |= snb_b_fdi_train_param[i];
2737 I915_WRITE(reg, temp);
2738
2739 POSTING_READ(reg);
2740 udelay(500);
2741
2742 reg = FDI_RX_IIR(pipe);
2743 temp = I915_READ(reg);
2744 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2745
2746 if (temp & FDI_RX_SYMBOL_LOCK) {
2747 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2748 DRM_DEBUG_KMS("FDI train 2 done.\n");
2749 break;
2750 }
2751 }
2752 if (i == 4)
2753 DRM_ERROR("FDI train 2 fail!\n");
2754
2755 DRM_DEBUG_KMS("FDI train done.\n");
2756 }
2757
2758 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2759 {
2760 struct drm_device *dev = crtc->dev;
2761 struct drm_i915_private *dev_priv = dev->dev_private;
2762 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2763 int pipe = intel_crtc->pipe;
2764 u32 reg, temp;
2765
2766 /* Write the TU size bits so error detection works */
2767 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2768 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2769
2770 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2771 reg = FDI_RX_CTL(pipe);
2772 temp = I915_READ(reg);
2773 temp &= ~((0x7 << 19) | (0x7 << 16));
2774 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2775 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2776 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2777
2778 POSTING_READ(reg);
2779 udelay(200);
2780
2781 /* Switch from Rawclk to PCDclk */
2782 temp = I915_READ(reg);
2783 I915_WRITE(reg, temp | FDI_PCDCLK);
2784
2785 POSTING_READ(reg);
2786 udelay(200);
2787
2788 /* Enable CPU FDI TX PLL, always on for Ironlake */
2789 reg = FDI_TX_CTL(pipe);
2790 temp = I915_READ(reg);
2791 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2792 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2793
2794 POSTING_READ(reg);
2795 udelay(100);
2796 }
2797 }
2798
2799 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2800 {
2801 struct drm_i915_private *dev_priv = dev->dev_private;
2802 u32 flags = I915_READ(SOUTH_CHICKEN1);
2803
2804 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2805 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2806 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2807 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2808 POSTING_READ(SOUTH_CHICKEN1);
2809 }
2810 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2811 {
2812 struct drm_device *dev = crtc->dev;
2813 struct drm_i915_private *dev_priv = dev->dev_private;
2814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2815 int pipe = intel_crtc->pipe;
2816 u32 reg, temp;
2817
2818 /* disable CPU FDI tx and PCH FDI rx */
2819 reg = FDI_TX_CTL(pipe);
2820 temp = I915_READ(reg);
2821 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2822 POSTING_READ(reg);
2823
2824 reg = FDI_RX_CTL(pipe);
2825 temp = I915_READ(reg);
2826 temp &= ~(0x7 << 16);
2827 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2828 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2829
2830 POSTING_READ(reg);
2831 udelay(100);
2832
2833 /* Ironlake workaround, disable clock pointer after downing FDI */
2834 if (HAS_PCH_IBX(dev)) {
2835 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2836 I915_WRITE(FDI_RX_CHICKEN(pipe),
2837 I915_READ(FDI_RX_CHICKEN(pipe) &
2838 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2839 } else if (HAS_PCH_CPT(dev)) {
2840 cpt_phase_pointer_disable(dev, pipe);
2841 }
2842
2843 /* still set train pattern 1 */
2844 reg = FDI_TX_CTL(pipe);
2845 temp = I915_READ(reg);
2846 temp &= ~FDI_LINK_TRAIN_NONE;
2847 temp |= FDI_LINK_TRAIN_PATTERN_1;
2848 I915_WRITE(reg, temp);
2849
2850 reg = FDI_RX_CTL(pipe);
2851 temp = I915_READ(reg);
2852 if (HAS_PCH_CPT(dev)) {
2853 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2854 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2855 } else {
2856 temp &= ~FDI_LINK_TRAIN_NONE;
2857 temp |= FDI_LINK_TRAIN_PATTERN_1;
2858 }
2859 /* BPC in FDI rx is consistent with that in PIPECONF */
2860 temp &= ~(0x07 << 16);
2861 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2862 I915_WRITE(reg, temp);
2863
2864 POSTING_READ(reg);
2865 udelay(100);
2866 }
2867
2868 /*
2869 * When we disable a pipe, we need to clear any pending scanline wait events
2870 * to avoid hanging the ring, which we assume we are waiting on.
2871 */
2872 static void intel_clear_scanline_wait(struct drm_device *dev)
2873 {
2874 struct drm_i915_private *dev_priv = dev->dev_private;
2875 struct intel_ring_buffer *ring;
2876 u32 tmp;
2877
2878 if (IS_GEN2(dev))
2879 /* Can't break the hang on i8xx */
2880 return;
2881
2882 ring = LP_RING(dev_priv);
2883 tmp = I915_READ_CTL(ring);
2884 if (tmp & RING_WAIT)
2885 I915_WRITE_CTL(ring, tmp);
2886 }
2887
2888 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2889 {
2890 struct drm_i915_gem_object *obj;
2891 struct drm_i915_private *dev_priv;
2892
2893 if (crtc->fb == NULL)
2894 return;
2895
2896 obj = to_intel_framebuffer(crtc->fb)->obj;
2897 dev_priv = crtc->dev->dev_private;
2898 wait_event(dev_priv->pending_flip_queue,
2899 atomic_read(&obj->pending_flip) == 0);
2900 }
2901
2902 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2903 {
2904 struct drm_device *dev = crtc->dev;
2905 struct drm_mode_config *mode_config = &dev->mode_config;
2906 struct intel_encoder *encoder;
2907
2908 /*
2909 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2910 * must be driven by its own crtc; no sharing is possible.
2911 */
2912 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2913 if (encoder->base.crtc != crtc)
2914 continue;
2915
2916 switch (encoder->type) {
2917 case INTEL_OUTPUT_EDP:
2918 if (!intel_encoder_is_pch_edp(&encoder->base))
2919 return false;
2920 continue;
2921 }
2922 }
2923
2924 return true;
2925 }
2926
2927 /*
2928 * Enable PCH resources required for PCH ports:
2929 * - PCH PLLs
2930 * - FDI training & RX/TX
2931 * - update transcoder timings
2932 * - DP transcoding bits
2933 * - transcoder
2934 */
2935 static void ironlake_pch_enable(struct drm_crtc *crtc)
2936 {
2937 struct drm_device *dev = crtc->dev;
2938 struct drm_i915_private *dev_priv = dev->dev_private;
2939 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2940 int pipe = intel_crtc->pipe;
2941 u32 reg, temp, transc_sel;
2942
2943 /* For PCH output, training FDI link */
2944 dev_priv->display.fdi_link_train(crtc);
2945
2946 intel_enable_pch_pll(dev_priv, pipe);
2947
2948 if (HAS_PCH_CPT(dev)) {
2949 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2950 TRANSC_DPLLB_SEL;
2951
2952 /* Be sure PCH DPLL SEL is set */
2953 temp = I915_READ(PCH_DPLL_SEL);
2954 if (pipe == 0) {
2955 temp &= ~(TRANSA_DPLLB_SEL);
2956 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2957 } else if (pipe == 1) {
2958 temp &= ~(TRANSB_DPLLB_SEL);
2959 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2960 } else if (pipe == 2) {
2961 temp &= ~(TRANSC_DPLLB_SEL);
2962 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
2963 }
2964 I915_WRITE(PCH_DPLL_SEL, temp);
2965 }
2966
2967 /* set transcoder timing, panel must allow it */
2968 assert_panel_unlocked(dev_priv, pipe);
2969 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2970 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2971 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2972
2973 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2974 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2975 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2976
2977 intel_fdi_normal_train(crtc);
2978
2979 /* For PCH DP, enable TRANS_DP_CTL */
2980 if (HAS_PCH_CPT(dev) &&
2981 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2982 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2983 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2984 reg = TRANS_DP_CTL(pipe);
2985 temp = I915_READ(reg);
2986 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2987 TRANS_DP_SYNC_MASK |
2988 TRANS_DP_BPC_MASK);
2989 temp |= (TRANS_DP_OUTPUT_ENABLE |
2990 TRANS_DP_ENH_FRAMING);
2991 temp |= bpc << 9; /* same format but at 11:9 */
2992
2993 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2994 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2995 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2996 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2997
2998 switch (intel_trans_dp_port_sel(crtc)) {
2999 case PCH_DP_B:
3000 temp |= TRANS_DP_PORT_SEL_B;
3001 break;
3002 case PCH_DP_C:
3003 temp |= TRANS_DP_PORT_SEL_C;
3004 break;
3005 case PCH_DP_D:
3006 temp |= TRANS_DP_PORT_SEL_D;
3007 break;
3008 default:
3009 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3010 temp |= TRANS_DP_PORT_SEL_B;
3011 break;
3012 }
3013
3014 I915_WRITE(reg, temp);
3015 }
3016
3017 intel_enable_transcoder(dev_priv, pipe);
3018 }
3019
3020 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3021 {
3022 struct drm_i915_private *dev_priv = dev->dev_private;
3023 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3024 u32 temp;
3025
3026 temp = I915_READ(dslreg);
3027 udelay(500);
3028 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3029 /* Without this, mode sets may fail silently on FDI */
3030 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3031 udelay(250);
3032 I915_WRITE(tc2reg, 0);
3033 if (wait_for(I915_READ(dslreg) != temp, 5))
3034 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3035 }
3036 }
3037
3038 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3039 {
3040 struct drm_device *dev = crtc->dev;
3041 struct drm_i915_private *dev_priv = dev->dev_private;
3042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3043 int pipe = intel_crtc->pipe;
3044 int plane = intel_crtc->plane;
3045 u32 temp;
3046 bool is_pch_port;
3047
3048 if (intel_crtc->active)
3049 return;
3050
3051 intel_crtc->active = true;
3052 intel_update_watermarks(dev);
3053
3054 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3055 temp = I915_READ(PCH_LVDS);
3056 if ((temp & LVDS_PORT_EN) == 0)
3057 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3058 }
3059
3060 is_pch_port = intel_crtc_driving_pch(crtc);
3061
3062 if (is_pch_port)
3063 ironlake_fdi_pll_enable(crtc);
3064 else
3065 ironlake_fdi_disable(crtc);
3066
3067 /* Enable panel fitting for LVDS */
3068 if (dev_priv->pch_pf_size &&
3069 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3070 /* Force use of hard-coded filter coefficients
3071 * as some pre-programmed values are broken,
3072 * e.g. x201.
3073 */
3074 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3075 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3076 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3077 }
3078
3079 /*
3080 * On ILK+ LUT must be loaded before the pipe is running but with
3081 * clocks enabled
3082 */
3083 intel_crtc_load_lut(crtc);
3084
3085 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3086 intel_enable_plane(dev_priv, plane, pipe);
3087
3088 if (is_pch_port)
3089 ironlake_pch_enable(crtc);
3090
3091 mutex_lock(&dev->struct_mutex);
3092 intel_update_fbc(dev);
3093 mutex_unlock(&dev->struct_mutex);
3094
3095 intel_crtc_update_cursor(crtc, true);
3096 }
3097
3098 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3099 {
3100 struct drm_device *dev = crtc->dev;
3101 struct drm_i915_private *dev_priv = dev->dev_private;
3102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3103 int pipe = intel_crtc->pipe;
3104 int plane = intel_crtc->plane;
3105 u32 reg, temp;
3106
3107 if (!intel_crtc->active)
3108 return;
3109
3110 intel_crtc_wait_for_pending_flips(crtc);
3111 drm_vblank_off(dev, pipe);
3112 intel_crtc_update_cursor(crtc, false);
3113
3114 intel_disable_plane(dev_priv, plane, pipe);
3115
3116 if (dev_priv->cfb_plane == plane)
3117 intel_disable_fbc(dev);
3118
3119 intel_disable_pipe(dev_priv, pipe);
3120
3121 /* Disable PF */
3122 I915_WRITE(PF_CTL(pipe), 0);
3123 I915_WRITE(PF_WIN_SZ(pipe), 0);
3124
3125 ironlake_fdi_disable(crtc);
3126
3127 /* This is a horrible layering violation; we should be doing this in
3128 * the connector/encoder ->prepare instead, but we don't always have
3129 * enough information there about the config to know whether it will
3130 * actually be necessary or just cause undesired flicker.
3131 */
3132 intel_disable_pch_ports(dev_priv, pipe);
3133
3134 intel_disable_transcoder(dev_priv, pipe);
3135
3136 if (HAS_PCH_CPT(dev)) {
3137 /* disable TRANS_DP_CTL */
3138 reg = TRANS_DP_CTL(pipe);
3139 temp = I915_READ(reg);
3140 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3141 temp |= TRANS_DP_PORT_SEL_NONE;
3142 I915_WRITE(reg, temp);
3143
3144 /* disable DPLL_SEL */
3145 temp = I915_READ(PCH_DPLL_SEL);
3146 switch (pipe) {
3147 case 0:
3148 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3149 break;
3150 case 1:
3151 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3152 break;
3153 case 2:
3154 /* C shares PLL A or B */
3155 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3156 break;
3157 default:
3158 BUG(); /* wtf */
3159 }
3160 I915_WRITE(PCH_DPLL_SEL, temp);
3161 }
3162
3163 /* disable PCH DPLL */
3164 if (!intel_crtc->no_pll)
3165 intel_disable_pch_pll(dev_priv, pipe);
3166
3167 /* Switch from PCDclk to Rawclk */
3168 reg = FDI_RX_CTL(pipe);
3169 temp = I915_READ(reg);
3170 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3171
3172 /* Disable CPU FDI TX PLL */
3173 reg = FDI_TX_CTL(pipe);
3174 temp = I915_READ(reg);
3175 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3176
3177 POSTING_READ(reg);
3178 udelay(100);
3179
3180 reg = FDI_RX_CTL(pipe);
3181 temp = I915_READ(reg);
3182 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3183
3184 /* Wait for the clocks to turn off. */
3185 POSTING_READ(reg);
3186 udelay(100);
3187
3188 intel_crtc->active = false;
3189 intel_update_watermarks(dev);
3190
3191 mutex_lock(&dev->struct_mutex);
3192 intel_update_fbc(dev);
3193 intel_clear_scanline_wait(dev);
3194 mutex_unlock(&dev->struct_mutex);
3195 }
3196
3197 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3198 {
3199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3200 int pipe = intel_crtc->pipe;
3201 int plane = intel_crtc->plane;
3202
3203 /* XXX: When our outputs are all unaware of DPMS modes other than off
3204 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3205 */
3206 switch (mode) {
3207 case DRM_MODE_DPMS_ON:
3208 case DRM_MODE_DPMS_STANDBY:
3209 case DRM_MODE_DPMS_SUSPEND:
3210 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3211 ironlake_crtc_enable(crtc);
3212 break;
3213
3214 case DRM_MODE_DPMS_OFF:
3215 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3216 ironlake_crtc_disable(crtc);
3217 break;
3218 }
3219 }
3220
3221 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3222 {
3223 if (!enable && intel_crtc->overlay) {
3224 struct drm_device *dev = intel_crtc->base.dev;
3225 struct drm_i915_private *dev_priv = dev->dev_private;
3226
3227 mutex_lock(&dev->struct_mutex);
3228 dev_priv->mm.interruptible = false;
3229 (void) intel_overlay_switch_off(intel_crtc->overlay);
3230 dev_priv->mm.interruptible = true;
3231 mutex_unlock(&dev->struct_mutex);
3232 }
3233
3234 /* Let userspace switch the overlay on again. In most cases userspace
3235 * has to recompute where to put it anyway.
3236 */
3237 }
3238
3239 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3240 {
3241 struct drm_device *dev = crtc->dev;
3242 struct drm_i915_private *dev_priv = dev->dev_private;
3243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3244 int pipe = intel_crtc->pipe;
3245 int plane = intel_crtc->plane;
3246
3247 if (intel_crtc->active)
3248 return;
3249
3250 intel_crtc->active = true;
3251 intel_update_watermarks(dev);
3252
3253 intel_enable_pll(dev_priv, pipe);
3254 intel_enable_pipe(dev_priv, pipe, false);
3255 intel_enable_plane(dev_priv, plane, pipe);
3256
3257 intel_crtc_load_lut(crtc);
3258 intel_update_fbc(dev);
3259
3260 /* Give the overlay scaler a chance to enable if it's on this pipe */
3261 intel_crtc_dpms_overlay(intel_crtc, true);
3262 intel_crtc_update_cursor(crtc, true);
3263 }
3264
3265 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3266 {
3267 struct drm_device *dev = crtc->dev;
3268 struct drm_i915_private *dev_priv = dev->dev_private;
3269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3270 int pipe = intel_crtc->pipe;
3271 int plane = intel_crtc->plane;
3272
3273 if (!intel_crtc->active)
3274 return;
3275
3276 /* Give the overlay scaler a chance to disable if it's on this pipe */
3277 intel_crtc_wait_for_pending_flips(crtc);
3278 drm_vblank_off(dev, pipe);
3279 intel_crtc_dpms_overlay(intel_crtc, false);
3280 intel_crtc_update_cursor(crtc, false);
3281
3282 if (dev_priv->cfb_plane == plane)
3283 intel_disable_fbc(dev);
3284
3285 intel_disable_plane(dev_priv, plane, pipe);
3286 intel_disable_pipe(dev_priv, pipe);
3287 intel_disable_pll(dev_priv, pipe);
3288
3289 intel_crtc->active = false;
3290 intel_update_fbc(dev);
3291 intel_update_watermarks(dev);
3292 intel_clear_scanline_wait(dev);
3293 }
3294
3295 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3296 {
3297 /* XXX: When our outputs are all unaware of DPMS modes other than off
3298 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3299 */
3300 switch (mode) {
3301 case DRM_MODE_DPMS_ON:
3302 case DRM_MODE_DPMS_STANDBY:
3303 case DRM_MODE_DPMS_SUSPEND:
3304 i9xx_crtc_enable(crtc);
3305 break;
3306 case DRM_MODE_DPMS_OFF:
3307 i9xx_crtc_disable(crtc);
3308 break;
3309 }
3310 }
3311
3312 /**
3313 * Sets the power management mode of the pipe and plane.
3314 */
3315 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3316 {
3317 struct drm_device *dev = crtc->dev;
3318 struct drm_i915_private *dev_priv = dev->dev_private;
3319 struct drm_i915_master_private *master_priv;
3320 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3321 int pipe = intel_crtc->pipe;
3322 bool enabled;
3323
3324 if (intel_crtc->dpms_mode == mode)
3325 return;
3326
3327 intel_crtc->dpms_mode = mode;
3328
3329 dev_priv->display.dpms(crtc, mode);
3330
3331 if (!dev->primary->master)
3332 return;
3333
3334 master_priv = dev->primary->master->driver_priv;
3335 if (!master_priv->sarea_priv)
3336 return;
3337
3338 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3339
3340 switch (pipe) {
3341 case 0:
3342 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3343 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3344 break;
3345 case 1:
3346 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3347 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3348 break;
3349 default:
3350 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3351 break;
3352 }
3353 }
3354
3355 static void intel_crtc_disable(struct drm_crtc *crtc)
3356 {
3357 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3358 struct drm_device *dev = crtc->dev;
3359
3360 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3361 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3362 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3363
3364 if (crtc->fb) {
3365 mutex_lock(&dev->struct_mutex);
3366 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3367 mutex_unlock(&dev->struct_mutex);
3368 }
3369 }
3370
3371 /* Prepare for a mode set.
3372 *
3373 * Note we could be a lot smarter here. We need to figure out which outputs
3374 * will be enabled, which disabled (in short, how the config will changes)
3375 * and perform the minimum necessary steps to accomplish that, e.g. updating
3376 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3377 * panel fitting is in the proper state, etc.
3378 */
3379 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3380 {
3381 i9xx_crtc_disable(crtc);
3382 }
3383
3384 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3385 {
3386 i9xx_crtc_enable(crtc);
3387 }
3388
3389 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3390 {
3391 ironlake_crtc_disable(crtc);
3392 }
3393
3394 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3395 {
3396 ironlake_crtc_enable(crtc);
3397 }
3398
3399 void intel_encoder_prepare(struct drm_encoder *encoder)
3400 {
3401 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3402 /* lvds has its own version of prepare see intel_lvds_prepare */
3403 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3404 }
3405
3406 void intel_encoder_commit(struct drm_encoder *encoder)
3407 {
3408 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3409 struct drm_device *dev = encoder->dev;
3410 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3411 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3412
3413 /* lvds has its own version of commit see intel_lvds_commit */
3414 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3415
3416 if (HAS_PCH_CPT(dev))
3417 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3418 }
3419
3420 void intel_encoder_destroy(struct drm_encoder *encoder)
3421 {
3422 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3423
3424 drm_encoder_cleanup(encoder);
3425 kfree(intel_encoder);
3426 }
3427
3428 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3429 struct drm_display_mode *mode,
3430 struct drm_display_mode *adjusted_mode)
3431 {
3432 struct drm_device *dev = crtc->dev;
3433
3434 if (HAS_PCH_SPLIT(dev)) {
3435 /* FDI link clock is fixed at 2.7G */
3436 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3437 return false;
3438 }
3439
3440 /* XXX some encoders set the crtcinfo, others don't.
3441 * Obviously we need some form of conflict resolution here...
3442 */
3443 if (adjusted_mode->crtc_htotal == 0)
3444 drm_mode_set_crtcinfo(adjusted_mode, 0);
3445
3446 return true;
3447 }
3448
3449 static int i945_get_display_clock_speed(struct drm_device *dev)
3450 {
3451 return 400000;
3452 }
3453
3454 static int i915_get_display_clock_speed(struct drm_device *dev)
3455 {
3456 return 333000;
3457 }
3458
3459 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3460 {
3461 return 200000;
3462 }
3463
3464 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3465 {
3466 u16 gcfgc = 0;
3467
3468 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3469
3470 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3471 return 133000;
3472 else {
3473 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3474 case GC_DISPLAY_CLOCK_333_MHZ:
3475 return 333000;
3476 default:
3477 case GC_DISPLAY_CLOCK_190_200_MHZ:
3478 return 190000;
3479 }
3480 }
3481 }
3482
3483 static int i865_get_display_clock_speed(struct drm_device *dev)
3484 {
3485 return 266000;
3486 }
3487
3488 static int i855_get_display_clock_speed(struct drm_device *dev)
3489 {
3490 u16 hpllcc = 0;
3491 /* Assume that the hardware is in the high speed state. This
3492 * should be the default.
3493 */
3494 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3495 case GC_CLOCK_133_200:
3496 case GC_CLOCK_100_200:
3497 return 200000;
3498 case GC_CLOCK_166_250:
3499 return 250000;
3500 case GC_CLOCK_100_133:
3501 return 133000;
3502 }
3503
3504 /* Shouldn't happen */
3505 return 0;
3506 }
3507
3508 static int i830_get_display_clock_speed(struct drm_device *dev)
3509 {
3510 return 133000;
3511 }
3512
3513 struct fdi_m_n {
3514 u32 tu;
3515 u32 gmch_m;
3516 u32 gmch_n;
3517 u32 link_m;
3518 u32 link_n;
3519 };
3520
3521 static void
3522 fdi_reduce_ratio(u32 *num, u32 *den)
3523 {
3524 while (*num > 0xffffff || *den > 0xffffff) {
3525 *num >>= 1;
3526 *den >>= 1;
3527 }
3528 }
3529
3530 static void
3531 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3532 int link_clock, struct fdi_m_n *m_n)
3533 {
3534 m_n->tu = 64; /* default size */
3535
3536 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3537 m_n->gmch_m = bits_per_pixel * pixel_clock;
3538 m_n->gmch_n = link_clock * nlanes * 8;
3539 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3540
3541 m_n->link_m = pixel_clock;
3542 m_n->link_n = link_clock;
3543 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3544 }
3545
3546
3547 struct intel_watermark_params {
3548 unsigned long fifo_size;
3549 unsigned long max_wm;
3550 unsigned long default_wm;
3551 unsigned long guard_size;
3552 unsigned long cacheline_size;
3553 };
3554
3555 /* Pineview has different values for various configs */
3556 static const struct intel_watermark_params pineview_display_wm = {
3557 PINEVIEW_DISPLAY_FIFO,
3558 PINEVIEW_MAX_WM,
3559 PINEVIEW_DFT_WM,
3560 PINEVIEW_GUARD_WM,
3561 PINEVIEW_FIFO_LINE_SIZE
3562 };
3563 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3564 PINEVIEW_DISPLAY_FIFO,
3565 PINEVIEW_MAX_WM,
3566 PINEVIEW_DFT_HPLLOFF_WM,
3567 PINEVIEW_GUARD_WM,
3568 PINEVIEW_FIFO_LINE_SIZE
3569 };
3570 static const struct intel_watermark_params pineview_cursor_wm = {
3571 PINEVIEW_CURSOR_FIFO,
3572 PINEVIEW_CURSOR_MAX_WM,
3573 PINEVIEW_CURSOR_DFT_WM,
3574 PINEVIEW_CURSOR_GUARD_WM,
3575 PINEVIEW_FIFO_LINE_SIZE,
3576 };
3577 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3578 PINEVIEW_CURSOR_FIFO,
3579 PINEVIEW_CURSOR_MAX_WM,
3580 PINEVIEW_CURSOR_DFT_WM,
3581 PINEVIEW_CURSOR_GUARD_WM,
3582 PINEVIEW_FIFO_LINE_SIZE
3583 };
3584 static const struct intel_watermark_params g4x_wm_info = {
3585 G4X_FIFO_SIZE,
3586 G4X_MAX_WM,
3587 G4X_MAX_WM,
3588 2,
3589 G4X_FIFO_LINE_SIZE,
3590 };
3591 static const struct intel_watermark_params g4x_cursor_wm_info = {
3592 I965_CURSOR_FIFO,
3593 I965_CURSOR_MAX_WM,
3594 I965_CURSOR_DFT_WM,
3595 2,
3596 G4X_FIFO_LINE_SIZE,
3597 };
3598 static const struct intel_watermark_params i965_cursor_wm_info = {
3599 I965_CURSOR_FIFO,
3600 I965_CURSOR_MAX_WM,
3601 I965_CURSOR_DFT_WM,
3602 2,
3603 I915_FIFO_LINE_SIZE,
3604 };
3605 static const struct intel_watermark_params i945_wm_info = {
3606 I945_FIFO_SIZE,
3607 I915_MAX_WM,
3608 1,
3609 2,
3610 I915_FIFO_LINE_SIZE
3611 };
3612 static const struct intel_watermark_params i915_wm_info = {
3613 I915_FIFO_SIZE,
3614 I915_MAX_WM,
3615 1,
3616 2,
3617 I915_FIFO_LINE_SIZE
3618 };
3619 static const struct intel_watermark_params i855_wm_info = {
3620 I855GM_FIFO_SIZE,
3621 I915_MAX_WM,
3622 1,
3623 2,
3624 I830_FIFO_LINE_SIZE
3625 };
3626 static const struct intel_watermark_params i830_wm_info = {
3627 I830_FIFO_SIZE,
3628 I915_MAX_WM,
3629 1,
3630 2,
3631 I830_FIFO_LINE_SIZE
3632 };
3633
3634 static const struct intel_watermark_params ironlake_display_wm_info = {
3635 ILK_DISPLAY_FIFO,
3636 ILK_DISPLAY_MAXWM,
3637 ILK_DISPLAY_DFTWM,
3638 2,
3639 ILK_FIFO_LINE_SIZE
3640 };
3641 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3642 ILK_CURSOR_FIFO,
3643 ILK_CURSOR_MAXWM,
3644 ILK_CURSOR_DFTWM,
3645 2,
3646 ILK_FIFO_LINE_SIZE
3647 };
3648 static const struct intel_watermark_params ironlake_display_srwm_info = {
3649 ILK_DISPLAY_SR_FIFO,
3650 ILK_DISPLAY_MAX_SRWM,
3651 ILK_DISPLAY_DFT_SRWM,
3652 2,
3653 ILK_FIFO_LINE_SIZE
3654 };
3655 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3656 ILK_CURSOR_SR_FIFO,
3657 ILK_CURSOR_MAX_SRWM,
3658 ILK_CURSOR_DFT_SRWM,
3659 2,
3660 ILK_FIFO_LINE_SIZE
3661 };
3662
3663 static const struct intel_watermark_params sandybridge_display_wm_info = {
3664 SNB_DISPLAY_FIFO,
3665 SNB_DISPLAY_MAXWM,
3666 SNB_DISPLAY_DFTWM,
3667 2,
3668 SNB_FIFO_LINE_SIZE
3669 };
3670 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3671 SNB_CURSOR_FIFO,
3672 SNB_CURSOR_MAXWM,
3673 SNB_CURSOR_DFTWM,
3674 2,
3675 SNB_FIFO_LINE_SIZE
3676 };
3677 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3678 SNB_DISPLAY_SR_FIFO,
3679 SNB_DISPLAY_MAX_SRWM,
3680 SNB_DISPLAY_DFT_SRWM,
3681 2,
3682 SNB_FIFO_LINE_SIZE
3683 };
3684 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3685 SNB_CURSOR_SR_FIFO,
3686 SNB_CURSOR_MAX_SRWM,
3687 SNB_CURSOR_DFT_SRWM,
3688 2,
3689 SNB_FIFO_LINE_SIZE
3690 };
3691
3692
3693 /**
3694 * intel_calculate_wm - calculate watermark level
3695 * @clock_in_khz: pixel clock
3696 * @wm: chip FIFO params
3697 * @pixel_size: display pixel size
3698 * @latency_ns: memory latency for the platform
3699 *
3700 * Calculate the watermark level (the level at which the display plane will
3701 * start fetching from memory again). Each chip has a different display
3702 * FIFO size and allocation, so the caller needs to figure that out and pass
3703 * in the correct intel_watermark_params structure.
3704 *
3705 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3706 * on the pixel size. When it reaches the watermark level, it'll start
3707 * fetching FIFO line sized based chunks from memory until the FIFO fills
3708 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3709 * will occur, and a display engine hang could result.
3710 */
3711 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3712 const struct intel_watermark_params *wm,
3713 int fifo_size,
3714 int pixel_size,
3715 unsigned long latency_ns)
3716 {
3717 long entries_required, wm_size;
3718
3719 /*
3720 * Note: we need to make sure we don't overflow for various clock &
3721 * latency values.
3722 * clocks go from a few thousand to several hundred thousand.
3723 * latency is usually a few thousand
3724 */
3725 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3726 1000;
3727 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3728
3729 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3730
3731 wm_size = fifo_size - (entries_required + wm->guard_size);
3732
3733 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3734
3735 /* Don't promote wm_size to unsigned... */
3736 if (wm_size > (long)wm->max_wm)
3737 wm_size = wm->max_wm;
3738 if (wm_size <= 0)
3739 wm_size = wm->default_wm;
3740 return wm_size;
3741 }
3742
3743 struct cxsr_latency {
3744 int is_desktop;
3745 int is_ddr3;
3746 unsigned long fsb_freq;
3747 unsigned long mem_freq;
3748 unsigned long display_sr;
3749 unsigned long display_hpll_disable;
3750 unsigned long cursor_sr;
3751 unsigned long cursor_hpll_disable;
3752 };
3753
3754 static const struct cxsr_latency cxsr_latency_table[] = {
3755 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3756 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3757 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3758 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3759 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3760
3761 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3762 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3763 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3764 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3765 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3766
3767 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3768 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3769 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3770 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3771 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3772
3773 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3774 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3775 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3776 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3777 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3778
3779 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3780 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3781 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3782 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3783 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3784
3785 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3786 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3787 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3788 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3789 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3790 };
3791
3792 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3793 int is_ddr3,
3794 int fsb,
3795 int mem)
3796 {
3797 const struct cxsr_latency *latency;
3798 int i;
3799
3800 if (fsb == 0 || mem == 0)
3801 return NULL;
3802
3803 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3804 latency = &cxsr_latency_table[i];
3805 if (is_desktop == latency->is_desktop &&
3806 is_ddr3 == latency->is_ddr3 &&
3807 fsb == latency->fsb_freq && mem == latency->mem_freq)
3808 return latency;
3809 }
3810
3811 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3812
3813 return NULL;
3814 }
3815
3816 static void pineview_disable_cxsr(struct drm_device *dev)
3817 {
3818 struct drm_i915_private *dev_priv = dev->dev_private;
3819
3820 /* deactivate cxsr */
3821 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3822 }
3823
3824 /*
3825 * Latency for FIFO fetches is dependent on several factors:
3826 * - memory configuration (speed, channels)
3827 * - chipset
3828 * - current MCH state
3829 * It can be fairly high in some situations, so here we assume a fairly
3830 * pessimal value. It's a tradeoff between extra memory fetches (if we
3831 * set this value too high, the FIFO will fetch frequently to stay full)
3832 * and power consumption (set it too low to save power and we might see
3833 * FIFO underruns and display "flicker").
3834 *
3835 * A value of 5us seems to be a good balance; safe for very low end
3836 * platforms but not overly aggressive on lower latency configs.
3837 */
3838 static const int latency_ns = 5000;
3839
3840 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3841 {
3842 struct drm_i915_private *dev_priv = dev->dev_private;
3843 uint32_t dsparb = I915_READ(DSPARB);
3844 int size;
3845
3846 size = dsparb & 0x7f;
3847 if (plane)
3848 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3849
3850 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3851 plane ? "B" : "A", size);
3852
3853 return size;
3854 }
3855
3856 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3857 {
3858 struct drm_i915_private *dev_priv = dev->dev_private;
3859 uint32_t dsparb = I915_READ(DSPARB);
3860 int size;
3861
3862 size = dsparb & 0x1ff;
3863 if (plane)
3864 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3865 size >>= 1; /* Convert to cachelines */
3866
3867 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3868 plane ? "B" : "A", size);
3869
3870 return size;
3871 }
3872
3873 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3874 {
3875 struct drm_i915_private *dev_priv = dev->dev_private;
3876 uint32_t dsparb = I915_READ(DSPARB);
3877 int size;
3878
3879 size = dsparb & 0x7f;
3880 size >>= 2; /* Convert to cachelines */
3881
3882 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3883 plane ? "B" : "A",
3884 size);
3885
3886 return size;
3887 }
3888
3889 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3890 {
3891 struct drm_i915_private *dev_priv = dev->dev_private;
3892 uint32_t dsparb = I915_READ(DSPARB);
3893 int size;
3894
3895 size = dsparb & 0x7f;
3896 size >>= 1; /* Convert to cachelines */
3897
3898 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3899 plane ? "B" : "A", size);
3900
3901 return size;
3902 }
3903
3904 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3905 {
3906 struct drm_crtc *crtc, *enabled = NULL;
3907
3908 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3909 if (crtc->enabled && crtc->fb) {
3910 if (enabled)
3911 return NULL;
3912 enabled = crtc;
3913 }
3914 }
3915
3916 return enabled;
3917 }
3918
3919 static void pineview_update_wm(struct drm_device *dev)
3920 {
3921 struct drm_i915_private *dev_priv = dev->dev_private;
3922 struct drm_crtc *crtc;
3923 const struct cxsr_latency *latency;
3924 u32 reg;
3925 unsigned long wm;
3926
3927 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3928 dev_priv->fsb_freq, dev_priv->mem_freq);
3929 if (!latency) {
3930 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3931 pineview_disable_cxsr(dev);
3932 return;
3933 }
3934
3935 crtc = single_enabled_crtc(dev);
3936 if (crtc) {
3937 int clock = crtc->mode.clock;
3938 int pixel_size = crtc->fb->bits_per_pixel / 8;
3939
3940 /* Display SR */
3941 wm = intel_calculate_wm(clock, &pineview_display_wm,
3942 pineview_display_wm.fifo_size,
3943 pixel_size, latency->display_sr);
3944 reg = I915_READ(DSPFW1);
3945 reg &= ~DSPFW_SR_MASK;
3946 reg |= wm << DSPFW_SR_SHIFT;
3947 I915_WRITE(DSPFW1, reg);
3948 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3949
3950 /* cursor SR */
3951 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3952 pineview_display_wm.fifo_size,
3953 pixel_size, latency->cursor_sr);
3954 reg = I915_READ(DSPFW3);
3955 reg &= ~DSPFW_CURSOR_SR_MASK;
3956 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3957 I915_WRITE(DSPFW3, reg);
3958
3959 /* Display HPLL off SR */
3960 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3961 pineview_display_hplloff_wm.fifo_size,
3962 pixel_size, latency->display_hpll_disable);
3963 reg = I915_READ(DSPFW3);
3964 reg &= ~DSPFW_HPLL_SR_MASK;
3965 reg |= wm & DSPFW_HPLL_SR_MASK;
3966 I915_WRITE(DSPFW3, reg);
3967
3968 /* cursor HPLL off SR */
3969 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3970 pineview_display_hplloff_wm.fifo_size,
3971 pixel_size, latency->cursor_hpll_disable);
3972 reg = I915_READ(DSPFW3);
3973 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3974 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3975 I915_WRITE(DSPFW3, reg);
3976 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3977
3978 /* activate cxsr */
3979 I915_WRITE(DSPFW3,
3980 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3981 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3982 } else {
3983 pineview_disable_cxsr(dev);
3984 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3985 }
3986 }
3987
3988 static bool g4x_compute_wm0(struct drm_device *dev,
3989 int plane,
3990 const struct intel_watermark_params *display,
3991 int display_latency_ns,
3992 const struct intel_watermark_params *cursor,
3993 int cursor_latency_ns,
3994 int *plane_wm,
3995 int *cursor_wm)
3996 {
3997 struct drm_crtc *crtc;
3998 int htotal, hdisplay, clock, pixel_size;
3999 int line_time_us, line_count;
4000 int entries, tlb_miss;
4001
4002 crtc = intel_get_crtc_for_plane(dev, plane);
4003 if (crtc->fb == NULL || !crtc->enabled) {
4004 *cursor_wm = cursor->guard_size;
4005 *plane_wm = display->guard_size;
4006 return false;
4007 }
4008
4009 htotal = crtc->mode.htotal;
4010 hdisplay = crtc->mode.hdisplay;
4011 clock = crtc->mode.clock;
4012 pixel_size = crtc->fb->bits_per_pixel / 8;
4013
4014 /* Use the small buffer method to calculate plane watermark */
4015 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4016 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4017 if (tlb_miss > 0)
4018 entries += tlb_miss;
4019 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4020 *plane_wm = entries + display->guard_size;
4021 if (*plane_wm > (int)display->max_wm)
4022 *plane_wm = display->max_wm;
4023
4024 /* Use the large buffer method to calculate cursor watermark */
4025 line_time_us = ((htotal * 1000) / clock);
4026 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4027 entries = line_count * 64 * pixel_size;
4028 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4029 if (tlb_miss > 0)
4030 entries += tlb_miss;
4031 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4032 *cursor_wm = entries + cursor->guard_size;
4033 if (*cursor_wm > (int)cursor->max_wm)
4034 *cursor_wm = (int)cursor->max_wm;
4035
4036 return true;
4037 }
4038
4039 /*
4040 * Check the wm result.
4041 *
4042 * If any calculated watermark values is larger than the maximum value that
4043 * can be programmed into the associated watermark register, that watermark
4044 * must be disabled.
4045 */
4046 static bool g4x_check_srwm(struct drm_device *dev,
4047 int display_wm, int cursor_wm,
4048 const struct intel_watermark_params *display,
4049 const struct intel_watermark_params *cursor)
4050 {
4051 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4052 display_wm, cursor_wm);
4053
4054 if (display_wm > display->max_wm) {
4055 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4056 display_wm, display->max_wm);
4057 return false;
4058 }
4059
4060 if (cursor_wm > cursor->max_wm) {
4061 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4062 cursor_wm, cursor->max_wm);
4063 return false;
4064 }
4065
4066 if (!(display_wm || cursor_wm)) {
4067 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4068 return false;
4069 }
4070
4071 return true;
4072 }
4073
4074 static bool g4x_compute_srwm(struct drm_device *dev,
4075 int plane,
4076 int latency_ns,
4077 const struct intel_watermark_params *display,
4078 const struct intel_watermark_params *cursor,
4079 int *display_wm, int *cursor_wm)
4080 {
4081 struct drm_crtc *crtc;
4082 int hdisplay, htotal, pixel_size, clock;
4083 unsigned long line_time_us;
4084 int line_count, line_size;
4085 int small, large;
4086 int entries;
4087
4088 if (!latency_ns) {
4089 *display_wm = *cursor_wm = 0;
4090 return false;
4091 }
4092
4093 crtc = intel_get_crtc_for_plane(dev, plane);
4094 hdisplay = crtc->mode.hdisplay;
4095 htotal = crtc->mode.htotal;
4096 clock = crtc->mode.clock;
4097 pixel_size = crtc->fb->bits_per_pixel / 8;
4098
4099 line_time_us = (htotal * 1000) / clock;
4100 line_count = (latency_ns / line_time_us + 1000) / 1000;
4101 line_size = hdisplay * pixel_size;
4102
4103 /* Use the minimum of the small and large buffer method for primary */
4104 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4105 large = line_count * line_size;
4106
4107 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4108 *display_wm = entries + display->guard_size;
4109
4110 /* calculate the self-refresh watermark for display cursor */
4111 entries = line_count * pixel_size * 64;
4112 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4113 *cursor_wm = entries + cursor->guard_size;
4114
4115 return g4x_check_srwm(dev,
4116 *display_wm, *cursor_wm,
4117 display, cursor);
4118 }
4119
4120 #define single_plane_enabled(mask) is_power_of_2(mask)
4121
4122 static void g4x_update_wm(struct drm_device *dev)
4123 {
4124 static const int sr_latency_ns = 12000;
4125 struct drm_i915_private *dev_priv = dev->dev_private;
4126 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4127 int plane_sr, cursor_sr;
4128 unsigned int enabled = 0;
4129
4130 if (g4x_compute_wm0(dev, 0,
4131 &g4x_wm_info, latency_ns,
4132 &g4x_cursor_wm_info, latency_ns,
4133 &planea_wm, &cursora_wm))
4134 enabled |= 1;
4135
4136 if (g4x_compute_wm0(dev, 1,
4137 &g4x_wm_info, latency_ns,
4138 &g4x_cursor_wm_info, latency_ns,
4139 &planeb_wm, &cursorb_wm))
4140 enabled |= 2;
4141
4142 plane_sr = cursor_sr = 0;
4143 if (single_plane_enabled(enabled) &&
4144 g4x_compute_srwm(dev, ffs(enabled) - 1,
4145 sr_latency_ns,
4146 &g4x_wm_info,
4147 &g4x_cursor_wm_info,
4148 &plane_sr, &cursor_sr))
4149 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4150 else
4151 I915_WRITE(FW_BLC_SELF,
4152 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4153
4154 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4155 planea_wm, cursora_wm,
4156 planeb_wm, cursorb_wm,
4157 plane_sr, cursor_sr);
4158
4159 I915_WRITE(DSPFW1,
4160 (plane_sr << DSPFW_SR_SHIFT) |
4161 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4162 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4163 planea_wm);
4164 I915_WRITE(DSPFW2,
4165 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4166 (cursora_wm << DSPFW_CURSORA_SHIFT));
4167 /* HPLL off in SR has some issues on G4x... disable it */
4168 I915_WRITE(DSPFW3,
4169 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4170 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4171 }
4172
4173 static void i965_update_wm(struct drm_device *dev)
4174 {
4175 struct drm_i915_private *dev_priv = dev->dev_private;
4176 struct drm_crtc *crtc;
4177 int srwm = 1;
4178 int cursor_sr = 16;
4179
4180 /* Calc sr entries for one plane configs */
4181 crtc = single_enabled_crtc(dev);
4182 if (crtc) {
4183 /* self-refresh has much higher latency */
4184 static const int sr_latency_ns = 12000;
4185 int clock = crtc->mode.clock;
4186 int htotal = crtc->mode.htotal;
4187 int hdisplay = crtc->mode.hdisplay;
4188 int pixel_size = crtc->fb->bits_per_pixel / 8;
4189 unsigned long line_time_us;
4190 int entries;
4191
4192 line_time_us = ((htotal * 1000) / clock);
4193
4194 /* Use ns/us then divide to preserve precision */
4195 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4196 pixel_size * hdisplay;
4197 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4198 srwm = I965_FIFO_SIZE - entries;
4199 if (srwm < 0)
4200 srwm = 1;
4201 srwm &= 0x1ff;
4202 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4203 entries, srwm);
4204
4205 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4206 pixel_size * 64;
4207 entries = DIV_ROUND_UP(entries,
4208 i965_cursor_wm_info.cacheline_size);
4209 cursor_sr = i965_cursor_wm_info.fifo_size -
4210 (entries + i965_cursor_wm_info.guard_size);
4211
4212 if (cursor_sr > i965_cursor_wm_info.max_wm)
4213 cursor_sr = i965_cursor_wm_info.max_wm;
4214
4215 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4216 "cursor %d\n", srwm, cursor_sr);
4217
4218 if (IS_CRESTLINE(dev))
4219 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4220 } else {
4221 /* Turn off self refresh if both pipes are enabled */
4222 if (IS_CRESTLINE(dev))
4223 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4224 & ~FW_BLC_SELF_EN);
4225 }
4226
4227 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4228 srwm);
4229
4230 /* 965 has limitations... */
4231 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4232 (8 << 16) | (8 << 8) | (8 << 0));
4233 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4234 /* update cursor SR watermark */
4235 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4236 }
4237
4238 static void i9xx_update_wm(struct drm_device *dev)
4239 {
4240 struct drm_i915_private *dev_priv = dev->dev_private;
4241 const struct intel_watermark_params *wm_info;
4242 uint32_t fwater_lo;
4243 uint32_t fwater_hi;
4244 int cwm, srwm = 1;
4245 int fifo_size;
4246 int planea_wm, planeb_wm;
4247 struct drm_crtc *crtc, *enabled = NULL;
4248
4249 if (IS_I945GM(dev))
4250 wm_info = &i945_wm_info;
4251 else if (!IS_GEN2(dev))
4252 wm_info = &i915_wm_info;
4253 else
4254 wm_info = &i855_wm_info;
4255
4256 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4257 crtc = intel_get_crtc_for_plane(dev, 0);
4258 if (crtc->enabled && crtc->fb) {
4259 planea_wm = intel_calculate_wm(crtc->mode.clock,
4260 wm_info, fifo_size,
4261 crtc->fb->bits_per_pixel / 8,
4262 latency_ns);
4263 enabled = crtc;
4264 } else
4265 planea_wm = fifo_size - wm_info->guard_size;
4266
4267 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4268 crtc = intel_get_crtc_for_plane(dev, 1);
4269 if (crtc->enabled && crtc->fb) {
4270 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4271 wm_info, fifo_size,
4272 crtc->fb->bits_per_pixel / 8,
4273 latency_ns);
4274 if (enabled == NULL)
4275 enabled = crtc;
4276 else
4277 enabled = NULL;
4278 } else
4279 planeb_wm = fifo_size - wm_info->guard_size;
4280
4281 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4282
4283 /*
4284 * Overlay gets an aggressive default since video jitter is bad.
4285 */
4286 cwm = 2;
4287
4288 /* Play safe and disable self-refresh before adjusting watermarks. */
4289 if (IS_I945G(dev) || IS_I945GM(dev))
4290 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4291 else if (IS_I915GM(dev))
4292 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4293
4294 /* Calc sr entries for one plane configs */
4295 if (HAS_FW_BLC(dev) && enabled) {
4296 /* self-refresh has much higher latency */
4297 static const int sr_latency_ns = 6000;
4298 int clock = enabled->mode.clock;
4299 int htotal = enabled->mode.htotal;
4300 int hdisplay = enabled->mode.hdisplay;
4301 int pixel_size = enabled->fb->bits_per_pixel / 8;
4302 unsigned long line_time_us;
4303 int entries;
4304
4305 line_time_us = (htotal * 1000) / clock;
4306
4307 /* Use ns/us then divide to preserve precision */
4308 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4309 pixel_size * hdisplay;
4310 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4311 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4312 srwm = wm_info->fifo_size - entries;
4313 if (srwm < 0)
4314 srwm = 1;
4315
4316 if (IS_I945G(dev) || IS_I945GM(dev))
4317 I915_WRITE(FW_BLC_SELF,
4318 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4319 else if (IS_I915GM(dev))
4320 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4321 }
4322
4323 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4324 planea_wm, planeb_wm, cwm, srwm);
4325
4326 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4327 fwater_hi = (cwm & 0x1f);
4328
4329 /* Set request length to 8 cachelines per fetch */
4330 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4331 fwater_hi = fwater_hi | (1 << 8);
4332
4333 I915_WRITE(FW_BLC, fwater_lo);
4334 I915_WRITE(FW_BLC2, fwater_hi);
4335
4336 if (HAS_FW_BLC(dev)) {
4337 if (enabled) {
4338 if (IS_I945G(dev) || IS_I945GM(dev))
4339 I915_WRITE(FW_BLC_SELF,
4340 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4341 else if (IS_I915GM(dev))
4342 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4343 DRM_DEBUG_KMS("memory self refresh enabled\n");
4344 } else
4345 DRM_DEBUG_KMS("memory self refresh disabled\n");
4346 }
4347 }
4348
4349 static void i830_update_wm(struct drm_device *dev)
4350 {
4351 struct drm_i915_private *dev_priv = dev->dev_private;
4352 struct drm_crtc *crtc;
4353 uint32_t fwater_lo;
4354 int planea_wm;
4355
4356 crtc = single_enabled_crtc(dev);
4357 if (crtc == NULL)
4358 return;
4359
4360 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4361 dev_priv->display.get_fifo_size(dev, 0),
4362 crtc->fb->bits_per_pixel / 8,
4363 latency_ns);
4364 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4365 fwater_lo |= (3<<8) | planea_wm;
4366
4367 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4368
4369 I915_WRITE(FW_BLC, fwater_lo);
4370 }
4371
4372 #define ILK_LP0_PLANE_LATENCY 700
4373 #define ILK_LP0_CURSOR_LATENCY 1300
4374
4375 /*
4376 * Check the wm result.
4377 *
4378 * If any calculated watermark values is larger than the maximum value that
4379 * can be programmed into the associated watermark register, that watermark
4380 * must be disabled.
4381 */
4382 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4383 int fbc_wm, int display_wm, int cursor_wm,
4384 const struct intel_watermark_params *display,
4385 const struct intel_watermark_params *cursor)
4386 {
4387 struct drm_i915_private *dev_priv = dev->dev_private;
4388
4389 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4390 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4391
4392 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4393 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4394 fbc_wm, SNB_FBC_MAX_SRWM, level);
4395
4396 /* fbc has it's own way to disable FBC WM */
4397 I915_WRITE(DISP_ARB_CTL,
4398 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4399 return false;
4400 }
4401
4402 if (display_wm > display->max_wm) {
4403 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4404 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4405 return false;
4406 }
4407
4408 if (cursor_wm > cursor->max_wm) {
4409 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4410 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4411 return false;
4412 }
4413
4414 if (!(fbc_wm || display_wm || cursor_wm)) {
4415 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4416 return false;
4417 }
4418
4419 return true;
4420 }
4421
4422 /*
4423 * Compute watermark values of WM[1-3],
4424 */
4425 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4426 int latency_ns,
4427 const struct intel_watermark_params *display,
4428 const struct intel_watermark_params *cursor,
4429 int *fbc_wm, int *display_wm, int *cursor_wm)
4430 {
4431 struct drm_crtc *crtc;
4432 unsigned long line_time_us;
4433 int hdisplay, htotal, pixel_size, clock;
4434 int line_count, line_size;
4435 int small, large;
4436 int entries;
4437
4438 if (!latency_ns) {
4439 *fbc_wm = *display_wm = *cursor_wm = 0;
4440 return false;
4441 }
4442
4443 crtc = intel_get_crtc_for_plane(dev, plane);
4444 hdisplay = crtc->mode.hdisplay;
4445 htotal = crtc->mode.htotal;
4446 clock = crtc->mode.clock;
4447 pixel_size = crtc->fb->bits_per_pixel / 8;
4448
4449 line_time_us = (htotal * 1000) / clock;
4450 line_count = (latency_ns / line_time_us + 1000) / 1000;
4451 line_size = hdisplay * pixel_size;
4452
4453 /* Use the minimum of the small and large buffer method for primary */
4454 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4455 large = line_count * line_size;
4456
4457 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4458 *display_wm = entries + display->guard_size;
4459
4460 /*
4461 * Spec says:
4462 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4463 */
4464 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4465
4466 /* calculate the self-refresh watermark for display cursor */
4467 entries = line_count * pixel_size * 64;
4468 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4469 *cursor_wm = entries + cursor->guard_size;
4470
4471 return ironlake_check_srwm(dev, level,
4472 *fbc_wm, *display_wm, *cursor_wm,
4473 display, cursor);
4474 }
4475
4476 static void ironlake_update_wm(struct drm_device *dev)
4477 {
4478 struct drm_i915_private *dev_priv = dev->dev_private;
4479 int fbc_wm, plane_wm, cursor_wm;
4480 unsigned int enabled;
4481
4482 enabled = 0;
4483 if (g4x_compute_wm0(dev, 0,
4484 &ironlake_display_wm_info,
4485 ILK_LP0_PLANE_LATENCY,
4486 &ironlake_cursor_wm_info,
4487 ILK_LP0_CURSOR_LATENCY,
4488 &plane_wm, &cursor_wm)) {
4489 I915_WRITE(WM0_PIPEA_ILK,
4490 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4491 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4492 " plane %d, " "cursor: %d\n",
4493 plane_wm, cursor_wm);
4494 enabled |= 1;
4495 }
4496
4497 if (g4x_compute_wm0(dev, 1,
4498 &ironlake_display_wm_info,
4499 ILK_LP0_PLANE_LATENCY,
4500 &ironlake_cursor_wm_info,
4501 ILK_LP0_CURSOR_LATENCY,
4502 &plane_wm, &cursor_wm)) {
4503 I915_WRITE(WM0_PIPEB_ILK,
4504 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4505 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4506 " plane %d, cursor: %d\n",
4507 plane_wm, cursor_wm);
4508 enabled |= 2;
4509 }
4510
4511 /*
4512 * Calculate and update the self-refresh watermark only when one
4513 * display plane is used.
4514 */
4515 I915_WRITE(WM3_LP_ILK, 0);
4516 I915_WRITE(WM2_LP_ILK, 0);
4517 I915_WRITE(WM1_LP_ILK, 0);
4518
4519 if (!single_plane_enabled(enabled))
4520 return;
4521 enabled = ffs(enabled) - 1;
4522
4523 /* WM1 */
4524 if (!ironlake_compute_srwm(dev, 1, enabled,
4525 ILK_READ_WM1_LATENCY() * 500,
4526 &ironlake_display_srwm_info,
4527 &ironlake_cursor_srwm_info,
4528 &fbc_wm, &plane_wm, &cursor_wm))
4529 return;
4530
4531 I915_WRITE(WM1_LP_ILK,
4532 WM1_LP_SR_EN |
4533 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4534 (fbc_wm << WM1_LP_FBC_SHIFT) |
4535 (plane_wm << WM1_LP_SR_SHIFT) |
4536 cursor_wm);
4537
4538 /* WM2 */
4539 if (!ironlake_compute_srwm(dev, 2, enabled,
4540 ILK_READ_WM2_LATENCY() * 500,
4541 &ironlake_display_srwm_info,
4542 &ironlake_cursor_srwm_info,
4543 &fbc_wm, &plane_wm, &cursor_wm))
4544 return;
4545
4546 I915_WRITE(WM2_LP_ILK,
4547 WM2_LP_EN |
4548 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4549 (fbc_wm << WM1_LP_FBC_SHIFT) |
4550 (plane_wm << WM1_LP_SR_SHIFT) |
4551 cursor_wm);
4552
4553 /*
4554 * WM3 is unsupported on ILK, probably because we don't have latency
4555 * data for that power state
4556 */
4557 }
4558
4559 void sandybridge_update_wm(struct drm_device *dev)
4560 {
4561 struct drm_i915_private *dev_priv = dev->dev_private;
4562 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4563 u32 val;
4564 int fbc_wm, plane_wm, cursor_wm;
4565 unsigned int enabled;
4566
4567 enabled = 0;
4568 if (g4x_compute_wm0(dev, 0,
4569 &sandybridge_display_wm_info, latency,
4570 &sandybridge_cursor_wm_info, latency,
4571 &plane_wm, &cursor_wm)) {
4572 val = I915_READ(WM0_PIPEA_ILK);
4573 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4574 I915_WRITE(WM0_PIPEA_ILK, val |
4575 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4576 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4577 " plane %d, " "cursor: %d\n",
4578 plane_wm, cursor_wm);
4579 enabled |= 1;
4580 }
4581
4582 if (g4x_compute_wm0(dev, 1,
4583 &sandybridge_display_wm_info, latency,
4584 &sandybridge_cursor_wm_info, latency,
4585 &plane_wm, &cursor_wm)) {
4586 val = I915_READ(WM0_PIPEB_ILK);
4587 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4588 I915_WRITE(WM0_PIPEB_ILK, val |
4589 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4590 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4591 " plane %d, cursor: %d\n",
4592 plane_wm, cursor_wm);
4593 enabled |= 2;
4594 }
4595
4596 /* IVB has 3 pipes */
4597 if (IS_IVYBRIDGE(dev) &&
4598 g4x_compute_wm0(dev, 2,
4599 &sandybridge_display_wm_info, latency,
4600 &sandybridge_cursor_wm_info, latency,
4601 &plane_wm, &cursor_wm)) {
4602 val = I915_READ(WM0_PIPEC_IVB);
4603 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4604 I915_WRITE(WM0_PIPEC_IVB, val |
4605 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4606 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4607 " plane %d, cursor: %d\n",
4608 plane_wm, cursor_wm);
4609 enabled |= 3;
4610 }
4611
4612 /*
4613 * Calculate and update the self-refresh watermark only when one
4614 * display plane is used.
4615 *
4616 * SNB support 3 levels of watermark.
4617 *
4618 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4619 * and disabled in the descending order
4620 *
4621 */
4622 I915_WRITE(WM3_LP_ILK, 0);
4623 I915_WRITE(WM2_LP_ILK, 0);
4624 I915_WRITE(WM1_LP_ILK, 0);
4625
4626 if (!single_plane_enabled(enabled) ||
4627 dev_priv->sprite_scaling_enabled)
4628 return;
4629 enabled = ffs(enabled) - 1;
4630
4631 /* WM1 */
4632 if (!ironlake_compute_srwm(dev, 1, enabled,
4633 SNB_READ_WM1_LATENCY() * 500,
4634 &sandybridge_display_srwm_info,
4635 &sandybridge_cursor_srwm_info,
4636 &fbc_wm, &plane_wm, &cursor_wm))
4637 return;
4638
4639 I915_WRITE(WM1_LP_ILK,
4640 WM1_LP_SR_EN |
4641 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4642 (fbc_wm << WM1_LP_FBC_SHIFT) |
4643 (plane_wm << WM1_LP_SR_SHIFT) |
4644 cursor_wm);
4645
4646 /* WM2 */
4647 if (!ironlake_compute_srwm(dev, 2, enabled,
4648 SNB_READ_WM2_LATENCY() * 500,
4649 &sandybridge_display_srwm_info,
4650 &sandybridge_cursor_srwm_info,
4651 &fbc_wm, &plane_wm, &cursor_wm))
4652 return;
4653
4654 I915_WRITE(WM2_LP_ILK,
4655 WM2_LP_EN |
4656 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4657 (fbc_wm << WM1_LP_FBC_SHIFT) |
4658 (plane_wm << WM1_LP_SR_SHIFT) |
4659 cursor_wm);
4660
4661 /* WM3 */
4662 if (!ironlake_compute_srwm(dev, 3, enabled,
4663 SNB_READ_WM3_LATENCY() * 500,
4664 &sandybridge_display_srwm_info,
4665 &sandybridge_cursor_srwm_info,
4666 &fbc_wm, &plane_wm, &cursor_wm))
4667 return;
4668
4669 I915_WRITE(WM3_LP_ILK,
4670 WM3_LP_EN |
4671 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4672 (fbc_wm << WM1_LP_FBC_SHIFT) |
4673 (plane_wm << WM1_LP_SR_SHIFT) |
4674 cursor_wm);
4675 }
4676
4677 static bool
4678 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4679 uint32_t sprite_width, int pixel_size,
4680 const struct intel_watermark_params *display,
4681 int display_latency_ns, int *sprite_wm)
4682 {
4683 struct drm_crtc *crtc;
4684 int clock;
4685 int entries, tlb_miss;
4686
4687 crtc = intel_get_crtc_for_plane(dev, plane);
4688 if (crtc->fb == NULL || !crtc->enabled) {
4689 *sprite_wm = display->guard_size;
4690 return false;
4691 }
4692
4693 clock = crtc->mode.clock;
4694
4695 /* Use the small buffer method to calculate the sprite watermark */
4696 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4697 tlb_miss = display->fifo_size*display->cacheline_size -
4698 sprite_width * 8;
4699 if (tlb_miss > 0)
4700 entries += tlb_miss;
4701 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4702 *sprite_wm = entries + display->guard_size;
4703 if (*sprite_wm > (int)display->max_wm)
4704 *sprite_wm = display->max_wm;
4705
4706 return true;
4707 }
4708
4709 static bool
4710 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4711 uint32_t sprite_width, int pixel_size,
4712 const struct intel_watermark_params *display,
4713 int latency_ns, int *sprite_wm)
4714 {
4715 struct drm_crtc *crtc;
4716 unsigned long line_time_us;
4717 int clock;
4718 int line_count, line_size;
4719 int small, large;
4720 int entries;
4721
4722 if (!latency_ns) {
4723 *sprite_wm = 0;
4724 return false;
4725 }
4726
4727 crtc = intel_get_crtc_for_plane(dev, plane);
4728 clock = crtc->mode.clock;
4729
4730 line_time_us = (sprite_width * 1000) / clock;
4731 line_count = (latency_ns / line_time_us + 1000) / 1000;
4732 line_size = sprite_width * pixel_size;
4733
4734 /* Use the minimum of the small and large buffer method for primary */
4735 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4736 large = line_count * line_size;
4737
4738 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4739 *sprite_wm = entries + display->guard_size;
4740
4741 return *sprite_wm > 0x3ff ? false : true;
4742 }
4743
4744 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4745 uint32_t sprite_width, int pixel_size)
4746 {
4747 struct drm_i915_private *dev_priv = dev->dev_private;
4748 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4749 u32 val;
4750 int sprite_wm, reg;
4751 int ret;
4752
4753 switch (pipe) {
4754 case 0:
4755 reg = WM0_PIPEA_ILK;
4756 break;
4757 case 1:
4758 reg = WM0_PIPEB_ILK;
4759 break;
4760 case 2:
4761 reg = WM0_PIPEC_IVB;
4762 break;
4763 default:
4764 return; /* bad pipe */
4765 }
4766
4767 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4768 &sandybridge_display_wm_info,
4769 latency, &sprite_wm);
4770 if (!ret) {
4771 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4772 pipe);
4773 return;
4774 }
4775
4776 val = I915_READ(reg);
4777 val &= ~WM0_PIPE_SPRITE_MASK;
4778 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
4779 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4780
4781
4782 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4783 pixel_size,
4784 &sandybridge_display_srwm_info,
4785 SNB_READ_WM1_LATENCY() * 500,
4786 &sprite_wm);
4787 if (!ret) {
4788 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4789 pipe);
4790 return;
4791 }
4792 I915_WRITE(WM1S_LP_ILK, sprite_wm);
4793
4794 /* Only IVB has two more LP watermarks for sprite */
4795 if (!IS_IVYBRIDGE(dev))
4796 return;
4797
4798 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4799 pixel_size,
4800 &sandybridge_display_srwm_info,
4801 SNB_READ_WM2_LATENCY() * 500,
4802 &sprite_wm);
4803 if (!ret) {
4804 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4805 pipe);
4806 return;
4807 }
4808 I915_WRITE(WM2S_LP_IVB, sprite_wm);
4809
4810 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4811 pixel_size,
4812 &sandybridge_display_srwm_info,
4813 SNB_READ_WM3_LATENCY() * 500,
4814 &sprite_wm);
4815 if (!ret) {
4816 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4817 pipe);
4818 return;
4819 }
4820 I915_WRITE(WM3S_LP_IVB, sprite_wm);
4821 }
4822
4823 /**
4824 * intel_update_watermarks - update FIFO watermark values based on current modes
4825 *
4826 * Calculate watermark values for the various WM regs based on current mode
4827 * and plane configuration.
4828 *
4829 * There are several cases to deal with here:
4830 * - normal (i.e. non-self-refresh)
4831 * - self-refresh (SR) mode
4832 * - lines are large relative to FIFO size (buffer can hold up to 2)
4833 * - lines are small relative to FIFO size (buffer can hold more than 2
4834 * lines), so need to account for TLB latency
4835 *
4836 * The normal calculation is:
4837 * watermark = dotclock * bytes per pixel * latency
4838 * where latency is platform & configuration dependent (we assume pessimal
4839 * values here).
4840 *
4841 * The SR calculation is:
4842 * watermark = (trunc(latency/line time)+1) * surface width *
4843 * bytes per pixel
4844 * where
4845 * line time = htotal / dotclock
4846 * surface width = hdisplay for normal plane and 64 for cursor
4847 * and latency is assumed to be high, as above.
4848 *
4849 * The final value programmed to the register should always be rounded up,
4850 * and include an extra 2 entries to account for clock crossings.
4851 *
4852 * We don't use the sprite, so we can ignore that. And on Crestline we have
4853 * to set the non-SR watermarks to 8.
4854 */
4855 static void intel_update_watermarks(struct drm_device *dev)
4856 {
4857 struct drm_i915_private *dev_priv = dev->dev_private;
4858
4859 if (dev_priv->display.update_wm)
4860 dev_priv->display.update_wm(dev);
4861 }
4862
4863 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4864 uint32_t sprite_width, int pixel_size)
4865 {
4866 struct drm_i915_private *dev_priv = dev->dev_private;
4867
4868 if (dev_priv->display.update_sprite_wm)
4869 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4870 pixel_size);
4871 }
4872
4873 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4874 {
4875 if (i915_panel_use_ssc >= 0)
4876 return i915_panel_use_ssc != 0;
4877 return dev_priv->lvds_use_ssc
4878 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4879 }
4880
4881 /**
4882 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4883 * @crtc: CRTC structure
4884 * @mode: requested mode
4885 *
4886 * A pipe may be connected to one or more outputs. Based on the depth of the
4887 * attached framebuffer, choose a good color depth to use on the pipe.
4888 *
4889 * If possible, match the pipe depth to the fb depth. In some cases, this
4890 * isn't ideal, because the connected output supports a lesser or restricted
4891 * set of depths. Resolve that here:
4892 * LVDS typically supports only 6bpc, so clamp down in that case
4893 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4894 * Displays may support a restricted set as well, check EDID and clamp as
4895 * appropriate.
4896 * DP may want to dither down to 6bpc to fit larger modes
4897 *
4898 * RETURNS:
4899 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4900 * true if they don't match).
4901 */
4902 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4903 unsigned int *pipe_bpp,
4904 struct drm_display_mode *mode)
4905 {
4906 struct drm_device *dev = crtc->dev;
4907 struct drm_i915_private *dev_priv = dev->dev_private;
4908 struct drm_encoder *encoder;
4909 struct drm_connector *connector;
4910 unsigned int display_bpc = UINT_MAX, bpc;
4911
4912 /* Walk the encoders & connectors on this crtc, get min bpc */
4913 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4914 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4915
4916 if (encoder->crtc != crtc)
4917 continue;
4918
4919 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4920 unsigned int lvds_bpc;
4921
4922 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4923 LVDS_A3_POWER_UP)
4924 lvds_bpc = 8;
4925 else
4926 lvds_bpc = 6;
4927
4928 if (lvds_bpc < display_bpc) {
4929 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4930 display_bpc = lvds_bpc;
4931 }
4932 continue;
4933 }
4934
4935 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4936 /* Use VBT settings if we have an eDP panel */
4937 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4938
4939 if (edp_bpc < display_bpc) {
4940 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4941 display_bpc = edp_bpc;
4942 }
4943 continue;
4944 }
4945
4946 /* Not one of the known troublemakers, check the EDID */
4947 list_for_each_entry(connector, &dev->mode_config.connector_list,
4948 head) {
4949 if (connector->encoder != encoder)
4950 continue;
4951
4952 /* Don't use an invalid EDID bpc value */
4953 if (connector->display_info.bpc &&
4954 connector->display_info.bpc < display_bpc) {
4955 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4956 display_bpc = connector->display_info.bpc;
4957 }
4958 }
4959
4960 /*
4961 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4962 * through, clamp it down. (Note: >12bpc will be caught below.)
4963 */
4964 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4965 if (display_bpc > 8 && display_bpc < 12) {
4966 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4967 display_bpc = 12;
4968 } else {
4969 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4970 display_bpc = 8;
4971 }
4972 }
4973 }
4974
4975 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4976 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4977 display_bpc = 6;
4978 }
4979
4980 /*
4981 * We could just drive the pipe at the highest bpc all the time and
4982 * enable dithering as needed, but that costs bandwidth. So choose
4983 * the minimum value that expresses the full color range of the fb but
4984 * also stays within the max display bpc discovered above.
4985 */
4986
4987 switch (crtc->fb->depth) {
4988 case 8:
4989 bpc = 8; /* since we go through a colormap */
4990 break;
4991 case 15:
4992 case 16:
4993 bpc = 6; /* min is 18bpp */
4994 break;
4995 case 24:
4996 bpc = 8;
4997 break;
4998 case 30:
4999 bpc = 10;
5000 break;
5001 case 48:
5002 bpc = 12;
5003 break;
5004 default:
5005 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
5006 bpc = min((unsigned int)8, display_bpc);
5007 break;
5008 }
5009
5010 display_bpc = min(display_bpc, bpc);
5011
5012 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
5013 bpc, display_bpc);
5014
5015 *pipe_bpp = display_bpc * 3;
5016
5017 return display_bpc != bpc;
5018 }
5019
5020 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5021 {
5022 struct drm_device *dev = crtc->dev;
5023 struct drm_i915_private *dev_priv = dev->dev_private;
5024 int refclk;
5025
5026 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5027 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5028 refclk = dev_priv->lvds_ssc_freq * 1000;
5029 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5030 refclk / 1000);
5031 } else if (!IS_GEN2(dev)) {
5032 refclk = 96000;
5033 } else {
5034 refclk = 48000;
5035 }
5036
5037 return refclk;
5038 }
5039
5040 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5041 intel_clock_t *clock)
5042 {
5043 /* SDVO TV has fixed PLL values depend on its clock range,
5044 this mirrors vbios setting. */
5045 if (adjusted_mode->clock >= 100000
5046 && adjusted_mode->clock < 140500) {
5047 clock->p1 = 2;
5048 clock->p2 = 10;
5049 clock->n = 3;
5050 clock->m1 = 16;
5051 clock->m2 = 8;
5052 } else if (adjusted_mode->clock >= 140500
5053 && adjusted_mode->clock <= 200000) {
5054 clock->p1 = 1;
5055 clock->p2 = 10;
5056 clock->n = 6;
5057 clock->m1 = 12;
5058 clock->m2 = 8;
5059 }
5060 }
5061
5062 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5063 intel_clock_t *clock,
5064 intel_clock_t *reduced_clock)
5065 {
5066 struct drm_device *dev = crtc->dev;
5067 struct drm_i915_private *dev_priv = dev->dev_private;
5068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5069 int pipe = intel_crtc->pipe;
5070 u32 fp, fp2 = 0;
5071
5072 if (IS_PINEVIEW(dev)) {
5073 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5074 if (reduced_clock)
5075 fp2 = (1 << reduced_clock->n) << 16 |
5076 reduced_clock->m1 << 8 | reduced_clock->m2;
5077 } else {
5078 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5079 if (reduced_clock)
5080 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5081 reduced_clock->m2;
5082 }
5083
5084 I915_WRITE(FP0(pipe), fp);
5085
5086 intel_crtc->lowfreq_avail = false;
5087 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5088 reduced_clock && i915_powersave) {
5089 I915_WRITE(FP1(pipe), fp2);
5090 intel_crtc->lowfreq_avail = true;
5091 } else {
5092 I915_WRITE(FP1(pipe), fp);
5093 }
5094 }
5095
5096 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5097 struct drm_display_mode *mode,
5098 struct drm_display_mode *adjusted_mode,
5099 int x, int y,
5100 struct drm_framebuffer *old_fb)
5101 {
5102 struct drm_device *dev = crtc->dev;
5103 struct drm_i915_private *dev_priv = dev->dev_private;
5104 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5105 int pipe = intel_crtc->pipe;
5106 int plane = intel_crtc->plane;
5107 int refclk, num_connectors = 0;
5108 intel_clock_t clock, reduced_clock;
5109 u32 dpll, dspcntr, pipeconf;
5110 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
5111 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5112 struct drm_mode_config *mode_config = &dev->mode_config;
5113 struct intel_encoder *encoder;
5114 const intel_limit_t *limit;
5115 int ret;
5116 u32 temp;
5117 u32 lvds_sync = 0;
5118
5119 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5120 if (encoder->base.crtc != crtc)
5121 continue;
5122
5123 switch (encoder->type) {
5124 case INTEL_OUTPUT_LVDS:
5125 is_lvds = true;
5126 break;
5127 case INTEL_OUTPUT_SDVO:
5128 case INTEL_OUTPUT_HDMI:
5129 is_sdvo = true;
5130 if (encoder->needs_tv_clock)
5131 is_tv = true;
5132 break;
5133 case INTEL_OUTPUT_DVO:
5134 is_dvo = true;
5135 break;
5136 case INTEL_OUTPUT_TVOUT:
5137 is_tv = true;
5138 break;
5139 case INTEL_OUTPUT_ANALOG:
5140 is_crt = true;
5141 break;
5142 case INTEL_OUTPUT_DISPLAYPORT:
5143 is_dp = true;
5144 break;
5145 }
5146
5147 num_connectors++;
5148 }
5149
5150 refclk = i9xx_get_refclk(crtc, num_connectors);
5151
5152 /*
5153 * Returns a set of divisors for the desired target clock with the given
5154 * refclk, or FALSE. The returned values represent the clock equation:
5155 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5156 */
5157 limit = intel_limit(crtc, refclk);
5158 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5159 &clock);
5160 if (!ok) {
5161 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5162 return -EINVAL;
5163 }
5164
5165 /* Ensure that the cursor is valid for the new mode before changing... */
5166 intel_crtc_update_cursor(crtc, true);
5167
5168 if (is_lvds && dev_priv->lvds_downclock_avail) {
5169 /*
5170 * Ensure we match the reduced clock's P to the target clock.
5171 * If the clocks don't match, we can't switch the display clock
5172 * by using the FP0/FP1. In such case we will disable the LVDS
5173 * downclock feature.
5174 */
5175 has_reduced_clock = limit->find_pll(limit, crtc,
5176 dev_priv->lvds_downclock,
5177 refclk,
5178 &clock,
5179 &reduced_clock);
5180 }
5181
5182 if (is_sdvo && is_tv)
5183 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
5184
5185 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5186 &reduced_clock : NULL);
5187
5188 dpll = DPLL_VGA_MODE_DIS;
5189
5190 if (!IS_GEN2(dev)) {
5191 if (is_lvds)
5192 dpll |= DPLLB_MODE_LVDS;
5193 else
5194 dpll |= DPLLB_MODE_DAC_SERIAL;
5195 if (is_sdvo) {
5196 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5197 if (pixel_multiplier > 1) {
5198 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5199 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
5200 }
5201 dpll |= DPLL_DVO_HIGH_SPEED;
5202 }
5203 if (is_dp)
5204 dpll |= DPLL_DVO_HIGH_SPEED;
5205
5206 /* compute bitmask from p1 value */
5207 if (IS_PINEVIEW(dev))
5208 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5209 else {
5210 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5211 if (IS_G4X(dev) && has_reduced_clock)
5212 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5213 }
5214 switch (clock.p2) {
5215 case 5:
5216 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5217 break;
5218 case 7:
5219 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5220 break;
5221 case 10:
5222 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5223 break;
5224 case 14:
5225 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5226 break;
5227 }
5228 if (INTEL_INFO(dev)->gen >= 4)
5229 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5230 } else {
5231 if (is_lvds) {
5232 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5233 } else {
5234 if (clock.p1 == 2)
5235 dpll |= PLL_P1_DIVIDE_BY_TWO;
5236 else
5237 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5238 if (clock.p2 == 4)
5239 dpll |= PLL_P2_DIVIDE_BY_4;
5240 }
5241 }
5242
5243 if (is_sdvo && is_tv)
5244 dpll |= PLL_REF_INPUT_TVCLKINBC;
5245 else if (is_tv)
5246 /* XXX: just matching BIOS for now */
5247 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5248 dpll |= 3;
5249 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5250 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5251 else
5252 dpll |= PLL_REF_INPUT_DREFCLK;
5253
5254 /* setup pipeconf */
5255 pipeconf = I915_READ(PIPECONF(pipe));
5256
5257 /* Set up the display plane register */
5258 dspcntr = DISPPLANE_GAMMA_ENABLE;
5259
5260 if (pipe == 0)
5261 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5262 else
5263 dspcntr |= DISPPLANE_SEL_PIPE_B;
5264
5265 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5266 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5267 * core speed.
5268 *
5269 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5270 * pipe == 0 check?
5271 */
5272 if (mode->clock >
5273 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5274 pipeconf |= PIPECONF_DOUBLE_WIDE;
5275 else
5276 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5277 }
5278
5279 /* default to 8bpc */
5280 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5281 if (is_dp) {
5282 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5283 pipeconf |= PIPECONF_BPP_6 |
5284 PIPECONF_DITHER_EN |
5285 PIPECONF_DITHER_TYPE_SP;
5286 }
5287 }
5288
5289 dpll |= DPLL_VCO_ENABLE;
5290
5291 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5292 drm_mode_debug_printmodeline(mode);
5293
5294 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5295
5296 POSTING_READ(DPLL(pipe));
5297 udelay(150);
5298
5299 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5300 * This is an exception to the general rule that mode_set doesn't turn
5301 * things on.
5302 */
5303 if (is_lvds) {
5304 temp = I915_READ(LVDS);
5305 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5306 if (pipe == 1) {
5307 temp |= LVDS_PIPEB_SELECT;
5308 } else {
5309 temp &= ~LVDS_PIPEB_SELECT;
5310 }
5311 /* set the corresponsding LVDS_BORDER bit */
5312 temp |= dev_priv->lvds_border_bits;
5313 /* Set the B0-B3 data pairs corresponding to whether we're going to
5314 * set the DPLLs for dual-channel mode or not.
5315 */
5316 if (clock.p2 == 7)
5317 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5318 else
5319 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5320
5321 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5322 * appropriately here, but we need to look more thoroughly into how
5323 * panels behave in the two modes.
5324 */
5325 /* set the dithering flag on LVDS as needed */
5326 if (INTEL_INFO(dev)->gen >= 4) {
5327 if (dev_priv->lvds_dither)
5328 temp |= LVDS_ENABLE_DITHER;
5329 else
5330 temp &= ~LVDS_ENABLE_DITHER;
5331 }
5332 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5333 lvds_sync |= LVDS_HSYNC_POLARITY;
5334 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5335 lvds_sync |= LVDS_VSYNC_POLARITY;
5336 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5337 != lvds_sync) {
5338 char flags[2] = "-+";
5339 DRM_INFO("Changing LVDS panel from "
5340 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5341 flags[!(temp & LVDS_HSYNC_POLARITY)],
5342 flags[!(temp & LVDS_VSYNC_POLARITY)],
5343 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5344 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5345 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5346 temp |= lvds_sync;
5347 }
5348 I915_WRITE(LVDS, temp);
5349 }
5350
5351 if (is_dp) {
5352 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5353 }
5354
5355 I915_WRITE(DPLL(pipe), dpll);
5356
5357 /* Wait for the clocks to stabilize. */
5358 POSTING_READ(DPLL(pipe));
5359 udelay(150);
5360
5361 if (INTEL_INFO(dev)->gen >= 4) {
5362 temp = 0;
5363 if (is_sdvo) {
5364 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5365 if (temp > 1)
5366 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5367 else
5368 temp = 0;
5369 }
5370 I915_WRITE(DPLL_MD(pipe), temp);
5371 } else {
5372 /* The pixel multiplier can only be updated once the
5373 * DPLL is enabled and the clocks are stable.
5374 *
5375 * So write it again.
5376 */
5377 I915_WRITE(DPLL(pipe), dpll);
5378 }
5379
5380 if (HAS_PIPE_CXSR(dev)) {
5381 if (intel_crtc->lowfreq_avail) {
5382 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5383 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5384 } else {
5385 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5386 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5387 }
5388 }
5389
5390 pipeconf &= ~PIPECONF_INTERLACE_MASK;
5391 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5392 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5393 /* the chip adds 2 halflines automatically */
5394 adjusted_mode->crtc_vdisplay -= 1;
5395 adjusted_mode->crtc_vtotal -= 1;
5396 adjusted_mode->crtc_vblank_start -= 1;
5397 adjusted_mode->crtc_vblank_end -= 1;
5398 adjusted_mode->crtc_vsync_end -= 1;
5399 adjusted_mode->crtc_vsync_start -= 1;
5400 } else
5401 pipeconf |= PIPECONF_PROGRESSIVE;
5402
5403 I915_WRITE(HTOTAL(pipe),
5404 (adjusted_mode->crtc_hdisplay - 1) |
5405 ((adjusted_mode->crtc_htotal - 1) << 16));
5406 I915_WRITE(HBLANK(pipe),
5407 (adjusted_mode->crtc_hblank_start - 1) |
5408 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5409 I915_WRITE(HSYNC(pipe),
5410 (adjusted_mode->crtc_hsync_start - 1) |
5411 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5412
5413 I915_WRITE(VTOTAL(pipe),
5414 (adjusted_mode->crtc_vdisplay - 1) |
5415 ((adjusted_mode->crtc_vtotal - 1) << 16));
5416 I915_WRITE(VBLANK(pipe),
5417 (adjusted_mode->crtc_vblank_start - 1) |
5418 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5419 I915_WRITE(VSYNC(pipe),
5420 (adjusted_mode->crtc_vsync_start - 1) |
5421 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5422
5423 /* pipesrc and dspsize control the size that is scaled from,
5424 * which should always be the user's requested size.
5425 */
5426 I915_WRITE(DSPSIZE(plane),
5427 ((mode->vdisplay - 1) << 16) |
5428 (mode->hdisplay - 1));
5429 I915_WRITE(DSPPOS(plane), 0);
5430 I915_WRITE(PIPESRC(pipe),
5431 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5432
5433 I915_WRITE(PIPECONF(pipe), pipeconf);
5434 POSTING_READ(PIPECONF(pipe));
5435 intel_enable_pipe(dev_priv, pipe, false);
5436
5437 intel_wait_for_vblank(dev, pipe);
5438
5439 I915_WRITE(DSPCNTR(plane), dspcntr);
5440 POSTING_READ(DSPCNTR(plane));
5441 intel_enable_plane(dev_priv, plane, pipe);
5442
5443 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5444
5445 intel_update_watermarks(dev);
5446
5447 return ret;
5448 }
5449
5450 /*
5451 * Initialize reference clocks when the driver loads
5452 */
5453 void ironlake_init_pch_refclk(struct drm_device *dev)
5454 {
5455 struct drm_i915_private *dev_priv = dev->dev_private;
5456 struct drm_mode_config *mode_config = &dev->mode_config;
5457 struct intel_encoder *encoder;
5458 u32 temp;
5459 bool has_lvds = false;
5460 bool has_cpu_edp = false;
5461 bool has_pch_edp = false;
5462 bool has_panel = false;
5463 bool has_ck505 = false;
5464 bool can_ssc = false;
5465
5466 /* We need to take the global config into account */
5467 list_for_each_entry(encoder, &mode_config->encoder_list,
5468 base.head) {
5469 switch (encoder->type) {
5470 case INTEL_OUTPUT_LVDS:
5471 has_panel = true;
5472 has_lvds = true;
5473 break;
5474 case INTEL_OUTPUT_EDP:
5475 has_panel = true;
5476 if (intel_encoder_is_pch_edp(&encoder->base))
5477 has_pch_edp = true;
5478 else
5479 has_cpu_edp = true;
5480 break;
5481 }
5482 }
5483
5484 if (HAS_PCH_IBX(dev)) {
5485 has_ck505 = dev_priv->display_clock_mode;
5486 can_ssc = has_ck505;
5487 } else {
5488 has_ck505 = false;
5489 can_ssc = true;
5490 }
5491
5492 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5493 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5494 has_ck505);
5495
5496 /* Ironlake: try to setup display ref clock before DPLL
5497 * enabling. This is only under driver's control after
5498 * PCH B stepping, previous chipset stepping should be
5499 * ignoring this setting.
5500 */
5501 temp = I915_READ(PCH_DREF_CONTROL);
5502 /* Always enable nonspread source */
5503 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5504
5505 if (has_ck505)
5506 temp |= DREF_NONSPREAD_CK505_ENABLE;
5507 else
5508 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5509
5510 if (has_panel) {
5511 temp &= ~DREF_SSC_SOURCE_MASK;
5512 temp |= DREF_SSC_SOURCE_ENABLE;
5513
5514 /* SSC must be turned on before enabling the CPU output */
5515 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5516 DRM_DEBUG_KMS("Using SSC on panel\n");
5517 temp |= DREF_SSC1_ENABLE;
5518 }
5519
5520 /* Get SSC going before enabling the outputs */
5521 I915_WRITE(PCH_DREF_CONTROL, temp);
5522 POSTING_READ(PCH_DREF_CONTROL);
5523 udelay(200);
5524
5525 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5526
5527 /* Enable CPU source on CPU attached eDP */
5528 if (has_cpu_edp) {
5529 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5530 DRM_DEBUG_KMS("Using SSC on eDP\n");
5531 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5532 }
5533 else
5534 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5535 } else
5536 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5537
5538 I915_WRITE(PCH_DREF_CONTROL, temp);
5539 POSTING_READ(PCH_DREF_CONTROL);
5540 udelay(200);
5541 } else {
5542 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5543
5544 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5545
5546 /* Turn off CPU output */
5547 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5548
5549 I915_WRITE(PCH_DREF_CONTROL, temp);
5550 POSTING_READ(PCH_DREF_CONTROL);
5551 udelay(200);
5552
5553 /* Turn off the SSC source */
5554 temp &= ~DREF_SSC_SOURCE_MASK;
5555 temp |= DREF_SSC_SOURCE_DISABLE;
5556
5557 /* Turn off SSC1 */
5558 temp &= ~ DREF_SSC1_ENABLE;
5559
5560 I915_WRITE(PCH_DREF_CONTROL, temp);
5561 POSTING_READ(PCH_DREF_CONTROL);
5562 udelay(200);
5563 }
5564 }
5565
5566 static int ironlake_get_refclk(struct drm_crtc *crtc)
5567 {
5568 struct drm_device *dev = crtc->dev;
5569 struct drm_i915_private *dev_priv = dev->dev_private;
5570 struct intel_encoder *encoder;
5571 struct drm_mode_config *mode_config = &dev->mode_config;
5572 struct intel_encoder *edp_encoder = NULL;
5573 int num_connectors = 0;
5574 bool is_lvds = false;
5575
5576 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5577 if (encoder->base.crtc != crtc)
5578 continue;
5579
5580 switch (encoder->type) {
5581 case INTEL_OUTPUT_LVDS:
5582 is_lvds = true;
5583 break;
5584 case INTEL_OUTPUT_EDP:
5585 edp_encoder = encoder;
5586 break;
5587 }
5588 num_connectors++;
5589 }
5590
5591 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5592 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5593 dev_priv->lvds_ssc_freq);
5594 return dev_priv->lvds_ssc_freq * 1000;
5595 }
5596
5597 return 120000;
5598 }
5599
5600 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5601 struct drm_display_mode *mode,
5602 struct drm_display_mode *adjusted_mode,
5603 int x, int y,
5604 struct drm_framebuffer *old_fb)
5605 {
5606 struct drm_device *dev = crtc->dev;
5607 struct drm_i915_private *dev_priv = dev->dev_private;
5608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5609 int pipe = intel_crtc->pipe;
5610 int plane = intel_crtc->plane;
5611 int refclk, num_connectors = 0;
5612 intel_clock_t clock, reduced_clock;
5613 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5614 bool ok, has_reduced_clock = false, is_sdvo = false;
5615 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5616 struct intel_encoder *has_edp_encoder = NULL;
5617 struct drm_mode_config *mode_config = &dev->mode_config;
5618 struct intel_encoder *encoder;
5619 const intel_limit_t *limit;
5620 int ret;
5621 struct fdi_m_n m_n = {0};
5622 u32 temp;
5623 u32 lvds_sync = 0;
5624 int target_clock, pixel_multiplier, lane, link_bw, factor;
5625 unsigned int pipe_bpp;
5626 bool dither;
5627
5628 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5629 if (encoder->base.crtc != crtc)
5630 continue;
5631
5632 switch (encoder->type) {
5633 case INTEL_OUTPUT_LVDS:
5634 is_lvds = true;
5635 break;
5636 case INTEL_OUTPUT_SDVO:
5637 case INTEL_OUTPUT_HDMI:
5638 is_sdvo = true;
5639 if (encoder->needs_tv_clock)
5640 is_tv = true;
5641 break;
5642 case INTEL_OUTPUT_TVOUT:
5643 is_tv = true;
5644 break;
5645 case INTEL_OUTPUT_ANALOG:
5646 is_crt = true;
5647 break;
5648 case INTEL_OUTPUT_DISPLAYPORT:
5649 is_dp = true;
5650 break;
5651 case INTEL_OUTPUT_EDP:
5652 has_edp_encoder = encoder;
5653 break;
5654 }
5655
5656 num_connectors++;
5657 }
5658
5659 refclk = ironlake_get_refclk(crtc);
5660
5661 /*
5662 * Returns a set of divisors for the desired target clock with the given
5663 * refclk, or FALSE. The returned values represent the clock equation:
5664 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5665 */
5666 limit = intel_limit(crtc, refclk);
5667 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5668 &clock);
5669 if (!ok) {
5670 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5671 return -EINVAL;
5672 }
5673
5674 /* Ensure that the cursor is valid for the new mode before changing... */
5675 intel_crtc_update_cursor(crtc, true);
5676
5677 if (is_lvds && dev_priv->lvds_downclock_avail) {
5678 /*
5679 * Ensure we match the reduced clock's P to the target clock.
5680 * If the clocks don't match, we can't switch the display clock
5681 * by using the FP0/FP1. In such case we will disable the LVDS
5682 * downclock feature.
5683 */
5684 has_reduced_clock = limit->find_pll(limit, crtc,
5685 dev_priv->lvds_downclock,
5686 refclk,
5687 &clock,
5688 &reduced_clock);
5689 }
5690 /* SDVO TV has fixed PLL values depend on its clock range,
5691 this mirrors vbios setting. */
5692 if (is_sdvo && is_tv) {
5693 if (adjusted_mode->clock >= 100000
5694 && adjusted_mode->clock < 140500) {
5695 clock.p1 = 2;
5696 clock.p2 = 10;
5697 clock.n = 3;
5698 clock.m1 = 16;
5699 clock.m2 = 8;
5700 } else if (adjusted_mode->clock >= 140500
5701 && adjusted_mode->clock <= 200000) {
5702 clock.p1 = 1;
5703 clock.p2 = 10;
5704 clock.n = 6;
5705 clock.m1 = 12;
5706 clock.m2 = 8;
5707 }
5708 }
5709
5710 /* FDI link */
5711 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5712 lane = 0;
5713 /* CPU eDP doesn't require FDI link, so just set DP M/N
5714 according to current link config */
5715 if (has_edp_encoder &&
5716 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5717 target_clock = mode->clock;
5718 intel_edp_link_config(has_edp_encoder,
5719 &lane, &link_bw);
5720 } else {
5721 /* [e]DP over FDI requires target mode clock
5722 instead of link clock */
5723 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5724 target_clock = mode->clock;
5725 else
5726 target_clock = adjusted_mode->clock;
5727
5728 /* FDI is a binary signal running at ~2.7GHz, encoding
5729 * each output octet as 10 bits. The actual frequency
5730 * is stored as a divider into a 100MHz clock, and the
5731 * mode pixel clock is stored in units of 1KHz.
5732 * Hence the bw of each lane in terms of the mode signal
5733 * is:
5734 */
5735 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5736 }
5737
5738 /* determine panel color depth */
5739 temp = I915_READ(PIPECONF(pipe));
5740 temp &= ~PIPE_BPC_MASK;
5741 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5742 switch (pipe_bpp) {
5743 case 18:
5744 temp |= PIPE_6BPC;
5745 break;
5746 case 24:
5747 temp |= PIPE_8BPC;
5748 break;
5749 case 30:
5750 temp |= PIPE_10BPC;
5751 break;
5752 case 36:
5753 temp |= PIPE_12BPC;
5754 break;
5755 default:
5756 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5757 pipe_bpp);
5758 temp |= PIPE_8BPC;
5759 pipe_bpp = 24;
5760 break;
5761 }
5762
5763 intel_crtc->bpp = pipe_bpp;
5764 I915_WRITE(PIPECONF(pipe), temp);
5765
5766 if (!lane) {
5767 /*
5768 * Account for spread spectrum to avoid
5769 * oversubscribing the link. Max center spread
5770 * is 2.5%; use 5% for safety's sake.
5771 */
5772 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5773 lane = bps / (link_bw * 8) + 1;
5774 }
5775
5776 intel_crtc->fdi_lanes = lane;
5777
5778 if (pixel_multiplier > 1)
5779 link_bw *= pixel_multiplier;
5780 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5781 &m_n);
5782
5783 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5784 if (has_reduced_clock)
5785 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5786 reduced_clock.m2;
5787
5788 /* Enable autotuning of the PLL clock (if permissible) */
5789 factor = 21;
5790 if (is_lvds) {
5791 if ((intel_panel_use_ssc(dev_priv) &&
5792 dev_priv->lvds_ssc_freq == 100) ||
5793 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5794 factor = 25;
5795 } else if (is_sdvo && is_tv)
5796 factor = 20;
5797
5798 if (clock.m < factor * clock.n)
5799 fp |= FP_CB_TUNE;
5800
5801 dpll = 0;
5802
5803 if (is_lvds)
5804 dpll |= DPLLB_MODE_LVDS;
5805 else
5806 dpll |= DPLLB_MODE_DAC_SERIAL;
5807 if (is_sdvo) {
5808 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5809 if (pixel_multiplier > 1) {
5810 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5811 }
5812 dpll |= DPLL_DVO_HIGH_SPEED;
5813 }
5814 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5815 dpll |= DPLL_DVO_HIGH_SPEED;
5816
5817 /* compute bitmask from p1 value */
5818 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5819 /* also FPA1 */
5820 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5821
5822 switch (clock.p2) {
5823 case 5:
5824 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5825 break;
5826 case 7:
5827 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5828 break;
5829 case 10:
5830 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5831 break;
5832 case 14:
5833 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5834 break;
5835 }
5836
5837 if (is_sdvo && is_tv)
5838 dpll |= PLL_REF_INPUT_TVCLKINBC;
5839 else if (is_tv)
5840 /* XXX: just matching BIOS for now */
5841 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5842 dpll |= 3;
5843 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5844 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5845 else
5846 dpll |= PLL_REF_INPUT_DREFCLK;
5847
5848 /* setup pipeconf */
5849 pipeconf = I915_READ(PIPECONF(pipe));
5850
5851 /* Set up the display plane register */
5852 dspcntr = DISPPLANE_GAMMA_ENABLE;
5853
5854 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5855 drm_mode_debug_printmodeline(mode);
5856
5857 /* PCH eDP needs FDI, but CPU eDP does not */
5858 if (!intel_crtc->no_pll) {
5859 if (!has_edp_encoder ||
5860 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5861 I915_WRITE(PCH_FP0(pipe), fp);
5862 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5863
5864 POSTING_READ(PCH_DPLL(pipe));
5865 udelay(150);
5866 }
5867 } else {
5868 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5869 fp == I915_READ(PCH_FP0(0))) {
5870 intel_crtc->use_pll_a = true;
5871 DRM_DEBUG_KMS("using pipe a dpll\n");
5872 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5873 fp == I915_READ(PCH_FP0(1))) {
5874 intel_crtc->use_pll_a = false;
5875 DRM_DEBUG_KMS("using pipe b dpll\n");
5876 } else {
5877 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5878 return -EINVAL;
5879 }
5880 }
5881
5882 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5883 * This is an exception to the general rule that mode_set doesn't turn
5884 * things on.
5885 */
5886 if (is_lvds) {
5887 temp = I915_READ(PCH_LVDS);
5888 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5889 if (HAS_PCH_CPT(dev)) {
5890 temp &= ~PORT_TRANS_SEL_MASK;
5891 temp |= PORT_TRANS_SEL_CPT(pipe);
5892 } else {
5893 if (pipe == 1)
5894 temp |= LVDS_PIPEB_SELECT;
5895 else
5896 temp &= ~LVDS_PIPEB_SELECT;
5897 }
5898
5899 /* set the corresponsding LVDS_BORDER bit */
5900 temp |= dev_priv->lvds_border_bits;
5901 /* Set the B0-B3 data pairs corresponding to whether we're going to
5902 * set the DPLLs for dual-channel mode or not.
5903 */
5904 if (clock.p2 == 7)
5905 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5906 else
5907 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5908
5909 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5910 * appropriately here, but we need to look more thoroughly into how
5911 * panels behave in the two modes.
5912 */
5913 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5914 lvds_sync |= LVDS_HSYNC_POLARITY;
5915 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5916 lvds_sync |= LVDS_VSYNC_POLARITY;
5917 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5918 != lvds_sync) {
5919 char flags[2] = "-+";
5920 DRM_INFO("Changing LVDS panel from "
5921 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5922 flags[!(temp & LVDS_HSYNC_POLARITY)],
5923 flags[!(temp & LVDS_VSYNC_POLARITY)],
5924 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5925 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5926 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5927 temp |= lvds_sync;
5928 }
5929 I915_WRITE(PCH_LVDS, temp);
5930 }
5931
5932 pipeconf &= ~PIPECONF_DITHER_EN;
5933 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5934 if ((is_lvds && dev_priv->lvds_dither) || dither) {
5935 pipeconf |= PIPECONF_DITHER_EN;
5936 pipeconf |= PIPECONF_DITHER_TYPE_SP;
5937 }
5938 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5939 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5940 } else {
5941 /* For non-DP output, clear any trans DP clock recovery setting.*/
5942 I915_WRITE(TRANSDATA_M1(pipe), 0);
5943 I915_WRITE(TRANSDATA_N1(pipe), 0);
5944 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5945 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5946 }
5947
5948 if (!intel_crtc->no_pll &&
5949 (!has_edp_encoder ||
5950 intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
5951 I915_WRITE(PCH_DPLL(pipe), dpll);
5952
5953 /* Wait for the clocks to stabilize. */
5954 POSTING_READ(PCH_DPLL(pipe));
5955 udelay(150);
5956
5957 /* The pixel multiplier can only be updated once the
5958 * DPLL is enabled and the clocks are stable.
5959 *
5960 * So write it again.
5961 */
5962 I915_WRITE(PCH_DPLL(pipe), dpll);
5963 }
5964
5965 intel_crtc->lowfreq_avail = false;
5966 if (!intel_crtc->no_pll) {
5967 if (is_lvds && has_reduced_clock && i915_powersave) {
5968 I915_WRITE(PCH_FP1(pipe), fp2);
5969 intel_crtc->lowfreq_avail = true;
5970 if (HAS_PIPE_CXSR(dev)) {
5971 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5972 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5973 }
5974 } else {
5975 I915_WRITE(PCH_FP1(pipe), fp);
5976 if (HAS_PIPE_CXSR(dev)) {
5977 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5978 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5979 }
5980 }
5981 }
5982
5983 pipeconf &= ~PIPECONF_INTERLACE_MASK;
5984 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5985 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5986 /* the chip adds 2 halflines automatically */
5987 adjusted_mode->crtc_vdisplay -= 1;
5988 adjusted_mode->crtc_vtotal -= 1;
5989 adjusted_mode->crtc_vblank_start -= 1;
5990 adjusted_mode->crtc_vblank_end -= 1;
5991 adjusted_mode->crtc_vsync_end -= 1;
5992 adjusted_mode->crtc_vsync_start -= 1;
5993 } else
5994 pipeconf |= PIPECONF_PROGRESSIVE;
5995
5996 I915_WRITE(HTOTAL(pipe),
5997 (adjusted_mode->crtc_hdisplay - 1) |
5998 ((adjusted_mode->crtc_htotal - 1) << 16));
5999 I915_WRITE(HBLANK(pipe),
6000 (adjusted_mode->crtc_hblank_start - 1) |
6001 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6002 I915_WRITE(HSYNC(pipe),
6003 (adjusted_mode->crtc_hsync_start - 1) |
6004 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6005
6006 I915_WRITE(VTOTAL(pipe),
6007 (adjusted_mode->crtc_vdisplay - 1) |
6008 ((adjusted_mode->crtc_vtotal - 1) << 16));
6009 I915_WRITE(VBLANK(pipe),
6010 (adjusted_mode->crtc_vblank_start - 1) |
6011 ((adjusted_mode->crtc_vblank_end - 1) << 16));
6012 I915_WRITE(VSYNC(pipe),
6013 (adjusted_mode->crtc_vsync_start - 1) |
6014 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6015
6016 /* pipesrc controls the size that is scaled from, which should
6017 * always be the user's requested size.
6018 */
6019 I915_WRITE(PIPESRC(pipe),
6020 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
6021
6022 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
6023 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
6024 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
6025 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
6026
6027 if (has_edp_encoder &&
6028 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6029 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
6030 }
6031
6032 I915_WRITE(PIPECONF(pipe), pipeconf);
6033 POSTING_READ(PIPECONF(pipe));
6034
6035 intel_wait_for_vblank(dev, pipe);
6036
6037 I915_WRITE(DSPCNTR(plane), dspcntr);
6038 POSTING_READ(DSPCNTR(plane));
6039
6040 ret = intel_pipe_set_base(crtc, x, y, old_fb);
6041
6042 intel_update_watermarks(dev);
6043
6044 return ret;
6045 }
6046
6047 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6048 struct drm_display_mode *mode,
6049 struct drm_display_mode *adjusted_mode,
6050 int x, int y,
6051 struct drm_framebuffer *old_fb)
6052 {
6053 struct drm_device *dev = crtc->dev;
6054 struct drm_i915_private *dev_priv = dev->dev_private;
6055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6056 int pipe = intel_crtc->pipe;
6057 int ret;
6058
6059 drm_vblank_pre_modeset(dev, pipe);
6060
6061 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
6062 x, y, old_fb);
6063 drm_vblank_post_modeset(dev, pipe);
6064
6065 if (ret)
6066 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
6067 else
6068 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
6069
6070 return ret;
6071 }
6072
6073 static bool intel_eld_uptodate(struct drm_connector *connector,
6074 int reg_eldv, uint32_t bits_eldv,
6075 int reg_elda, uint32_t bits_elda,
6076 int reg_edid)
6077 {
6078 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6079 uint8_t *eld = connector->eld;
6080 uint32_t i;
6081
6082 i = I915_READ(reg_eldv);
6083 i &= bits_eldv;
6084
6085 if (!eld[0])
6086 return !i;
6087
6088 if (!i)
6089 return false;
6090
6091 i = I915_READ(reg_elda);
6092 i &= ~bits_elda;
6093 I915_WRITE(reg_elda, i);
6094
6095 for (i = 0; i < eld[2]; i++)
6096 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6097 return false;
6098
6099 return true;
6100 }
6101
6102 static void g4x_write_eld(struct drm_connector *connector,
6103 struct drm_crtc *crtc)
6104 {
6105 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6106 uint8_t *eld = connector->eld;
6107 uint32_t eldv;
6108 uint32_t len;
6109 uint32_t i;
6110
6111 i = I915_READ(G4X_AUD_VID_DID);
6112
6113 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6114 eldv = G4X_ELDV_DEVCL_DEVBLC;
6115 else
6116 eldv = G4X_ELDV_DEVCTG;
6117
6118 if (intel_eld_uptodate(connector,
6119 G4X_AUD_CNTL_ST, eldv,
6120 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6121 G4X_HDMIW_HDMIEDID))
6122 return;
6123
6124 i = I915_READ(G4X_AUD_CNTL_ST);
6125 i &= ~(eldv | G4X_ELD_ADDR);
6126 len = (i >> 9) & 0x1f; /* ELD buffer size */
6127 I915_WRITE(G4X_AUD_CNTL_ST, i);
6128
6129 if (!eld[0])
6130 return;
6131
6132 len = min_t(uint8_t, eld[2], len);
6133 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6134 for (i = 0; i < len; i++)
6135 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6136
6137 i = I915_READ(G4X_AUD_CNTL_ST);
6138 i |= eldv;
6139 I915_WRITE(G4X_AUD_CNTL_ST, i);
6140 }
6141
6142 static void ironlake_write_eld(struct drm_connector *connector,
6143 struct drm_crtc *crtc)
6144 {
6145 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6146 uint8_t *eld = connector->eld;
6147 uint32_t eldv;
6148 uint32_t i;
6149 int len;
6150 int hdmiw_hdmiedid;
6151 int aud_config;
6152 int aud_cntl_st;
6153 int aud_cntrl_st2;
6154
6155 if (HAS_PCH_IBX(connector->dev)) {
6156 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
6157 aud_config = IBX_AUD_CONFIG_A;
6158 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6159 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6160 } else {
6161 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
6162 aud_config = CPT_AUD_CONFIG_A;
6163 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6164 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6165 }
6166
6167 i = to_intel_crtc(crtc)->pipe;
6168 hdmiw_hdmiedid += i * 0x100;
6169 aud_cntl_st += i * 0x100;
6170 aud_config += i * 0x100;
6171
6172 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6173
6174 i = I915_READ(aud_cntl_st);
6175 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
6176 if (!i) {
6177 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6178 /* operate blindly on all ports */
6179 eldv = IBX_ELD_VALIDB;
6180 eldv |= IBX_ELD_VALIDB << 4;
6181 eldv |= IBX_ELD_VALIDB << 8;
6182 } else {
6183 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6184 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6185 }
6186
6187 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6188 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6189 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6190 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6191 } else
6192 I915_WRITE(aud_config, 0);
6193
6194 if (intel_eld_uptodate(connector,
6195 aud_cntrl_st2, eldv,
6196 aud_cntl_st, IBX_ELD_ADDRESS,
6197 hdmiw_hdmiedid))
6198 return;
6199
6200 i = I915_READ(aud_cntrl_st2);
6201 i &= ~eldv;
6202 I915_WRITE(aud_cntrl_st2, i);
6203
6204 if (!eld[0])
6205 return;
6206
6207 i = I915_READ(aud_cntl_st);
6208 i &= ~IBX_ELD_ADDRESS;
6209 I915_WRITE(aud_cntl_st, i);
6210
6211 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6212 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6213 for (i = 0; i < len; i++)
6214 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6215
6216 i = I915_READ(aud_cntrl_st2);
6217 i |= eldv;
6218 I915_WRITE(aud_cntrl_st2, i);
6219 }
6220
6221 void intel_write_eld(struct drm_encoder *encoder,
6222 struct drm_display_mode *mode)
6223 {
6224 struct drm_crtc *crtc = encoder->crtc;
6225 struct drm_connector *connector;
6226 struct drm_device *dev = encoder->dev;
6227 struct drm_i915_private *dev_priv = dev->dev_private;
6228
6229 connector = drm_select_eld(encoder, mode);
6230 if (!connector)
6231 return;
6232
6233 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6234 connector->base.id,
6235 drm_get_connector_name(connector),
6236 connector->encoder->base.id,
6237 drm_get_encoder_name(connector->encoder));
6238
6239 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6240
6241 if (dev_priv->display.write_eld)
6242 dev_priv->display.write_eld(connector, crtc);
6243 }
6244
6245 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6246 void intel_crtc_load_lut(struct drm_crtc *crtc)
6247 {
6248 struct drm_device *dev = crtc->dev;
6249 struct drm_i915_private *dev_priv = dev->dev_private;
6250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6251 int palreg = PALETTE(intel_crtc->pipe);
6252 int i;
6253
6254 /* The clocks have to be on to load the palette. */
6255 if (!crtc->enabled)
6256 return;
6257
6258 /* use legacy palette for Ironlake */
6259 if (HAS_PCH_SPLIT(dev))
6260 palreg = LGC_PALETTE(intel_crtc->pipe);
6261
6262 for (i = 0; i < 256; i++) {
6263 I915_WRITE(palreg + 4 * i,
6264 (intel_crtc->lut_r[i] << 16) |
6265 (intel_crtc->lut_g[i] << 8) |
6266 intel_crtc->lut_b[i]);
6267 }
6268 }
6269
6270 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6271 {
6272 struct drm_device *dev = crtc->dev;
6273 struct drm_i915_private *dev_priv = dev->dev_private;
6274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6275 bool visible = base != 0;
6276 u32 cntl;
6277
6278 if (intel_crtc->cursor_visible == visible)
6279 return;
6280
6281 cntl = I915_READ(_CURACNTR);
6282 if (visible) {
6283 /* On these chipsets we can only modify the base whilst
6284 * the cursor is disabled.
6285 */
6286 I915_WRITE(_CURABASE, base);
6287
6288 cntl &= ~(CURSOR_FORMAT_MASK);
6289 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6290 cntl |= CURSOR_ENABLE |
6291 CURSOR_GAMMA_ENABLE |
6292 CURSOR_FORMAT_ARGB;
6293 } else
6294 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6295 I915_WRITE(_CURACNTR, cntl);
6296
6297 intel_crtc->cursor_visible = visible;
6298 }
6299
6300 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6301 {
6302 struct drm_device *dev = crtc->dev;
6303 struct drm_i915_private *dev_priv = dev->dev_private;
6304 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6305 int pipe = intel_crtc->pipe;
6306 bool visible = base != 0;
6307
6308 if (intel_crtc->cursor_visible != visible) {
6309 uint32_t cntl = I915_READ(CURCNTR(pipe));
6310 if (base) {
6311 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6312 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6313 cntl |= pipe << 28; /* Connect to correct pipe */
6314 } else {
6315 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6316 cntl |= CURSOR_MODE_DISABLE;
6317 }
6318 I915_WRITE(CURCNTR(pipe), cntl);
6319
6320 intel_crtc->cursor_visible = visible;
6321 }
6322 /* and commit changes on next vblank */
6323 I915_WRITE(CURBASE(pipe), base);
6324 }
6325
6326 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6327 {
6328 struct drm_device *dev = crtc->dev;
6329 struct drm_i915_private *dev_priv = dev->dev_private;
6330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6331 int pipe = intel_crtc->pipe;
6332 bool visible = base != 0;
6333
6334 if (intel_crtc->cursor_visible != visible) {
6335 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6336 if (base) {
6337 cntl &= ~CURSOR_MODE;
6338 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6339 } else {
6340 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6341 cntl |= CURSOR_MODE_DISABLE;
6342 }
6343 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6344
6345 intel_crtc->cursor_visible = visible;
6346 }
6347 /* and commit changes on next vblank */
6348 I915_WRITE(CURBASE_IVB(pipe), base);
6349 }
6350
6351 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6352 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6353 bool on)
6354 {
6355 struct drm_device *dev = crtc->dev;
6356 struct drm_i915_private *dev_priv = dev->dev_private;
6357 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6358 int pipe = intel_crtc->pipe;
6359 int x = intel_crtc->cursor_x;
6360 int y = intel_crtc->cursor_y;
6361 u32 base, pos;
6362 bool visible;
6363
6364 pos = 0;
6365
6366 if (on && crtc->enabled && crtc->fb) {
6367 base = intel_crtc->cursor_addr;
6368 if (x > (int) crtc->fb->width)
6369 base = 0;
6370
6371 if (y > (int) crtc->fb->height)
6372 base = 0;
6373 } else
6374 base = 0;
6375
6376 if (x < 0) {
6377 if (x + intel_crtc->cursor_width < 0)
6378 base = 0;
6379
6380 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6381 x = -x;
6382 }
6383 pos |= x << CURSOR_X_SHIFT;
6384
6385 if (y < 0) {
6386 if (y + intel_crtc->cursor_height < 0)
6387 base = 0;
6388
6389 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6390 y = -y;
6391 }
6392 pos |= y << CURSOR_Y_SHIFT;
6393
6394 visible = base != 0;
6395 if (!visible && !intel_crtc->cursor_visible)
6396 return;
6397
6398 if (IS_IVYBRIDGE(dev)) {
6399 I915_WRITE(CURPOS_IVB(pipe), pos);
6400 ivb_update_cursor(crtc, base);
6401 } else {
6402 I915_WRITE(CURPOS(pipe), pos);
6403 if (IS_845G(dev) || IS_I865G(dev))
6404 i845_update_cursor(crtc, base);
6405 else
6406 i9xx_update_cursor(crtc, base);
6407 }
6408
6409 if (visible)
6410 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6411 }
6412
6413 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6414 struct drm_file *file,
6415 uint32_t handle,
6416 uint32_t width, uint32_t height)
6417 {
6418 struct drm_device *dev = crtc->dev;
6419 struct drm_i915_private *dev_priv = dev->dev_private;
6420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6421 struct drm_i915_gem_object *obj;
6422 uint32_t addr;
6423 int ret;
6424
6425 DRM_DEBUG_KMS("\n");
6426
6427 /* if we want to turn off the cursor ignore width and height */
6428 if (!handle) {
6429 DRM_DEBUG_KMS("cursor off\n");
6430 addr = 0;
6431 obj = NULL;
6432 mutex_lock(&dev->struct_mutex);
6433 goto finish;
6434 }
6435
6436 /* Currently we only support 64x64 cursors */
6437 if (width != 64 || height != 64) {
6438 DRM_ERROR("we currently only support 64x64 cursors\n");
6439 return -EINVAL;
6440 }
6441
6442 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6443 if (&obj->base == NULL)
6444 return -ENOENT;
6445
6446 if (obj->base.size < width * height * 4) {
6447 DRM_ERROR("buffer is to small\n");
6448 ret = -ENOMEM;
6449 goto fail;
6450 }
6451
6452 /* we only need to pin inside GTT if cursor is non-phy */
6453 mutex_lock(&dev->struct_mutex);
6454 if (!dev_priv->info->cursor_needs_physical) {
6455 if (obj->tiling_mode) {
6456 DRM_ERROR("cursor cannot be tiled\n");
6457 ret = -EINVAL;
6458 goto fail_locked;
6459 }
6460
6461 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6462 if (ret) {
6463 DRM_ERROR("failed to move cursor bo into the GTT\n");
6464 goto fail_locked;
6465 }
6466
6467 ret = i915_gem_object_put_fence(obj);
6468 if (ret) {
6469 DRM_ERROR("failed to release fence for cursor");
6470 goto fail_unpin;
6471 }
6472
6473 addr = obj->gtt_offset;
6474 } else {
6475 int align = IS_I830(dev) ? 16 * 1024 : 256;
6476 ret = i915_gem_attach_phys_object(dev, obj,
6477 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6478 align);
6479 if (ret) {
6480 DRM_ERROR("failed to attach phys object\n");
6481 goto fail_locked;
6482 }
6483 addr = obj->phys_obj->handle->busaddr;
6484 }
6485
6486 if (IS_GEN2(dev))
6487 I915_WRITE(CURSIZE, (height << 12) | width);
6488
6489 finish:
6490 if (intel_crtc->cursor_bo) {
6491 if (dev_priv->info->cursor_needs_physical) {
6492 if (intel_crtc->cursor_bo != obj)
6493 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6494 } else
6495 i915_gem_object_unpin(intel_crtc->cursor_bo);
6496 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6497 }
6498
6499 mutex_unlock(&dev->struct_mutex);
6500
6501 intel_crtc->cursor_addr = addr;
6502 intel_crtc->cursor_bo = obj;
6503 intel_crtc->cursor_width = width;
6504 intel_crtc->cursor_height = height;
6505
6506 intel_crtc_update_cursor(crtc, true);
6507
6508 return 0;
6509 fail_unpin:
6510 i915_gem_object_unpin(obj);
6511 fail_locked:
6512 mutex_unlock(&dev->struct_mutex);
6513 fail:
6514 drm_gem_object_unreference_unlocked(&obj->base);
6515 return ret;
6516 }
6517
6518 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6519 {
6520 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6521
6522 intel_crtc->cursor_x = x;
6523 intel_crtc->cursor_y = y;
6524
6525 intel_crtc_update_cursor(crtc, true);
6526
6527 return 0;
6528 }
6529
6530 /** Sets the color ramps on behalf of RandR */
6531 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6532 u16 blue, int regno)
6533 {
6534 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6535
6536 intel_crtc->lut_r[regno] = red >> 8;
6537 intel_crtc->lut_g[regno] = green >> 8;
6538 intel_crtc->lut_b[regno] = blue >> 8;
6539 }
6540
6541 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6542 u16 *blue, int regno)
6543 {
6544 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6545
6546 *red = intel_crtc->lut_r[regno] << 8;
6547 *green = intel_crtc->lut_g[regno] << 8;
6548 *blue = intel_crtc->lut_b[regno] << 8;
6549 }
6550
6551 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6552 u16 *blue, uint32_t start, uint32_t size)
6553 {
6554 int end = (start + size > 256) ? 256 : start + size, i;
6555 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6556
6557 for (i = start; i < end; i++) {
6558 intel_crtc->lut_r[i] = red[i] >> 8;
6559 intel_crtc->lut_g[i] = green[i] >> 8;
6560 intel_crtc->lut_b[i] = blue[i] >> 8;
6561 }
6562
6563 intel_crtc_load_lut(crtc);
6564 }
6565
6566 /**
6567 * Get a pipe with a simple mode set on it for doing load-based monitor
6568 * detection.
6569 *
6570 * It will be up to the load-detect code to adjust the pipe as appropriate for
6571 * its requirements. The pipe will be connected to no other encoders.
6572 *
6573 * Currently this code will only succeed if there is a pipe with no encoders
6574 * configured for it. In the future, it could choose to temporarily disable
6575 * some outputs to free up a pipe for its use.
6576 *
6577 * \return crtc, or NULL if no pipes are available.
6578 */
6579
6580 /* VESA 640x480x72Hz mode to set on the pipe */
6581 static struct drm_display_mode load_detect_mode = {
6582 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6583 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6584 };
6585
6586 static struct drm_framebuffer *
6587 intel_framebuffer_create(struct drm_device *dev,
6588 struct drm_mode_fb_cmd2 *mode_cmd,
6589 struct drm_i915_gem_object *obj)
6590 {
6591 struct intel_framebuffer *intel_fb;
6592 int ret;
6593
6594 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6595 if (!intel_fb) {
6596 drm_gem_object_unreference_unlocked(&obj->base);
6597 return ERR_PTR(-ENOMEM);
6598 }
6599
6600 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6601 if (ret) {
6602 drm_gem_object_unreference_unlocked(&obj->base);
6603 kfree(intel_fb);
6604 return ERR_PTR(ret);
6605 }
6606
6607 return &intel_fb->base;
6608 }
6609
6610 static u32
6611 intel_framebuffer_pitch_for_width(int width, int bpp)
6612 {
6613 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6614 return ALIGN(pitch, 64);
6615 }
6616
6617 static u32
6618 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6619 {
6620 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6621 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6622 }
6623
6624 static struct drm_framebuffer *
6625 intel_framebuffer_create_for_mode(struct drm_device *dev,
6626 struct drm_display_mode *mode,
6627 int depth, int bpp)
6628 {
6629 struct drm_i915_gem_object *obj;
6630 struct drm_mode_fb_cmd2 mode_cmd;
6631
6632 obj = i915_gem_alloc_object(dev,
6633 intel_framebuffer_size_for_mode(mode, bpp));
6634 if (obj == NULL)
6635 return ERR_PTR(-ENOMEM);
6636
6637 mode_cmd.width = mode->hdisplay;
6638 mode_cmd.height = mode->vdisplay;
6639 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6640 bpp);
6641 mode_cmd.pixel_format = 0;
6642
6643 return intel_framebuffer_create(dev, &mode_cmd, obj);
6644 }
6645
6646 static struct drm_framebuffer *
6647 mode_fits_in_fbdev(struct drm_device *dev,
6648 struct drm_display_mode *mode)
6649 {
6650 struct drm_i915_private *dev_priv = dev->dev_private;
6651 struct drm_i915_gem_object *obj;
6652 struct drm_framebuffer *fb;
6653
6654 if (dev_priv->fbdev == NULL)
6655 return NULL;
6656
6657 obj = dev_priv->fbdev->ifb.obj;
6658 if (obj == NULL)
6659 return NULL;
6660
6661 fb = &dev_priv->fbdev->ifb.base;
6662 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6663 fb->bits_per_pixel))
6664 return NULL;
6665
6666 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6667 return NULL;
6668
6669 return fb;
6670 }
6671
6672 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6673 struct drm_connector *connector,
6674 struct drm_display_mode *mode,
6675 struct intel_load_detect_pipe *old)
6676 {
6677 struct intel_crtc *intel_crtc;
6678 struct drm_crtc *possible_crtc;
6679 struct drm_encoder *encoder = &intel_encoder->base;
6680 struct drm_crtc *crtc = NULL;
6681 struct drm_device *dev = encoder->dev;
6682 struct drm_framebuffer *old_fb;
6683 int i = -1;
6684
6685 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6686 connector->base.id, drm_get_connector_name(connector),
6687 encoder->base.id, drm_get_encoder_name(encoder));
6688
6689 /*
6690 * Algorithm gets a little messy:
6691 *
6692 * - if the connector already has an assigned crtc, use it (but make
6693 * sure it's on first)
6694 *
6695 * - try to find the first unused crtc that can drive this connector,
6696 * and use that if we find one
6697 */
6698
6699 /* See if we already have a CRTC for this connector */
6700 if (encoder->crtc) {
6701 crtc = encoder->crtc;
6702
6703 intel_crtc = to_intel_crtc(crtc);
6704 old->dpms_mode = intel_crtc->dpms_mode;
6705 old->load_detect_temp = false;
6706
6707 /* Make sure the crtc and connector are running */
6708 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6709 struct drm_encoder_helper_funcs *encoder_funcs;
6710 struct drm_crtc_helper_funcs *crtc_funcs;
6711
6712 crtc_funcs = crtc->helper_private;
6713 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6714
6715 encoder_funcs = encoder->helper_private;
6716 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6717 }
6718
6719 return true;
6720 }
6721
6722 /* Find an unused one (if possible) */
6723 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6724 i++;
6725 if (!(encoder->possible_crtcs & (1 << i)))
6726 continue;
6727 if (!possible_crtc->enabled) {
6728 crtc = possible_crtc;
6729 break;
6730 }
6731 }
6732
6733 /*
6734 * If we didn't find an unused CRTC, don't use any.
6735 */
6736 if (!crtc) {
6737 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6738 return false;
6739 }
6740
6741 encoder->crtc = crtc;
6742 connector->encoder = encoder;
6743
6744 intel_crtc = to_intel_crtc(crtc);
6745 old->dpms_mode = intel_crtc->dpms_mode;
6746 old->load_detect_temp = true;
6747 old->release_fb = NULL;
6748
6749 if (!mode)
6750 mode = &load_detect_mode;
6751
6752 old_fb = crtc->fb;
6753
6754 /* We need a framebuffer large enough to accommodate all accesses
6755 * that the plane may generate whilst we perform load detection.
6756 * We can not rely on the fbcon either being present (we get called
6757 * during its initialisation to detect all boot displays, or it may
6758 * not even exist) or that it is large enough to satisfy the
6759 * requested mode.
6760 */
6761 crtc->fb = mode_fits_in_fbdev(dev, mode);
6762 if (crtc->fb == NULL) {
6763 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6764 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6765 old->release_fb = crtc->fb;
6766 } else
6767 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6768 if (IS_ERR(crtc->fb)) {
6769 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6770 crtc->fb = old_fb;
6771 return false;
6772 }
6773
6774 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6775 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6776 if (old->release_fb)
6777 old->release_fb->funcs->destroy(old->release_fb);
6778 crtc->fb = old_fb;
6779 return false;
6780 }
6781
6782 /* let the connector get through one full cycle before testing */
6783 intel_wait_for_vblank(dev, intel_crtc->pipe);
6784
6785 return true;
6786 }
6787
6788 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6789 struct drm_connector *connector,
6790 struct intel_load_detect_pipe *old)
6791 {
6792 struct drm_encoder *encoder = &intel_encoder->base;
6793 struct drm_device *dev = encoder->dev;
6794 struct drm_crtc *crtc = encoder->crtc;
6795 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6796 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6797
6798 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6799 connector->base.id, drm_get_connector_name(connector),
6800 encoder->base.id, drm_get_encoder_name(encoder));
6801
6802 if (old->load_detect_temp) {
6803 connector->encoder = NULL;
6804 drm_helper_disable_unused_functions(dev);
6805
6806 if (old->release_fb)
6807 old->release_fb->funcs->destroy(old->release_fb);
6808
6809 return;
6810 }
6811
6812 /* Switch crtc and encoder back off if necessary */
6813 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6814 encoder_funcs->dpms(encoder, old->dpms_mode);
6815 crtc_funcs->dpms(crtc, old->dpms_mode);
6816 }
6817 }
6818
6819 /* Returns the clock of the currently programmed mode of the given pipe. */
6820 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6821 {
6822 struct drm_i915_private *dev_priv = dev->dev_private;
6823 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6824 int pipe = intel_crtc->pipe;
6825 u32 dpll = I915_READ(DPLL(pipe));
6826 u32 fp;
6827 intel_clock_t clock;
6828
6829 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6830 fp = I915_READ(FP0(pipe));
6831 else
6832 fp = I915_READ(FP1(pipe));
6833
6834 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6835 if (IS_PINEVIEW(dev)) {
6836 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6837 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6838 } else {
6839 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6840 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6841 }
6842
6843 if (!IS_GEN2(dev)) {
6844 if (IS_PINEVIEW(dev))
6845 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6846 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6847 else
6848 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6849 DPLL_FPA01_P1_POST_DIV_SHIFT);
6850
6851 switch (dpll & DPLL_MODE_MASK) {
6852 case DPLLB_MODE_DAC_SERIAL:
6853 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6854 5 : 10;
6855 break;
6856 case DPLLB_MODE_LVDS:
6857 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6858 7 : 14;
6859 break;
6860 default:
6861 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6862 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6863 return 0;
6864 }
6865
6866 /* XXX: Handle the 100Mhz refclk */
6867 intel_clock(dev, 96000, &clock);
6868 } else {
6869 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6870
6871 if (is_lvds) {
6872 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6873 DPLL_FPA01_P1_POST_DIV_SHIFT);
6874 clock.p2 = 14;
6875
6876 if ((dpll & PLL_REF_INPUT_MASK) ==
6877 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6878 /* XXX: might not be 66MHz */
6879 intel_clock(dev, 66000, &clock);
6880 } else
6881 intel_clock(dev, 48000, &clock);
6882 } else {
6883 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6884 clock.p1 = 2;
6885 else {
6886 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6887 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6888 }
6889 if (dpll & PLL_P2_DIVIDE_BY_4)
6890 clock.p2 = 4;
6891 else
6892 clock.p2 = 2;
6893
6894 intel_clock(dev, 48000, &clock);
6895 }
6896 }
6897
6898 /* XXX: It would be nice to validate the clocks, but we can't reuse
6899 * i830PllIsValid() because it relies on the xf86_config connector
6900 * configuration being accurate, which it isn't necessarily.
6901 */
6902
6903 return clock.dot;
6904 }
6905
6906 /** Returns the currently programmed mode of the given pipe. */
6907 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6908 struct drm_crtc *crtc)
6909 {
6910 struct drm_i915_private *dev_priv = dev->dev_private;
6911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6912 int pipe = intel_crtc->pipe;
6913 struct drm_display_mode *mode;
6914 int htot = I915_READ(HTOTAL(pipe));
6915 int hsync = I915_READ(HSYNC(pipe));
6916 int vtot = I915_READ(VTOTAL(pipe));
6917 int vsync = I915_READ(VSYNC(pipe));
6918
6919 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6920 if (!mode)
6921 return NULL;
6922
6923 mode->clock = intel_crtc_clock_get(dev, crtc);
6924 mode->hdisplay = (htot & 0xffff) + 1;
6925 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6926 mode->hsync_start = (hsync & 0xffff) + 1;
6927 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6928 mode->vdisplay = (vtot & 0xffff) + 1;
6929 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6930 mode->vsync_start = (vsync & 0xffff) + 1;
6931 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6932
6933 drm_mode_set_name(mode);
6934 drm_mode_set_crtcinfo(mode, 0);
6935
6936 return mode;
6937 }
6938
6939 #define GPU_IDLE_TIMEOUT 500 /* ms */
6940
6941 /* When this timer fires, we've been idle for awhile */
6942 static void intel_gpu_idle_timer(unsigned long arg)
6943 {
6944 struct drm_device *dev = (struct drm_device *)arg;
6945 drm_i915_private_t *dev_priv = dev->dev_private;
6946
6947 if (!list_empty(&dev_priv->mm.active_list)) {
6948 /* Still processing requests, so just re-arm the timer. */
6949 mod_timer(&dev_priv->idle_timer, jiffies +
6950 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6951 return;
6952 }
6953
6954 dev_priv->busy = false;
6955 queue_work(dev_priv->wq, &dev_priv->idle_work);
6956 }
6957
6958 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6959
6960 static void intel_crtc_idle_timer(unsigned long arg)
6961 {
6962 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6963 struct drm_crtc *crtc = &intel_crtc->base;
6964 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6965 struct intel_framebuffer *intel_fb;
6966
6967 intel_fb = to_intel_framebuffer(crtc->fb);
6968 if (intel_fb && intel_fb->obj->active) {
6969 /* The framebuffer is still being accessed by the GPU. */
6970 mod_timer(&intel_crtc->idle_timer, jiffies +
6971 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6972 return;
6973 }
6974
6975 intel_crtc->busy = false;
6976 queue_work(dev_priv->wq, &dev_priv->idle_work);
6977 }
6978
6979 static void intel_increase_pllclock(struct drm_crtc *crtc)
6980 {
6981 struct drm_device *dev = crtc->dev;
6982 drm_i915_private_t *dev_priv = dev->dev_private;
6983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6984 int pipe = intel_crtc->pipe;
6985 int dpll_reg = DPLL(pipe);
6986 int dpll;
6987
6988 if (HAS_PCH_SPLIT(dev))
6989 return;
6990
6991 if (!dev_priv->lvds_downclock_avail)
6992 return;
6993
6994 dpll = I915_READ(dpll_reg);
6995 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6996 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6997
6998 /* Unlock panel regs */
6999 I915_WRITE(PP_CONTROL,
7000 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
7001
7002 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7003 I915_WRITE(dpll_reg, dpll);
7004 intel_wait_for_vblank(dev, pipe);
7005
7006 dpll = I915_READ(dpll_reg);
7007 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7008 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7009
7010 /* ...and lock them again */
7011 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
7012 }
7013
7014 /* Schedule downclock */
7015 mod_timer(&intel_crtc->idle_timer, jiffies +
7016 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7017 }
7018
7019 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7020 {
7021 struct drm_device *dev = crtc->dev;
7022 drm_i915_private_t *dev_priv = dev->dev_private;
7023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7024 int pipe = intel_crtc->pipe;
7025 int dpll_reg = DPLL(pipe);
7026 int dpll = I915_READ(dpll_reg);
7027
7028 if (HAS_PCH_SPLIT(dev))
7029 return;
7030
7031 if (!dev_priv->lvds_downclock_avail)
7032 return;
7033
7034 /*
7035 * Since this is called by a timer, we should never get here in
7036 * the manual case.
7037 */
7038 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7039 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7040
7041 /* Unlock panel regs */
7042 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
7043 PANEL_UNLOCK_REGS);
7044
7045 dpll |= DISPLAY_RATE_SELECT_FPA1;
7046 I915_WRITE(dpll_reg, dpll);
7047 intel_wait_for_vblank(dev, pipe);
7048 dpll = I915_READ(dpll_reg);
7049 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7050 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7051
7052 /* ...and lock them again */
7053 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
7054 }
7055
7056 }
7057
7058 /**
7059 * intel_idle_update - adjust clocks for idleness
7060 * @work: work struct
7061 *
7062 * Either the GPU or display (or both) went idle. Check the busy status
7063 * here and adjust the CRTC and GPU clocks as necessary.
7064 */
7065 static void intel_idle_update(struct work_struct *work)
7066 {
7067 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
7068 idle_work);
7069 struct drm_device *dev = dev_priv->dev;
7070 struct drm_crtc *crtc;
7071 struct intel_crtc *intel_crtc;
7072
7073 if (!i915_powersave)
7074 return;
7075
7076 mutex_lock(&dev->struct_mutex);
7077
7078 i915_update_gfx_val(dev_priv);
7079
7080 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7081 /* Skip inactive CRTCs */
7082 if (!crtc->fb)
7083 continue;
7084
7085 intel_crtc = to_intel_crtc(crtc);
7086 if (!intel_crtc->busy)
7087 intel_decrease_pllclock(crtc);
7088 }
7089
7090
7091 mutex_unlock(&dev->struct_mutex);
7092 }
7093
7094 /**
7095 * intel_mark_busy - mark the GPU and possibly the display busy
7096 * @dev: drm device
7097 * @obj: object we're operating on
7098 *
7099 * Callers can use this function to indicate that the GPU is busy processing
7100 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
7101 * buffer), we'll also mark the display as busy, so we know to increase its
7102 * clock frequency.
7103 */
7104 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
7105 {
7106 drm_i915_private_t *dev_priv = dev->dev_private;
7107 struct drm_crtc *crtc = NULL;
7108 struct intel_framebuffer *intel_fb;
7109 struct intel_crtc *intel_crtc;
7110
7111 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7112 return;
7113
7114 if (!dev_priv->busy)
7115 dev_priv->busy = true;
7116 else
7117 mod_timer(&dev_priv->idle_timer, jiffies +
7118 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7119
7120 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7121 if (!crtc->fb)
7122 continue;
7123
7124 intel_crtc = to_intel_crtc(crtc);
7125 intel_fb = to_intel_framebuffer(crtc->fb);
7126 if (intel_fb->obj == obj) {
7127 if (!intel_crtc->busy) {
7128 /* Non-busy -> busy, upclock */
7129 intel_increase_pllclock(crtc);
7130 intel_crtc->busy = true;
7131 } else {
7132 /* Busy -> busy, put off timer */
7133 mod_timer(&intel_crtc->idle_timer, jiffies +
7134 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7135 }
7136 }
7137 }
7138 }
7139
7140 static void intel_crtc_destroy(struct drm_crtc *crtc)
7141 {
7142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7143 struct drm_device *dev = crtc->dev;
7144 struct intel_unpin_work *work;
7145 unsigned long flags;
7146
7147 spin_lock_irqsave(&dev->event_lock, flags);
7148 work = intel_crtc->unpin_work;
7149 intel_crtc->unpin_work = NULL;
7150 spin_unlock_irqrestore(&dev->event_lock, flags);
7151
7152 if (work) {
7153 cancel_work_sync(&work->work);
7154 kfree(work);
7155 }
7156
7157 drm_crtc_cleanup(crtc);
7158
7159 kfree(intel_crtc);
7160 }
7161
7162 static void intel_unpin_work_fn(struct work_struct *__work)
7163 {
7164 struct intel_unpin_work *work =
7165 container_of(__work, struct intel_unpin_work, work);
7166
7167 mutex_lock(&work->dev->struct_mutex);
7168 intel_unpin_fb_obj(work->old_fb_obj);
7169 drm_gem_object_unreference(&work->pending_flip_obj->base);
7170 drm_gem_object_unreference(&work->old_fb_obj->base);
7171
7172 intel_update_fbc(work->dev);
7173 mutex_unlock(&work->dev->struct_mutex);
7174 kfree(work);
7175 }
7176
7177 static void do_intel_finish_page_flip(struct drm_device *dev,
7178 struct drm_crtc *crtc)
7179 {
7180 drm_i915_private_t *dev_priv = dev->dev_private;
7181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7182 struct intel_unpin_work *work;
7183 struct drm_i915_gem_object *obj;
7184 struct drm_pending_vblank_event *e;
7185 struct timeval tnow, tvbl;
7186 unsigned long flags;
7187
7188 /* Ignore early vblank irqs */
7189 if (intel_crtc == NULL)
7190 return;
7191
7192 do_gettimeofday(&tnow);
7193
7194 spin_lock_irqsave(&dev->event_lock, flags);
7195 work = intel_crtc->unpin_work;
7196 if (work == NULL || !work->pending) {
7197 spin_unlock_irqrestore(&dev->event_lock, flags);
7198 return;
7199 }
7200
7201 intel_crtc->unpin_work = NULL;
7202
7203 if (work->event) {
7204 e = work->event;
7205 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
7206
7207 /* Called before vblank count and timestamps have
7208 * been updated for the vblank interval of flip
7209 * completion? Need to increment vblank count and
7210 * add one videorefresh duration to returned timestamp
7211 * to account for this. We assume this happened if we
7212 * get called over 0.9 frame durations after the last
7213 * timestamped vblank.
7214 *
7215 * This calculation can not be used with vrefresh rates
7216 * below 5Hz (10Hz to be on the safe side) without
7217 * promoting to 64 integers.
7218 */
7219 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7220 9 * crtc->framedur_ns) {
7221 e->event.sequence++;
7222 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7223 crtc->framedur_ns);
7224 }
7225
7226 e->event.tv_sec = tvbl.tv_sec;
7227 e->event.tv_usec = tvbl.tv_usec;
7228
7229 list_add_tail(&e->base.link,
7230 &e->base.file_priv->event_list);
7231 wake_up_interruptible(&e->base.file_priv->event_wait);
7232 }
7233
7234 drm_vblank_put(dev, intel_crtc->pipe);
7235
7236 spin_unlock_irqrestore(&dev->event_lock, flags);
7237
7238 obj = work->old_fb_obj;
7239
7240 atomic_clear_mask(1 << intel_crtc->plane,
7241 &obj->pending_flip.counter);
7242 if (atomic_read(&obj->pending_flip) == 0)
7243 wake_up(&dev_priv->pending_flip_queue);
7244
7245 schedule_work(&work->work);
7246
7247 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7248 }
7249
7250 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7251 {
7252 drm_i915_private_t *dev_priv = dev->dev_private;
7253 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7254
7255 do_intel_finish_page_flip(dev, crtc);
7256 }
7257
7258 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7259 {
7260 drm_i915_private_t *dev_priv = dev->dev_private;
7261 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7262
7263 do_intel_finish_page_flip(dev, crtc);
7264 }
7265
7266 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7267 {
7268 drm_i915_private_t *dev_priv = dev->dev_private;
7269 struct intel_crtc *intel_crtc =
7270 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7271 unsigned long flags;
7272
7273 spin_lock_irqsave(&dev->event_lock, flags);
7274 if (intel_crtc->unpin_work) {
7275 if ((++intel_crtc->unpin_work->pending) > 1)
7276 DRM_ERROR("Prepared flip multiple times\n");
7277 } else {
7278 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7279 }
7280 spin_unlock_irqrestore(&dev->event_lock, flags);
7281 }
7282
7283 static int intel_gen2_queue_flip(struct drm_device *dev,
7284 struct drm_crtc *crtc,
7285 struct drm_framebuffer *fb,
7286 struct drm_i915_gem_object *obj)
7287 {
7288 struct drm_i915_private *dev_priv = dev->dev_private;
7289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7290 unsigned long offset;
7291 u32 flip_mask;
7292 int ret;
7293
7294 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7295 if (ret)
7296 goto out;
7297
7298 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7299 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7300
7301 ret = BEGIN_LP_RING(6);
7302 if (ret)
7303 goto out;
7304
7305 /* Can't queue multiple flips, so wait for the previous
7306 * one to finish before executing the next.
7307 */
7308 if (intel_crtc->plane)
7309 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7310 else
7311 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7312 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7313 OUT_RING(MI_NOOP);
7314 OUT_RING(MI_DISPLAY_FLIP |
7315 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7316 OUT_RING(fb->pitches[0]);
7317 OUT_RING(obj->gtt_offset + offset);
7318 OUT_RING(0); /* aux display base address, unused */
7319 ADVANCE_LP_RING();
7320 out:
7321 return ret;
7322 }
7323
7324 static int intel_gen3_queue_flip(struct drm_device *dev,
7325 struct drm_crtc *crtc,
7326 struct drm_framebuffer *fb,
7327 struct drm_i915_gem_object *obj)
7328 {
7329 struct drm_i915_private *dev_priv = dev->dev_private;
7330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7331 unsigned long offset;
7332 u32 flip_mask;
7333 int ret;
7334
7335 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7336 if (ret)
7337 goto out;
7338
7339 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7340 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7341
7342 ret = BEGIN_LP_RING(6);
7343 if (ret)
7344 goto out;
7345
7346 if (intel_crtc->plane)
7347 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7348 else
7349 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7350 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7351 OUT_RING(MI_NOOP);
7352 OUT_RING(MI_DISPLAY_FLIP_I915 |
7353 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7354 OUT_RING(fb->pitches[0]);
7355 OUT_RING(obj->gtt_offset + offset);
7356 OUT_RING(MI_NOOP);
7357
7358 ADVANCE_LP_RING();
7359 out:
7360 return ret;
7361 }
7362
7363 static int intel_gen4_queue_flip(struct drm_device *dev,
7364 struct drm_crtc *crtc,
7365 struct drm_framebuffer *fb,
7366 struct drm_i915_gem_object *obj)
7367 {
7368 struct drm_i915_private *dev_priv = dev->dev_private;
7369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7370 uint32_t pf, pipesrc;
7371 int ret;
7372
7373 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7374 if (ret)
7375 goto out;
7376
7377 ret = BEGIN_LP_RING(4);
7378 if (ret)
7379 goto out;
7380
7381 /* i965+ uses the linear or tiled offsets from the
7382 * Display Registers (which do not change across a page-flip)
7383 * so we need only reprogram the base address.
7384 */
7385 OUT_RING(MI_DISPLAY_FLIP |
7386 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7387 OUT_RING(fb->pitches[0]);
7388 OUT_RING(obj->gtt_offset | obj->tiling_mode);
7389
7390 /* XXX Enabling the panel-fitter across page-flip is so far
7391 * untested on non-native modes, so ignore it for now.
7392 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7393 */
7394 pf = 0;
7395 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7396 OUT_RING(pf | pipesrc);
7397 ADVANCE_LP_RING();
7398 out:
7399 return ret;
7400 }
7401
7402 static int intel_gen6_queue_flip(struct drm_device *dev,
7403 struct drm_crtc *crtc,
7404 struct drm_framebuffer *fb,
7405 struct drm_i915_gem_object *obj)
7406 {
7407 struct drm_i915_private *dev_priv = dev->dev_private;
7408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7409 uint32_t pf, pipesrc;
7410 int ret;
7411
7412 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7413 if (ret)
7414 goto out;
7415
7416 ret = BEGIN_LP_RING(4);
7417 if (ret)
7418 goto out;
7419
7420 OUT_RING(MI_DISPLAY_FLIP |
7421 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7422 OUT_RING(fb->pitches[0] | obj->tiling_mode);
7423 OUT_RING(obj->gtt_offset);
7424
7425 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7426 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7427 OUT_RING(pf | pipesrc);
7428 ADVANCE_LP_RING();
7429 out:
7430 return ret;
7431 }
7432
7433 /*
7434 * On gen7 we currently use the blit ring because (in early silicon at least)
7435 * the render ring doesn't give us interrpts for page flip completion, which
7436 * means clients will hang after the first flip is queued. Fortunately the
7437 * blit ring generates interrupts properly, so use it instead.
7438 */
7439 static int intel_gen7_queue_flip(struct drm_device *dev,
7440 struct drm_crtc *crtc,
7441 struct drm_framebuffer *fb,
7442 struct drm_i915_gem_object *obj)
7443 {
7444 struct drm_i915_private *dev_priv = dev->dev_private;
7445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7446 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7447 int ret;
7448
7449 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7450 if (ret)
7451 goto out;
7452
7453 ret = intel_ring_begin(ring, 4);
7454 if (ret)
7455 goto out;
7456
7457 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
7458 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7459 intel_ring_emit(ring, (obj->gtt_offset));
7460 intel_ring_emit(ring, (MI_NOOP));
7461 intel_ring_advance(ring);
7462 out:
7463 return ret;
7464 }
7465
7466 static int intel_default_queue_flip(struct drm_device *dev,
7467 struct drm_crtc *crtc,
7468 struct drm_framebuffer *fb,
7469 struct drm_i915_gem_object *obj)
7470 {
7471 return -ENODEV;
7472 }
7473
7474 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7475 struct drm_framebuffer *fb,
7476 struct drm_pending_vblank_event *event)
7477 {
7478 struct drm_device *dev = crtc->dev;
7479 struct drm_i915_private *dev_priv = dev->dev_private;
7480 struct intel_framebuffer *intel_fb;
7481 struct drm_i915_gem_object *obj;
7482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7483 struct intel_unpin_work *work;
7484 unsigned long flags;
7485 int ret;
7486
7487 work = kzalloc(sizeof *work, GFP_KERNEL);
7488 if (work == NULL)
7489 return -ENOMEM;
7490
7491 work->event = event;
7492 work->dev = crtc->dev;
7493 intel_fb = to_intel_framebuffer(crtc->fb);
7494 work->old_fb_obj = intel_fb->obj;
7495 INIT_WORK(&work->work, intel_unpin_work_fn);
7496
7497 ret = drm_vblank_get(dev, intel_crtc->pipe);
7498 if (ret)
7499 goto free_work;
7500
7501 /* We borrow the event spin lock for protecting unpin_work */
7502 spin_lock_irqsave(&dev->event_lock, flags);
7503 if (intel_crtc->unpin_work) {
7504 spin_unlock_irqrestore(&dev->event_lock, flags);
7505 kfree(work);
7506 drm_vblank_put(dev, intel_crtc->pipe);
7507
7508 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7509 return -EBUSY;
7510 }
7511 intel_crtc->unpin_work = work;
7512 spin_unlock_irqrestore(&dev->event_lock, flags);
7513
7514 intel_fb = to_intel_framebuffer(fb);
7515 obj = intel_fb->obj;
7516
7517 mutex_lock(&dev->struct_mutex);
7518
7519 /* Reference the objects for the scheduled work. */
7520 drm_gem_object_reference(&work->old_fb_obj->base);
7521 drm_gem_object_reference(&obj->base);
7522
7523 crtc->fb = fb;
7524
7525 work->pending_flip_obj = obj;
7526
7527 work->enable_stall_check = true;
7528
7529 /* Block clients from rendering to the new back buffer until
7530 * the flip occurs and the object is no longer visible.
7531 */
7532 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7533
7534 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7535 if (ret)
7536 goto cleanup_pending;
7537
7538 intel_disable_fbc(dev);
7539 mutex_unlock(&dev->struct_mutex);
7540
7541 trace_i915_flip_request(intel_crtc->plane, obj);
7542
7543 return 0;
7544
7545 cleanup_pending:
7546 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7547 drm_gem_object_unreference(&work->old_fb_obj->base);
7548 drm_gem_object_unreference(&obj->base);
7549 mutex_unlock(&dev->struct_mutex);
7550
7551 spin_lock_irqsave(&dev->event_lock, flags);
7552 intel_crtc->unpin_work = NULL;
7553 spin_unlock_irqrestore(&dev->event_lock, flags);
7554
7555 drm_vblank_put(dev, intel_crtc->pipe);
7556 free_work:
7557 kfree(work);
7558
7559 return ret;
7560 }
7561
7562 static void intel_sanitize_modesetting(struct drm_device *dev,
7563 int pipe, int plane)
7564 {
7565 struct drm_i915_private *dev_priv = dev->dev_private;
7566 u32 reg, val;
7567
7568 if (HAS_PCH_SPLIT(dev))
7569 return;
7570
7571 /* Who knows what state these registers were left in by the BIOS or
7572 * grub?
7573 *
7574 * If we leave the registers in a conflicting state (e.g. with the
7575 * display plane reading from the other pipe than the one we intend
7576 * to use) then when we attempt to teardown the active mode, we will
7577 * not disable the pipes and planes in the correct order -- leaving
7578 * a plane reading from a disabled pipe and possibly leading to
7579 * undefined behaviour.
7580 */
7581
7582 reg = DSPCNTR(plane);
7583 val = I915_READ(reg);
7584
7585 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7586 return;
7587 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7588 return;
7589
7590 /* This display plane is active and attached to the other CPU pipe. */
7591 pipe = !pipe;
7592
7593 /* Disable the plane and wait for it to stop reading from the pipe. */
7594 intel_disable_plane(dev_priv, plane, pipe);
7595 intel_disable_pipe(dev_priv, pipe);
7596 }
7597
7598 static void intel_crtc_reset(struct drm_crtc *crtc)
7599 {
7600 struct drm_device *dev = crtc->dev;
7601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7602
7603 /* Reset flags back to the 'unknown' status so that they
7604 * will be correctly set on the initial modeset.
7605 */
7606 intel_crtc->dpms_mode = -1;
7607
7608 /* We need to fix up any BIOS configuration that conflicts with
7609 * our expectations.
7610 */
7611 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7612 }
7613
7614 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7615 .dpms = intel_crtc_dpms,
7616 .mode_fixup = intel_crtc_mode_fixup,
7617 .mode_set = intel_crtc_mode_set,
7618 .mode_set_base = intel_pipe_set_base,
7619 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7620 .load_lut = intel_crtc_load_lut,
7621 .disable = intel_crtc_disable,
7622 };
7623
7624 static const struct drm_crtc_funcs intel_crtc_funcs = {
7625 .reset = intel_crtc_reset,
7626 .cursor_set = intel_crtc_cursor_set,
7627 .cursor_move = intel_crtc_cursor_move,
7628 .gamma_set = intel_crtc_gamma_set,
7629 .set_config = drm_crtc_helper_set_config,
7630 .destroy = intel_crtc_destroy,
7631 .page_flip = intel_crtc_page_flip,
7632 };
7633
7634 static void intel_crtc_init(struct drm_device *dev, int pipe)
7635 {
7636 drm_i915_private_t *dev_priv = dev->dev_private;
7637 struct intel_crtc *intel_crtc;
7638 int i;
7639
7640 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7641 if (intel_crtc == NULL)
7642 return;
7643
7644 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7645
7646 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7647 for (i = 0; i < 256; i++) {
7648 intel_crtc->lut_r[i] = i;
7649 intel_crtc->lut_g[i] = i;
7650 intel_crtc->lut_b[i] = i;
7651 }
7652
7653 /* Swap pipes & planes for FBC on pre-965 */
7654 intel_crtc->pipe = pipe;
7655 intel_crtc->plane = pipe;
7656 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7657 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7658 intel_crtc->plane = !pipe;
7659 }
7660
7661 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7662 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7663 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7664 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7665
7666 intel_crtc_reset(&intel_crtc->base);
7667 intel_crtc->active = true; /* force the pipe off on setup_init_config */
7668 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7669
7670 if (HAS_PCH_SPLIT(dev)) {
7671 if (pipe == 2 && IS_IVYBRIDGE(dev))
7672 intel_crtc->no_pll = true;
7673 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7674 intel_helper_funcs.commit = ironlake_crtc_commit;
7675 } else {
7676 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7677 intel_helper_funcs.commit = i9xx_crtc_commit;
7678 }
7679
7680 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7681
7682 intel_crtc->busy = false;
7683
7684 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7685 (unsigned long)intel_crtc);
7686 }
7687
7688 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7689 struct drm_file *file)
7690 {
7691 drm_i915_private_t *dev_priv = dev->dev_private;
7692 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7693 struct drm_mode_object *drmmode_obj;
7694 struct intel_crtc *crtc;
7695
7696 if (!dev_priv) {
7697 DRM_ERROR("called with no initialization\n");
7698 return -EINVAL;
7699 }
7700
7701 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7702 DRM_MODE_OBJECT_CRTC);
7703
7704 if (!drmmode_obj) {
7705 DRM_ERROR("no such CRTC id\n");
7706 return -EINVAL;
7707 }
7708
7709 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7710 pipe_from_crtc_id->pipe = crtc->pipe;
7711
7712 return 0;
7713 }
7714
7715 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7716 {
7717 struct intel_encoder *encoder;
7718 int index_mask = 0;
7719 int entry = 0;
7720
7721 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7722 if (type_mask & encoder->clone_mask)
7723 index_mask |= (1 << entry);
7724 entry++;
7725 }
7726
7727 return index_mask;
7728 }
7729
7730 static bool has_edp_a(struct drm_device *dev)
7731 {
7732 struct drm_i915_private *dev_priv = dev->dev_private;
7733
7734 if (!IS_MOBILE(dev))
7735 return false;
7736
7737 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7738 return false;
7739
7740 if (IS_GEN5(dev) &&
7741 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7742 return false;
7743
7744 return true;
7745 }
7746
7747 static void intel_setup_outputs(struct drm_device *dev)
7748 {
7749 struct drm_i915_private *dev_priv = dev->dev_private;
7750 struct intel_encoder *encoder;
7751 bool dpd_is_edp = false;
7752 bool has_lvds = false;
7753
7754 if (IS_MOBILE(dev) && !IS_I830(dev))
7755 has_lvds = intel_lvds_init(dev);
7756 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7757 /* disable the panel fitter on everything but LVDS */
7758 I915_WRITE(PFIT_CONTROL, 0);
7759 }
7760
7761 if (HAS_PCH_SPLIT(dev)) {
7762 dpd_is_edp = intel_dpd_is_edp(dev);
7763
7764 if (has_edp_a(dev))
7765 intel_dp_init(dev, DP_A);
7766
7767 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7768 intel_dp_init(dev, PCH_DP_D);
7769 }
7770
7771 intel_crt_init(dev);
7772
7773 if (HAS_PCH_SPLIT(dev)) {
7774 int found;
7775
7776 if (I915_READ(HDMIB) & PORT_DETECTED) {
7777 /* PCH SDVOB multiplex with HDMIB */
7778 found = intel_sdvo_init(dev, PCH_SDVOB);
7779 if (!found)
7780 intel_hdmi_init(dev, HDMIB);
7781 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7782 intel_dp_init(dev, PCH_DP_B);
7783 }
7784
7785 if (I915_READ(HDMIC) & PORT_DETECTED)
7786 intel_hdmi_init(dev, HDMIC);
7787
7788 if (I915_READ(HDMID) & PORT_DETECTED)
7789 intel_hdmi_init(dev, HDMID);
7790
7791 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7792 intel_dp_init(dev, PCH_DP_C);
7793
7794 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7795 intel_dp_init(dev, PCH_DP_D);
7796
7797 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7798 bool found = false;
7799
7800 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7801 DRM_DEBUG_KMS("probing SDVOB\n");
7802 found = intel_sdvo_init(dev, SDVOB);
7803 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7804 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7805 intel_hdmi_init(dev, SDVOB);
7806 }
7807
7808 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7809 DRM_DEBUG_KMS("probing DP_B\n");
7810 intel_dp_init(dev, DP_B);
7811 }
7812 }
7813
7814 /* Before G4X SDVOC doesn't have its own detect register */
7815
7816 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7817 DRM_DEBUG_KMS("probing SDVOC\n");
7818 found = intel_sdvo_init(dev, SDVOC);
7819 }
7820
7821 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7822
7823 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7824 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7825 intel_hdmi_init(dev, SDVOC);
7826 }
7827 if (SUPPORTS_INTEGRATED_DP(dev)) {
7828 DRM_DEBUG_KMS("probing DP_C\n");
7829 intel_dp_init(dev, DP_C);
7830 }
7831 }
7832
7833 if (SUPPORTS_INTEGRATED_DP(dev) &&
7834 (I915_READ(DP_D) & DP_DETECTED)) {
7835 DRM_DEBUG_KMS("probing DP_D\n");
7836 intel_dp_init(dev, DP_D);
7837 }
7838 } else if (IS_GEN2(dev))
7839 intel_dvo_init(dev);
7840
7841 if (SUPPORTS_TV(dev))
7842 intel_tv_init(dev);
7843
7844 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7845 encoder->base.possible_crtcs = encoder->crtc_mask;
7846 encoder->base.possible_clones =
7847 intel_encoder_clones(dev, encoder->clone_mask);
7848 }
7849
7850 /* disable all the possible outputs/crtcs before entering KMS mode */
7851 drm_helper_disable_unused_functions(dev);
7852
7853 if (HAS_PCH_SPLIT(dev))
7854 ironlake_init_pch_refclk(dev);
7855 }
7856
7857 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7858 {
7859 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7860
7861 drm_framebuffer_cleanup(fb);
7862 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7863
7864 kfree(intel_fb);
7865 }
7866
7867 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7868 struct drm_file *file,
7869 unsigned int *handle)
7870 {
7871 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7872 struct drm_i915_gem_object *obj = intel_fb->obj;
7873
7874 return drm_gem_handle_create(file, &obj->base, handle);
7875 }
7876
7877 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7878 .destroy = intel_user_framebuffer_destroy,
7879 .create_handle = intel_user_framebuffer_create_handle,
7880 };
7881
7882 int intel_framebuffer_init(struct drm_device *dev,
7883 struct intel_framebuffer *intel_fb,
7884 struct drm_mode_fb_cmd2 *mode_cmd,
7885 struct drm_i915_gem_object *obj)
7886 {
7887 int ret;
7888
7889 if (obj->tiling_mode == I915_TILING_Y)
7890 return -EINVAL;
7891
7892 if (mode_cmd->pitches[0] & 63)
7893 return -EINVAL;
7894
7895 switch (mode_cmd->pixel_format) {
7896 case DRM_FORMAT_RGB332:
7897 case DRM_FORMAT_RGB565:
7898 case DRM_FORMAT_XRGB8888:
7899 case DRM_FORMAT_ARGB8888:
7900 case DRM_FORMAT_XRGB2101010:
7901 case DRM_FORMAT_ARGB2101010:
7902 /* RGB formats are common across chipsets */
7903 break;
7904 case DRM_FORMAT_YUYV:
7905 case DRM_FORMAT_UYVY:
7906 case DRM_FORMAT_YVYU:
7907 case DRM_FORMAT_VYUY:
7908 break;
7909 default:
7910 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7911 mode_cmd->pixel_format);
7912 return -EINVAL;
7913 }
7914
7915 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7916 if (ret) {
7917 DRM_ERROR("framebuffer init failed %d\n", ret);
7918 return ret;
7919 }
7920
7921 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7922 intel_fb->obj = obj;
7923 return 0;
7924 }
7925
7926 static struct drm_framebuffer *
7927 intel_user_framebuffer_create(struct drm_device *dev,
7928 struct drm_file *filp,
7929 struct drm_mode_fb_cmd2 *mode_cmd)
7930 {
7931 struct drm_i915_gem_object *obj;
7932
7933 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7934 mode_cmd->handles[0]));
7935 if (&obj->base == NULL)
7936 return ERR_PTR(-ENOENT);
7937
7938 return intel_framebuffer_create(dev, mode_cmd, obj);
7939 }
7940
7941 static const struct drm_mode_config_funcs intel_mode_funcs = {
7942 .fb_create = intel_user_framebuffer_create,
7943 .output_poll_changed = intel_fb_output_poll_changed,
7944 };
7945
7946 static struct drm_i915_gem_object *
7947 intel_alloc_context_page(struct drm_device *dev)
7948 {
7949 struct drm_i915_gem_object *ctx;
7950 int ret;
7951
7952 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7953
7954 ctx = i915_gem_alloc_object(dev, 4096);
7955 if (!ctx) {
7956 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7957 return NULL;
7958 }
7959
7960 ret = i915_gem_object_pin(ctx, 4096, true);
7961 if (ret) {
7962 DRM_ERROR("failed to pin power context: %d\n", ret);
7963 goto err_unref;
7964 }
7965
7966 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7967 if (ret) {
7968 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7969 goto err_unpin;
7970 }
7971
7972 return ctx;
7973
7974 err_unpin:
7975 i915_gem_object_unpin(ctx);
7976 err_unref:
7977 drm_gem_object_unreference(&ctx->base);
7978 mutex_unlock(&dev->struct_mutex);
7979 return NULL;
7980 }
7981
7982 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7983 {
7984 struct drm_i915_private *dev_priv = dev->dev_private;
7985 u16 rgvswctl;
7986
7987 rgvswctl = I915_READ16(MEMSWCTL);
7988 if (rgvswctl & MEMCTL_CMD_STS) {
7989 DRM_DEBUG("gpu busy, RCS change rejected\n");
7990 return false; /* still busy with another command */
7991 }
7992
7993 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7994 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7995 I915_WRITE16(MEMSWCTL, rgvswctl);
7996 POSTING_READ16(MEMSWCTL);
7997
7998 rgvswctl |= MEMCTL_CMD_STS;
7999 I915_WRITE16(MEMSWCTL, rgvswctl);
8000
8001 return true;
8002 }
8003
8004 void ironlake_enable_drps(struct drm_device *dev)
8005 {
8006 struct drm_i915_private *dev_priv = dev->dev_private;
8007 u32 rgvmodectl = I915_READ(MEMMODECTL);
8008 u8 fmax, fmin, fstart, vstart;
8009
8010 /* Enable temp reporting */
8011 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
8012 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
8013
8014 /* 100ms RC evaluation intervals */
8015 I915_WRITE(RCUPEI, 100000);
8016 I915_WRITE(RCDNEI, 100000);
8017
8018 /* Set max/min thresholds to 90ms and 80ms respectively */
8019 I915_WRITE(RCBMAXAVG, 90000);
8020 I915_WRITE(RCBMINAVG, 80000);
8021
8022 I915_WRITE(MEMIHYST, 1);
8023
8024 /* Set up min, max, and cur for interrupt handling */
8025 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
8026 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
8027 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
8028 MEMMODE_FSTART_SHIFT;
8029
8030 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
8031 PXVFREQ_PX_SHIFT;
8032
8033 dev_priv->fmax = fmax; /* IPS callback will increase this */
8034 dev_priv->fstart = fstart;
8035
8036 dev_priv->max_delay = fstart;
8037 dev_priv->min_delay = fmin;
8038 dev_priv->cur_delay = fstart;
8039
8040 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
8041 fmax, fmin, fstart);
8042
8043 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
8044
8045 /*
8046 * Interrupts will be enabled in ironlake_irq_postinstall
8047 */
8048
8049 I915_WRITE(VIDSTART, vstart);
8050 POSTING_READ(VIDSTART);
8051
8052 rgvmodectl |= MEMMODE_SWMODE_EN;
8053 I915_WRITE(MEMMODECTL, rgvmodectl);
8054
8055 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
8056 DRM_ERROR("stuck trying to change perf mode\n");
8057 msleep(1);
8058
8059 ironlake_set_drps(dev, fstart);
8060
8061 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
8062 I915_READ(0x112e0);
8063 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
8064 dev_priv->last_count2 = I915_READ(0x112f4);
8065 getrawmonotonic(&dev_priv->last_time2);
8066 }
8067
8068 void ironlake_disable_drps(struct drm_device *dev)
8069 {
8070 struct drm_i915_private *dev_priv = dev->dev_private;
8071 u16 rgvswctl = I915_READ16(MEMSWCTL);
8072
8073 /* Ack interrupts, disable EFC interrupt */
8074 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
8075 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
8076 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
8077 I915_WRITE(DEIIR, DE_PCU_EVENT);
8078 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8079
8080 /* Go back to the starting frequency */
8081 ironlake_set_drps(dev, dev_priv->fstart);
8082 msleep(1);
8083 rgvswctl |= MEMCTL_CMD_STS;
8084 I915_WRITE(MEMSWCTL, rgvswctl);
8085 msleep(1);
8086
8087 }
8088
8089 void gen6_set_rps(struct drm_device *dev, u8 val)
8090 {
8091 struct drm_i915_private *dev_priv = dev->dev_private;
8092 u32 swreq;
8093
8094 swreq = (val & 0x3ff) << 25;
8095 I915_WRITE(GEN6_RPNSWREQ, swreq);
8096 }
8097
8098 void gen6_disable_rps(struct drm_device *dev)
8099 {
8100 struct drm_i915_private *dev_priv = dev->dev_private;
8101
8102 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8103 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8104 I915_WRITE(GEN6_PMIER, 0);
8105 /* Complete PM interrupt masking here doesn't race with the rps work
8106 * item again unmasking PM interrupts because that is using a different
8107 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8108 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
8109
8110 spin_lock_irq(&dev_priv->rps_lock);
8111 dev_priv->pm_iir = 0;
8112 spin_unlock_irq(&dev_priv->rps_lock);
8113
8114 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8115 }
8116
8117 static unsigned long intel_pxfreq(u32 vidfreq)
8118 {
8119 unsigned long freq;
8120 int div = (vidfreq & 0x3f0000) >> 16;
8121 int post = (vidfreq & 0x3000) >> 12;
8122 int pre = (vidfreq & 0x7);
8123
8124 if (!pre)
8125 return 0;
8126
8127 freq = ((div * 133333) / ((1<<post) * pre));
8128
8129 return freq;
8130 }
8131
8132 void intel_init_emon(struct drm_device *dev)
8133 {
8134 struct drm_i915_private *dev_priv = dev->dev_private;
8135 u32 lcfuse;
8136 u8 pxw[16];
8137 int i;
8138
8139 /* Disable to program */
8140 I915_WRITE(ECR, 0);
8141 POSTING_READ(ECR);
8142
8143 /* Program energy weights for various events */
8144 I915_WRITE(SDEW, 0x15040d00);
8145 I915_WRITE(CSIEW0, 0x007f0000);
8146 I915_WRITE(CSIEW1, 0x1e220004);
8147 I915_WRITE(CSIEW2, 0x04000004);
8148
8149 for (i = 0; i < 5; i++)
8150 I915_WRITE(PEW + (i * 4), 0);
8151 for (i = 0; i < 3; i++)
8152 I915_WRITE(DEW + (i * 4), 0);
8153
8154 /* Program P-state weights to account for frequency power adjustment */
8155 for (i = 0; i < 16; i++) {
8156 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8157 unsigned long freq = intel_pxfreq(pxvidfreq);
8158 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8159 PXVFREQ_PX_SHIFT;
8160 unsigned long val;
8161
8162 val = vid * vid;
8163 val *= (freq / 1000);
8164 val *= 255;
8165 val /= (127*127*900);
8166 if (val > 0xff)
8167 DRM_ERROR("bad pxval: %ld\n", val);
8168 pxw[i] = val;
8169 }
8170 /* Render standby states get 0 weight */
8171 pxw[14] = 0;
8172 pxw[15] = 0;
8173
8174 for (i = 0; i < 4; i++) {
8175 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8176 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8177 I915_WRITE(PXW + (i * 4), val);
8178 }
8179
8180 /* Adjust magic regs to magic values (more experimental results) */
8181 I915_WRITE(OGW0, 0);
8182 I915_WRITE(OGW1, 0);
8183 I915_WRITE(EG0, 0x00007f00);
8184 I915_WRITE(EG1, 0x0000000e);
8185 I915_WRITE(EG2, 0x000e0000);
8186 I915_WRITE(EG3, 0x68000300);
8187 I915_WRITE(EG4, 0x42000000);
8188 I915_WRITE(EG5, 0x00140031);
8189 I915_WRITE(EG6, 0);
8190 I915_WRITE(EG7, 0);
8191
8192 for (i = 0; i < 8; i++)
8193 I915_WRITE(PXWL + (i * 4), 0);
8194
8195 /* Enable PMON + select events */
8196 I915_WRITE(ECR, 0x80000019);
8197
8198 lcfuse = I915_READ(LCFUSE02);
8199
8200 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8201 }
8202
8203 static bool intel_enable_rc6(struct drm_device *dev)
8204 {
8205 /*
8206 * Respect the kernel parameter if it is set
8207 */
8208 if (i915_enable_rc6 >= 0)
8209 return i915_enable_rc6;
8210
8211 /*
8212 * Disable RC6 on Ironlake
8213 */
8214 if (INTEL_INFO(dev)->gen == 5)
8215 return 0;
8216
8217 /*
8218 * Disable rc6 on Sandybridge
8219 */
8220 if (INTEL_INFO(dev)->gen == 6) {
8221 DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
8222 return 0;
8223 }
8224 DRM_DEBUG_DRIVER("RC6 enabled\n");
8225 return 1;
8226 }
8227
8228 void gen6_enable_rps(struct drm_i915_private *dev_priv)
8229 {
8230 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8231 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
8232 u32 pcu_mbox, rc6_mask = 0;
8233 int cur_freq, min_freq, max_freq;
8234 int i;
8235
8236 /* Here begins a magic sequence of register writes to enable
8237 * auto-downclocking.
8238 *
8239 * Perhaps there might be some value in exposing these to
8240 * userspace...
8241 */
8242 I915_WRITE(GEN6_RC_STATE, 0);
8243 mutex_lock(&dev_priv->dev->struct_mutex);
8244 gen6_gt_force_wake_get(dev_priv);
8245
8246 /* disable the counters and set deterministic thresholds */
8247 I915_WRITE(GEN6_RC_CONTROL, 0);
8248
8249 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8250 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8251 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8252 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8253 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8254
8255 for (i = 0; i < I915_NUM_RINGS; i++)
8256 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8257
8258 I915_WRITE(GEN6_RC_SLEEP, 0);
8259 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8260 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8261 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8262 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8263
8264 if (intel_enable_rc6(dev_priv->dev))
8265 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
8266 GEN6_RC_CTL_RC6_ENABLE;
8267
8268 I915_WRITE(GEN6_RC_CONTROL,
8269 rc6_mask |
8270 GEN6_RC_CTL_EI_MODE(1) |
8271 GEN6_RC_CTL_HW_ENABLE);
8272
8273 I915_WRITE(GEN6_RPNSWREQ,
8274 GEN6_FREQUENCY(10) |
8275 GEN6_OFFSET(0) |
8276 GEN6_AGGRESSIVE_TURBO);
8277 I915_WRITE(GEN6_RC_VIDEO_FREQ,
8278 GEN6_FREQUENCY(12));
8279
8280 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8281 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8282 18 << 24 |
8283 6 << 16);
8284 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8285 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8286 I915_WRITE(GEN6_RP_UP_EI, 100000);
8287 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8288 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8289 I915_WRITE(GEN6_RP_CONTROL,
8290 GEN6_RP_MEDIA_TURBO |
8291 GEN6_RP_MEDIA_HW_MODE |
8292 GEN6_RP_MEDIA_IS_GFX |
8293 GEN6_RP_ENABLE |
8294 GEN6_RP_UP_BUSY_AVG |
8295 GEN6_RP_DOWN_IDLE_CONT);
8296
8297 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8298 500))
8299 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8300
8301 I915_WRITE(GEN6_PCODE_DATA, 0);
8302 I915_WRITE(GEN6_PCODE_MAILBOX,
8303 GEN6_PCODE_READY |
8304 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8305 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8306 500))
8307 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8308
8309 min_freq = (rp_state_cap & 0xff0000) >> 16;
8310 max_freq = rp_state_cap & 0xff;
8311 cur_freq = (gt_perf_status & 0xff00) >> 8;
8312
8313 /* Check for overclock support */
8314 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8315 500))
8316 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8317 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8318 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8319 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8320 500))
8321 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8322 if (pcu_mbox & (1<<31)) { /* OC supported */
8323 max_freq = pcu_mbox & 0xff;
8324 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8325 }
8326
8327 /* In units of 100MHz */
8328 dev_priv->max_delay = max_freq;
8329 dev_priv->min_delay = min_freq;
8330 dev_priv->cur_delay = cur_freq;
8331
8332 /* requires MSI enabled */
8333 I915_WRITE(GEN6_PMIER,
8334 GEN6_PM_MBOX_EVENT |
8335 GEN6_PM_THERMAL_EVENT |
8336 GEN6_PM_RP_DOWN_TIMEOUT |
8337 GEN6_PM_RP_UP_THRESHOLD |
8338 GEN6_PM_RP_DOWN_THRESHOLD |
8339 GEN6_PM_RP_UP_EI_EXPIRED |
8340 GEN6_PM_RP_DOWN_EI_EXPIRED);
8341 spin_lock_irq(&dev_priv->rps_lock);
8342 WARN_ON(dev_priv->pm_iir != 0);
8343 I915_WRITE(GEN6_PMIMR, 0);
8344 spin_unlock_irq(&dev_priv->rps_lock);
8345 /* enable all PM interrupts */
8346 I915_WRITE(GEN6_PMINTRMSK, 0);
8347
8348 gen6_gt_force_wake_put(dev_priv);
8349 mutex_unlock(&dev_priv->dev->struct_mutex);
8350 }
8351
8352 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8353 {
8354 int min_freq = 15;
8355 int gpu_freq, ia_freq, max_ia_freq;
8356 int scaling_factor = 180;
8357
8358 max_ia_freq = cpufreq_quick_get_max(0);
8359 /*
8360 * Default to measured freq if none found, PCU will ensure we don't go
8361 * over
8362 */
8363 if (!max_ia_freq)
8364 max_ia_freq = tsc_khz;
8365
8366 /* Convert from kHz to MHz */
8367 max_ia_freq /= 1000;
8368
8369 mutex_lock(&dev_priv->dev->struct_mutex);
8370
8371 /*
8372 * For each potential GPU frequency, load a ring frequency we'd like
8373 * to use for memory access. We do this by specifying the IA frequency
8374 * the PCU should use as a reference to determine the ring frequency.
8375 */
8376 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8377 gpu_freq--) {
8378 int diff = dev_priv->max_delay - gpu_freq;
8379
8380 /*
8381 * For GPU frequencies less than 750MHz, just use the lowest
8382 * ring freq.
8383 */
8384 if (gpu_freq < min_freq)
8385 ia_freq = 800;
8386 else
8387 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8388 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8389
8390 I915_WRITE(GEN6_PCODE_DATA,
8391 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8392 gpu_freq);
8393 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8394 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8395 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8396 GEN6_PCODE_READY) == 0, 10)) {
8397 DRM_ERROR("pcode write of freq table timed out\n");
8398 continue;
8399 }
8400 }
8401
8402 mutex_unlock(&dev_priv->dev->struct_mutex);
8403 }
8404
8405 static void ironlake_init_clock_gating(struct drm_device *dev)
8406 {
8407 struct drm_i915_private *dev_priv = dev->dev_private;
8408 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8409
8410 /* Required for FBC */
8411 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8412 DPFCRUNIT_CLOCK_GATE_DISABLE |
8413 DPFDUNIT_CLOCK_GATE_DISABLE;
8414 /* Required for CxSR */
8415 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8416
8417 I915_WRITE(PCH_3DCGDIS0,
8418 MARIUNIT_CLOCK_GATE_DISABLE |
8419 SVSMUNIT_CLOCK_GATE_DISABLE);
8420 I915_WRITE(PCH_3DCGDIS1,
8421 VFMUNIT_CLOCK_GATE_DISABLE);
8422
8423 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8424
8425 /*
8426 * According to the spec the following bits should be set in
8427 * order to enable memory self-refresh
8428 * The bit 22/21 of 0x42004
8429 * The bit 5 of 0x42020
8430 * The bit 15 of 0x45000
8431 */
8432 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8433 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8434 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8435 I915_WRITE(ILK_DSPCLK_GATE,
8436 (I915_READ(ILK_DSPCLK_GATE) |
8437 ILK_DPARB_CLK_GATE));
8438 I915_WRITE(DISP_ARB_CTL,
8439 (I915_READ(DISP_ARB_CTL) |
8440 DISP_FBC_WM_DIS));
8441 I915_WRITE(WM3_LP_ILK, 0);
8442 I915_WRITE(WM2_LP_ILK, 0);
8443 I915_WRITE(WM1_LP_ILK, 0);
8444
8445 /*
8446 * Based on the document from hardware guys the following bits
8447 * should be set unconditionally in order to enable FBC.
8448 * The bit 22 of 0x42000
8449 * The bit 22 of 0x42004
8450 * The bit 7,8,9 of 0x42020.
8451 */
8452 if (IS_IRONLAKE_M(dev)) {
8453 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8454 I915_READ(ILK_DISPLAY_CHICKEN1) |
8455 ILK_FBCQ_DIS);
8456 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8457 I915_READ(ILK_DISPLAY_CHICKEN2) |
8458 ILK_DPARB_GATE);
8459 I915_WRITE(ILK_DSPCLK_GATE,
8460 I915_READ(ILK_DSPCLK_GATE) |
8461 ILK_DPFC_DIS1 |
8462 ILK_DPFC_DIS2 |
8463 ILK_CLK_FBC);
8464 }
8465
8466 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8467 I915_READ(ILK_DISPLAY_CHICKEN2) |
8468 ILK_ELPIN_409_SELECT);
8469 I915_WRITE(_3D_CHICKEN2,
8470 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8471 _3D_CHICKEN2_WM_READ_PIPELINED);
8472 }
8473
8474 static void gen6_init_clock_gating(struct drm_device *dev)
8475 {
8476 struct drm_i915_private *dev_priv = dev->dev_private;
8477 int pipe;
8478 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8479
8480 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8481
8482 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8483 I915_READ(ILK_DISPLAY_CHICKEN2) |
8484 ILK_ELPIN_409_SELECT);
8485
8486 I915_WRITE(WM3_LP_ILK, 0);
8487 I915_WRITE(WM2_LP_ILK, 0);
8488 I915_WRITE(WM1_LP_ILK, 0);
8489
8490 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8491 * gating disable must be set. Failure to set it results in
8492 * flickering pixels due to Z write ordering failures after
8493 * some amount of runtime in the Mesa "fire" demo, and Unigine
8494 * Sanctuary and Tropics, and apparently anything else with
8495 * alpha test or pixel discard.
8496 *
8497 * According to the spec, bit 11 (RCCUNIT) must also be set,
8498 * but we didn't debug actual testcases to find it out.
8499 */
8500 I915_WRITE(GEN6_UCGCTL2,
8501 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8502 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8503
8504 /*
8505 * According to the spec the following bits should be
8506 * set in order to enable memory self-refresh and fbc:
8507 * The bit21 and bit22 of 0x42000
8508 * The bit21 and bit22 of 0x42004
8509 * The bit5 and bit7 of 0x42020
8510 * The bit14 of 0x70180
8511 * The bit14 of 0x71180
8512 */
8513 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8514 I915_READ(ILK_DISPLAY_CHICKEN1) |
8515 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8516 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8517 I915_READ(ILK_DISPLAY_CHICKEN2) |
8518 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8519 I915_WRITE(ILK_DSPCLK_GATE,
8520 I915_READ(ILK_DSPCLK_GATE) |
8521 ILK_DPARB_CLK_GATE |
8522 ILK_DPFD_CLK_GATE);
8523
8524 for_each_pipe(pipe) {
8525 I915_WRITE(DSPCNTR(pipe),
8526 I915_READ(DSPCNTR(pipe)) |
8527 DISPPLANE_TRICKLE_FEED_DISABLE);
8528 intel_flush_display_plane(dev_priv, pipe);
8529 }
8530 }
8531
8532 static void ivybridge_init_clock_gating(struct drm_device *dev)
8533 {
8534 struct drm_i915_private *dev_priv = dev->dev_private;
8535 int pipe;
8536 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8537
8538 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8539
8540 I915_WRITE(WM3_LP_ILK, 0);
8541 I915_WRITE(WM2_LP_ILK, 0);
8542 I915_WRITE(WM1_LP_ILK, 0);
8543
8544 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8545
8546 I915_WRITE(IVB_CHICKEN3,
8547 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8548 CHICKEN3_DGMG_DONE_FIX_DISABLE);
8549
8550 for_each_pipe(pipe) {
8551 I915_WRITE(DSPCNTR(pipe),
8552 I915_READ(DSPCNTR(pipe)) |
8553 DISPPLANE_TRICKLE_FEED_DISABLE);
8554 intel_flush_display_plane(dev_priv, pipe);
8555 }
8556 }
8557
8558 static void g4x_init_clock_gating(struct drm_device *dev)
8559 {
8560 struct drm_i915_private *dev_priv = dev->dev_private;
8561 uint32_t dspclk_gate;
8562
8563 I915_WRITE(RENCLK_GATE_D1, 0);
8564 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8565 GS_UNIT_CLOCK_GATE_DISABLE |
8566 CL_UNIT_CLOCK_GATE_DISABLE);
8567 I915_WRITE(RAMCLK_GATE_D, 0);
8568 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8569 OVRUNIT_CLOCK_GATE_DISABLE |
8570 OVCUNIT_CLOCK_GATE_DISABLE;
8571 if (IS_GM45(dev))
8572 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8573 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8574 }
8575
8576 static void crestline_init_clock_gating(struct drm_device *dev)
8577 {
8578 struct drm_i915_private *dev_priv = dev->dev_private;
8579
8580 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8581 I915_WRITE(RENCLK_GATE_D2, 0);
8582 I915_WRITE(DSPCLK_GATE_D, 0);
8583 I915_WRITE(RAMCLK_GATE_D, 0);
8584 I915_WRITE16(DEUC, 0);
8585 }
8586
8587 static void broadwater_init_clock_gating(struct drm_device *dev)
8588 {
8589 struct drm_i915_private *dev_priv = dev->dev_private;
8590
8591 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8592 I965_RCC_CLOCK_GATE_DISABLE |
8593 I965_RCPB_CLOCK_GATE_DISABLE |
8594 I965_ISC_CLOCK_GATE_DISABLE |
8595 I965_FBC_CLOCK_GATE_DISABLE);
8596 I915_WRITE(RENCLK_GATE_D2, 0);
8597 }
8598
8599 static void gen3_init_clock_gating(struct drm_device *dev)
8600 {
8601 struct drm_i915_private *dev_priv = dev->dev_private;
8602 u32 dstate = I915_READ(D_STATE);
8603
8604 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8605 DSTATE_DOT_CLOCK_GATING;
8606 I915_WRITE(D_STATE, dstate);
8607 }
8608
8609 static void i85x_init_clock_gating(struct drm_device *dev)
8610 {
8611 struct drm_i915_private *dev_priv = dev->dev_private;
8612
8613 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8614 }
8615
8616 static void i830_init_clock_gating(struct drm_device *dev)
8617 {
8618 struct drm_i915_private *dev_priv = dev->dev_private;
8619
8620 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8621 }
8622
8623 static void ibx_init_clock_gating(struct drm_device *dev)
8624 {
8625 struct drm_i915_private *dev_priv = dev->dev_private;
8626
8627 /*
8628 * On Ibex Peak and Cougar Point, we need to disable clock
8629 * gating for the panel power sequencer or it will fail to
8630 * start up when no ports are active.
8631 */
8632 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8633 }
8634
8635 static void cpt_init_clock_gating(struct drm_device *dev)
8636 {
8637 struct drm_i915_private *dev_priv = dev->dev_private;
8638 int pipe;
8639
8640 /*
8641 * On Ibex Peak and Cougar Point, we need to disable clock
8642 * gating for the panel power sequencer or it will fail to
8643 * start up when no ports are active.
8644 */
8645 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8646 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8647 DPLS_EDP_PPS_FIX_DIS);
8648 /* Without this, mode sets may fail silently on FDI */
8649 for_each_pipe(pipe)
8650 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8651 }
8652
8653 static void ironlake_teardown_rc6(struct drm_device *dev)
8654 {
8655 struct drm_i915_private *dev_priv = dev->dev_private;
8656
8657 if (dev_priv->renderctx) {
8658 i915_gem_object_unpin(dev_priv->renderctx);
8659 drm_gem_object_unreference(&dev_priv->renderctx->base);
8660 dev_priv->renderctx = NULL;
8661 }
8662
8663 if (dev_priv->pwrctx) {
8664 i915_gem_object_unpin(dev_priv->pwrctx);
8665 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8666 dev_priv->pwrctx = NULL;
8667 }
8668 }
8669
8670 static void ironlake_disable_rc6(struct drm_device *dev)
8671 {
8672 struct drm_i915_private *dev_priv = dev->dev_private;
8673
8674 if (I915_READ(PWRCTXA)) {
8675 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8676 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8677 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8678 50);
8679
8680 I915_WRITE(PWRCTXA, 0);
8681 POSTING_READ(PWRCTXA);
8682
8683 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8684 POSTING_READ(RSTDBYCTL);
8685 }
8686
8687 ironlake_teardown_rc6(dev);
8688 }
8689
8690 static int ironlake_setup_rc6(struct drm_device *dev)
8691 {
8692 struct drm_i915_private *dev_priv = dev->dev_private;
8693
8694 if (dev_priv->renderctx == NULL)
8695 dev_priv->renderctx = intel_alloc_context_page(dev);
8696 if (!dev_priv->renderctx)
8697 return -ENOMEM;
8698
8699 if (dev_priv->pwrctx == NULL)
8700 dev_priv->pwrctx = intel_alloc_context_page(dev);
8701 if (!dev_priv->pwrctx) {
8702 ironlake_teardown_rc6(dev);
8703 return -ENOMEM;
8704 }
8705
8706 return 0;
8707 }
8708
8709 void ironlake_enable_rc6(struct drm_device *dev)
8710 {
8711 struct drm_i915_private *dev_priv = dev->dev_private;
8712 int ret;
8713
8714 /* rc6 disabled by default due to repeated reports of hanging during
8715 * boot and resume.
8716 */
8717 if (!intel_enable_rc6(dev))
8718 return;
8719
8720 mutex_lock(&dev->struct_mutex);
8721 ret = ironlake_setup_rc6(dev);
8722 if (ret) {
8723 mutex_unlock(&dev->struct_mutex);
8724 return;
8725 }
8726
8727 /*
8728 * GPU can automatically power down the render unit if given a page
8729 * to save state.
8730 */
8731 ret = BEGIN_LP_RING(6);
8732 if (ret) {
8733 ironlake_teardown_rc6(dev);
8734 mutex_unlock(&dev->struct_mutex);
8735 return;
8736 }
8737
8738 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8739 OUT_RING(MI_SET_CONTEXT);
8740 OUT_RING(dev_priv->renderctx->gtt_offset |
8741 MI_MM_SPACE_GTT |
8742 MI_SAVE_EXT_STATE_EN |
8743 MI_RESTORE_EXT_STATE_EN |
8744 MI_RESTORE_INHIBIT);
8745 OUT_RING(MI_SUSPEND_FLUSH);
8746 OUT_RING(MI_NOOP);
8747 OUT_RING(MI_FLUSH);
8748 ADVANCE_LP_RING();
8749
8750 /*
8751 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8752 * does an implicit flush, combined with MI_FLUSH above, it should be
8753 * safe to assume that renderctx is valid
8754 */
8755 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8756 if (ret) {
8757 DRM_ERROR("failed to enable ironlake power power savings\n");
8758 ironlake_teardown_rc6(dev);
8759 mutex_unlock(&dev->struct_mutex);
8760 return;
8761 }
8762
8763 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8764 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8765 mutex_unlock(&dev->struct_mutex);
8766 }
8767
8768 void intel_init_clock_gating(struct drm_device *dev)
8769 {
8770 struct drm_i915_private *dev_priv = dev->dev_private;
8771
8772 dev_priv->display.init_clock_gating(dev);
8773
8774 if (dev_priv->display.init_pch_clock_gating)
8775 dev_priv->display.init_pch_clock_gating(dev);
8776 }
8777
8778 /* Set up chip specific display functions */
8779 static void intel_init_display(struct drm_device *dev)
8780 {
8781 struct drm_i915_private *dev_priv = dev->dev_private;
8782
8783 /* We always want a DPMS function */
8784 if (HAS_PCH_SPLIT(dev)) {
8785 dev_priv->display.dpms = ironlake_crtc_dpms;
8786 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8787 dev_priv->display.update_plane = ironlake_update_plane;
8788 } else {
8789 dev_priv->display.dpms = i9xx_crtc_dpms;
8790 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8791 dev_priv->display.update_plane = i9xx_update_plane;
8792 }
8793
8794 if (I915_HAS_FBC(dev)) {
8795 if (HAS_PCH_SPLIT(dev)) {
8796 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8797 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8798 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8799 } else if (IS_GM45(dev)) {
8800 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8801 dev_priv->display.enable_fbc = g4x_enable_fbc;
8802 dev_priv->display.disable_fbc = g4x_disable_fbc;
8803 } else if (IS_CRESTLINE(dev)) {
8804 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8805 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8806 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8807 }
8808 /* 855GM needs testing */
8809 }
8810
8811 /* Returns the core display clock speed */
8812 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8813 dev_priv->display.get_display_clock_speed =
8814 i945_get_display_clock_speed;
8815 else if (IS_I915G(dev))
8816 dev_priv->display.get_display_clock_speed =
8817 i915_get_display_clock_speed;
8818 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8819 dev_priv->display.get_display_clock_speed =
8820 i9xx_misc_get_display_clock_speed;
8821 else if (IS_I915GM(dev))
8822 dev_priv->display.get_display_clock_speed =
8823 i915gm_get_display_clock_speed;
8824 else if (IS_I865G(dev))
8825 dev_priv->display.get_display_clock_speed =
8826 i865_get_display_clock_speed;
8827 else if (IS_I85X(dev))
8828 dev_priv->display.get_display_clock_speed =
8829 i855_get_display_clock_speed;
8830 else /* 852, 830 */
8831 dev_priv->display.get_display_clock_speed =
8832 i830_get_display_clock_speed;
8833
8834 /* For FIFO watermark updates */
8835 if (HAS_PCH_SPLIT(dev)) {
8836 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8837 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8838
8839 /* IVB configs may use multi-threaded forcewake */
8840 if (IS_IVYBRIDGE(dev)) {
8841 u32 ecobus;
8842
8843 /* A small trick here - if the bios hasn't configured MT forcewake,
8844 * and if the device is in RC6, then force_wake_mt_get will not wake
8845 * the device and the ECOBUS read will return zero. Which will be
8846 * (correctly) interpreted by the test below as MT forcewake being
8847 * disabled.
8848 */
8849 mutex_lock(&dev->struct_mutex);
8850 __gen6_gt_force_wake_mt_get(dev_priv);
8851 ecobus = I915_READ_NOTRACE(ECOBUS);
8852 __gen6_gt_force_wake_mt_put(dev_priv);
8853 mutex_unlock(&dev->struct_mutex);
8854
8855 if (ecobus & FORCEWAKE_MT_ENABLE) {
8856 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8857 dev_priv->display.force_wake_get =
8858 __gen6_gt_force_wake_mt_get;
8859 dev_priv->display.force_wake_put =
8860 __gen6_gt_force_wake_mt_put;
8861 }
8862 }
8863
8864 if (HAS_PCH_IBX(dev))
8865 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8866 else if (HAS_PCH_CPT(dev))
8867 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8868
8869 if (IS_GEN5(dev)) {
8870 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8871 dev_priv->display.update_wm = ironlake_update_wm;
8872 else {
8873 DRM_DEBUG_KMS("Failed to get proper latency. "
8874 "Disable CxSR\n");
8875 dev_priv->display.update_wm = NULL;
8876 }
8877 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8878 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8879 dev_priv->display.write_eld = ironlake_write_eld;
8880 } else if (IS_GEN6(dev)) {
8881 if (SNB_READ_WM0_LATENCY()) {
8882 dev_priv->display.update_wm = sandybridge_update_wm;
8883 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
8884 } else {
8885 DRM_DEBUG_KMS("Failed to read display plane latency. "
8886 "Disable CxSR\n");
8887 dev_priv->display.update_wm = NULL;
8888 }
8889 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8890 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8891 dev_priv->display.write_eld = ironlake_write_eld;
8892 } else if (IS_IVYBRIDGE(dev)) {
8893 /* FIXME: detect B0+ stepping and use auto training */
8894 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8895 if (SNB_READ_WM0_LATENCY()) {
8896 dev_priv->display.update_wm = sandybridge_update_wm;
8897 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
8898 } else {
8899 DRM_DEBUG_KMS("Failed to read display plane latency. "
8900 "Disable CxSR\n");
8901 dev_priv->display.update_wm = NULL;
8902 }
8903 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8904 dev_priv->display.write_eld = ironlake_write_eld;
8905 } else
8906 dev_priv->display.update_wm = NULL;
8907 } else if (IS_PINEVIEW(dev)) {
8908 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8909 dev_priv->is_ddr3,
8910 dev_priv->fsb_freq,
8911 dev_priv->mem_freq)) {
8912 DRM_INFO("failed to find known CxSR latency "
8913 "(found ddr%s fsb freq %d, mem freq %d), "
8914 "disabling CxSR\n",
8915 (dev_priv->is_ddr3 == 1) ? "3" : "2",
8916 dev_priv->fsb_freq, dev_priv->mem_freq);
8917 /* Disable CxSR and never update its watermark again */
8918 pineview_disable_cxsr(dev);
8919 dev_priv->display.update_wm = NULL;
8920 } else
8921 dev_priv->display.update_wm = pineview_update_wm;
8922 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8923 } else if (IS_G4X(dev)) {
8924 dev_priv->display.write_eld = g4x_write_eld;
8925 dev_priv->display.update_wm = g4x_update_wm;
8926 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8927 } else if (IS_GEN4(dev)) {
8928 dev_priv->display.update_wm = i965_update_wm;
8929 if (IS_CRESTLINE(dev))
8930 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8931 else if (IS_BROADWATER(dev))
8932 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8933 } else if (IS_GEN3(dev)) {
8934 dev_priv->display.update_wm = i9xx_update_wm;
8935 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8936 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8937 } else if (IS_I865G(dev)) {
8938 dev_priv->display.update_wm = i830_update_wm;
8939 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8940 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8941 } else if (IS_I85X(dev)) {
8942 dev_priv->display.update_wm = i9xx_update_wm;
8943 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8944 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8945 } else {
8946 dev_priv->display.update_wm = i830_update_wm;
8947 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8948 if (IS_845G(dev))
8949 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8950 else
8951 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8952 }
8953
8954 /* Default just returns -ENODEV to indicate unsupported */
8955 dev_priv->display.queue_flip = intel_default_queue_flip;
8956
8957 switch (INTEL_INFO(dev)->gen) {
8958 case 2:
8959 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8960 break;
8961
8962 case 3:
8963 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8964 break;
8965
8966 case 4:
8967 case 5:
8968 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8969 break;
8970
8971 case 6:
8972 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8973 break;
8974 case 7:
8975 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8976 break;
8977 }
8978 }
8979
8980 /*
8981 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8982 * resume, or other times. This quirk makes sure that's the case for
8983 * affected systems.
8984 */
8985 static void quirk_pipea_force(struct drm_device *dev)
8986 {
8987 struct drm_i915_private *dev_priv = dev->dev_private;
8988
8989 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8990 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8991 }
8992
8993 /*
8994 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8995 */
8996 static void quirk_ssc_force_disable(struct drm_device *dev)
8997 {
8998 struct drm_i915_private *dev_priv = dev->dev_private;
8999 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9000 }
9001
9002 struct intel_quirk {
9003 int device;
9004 int subsystem_vendor;
9005 int subsystem_device;
9006 void (*hook)(struct drm_device *dev);
9007 };
9008
9009 struct intel_quirk intel_quirks[] = {
9010 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
9011 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
9012 /* HP Mini needs pipe A force quirk (LP: #322104) */
9013 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9014
9015 /* Thinkpad R31 needs pipe A force quirk */
9016 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
9017 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9018 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9019
9020 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
9021 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
9022 /* ThinkPad X40 needs pipe A force quirk */
9023
9024 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9025 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9026
9027 /* 855 & before need to leave pipe A & dpll A up */
9028 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9029 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9030
9031 /* Lenovo U160 cannot use SSC on LVDS */
9032 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9033
9034 /* Sony Vaio Y cannot use SSC on LVDS */
9035 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9036 };
9037
9038 static void intel_init_quirks(struct drm_device *dev)
9039 {
9040 struct pci_dev *d = dev->pdev;
9041 int i;
9042
9043 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9044 struct intel_quirk *q = &intel_quirks[i];
9045
9046 if (d->device == q->device &&
9047 (d->subsystem_vendor == q->subsystem_vendor ||
9048 q->subsystem_vendor == PCI_ANY_ID) &&
9049 (d->subsystem_device == q->subsystem_device ||
9050 q->subsystem_device == PCI_ANY_ID))
9051 q->hook(dev);
9052 }
9053 }
9054
9055 /* Disable the VGA plane that we never use */
9056 static void i915_disable_vga(struct drm_device *dev)
9057 {
9058 struct drm_i915_private *dev_priv = dev->dev_private;
9059 u8 sr1;
9060 u32 vga_reg;
9061
9062 if (HAS_PCH_SPLIT(dev))
9063 vga_reg = CPU_VGACNTRL;
9064 else
9065 vga_reg = VGACNTRL;
9066
9067 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9068 outb(1, VGA_SR_INDEX);
9069 sr1 = inb(VGA_SR_DATA);
9070 outb(sr1 | 1<<5, VGA_SR_DATA);
9071 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9072 udelay(300);
9073
9074 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9075 POSTING_READ(vga_reg);
9076 }
9077
9078 void intel_modeset_init(struct drm_device *dev)
9079 {
9080 struct drm_i915_private *dev_priv = dev->dev_private;
9081 int i, ret;
9082
9083 drm_mode_config_init(dev);
9084
9085 dev->mode_config.min_width = 0;
9086 dev->mode_config.min_height = 0;
9087
9088 dev->mode_config.funcs = (void *)&intel_mode_funcs;
9089
9090 intel_init_quirks(dev);
9091
9092 intel_init_display(dev);
9093
9094 if (IS_GEN2(dev)) {
9095 dev->mode_config.max_width = 2048;
9096 dev->mode_config.max_height = 2048;
9097 } else if (IS_GEN3(dev)) {
9098 dev->mode_config.max_width = 4096;
9099 dev->mode_config.max_height = 4096;
9100 } else {
9101 dev->mode_config.max_width = 8192;
9102 dev->mode_config.max_height = 8192;
9103 }
9104 dev->mode_config.fb_base = dev->agp->base;
9105
9106 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9107 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
9108
9109 for (i = 0; i < dev_priv->num_pipe; i++) {
9110 intel_crtc_init(dev, i);
9111 ret = intel_plane_init(dev, i);
9112 if (ret)
9113 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
9114 }
9115
9116 /* Just disable it once at startup */
9117 i915_disable_vga(dev);
9118 intel_setup_outputs(dev);
9119
9120 intel_init_clock_gating(dev);
9121
9122 if (IS_IRONLAKE_M(dev)) {
9123 ironlake_enable_drps(dev);
9124 intel_init_emon(dev);
9125 }
9126
9127 if (IS_GEN6(dev) || IS_GEN7(dev)) {
9128 gen6_enable_rps(dev_priv);
9129 gen6_update_ring_freq(dev_priv);
9130 }
9131
9132 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9133 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9134 (unsigned long)dev);
9135 }
9136
9137 void intel_modeset_gem_init(struct drm_device *dev)
9138 {
9139 if (IS_IRONLAKE_M(dev))
9140 ironlake_enable_rc6(dev);
9141
9142 intel_setup_overlay(dev);
9143 }
9144
9145 void intel_modeset_cleanup(struct drm_device *dev)
9146 {
9147 struct drm_i915_private *dev_priv = dev->dev_private;
9148 struct drm_crtc *crtc;
9149 struct intel_crtc *intel_crtc;
9150
9151 drm_kms_helper_poll_fini(dev);
9152 mutex_lock(&dev->struct_mutex);
9153
9154 intel_unregister_dsm_handler();
9155
9156
9157 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9158 /* Skip inactive CRTCs */
9159 if (!crtc->fb)
9160 continue;
9161
9162 intel_crtc = to_intel_crtc(crtc);
9163 intel_increase_pllclock(crtc);
9164 }
9165
9166 intel_disable_fbc(dev);
9167
9168 if (IS_IRONLAKE_M(dev))
9169 ironlake_disable_drps(dev);
9170 if (IS_GEN6(dev) || IS_GEN7(dev))
9171 gen6_disable_rps(dev);
9172
9173 if (IS_IRONLAKE_M(dev))
9174 ironlake_disable_rc6(dev);
9175
9176 mutex_unlock(&dev->struct_mutex);
9177
9178 /* Disable the irq before mode object teardown, for the irq might
9179 * enqueue unpin/hotplug work. */
9180 drm_irq_uninstall(dev);
9181 cancel_work_sync(&dev_priv->hotplug_work);
9182 cancel_work_sync(&dev_priv->rps_work);
9183
9184 /* flush any delayed tasks or pending work */
9185 flush_scheduled_work();
9186
9187 /* Shut off idle work before the crtcs get freed. */
9188 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9189 intel_crtc = to_intel_crtc(crtc);
9190 del_timer_sync(&intel_crtc->idle_timer);
9191 }
9192 del_timer_sync(&dev_priv->idle_timer);
9193 cancel_work_sync(&dev_priv->idle_work);
9194
9195 drm_mode_config_cleanup(dev);
9196 }
9197
9198 /*
9199 * Return which encoder is currently attached for connector.
9200 */
9201 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9202 {
9203 return &intel_attached_encoder(connector)->base;
9204 }
9205
9206 void intel_connector_attach_encoder(struct intel_connector *connector,
9207 struct intel_encoder *encoder)
9208 {
9209 connector->encoder = encoder;
9210 drm_mode_connector_attach_encoder(&connector->base,
9211 &encoder->base);
9212 }
9213
9214 /*
9215 * set vga decode state - true == enable VGA decode
9216 */
9217 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9218 {
9219 struct drm_i915_private *dev_priv = dev->dev_private;
9220 u16 gmch_ctrl;
9221
9222 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9223 if (state)
9224 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9225 else
9226 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9227 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9228 return 0;
9229 }
9230
9231 #ifdef CONFIG_DEBUG_FS
9232 #include <linux/seq_file.h>
9233
9234 struct intel_display_error_state {
9235 struct intel_cursor_error_state {
9236 u32 control;
9237 u32 position;
9238 u32 base;
9239 u32 size;
9240 } cursor[2];
9241
9242 struct intel_pipe_error_state {
9243 u32 conf;
9244 u32 source;
9245
9246 u32 htotal;
9247 u32 hblank;
9248 u32 hsync;
9249 u32 vtotal;
9250 u32 vblank;
9251 u32 vsync;
9252 } pipe[2];
9253
9254 struct intel_plane_error_state {
9255 u32 control;
9256 u32 stride;
9257 u32 size;
9258 u32 pos;
9259 u32 addr;
9260 u32 surface;
9261 u32 tile_offset;
9262 } plane[2];
9263 };
9264
9265 struct intel_display_error_state *
9266 intel_display_capture_error_state(struct drm_device *dev)
9267 {
9268 drm_i915_private_t *dev_priv = dev->dev_private;
9269 struct intel_display_error_state *error;
9270 int i;
9271
9272 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9273 if (error == NULL)
9274 return NULL;
9275
9276 for (i = 0; i < 2; i++) {
9277 error->cursor[i].control = I915_READ(CURCNTR(i));
9278 error->cursor[i].position = I915_READ(CURPOS(i));
9279 error->cursor[i].base = I915_READ(CURBASE(i));
9280
9281 error->plane[i].control = I915_READ(DSPCNTR(i));
9282 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9283 error->plane[i].size = I915_READ(DSPSIZE(i));
9284 error->plane[i].pos = I915_READ(DSPPOS(i));
9285 error->plane[i].addr = I915_READ(DSPADDR(i));
9286 if (INTEL_INFO(dev)->gen >= 4) {
9287 error->plane[i].surface = I915_READ(DSPSURF(i));
9288 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9289 }
9290
9291 error->pipe[i].conf = I915_READ(PIPECONF(i));
9292 error->pipe[i].source = I915_READ(PIPESRC(i));
9293 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9294 error->pipe[i].hblank = I915_READ(HBLANK(i));
9295 error->pipe[i].hsync = I915_READ(HSYNC(i));
9296 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9297 error->pipe[i].vblank = I915_READ(VBLANK(i));
9298 error->pipe[i].vsync = I915_READ(VSYNC(i));
9299 }
9300
9301 return error;
9302 }
9303
9304 void
9305 intel_display_print_error_state(struct seq_file *m,
9306 struct drm_device *dev,
9307 struct intel_display_error_state *error)
9308 {
9309 int i;
9310
9311 for (i = 0; i < 2; i++) {
9312 seq_printf(m, "Pipe [%d]:\n", i);
9313 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9314 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9315 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9316 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9317 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9318 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9319 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9320 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9321
9322 seq_printf(m, "Plane [%d]:\n", i);
9323 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9324 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9325 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9326 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9327 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9328 if (INTEL_INFO(dev)->gen >= 4) {
9329 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9330 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9331 }
9332
9333 seq_printf(m, "Cursor [%d]:\n", i);
9334 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9335 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9336 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9337 }
9338 }
9339 #endif
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