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Merge tag 'drm-intel-next-2014-02-14' of ssh://git.freedesktop.org/git/drm-intel...
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 static void intel_increase_pllclock(struct drm_crtc *crtc);
45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
46
47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
51
52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
54 static int intel_framebuffer_init(struct drm_device *dev,
55 struct intel_framebuffer *ifb,
56 struct drm_mode_fb_cmd2 *mode_cmd,
57 struct drm_i915_gem_object *obj);
58
59 typedef struct {
60 int min, max;
61 } intel_range_t;
62
63 typedef struct {
64 int dot_limit;
65 int p2_slow, p2_fast;
66 } intel_p2_t;
67
68 typedef struct intel_limit intel_limit_t;
69 struct intel_limit {
70 intel_range_t dot, vco, n, m, m1, m2, p, p1;
71 intel_p2_t p2;
72 };
73
74 int
75 intel_pch_rawclk(struct drm_device *dev)
76 {
77 struct drm_i915_private *dev_priv = dev->dev_private;
78
79 WARN_ON(!HAS_PCH_SPLIT(dev));
80
81 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
82 }
83
84 static inline u32 /* units of 100MHz */
85 intel_fdi_link_freq(struct drm_device *dev)
86 {
87 if (IS_GEN5(dev)) {
88 struct drm_i915_private *dev_priv = dev->dev_private;
89 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
90 } else
91 return 27;
92 }
93
94 static const intel_limit_t intel_limits_i8xx_dac = {
95 .dot = { .min = 25000, .max = 350000 },
96 .vco = { .min = 908000, .max = 1512000 },
97 .n = { .min = 2, .max = 16 },
98 .m = { .min = 96, .max = 140 },
99 .m1 = { .min = 18, .max = 26 },
100 .m2 = { .min = 6, .max = 16 },
101 .p = { .min = 4, .max = 128 },
102 .p1 = { .min = 2, .max = 33 },
103 .p2 = { .dot_limit = 165000,
104 .p2_slow = 4, .p2_fast = 2 },
105 };
106
107 static const intel_limit_t intel_limits_i8xx_dvo = {
108 .dot = { .min = 25000, .max = 350000 },
109 .vco = { .min = 908000, .max = 1512000 },
110 .n = { .min = 2, .max = 16 },
111 .m = { .min = 96, .max = 140 },
112 .m1 = { .min = 18, .max = 26 },
113 .m2 = { .min = 6, .max = 16 },
114 .p = { .min = 4, .max = 128 },
115 .p1 = { .min = 2, .max = 33 },
116 .p2 = { .dot_limit = 165000,
117 .p2_slow = 4, .p2_fast = 4 },
118 };
119
120 static const intel_limit_t intel_limits_i8xx_lvds = {
121 .dot = { .min = 25000, .max = 350000 },
122 .vco = { .min = 908000, .max = 1512000 },
123 .n = { .min = 2, .max = 16 },
124 .m = { .min = 96, .max = 140 },
125 .m1 = { .min = 18, .max = 26 },
126 .m2 = { .min = 6, .max = 16 },
127 .p = { .min = 4, .max = 128 },
128 .p1 = { .min = 1, .max = 6 },
129 .p2 = { .dot_limit = 165000,
130 .p2_slow = 14, .p2_fast = 7 },
131 };
132
133 static const intel_limit_t intel_limits_i9xx_sdvo = {
134 .dot = { .min = 20000, .max = 400000 },
135 .vco = { .min = 1400000, .max = 2800000 },
136 .n = { .min = 1, .max = 6 },
137 .m = { .min = 70, .max = 120 },
138 .m1 = { .min = 8, .max = 18 },
139 .m2 = { .min = 3, .max = 7 },
140 .p = { .min = 5, .max = 80 },
141 .p1 = { .min = 1, .max = 8 },
142 .p2 = { .dot_limit = 200000,
143 .p2_slow = 10, .p2_fast = 5 },
144 };
145
146 static const intel_limit_t intel_limits_i9xx_lvds = {
147 .dot = { .min = 20000, .max = 400000 },
148 .vco = { .min = 1400000, .max = 2800000 },
149 .n = { .min = 1, .max = 6 },
150 .m = { .min = 70, .max = 120 },
151 .m1 = { .min = 8, .max = 18 },
152 .m2 = { .min = 3, .max = 7 },
153 .p = { .min = 7, .max = 98 },
154 .p1 = { .min = 1, .max = 8 },
155 .p2 = { .dot_limit = 112000,
156 .p2_slow = 14, .p2_fast = 7 },
157 };
158
159
160 static const intel_limit_t intel_limits_g4x_sdvo = {
161 .dot = { .min = 25000, .max = 270000 },
162 .vco = { .min = 1750000, .max = 3500000},
163 .n = { .min = 1, .max = 4 },
164 .m = { .min = 104, .max = 138 },
165 .m1 = { .min = 17, .max = 23 },
166 .m2 = { .min = 5, .max = 11 },
167 .p = { .min = 10, .max = 30 },
168 .p1 = { .min = 1, .max = 3},
169 .p2 = { .dot_limit = 270000,
170 .p2_slow = 10,
171 .p2_fast = 10
172 },
173 };
174
175 static const intel_limit_t intel_limits_g4x_hdmi = {
176 .dot = { .min = 22000, .max = 400000 },
177 .vco = { .min = 1750000, .max = 3500000},
178 .n = { .min = 1, .max = 4 },
179 .m = { .min = 104, .max = 138 },
180 .m1 = { .min = 16, .max = 23 },
181 .m2 = { .min = 5, .max = 11 },
182 .p = { .min = 5, .max = 80 },
183 .p1 = { .min = 1, .max = 8},
184 .p2 = { .dot_limit = 165000,
185 .p2_slow = 10, .p2_fast = 5 },
186 };
187
188 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
189 .dot = { .min = 20000, .max = 115000 },
190 .vco = { .min = 1750000, .max = 3500000 },
191 .n = { .min = 1, .max = 3 },
192 .m = { .min = 104, .max = 138 },
193 .m1 = { .min = 17, .max = 23 },
194 .m2 = { .min = 5, .max = 11 },
195 .p = { .min = 28, .max = 112 },
196 .p1 = { .min = 2, .max = 8 },
197 .p2 = { .dot_limit = 0,
198 .p2_slow = 14, .p2_fast = 14
199 },
200 };
201
202 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
203 .dot = { .min = 80000, .max = 224000 },
204 .vco = { .min = 1750000, .max = 3500000 },
205 .n = { .min = 1, .max = 3 },
206 .m = { .min = 104, .max = 138 },
207 .m1 = { .min = 17, .max = 23 },
208 .m2 = { .min = 5, .max = 11 },
209 .p = { .min = 14, .max = 42 },
210 .p1 = { .min = 2, .max = 6 },
211 .p2 = { .dot_limit = 0,
212 .p2_slow = 7, .p2_fast = 7
213 },
214 };
215
216 static const intel_limit_t intel_limits_pineview_sdvo = {
217 .dot = { .min = 20000, .max = 400000},
218 .vco = { .min = 1700000, .max = 3500000 },
219 /* Pineview's Ncounter is a ring counter */
220 .n = { .min = 3, .max = 6 },
221 .m = { .min = 2, .max = 256 },
222 /* Pineview only has one combined m divider, which we treat as m2. */
223 .m1 = { .min = 0, .max = 0 },
224 .m2 = { .min = 0, .max = 254 },
225 .p = { .min = 5, .max = 80 },
226 .p1 = { .min = 1, .max = 8 },
227 .p2 = { .dot_limit = 200000,
228 .p2_slow = 10, .p2_fast = 5 },
229 };
230
231 static const intel_limit_t intel_limits_pineview_lvds = {
232 .dot = { .min = 20000, .max = 400000 },
233 .vco = { .min = 1700000, .max = 3500000 },
234 .n = { .min = 3, .max = 6 },
235 .m = { .min = 2, .max = 256 },
236 .m1 = { .min = 0, .max = 0 },
237 .m2 = { .min = 0, .max = 254 },
238 .p = { .min = 7, .max = 112 },
239 .p1 = { .min = 1, .max = 8 },
240 .p2 = { .dot_limit = 112000,
241 .p2_slow = 14, .p2_fast = 14 },
242 };
243
244 /* Ironlake / Sandybridge
245 *
246 * We calculate clock using (register_value + 2) for N/M1/M2, so here
247 * the range value for them is (actual_value - 2).
248 */
249 static const intel_limit_t intel_limits_ironlake_dac = {
250 .dot = { .min = 25000, .max = 350000 },
251 .vco = { .min = 1760000, .max = 3510000 },
252 .n = { .min = 1, .max = 5 },
253 .m = { .min = 79, .max = 127 },
254 .m1 = { .min = 12, .max = 22 },
255 .m2 = { .min = 5, .max = 9 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
258 .p2 = { .dot_limit = 225000,
259 .p2_slow = 10, .p2_fast = 5 },
260 };
261
262 static const intel_limit_t intel_limits_ironlake_single_lvds = {
263 .dot = { .min = 25000, .max = 350000 },
264 .vco = { .min = 1760000, .max = 3510000 },
265 .n = { .min = 1, .max = 3 },
266 .m = { .min = 79, .max = 118 },
267 .m1 = { .min = 12, .max = 22 },
268 .m2 = { .min = 5, .max = 9 },
269 .p = { .min = 28, .max = 112 },
270 .p1 = { .min = 2, .max = 8 },
271 .p2 = { .dot_limit = 225000,
272 .p2_slow = 14, .p2_fast = 14 },
273 };
274
275 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
276 .dot = { .min = 25000, .max = 350000 },
277 .vco = { .min = 1760000, .max = 3510000 },
278 .n = { .min = 1, .max = 3 },
279 .m = { .min = 79, .max = 127 },
280 .m1 = { .min = 12, .max = 22 },
281 .m2 = { .min = 5, .max = 9 },
282 .p = { .min = 14, .max = 56 },
283 .p1 = { .min = 2, .max = 8 },
284 .p2 = { .dot_limit = 225000,
285 .p2_slow = 7, .p2_fast = 7 },
286 };
287
288 /* LVDS 100mhz refclk limits. */
289 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
290 .dot = { .min = 25000, .max = 350000 },
291 .vco = { .min = 1760000, .max = 3510000 },
292 .n = { .min = 1, .max = 2 },
293 .m = { .min = 79, .max = 126 },
294 .m1 = { .min = 12, .max = 22 },
295 .m2 = { .min = 5, .max = 9 },
296 .p = { .min = 28, .max = 112 },
297 .p1 = { .min = 2, .max = 8 },
298 .p2 = { .dot_limit = 225000,
299 .p2_slow = 14, .p2_fast = 14 },
300 };
301
302 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
303 .dot = { .min = 25000, .max = 350000 },
304 .vco = { .min = 1760000, .max = 3510000 },
305 .n = { .min = 1, .max = 3 },
306 .m = { .min = 79, .max = 126 },
307 .m1 = { .min = 12, .max = 22 },
308 .m2 = { .min = 5, .max = 9 },
309 .p = { .min = 14, .max = 42 },
310 .p1 = { .min = 2, .max = 6 },
311 .p2 = { .dot_limit = 225000,
312 .p2_slow = 7, .p2_fast = 7 },
313 };
314
315 static const intel_limit_t intel_limits_vlv = {
316 /*
317 * These are the data rate limits (measured in fast clocks)
318 * since those are the strictest limits we have. The fast
319 * clock and actual rate limits are more relaxed, so checking
320 * them would make no difference.
321 */
322 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
323 .vco = { .min = 4000000, .max = 6000000 },
324 .n = { .min = 1, .max = 7 },
325 .m1 = { .min = 2, .max = 3 },
326 .m2 = { .min = 11, .max = 156 },
327 .p1 = { .min = 2, .max = 3 },
328 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
329 };
330
331 static void vlv_clock(int refclk, intel_clock_t *clock)
332 {
333 clock->m = clock->m1 * clock->m2;
334 clock->p = clock->p1 * clock->p2;
335 if (WARN_ON(clock->n == 0 || clock->p == 0))
336 return;
337 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
338 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
339 }
340
341 /**
342 * Returns whether any output on the specified pipe is of the specified type
343 */
344 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
345 {
346 struct drm_device *dev = crtc->dev;
347 struct intel_encoder *encoder;
348
349 for_each_encoder_on_crtc(dev, crtc, encoder)
350 if (encoder->type == type)
351 return true;
352
353 return false;
354 }
355
356 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
357 int refclk)
358 {
359 struct drm_device *dev = crtc->dev;
360 const intel_limit_t *limit;
361
362 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
363 if (intel_is_dual_link_lvds(dev)) {
364 if (refclk == 100000)
365 limit = &intel_limits_ironlake_dual_lvds_100m;
366 else
367 limit = &intel_limits_ironlake_dual_lvds;
368 } else {
369 if (refclk == 100000)
370 limit = &intel_limits_ironlake_single_lvds_100m;
371 else
372 limit = &intel_limits_ironlake_single_lvds;
373 }
374 } else
375 limit = &intel_limits_ironlake_dac;
376
377 return limit;
378 }
379
380 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
381 {
382 struct drm_device *dev = crtc->dev;
383 const intel_limit_t *limit;
384
385 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
386 if (intel_is_dual_link_lvds(dev))
387 limit = &intel_limits_g4x_dual_channel_lvds;
388 else
389 limit = &intel_limits_g4x_single_channel_lvds;
390 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
391 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
392 limit = &intel_limits_g4x_hdmi;
393 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
394 limit = &intel_limits_g4x_sdvo;
395 } else /* The option is for other outputs */
396 limit = &intel_limits_i9xx_sdvo;
397
398 return limit;
399 }
400
401 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
402 {
403 struct drm_device *dev = crtc->dev;
404 const intel_limit_t *limit;
405
406 if (HAS_PCH_SPLIT(dev))
407 limit = intel_ironlake_limit(crtc, refclk);
408 else if (IS_G4X(dev)) {
409 limit = intel_g4x_limit(crtc);
410 } else if (IS_PINEVIEW(dev)) {
411 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
412 limit = &intel_limits_pineview_lvds;
413 else
414 limit = &intel_limits_pineview_sdvo;
415 } else if (IS_VALLEYVIEW(dev)) {
416 limit = &intel_limits_vlv;
417 } else if (!IS_GEN2(dev)) {
418 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
419 limit = &intel_limits_i9xx_lvds;
420 else
421 limit = &intel_limits_i9xx_sdvo;
422 } else {
423 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
424 limit = &intel_limits_i8xx_lvds;
425 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
426 limit = &intel_limits_i8xx_dvo;
427 else
428 limit = &intel_limits_i8xx_dac;
429 }
430 return limit;
431 }
432
433 /* m1 is reserved as 0 in Pineview, n is a ring counter */
434 static void pineview_clock(int refclk, intel_clock_t *clock)
435 {
436 clock->m = clock->m2 + 2;
437 clock->p = clock->p1 * clock->p2;
438 if (WARN_ON(clock->n == 0 || clock->p == 0))
439 return;
440 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
441 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
442 }
443
444 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
445 {
446 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
447 }
448
449 static void i9xx_clock(int refclk, intel_clock_t *clock)
450 {
451 clock->m = i9xx_dpll_compute_m(clock);
452 clock->p = clock->p1 * clock->p2;
453 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
454 return;
455 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
456 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
457 }
458
459 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
460 /**
461 * Returns whether the given set of divisors are valid for a given refclk with
462 * the given connectors.
463 */
464
465 static bool intel_PLL_is_valid(struct drm_device *dev,
466 const intel_limit_t *limit,
467 const intel_clock_t *clock)
468 {
469 if (clock->n < limit->n.min || limit->n.max < clock->n)
470 INTELPllInvalid("n out of range\n");
471 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
472 INTELPllInvalid("p1 out of range\n");
473 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
474 INTELPllInvalid("m2 out of range\n");
475 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
476 INTELPllInvalid("m1 out of range\n");
477
478 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
479 if (clock->m1 <= clock->m2)
480 INTELPllInvalid("m1 <= m2\n");
481
482 if (!IS_VALLEYVIEW(dev)) {
483 if (clock->p < limit->p.min || limit->p.max < clock->p)
484 INTELPllInvalid("p out of range\n");
485 if (clock->m < limit->m.min || limit->m.max < clock->m)
486 INTELPllInvalid("m out of range\n");
487 }
488
489 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
490 INTELPllInvalid("vco out of range\n");
491 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
492 * connector, etc., rather than just a single range.
493 */
494 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
495 INTELPllInvalid("dot out of range\n");
496
497 return true;
498 }
499
500 static bool
501 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
502 int target, int refclk, intel_clock_t *match_clock,
503 intel_clock_t *best_clock)
504 {
505 struct drm_device *dev = crtc->dev;
506 intel_clock_t clock;
507 int err = target;
508
509 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
510 /*
511 * For LVDS just rely on its current settings for dual-channel.
512 * We haven't figured out how to reliably set up different
513 * single/dual channel state, if we even can.
514 */
515 if (intel_is_dual_link_lvds(dev))
516 clock.p2 = limit->p2.p2_fast;
517 else
518 clock.p2 = limit->p2.p2_slow;
519 } else {
520 if (target < limit->p2.dot_limit)
521 clock.p2 = limit->p2.p2_slow;
522 else
523 clock.p2 = limit->p2.p2_fast;
524 }
525
526 memset(best_clock, 0, sizeof(*best_clock));
527
528 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
529 clock.m1++) {
530 for (clock.m2 = limit->m2.min;
531 clock.m2 <= limit->m2.max; clock.m2++) {
532 if (clock.m2 >= clock.m1)
533 break;
534 for (clock.n = limit->n.min;
535 clock.n <= limit->n.max; clock.n++) {
536 for (clock.p1 = limit->p1.min;
537 clock.p1 <= limit->p1.max; clock.p1++) {
538 int this_err;
539
540 i9xx_clock(refclk, &clock);
541 if (!intel_PLL_is_valid(dev, limit,
542 &clock))
543 continue;
544 if (match_clock &&
545 clock.p != match_clock->p)
546 continue;
547
548 this_err = abs(clock.dot - target);
549 if (this_err < err) {
550 *best_clock = clock;
551 err = this_err;
552 }
553 }
554 }
555 }
556 }
557
558 return (err != target);
559 }
560
561 static bool
562 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
563 int target, int refclk, intel_clock_t *match_clock,
564 intel_clock_t *best_clock)
565 {
566 struct drm_device *dev = crtc->dev;
567 intel_clock_t clock;
568 int err = target;
569
570 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
571 /*
572 * For LVDS just rely on its current settings for dual-channel.
573 * We haven't figured out how to reliably set up different
574 * single/dual channel state, if we even can.
575 */
576 if (intel_is_dual_link_lvds(dev))
577 clock.p2 = limit->p2.p2_fast;
578 else
579 clock.p2 = limit->p2.p2_slow;
580 } else {
581 if (target < limit->p2.dot_limit)
582 clock.p2 = limit->p2.p2_slow;
583 else
584 clock.p2 = limit->p2.p2_fast;
585 }
586
587 memset(best_clock, 0, sizeof(*best_clock));
588
589 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
590 clock.m1++) {
591 for (clock.m2 = limit->m2.min;
592 clock.m2 <= limit->m2.max; clock.m2++) {
593 for (clock.n = limit->n.min;
594 clock.n <= limit->n.max; clock.n++) {
595 for (clock.p1 = limit->p1.min;
596 clock.p1 <= limit->p1.max; clock.p1++) {
597 int this_err;
598
599 pineview_clock(refclk, &clock);
600 if (!intel_PLL_is_valid(dev, limit,
601 &clock))
602 continue;
603 if (match_clock &&
604 clock.p != match_clock->p)
605 continue;
606
607 this_err = abs(clock.dot - target);
608 if (this_err < err) {
609 *best_clock = clock;
610 err = this_err;
611 }
612 }
613 }
614 }
615 }
616
617 return (err != target);
618 }
619
620 static bool
621 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
622 int target, int refclk, intel_clock_t *match_clock,
623 intel_clock_t *best_clock)
624 {
625 struct drm_device *dev = crtc->dev;
626 intel_clock_t clock;
627 int max_n;
628 bool found;
629 /* approximately equals target * 0.00585 */
630 int err_most = (target >> 8) + (target >> 9);
631 found = false;
632
633 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
634 if (intel_is_dual_link_lvds(dev))
635 clock.p2 = limit->p2.p2_fast;
636 else
637 clock.p2 = limit->p2.p2_slow;
638 } else {
639 if (target < limit->p2.dot_limit)
640 clock.p2 = limit->p2.p2_slow;
641 else
642 clock.p2 = limit->p2.p2_fast;
643 }
644
645 memset(best_clock, 0, sizeof(*best_clock));
646 max_n = limit->n.max;
647 /* based on hardware requirement, prefer smaller n to precision */
648 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
649 /* based on hardware requirement, prefere larger m1,m2 */
650 for (clock.m1 = limit->m1.max;
651 clock.m1 >= limit->m1.min; clock.m1--) {
652 for (clock.m2 = limit->m2.max;
653 clock.m2 >= limit->m2.min; clock.m2--) {
654 for (clock.p1 = limit->p1.max;
655 clock.p1 >= limit->p1.min; clock.p1--) {
656 int this_err;
657
658 i9xx_clock(refclk, &clock);
659 if (!intel_PLL_is_valid(dev, limit,
660 &clock))
661 continue;
662
663 this_err = abs(clock.dot - target);
664 if (this_err < err_most) {
665 *best_clock = clock;
666 err_most = this_err;
667 max_n = clock.n;
668 found = true;
669 }
670 }
671 }
672 }
673 }
674 return found;
675 }
676
677 static bool
678 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
679 int target, int refclk, intel_clock_t *match_clock,
680 intel_clock_t *best_clock)
681 {
682 struct drm_device *dev = crtc->dev;
683 intel_clock_t clock;
684 unsigned int bestppm = 1000000;
685 /* min update 19.2 MHz */
686 int max_n = min(limit->n.max, refclk / 19200);
687 bool found = false;
688
689 target *= 5; /* fast clock */
690
691 memset(best_clock, 0, sizeof(*best_clock));
692
693 /* based on hardware requirement, prefer smaller n to precision */
694 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
695 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
696 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
697 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
698 clock.p = clock.p1 * clock.p2;
699 /* based on hardware requirement, prefer bigger m1,m2 values */
700 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
701 unsigned int ppm, diff;
702
703 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
704 refclk * clock.m1);
705
706 vlv_clock(refclk, &clock);
707
708 if (!intel_PLL_is_valid(dev, limit,
709 &clock))
710 continue;
711
712 diff = abs(clock.dot - target);
713 ppm = div_u64(1000000ULL * diff, target);
714
715 if (ppm < 100 && clock.p > best_clock->p) {
716 bestppm = 0;
717 *best_clock = clock;
718 found = true;
719 }
720
721 if (bestppm >= 10 && ppm < bestppm - 10) {
722 bestppm = ppm;
723 *best_clock = clock;
724 found = true;
725 }
726 }
727 }
728 }
729 }
730
731 return found;
732 }
733
734 bool intel_crtc_active(struct drm_crtc *crtc)
735 {
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
737
738 /* Be paranoid as we can arrive here with only partial
739 * state retrieved from the hardware during setup.
740 *
741 * We can ditch the adjusted_mode.crtc_clock check as soon
742 * as Haswell has gained clock readout/fastboot support.
743 *
744 * We can ditch the crtc->fb check as soon as we can
745 * properly reconstruct framebuffers.
746 */
747 return intel_crtc->active && crtc->fb &&
748 intel_crtc->config.adjusted_mode.crtc_clock;
749 }
750
751 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
752 enum pipe pipe)
753 {
754 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756
757 return intel_crtc->config.cpu_transcoder;
758 }
759
760 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
761 {
762 struct drm_i915_private *dev_priv = dev->dev_private;
763 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
764
765 frame = I915_READ(frame_reg);
766
767 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
768 DRM_DEBUG_KMS("vblank wait timed out\n");
769 }
770
771 /**
772 * intel_wait_for_vblank - wait for vblank on a given pipe
773 * @dev: drm device
774 * @pipe: pipe to wait for
775 *
776 * Wait for vblank to occur on a given pipe. Needed for various bits of
777 * mode setting code.
778 */
779 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
780 {
781 struct drm_i915_private *dev_priv = dev->dev_private;
782 int pipestat_reg = PIPESTAT(pipe);
783
784 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
785 g4x_wait_for_vblank(dev, pipe);
786 return;
787 }
788
789 /* Clear existing vblank status. Note this will clear any other
790 * sticky status fields as well.
791 *
792 * This races with i915_driver_irq_handler() with the result
793 * that either function could miss a vblank event. Here it is not
794 * fatal, as we will either wait upon the next vblank interrupt or
795 * timeout. Generally speaking intel_wait_for_vblank() is only
796 * called during modeset at which time the GPU should be idle and
797 * should *not* be performing page flips and thus not waiting on
798 * vblanks...
799 * Currently, the result of us stealing a vblank from the irq
800 * handler is that a single frame will be skipped during swapbuffers.
801 */
802 I915_WRITE(pipestat_reg,
803 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
804
805 /* Wait for vblank interrupt bit to set */
806 if (wait_for(I915_READ(pipestat_reg) &
807 PIPE_VBLANK_INTERRUPT_STATUS,
808 50))
809 DRM_DEBUG_KMS("vblank wait timed out\n");
810 }
811
812 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
813 {
814 struct drm_i915_private *dev_priv = dev->dev_private;
815 u32 reg = PIPEDSL(pipe);
816 u32 line1, line2;
817 u32 line_mask;
818
819 if (IS_GEN2(dev))
820 line_mask = DSL_LINEMASK_GEN2;
821 else
822 line_mask = DSL_LINEMASK_GEN3;
823
824 line1 = I915_READ(reg) & line_mask;
825 mdelay(5);
826 line2 = I915_READ(reg) & line_mask;
827
828 return line1 == line2;
829 }
830
831 /*
832 * intel_wait_for_pipe_off - wait for pipe to turn off
833 * @dev: drm device
834 * @pipe: pipe to wait for
835 *
836 * After disabling a pipe, we can't wait for vblank in the usual way,
837 * spinning on the vblank interrupt status bit, since we won't actually
838 * see an interrupt when the pipe is disabled.
839 *
840 * On Gen4 and above:
841 * wait for the pipe register state bit to turn off
842 *
843 * Otherwise:
844 * wait for the display line value to settle (it usually
845 * ends up stopping at the start of the next frame).
846 *
847 */
848 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
849 {
850 struct drm_i915_private *dev_priv = dev->dev_private;
851 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
852 pipe);
853
854 if (INTEL_INFO(dev)->gen >= 4) {
855 int reg = PIPECONF(cpu_transcoder);
856
857 /* Wait for the Pipe State to go off */
858 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
859 100))
860 WARN(1, "pipe_off wait timed out\n");
861 } else {
862 /* Wait for the display line to settle */
863 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
864 WARN(1, "pipe_off wait timed out\n");
865 }
866 }
867
868 /*
869 * ibx_digital_port_connected - is the specified port connected?
870 * @dev_priv: i915 private structure
871 * @port: the port to test
872 *
873 * Returns true if @port is connected, false otherwise.
874 */
875 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
876 struct intel_digital_port *port)
877 {
878 u32 bit;
879
880 if (HAS_PCH_IBX(dev_priv->dev)) {
881 switch(port->port) {
882 case PORT_B:
883 bit = SDE_PORTB_HOTPLUG;
884 break;
885 case PORT_C:
886 bit = SDE_PORTC_HOTPLUG;
887 break;
888 case PORT_D:
889 bit = SDE_PORTD_HOTPLUG;
890 break;
891 default:
892 return true;
893 }
894 } else {
895 switch(port->port) {
896 case PORT_B:
897 bit = SDE_PORTB_HOTPLUG_CPT;
898 break;
899 case PORT_C:
900 bit = SDE_PORTC_HOTPLUG_CPT;
901 break;
902 case PORT_D:
903 bit = SDE_PORTD_HOTPLUG_CPT;
904 break;
905 default:
906 return true;
907 }
908 }
909
910 return I915_READ(SDEISR) & bit;
911 }
912
913 static const char *state_string(bool enabled)
914 {
915 return enabled ? "on" : "off";
916 }
917
918 /* Only for pre-ILK configs */
919 void assert_pll(struct drm_i915_private *dev_priv,
920 enum pipe pipe, bool state)
921 {
922 int reg;
923 u32 val;
924 bool cur_state;
925
926 reg = DPLL(pipe);
927 val = I915_READ(reg);
928 cur_state = !!(val & DPLL_VCO_ENABLE);
929 WARN(cur_state != state,
930 "PLL state assertion failure (expected %s, current %s)\n",
931 state_string(state), state_string(cur_state));
932 }
933
934 /* XXX: the dsi pll is shared between MIPI DSI ports */
935 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
936 {
937 u32 val;
938 bool cur_state;
939
940 mutex_lock(&dev_priv->dpio_lock);
941 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
942 mutex_unlock(&dev_priv->dpio_lock);
943
944 cur_state = val & DSI_PLL_VCO_EN;
945 WARN(cur_state != state,
946 "DSI PLL state assertion failure (expected %s, current %s)\n",
947 state_string(state), state_string(cur_state));
948 }
949 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
950 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
951
952 struct intel_shared_dpll *
953 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
954 {
955 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
956
957 if (crtc->config.shared_dpll < 0)
958 return NULL;
959
960 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
961 }
962
963 /* For ILK+ */
964 void assert_shared_dpll(struct drm_i915_private *dev_priv,
965 struct intel_shared_dpll *pll,
966 bool state)
967 {
968 bool cur_state;
969 struct intel_dpll_hw_state hw_state;
970
971 if (HAS_PCH_LPT(dev_priv->dev)) {
972 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
973 return;
974 }
975
976 if (WARN (!pll,
977 "asserting DPLL %s with no DPLL\n", state_string(state)))
978 return;
979
980 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
981 WARN(cur_state != state,
982 "%s assertion failure (expected %s, current %s)\n",
983 pll->name, state_string(state), state_string(cur_state));
984 }
985
986 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
987 enum pipe pipe, bool state)
988 {
989 int reg;
990 u32 val;
991 bool cur_state;
992 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
993 pipe);
994
995 if (HAS_DDI(dev_priv->dev)) {
996 /* DDI does not have a specific FDI_TX register */
997 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
998 val = I915_READ(reg);
999 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1000 } else {
1001 reg = FDI_TX_CTL(pipe);
1002 val = I915_READ(reg);
1003 cur_state = !!(val & FDI_TX_ENABLE);
1004 }
1005 WARN(cur_state != state,
1006 "FDI TX state assertion failure (expected %s, current %s)\n",
1007 state_string(state), state_string(cur_state));
1008 }
1009 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1010 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1011
1012 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1013 enum pipe pipe, bool state)
1014 {
1015 int reg;
1016 u32 val;
1017 bool cur_state;
1018
1019 reg = FDI_RX_CTL(pipe);
1020 val = I915_READ(reg);
1021 cur_state = !!(val & FDI_RX_ENABLE);
1022 WARN(cur_state != state,
1023 "FDI RX state assertion failure (expected %s, current %s)\n",
1024 state_string(state), state_string(cur_state));
1025 }
1026 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1027 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1028
1029 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1030 enum pipe pipe)
1031 {
1032 int reg;
1033 u32 val;
1034
1035 /* ILK FDI PLL is always enabled */
1036 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1037 return;
1038
1039 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1040 if (HAS_DDI(dev_priv->dev))
1041 return;
1042
1043 reg = FDI_TX_CTL(pipe);
1044 val = I915_READ(reg);
1045 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1046 }
1047
1048 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1049 enum pipe pipe, bool state)
1050 {
1051 int reg;
1052 u32 val;
1053 bool cur_state;
1054
1055 reg = FDI_RX_CTL(pipe);
1056 val = I915_READ(reg);
1057 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1058 WARN(cur_state != state,
1059 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1060 state_string(state), state_string(cur_state));
1061 }
1062
1063 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1064 enum pipe pipe)
1065 {
1066 int pp_reg, lvds_reg;
1067 u32 val;
1068 enum pipe panel_pipe = PIPE_A;
1069 bool locked = true;
1070
1071 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1072 pp_reg = PCH_PP_CONTROL;
1073 lvds_reg = PCH_LVDS;
1074 } else {
1075 pp_reg = PP_CONTROL;
1076 lvds_reg = LVDS;
1077 }
1078
1079 val = I915_READ(pp_reg);
1080 if (!(val & PANEL_POWER_ON) ||
1081 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1082 locked = false;
1083
1084 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1085 panel_pipe = PIPE_B;
1086
1087 WARN(panel_pipe == pipe && locked,
1088 "panel assertion failure, pipe %c regs locked\n",
1089 pipe_name(pipe));
1090 }
1091
1092 static void assert_cursor(struct drm_i915_private *dev_priv,
1093 enum pipe pipe, bool state)
1094 {
1095 struct drm_device *dev = dev_priv->dev;
1096 bool cur_state;
1097
1098 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1099 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1100 else if (IS_845G(dev) || IS_I865G(dev))
1101 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1102 else
1103 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1104
1105 WARN(cur_state != state,
1106 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1107 pipe_name(pipe), state_string(state), state_string(cur_state));
1108 }
1109 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1110 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1111
1112 void assert_pipe(struct drm_i915_private *dev_priv,
1113 enum pipe pipe, bool state)
1114 {
1115 int reg;
1116 u32 val;
1117 bool cur_state;
1118 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1119 pipe);
1120
1121 /* if we need the pipe A quirk it must be always on */
1122 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1123 state = true;
1124
1125 if (!intel_display_power_enabled(dev_priv->dev,
1126 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1127 cur_state = false;
1128 } else {
1129 reg = PIPECONF(cpu_transcoder);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & PIPECONF_ENABLE);
1132 }
1133
1134 WARN(cur_state != state,
1135 "pipe %c assertion failure (expected %s, current %s)\n",
1136 pipe_name(pipe), state_string(state), state_string(cur_state));
1137 }
1138
1139 static void assert_plane(struct drm_i915_private *dev_priv,
1140 enum plane plane, bool state)
1141 {
1142 int reg;
1143 u32 val;
1144 bool cur_state;
1145
1146 reg = DSPCNTR(plane);
1147 val = I915_READ(reg);
1148 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1149 WARN(cur_state != state,
1150 "plane %c assertion failure (expected %s, current %s)\n",
1151 plane_name(plane), state_string(state), state_string(cur_state));
1152 }
1153
1154 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1155 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1156
1157 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1158 enum pipe pipe)
1159 {
1160 struct drm_device *dev = dev_priv->dev;
1161 int reg, i;
1162 u32 val;
1163 int cur_pipe;
1164
1165 /* Primary planes are fixed to pipes on gen4+ */
1166 if (INTEL_INFO(dev)->gen >= 4) {
1167 reg = DSPCNTR(pipe);
1168 val = I915_READ(reg);
1169 WARN((val & DISPLAY_PLANE_ENABLE),
1170 "plane %c assertion failure, should be disabled but not\n",
1171 plane_name(pipe));
1172 return;
1173 }
1174
1175 /* Need to check both planes against the pipe */
1176 for_each_pipe(i) {
1177 reg = DSPCNTR(i);
1178 val = I915_READ(reg);
1179 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1180 DISPPLANE_SEL_PIPE_SHIFT;
1181 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1182 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1183 plane_name(i), pipe_name(pipe));
1184 }
1185 }
1186
1187 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1188 enum pipe pipe)
1189 {
1190 struct drm_device *dev = dev_priv->dev;
1191 int reg, i;
1192 u32 val;
1193
1194 if (IS_VALLEYVIEW(dev)) {
1195 for (i = 0; i < INTEL_INFO(dev)->num_sprites; i++) {
1196 reg = SPCNTR(pipe, i);
1197 val = I915_READ(reg);
1198 WARN((val & SP_ENABLE),
1199 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1200 sprite_name(pipe, i), pipe_name(pipe));
1201 }
1202 } else if (INTEL_INFO(dev)->gen >= 7) {
1203 reg = SPRCTL(pipe);
1204 val = I915_READ(reg);
1205 WARN((val & SPRITE_ENABLE),
1206 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1207 plane_name(pipe), pipe_name(pipe));
1208 } else if (INTEL_INFO(dev)->gen >= 5) {
1209 reg = DVSCNTR(pipe);
1210 val = I915_READ(reg);
1211 WARN((val & DVS_ENABLE),
1212 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1213 plane_name(pipe), pipe_name(pipe));
1214 }
1215 }
1216
1217 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1218 {
1219 u32 val;
1220 bool enabled;
1221
1222 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1223
1224 val = I915_READ(PCH_DREF_CONTROL);
1225 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226 DREF_SUPERSPREAD_SOURCE_MASK));
1227 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228 }
1229
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231 enum pipe pipe)
1232 {
1233 int reg;
1234 u32 val;
1235 bool enabled;
1236
1237 reg = PCH_TRANSCONF(pipe);
1238 val = I915_READ(reg);
1239 enabled = !!(val & TRANS_ENABLE);
1240 WARN(enabled,
1241 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242 pipe_name(pipe));
1243 }
1244
1245 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, u32 port_sel, u32 val)
1247 {
1248 if ((val & DP_PORT_EN) == 0)
1249 return false;
1250
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
1252 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255 return false;
1256 } else {
1257 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258 return false;
1259 }
1260 return true;
1261 }
1262
1263 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, u32 val)
1265 {
1266 if ((val & SDVO_ENABLE) == 0)
1267 return false;
1268
1269 if (HAS_PCH_CPT(dev_priv->dev)) {
1270 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1271 return false;
1272 } else {
1273 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1274 return false;
1275 }
1276 return true;
1277 }
1278
1279 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280 enum pipe pipe, u32 val)
1281 {
1282 if ((val & LVDS_PORT_EN) == 0)
1283 return false;
1284
1285 if (HAS_PCH_CPT(dev_priv->dev)) {
1286 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287 return false;
1288 } else {
1289 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290 return false;
1291 }
1292 return true;
1293 }
1294
1295 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe, u32 val)
1297 {
1298 if ((val & ADPA_DAC_ENABLE) == 0)
1299 return false;
1300 if (HAS_PCH_CPT(dev_priv->dev)) {
1301 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302 return false;
1303 } else {
1304 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305 return false;
1306 }
1307 return true;
1308 }
1309
1310 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311 enum pipe pipe, int reg, u32 port_sel)
1312 {
1313 u32 val = I915_READ(reg);
1314 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316 reg, pipe_name(pipe));
1317
1318 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319 && (val & DP_PIPEB_SELECT),
1320 "IBX PCH dp port still using transcoder B\n");
1321 }
1322
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324 enum pipe pipe, int reg)
1325 {
1326 u32 val = I915_READ(reg);
1327 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329 reg, pipe_name(pipe));
1330
1331 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332 && (val & SDVO_PIPE_B_SELECT),
1333 "IBX PCH hdmi port still using transcoder B\n");
1334 }
1335
1336 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337 enum pipe pipe)
1338 {
1339 int reg;
1340 u32 val;
1341
1342 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1345
1346 reg = PCH_ADPA;
1347 val = I915_READ(reg);
1348 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349 "PCH VGA enabled on transcoder %c, should be disabled\n",
1350 pipe_name(pipe));
1351
1352 reg = PCH_LVDS;
1353 val = I915_READ(reg);
1354 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1356 pipe_name(pipe));
1357
1358 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1361 }
1362
1363 static void intel_init_dpio(struct drm_device *dev)
1364 {
1365 struct drm_i915_private *dev_priv = dev->dev_private;
1366
1367 if (!IS_VALLEYVIEW(dev))
1368 return;
1369
1370 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1371 }
1372
1373 static void intel_reset_dpio(struct drm_device *dev)
1374 {
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1376
1377 if (!IS_VALLEYVIEW(dev))
1378 return;
1379
1380 /*
1381 * Enable the CRI clock source so we can get at the display and the
1382 * reference clock for VGA hotplug / manual detection.
1383 */
1384 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1385 DPLL_REFA_CLK_ENABLE_VLV |
1386 DPLL_INTEGRATED_CRI_CLK_VLV);
1387
1388 /*
1389 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1390 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1391 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1392 * b. The other bits such as sfr settings / modesel may all be set
1393 * to 0.
1394 *
1395 * This should only be done on init and resume from S3 with both
1396 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1397 */
1398 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1399 }
1400
1401 static void vlv_enable_pll(struct intel_crtc *crtc)
1402 {
1403 struct drm_device *dev = crtc->base.dev;
1404 struct drm_i915_private *dev_priv = dev->dev_private;
1405 int reg = DPLL(crtc->pipe);
1406 u32 dpll = crtc->config.dpll_hw_state.dpll;
1407
1408 assert_pipe_disabled(dev_priv, crtc->pipe);
1409
1410 /* No really, not for ILK+ */
1411 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1412
1413 /* PLL is protected by panel, make sure we can write it */
1414 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1415 assert_panel_unlocked(dev_priv, crtc->pipe);
1416
1417 I915_WRITE(reg, dpll);
1418 POSTING_READ(reg);
1419 udelay(150);
1420
1421 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1422 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1423
1424 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1425 POSTING_READ(DPLL_MD(crtc->pipe));
1426
1427 /* We do this three times for luck */
1428 I915_WRITE(reg, dpll);
1429 POSTING_READ(reg);
1430 udelay(150); /* wait for warmup */
1431 I915_WRITE(reg, dpll);
1432 POSTING_READ(reg);
1433 udelay(150); /* wait for warmup */
1434 I915_WRITE(reg, dpll);
1435 POSTING_READ(reg);
1436 udelay(150); /* wait for warmup */
1437 }
1438
1439 static void i9xx_enable_pll(struct intel_crtc *crtc)
1440 {
1441 struct drm_device *dev = crtc->base.dev;
1442 struct drm_i915_private *dev_priv = dev->dev_private;
1443 int reg = DPLL(crtc->pipe);
1444 u32 dpll = crtc->config.dpll_hw_state.dpll;
1445
1446 assert_pipe_disabled(dev_priv, crtc->pipe);
1447
1448 /* No really, not for ILK+ */
1449 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1450
1451 /* PLL is protected by panel, make sure we can write it */
1452 if (IS_MOBILE(dev) && !IS_I830(dev))
1453 assert_panel_unlocked(dev_priv, crtc->pipe);
1454
1455 I915_WRITE(reg, dpll);
1456
1457 /* Wait for the clocks to stabilize. */
1458 POSTING_READ(reg);
1459 udelay(150);
1460
1461 if (INTEL_INFO(dev)->gen >= 4) {
1462 I915_WRITE(DPLL_MD(crtc->pipe),
1463 crtc->config.dpll_hw_state.dpll_md);
1464 } else {
1465 /* The pixel multiplier can only be updated once the
1466 * DPLL is enabled and the clocks are stable.
1467 *
1468 * So write it again.
1469 */
1470 I915_WRITE(reg, dpll);
1471 }
1472
1473 /* We do this three times for luck */
1474 I915_WRITE(reg, dpll);
1475 POSTING_READ(reg);
1476 udelay(150); /* wait for warmup */
1477 I915_WRITE(reg, dpll);
1478 POSTING_READ(reg);
1479 udelay(150); /* wait for warmup */
1480 I915_WRITE(reg, dpll);
1481 POSTING_READ(reg);
1482 udelay(150); /* wait for warmup */
1483 }
1484
1485 /**
1486 * i9xx_disable_pll - disable a PLL
1487 * @dev_priv: i915 private structure
1488 * @pipe: pipe PLL to disable
1489 *
1490 * Disable the PLL for @pipe, making sure the pipe is off first.
1491 *
1492 * Note! This is for pre-ILK only.
1493 */
1494 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1495 {
1496 /* Don't disable pipe A or pipe A PLLs if needed */
1497 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1498 return;
1499
1500 /* Make sure the pipe isn't still relying on us */
1501 assert_pipe_disabled(dev_priv, pipe);
1502
1503 I915_WRITE(DPLL(pipe), 0);
1504 POSTING_READ(DPLL(pipe));
1505 }
1506
1507 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1508 {
1509 u32 val = 0;
1510
1511 /* Make sure the pipe isn't still relying on us */
1512 assert_pipe_disabled(dev_priv, pipe);
1513
1514 /*
1515 * Leave integrated clock source and reference clock enabled for pipe B.
1516 * The latter is needed for VGA hotplug / manual detection.
1517 */
1518 if (pipe == PIPE_B)
1519 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1520 I915_WRITE(DPLL(pipe), val);
1521 POSTING_READ(DPLL(pipe));
1522 }
1523
1524 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1525 struct intel_digital_port *dport)
1526 {
1527 u32 port_mask;
1528
1529 switch (dport->port) {
1530 case PORT_B:
1531 port_mask = DPLL_PORTB_READY_MASK;
1532 break;
1533 case PORT_C:
1534 port_mask = DPLL_PORTC_READY_MASK;
1535 break;
1536 default:
1537 BUG();
1538 }
1539
1540 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1541 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1542 port_name(dport->port), I915_READ(DPLL(0)));
1543 }
1544
1545 /**
1546 * ironlake_enable_shared_dpll - enable PCH PLL
1547 * @dev_priv: i915 private structure
1548 * @pipe: pipe PLL to enable
1549 *
1550 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1551 * drives the transcoder clock.
1552 */
1553 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1554 {
1555 struct drm_device *dev = crtc->base.dev;
1556 struct drm_i915_private *dev_priv = dev->dev_private;
1557 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1558
1559 /* PCH PLLs only available on ILK, SNB and IVB */
1560 BUG_ON(INTEL_INFO(dev)->gen < 5);
1561 if (WARN_ON(pll == NULL))
1562 return;
1563
1564 if (WARN_ON(pll->refcount == 0))
1565 return;
1566
1567 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1568 pll->name, pll->active, pll->on,
1569 crtc->base.base.id);
1570
1571 if (pll->active++) {
1572 WARN_ON(!pll->on);
1573 assert_shared_dpll_enabled(dev_priv, pll);
1574 return;
1575 }
1576 WARN_ON(pll->on);
1577
1578 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1579 pll->enable(dev_priv, pll);
1580 pll->on = true;
1581 }
1582
1583 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1584 {
1585 struct drm_device *dev = crtc->base.dev;
1586 struct drm_i915_private *dev_priv = dev->dev_private;
1587 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1588
1589 /* PCH only available on ILK+ */
1590 BUG_ON(INTEL_INFO(dev)->gen < 5);
1591 if (WARN_ON(pll == NULL))
1592 return;
1593
1594 if (WARN_ON(pll->refcount == 0))
1595 return;
1596
1597 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1598 pll->name, pll->active, pll->on,
1599 crtc->base.base.id);
1600
1601 if (WARN_ON(pll->active == 0)) {
1602 assert_shared_dpll_disabled(dev_priv, pll);
1603 return;
1604 }
1605
1606 assert_shared_dpll_enabled(dev_priv, pll);
1607 WARN_ON(!pll->on);
1608 if (--pll->active)
1609 return;
1610
1611 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1612 pll->disable(dev_priv, pll);
1613 pll->on = false;
1614 }
1615
1616 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1617 enum pipe pipe)
1618 {
1619 struct drm_device *dev = dev_priv->dev;
1620 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1622 uint32_t reg, val, pipeconf_val;
1623
1624 /* PCH only available on ILK+ */
1625 BUG_ON(INTEL_INFO(dev)->gen < 5);
1626
1627 /* Make sure PCH DPLL is enabled */
1628 assert_shared_dpll_enabled(dev_priv,
1629 intel_crtc_to_shared_dpll(intel_crtc));
1630
1631 /* FDI must be feeding us bits for PCH ports */
1632 assert_fdi_tx_enabled(dev_priv, pipe);
1633 assert_fdi_rx_enabled(dev_priv, pipe);
1634
1635 if (HAS_PCH_CPT(dev)) {
1636 /* Workaround: Set the timing override bit before enabling the
1637 * pch transcoder. */
1638 reg = TRANS_CHICKEN2(pipe);
1639 val = I915_READ(reg);
1640 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1641 I915_WRITE(reg, val);
1642 }
1643
1644 reg = PCH_TRANSCONF(pipe);
1645 val = I915_READ(reg);
1646 pipeconf_val = I915_READ(PIPECONF(pipe));
1647
1648 if (HAS_PCH_IBX(dev_priv->dev)) {
1649 /*
1650 * make the BPC in transcoder be consistent with
1651 * that in pipeconf reg.
1652 */
1653 val &= ~PIPECONF_BPC_MASK;
1654 val |= pipeconf_val & PIPECONF_BPC_MASK;
1655 }
1656
1657 val &= ~TRANS_INTERLACE_MASK;
1658 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1659 if (HAS_PCH_IBX(dev_priv->dev) &&
1660 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1661 val |= TRANS_LEGACY_INTERLACED_ILK;
1662 else
1663 val |= TRANS_INTERLACED;
1664 else
1665 val |= TRANS_PROGRESSIVE;
1666
1667 I915_WRITE(reg, val | TRANS_ENABLE);
1668 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1669 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1670 }
1671
1672 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1673 enum transcoder cpu_transcoder)
1674 {
1675 u32 val, pipeconf_val;
1676
1677 /* PCH only available on ILK+ */
1678 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1679
1680 /* FDI must be feeding us bits for PCH ports */
1681 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1682 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1683
1684 /* Workaround: set timing override bit. */
1685 val = I915_READ(_TRANSA_CHICKEN2);
1686 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687 I915_WRITE(_TRANSA_CHICKEN2, val);
1688
1689 val = TRANS_ENABLE;
1690 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1691
1692 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1693 PIPECONF_INTERLACED_ILK)
1694 val |= TRANS_INTERLACED;
1695 else
1696 val |= TRANS_PROGRESSIVE;
1697
1698 I915_WRITE(LPT_TRANSCONF, val);
1699 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1700 DRM_ERROR("Failed to enable PCH transcoder\n");
1701 }
1702
1703 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1704 enum pipe pipe)
1705 {
1706 struct drm_device *dev = dev_priv->dev;
1707 uint32_t reg, val;
1708
1709 /* FDI relies on the transcoder */
1710 assert_fdi_tx_disabled(dev_priv, pipe);
1711 assert_fdi_rx_disabled(dev_priv, pipe);
1712
1713 /* Ports must be off as well */
1714 assert_pch_ports_disabled(dev_priv, pipe);
1715
1716 reg = PCH_TRANSCONF(pipe);
1717 val = I915_READ(reg);
1718 val &= ~TRANS_ENABLE;
1719 I915_WRITE(reg, val);
1720 /* wait for PCH transcoder off, transcoder state */
1721 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1722 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1723
1724 if (!HAS_PCH_IBX(dev)) {
1725 /* Workaround: Clear the timing override chicken bit again. */
1726 reg = TRANS_CHICKEN2(pipe);
1727 val = I915_READ(reg);
1728 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1729 I915_WRITE(reg, val);
1730 }
1731 }
1732
1733 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1734 {
1735 u32 val;
1736
1737 val = I915_READ(LPT_TRANSCONF);
1738 val &= ~TRANS_ENABLE;
1739 I915_WRITE(LPT_TRANSCONF, val);
1740 /* wait for PCH transcoder off, transcoder state */
1741 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1742 DRM_ERROR("Failed to disable PCH transcoder\n");
1743
1744 /* Workaround: clear timing override bit. */
1745 val = I915_READ(_TRANSA_CHICKEN2);
1746 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1747 I915_WRITE(_TRANSA_CHICKEN2, val);
1748 }
1749
1750 /**
1751 * intel_enable_pipe - enable a pipe, asserting requirements
1752 * @crtc: crtc responsible for the pipe
1753 *
1754 * Enable @crtc's pipe, making sure that various hardware specific requirements
1755 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1756 */
1757 static void intel_enable_pipe(struct intel_crtc *crtc)
1758 {
1759 struct drm_device *dev = crtc->base.dev;
1760 struct drm_i915_private *dev_priv = dev->dev_private;
1761 enum pipe pipe = crtc->pipe;
1762 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1763 pipe);
1764 enum pipe pch_transcoder;
1765 int reg;
1766 u32 val;
1767
1768 assert_planes_disabled(dev_priv, pipe);
1769 assert_cursor_disabled(dev_priv, pipe);
1770 assert_sprites_disabled(dev_priv, pipe);
1771
1772 if (HAS_PCH_LPT(dev_priv->dev))
1773 pch_transcoder = TRANSCODER_A;
1774 else
1775 pch_transcoder = pipe;
1776
1777 /*
1778 * A pipe without a PLL won't actually be able to drive bits from
1779 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1780 * need the check.
1781 */
1782 if (!HAS_PCH_SPLIT(dev_priv->dev))
1783 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1784 assert_dsi_pll_enabled(dev_priv);
1785 else
1786 assert_pll_enabled(dev_priv, pipe);
1787 else {
1788 if (crtc->config.has_pch_encoder) {
1789 /* if driving the PCH, we need FDI enabled */
1790 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1791 assert_fdi_tx_pll_enabled(dev_priv,
1792 (enum pipe) cpu_transcoder);
1793 }
1794 /* FIXME: assert CPU port conditions for SNB+ */
1795 }
1796
1797 reg = PIPECONF(cpu_transcoder);
1798 val = I915_READ(reg);
1799 if (val & PIPECONF_ENABLE) {
1800 WARN_ON(!(pipe == PIPE_A &&
1801 dev_priv->quirks & QUIRK_PIPEA_FORCE));
1802 return;
1803 }
1804
1805 I915_WRITE(reg, val | PIPECONF_ENABLE);
1806 POSTING_READ(reg);
1807
1808 /*
1809 * There's no guarantee the pipe will really start running now. It
1810 * depends on the Gen, the output type and the relative order between
1811 * pipe and plane enabling. Avoid waiting on HSW+ since it's not
1812 * necessary.
1813 * TODO: audit the previous gens.
1814 */
1815 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
1816 intel_wait_for_vblank(dev_priv->dev, pipe);
1817 }
1818
1819 /**
1820 * intel_disable_pipe - disable a pipe, asserting requirements
1821 * @dev_priv: i915 private structure
1822 * @pipe: pipe to disable
1823 *
1824 * Disable @pipe, making sure that various hardware specific requirements
1825 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1826 *
1827 * @pipe should be %PIPE_A or %PIPE_B.
1828 *
1829 * Will wait until the pipe has shut down before returning.
1830 */
1831 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1832 enum pipe pipe)
1833 {
1834 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1835 pipe);
1836 int reg;
1837 u32 val;
1838
1839 /*
1840 * Make sure planes won't keep trying to pump pixels to us,
1841 * or we might hang the display.
1842 */
1843 assert_planes_disabled(dev_priv, pipe);
1844 assert_cursor_disabled(dev_priv, pipe);
1845 assert_sprites_disabled(dev_priv, pipe);
1846
1847 /* Don't disable pipe A or pipe A PLLs if needed */
1848 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1849 return;
1850
1851 reg = PIPECONF(cpu_transcoder);
1852 val = I915_READ(reg);
1853 if ((val & PIPECONF_ENABLE) == 0)
1854 return;
1855
1856 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1857 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1858 }
1859
1860 /*
1861 * Plane regs are double buffered, going from enabled->disabled needs a
1862 * trigger in order to latch. The display address reg provides this.
1863 */
1864 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1865 enum plane plane)
1866 {
1867 struct drm_device *dev = dev_priv->dev;
1868 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1869
1870 I915_WRITE(reg, I915_READ(reg));
1871 POSTING_READ(reg);
1872 }
1873
1874 /**
1875 * intel_enable_primary_plane - enable the primary plane on a given pipe
1876 * @dev_priv: i915 private structure
1877 * @plane: plane to enable
1878 * @pipe: pipe being fed
1879 *
1880 * Enable @plane on @pipe, making sure that @pipe is running first.
1881 */
1882 static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1883 enum plane plane, enum pipe pipe)
1884 {
1885 struct intel_crtc *intel_crtc =
1886 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1887 int reg;
1888 u32 val;
1889
1890 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1891 assert_pipe_enabled(dev_priv, pipe);
1892
1893 WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1894
1895 intel_crtc->primary_enabled = true;
1896
1897 reg = DSPCNTR(plane);
1898 val = I915_READ(reg);
1899 if (val & DISPLAY_PLANE_ENABLE)
1900 return;
1901
1902 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1903 intel_flush_primary_plane(dev_priv, plane);
1904 intel_wait_for_vblank(dev_priv->dev, pipe);
1905 }
1906
1907 /**
1908 * intel_disable_primary_plane - disable the primary plane
1909 * @dev_priv: i915 private structure
1910 * @plane: plane to disable
1911 * @pipe: pipe consuming the data
1912 *
1913 * Disable @plane; should be an independent operation.
1914 */
1915 static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1916 enum plane plane, enum pipe pipe)
1917 {
1918 struct intel_crtc *intel_crtc =
1919 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1920 int reg;
1921 u32 val;
1922
1923 WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1924
1925 intel_crtc->primary_enabled = false;
1926
1927 reg = DSPCNTR(plane);
1928 val = I915_READ(reg);
1929 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1930 return;
1931
1932 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1933 intel_flush_primary_plane(dev_priv, plane);
1934 intel_wait_for_vblank(dev_priv->dev, pipe);
1935 }
1936
1937 static bool need_vtd_wa(struct drm_device *dev)
1938 {
1939 #ifdef CONFIG_INTEL_IOMMU
1940 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1941 return true;
1942 #endif
1943 return false;
1944 }
1945
1946 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
1947 {
1948 int tile_height;
1949
1950 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
1951 return ALIGN(height, tile_height);
1952 }
1953
1954 int
1955 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1956 struct drm_i915_gem_object *obj,
1957 struct intel_ring_buffer *pipelined)
1958 {
1959 struct drm_i915_private *dev_priv = dev->dev_private;
1960 u32 alignment;
1961 int ret;
1962
1963 switch (obj->tiling_mode) {
1964 case I915_TILING_NONE:
1965 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1966 alignment = 128 * 1024;
1967 else if (INTEL_INFO(dev)->gen >= 4)
1968 alignment = 4 * 1024;
1969 else
1970 alignment = 64 * 1024;
1971 break;
1972 case I915_TILING_X:
1973 /* pin() will align the object as required by fence */
1974 alignment = 0;
1975 break;
1976 case I915_TILING_Y:
1977 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1978 return -EINVAL;
1979 default:
1980 BUG();
1981 }
1982
1983 /* Note that the w/a also requires 64 PTE of padding following the
1984 * bo. We currently fill all unused PTE with the shadow page and so
1985 * we should always have valid PTE following the scanout preventing
1986 * the VT-d warning.
1987 */
1988 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1989 alignment = 256 * 1024;
1990
1991 dev_priv->mm.interruptible = false;
1992 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1993 if (ret)
1994 goto err_interruptible;
1995
1996 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1997 * fence, whereas 965+ only requires a fence if using
1998 * framebuffer compression. For simplicity, we always install
1999 * a fence as the cost is not that onerous.
2000 */
2001 ret = i915_gem_object_get_fence(obj);
2002 if (ret)
2003 goto err_unpin;
2004
2005 i915_gem_object_pin_fence(obj);
2006
2007 dev_priv->mm.interruptible = true;
2008 return 0;
2009
2010 err_unpin:
2011 i915_gem_object_unpin_from_display_plane(obj);
2012 err_interruptible:
2013 dev_priv->mm.interruptible = true;
2014 return ret;
2015 }
2016
2017 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2018 {
2019 i915_gem_object_unpin_fence(obj);
2020 i915_gem_object_unpin_from_display_plane(obj);
2021 }
2022
2023 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2024 * is assumed to be a power-of-two. */
2025 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2026 unsigned int tiling_mode,
2027 unsigned int cpp,
2028 unsigned int pitch)
2029 {
2030 if (tiling_mode != I915_TILING_NONE) {
2031 unsigned int tile_rows, tiles;
2032
2033 tile_rows = *y / 8;
2034 *y %= 8;
2035
2036 tiles = *x / (512/cpp);
2037 *x %= 512/cpp;
2038
2039 return tile_rows * pitch * 8 + tiles * 4096;
2040 } else {
2041 unsigned int offset;
2042
2043 offset = *y * pitch + *x * cpp;
2044 *y = 0;
2045 *x = (offset & 4095) / cpp;
2046 return offset & -4096;
2047 }
2048 }
2049
2050 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2051 int x, int y)
2052 {
2053 struct drm_device *dev = crtc->dev;
2054 struct drm_i915_private *dev_priv = dev->dev_private;
2055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2056 struct intel_framebuffer *intel_fb;
2057 struct drm_i915_gem_object *obj;
2058 int plane = intel_crtc->plane;
2059 unsigned long linear_offset;
2060 u32 dspcntr;
2061 u32 reg;
2062
2063 switch (plane) {
2064 case 0:
2065 case 1:
2066 break;
2067 default:
2068 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2069 return -EINVAL;
2070 }
2071
2072 intel_fb = to_intel_framebuffer(fb);
2073 obj = intel_fb->obj;
2074
2075 reg = DSPCNTR(plane);
2076 dspcntr = I915_READ(reg);
2077 /* Mask out pixel format bits in case we change it */
2078 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2079 switch (fb->pixel_format) {
2080 case DRM_FORMAT_C8:
2081 dspcntr |= DISPPLANE_8BPP;
2082 break;
2083 case DRM_FORMAT_XRGB1555:
2084 case DRM_FORMAT_ARGB1555:
2085 dspcntr |= DISPPLANE_BGRX555;
2086 break;
2087 case DRM_FORMAT_RGB565:
2088 dspcntr |= DISPPLANE_BGRX565;
2089 break;
2090 case DRM_FORMAT_XRGB8888:
2091 case DRM_FORMAT_ARGB8888:
2092 dspcntr |= DISPPLANE_BGRX888;
2093 break;
2094 case DRM_FORMAT_XBGR8888:
2095 case DRM_FORMAT_ABGR8888:
2096 dspcntr |= DISPPLANE_RGBX888;
2097 break;
2098 case DRM_FORMAT_XRGB2101010:
2099 case DRM_FORMAT_ARGB2101010:
2100 dspcntr |= DISPPLANE_BGRX101010;
2101 break;
2102 case DRM_FORMAT_XBGR2101010:
2103 case DRM_FORMAT_ABGR2101010:
2104 dspcntr |= DISPPLANE_RGBX101010;
2105 break;
2106 default:
2107 BUG();
2108 }
2109
2110 if (INTEL_INFO(dev)->gen >= 4) {
2111 if (obj->tiling_mode != I915_TILING_NONE)
2112 dspcntr |= DISPPLANE_TILED;
2113 else
2114 dspcntr &= ~DISPPLANE_TILED;
2115 }
2116
2117 if (IS_G4X(dev))
2118 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2119
2120 I915_WRITE(reg, dspcntr);
2121
2122 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2123
2124 if (INTEL_INFO(dev)->gen >= 4) {
2125 intel_crtc->dspaddr_offset =
2126 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2127 fb->bits_per_pixel / 8,
2128 fb->pitches[0]);
2129 linear_offset -= intel_crtc->dspaddr_offset;
2130 } else {
2131 intel_crtc->dspaddr_offset = linear_offset;
2132 }
2133
2134 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2135 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2136 fb->pitches[0]);
2137 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2138 if (INTEL_INFO(dev)->gen >= 4) {
2139 I915_WRITE(DSPSURF(plane),
2140 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2141 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2142 I915_WRITE(DSPLINOFF(plane), linear_offset);
2143 } else
2144 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2145 POSTING_READ(reg);
2146
2147 return 0;
2148 }
2149
2150 static int ironlake_update_plane(struct drm_crtc *crtc,
2151 struct drm_framebuffer *fb, int x, int y)
2152 {
2153 struct drm_device *dev = crtc->dev;
2154 struct drm_i915_private *dev_priv = dev->dev_private;
2155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2156 struct intel_framebuffer *intel_fb;
2157 struct drm_i915_gem_object *obj;
2158 int plane = intel_crtc->plane;
2159 unsigned long linear_offset;
2160 u32 dspcntr;
2161 u32 reg;
2162
2163 switch (plane) {
2164 case 0:
2165 case 1:
2166 case 2:
2167 break;
2168 default:
2169 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2170 return -EINVAL;
2171 }
2172
2173 intel_fb = to_intel_framebuffer(fb);
2174 obj = intel_fb->obj;
2175
2176 reg = DSPCNTR(plane);
2177 dspcntr = I915_READ(reg);
2178 /* Mask out pixel format bits in case we change it */
2179 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2180 switch (fb->pixel_format) {
2181 case DRM_FORMAT_C8:
2182 dspcntr |= DISPPLANE_8BPP;
2183 break;
2184 case DRM_FORMAT_RGB565:
2185 dspcntr |= DISPPLANE_BGRX565;
2186 break;
2187 case DRM_FORMAT_XRGB8888:
2188 case DRM_FORMAT_ARGB8888:
2189 dspcntr |= DISPPLANE_BGRX888;
2190 break;
2191 case DRM_FORMAT_XBGR8888:
2192 case DRM_FORMAT_ABGR8888:
2193 dspcntr |= DISPPLANE_RGBX888;
2194 break;
2195 case DRM_FORMAT_XRGB2101010:
2196 case DRM_FORMAT_ARGB2101010:
2197 dspcntr |= DISPPLANE_BGRX101010;
2198 break;
2199 case DRM_FORMAT_XBGR2101010:
2200 case DRM_FORMAT_ABGR2101010:
2201 dspcntr |= DISPPLANE_RGBX101010;
2202 break;
2203 default:
2204 BUG();
2205 }
2206
2207 if (obj->tiling_mode != I915_TILING_NONE)
2208 dspcntr |= DISPPLANE_TILED;
2209 else
2210 dspcntr &= ~DISPPLANE_TILED;
2211
2212 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2213 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2214 else
2215 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2216
2217 I915_WRITE(reg, dspcntr);
2218
2219 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2220 intel_crtc->dspaddr_offset =
2221 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2222 fb->bits_per_pixel / 8,
2223 fb->pitches[0]);
2224 linear_offset -= intel_crtc->dspaddr_offset;
2225
2226 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2227 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2228 fb->pitches[0]);
2229 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2230 I915_WRITE(DSPSURF(plane),
2231 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2232 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2233 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2234 } else {
2235 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2236 I915_WRITE(DSPLINOFF(plane), linear_offset);
2237 }
2238 POSTING_READ(reg);
2239
2240 return 0;
2241 }
2242
2243 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2244 static int
2245 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2246 int x, int y, enum mode_set_atomic state)
2247 {
2248 struct drm_device *dev = crtc->dev;
2249 struct drm_i915_private *dev_priv = dev->dev_private;
2250
2251 if (dev_priv->display.disable_fbc)
2252 dev_priv->display.disable_fbc(dev);
2253 intel_increase_pllclock(crtc);
2254
2255 return dev_priv->display.update_plane(crtc, fb, x, y);
2256 }
2257
2258 void intel_display_handle_reset(struct drm_device *dev)
2259 {
2260 struct drm_i915_private *dev_priv = dev->dev_private;
2261 struct drm_crtc *crtc;
2262
2263 /*
2264 * Flips in the rings have been nuked by the reset,
2265 * so complete all pending flips so that user space
2266 * will get its events and not get stuck.
2267 *
2268 * Also update the base address of all primary
2269 * planes to the the last fb to make sure we're
2270 * showing the correct fb after a reset.
2271 *
2272 * Need to make two loops over the crtcs so that we
2273 * don't try to grab a crtc mutex before the
2274 * pending_flip_queue really got woken up.
2275 */
2276
2277 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2279 enum plane plane = intel_crtc->plane;
2280
2281 intel_prepare_page_flip(dev, plane);
2282 intel_finish_page_flip_plane(dev, plane);
2283 }
2284
2285 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2287
2288 mutex_lock(&crtc->mutex);
2289 /*
2290 * FIXME: Once we have proper support for primary planes (and
2291 * disabling them without disabling the entire crtc) allow again
2292 * a NULL crtc->fb.
2293 */
2294 if (intel_crtc->active && crtc->fb)
2295 dev_priv->display.update_plane(crtc, crtc->fb,
2296 crtc->x, crtc->y);
2297 mutex_unlock(&crtc->mutex);
2298 }
2299 }
2300
2301 static int
2302 intel_finish_fb(struct drm_framebuffer *old_fb)
2303 {
2304 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2305 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2306 bool was_interruptible = dev_priv->mm.interruptible;
2307 int ret;
2308
2309 /* Big Hammer, we also need to ensure that any pending
2310 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2311 * current scanout is retired before unpinning the old
2312 * framebuffer.
2313 *
2314 * This should only fail upon a hung GPU, in which case we
2315 * can safely continue.
2316 */
2317 dev_priv->mm.interruptible = false;
2318 ret = i915_gem_object_finish_gpu(obj);
2319 dev_priv->mm.interruptible = was_interruptible;
2320
2321 return ret;
2322 }
2323
2324 static int
2325 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2326 struct drm_framebuffer *fb)
2327 {
2328 struct drm_device *dev = crtc->dev;
2329 struct drm_i915_private *dev_priv = dev->dev_private;
2330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2331 struct drm_framebuffer *old_fb;
2332 int ret;
2333
2334 /* no fb bound */
2335 if (!fb) {
2336 DRM_ERROR("No FB bound\n");
2337 return 0;
2338 }
2339
2340 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2341 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2342 plane_name(intel_crtc->plane),
2343 INTEL_INFO(dev)->num_pipes);
2344 return -EINVAL;
2345 }
2346
2347 mutex_lock(&dev->struct_mutex);
2348 ret = intel_pin_and_fence_fb_obj(dev,
2349 to_intel_framebuffer(fb)->obj,
2350 NULL);
2351 if (ret != 0) {
2352 mutex_unlock(&dev->struct_mutex);
2353 DRM_ERROR("pin & fence failed\n");
2354 return ret;
2355 }
2356
2357 /*
2358 * Update pipe size and adjust fitter if needed: the reason for this is
2359 * that in compute_mode_changes we check the native mode (not the pfit
2360 * mode) to see if we can flip rather than do a full mode set. In the
2361 * fastboot case, we'll flip, but if we don't update the pipesrc and
2362 * pfit state, we'll end up with a big fb scanned out into the wrong
2363 * sized surface.
2364 *
2365 * To fix this properly, we need to hoist the checks up into
2366 * compute_mode_changes (or above), check the actual pfit state and
2367 * whether the platform allows pfit disable with pipe active, and only
2368 * then update the pipesrc and pfit state, even on the flip path.
2369 */
2370 if (i915.fastboot) {
2371 const struct drm_display_mode *adjusted_mode =
2372 &intel_crtc->config.adjusted_mode;
2373
2374 I915_WRITE(PIPESRC(intel_crtc->pipe),
2375 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2376 (adjusted_mode->crtc_vdisplay - 1));
2377 if (!intel_crtc->config.pch_pfit.enabled &&
2378 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2379 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2380 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2381 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2382 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2383 }
2384 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2385 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2386 }
2387
2388 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2389 if (ret) {
2390 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2391 mutex_unlock(&dev->struct_mutex);
2392 DRM_ERROR("failed to update base address\n");
2393 return ret;
2394 }
2395
2396 old_fb = crtc->fb;
2397 crtc->fb = fb;
2398 crtc->x = x;
2399 crtc->y = y;
2400
2401 if (old_fb) {
2402 if (intel_crtc->active && old_fb != fb)
2403 intel_wait_for_vblank(dev, intel_crtc->pipe);
2404 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2405 }
2406
2407 intel_update_fbc(dev);
2408 intel_edp_psr_update(dev);
2409 mutex_unlock(&dev->struct_mutex);
2410
2411 return 0;
2412 }
2413
2414 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2415 {
2416 struct drm_device *dev = crtc->dev;
2417 struct drm_i915_private *dev_priv = dev->dev_private;
2418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2419 int pipe = intel_crtc->pipe;
2420 u32 reg, temp;
2421
2422 /* enable normal train */
2423 reg = FDI_TX_CTL(pipe);
2424 temp = I915_READ(reg);
2425 if (IS_IVYBRIDGE(dev)) {
2426 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2427 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2428 } else {
2429 temp &= ~FDI_LINK_TRAIN_NONE;
2430 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2431 }
2432 I915_WRITE(reg, temp);
2433
2434 reg = FDI_RX_CTL(pipe);
2435 temp = I915_READ(reg);
2436 if (HAS_PCH_CPT(dev)) {
2437 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2438 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2439 } else {
2440 temp &= ~FDI_LINK_TRAIN_NONE;
2441 temp |= FDI_LINK_TRAIN_NONE;
2442 }
2443 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2444
2445 /* wait one idle pattern time */
2446 POSTING_READ(reg);
2447 udelay(1000);
2448
2449 /* IVB wants error correction enabled */
2450 if (IS_IVYBRIDGE(dev))
2451 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2452 FDI_FE_ERRC_ENABLE);
2453 }
2454
2455 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2456 {
2457 return crtc->base.enabled && crtc->active &&
2458 crtc->config.has_pch_encoder;
2459 }
2460
2461 static void ivb_modeset_global_resources(struct drm_device *dev)
2462 {
2463 struct drm_i915_private *dev_priv = dev->dev_private;
2464 struct intel_crtc *pipe_B_crtc =
2465 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2466 struct intel_crtc *pipe_C_crtc =
2467 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2468 uint32_t temp;
2469
2470 /*
2471 * When everything is off disable fdi C so that we could enable fdi B
2472 * with all lanes. Note that we don't care about enabled pipes without
2473 * an enabled pch encoder.
2474 */
2475 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2476 !pipe_has_enabled_pch(pipe_C_crtc)) {
2477 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2478 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2479
2480 temp = I915_READ(SOUTH_CHICKEN1);
2481 temp &= ~FDI_BC_BIFURCATION_SELECT;
2482 DRM_DEBUG_KMS("disabling fdi C rx\n");
2483 I915_WRITE(SOUTH_CHICKEN1, temp);
2484 }
2485 }
2486
2487 /* The FDI link training functions for ILK/Ibexpeak. */
2488 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2489 {
2490 struct drm_device *dev = crtc->dev;
2491 struct drm_i915_private *dev_priv = dev->dev_private;
2492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2493 int pipe = intel_crtc->pipe;
2494 int plane = intel_crtc->plane;
2495 u32 reg, temp, tries;
2496
2497 /* FDI needs bits from pipe & plane first */
2498 assert_pipe_enabled(dev_priv, pipe);
2499 assert_plane_enabled(dev_priv, plane);
2500
2501 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2502 for train result */
2503 reg = FDI_RX_IMR(pipe);
2504 temp = I915_READ(reg);
2505 temp &= ~FDI_RX_SYMBOL_LOCK;
2506 temp &= ~FDI_RX_BIT_LOCK;
2507 I915_WRITE(reg, temp);
2508 I915_READ(reg);
2509 udelay(150);
2510
2511 /* enable CPU FDI TX and PCH FDI RX */
2512 reg = FDI_TX_CTL(pipe);
2513 temp = I915_READ(reg);
2514 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2515 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2516 temp &= ~FDI_LINK_TRAIN_NONE;
2517 temp |= FDI_LINK_TRAIN_PATTERN_1;
2518 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2519
2520 reg = FDI_RX_CTL(pipe);
2521 temp = I915_READ(reg);
2522 temp &= ~FDI_LINK_TRAIN_NONE;
2523 temp |= FDI_LINK_TRAIN_PATTERN_1;
2524 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2525
2526 POSTING_READ(reg);
2527 udelay(150);
2528
2529 /* Ironlake workaround, enable clock pointer after FDI enable*/
2530 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2531 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2532 FDI_RX_PHASE_SYNC_POINTER_EN);
2533
2534 reg = FDI_RX_IIR(pipe);
2535 for (tries = 0; tries < 5; tries++) {
2536 temp = I915_READ(reg);
2537 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2538
2539 if ((temp & FDI_RX_BIT_LOCK)) {
2540 DRM_DEBUG_KMS("FDI train 1 done.\n");
2541 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2542 break;
2543 }
2544 }
2545 if (tries == 5)
2546 DRM_ERROR("FDI train 1 fail!\n");
2547
2548 /* Train 2 */
2549 reg = FDI_TX_CTL(pipe);
2550 temp = I915_READ(reg);
2551 temp &= ~FDI_LINK_TRAIN_NONE;
2552 temp |= FDI_LINK_TRAIN_PATTERN_2;
2553 I915_WRITE(reg, temp);
2554
2555 reg = FDI_RX_CTL(pipe);
2556 temp = I915_READ(reg);
2557 temp &= ~FDI_LINK_TRAIN_NONE;
2558 temp |= FDI_LINK_TRAIN_PATTERN_2;
2559 I915_WRITE(reg, temp);
2560
2561 POSTING_READ(reg);
2562 udelay(150);
2563
2564 reg = FDI_RX_IIR(pipe);
2565 for (tries = 0; tries < 5; tries++) {
2566 temp = I915_READ(reg);
2567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2568
2569 if (temp & FDI_RX_SYMBOL_LOCK) {
2570 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2571 DRM_DEBUG_KMS("FDI train 2 done.\n");
2572 break;
2573 }
2574 }
2575 if (tries == 5)
2576 DRM_ERROR("FDI train 2 fail!\n");
2577
2578 DRM_DEBUG_KMS("FDI train done\n");
2579
2580 }
2581
2582 static const int snb_b_fdi_train_param[] = {
2583 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2584 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2585 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2586 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2587 };
2588
2589 /* The FDI link training functions for SNB/Cougarpoint. */
2590 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2591 {
2592 struct drm_device *dev = crtc->dev;
2593 struct drm_i915_private *dev_priv = dev->dev_private;
2594 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2595 int pipe = intel_crtc->pipe;
2596 u32 reg, temp, i, retry;
2597
2598 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2599 for train result */
2600 reg = FDI_RX_IMR(pipe);
2601 temp = I915_READ(reg);
2602 temp &= ~FDI_RX_SYMBOL_LOCK;
2603 temp &= ~FDI_RX_BIT_LOCK;
2604 I915_WRITE(reg, temp);
2605
2606 POSTING_READ(reg);
2607 udelay(150);
2608
2609 /* enable CPU FDI TX and PCH FDI RX */
2610 reg = FDI_TX_CTL(pipe);
2611 temp = I915_READ(reg);
2612 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2613 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2614 temp &= ~FDI_LINK_TRAIN_NONE;
2615 temp |= FDI_LINK_TRAIN_PATTERN_1;
2616 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2617 /* SNB-B */
2618 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2619 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2620
2621 I915_WRITE(FDI_RX_MISC(pipe),
2622 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2623
2624 reg = FDI_RX_CTL(pipe);
2625 temp = I915_READ(reg);
2626 if (HAS_PCH_CPT(dev)) {
2627 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2628 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2629 } else {
2630 temp &= ~FDI_LINK_TRAIN_NONE;
2631 temp |= FDI_LINK_TRAIN_PATTERN_1;
2632 }
2633 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2634
2635 POSTING_READ(reg);
2636 udelay(150);
2637
2638 for (i = 0; i < 4; i++) {
2639 reg = FDI_TX_CTL(pipe);
2640 temp = I915_READ(reg);
2641 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2642 temp |= snb_b_fdi_train_param[i];
2643 I915_WRITE(reg, temp);
2644
2645 POSTING_READ(reg);
2646 udelay(500);
2647
2648 for (retry = 0; retry < 5; retry++) {
2649 reg = FDI_RX_IIR(pipe);
2650 temp = I915_READ(reg);
2651 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2652 if (temp & FDI_RX_BIT_LOCK) {
2653 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2654 DRM_DEBUG_KMS("FDI train 1 done.\n");
2655 break;
2656 }
2657 udelay(50);
2658 }
2659 if (retry < 5)
2660 break;
2661 }
2662 if (i == 4)
2663 DRM_ERROR("FDI train 1 fail!\n");
2664
2665 /* Train 2 */
2666 reg = FDI_TX_CTL(pipe);
2667 temp = I915_READ(reg);
2668 temp &= ~FDI_LINK_TRAIN_NONE;
2669 temp |= FDI_LINK_TRAIN_PATTERN_2;
2670 if (IS_GEN6(dev)) {
2671 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2672 /* SNB-B */
2673 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2674 }
2675 I915_WRITE(reg, temp);
2676
2677 reg = FDI_RX_CTL(pipe);
2678 temp = I915_READ(reg);
2679 if (HAS_PCH_CPT(dev)) {
2680 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2681 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2682 } else {
2683 temp &= ~FDI_LINK_TRAIN_NONE;
2684 temp |= FDI_LINK_TRAIN_PATTERN_2;
2685 }
2686 I915_WRITE(reg, temp);
2687
2688 POSTING_READ(reg);
2689 udelay(150);
2690
2691 for (i = 0; i < 4; i++) {
2692 reg = FDI_TX_CTL(pipe);
2693 temp = I915_READ(reg);
2694 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2695 temp |= snb_b_fdi_train_param[i];
2696 I915_WRITE(reg, temp);
2697
2698 POSTING_READ(reg);
2699 udelay(500);
2700
2701 for (retry = 0; retry < 5; retry++) {
2702 reg = FDI_RX_IIR(pipe);
2703 temp = I915_READ(reg);
2704 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2705 if (temp & FDI_RX_SYMBOL_LOCK) {
2706 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2707 DRM_DEBUG_KMS("FDI train 2 done.\n");
2708 break;
2709 }
2710 udelay(50);
2711 }
2712 if (retry < 5)
2713 break;
2714 }
2715 if (i == 4)
2716 DRM_ERROR("FDI train 2 fail!\n");
2717
2718 DRM_DEBUG_KMS("FDI train done.\n");
2719 }
2720
2721 /* Manual link training for Ivy Bridge A0 parts */
2722 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2723 {
2724 struct drm_device *dev = crtc->dev;
2725 struct drm_i915_private *dev_priv = dev->dev_private;
2726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2727 int pipe = intel_crtc->pipe;
2728 u32 reg, temp, i, j;
2729
2730 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2731 for train result */
2732 reg = FDI_RX_IMR(pipe);
2733 temp = I915_READ(reg);
2734 temp &= ~FDI_RX_SYMBOL_LOCK;
2735 temp &= ~FDI_RX_BIT_LOCK;
2736 I915_WRITE(reg, temp);
2737
2738 POSTING_READ(reg);
2739 udelay(150);
2740
2741 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2742 I915_READ(FDI_RX_IIR(pipe)));
2743
2744 /* Try each vswing and preemphasis setting twice before moving on */
2745 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2746 /* disable first in case we need to retry */
2747 reg = FDI_TX_CTL(pipe);
2748 temp = I915_READ(reg);
2749 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2750 temp &= ~FDI_TX_ENABLE;
2751 I915_WRITE(reg, temp);
2752
2753 reg = FDI_RX_CTL(pipe);
2754 temp = I915_READ(reg);
2755 temp &= ~FDI_LINK_TRAIN_AUTO;
2756 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2757 temp &= ~FDI_RX_ENABLE;
2758 I915_WRITE(reg, temp);
2759
2760 /* enable CPU FDI TX and PCH FDI RX */
2761 reg = FDI_TX_CTL(pipe);
2762 temp = I915_READ(reg);
2763 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2764 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2765 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2766 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2767 temp |= snb_b_fdi_train_param[j/2];
2768 temp |= FDI_COMPOSITE_SYNC;
2769 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2770
2771 I915_WRITE(FDI_RX_MISC(pipe),
2772 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2773
2774 reg = FDI_RX_CTL(pipe);
2775 temp = I915_READ(reg);
2776 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2777 temp |= FDI_COMPOSITE_SYNC;
2778 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2779
2780 POSTING_READ(reg);
2781 udelay(1); /* should be 0.5us */
2782
2783 for (i = 0; i < 4; i++) {
2784 reg = FDI_RX_IIR(pipe);
2785 temp = I915_READ(reg);
2786 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2787
2788 if (temp & FDI_RX_BIT_LOCK ||
2789 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2790 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2791 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2792 i);
2793 break;
2794 }
2795 udelay(1); /* should be 0.5us */
2796 }
2797 if (i == 4) {
2798 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2799 continue;
2800 }
2801
2802 /* Train 2 */
2803 reg = FDI_TX_CTL(pipe);
2804 temp = I915_READ(reg);
2805 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2806 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2807 I915_WRITE(reg, temp);
2808
2809 reg = FDI_RX_CTL(pipe);
2810 temp = I915_READ(reg);
2811 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2812 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2813 I915_WRITE(reg, temp);
2814
2815 POSTING_READ(reg);
2816 udelay(2); /* should be 1.5us */
2817
2818 for (i = 0; i < 4; i++) {
2819 reg = FDI_RX_IIR(pipe);
2820 temp = I915_READ(reg);
2821 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2822
2823 if (temp & FDI_RX_SYMBOL_LOCK ||
2824 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2825 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2826 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2827 i);
2828 goto train_done;
2829 }
2830 udelay(2); /* should be 1.5us */
2831 }
2832 if (i == 4)
2833 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2834 }
2835
2836 train_done:
2837 DRM_DEBUG_KMS("FDI train done.\n");
2838 }
2839
2840 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2841 {
2842 struct drm_device *dev = intel_crtc->base.dev;
2843 struct drm_i915_private *dev_priv = dev->dev_private;
2844 int pipe = intel_crtc->pipe;
2845 u32 reg, temp;
2846
2847
2848 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2849 reg = FDI_RX_CTL(pipe);
2850 temp = I915_READ(reg);
2851 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2852 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2853 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2854 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2855
2856 POSTING_READ(reg);
2857 udelay(200);
2858
2859 /* Switch from Rawclk to PCDclk */
2860 temp = I915_READ(reg);
2861 I915_WRITE(reg, temp | FDI_PCDCLK);
2862
2863 POSTING_READ(reg);
2864 udelay(200);
2865
2866 /* Enable CPU FDI TX PLL, always on for Ironlake */
2867 reg = FDI_TX_CTL(pipe);
2868 temp = I915_READ(reg);
2869 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2870 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2871
2872 POSTING_READ(reg);
2873 udelay(100);
2874 }
2875 }
2876
2877 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2878 {
2879 struct drm_device *dev = intel_crtc->base.dev;
2880 struct drm_i915_private *dev_priv = dev->dev_private;
2881 int pipe = intel_crtc->pipe;
2882 u32 reg, temp;
2883
2884 /* Switch from PCDclk to Rawclk */
2885 reg = FDI_RX_CTL(pipe);
2886 temp = I915_READ(reg);
2887 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2888
2889 /* Disable CPU FDI TX PLL */
2890 reg = FDI_TX_CTL(pipe);
2891 temp = I915_READ(reg);
2892 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2893
2894 POSTING_READ(reg);
2895 udelay(100);
2896
2897 reg = FDI_RX_CTL(pipe);
2898 temp = I915_READ(reg);
2899 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2900
2901 /* Wait for the clocks to turn off. */
2902 POSTING_READ(reg);
2903 udelay(100);
2904 }
2905
2906 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2907 {
2908 struct drm_device *dev = crtc->dev;
2909 struct drm_i915_private *dev_priv = dev->dev_private;
2910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2911 int pipe = intel_crtc->pipe;
2912 u32 reg, temp;
2913
2914 /* disable CPU FDI tx and PCH FDI rx */
2915 reg = FDI_TX_CTL(pipe);
2916 temp = I915_READ(reg);
2917 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2918 POSTING_READ(reg);
2919
2920 reg = FDI_RX_CTL(pipe);
2921 temp = I915_READ(reg);
2922 temp &= ~(0x7 << 16);
2923 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2924 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2925
2926 POSTING_READ(reg);
2927 udelay(100);
2928
2929 /* Ironlake workaround, disable clock pointer after downing FDI */
2930 if (HAS_PCH_IBX(dev)) {
2931 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2932 }
2933
2934 /* still set train pattern 1 */
2935 reg = FDI_TX_CTL(pipe);
2936 temp = I915_READ(reg);
2937 temp &= ~FDI_LINK_TRAIN_NONE;
2938 temp |= FDI_LINK_TRAIN_PATTERN_1;
2939 I915_WRITE(reg, temp);
2940
2941 reg = FDI_RX_CTL(pipe);
2942 temp = I915_READ(reg);
2943 if (HAS_PCH_CPT(dev)) {
2944 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2945 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2946 } else {
2947 temp &= ~FDI_LINK_TRAIN_NONE;
2948 temp |= FDI_LINK_TRAIN_PATTERN_1;
2949 }
2950 /* BPC in FDI rx is consistent with that in PIPECONF */
2951 temp &= ~(0x07 << 16);
2952 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2953 I915_WRITE(reg, temp);
2954
2955 POSTING_READ(reg);
2956 udelay(100);
2957 }
2958
2959 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2960 {
2961 struct drm_device *dev = crtc->dev;
2962 struct drm_i915_private *dev_priv = dev->dev_private;
2963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2964 unsigned long flags;
2965 bool pending;
2966
2967 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2968 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2969 return false;
2970
2971 spin_lock_irqsave(&dev->event_lock, flags);
2972 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2973 spin_unlock_irqrestore(&dev->event_lock, flags);
2974
2975 return pending;
2976 }
2977
2978 bool intel_has_pending_fb_unpin(struct drm_device *dev)
2979 {
2980 struct intel_crtc *crtc;
2981
2982 /* Note that we don't need to be called with mode_config.lock here
2983 * as our list of CRTC objects is static for the lifetime of the
2984 * device and so cannot disappear as we iterate. Similarly, we can
2985 * happily treat the predicates as racy, atomic checks as userspace
2986 * cannot claim and pin a new fb without at least acquring the
2987 * struct_mutex and so serialising with us.
2988 */
2989 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
2990 if (atomic_read(&crtc->unpin_work_count) == 0)
2991 continue;
2992
2993 if (crtc->unpin_work)
2994 intel_wait_for_vblank(dev, crtc->pipe);
2995
2996 return true;
2997 }
2998
2999 return false;
3000 }
3001
3002 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3003 {
3004 struct drm_device *dev = crtc->dev;
3005 struct drm_i915_private *dev_priv = dev->dev_private;
3006
3007 if (crtc->fb == NULL)
3008 return;
3009
3010 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3011
3012 wait_event(dev_priv->pending_flip_queue,
3013 !intel_crtc_has_pending_flip(crtc));
3014
3015 mutex_lock(&dev->struct_mutex);
3016 intel_finish_fb(crtc->fb);
3017 mutex_unlock(&dev->struct_mutex);
3018 }
3019
3020 /* Program iCLKIP clock to the desired frequency */
3021 static void lpt_program_iclkip(struct drm_crtc *crtc)
3022 {
3023 struct drm_device *dev = crtc->dev;
3024 struct drm_i915_private *dev_priv = dev->dev_private;
3025 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3026 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3027 u32 temp;
3028
3029 mutex_lock(&dev_priv->dpio_lock);
3030
3031 /* It is necessary to ungate the pixclk gate prior to programming
3032 * the divisors, and gate it back when it is done.
3033 */
3034 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3035
3036 /* Disable SSCCTL */
3037 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3038 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3039 SBI_SSCCTL_DISABLE,
3040 SBI_ICLK);
3041
3042 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3043 if (clock == 20000) {
3044 auxdiv = 1;
3045 divsel = 0x41;
3046 phaseinc = 0x20;
3047 } else {
3048 /* The iCLK virtual clock root frequency is in MHz,
3049 * but the adjusted_mode->crtc_clock in in KHz. To get the
3050 * divisors, it is necessary to divide one by another, so we
3051 * convert the virtual clock precision to KHz here for higher
3052 * precision.
3053 */
3054 u32 iclk_virtual_root_freq = 172800 * 1000;
3055 u32 iclk_pi_range = 64;
3056 u32 desired_divisor, msb_divisor_value, pi_value;
3057
3058 desired_divisor = (iclk_virtual_root_freq / clock);
3059 msb_divisor_value = desired_divisor / iclk_pi_range;
3060 pi_value = desired_divisor % iclk_pi_range;
3061
3062 auxdiv = 0;
3063 divsel = msb_divisor_value - 2;
3064 phaseinc = pi_value;
3065 }
3066
3067 /* This should not happen with any sane values */
3068 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3069 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3070 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3071 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3072
3073 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3074 clock,
3075 auxdiv,
3076 divsel,
3077 phasedir,
3078 phaseinc);
3079
3080 /* Program SSCDIVINTPHASE6 */
3081 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3082 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3083 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3084 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3085 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3086 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3087 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3088 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3089
3090 /* Program SSCAUXDIV */
3091 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3092 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3093 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3094 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3095
3096 /* Enable modulator and associated divider */
3097 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3098 temp &= ~SBI_SSCCTL_DISABLE;
3099 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3100
3101 /* Wait for initialization time */
3102 udelay(24);
3103
3104 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3105
3106 mutex_unlock(&dev_priv->dpio_lock);
3107 }
3108
3109 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3110 enum pipe pch_transcoder)
3111 {
3112 struct drm_device *dev = crtc->base.dev;
3113 struct drm_i915_private *dev_priv = dev->dev_private;
3114 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3115
3116 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3117 I915_READ(HTOTAL(cpu_transcoder)));
3118 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3119 I915_READ(HBLANK(cpu_transcoder)));
3120 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3121 I915_READ(HSYNC(cpu_transcoder)));
3122
3123 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3124 I915_READ(VTOTAL(cpu_transcoder)));
3125 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3126 I915_READ(VBLANK(cpu_transcoder)));
3127 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3128 I915_READ(VSYNC(cpu_transcoder)));
3129 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3130 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3131 }
3132
3133 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3134 {
3135 struct drm_i915_private *dev_priv = dev->dev_private;
3136 uint32_t temp;
3137
3138 temp = I915_READ(SOUTH_CHICKEN1);
3139 if (temp & FDI_BC_BIFURCATION_SELECT)
3140 return;
3141
3142 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3143 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3144
3145 temp |= FDI_BC_BIFURCATION_SELECT;
3146 DRM_DEBUG_KMS("enabling fdi C rx\n");
3147 I915_WRITE(SOUTH_CHICKEN1, temp);
3148 POSTING_READ(SOUTH_CHICKEN1);
3149 }
3150
3151 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3152 {
3153 struct drm_device *dev = intel_crtc->base.dev;
3154 struct drm_i915_private *dev_priv = dev->dev_private;
3155
3156 switch (intel_crtc->pipe) {
3157 case PIPE_A:
3158 break;
3159 case PIPE_B:
3160 if (intel_crtc->config.fdi_lanes > 2)
3161 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3162 else
3163 cpt_enable_fdi_bc_bifurcation(dev);
3164
3165 break;
3166 case PIPE_C:
3167 cpt_enable_fdi_bc_bifurcation(dev);
3168
3169 break;
3170 default:
3171 BUG();
3172 }
3173 }
3174
3175 /*
3176 * Enable PCH resources required for PCH ports:
3177 * - PCH PLLs
3178 * - FDI training & RX/TX
3179 * - update transcoder timings
3180 * - DP transcoding bits
3181 * - transcoder
3182 */
3183 static void ironlake_pch_enable(struct drm_crtc *crtc)
3184 {
3185 struct drm_device *dev = crtc->dev;
3186 struct drm_i915_private *dev_priv = dev->dev_private;
3187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3188 int pipe = intel_crtc->pipe;
3189 u32 reg, temp;
3190
3191 assert_pch_transcoder_disabled(dev_priv, pipe);
3192
3193 if (IS_IVYBRIDGE(dev))
3194 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3195
3196 /* Write the TU size bits before fdi link training, so that error
3197 * detection works. */
3198 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3199 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3200
3201 /* For PCH output, training FDI link */
3202 dev_priv->display.fdi_link_train(crtc);
3203
3204 /* We need to program the right clock selection before writing the pixel
3205 * mutliplier into the DPLL. */
3206 if (HAS_PCH_CPT(dev)) {
3207 u32 sel;
3208
3209 temp = I915_READ(PCH_DPLL_SEL);
3210 temp |= TRANS_DPLL_ENABLE(pipe);
3211 sel = TRANS_DPLLB_SEL(pipe);
3212 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3213 temp |= sel;
3214 else
3215 temp &= ~sel;
3216 I915_WRITE(PCH_DPLL_SEL, temp);
3217 }
3218
3219 /* XXX: pch pll's can be enabled any time before we enable the PCH
3220 * transcoder, and we actually should do this to not upset any PCH
3221 * transcoder that already use the clock when we share it.
3222 *
3223 * Note that enable_shared_dpll tries to do the right thing, but
3224 * get_shared_dpll unconditionally resets the pll - we need that to have
3225 * the right LVDS enable sequence. */
3226 ironlake_enable_shared_dpll(intel_crtc);
3227
3228 /* set transcoder timing, panel must allow it */
3229 assert_panel_unlocked(dev_priv, pipe);
3230 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3231
3232 intel_fdi_normal_train(crtc);
3233
3234 /* For PCH DP, enable TRANS_DP_CTL */
3235 if (HAS_PCH_CPT(dev) &&
3236 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3237 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3238 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3239 reg = TRANS_DP_CTL(pipe);
3240 temp = I915_READ(reg);
3241 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3242 TRANS_DP_SYNC_MASK |
3243 TRANS_DP_BPC_MASK);
3244 temp |= (TRANS_DP_OUTPUT_ENABLE |
3245 TRANS_DP_ENH_FRAMING);
3246 temp |= bpc << 9; /* same format but at 11:9 */
3247
3248 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3249 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3250 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3251 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3252
3253 switch (intel_trans_dp_port_sel(crtc)) {
3254 case PCH_DP_B:
3255 temp |= TRANS_DP_PORT_SEL_B;
3256 break;
3257 case PCH_DP_C:
3258 temp |= TRANS_DP_PORT_SEL_C;
3259 break;
3260 case PCH_DP_D:
3261 temp |= TRANS_DP_PORT_SEL_D;
3262 break;
3263 default:
3264 BUG();
3265 }
3266
3267 I915_WRITE(reg, temp);
3268 }
3269
3270 ironlake_enable_pch_transcoder(dev_priv, pipe);
3271 }
3272
3273 static void lpt_pch_enable(struct drm_crtc *crtc)
3274 {
3275 struct drm_device *dev = crtc->dev;
3276 struct drm_i915_private *dev_priv = dev->dev_private;
3277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3278 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3279
3280 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3281
3282 lpt_program_iclkip(crtc);
3283
3284 /* Set transcoder timing. */
3285 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3286
3287 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3288 }
3289
3290 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3291 {
3292 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3293
3294 if (pll == NULL)
3295 return;
3296
3297 if (pll->refcount == 0) {
3298 WARN(1, "bad %s refcount\n", pll->name);
3299 return;
3300 }
3301
3302 if (--pll->refcount == 0) {
3303 WARN_ON(pll->on);
3304 WARN_ON(pll->active);
3305 }
3306
3307 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3308 }
3309
3310 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3311 {
3312 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3313 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3314 enum intel_dpll_id i;
3315
3316 if (pll) {
3317 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3318 crtc->base.base.id, pll->name);
3319 intel_put_shared_dpll(crtc);
3320 }
3321
3322 if (HAS_PCH_IBX(dev_priv->dev)) {
3323 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3324 i = (enum intel_dpll_id) crtc->pipe;
3325 pll = &dev_priv->shared_dplls[i];
3326
3327 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3328 crtc->base.base.id, pll->name);
3329
3330 goto found;
3331 }
3332
3333 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3334 pll = &dev_priv->shared_dplls[i];
3335
3336 /* Only want to check enabled timings first */
3337 if (pll->refcount == 0)
3338 continue;
3339
3340 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3341 sizeof(pll->hw_state)) == 0) {
3342 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3343 crtc->base.base.id,
3344 pll->name, pll->refcount, pll->active);
3345
3346 goto found;
3347 }
3348 }
3349
3350 /* Ok no matching timings, maybe there's a free one? */
3351 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3352 pll = &dev_priv->shared_dplls[i];
3353 if (pll->refcount == 0) {
3354 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3355 crtc->base.base.id, pll->name);
3356 goto found;
3357 }
3358 }
3359
3360 return NULL;
3361
3362 found:
3363 crtc->config.shared_dpll = i;
3364 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3365 pipe_name(crtc->pipe));
3366
3367 if (pll->active == 0) {
3368 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3369 sizeof(pll->hw_state));
3370
3371 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3372 WARN_ON(pll->on);
3373 assert_shared_dpll_disabled(dev_priv, pll);
3374
3375 pll->mode_set(dev_priv, pll);
3376 }
3377 pll->refcount++;
3378
3379 return pll;
3380 }
3381
3382 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3383 {
3384 struct drm_i915_private *dev_priv = dev->dev_private;
3385 int dslreg = PIPEDSL(pipe);
3386 u32 temp;
3387
3388 temp = I915_READ(dslreg);
3389 udelay(500);
3390 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3391 if (wait_for(I915_READ(dslreg) != temp, 5))
3392 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3393 }
3394 }
3395
3396 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3397 {
3398 struct drm_device *dev = crtc->base.dev;
3399 struct drm_i915_private *dev_priv = dev->dev_private;
3400 int pipe = crtc->pipe;
3401
3402 if (crtc->config.pch_pfit.enabled) {
3403 /* Force use of hard-coded filter coefficients
3404 * as some pre-programmed values are broken,
3405 * e.g. x201.
3406 */
3407 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3408 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3409 PF_PIPE_SEL_IVB(pipe));
3410 else
3411 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3412 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3413 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3414 }
3415 }
3416
3417 static void intel_enable_planes(struct drm_crtc *crtc)
3418 {
3419 struct drm_device *dev = crtc->dev;
3420 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3421 struct intel_plane *intel_plane;
3422
3423 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3424 if (intel_plane->pipe == pipe)
3425 intel_plane_restore(&intel_plane->base);
3426 }
3427
3428 static void intel_disable_planes(struct drm_crtc *crtc)
3429 {
3430 struct drm_device *dev = crtc->dev;
3431 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3432 struct intel_plane *intel_plane;
3433
3434 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3435 if (intel_plane->pipe == pipe)
3436 intel_plane_disable(&intel_plane->base);
3437 }
3438
3439 void hsw_enable_ips(struct intel_crtc *crtc)
3440 {
3441 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3442
3443 if (!crtc->config.ips_enabled)
3444 return;
3445
3446 /* We can only enable IPS after we enable a plane and wait for a vblank.
3447 * We guarantee that the plane is enabled by calling intel_enable_ips
3448 * only after intel_enable_plane. And intel_enable_plane already waits
3449 * for a vblank, so all we need to do here is to enable the IPS bit. */
3450 assert_plane_enabled(dev_priv, crtc->plane);
3451 if (IS_BROADWELL(crtc->base.dev)) {
3452 mutex_lock(&dev_priv->rps.hw_lock);
3453 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3454 mutex_unlock(&dev_priv->rps.hw_lock);
3455 /* Quoting Art Runyan: "its not safe to expect any particular
3456 * value in IPS_CTL bit 31 after enabling IPS through the
3457 * mailbox." Moreover, the mailbox may return a bogus state,
3458 * so we need to just enable it and continue on.
3459 */
3460 } else {
3461 I915_WRITE(IPS_CTL, IPS_ENABLE);
3462 /* The bit only becomes 1 in the next vblank, so this wait here
3463 * is essentially intel_wait_for_vblank. If we don't have this
3464 * and don't wait for vblanks until the end of crtc_enable, then
3465 * the HW state readout code will complain that the expected
3466 * IPS_CTL value is not the one we read. */
3467 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3468 DRM_ERROR("Timed out waiting for IPS enable\n");
3469 }
3470 }
3471
3472 void hsw_disable_ips(struct intel_crtc *crtc)
3473 {
3474 struct drm_device *dev = crtc->base.dev;
3475 struct drm_i915_private *dev_priv = dev->dev_private;
3476
3477 if (!crtc->config.ips_enabled)
3478 return;
3479
3480 assert_plane_enabled(dev_priv, crtc->plane);
3481 if (IS_BROADWELL(crtc->base.dev)) {
3482 mutex_lock(&dev_priv->rps.hw_lock);
3483 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3484 mutex_unlock(&dev_priv->rps.hw_lock);
3485 } else {
3486 I915_WRITE(IPS_CTL, 0);
3487 POSTING_READ(IPS_CTL);
3488 }
3489
3490 /* We need to wait for a vblank before we can disable the plane. */
3491 intel_wait_for_vblank(dev, crtc->pipe);
3492 }
3493
3494 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3495 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3496 {
3497 struct drm_device *dev = crtc->dev;
3498 struct drm_i915_private *dev_priv = dev->dev_private;
3499 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3500 enum pipe pipe = intel_crtc->pipe;
3501 int palreg = PALETTE(pipe);
3502 int i;
3503 bool reenable_ips = false;
3504
3505 /* The clocks have to be on to load the palette. */
3506 if (!crtc->enabled || !intel_crtc->active)
3507 return;
3508
3509 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3510 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3511 assert_dsi_pll_enabled(dev_priv);
3512 else
3513 assert_pll_enabled(dev_priv, pipe);
3514 }
3515
3516 /* use legacy palette for Ironlake */
3517 if (HAS_PCH_SPLIT(dev))
3518 palreg = LGC_PALETTE(pipe);
3519
3520 /* Workaround : Do not read or write the pipe palette/gamma data while
3521 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3522 */
3523 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3524 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3525 GAMMA_MODE_MODE_SPLIT)) {
3526 hsw_disable_ips(intel_crtc);
3527 reenable_ips = true;
3528 }
3529
3530 for (i = 0; i < 256; i++) {
3531 I915_WRITE(palreg + 4 * i,
3532 (intel_crtc->lut_r[i] << 16) |
3533 (intel_crtc->lut_g[i] << 8) |
3534 intel_crtc->lut_b[i]);
3535 }
3536
3537 if (reenable_ips)
3538 hsw_enable_ips(intel_crtc);
3539 }
3540
3541 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3542 {
3543 struct drm_device *dev = crtc->dev;
3544 struct drm_i915_private *dev_priv = dev->dev_private;
3545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3546 struct intel_encoder *encoder;
3547 int pipe = intel_crtc->pipe;
3548 int plane = intel_crtc->plane;
3549
3550 WARN_ON(!crtc->enabled);
3551
3552 if (intel_crtc->active)
3553 return;
3554
3555 intel_crtc->active = true;
3556
3557 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3558 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3559
3560 for_each_encoder_on_crtc(dev, crtc, encoder)
3561 if (encoder->pre_enable)
3562 encoder->pre_enable(encoder);
3563
3564 if (intel_crtc->config.has_pch_encoder) {
3565 /* Note: FDI PLL enabling _must_ be done before we enable the
3566 * cpu pipes, hence this is separate from all the other fdi/pch
3567 * enabling. */
3568 ironlake_fdi_pll_enable(intel_crtc);
3569 } else {
3570 assert_fdi_tx_disabled(dev_priv, pipe);
3571 assert_fdi_rx_disabled(dev_priv, pipe);
3572 }
3573
3574 ironlake_pfit_enable(intel_crtc);
3575
3576 /*
3577 * On ILK+ LUT must be loaded before the pipe is running but with
3578 * clocks enabled
3579 */
3580 intel_crtc_load_lut(crtc);
3581
3582 intel_update_watermarks(crtc);
3583 intel_enable_pipe(intel_crtc);
3584 intel_enable_primary_plane(dev_priv, plane, pipe);
3585 intel_enable_planes(crtc);
3586 intel_crtc_update_cursor(crtc, true);
3587
3588 if (intel_crtc->config.has_pch_encoder)
3589 ironlake_pch_enable(crtc);
3590
3591 mutex_lock(&dev->struct_mutex);
3592 intel_update_fbc(dev);
3593 mutex_unlock(&dev->struct_mutex);
3594
3595 for_each_encoder_on_crtc(dev, crtc, encoder)
3596 encoder->enable(encoder);
3597
3598 if (HAS_PCH_CPT(dev))
3599 cpt_verify_modeset(dev, intel_crtc->pipe);
3600
3601 /*
3602 * There seems to be a race in PCH platform hw (at least on some
3603 * outputs) where an enabled pipe still completes any pageflip right
3604 * away (as if the pipe is off) instead of waiting for vblank. As soon
3605 * as the first vblank happend, everything works as expected. Hence just
3606 * wait for one vblank before returning to avoid strange things
3607 * happening.
3608 */
3609 intel_wait_for_vblank(dev, intel_crtc->pipe);
3610 }
3611
3612 /* IPS only exists on ULT machines and is tied to pipe A. */
3613 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3614 {
3615 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3616 }
3617
3618 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3619 {
3620 struct drm_device *dev = crtc->dev;
3621 struct drm_i915_private *dev_priv = dev->dev_private;
3622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3623 int pipe = intel_crtc->pipe;
3624 int plane = intel_crtc->plane;
3625
3626 intel_enable_primary_plane(dev_priv, plane, pipe);
3627 intel_enable_planes(crtc);
3628 intel_crtc_update_cursor(crtc, true);
3629
3630 hsw_enable_ips(intel_crtc);
3631
3632 mutex_lock(&dev->struct_mutex);
3633 intel_update_fbc(dev);
3634 mutex_unlock(&dev->struct_mutex);
3635 }
3636
3637 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3638 {
3639 struct drm_device *dev = crtc->dev;
3640 struct drm_i915_private *dev_priv = dev->dev_private;
3641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3642 int pipe = intel_crtc->pipe;
3643 int plane = intel_crtc->plane;
3644
3645 intel_crtc_wait_for_pending_flips(crtc);
3646 drm_vblank_off(dev, pipe);
3647
3648 /* FBC must be disabled before disabling the plane on HSW. */
3649 if (dev_priv->fbc.plane == plane)
3650 intel_disable_fbc(dev);
3651
3652 hsw_disable_ips(intel_crtc);
3653
3654 intel_crtc_update_cursor(crtc, false);
3655 intel_disable_planes(crtc);
3656 intel_disable_primary_plane(dev_priv, plane, pipe);
3657 }
3658
3659 /*
3660 * This implements the workaround described in the "notes" section of the mode
3661 * set sequence documentation. When going from no pipes or single pipe to
3662 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3663 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3664 */
3665 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3666 {
3667 struct drm_device *dev = crtc->base.dev;
3668 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3669
3670 /* We want to get the other_active_crtc only if there's only 1 other
3671 * active crtc. */
3672 list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3673 if (!crtc_it->active || crtc_it == crtc)
3674 continue;
3675
3676 if (other_active_crtc)
3677 return;
3678
3679 other_active_crtc = crtc_it;
3680 }
3681 if (!other_active_crtc)
3682 return;
3683
3684 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3685 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3686 }
3687
3688 static void haswell_crtc_enable(struct drm_crtc *crtc)
3689 {
3690 struct drm_device *dev = crtc->dev;
3691 struct drm_i915_private *dev_priv = dev->dev_private;
3692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3693 struct intel_encoder *encoder;
3694 int pipe = intel_crtc->pipe;
3695
3696 WARN_ON(!crtc->enabled);
3697
3698 if (intel_crtc->active)
3699 return;
3700
3701 intel_crtc->active = true;
3702
3703 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3704 if (intel_crtc->config.has_pch_encoder)
3705 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3706
3707 if (intel_crtc->config.has_pch_encoder)
3708 dev_priv->display.fdi_link_train(crtc);
3709
3710 for_each_encoder_on_crtc(dev, crtc, encoder)
3711 if (encoder->pre_enable)
3712 encoder->pre_enable(encoder);
3713
3714 intel_ddi_enable_pipe_clock(intel_crtc);
3715
3716 ironlake_pfit_enable(intel_crtc);
3717
3718 /*
3719 * On ILK+ LUT must be loaded before the pipe is running but with
3720 * clocks enabled
3721 */
3722 intel_crtc_load_lut(crtc);
3723
3724 intel_ddi_set_pipe_settings(crtc);
3725 intel_ddi_enable_transcoder_func(crtc);
3726
3727 intel_update_watermarks(crtc);
3728 intel_enable_pipe(intel_crtc);
3729
3730 if (intel_crtc->config.has_pch_encoder)
3731 lpt_pch_enable(crtc);
3732
3733 for_each_encoder_on_crtc(dev, crtc, encoder) {
3734 encoder->enable(encoder);
3735 intel_opregion_notify_encoder(encoder, true);
3736 }
3737
3738 /* If we change the relative order between pipe/planes enabling, we need
3739 * to change the workaround. */
3740 haswell_mode_set_planes_workaround(intel_crtc);
3741 haswell_crtc_enable_planes(crtc);
3742 }
3743
3744 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3745 {
3746 struct drm_device *dev = crtc->base.dev;
3747 struct drm_i915_private *dev_priv = dev->dev_private;
3748 int pipe = crtc->pipe;
3749
3750 /* To avoid upsetting the power well on haswell only disable the pfit if
3751 * it's in use. The hw state code will make sure we get this right. */
3752 if (crtc->config.pch_pfit.enabled) {
3753 I915_WRITE(PF_CTL(pipe), 0);
3754 I915_WRITE(PF_WIN_POS(pipe), 0);
3755 I915_WRITE(PF_WIN_SZ(pipe), 0);
3756 }
3757 }
3758
3759 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3760 {
3761 struct drm_device *dev = crtc->dev;
3762 struct drm_i915_private *dev_priv = dev->dev_private;
3763 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3764 struct intel_encoder *encoder;
3765 int pipe = intel_crtc->pipe;
3766 int plane = intel_crtc->plane;
3767 u32 reg, temp;
3768
3769
3770 if (!intel_crtc->active)
3771 return;
3772
3773 for_each_encoder_on_crtc(dev, crtc, encoder)
3774 encoder->disable(encoder);
3775
3776 intel_crtc_wait_for_pending_flips(crtc);
3777 drm_vblank_off(dev, pipe);
3778
3779 if (dev_priv->fbc.plane == plane)
3780 intel_disable_fbc(dev);
3781
3782 intel_crtc_update_cursor(crtc, false);
3783 intel_disable_planes(crtc);
3784 intel_disable_primary_plane(dev_priv, plane, pipe);
3785
3786 if (intel_crtc->config.has_pch_encoder)
3787 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3788
3789 intel_disable_pipe(dev_priv, pipe);
3790
3791 ironlake_pfit_disable(intel_crtc);
3792
3793 for_each_encoder_on_crtc(dev, crtc, encoder)
3794 if (encoder->post_disable)
3795 encoder->post_disable(encoder);
3796
3797 if (intel_crtc->config.has_pch_encoder) {
3798 ironlake_fdi_disable(crtc);
3799
3800 ironlake_disable_pch_transcoder(dev_priv, pipe);
3801 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3802
3803 if (HAS_PCH_CPT(dev)) {
3804 /* disable TRANS_DP_CTL */
3805 reg = TRANS_DP_CTL(pipe);
3806 temp = I915_READ(reg);
3807 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3808 TRANS_DP_PORT_SEL_MASK);
3809 temp |= TRANS_DP_PORT_SEL_NONE;
3810 I915_WRITE(reg, temp);
3811
3812 /* disable DPLL_SEL */
3813 temp = I915_READ(PCH_DPLL_SEL);
3814 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3815 I915_WRITE(PCH_DPLL_SEL, temp);
3816 }
3817
3818 /* disable PCH DPLL */
3819 intel_disable_shared_dpll(intel_crtc);
3820
3821 ironlake_fdi_pll_disable(intel_crtc);
3822 }
3823
3824 intel_crtc->active = false;
3825 intel_update_watermarks(crtc);
3826
3827 mutex_lock(&dev->struct_mutex);
3828 intel_update_fbc(dev);
3829 mutex_unlock(&dev->struct_mutex);
3830 }
3831
3832 static void haswell_crtc_disable(struct drm_crtc *crtc)
3833 {
3834 struct drm_device *dev = crtc->dev;
3835 struct drm_i915_private *dev_priv = dev->dev_private;
3836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3837 struct intel_encoder *encoder;
3838 int pipe = intel_crtc->pipe;
3839 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3840
3841 if (!intel_crtc->active)
3842 return;
3843
3844 haswell_crtc_disable_planes(crtc);
3845
3846 for_each_encoder_on_crtc(dev, crtc, encoder) {
3847 intel_opregion_notify_encoder(encoder, false);
3848 encoder->disable(encoder);
3849 }
3850
3851 if (intel_crtc->config.has_pch_encoder)
3852 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3853 intel_disable_pipe(dev_priv, pipe);
3854
3855 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3856
3857 ironlake_pfit_disable(intel_crtc);
3858
3859 intel_ddi_disable_pipe_clock(intel_crtc);
3860
3861 for_each_encoder_on_crtc(dev, crtc, encoder)
3862 if (encoder->post_disable)
3863 encoder->post_disable(encoder);
3864
3865 if (intel_crtc->config.has_pch_encoder) {
3866 lpt_disable_pch_transcoder(dev_priv);
3867 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3868 intel_ddi_fdi_disable(crtc);
3869 }
3870
3871 intel_crtc->active = false;
3872 intel_update_watermarks(crtc);
3873
3874 mutex_lock(&dev->struct_mutex);
3875 intel_update_fbc(dev);
3876 mutex_unlock(&dev->struct_mutex);
3877 }
3878
3879 static void ironlake_crtc_off(struct drm_crtc *crtc)
3880 {
3881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3882 intel_put_shared_dpll(intel_crtc);
3883 }
3884
3885 static void haswell_crtc_off(struct drm_crtc *crtc)
3886 {
3887 intel_ddi_put_crtc_pll(crtc);
3888 }
3889
3890 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3891 {
3892 if (!enable && intel_crtc->overlay) {
3893 struct drm_device *dev = intel_crtc->base.dev;
3894 struct drm_i915_private *dev_priv = dev->dev_private;
3895
3896 mutex_lock(&dev->struct_mutex);
3897 dev_priv->mm.interruptible = false;
3898 (void) intel_overlay_switch_off(intel_crtc->overlay);
3899 dev_priv->mm.interruptible = true;
3900 mutex_unlock(&dev->struct_mutex);
3901 }
3902
3903 /* Let userspace switch the overlay on again. In most cases userspace
3904 * has to recompute where to put it anyway.
3905 */
3906 }
3907
3908 /**
3909 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3910 * cursor plane briefly if not already running after enabling the display
3911 * plane.
3912 * This workaround avoids occasional blank screens when self refresh is
3913 * enabled.
3914 */
3915 static void
3916 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3917 {
3918 u32 cntl = I915_READ(CURCNTR(pipe));
3919
3920 if ((cntl & CURSOR_MODE) == 0) {
3921 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3922
3923 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3924 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3925 intel_wait_for_vblank(dev_priv->dev, pipe);
3926 I915_WRITE(CURCNTR(pipe), cntl);
3927 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3928 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3929 }
3930 }
3931
3932 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3933 {
3934 struct drm_device *dev = crtc->base.dev;
3935 struct drm_i915_private *dev_priv = dev->dev_private;
3936 struct intel_crtc_config *pipe_config = &crtc->config;
3937
3938 if (!crtc->config.gmch_pfit.control)
3939 return;
3940
3941 /*
3942 * The panel fitter should only be adjusted whilst the pipe is disabled,
3943 * according to register description and PRM.
3944 */
3945 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3946 assert_pipe_disabled(dev_priv, crtc->pipe);
3947
3948 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3949 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3950
3951 /* Border color in case we don't scale up to the full screen. Black by
3952 * default, change to something else for debugging. */
3953 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3954 }
3955
3956 int valleyview_get_vco(struct drm_i915_private *dev_priv)
3957 {
3958 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
3959
3960 /* Obtain SKU information */
3961 mutex_lock(&dev_priv->dpio_lock);
3962 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
3963 CCK_FUSE_HPLL_FREQ_MASK;
3964 mutex_unlock(&dev_priv->dpio_lock);
3965
3966 return vco_freq[hpll_freq];
3967 }
3968
3969 /* Adjust CDclk dividers to allow high res or save power if possible */
3970 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
3971 {
3972 struct drm_i915_private *dev_priv = dev->dev_private;
3973 u32 val, cmd;
3974
3975 if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
3976 cmd = 2;
3977 else if (cdclk == 266)
3978 cmd = 1;
3979 else
3980 cmd = 0;
3981
3982 mutex_lock(&dev_priv->rps.hw_lock);
3983 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3984 val &= ~DSPFREQGUAR_MASK;
3985 val |= (cmd << DSPFREQGUAR_SHIFT);
3986 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
3987 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
3988 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
3989 50)) {
3990 DRM_ERROR("timed out waiting for CDclk change\n");
3991 }
3992 mutex_unlock(&dev_priv->rps.hw_lock);
3993
3994 if (cdclk == 400) {
3995 u32 divider, vco;
3996
3997 vco = valleyview_get_vco(dev_priv);
3998 divider = ((vco << 1) / cdclk) - 1;
3999
4000 mutex_lock(&dev_priv->dpio_lock);
4001 /* adjust cdclk divider */
4002 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4003 val &= ~0xf;
4004 val |= divider;
4005 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4006 mutex_unlock(&dev_priv->dpio_lock);
4007 }
4008
4009 mutex_lock(&dev_priv->dpio_lock);
4010 /* adjust self-refresh exit latency value */
4011 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4012 val &= ~0x7f;
4013
4014 /*
4015 * For high bandwidth configs, we set a higher latency in the bunit
4016 * so that the core display fetch happens in time to avoid underruns.
4017 */
4018 if (cdclk == 400)
4019 val |= 4500 / 250; /* 4.5 usec */
4020 else
4021 val |= 3000 / 250; /* 3.0 usec */
4022 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4023 mutex_unlock(&dev_priv->dpio_lock);
4024
4025 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4026 intel_i2c_reset(dev);
4027 }
4028
4029 static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4030 {
4031 int cur_cdclk, vco;
4032 int divider;
4033
4034 vco = valleyview_get_vco(dev_priv);
4035
4036 mutex_lock(&dev_priv->dpio_lock);
4037 divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4038 mutex_unlock(&dev_priv->dpio_lock);
4039
4040 divider &= 0xf;
4041
4042 cur_cdclk = (vco << 1) / (divider + 1);
4043
4044 return cur_cdclk;
4045 }
4046
4047 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4048 int max_pixclk)
4049 {
4050 int cur_cdclk;
4051
4052 cur_cdclk = valleyview_cur_cdclk(dev_priv);
4053
4054 /*
4055 * Really only a few cases to deal with, as only 4 CDclks are supported:
4056 * 200MHz
4057 * 267MHz
4058 * 320MHz
4059 * 400MHz
4060 * So we check to see whether we're above 90% of the lower bin and
4061 * adjust if needed.
4062 */
4063 if (max_pixclk > 288000) {
4064 return 400;
4065 } else if (max_pixclk > 240000) {
4066 return 320;
4067 } else
4068 return 266;
4069 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4070 }
4071
4072 /* compute the max pixel clock for new configuration */
4073 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4074 {
4075 struct drm_device *dev = dev_priv->dev;
4076 struct intel_crtc *intel_crtc;
4077 int max_pixclk = 0;
4078
4079 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4080 base.head) {
4081 if (intel_crtc->new_enabled)
4082 max_pixclk = max(max_pixclk,
4083 intel_crtc->new_config->adjusted_mode.crtc_clock);
4084 }
4085
4086 return max_pixclk;
4087 }
4088
4089 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4090 unsigned *prepare_pipes)
4091 {
4092 struct drm_i915_private *dev_priv = dev->dev_private;
4093 struct intel_crtc *intel_crtc;
4094 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4095 int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4096
4097 if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk)
4098 return;
4099
4100 /* disable/enable all currently active pipes while we change cdclk */
4101 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4102 base.head)
4103 if (intel_crtc->base.enabled)
4104 *prepare_pipes |= (1 << intel_crtc->pipe);
4105 }
4106
4107 static void valleyview_modeset_global_resources(struct drm_device *dev)
4108 {
4109 struct drm_i915_private *dev_priv = dev->dev_private;
4110 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4111 int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4112 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4113
4114 if (req_cdclk != cur_cdclk)
4115 valleyview_set_cdclk(dev, req_cdclk);
4116 }
4117
4118 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4119 {
4120 struct drm_device *dev = crtc->dev;
4121 struct drm_i915_private *dev_priv = dev->dev_private;
4122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4123 struct intel_encoder *encoder;
4124 int pipe = intel_crtc->pipe;
4125 int plane = intel_crtc->plane;
4126 bool is_dsi;
4127
4128 WARN_ON(!crtc->enabled);
4129
4130 if (intel_crtc->active)
4131 return;
4132
4133 intel_crtc->active = true;
4134
4135 for_each_encoder_on_crtc(dev, crtc, encoder)
4136 if (encoder->pre_pll_enable)
4137 encoder->pre_pll_enable(encoder);
4138
4139 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4140
4141 if (!is_dsi)
4142 vlv_enable_pll(intel_crtc);
4143
4144 for_each_encoder_on_crtc(dev, crtc, encoder)
4145 if (encoder->pre_enable)
4146 encoder->pre_enable(encoder);
4147
4148 i9xx_pfit_enable(intel_crtc);
4149
4150 intel_crtc_load_lut(crtc);
4151
4152 intel_update_watermarks(crtc);
4153 intel_enable_pipe(intel_crtc);
4154 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4155 intel_enable_primary_plane(dev_priv, plane, pipe);
4156 intel_enable_planes(crtc);
4157 intel_crtc_update_cursor(crtc, true);
4158
4159 intel_update_fbc(dev);
4160
4161 for_each_encoder_on_crtc(dev, crtc, encoder)
4162 encoder->enable(encoder);
4163 }
4164
4165 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4166 {
4167 struct drm_device *dev = crtc->dev;
4168 struct drm_i915_private *dev_priv = dev->dev_private;
4169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4170 struct intel_encoder *encoder;
4171 int pipe = intel_crtc->pipe;
4172 int plane = intel_crtc->plane;
4173
4174 WARN_ON(!crtc->enabled);
4175
4176 if (intel_crtc->active)
4177 return;
4178
4179 intel_crtc->active = true;
4180
4181 for_each_encoder_on_crtc(dev, crtc, encoder)
4182 if (encoder->pre_enable)
4183 encoder->pre_enable(encoder);
4184
4185 i9xx_enable_pll(intel_crtc);
4186
4187 i9xx_pfit_enable(intel_crtc);
4188
4189 intel_crtc_load_lut(crtc);
4190
4191 intel_update_watermarks(crtc);
4192 intel_enable_pipe(intel_crtc);
4193 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4194 intel_enable_primary_plane(dev_priv, plane, pipe);
4195 intel_enable_planes(crtc);
4196 /* The fixup needs to happen before cursor is enabled */
4197 if (IS_G4X(dev))
4198 g4x_fixup_plane(dev_priv, pipe);
4199 intel_crtc_update_cursor(crtc, true);
4200
4201 /* Give the overlay scaler a chance to enable if it's on this pipe */
4202 intel_crtc_dpms_overlay(intel_crtc, true);
4203
4204 intel_update_fbc(dev);
4205
4206 for_each_encoder_on_crtc(dev, crtc, encoder)
4207 encoder->enable(encoder);
4208 }
4209
4210 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4211 {
4212 struct drm_device *dev = crtc->base.dev;
4213 struct drm_i915_private *dev_priv = dev->dev_private;
4214
4215 if (!crtc->config.gmch_pfit.control)
4216 return;
4217
4218 assert_pipe_disabled(dev_priv, crtc->pipe);
4219
4220 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4221 I915_READ(PFIT_CONTROL));
4222 I915_WRITE(PFIT_CONTROL, 0);
4223 }
4224
4225 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4226 {
4227 struct drm_device *dev = crtc->dev;
4228 struct drm_i915_private *dev_priv = dev->dev_private;
4229 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4230 struct intel_encoder *encoder;
4231 int pipe = intel_crtc->pipe;
4232 int plane = intel_crtc->plane;
4233
4234 if (!intel_crtc->active)
4235 return;
4236
4237 for_each_encoder_on_crtc(dev, crtc, encoder)
4238 encoder->disable(encoder);
4239
4240 /* Give the overlay scaler a chance to disable if it's on this pipe */
4241 intel_crtc_wait_for_pending_flips(crtc);
4242 drm_vblank_off(dev, pipe);
4243
4244 if (dev_priv->fbc.plane == plane)
4245 intel_disable_fbc(dev);
4246
4247 intel_crtc_dpms_overlay(intel_crtc, false);
4248 intel_crtc_update_cursor(crtc, false);
4249 intel_disable_planes(crtc);
4250 intel_disable_primary_plane(dev_priv, plane, pipe);
4251
4252 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4253 intel_disable_pipe(dev_priv, pipe);
4254
4255 i9xx_pfit_disable(intel_crtc);
4256
4257 for_each_encoder_on_crtc(dev, crtc, encoder)
4258 if (encoder->post_disable)
4259 encoder->post_disable(encoder);
4260
4261 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4262 vlv_disable_pll(dev_priv, pipe);
4263 else if (!IS_VALLEYVIEW(dev))
4264 i9xx_disable_pll(dev_priv, pipe);
4265
4266 intel_crtc->active = false;
4267 intel_update_watermarks(crtc);
4268
4269 intel_update_fbc(dev);
4270 }
4271
4272 static void i9xx_crtc_off(struct drm_crtc *crtc)
4273 {
4274 }
4275
4276 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4277 bool enabled)
4278 {
4279 struct drm_device *dev = crtc->dev;
4280 struct drm_i915_master_private *master_priv;
4281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4282 int pipe = intel_crtc->pipe;
4283
4284 if (!dev->primary->master)
4285 return;
4286
4287 master_priv = dev->primary->master->driver_priv;
4288 if (!master_priv->sarea_priv)
4289 return;
4290
4291 switch (pipe) {
4292 case 0:
4293 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4294 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4295 break;
4296 case 1:
4297 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4298 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4299 break;
4300 default:
4301 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4302 break;
4303 }
4304 }
4305
4306 /**
4307 * Sets the power management mode of the pipe and plane.
4308 */
4309 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4310 {
4311 struct drm_device *dev = crtc->dev;
4312 struct drm_i915_private *dev_priv = dev->dev_private;
4313 struct intel_encoder *intel_encoder;
4314 bool enable = false;
4315
4316 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4317 enable |= intel_encoder->connectors_active;
4318
4319 if (enable)
4320 dev_priv->display.crtc_enable(crtc);
4321 else
4322 dev_priv->display.crtc_disable(crtc);
4323
4324 intel_crtc_update_sarea(crtc, enable);
4325 }
4326
4327 static void intel_crtc_disable(struct drm_crtc *crtc)
4328 {
4329 struct drm_device *dev = crtc->dev;
4330 struct drm_connector *connector;
4331 struct drm_i915_private *dev_priv = dev->dev_private;
4332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4333
4334 /* crtc should still be enabled when we disable it. */
4335 WARN_ON(!crtc->enabled);
4336
4337 dev_priv->display.crtc_disable(crtc);
4338 intel_crtc->eld_vld = false;
4339 intel_crtc_update_sarea(crtc, false);
4340 dev_priv->display.off(crtc);
4341
4342 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4343 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4344 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4345
4346 if (crtc->fb) {
4347 mutex_lock(&dev->struct_mutex);
4348 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4349 mutex_unlock(&dev->struct_mutex);
4350 crtc->fb = NULL;
4351 }
4352
4353 /* Update computed state. */
4354 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4355 if (!connector->encoder || !connector->encoder->crtc)
4356 continue;
4357
4358 if (connector->encoder->crtc != crtc)
4359 continue;
4360
4361 connector->dpms = DRM_MODE_DPMS_OFF;
4362 to_intel_encoder(connector->encoder)->connectors_active = false;
4363 }
4364 }
4365
4366 void intel_encoder_destroy(struct drm_encoder *encoder)
4367 {
4368 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4369
4370 drm_encoder_cleanup(encoder);
4371 kfree(intel_encoder);
4372 }
4373
4374 /* Simple dpms helper for encoders with just one connector, no cloning and only
4375 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4376 * state of the entire output pipe. */
4377 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4378 {
4379 if (mode == DRM_MODE_DPMS_ON) {
4380 encoder->connectors_active = true;
4381
4382 intel_crtc_update_dpms(encoder->base.crtc);
4383 } else {
4384 encoder->connectors_active = false;
4385
4386 intel_crtc_update_dpms(encoder->base.crtc);
4387 }
4388 }
4389
4390 /* Cross check the actual hw state with our own modeset state tracking (and it's
4391 * internal consistency). */
4392 static void intel_connector_check_state(struct intel_connector *connector)
4393 {
4394 if (connector->get_hw_state(connector)) {
4395 struct intel_encoder *encoder = connector->encoder;
4396 struct drm_crtc *crtc;
4397 bool encoder_enabled;
4398 enum pipe pipe;
4399
4400 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4401 connector->base.base.id,
4402 drm_get_connector_name(&connector->base));
4403
4404 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4405 "wrong connector dpms state\n");
4406 WARN(connector->base.encoder != &encoder->base,
4407 "active connector not linked to encoder\n");
4408 WARN(!encoder->connectors_active,
4409 "encoder->connectors_active not set\n");
4410
4411 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4412 WARN(!encoder_enabled, "encoder not enabled\n");
4413 if (WARN_ON(!encoder->base.crtc))
4414 return;
4415
4416 crtc = encoder->base.crtc;
4417
4418 WARN(!crtc->enabled, "crtc not enabled\n");
4419 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4420 WARN(pipe != to_intel_crtc(crtc)->pipe,
4421 "encoder active on the wrong pipe\n");
4422 }
4423 }
4424
4425 /* Even simpler default implementation, if there's really no special case to
4426 * consider. */
4427 void intel_connector_dpms(struct drm_connector *connector, int mode)
4428 {
4429 /* All the simple cases only support two dpms states. */
4430 if (mode != DRM_MODE_DPMS_ON)
4431 mode = DRM_MODE_DPMS_OFF;
4432
4433 if (mode == connector->dpms)
4434 return;
4435
4436 connector->dpms = mode;
4437
4438 /* Only need to change hw state when actually enabled */
4439 if (connector->encoder)
4440 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4441
4442 intel_modeset_check_state(connector->dev);
4443 }
4444
4445 /* Simple connector->get_hw_state implementation for encoders that support only
4446 * one connector and no cloning and hence the encoder state determines the state
4447 * of the connector. */
4448 bool intel_connector_get_hw_state(struct intel_connector *connector)
4449 {
4450 enum pipe pipe = 0;
4451 struct intel_encoder *encoder = connector->encoder;
4452
4453 return encoder->get_hw_state(encoder, &pipe);
4454 }
4455
4456 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4457 struct intel_crtc_config *pipe_config)
4458 {
4459 struct drm_i915_private *dev_priv = dev->dev_private;
4460 struct intel_crtc *pipe_B_crtc =
4461 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4462
4463 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4464 pipe_name(pipe), pipe_config->fdi_lanes);
4465 if (pipe_config->fdi_lanes > 4) {
4466 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4467 pipe_name(pipe), pipe_config->fdi_lanes);
4468 return false;
4469 }
4470
4471 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4472 if (pipe_config->fdi_lanes > 2) {
4473 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4474 pipe_config->fdi_lanes);
4475 return false;
4476 } else {
4477 return true;
4478 }
4479 }
4480
4481 if (INTEL_INFO(dev)->num_pipes == 2)
4482 return true;
4483
4484 /* Ivybridge 3 pipe is really complicated */
4485 switch (pipe) {
4486 case PIPE_A:
4487 return true;
4488 case PIPE_B:
4489 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4490 pipe_config->fdi_lanes > 2) {
4491 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4492 pipe_name(pipe), pipe_config->fdi_lanes);
4493 return false;
4494 }
4495 return true;
4496 case PIPE_C:
4497 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4498 pipe_B_crtc->config.fdi_lanes <= 2) {
4499 if (pipe_config->fdi_lanes > 2) {
4500 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4501 pipe_name(pipe), pipe_config->fdi_lanes);
4502 return false;
4503 }
4504 } else {
4505 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4506 return false;
4507 }
4508 return true;
4509 default:
4510 BUG();
4511 }
4512 }
4513
4514 #define RETRY 1
4515 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4516 struct intel_crtc_config *pipe_config)
4517 {
4518 struct drm_device *dev = intel_crtc->base.dev;
4519 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4520 int lane, link_bw, fdi_dotclock;
4521 bool setup_ok, needs_recompute = false;
4522
4523 retry:
4524 /* FDI is a binary signal running at ~2.7GHz, encoding
4525 * each output octet as 10 bits. The actual frequency
4526 * is stored as a divider into a 100MHz clock, and the
4527 * mode pixel clock is stored in units of 1KHz.
4528 * Hence the bw of each lane in terms of the mode signal
4529 * is:
4530 */
4531 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4532
4533 fdi_dotclock = adjusted_mode->crtc_clock;
4534
4535 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4536 pipe_config->pipe_bpp);
4537
4538 pipe_config->fdi_lanes = lane;
4539
4540 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4541 link_bw, &pipe_config->fdi_m_n);
4542
4543 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4544 intel_crtc->pipe, pipe_config);
4545 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4546 pipe_config->pipe_bpp -= 2*3;
4547 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4548 pipe_config->pipe_bpp);
4549 needs_recompute = true;
4550 pipe_config->bw_constrained = true;
4551
4552 goto retry;
4553 }
4554
4555 if (needs_recompute)
4556 return RETRY;
4557
4558 return setup_ok ? 0 : -EINVAL;
4559 }
4560
4561 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4562 struct intel_crtc_config *pipe_config)
4563 {
4564 pipe_config->ips_enabled = i915.enable_ips &&
4565 hsw_crtc_supports_ips(crtc) &&
4566 pipe_config->pipe_bpp <= 24;
4567 }
4568
4569 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4570 struct intel_crtc_config *pipe_config)
4571 {
4572 struct drm_device *dev = crtc->base.dev;
4573 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4574
4575 /* FIXME should check pixel clock limits on all platforms */
4576 if (INTEL_INFO(dev)->gen < 4) {
4577 struct drm_i915_private *dev_priv = dev->dev_private;
4578 int clock_limit =
4579 dev_priv->display.get_display_clock_speed(dev);
4580
4581 /*
4582 * Enable pixel doubling when the dot clock
4583 * is > 90% of the (display) core speed.
4584 *
4585 * GDG double wide on either pipe,
4586 * otherwise pipe A only.
4587 */
4588 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4589 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4590 clock_limit *= 2;
4591 pipe_config->double_wide = true;
4592 }
4593
4594 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4595 return -EINVAL;
4596 }
4597
4598 /*
4599 * Pipe horizontal size must be even in:
4600 * - DVO ganged mode
4601 * - LVDS dual channel mode
4602 * - Double wide pipe
4603 */
4604 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4605 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4606 pipe_config->pipe_src_w &= ~1;
4607
4608 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4609 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4610 */
4611 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4612 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4613 return -EINVAL;
4614
4615 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4616 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4617 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4618 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4619 * for lvds. */
4620 pipe_config->pipe_bpp = 8*3;
4621 }
4622
4623 if (HAS_IPS(dev))
4624 hsw_compute_ips_config(crtc, pipe_config);
4625
4626 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4627 * clock survives for now. */
4628 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4629 pipe_config->shared_dpll = crtc->config.shared_dpll;
4630
4631 if (pipe_config->has_pch_encoder)
4632 return ironlake_fdi_compute_config(crtc, pipe_config);
4633
4634 return 0;
4635 }
4636
4637 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4638 {
4639 return 400000; /* FIXME */
4640 }
4641
4642 static int i945_get_display_clock_speed(struct drm_device *dev)
4643 {
4644 return 400000;
4645 }
4646
4647 static int i915_get_display_clock_speed(struct drm_device *dev)
4648 {
4649 return 333000;
4650 }
4651
4652 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4653 {
4654 return 200000;
4655 }
4656
4657 static int pnv_get_display_clock_speed(struct drm_device *dev)
4658 {
4659 u16 gcfgc = 0;
4660
4661 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4662
4663 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4664 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4665 return 267000;
4666 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4667 return 333000;
4668 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4669 return 444000;
4670 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4671 return 200000;
4672 default:
4673 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4674 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4675 return 133000;
4676 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4677 return 167000;
4678 }
4679 }
4680
4681 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4682 {
4683 u16 gcfgc = 0;
4684
4685 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4686
4687 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4688 return 133000;
4689 else {
4690 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4691 case GC_DISPLAY_CLOCK_333_MHZ:
4692 return 333000;
4693 default:
4694 case GC_DISPLAY_CLOCK_190_200_MHZ:
4695 return 190000;
4696 }
4697 }
4698 }
4699
4700 static int i865_get_display_clock_speed(struct drm_device *dev)
4701 {
4702 return 266000;
4703 }
4704
4705 static int i855_get_display_clock_speed(struct drm_device *dev)
4706 {
4707 u16 hpllcc = 0;
4708 /* Assume that the hardware is in the high speed state. This
4709 * should be the default.
4710 */
4711 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4712 case GC_CLOCK_133_200:
4713 case GC_CLOCK_100_200:
4714 return 200000;
4715 case GC_CLOCK_166_250:
4716 return 250000;
4717 case GC_CLOCK_100_133:
4718 return 133000;
4719 }
4720
4721 /* Shouldn't happen */
4722 return 0;
4723 }
4724
4725 static int i830_get_display_clock_speed(struct drm_device *dev)
4726 {
4727 return 133000;
4728 }
4729
4730 static void
4731 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4732 {
4733 while (*num > DATA_LINK_M_N_MASK ||
4734 *den > DATA_LINK_M_N_MASK) {
4735 *num >>= 1;
4736 *den >>= 1;
4737 }
4738 }
4739
4740 static void compute_m_n(unsigned int m, unsigned int n,
4741 uint32_t *ret_m, uint32_t *ret_n)
4742 {
4743 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4744 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4745 intel_reduce_m_n_ratio(ret_m, ret_n);
4746 }
4747
4748 void
4749 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4750 int pixel_clock, int link_clock,
4751 struct intel_link_m_n *m_n)
4752 {
4753 m_n->tu = 64;
4754
4755 compute_m_n(bits_per_pixel * pixel_clock,
4756 link_clock * nlanes * 8,
4757 &m_n->gmch_m, &m_n->gmch_n);
4758
4759 compute_m_n(pixel_clock, link_clock,
4760 &m_n->link_m, &m_n->link_n);
4761 }
4762
4763 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4764 {
4765 if (i915.panel_use_ssc >= 0)
4766 return i915.panel_use_ssc != 0;
4767 return dev_priv->vbt.lvds_use_ssc
4768 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4769 }
4770
4771 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4772 {
4773 struct drm_device *dev = crtc->dev;
4774 struct drm_i915_private *dev_priv = dev->dev_private;
4775 int refclk;
4776
4777 if (IS_VALLEYVIEW(dev)) {
4778 refclk = 100000;
4779 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4780 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4781 refclk = dev_priv->vbt.lvds_ssc_freq;
4782 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
4783 } else if (!IS_GEN2(dev)) {
4784 refclk = 96000;
4785 } else {
4786 refclk = 48000;
4787 }
4788
4789 return refclk;
4790 }
4791
4792 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4793 {
4794 return (1 << dpll->n) << 16 | dpll->m2;
4795 }
4796
4797 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4798 {
4799 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4800 }
4801
4802 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4803 intel_clock_t *reduced_clock)
4804 {
4805 struct drm_device *dev = crtc->base.dev;
4806 struct drm_i915_private *dev_priv = dev->dev_private;
4807 int pipe = crtc->pipe;
4808 u32 fp, fp2 = 0;
4809
4810 if (IS_PINEVIEW(dev)) {
4811 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4812 if (reduced_clock)
4813 fp2 = pnv_dpll_compute_fp(reduced_clock);
4814 } else {
4815 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4816 if (reduced_clock)
4817 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4818 }
4819
4820 I915_WRITE(FP0(pipe), fp);
4821 crtc->config.dpll_hw_state.fp0 = fp;
4822
4823 crtc->lowfreq_avail = false;
4824 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4825 reduced_clock && i915.powersave) {
4826 I915_WRITE(FP1(pipe), fp2);
4827 crtc->config.dpll_hw_state.fp1 = fp2;
4828 crtc->lowfreq_avail = true;
4829 } else {
4830 I915_WRITE(FP1(pipe), fp);
4831 crtc->config.dpll_hw_state.fp1 = fp;
4832 }
4833 }
4834
4835 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4836 pipe)
4837 {
4838 u32 reg_val;
4839
4840 /*
4841 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4842 * and set it to a reasonable value instead.
4843 */
4844 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4845 reg_val &= 0xffffff00;
4846 reg_val |= 0x00000030;
4847 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4848
4849 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4850 reg_val &= 0x8cffffff;
4851 reg_val = 0x8c000000;
4852 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4853
4854 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4855 reg_val &= 0xffffff00;
4856 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4857
4858 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4859 reg_val &= 0x00ffffff;
4860 reg_val |= 0xb0000000;
4861 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4862 }
4863
4864 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4865 struct intel_link_m_n *m_n)
4866 {
4867 struct drm_device *dev = crtc->base.dev;
4868 struct drm_i915_private *dev_priv = dev->dev_private;
4869 int pipe = crtc->pipe;
4870
4871 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4872 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4873 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4874 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4875 }
4876
4877 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4878 struct intel_link_m_n *m_n)
4879 {
4880 struct drm_device *dev = crtc->base.dev;
4881 struct drm_i915_private *dev_priv = dev->dev_private;
4882 int pipe = crtc->pipe;
4883 enum transcoder transcoder = crtc->config.cpu_transcoder;
4884
4885 if (INTEL_INFO(dev)->gen >= 5) {
4886 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4887 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4888 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4889 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4890 } else {
4891 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4892 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4893 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4894 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4895 }
4896 }
4897
4898 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4899 {
4900 if (crtc->config.has_pch_encoder)
4901 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4902 else
4903 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4904 }
4905
4906 static void vlv_update_pll(struct intel_crtc *crtc)
4907 {
4908 struct drm_device *dev = crtc->base.dev;
4909 struct drm_i915_private *dev_priv = dev->dev_private;
4910 int pipe = crtc->pipe;
4911 u32 dpll, mdiv;
4912 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4913 u32 coreclk, reg_val, dpll_md;
4914
4915 mutex_lock(&dev_priv->dpio_lock);
4916
4917 bestn = crtc->config.dpll.n;
4918 bestm1 = crtc->config.dpll.m1;
4919 bestm2 = crtc->config.dpll.m2;
4920 bestp1 = crtc->config.dpll.p1;
4921 bestp2 = crtc->config.dpll.p2;
4922
4923 /* See eDP HDMI DPIO driver vbios notes doc */
4924
4925 /* PLL B needs special handling */
4926 if (pipe)
4927 vlv_pllb_recal_opamp(dev_priv, pipe);
4928
4929 /* Set up Tx target for periodic Rcomp update */
4930 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
4931
4932 /* Disable target IRef on PLL */
4933 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
4934 reg_val &= 0x00ffffff;
4935 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
4936
4937 /* Disable fast lock */
4938 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
4939
4940 /* Set idtafcrecal before PLL is enabled */
4941 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4942 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4943 mdiv |= ((bestn << DPIO_N_SHIFT));
4944 mdiv |= (1 << DPIO_K_SHIFT);
4945
4946 /*
4947 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4948 * but we don't support that).
4949 * Note: don't use the DAC post divider as it seems unstable.
4950 */
4951 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4952 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4953
4954 mdiv |= DPIO_ENABLE_CALIBRATION;
4955 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4956
4957 /* Set HBR and RBR LPF coefficients */
4958 if (crtc->config.port_clock == 162000 ||
4959 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4960 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4961 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4962 0x009f0003);
4963 else
4964 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4965 0x00d0000f);
4966
4967 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4968 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4969 /* Use SSC source */
4970 if (!pipe)
4971 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4972 0x0df40000);
4973 else
4974 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4975 0x0df70000);
4976 } else { /* HDMI or VGA */
4977 /* Use bend source */
4978 if (!pipe)
4979 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4980 0x0df70000);
4981 else
4982 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4983 0x0df40000);
4984 }
4985
4986 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
4987 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4988 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4989 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4990 coreclk |= 0x01000000;
4991 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
4992
4993 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
4994
4995 /*
4996 * Enable DPIO clock input. We should never disable the reference
4997 * clock for pipe B, since VGA hotplug / manual detection depends
4998 * on it.
4999 */
5000 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5001 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5002 /* We should never disable this, set it here for state tracking */
5003 if (pipe == PIPE_B)
5004 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5005 dpll |= DPLL_VCO_ENABLE;
5006 crtc->config.dpll_hw_state.dpll = dpll;
5007
5008 dpll_md = (crtc->config.pixel_multiplier - 1)
5009 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5010 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5011
5012 if (crtc->config.has_dp_encoder)
5013 intel_dp_set_m_n(crtc);
5014
5015 mutex_unlock(&dev_priv->dpio_lock);
5016 }
5017
5018 static void i9xx_update_pll(struct intel_crtc *crtc,
5019 intel_clock_t *reduced_clock,
5020 int num_connectors)
5021 {
5022 struct drm_device *dev = crtc->base.dev;
5023 struct drm_i915_private *dev_priv = dev->dev_private;
5024 u32 dpll;
5025 bool is_sdvo;
5026 struct dpll *clock = &crtc->config.dpll;
5027
5028 i9xx_update_pll_dividers(crtc, reduced_clock);
5029
5030 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5031 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5032
5033 dpll = DPLL_VGA_MODE_DIS;
5034
5035 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5036 dpll |= DPLLB_MODE_LVDS;
5037 else
5038 dpll |= DPLLB_MODE_DAC_SERIAL;
5039
5040 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5041 dpll |= (crtc->config.pixel_multiplier - 1)
5042 << SDVO_MULTIPLIER_SHIFT_HIRES;
5043 }
5044
5045 if (is_sdvo)
5046 dpll |= DPLL_SDVO_HIGH_SPEED;
5047
5048 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5049 dpll |= DPLL_SDVO_HIGH_SPEED;
5050
5051 /* compute bitmask from p1 value */
5052 if (IS_PINEVIEW(dev))
5053 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5054 else {
5055 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5056 if (IS_G4X(dev) && reduced_clock)
5057 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5058 }
5059 switch (clock->p2) {
5060 case 5:
5061 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5062 break;
5063 case 7:
5064 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5065 break;
5066 case 10:
5067 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5068 break;
5069 case 14:
5070 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5071 break;
5072 }
5073 if (INTEL_INFO(dev)->gen >= 4)
5074 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5075
5076 if (crtc->config.sdvo_tv_clock)
5077 dpll |= PLL_REF_INPUT_TVCLKINBC;
5078 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5079 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5080 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5081 else
5082 dpll |= PLL_REF_INPUT_DREFCLK;
5083
5084 dpll |= DPLL_VCO_ENABLE;
5085 crtc->config.dpll_hw_state.dpll = dpll;
5086
5087 if (INTEL_INFO(dev)->gen >= 4) {
5088 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5089 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5090 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5091 }
5092
5093 if (crtc->config.has_dp_encoder)
5094 intel_dp_set_m_n(crtc);
5095 }
5096
5097 static void i8xx_update_pll(struct intel_crtc *crtc,
5098 intel_clock_t *reduced_clock,
5099 int num_connectors)
5100 {
5101 struct drm_device *dev = crtc->base.dev;
5102 struct drm_i915_private *dev_priv = dev->dev_private;
5103 u32 dpll;
5104 struct dpll *clock = &crtc->config.dpll;
5105
5106 i9xx_update_pll_dividers(crtc, reduced_clock);
5107
5108 dpll = DPLL_VGA_MODE_DIS;
5109
5110 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5111 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5112 } else {
5113 if (clock->p1 == 2)
5114 dpll |= PLL_P1_DIVIDE_BY_TWO;
5115 else
5116 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5117 if (clock->p2 == 4)
5118 dpll |= PLL_P2_DIVIDE_BY_4;
5119 }
5120
5121 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5122 dpll |= DPLL_DVO_2X_MODE;
5123
5124 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5125 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5126 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5127 else
5128 dpll |= PLL_REF_INPUT_DREFCLK;
5129
5130 dpll |= DPLL_VCO_ENABLE;
5131 crtc->config.dpll_hw_state.dpll = dpll;
5132 }
5133
5134 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5135 {
5136 struct drm_device *dev = intel_crtc->base.dev;
5137 struct drm_i915_private *dev_priv = dev->dev_private;
5138 enum pipe pipe = intel_crtc->pipe;
5139 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5140 struct drm_display_mode *adjusted_mode =
5141 &intel_crtc->config.adjusted_mode;
5142 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
5143
5144 /* We need to be careful not to changed the adjusted mode, for otherwise
5145 * the hw state checker will get angry at the mismatch. */
5146 crtc_vtotal = adjusted_mode->crtc_vtotal;
5147 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5148
5149 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5150 /* the chip adds 2 halflines automatically */
5151 crtc_vtotal -= 1;
5152 crtc_vblank_end -= 1;
5153 vsyncshift = adjusted_mode->crtc_hsync_start
5154 - adjusted_mode->crtc_htotal / 2;
5155 } else {
5156 vsyncshift = 0;
5157 }
5158
5159 if (INTEL_INFO(dev)->gen > 3)
5160 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5161
5162 I915_WRITE(HTOTAL(cpu_transcoder),
5163 (adjusted_mode->crtc_hdisplay - 1) |
5164 ((adjusted_mode->crtc_htotal - 1) << 16));
5165 I915_WRITE(HBLANK(cpu_transcoder),
5166 (adjusted_mode->crtc_hblank_start - 1) |
5167 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5168 I915_WRITE(HSYNC(cpu_transcoder),
5169 (adjusted_mode->crtc_hsync_start - 1) |
5170 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5171
5172 I915_WRITE(VTOTAL(cpu_transcoder),
5173 (adjusted_mode->crtc_vdisplay - 1) |
5174 ((crtc_vtotal - 1) << 16));
5175 I915_WRITE(VBLANK(cpu_transcoder),
5176 (adjusted_mode->crtc_vblank_start - 1) |
5177 ((crtc_vblank_end - 1) << 16));
5178 I915_WRITE(VSYNC(cpu_transcoder),
5179 (adjusted_mode->crtc_vsync_start - 1) |
5180 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5181
5182 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5183 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5184 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5185 * bits. */
5186 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5187 (pipe == PIPE_B || pipe == PIPE_C))
5188 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5189
5190 /* pipesrc controls the size that is scaled from, which should
5191 * always be the user's requested size.
5192 */
5193 I915_WRITE(PIPESRC(pipe),
5194 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5195 (intel_crtc->config.pipe_src_h - 1));
5196 }
5197
5198 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5199 struct intel_crtc_config *pipe_config)
5200 {
5201 struct drm_device *dev = crtc->base.dev;
5202 struct drm_i915_private *dev_priv = dev->dev_private;
5203 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5204 uint32_t tmp;
5205
5206 tmp = I915_READ(HTOTAL(cpu_transcoder));
5207 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5208 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5209 tmp = I915_READ(HBLANK(cpu_transcoder));
5210 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5211 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5212 tmp = I915_READ(HSYNC(cpu_transcoder));
5213 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5214 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5215
5216 tmp = I915_READ(VTOTAL(cpu_transcoder));
5217 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5218 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5219 tmp = I915_READ(VBLANK(cpu_transcoder));
5220 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5221 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5222 tmp = I915_READ(VSYNC(cpu_transcoder));
5223 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5224 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5225
5226 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5227 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5228 pipe_config->adjusted_mode.crtc_vtotal += 1;
5229 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5230 }
5231
5232 tmp = I915_READ(PIPESRC(crtc->pipe));
5233 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5234 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5235
5236 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5237 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5238 }
5239
5240 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5241 struct intel_crtc_config *pipe_config)
5242 {
5243 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5244 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5245 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5246 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5247
5248 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5249 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5250 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5251 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5252
5253 mode->flags = pipe_config->adjusted_mode.flags;
5254
5255 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5256 mode->flags |= pipe_config->adjusted_mode.flags;
5257 }
5258
5259 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5260 {
5261 struct drm_device *dev = intel_crtc->base.dev;
5262 struct drm_i915_private *dev_priv = dev->dev_private;
5263 uint32_t pipeconf;
5264
5265 pipeconf = 0;
5266
5267 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5268 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5269 pipeconf |= PIPECONF_ENABLE;
5270
5271 if (intel_crtc->config.double_wide)
5272 pipeconf |= PIPECONF_DOUBLE_WIDE;
5273
5274 /* only g4x and later have fancy bpc/dither controls */
5275 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5276 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5277 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5278 pipeconf |= PIPECONF_DITHER_EN |
5279 PIPECONF_DITHER_TYPE_SP;
5280
5281 switch (intel_crtc->config.pipe_bpp) {
5282 case 18:
5283 pipeconf |= PIPECONF_6BPC;
5284 break;
5285 case 24:
5286 pipeconf |= PIPECONF_8BPC;
5287 break;
5288 case 30:
5289 pipeconf |= PIPECONF_10BPC;
5290 break;
5291 default:
5292 /* Case prevented by intel_choose_pipe_bpp_dither. */
5293 BUG();
5294 }
5295 }
5296
5297 if (HAS_PIPE_CXSR(dev)) {
5298 if (intel_crtc->lowfreq_avail) {
5299 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5300 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5301 } else {
5302 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5303 }
5304 }
5305
5306 if (!IS_GEN2(dev) &&
5307 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5308 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5309 else
5310 pipeconf |= PIPECONF_PROGRESSIVE;
5311
5312 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5313 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5314
5315 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5316 POSTING_READ(PIPECONF(intel_crtc->pipe));
5317 }
5318
5319 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5320 int x, int y,
5321 struct drm_framebuffer *fb)
5322 {
5323 struct drm_device *dev = crtc->dev;
5324 struct drm_i915_private *dev_priv = dev->dev_private;
5325 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5326 int pipe = intel_crtc->pipe;
5327 int plane = intel_crtc->plane;
5328 int refclk, num_connectors = 0;
5329 intel_clock_t clock, reduced_clock;
5330 u32 dspcntr;
5331 bool ok, has_reduced_clock = false;
5332 bool is_lvds = false, is_dsi = false;
5333 struct intel_encoder *encoder;
5334 const intel_limit_t *limit;
5335 int ret;
5336
5337 for_each_encoder_on_crtc(dev, crtc, encoder) {
5338 switch (encoder->type) {
5339 case INTEL_OUTPUT_LVDS:
5340 is_lvds = true;
5341 break;
5342 case INTEL_OUTPUT_DSI:
5343 is_dsi = true;
5344 break;
5345 }
5346
5347 num_connectors++;
5348 }
5349
5350 if (is_dsi)
5351 goto skip_dpll;
5352
5353 if (!intel_crtc->config.clock_set) {
5354 refclk = i9xx_get_refclk(crtc, num_connectors);
5355
5356 /*
5357 * Returns a set of divisors for the desired target clock with
5358 * the given refclk, or FALSE. The returned values represent
5359 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5360 * 2) / p1 / p2.
5361 */
5362 limit = intel_limit(crtc, refclk);
5363 ok = dev_priv->display.find_dpll(limit, crtc,
5364 intel_crtc->config.port_clock,
5365 refclk, NULL, &clock);
5366 if (!ok) {
5367 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5368 return -EINVAL;
5369 }
5370
5371 if (is_lvds && dev_priv->lvds_downclock_avail) {
5372 /*
5373 * Ensure we match the reduced clock's P to the target
5374 * clock. If the clocks don't match, we can't switch
5375 * the display clock by using the FP0/FP1. In such case
5376 * we will disable the LVDS downclock feature.
5377 */
5378 has_reduced_clock =
5379 dev_priv->display.find_dpll(limit, crtc,
5380 dev_priv->lvds_downclock,
5381 refclk, &clock,
5382 &reduced_clock);
5383 }
5384 /* Compat-code for transition, will disappear. */
5385 intel_crtc->config.dpll.n = clock.n;
5386 intel_crtc->config.dpll.m1 = clock.m1;
5387 intel_crtc->config.dpll.m2 = clock.m2;
5388 intel_crtc->config.dpll.p1 = clock.p1;
5389 intel_crtc->config.dpll.p2 = clock.p2;
5390 }
5391
5392 if (IS_GEN2(dev)) {
5393 i8xx_update_pll(intel_crtc,
5394 has_reduced_clock ? &reduced_clock : NULL,
5395 num_connectors);
5396 } else if (IS_VALLEYVIEW(dev)) {
5397 vlv_update_pll(intel_crtc);
5398 } else {
5399 i9xx_update_pll(intel_crtc,
5400 has_reduced_clock ? &reduced_clock : NULL,
5401 num_connectors);
5402 }
5403
5404 skip_dpll:
5405 /* Set up the display plane register */
5406 dspcntr = DISPPLANE_GAMMA_ENABLE;
5407
5408 if (!IS_VALLEYVIEW(dev)) {
5409 if (pipe == 0)
5410 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5411 else
5412 dspcntr |= DISPPLANE_SEL_PIPE_B;
5413 }
5414
5415 intel_set_pipe_timings(intel_crtc);
5416
5417 /* pipesrc and dspsize control the size that is scaled from,
5418 * which should always be the user's requested size.
5419 */
5420 I915_WRITE(DSPSIZE(plane),
5421 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5422 (intel_crtc->config.pipe_src_w - 1));
5423 I915_WRITE(DSPPOS(plane), 0);
5424
5425 i9xx_set_pipeconf(intel_crtc);
5426
5427 I915_WRITE(DSPCNTR(plane), dspcntr);
5428 POSTING_READ(DSPCNTR(plane));
5429
5430 ret = intel_pipe_set_base(crtc, x, y, fb);
5431
5432 return ret;
5433 }
5434
5435 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5436 struct intel_crtc_config *pipe_config)
5437 {
5438 struct drm_device *dev = crtc->base.dev;
5439 struct drm_i915_private *dev_priv = dev->dev_private;
5440 uint32_t tmp;
5441
5442 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5443 return;
5444
5445 tmp = I915_READ(PFIT_CONTROL);
5446 if (!(tmp & PFIT_ENABLE))
5447 return;
5448
5449 /* Check whether the pfit is attached to our pipe. */
5450 if (INTEL_INFO(dev)->gen < 4) {
5451 if (crtc->pipe != PIPE_B)
5452 return;
5453 } else {
5454 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5455 return;
5456 }
5457
5458 pipe_config->gmch_pfit.control = tmp;
5459 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5460 if (INTEL_INFO(dev)->gen < 5)
5461 pipe_config->gmch_pfit.lvds_border_bits =
5462 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5463 }
5464
5465 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5466 struct intel_crtc_config *pipe_config)
5467 {
5468 struct drm_device *dev = crtc->base.dev;
5469 struct drm_i915_private *dev_priv = dev->dev_private;
5470 int pipe = pipe_config->cpu_transcoder;
5471 intel_clock_t clock;
5472 u32 mdiv;
5473 int refclk = 100000;
5474
5475 mutex_lock(&dev_priv->dpio_lock);
5476 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5477 mutex_unlock(&dev_priv->dpio_lock);
5478
5479 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5480 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5481 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5482 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5483 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5484
5485 vlv_clock(refclk, &clock);
5486
5487 /* clock.dot is the fast clock */
5488 pipe_config->port_clock = clock.dot / 5;
5489 }
5490
5491 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5492 struct intel_crtc_config *pipe_config)
5493 {
5494 struct drm_device *dev = crtc->base.dev;
5495 struct drm_i915_private *dev_priv = dev->dev_private;
5496 uint32_t tmp;
5497
5498 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5499 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5500
5501 tmp = I915_READ(PIPECONF(crtc->pipe));
5502 if (!(tmp & PIPECONF_ENABLE))
5503 return false;
5504
5505 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5506 switch (tmp & PIPECONF_BPC_MASK) {
5507 case PIPECONF_6BPC:
5508 pipe_config->pipe_bpp = 18;
5509 break;
5510 case PIPECONF_8BPC:
5511 pipe_config->pipe_bpp = 24;
5512 break;
5513 case PIPECONF_10BPC:
5514 pipe_config->pipe_bpp = 30;
5515 break;
5516 default:
5517 break;
5518 }
5519 }
5520
5521 if (INTEL_INFO(dev)->gen < 4)
5522 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5523
5524 intel_get_pipe_timings(crtc, pipe_config);
5525
5526 i9xx_get_pfit_config(crtc, pipe_config);
5527
5528 if (INTEL_INFO(dev)->gen >= 4) {
5529 tmp = I915_READ(DPLL_MD(crtc->pipe));
5530 pipe_config->pixel_multiplier =
5531 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5532 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5533 pipe_config->dpll_hw_state.dpll_md = tmp;
5534 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5535 tmp = I915_READ(DPLL(crtc->pipe));
5536 pipe_config->pixel_multiplier =
5537 ((tmp & SDVO_MULTIPLIER_MASK)
5538 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5539 } else {
5540 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5541 * port and will be fixed up in the encoder->get_config
5542 * function. */
5543 pipe_config->pixel_multiplier = 1;
5544 }
5545 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5546 if (!IS_VALLEYVIEW(dev)) {
5547 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5548 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5549 } else {
5550 /* Mask out read-only status bits. */
5551 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5552 DPLL_PORTC_READY_MASK |
5553 DPLL_PORTB_READY_MASK);
5554 }
5555
5556 if (IS_VALLEYVIEW(dev))
5557 vlv_crtc_clock_get(crtc, pipe_config);
5558 else
5559 i9xx_crtc_clock_get(crtc, pipe_config);
5560
5561 return true;
5562 }
5563
5564 static void ironlake_init_pch_refclk(struct drm_device *dev)
5565 {
5566 struct drm_i915_private *dev_priv = dev->dev_private;
5567 struct drm_mode_config *mode_config = &dev->mode_config;
5568 struct intel_encoder *encoder;
5569 u32 val, final;
5570 bool has_lvds = false;
5571 bool has_cpu_edp = false;
5572 bool has_panel = false;
5573 bool has_ck505 = false;
5574 bool can_ssc = false;
5575
5576 /* We need to take the global config into account */
5577 list_for_each_entry(encoder, &mode_config->encoder_list,
5578 base.head) {
5579 switch (encoder->type) {
5580 case INTEL_OUTPUT_LVDS:
5581 has_panel = true;
5582 has_lvds = true;
5583 break;
5584 case INTEL_OUTPUT_EDP:
5585 has_panel = true;
5586 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5587 has_cpu_edp = true;
5588 break;
5589 }
5590 }
5591
5592 if (HAS_PCH_IBX(dev)) {
5593 has_ck505 = dev_priv->vbt.display_clock_mode;
5594 can_ssc = has_ck505;
5595 } else {
5596 has_ck505 = false;
5597 can_ssc = true;
5598 }
5599
5600 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5601 has_panel, has_lvds, has_ck505);
5602
5603 /* Ironlake: try to setup display ref clock before DPLL
5604 * enabling. This is only under driver's control after
5605 * PCH B stepping, previous chipset stepping should be
5606 * ignoring this setting.
5607 */
5608 val = I915_READ(PCH_DREF_CONTROL);
5609
5610 /* As we must carefully and slowly disable/enable each source in turn,
5611 * compute the final state we want first and check if we need to
5612 * make any changes at all.
5613 */
5614 final = val;
5615 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5616 if (has_ck505)
5617 final |= DREF_NONSPREAD_CK505_ENABLE;
5618 else
5619 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5620
5621 final &= ~DREF_SSC_SOURCE_MASK;
5622 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5623 final &= ~DREF_SSC1_ENABLE;
5624
5625 if (has_panel) {
5626 final |= DREF_SSC_SOURCE_ENABLE;
5627
5628 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5629 final |= DREF_SSC1_ENABLE;
5630
5631 if (has_cpu_edp) {
5632 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5633 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5634 else
5635 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5636 } else
5637 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5638 } else {
5639 final |= DREF_SSC_SOURCE_DISABLE;
5640 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5641 }
5642
5643 if (final == val)
5644 return;
5645
5646 /* Always enable nonspread source */
5647 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5648
5649 if (has_ck505)
5650 val |= DREF_NONSPREAD_CK505_ENABLE;
5651 else
5652 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5653
5654 if (has_panel) {
5655 val &= ~DREF_SSC_SOURCE_MASK;
5656 val |= DREF_SSC_SOURCE_ENABLE;
5657
5658 /* SSC must be turned on before enabling the CPU output */
5659 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5660 DRM_DEBUG_KMS("Using SSC on panel\n");
5661 val |= DREF_SSC1_ENABLE;
5662 } else
5663 val &= ~DREF_SSC1_ENABLE;
5664
5665 /* Get SSC going before enabling the outputs */
5666 I915_WRITE(PCH_DREF_CONTROL, val);
5667 POSTING_READ(PCH_DREF_CONTROL);
5668 udelay(200);
5669
5670 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5671
5672 /* Enable CPU source on CPU attached eDP */
5673 if (has_cpu_edp) {
5674 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5675 DRM_DEBUG_KMS("Using SSC on eDP\n");
5676 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5677 }
5678 else
5679 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5680 } else
5681 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5682
5683 I915_WRITE(PCH_DREF_CONTROL, val);
5684 POSTING_READ(PCH_DREF_CONTROL);
5685 udelay(200);
5686 } else {
5687 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5688
5689 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5690
5691 /* Turn off CPU output */
5692 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5693
5694 I915_WRITE(PCH_DREF_CONTROL, val);
5695 POSTING_READ(PCH_DREF_CONTROL);
5696 udelay(200);
5697
5698 /* Turn off the SSC source */
5699 val &= ~DREF_SSC_SOURCE_MASK;
5700 val |= DREF_SSC_SOURCE_DISABLE;
5701
5702 /* Turn off SSC1 */
5703 val &= ~DREF_SSC1_ENABLE;
5704
5705 I915_WRITE(PCH_DREF_CONTROL, val);
5706 POSTING_READ(PCH_DREF_CONTROL);
5707 udelay(200);
5708 }
5709
5710 BUG_ON(val != final);
5711 }
5712
5713 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5714 {
5715 uint32_t tmp;
5716
5717 tmp = I915_READ(SOUTH_CHICKEN2);
5718 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5719 I915_WRITE(SOUTH_CHICKEN2, tmp);
5720
5721 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5722 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5723 DRM_ERROR("FDI mPHY reset assert timeout\n");
5724
5725 tmp = I915_READ(SOUTH_CHICKEN2);
5726 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5727 I915_WRITE(SOUTH_CHICKEN2, tmp);
5728
5729 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5730 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5731 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5732 }
5733
5734 /* WaMPhyProgramming:hsw */
5735 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5736 {
5737 uint32_t tmp;
5738
5739 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5740 tmp &= ~(0xFF << 24);
5741 tmp |= (0x12 << 24);
5742 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5743
5744 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5745 tmp |= (1 << 11);
5746 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5747
5748 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5749 tmp |= (1 << 11);
5750 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5751
5752 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5753 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5754 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5755
5756 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5757 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5758 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5759
5760 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5761 tmp &= ~(7 << 13);
5762 tmp |= (5 << 13);
5763 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5764
5765 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5766 tmp &= ~(7 << 13);
5767 tmp |= (5 << 13);
5768 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5769
5770 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5771 tmp &= ~0xFF;
5772 tmp |= 0x1C;
5773 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5774
5775 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5776 tmp &= ~0xFF;
5777 tmp |= 0x1C;
5778 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5779
5780 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5781 tmp &= ~(0xFF << 16);
5782 tmp |= (0x1C << 16);
5783 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5784
5785 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5786 tmp &= ~(0xFF << 16);
5787 tmp |= (0x1C << 16);
5788 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5789
5790 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5791 tmp |= (1 << 27);
5792 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5793
5794 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5795 tmp |= (1 << 27);
5796 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5797
5798 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5799 tmp &= ~(0xF << 28);
5800 tmp |= (4 << 28);
5801 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5802
5803 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5804 tmp &= ~(0xF << 28);
5805 tmp |= (4 << 28);
5806 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5807 }
5808
5809 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5810 * Programming" based on the parameters passed:
5811 * - Sequence to enable CLKOUT_DP
5812 * - Sequence to enable CLKOUT_DP without spread
5813 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5814 */
5815 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5816 bool with_fdi)
5817 {
5818 struct drm_i915_private *dev_priv = dev->dev_private;
5819 uint32_t reg, tmp;
5820
5821 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5822 with_spread = true;
5823 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5824 with_fdi, "LP PCH doesn't have FDI\n"))
5825 with_fdi = false;
5826
5827 mutex_lock(&dev_priv->dpio_lock);
5828
5829 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5830 tmp &= ~SBI_SSCCTL_DISABLE;
5831 tmp |= SBI_SSCCTL_PATHALT;
5832 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5833
5834 udelay(24);
5835
5836 if (with_spread) {
5837 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5838 tmp &= ~SBI_SSCCTL_PATHALT;
5839 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5840
5841 if (with_fdi) {
5842 lpt_reset_fdi_mphy(dev_priv);
5843 lpt_program_fdi_mphy(dev_priv);
5844 }
5845 }
5846
5847 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5848 SBI_GEN0 : SBI_DBUFF0;
5849 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5850 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5851 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5852
5853 mutex_unlock(&dev_priv->dpio_lock);
5854 }
5855
5856 /* Sequence to disable CLKOUT_DP */
5857 static void lpt_disable_clkout_dp(struct drm_device *dev)
5858 {
5859 struct drm_i915_private *dev_priv = dev->dev_private;
5860 uint32_t reg, tmp;
5861
5862 mutex_lock(&dev_priv->dpio_lock);
5863
5864 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5865 SBI_GEN0 : SBI_DBUFF0;
5866 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5867 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5868 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5869
5870 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5871 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5872 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5873 tmp |= SBI_SSCCTL_PATHALT;
5874 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5875 udelay(32);
5876 }
5877 tmp |= SBI_SSCCTL_DISABLE;
5878 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5879 }
5880
5881 mutex_unlock(&dev_priv->dpio_lock);
5882 }
5883
5884 static void lpt_init_pch_refclk(struct drm_device *dev)
5885 {
5886 struct drm_mode_config *mode_config = &dev->mode_config;
5887 struct intel_encoder *encoder;
5888 bool has_vga = false;
5889
5890 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5891 switch (encoder->type) {
5892 case INTEL_OUTPUT_ANALOG:
5893 has_vga = true;
5894 break;
5895 }
5896 }
5897
5898 if (has_vga)
5899 lpt_enable_clkout_dp(dev, true, true);
5900 else
5901 lpt_disable_clkout_dp(dev);
5902 }
5903
5904 /*
5905 * Initialize reference clocks when the driver loads
5906 */
5907 void intel_init_pch_refclk(struct drm_device *dev)
5908 {
5909 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5910 ironlake_init_pch_refclk(dev);
5911 else if (HAS_PCH_LPT(dev))
5912 lpt_init_pch_refclk(dev);
5913 }
5914
5915 static int ironlake_get_refclk(struct drm_crtc *crtc)
5916 {
5917 struct drm_device *dev = crtc->dev;
5918 struct drm_i915_private *dev_priv = dev->dev_private;
5919 struct intel_encoder *encoder;
5920 int num_connectors = 0;
5921 bool is_lvds = false;
5922
5923 for_each_encoder_on_crtc(dev, crtc, encoder) {
5924 switch (encoder->type) {
5925 case INTEL_OUTPUT_LVDS:
5926 is_lvds = true;
5927 break;
5928 }
5929 num_connectors++;
5930 }
5931
5932 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5933 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
5934 dev_priv->vbt.lvds_ssc_freq);
5935 return dev_priv->vbt.lvds_ssc_freq;
5936 }
5937
5938 return 120000;
5939 }
5940
5941 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5942 {
5943 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5945 int pipe = intel_crtc->pipe;
5946 uint32_t val;
5947
5948 val = 0;
5949
5950 switch (intel_crtc->config.pipe_bpp) {
5951 case 18:
5952 val |= PIPECONF_6BPC;
5953 break;
5954 case 24:
5955 val |= PIPECONF_8BPC;
5956 break;
5957 case 30:
5958 val |= PIPECONF_10BPC;
5959 break;
5960 case 36:
5961 val |= PIPECONF_12BPC;
5962 break;
5963 default:
5964 /* Case prevented by intel_choose_pipe_bpp_dither. */
5965 BUG();
5966 }
5967
5968 if (intel_crtc->config.dither)
5969 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5970
5971 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5972 val |= PIPECONF_INTERLACED_ILK;
5973 else
5974 val |= PIPECONF_PROGRESSIVE;
5975
5976 if (intel_crtc->config.limited_color_range)
5977 val |= PIPECONF_COLOR_RANGE_SELECT;
5978
5979 I915_WRITE(PIPECONF(pipe), val);
5980 POSTING_READ(PIPECONF(pipe));
5981 }
5982
5983 /*
5984 * Set up the pipe CSC unit.
5985 *
5986 * Currently only full range RGB to limited range RGB conversion
5987 * is supported, but eventually this should handle various
5988 * RGB<->YCbCr scenarios as well.
5989 */
5990 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5991 {
5992 struct drm_device *dev = crtc->dev;
5993 struct drm_i915_private *dev_priv = dev->dev_private;
5994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5995 int pipe = intel_crtc->pipe;
5996 uint16_t coeff = 0x7800; /* 1.0 */
5997
5998 /*
5999 * TODO: Check what kind of values actually come out of the pipe
6000 * with these coeff/postoff values and adjust to get the best
6001 * accuracy. Perhaps we even need to take the bpc value into
6002 * consideration.
6003 */
6004
6005 if (intel_crtc->config.limited_color_range)
6006 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6007
6008 /*
6009 * GY/GU and RY/RU should be the other way around according
6010 * to BSpec, but reality doesn't agree. Just set them up in
6011 * a way that results in the correct picture.
6012 */
6013 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6014 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6015
6016 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6017 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6018
6019 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6020 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6021
6022 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6023 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6024 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6025
6026 if (INTEL_INFO(dev)->gen > 6) {
6027 uint16_t postoff = 0;
6028
6029 if (intel_crtc->config.limited_color_range)
6030 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6031
6032 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6033 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6034 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6035
6036 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6037 } else {
6038 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6039
6040 if (intel_crtc->config.limited_color_range)
6041 mode |= CSC_BLACK_SCREEN_OFFSET;
6042
6043 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6044 }
6045 }
6046
6047 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6048 {
6049 struct drm_device *dev = crtc->dev;
6050 struct drm_i915_private *dev_priv = dev->dev_private;
6051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6052 enum pipe pipe = intel_crtc->pipe;
6053 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6054 uint32_t val;
6055
6056 val = 0;
6057
6058 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6059 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6060
6061 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6062 val |= PIPECONF_INTERLACED_ILK;
6063 else
6064 val |= PIPECONF_PROGRESSIVE;
6065
6066 I915_WRITE(PIPECONF(cpu_transcoder), val);
6067 POSTING_READ(PIPECONF(cpu_transcoder));
6068
6069 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6070 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6071
6072 if (IS_BROADWELL(dev)) {
6073 val = 0;
6074
6075 switch (intel_crtc->config.pipe_bpp) {
6076 case 18:
6077 val |= PIPEMISC_DITHER_6_BPC;
6078 break;
6079 case 24:
6080 val |= PIPEMISC_DITHER_8_BPC;
6081 break;
6082 case 30:
6083 val |= PIPEMISC_DITHER_10_BPC;
6084 break;
6085 case 36:
6086 val |= PIPEMISC_DITHER_12_BPC;
6087 break;
6088 default:
6089 /* Case prevented by pipe_config_set_bpp. */
6090 BUG();
6091 }
6092
6093 if (intel_crtc->config.dither)
6094 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6095
6096 I915_WRITE(PIPEMISC(pipe), val);
6097 }
6098 }
6099
6100 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6101 intel_clock_t *clock,
6102 bool *has_reduced_clock,
6103 intel_clock_t *reduced_clock)
6104 {
6105 struct drm_device *dev = crtc->dev;
6106 struct drm_i915_private *dev_priv = dev->dev_private;
6107 struct intel_encoder *intel_encoder;
6108 int refclk;
6109 const intel_limit_t *limit;
6110 bool ret, is_lvds = false;
6111
6112 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6113 switch (intel_encoder->type) {
6114 case INTEL_OUTPUT_LVDS:
6115 is_lvds = true;
6116 break;
6117 }
6118 }
6119
6120 refclk = ironlake_get_refclk(crtc);
6121
6122 /*
6123 * Returns a set of divisors for the desired target clock with the given
6124 * refclk, or FALSE. The returned values represent the clock equation:
6125 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6126 */
6127 limit = intel_limit(crtc, refclk);
6128 ret = dev_priv->display.find_dpll(limit, crtc,
6129 to_intel_crtc(crtc)->config.port_clock,
6130 refclk, NULL, clock);
6131 if (!ret)
6132 return false;
6133
6134 if (is_lvds && dev_priv->lvds_downclock_avail) {
6135 /*
6136 * Ensure we match the reduced clock's P to the target clock.
6137 * If the clocks don't match, we can't switch the display clock
6138 * by using the FP0/FP1. In such case we will disable the LVDS
6139 * downclock feature.
6140 */
6141 *has_reduced_clock =
6142 dev_priv->display.find_dpll(limit, crtc,
6143 dev_priv->lvds_downclock,
6144 refclk, clock,
6145 reduced_clock);
6146 }
6147
6148 return true;
6149 }
6150
6151 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6152 {
6153 /*
6154 * Account for spread spectrum to avoid
6155 * oversubscribing the link. Max center spread
6156 * is 2.5%; use 5% for safety's sake.
6157 */
6158 u32 bps = target_clock * bpp * 21 / 20;
6159 return bps / (link_bw * 8) + 1;
6160 }
6161
6162 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6163 {
6164 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6165 }
6166
6167 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6168 u32 *fp,
6169 intel_clock_t *reduced_clock, u32 *fp2)
6170 {
6171 struct drm_crtc *crtc = &intel_crtc->base;
6172 struct drm_device *dev = crtc->dev;
6173 struct drm_i915_private *dev_priv = dev->dev_private;
6174 struct intel_encoder *intel_encoder;
6175 uint32_t dpll;
6176 int factor, num_connectors = 0;
6177 bool is_lvds = false, is_sdvo = false;
6178
6179 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6180 switch (intel_encoder->type) {
6181 case INTEL_OUTPUT_LVDS:
6182 is_lvds = true;
6183 break;
6184 case INTEL_OUTPUT_SDVO:
6185 case INTEL_OUTPUT_HDMI:
6186 is_sdvo = true;
6187 break;
6188 }
6189
6190 num_connectors++;
6191 }
6192
6193 /* Enable autotuning of the PLL clock (if permissible) */
6194 factor = 21;
6195 if (is_lvds) {
6196 if ((intel_panel_use_ssc(dev_priv) &&
6197 dev_priv->vbt.lvds_ssc_freq == 100000) ||
6198 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6199 factor = 25;
6200 } else if (intel_crtc->config.sdvo_tv_clock)
6201 factor = 20;
6202
6203 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6204 *fp |= FP_CB_TUNE;
6205
6206 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6207 *fp2 |= FP_CB_TUNE;
6208
6209 dpll = 0;
6210
6211 if (is_lvds)
6212 dpll |= DPLLB_MODE_LVDS;
6213 else
6214 dpll |= DPLLB_MODE_DAC_SERIAL;
6215
6216 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6217 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6218
6219 if (is_sdvo)
6220 dpll |= DPLL_SDVO_HIGH_SPEED;
6221 if (intel_crtc->config.has_dp_encoder)
6222 dpll |= DPLL_SDVO_HIGH_SPEED;
6223
6224 /* compute bitmask from p1 value */
6225 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6226 /* also FPA1 */
6227 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6228
6229 switch (intel_crtc->config.dpll.p2) {
6230 case 5:
6231 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6232 break;
6233 case 7:
6234 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6235 break;
6236 case 10:
6237 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6238 break;
6239 case 14:
6240 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6241 break;
6242 }
6243
6244 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6245 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6246 else
6247 dpll |= PLL_REF_INPUT_DREFCLK;
6248
6249 return dpll | DPLL_VCO_ENABLE;
6250 }
6251
6252 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6253 int x, int y,
6254 struct drm_framebuffer *fb)
6255 {
6256 struct drm_device *dev = crtc->dev;
6257 struct drm_i915_private *dev_priv = dev->dev_private;
6258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6259 int pipe = intel_crtc->pipe;
6260 int plane = intel_crtc->plane;
6261 int num_connectors = 0;
6262 intel_clock_t clock, reduced_clock;
6263 u32 dpll = 0, fp = 0, fp2 = 0;
6264 bool ok, has_reduced_clock = false;
6265 bool is_lvds = false;
6266 struct intel_encoder *encoder;
6267 struct intel_shared_dpll *pll;
6268 int ret;
6269
6270 for_each_encoder_on_crtc(dev, crtc, encoder) {
6271 switch (encoder->type) {
6272 case INTEL_OUTPUT_LVDS:
6273 is_lvds = true;
6274 break;
6275 }
6276
6277 num_connectors++;
6278 }
6279
6280 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6281 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6282
6283 ok = ironlake_compute_clocks(crtc, &clock,
6284 &has_reduced_clock, &reduced_clock);
6285 if (!ok && !intel_crtc->config.clock_set) {
6286 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6287 return -EINVAL;
6288 }
6289 /* Compat-code for transition, will disappear. */
6290 if (!intel_crtc->config.clock_set) {
6291 intel_crtc->config.dpll.n = clock.n;
6292 intel_crtc->config.dpll.m1 = clock.m1;
6293 intel_crtc->config.dpll.m2 = clock.m2;
6294 intel_crtc->config.dpll.p1 = clock.p1;
6295 intel_crtc->config.dpll.p2 = clock.p2;
6296 }
6297
6298 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6299 if (intel_crtc->config.has_pch_encoder) {
6300 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6301 if (has_reduced_clock)
6302 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6303
6304 dpll = ironlake_compute_dpll(intel_crtc,
6305 &fp, &reduced_clock,
6306 has_reduced_clock ? &fp2 : NULL);
6307
6308 intel_crtc->config.dpll_hw_state.dpll = dpll;
6309 intel_crtc->config.dpll_hw_state.fp0 = fp;
6310 if (has_reduced_clock)
6311 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6312 else
6313 intel_crtc->config.dpll_hw_state.fp1 = fp;
6314
6315 pll = intel_get_shared_dpll(intel_crtc);
6316 if (pll == NULL) {
6317 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6318 pipe_name(pipe));
6319 return -EINVAL;
6320 }
6321 } else
6322 intel_put_shared_dpll(intel_crtc);
6323
6324 if (intel_crtc->config.has_dp_encoder)
6325 intel_dp_set_m_n(intel_crtc);
6326
6327 if (is_lvds && has_reduced_clock && i915.powersave)
6328 intel_crtc->lowfreq_avail = true;
6329 else
6330 intel_crtc->lowfreq_avail = false;
6331
6332 intel_set_pipe_timings(intel_crtc);
6333
6334 if (intel_crtc->config.has_pch_encoder) {
6335 intel_cpu_transcoder_set_m_n(intel_crtc,
6336 &intel_crtc->config.fdi_m_n);
6337 }
6338
6339 ironlake_set_pipeconf(crtc);
6340
6341 /* Set up the display plane register */
6342 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6343 POSTING_READ(DSPCNTR(plane));
6344
6345 ret = intel_pipe_set_base(crtc, x, y, fb);
6346
6347 return ret;
6348 }
6349
6350 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6351 struct intel_link_m_n *m_n)
6352 {
6353 struct drm_device *dev = crtc->base.dev;
6354 struct drm_i915_private *dev_priv = dev->dev_private;
6355 enum pipe pipe = crtc->pipe;
6356
6357 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6358 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6359 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6360 & ~TU_SIZE_MASK;
6361 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6362 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6363 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6364 }
6365
6366 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6367 enum transcoder transcoder,
6368 struct intel_link_m_n *m_n)
6369 {
6370 struct drm_device *dev = crtc->base.dev;
6371 struct drm_i915_private *dev_priv = dev->dev_private;
6372 enum pipe pipe = crtc->pipe;
6373
6374 if (INTEL_INFO(dev)->gen >= 5) {
6375 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6376 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6377 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6378 & ~TU_SIZE_MASK;
6379 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6380 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6381 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6382 } else {
6383 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6384 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6385 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6386 & ~TU_SIZE_MASK;
6387 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6388 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6389 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6390 }
6391 }
6392
6393 void intel_dp_get_m_n(struct intel_crtc *crtc,
6394 struct intel_crtc_config *pipe_config)
6395 {
6396 if (crtc->config.has_pch_encoder)
6397 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6398 else
6399 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6400 &pipe_config->dp_m_n);
6401 }
6402
6403 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6404 struct intel_crtc_config *pipe_config)
6405 {
6406 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6407 &pipe_config->fdi_m_n);
6408 }
6409
6410 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6411 struct intel_crtc_config *pipe_config)
6412 {
6413 struct drm_device *dev = crtc->base.dev;
6414 struct drm_i915_private *dev_priv = dev->dev_private;
6415 uint32_t tmp;
6416
6417 tmp = I915_READ(PF_CTL(crtc->pipe));
6418
6419 if (tmp & PF_ENABLE) {
6420 pipe_config->pch_pfit.enabled = true;
6421 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6422 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6423
6424 /* We currently do not free assignements of panel fitters on
6425 * ivb/hsw (since we don't use the higher upscaling modes which
6426 * differentiates them) so just WARN about this case for now. */
6427 if (IS_GEN7(dev)) {
6428 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6429 PF_PIPE_SEL_IVB(crtc->pipe));
6430 }
6431 }
6432 }
6433
6434 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6435 struct intel_crtc_config *pipe_config)
6436 {
6437 struct drm_device *dev = crtc->base.dev;
6438 struct drm_i915_private *dev_priv = dev->dev_private;
6439 uint32_t tmp;
6440
6441 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6442 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6443
6444 tmp = I915_READ(PIPECONF(crtc->pipe));
6445 if (!(tmp & PIPECONF_ENABLE))
6446 return false;
6447
6448 switch (tmp & PIPECONF_BPC_MASK) {
6449 case PIPECONF_6BPC:
6450 pipe_config->pipe_bpp = 18;
6451 break;
6452 case PIPECONF_8BPC:
6453 pipe_config->pipe_bpp = 24;
6454 break;
6455 case PIPECONF_10BPC:
6456 pipe_config->pipe_bpp = 30;
6457 break;
6458 case PIPECONF_12BPC:
6459 pipe_config->pipe_bpp = 36;
6460 break;
6461 default:
6462 break;
6463 }
6464
6465 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6466 struct intel_shared_dpll *pll;
6467
6468 pipe_config->has_pch_encoder = true;
6469
6470 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6471 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6472 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6473
6474 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6475
6476 if (HAS_PCH_IBX(dev_priv->dev)) {
6477 pipe_config->shared_dpll =
6478 (enum intel_dpll_id) crtc->pipe;
6479 } else {
6480 tmp = I915_READ(PCH_DPLL_SEL);
6481 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6482 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6483 else
6484 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6485 }
6486
6487 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6488
6489 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6490 &pipe_config->dpll_hw_state));
6491
6492 tmp = pipe_config->dpll_hw_state.dpll;
6493 pipe_config->pixel_multiplier =
6494 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6495 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6496
6497 ironlake_pch_clock_get(crtc, pipe_config);
6498 } else {
6499 pipe_config->pixel_multiplier = 1;
6500 }
6501
6502 intel_get_pipe_timings(crtc, pipe_config);
6503
6504 ironlake_get_pfit_config(crtc, pipe_config);
6505
6506 return true;
6507 }
6508
6509 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6510 {
6511 struct drm_device *dev = dev_priv->dev;
6512 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6513 struct intel_crtc *crtc;
6514 unsigned long irqflags;
6515 uint32_t val;
6516
6517 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6518 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6519 pipe_name(crtc->pipe));
6520
6521 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6522 WARN(plls->spll_refcount, "SPLL enabled\n");
6523 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6524 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6525 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6526 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6527 "CPU PWM1 enabled\n");
6528 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6529 "CPU PWM2 enabled\n");
6530 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6531 "PCH PWM1 enabled\n");
6532 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6533 "Utility pin enabled\n");
6534 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6535
6536 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6537 val = I915_READ(DEIMR);
6538 WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff,
6539 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6540 val = I915_READ(SDEIMR);
6541 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6542 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6543 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6544 }
6545
6546 /*
6547 * This function implements pieces of two sequences from BSpec:
6548 * - Sequence for display software to disable LCPLL
6549 * - Sequence for display software to allow package C8+
6550 * The steps implemented here are just the steps that actually touch the LCPLL
6551 * register. Callers should take care of disabling all the display engine
6552 * functions, doing the mode unset, fixing interrupts, etc.
6553 */
6554 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6555 bool switch_to_fclk, bool allow_power_down)
6556 {
6557 uint32_t val;
6558
6559 assert_can_disable_lcpll(dev_priv);
6560
6561 val = I915_READ(LCPLL_CTL);
6562
6563 if (switch_to_fclk) {
6564 val |= LCPLL_CD_SOURCE_FCLK;
6565 I915_WRITE(LCPLL_CTL, val);
6566
6567 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6568 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6569 DRM_ERROR("Switching to FCLK failed\n");
6570
6571 val = I915_READ(LCPLL_CTL);
6572 }
6573
6574 val |= LCPLL_PLL_DISABLE;
6575 I915_WRITE(LCPLL_CTL, val);
6576 POSTING_READ(LCPLL_CTL);
6577
6578 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6579 DRM_ERROR("LCPLL still locked\n");
6580
6581 val = I915_READ(D_COMP);
6582 val |= D_COMP_COMP_DISABLE;
6583 mutex_lock(&dev_priv->rps.hw_lock);
6584 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6585 DRM_ERROR("Failed to disable D_COMP\n");
6586 mutex_unlock(&dev_priv->rps.hw_lock);
6587 POSTING_READ(D_COMP);
6588 ndelay(100);
6589
6590 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6591 DRM_ERROR("D_COMP RCOMP still in progress\n");
6592
6593 if (allow_power_down) {
6594 val = I915_READ(LCPLL_CTL);
6595 val |= LCPLL_POWER_DOWN_ALLOW;
6596 I915_WRITE(LCPLL_CTL, val);
6597 POSTING_READ(LCPLL_CTL);
6598 }
6599 }
6600
6601 /*
6602 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6603 * source.
6604 */
6605 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6606 {
6607 uint32_t val;
6608
6609 val = I915_READ(LCPLL_CTL);
6610
6611 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6612 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6613 return;
6614
6615 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6616 * we'll hang the machine! */
6617 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6618
6619 if (val & LCPLL_POWER_DOWN_ALLOW) {
6620 val &= ~LCPLL_POWER_DOWN_ALLOW;
6621 I915_WRITE(LCPLL_CTL, val);
6622 POSTING_READ(LCPLL_CTL);
6623 }
6624
6625 val = I915_READ(D_COMP);
6626 val |= D_COMP_COMP_FORCE;
6627 val &= ~D_COMP_COMP_DISABLE;
6628 mutex_lock(&dev_priv->rps.hw_lock);
6629 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6630 DRM_ERROR("Failed to enable D_COMP\n");
6631 mutex_unlock(&dev_priv->rps.hw_lock);
6632 POSTING_READ(D_COMP);
6633
6634 val = I915_READ(LCPLL_CTL);
6635 val &= ~LCPLL_PLL_DISABLE;
6636 I915_WRITE(LCPLL_CTL, val);
6637
6638 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6639 DRM_ERROR("LCPLL not locked yet\n");
6640
6641 if (val & LCPLL_CD_SOURCE_FCLK) {
6642 val = I915_READ(LCPLL_CTL);
6643 val &= ~LCPLL_CD_SOURCE_FCLK;
6644 I915_WRITE(LCPLL_CTL, val);
6645
6646 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6647 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6648 DRM_ERROR("Switching back to LCPLL failed\n");
6649 }
6650
6651 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6652 }
6653
6654 void hsw_enable_pc8_work(struct work_struct *__work)
6655 {
6656 struct drm_i915_private *dev_priv =
6657 container_of(to_delayed_work(__work), struct drm_i915_private,
6658 pc8.enable_work);
6659 struct drm_device *dev = dev_priv->dev;
6660 uint32_t val;
6661
6662 WARN_ON(!HAS_PC8(dev));
6663
6664 if (dev_priv->pc8.enabled)
6665 return;
6666
6667 DRM_DEBUG_KMS("Enabling package C8+\n");
6668
6669 dev_priv->pc8.enabled = true;
6670
6671 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6672 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6673 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6674 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6675 }
6676
6677 lpt_disable_clkout_dp(dev);
6678 hsw_pc8_disable_interrupts(dev);
6679 hsw_disable_lcpll(dev_priv, true, true);
6680
6681 intel_runtime_pm_put(dev_priv);
6682 }
6683
6684 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6685 {
6686 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6687 WARN(dev_priv->pc8.disable_count < 1,
6688 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6689
6690 dev_priv->pc8.disable_count--;
6691 if (dev_priv->pc8.disable_count != 0)
6692 return;
6693
6694 schedule_delayed_work(&dev_priv->pc8.enable_work,
6695 msecs_to_jiffies(i915.pc8_timeout));
6696 }
6697
6698 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6699 {
6700 struct drm_device *dev = dev_priv->dev;
6701 uint32_t val;
6702
6703 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6704 WARN(dev_priv->pc8.disable_count < 0,
6705 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6706
6707 dev_priv->pc8.disable_count++;
6708 if (dev_priv->pc8.disable_count != 1)
6709 return;
6710
6711 WARN_ON(!HAS_PC8(dev));
6712
6713 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6714 if (!dev_priv->pc8.enabled)
6715 return;
6716
6717 DRM_DEBUG_KMS("Disabling package C8+\n");
6718
6719 intel_runtime_pm_get(dev_priv);
6720
6721 hsw_restore_lcpll(dev_priv);
6722 hsw_pc8_restore_interrupts(dev);
6723 lpt_init_pch_refclk(dev);
6724
6725 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6726 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6727 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6728 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6729 }
6730
6731 intel_prepare_ddi(dev);
6732 i915_gem_init_swizzling(dev);
6733 mutex_lock(&dev_priv->rps.hw_lock);
6734 gen6_update_ring_freq(dev);
6735 mutex_unlock(&dev_priv->rps.hw_lock);
6736 dev_priv->pc8.enabled = false;
6737 }
6738
6739 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6740 {
6741 if (!HAS_PC8(dev_priv->dev))
6742 return;
6743
6744 mutex_lock(&dev_priv->pc8.lock);
6745 __hsw_enable_package_c8(dev_priv);
6746 mutex_unlock(&dev_priv->pc8.lock);
6747 }
6748
6749 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6750 {
6751 if (!HAS_PC8(dev_priv->dev))
6752 return;
6753
6754 mutex_lock(&dev_priv->pc8.lock);
6755 __hsw_disable_package_c8(dev_priv);
6756 mutex_unlock(&dev_priv->pc8.lock);
6757 }
6758
6759 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6760 {
6761 struct drm_device *dev = dev_priv->dev;
6762 struct intel_crtc *crtc;
6763 uint32_t val;
6764
6765 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6766 if (crtc->base.enabled)
6767 return false;
6768
6769 /* This case is still possible since we have the i915.disable_power_well
6770 * parameter and also the KVMr or something else might be requesting the
6771 * power well. */
6772 val = I915_READ(HSW_PWR_WELL_DRIVER);
6773 if (val != 0) {
6774 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6775 return false;
6776 }
6777
6778 return true;
6779 }
6780
6781 /* Since we're called from modeset_global_resources there's no way to
6782 * symmetrically increase and decrease the refcount, so we use
6783 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6784 * or not.
6785 */
6786 static void hsw_update_package_c8(struct drm_device *dev)
6787 {
6788 struct drm_i915_private *dev_priv = dev->dev_private;
6789 bool allow;
6790
6791 if (!HAS_PC8(dev_priv->dev))
6792 return;
6793
6794 if (!i915.enable_pc8)
6795 return;
6796
6797 mutex_lock(&dev_priv->pc8.lock);
6798
6799 allow = hsw_can_enable_package_c8(dev_priv);
6800
6801 if (allow == dev_priv->pc8.requirements_met)
6802 goto done;
6803
6804 dev_priv->pc8.requirements_met = allow;
6805
6806 if (allow)
6807 __hsw_enable_package_c8(dev_priv);
6808 else
6809 __hsw_disable_package_c8(dev_priv);
6810
6811 done:
6812 mutex_unlock(&dev_priv->pc8.lock);
6813 }
6814
6815 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6816 {
6817 if (!HAS_PC8(dev_priv->dev))
6818 return;
6819
6820 mutex_lock(&dev_priv->pc8.lock);
6821 if (!dev_priv->pc8.gpu_idle) {
6822 dev_priv->pc8.gpu_idle = true;
6823 __hsw_enable_package_c8(dev_priv);
6824 }
6825 mutex_unlock(&dev_priv->pc8.lock);
6826 }
6827
6828 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6829 {
6830 if (!HAS_PC8(dev_priv->dev))
6831 return;
6832
6833 mutex_lock(&dev_priv->pc8.lock);
6834 if (dev_priv->pc8.gpu_idle) {
6835 dev_priv->pc8.gpu_idle = false;
6836 __hsw_disable_package_c8(dev_priv);
6837 }
6838 mutex_unlock(&dev_priv->pc8.lock);
6839 }
6840
6841 #define for_each_power_domain(domain, mask) \
6842 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
6843 if ((1 << (domain)) & (mask))
6844
6845 static unsigned long get_pipe_power_domains(struct drm_device *dev,
6846 enum pipe pipe, bool pfit_enabled)
6847 {
6848 unsigned long mask;
6849 enum transcoder transcoder;
6850
6851 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
6852
6853 mask = BIT(POWER_DOMAIN_PIPE(pipe));
6854 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6855 if (pfit_enabled)
6856 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6857
6858 return mask;
6859 }
6860
6861 void intel_display_set_init_power(struct drm_device *dev, bool enable)
6862 {
6863 struct drm_i915_private *dev_priv = dev->dev_private;
6864
6865 if (dev_priv->power_domains.init_power_on == enable)
6866 return;
6867
6868 if (enable)
6869 intel_display_power_get(dev, POWER_DOMAIN_INIT);
6870 else
6871 intel_display_power_put(dev, POWER_DOMAIN_INIT);
6872
6873 dev_priv->power_domains.init_power_on = enable;
6874 }
6875
6876 static void modeset_update_power_wells(struct drm_device *dev)
6877 {
6878 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
6879 struct intel_crtc *crtc;
6880
6881 /*
6882 * First get all needed power domains, then put all unneeded, to avoid
6883 * any unnecessary toggling of the power wells.
6884 */
6885 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6886 enum intel_display_power_domain domain;
6887
6888 if (!crtc->base.enabled)
6889 continue;
6890
6891 pipe_domains[crtc->pipe] = get_pipe_power_domains(dev,
6892 crtc->pipe,
6893 crtc->config.pch_pfit.enabled);
6894
6895 for_each_power_domain(domain, pipe_domains[crtc->pipe])
6896 intel_display_power_get(dev, domain);
6897 }
6898
6899 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6900 enum intel_display_power_domain domain;
6901
6902 for_each_power_domain(domain, crtc->enabled_power_domains)
6903 intel_display_power_put(dev, domain);
6904
6905 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
6906 }
6907
6908 intel_display_set_init_power(dev, false);
6909 }
6910
6911 static void haswell_modeset_global_resources(struct drm_device *dev)
6912 {
6913 modeset_update_power_wells(dev);
6914 hsw_update_package_c8(dev);
6915 }
6916
6917 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6918 int x, int y,
6919 struct drm_framebuffer *fb)
6920 {
6921 struct drm_device *dev = crtc->dev;
6922 struct drm_i915_private *dev_priv = dev->dev_private;
6923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6924 int plane = intel_crtc->plane;
6925 int ret;
6926
6927 if (!intel_ddi_pll_select(intel_crtc))
6928 return -EINVAL;
6929 intel_ddi_pll_enable(intel_crtc);
6930
6931 if (intel_crtc->config.has_dp_encoder)
6932 intel_dp_set_m_n(intel_crtc);
6933
6934 intel_crtc->lowfreq_avail = false;
6935
6936 intel_set_pipe_timings(intel_crtc);
6937
6938 if (intel_crtc->config.has_pch_encoder) {
6939 intel_cpu_transcoder_set_m_n(intel_crtc,
6940 &intel_crtc->config.fdi_m_n);
6941 }
6942
6943 haswell_set_pipeconf(crtc);
6944
6945 intel_set_pipe_csc(crtc);
6946
6947 /* Set up the display plane register */
6948 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6949 POSTING_READ(DSPCNTR(plane));
6950
6951 ret = intel_pipe_set_base(crtc, x, y, fb);
6952
6953 return ret;
6954 }
6955
6956 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6957 struct intel_crtc_config *pipe_config)
6958 {
6959 struct drm_device *dev = crtc->base.dev;
6960 struct drm_i915_private *dev_priv = dev->dev_private;
6961 enum intel_display_power_domain pfit_domain;
6962 uint32_t tmp;
6963
6964 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6965 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6966
6967 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6968 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6969 enum pipe trans_edp_pipe;
6970 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6971 default:
6972 WARN(1, "unknown pipe linked to edp transcoder\n");
6973 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6974 case TRANS_DDI_EDP_INPUT_A_ON:
6975 trans_edp_pipe = PIPE_A;
6976 break;
6977 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6978 trans_edp_pipe = PIPE_B;
6979 break;
6980 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6981 trans_edp_pipe = PIPE_C;
6982 break;
6983 }
6984
6985 if (trans_edp_pipe == crtc->pipe)
6986 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6987 }
6988
6989 if (!intel_display_power_enabled(dev,
6990 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6991 return false;
6992
6993 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6994 if (!(tmp & PIPECONF_ENABLE))
6995 return false;
6996
6997 /*
6998 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6999 * DDI E. So just check whether this pipe is wired to DDI E and whether
7000 * the PCH transcoder is on.
7001 */
7002 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7003 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7004 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7005 pipe_config->has_pch_encoder = true;
7006
7007 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7008 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7009 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7010
7011 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7012 }
7013
7014 intel_get_pipe_timings(crtc, pipe_config);
7015
7016 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7017 if (intel_display_power_enabled(dev, pfit_domain))
7018 ironlake_get_pfit_config(crtc, pipe_config);
7019
7020 if (IS_HASWELL(dev))
7021 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7022 (I915_READ(IPS_CTL) & IPS_ENABLE);
7023
7024 pipe_config->pixel_multiplier = 1;
7025
7026 return true;
7027 }
7028
7029 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7030 int x, int y,
7031 struct drm_framebuffer *fb)
7032 {
7033 struct drm_device *dev = crtc->dev;
7034 struct drm_i915_private *dev_priv = dev->dev_private;
7035 struct intel_encoder *encoder;
7036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7037 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7038 int pipe = intel_crtc->pipe;
7039 int ret;
7040
7041 drm_vblank_pre_modeset(dev, pipe);
7042
7043 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7044
7045 drm_vblank_post_modeset(dev, pipe);
7046
7047 if (ret != 0)
7048 return ret;
7049
7050 for_each_encoder_on_crtc(dev, crtc, encoder) {
7051 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7052 encoder->base.base.id,
7053 drm_get_encoder_name(&encoder->base),
7054 mode->base.id, mode->name);
7055 encoder->mode_set(encoder);
7056 }
7057
7058 return 0;
7059 }
7060
7061 static struct {
7062 int clock;
7063 u32 config;
7064 } hdmi_audio_clock[] = {
7065 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7066 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7067 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7068 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7069 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7070 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7071 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7072 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7073 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7074 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7075 };
7076
7077 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7078 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7079 {
7080 int i;
7081
7082 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7083 if (mode->clock == hdmi_audio_clock[i].clock)
7084 break;
7085 }
7086
7087 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7088 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7089 i = 1;
7090 }
7091
7092 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7093 hdmi_audio_clock[i].clock,
7094 hdmi_audio_clock[i].config);
7095
7096 return hdmi_audio_clock[i].config;
7097 }
7098
7099 static bool intel_eld_uptodate(struct drm_connector *connector,
7100 int reg_eldv, uint32_t bits_eldv,
7101 int reg_elda, uint32_t bits_elda,
7102 int reg_edid)
7103 {
7104 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7105 uint8_t *eld = connector->eld;
7106 uint32_t i;
7107
7108 i = I915_READ(reg_eldv);
7109 i &= bits_eldv;
7110
7111 if (!eld[0])
7112 return !i;
7113
7114 if (!i)
7115 return false;
7116
7117 i = I915_READ(reg_elda);
7118 i &= ~bits_elda;
7119 I915_WRITE(reg_elda, i);
7120
7121 for (i = 0; i < eld[2]; i++)
7122 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7123 return false;
7124
7125 return true;
7126 }
7127
7128 static void g4x_write_eld(struct drm_connector *connector,
7129 struct drm_crtc *crtc,
7130 struct drm_display_mode *mode)
7131 {
7132 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7133 uint8_t *eld = connector->eld;
7134 uint32_t eldv;
7135 uint32_t len;
7136 uint32_t i;
7137
7138 i = I915_READ(G4X_AUD_VID_DID);
7139
7140 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7141 eldv = G4X_ELDV_DEVCL_DEVBLC;
7142 else
7143 eldv = G4X_ELDV_DEVCTG;
7144
7145 if (intel_eld_uptodate(connector,
7146 G4X_AUD_CNTL_ST, eldv,
7147 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7148 G4X_HDMIW_HDMIEDID))
7149 return;
7150
7151 i = I915_READ(G4X_AUD_CNTL_ST);
7152 i &= ~(eldv | G4X_ELD_ADDR);
7153 len = (i >> 9) & 0x1f; /* ELD buffer size */
7154 I915_WRITE(G4X_AUD_CNTL_ST, i);
7155
7156 if (!eld[0])
7157 return;
7158
7159 len = min_t(uint8_t, eld[2], len);
7160 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7161 for (i = 0; i < len; i++)
7162 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7163
7164 i = I915_READ(G4X_AUD_CNTL_ST);
7165 i |= eldv;
7166 I915_WRITE(G4X_AUD_CNTL_ST, i);
7167 }
7168
7169 static void haswell_write_eld(struct drm_connector *connector,
7170 struct drm_crtc *crtc,
7171 struct drm_display_mode *mode)
7172 {
7173 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7174 uint8_t *eld = connector->eld;
7175 struct drm_device *dev = crtc->dev;
7176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7177 uint32_t eldv;
7178 uint32_t i;
7179 int len;
7180 int pipe = to_intel_crtc(crtc)->pipe;
7181 int tmp;
7182
7183 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7184 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7185 int aud_config = HSW_AUD_CFG(pipe);
7186 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7187
7188
7189 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
7190
7191 /* Audio output enable */
7192 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7193 tmp = I915_READ(aud_cntrl_st2);
7194 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7195 I915_WRITE(aud_cntrl_st2, tmp);
7196
7197 /* Wait for 1 vertical blank */
7198 intel_wait_for_vblank(dev, pipe);
7199
7200 /* Set ELD valid state */
7201 tmp = I915_READ(aud_cntrl_st2);
7202 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7203 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7204 I915_WRITE(aud_cntrl_st2, tmp);
7205 tmp = I915_READ(aud_cntrl_st2);
7206 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7207
7208 /* Enable HDMI mode */
7209 tmp = I915_READ(aud_config);
7210 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7211 /* clear N_programing_enable and N_value_index */
7212 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7213 I915_WRITE(aud_config, tmp);
7214
7215 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7216
7217 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7218 intel_crtc->eld_vld = true;
7219
7220 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7221 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7222 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7223 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7224 } else {
7225 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7226 }
7227
7228 if (intel_eld_uptodate(connector,
7229 aud_cntrl_st2, eldv,
7230 aud_cntl_st, IBX_ELD_ADDRESS,
7231 hdmiw_hdmiedid))
7232 return;
7233
7234 i = I915_READ(aud_cntrl_st2);
7235 i &= ~eldv;
7236 I915_WRITE(aud_cntrl_st2, i);
7237
7238 if (!eld[0])
7239 return;
7240
7241 i = I915_READ(aud_cntl_st);
7242 i &= ~IBX_ELD_ADDRESS;
7243 I915_WRITE(aud_cntl_st, i);
7244 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7245 DRM_DEBUG_DRIVER("port num:%d\n", i);
7246
7247 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7248 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7249 for (i = 0; i < len; i++)
7250 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7251
7252 i = I915_READ(aud_cntrl_st2);
7253 i |= eldv;
7254 I915_WRITE(aud_cntrl_st2, i);
7255
7256 }
7257
7258 static void ironlake_write_eld(struct drm_connector *connector,
7259 struct drm_crtc *crtc,
7260 struct drm_display_mode *mode)
7261 {
7262 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7263 uint8_t *eld = connector->eld;
7264 uint32_t eldv;
7265 uint32_t i;
7266 int len;
7267 int hdmiw_hdmiedid;
7268 int aud_config;
7269 int aud_cntl_st;
7270 int aud_cntrl_st2;
7271 int pipe = to_intel_crtc(crtc)->pipe;
7272
7273 if (HAS_PCH_IBX(connector->dev)) {
7274 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7275 aud_config = IBX_AUD_CFG(pipe);
7276 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7277 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7278 } else if (IS_VALLEYVIEW(connector->dev)) {
7279 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7280 aud_config = VLV_AUD_CFG(pipe);
7281 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7282 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7283 } else {
7284 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7285 aud_config = CPT_AUD_CFG(pipe);
7286 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7287 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7288 }
7289
7290 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7291
7292 if (IS_VALLEYVIEW(connector->dev)) {
7293 struct intel_encoder *intel_encoder;
7294 struct intel_digital_port *intel_dig_port;
7295
7296 intel_encoder = intel_attached_encoder(connector);
7297 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7298 i = intel_dig_port->port;
7299 } else {
7300 i = I915_READ(aud_cntl_st);
7301 i = (i >> 29) & DIP_PORT_SEL_MASK;
7302 /* DIP_Port_Select, 0x1 = PortB */
7303 }
7304
7305 if (!i) {
7306 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7307 /* operate blindly on all ports */
7308 eldv = IBX_ELD_VALIDB;
7309 eldv |= IBX_ELD_VALIDB << 4;
7310 eldv |= IBX_ELD_VALIDB << 8;
7311 } else {
7312 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7313 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7314 }
7315
7316 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7317 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7318 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7319 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7320 } else {
7321 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7322 }
7323
7324 if (intel_eld_uptodate(connector,
7325 aud_cntrl_st2, eldv,
7326 aud_cntl_st, IBX_ELD_ADDRESS,
7327 hdmiw_hdmiedid))
7328 return;
7329
7330 i = I915_READ(aud_cntrl_st2);
7331 i &= ~eldv;
7332 I915_WRITE(aud_cntrl_st2, i);
7333
7334 if (!eld[0])
7335 return;
7336
7337 i = I915_READ(aud_cntl_st);
7338 i &= ~IBX_ELD_ADDRESS;
7339 I915_WRITE(aud_cntl_st, i);
7340
7341 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7342 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7343 for (i = 0; i < len; i++)
7344 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7345
7346 i = I915_READ(aud_cntrl_st2);
7347 i |= eldv;
7348 I915_WRITE(aud_cntrl_st2, i);
7349 }
7350
7351 void intel_write_eld(struct drm_encoder *encoder,
7352 struct drm_display_mode *mode)
7353 {
7354 struct drm_crtc *crtc = encoder->crtc;
7355 struct drm_connector *connector;
7356 struct drm_device *dev = encoder->dev;
7357 struct drm_i915_private *dev_priv = dev->dev_private;
7358
7359 connector = drm_select_eld(encoder, mode);
7360 if (!connector)
7361 return;
7362
7363 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7364 connector->base.id,
7365 drm_get_connector_name(connector),
7366 connector->encoder->base.id,
7367 drm_get_encoder_name(connector->encoder));
7368
7369 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7370
7371 if (dev_priv->display.write_eld)
7372 dev_priv->display.write_eld(connector, crtc, mode);
7373 }
7374
7375 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7376 {
7377 struct drm_device *dev = crtc->dev;
7378 struct drm_i915_private *dev_priv = dev->dev_private;
7379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7380 bool visible = base != 0;
7381 u32 cntl;
7382
7383 if (intel_crtc->cursor_visible == visible)
7384 return;
7385
7386 cntl = I915_READ(_CURACNTR);
7387 if (visible) {
7388 /* On these chipsets we can only modify the base whilst
7389 * the cursor is disabled.
7390 */
7391 I915_WRITE(_CURABASE, base);
7392
7393 cntl &= ~(CURSOR_FORMAT_MASK);
7394 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7395 cntl |= CURSOR_ENABLE |
7396 CURSOR_GAMMA_ENABLE |
7397 CURSOR_FORMAT_ARGB;
7398 } else
7399 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7400 I915_WRITE(_CURACNTR, cntl);
7401
7402 intel_crtc->cursor_visible = visible;
7403 }
7404
7405 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7406 {
7407 struct drm_device *dev = crtc->dev;
7408 struct drm_i915_private *dev_priv = dev->dev_private;
7409 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7410 int pipe = intel_crtc->pipe;
7411 bool visible = base != 0;
7412
7413 if (intel_crtc->cursor_visible != visible) {
7414 uint32_t cntl = I915_READ(CURCNTR(pipe));
7415 if (base) {
7416 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7417 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7418 cntl |= pipe << 28; /* Connect to correct pipe */
7419 } else {
7420 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7421 cntl |= CURSOR_MODE_DISABLE;
7422 }
7423 I915_WRITE(CURCNTR(pipe), cntl);
7424
7425 intel_crtc->cursor_visible = visible;
7426 }
7427 /* and commit changes on next vblank */
7428 POSTING_READ(CURCNTR(pipe));
7429 I915_WRITE(CURBASE(pipe), base);
7430 POSTING_READ(CURBASE(pipe));
7431 }
7432
7433 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7434 {
7435 struct drm_device *dev = crtc->dev;
7436 struct drm_i915_private *dev_priv = dev->dev_private;
7437 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7438 int pipe = intel_crtc->pipe;
7439 bool visible = base != 0;
7440
7441 if (intel_crtc->cursor_visible != visible) {
7442 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7443 if (base) {
7444 cntl &= ~CURSOR_MODE;
7445 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7446 } else {
7447 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7448 cntl |= CURSOR_MODE_DISABLE;
7449 }
7450 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7451 cntl |= CURSOR_PIPE_CSC_ENABLE;
7452 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7453 }
7454 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7455
7456 intel_crtc->cursor_visible = visible;
7457 }
7458 /* and commit changes on next vblank */
7459 POSTING_READ(CURCNTR_IVB(pipe));
7460 I915_WRITE(CURBASE_IVB(pipe), base);
7461 POSTING_READ(CURBASE_IVB(pipe));
7462 }
7463
7464 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7465 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7466 bool on)
7467 {
7468 struct drm_device *dev = crtc->dev;
7469 struct drm_i915_private *dev_priv = dev->dev_private;
7470 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7471 int pipe = intel_crtc->pipe;
7472 int x = intel_crtc->cursor_x;
7473 int y = intel_crtc->cursor_y;
7474 u32 base = 0, pos = 0;
7475 bool visible;
7476
7477 if (on)
7478 base = intel_crtc->cursor_addr;
7479
7480 if (x >= intel_crtc->config.pipe_src_w)
7481 base = 0;
7482
7483 if (y >= intel_crtc->config.pipe_src_h)
7484 base = 0;
7485
7486 if (x < 0) {
7487 if (x + intel_crtc->cursor_width <= 0)
7488 base = 0;
7489
7490 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7491 x = -x;
7492 }
7493 pos |= x << CURSOR_X_SHIFT;
7494
7495 if (y < 0) {
7496 if (y + intel_crtc->cursor_height <= 0)
7497 base = 0;
7498
7499 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7500 y = -y;
7501 }
7502 pos |= y << CURSOR_Y_SHIFT;
7503
7504 visible = base != 0;
7505 if (!visible && !intel_crtc->cursor_visible)
7506 return;
7507
7508 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7509 I915_WRITE(CURPOS_IVB(pipe), pos);
7510 ivb_update_cursor(crtc, base);
7511 } else {
7512 I915_WRITE(CURPOS(pipe), pos);
7513 if (IS_845G(dev) || IS_I865G(dev))
7514 i845_update_cursor(crtc, base);
7515 else
7516 i9xx_update_cursor(crtc, base);
7517 }
7518 }
7519
7520 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7521 struct drm_file *file,
7522 uint32_t handle,
7523 uint32_t width, uint32_t height)
7524 {
7525 struct drm_device *dev = crtc->dev;
7526 struct drm_i915_private *dev_priv = dev->dev_private;
7527 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7528 struct drm_i915_gem_object *obj;
7529 uint32_t addr;
7530 int ret;
7531
7532 /* if we want to turn off the cursor ignore width and height */
7533 if (!handle) {
7534 DRM_DEBUG_KMS("cursor off\n");
7535 addr = 0;
7536 obj = NULL;
7537 mutex_lock(&dev->struct_mutex);
7538 goto finish;
7539 }
7540
7541 /* Currently we only support 64x64 cursors */
7542 if (width != 64 || height != 64) {
7543 DRM_ERROR("we currently only support 64x64 cursors\n");
7544 return -EINVAL;
7545 }
7546
7547 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7548 if (&obj->base == NULL)
7549 return -ENOENT;
7550
7551 if (obj->base.size < width * height * 4) {
7552 DRM_ERROR("buffer is to small\n");
7553 ret = -ENOMEM;
7554 goto fail;
7555 }
7556
7557 /* we only need to pin inside GTT if cursor is non-phy */
7558 mutex_lock(&dev->struct_mutex);
7559 if (!INTEL_INFO(dev)->cursor_needs_physical) {
7560 unsigned alignment;
7561
7562 if (obj->tiling_mode) {
7563 DRM_ERROR("cursor cannot be tiled\n");
7564 ret = -EINVAL;
7565 goto fail_locked;
7566 }
7567
7568 /* Note that the w/a also requires 2 PTE of padding following
7569 * the bo. We currently fill all unused PTE with the shadow
7570 * page and so we should always have valid PTE following the
7571 * cursor preventing the VT-d warning.
7572 */
7573 alignment = 0;
7574 if (need_vtd_wa(dev))
7575 alignment = 64*1024;
7576
7577 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7578 if (ret) {
7579 DRM_ERROR("failed to move cursor bo into the GTT\n");
7580 goto fail_locked;
7581 }
7582
7583 ret = i915_gem_object_put_fence(obj);
7584 if (ret) {
7585 DRM_ERROR("failed to release fence for cursor");
7586 goto fail_unpin;
7587 }
7588
7589 addr = i915_gem_obj_ggtt_offset(obj);
7590 } else {
7591 int align = IS_I830(dev) ? 16 * 1024 : 256;
7592 ret = i915_gem_attach_phys_object(dev, obj,
7593 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7594 align);
7595 if (ret) {
7596 DRM_ERROR("failed to attach phys object\n");
7597 goto fail_locked;
7598 }
7599 addr = obj->phys_obj->handle->busaddr;
7600 }
7601
7602 if (IS_GEN2(dev))
7603 I915_WRITE(CURSIZE, (height << 12) | width);
7604
7605 finish:
7606 if (intel_crtc->cursor_bo) {
7607 if (INTEL_INFO(dev)->cursor_needs_physical) {
7608 if (intel_crtc->cursor_bo != obj)
7609 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7610 } else
7611 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7612 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7613 }
7614
7615 mutex_unlock(&dev->struct_mutex);
7616
7617 intel_crtc->cursor_addr = addr;
7618 intel_crtc->cursor_bo = obj;
7619 intel_crtc->cursor_width = width;
7620 intel_crtc->cursor_height = height;
7621
7622 if (intel_crtc->active)
7623 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7624
7625 return 0;
7626 fail_unpin:
7627 i915_gem_object_unpin_from_display_plane(obj);
7628 fail_locked:
7629 mutex_unlock(&dev->struct_mutex);
7630 fail:
7631 drm_gem_object_unreference_unlocked(&obj->base);
7632 return ret;
7633 }
7634
7635 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7636 {
7637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7638
7639 intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7640 intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7641
7642 if (intel_crtc->active)
7643 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7644
7645 return 0;
7646 }
7647
7648 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7649 u16 *blue, uint32_t start, uint32_t size)
7650 {
7651 int end = (start + size > 256) ? 256 : start + size, i;
7652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7653
7654 for (i = start; i < end; i++) {
7655 intel_crtc->lut_r[i] = red[i] >> 8;
7656 intel_crtc->lut_g[i] = green[i] >> 8;
7657 intel_crtc->lut_b[i] = blue[i] >> 8;
7658 }
7659
7660 intel_crtc_load_lut(crtc);
7661 }
7662
7663 /* VESA 640x480x72Hz mode to set on the pipe */
7664 static struct drm_display_mode load_detect_mode = {
7665 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7666 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7667 };
7668
7669 struct drm_framebuffer *
7670 __intel_framebuffer_create(struct drm_device *dev,
7671 struct drm_mode_fb_cmd2 *mode_cmd,
7672 struct drm_i915_gem_object *obj)
7673 {
7674 struct intel_framebuffer *intel_fb;
7675 int ret;
7676
7677 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7678 if (!intel_fb) {
7679 drm_gem_object_unreference_unlocked(&obj->base);
7680 return ERR_PTR(-ENOMEM);
7681 }
7682
7683 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7684 if (ret)
7685 goto err;
7686
7687 return &intel_fb->base;
7688 err:
7689 drm_gem_object_unreference_unlocked(&obj->base);
7690 kfree(intel_fb);
7691
7692 return ERR_PTR(ret);
7693 }
7694
7695 struct drm_framebuffer *
7696 intel_framebuffer_create(struct drm_device *dev,
7697 struct drm_mode_fb_cmd2 *mode_cmd,
7698 struct drm_i915_gem_object *obj)
7699 {
7700 struct drm_framebuffer *fb;
7701 int ret;
7702
7703 ret = i915_mutex_lock_interruptible(dev);
7704 if (ret)
7705 return ERR_PTR(ret);
7706 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
7707 mutex_unlock(&dev->struct_mutex);
7708
7709 return fb;
7710 }
7711
7712 static u32
7713 intel_framebuffer_pitch_for_width(int width, int bpp)
7714 {
7715 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7716 return ALIGN(pitch, 64);
7717 }
7718
7719 static u32
7720 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7721 {
7722 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7723 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7724 }
7725
7726 static struct drm_framebuffer *
7727 intel_framebuffer_create_for_mode(struct drm_device *dev,
7728 struct drm_display_mode *mode,
7729 int depth, int bpp)
7730 {
7731 struct drm_i915_gem_object *obj;
7732 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7733
7734 obj = i915_gem_alloc_object(dev,
7735 intel_framebuffer_size_for_mode(mode, bpp));
7736 if (obj == NULL)
7737 return ERR_PTR(-ENOMEM);
7738
7739 mode_cmd.width = mode->hdisplay;
7740 mode_cmd.height = mode->vdisplay;
7741 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7742 bpp);
7743 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7744
7745 return intel_framebuffer_create(dev, &mode_cmd, obj);
7746 }
7747
7748 static struct drm_framebuffer *
7749 mode_fits_in_fbdev(struct drm_device *dev,
7750 struct drm_display_mode *mode)
7751 {
7752 #ifdef CONFIG_DRM_I915_FBDEV
7753 struct drm_i915_private *dev_priv = dev->dev_private;
7754 struct drm_i915_gem_object *obj;
7755 struct drm_framebuffer *fb;
7756
7757 if (!dev_priv->fbdev)
7758 return NULL;
7759
7760 if (!dev_priv->fbdev->fb)
7761 return NULL;
7762
7763 obj = dev_priv->fbdev->fb->obj;
7764 BUG_ON(!obj);
7765
7766 fb = &dev_priv->fbdev->fb->base;
7767 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7768 fb->bits_per_pixel))
7769 return NULL;
7770
7771 if (obj->base.size < mode->vdisplay * fb->pitches[0])
7772 return NULL;
7773
7774 return fb;
7775 #else
7776 return NULL;
7777 #endif
7778 }
7779
7780 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7781 struct drm_display_mode *mode,
7782 struct intel_load_detect_pipe *old)
7783 {
7784 struct intel_crtc *intel_crtc;
7785 struct intel_encoder *intel_encoder =
7786 intel_attached_encoder(connector);
7787 struct drm_crtc *possible_crtc;
7788 struct drm_encoder *encoder = &intel_encoder->base;
7789 struct drm_crtc *crtc = NULL;
7790 struct drm_device *dev = encoder->dev;
7791 struct drm_framebuffer *fb;
7792 int i = -1;
7793
7794 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7795 connector->base.id, drm_get_connector_name(connector),
7796 encoder->base.id, drm_get_encoder_name(encoder));
7797
7798 /*
7799 * Algorithm gets a little messy:
7800 *
7801 * - if the connector already has an assigned crtc, use it (but make
7802 * sure it's on first)
7803 *
7804 * - try to find the first unused crtc that can drive this connector,
7805 * and use that if we find one
7806 */
7807
7808 /* See if we already have a CRTC for this connector */
7809 if (encoder->crtc) {
7810 crtc = encoder->crtc;
7811
7812 mutex_lock(&crtc->mutex);
7813
7814 old->dpms_mode = connector->dpms;
7815 old->load_detect_temp = false;
7816
7817 /* Make sure the crtc and connector are running */
7818 if (connector->dpms != DRM_MODE_DPMS_ON)
7819 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7820
7821 return true;
7822 }
7823
7824 /* Find an unused one (if possible) */
7825 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7826 i++;
7827 if (!(encoder->possible_crtcs & (1 << i)))
7828 continue;
7829 if (!possible_crtc->enabled) {
7830 crtc = possible_crtc;
7831 break;
7832 }
7833 }
7834
7835 /*
7836 * If we didn't find an unused CRTC, don't use any.
7837 */
7838 if (!crtc) {
7839 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7840 return false;
7841 }
7842
7843 mutex_lock(&crtc->mutex);
7844 intel_encoder->new_crtc = to_intel_crtc(crtc);
7845 to_intel_connector(connector)->new_encoder = intel_encoder;
7846
7847 intel_crtc = to_intel_crtc(crtc);
7848 intel_crtc->new_enabled = true;
7849 intel_crtc->new_config = &intel_crtc->config;
7850 old->dpms_mode = connector->dpms;
7851 old->load_detect_temp = true;
7852 old->release_fb = NULL;
7853
7854 if (!mode)
7855 mode = &load_detect_mode;
7856
7857 /* We need a framebuffer large enough to accommodate all accesses
7858 * that the plane may generate whilst we perform load detection.
7859 * We can not rely on the fbcon either being present (we get called
7860 * during its initialisation to detect all boot displays, or it may
7861 * not even exist) or that it is large enough to satisfy the
7862 * requested mode.
7863 */
7864 fb = mode_fits_in_fbdev(dev, mode);
7865 if (fb == NULL) {
7866 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7867 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7868 old->release_fb = fb;
7869 } else
7870 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7871 if (IS_ERR(fb)) {
7872 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7873 goto fail;
7874 }
7875
7876 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7877 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7878 if (old->release_fb)
7879 old->release_fb->funcs->destroy(old->release_fb);
7880 goto fail;
7881 }
7882
7883 /* let the connector get through one full cycle before testing */
7884 intel_wait_for_vblank(dev, intel_crtc->pipe);
7885 return true;
7886
7887 fail:
7888 intel_crtc->new_enabled = crtc->enabled;
7889 if (intel_crtc->new_enabled)
7890 intel_crtc->new_config = &intel_crtc->config;
7891 else
7892 intel_crtc->new_config = NULL;
7893 mutex_unlock(&crtc->mutex);
7894 return false;
7895 }
7896
7897 void intel_release_load_detect_pipe(struct drm_connector *connector,
7898 struct intel_load_detect_pipe *old)
7899 {
7900 struct intel_encoder *intel_encoder =
7901 intel_attached_encoder(connector);
7902 struct drm_encoder *encoder = &intel_encoder->base;
7903 struct drm_crtc *crtc = encoder->crtc;
7904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7905
7906 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7907 connector->base.id, drm_get_connector_name(connector),
7908 encoder->base.id, drm_get_encoder_name(encoder));
7909
7910 if (old->load_detect_temp) {
7911 to_intel_connector(connector)->new_encoder = NULL;
7912 intel_encoder->new_crtc = NULL;
7913 intel_crtc->new_enabled = false;
7914 intel_crtc->new_config = NULL;
7915 intel_set_mode(crtc, NULL, 0, 0, NULL);
7916
7917 if (old->release_fb) {
7918 drm_framebuffer_unregister_private(old->release_fb);
7919 drm_framebuffer_unreference(old->release_fb);
7920 }
7921
7922 mutex_unlock(&crtc->mutex);
7923 return;
7924 }
7925
7926 /* Switch crtc and encoder back off if necessary */
7927 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7928 connector->funcs->dpms(connector, old->dpms_mode);
7929
7930 mutex_unlock(&crtc->mutex);
7931 }
7932
7933 static int i9xx_pll_refclk(struct drm_device *dev,
7934 const struct intel_crtc_config *pipe_config)
7935 {
7936 struct drm_i915_private *dev_priv = dev->dev_private;
7937 u32 dpll = pipe_config->dpll_hw_state.dpll;
7938
7939 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7940 return dev_priv->vbt.lvds_ssc_freq;
7941 else if (HAS_PCH_SPLIT(dev))
7942 return 120000;
7943 else if (!IS_GEN2(dev))
7944 return 96000;
7945 else
7946 return 48000;
7947 }
7948
7949 /* Returns the clock of the currently programmed mode of the given pipe. */
7950 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7951 struct intel_crtc_config *pipe_config)
7952 {
7953 struct drm_device *dev = crtc->base.dev;
7954 struct drm_i915_private *dev_priv = dev->dev_private;
7955 int pipe = pipe_config->cpu_transcoder;
7956 u32 dpll = pipe_config->dpll_hw_state.dpll;
7957 u32 fp;
7958 intel_clock_t clock;
7959 int refclk = i9xx_pll_refclk(dev, pipe_config);
7960
7961 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7962 fp = pipe_config->dpll_hw_state.fp0;
7963 else
7964 fp = pipe_config->dpll_hw_state.fp1;
7965
7966 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7967 if (IS_PINEVIEW(dev)) {
7968 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7969 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7970 } else {
7971 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7972 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7973 }
7974
7975 if (!IS_GEN2(dev)) {
7976 if (IS_PINEVIEW(dev))
7977 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7978 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7979 else
7980 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7981 DPLL_FPA01_P1_POST_DIV_SHIFT);
7982
7983 switch (dpll & DPLL_MODE_MASK) {
7984 case DPLLB_MODE_DAC_SERIAL:
7985 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7986 5 : 10;
7987 break;
7988 case DPLLB_MODE_LVDS:
7989 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7990 7 : 14;
7991 break;
7992 default:
7993 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7994 "mode\n", (int)(dpll & DPLL_MODE_MASK));
7995 return;
7996 }
7997
7998 if (IS_PINEVIEW(dev))
7999 pineview_clock(refclk, &clock);
8000 else
8001 i9xx_clock(refclk, &clock);
8002 } else {
8003 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8004 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8005
8006 if (is_lvds) {
8007 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8008 DPLL_FPA01_P1_POST_DIV_SHIFT);
8009
8010 if (lvds & LVDS_CLKB_POWER_UP)
8011 clock.p2 = 7;
8012 else
8013 clock.p2 = 14;
8014 } else {
8015 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8016 clock.p1 = 2;
8017 else {
8018 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8019 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8020 }
8021 if (dpll & PLL_P2_DIVIDE_BY_4)
8022 clock.p2 = 4;
8023 else
8024 clock.p2 = 2;
8025 }
8026
8027 i9xx_clock(refclk, &clock);
8028 }
8029
8030 /*
8031 * This value includes pixel_multiplier. We will use
8032 * port_clock to compute adjusted_mode.crtc_clock in the
8033 * encoder's get_config() function.
8034 */
8035 pipe_config->port_clock = clock.dot;
8036 }
8037
8038 int intel_dotclock_calculate(int link_freq,
8039 const struct intel_link_m_n *m_n)
8040 {
8041 /*
8042 * The calculation for the data clock is:
8043 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8044 * But we want to avoid losing precison if possible, so:
8045 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8046 *
8047 * and the link clock is simpler:
8048 * link_clock = (m * link_clock) / n
8049 */
8050
8051 if (!m_n->link_n)
8052 return 0;
8053
8054 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8055 }
8056
8057 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8058 struct intel_crtc_config *pipe_config)
8059 {
8060 struct drm_device *dev = crtc->base.dev;
8061
8062 /* read out port_clock from the DPLL */
8063 i9xx_crtc_clock_get(crtc, pipe_config);
8064
8065 /*
8066 * This value does not include pixel_multiplier.
8067 * We will check that port_clock and adjusted_mode.crtc_clock
8068 * agree once we know their relationship in the encoder's
8069 * get_config() function.
8070 */
8071 pipe_config->adjusted_mode.crtc_clock =
8072 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8073 &pipe_config->fdi_m_n);
8074 }
8075
8076 /** Returns the currently programmed mode of the given pipe. */
8077 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8078 struct drm_crtc *crtc)
8079 {
8080 struct drm_i915_private *dev_priv = dev->dev_private;
8081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8082 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8083 struct drm_display_mode *mode;
8084 struct intel_crtc_config pipe_config;
8085 int htot = I915_READ(HTOTAL(cpu_transcoder));
8086 int hsync = I915_READ(HSYNC(cpu_transcoder));
8087 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8088 int vsync = I915_READ(VSYNC(cpu_transcoder));
8089 enum pipe pipe = intel_crtc->pipe;
8090
8091 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8092 if (!mode)
8093 return NULL;
8094
8095 /*
8096 * Construct a pipe_config sufficient for getting the clock info
8097 * back out of crtc_clock_get.
8098 *
8099 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8100 * to use a real value here instead.
8101 */
8102 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8103 pipe_config.pixel_multiplier = 1;
8104 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8105 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8106 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8107 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8108
8109 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8110 mode->hdisplay = (htot & 0xffff) + 1;
8111 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8112 mode->hsync_start = (hsync & 0xffff) + 1;
8113 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8114 mode->vdisplay = (vtot & 0xffff) + 1;
8115 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8116 mode->vsync_start = (vsync & 0xffff) + 1;
8117 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8118
8119 drm_mode_set_name(mode);
8120
8121 return mode;
8122 }
8123
8124 static void intel_increase_pllclock(struct drm_crtc *crtc)
8125 {
8126 struct drm_device *dev = crtc->dev;
8127 drm_i915_private_t *dev_priv = dev->dev_private;
8128 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8129 int pipe = intel_crtc->pipe;
8130 int dpll_reg = DPLL(pipe);
8131 int dpll;
8132
8133 if (HAS_PCH_SPLIT(dev))
8134 return;
8135
8136 if (!dev_priv->lvds_downclock_avail)
8137 return;
8138
8139 dpll = I915_READ(dpll_reg);
8140 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8141 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8142
8143 assert_panel_unlocked(dev_priv, pipe);
8144
8145 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8146 I915_WRITE(dpll_reg, dpll);
8147 intel_wait_for_vblank(dev, pipe);
8148
8149 dpll = I915_READ(dpll_reg);
8150 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8151 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8152 }
8153 }
8154
8155 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8156 {
8157 struct drm_device *dev = crtc->dev;
8158 drm_i915_private_t *dev_priv = dev->dev_private;
8159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8160
8161 if (HAS_PCH_SPLIT(dev))
8162 return;
8163
8164 if (!dev_priv->lvds_downclock_avail)
8165 return;
8166
8167 /*
8168 * Since this is called by a timer, we should never get here in
8169 * the manual case.
8170 */
8171 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8172 int pipe = intel_crtc->pipe;
8173 int dpll_reg = DPLL(pipe);
8174 int dpll;
8175
8176 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8177
8178 assert_panel_unlocked(dev_priv, pipe);
8179
8180 dpll = I915_READ(dpll_reg);
8181 dpll |= DISPLAY_RATE_SELECT_FPA1;
8182 I915_WRITE(dpll_reg, dpll);
8183 intel_wait_for_vblank(dev, pipe);
8184 dpll = I915_READ(dpll_reg);
8185 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8186 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8187 }
8188
8189 }
8190
8191 void intel_mark_busy(struct drm_device *dev)
8192 {
8193 struct drm_i915_private *dev_priv = dev->dev_private;
8194
8195 hsw_package_c8_gpu_busy(dev_priv);
8196 i915_update_gfx_val(dev_priv);
8197 }
8198
8199 void intel_mark_idle(struct drm_device *dev)
8200 {
8201 struct drm_i915_private *dev_priv = dev->dev_private;
8202 struct drm_crtc *crtc;
8203
8204 hsw_package_c8_gpu_idle(dev_priv);
8205
8206 if (!i915.powersave)
8207 return;
8208
8209 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8210 if (!crtc->fb)
8211 continue;
8212
8213 intel_decrease_pllclock(crtc);
8214 }
8215
8216 if (INTEL_INFO(dev)->gen >= 6)
8217 gen6_rps_idle(dev->dev_private);
8218 }
8219
8220 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8221 struct intel_ring_buffer *ring)
8222 {
8223 struct drm_device *dev = obj->base.dev;
8224 struct drm_crtc *crtc;
8225
8226 if (!i915.powersave)
8227 return;
8228
8229 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8230 if (!crtc->fb)
8231 continue;
8232
8233 if (to_intel_framebuffer(crtc->fb)->obj != obj)
8234 continue;
8235
8236 intel_increase_pllclock(crtc);
8237 if (ring && intel_fbc_enabled(dev))
8238 ring->fbc_dirty = true;
8239 }
8240 }
8241
8242 static void intel_crtc_destroy(struct drm_crtc *crtc)
8243 {
8244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8245 struct drm_device *dev = crtc->dev;
8246 struct intel_unpin_work *work;
8247 unsigned long flags;
8248
8249 spin_lock_irqsave(&dev->event_lock, flags);
8250 work = intel_crtc->unpin_work;
8251 intel_crtc->unpin_work = NULL;
8252 spin_unlock_irqrestore(&dev->event_lock, flags);
8253
8254 if (work) {
8255 cancel_work_sync(&work->work);
8256 kfree(work);
8257 }
8258
8259 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8260
8261 drm_crtc_cleanup(crtc);
8262
8263 kfree(intel_crtc);
8264 }
8265
8266 static void intel_unpin_work_fn(struct work_struct *__work)
8267 {
8268 struct intel_unpin_work *work =
8269 container_of(__work, struct intel_unpin_work, work);
8270 struct drm_device *dev = work->crtc->dev;
8271
8272 mutex_lock(&dev->struct_mutex);
8273 intel_unpin_fb_obj(work->old_fb_obj);
8274 drm_gem_object_unreference(&work->pending_flip_obj->base);
8275 drm_gem_object_unreference(&work->old_fb_obj->base);
8276
8277 intel_update_fbc(dev);
8278 mutex_unlock(&dev->struct_mutex);
8279
8280 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8281 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8282
8283 kfree(work);
8284 }
8285
8286 static void do_intel_finish_page_flip(struct drm_device *dev,
8287 struct drm_crtc *crtc)
8288 {
8289 drm_i915_private_t *dev_priv = dev->dev_private;
8290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8291 struct intel_unpin_work *work;
8292 unsigned long flags;
8293
8294 /* Ignore early vblank irqs */
8295 if (intel_crtc == NULL)
8296 return;
8297
8298 spin_lock_irqsave(&dev->event_lock, flags);
8299 work = intel_crtc->unpin_work;
8300
8301 /* Ensure we don't miss a work->pending update ... */
8302 smp_rmb();
8303
8304 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8305 spin_unlock_irqrestore(&dev->event_lock, flags);
8306 return;
8307 }
8308
8309 /* and that the unpin work is consistent wrt ->pending. */
8310 smp_rmb();
8311
8312 intel_crtc->unpin_work = NULL;
8313
8314 if (work->event)
8315 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8316
8317 drm_vblank_put(dev, intel_crtc->pipe);
8318
8319 spin_unlock_irqrestore(&dev->event_lock, flags);
8320
8321 wake_up_all(&dev_priv->pending_flip_queue);
8322
8323 queue_work(dev_priv->wq, &work->work);
8324
8325 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8326 }
8327
8328 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8329 {
8330 drm_i915_private_t *dev_priv = dev->dev_private;
8331 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8332
8333 do_intel_finish_page_flip(dev, crtc);
8334 }
8335
8336 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8337 {
8338 drm_i915_private_t *dev_priv = dev->dev_private;
8339 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8340
8341 do_intel_finish_page_flip(dev, crtc);
8342 }
8343
8344 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8345 {
8346 drm_i915_private_t *dev_priv = dev->dev_private;
8347 struct intel_crtc *intel_crtc =
8348 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8349 unsigned long flags;
8350
8351 /* NB: An MMIO update of the plane base pointer will also
8352 * generate a page-flip completion irq, i.e. every modeset
8353 * is also accompanied by a spurious intel_prepare_page_flip().
8354 */
8355 spin_lock_irqsave(&dev->event_lock, flags);
8356 if (intel_crtc->unpin_work)
8357 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8358 spin_unlock_irqrestore(&dev->event_lock, flags);
8359 }
8360
8361 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8362 {
8363 /* Ensure that the work item is consistent when activating it ... */
8364 smp_wmb();
8365 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8366 /* and that it is marked active as soon as the irq could fire. */
8367 smp_wmb();
8368 }
8369
8370 static int intel_gen2_queue_flip(struct drm_device *dev,
8371 struct drm_crtc *crtc,
8372 struct drm_framebuffer *fb,
8373 struct drm_i915_gem_object *obj,
8374 uint32_t flags)
8375 {
8376 struct drm_i915_private *dev_priv = dev->dev_private;
8377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8378 u32 flip_mask;
8379 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8380 int ret;
8381
8382 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8383 if (ret)
8384 goto err;
8385
8386 ret = intel_ring_begin(ring, 6);
8387 if (ret)
8388 goto err_unpin;
8389
8390 /* Can't queue multiple flips, so wait for the previous
8391 * one to finish before executing the next.
8392 */
8393 if (intel_crtc->plane)
8394 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8395 else
8396 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8397 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8398 intel_ring_emit(ring, MI_NOOP);
8399 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8400 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8401 intel_ring_emit(ring, fb->pitches[0]);
8402 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8403 intel_ring_emit(ring, 0); /* aux display base address, unused */
8404
8405 intel_mark_page_flip_active(intel_crtc);
8406 __intel_ring_advance(ring);
8407 return 0;
8408
8409 err_unpin:
8410 intel_unpin_fb_obj(obj);
8411 err:
8412 return ret;
8413 }
8414
8415 static int intel_gen3_queue_flip(struct drm_device *dev,
8416 struct drm_crtc *crtc,
8417 struct drm_framebuffer *fb,
8418 struct drm_i915_gem_object *obj,
8419 uint32_t flags)
8420 {
8421 struct drm_i915_private *dev_priv = dev->dev_private;
8422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8423 u32 flip_mask;
8424 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8425 int ret;
8426
8427 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8428 if (ret)
8429 goto err;
8430
8431 ret = intel_ring_begin(ring, 6);
8432 if (ret)
8433 goto err_unpin;
8434
8435 if (intel_crtc->plane)
8436 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8437 else
8438 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8439 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8440 intel_ring_emit(ring, MI_NOOP);
8441 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8442 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8443 intel_ring_emit(ring, fb->pitches[0]);
8444 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8445 intel_ring_emit(ring, MI_NOOP);
8446
8447 intel_mark_page_flip_active(intel_crtc);
8448 __intel_ring_advance(ring);
8449 return 0;
8450
8451 err_unpin:
8452 intel_unpin_fb_obj(obj);
8453 err:
8454 return ret;
8455 }
8456
8457 static int intel_gen4_queue_flip(struct drm_device *dev,
8458 struct drm_crtc *crtc,
8459 struct drm_framebuffer *fb,
8460 struct drm_i915_gem_object *obj,
8461 uint32_t flags)
8462 {
8463 struct drm_i915_private *dev_priv = dev->dev_private;
8464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8465 uint32_t pf, pipesrc;
8466 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8467 int ret;
8468
8469 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8470 if (ret)
8471 goto err;
8472
8473 ret = intel_ring_begin(ring, 4);
8474 if (ret)
8475 goto err_unpin;
8476
8477 /* i965+ uses the linear or tiled offsets from the
8478 * Display Registers (which do not change across a page-flip)
8479 * so we need only reprogram the base address.
8480 */
8481 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8482 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8483 intel_ring_emit(ring, fb->pitches[0]);
8484 intel_ring_emit(ring,
8485 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8486 obj->tiling_mode);
8487
8488 /* XXX Enabling the panel-fitter across page-flip is so far
8489 * untested on non-native modes, so ignore it for now.
8490 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8491 */
8492 pf = 0;
8493 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8494 intel_ring_emit(ring, pf | pipesrc);
8495
8496 intel_mark_page_flip_active(intel_crtc);
8497 __intel_ring_advance(ring);
8498 return 0;
8499
8500 err_unpin:
8501 intel_unpin_fb_obj(obj);
8502 err:
8503 return ret;
8504 }
8505
8506 static int intel_gen6_queue_flip(struct drm_device *dev,
8507 struct drm_crtc *crtc,
8508 struct drm_framebuffer *fb,
8509 struct drm_i915_gem_object *obj,
8510 uint32_t flags)
8511 {
8512 struct drm_i915_private *dev_priv = dev->dev_private;
8513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8514 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8515 uint32_t pf, pipesrc;
8516 int ret;
8517
8518 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8519 if (ret)
8520 goto err;
8521
8522 ret = intel_ring_begin(ring, 4);
8523 if (ret)
8524 goto err_unpin;
8525
8526 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8527 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8528 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8529 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8530
8531 /* Contrary to the suggestions in the documentation,
8532 * "Enable Panel Fitter" does not seem to be required when page
8533 * flipping with a non-native mode, and worse causes a normal
8534 * modeset to fail.
8535 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8536 */
8537 pf = 0;
8538 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8539 intel_ring_emit(ring, pf | pipesrc);
8540
8541 intel_mark_page_flip_active(intel_crtc);
8542 __intel_ring_advance(ring);
8543 return 0;
8544
8545 err_unpin:
8546 intel_unpin_fb_obj(obj);
8547 err:
8548 return ret;
8549 }
8550
8551 static int intel_gen7_queue_flip(struct drm_device *dev,
8552 struct drm_crtc *crtc,
8553 struct drm_framebuffer *fb,
8554 struct drm_i915_gem_object *obj,
8555 uint32_t flags)
8556 {
8557 struct drm_i915_private *dev_priv = dev->dev_private;
8558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8559 struct intel_ring_buffer *ring;
8560 uint32_t plane_bit = 0;
8561 int len, ret;
8562
8563 ring = obj->ring;
8564 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8565 ring = &dev_priv->ring[BCS];
8566
8567 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8568 if (ret)
8569 goto err;
8570
8571 switch(intel_crtc->plane) {
8572 case PLANE_A:
8573 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8574 break;
8575 case PLANE_B:
8576 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8577 break;
8578 case PLANE_C:
8579 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8580 break;
8581 default:
8582 WARN_ONCE(1, "unknown plane in flip command\n");
8583 ret = -ENODEV;
8584 goto err_unpin;
8585 }
8586
8587 len = 4;
8588 if (ring->id == RCS)
8589 len += 6;
8590
8591 /*
8592 * BSpec MI_DISPLAY_FLIP for IVB:
8593 * "The full packet must be contained within the same cache line."
8594 *
8595 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
8596 * cacheline, if we ever start emitting more commands before
8597 * the MI_DISPLAY_FLIP we may need to first emit everything else,
8598 * then do the cacheline alignment, and finally emit the
8599 * MI_DISPLAY_FLIP.
8600 */
8601 ret = intel_ring_cacheline_align(ring);
8602 if (ret)
8603 goto err_unpin;
8604
8605 ret = intel_ring_begin(ring, len);
8606 if (ret)
8607 goto err_unpin;
8608
8609 /* Unmask the flip-done completion message. Note that the bspec says that
8610 * we should do this for both the BCS and RCS, and that we must not unmask
8611 * more than one flip event at any time (or ensure that one flip message
8612 * can be sent by waiting for flip-done prior to queueing new flips).
8613 * Experimentation says that BCS works despite DERRMR masking all
8614 * flip-done completion events and that unmasking all planes at once
8615 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8616 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8617 */
8618 if (ring->id == RCS) {
8619 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8620 intel_ring_emit(ring, DERRMR);
8621 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8622 DERRMR_PIPEB_PRI_FLIP_DONE |
8623 DERRMR_PIPEC_PRI_FLIP_DONE));
8624 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
8625 MI_SRM_LRM_GLOBAL_GTT);
8626 intel_ring_emit(ring, DERRMR);
8627 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8628 }
8629
8630 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8631 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8632 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8633 intel_ring_emit(ring, (MI_NOOP));
8634
8635 intel_mark_page_flip_active(intel_crtc);
8636 __intel_ring_advance(ring);
8637 return 0;
8638
8639 err_unpin:
8640 intel_unpin_fb_obj(obj);
8641 err:
8642 return ret;
8643 }
8644
8645 static int intel_default_queue_flip(struct drm_device *dev,
8646 struct drm_crtc *crtc,
8647 struct drm_framebuffer *fb,
8648 struct drm_i915_gem_object *obj,
8649 uint32_t flags)
8650 {
8651 return -ENODEV;
8652 }
8653
8654 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8655 struct drm_framebuffer *fb,
8656 struct drm_pending_vblank_event *event,
8657 uint32_t page_flip_flags)
8658 {
8659 struct drm_device *dev = crtc->dev;
8660 struct drm_i915_private *dev_priv = dev->dev_private;
8661 struct drm_framebuffer *old_fb = crtc->fb;
8662 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8664 struct intel_unpin_work *work;
8665 unsigned long flags;
8666 int ret;
8667
8668 /* Can't change pixel format via MI display flips. */
8669 if (fb->pixel_format != crtc->fb->pixel_format)
8670 return -EINVAL;
8671
8672 /*
8673 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8674 * Note that pitch changes could also affect these register.
8675 */
8676 if (INTEL_INFO(dev)->gen > 3 &&
8677 (fb->offsets[0] != crtc->fb->offsets[0] ||
8678 fb->pitches[0] != crtc->fb->pitches[0]))
8679 return -EINVAL;
8680
8681 work = kzalloc(sizeof(*work), GFP_KERNEL);
8682 if (work == NULL)
8683 return -ENOMEM;
8684
8685 work->event = event;
8686 work->crtc = crtc;
8687 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8688 INIT_WORK(&work->work, intel_unpin_work_fn);
8689
8690 ret = drm_vblank_get(dev, intel_crtc->pipe);
8691 if (ret)
8692 goto free_work;
8693
8694 /* We borrow the event spin lock for protecting unpin_work */
8695 spin_lock_irqsave(&dev->event_lock, flags);
8696 if (intel_crtc->unpin_work) {
8697 spin_unlock_irqrestore(&dev->event_lock, flags);
8698 kfree(work);
8699 drm_vblank_put(dev, intel_crtc->pipe);
8700
8701 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8702 return -EBUSY;
8703 }
8704 intel_crtc->unpin_work = work;
8705 spin_unlock_irqrestore(&dev->event_lock, flags);
8706
8707 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8708 flush_workqueue(dev_priv->wq);
8709
8710 ret = i915_mutex_lock_interruptible(dev);
8711 if (ret)
8712 goto cleanup;
8713
8714 /* Reference the objects for the scheduled work. */
8715 drm_gem_object_reference(&work->old_fb_obj->base);
8716 drm_gem_object_reference(&obj->base);
8717
8718 crtc->fb = fb;
8719
8720 work->pending_flip_obj = obj;
8721
8722 work->enable_stall_check = true;
8723
8724 atomic_inc(&intel_crtc->unpin_work_count);
8725 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8726
8727 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8728 if (ret)
8729 goto cleanup_pending;
8730
8731 intel_disable_fbc(dev);
8732 intel_mark_fb_busy(obj, NULL);
8733 mutex_unlock(&dev->struct_mutex);
8734
8735 trace_i915_flip_request(intel_crtc->plane, obj);
8736
8737 return 0;
8738
8739 cleanup_pending:
8740 atomic_dec(&intel_crtc->unpin_work_count);
8741 crtc->fb = old_fb;
8742 drm_gem_object_unreference(&work->old_fb_obj->base);
8743 drm_gem_object_unreference(&obj->base);
8744 mutex_unlock(&dev->struct_mutex);
8745
8746 cleanup:
8747 spin_lock_irqsave(&dev->event_lock, flags);
8748 intel_crtc->unpin_work = NULL;
8749 spin_unlock_irqrestore(&dev->event_lock, flags);
8750
8751 drm_vblank_put(dev, intel_crtc->pipe);
8752 free_work:
8753 kfree(work);
8754
8755 return ret;
8756 }
8757
8758 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8759 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8760 .load_lut = intel_crtc_load_lut,
8761 };
8762
8763 /**
8764 * intel_modeset_update_staged_output_state
8765 *
8766 * Updates the staged output configuration state, e.g. after we've read out the
8767 * current hw state.
8768 */
8769 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8770 {
8771 struct intel_crtc *crtc;
8772 struct intel_encoder *encoder;
8773 struct intel_connector *connector;
8774
8775 list_for_each_entry(connector, &dev->mode_config.connector_list,
8776 base.head) {
8777 connector->new_encoder =
8778 to_intel_encoder(connector->base.encoder);
8779 }
8780
8781 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8782 base.head) {
8783 encoder->new_crtc =
8784 to_intel_crtc(encoder->base.crtc);
8785 }
8786
8787 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8788 base.head) {
8789 crtc->new_enabled = crtc->base.enabled;
8790
8791 if (crtc->new_enabled)
8792 crtc->new_config = &crtc->config;
8793 else
8794 crtc->new_config = NULL;
8795 }
8796 }
8797
8798 /**
8799 * intel_modeset_commit_output_state
8800 *
8801 * This function copies the stage display pipe configuration to the real one.
8802 */
8803 static void intel_modeset_commit_output_state(struct drm_device *dev)
8804 {
8805 struct intel_crtc *crtc;
8806 struct intel_encoder *encoder;
8807 struct intel_connector *connector;
8808
8809 list_for_each_entry(connector, &dev->mode_config.connector_list,
8810 base.head) {
8811 connector->base.encoder = &connector->new_encoder->base;
8812 }
8813
8814 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8815 base.head) {
8816 encoder->base.crtc = &encoder->new_crtc->base;
8817 }
8818
8819 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8820 base.head) {
8821 crtc->base.enabled = crtc->new_enabled;
8822 }
8823 }
8824
8825 static void
8826 connected_sink_compute_bpp(struct intel_connector * connector,
8827 struct intel_crtc_config *pipe_config)
8828 {
8829 int bpp = pipe_config->pipe_bpp;
8830
8831 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8832 connector->base.base.id,
8833 drm_get_connector_name(&connector->base));
8834
8835 /* Don't use an invalid EDID bpc value */
8836 if (connector->base.display_info.bpc &&
8837 connector->base.display_info.bpc * 3 < bpp) {
8838 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8839 bpp, connector->base.display_info.bpc*3);
8840 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8841 }
8842
8843 /* Clamp bpp to 8 on screens without EDID 1.4 */
8844 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8845 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8846 bpp);
8847 pipe_config->pipe_bpp = 24;
8848 }
8849 }
8850
8851 static int
8852 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8853 struct drm_framebuffer *fb,
8854 struct intel_crtc_config *pipe_config)
8855 {
8856 struct drm_device *dev = crtc->base.dev;
8857 struct intel_connector *connector;
8858 int bpp;
8859
8860 switch (fb->pixel_format) {
8861 case DRM_FORMAT_C8:
8862 bpp = 8*3; /* since we go through a colormap */
8863 break;
8864 case DRM_FORMAT_XRGB1555:
8865 case DRM_FORMAT_ARGB1555:
8866 /* checked in intel_framebuffer_init already */
8867 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8868 return -EINVAL;
8869 case DRM_FORMAT_RGB565:
8870 bpp = 6*3; /* min is 18bpp */
8871 break;
8872 case DRM_FORMAT_XBGR8888:
8873 case DRM_FORMAT_ABGR8888:
8874 /* checked in intel_framebuffer_init already */
8875 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8876 return -EINVAL;
8877 case DRM_FORMAT_XRGB8888:
8878 case DRM_FORMAT_ARGB8888:
8879 bpp = 8*3;
8880 break;
8881 case DRM_FORMAT_XRGB2101010:
8882 case DRM_FORMAT_ARGB2101010:
8883 case DRM_FORMAT_XBGR2101010:
8884 case DRM_FORMAT_ABGR2101010:
8885 /* checked in intel_framebuffer_init already */
8886 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8887 return -EINVAL;
8888 bpp = 10*3;
8889 break;
8890 /* TODO: gen4+ supports 16 bpc floating point, too. */
8891 default:
8892 DRM_DEBUG_KMS("unsupported depth\n");
8893 return -EINVAL;
8894 }
8895
8896 pipe_config->pipe_bpp = bpp;
8897
8898 /* Clamp display bpp to EDID value */
8899 list_for_each_entry(connector, &dev->mode_config.connector_list,
8900 base.head) {
8901 if (!connector->new_encoder ||
8902 connector->new_encoder->new_crtc != crtc)
8903 continue;
8904
8905 connected_sink_compute_bpp(connector, pipe_config);
8906 }
8907
8908 return bpp;
8909 }
8910
8911 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8912 {
8913 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8914 "type: 0x%x flags: 0x%x\n",
8915 mode->crtc_clock,
8916 mode->crtc_hdisplay, mode->crtc_hsync_start,
8917 mode->crtc_hsync_end, mode->crtc_htotal,
8918 mode->crtc_vdisplay, mode->crtc_vsync_start,
8919 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8920 }
8921
8922 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8923 struct intel_crtc_config *pipe_config,
8924 const char *context)
8925 {
8926 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8927 context, pipe_name(crtc->pipe));
8928
8929 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8930 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8931 pipe_config->pipe_bpp, pipe_config->dither);
8932 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8933 pipe_config->has_pch_encoder,
8934 pipe_config->fdi_lanes,
8935 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8936 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8937 pipe_config->fdi_m_n.tu);
8938 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8939 pipe_config->has_dp_encoder,
8940 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8941 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8942 pipe_config->dp_m_n.tu);
8943 DRM_DEBUG_KMS("requested mode:\n");
8944 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8945 DRM_DEBUG_KMS("adjusted mode:\n");
8946 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8947 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
8948 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8949 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8950 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8951 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8952 pipe_config->gmch_pfit.control,
8953 pipe_config->gmch_pfit.pgm_ratios,
8954 pipe_config->gmch_pfit.lvds_border_bits);
8955 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8956 pipe_config->pch_pfit.pos,
8957 pipe_config->pch_pfit.size,
8958 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8959 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8960 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8961 }
8962
8963 static bool check_encoder_cloning(struct drm_crtc *crtc)
8964 {
8965 int num_encoders = 0;
8966 bool uncloneable_encoders = false;
8967 struct intel_encoder *encoder;
8968
8969 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8970 base.head) {
8971 if (&encoder->new_crtc->base != crtc)
8972 continue;
8973
8974 num_encoders++;
8975 if (!encoder->cloneable)
8976 uncloneable_encoders = true;
8977 }
8978
8979 return !(num_encoders > 1 && uncloneable_encoders);
8980 }
8981
8982 static struct intel_crtc_config *
8983 intel_modeset_pipe_config(struct drm_crtc *crtc,
8984 struct drm_framebuffer *fb,
8985 struct drm_display_mode *mode)
8986 {
8987 struct drm_device *dev = crtc->dev;
8988 struct intel_encoder *encoder;
8989 struct intel_crtc_config *pipe_config;
8990 int plane_bpp, ret = -EINVAL;
8991 bool retry = true;
8992
8993 if (!check_encoder_cloning(crtc)) {
8994 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8995 return ERR_PTR(-EINVAL);
8996 }
8997
8998 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8999 if (!pipe_config)
9000 return ERR_PTR(-ENOMEM);
9001
9002 drm_mode_copy(&pipe_config->adjusted_mode, mode);
9003 drm_mode_copy(&pipe_config->requested_mode, mode);
9004
9005 pipe_config->cpu_transcoder =
9006 (enum transcoder) to_intel_crtc(crtc)->pipe;
9007 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9008
9009 /*
9010 * Sanitize sync polarity flags based on requested ones. If neither
9011 * positive or negative polarity is requested, treat this as meaning
9012 * negative polarity.
9013 */
9014 if (!(pipe_config->adjusted_mode.flags &
9015 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9016 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9017
9018 if (!(pipe_config->adjusted_mode.flags &
9019 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9020 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9021
9022 /* Compute a starting value for pipe_config->pipe_bpp taking the source
9023 * plane pixel format and any sink constraints into account. Returns the
9024 * source plane bpp so that dithering can be selected on mismatches
9025 * after encoders and crtc also have had their say. */
9026 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9027 fb, pipe_config);
9028 if (plane_bpp < 0)
9029 goto fail;
9030
9031 /*
9032 * Determine the real pipe dimensions. Note that stereo modes can
9033 * increase the actual pipe size due to the frame doubling and
9034 * insertion of additional space for blanks between the frame. This
9035 * is stored in the crtc timings. We use the requested mode to do this
9036 * computation to clearly distinguish it from the adjusted mode, which
9037 * can be changed by the connectors in the below retry loop.
9038 */
9039 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9040 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9041 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9042
9043 encoder_retry:
9044 /* Ensure the port clock defaults are reset when retrying. */
9045 pipe_config->port_clock = 0;
9046 pipe_config->pixel_multiplier = 1;
9047
9048 /* Fill in default crtc timings, allow encoders to overwrite them. */
9049 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9050
9051 /* Pass our mode to the connectors and the CRTC to give them a chance to
9052 * adjust it according to limitations or connector properties, and also
9053 * a chance to reject the mode entirely.
9054 */
9055 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9056 base.head) {
9057
9058 if (&encoder->new_crtc->base != crtc)
9059 continue;
9060
9061 if (!(encoder->compute_config(encoder, pipe_config))) {
9062 DRM_DEBUG_KMS("Encoder config failure\n");
9063 goto fail;
9064 }
9065 }
9066
9067 /* Set default port clock if not overwritten by the encoder. Needs to be
9068 * done afterwards in case the encoder adjusts the mode. */
9069 if (!pipe_config->port_clock)
9070 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9071 * pipe_config->pixel_multiplier;
9072
9073 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9074 if (ret < 0) {
9075 DRM_DEBUG_KMS("CRTC fixup failed\n");
9076 goto fail;
9077 }
9078
9079 if (ret == RETRY) {
9080 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9081 ret = -EINVAL;
9082 goto fail;
9083 }
9084
9085 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9086 retry = false;
9087 goto encoder_retry;
9088 }
9089
9090 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9091 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9092 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9093
9094 return pipe_config;
9095 fail:
9096 kfree(pipe_config);
9097 return ERR_PTR(ret);
9098 }
9099
9100 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9101 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9102 static void
9103 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9104 unsigned *prepare_pipes, unsigned *disable_pipes)
9105 {
9106 struct intel_crtc *intel_crtc;
9107 struct drm_device *dev = crtc->dev;
9108 struct intel_encoder *encoder;
9109 struct intel_connector *connector;
9110 struct drm_crtc *tmp_crtc;
9111
9112 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9113
9114 /* Check which crtcs have changed outputs connected to them, these need
9115 * to be part of the prepare_pipes mask. We don't (yet) support global
9116 * modeset across multiple crtcs, so modeset_pipes will only have one
9117 * bit set at most. */
9118 list_for_each_entry(connector, &dev->mode_config.connector_list,
9119 base.head) {
9120 if (connector->base.encoder == &connector->new_encoder->base)
9121 continue;
9122
9123 if (connector->base.encoder) {
9124 tmp_crtc = connector->base.encoder->crtc;
9125
9126 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9127 }
9128
9129 if (connector->new_encoder)
9130 *prepare_pipes |=
9131 1 << connector->new_encoder->new_crtc->pipe;
9132 }
9133
9134 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9135 base.head) {
9136 if (encoder->base.crtc == &encoder->new_crtc->base)
9137 continue;
9138
9139 if (encoder->base.crtc) {
9140 tmp_crtc = encoder->base.crtc;
9141
9142 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9143 }
9144
9145 if (encoder->new_crtc)
9146 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9147 }
9148
9149 /* Check for pipes that will be enabled/disabled ... */
9150 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9151 base.head) {
9152 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9153 continue;
9154
9155 if (!intel_crtc->new_enabled)
9156 *disable_pipes |= 1 << intel_crtc->pipe;
9157 else
9158 *prepare_pipes |= 1 << intel_crtc->pipe;
9159 }
9160
9161
9162 /* set_mode is also used to update properties on life display pipes. */
9163 intel_crtc = to_intel_crtc(crtc);
9164 if (intel_crtc->new_enabled)
9165 *prepare_pipes |= 1 << intel_crtc->pipe;
9166
9167 /*
9168 * For simplicity do a full modeset on any pipe where the output routing
9169 * changed. We could be more clever, but that would require us to be
9170 * more careful with calling the relevant encoder->mode_set functions.
9171 */
9172 if (*prepare_pipes)
9173 *modeset_pipes = *prepare_pipes;
9174
9175 /* ... and mask these out. */
9176 *modeset_pipes &= ~(*disable_pipes);
9177 *prepare_pipes &= ~(*disable_pipes);
9178
9179 /*
9180 * HACK: We don't (yet) fully support global modesets. intel_set_config
9181 * obies this rule, but the modeset restore mode of
9182 * intel_modeset_setup_hw_state does not.
9183 */
9184 *modeset_pipes &= 1 << intel_crtc->pipe;
9185 *prepare_pipes &= 1 << intel_crtc->pipe;
9186
9187 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9188 *modeset_pipes, *prepare_pipes, *disable_pipes);
9189 }
9190
9191 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9192 {
9193 struct drm_encoder *encoder;
9194 struct drm_device *dev = crtc->dev;
9195
9196 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9197 if (encoder->crtc == crtc)
9198 return true;
9199
9200 return false;
9201 }
9202
9203 static void
9204 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9205 {
9206 struct intel_encoder *intel_encoder;
9207 struct intel_crtc *intel_crtc;
9208 struct drm_connector *connector;
9209
9210 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9211 base.head) {
9212 if (!intel_encoder->base.crtc)
9213 continue;
9214
9215 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9216
9217 if (prepare_pipes & (1 << intel_crtc->pipe))
9218 intel_encoder->connectors_active = false;
9219 }
9220
9221 intel_modeset_commit_output_state(dev);
9222
9223 /* Double check state. */
9224 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9225 base.head) {
9226 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9227 WARN_ON(intel_crtc->new_config &&
9228 intel_crtc->new_config != &intel_crtc->config);
9229 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9230 }
9231
9232 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9233 if (!connector->encoder || !connector->encoder->crtc)
9234 continue;
9235
9236 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9237
9238 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9239 struct drm_property *dpms_property =
9240 dev->mode_config.dpms_property;
9241
9242 connector->dpms = DRM_MODE_DPMS_ON;
9243 drm_object_property_set_value(&connector->base,
9244 dpms_property,
9245 DRM_MODE_DPMS_ON);
9246
9247 intel_encoder = to_intel_encoder(connector->encoder);
9248 intel_encoder->connectors_active = true;
9249 }
9250 }
9251
9252 }
9253
9254 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9255 {
9256 int diff;
9257
9258 if (clock1 == clock2)
9259 return true;
9260
9261 if (!clock1 || !clock2)
9262 return false;
9263
9264 diff = abs(clock1 - clock2);
9265
9266 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9267 return true;
9268
9269 return false;
9270 }
9271
9272 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9273 list_for_each_entry((intel_crtc), \
9274 &(dev)->mode_config.crtc_list, \
9275 base.head) \
9276 if (mask & (1 <<(intel_crtc)->pipe))
9277
9278 static bool
9279 intel_pipe_config_compare(struct drm_device *dev,
9280 struct intel_crtc_config *current_config,
9281 struct intel_crtc_config *pipe_config)
9282 {
9283 #define PIPE_CONF_CHECK_X(name) \
9284 if (current_config->name != pipe_config->name) { \
9285 DRM_ERROR("mismatch in " #name " " \
9286 "(expected 0x%08x, found 0x%08x)\n", \
9287 current_config->name, \
9288 pipe_config->name); \
9289 return false; \
9290 }
9291
9292 #define PIPE_CONF_CHECK_I(name) \
9293 if (current_config->name != pipe_config->name) { \
9294 DRM_ERROR("mismatch in " #name " " \
9295 "(expected %i, found %i)\n", \
9296 current_config->name, \
9297 pipe_config->name); \
9298 return false; \
9299 }
9300
9301 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
9302 if ((current_config->name ^ pipe_config->name) & (mask)) { \
9303 DRM_ERROR("mismatch in " #name "(" #mask ") " \
9304 "(expected %i, found %i)\n", \
9305 current_config->name & (mask), \
9306 pipe_config->name & (mask)); \
9307 return false; \
9308 }
9309
9310 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9311 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9312 DRM_ERROR("mismatch in " #name " " \
9313 "(expected %i, found %i)\n", \
9314 current_config->name, \
9315 pipe_config->name); \
9316 return false; \
9317 }
9318
9319 #define PIPE_CONF_QUIRK(quirk) \
9320 ((current_config->quirks | pipe_config->quirks) & (quirk))
9321
9322 PIPE_CONF_CHECK_I(cpu_transcoder);
9323
9324 PIPE_CONF_CHECK_I(has_pch_encoder);
9325 PIPE_CONF_CHECK_I(fdi_lanes);
9326 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9327 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9328 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9329 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9330 PIPE_CONF_CHECK_I(fdi_m_n.tu);
9331
9332 PIPE_CONF_CHECK_I(has_dp_encoder);
9333 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9334 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9335 PIPE_CONF_CHECK_I(dp_m_n.link_m);
9336 PIPE_CONF_CHECK_I(dp_m_n.link_n);
9337 PIPE_CONF_CHECK_I(dp_m_n.tu);
9338
9339 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9340 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9341 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9342 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9343 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9344 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9345
9346 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9347 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9348 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9349 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9350 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9351 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9352
9353 PIPE_CONF_CHECK_I(pixel_multiplier);
9354
9355 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9356 DRM_MODE_FLAG_INTERLACE);
9357
9358 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9359 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9360 DRM_MODE_FLAG_PHSYNC);
9361 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9362 DRM_MODE_FLAG_NHSYNC);
9363 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9364 DRM_MODE_FLAG_PVSYNC);
9365 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9366 DRM_MODE_FLAG_NVSYNC);
9367 }
9368
9369 PIPE_CONF_CHECK_I(pipe_src_w);
9370 PIPE_CONF_CHECK_I(pipe_src_h);
9371
9372 PIPE_CONF_CHECK_I(gmch_pfit.control);
9373 /* pfit ratios are autocomputed by the hw on gen4+ */
9374 if (INTEL_INFO(dev)->gen < 4)
9375 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9376 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9377 PIPE_CONF_CHECK_I(pch_pfit.enabled);
9378 if (current_config->pch_pfit.enabled) {
9379 PIPE_CONF_CHECK_I(pch_pfit.pos);
9380 PIPE_CONF_CHECK_I(pch_pfit.size);
9381 }
9382
9383 /* BDW+ don't expose a synchronous way to read the state */
9384 if (IS_HASWELL(dev))
9385 PIPE_CONF_CHECK_I(ips_enabled);
9386
9387 PIPE_CONF_CHECK_I(double_wide);
9388
9389 PIPE_CONF_CHECK_I(shared_dpll);
9390 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9391 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9392 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9393 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9394
9395 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9396 PIPE_CONF_CHECK_I(pipe_bpp);
9397
9398 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9399 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9400
9401 #undef PIPE_CONF_CHECK_X
9402 #undef PIPE_CONF_CHECK_I
9403 #undef PIPE_CONF_CHECK_FLAGS
9404 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9405 #undef PIPE_CONF_QUIRK
9406
9407 return true;
9408 }
9409
9410 static void
9411 check_connector_state(struct drm_device *dev)
9412 {
9413 struct intel_connector *connector;
9414
9415 list_for_each_entry(connector, &dev->mode_config.connector_list,
9416 base.head) {
9417 /* This also checks the encoder/connector hw state with the
9418 * ->get_hw_state callbacks. */
9419 intel_connector_check_state(connector);
9420
9421 WARN(&connector->new_encoder->base != connector->base.encoder,
9422 "connector's staged encoder doesn't match current encoder\n");
9423 }
9424 }
9425
9426 static void
9427 check_encoder_state(struct drm_device *dev)
9428 {
9429 struct intel_encoder *encoder;
9430 struct intel_connector *connector;
9431
9432 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9433 base.head) {
9434 bool enabled = false;
9435 bool active = false;
9436 enum pipe pipe, tracked_pipe;
9437
9438 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9439 encoder->base.base.id,
9440 drm_get_encoder_name(&encoder->base));
9441
9442 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9443 "encoder's stage crtc doesn't match current crtc\n");
9444 WARN(encoder->connectors_active && !encoder->base.crtc,
9445 "encoder's active_connectors set, but no crtc\n");
9446
9447 list_for_each_entry(connector, &dev->mode_config.connector_list,
9448 base.head) {
9449 if (connector->base.encoder != &encoder->base)
9450 continue;
9451 enabled = true;
9452 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9453 active = true;
9454 }
9455 WARN(!!encoder->base.crtc != enabled,
9456 "encoder's enabled state mismatch "
9457 "(expected %i, found %i)\n",
9458 !!encoder->base.crtc, enabled);
9459 WARN(active && !encoder->base.crtc,
9460 "active encoder with no crtc\n");
9461
9462 WARN(encoder->connectors_active != active,
9463 "encoder's computed active state doesn't match tracked active state "
9464 "(expected %i, found %i)\n", active, encoder->connectors_active);
9465
9466 active = encoder->get_hw_state(encoder, &pipe);
9467 WARN(active != encoder->connectors_active,
9468 "encoder's hw state doesn't match sw tracking "
9469 "(expected %i, found %i)\n",
9470 encoder->connectors_active, active);
9471
9472 if (!encoder->base.crtc)
9473 continue;
9474
9475 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9476 WARN(active && pipe != tracked_pipe,
9477 "active encoder's pipe doesn't match"
9478 "(expected %i, found %i)\n",
9479 tracked_pipe, pipe);
9480
9481 }
9482 }
9483
9484 static void
9485 check_crtc_state(struct drm_device *dev)
9486 {
9487 drm_i915_private_t *dev_priv = dev->dev_private;
9488 struct intel_crtc *crtc;
9489 struct intel_encoder *encoder;
9490 struct intel_crtc_config pipe_config;
9491
9492 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9493 base.head) {
9494 bool enabled = false;
9495 bool active = false;
9496
9497 memset(&pipe_config, 0, sizeof(pipe_config));
9498
9499 DRM_DEBUG_KMS("[CRTC:%d]\n",
9500 crtc->base.base.id);
9501
9502 WARN(crtc->active && !crtc->base.enabled,
9503 "active crtc, but not enabled in sw tracking\n");
9504
9505 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9506 base.head) {
9507 if (encoder->base.crtc != &crtc->base)
9508 continue;
9509 enabled = true;
9510 if (encoder->connectors_active)
9511 active = true;
9512 }
9513
9514 WARN(active != crtc->active,
9515 "crtc's computed active state doesn't match tracked active state "
9516 "(expected %i, found %i)\n", active, crtc->active);
9517 WARN(enabled != crtc->base.enabled,
9518 "crtc's computed enabled state doesn't match tracked enabled state "
9519 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9520
9521 active = dev_priv->display.get_pipe_config(crtc,
9522 &pipe_config);
9523
9524 /* hw state is inconsistent with the pipe A quirk */
9525 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9526 active = crtc->active;
9527
9528 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9529 base.head) {
9530 enum pipe pipe;
9531 if (encoder->base.crtc != &crtc->base)
9532 continue;
9533 if (encoder->get_hw_state(encoder, &pipe))
9534 encoder->get_config(encoder, &pipe_config);
9535 }
9536
9537 WARN(crtc->active != active,
9538 "crtc active state doesn't match with hw state "
9539 "(expected %i, found %i)\n", crtc->active, active);
9540
9541 if (active &&
9542 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9543 WARN(1, "pipe state doesn't match!\n");
9544 intel_dump_pipe_config(crtc, &pipe_config,
9545 "[hw state]");
9546 intel_dump_pipe_config(crtc, &crtc->config,
9547 "[sw state]");
9548 }
9549 }
9550 }
9551
9552 static void
9553 check_shared_dpll_state(struct drm_device *dev)
9554 {
9555 drm_i915_private_t *dev_priv = dev->dev_private;
9556 struct intel_crtc *crtc;
9557 struct intel_dpll_hw_state dpll_hw_state;
9558 int i;
9559
9560 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9561 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9562 int enabled_crtcs = 0, active_crtcs = 0;
9563 bool active;
9564
9565 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9566
9567 DRM_DEBUG_KMS("%s\n", pll->name);
9568
9569 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9570
9571 WARN(pll->active > pll->refcount,
9572 "more active pll users than references: %i vs %i\n",
9573 pll->active, pll->refcount);
9574 WARN(pll->active && !pll->on,
9575 "pll in active use but not on in sw tracking\n");
9576 WARN(pll->on && !pll->active,
9577 "pll in on but not on in use in sw tracking\n");
9578 WARN(pll->on != active,
9579 "pll on state mismatch (expected %i, found %i)\n",
9580 pll->on, active);
9581
9582 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9583 base.head) {
9584 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9585 enabled_crtcs++;
9586 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9587 active_crtcs++;
9588 }
9589 WARN(pll->active != active_crtcs,
9590 "pll active crtcs mismatch (expected %i, found %i)\n",
9591 pll->active, active_crtcs);
9592 WARN(pll->refcount != enabled_crtcs,
9593 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9594 pll->refcount, enabled_crtcs);
9595
9596 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9597 sizeof(dpll_hw_state)),
9598 "pll hw state mismatch\n");
9599 }
9600 }
9601
9602 void
9603 intel_modeset_check_state(struct drm_device *dev)
9604 {
9605 check_connector_state(dev);
9606 check_encoder_state(dev);
9607 check_crtc_state(dev);
9608 check_shared_dpll_state(dev);
9609 }
9610
9611 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9612 int dotclock)
9613 {
9614 /*
9615 * FDI already provided one idea for the dotclock.
9616 * Yell if the encoder disagrees.
9617 */
9618 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9619 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9620 pipe_config->adjusted_mode.crtc_clock, dotclock);
9621 }
9622
9623 static int __intel_set_mode(struct drm_crtc *crtc,
9624 struct drm_display_mode *mode,
9625 int x, int y, struct drm_framebuffer *fb)
9626 {
9627 struct drm_device *dev = crtc->dev;
9628 drm_i915_private_t *dev_priv = dev->dev_private;
9629 struct drm_display_mode *saved_mode;
9630 struct intel_crtc_config *pipe_config = NULL;
9631 struct intel_crtc *intel_crtc;
9632 unsigned disable_pipes, prepare_pipes, modeset_pipes;
9633 int ret = 0;
9634
9635 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
9636 if (!saved_mode)
9637 return -ENOMEM;
9638
9639 intel_modeset_affected_pipes(crtc, &modeset_pipes,
9640 &prepare_pipes, &disable_pipes);
9641
9642 *saved_mode = crtc->mode;
9643
9644 /* Hack: Because we don't (yet) support global modeset on multiple
9645 * crtcs, we don't keep track of the new mode for more than one crtc.
9646 * Hence simply check whether any bit is set in modeset_pipes in all the
9647 * pieces of code that are not yet converted to deal with mutliple crtcs
9648 * changing their mode at the same time. */
9649 if (modeset_pipes) {
9650 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9651 if (IS_ERR(pipe_config)) {
9652 ret = PTR_ERR(pipe_config);
9653 pipe_config = NULL;
9654
9655 goto out;
9656 }
9657 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9658 "[modeset]");
9659 to_intel_crtc(crtc)->new_config = pipe_config;
9660 }
9661
9662 /*
9663 * See if the config requires any additional preparation, e.g.
9664 * to adjust global state with pipes off. We need to do this
9665 * here so we can get the modeset_pipe updated config for the new
9666 * mode set on this crtc. For other crtcs we need to use the
9667 * adjusted_mode bits in the crtc directly.
9668 */
9669 if (IS_VALLEYVIEW(dev)) {
9670 valleyview_modeset_global_pipes(dev, &prepare_pipes);
9671
9672 /* may have added more to prepare_pipes than we should */
9673 prepare_pipes &= ~disable_pipes;
9674 }
9675
9676 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9677 intel_crtc_disable(&intel_crtc->base);
9678
9679 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9680 if (intel_crtc->base.enabled)
9681 dev_priv->display.crtc_disable(&intel_crtc->base);
9682 }
9683
9684 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9685 * to set it here already despite that we pass it down the callchain.
9686 */
9687 if (modeset_pipes) {
9688 crtc->mode = *mode;
9689 /* mode_set/enable/disable functions rely on a correct pipe
9690 * config. */
9691 to_intel_crtc(crtc)->config = *pipe_config;
9692 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
9693
9694 /*
9695 * Calculate and store various constants which
9696 * are later needed by vblank and swap-completion
9697 * timestamping. They are derived from true hwmode.
9698 */
9699 drm_calc_timestamping_constants(crtc,
9700 &pipe_config->adjusted_mode);
9701 }
9702
9703 /* Only after disabling all output pipelines that will be changed can we
9704 * update the the output configuration. */
9705 intel_modeset_update_state(dev, prepare_pipes);
9706
9707 if (dev_priv->display.modeset_global_resources)
9708 dev_priv->display.modeset_global_resources(dev);
9709
9710 /* Set up the DPLL and any encoders state that needs to adjust or depend
9711 * on the DPLL.
9712 */
9713 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9714 ret = intel_crtc_mode_set(&intel_crtc->base,
9715 x, y, fb);
9716 if (ret)
9717 goto done;
9718 }
9719
9720 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9721 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9722 dev_priv->display.crtc_enable(&intel_crtc->base);
9723
9724 /* FIXME: add subpixel order */
9725 done:
9726 if (ret && crtc->enabled)
9727 crtc->mode = *saved_mode;
9728
9729 out:
9730 kfree(pipe_config);
9731 kfree(saved_mode);
9732 return ret;
9733 }
9734
9735 static int intel_set_mode(struct drm_crtc *crtc,
9736 struct drm_display_mode *mode,
9737 int x, int y, struct drm_framebuffer *fb)
9738 {
9739 int ret;
9740
9741 ret = __intel_set_mode(crtc, mode, x, y, fb);
9742
9743 if (ret == 0)
9744 intel_modeset_check_state(crtc->dev);
9745
9746 return ret;
9747 }
9748
9749 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9750 {
9751 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9752 }
9753
9754 #undef for_each_intel_crtc_masked
9755
9756 static void intel_set_config_free(struct intel_set_config *config)
9757 {
9758 if (!config)
9759 return;
9760
9761 kfree(config->save_connector_encoders);
9762 kfree(config->save_encoder_crtcs);
9763 kfree(config->save_crtc_enabled);
9764 kfree(config);
9765 }
9766
9767 static int intel_set_config_save_state(struct drm_device *dev,
9768 struct intel_set_config *config)
9769 {
9770 struct drm_crtc *crtc;
9771 struct drm_encoder *encoder;
9772 struct drm_connector *connector;
9773 int count;
9774
9775 config->save_crtc_enabled =
9776 kcalloc(dev->mode_config.num_crtc,
9777 sizeof(bool), GFP_KERNEL);
9778 if (!config->save_crtc_enabled)
9779 return -ENOMEM;
9780
9781 config->save_encoder_crtcs =
9782 kcalloc(dev->mode_config.num_encoder,
9783 sizeof(struct drm_crtc *), GFP_KERNEL);
9784 if (!config->save_encoder_crtcs)
9785 return -ENOMEM;
9786
9787 config->save_connector_encoders =
9788 kcalloc(dev->mode_config.num_connector,
9789 sizeof(struct drm_encoder *), GFP_KERNEL);
9790 if (!config->save_connector_encoders)
9791 return -ENOMEM;
9792
9793 /* Copy data. Note that driver private data is not affected.
9794 * Should anything bad happen only the expected state is
9795 * restored, not the drivers personal bookkeeping.
9796 */
9797 count = 0;
9798 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9799 config->save_crtc_enabled[count++] = crtc->enabled;
9800 }
9801
9802 count = 0;
9803 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9804 config->save_encoder_crtcs[count++] = encoder->crtc;
9805 }
9806
9807 count = 0;
9808 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9809 config->save_connector_encoders[count++] = connector->encoder;
9810 }
9811
9812 return 0;
9813 }
9814
9815 static void intel_set_config_restore_state(struct drm_device *dev,
9816 struct intel_set_config *config)
9817 {
9818 struct intel_crtc *crtc;
9819 struct intel_encoder *encoder;
9820 struct intel_connector *connector;
9821 int count;
9822
9823 count = 0;
9824 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9825 crtc->new_enabled = config->save_crtc_enabled[count++];
9826
9827 if (crtc->new_enabled)
9828 crtc->new_config = &crtc->config;
9829 else
9830 crtc->new_config = NULL;
9831 }
9832
9833 count = 0;
9834 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9835 encoder->new_crtc =
9836 to_intel_crtc(config->save_encoder_crtcs[count++]);
9837 }
9838
9839 count = 0;
9840 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9841 connector->new_encoder =
9842 to_intel_encoder(config->save_connector_encoders[count++]);
9843 }
9844 }
9845
9846 static bool
9847 is_crtc_connector_off(struct drm_mode_set *set)
9848 {
9849 int i;
9850
9851 if (set->num_connectors == 0)
9852 return false;
9853
9854 if (WARN_ON(set->connectors == NULL))
9855 return false;
9856
9857 for (i = 0; i < set->num_connectors; i++)
9858 if (set->connectors[i]->encoder &&
9859 set->connectors[i]->encoder->crtc == set->crtc &&
9860 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9861 return true;
9862
9863 return false;
9864 }
9865
9866 static void
9867 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9868 struct intel_set_config *config)
9869 {
9870
9871 /* We should be able to check here if the fb has the same properties
9872 * and then just flip_or_move it */
9873 if (is_crtc_connector_off(set)) {
9874 config->mode_changed = true;
9875 } else if (set->crtc->fb != set->fb) {
9876 /* If we have no fb then treat it as a full mode set */
9877 if (set->crtc->fb == NULL) {
9878 struct intel_crtc *intel_crtc =
9879 to_intel_crtc(set->crtc);
9880
9881 if (intel_crtc->active && i915.fastboot) {
9882 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9883 config->fb_changed = true;
9884 } else {
9885 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9886 config->mode_changed = true;
9887 }
9888 } else if (set->fb == NULL) {
9889 config->mode_changed = true;
9890 } else if (set->fb->pixel_format !=
9891 set->crtc->fb->pixel_format) {
9892 config->mode_changed = true;
9893 } else {
9894 config->fb_changed = true;
9895 }
9896 }
9897
9898 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9899 config->fb_changed = true;
9900
9901 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9902 DRM_DEBUG_KMS("modes are different, full mode set\n");
9903 drm_mode_debug_printmodeline(&set->crtc->mode);
9904 drm_mode_debug_printmodeline(set->mode);
9905 config->mode_changed = true;
9906 }
9907
9908 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9909 set->crtc->base.id, config->mode_changed, config->fb_changed);
9910 }
9911
9912 static int
9913 intel_modeset_stage_output_state(struct drm_device *dev,
9914 struct drm_mode_set *set,
9915 struct intel_set_config *config)
9916 {
9917 struct intel_connector *connector;
9918 struct intel_encoder *encoder;
9919 struct intel_crtc *crtc;
9920 int ro;
9921
9922 /* The upper layers ensure that we either disable a crtc or have a list
9923 * of connectors. For paranoia, double-check this. */
9924 WARN_ON(!set->fb && (set->num_connectors != 0));
9925 WARN_ON(set->fb && (set->num_connectors == 0));
9926
9927 list_for_each_entry(connector, &dev->mode_config.connector_list,
9928 base.head) {
9929 /* Otherwise traverse passed in connector list and get encoders
9930 * for them. */
9931 for (ro = 0; ro < set->num_connectors; ro++) {
9932 if (set->connectors[ro] == &connector->base) {
9933 connector->new_encoder = connector->encoder;
9934 break;
9935 }
9936 }
9937
9938 /* If we disable the crtc, disable all its connectors. Also, if
9939 * the connector is on the changing crtc but not on the new
9940 * connector list, disable it. */
9941 if ((!set->fb || ro == set->num_connectors) &&
9942 connector->base.encoder &&
9943 connector->base.encoder->crtc == set->crtc) {
9944 connector->new_encoder = NULL;
9945
9946 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9947 connector->base.base.id,
9948 drm_get_connector_name(&connector->base));
9949 }
9950
9951
9952 if (&connector->new_encoder->base != connector->base.encoder) {
9953 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9954 config->mode_changed = true;
9955 }
9956 }
9957 /* connector->new_encoder is now updated for all connectors. */
9958
9959 /* Update crtc of enabled connectors. */
9960 list_for_each_entry(connector, &dev->mode_config.connector_list,
9961 base.head) {
9962 struct drm_crtc *new_crtc;
9963
9964 if (!connector->new_encoder)
9965 continue;
9966
9967 new_crtc = connector->new_encoder->base.crtc;
9968
9969 for (ro = 0; ro < set->num_connectors; ro++) {
9970 if (set->connectors[ro] == &connector->base)
9971 new_crtc = set->crtc;
9972 }
9973
9974 /* Make sure the new CRTC will work with the encoder */
9975 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
9976 new_crtc)) {
9977 return -EINVAL;
9978 }
9979 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9980
9981 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9982 connector->base.base.id,
9983 drm_get_connector_name(&connector->base),
9984 new_crtc->base.id);
9985 }
9986
9987 /* Check for any encoders that needs to be disabled. */
9988 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9989 base.head) {
9990 int num_connectors = 0;
9991 list_for_each_entry(connector,
9992 &dev->mode_config.connector_list,
9993 base.head) {
9994 if (connector->new_encoder == encoder) {
9995 WARN_ON(!connector->new_encoder->new_crtc);
9996 num_connectors++;
9997 }
9998 }
9999
10000 if (num_connectors == 0)
10001 encoder->new_crtc = NULL;
10002 else if (num_connectors > 1)
10003 return -EINVAL;
10004
10005 /* Only now check for crtc changes so we don't miss encoders
10006 * that will be disabled. */
10007 if (&encoder->new_crtc->base != encoder->base.crtc) {
10008 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10009 config->mode_changed = true;
10010 }
10011 }
10012 /* Now we've also updated encoder->new_crtc for all encoders. */
10013
10014 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10015 base.head) {
10016 crtc->new_enabled = false;
10017
10018 list_for_each_entry(encoder,
10019 &dev->mode_config.encoder_list,
10020 base.head) {
10021 if (encoder->new_crtc == crtc) {
10022 crtc->new_enabled = true;
10023 break;
10024 }
10025 }
10026
10027 if (crtc->new_enabled != crtc->base.enabled) {
10028 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10029 crtc->new_enabled ? "en" : "dis");
10030 config->mode_changed = true;
10031 }
10032
10033 if (crtc->new_enabled)
10034 crtc->new_config = &crtc->config;
10035 else
10036 crtc->new_config = NULL;
10037 }
10038
10039 return 0;
10040 }
10041
10042 static void disable_crtc_nofb(struct intel_crtc *crtc)
10043 {
10044 struct drm_device *dev = crtc->base.dev;
10045 struct intel_encoder *encoder;
10046 struct intel_connector *connector;
10047
10048 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10049 pipe_name(crtc->pipe));
10050
10051 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10052 if (connector->new_encoder &&
10053 connector->new_encoder->new_crtc == crtc)
10054 connector->new_encoder = NULL;
10055 }
10056
10057 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10058 if (encoder->new_crtc == crtc)
10059 encoder->new_crtc = NULL;
10060 }
10061
10062 crtc->new_enabled = false;
10063 crtc->new_config = NULL;
10064 }
10065
10066 static int intel_crtc_set_config(struct drm_mode_set *set)
10067 {
10068 struct drm_device *dev;
10069 struct drm_mode_set save_set;
10070 struct intel_set_config *config;
10071 int ret;
10072
10073 BUG_ON(!set);
10074 BUG_ON(!set->crtc);
10075 BUG_ON(!set->crtc->helper_private);
10076
10077 /* Enforce sane interface api - has been abused by the fb helper. */
10078 BUG_ON(!set->mode && set->fb);
10079 BUG_ON(set->fb && set->num_connectors == 0);
10080
10081 if (set->fb) {
10082 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10083 set->crtc->base.id, set->fb->base.id,
10084 (int)set->num_connectors, set->x, set->y);
10085 } else {
10086 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10087 }
10088
10089 dev = set->crtc->dev;
10090
10091 ret = -ENOMEM;
10092 config = kzalloc(sizeof(*config), GFP_KERNEL);
10093 if (!config)
10094 goto out_config;
10095
10096 ret = intel_set_config_save_state(dev, config);
10097 if (ret)
10098 goto out_config;
10099
10100 save_set.crtc = set->crtc;
10101 save_set.mode = &set->crtc->mode;
10102 save_set.x = set->crtc->x;
10103 save_set.y = set->crtc->y;
10104 save_set.fb = set->crtc->fb;
10105
10106 /* Compute whether we need a full modeset, only an fb base update or no
10107 * change at all. In the future we might also check whether only the
10108 * mode changed, e.g. for LVDS where we only change the panel fitter in
10109 * such cases. */
10110 intel_set_config_compute_mode_changes(set, config);
10111
10112 ret = intel_modeset_stage_output_state(dev, set, config);
10113 if (ret)
10114 goto fail;
10115
10116 if (config->mode_changed) {
10117 ret = intel_set_mode(set->crtc, set->mode,
10118 set->x, set->y, set->fb);
10119 } else if (config->fb_changed) {
10120 intel_crtc_wait_for_pending_flips(set->crtc);
10121
10122 ret = intel_pipe_set_base(set->crtc,
10123 set->x, set->y, set->fb);
10124 /*
10125 * In the fastboot case this may be our only check of the
10126 * state after boot. It would be better to only do it on
10127 * the first update, but we don't have a nice way of doing that
10128 * (and really, set_config isn't used much for high freq page
10129 * flipping, so increasing its cost here shouldn't be a big
10130 * deal).
10131 */
10132 if (i915.fastboot && ret == 0)
10133 intel_modeset_check_state(set->crtc->dev);
10134 }
10135
10136 if (ret) {
10137 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10138 set->crtc->base.id, ret);
10139 fail:
10140 intel_set_config_restore_state(dev, config);
10141
10142 /*
10143 * HACK: if the pipe was on, but we didn't have a framebuffer,
10144 * force the pipe off to avoid oopsing in the modeset code
10145 * due to fb==NULL. This should only happen during boot since
10146 * we don't yet reconstruct the FB from the hardware state.
10147 */
10148 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10149 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10150
10151 /* Try to restore the config */
10152 if (config->mode_changed &&
10153 intel_set_mode(save_set.crtc, save_set.mode,
10154 save_set.x, save_set.y, save_set.fb))
10155 DRM_ERROR("failed to restore config after modeset failure\n");
10156 }
10157
10158 out_config:
10159 intel_set_config_free(config);
10160 return ret;
10161 }
10162
10163 static const struct drm_crtc_funcs intel_crtc_funcs = {
10164 .cursor_set = intel_crtc_cursor_set,
10165 .cursor_move = intel_crtc_cursor_move,
10166 .gamma_set = intel_crtc_gamma_set,
10167 .set_config = intel_crtc_set_config,
10168 .destroy = intel_crtc_destroy,
10169 .page_flip = intel_crtc_page_flip,
10170 };
10171
10172 static void intel_cpu_pll_init(struct drm_device *dev)
10173 {
10174 if (HAS_DDI(dev))
10175 intel_ddi_pll_init(dev);
10176 }
10177
10178 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10179 struct intel_shared_dpll *pll,
10180 struct intel_dpll_hw_state *hw_state)
10181 {
10182 uint32_t val;
10183
10184 val = I915_READ(PCH_DPLL(pll->id));
10185 hw_state->dpll = val;
10186 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10187 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10188
10189 return val & DPLL_VCO_ENABLE;
10190 }
10191
10192 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10193 struct intel_shared_dpll *pll)
10194 {
10195 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10196 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10197 }
10198
10199 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10200 struct intel_shared_dpll *pll)
10201 {
10202 /* PCH refclock must be enabled first */
10203 ibx_assert_pch_refclk_enabled(dev_priv);
10204
10205 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10206
10207 /* Wait for the clocks to stabilize. */
10208 POSTING_READ(PCH_DPLL(pll->id));
10209 udelay(150);
10210
10211 /* The pixel multiplier can only be updated once the
10212 * DPLL is enabled and the clocks are stable.
10213 *
10214 * So write it again.
10215 */
10216 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10217 POSTING_READ(PCH_DPLL(pll->id));
10218 udelay(200);
10219 }
10220
10221 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10222 struct intel_shared_dpll *pll)
10223 {
10224 struct drm_device *dev = dev_priv->dev;
10225 struct intel_crtc *crtc;
10226
10227 /* Make sure no transcoder isn't still depending on us. */
10228 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10229 if (intel_crtc_to_shared_dpll(crtc) == pll)
10230 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10231 }
10232
10233 I915_WRITE(PCH_DPLL(pll->id), 0);
10234 POSTING_READ(PCH_DPLL(pll->id));
10235 udelay(200);
10236 }
10237
10238 static char *ibx_pch_dpll_names[] = {
10239 "PCH DPLL A",
10240 "PCH DPLL B",
10241 };
10242
10243 static void ibx_pch_dpll_init(struct drm_device *dev)
10244 {
10245 struct drm_i915_private *dev_priv = dev->dev_private;
10246 int i;
10247
10248 dev_priv->num_shared_dpll = 2;
10249
10250 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10251 dev_priv->shared_dplls[i].id = i;
10252 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10253 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10254 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10255 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10256 dev_priv->shared_dplls[i].get_hw_state =
10257 ibx_pch_dpll_get_hw_state;
10258 }
10259 }
10260
10261 static void intel_shared_dpll_init(struct drm_device *dev)
10262 {
10263 struct drm_i915_private *dev_priv = dev->dev_private;
10264
10265 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10266 ibx_pch_dpll_init(dev);
10267 else
10268 dev_priv->num_shared_dpll = 0;
10269
10270 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10271 }
10272
10273 static void intel_crtc_init(struct drm_device *dev, int pipe)
10274 {
10275 drm_i915_private_t *dev_priv = dev->dev_private;
10276 struct intel_crtc *intel_crtc;
10277 int i;
10278
10279 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10280 if (intel_crtc == NULL)
10281 return;
10282
10283 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10284
10285 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10286 for (i = 0; i < 256; i++) {
10287 intel_crtc->lut_r[i] = i;
10288 intel_crtc->lut_g[i] = i;
10289 intel_crtc->lut_b[i] = i;
10290 }
10291
10292 /*
10293 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10294 * is hooked to plane B. Hence we want plane A feeding pipe B.
10295 */
10296 intel_crtc->pipe = pipe;
10297 intel_crtc->plane = pipe;
10298 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10299 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10300 intel_crtc->plane = !pipe;
10301 }
10302
10303 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10304 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10305 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10306 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10307
10308 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10309 }
10310
10311 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10312 {
10313 struct drm_encoder *encoder = connector->base.encoder;
10314
10315 WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10316
10317 if (!encoder)
10318 return INVALID_PIPE;
10319
10320 return to_intel_crtc(encoder->crtc)->pipe;
10321 }
10322
10323 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10324 struct drm_file *file)
10325 {
10326 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10327 struct drm_mode_object *drmmode_obj;
10328 struct intel_crtc *crtc;
10329
10330 if (!drm_core_check_feature(dev, DRIVER_MODESET))
10331 return -ENODEV;
10332
10333 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10334 DRM_MODE_OBJECT_CRTC);
10335
10336 if (!drmmode_obj) {
10337 DRM_ERROR("no such CRTC id\n");
10338 return -ENOENT;
10339 }
10340
10341 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10342 pipe_from_crtc_id->pipe = crtc->pipe;
10343
10344 return 0;
10345 }
10346
10347 static int intel_encoder_clones(struct intel_encoder *encoder)
10348 {
10349 struct drm_device *dev = encoder->base.dev;
10350 struct intel_encoder *source_encoder;
10351 int index_mask = 0;
10352 int entry = 0;
10353
10354 list_for_each_entry(source_encoder,
10355 &dev->mode_config.encoder_list, base.head) {
10356
10357 if (encoder == source_encoder)
10358 index_mask |= (1 << entry);
10359
10360 /* Intel hw has only one MUX where enocoders could be cloned. */
10361 if (encoder->cloneable && source_encoder->cloneable)
10362 index_mask |= (1 << entry);
10363
10364 entry++;
10365 }
10366
10367 return index_mask;
10368 }
10369
10370 static bool has_edp_a(struct drm_device *dev)
10371 {
10372 struct drm_i915_private *dev_priv = dev->dev_private;
10373
10374 if (!IS_MOBILE(dev))
10375 return false;
10376
10377 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10378 return false;
10379
10380 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
10381 return false;
10382
10383 return true;
10384 }
10385
10386 const char *intel_output_name(int output)
10387 {
10388 static const char *names[] = {
10389 [INTEL_OUTPUT_UNUSED] = "Unused",
10390 [INTEL_OUTPUT_ANALOG] = "Analog",
10391 [INTEL_OUTPUT_DVO] = "DVO",
10392 [INTEL_OUTPUT_SDVO] = "SDVO",
10393 [INTEL_OUTPUT_LVDS] = "LVDS",
10394 [INTEL_OUTPUT_TVOUT] = "TV",
10395 [INTEL_OUTPUT_HDMI] = "HDMI",
10396 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10397 [INTEL_OUTPUT_EDP] = "eDP",
10398 [INTEL_OUTPUT_DSI] = "DSI",
10399 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10400 };
10401
10402 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10403 return "Invalid";
10404
10405 return names[output];
10406 }
10407
10408 static void intel_setup_outputs(struct drm_device *dev)
10409 {
10410 struct drm_i915_private *dev_priv = dev->dev_private;
10411 struct intel_encoder *encoder;
10412 bool dpd_is_edp = false;
10413
10414 intel_lvds_init(dev);
10415
10416 if (!IS_ULT(dev))
10417 intel_crt_init(dev);
10418
10419 if (HAS_DDI(dev)) {
10420 int found;
10421
10422 /* Haswell uses DDI functions to detect digital outputs */
10423 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10424 /* DDI A only supports eDP */
10425 if (found)
10426 intel_ddi_init(dev, PORT_A);
10427
10428 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10429 * register */
10430 found = I915_READ(SFUSE_STRAP);
10431
10432 if (found & SFUSE_STRAP_DDIB_DETECTED)
10433 intel_ddi_init(dev, PORT_B);
10434 if (found & SFUSE_STRAP_DDIC_DETECTED)
10435 intel_ddi_init(dev, PORT_C);
10436 if (found & SFUSE_STRAP_DDID_DETECTED)
10437 intel_ddi_init(dev, PORT_D);
10438 } else if (HAS_PCH_SPLIT(dev)) {
10439 int found;
10440 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10441
10442 if (has_edp_a(dev))
10443 intel_dp_init(dev, DP_A, PORT_A);
10444
10445 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10446 /* PCH SDVOB multiplex with HDMIB */
10447 found = intel_sdvo_init(dev, PCH_SDVOB, true);
10448 if (!found)
10449 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10450 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10451 intel_dp_init(dev, PCH_DP_B, PORT_B);
10452 }
10453
10454 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10455 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10456
10457 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10458 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10459
10460 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10461 intel_dp_init(dev, PCH_DP_C, PORT_C);
10462
10463 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10464 intel_dp_init(dev, PCH_DP_D, PORT_D);
10465 } else if (IS_VALLEYVIEW(dev)) {
10466 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10467 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10468 PORT_B);
10469 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10470 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10471 }
10472
10473 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10474 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10475 PORT_C);
10476 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10477 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
10478 }
10479
10480 intel_dsi_init(dev);
10481 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10482 bool found = false;
10483
10484 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10485 DRM_DEBUG_KMS("probing SDVOB\n");
10486 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10487 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10488 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10489 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10490 }
10491
10492 if (!found && SUPPORTS_INTEGRATED_DP(dev))
10493 intel_dp_init(dev, DP_B, PORT_B);
10494 }
10495
10496 /* Before G4X SDVOC doesn't have its own detect register */
10497
10498 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10499 DRM_DEBUG_KMS("probing SDVOC\n");
10500 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10501 }
10502
10503 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10504
10505 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10506 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10507 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10508 }
10509 if (SUPPORTS_INTEGRATED_DP(dev))
10510 intel_dp_init(dev, DP_C, PORT_C);
10511 }
10512
10513 if (SUPPORTS_INTEGRATED_DP(dev) &&
10514 (I915_READ(DP_D) & DP_DETECTED))
10515 intel_dp_init(dev, DP_D, PORT_D);
10516 } else if (IS_GEN2(dev))
10517 intel_dvo_init(dev);
10518
10519 if (SUPPORTS_TV(dev))
10520 intel_tv_init(dev);
10521
10522 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10523 encoder->base.possible_crtcs = encoder->crtc_mask;
10524 encoder->base.possible_clones =
10525 intel_encoder_clones(encoder);
10526 }
10527
10528 intel_init_pch_refclk(dev);
10529
10530 drm_helper_move_panel_connectors_to_head(dev);
10531 }
10532
10533 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10534 {
10535 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10536
10537 drm_framebuffer_cleanup(fb);
10538 WARN_ON(!intel_fb->obj->framebuffer_references--);
10539 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
10540 kfree(intel_fb);
10541 }
10542
10543 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10544 struct drm_file *file,
10545 unsigned int *handle)
10546 {
10547 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10548 struct drm_i915_gem_object *obj = intel_fb->obj;
10549
10550 return drm_gem_handle_create(file, &obj->base, handle);
10551 }
10552
10553 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10554 .destroy = intel_user_framebuffer_destroy,
10555 .create_handle = intel_user_framebuffer_create_handle,
10556 };
10557
10558 int intel_framebuffer_init(struct drm_device *dev,
10559 struct intel_framebuffer *intel_fb,
10560 struct drm_mode_fb_cmd2 *mode_cmd,
10561 struct drm_i915_gem_object *obj)
10562 {
10563 int aligned_height;
10564 int pitch_limit;
10565 int ret;
10566
10567 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10568
10569 if (obj->tiling_mode == I915_TILING_Y) {
10570 DRM_DEBUG("hardware does not support tiling Y\n");
10571 return -EINVAL;
10572 }
10573
10574 if (mode_cmd->pitches[0] & 63) {
10575 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10576 mode_cmd->pitches[0]);
10577 return -EINVAL;
10578 }
10579
10580 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10581 pitch_limit = 32*1024;
10582 } else if (INTEL_INFO(dev)->gen >= 4) {
10583 if (obj->tiling_mode)
10584 pitch_limit = 16*1024;
10585 else
10586 pitch_limit = 32*1024;
10587 } else if (INTEL_INFO(dev)->gen >= 3) {
10588 if (obj->tiling_mode)
10589 pitch_limit = 8*1024;
10590 else
10591 pitch_limit = 16*1024;
10592 } else
10593 /* XXX DSPC is limited to 4k tiled */
10594 pitch_limit = 8*1024;
10595
10596 if (mode_cmd->pitches[0] > pitch_limit) {
10597 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10598 obj->tiling_mode ? "tiled" : "linear",
10599 mode_cmd->pitches[0], pitch_limit);
10600 return -EINVAL;
10601 }
10602
10603 if (obj->tiling_mode != I915_TILING_NONE &&
10604 mode_cmd->pitches[0] != obj->stride) {
10605 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10606 mode_cmd->pitches[0], obj->stride);
10607 return -EINVAL;
10608 }
10609
10610 /* Reject formats not supported by any plane early. */
10611 switch (mode_cmd->pixel_format) {
10612 case DRM_FORMAT_C8:
10613 case DRM_FORMAT_RGB565:
10614 case DRM_FORMAT_XRGB8888:
10615 case DRM_FORMAT_ARGB8888:
10616 break;
10617 case DRM_FORMAT_XRGB1555:
10618 case DRM_FORMAT_ARGB1555:
10619 if (INTEL_INFO(dev)->gen > 3) {
10620 DRM_DEBUG("unsupported pixel format: %s\n",
10621 drm_get_format_name(mode_cmd->pixel_format));
10622 return -EINVAL;
10623 }
10624 break;
10625 case DRM_FORMAT_XBGR8888:
10626 case DRM_FORMAT_ABGR8888:
10627 case DRM_FORMAT_XRGB2101010:
10628 case DRM_FORMAT_ARGB2101010:
10629 case DRM_FORMAT_XBGR2101010:
10630 case DRM_FORMAT_ABGR2101010:
10631 if (INTEL_INFO(dev)->gen < 4) {
10632 DRM_DEBUG("unsupported pixel format: %s\n",
10633 drm_get_format_name(mode_cmd->pixel_format));
10634 return -EINVAL;
10635 }
10636 break;
10637 case DRM_FORMAT_YUYV:
10638 case DRM_FORMAT_UYVY:
10639 case DRM_FORMAT_YVYU:
10640 case DRM_FORMAT_VYUY:
10641 if (INTEL_INFO(dev)->gen < 5) {
10642 DRM_DEBUG("unsupported pixel format: %s\n",
10643 drm_get_format_name(mode_cmd->pixel_format));
10644 return -EINVAL;
10645 }
10646 break;
10647 default:
10648 DRM_DEBUG("unsupported pixel format: %s\n",
10649 drm_get_format_name(mode_cmd->pixel_format));
10650 return -EINVAL;
10651 }
10652
10653 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10654 if (mode_cmd->offsets[0] != 0)
10655 return -EINVAL;
10656
10657 aligned_height = intel_align_height(dev, mode_cmd->height,
10658 obj->tiling_mode);
10659 /* FIXME drm helper for size checks (especially planar formats)? */
10660 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10661 return -EINVAL;
10662
10663 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10664 intel_fb->obj = obj;
10665 intel_fb->obj->framebuffer_references++;
10666
10667 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10668 if (ret) {
10669 DRM_ERROR("framebuffer init failed %d\n", ret);
10670 return ret;
10671 }
10672
10673 return 0;
10674 }
10675
10676 static struct drm_framebuffer *
10677 intel_user_framebuffer_create(struct drm_device *dev,
10678 struct drm_file *filp,
10679 struct drm_mode_fb_cmd2 *mode_cmd)
10680 {
10681 struct drm_i915_gem_object *obj;
10682
10683 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10684 mode_cmd->handles[0]));
10685 if (&obj->base == NULL)
10686 return ERR_PTR(-ENOENT);
10687
10688 return intel_framebuffer_create(dev, mode_cmd, obj);
10689 }
10690
10691 #ifndef CONFIG_DRM_I915_FBDEV
10692 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10693 {
10694 }
10695 #endif
10696
10697 static const struct drm_mode_config_funcs intel_mode_funcs = {
10698 .fb_create = intel_user_framebuffer_create,
10699 .output_poll_changed = intel_fbdev_output_poll_changed,
10700 };
10701
10702 /* Set up chip specific display functions */
10703 static void intel_init_display(struct drm_device *dev)
10704 {
10705 struct drm_i915_private *dev_priv = dev->dev_private;
10706
10707 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10708 dev_priv->display.find_dpll = g4x_find_best_dpll;
10709 else if (IS_VALLEYVIEW(dev))
10710 dev_priv->display.find_dpll = vlv_find_best_dpll;
10711 else if (IS_PINEVIEW(dev))
10712 dev_priv->display.find_dpll = pnv_find_best_dpll;
10713 else
10714 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10715
10716 if (HAS_DDI(dev)) {
10717 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10718 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10719 dev_priv->display.crtc_enable = haswell_crtc_enable;
10720 dev_priv->display.crtc_disable = haswell_crtc_disable;
10721 dev_priv->display.off = haswell_crtc_off;
10722 dev_priv->display.update_plane = ironlake_update_plane;
10723 } else if (HAS_PCH_SPLIT(dev)) {
10724 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10725 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10726 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10727 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10728 dev_priv->display.off = ironlake_crtc_off;
10729 dev_priv->display.update_plane = ironlake_update_plane;
10730 } else if (IS_VALLEYVIEW(dev)) {
10731 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10732 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10733 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10734 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10735 dev_priv->display.off = i9xx_crtc_off;
10736 dev_priv->display.update_plane = i9xx_update_plane;
10737 } else {
10738 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10739 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10740 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10741 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10742 dev_priv->display.off = i9xx_crtc_off;
10743 dev_priv->display.update_plane = i9xx_update_plane;
10744 }
10745
10746 /* Returns the core display clock speed */
10747 if (IS_VALLEYVIEW(dev))
10748 dev_priv->display.get_display_clock_speed =
10749 valleyview_get_display_clock_speed;
10750 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10751 dev_priv->display.get_display_clock_speed =
10752 i945_get_display_clock_speed;
10753 else if (IS_I915G(dev))
10754 dev_priv->display.get_display_clock_speed =
10755 i915_get_display_clock_speed;
10756 else if (IS_I945GM(dev) || IS_845G(dev))
10757 dev_priv->display.get_display_clock_speed =
10758 i9xx_misc_get_display_clock_speed;
10759 else if (IS_PINEVIEW(dev))
10760 dev_priv->display.get_display_clock_speed =
10761 pnv_get_display_clock_speed;
10762 else if (IS_I915GM(dev))
10763 dev_priv->display.get_display_clock_speed =
10764 i915gm_get_display_clock_speed;
10765 else if (IS_I865G(dev))
10766 dev_priv->display.get_display_clock_speed =
10767 i865_get_display_clock_speed;
10768 else if (IS_I85X(dev))
10769 dev_priv->display.get_display_clock_speed =
10770 i855_get_display_clock_speed;
10771 else /* 852, 830 */
10772 dev_priv->display.get_display_clock_speed =
10773 i830_get_display_clock_speed;
10774
10775 if (HAS_PCH_SPLIT(dev)) {
10776 if (IS_GEN5(dev)) {
10777 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10778 dev_priv->display.write_eld = ironlake_write_eld;
10779 } else if (IS_GEN6(dev)) {
10780 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10781 dev_priv->display.write_eld = ironlake_write_eld;
10782 } else if (IS_IVYBRIDGE(dev)) {
10783 /* FIXME: detect B0+ stepping and use auto training */
10784 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10785 dev_priv->display.write_eld = ironlake_write_eld;
10786 dev_priv->display.modeset_global_resources =
10787 ivb_modeset_global_resources;
10788 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
10789 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10790 dev_priv->display.write_eld = haswell_write_eld;
10791 dev_priv->display.modeset_global_resources =
10792 haswell_modeset_global_resources;
10793 }
10794 } else if (IS_G4X(dev)) {
10795 dev_priv->display.write_eld = g4x_write_eld;
10796 } else if (IS_VALLEYVIEW(dev)) {
10797 dev_priv->display.modeset_global_resources =
10798 valleyview_modeset_global_resources;
10799 dev_priv->display.write_eld = ironlake_write_eld;
10800 }
10801
10802 /* Default just returns -ENODEV to indicate unsupported */
10803 dev_priv->display.queue_flip = intel_default_queue_flip;
10804
10805 switch (INTEL_INFO(dev)->gen) {
10806 case 2:
10807 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10808 break;
10809
10810 case 3:
10811 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10812 break;
10813
10814 case 4:
10815 case 5:
10816 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10817 break;
10818
10819 case 6:
10820 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10821 break;
10822 case 7:
10823 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
10824 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10825 break;
10826 }
10827
10828 intel_panel_init_backlight_funcs(dev);
10829 }
10830
10831 /*
10832 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10833 * resume, or other times. This quirk makes sure that's the case for
10834 * affected systems.
10835 */
10836 static void quirk_pipea_force(struct drm_device *dev)
10837 {
10838 struct drm_i915_private *dev_priv = dev->dev_private;
10839
10840 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10841 DRM_INFO("applying pipe a force quirk\n");
10842 }
10843
10844 /*
10845 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10846 */
10847 static void quirk_ssc_force_disable(struct drm_device *dev)
10848 {
10849 struct drm_i915_private *dev_priv = dev->dev_private;
10850 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10851 DRM_INFO("applying lvds SSC disable quirk\n");
10852 }
10853
10854 /*
10855 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10856 * brightness value
10857 */
10858 static void quirk_invert_brightness(struct drm_device *dev)
10859 {
10860 struct drm_i915_private *dev_priv = dev->dev_private;
10861 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10862 DRM_INFO("applying inverted panel brightness quirk\n");
10863 }
10864
10865 struct intel_quirk {
10866 int device;
10867 int subsystem_vendor;
10868 int subsystem_device;
10869 void (*hook)(struct drm_device *dev);
10870 };
10871
10872 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10873 struct intel_dmi_quirk {
10874 void (*hook)(struct drm_device *dev);
10875 const struct dmi_system_id (*dmi_id_list)[];
10876 };
10877
10878 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10879 {
10880 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10881 return 1;
10882 }
10883
10884 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10885 {
10886 .dmi_id_list = &(const struct dmi_system_id[]) {
10887 {
10888 .callback = intel_dmi_reverse_brightness,
10889 .ident = "NCR Corporation",
10890 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10891 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10892 },
10893 },
10894 { } /* terminating entry */
10895 },
10896 .hook = quirk_invert_brightness,
10897 },
10898 };
10899
10900 static struct intel_quirk intel_quirks[] = {
10901 /* HP Mini needs pipe A force quirk (LP: #322104) */
10902 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10903
10904 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10905 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10906
10907 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10908 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10909
10910 /* 830 needs to leave pipe A & dpll A up */
10911 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10912
10913 /* Lenovo U160 cannot use SSC on LVDS */
10914 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10915
10916 /* Sony Vaio Y cannot use SSC on LVDS */
10917 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10918
10919 /* Acer Aspire 5734Z must invert backlight brightness */
10920 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
10921
10922 /* Acer/eMachines G725 */
10923 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
10924
10925 /* Acer/eMachines e725 */
10926 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
10927
10928 /* Acer/Packard Bell NCL20 */
10929 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
10930
10931 /* Acer Aspire 4736Z */
10932 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
10933
10934 /* Acer Aspire 5336 */
10935 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
10936 };
10937
10938 static void intel_init_quirks(struct drm_device *dev)
10939 {
10940 struct pci_dev *d = dev->pdev;
10941 int i;
10942
10943 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10944 struct intel_quirk *q = &intel_quirks[i];
10945
10946 if (d->device == q->device &&
10947 (d->subsystem_vendor == q->subsystem_vendor ||
10948 q->subsystem_vendor == PCI_ANY_ID) &&
10949 (d->subsystem_device == q->subsystem_device ||
10950 q->subsystem_device == PCI_ANY_ID))
10951 q->hook(dev);
10952 }
10953 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10954 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10955 intel_dmi_quirks[i].hook(dev);
10956 }
10957 }
10958
10959 /* Disable the VGA plane that we never use */
10960 static void i915_disable_vga(struct drm_device *dev)
10961 {
10962 struct drm_i915_private *dev_priv = dev->dev_private;
10963 u8 sr1;
10964 u32 vga_reg = i915_vgacntrl_reg(dev);
10965
10966 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
10967 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10968 outb(SR01, VGA_SR_INDEX);
10969 sr1 = inb(VGA_SR_DATA);
10970 outb(sr1 | 1<<5, VGA_SR_DATA);
10971 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10972 udelay(300);
10973
10974 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10975 POSTING_READ(vga_reg);
10976 }
10977
10978 void intel_modeset_init_hw(struct drm_device *dev)
10979 {
10980 intel_prepare_ddi(dev);
10981
10982 intel_init_clock_gating(dev);
10983
10984 intel_reset_dpio(dev);
10985
10986 mutex_lock(&dev->struct_mutex);
10987 intel_enable_gt_powersave(dev);
10988 mutex_unlock(&dev->struct_mutex);
10989 }
10990
10991 void intel_modeset_suspend_hw(struct drm_device *dev)
10992 {
10993 intel_suspend_hw(dev);
10994 }
10995
10996 void intel_modeset_init(struct drm_device *dev)
10997 {
10998 struct drm_i915_private *dev_priv = dev->dev_private;
10999 int i, j, ret;
11000
11001 drm_mode_config_init(dev);
11002
11003 dev->mode_config.min_width = 0;
11004 dev->mode_config.min_height = 0;
11005
11006 dev->mode_config.preferred_depth = 24;
11007 dev->mode_config.prefer_shadow = 1;
11008
11009 dev->mode_config.funcs = &intel_mode_funcs;
11010
11011 intel_init_quirks(dev);
11012
11013 intel_init_pm(dev);
11014
11015 if (INTEL_INFO(dev)->num_pipes == 0)
11016 return;
11017
11018 intel_init_display(dev);
11019
11020 if (IS_GEN2(dev)) {
11021 dev->mode_config.max_width = 2048;
11022 dev->mode_config.max_height = 2048;
11023 } else if (IS_GEN3(dev)) {
11024 dev->mode_config.max_width = 4096;
11025 dev->mode_config.max_height = 4096;
11026 } else {
11027 dev->mode_config.max_width = 8192;
11028 dev->mode_config.max_height = 8192;
11029 }
11030 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11031
11032 DRM_DEBUG_KMS("%d display pipe%s available.\n",
11033 INTEL_INFO(dev)->num_pipes,
11034 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11035
11036 for_each_pipe(i) {
11037 intel_crtc_init(dev, i);
11038 for (j = 0; j < INTEL_INFO(dev)->num_sprites; j++) {
11039 ret = intel_plane_init(dev, i, j);
11040 if (ret)
11041 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11042 pipe_name(i), sprite_name(i, j), ret);
11043 }
11044 }
11045
11046 intel_init_dpio(dev);
11047 intel_reset_dpio(dev);
11048
11049 intel_cpu_pll_init(dev);
11050 intel_shared_dpll_init(dev);
11051
11052 /* Just disable it once at startup */
11053 i915_disable_vga(dev);
11054 intel_setup_outputs(dev);
11055
11056 /* Just in case the BIOS is doing something questionable. */
11057 intel_disable_fbc(dev);
11058
11059 intel_modeset_setup_hw_state(dev, false);
11060 }
11061
11062 static void
11063 intel_connector_break_all_links(struct intel_connector *connector)
11064 {
11065 connector->base.dpms = DRM_MODE_DPMS_OFF;
11066 connector->base.encoder = NULL;
11067 connector->encoder->connectors_active = false;
11068 connector->encoder->base.crtc = NULL;
11069 }
11070
11071 static void intel_enable_pipe_a(struct drm_device *dev)
11072 {
11073 struct intel_connector *connector;
11074 struct drm_connector *crt = NULL;
11075 struct intel_load_detect_pipe load_detect_temp;
11076
11077 /* We can't just switch on the pipe A, we need to set things up with a
11078 * proper mode and output configuration. As a gross hack, enable pipe A
11079 * by enabling the load detect pipe once. */
11080 list_for_each_entry(connector,
11081 &dev->mode_config.connector_list,
11082 base.head) {
11083 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11084 crt = &connector->base;
11085 break;
11086 }
11087 }
11088
11089 if (!crt)
11090 return;
11091
11092 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11093 intel_release_load_detect_pipe(crt, &load_detect_temp);
11094
11095
11096 }
11097
11098 static bool
11099 intel_check_plane_mapping(struct intel_crtc *crtc)
11100 {
11101 struct drm_device *dev = crtc->base.dev;
11102 struct drm_i915_private *dev_priv = dev->dev_private;
11103 u32 reg, val;
11104
11105 if (INTEL_INFO(dev)->num_pipes == 1)
11106 return true;
11107
11108 reg = DSPCNTR(!crtc->plane);
11109 val = I915_READ(reg);
11110
11111 if ((val & DISPLAY_PLANE_ENABLE) &&
11112 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11113 return false;
11114
11115 return true;
11116 }
11117
11118 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11119 {
11120 struct drm_device *dev = crtc->base.dev;
11121 struct drm_i915_private *dev_priv = dev->dev_private;
11122 u32 reg;
11123
11124 /* Clear any frame start delays used for debugging left by the BIOS */
11125 reg = PIPECONF(crtc->config.cpu_transcoder);
11126 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11127
11128 /* We need to sanitize the plane -> pipe mapping first because this will
11129 * disable the crtc (and hence change the state) if it is wrong. Note
11130 * that gen4+ has a fixed plane -> pipe mapping. */
11131 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11132 struct intel_connector *connector;
11133 bool plane;
11134
11135 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11136 crtc->base.base.id);
11137
11138 /* Pipe has the wrong plane attached and the plane is active.
11139 * Temporarily change the plane mapping and disable everything
11140 * ... */
11141 plane = crtc->plane;
11142 crtc->plane = !plane;
11143 dev_priv->display.crtc_disable(&crtc->base);
11144 crtc->plane = plane;
11145
11146 /* ... and break all links. */
11147 list_for_each_entry(connector, &dev->mode_config.connector_list,
11148 base.head) {
11149 if (connector->encoder->base.crtc != &crtc->base)
11150 continue;
11151
11152 intel_connector_break_all_links(connector);
11153 }
11154
11155 WARN_ON(crtc->active);
11156 crtc->base.enabled = false;
11157 }
11158
11159 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11160 crtc->pipe == PIPE_A && !crtc->active) {
11161 /* BIOS forgot to enable pipe A, this mostly happens after
11162 * resume. Force-enable the pipe to fix this, the update_dpms
11163 * call below we restore the pipe to the right state, but leave
11164 * the required bits on. */
11165 intel_enable_pipe_a(dev);
11166 }
11167
11168 /* Adjust the state of the output pipe according to whether we
11169 * have active connectors/encoders. */
11170 intel_crtc_update_dpms(&crtc->base);
11171
11172 if (crtc->active != crtc->base.enabled) {
11173 struct intel_encoder *encoder;
11174
11175 /* This can happen either due to bugs in the get_hw_state
11176 * functions or because the pipe is force-enabled due to the
11177 * pipe A quirk. */
11178 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11179 crtc->base.base.id,
11180 crtc->base.enabled ? "enabled" : "disabled",
11181 crtc->active ? "enabled" : "disabled");
11182
11183 crtc->base.enabled = crtc->active;
11184
11185 /* Because we only establish the connector -> encoder ->
11186 * crtc links if something is active, this means the
11187 * crtc is now deactivated. Break the links. connector
11188 * -> encoder links are only establish when things are
11189 * actually up, hence no need to break them. */
11190 WARN_ON(crtc->active);
11191
11192 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11193 WARN_ON(encoder->connectors_active);
11194 encoder->base.crtc = NULL;
11195 }
11196 }
11197 }
11198
11199 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11200 {
11201 struct intel_connector *connector;
11202 struct drm_device *dev = encoder->base.dev;
11203
11204 /* We need to check both for a crtc link (meaning that the
11205 * encoder is active and trying to read from a pipe) and the
11206 * pipe itself being active. */
11207 bool has_active_crtc = encoder->base.crtc &&
11208 to_intel_crtc(encoder->base.crtc)->active;
11209
11210 if (encoder->connectors_active && !has_active_crtc) {
11211 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11212 encoder->base.base.id,
11213 drm_get_encoder_name(&encoder->base));
11214
11215 /* Connector is active, but has no active pipe. This is
11216 * fallout from our resume register restoring. Disable
11217 * the encoder manually again. */
11218 if (encoder->base.crtc) {
11219 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11220 encoder->base.base.id,
11221 drm_get_encoder_name(&encoder->base));
11222 encoder->disable(encoder);
11223 }
11224
11225 /* Inconsistent output/port/pipe state happens presumably due to
11226 * a bug in one of the get_hw_state functions. Or someplace else
11227 * in our code, like the register restore mess on resume. Clamp
11228 * things to off as a safer default. */
11229 list_for_each_entry(connector,
11230 &dev->mode_config.connector_list,
11231 base.head) {
11232 if (connector->encoder != encoder)
11233 continue;
11234
11235 intel_connector_break_all_links(connector);
11236 }
11237 }
11238 /* Enabled encoders without active connectors will be fixed in
11239 * the crtc fixup. */
11240 }
11241
11242 void i915_redisable_vga(struct drm_device *dev)
11243 {
11244 struct drm_i915_private *dev_priv = dev->dev_private;
11245 u32 vga_reg = i915_vgacntrl_reg(dev);
11246
11247 /* This function can be called both from intel_modeset_setup_hw_state or
11248 * at a very early point in our resume sequence, where the power well
11249 * structures are not yet restored. Since this function is at a very
11250 * paranoid "someone might have enabled VGA while we were not looking"
11251 * level, just check if the power well is enabled instead of trying to
11252 * follow the "don't touch the power well if we don't need it" policy
11253 * the rest of the driver uses. */
11254 if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
11255 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
11256 return;
11257
11258 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11259 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11260 i915_disable_vga(dev);
11261 }
11262 }
11263
11264 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11265 {
11266 struct drm_i915_private *dev_priv = dev->dev_private;
11267 enum pipe pipe;
11268 struct intel_crtc *crtc;
11269 struct intel_encoder *encoder;
11270 struct intel_connector *connector;
11271 int i;
11272
11273 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11274 base.head) {
11275 memset(&crtc->config, 0, sizeof(crtc->config));
11276
11277 crtc->active = dev_priv->display.get_pipe_config(crtc,
11278 &crtc->config);
11279
11280 crtc->base.enabled = crtc->active;
11281 crtc->primary_enabled = crtc->active;
11282
11283 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11284 crtc->base.base.id,
11285 crtc->active ? "enabled" : "disabled");
11286 }
11287
11288 /* FIXME: Smash this into the new shared dpll infrastructure. */
11289 if (HAS_DDI(dev))
11290 intel_ddi_setup_hw_pll_state(dev);
11291
11292 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11293 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11294
11295 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11296 pll->active = 0;
11297 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11298 base.head) {
11299 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11300 pll->active++;
11301 }
11302 pll->refcount = pll->active;
11303
11304 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11305 pll->name, pll->refcount, pll->on);
11306 }
11307
11308 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11309 base.head) {
11310 pipe = 0;
11311
11312 if (encoder->get_hw_state(encoder, &pipe)) {
11313 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11314 encoder->base.crtc = &crtc->base;
11315 encoder->get_config(encoder, &crtc->config);
11316 } else {
11317 encoder->base.crtc = NULL;
11318 }
11319
11320 encoder->connectors_active = false;
11321 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11322 encoder->base.base.id,
11323 drm_get_encoder_name(&encoder->base),
11324 encoder->base.crtc ? "enabled" : "disabled",
11325 pipe_name(pipe));
11326 }
11327
11328 list_for_each_entry(connector, &dev->mode_config.connector_list,
11329 base.head) {
11330 if (connector->get_hw_state(connector)) {
11331 connector->base.dpms = DRM_MODE_DPMS_ON;
11332 connector->encoder->connectors_active = true;
11333 connector->base.encoder = &connector->encoder->base;
11334 } else {
11335 connector->base.dpms = DRM_MODE_DPMS_OFF;
11336 connector->base.encoder = NULL;
11337 }
11338 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11339 connector->base.base.id,
11340 drm_get_connector_name(&connector->base),
11341 connector->base.encoder ? "enabled" : "disabled");
11342 }
11343 }
11344
11345 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11346 * and i915 state tracking structures. */
11347 void intel_modeset_setup_hw_state(struct drm_device *dev,
11348 bool force_restore)
11349 {
11350 struct drm_i915_private *dev_priv = dev->dev_private;
11351 enum pipe pipe;
11352 struct intel_crtc *crtc;
11353 struct intel_encoder *encoder;
11354 int i;
11355
11356 intel_modeset_readout_hw_state(dev);
11357
11358 /*
11359 * Now that we have the config, copy it to each CRTC struct
11360 * Note that this could go away if we move to using crtc_config
11361 * checking everywhere.
11362 */
11363 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11364 base.head) {
11365 if (crtc->active && i915.fastboot) {
11366 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
11367 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11368 crtc->base.base.id);
11369 drm_mode_debug_printmodeline(&crtc->base.mode);
11370 }
11371 }
11372
11373 /* HW state is read out, now we need to sanitize this mess. */
11374 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11375 base.head) {
11376 intel_sanitize_encoder(encoder);
11377 }
11378
11379 for_each_pipe(pipe) {
11380 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11381 intel_sanitize_crtc(crtc);
11382 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11383 }
11384
11385 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11386 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11387
11388 if (!pll->on || pll->active)
11389 continue;
11390
11391 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11392
11393 pll->disable(dev_priv, pll);
11394 pll->on = false;
11395 }
11396
11397 if (HAS_PCH_SPLIT(dev))
11398 ilk_wm_get_hw_state(dev);
11399
11400 if (force_restore) {
11401 i915_redisable_vga(dev);
11402
11403 /*
11404 * We need to use raw interfaces for restoring state to avoid
11405 * checking (bogus) intermediate states.
11406 */
11407 for_each_pipe(pipe) {
11408 struct drm_crtc *crtc =
11409 dev_priv->pipe_to_crtc_mapping[pipe];
11410
11411 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11412 crtc->fb);
11413 }
11414 } else {
11415 intel_modeset_update_staged_output_state(dev);
11416 }
11417
11418 intel_modeset_check_state(dev);
11419 }
11420
11421 void intel_modeset_gem_init(struct drm_device *dev)
11422 {
11423 intel_modeset_init_hw(dev);
11424
11425 intel_setup_overlay(dev);
11426 }
11427
11428 void intel_connector_unregister(struct intel_connector *intel_connector)
11429 {
11430 struct drm_connector *connector = &intel_connector->base;
11431
11432 intel_panel_destroy_backlight(connector);
11433 drm_sysfs_connector_remove(connector);
11434 }
11435
11436 void intel_modeset_cleanup(struct drm_device *dev)
11437 {
11438 struct drm_i915_private *dev_priv = dev->dev_private;
11439 struct drm_crtc *crtc;
11440 struct drm_connector *connector;
11441
11442 /*
11443 * Interrupts and polling as the first thing to avoid creating havoc.
11444 * Too much stuff here (turning of rps, connectors, ...) would
11445 * experience fancy races otherwise.
11446 */
11447 drm_irq_uninstall(dev);
11448 cancel_work_sync(&dev_priv->hotplug_work);
11449 /*
11450 * Due to the hpd irq storm handling the hotplug work can re-arm the
11451 * poll handlers. Hence disable polling after hpd handling is shut down.
11452 */
11453 drm_kms_helper_poll_fini(dev);
11454
11455 mutex_lock(&dev->struct_mutex);
11456
11457 intel_unregister_dsm_handler();
11458
11459 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11460 /* Skip inactive CRTCs */
11461 if (!crtc->fb)
11462 continue;
11463
11464 intel_increase_pllclock(crtc);
11465 }
11466
11467 intel_disable_fbc(dev);
11468
11469 intel_disable_gt_powersave(dev);
11470
11471 ironlake_teardown_rc6(dev);
11472
11473 mutex_unlock(&dev->struct_mutex);
11474
11475 /* flush any delayed tasks or pending work */
11476 flush_scheduled_work();
11477
11478 /* destroy the backlight and sysfs files before encoders/connectors */
11479 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11480 struct intel_connector *intel_connector;
11481
11482 intel_connector = to_intel_connector(connector);
11483 intel_connector->unregister(intel_connector);
11484 }
11485
11486 drm_mode_config_cleanup(dev);
11487
11488 intel_cleanup_overlay(dev);
11489 }
11490
11491 /*
11492 * Return which encoder is currently attached for connector.
11493 */
11494 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11495 {
11496 return &intel_attached_encoder(connector)->base;
11497 }
11498
11499 void intel_connector_attach_encoder(struct intel_connector *connector,
11500 struct intel_encoder *encoder)
11501 {
11502 connector->encoder = encoder;
11503 drm_mode_connector_attach_encoder(&connector->base,
11504 &encoder->base);
11505 }
11506
11507 /*
11508 * set vga decode state - true == enable VGA decode
11509 */
11510 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11511 {
11512 struct drm_i915_private *dev_priv = dev->dev_private;
11513 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
11514 u16 gmch_ctrl;
11515
11516 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
11517 DRM_ERROR("failed to read control word\n");
11518 return -EIO;
11519 }
11520
11521 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
11522 return 0;
11523
11524 if (state)
11525 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11526 else
11527 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11528
11529 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
11530 DRM_ERROR("failed to write control word\n");
11531 return -EIO;
11532 }
11533
11534 return 0;
11535 }
11536
11537 struct intel_display_error_state {
11538
11539 u32 power_well_driver;
11540
11541 int num_transcoders;
11542
11543 struct intel_cursor_error_state {
11544 u32 control;
11545 u32 position;
11546 u32 base;
11547 u32 size;
11548 } cursor[I915_MAX_PIPES];
11549
11550 struct intel_pipe_error_state {
11551 bool power_domain_on;
11552 u32 source;
11553 } pipe[I915_MAX_PIPES];
11554
11555 struct intel_plane_error_state {
11556 u32 control;
11557 u32 stride;
11558 u32 size;
11559 u32 pos;
11560 u32 addr;
11561 u32 surface;
11562 u32 tile_offset;
11563 } plane[I915_MAX_PIPES];
11564
11565 struct intel_transcoder_error_state {
11566 bool power_domain_on;
11567 enum transcoder cpu_transcoder;
11568
11569 u32 conf;
11570
11571 u32 htotal;
11572 u32 hblank;
11573 u32 hsync;
11574 u32 vtotal;
11575 u32 vblank;
11576 u32 vsync;
11577 } transcoder[4];
11578 };
11579
11580 struct intel_display_error_state *
11581 intel_display_capture_error_state(struct drm_device *dev)
11582 {
11583 drm_i915_private_t *dev_priv = dev->dev_private;
11584 struct intel_display_error_state *error;
11585 int transcoders[] = {
11586 TRANSCODER_A,
11587 TRANSCODER_B,
11588 TRANSCODER_C,
11589 TRANSCODER_EDP,
11590 };
11591 int i;
11592
11593 if (INTEL_INFO(dev)->num_pipes == 0)
11594 return NULL;
11595
11596 error = kzalloc(sizeof(*error), GFP_ATOMIC);
11597 if (error == NULL)
11598 return NULL;
11599
11600 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11601 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11602
11603 for_each_pipe(i) {
11604 error->pipe[i].power_domain_on =
11605 intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i));
11606 if (!error->pipe[i].power_domain_on)
11607 continue;
11608
11609 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11610 error->cursor[i].control = I915_READ(CURCNTR(i));
11611 error->cursor[i].position = I915_READ(CURPOS(i));
11612 error->cursor[i].base = I915_READ(CURBASE(i));
11613 } else {
11614 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11615 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11616 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11617 }
11618
11619 error->plane[i].control = I915_READ(DSPCNTR(i));
11620 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11621 if (INTEL_INFO(dev)->gen <= 3) {
11622 error->plane[i].size = I915_READ(DSPSIZE(i));
11623 error->plane[i].pos = I915_READ(DSPPOS(i));
11624 }
11625 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11626 error->plane[i].addr = I915_READ(DSPADDR(i));
11627 if (INTEL_INFO(dev)->gen >= 4) {
11628 error->plane[i].surface = I915_READ(DSPSURF(i));
11629 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11630 }
11631
11632 error->pipe[i].source = I915_READ(PIPESRC(i));
11633 }
11634
11635 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11636 if (HAS_DDI(dev_priv->dev))
11637 error->num_transcoders++; /* Account for eDP. */
11638
11639 for (i = 0; i < error->num_transcoders; i++) {
11640 enum transcoder cpu_transcoder = transcoders[i];
11641
11642 error->transcoder[i].power_domain_on =
11643 intel_display_power_enabled_sw(dev,
11644 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
11645 if (!error->transcoder[i].power_domain_on)
11646 continue;
11647
11648 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11649
11650 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11651 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11652 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11653 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11654 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11655 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11656 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
11657 }
11658
11659 return error;
11660 }
11661
11662 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11663
11664 void
11665 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11666 struct drm_device *dev,
11667 struct intel_display_error_state *error)
11668 {
11669 int i;
11670
11671 if (!error)
11672 return;
11673
11674 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
11675 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11676 err_printf(m, "PWR_WELL_CTL2: %08x\n",
11677 error->power_well_driver);
11678 for_each_pipe(i) {
11679 err_printf(m, "Pipe [%d]:\n", i);
11680 err_printf(m, " Power: %s\n",
11681 error->pipe[i].power_domain_on ? "on" : "off");
11682 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
11683
11684 err_printf(m, "Plane [%d]:\n", i);
11685 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
11686 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
11687 if (INTEL_INFO(dev)->gen <= 3) {
11688 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
11689 err_printf(m, " POS: %08x\n", error->plane[i].pos);
11690 }
11691 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11692 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
11693 if (INTEL_INFO(dev)->gen >= 4) {
11694 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
11695 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
11696 }
11697
11698 err_printf(m, "Cursor [%d]:\n", i);
11699 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
11700 err_printf(m, " POS: %08x\n", error->cursor[i].position);
11701 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
11702 }
11703
11704 for (i = 0; i < error->num_transcoders; i++) {
11705 err_printf(m, "CPU transcoder: %c\n",
11706 transcoder_name(error->transcoder[i].cpu_transcoder));
11707 err_printf(m, " Power: %s\n",
11708 error->transcoder[i].power_domain_on ? "on" : "off");
11709 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
11710 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
11711 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
11712 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
11713 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
11714 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
11715 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
11716 }
11717 }
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