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Merge branch 'common/fbdev' of master.kernel.org:/pub/scm/linux/kernel/git/lethal...
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
33 #include "drmP.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
39
40 #include "drm_crtc_helper.h"
41
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43
44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
45 static void intel_update_watermarks(struct drm_device *dev);
46 static void intel_increase_pllclock(struct drm_crtc *crtc);
47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
48
49 typedef struct {
50 /* given values */
51 int n;
52 int m1, m2;
53 int p1, p2;
54 /* derived values */
55 int dot;
56 int vco;
57 int m;
58 int p;
59 } intel_clock_t;
60
61 typedef struct {
62 int min, max;
63 } intel_range_t;
64
65 typedef struct {
66 int dot_limit;
67 int p2_slow, p2_fast;
68 } intel_p2_t;
69
70 #define INTEL_P2_NUM 2
71 typedef struct intel_limit intel_limit_t;
72 struct intel_limit {
73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 intel_p2_t p2;
75 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
77 };
78
79 #define I8XX_DOT_MIN 25000
80 #define I8XX_DOT_MAX 350000
81 #define I8XX_VCO_MIN 930000
82 #define I8XX_VCO_MAX 1400000
83 #define I8XX_N_MIN 3
84 #define I8XX_N_MAX 16
85 #define I8XX_M_MIN 96
86 #define I8XX_M_MAX 140
87 #define I8XX_M1_MIN 18
88 #define I8XX_M1_MAX 26
89 #define I8XX_M2_MIN 6
90 #define I8XX_M2_MAX 16
91 #define I8XX_P_MIN 4
92 #define I8XX_P_MAX 128
93 #define I8XX_P1_MIN 2
94 #define I8XX_P1_MAX 33
95 #define I8XX_P1_LVDS_MIN 1
96 #define I8XX_P1_LVDS_MAX 6
97 #define I8XX_P2_SLOW 4
98 #define I8XX_P2_FAST 2
99 #define I8XX_P2_LVDS_SLOW 14
100 #define I8XX_P2_LVDS_FAST 7
101 #define I8XX_P2_SLOW_LIMIT 165000
102
103 #define I9XX_DOT_MIN 20000
104 #define I9XX_DOT_MAX 400000
105 #define I9XX_VCO_MIN 1400000
106 #define I9XX_VCO_MAX 2800000
107 #define PINEVIEW_VCO_MIN 1700000
108 #define PINEVIEW_VCO_MAX 3500000
109 #define I9XX_N_MIN 1
110 #define I9XX_N_MAX 6
111 /* Pineview's Ncounter is a ring counter */
112 #define PINEVIEW_N_MIN 3
113 #define PINEVIEW_N_MAX 6
114 #define I9XX_M_MIN 70
115 #define I9XX_M_MAX 120
116 #define PINEVIEW_M_MIN 2
117 #define PINEVIEW_M_MAX 256
118 #define I9XX_M1_MIN 10
119 #define I9XX_M1_MAX 22
120 #define I9XX_M2_MIN 5
121 #define I9XX_M2_MAX 9
122 /* Pineview M1 is reserved, and must be 0 */
123 #define PINEVIEW_M1_MIN 0
124 #define PINEVIEW_M1_MAX 0
125 #define PINEVIEW_M2_MIN 0
126 #define PINEVIEW_M2_MAX 254
127 #define I9XX_P_SDVO_DAC_MIN 5
128 #define I9XX_P_SDVO_DAC_MAX 80
129 #define I9XX_P_LVDS_MIN 7
130 #define I9XX_P_LVDS_MAX 98
131 #define PINEVIEW_P_LVDS_MIN 7
132 #define PINEVIEW_P_LVDS_MAX 112
133 #define I9XX_P1_MIN 1
134 #define I9XX_P1_MAX 8
135 #define I9XX_P2_SDVO_DAC_SLOW 10
136 #define I9XX_P2_SDVO_DAC_FAST 5
137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138 #define I9XX_P2_LVDS_SLOW 14
139 #define I9XX_P2_LVDS_FAST 7
140 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
141
142 /*The parameter is for SDVO on G4x platform*/
143 #define G4X_DOT_SDVO_MIN 25000
144 #define G4X_DOT_SDVO_MAX 270000
145 #define G4X_VCO_MIN 1750000
146 #define G4X_VCO_MAX 3500000
147 #define G4X_N_SDVO_MIN 1
148 #define G4X_N_SDVO_MAX 4
149 #define G4X_M_SDVO_MIN 104
150 #define G4X_M_SDVO_MAX 138
151 #define G4X_M1_SDVO_MIN 17
152 #define G4X_M1_SDVO_MAX 23
153 #define G4X_M2_SDVO_MIN 5
154 #define G4X_M2_SDVO_MAX 11
155 #define G4X_P_SDVO_MIN 10
156 #define G4X_P_SDVO_MAX 30
157 #define G4X_P1_SDVO_MIN 1
158 #define G4X_P1_SDVO_MAX 3
159 #define G4X_P2_SDVO_SLOW 10
160 #define G4X_P2_SDVO_FAST 10
161 #define G4X_P2_SDVO_LIMIT 270000
162
163 /*The parameter is for HDMI_DAC on G4x platform*/
164 #define G4X_DOT_HDMI_DAC_MIN 22000
165 #define G4X_DOT_HDMI_DAC_MAX 400000
166 #define G4X_N_HDMI_DAC_MIN 1
167 #define G4X_N_HDMI_DAC_MAX 4
168 #define G4X_M_HDMI_DAC_MIN 104
169 #define G4X_M_HDMI_DAC_MAX 138
170 #define G4X_M1_HDMI_DAC_MIN 16
171 #define G4X_M1_HDMI_DAC_MAX 23
172 #define G4X_M2_HDMI_DAC_MIN 5
173 #define G4X_M2_HDMI_DAC_MAX 11
174 #define G4X_P_HDMI_DAC_MIN 5
175 #define G4X_P_HDMI_DAC_MAX 80
176 #define G4X_P1_HDMI_DAC_MIN 1
177 #define G4X_P1_HDMI_DAC_MAX 8
178 #define G4X_P2_HDMI_DAC_SLOW 10
179 #define G4X_P2_HDMI_DAC_FAST 5
180 #define G4X_P2_HDMI_DAC_LIMIT 165000
181
182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
200
201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
219
220 /*The parameter is for DISPLAY PORT on G4x platform*/
221 #define G4X_DOT_DISPLAY_PORT_MIN 161670
222 #define G4X_DOT_DISPLAY_PORT_MAX 227000
223 #define G4X_N_DISPLAY_PORT_MIN 1
224 #define G4X_N_DISPLAY_PORT_MAX 2
225 #define G4X_M_DISPLAY_PORT_MIN 97
226 #define G4X_M_DISPLAY_PORT_MAX 108
227 #define G4X_M1_DISPLAY_PORT_MIN 0x10
228 #define G4X_M1_DISPLAY_PORT_MAX 0x12
229 #define G4X_M2_DISPLAY_PORT_MIN 0x05
230 #define G4X_M2_DISPLAY_PORT_MAX 0x06
231 #define G4X_P_DISPLAY_PORT_MIN 10
232 #define G4X_P_DISPLAY_PORT_MAX 20
233 #define G4X_P1_DISPLAY_PORT_MIN 1
234 #define G4X_P1_DISPLAY_PORT_MAX 2
235 #define G4X_P2_DISPLAY_PORT_SLOW 10
236 #define G4X_P2_DISPLAY_PORT_FAST 10
237 #define G4X_P2_DISPLAY_PORT_LIMIT 0
238
239 /* Ironlake / Sandybridge */
240 /* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
242 */
243 #define IRONLAKE_DOT_MIN 25000
244 #define IRONLAKE_DOT_MAX 350000
245 #define IRONLAKE_VCO_MIN 1760000
246 #define IRONLAKE_VCO_MAX 3510000
247 #define IRONLAKE_M1_MIN 12
248 #define IRONLAKE_M1_MAX 22
249 #define IRONLAKE_M2_MIN 5
250 #define IRONLAKE_M2_MAX 9
251 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
252
253 /* We have parameter ranges for different type of outputs. */
254
255 /* DAC & HDMI Refclk 120Mhz */
256 #define IRONLAKE_DAC_N_MIN 1
257 #define IRONLAKE_DAC_N_MAX 5
258 #define IRONLAKE_DAC_M_MIN 79
259 #define IRONLAKE_DAC_M_MAX 127
260 #define IRONLAKE_DAC_P_MIN 5
261 #define IRONLAKE_DAC_P_MAX 80
262 #define IRONLAKE_DAC_P1_MIN 1
263 #define IRONLAKE_DAC_P1_MAX 8
264 #define IRONLAKE_DAC_P2_SLOW 10
265 #define IRONLAKE_DAC_P2_FAST 5
266
267 /* LVDS single-channel 120Mhz refclk */
268 #define IRONLAKE_LVDS_S_N_MIN 1
269 #define IRONLAKE_LVDS_S_N_MAX 3
270 #define IRONLAKE_LVDS_S_M_MIN 79
271 #define IRONLAKE_LVDS_S_M_MAX 118
272 #define IRONLAKE_LVDS_S_P_MIN 28
273 #define IRONLAKE_LVDS_S_P_MAX 112
274 #define IRONLAKE_LVDS_S_P1_MIN 2
275 #define IRONLAKE_LVDS_S_P1_MAX 8
276 #define IRONLAKE_LVDS_S_P2_SLOW 14
277 #define IRONLAKE_LVDS_S_P2_FAST 14
278
279 /* LVDS dual-channel 120Mhz refclk */
280 #define IRONLAKE_LVDS_D_N_MIN 1
281 #define IRONLAKE_LVDS_D_N_MAX 3
282 #define IRONLAKE_LVDS_D_M_MIN 79
283 #define IRONLAKE_LVDS_D_M_MAX 127
284 #define IRONLAKE_LVDS_D_P_MIN 14
285 #define IRONLAKE_LVDS_D_P_MAX 56
286 #define IRONLAKE_LVDS_D_P1_MIN 2
287 #define IRONLAKE_LVDS_D_P1_MAX 8
288 #define IRONLAKE_LVDS_D_P2_SLOW 7
289 #define IRONLAKE_LVDS_D_P2_FAST 7
290
291 /* LVDS single-channel 100Mhz refclk */
292 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
293 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
294 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
295 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
296 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
297 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
298 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
302
303 /* LVDS dual-channel 100Mhz refclk */
304 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
305 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
306 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
307 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
308 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
309 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
310 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
314
315 /* DisplayPort */
316 #define IRONLAKE_DP_N_MIN 1
317 #define IRONLAKE_DP_N_MAX 2
318 #define IRONLAKE_DP_M_MIN 81
319 #define IRONLAKE_DP_M_MAX 90
320 #define IRONLAKE_DP_P_MIN 10
321 #define IRONLAKE_DP_P_MAX 20
322 #define IRONLAKE_DP_P2_FAST 10
323 #define IRONLAKE_DP_P2_SLOW 10
324 #define IRONLAKE_DP_P2_LIMIT 0
325 #define IRONLAKE_DP_P1_MIN 1
326 #define IRONLAKE_DP_P1_MAX 2
327
328 /* FDI */
329 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
330
331 static bool
332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
333 int target, int refclk, intel_clock_t *best_clock);
334 static bool
335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
336 int target, int refclk, intel_clock_t *best_clock);
337
338 static bool
339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
340 int target, int refclk, intel_clock_t *best_clock);
341 static bool
342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
343 int target, int refclk, intel_clock_t *best_clock);
344
345 static inline u32 /* units of 100MHz */
346 intel_fdi_link_freq(struct drm_device *dev)
347 {
348 if (IS_GEN5(dev)) {
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
351 } else
352 return 27;
353 }
354
355 static const intel_limit_t intel_limits_i8xx_dvo = {
356 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
357 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
358 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
359 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
360 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
361 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
362 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
363 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
364 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
365 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
366 .find_pll = intel_find_best_PLL,
367 };
368
369 static const intel_limit_t intel_limits_i8xx_lvds = {
370 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
371 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
372 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
373 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
374 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
375 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
376 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
377 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
378 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
379 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
380 .find_pll = intel_find_best_PLL,
381 };
382
383 static const intel_limit_t intel_limits_i9xx_sdvo = {
384 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
385 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
386 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
387 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
388 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
389 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
390 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
391 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
392 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
393 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
394 .find_pll = intel_find_best_PLL,
395 };
396
397 static const intel_limit_t intel_limits_i9xx_lvds = {
398 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
399 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
400 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
401 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
402 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
403 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
404 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
405 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
406 /* The single-channel range is 25-112Mhz, and dual-channel
407 * is 80-224Mhz. Prefer single channel as much as possible.
408 */
409 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
410 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
411 .find_pll = intel_find_best_PLL,
412 };
413
414 /* below parameter and function is for G4X Chipset Family*/
415 static const intel_limit_t intel_limits_g4x_sdvo = {
416 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
417 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
418 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
419 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
420 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
421 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
422 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
423 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
424 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
425 .p2_slow = G4X_P2_SDVO_SLOW,
426 .p2_fast = G4X_P2_SDVO_FAST
427 },
428 .find_pll = intel_g4x_find_best_PLL,
429 };
430
431 static const intel_limit_t intel_limits_g4x_hdmi = {
432 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
433 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
434 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
435 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
436 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
437 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
438 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
439 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
440 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
441 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
442 .p2_fast = G4X_P2_HDMI_DAC_FAST
443 },
444 .find_pll = intel_g4x_find_best_PLL,
445 };
446
447 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
448 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
449 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
450 .vco = { .min = G4X_VCO_MIN,
451 .max = G4X_VCO_MAX },
452 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
453 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
454 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
455 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
456 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
457 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
458 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
459 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
460 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
461 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
462 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
463 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
464 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
465 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
466 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
467 },
468 .find_pll = intel_g4x_find_best_PLL,
469 };
470
471 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
472 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
473 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
474 .vco = { .min = G4X_VCO_MIN,
475 .max = G4X_VCO_MAX },
476 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
477 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
478 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
479 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
480 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
481 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
482 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
483 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
484 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
485 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
486 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
487 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
488 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
489 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
490 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
491 },
492 .find_pll = intel_g4x_find_best_PLL,
493 };
494
495 static const intel_limit_t intel_limits_g4x_display_port = {
496 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
497 .max = G4X_DOT_DISPLAY_PORT_MAX },
498 .vco = { .min = G4X_VCO_MIN,
499 .max = G4X_VCO_MAX},
500 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
501 .max = G4X_N_DISPLAY_PORT_MAX },
502 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
503 .max = G4X_M_DISPLAY_PORT_MAX },
504 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
505 .max = G4X_M1_DISPLAY_PORT_MAX },
506 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
507 .max = G4X_M2_DISPLAY_PORT_MAX },
508 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
509 .max = G4X_P_DISPLAY_PORT_MAX },
510 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
511 .max = G4X_P1_DISPLAY_PORT_MAX},
512 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
513 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
514 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
515 .find_pll = intel_find_pll_g4x_dp,
516 };
517
518 static const intel_limit_t intel_limits_pineview_sdvo = {
519 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
520 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
521 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
522 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
523 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
524 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
525 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
526 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
527 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
528 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
529 .find_pll = intel_find_best_PLL,
530 };
531
532 static const intel_limit_t intel_limits_pineview_lvds = {
533 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
534 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
535 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
536 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
537 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
538 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
539 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
540 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
541 /* Pineview only supports single-channel mode. */
542 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
543 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
544 .find_pll = intel_find_best_PLL,
545 };
546
547 static const intel_limit_t intel_limits_ironlake_dac = {
548 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
549 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
550 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
551 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
552 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
553 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
554 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
555 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
556 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
557 .p2_slow = IRONLAKE_DAC_P2_SLOW,
558 .p2_fast = IRONLAKE_DAC_P2_FAST },
559 .find_pll = intel_g4x_find_best_PLL,
560 };
561
562 static const intel_limit_t intel_limits_ironlake_single_lvds = {
563 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
564 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
565 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
566 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
567 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
568 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
569 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
570 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
571 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
572 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
573 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
574 .find_pll = intel_g4x_find_best_PLL,
575 };
576
577 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
578 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
579 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
580 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
581 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
582 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
583 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
584 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
585 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
586 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
587 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
588 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
589 .find_pll = intel_g4x_find_best_PLL,
590 };
591
592 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
593 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
594 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
595 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
596 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
597 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
598 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
599 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
600 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
601 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
602 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
603 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
604 .find_pll = intel_g4x_find_best_PLL,
605 };
606
607 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
608 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
609 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
610 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
611 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
612 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
613 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
614 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
615 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
616 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
617 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
618 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
619 .find_pll = intel_g4x_find_best_PLL,
620 };
621
622 static const intel_limit_t intel_limits_ironlake_display_port = {
623 .dot = { .min = IRONLAKE_DOT_MIN,
624 .max = IRONLAKE_DOT_MAX },
625 .vco = { .min = IRONLAKE_VCO_MIN,
626 .max = IRONLAKE_VCO_MAX},
627 .n = { .min = IRONLAKE_DP_N_MIN,
628 .max = IRONLAKE_DP_N_MAX },
629 .m = { .min = IRONLAKE_DP_M_MIN,
630 .max = IRONLAKE_DP_M_MAX },
631 .m1 = { .min = IRONLAKE_M1_MIN,
632 .max = IRONLAKE_M1_MAX },
633 .m2 = { .min = IRONLAKE_M2_MIN,
634 .max = IRONLAKE_M2_MAX },
635 .p = { .min = IRONLAKE_DP_P_MIN,
636 .max = IRONLAKE_DP_P_MAX },
637 .p1 = { .min = IRONLAKE_DP_P1_MIN,
638 .max = IRONLAKE_DP_P1_MAX},
639 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
640 .p2_slow = IRONLAKE_DP_P2_SLOW,
641 .p2_fast = IRONLAKE_DP_P2_FAST },
642 .find_pll = intel_find_pll_ironlake_dp,
643 };
644
645 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
646 int refclk)
647 {
648 struct drm_device *dev = crtc->dev;
649 struct drm_i915_private *dev_priv = dev->dev_private;
650 const intel_limit_t *limit;
651
652 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
653 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
654 LVDS_CLKB_POWER_UP) {
655 /* LVDS dual channel */
656 if (refclk == 100000)
657 limit = &intel_limits_ironlake_dual_lvds_100m;
658 else
659 limit = &intel_limits_ironlake_dual_lvds;
660 } else {
661 if (refclk == 100000)
662 limit = &intel_limits_ironlake_single_lvds_100m;
663 else
664 limit = &intel_limits_ironlake_single_lvds;
665 }
666 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
667 HAS_eDP)
668 limit = &intel_limits_ironlake_display_port;
669 else
670 limit = &intel_limits_ironlake_dac;
671
672 return limit;
673 }
674
675 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
676 {
677 struct drm_device *dev = crtc->dev;
678 struct drm_i915_private *dev_priv = dev->dev_private;
679 const intel_limit_t *limit;
680
681 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
682 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
683 LVDS_CLKB_POWER_UP)
684 /* LVDS with dual channel */
685 limit = &intel_limits_g4x_dual_channel_lvds;
686 else
687 /* LVDS with dual channel */
688 limit = &intel_limits_g4x_single_channel_lvds;
689 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
690 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
691 limit = &intel_limits_g4x_hdmi;
692 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
693 limit = &intel_limits_g4x_sdvo;
694 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
695 limit = &intel_limits_g4x_display_port;
696 } else /* The option is for other outputs */
697 limit = &intel_limits_i9xx_sdvo;
698
699 return limit;
700 }
701
702 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
703 {
704 struct drm_device *dev = crtc->dev;
705 const intel_limit_t *limit;
706
707 if (HAS_PCH_SPLIT(dev))
708 limit = intel_ironlake_limit(crtc, refclk);
709 else if (IS_G4X(dev)) {
710 limit = intel_g4x_limit(crtc);
711 } else if (IS_PINEVIEW(dev)) {
712 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
713 limit = &intel_limits_pineview_lvds;
714 else
715 limit = &intel_limits_pineview_sdvo;
716 } else if (!IS_GEN2(dev)) {
717 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
718 limit = &intel_limits_i9xx_lvds;
719 else
720 limit = &intel_limits_i9xx_sdvo;
721 } else {
722 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
723 limit = &intel_limits_i8xx_lvds;
724 else
725 limit = &intel_limits_i8xx_dvo;
726 }
727 return limit;
728 }
729
730 /* m1 is reserved as 0 in Pineview, n is a ring counter */
731 static void pineview_clock(int refclk, intel_clock_t *clock)
732 {
733 clock->m = clock->m2 + 2;
734 clock->p = clock->p1 * clock->p2;
735 clock->vco = refclk * clock->m / clock->n;
736 clock->dot = clock->vco / clock->p;
737 }
738
739 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
740 {
741 if (IS_PINEVIEW(dev)) {
742 pineview_clock(refclk, clock);
743 return;
744 }
745 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
746 clock->p = clock->p1 * clock->p2;
747 clock->vco = refclk * clock->m / (clock->n + 2);
748 clock->dot = clock->vco / clock->p;
749 }
750
751 /**
752 * Returns whether any output on the specified pipe is of the specified type
753 */
754 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
755 {
756 struct drm_device *dev = crtc->dev;
757 struct drm_mode_config *mode_config = &dev->mode_config;
758 struct intel_encoder *encoder;
759
760 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
761 if (encoder->base.crtc == crtc && encoder->type == type)
762 return true;
763
764 return false;
765 }
766
767 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
768 /**
769 * Returns whether the given set of divisors are valid for a given refclk with
770 * the given connectors.
771 */
772
773 static bool intel_PLL_is_valid(struct drm_device *dev,
774 const intel_limit_t *limit,
775 const intel_clock_t *clock)
776 {
777 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
778 INTELPllInvalid ("p1 out of range\n");
779 if (clock->p < limit->p.min || limit->p.max < clock->p)
780 INTELPllInvalid ("p out of range\n");
781 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
782 INTELPllInvalid ("m2 out of range\n");
783 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
784 INTELPllInvalid ("m1 out of range\n");
785 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
786 INTELPllInvalid ("m1 <= m2\n");
787 if (clock->m < limit->m.min || limit->m.max < clock->m)
788 INTELPllInvalid ("m out of range\n");
789 if (clock->n < limit->n.min || limit->n.max < clock->n)
790 INTELPllInvalid ("n out of range\n");
791 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
792 INTELPllInvalid ("vco out of range\n");
793 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
794 * connector, etc., rather than just a single range.
795 */
796 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
797 INTELPllInvalid ("dot out of range\n");
798
799 return true;
800 }
801
802 static bool
803 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
804 int target, int refclk, intel_clock_t *best_clock)
805
806 {
807 struct drm_device *dev = crtc->dev;
808 struct drm_i915_private *dev_priv = dev->dev_private;
809 intel_clock_t clock;
810 int err = target;
811
812 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
813 (I915_READ(LVDS)) != 0) {
814 /*
815 * For LVDS, if the panel is on, just rely on its current
816 * settings for dual-channel. We haven't figured out how to
817 * reliably set up different single/dual channel state, if we
818 * even can.
819 */
820 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
821 LVDS_CLKB_POWER_UP)
822 clock.p2 = limit->p2.p2_fast;
823 else
824 clock.p2 = limit->p2.p2_slow;
825 } else {
826 if (target < limit->p2.dot_limit)
827 clock.p2 = limit->p2.p2_slow;
828 else
829 clock.p2 = limit->p2.p2_fast;
830 }
831
832 memset (best_clock, 0, sizeof (*best_clock));
833
834 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
835 clock.m1++) {
836 for (clock.m2 = limit->m2.min;
837 clock.m2 <= limit->m2.max; clock.m2++) {
838 /* m1 is always 0 in Pineview */
839 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
840 break;
841 for (clock.n = limit->n.min;
842 clock.n <= limit->n.max; clock.n++) {
843 for (clock.p1 = limit->p1.min;
844 clock.p1 <= limit->p1.max; clock.p1++) {
845 int this_err;
846
847 intel_clock(dev, refclk, &clock);
848 if (!intel_PLL_is_valid(dev, limit,
849 &clock))
850 continue;
851
852 this_err = abs(clock.dot - target);
853 if (this_err < err) {
854 *best_clock = clock;
855 err = this_err;
856 }
857 }
858 }
859 }
860 }
861
862 return (err != target);
863 }
864
865 static bool
866 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
867 int target, int refclk, intel_clock_t *best_clock)
868 {
869 struct drm_device *dev = crtc->dev;
870 struct drm_i915_private *dev_priv = dev->dev_private;
871 intel_clock_t clock;
872 int max_n;
873 bool found;
874 /* approximately equals target * 0.00585 */
875 int err_most = (target >> 8) + (target >> 9);
876 found = false;
877
878 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
879 int lvds_reg;
880
881 if (HAS_PCH_SPLIT(dev))
882 lvds_reg = PCH_LVDS;
883 else
884 lvds_reg = LVDS;
885 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
886 LVDS_CLKB_POWER_UP)
887 clock.p2 = limit->p2.p2_fast;
888 else
889 clock.p2 = limit->p2.p2_slow;
890 } else {
891 if (target < limit->p2.dot_limit)
892 clock.p2 = limit->p2.p2_slow;
893 else
894 clock.p2 = limit->p2.p2_fast;
895 }
896
897 memset(best_clock, 0, sizeof(*best_clock));
898 max_n = limit->n.max;
899 /* based on hardware requirement, prefer smaller n to precision */
900 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
901 /* based on hardware requirement, prefere larger m1,m2 */
902 for (clock.m1 = limit->m1.max;
903 clock.m1 >= limit->m1.min; clock.m1--) {
904 for (clock.m2 = limit->m2.max;
905 clock.m2 >= limit->m2.min; clock.m2--) {
906 for (clock.p1 = limit->p1.max;
907 clock.p1 >= limit->p1.min; clock.p1--) {
908 int this_err;
909
910 intel_clock(dev, refclk, &clock);
911 if (!intel_PLL_is_valid(dev, limit,
912 &clock))
913 continue;
914
915 this_err = abs(clock.dot - target);
916 if (this_err < err_most) {
917 *best_clock = clock;
918 err_most = this_err;
919 max_n = clock.n;
920 found = true;
921 }
922 }
923 }
924 }
925 }
926 return found;
927 }
928
929 static bool
930 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
931 int target, int refclk, intel_clock_t *best_clock)
932 {
933 struct drm_device *dev = crtc->dev;
934 intel_clock_t clock;
935
936 if (target < 200000) {
937 clock.n = 1;
938 clock.p1 = 2;
939 clock.p2 = 10;
940 clock.m1 = 12;
941 clock.m2 = 9;
942 } else {
943 clock.n = 2;
944 clock.p1 = 1;
945 clock.p2 = 10;
946 clock.m1 = 14;
947 clock.m2 = 8;
948 }
949 intel_clock(dev, refclk, &clock);
950 memcpy(best_clock, &clock, sizeof(intel_clock_t));
951 return true;
952 }
953
954 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
955 static bool
956 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
957 int target, int refclk, intel_clock_t *best_clock)
958 {
959 intel_clock_t clock;
960 if (target < 200000) {
961 clock.p1 = 2;
962 clock.p2 = 10;
963 clock.n = 2;
964 clock.m1 = 23;
965 clock.m2 = 8;
966 } else {
967 clock.p1 = 1;
968 clock.p2 = 10;
969 clock.n = 1;
970 clock.m1 = 14;
971 clock.m2 = 2;
972 }
973 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
974 clock.p = (clock.p1 * clock.p2);
975 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
976 clock.vco = 0;
977 memcpy(best_clock, &clock, sizeof(intel_clock_t));
978 return true;
979 }
980
981 /**
982 * intel_wait_for_vblank - wait for vblank on a given pipe
983 * @dev: drm device
984 * @pipe: pipe to wait for
985 *
986 * Wait for vblank to occur on a given pipe. Needed for various bits of
987 * mode setting code.
988 */
989 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
990 {
991 struct drm_i915_private *dev_priv = dev->dev_private;
992 int pipestat_reg = PIPESTAT(pipe);
993
994 /* Clear existing vblank status. Note this will clear any other
995 * sticky status fields as well.
996 *
997 * This races with i915_driver_irq_handler() with the result
998 * that either function could miss a vblank event. Here it is not
999 * fatal, as we will either wait upon the next vblank interrupt or
1000 * timeout. Generally speaking intel_wait_for_vblank() is only
1001 * called during modeset at which time the GPU should be idle and
1002 * should *not* be performing page flips and thus not waiting on
1003 * vblanks...
1004 * Currently, the result of us stealing a vblank from the irq
1005 * handler is that a single frame will be skipped during swapbuffers.
1006 */
1007 I915_WRITE(pipestat_reg,
1008 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1009
1010 /* Wait for vblank interrupt bit to set */
1011 if (wait_for(I915_READ(pipestat_reg) &
1012 PIPE_VBLANK_INTERRUPT_STATUS,
1013 50))
1014 DRM_DEBUG_KMS("vblank wait timed out\n");
1015 }
1016
1017 /*
1018 * intel_wait_for_pipe_off - wait for pipe to turn off
1019 * @dev: drm device
1020 * @pipe: pipe to wait for
1021 *
1022 * After disabling a pipe, we can't wait for vblank in the usual way,
1023 * spinning on the vblank interrupt status bit, since we won't actually
1024 * see an interrupt when the pipe is disabled.
1025 *
1026 * On Gen4 and above:
1027 * wait for the pipe register state bit to turn off
1028 *
1029 * Otherwise:
1030 * wait for the display line value to settle (it usually
1031 * ends up stopping at the start of the next frame).
1032 *
1033 */
1034 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1035 {
1036 struct drm_i915_private *dev_priv = dev->dev_private;
1037
1038 if (INTEL_INFO(dev)->gen >= 4) {
1039 int reg = PIPECONF(pipe);
1040
1041 /* Wait for the Pipe State to go off */
1042 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1043 100))
1044 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1045 } else {
1046 u32 last_line;
1047 int reg = PIPEDSL(pipe);
1048 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1049
1050 /* Wait for the display line to settle */
1051 do {
1052 last_line = I915_READ(reg) & DSL_LINEMASK;
1053 mdelay(5);
1054 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
1055 time_after(timeout, jiffies));
1056 if (time_after(jiffies, timeout))
1057 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1058 }
1059 }
1060
1061 static const char *state_string(bool enabled)
1062 {
1063 return enabled ? "on" : "off";
1064 }
1065
1066 /* Only for pre-ILK configs */
1067 static void assert_pll(struct drm_i915_private *dev_priv,
1068 enum pipe pipe, bool state)
1069 {
1070 int reg;
1071 u32 val;
1072 bool cur_state;
1073
1074 reg = DPLL(pipe);
1075 val = I915_READ(reg);
1076 cur_state = !!(val & DPLL_VCO_ENABLE);
1077 WARN(cur_state != state,
1078 "PLL state assertion failure (expected %s, current %s)\n",
1079 state_string(state), state_string(cur_state));
1080 }
1081 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1082 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1083
1084 /* For ILK+ */
1085 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1086 enum pipe pipe, bool state)
1087 {
1088 int reg;
1089 u32 val;
1090 bool cur_state;
1091
1092 reg = PCH_DPLL(pipe);
1093 val = I915_READ(reg);
1094 cur_state = !!(val & DPLL_VCO_ENABLE);
1095 WARN(cur_state != state,
1096 "PCH PLL state assertion failure (expected %s, current %s)\n",
1097 state_string(state), state_string(cur_state));
1098 }
1099 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
1100 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
1101
1102 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1103 enum pipe pipe, bool state)
1104 {
1105 int reg;
1106 u32 val;
1107 bool cur_state;
1108
1109 reg = FDI_TX_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & FDI_TX_ENABLE);
1112 WARN(cur_state != state,
1113 "FDI TX state assertion failure (expected %s, current %s)\n",
1114 state_string(state), state_string(cur_state));
1115 }
1116 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1117 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1118
1119 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1120 enum pipe pipe, bool state)
1121 {
1122 int reg;
1123 u32 val;
1124 bool cur_state;
1125
1126 reg = FDI_RX_CTL(pipe);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & FDI_RX_ENABLE);
1129 WARN(cur_state != state,
1130 "FDI RX state assertion failure (expected %s, current %s)\n",
1131 state_string(state), state_string(cur_state));
1132 }
1133 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1134 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1135
1136 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1137 enum pipe pipe)
1138 {
1139 int reg;
1140 u32 val;
1141
1142 /* ILK FDI PLL is always enabled */
1143 if (dev_priv->info->gen == 5)
1144 return;
1145
1146 reg = FDI_TX_CTL(pipe);
1147 val = I915_READ(reg);
1148 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1149 }
1150
1151 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1152 enum pipe pipe)
1153 {
1154 int reg;
1155 u32 val;
1156
1157 reg = FDI_RX_CTL(pipe);
1158 val = I915_READ(reg);
1159 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1160 }
1161
1162 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1163 enum pipe pipe)
1164 {
1165 int pp_reg, lvds_reg;
1166 u32 val;
1167 enum pipe panel_pipe = PIPE_A;
1168 bool locked = locked;
1169
1170 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1171 pp_reg = PCH_PP_CONTROL;
1172 lvds_reg = PCH_LVDS;
1173 } else {
1174 pp_reg = PP_CONTROL;
1175 lvds_reg = LVDS;
1176 }
1177
1178 val = I915_READ(pp_reg);
1179 if (!(val & PANEL_POWER_ON) ||
1180 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1181 locked = false;
1182
1183 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1184 panel_pipe = PIPE_B;
1185
1186 WARN(panel_pipe == pipe && locked,
1187 "panel assertion failure, pipe %c regs locked\n",
1188 pipe_name(pipe));
1189 }
1190
1191 static void assert_pipe(struct drm_i915_private *dev_priv,
1192 enum pipe pipe, bool state)
1193 {
1194 int reg;
1195 u32 val;
1196 bool cur_state;
1197
1198 reg = PIPECONF(pipe);
1199 val = I915_READ(reg);
1200 cur_state = !!(val & PIPECONF_ENABLE);
1201 WARN(cur_state != state,
1202 "pipe %c assertion failure (expected %s, current %s)\n",
1203 pipe_name(pipe), state_string(state), state_string(cur_state));
1204 }
1205 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1206 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1207
1208 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
1209 enum plane plane)
1210 {
1211 int reg;
1212 u32 val;
1213
1214 reg = DSPCNTR(plane);
1215 val = I915_READ(reg);
1216 WARN(!(val & DISPLAY_PLANE_ENABLE),
1217 "plane %c assertion failure, should be active but is disabled\n",
1218 plane_name(plane));
1219 }
1220
1221 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1222 enum pipe pipe)
1223 {
1224 int reg, i;
1225 u32 val;
1226 int cur_pipe;
1227
1228 /* Planes are fixed to pipes on ILK+ */
1229 if (HAS_PCH_SPLIT(dev_priv->dev))
1230 return;
1231
1232 /* Need to check both planes against the pipe */
1233 for (i = 0; i < 2; i++) {
1234 reg = DSPCNTR(i);
1235 val = I915_READ(reg);
1236 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1237 DISPPLANE_SEL_PIPE_SHIFT;
1238 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1239 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1240 plane_name(i), pipe_name(pipe));
1241 }
1242 }
1243
1244 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1245 {
1246 u32 val;
1247 bool enabled;
1248
1249 val = I915_READ(PCH_DREF_CONTROL);
1250 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1251 DREF_SUPERSPREAD_SOURCE_MASK));
1252 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1253 }
1254
1255 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1256 enum pipe pipe)
1257 {
1258 int reg;
1259 u32 val;
1260 bool enabled;
1261
1262 reg = TRANSCONF(pipe);
1263 val = I915_READ(reg);
1264 enabled = !!(val & TRANS_ENABLE);
1265 WARN(enabled,
1266 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1267 pipe_name(pipe));
1268 }
1269
1270 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1271 enum pipe pipe, int reg)
1272 {
1273 u32 val = I915_READ(reg);
1274 WARN(DP_PIPE_ENABLED(val, pipe),
1275 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1276 reg, pipe_name(pipe));
1277 }
1278
1279 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1280 enum pipe pipe, int reg)
1281 {
1282 u32 val = I915_READ(reg);
1283 WARN(HDMI_PIPE_ENABLED(val, pipe),
1284 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1285 reg, pipe_name(pipe));
1286 }
1287
1288 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1289 enum pipe pipe)
1290 {
1291 int reg;
1292 u32 val;
1293
1294 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
1295 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
1296 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
1297
1298 reg = PCH_ADPA;
1299 val = I915_READ(reg);
1300 WARN(ADPA_PIPE_ENABLED(val, pipe),
1301 "PCH VGA enabled on transcoder %c, should be disabled\n",
1302 pipe_name(pipe));
1303
1304 reg = PCH_LVDS;
1305 val = I915_READ(reg);
1306 WARN(LVDS_PIPE_ENABLED(val, pipe),
1307 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1308 pipe_name(pipe));
1309
1310 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1311 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1312 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1313 }
1314
1315 /**
1316 * intel_enable_pll - enable a PLL
1317 * @dev_priv: i915 private structure
1318 * @pipe: pipe PLL to enable
1319 *
1320 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1321 * make sure the PLL reg is writable first though, since the panel write
1322 * protect mechanism may be enabled.
1323 *
1324 * Note! This is for pre-ILK only.
1325 */
1326 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1327 {
1328 int reg;
1329 u32 val;
1330
1331 /* No really, not for ILK+ */
1332 BUG_ON(dev_priv->info->gen >= 5);
1333
1334 /* PLL is protected by panel, make sure we can write it */
1335 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1336 assert_panel_unlocked(dev_priv, pipe);
1337
1338 reg = DPLL(pipe);
1339 val = I915_READ(reg);
1340 val |= DPLL_VCO_ENABLE;
1341
1342 /* We do this three times for luck */
1343 I915_WRITE(reg, val);
1344 POSTING_READ(reg);
1345 udelay(150); /* wait for warmup */
1346 I915_WRITE(reg, val);
1347 POSTING_READ(reg);
1348 udelay(150); /* wait for warmup */
1349 I915_WRITE(reg, val);
1350 POSTING_READ(reg);
1351 udelay(150); /* wait for warmup */
1352 }
1353
1354 /**
1355 * intel_disable_pll - disable a PLL
1356 * @dev_priv: i915 private structure
1357 * @pipe: pipe PLL to disable
1358 *
1359 * Disable the PLL for @pipe, making sure the pipe is off first.
1360 *
1361 * Note! This is for pre-ILK only.
1362 */
1363 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1364 {
1365 int reg;
1366 u32 val;
1367
1368 /* Don't disable pipe A or pipe A PLLs if needed */
1369 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1370 return;
1371
1372 /* Make sure the pipe isn't still relying on us */
1373 assert_pipe_disabled(dev_priv, pipe);
1374
1375 reg = DPLL(pipe);
1376 val = I915_READ(reg);
1377 val &= ~DPLL_VCO_ENABLE;
1378 I915_WRITE(reg, val);
1379 POSTING_READ(reg);
1380 }
1381
1382 /**
1383 * intel_enable_pch_pll - enable PCH PLL
1384 * @dev_priv: i915 private structure
1385 * @pipe: pipe PLL to enable
1386 *
1387 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1388 * drives the transcoder clock.
1389 */
1390 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1391 enum pipe pipe)
1392 {
1393 int reg;
1394 u32 val;
1395
1396 /* PCH only available on ILK+ */
1397 BUG_ON(dev_priv->info->gen < 5);
1398
1399 /* PCH refclock must be enabled first */
1400 assert_pch_refclk_enabled(dev_priv);
1401
1402 reg = PCH_DPLL(pipe);
1403 val = I915_READ(reg);
1404 val |= DPLL_VCO_ENABLE;
1405 I915_WRITE(reg, val);
1406 POSTING_READ(reg);
1407 udelay(200);
1408 }
1409
1410 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1411 enum pipe pipe)
1412 {
1413 int reg;
1414 u32 val;
1415
1416 /* PCH only available on ILK+ */
1417 BUG_ON(dev_priv->info->gen < 5);
1418
1419 /* Make sure transcoder isn't still depending on us */
1420 assert_transcoder_disabled(dev_priv, pipe);
1421
1422 reg = PCH_DPLL(pipe);
1423 val = I915_READ(reg);
1424 val &= ~DPLL_VCO_ENABLE;
1425 I915_WRITE(reg, val);
1426 POSTING_READ(reg);
1427 udelay(200);
1428 }
1429
1430 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1431 enum pipe pipe)
1432 {
1433 int reg;
1434 u32 val;
1435
1436 /* PCH only available on ILK+ */
1437 BUG_ON(dev_priv->info->gen < 5);
1438
1439 /* Make sure PCH DPLL is enabled */
1440 assert_pch_pll_enabled(dev_priv, pipe);
1441
1442 /* FDI must be feeding us bits for PCH ports */
1443 assert_fdi_tx_enabled(dev_priv, pipe);
1444 assert_fdi_rx_enabled(dev_priv, pipe);
1445
1446 reg = TRANSCONF(pipe);
1447 val = I915_READ(reg);
1448 /*
1449 * make the BPC in transcoder be consistent with
1450 * that in pipeconf reg.
1451 */
1452 val &= ~PIPE_BPC_MASK;
1453 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1454 I915_WRITE(reg, val | TRANS_ENABLE);
1455 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1456 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1457 }
1458
1459 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1460 enum pipe pipe)
1461 {
1462 int reg;
1463 u32 val;
1464
1465 /* FDI relies on the transcoder */
1466 assert_fdi_tx_disabled(dev_priv, pipe);
1467 assert_fdi_rx_disabled(dev_priv, pipe);
1468
1469 /* Ports must be off as well */
1470 assert_pch_ports_disabled(dev_priv, pipe);
1471
1472 reg = TRANSCONF(pipe);
1473 val = I915_READ(reg);
1474 val &= ~TRANS_ENABLE;
1475 I915_WRITE(reg, val);
1476 /* wait for PCH transcoder off, transcoder state */
1477 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1478 DRM_ERROR("failed to disable transcoder\n");
1479 }
1480
1481 /**
1482 * intel_enable_pipe - enable a pipe, asserting requirements
1483 * @dev_priv: i915 private structure
1484 * @pipe: pipe to enable
1485 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1486 *
1487 * Enable @pipe, making sure that various hardware specific requirements
1488 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1489 *
1490 * @pipe should be %PIPE_A or %PIPE_B.
1491 *
1492 * Will wait until the pipe is actually running (i.e. first vblank) before
1493 * returning.
1494 */
1495 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1496 bool pch_port)
1497 {
1498 int reg;
1499 u32 val;
1500
1501 /*
1502 * A pipe without a PLL won't actually be able to drive bits from
1503 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1504 * need the check.
1505 */
1506 if (!HAS_PCH_SPLIT(dev_priv->dev))
1507 assert_pll_enabled(dev_priv, pipe);
1508 else {
1509 if (pch_port) {
1510 /* if driving the PCH, we need FDI enabled */
1511 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1512 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1513 }
1514 /* FIXME: assert CPU port conditions for SNB+ */
1515 }
1516
1517 reg = PIPECONF(pipe);
1518 val = I915_READ(reg);
1519 val |= PIPECONF_ENABLE;
1520 I915_WRITE(reg, val);
1521 POSTING_READ(reg);
1522 intel_wait_for_vblank(dev_priv->dev, pipe);
1523 }
1524
1525 /**
1526 * intel_disable_pipe - disable a pipe, asserting requirements
1527 * @dev_priv: i915 private structure
1528 * @pipe: pipe to disable
1529 *
1530 * Disable @pipe, making sure that various hardware specific requirements
1531 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1532 *
1533 * @pipe should be %PIPE_A or %PIPE_B.
1534 *
1535 * Will wait until the pipe has shut down before returning.
1536 */
1537 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1538 enum pipe pipe)
1539 {
1540 int reg;
1541 u32 val;
1542
1543 /*
1544 * Make sure planes won't keep trying to pump pixels to us,
1545 * or we might hang the display.
1546 */
1547 assert_planes_disabled(dev_priv, pipe);
1548
1549 /* Don't disable pipe A or pipe A PLLs if needed */
1550 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1551 return;
1552
1553 reg = PIPECONF(pipe);
1554 val = I915_READ(reg);
1555 val &= ~PIPECONF_ENABLE;
1556 I915_WRITE(reg, val);
1557 POSTING_READ(reg);
1558 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1559 }
1560
1561 /**
1562 * intel_enable_plane - enable a display plane on a given pipe
1563 * @dev_priv: i915 private structure
1564 * @plane: plane to enable
1565 * @pipe: pipe being fed
1566 *
1567 * Enable @plane on @pipe, making sure that @pipe is running first.
1568 */
1569 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1570 enum plane plane, enum pipe pipe)
1571 {
1572 int reg;
1573 u32 val;
1574
1575 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1576 assert_pipe_enabled(dev_priv, pipe);
1577
1578 reg = DSPCNTR(plane);
1579 val = I915_READ(reg);
1580 val |= DISPLAY_PLANE_ENABLE;
1581 I915_WRITE(reg, val);
1582 POSTING_READ(reg);
1583 intel_wait_for_vblank(dev_priv->dev, pipe);
1584 }
1585
1586 /*
1587 * Plane regs are double buffered, going from enabled->disabled needs a
1588 * trigger in order to latch. The display address reg provides this.
1589 */
1590 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1591 enum plane plane)
1592 {
1593 u32 reg = DSPADDR(plane);
1594 I915_WRITE(reg, I915_READ(reg));
1595 }
1596
1597 /**
1598 * intel_disable_plane - disable a display plane
1599 * @dev_priv: i915 private structure
1600 * @plane: plane to disable
1601 * @pipe: pipe consuming the data
1602 *
1603 * Disable @plane; should be an independent operation.
1604 */
1605 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1606 enum plane plane, enum pipe pipe)
1607 {
1608 int reg;
1609 u32 val;
1610
1611 reg = DSPCNTR(plane);
1612 val = I915_READ(reg);
1613 val &= ~DISPLAY_PLANE_ENABLE;
1614 I915_WRITE(reg, val);
1615 POSTING_READ(reg);
1616 intel_flush_display_plane(dev_priv, plane);
1617 intel_wait_for_vblank(dev_priv->dev, pipe);
1618 }
1619
1620 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1621 enum pipe pipe, int reg)
1622 {
1623 u32 val = I915_READ(reg);
1624 if (DP_PIPE_ENABLED(val, pipe))
1625 I915_WRITE(reg, val & ~DP_PORT_EN);
1626 }
1627
1628 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1629 enum pipe pipe, int reg)
1630 {
1631 u32 val = I915_READ(reg);
1632 if (HDMI_PIPE_ENABLED(val, pipe))
1633 I915_WRITE(reg, val & ~PORT_ENABLE);
1634 }
1635
1636 /* Disable any ports connected to this transcoder */
1637 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1638 enum pipe pipe)
1639 {
1640 u32 reg, val;
1641
1642 val = I915_READ(PCH_PP_CONTROL);
1643 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1644
1645 disable_pch_dp(dev_priv, pipe, PCH_DP_B);
1646 disable_pch_dp(dev_priv, pipe, PCH_DP_C);
1647 disable_pch_dp(dev_priv, pipe, PCH_DP_D);
1648
1649 reg = PCH_ADPA;
1650 val = I915_READ(reg);
1651 if (ADPA_PIPE_ENABLED(val, pipe))
1652 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1653
1654 reg = PCH_LVDS;
1655 val = I915_READ(reg);
1656 if (LVDS_PIPE_ENABLED(val, pipe)) {
1657 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1658 POSTING_READ(reg);
1659 udelay(100);
1660 }
1661
1662 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1663 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1664 disable_pch_hdmi(dev_priv, pipe, HDMID);
1665 }
1666
1667 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1668 {
1669 struct drm_device *dev = crtc->dev;
1670 struct drm_i915_private *dev_priv = dev->dev_private;
1671 struct drm_framebuffer *fb = crtc->fb;
1672 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1673 struct drm_i915_gem_object *obj = intel_fb->obj;
1674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1675 int plane, i;
1676 u32 fbc_ctl, fbc_ctl2;
1677
1678 if (fb->pitch == dev_priv->cfb_pitch &&
1679 obj->fence_reg == dev_priv->cfb_fence &&
1680 intel_crtc->plane == dev_priv->cfb_plane &&
1681 I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1682 return;
1683
1684 i8xx_disable_fbc(dev);
1685
1686 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1687
1688 if (fb->pitch < dev_priv->cfb_pitch)
1689 dev_priv->cfb_pitch = fb->pitch;
1690
1691 /* FBC_CTL wants 64B units */
1692 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1693 dev_priv->cfb_fence = obj->fence_reg;
1694 dev_priv->cfb_plane = intel_crtc->plane;
1695 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1696
1697 /* Clear old tags */
1698 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1699 I915_WRITE(FBC_TAG + (i * 4), 0);
1700
1701 /* Set it up... */
1702 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1703 if (obj->tiling_mode != I915_TILING_NONE)
1704 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1705 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1706 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1707
1708 /* enable it... */
1709 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1710 if (IS_I945GM(dev))
1711 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1712 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1713 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1714 if (obj->tiling_mode != I915_TILING_NONE)
1715 fbc_ctl |= dev_priv->cfb_fence;
1716 I915_WRITE(FBC_CONTROL, fbc_ctl);
1717
1718 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1719 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1720 }
1721
1722 void i8xx_disable_fbc(struct drm_device *dev)
1723 {
1724 struct drm_i915_private *dev_priv = dev->dev_private;
1725 u32 fbc_ctl;
1726
1727 /* Disable compression */
1728 fbc_ctl = I915_READ(FBC_CONTROL);
1729 if ((fbc_ctl & FBC_CTL_EN) == 0)
1730 return;
1731
1732 fbc_ctl &= ~FBC_CTL_EN;
1733 I915_WRITE(FBC_CONTROL, fbc_ctl);
1734
1735 /* Wait for compressing bit to clear */
1736 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1737 DRM_DEBUG_KMS("FBC idle timed out\n");
1738 return;
1739 }
1740
1741 DRM_DEBUG_KMS("disabled FBC\n");
1742 }
1743
1744 static bool i8xx_fbc_enabled(struct drm_device *dev)
1745 {
1746 struct drm_i915_private *dev_priv = dev->dev_private;
1747
1748 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1749 }
1750
1751 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1752 {
1753 struct drm_device *dev = crtc->dev;
1754 struct drm_i915_private *dev_priv = dev->dev_private;
1755 struct drm_framebuffer *fb = crtc->fb;
1756 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1757 struct drm_i915_gem_object *obj = intel_fb->obj;
1758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1759 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1760 unsigned long stall_watermark = 200;
1761 u32 dpfc_ctl;
1762
1763 dpfc_ctl = I915_READ(DPFC_CONTROL);
1764 if (dpfc_ctl & DPFC_CTL_EN) {
1765 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1766 dev_priv->cfb_fence == obj->fence_reg &&
1767 dev_priv->cfb_plane == intel_crtc->plane &&
1768 dev_priv->cfb_y == crtc->y)
1769 return;
1770
1771 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1772 POSTING_READ(DPFC_CONTROL);
1773 intel_wait_for_vblank(dev, intel_crtc->pipe);
1774 }
1775
1776 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1777 dev_priv->cfb_fence = obj->fence_reg;
1778 dev_priv->cfb_plane = intel_crtc->plane;
1779 dev_priv->cfb_y = crtc->y;
1780
1781 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1782 if (obj->tiling_mode != I915_TILING_NONE) {
1783 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1784 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1785 } else {
1786 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1787 }
1788
1789 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1790 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1791 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1792 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1793
1794 /* enable it... */
1795 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1796
1797 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1798 }
1799
1800 void g4x_disable_fbc(struct drm_device *dev)
1801 {
1802 struct drm_i915_private *dev_priv = dev->dev_private;
1803 u32 dpfc_ctl;
1804
1805 /* Disable compression */
1806 dpfc_ctl = I915_READ(DPFC_CONTROL);
1807 if (dpfc_ctl & DPFC_CTL_EN) {
1808 dpfc_ctl &= ~DPFC_CTL_EN;
1809 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1810
1811 DRM_DEBUG_KMS("disabled FBC\n");
1812 }
1813 }
1814
1815 static bool g4x_fbc_enabled(struct drm_device *dev)
1816 {
1817 struct drm_i915_private *dev_priv = dev->dev_private;
1818
1819 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1820 }
1821
1822 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1823 {
1824 struct drm_i915_private *dev_priv = dev->dev_private;
1825 u32 blt_ecoskpd;
1826
1827 /* Make sure blitter notifies FBC of writes */
1828 __gen6_gt_force_wake_get(dev_priv);
1829 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1830 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1831 GEN6_BLITTER_LOCK_SHIFT;
1832 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1833 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1834 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1835 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1836 GEN6_BLITTER_LOCK_SHIFT);
1837 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1838 POSTING_READ(GEN6_BLITTER_ECOSKPD);
1839 __gen6_gt_force_wake_put(dev_priv);
1840 }
1841
1842 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1843 {
1844 struct drm_device *dev = crtc->dev;
1845 struct drm_i915_private *dev_priv = dev->dev_private;
1846 struct drm_framebuffer *fb = crtc->fb;
1847 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1848 struct drm_i915_gem_object *obj = intel_fb->obj;
1849 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1850 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1851 unsigned long stall_watermark = 200;
1852 u32 dpfc_ctl;
1853
1854 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1855 if (dpfc_ctl & DPFC_CTL_EN) {
1856 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1857 dev_priv->cfb_fence == obj->fence_reg &&
1858 dev_priv->cfb_plane == intel_crtc->plane &&
1859 dev_priv->cfb_offset == obj->gtt_offset &&
1860 dev_priv->cfb_y == crtc->y)
1861 return;
1862
1863 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1864 POSTING_READ(ILK_DPFC_CONTROL);
1865 intel_wait_for_vblank(dev, intel_crtc->pipe);
1866 }
1867
1868 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1869 dev_priv->cfb_fence = obj->fence_reg;
1870 dev_priv->cfb_plane = intel_crtc->plane;
1871 dev_priv->cfb_offset = obj->gtt_offset;
1872 dev_priv->cfb_y = crtc->y;
1873
1874 dpfc_ctl &= DPFC_RESERVED;
1875 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1876 if (obj->tiling_mode != I915_TILING_NONE) {
1877 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1878 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1879 } else {
1880 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1881 }
1882
1883 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1884 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1885 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1886 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1887 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1888 /* enable it... */
1889 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1890
1891 if (IS_GEN6(dev)) {
1892 I915_WRITE(SNB_DPFC_CTL_SA,
1893 SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1894 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1895 sandybridge_blit_fbc_update(dev);
1896 }
1897
1898 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1899 }
1900
1901 void ironlake_disable_fbc(struct drm_device *dev)
1902 {
1903 struct drm_i915_private *dev_priv = dev->dev_private;
1904 u32 dpfc_ctl;
1905
1906 /* Disable compression */
1907 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1908 if (dpfc_ctl & DPFC_CTL_EN) {
1909 dpfc_ctl &= ~DPFC_CTL_EN;
1910 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1911
1912 DRM_DEBUG_KMS("disabled FBC\n");
1913 }
1914 }
1915
1916 static bool ironlake_fbc_enabled(struct drm_device *dev)
1917 {
1918 struct drm_i915_private *dev_priv = dev->dev_private;
1919
1920 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1921 }
1922
1923 bool intel_fbc_enabled(struct drm_device *dev)
1924 {
1925 struct drm_i915_private *dev_priv = dev->dev_private;
1926
1927 if (!dev_priv->display.fbc_enabled)
1928 return false;
1929
1930 return dev_priv->display.fbc_enabled(dev);
1931 }
1932
1933 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1934 {
1935 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1936
1937 if (!dev_priv->display.enable_fbc)
1938 return;
1939
1940 dev_priv->display.enable_fbc(crtc, interval);
1941 }
1942
1943 void intel_disable_fbc(struct drm_device *dev)
1944 {
1945 struct drm_i915_private *dev_priv = dev->dev_private;
1946
1947 if (!dev_priv->display.disable_fbc)
1948 return;
1949
1950 dev_priv->display.disable_fbc(dev);
1951 }
1952
1953 /**
1954 * intel_update_fbc - enable/disable FBC as needed
1955 * @dev: the drm_device
1956 *
1957 * Set up the framebuffer compression hardware at mode set time. We
1958 * enable it if possible:
1959 * - plane A only (on pre-965)
1960 * - no pixel mulitply/line duplication
1961 * - no alpha buffer discard
1962 * - no dual wide
1963 * - framebuffer <= 2048 in width, 1536 in height
1964 *
1965 * We can't assume that any compression will take place (worst case),
1966 * so the compressed buffer has to be the same size as the uncompressed
1967 * one. It also must reside (along with the line length buffer) in
1968 * stolen memory.
1969 *
1970 * We need to enable/disable FBC on a global basis.
1971 */
1972 static void intel_update_fbc(struct drm_device *dev)
1973 {
1974 struct drm_i915_private *dev_priv = dev->dev_private;
1975 struct drm_crtc *crtc = NULL, *tmp_crtc;
1976 struct intel_crtc *intel_crtc;
1977 struct drm_framebuffer *fb;
1978 struct intel_framebuffer *intel_fb;
1979 struct drm_i915_gem_object *obj;
1980
1981 DRM_DEBUG_KMS("\n");
1982
1983 if (!i915_powersave)
1984 return;
1985
1986 if (!I915_HAS_FBC(dev))
1987 return;
1988
1989 /*
1990 * If FBC is already on, we just have to verify that we can
1991 * keep it that way...
1992 * Need to disable if:
1993 * - more than one pipe is active
1994 * - changing FBC params (stride, fence, mode)
1995 * - new fb is too large to fit in compressed buffer
1996 * - going to an unsupported config (interlace, pixel multiply, etc.)
1997 */
1998 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1999 if (tmp_crtc->enabled && tmp_crtc->fb) {
2000 if (crtc) {
2001 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
2002 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
2003 goto out_disable;
2004 }
2005 crtc = tmp_crtc;
2006 }
2007 }
2008
2009 if (!crtc || crtc->fb == NULL) {
2010 DRM_DEBUG_KMS("no output, disabling\n");
2011 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
2012 goto out_disable;
2013 }
2014
2015 intel_crtc = to_intel_crtc(crtc);
2016 fb = crtc->fb;
2017 intel_fb = to_intel_framebuffer(fb);
2018 obj = intel_fb->obj;
2019
2020 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
2021 DRM_DEBUG_KMS("framebuffer too large, disabling "
2022 "compression\n");
2023 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
2024 goto out_disable;
2025 }
2026 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
2027 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
2028 DRM_DEBUG_KMS("mode incompatible with compression, "
2029 "disabling\n");
2030 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
2031 goto out_disable;
2032 }
2033 if ((crtc->mode.hdisplay > 2048) ||
2034 (crtc->mode.vdisplay > 1536)) {
2035 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
2036 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
2037 goto out_disable;
2038 }
2039 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
2040 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
2041 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
2042 goto out_disable;
2043 }
2044 if (obj->tiling_mode != I915_TILING_X) {
2045 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
2046 dev_priv->no_fbc_reason = FBC_NOT_TILED;
2047 goto out_disable;
2048 }
2049
2050 /* If the kernel debugger is active, always disable compression */
2051 if (in_dbg_master())
2052 goto out_disable;
2053
2054 intel_enable_fbc(crtc, 500);
2055 return;
2056
2057 out_disable:
2058 /* Multiple disables should be harmless */
2059 if (intel_fbc_enabled(dev)) {
2060 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
2061 intel_disable_fbc(dev);
2062 }
2063 }
2064
2065 int
2066 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2067 struct drm_i915_gem_object *obj,
2068 struct intel_ring_buffer *pipelined)
2069 {
2070 struct drm_i915_private *dev_priv = dev->dev_private;
2071 u32 alignment;
2072 int ret;
2073
2074 switch (obj->tiling_mode) {
2075 case I915_TILING_NONE:
2076 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2077 alignment = 128 * 1024;
2078 else if (INTEL_INFO(dev)->gen >= 4)
2079 alignment = 4 * 1024;
2080 else
2081 alignment = 64 * 1024;
2082 break;
2083 case I915_TILING_X:
2084 /* pin() will align the object as required by fence */
2085 alignment = 0;
2086 break;
2087 case I915_TILING_Y:
2088 /* FIXME: Is this true? */
2089 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2090 return -EINVAL;
2091 default:
2092 BUG();
2093 }
2094
2095 dev_priv->mm.interruptible = false;
2096 ret = i915_gem_object_pin(obj, alignment, true);
2097 if (ret)
2098 goto err_interruptible;
2099
2100 ret = i915_gem_object_set_to_display_plane(obj, pipelined);
2101 if (ret)
2102 goto err_unpin;
2103
2104 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2105 * fence, whereas 965+ only requires a fence if using
2106 * framebuffer compression. For simplicity, we always install
2107 * a fence as the cost is not that onerous.
2108 */
2109 if (obj->tiling_mode != I915_TILING_NONE) {
2110 ret = i915_gem_object_get_fence(obj, pipelined);
2111 if (ret)
2112 goto err_unpin;
2113 }
2114
2115 dev_priv->mm.interruptible = true;
2116 return 0;
2117
2118 err_unpin:
2119 i915_gem_object_unpin(obj);
2120 err_interruptible:
2121 dev_priv->mm.interruptible = true;
2122 return ret;
2123 }
2124
2125 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2126 static int
2127 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2128 int x, int y, enum mode_set_atomic state)
2129 {
2130 struct drm_device *dev = crtc->dev;
2131 struct drm_i915_private *dev_priv = dev->dev_private;
2132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133 struct intel_framebuffer *intel_fb;
2134 struct drm_i915_gem_object *obj;
2135 int plane = intel_crtc->plane;
2136 unsigned long Start, Offset;
2137 u32 dspcntr;
2138 u32 reg;
2139
2140 switch (plane) {
2141 case 0:
2142 case 1:
2143 break;
2144 default:
2145 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2146 return -EINVAL;
2147 }
2148
2149 intel_fb = to_intel_framebuffer(fb);
2150 obj = intel_fb->obj;
2151
2152 reg = DSPCNTR(plane);
2153 dspcntr = I915_READ(reg);
2154 /* Mask out pixel format bits in case we change it */
2155 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2156 switch (fb->bits_per_pixel) {
2157 case 8:
2158 dspcntr |= DISPPLANE_8BPP;
2159 break;
2160 case 16:
2161 if (fb->depth == 15)
2162 dspcntr |= DISPPLANE_15_16BPP;
2163 else
2164 dspcntr |= DISPPLANE_16BPP;
2165 break;
2166 case 24:
2167 case 32:
2168 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2169 break;
2170 default:
2171 DRM_ERROR("Unknown color depth\n");
2172 return -EINVAL;
2173 }
2174 if (INTEL_INFO(dev)->gen >= 4) {
2175 if (obj->tiling_mode != I915_TILING_NONE)
2176 dspcntr |= DISPPLANE_TILED;
2177 else
2178 dspcntr &= ~DISPPLANE_TILED;
2179 }
2180
2181 if (HAS_PCH_SPLIT(dev))
2182 /* must disable */
2183 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2184
2185 I915_WRITE(reg, dspcntr);
2186
2187 Start = obj->gtt_offset;
2188 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2189
2190 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2191 Start, Offset, x, y, fb->pitch);
2192 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2193 if (INTEL_INFO(dev)->gen >= 4) {
2194 I915_WRITE(DSPSURF(plane), Start);
2195 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2196 I915_WRITE(DSPADDR(plane), Offset);
2197 } else
2198 I915_WRITE(DSPADDR(plane), Start + Offset);
2199 POSTING_READ(reg);
2200
2201 intel_update_fbc(dev);
2202 intel_increase_pllclock(crtc);
2203
2204 return 0;
2205 }
2206
2207 static int
2208 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2209 struct drm_framebuffer *old_fb)
2210 {
2211 struct drm_device *dev = crtc->dev;
2212 struct drm_i915_master_private *master_priv;
2213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2214 int ret;
2215
2216 /* no fb bound */
2217 if (!crtc->fb) {
2218 DRM_DEBUG_KMS("No FB bound\n");
2219 return 0;
2220 }
2221
2222 switch (intel_crtc->plane) {
2223 case 0:
2224 case 1:
2225 break;
2226 default:
2227 return -EINVAL;
2228 }
2229
2230 mutex_lock(&dev->struct_mutex);
2231 ret = intel_pin_and_fence_fb_obj(dev,
2232 to_intel_framebuffer(crtc->fb)->obj,
2233 NULL);
2234 if (ret != 0) {
2235 mutex_unlock(&dev->struct_mutex);
2236 return ret;
2237 }
2238
2239 if (old_fb) {
2240 struct drm_i915_private *dev_priv = dev->dev_private;
2241 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2242
2243 wait_event(dev_priv->pending_flip_queue,
2244 atomic_read(&dev_priv->mm.wedged) ||
2245 atomic_read(&obj->pending_flip) == 0);
2246
2247 /* Big Hammer, we also need to ensure that any pending
2248 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2249 * current scanout is retired before unpinning the old
2250 * framebuffer.
2251 *
2252 * This should only fail upon a hung GPU, in which case we
2253 * can safely continue.
2254 */
2255 ret = i915_gem_object_flush_gpu(obj);
2256 (void) ret;
2257 }
2258
2259 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2260 LEAVE_ATOMIC_MODE_SET);
2261 if (ret) {
2262 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2263 mutex_unlock(&dev->struct_mutex);
2264 return ret;
2265 }
2266
2267 if (old_fb) {
2268 intel_wait_for_vblank(dev, intel_crtc->pipe);
2269 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2270 }
2271
2272 mutex_unlock(&dev->struct_mutex);
2273
2274 if (!dev->primary->master)
2275 return 0;
2276
2277 master_priv = dev->primary->master->driver_priv;
2278 if (!master_priv->sarea_priv)
2279 return 0;
2280
2281 if (intel_crtc->pipe) {
2282 master_priv->sarea_priv->pipeB_x = x;
2283 master_priv->sarea_priv->pipeB_y = y;
2284 } else {
2285 master_priv->sarea_priv->pipeA_x = x;
2286 master_priv->sarea_priv->pipeA_y = y;
2287 }
2288
2289 return 0;
2290 }
2291
2292 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2293 {
2294 struct drm_device *dev = crtc->dev;
2295 struct drm_i915_private *dev_priv = dev->dev_private;
2296 u32 dpa_ctl;
2297
2298 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2299 dpa_ctl = I915_READ(DP_A);
2300 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2301
2302 if (clock < 200000) {
2303 u32 temp;
2304 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2305 /* workaround for 160Mhz:
2306 1) program 0x4600c bits 15:0 = 0x8124
2307 2) program 0x46010 bit 0 = 1
2308 3) program 0x46034 bit 24 = 1
2309 4) program 0x64000 bit 14 = 1
2310 */
2311 temp = I915_READ(0x4600c);
2312 temp &= 0xffff0000;
2313 I915_WRITE(0x4600c, temp | 0x8124);
2314
2315 temp = I915_READ(0x46010);
2316 I915_WRITE(0x46010, temp | 1);
2317
2318 temp = I915_READ(0x46034);
2319 I915_WRITE(0x46034, temp | (1 << 24));
2320 } else {
2321 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2322 }
2323 I915_WRITE(DP_A, dpa_ctl);
2324
2325 POSTING_READ(DP_A);
2326 udelay(500);
2327 }
2328
2329 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2330 {
2331 struct drm_device *dev = crtc->dev;
2332 struct drm_i915_private *dev_priv = dev->dev_private;
2333 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2334 int pipe = intel_crtc->pipe;
2335 u32 reg, temp;
2336
2337 /* enable normal train */
2338 reg = FDI_TX_CTL(pipe);
2339 temp = I915_READ(reg);
2340 temp &= ~FDI_LINK_TRAIN_NONE;
2341 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2342 I915_WRITE(reg, temp);
2343
2344 reg = FDI_RX_CTL(pipe);
2345 temp = I915_READ(reg);
2346 if (HAS_PCH_CPT(dev)) {
2347 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2348 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2349 } else {
2350 temp &= ~FDI_LINK_TRAIN_NONE;
2351 temp |= FDI_LINK_TRAIN_NONE;
2352 }
2353 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2354
2355 /* wait one idle pattern time */
2356 POSTING_READ(reg);
2357 udelay(1000);
2358 }
2359
2360 /* The FDI link training functions for ILK/Ibexpeak. */
2361 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2362 {
2363 struct drm_device *dev = crtc->dev;
2364 struct drm_i915_private *dev_priv = dev->dev_private;
2365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2366 int pipe = intel_crtc->pipe;
2367 int plane = intel_crtc->plane;
2368 u32 reg, temp, tries;
2369
2370 /* FDI needs bits from pipe & plane first */
2371 assert_pipe_enabled(dev_priv, pipe);
2372 assert_plane_enabled(dev_priv, plane);
2373
2374 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2375 for train result */
2376 reg = FDI_RX_IMR(pipe);
2377 temp = I915_READ(reg);
2378 temp &= ~FDI_RX_SYMBOL_LOCK;
2379 temp &= ~FDI_RX_BIT_LOCK;
2380 I915_WRITE(reg, temp);
2381 I915_READ(reg);
2382 udelay(150);
2383
2384 /* enable CPU FDI TX and PCH FDI RX */
2385 reg = FDI_TX_CTL(pipe);
2386 temp = I915_READ(reg);
2387 temp &= ~(7 << 19);
2388 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2389 temp &= ~FDI_LINK_TRAIN_NONE;
2390 temp |= FDI_LINK_TRAIN_PATTERN_1;
2391 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2392
2393 reg = FDI_RX_CTL(pipe);
2394 temp = I915_READ(reg);
2395 temp &= ~FDI_LINK_TRAIN_NONE;
2396 temp |= FDI_LINK_TRAIN_PATTERN_1;
2397 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2398
2399 POSTING_READ(reg);
2400 udelay(150);
2401
2402 /* Ironlake workaround, enable clock pointer after FDI enable*/
2403 if (HAS_PCH_IBX(dev)) {
2404 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2405 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2406 FDI_RX_PHASE_SYNC_POINTER_EN);
2407 }
2408
2409 reg = FDI_RX_IIR(pipe);
2410 for (tries = 0; tries < 5; tries++) {
2411 temp = I915_READ(reg);
2412 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2413
2414 if ((temp & FDI_RX_BIT_LOCK)) {
2415 DRM_DEBUG_KMS("FDI train 1 done.\n");
2416 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2417 break;
2418 }
2419 }
2420 if (tries == 5)
2421 DRM_ERROR("FDI train 1 fail!\n");
2422
2423 /* Train 2 */
2424 reg = FDI_TX_CTL(pipe);
2425 temp = I915_READ(reg);
2426 temp &= ~FDI_LINK_TRAIN_NONE;
2427 temp |= FDI_LINK_TRAIN_PATTERN_2;
2428 I915_WRITE(reg, temp);
2429
2430 reg = FDI_RX_CTL(pipe);
2431 temp = I915_READ(reg);
2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_2;
2434 I915_WRITE(reg, temp);
2435
2436 POSTING_READ(reg);
2437 udelay(150);
2438
2439 reg = FDI_RX_IIR(pipe);
2440 for (tries = 0; tries < 5; tries++) {
2441 temp = I915_READ(reg);
2442 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2443
2444 if (temp & FDI_RX_SYMBOL_LOCK) {
2445 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2446 DRM_DEBUG_KMS("FDI train 2 done.\n");
2447 break;
2448 }
2449 }
2450 if (tries == 5)
2451 DRM_ERROR("FDI train 2 fail!\n");
2452
2453 DRM_DEBUG_KMS("FDI train done\n");
2454
2455 }
2456
2457 static const int snb_b_fdi_train_param [] = {
2458 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2459 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2460 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2461 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2462 };
2463
2464 /* The FDI link training functions for SNB/Cougarpoint. */
2465 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2466 {
2467 struct drm_device *dev = crtc->dev;
2468 struct drm_i915_private *dev_priv = dev->dev_private;
2469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2470 int pipe = intel_crtc->pipe;
2471 u32 reg, temp, i;
2472
2473 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2474 for train result */
2475 reg = FDI_RX_IMR(pipe);
2476 temp = I915_READ(reg);
2477 temp &= ~FDI_RX_SYMBOL_LOCK;
2478 temp &= ~FDI_RX_BIT_LOCK;
2479 I915_WRITE(reg, temp);
2480
2481 POSTING_READ(reg);
2482 udelay(150);
2483
2484 /* enable CPU FDI TX and PCH FDI RX */
2485 reg = FDI_TX_CTL(pipe);
2486 temp = I915_READ(reg);
2487 temp &= ~(7 << 19);
2488 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2489 temp &= ~FDI_LINK_TRAIN_NONE;
2490 temp |= FDI_LINK_TRAIN_PATTERN_1;
2491 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2492 /* SNB-B */
2493 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2494 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2495
2496 reg = FDI_RX_CTL(pipe);
2497 temp = I915_READ(reg);
2498 if (HAS_PCH_CPT(dev)) {
2499 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2500 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2501 } else {
2502 temp &= ~FDI_LINK_TRAIN_NONE;
2503 temp |= FDI_LINK_TRAIN_PATTERN_1;
2504 }
2505 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2506
2507 POSTING_READ(reg);
2508 udelay(150);
2509
2510 for (i = 0; i < 4; i++ ) {
2511 reg = FDI_TX_CTL(pipe);
2512 temp = I915_READ(reg);
2513 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2514 temp |= snb_b_fdi_train_param[i];
2515 I915_WRITE(reg, temp);
2516
2517 POSTING_READ(reg);
2518 udelay(500);
2519
2520 reg = FDI_RX_IIR(pipe);
2521 temp = I915_READ(reg);
2522 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2523
2524 if (temp & FDI_RX_BIT_LOCK) {
2525 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2526 DRM_DEBUG_KMS("FDI train 1 done.\n");
2527 break;
2528 }
2529 }
2530 if (i == 4)
2531 DRM_ERROR("FDI train 1 fail!\n");
2532
2533 /* Train 2 */
2534 reg = FDI_TX_CTL(pipe);
2535 temp = I915_READ(reg);
2536 temp &= ~FDI_LINK_TRAIN_NONE;
2537 temp |= FDI_LINK_TRAIN_PATTERN_2;
2538 if (IS_GEN6(dev)) {
2539 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2540 /* SNB-B */
2541 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2542 }
2543 I915_WRITE(reg, temp);
2544
2545 reg = FDI_RX_CTL(pipe);
2546 temp = I915_READ(reg);
2547 if (HAS_PCH_CPT(dev)) {
2548 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2549 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2550 } else {
2551 temp &= ~FDI_LINK_TRAIN_NONE;
2552 temp |= FDI_LINK_TRAIN_PATTERN_2;
2553 }
2554 I915_WRITE(reg, temp);
2555
2556 POSTING_READ(reg);
2557 udelay(150);
2558
2559 for (i = 0; i < 4; i++ ) {
2560 reg = FDI_TX_CTL(pipe);
2561 temp = I915_READ(reg);
2562 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2563 temp |= snb_b_fdi_train_param[i];
2564 I915_WRITE(reg, temp);
2565
2566 POSTING_READ(reg);
2567 udelay(500);
2568
2569 reg = FDI_RX_IIR(pipe);
2570 temp = I915_READ(reg);
2571 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2572
2573 if (temp & FDI_RX_SYMBOL_LOCK) {
2574 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2575 DRM_DEBUG_KMS("FDI train 2 done.\n");
2576 break;
2577 }
2578 }
2579 if (i == 4)
2580 DRM_ERROR("FDI train 2 fail!\n");
2581
2582 DRM_DEBUG_KMS("FDI train done.\n");
2583 }
2584
2585 static void ironlake_fdi_enable(struct drm_crtc *crtc)
2586 {
2587 struct drm_device *dev = crtc->dev;
2588 struct drm_i915_private *dev_priv = dev->dev_private;
2589 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2590 int pipe = intel_crtc->pipe;
2591 u32 reg, temp;
2592
2593 /* Write the TU size bits so error detection works */
2594 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2595 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2596
2597 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2598 reg = FDI_RX_CTL(pipe);
2599 temp = I915_READ(reg);
2600 temp &= ~((0x7 << 19) | (0x7 << 16));
2601 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2602 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2603 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2604
2605 POSTING_READ(reg);
2606 udelay(200);
2607
2608 /* Switch from Rawclk to PCDclk */
2609 temp = I915_READ(reg);
2610 I915_WRITE(reg, temp | FDI_PCDCLK);
2611
2612 POSTING_READ(reg);
2613 udelay(200);
2614
2615 /* Enable CPU FDI TX PLL, always on for Ironlake */
2616 reg = FDI_TX_CTL(pipe);
2617 temp = I915_READ(reg);
2618 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2619 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2620
2621 POSTING_READ(reg);
2622 udelay(100);
2623 }
2624 }
2625
2626 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2627 {
2628 struct drm_device *dev = crtc->dev;
2629 struct drm_i915_private *dev_priv = dev->dev_private;
2630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2631 int pipe = intel_crtc->pipe;
2632 u32 reg, temp;
2633
2634 /* disable CPU FDI tx and PCH FDI rx */
2635 reg = FDI_TX_CTL(pipe);
2636 temp = I915_READ(reg);
2637 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2638 POSTING_READ(reg);
2639
2640 reg = FDI_RX_CTL(pipe);
2641 temp = I915_READ(reg);
2642 temp &= ~(0x7 << 16);
2643 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2644 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2645
2646 POSTING_READ(reg);
2647 udelay(100);
2648
2649 /* Ironlake workaround, disable clock pointer after downing FDI */
2650 if (HAS_PCH_IBX(dev)) {
2651 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2652 I915_WRITE(FDI_RX_CHICKEN(pipe),
2653 I915_READ(FDI_RX_CHICKEN(pipe) &
2654 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2655 }
2656
2657 /* still set train pattern 1 */
2658 reg = FDI_TX_CTL(pipe);
2659 temp = I915_READ(reg);
2660 temp &= ~FDI_LINK_TRAIN_NONE;
2661 temp |= FDI_LINK_TRAIN_PATTERN_1;
2662 I915_WRITE(reg, temp);
2663
2664 reg = FDI_RX_CTL(pipe);
2665 temp = I915_READ(reg);
2666 if (HAS_PCH_CPT(dev)) {
2667 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2668 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2669 } else {
2670 temp &= ~FDI_LINK_TRAIN_NONE;
2671 temp |= FDI_LINK_TRAIN_PATTERN_1;
2672 }
2673 /* BPC in FDI rx is consistent with that in PIPECONF */
2674 temp &= ~(0x07 << 16);
2675 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2676 I915_WRITE(reg, temp);
2677
2678 POSTING_READ(reg);
2679 udelay(100);
2680 }
2681
2682 /*
2683 * When we disable a pipe, we need to clear any pending scanline wait events
2684 * to avoid hanging the ring, which we assume we are waiting on.
2685 */
2686 static void intel_clear_scanline_wait(struct drm_device *dev)
2687 {
2688 struct drm_i915_private *dev_priv = dev->dev_private;
2689 struct intel_ring_buffer *ring;
2690 u32 tmp;
2691
2692 if (IS_GEN2(dev))
2693 /* Can't break the hang on i8xx */
2694 return;
2695
2696 ring = LP_RING(dev_priv);
2697 tmp = I915_READ_CTL(ring);
2698 if (tmp & RING_WAIT)
2699 I915_WRITE_CTL(ring, tmp);
2700 }
2701
2702 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2703 {
2704 struct drm_i915_gem_object *obj;
2705 struct drm_i915_private *dev_priv;
2706
2707 if (crtc->fb == NULL)
2708 return;
2709
2710 obj = to_intel_framebuffer(crtc->fb)->obj;
2711 dev_priv = crtc->dev->dev_private;
2712 wait_event(dev_priv->pending_flip_queue,
2713 atomic_read(&obj->pending_flip) == 0);
2714 }
2715
2716 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2717 {
2718 struct drm_device *dev = crtc->dev;
2719 struct drm_mode_config *mode_config = &dev->mode_config;
2720 struct intel_encoder *encoder;
2721
2722 /*
2723 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2724 * must be driven by its own crtc; no sharing is possible.
2725 */
2726 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2727 if (encoder->base.crtc != crtc)
2728 continue;
2729
2730 switch (encoder->type) {
2731 case INTEL_OUTPUT_EDP:
2732 if (!intel_encoder_is_pch_edp(&encoder->base))
2733 return false;
2734 continue;
2735 }
2736 }
2737
2738 return true;
2739 }
2740
2741 /*
2742 * Enable PCH resources required for PCH ports:
2743 * - PCH PLLs
2744 * - FDI training & RX/TX
2745 * - update transcoder timings
2746 * - DP transcoding bits
2747 * - transcoder
2748 */
2749 static void ironlake_pch_enable(struct drm_crtc *crtc)
2750 {
2751 struct drm_device *dev = crtc->dev;
2752 struct drm_i915_private *dev_priv = dev->dev_private;
2753 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2754 int pipe = intel_crtc->pipe;
2755 u32 reg, temp;
2756
2757 /* For PCH output, training FDI link */
2758 if (IS_GEN6(dev))
2759 gen6_fdi_link_train(crtc);
2760 else
2761 ironlake_fdi_link_train(crtc);
2762
2763 intel_enable_pch_pll(dev_priv, pipe);
2764
2765 if (HAS_PCH_CPT(dev)) {
2766 /* Be sure PCH DPLL SEL is set */
2767 temp = I915_READ(PCH_DPLL_SEL);
2768 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2769 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2770 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2771 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2772 I915_WRITE(PCH_DPLL_SEL, temp);
2773 }
2774
2775 /* set transcoder timing, panel must allow it */
2776 assert_panel_unlocked(dev_priv, pipe);
2777 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2778 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2779 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2780
2781 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2782 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2783 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2784
2785 intel_fdi_normal_train(crtc);
2786
2787 /* For PCH DP, enable TRANS_DP_CTL */
2788 if (HAS_PCH_CPT(dev) &&
2789 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2790 reg = TRANS_DP_CTL(pipe);
2791 temp = I915_READ(reg);
2792 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2793 TRANS_DP_SYNC_MASK |
2794 TRANS_DP_BPC_MASK);
2795 temp |= (TRANS_DP_OUTPUT_ENABLE |
2796 TRANS_DP_ENH_FRAMING);
2797 temp |= TRANS_DP_8BPC;
2798
2799 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2800 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2801 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2802 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2803
2804 switch (intel_trans_dp_port_sel(crtc)) {
2805 case PCH_DP_B:
2806 temp |= TRANS_DP_PORT_SEL_B;
2807 break;
2808 case PCH_DP_C:
2809 temp |= TRANS_DP_PORT_SEL_C;
2810 break;
2811 case PCH_DP_D:
2812 temp |= TRANS_DP_PORT_SEL_D;
2813 break;
2814 default:
2815 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2816 temp |= TRANS_DP_PORT_SEL_B;
2817 break;
2818 }
2819
2820 I915_WRITE(reg, temp);
2821 }
2822
2823 intel_enable_transcoder(dev_priv, pipe);
2824 }
2825
2826 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2827 {
2828 struct drm_device *dev = crtc->dev;
2829 struct drm_i915_private *dev_priv = dev->dev_private;
2830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2831 int pipe = intel_crtc->pipe;
2832 int plane = intel_crtc->plane;
2833 u32 temp;
2834 bool is_pch_port;
2835
2836 if (intel_crtc->active)
2837 return;
2838
2839 intel_crtc->active = true;
2840 intel_update_watermarks(dev);
2841
2842 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2843 temp = I915_READ(PCH_LVDS);
2844 if ((temp & LVDS_PORT_EN) == 0)
2845 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2846 }
2847
2848 is_pch_port = intel_crtc_driving_pch(crtc);
2849
2850 if (is_pch_port)
2851 ironlake_fdi_enable(crtc);
2852 else
2853 ironlake_fdi_disable(crtc);
2854
2855 /* Enable panel fitting for LVDS */
2856 if (dev_priv->pch_pf_size &&
2857 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2858 /* Force use of hard-coded filter coefficients
2859 * as some pre-programmed values are broken,
2860 * e.g. x201.
2861 */
2862 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2863 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2864 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2865 }
2866
2867 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2868 intel_enable_plane(dev_priv, plane, pipe);
2869
2870 if (is_pch_port)
2871 ironlake_pch_enable(crtc);
2872
2873 intel_crtc_load_lut(crtc);
2874 intel_update_fbc(dev);
2875 intel_crtc_update_cursor(crtc, true);
2876 }
2877
2878 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2879 {
2880 struct drm_device *dev = crtc->dev;
2881 struct drm_i915_private *dev_priv = dev->dev_private;
2882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2883 int pipe = intel_crtc->pipe;
2884 int plane = intel_crtc->plane;
2885 u32 reg, temp;
2886
2887 if (!intel_crtc->active)
2888 return;
2889
2890 intel_crtc_wait_for_pending_flips(crtc);
2891 drm_vblank_off(dev, pipe);
2892 intel_crtc_update_cursor(crtc, false);
2893
2894 intel_disable_plane(dev_priv, plane, pipe);
2895
2896 if (dev_priv->cfb_plane == plane &&
2897 dev_priv->display.disable_fbc)
2898 dev_priv->display.disable_fbc(dev);
2899
2900 intel_disable_pipe(dev_priv, pipe);
2901
2902 /* Disable PF */
2903 I915_WRITE(PF_CTL(pipe), 0);
2904 I915_WRITE(PF_WIN_SZ(pipe), 0);
2905
2906 ironlake_fdi_disable(crtc);
2907
2908 /* This is a horrible layering violation; we should be doing this in
2909 * the connector/encoder ->prepare instead, but we don't always have
2910 * enough information there about the config to know whether it will
2911 * actually be necessary or just cause undesired flicker.
2912 */
2913 intel_disable_pch_ports(dev_priv, pipe);
2914
2915 intel_disable_transcoder(dev_priv, pipe);
2916
2917 if (HAS_PCH_CPT(dev)) {
2918 /* disable TRANS_DP_CTL */
2919 reg = TRANS_DP_CTL(pipe);
2920 temp = I915_READ(reg);
2921 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2922 temp |= TRANS_DP_PORT_SEL_NONE;
2923 I915_WRITE(reg, temp);
2924
2925 /* disable DPLL_SEL */
2926 temp = I915_READ(PCH_DPLL_SEL);
2927 switch (pipe) {
2928 case 0:
2929 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2930 break;
2931 case 1:
2932 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2933 break;
2934 case 2:
2935 /* FIXME: manage transcoder PLLs? */
2936 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2937 break;
2938 default:
2939 BUG(); /* wtf */
2940 }
2941 I915_WRITE(PCH_DPLL_SEL, temp);
2942 }
2943
2944 /* disable PCH DPLL */
2945 intel_disable_pch_pll(dev_priv, pipe);
2946
2947 /* Switch from PCDclk to Rawclk */
2948 reg = FDI_RX_CTL(pipe);
2949 temp = I915_READ(reg);
2950 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2951
2952 /* Disable CPU FDI TX PLL */
2953 reg = FDI_TX_CTL(pipe);
2954 temp = I915_READ(reg);
2955 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2956
2957 POSTING_READ(reg);
2958 udelay(100);
2959
2960 reg = FDI_RX_CTL(pipe);
2961 temp = I915_READ(reg);
2962 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2963
2964 /* Wait for the clocks to turn off. */
2965 POSTING_READ(reg);
2966 udelay(100);
2967
2968 intel_crtc->active = false;
2969 intel_update_watermarks(dev);
2970 intel_update_fbc(dev);
2971 intel_clear_scanline_wait(dev);
2972 }
2973
2974 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2975 {
2976 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2977 int pipe = intel_crtc->pipe;
2978 int plane = intel_crtc->plane;
2979
2980 /* XXX: When our outputs are all unaware of DPMS modes other than off
2981 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2982 */
2983 switch (mode) {
2984 case DRM_MODE_DPMS_ON:
2985 case DRM_MODE_DPMS_STANDBY:
2986 case DRM_MODE_DPMS_SUSPEND:
2987 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2988 ironlake_crtc_enable(crtc);
2989 break;
2990
2991 case DRM_MODE_DPMS_OFF:
2992 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2993 ironlake_crtc_disable(crtc);
2994 break;
2995 }
2996 }
2997
2998 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2999 {
3000 if (!enable && intel_crtc->overlay) {
3001 struct drm_device *dev = intel_crtc->base.dev;
3002 struct drm_i915_private *dev_priv = dev->dev_private;
3003
3004 mutex_lock(&dev->struct_mutex);
3005 dev_priv->mm.interruptible = false;
3006 (void) intel_overlay_switch_off(intel_crtc->overlay);
3007 dev_priv->mm.interruptible = true;
3008 mutex_unlock(&dev->struct_mutex);
3009 }
3010
3011 /* Let userspace switch the overlay on again. In most cases userspace
3012 * has to recompute where to put it anyway.
3013 */
3014 }
3015
3016 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3017 {
3018 struct drm_device *dev = crtc->dev;
3019 struct drm_i915_private *dev_priv = dev->dev_private;
3020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3021 int pipe = intel_crtc->pipe;
3022 int plane = intel_crtc->plane;
3023
3024 if (intel_crtc->active)
3025 return;
3026
3027 intel_crtc->active = true;
3028 intel_update_watermarks(dev);
3029
3030 intel_enable_pll(dev_priv, pipe);
3031 intel_enable_pipe(dev_priv, pipe, false);
3032 intel_enable_plane(dev_priv, plane, pipe);
3033
3034 intel_crtc_load_lut(crtc);
3035 intel_update_fbc(dev);
3036
3037 /* Give the overlay scaler a chance to enable if it's on this pipe */
3038 intel_crtc_dpms_overlay(intel_crtc, true);
3039 intel_crtc_update_cursor(crtc, true);
3040 }
3041
3042 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3043 {
3044 struct drm_device *dev = crtc->dev;
3045 struct drm_i915_private *dev_priv = dev->dev_private;
3046 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3047 int pipe = intel_crtc->pipe;
3048 int plane = intel_crtc->plane;
3049
3050 if (!intel_crtc->active)
3051 return;
3052
3053 /* Give the overlay scaler a chance to disable if it's on this pipe */
3054 intel_crtc_wait_for_pending_flips(crtc);
3055 drm_vblank_off(dev, pipe);
3056 intel_crtc_dpms_overlay(intel_crtc, false);
3057 intel_crtc_update_cursor(crtc, false);
3058
3059 if (dev_priv->cfb_plane == plane &&
3060 dev_priv->display.disable_fbc)
3061 dev_priv->display.disable_fbc(dev);
3062
3063 intel_disable_plane(dev_priv, plane, pipe);
3064 intel_disable_pipe(dev_priv, pipe);
3065 intel_disable_pll(dev_priv, pipe);
3066
3067 intel_crtc->active = false;
3068 intel_update_fbc(dev);
3069 intel_update_watermarks(dev);
3070 intel_clear_scanline_wait(dev);
3071 }
3072
3073 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3074 {
3075 /* XXX: When our outputs are all unaware of DPMS modes other than off
3076 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3077 */
3078 switch (mode) {
3079 case DRM_MODE_DPMS_ON:
3080 case DRM_MODE_DPMS_STANDBY:
3081 case DRM_MODE_DPMS_SUSPEND:
3082 i9xx_crtc_enable(crtc);
3083 break;
3084 case DRM_MODE_DPMS_OFF:
3085 i9xx_crtc_disable(crtc);
3086 break;
3087 }
3088 }
3089
3090 /**
3091 * Sets the power management mode of the pipe and plane.
3092 */
3093 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3094 {
3095 struct drm_device *dev = crtc->dev;
3096 struct drm_i915_private *dev_priv = dev->dev_private;
3097 struct drm_i915_master_private *master_priv;
3098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3099 int pipe = intel_crtc->pipe;
3100 bool enabled;
3101
3102 if (intel_crtc->dpms_mode == mode)
3103 return;
3104
3105 intel_crtc->dpms_mode = mode;
3106
3107 dev_priv->display.dpms(crtc, mode);
3108
3109 if (!dev->primary->master)
3110 return;
3111
3112 master_priv = dev->primary->master->driver_priv;
3113 if (!master_priv->sarea_priv)
3114 return;
3115
3116 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3117
3118 switch (pipe) {
3119 case 0:
3120 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3121 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3122 break;
3123 case 1:
3124 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3125 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3126 break;
3127 default:
3128 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3129 break;
3130 }
3131 }
3132
3133 static void intel_crtc_disable(struct drm_crtc *crtc)
3134 {
3135 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3136 struct drm_device *dev = crtc->dev;
3137
3138 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3139
3140 if (crtc->fb) {
3141 mutex_lock(&dev->struct_mutex);
3142 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3143 mutex_unlock(&dev->struct_mutex);
3144 }
3145 }
3146
3147 /* Prepare for a mode set.
3148 *
3149 * Note we could be a lot smarter here. We need to figure out which outputs
3150 * will be enabled, which disabled (in short, how the config will changes)
3151 * and perform the minimum necessary steps to accomplish that, e.g. updating
3152 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3153 * panel fitting is in the proper state, etc.
3154 */
3155 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3156 {
3157 i9xx_crtc_disable(crtc);
3158 }
3159
3160 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3161 {
3162 i9xx_crtc_enable(crtc);
3163 }
3164
3165 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3166 {
3167 ironlake_crtc_disable(crtc);
3168 }
3169
3170 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3171 {
3172 ironlake_crtc_enable(crtc);
3173 }
3174
3175 void intel_encoder_prepare (struct drm_encoder *encoder)
3176 {
3177 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3178 /* lvds has its own version of prepare see intel_lvds_prepare */
3179 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3180 }
3181
3182 void intel_encoder_commit (struct drm_encoder *encoder)
3183 {
3184 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3185 /* lvds has its own version of commit see intel_lvds_commit */
3186 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3187 }
3188
3189 void intel_encoder_destroy(struct drm_encoder *encoder)
3190 {
3191 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3192
3193 drm_encoder_cleanup(encoder);
3194 kfree(intel_encoder);
3195 }
3196
3197 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3198 struct drm_display_mode *mode,
3199 struct drm_display_mode *adjusted_mode)
3200 {
3201 struct drm_device *dev = crtc->dev;
3202
3203 if (HAS_PCH_SPLIT(dev)) {
3204 /* FDI link clock is fixed at 2.7G */
3205 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3206 return false;
3207 }
3208
3209 /* XXX some encoders set the crtcinfo, others don't.
3210 * Obviously we need some form of conflict resolution here...
3211 */
3212 if (adjusted_mode->crtc_htotal == 0)
3213 drm_mode_set_crtcinfo(adjusted_mode, 0);
3214
3215 return true;
3216 }
3217
3218 static int i945_get_display_clock_speed(struct drm_device *dev)
3219 {
3220 return 400000;
3221 }
3222
3223 static int i915_get_display_clock_speed(struct drm_device *dev)
3224 {
3225 return 333000;
3226 }
3227
3228 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3229 {
3230 return 200000;
3231 }
3232
3233 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3234 {
3235 u16 gcfgc = 0;
3236
3237 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3238
3239 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3240 return 133000;
3241 else {
3242 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3243 case GC_DISPLAY_CLOCK_333_MHZ:
3244 return 333000;
3245 default:
3246 case GC_DISPLAY_CLOCK_190_200_MHZ:
3247 return 190000;
3248 }
3249 }
3250 }
3251
3252 static int i865_get_display_clock_speed(struct drm_device *dev)
3253 {
3254 return 266000;
3255 }
3256
3257 static int i855_get_display_clock_speed(struct drm_device *dev)
3258 {
3259 u16 hpllcc = 0;
3260 /* Assume that the hardware is in the high speed state. This
3261 * should be the default.
3262 */
3263 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3264 case GC_CLOCK_133_200:
3265 case GC_CLOCK_100_200:
3266 return 200000;
3267 case GC_CLOCK_166_250:
3268 return 250000;
3269 case GC_CLOCK_100_133:
3270 return 133000;
3271 }
3272
3273 /* Shouldn't happen */
3274 return 0;
3275 }
3276
3277 static int i830_get_display_clock_speed(struct drm_device *dev)
3278 {
3279 return 133000;
3280 }
3281
3282 struct fdi_m_n {
3283 u32 tu;
3284 u32 gmch_m;
3285 u32 gmch_n;
3286 u32 link_m;
3287 u32 link_n;
3288 };
3289
3290 static void
3291 fdi_reduce_ratio(u32 *num, u32 *den)
3292 {
3293 while (*num > 0xffffff || *den > 0xffffff) {
3294 *num >>= 1;
3295 *den >>= 1;
3296 }
3297 }
3298
3299 static void
3300 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3301 int link_clock, struct fdi_m_n *m_n)
3302 {
3303 m_n->tu = 64; /* default size */
3304
3305 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3306 m_n->gmch_m = bits_per_pixel * pixel_clock;
3307 m_n->gmch_n = link_clock * nlanes * 8;
3308 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3309
3310 m_n->link_m = pixel_clock;
3311 m_n->link_n = link_clock;
3312 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3313 }
3314
3315
3316 struct intel_watermark_params {
3317 unsigned long fifo_size;
3318 unsigned long max_wm;
3319 unsigned long default_wm;
3320 unsigned long guard_size;
3321 unsigned long cacheline_size;
3322 };
3323
3324 /* Pineview has different values for various configs */
3325 static const struct intel_watermark_params pineview_display_wm = {
3326 PINEVIEW_DISPLAY_FIFO,
3327 PINEVIEW_MAX_WM,
3328 PINEVIEW_DFT_WM,
3329 PINEVIEW_GUARD_WM,
3330 PINEVIEW_FIFO_LINE_SIZE
3331 };
3332 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3333 PINEVIEW_DISPLAY_FIFO,
3334 PINEVIEW_MAX_WM,
3335 PINEVIEW_DFT_HPLLOFF_WM,
3336 PINEVIEW_GUARD_WM,
3337 PINEVIEW_FIFO_LINE_SIZE
3338 };
3339 static const struct intel_watermark_params pineview_cursor_wm = {
3340 PINEVIEW_CURSOR_FIFO,
3341 PINEVIEW_CURSOR_MAX_WM,
3342 PINEVIEW_CURSOR_DFT_WM,
3343 PINEVIEW_CURSOR_GUARD_WM,
3344 PINEVIEW_FIFO_LINE_SIZE,
3345 };
3346 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3347 PINEVIEW_CURSOR_FIFO,
3348 PINEVIEW_CURSOR_MAX_WM,
3349 PINEVIEW_CURSOR_DFT_WM,
3350 PINEVIEW_CURSOR_GUARD_WM,
3351 PINEVIEW_FIFO_LINE_SIZE
3352 };
3353 static const struct intel_watermark_params g4x_wm_info = {
3354 G4X_FIFO_SIZE,
3355 G4X_MAX_WM,
3356 G4X_MAX_WM,
3357 2,
3358 G4X_FIFO_LINE_SIZE,
3359 };
3360 static const struct intel_watermark_params g4x_cursor_wm_info = {
3361 I965_CURSOR_FIFO,
3362 I965_CURSOR_MAX_WM,
3363 I965_CURSOR_DFT_WM,
3364 2,
3365 G4X_FIFO_LINE_SIZE,
3366 };
3367 static const struct intel_watermark_params i965_cursor_wm_info = {
3368 I965_CURSOR_FIFO,
3369 I965_CURSOR_MAX_WM,
3370 I965_CURSOR_DFT_WM,
3371 2,
3372 I915_FIFO_LINE_SIZE,
3373 };
3374 static const struct intel_watermark_params i945_wm_info = {
3375 I945_FIFO_SIZE,
3376 I915_MAX_WM,
3377 1,
3378 2,
3379 I915_FIFO_LINE_SIZE
3380 };
3381 static const struct intel_watermark_params i915_wm_info = {
3382 I915_FIFO_SIZE,
3383 I915_MAX_WM,
3384 1,
3385 2,
3386 I915_FIFO_LINE_SIZE
3387 };
3388 static const struct intel_watermark_params i855_wm_info = {
3389 I855GM_FIFO_SIZE,
3390 I915_MAX_WM,
3391 1,
3392 2,
3393 I830_FIFO_LINE_SIZE
3394 };
3395 static const struct intel_watermark_params i830_wm_info = {
3396 I830_FIFO_SIZE,
3397 I915_MAX_WM,
3398 1,
3399 2,
3400 I830_FIFO_LINE_SIZE
3401 };
3402
3403 static const struct intel_watermark_params ironlake_display_wm_info = {
3404 ILK_DISPLAY_FIFO,
3405 ILK_DISPLAY_MAXWM,
3406 ILK_DISPLAY_DFTWM,
3407 2,
3408 ILK_FIFO_LINE_SIZE
3409 };
3410 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3411 ILK_CURSOR_FIFO,
3412 ILK_CURSOR_MAXWM,
3413 ILK_CURSOR_DFTWM,
3414 2,
3415 ILK_FIFO_LINE_SIZE
3416 };
3417 static const struct intel_watermark_params ironlake_display_srwm_info = {
3418 ILK_DISPLAY_SR_FIFO,
3419 ILK_DISPLAY_MAX_SRWM,
3420 ILK_DISPLAY_DFT_SRWM,
3421 2,
3422 ILK_FIFO_LINE_SIZE
3423 };
3424 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3425 ILK_CURSOR_SR_FIFO,
3426 ILK_CURSOR_MAX_SRWM,
3427 ILK_CURSOR_DFT_SRWM,
3428 2,
3429 ILK_FIFO_LINE_SIZE
3430 };
3431
3432 static const struct intel_watermark_params sandybridge_display_wm_info = {
3433 SNB_DISPLAY_FIFO,
3434 SNB_DISPLAY_MAXWM,
3435 SNB_DISPLAY_DFTWM,
3436 2,
3437 SNB_FIFO_LINE_SIZE
3438 };
3439 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3440 SNB_CURSOR_FIFO,
3441 SNB_CURSOR_MAXWM,
3442 SNB_CURSOR_DFTWM,
3443 2,
3444 SNB_FIFO_LINE_SIZE
3445 };
3446 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3447 SNB_DISPLAY_SR_FIFO,
3448 SNB_DISPLAY_MAX_SRWM,
3449 SNB_DISPLAY_DFT_SRWM,
3450 2,
3451 SNB_FIFO_LINE_SIZE
3452 };
3453 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3454 SNB_CURSOR_SR_FIFO,
3455 SNB_CURSOR_MAX_SRWM,
3456 SNB_CURSOR_DFT_SRWM,
3457 2,
3458 SNB_FIFO_LINE_SIZE
3459 };
3460
3461
3462 /**
3463 * intel_calculate_wm - calculate watermark level
3464 * @clock_in_khz: pixel clock
3465 * @wm: chip FIFO params
3466 * @pixel_size: display pixel size
3467 * @latency_ns: memory latency for the platform
3468 *
3469 * Calculate the watermark level (the level at which the display plane will
3470 * start fetching from memory again). Each chip has a different display
3471 * FIFO size and allocation, so the caller needs to figure that out and pass
3472 * in the correct intel_watermark_params structure.
3473 *
3474 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3475 * on the pixel size. When it reaches the watermark level, it'll start
3476 * fetching FIFO line sized based chunks from memory until the FIFO fills
3477 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3478 * will occur, and a display engine hang could result.
3479 */
3480 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3481 const struct intel_watermark_params *wm,
3482 int fifo_size,
3483 int pixel_size,
3484 unsigned long latency_ns)
3485 {
3486 long entries_required, wm_size;
3487
3488 /*
3489 * Note: we need to make sure we don't overflow for various clock &
3490 * latency values.
3491 * clocks go from a few thousand to several hundred thousand.
3492 * latency is usually a few thousand
3493 */
3494 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3495 1000;
3496 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3497
3498 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
3499
3500 wm_size = fifo_size - (entries_required + wm->guard_size);
3501
3502 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
3503
3504 /* Don't promote wm_size to unsigned... */
3505 if (wm_size > (long)wm->max_wm)
3506 wm_size = wm->max_wm;
3507 if (wm_size <= 0)
3508 wm_size = wm->default_wm;
3509 return wm_size;
3510 }
3511
3512 struct cxsr_latency {
3513 int is_desktop;
3514 int is_ddr3;
3515 unsigned long fsb_freq;
3516 unsigned long mem_freq;
3517 unsigned long display_sr;
3518 unsigned long display_hpll_disable;
3519 unsigned long cursor_sr;
3520 unsigned long cursor_hpll_disable;
3521 };
3522
3523 static const struct cxsr_latency cxsr_latency_table[] = {
3524 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3525 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3526 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3527 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3528 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3529
3530 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3531 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3532 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3533 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3534 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3535
3536 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3537 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3538 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3539 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3540 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3541
3542 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3543 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3544 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3545 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3546 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3547
3548 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3549 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3550 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3551 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3552 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3553
3554 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3555 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3556 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3557 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3558 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3559 };
3560
3561 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3562 int is_ddr3,
3563 int fsb,
3564 int mem)
3565 {
3566 const struct cxsr_latency *latency;
3567 int i;
3568
3569 if (fsb == 0 || mem == 0)
3570 return NULL;
3571
3572 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3573 latency = &cxsr_latency_table[i];
3574 if (is_desktop == latency->is_desktop &&
3575 is_ddr3 == latency->is_ddr3 &&
3576 fsb == latency->fsb_freq && mem == latency->mem_freq)
3577 return latency;
3578 }
3579
3580 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3581
3582 return NULL;
3583 }
3584
3585 static void pineview_disable_cxsr(struct drm_device *dev)
3586 {
3587 struct drm_i915_private *dev_priv = dev->dev_private;
3588
3589 /* deactivate cxsr */
3590 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3591 }
3592
3593 /*
3594 * Latency for FIFO fetches is dependent on several factors:
3595 * - memory configuration (speed, channels)
3596 * - chipset
3597 * - current MCH state
3598 * It can be fairly high in some situations, so here we assume a fairly
3599 * pessimal value. It's a tradeoff between extra memory fetches (if we
3600 * set this value too high, the FIFO will fetch frequently to stay full)
3601 * and power consumption (set it too low to save power and we might see
3602 * FIFO underruns and display "flicker").
3603 *
3604 * A value of 5us seems to be a good balance; safe for very low end
3605 * platforms but not overly aggressive on lower latency configs.
3606 */
3607 static const int latency_ns = 5000;
3608
3609 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3610 {
3611 struct drm_i915_private *dev_priv = dev->dev_private;
3612 uint32_t dsparb = I915_READ(DSPARB);
3613 int size;
3614
3615 size = dsparb & 0x7f;
3616 if (plane)
3617 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3618
3619 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3620 plane ? "B" : "A", size);
3621
3622 return size;
3623 }
3624
3625 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3626 {
3627 struct drm_i915_private *dev_priv = dev->dev_private;
3628 uint32_t dsparb = I915_READ(DSPARB);
3629 int size;
3630
3631 size = dsparb & 0x1ff;
3632 if (plane)
3633 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3634 size >>= 1; /* Convert to cachelines */
3635
3636 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3637 plane ? "B" : "A", size);
3638
3639 return size;
3640 }
3641
3642 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3643 {
3644 struct drm_i915_private *dev_priv = dev->dev_private;
3645 uint32_t dsparb = I915_READ(DSPARB);
3646 int size;
3647
3648 size = dsparb & 0x7f;
3649 size >>= 2; /* Convert to cachelines */
3650
3651 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3652 plane ? "B" : "A",
3653 size);
3654
3655 return size;
3656 }
3657
3658 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3659 {
3660 struct drm_i915_private *dev_priv = dev->dev_private;
3661 uint32_t dsparb = I915_READ(DSPARB);
3662 int size;
3663
3664 size = dsparb & 0x7f;
3665 size >>= 1; /* Convert to cachelines */
3666
3667 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3668 plane ? "B" : "A", size);
3669
3670 return size;
3671 }
3672
3673 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3674 {
3675 struct drm_crtc *crtc, *enabled = NULL;
3676
3677 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3678 if (crtc->enabled && crtc->fb) {
3679 if (enabled)
3680 return NULL;
3681 enabled = crtc;
3682 }
3683 }
3684
3685 return enabled;
3686 }
3687
3688 static void pineview_update_wm(struct drm_device *dev)
3689 {
3690 struct drm_i915_private *dev_priv = dev->dev_private;
3691 struct drm_crtc *crtc;
3692 const struct cxsr_latency *latency;
3693 u32 reg;
3694 unsigned long wm;
3695
3696 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3697 dev_priv->fsb_freq, dev_priv->mem_freq);
3698 if (!latency) {
3699 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3700 pineview_disable_cxsr(dev);
3701 return;
3702 }
3703
3704 crtc = single_enabled_crtc(dev);
3705 if (crtc) {
3706 int clock = crtc->mode.clock;
3707 int pixel_size = crtc->fb->bits_per_pixel / 8;
3708
3709 /* Display SR */
3710 wm = intel_calculate_wm(clock, &pineview_display_wm,
3711 pineview_display_wm.fifo_size,
3712 pixel_size, latency->display_sr);
3713 reg = I915_READ(DSPFW1);
3714 reg &= ~DSPFW_SR_MASK;
3715 reg |= wm << DSPFW_SR_SHIFT;
3716 I915_WRITE(DSPFW1, reg);
3717 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3718
3719 /* cursor SR */
3720 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3721 pineview_display_wm.fifo_size,
3722 pixel_size, latency->cursor_sr);
3723 reg = I915_READ(DSPFW3);
3724 reg &= ~DSPFW_CURSOR_SR_MASK;
3725 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3726 I915_WRITE(DSPFW3, reg);
3727
3728 /* Display HPLL off SR */
3729 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3730 pineview_display_hplloff_wm.fifo_size,
3731 pixel_size, latency->display_hpll_disable);
3732 reg = I915_READ(DSPFW3);
3733 reg &= ~DSPFW_HPLL_SR_MASK;
3734 reg |= wm & DSPFW_HPLL_SR_MASK;
3735 I915_WRITE(DSPFW3, reg);
3736
3737 /* cursor HPLL off SR */
3738 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3739 pineview_display_hplloff_wm.fifo_size,
3740 pixel_size, latency->cursor_hpll_disable);
3741 reg = I915_READ(DSPFW3);
3742 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3743 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3744 I915_WRITE(DSPFW3, reg);
3745 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3746
3747 /* activate cxsr */
3748 I915_WRITE(DSPFW3,
3749 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3750 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3751 } else {
3752 pineview_disable_cxsr(dev);
3753 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3754 }
3755 }
3756
3757 static bool g4x_compute_wm0(struct drm_device *dev,
3758 int plane,
3759 const struct intel_watermark_params *display,
3760 int display_latency_ns,
3761 const struct intel_watermark_params *cursor,
3762 int cursor_latency_ns,
3763 int *plane_wm,
3764 int *cursor_wm)
3765 {
3766 struct drm_crtc *crtc;
3767 int htotal, hdisplay, clock, pixel_size;
3768 int line_time_us, line_count;
3769 int entries, tlb_miss;
3770
3771 crtc = intel_get_crtc_for_plane(dev, plane);
3772 if (crtc->fb == NULL || !crtc->enabled)
3773 return false;
3774
3775 htotal = crtc->mode.htotal;
3776 hdisplay = crtc->mode.hdisplay;
3777 clock = crtc->mode.clock;
3778 pixel_size = crtc->fb->bits_per_pixel / 8;
3779
3780 /* Use the small buffer method to calculate plane watermark */
3781 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3782 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3783 if (tlb_miss > 0)
3784 entries += tlb_miss;
3785 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3786 *plane_wm = entries + display->guard_size;
3787 if (*plane_wm > (int)display->max_wm)
3788 *plane_wm = display->max_wm;
3789
3790 /* Use the large buffer method to calculate cursor watermark */
3791 line_time_us = ((htotal * 1000) / clock);
3792 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3793 entries = line_count * 64 * pixel_size;
3794 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3795 if (tlb_miss > 0)
3796 entries += tlb_miss;
3797 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3798 *cursor_wm = entries + cursor->guard_size;
3799 if (*cursor_wm > (int)cursor->max_wm)
3800 *cursor_wm = (int)cursor->max_wm;
3801
3802 return true;
3803 }
3804
3805 /*
3806 * Check the wm result.
3807 *
3808 * If any calculated watermark values is larger than the maximum value that
3809 * can be programmed into the associated watermark register, that watermark
3810 * must be disabled.
3811 */
3812 static bool g4x_check_srwm(struct drm_device *dev,
3813 int display_wm, int cursor_wm,
3814 const struct intel_watermark_params *display,
3815 const struct intel_watermark_params *cursor)
3816 {
3817 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3818 display_wm, cursor_wm);
3819
3820 if (display_wm > display->max_wm) {
3821 DRM_DEBUG_KMS("display watermark is too large(%d), disabling\n",
3822 display_wm, display->max_wm);
3823 return false;
3824 }
3825
3826 if (cursor_wm > cursor->max_wm) {
3827 DRM_DEBUG_KMS("cursor watermark is too large(%d), disabling\n",
3828 cursor_wm, cursor->max_wm);
3829 return false;
3830 }
3831
3832 if (!(display_wm || cursor_wm)) {
3833 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3834 return false;
3835 }
3836
3837 return true;
3838 }
3839
3840 static bool g4x_compute_srwm(struct drm_device *dev,
3841 int plane,
3842 int latency_ns,
3843 const struct intel_watermark_params *display,
3844 const struct intel_watermark_params *cursor,
3845 int *display_wm, int *cursor_wm)
3846 {
3847 struct drm_crtc *crtc;
3848 int hdisplay, htotal, pixel_size, clock;
3849 unsigned long line_time_us;
3850 int line_count, line_size;
3851 int small, large;
3852 int entries;
3853
3854 if (!latency_ns) {
3855 *display_wm = *cursor_wm = 0;
3856 return false;
3857 }
3858
3859 crtc = intel_get_crtc_for_plane(dev, plane);
3860 hdisplay = crtc->mode.hdisplay;
3861 htotal = crtc->mode.htotal;
3862 clock = crtc->mode.clock;
3863 pixel_size = crtc->fb->bits_per_pixel / 8;
3864
3865 line_time_us = (htotal * 1000) / clock;
3866 line_count = (latency_ns / line_time_us + 1000) / 1000;
3867 line_size = hdisplay * pixel_size;
3868
3869 /* Use the minimum of the small and large buffer method for primary */
3870 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3871 large = line_count * line_size;
3872
3873 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3874 *display_wm = entries + display->guard_size;
3875
3876 /* calculate the self-refresh watermark for display cursor */
3877 entries = line_count * pixel_size * 64;
3878 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3879 *cursor_wm = entries + cursor->guard_size;
3880
3881 return g4x_check_srwm(dev,
3882 *display_wm, *cursor_wm,
3883 display, cursor);
3884 }
3885
3886 static inline bool single_plane_enabled(unsigned int mask)
3887 {
3888 return mask && (mask & -mask) == 0;
3889 }
3890
3891 static void g4x_update_wm(struct drm_device *dev)
3892 {
3893 static const int sr_latency_ns = 12000;
3894 struct drm_i915_private *dev_priv = dev->dev_private;
3895 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3896 int plane_sr, cursor_sr;
3897 unsigned int enabled = 0;
3898
3899 if (g4x_compute_wm0(dev, 0,
3900 &g4x_wm_info, latency_ns,
3901 &g4x_cursor_wm_info, latency_ns,
3902 &planea_wm, &cursora_wm))
3903 enabled |= 1;
3904
3905 if (g4x_compute_wm0(dev, 1,
3906 &g4x_wm_info, latency_ns,
3907 &g4x_cursor_wm_info, latency_ns,
3908 &planeb_wm, &cursorb_wm))
3909 enabled |= 2;
3910
3911 plane_sr = cursor_sr = 0;
3912 if (single_plane_enabled(enabled) &&
3913 g4x_compute_srwm(dev, ffs(enabled) - 1,
3914 sr_latency_ns,
3915 &g4x_wm_info,
3916 &g4x_cursor_wm_info,
3917 &plane_sr, &cursor_sr))
3918 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3919 else
3920 I915_WRITE(FW_BLC_SELF,
3921 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
3922
3923 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3924 planea_wm, cursora_wm,
3925 planeb_wm, cursorb_wm,
3926 plane_sr, cursor_sr);
3927
3928 I915_WRITE(DSPFW1,
3929 (plane_sr << DSPFW_SR_SHIFT) |
3930 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3931 (planeb_wm << DSPFW_PLANEB_SHIFT) |
3932 planea_wm);
3933 I915_WRITE(DSPFW2,
3934 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3935 (cursora_wm << DSPFW_CURSORA_SHIFT));
3936 /* HPLL off in SR has some issues on G4x... disable it */
3937 I915_WRITE(DSPFW3,
3938 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3939 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3940 }
3941
3942 static void i965_update_wm(struct drm_device *dev)
3943 {
3944 struct drm_i915_private *dev_priv = dev->dev_private;
3945 struct drm_crtc *crtc;
3946 int srwm = 1;
3947 int cursor_sr = 16;
3948
3949 /* Calc sr entries for one plane configs */
3950 crtc = single_enabled_crtc(dev);
3951 if (crtc) {
3952 /* self-refresh has much higher latency */
3953 static const int sr_latency_ns = 12000;
3954 int clock = crtc->mode.clock;
3955 int htotal = crtc->mode.htotal;
3956 int hdisplay = crtc->mode.hdisplay;
3957 int pixel_size = crtc->fb->bits_per_pixel / 8;
3958 unsigned long line_time_us;
3959 int entries;
3960
3961 line_time_us = ((htotal * 1000) / clock);
3962
3963 /* Use ns/us then divide to preserve precision */
3964 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3965 pixel_size * hdisplay;
3966 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
3967 srwm = I965_FIFO_SIZE - entries;
3968 if (srwm < 0)
3969 srwm = 1;
3970 srwm &= 0x1ff;
3971 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3972 entries, srwm);
3973
3974 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3975 pixel_size * 64;
3976 entries = DIV_ROUND_UP(entries,
3977 i965_cursor_wm_info.cacheline_size);
3978 cursor_sr = i965_cursor_wm_info.fifo_size -
3979 (entries + i965_cursor_wm_info.guard_size);
3980
3981 if (cursor_sr > i965_cursor_wm_info.max_wm)
3982 cursor_sr = i965_cursor_wm_info.max_wm;
3983
3984 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3985 "cursor %d\n", srwm, cursor_sr);
3986
3987 if (IS_CRESTLINE(dev))
3988 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3989 } else {
3990 /* Turn off self refresh if both pipes are enabled */
3991 if (IS_CRESTLINE(dev))
3992 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3993 & ~FW_BLC_SELF_EN);
3994 }
3995
3996 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3997 srwm);
3998
3999 /* 965 has limitations... */
4000 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4001 (8 << 16) | (8 << 8) | (8 << 0));
4002 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4003 /* update cursor SR watermark */
4004 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4005 }
4006
4007 static void i9xx_update_wm(struct drm_device *dev)
4008 {
4009 struct drm_i915_private *dev_priv = dev->dev_private;
4010 const struct intel_watermark_params *wm_info;
4011 uint32_t fwater_lo;
4012 uint32_t fwater_hi;
4013 int cwm, srwm = 1;
4014 int fifo_size;
4015 int planea_wm, planeb_wm;
4016 struct drm_crtc *crtc, *enabled = NULL;
4017
4018 if (IS_I945GM(dev))
4019 wm_info = &i945_wm_info;
4020 else if (!IS_GEN2(dev))
4021 wm_info = &i915_wm_info;
4022 else
4023 wm_info = &i855_wm_info;
4024
4025 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4026 crtc = intel_get_crtc_for_plane(dev, 0);
4027 if (crtc->enabled && crtc->fb) {
4028 planea_wm = intel_calculate_wm(crtc->mode.clock,
4029 wm_info, fifo_size,
4030 crtc->fb->bits_per_pixel / 8,
4031 latency_ns);
4032 enabled = crtc;
4033 } else
4034 planea_wm = fifo_size - wm_info->guard_size;
4035
4036 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4037 crtc = intel_get_crtc_for_plane(dev, 1);
4038 if (crtc->enabled && crtc->fb) {
4039 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4040 wm_info, fifo_size,
4041 crtc->fb->bits_per_pixel / 8,
4042 latency_ns);
4043 if (enabled == NULL)
4044 enabled = crtc;
4045 else
4046 enabled = NULL;
4047 } else
4048 planeb_wm = fifo_size - wm_info->guard_size;
4049
4050 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4051
4052 /*
4053 * Overlay gets an aggressive default since video jitter is bad.
4054 */
4055 cwm = 2;
4056
4057 /* Play safe and disable self-refresh before adjusting watermarks. */
4058 if (IS_I945G(dev) || IS_I945GM(dev))
4059 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4060 else if (IS_I915GM(dev))
4061 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4062
4063 /* Calc sr entries for one plane configs */
4064 if (HAS_FW_BLC(dev) && enabled) {
4065 /* self-refresh has much higher latency */
4066 static const int sr_latency_ns = 6000;
4067 int clock = enabled->mode.clock;
4068 int htotal = enabled->mode.htotal;
4069 int hdisplay = enabled->mode.hdisplay;
4070 int pixel_size = enabled->fb->bits_per_pixel / 8;
4071 unsigned long line_time_us;
4072 int entries;
4073
4074 line_time_us = (htotal * 1000) / clock;
4075
4076 /* Use ns/us then divide to preserve precision */
4077 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4078 pixel_size * hdisplay;
4079 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4080 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4081 srwm = wm_info->fifo_size - entries;
4082 if (srwm < 0)
4083 srwm = 1;
4084
4085 if (IS_I945G(dev) || IS_I945GM(dev))
4086 I915_WRITE(FW_BLC_SELF,
4087 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4088 else if (IS_I915GM(dev))
4089 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4090 }
4091
4092 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4093 planea_wm, planeb_wm, cwm, srwm);
4094
4095 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4096 fwater_hi = (cwm & 0x1f);
4097
4098 /* Set request length to 8 cachelines per fetch */
4099 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4100 fwater_hi = fwater_hi | (1 << 8);
4101
4102 I915_WRITE(FW_BLC, fwater_lo);
4103 I915_WRITE(FW_BLC2, fwater_hi);
4104
4105 if (HAS_FW_BLC(dev)) {
4106 if (enabled) {
4107 if (IS_I945G(dev) || IS_I945GM(dev))
4108 I915_WRITE(FW_BLC_SELF,
4109 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4110 else if (IS_I915GM(dev))
4111 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4112 DRM_DEBUG_KMS("memory self refresh enabled\n");
4113 } else
4114 DRM_DEBUG_KMS("memory self refresh disabled\n");
4115 }
4116 }
4117
4118 static void i830_update_wm(struct drm_device *dev)
4119 {
4120 struct drm_i915_private *dev_priv = dev->dev_private;
4121 struct drm_crtc *crtc;
4122 uint32_t fwater_lo;
4123 int planea_wm;
4124
4125 crtc = single_enabled_crtc(dev);
4126 if (crtc == NULL)
4127 return;
4128
4129 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4130 dev_priv->display.get_fifo_size(dev, 0),
4131 crtc->fb->bits_per_pixel / 8,
4132 latency_ns);
4133 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4134 fwater_lo |= (3<<8) | planea_wm;
4135
4136 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4137
4138 I915_WRITE(FW_BLC, fwater_lo);
4139 }
4140
4141 #define ILK_LP0_PLANE_LATENCY 700
4142 #define ILK_LP0_CURSOR_LATENCY 1300
4143
4144 static bool ironlake_compute_wm0(struct drm_device *dev,
4145 int pipe,
4146 const struct intel_watermark_params *display,
4147 int display_latency_ns,
4148 const struct intel_watermark_params *cursor,
4149 int cursor_latency_ns,
4150 int *plane_wm,
4151 int *cursor_wm)
4152 {
4153 struct drm_crtc *crtc;
4154 int htotal, hdisplay, clock, pixel_size;
4155 int line_time_us, line_count;
4156 int entries, tlb_miss;
4157
4158 crtc = intel_get_crtc_for_pipe(dev, pipe);
4159 if (crtc->fb == NULL || !crtc->enabled)
4160 return false;
4161
4162 htotal = crtc->mode.htotal;
4163 hdisplay = crtc->mode.hdisplay;
4164 clock = crtc->mode.clock;
4165 pixel_size = crtc->fb->bits_per_pixel / 8;
4166
4167 /* Use the small buffer method to calculate plane watermark */
4168 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4169 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4170 if (tlb_miss > 0)
4171 entries += tlb_miss;
4172 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4173 *plane_wm = entries + display->guard_size;
4174 if (*plane_wm > (int)display->max_wm)
4175 *plane_wm = display->max_wm;
4176
4177 /* Use the large buffer method to calculate cursor watermark */
4178 line_time_us = ((htotal * 1000) / clock);
4179 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4180 entries = line_count * 64 * pixel_size;
4181 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4182 if (tlb_miss > 0)
4183 entries += tlb_miss;
4184 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4185 *cursor_wm = entries + cursor->guard_size;
4186 if (*cursor_wm > (int)cursor->max_wm)
4187 *cursor_wm = (int)cursor->max_wm;
4188
4189 return true;
4190 }
4191
4192 /*
4193 * Check the wm result.
4194 *
4195 * If any calculated watermark values is larger than the maximum value that
4196 * can be programmed into the associated watermark register, that watermark
4197 * must be disabled.
4198 */
4199 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4200 int fbc_wm, int display_wm, int cursor_wm,
4201 const struct intel_watermark_params *display,
4202 const struct intel_watermark_params *cursor)
4203 {
4204 struct drm_i915_private *dev_priv = dev->dev_private;
4205
4206 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4207 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4208
4209 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4210 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4211 fbc_wm, SNB_FBC_MAX_SRWM, level);
4212
4213 /* fbc has it's own way to disable FBC WM */
4214 I915_WRITE(DISP_ARB_CTL,
4215 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4216 return false;
4217 }
4218
4219 if (display_wm > display->max_wm) {
4220 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4221 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4222 return false;
4223 }
4224
4225 if (cursor_wm > cursor->max_wm) {
4226 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4227 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4228 return false;
4229 }
4230
4231 if (!(fbc_wm || display_wm || cursor_wm)) {
4232 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4233 return false;
4234 }
4235
4236 return true;
4237 }
4238
4239 /*
4240 * Compute watermark values of WM[1-3],
4241 */
4242 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4243 int latency_ns,
4244 const struct intel_watermark_params *display,
4245 const struct intel_watermark_params *cursor,
4246 int *fbc_wm, int *display_wm, int *cursor_wm)
4247 {
4248 struct drm_crtc *crtc;
4249 unsigned long line_time_us;
4250 int hdisplay, htotal, pixel_size, clock;
4251 int line_count, line_size;
4252 int small, large;
4253 int entries;
4254
4255 if (!latency_ns) {
4256 *fbc_wm = *display_wm = *cursor_wm = 0;
4257 return false;
4258 }
4259
4260 crtc = intel_get_crtc_for_plane(dev, plane);
4261 hdisplay = crtc->mode.hdisplay;
4262 htotal = crtc->mode.htotal;
4263 clock = crtc->mode.clock;
4264 pixel_size = crtc->fb->bits_per_pixel / 8;
4265
4266 line_time_us = (htotal * 1000) / clock;
4267 line_count = (latency_ns / line_time_us + 1000) / 1000;
4268 line_size = hdisplay * pixel_size;
4269
4270 /* Use the minimum of the small and large buffer method for primary */
4271 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4272 large = line_count * line_size;
4273
4274 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4275 *display_wm = entries + display->guard_size;
4276
4277 /*
4278 * Spec says:
4279 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4280 */
4281 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4282
4283 /* calculate the self-refresh watermark for display cursor */
4284 entries = line_count * pixel_size * 64;
4285 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4286 *cursor_wm = entries + cursor->guard_size;
4287
4288 return ironlake_check_srwm(dev, level,
4289 *fbc_wm, *display_wm, *cursor_wm,
4290 display, cursor);
4291 }
4292
4293 static void ironlake_update_wm(struct drm_device *dev)
4294 {
4295 struct drm_i915_private *dev_priv = dev->dev_private;
4296 int fbc_wm, plane_wm, cursor_wm;
4297 unsigned int enabled;
4298
4299 enabled = 0;
4300 if (ironlake_compute_wm0(dev, 0,
4301 &ironlake_display_wm_info,
4302 ILK_LP0_PLANE_LATENCY,
4303 &ironlake_cursor_wm_info,
4304 ILK_LP0_CURSOR_LATENCY,
4305 &plane_wm, &cursor_wm)) {
4306 I915_WRITE(WM0_PIPEA_ILK,
4307 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4308 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4309 " plane %d, " "cursor: %d\n",
4310 plane_wm, cursor_wm);
4311 enabled |= 1;
4312 }
4313
4314 if (ironlake_compute_wm0(dev, 1,
4315 &ironlake_display_wm_info,
4316 ILK_LP0_PLANE_LATENCY,
4317 &ironlake_cursor_wm_info,
4318 ILK_LP0_CURSOR_LATENCY,
4319 &plane_wm, &cursor_wm)) {
4320 I915_WRITE(WM0_PIPEB_ILK,
4321 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4322 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4323 " plane %d, cursor: %d\n",
4324 plane_wm, cursor_wm);
4325 enabled |= 2;
4326 }
4327
4328 /*
4329 * Calculate and update the self-refresh watermark only when one
4330 * display plane is used.
4331 */
4332 I915_WRITE(WM3_LP_ILK, 0);
4333 I915_WRITE(WM2_LP_ILK, 0);
4334 I915_WRITE(WM1_LP_ILK, 0);
4335
4336 if (!single_plane_enabled(enabled))
4337 return;
4338 enabled = ffs(enabled) - 1;
4339
4340 /* WM1 */
4341 if (!ironlake_compute_srwm(dev, 1, enabled,
4342 ILK_READ_WM1_LATENCY() * 500,
4343 &ironlake_display_srwm_info,
4344 &ironlake_cursor_srwm_info,
4345 &fbc_wm, &plane_wm, &cursor_wm))
4346 return;
4347
4348 I915_WRITE(WM1_LP_ILK,
4349 WM1_LP_SR_EN |
4350 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4351 (fbc_wm << WM1_LP_FBC_SHIFT) |
4352 (plane_wm << WM1_LP_SR_SHIFT) |
4353 cursor_wm);
4354
4355 /* WM2 */
4356 if (!ironlake_compute_srwm(dev, 2, enabled,
4357 ILK_READ_WM2_LATENCY() * 500,
4358 &ironlake_display_srwm_info,
4359 &ironlake_cursor_srwm_info,
4360 &fbc_wm, &plane_wm, &cursor_wm))
4361 return;
4362
4363 I915_WRITE(WM2_LP_ILK,
4364 WM2_LP_EN |
4365 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4366 (fbc_wm << WM1_LP_FBC_SHIFT) |
4367 (plane_wm << WM1_LP_SR_SHIFT) |
4368 cursor_wm);
4369
4370 /*
4371 * WM3 is unsupported on ILK, probably because we don't have latency
4372 * data for that power state
4373 */
4374 }
4375
4376 static void sandybridge_update_wm(struct drm_device *dev)
4377 {
4378 struct drm_i915_private *dev_priv = dev->dev_private;
4379 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4380 int fbc_wm, plane_wm, cursor_wm;
4381 unsigned int enabled;
4382
4383 enabled = 0;
4384 if (ironlake_compute_wm0(dev, 0,
4385 &sandybridge_display_wm_info, latency,
4386 &sandybridge_cursor_wm_info, latency,
4387 &plane_wm, &cursor_wm)) {
4388 I915_WRITE(WM0_PIPEA_ILK,
4389 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4390 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4391 " plane %d, " "cursor: %d\n",
4392 plane_wm, cursor_wm);
4393 enabled |= 1;
4394 }
4395
4396 if (ironlake_compute_wm0(dev, 1,
4397 &sandybridge_display_wm_info, latency,
4398 &sandybridge_cursor_wm_info, latency,
4399 &plane_wm, &cursor_wm)) {
4400 I915_WRITE(WM0_PIPEB_ILK,
4401 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4402 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4403 " plane %d, cursor: %d\n",
4404 plane_wm, cursor_wm);
4405 enabled |= 2;
4406 }
4407
4408 /*
4409 * Calculate and update the self-refresh watermark only when one
4410 * display plane is used.
4411 *
4412 * SNB support 3 levels of watermark.
4413 *
4414 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4415 * and disabled in the descending order
4416 *
4417 */
4418 I915_WRITE(WM3_LP_ILK, 0);
4419 I915_WRITE(WM2_LP_ILK, 0);
4420 I915_WRITE(WM1_LP_ILK, 0);
4421
4422 if (!single_plane_enabled(enabled))
4423 return;
4424 enabled = ffs(enabled) - 1;
4425
4426 /* WM1 */
4427 if (!ironlake_compute_srwm(dev, 1, enabled,
4428 SNB_READ_WM1_LATENCY() * 500,
4429 &sandybridge_display_srwm_info,
4430 &sandybridge_cursor_srwm_info,
4431 &fbc_wm, &plane_wm, &cursor_wm))
4432 return;
4433
4434 I915_WRITE(WM1_LP_ILK,
4435 WM1_LP_SR_EN |
4436 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4437 (fbc_wm << WM1_LP_FBC_SHIFT) |
4438 (plane_wm << WM1_LP_SR_SHIFT) |
4439 cursor_wm);
4440
4441 /* WM2 */
4442 if (!ironlake_compute_srwm(dev, 2, enabled,
4443 SNB_READ_WM2_LATENCY() * 500,
4444 &sandybridge_display_srwm_info,
4445 &sandybridge_cursor_srwm_info,
4446 &fbc_wm, &plane_wm, &cursor_wm))
4447 return;
4448
4449 I915_WRITE(WM2_LP_ILK,
4450 WM2_LP_EN |
4451 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4452 (fbc_wm << WM1_LP_FBC_SHIFT) |
4453 (plane_wm << WM1_LP_SR_SHIFT) |
4454 cursor_wm);
4455
4456 /* WM3 */
4457 if (!ironlake_compute_srwm(dev, 3, enabled,
4458 SNB_READ_WM3_LATENCY() * 500,
4459 &sandybridge_display_srwm_info,
4460 &sandybridge_cursor_srwm_info,
4461 &fbc_wm, &plane_wm, &cursor_wm))
4462 return;
4463
4464 I915_WRITE(WM3_LP_ILK,
4465 WM3_LP_EN |
4466 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4467 (fbc_wm << WM1_LP_FBC_SHIFT) |
4468 (plane_wm << WM1_LP_SR_SHIFT) |
4469 cursor_wm);
4470 }
4471
4472 /**
4473 * intel_update_watermarks - update FIFO watermark values based on current modes
4474 *
4475 * Calculate watermark values for the various WM regs based on current mode
4476 * and plane configuration.
4477 *
4478 * There are several cases to deal with here:
4479 * - normal (i.e. non-self-refresh)
4480 * - self-refresh (SR) mode
4481 * - lines are large relative to FIFO size (buffer can hold up to 2)
4482 * - lines are small relative to FIFO size (buffer can hold more than 2
4483 * lines), so need to account for TLB latency
4484 *
4485 * The normal calculation is:
4486 * watermark = dotclock * bytes per pixel * latency
4487 * where latency is platform & configuration dependent (we assume pessimal
4488 * values here).
4489 *
4490 * The SR calculation is:
4491 * watermark = (trunc(latency/line time)+1) * surface width *
4492 * bytes per pixel
4493 * where
4494 * line time = htotal / dotclock
4495 * surface width = hdisplay for normal plane and 64 for cursor
4496 * and latency is assumed to be high, as above.
4497 *
4498 * The final value programmed to the register should always be rounded up,
4499 * and include an extra 2 entries to account for clock crossings.
4500 *
4501 * We don't use the sprite, so we can ignore that. And on Crestline we have
4502 * to set the non-SR watermarks to 8.
4503 */
4504 static void intel_update_watermarks(struct drm_device *dev)
4505 {
4506 struct drm_i915_private *dev_priv = dev->dev_private;
4507
4508 if (dev_priv->display.update_wm)
4509 dev_priv->display.update_wm(dev);
4510 }
4511
4512 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4513 {
4514 return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
4515 }
4516
4517 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4518 struct drm_display_mode *mode,
4519 struct drm_display_mode *adjusted_mode,
4520 int x, int y,
4521 struct drm_framebuffer *old_fb)
4522 {
4523 struct drm_device *dev = crtc->dev;
4524 struct drm_i915_private *dev_priv = dev->dev_private;
4525 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4526 int pipe = intel_crtc->pipe;
4527 int plane = intel_crtc->plane;
4528 u32 fp_reg, dpll_reg;
4529 int refclk, num_connectors = 0;
4530 intel_clock_t clock, reduced_clock;
4531 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4532 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4533 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4534 struct intel_encoder *has_edp_encoder = NULL;
4535 struct drm_mode_config *mode_config = &dev->mode_config;
4536 struct intel_encoder *encoder;
4537 const intel_limit_t *limit;
4538 int ret;
4539 struct fdi_m_n m_n = {0};
4540 u32 reg, temp;
4541 u32 lvds_sync = 0;
4542 int target_clock;
4543
4544 drm_vblank_pre_modeset(dev, pipe);
4545
4546 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4547 if (encoder->base.crtc != crtc)
4548 continue;
4549
4550 switch (encoder->type) {
4551 case INTEL_OUTPUT_LVDS:
4552 is_lvds = true;
4553 break;
4554 case INTEL_OUTPUT_SDVO:
4555 case INTEL_OUTPUT_HDMI:
4556 is_sdvo = true;
4557 if (encoder->needs_tv_clock)
4558 is_tv = true;
4559 break;
4560 case INTEL_OUTPUT_DVO:
4561 is_dvo = true;
4562 break;
4563 case INTEL_OUTPUT_TVOUT:
4564 is_tv = true;
4565 break;
4566 case INTEL_OUTPUT_ANALOG:
4567 is_crt = true;
4568 break;
4569 case INTEL_OUTPUT_DISPLAYPORT:
4570 is_dp = true;
4571 break;
4572 case INTEL_OUTPUT_EDP:
4573 has_edp_encoder = encoder;
4574 break;
4575 }
4576
4577 num_connectors++;
4578 }
4579
4580 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4581 refclk = dev_priv->lvds_ssc_freq * 1000;
4582 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4583 refclk / 1000);
4584 } else if (!IS_GEN2(dev)) {
4585 refclk = 96000;
4586 if (HAS_PCH_SPLIT(dev) &&
4587 (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
4588 refclk = 120000; /* 120Mhz refclk */
4589 } else {
4590 refclk = 48000;
4591 }
4592
4593 /*
4594 * Returns a set of divisors for the desired target clock with the given
4595 * refclk, or FALSE. The returned values represent the clock equation:
4596 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4597 */
4598 limit = intel_limit(crtc, refclk);
4599 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4600 if (!ok) {
4601 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4602 drm_vblank_post_modeset(dev, pipe);
4603 return -EINVAL;
4604 }
4605
4606 /* Ensure that the cursor is valid for the new mode before changing... */
4607 intel_crtc_update_cursor(crtc, true);
4608
4609 if (is_lvds && dev_priv->lvds_downclock_avail) {
4610 has_reduced_clock = limit->find_pll(limit, crtc,
4611 dev_priv->lvds_downclock,
4612 refclk,
4613 &reduced_clock);
4614 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4615 /*
4616 * If the different P is found, it means that we can't
4617 * switch the display clock by using the FP0/FP1.
4618 * In such case we will disable the LVDS downclock
4619 * feature.
4620 */
4621 DRM_DEBUG_KMS("Different P is found for "
4622 "LVDS clock/downclock\n");
4623 has_reduced_clock = 0;
4624 }
4625 }
4626 /* SDVO TV has fixed PLL values depend on its clock range,
4627 this mirrors vbios setting. */
4628 if (is_sdvo && is_tv) {
4629 if (adjusted_mode->clock >= 100000
4630 && adjusted_mode->clock < 140500) {
4631 clock.p1 = 2;
4632 clock.p2 = 10;
4633 clock.n = 3;
4634 clock.m1 = 16;
4635 clock.m2 = 8;
4636 } else if (adjusted_mode->clock >= 140500
4637 && adjusted_mode->clock <= 200000) {
4638 clock.p1 = 1;
4639 clock.p2 = 10;
4640 clock.n = 6;
4641 clock.m1 = 12;
4642 clock.m2 = 8;
4643 }
4644 }
4645
4646 /* FDI link */
4647 if (HAS_PCH_SPLIT(dev)) {
4648 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4649 int lane = 0, link_bw, bpp;
4650 /* CPU eDP doesn't require FDI link, so just set DP M/N
4651 according to current link config */
4652 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4653 target_clock = mode->clock;
4654 intel_edp_link_config(has_edp_encoder,
4655 &lane, &link_bw);
4656 } else {
4657 /* [e]DP over FDI requires target mode clock
4658 instead of link clock */
4659 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4660 target_clock = mode->clock;
4661 else
4662 target_clock = adjusted_mode->clock;
4663
4664 /* FDI is a binary signal running at ~2.7GHz, encoding
4665 * each output octet as 10 bits. The actual frequency
4666 * is stored as a divider into a 100MHz clock, and the
4667 * mode pixel clock is stored in units of 1KHz.
4668 * Hence the bw of each lane in terms of the mode signal
4669 * is:
4670 */
4671 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4672 }
4673
4674 /* determine panel color depth */
4675 temp = I915_READ(PIPECONF(pipe));
4676 temp &= ~PIPE_BPC_MASK;
4677 if (is_lvds) {
4678 /* the BPC will be 6 if it is 18-bit LVDS panel */
4679 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
4680 temp |= PIPE_8BPC;
4681 else
4682 temp |= PIPE_6BPC;
4683 } else if (has_edp_encoder) {
4684 switch (dev_priv->edp.bpp/3) {
4685 case 8:
4686 temp |= PIPE_8BPC;
4687 break;
4688 case 10:
4689 temp |= PIPE_10BPC;
4690 break;
4691 case 6:
4692 temp |= PIPE_6BPC;
4693 break;
4694 case 12:
4695 temp |= PIPE_12BPC;
4696 break;
4697 }
4698 } else
4699 temp |= PIPE_8BPC;
4700 I915_WRITE(PIPECONF(pipe), temp);
4701
4702 switch (temp & PIPE_BPC_MASK) {
4703 case PIPE_8BPC:
4704 bpp = 24;
4705 break;
4706 case PIPE_10BPC:
4707 bpp = 30;
4708 break;
4709 case PIPE_6BPC:
4710 bpp = 18;
4711 break;
4712 case PIPE_12BPC:
4713 bpp = 36;
4714 break;
4715 default:
4716 DRM_ERROR("unknown pipe bpc value\n");
4717 bpp = 24;
4718 }
4719
4720 if (!lane) {
4721 /*
4722 * Account for spread spectrum to avoid
4723 * oversubscribing the link. Max center spread
4724 * is 2.5%; use 5% for safety's sake.
4725 */
4726 u32 bps = target_clock * bpp * 21 / 20;
4727 lane = bps / (link_bw * 8) + 1;
4728 }
4729
4730 intel_crtc->fdi_lanes = lane;
4731
4732 if (pixel_multiplier > 1)
4733 link_bw *= pixel_multiplier;
4734 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4735 }
4736
4737 /* Ironlake: try to setup display ref clock before DPLL
4738 * enabling. This is only under driver's control after
4739 * PCH B stepping, previous chipset stepping should be
4740 * ignoring this setting.
4741 */
4742 if (HAS_PCH_SPLIT(dev)) {
4743 temp = I915_READ(PCH_DREF_CONTROL);
4744 /* Always enable nonspread source */
4745 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4746 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4747 temp &= ~DREF_SSC_SOURCE_MASK;
4748 temp |= DREF_SSC_SOURCE_ENABLE;
4749 I915_WRITE(PCH_DREF_CONTROL, temp);
4750
4751 POSTING_READ(PCH_DREF_CONTROL);
4752 udelay(200);
4753
4754 if (has_edp_encoder) {
4755 if (intel_panel_use_ssc(dev_priv)) {
4756 temp |= DREF_SSC1_ENABLE;
4757 I915_WRITE(PCH_DREF_CONTROL, temp);
4758
4759 POSTING_READ(PCH_DREF_CONTROL);
4760 udelay(200);
4761 }
4762 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4763
4764 /* Enable CPU source on CPU attached eDP */
4765 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4766 if (intel_panel_use_ssc(dev_priv))
4767 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4768 else
4769 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4770 } else {
4771 /* Enable SSC on PCH eDP if needed */
4772 if (intel_panel_use_ssc(dev_priv)) {
4773 DRM_ERROR("enabling SSC on PCH\n");
4774 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4775 }
4776 }
4777 I915_WRITE(PCH_DREF_CONTROL, temp);
4778 POSTING_READ(PCH_DREF_CONTROL);
4779 udelay(200);
4780 }
4781 }
4782
4783 if (IS_PINEVIEW(dev)) {
4784 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4785 if (has_reduced_clock)
4786 fp2 = (1 << reduced_clock.n) << 16 |
4787 reduced_clock.m1 << 8 | reduced_clock.m2;
4788 } else {
4789 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4790 if (has_reduced_clock)
4791 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4792 reduced_clock.m2;
4793 }
4794
4795 /* Enable autotuning of the PLL clock (if permissible) */
4796 if (HAS_PCH_SPLIT(dev)) {
4797 int factor = 21;
4798
4799 if (is_lvds) {
4800 if ((intel_panel_use_ssc(dev_priv) &&
4801 dev_priv->lvds_ssc_freq == 100) ||
4802 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4803 factor = 25;
4804 } else if (is_sdvo && is_tv)
4805 factor = 20;
4806
4807 if (clock.m1 < factor * clock.n)
4808 fp |= FP_CB_TUNE;
4809 }
4810
4811 dpll = 0;
4812 if (!HAS_PCH_SPLIT(dev))
4813 dpll = DPLL_VGA_MODE_DIS;
4814
4815 if (!IS_GEN2(dev)) {
4816 if (is_lvds)
4817 dpll |= DPLLB_MODE_LVDS;
4818 else
4819 dpll |= DPLLB_MODE_DAC_SERIAL;
4820 if (is_sdvo) {
4821 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4822 if (pixel_multiplier > 1) {
4823 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4824 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4825 else if (HAS_PCH_SPLIT(dev))
4826 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4827 }
4828 dpll |= DPLL_DVO_HIGH_SPEED;
4829 }
4830 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4831 dpll |= DPLL_DVO_HIGH_SPEED;
4832
4833 /* compute bitmask from p1 value */
4834 if (IS_PINEVIEW(dev))
4835 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4836 else {
4837 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4838 /* also FPA1 */
4839 if (HAS_PCH_SPLIT(dev))
4840 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4841 if (IS_G4X(dev) && has_reduced_clock)
4842 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4843 }
4844 switch (clock.p2) {
4845 case 5:
4846 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4847 break;
4848 case 7:
4849 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4850 break;
4851 case 10:
4852 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4853 break;
4854 case 14:
4855 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4856 break;
4857 }
4858 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
4859 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4860 } else {
4861 if (is_lvds) {
4862 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4863 } else {
4864 if (clock.p1 == 2)
4865 dpll |= PLL_P1_DIVIDE_BY_TWO;
4866 else
4867 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4868 if (clock.p2 == 4)
4869 dpll |= PLL_P2_DIVIDE_BY_4;
4870 }
4871 }
4872
4873 if (is_sdvo && is_tv)
4874 dpll |= PLL_REF_INPUT_TVCLKINBC;
4875 else if (is_tv)
4876 /* XXX: just matching BIOS for now */
4877 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4878 dpll |= 3;
4879 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4880 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4881 else
4882 dpll |= PLL_REF_INPUT_DREFCLK;
4883
4884 /* setup pipeconf */
4885 pipeconf = I915_READ(PIPECONF(pipe));
4886
4887 /* Set up the display plane register */
4888 dspcntr = DISPPLANE_GAMMA_ENABLE;
4889
4890 /* Ironlake's plane is forced to pipe, bit 24 is to
4891 enable color space conversion */
4892 if (!HAS_PCH_SPLIT(dev)) {
4893 if (pipe == 0)
4894 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4895 else
4896 dspcntr |= DISPPLANE_SEL_PIPE_B;
4897 }
4898
4899 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4900 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4901 * core speed.
4902 *
4903 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4904 * pipe == 0 check?
4905 */
4906 if (mode->clock >
4907 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4908 pipeconf |= PIPECONF_DOUBLE_WIDE;
4909 else
4910 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4911 }
4912
4913 if (!HAS_PCH_SPLIT(dev))
4914 dpll |= DPLL_VCO_ENABLE;
4915
4916 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4917 drm_mode_debug_printmodeline(mode);
4918
4919 /* assign to Ironlake registers */
4920 if (HAS_PCH_SPLIT(dev)) {
4921 fp_reg = PCH_FP0(pipe);
4922 dpll_reg = PCH_DPLL(pipe);
4923 } else {
4924 fp_reg = FP0(pipe);
4925 dpll_reg = DPLL(pipe);
4926 }
4927
4928 /* PCH eDP needs FDI, but CPU eDP does not */
4929 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4930 I915_WRITE(fp_reg, fp);
4931 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
4932
4933 POSTING_READ(dpll_reg);
4934 udelay(150);
4935 }
4936
4937 /* enable transcoder DPLL */
4938 if (HAS_PCH_CPT(dev)) {
4939 temp = I915_READ(PCH_DPLL_SEL);
4940 switch (pipe) {
4941 case 0:
4942 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
4943 break;
4944 case 1:
4945 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
4946 break;
4947 case 2:
4948 /* FIXME: manage transcoder PLLs? */
4949 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
4950 break;
4951 default:
4952 BUG();
4953 }
4954 I915_WRITE(PCH_DPLL_SEL, temp);
4955
4956 POSTING_READ(PCH_DPLL_SEL);
4957 udelay(150);
4958 }
4959
4960 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4961 * This is an exception to the general rule that mode_set doesn't turn
4962 * things on.
4963 */
4964 if (is_lvds) {
4965 reg = LVDS;
4966 if (HAS_PCH_SPLIT(dev))
4967 reg = PCH_LVDS;
4968
4969 temp = I915_READ(reg);
4970 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4971 if (pipe == 1) {
4972 if (HAS_PCH_CPT(dev))
4973 temp |= PORT_TRANS_B_SEL_CPT;
4974 else
4975 temp |= LVDS_PIPEB_SELECT;
4976 } else {
4977 if (HAS_PCH_CPT(dev))
4978 temp &= ~PORT_TRANS_SEL_MASK;
4979 else
4980 temp &= ~LVDS_PIPEB_SELECT;
4981 }
4982 /* set the corresponsding LVDS_BORDER bit */
4983 temp |= dev_priv->lvds_border_bits;
4984 /* Set the B0-B3 data pairs corresponding to whether we're going to
4985 * set the DPLLs for dual-channel mode or not.
4986 */
4987 if (clock.p2 == 7)
4988 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4989 else
4990 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4991
4992 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4993 * appropriately here, but we need to look more thoroughly into how
4994 * panels behave in the two modes.
4995 */
4996 /* set the dithering flag on non-PCH LVDS as needed */
4997 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4998 if (dev_priv->lvds_dither)
4999 temp |= LVDS_ENABLE_DITHER;
5000 else
5001 temp &= ~LVDS_ENABLE_DITHER;
5002 }
5003 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5004 lvds_sync |= LVDS_HSYNC_POLARITY;
5005 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5006 lvds_sync |= LVDS_VSYNC_POLARITY;
5007 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5008 != lvds_sync) {
5009 char flags[2] = "-+";
5010 DRM_INFO("Changing LVDS panel from "
5011 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5012 flags[!(temp & LVDS_HSYNC_POLARITY)],
5013 flags[!(temp & LVDS_VSYNC_POLARITY)],
5014 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5015 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5016 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5017 temp |= lvds_sync;
5018 }
5019 I915_WRITE(reg, temp);
5020 }
5021
5022 /* set the dithering flag and clear for anything other than a panel. */
5023 if (HAS_PCH_SPLIT(dev)) {
5024 pipeconf &= ~PIPECONF_DITHER_EN;
5025 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5026 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
5027 pipeconf |= PIPECONF_DITHER_EN;
5028 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
5029 }
5030 }
5031
5032 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5033 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5034 } else if (HAS_PCH_SPLIT(dev)) {
5035 /* For non-DP output, clear any trans DP clock recovery setting.*/
5036 I915_WRITE(TRANSDATA_M1(pipe), 0);
5037 I915_WRITE(TRANSDATA_N1(pipe), 0);
5038 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5039 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5040 }
5041
5042 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5043 I915_WRITE(dpll_reg, dpll);
5044
5045 /* Wait for the clocks to stabilize. */
5046 POSTING_READ(dpll_reg);
5047 udelay(150);
5048
5049 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
5050 temp = 0;
5051 if (is_sdvo) {
5052 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5053 if (temp > 1)
5054 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5055 else
5056 temp = 0;
5057 }
5058 I915_WRITE(DPLL_MD(pipe), temp);
5059 } else {
5060 /* The pixel multiplier can only be updated once the
5061 * DPLL is enabled and the clocks are stable.
5062 *
5063 * So write it again.
5064 */
5065 I915_WRITE(dpll_reg, dpll);
5066 }
5067 }
5068
5069 intel_crtc->lowfreq_avail = false;
5070 if (is_lvds && has_reduced_clock && i915_powersave) {
5071 I915_WRITE(fp_reg + 4, fp2);
5072 intel_crtc->lowfreq_avail = true;
5073 if (HAS_PIPE_CXSR(dev)) {
5074 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5075 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5076 }
5077 } else {
5078 I915_WRITE(fp_reg + 4, fp);
5079 if (HAS_PIPE_CXSR(dev)) {
5080 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5081 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5082 }
5083 }
5084
5085 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5086 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5087 /* the chip adds 2 halflines automatically */
5088 adjusted_mode->crtc_vdisplay -= 1;
5089 adjusted_mode->crtc_vtotal -= 1;
5090 adjusted_mode->crtc_vblank_start -= 1;
5091 adjusted_mode->crtc_vblank_end -= 1;
5092 adjusted_mode->crtc_vsync_end -= 1;
5093 adjusted_mode->crtc_vsync_start -= 1;
5094 } else
5095 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5096
5097 I915_WRITE(HTOTAL(pipe),
5098 (adjusted_mode->crtc_hdisplay - 1) |
5099 ((adjusted_mode->crtc_htotal - 1) << 16));
5100 I915_WRITE(HBLANK(pipe),
5101 (adjusted_mode->crtc_hblank_start - 1) |
5102 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5103 I915_WRITE(HSYNC(pipe),
5104 (adjusted_mode->crtc_hsync_start - 1) |
5105 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5106
5107 I915_WRITE(VTOTAL(pipe),
5108 (adjusted_mode->crtc_vdisplay - 1) |
5109 ((adjusted_mode->crtc_vtotal - 1) << 16));
5110 I915_WRITE(VBLANK(pipe),
5111 (adjusted_mode->crtc_vblank_start - 1) |
5112 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5113 I915_WRITE(VSYNC(pipe),
5114 (adjusted_mode->crtc_vsync_start - 1) |
5115 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5116
5117 /* pipesrc and dspsize control the size that is scaled from,
5118 * which should always be the user's requested size.
5119 */
5120 if (!HAS_PCH_SPLIT(dev)) {
5121 I915_WRITE(DSPSIZE(plane),
5122 ((mode->vdisplay - 1) << 16) |
5123 (mode->hdisplay - 1));
5124 I915_WRITE(DSPPOS(plane), 0);
5125 }
5126 I915_WRITE(PIPESRC(pipe),
5127 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5128
5129 if (HAS_PCH_SPLIT(dev)) {
5130 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5131 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5132 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5133 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5134
5135 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5136 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5137 }
5138 }
5139
5140 I915_WRITE(PIPECONF(pipe), pipeconf);
5141 POSTING_READ(PIPECONF(pipe));
5142 if (!HAS_PCH_SPLIT(dev))
5143 intel_enable_pipe(dev_priv, pipe, false);
5144
5145 intel_wait_for_vblank(dev, pipe);
5146
5147 if (IS_GEN5(dev)) {
5148 /* enable address swizzle for tiling buffer */
5149 temp = I915_READ(DISP_ARB_CTL);
5150 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5151 }
5152
5153 I915_WRITE(DSPCNTR(plane), dspcntr);
5154 POSTING_READ(DSPCNTR(plane));
5155 if (!HAS_PCH_SPLIT(dev))
5156 intel_enable_plane(dev_priv, plane, pipe);
5157
5158 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5159
5160 intel_update_watermarks(dev);
5161
5162 drm_vblank_post_modeset(dev, pipe);
5163
5164 return ret;
5165 }
5166
5167 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5168 void intel_crtc_load_lut(struct drm_crtc *crtc)
5169 {
5170 struct drm_device *dev = crtc->dev;
5171 struct drm_i915_private *dev_priv = dev->dev_private;
5172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5173 int palreg = PALETTE(intel_crtc->pipe);
5174 int i;
5175
5176 /* The clocks have to be on to load the palette. */
5177 if (!crtc->enabled)
5178 return;
5179
5180 /* use legacy palette for Ironlake */
5181 if (HAS_PCH_SPLIT(dev))
5182 palreg = LGC_PALETTE(intel_crtc->pipe);
5183
5184 for (i = 0; i < 256; i++) {
5185 I915_WRITE(palreg + 4 * i,
5186 (intel_crtc->lut_r[i] << 16) |
5187 (intel_crtc->lut_g[i] << 8) |
5188 intel_crtc->lut_b[i]);
5189 }
5190 }
5191
5192 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5193 {
5194 struct drm_device *dev = crtc->dev;
5195 struct drm_i915_private *dev_priv = dev->dev_private;
5196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5197 bool visible = base != 0;
5198 u32 cntl;
5199
5200 if (intel_crtc->cursor_visible == visible)
5201 return;
5202
5203 cntl = I915_READ(_CURACNTR);
5204 if (visible) {
5205 /* On these chipsets we can only modify the base whilst
5206 * the cursor is disabled.
5207 */
5208 I915_WRITE(_CURABASE, base);
5209
5210 cntl &= ~(CURSOR_FORMAT_MASK);
5211 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5212 cntl |= CURSOR_ENABLE |
5213 CURSOR_GAMMA_ENABLE |
5214 CURSOR_FORMAT_ARGB;
5215 } else
5216 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5217 I915_WRITE(_CURACNTR, cntl);
5218
5219 intel_crtc->cursor_visible = visible;
5220 }
5221
5222 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5223 {
5224 struct drm_device *dev = crtc->dev;
5225 struct drm_i915_private *dev_priv = dev->dev_private;
5226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5227 int pipe = intel_crtc->pipe;
5228 bool visible = base != 0;
5229
5230 if (intel_crtc->cursor_visible != visible) {
5231 uint32_t cntl = I915_READ(CURCNTR(pipe));
5232 if (base) {
5233 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5234 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5235 cntl |= pipe << 28; /* Connect to correct pipe */
5236 } else {
5237 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5238 cntl |= CURSOR_MODE_DISABLE;
5239 }
5240 I915_WRITE(CURCNTR(pipe), cntl);
5241
5242 intel_crtc->cursor_visible = visible;
5243 }
5244 /* and commit changes on next vblank */
5245 I915_WRITE(CURBASE(pipe), base);
5246 }
5247
5248 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5249 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5250 bool on)
5251 {
5252 struct drm_device *dev = crtc->dev;
5253 struct drm_i915_private *dev_priv = dev->dev_private;
5254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5255 int pipe = intel_crtc->pipe;
5256 int x = intel_crtc->cursor_x;
5257 int y = intel_crtc->cursor_y;
5258 u32 base, pos;
5259 bool visible;
5260
5261 pos = 0;
5262
5263 if (on && crtc->enabled && crtc->fb) {
5264 base = intel_crtc->cursor_addr;
5265 if (x > (int) crtc->fb->width)
5266 base = 0;
5267
5268 if (y > (int) crtc->fb->height)
5269 base = 0;
5270 } else
5271 base = 0;
5272
5273 if (x < 0) {
5274 if (x + intel_crtc->cursor_width < 0)
5275 base = 0;
5276
5277 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5278 x = -x;
5279 }
5280 pos |= x << CURSOR_X_SHIFT;
5281
5282 if (y < 0) {
5283 if (y + intel_crtc->cursor_height < 0)
5284 base = 0;
5285
5286 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5287 y = -y;
5288 }
5289 pos |= y << CURSOR_Y_SHIFT;
5290
5291 visible = base != 0;
5292 if (!visible && !intel_crtc->cursor_visible)
5293 return;
5294
5295 I915_WRITE(CURPOS(pipe), pos);
5296 if (IS_845G(dev) || IS_I865G(dev))
5297 i845_update_cursor(crtc, base);
5298 else
5299 i9xx_update_cursor(crtc, base);
5300
5301 if (visible)
5302 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5303 }
5304
5305 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5306 struct drm_file *file,
5307 uint32_t handle,
5308 uint32_t width, uint32_t height)
5309 {
5310 struct drm_device *dev = crtc->dev;
5311 struct drm_i915_private *dev_priv = dev->dev_private;
5312 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5313 struct drm_i915_gem_object *obj;
5314 uint32_t addr;
5315 int ret;
5316
5317 DRM_DEBUG_KMS("\n");
5318
5319 /* if we want to turn off the cursor ignore width and height */
5320 if (!handle) {
5321 DRM_DEBUG_KMS("cursor off\n");
5322 addr = 0;
5323 obj = NULL;
5324 mutex_lock(&dev->struct_mutex);
5325 goto finish;
5326 }
5327
5328 /* Currently we only support 64x64 cursors */
5329 if (width != 64 || height != 64) {
5330 DRM_ERROR("we currently only support 64x64 cursors\n");
5331 return -EINVAL;
5332 }
5333
5334 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5335 if (&obj->base == NULL)
5336 return -ENOENT;
5337
5338 if (obj->base.size < width * height * 4) {
5339 DRM_ERROR("buffer is to small\n");
5340 ret = -ENOMEM;
5341 goto fail;
5342 }
5343
5344 /* we only need to pin inside GTT if cursor is non-phy */
5345 mutex_lock(&dev->struct_mutex);
5346 if (!dev_priv->info->cursor_needs_physical) {
5347 if (obj->tiling_mode) {
5348 DRM_ERROR("cursor cannot be tiled\n");
5349 ret = -EINVAL;
5350 goto fail_locked;
5351 }
5352
5353 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
5354 if (ret) {
5355 DRM_ERROR("failed to pin cursor bo\n");
5356 goto fail_locked;
5357 }
5358
5359 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
5360 if (ret) {
5361 DRM_ERROR("failed to move cursor bo into the GTT\n");
5362 goto fail_unpin;
5363 }
5364
5365 ret = i915_gem_object_put_fence(obj);
5366 if (ret) {
5367 DRM_ERROR("failed to move cursor bo into the GTT\n");
5368 goto fail_unpin;
5369 }
5370
5371 addr = obj->gtt_offset;
5372 } else {
5373 int align = IS_I830(dev) ? 16 * 1024 : 256;
5374 ret = i915_gem_attach_phys_object(dev, obj,
5375 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5376 align);
5377 if (ret) {
5378 DRM_ERROR("failed to attach phys object\n");
5379 goto fail_locked;
5380 }
5381 addr = obj->phys_obj->handle->busaddr;
5382 }
5383
5384 if (IS_GEN2(dev))
5385 I915_WRITE(CURSIZE, (height << 12) | width);
5386
5387 finish:
5388 if (intel_crtc->cursor_bo) {
5389 if (dev_priv->info->cursor_needs_physical) {
5390 if (intel_crtc->cursor_bo != obj)
5391 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5392 } else
5393 i915_gem_object_unpin(intel_crtc->cursor_bo);
5394 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5395 }
5396
5397 mutex_unlock(&dev->struct_mutex);
5398
5399 intel_crtc->cursor_addr = addr;
5400 intel_crtc->cursor_bo = obj;
5401 intel_crtc->cursor_width = width;
5402 intel_crtc->cursor_height = height;
5403
5404 intel_crtc_update_cursor(crtc, true);
5405
5406 return 0;
5407 fail_unpin:
5408 i915_gem_object_unpin(obj);
5409 fail_locked:
5410 mutex_unlock(&dev->struct_mutex);
5411 fail:
5412 drm_gem_object_unreference_unlocked(&obj->base);
5413 return ret;
5414 }
5415
5416 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5417 {
5418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5419
5420 intel_crtc->cursor_x = x;
5421 intel_crtc->cursor_y = y;
5422
5423 intel_crtc_update_cursor(crtc, true);
5424
5425 return 0;
5426 }
5427
5428 /** Sets the color ramps on behalf of RandR */
5429 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5430 u16 blue, int regno)
5431 {
5432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5433
5434 intel_crtc->lut_r[regno] = red >> 8;
5435 intel_crtc->lut_g[regno] = green >> 8;
5436 intel_crtc->lut_b[regno] = blue >> 8;
5437 }
5438
5439 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5440 u16 *blue, int regno)
5441 {
5442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5443
5444 *red = intel_crtc->lut_r[regno] << 8;
5445 *green = intel_crtc->lut_g[regno] << 8;
5446 *blue = intel_crtc->lut_b[regno] << 8;
5447 }
5448
5449 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5450 u16 *blue, uint32_t start, uint32_t size)
5451 {
5452 int end = (start + size > 256) ? 256 : start + size, i;
5453 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5454
5455 for (i = start; i < end; i++) {
5456 intel_crtc->lut_r[i] = red[i] >> 8;
5457 intel_crtc->lut_g[i] = green[i] >> 8;
5458 intel_crtc->lut_b[i] = blue[i] >> 8;
5459 }
5460
5461 intel_crtc_load_lut(crtc);
5462 }
5463
5464 /**
5465 * Get a pipe with a simple mode set on it for doing load-based monitor
5466 * detection.
5467 *
5468 * It will be up to the load-detect code to adjust the pipe as appropriate for
5469 * its requirements. The pipe will be connected to no other encoders.
5470 *
5471 * Currently this code will only succeed if there is a pipe with no encoders
5472 * configured for it. In the future, it could choose to temporarily disable
5473 * some outputs to free up a pipe for its use.
5474 *
5475 * \return crtc, or NULL if no pipes are available.
5476 */
5477
5478 /* VESA 640x480x72Hz mode to set on the pipe */
5479 static struct drm_display_mode load_detect_mode = {
5480 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5481 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5482 };
5483
5484 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5485 struct drm_connector *connector,
5486 struct drm_display_mode *mode,
5487 int *dpms_mode)
5488 {
5489 struct intel_crtc *intel_crtc;
5490 struct drm_crtc *possible_crtc;
5491 struct drm_crtc *supported_crtc =NULL;
5492 struct drm_encoder *encoder = &intel_encoder->base;
5493 struct drm_crtc *crtc = NULL;
5494 struct drm_device *dev = encoder->dev;
5495 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5496 struct drm_crtc_helper_funcs *crtc_funcs;
5497 int i = -1;
5498
5499 /*
5500 * Algorithm gets a little messy:
5501 * - if the connector already has an assigned crtc, use it (but make
5502 * sure it's on first)
5503 * - try to find the first unused crtc that can drive this connector,
5504 * and use that if we find one
5505 * - if there are no unused crtcs available, try to use the first
5506 * one we found that supports the connector
5507 */
5508
5509 /* See if we already have a CRTC for this connector */
5510 if (encoder->crtc) {
5511 crtc = encoder->crtc;
5512 /* Make sure the crtc and connector are running */
5513 intel_crtc = to_intel_crtc(crtc);
5514 *dpms_mode = intel_crtc->dpms_mode;
5515 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5516 crtc_funcs = crtc->helper_private;
5517 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5518 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5519 }
5520 return crtc;
5521 }
5522
5523 /* Find an unused one (if possible) */
5524 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5525 i++;
5526 if (!(encoder->possible_crtcs & (1 << i)))
5527 continue;
5528 if (!possible_crtc->enabled) {
5529 crtc = possible_crtc;
5530 break;
5531 }
5532 if (!supported_crtc)
5533 supported_crtc = possible_crtc;
5534 }
5535
5536 /*
5537 * If we didn't find an unused CRTC, don't use any.
5538 */
5539 if (!crtc) {
5540 return NULL;
5541 }
5542
5543 encoder->crtc = crtc;
5544 connector->encoder = encoder;
5545 intel_encoder->load_detect_temp = true;
5546
5547 intel_crtc = to_intel_crtc(crtc);
5548 *dpms_mode = intel_crtc->dpms_mode;
5549
5550 if (!crtc->enabled) {
5551 if (!mode)
5552 mode = &load_detect_mode;
5553 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
5554 } else {
5555 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5556 crtc_funcs = crtc->helper_private;
5557 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5558 }
5559
5560 /* Add this connector to the crtc */
5561 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
5562 encoder_funcs->commit(encoder);
5563 }
5564 /* let the connector get through one full cycle before testing */
5565 intel_wait_for_vblank(dev, intel_crtc->pipe);
5566
5567 return crtc;
5568 }
5569
5570 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5571 struct drm_connector *connector, int dpms_mode)
5572 {
5573 struct drm_encoder *encoder = &intel_encoder->base;
5574 struct drm_device *dev = encoder->dev;
5575 struct drm_crtc *crtc = encoder->crtc;
5576 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5577 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5578
5579 if (intel_encoder->load_detect_temp) {
5580 encoder->crtc = NULL;
5581 connector->encoder = NULL;
5582 intel_encoder->load_detect_temp = false;
5583 crtc->enabled = drm_helper_crtc_in_use(crtc);
5584 drm_helper_disable_unused_functions(dev);
5585 }
5586
5587 /* Switch crtc and encoder back off if necessary */
5588 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
5589 if (encoder->crtc == crtc)
5590 encoder_funcs->dpms(encoder, dpms_mode);
5591 crtc_funcs->dpms(crtc, dpms_mode);
5592 }
5593 }
5594
5595 /* Returns the clock of the currently programmed mode of the given pipe. */
5596 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5597 {
5598 struct drm_i915_private *dev_priv = dev->dev_private;
5599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5600 int pipe = intel_crtc->pipe;
5601 u32 dpll = I915_READ(DPLL(pipe));
5602 u32 fp;
5603 intel_clock_t clock;
5604
5605 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5606 fp = FP0(pipe);
5607 else
5608 fp = FP1(pipe);
5609
5610 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5611 if (IS_PINEVIEW(dev)) {
5612 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5613 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5614 } else {
5615 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5616 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5617 }
5618
5619 if (!IS_GEN2(dev)) {
5620 if (IS_PINEVIEW(dev))
5621 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5622 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5623 else
5624 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5625 DPLL_FPA01_P1_POST_DIV_SHIFT);
5626
5627 switch (dpll & DPLL_MODE_MASK) {
5628 case DPLLB_MODE_DAC_SERIAL:
5629 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5630 5 : 10;
5631 break;
5632 case DPLLB_MODE_LVDS:
5633 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5634 7 : 14;
5635 break;
5636 default:
5637 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5638 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5639 return 0;
5640 }
5641
5642 /* XXX: Handle the 100Mhz refclk */
5643 intel_clock(dev, 96000, &clock);
5644 } else {
5645 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5646
5647 if (is_lvds) {
5648 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5649 DPLL_FPA01_P1_POST_DIV_SHIFT);
5650 clock.p2 = 14;
5651
5652 if ((dpll & PLL_REF_INPUT_MASK) ==
5653 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5654 /* XXX: might not be 66MHz */
5655 intel_clock(dev, 66000, &clock);
5656 } else
5657 intel_clock(dev, 48000, &clock);
5658 } else {
5659 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5660 clock.p1 = 2;
5661 else {
5662 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5663 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5664 }
5665 if (dpll & PLL_P2_DIVIDE_BY_4)
5666 clock.p2 = 4;
5667 else
5668 clock.p2 = 2;
5669
5670 intel_clock(dev, 48000, &clock);
5671 }
5672 }
5673
5674 /* XXX: It would be nice to validate the clocks, but we can't reuse
5675 * i830PllIsValid() because it relies on the xf86_config connector
5676 * configuration being accurate, which it isn't necessarily.
5677 */
5678
5679 return clock.dot;
5680 }
5681
5682 /** Returns the currently programmed mode of the given pipe. */
5683 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5684 struct drm_crtc *crtc)
5685 {
5686 struct drm_i915_private *dev_priv = dev->dev_private;
5687 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5688 int pipe = intel_crtc->pipe;
5689 struct drm_display_mode *mode;
5690 int htot = I915_READ(HTOTAL(pipe));
5691 int hsync = I915_READ(HSYNC(pipe));
5692 int vtot = I915_READ(VTOTAL(pipe));
5693 int vsync = I915_READ(VSYNC(pipe));
5694
5695 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5696 if (!mode)
5697 return NULL;
5698
5699 mode->clock = intel_crtc_clock_get(dev, crtc);
5700 mode->hdisplay = (htot & 0xffff) + 1;
5701 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5702 mode->hsync_start = (hsync & 0xffff) + 1;
5703 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5704 mode->vdisplay = (vtot & 0xffff) + 1;
5705 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5706 mode->vsync_start = (vsync & 0xffff) + 1;
5707 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5708
5709 drm_mode_set_name(mode);
5710 drm_mode_set_crtcinfo(mode, 0);
5711
5712 return mode;
5713 }
5714
5715 #define GPU_IDLE_TIMEOUT 500 /* ms */
5716
5717 /* When this timer fires, we've been idle for awhile */
5718 static void intel_gpu_idle_timer(unsigned long arg)
5719 {
5720 struct drm_device *dev = (struct drm_device *)arg;
5721 drm_i915_private_t *dev_priv = dev->dev_private;
5722
5723 if (!list_empty(&dev_priv->mm.active_list)) {
5724 /* Still processing requests, so just re-arm the timer. */
5725 mod_timer(&dev_priv->idle_timer, jiffies +
5726 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5727 return;
5728 }
5729
5730 dev_priv->busy = false;
5731 queue_work(dev_priv->wq, &dev_priv->idle_work);
5732 }
5733
5734 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5735
5736 static void intel_crtc_idle_timer(unsigned long arg)
5737 {
5738 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5739 struct drm_crtc *crtc = &intel_crtc->base;
5740 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5741 struct intel_framebuffer *intel_fb;
5742
5743 intel_fb = to_intel_framebuffer(crtc->fb);
5744 if (intel_fb && intel_fb->obj->active) {
5745 /* The framebuffer is still being accessed by the GPU. */
5746 mod_timer(&intel_crtc->idle_timer, jiffies +
5747 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5748 return;
5749 }
5750
5751 intel_crtc->busy = false;
5752 queue_work(dev_priv->wq, &dev_priv->idle_work);
5753 }
5754
5755 static void intel_increase_pllclock(struct drm_crtc *crtc)
5756 {
5757 struct drm_device *dev = crtc->dev;
5758 drm_i915_private_t *dev_priv = dev->dev_private;
5759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5760 int pipe = intel_crtc->pipe;
5761 int dpll_reg = DPLL(pipe);
5762 int dpll;
5763
5764 if (HAS_PCH_SPLIT(dev))
5765 return;
5766
5767 if (!dev_priv->lvds_downclock_avail)
5768 return;
5769
5770 dpll = I915_READ(dpll_reg);
5771 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5772 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5773
5774 /* Unlock panel regs */
5775 I915_WRITE(PP_CONTROL,
5776 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
5777
5778 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5779 I915_WRITE(dpll_reg, dpll);
5780 POSTING_READ(dpll_reg);
5781 intel_wait_for_vblank(dev, pipe);
5782
5783 dpll = I915_READ(dpll_reg);
5784 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5785 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5786
5787 /* ...and lock them again */
5788 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5789 }
5790
5791 /* Schedule downclock */
5792 mod_timer(&intel_crtc->idle_timer, jiffies +
5793 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5794 }
5795
5796 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5797 {
5798 struct drm_device *dev = crtc->dev;
5799 drm_i915_private_t *dev_priv = dev->dev_private;
5800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5801 int pipe = intel_crtc->pipe;
5802 int dpll_reg = DPLL(pipe);
5803 int dpll = I915_READ(dpll_reg);
5804
5805 if (HAS_PCH_SPLIT(dev))
5806 return;
5807
5808 if (!dev_priv->lvds_downclock_avail)
5809 return;
5810
5811 /*
5812 * Since this is called by a timer, we should never get here in
5813 * the manual case.
5814 */
5815 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5816 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5817
5818 /* Unlock panel regs */
5819 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
5820 PANEL_UNLOCK_REGS);
5821
5822 dpll |= DISPLAY_RATE_SELECT_FPA1;
5823 I915_WRITE(dpll_reg, dpll);
5824 dpll = I915_READ(dpll_reg);
5825 intel_wait_for_vblank(dev, pipe);
5826 dpll = I915_READ(dpll_reg);
5827 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5828 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5829
5830 /* ...and lock them again */
5831 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5832 }
5833
5834 }
5835
5836 /**
5837 * intel_idle_update - adjust clocks for idleness
5838 * @work: work struct
5839 *
5840 * Either the GPU or display (or both) went idle. Check the busy status
5841 * here and adjust the CRTC and GPU clocks as necessary.
5842 */
5843 static void intel_idle_update(struct work_struct *work)
5844 {
5845 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5846 idle_work);
5847 struct drm_device *dev = dev_priv->dev;
5848 struct drm_crtc *crtc;
5849 struct intel_crtc *intel_crtc;
5850
5851 if (!i915_powersave)
5852 return;
5853
5854 mutex_lock(&dev->struct_mutex);
5855
5856 i915_update_gfx_val(dev_priv);
5857
5858 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5859 /* Skip inactive CRTCs */
5860 if (!crtc->fb)
5861 continue;
5862
5863 intel_crtc = to_intel_crtc(crtc);
5864 if (!intel_crtc->busy)
5865 intel_decrease_pllclock(crtc);
5866 }
5867
5868
5869 mutex_unlock(&dev->struct_mutex);
5870 }
5871
5872 /**
5873 * intel_mark_busy - mark the GPU and possibly the display busy
5874 * @dev: drm device
5875 * @obj: object we're operating on
5876 *
5877 * Callers can use this function to indicate that the GPU is busy processing
5878 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
5879 * buffer), we'll also mark the display as busy, so we know to increase its
5880 * clock frequency.
5881 */
5882 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5883 {
5884 drm_i915_private_t *dev_priv = dev->dev_private;
5885 struct drm_crtc *crtc = NULL;
5886 struct intel_framebuffer *intel_fb;
5887 struct intel_crtc *intel_crtc;
5888
5889 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5890 return;
5891
5892 if (!dev_priv->busy)
5893 dev_priv->busy = true;
5894 else
5895 mod_timer(&dev_priv->idle_timer, jiffies +
5896 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5897
5898 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5899 if (!crtc->fb)
5900 continue;
5901
5902 intel_crtc = to_intel_crtc(crtc);
5903 intel_fb = to_intel_framebuffer(crtc->fb);
5904 if (intel_fb->obj == obj) {
5905 if (!intel_crtc->busy) {
5906 /* Non-busy -> busy, upclock */
5907 intel_increase_pllclock(crtc);
5908 intel_crtc->busy = true;
5909 } else {
5910 /* Busy -> busy, put off timer */
5911 mod_timer(&intel_crtc->idle_timer, jiffies +
5912 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5913 }
5914 }
5915 }
5916 }
5917
5918 static void intel_crtc_destroy(struct drm_crtc *crtc)
5919 {
5920 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5921 struct drm_device *dev = crtc->dev;
5922 struct intel_unpin_work *work;
5923 unsigned long flags;
5924
5925 spin_lock_irqsave(&dev->event_lock, flags);
5926 work = intel_crtc->unpin_work;
5927 intel_crtc->unpin_work = NULL;
5928 spin_unlock_irqrestore(&dev->event_lock, flags);
5929
5930 if (work) {
5931 cancel_work_sync(&work->work);
5932 kfree(work);
5933 }
5934
5935 drm_crtc_cleanup(crtc);
5936
5937 kfree(intel_crtc);
5938 }
5939
5940 static void intel_unpin_work_fn(struct work_struct *__work)
5941 {
5942 struct intel_unpin_work *work =
5943 container_of(__work, struct intel_unpin_work, work);
5944
5945 mutex_lock(&work->dev->struct_mutex);
5946 i915_gem_object_unpin(work->old_fb_obj);
5947 drm_gem_object_unreference(&work->pending_flip_obj->base);
5948 drm_gem_object_unreference(&work->old_fb_obj->base);
5949
5950 mutex_unlock(&work->dev->struct_mutex);
5951 kfree(work);
5952 }
5953
5954 static void do_intel_finish_page_flip(struct drm_device *dev,
5955 struct drm_crtc *crtc)
5956 {
5957 drm_i915_private_t *dev_priv = dev->dev_private;
5958 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5959 struct intel_unpin_work *work;
5960 struct drm_i915_gem_object *obj;
5961 struct drm_pending_vblank_event *e;
5962 struct timeval tnow, tvbl;
5963 unsigned long flags;
5964
5965 /* Ignore early vblank irqs */
5966 if (intel_crtc == NULL)
5967 return;
5968
5969 do_gettimeofday(&tnow);
5970
5971 spin_lock_irqsave(&dev->event_lock, flags);
5972 work = intel_crtc->unpin_work;
5973 if (work == NULL || !work->pending) {
5974 spin_unlock_irqrestore(&dev->event_lock, flags);
5975 return;
5976 }
5977
5978 intel_crtc->unpin_work = NULL;
5979
5980 if (work->event) {
5981 e = work->event;
5982 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5983
5984 /* Called before vblank count and timestamps have
5985 * been updated for the vblank interval of flip
5986 * completion? Need to increment vblank count and
5987 * add one videorefresh duration to returned timestamp
5988 * to account for this. We assume this happened if we
5989 * get called over 0.9 frame durations after the last
5990 * timestamped vblank.
5991 *
5992 * This calculation can not be used with vrefresh rates
5993 * below 5Hz (10Hz to be on the safe side) without
5994 * promoting to 64 integers.
5995 */
5996 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5997 9 * crtc->framedur_ns) {
5998 e->event.sequence++;
5999 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6000 crtc->framedur_ns);
6001 }
6002
6003 e->event.tv_sec = tvbl.tv_sec;
6004 e->event.tv_usec = tvbl.tv_usec;
6005
6006 list_add_tail(&e->base.link,
6007 &e->base.file_priv->event_list);
6008 wake_up_interruptible(&e->base.file_priv->event_wait);
6009 }
6010
6011 drm_vblank_put(dev, intel_crtc->pipe);
6012
6013 spin_unlock_irqrestore(&dev->event_lock, flags);
6014
6015 obj = work->old_fb_obj;
6016
6017 atomic_clear_mask(1 << intel_crtc->plane,
6018 &obj->pending_flip.counter);
6019 if (atomic_read(&obj->pending_flip) == 0)
6020 wake_up(&dev_priv->pending_flip_queue);
6021
6022 schedule_work(&work->work);
6023
6024 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6025 }
6026
6027 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6028 {
6029 drm_i915_private_t *dev_priv = dev->dev_private;
6030 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6031
6032 do_intel_finish_page_flip(dev, crtc);
6033 }
6034
6035 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6036 {
6037 drm_i915_private_t *dev_priv = dev->dev_private;
6038 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6039
6040 do_intel_finish_page_flip(dev, crtc);
6041 }
6042
6043 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6044 {
6045 drm_i915_private_t *dev_priv = dev->dev_private;
6046 struct intel_crtc *intel_crtc =
6047 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6048 unsigned long flags;
6049
6050 spin_lock_irqsave(&dev->event_lock, flags);
6051 if (intel_crtc->unpin_work) {
6052 if ((++intel_crtc->unpin_work->pending) > 1)
6053 DRM_ERROR("Prepared flip multiple times\n");
6054 } else {
6055 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6056 }
6057 spin_unlock_irqrestore(&dev->event_lock, flags);
6058 }
6059
6060 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6061 struct drm_framebuffer *fb,
6062 struct drm_pending_vblank_event *event)
6063 {
6064 struct drm_device *dev = crtc->dev;
6065 struct drm_i915_private *dev_priv = dev->dev_private;
6066 struct intel_framebuffer *intel_fb;
6067 struct drm_i915_gem_object *obj;
6068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6069 struct intel_unpin_work *work;
6070 unsigned long flags, offset;
6071 int pipe = intel_crtc->pipe;
6072 u32 pf, pipesrc;
6073 int ret;
6074
6075 work = kzalloc(sizeof *work, GFP_KERNEL);
6076 if (work == NULL)
6077 return -ENOMEM;
6078
6079 work->event = event;
6080 work->dev = crtc->dev;
6081 intel_fb = to_intel_framebuffer(crtc->fb);
6082 work->old_fb_obj = intel_fb->obj;
6083 INIT_WORK(&work->work, intel_unpin_work_fn);
6084
6085 /* We borrow the event spin lock for protecting unpin_work */
6086 spin_lock_irqsave(&dev->event_lock, flags);
6087 if (intel_crtc->unpin_work) {
6088 spin_unlock_irqrestore(&dev->event_lock, flags);
6089 kfree(work);
6090
6091 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6092 return -EBUSY;
6093 }
6094 intel_crtc->unpin_work = work;
6095 spin_unlock_irqrestore(&dev->event_lock, flags);
6096
6097 intel_fb = to_intel_framebuffer(fb);
6098 obj = intel_fb->obj;
6099
6100 mutex_lock(&dev->struct_mutex);
6101 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6102 if (ret)
6103 goto cleanup_work;
6104
6105 /* Reference the objects for the scheduled work. */
6106 drm_gem_object_reference(&work->old_fb_obj->base);
6107 drm_gem_object_reference(&obj->base);
6108
6109 crtc->fb = fb;
6110
6111 ret = drm_vblank_get(dev, intel_crtc->pipe);
6112 if (ret)
6113 goto cleanup_objs;
6114
6115 if (IS_GEN3(dev) || IS_GEN2(dev)) {
6116 u32 flip_mask;
6117
6118 /* Can't queue multiple flips, so wait for the previous
6119 * one to finish before executing the next.
6120 */
6121 ret = BEGIN_LP_RING(2);
6122 if (ret)
6123 goto cleanup_objs;
6124
6125 if (intel_crtc->plane)
6126 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6127 else
6128 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6129 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6130 OUT_RING(MI_NOOP);
6131 ADVANCE_LP_RING();
6132 }
6133
6134 work->pending_flip_obj = obj;
6135
6136 work->enable_stall_check = true;
6137
6138 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6139 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6140
6141 ret = BEGIN_LP_RING(4);
6142 if (ret)
6143 goto cleanup_objs;
6144
6145 /* Block clients from rendering to the new back buffer until
6146 * the flip occurs and the object is no longer visible.
6147 */
6148 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6149
6150 switch (INTEL_INFO(dev)->gen) {
6151 case 2:
6152 OUT_RING(MI_DISPLAY_FLIP |
6153 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6154 OUT_RING(fb->pitch);
6155 OUT_RING(obj->gtt_offset + offset);
6156 OUT_RING(MI_NOOP);
6157 break;
6158
6159 case 3:
6160 OUT_RING(MI_DISPLAY_FLIP_I915 |
6161 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6162 OUT_RING(fb->pitch);
6163 OUT_RING(obj->gtt_offset + offset);
6164 OUT_RING(MI_NOOP);
6165 break;
6166
6167 case 4:
6168 case 5:
6169 /* i965+ uses the linear or tiled offsets from the
6170 * Display Registers (which do not change across a page-flip)
6171 * so we need only reprogram the base address.
6172 */
6173 OUT_RING(MI_DISPLAY_FLIP |
6174 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6175 OUT_RING(fb->pitch);
6176 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6177
6178 /* XXX Enabling the panel-fitter across page-flip is so far
6179 * untested on non-native modes, so ignore it for now.
6180 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6181 */
6182 pf = 0;
6183 pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
6184 OUT_RING(pf | pipesrc);
6185 break;
6186
6187 case 6:
6188 OUT_RING(MI_DISPLAY_FLIP |
6189 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6190 OUT_RING(fb->pitch | obj->tiling_mode);
6191 OUT_RING(obj->gtt_offset);
6192
6193 pf = I915_READ(PF_CTL(pipe)) & PF_ENABLE;
6194 pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
6195 OUT_RING(pf | pipesrc);
6196 break;
6197 }
6198 ADVANCE_LP_RING();
6199
6200 mutex_unlock(&dev->struct_mutex);
6201
6202 trace_i915_flip_request(intel_crtc->plane, obj);
6203
6204 return 0;
6205
6206 cleanup_objs:
6207 drm_gem_object_unreference(&work->old_fb_obj->base);
6208 drm_gem_object_unreference(&obj->base);
6209 cleanup_work:
6210 mutex_unlock(&dev->struct_mutex);
6211
6212 spin_lock_irqsave(&dev->event_lock, flags);
6213 intel_crtc->unpin_work = NULL;
6214 spin_unlock_irqrestore(&dev->event_lock, flags);
6215
6216 kfree(work);
6217
6218 return ret;
6219 }
6220
6221 static void intel_crtc_reset(struct drm_crtc *crtc)
6222 {
6223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6224
6225 /* Reset flags back to the 'unknown' status so that they
6226 * will be correctly set on the initial modeset.
6227 */
6228 intel_crtc->dpms_mode = -1;
6229 }
6230
6231 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6232 .dpms = intel_crtc_dpms,
6233 .mode_fixup = intel_crtc_mode_fixup,
6234 .mode_set = intel_crtc_mode_set,
6235 .mode_set_base = intel_pipe_set_base,
6236 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6237 .load_lut = intel_crtc_load_lut,
6238 .disable = intel_crtc_disable,
6239 };
6240
6241 static const struct drm_crtc_funcs intel_crtc_funcs = {
6242 .reset = intel_crtc_reset,
6243 .cursor_set = intel_crtc_cursor_set,
6244 .cursor_move = intel_crtc_cursor_move,
6245 .gamma_set = intel_crtc_gamma_set,
6246 .set_config = drm_crtc_helper_set_config,
6247 .destroy = intel_crtc_destroy,
6248 .page_flip = intel_crtc_page_flip,
6249 };
6250
6251 static void intel_sanitize_modesetting(struct drm_device *dev,
6252 int pipe, int plane)
6253 {
6254 struct drm_i915_private *dev_priv = dev->dev_private;
6255 u32 reg, val;
6256
6257 if (HAS_PCH_SPLIT(dev))
6258 return;
6259
6260 /* Who knows what state these registers were left in by the BIOS or
6261 * grub?
6262 *
6263 * If we leave the registers in a conflicting state (e.g. with the
6264 * display plane reading from the other pipe than the one we intend
6265 * to use) then when we attempt to teardown the active mode, we will
6266 * not disable the pipes and planes in the correct order -- leaving
6267 * a plane reading from a disabled pipe and possibly leading to
6268 * undefined behaviour.
6269 */
6270
6271 reg = DSPCNTR(plane);
6272 val = I915_READ(reg);
6273
6274 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6275 return;
6276 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6277 return;
6278
6279 /* This display plane is active and attached to the other CPU pipe. */
6280 pipe = !pipe;
6281
6282 /* Disable the plane and wait for it to stop reading from the pipe. */
6283 intel_disable_plane(dev_priv, plane, pipe);
6284 intel_disable_pipe(dev_priv, pipe);
6285 }
6286
6287 static void intel_crtc_init(struct drm_device *dev, int pipe)
6288 {
6289 drm_i915_private_t *dev_priv = dev->dev_private;
6290 struct intel_crtc *intel_crtc;
6291 int i;
6292
6293 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6294 if (intel_crtc == NULL)
6295 return;
6296
6297 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6298
6299 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6300 for (i = 0; i < 256; i++) {
6301 intel_crtc->lut_r[i] = i;
6302 intel_crtc->lut_g[i] = i;
6303 intel_crtc->lut_b[i] = i;
6304 }
6305
6306 /* Swap pipes & planes for FBC on pre-965 */
6307 intel_crtc->pipe = pipe;
6308 intel_crtc->plane = pipe;
6309 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6310 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6311 intel_crtc->plane = !pipe;
6312 }
6313
6314 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6315 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6316 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6317 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6318
6319 intel_crtc_reset(&intel_crtc->base);
6320 intel_crtc->active = true; /* force the pipe off on setup_init_config */
6321
6322 if (HAS_PCH_SPLIT(dev)) {
6323 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6324 intel_helper_funcs.commit = ironlake_crtc_commit;
6325 } else {
6326 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6327 intel_helper_funcs.commit = i9xx_crtc_commit;
6328 }
6329
6330 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6331
6332 intel_crtc->busy = false;
6333
6334 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6335 (unsigned long)intel_crtc);
6336
6337 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6338 }
6339
6340 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6341 struct drm_file *file)
6342 {
6343 drm_i915_private_t *dev_priv = dev->dev_private;
6344 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6345 struct drm_mode_object *drmmode_obj;
6346 struct intel_crtc *crtc;
6347
6348 if (!dev_priv) {
6349 DRM_ERROR("called with no initialization\n");
6350 return -EINVAL;
6351 }
6352
6353 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6354 DRM_MODE_OBJECT_CRTC);
6355
6356 if (!drmmode_obj) {
6357 DRM_ERROR("no such CRTC id\n");
6358 return -EINVAL;
6359 }
6360
6361 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6362 pipe_from_crtc_id->pipe = crtc->pipe;
6363
6364 return 0;
6365 }
6366
6367 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6368 {
6369 struct intel_encoder *encoder;
6370 int index_mask = 0;
6371 int entry = 0;
6372
6373 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6374 if (type_mask & encoder->clone_mask)
6375 index_mask |= (1 << entry);
6376 entry++;
6377 }
6378
6379 return index_mask;
6380 }
6381
6382 static bool has_edp_a(struct drm_device *dev)
6383 {
6384 struct drm_i915_private *dev_priv = dev->dev_private;
6385
6386 if (!IS_MOBILE(dev))
6387 return false;
6388
6389 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6390 return false;
6391
6392 if (IS_GEN5(dev) &&
6393 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6394 return false;
6395
6396 return true;
6397 }
6398
6399 static void intel_setup_outputs(struct drm_device *dev)
6400 {
6401 struct drm_i915_private *dev_priv = dev->dev_private;
6402 struct intel_encoder *encoder;
6403 bool dpd_is_edp = false;
6404 bool has_lvds = false;
6405
6406 if (IS_MOBILE(dev) && !IS_I830(dev))
6407 has_lvds = intel_lvds_init(dev);
6408 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6409 /* disable the panel fitter on everything but LVDS */
6410 I915_WRITE(PFIT_CONTROL, 0);
6411 }
6412
6413 if (HAS_PCH_SPLIT(dev)) {
6414 dpd_is_edp = intel_dpd_is_edp(dev);
6415
6416 if (has_edp_a(dev))
6417 intel_dp_init(dev, DP_A);
6418
6419 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6420 intel_dp_init(dev, PCH_DP_D);
6421 }
6422
6423 intel_crt_init(dev);
6424
6425 if (HAS_PCH_SPLIT(dev)) {
6426 int found;
6427
6428 if (I915_READ(HDMIB) & PORT_DETECTED) {
6429 /* PCH SDVOB multiplex with HDMIB */
6430 found = intel_sdvo_init(dev, PCH_SDVOB);
6431 if (!found)
6432 intel_hdmi_init(dev, HDMIB);
6433 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6434 intel_dp_init(dev, PCH_DP_B);
6435 }
6436
6437 if (I915_READ(HDMIC) & PORT_DETECTED)
6438 intel_hdmi_init(dev, HDMIC);
6439
6440 if (I915_READ(HDMID) & PORT_DETECTED)
6441 intel_hdmi_init(dev, HDMID);
6442
6443 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6444 intel_dp_init(dev, PCH_DP_C);
6445
6446 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6447 intel_dp_init(dev, PCH_DP_D);
6448
6449 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6450 bool found = false;
6451
6452 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6453 DRM_DEBUG_KMS("probing SDVOB\n");
6454 found = intel_sdvo_init(dev, SDVOB);
6455 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6456 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6457 intel_hdmi_init(dev, SDVOB);
6458 }
6459
6460 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6461 DRM_DEBUG_KMS("probing DP_B\n");
6462 intel_dp_init(dev, DP_B);
6463 }
6464 }
6465
6466 /* Before G4X SDVOC doesn't have its own detect register */
6467
6468 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6469 DRM_DEBUG_KMS("probing SDVOC\n");
6470 found = intel_sdvo_init(dev, SDVOC);
6471 }
6472
6473 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6474
6475 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6476 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6477 intel_hdmi_init(dev, SDVOC);
6478 }
6479 if (SUPPORTS_INTEGRATED_DP(dev)) {
6480 DRM_DEBUG_KMS("probing DP_C\n");
6481 intel_dp_init(dev, DP_C);
6482 }
6483 }
6484
6485 if (SUPPORTS_INTEGRATED_DP(dev) &&
6486 (I915_READ(DP_D) & DP_DETECTED)) {
6487 DRM_DEBUG_KMS("probing DP_D\n");
6488 intel_dp_init(dev, DP_D);
6489 }
6490 } else if (IS_GEN2(dev))
6491 intel_dvo_init(dev);
6492
6493 if (SUPPORTS_TV(dev))
6494 intel_tv_init(dev);
6495
6496 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6497 encoder->base.possible_crtcs = encoder->crtc_mask;
6498 encoder->base.possible_clones =
6499 intel_encoder_clones(dev, encoder->clone_mask);
6500 }
6501
6502 intel_panel_setup_backlight(dev);
6503 }
6504
6505 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6506 {
6507 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6508
6509 drm_framebuffer_cleanup(fb);
6510 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6511
6512 kfree(intel_fb);
6513 }
6514
6515 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6516 struct drm_file *file,
6517 unsigned int *handle)
6518 {
6519 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6520 struct drm_i915_gem_object *obj = intel_fb->obj;
6521
6522 return drm_gem_handle_create(file, &obj->base, handle);
6523 }
6524
6525 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6526 .destroy = intel_user_framebuffer_destroy,
6527 .create_handle = intel_user_framebuffer_create_handle,
6528 };
6529
6530 int intel_framebuffer_init(struct drm_device *dev,
6531 struct intel_framebuffer *intel_fb,
6532 struct drm_mode_fb_cmd *mode_cmd,
6533 struct drm_i915_gem_object *obj)
6534 {
6535 int ret;
6536
6537 if (obj->tiling_mode == I915_TILING_Y)
6538 return -EINVAL;
6539
6540 if (mode_cmd->pitch & 63)
6541 return -EINVAL;
6542
6543 switch (mode_cmd->bpp) {
6544 case 8:
6545 case 16:
6546 case 24:
6547 case 32:
6548 break;
6549 default:
6550 return -EINVAL;
6551 }
6552
6553 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6554 if (ret) {
6555 DRM_ERROR("framebuffer init failed %d\n", ret);
6556 return ret;
6557 }
6558
6559 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6560 intel_fb->obj = obj;
6561 return 0;
6562 }
6563
6564 static struct drm_framebuffer *
6565 intel_user_framebuffer_create(struct drm_device *dev,
6566 struct drm_file *filp,
6567 struct drm_mode_fb_cmd *mode_cmd)
6568 {
6569 struct drm_i915_gem_object *obj;
6570 struct intel_framebuffer *intel_fb;
6571 int ret;
6572
6573 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
6574 if (&obj->base == NULL)
6575 return ERR_PTR(-ENOENT);
6576
6577 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6578 if (!intel_fb)
6579 return ERR_PTR(-ENOMEM);
6580
6581 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6582 if (ret) {
6583 drm_gem_object_unreference_unlocked(&obj->base);
6584 kfree(intel_fb);
6585 return ERR_PTR(ret);
6586 }
6587
6588 return &intel_fb->base;
6589 }
6590
6591 static const struct drm_mode_config_funcs intel_mode_funcs = {
6592 .fb_create = intel_user_framebuffer_create,
6593 .output_poll_changed = intel_fb_output_poll_changed,
6594 };
6595
6596 static struct drm_i915_gem_object *
6597 intel_alloc_context_page(struct drm_device *dev)
6598 {
6599 struct drm_i915_gem_object *ctx;
6600 int ret;
6601
6602 ctx = i915_gem_alloc_object(dev, 4096);
6603 if (!ctx) {
6604 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6605 return NULL;
6606 }
6607
6608 mutex_lock(&dev->struct_mutex);
6609 ret = i915_gem_object_pin(ctx, 4096, true);
6610 if (ret) {
6611 DRM_ERROR("failed to pin power context: %d\n", ret);
6612 goto err_unref;
6613 }
6614
6615 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
6616 if (ret) {
6617 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
6618 goto err_unpin;
6619 }
6620 mutex_unlock(&dev->struct_mutex);
6621
6622 return ctx;
6623
6624 err_unpin:
6625 i915_gem_object_unpin(ctx);
6626 err_unref:
6627 drm_gem_object_unreference(&ctx->base);
6628 mutex_unlock(&dev->struct_mutex);
6629 return NULL;
6630 }
6631
6632 bool ironlake_set_drps(struct drm_device *dev, u8 val)
6633 {
6634 struct drm_i915_private *dev_priv = dev->dev_private;
6635 u16 rgvswctl;
6636
6637 rgvswctl = I915_READ16(MEMSWCTL);
6638 if (rgvswctl & MEMCTL_CMD_STS) {
6639 DRM_DEBUG("gpu busy, RCS change rejected\n");
6640 return false; /* still busy with another command */
6641 }
6642
6643 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
6644 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
6645 I915_WRITE16(MEMSWCTL, rgvswctl);
6646 POSTING_READ16(MEMSWCTL);
6647
6648 rgvswctl |= MEMCTL_CMD_STS;
6649 I915_WRITE16(MEMSWCTL, rgvswctl);
6650
6651 return true;
6652 }
6653
6654 void ironlake_enable_drps(struct drm_device *dev)
6655 {
6656 struct drm_i915_private *dev_priv = dev->dev_private;
6657 u32 rgvmodectl = I915_READ(MEMMODECTL);
6658 u8 fmax, fmin, fstart, vstart;
6659
6660 /* Enable temp reporting */
6661 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
6662 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
6663
6664 /* 100ms RC evaluation intervals */
6665 I915_WRITE(RCUPEI, 100000);
6666 I915_WRITE(RCDNEI, 100000);
6667
6668 /* Set max/min thresholds to 90ms and 80ms respectively */
6669 I915_WRITE(RCBMAXAVG, 90000);
6670 I915_WRITE(RCBMINAVG, 80000);
6671
6672 I915_WRITE(MEMIHYST, 1);
6673
6674 /* Set up min, max, and cur for interrupt handling */
6675 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
6676 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
6677 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
6678 MEMMODE_FSTART_SHIFT;
6679
6680 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
6681 PXVFREQ_PX_SHIFT;
6682
6683 dev_priv->fmax = fmax; /* IPS callback will increase this */
6684 dev_priv->fstart = fstart;
6685
6686 dev_priv->max_delay = fstart;
6687 dev_priv->min_delay = fmin;
6688 dev_priv->cur_delay = fstart;
6689
6690 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
6691 fmax, fmin, fstart);
6692
6693 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
6694
6695 /*
6696 * Interrupts will be enabled in ironlake_irq_postinstall
6697 */
6698
6699 I915_WRITE(VIDSTART, vstart);
6700 POSTING_READ(VIDSTART);
6701
6702 rgvmodectl |= MEMMODE_SWMODE_EN;
6703 I915_WRITE(MEMMODECTL, rgvmodectl);
6704
6705 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
6706 DRM_ERROR("stuck trying to change perf mode\n");
6707 msleep(1);
6708
6709 ironlake_set_drps(dev, fstart);
6710
6711 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
6712 I915_READ(0x112e0);
6713 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
6714 dev_priv->last_count2 = I915_READ(0x112f4);
6715 getrawmonotonic(&dev_priv->last_time2);
6716 }
6717
6718 void ironlake_disable_drps(struct drm_device *dev)
6719 {
6720 struct drm_i915_private *dev_priv = dev->dev_private;
6721 u16 rgvswctl = I915_READ16(MEMSWCTL);
6722
6723 /* Ack interrupts, disable EFC interrupt */
6724 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
6725 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
6726 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
6727 I915_WRITE(DEIIR, DE_PCU_EVENT);
6728 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
6729
6730 /* Go back to the starting frequency */
6731 ironlake_set_drps(dev, dev_priv->fstart);
6732 msleep(1);
6733 rgvswctl |= MEMCTL_CMD_STS;
6734 I915_WRITE(MEMSWCTL, rgvswctl);
6735 msleep(1);
6736
6737 }
6738
6739 void gen6_set_rps(struct drm_device *dev, u8 val)
6740 {
6741 struct drm_i915_private *dev_priv = dev->dev_private;
6742 u32 swreq;
6743
6744 swreq = (val & 0x3ff) << 25;
6745 I915_WRITE(GEN6_RPNSWREQ, swreq);
6746 }
6747
6748 void gen6_disable_rps(struct drm_device *dev)
6749 {
6750 struct drm_i915_private *dev_priv = dev->dev_private;
6751
6752 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6753 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
6754 I915_WRITE(GEN6_PMIER, 0);
6755 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
6756 }
6757
6758 static unsigned long intel_pxfreq(u32 vidfreq)
6759 {
6760 unsigned long freq;
6761 int div = (vidfreq & 0x3f0000) >> 16;
6762 int post = (vidfreq & 0x3000) >> 12;
6763 int pre = (vidfreq & 0x7);
6764
6765 if (!pre)
6766 return 0;
6767
6768 freq = ((div * 133333) / ((1<<post) * pre));
6769
6770 return freq;
6771 }
6772
6773 void intel_init_emon(struct drm_device *dev)
6774 {
6775 struct drm_i915_private *dev_priv = dev->dev_private;
6776 u32 lcfuse;
6777 u8 pxw[16];
6778 int i;
6779
6780 /* Disable to program */
6781 I915_WRITE(ECR, 0);
6782 POSTING_READ(ECR);
6783
6784 /* Program energy weights for various events */
6785 I915_WRITE(SDEW, 0x15040d00);
6786 I915_WRITE(CSIEW0, 0x007f0000);
6787 I915_WRITE(CSIEW1, 0x1e220004);
6788 I915_WRITE(CSIEW2, 0x04000004);
6789
6790 for (i = 0; i < 5; i++)
6791 I915_WRITE(PEW + (i * 4), 0);
6792 for (i = 0; i < 3; i++)
6793 I915_WRITE(DEW + (i * 4), 0);
6794
6795 /* Program P-state weights to account for frequency power adjustment */
6796 for (i = 0; i < 16; i++) {
6797 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
6798 unsigned long freq = intel_pxfreq(pxvidfreq);
6799 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6800 PXVFREQ_PX_SHIFT;
6801 unsigned long val;
6802
6803 val = vid * vid;
6804 val *= (freq / 1000);
6805 val *= 255;
6806 val /= (127*127*900);
6807 if (val > 0xff)
6808 DRM_ERROR("bad pxval: %ld\n", val);
6809 pxw[i] = val;
6810 }
6811 /* Render standby states get 0 weight */
6812 pxw[14] = 0;
6813 pxw[15] = 0;
6814
6815 for (i = 0; i < 4; i++) {
6816 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6817 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6818 I915_WRITE(PXW + (i * 4), val);
6819 }
6820
6821 /* Adjust magic regs to magic values (more experimental results) */
6822 I915_WRITE(OGW0, 0);
6823 I915_WRITE(OGW1, 0);
6824 I915_WRITE(EG0, 0x00007f00);
6825 I915_WRITE(EG1, 0x0000000e);
6826 I915_WRITE(EG2, 0x000e0000);
6827 I915_WRITE(EG3, 0x68000300);
6828 I915_WRITE(EG4, 0x42000000);
6829 I915_WRITE(EG5, 0x00140031);
6830 I915_WRITE(EG6, 0);
6831 I915_WRITE(EG7, 0);
6832
6833 for (i = 0; i < 8; i++)
6834 I915_WRITE(PXWL + (i * 4), 0);
6835
6836 /* Enable PMON + select events */
6837 I915_WRITE(ECR, 0x80000019);
6838
6839 lcfuse = I915_READ(LCFUSE02);
6840
6841 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
6842 }
6843
6844 void gen6_enable_rps(struct drm_i915_private *dev_priv)
6845 {
6846 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
6847 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
6848 u32 pcu_mbox;
6849 int cur_freq, min_freq, max_freq;
6850 int i;
6851
6852 /* Here begins a magic sequence of register writes to enable
6853 * auto-downclocking.
6854 *
6855 * Perhaps there might be some value in exposing these to
6856 * userspace...
6857 */
6858 I915_WRITE(GEN6_RC_STATE, 0);
6859 __gen6_gt_force_wake_get(dev_priv);
6860
6861 /* disable the counters and set deterministic thresholds */
6862 I915_WRITE(GEN6_RC_CONTROL, 0);
6863
6864 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
6865 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
6866 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
6867 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6868 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6869
6870 for (i = 0; i < I915_NUM_RINGS; i++)
6871 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
6872
6873 I915_WRITE(GEN6_RC_SLEEP, 0);
6874 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
6875 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
6876 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
6877 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
6878
6879 I915_WRITE(GEN6_RC_CONTROL,
6880 GEN6_RC_CTL_RC6p_ENABLE |
6881 GEN6_RC_CTL_RC6_ENABLE |
6882 GEN6_RC_CTL_EI_MODE(1) |
6883 GEN6_RC_CTL_HW_ENABLE);
6884
6885 I915_WRITE(GEN6_RPNSWREQ,
6886 GEN6_FREQUENCY(10) |
6887 GEN6_OFFSET(0) |
6888 GEN6_AGGRESSIVE_TURBO);
6889 I915_WRITE(GEN6_RC_VIDEO_FREQ,
6890 GEN6_FREQUENCY(12));
6891
6892 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6893 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
6894 18 << 24 |
6895 6 << 16);
6896 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
6897 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
6898 I915_WRITE(GEN6_RP_UP_EI, 100000);
6899 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
6900 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6901 I915_WRITE(GEN6_RP_CONTROL,
6902 GEN6_RP_MEDIA_TURBO |
6903 GEN6_RP_USE_NORMAL_FREQ |
6904 GEN6_RP_MEDIA_IS_GFX |
6905 GEN6_RP_ENABLE |
6906 GEN6_RP_UP_BUSY_AVG |
6907 GEN6_RP_DOWN_IDLE_CONT);
6908
6909 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6910 500))
6911 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6912
6913 I915_WRITE(GEN6_PCODE_DATA, 0);
6914 I915_WRITE(GEN6_PCODE_MAILBOX,
6915 GEN6_PCODE_READY |
6916 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
6917 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6918 500))
6919 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6920
6921 min_freq = (rp_state_cap & 0xff0000) >> 16;
6922 max_freq = rp_state_cap & 0xff;
6923 cur_freq = (gt_perf_status & 0xff00) >> 8;
6924
6925 /* Check for overclock support */
6926 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6927 500))
6928 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6929 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
6930 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
6931 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6932 500))
6933 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6934 if (pcu_mbox & (1<<31)) { /* OC supported */
6935 max_freq = pcu_mbox & 0xff;
6936 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 100);
6937 }
6938
6939 /* In units of 100MHz */
6940 dev_priv->max_delay = max_freq;
6941 dev_priv->min_delay = min_freq;
6942 dev_priv->cur_delay = cur_freq;
6943
6944 /* requires MSI enabled */
6945 I915_WRITE(GEN6_PMIER,
6946 GEN6_PM_MBOX_EVENT |
6947 GEN6_PM_THERMAL_EVENT |
6948 GEN6_PM_RP_DOWN_TIMEOUT |
6949 GEN6_PM_RP_UP_THRESHOLD |
6950 GEN6_PM_RP_DOWN_THRESHOLD |
6951 GEN6_PM_RP_UP_EI_EXPIRED |
6952 GEN6_PM_RP_DOWN_EI_EXPIRED);
6953 I915_WRITE(GEN6_PMIMR, 0);
6954 /* enable all PM interrupts */
6955 I915_WRITE(GEN6_PMINTRMSK, 0);
6956
6957 __gen6_gt_force_wake_put(dev_priv);
6958 }
6959
6960 void intel_enable_clock_gating(struct drm_device *dev)
6961 {
6962 struct drm_i915_private *dev_priv = dev->dev_private;
6963 int pipe;
6964
6965 /*
6966 * Disable clock gating reported to work incorrectly according to the
6967 * specs, but enable as much else as we can.
6968 */
6969 if (HAS_PCH_SPLIT(dev)) {
6970 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
6971
6972 if (IS_GEN5(dev)) {
6973 /* Required for FBC */
6974 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
6975 DPFCRUNIT_CLOCK_GATE_DISABLE |
6976 DPFDUNIT_CLOCK_GATE_DISABLE;
6977 /* Required for CxSR */
6978 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
6979
6980 I915_WRITE(PCH_3DCGDIS0,
6981 MARIUNIT_CLOCK_GATE_DISABLE |
6982 SVSMUNIT_CLOCK_GATE_DISABLE);
6983 I915_WRITE(PCH_3DCGDIS1,
6984 VFMUNIT_CLOCK_GATE_DISABLE);
6985 }
6986
6987 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
6988
6989 /*
6990 * On Ibex Peak and Cougar Point, we need to disable clock
6991 * gating for the panel power sequencer or it will fail to
6992 * start up when no ports are active.
6993 */
6994 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6995
6996 /*
6997 * According to the spec the following bits should be set in
6998 * order to enable memory self-refresh
6999 * The bit 22/21 of 0x42004
7000 * The bit 5 of 0x42020
7001 * The bit 15 of 0x45000
7002 */
7003 if (IS_GEN5(dev)) {
7004 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7005 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7006 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7007 I915_WRITE(ILK_DSPCLK_GATE,
7008 (I915_READ(ILK_DSPCLK_GATE) |
7009 ILK_DPARB_CLK_GATE));
7010 I915_WRITE(DISP_ARB_CTL,
7011 (I915_READ(DISP_ARB_CTL) |
7012 DISP_FBC_WM_DIS));
7013 I915_WRITE(WM3_LP_ILK, 0);
7014 I915_WRITE(WM2_LP_ILK, 0);
7015 I915_WRITE(WM1_LP_ILK, 0);
7016 }
7017 /*
7018 * Based on the document from hardware guys the following bits
7019 * should be set unconditionally in order to enable FBC.
7020 * The bit 22 of 0x42000
7021 * The bit 22 of 0x42004
7022 * The bit 7,8,9 of 0x42020.
7023 */
7024 if (IS_IRONLAKE_M(dev)) {
7025 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7026 I915_READ(ILK_DISPLAY_CHICKEN1) |
7027 ILK_FBCQ_DIS);
7028 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7029 I915_READ(ILK_DISPLAY_CHICKEN2) |
7030 ILK_DPARB_GATE);
7031 I915_WRITE(ILK_DSPCLK_GATE,
7032 I915_READ(ILK_DSPCLK_GATE) |
7033 ILK_DPFC_DIS1 |
7034 ILK_DPFC_DIS2 |
7035 ILK_CLK_FBC);
7036 }
7037
7038 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7039 I915_READ(ILK_DISPLAY_CHICKEN2) |
7040 ILK_ELPIN_409_SELECT);
7041
7042 if (IS_GEN5(dev)) {
7043 I915_WRITE(_3D_CHICKEN2,
7044 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7045 _3D_CHICKEN2_WM_READ_PIPELINED);
7046 }
7047
7048 if (IS_GEN6(dev)) {
7049 I915_WRITE(WM3_LP_ILK, 0);
7050 I915_WRITE(WM2_LP_ILK, 0);
7051 I915_WRITE(WM1_LP_ILK, 0);
7052
7053 /*
7054 * According to the spec the following bits should be
7055 * set in order to enable memory self-refresh and fbc:
7056 * The bit21 and bit22 of 0x42000
7057 * The bit21 and bit22 of 0x42004
7058 * The bit5 and bit7 of 0x42020
7059 * The bit14 of 0x70180
7060 * The bit14 of 0x71180
7061 */
7062 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7063 I915_READ(ILK_DISPLAY_CHICKEN1) |
7064 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7065 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7066 I915_READ(ILK_DISPLAY_CHICKEN2) |
7067 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7068 I915_WRITE(ILK_DSPCLK_GATE,
7069 I915_READ(ILK_DSPCLK_GATE) |
7070 ILK_DPARB_CLK_GATE |
7071 ILK_DPFD_CLK_GATE);
7072
7073 for_each_pipe(pipe)
7074 I915_WRITE(DSPCNTR(pipe),
7075 I915_READ(DSPCNTR(pipe)) |
7076 DISPPLANE_TRICKLE_FEED_DISABLE);
7077 }
7078 } else if (IS_G4X(dev)) {
7079 uint32_t dspclk_gate;
7080 I915_WRITE(RENCLK_GATE_D1, 0);
7081 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7082 GS_UNIT_CLOCK_GATE_DISABLE |
7083 CL_UNIT_CLOCK_GATE_DISABLE);
7084 I915_WRITE(RAMCLK_GATE_D, 0);
7085 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7086 OVRUNIT_CLOCK_GATE_DISABLE |
7087 OVCUNIT_CLOCK_GATE_DISABLE;
7088 if (IS_GM45(dev))
7089 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7090 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7091 } else if (IS_CRESTLINE(dev)) {
7092 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7093 I915_WRITE(RENCLK_GATE_D2, 0);
7094 I915_WRITE(DSPCLK_GATE_D, 0);
7095 I915_WRITE(RAMCLK_GATE_D, 0);
7096 I915_WRITE16(DEUC, 0);
7097 } else if (IS_BROADWATER(dev)) {
7098 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7099 I965_RCC_CLOCK_GATE_DISABLE |
7100 I965_RCPB_CLOCK_GATE_DISABLE |
7101 I965_ISC_CLOCK_GATE_DISABLE |
7102 I965_FBC_CLOCK_GATE_DISABLE);
7103 I915_WRITE(RENCLK_GATE_D2, 0);
7104 } else if (IS_GEN3(dev)) {
7105 u32 dstate = I915_READ(D_STATE);
7106
7107 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7108 DSTATE_DOT_CLOCK_GATING;
7109 I915_WRITE(D_STATE, dstate);
7110 } else if (IS_I85X(dev) || IS_I865G(dev)) {
7111 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7112 } else if (IS_I830(dev)) {
7113 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7114 }
7115 }
7116
7117 static void ironlake_teardown_rc6(struct drm_device *dev)
7118 {
7119 struct drm_i915_private *dev_priv = dev->dev_private;
7120
7121 if (dev_priv->renderctx) {
7122 i915_gem_object_unpin(dev_priv->renderctx);
7123 drm_gem_object_unreference(&dev_priv->renderctx->base);
7124 dev_priv->renderctx = NULL;
7125 }
7126
7127 if (dev_priv->pwrctx) {
7128 i915_gem_object_unpin(dev_priv->pwrctx);
7129 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7130 dev_priv->pwrctx = NULL;
7131 }
7132 }
7133
7134 static void ironlake_disable_rc6(struct drm_device *dev)
7135 {
7136 struct drm_i915_private *dev_priv = dev->dev_private;
7137
7138 if (I915_READ(PWRCTXA)) {
7139 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7140 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7141 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7142 50);
7143
7144 I915_WRITE(PWRCTXA, 0);
7145 POSTING_READ(PWRCTXA);
7146
7147 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7148 POSTING_READ(RSTDBYCTL);
7149 }
7150
7151 ironlake_teardown_rc6(dev);
7152 }
7153
7154 static int ironlake_setup_rc6(struct drm_device *dev)
7155 {
7156 struct drm_i915_private *dev_priv = dev->dev_private;
7157
7158 if (dev_priv->renderctx == NULL)
7159 dev_priv->renderctx = intel_alloc_context_page(dev);
7160 if (!dev_priv->renderctx)
7161 return -ENOMEM;
7162
7163 if (dev_priv->pwrctx == NULL)
7164 dev_priv->pwrctx = intel_alloc_context_page(dev);
7165 if (!dev_priv->pwrctx) {
7166 ironlake_teardown_rc6(dev);
7167 return -ENOMEM;
7168 }
7169
7170 return 0;
7171 }
7172
7173 void ironlake_enable_rc6(struct drm_device *dev)
7174 {
7175 struct drm_i915_private *dev_priv = dev->dev_private;
7176 int ret;
7177
7178 /* rc6 disabled by default due to repeated reports of hanging during
7179 * boot and resume.
7180 */
7181 if (!i915_enable_rc6)
7182 return;
7183
7184 ret = ironlake_setup_rc6(dev);
7185 if (ret)
7186 return;
7187
7188 /*
7189 * GPU can automatically power down the render unit if given a page
7190 * to save state.
7191 */
7192 ret = BEGIN_LP_RING(6);
7193 if (ret) {
7194 ironlake_teardown_rc6(dev);
7195 return;
7196 }
7197
7198 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7199 OUT_RING(MI_SET_CONTEXT);
7200 OUT_RING(dev_priv->renderctx->gtt_offset |
7201 MI_MM_SPACE_GTT |
7202 MI_SAVE_EXT_STATE_EN |
7203 MI_RESTORE_EXT_STATE_EN |
7204 MI_RESTORE_INHIBIT);
7205 OUT_RING(MI_SUSPEND_FLUSH);
7206 OUT_RING(MI_NOOP);
7207 OUT_RING(MI_FLUSH);
7208 ADVANCE_LP_RING();
7209
7210 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7211 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7212 }
7213
7214
7215 /* Set up chip specific display functions */
7216 static void intel_init_display(struct drm_device *dev)
7217 {
7218 struct drm_i915_private *dev_priv = dev->dev_private;
7219
7220 /* We always want a DPMS function */
7221 if (HAS_PCH_SPLIT(dev))
7222 dev_priv->display.dpms = ironlake_crtc_dpms;
7223 else
7224 dev_priv->display.dpms = i9xx_crtc_dpms;
7225
7226 if (I915_HAS_FBC(dev)) {
7227 if (HAS_PCH_SPLIT(dev)) {
7228 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7229 dev_priv->display.enable_fbc = ironlake_enable_fbc;
7230 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7231 } else if (IS_GM45(dev)) {
7232 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7233 dev_priv->display.enable_fbc = g4x_enable_fbc;
7234 dev_priv->display.disable_fbc = g4x_disable_fbc;
7235 } else if (IS_CRESTLINE(dev)) {
7236 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7237 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7238 dev_priv->display.disable_fbc = i8xx_disable_fbc;
7239 }
7240 /* 855GM needs testing */
7241 }
7242
7243 /* Returns the core display clock speed */
7244 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
7245 dev_priv->display.get_display_clock_speed =
7246 i945_get_display_clock_speed;
7247 else if (IS_I915G(dev))
7248 dev_priv->display.get_display_clock_speed =
7249 i915_get_display_clock_speed;
7250 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7251 dev_priv->display.get_display_clock_speed =
7252 i9xx_misc_get_display_clock_speed;
7253 else if (IS_I915GM(dev))
7254 dev_priv->display.get_display_clock_speed =
7255 i915gm_get_display_clock_speed;
7256 else if (IS_I865G(dev))
7257 dev_priv->display.get_display_clock_speed =
7258 i865_get_display_clock_speed;
7259 else if (IS_I85X(dev))
7260 dev_priv->display.get_display_clock_speed =
7261 i855_get_display_clock_speed;
7262 else /* 852, 830 */
7263 dev_priv->display.get_display_clock_speed =
7264 i830_get_display_clock_speed;
7265
7266 /* For FIFO watermark updates */
7267 if (HAS_PCH_SPLIT(dev)) {
7268 if (IS_GEN5(dev)) {
7269 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7270 dev_priv->display.update_wm = ironlake_update_wm;
7271 else {
7272 DRM_DEBUG_KMS("Failed to get proper latency. "
7273 "Disable CxSR\n");
7274 dev_priv->display.update_wm = NULL;
7275 }
7276 } else if (IS_GEN6(dev)) {
7277 if (SNB_READ_WM0_LATENCY()) {
7278 dev_priv->display.update_wm = sandybridge_update_wm;
7279 } else {
7280 DRM_DEBUG_KMS("Failed to read display plane latency. "
7281 "Disable CxSR\n");
7282 dev_priv->display.update_wm = NULL;
7283 }
7284 } else
7285 dev_priv->display.update_wm = NULL;
7286 } else if (IS_PINEVIEW(dev)) {
7287 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7288 dev_priv->is_ddr3,
7289 dev_priv->fsb_freq,
7290 dev_priv->mem_freq)) {
7291 DRM_INFO("failed to find known CxSR latency "
7292 "(found ddr%s fsb freq %d, mem freq %d), "
7293 "disabling CxSR\n",
7294 (dev_priv->is_ddr3 == 1) ? "3": "2",
7295 dev_priv->fsb_freq, dev_priv->mem_freq);
7296 /* Disable CxSR and never update its watermark again */
7297 pineview_disable_cxsr(dev);
7298 dev_priv->display.update_wm = NULL;
7299 } else
7300 dev_priv->display.update_wm = pineview_update_wm;
7301 } else if (IS_G4X(dev))
7302 dev_priv->display.update_wm = g4x_update_wm;
7303 else if (IS_GEN4(dev))
7304 dev_priv->display.update_wm = i965_update_wm;
7305 else if (IS_GEN3(dev)) {
7306 dev_priv->display.update_wm = i9xx_update_wm;
7307 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7308 } else if (IS_I85X(dev)) {
7309 dev_priv->display.update_wm = i9xx_update_wm;
7310 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
7311 } else {
7312 dev_priv->display.update_wm = i830_update_wm;
7313 if (IS_845G(dev))
7314 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7315 else
7316 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7317 }
7318 }
7319
7320 /*
7321 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7322 * resume, or other times. This quirk makes sure that's the case for
7323 * affected systems.
7324 */
7325 static void quirk_pipea_force (struct drm_device *dev)
7326 {
7327 struct drm_i915_private *dev_priv = dev->dev_private;
7328
7329 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7330 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
7331 }
7332
7333 struct intel_quirk {
7334 int device;
7335 int subsystem_vendor;
7336 int subsystem_device;
7337 void (*hook)(struct drm_device *dev);
7338 };
7339
7340 struct intel_quirk intel_quirks[] = {
7341 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
7342 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
7343 /* HP Mini needs pipe A force quirk (LP: #322104) */
7344 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
7345
7346 /* Thinkpad R31 needs pipe A force quirk */
7347 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7348 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7349 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7350
7351 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7352 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
7353 /* ThinkPad X40 needs pipe A force quirk */
7354
7355 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7356 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7357
7358 /* 855 & before need to leave pipe A & dpll A up */
7359 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7360 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7361 };
7362
7363 static void intel_init_quirks(struct drm_device *dev)
7364 {
7365 struct pci_dev *d = dev->pdev;
7366 int i;
7367
7368 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7369 struct intel_quirk *q = &intel_quirks[i];
7370
7371 if (d->device == q->device &&
7372 (d->subsystem_vendor == q->subsystem_vendor ||
7373 q->subsystem_vendor == PCI_ANY_ID) &&
7374 (d->subsystem_device == q->subsystem_device ||
7375 q->subsystem_device == PCI_ANY_ID))
7376 q->hook(dev);
7377 }
7378 }
7379
7380 /* Disable the VGA plane that we never use */
7381 static void i915_disable_vga(struct drm_device *dev)
7382 {
7383 struct drm_i915_private *dev_priv = dev->dev_private;
7384 u8 sr1;
7385 u32 vga_reg;
7386
7387 if (HAS_PCH_SPLIT(dev))
7388 vga_reg = CPU_VGACNTRL;
7389 else
7390 vga_reg = VGACNTRL;
7391
7392 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7393 outb(1, VGA_SR_INDEX);
7394 sr1 = inb(VGA_SR_DATA);
7395 outb(sr1 | 1<<5, VGA_SR_DATA);
7396 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7397 udelay(300);
7398
7399 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7400 POSTING_READ(vga_reg);
7401 }
7402
7403 void intel_modeset_init(struct drm_device *dev)
7404 {
7405 struct drm_i915_private *dev_priv = dev->dev_private;
7406 int i;
7407
7408 drm_mode_config_init(dev);
7409
7410 dev->mode_config.min_width = 0;
7411 dev->mode_config.min_height = 0;
7412
7413 dev->mode_config.funcs = (void *)&intel_mode_funcs;
7414
7415 intel_init_quirks(dev);
7416
7417 intel_init_display(dev);
7418
7419 if (IS_GEN2(dev)) {
7420 dev->mode_config.max_width = 2048;
7421 dev->mode_config.max_height = 2048;
7422 } else if (IS_GEN3(dev)) {
7423 dev->mode_config.max_width = 4096;
7424 dev->mode_config.max_height = 4096;
7425 } else {
7426 dev->mode_config.max_width = 8192;
7427 dev->mode_config.max_height = 8192;
7428 }
7429 dev->mode_config.fb_base = dev->agp->base;
7430
7431 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7432 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
7433
7434 for (i = 0; i < dev_priv->num_pipe; i++) {
7435 intel_crtc_init(dev, i);
7436 }
7437
7438 intel_setup_outputs(dev);
7439
7440 intel_enable_clock_gating(dev);
7441
7442 /* Just disable it once at startup */
7443 i915_disable_vga(dev);
7444
7445 if (IS_IRONLAKE_M(dev)) {
7446 ironlake_enable_drps(dev);
7447 intel_init_emon(dev);
7448 }
7449
7450 if (IS_GEN6(dev))
7451 gen6_enable_rps(dev_priv);
7452
7453 if (IS_IRONLAKE_M(dev))
7454 ironlake_enable_rc6(dev);
7455
7456 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7457 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7458 (unsigned long)dev);
7459
7460 intel_setup_overlay(dev);
7461 }
7462
7463 void intel_modeset_cleanup(struct drm_device *dev)
7464 {
7465 struct drm_i915_private *dev_priv = dev->dev_private;
7466 struct drm_crtc *crtc;
7467 struct intel_crtc *intel_crtc;
7468
7469 drm_kms_helper_poll_fini(dev);
7470 mutex_lock(&dev->struct_mutex);
7471
7472 intel_unregister_dsm_handler();
7473
7474
7475 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7476 /* Skip inactive CRTCs */
7477 if (!crtc->fb)
7478 continue;
7479
7480 intel_crtc = to_intel_crtc(crtc);
7481 intel_increase_pllclock(crtc);
7482 }
7483
7484 if (dev_priv->display.disable_fbc)
7485 dev_priv->display.disable_fbc(dev);
7486
7487 if (IS_IRONLAKE_M(dev))
7488 ironlake_disable_drps(dev);
7489 if (IS_GEN6(dev))
7490 gen6_disable_rps(dev);
7491
7492 if (IS_IRONLAKE_M(dev))
7493 ironlake_disable_rc6(dev);
7494
7495 mutex_unlock(&dev->struct_mutex);
7496
7497 /* Disable the irq before mode object teardown, for the irq might
7498 * enqueue unpin/hotplug work. */
7499 drm_irq_uninstall(dev);
7500 cancel_work_sync(&dev_priv->hotplug_work);
7501
7502 /* Shut off idle work before the crtcs get freed. */
7503 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7504 intel_crtc = to_intel_crtc(crtc);
7505 del_timer_sync(&intel_crtc->idle_timer);
7506 }
7507 del_timer_sync(&dev_priv->idle_timer);
7508 cancel_work_sync(&dev_priv->idle_work);
7509
7510 drm_mode_config_cleanup(dev);
7511 }
7512
7513 /*
7514 * Return which encoder is currently attached for connector.
7515 */
7516 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
7517 {
7518 return &intel_attached_encoder(connector)->base;
7519 }
7520
7521 void intel_connector_attach_encoder(struct intel_connector *connector,
7522 struct intel_encoder *encoder)
7523 {
7524 connector->encoder = encoder;
7525 drm_mode_connector_attach_encoder(&connector->base,
7526 &encoder->base);
7527 }
7528
7529 /*
7530 * set vga decode state - true == enable VGA decode
7531 */
7532 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7533 {
7534 struct drm_i915_private *dev_priv = dev->dev_private;
7535 u16 gmch_ctrl;
7536
7537 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7538 if (state)
7539 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7540 else
7541 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7542 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7543 return 0;
7544 }
7545
7546 #ifdef CONFIG_DEBUG_FS
7547 #include <linux/seq_file.h>
7548
7549 struct intel_display_error_state {
7550 struct intel_cursor_error_state {
7551 u32 control;
7552 u32 position;
7553 u32 base;
7554 u32 size;
7555 } cursor[2];
7556
7557 struct intel_pipe_error_state {
7558 u32 conf;
7559 u32 source;
7560
7561 u32 htotal;
7562 u32 hblank;
7563 u32 hsync;
7564 u32 vtotal;
7565 u32 vblank;
7566 u32 vsync;
7567 } pipe[2];
7568
7569 struct intel_plane_error_state {
7570 u32 control;
7571 u32 stride;
7572 u32 size;
7573 u32 pos;
7574 u32 addr;
7575 u32 surface;
7576 u32 tile_offset;
7577 } plane[2];
7578 };
7579
7580 struct intel_display_error_state *
7581 intel_display_capture_error_state(struct drm_device *dev)
7582 {
7583 drm_i915_private_t *dev_priv = dev->dev_private;
7584 struct intel_display_error_state *error;
7585 int i;
7586
7587 error = kmalloc(sizeof(*error), GFP_ATOMIC);
7588 if (error == NULL)
7589 return NULL;
7590
7591 for (i = 0; i < 2; i++) {
7592 error->cursor[i].control = I915_READ(CURCNTR(i));
7593 error->cursor[i].position = I915_READ(CURPOS(i));
7594 error->cursor[i].base = I915_READ(CURBASE(i));
7595
7596 error->plane[i].control = I915_READ(DSPCNTR(i));
7597 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7598 error->plane[i].size = I915_READ(DSPSIZE(i));
7599 error->plane[i].pos= I915_READ(DSPPOS(i));
7600 error->plane[i].addr = I915_READ(DSPADDR(i));
7601 if (INTEL_INFO(dev)->gen >= 4) {
7602 error->plane[i].surface = I915_READ(DSPSURF(i));
7603 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7604 }
7605
7606 error->pipe[i].conf = I915_READ(PIPECONF(i));
7607 error->pipe[i].source = I915_READ(PIPESRC(i));
7608 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7609 error->pipe[i].hblank = I915_READ(HBLANK(i));
7610 error->pipe[i].hsync = I915_READ(HSYNC(i));
7611 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7612 error->pipe[i].vblank = I915_READ(VBLANK(i));
7613 error->pipe[i].vsync = I915_READ(VSYNC(i));
7614 }
7615
7616 return error;
7617 }
7618
7619 void
7620 intel_display_print_error_state(struct seq_file *m,
7621 struct drm_device *dev,
7622 struct intel_display_error_state *error)
7623 {
7624 int i;
7625
7626 for (i = 0; i < 2; i++) {
7627 seq_printf(m, "Pipe [%d]:\n", i);
7628 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
7629 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
7630 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
7631 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
7632 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
7633 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
7634 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
7635 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
7636
7637 seq_printf(m, "Plane [%d]:\n", i);
7638 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
7639 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
7640 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
7641 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
7642 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
7643 if (INTEL_INFO(dev)->gen >= 4) {
7644 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
7645 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
7646 }
7647
7648 seq_printf(m, "Cursor [%d]:\n", i);
7649 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
7650 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
7651 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
7652 }
7653 }
7654 #endif
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