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Merge tag 'drm-misc-next-2017-09-20' of git://anongit.freedesktop.org/git/drm-misc...
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "i915_gem_clflush.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
51
52 /* Primary plane formats for gen <= 3 */
53 static const uint32_t i8xx_primary_formats[] = {
54 DRM_FORMAT_C8,
55 DRM_FORMAT_RGB565,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_XRGB8888,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t i965_primary_formats[] = {
62 DRM_FORMAT_C8,
63 DRM_FORMAT_RGB565,
64 DRM_FORMAT_XRGB8888,
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_XRGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 };
69
70 static const uint64_t i9xx_format_modifiers[] = {
71 I915_FORMAT_MOD_X_TILED,
72 DRM_FORMAT_MOD_LINEAR,
73 DRM_FORMAT_MOD_INVALID
74 };
75
76 static const uint32_t skl_primary_formats[] = {
77 DRM_FORMAT_C8,
78 DRM_FORMAT_RGB565,
79 DRM_FORMAT_XRGB8888,
80 DRM_FORMAT_XBGR8888,
81 DRM_FORMAT_ARGB8888,
82 DRM_FORMAT_ABGR8888,
83 DRM_FORMAT_XRGB2101010,
84 DRM_FORMAT_XBGR2101010,
85 DRM_FORMAT_YUYV,
86 DRM_FORMAT_YVYU,
87 DRM_FORMAT_UYVY,
88 DRM_FORMAT_VYUY,
89 };
90
91 static const uint64_t skl_format_modifiers_noccs[] = {
92 I915_FORMAT_MOD_Yf_TILED,
93 I915_FORMAT_MOD_Y_TILED,
94 I915_FORMAT_MOD_X_TILED,
95 DRM_FORMAT_MOD_LINEAR,
96 DRM_FORMAT_MOD_INVALID
97 };
98
99 static const uint64_t skl_format_modifiers_ccs[] = {
100 I915_FORMAT_MOD_Yf_TILED_CCS,
101 I915_FORMAT_MOD_Y_TILED_CCS,
102 I915_FORMAT_MOD_Yf_TILED,
103 I915_FORMAT_MOD_Y_TILED,
104 I915_FORMAT_MOD_X_TILED,
105 DRM_FORMAT_MOD_LINEAR,
106 DRM_FORMAT_MOD_INVALID
107 };
108
109 /* Cursor formats */
110 static const uint32_t intel_cursor_formats[] = {
111 DRM_FORMAT_ARGB8888,
112 };
113
114 static const uint64_t cursor_format_modifiers[] = {
115 DRM_FORMAT_MOD_LINEAR,
116 DRM_FORMAT_MOD_INVALID
117 };
118
119 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
120 struct intel_crtc_state *pipe_config);
121 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
122 struct intel_crtc_state *pipe_config);
123
124 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
125 struct drm_i915_gem_object *obj,
126 struct drm_mode_fb_cmd2 *mode_cmd);
127 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
128 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
129 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
130 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
131 struct intel_link_m_n *m_n,
132 struct intel_link_m_n *m2_n2);
133 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
134 static void haswell_set_pipeconf(struct drm_crtc *crtc);
135 static void haswell_set_pipemisc(struct drm_crtc *crtc);
136 static void vlv_prepare_pll(struct intel_crtc *crtc,
137 const struct intel_crtc_state *pipe_config);
138 static void chv_prepare_pll(struct intel_crtc *crtc,
139 const struct intel_crtc_state *pipe_config);
140 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
141 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
142 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
143 struct intel_crtc_state *crtc_state);
144 static void skylake_pfit_enable(struct intel_crtc *crtc);
145 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
146 static void ironlake_pfit_enable(struct intel_crtc *crtc);
147 static void intel_modeset_setup_hw_state(struct drm_device *dev,
148 struct drm_modeset_acquire_ctx *ctx);
149 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
150
151 struct intel_limit {
152 struct {
153 int min, max;
154 } dot, vco, n, m, m1, m2, p, p1;
155
156 struct {
157 int dot_limit;
158 int p2_slow, p2_fast;
159 } p2;
160 };
161
162 /* returns HPLL frequency in kHz */
163 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
164 {
165 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
166
167 /* Obtain SKU information */
168 mutex_lock(&dev_priv->sb_lock);
169 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
170 CCK_FUSE_HPLL_FREQ_MASK;
171 mutex_unlock(&dev_priv->sb_lock);
172
173 return vco_freq[hpll_freq] * 1000;
174 }
175
176 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
177 const char *name, u32 reg, int ref_freq)
178 {
179 u32 val;
180 int divider;
181
182 mutex_lock(&dev_priv->sb_lock);
183 val = vlv_cck_read(dev_priv, reg);
184 mutex_unlock(&dev_priv->sb_lock);
185
186 divider = val & CCK_FREQUENCY_VALUES;
187
188 WARN((val & CCK_FREQUENCY_STATUS) !=
189 (divider << CCK_FREQUENCY_STATUS_SHIFT),
190 "%s change in progress\n", name);
191
192 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
193 }
194
195 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
196 const char *name, u32 reg)
197 {
198 if (dev_priv->hpll_freq == 0)
199 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
200
201 return vlv_get_cck_clock(dev_priv, name, reg,
202 dev_priv->hpll_freq);
203 }
204
205 static void intel_update_czclk(struct drm_i915_private *dev_priv)
206 {
207 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
208 return;
209
210 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
211 CCK_CZ_CLOCK_CONTROL);
212
213 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
214 }
215
216 static inline u32 /* units of 100MHz */
217 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
218 const struct intel_crtc_state *pipe_config)
219 {
220 if (HAS_DDI(dev_priv))
221 return pipe_config->port_clock; /* SPLL */
222 else if (IS_GEN5(dev_priv))
223 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
224 else
225 return 270000;
226 }
227
228 static const struct intel_limit intel_limits_i8xx_dac = {
229 .dot = { .min = 25000, .max = 350000 },
230 .vco = { .min = 908000, .max = 1512000 },
231 .n = { .min = 2, .max = 16 },
232 .m = { .min = 96, .max = 140 },
233 .m1 = { .min = 18, .max = 26 },
234 .m2 = { .min = 6, .max = 16 },
235 .p = { .min = 4, .max = 128 },
236 .p1 = { .min = 2, .max = 33 },
237 .p2 = { .dot_limit = 165000,
238 .p2_slow = 4, .p2_fast = 2 },
239 };
240
241 static const struct intel_limit intel_limits_i8xx_dvo = {
242 .dot = { .min = 25000, .max = 350000 },
243 .vco = { .min = 908000, .max = 1512000 },
244 .n = { .min = 2, .max = 16 },
245 .m = { .min = 96, .max = 140 },
246 .m1 = { .min = 18, .max = 26 },
247 .m2 = { .min = 6, .max = 16 },
248 .p = { .min = 4, .max = 128 },
249 .p1 = { .min = 2, .max = 33 },
250 .p2 = { .dot_limit = 165000,
251 .p2_slow = 4, .p2_fast = 4 },
252 };
253
254 static const struct intel_limit intel_limits_i8xx_lvds = {
255 .dot = { .min = 25000, .max = 350000 },
256 .vco = { .min = 908000, .max = 1512000 },
257 .n = { .min = 2, .max = 16 },
258 .m = { .min = 96, .max = 140 },
259 .m1 = { .min = 18, .max = 26 },
260 .m2 = { .min = 6, .max = 16 },
261 .p = { .min = 4, .max = 128 },
262 .p1 = { .min = 1, .max = 6 },
263 .p2 = { .dot_limit = 165000,
264 .p2_slow = 14, .p2_fast = 7 },
265 };
266
267 static const struct intel_limit intel_limits_i9xx_sdvo = {
268 .dot = { .min = 20000, .max = 400000 },
269 .vco = { .min = 1400000, .max = 2800000 },
270 .n = { .min = 1, .max = 6 },
271 .m = { .min = 70, .max = 120 },
272 .m1 = { .min = 8, .max = 18 },
273 .m2 = { .min = 3, .max = 7 },
274 .p = { .min = 5, .max = 80 },
275 .p1 = { .min = 1, .max = 8 },
276 .p2 = { .dot_limit = 200000,
277 .p2_slow = 10, .p2_fast = 5 },
278 };
279
280 static const struct intel_limit intel_limits_i9xx_lvds = {
281 .dot = { .min = 20000, .max = 400000 },
282 .vco = { .min = 1400000, .max = 2800000 },
283 .n = { .min = 1, .max = 6 },
284 .m = { .min = 70, .max = 120 },
285 .m1 = { .min = 8, .max = 18 },
286 .m2 = { .min = 3, .max = 7 },
287 .p = { .min = 7, .max = 98 },
288 .p1 = { .min = 1, .max = 8 },
289 .p2 = { .dot_limit = 112000,
290 .p2_slow = 14, .p2_fast = 7 },
291 };
292
293
294 static const struct intel_limit intel_limits_g4x_sdvo = {
295 .dot = { .min = 25000, .max = 270000 },
296 .vco = { .min = 1750000, .max = 3500000},
297 .n = { .min = 1, .max = 4 },
298 .m = { .min = 104, .max = 138 },
299 .m1 = { .min = 17, .max = 23 },
300 .m2 = { .min = 5, .max = 11 },
301 .p = { .min = 10, .max = 30 },
302 .p1 = { .min = 1, .max = 3},
303 .p2 = { .dot_limit = 270000,
304 .p2_slow = 10,
305 .p2_fast = 10
306 },
307 };
308
309 static const struct intel_limit intel_limits_g4x_hdmi = {
310 .dot = { .min = 22000, .max = 400000 },
311 .vco = { .min = 1750000, .max = 3500000},
312 .n = { .min = 1, .max = 4 },
313 .m = { .min = 104, .max = 138 },
314 .m1 = { .min = 16, .max = 23 },
315 .m2 = { .min = 5, .max = 11 },
316 .p = { .min = 5, .max = 80 },
317 .p1 = { .min = 1, .max = 8},
318 .p2 = { .dot_limit = 165000,
319 .p2_slow = 10, .p2_fast = 5 },
320 };
321
322 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
323 .dot = { .min = 20000, .max = 115000 },
324 .vco = { .min = 1750000, .max = 3500000 },
325 .n = { .min = 1, .max = 3 },
326 .m = { .min = 104, .max = 138 },
327 .m1 = { .min = 17, .max = 23 },
328 .m2 = { .min = 5, .max = 11 },
329 .p = { .min = 28, .max = 112 },
330 .p1 = { .min = 2, .max = 8 },
331 .p2 = { .dot_limit = 0,
332 .p2_slow = 14, .p2_fast = 14
333 },
334 };
335
336 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
337 .dot = { .min = 80000, .max = 224000 },
338 .vco = { .min = 1750000, .max = 3500000 },
339 .n = { .min = 1, .max = 3 },
340 .m = { .min = 104, .max = 138 },
341 .m1 = { .min = 17, .max = 23 },
342 .m2 = { .min = 5, .max = 11 },
343 .p = { .min = 14, .max = 42 },
344 .p1 = { .min = 2, .max = 6 },
345 .p2 = { .dot_limit = 0,
346 .p2_slow = 7, .p2_fast = 7
347 },
348 };
349
350 static const struct intel_limit intel_limits_pineview_sdvo = {
351 .dot = { .min = 20000, .max = 400000},
352 .vco = { .min = 1700000, .max = 3500000 },
353 /* Pineview's Ncounter is a ring counter */
354 .n = { .min = 3, .max = 6 },
355 .m = { .min = 2, .max = 256 },
356 /* Pineview only has one combined m divider, which we treat as m2. */
357 .m1 = { .min = 0, .max = 0 },
358 .m2 = { .min = 0, .max = 254 },
359 .p = { .min = 5, .max = 80 },
360 .p1 = { .min = 1, .max = 8 },
361 .p2 = { .dot_limit = 200000,
362 .p2_slow = 10, .p2_fast = 5 },
363 };
364
365 static const struct intel_limit intel_limits_pineview_lvds = {
366 .dot = { .min = 20000, .max = 400000 },
367 .vco = { .min = 1700000, .max = 3500000 },
368 .n = { .min = 3, .max = 6 },
369 .m = { .min = 2, .max = 256 },
370 .m1 = { .min = 0, .max = 0 },
371 .m2 = { .min = 0, .max = 254 },
372 .p = { .min = 7, .max = 112 },
373 .p1 = { .min = 1, .max = 8 },
374 .p2 = { .dot_limit = 112000,
375 .p2_slow = 14, .p2_fast = 14 },
376 };
377
378 /* Ironlake / Sandybridge
379 *
380 * We calculate clock using (register_value + 2) for N/M1/M2, so here
381 * the range value for them is (actual_value - 2).
382 */
383 static const struct intel_limit intel_limits_ironlake_dac = {
384 .dot = { .min = 25000, .max = 350000 },
385 .vco = { .min = 1760000, .max = 3510000 },
386 .n = { .min = 1, .max = 5 },
387 .m = { .min = 79, .max = 127 },
388 .m1 = { .min = 12, .max = 22 },
389 .m2 = { .min = 5, .max = 9 },
390 .p = { .min = 5, .max = 80 },
391 .p1 = { .min = 1, .max = 8 },
392 .p2 = { .dot_limit = 225000,
393 .p2_slow = 10, .p2_fast = 5 },
394 };
395
396 static const struct intel_limit intel_limits_ironlake_single_lvds = {
397 .dot = { .min = 25000, .max = 350000 },
398 .vco = { .min = 1760000, .max = 3510000 },
399 .n = { .min = 1, .max = 3 },
400 .m = { .min = 79, .max = 118 },
401 .m1 = { .min = 12, .max = 22 },
402 .m2 = { .min = 5, .max = 9 },
403 .p = { .min = 28, .max = 112 },
404 .p1 = { .min = 2, .max = 8 },
405 .p2 = { .dot_limit = 225000,
406 .p2_slow = 14, .p2_fast = 14 },
407 };
408
409 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
410 .dot = { .min = 25000, .max = 350000 },
411 .vco = { .min = 1760000, .max = 3510000 },
412 .n = { .min = 1, .max = 3 },
413 .m = { .min = 79, .max = 127 },
414 .m1 = { .min = 12, .max = 22 },
415 .m2 = { .min = 5, .max = 9 },
416 .p = { .min = 14, .max = 56 },
417 .p1 = { .min = 2, .max = 8 },
418 .p2 = { .dot_limit = 225000,
419 .p2_slow = 7, .p2_fast = 7 },
420 };
421
422 /* LVDS 100mhz refclk limits. */
423 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
424 .dot = { .min = 25000, .max = 350000 },
425 .vco = { .min = 1760000, .max = 3510000 },
426 .n = { .min = 1, .max = 2 },
427 .m = { .min = 79, .max = 126 },
428 .m1 = { .min = 12, .max = 22 },
429 .m2 = { .min = 5, .max = 9 },
430 .p = { .min = 28, .max = 112 },
431 .p1 = { .min = 2, .max = 8 },
432 .p2 = { .dot_limit = 225000,
433 .p2_slow = 14, .p2_fast = 14 },
434 };
435
436 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
437 .dot = { .min = 25000, .max = 350000 },
438 .vco = { .min = 1760000, .max = 3510000 },
439 .n = { .min = 1, .max = 3 },
440 .m = { .min = 79, .max = 126 },
441 .m1 = { .min = 12, .max = 22 },
442 .m2 = { .min = 5, .max = 9 },
443 .p = { .min = 14, .max = 42 },
444 .p1 = { .min = 2, .max = 6 },
445 .p2 = { .dot_limit = 225000,
446 .p2_slow = 7, .p2_fast = 7 },
447 };
448
449 static const struct intel_limit intel_limits_vlv = {
450 /*
451 * These are the data rate limits (measured in fast clocks)
452 * since those are the strictest limits we have. The fast
453 * clock and actual rate limits are more relaxed, so checking
454 * them would make no difference.
455 */
456 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
457 .vco = { .min = 4000000, .max = 6000000 },
458 .n = { .min = 1, .max = 7 },
459 .m1 = { .min = 2, .max = 3 },
460 .m2 = { .min = 11, .max = 156 },
461 .p1 = { .min = 2, .max = 3 },
462 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
463 };
464
465 static const struct intel_limit intel_limits_chv = {
466 /*
467 * These are the data rate limits (measured in fast clocks)
468 * since those are the strictest limits we have. The fast
469 * clock and actual rate limits are more relaxed, so checking
470 * them would make no difference.
471 */
472 .dot = { .min = 25000 * 5, .max = 540000 * 5},
473 .vco = { .min = 4800000, .max = 6480000 },
474 .n = { .min = 1, .max = 1 },
475 .m1 = { .min = 2, .max = 2 },
476 .m2 = { .min = 24 << 22, .max = 175 << 22 },
477 .p1 = { .min = 2, .max = 4 },
478 .p2 = { .p2_slow = 1, .p2_fast = 14 },
479 };
480
481 static const struct intel_limit intel_limits_bxt = {
482 /* FIXME: find real dot limits */
483 .dot = { .min = 0, .max = INT_MAX },
484 .vco = { .min = 4800000, .max = 6700000 },
485 .n = { .min = 1, .max = 1 },
486 .m1 = { .min = 2, .max = 2 },
487 /* FIXME: find real m2 limits */
488 .m2 = { .min = 2 << 22, .max = 255 << 22 },
489 .p1 = { .min = 2, .max = 4 },
490 .p2 = { .p2_slow = 1, .p2_fast = 20 },
491 };
492
493 static bool
494 needs_modeset(struct drm_crtc_state *state)
495 {
496 return drm_atomic_crtc_needs_modeset(state);
497 }
498
499 /*
500 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
501 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
502 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
503 * The helpers' return value is the rate of the clock that is fed to the
504 * display engine's pipe which can be the above fast dot clock rate or a
505 * divided-down version of it.
506 */
507 /* m1 is reserved as 0 in Pineview, n is a ring counter */
508 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
509 {
510 clock->m = clock->m2 + 2;
511 clock->p = clock->p1 * clock->p2;
512 if (WARN_ON(clock->n == 0 || clock->p == 0))
513 return 0;
514 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
515 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
516
517 return clock->dot;
518 }
519
520 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
521 {
522 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
523 }
524
525 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
526 {
527 clock->m = i9xx_dpll_compute_m(clock);
528 clock->p = clock->p1 * clock->p2;
529 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
530 return 0;
531 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
532 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
533
534 return clock->dot;
535 }
536
537 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
538 {
539 clock->m = clock->m1 * clock->m2;
540 clock->p = clock->p1 * clock->p2;
541 if (WARN_ON(clock->n == 0 || clock->p == 0))
542 return 0;
543 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
544 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
545
546 return clock->dot / 5;
547 }
548
549 int chv_calc_dpll_params(int refclk, struct dpll *clock)
550 {
551 clock->m = clock->m1 * clock->m2;
552 clock->p = clock->p1 * clock->p2;
553 if (WARN_ON(clock->n == 0 || clock->p == 0))
554 return 0;
555 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
556 clock->n << 22);
557 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
558
559 return clock->dot / 5;
560 }
561
562 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
563 /**
564 * Returns whether the given set of divisors are valid for a given refclk with
565 * the given connectors.
566 */
567
568 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
569 const struct intel_limit *limit,
570 const struct dpll *clock)
571 {
572 if (clock->n < limit->n.min || limit->n.max < clock->n)
573 INTELPllInvalid("n out of range\n");
574 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
575 INTELPllInvalid("p1 out of range\n");
576 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
577 INTELPllInvalid("m2 out of range\n");
578 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
579 INTELPllInvalid("m1 out of range\n");
580
581 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
582 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
583 if (clock->m1 <= clock->m2)
584 INTELPllInvalid("m1 <= m2\n");
585
586 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
587 !IS_GEN9_LP(dev_priv)) {
588 if (clock->p < limit->p.min || limit->p.max < clock->p)
589 INTELPllInvalid("p out of range\n");
590 if (clock->m < limit->m.min || limit->m.max < clock->m)
591 INTELPllInvalid("m out of range\n");
592 }
593
594 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
595 INTELPllInvalid("vco out of range\n");
596 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
597 * connector, etc., rather than just a single range.
598 */
599 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
600 INTELPllInvalid("dot out of range\n");
601
602 return true;
603 }
604
605 static int
606 i9xx_select_p2_div(const struct intel_limit *limit,
607 const struct intel_crtc_state *crtc_state,
608 int target)
609 {
610 struct drm_device *dev = crtc_state->base.crtc->dev;
611
612 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
613 /*
614 * For LVDS just rely on its current settings for dual-channel.
615 * We haven't figured out how to reliably set up different
616 * single/dual channel state, if we even can.
617 */
618 if (intel_is_dual_link_lvds(dev))
619 return limit->p2.p2_fast;
620 else
621 return limit->p2.p2_slow;
622 } else {
623 if (target < limit->p2.dot_limit)
624 return limit->p2.p2_slow;
625 else
626 return limit->p2.p2_fast;
627 }
628 }
629
630 /*
631 * Returns a set of divisors for the desired target clock with the given
632 * refclk, or FALSE. The returned values represent the clock equation:
633 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
634 *
635 * Target and reference clocks are specified in kHz.
636 *
637 * If match_clock is provided, then best_clock P divider must match the P
638 * divider from @match_clock used for LVDS downclocking.
639 */
640 static bool
641 i9xx_find_best_dpll(const struct intel_limit *limit,
642 struct intel_crtc_state *crtc_state,
643 int target, int refclk, struct dpll *match_clock,
644 struct dpll *best_clock)
645 {
646 struct drm_device *dev = crtc_state->base.crtc->dev;
647 struct dpll clock;
648 int err = target;
649
650 memset(best_clock, 0, sizeof(*best_clock));
651
652 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
653
654 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
655 clock.m1++) {
656 for (clock.m2 = limit->m2.min;
657 clock.m2 <= limit->m2.max; clock.m2++) {
658 if (clock.m2 >= clock.m1)
659 break;
660 for (clock.n = limit->n.min;
661 clock.n <= limit->n.max; clock.n++) {
662 for (clock.p1 = limit->p1.min;
663 clock.p1 <= limit->p1.max; clock.p1++) {
664 int this_err;
665
666 i9xx_calc_dpll_params(refclk, &clock);
667 if (!intel_PLL_is_valid(to_i915(dev),
668 limit,
669 &clock))
670 continue;
671 if (match_clock &&
672 clock.p != match_clock->p)
673 continue;
674
675 this_err = abs(clock.dot - target);
676 if (this_err < err) {
677 *best_clock = clock;
678 err = this_err;
679 }
680 }
681 }
682 }
683 }
684
685 return (err != target);
686 }
687
688 /*
689 * Returns a set of divisors for the desired target clock with the given
690 * refclk, or FALSE. The returned values represent the clock equation:
691 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
692 *
693 * Target and reference clocks are specified in kHz.
694 *
695 * If match_clock is provided, then best_clock P divider must match the P
696 * divider from @match_clock used for LVDS downclocking.
697 */
698 static bool
699 pnv_find_best_dpll(const struct intel_limit *limit,
700 struct intel_crtc_state *crtc_state,
701 int target, int refclk, struct dpll *match_clock,
702 struct dpll *best_clock)
703 {
704 struct drm_device *dev = crtc_state->base.crtc->dev;
705 struct dpll clock;
706 int err = target;
707
708 memset(best_clock, 0, sizeof(*best_clock));
709
710 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
711
712 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
713 clock.m1++) {
714 for (clock.m2 = limit->m2.min;
715 clock.m2 <= limit->m2.max; clock.m2++) {
716 for (clock.n = limit->n.min;
717 clock.n <= limit->n.max; clock.n++) {
718 for (clock.p1 = limit->p1.min;
719 clock.p1 <= limit->p1.max; clock.p1++) {
720 int this_err;
721
722 pnv_calc_dpll_params(refclk, &clock);
723 if (!intel_PLL_is_valid(to_i915(dev),
724 limit,
725 &clock))
726 continue;
727 if (match_clock &&
728 clock.p != match_clock->p)
729 continue;
730
731 this_err = abs(clock.dot - target);
732 if (this_err < err) {
733 *best_clock = clock;
734 err = this_err;
735 }
736 }
737 }
738 }
739 }
740
741 return (err != target);
742 }
743
744 /*
745 * Returns a set of divisors for the desired target clock with the given
746 * refclk, or FALSE. The returned values represent the clock equation:
747 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
748 *
749 * Target and reference clocks are specified in kHz.
750 *
751 * If match_clock is provided, then best_clock P divider must match the P
752 * divider from @match_clock used for LVDS downclocking.
753 */
754 static bool
755 g4x_find_best_dpll(const struct intel_limit *limit,
756 struct intel_crtc_state *crtc_state,
757 int target, int refclk, struct dpll *match_clock,
758 struct dpll *best_clock)
759 {
760 struct drm_device *dev = crtc_state->base.crtc->dev;
761 struct dpll clock;
762 int max_n;
763 bool found = false;
764 /* approximately equals target * 0.00585 */
765 int err_most = (target >> 8) + (target >> 9);
766
767 memset(best_clock, 0, sizeof(*best_clock));
768
769 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
770
771 max_n = limit->n.max;
772 /* based on hardware requirement, prefer smaller n to precision */
773 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
774 /* based on hardware requirement, prefere larger m1,m2 */
775 for (clock.m1 = limit->m1.max;
776 clock.m1 >= limit->m1.min; clock.m1--) {
777 for (clock.m2 = limit->m2.max;
778 clock.m2 >= limit->m2.min; clock.m2--) {
779 for (clock.p1 = limit->p1.max;
780 clock.p1 >= limit->p1.min; clock.p1--) {
781 int this_err;
782
783 i9xx_calc_dpll_params(refclk, &clock);
784 if (!intel_PLL_is_valid(to_i915(dev),
785 limit,
786 &clock))
787 continue;
788
789 this_err = abs(clock.dot - target);
790 if (this_err < err_most) {
791 *best_clock = clock;
792 err_most = this_err;
793 max_n = clock.n;
794 found = true;
795 }
796 }
797 }
798 }
799 }
800 return found;
801 }
802
803 /*
804 * Check if the calculated PLL configuration is more optimal compared to the
805 * best configuration and error found so far. Return the calculated error.
806 */
807 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
808 const struct dpll *calculated_clock,
809 const struct dpll *best_clock,
810 unsigned int best_error_ppm,
811 unsigned int *error_ppm)
812 {
813 /*
814 * For CHV ignore the error and consider only the P value.
815 * Prefer a bigger P value based on HW requirements.
816 */
817 if (IS_CHERRYVIEW(to_i915(dev))) {
818 *error_ppm = 0;
819
820 return calculated_clock->p > best_clock->p;
821 }
822
823 if (WARN_ON_ONCE(!target_freq))
824 return false;
825
826 *error_ppm = div_u64(1000000ULL *
827 abs(target_freq - calculated_clock->dot),
828 target_freq);
829 /*
830 * Prefer a better P value over a better (smaller) error if the error
831 * is small. Ensure this preference for future configurations too by
832 * setting the error to 0.
833 */
834 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
835 *error_ppm = 0;
836
837 return true;
838 }
839
840 return *error_ppm + 10 < best_error_ppm;
841 }
842
843 /*
844 * Returns a set of divisors for the desired target clock with the given
845 * refclk, or FALSE. The returned values represent the clock equation:
846 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
847 */
848 static bool
849 vlv_find_best_dpll(const struct intel_limit *limit,
850 struct intel_crtc_state *crtc_state,
851 int target, int refclk, struct dpll *match_clock,
852 struct dpll *best_clock)
853 {
854 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
855 struct drm_device *dev = crtc->base.dev;
856 struct dpll clock;
857 unsigned int bestppm = 1000000;
858 /* min update 19.2 MHz */
859 int max_n = min(limit->n.max, refclk / 19200);
860 bool found = false;
861
862 target *= 5; /* fast clock */
863
864 memset(best_clock, 0, sizeof(*best_clock));
865
866 /* based on hardware requirement, prefer smaller n to precision */
867 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
868 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
869 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
870 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
871 clock.p = clock.p1 * clock.p2;
872 /* based on hardware requirement, prefer bigger m1,m2 values */
873 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
874 unsigned int ppm;
875
876 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
877 refclk * clock.m1);
878
879 vlv_calc_dpll_params(refclk, &clock);
880
881 if (!intel_PLL_is_valid(to_i915(dev),
882 limit,
883 &clock))
884 continue;
885
886 if (!vlv_PLL_is_optimal(dev, target,
887 &clock,
888 best_clock,
889 bestppm, &ppm))
890 continue;
891
892 *best_clock = clock;
893 bestppm = ppm;
894 found = true;
895 }
896 }
897 }
898 }
899
900 return found;
901 }
902
903 /*
904 * Returns a set of divisors for the desired target clock with the given
905 * refclk, or FALSE. The returned values represent the clock equation:
906 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
907 */
908 static bool
909 chv_find_best_dpll(const struct intel_limit *limit,
910 struct intel_crtc_state *crtc_state,
911 int target, int refclk, struct dpll *match_clock,
912 struct dpll *best_clock)
913 {
914 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
915 struct drm_device *dev = crtc->base.dev;
916 unsigned int best_error_ppm;
917 struct dpll clock;
918 uint64_t m2;
919 int found = false;
920
921 memset(best_clock, 0, sizeof(*best_clock));
922 best_error_ppm = 1000000;
923
924 /*
925 * Based on hardware doc, the n always set to 1, and m1 always
926 * set to 2. If requires to support 200Mhz refclk, we need to
927 * revisit this because n may not 1 anymore.
928 */
929 clock.n = 1, clock.m1 = 2;
930 target *= 5; /* fast clock */
931
932 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
933 for (clock.p2 = limit->p2.p2_fast;
934 clock.p2 >= limit->p2.p2_slow;
935 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
936 unsigned int error_ppm;
937
938 clock.p = clock.p1 * clock.p2;
939
940 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
941 clock.n) << 22, refclk * clock.m1);
942
943 if (m2 > INT_MAX/clock.m1)
944 continue;
945
946 clock.m2 = m2;
947
948 chv_calc_dpll_params(refclk, &clock);
949
950 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
951 continue;
952
953 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
954 best_error_ppm, &error_ppm))
955 continue;
956
957 *best_clock = clock;
958 best_error_ppm = error_ppm;
959 found = true;
960 }
961 }
962
963 return found;
964 }
965
966 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
967 struct dpll *best_clock)
968 {
969 int refclk = 100000;
970 const struct intel_limit *limit = &intel_limits_bxt;
971
972 return chv_find_best_dpll(limit, crtc_state,
973 target_clock, refclk, NULL, best_clock);
974 }
975
976 bool intel_crtc_active(struct intel_crtc *crtc)
977 {
978 /* Be paranoid as we can arrive here with only partial
979 * state retrieved from the hardware during setup.
980 *
981 * We can ditch the adjusted_mode.crtc_clock check as soon
982 * as Haswell has gained clock readout/fastboot support.
983 *
984 * We can ditch the crtc->primary->fb check as soon as we can
985 * properly reconstruct framebuffers.
986 *
987 * FIXME: The intel_crtc->active here should be switched to
988 * crtc->state->active once we have proper CRTC states wired up
989 * for atomic.
990 */
991 return crtc->active && crtc->base.primary->state->fb &&
992 crtc->config->base.adjusted_mode.crtc_clock;
993 }
994
995 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
996 enum pipe pipe)
997 {
998 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
999
1000 return crtc->config->cpu_transcoder;
1001 }
1002
1003 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
1004 {
1005 i915_reg_t reg = PIPEDSL(pipe);
1006 u32 line1, line2;
1007 u32 line_mask;
1008
1009 if (IS_GEN2(dev_priv))
1010 line_mask = DSL_LINEMASK_GEN2;
1011 else
1012 line_mask = DSL_LINEMASK_GEN3;
1013
1014 line1 = I915_READ(reg) & line_mask;
1015 msleep(5);
1016 line2 = I915_READ(reg) & line_mask;
1017
1018 return line1 == line2;
1019 }
1020
1021 /*
1022 * intel_wait_for_pipe_off - wait for pipe to turn off
1023 * @crtc: crtc whose pipe to wait for
1024 *
1025 * After disabling a pipe, we can't wait for vblank in the usual way,
1026 * spinning on the vblank interrupt status bit, since we won't actually
1027 * see an interrupt when the pipe is disabled.
1028 *
1029 * On Gen4 and above:
1030 * wait for the pipe register state bit to turn off
1031 *
1032 * Otherwise:
1033 * wait for the display line value to settle (it usually
1034 * ends up stopping at the start of the next frame).
1035 *
1036 */
1037 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1038 {
1039 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1040 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1041 enum pipe pipe = crtc->pipe;
1042
1043 if (INTEL_GEN(dev_priv) >= 4) {
1044 i915_reg_t reg = PIPECONF(cpu_transcoder);
1045
1046 /* Wait for the Pipe State to go off */
1047 if (intel_wait_for_register(dev_priv,
1048 reg, I965_PIPECONF_ACTIVE, 0,
1049 100))
1050 WARN(1, "pipe_off wait timed out\n");
1051 } else {
1052 /* Wait for the display line to settle */
1053 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1054 WARN(1, "pipe_off wait timed out\n");
1055 }
1056 }
1057
1058 /* Only for pre-ILK configs */
1059 void assert_pll(struct drm_i915_private *dev_priv,
1060 enum pipe pipe, bool state)
1061 {
1062 u32 val;
1063 bool cur_state;
1064
1065 val = I915_READ(DPLL(pipe));
1066 cur_state = !!(val & DPLL_VCO_ENABLE);
1067 I915_STATE_WARN(cur_state != state,
1068 "PLL state assertion failure (expected %s, current %s)\n",
1069 onoff(state), onoff(cur_state));
1070 }
1071
1072 /* XXX: the dsi pll is shared between MIPI DSI ports */
1073 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1074 {
1075 u32 val;
1076 bool cur_state;
1077
1078 mutex_lock(&dev_priv->sb_lock);
1079 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1080 mutex_unlock(&dev_priv->sb_lock);
1081
1082 cur_state = val & DSI_PLL_VCO_EN;
1083 I915_STATE_WARN(cur_state != state,
1084 "DSI PLL state assertion failure (expected %s, current %s)\n",
1085 onoff(state), onoff(cur_state));
1086 }
1087
1088 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1089 enum pipe pipe, bool state)
1090 {
1091 bool cur_state;
1092 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1093 pipe);
1094
1095 if (HAS_DDI(dev_priv)) {
1096 /* DDI does not have a specific FDI_TX register */
1097 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1098 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1099 } else {
1100 u32 val = I915_READ(FDI_TX_CTL(pipe));
1101 cur_state = !!(val & FDI_TX_ENABLE);
1102 }
1103 I915_STATE_WARN(cur_state != state,
1104 "FDI TX state assertion failure (expected %s, current %s)\n",
1105 onoff(state), onoff(cur_state));
1106 }
1107 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1108 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1109
1110 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1111 enum pipe pipe, bool state)
1112 {
1113 u32 val;
1114 bool cur_state;
1115
1116 val = I915_READ(FDI_RX_CTL(pipe));
1117 cur_state = !!(val & FDI_RX_ENABLE);
1118 I915_STATE_WARN(cur_state != state,
1119 "FDI RX state assertion failure (expected %s, current %s)\n",
1120 onoff(state), onoff(cur_state));
1121 }
1122 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1123 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1124
1125 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1126 enum pipe pipe)
1127 {
1128 u32 val;
1129
1130 /* ILK FDI PLL is always enabled */
1131 if (IS_GEN5(dev_priv))
1132 return;
1133
1134 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1135 if (HAS_DDI(dev_priv))
1136 return;
1137
1138 val = I915_READ(FDI_TX_CTL(pipe));
1139 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1140 }
1141
1142 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1143 enum pipe pipe, bool state)
1144 {
1145 u32 val;
1146 bool cur_state;
1147
1148 val = I915_READ(FDI_RX_CTL(pipe));
1149 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1150 I915_STATE_WARN(cur_state != state,
1151 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1152 onoff(state), onoff(cur_state));
1153 }
1154
1155 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1156 {
1157 i915_reg_t pp_reg;
1158 u32 val;
1159 enum pipe panel_pipe = PIPE_A;
1160 bool locked = true;
1161
1162 if (WARN_ON(HAS_DDI(dev_priv)))
1163 return;
1164
1165 if (HAS_PCH_SPLIT(dev_priv)) {
1166 u32 port_sel;
1167
1168 pp_reg = PP_CONTROL(0);
1169 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1170
1171 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1172 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1173 panel_pipe = PIPE_B;
1174 /* XXX: else fix for eDP */
1175 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1176 /* presumably write lock depends on pipe, not port select */
1177 pp_reg = PP_CONTROL(pipe);
1178 panel_pipe = pipe;
1179 } else {
1180 pp_reg = PP_CONTROL(0);
1181 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1182 panel_pipe = PIPE_B;
1183 }
1184
1185 val = I915_READ(pp_reg);
1186 if (!(val & PANEL_POWER_ON) ||
1187 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1188 locked = false;
1189
1190 I915_STATE_WARN(panel_pipe == pipe && locked,
1191 "panel assertion failure, pipe %c regs locked\n",
1192 pipe_name(pipe));
1193 }
1194
1195 static void assert_cursor(struct drm_i915_private *dev_priv,
1196 enum pipe pipe, bool state)
1197 {
1198 bool cur_state;
1199
1200 if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1201 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1202 else
1203 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1204
1205 I915_STATE_WARN(cur_state != state,
1206 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1207 pipe_name(pipe), onoff(state), onoff(cur_state));
1208 }
1209 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1210 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1211
1212 void assert_pipe(struct drm_i915_private *dev_priv,
1213 enum pipe pipe, bool state)
1214 {
1215 bool cur_state;
1216 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1217 pipe);
1218 enum intel_display_power_domain power_domain;
1219
1220 /* we keep both pipes enabled on 830 */
1221 if (IS_I830(dev_priv))
1222 state = true;
1223
1224 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1225 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1226 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1227 cur_state = !!(val & PIPECONF_ENABLE);
1228
1229 intel_display_power_put(dev_priv, power_domain);
1230 } else {
1231 cur_state = false;
1232 }
1233
1234 I915_STATE_WARN(cur_state != state,
1235 "pipe %c assertion failure (expected %s, current %s)\n",
1236 pipe_name(pipe), onoff(state), onoff(cur_state));
1237 }
1238
1239 static void assert_plane(struct drm_i915_private *dev_priv,
1240 enum plane plane, bool state)
1241 {
1242 u32 val;
1243 bool cur_state;
1244
1245 val = I915_READ(DSPCNTR(plane));
1246 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1247 I915_STATE_WARN(cur_state != state,
1248 "plane %c assertion failure (expected %s, current %s)\n",
1249 plane_name(plane), onoff(state), onoff(cur_state));
1250 }
1251
1252 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1253 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1254
1255 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1256 enum pipe pipe)
1257 {
1258 int i;
1259
1260 /* Primary planes are fixed to pipes on gen4+ */
1261 if (INTEL_GEN(dev_priv) >= 4) {
1262 u32 val = I915_READ(DSPCNTR(pipe));
1263 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1264 "plane %c assertion failure, should be disabled but not\n",
1265 plane_name(pipe));
1266 return;
1267 }
1268
1269 /* Need to check both planes against the pipe */
1270 for_each_pipe(dev_priv, i) {
1271 u32 val = I915_READ(DSPCNTR(i));
1272 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1273 DISPPLANE_SEL_PIPE_SHIFT;
1274 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1275 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1276 plane_name(i), pipe_name(pipe));
1277 }
1278 }
1279
1280 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1281 enum pipe pipe)
1282 {
1283 int sprite;
1284
1285 if (INTEL_GEN(dev_priv) >= 9) {
1286 for_each_sprite(dev_priv, pipe, sprite) {
1287 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1288 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1289 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1290 sprite, pipe_name(pipe));
1291 }
1292 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1293 for_each_sprite(dev_priv, pipe, sprite) {
1294 u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1295 I915_STATE_WARN(val & SP_ENABLE,
1296 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1297 sprite_name(pipe, sprite), pipe_name(pipe));
1298 }
1299 } else if (INTEL_GEN(dev_priv) >= 7) {
1300 u32 val = I915_READ(SPRCTL(pipe));
1301 I915_STATE_WARN(val & SPRITE_ENABLE,
1302 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1303 plane_name(pipe), pipe_name(pipe));
1304 } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
1305 u32 val = I915_READ(DVSCNTR(pipe));
1306 I915_STATE_WARN(val & DVS_ENABLE,
1307 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1308 plane_name(pipe), pipe_name(pipe));
1309 }
1310 }
1311
1312 static void assert_vblank_disabled(struct drm_crtc *crtc)
1313 {
1314 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1315 drm_crtc_vblank_put(crtc);
1316 }
1317
1318 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1319 enum pipe pipe)
1320 {
1321 u32 val;
1322 bool enabled;
1323
1324 val = I915_READ(PCH_TRANSCONF(pipe));
1325 enabled = !!(val & TRANS_ENABLE);
1326 I915_STATE_WARN(enabled,
1327 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328 pipe_name(pipe));
1329 }
1330
1331 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332 enum pipe pipe, u32 port_sel, u32 val)
1333 {
1334 if ((val & DP_PORT_EN) == 0)
1335 return false;
1336
1337 if (HAS_PCH_CPT(dev_priv)) {
1338 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1339 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1340 return false;
1341 } else if (IS_CHERRYVIEW(dev_priv)) {
1342 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1343 return false;
1344 } else {
1345 if ((val & DP_PIPE_MASK) != (pipe << 30))
1346 return false;
1347 }
1348 return true;
1349 }
1350
1351 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1352 enum pipe pipe, u32 val)
1353 {
1354 if ((val & SDVO_ENABLE) == 0)
1355 return false;
1356
1357 if (HAS_PCH_CPT(dev_priv)) {
1358 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1359 return false;
1360 } else if (IS_CHERRYVIEW(dev_priv)) {
1361 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1362 return false;
1363 } else {
1364 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1365 return false;
1366 }
1367 return true;
1368 }
1369
1370 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1371 enum pipe pipe, u32 val)
1372 {
1373 if ((val & LVDS_PORT_EN) == 0)
1374 return false;
1375
1376 if (HAS_PCH_CPT(dev_priv)) {
1377 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1378 return false;
1379 } else {
1380 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1381 return false;
1382 }
1383 return true;
1384 }
1385
1386 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1387 enum pipe pipe, u32 val)
1388 {
1389 if ((val & ADPA_DAC_ENABLE) == 0)
1390 return false;
1391 if (HAS_PCH_CPT(dev_priv)) {
1392 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1393 return false;
1394 } else {
1395 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1396 return false;
1397 }
1398 return true;
1399 }
1400
1401 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1402 enum pipe pipe, i915_reg_t reg,
1403 u32 port_sel)
1404 {
1405 u32 val = I915_READ(reg);
1406 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1407 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1408 i915_mmio_reg_offset(reg), pipe_name(pipe));
1409
1410 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1411 && (val & DP_PIPEB_SELECT),
1412 "IBX PCH dp port still using transcoder B\n");
1413 }
1414
1415 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1416 enum pipe pipe, i915_reg_t reg)
1417 {
1418 u32 val = I915_READ(reg);
1419 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1420 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1421 i915_mmio_reg_offset(reg), pipe_name(pipe));
1422
1423 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1424 && (val & SDVO_PIPE_B_SELECT),
1425 "IBX PCH hdmi port still using transcoder B\n");
1426 }
1427
1428 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1429 enum pipe pipe)
1430 {
1431 u32 val;
1432
1433 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1434 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1435 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1436
1437 val = I915_READ(PCH_ADPA);
1438 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1439 "PCH VGA enabled on transcoder %c, should be disabled\n",
1440 pipe_name(pipe));
1441
1442 val = I915_READ(PCH_LVDS);
1443 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1444 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1445 pipe_name(pipe));
1446
1447 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1448 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1449 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1450 }
1451
1452 static void _vlv_enable_pll(struct intel_crtc *crtc,
1453 const struct intel_crtc_state *pipe_config)
1454 {
1455 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1456 enum pipe pipe = crtc->pipe;
1457
1458 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1459 POSTING_READ(DPLL(pipe));
1460 udelay(150);
1461
1462 if (intel_wait_for_register(dev_priv,
1463 DPLL(pipe),
1464 DPLL_LOCK_VLV,
1465 DPLL_LOCK_VLV,
1466 1))
1467 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1468 }
1469
1470 static void vlv_enable_pll(struct intel_crtc *crtc,
1471 const struct intel_crtc_state *pipe_config)
1472 {
1473 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1474 enum pipe pipe = crtc->pipe;
1475
1476 assert_pipe_disabled(dev_priv, pipe);
1477
1478 /* PLL is protected by panel, make sure we can write it */
1479 assert_panel_unlocked(dev_priv, pipe);
1480
1481 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1482 _vlv_enable_pll(crtc, pipe_config);
1483
1484 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1485 POSTING_READ(DPLL_MD(pipe));
1486 }
1487
1488
1489 static void _chv_enable_pll(struct intel_crtc *crtc,
1490 const struct intel_crtc_state *pipe_config)
1491 {
1492 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1493 enum pipe pipe = crtc->pipe;
1494 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1495 u32 tmp;
1496
1497 mutex_lock(&dev_priv->sb_lock);
1498
1499 /* Enable back the 10bit clock to display controller */
1500 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1501 tmp |= DPIO_DCLKP_EN;
1502 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1503
1504 mutex_unlock(&dev_priv->sb_lock);
1505
1506 /*
1507 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1508 */
1509 udelay(1);
1510
1511 /* Enable PLL */
1512 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1513
1514 /* Check PLL is locked */
1515 if (intel_wait_for_register(dev_priv,
1516 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1517 1))
1518 DRM_ERROR("PLL %d failed to lock\n", pipe);
1519 }
1520
1521 static void chv_enable_pll(struct intel_crtc *crtc,
1522 const struct intel_crtc_state *pipe_config)
1523 {
1524 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1525 enum pipe pipe = crtc->pipe;
1526
1527 assert_pipe_disabled(dev_priv, pipe);
1528
1529 /* PLL is protected by panel, make sure we can write it */
1530 assert_panel_unlocked(dev_priv, pipe);
1531
1532 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1533 _chv_enable_pll(crtc, pipe_config);
1534
1535 if (pipe != PIPE_A) {
1536 /*
1537 * WaPixelRepeatModeFixForC0:chv
1538 *
1539 * DPLLCMD is AWOL. Use chicken bits to propagate
1540 * the value from DPLLBMD to either pipe B or C.
1541 */
1542 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1543 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1544 I915_WRITE(CBR4_VLV, 0);
1545 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1546
1547 /*
1548 * DPLLB VGA mode also seems to cause problems.
1549 * We should always have it disabled.
1550 */
1551 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1552 } else {
1553 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1554 POSTING_READ(DPLL_MD(pipe));
1555 }
1556 }
1557
1558 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1559 {
1560 struct intel_crtc *crtc;
1561 int count = 0;
1562
1563 for_each_intel_crtc(&dev_priv->drm, crtc) {
1564 count += crtc->base.state->active &&
1565 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1566 }
1567
1568 return count;
1569 }
1570
1571 static void i9xx_enable_pll(struct intel_crtc *crtc)
1572 {
1573 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1574 i915_reg_t reg = DPLL(crtc->pipe);
1575 u32 dpll = crtc->config->dpll_hw_state.dpll;
1576 int i;
1577
1578 assert_pipe_disabled(dev_priv, crtc->pipe);
1579
1580 /* PLL is protected by panel, make sure we can write it */
1581 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1582 assert_panel_unlocked(dev_priv, crtc->pipe);
1583
1584 /* Enable DVO 2x clock on both PLLs if necessary */
1585 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1586 /*
1587 * It appears to be important that we don't enable this
1588 * for the current pipe before otherwise configuring the
1589 * PLL. No idea how this should be handled if multiple
1590 * DVO outputs are enabled simultaneosly.
1591 */
1592 dpll |= DPLL_DVO_2X_MODE;
1593 I915_WRITE(DPLL(!crtc->pipe),
1594 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1595 }
1596
1597 /*
1598 * Apparently we need to have VGA mode enabled prior to changing
1599 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1600 * dividers, even though the register value does change.
1601 */
1602 I915_WRITE(reg, 0);
1603
1604 I915_WRITE(reg, dpll);
1605
1606 /* Wait for the clocks to stabilize. */
1607 POSTING_READ(reg);
1608 udelay(150);
1609
1610 if (INTEL_GEN(dev_priv) >= 4) {
1611 I915_WRITE(DPLL_MD(crtc->pipe),
1612 crtc->config->dpll_hw_state.dpll_md);
1613 } else {
1614 /* The pixel multiplier can only be updated once the
1615 * DPLL is enabled and the clocks are stable.
1616 *
1617 * So write it again.
1618 */
1619 I915_WRITE(reg, dpll);
1620 }
1621
1622 /* We do this three times for luck */
1623 for (i = 0; i < 3; i++) {
1624 I915_WRITE(reg, dpll);
1625 POSTING_READ(reg);
1626 udelay(150); /* wait for warmup */
1627 }
1628 }
1629
1630 /**
1631 * i9xx_disable_pll - disable a PLL
1632 * @dev_priv: i915 private structure
1633 * @pipe: pipe PLL to disable
1634 *
1635 * Disable the PLL for @pipe, making sure the pipe is off first.
1636 *
1637 * Note! This is for pre-ILK only.
1638 */
1639 static void i9xx_disable_pll(struct intel_crtc *crtc)
1640 {
1641 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1642 enum pipe pipe = crtc->pipe;
1643
1644 /* Disable DVO 2x clock on both PLLs if necessary */
1645 if (IS_I830(dev_priv) &&
1646 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1647 !intel_num_dvo_pipes(dev_priv)) {
1648 I915_WRITE(DPLL(PIPE_B),
1649 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1650 I915_WRITE(DPLL(PIPE_A),
1651 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1652 }
1653
1654 /* Don't disable pipe or pipe PLLs if needed */
1655 if (IS_I830(dev_priv))
1656 return;
1657
1658 /* Make sure the pipe isn't still relying on us */
1659 assert_pipe_disabled(dev_priv, pipe);
1660
1661 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1662 POSTING_READ(DPLL(pipe));
1663 }
1664
1665 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1666 {
1667 u32 val;
1668
1669 /* Make sure the pipe isn't still relying on us */
1670 assert_pipe_disabled(dev_priv, pipe);
1671
1672 val = DPLL_INTEGRATED_REF_CLK_VLV |
1673 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1674 if (pipe != PIPE_A)
1675 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1676
1677 I915_WRITE(DPLL(pipe), val);
1678 POSTING_READ(DPLL(pipe));
1679 }
1680
1681 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1682 {
1683 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1684 u32 val;
1685
1686 /* Make sure the pipe isn't still relying on us */
1687 assert_pipe_disabled(dev_priv, pipe);
1688
1689 val = DPLL_SSC_REF_CLK_CHV |
1690 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1691 if (pipe != PIPE_A)
1692 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1693
1694 I915_WRITE(DPLL(pipe), val);
1695 POSTING_READ(DPLL(pipe));
1696
1697 mutex_lock(&dev_priv->sb_lock);
1698
1699 /* Disable 10bit clock to display controller */
1700 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1701 val &= ~DPIO_DCLKP_EN;
1702 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1703
1704 mutex_unlock(&dev_priv->sb_lock);
1705 }
1706
1707 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1708 struct intel_digital_port *dport,
1709 unsigned int expected_mask)
1710 {
1711 u32 port_mask;
1712 i915_reg_t dpll_reg;
1713
1714 switch (dport->port) {
1715 case PORT_B:
1716 port_mask = DPLL_PORTB_READY_MASK;
1717 dpll_reg = DPLL(0);
1718 break;
1719 case PORT_C:
1720 port_mask = DPLL_PORTC_READY_MASK;
1721 dpll_reg = DPLL(0);
1722 expected_mask <<= 4;
1723 break;
1724 case PORT_D:
1725 port_mask = DPLL_PORTD_READY_MASK;
1726 dpll_reg = DPIO_PHY_STATUS;
1727 break;
1728 default:
1729 BUG();
1730 }
1731
1732 if (intel_wait_for_register(dev_priv,
1733 dpll_reg, port_mask, expected_mask,
1734 1000))
1735 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1736 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1737 }
1738
1739 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1740 enum pipe pipe)
1741 {
1742 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1743 pipe);
1744 i915_reg_t reg;
1745 uint32_t val, pipeconf_val;
1746
1747 /* Make sure PCH DPLL is enabled */
1748 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1749
1750 /* FDI must be feeding us bits for PCH ports */
1751 assert_fdi_tx_enabled(dev_priv, pipe);
1752 assert_fdi_rx_enabled(dev_priv, pipe);
1753
1754 if (HAS_PCH_CPT(dev_priv)) {
1755 /* Workaround: Set the timing override bit before enabling the
1756 * pch transcoder. */
1757 reg = TRANS_CHICKEN2(pipe);
1758 val = I915_READ(reg);
1759 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1760 I915_WRITE(reg, val);
1761 }
1762
1763 reg = PCH_TRANSCONF(pipe);
1764 val = I915_READ(reg);
1765 pipeconf_val = I915_READ(PIPECONF(pipe));
1766
1767 if (HAS_PCH_IBX(dev_priv)) {
1768 /*
1769 * Make the BPC in transcoder be consistent with
1770 * that in pipeconf reg. For HDMI we must use 8bpc
1771 * here for both 8bpc and 12bpc.
1772 */
1773 val &= ~PIPECONF_BPC_MASK;
1774 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1775 val |= PIPECONF_8BPC;
1776 else
1777 val |= pipeconf_val & PIPECONF_BPC_MASK;
1778 }
1779
1780 val &= ~TRANS_INTERLACE_MASK;
1781 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1782 if (HAS_PCH_IBX(dev_priv) &&
1783 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1784 val |= TRANS_LEGACY_INTERLACED_ILK;
1785 else
1786 val |= TRANS_INTERLACED;
1787 else
1788 val |= TRANS_PROGRESSIVE;
1789
1790 I915_WRITE(reg, val | TRANS_ENABLE);
1791 if (intel_wait_for_register(dev_priv,
1792 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1793 100))
1794 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1795 }
1796
1797 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1798 enum transcoder cpu_transcoder)
1799 {
1800 u32 val, pipeconf_val;
1801
1802 /* FDI must be feeding us bits for PCH ports */
1803 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1804 assert_fdi_rx_enabled(dev_priv, PIPE_A);
1805
1806 /* Workaround: set timing override bit. */
1807 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1808 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1809 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1810
1811 val = TRANS_ENABLE;
1812 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1813
1814 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1815 PIPECONF_INTERLACED_ILK)
1816 val |= TRANS_INTERLACED;
1817 else
1818 val |= TRANS_PROGRESSIVE;
1819
1820 I915_WRITE(LPT_TRANSCONF, val);
1821 if (intel_wait_for_register(dev_priv,
1822 LPT_TRANSCONF,
1823 TRANS_STATE_ENABLE,
1824 TRANS_STATE_ENABLE,
1825 100))
1826 DRM_ERROR("Failed to enable PCH transcoder\n");
1827 }
1828
1829 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1830 enum pipe pipe)
1831 {
1832 i915_reg_t reg;
1833 uint32_t val;
1834
1835 /* FDI relies on the transcoder */
1836 assert_fdi_tx_disabled(dev_priv, pipe);
1837 assert_fdi_rx_disabled(dev_priv, pipe);
1838
1839 /* Ports must be off as well */
1840 assert_pch_ports_disabled(dev_priv, pipe);
1841
1842 reg = PCH_TRANSCONF(pipe);
1843 val = I915_READ(reg);
1844 val &= ~TRANS_ENABLE;
1845 I915_WRITE(reg, val);
1846 /* wait for PCH transcoder off, transcoder state */
1847 if (intel_wait_for_register(dev_priv,
1848 reg, TRANS_STATE_ENABLE, 0,
1849 50))
1850 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1851
1852 if (HAS_PCH_CPT(dev_priv)) {
1853 /* Workaround: Clear the timing override chicken bit again. */
1854 reg = TRANS_CHICKEN2(pipe);
1855 val = I915_READ(reg);
1856 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1857 I915_WRITE(reg, val);
1858 }
1859 }
1860
1861 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1862 {
1863 u32 val;
1864
1865 val = I915_READ(LPT_TRANSCONF);
1866 val &= ~TRANS_ENABLE;
1867 I915_WRITE(LPT_TRANSCONF, val);
1868 /* wait for PCH transcoder off, transcoder state */
1869 if (intel_wait_for_register(dev_priv,
1870 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1871 50))
1872 DRM_ERROR("Failed to disable PCH transcoder\n");
1873
1874 /* Workaround: clear timing override bit. */
1875 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1876 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1877 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1878 }
1879
1880 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1881 {
1882 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1883
1884 WARN_ON(!crtc->config->has_pch_encoder);
1885
1886 if (HAS_PCH_LPT(dev_priv))
1887 return PIPE_A;
1888 else
1889 return crtc->pipe;
1890 }
1891
1892 /**
1893 * intel_enable_pipe - enable a pipe, asserting requirements
1894 * @crtc: crtc responsible for the pipe
1895 *
1896 * Enable @crtc's pipe, making sure that various hardware specific requirements
1897 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1898 */
1899 static void intel_enable_pipe(struct intel_crtc *crtc)
1900 {
1901 struct drm_device *dev = crtc->base.dev;
1902 struct drm_i915_private *dev_priv = to_i915(dev);
1903 enum pipe pipe = crtc->pipe;
1904 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1905 i915_reg_t reg;
1906 u32 val;
1907
1908 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1909
1910 assert_planes_disabled(dev_priv, pipe);
1911 assert_cursor_disabled(dev_priv, pipe);
1912 assert_sprites_disabled(dev_priv, pipe);
1913
1914 /*
1915 * A pipe without a PLL won't actually be able to drive bits from
1916 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1917 * need the check.
1918 */
1919 if (HAS_GMCH_DISPLAY(dev_priv)) {
1920 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1921 assert_dsi_pll_enabled(dev_priv);
1922 else
1923 assert_pll_enabled(dev_priv, pipe);
1924 } else {
1925 if (crtc->config->has_pch_encoder) {
1926 /* if driving the PCH, we need FDI enabled */
1927 assert_fdi_rx_pll_enabled(dev_priv,
1928 intel_crtc_pch_transcoder(crtc));
1929 assert_fdi_tx_pll_enabled(dev_priv,
1930 (enum pipe) cpu_transcoder);
1931 }
1932 /* FIXME: assert CPU port conditions for SNB+ */
1933 }
1934
1935 reg = PIPECONF(cpu_transcoder);
1936 val = I915_READ(reg);
1937 if (val & PIPECONF_ENABLE) {
1938 /* we keep both pipes enabled on 830 */
1939 WARN_ON(!IS_I830(dev_priv));
1940 return;
1941 }
1942
1943 I915_WRITE(reg, val | PIPECONF_ENABLE);
1944 POSTING_READ(reg);
1945
1946 /*
1947 * Until the pipe starts DSL will read as 0, which would cause
1948 * an apparent vblank timestamp jump, which messes up also the
1949 * frame count when it's derived from the timestamps. So let's
1950 * wait for the pipe to start properly before we call
1951 * drm_crtc_vblank_on()
1952 */
1953 if (dev->max_vblank_count == 0 &&
1954 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1955 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1956 }
1957
1958 /**
1959 * intel_disable_pipe - disable a pipe, asserting requirements
1960 * @crtc: crtc whose pipes is to be disabled
1961 *
1962 * Disable the pipe of @crtc, making sure that various hardware
1963 * specific requirements are met, if applicable, e.g. plane
1964 * disabled, panel fitter off, etc.
1965 *
1966 * Will wait until the pipe has shut down before returning.
1967 */
1968 static void intel_disable_pipe(struct intel_crtc *crtc)
1969 {
1970 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1971 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1972 enum pipe pipe = crtc->pipe;
1973 i915_reg_t reg;
1974 u32 val;
1975
1976 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1977
1978 /*
1979 * Make sure planes won't keep trying to pump pixels to us,
1980 * or we might hang the display.
1981 */
1982 assert_planes_disabled(dev_priv, pipe);
1983 assert_cursor_disabled(dev_priv, pipe);
1984 assert_sprites_disabled(dev_priv, pipe);
1985
1986 reg = PIPECONF(cpu_transcoder);
1987 val = I915_READ(reg);
1988 if ((val & PIPECONF_ENABLE) == 0)
1989 return;
1990
1991 /*
1992 * Double wide has implications for planes
1993 * so best keep it disabled when not needed.
1994 */
1995 if (crtc->config->double_wide)
1996 val &= ~PIPECONF_DOUBLE_WIDE;
1997
1998 /* Don't disable pipe or pipe PLLs if needed */
1999 if (!IS_I830(dev_priv))
2000 val &= ~PIPECONF_ENABLE;
2001
2002 I915_WRITE(reg, val);
2003 if ((val & PIPECONF_ENABLE) == 0)
2004 intel_wait_for_pipe_off(crtc);
2005 }
2006
2007 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2008 {
2009 return IS_GEN2(dev_priv) ? 2048 : 4096;
2010 }
2011
2012 static unsigned int
2013 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
2014 {
2015 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2016 unsigned int cpp = fb->format->cpp[plane];
2017
2018 switch (fb->modifier) {
2019 case DRM_FORMAT_MOD_LINEAR:
2020 return cpp;
2021 case I915_FORMAT_MOD_X_TILED:
2022 if (IS_GEN2(dev_priv))
2023 return 128;
2024 else
2025 return 512;
2026 case I915_FORMAT_MOD_Y_TILED_CCS:
2027 if (plane == 1)
2028 return 128;
2029 /* fall through */
2030 case I915_FORMAT_MOD_Y_TILED:
2031 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2032 return 128;
2033 else
2034 return 512;
2035 case I915_FORMAT_MOD_Yf_TILED_CCS:
2036 if (plane == 1)
2037 return 128;
2038 /* fall through */
2039 case I915_FORMAT_MOD_Yf_TILED:
2040 switch (cpp) {
2041 case 1:
2042 return 64;
2043 case 2:
2044 case 4:
2045 return 128;
2046 case 8:
2047 case 16:
2048 return 256;
2049 default:
2050 MISSING_CASE(cpp);
2051 return cpp;
2052 }
2053 break;
2054 default:
2055 MISSING_CASE(fb->modifier);
2056 return cpp;
2057 }
2058 }
2059
2060 static unsigned int
2061 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2062 {
2063 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
2064 return 1;
2065 else
2066 return intel_tile_size(to_i915(fb->dev)) /
2067 intel_tile_width_bytes(fb, plane);
2068 }
2069
2070 /* Return the tile dimensions in pixel units */
2071 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2072 unsigned int *tile_width,
2073 unsigned int *tile_height)
2074 {
2075 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2076 unsigned int cpp = fb->format->cpp[plane];
2077
2078 *tile_width = tile_width_bytes / cpp;
2079 *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2080 }
2081
2082 unsigned int
2083 intel_fb_align_height(const struct drm_framebuffer *fb,
2084 int plane, unsigned int height)
2085 {
2086 unsigned int tile_height = intel_tile_height(fb, plane);
2087
2088 return ALIGN(height, tile_height);
2089 }
2090
2091 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2092 {
2093 unsigned int size = 0;
2094 int i;
2095
2096 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2097 size += rot_info->plane[i].width * rot_info->plane[i].height;
2098
2099 return size;
2100 }
2101
2102 static void
2103 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2104 const struct drm_framebuffer *fb,
2105 unsigned int rotation)
2106 {
2107 view->type = I915_GGTT_VIEW_NORMAL;
2108 if (drm_rotation_90_or_270(rotation)) {
2109 view->type = I915_GGTT_VIEW_ROTATED;
2110 view->rotated = to_intel_framebuffer(fb)->rot_info;
2111 }
2112 }
2113
2114 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2115 {
2116 if (IS_I830(dev_priv))
2117 return 16 * 1024;
2118 else if (IS_I85X(dev_priv))
2119 return 256;
2120 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2121 return 32;
2122 else
2123 return 4 * 1024;
2124 }
2125
2126 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2127 {
2128 if (INTEL_INFO(dev_priv)->gen >= 9)
2129 return 256 * 1024;
2130 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2131 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2132 return 128 * 1024;
2133 else if (INTEL_INFO(dev_priv)->gen >= 4)
2134 return 4 * 1024;
2135 else
2136 return 0;
2137 }
2138
2139 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2140 int plane)
2141 {
2142 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2143
2144 /* AUX_DIST needs only 4K alignment */
2145 if (plane == 1)
2146 return 4096;
2147
2148 switch (fb->modifier) {
2149 case DRM_FORMAT_MOD_LINEAR:
2150 return intel_linear_alignment(dev_priv);
2151 case I915_FORMAT_MOD_X_TILED:
2152 if (INTEL_GEN(dev_priv) >= 9)
2153 return 256 * 1024;
2154 return 0;
2155 case I915_FORMAT_MOD_Y_TILED_CCS:
2156 case I915_FORMAT_MOD_Yf_TILED_CCS:
2157 case I915_FORMAT_MOD_Y_TILED:
2158 case I915_FORMAT_MOD_Yf_TILED:
2159 return 1 * 1024 * 1024;
2160 default:
2161 MISSING_CASE(fb->modifier);
2162 return 0;
2163 }
2164 }
2165
2166 struct i915_vma *
2167 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2168 {
2169 struct drm_device *dev = fb->dev;
2170 struct drm_i915_private *dev_priv = to_i915(dev);
2171 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2172 struct i915_ggtt_view view;
2173 struct i915_vma *vma;
2174 u32 alignment;
2175
2176 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2177
2178 alignment = intel_surf_alignment(fb, 0);
2179
2180 intel_fill_fb_ggtt_view(&view, fb, rotation);
2181
2182 /* Note that the w/a also requires 64 PTE of padding following the
2183 * bo. We currently fill all unused PTE with the shadow page and so
2184 * we should always have valid PTE following the scanout preventing
2185 * the VT-d warning.
2186 */
2187 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2188 alignment = 256 * 1024;
2189
2190 /*
2191 * Global gtt pte registers are special registers which actually forward
2192 * writes to a chunk of system memory. Which means that there is no risk
2193 * that the register values disappear as soon as we call
2194 * intel_runtime_pm_put(), so it is correct to wrap only the
2195 * pin/unpin/fence and not more.
2196 */
2197 intel_runtime_pm_get(dev_priv);
2198
2199 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2200
2201 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2202 if (IS_ERR(vma))
2203 goto err;
2204
2205 if (i915_vma_is_map_and_fenceable(vma)) {
2206 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2207 * fence, whereas 965+ only requires a fence if using
2208 * framebuffer compression. For simplicity, we always, when
2209 * possible, install a fence as the cost is not that onerous.
2210 *
2211 * If we fail to fence the tiled scanout, then either the
2212 * modeset will reject the change (which is highly unlikely as
2213 * the affected systems, all but one, do not have unmappable
2214 * space) or we will not be able to enable full powersaving
2215 * techniques (also likely not to apply due to various limits
2216 * FBC and the like impose on the size of the buffer, which
2217 * presumably we violated anyway with this unmappable buffer).
2218 * Anyway, it is presumably better to stumble onwards with
2219 * something and try to run the system in a "less than optimal"
2220 * mode that matches the user configuration.
2221 */
2222 if (i915_vma_get_fence(vma) == 0)
2223 i915_vma_pin_fence(vma);
2224 }
2225
2226 i915_vma_get(vma);
2227 err:
2228 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2229
2230 intel_runtime_pm_put(dev_priv);
2231 return vma;
2232 }
2233
2234 void intel_unpin_fb_vma(struct i915_vma *vma)
2235 {
2236 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2237
2238 i915_vma_unpin_fence(vma);
2239 i915_gem_object_unpin_from_display_plane(vma);
2240 i915_vma_put(vma);
2241 }
2242
2243 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2244 unsigned int rotation)
2245 {
2246 if (drm_rotation_90_or_270(rotation))
2247 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2248 else
2249 return fb->pitches[plane];
2250 }
2251
2252 /*
2253 * Convert the x/y offsets into a linear offset.
2254 * Only valid with 0/180 degree rotation, which is fine since linear
2255 * offset is only used with linear buffers on pre-hsw and tiled buffers
2256 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2257 */
2258 u32 intel_fb_xy_to_linear(int x, int y,
2259 const struct intel_plane_state *state,
2260 int plane)
2261 {
2262 const struct drm_framebuffer *fb = state->base.fb;
2263 unsigned int cpp = fb->format->cpp[plane];
2264 unsigned int pitch = fb->pitches[plane];
2265
2266 return y * pitch + x * cpp;
2267 }
2268
2269 /*
2270 * Add the x/y offsets derived from fb->offsets[] to the user
2271 * specified plane src x/y offsets. The resulting x/y offsets
2272 * specify the start of scanout from the beginning of the gtt mapping.
2273 */
2274 void intel_add_fb_offsets(int *x, int *y,
2275 const struct intel_plane_state *state,
2276 int plane)
2277
2278 {
2279 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2280 unsigned int rotation = state->base.rotation;
2281
2282 if (drm_rotation_90_or_270(rotation)) {
2283 *x += intel_fb->rotated[plane].x;
2284 *y += intel_fb->rotated[plane].y;
2285 } else {
2286 *x += intel_fb->normal[plane].x;
2287 *y += intel_fb->normal[plane].y;
2288 }
2289 }
2290
2291 static u32 __intel_adjust_tile_offset(int *x, int *y,
2292 unsigned int tile_width,
2293 unsigned int tile_height,
2294 unsigned int tile_size,
2295 unsigned int pitch_tiles,
2296 u32 old_offset,
2297 u32 new_offset)
2298 {
2299 unsigned int pitch_pixels = pitch_tiles * tile_width;
2300 unsigned int tiles;
2301
2302 WARN_ON(old_offset & (tile_size - 1));
2303 WARN_ON(new_offset & (tile_size - 1));
2304 WARN_ON(new_offset > old_offset);
2305
2306 tiles = (old_offset - new_offset) / tile_size;
2307
2308 *y += tiles / pitch_tiles * tile_height;
2309 *x += tiles % pitch_tiles * tile_width;
2310
2311 /* minimize x in case it got needlessly big */
2312 *y += *x / pitch_pixels * tile_height;
2313 *x %= pitch_pixels;
2314
2315 return new_offset;
2316 }
2317
2318 static u32 _intel_adjust_tile_offset(int *x, int *y,
2319 const struct drm_framebuffer *fb, int plane,
2320 unsigned int rotation,
2321 u32 old_offset, u32 new_offset)
2322 {
2323 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2324 unsigned int cpp = fb->format->cpp[plane];
2325 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2326
2327 WARN_ON(new_offset > old_offset);
2328
2329 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2330 unsigned int tile_size, tile_width, tile_height;
2331 unsigned int pitch_tiles;
2332
2333 tile_size = intel_tile_size(dev_priv);
2334 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2335
2336 if (drm_rotation_90_or_270(rotation)) {
2337 pitch_tiles = pitch / tile_height;
2338 swap(tile_width, tile_height);
2339 } else {
2340 pitch_tiles = pitch / (tile_width * cpp);
2341 }
2342
2343 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2344 tile_size, pitch_tiles,
2345 old_offset, new_offset);
2346 } else {
2347 old_offset += *y * pitch + *x * cpp;
2348
2349 *y = (old_offset - new_offset) / pitch;
2350 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2351 }
2352
2353 return new_offset;
2354 }
2355
2356 /*
2357 * Adjust the tile offset by moving the difference into
2358 * the x/y offsets.
2359 */
2360 static u32 intel_adjust_tile_offset(int *x, int *y,
2361 const struct intel_plane_state *state, int plane,
2362 u32 old_offset, u32 new_offset)
2363 {
2364 return _intel_adjust_tile_offset(x, y, state->base.fb, plane,
2365 state->base.rotation,
2366 old_offset, new_offset);
2367 }
2368
2369 /*
2370 * Computes the linear offset to the base tile and adjusts
2371 * x, y. bytes per pixel is assumed to be a power-of-two.
2372 *
2373 * In the 90/270 rotated case, x and y are assumed
2374 * to be already rotated to match the rotated GTT view, and
2375 * pitch is the tile_height aligned framebuffer height.
2376 *
2377 * This function is used when computing the derived information
2378 * under intel_framebuffer, so using any of that information
2379 * here is not allowed. Anything under drm_framebuffer can be
2380 * used. This is why the user has to pass in the pitch since it
2381 * is specified in the rotated orientation.
2382 */
2383 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2384 int *x, int *y,
2385 const struct drm_framebuffer *fb, int plane,
2386 unsigned int pitch,
2387 unsigned int rotation,
2388 u32 alignment)
2389 {
2390 uint64_t fb_modifier = fb->modifier;
2391 unsigned int cpp = fb->format->cpp[plane];
2392 u32 offset, offset_aligned;
2393
2394 if (alignment)
2395 alignment--;
2396
2397 if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2398 unsigned int tile_size, tile_width, tile_height;
2399 unsigned int tile_rows, tiles, pitch_tiles;
2400
2401 tile_size = intel_tile_size(dev_priv);
2402 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2403
2404 if (drm_rotation_90_or_270(rotation)) {
2405 pitch_tiles = pitch / tile_height;
2406 swap(tile_width, tile_height);
2407 } else {
2408 pitch_tiles = pitch / (tile_width * cpp);
2409 }
2410
2411 tile_rows = *y / tile_height;
2412 *y %= tile_height;
2413
2414 tiles = *x / tile_width;
2415 *x %= tile_width;
2416
2417 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2418 offset_aligned = offset & ~alignment;
2419
2420 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2421 tile_size, pitch_tiles,
2422 offset, offset_aligned);
2423 } else {
2424 offset = *y * pitch + *x * cpp;
2425 offset_aligned = offset & ~alignment;
2426
2427 *y = (offset & alignment) / pitch;
2428 *x = ((offset & alignment) - *y * pitch) / cpp;
2429 }
2430
2431 return offset_aligned;
2432 }
2433
2434 u32 intel_compute_tile_offset(int *x, int *y,
2435 const struct intel_plane_state *state,
2436 int plane)
2437 {
2438 struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2439 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2440 const struct drm_framebuffer *fb = state->base.fb;
2441 unsigned int rotation = state->base.rotation;
2442 int pitch = intel_fb_pitch(fb, plane, rotation);
2443 u32 alignment;
2444
2445 if (intel_plane->id == PLANE_CURSOR)
2446 alignment = intel_cursor_alignment(dev_priv);
2447 else
2448 alignment = intel_surf_alignment(fb, plane);
2449
2450 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2451 rotation, alignment);
2452 }
2453
2454 /* Convert the fb->offset[] into x/y offsets */
2455 static int intel_fb_offset_to_xy(int *x, int *y,
2456 const struct drm_framebuffer *fb, int plane)
2457 {
2458 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2459
2460 if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2461 fb->offsets[plane] % intel_tile_size(dev_priv))
2462 return -EINVAL;
2463
2464 *x = 0;
2465 *y = 0;
2466
2467 _intel_adjust_tile_offset(x, y,
2468 fb, plane, DRM_MODE_ROTATE_0,
2469 fb->offsets[plane], 0);
2470
2471 return 0;
2472 }
2473
2474 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2475 {
2476 switch (fb_modifier) {
2477 case I915_FORMAT_MOD_X_TILED:
2478 return I915_TILING_X;
2479 case I915_FORMAT_MOD_Y_TILED:
2480 case I915_FORMAT_MOD_Y_TILED_CCS:
2481 return I915_TILING_Y;
2482 default:
2483 return I915_TILING_NONE;
2484 }
2485 }
2486
2487 static const struct drm_format_info ccs_formats[] = {
2488 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2489 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2490 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2491 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2492 };
2493
2494 static const struct drm_format_info *
2495 lookup_format_info(const struct drm_format_info formats[],
2496 int num_formats, u32 format)
2497 {
2498 int i;
2499
2500 for (i = 0; i < num_formats; i++) {
2501 if (formats[i].format == format)
2502 return &formats[i];
2503 }
2504
2505 return NULL;
2506 }
2507
2508 static const struct drm_format_info *
2509 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2510 {
2511 switch (cmd->modifier[0]) {
2512 case I915_FORMAT_MOD_Y_TILED_CCS:
2513 case I915_FORMAT_MOD_Yf_TILED_CCS:
2514 return lookup_format_info(ccs_formats,
2515 ARRAY_SIZE(ccs_formats),
2516 cmd->pixel_format);
2517 default:
2518 return NULL;
2519 }
2520 }
2521
2522 static int
2523 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2524 struct drm_framebuffer *fb)
2525 {
2526 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2527 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2528 u32 gtt_offset_rotated = 0;
2529 unsigned int max_size = 0;
2530 int i, num_planes = fb->format->num_planes;
2531 unsigned int tile_size = intel_tile_size(dev_priv);
2532
2533 for (i = 0; i < num_planes; i++) {
2534 unsigned int width, height;
2535 unsigned int cpp, size;
2536 u32 offset;
2537 int x, y;
2538 int ret;
2539
2540 cpp = fb->format->cpp[i];
2541 width = drm_framebuffer_plane_width(fb->width, fb, i);
2542 height = drm_framebuffer_plane_height(fb->height, fb, i);
2543
2544 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2545 if (ret) {
2546 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2547 i, fb->offsets[i]);
2548 return ret;
2549 }
2550
2551 if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2552 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) {
2553 int hsub = fb->format->hsub;
2554 int vsub = fb->format->vsub;
2555 int tile_width, tile_height;
2556 int main_x, main_y;
2557 int ccs_x, ccs_y;
2558
2559 intel_tile_dims(fb, i, &tile_width, &tile_height);
2560 tile_width *= hsub;
2561 tile_height *= vsub;
2562
2563 ccs_x = (x * hsub) % tile_width;
2564 ccs_y = (y * vsub) % tile_height;
2565 main_x = intel_fb->normal[0].x % tile_width;
2566 main_y = intel_fb->normal[0].y % tile_height;
2567
2568 /*
2569 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2570 * x/y offsets must match between CCS and the main surface.
2571 */
2572 if (main_x != ccs_x || main_y != ccs_y) {
2573 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2574 main_x, main_y,
2575 ccs_x, ccs_y,
2576 intel_fb->normal[0].x,
2577 intel_fb->normal[0].y,
2578 x, y);
2579 return -EINVAL;
2580 }
2581 }
2582
2583 /*
2584 * The fence (if used) is aligned to the start of the object
2585 * so having the framebuffer wrap around across the edge of the
2586 * fenced region doesn't really work. We have no API to configure
2587 * the fence start offset within the object (nor could we probably
2588 * on gen2/3). So it's just easier if we just require that the
2589 * fb layout agrees with the fence layout. We already check that the
2590 * fb stride matches the fence stride elsewhere.
2591 */
2592 if (i == 0 && i915_gem_object_is_tiled(intel_fb->obj) &&
2593 (x + width) * cpp > fb->pitches[i]) {
2594 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2595 i, fb->offsets[i]);
2596 return -EINVAL;
2597 }
2598
2599 /*
2600 * First pixel of the framebuffer from
2601 * the start of the normal gtt mapping.
2602 */
2603 intel_fb->normal[i].x = x;
2604 intel_fb->normal[i].y = y;
2605
2606 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2607 fb, i, fb->pitches[i],
2608 DRM_MODE_ROTATE_0, tile_size);
2609 offset /= tile_size;
2610
2611 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2612 unsigned int tile_width, tile_height;
2613 unsigned int pitch_tiles;
2614 struct drm_rect r;
2615
2616 intel_tile_dims(fb, i, &tile_width, &tile_height);
2617
2618 rot_info->plane[i].offset = offset;
2619 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2620 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2621 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2622
2623 intel_fb->rotated[i].pitch =
2624 rot_info->plane[i].height * tile_height;
2625
2626 /* how many tiles does this plane need */
2627 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2628 /*
2629 * If the plane isn't horizontally tile aligned,
2630 * we need one more tile.
2631 */
2632 if (x != 0)
2633 size++;
2634
2635 /* rotate the x/y offsets to match the GTT view */
2636 r.x1 = x;
2637 r.y1 = y;
2638 r.x2 = x + width;
2639 r.y2 = y + height;
2640 drm_rect_rotate(&r,
2641 rot_info->plane[i].width * tile_width,
2642 rot_info->plane[i].height * tile_height,
2643 DRM_MODE_ROTATE_270);
2644 x = r.x1;
2645 y = r.y1;
2646
2647 /* rotate the tile dimensions to match the GTT view */
2648 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2649 swap(tile_width, tile_height);
2650
2651 /*
2652 * We only keep the x/y offsets, so push all of the
2653 * gtt offset into the x/y offsets.
2654 */
2655 __intel_adjust_tile_offset(&x, &y,
2656 tile_width, tile_height,
2657 tile_size, pitch_tiles,
2658 gtt_offset_rotated * tile_size, 0);
2659
2660 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2661
2662 /*
2663 * First pixel of the framebuffer from
2664 * the start of the rotated gtt mapping.
2665 */
2666 intel_fb->rotated[i].x = x;
2667 intel_fb->rotated[i].y = y;
2668 } else {
2669 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2670 x * cpp, tile_size);
2671 }
2672
2673 /* how many tiles in total needed in the bo */
2674 max_size = max(max_size, offset + size);
2675 }
2676
2677 if (max_size * tile_size > intel_fb->obj->base.size) {
2678 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2679 max_size * tile_size, intel_fb->obj->base.size);
2680 return -EINVAL;
2681 }
2682
2683 return 0;
2684 }
2685
2686 static int i9xx_format_to_fourcc(int format)
2687 {
2688 switch (format) {
2689 case DISPPLANE_8BPP:
2690 return DRM_FORMAT_C8;
2691 case DISPPLANE_BGRX555:
2692 return DRM_FORMAT_XRGB1555;
2693 case DISPPLANE_BGRX565:
2694 return DRM_FORMAT_RGB565;
2695 default:
2696 case DISPPLANE_BGRX888:
2697 return DRM_FORMAT_XRGB8888;
2698 case DISPPLANE_RGBX888:
2699 return DRM_FORMAT_XBGR8888;
2700 case DISPPLANE_BGRX101010:
2701 return DRM_FORMAT_XRGB2101010;
2702 case DISPPLANE_RGBX101010:
2703 return DRM_FORMAT_XBGR2101010;
2704 }
2705 }
2706
2707 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2708 {
2709 switch (format) {
2710 case PLANE_CTL_FORMAT_RGB_565:
2711 return DRM_FORMAT_RGB565;
2712 default:
2713 case PLANE_CTL_FORMAT_XRGB_8888:
2714 if (rgb_order) {
2715 if (alpha)
2716 return DRM_FORMAT_ABGR8888;
2717 else
2718 return DRM_FORMAT_XBGR8888;
2719 } else {
2720 if (alpha)
2721 return DRM_FORMAT_ARGB8888;
2722 else
2723 return DRM_FORMAT_XRGB8888;
2724 }
2725 case PLANE_CTL_FORMAT_XRGB_2101010:
2726 if (rgb_order)
2727 return DRM_FORMAT_XBGR2101010;
2728 else
2729 return DRM_FORMAT_XRGB2101010;
2730 }
2731 }
2732
2733 static bool
2734 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2735 struct intel_initial_plane_config *plane_config)
2736 {
2737 struct drm_device *dev = crtc->base.dev;
2738 struct drm_i915_private *dev_priv = to_i915(dev);
2739 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2740 struct drm_i915_gem_object *obj = NULL;
2741 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2742 struct drm_framebuffer *fb = &plane_config->fb->base;
2743 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2744 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2745 PAGE_SIZE);
2746
2747 size_aligned -= base_aligned;
2748
2749 if (plane_config->size == 0)
2750 return false;
2751
2752 /* If the FB is too big, just don't use it since fbdev is not very
2753 * important and we should probably use that space with FBC or other
2754 * features. */
2755 if (size_aligned * 2 > ggtt->stolen_usable_size)
2756 return false;
2757
2758 mutex_lock(&dev->struct_mutex);
2759 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2760 base_aligned,
2761 base_aligned,
2762 size_aligned);
2763 mutex_unlock(&dev->struct_mutex);
2764 if (!obj)
2765 return false;
2766
2767 if (plane_config->tiling == I915_TILING_X)
2768 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2769
2770 mode_cmd.pixel_format = fb->format->format;
2771 mode_cmd.width = fb->width;
2772 mode_cmd.height = fb->height;
2773 mode_cmd.pitches[0] = fb->pitches[0];
2774 mode_cmd.modifier[0] = fb->modifier;
2775 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2776
2777 if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2778 DRM_DEBUG_KMS("intel fb init failed\n");
2779 goto out_unref_obj;
2780 }
2781
2782
2783 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2784 return true;
2785
2786 out_unref_obj:
2787 i915_gem_object_put(obj);
2788 return false;
2789 }
2790
2791 static void
2792 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2793 struct intel_plane_state *plane_state,
2794 bool visible)
2795 {
2796 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2797
2798 plane_state->base.visible = visible;
2799
2800 /* FIXME pre-g4x don't work like this */
2801 if (visible) {
2802 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2803 crtc_state->active_planes |= BIT(plane->id);
2804 } else {
2805 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2806 crtc_state->active_planes &= ~BIT(plane->id);
2807 }
2808
2809 DRM_DEBUG_KMS("%s active planes 0x%x\n",
2810 crtc_state->base.crtc->name,
2811 crtc_state->active_planes);
2812 }
2813
2814 static void
2815 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2816 struct intel_initial_plane_config *plane_config)
2817 {
2818 struct drm_device *dev = intel_crtc->base.dev;
2819 struct drm_i915_private *dev_priv = to_i915(dev);
2820 struct drm_crtc *c;
2821 struct drm_i915_gem_object *obj;
2822 struct drm_plane *primary = intel_crtc->base.primary;
2823 struct drm_plane_state *plane_state = primary->state;
2824 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2825 struct intel_plane *intel_plane = to_intel_plane(primary);
2826 struct intel_plane_state *intel_state =
2827 to_intel_plane_state(plane_state);
2828 struct drm_framebuffer *fb;
2829
2830 if (!plane_config->fb)
2831 return;
2832
2833 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2834 fb = &plane_config->fb->base;
2835 goto valid_fb;
2836 }
2837
2838 kfree(plane_config->fb);
2839
2840 /*
2841 * Failed to alloc the obj, check to see if we should share
2842 * an fb with another CRTC instead
2843 */
2844 for_each_crtc(dev, c) {
2845 struct intel_plane_state *state;
2846
2847 if (c == &intel_crtc->base)
2848 continue;
2849
2850 if (!to_intel_crtc(c)->active)
2851 continue;
2852
2853 state = to_intel_plane_state(c->primary->state);
2854 if (!state->vma)
2855 continue;
2856
2857 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2858 fb = c->primary->fb;
2859 drm_framebuffer_reference(fb);
2860 goto valid_fb;
2861 }
2862 }
2863
2864 /*
2865 * We've failed to reconstruct the BIOS FB. Current display state
2866 * indicates that the primary plane is visible, but has a NULL FB,
2867 * which will lead to problems later if we don't fix it up. The
2868 * simplest solution is to just disable the primary plane now and
2869 * pretend the BIOS never had it enabled.
2870 */
2871 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2872 to_intel_plane_state(plane_state),
2873 false);
2874 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2875 trace_intel_disable_plane(primary, intel_crtc);
2876 intel_plane->disable_plane(intel_plane, intel_crtc);
2877
2878 return;
2879
2880 valid_fb:
2881 mutex_lock(&dev->struct_mutex);
2882 intel_state->vma =
2883 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2884 mutex_unlock(&dev->struct_mutex);
2885 if (IS_ERR(intel_state->vma)) {
2886 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2887 intel_crtc->pipe, PTR_ERR(intel_state->vma));
2888
2889 intel_state->vma = NULL;
2890 drm_framebuffer_unreference(fb);
2891 return;
2892 }
2893
2894 plane_state->src_x = 0;
2895 plane_state->src_y = 0;
2896 plane_state->src_w = fb->width << 16;
2897 plane_state->src_h = fb->height << 16;
2898
2899 plane_state->crtc_x = 0;
2900 plane_state->crtc_y = 0;
2901 plane_state->crtc_w = fb->width;
2902 plane_state->crtc_h = fb->height;
2903
2904 intel_state->base.src = drm_plane_state_src(plane_state);
2905 intel_state->base.dst = drm_plane_state_dest(plane_state);
2906
2907 obj = intel_fb_obj(fb);
2908 if (i915_gem_object_is_tiled(obj))
2909 dev_priv->preserve_bios_swizzle = true;
2910
2911 drm_framebuffer_reference(fb);
2912 primary->fb = primary->state->fb = fb;
2913 primary->crtc = primary->state->crtc = &intel_crtc->base;
2914
2915 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2916 to_intel_plane_state(plane_state),
2917 true);
2918
2919 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2920 &obj->frontbuffer_bits);
2921 }
2922
2923 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2924 unsigned int rotation)
2925 {
2926 int cpp = fb->format->cpp[plane];
2927
2928 switch (fb->modifier) {
2929 case DRM_FORMAT_MOD_LINEAR:
2930 case I915_FORMAT_MOD_X_TILED:
2931 switch (cpp) {
2932 case 8:
2933 return 4096;
2934 case 4:
2935 case 2:
2936 case 1:
2937 return 8192;
2938 default:
2939 MISSING_CASE(cpp);
2940 break;
2941 }
2942 break;
2943 case I915_FORMAT_MOD_Y_TILED_CCS:
2944 case I915_FORMAT_MOD_Yf_TILED_CCS:
2945 /* FIXME AUX plane? */
2946 case I915_FORMAT_MOD_Y_TILED:
2947 case I915_FORMAT_MOD_Yf_TILED:
2948 switch (cpp) {
2949 case 8:
2950 return 2048;
2951 case 4:
2952 return 4096;
2953 case 2:
2954 case 1:
2955 return 8192;
2956 default:
2957 MISSING_CASE(cpp);
2958 break;
2959 }
2960 break;
2961 default:
2962 MISSING_CASE(fb->modifier);
2963 }
2964
2965 return 2048;
2966 }
2967
2968 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
2969 int main_x, int main_y, u32 main_offset)
2970 {
2971 const struct drm_framebuffer *fb = plane_state->base.fb;
2972 int hsub = fb->format->hsub;
2973 int vsub = fb->format->vsub;
2974 int aux_x = plane_state->aux.x;
2975 int aux_y = plane_state->aux.y;
2976 u32 aux_offset = plane_state->aux.offset;
2977 u32 alignment = intel_surf_alignment(fb, 1);
2978
2979 while (aux_offset >= main_offset && aux_y <= main_y) {
2980 int x, y;
2981
2982 if (aux_x == main_x && aux_y == main_y)
2983 break;
2984
2985 if (aux_offset == 0)
2986 break;
2987
2988 x = aux_x / hsub;
2989 y = aux_y / vsub;
2990 aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1,
2991 aux_offset, aux_offset - alignment);
2992 aux_x = x * hsub + aux_x % hsub;
2993 aux_y = y * vsub + aux_y % vsub;
2994 }
2995
2996 if (aux_x != main_x || aux_y != main_y)
2997 return false;
2998
2999 plane_state->aux.offset = aux_offset;
3000 plane_state->aux.x = aux_x;
3001 plane_state->aux.y = aux_y;
3002
3003 return true;
3004 }
3005
3006 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3007 {
3008 const struct drm_framebuffer *fb = plane_state->base.fb;
3009 unsigned int rotation = plane_state->base.rotation;
3010 int x = plane_state->base.src.x1 >> 16;
3011 int y = plane_state->base.src.y1 >> 16;
3012 int w = drm_rect_width(&plane_state->base.src) >> 16;
3013 int h = drm_rect_height(&plane_state->base.src) >> 16;
3014 int max_width = skl_max_plane_width(fb, 0, rotation);
3015 int max_height = 4096;
3016 u32 alignment, offset, aux_offset = plane_state->aux.offset;
3017
3018 if (w > max_width || h > max_height) {
3019 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3020 w, h, max_width, max_height);
3021 return -EINVAL;
3022 }
3023
3024 intel_add_fb_offsets(&x, &y, plane_state, 0);
3025 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
3026 alignment = intel_surf_alignment(fb, 0);
3027
3028 /*
3029 * AUX surface offset is specified as the distance from the
3030 * main surface offset, and it must be non-negative. Make
3031 * sure that is what we will get.
3032 */
3033 if (offset > aux_offset)
3034 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3035 offset, aux_offset & ~(alignment - 1));
3036
3037 /*
3038 * When using an X-tiled surface, the plane blows up
3039 * if the x offset + width exceed the stride.
3040 *
3041 * TODO: linear and Y-tiled seem fine, Yf untested,
3042 */
3043 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3044 int cpp = fb->format->cpp[0];
3045
3046 while ((x + w) * cpp > fb->pitches[0]) {
3047 if (offset == 0) {
3048 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3049 return -EINVAL;
3050 }
3051
3052 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3053 offset, offset - alignment);
3054 }
3055 }
3056
3057 /*
3058 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3059 * they match with the main surface x/y offsets.
3060 */
3061 if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3062 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3063 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3064 if (offset == 0)
3065 break;
3066
3067 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3068 offset, offset - alignment);
3069 }
3070
3071 if (x != plane_state->aux.x || y != plane_state->aux.y) {
3072 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3073 return -EINVAL;
3074 }
3075 }
3076
3077 plane_state->main.offset = offset;
3078 plane_state->main.x = x;
3079 plane_state->main.y = y;
3080
3081 return 0;
3082 }
3083
3084 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3085 {
3086 const struct drm_framebuffer *fb = plane_state->base.fb;
3087 unsigned int rotation = plane_state->base.rotation;
3088 int max_width = skl_max_plane_width(fb, 1, rotation);
3089 int max_height = 4096;
3090 int x = plane_state->base.src.x1 >> 17;
3091 int y = plane_state->base.src.y1 >> 17;
3092 int w = drm_rect_width(&plane_state->base.src) >> 17;
3093 int h = drm_rect_height(&plane_state->base.src) >> 17;
3094 u32 offset;
3095
3096 intel_add_fb_offsets(&x, &y, plane_state, 1);
3097 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3098
3099 /* FIXME not quite sure how/if these apply to the chroma plane */
3100 if (w > max_width || h > max_height) {
3101 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3102 w, h, max_width, max_height);
3103 return -EINVAL;
3104 }
3105
3106 plane_state->aux.offset = offset;
3107 plane_state->aux.x = x;
3108 plane_state->aux.y = y;
3109
3110 return 0;
3111 }
3112
3113 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3114 {
3115 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
3116 struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
3117 const struct drm_framebuffer *fb = plane_state->base.fb;
3118 int src_x = plane_state->base.src.x1 >> 16;
3119 int src_y = plane_state->base.src.y1 >> 16;
3120 int hsub = fb->format->hsub;
3121 int vsub = fb->format->vsub;
3122 int x = src_x / hsub;
3123 int y = src_y / vsub;
3124 u32 offset;
3125
3126 switch (plane->id) {
3127 case PLANE_PRIMARY:
3128 case PLANE_SPRITE0:
3129 break;
3130 default:
3131 DRM_DEBUG_KMS("RC support only on plane 1 and 2\n");
3132 return -EINVAL;
3133 }
3134
3135 if (crtc->pipe == PIPE_C) {
3136 DRM_DEBUG_KMS("No RC support on pipe C\n");
3137 return -EINVAL;
3138 }
3139
3140 if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) {
3141 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n",
3142 plane_state->base.rotation);
3143 return -EINVAL;
3144 }
3145
3146 intel_add_fb_offsets(&x, &y, plane_state, 1);
3147 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3148
3149 plane_state->aux.offset = offset;
3150 plane_state->aux.x = x * hsub + src_x % hsub;
3151 plane_state->aux.y = y * vsub + src_y % vsub;
3152
3153 return 0;
3154 }
3155
3156 int skl_check_plane_surface(struct intel_plane_state *plane_state)
3157 {
3158 const struct drm_framebuffer *fb = plane_state->base.fb;
3159 unsigned int rotation = plane_state->base.rotation;
3160 int ret;
3161
3162 if (!plane_state->base.visible)
3163 return 0;
3164
3165 /* Rotate src coordinates to match rotated GTT view */
3166 if (drm_rotation_90_or_270(rotation))
3167 drm_rect_rotate(&plane_state->base.src,
3168 fb->width << 16, fb->height << 16,
3169 DRM_MODE_ROTATE_270);
3170
3171 /*
3172 * Handle the AUX surface first since
3173 * the main surface setup depends on it.
3174 */
3175 if (fb->format->format == DRM_FORMAT_NV12) {
3176 ret = skl_check_nv12_aux_surface(plane_state);
3177 if (ret)
3178 return ret;
3179 } else if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3180 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3181 ret = skl_check_ccs_aux_surface(plane_state);
3182 if (ret)
3183 return ret;
3184 } else {
3185 plane_state->aux.offset = ~0xfff;
3186 plane_state->aux.x = 0;
3187 plane_state->aux.y = 0;
3188 }
3189
3190 ret = skl_check_main_surface(plane_state);
3191 if (ret)
3192 return ret;
3193
3194 return 0;
3195 }
3196
3197 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3198 const struct intel_plane_state *plane_state)
3199 {
3200 struct drm_i915_private *dev_priv =
3201 to_i915(plane_state->base.plane->dev);
3202 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3203 const struct drm_framebuffer *fb = plane_state->base.fb;
3204 unsigned int rotation = plane_state->base.rotation;
3205 u32 dspcntr;
3206
3207 dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
3208
3209 if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
3210 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
3211 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3212
3213 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3214 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3215
3216 if (INTEL_GEN(dev_priv) < 4)
3217 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3218
3219 switch (fb->format->format) {
3220 case DRM_FORMAT_C8:
3221 dspcntr |= DISPPLANE_8BPP;
3222 break;
3223 case DRM_FORMAT_XRGB1555:
3224 dspcntr |= DISPPLANE_BGRX555;
3225 break;
3226 case DRM_FORMAT_RGB565:
3227 dspcntr |= DISPPLANE_BGRX565;
3228 break;
3229 case DRM_FORMAT_XRGB8888:
3230 dspcntr |= DISPPLANE_BGRX888;
3231 break;
3232 case DRM_FORMAT_XBGR8888:
3233 dspcntr |= DISPPLANE_RGBX888;
3234 break;
3235 case DRM_FORMAT_XRGB2101010:
3236 dspcntr |= DISPPLANE_BGRX101010;
3237 break;
3238 case DRM_FORMAT_XBGR2101010:
3239 dspcntr |= DISPPLANE_RGBX101010;
3240 break;
3241 default:
3242 MISSING_CASE(fb->format->format);
3243 return 0;
3244 }
3245
3246 if (INTEL_GEN(dev_priv) >= 4 &&
3247 fb->modifier == I915_FORMAT_MOD_X_TILED)
3248 dspcntr |= DISPPLANE_TILED;
3249
3250 if (rotation & DRM_MODE_ROTATE_180)
3251 dspcntr |= DISPPLANE_ROTATE_180;
3252
3253 if (rotation & DRM_MODE_REFLECT_X)
3254 dspcntr |= DISPPLANE_MIRROR;
3255
3256 return dspcntr;
3257 }
3258
3259 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3260 {
3261 struct drm_i915_private *dev_priv =
3262 to_i915(plane_state->base.plane->dev);
3263 int src_x = plane_state->base.src.x1 >> 16;
3264 int src_y = plane_state->base.src.y1 >> 16;
3265 u32 offset;
3266
3267 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3268
3269 if (INTEL_GEN(dev_priv) >= 4)
3270 offset = intel_compute_tile_offset(&src_x, &src_y,
3271 plane_state, 0);
3272 else
3273 offset = 0;
3274
3275 /* HSW/BDW do this automagically in hardware */
3276 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3277 unsigned int rotation = plane_state->base.rotation;
3278 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3279 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3280
3281 if (rotation & DRM_MODE_ROTATE_180) {
3282 src_x += src_w - 1;
3283 src_y += src_h - 1;
3284 } else if (rotation & DRM_MODE_REFLECT_X) {
3285 src_x += src_w - 1;
3286 }
3287 }
3288
3289 plane_state->main.offset = offset;
3290 plane_state->main.x = src_x;
3291 plane_state->main.y = src_y;
3292
3293 return 0;
3294 }
3295
3296 static void i9xx_update_primary_plane(struct intel_plane *primary,
3297 const struct intel_crtc_state *crtc_state,
3298 const struct intel_plane_state *plane_state)
3299 {
3300 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3301 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3302 const struct drm_framebuffer *fb = plane_state->base.fb;
3303 enum plane plane = primary->plane;
3304 u32 linear_offset;
3305 u32 dspcntr = plane_state->ctl;
3306 i915_reg_t reg = DSPCNTR(plane);
3307 int x = plane_state->main.x;
3308 int y = plane_state->main.y;
3309 unsigned long irqflags;
3310
3311 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3312
3313 if (INTEL_GEN(dev_priv) >= 4)
3314 crtc->dspaddr_offset = plane_state->main.offset;
3315 else
3316 crtc->dspaddr_offset = linear_offset;
3317
3318 crtc->adjusted_x = x;
3319 crtc->adjusted_y = y;
3320
3321 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3322
3323 if (INTEL_GEN(dev_priv) < 4) {
3324 /* pipesrc and dspsize control the size that is scaled from,
3325 * which should always be the user's requested size.
3326 */
3327 I915_WRITE_FW(DSPSIZE(plane),
3328 ((crtc_state->pipe_src_h - 1) << 16) |
3329 (crtc_state->pipe_src_w - 1));
3330 I915_WRITE_FW(DSPPOS(plane), 0);
3331 } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3332 I915_WRITE_FW(PRIMSIZE(plane),
3333 ((crtc_state->pipe_src_h - 1) << 16) |
3334 (crtc_state->pipe_src_w - 1));
3335 I915_WRITE_FW(PRIMPOS(plane), 0);
3336 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3337 }
3338
3339 I915_WRITE_FW(reg, dspcntr);
3340
3341 I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3342 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3343 I915_WRITE_FW(DSPSURF(plane),
3344 intel_plane_ggtt_offset(plane_state) +
3345 crtc->dspaddr_offset);
3346 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3347 } else if (INTEL_GEN(dev_priv) >= 4) {
3348 I915_WRITE_FW(DSPSURF(plane),
3349 intel_plane_ggtt_offset(plane_state) +
3350 crtc->dspaddr_offset);
3351 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3352 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3353 } else {
3354 I915_WRITE_FW(DSPADDR(plane),
3355 intel_plane_ggtt_offset(plane_state) +
3356 crtc->dspaddr_offset);
3357 }
3358 POSTING_READ_FW(reg);
3359
3360 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3361 }
3362
3363 static void i9xx_disable_primary_plane(struct intel_plane *primary,
3364 struct intel_crtc *crtc)
3365 {
3366 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3367 enum plane plane = primary->plane;
3368 unsigned long irqflags;
3369
3370 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3371
3372 I915_WRITE_FW(DSPCNTR(plane), 0);
3373 if (INTEL_INFO(dev_priv)->gen >= 4)
3374 I915_WRITE_FW(DSPSURF(plane), 0);
3375 else
3376 I915_WRITE_FW(DSPADDR(plane), 0);
3377 POSTING_READ_FW(DSPCNTR(plane));
3378
3379 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3380 }
3381
3382 static u32
3383 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3384 {
3385 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3386 return 64;
3387 else
3388 return intel_tile_width_bytes(fb, plane);
3389 }
3390
3391 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3392 {
3393 struct drm_device *dev = intel_crtc->base.dev;
3394 struct drm_i915_private *dev_priv = to_i915(dev);
3395
3396 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3397 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3398 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3399 }
3400
3401 /*
3402 * This function detaches (aka. unbinds) unused scalers in hardware
3403 */
3404 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3405 {
3406 struct intel_crtc_scaler_state *scaler_state;
3407 int i;
3408
3409 scaler_state = &intel_crtc->config->scaler_state;
3410
3411 /* loop through and disable scalers that aren't in use */
3412 for (i = 0; i < intel_crtc->num_scalers; i++) {
3413 if (!scaler_state->scalers[i].in_use)
3414 skl_detach_scaler(intel_crtc, i);
3415 }
3416 }
3417
3418 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3419 unsigned int rotation)
3420 {
3421 u32 stride;
3422
3423 if (plane >= fb->format->num_planes)
3424 return 0;
3425
3426 stride = intel_fb_pitch(fb, plane, rotation);
3427
3428 /*
3429 * The stride is either expressed as a multiple of 64 bytes chunks for
3430 * linear buffers or in number of tiles for tiled buffers.
3431 */
3432 if (drm_rotation_90_or_270(rotation))
3433 stride /= intel_tile_height(fb, plane);
3434 else
3435 stride /= intel_fb_stride_alignment(fb, plane);
3436
3437 return stride;
3438 }
3439
3440 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3441 {
3442 switch (pixel_format) {
3443 case DRM_FORMAT_C8:
3444 return PLANE_CTL_FORMAT_INDEXED;
3445 case DRM_FORMAT_RGB565:
3446 return PLANE_CTL_FORMAT_RGB_565;
3447 case DRM_FORMAT_XBGR8888:
3448 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3449 case DRM_FORMAT_XRGB8888:
3450 return PLANE_CTL_FORMAT_XRGB_8888;
3451 /*
3452 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3453 * to be already pre-multiplied. We need to add a knob (or a different
3454 * DRM_FORMAT) for user-space to configure that.
3455 */
3456 case DRM_FORMAT_ABGR8888:
3457 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3458 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3459 case DRM_FORMAT_ARGB8888:
3460 return PLANE_CTL_FORMAT_XRGB_8888 |
3461 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3462 case DRM_FORMAT_XRGB2101010:
3463 return PLANE_CTL_FORMAT_XRGB_2101010;
3464 case DRM_FORMAT_XBGR2101010:
3465 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3466 case DRM_FORMAT_YUYV:
3467 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3468 case DRM_FORMAT_YVYU:
3469 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3470 case DRM_FORMAT_UYVY:
3471 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3472 case DRM_FORMAT_VYUY:
3473 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3474 default:
3475 MISSING_CASE(pixel_format);
3476 }
3477
3478 return 0;
3479 }
3480
3481 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3482 {
3483 switch (fb_modifier) {
3484 case DRM_FORMAT_MOD_LINEAR:
3485 break;
3486 case I915_FORMAT_MOD_X_TILED:
3487 return PLANE_CTL_TILED_X;
3488 case I915_FORMAT_MOD_Y_TILED:
3489 return PLANE_CTL_TILED_Y;
3490 case I915_FORMAT_MOD_Y_TILED_CCS:
3491 return PLANE_CTL_TILED_Y | PLANE_CTL_DECOMPRESSION_ENABLE;
3492 case I915_FORMAT_MOD_Yf_TILED:
3493 return PLANE_CTL_TILED_YF;
3494 case I915_FORMAT_MOD_Yf_TILED_CCS:
3495 return PLANE_CTL_TILED_YF | PLANE_CTL_DECOMPRESSION_ENABLE;
3496 default:
3497 MISSING_CASE(fb_modifier);
3498 }
3499
3500 return 0;
3501 }
3502
3503 static u32 skl_plane_ctl_rotation(unsigned int rotation)
3504 {
3505 switch (rotation) {
3506 case DRM_MODE_ROTATE_0:
3507 break;
3508 /*
3509 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3510 * while i915 HW rotation is clockwise, thats why this swapping.
3511 */
3512 case DRM_MODE_ROTATE_90:
3513 return PLANE_CTL_ROTATE_270;
3514 case DRM_MODE_ROTATE_180:
3515 return PLANE_CTL_ROTATE_180;
3516 case DRM_MODE_ROTATE_270:
3517 return PLANE_CTL_ROTATE_90;
3518 default:
3519 MISSING_CASE(rotation);
3520 }
3521
3522 return 0;
3523 }
3524
3525 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3526 const struct intel_plane_state *plane_state)
3527 {
3528 struct drm_i915_private *dev_priv =
3529 to_i915(plane_state->base.plane->dev);
3530 const struct drm_framebuffer *fb = plane_state->base.fb;
3531 unsigned int rotation = plane_state->base.rotation;
3532 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3533 u32 plane_ctl;
3534
3535 plane_ctl = PLANE_CTL_ENABLE;
3536
3537 if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
3538 plane_ctl |=
3539 PLANE_CTL_PIPE_GAMMA_ENABLE |
3540 PLANE_CTL_PIPE_CSC_ENABLE |
3541 PLANE_CTL_PLANE_GAMMA_DISABLE;
3542 }
3543
3544 plane_ctl |= skl_plane_ctl_format(fb->format->format);
3545 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3546 plane_ctl |= skl_plane_ctl_rotation(rotation);
3547
3548 if (key->flags & I915_SET_COLORKEY_DESTINATION)
3549 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3550 else if (key->flags & I915_SET_COLORKEY_SOURCE)
3551 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3552
3553 return plane_ctl;
3554 }
3555
3556 static void skylake_update_primary_plane(struct intel_plane *plane,
3557 const struct intel_crtc_state *crtc_state,
3558 const struct intel_plane_state *plane_state)
3559 {
3560 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3561 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3562 const struct drm_framebuffer *fb = plane_state->base.fb;
3563 enum plane_id plane_id = plane->id;
3564 enum pipe pipe = plane->pipe;
3565 u32 plane_ctl = plane_state->ctl;
3566 unsigned int rotation = plane_state->base.rotation;
3567 u32 stride = skl_plane_stride(fb, 0, rotation);
3568 u32 aux_stride = skl_plane_stride(fb, 1, rotation);
3569 u32 surf_addr = plane_state->main.offset;
3570 int scaler_id = plane_state->scaler_id;
3571 int src_x = plane_state->main.x;
3572 int src_y = plane_state->main.y;
3573 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3574 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3575 int dst_x = plane_state->base.dst.x1;
3576 int dst_y = plane_state->base.dst.y1;
3577 int dst_w = drm_rect_width(&plane_state->base.dst);
3578 int dst_h = drm_rect_height(&plane_state->base.dst);
3579 unsigned long irqflags;
3580
3581 /* Sizes are 0 based */
3582 src_w--;
3583 src_h--;
3584 dst_w--;
3585 dst_h--;
3586
3587 crtc->dspaddr_offset = surf_addr;
3588
3589 crtc->adjusted_x = src_x;
3590 crtc->adjusted_y = src_y;
3591
3592 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3593
3594 if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
3595 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
3596 PLANE_COLOR_PIPE_GAMMA_ENABLE |
3597 PLANE_COLOR_PIPE_CSC_ENABLE |
3598 PLANE_COLOR_PLANE_GAMMA_DISABLE);
3599 }
3600
3601 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
3602 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3603 I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
3604 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3605 I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
3606 (plane_state->aux.offset - surf_addr) | aux_stride);
3607 I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
3608 (plane_state->aux.y << 16) | plane_state->aux.x);
3609
3610 if (scaler_id >= 0) {
3611 uint32_t ps_ctrl = 0;
3612
3613 WARN_ON(!dst_w || !dst_h);
3614 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3615 crtc_state->scaler_state.scalers[scaler_id].mode;
3616 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3617 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3618 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3619 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3620 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
3621 } else {
3622 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3623 }
3624
3625 I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
3626 intel_plane_ggtt_offset(plane_state) + surf_addr);
3627
3628 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3629
3630 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3631 }
3632
3633 static void skylake_disable_primary_plane(struct intel_plane *primary,
3634 struct intel_crtc *crtc)
3635 {
3636 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3637 enum plane_id plane_id = primary->id;
3638 enum pipe pipe = primary->pipe;
3639 unsigned long irqflags;
3640
3641 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3642
3643 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
3644 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
3645 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3646
3647 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3648 }
3649
3650 static int
3651 __intel_display_resume(struct drm_device *dev,
3652 struct drm_atomic_state *state,
3653 struct drm_modeset_acquire_ctx *ctx)
3654 {
3655 struct drm_crtc_state *crtc_state;
3656 struct drm_crtc *crtc;
3657 int i, ret;
3658
3659 intel_modeset_setup_hw_state(dev, ctx);
3660 i915_redisable_vga(to_i915(dev));
3661
3662 if (!state)
3663 return 0;
3664
3665 /*
3666 * We've duplicated the state, pointers to the old state are invalid.
3667 *
3668 * Don't attempt to use the old state until we commit the duplicated state.
3669 */
3670 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3671 /*
3672 * Force recalculation even if we restore
3673 * current state. With fast modeset this may not result
3674 * in a modeset when the state is compatible.
3675 */
3676 crtc_state->mode_changed = true;
3677 }
3678
3679 /* ignore any reset values/BIOS leftovers in the WM registers */
3680 if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3681 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3682
3683 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3684
3685 WARN_ON(ret == -EDEADLK);
3686 return ret;
3687 }
3688
3689 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3690 {
3691 return intel_has_gpu_reset(dev_priv) &&
3692 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3693 }
3694
3695 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3696 {
3697 struct drm_device *dev = &dev_priv->drm;
3698 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3699 struct drm_atomic_state *state;
3700 int ret;
3701
3702
3703 /* reset doesn't touch the display */
3704 if (!i915.force_reset_modeset_test &&
3705 !gpu_reset_clobbers_display(dev_priv))
3706 return;
3707
3708 /* We have a modeset vs reset deadlock, defensively unbreak it. */
3709 set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3710 wake_up_all(&dev_priv->gpu_error.wait_queue);
3711
3712 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
3713 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
3714 i915_gem_set_wedged(dev_priv);
3715 }
3716
3717 /*
3718 * Need mode_config.mutex so that we don't
3719 * trample ongoing ->detect() and whatnot.
3720 */
3721 mutex_lock(&dev->mode_config.mutex);
3722 drm_modeset_acquire_init(ctx, 0);
3723 while (1) {
3724 ret = drm_modeset_lock_all_ctx(dev, ctx);
3725 if (ret != -EDEADLK)
3726 break;
3727
3728 drm_modeset_backoff(ctx);
3729 }
3730 /*
3731 * Disabling the crtcs gracefully seems nicer. Also the
3732 * g33 docs say we should at least disable all the planes.
3733 */
3734 state = drm_atomic_helper_duplicate_state(dev, ctx);
3735 if (IS_ERR(state)) {
3736 ret = PTR_ERR(state);
3737 DRM_ERROR("Duplicating state failed with %i\n", ret);
3738 return;
3739 }
3740
3741 ret = drm_atomic_helper_disable_all(dev, ctx);
3742 if (ret) {
3743 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3744 drm_atomic_state_put(state);
3745 return;
3746 }
3747
3748 dev_priv->modeset_restore_state = state;
3749 state->acquire_ctx = ctx;
3750 }
3751
3752 void intel_finish_reset(struct drm_i915_private *dev_priv)
3753 {
3754 struct drm_device *dev = &dev_priv->drm;
3755 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3756 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3757 int ret;
3758
3759 /* reset doesn't touch the display */
3760 if (!i915.force_reset_modeset_test &&
3761 !gpu_reset_clobbers_display(dev_priv))
3762 return;
3763
3764 if (!state)
3765 goto unlock;
3766
3767 dev_priv->modeset_restore_state = NULL;
3768
3769 /* reset doesn't touch the display */
3770 if (!gpu_reset_clobbers_display(dev_priv)) {
3771 /* for testing only restore the display */
3772 ret = __intel_display_resume(dev, state, ctx);
3773 if (ret)
3774 DRM_ERROR("Restoring old state failed with %i\n", ret);
3775 } else {
3776 /*
3777 * The display has been reset as well,
3778 * so need a full re-initialization.
3779 */
3780 intel_runtime_pm_disable_interrupts(dev_priv);
3781 intel_runtime_pm_enable_interrupts(dev_priv);
3782
3783 intel_pps_unlock_regs_wa(dev_priv);
3784 intel_modeset_init_hw(dev);
3785
3786 spin_lock_irq(&dev_priv->irq_lock);
3787 if (dev_priv->display.hpd_irq_setup)
3788 dev_priv->display.hpd_irq_setup(dev_priv);
3789 spin_unlock_irq(&dev_priv->irq_lock);
3790
3791 ret = __intel_display_resume(dev, state, ctx);
3792 if (ret)
3793 DRM_ERROR("Restoring old state failed with %i\n", ret);
3794
3795 intel_hpd_init(dev_priv);
3796 }
3797
3798 drm_atomic_state_put(state);
3799 unlock:
3800 drm_modeset_drop_locks(ctx);
3801 drm_modeset_acquire_fini(ctx);
3802 mutex_unlock(&dev->mode_config.mutex);
3803
3804 clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3805 }
3806
3807 static void intel_update_pipe_config(struct intel_crtc *crtc,
3808 struct intel_crtc_state *old_crtc_state)
3809 {
3810 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3811 struct intel_crtc_state *pipe_config =
3812 to_intel_crtc_state(crtc->base.state);
3813
3814 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3815 crtc->base.mode = crtc->base.state->mode;
3816
3817 /*
3818 * Update pipe size and adjust fitter if needed: the reason for this is
3819 * that in compute_mode_changes we check the native mode (not the pfit
3820 * mode) to see if we can flip rather than do a full mode set. In the
3821 * fastboot case, we'll flip, but if we don't update the pipesrc and
3822 * pfit state, we'll end up with a big fb scanned out into the wrong
3823 * sized surface.
3824 */
3825
3826 I915_WRITE(PIPESRC(crtc->pipe),
3827 ((pipe_config->pipe_src_w - 1) << 16) |
3828 (pipe_config->pipe_src_h - 1));
3829
3830 /* on skylake this is done by detaching scalers */
3831 if (INTEL_GEN(dev_priv) >= 9) {
3832 skl_detach_scalers(crtc);
3833
3834 if (pipe_config->pch_pfit.enabled)
3835 skylake_pfit_enable(crtc);
3836 } else if (HAS_PCH_SPLIT(dev_priv)) {
3837 if (pipe_config->pch_pfit.enabled)
3838 ironlake_pfit_enable(crtc);
3839 else if (old_crtc_state->pch_pfit.enabled)
3840 ironlake_pfit_disable(crtc, true);
3841 }
3842 }
3843
3844 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3845 {
3846 struct drm_device *dev = crtc->base.dev;
3847 struct drm_i915_private *dev_priv = to_i915(dev);
3848 int pipe = crtc->pipe;
3849 i915_reg_t reg;
3850 u32 temp;
3851
3852 /* enable normal train */
3853 reg = FDI_TX_CTL(pipe);
3854 temp = I915_READ(reg);
3855 if (IS_IVYBRIDGE(dev_priv)) {
3856 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3857 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3858 } else {
3859 temp &= ~FDI_LINK_TRAIN_NONE;
3860 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3861 }
3862 I915_WRITE(reg, temp);
3863
3864 reg = FDI_RX_CTL(pipe);
3865 temp = I915_READ(reg);
3866 if (HAS_PCH_CPT(dev_priv)) {
3867 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3868 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3869 } else {
3870 temp &= ~FDI_LINK_TRAIN_NONE;
3871 temp |= FDI_LINK_TRAIN_NONE;
3872 }
3873 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3874
3875 /* wait one idle pattern time */
3876 POSTING_READ(reg);
3877 udelay(1000);
3878
3879 /* IVB wants error correction enabled */
3880 if (IS_IVYBRIDGE(dev_priv))
3881 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3882 FDI_FE_ERRC_ENABLE);
3883 }
3884
3885 /* The FDI link training functions for ILK/Ibexpeak. */
3886 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3887 const struct intel_crtc_state *crtc_state)
3888 {
3889 struct drm_device *dev = crtc->base.dev;
3890 struct drm_i915_private *dev_priv = to_i915(dev);
3891 int pipe = crtc->pipe;
3892 i915_reg_t reg;
3893 u32 temp, tries;
3894
3895 /* FDI needs bits from pipe first */
3896 assert_pipe_enabled(dev_priv, pipe);
3897
3898 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3899 for train result */
3900 reg = FDI_RX_IMR(pipe);
3901 temp = I915_READ(reg);
3902 temp &= ~FDI_RX_SYMBOL_LOCK;
3903 temp &= ~FDI_RX_BIT_LOCK;
3904 I915_WRITE(reg, temp);
3905 I915_READ(reg);
3906 udelay(150);
3907
3908 /* enable CPU FDI TX and PCH FDI RX */
3909 reg = FDI_TX_CTL(pipe);
3910 temp = I915_READ(reg);
3911 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3912 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3913 temp &= ~FDI_LINK_TRAIN_NONE;
3914 temp |= FDI_LINK_TRAIN_PATTERN_1;
3915 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3916
3917 reg = FDI_RX_CTL(pipe);
3918 temp = I915_READ(reg);
3919 temp &= ~FDI_LINK_TRAIN_NONE;
3920 temp |= FDI_LINK_TRAIN_PATTERN_1;
3921 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3922
3923 POSTING_READ(reg);
3924 udelay(150);
3925
3926 /* Ironlake workaround, enable clock pointer after FDI enable*/
3927 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3928 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3929 FDI_RX_PHASE_SYNC_POINTER_EN);
3930
3931 reg = FDI_RX_IIR(pipe);
3932 for (tries = 0; tries < 5; tries++) {
3933 temp = I915_READ(reg);
3934 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3935
3936 if ((temp & FDI_RX_BIT_LOCK)) {
3937 DRM_DEBUG_KMS("FDI train 1 done.\n");
3938 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3939 break;
3940 }
3941 }
3942 if (tries == 5)
3943 DRM_ERROR("FDI train 1 fail!\n");
3944
3945 /* Train 2 */
3946 reg = FDI_TX_CTL(pipe);
3947 temp = I915_READ(reg);
3948 temp &= ~FDI_LINK_TRAIN_NONE;
3949 temp |= FDI_LINK_TRAIN_PATTERN_2;
3950 I915_WRITE(reg, temp);
3951
3952 reg = FDI_RX_CTL(pipe);
3953 temp = I915_READ(reg);
3954 temp &= ~FDI_LINK_TRAIN_NONE;
3955 temp |= FDI_LINK_TRAIN_PATTERN_2;
3956 I915_WRITE(reg, temp);
3957
3958 POSTING_READ(reg);
3959 udelay(150);
3960
3961 reg = FDI_RX_IIR(pipe);
3962 for (tries = 0; tries < 5; tries++) {
3963 temp = I915_READ(reg);
3964 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3965
3966 if (temp & FDI_RX_SYMBOL_LOCK) {
3967 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3968 DRM_DEBUG_KMS("FDI train 2 done.\n");
3969 break;
3970 }
3971 }
3972 if (tries == 5)
3973 DRM_ERROR("FDI train 2 fail!\n");
3974
3975 DRM_DEBUG_KMS("FDI train done\n");
3976
3977 }
3978
3979 static const int snb_b_fdi_train_param[] = {
3980 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3981 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3982 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3983 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3984 };
3985
3986 /* The FDI link training functions for SNB/Cougarpoint. */
3987 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3988 const struct intel_crtc_state *crtc_state)
3989 {
3990 struct drm_device *dev = crtc->base.dev;
3991 struct drm_i915_private *dev_priv = to_i915(dev);
3992 int pipe = crtc->pipe;
3993 i915_reg_t reg;
3994 u32 temp, i, retry;
3995
3996 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3997 for train result */
3998 reg = FDI_RX_IMR(pipe);
3999 temp = I915_READ(reg);
4000 temp &= ~FDI_RX_SYMBOL_LOCK;
4001 temp &= ~FDI_RX_BIT_LOCK;
4002 I915_WRITE(reg, temp);
4003
4004 POSTING_READ(reg);
4005 udelay(150);
4006
4007 /* enable CPU FDI TX and PCH FDI RX */
4008 reg = FDI_TX_CTL(pipe);
4009 temp = I915_READ(reg);
4010 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4011 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4012 temp &= ~FDI_LINK_TRAIN_NONE;
4013 temp |= FDI_LINK_TRAIN_PATTERN_1;
4014 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4015 /* SNB-B */
4016 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4017 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4018
4019 I915_WRITE(FDI_RX_MISC(pipe),
4020 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4021
4022 reg = FDI_RX_CTL(pipe);
4023 temp = I915_READ(reg);
4024 if (HAS_PCH_CPT(dev_priv)) {
4025 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4026 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4027 } else {
4028 temp &= ~FDI_LINK_TRAIN_NONE;
4029 temp |= FDI_LINK_TRAIN_PATTERN_1;
4030 }
4031 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4032
4033 POSTING_READ(reg);
4034 udelay(150);
4035
4036 for (i = 0; i < 4; i++) {
4037 reg = FDI_TX_CTL(pipe);
4038 temp = I915_READ(reg);
4039 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4040 temp |= snb_b_fdi_train_param[i];
4041 I915_WRITE(reg, temp);
4042
4043 POSTING_READ(reg);
4044 udelay(500);
4045
4046 for (retry = 0; retry < 5; retry++) {
4047 reg = FDI_RX_IIR(pipe);
4048 temp = I915_READ(reg);
4049 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4050 if (temp & FDI_RX_BIT_LOCK) {
4051 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4052 DRM_DEBUG_KMS("FDI train 1 done.\n");
4053 break;
4054 }
4055 udelay(50);
4056 }
4057 if (retry < 5)
4058 break;
4059 }
4060 if (i == 4)
4061 DRM_ERROR("FDI train 1 fail!\n");
4062
4063 /* Train 2 */
4064 reg = FDI_TX_CTL(pipe);
4065 temp = I915_READ(reg);
4066 temp &= ~FDI_LINK_TRAIN_NONE;
4067 temp |= FDI_LINK_TRAIN_PATTERN_2;
4068 if (IS_GEN6(dev_priv)) {
4069 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4070 /* SNB-B */
4071 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4072 }
4073 I915_WRITE(reg, temp);
4074
4075 reg = FDI_RX_CTL(pipe);
4076 temp = I915_READ(reg);
4077 if (HAS_PCH_CPT(dev_priv)) {
4078 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4079 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4080 } else {
4081 temp &= ~FDI_LINK_TRAIN_NONE;
4082 temp |= FDI_LINK_TRAIN_PATTERN_2;
4083 }
4084 I915_WRITE(reg, temp);
4085
4086 POSTING_READ(reg);
4087 udelay(150);
4088
4089 for (i = 0; i < 4; i++) {
4090 reg = FDI_TX_CTL(pipe);
4091 temp = I915_READ(reg);
4092 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4093 temp |= snb_b_fdi_train_param[i];
4094 I915_WRITE(reg, temp);
4095
4096 POSTING_READ(reg);
4097 udelay(500);
4098
4099 for (retry = 0; retry < 5; retry++) {
4100 reg = FDI_RX_IIR(pipe);
4101 temp = I915_READ(reg);
4102 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4103 if (temp & FDI_RX_SYMBOL_LOCK) {
4104 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4105 DRM_DEBUG_KMS("FDI train 2 done.\n");
4106 break;
4107 }
4108 udelay(50);
4109 }
4110 if (retry < 5)
4111 break;
4112 }
4113 if (i == 4)
4114 DRM_ERROR("FDI train 2 fail!\n");
4115
4116 DRM_DEBUG_KMS("FDI train done.\n");
4117 }
4118
4119 /* Manual link training for Ivy Bridge A0 parts */
4120 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4121 const struct intel_crtc_state *crtc_state)
4122 {
4123 struct drm_device *dev = crtc->base.dev;
4124 struct drm_i915_private *dev_priv = to_i915(dev);
4125 int pipe = crtc->pipe;
4126 i915_reg_t reg;
4127 u32 temp, i, j;
4128
4129 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4130 for train result */
4131 reg = FDI_RX_IMR(pipe);
4132 temp = I915_READ(reg);
4133 temp &= ~FDI_RX_SYMBOL_LOCK;
4134 temp &= ~FDI_RX_BIT_LOCK;
4135 I915_WRITE(reg, temp);
4136
4137 POSTING_READ(reg);
4138 udelay(150);
4139
4140 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4141 I915_READ(FDI_RX_IIR(pipe)));
4142
4143 /* Try each vswing and preemphasis setting twice before moving on */
4144 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4145 /* disable first in case we need to retry */
4146 reg = FDI_TX_CTL(pipe);
4147 temp = I915_READ(reg);
4148 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4149 temp &= ~FDI_TX_ENABLE;
4150 I915_WRITE(reg, temp);
4151
4152 reg = FDI_RX_CTL(pipe);
4153 temp = I915_READ(reg);
4154 temp &= ~FDI_LINK_TRAIN_AUTO;
4155 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4156 temp &= ~FDI_RX_ENABLE;
4157 I915_WRITE(reg, temp);
4158
4159 /* enable CPU FDI TX and PCH FDI RX */
4160 reg = FDI_TX_CTL(pipe);
4161 temp = I915_READ(reg);
4162 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4163 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4164 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4165 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4166 temp |= snb_b_fdi_train_param[j/2];
4167 temp |= FDI_COMPOSITE_SYNC;
4168 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4169
4170 I915_WRITE(FDI_RX_MISC(pipe),
4171 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4172
4173 reg = FDI_RX_CTL(pipe);
4174 temp = I915_READ(reg);
4175 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4176 temp |= FDI_COMPOSITE_SYNC;
4177 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4178
4179 POSTING_READ(reg);
4180 udelay(1); /* should be 0.5us */
4181
4182 for (i = 0; i < 4; i++) {
4183 reg = FDI_RX_IIR(pipe);
4184 temp = I915_READ(reg);
4185 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4186
4187 if (temp & FDI_RX_BIT_LOCK ||
4188 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4189 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4190 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4191 i);
4192 break;
4193 }
4194 udelay(1); /* should be 0.5us */
4195 }
4196 if (i == 4) {
4197 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4198 continue;
4199 }
4200
4201 /* Train 2 */
4202 reg = FDI_TX_CTL(pipe);
4203 temp = I915_READ(reg);
4204 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4205 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4206 I915_WRITE(reg, temp);
4207
4208 reg = FDI_RX_CTL(pipe);
4209 temp = I915_READ(reg);
4210 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4211 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4212 I915_WRITE(reg, temp);
4213
4214 POSTING_READ(reg);
4215 udelay(2); /* should be 1.5us */
4216
4217 for (i = 0; i < 4; i++) {
4218 reg = FDI_RX_IIR(pipe);
4219 temp = I915_READ(reg);
4220 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4221
4222 if (temp & FDI_RX_SYMBOL_LOCK ||
4223 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4224 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4225 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4226 i);
4227 goto train_done;
4228 }
4229 udelay(2); /* should be 1.5us */
4230 }
4231 if (i == 4)
4232 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4233 }
4234
4235 train_done:
4236 DRM_DEBUG_KMS("FDI train done.\n");
4237 }
4238
4239 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4240 {
4241 struct drm_device *dev = intel_crtc->base.dev;
4242 struct drm_i915_private *dev_priv = to_i915(dev);
4243 int pipe = intel_crtc->pipe;
4244 i915_reg_t reg;
4245 u32 temp;
4246
4247 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4248 reg = FDI_RX_CTL(pipe);
4249 temp = I915_READ(reg);
4250 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4251 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4252 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4253 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4254
4255 POSTING_READ(reg);
4256 udelay(200);
4257
4258 /* Switch from Rawclk to PCDclk */
4259 temp = I915_READ(reg);
4260 I915_WRITE(reg, temp | FDI_PCDCLK);
4261
4262 POSTING_READ(reg);
4263 udelay(200);
4264
4265 /* Enable CPU FDI TX PLL, always on for Ironlake */
4266 reg = FDI_TX_CTL(pipe);
4267 temp = I915_READ(reg);
4268 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4269 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4270
4271 POSTING_READ(reg);
4272 udelay(100);
4273 }
4274 }
4275
4276 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4277 {
4278 struct drm_device *dev = intel_crtc->base.dev;
4279 struct drm_i915_private *dev_priv = to_i915(dev);
4280 int pipe = intel_crtc->pipe;
4281 i915_reg_t reg;
4282 u32 temp;
4283
4284 /* Switch from PCDclk to Rawclk */
4285 reg = FDI_RX_CTL(pipe);
4286 temp = I915_READ(reg);
4287 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4288
4289 /* Disable CPU FDI TX PLL */
4290 reg = FDI_TX_CTL(pipe);
4291 temp = I915_READ(reg);
4292 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4293
4294 POSTING_READ(reg);
4295 udelay(100);
4296
4297 reg = FDI_RX_CTL(pipe);
4298 temp = I915_READ(reg);
4299 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4300
4301 /* Wait for the clocks to turn off. */
4302 POSTING_READ(reg);
4303 udelay(100);
4304 }
4305
4306 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4307 {
4308 struct drm_device *dev = crtc->dev;
4309 struct drm_i915_private *dev_priv = to_i915(dev);
4310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4311 int pipe = intel_crtc->pipe;
4312 i915_reg_t reg;
4313 u32 temp;
4314
4315 /* disable CPU FDI tx and PCH FDI rx */
4316 reg = FDI_TX_CTL(pipe);
4317 temp = I915_READ(reg);
4318 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4319 POSTING_READ(reg);
4320
4321 reg = FDI_RX_CTL(pipe);
4322 temp = I915_READ(reg);
4323 temp &= ~(0x7 << 16);
4324 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4325 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4326
4327 POSTING_READ(reg);
4328 udelay(100);
4329
4330 /* Ironlake workaround, disable clock pointer after downing FDI */
4331 if (HAS_PCH_IBX(dev_priv))
4332 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4333
4334 /* still set train pattern 1 */
4335 reg = FDI_TX_CTL(pipe);
4336 temp = I915_READ(reg);
4337 temp &= ~FDI_LINK_TRAIN_NONE;
4338 temp |= FDI_LINK_TRAIN_PATTERN_1;
4339 I915_WRITE(reg, temp);
4340
4341 reg = FDI_RX_CTL(pipe);
4342 temp = I915_READ(reg);
4343 if (HAS_PCH_CPT(dev_priv)) {
4344 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4345 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4346 } else {
4347 temp &= ~FDI_LINK_TRAIN_NONE;
4348 temp |= FDI_LINK_TRAIN_PATTERN_1;
4349 }
4350 /* BPC in FDI rx is consistent with that in PIPECONF */
4351 temp &= ~(0x07 << 16);
4352 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4353 I915_WRITE(reg, temp);
4354
4355 POSTING_READ(reg);
4356 udelay(100);
4357 }
4358
4359 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4360 {
4361 struct drm_crtc *crtc;
4362 bool cleanup_done;
4363
4364 drm_for_each_crtc(crtc, &dev_priv->drm) {
4365 struct drm_crtc_commit *commit;
4366 spin_lock(&crtc->commit_lock);
4367 commit = list_first_entry_or_null(&crtc->commit_list,
4368 struct drm_crtc_commit, commit_entry);
4369 cleanup_done = commit ?
4370 try_wait_for_completion(&commit->cleanup_done) : true;
4371 spin_unlock(&crtc->commit_lock);
4372
4373 if (cleanup_done)
4374 continue;
4375
4376 drm_crtc_wait_one_vblank(crtc);
4377
4378 return true;
4379 }
4380
4381 return false;
4382 }
4383
4384 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4385 {
4386 u32 temp;
4387
4388 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4389
4390 mutex_lock(&dev_priv->sb_lock);
4391
4392 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4393 temp |= SBI_SSCCTL_DISABLE;
4394 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4395
4396 mutex_unlock(&dev_priv->sb_lock);
4397 }
4398
4399 /* Program iCLKIP clock to the desired frequency */
4400 static void lpt_program_iclkip(struct intel_crtc *crtc)
4401 {
4402 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4403 int clock = crtc->config->base.adjusted_mode.crtc_clock;
4404 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4405 u32 temp;
4406
4407 lpt_disable_iclkip(dev_priv);
4408
4409 /* The iCLK virtual clock root frequency is in MHz,
4410 * but the adjusted_mode->crtc_clock in in KHz. To get the
4411 * divisors, it is necessary to divide one by another, so we
4412 * convert the virtual clock precision to KHz here for higher
4413 * precision.
4414 */
4415 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4416 u32 iclk_virtual_root_freq = 172800 * 1000;
4417 u32 iclk_pi_range = 64;
4418 u32 desired_divisor;
4419
4420 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4421 clock << auxdiv);
4422 divsel = (desired_divisor / iclk_pi_range) - 2;
4423 phaseinc = desired_divisor % iclk_pi_range;
4424
4425 /*
4426 * Near 20MHz is a corner case which is
4427 * out of range for the 7-bit divisor
4428 */
4429 if (divsel <= 0x7f)
4430 break;
4431 }
4432
4433 /* This should not happen with any sane values */
4434 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4435 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4436 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4437 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4438
4439 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4440 clock,
4441 auxdiv,
4442 divsel,
4443 phasedir,
4444 phaseinc);
4445
4446 mutex_lock(&dev_priv->sb_lock);
4447
4448 /* Program SSCDIVINTPHASE6 */
4449 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4450 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4451 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4452 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4453 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4454 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4455 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4456 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4457
4458 /* Program SSCAUXDIV */
4459 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4460 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4461 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4462 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4463
4464 /* Enable modulator and associated divider */
4465 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4466 temp &= ~SBI_SSCCTL_DISABLE;
4467 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4468
4469 mutex_unlock(&dev_priv->sb_lock);
4470
4471 /* Wait for initialization time */
4472 udelay(24);
4473
4474 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4475 }
4476
4477 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4478 {
4479 u32 divsel, phaseinc, auxdiv;
4480 u32 iclk_virtual_root_freq = 172800 * 1000;
4481 u32 iclk_pi_range = 64;
4482 u32 desired_divisor;
4483 u32 temp;
4484
4485 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4486 return 0;
4487
4488 mutex_lock(&dev_priv->sb_lock);
4489
4490 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4491 if (temp & SBI_SSCCTL_DISABLE) {
4492 mutex_unlock(&dev_priv->sb_lock);
4493 return 0;
4494 }
4495
4496 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4497 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4498 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4499 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4500 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4501
4502 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4503 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4504 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4505
4506 mutex_unlock(&dev_priv->sb_lock);
4507
4508 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4509
4510 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4511 desired_divisor << auxdiv);
4512 }
4513
4514 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4515 enum pipe pch_transcoder)
4516 {
4517 struct drm_device *dev = crtc->base.dev;
4518 struct drm_i915_private *dev_priv = to_i915(dev);
4519 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4520
4521 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4522 I915_READ(HTOTAL(cpu_transcoder)));
4523 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4524 I915_READ(HBLANK(cpu_transcoder)));
4525 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4526 I915_READ(HSYNC(cpu_transcoder)));
4527
4528 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4529 I915_READ(VTOTAL(cpu_transcoder)));
4530 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4531 I915_READ(VBLANK(cpu_transcoder)));
4532 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4533 I915_READ(VSYNC(cpu_transcoder)));
4534 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4535 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4536 }
4537
4538 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4539 {
4540 struct drm_i915_private *dev_priv = to_i915(dev);
4541 uint32_t temp;
4542
4543 temp = I915_READ(SOUTH_CHICKEN1);
4544 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4545 return;
4546
4547 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4548 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4549
4550 temp &= ~FDI_BC_BIFURCATION_SELECT;
4551 if (enable)
4552 temp |= FDI_BC_BIFURCATION_SELECT;
4553
4554 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4555 I915_WRITE(SOUTH_CHICKEN1, temp);
4556 POSTING_READ(SOUTH_CHICKEN1);
4557 }
4558
4559 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4560 {
4561 struct drm_device *dev = intel_crtc->base.dev;
4562
4563 switch (intel_crtc->pipe) {
4564 case PIPE_A:
4565 break;
4566 case PIPE_B:
4567 if (intel_crtc->config->fdi_lanes > 2)
4568 cpt_set_fdi_bc_bifurcation(dev, false);
4569 else
4570 cpt_set_fdi_bc_bifurcation(dev, true);
4571
4572 break;
4573 case PIPE_C:
4574 cpt_set_fdi_bc_bifurcation(dev, true);
4575
4576 break;
4577 default:
4578 BUG();
4579 }
4580 }
4581
4582 /* Return which DP Port should be selected for Transcoder DP control */
4583 static enum port
4584 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4585 {
4586 struct drm_device *dev = crtc->base.dev;
4587 struct intel_encoder *encoder;
4588
4589 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4590 if (encoder->type == INTEL_OUTPUT_DP ||
4591 encoder->type == INTEL_OUTPUT_EDP)
4592 return enc_to_dig_port(&encoder->base)->port;
4593 }
4594
4595 return -1;
4596 }
4597
4598 /*
4599 * Enable PCH resources required for PCH ports:
4600 * - PCH PLLs
4601 * - FDI training & RX/TX
4602 * - update transcoder timings
4603 * - DP transcoding bits
4604 * - transcoder
4605 */
4606 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4607 {
4608 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4609 struct drm_device *dev = crtc->base.dev;
4610 struct drm_i915_private *dev_priv = to_i915(dev);
4611 int pipe = crtc->pipe;
4612 u32 temp;
4613
4614 assert_pch_transcoder_disabled(dev_priv, pipe);
4615
4616 if (IS_IVYBRIDGE(dev_priv))
4617 ivybridge_update_fdi_bc_bifurcation(crtc);
4618
4619 /* Write the TU size bits before fdi link training, so that error
4620 * detection works. */
4621 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4622 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4623
4624 /* For PCH output, training FDI link */
4625 dev_priv->display.fdi_link_train(crtc, crtc_state);
4626
4627 /* We need to program the right clock selection before writing the pixel
4628 * mutliplier into the DPLL. */
4629 if (HAS_PCH_CPT(dev_priv)) {
4630 u32 sel;
4631
4632 temp = I915_READ(PCH_DPLL_SEL);
4633 temp |= TRANS_DPLL_ENABLE(pipe);
4634 sel = TRANS_DPLLB_SEL(pipe);
4635 if (crtc_state->shared_dpll ==
4636 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4637 temp |= sel;
4638 else
4639 temp &= ~sel;
4640 I915_WRITE(PCH_DPLL_SEL, temp);
4641 }
4642
4643 /* XXX: pch pll's can be enabled any time before we enable the PCH
4644 * transcoder, and we actually should do this to not upset any PCH
4645 * transcoder that already use the clock when we share it.
4646 *
4647 * Note that enable_shared_dpll tries to do the right thing, but
4648 * get_shared_dpll unconditionally resets the pll - we need that to have
4649 * the right LVDS enable sequence. */
4650 intel_enable_shared_dpll(crtc);
4651
4652 /* set transcoder timing, panel must allow it */
4653 assert_panel_unlocked(dev_priv, pipe);
4654 ironlake_pch_transcoder_set_timings(crtc, pipe);
4655
4656 intel_fdi_normal_train(crtc);
4657
4658 /* For PCH DP, enable TRANS_DP_CTL */
4659 if (HAS_PCH_CPT(dev_priv) &&
4660 intel_crtc_has_dp_encoder(crtc_state)) {
4661 const struct drm_display_mode *adjusted_mode =
4662 &crtc_state->base.adjusted_mode;
4663 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4664 i915_reg_t reg = TRANS_DP_CTL(pipe);
4665 temp = I915_READ(reg);
4666 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4667 TRANS_DP_SYNC_MASK |
4668 TRANS_DP_BPC_MASK);
4669 temp |= TRANS_DP_OUTPUT_ENABLE;
4670 temp |= bpc << 9; /* same format but at 11:9 */
4671
4672 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4673 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4674 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4675 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4676
4677 switch (intel_trans_dp_port_sel(crtc)) {
4678 case PORT_B:
4679 temp |= TRANS_DP_PORT_SEL_B;
4680 break;
4681 case PORT_C:
4682 temp |= TRANS_DP_PORT_SEL_C;
4683 break;
4684 case PORT_D:
4685 temp |= TRANS_DP_PORT_SEL_D;
4686 break;
4687 default:
4688 BUG();
4689 }
4690
4691 I915_WRITE(reg, temp);
4692 }
4693
4694 ironlake_enable_pch_transcoder(dev_priv, pipe);
4695 }
4696
4697 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4698 {
4699 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4700 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4701 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4702
4703 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4704
4705 lpt_program_iclkip(crtc);
4706
4707 /* Set transcoder timing. */
4708 ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4709
4710 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4711 }
4712
4713 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4714 {
4715 struct drm_i915_private *dev_priv = to_i915(dev);
4716 i915_reg_t dslreg = PIPEDSL(pipe);
4717 u32 temp;
4718
4719 temp = I915_READ(dslreg);
4720 udelay(500);
4721 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4722 if (wait_for(I915_READ(dslreg) != temp, 5))
4723 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4724 }
4725 }
4726
4727 static int
4728 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4729 unsigned int scaler_user, int *scaler_id,
4730 int src_w, int src_h, int dst_w, int dst_h)
4731 {
4732 struct intel_crtc_scaler_state *scaler_state =
4733 &crtc_state->scaler_state;
4734 struct intel_crtc *intel_crtc =
4735 to_intel_crtc(crtc_state->base.crtc);
4736 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4737 const struct drm_display_mode *adjusted_mode =
4738 &crtc_state->base.adjusted_mode;
4739 int need_scaling;
4740
4741 /*
4742 * Src coordinates are already rotated by 270 degrees for
4743 * the 90/270 degree plane rotation cases (to match the
4744 * GTT mapping), hence no need to account for rotation here.
4745 */
4746 need_scaling = src_w != dst_w || src_h != dst_h;
4747
4748 if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
4749 need_scaling = true;
4750
4751 /*
4752 * Scaling/fitting not supported in IF-ID mode in GEN9+
4753 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4754 * Once NV12 is enabled, handle it here while allocating scaler
4755 * for NV12.
4756 */
4757 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
4758 need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4759 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4760 return -EINVAL;
4761 }
4762
4763 /*
4764 * if plane is being disabled or scaler is no more required or force detach
4765 * - free scaler binded to this plane/crtc
4766 * - in order to do this, update crtc->scaler_usage
4767 *
4768 * Here scaler state in crtc_state is set free so that
4769 * scaler can be assigned to other user. Actual register
4770 * update to free the scaler is done in plane/panel-fit programming.
4771 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4772 */
4773 if (force_detach || !need_scaling) {
4774 if (*scaler_id >= 0) {
4775 scaler_state->scaler_users &= ~(1 << scaler_user);
4776 scaler_state->scalers[*scaler_id].in_use = 0;
4777
4778 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4779 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4780 intel_crtc->pipe, scaler_user, *scaler_id,
4781 scaler_state->scaler_users);
4782 *scaler_id = -1;
4783 }
4784 return 0;
4785 }
4786
4787 /* range checks */
4788 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4789 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4790
4791 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4792 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4793 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4794 "size is out of scaler range\n",
4795 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4796 return -EINVAL;
4797 }
4798
4799 /* mark this plane as a scaler user in crtc_state */
4800 scaler_state->scaler_users |= (1 << scaler_user);
4801 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4802 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4803 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4804 scaler_state->scaler_users);
4805
4806 return 0;
4807 }
4808
4809 /**
4810 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4811 *
4812 * @state: crtc's scaler state
4813 *
4814 * Return
4815 * 0 - scaler_usage updated successfully
4816 * error - requested scaling cannot be supported or other error condition
4817 */
4818 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4819 {
4820 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4821
4822 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4823 &state->scaler_state.scaler_id,
4824 state->pipe_src_w, state->pipe_src_h,
4825 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4826 }
4827
4828 /**
4829 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4830 *
4831 * @state: crtc's scaler state
4832 * @plane_state: atomic plane state to update
4833 *
4834 * Return
4835 * 0 - scaler_usage updated successfully
4836 * error - requested scaling cannot be supported or other error condition
4837 */
4838 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4839 struct intel_plane_state *plane_state)
4840 {
4841
4842 struct intel_plane *intel_plane =
4843 to_intel_plane(plane_state->base.plane);
4844 struct drm_framebuffer *fb = plane_state->base.fb;
4845 int ret;
4846
4847 bool force_detach = !fb || !plane_state->base.visible;
4848
4849 ret = skl_update_scaler(crtc_state, force_detach,
4850 drm_plane_index(&intel_plane->base),
4851 &plane_state->scaler_id,
4852 drm_rect_width(&plane_state->base.src) >> 16,
4853 drm_rect_height(&plane_state->base.src) >> 16,
4854 drm_rect_width(&plane_state->base.dst),
4855 drm_rect_height(&plane_state->base.dst));
4856
4857 if (ret || plane_state->scaler_id < 0)
4858 return ret;
4859
4860 /* check colorkey */
4861 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4862 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4863 intel_plane->base.base.id,
4864 intel_plane->base.name);
4865 return -EINVAL;
4866 }
4867
4868 /* Check src format */
4869 switch (fb->format->format) {
4870 case DRM_FORMAT_RGB565:
4871 case DRM_FORMAT_XBGR8888:
4872 case DRM_FORMAT_XRGB8888:
4873 case DRM_FORMAT_ABGR8888:
4874 case DRM_FORMAT_ARGB8888:
4875 case DRM_FORMAT_XRGB2101010:
4876 case DRM_FORMAT_XBGR2101010:
4877 case DRM_FORMAT_YUYV:
4878 case DRM_FORMAT_YVYU:
4879 case DRM_FORMAT_UYVY:
4880 case DRM_FORMAT_VYUY:
4881 break;
4882 default:
4883 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4884 intel_plane->base.base.id, intel_plane->base.name,
4885 fb->base.id, fb->format->format);
4886 return -EINVAL;
4887 }
4888
4889 return 0;
4890 }
4891
4892 static void skylake_scaler_disable(struct intel_crtc *crtc)
4893 {
4894 int i;
4895
4896 for (i = 0; i < crtc->num_scalers; i++)
4897 skl_detach_scaler(crtc, i);
4898 }
4899
4900 static void skylake_pfit_enable(struct intel_crtc *crtc)
4901 {
4902 struct drm_device *dev = crtc->base.dev;
4903 struct drm_i915_private *dev_priv = to_i915(dev);
4904 int pipe = crtc->pipe;
4905 struct intel_crtc_scaler_state *scaler_state =
4906 &crtc->config->scaler_state;
4907
4908 if (crtc->config->pch_pfit.enabled) {
4909 int id;
4910
4911 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4912 return;
4913
4914 id = scaler_state->scaler_id;
4915 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4916 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4917 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4918 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4919 }
4920 }
4921
4922 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4923 {
4924 struct drm_device *dev = crtc->base.dev;
4925 struct drm_i915_private *dev_priv = to_i915(dev);
4926 int pipe = crtc->pipe;
4927
4928 if (crtc->config->pch_pfit.enabled) {
4929 /* Force use of hard-coded filter coefficients
4930 * as some pre-programmed values are broken,
4931 * e.g. x201.
4932 */
4933 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4934 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4935 PF_PIPE_SEL_IVB(pipe));
4936 else
4937 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4938 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4939 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4940 }
4941 }
4942
4943 void hsw_enable_ips(struct intel_crtc *crtc)
4944 {
4945 struct drm_device *dev = crtc->base.dev;
4946 struct drm_i915_private *dev_priv = to_i915(dev);
4947
4948 if (!crtc->config->ips_enabled)
4949 return;
4950
4951 /*
4952 * We can only enable IPS after we enable a plane and wait for a vblank
4953 * This function is called from post_plane_update, which is run after
4954 * a vblank wait.
4955 */
4956
4957 assert_plane_enabled(dev_priv, crtc->plane);
4958 if (IS_BROADWELL(dev_priv)) {
4959 mutex_lock(&dev_priv->rps.hw_lock);
4960 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4961 mutex_unlock(&dev_priv->rps.hw_lock);
4962 /* Quoting Art Runyan: "its not safe to expect any particular
4963 * value in IPS_CTL bit 31 after enabling IPS through the
4964 * mailbox." Moreover, the mailbox may return a bogus state,
4965 * so we need to just enable it and continue on.
4966 */
4967 } else {
4968 I915_WRITE(IPS_CTL, IPS_ENABLE);
4969 /* The bit only becomes 1 in the next vblank, so this wait here
4970 * is essentially intel_wait_for_vblank. If we don't have this
4971 * and don't wait for vblanks until the end of crtc_enable, then
4972 * the HW state readout code will complain that the expected
4973 * IPS_CTL value is not the one we read. */
4974 if (intel_wait_for_register(dev_priv,
4975 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4976 50))
4977 DRM_ERROR("Timed out waiting for IPS enable\n");
4978 }
4979 }
4980
4981 void hsw_disable_ips(struct intel_crtc *crtc)
4982 {
4983 struct drm_device *dev = crtc->base.dev;
4984 struct drm_i915_private *dev_priv = to_i915(dev);
4985
4986 if (!crtc->config->ips_enabled)
4987 return;
4988
4989 assert_plane_enabled(dev_priv, crtc->plane);
4990 if (IS_BROADWELL(dev_priv)) {
4991 mutex_lock(&dev_priv->rps.hw_lock);
4992 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4993 mutex_unlock(&dev_priv->rps.hw_lock);
4994 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4995 if (intel_wait_for_register(dev_priv,
4996 IPS_CTL, IPS_ENABLE, 0,
4997 42))
4998 DRM_ERROR("Timed out waiting for IPS disable\n");
4999 } else {
5000 I915_WRITE(IPS_CTL, 0);
5001 POSTING_READ(IPS_CTL);
5002 }
5003
5004 /* We need to wait for a vblank before we can disable the plane. */
5005 intel_wait_for_vblank(dev_priv, crtc->pipe);
5006 }
5007
5008 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
5009 {
5010 if (intel_crtc->overlay) {
5011 struct drm_device *dev = intel_crtc->base.dev;
5012
5013 mutex_lock(&dev->struct_mutex);
5014 (void) intel_overlay_switch_off(intel_crtc->overlay);
5015 mutex_unlock(&dev->struct_mutex);
5016 }
5017
5018 /* Let userspace switch the overlay on again. In most cases userspace
5019 * has to recompute where to put it anyway.
5020 */
5021 }
5022
5023 /**
5024 * intel_post_enable_primary - Perform operations after enabling primary plane
5025 * @crtc: the CRTC whose primary plane was just enabled
5026 *
5027 * Performs potentially sleeping operations that must be done after the primary
5028 * plane is enabled, such as updating FBC and IPS. Note that this may be
5029 * called due to an explicit primary plane update, or due to an implicit
5030 * re-enable that is caused when a sprite plane is updated to no longer
5031 * completely hide the primary plane.
5032 */
5033 static void
5034 intel_post_enable_primary(struct drm_crtc *crtc)
5035 {
5036 struct drm_device *dev = crtc->dev;
5037 struct drm_i915_private *dev_priv = to_i915(dev);
5038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5039 int pipe = intel_crtc->pipe;
5040
5041 /*
5042 * FIXME IPS should be fine as long as one plane is
5043 * enabled, but in practice it seems to have problems
5044 * when going from primary only to sprite only and vice
5045 * versa.
5046 */
5047 hsw_enable_ips(intel_crtc);
5048
5049 /*
5050 * Gen2 reports pipe underruns whenever all planes are disabled.
5051 * So don't enable underrun reporting before at least some planes
5052 * are enabled.
5053 * FIXME: Need to fix the logic to work when we turn off all planes
5054 * but leave the pipe running.
5055 */
5056 if (IS_GEN2(dev_priv))
5057 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5058
5059 /* Underruns don't always raise interrupts, so check manually. */
5060 intel_check_cpu_fifo_underruns(dev_priv);
5061 intel_check_pch_fifo_underruns(dev_priv);
5062 }
5063
5064 /* FIXME move all this to pre_plane_update() with proper state tracking */
5065 static void
5066 intel_pre_disable_primary(struct drm_crtc *crtc)
5067 {
5068 struct drm_device *dev = crtc->dev;
5069 struct drm_i915_private *dev_priv = to_i915(dev);
5070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5071 int pipe = intel_crtc->pipe;
5072
5073 /*
5074 * Gen2 reports pipe underruns whenever all planes are disabled.
5075 * So diasble underrun reporting before all the planes get disabled.
5076 * FIXME: Need to fix the logic to work when we turn off all planes
5077 * but leave the pipe running.
5078 */
5079 if (IS_GEN2(dev_priv))
5080 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5081
5082 /*
5083 * FIXME IPS should be fine as long as one plane is
5084 * enabled, but in practice it seems to have problems
5085 * when going from primary only to sprite only and vice
5086 * versa.
5087 */
5088 hsw_disable_ips(intel_crtc);
5089 }
5090
5091 /* FIXME get rid of this and use pre_plane_update */
5092 static void
5093 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5094 {
5095 struct drm_device *dev = crtc->dev;
5096 struct drm_i915_private *dev_priv = to_i915(dev);
5097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5098 int pipe = intel_crtc->pipe;
5099
5100 intel_pre_disable_primary(crtc);
5101
5102 /*
5103 * Vblank time updates from the shadow to live plane control register
5104 * are blocked if the memory self-refresh mode is active at that
5105 * moment. So to make sure the plane gets truly disabled, disable
5106 * first the self-refresh mode. The self-refresh enable bit in turn
5107 * will be checked/applied by the HW only at the next frame start
5108 * event which is after the vblank start event, so we need to have a
5109 * wait-for-vblank between disabling the plane and the pipe.
5110 */
5111 if (HAS_GMCH_DISPLAY(dev_priv) &&
5112 intel_set_memory_cxsr(dev_priv, false))
5113 intel_wait_for_vblank(dev_priv, pipe);
5114 }
5115
5116 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5117 {
5118 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5119 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5120 struct intel_crtc_state *pipe_config =
5121 to_intel_crtc_state(crtc->base.state);
5122 struct drm_plane *primary = crtc->base.primary;
5123 struct drm_plane_state *old_pri_state =
5124 drm_atomic_get_existing_plane_state(old_state, primary);
5125
5126 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5127
5128 if (pipe_config->update_wm_post && pipe_config->base.active)
5129 intel_update_watermarks(crtc);
5130
5131 if (old_pri_state) {
5132 struct intel_plane_state *primary_state =
5133 to_intel_plane_state(primary->state);
5134 struct intel_plane_state *old_primary_state =
5135 to_intel_plane_state(old_pri_state);
5136
5137 intel_fbc_post_update(crtc);
5138
5139 if (primary_state->base.visible &&
5140 (needs_modeset(&pipe_config->base) ||
5141 !old_primary_state->base.visible))
5142 intel_post_enable_primary(&crtc->base);
5143 }
5144 }
5145
5146 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5147 struct intel_crtc_state *pipe_config)
5148 {
5149 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5150 struct drm_device *dev = crtc->base.dev;
5151 struct drm_i915_private *dev_priv = to_i915(dev);
5152 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5153 struct drm_plane *primary = crtc->base.primary;
5154 struct drm_plane_state *old_pri_state =
5155 drm_atomic_get_existing_plane_state(old_state, primary);
5156 bool modeset = needs_modeset(&pipe_config->base);
5157 struct intel_atomic_state *old_intel_state =
5158 to_intel_atomic_state(old_state);
5159
5160 if (old_pri_state) {
5161 struct intel_plane_state *primary_state =
5162 to_intel_plane_state(primary->state);
5163 struct intel_plane_state *old_primary_state =
5164 to_intel_plane_state(old_pri_state);
5165
5166 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5167
5168 if (old_primary_state->base.visible &&
5169 (modeset || !primary_state->base.visible))
5170 intel_pre_disable_primary(&crtc->base);
5171 }
5172
5173 /*
5174 * Vblank time updates from the shadow to live plane control register
5175 * are blocked if the memory self-refresh mode is active at that
5176 * moment. So to make sure the plane gets truly disabled, disable
5177 * first the self-refresh mode. The self-refresh enable bit in turn
5178 * will be checked/applied by the HW only at the next frame start
5179 * event which is after the vblank start event, so we need to have a
5180 * wait-for-vblank between disabling the plane and the pipe.
5181 */
5182 if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5183 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5184 intel_wait_for_vblank(dev_priv, crtc->pipe);
5185
5186 /*
5187 * IVB workaround: must disable low power watermarks for at least
5188 * one frame before enabling scaling. LP watermarks can be re-enabled
5189 * when scaling is disabled.
5190 *
5191 * WaCxSRDisabledForSpriteScaling:ivb
5192 */
5193 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5194 intel_wait_for_vblank(dev_priv, crtc->pipe);
5195
5196 /*
5197 * If we're doing a modeset, we're done. No need to do any pre-vblank
5198 * watermark programming here.
5199 */
5200 if (needs_modeset(&pipe_config->base))
5201 return;
5202
5203 /*
5204 * For platforms that support atomic watermarks, program the
5205 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5206 * will be the intermediate values that are safe for both pre- and
5207 * post- vblank; when vblank happens, the 'active' values will be set
5208 * to the final 'target' values and we'll do this again to get the
5209 * optimal watermarks. For gen9+ platforms, the values we program here
5210 * will be the final target values which will get automatically latched
5211 * at vblank time; no further programming will be necessary.
5212 *
5213 * If a platform hasn't been transitioned to atomic watermarks yet,
5214 * we'll continue to update watermarks the old way, if flags tell
5215 * us to.
5216 */
5217 if (dev_priv->display.initial_watermarks != NULL)
5218 dev_priv->display.initial_watermarks(old_intel_state,
5219 pipe_config);
5220 else if (pipe_config->update_wm_pre)
5221 intel_update_watermarks(crtc);
5222 }
5223
5224 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5225 {
5226 struct drm_device *dev = crtc->dev;
5227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5228 struct drm_plane *p;
5229 int pipe = intel_crtc->pipe;
5230
5231 intel_crtc_dpms_overlay_disable(intel_crtc);
5232
5233 drm_for_each_plane_mask(p, dev, plane_mask)
5234 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
5235
5236 /*
5237 * FIXME: Once we grow proper nuclear flip support out of this we need
5238 * to compute the mask of flip planes precisely. For the time being
5239 * consider this a flip to a NULL plane.
5240 */
5241 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5242 }
5243
5244 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5245 struct intel_crtc_state *crtc_state,
5246 struct drm_atomic_state *old_state)
5247 {
5248 struct drm_connector_state *conn_state;
5249 struct drm_connector *conn;
5250 int i;
5251
5252 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5253 struct intel_encoder *encoder =
5254 to_intel_encoder(conn_state->best_encoder);
5255
5256 if (conn_state->crtc != crtc)
5257 continue;
5258
5259 if (encoder->pre_pll_enable)
5260 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5261 }
5262 }
5263
5264 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5265 struct intel_crtc_state *crtc_state,
5266 struct drm_atomic_state *old_state)
5267 {
5268 struct drm_connector_state *conn_state;
5269 struct drm_connector *conn;
5270 int i;
5271
5272 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5273 struct intel_encoder *encoder =
5274 to_intel_encoder(conn_state->best_encoder);
5275
5276 if (conn_state->crtc != crtc)
5277 continue;
5278
5279 if (encoder->pre_enable)
5280 encoder->pre_enable(encoder, crtc_state, conn_state);
5281 }
5282 }
5283
5284 static void intel_encoders_enable(struct drm_crtc *crtc,
5285 struct intel_crtc_state *crtc_state,
5286 struct drm_atomic_state *old_state)
5287 {
5288 struct drm_connector_state *conn_state;
5289 struct drm_connector *conn;
5290 int i;
5291
5292 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5293 struct intel_encoder *encoder =
5294 to_intel_encoder(conn_state->best_encoder);
5295
5296 if (conn_state->crtc != crtc)
5297 continue;
5298
5299 encoder->enable(encoder, crtc_state, conn_state);
5300 intel_opregion_notify_encoder(encoder, true);
5301 }
5302 }
5303
5304 static void intel_encoders_disable(struct drm_crtc *crtc,
5305 struct intel_crtc_state *old_crtc_state,
5306 struct drm_atomic_state *old_state)
5307 {
5308 struct drm_connector_state *old_conn_state;
5309 struct drm_connector *conn;
5310 int i;
5311
5312 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5313 struct intel_encoder *encoder =
5314 to_intel_encoder(old_conn_state->best_encoder);
5315
5316 if (old_conn_state->crtc != crtc)
5317 continue;
5318
5319 intel_opregion_notify_encoder(encoder, false);
5320 encoder->disable(encoder, old_crtc_state, old_conn_state);
5321 }
5322 }
5323
5324 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5325 struct intel_crtc_state *old_crtc_state,
5326 struct drm_atomic_state *old_state)
5327 {
5328 struct drm_connector_state *old_conn_state;
5329 struct drm_connector *conn;
5330 int i;
5331
5332 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5333 struct intel_encoder *encoder =
5334 to_intel_encoder(old_conn_state->best_encoder);
5335
5336 if (old_conn_state->crtc != crtc)
5337 continue;
5338
5339 if (encoder->post_disable)
5340 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5341 }
5342 }
5343
5344 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5345 struct intel_crtc_state *old_crtc_state,
5346 struct drm_atomic_state *old_state)
5347 {
5348 struct drm_connector_state *old_conn_state;
5349 struct drm_connector *conn;
5350 int i;
5351
5352 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5353 struct intel_encoder *encoder =
5354 to_intel_encoder(old_conn_state->best_encoder);
5355
5356 if (old_conn_state->crtc != crtc)
5357 continue;
5358
5359 if (encoder->post_pll_disable)
5360 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5361 }
5362 }
5363
5364 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5365 struct drm_atomic_state *old_state)
5366 {
5367 struct drm_crtc *crtc = pipe_config->base.crtc;
5368 struct drm_device *dev = crtc->dev;
5369 struct drm_i915_private *dev_priv = to_i915(dev);
5370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5371 int pipe = intel_crtc->pipe;
5372 struct intel_atomic_state *old_intel_state =
5373 to_intel_atomic_state(old_state);
5374
5375 if (WARN_ON(intel_crtc->active))
5376 return;
5377
5378 /*
5379 * Sometimes spurious CPU pipe underruns happen during FDI
5380 * training, at least with VGA+HDMI cloning. Suppress them.
5381 *
5382 * On ILK we get an occasional spurious CPU pipe underruns
5383 * between eDP port A enable and vdd enable. Also PCH port
5384 * enable seems to result in the occasional CPU pipe underrun.
5385 *
5386 * Spurious PCH underruns also occur during PCH enabling.
5387 */
5388 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5389 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5390 if (intel_crtc->config->has_pch_encoder)
5391 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5392
5393 if (intel_crtc->config->has_pch_encoder)
5394 intel_prepare_shared_dpll(intel_crtc);
5395
5396 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5397 intel_dp_set_m_n(intel_crtc, M1_N1);
5398
5399 intel_set_pipe_timings(intel_crtc);
5400 intel_set_pipe_src_size(intel_crtc);
5401
5402 if (intel_crtc->config->has_pch_encoder) {
5403 intel_cpu_transcoder_set_m_n(intel_crtc,
5404 &intel_crtc->config->fdi_m_n, NULL);
5405 }
5406
5407 ironlake_set_pipeconf(crtc);
5408
5409 intel_crtc->active = true;
5410
5411 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5412
5413 if (intel_crtc->config->has_pch_encoder) {
5414 /* Note: FDI PLL enabling _must_ be done before we enable the
5415 * cpu pipes, hence this is separate from all the other fdi/pch
5416 * enabling. */
5417 ironlake_fdi_pll_enable(intel_crtc);
5418 } else {
5419 assert_fdi_tx_disabled(dev_priv, pipe);
5420 assert_fdi_rx_disabled(dev_priv, pipe);
5421 }
5422
5423 ironlake_pfit_enable(intel_crtc);
5424
5425 /*
5426 * On ILK+ LUT must be loaded before the pipe is running but with
5427 * clocks enabled
5428 */
5429 intel_color_load_luts(&pipe_config->base);
5430
5431 if (dev_priv->display.initial_watermarks != NULL)
5432 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5433 intel_enable_pipe(intel_crtc);
5434
5435 if (intel_crtc->config->has_pch_encoder)
5436 ironlake_pch_enable(pipe_config);
5437
5438 assert_vblank_disabled(crtc);
5439 drm_crtc_vblank_on(crtc);
5440
5441 intel_encoders_enable(crtc, pipe_config, old_state);
5442
5443 if (HAS_PCH_CPT(dev_priv))
5444 cpt_verify_modeset(dev, intel_crtc->pipe);
5445
5446 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5447 if (intel_crtc->config->has_pch_encoder)
5448 intel_wait_for_vblank(dev_priv, pipe);
5449 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5450 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5451 }
5452
5453 /* IPS only exists on ULT machines and is tied to pipe A. */
5454 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5455 {
5456 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5457 }
5458
5459 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5460 struct drm_atomic_state *old_state)
5461 {
5462 struct drm_crtc *crtc = pipe_config->base.crtc;
5463 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5465 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5466 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5467 struct intel_atomic_state *old_intel_state =
5468 to_intel_atomic_state(old_state);
5469
5470 if (WARN_ON(intel_crtc->active))
5471 return;
5472
5473 if (intel_crtc->config->has_pch_encoder)
5474 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
5475
5476 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5477
5478 if (intel_crtc->config->shared_dpll)
5479 intel_enable_shared_dpll(intel_crtc);
5480
5481 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5482 intel_dp_set_m_n(intel_crtc, M1_N1);
5483
5484 if (!transcoder_is_dsi(cpu_transcoder))
5485 intel_set_pipe_timings(intel_crtc);
5486
5487 intel_set_pipe_src_size(intel_crtc);
5488
5489 if (cpu_transcoder != TRANSCODER_EDP &&
5490 !transcoder_is_dsi(cpu_transcoder)) {
5491 I915_WRITE(PIPE_MULT(cpu_transcoder),
5492 intel_crtc->config->pixel_multiplier - 1);
5493 }
5494
5495 if (intel_crtc->config->has_pch_encoder) {
5496 intel_cpu_transcoder_set_m_n(intel_crtc,
5497 &intel_crtc->config->fdi_m_n, NULL);
5498 }
5499
5500 if (!transcoder_is_dsi(cpu_transcoder))
5501 haswell_set_pipeconf(crtc);
5502
5503 haswell_set_pipemisc(crtc);
5504
5505 intel_color_set_csc(&pipe_config->base);
5506
5507 intel_crtc->active = true;
5508
5509 if (intel_crtc->config->has_pch_encoder)
5510 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5511 else
5512 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5513
5514 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5515
5516 if (intel_crtc->config->has_pch_encoder)
5517 dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
5518
5519 if (!transcoder_is_dsi(cpu_transcoder))
5520 intel_ddi_enable_pipe_clock(pipe_config);
5521
5522 if (INTEL_GEN(dev_priv) >= 9)
5523 skylake_pfit_enable(intel_crtc);
5524 else
5525 ironlake_pfit_enable(intel_crtc);
5526
5527 /*
5528 * On ILK+ LUT must be loaded before the pipe is running but with
5529 * clocks enabled
5530 */
5531 intel_color_load_luts(&pipe_config->base);
5532
5533 intel_ddi_set_pipe_settings(pipe_config);
5534 if (!transcoder_is_dsi(cpu_transcoder))
5535 intel_ddi_enable_transcoder_func(pipe_config);
5536
5537 if (dev_priv->display.initial_watermarks != NULL)
5538 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5539
5540 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5541 if (!transcoder_is_dsi(cpu_transcoder))
5542 intel_enable_pipe(intel_crtc);
5543
5544 if (intel_crtc->config->has_pch_encoder)
5545 lpt_pch_enable(pipe_config);
5546
5547 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5548 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5549
5550 assert_vblank_disabled(crtc);
5551 drm_crtc_vblank_on(crtc);
5552
5553 intel_encoders_enable(crtc, pipe_config, old_state);
5554
5555 if (intel_crtc->config->has_pch_encoder) {
5556 intel_wait_for_vblank(dev_priv, pipe);
5557 intel_wait_for_vblank(dev_priv, pipe);
5558 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5559 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5560 }
5561
5562 /* If we change the relative order between pipe/planes enabling, we need
5563 * to change the workaround. */
5564 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5565 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5566 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5567 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5568 }
5569 }
5570
5571 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5572 {
5573 struct drm_device *dev = crtc->base.dev;
5574 struct drm_i915_private *dev_priv = to_i915(dev);
5575 int pipe = crtc->pipe;
5576
5577 /* To avoid upsetting the power well on haswell only disable the pfit if
5578 * it's in use. The hw state code will make sure we get this right. */
5579 if (force || crtc->config->pch_pfit.enabled) {
5580 I915_WRITE(PF_CTL(pipe), 0);
5581 I915_WRITE(PF_WIN_POS(pipe), 0);
5582 I915_WRITE(PF_WIN_SZ(pipe), 0);
5583 }
5584 }
5585
5586 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5587 struct drm_atomic_state *old_state)
5588 {
5589 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5590 struct drm_device *dev = crtc->dev;
5591 struct drm_i915_private *dev_priv = to_i915(dev);
5592 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5593 int pipe = intel_crtc->pipe;
5594
5595 /*
5596 * Sometimes spurious CPU pipe underruns happen when the
5597 * pipe is already disabled, but FDI RX/TX is still enabled.
5598 * Happens at least with VGA+HDMI cloning. Suppress them.
5599 */
5600 if (intel_crtc->config->has_pch_encoder) {
5601 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5602 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5603 }
5604
5605 intel_encoders_disable(crtc, old_crtc_state, old_state);
5606
5607 drm_crtc_vblank_off(crtc);
5608 assert_vblank_disabled(crtc);
5609
5610 intel_disable_pipe(intel_crtc);
5611
5612 ironlake_pfit_disable(intel_crtc, false);
5613
5614 if (intel_crtc->config->has_pch_encoder)
5615 ironlake_fdi_disable(crtc);
5616
5617 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5618
5619 if (intel_crtc->config->has_pch_encoder) {
5620 ironlake_disable_pch_transcoder(dev_priv, pipe);
5621
5622 if (HAS_PCH_CPT(dev_priv)) {
5623 i915_reg_t reg;
5624 u32 temp;
5625
5626 /* disable TRANS_DP_CTL */
5627 reg = TRANS_DP_CTL(pipe);
5628 temp = I915_READ(reg);
5629 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5630 TRANS_DP_PORT_SEL_MASK);
5631 temp |= TRANS_DP_PORT_SEL_NONE;
5632 I915_WRITE(reg, temp);
5633
5634 /* disable DPLL_SEL */
5635 temp = I915_READ(PCH_DPLL_SEL);
5636 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5637 I915_WRITE(PCH_DPLL_SEL, temp);
5638 }
5639
5640 ironlake_fdi_pll_disable(intel_crtc);
5641 }
5642
5643 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5644 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5645 }
5646
5647 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5648 struct drm_atomic_state *old_state)
5649 {
5650 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5651 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5653 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5654
5655 if (intel_crtc->config->has_pch_encoder)
5656 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
5657
5658 intel_encoders_disable(crtc, old_crtc_state, old_state);
5659
5660 drm_crtc_vblank_off(crtc);
5661 assert_vblank_disabled(crtc);
5662
5663 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5664 if (!transcoder_is_dsi(cpu_transcoder))
5665 intel_disable_pipe(intel_crtc);
5666
5667 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5668 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5669
5670 if (!transcoder_is_dsi(cpu_transcoder))
5671 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5672
5673 if (INTEL_GEN(dev_priv) >= 9)
5674 skylake_scaler_disable(intel_crtc);
5675 else
5676 ironlake_pfit_disable(intel_crtc, false);
5677
5678 if (!transcoder_is_dsi(cpu_transcoder))
5679 intel_ddi_disable_pipe_clock(intel_crtc->config);
5680
5681 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5682
5683 if (old_crtc_state->has_pch_encoder)
5684 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5685 }
5686
5687 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5688 {
5689 struct drm_device *dev = crtc->base.dev;
5690 struct drm_i915_private *dev_priv = to_i915(dev);
5691 struct intel_crtc_state *pipe_config = crtc->config;
5692
5693 if (!pipe_config->gmch_pfit.control)
5694 return;
5695
5696 /*
5697 * The panel fitter should only be adjusted whilst the pipe is disabled,
5698 * according to register description and PRM.
5699 */
5700 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5701 assert_pipe_disabled(dev_priv, crtc->pipe);
5702
5703 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5704 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5705
5706 /* Border color in case we don't scale up to the full screen. Black by
5707 * default, change to something else for debugging. */
5708 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5709 }
5710
5711 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5712 {
5713 switch (port) {
5714 case PORT_A:
5715 return POWER_DOMAIN_PORT_DDI_A_LANES;
5716 case PORT_B:
5717 return POWER_DOMAIN_PORT_DDI_B_LANES;
5718 case PORT_C:
5719 return POWER_DOMAIN_PORT_DDI_C_LANES;
5720 case PORT_D:
5721 return POWER_DOMAIN_PORT_DDI_D_LANES;
5722 case PORT_E:
5723 return POWER_DOMAIN_PORT_DDI_E_LANES;
5724 default:
5725 MISSING_CASE(port);
5726 return POWER_DOMAIN_PORT_OTHER;
5727 }
5728 }
5729
5730 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5731 struct intel_crtc_state *crtc_state)
5732 {
5733 struct drm_device *dev = crtc->dev;
5734 struct drm_i915_private *dev_priv = to_i915(dev);
5735 struct drm_encoder *encoder;
5736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5737 enum pipe pipe = intel_crtc->pipe;
5738 u64 mask;
5739 enum transcoder transcoder = crtc_state->cpu_transcoder;
5740
5741 if (!crtc_state->base.active)
5742 return 0;
5743
5744 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5745 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5746 if (crtc_state->pch_pfit.enabled ||
5747 crtc_state->pch_pfit.force_thru)
5748 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5749
5750 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5751 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5752
5753 mask |= BIT_ULL(intel_encoder->power_domain);
5754 }
5755
5756 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5757 mask |= BIT(POWER_DOMAIN_AUDIO);
5758
5759 if (crtc_state->shared_dpll)
5760 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5761
5762 return mask;
5763 }
5764
5765 static u64
5766 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5767 struct intel_crtc_state *crtc_state)
5768 {
5769 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5771 enum intel_display_power_domain domain;
5772 u64 domains, new_domains, old_domains;
5773
5774 old_domains = intel_crtc->enabled_power_domains;
5775 intel_crtc->enabled_power_domains = new_domains =
5776 get_crtc_power_domains(crtc, crtc_state);
5777
5778 domains = new_domains & ~old_domains;
5779
5780 for_each_power_domain(domain, domains)
5781 intel_display_power_get(dev_priv, domain);
5782
5783 return old_domains & ~new_domains;
5784 }
5785
5786 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5787 u64 domains)
5788 {
5789 enum intel_display_power_domain domain;
5790
5791 for_each_power_domain(domain, domains)
5792 intel_display_power_put(dev_priv, domain);
5793 }
5794
5795 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5796 struct drm_atomic_state *old_state)
5797 {
5798 struct intel_atomic_state *old_intel_state =
5799 to_intel_atomic_state(old_state);
5800 struct drm_crtc *crtc = pipe_config->base.crtc;
5801 struct drm_device *dev = crtc->dev;
5802 struct drm_i915_private *dev_priv = to_i915(dev);
5803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5804 int pipe = intel_crtc->pipe;
5805
5806 if (WARN_ON(intel_crtc->active))
5807 return;
5808
5809 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5810 intel_dp_set_m_n(intel_crtc, M1_N1);
5811
5812 intel_set_pipe_timings(intel_crtc);
5813 intel_set_pipe_src_size(intel_crtc);
5814
5815 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5816 struct drm_i915_private *dev_priv = to_i915(dev);
5817
5818 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5819 I915_WRITE(CHV_CANVAS(pipe), 0);
5820 }
5821
5822 i9xx_set_pipeconf(intel_crtc);
5823
5824 intel_crtc->active = true;
5825
5826 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5827
5828 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5829
5830 if (IS_CHERRYVIEW(dev_priv)) {
5831 chv_prepare_pll(intel_crtc, intel_crtc->config);
5832 chv_enable_pll(intel_crtc, intel_crtc->config);
5833 } else {
5834 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5835 vlv_enable_pll(intel_crtc, intel_crtc->config);
5836 }
5837
5838 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5839
5840 i9xx_pfit_enable(intel_crtc);
5841
5842 intel_color_load_luts(&pipe_config->base);
5843
5844 dev_priv->display.initial_watermarks(old_intel_state,
5845 pipe_config);
5846 intel_enable_pipe(intel_crtc);
5847
5848 assert_vblank_disabled(crtc);
5849 drm_crtc_vblank_on(crtc);
5850
5851 intel_encoders_enable(crtc, pipe_config, old_state);
5852 }
5853
5854 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5855 {
5856 struct drm_device *dev = crtc->base.dev;
5857 struct drm_i915_private *dev_priv = to_i915(dev);
5858
5859 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5860 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5861 }
5862
5863 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5864 struct drm_atomic_state *old_state)
5865 {
5866 struct intel_atomic_state *old_intel_state =
5867 to_intel_atomic_state(old_state);
5868 struct drm_crtc *crtc = pipe_config->base.crtc;
5869 struct drm_device *dev = crtc->dev;
5870 struct drm_i915_private *dev_priv = to_i915(dev);
5871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5872 enum pipe pipe = intel_crtc->pipe;
5873
5874 if (WARN_ON(intel_crtc->active))
5875 return;
5876
5877 i9xx_set_pll_dividers(intel_crtc);
5878
5879 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5880 intel_dp_set_m_n(intel_crtc, M1_N1);
5881
5882 intel_set_pipe_timings(intel_crtc);
5883 intel_set_pipe_src_size(intel_crtc);
5884
5885 i9xx_set_pipeconf(intel_crtc);
5886
5887 intel_crtc->active = true;
5888
5889 if (!IS_GEN2(dev_priv))
5890 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5891
5892 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5893
5894 i9xx_enable_pll(intel_crtc);
5895
5896 i9xx_pfit_enable(intel_crtc);
5897
5898 intel_color_load_luts(&pipe_config->base);
5899
5900 if (dev_priv->display.initial_watermarks != NULL)
5901 dev_priv->display.initial_watermarks(old_intel_state,
5902 intel_crtc->config);
5903 else
5904 intel_update_watermarks(intel_crtc);
5905 intel_enable_pipe(intel_crtc);
5906
5907 assert_vblank_disabled(crtc);
5908 drm_crtc_vblank_on(crtc);
5909
5910 intel_encoders_enable(crtc, pipe_config, old_state);
5911 }
5912
5913 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5914 {
5915 struct drm_device *dev = crtc->base.dev;
5916 struct drm_i915_private *dev_priv = to_i915(dev);
5917
5918 if (!crtc->config->gmch_pfit.control)
5919 return;
5920
5921 assert_pipe_disabled(dev_priv, crtc->pipe);
5922
5923 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5924 I915_READ(PFIT_CONTROL));
5925 I915_WRITE(PFIT_CONTROL, 0);
5926 }
5927
5928 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5929 struct drm_atomic_state *old_state)
5930 {
5931 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5932 struct drm_device *dev = crtc->dev;
5933 struct drm_i915_private *dev_priv = to_i915(dev);
5934 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5935 int pipe = intel_crtc->pipe;
5936
5937 /*
5938 * On gen2 planes are double buffered but the pipe isn't, so we must
5939 * wait for planes to fully turn off before disabling the pipe.
5940 */
5941 if (IS_GEN2(dev_priv))
5942 intel_wait_for_vblank(dev_priv, pipe);
5943
5944 intel_encoders_disable(crtc, old_crtc_state, old_state);
5945
5946 drm_crtc_vblank_off(crtc);
5947 assert_vblank_disabled(crtc);
5948
5949 intel_disable_pipe(intel_crtc);
5950
5951 i9xx_pfit_disable(intel_crtc);
5952
5953 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5954
5955 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5956 if (IS_CHERRYVIEW(dev_priv))
5957 chv_disable_pll(dev_priv, pipe);
5958 else if (IS_VALLEYVIEW(dev_priv))
5959 vlv_disable_pll(dev_priv, pipe);
5960 else
5961 i9xx_disable_pll(intel_crtc);
5962 }
5963
5964 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5965
5966 if (!IS_GEN2(dev_priv))
5967 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5968
5969 if (!dev_priv->display.initial_watermarks)
5970 intel_update_watermarks(intel_crtc);
5971
5972 /* clock the pipe down to 640x480@60 to potentially save power */
5973 if (IS_I830(dev_priv))
5974 i830_enable_pipe(dev_priv, pipe);
5975 }
5976
5977 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
5978 struct drm_modeset_acquire_ctx *ctx)
5979 {
5980 struct intel_encoder *encoder;
5981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5982 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5983 enum intel_display_power_domain domain;
5984 u64 domains;
5985 struct drm_atomic_state *state;
5986 struct intel_crtc_state *crtc_state;
5987 int ret;
5988
5989 if (!intel_crtc->active)
5990 return;
5991
5992 if (crtc->primary->state->visible) {
5993 intel_pre_disable_primary_noatomic(crtc);
5994
5995 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5996 crtc->primary->state->visible = false;
5997 }
5998
5999 state = drm_atomic_state_alloc(crtc->dev);
6000 if (!state) {
6001 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
6002 crtc->base.id, crtc->name);
6003 return;
6004 }
6005
6006 state->acquire_ctx = ctx;
6007
6008 /* Everything's already locked, -EDEADLK can't happen. */
6009 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6010 ret = drm_atomic_add_affected_connectors(state, crtc);
6011
6012 WARN_ON(IS_ERR(crtc_state) || ret);
6013
6014 dev_priv->display.crtc_disable(crtc_state, state);
6015
6016 drm_atomic_state_put(state);
6017
6018 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6019 crtc->base.id, crtc->name);
6020
6021 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6022 crtc->state->active = false;
6023 intel_crtc->active = false;
6024 crtc->enabled = false;
6025 crtc->state->connector_mask = 0;
6026 crtc->state->encoder_mask = 0;
6027
6028 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6029 encoder->base.crtc = NULL;
6030
6031 intel_fbc_disable(intel_crtc);
6032 intel_update_watermarks(intel_crtc);
6033 intel_disable_shared_dpll(intel_crtc);
6034
6035 domains = intel_crtc->enabled_power_domains;
6036 for_each_power_domain(domain, domains)
6037 intel_display_power_put(dev_priv, domain);
6038 intel_crtc->enabled_power_domains = 0;
6039
6040 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6041 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6042 }
6043
6044 /*
6045 * turn all crtc's off, but do not adjust state
6046 * This has to be paired with a call to intel_modeset_setup_hw_state.
6047 */
6048 int intel_display_suspend(struct drm_device *dev)
6049 {
6050 struct drm_i915_private *dev_priv = to_i915(dev);
6051 struct drm_atomic_state *state;
6052 int ret;
6053
6054 state = drm_atomic_helper_suspend(dev);
6055 ret = PTR_ERR_OR_ZERO(state);
6056 if (ret)
6057 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6058 else
6059 dev_priv->modeset_restore_state = state;
6060 return ret;
6061 }
6062
6063 void intel_encoder_destroy(struct drm_encoder *encoder)
6064 {
6065 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6066
6067 drm_encoder_cleanup(encoder);
6068 kfree(intel_encoder);
6069 }
6070
6071 /* Cross check the actual hw state with our own modeset state tracking (and it's
6072 * internal consistency). */
6073 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
6074 struct drm_connector_state *conn_state)
6075 {
6076 struct intel_connector *connector = to_intel_connector(conn_state->connector);
6077
6078 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6079 connector->base.base.id,
6080 connector->base.name);
6081
6082 if (connector->get_hw_state(connector)) {
6083 struct intel_encoder *encoder = connector->encoder;
6084
6085 I915_STATE_WARN(!crtc_state,
6086 "connector enabled without attached crtc\n");
6087
6088 if (!crtc_state)
6089 return;
6090
6091 I915_STATE_WARN(!crtc_state->active,
6092 "connector is active, but attached crtc isn't\n");
6093
6094 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6095 return;
6096
6097 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6098 "atomic encoder doesn't match attached encoder\n");
6099
6100 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6101 "attached encoder crtc differs from connector crtc\n");
6102 } else {
6103 I915_STATE_WARN(crtc_state && crtc_state->active,
6104 "attached crtc is active, but connector isn't\n");
6105 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
6106 "best encoder set without crtc!\n");
6107 }
6108 }
6109
6110 int intel_connector_init(struct intel_connector *connector)
6111 {
6112 struct intel_digital_connector_state *conn_state;
6113
6114 /*
6115 * Allocate enough memory to hold intel_digital_connector_state,
6116 * This might be a few bytes too many, but for connectors that don't
6117 * need it we'll free the state and allocate a smaller one on the first
6118 * succesful commit anyway.
6119 */
6120 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
6121 if (!conn_state)
6122 return -ENOMEM;
6123
6124 __drm_atomic_helper_connector_reset(&connector->base,
6125 &conn_state->base);
6126
6127 return 0;
6128 }
6129
6130 struct intel_connector *intel_connector_alloc(void)
6131 {
6132 struct intel_connector *connector;
6133
6134 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6135 if (!connector)
6136 return NULL;
6137
6138 if (intel_connector_init(connector) < 0) {
6139 kfree(connector);
6140 return NULL;
6141 }
6142
6143 return connector;
6144 }
6145
6146 /* Simple connector->get_hw_state implementation for encoders that support only
6147 * one connector and no cloning and hence the encoder state determines the state
6148 * of the connector. */
6149 bool intel_connector_get_hw_state(struct intel_connector *connector)
6150 {
6151 enum pipe pipe = 0;
6152 struct intel_encoder *encoder = connector->encoder;
6153
6154 return encoder->get_hw_state(encoder, &pipe);
6155 }
6156
6157 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6158 {
6159 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6160 return crtc_state->fdi_lanes;
6161
6162 return 0;
6163 }
6164
6165 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6166 struct intel_crtc_state *pipe_config)
6167 {
6168 struct drm_i915_private *dev_priv = to_i915(dev);
6169 struct drm_atomic_state *state = pipe_config->base.state;
6170 struct intel_crtc *other_crtc;
6171 struct intel_crtc_state *other_crtc_state;
6172
6173 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6174 pipe_name(pipe), pipe_config->fdi_lanes);
6175 if (pipe_config->fdi_lanes > 4) {
6176 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6177 pipe_name(pipe), pipe_config->fdi_lanes);
6178 return -EINVAL;
6179 }
6180
6181 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6182 if (pipe_config->fdi_lanes > 2) {
6183 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6184 pipe_config->fdi_lanes);
6185 return -EINVAL;
6186 } else {
6187 return 0;
6188 }
6189 }
6190
6191 if (INTEL_INFO(dev_priv)->num_pipes == 2)
6192 return 0;
6193
6194 /* Ivybridge 3 pipe is really complicated */
6195 switch (pipe) {
6196 case PIPE_A:
6197 return 0;
6198 case PIPE_B:
6199 if (pipe_config->fdi_lanes <= 2)
6200 return 0;
6201
6202 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6203 other_crtc_state =
6204 intel_atomic_get_crtc_state(state, other_crtc);
6205 if (IS_ERR(other_crtc_state))
6206 return PTR_ERR(other_crtc_state);
6207
6208 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6209 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6210 pipe_name(pipe), pipe_config->fdi_lanes);
6211 return -EINVAL;
6212 }
6213 return 0;
6214 case PIPE_C:
6215 if (pipe_config->fdi_lanes > 2) {
6216 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6217 pipe_name(pipe), pipe_config->fdi_lanes);
6218 return -EINVAL;
6219 }
6220
6221 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6222 other_crtc_state =
6223 intel_atomic_get_crtc_state(state, other_crtc);
6224 if (IS_ERR(other_crtc_state))
6225 return PTR_ERR(other_crtc_state);
6226
6227 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6228 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6229 return -EINVAL;
6230 }
6231 return 0;
6232 default:
6233 BUG();
6234 }
6235 }
6236
6237 #define RETRY 1
6238 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6239 struct intel_crtc_state *pipe_config)
6240 {
6241 struct drm_device *dev = intel_crtc->base.dev;
6242 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6243 int lane, link_bw, fdi_dotclock, ret;
6244 bool needs_recompute = false;
6245
6246 retry:
6247 /* FDI is a binary signal running at ~2.7GHz, encoding
6248 * each output octet as 10 bits. The actual frequency
6249 * is stored as a divider into a 100MHz clock, and the
6250 * mode pixel clock is stored in units of 1KHz.
6251 * Hence the bw of each lane in terms of the mode signal
6252 * is:
6253 */
6254 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6255
6256 fdi_dotclock = adjusted_mode->crtc_clock;
6257
6258 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6259 pipe_config->pipe_bpp);
6260
6261 pipe_config->fdi_lanes = lane;
6262
6263 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6264 link_bw, &pipe_config->fdi_m_n, false);
6265
6266 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6267 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6268 pipe_config->pipe_bpp -= 2*3;
6269 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6270 pipe_config->pipe_bpp);
6271 needs_recompute = true;
6272 pipe_config->bw_constrained = true;
6273
6274 goto retry;
6275 }
6276
6277 if (needs_recompute)
6278 return RETRY;
6279
6280 return ret;
6281 }
6282
6283 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6284 struct intel_crtc_state *pipe_config)
6285 {
6286 if (pipe_config->pipe_bpp > 24)
6287 return false;
6288
6289 /* HSW can handle pixel rate up to cdclk? */
6290 if (IS_HASWELL(dev_priv))
6291 return true;
6292
6293 /*
6294 * We compare against max which means we must take
6295 * the increased cdclk requirement into account when
6296 * calculating the new cdclk.
6297 *
6298 * Should measure whether using a lower cdclk w/o IPS
6299 */
6300 return pipe_config->pixel_rate <=
6301 dev_priv->max_cdclk_freq * 95 / 100;
6302 }
6303
6304 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6305 struct intel_crtc_state *pipe_config)
6306 {
6307 struct drm_device *dev = crtc->base.dev;
6308 struct drm_i915_private *dev_priv = to_i915(dev);
6309
6310 pipe_config->ips_enabled = i915.enable_ips &&
6311 hsw_crtc_supports_ips(crtc) &&
6312 pipe_config_supports_ips(dev_priv, pipe_config);
6313 }
6314
6315 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6316 {
6317 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6318
6319 /* GDG double wide on either pipe, otherwise pipe A only */
6320 return INTEL_INFO(dev_priv)->gen < 4 &&
6321 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6322 }
6323
6324 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6325 {
6326 uint32_t pixel_rate;
6327
6328 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6329
6330 /*
6331 * We only use IF-ID interlacing. If we ever use
6332 * PF-ID we'll need to adjust the pixel_rate here.
6333 */
6334
6335 if (pipe_config->pch_pfit.enabled) {
6336 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6337 uint32_t pfit_size = pipe_config->pch_pfit.size;
6338
6339 pipe_w = pipe_config->pipe_src_w;
6340 pipe_h = pipe_config->pipe_src_h;
6341
6342 pfit_w = (pfit_size >> 16) & 0xFFFF;
6343 pfit_h = pfit_size & 0xFFFF;
6344 if (pipe_w < pfit_w)
6345 pipe_w = pfit_w;
6346 if (pipe_h < pfit_h)
6347 pipe_h = pfit_h;
6348
6349 if (WARN_ON(!pfit_w || !pfit_h))
6350 return pixel_rate;
6351
6352 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6353 pfit_w * pfit_h);
6354 }
6355
6356 return pixel_rate;
6357 }
6358
6359 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6360 {
6361 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6362
6363 if (HAS_GMCH_DISPLAY(dev_priv))
6364 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6365 crtc_state->pixel_rate =
6366 crtc_state->base.adjusted_mode.crtc_clock;
6367 else
6368 crtc_state->pixel_rate =
6369 ilk_pipe_pixel_rate(crtc_state);
6370 }
6371
6372 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6373 struct intel_crtc_state *pipe_config)
6374 {
6375 struct drm_device *dev = crtc->base.dev;
6376 struct drm_i915_private *dev_priv = to_i915(dev);
6377 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6378 int clock_limit = dev_priv->max_dotclk_freq;
6379
6380 if (INTEL_GEN(dev_priv) < 4) {
6381 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6382
6383 /*
6384 * Enable double wide mode when the dot clock
6385 * is > 90% of the (display) core speed.
6386 */
6387 if (intel_crtc_supports_double_wide(crtc) &&
6388 adjusted_mode->crtc_clock > clock_limit) {
6389 clock_limit = dev_priv->max_dotclk_freq;
6390 pipe_config->double_wide = true;
6391 }
6392 }
6393
6394 if (adjusted_mode->crtc_clock > clock_limit) {
6395 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6396 adjusted_mode->crtc_clock, clock_limit,
6397 yesno(pipe_config->double_wide));
6398 return -EINVAL;
6399 }
6400
6401 if (pipe_config->ycbcr420 && pipe_config->base.ctm) {
6402 /*
6403 * There is only one pipe CSC unit per pipe, and we need that
6404 * for output conversion from RGB->YCBCR. So if CTM is already
6405 * applied we can't support YCBCR420 output.
6406 */
6407 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
6408 return -EINVAL;
6409 }
6410
6411 /*
6412 * Pipe horizontal size must be even in:
6413 * - DVO ganged mode
6414 * - LVDS dual channel mode
6415 * - Double wide pipe
6416 */
6417 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6418 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6419 pipe_config->pipe_src_w &= ~1;
6420
6421 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6422 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6423 */
6424 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6425 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6426 return -EINVAL;
6427
6428 intel_crtc_compute_pixel_rate(pipe_config);
6429
6430 if (HAS_IPS(dev_priv))
6431 hsw_compute_ips_config(crtc, pipe_config);
6432
6433 if (pipe_config->has_pch_encoder)
6434 return ironlake_fdi_compute_config(crtc, pipe_config);
6435
6436 return 0;
6437 }
6438
6439 static void
6440 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6441 {
6442 while (*num > DATA_LINK_M_N_MASK ||
6443 *den > DATA_LINK_M_N_MASK) {
6444 *num >>= 1;
6445 *den >>= 1;
6446 }
6447 }
6448
6449 static void compute_m_n(unsigned int m, unsigned int n,
6450 uint32_t *ret_m, uint32_t *ret_n,
6451 bool reduce_m_n)
6452 {
6453 /*
6454 * Reduce M/N as much as possible without loss in precision. Several DP
6455 * dongles in particular seem to be fussy about too large *link* M/N
6456 * values. The passed in values are more likely to have the least
6457 * significant bits zero than M after rounding below, so do this first.
6458 */
6459 if (reduce_m_n) {
6460 while ((m & 1) == 0 && (n & 1) == 0) {
6461 m >>= 1;
6462 n >>= 1;
6463 }
6464 }
6465
6466 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6467 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6468 intel_reduce_m_n_ratio(ret_m, ret_n);
6469 }
6470
6471 void
6472 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6473 int pixel_clock, int link_clock,
6474 struct intel_link_m_n *m_n,
6475 bool reduce_m_n)
6476 {
6477 m_n->tu = 64;
6478
6479 compute_m_n(bits_per_pixel * pixel_clock,
6480 link_clock * nlanes * 8,
6481 &m_n->gmch_m, &m_n->gmch_n,
6482 reduce_m_n);
6483
6484 compute_m_n(pixel_clock, link_clock,
6485 &m_n->link_m, &m_n->link_n,
6486 reduce_m_n);
6487 }
6488
6489 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6490 {
6491 if (i915.panel_use_ssc >= 0)
6492 return i915.panel_use_ssc != 0;
6493 return dev_priv->vbt.lvds_use_ssc
6494 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6495 }
6496
6497 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6498 {
6499 return (1 << dpll->n) << 16 | dpll->m2;
6500 }
6501
6502 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6503 {
6504 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6505 }
6506
6507 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6508 struct intel_crtc_state *crtc_state,
6509 struct dpll *reduced_clock)
6510 {
6511 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6512 u32 fp, fp2 = 0;
6513
6514 if (IS_PINEVIEW(dev_priv)) {
6515 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6516 if (reduced_clock)
6517 fp2 = pnv_dpll_compute_fp(reduced_clock);
6518 } else {
6519 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6520 if (reduced_clock)
6521 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6522 }
6523
6524 crtc_state->dpll_hw_state.fp0 = fp;
6525
6526 crtc->lowfreq_avail = false;
6527 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6528 reduced_clock) {
6529 crtc_state->dpll_hw_state.fp1 = fp2;
6530 crtc->lowfreq_avail = true;
6531 } else {
6532 crtc_state->dpll_hw_state.fp1 = fp;
6533 }
6534 }
6535
6536 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6537 pipe)
6538 {
6539 u32 reg_val;
6540
6541 /*
6542 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6543 * and set it to a reasonable value instead.
6544 */
6545 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6546 reg_val &= 0xffffff00;
6547 reg_val |= 0x00000030;
6548 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6549
6550 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6551 reg_val &= 0x00ffffff;
6552 reg_val |= 0x8c000000;
6553 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6554
6555 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6556 reg_val &= 0xffffff00;
6557 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6558
6559 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6560 reg_val &= 0x00ffffff;
6561 reg_val |= 0xb0000000;
6562 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6563 }
6564
6565 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6566 struct intel_link_m_n *m_n)
6567 {
6568 struct drm_device *dev = crtc->base.dev;
6569 struct drm_i915_private *dev_priv = to_i915(dev);
6570 int pipe = crtc->pipe;
6571
6572 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6573 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6574 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6575 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6576 }
6577
6578 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6579 struct intel_link_m_n *m_n,
6580 struct intel_link_m_n *m2_n2)
6581 {
6582 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6583 int pipe = crtc->pipe;
6584 enum transcoder transcoder = crtc->config->cpu_transcoder;
6585
6586 if (INTEL_GEN(dev_priv) >= 5) {
6587 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6588 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6589 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6590 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6591 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6592 * for gen < 8) and if DRRS is supported (to make sure the
6593 * registers are not unnecessarily accessed).
6594 */
6595 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6596 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6597 I915_WRITE(PIPE_DATA_M2(transcoder),
6598 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6599 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6600 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6601 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6602 }
6603 } else {
6604 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6605 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6606 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6607 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6608 }
6609 }
6610
6611 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6612 {
6613 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6614
6615 if (m_n == M1_N1) {
6616 dp_m_n = &crtc->config->dp_m_n;
6617 dp_m2_n2 = &crtc->config->dp_m2_n2;
6618 } else if (m_n == M2_N2) {
6619
6620 /*
6621 * M2_N2 registers are not supported. Hence m2_n2 divider value
6622 * needs to be programmed into M1_N1.
6623 */
6624 dp_m_n = &crtc->config->dp_m2_n2;
6625 } else {
6626 DRM_ERROR("Unsupported divider value\n");
6627 return;
6628 }
6629
6630 if (crtc->config->has_pch_encoder)
6631 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6632 else
6633 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6634 }
6635
6636 static void vlv_compute_dpll(struct intel_crtc *crtc,
6637 struct intel_crtc_state *pipe_config)
6638 {
6639 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6640 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6641 if (crtc->pipe != PIPE_A)
6642 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6643
6644 /* DPLL not used with DSI, but still need the rest set up */
6645 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6646 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6647 DPLL_EXT_BUFFER_ENABLE_VLV;
6648
6649 pipe_config->dpll_hw_state.dpll_md =
6650 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6651 }
6652
6653 static void chv_compute_dpll(struct intel_crtc *crtc,
6654 struct intel_crtc_state *pipe_config)
6655 {
6656 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6657 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6658 if (crtc->pipe != PIPE_A)
6659 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6660
6661 /* DPLL not used with DSI, but still need the rest set up */
6662 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6663 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6664
6665 pipe_config->dpll_hw_state.dpll_md =
6666 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6667 }
6668
6669 static void vlv_prepare_pll(struct intel_crtc *crtc,
6670 const struct intel_crtc_state *pipe_config)
6671 {
6672 struct drm_device *dev = crtc->base.dev;
6673 struct drm_i915_private *dev_priv = to_i915(dev);
6674 enum pipe pipe = crtc->pipe;
6675 u32 mdiv;
6676 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6677 u32 coreclk, reg_val;
6678
6679 /* Enable Refclk */
6680 I915_WRITE(DPLL(pipe),
6681 pipe_config->dpll_hw_state.dpll &
6682 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6683
6684 /* No need to actually set up the DPLL with DSI */
6685 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6686 return;
6687
6688 mutex_lock(&dev_priv->sb_lock);
6689
6690 bestn = pipe_config->dpll.n;
6691 bestm1 = pipe_config->dpll.m1;
6692 bestm2 = pipe_config->dpll.m2;
6693 bestp1 = pipe_config->dpll.p1;
6694 bestp2 = pipe_config->dpll.p2;
6695
6696 /* See eDP HDMI DPIO driver vbios notes doc */
6697
6698 /* PLL B needs special handling */
6699 if (pipe == PIPE_B)
6700 vlv_pllb_recal_opamp(dev_priv, pipe);
6701
6702 /* Set up Tx target for periodic Rcomp update */
6703 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6704
6705 /* Disable target IRef on PLL */
6706 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6707 reg_val &= 0x00ffffff;
6708 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6709
6710 /* Disable fast lock */
6711 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6712
6713 /* Set idtafcrecal before PLL is enabled */
6714 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6715 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6716 mdiv |= ((bestn << DPIO_N_SHIFT));
6717 mdiv |= (1 << DPIO_K_SHIFT);
6718
6719 /*
6720 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6721 * but we don't support that).
6722 * Note: don't use the DAC post divider as it seems unstable.
6723 */
6724 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6725 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6726
6727 mdiv |= DPIO_ENABLE_CALIBRATION;
6728 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6729
6730 /* Set HBR and RBR LPF coefficients */
6731 if (pipe_config->port_clock == 162000 ||
6732 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6733 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6734 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6735 0x009f0003);
6736 else
6737 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6738 0x00d0000f);
6739
6740 if (intel_crtc_has_dp_encoder(pipe_config)) {
6741 /* Use SSC source */
6742 if (pipe == PIPE_A)
6743 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6744 0x0df40000);
6745 else
6746 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6747 0x0df70000);
6748 } else { /* HDMI or VGA */
6749 /* Use bend source */
6750 if (pipe == PIPE_A)
6751 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6752 0x0df70000);
6753 else
6754 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6755 0x0df40000);
6756 }
6757
6758 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6759 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6760 if (intel_crtc_has_dp_encoder(crtc->config))
6761 coreclk |= 0x01000000;
6762 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6763
6764 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6765 mutex_unlock(&dev_priv->sb_lock);
6766 }
6767
6768 static void chv_prepare_pll(struct intel_crtc *crtc,
6769 const struct intel_crtc_state *pipe_config)
6770 {
6771 struct drm_device *dev = crtc->base.dev;
6772 struct drm_i915_private *dev_priv = to_i915(dev);
6773 enum pipe pipe = crtc->pipe;
6774 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6775 u32 loopfilter, tribuf_calcntr;
6776 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6777 u32 dpio_val;
6778 int vco;
6779
6780 /* Enable Refclk and SSC */
6781 I915_WRITE(DPLL(pipe),
6782 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6783
6784 /* No need to actually set up the DPLL with DSI */
6785 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6786 return;
6787
6788 bestn = pipe_config->dpll.n;
6789 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6790 bestm1 = pipe_config->dpll.m1;
6791 bestm2 = pipe_config->dpll.m2 >> 22;
6792 bestp1 = pipe_config->dpll.p1;
6793 bestp2 = pipe_config->dpll.p2;
6794 vco = pipe_config->dpll.vco;
6795 dpio_val = 0;
6796 loopfilter = 0;
6797
6798 mutex_lock(&dev_priv->sb_lock);
6799
6800 /* p1 and p2 divider */
6801 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6802 5 << DPIO_CHV_S1_DIV_SHIFT |
6803 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6804 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6805 1 << DPIO_CHV_K_DIV_SHIFT);
6806
6807 /* Feedback post-divider - m2 */
6808 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6809
6810 /* Feedback refclk divider - n and m1 */
6811 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6812 DPIO_CHV_M1_DIV_BY_2 |
6813 1 << DPIO_CHV_N_DIV_SHIFT);
6814
6815 /* M2 fraction division */
6816 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6817
6818 /* M2 fraction division enable */
6819 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6820 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6821 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6822 if (bestm2_frac)
6823 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6824 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6825
6826 /* Program digital lock detect threshold */
6827 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6828 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6829 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6830 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6831 if (!bestm2_frac)
6832 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6833 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6834
6835 /* Loop filter */
6836 if (vco == 5400000) {
6837 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6838 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6839 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6840 tribuf_calcntr = 0x9;
6841 } else if (vco <= 6200000) {
6842 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6843 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6844 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6845 tribuf_calcntr = 0x9;
6846 } else if (vco <= 6480000) {
6847 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6848 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6849 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6850 tribuf_calcntr = 0x8;
6851 } else {
6852 /* Not supported. Apply the same limits as in the max case */
6853 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6854 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6855 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6856 tribuf_calcntr = 0;
6857 }
6858 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6859
6860 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6861 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6862 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6863 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6864
6865 /* AFC Recal */
6866 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6867 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6868 DPIO_AFC_RECAL);
6869
6870 mutex_unlock(&dev_priv->sb_lock);
6871 }
6872
6873 /**
6874 * vlv_force_pll_on - forcibly enable just the PLL
6875 * @dev_priv: i915 private structure
6876 * @pipe: pipe PLL to enable
6877 * @dpll: PLL configuration
6878 *
6879 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6880 * in cases where we need the PLL enabled even when @pipe is not going to
6881 * be enabled.
6882 */
6883 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6884 const struct dpll *dpll)
6885 {
6886 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6887 struct intel_crtc_state *pipe_config;
6888
6889 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6890 if (!pipe_config)
6891 return -ENOMEM;
6892
6893 pipe_config->base.crtc = &crtc->base;
6894 pipe_config->pixel_multiplier = 1;
6895 pipe_config->dpll = *dpll;
6896
6897 if (IS_CHERRYVIEW(dev_priv)) {
6898 chv_compute_dpll(crtc, pipe_config);
6899 chv_prepare_pll(crtc, pipe_config);
6900 chv_enable_pll(crtc, pipe_config);
6901 } else {
6902 vlv_compute_dpll(crtc, pipe_config);
6903 vlv_prepare_pll(crtc, pipe_config);
6904 vlv_enable_pll(crtc, pipe_config);
6905 }
6906
6907 kfree(pipe_config);
6908
6909 return 0;
6910 }
6911
6912 /**
6913 * vlv_force_pll_off - forcibly disable just the PLL
6914 * @dev_priv: i915 private structure
6915 * @pipe: pipe PLL to disable
6916 *
6917 * Disable the PLL for @pipe. To be used in cases where we need
6918 * the PLL enabled even when @pipe is not going to be enabled.
6919 */
6920 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6921 {
6922 if (IS_CHERRYVIEW(dev_priv))
6923 chv_disable_pll(dev_priv, pipe);
6924 else
6925 vlv_disable_pll(dev_priv, pipe);
6926 }
6927
6928 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6929 struct intel_crtc_state *crtc_state,
6930 struct dpll *reduced_clock)
6931 {
6932 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6933 u32 dpll;
6934 struct dpll *clock = &crtc_state->dpll;
6935
6936 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6937
6938 dpll = DPLL_VGA_MODE_DIS;
6939
6940 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6941 dpll |= DPLLB_MODE_LVDS;
6942 else
6943 dpll |= DPLLB_MODE_DAC_SERIAL;
6944
6945 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6946 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6947 dpll |= (crtc_state->pixel_multiplier - 1)
6948 << SDVO_MULTIPLIER_SHIFT_HIRES;
6949 }
6950
6951 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6952 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6953 dpll |= DPLL_SDVO_HIGH_SPEED;
6954
6955 if (intel_crtc_has_dp_encoder(crtc_state))
6956 dpll |= DPLL_SDVO_HIGH_SPEED;
6957
6958 /* compute bitmask from p1 value */
6959 if (IS_PINEVIEW(dev_priv))
6960 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6961 else {
6962 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6963 if (IS_G4X(dev_priv) && reduced_clock)
6964 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6965 }
6966 switch (clock->p2) {
6967 case 5:
6968 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6969 break;
6970 case 7:
6971 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6972 break;
6973 case 10:
6974 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6975 break;
6976 case 14:
6977 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6978 break;
6979 }
6980 if (INTEL_GEN(dev_priv) >= 4)
6981 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6982
6983 if (crtc_state->sdvo_tv_clock)
6984 dpll |= PLL_REF_INPUT_TVCLKINBC;
6985 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6986 intel_panel_use_ssc(dev_priv))
6987 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6988 else
6989 dpll |= PLL_REF_INPUT_DREFCLK;
6990
6991 dpll |= DPLL_VCO_ENABLE;
6992 crtc_state->dpll_hw_state.dpll = dpll;
6993
6994 if (INTEL_GEN(dev_priv) >= 4) {
6995 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6996 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6997 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6998 }
6999 }
7000
7001 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7002 struct intel_crtc_state *crtc_state,
7003 struct dpll *reduced_clock)
7004 {
7005 struct drm_device *dev = crtc->base.dev;
7006 struct drm_i915_private *dev_priv = to_i915(dev);
7007 u32 dpll;
7008 struct dpll *clock = &crtc_state->dpll;
7009
7010 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7011
7012 dpll = DPLL_VGA_MODE_DIS;
7013
7014 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7015 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7016 } else {
7017 if (clock->p1 == 2)
7018 dpll |= PLL_P1_DIVIDE_BY_TWO;
7019 else
7020 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7021 if (clock->p2 == 4)
7022 dpll |= PLL_P2_DIVIDE_BY_4;
7023 }
7024
7025 if (!IS_I830(dev_priv) &&
7026 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
7027 dpll |= DPLL_DVO_2X_MODE;
7028
7029 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7030 intel_panel_use_ssc(dev_priv))
7031 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7032 else
7033 dpll |= PLL_REF_INPUT_DREFCLK;
7034
7035 dpll |= DPLL_VCO_ENABLE;
7036 crtc_state->dpll_hw_state.dpll = dpll;
7037 }
7038
7039 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7040 {
7041 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7042 enum pipe pipe = intel_crtc->pipe;
7043 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7044 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7045 uint32_t crtc_vtotal, crtc_vblank_end;
7046 int vsyncshift = 0;
7047
7048 /* We need to be careful not to changed the adjusted mode, for otherwise
7049 * the hw state checker will get angry at the mismatch. */
7050 crtc_vtotal = adjusted_mode->crtc_vtotal;
7051 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7052
7053 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7054 /* the chip adds 2 halflines automatically */
7055 crtc_vtotal -= 1;
7056 crtc_vblank_end -= 1;
7057
7058 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7059 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7060 else
7061 vsyncshift = adjusted_mode->crtc_hsync_start -
7062 adjusted_mode->crtc_htotal / 2;
7063 if (vsyncshift < 0)
7064 vsyncshift += adjusted_mode->crtc_htotal;
7065 }
7066
7067 if (INTEL_GEN(dev_priv) > 3)
7068 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7069
7070 I915_WRITE(HTOTAL(cpu_transcoder),
7071 (adjusted_mode->crtc_hdisplay - 1) |
7072 ((adjusted_mode->crtc_htotal - 1) << 16));
7073 I915_WRITE(HBLANK(cpu_transcoder),
7074 (adjusted_mode->crtc_hblank_start - 1) |
7075 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7076 I915_WRITE(HSYNC(cpu_transcoder),
7077 (adjusted_mode->crtc_hsync_start - 1) |
7078 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7079
7080 I915_WRITE(VTOTAL(cpu_transcoder),
7081 (adjusted_mode->crtc_vdisplay - 1) |
7082 ((crtc_vtotal - 1) << 16));
7083 I915_WRITE(VBLANK(cpu_transcoder),
7084 (adjusted_mode->crtc_vblank_start - 1) |
7085 ((crtc_vblank_end - 1) << 16));
7086 I915_WRITE(VSYNC(cpu_transcoder),
7087 (adjusted_mode->crtc_vsync_start - 1) |
7088 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7089
7090 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7091 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7092 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7093 * bits. */
7094 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
7095 (pipe == PIPE_B || pipe == PIPE_C))
7096 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7097
7098 }
7099
7100 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7101 {
7102 struct drm_device *dev = intel_crtc->base.dev;
7103 struct drm_i915_private *dev_priv = to_i915(dev);
7104 enum pipe pipe = intel_crtc->pipe;
7105
7106 /* pipesrc controls the size that is scaled from, which should
7107 * always be the user's requested size.
7108 */
7109 I915_WRITE(PIPESRC(pipe),
7110 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7111 (intel_crtc->config->pipe_src_h - 1));
7112 }
7113
7114 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7115 struct intel_crtc_state *pipe_config)
7116 {
7117 struct drm_device *dev = crtc->base.dev;
7118 struct drm_i915_private *dev_priv = to_i915(dev);
7119 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7120 uint32_t tmp;
7121
7122 tmp = I915_READ(HTOTAL(cpu_transcoder));
7123 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7124 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7125 tmp = I915_READ(HBLANK(cpu_transcoder));
7126 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7127 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7128 tmp = I915_READ(HSYNC(cpu_transcoder));
7129 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7130 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7131
7132 tmp = I915_READ(VTOTAL(cpu_transcoder));
7133 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7134 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7135 tmp = I915_READ(VBLANK(cpu_transcoder));
7136 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7137 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7138 tmp = I915_READ(VSYNC(cpu_transcoder));
7139 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7140 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7141
7142 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7143 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7144 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7145 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7146 }
7147 }
7148
7149 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7150 struct intel_crtc_state *pipe_config)
7151 {
7152 struct drm_device *dev = crtc->base.dev;
7153 struct drm_i915_private *dev_priv = to_i915(dev);
7154 u32 tmp;
7155
7156 tmp = I915_READ(PIPESRC(crtc->pipe));
7157 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7158 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7159
7160 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7161 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7162 }
7163
7164 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7165 struct intel_crtc_state *pipe_config)
7166 {
7167 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7168 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7169 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7170 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7171
7172 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7173 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7174 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7175 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7176
7177 mode->flags = pipe_config->base.adjusted_mode.flags;
7178 mode->type = DRM_MODE_TYPE_DRIVER;
7179
7180 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7181
7182 mode->hsync = drm_mode_hsync(mode);
7183 mode->vrefresh = drm_mode_vrefresh(mode);
7184 drm_mode_set_name(mode);
7185 }
7186
7187 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7188 {
7189 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7190 uint32_t pipeconf;
7191
7192 pipeconf = 0;
7193
7194 /* we keep both pipes enabled on 830 */
7195 if (IS_I830(dev_priv))
7196 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7197
7198 if (intel_crtc->config->double_wide)
7199 pipeconf |= PIPECONF_DOUBLE_WIDE;
7200
7201 /* only g4x and later have fancy bpc/dither controls */
7202 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7203 IS_CHERRYVIEW(dev_priv)) {
7204 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7205 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7206 pipeconf |= PIPECONF_DITHER_EN |
7207 PIPECONF_DITHER_TYPE_SP;
7208
7209 switch (intel_crtc->config->pipe_bpp) {
7210 case 18:
7211 pipeconf |= PIPECONF_6BPC;
7212 break;
7213 case 24:
7214 pipeconf |= PIPECONF_8BPC;
7215 break;
7216 case 30:
7217 pipeconf |= PIPECONF_10BPC;
7218 break;
7219 default:
7220 /* Case prevented by intel_choose_pipe_bpp_dither. */
7221 BUG();
7222 }
7223 }
7224
7225 if (HAS_PIPE_CXSR(dev_priv)) {
7226 if (intel_crtc->lowfreq_avail) {
7227 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7228 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7229 } else {
7230 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7231 }
7232 }
7233
7234 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7235 if (INTEL_GEN(dev_priv) < 4 ||
7236 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7237 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7238 else
7239 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7240 } else
7241 pipeconf |= PIPECONF_PROGRESSIVE;
7242
7243 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7244 intel_crtc->config->limited_color_range)
7245 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7246
7247 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7248 POSTING_READ(PIPECONF(intel_crtc->pipe));
7249 }
7250
7251 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7252 struct intel_crtc_state *crtc_state)
7253 {
7254 struct drm_device *dev = crtc->base.dev;
7255 struct drm_i915_private *dev_priv = to_i915(dev);
7256 const struct intel_limit *limit;
7257 int refclk = 48000;
7258
7259 memset(&crtc_state->dpll_hw_state, 0,
7260 sizeof(crtc_state->dpll_hw_state));
7261
7262 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7263 if (intel_panel_use_ssc(dev_priv)) {
7264 refclk = dev_priv->vbt.lvds_ssc_freq;
7265 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7266 }
7267
7268 limit = &intel_limits_i8xx_lvds;
7269 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7270 limit = &intel_limits_i8xx_dvo;
7271 } else {
7272 limit = &intel_limits_i8xx_dac;
7273 }
7274
7275 if (!crtc_state->clock_set &&
7276 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7277 refclk, NULL, &crtc_state->dpll)) {
7278 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7279 return -EINVAL;
7280 }
7281
7282 i8xx_compute_dpll(crtc, crtc_state, NULL);
7283
7284 return 0;
7285 }
7286
7287 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7288 struct intel_crtc_state *crtc_state)
7289 {
7290 struct drm_device *dev = crtc->base.dev;
7291 struct drm_i915_private *dev_priv = to_i915(dev);
7292 const struct intel_limit *limit;
7293 int refclk = 96000;
7294
7295 memset(&crtc_state->dpll_hw_state, 0,
7296 sizeof(crtc_state->dpll_hw_state));
7297
7298 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7299 if (intel_panel_use_ssc(dev_priv)) {
7300 refclk = dev_priv->vbt.lvds_ssc_freq;
7301 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7302 }
7303
7304 if (intel_is_dual_link_lvds(dev))
7305 limit = &intel_limits_g4x_dual_channel_lvds;
7306 else
7307 limit = &intel_limits_g4x_single_channel_lvds;
7308 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7309 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7310 limit = &intel_limits_g4x_hdmi;
7311 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7312 limit = &intel_limits_g4x_sdvo;
7313 } else {
7314 /* The option is for other outputs */
7315 limit = &intel_limits_i9xx_sdvo;
7316 }
7317
7318 if (!crtc_state->clock_set &&
7319 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7320 refclk, NULL, &crtc_state->dpll)) {
7321 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7322 return -EINVAL;
7323 }
7324
7325 i9xx_compute_dpll(crtc, crtc_state, NULL);
7326
7327 return 0;
7328 }
7329
7330 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7331 struct intel_crtc_state *crtc_state)
7332 {
7333 struct drm_device *dev = crtc->base.dev;
7334 struct drm_i915_private *dev_priv = to_i915(dev);
7335 const struct intel_limit *limit;
7336 int refclk = 96000;
7337
7338 memset(&crtc_state->dpll_hw_state, 0,
7339 sizeof(crtc_state->dpll_hw_state));
7340
7341 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7342 if (intel_panel_use_ssc(dev_priv)) {
7343 refclk = dev_priv->vbt.lvds_ssc_freq;
7344 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7345 }
7346
7347 limit = &intel_limits_pineview_lvds;
7348 } else {
7349 limit = &intel_limits_pineview_sdvo;
7350 }
7351
7352 if (!crtc_state->clock_set &&
7353 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7354 refclk, NULL, &crtc_state->dpll)) {
7355 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7356 return -EINVAL;
7357 }
7358
7359 i9xx_compute_dpll(crtc, crtc_state, NULL);
7360
7361 return 0;
7362 }
7363
7364 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7365 struct intel_crtc_state *crtc_state)
7366 {
7367 struct drm_device *dev = crtc->base.dev;
7368 struct drm_i915_private *dev_priv = to_i915(dev);
7369 const struct intel_limit *limit;
7370 int refclk = 96000;
7371
7372 memset(&crtc_state->dpll_hw_state, 0,
7373 sizeof(crtc_state->dpll_hw_state));
7374
7375 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7376 if (intel_panel_use_ssc(dev_priv)) {
7377 refclk = dev_priv->vbt.lvds_ssc_freq;
7378 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7379 }
7380
7381 limit = &intel_limits_i9xx_lvds;
7382 } else {
7383 limit = &intel_limits_i9xx_sdvo;
7384 }
7385
7386 if (!crtc_state->clock_set &&
7387 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7388 refclk, NULL, &crtc_state->dpll)) {
7389 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7390 return -EINVAL;
7391 }
7392
7393 i9xx_compute_dpll(crtc, crtc_state, NULL);
7394
7395 return 0;
7396 }
7397
7398 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7399 struct intel_crtc_state *crtc_state)
7400 {
7401 int refclk = 100000;
7402 const struct intel_limit *limit = &intel_limits_chv;
7403
7404 memset(&crtc_state->dpll_hw_state, 0,
7405 sizeof(crtc_state->dpll_hw_state));
7406
7407 if (!crtc_state->clock_set &&
7408 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7409 refclk, NULL, &crtc_state->dpll)) {
7410 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7411 return -EINVAL;
7412 }
7413
7414 chv_compute_dpll(crtc, crtc_state);
7415
7416 return 0;
7417 }
7418
7419 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7420 struct intel_crtc_state *crtc_state)
7421 {
7422 int refclk = 100000;
7423 const struct intel_limit *limit = &intel_limits_vlv;
7424
7425 memset(&crtc_state->dpll_hw_state, 0,
7426 sizeof(crtc_state->dpll_hw_state));
7427
7428 if (!crtc_state->clock_set &&
7429 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7430 refclk, NULL, &crtc_state->dpll)) {
7431 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7432 return -EINVAL;
7433 }
7434
7435 vlv_compute_dpll(crtc, crtc_state);
7436
7437 return 0;
7438 }
7439
7440 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7441 struct intel_crtc_state *pipe_config)
7442 {
7443 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7444 uint32_t tmp;
7445
7446 if (INTEL_GEN(dev_priv) <= 3 &&
7447 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7448 return;
7449
7450 tmp = I915_READ(PFIT_CONTROL);
7451 if (!(tmp & PFIT_ENABLE))
7452 return;
7453
7454 /* Check whether the pfit is attached to our pipe. */
7455 if (INTEL_GEN(dev_priv) < 4) {
7456 if (crtc->pipe != PIPE_B)
7457 return;
7458 } else {
7459 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7460 return;
7461 }
7462
7463 pipe_config->gmch_pfit.control = tmp;
7464 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7465 }
7466
7467 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7468 struct intel_crtc_state *pipe_config)
7469 {
7470 struct drm_device *dev = crtc->base.dev;
7471 struct drm_i915_private *dev_priv = to_i915(dev);
7472 int pipe = pipe_config->cpu_transcoder;
7473 struct dpll clock;
7474 u32 mdiv;
7475 int refclk = 100000;
7476
7477 /* In case of DSI, DPLL will not be used */
7478 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7479 return;
7480
7481 mutex_lock(&dev_priv->sb_lock);
7482 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7483 mutex_unlock(&dev_priv->sb_lock);
7484
7485 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7486 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7487 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7488 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7489 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7490
7491 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7492 }
7493
7494 static void
7495 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7496 struct intel_initial_plane_config *plane_config)
7497 {
7498 struct drm_device *dev = crtc->base.dev;
7499 struct drm_i915_private *dev_priv = to_i915(dev);
7500 u32 val, base, offset;
7501 int pipe = crtc->pipe, plane = crtc->plane;
7502 int fourcc, pixel_format;
7503 unsigned int aligned_height;
7504 struct drm_framebuffer *fb;
7505 struct intel_framebuffer *intel_fb;
7506
7507 val = I915_READ(DSPCNTR(plane));
7508 if (!(val & DISPLAY_PLANE_ENABLE))
7509 return;
7510
7511 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7512 if (!intel_fb) {
7513 DRM_DEBUG_KMS("failed to alloc fb\n");
7514 return;
7515 }
7516
7517 fb = &intel_fb->base;
7518
7519 fb->dev = dev;
7520
7521 if (INTEL_GEN(dev_priv) >= 4) {
7522 if (val & DISPPLANE_TILED) {
7523 plane_config->tiling = I915_TILING_X;
7524 fb->modifier = I915_FORMAT_MOD_X_TILED;
7525 }
7526 }
7527
7528 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7529 fourcc = i9xx_format_to_fourcc(pixel_format);
7530 fb->format = drm_format_info(fourcc);
7531
7532 if (INTEL_GEN(dev_priv) >= 4) {
7533 if (plane_config->tiling)
7534 offset = I915_READ(DSPTILEOFF(plane));
7535 else
7536 offset = I915_READ(DSPLINOFF(plane));
7537 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7538 } else {
7539 base = I915_READ(DSPADDR(plane));
7540 }
7541 plane_config->base = base;
7542
7543 val = I915_READ(PIPESRC(pipe));
7544 fb->width = ((val >> 16) & 0xfff) + 1;
7545 fb->height = ((val >> 0) & 0xfff) + 1;
7546
7547 val = I915_READ(DSPSTRIDE(pipe));
7548 fb->pitches[0] = val & 0xffffffc0;
7549
7550 aligned_height = intel_fb_align_height(fb, 0, fb->height);
7551
7552 plane_config->size = fb->pitches[0] * aligned_height;
7553
7554 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7555 pipe_name(pipe), plane, fb->width, fb->height,
7556 fb->format->cpp[0] * 8, base, fb->pitches[0],
7557 plane_config->size);
7558
7559 plane_config->fb = intel_fb;
7560 }
7561
7562 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7563 struct intel_crtc_state *pipe_config)
7564 {
7565 struct drm_device *dev = crtc->base.dev;
7566 struct drm_i915_private *dev_priv = to_i915(dev);
7567 int pipe = pipe_config->cpu_transcoder;
7568 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7569 struct dpll clock;
7570 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7571 int refclk = 100000;
7572
7573 /* In case of DSI, DPLL will not be used */
7574 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7575 return;
7576
7577 mutex_lock(&dev_priv->sb_lock);
7578 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7579 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7580 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7581 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7582 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7583 mutex_unlock(&dev_priv->sb_lock);
7584
7585 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7586 clock.m2 = (pll_dw0 & 0xff) << 22;
7587 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7588 clock.m2 |= pll_dw2 & 0x3fffff;
7589 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7590 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7591 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7592
7593 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7594 }
7595
7596 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7597 struct intel_crtc_state *pipe_config)
7598 {
7599 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7600 enum intel_display_power_domain power_domain;
7601 uint32_t tmp;
7602 bool ret;
7603
7604 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7605 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7606 return false;
7607
7608 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7609 pipe_config->shared_dpll = NULL;
7610
7611 ret = false;
7612
7613 tmp = I915_READ(PIPECONF(crtc->pipe));
7614 if (!(tmp & PIPECONF_ENABLE))
7615 goto out;
7616
7617 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7618 IS_CHERRYVIEW(dev_priv)) {
7619 switch (tmp & PIPECONF_BPC_MASK) {
7620 case PIPECONF_6BPC:
7621 pipe_config->pipe_bpp = 18;
7622 break;
7623 case PIPECONF_8BPC:
7624 pipe_config->pipe_bpp = 24;
7625 break;
7626 case PIPECONF_10BPC:
7627 pipe_config->pipe_bpp = 30;
7628 break;
7629 default:
7630 break;
7631 }
7632 }
7633
7634 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7635 (tmp & PIPECONF_COLOR_RANGE_SELECT))
7636 pipe_config->limited_color_range = true;
7637
7638 if (INTEL_GEN(dev_priv) < 4)
7639 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7640
7641 intel_get_pipe_timings(crtc, pipe_config);
7642 intel_get_pipe_src_size(crtc, pipe_config);
7643
7644 i9xx_get_pfit_config(crtc, pipe_config);
7645
7646 if (INTEL_GEN(dev_priv) >= 4) {
7647 /* No way to read it out on pipes B and C */
7648 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7649 tmp = dev_priv->chv_dpll_md[crtc->pipe];
7650 else
7651 tmp = I915_READ(DPLL_MD(crtc->pipe));
7652 pipe_config->pixel_multiplier =
7653 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7654 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7655 pipe_config->dpll_hw_state.dpll_md = tmp;
7656 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7657 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7658 tmp = I915_READ(DPLL(crtc->pipe));
7659 pipe_config->pixel_multiplier =
7660 ((tmp & SDVO_MULTIPLIER_MASK)
7661 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7662 } else {
7663 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7664 * port and will be fixed up in the encoder->get_config
7665 * function. */
7666 pipe_config->pixel_multiplier = 1;
7667 }
7668 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7669 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7670 /*
7671 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7672 * on 830. Filter it out here so that we don't
7673 * report errors due to that.
7674 */
7675 if (IS_I830(dev_priv))
7676 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7677
7678 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7679 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7680 } else {
7681 /* Mask out read-only status bits. */
7682 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7683 DPLL_PORTC_READY_MASK |
7684 DPLL_PORTB_READY_MASK);
7685 }
7686
7687 if (IS_CHERRYVIEW(dev_priv))
7688 chv_crtc_clock_get(crtc, pipe_config);
7689 else if (IS_VALLEYVIEW(dev_priv))
7690 vlv_crtc_clock_get(crtc, pipe_config);
7691 else
7692 i9xx_crtc_clock_get(crtc, pipe_config);
7693
7694 /*
7695 * Normally the dotclock is filled in by the encoder .get_config()
7696 * but in case the pipe is enabled w/o any ports we need a sane
7697 * default.
7698 */
7699 pipe_config->base.adjusted_mode.crtc_clock =
7700 pipe_config->port_clock / pipe_config->pixel_multiplier;
7701
7702 ret = true;
7703
7704 out:
7705 intel_display_power_put(dev_priv, power_domain);
7706
7707 return ret;
7708 }
7709
7710 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7711 {
7712 struct intel_encoder *encoder;
7713 int i;
7714 u32 val, final;
7715 bool has_lvds = false;
7716 bool has_cpu_edp = false;
7717 bool has_panel = false;
7718 bool has_ck505 = false;
7719 bool can_ssc = false;
7720 bool using_ssc_source = false;
7721
7722 /* We need to take the global config into account */
7723 for_each_intel_encoder(&dev_priv->drm, encoder) {
7724 switch (encoder->type) {
7725 case INTEL_OUTPUT_LVDS:
7726 has_panel = true;
7727 has_lvds = true;
7728 break;
7729 case INTEL_OUTPUT_EDP:
7730 has_panel = true;
7731 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7732 has_cpu_edp = true;
7733 break;
7734 default:
7735 break;
7736 }
7737 }
7738
7739 if (HAS_PCH_IBX(dev_priv)) {
7740 has_ck505 = dev_priv->vbt.display_clock_mode;
7741 can_ssc = has_ck505;
7742 } else {
7743 has_ck505 = false;
7744 can_ssc = true;
7745 }
7746
7747 /* Check if any DPLLs are using the SSC source */
7748 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7749 u32 temp = I915_READ(PCH_DPLL(i));
7750
7751 if (!(temp & DPLL_VCO_ENABLE))
7752 continue;
7753
7754 if ((temp & PLL_REF_INPUT_MASK) ==
7755 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7756 using_ssc_source = true;
7757 break;
7758 }
7759 }
7760
7761 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7762 has_panel, has_lvds, has_ck505, using_ssc_source);
7763
7764 /* Ironlake: try to setup display ref clock before DPLL
7765 * enabling. This is only under driver's control after
7766 * PCH B stepping, previous chipset stepping should be
7767 * ignoring this setting.
7768 */
7769 val = I915_READ(PCH_DREF_CONTROL);
7770
7771 /* As we must carefully and slowly disable/enable each source in turn,
7772 * compute the final state we want first and check if we need to
7773 * make any changes at all.
7774 */
7775 final = val;
7776 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7777 if (has_ck505)
7778 final |= DREF_NONSPREAD_CK505_ENABLE;
7779 else
7780 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7781
7782 final &= ~DREF_SSC_SOURCE_MASK;
7783 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7784 final &= ~DREF_SSC1_ENABLE;
7785
7786 if (has_panel) {
7787 final |= DREF_SSC_SOURCE_ENABLE;
7788
7789 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7790 final |= DREF_SSC1_ENABLE;
7791
7792 if (has_cpu_edp) {
7793 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7794 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7795 else
7796 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7797 } else
7798 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7799 } else if (using_ssc_source) {
7800 final |= DREF_SSC_SOURCE_ENABLE;
7801 final |= DREF_SSC1_ENABLE;
7802 }
7803
7804 if (final == val)
7805 return;
7806
7807 /* Always enable nonspread source */
7808 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7809
7810 if (has_ck505)
7811 val |= DREF_NONSPREAD_CK505_ENABLE;
7812 else
7813 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7814
7815 if (has_panel) {
7816 val &= ~DREF_SSC_SOURCE_MASK;
7817 val |= DREF_SSC_SOURCE_ENABLE;
7818
7819 /* SSC must be turned on before enabling the CPU output */
7820 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7821 DRM_DEBUG_KMS("Using SSC on panel\n");
7822 val |= DREF_SSC1_ENABLE;
7823 } else
7824 val &= ~DREF_SSC1_ENABLE;
7825
7826 /* Get SSC going before enabling the outputs */
7827 I915_WRITE(PCH_DREF_CONTROL, val);
7828 POSTING_READ(PCH_DREF_CONTROL);
7829 udelay(200);
7830
7831 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7832
7833 /* Enable CPU source on CPU attached eDP */
7834 if (has_cpu_edp) {
7835 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7836 DRM_DEBUG_KMS("Using SSC on eDP\n");
7837 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7838 } else
7839 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7840 } else
7841 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7842
7843 I915_WRITE(PCH_DREF_CONTROL, val);
7844 POSTING_READ(PCH_DREF_CONTROL);
7845 udelay(200);
7846 } else {
7847 DRM_DEBUG_KMS("Disabling CPU source output\n");
7848
7849 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7850
7851 /* Turn off CPU output */
7852 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7853
7854 I915_WRITE(PCH_DREF_CONTROL, val);
7855 POSTING_READ(PCH_DREF_CONTROL);
7856 udelay(200);
7857
7858 if (!using_ssc_source) {
7859 DRM_DEBUG_KMS("Disabling SSC source\n");
7860
7861 /* Turn off the SSC source */
7862 val &= ~DREF_SSC_SOURCE_MASK;
7863 val |= DREF_SSC_SOURCE_DISABLE;
7864
7865 /* Turn off SSC1 */
7866 val &= ~DREF_SSC1_ENABLE;
7867
7868 I915_WRITE(PCH_DREF_CONTROL, val);
7869 POSTING_READ(PCH_DREF_CONTROL);
7870 udelay(200);
7871 }
7872 }
7873
7874 BUG_ON(val != final);
7875 }
7876
7877 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7878 {
7879 uint32_t tmp;
7880
7881 tmp = I915_READ(SOUTH_CHICKEN2);
7882 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7883 I915_WRITE(SOUTH_CHICKEN2, tmp);
7884
7885 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7886 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7887 DRM_ERROR("FDI mPHY reset assert timeout\n");
7888
7889 tmp = I915_READ(SOUTH_CHICKEN2);
7890 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7891 I915_WRITE(SOUTH_CHICKEN2, tmp);
7892
7893 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7894 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7895 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7896 }
7897
7898 /* WaMPhyProgramming:hsw */
7899 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7900 {
7901 uint32_t tmp;
7902
7903 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7904 tmp &= ~(0xFF << 24);
7905 tmp |= (0x12 << 24);
7906 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7907
7908 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7909 tmp |= (1 << 11);
7910 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7911
7912 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7913 tmp |= (1 << 11);
7914 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7915
7916 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7917 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7918 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7919
7920 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7921 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7922 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7923
7924 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7925 tmp &= ~(7 << 13);
7926 tmp |= (5 << 13);
7927 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7928
7929 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7930 tmp &= ~(7 << 13);
7931 tmp |= (5 << 13);
7932 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7933
7934 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7935 tmp &= ~0xFF;
7936 tmp |= 0x1C;
7937 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7938
7939 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7940 tmp &= ~0xFF;
7941 tmp |= 0x1C;
7942 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7943
7944 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7945 tmp &= ~(0xFF << 16);
7946 tmp |= (0x1C << 16);
7947 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7948
7949 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7950 tmp &= ~(0xFF << 16);
7951 tmp |= (0x1C << 16);
7952 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7953
7954 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7955 tmp |= (1 << 27);
7956 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7957
7958 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7959 tmp |= (1 << 27);
7960 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7961
7962 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7963 tmp &= ~(0xF << 28);
7964 tmp |= (4 << 28);
7965 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7966
7967 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7968 tmp &= ~(0xF << 28);
7969 tmp |= (4 << 28);
7970 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7971 }
7972
7973 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7974 * Programming" based on the parameters passed:
7975 * - Sequence to enable CLKOUT_DP
7976 * - Sequence to enable CLKOUT_DP without spread
7977 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7978 */
7979 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7980 bool with_spread, bool with_fdi)
7981 {
7982 uint32_t reg, tmp;
7983
7984 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7985 with_spread = true;
7986 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7987 with_fdi, "LP PCH doesn't have FDI\n"))
7988 with_fdi = false;
7989
7990 mutex_lock(&dev_priv->sb_lock);
7991
7992 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7993 tmp &= ~SBI_SSCCTL_DISABLE;
7994 tmp |= SBI_SSCCTL_PATHALT;
7995 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7996
7997 udelay(24);
7998
7999 if (with_spread) {
8000 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8001 tmp &= ~SBI_SSCCTL_PATHALT;
8002 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8003
8004 if (with_fdi) {
8005 lpt_reset_fdi_mphy(dev_priv);
8006 lpt_program_fdi_mphy(dev_priv);
8007 }
8008 }
8009
8010 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8011 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8012 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8013 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8014
8015 mutex_unlock(&dev_priv->sb_lock);
8016 }
8017
8018 /* Sequence to disable CLKOUT_DP */
8019 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
8020 {
8021 uint32_t reg, tmp;
8022
8023 mutex_lock(&dev_priv->sb_lock);
8024
8025 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8026 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8027 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8028 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8029
8030 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8031 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8032 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8033 tmp |= SBI_SSCCTL_PATHALT;
8034 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8035 udelay(32);
8036 }
8037 tmp |= SBI_SSCCTL_DISABLE;
8038 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8039 }
8040
8041 mutex_unlock(&dev_priv->sb_lock);
8042 }
8043
8044 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8045
8046 static const uint16_t sscdivintphase[] = {
8047 [BEND_IDX( 50)] = 0x3B23,
8048 [BEND_IDX( 45)] = 0x3B23,
8049 [BEND_IDX( 40)] = 0x3C23,
8050 [BEND_IDX( 35)] = 0x3C23,
8051 [BEND_IDX( 30)] = 0x3D23,
8052 [BEND_IDX( 25)] = 0x3D23,
8053 [BEND_IDX( 20)] = 0x3E23,
8054 [BEND_IDX( 15)] = 0x3E23,
8055 [BEND_IDX( 10)] = 0x3F23,
8056 [BEND_IDX( 5)] = 0x3F23,
8057 [BEND_IDX( 0)] = 0x0025,
8058 [BEND_IDX( -5)] = 0x0025,
8059 [BEND_IDX(-10)] = 0x0125,
8060 [BEND_IDX(-15)] = 0x0125,
8061 [BEND_IDX(-20)] = 0x0225,
8062 [BEND_IDX(-25)] = 0x0225,
8063 [BEND_IDX(-30)] = 0x0325,
8064 [BEND_IDX(-35)] = 0x0325,
8065 [BEND_IDX(-40)] = 0x0425,
8066 [BEND_IDX(-45)] = 0x0425,
8067 [BEND_IDX(-50)] = 0x0525,
8068 };
8069
8070 /*
8071 * Bend CLKOUT_DP
8072 * steps -50 to 50 inclusive, in steps of 5
8073 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8074 * change in clock period = -(steps / 10) * 5.787 ps
8075 */
8076 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8077 {
8078 uint32_t tmp;
8079 int idx = BEND_IDX(steps);
8080
8081 if (WARN_ON(steps % 5 != 0))
8082 return;
8083
8084 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8085 return;
8086
8087 mutex_lock(&dev_priv->sb_lock);
8088
8089 if (steps % 10 != 0)
8090 tmp = 0xAAAAAAAB;
8091 else
8092 tmp = 0x00000000;
8093 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8094
8095 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8096 tmp &= 0xffff0000;
8097 tmp |= sscdivintphase[idx];
8098 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8099
8100 mutex_unlock(&dev_priv->sb_lock);
8101 }
8102
8103 #undef BEND_IDX
8104
8105 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
8106 {
8107 struct intel_encoder *encoder;
8108 bool has_vga = false;
8109
8110 for_each_intel_encoder(&dev_priv->drm, encoder) {
8111 switch (encoder->type) {
8112 case INTEL_OUTPUT_ANALOG:
8113 has_vga = true;
8114 break;
8115 default:
8116 break;
8117 }
8118 }
8119
8120 if (has_vga) {
8121 lpt_bend_clkout_dp(dev_priv, 0);
8122 lpt_enable_clkout_dp(dev_priv, true, true);
8123 } else {
8124 lpt_disable_clkout_dp(dev_priv);
8125 }
8126 }
8127
8128 /*
8129 * Initialize reference clocks when the driver loads
8130 */
8131 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8132 {
8133 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8134 ironlake_init_pch_refclk(dev_priv);
8135 else if (HAS_PCH_LPT(dev_priv))
8136 lpt_init_pch_refclk(dev_priv);
8137 }
8138
8139 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8140 {
8141 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8143 int pipe = intel_crtc->pipe;
8144 uint32_t val;
8145
8146 val = 0;
8147
8148 switch (intel_crtc->config->pipe_bpp) {
8149 case 18:
8150 val |= PIPECONF_6BPC;
8151 break;
8152 case 24:
8153 val |= PIPECONF_8BPC;
8154 break;
8155 case 30:
8156 val |= PIPECONF_10BPC;
8157 break;
8158 case 36:
8159 val |= PIPECONF_12BPC;
8160 break;
8161 default:
8162 /* Case prevented by intel_choose_pipe_bpp_dither. */
8163 BUG();
8164 }
8165
8166 if (intel_crtc->config->dither)
8167 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8168
8169 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8170 val |= PIPECONF_INTERLACED_ILK;
8171 else
8172 val |= PIPECONF_PROGRESSIVE;
8173
8174 if (intel_crtc->config->limited_color_range)
8175 val |= PIPECONF_COLOR_RANGE_SELECT;
8176
8177 I915_WRITE(PIPECONF(pipe), val);
8178 POSTING_READ(PIPECONF(pipe));
8179 }
8180
8181 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8182 {
8183 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8185 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8186 u32 val = 0;
8187
8188 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8189 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8190
8191 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8192 val |= PIPECONF_INTERLACED_ILK;
8193 else
8194 val |= PIPECONF_PROGRESSIVE;
8195
8196 I915_WRITE(PIPECONF(cpu_transcoder), val);
8197 POSTING_READ(PIPECONF(cpu_transcoder));
8198 }
8199
8200 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8201 {
8202 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8204 struct intel_crtc_state *config = intel_crtc->config;
8205
8206 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8207 u32 val = 0;
8208
8209 switch (intel_crtc->config->pipe_bpp) {
8210 case 18:
8211 val |= PIPEMISC_DITHER_6_BPC;
8212 break;
8213 case 24:
8214 val |= PIPEMISC_DITHER_8_BPC;
8215 break;
8216 case 30:
8217 val |= PIPEMISC_DITHER_10_BPC;
8218 break;
8219 case 36:
8220 val |= PIPEMISC_DITHER_12_BPC;
8221 break;
8222 default:
8223 /* Case prevented by pipe_config_set_bpp. */
8224 BUG();
8225 }
8226
8227 if (intel_crtc->config->dither)
8228 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8229
8230 if (config->ycbcr420) {
8231 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV |
8232 PIPEMISC_YUV420_ENABLE |
8233 PIPEMISC_YUV420_MODE_FULL_BLEND;
8234 }
8235
8236 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8237 }
8238 }
8239
8240 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8241 {
8242 /*
8243 * Account for spread spectrum to avoid
8244 * oversubscribing the link. Max center spread
8245 * is 2.5%; use 5% for safety's sake.
8246 */
8247 u32 bps = target_clock * bpp * 21 / 20;
8248 return DIV_ROUND_UP(bps, link_bw * 8);
8249 }
8250
8251 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8252 {
8253 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8254 }
8255
8256 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8257 struct intel_crtc_state *crtc_state,
8258 struct dpll *reduced_clock)
8259 {
8260 struct drm_crtc *crtc = &intel_crtc->base;
8261 struct drm_device *dev = crtc->dev;
8262 struct drm_i915_private *dev_priv = to_i915(dev);
8263 u32 dpll, fp, fp2;
8264 int factor;
8265
8266 /* Enable autotuning of the PLL clock (if permissible) */
8267 factor = 21;
8268 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8269 if ((intel_panel_use_ssc(dev_priv) &&
8270 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8271 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8272 factor = 25;
8273 } else if (crtc_state->sdvo_tv_clock)
8274 factor = 20;
8275
8276 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8277
8278 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8279 fp |= FP_CB_TUNE;
8280
8281 if (reduced_clock) {
8282 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8283
8284 if (reduced_clock->m < factor * reduced_clock->n)
8285 fp2 |= FP_CB_TUNE;
8286 } else {
8287 fp2 = fp;
8288 }
8289
8290 dpll = 0;
8291
8292 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8293 dpll |= DPLLB_MODE_LVDS;
8294 else
8295 dpll |= DPLLB_MODE_DAC_SERIAL;
8296
8297 dpll |= (crtc_state->pixel_multiplier - 1)
8298 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8299
8300 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8301 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8302 dpll |= DPLL_SDVO_HIGH_SPEED;
8303
8304 if (intel_crtc_has_dp_encoder(crtc_state))
8305 dpll |= DPLL_SDVO_HIGH_SPEED;
8306
8307 /*
8308 * The high speed IO clock is only really required for
8309 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8310 * possible to share the DPLL between CRT and HDMI. Enabling
8311 * the clock needlessly does no real harm, except use up a
8312 * bit of power potentially.
8313 *
8314 * We'll limit this to IVB with 3 pipes, since it has only two
8315 * DPLLs and so DPLL sharing is the only way to get three pipes
8316 * driving PCH ports at the same time. On SNB we could do this,
8317 * and potentially avoid enabling the second DPLL, but it's not
8318 * clear if it''s a win or loss power wise. No point in doing
8319 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8320 */
8321 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8322 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8323 dpll |= DPLL_SDVO_HIGH_SPEED;
8324
8325 /* compute bitmask from p1 value */
8326 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8327 /* also FPA1 */
8328 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8329
8330 switch (crtc_state->dpll.p2) {
8331 case 5:
8332 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8333 break;
8334 case 7:
8335 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8336 break;
8337 case 10:
8338 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8339 break;
8340 case 14:
8341 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8342 break;
8343 }
8344
8345 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8346 intel_panel_use_ssc(dev_priv))
8347 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8348 else
8349 dpll |= PLL_REF_INPUT_DREFCLK;
8350
8351 dpll |= DPLL_VCO_ENABLE;
8352
8353 crtc_state->dpll_hw_state.dpll = dpll;
8354 crtc_state->dpll_hw_state.fp0 = fp;
8355 crtc_state->dpll_hw_state.fp1 = fp2;
8356 }
8357
8358 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8359 struct intel_crtc_state *crtc_state)
8360 {
8361 struct drm_device *dev = crtc->base.dev;
8362 struct drm_i915_private *dev_priv = to_i915(dev);
8363 const struct intel_limit *limit;
8364 int refclk = 120000;
8365
8366 memset(&crtc_state->dpll_hw_state, 0,
8367 sizeof(crtc_state->dpll_hw_state));
8368
8369 crtc->lowfreq_avail = false;
8370
8371 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8372 if (!crtc_state->has_pch_encoder)
8373 return 0;
8374
8375 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8376 if (intel_panel_use_ssc(dev_priv)) {
8377 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8378 dev_priv->vbt.lvds_ssc_freq);
8379 refclk = dev_priv->vbt.lvds_ssc_freq;
8380 }
8381
8382 if (intel_is_dual_link_lvds(dev)) {
8383 if (refclk == 100000)
8384 limit = &intel_limits_ironlake_dual_lvds_100m;
8385 else
8386 limit = &intel_limits_ironlake_dual_lvds;
8387 } else {
8388 if (refclk == 100000)
8389 limit = &intel_limits_ironlake_single_lvds_100m;
8390 else
8391 limit = &intel_limits_ironlake_single_lvds;
8392 }
8393 } else {
8394 limit = &intel_limits_ironlake_dac;
8395 }
8396
8397 if (!crtc_state->clock_set &&
8398 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8399 refclk, NULL, &crtc_state->dpll)) {
8400 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8401 return -EINVAL;
8402 }
8403
8404 ironlake_compute_dpll(crtc, crtc_state, NULL);
8405
8406 if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8407 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8408 pipe_name(crtc->pipe));
8409 return -EINVAL;
8410 }
8411
8412 return 0;
8413 }
8414
8415 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8416 struct intel_link_m_n *m_n)
8417 {
8418 struct drm_device *dev = crtc->base.dev;
8419 struct drm_i915_private *dev_priv = to_i915(dev);
8420 enum pipe pipe = crtc->pipe;
8421
8422 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8423 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8424 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8425 & ~TU_SIZE_MASK;
8426 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8427 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8428 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8429 }
8430
8431 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8432 enum transcoder transcoder,
8433 struct intel_link_m_n *m_n,
8434 struct intel_link_m_n *m2_n2)
8435 {
8436 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8437 enum pipe pipe = crtc->pipe;
8438
8439 if (INTEL_GEN(dev_priv) >= 5) {
8440 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8441 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8442 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8443 & ~TU_SIZE_MASK;
8444 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8445 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8446 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8447 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8448 * gen < 8) and if DRRS is supported (to make sure the
8449 * registers are not unnecessarily read).
8450 */
8451 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8452 crtc->config->has_drrs) {
8453 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8454 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8455 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8456 & ~TU_SIZE_MASK;
8457 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8458 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8459 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8460 }
8461 } else {
8462 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8463 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8464 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8465 & ~TU_SIZE_MASK;
8466 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8467 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8468 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8469 }
8470 }
8471
8472 void intel_dp_get_m_n(struct intel_crtc *crtc,
8473 struct intel_crtc_state *pipe_config)
8474 {
8475 if (pipe_config->has_pch_encoder)
8476 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8477 else
8478 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8479 &pipe_config->dp_m_n,
8480 &pipe_config->dp_m2_n2);
8481 }
8482
8483 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8484 struct intel_crtc_state *pipe_config)
8485 {
8486 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8487 &pipe_config->fdi_m_n, NULL);
8488 }
8489
8490 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8491 struct intel_crtc_state *pipe_config)
8492 {
8493 struct drm_device *dev = crtc->base.dev;
8494 struct drm_i915_private *dev_priv = to_i915(dev);
8495 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8496 uint32_t ps_ctrl = 0;
8497 int id = -1;
8498 int i;
8499
8500 /* find scaler attached to this pipe */
8501 for (i = 0; i < crtc->num_scalers; i++) {
8502 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8503 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8504 id = i;
8505 pipe_config->pch_pfit.enabled = true;
8506 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8507 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8508 break;
8509 }
8510 }
8511
8512 scaler_state->scaler_id = id;
8513 if (id >= 0) {
8514 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8515 } else {
8516 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8517 }
8518 }
8519
8520 static void
8521 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8522 struct intel_initial_plane_config *plane_config)
8523 {
8524 struct drm_device *dev = crtc->base.dev;
8525 struct drm_i915_private *dev_priv = to_i915(dev);
8526 u32 val, base, offset, stride_mult, tiling;
8527 int pipe = crtc->pipe;
8528 int fourcc, pixel_format;
8529 unsigned int aligned_height;
8530 struct drm_framebuffer *fb;
8531 struct intel_framebuffer *intel_fb;
8532
8533 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8534 if (!intel_fb) {
8535 DRM_DEBUG_KMS("failed to alloc fb\n");
8536 return;
8537 }
8538
8539 fb = &intel_fb->base;
8540
8541 fb->dev = dev;
8542
8543 val = I915_READ(PLANE_CTL(pipe, 0));
8544 if (!(val & PLANE_CTL_ENABLE))
8545 goto error;
8546
8547 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8548 fourcc = skl_format_to_fourcc(pixel_format,
8549 val & PLANE_CTL_ORDER_RGBX,
8550 val & PLANE_CTL_ALPHA_MASK);
8551 fb->format = drm_format_info(fourcc);
8552
8553 tiling = val & PLANE_CTL_TILED_MASK;
8554 switch (tiling) {
8555 case PLANE_CTL_TILED_LINEAR:
8556 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8557 break;
8558 case PLANE_CTL_TILED_X:
8559 plane_config->tiling = I915_TILING_X;
8560 fb->modifier = I915_FORMAT_MOD_X_TILED;
8561 break;
8562 case PLANE_CTL_TILED_Y:
8563 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8564 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
8565 else
8566 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8567 break;
8568 case PLANE_CTL_TILED_YF:
8569 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8570 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
8571 else
8572 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8573 break;
8574 default:
8575 MISSING_CASE(tiling);
8576 goto error;
8577 }
8578
8579 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8580 plane_config->base = base;
8581
8582 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8583
8584 val = I915_READ(PLANE_SIZE(pipe, 0));
8585 fb->height = ((val >> 16) & 0xfff) + 1;
8586 fb->width = ((val >> 0) & 0x1fff) + 1;
8587
8588 val = I915_READ(PLANE_STRIDE(pipe, 0));
8589 stride_mult = intel_fb_stride_alignment(fb, 0);
8590 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8591
8592 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8593
8594 plane_config->size = fb->pitches[0] * aligned_height;
8595
8596 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8597 pipe_name(pipe), fb->width, fb->height,
8598 fb->format->cpp[0] * 8, base, fb->pitches[0],
8599 plane_config->size);
8600
8601 plane_config->fb = intel_fb;
8602 return;
8603
8604 error:
8605 kfree(intel_fb);
8606 }
8607
8608 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8609 struct intel_crtc_state *pipe_config)
8610 {
8611 struct drm_device *dev = crtc->base.dev;
8612 struct drm_i915_private *dev_priv = to_i915(dev);
8613 uint32_t tmp;
8614
8615 tmp = I915_READ(PF_CTL(crtc->pipe));
8616
8617 if (tmp & PF_ENABLE) {
8618 pipe_config->pch_pfit.enabled = true;
8619 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8620 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8621
8622 /* We currently do not free assignements of panel fitters on
8623 * ivb/hsw (since we don't use the higher upscaling modes which
8624 * differentiates them) so just WARN about this case for now. */
8625 if (IS_GEN7(dev_priv)) {
8626 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8627 PF_PIPE_SEL_IVB(crtc->pipe));
8628 }
8629 }
8630 }
8631
8632 static void
8633 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8634 struct intel_initial_plane_config *plane_config)
8635 {
8636 struct drm_device *dev = crtc->base.dev;
8637 struct drm_i915_private *dev_priv = to_i915(dev);
8638 u32 val, base, offset;
8639 int pipe = crtc->pipe;
8640 int fourcc, pixel_format;
8641 unsigned int aligned_height;
8642 struct drm_framebuffer *fb;
8643 struct intel_framebuffer *intel_fb;
8644
8645 val = I915_READ(DSPCNTR(pipe));
8646 if (!(val & DISPLAY_PLANE_ENABLE))
8647 return;
8648
8649 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8650 if (!intel_fb) {
8651 DRM_DEBUG_KMS("failed to alloc fb\n");
8652 return;
8653 }
8654
8655 fb = &intel_fb->base;
8656
8657 fb->dev = dev;
8658
8659 if (INTEL_GEN(dev_priv) >= 4) {
8660 if (val & DISPPLANE_TILED) {
8661 plane_config->tiling = I915_TILING_X;
8662 fb->modifier = I915_FORMAT_MOD_X_TILED;
8663 }
8664 }
8665
8666 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8667 fourcc = i9xx_format_to_fourcc(pixel_format);
8668 fb->format = drm_format_info(fourcc);
8669
8670 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8671 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8672 offset = I915_READ(DSPOFFSET(pipe));
8673 } else {
8674 if (plane_config->tiling)
8675 offset = I915_READ(DSPTILEOFF(pipe));
8676 else
8677 offset = I915_READ(DSPLINOFF(pipe));
8678 }
8679 plane_config->base = base;
8680
8681 val = I915_READ(PIPESRC(pipe));
8682 fb->width = ((val >> 16) & 0xfff) + 1;
8683 fb->height = ((val >> 0) & 0xfff) + 1;
8684
8685 val = I915_READ(DSPSTRIDE(pipe));
8686 fb->pitches[0] = val & 0xffffffc0;
8687
8688 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8689
8690 plane_config->size = fb->pitches[0] * aligned_height;
8691
8692 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8693 pipe_name(pipe), fb->width, fb->height,
8694 fb->format->cpp[0] * 8, base, fb->pitches[0],
8695 plane_config->size);
8696
8697 plane_config->fb = intel_fb;
8698 }
8699
8700 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8701 struct intel_crtc_state *pipe_config)
8702 {
8703 struct drm_device *dev = crtc->base.dev;
8704 struct drm_i915_private *dev_priv = to_i915(dev);
8705 enum intel_display_power_domain power_domain;
8706 uint32_t tmp;
8707 bool ret;
8708
8709 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8710 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8711 return false;
8712
8713 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8714 pipe_config->shared_dpll = NULL;
8715
8716 ret = false;
8717 tmp = I915_READ(PIPECONF(crtc->pipe));
8718 if (!(tmp & PIPECONF_ENABLE))
8719 goto out;
8720
8721 switch (tmp & PIPECONF_BPC_MASK) {
8722 case PIPECONF_6BPC:
8723 pipe_config->pipe_bpp = 18;
8724 break;
8725 case PIPECONF_8BPC:
8726 pipe_config->pipe_bpp = 24;
8727 break;
8728 case PIPECONF_10BPC:
8729 pipe_config->pipe_bpp = 30;
8730 break;
8731 case PIPECONF_12BPC:
8732 pipe_config->pipe_bpp = 36;
8733 break;
8734 default:
8735 break;
8736 }
8737
8738 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8739 pipe_config->limited_color_range = true;
8740
8741 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8742 struct intel_shared_dpll *pll;
8743 enum intel_dpll_id pll_id;
8744
8745 pipe_config->has_pch_encoder = true;
8746
8747 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8748 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8749 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8750
8751 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8752
8753 if (HAS_PCH_IBX(dev_priv)) {
8754 /*
8755 * The pipe->pch transcoder and pch transcoder->pll
8756 * mapping is fixed.
8757 */
8758 pll_id = (enum intel_dpll_id) crtc->pipe;
8759 } else {
8760 tmp = I915_READ(PCH_DPLL_SEL);
8761 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8762 pll_id = DPLL_ID_PCH_PLL_B;
8763 else
8764 pll_id= DPLL_ID_PCH_PLL_A;
8765 }
8766
8767 pipe_config->shared_dpll =
8768 intel_get_shared_dpll_by_id(dev_priv, pll_id);
8769 pll = pipe_config->shared_dpll;
8770
8771 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8772 &pipe_config->dpll_hw_state));
8773
8774 tmp = pipe_config->dpll_hw_state.dpll;
8775 pipe_config->pixel_multiplier =
8776 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8777 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8778
8779 ironlake_pch_clock_get(crtc, pipe_config);
8780 } else {
8781 pipe_config->pixel_multiplier = 1;
8782 }
8783
8784 intel_get_pipe_timings(crtc, pipe_config);
8785 intel_get_pipe_src_size(crtc, pipe_config);
8786
8787 ironlake_get_pfit_config(crtc, pipe_config);
8788
8789 ret = true;
8790
8791 out:
8792 intel_display_power_put(dev_priv, power_domain);
8793
8794 return ret;
8795 }
8796
8797 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8798 {
8799 struct drm_device *dev = &dev_priv->drm;
8800 struct intel_crtc *crtc;
8801
8802 for_each_intel_crtc(dev, crtc)
8803 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8804 pipe_name(crtc->pipe));
8805
8806 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)),
8807 "Display power well on\n");
8808 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8809 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8810 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8811 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8812 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8813 "CPU PWM1 enabled\n");
8814 if (IS_HASWELL(dev_priv))
8815 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8816 "CPU PWM2 enabled\n");
8817 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8818 "PCH PWM1 enabled\n");
8819 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8820 "Utility pin enabled\n");
8821 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8822
8823 /*
8824 * In theory we can still leave IRQs enabled, as long as only the HPD
8825 * interrupts remain enabled. We used to check for that, but since it's
8826 * gen-specific and since we only disable LCPLL after we fully disable
8827 * the interrupts, the check below should be enough.
8828 */
8829 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8830 }
8831
8832 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8833 {
8834 if (IS_HASWELL(dev_priv))
8835 return I915_READ(D_COMP_HSW);
8836 else
8837 return I915_READ(D_COMP_BDW);
8838 }
8839
8840 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8841 {
8842 if (IS_HASWELL(dev_priv)) {
8843 mutex_lock(&dev_priv->rps.hw_lock);
8844 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8845 val))
8846 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8847 mutex_unlock(&dev_priv->rps.hw_lock);
8848 } else {
8849 I915_WRITE(D_COMP_BDW, val);
8850 POSTING_READ(D_COMP_BDW);
8851 }
8852 }
8853
8854 /*
8855 * This function implements pieces of two sequences from BSpec:
8856 * - Sequence for display software to disable LCPLL
8857 * - Sequence for display software to allow package C8+
8858 * The steps implemented here are just the steps that actually touch the LCPLL
8859 * register. Callers should take care of disabling all the display engine
8860 * functions, doing the mode unset, fixing interrupts, etc.
8861 */
8862 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8863 bool switch_to_fclk, bool allow_power_down)
8864 {
8865 uint32_t val;
8866
8867 assert_can_disable_lcpll(dev_priv);
8868
8869 val = I915_READ(LCPLL_CTL);
8870
8871 if (switch_to_fclk) {
8872 val |= LCPLL_CD_SOURCE_FCLK;
8873 I915_WRITE(LCPLL_CTL, val);
8874
8875 if (wait_for_us(I915_READ(LCPLL_CTL) &
8876 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8877 DRM_ERROR("Switching to FCLK failed\n");
8878
8879 val = I915_READ(LCPLL_CTL);
8880 }
8881
8882 val |= LCPLL_PLL_DISABLE;
8883 I915_WRITE(LCPLL_CTL, val);
8884 POSTING_READ(LCPLL_CTL);
8885
8886 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8887 DRM_ERROR("LCPLL still locked\n");
8888
8889 val = hsw_read_dcomp(dev_priv);
8890 val |= D_COMP_COMP_DISABLE;
8891 hsw_write_dcomp(dev_priv, val);
8892 ndelay(100);
8893
8894 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8895 1))
8896 DRM_ERROR("D_COMP RCOMP still in progress\n");
8897
8898 if (allow_power_down) {
8899 val = I915_READ(LCPLL_CTL);
8900 val |= LCPLL_POWER_DOWN_ALLOW;
8901 I915_WRITE(LCPLL_CTL, val);
8902 POSTING_READ(LCPLL_CTL);
8903 }
8904 }
8905
8906 /*
8907 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8908 * source.
8909 */
8910 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8911 {
8912 uint32_t val;
8913
8914 val = I915_READ(LCPLL_CTL);
8915
8916 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8917 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8918 return;
8919
8920 /*
8921 * Make sure we're not on PC8 state before disabling PC8, otherwise
8922 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8923 */
8924 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8925
8926 if (val & LCPLL_POWER_DOWN_ALLOW) {
8927 val &= ~LCPLL_POWER_DOWN_ALLOW;
8928 I915_WRITE(LCPLL_CTL, val);
8929 POSTING_READ(LCPLL_CTL);
8930 }
8931
8932 val = hsw_read_dcomp(dev_priv);
8933 val |= D_COMP_COMP_FORCE;
8934 val &= ~D_COMP_COMP_DISABLE;
8935 hsw_write_dcomp(dev_priv, val);
8936
8937 val = I915_READ(LCPLL_CTL);
8938 val &= ~LCPLL_PLL_DISABLE;
8939 I915_WRITE(LCPLL_CTL, val);
8940
8941 if (intel_wait_for_register(dev_priv,
8942 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8943 5))
8944 DRM_ERROR("LCPLL not locked yet\n");
8945
8946 if (val & LCPLL_CD_SOURCE_FCLK) {
8947 val = I915_READ(LCPLL_CTL);
8948 val &= ~LCPLL_CD_SOURCE_FCLK;
8949 I915_WRITE(LCPLL_CTL, val);
8950
8951 if (wait_for_us((I915_READ(LCPLL_CTL) &
8952 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8953 DRM_ERROR("Switching back to LCPLL failed\n");
8954 }
8955
8956 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8957 intel_update_cdclk(dev_priv);
8958 }
8959
8960 /*
8961 * Package states C8 and deeper are really deep PC states that can only be
8962 * reached when all the devices on the system allow it, so even if the graphics
8963 * device allows PC8+, it doesn't mean the system will actually get to these
8964 * states. Our driver only allows PC8+ when going into runtime PM.
8965 *
8966 * The requirements for PC8+ are that all the outputs are disabled, the power
8967 * well is disabled and most interrupts are disabled, and these are also
8968 * requirements for runtime PM. When these conditions are met, we manually do
8969 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8970 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8971 * hang the machine.
8972 *
8973 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8974 * the state of some registers, so when we come back from PC8+ we need to
8975 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8976 * need to take care of the registers kept by RC6. Notice that this happens even
8977 * if we don't put the device in PCI D3 state (which is what currently happens
8978 * because of the runtime PM support).
8979 *
8980 * For more, read "Display Sequences for Package C8" on the hardware
8981 * documentation.
8982 */
8983 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8984 {
8985 uint32_t val;
8986
8987 DRM_DEBUG_KMS("Enabling package C8+\n");
8988
8989 if (HAS_PCH_LPT_LP(dev_priv)) {
8990 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8991 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8992 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8993 }
8994
8995 lpt_disable_clkout_dp(dev_priv);
8996 hsw_disable_lcpll(dev_priv, true, true);
8997 }
8998
8999 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9000 {
9001 uint32_t val;
9002
9003 DRM_DEBUG_KMS("Disabling package C8+\n");
9004
9005 hsw_restore_lcpll(dev_priv);
9006 lpt_init_pch_refclk(dev_priv);
9007
9008 if (HAS_PCH_LPT_LP(dev_priv)) {
9009 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9010 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9011 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9012 }
9013 }
9014
9015 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9016 struct intel_crtc_state *crtc_state)
9017 {
9018 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
9019 struct intel_encoder *encoder =
9020 intel_ddi_get_crtc_new_encoder(crtc_state);
9021
9022 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
9023 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9024 pipe_name(crtc->pipe));
9025 return -EINVAL;
9026 }
9027 }
9028
9029 crtc->lowfreq_avail = false;
9030
9031 return 0;
9032 }
9033
9034 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
9035 enum port port,
9036 struct intel_crtc_state *pipe_config)
9037 {
9038 enum intel_dpll_id id;
9039 u32 temp;
9040
9041 temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
9042 id = temp >> (port * 2);
9043
9044 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
9045 return;
9046
9047 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9048 }
9049
9050 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9051 enum port port,
9052 struct intel_crtc_state *pipe_config)
9053 {
9054 enum intel_dpll_id id;
9055
9056 switch (port) {
9057 case PORT_A:
9058 id = DPLL_ID_SKL_DPLL0;
9059 break;
9060 case PORT_B:
9061 id = DPLL_ID_SKL_DPLL1;
9062 break;
9063 case PORT_C:
9064 id = DPLL_ID_SKL_DPLL2;
9065 break;
9066 default:
9067 DRM_ERROR("Incorrect port type\n");
9068 return;
9069 }
9070
9071 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9072 }
9073
9074 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9075 enum port port,
9076 struct intel_crtc_state *pipe_config)
9077 {
9078 enum intel_dpll_id id;
9079 u32 temp;
9080
9081 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9082 id = temp >> (port * 3 + 1);
9083
9084 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
9085 return;
9086
9087 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9088 }
9089
9090 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9091 enum port port,
9092 struct intel_crtc_state *pipe_config)
9093 {
9094 enum intel_dpll_id id;
9095 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9096
9097 switch (ddi_pll_sel) {
9098 case PORT_CLK_SEL_WRPLL1:
9099 id = DPLL_ID_WRPLL1;
9100 break;
9101 case PORT_CLK_SEL_WRPLL2:
9102 id = DPLL_ID_WRPLL2;
9103 break;
9104 case PORT_CLK_SEL_SPLL:
9105 id = DPLL_ID_SPLL;
9106 break;
9107 case PORT_CLK_SEL_LCPLL_810:
9108 id = DPLL_ID_LCPLL_810;
9109 break;
9110 case PORT_CLK_SEL_LCPLL_1350:
9111 id = DPLL_ID_LCPLL_1350;
9112 break;
9113 case PORT_CLK_SEL_LCPLL_2700:
9114 id = DPLL_ID_LCPLL_2700;
9115 break;
9116 default:
9117 MISSING_CASE(ddi_pll_sel);
9118 /* fall through */
9119 case PORT_CLK_SEL_NONE:
9120 return;
9121 }
9122
9123 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9124 }
9125
9126 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9127 struct intel_crtc_state *pipe_config,
9128 u64 *power_domain_mask)
9129 {
9130 struct drm_device *dev = crtc->base.dev;
9131 struct drm_i915_private *dev_priv = to_i915(dev);
9132 enum intel_display_power_domain power_domain;
9133 u32 tmp;
9134
9135 /*
9136 * The pipe->transcoder mapping is fixed with the exception of the eDP
9137 * transcoder handled below.
9138 */
9139 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9140
9141 /*
9142 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9143 * consistency and less surprising code; it's in always on power).
9144 */
9145 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9146 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9147 enum pipe trans_edp_pipe;
9148 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9149 default:
9150 WARN(1, "unknown pipe linked to edp transcoder\n");
9151 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9152 case TRANS_DDI_EDP_INPUT_A_ON:
9153 trans_edp_pipe = PIPE_A;
9154 break;
9155 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9156 trans_edp_pipe = PIPE_B;
9157 break;
9158 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9159 trans_edp_pipe = PIPE_C;
9160 break;
9161 }
9162
9163 if (trans_edp_pipe == crtc->pipe)
9164 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9165 }
9166
9167 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9168 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9169 return false;
9170 *power_domain_mask |= BIT_ULL(power_domain);
9171
9172 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9173
9174 return tmp & PIPECONF_ENABLE;
9175 }
9176
9177 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9178 struct intel_crtc_state *pipe_config,
9179 u64 *power_domain_mask)
9180 {
9181 struct drm_device *dev = crtc->base.dev;
9182 struct drm_i915_private *dev_priv = to_i915(dev);
9183 enum intel_display_power_domain power_domain;
9184 enum port port;
9185 enum transcoder cpu_transcoder;
9186 u32 tmp;
9187
9188 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9189 if (port == PORT_A)
9190 cpu_transcoder = TRANSCODER_DSI_A;
9191 else
9192 cpu_transcoder = TRANSCODER_DSI_C;
9193
9194 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9195 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9196 continue;
9197 *power_domain_mask |= BIT_ULL(power_domain);
9198
9199 /*
9200 * The PLL needs to be enabled with a valid divider
9201 * configuration, otherwise accessing DSI registers will hang
9202 * the machine. See BSpec North Display Engine
9203 * registers/MIPI[BXT]. We can break out here early, since we
9204 * need the same DSI PLL to be enabled for both DSI ports.
9205 */
9206 if (!intel_dsi_pll_is_enabled(dev_priv))
9207 break;
9208
9209 /* XXX: this works for video mode only */
9210 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9211 if (!(tmp & DPI_ENABLE))
9212 continue;
9213
9214 tmp = I915_READ(MIPI_CTRL(port));
9215 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9216 continue;
9217
9218 pipe_config->cpu_transcoder = cpu_transcoder;
9219 break;
9220 }
9221
9222 return transcoder_is_dsi(pipe_config->cpu_transcoder);
9223 }
9224
9225 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9226 struct intel_crtc_state *pipe_config)
9227 {
9228 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9229 struct intel_shared_dpll *pll;
9230 enum port port;
9231 uint32_t tmp;
9232
9233 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9234
9235 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9236
9237 if (IS_CANNONLAKE(dev_priv))
9238 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9239 else if (IS_GEN9_BC(dev_priv))
9240 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9241 else if (IS_GEN9_LP(dev_priv))
9242 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9243 else
9244 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9245
9246 pll = pipe_config->shared_dpll;
9247 if (pll) {
9248 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9249 &pipe_config->dpll_hw_state));
9250 }
9251
9252 /*
9253 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9254 * DDI E. So just check whether this pipe is wired to DDI E and whether
9255 * the PCH transcoder is on.
9256 */
9257 if (INTEL_GEN(dev_priv) < 9 &&
9258 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9259 pipe_config->has_pch_encoder = true;
9260
9261 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9262 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9263 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9264
9265 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9266 }
9267 }
9268
9269 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9270 struct intel_crtc_state *pipe_config)
9271 {
9272 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9273 enum intel_display_power_domain power_domain;
9274 u64 power_domain_mask;
9275 bool active;
9276
9277 intel_crtc_init_scalers(crtc, pipe_config);
9278
9279 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9280 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9281 return false;
9282 power_domain_mask = BIT_ULL(power_domain);
9283
9284 pipe_config->shared_dpll = NULL;
9285
9286 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9287
9288 if (IS_GEN9_LP(dev_priv) &&
9289 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9290 WARN_ON(active);
9291 active = true;
9292 }
9293
9294 if (!active)
9295 goto out;
9296
9297 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9298 haswell_get_ddi_port_state(crtc, pipe_config);
9299 intel_get_pipe_timings(crtc, pipe_config);
9300 }
9301
9302 intel_get_pipe_src_size(crtc, pipe_config);
9303
9304 pipe_config->gamma_mode =
9305 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9306
9307 if (IS_BROADWELL(dev_priv) || dev_priv->info.gen >= 9) {
9308 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
9309 bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
9310
9311 if (IS_GEMINILAKE(dev_priv) || dev_priv->info.gen >= 10) {
9312 bool blend_mode_420 = tmp &
9313 PIPEMISC_YUV420_MODE_FULL_BLEND;
9314
9315 pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE;
9316 if (pipe_config->ycbcr420 != clrspace_yuv ||
9317 pipe_config->ycbcr420 != blend_mode_420)
9318 DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp);
9319 } else if (clrspace_yuv) {
9320 DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n");
9321 }
9322 }
9323
9324 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9325 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9326 power_domain_mask |= BIT_ULL(power_domain);
9327 if (INTEL_GEN(dev_priv) >= 9)
9328 skylake_get_pfit_config(crtc, pipe_config);
9329 else
9330 ironlake_get_pfit_config(crtc, pipe_config);
9331 }
9332
9333 if (IS_HASWELL(dev_priv))
9334 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9335 (I915_READ(IPS_CTL) & IPS_ENABLE);
9336
9337 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9338 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9339 pipe_config->pixel_multiplier =
9340 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9341 } else {
9342 pipe_config->pixel_multiplier = 1;
9343 }
9344
9345 out:
9346 for_each_power_domain(power_domain, power_domain_mask)
9347 intel_display_power_put(dev_priv, power_domain);
9348
9349 return active;
9350 }
9351
9352 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9353 {
9354 struct drm_i915_private *dev_priv =
9355 to_i915(plane_state->base.plane->dev);
9356 const struct drm_framebuffer *fb = plane_state->base.fb;
9357 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9358 u32 base;
9359
9360 if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9361 base = obj->phys_handle->busaddr;
9362 else
9363 base = intel_plane_ggtt_offset(plane_state);
9364
9365 base += plane_state->main.offset;
9366
9367 /* ILK+ do this automagically */
9368 if (HAS_GMCH_DISPLAY(dev_priv) &&
9369 plane_state->base.rotation & DRM_MODE_ROTATE_180)
9370 base += (plane_state->base.crtc_h *
9371 plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9372
9373 return base;
9374 }
9375
9376 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9377 {
9378 int x = plane_state->base.crtc_x;
9379 int y = plane_state->base.crtc_y;
9380 u32 pos = 0;
9381
9382 if (x < 0) {
9383 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9384 x = -x;
9385 }
9386 pos |= x << CURSOR_X_SHIFT;
9387
9388 if (y < 0) {
9389 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9390 y = -y;
9391 }
9392 pos |= y << CURSOR_Y_SHIFT;
9393
9394 return pos;
9395 }
9396
9397 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9398 {
9399 const struct drm_mode_config *config =
9400 &plane_state->base.plane->dev->mode_config;
9401 int width = plane_state->base.crtc_w;
9402 int height = plane_state->base.crtc_h;
9403
9404 return width > 0 && width <= config->cursor_width &&
9405 height > 0 && height <= config->cursor_height;
9406 }
9407
9408 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9409 struct intel_plane_state *plane_state)
9410 {
9411 const struct drm_framebuffer *fb = plane_state->base.fb;
9412 int src_x, src_y;
9413 u32 offset;
9414 int ret;
9415
9416 ret = drm_plane_helper_check_state(&plane_state->base,
9417 &plane_state->clip,
9418 DRM_PLANE_HELPER_NO_SCALING,
9419 DRM_PLANE_HELPER_NO_SCALING,
9420 true, true);
9421 if (ret)
9422 return ret;
9423
9424 if (!fb)
9425 return 0;
9426
9427 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9428 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9429 return -EINVAL;
9430 }
9431
9432 src_x = plane_state->base.src_x >> 16;
9433 src_y = plane_state->base.src_y >> 16;
9434
9435 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9436 offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9437
9438 if (src_x != 0 || src_y != 0) {
9439 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9440 return -EINVAL;
9441 }
9442
9443 plane_state->main.offset = offset;
9444
9445 return 0;
9446 }
9447
9448 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9449 const struct intel_plane_state *plane_state)
9450 {
9451 const struct drm_framebuffer *fb = plane_state->base.fb;
9452
9453 return CURSOR_ENABLE |
9454 CURSOR_GAMMA_ENABLE |
9455 CURSOR_FORMAT_ARGB |
9456 CURSOR_STRIDE(fb->pitches[0]);
9457 }
9458
9459 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9460 {
9461 int width = plane_state->base.crtc_w;
9462
9463 /*
9464 * 845g/865g are only limited by the width of their cursors,
9465 * the height is arbitrary up to the precision of the register.
9466 */
9467 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9468 }
9469
9470 static int i845_check_cursor(struct intel_plane *plane,
9471 struct intel_crtc_state *crtc_state,
9472 struct intel_plane_state *plane_state)
9473 {
9474 const struct drm_framebuffer *fb = plane_state->base.fb;
9475 int ret;
9476
9477 ret = intel_check_cursor(crtc_state, plane_state);
9478 if (ret)
9479 return ret;
9480
9481 /* if we want to turn off the cursor ignore width and height */
9482 if (!fb)
9483 return 0;
9484
9485 /* Check for which cursor types we support */
9486 if (!i845_cursor_size_ok(plane_state)) {
9487 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9488 plane_state->base.crtc_w,
9489 plane_state->base.crtc_h);
9490 return -EINVAL;
9491 }
9492
9493 switch (fb->pitches[0]) {
9494 case 256:
9495 case 512:
9496 case 1024:
9497 case 2048:
9498 break;
9499 default:
9500 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9501 fb->pitches[0]);
9502 return -EINVAL;
9503 }
9504
9505 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9506
9507 return 0;
9508 }
9509
9510 static void i845_update_cursor(struct intel_plane *plane,
9511 const struct intel_crtc_state *crtc_state,
9512 const struct intel_plane_state *plane_state)
9513 {
9514 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9515 u32 cntl = 0, base = 0, pos = 0, size = 0;
9516 unsigned long irqflags;
9517
9518 if (plane_state && plane_state->base.visible) {
9519 unsigned int width = plane_state->base.crtc_w;
9520 unsigned int height = plane_state->base.crtc_h;
9521
9522 cntl = plane_state->ctl;
9523 size = (height << 12) | width;
9524
9525 base = intel_cursor_base(plane_state);
9526 pos = intel_cursor_position(plane_state);
9527 }
9528
9529 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9530
9531 /* On these chipsets we can only modify the base/size/stride
9532 * whilst the cursor is disabled.
9533 */
9534 if (plane->cursor.base != base ||
9535 plane->cursor.size != size ||
9536 plane->cursor.cntl != cntl) {
9537 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9538 I915_WRITE_FW(CURBASE(PIPE_A), base);
9539 I915_WRITE_FW(CURSIZE, size);
9540 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9541 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9542
9543 plane->cursor.base = base;
9544 plane->cursor.size = size;
9545 plane->cursor.cntl = cntl;
9546 } else {
9547 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9548 }
9549
9550 POSTING_READ_FW(CURCNTR(PIPE_A));
9551
9552 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9553 }
9554
9555 static void i845_disable_cursor(struct intel_plane *plane,
9556 struct intel_crtc *crtc)
9557 {
9558 i845_update_cursor(plane, NULL, NULL);
9559 }
9560
9561 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9562 const struct intel_plane_state *plane_state)
9563 {
9564 struct drm_i915_private *dev_priv =
9565 to_i915(plane_state->base.plane->dev);
9566 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9567 u32 cntl;
9568
9569 cntl = MCURSOR_GAMMA_ENABLE;
9570
9571 if (HAS_DDI(dev_priv))
9572 cntl |= CURSOR_PIPE_CSC_ENABLE;
9573
9574 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9575
9576 switch (plane_state->base.crtc_w) {
9577 case 64:
9578 cntl |= CURSOR_MODE_64_ARGB_AX;
9579 break;
9580 case 128:
9581 cntl |= CURSOR_MODE_128_ARGB_AX;
9582 break;
9583 case 256:
9584 cntl |= CURSOR_MODE_256_ARGB_AX;
9585 break;
9586 default:
9587 MISSING_CASE(plane_state->base.crtc_w);
9588 return 0;
9589 }
9590
9591 if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9592 cntl |= CURSOR_ROTATE_180;
9593
9594 return cntl;
9595 }
9596
9597 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9598 {
9599 struct drm_i915_private *dev_priv =
9600 to_i915(plane_state->base.plane->dev);
9601 int width = plane_state->base.crtc_w;
9602 int height = plane_state->base.crtc_h;
9603
9604 if (!intel_cursor_size_ok(plane_state))
9605 return false;
9606
9607 /* Cursor width is limited to a few power-of-two sizes */
9608 switch (width) {
9609 case 256:
9610 case 128:
9611 case 64:
9612 break;
9613 default:
9614 return false;
9615 }
9616
9617 /*
9618 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9619 * height from 8 lines up to the cursor width, when the
9620 * cursor is not rotated. Everything else requires square
9621 * cursors.
9622 */
9623 if (HAS_CUR_FBC(dev_priv) &&
9624 plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9625 if (height < 8 || height > width)
9626 return false;
9627 } else {
9628 if (height != width)
9629 return false;
9630 }
9631
9632 return true;
9633 }
9634
9635 static int i9xx_check_cursor(struct intel_plane *plane,
9636 struct intel_crtc_state *crtc_state,
9637 struct intel_plane_state *plane_state)
9638 {
9639 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9640 const struct drm_framebuffer *fb = plane_state->base.fb;
9641 enum pipe pipe = plane->pipe;
9642 int ret;
9643
9644 ret = intel_check_cursor(crtc_state, plane_state);
9645 if (ret)
9646 return ret;
9647
9648 /* if we want to turn off the cursor ignore width and height */
9649 if (!fb)
9650 return 0;
9651
9652 /* Check for which cursor types we support */
9653 if (!i9xx_cursor_size_ok(plane_state)) {
9654 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9655 plane_state->base.crtc_w,
9656 plane_state->base.crtc_h);
9657 return -EINVAL;
9658 }
9659
9660 if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9661 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9662 fb->pitches[0], plane_state->base.crtc_w);
9663 return -EINVAL;
9664 }
9665
9666 /*
9667 * There's something wrong with the cursor on CHV pipe C.
9668 * If it straddles the left edge of the screen then
9669 * moving it away from the edge or disabling it often
9670 * results in a pipe underrun, and often that can lead to
9671 * dead pipe (constant underrun reported, and it scans
9672 * out just a solid color). To recover from that, the
9673 * display power well must be turned off and on again.
9674 * Refuse the put the cursor into that compromised position.
9675 */
9676 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9677 plane_state->base.visible && plane_state->base.crtc_x < 0) {
9678 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9679 return -EINVAL;
9680 }
9681
9682 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9683
9684 return 0;
9685 }
9686
9687 static void i9xx_update_cursor(struct intel_plane *plane,
9688 const struct intel_crtc_state *crtc_state,
9689 const struct intel_plane_state *plane_state)
9690 {
9691 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9692 enum pipe pipe = plane->pipe;
9693 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9694 unsigned long irqflags;
9695
9696 if (plane_state && plane_state->base.visible) {
9697 cntl = plane_state->ctl;
9698
9699 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9700 fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9701
9702 base = intel_cursor_base(plane_state);
9703 pos = intel_cursor_position(plane_state);
9704 }
9705
9706 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9707
9708 /*
9709 * On some platforms writing CURCNTR first will also
9710 * cause CURPOS to be armed by the CURBASE write.
9711 * Without the CURCNTR write the CURPOS write would
9712 * arm itself. Thus we always start the full update
9713 * with a CURCNTR write.
9714 *
9715 * On other platforms CURPOS always requires the
9716 * CURBASE write to arm the update. Additonally
9717 * a write to any of the cursor register will cancel
9718 * an already armed cursor update. Thus leaving out
9719 * the CURBASE write after CURPOS could lead to a
9720 * cursor that doesn't appear to move, or even change
9721 * shape. Thus we always write CURBASE.
9722 *
9723 * CURCNTR and CUR_FBC_CTL are always
9724 * armed by the CURBASE write only.
9725 */
9726 if (plane->cursor.base != base ||
9727 plane->cursor.size != fbc_ctl ||
9728 plane->cursor.cntl != cntl) {
9729 I915_WRITE_FW(CURCNTR(pipe), cntl);
9730 if (HAS_CUR_FBC(dev_priv))
9731 I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
9732 I915_WRITE_FW(CURPOS(pipe), pos);
9733 I915_WRITE_FW(CURBASE(pipe), base);
9734
9735 plane->cursor.base = base;
9736 plane->cursor.size = fbc_ctl;
9737 plane->cursor.cntl = cntl;
9738 } else {
9739 I915_WRITE_FW(CURPOS(pipe), pos);
9740 I915_WRITE_FW(CURBASE(pipe), base);
9741 }
9742
9743 POSTING_READ_FW(CURBASE(pipe));
9744
9745 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9746 }
9747
9748 static void i9xx_disable_cursor(struct intel_plane *plane,
9749 struct intel_crtc *crtc)
9750 {
9751 i9xx_update_cursor(plane, NULL, NULL);
9752 }
9753
9754
9755 /* VESA 640x480x72Hz mode to set on the pipe */
9756 static struct drm_display_mode load_detect_mode = {
9757 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9758 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9759 };
9760
9761 struct drm_framebuffer *
9762 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9763 struct drm_mode_fb_cmd2 *mode_cmd)
9764 {
9765 struct intel_framebuffer *intel_fb;
9766 int ret;
9767
9768 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9769 if (!intel_fb)
9770 return ERR_PTR(-ENOMEM);
9771
9772 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9773 if (ret)
9774 goto err;
9775
9776 return &intel_fb->base;
9777
9778 err:
9779 kfree(intel_fb);
9780 return ERR_PTR(ret);
9781 }
9782
9783 static u32
9784 intel_framebuffer_pitch_for_width(int width, int bpp)
9785 {
9786 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9787 return ALIGN(pitch, 64);
9788 }
9789
9790 static u32
9791 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9792 {
9793 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9794 return PAGE_ALIGN(pitch * mode->vdisplay);
9795 }
9796
9797 static struct drm_framebuffer *
9798 intel_framebuffer_create_for_mode(struct drm_device *dev,
9799 struct drm_display_mode *mode,
9800 int depth, int bpp)
9801 {
9802 struct drm_framebuffer *fb;
9803 struct drm_i915_gem_object *obj;
9804 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9805
9806 obj = i915_gem_object_create(to_i915(dev),
9807 intel_framebuffer_size_for_mode(mode, bpp));
9808 if (IS_ERR(obj))
9809 return ERR_CAST(obj);
9810
9811 mode_cmd.width = mode->hdisplay;
9812 mode_cmd.height = mode->vdisplay;
9813 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9814 bpp);
9815 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9816
9817 fb = intel_framebuffer_create(obj, &mode_cmd);
9818 if (IS_ERR(fb))
9819 i915_gem_object_put(obj);
9820
9821 return fb;
9822 }
9823
9824 static struct drm_framebuffer *
9825 mode_fits_in_fbdev(struct drm_device *dev,
9826 struct drm_display_mode *mode)
9827 {
9828 #ifdef CONFIG_DRM_FBDEV_EMULATION
9829 struct drm_i915_private *dev_priv = to_i915(dev);
9830 struct drm_i915_gem_object *obj;
9831 struct drm_framebuffer *fb;
9832
9833 if (!dev_priv->fbdev)
9834 return NULL;
9835
9836 if (!dev_priv->fbdev->fb)
9837 return NULL;
9838
9839 obj = dev_priv->fbdev->fb->obj;
9840 BUG_ON(!obj);
9841
9842 fb = &dev_priv->fbdev->fb->base;
9843 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9844 fb->format->cpp[0] * 8))
9845 return NULL;
9846
9847 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9848 return NULL;
9849
9850 drm_framebuffer_reference(fb);
9851 return fb;
9852 #else
9853 return NULL;
9854 #endif
9855 }
9856
9857 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9858 struct drm_crtc *crtc,
9859 struct drm_display_mode *mode,
9860 struct drm_framebuffer *fb,
9861 int x, int y)
9862 {
9863 struct drm_plane_state *plane_state;
9864 int hdisplay, vdisplay;
9865 int ret;
9866
9867 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9868 if (IS_ERR(plane_state))
9869 return PTR_ERR(plane_state);
9870
9871 if (mode)
9872 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9873 else
9874 hdisplay = vdisplay = 0;
9875
9876 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9877 if (ret)
9878 return ret;
9879 drm_atomic_set_fb_for_plane(plane_state, fb);
9880 plane_state->crtc_x = 0;
9881 plane_state->crtc_y = 0;
9882 plane_state->crtc_w = hdisplay;
9883 plane_state->crtc_h = vdisplay;
9884 plane_state->src_x = x << 16;
9885 plane_state->src_y = y << 16;
9886 plane_state->src_w = hdisplay << 16;
9887 plane_state->src_h = vdisplay << 16;
9888
9889 return 0;
9890 }
9891
9892 int intel_get_load_detect_pipe(struct drm_connector *connector,
9893 struct drm_display_mode *mode,
9894 struct intel_load_detect_pipe *old,
9895 struct drm_modeset_acquire_ctx *ctx)
9896 {
9897 struct intel_crtc *intel_crtc;
9898 struct intel_encoder *intel_encoder =
9899 intel_attached_encoder(connector);
9900 struct drm_crtc *possible_crtc;
9901 struct drm_encoder *encoder = &intel_encoder->base;
9902 struct drm_crtc *crtc = NULL;
9903 struct drm_device *dev = encoder->dev;
9904 struct drm_i915_private *dev_priv = to_i915(dev);
9905 struct drm_framebuffer *fb;
9906 struct drm_mode_config *config = &dev->mode_config;
9907 struct drm_atomic_state *state = NULL, *restore_state = NULL;
9908 struct drm_connector_state *connector_state;
9909 struct intel_crtc_state *crtc_state;
9910 int ret, i = -1;
9911
9912 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9913 connector->base.id, connector->name,
9914 encoder->base.id, encoder->name);
9915
9916 old->restore_state = NULL;
9917
9918 WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
9919
9920 /*
9921 * Algorithm gets a little messy:
9922 *
9923 * - if the connector already has an assigned crtc, use it (but make
9924 * sure it's on first)
9925 *
9926 * - try to find the first unused crtc that can drive this connector,
9927 * and use that if we find one
9928 */
9929
9930 /* See if we already have a CRTC for this connector */
9931 if (connector->state->crtc) {
9932 crtc = connector->state->crtc;
9933
9934 ret = drm_modeset_lock(&crtc->mutex, ctx);
9935 if (ret)
9936 goto fail;
9937
9938 /* Make sure the crtc and connector are running */
9939 goto found;
9940 }
9941
9942 /* Find an unused one (if possible) */
9943 for_each_crtc(dev, possible_crtc) {
9944 i++;
9945 if (!(encoder->possible_crtcs & (1 << i)))
9946 continue;
9947
9948 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9949 if (ret)
9950 goto fail;
9951
9952 if (possible_crtc->state->enable) {
9953 drm_modeset_unlock(&possible_crtc->mutex);
9954 continue;
9955 }
9956
9957 crtc = possible_crtc;
9958 break;
9959 }
9960
9961 /*
9962 * If we didn't find an unused CRTC, don't use any.
9963 */
9964 if (!crtc) {
9965 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9966 ret = -ENODEV;
9967 goto fail;
9968 }
9969
9970 found:
9971 intel_crtc = to_intel_crtc(crtc);
9972
9973 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9974 if (ret)
9975 goto fail;
9976
9977 state = drm_atomic_state_alloc(dev);
9978 restore_state = drm_atomic_state_alloc(dev);
9979 if (!state || !restore_state) {
9980 ret = -ENOMEM;
9981 goto fail;
9982 }
9983
9984 state->acquire_ctx = ctx;
9985 restore_state->acquire_ctx = ctx;
9986
9987 connector_state = drm_atomic_get_connector_state(state, connector);
9988 if (IS_ERR(connector_state)) {
9989 ret = PTR_ERR(connector_state);
9990 goto fail;
9991 }
9992
9993 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9994 if (ret)
9995 goto fail;
9996
9997 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9998 if (IS_ERR(crtc_state)) {
9999 ret = PTR_ERR(crtc_state);
10000 goto fail;
10001 }
10002
10003 crtc_state->base.active = crtc_state->base.enable = true;
10004
10005 if (!mode)
10006 mode = &load_detect_mode;
10007
10008 /* We need a framebuffer large enough to accommodate all accesses
10009 * that the plane may generate whilst we perform load detection.
10010 * We can not rely on the fbcon either being present (we get called
10011 * during its initialisation to detect all boot displays, or it may
10012 * not even exist) or that it is large enough to satisfy the
10013 * requested mode.
10014 */
10015 fb = mode_fits_in_fbdev(dev, mode);
10016 if (fb == NULL) {
10017 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10018 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10019 } else
10020 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10021 if (IS_ERR(fb)) {
10022 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10023 ret = PTR_ERR(fb);
10024 goto fail;
10025 }
10026
10027 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10028 if (ret)
10029 goto fail;
10030
10031 drm_framebuffer_unreference(fb);
10032
10033 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10034 if (ret)
10035 goto fail;
10036
10037 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10038 if (!ret)
10039 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10040 if (!ret)
10041 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10042 if (ret) {
10043 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10044 goto fail;
10045 }
10046
10047 ret = drm_atomic_commit(state);
10048 if (ret) {
10049 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10050 goto fail;
10051 }
10052
10053 old->restore_state = restore_state;
10054 drm_atomic_state_put(state);
10055
10056 /* let the connector get through one full cycle before testing */
10057 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
10058 return true;
10059
10060 fail:
10061 if (state) {
10062 drm_atomic_state_put(state);
10063 state = NULL;
10064 }
10065 if (restore_state) {
10066 drm_atomic_state_put(restore_state);
10067 restore_state = NULL;
10068 }
10069
10070 if (ret == -EDEADLK)
10071 return ret;
10072
10073 return false;
10074 }
10075
10076 void intel_release_load_detect_pipe(struct drm_connector *connector,
10077 struct intel_load_detect_pipe *old,
10078 struct drm_modeset_acquire_ctx *ctx)
10079 {
10080 struct intel_encoder *intel_encoder =
10081 intel_attached_encoder(connector);
10082 struct drm_encoder *encoder = &intel_encoder->base;
10083 struct drm_atomic_state *state = old->restore_state;
10084 int ret;
10085
10086 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10087 connector->base.id, connector->name,
10088 encoder->base.id, encoder->name);
10089
10090 if (!state)
10091 return;
10092
10093 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
10094 if (ret)
10095 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10096 drm_atomic_state_put(state);
10097 }
10098
10099 static int i9xx_pll_refclk(struct drm_device *dev,
10100 const struct intel_crtc_state *pipe_config)
10101 {
10102 struct drm_i915_private *dev_priv = to_i915(dev);
10103 u32 dpll = pipe_config->dpll_hw_state.dpll;
10104
10105 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10106 return dev_priv->vbt.lvds_ssc_freq;
10107 else if (HAS_PCH_SPLIT(dev_priv))
10108 return 120000;
10109 else if (!IS_GEN2(dev_priv))
10110 return 96000;
10111 else
10112 return 48000;
10113 }
10114
10115 /* Returns the clock of the currently programmed mode of the given pipe. */
10116 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10117 struct intel_crtc_state *pipe_config)
10118 {
10119 struct drm_device *dev = crtc->base.dev;
10120 struct drm_i915_private *dev_priv = to_i915(dev);
10121 int pipe = pipe_config->cpu_transcoder;
10122 u32 dpll = pipe_config->dpll_hw_state.dpll;
10123 u32 fp;
10124 struct dpll clock;
10125 int port_clock;
10126 int refclk = i9xx_pll_refclk(dev, pipe_config);
10127
10128 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10129 fp = pipe_config->dpll_hw_state.fp0;
10130 else
10131 fp = pipe_config->dpll_hw_state.fp1;
10132
10133 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10134 if (IS_PINEVIEW(dev_priv)) {
10135 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10136 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10137 } else {
10138 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10139 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10140 }
10141
10142 if (!IS_GEN2(dev_priv)) {
10143 if (IS_PINEVIEW(dev_priv))
10144 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10145 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10146 else
10147 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10148 DPLL_FPA01_P1_POST_DIV_SHIFT);
10149
10150 switch (dpll & DPLL_MODE_MASK) {
10151 case DPLLB_MODE_DAC_SERIAL:
10152 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10153 5 : 10;
10154 break;
10155 case DPLLB_MODE_LVDS:
10156 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10157 7 : 14;
10158 break;
10159 default:
10160 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10161 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10162 return;
10163 }
10164
10165 if (IS_PINEVIEW(dev_priv))
10166 port_clock = pnv_calc_dpll_params(refclk, &clock);
10167 else
10168 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10169 } else {
10170 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
10171 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10172
10173 if (is_lvds) {
10174 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10175 DPLL_FPA01_P1_POST_DIV_SHIFT);
10176
10177 if (lvds & LVDS_CLKB_POWER_UP)
10178 clock.p2 = 7;
10179 else
10180 clock.p2 = 14;
10181 } else {
10182 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10183 clock.p1 = 2;
10184 else {
10185 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10186 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10187 }
10188 if (dpll & PLL_P2_DIVIDE_BY_4)
10189 clock.p2 = 4;
10190 else
10191 clock.p2 = 2;
10192 }
10193
10194 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10195 }
10196
10197 /*
10198 * This value includes pixel_multiplier. We will use
10199 * port_clock to compute adjusted_mode.crtc_clock in the
10200 * encoder's get_config() function.
10201 */
10202 pipe_config->port_clock = port_clock;
10203 }
10204
10205 int intel_dotclock_calculate(int link_freq,
10206 const struct intel_link_m_n *m_n)
10207 {
10208 /*
10209 * The calculation for the data clock is:
10210 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10211 * But we want to avoid losing precison if possible, so:
10212 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10213 *
10214 * and the link clock is simpler:
10215 * link_clock = (m * link_clock) / n
10216 */
10217
10218 if (!m_n->link_n)
10219 return 0;
10220
10221 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10222 }
10223
10224 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10225 struct intel_crtc_state *pipe_config)
10226 {
10227 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10228
10229 /* read out port_clock from the DPLL */
10230 i9xx_crtc_clock_get(crtc, pipe_config);
10231
10232 /*
10233 * In case there is an active pipe without active ports,
10234 * we may need some idea for the dotclock anyway.
10235 * Calculate one based on the FDI configuration.
10236 */
10237 pipe_config->base.adjusted_mode.crtc_clock =
10238 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10239 &pipe_config->fdi_m_n);
10240 }
10241
10242 /** Returns the currently programmed mode of the given pipe. */
10243 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10244 struct drm_crtc *crtc)
10245 {
10246 struct drm_i915_private *dev_priv = to_i915(dev);
10247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10248 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10249 struct drm_display_mode *mode;
10250 struct intel_crtc_state *pipe_config;
10251 int htot = I915_READ(HTOTAL(cpu_transcoder));
10252 int hsync = I915_READ(HSYNC(cpu_transcoder));
10253 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10254 int vsync = I915_READ(VSYNC(cpu_transcoder));
10255 enum pipe pipe = intel_crtc->pipe;
10256
10257 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10258 if (!mode)
10259 return NULL;
10260
10261 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10262 if (!pipe_config) {
10263 kfree(mode);
10264 return NULL;
10265 }
10266
10267 /*
10268 * Construct a pipe_config sufficient for getting the clock info
10269 * back out of crtc_clock_get.
10270 *
10271 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10272 * to use a real value here instead.
10273 */
10274 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10275 pipe_config->pixel_multiplier = 1;
10276 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10277 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10278 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10279 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10280
10281 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10282 mode->hdisplay = (htot & 0xffff) + 1;
10283 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10284 mode->hsync_start = (hsync & 0xffff) + 1;
10285 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10286 mode->vdisplay = (vtot & 0xffff) + 1;
10287 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10288 mode->vsync_start = (vsync & 0xffff) + 1;
10289 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10290
10291 drm_mode_set_name(mode);
10292
10293 kfree(pipe_config);
10294
10295 return mode;
10296 }
10297
10298 static void intel_crtc_destroy(struct drm_crtc *crtc)
10299 {
10300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10301
10302 drm_crtc_cleanup(crtc);
10303 kfree(intel_crtc);
10304 }
10305
10306 /**
10307 * intel_wm_need_update - Check whether watermarks need updating
10308 * @plane: drm plane
10309 * @state: new plane state
10310 *
10311 * Check current plane state versus the new one to determine whether
10312 * watermarks need to be recalculated.
10313 *
10314 * Returns true or false.
10315 */
10316 static bool intel_wm_need_update(struct drm_plane *plane,
10317 struct drm_plane_state *state)
10318 {
10319 struct intel_plane_state *new = to_intel_plane_state(state);
10320 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10321
10322 /* Update watermarks on tiling or size changes. */
10323 if (new->base.visible != cur->base.visible)
10324 return true;
10325
10326 if (!cur->base.fb || !new->base.fb)
10327 return false;
10328
10329 if (cur->base.fb->modifier != new->base.fb->modifier ||
10330 cur->base.rotation != new->base.rotation ||
10331 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10332 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10333 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10334 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10335 return true;
10336
10337 return false;
10338 }
10339
10340 static bool needs_scaling(struct intel_plane_state *state)
10341 {
10342 int src_w = drm_rect_width(&state->base.src) >> 16;
10343 int src_h = drm_rect_height(&state->base.src) >> 16;
10344 int dst_w = drm_rect_width(&state->base.dst);
10345 int dst_h = drm_rect_height(&state->base.dst);
10346
10347 return (src_w != dst_w || src_h != dst_h);
10348 }
10349
10350 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
10351 struct drm_plane_state *plane_state)
10352 {
10353 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10354 struct drm_crtc *crtc = crtc_state->crtc;
10355 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10356 struct intel_plane *plane = to_intel_plane(plane_state->plane);
10357 struct drm_device *dev = crtc->dev;
10358 struct drm_i915_private *dev_priv = to_i915(dev);
10359 struct intel_plane_state *old_plane_state =
10360 to_intel_plane_state(plane->base.state);
10361 bool mode_changed = needs_modeset(crtc_state);
10362 bool was_crtc_enabled = crtc->state->active;
10363 bool is_crtc_enabled = crtc_state->active;
10364 bool turn_off, turn_on, visible, was_visible;
10365 struct drm_framebuffer *fb = plane_state->fb;
10366 int ret;
10367
10368 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10369 ret = skl_update_scaler_plane(
10370 to_intel_crtc_state(crtc_state),
10371 to_intel_plane_state(plane_state));
10372 if (ret)
10373 return ret;
10374 }
10375
10376 was_visible = old_plane_state->base.visible;
10377 visible = plane_state->visible;
10378
10379 if (!was_crtc_enabled && WARN_ON(was_visible))
10380 was_visible = false;
10381
10382 /*
10383 * Visibility is calculated as if the crtc was on, but
10384 * after scaler setup everything depends on it being off
10385 * when the crtc isn't active.
10386 *
10387 * FIXME this is wrong for watermarks. Watermarks should also
10388 * be computed as if the pipe would be active. Perhaps move
10389 * per-plane wm computation to the .check_plane() hook, and
10390 * only combine the results from all planes in the current place?
10391 */
10392 if (!is_crtc_enabled) {
10393 plane_state->visible = visible = false;
10394 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10395 }
10396
10397 if (!was_visible && !visible)
10398 return 0;
10399
10400 if (fb != old_plane_state->base.fb)
10401 pipe_config->fb_changed = true;
10402
10403 turn_off = was_visible && (!visible || mode_changed);
10404 turn_on = visible && (!was_visible || mode_changed);
10405
10406 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10407 intel_crtc->base.base.id, intel_crtc->base.name,
10408 plane->base.base.id, plane->base.name,
10409 fb ? fb->base.id : -1);
10410
10411 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10412 plane->base.base.id, plane->base.name,
10413 was_visible, visible,
10414 turn_off, turn_on, mode_changed);
10415
10416 if (turn_on) {
10417 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10418 pipe_config->update_wm_pre = true;
10419
10420 /* must disable cxsr around plane enable/disable */
10421 if (plane->id != PLANE_CURSOR)
10422 pipe_config->disable_cxsr = true;
10423 } else if (turn_off) {
10424 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10425 pipe_config->update_wm_post = true;
10426
10427 /* must disable cxsr around plane enable/disable */
10428 if (plane->id != PLANE_CURSOR)
10429 pipe_config->disable_cxsr = true;
10430 } else if (intel_wm_need_update(&plane->base, plane_state)) {
10431 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
10432 /* FIXME bollocks */
10433 pipe_config->update_wm_pre = true;
10434 pipe_config->update_wm_post = true;
10435 }
10436 }
10437
10438 if (visible || was_visible)
10439 pipe_config->fb_bits |= plane->frontbuffer_bit;
10440
10441 /*
10442 * WaCxSRDisabledForSpriteScaling:ivb
10443 *
10444 * cstate->update_wm was already set above, so this flag will
10445 * take effect when we commit and program watermarks.
10446 */
10447 if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10448 needs_scaling(to_intel_plane_state(plane_state)) &&
10449 !needs_scaling(old_plane_state))
10450 pipe_config->disable_lp_wm = true;
10451
10452 return 0;
10453 }
10454
10455 static bool encoders_cloneable(const struct intel_encoder *a,
10456 const struct intel_encoder *b)
10457 {
10458 /* masks could be asymmetric, so check both ways */
10459 return a == b || (a->cloneable & (1 << b->type) &&
10460 b->cloneable & (1 << a->type));
10461 }
10462
10463 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10464 struct intel_crtc *crtc,
10465 struct intel_encoder *encoder)
10466 {
10467 struct intel_encoder *source_encoder;
10468 struct drm_connector *connector;
10469 struct drm_connector_state *connector_state;
10470 int i;
10471
10472 for_each_new_connector_in_state(state, connector, connector_state, i) {
10473 if (connector_state->crtc != &crtc->base)
10474 continue;
10475
10476 source_encoder =
10477 to_intel_encoder(connector_state->best_encoder);
10478 if (!encoders_cloneable(encoder, source_encoder))
10479 return false;
10480 }
10481
10482 return true;
10483 }
10484
10485 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10486 struct drm_crtc_state *crtc_state)
10487 {
10488 struct drm_device *dev = crtc->dev;
10489 struct drm_i915_private *dev_priv = to_i915(dev);
10490 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10491 struct intel_crtc_state *pipe_config =
10492 to_intel_crtc_state(crtc_state);
10493 struct drm_atomic_state *state = crtc_state->state;
10494 int ret;
10495 bool mode_changed = needs_modeset(crtc_state);
10496
10497 if (mode_changed && !crtc_state->active)
10498 pipe_config->update_wm_post = true;
10499
10500 if (mode_changed && crtc_state->enable &&
10501 dev_priv->display.crtc_compute_clock &&
10502 !WARN_ON(pipe_config->shared_dpll)) {
10503 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10504 pipe_config);
10505 if (ret)
10506 return ret;
10507 }
10508
10509 if (crtc_state->color_mgmt_changed) {
10510 ret = intel_color_check(crtc, crtc_state);
10511 if (ret)
10512 return ret;
10513
10514 /*
10515 * Changing color management on Intel hardware is
10516 * handled as part of planes update.
10517 */
10518 crtc_state->planes_changed = true;
10519 }
10520
10521 ret = 0;
10522 if (dev_priv->display.compute_pipe_wm) {
10523 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10524 if (ret) {
10525 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10526 return ret;
10527 }
10528 }
10529
10530 if (dev_priv->display.compute_intermediate_wm &&
10531 !to_intel_atomic_state(state)->skip_intermediate_wm) {
10532 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10533 return 0;
10534
10535 /*
10536 * Calculate 'intermediate' watermarks that satisfy both the
10537 * old state and the new state. We can program these
10538 * immediately.
10539 */
10540 ret = dev_priv->display.compute_intermediate_wm(dev,
10541 intel_crtc,
10542 pipe_config);
10543 if (ret) {
10544 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10545 return ret;
10546 }
10547 } else if (dev_priv->display.compute_intermediate_wm) {
10548 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10549 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10550 }
10551
10552 if (INTEL_GEN(dev_priv) >= 9) {
10553 if (mode_changed)
10554 ret = skl_update_scaler_crtc(pipe_config);
10555
10556 if (!ret)
10557 ret = skl_check_pipe_max_pixel_rate(intel_crtc,
10558 pipe_config);
10559 if (!ret)
10560 ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
10561 pipe_config);
10562 }
10563
10564 return ret;
10565 }
10566
10567 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
10568 .atomic_begin = intel_begin_crtc_commit,
10569 .atomic_flush = intel_finish_crtc_commit,
10570 .atomic_check = intel_crtc_atomic_check,
10571 };
10572
10573 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10574 {
10575 struct intel_connector *connector;
10576 struct drm_connector_list_iter conn_iter;
10577
10578 drm_connector_list_iter_begin(dev, &conn_iter);
10579 for_each_intel_connector_iter(connector, &conn_iter) {
10580 if (connector->base.state->crtc)
10581 drm_connector_unreference(&connector->base);
10582
10583 if (connector->base.encoder) {
10584 connector->base.state->best_encoder =
10585 connector->base.encoder;
10586 connector->base.state->crtc =
10587 connector->base.encoder->crtc;
10588
10589 drm_connector_reference(&connector->base);
10590 } else {
10591 connector->base.state->best_encoder = NULL;
10592 connector->base.state->crtc = NULL;
10593 }
10594 }
10595 drm_connector_list_iter_end(&conn_iter);
10596 }
10597
10598 static void
10599 connected_sink_compute_bpp(struct intel_connector *connector,
10600 struct intel_crtc_state *pipe_config)
10601 {
10602 const struct drm_display_info *info = &connector->base.display_info;
10603 int bpp = pipe_config->pipe_bpp;
10604
10605 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10606 connector->base.base.id,
10607 connector->base.name);
10608
10609 /* Don't use an invalid EDID bpc value */
10610 if (info->bpc != 0 && info->bpc * 3 < bpp) {
10611 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10612 bpp, info->bpc * 3);
10613 pipe_config->pipe_bpp = info->bpc * 3;
10614 }
10615
10616 /* Clamp bpp to 8 on screens without EDID 1.4 */
10617 if (info->bpc == 0 && bpp > 24) {
10618 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10619 bpp);
10620 pipe_config->pipe_bpp = 24;
10621 }
10622 }
10623
10624 static int
10625 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10626 struct intel_crtc_state *pipe_config)
10627 {
10628 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10629 struct drm_atomic_state *state;
10630 struct drm_connector *connector;
10631 struct drm_connector_state *connector_state;
10632 int bpp, i;
10633
10634 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
10635 IS_CHERRYVIEW(dev_priv)))
10636 bpp = 10*3;
10637 else if (INTEL_GEN(dev_priv) >= 5)
10638 bpp = 12*3;
10639 else
10640 bpp = 8*3;
10641
10642
10643 pipe_config->pipe_bpp = bpp;
10644
10645 state = pipe_config->base.state;
10646
10647 /* Clamp display bpp to EDID value */
10648 for_each_new_connector_in_state(state, connector, connector_state, i) {
10649 if (connector_state->crtc != &crtc->base)
10650 continue;
10651
10652 connected_sink_compute_bpp(to_intel_connector(connector),
10653 pipe_config);
10654 }
10655
10656 return bpp;
10657 }
10658
10659 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10660 {
10661 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10662 "type: 0x%x flags: 0x%x\n",
10663 mode->crtc_clock,
10664 mode->crtc_hdisplay, mode->crtc_hsync_start,
10665 mode->crtc_hsync_end, mode->crtc_htotal,
10666 mode->crtc_vdisplay, mode->crtc_vsync_start,
10667 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10668 }
10669
10670 static inline void
10671 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
10672 unsigned int lane_count, struct intel_link_m_n *m_n)
10673 {
10674 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10675 id, lane_count,
10676 m_n->gmch_m, m_n->gmch_n,
10677 m_n->link_m, m_n->link_n, m_n->tu);
10678 }
10679
10680 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10681 struct intel_crtc_state *pipe_config,
10682 const char *context)
10683 {
10684 struct drm_device *dev = crtc->base.dev;
10685 struct drm_i915_private *dev_priv = to_i915(dev);
10686 struct drm_plane *plane;
10687 struct intel_plane *intel_plane;
10688 struct intel_plane_state *state;
10689 struct drm_framebuffer *fb;
10690
10691 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
10692 crtc->base.base.id, crtc->base.name, context);
10693
10694 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
10695 transcoder_name(pipe_config->cpu_transcoder),
10696 pipe_config->pipe_bpp, pipe_config->dither);
10697
10698 if (pipe_config->has_pch_encoder)
10699 intel_dump_m_n_config(pipe_config, "fdi",
10700 pipe_config->fdi_lanes,
10701 &pipe_config->fdi_m_n);
10702
10703 if (pipe_config->ycbcr420)
10704 DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n");
10705
10706 if (intel_crtc_has_dp_encoder(pipe_config)) {
10707 intel_dump_m_n_config(pipe_config, "dp m_n",
10708 pipe_config->lane_count, &pipe_config->dp_m_n);
10709 if (pipe_config->has_drrs)
10710 intel_dump_m_n_config(pipe_config, "dp m2_n2",
10711 pipe_config->lane_count,
10712 &pipe_config->dp_m2_n2);
10713 }
10714
10715 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10716 pipe_config->has_audio, pipe_config->has_infoframe);
10717
10718 DRM_DEBUG_KMS("requested mode:\n");
10719 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10720 DRM_DEBUG_KMS("adjusted mode:\n");
10721 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10722 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10723 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
10724 pipe_config->port_clock,
10725 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
10726 pipe_config->pixel_rate);
10727
10728 if (INTEL_GEN(dev_priv) >= 9)
10729 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
10730 crtc->num_scalers,
10731 pipe_config->scaler_state.scaler_users,
10732 pipe_config->scaler_state.scaler_id);
10733
10734 if (HAS_GMCH_DISPLAY(dev_priv))
10735 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10736 pipe_config->gmch_pfit.control,
10737 pipe_config->gmch_pfit.pgm_ratios,
10738 pipe_config->gmch_pfit.lvds_border_bits);
10739 else
10740 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10741 pipe_config->pch_pfit.pos,
10742 pipe_config->pch_pfit.size,
10743 enableddisabled(pipe_config->pch_pfit.enabled));
10744
10745 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
10746 pipe_config->ips_enabled, pipe_config->double_wide);
10747
10748 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
10749
10750 DRM_DEBUG_KMS("planes on this crtc\n");
10751 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
10752 struct drm_format_name_buf format_name;
10753 intel_plane = to_intel_plane(plane);
10754 if (intel_plane->pipe != crtc->pipe)
10755 continue;
10756
10757 state = to_intel_plane_state(plane->state);
10758 fb = state->base.fb;
10759 if (!fb) {
10760 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
10761 plane->base.id, plane->name, state->scaler_id);
10762 continue;
10763 }
10764
10765 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
10766 plane->base.id, plane->name,
10767 fb->base.id, fb->width, fb->height,
10768 drm_get_format_name(fb->format->format, &format_name));
10769 if (INTEL_GEN(dev_priv) >= 9)
10770 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
10771 state->scaler_id,
10772 state->base.src.x1 >> 16,
10773 state->base.src.y1 >> 16,
10774 drm_rect_width(&state->base.src) >> 16,
10775 drm_rect_height(&state->base.src) >> 16,
10776 state->base.dst.x1, state->base.dst.y1,
10777 drm_rect_width(&state->base.dst),
10778 drm_rect_height(&state->base.dst));
10779 }
10780 }
10781
10782 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
10783 {
10784 struct drm_device *dev = state->dev;
10785 struct drm_connector *connector;
10786 struct drm_connector_list_iter conn_iter;
10787 unsigned int used_ports = 0;
10788 unsigned int used_mst_ports = 0;
10789
10790 /*
10791 * Walk the connector list instead of the encoder
10792 * list to detect the problem on ddi platforms
10793 * where there's just one encoder per digital port.
10794 */
10795 drm_connector_list_iter_begin(dev, &conn_iter);
10796 drm_for_each_connector_iter(connector, &conn_iter) {
10797 struct drm_connector_state *connector_state;
10798 struct intel_encoder *encoder;
10799
10800 connector_state = drm_atomic_get_existing_connector_state(state, connector);
10801 if (!connector_state)
10802 connector_state = connector->state;
10803
10804 if (!connector_state->best_encoder)
10805 continue;
10806
10807 encoder = to_intel_encoder(connector_state->best_encoder);
10808
10809 WARN_ON(!connector_state->crtc);
10810
10811 switch (encoder->type) {
10812 unsigned int port_mask;
10813 case INTEL_OUTPUT_UNKNOWN:
10814 if (WARN_ON(!HAS_DDI(to_i915(dev))))
10815 break;
10816 case INTEL_OUTPUT_DP:
10817 case INTEL_OUTPUT_HDMI:
10818 case INTEL_OUTPUT_EDP:
10819 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10820
10821 /* the same port mustn't appear more than once */
10822 if (used_ports & port_mask)
10823 return false;
10824
10825 used_ports |= port_mask;
10826 break;
10827 case INTEL_OUTPUT_DP_MST:
10828 used_mst_ports |=
10829 1 << enc_to_mst(&encoder->base)->primary->port;
10830 break;
10831 default:
10832 break;
10833 }
10834 }
10835 drm_connector_list_iter_end(&conn_iter);
10836
10837 /* can't mix MST and SST/HDMI on the same port */
10838 if (used_ports & used_mst_ports)
10839 return false;
10840
10841 return true;
10842 }
10843
10844 static void
10845 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10846 {
10847 struct drm_i915_private *dev_priv =
10848 to_i915(crtc_state->base.crtc->dev);
10849 struct intel_crtc_scaler_state scaler_state;
10850 struct intel_dpll_hw_state dpll_hw_state;
10851 struct intel_shared_dpll *shared_dpll;
10852 struct intel_crtc_wm_state wm_state;
10853 bool force_thru;
10854
10855 /* FIXME: before the switch to atomic started, a new pipe_config was
10856 * kzalloc'd. Code that depends on any field being zero should be
10857 * fixed, so that the crtc_state can be safely duplicated. For now,
10858 * only fields that are know to not cause problems are preserved. */
10859
10860 scaler_state = crtc_state->scaler_state;
10861 shared_dpll = crtc_state->shared_dpll;
10862 dpll_hw_state = crtc_state->dpll_hw_state;
10863 force_thru = crtc_state->pch_pfit.force_thru;
10864 if (IS_G4X(dev_priv) ||
10865 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10866 wm_state = crtc_state->wm;
10867
10868 /* Keep base drm_crtc_state intact, only clear our extended struct */
10869 BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
10870 memset(&crtc_state->base + 1, 0,
10871 sizeof(*crtc_state) - sizeof(crtc_state->base));
10872
10873 crtc_state->scaler_state = scaler_state;
10874 crtc_state->shared_dpll = shared_dpll;
10875 crtc_state->dpll_hw_state = dpll_hw_state;
10876 crtc_state->pch_pfit.force_thru = force_thru;
10877 if (IS_G4X(dev_priv) ||
10878 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10879 crtc_state->wm = wm_state;
10880 }
10881
10882 static int
10883 intel_modeset_pipe_config(struct drm_crtc *crtc,
10884 struct intel_crtc_state *pipe_config)
10885 {
10886 struct drm_atomic_state *state = pipe_config->base.state;
10887 struct intel_encoder *encoder;
10888 struct drm_connector *connector;
10889 struct drm_connector_state *connector_state;
10890 int base_bpp, ret = -EINVAL;
10891 int i;
10892 bool retry = true;
10893
10894 clear_intel_crtc_state(pipe_config);
10895
10896 pipe_config->cpu_transcoder =
10897 (enum transcoder) to_intel_crtc(crtc)->pipe;
10898
10899 /*
10900 * Sanitize sync polarity flags based on requested ones. If neither
10901 * positive or negative polarity is requested, treat this as meaning
10902 * negative polarity.
10903 */
10904 if (!(pipe_config->base.adjusted_mode.flags &
10905 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10906 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10907
10908 if (!(pipe_config->base.adjusted_mode.flags &
10909 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10910 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10911
10912 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10913 pipe_config);
10914 if (base_bpp < 0)
10915 goto fail;
10916
10917 /*
10918 * Determine the real pipe dimensions. Note that stereo modes can
10919 * increase the actual pipe size due to the frame doubling and
10920 * insertion of additional space for blanks between the frame. This
10921 * is stored in the crtc timings. We use the requested mode to do this
10922 * computation to clearly distinguish it from the adjusted mode, which
10923 * can be changed by the connectors in the below retry loop.
10924 */
10925 drm_mode_get_hv_timing(&pipe_config->base.mode,
10926 &pipe_config->pipe_src_w,
10927 &pipe_config->pipe_src_h);
10928
10929 for_each_new_connector_in_state(state, connector, connector_state, i) {
10930 if (connector_state->crtc != crtc)
10931 continue;
10932
10933 encoder = to_intel_encoder(connector_state->best_encoder);
10934
10935 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
10936 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10937 goto fail;
10938 }
10939
10940 /*
10941 * Determine output_types before calling the .compute_config()
10942 * hooks so that the hooks can use this information safely.
10943 */
10944 pipe_config->output_types |= 1 << encoder->type;
10945 }
10946
10947 encoder_retry:
10948 /* Ensure the port clock defaults are reset when retrying. */
10949 pipe_config->port_clock = 0;
10950 pipe_config->pixel_multiplier = 1;
10951
10952 /* Fill in default crtc timings, allow encoders to overwrite them. */
10953 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10954 CRTC_STEREO_DOUBLE);
10955
10956 /* Pass our mode to the connectors and the CRTC to give them a chance to
10957 * adjust it according to limitations or connector properties, and also
10958 * a chance to reject the mode entirely.
10959 */
10960 for_each_new_connector_in_state(state, connector, connector_state, i) {
10961 if (connector_state->crtc != crtc)
10962 continue;
10963
10964 encoder = to_intel_encoder(connector_state->best_encoder);
10965
10966 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
10967 DRM_DEBUG_KMS("Encoder config failure\n");
10968 goto fail;
10969 }
10970 }
10971
10972 /* Set default port clock if not overwritten by the encoder. Needs to be
10973 * done afterwards in case the encoder adjusts the mode. */
10974 if (!pipe_config->port_clock)
10975 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10976 * pipe_config->pixel_multiplier;
10977
10978 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10979 if (ret < 0) {
10980 DRM_DEBUG_KMS("CRTC fixup failed\n");
10981 goto fail;
10982 }
10983
10984 if (ret == RETRY) {
10985 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10986 ret = -EINVAL;
10987 goto fail;
10988 }
10989
10990 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10991 retry = false;
10992 goto encoder_retry;
10993 }
10994
10995 /* Dithering seems to not pass-through bits correctly when it should, so
10996 * only enable it on 6bpc panels and when its not a compliance
10997 * test requesting 6bpc video pattern.
10998 */
10999 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11000 !pipe_config->dither_force_disable;
11001 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11002 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11003
11004 fail:
11005 return ret;
11006 }
11007
11008 static void
11009 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
11010 {
11011 struct drm_crtc *crtc;
11012 struct drm_crtc_state *new_crtc_state;
11013 int i;
11014
11015 /* Double check state. */
11016 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
11017 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
11018
11019 /*
11020 * Update legacy state to satisfy fbc code. This can
11021 * be removed when fbc uses the atomic state.
11022 */
11023 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11024 struct drm_plane_state *plane_state = crtc->primary->state;
11025
11026 crtc->primary->fb = plane_state->fb;
11027 crtc->x = plane_state->src_x >> 16;
11028 crtc->y = plane_state->src_y >> 16;
11029 }
11030 }
11031 }
11032
11033 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11034 {
11035 int diff;
11036
11037 if (clock1 == clock2)
11038 return true;
11039
11040 if (!clock1 || !clock2)
11041 return false;
11042
11043 diff = abs(clock1 - clock2);
11044
11045 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11046 return true;
11047
11048 return false;
11049 }
11050
11051 static bool
11052 intel_compare_m_n(unsigned int m, unsigned int n,
11053 unsigned int m2, unsigned int n2,
11054 bool exact)
11055 {
11056 if (m == m2 && n == n2)
11057 return true;
11058
11059 if (exact || !m || !n || !m2 || !n2)
11060 return false;
11061
11062 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11063
11064 if (n > n2) {
11065 while (n > n2) {
11066 m2 <<= 1;
11067 n2 <<= 1;
11068 }
11069 } else if (n < n2) {
11070 while (n < n2) {
11071 m <<= 1;
11072 n <<= 1;
11073 }
11074 }
11075
11076 if (n != n2)
11077 return false;
11078
11079 return intel_fuzzy_clock_check(m, m2);
11080 }
11081
11082 static bool
11083 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11084 struct intel_link_m_n *m2_n2,
11085 bool adjust)
11086 {
11087 if (m_n->tu == m2_n2->tu &&
11088 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11089 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11090 intel_compare_m_n(m_n->link_m, m_n->link_n,
11091 m2_n2->link_m, m2_n2->link_n, !adjust)) {
11092 if (adjust)
11093 *m2_n2 = *m_n;
11094
11095 return true;
11096 }
11097
11098 return false;
11099 }
11100
11101 static void __printf(3, 4)
11102 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11103 {
11104 char *level;
11105 unsigned int category;
11106 struct va_format vaf;
11107 va_list args;
11108
11109 if (adjust) {
11110 level = KERN_DEBUG;
11111 category = DRM_UT_KMS;
11112 } else {
11113 level = KERN_ERR;
11114 category = DRM_UT_NONE;
11115 }
11116
11117 va_start(args, format);
11118 vaf.fmt = format;
11119 vaf.va = &args;
11120
11121 drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11122
11123 va_end(args);
11124 }
11125
11126 static bool
11127 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11128 struct intel_crtc_state *current_config,
11129 struct intel_crtc_state *pipe_config,
11130 bool adjust)
11131 {
11132 bool ret = true;
11133
11134 #define PIPE_CONF_CHECK_X(name) \
11135 if (current_config->name != pipe_config->name) { \
11136 pipe_config_err(adjust, __stringify(name), \
11137 "(expected 0x%08x, found 0x%08x)\n", \
11138 current_config->name, \
11139 pipe_config->name); \
11140 ret = false; \
11141 }
11142
11143 #define PIPE_CONF_CHECK_I(name) \
11144 if (current_config->name != pipe_config->name) { \
11145 pipe_config_err(adjust, __stringify(name), \
11146 "(expected %i, found %i)\n", \
11147 current_config->name, \
11148 pipe_config->name); \
11149 ret = false; \
11150 }
11151
11152 #define PIPE_CONF_CHECK_P(name) \
11153 if (current_config->name != pipe_config->name) { \
11154 pipe_config_err(adjust, __stringify(name), \
11155 "(expected %p, found %p)\n", \
11156 current_config->name, \
11157 pipe_config->name); \
11158 ret = false; \
11159 }
11160
11161 #define PIPE_CONF_CHECK_M_N(name) \
11162 if (!intel_compare_link_m_n(&current_config->name, \
11163 &pipe_config->name,\
11164 adjust)) { \
11165 pipe_config_err(adjust, __stringify(name), \
11166 "(expected tu %i gmch %i/%i link %i/%i, " \
11167 "found tu %i, gmch %i/%i link %i/%i)\n", \
11168 current_config->name.tu, \
11169 current_config->name.gmch_m, \
11170 current_config->name.gmch_n, \
11171 current_config->name.link_m, \
11172 current_config->name.link_n, \
11173 pipe_config->name.tu, \
11174 pipe_config->name.gmch_m, \
11175 pipe_config->name.gmch_n, \
11176 pipe_config->name.link_m, \
11177 pipe_config->name.link_n); \
11178 ret = false; \
11179 }
11180
11181 /* This is required for BDW+ where there is only one set of registers for
11182 * switching between high and low RR.
11183 * This macro can be used whenever a comparison has to be made between one
11184 * hw state and multiple sw state variables.
11185 */
11186 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11187 if (!intel_compare_link_m_n(&current_config->name, \
11188 &pipe_config->name, adjust) && \
11189 !intel_compare_link_m_n(&current_config->alt_name, \
11190 &pipe_config->name, adjust)) { \
11191 pipe_config_err(adjust, __stringify(name), \
11192 "(expected tu %i gmch %i/%i link %i/%i, " \
11193 "or tu %i gmch %i/%i link %i/%i, " \
11194 "found tu %i, gmch %i/%i link %i/%i)\n", \
11195 current_config->name.tu, \
11196 current_config->name.gmch_m, \
11197 current_config->name.gmch_n, \
11198 current_config->name.link_m, \
11199 current_config->name.link_n, \
11200 current_config->alt_name.tu, \
11201 current_config->alt_name.gmch_m, \
11202 current_config->alt_name.gmch_n, \
11203 current_config->alt_name.link_m, \
11204 current_config->alt_name.link_n, \
11205 pipe_config->name.tu, \
11206 pipe_config->name.gmch_m, \
11207 pipe_config->name.gmch_n, \
11208 pipe_config->name.link_m, \
11209 pipe_config->name.link_n); \
11210 ret = false; \
11211 }
11212
11213 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11214 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11215 pipe_config_err(adjust, __stringify(name), \
11216 "(%x) (expected %i, found %i)\n", \
11217 (mask), \
11218 current_config->name & (mask), \
11219 pipe_config->name & (mask)); \
11220 ret = false; \
11221 }
11222
11223 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11224 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11225 pipe_config_err(adjust, __stringify(name), \
11226 "(expected %i, found %i)\n", \
11227 current_config->name, \
11228 pipe_config->name); \
11229 ret = false; \
11230 }
11231
11232 #define PIPE_CONF_QUIRK(quirk) \
11233 ((current_config->quirks | pipe_config->quirks) & (quirk))
11234
11235 PIPE_CONF_CHECK_I(cpu_transcoder);
11236
11237 PIPE_CONF_CHECK_I(has_pch_encoder);
11238 PIPE_CONF_CHECK_I(fdi_lanes);
11239 PIPE_CONF_CHECK_M_N(fdi_m_n);
11240
11241 PIPE_CONF_CHECK_I(lane_count);
11242 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11243
11244 if (INTEL_GEN(dev_priv) < 8) {
11245 PIPE_CONF_CHECK_M_N(dp_m_n);
11246
11247 if (current_config->has_drrs)
11248 PIPE_CONF_CHECK_M_N(dp_m2_n2);
11249 } else
11250 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11251
11252 PIPE_CONF_CHECK_X(output_types);
11253
11254 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11255 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11256 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11257 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11258 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11259 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11260
11261 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11262 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11263 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11264 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11265 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11266 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11267
11268 PIPE_CONF_CHECK_I(pixel_multiplier);
11269 PIPE_CONF_CHECK_I(has_hdmi_sink);
11270 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11271 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11272 PIPE_CONF_CHECK_I(limited_color_range);
11273
11274 PIPE_CONF_CHECK_I(hdmi_scrambling);
11275 PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio);
11276 PIPE_CONF_CHECK_I(has_infoframe);
11277 PIPE_CONF_CHECK_I(ycbcr420);
11278
11279 PIPE_CONF_CHECK_I(has_audio);
11280
11281 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11282 DRM_MODE_FLAG_INTERLACE);
11283
11284 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11285 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11286 DRM_MODE_FLAG_PHSYNC);
11287 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11288 DRM_MODE_FLAG_NHSYNC);
11289 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11290 DRM_MODE_FLAG_PVSYNC);
11291 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11292 DRM_MODE_FLAG_NVSYNC);
11293 }
11294
11295 PIPE_CONF_CHECK_X(gmch_pfit.control);
11296 /* pfit ratios are autocomputed by the hw on gen4+ */
11297 if (INTEL_GEN(dev_priv) < 4)
11298 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11299 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11300
11301 if (!adjust) {
11302 PIPE_CONF_CHECK_I(pipe_src_w);
11303 PIPE_CONF_CHECK_I(pipe_src_h);
11304
11305 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11306 if (current_config->pch_pfit.enabled) {
11307 PIPE_CONF_CHECK_X(pch_pfit.pos);
11308 PIPE_CONF_CHECK_X(pch_pfit.size);
11309 }
11310
11311 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11312 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11313 }
11314
11315 /* BDW+ don't expose a synchronous way to read the state */
11316 if (IS_HASWELL(dev_priv))
11317 PIPE_CONF_CHECK_I(ips_enabled);
11318
11319 PIPE_CONF_CHECK_I(double_wide);
11320
11321 PIPE_CONF_CHECK_P(shared_dpll);
11322 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11323 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11324 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11325 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11326 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11327 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11328 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11329 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11330 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11331
11332 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11333 PIPE_CONF_CHECK_X(dsi_pll.div);
11334
11335 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11336 PIPE_CONF_CHECK_I(pipe_bpp);
11337
11338 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11339 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11340
11341 #undef PIPE_CONF_CHECK_X
11342 #undef PIPE_CONF_CHECK_I
11343 #undef PIPE_CONF_CHECK_P
11344 #undef PIPE_CONF_CHECK_FLAGS
11345 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11346 #undef PIPE_CONF_QUIRK
11347
11348 return ret;
11349 }
11350
11351 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11352 const struct intel_crtc_state *pipe_config)
11353 {
11354 if (pipe_config->has_pch_encoder) {
11355 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11356 &pipe_config->fdi_m_n);
11357 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11358
11359 /*
11360 * FDI already provided one idea for the dotclock.
11361 * Yell if the encoder disagrees.
11362 */
11363 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11364 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11365 fdi_dotclock, dotclock);
11366 }
11367 }
11368
11369 static void verify_wm_state(struct drm_crtc *crtc,
11370 struct drm_crtc_state *new_state)
11371 {
11372 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11373 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11374 struct skl_pipe_wm hw_wm, *sw_wm;
11375 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11376 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11378 const enum pipe pipe = intel_crtc->pipe;
11379 int plane, level, max_level = ilk_wm_max_level(dev_priv);
11380
11381 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11382 return;
11383
11384 skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11385 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11386
11387 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11388 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11389
11390 /* planes */
11391 for_each_universal_plane(dev_priv, pipe, plane) {
11392 hw_plane_wm = &hw_wm.planes[plane];
11393 sw_plane_wm = &sw_wm->planes[plane];
11394
11395 /* Watermarks */
11396 for (level = 0; level <= max_level; level++) {
11397 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11398 &sw_plane_wm->wm[level]))
11399 continue;
11400
11401 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11402 pipe_name(pipe), plane + 1, level,
11403 sw_plane_wm->wm[level].plane_en,
11404 sw_plane_wm->wm[level].plane_res_b,
11405 sw_plane_wm->wm[level].plane_res_l,
11406 hw_plane_wm->wm[level].plane_en,
11407 hw_plane_wm->wm[level].plane_res_b,
11408 hw_plane_wm->wm[level].plane_res_l);
11409 }
11410
11411 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11412 &sw_plane_wm->trans_wm)) {
11413 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11414 pipe_name(pipe), plane + 1,
11415 sw_plane_wm->trans_wm.plane_en,
11416 sw_plane_wm->trans_wm.plane_res_b,
11417 sw_plane_wm->trans_wm.plane_res_l,
11418 hw_plane_wm->trans_wm.plane_en,
11419 hw_plane_wm->trans_wm.plane_res_b,
11420 hw_plane_wm->trans_wm.plane_res_l);
11421 }
11422
11423 /* DDB */
11424 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11425 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11426
11427 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11428 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11429 pipe_name(pipe), plane + 1,
11430 sw_ddb_entry->start, sw_ddb_entry->end,
11431 hw_ddb_entry->start, hw_ddb_entry->end);
11432 }
11433 }
11434
11435 /*
11436 * cursor
11437 * If the cursor plane isn't active, we may not have updated it's ddb
11438 * allocation. In that case since the ddb allocation will be updated
11439 * once the plane becomes visible, we can skip this check
11440 */
11441 if (1) {
11442 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11443 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11444
11445 /* Watermarks */
11446 for (level = 0; level <= max_level; level++) {
11447 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11448 &sw_plane_wm->wm[level]))
11449 continue;
11450
11451 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11452 pipe_name(pipe), level,
11453 sw_plane_wm->wm[level].plane_en,
11454 sw_plane_wm->wm[level].plane_res_b,
11455 sw_plane_wm->wm[level].plane_res_l,
11456 hw_plane_wm->wm[level].plane_en,
11457 hw_plane_wm->wm[level].plane_res_b,
11458 hw_plane_wm->wm[level].plane_res_l);
11459 }
11460
11461 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11462 &sw_plane_wm->trans_wm)) {
11463 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11464 pipe_name(pipe),
11465 sw_plane_wm->trans_wm.plane_en,
11466 sw_plane_wm->trans_wm.plane_res_b,
11467 sw_plane_wm->trans_wm.plane_res_l,
11468 hw_plane_wm->trans_wm.plane_en,
11469 hw_plane_wm->trans_wm.plane_res_b,
11470 hw_plane_wm->trans_wm.plane_res_l);
11471 }
11472
11473 /* DDB */
11474 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11475 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11476
11477 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11478 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11479 pipe_name(pipe),
11480 sw_ddb_entry->start, sw_ddb_entry->end,
11481 hw_ddb_entry->start, hw_ddb_entry->end);
11482 }
11483 }
11484 }
11485
11486 static void
11487 verify_connector_state(struct drm_device *dev,
11488 struct drm_atomic_state *state,
11489 struct drm_crtc *crtc)
11490 {
11491 struct drm_connector *connector;
11492 struct drm_connector_state *new_conn_state;
11493 int i;
11494
11495 for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11496 struct drm_encoder *encoder = connector->encoder;
11497 struct drm_crtc_state *crtc_state = NULL;
11498
11499 if (new_conn_state->crtc != crtc)
11500 continue;
11501
11502 if (crtc)
11503 crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
11504
11505 intel_connector_verify_state(crtc_state, new_conn_state);
11506
11507 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11508 "connector's atomic encoder doesn't match legacy encoder\n");
11509 }
11510 }
11511
11512 static void
11513 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11514 {
11515 struct intel_encoder *encoder;
11516 struct drm_connector *connector;
11517 struct drm_connector_state *old_conn_state, *new_conn_state;
11518 int i;
11519
11520 for_each_intel_encoder(dev, encoder) {
11521 bool enabled = false, found = false;
11522 enum pipe pipe;
11523
11524 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11525 encoder->base.base.id,
11526 encoder->base.name);
11527
11528 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11529 new_conn_state, i) {
11530 if (old_conn_state->best_encoder == &encoder->base)
11531 found = true;
11532
11533 if (new_conn_state->best_encoder != &encoder->base)
11534 continue;
11535 found = enabled = true;
11536
11537 I915_STATE_WARN(new_conn_state->crtc !=
11538 encoder->base.crtc,
11539 "connector's crtc doesn't match encoder crtc\n");
11540 }
11541
11542 if (!found)
11543 continue;
11544
11545 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11546 "encoder's enabled state mismatch "
11547 "(expected %i, found %i)\n",
11548 !!encoder->base.crtc, enabled);
11549
11550 if (!encoder->base.crtc) {
11551 bool active;
11552
11553 active = encoder->get_hw_state(encoder, &pipe);
11554 I915_STATE_WARN(active,
11555 "encoder detached but still enabled on pipe %c.\n",
11556 pipe_name(pipe));
11557 }
11558 }
11559 }
11560
11561 static void
11562 verify_crtc_state(struct drm_crtc *crtc,
11563 struct drm_crtc_state *old_crtc_state,
11564 struct drm_crtc_state *new_crtc_state)
11565 {
11566 struct drm_device *dev = crtc->dev;
11567 struct drm_i915_private *dev_priv = to_i915(dev);
11568 struct intel_encoder *encoder;
11569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11570 struct intel_crtc_state *pipe_config, *sw_config;
11571 struct drm_atomic_state *old_state;
11572 bool active;
11573
11574 old_state = old_crtc_state->state;
11575 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
11576 pipe_config = to_intel_crtc_state(old_crtc_state);
11577 memset(pipe_config, 0, sizeof(*pipe_config));
11578 pipe_config->base.crtc = crtc;
11579 pipe_config->base.state = old_state;
11580
11581 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
11582
11583 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
11584
11585 /* we keep both pipes enabled on 830 */
11586 if (IS_I830(dev_priv))
11587 active = new_crtc_state->active;
11588
11589 I915_STATE_WARN(new_crtc_state->active != active,
11590 "crtc active state doesn't match with hw state "
11591 "(expected %i, found %i)\n", new_crtc_state->active, active);
11592
11593 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
11594 "transitional active state does not match atomic hw state "
11595 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
11596
11597 for_each_encoder_on_crtc(dev, crtc, encoder) {
11598 enum pipe pipe;
11599
11600 active = encoder->get_hw_state(encoder, &pipe);
11601 I915_STATE_WARN(active != new_crtc_state->active,
11602 "[ENCODER:%i] active %i with crtc active %i\n",
11603 encoder->base.base.id, active, new_crtc_state->active);
11604
11605 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
11606 "Encoder connected to wrong pipe %c\n",
11607 pipe_name(pipe));
11608
11609 if (active) {
11610 pipe_config->output_types |= 1 << encoder->type;
11611 encoder->get_config(encoder, pipe_config);
11612 }
11613 }
11614
11615 intel_crtc_compute_pixel_rate(pipe_config);
11616
11617 if (!new_crtc_state->active)
11618 return;
11619
11620 intel_pipe_config_sanity_check(dev_priv, pipe_config);
11621
11622 sw_config = to_intel_crtc_state(new_crtc_state);
11623 if (!intel_pipe_config_compare(dev_priv, sw_config,
11624 pipe_config, false)) {
11625 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11626 intel_dump_pipe_config(intel_crtc, pipe_config,
11627 "[hw state]");
11628 intel_dump_pipe_config(intel_crtc, sw_config,
11629 "[sw state]");
11630 }
11631 }
11632
11633 static void
11634 verify_single_dpll_state(struct drm_i915_private *dev_priv,
11635 struct intel_shared_dpll *pll,
11636 struct drm_crtc *crtc,
11637 struct drm_crtc_state *new_state)
11638 {
11639 struct intel_dpll_hw_state dpll_hw_state;
11640 unsigned crtc_mask;
11641 bool active;
11642
11643 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11644
11645 DRM_DEBUG_KMS("%s\n", pll->name);
11646
11647 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
11648
11649 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
11650 I915_STATE_WARN(!pll->on && pll->active_mask,
11651 "pll in active use but not on in sw tracking\n");
11652 I915_STATE_WARN(pll->on && !pll->active_mask,
11653 "pll is on but not used by any active crtc\n");
11654 I915_STATE_WARN(pll->on != active,
11655 "pll on state mismatch (expected %i, found %i)\n",
11656 pll->on, active);
11657 }
11658
11659 if (!crtc) {
11660 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
11661 "more active pll users than references: %x vs %x\n",
11662 pll->active_mask, pll->state.crtc_mask);
11663
11664 return;
11665 }
11666
11667 crtc_mask = 1 << drm_crtc_index(crtc);
11668
11669 if (new_state->active)
11670 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
11671 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
11672 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11673 else
11674 I915_STATE_WARN(pll->active_mask & crtc_mask,
11675 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
11676 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11677
11678 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
11679 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
11680 crtc_mask, pll->state.crtc_mask);
11681
11682 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
11683 &dpll_hw_state,
11684 sizeof(dpll_hw_state)),
11685 "pll hw state mismatch\n");
11686 }
11687
11688 static void
11689 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
11690 struct drm_crtc_state *old_crtc_state,
11691 struct drm_crtc_state *new_crtc_state)
11692 {
11693 struct drm_i915_private *dev_priv = to_i915(dev);
11694 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
11695 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
11696
11697 if (new_state->shared_dpll)
11698 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
11699
11700 if (old_state->shared_dpll &&
11701 old_state->shared_dpll != new_state->shared_dpll) {
11702 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
11703 struct intel_shared_dpll *pll = old_state->shared_dpll;
11704
11705 I915_STATE_WARN(pll->active_mask & crtc_mask,
11706 "pll active mismatch (didn't expect pipe %c in active mask)\n",
11707 pipe_name(drm_crtc_index(crtc)));
11708 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
11709 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
11710 pipe_name(drm_crtc_index(crtc)));
11711 }
11712 }
11713
11714 static void
11715 intel_modeset_verify_crtc(struct drm_crtc *crtc,
11716 struct drm_atomic_state *state,
11717 struct drm_crtc_state *old_state,
11718 struct drm_crtc_state *new_state)
11719 {
11720 if (!needs_modeset(new_state) &&
11721 !to_intel_crtc_state(new_state)->update_pipe)
11722 return;
11723
11724 verify_wm_state(crtc, new_state);
11725 verify_connector_state(crtc->dev, state, crtc);
11726 verify_crtc_state(crtc, old_state, new_state);
11727 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
11728 }
11729
11730 static void
11731 verify_disabled_dpll_state(struct drm_device *dev)
11732 {
11733 struct drm_i915_private *dev_priv = to_i915(dev);
11734 int i;
11735
11736 for (i = 0; i < dev_priv->num_shared_dpll; i++)
11737 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
11738 }
11739
11740 static void
11741 intel_modeset_verify_disabled(struct drm_device *dev,
11742 struct drm_atomic_state *state)
11743 {
11744 verify_encoder_state(dev, state);
11745 verify_connector_state(dev, state, NULL);
11746 verify_disabled_dpll_state(dev);
11747 }
11748
11749 static void update_scanline_offset(struct intel_crtc *crtc)
11750 {
11751 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11752
11753 /*
11754 * The scanline counter increments at the leading edge of hsync.
11755 *
11756 * On most platforms it starts counting from vtotal-1 on the
11757 * first active line. That means the scanline counter value is
11758 * always one less than what we would expect. Ie. just after
11759 * start of vblank, which also occurs at start of hsync (on the
11760 * last active line), the scanline counter will read vblank_start-1.
11761 *
11762 * On gen2 the scanline counter starts counting from 1 instead
11763 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11764 * to keep the value positive), instead of adding one.
11765 *
11766 * On HSW+ the behaviour of the scanline counter depends on the output
11767 * type. For DP ports it behaves like most other platforms, but on HDMI
11768 * there's an extra 1 line difference. So we need to add two instead of
11769 * one to the value.
11770 *
11771 * On VLV/CHV DSI the scanline counter would appear to increment
11772 * approx. 1/3 of a scanline before start of vblank. Unfortunately
11773 * that means we can't tell whether we're in vblank or not while
11774 * we're on that particular line. We must still set scanline_offset
11775 * to 1 so that the vblank timestamps come out correct when we query
11776 * the scanline counter from within the vblank interrupt handler.
11777 * However if queried just before the start of vblank we'll get an
11778 * answer that's slightly in the future.
11779 */
11780 if (IS_GEN2(dev_priv)) {
11781 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
11782 int vtotal;
11783
11784 vtotal = adjusted_mode->crtc_vtotal;
11785 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
11786 vtotal /= 2;
11787
11788 crtc->scanline_offset = vtotal - 1;
11789 } else if (HAS_DDI(dev_priv) &&
11790 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
11791 crtc->scanline_offset = 2;
11792 } else
11793 crtc->scanline_offset = 1;
11794 }
11795
11796 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
11797 {
11798 struct drm_device *dev = state->dev;
11799 struct drm_i915_private *dev_priv = to_i915(dev);
11800 struct drm_crtc *crtc;
11801 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11802 int i;
11803
11804 if (!dev_priv->display.crtc_compute_clock)
11805 return;
11806
11807 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11809 struct intel_shared_dpll *old_dpll =
11810 to_intel_crtc_state(old_crtc_state)->shared_dpll;
11811
11812 if (!needs_modeset(new_crtc_state))
11813 continue;
11814
11815 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
11816
11817 if (!old_dpll)
11818 continue;
11819
11820 intel_release_shared_dpll(old_dpll, intel_crtc, state);
11821 }
11822 }
11823
11824 /*
11825 * This implements the workaround described in the "notes" section of the mode
11826 * set sequence documentation. When going from no pipes or single pipe to
11827 * multiple pipes, and planes are enabled after the pipe, we need to wait at
11828 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
11829 */
11830 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
11831 {
11832 struct drm_crtc_state *crtc_state;
11833 struct intel_crtc *intel_crtc;
11834 struct drm_crtc *crtc;
11835 struct intel_crtc_state *first_crtc_state = NULL;
11836 struct intel_crtc_state *other_crtc_state = NULL;
11837 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
11838 int i;
11839
11840 /* look at all crtc's that are going to be enabled in during modeset */
11841 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
11842 intel_crtc = to_intel_crtc(crtc);
11843
11844 if (!crtc_state->active || !needs_modeset(crtc_state))
11845 continue;
11846
11847 if (first_crtc_state) {
11848 other_crtc_state = to_intel_crtc_state(crtc_state);
11849 break;
11850 } else {
11851 first_crtc_state = to_intel_crtc_state(crtc_state);
11852 first_pipe = intel_crtc->pipe;
11853 }
11854 }
11855
11856 /* No workaround needed? */
11857 if (!first_crtc_state)
11858 return 0;
11859
11860 /* w/a possibly needed, check how many crtc's are already enabled. */
11861 for_each_intel_crtc(state->dev, intel_crtc) {
11862 struct intel_crtc_state *pipe_config;
11863
11864 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
11865 if (IS_ERR(pipe_config))
11866 return PTR_ERR(pipe_config);
11867
11868 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
11869
11870 if (!pipe_config->base.active ||
11871 needs_modeset(&pipe_config->base))
11872 continue;
11873
11874 /* 2 or more enabled crtcs means no need for w/a */
11875 if (enabled_pipe != INVALID_PIPE)
11876 return 0;
11877
11878 enabled_pipe = intel_crtc->pipe;
11879 }
11880
11881 if (enabled_pipe != INVALID_PIPE)
11882 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
11883 else if (other_crtc_state)
11884 other_crtc_state->hsw_workaround_pipe = first_pipe;
11885
11886 return 0;
11887 }
11888
11889 static int intel_lock_all_pipes(struct drm_atomic_state *state)
11890 {
11891 struct drm_crtc *crtc;
11892
11893 /* Add all pipes to the state */
11894 for_each_crtc(state->dev, crtc) {
11895 struct drm_crtc_state *crtc_state;
11896
11897 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11898 if (IS_ERR(crtc_state))
11899 return PTR_ERR(crtc_state);
11900 }
11901
11902 return 0;
11903 }
11904
11905 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
11906 {
11907 struct drm_crtc *crtc;
11908
11909 /*
11910 * Add all pipes to the state, and force
11911 * a modeset on all the active ones.
11912 */
11913 for_each_crtc(state->dev, crtc) {
11914 struct drm_crtc_state *crtc_state;
11915 int ret;
11916
11917 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11918 if (IS_ERR(crtc_state))
11919 return PTR_ERR(crtc_state);
11920
11921 if (!crtc_state->active || needs_modeset(crtc_state))
11922 continue;
11923
11924 crtc_state->mode_changed = true;
11925
11926 ret = drm_atomic_add_affected_connectors(state, crtc);
11927 if (ret)
11928 return ret;
11929
11930 ret = drm_atomic_add_affected_planes(state, crtc);
11931 if (ret)
11932 return ret;
11933 }
11934
11935 return 0;
11936 }
11937
11938 static int intel_modeset_checks(struct drm_atomic_state *state)
11939 {
11940 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
11941 struct drm_i915_private *dev_priv = to_i915(state->dev);
11942 struct drm_crtc *crtc;
11943 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11944 int ret = 0, i;
11945
11946 if (!check_digital_port_conflicts(state)) {
11947 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11948 return -EINVAL;
11949 }
11950
11951 intel_state->modeset = true;
11952 intel_state->active_crtcs = dev_priv->active_crtcs;
11953 intel_state->cdclk.logical = dev_priv->cdclk.logical;
11954 intel_state->cdclk.actual = dev_priv->cdclk.actual;
11955
11956 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11957 if (new_crtc_state->active)
11958 intel_state->active_crtcs |= 1 << i;
11959 else
11960 intel_state->active_crtcs &= ~(1 << i);
11961
11962 if (old_crtc_state->active != new_crtc_state->active)
11963 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
11964 }
11965
11966 /*
11967 * See if the config requires any additional preparation, e.g.
11968 * to adjust global state with pipes off. We need to do this
11969 * here so we can get the modeset_pipe updated config for the new
11970 * mode set on this crtc. For other crtcs we need to use the
11971 * adjusted_mode bits in the crtc directly.
11972 */
11973 if (dev_priv->display.modeset_calc_cdclk) {
11974 ret = dev_priv->display.modeset_calc_cdclk(state);
11975 if (ret < 0)
11976 return ret;
11977
11978 /*
11979 * Writes to dev_priv->cdclk.logical must protected by
11980 * holding all the crtc locks, even if we don't end up
11981 * touching the hardware
11982 */
11983 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
11984 &intel_state->cdclk.logical)) {
11985 ret = intel_lock_all_pipes(state);
11986 if (ret < 0)
11987 return ret;
11988 }
11989
11990 /* All pipes must be switched off while we change the cdclk. */
11991 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
11992 &intel_state->cdclk.actual)) {
11993 ret = intel_modeset_all_pipes(state);
11994 if (ret < 0)
11995 return ret;
11996 }
11997
11998 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
11999 intel_state->cdclk.logical.cdclk,
12000 intel_state->cdclk.actual.cdclk);
12001 } else {
12002 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12003 }
12004
12005 intel_modeset_clear_plls(state);
12006
12007 if (IS_HASWELL(dev_priv))
12008 return haswell_mode_set_planes_workaround(state);
12009
12010 return 0;
12011 }
12012
12013 /*
12014 * Handle calculation of various watermark data at the end of the atomic check
12015 * phase. The code here should be run after the per-crtc and per-plane 'check'
12016 * handlers to ensure that all derived state has been updated.
12017 */
12018 static int calc_watermark_data(struct drm_atomic_state *state)
12019 {
12020 struct drm_device *dev = state->dev;
12021 struct drm_i915_private *dev_priv = to_i915(dev);
12022
12023 /* Is there platform-specific watermark information to calculate? */
12024 if (dev_priv->display.compute_global_watermarks)
12025 return dev_priv->display.compute_global_watermarks(state);
12026
12027 return 0;
12028 }
12029
12030 /**
12031 * intel_atomic_check - validate state object
12032 * @dev: drm device
12033 * @state: state to validate
12034 */
12035 static int intel_atomic_check(struct drm_device *dev,
12036 struct drm_atomic_state *state)
12037 {
12038 struct drm_i915_private *dev_priv = to_i915(dev);
12039 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12040 struct drm_crtc *crtc;
12041 struct drm_crtc_state *old_crtc_state, *crtc_state;
12042 int ret, i;
12043 bool any_ms = false;
12044
12045 ret = drm_atomic_helper_check_modeset(dev, state);
12046 if (ret)
12047 return ret;
12048
12049 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12050 struct intel_crtc_state *pipe_config =
12051 to_intel_crtc_state(crtc_state);
12052
12053 /* Catch I915_MODE_FLAG_INHERITED */
12054 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
12055 crtc_state->mode_changed = true;
12056
12057 if (!needs_modeset(crtc_state))
12058 continue;
12059
12060 if (!crtc_state->enable) {
12061 any_ms = true;
12062 continue;
12063 }
12064
12065 /* FIXME: For only active_changed we shouldn't need to do any
12066 * state recomputation at all. */
12067
12068 ret = drm_atomic_add_affected_connectors(state, crtc);
12069 if (ret)
12070 return ret;
12071
12072 ret = intel_modeset_pipe_config(crtc, pipe_config);
12073 if (ret) {
12074 intel_dump_pipe_config(to_intel_crtc(crtc),
12075 pipe_config, "[failed]");
12076 return ret;
12077 }
12078
12079 if (i915.fastboot &&
12080 intel_pipe_config_compare(dev_priv,
12081 to_intel_crtc_state(old_crtc_state),
12082 pipe_config, true)) {
12083 crtc_state->mode_changed = false;
12084 pipe_config->update_pipe = true;
12085 }
12086
12087 if (needs_modeset(crtc_state))
12088 any_ms = true;
12089
12090 ret = drm_atomic_add_affected_planes(state, crtc);
12091 if (ret)
12092 return ret;
12093
12094 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12095 needs_modeset(crtc_state) ?
12096 "[modeset]" : "[fastset]");
12097 }
12098
12099 if (any_ms) {
12100 ret = intel_modeset_checks(state);
12101
12102 if (ret)
12103 return ret;
12104 } else {
12105 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12106 }
12107
12108 ret = drm_atomic_helper_check_planes(dev, state);
12109 if (ret)
12110 return ret;
12111
12112 intel_fbc_choose_crtc(dev_priv, state);
12113 return calc_watermark_data(state);
12114 }
12115
12116 static int intel_atomic_prepare_commit(struct drm_device *dev,
12117 struct drm_atomic_state *state)
12118 {
12119 return drm_atomic_helper_prepare_planes(dev, state);
12120 }
12121
12122 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12123 {
12124 struct drm_device *dev = crtc->base.dev;
12125
12126 if (!dev->max_vblank_count)
12127 return drm_crtc_accurate_vblank_count(&crtc->base);
12128
12129 return dev->driver->get_vblank_counter(dev, crtc->pipe);
12130 }
12131
12132 static void intel_update_crtc(struct drm_crtc *crtc,
12133 struct drm_atomic_state *state,
12134 struct drm_crtc_state *old_crtc_state,
12135 struct drm_crtc_state *new_crtc_state)
12136 {
12137 struct drm_device *dev = crtc->dev;
12138 struct drm_i915_private *dev_priv = to_i915(dev);
12139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12140 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12141 bool modeset = needs_modeset(new_crtc_state);
12142
12143 if (modeset) {
12144 update_scanline_offset(intel_crtc);
12145 dev_priv->display.crtc_enable(pipe_config, state);
12146 } else {
12147 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12148 pipe_config);
12149 }
12150
12151 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12152 intel_fbc_enable(
12153 intel_crtc, pipe_config,
12154 to_intel_plane_state(crtc->primary->state));
12155 }
12156
12157 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12158 }
12159
12160 static void intel_update_crtcs(struct drm_atomic_state *state)
12161 {
12162 struct drm_crtc *crtc;
12163 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12164 int i;
12165
12166 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12167 if (!new_crtc_state->active)
12168 continue;
12169
12170 intel_update_crtc(crtc, state, old_crtc_state,
12171 new_crtc_state);
12172 }
12173 }
12174
12175 static void skl_update_crtcs(struct drm_atomic_state *state)
12176 {
12177 struct drm_i915_private *dev_priv = to_i915(state->dev);
12178 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12179 struct drm_crtc *crtc;
12180 struct intel_crtc *intel_crtc;
12181 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12182 struct intel_crtc_state *cstate;
12183 unsigned int updated = 0;
12184 bool progress;
12185 enum pipe pipe;
12186 int i;
12187
12188 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12189
12190 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12191 /* ignore allocations for crtc's that have been turned off. */
12192 if (new_crtc_state->active)
12193 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12194
12195 /*
12196 * Whenever the number of active pipes changes, we need to make sure we
12197 * update the pipes in the right order so that their ddb allocations
12198 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12199 * cause pipe underruns and other bad stuff.
12200 */
12201 do {
12202 progress = false;
12203
12204 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12205 bool vbl_wait = false;
12206 unsigned int cmask = drm_crtc_mask(crtc);
12207
12208 intel_crtc = to_intel_crtc(crtc);
12209 cstate = to_intel_crtc_state(crtc->state);
12210 pipe = intel_crtc->pipe;
12211
12212 if (updated & cmask || !cstate->base.active)
12213 continue;
12214
12215 if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
12216 continue;
12217
12218 updated |= cmask;
12219 entries[i] = &cstate->wm.skl.ddb;
12220
12221 /*
12222 * If this is an already active pipe, it's DDB changed,
12223 * and this isn't the last pipe that needs updating
12224 * then we need to wait for a vblank to pass for the
12225 * new ddb allocation to take effect.
12226 */
12227 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12228 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12229 !new_crtc_state->active_changed &&
12230 intel_state->wm_results.dirty_pipes != updated)
12231 vbl_wait = true;
12232
12233 intel_update_crtc(crtc, state, old_crtc_state,
12234 new_crtc_state);
12235
12236 if (vbl_wait)
12237 intel_wait_for_vblank(dev_priv, pipe);
12238
12239 progress = true;
12240 }
12241 } while (progress);
12242 }
12243
12244 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12245 {
12246 struct intel_atomic_state *state, *next;
12247 struct llist_node *freed;
12248
12249 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12250 llist_for_each_entry_safe(state, next, freed, freed)
12251 drm_atomic_state_put(&state->base);
12252 }
12253
12254 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12255 {
12256 struct drm_i915_private *dev_priv =
12257 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12258
12259 intel_atomic_helper_free_state(dev_priv);
12260 }
12261
12262 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
12263 {
12264 struct wait_queue_entry wait_fence, wait_reset;
12265 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
12266
12267 init_wait_entry(&wait_fence, 0);
12268 init_wait_entry(&wait_reset, 0);
12269 for (;;) {
12270 prepare_to_wait(&intel_state->commit_ready.wait,
12271 &wait_fence, TASK_UNINTERRUPTIBLE);
12272 prepare_to_wait(&dev_priv->gpu_error.wait_queue,
12273 &wait_reset, TASK_UNINTERRUPTIBLE);
12274
12275
12276 if (i915_sw_fence_done(&intel_state->commit_ready)
12277 || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
12278 break;
12279
12280 schedule();
12281 }
12282 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
12283 finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset);
12284 }
12285
12286 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12287 {
12288 struct drm_device *dev = state->dev;
12289 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12290 struct drm_i915_private *dev_priv = to_i915(dev);
12291 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12292 struct drm_crtc *crtc;
12293 struct intel_crtc_state *intel_cstate;
12294 bool hw_check = intel_state->modeset;
12295 u64 put_domains[I915_MAX_PIPES] = {};
12296 int i;
12297
12298 intel_atomic_commit_fence_wait(intel_state);
12299
12300 drm_atomic_helper_wait_for_dependencies(state);
12301
12302 if (intel_state->modeset)
12303 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12304
12305 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12307
12308 if (needs_modeset(new_crtc_state) ||
12309 to_intel_crtc_state(new_crtc_state)->update_pipe) {
12310 hw_check = true;
12311
12312 put_domains[to_intel_crtc(crtc)->pipe] =
12313 modeset_get_crtc_power_domains(crtc,
12314 to_intel_crtc_state(new_crtc_state));
12315 }
12316
12317 if (!needs_modeset(new_crtc_state))
12318 continue;
12319
12320 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12321 to_intel_crtc_state(new_crtc_state));
12322
12323 if (old_crtc_state->active) {
12324 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12325 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12326 intel_crtc->active = false;
12327 intel_fbc_disable(intel_crtc);
12328 intel_disable_shared_dpll(intel_crtc);
12329
12330 /*
12331 * Underruns don't always raise
12332 * interrupts, so check manually.
12333 */
12334 intel_check_cpu_fifo_underruns(dev_priv);
12335 intel_check_pch_fifo_underruns(dev_priv);
12336
12337 if (!crtc->state->active) {
12338 /*
12339 * Make sure we don't call initial_watermarks
12340 * for ILK-style watermark updates.
12341 *
12342 * No clue what this is supposed to achieve.
12343 */
12344 if (INTEL_GEN(dev_priv) >= 9)
12345 dev_priv->display.initial_watermarks(intel_state,
12346 to_intel_crtc_state(crtc->state));
12347 }
12348 }
12349 }
12350
12351 /* Only after disabling all output pipelines that will be changed can we
12352 * update the the output configuration. */
12353 intel_modeset_update_crtc_state(state);
12354
12355 if (intel_state->modeset) {
12356 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12357
12358 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12359
12360 /*
12361 * SKL workaround: bspec recommends we disable the SAGV when we
12362 * have more then one pipe enabled
12363 */
12364 if (!intel_can_enable_sagv(state))
12365 intel_disable_sagv(dev_priv);
12366
12367 intel_modeset_verify_disabled(dev, state);
12368 }
12369
12370 /* Complete the events for pipes that have now been disabled */
12371 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12372 bool modeset = needs_modeset(new_crtc_state);
12373
12374 /* Complete events for now disable pipes here. */
12375 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12376 spin_lock_irq(&dev->event_lock);
12377 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12378 spin_unlock_irq(&dev->event_lock);
12379
12380 new_crtc_state->event = NULL;
12381 }
12382 }
12383
12384 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12385 dev_priv->display.update_crtcs(state);
12386
12387 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12388 * already, but still need the state for the delayed optimization. To
12389 * fix this:
12390 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12391 * - schedule that vblank worker _before_ calling hw_done
12392 * - at the start of commit_tail, cancel it _synchrously
12393 * - switch over to the vblank wait helper in the core after that since
12394 * we don't need out special handling any more.
12395 */
12396 drm_atomic_helper_wait_for_flip_done(dev, state);
12397
12398 /*
12399 * Now that the vblank has passed, we can go ahead and program the
12400 * optimal watermarks on platforms that need two-step watermark
12401 * programming.
12402 *
12403 * TODO: Move this (and other cleanup) to an async worker eventually.
12404 */
12405 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12406 intel_cstate = to_intel_crtc_state(new_crtc_state);
12407
12408 if (dev_priv->display.optimize_watermarks)
12409 dev_priv->display.optimize_watermarks(intel_state,
12410 intel_cstate);
12411 }
12412
12413 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12414 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12415
12416 if (put_domains[i])
12417 modeset_put_power_domains(dev_priv, put_domains[i]);
12418
12419 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12420 }
12421
12422 if (intel_state->modeset && intel_can_enable_sagv(state))
12423 intel_enable_sagv(dev_priv);
12424
12425 drm_atomic_helper_commit_hw_done(state);
12426
12427 if (intel_state->modeset) {
12428 /* As one of the primary mmio accessors, KMS has a high
12429 * likelihood of triggering bugs in unclaimed access. After we
12430 * finish modesetting, see if an error has been flagged, and if
12431 * so enable debugging for the next modeset - and hope we catch
12432 * the culprit.
12433 */
12434 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12435 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12436 }
12437
12438 drm_atomic_helper_cleanup_planes(dev, state);
12439
12440 drm_atomic_helper_commit_cleanup_done(state);
12441
12442 drm_atomic_state_put(state);
12443
12444 intel_atomic_helper_free_state(dev_priv);
12445 }
12446
12447 static void intel_atomic_commit_work(struct work_struct *work)
12448 {
12449 struct drm_atomic_state *state =
12450 container_of(work, struct drm_atomic_state, commit_work);
12451
12452 intel_atomic_commit_tail(state);
12453 }
12454
12455 static int __i915_sw_fence_call
12456 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12457 enum i915_sw_fence_notify notify)
12458 {
12459 struct intel_atomic_state *state =
12460 container_of(fence, struct intel_atomic_state, commit_ready);
12461
12462 switch (notify) {
12463 case FENCE_COMPLETE:
12464 /* we do blocking waits in the worker, nothing to do here */
12465 break;
12466 case FENCE_FREE:
12467 {
12468 struct intel_atomic_helper *helper =
12469 &to_i915(state->base.dev)->atomic_helper;
12470
12471 if (llist_add(&state->freed, &helper->free_list))
12472 schedule_work(&helper->free_work);
12473 break;
12474 }
12475 }
12476
12477 return NOTIFY_DONE;
12478 }
12479
12480 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12481 {
12482 struct drm_plane_state *old_plane_state, *new_plane_state;
12483 struct drm_plane *plane;
12484 int i;
12485
12486 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
12487 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
12488 intel_fb_obj(new_plane_state->fb),
12489 to_intel_plane(plane)->frontbuffer_bit);
12490 }
12491
12492 /**
12493 * intel_atomic_commit - commit validated state object
12494 * @dev: DRM device
12495 * @state: the top-level driver state object
12496 * @nonblock: nonblocking commit
12497 *
12498 * This function commits a top-level state object that has been validated
12499 * with drm_atomic_helper_check().
12500 *
12501 * RETURNS
12502 * Zero for success or -errno.
12503 */
12504 static int intel_atomic_commit(struct drm_device *dev,
12505 struct drm_atomic_state *state,
12506 bool nonblock)
12507 {
12508 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12509 struct drm_i915_private *dev_priv = to_i915(dev);
12510 int ret = 0;
12511
12512 ret = drm_atomic_helper_setup_commit(state, nonblock);
12513 if (ret)
12514 return ret;
12515
12516 drm_atomic_state_get(state);
12517 i915_sw_fence_init(&intel_state->commit_ready,
12518 intel_atomic_commit_ready);
12519
12520 ret = intel_atomic_prepare_commit(dev, state);
12521 if (ret) {
12522 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
12523 i915_sw_fence_commit(&intel_state->commit_ready);
12524 return ret;
12525 }
12526
12527 /*
12528 * The intel_legacy_cursor_update() fast path takes care
12529 * of avoiding the vblank waits for simple cursor
12530 * movement and flips. For cursor on/off and size changes,
12531 * we want to perform the vblank waits so that watermark
12532 * updates happen during the correct frames. Gen9+ have
12533 * double buffered watermarks and so shouldn't need this.
12534 *
12535 * Do this after drm_atomic_helper_setup_commit() and
12536 * intel_atomic_prepare_commit() because we still want
12537 * to skip the flip and fb cleanup waits. Although that
12538 * does risk yanking the mapping from under the display
12539 * engine.
12540 *
12541 * FIXME doing watermarks and fb cleanup from a vblank worker
12542 * (assuming we had any) would solve these problems.
12543 */
12544 if (INTEL_GEN(dev_priv) < 9)
12545 state->legacy_cursor_update = false;
12546
12547 ret = drm_atomic_helper_swap_state(state, true);
12548 if (ret) {
12549 i915_sw_fence_commit(&intel_state->commit_ready);
12550
12551 drm_atomic_helper_cleanup_planes(dev, state);
12552 return ret;
12553 }
12554 dev_priv->wm.distrust_bios_wm = false;
12555 intel_shared_dpll_swap_state(state);
12556 intel_atomic_track_fbs(state);
12557
12558 if (intel_state->modeset) {
12559 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
12560 sizeof(intel_state->min_pixclk));
12561 dev_priv->active_crtcs = intel_state->active_crtcs;
12562 dev_priv->cdclk.logical = intel_state->cdclk.logical;
12563 dev_priv->cdclk.actual = intel_state->cdclk.actual;
12564 }
12565
12566 drm_atomic_state_get(state);
12567 INIT_WORK(&state->commit_work, intel_atomic_commit_work);
12568
12569 i915_sw_fence_commit(&intel_state->commit_ready);
12570 if (nonblock)
12571 queue_work(system_unbound_wq, &state->commit_work);
12572 else
12573 intel_atomic_commit_tail(state);
12574
12575
12576 return 0;
12577 }
12578
12579 static const struct drm_crtc_funcs intel_crtc_funcs = {
12580 .gamma_set = drm_atomic_helper_legacy_gamma_set,
12581 .set_config = drm_atomic_helper_set_config,
12582 .destroy = intel_crtc_destroy,
12583 .page_flip = drm_atomic_helper_page_flip,
12584 .atomic_duplicate_state = intel_crtc_duplicate_state,
12585 .atomic_destroy_state = intel_crtc_destroy_state,
12586 .set_crc_source = intel_crtc_set_crc_source,
12587 };
12588
12589 /**
12590 * intel_prepare_plane_fb - Prepare fb for usage on plane
12591 * @plane: drm plane to prepare for
12592 * @fb: framebuffer to prepare for presentation
12593 *
12594 * Prepares a framebuffer for usage on a display plane. Generally this
12595 * involves pinning the underlying object and updating the frontbuffer tracking
12596 * bits. Some older platforms need special physical address handling for
12597 * cursor planes.
12598 *
12599 * Must be called with struct_mutex held.
12600 *
12601 * Returns 0 on success, negative error code on failure.
12602 */
12603 int
12604 intel_prepare_plane_fb(struct drm_plane *plane,
12605 struct drm_plane_state *new_state)
12606 {
12607 struct intel_atomic_state *intel_state =
12608 to_intel_atomic_state(new_state->state);
12609 struct drm_i915_private *dev_priv = to_i915(plane->dev);
12610 struct drm_framebuffer *fb = new_state->fb;
12611 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12612 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
12613 int ret;
12614
12615 if (old_obj) {
12616 struct drm_crtc_state *crtc_state =
12617 drm_atomic_get_existing_crtc_state(new_state->state,
12618 plane->state->crtc);
12619
12620 /* Big Hammer, we also need to ensure that any pending
12621 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
12622 * current scanout is retired before unpinning the old
12623 * framebuffer. Note that we rely on userspace rendering
12624 * into the buffer attached to the pipe they are waiting
12625 * on. If not, userspace generates a GPU hang with IPEHR
12626 * point to the MI_WAIT_FOR_EVENT.
12627 *
12628 * This should only fail upon a hung GPU, in which case we
12629 * can safely continue.
12630 */
12631 if (needs_modeset(crtc_state)) {
12632 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12633 old_obj->resv, NULL,
12634 false, 0,
12635 GFP_KERNEL);
12636 if (ret < 0)
12637 return ret;
12638 }
12639 }
12640
12641 if (new_state->fence) { /* explicit fencing */
12642 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
12643 new_state->fence,
12644 I915_FENCE_TIMEOUT,
12645 GFP_KERNEL);
12646 if (ret < 0)
12647 return ret;
12648 }
12649
12650 if (!obj)
12651 return 0;
12652
12653 ret = i915_gem_object_pin_pages(obj);
12654 if (ret)
12655 return ret;
12656
12657 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
12658 if (ret) {
12659 i915_gem_object_unpin_pages(obj);
12660 return ret;
12661 }
12662
12663 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12664 INTEL_INFO(dev_priv)->cursor_needs_physical) {
12665 const int align = intel_cursor_alignment(dev_priv);
12666
12667 ret = i915_gem_object_attach_phys(obj, align);
12668 } else {
12669 struct i915_vma *vma;
12670
12671 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
12672 if (!IS_ERR(vma))
12673 to_intel_plane_state(new_state)->vma = vma;
12674 else
12675 ret = PTR_ERR(vma);
12676 }
12677
12678 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
12679
12680 mutex_unlock(&dev_priv->drm.struct_mutex);
12681 i915_gem_object_unpin_pages(obj);
12682 if (ret)
12683 return ret;
12684
12685 if (!new_state->fence) { /* implicit fencing */
12686 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12687 obj->resv, NULL,
12688 false, I915_FENCE_TIMEOUT,
12689 GFP_KERNEL);
12690 if (ret < 0)
12691 return ret;
12692 }
12693
12694 return 0;
12695 }
12696
12697 /**
12698 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12699 * @plane: drm plane to clean up for
12700 * @fb: old framebuffer that was on plane
12701 *
12702 * Cleans up a framebuffer that has just been removed from a plane.
12703 *
12704 * Must be called with struct_mutex held.
12705 */
12706 void
12707 intel_cleanup_plane_fb(struct drm_plane *plane,
12708 struct drm_plane_state *old_state)
12709 {
12710 struct i915_vma *vma;
12711
12712 /* Should only be called after a successful intel_prepare_plane_fb()! */
12713 vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
12714 if (vma) {
12715 mutex_lock(&plane->dev->struct_mutex);
12716 intel_unpin_fb_vma(vma);
12717 mutex_unlock(&plane->dev->struct_mutex);
12718 }
12719 }
12720
12721 int
12722 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
12723 {
12724 struct drm_i915_private *dev_priv;
12725 int max_scale;
12726 int crtc_clock, max_dotclk;
12727
12728 if (!intel_crtc || !crtc_state->base.enable)
12729 return DRM_PLANE_HELPER_NO_SCALING;
12730
12731 dev_priv = to_i915(intel_crtc->base.dev);
12732
12733 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
12734 max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
12735
12736 if (IS_GEMINILAKE(dev_priv))
12737 max_dotclk *= 2;
12738
12739 if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
12740 return DRM_PLANE_HELPER_NO_SCALING;
12741
12742 /*
12743 * skl max scale is lower of:
12744 * close to 3 but not 3, -1 is for that purpose
12745 * or
12746 * cdclk/crtc_clock
12747 */
12748 max_scale = min((1 << 16) * 3 - 1,
12749 (1 << 8) * ((max_dotclk << 8) / crtc_clock));
12750
12751 return max_scale;
12752 }
12753
12754 static int
12755 intel_check_primary_plane(struct intel_plane *plane,
12756 struct intel_crtc_state *crtc_state,
12757 struct intel_plane_state *state)
12758 {
12759 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
12760 struct drm_crtc *crtc = state->base.crtc;
12761 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
12762 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
12763 bool can_position = false;
12764 int ret;
12765
12766 if (INTEL_GEN(dev_priv) >= 9) {
12767 /* use scaler when colorkey is not required */
12768 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
12769 min_scale = 1;
12770 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
12771 }
12772 can_position = true;
12773 }
12774
12775 ret = drm_plane_helper_check_state(&state->base,
12776 &state->clip,
12777 min_scale, max_scale,
12778 can_position, true);
12779 if (ret)
12780 return ret;
12781
12782 if (!state->base.fb)
12783 return 0;
12784
12785 if (INTEL_GEN(dev_priv) >= 9) {
12786 ret = skl_check_plane_surface(state);
12787 if (ret)
12788 return ret;
12789
12790 state->ctl = skl_plane_ctl(crtc_state, state);
12791 } else {
12792 ret = i9xx_check_plane_surface(state);
12793 if (ret)
12794 return ret;
12795
12796 state->ctl = i9xx_plane_ctl(crtc_state, state);
12797 }
12798
12799 return 0;
12800 }
12801
12802 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
12803 struct drm_crtc_state *old_crtc_state)
12804 {
12805 struct drm_device *dev = crtc->dev;
12806 struct drm_i915_private *dev_priv = to_i915(dev);
12807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12808 struct intel_crtc_state *intel_cstate =
12809 to_intel_crtc_state(crtc->state);
12810 struct intel_crtc_state *old_intel_cstate =
12811 to_intel_crtc_state(old_crtc_state);
12812 struct intel_atomic_state *old_intel_state =
12813 to_intel_atomic_state(old_crtc_state->state);
12814 bool modeset = needs_modeset(crtc->state);
12815
12816 if (!modeset &&
12817 (intel_cstate->base.color_mgmt_changed ||
12818 intel_cstate->update_pipe)) {
12819 intel_color_set_csc(crtc->state);
12820 intel_color_load_luts(crtc->state);
12821 }
12822
12823 /* Perform vblank evasion around commit operation */
12824 intel_pipe_update_start(intel_crtc);
12825
12826 if (modeset)
12827 goto out;
12828
12829 if (intel_cstate->update_pipe)
12830 intel_update_pipe_config(intel_crtc, old_intel_cstate);
12831 else if (INTEL_GEN(dev_priv) >= 9)
12832 skl_detach_scalers(intel_crtc);
12833
12834 out:
12835 if (dev_priv->display.atomic_update_watermarks)
12836 dev_priv->display.atomic_update_watermarks(old_intel_state,
12837 intel_cstate);
12838 }
12839
12840 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
12841 struct drm_crtc_state *old_crtc_state)
12842 {
12843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12844
12845 intel_pipe_update_end(intel_crtc);
12846 }
12847
12848 /**
12849 * intel_plane_destroy - destroy a plane
12850 * @plane: plane to destroy
12851 *
12852 * Common destruction function for all types of planes (primary, cursor,
12853 * sprite).
12854 */
12855 void intel_plane_destroy(struct drm_plane *plane)
12856 {
12857 drm_plane_cleanup(plane);
12858 kfree(to_intel_plane(plane));
12859 }
12860
12861 static bool i8xx_mod_supported(uint32_t format, uint64_t modifier)
12862 {
12863 switch (format) {
12864 case DRM_FORMAT_C8:
12865 case DRM_FORMAT_RGB565:
12866 case DRM_FORMAT_XRGB1555:
12867 case DRM_FORMAT_XRGB8888:
12868 return modifier == DRM_FORMAT_MOD_LINEAR ||
12869 modifier == I915_FORMAT_MOD_X_TILED;
12870 default:
12871 return false;
12872 }
12873 }
12874
12875 static bool i965_mod_supported(uint32_t format, uint64_t modifier)
12876 {
12877 switch (format) {
12878 case DRM_FORMAT_C8:
12879 case DRM_FORMAT_RGB565:
12880 case DRM_FORMAT_XRGB8888:
12881 case DRM_FORMAT_XBGR8888:
12882 case DRM_FORMAT_XRGB2101010:
12883 case DRM_FORMAT_XBGR2101010:
12884 return modifier == DRM_FORMAT_MOD_LINEAR ||
12885 modifier == I915_FORMAT_MOD_X_TILED;
12886 default:
12887 return false;
12888 }
12889 }
12890
12891 static bool skl_mod_supported(uint32_t format, uint64_t modifier)
12892 {
12893 switch (format) {
12894 case DRM_FORMAT_XRGB8888:
12895 case DRM_FORMAT_XBGR8888:
12896 case DRM_FORMAT_ARGB8888:
12897 case DRM_FORMAT_ABGR8888:
12898 if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
12899 modifier == I915_FORMAT_MOD_Y_TILED_CCS)
12900 return true;
12901 /* fall through */
12902 case DRM_FORMAT_RGB565:
12903 case DRM_FORMAT_XRGB2101010:
12904 case DRM_FORMAT_XBGR2101010:
12905 case DRM_FORMAT_YUYV:
12906 case DRM_FORMAT_YVYU:
12907 case DRM_FORMAT_UYVY:
12908 case DRM_FORMAT_VYUY:
12909 if (modifier == I915_FORMAT_MOD_Yf_TILED)
12910 return true;
12911 /* fall through */
12912 case DRM_FORMAT_C8:
12913 if (modifier == DRM_FORMAT_MOD_LINEAR ||
12914 modifier == I915_FORMAT_MOD_X_TILED ||
12915 modifier == I915_FORMAT_MOD_Y_TILED)
12916 return true;
12917 /* fall through */
12918 default:
12919 return false;
12920 }
12921 }
12922
12923 static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane,
12924 uint32_t format,
12925 uint64_t modifier)
12926 {
12927 struct drm_i915_private *dev_priv = to_i915(plane->dev);
12928
12929 if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
12930 return false;
12931
12932 if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL &&
12933 modifier != DRM_FORMAT_MOD_LINEAR)
12934 return false;
12935
12936 if (INTEL_GEN(dev_priv) >= 9)
12937 return skl_mod_supported(format, modifier);
12938 else if (INTEL_GEN(dev_priv) >= 4)
12939 return i965_mod_supported(format, modifier);
12940 else
12941 return i8xx_mod_supported(format, modifier);
12942
12943 unreachable();
12944 }
12945
12946 static bool intel_cursor_plane_format_mod_supported(struct drm_plane *plane,
12947 uint32_t format,
12948 uint64_t modifier)
12949 {
12950 if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
12951 return false;
12952
12953 return modifier == DRM_FORMAT_MOD_LINEAR && format == DRM_FORMAT_ARGB8888;
12954 }
12955
12956 static struct drm_plane_funcs intel_plane_funcs = {
12957 .update_plane = drm_atomic_helper_update_plane,
12958 .disable_plane = drm_atomic_helper_disable_plane,
12959 .destroy = intel_plane_destroy,
12960 .atomic_get_property = intel_plane_atomic_get_property,
12961 .atomic_set_property = intel_plane_atomic_set_property,
12962 .atomic_duplicate_state = intel_plane_duplicate_state,
12963 .atomic_destroy_state = intel_plane_destroy_state,
12964 .format_mod_supported = intel_primary_plane_format_mod_supported,
12965 };
12966
12967 static int
12968 intel_legacy_cursor_update(struct drm_plane *plane,
12969 struct drm_crtc *crtc,
12970 struct drm_framebuffer *fb,
12971 int crtc_x, int crtc_y,
12972 unsigned int crtc_w, unsigned int crtc_h,
12973 uint32_t src_x, uint32_t src_y,
12974 uint32_t src_w, uint32_t src_h,
12975 struct drm_modeset_acquire_ctx *ctx)
12976 {
12977 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
12978 int ret;
12979 struct drm_plane_state *old_plane_state, *new_plane_state;
12980 struct intel_plane *intel_plane = to_intel_plane(plane);
12981 struct drm_framebuffer *old_fb;
12982 struct drm_crtc_state *crtc_state = crtc->state;
12983 struct i915_vma *old_vma, *vma;
12984
12985 /*
12986 * When crtc is inactive or there is a modeset pending,
12987 * wait for it to complete in the slowpath
12988 */
12989 if (!crtc_state->active || needs_modeset(crtc_state) ||
12990 to_intel_crtc_state(crtc_state)->update_pipe)
12991 goto slow;
12992
12993 old_plane_state = plane->state;
12994 /*
12995 * Don't do an async update if there is an outstanding commit modifying
12996 * the plane. This prevents our async update's changes from getting
12997 * overridden by a previous synchronous update's state.
12998 */
12999 if (old_plane_state->commit &&
13000 !try_wait_for_completion(&old_plane_state->commit->hw_done))
13001 goto slow;
13002
13003 /*
13004 * If any parameters change that may affect watermarks,
13005 * take the slowpath. Only changing fb or position should be
13006 * in the fastpath.
13007 */
13008 if (old_plane_state->crtc != crtc ||
13009 old_plane_state->src_w != src_w ||
13010 old_plane_state->src_h != src_h ||
13011 old_plane_state->crtc_w != crtc_w ||
13012 old_plane_state->crtc_h != crtc_h ||
13013 !old_plane_state->fb != !fb)
13014 goto slow;
13015
13016 new_plane_state = intel_plane_duplicate_state(plane);
13017 if (!new_plane_state)
13018 return -ENOMEM;
13019
13020 drm_atomic_set_fb_for_plane(new_plane_state, fb);
13021
13022 new_plane_state->src_x = src_x;
13023 new_plane_state->src_y = src_y;
13024 new_plane_state->src_w = src_w;
13025 new_plane_state->src_h = src_h;
13026 new_plane_state->crtc_x = crtc_x;
13027 new_plane_state->crtc_y = crtc_y;
13028 new_plane_state->crtc_w = crtc_w;
13029 new_plane_state->crtc_h = crtc_h;
13030
13031 ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13032 to_intel_plane_state(new_plane_state));
13033 if (ret)
13034 goto out_free;
13035
13036 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13037 if (ret)
13038 goto out_free;
13039
13040 if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13041 int align = intel_cursor_alignment(dev_priv);
13042
13043 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13044 if (ret) {
13045 DRM_DEBUG_KMS("failed to attach phys object\n");
13046 goto out_unlock;
13047 }
13048 } else {
13049 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13050 if (IS_ERR(vma)) {
13051 DRM_DEBUG_KMS("failed to pin object\n");
13052
13053 ret = PTR_ERR(vma);
13054 goto out_unlock;
13055 }
13056
13057 to_intel_plane_state(new_plane_state)->vma = vma;
13058 }
13059
13060 old_fb = old_plane_state->fb;
13061
13062 i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13063 intel_plane->frontbuffer_bit);
13064
13065 /* Swap plane state */
13066 plane->state = new_plane_state;
13067
13068 if (plane->state->visible) {
13069 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13070 intel_plane->update_plane(intel_plane,
13071 to_intel_crtc_state(crtc->state),
13072 to_intel_plane_state(plane->state));
13073 } else {
13074 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13075 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
13076 }
13077
13078 old_vma = fetch_and_zero(&to_intel_plane_state(old_plane_state)->vma);
13079 if (old_vma)
13080 intel_unpin_fb_vma(old_vma);
13081
13082 out_unlock:
13083 mutex_unlock(&dev_priv->drm.struct_mutex);
13084 out_free:
13085 if (ret)
13086 intel_plane_destroy_state(plane, new_plane_state);
13087 else
13088 intel_plane_destroy_state(plane, old_plane_state);
13089 return ret;
13090
13091 slow:
13092 return drm_atomic_helper_update_plane(plane, crtc, fb,
13093 crtc_x, crtc_y, crtc_w, crtc_h,
13094 src_x, src_y, src_w, src_h, ctx);
13095 }
13096
13097 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13098 .update_plane = intel_legacy_cursor_update,
13099 .disable_plane = drm_atomic_helper_disable_plane,
13100 .destroy = intel_plane_destroy,
13101 .atomic_get_property = intel_plane_atomic_get_property,
13102 .atomic_set_property = intel_plane_atomic_set_property,
13103 .atomic_duplicate_state = intel_plane_duplicate_state,
13104 .atomic_destroy_state = intel_plane_destroy_state,
13105 .format_mod_supported = intel_cursor_plane_format_mod_supported,
13106 };
13107
13108 static struct intel_plane *
13109 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13110 {
13111 struct intel_plane *primary = NULL;
13112 struct intel_plane_state *state = NULL;
13113 const uint32_t *intel_primary_formats;
13114 unsigned int supported_rotations;
13115 unsigned int num_formats;
13116 const uint64_t *modifiers;
13117 int ret;
13118
13119 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13120 if (!primary) {
13121 ret = -ENOMEM;
13122 goto fail;
13123 }
13124
13125 state = intel_create_plane_state(&primary->base);
13126 if (!state) {
13127 ret = -ENOMEM;
13128 goto fail;
13129 }
13130
13131 primary->base.state = &state->base;
13132
13133 primary->can_scale = false;
13134 primary->max_downscale = 1;
13135 if (INTEL_GEN(dev_priv) >= 9) {
13136 primary->can_scale = true;
13137 state->scaler_id = -1;
13138 }
13139 primary->pipe = pipe;
13140 /*
13141 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13142 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13143 */
13144 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13145 primary->plane = (enum plane) !pipe;
13146 else
13147 primary->plane = (enum plane) pipe;
13148 primary->id = PLANE_PRIMARY;
13149 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13150 primary->check_plane = intel_check_primary_plane;
13151
13152 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
13153 intel_primary_formats = skl_primary_formats;
13154 num_formats = ARRAY_SIZE(skl_primary_formats);
13155 modifiers = skl_format_modifiers_ccs;
13156
13157 primary->update_plane = skylake_update_primary_plane;
13158 primary->disable_plane = skylake_disable_primary_plane;
13159 } else if (INTEL_GEN(dev_priv) >= 9) {
13160 intel_primary_formats = skl_primary_formats;
13161 num_formats = ARRAY_SIZE(skl_primary_formats);
13162 if (pipe < PIPE_C)
13163 modifiers = skl_format_modifiers_ccs;
13164 else
13165 modifiers = skl_format_modifiers_noccs;
13166
13167 primary->update_plane = skylake_update_primary_plane;
13168 primary->disable_plane = skylake_disable_primary_plane;
13169 } else if (INTEL_GEN(dev_priv) >= 4) {
13170 intel_primary_formats = i965_primary_formats;
13171 num_formats = ARRAY_SIZE(i965_primary_formats);
13172 modifiers = i9xx_format_modifiers;
13173
13174 primary->update_plane = i9xx_update_primary_plane;
13175 primary->disable_plane = i9xx_disable_primary_plane;
13176 } else {
13177 intel_primary_formats = i8xx_primary_formats;
13178 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13179 modifiers = i9xx_format_modifiers;
13180
13181 primary->update_plane = i9xx_update_primary_plane;
13182 primary->disable_plane = i9xx_disable_primary_plane;
13183 }
13184
13185 if (INTEL_GEN(dev_priv) >= 9)
13186 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13187 0, &intel_plane_funcs,
13188 intel_primary_formats, num_formats,
13189 modifiers,
13190 DRM_PLANE_TYPE_PRIMARY,
13191 "plane 1%c", pipe_name(pipe));
13192 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13193 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13194 0, &intel_plane_funcs,
13195 intel_primary_formats, num_formats,
13196 modifiers,
13197 DRM_PLANE_TYPE_PRIMARY,
13198 "primary %c", pipe_name(pipe));
13199 else
13200 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13201 0, &intel_plane_funcs,
13202 intel_primary_formats, num_formats,
13203 modifiers,
13204 DRM_PLANE_TYPE_PRIMARY,
13205 "plane %c", plane_name(primary->plane));
13206 if (ret)
13207 goto fail;
13208
13209 if (INTEL_GEN(dev_priv) >= 9) {
13210 supported_rotations =
13211 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13212 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
13213 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13214 supported_rotations =
13215 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
13216 DRM_MODE_REFLECT_X;
13217 } else if (INTEL_GEN(dev_priv) >= 4) {
13218 supported_rotations =
13219 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
13220 } else {
13221 supported_rotations = DRM_MODE_ROTATE_0;
13222 }
13223
13224 if (INTEL_GEN(dev_priv) >= 4)
13225 drm_plane_create_rotation_property(&primary->base,
13226 DRM_MODE_ROTATE_0,
13227 supported_rotations);
13228
13229 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13230
13231 return primary;
13232
13233 fail:
13234 kfree(state);
13235 kfree(primary);
13236
13237 return ERR_PTR(ret);
13238 }
13239
13240 static struct intel_plane *
13241 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13242 enum pipe pipe)
13243 {
13244 struct intel_plane *cursor = NULL;
13245 struct intel_plane_state *state = NULL;
13246 int ret;
13247
13248 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13249 if (!cursor) {
13250 ret = -ENOMEM;
13251 goto fail;
13252 }
13253
13254 state = intel_create_plane_state(&cursor->base);
13255 if (!state) {
13256 ret = -ENOMEM;
13257 goto fail;
13258 }
13259
13260 cursor->base.state = &state->base;
13261
13262 cursor->can_scale = false;
13263 cursor->max_downscale = 1;
13264 cursor->pipe = pipe;
13265 cursor->plane = pipe;
13266 cursor->id = PLANE_CURSOR;
13267 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13268
13269 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
13270 cursor->update_plane = i845_update_cursor;
13271 cursor->disable_plane = i845_disable_cursor;
13272 cursor->check_plane = i845_check_cursor;
13273 } else {
13274 cursor->update_plane = i9xx_update_cursor;
13275 cursor->disable_plane = i9xx_disable_cursor;
13276 cursor->check_plane = i9xx_check_cursor;
13277 }
13278
13279 cursor->cursor.base = ~0;
13280 cursor->cursor.cntl = ~0;
13281
13282 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
13283 cursor->cursor.size = ~0;
13284
13285 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13286 0, &intel_cursor_plane_funcs,
13287 intel_cursor_formats,
13288 ARRAY_SIZE(intel_cursor_formats),
13289 cursor_format_modifiers,
13290 DRM_PLANE_TYPE_CURSOR,
13291 "cursor %c", pipe_name(pipe));
13292 if (ret)
13293 goto fail;
13294
13295 if (INTEL_GEN(dev_priv) >= 4)
13296 drm_plane_create_rotation_property(&cursor->base,
13297 DRM_MODE_ROTATE_0,
13298 DRM_MODE_ROTATE_0 |
13299 DRM_MODE_ROTATE_180);
13300
13301 if (INTEL_GEN(dev_priv) >= 9)
13302 state->scaler_id = -1;
13303
13304 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13305
13306 return cursor;
13307
13308 fail:
13309 kfree(state);
13310 kfree(cursor);
13311
13312 return ERR_PTR(ret);
13313 }
13314
13315 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13316 struct intel_crtc_state *crtc_state)
13317 {
13318 struct intel_crtc_scaler_state *scaler_state =
13319 &crtc_state->scaler_state;
13320 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13321 int i;
13322
13323 crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13324 if (!crtc->num_scalers)
13325 return;
13326
13327 for (i = 0; i < crtc->num_scalers; i++) {
13328 struct intel_scaler *scaler = &scaler_state->scalers[i];
13329
13330 scaler->in_use = 0;
13331 scaler->mode = PS_SCALER_MODE_DYN;
13332 }
13333
13334 scaler_state->scaler_id = -1;
13335 }
13336
13337 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13338 {
13339 struct intel_crtc *intel_crtc;
13340 struct intel_crtc_state *crtc_state = NULL;
13341 struct intel_plane *primary = NULL;
13342 struct intel_plane *cursor = NULL;
13343 int sprite, ret;
13344
13345 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13346 if (!intel_crtc)
13347 return -ENOMEM;
13348
13349 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13350 if (!crtc_state) {
13351 ret = -ENOMEM;
13352 goto fail;
13353 }
13354 intel_crtc->config = crtc_state;
13355 intel_crtc->base.state = &crtc_state->base;
13356 crtc_state->base.crtc = &intel_crtc->base;
13357
13358 primary = intel_primary_plane_create(dev_priv, pipe);
13359 if (IS_ERR(primary)) {
13360 ret = PTR_ERR(primary);
13361 goto fail;
13362 }
13363 intel_crtc->plane_ids_mask |= BIT(primary->id);
13364
13365 for_each_sprite(dev_priv, pipe, sprite) {
13366 struct intel_plane *plane;
13367
13368 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13369 if (IS_ERR(plane)) {
13370 ret = PTR_ERR(plane);
13371 goto fail;
13372 }
13373 intel_crtc->plane_ids_mask |= BIT(plane->id);
13374 }
13375
13376 cursor = intel_cursor_plane_create(dev_priv, pipe);
13377 if (IS_ERR(cursor)) {
13378 ret = PTR_ERR(cursor);
13379 goto fail;
13380 }
13381 intel_crtc->plane_ids_mask |= BIT(cursor->id);
13382
13383 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13384 &primary->base, &cursor->base,
13385 &intel_crtc_funcs,
13386 "pipe %c", pipe_name(pipe));
13387 if (ret)
13388 goto fail;
13389
13390 intel_crtc->pipe = pipe;
13391 intel_crtc->plane = primary->plane;
13392
13393 /* initialize shared scalers */
13394 intel_crtc_init_scalers(intel_crtc, crtc_state);
13395
13396 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13397 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13398 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13399 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13400
13401 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13402
13403 intel_color_init(&intel_crtc->base);
13404
13405 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13406
13407 return 0;
13408
13409 fail:
13410 /*
13411 * drm_mode_config_cleanup() will free up any
13412 * crtcs/planes already initialized.
13413 */
13414 kfree(crtc_state);
13415 kfree(intel_crtc);
13416
13417 return ret;
13418 }
13419
13420 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13421 {
13422 struct drm_device *dev = connector->base.dev;
13423
13424 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13425
13426 if (!connector->base.state->crtc)
13427 return INVALID_PIPE;
13428
13429 return to_intel_crtc(connector->base.state->crtc)->pipe;
13430 }
13431
13432 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13433 struct drm_file *file)
13434 {
13435 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13436 struct drm_crtc *drmmode_crtc;
13437 struct intel_crtc *crtc;
13438
13439 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13440 if (!drmmode_crtc)
13441 return -ENOENT;
13442
13443 crtc = to_intel_crtc(drmmode_crtc);
13444 pipe_from_crtc_id->pipe = crtc->pipe;
13445
13446 return 0;
13447 }
13448
13449 static int intel_encoder_clones(struct intel_encoder *encoder)
13450 {
13451 struct drm_device *dev = encoder->base.dev;
13452 struct intel_encoder *source_encoder;
13453 int index_mask = 0;
13454 int entry = 0;
13455
13456 for_each_intel_encoder(dev, source_encoder) {
13457 if (encoders_cloneable(encoder, source_encoder))
13458 index_mask |= (1 << entry);
13459
13460 entry++;
13461 }
13462
13463 return index_mask;
13464 }
13465
13466 static bool has_edp_a(struct drm_i915_private *dev_priv)
13467 {
13468 if (!IS_MOBILE(dev_priv))
13469 return false;
13470
13471 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13472 return false;
13473
13474 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13475 return false;
13476
13477 return true;
13478 }
13479
13480 static bool intel_crt_present(struct drm_i915_private *dev_priv)
13481 {
13482 if (INTEL_GEN(dev_priv) >= 9)
13483 return false;
13484
13485 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
13486 return false;
13487
13488 if (IS_CHERRYVIEW(dev_priv))
13489 return false;
13490
13491 if (HAS_PCH_LPT_H(dev_priv) &&
13492 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
13493 return false;
13494
13495 /* DDI E can't be used if DDI A requires 4 lanes */
13496 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
13497 return false;
13498
13499 if (!dev_priv->vbt.int_crt_support)
13500 return false;
13501
13502 return true;
13503 }
13504
13505 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
13506 {
13507 int pps_num;
13508 int pps_idx;
13509
13510 if (HAS_DDI(dev_priv))
13511 return;
13512 /*
13513 * This w/a is needed at least on CPT/PPT, but to be sure apply it
13514 * everywhere where registers can be write protected.
13515 */
13516 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13517 pps_num = 2;
13518 else
13519 pps_num = 1;
13520
13521 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
13522 u32 val = I915_READ(PP_CONTROL(pps_idx));
13523
13524 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
13525 I915_WRITE(PP_CONTROL(pps_idx), val);
13526 }
13527 }
13528
13529 static void intel_pps_init(struct drm_i915_private *dev_priv)
13530 {
13531 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
13532 dev_priv->pps_mmio_base = PCH_PPS_BASE;
13533 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13534 dev_priv->pps_mmio_base = VLV_PPS_BASE;
13535 else
13536 dev_priv->pps_mmio_base = PPS_BASE;
13537
13538 intel_pps_unlock_regs_wa(dev_priv);
13539 }
13540
13541 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
13542 {
13543 struct intel_encoder *encoder;
13544 bool dpd_is_edp = false;
13545
13546 intel_pps_init(dev_priv);
13547
13548 /*
13549 * intel_edp_init_connector() depends on this completing first, to
13550 * prevent the registeration of both eDP and LVDS and the incorrect
13551 * sharing of the PPS.
13552 */
13553 intel_lvds_init(dev_priv);
13554
13555 if (intel_crt_present(dev_priv))
13556 intel_crt_init(dev_priv);
13557
13558 if (IS_GEN9_LP(dev_priv)) {
13559 /*
13560 * FIXME: Broxton doesn't support port detection via the
13561 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13562 * detect the ports.
13563 */
13564 intel_ddi_init(dev_priv, PORT_A);
13565 intel_ddi_init(dev_priv, PORT_B);
13566 intel_ddi_init(dev_priv, PORT_C);
13567
13568 intel_dsi_init(dev_priv);
13569 } else if (HAS_DDI(dev_priv)) {
13570 int found;
13571
13572 /*
13573 * Haswell uses DDI functions to detect digital outputs.
13574 * On SKL pre-D0 the strap isn't connected, so we assume
13575 * it's there.
13576 */
13577 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13578 /* WaIgnoreDDIAStrap: skl */
13579 if (found || IS_GEN9_BC(dev_priv))
13580 intel_ddi_init(dev_priv, PORT_A);
13581
13582 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13583 * register */
13584 found = I915_READ(SFUSE_STRAP);
13585
13586 if (found & SFUSE_STRAP_DDIB_DETECTED)
13587 intel_ddi_init(dev_priv, PORT_B);
13588 if (found & SFUSE_STRAP_DDIC_DETECTED)
13589 intel_ddi_init(dev_priv, PORT_C);
13590 if (found & SFUSE_STRAP_DDID_DETECTED)
13591 intel_ddi_init(dev_priv, PORT_D);
13592 /*
13593 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13594 */
13595 if (IS_GEN9_BC(dev_priv) &&
13596 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13597 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13598 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13599 intel_ddi_init(dev_priv, PORT_E);
13600
13601 } else if (HAS_PCH_SPLIT(dev_priv)) {
13602 int found;
13603 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
13604
13605 if (has_edp_a(dev_priv))
13606 intel_dp_init(dev_priv, DP_A, PORT_A);
13607
13608 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13609 /* PCH SDVOB multiplex with HDMIB */
13610 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
13611 if (!found)
13612 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
13613 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13614 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
13615 }
13616
13617 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13618 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
13619
13620 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13621 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
13622
13623 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13624 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
13625
13626 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13627 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
13628 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
13629 bool has_edp, has_port;
13630
13631 /*
13632 * The DP_DETECTED bit is the latched state of the DDC
13633 * SDA pin at boot. However since eDP doesn't require DDC
13634 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13635 * eDP ports may have been muxed to an alternate function.
13636 * Thus we can't rely on the DP_DETECTED bit alone to detect
13637 * eDP ports. Consult the VBT as well as DP_DETECTED to
13638 * detect eDP ports.
13639 *
13640 * Sadly the straps seem to be missing sometimes even for HDMI
13641 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
13642 * and VBT for the presence of the port. Additionally we can't
13643 * trust the port type the VBT declares as we've seen at least
13644 * HDMI ports that the VBT claim are DP or eDP.
13645 */
13646 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
13647 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
13648 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
13649 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
13650 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
13651 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
13652
13653 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
13654 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
13655 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
13656 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
13657 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
13658 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
13659
13660 if (IS_CHERRYVIEW(dev_priv)) {
13661 /*
13662 * eDP not supported on port D,
13663 * so no need to worry about it
13664 */
13665 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
13666 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
13667 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
13668 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
13669 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
13670 }
13671
13672 intel_dsi_init(dev_priv);
13673 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
13674 bool found = false;
13675
13676 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13677 DRM_DEBUG_KMS("probing SDVOB\n");
13678 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
13679 if (!found && IS_G4X(dev_priv)) {
13680 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13681 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
13682 }
13683
13684 if (!found && IS_G4X(dev_priv))
13685 intel_dp_init(dev_priv, DP_B, PORT_B);
13686 }
13687
13688 /* Before G4X SDVOC doesn't have its own detect register */
13689
13690 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13691 DRM_DEBUG_KMS("probing SDVOC\n");
13692 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
13693 }
13694
13695 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13696
13697 if (IS_G4X(dev_priv)) {
13698 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13699 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
13700 }
13701 if (IS_G4X(dev_priv))
13702 intel_dp_init(dev_priv, DP_C, PORT_C);
13703 }
13704
13705 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
13706 intel_dp_init(dev_priv, DP_D, PORT_D);
13707 } else if (IS_GEN2(dev_priv))
13708 intel_dvo_init(dev_priv);
13709
13710 if (SUPPORTS_TV(dev_priv))
13711 intel_tv_init(dev_priv);
13712
13713 intel_psr_init(dev_priv);
13714
13715 for_each_intel_encoder(&dev_priv->drm, encoder) {
13716 encoder->base.possible_crtcs = encoder->crtc_mask;
13717 encoder->base.possible_clones =
13718 intel_encoder_clones(encoder);
13719 }
13720
13721 intel_init_pch_refclk(dev_priv);
13722
13723 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
13724 }
13725
13726 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13727 {
13728 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13729
13730 drm_framebuffer_cleanup(fb);
13731
13732 i915_gem_object_lock(intel_fb->obj);
13733 WARN_ON(!intel_fb->obj->framebuffer_references--);
13734 i915_gem_object_unlock(intel_fb->obj);
13735
13736 i915_gem_object_put(intel_fb->obj);
13737
13738 kfree(intel_fb);
13739 }
13740
13741 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13742 struct drm_file *file,
13743 unsigned int *handle)
13744 {
13745 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13746 struct drm_i915_gem_object *obj = intel_fb->obj;
13747
13748 if (obj->userptr.mm) {
13749 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
13750 return -EINVAL;
13751 }
13752
13753 return drm_gem_handle_create(file, &obj->base, handle);
13754 }
13755
13756 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
13757 struct drm_file *file,
13758 unsigned flags, unsigned color,
13759 struct drm_clip_rect *clips,
13760 unsigned num_clips)
13761 {
13762 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13763
13764 i915_gem_object_flush_if_display(obj);
13765 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
13766
13767 return 0;
13768 }
13769
13770 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13771 .destroy = intel_user_framebuffer_destroy,
13772 .create_handle = intel_user_framebuffer_create_handle,
13773 .dirty = intel_user_framebuffer_dirty,
13774 };
13775
13776 static
13777 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
13778 uint64_t fb_modifier, uint32_t pixel_format)
13779 {
13780 u32 gen = INTEL_GEN(dev_priv);
13781
13782 if (gen >= 9) {
13783 int cpp = drm_format_plane_cpp(pixel_format, 0);
13784
13785 /* "The stride in bytes must not exceed the of the size of 8K
13786 * pixels and 32K bytes."
13787 */
13788 return min(8192 * cpp, 32768);
13789 } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
13790 return 32*1024;
13791 } else if (gen >= 4) {
13792 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13793 return 16*1024;
13794 else
13795 return 32*1024;
13796 } else if (gen >= 3) {
13797 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13798 return 8*1024;
13799 else
13800 return 16*1024;
13801 } else {
13802 /* XXX DSPC is limited to 4k tiled */
13803 return 8*1024;
13804 }
13805 }
13806
13807 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
13808 struct drm_i915_gem_object *obj,
13809 struct drm_mode_fb_cmd2 *mode_cmd)
13810 {
13811 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
13812 struct drm_framebuffer *fb = &intel_fb->base;
13813 struct drm_format_name_buf format_name;
13814 u32 pitch_limit;
13815 unsigned int tiling, stride;
13816 int ret = -EINVAL;
13817 int i;
13818
13819 i915_gem_object_lock(obj);
13820 obj->framebuffer_references++;
13821 tiling = i915_gem_object_get_tiling(obj);
13822 stride = i915_gem_object_get_stride(obj);
13823 i915_gem_object_unlock(obj);
13824
13825 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13826 /*
13827 * If there's a fence, enforce that
13828 * the fb modifier and tiling mode match.
13829 */
13830 if (tiling != I915_TILING_NONE &&
13831 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13832 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
13833 goto err;
13834 }
13835 } else {
13836 if (tiling == I915_TILING_X) {
13837 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13838 } else if (tiling == I915_TILING_Y) {
13839 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
13840 goto err;
13841 }
13842 }
13843
13844 /* Passed in modifier sanity checking. */
13845 switch (mode_cmd->modifier[0]) {
13846 case I915_FORMAT_MOD_Y_TILED_CCS:
13847 case I915_FORMAT_MOD_Yf_TILED_CCS:
13848 switch (mode_cmd->pixel_format) {
13849 case DRM_FORMAT_XBGR8888:
13850 case DRM_FORMAT_ABGR8888:
13851 case DRM_FORMAT_XRGB8888:
13852 case DRM_FORMAT_ARGB8888:
13853 break;
13854 default:
13855 DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n");
13856 goto err;
13857 }
13858 /* fall through */
13859 case I915_FORMAT_MOD_Y_TILED:
13860 case I915_FORMAT_MOD_Yf_TILED:
13861 if (INTEL_GEN(dev_priv) < 9) {
13862 DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
13863 mode_cmd->modifier[0]);
13864 goto err;
13865 }
13866 case DRM_FORMAT_MOD_LINEAR:
13867 case I915_FORMAT_MOD_X_TILED:
13868 break;
13869 default:
13870 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
13871 mode_cmd->modifier[0]);
13872 goto err;
13873 }
13874
13875 /*
13876 * gen2/3 display engine uses the fence if present,
13877 * so the tiling mode must match the fb modifier exactly.
13878 */
13879 if (INTEL_INFO(dev_priv)->gen < 4 &&
13880 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13881 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
13882 goto err;
13883 }
13884
13885 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
13886 mode_cmd->pixel_format);
13887 if (mode_cmd->pitches[0] > pitch_limit) {
13888 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
13889 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
13890 "tiled" : "linear",
13891 mode_cmd->pitches[0], pitch_limit);
13892 goto err;
13893 }
13894
13895 /*
13896 * If there's a fence, enforce that
13897 * the fb pitch and fence stride match.
13898 */
13899 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
13900 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
13901 mode_cmd->pitches[0], stride);
13902 goto err;
13903 }
13904
13905 /* Reject formats not supported by any plane early. */
13906 switch (mode_cmd->pixel_format) {
13907 case DRM_FORMAT_C8:
13908 case DRM_FORMAT_RGB565:
13909 case DRM_FORMAT_XRGB8888:
13910 case DRM_FORMAT_ARGB8888:
13911 break;
13912 case DRM_FORMAT_XRGB1555:
13913 if (INTEL_GEN(dev_priv) > 3) {
13914 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13915 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13916 goto err;
13917 }
13918 break;
13919 case DRM_FORMAT_ABGR8888:
13920 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
13921 INTEL_GEN(dev_priv) < 9) {
13922 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13923 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13924 goto err;
13925 }
13926 break;
13927 case DRM_FORMAT_XBGR8888:
13928 case DRM_FORMAT_XRGB2101010:
13929 case DRM_FORMAT_XBGR2101010:
13930 if (INTEL_GEN(dev_priv) < 4) {
13931 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13932 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13933 goto err;
13934 }
13935 break;
13936 case DRM_FORMAT_ABGR2101010:
13937 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
13938 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13939 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13940 goto err;
13941 }
13942 break;
13943 case DRM_FORMAT_YUYV:
13944 case DRM_FORMAT_UYVY:
13945 case DRM_FORMAT_YVYU:
13946 case DRM_FORMAT_VYUY:
13947 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
13948 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13949 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13950 goto err;
13951 }
13952 break;
13953 default:
13954 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13955 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13956 goto err;
13957 }
13958
13959 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13960 if (mode_cmd->offsets[0] != 0)
13961 goto err;
13962
13963 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
13964
13965 for (i = 0; i < fb->format->num_planes; i++) {
13966 u32 stride_alignment;
13967
13968 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
13969 DRM_DEBUG_KMS("bad plane %d handle\n", i);
13970 goto err;
13971 }
13972
13973 stride_alignment = intel_fb_stride_alignment(fb, i);
13974
13975 /*
13976 * Display WA #0531: skl,bxt,kbl,glk
13977 *
13978 * Render decompression and plane width > 3840
13979 * combined with horizontal panning requires the
13980 * plane stride to be a multiple of 4. We'll just
13981 * require the entire fb to accommodate that to avoid
13982 * potential runtime errors at plane configuration time.
13983 */
13984 if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 &&
13985 (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
13986 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS))
13987 stride_alignment *= 4;
13988
13989 if (fb->pitches[i] & (stride_alignment - 1)) {
13990 DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
13991 i, fb->pitches[i], stride_alignment);
13992 goto err;
13993 }
13994 }
13995
13996 intel_fb->obj = obj;
13997
13998 ret = intel_fill_fb_info(dev_priv, fb);
13999 if (ret)
14000 goto err;
14001
14002 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
14003 if (ret) {
14004 DRM_ERROR("framebuffer init failed %d\n", ret);
14005 goto err;
14006 }
14007
14008 return 0;
14009
14010 err:
14011 i915_gem_object_lock(obj);
14012 obj->framebuffer_references--;
14013 i915_gem_object_unlock(obj);
14014 return ret;
14015 }
14016
14017 static struct drm_framebuffer *
14018 intel_user_framebuffer_create(struct drm_device *dev,
14019 struct drm_file *filp,
14020 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14021 {
14022 struct drm_framebuffer *fb;
14023 struct drm_i915_gem_object *obj;
14024 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14025
14026 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14027 if (!obj)
14028 return ERR_PTR(-ENOENT);
14029
14030 fb = intel_framebuffer_create(obj, &mode_cmd);
14031 if (IS_ERR(fb))
14032 i915_gem_object_put(obj);
14033
14034 return fb;
14035 }
14036
14037 static void intel_atomic_state_free(struct drm_atomic_state *state)
14038 {
14039 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14040
14041 drm_atomic_state_default_release(state);
14042
14043 i915_sw_fence_fini(&intel_state->commit_ready);
14044
14045 kfree(state);
14046 }
14047
14048 static const struct drm_mode_config_funcs intel_mode_funcs = {
14049 .fb_create = intel_user_framebuffer_create,
14050 .get_format_info = intel_get_format_info,
14051 .output_poll_changed = intel_fbdev_output_poll_changed,
14052 .atomic_check = intel_atomic_check,
14053 .atomic_commit = intel_atomic_commit,
14054 .atomic_state_alloc = intel_atomic_state_alloc,
14055 .atomic_state_clear = intel_atomic_state_clear,
14056 .atomic_state_free = intel_atomic_state_free,
14057 };
14058
14059 /**
14060 * intel_init_display_hooks - initialize the display modesetting hooks
14061 * @dev_priv: device private
14062 */
14063 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14064 {
14065 intel_init_cdclk_hooks(dev_priv);
14066
14067 if (INTEL_INFO(dev_priv)->gen >= 9) {
14068 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14069 dev_priv->display.get_initial_plane_config =
14070 skylake_get_initial_plane_config;
14071 dev_priv->display.crtc_compute_clock =
14072 haswell_crtc_compute_clock;
14073 dev_priv->display.crtc_enable = haswell_crtc_enable;
14074 dev_priv->display.crtc_disable = haswell_crtc_disable;
14075 } else if (HAS_DDI(dev_priv)) {
14076 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14077 dev_priv->display.get_initial_plane_config =
14078 ironlake_get_initial_plane_config;
14079 dev_priv->display.crtc_compute_clock =
14080 haswell_crtc_compute_clock;
14081 dev_priv->display.crtc_enable = haswell_crtc_enable;
14082 dev_priv->display.crtc_disable = haswell_crtc_disable;
14083 } else if (HAS_PCH_SPLIT(dev_priv)) {
14084 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14085 dev_priv->display.get_initial_plane_config =
14086 ironlake_get_initial_plane_config;
14087 dev_priv->display.crtc_compute_clock =
14088 ironlake_crtc_compute_clock;
14089 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14090 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14091 } else if (IS_CHERRYVIEW(dev_priv)) {
14092 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14093 dev_priv->display.get_initial_plane_config =
14094 i9xx_get_initial_plane_config;
14095 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14096 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14097 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14098 } else if (IS_VALLEYVIEW(dev_priv)) {
14099 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14100 dev_priv->display.get_initial_plane_config =
14101 i9xx_get_initial_plane_config;
14102 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14103 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14104 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14105 } else if (IS_G4X(dev_priv)) {
14106 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14107 dev_priv->display.get_initial_plane_config =
14108 i9xx_get_initial_plane_config;
14109 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14110 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14111 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14112 } else if (IS_PINEVIEW(dev_priv)) {
14113 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14114 dev_priv->display.get_initial_plane_config =
14115 i9xx_get_initial_plane_config;
14116 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14117 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14118 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14119 } else if (!IS_GEN2(dev_priv)) {
14120 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14121 dev_priv->display.get_initial_plane_config =
14122 i9xx_get_initial_plane_config;
14123 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14124 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14125 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14126 } else {
14127 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14128 dev_priv->display.get_initial_plane_config =
14129 i9xx_get_initial_plane_config;
14130 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14131 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14132 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14133 }
14134
14135 if (IS_GEN5(dev_priv)) {
14136 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14137 } else if (IS_GEN6(dev_priv)) {
14138 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14139 } else if (IS_IVYBRIDGE(dev_priv)) {
14140 /* FIXME: detect B0+ stepping and use auto training */
14141 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14142 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14143 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14144 }
14145
14146 if (dev_priv->info.gen >= 9)
14147 dev_priv->display.update_crtcs = skl_update_crtcs;
14148 else
14149 dev_priv->display.update_crtcs = intel_update_crtcs;
14150 }
14151
14152 /*
14153 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14154 */
14155 static void quirk_ssc_force_disable(struct drm_device *dev)
14156 {
14157 struct drm_i915_private *dev_priv = to_i915(dev);
14158 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14159 DRM_INFO("applying lvds SSC disable quirk\n");
14160 }
14161
14162 /*
14163 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14164 * brightness value
14165 */
14166 static void quirk_invert_brightness(struct drm_device *dev)
14167 {
14168 struct drm_i915_private *dev_priv = to_i915(dev);
14169 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14170 DRM_INFO("applying inverted panel brightness quirk\n");
14171 }
14172
14173 /* Some VBT's incorrectly indicate no backlight is present */
14174 static void quirk_backlight_present(struct drm_device *dev)
14175 {
14176 struct drm_i915_private *dev_priv = to_i915(dev);
14177 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14178 DRM_INFO("applying backlight present quirk\n");
14179 }
14180
14181 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
14182 * which is 300 ms greater than eDP spec T12 min.
14183 */
14184 static void quirk_increase_t12_delay(struct drm_device *dev)
14185 {
14186 struct drm_i915_private *dev_priv = to_i915(dev);
14187
14188 dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY;
14189 DRM_INFO("Applying T12 delay quirk\n");
14190 }
14191
14192 struct intel_quirk {
14193 int device;
14194 int subsystem_vendor;
14195 int subsystem_device;
14196 void (*hook)(struct drm_device *dev);
14197 };
14198
14199 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14200 struct intel_dmi_quirk {
14201 void (*hook)(struct drm_device *dev);
14202 const struct dmi_system_id (*dmi_id_list)[];
14203 };
14204
14205 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14206 {
14207 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14208 return 1;
14209 }
14210
14211 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14212 {
14213 .dmi_id_list = &(const struct dmi_system_id[]) {
14214 {
14215 .callback = intel_dmi_reverse_brightness,
14216 .ident = "NCR Corporation",
14217 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14218 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14219 },
14220 },
14221 { } /* terminating entry */
14222 },
14223 .hook = quirk_invert_brightness,
14224 },
14225 };
14226
14227 static struct intel_quirk intel_quirks[] = {
14228 /* Lenovo U160 cannot use SSC on LVDS */
14229 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14230
14231 /* Sony Vaio Y cannot use SSC on LVDS */
14232 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14233
14234 /* Acer Aspire 5734Z must invert backlight brightness */
14235 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14236
14237 /* Acer/eMachines G725 */
14238 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14239
14240 /* Acer/eMachines e725 */
14241 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14242
14243 /* Acer/Packard Bell NCL20 */
14244 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14245
14246 /* Acer Aspire 4736Z */
14247 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14248
14249 /* Acer Aspire 5336 */
14250 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14251
14252 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14253 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14254
14255 /* Acer C720 Chromebook (Core i3 4005U) */
14256 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14257
14258 /* Apple Macbook 2,1 (Core 2 T7400) */
14259 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14260
14261 /* Apple Macbook 4,1 */
14262 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14263
14264 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14265 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14266
14267 /* HP Chromebook 14 (Celeron 2955U) */
14268 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14269
14270 /* Dell Chromebook 11 */
14271 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14272
14273 /* Dell Chromebook 11 (2015 version) */
14274 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14275
14276 /* Toshiba Satellite P50-C-18C */
14277 { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
14278 };
14279
14280 static void intel_init_quirks(struct drm_device *dev)
14281 {
14282 struct pci_dev *d = dev->pdev;
14283 int i;
14284
14285 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14286 struct intel_quirk *q = &intel_quirks[i];
14287
14288 if (d->device == q->device &&
14289 (d->subsystem_vendor == q->subsystem_vendor ||
14290 q->subsystem_vendor == PCI_ANY_ID) &&
14291 (d->subsystem_device == q->subsystem_device ||
14292 q->subsystem_device == PCI_ANY_ID))
14293 q->hook(dev);
14294 }
14295 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14296 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14297 intel_dmi_quirks[i].hook(dev);
14298 }
14299 }
14300
14301 /* Disable the VGA plane that we never use */
14302 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14303 {
14304 struct pci_dev *pdev = dev_priv->drm.pdev;
14305 u8 sr1;
14306 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14307
14308 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14309 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14310 outb(SR01, VGA_SR_INDEX);
14311 sr1 = inb(VGA_SR_DATA);
14312 outb(sr1 | 1<<5, VGA_SR_DATA);
14313 vga_put(pdev, VGA_RSRC_LEGACY_IO);
14314 udelay(300);
14315
14316 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14317 POSTING_READ(vga_reg);
14318 }
14319
14320 void intel_modeset_init_hw(struct drm_device *dev)
14321 {
14322 struct drm_i915_private *dev_priv = to_i915(dev);
14323
14324 intel_update_cdclk(dev_priv);
14325 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14326
14327 intel_init_clock_gating(dev_priv);
14328 }
14329
14330 /*
14331 * Calculate what we think the watermarks should be for the state we've read
14332 * out of the hardware and then immediately program those watermarks so that
14333 * we ensure the hardware settings match our internal state.
14334 *
14335 * We can calculate what we think WM's should be by creating a duplicate of the
14336 * current state (which was constructed during hardware readout) and running it
14337 * through the atomic check code to calculate new watermark values in the
14338 * state object.
14339 */
14340 static void sanitize_watermarks(struct drm_device *dev)
14341 {
14342 struct drm_i915_private *dev_priv = to_i915(dev);
14343 struct drm_atomic_state *state;
14344 struct intel_atomic_state *intel_state;
14345 struct drm_crtc *crtc;
14346 struct drm_crtc_state *cstate;
14347 struct drm_modeset_acquire_ctx ctx;
14348 int ret;
14349 int i;
14350
14351 /* Only supported on platforms that use atomic watermark design */
14352 if (!dev_priv->display.optimize_watermarks)
14353 return;
14354
14355 /*
14356 * We need to hold connection_mutex before calling duplicate_state so
14357 * that the connector loop is protected.
14358 */
14359 drm_modeset_acquire_init(&ctx, 0);
14360 retry:
14361 ret = drm_modeset_lock_all_ctx(dev, &ctx);
14362 if (ret == -EDEADLK) {
14363 drm_modeset_backoff(&ctx);
14364 goto retry;
14365 } else if (WARN_ON(ret)) {
14366 goto fail;
14367 }
14368
14369 state = drm_atomic_helper_duplicate_state(dev, &ctx);
14370 if (WARN_ON(IS_ERR(state)))
14371 goto fail;
14372
14373 intel_state = to_intel_atomic_state(state);
14374
14375 /*
14376 * Hardware readout is the only time we don't want to calculate
14377 * intermediate watermarks (since we don't trust the current
14378 * watermarks).
14379 */
14380 if (!HAS_GMCH_DISPLAY(dev_priv))
14381 intel_state->skip_intermediate_wm = true;
14382
14383 ret = intel_atomic_check(dev, state);
14384 if (ret) {
14385 /*
14386 * If we fail here, it means that the hardware appears to be
14387 * programmed in a way that shouldn't be possible, given our
14388 * understanding of watermark requirements. This might mean a
14389 * mistake in the hardware readout code or a mistake in the
14390 * watermark calculations for a given platform. Raise a WARN
14391 * so that this is noticeable.
14392 *
14393 * If this actually happens, we'll have to just leave the
14394 * BIOS-programmed watermarks untouched and hope for the best.
14395 */
14396 WARN(true, "Could not determine valid watermarks for inherited state\n");
14397 goto put_state;
14398 }
14399
14400 /* Write calculated watermark values back */
14401 for_each_new_crtc_in_state(state, crtc, cstate, i) {
14402 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14403
14404 cs->wm.need_postvbl_update = true;
14405 dev_priv->display.optimize_watermarks(intel_state, cs);
14406 }
14407
14408 put_state:
14409 drm_atomic_state_put(state);
14410 fail:
14411 drm_modeset_drop_locks(&ctx);
14412 drm_modeset_acquire_fini(&ctx);
14413 }
14414
14415 int intel_modeset_init(struct drm_device *dev)
14416 {
14417 struct drm_i915_private *dev_priv = to_i915(dev);
14418 struct i915_ggtt *ggtt = &dev_priv->ggtt;
14419 enum pipe pipe;
14420 struct intel_crtc *crtc;
14421
14422 drm_mode_config_init(dev);
14423
14424 dev->mode_config.min_width = 0;
14425 dev->mode_config.min_height = 0;
14426
14427 dev->mode_config.preferred_depth = 24;
14428 dev->mode_config.prefer_shadow = 1;
14429
14430 dev->mode_config.allow_fb_modifiers = true;
14431
14432 dev->mode_config.funcs = &intel_mode_funcs;
14433
14434 init_llist_head(&dev_priv->atomic_helper.free_list);
14435 INIT_WORK(&dev_priv->atomic_helper.free_work,
14436 intel_atomic_helper_free_state_worker);
14437
14438 intel_init_quirks(dev);
14439
14440 intel_init_pm(dev_priv);
14441
14442 if (INTEL_INFO(dev_priv)->num_pipes == 0)
14443 return 0;
14444
14445 /*
14446 * There may be no VBT; and if the BIOS enabled SSC we can
14447 * just keep using it to avoid unnecessary flicker. Whereas if the
14448 * BIOS isn't using it, don't assume it will work even if the VBT
14449 * indicates as much.
14450 */
14451 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
14452 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14453 DREF_SSC1_ENABLE);
14454
14455 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14456 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14457 bios_lvds_use_ssc ? "en" : "dis",
14458 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14459 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14460 }
14461 }
14462
14463 if (IS_GEN2(dev_priv)) {
14464 dev->mode_config.max_width = 2048;
14465 dev->mode_config.max_height = 2048;
14466 } else if (IS_GEN3(dev_priv)) {
14467 dev->mode_config.max_width = 4096;
14468 dev->mode_config.max_height = 4096;
14469 } else {
14470 dev->mode_config.max_width = 8192;
14471 dev->mode_config.max_height = 8192;
14472 }
14473
14474 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14475 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
14476 dev->mode_config.cursor_height = 1023;
14477 } else if (IS_GEN2(dev_priv)) {
14478 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14479 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14480 } else {
14481 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14482 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14483 }
14484
14485 dev->mode_config.fb_base = ggtt->mappable_base;
14486
14487 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14488 INTEL_INFO(dev_priv)->num_pipes,
14489 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
14490
14491 for_each_pipe(dev_priv, pipe) {
14492 int ret;
14493
14494 ret = intel_crtc_init(dev_priv, pipe);
14495 if (ret) {
14496 drm_mode_config_cleanup(dev);
14497 return ret;
14498 }
14499 }
14500
14501 intel_shared_dpll_init(dev);
14502
14503 intel_update_czclk(dev_priv);
14504 intel_modeset_init_hw(dev);
14505
14506 if (dev_priv->max_cdclk_freq == 0)
14507 intel_update_max_cdclk(dev_priv);
14508
14509 /* Just disable it once at startup */
14510 i915_disable_vga(dev_priv);
14511 intel_setup_outputs(dev_priv);
14512
14513 drm_modeset_lock_all(dev);
14514 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
14515 drm_modeset_unlock_all(dev);
14516
14517 for_each_intel_crtc(dev, crtc) {
14518 struct intel_initial_plane_config plane_config = {};
14519
14520 if (!crtc->active)
14521 continue;
14522
14523 /*
14524 * Note that reserving the BIOS fb up front prevents us
14525 * from stuffing other stolen allocations like the ring
14526 * on top. This prevents some ugliness at boot time, and
14527 * can even allow for smooth boot transitions if the BIOS
14528 * fb is large enough for the active pipe configuration.
14529 */
14530 dev_priv->display.get_initial_plane_config(crtc,
14531 &plane_config);
14532
14533 /*
14534 * If the fb is shared between multiple heads, we'll
14535 * just get the first one.
14536 */
14537 intel_find_initial_plane_obj(crtc, &plane_config);
14538 }
14539
14540 /*
14541 * Make sure hardware watermarks really match the state we read out.
14542 * Note that we need to do this after reconstructing the BIOS fb's
14543 * since the watermark calculation done here will use pstate->fb.
14544 */
14545 if (!HAS_GMCH_DISPLAY(dev_priv))
14546 sanitize_watermarks(dev);
14547
14548 return 0;
14549 }
14550
14551 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14552 {
14553 /* 640x480@60Hz, ~25175 kHz */
14554 struct dpll clock = {
14555 .m1 = 18,
14556 .m2 = 7,
14557 .p1 = 13,
14558 .p2 = 4,
14559 .n = 2,
14560 };
14561 u32 dpll, fp;
14562 int i;
14563
14564 WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
14565
14566 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
14567 pipe_name(pipe), clock.vco, clock.dot);
14568
14569 fp = i9xx_dpll_compute_fp(&clock);
14570 dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
14571 DPLL_VGA_MODE_DIS |
14572 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
14573 PLL_P2_DIVIDE_BY_4 |
14574 PLL_REF_INPUT_DREFCLK |
14575 DPLL_VCO_ENABLE;
14576
14577 I915_WRITE(FP0(pipe), fp);
14578 I915_WRITE(FP1(pipe), fp);
14579
14580 I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
14581 I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
14582 I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
14583 I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
14584 I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
14585 I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
14586 I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
14587
14588 /*
14589 * Apparently we need to have VGA mode enabled prior to changing
14590 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
14591 * dividers, even though the register value does change.
14592 */
14593 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
14594 I915_WRITE(DPLL(pipe), dpll);
14595
14596 /* Wait for the clocks to stabilize. */
14597 POSTING_READ(DPLL(pipe));
14598 udelay(150);
14599
14600 /* The pixel multiplier can only be updated once the
14601 * DPLL is enabled and the clocks are stable.
14602 *
14603 * So write it again.
14604 */
14605 I915_WRITE(DPLL(pipe), dpll);
14606
14607 /* We do this three times for luck */
14608 for (i = 0; i < 3 ; i++) {
14609 I915_WRITE(DPLL(pipe), dpll);
14610 POSTING_READ(DPLL(pipe));
14611 udelay(150); /* wait for warmup */
14612 }
14613
14614 I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
14615 POSTING_READ(PIPECONF(pipe));
14616 }
14617
14618 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14619 {
14620 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
14621 pipe_name(pipe));
14622
14623 assert_plane_disabled(dev_priv, PLANE_A);
14624 assert_plane_disabled(dev_priv, PLANE_B);
14625
14626 I915_WRITE(PIPECONF(pipe), 0);
14627 POSTING_READ(PIPECONF(pipe));
14628
14629 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
14630 DRM_ERROR("pipe %c off wait timed out\n", pipe_name(pipe));
14631
14632 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
14633 POSTING_READ(DPLL(pipe));
14634 }
14635
14636 static bool
14637 intel_check_plane_mapping(struct intel_crtc *crtc)
14638 {
14639 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14640 u32 val;
14641
14642 if (INTEL_INFO(dev_priv)->num_pipes == 1)
14643 return true;
14644
14645 val = I915_READ(DSPCNTR(!crtc->plane));
14646
14647 if ((val & DISPLAY_PLANE_ENABLE) &&
14648 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14649 return false;
14650
14651 return true;
14652 }
14653
14654 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14655 {
14656 struct drm_device *dev = crtc->base.dev;
14657 struct intel_encoder *encoder;
14658
14659 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14660 return true;
14661
14662 return false;
14663 }
14664
14665 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
14666 {
14667 struct drm_device *dev = encoder->base.dev;
14668 struct intel_connector *connector;
14669
14670 for_each_connector_on_encoder(dev, &encoder->base, connector)
14671 return connector;
14672
14673 return NULL;
14674 }
14675
14676 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
14677 enum transcoder pch_transcoder)
14678 {
14679 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
14680 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
14681 }
14682
14683 static void intel_sanitize_crtc(struct intel_crtc *crtc,
14684 struct drm_modeset_acquire_ctx *ctx)
14685 {
14686 struct drm_device *dev = crtc->base.dev;
14687 struct drm_i915_private *dev_priv = to_i915(dev);
14688 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
14689
14690 /* Clear any frame start delays used for debugging left by the BIOS */
14691 if (!transcoder_is_dsi(cpu_transcoder)) {
14692 i915_reg_t reg = PIPECONF(cpu_transcoder);
14693
14694 I915_WRITE(reg,
14695 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14696 }
14697
14698 /* restore vblank interrupts to correct state */
14699 drm_crtc_vblank_reset(&crtc->base);
14700 if (crtc->active) {
14701 struct intel_plane *plane;
14702
14703 drm_crtc_vblank_on(&crtc->base);
14704
14705 /* Disable everything but the primary plane */
14706 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14707 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14708 continue;
14709
14710 trace_intel_disable_plane(&plane->base, crtc);
14711 plane->disable_plane(plane, crtc);
14712 }
14713 }
14714
14715 /* We need to sanitize the plane -> pipe mapping first because this will
14716 * disable the crtc (and hence change the state) if it is wrong. Note
14717 * that gen4+ has a fixed plane -> pipe mapping. */
14718 if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
14719 bool plane;
14720
14721 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
14722 crtc->base.base.id, crtc->base.name);
14723
14724 /* Pipe has the wrong plane attached and the plane is active.
14725 * Temporarily change the plane mapping and disable everything
14726 * ... */
14727 plane = crtc->plane;
14728 crtc->base.primary->state->visible = true;
14729 crtc->plane = !plane;
14730 intel_crtc_disable_noatomic(&crtc->base, ctx);
14731 crtc->plane = plane;
14732 }
14733
14734 /* Adjust the state of the output pipe according to whether we
14735 * have active connectors/encoders. */
14736 if (crtc->active && !intel_crtc_has_encoders(crtc))
14737 intel_crtc_disable_noatomic(&crtc->base, ctx);
14738
14739 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
14740 /*
14741 * We start out with underrun reporting disabled to avoid races.
14742 * For correct bookkeeping mark this on active crtcs.
14743 *
14744 * Also on gmch platforms we dont have any hardware bits to
14745 * disable the underrun reporting. Which means we need to start
14746 * out with underrun reporting disabled also on inactive pipes,
14747 * since otherwise we'll complain about the garbage we read when
14748 * e.g. coming up after runtime pm.
14749 *
14750 * No protection against concurrent access is required - at
14751 * worst a fifo underrun happens which also sets this to false.
14752 */
14753 crtc->cpu_fifo_underrun_disabled = true;
14754 /*
14755 * We track the PCH trancoder underrun reporting state
14756 * within the crtc. With crtc for pipe A housing the underrun
14757 * reporting state for PCH transcoder A, crtc for pipe B housing
14758 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
14759 * and marking underrun reporting as disabled for the non-existing
14760 * PCH transcoders B and C would prevent enabling the south
14761 * error interrupt (see cpt_can_enable_serr_int()).
14762 */
14763 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
14764 crtc->pch_fifo_underrun_disabled = true;
14765 }
14766 }
14767
14768 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14769 {
14770 struct intel_connector *connector;
14771
14772 /* We need to check both for a crtc link (meaning that the
14773 * encoder is active and trying to read from a pipe) and the
14774 * pipe itself being active. */
14775 bool has_active_crtc = encoder->base.crtc &&
14776 to_intel_crtc(encoder->base.crtc)->active;
14777
14778 connector = intel_encoder_find_connector(encoder);
14779 if (connector && !has_active_crtc) {
14780 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14781 encoder->base.base.id,
14782 encoder->base.name);
14783
14784 /* Connector is active, but has no active pipe. This is
14785 * fallout from our resume register restoring. Disable
14786 * the encoder manually again. */
14787 if (encoder->base.crtc) {
14788 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
14789
14790 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14791 encoder->base.base.id,
14792 encoder->base.name);
14793 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14794 if (encoder->post_disable)
14795 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14796 }
14797 encoder->base.crtc = NULL;
14798
14799 /* Inconsistent output/port/pipe state happens presumably due to
14800 * a bug in one of the get_hw_state functions. Or someplace else
14801 * in our code, like the register restore mess on resume. Clamp
14802 * things to off as a safer default. */
14803
14804 connector->base.dpms = DRM_MODE_DPMS_OFF;
14805 connector->base.encoder = NULL;
14806 }
14807 /* Enabled encoders without active connectors will be fixed in
14808 * the crtc fixup. */
14809 }
14810
14811 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
14812 {
14813 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14814
14815 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14816 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14817 i915_disable_vga(dev_priv);
14818 }
14819 }
14820
14821 void i915_redisable_vga(struct drm_i915_private *dev_priv)
14822 {
14823 /* This function can be called both from intel_modeset_setup_hw_state or
14824 * at a very early point in our resume sequence, where the power well
14825 * structures are not yet restored. Since this function is at a very
14826 * paranoid "someone might have enabled VGA while we were not looking"
14827 * level, just check if the power well is enabled instead of trying to
14828 * follow the "don't touch the power well if we don't need it" policy
14829 * the rest of the driver uses. */
14830 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
14831 return;
14832
14833 i915_redisable_vga_power_on(dev_priv);
14834
14835 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
14836 }
14837
14838 static bool primary_get_hw_state(struct intel_plane *plane)
14839 {
14840 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
14841
14842 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
14843 }
14844
14845 /* FIXME read out full plane state for all planes */
14846 static void readout_plane_state(struct intel_crtc *crtc)
14847 {
14848 struct intel_plane *primary = to_intel_plane(crtc->base.primary);
14849 bool visible;
14850
14851 visible = crtc->active && primary_get_hw_state(primary);
14852
14853 intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
14854 to_intel_plane_state(primary->base.state),
14855 visible);
14856 }
14857
14858 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14859 {
14860 struct drm_i915_private *dev_priv = to_i915(dev);
14861 enum pipe pipe;
14862 struct intel_crtc *crtc;
14863 struct intel_encoder *encoder;
14864 struct intel_connector *connector;
14865 struct drm_connector_list_iter conn_iter;
14866 int i;
14867
14868 dev_priv->active_crtcs = 0;
14869
14870 for_each_intel_crtc(dev, crtc) {
14871 struct intel_crtc_state *crtc_state =
14872 to_intel_crtc_state(crtc->base.state);
14873
14874 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
14875 memset(crtc_state, 0, sizeof(*crtc_state));
14876 crtc_state->base.crtc = &crtc->base;
14877
14878 crtc_state->base.active = crtc_state->base.enable =
14879 dev_priv->display.get_pipe_config(crtc, crtc_state);
14880
14881 crtc->base.enabled = crtc_state->base.enable;
14882 crtc->active = crtc_state->base.active;
14883
14884 if (crtc_state->base.active)
14885 dev_priv->active_crtcs |= 1 << crtc->pipe;
14886
14887 readout_plane_state(crtc);
14888
14889 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
14890 crtc->base.base.id, crtc->base.name,
14891 enableddisabled(crtc_state->base.active));
14892 }
14893
14894 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14895 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14896
14897 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
14898 &pll->state.hw_state);
14899 pll->state.crtc_mask = 0;
14900 for_each_intel_crtc(dev, crtc) {
14901 struct intel_crtc_state *crtc_state =
14902 to_intel_crtc_state(crtc->base.state);
14903
14904 if (crtc_state->base.active &&
14905 crtc_state->shared_dpll == pll)
14906 pll->state.crtc_mask |= 1 << crtc->pipe;
14907 }
14908 pll->active_mask = pll->state.crtc_mask;
14909
14910 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14911 pll->name, pll->state.crtc_mask, pll->on);
14912 }
14913
14914 for_each_intel_encoder(dev, encoder) {
14915 pipe = 0;
14916
14917 if (encoder->get_hw_state(encoder, &pipe)) {
14918 struct intel_crtc_state *crtc_state;
14919
14920 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
14921 crtc_state = to_intel_crtc_state(crtc->base.state);
14922
14923 encoder->base.crtc = &crtc->base;
14924 crtc_state->output_types |= 1 << encoder->type;
14925 encoder->get_config(encoder, crtc_state);
14926 } else {
14927 encoder->base.crtc = NULL;
14928 }
14929
14930 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14931 encoder->base.base.id, encoder->base.name,
14932 enableddisabled(encoder->base.crtc),
14933 pipe_name(pipe));
14934 }
14935
14936 drm_connector_list_iter_begin(dev, &conn_iter);
14937 for_each_intel_connector_iter(connector, &conn_iter) {
14938 if (connector->get_hw_state(connector)) {
14939 connector->base.dpms = DRM_MODE_DPMS_ON;
14940
14941 encoder = connector->encoder;
14942 connector->base.encoder = &encoder->base;
14943
14944 if (encoder->base.crtc &&
14945 encoder->base.crtc->state->active) {
14946 /*
14947 * This has to be done during hardware readout
14948 * because anything calling .crtc_disable may
14949 * rely on the connector_mask being accurate.
14950 */
14951 encoder->base.crtc->state->connector_mask |=
14952 1 << drm_connector_index(&connector->base);
14953 encoder->base.crtc->state->encoder_mask |=
14954 1 << drm_encoder_index(&encoder->base);
14955 }
14956
14957 } else {
14958 connector->base.dpms = DRM_MODE_DPMS_OFF;
14959 connector->base.encoder = NULL;
14960 }
14961 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14962 connector->base.base.id, connector->base.name,
14963 enableddisabled(connector->base.encoder));
14964 }
14965 drm_connector_list_iter_end(&conn_iter);
14966
14967 for_each_intel_crtc(dev, crtc) {
14968 struct intel_crtc_state *crtc_state =
14969 to_intel_crtc_state(crtc->base.state);
14970 int pixclk = 0;
14971
14972 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
14973 if (crtc_state->base.active) {
14974 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
14975 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
14976 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
14977
14978 /*
14979 * The initial mode needs to be set in order to keep
14980 * the atomic core happy. It wants a valid mode if the
14981 * crtc's enabled, so we do the above call.
14982 *
14983 * But we don't set all the derived state fully, hence
14984 * set a flag to indicate that a full recalculation is
14985 * needed on the next commit.
14986 */
14987 crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
14988
14989 intel_crtc_compute_pixel_rate(crtc_state);
14990
14991 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) ||
14992 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14993 pixclk = crtc_state->pixel_rate;
14994 else
14995 WARN_ON(dev_priv->display.modeset_calc_cdclk);
14996
14997 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
14998 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
14999 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15000
15001 drm_calc_timestamping_constants(&crtc->base,
15002 &crtc_state->base.adjusted_mode);
15003 update_scanline_offset(crtc);
15004 }
15005
15006 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15007
15008 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15009 }
15010 }
15011
15012 static void
15013 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15014 {
15015 struct intel_encoder *encoder;
15016
15017 for_each_intel_encoder(&dev_priv->drm, encoder) {
15018 u64 get_domains;
15019 enum intel_display_power_domain domain;
15020
15021 if (!encoder->get_power_domains)
15022 continue;
15023
15024 get_domains = encoder->get_power_domains(encoder);
15025 for_each_power_domain(domain, get_domains)
15026 intel_display_power_get(dev_priv, domain);
15027 }
15028 }
15029
15030 /* Scan out the current hw modeset state,
15031 * and sanitizes it to the current state
15032 */
15033 static void
15034 intel_modeset_setup_hw_state(struct drm_device *dev,
15035 struct drm_modeset_acquire_ctx *ctx)
15036 {
15037 struct drm_i915_private *dev_priv = to_i915(dev);
15038 enum pipe pipe;
15039 struct intel_crtc *crtc;
15040 struct intel_encoder *encoder;
15041 int i;
15042
15043 intel_modeset_readout_hw_state(dev);
15044
15045 /* HW state is read out, now we need to sanitize this mess. */
15046 get_encoder_power_domains(dev_priv);
15047
15048 for_each_intel_encoder(dev, encoder) {
15049 intel_sanitize_encoder(encoder);
15050 }
15051
15052 for_each_pipe(dev_priv, pipe) {
15053 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15054
15055 intel_sanitize_crtc(crtc, ctx);
15056 intel_dump_pipe_config(crtc, crtc->config,
15057 "[setup_hw_state]");
15058 }
15059
15060 intel_modeset_update_connector_atomic_state(dev);
15061
15062 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15063 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15064
15065 if (!pll->on || pll->active_mask)
15066 continue;
15067
15068 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15069
15070 pll->funcs.disable(dev_priv, pll);
15071 pll->on = false;
15072 }
15073
15074 if (IS_G4X(dev_priv)) {
15075 g4x_wm_get_hw_state(dev);
15076 g4x_wm_sanitize(dev_priv);
15077 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15078 vlv_wm_get_hw_state(dev);
15079 vlv_wm_sanitize(dev_priv);
15080 } else if (INTEL_GEN(dev_priv) >= 9) {
15081 skl_wm_get_hw_state(dev);
15082 } else if (HAS_PCH_SPLIT(dev_priv)) {
15083 ilk_wm_get_hw_state(dev);
15084 }
15085
15086 for_each_intel_crtc(dev, crtc) {
15087 u64 put_domains;
15088
15089 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15090 if (WARN_ON(put_domains))
15091 modeset_put_power_domains(dev_priv, put_domains);
15092 }
15093 intel_display_set_init_power(dev_priv, false);
15094
15095 intel_power_domains_verify_state(dev_priv);
15096
15097 intel_fbc_init_pipe_state(dev_priv);
15098 }
15099
15100 void intel_display_resume(struct drm_device *dev)
15101 {
15102 struct drm_i915_private *dev_priv = to_i915(dev);
15103 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15104 struct drm_modeset_acquire_ctx ctx;
15105 int ret;
15106
15107 dev_priv->modeset_restore_state = NULL;
15108 if (state)
15109 state->acquire_ctx = &ctx;
15110
15111 drm_modeset_acquire_init(&ctx, 0);
15112
15113 while (1) {
15114 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15115 if (ret != -EDEADLK)
15116 break;
15117
15118 drm_modeset_backoff(&ctx);
15119 }
15120
15121 if (!ret)
15122 ret = __intel_display_resume(dev, state, &ctx);
15123
15124 drm_modeset_drop_locks(&ctx);
15125 drm_modeset_acquire_fini(&ctx);
15126
15127 if (ret)
15128 DRM_ERROR("Restoring old state failed with %i\n", ret);
15129 if (state)
15130 drm_atomic_state_put(state);
15131 }
15132
15133 void intel_modeset_gem_init(struct drm_device *dev)
15134 {
15135 struct drm_i915_private *dev_priv = to_i915(dev);
15136
15137 intel_init_gt_powersave(dev_priv);
15138
15139 intel_setup_overlay(dev_priv);
15140 }
15141
15142 int intel_connector_register(struct drm_connector *connector)
15143 {
15144 struct intel_connector *intel_connector = to_intel_connector(connector);
15145 int ret;
15146
15147 ret = intel_backlight_device_register(intel_connector);
15148 if (ret)
15149 goto err;
15150
15151 return 0;
15152
15153 err:
15154 return ret;
15155 }
15156
15157 void intel_connector_unregister(struct drm_connector *connector)
15158 {
15159 struct intel_connector *intel_connector = to_intel_connector(connector);
15160
15161 intel_backlight_device_unregister(intel_connector);
15162 intel_panel_destroy_backlight(connector);
15163 }
15164
15165 void intel_modeset_cleanup(struct drm_device *dev)
15166 {
15167 struct drm_i915_private *dev_priv = to_i915(dev);
15168
15169 flush_work(&dev_priv->atomic_helper.free_work);
15170 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15171
15172 intel_disable_gt_powersave(dev_priv);
15173
15174 /*
15175 * Interrupts and polling as the first thing to avoid creating havoc.
15176 * Too much stuff here (turning of connectors, ...) would
15177 * experience fancy races otherwise.
15178 */
15179 intel_irq_uninstall(dev_priv);
15180
15181 /*
15182 * Due to the hpd irq storm handling the hotplug work can re-arm the
15183 * poll handlers. Hence disable polling after hpd handling is shut down.
15184 */
15185 drm_kms_helper_poll_fini(dev);
15186
15187 /* poll work can call into fbdev, hence clean that up afterwards */
15188 intel_fbdev_fini(dev_priv);
15189
15190 intel_unregister_dsm_handler();
15191
15192 intel_fbc_global_disable(dev_priv);
15193
15194 /* flush any delayed tasks or pending work */
15195 flush_scheduled_work();
15196
15197 drm_mode_config_cleanup(dev);
15198
15199 intel_cleanup_overlay(dev_priv);
15200
15201 intel_cleanup_gt_powersave(dev_priv);
15202
15203 intel_teardown_gmbus(dev_priv);
15204 }
15205
15206 void intel_connector_attach_encoder(struct intel_connector *connector,
15207 struct intel_encoder *encoder)
15208 {
15209 connector->encoder = encoder;
15210 drm_mode_connector_attach_encoder(&connector->base,
15211 &encoder->base);
15212 }
15213
15214 /*
15215 * set vga decode state - true == enable VGA decode
15216 */
15217 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15218 {
15219 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15220 u16 gmch_ctrl;
15221
15222 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15223 DRM_ERROR("failed to read control word\n");
15224 return -EIO;
15225 }
15226
15227 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15228 return 0;
15229
15230 if (state)
15231 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15232 else
15233 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15234
15235 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15236 DRM_ERROR("failed to write control word\n");
15237 return -EIO;
15238 }
15239
15240 return 0;
15241 }
15242
15243 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15244
15245 struct intel_display_error_state {
15246
15247 u32 power_well_driver;
15248
15249 int num_transcoders;
15250
15251 struct intel_cursor_error_state {
15252 u32 control;
15253 u32 position;
15254 u32 base;
15255 u32 size;
15256 } cursor[I915_MAX_PIPES];
15257
15258 struct intel_pipe_error_state {
15259 bool power_domain_on;
15260 u32 source;
15261 u32 stat;
15262 } pipe[I915_MAX_PIPES];
15263
15264 struct intel_plane_error_state {
15265 u32 control;
15266 u32 stride;
15267 u32 size;
15268 u32 pos;
15269 u32 addr;
15270 u32 surface;
15271 u32 tile_offset;
15272 } plane[I915_MAX_PIPES];
15273
15274 struct intel_transcoder_error_state {
15275 bool power_domain_on;
15276 enum transcoder cpu_transcoder;
15277
15278 u32 conf;
15279
15280 u32 htotal;
15281 u32 hblank;
15282 u32 hsync;
15283 u32 vtotal;
15284 u32 vblank;
15285 u32 vsync;
15286 } transcoder[4];
15287 };
15288
15289 struct intel_display_error_state *
15290 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15291 {
15292 struct intel_display_error_state *error;
15293 int transcoders[] = {
15294 TRANSCODER_A,
15295 TRANSCODER_B,
15296 TRANSCODER_C,
15297 TRANSCODER_EDP,
15298 };
15299 int i;
15300
15301 if (INTEL_INFO(dev_priv)->num_pipes == 0)
15302 return NULL;
15303
15304 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15305 if (error == NULL)
15306 return NULL;
15307
15308 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15309 error->power_well_driver =
15310 I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL));
15311
15312 for_each_pipe(dev_priv, i) {
15313 error->pipe[i].power_domain_on =
15314 __intel_display_power_is_enabled(dev_priv,
15315 POWER_DOMAIN_PIPE(i));
15316 if (!error->pipe[i].power_domain_on)
15317 continue;
15318
15319 error->cursor[i].control = I915_READ(CURCNTR(i));
15320 error->cursor[i].position = I915_READ(CURPOS(i));
15321 error->cursor[i].base = I915_READ(CURBASE(i));
15322
15323 error->plane[i].control = I915_READ(DSPCNTR(i));
15324 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15325 if (INTEL_GEN(dev_priv) <= 3) {
15326 error->plane[i].size = I915_READ(DSPSIZE(i));
15327 error->plane[i].pos = I915_READ(DSPPOS(i));
15328 }
15329 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15330 error->plane[i].addr = I915_READ(DSPADDR(i));
15331 if (INTEL_GEN(dev_priv) >= 4) {
15332 error->plane[i].surface = I915_READ(DSPSURF(i));
15333 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15334 }
15335
15336 error->pipe[i].source = I915_READ(PIPESRC(i));
15337
15338 if (HAS_GMCH_DISPLAY(dev_priv))
15339 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15340 }
15341
15342 /* Note: this does not include DSI transcoders. */
15343 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15344 if (HAS_DDI(dev_priv))
15345 error->num_transcoders++; /* Account for eDP. */
15346
15347 for (i = 0; i < error->num_transcoders; i++) {
15348 enum transcoder cpu_transcoder = transcoders[i];
15349
15350 error->transcoder[i].power_domain_on =
15351 __intel_display_power_is_enabled(dev_priv,
15352 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15353 if (!error->transcoder[i].power_domain_on)
15354 continue;
15355
15356 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15357
15358 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15359 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15360 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15361 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15362 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15363 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15364 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15365 }
15366
15367 return error;
15368 }
15369
15370 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15371
15372 void
15373 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15374 struct intel_display_error_state *error)
15375 {
15376 struct drm_i915_private *dev_priv = m->i915;
15377 int i;
15378
15379 if (!error)
15380 return;
15381
15382 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15383 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15384 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15385 error->power_well_driver);
15386 for_each_pipe(dev_priv, i) {
15387 err_printf(m, "Pipe [%d]:\n", i);
15388 err_printf(m, " Power: %s\n",
15389 onoff(error->pipe[i].power_domain_on));
15390 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15391 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15392
15393 err_printf(m, "Plane [%d]:\n", i);
15394 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15395 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15396 if (INTEL_GEN(dev_priv) <= 3) {
15397 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15398 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15399 }
15400 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15401 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15402 if (INTEL_GEN(dev_priv) >= 4) {
15403 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15404 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15405 }
15406
15407 err_printf(m, "Cursor [%d]:\n", i);
15408 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15409 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15410 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15411 }
15412
15413 for (i = 0; i < error->num_transcoders; i++) {
15414 err_printf(m, "CPU transcoder: %s\n",
15415 transcoder_name(error->transcoder[i].cpu_transcoder));
15416 err_printf(m, " Power: %s\n",
15417 onoff(error->transcoder[i].power_domain_on));
15418 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15419 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15420 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15421 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15422 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15423 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15424 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15425 }
15426 }
15427
15428 #endif
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