]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/gpu/drm/i915/intel_display.c
projects / mirror_ubuntu-artful-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/i915: Drop schedule_back from psr_exit
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
78
79 static void intel_increase_pllclock(struct drm_crtc *crtc);
80 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
81
82 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
83 struct intel_crtc_config *pipe_config);
84 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
85 struct intel_crtc_config *pipe_config);
86
87 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
88 int x, int y, struct drm_framebuffer *old_fb);
89 static int intel_framebuffer_init(struct drm_device *dev,
90 struct intel_framebuffer *ifb,
91 struct drm_mode_fb_cmd2 *mode_cmd,
92 struct drm_i915_gem_object *obj);
93 static void intel_dp_set_m_n(struct intel_crtc *crtc);
94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
97 struct intel_link_m_n *m_n);
98 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
99 static void haswell_set_pipeconf(struct drm_crtc *crtc);
100 static void intel_set_pipe_csc(struct drm_crtc *crtc);
101 static void vlv_prepare_pll(struct intel_crtc *crtc);
102
103 typedef struct {
104 int min, max;
105 } intel_range_t;
106
107 typedef struct {
108 int dot_limit;
109 int p2_slow, p2_fast;
110 } intel_p2_t;
111
112 typedef struct intel_limit intel_limit_t;
113 struct intel_limit {
114 intel_range_t dot, vco, n, m, m1, m2, p, p1;
115 intel_p2_t p2;
116 };
117
118 int
119 intel_pch_rawclk(struct drm_device *dev)
120 {
121 struct drm_i915_private *dev_priv = dev->dev_private;
122
123 WARN_ON(!HAS_PCH_SPLIT(dev));
124
125 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
126 }
127
128 static inline u32 /* units of 100MHz */
129 intel_fdi_link_freq(struct drm_device *dev)
130 {
131 if (IS_GEN5(dev)) {
132 struct drm_i915_private *dev_priv = dev->dev_private;
133 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
134 } else
135 return 27;
136 }
137
138 static const intel_limit_t intel_limits_i8xx_dac = {
139 .dot = { .min = 25000, .max = 350000 },
140 .vco = { .min = 908000, .max = 1512000 },
141 .n = { .min = 2, .max = 16 },
142 .m = { .min = 96, .max = 140 },
143 .m1 = { .min = 18, .max = 26 },
144 .m2 = { .min = 6, .max = 16 },
145 .p = { .min = 4, .max = 128 },
146 .p1 = { .min = 2, .max = 33 },
147 .p2 = { .dot_limit = 165000,
148 .p2_slow = 4, .p2_fast = 2 },
149 };
150
151 static const intel_limit_t intel_limits_i8xx_dvo = {
152 .dot = { .min = 25000, .max = 350000 },
153 .vco = { .min = 908000, .max = 1512000 },
154 .n = { .min = 2, .max = 16 },
155 .m = { .min = 96, .max = 140 },
156 .m1 = { .min = 18, .max = 26 },
157 .m2 = { .min = 6, .max = 16 },
158 .p = { .min = 4, .max = 128 },
159 .p1 = { .min = 2, .max = 33 },
160 .p2 = { .dot_limit = 165000,
161 .p2_slow = 4, .p2_fast = 4 },
162 };
163
164 static const intel_limit_t intel_limits_i8xx_lvds = {
165 .dot = { .min = 25000, .max = 350000 },
166 .vco = { .min = 908000, .max = 1512000 },
167 .n = { .min = 2, .max = 16 },
168 .m = { .min = 96, .max = 140 },
169 .m1 = { .min = 18, .max = 26 },
170 .m2 = { .min = 6, .max = 16 },
171 .p = { .min = 4, .max = 128 },
172 .p1 = { .min = 1, .max = 6 },
173 .p2 = { .dot_limit = 165000,
174 .p2_slow = 14, .p2_fast = 7 },
175 };
176
177 static const intel_limit_t intel_limits_i9xx_sdvo = {
178 .dot = { .min = 20000, .max = 400000 },
179 .vco = { .min = 1400000, .max = 2800000 },
180 .n = { .min = 1, .max = 6 },
181 .m = { .min = 70, .max = 120 },
182 .m1 = { .min = 8, .max = 18 },
183 .m2 = { .min = 3, .max = 7 },
184 .p = { .min = 5, .max = 80 },
185 .p1 = { .min = 1, .max = 8 },
186 .p2 = { .dot_limit = 200000,
187 .p2_slow = 10, .p2_fast = 5 },
188 };
189
190 static const intel_limit_t intel_limits_i9xx_lvds = {
191 .dot = { .min = 20000, .max = 400000 },
192 .vco = { .min = 1400000, .max = 2800000 },
193 .n = { .min = 1, .max = 6 },
194 .m = { .min = 70, .max = 120 },
195 .m1 = { .min = 8, .max = 18 },
196 .m2 = { .min = 3, .max = 7 },
197 .p = { .min = 7, .max = 98 },
198 .p1 = { .min = 1, .max = 8 },
199 .p2 = { .dot_limit = 112000,
200 .p2_slow = 14, .p2_fast = 7 },
201 };
202
203
204 static const intel_limit_t intel_limits_g4x_sdvo = {
205 .dot = { .min = 25000, .max = 270000 },
206 .vco = { .min = 1750000, .max = 3500000},
207 .n = { .min = 1, .max = 4 },
208 .m = { .min = 104, .max = 138 },
209 .m1 = { .min = 17, .max = 23 },
210 .m2 = { .min = 5, .max = 11 },
211 .p = { .min = 10, .max = 30 },
212 .p1 = { .min = 1, .max = 3},
213 .p2 = { .dot_limit = 270000,
214 .p2_slow = 10,
215 .p2_fast = 10
216 },
217 };
218
219 static const intel_limit_t intel_limits_g4x_hdmi = {
220 .dot = { .min = 22000, .max = 400000 },
221 .vco = { .min = 1750000, .max = 3500000},
222 .n = { .min = 1, .max = 4 },
223 .m = { .min = 104, .max = 138 },
224 .m1 = { .min = 16, .max = 23 },
225 .m2 = { .min = 5, .max = 11 },
226 .p = { .min = 5, .max = 80 },
227 .p1 = { .min = 1, .max = 8},
228 .p2 = { .dot_limit = 165000,
229 .p2_slow = 10, .p2_fast = 5 },
230 };
231
232 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
233 .dot = { .min = 20000, .max = 115000 },
234 .vco = { .min = 1750000, .max = 3500000 },
235 .n = { .min = 1, .max = 3 },
236 .m = { .min = 104, .max = 138 },
237 .m1 = { .min = 17, .max = 23 },
238 .m2 = { .min = 5, .max = 11 },
239 .p = { .min = 28, .max = 112 },
240 .p1 = { .min = 2, .max = 8 },
241 .p2 = { .dot_limit = 0,
242 .p2_slow = 14, .p2_fast = 14
243 },
244 };
245
246 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
247 .dot = { .min = 80000, .max = 224000 },
248 .vco = { .min = 1750000, .max = 3500000 },
249 .n = { .min = 1, .max = 3 },
250 .m = { .min = 104, .max = 138 },
251 .m1 = { .min = 17, .max = 23 },
252 .m2 = { .min = 5, .max = 11 },
253 .p = { .min = 14, .max = 42 },
254 .p1 = { .min = 2, .max = 6 },
255 .p2 = { .dot_limit = 0,
256 .p2_slow = 7, .p2_fast = 7
257 },
258 };
259
260 static const intel_limit_t intel_limits_pineview_sdvo = {
261 .dot = { .min = 20000, .max = 400000},
262 .vco = { .min = 1700000, .max = 3500000 },
263 /* Pineview's Ncounter is a ring counter */
264 .n = { .min = 3, .max = 6 },
265 .m = { .min = 2, .max = 256 },
266 /* Pineview only has one combined m divider, which we treat as m2. */
267 .m1 = { .min = 0, .max = 0 },
268 .m2 = { .min = 0, .max = 254 },
269 .p = { .min = 5, .max = 80 },
270 .p1 = { .min = 1, .max = 8 },
271 .p2 = { .dot_limit = 200000,
272 .p2_slow = 10, .p2_fast = 5 },
273 };
274
275 static const intel_limit_t intel_limits_pineview_lvds = {
276 .dot = { .min = 20000, .max = 400000 },
277 .vco = { .min = 1700000, .max = 3500000 },
278 .n = { .min = 3, .max = 6 },
279 .m = { .min = 2, .max = 256 },
280 .m1 = { .min = 0, .max = 0 },
281 .m2 = { .min = 0, .max = 254 },
282 .p = { .min = 7, .max = 112 },
283 .p1 = { .min = 1, .max = 8 },
284 .p2 = { .dot_limit = 112000,
285 .p2_slow = 14, .p2_fast = 14 },
286 };
287
288 /* Ironlake / Sandybridge
289 *
290 * We calculate clock using (register_value + 2) for N/M1/M2, so here
291 * the range value for them is (actual_value - 2).
292 */
293 static const intel_limit_t intel_limits_ironlake_dac = {
294 .dot = { .min = 25000, .max = 350000 },
295 .vco = { .min = 1760000, .max = 3510000 },
296 .n = { .min = 1, .max = 5 },
297 .m = { .min = 79, .max = 127 },
298 .m1 = { .min = 12, .max = 22 },
299 .m2 = { .min = 5, .max = 9 },
300 .p = { .min = 5, .max = 80 },
301 .p1 = { .min = 1, .max = 8 },
302 .p2 = { .dot_limit = 225000,
303 .p2_slow = 10, .p2_fast = 5 },
304 };
305
306 static const intel_limit_t intel_limits_ironlake_single_lvds = {
307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 118 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 28, .max = 112 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 14, .p2_fast = 14 },
317 };
318
319 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
320 .dot = { .min = 25000, .max = 350000 },
321 .vco = { .min = 1760000, .max = 3510000 },
322 .n = { .min = 1, .max = 3 },
323 .m = { .min = 79, .max = 127 },
324 .m1 = { .min = 12, .max = 22 },
325 .m2 = { .min = 5, .max = 9 },
326 .p = { .min = 14, .max = 56 },
327 .p1 = { .min = 2, .max = 8 },
328 .p2 = { .dot_limit = 225000,
329 .p2_slow = 7, .p2_fast = 7 },
330 };
331
332 /* LVDS 100mhz refclk limits. */
333 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 2 },
337 .m = { .min = 79, .max = 126 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 28, .max = 112 },
341 .p1 = { .min = 2, .max = 8 },
342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 14, .p2_fast = 14 },
344 };
345
346 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
347 .dot = { .min = 25000, .max = 350000 },
348 .vco = { .min = 1760000, .max = 3510000 },
349 .n = { .min = 1, .max = 3 },
350 .m = { .min = 79, .max = 126 },
351 .m1 = { .min = 12, .max = 22 },
352 .m2 = { .min = 5, .max = 9 },
353 .p = { .min = 14, .max = 42 },
354 .p1 = { .min = 2, .max = 6 },
355 .p2 = { .dot_limit = 225000,
356 .p2_slow = 7, .p2_fast = 7 },
357 };
358
359 static const intel_limit_t intel_limits_vlv = {
360 /*
361 * These are the data rate limits (measured in fast clocks)
362 * since those are the strictest limits we have. The fast
363 * clock and actual rate limits are more relaxed, so checking
364 * them would make no difference.
365 */
366 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
367 .vco = { .min = 4000000, .max = 6000000 },
368 .n = { .min = 1, .max = 7 },
369 .m1 = { .min = 2, .max = 3 },
370 .m2 = { .min = 11, .max = 156 },
371 .p1 = { .min = 2, .max = 3 },
372 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
373 };
374
375 static const intel_limit_t intel_limits_chv = {
376 /*
377 * These are the data rate limits (measured in fast clocks)
378 * since those are the strictest limits we have. The fast
379 * clock and actual rate limits are more relaxed, so checking
380 * them would make no difference.
381 */
382 .dot = { .min = 25000 * 5, .max = 540000 * 5},
383 .vco = { .min = 4860000, .max = 6700000 },
384 .n = { .min = 1, .max = 1 },
385 .m1 = { .min = 2, .max = 2 },
386 .m2 = { .min = 24 << 22, .max = 175 << 22 },
387 .p1 = { .min = 2, .max = 4 },
388 .p2 = { .p2_slow = 1, .p2_fast = 14 },
389 };
390
391 static void vlv_clock(int refclk, intel_clock_t *clock)
392 {
393 clock->m = clock->m1 * clock->m2;
394 clock->p = clock->p1 * clock->p2;
395 if (WARN_ON(clock->n == 0 || clock->p == 0))
396 return;
397 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
398 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
399 }
400
401 /**
402 * Returns whether any output on the specified pipe is of the specified type
403 */
404 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
405 {
406 struct drm_device *dev = crtc->dev;
407 struct intel_encoder *encoder;
408
409 for_each_encoder_on_crtc(dev, crtc, encoder)
410 if (encoder->type == type)
411 return true;
412
413 return false;
414 }
415
416 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
417 int refclk)
418 {
419 struct drm_device *dev = crtc->dev;
420 const intel_limit_t *limit;
421
422 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
423 if (intel_is_dual_link_lvds(dev)) {
424 if (refclk == 100000)
425 limit = &intel_limits_ironlake_dual_lvds_100m;
426 else
427 limit = &intel_limits_ironlake_dual_lvds;
428 } else {
429 if (refclk == 100000)
430 limit = &intel_limits_ironlake_single_lvds_100m;
431 else
432 limit = &intel_limits_ironlake_single_lvds;
433 }
434 } else
435 limit = &intel_limits_ironlake_dac;
436
437 return limit;
438 }
439
440 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
441 {
442 struct drm_device *dev = crtc->dev;
443 const intel_limit_t *limit;
444
445 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
446 if (intel_is_dual_link_lvds(dev))
447 limit = &intel_limits_g4x_dual_channel_lvds;
448 else
449 limit = &intel_limits_g4x_single_channel_lvds;
450 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
451 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
452 limit = &intel_limits_g4x_hdmi;
453 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
454 limit = &intel_limits_g4x_sdvo;
455 } else /* The option is for other outputs */
456 limit = &intel_limits_i9xx_sdvo;
457
458 return limit;
459 }
460
461 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
462 {
463 struct drm_device *dev = crtc->dev;
464 const intel_limit_t *limit;
465
466 if (HAS_PCH_SPLIT(dev))
467 limit = intel_ironlake_limit(crtc, refclk);
468 else if (IS_G4X(dev)) {
469 limit = intel_g4x_limit(crtc);
470 } else if (IS_PINEVIEW(dev)) {
471 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
472 limit = &intel_limits_pineview_lvds;
473 else
474 limit = &intel_limits_pineview_sdvo;
475 } else if (IS_CHERRYVIEW(dev)) {
476 limit = &intel_limits_chv;
477 } else if (IS_VALLEYVIEW(dev)) {
478 limit = &intel_limits_vlv;
479 } else if (!IS_GEN2(dev)) {
480 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
481 limit = &intel_limits_i9xx_lvds;
482 else
483 limit = &intel_limits_i9xx_sdvo;
484 } else {
485 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
486 limit = &intel_limits_i8xx_lvds;
487 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
488 limit = &intel_limits_i8xx_dvo;
489 else
490 limit = &intel_limits_i8xx_dac;
491 }
492 return limit;
493 }
494
495 /* m1 is reserved as 0 in Pineview, n is a ring counter */
496 static void pineview_clock(int refclk, intel_clock_t *clock)
497 {
498 clock->m = clock->m2 + 2;
499 clock->p = clock->p1 * clock->p2;
500 if (WARN_ON(clock->n == 0 || clock->p == 0))
501 return;
502 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
503 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
504 }
505
506 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
507 {
508 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
509 }
510
511 static void i9xx_clock(int refclk, intel_clock_t *clock)
512 {
513 clock->m = i9xx_dpll_compute_m(clock);
514 clock->p = clock->p1 * clock->p2;
515 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
516 return;
517 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
518 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
519 }
520
521 static void chv_clock(int refclk, intel_clock_t *clock)
522 {
523 clock->m = clock->m1 * clock->m2;
524 clock->p = clock->p1 * clock->p2;
525 if (WARN_ON(clock->n == 0 || clock->p == 0))
526 return;
527 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
528 clock->n << 22);
529 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
530 }
531
532 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
533 /**
534 * Returns whether the given set of divisors are valid for a given refclk with
535 * the given connectors.
536 */
537
538 static bool intel_PLL_is_valid(struct drm_device *dev,
539 const intel_limit_t *limit,
540 const intel_clock_t *clock)
541 {
542 if (clock->n < limit->n.min || limit->n.max < clock->n)
543 INTELPllInvalid("n out of range\n");
544 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
545 INTELPllInvalid("p1 out of range\n");
546 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
547 INTELPllInvalid("m2 out of range\n");
548 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
549 INTELPllInvalid("m1 out of range\n");
550
551 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
552 if (clock->m1 <= clock->m2)
553 INTELPllInvalid("m1 <= m2\n");
554
555 if (!IS_VALLEYVIEW(dev)) {
556 if (clock->p < limit->p.min || limit->p.max < clock->p)
557 INTELPllInvalid("p out of range\n");
558 if (clock->m < limit->m.min || limit->m.max < clock->m)
559 INTELPllInvalid("m out of range\n");
560 }
561
562 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
563 INTELPllInvalid("vco out of range\n");
564 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
565 * connector, etc., rather than just a single range.
566 */
567 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
568 INTELPllInvalid("dot out of range\n");
569
570 return true;
571 }
572
573 static bool
574 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
575 int target, int refclk, intel_clock_t *match_clock,
576 intel_clock_t *best_clock)
577 {
578 struct drm_device *dev = crtc->dev;
579 intel_clock_t clock;
580 int err = target;
581
582 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
583 /*
584 * For LVDS just rely on its current settings for dual-channel.
585 * We haven't figured out how to reliably set up different
586 * single/dual channel state, if we even can.
587 */
588 if (intel_is_dual_link_lvds(dev))
589 clock.p2 = limit->p2.p2_fast;
590 else
591 clock.p2 = limit->p2.p2_slow;
592 } else {
593 if (target < limit->p2.dot_limit)
594 clock.p2 = limit->p2.p2_slow;
595 else
596 clock.p2 = limit->p2.p2_fast;
597 }
598
599 memset(best_clock, 0, sizeof(*best_clock));
600
601 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
602 clock.m1++) {
603 for (clock.m2 = limit->m2.min;
604 clock.m2 <= limit->m2.max; clock.m2++) {
605 if (clock.m2 >= clock.m1)
606 break;
607 for (clock.n = limit->n.min;
608 clock.n <= limit->n.max; clock.n++) {
609 for (clock.p1 = limit->p1.min;
610 clock.p1 <= limit->p1.max; clock.p1++) {
611 int this_err;
612
613 i9xx_clock(refclk, &clock);
614 if (!intel_PLL_is_valid(dev, limit,
615 &clock))
616 continue;
617 if (match_clock &&
618 clock.p != match_clock->p)
619 continue;
620
621 this_err = abs(clock.dot - target);
622 if (this_err < err) {
623 *best_clock = clock;
624 err = this_err;
625 }
626 }
627 }
628 }
629 }
630
631 return (err != target);
632 }
633
634 static bool
635 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
636 int target, int refclk, intel_clock_t *match_clock,
637 intel_clock_t *best_clock)
638 {
639 struct drm_device *dev = crtc->dev;
640 intel_clock_t clock;
641 int err = target;
642
643 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
644 /*
645 * For LVDS just rely on its current settings for dual-channel.
646 * We haven't figured out how to reliably set up different
647 * single/dual channel state, if we even can.
648 */
649 if (intel_is_dual_link_lvds(dev))
650 clock.p2 = limit->p2.p2_fast;
651 else
652 clock.p2 = limit->p2.p2_slow;
653 } else {
654 if (target < limit->p2.dot_limit)
655 clock.p2 = limit->p2.p2_slow;
656 else
657 clock.p2 = limit->p2.p2_fast;
658 }
659
660 memset(best_clock, 0, sizeof(*best_clock));
661
662 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
663 clock.m1++) {
664 for (clock.m2 = limit->m2.min;
665 clock.m2 <= limit->m2.max; clock.m2++) {
666 for (clock.n = limit->n.min;
667 clock.n <= limit->n.max; clock.n++) {
668 for (clock.p1 = limit->p1.min;
669 clock.p1 <= limit->p1.max; clock.p1++) {
670 int this_err;
671
672 pineview_clock(refclk, &clock);
673 if (!intel_PLL_is_valid(dev, limit,
674 &clock))
675 continue;
676 if (match_clock &&
677 clock.p != match_clock->p)
678 continue;
679
680 this_err = abs(clock.dot - target);
681 if (this_err < err) {
682 *best_clock = clock;
683 err = this_err;
684 }
685 }
686 }
687 }
688 }
689
690 return (err != target);
691 }
692
693 static bool
694 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
695 int target, int refclk, intel_clock_t *match_clock,
696 intel_clock_t *best_clock)
697 {
698 struct drm_device *dev = crtc->dev;
699 intel_clock_t clock;
700 int max_n;
701 bool found;
702 /* approximately equals target * 0.00585 */
703 int err_most = (target >> 8) + (target >> 9);
704 found = false;
705
706 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
707 if (intel_is_dual_link_lvds(dev))
708 clock.p2 = limit->p2.p2_fast;
709 else
710 clock.p2 = limit->p2.p2_slow;
711 } else {
712 if (target < limit->p2.dot_limit)
713 clock.p2 = limit->p2.p2_slow;
714 else
715 clock.p2 = limit->p2.p2_fast;
716 }
717
718 memset(best_clock, 0, sizeof(*best_clock));
719 max_n = limit->n.max;
720 /* based on hardware requirement, prefer smaller n to precision */
721 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
722 /* based on hardware requirement, prefere larger m1,m2 */
723 for (clock.m1 = limit->m1.max;
724 clock.m1 >= limit->m1.min; clock.m1--) {
725 for (clock.m2 = limit->m2.max;
726 clock.m2 >= limit->m2.min; clock.m2--) {
727 for (clock.p1 = limit->p1.max;
728 clock.p1 >= limit->p1.min; clock.p1--) {
729 int this_err;
730
731 i9xx_clock(refclk, &clock);
732 if (!intel_PLL_is_valid(dev, limit,
733 &clock))
734 continue;
735
736 this_err = abs(clock.dot - target);
737 if (this_err < err_most) {
738 *best_clock = clock;
739 err_most = this_err;
740 max_n = clock.n;
741 found = true;
742 }
743 }
744 }
745 }
746 }
747 return found;
748 }
749
750 static bool
751 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
752 int target, int refclk, intel_clock_t *match_clock,
753 intel_clock_t *best_clock)
754 {
755 struct drm_device *dev = crtc->dev;
756 intel_clock_t clock;
757 unsigned int bestppm = 1000000;
758 /* min update 19.2 MHz */
759 int max_n = min(limit->n.max, refclk / 19200);
760 bool found = false;
761
762 target *= 5; /* fast clock */
763
764 memset(best_clock, 0, sizeof(*best_clock));
765
766 /* based on hardware requirement, prefer smaller n to precision */
767 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
768 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
769 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
770 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
771 clock.p = clock.p1 * clock.p2;
772 /* based on hardware requirement, prefer bigger m1,m2 values */
773 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
774 unsigned int ppm, diff;
775
776 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
777 refclk * clock.m1);
778
779 vlv_clock(refclk, &clock);
780
781 if (!intel_PLL_is_valid(dev, limit,
782 &clock))
783 continue;
784
785 diff = abs(clock.dot - target);
786 ppm = div_u64(1000000ULL * diff, target);
787
788 if (ppm < 100 && clock.p > best_clock->p) {
789 bestppm = 0;
790 *best_clock = clock;
791 found = true;
792 }
793
794 if (bestppm >= 10 && ppm < bestppm - 10) {
795 bestppm = ppm;
796 *best_clock = clock;
797 found = true;
798 }
799 }
800 }
801 }
802 }
803
804 return found;
805 }
806
807 static bool
808 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
809 int target, int refclk, intel_clock_t *match_clock,
810 intel_clock_t *best_clock)
811 {
812 struct drm_device *dev = crtc->dev;
813 intel_clock_t clock;
814 uint64_t m2;
815 int found = false;
816
817 memset(best_clock, 0, sizeof(*best_clock));
818
819 /*
820 * Based on hardware doc, the n always set to 1, and m1 always
821 * set to 2. If requires to support 200Mhz refclk, we need to
822 * revisit this because n may not 1 anymore.
823 */
824 clock.n = 1, clock.m1 = 2;
825 target *= 5; /* fast clock */
826
827 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
828 for (clock.p2 = limit->p2.p2_fast;
829 clock.p2 >= limit->p2.p2_slow;
830 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
831
832 clock.p = clock.p1 * clock.p2;
833
834 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
835 clock.n) << 22, refclk * clock.m1);
836
837 if (m2 > INT_MAX/clock.m1)
838 continue;
839
840 clock.m2 = m2;
841
842 chv_clock(refclk, &clock);
843
844 if (!intel_PLL_is_valid(dev, limit, &clock))
845 continue;
846
847 /* based on hardware requirement, prefer bigger p
848 */
849 if (clock.p > best_clock->p) {
850 *best_clock = clock;
851 found = true;
852 }
853 }
854 }
855
856 return found;
857 }
858
859 bool intel_crtc_active(struct drm_crtc *crtc)
860 {
861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
862
863 /* Be paranoid as we can arrive here with only partial
864 * state retrieved from the hardware during setup.
865 *
866 * We can ditch the adjusted_mode.crtc_clock check as soon
867 * as Haswell has gained clock readout/fastboot support.
868 *
869 * We can ditch the crtc->primary->fb check as soon as we can
870 * properly reconstruct framebuffers.
871 */
872 return intel_crtc->active && crtc->primary->fb &&
873 intel_crtc->config.adjusted_mode.crtc_clock;
874 }
875
876 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
877 enum pipe pipe)
878 {
879 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
881
882 return intel_crtc->config.cpu_transcoder;
883 }
884
885 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
886 {
887 struct drm_i915_private *dev_priv = dev->dev_private;
888 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
889
890 frame = I915_READ(frame_reg);
891
892 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
893 WARN(1, "vblank wait timed out\n");
894 }
895
896 /**
897 * intel_wait_for_vblank - wait for vblank on a given pipe
898 * @dev: drm device
899 * @pipe: pipe to wait for
900 *
901 * Wait for vblank to occur on a given pipe. Needed for various bits of
902 * mode setting code.
903 */
904 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
905 {
906 struct drm_i915_private *dev_priv = dev->dev_private;
907 int pipestat_reg = PIPESTAT(pipe);
908
909 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
910 g4x_wait_for_vblank(dev, pipe);
911 return;
912 }
913
914 /* Clear existing vblank status. Note this will clear any other
915 * sticky status fields as well.
916 *
917 * This races with i915_driver_irq_handler() with the result
918 * that either function could miss a vblank event. Here it is not
919 * fatal, as we will either wait upon the next vblank interrupt or
920 * timeout. Generally speaking intel_wait_for_vblank() is only
921 * called during modeset at which time the GPU should be idle and
922 * should *not* be performing page flips and thus not waiting on
923 * vblanks...
924 * Currently, the result of us stealing a vblank from the irq
925 * handler is that a single frame will be skipped during swapbuffers.
926 */
927 I915_WRITE(pipestat_reg,
928 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
929
930 /* Wait for vblank interrupt bit to set */
931 if (wait_for(I915_READ(pipestat_reg) &
932 PIPE_VBLANK_INTERRUPT_STATUS,
933 50))
934 DRM_DEBUG_KMS("vblank wait timed out\n");
935 }
936
937 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
938 {
939 struct drm_i915_private *dev_priv = dev->dev_private;
940 u32 reg = PIPEDSL(pipe);
941 u32 line1, line2;
942 u32 line_mask;
943
944 if (IS_GEN2(dev))
945 line_mask = DSL_LINEMASK_GEN2;
946 else
947 line_mask = DSL_LINEMASK_GEN3;
948
949 line1 = I915_READ(reg) & line_mask;
950 mdelay(5);
951 line2 = I915_READ(reg) & line_mask;
952
953 return line1 == line2;
954 }
955
956 /*
957 * intel_wait_for_pipe_off - wait for pipe to turn off
958 * @dev: drm device
959 * @pipe: pipe to wait for
960 *
961 * After disabling a pipe, we can't wait for vblank in the usual way,
962 * spinning on the vblank interrupt status bit, since we won't actually
963 * see an interrupt when the pipe is disabled.
964 *
965 * On Gen4 and above:
966 * wait for the pipe register state bit to turn off
967 *
968 * Otherwise:
969 * wait for the display line value to settle (it usually
970 * ends up stopping at the start of the next frame).
971 *
972 */
973 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
974 {
975 struct drm_i915_private *dev_priv = dev->dev_private;
976 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
977 pipe);
978
979 if (INTEL_INFO(dev)->gen >= 4) {
980 int reg = PIPECONF(cpu_transcoder);
981
982 /* Wait for the Pipe State to go off */
983 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
984 100))
985 WARN(1, "pipe_off wait timed out\n");
986 } else {
987 /* Wait for the display line to settle */
988 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
989 WARN(1, "pipe_off wait timed out\n");
990 }
991 }
992
993 /*
994 * ibx_digital_port_connected - is the specified port connected?
995 * @dev_priv: i915 private structure
996 * @port: the port to test
997 *
998 * Returns true if @port is connected, false otherwise.
999 */
1000 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1001 struct intel_digital_port *port)
1002 {
1003 u32 bit;
1004
1005 if (HAS_PCH_IBX(dev_priv->dev)) {
1006 switch (port->port) {
1007 case PORT_B:
1008 bit = SDE_PORTB_HOTPLUG;
1009 break;
1010 case PORT_C:
1011 bit = SDE_PORTC_HOTPLUG;
1012 break;
1013 case PORT_D:
1014 bit = SDE_PORTD_HOTPLUG;
1015 break;
1016 default:
1017 return true;
1018 }
1019 } else {
1020 switch (port->port) {
1021 case PORT_B:
1022 bit = SDE_PORTB_HOTPLUG_CPT;
1023 break;
1024 case PORT_C:
1025 bit = SDE_PORTC_HOTPLUG_CPT;
1026 break;
1027 case PORT_D:
1028 bit = SDE_PORTD_HOTPLUG_CPT;
1029 break;
1030 default:
1031 return true;
1032 }
1033 }
1034
1035 return I915_READ(SDEISR) & bit;
1036 }
1037
1038 static const char *state_string(bool enabled)
1039 {
1040 return enabled ? "on" : "off";
1041 }
1042
1043 /* Only for pre-ILK configs */
1044 void assert_pll(struct drm_i915_private *dev_priv,
1045 enum pipe pipe, bool state)
1046 {
1047 int reg;
1048 u32 val;
1049 bool cur_state;
1050
1051 reg = DPLL(pipe);
1052 val = I915_READ(reg);
1053 cur_state = !!(val & DPLL_VCO_ENABLE);
1054 WARN(cur_state != state,
1055 "PLL state assertion failure (expected %s, current %s)\n",
1056 state_string(state), state_string(cur_state));
1057 }
1058
1059 /* XXX: the dsi pll is shared between MIPI DSI ports */
1060 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1061 {
1062 u32 val;
1063 bool cur_state;
1064
1065 mutex_lock(&dev_priv->dpio_lock);
1066 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1067 mutex_unlock(&dev_priv->dpio_lock);
1068
1069 cur_state = val & DSI_PLL_VCO_EN;
1070 WARN(cur_state != state,
1071 "DSI PLL state assertion failure (expected %s, current %s)\n",
1072 state_string(state), state_string(cur_state));
1073 }
1074 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1075 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1076
1077 struct intel_shared_dpll *
1078 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1079 {
1080 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1081
1082 if (crtc->config.shared_dpll < 0)
1083 return NULL;
1084
1085 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1086 }
1087
1088 /* For ILK+ */
1089 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1090 struct intel_shared_dpll *pll,
1091 bool state)
1092 {
1093 bool cur_state;
1094 struct intel_dpll_hw_state hw_state;
1095
1096 if (HAS_PCH_LPT(dev_priv->dev)) {
1097 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1098 return;
1099 }
1100
1101 if (WARN (!pll,
1102 "asserting DPLL %s with no DPLL\n", state_string(state)))
1103 return;
1104
1105 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1106 WARN(cur_state != state,
1107 "%s assertion failure (expected %s, current %s)\n",
1108 pll->name, state_string(state), state_string(cur_state));
1109 }
1110
1111 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1112 enum pipe pipe, bool state)
1113 {
1114 int reg;
1115 u32 val;
1116 bool cur_state;
1117 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1118 pipe);
1119
1120 if (HAS_DDI(dev_priv->dev)) {
1121 /* DDI does not have a specific FDI_TX register */
1122 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1123 val = I915_READ(reg);
1124 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1125 } else {
1126 reg = FDI_TX_CTL(pipe);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & FDI_TX_ENABLE);
1129 }
1130 WARN(cur_state != state,
1131 "FDI TX state assertion failure (expected %s, current %s)\n",
1132 state_string(state), state_string(cur_state));
1133 }
1134 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1135 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1136
1137 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1138 enum pipe pipe, bool state)
1139 {
1140 int reg;
1141 u32 val;
1142 bool cur_state;
1143
1144 reg = FDI_RX_CTL(pipe);
1145 val = I915_READ(reg);
1146 cur_state = !!(val & FDI_RX_ENABLE);
1147 WARN(cur_state != state,
1148 "FDI RX state assertion failure (expected %s, current %s)\n",
1149 state_string(state), state_string(cur_state));
1150 }
1151 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1152 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1153
1154 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1155 enum pipe pipe)
1156 {
1157 int reg;
1158 u32 val;
1159
1160 /* ILK FDI PLL is always enabled */
1161 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1162 return;
1163
1164 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1165 if (HAS_DDI(dev_priv->dev))
1166 return;
1167
1168 reg = FDI_TX_CTL(pipe);
1169 val = I915_READ(reg);
1170 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1171 }
1172
1173 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1174 enum pipe pipe, bool state)
1175 {
1176 int reg;
1177 u32 val;
1178 bool cur_state;
1179
1180 reg = FDI_RX_CTL(pipe);
1181 val = I915_READ(reg);
1182 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1183 WARN(cur_state != state,
1184 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1185 state_string(state), state_string(cur_state));
1186 }
1187
1188 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190 {
1191 int pp_reg, lvds_reg;
1192 u32 val;
1193 enum pipe panel_pipe = PIPE_A;
1194 bool locked = true;
1195
1196 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1197 pp_reg = PCH_PP_CONTROL;
1198 lvds_reg = PCH_LVDS;
1199 } else {
1200 pp_reg = PP_CONTROL;
1201 lvds_reg = LVDS;
1202 }
1203
1204 val = I915_READ(pp_reg);
1205 if (!(val & PANEL_POWER_ON) ||
1206 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1207 locked = false;
1208
1209 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1211
1212 WARN(panel_pipe == pipe && locked,
1213 "panel assertion failure, pipe %c regs locked\n",
1214 pipe_name(pipe));
1215 }
1216
1217 static void assert_cursor(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
1219 {
1220 struct drm_device *dev = dev_priv->dev;
1221 bool cur_state;
1222
1223 if (IS_845G(dev) || IS_I865G(dev))
1224 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1225 else
1226 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1227
1228 WARN(cur_state != state,
1229 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1230 pipe_name(pipe), state_string(state), state_string(cur_state));
1231 }
1232 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1233 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1234
1235 void assert_pipe(struct drm_i915_private *dev_priv,
1236 enum pipe pipe, bool state)
1237 {
1238 int reg;
1239 u32 val;
1240 bool cur_state;
1241 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1242 pipe);
1243
1244 /* if we need the pipe A quirk it must be always on */
1245 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1246 state = true;
1247
1248 if (!intel_display_power_enabled(dev_priv,
1249 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1250 cur_state = false;
1251 } else {
1252 reg = PIPECONF(cpu_transcoder);
1253 val = I915_READ(reg);
1254 cur_state = !!(val & PIPECONF_ENABLE);
1255 }
1256
1257 WARN(cur_state != state,
1258 "pipe %c assertion failure (expected %s, current %s)\n",
1259 pipe_name(pipe), state_string(state), state_string(cur_state));
1260 }
1261
1262 static void assert_plane(struct drm_i915_private *dev_priv,
1263 enum plane plane, bool state)
1264 {
1265 int reg;
1266 u32 val;
1267 bool cur_state;
1268
1269 reg = DSPCNTR(plane);
1270 val = I915_READ(reg);
1271 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1272 WARN(cur_state != state,
1273 "plane %c assertion failure (expected %s, current %s)\n",
1274 plane_name(plane), state_string(state), state_string(cur_state));
1275 }
1276
1277 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1278 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1279
1280 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1281 enum pipe pipe)
1282 {
1283 struct drm_device *dev = dev_priv->dev;
1284 int reg, i;
1285 u32 val;
1286 int cur_pipe;
1287
1288 /* Primary planes are fixed to pipes on gen4+ */
1289 if (INTEL_INFO(dev)->gen >= 4) {
1290 reg = DSPCNTR(pipe);
1291 val = I915_READ(reg);
1292 WARN(val & DISPLAY_PLANE_ENABLE,
1293 "plane %c assertion failure, should be disabled but not\n",
1294 plane_name(pipe));
1295 return;
1296 }
1297
1298 /* Need to check both planes against the pipe */
1299 for_each_pipe(i) {
1300 reg = DSPCNTR(i);
1301 val = I915_READ(reg);
1302 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1303 DISPPLANE_SEL_PIPE_SHIFT;
1304 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1305 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1306 plane_name(i), pipe_name(pipe));
1307 }
1308 }
1309
1310 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1311 enum pipe pipe)
1312 {
1313 struct drm_device *dev = dev_priv->dev;
1314 int reg, sprite;
1315 u32 val;
1316
1317 if (IS_VALLEYVIEW(dev)) {
1318 for_each_sprite(pipe, sprite) {
1319 reg = SPCNTR(pipe, sprite);
1320 val = I915_READ(reg);
1321 WARN(val & SP_ENABLE,
1322 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1323 sprite_name(pipe, sprite), pipe_name(pipe));
1324 }
1325 } else if (INTEL_INFO(dev)->gen >= 7) {
1326 reg = SPRCTL(pipe);
1327 val = I915_READ(reg);
1328 WARN(val & SPRITE_ENABLE,
1329 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1330 plane_name(pipe), pipe_name(pipe));
1331 } else if (INTEL_INFO(dev)->gen >= 5) {
1332 reg = DVSCNTR(pipe);
1333 val = I915_READ(reg);
1334 WARN(val & DVS_ENABLE,
1335 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1336 plane_name(pipe), pipe_name(pipe));
1337 }
1338 }
1339
1340 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1341 {
1342 u32 val;
1343 bool enabled;
1344
1345 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1346
1347 val = I915_READ(PCH_DREF_CONTROL);
1348 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1349 DREF_SUPERSPREAD_SOURCE_MASK));
1350 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1351 }
1352
1353 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1354 enum pipe pipe)
1355 {
1356 int reg;
1357 u32 val;
1358 bool enabled;
1359
1360 reg = PCH_TRANSCONF(pipe);
1361 val = I915_READ(reg);
1362 enabled = !!(val & TRANS_ENABLE);
1363 WARN(enabled,
1364 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1365 pipe_name(pipe));
1366 }
1367
1368 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1369 enum pipe pipe, u32 port_sel, u32 val)
1370 {
1371 if ((val & DP_PORT_EN) == 0)
1372 return false;
1373
1374 if (HAS_PCH_CPT(dev_priv->dev)) {
1375 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1376 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1377 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1378 return false;
1379 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1380 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1381 return false;
1382 } else {
1383 if ((val & DP_PIPE_MASK) != (pipe << 30))
1384 return false;
1385 }
1386 return true;
1387 }
1388
1389 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1390 enum pipe pipe, u32 val)
1391 {
1392 if ((val & SDVO_ENABLE) == 0)
1393 return false;
1394
1395 if (HAS_PCH_CPT(dev_priv->dev)) {
1396 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1397 return false;
1398 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1399 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1400 return false;
1401 } else {
1402 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1403 return false;
1404 }
1405 return true;
1406 }
1407
1408 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1409 enum pipe pipe, u32 val)
1410 {
1411 if ((val & LVDS_PORT_EN) == 0)
1412 return false;
1413
1414 if (HAS_PCH_CPT(dev_priv->dev)) {
1415 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1416 return false;
1417 } else {
1418 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1419 return false;
1420 }
1421 return true;
1422 }
1423
1424 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1425 enum pipe pipe, u32 val)
1426 {
1427 if ((val & ADPA_DAC_ENABLE) == 0)
1428 return false;
1429 if (HAS_PCH_CPT(dev_priv->dev)) {
1430 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1431 return false;
1432 } else {
1433 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1434 return false;
1435 }
1436 return true;
1437 }
1438
1439 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1440 enum pipe pipe, int reg, u32 port_sel)
1441 {
1442 u32 val = I915_READ(reg);
1443 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1444 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1445 reg, pipe_name(pipe));
1446
1447 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1448 && (val & DP_PIPEB_SELECT),
1449 "IBX PCH dp port still using transcoder B\n");
1450 }
1451
1452 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1453 enum pipe pipe, int reg)
1454 {
1455 u32 val = I915_READ(reg);
1456 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1457 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1458 reg, pipe_name(pipe));
1459
1460 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1461 && (val & SDVO_PIPE_B_SELECT),
1462 "IBX PCH hdmi port still using transcoder B\n");
1463 }
1464
1465 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1466 enum pipe pipe)
1467 {
1468 int reg;
1469 u32 val;
1470
1471 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1472 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1473 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1474
1475 reg = PCH_ADPA;
1476 val = I915_READ(reg);
1477 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1478 "PCH VGA enabled on transcoder %c, should be disabled\n",
1479 pipe_name(pipe));
1480
1481 reg = PCH_LVDS;
1482 val = I915_READ(reg);
1483 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1484 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1485 pipe_name(pipe));
1486
1487 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1488 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1489 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1490 }
1491
1492 static void intel_init_dpio(struct drm_device *dev)
1493 {
1494 struct drm_i915_private *dev_priv = dev->dev_private;
1495
1496 if (!IS_VALLEYVIEW(dev))
1497 return;
1498
1499 /*
1500 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1501 * CHV x1 PHY (DP/HDMI D)
1502 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1503 */
1504 if (IS_CHERRYVIEW(dev)) {
1505 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1506 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1507 } else {
1508 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1509 }
1510 }
1511
1512 static void intel_reset_dpio(struct drm_device *dev)
1513 {
1514 struct drm_i915_private *dev_priv = dev->dev_private;
1515
1516 if (!IS_VALLEYVIEW(dev))
1517 return;
1518
1519 if (IS_CHERRYVIEW(dev)) {
1520 enum dpio_phy phy;
1521 u32 val;
1522
1523 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1524 /* Poll for phypwrgood signal */
1525 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1526 PHY_POWERGOOD(phy), 1))
1527 DRM_ERROR("Display PHY %d is not power up\n", phy);
1528
1529 /*
1530 * Deassert common lane reset for PHY.
1531 *
1532 * This should only be done on init and resume from S3
1533 * with both PLLs disabled, or we risk losing DPIO and
1534 * PLL synchronization.
1535 */
1536 val = I915_READ(DISPLAY_PHY_CONTROL);
1537 I915_WRITE(DISPLAY_PHY_CONTROL,
1538 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1539 }
1540
1541 } else {
1542 /*
1543 * If DPIO has already been reset, e.g. by BIOS, just skip all
1544 * this.
1545 */
1546 if (I915_READ(DPIO_CTL) & DPIO_CMNRST)
1547 return;
1548
1549 /*
1550 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
1551 * Need to assert and de-assert PHY SB reset by gating the
1552 * common lane power, then un-gating it.
1553 * Simply ungating isn't enough to reset the PHY enough to get
1554 * ports and lanes running.
1555 */
1556 __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC,
1557 false);
1558 __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC,
1559 true);
1560 }
1561 }
1562
1563 static void vlv_enable_pll(struct intel_crtc *crtc)
1564 {
1565 struct drm_device *dev = crtc->base.dev;
1566 struct drm_i915_private *dev_priv = dev->dev_private;
1567 int reg = DPLL(crtc->pipe);
1568 u32 dpll = crtc->config.dpll_hw_state.dpll;
1569
1570 assert_pipe_disabled(dev_priv, crtc->pipe);
1571
1572 /* No really, not for ILK+ */
1573 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1574
1575 /* PLL is protected by panel, make sure we can write it */
1576 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1577 assert_panel_unlocked(dev_priv, crtc->pipe);
1578
1579 I915_WRITE(reg, dpll);
1580 POSTING_READ(reg);
1581 udelay(150);
1582
1583 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1584 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1585
1586 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1587 POSTING_READ(DPLL_MD(crtc->pipe));
1588
1589 /* We do this three times for luck */
1590 I915_WRITE(reg, dpll);
1591 POSTING_READ(reg);
1592 udelay(150); /* wait for warmup */
1593 I915_WRITE(reg, dpll);
1594 POSTING_READ(reg);
1595 udelay(150); /* wait for warmup */
1596 I915_WRITE(reg, dpll);
1597 POSTING_READ(reg);
1598 udelay(150); /* wait for warmup */
1599 }
1600
1601 static void chv_enable_pll(struct intel_crtc *crtc)
1602 {
1603 struct drm_device *dev = crtc->base.dev;
1604 struct drm_i915_private *dev_priv = dev->dev_private;
1605 int pipe = crtc->pipe;
1606 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1607 u32 tmp;
1608
1609 assert_pipe_disabled(dev_priv, crtc->pipe);
1610
1611 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1612
1613 mutex_lock(&dev_priv->dpio_lock);
1614
1615 /* Enable back the 10bit clock to display controller */
1616 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1617 tmp |= DPIO_DCLKP_EN;
1618 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1619
1620 /*
1621 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1622 */
1623 udelay(1);
1624
1625 /* Enable PLL */
1626 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1627
1628 /* Check PLL is locked */
1629 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1630 DRM_ERROR("PLL %d failed to lock\n", pipe);
1631
1632 /* not sure when this should be written */
1633 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1634 POSTING_READ(DPLL_MD(pipe));
1635
1636 mutex_unlock(&dev_priv->dpio_lock);
1637 }
1638
1639 static void i9xx_enable_pll(struct intel_crtc *crtc)
1640 {
1641 struct drm_device *dev = crtc->base.dev;
1642 struct drm_i915_private *dev_priv = dev->dev_private;
1643 int reg = DPLL(crtc->pipe);
1644 u32 dpll = crtc->config.dpll_hw_state.dpll;
1645
1646 assert_pipe_disabled(dev_priv, crtc->pipe);
1647
1648 /* No really, not for ILK+ */
1649 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1650
1651 /* PLL is protected by panel, make sure we can write it */
1652 if (IS_MOBILE(dev) && !IS_I830(dev))
1653 assert_panel_unlocked(dev_priv, crtc->pipe);
1654
1655 I915_WRITE(reg, dpll);
1656
1657 /* Wait for the clocks to stabilize. */
1658 POSTING_READ(reg);
1659 udelay(150);
1660
1661 if (INTEL_INFO(dev)->gen >= 4) {
1662 I915_WRITE(DPLL_MD(crtc->pipe),
1663 crtc->config.dpll_hw_state.dpll_md);
1664 } else {
1665 /* The pixel multiplier can only be updated once the
1666 * DPLL is enabled and the clocks are stable.
1667 *
1668 * So write it again.
1669 */
1670 I915_WRITE(reg, dpll);
1671 }
1672
1673 /* We do this three times for luck */
1674 I915_WRITE(reg, dpll);
1675 POSTING_READ(reg);
1676 udelay(150); /* wait for warmup */
1677 I915_WRITE(reg, dpll);
1678 POSTING_READ(reg);
1679 udelay(150); /* wait for warmup */
1680 I915_WRITE(reg, dpll);
1681 POSTING_READ(reg);
1682 udelay(150); /* wait for warmup */
1683 }
1684
1685 /**
1686 * i9xx_disable_pll - disable a PLL
1687 * @dev_priv: i915 private structure
1688 * @pipe: pipe PLL to disable
1689 *
1690 * Disable the PLL for @pipe, making sure the pipe is off first.
1691 *
1692 * Note! This is for pre-ILK only.
1693 */
1694 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1695 {
1696 /* Don't disable pipe A or pipe A PLLs if needed */
1697 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1698 return;
1699
1700 /* Make sure the pipe isn't still relying on us */
1701 assert_pipe_disabled(dev_priv, pipe);
1702
1703 I915_WRITE(DPLL(pipe), 0);
1704 POSTING_READ(DPLL(pipe));
1705 }
1706
1707 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1708 {
1709 u32 val = 0;
1710
1711 /* Make sure the pipe isn't still relying on us */
1712 assert_pipe_disabled(dev_priv, pipe);
1713
1714 /*
1715 * Leave integrated clock source and reference clock enabled for pipe B.
1716 * The latter is needed for VGA hotplug / manual detection.
1717 */
1718 if (pipe == PIPE_B)
1719 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1720 I915_WRITE(DPLL(pipe), val);
1721 POSTING_READ(DPLL(pipe));
1722
1723 }
1724
1725 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1726 {
1727 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1728 u32 val;
1729
1730 /* Make sure the pipe isn't still relying on us */
1731 assert_pipe_disabled(dev_priv, pipe);
1732
1733 /* Set PLL en = 0 */
1734 val = DPLL_SSC_REF_CLOCK_CHV;
1735 if (pipe != PIPE_A)
1736 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1737 I915_WRITE(DPLL(pipe), val);
1738 POSTING_READ(DPLL(pipe));
1739
1740 mutex_lock(&dev_priv->dpio_lock);
1741
1742 /* Disable 10bit clock to display controller */
1743 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1744 val &= ~DPIO_DCLKP_EN;
1745 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1746
1747 /* disable left/right clock distribution */
1748 if (pipe != PIPE_B) {
1749 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1750 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1751 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1752 } else {
1753 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1754 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1755 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1756 }
1757
1758 mutex_unlock(&dev_priv->dpio_lock);
1759 }
1760
1761 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1762 struct intel_digital_port *dport)
1763 {
1764 u32 port_mask;
1765 int dpll_reg;
1766
1767 switch (dport->port) {
1768 case PORT_B:
1769 port_mask = DPLL_PORTB_READY_MASK;
1770 dpll_reg = DPLL(0);
1771 break;
1772 case PORT_C:
1773 port_mask = DPLL_PORTC_READY_MASK;
1774 dpll_reg = DPLL(0);
1775 break;
1776 case PORT_D:
1777 port_mask = DPLL_PORTD_READY_MASK;
1778 dpll_reg = DPIO_PHY_STATUS;
1779 break;
1780 default:
1781 BUG();
1782 }
1783
1784 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1785 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1786 port_name(dport->port), I915_READ(dpll_reg));
1787 }
1788
1789 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1790 {
1791 struct drm_device *dev = crtc->base.dev;
1792 struct drm_i915_private *dev_priv = dev->dev_private;
1793 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1794
1795 if (WARN_ON(pll == NULL))
1796 return;
1797
1798 WARN_ON(!pll->refcount);
1799 if (pll->active == 0) {
1800 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1801 WARN_ON(pll->on);
1802 assert_shared_dpll_disabled(dev_priv, pll);
1803
1804 pll->mode_set(dev_priv, pll);
1805 }
1806 }
1807
1808 /**
1809 * intel_enable_shared_dpll - enable PCH PLL
1810 * @dev_priv: i915 private structure
1811 * @pipe: pipe PLL to enable
1812 *
1813 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1814 * drives the transcoder clock.
1815 */
1816 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1817 {
1818 struct drm_device *dev = crtc->base.dev;
1819 struct drm_i915_private *dev_priv = dev->dev_private;
1820 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1821
1822 if (WARN_ON(pll == NULL))
1823 return;
1824
1825 if (WARN_ON(pll->refcount == 0))
1826 return;
1827
1828 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1829 pll->name, pll->active, pll->on,
1830 crtc->base.base.id);
1831
1832 if (pll->active++) {
1833 WARN_ON(!pll->on);
1834 assert_shared_dpll_enabled(dev_priv, pll);
1835 return;
1836 }
1837 WARN_ON(pll->on);
1838
1839 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1840 pll->enable(dev_priv, pll);
1841 pll->on = true;
1842 }
1843
1844 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1845 {
1846 struct drm_device *dev = crtc->base.dev;
1847 struct drm_i915_private *dev_priv = dev->dev_private;
1848 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1849
1850 /* PCH only available on ILK+ */
1851 BUG_ON(INTEL_INFO(dev)->gen < 5);
1852 if (WARN_ON(pll == NULL))
1853 return;
1854
1855 if (WARN_ON(pll->refcount == 0))
1856 return;
1857
1858 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1859 pll->name, pll->active, pll->on,
1860 crtc->base.base.id);
1861
1862 if (WARN_ON(pll->active == 0)) {
1863 assert_shared_dpll_disabled(dev_priv, pll);
1864 return;
1865 }
1866
1867 assert_shared_dpll_enabled(dev_priv, pll);
1868 WARN_ON(!pll->on);
1869 if (--pll->active)
1870 return;
1871
1872 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1873 pll->disable(dev_priv, pll);
1874 pll->on = false;
1875 }
1876
1877 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1878 enum pipe pipe)
1879 {
1880 struct drm_device *dev = dev_priv->dev;
1881 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1883 uint32_t reg, val, pipeconf_val;
1884
1885 /* PCH only available on ILK+ */
1886 BUG_ON(INTEL_INFO(dev)->gen < 5);
1887
1888 /* Make sure PCH DPLL is enabled */
1889 assert_shared_dpll_enabled(dev_priv,
1890 intel_crtc_to_shared_dpll(intel_crtc));
1891
1892 /* FDI must be feeding us bits for PCH ports */
1893 assert_fdi_tx_enabled(dev_priv, pipe);
1894 assert_fdi_rx_enabled(dev_priv, pipe);
1895
1896 if (HAS_PCH_CPT(dev)) {
1897 /* Workaround: Set the timing override bit before enabling the
1898 * pch transcoder. */
1899 reg = TRANS_CHICKEN2(pipe);
1900 val = I915_READ(reg);
1901 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1902 I915_WRITE(reg, val);
1903 }
1904
1905 reg = PCH_TRANSCONF(pipe);
1906 val = I915_READ(reg);
1907 pipeconf_val = I915_READ(PIPECONF(pipe));
1908
1909 if (HAS_PCH_IBX(dev_priv->dev)) {
1910 /*
1911 * make the BPC in transcoder be consistent with
1912 * that in pipeconf reg.
1913 */
1914 val &= ~PIPECONF_BPC_MASK;
1915 val |= pipeconf_val & PIPECONF_BPC_MASK;
1916 }
1917
1918 val &= ~TRANS_INTERLACE_MASK;
1919 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1920 if (HAS_PCH_IBX(dev_priv->dev) &&
1921 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1922 val |= TRANS_LEGACY_INTERLACED_ILK;
1923 else
1924 val |= TRANS_INTERLACED;
1925 else
1926 val |= TRANS_PROGRESSIVE;
1927
1928 I915_WRITE(reg, val | TRANS_ENABLE);
1929 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1930 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1931 }
1932
1933 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1934 enum transcoder cpu_transcoder)
1935 {
1936 u32 val, pipeconf_val;
1937
1938 /* PCH only available on ILK+ */
1939 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1940
1941 /* FDI must be feeding us bits for PCH ports */
1942 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1943 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1944
1945 /* Workaround: set timing override bit. */
1946 val = I915_READ(_TRANSA_CHICKEN2);
1947 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1948 I915_WRITE(_TRANSA_CHICKEN2, val);
1949
1950 val = TRANS_ENABLE;
1951 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1952
1953 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1954 PIPECONF_INTERLACED_ILK)
1955 val |= TRANS_INTERLACED;
1956 else
1957 val |= TRANS_PROGRESSIVE;
1958
1959 I915_WRITE(LPT_TRANSCONF, val);
1960 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1961 DRM_ERROR("Failed to enable PCH transcoder\n");
1962 }
1963
1964 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1965 enum pipe pipe)
1966 {
1967 struct drm_device *dev = dev_priv->dev;
1968 uint32_t reg, val;
1969
1970 /* FDI relies on the transcoder */
1971 assert_fdi_tx_disabled(dev_priv, pipe);
1972 assert_fdi_rx_disabled(dev_priv, pipe);
1973
1974 /* Ports must be off as well */
1975 assert_pch_ports_disabled(dev_priv, pipe);
1976
1977 reg = PCH_TRANSCONF(pipe);
1978 val = I915_READ(reg);
1979 val &= ~TRANS_ENABLE;
1980 I915_WRITE(reg, val);
1981 /* wait for PCH transcoder off, transcoder state */
1982 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1983 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1984
1985 if (!HAS_PCH_IBX(dev)) {
1986 /* Workaround: Clear the timing override chicken bit again. */
1987 reg = TRANS_CHICKEN2(pipe);
1988 val = I915_READ(reg);
1989 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1990 I915_WRITE(reg, val);
1991 }
1992 }
1993
1994 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1995 {
1996 u32 val;
1997
1998 val = I915_READ(LPT_TRANSCONF);
1999 val &= ~TRANS_ENABLE;
2000 I915_WRITE(LPT_TRANSCONF, val);
2001 /* wait for PCH transcoder off, transcoder state */
2002 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2003 DRM_ERROR("Failed to disable PCH transcoder\n");
2004
2005 /* Workaround: clear timing override bit. */
2006 val = I915_READ(_TRANSA_CHICKEN2);
2007 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2008 I915_WRITE(_TRANSA_CHICKEN2, val);
2009 }
2010
2011 /**
2012 * intel_enable_pipe - enable a pipe, asserting requirements
2013 * @crtc: crtc responsible for the pipe
2014 *
2015 * Enable @crtc's pipe, making sure that various hardware specific requirements
2016 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2017 */
2018 static void intel_enable_pipe(struct intel_crtc *crtc)
2019 {
2020 struct drm_device *dev = crtc->base.dev;
2021 struct drm_i915_private *dev_priv = dev->dev_private;
2022 enum pipe pipe = crtc->pipe;
2023 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2024 pipe);
2025 enum pipe pch_transcoder;
2026 int reg;
2027 u32 val;
2028
2029 assert_planes_disabled(dev_priv, pipe);
2030 assert_cursor_disabled(dev_priv, pipe);
2031 assert_sprites_disabled(dev_priv, pipe);
2032
2033 if (HAS_PCH_LPT(dev_priv->dev))
2034 pch_transcoder = TRANSCODER_A;
2035 else
2036 pch_transcoder = pipe;
2037
2038 /*
2039 * A pipe without a PLL won't actually be able to drive bits from
2040 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2041 * need the check.
2042 */
2043 if (!HAS_PCH_SPLIT(dev_priv->dev))
2044 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2045 assert_dsi_pll_enabled(dev_priv);
2046 else
2047 assert_pll_enabled(dev_priv, pipe);
2048 else {
2049 if (crtc->config.has_pch_encoder) {
2050 /* if driving the PCH, we need FDI enabled */
2051 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2052 assert_fdi_tx_pll_enabled(dev_priv,
2053 (enum pipe) cpu_transcoder);
2054 }
2055 /* FIXME: assert CPU port conditions for SNB+ */
2056 }
2057
2058 reg = PIPECONF(cpu_transcoder);
2059 val = I915_READ(reg);
2060 if (val & PIPECONF_ENABLE) {
2061 WARN_ON(!(pipe == PIPE_A &&
2062 dev_priv->quirks & QUIRK_PIPEA_FORCE));
2063 return;
2064 }
2065
2066 I915_WRITE(reg, val | PIPECONF_ENABLE);
2067 POSTING_READ(reg);
2068 }
2069
2070 /**
2071 * intel_disable_pipe - disable a pipe, asserting requirements
2072 * @dev_priv: i915 private structure
2073 * @pipe: pipe to disable
2074 *
2075 * Disable @pipe, making sure that various hardware specific requirements
2076 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2077 *
2078 * @pipe should be %PIPE_A or %PIPE_B.
2079 *
2080 * Will wait until the pipe has shut down before returning.
2081 */
2082 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2083 enum pipe pipe)
2084 {
2085 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2086 pipe);
2087 int reg;
2088 u32 val;
2089
2090 /*
2091 * Make sure planes won't keep trying to pump pixels to us,
2092 * or we might hang the display.
2093 */
2094 assert_planes_disabled(dev_priv, pipe);
2095 assert_cursor_disabled(dev_priv, pipe);
2096 assert_sprites_disabled(dev_priv, pipe);
2097
2098 /* Don't disable pipe A or pipe A PLLs if needed */
2099 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2100 return;
2101
2102 reg = PIPECONF(cpu_transcoder);
2103 val = I915_READ(reg);
2104 if ((val & PIPECONF_ENABLE) == 0)
2105 return;
2106
2107 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2108 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2109 }
2110
2111 /*
2112 * Plane regs are double buffered, going from enabled->disabled needs a
2113 * trigger in order to latch. The display address reg provides this.
2114 */
2115 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2116 enum plane plane)
2117 {
2118 struct drm_device *dev = dev_priv->dev;
2119 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2120
2121 I915_WRITE(reg, I915_READ(reg));
2122 POSTING_READ(reg);
2123 }
2124
2125 /**
2126 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2127 * @dev_priv: i915 private structure
2128 * @plane: plane to enable
2129 * @pipe: pipe being fed
2130 *
2131 * Enable @plane on @pipe, making sure that @pipe is running first.
2132 */
2133 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2134 enum plane plane, enum pipe pipe)
2135 {
2136 struct intel_crtc *intel_crtc =
2137 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2138 int reg;
2139 u32 val;
2140
2141 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2142 assert_pipe_enabled(dev_priv, pipe);
2143
2144 if (intel_crtc->primary_enabled)
2145 return;
2146
2147 intel_crtc->primary_enabled = true;
2148
2149 reg = DSPCNTR(plane);
2150 val = I915_READ(reg);
2151 WARN_ON(val & DISPLAY_PLANE_ENABLE);
2152
2153 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2154 intel_flush_primary_plane(dev_priv, plane);
2155 }
2156
2157 /**
2158 * intel_disable_primary_hw_plane - disable the primary hardware plane
2159 * @dev_priv: i915 private structure
2160 * @plane: plane to disable
2161 * @pipe: pipe consuming the data
2162 *
2163 * Disable @plane; should be an independent operation.
2164 */
2165 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2166 enum plane plane, enum pipe pipe)
2167 {
2168 struct intel_crtc *intel_crtc =
2169 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2170 int reg;
2171 u32 val;
2172
2173 if (!intel_crtc->primary_enabled)
2174 return;
2175
2176 intel_crtc->primary_enabled = false;
2177
2178 reg = DSPCNTR(plane);
2179 val = I915_READ(reg);
2180 WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2181
2182 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2183 intel_flush_primary_plane(dev_priv, plane);
2184 }
2185
2186 static bool need_vtd_wa(struct drm_device *dev)
2187 {
2188 #ifdef CONFIG_INTEL_IOMMU
2189 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2190 return true;
2191 #endif
2192 return false;
2193 }
2194
2195 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2196 {
2197 int tile_height;
2198
2199 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2200 return ALIGN(height, tile_height);
2201 }
2202
2203 int
2204 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2205 struct drm_i915_gem_object *obj,
2206 struct intel_engine_cs *pipelined)
2207 {
2208 struct drm_i915_private *dev_priv = dev->dev_private;
2209 u32 alignment;
2210 int ret;
2211
2212 switch (obj->tiling_mode) {
2213 case I915_TILING_NONE:
2214 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2215 alignment = 128 * 1024;
2216 else if (INTEL_INFO(dev)->gen >= 4)
2217 alignment = 4 * 1024;
2218 else
2219 alignment = 64 * 1024;
2220 break;
2221 case I915_TILING_X:
2222 /* pin() will align the object as required by fence */
2223 alignment = 0;
2224 break;
2225 case I915_TILING_Y:
2226 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2227 return -EINVAL;
2228 default:
2229 BUG();
2230 }
2231
2232 /* Note that the w/a also requires 64 PTE of padding following the
2233 * bo. We currently fill all unused PTE with the shadow page and so
2234 * we should always have valid PTE following the scanout preventing
2235 * the VT-d warning.
2236 */
2237 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2238 alignment = 256 * 1024;
2239
2240 dev_priv->mm.interruptible = false;
2241 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2242 if (ret)
2243 goto err_interruptible;
2244
2245 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2246 * fence, whereas 965+ only requires a fence if using
2247 * framebuffer compression. For simplicity, we always install
2248 * a fence as the cost is not that onerous.
2249 */
2250 ret = i915_gem_object_get_fence(obj);
2251 if (ret)
2252 goto err_unpin;
2253
2254 i915_gem_object_pin_fence(obj);
2255
2256 dev_priv->mm.interruptible = true;
2257 return 0;
2258
2259 err_unpin:
2260 i915_gem_object_unpin_from_display_plane(obj);
2261 err_interruptible:
2262 dev_priv->mm.interruptible = true;
2263 return ret;
2264 }
2265
2266 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2267 {
2268 i915_gem_object_unpin_fence(obj);
2269 i915_gem_object_unpin_from_display_plane(obj);
2270 }
2271
2272 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2273 * is assumed to be a power-of-two. */
2274 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2275 unsigned int tiling_mode,
2276 unsigned int cpp,
2277 unsigned int pitch)
2278 {
2279 if (tiling_mode != I915_TILING_NONE) {
2280 unsigned int tile_rows, tiles;
2281
2282 tile_rows = *y / 8;
2283 *y %= 8;
2284
2285 tiles = *x / (512/cpp);
2286 *x %= 512/cpp;
2287
2288 return tile_rows * pitch * 8 + tiles * 4096;
2289 } else {
2290 unsigned int offset;
2291
2292 offset = *y * pitch + *x * cpp;
2293 *y = 0;
2294 *x = (offset & 4095) / cpp;
2295 return offset & -4096;
2296 }
2297 }
2298
2299 int intel_format_to_fourcc(int format)
2300 {
2301 switch (format) {
2302 case DISPPLANE_8BPP:
2303 return DRM_FORMAT_C8;
2304 case DISPPLANE_BGRX555:
2305 return DRM_FORMAT_XRGB1555;
2306 case DISPPLANE_BGRX565:
2307 return DRM_FORMAT_RGB565;
2308 default:
2309 case DISPPLANE_BGRX888:
2310 return DRM_FORMAT_XRGB8888;
2311 case DISPPLANE_RGBX888:
2312 return DRM_FORMAT_XBGR8888;
2313 case DISPPLANE_BGRX101010:
2314 return DRM_FORMAT_XRGB2101010;
2315 case DISPPLANE_RGBX101010:
2316 return DRM_FORMAT_XBGR2101010;
2317 }
2318 }
2319
2320 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2321 struct intel_plane_config *plane_config)
2322 {
2323 struct drm_device *dev = crtc->base.dev;
2324 struct drm_i915_gem_object *obj = NULL;
2325 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2326 u32 base = plane_config->base;
2327
2328 if (plane_config->size == 0)
2329 return false;
2330
2331 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2332 plane_config->size);
2333 if (!obj)
2334 return false;
2335
2336 if (plane_config->tiled) {
2337 obj->tiling_mode = I915_TILING_X;
2338 obj->stride = crtc->base.primary->fb->pitches[0];
2339 }
2340
2341 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2342 mode_cmd.width = crtc->base.primary->fb->width;
2343 mode_cmd.height = crtc->base.primary->fb->height;
2344 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2345
2346 mutex_lock(&dev->struct_mutex);
2347
2348 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2349 &mode_cmd, obj)) {
2350 DRM_DEBUG_KMS("intel fb init failed\n");
2351 goto out_unref_obj;
2352 }
2353
2354 mutex_unlock(&dev->struct_mutex);
2355
2356 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2357 return true;
2358
2359 out_unref_obj:
2360 drm_gem_object_unreference(&obj->base);
2361 mutex_unlock(&dev->struct_mutex);
2362 return false;
2363 }
2364
2365 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2366 struct intel_plane_config *plane_config)
2367 {
2368 struct drm_device *dev = intel_crtc->base.dev;
2369 struct drm_crtc *c;
2370 struct intel_crtc *i;
2371 struct intel_framebuffer *fb;
2372
2373 if (!intel_crtc->base.primary->fb)
2374 return;
2375
2376 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2377 return;
2378
2379 kfree(intel_crtc->base.primary->fb);
2380 intel_crtc->base.primary->fb = NULL;
2381
2382 /*
2383 * Failed to alloc the obj, check to see if we should share
2384 * an fb with another CRTC instead
2385 */
2386 for_each_crtc(dev, c) {
2387 i = to_intel_crtc(c);
2388
2389 if (c == &intel_crtc->base)
2390 continue;
2391
2392 if (!i->active || !c->primary->fb)
2393 continue;
2394
2395 fb = to_intel_framebuffer(c->primary->fb);
2396 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2397 drm_framebuffer_reference(c->primary->fb);
2398 intel_crtc->base.primary->fb = c->primary->fb;
2399 break;
2400 }
2401 }
2402 }
2403
2404 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2405 struct drm_framebuffer *fb,
2406 int x, int y)
2407 {
2408 struct drm_device *dev = crtc->dev;
2409 struct drm_i915_private *dev_priv = dev->dev_private;
2410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2411 struct intel_framebuffer *intel_fb;
2412 struct drm_i915_gem_object *obj;
2413 int plane = intel_crtc->plane;
2414 unsigned long linear_offset;
2415 u32 dspcntr;
2416 u32 reg;
2417
2418 intel_fb = to_intel_framebuffer(fb);
2419 obj = intel_fb->obj;
2420
2421 reg = DSPCNTR(plane);
2422 dspcntr = I915_READ(reg);
2423 /* Mask out pixel format bits in case we change it */
2424 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2425 switch (fb->pixel_format) {
2426 case DRM_FORMAT_C8:
2427 dspcntr |= DISPPLANE_8BPP;
2428 break;
2429 case DRM_FORMAT_XRGB1555:
2430 case DRM_FORMAT_ARGB1555:
2431 dspcntr |= DISPPLANE_BGRX555;
2432 break;
2433 case DRM_FORMAT_RGB565:
2434 dspcntr |= DISPPLANE_BGRX565;
2435 break;
2436 case DRM_FORMAT_XRGB8888:
2437 case DRM_FORMAT_ARGB8888:
2438 dspcntr |= DISPPLANE_BGRX888;
2439 break;
2440 case DRM_FORMAT_XBGR8888:
2441 case DRM_FORMAT_ABGR8888:
2442 dspcntr |= DISPPLANE_RGBX888;
2443 break;
2444 case DRM_FORMAT_XRGB2101010:
2445 case DRM_FORMAT_ARGB2101010:
2446 dspcntr |= DISPPLANE_BGRX101010;
2447 break;
2448 case DRM_FORMAT_XBGR2101010:
2449 case DRM_FORMAT_ABGR2101010:
2450 dspcntr |= DISPPLANE_RGBX101010;
2451 break;
2452 default:
2453 BUG();
2454 }
2455
2456 if (INTEL_INFO(dev)->gen >= 4) {
2457 if (obj->tiling_mode != I915_TILING_NONE)
2458 dspcntr |= DISPPLANE_TILED;
2459 else
2460 dspcntr &= ~DISPPLANE_TILED;
2461 }
2462
2463 if (IS_G4X(dev))
2464 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2465
2466 I915_WRITE(reg, dspcntr);
2467
2468 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2469
2470 if (INTEL_INFO(dev)->gen >= 4) {
2471 intel_crtc->dspaddr_offset =
2472 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2473 fb->bits_per_pixel / 8,
2474 fb->pitches[0]);
2475 linear_offset -= intel_crtc->dspaddr_offset;
2476 } else {
2477 intel_crtc->dspaddr_offset = linear_offset;
2478 }
2479
2480 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2481 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2482 fb->pitches[0]);
2483 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2484 if (INTEL_INFO(dev)->gen >= 4) {
2485 I915_WRITE(DSPSURF(plane),
2486 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2487 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2488 I915_WRITE(DSPLINOFF(plane), linear_offset);
2489 } else
2490 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2491 POSTING_READ(reg);
2492 }
2493
2494 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2495 struct drm_framebuffer *fb,
2496 int x, int y)
2497 {
2498 struct drm_device *dev = crtc->dev;
2499 struct drm_i915_private *dev_priv = dev->dev_private;
2500 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2501 struct intel_framebuffer *intel_fb;
2502 struct drm_i915_gem_object *obj;
2503 int plane = intel_crtc->plane;
2504 unsigned long linear_offset;
2505 u32 dspcntr;
2506 u32 reg;
2507
2508 intel_fb = to_intel_framebuffer(fb);
2509 obj = intel_fb->obj;
2510
2511 reg = DSPCNTR(plane);
2512 dspcntr = I915_READ(reg);
2513 /* Mask out pixel format bits in case we change it */
2514 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2515 switch (fb->pixel_format) {
2516 case DRM_FORMAT_C8:
2517 dspcntr |= DISPPLANE_8BPP;
2518 break;
2519 case DRM_FORMAT_RGB565:
2520 dspcntr |= DISPPLANE_BGRX565;
2521 break;
2522 case DRM_FORMAT_XRGB8888:
2523 case DRM_FORMAT_ARGB8888:
2524 dspcntr |= DISPPLANE_BGRX888;
2525 break;
2526 case DRM_FORMAT_XBGR8888:
2527 case DRM_FORMAT_ABGR8888:
2528 dspcntr |= DISPPLANE_RGBX888;
2529 break;
2530 case DRM_FORMAT_XRGB2101010:
2531 case DRM_FORMAT_ARGB2101010:
2532 dspcntr |= DISPPLANE_BGRX101010;
2533 break;
2534 case DRM_FORMAT_XBGR2101010:
2535 case DRM_FORMAT_ABGR2101010:
2536 dspcntr |= DISPPLANE_RGBX101010;
2537 break;
2538 default:
2539 BUG();
2540 }
2541
2542 if (obj->tiling_mode != I915_TILING_NONE)
2543 dspcntr |= DISPPLANE_TILED;
2544 else
2545 dspcntr &= ~DISPPLANE_TILED;
2546
2547 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2548 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2549 else
2550 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2551
2552 I915_WRITE(reg, dspcntr);
2553
2554 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2555 intel_crtc->dspaddr_offset =
2556 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2557 fb->bits_per_pixel / 8,
2558 fb->pitches[0]);
2559 linear_offset -= intel_crtc->dspaddr_offset;
2560
2561 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2562 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2563 fb->pitches[0]);
2564 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2565 I915_WRITE(DSPSURF(plane),
2566 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2567 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2568 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2569 } else {
2570 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2571 I915_WRITE(DSPLINOFF(plane), linear_offset);
2572 }
2573 POSTING_READ(reg);
2574 }
2575
2576 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2577 static int
2578 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2579 int x, int y, enum mode_set_atomic state)
2580 {
2581 struct drm_device *dev = crtc->dev;
2582 struct drm_i915_private *dev_priv = dev->dev_private;
2583
2584 if (dev_priv->display.disable_fbc)
2585 dev_priv->display.disable_fbc(dev);
2586 intel_increase_pllclock(crtc);
2587
2588 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2589
2590 return 0;
2591 }
2592
2593 void intel_display_handle_reset(struct drm_device *dev)
2594 {
2595 struct drm_i915_private *dev_priv = dev->dev_private;
2596 struct drm_crtc *crtc;
2597
2598 /*
2599 * Flips in the rings have been nuked by the reset,
2600 * so complete all pending flips so that user space
2601 * will get its events and not get stuck.
2602 *
2603 * Also update the base address of all primary
2604 * planes to the the last fb to make sure we're
2605 * showing the correct fb after a reset.
2606 *
2607 * Need to make two loops over the crtcs so that we
2608 * don't try to grab a crtc mutex before the
2609 * pending_flip_queue really got woken up.
2610 */
2611
2612 for_each_crtc(dev, crtc) {
2613 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2614 enum plane plane = intel_crtc->plane;
2615
2616 intel_prepare_page_flip(dev, plane);
2617 intel_finish_page_flip_plane(dev, plane);
2618 }
2619
2620 for_each_crtc(dev, crtc) {
2621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2622
2623 drm_modeset_lock(&crtc->mutex, NULL);
2624 /*
2625 * FIXME: Once we have proper support for primary planes (and
2626 * disabling them without disabling the entire crtc) allow again
2627 * a NULL crtc->primary->fb.
2628 */
2629 if (intel_crtc->active && crtc->primary->fb)
2630 dev_priv->display.update_primary_plane(crtc,
2631 crtc->primary->fb,
2632 crtc->x,
2633 crtc->y);
2634 drm_modeset_unlock(&crtc->mutex);
2635 }
2636 }
2637
2638 static int
2639 intel_finish_fb(struct drm_framebuffer *old_fb)
2640 {
2641 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2642 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2643 bool was_interruptible = dev_priv->mm.interruptible;
2644 int ret;
2645
2646 /* Big Hammer, we also need to ensure that any pending
2647 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2648 * current scanout is retired before unpinning the old
2649 * framebuffer.
2650 *
2651 * This should only fail upon a hung GPU, in which case we
2652 * can safely continue.
2653 */
2654 dev_priv->mm.interruptible = false;
2655 ret = i915_gem_object_finish_gpu(obj);
2656 dev_priv->mm.interruptible = was_interruptible;
2657
2658 return ret;
2659 }
2660
2661 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2662 {
2663 struct drm_device *dev = crtc->dev;
2664 struct drm_i915_private *dev_priv = dev->dev_private;
2665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2666 unsigned long flags;
2667 bool pending;
2668
2669 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2670 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2671 return false;
2672
2673 spin_lock_irqsave(&dev->event_lock, flags);
2674 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2675 spin_unlock_irqrestore(&dev->event_lock, flags);
2676
2677 return pending;
2678 }
2679
2680 static int
2681 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2682 struct drm_framebuffer *fb)
2683 {
2684 struct drm_device *dev = crtc->dev;
2685 struct drm_i915_private *dev_priv = dev->dev_private;
2686 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2687 struct drm_framebuffer *old_fb;
2688 int ret;
2689
2690 if (intel_crtc_has_pending_flip(crtc)) {
2691 DRM_ERROR("pipe is still busy with an old pageflip\n");
2692 return -EBUSY;
2693 }
2694
2695 /* no fb bound */
2696 if (!fb) {
2697 DRM_ERROR("No FB bound\n");
2698 return 0;
2699 }
2700
2701 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2702 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2703 plane_name(intel_crtc->plane),
2704 INTEL_INFO(dev)->num_pipes);
2705 return -EINVAL;
2706 }
2707
2708 mutex_lock(&dev->struct_mutex);
2709 ret = intel_pin_and_fence_fb_obj(dev,
2710 to_intel_framebuffer(fb)->obj,
2711 NULL);
2712 mutex_unlock(&dev->struct_mutex);
2713 if (ret != 0) {
2714 DRM_ERROR("pin & fence failed\n");
2715 return ret;
2716 }
2717
2718 /*
2719 * Update pipe size and adjust fitter if needed: the reason for this is
2720 * that in compute_mode_changes we check the native mode (not the pfit
2721 * mode) to see if we can flip rather than do a full mode set. In the
2722 * fastboot case, we'll flip, but if we don't update the pipesrc and
2723 * pfit state, we'll end up with a big fb scanned out into the wrong
2724 * sized surface.
2725 *
2726 * To fix this properly, we need to hoist the checks up into
2727 * compute_mode_changes (or above), check the actual pfit state and
2728 * whether the platform allows pfit disable with pipe active, and only
2729 * then update the pipesrc and pfit state, even on the flip path.
2730 */
2731 if (i915.fastboot) {
2732 const struct drm_display_mode *adjusted_mode =
2733 &intel_crtc->config.adjusted_mode;
2734
2735 I915_WRITE(PIPESRC(intel_crtc->pipe),
2736 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2737 (adjusted_mode->crtc_vdisplay - 1));
2738 if (!intel_crtc->config.pch_pfit.enabled &&
2739 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2740 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2741 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2742 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2743 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2744 }
2745 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2746 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2747 }
2748
2749 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2750
2751 old_fb = crtc->primary->fb;
2752 crtc->primary->fb = fb;
2753 crtc->x = x;
2754 crtc->y = y;
2755
2756 if (old_fb) {
2757 if (intel_crtc->active && old_fb != fb)
2758 intel_wait_for_vblank(dev, intel_crtc->pipe);
2759 mutex_lock(&dev->struct_mutex);
2760 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2761 mutex_unlock(&dev->struct_mutex);
2762 }
2763
2764 mutex_lock(&dev->struct_mutex);
2765 intel_update_fbc(dev);
2766 mutex_unlock(&dev->struct_mutex);
2767
2768 return 0;
2769 }
2770
2771 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2772 {
2773 struct drm_device *dev = crtc->dev;
2774 struct drm_i915_private *dev_priv = dev->dev_private;
2775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2776 int pipe = intel_crtc->pipe;
2777 u32 reg, temp;
2778
2779 /* enable normal train */
2780 reg = FDI_TX_CTL(pipe);
2781 temp = I915_READ(reg);
2782 if (IS_IVYBRIDGE(dev)) {
2783 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2784 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2785 } else {
2786 temp &= ~FDI_LINK_TRAIN_NONE;
2787 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2788 }
2789 I915_WRITE(reg, temp);
2790
2791 reg = FDI_RX_CTL(pipe);
2792 temp = I915_READ(reg);
2793 if (HAS_PCH_CPT(dev)) {
2794 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2795 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2796 } else {
2797 temp &= ~FDI_LINK_TRAIN_NONE;
2798 temp |= FDI_LINK_TRAIN_NONE;
2799 }
2800 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2801
2802 /* wait one idle pattern time */
2803 POSTING_READ(reg);
2804 udelay(1000);
2805
2806 /* IVB wants error correction enabled */
2807 if (IS_IVYBRIDGE(dev))
2808 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2809 FDI_FE_ERRC_ENABLE);
2810 }
2811
2812 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2813 {
2814 return crtc->base.enabled && crtc->active &&
2815 crtc->config.has_pch_encoder;
2816 }
2817
2818 static void ivb_modeset_global_resources(struct drm_device *dev)
2819 {
2820 struct drm_i915_private *dev_priv = dev->dev_private;
2821 struct intel_crtc *pipe_B_crtc =
2822 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2823 struct intel_crtc *pipe_C_crtc =
2824 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2825 uint32_t temp;
2826
2827 /*
2828 * When everything is off disable fdi C so that we could enable fdi B
2829 * with all lanes. Note that we don't care about enabled pipes without
2830 * an enabled pch encoder.
2831 */
2832 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2833 !pipe_has_enabled_pch(pipe_C_crtc)) {
2834 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2835 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2836
2837 temp = I915_READ(SOUTH_CHICKEN1);
2838 temp &= ~FDI_BC_BIFURCATION_SELECT;
2839 DRM_DEBUG_KMS("disabling fdi C rx\n");
2840 I915_WRITE(SOUTH_CHICKEN1, temp);
2841 }
2842 }
2843
2844 /* The FDI link training functions for ILK/Ibexpeak. */
2845 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2846 {
2847 struct drm_device *dev = crtc->dev;
2848 struct drm_i915_private *dev_priv = dev->dev_private;
2849 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2850 int pipe = intel_crtc->pipe;
2851 u32 reg, temp, tries;
2852
2853 /* FDI needs bits from pipe first */
2854 assert_pipe_enabled(dev_priv, pipe);
2855
2856 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2857 for train result */
2858 reg = FDI_RX_IMR(pipe);
2859 temp = I915_READ(reg);
2860 temp &= ~FDI_RX_SYMBOL_LOCK;
2861 temp &= ~FDI_RX_BIT_LOCK;
2862 I915_WRITE(reg, temp);
2863 I915_READ(reg);
2864 udelay(150);
2865
2866 /* enable CPU FDI TX and PCH FDI RX */
2867 reg = FDI_TX_CTL(pipe);
2868 temp = I915_READ(reg);
2869 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2870 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2871 temp &= ~FDI_LINK_TRAIN_NONE;
2872 temp |= FDI_LINK_TRAIN_PATTERN_1;
2873 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2874
2875 reg = FDI_RX_CTL(pipe);
2876 temp = I915_READ(reg);
2877 temp &= ~FDI_LINK_TRAIN_NONE;
2878 temp |= FDI_LINK_TRAIN_PATTERN_1;
2879 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2880
2881 POSTING_READ(reg);
2882 udelay(150);
2883
2884 /* Ironlake workaround, enable clock pointer after FDI enable*/
2885 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2886 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2887 FDI_RX_PHASE_SYNC_POINTER_EN);
2888
2889 reg = FDI_RX_IIR(pipe);
2890 for (tries = 0; tries < 5; tries++) {
2891 temp = I915_READ(reg);
2892 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2893
2894 if ((temp & FDI_RX_BIT_LOCK)) {
2895 DRM_DEBUG_KMS("FDI train 1 done.\n");
2896 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2897 break;
2898 }
2899 }
2900 if (tries == 5)
2901 DRM_ERROR("FDI train 1 fail!\n");
2902
2903 /* Train 2 */
2904 reg = FDI_TX_CTL(pipe);
2905 temp = I915_READ(reg);
2906 temp &= ~FDI_LINK_TRAIN_NONE;
2907 temp |= FDI_LINK_TRAIN_PATTERN_2;
2908 I915_WRITE(reg, temp);
2909
2910 reg = FDI_RX_CTL(pipe);
2911 temp = I915_READ(reg);
2912 temp &= ~FDI_LINK_TRAIN_NONE;
2913 temp |= FDI_LINK_TRAIN_PATTERN_2;
2914 I915_WRITE(reg, temp);
2915
2916 POSTING_READ(reg);
2917 udelay(150);
2918
2919 reg = FDI_RX_IIR(pipe);
2920 for (tries = 0; tries < 5; tries++) {
2921 temp = I915_READ(reg);
2922 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2923
2924 if (temp & FDI_RX_SYMBOL_LOCK) {
2925 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2926 DRM_DEBUG_KMS("FDI train 2 done.\n");
2927 break;
2928 }
2929 }
2930 if (tries == 5)
2931 DRM_ERROR("FDI train 2 fail!\n");
2932
2933 DRM_DEBUG_KMS("FDI train done\n");
2934
2935 }
2936
2937 static const int snb_b_fdi_train_param[] = {
2938 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2939 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2940 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2941 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2942 };
2943
2944 /* The FDI link training functions for SNB/Cougarpoint. */
2945 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2946 {
2947 struct drm_device *dev = crtc->dev;
2948 struct drm_i915_private *dev_priv = dev->dev_private;
2949 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2950 int pipe = intel_crtc->pipe;
2951 u32 reg, temp, i, retry;
2952
2953 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2954 for train result */
2955 reg = FDI_RX_IMR(pipe);
2956 temp = I915_READ(reg);
2957 temp &= ~FDI_RX_SYMBOL_LOCK;
2958 temp &= ~FDI_RX_BIT_LOCK;
2959 I915_WRITE(reg, temp);
2960
2961 POSTING_READ(reg);
2962 udelay(150);
2963
2964 /* enable CPU FDI TX and PCH FDI RX */
2965 reg = FDI_TX_CTL(pipe);
2966 temp = I915_READ(reg);
2967 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2968 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2969 temp &= ~FDI_LINK_TRAIN_NONE;
2970 temp |= FDI_LINK_TRAIN_PATTERN_1;
2971 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2972 /* SNB-B */
2973 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2974 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2975
2976 I915_WRITE(FDI_RX_MISC(pipe),
2977 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2978
2979 reg = FDI_RX_CTL(pipe);
2980 temp = I915_READ(reg);
2981 if (HAS_PCH_CPT(dev)) {
2982 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2983 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2984 } else {
2985 temp &= ~FDI_LINK_TRAIN_NONE;
2986 temp |= FDI_LINK_TRAIN_PATTERN_1;
2987 }
2988 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2989
2990 POSTING_READ(reg);
2991 udelay(150);
2992
2993 for (i = 0; i < 4; i++) {
2994 reg = FDI_TX_CTL(pipe);
2995 temp = I915_READ(reg);
2996 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2997 temp |= snb_b_fdi_train_param[i];
2998 I915_WRITE(reg, temp);
2999
3000 POSTING_READ(reg);
3001 udelay(500);
3002
3003 for (retry = 0; retry < 5; retry++) {
3004 reg = FDI_RX_IIR(pipe);
3005 temp = I915_READ(reg);
3006 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3007 if (temp & FDI_RX_BIT_LOCK) {
3008 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3009 DRM_DEBUG_KMS("FDI train 1 done.\n");
3010 break;
3011 }
3012 udelay(50);
3013 }
3014 if (retry < 5)
3015 break;
3016 }
3017 if (i == 4)
3018 DRM_ERROR("FDI train 1 fail!\n");
3019
3020 /* Train 2 */
3021 reg = FDI_TX_CTL(pipe);
3022 temp = I915_READ(reg);
3023 temp &= ~FDI_LINK_TRAIN_NONE;
3024 temp |= FDI_LINK_TRAIN_PATTERN_2;
3025 if (IS_GEN6(dev)) {
3026 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3027 /* SNB-B */
3028 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3029 }
3030 I915_WRITE(reg, temp);
3031
3032 reg = FDI_RX_CTL(pipe);
3033 temp = I915_READ(reg);
3034 if (HAS_PCH_CPT(dev)) {
3035 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3036 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3037 } else {
3038 temp &= ~FDI_LINK_TRAIN_NONE;
3039 temp |= FDI_LINK_TRAIN_PATTERN_2;
3040 }
3041 I915_WRITE(reg, temp);
3042
3043 POSTING_READ(reg);
3044 udelay(150);
3045
3046 for (i = 0; i < 4; i++) {
3047 reg = FDI_TX_CTL(pipe);
3048 temp = I915_READ(reg);
3049 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3050 temp |= snb_b_fdi_train_param[i];
3051 I915_WRITE(reg, temp);
3052
3053 POSTING_READ(reg);
3054 udelay(500);
3055
3056 for (retry = 0; retry < 5; retry++) {
3057 reg = FDI_RX_IIR(pipe);
3058 temp = I915_READ(reg);
3059 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3060 if (temp & FDI_RX_SYMBOL_LOCK) {
3061 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3062 DRM_DEBUG_KMS("FDI train 2 done.\n");
3063 break;
3064 }
3065 udelay(50);
3066 }
3067 if (retry < 5)
3068 break;
3069 }
3070 if (i == 4)
3071 DRM_ERROR("FDI train 2 fail!\n");
3072
3073 DRM_DEBUG_KMS("FDI train done.\n");
3074 }
3075
3076 /* Manual link training for Ivy Bridge A0 parts */
3077 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3078 {
3079 struct drm_device *dev = crtc->dev;
3080 struct drm_i915_private *dev_priv = dev->dev_private;
3081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3082 int pipe = intel_crtc->pipe;
3083 u32 reg, temp, i, j;
3084
3085 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3086 for train result */
3087 reg = FDI_RX_IMR(pipe);
3088 temp = I915_READ(reg);
3089 temp &= ~FDI_RX_SYMBOL_LOCK;
3090 temp &= ~FDI_RX_BIT_LOCK;
3091 I915_WRITE(reg, temp);
3092
3093 POSTING_READ(reg);
3094 udelay(150);
3095
3096 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3097 I915_READ(FDI_RX_IIR(pipe)));
3098
3099 /* Try each vswing and preemphasis setting twice before moving on */
3100 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3101 /* disable first in case we need to retry */
3102 reg = FDI_TX_CTL(pipe);
3103 temp = I915_READ(reg);
3104 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3105 temp &= ~FDI_TX_ENABLE;
3106 I915_WRITE(reg, temp);
3107
3108 reg = FDI_RX_CTL(pipe);
3109 temp = I915_READ(reg);
3110 temp &= ~FDI_LINK_TRAIN_AUTO;
3111 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3112 temp &= ~FDI_RX_ENABLE;
3113 I915_WRITE(reg, temp);
3114
3115 /* enable CPU FDI TX and PCH FDI RX */
3116 reg = FDI_TX_CTL(pipe);
3117 temp = I915_READ(reg);
3118 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3119 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3120 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3121 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3122 temp |= snb_b_fdi_train_param[j/2];
3123 temp |= FDI_COMPOSITE_SYNC;
3124 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3125
3126 I915_WRITE(FDI_RX_MISC(pipe),
3127 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3128
3129 reg = FDI_RX_CTL(pipe);
3130 temp = I915_READ(reg);
3131 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3132 temp |= FDI_COMPOSITE_SYNC;
3133 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3134
3135 POSTING_READ(reg);
3136 udelay(1); /* should be 0.5us */
3137
3138 for (i = 0; i < 4; i++) {
3139 reg = FDI_RX_IIR(pipe);
3140 temp = I915_READ(reg);
3141 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3142
3143 if (temp & FDI_RX_BIT_LOCK ||
3144 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3145 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3146 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3147 i);
3148 break;
3149 }
3150 udelay(1); /* should be 0.5us */
3151 }
3152 if (i == 4) {
3153 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3154 continue;
3155 }
3156
3157 /* Train 2 */
3158 reg = FDI_TX_CTL(pipe);
3159 temp = I915_READ(reg);
3160 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3161 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3162 I915_WRITE(reg, temp);
3163
3164 reg = FDI_RX_CTL(pipe);
3165 temp = I915_READ(reg);
3166 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3167 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3168 I915_WRITE(reg, temp);
3169
3170 POSTING_READ(reg);
3171 udelay(2); /* should be 1.5us */
3172
3173 for (i = 0; i < 4; i++) {
3174 reg = FDI_RX_IIR(pipe);
3175 temp = I915_READ(reg);
3176 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3177
3178 if (temp & FDI_RX_SYMBOL_LOCK ||
3179 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3180 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3181 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3182 i);
3183 goto train_done;
3184 }
3185 udelay(2); /* should be 1.5us */
3186 }
3187 if (i == 4)
3188 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3189 }
3190
3191 train_done:
3192 DRM_DEBUG_KMS("FDI train done.\n");
3193 }
3194
3195 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3196 {
3197 struct drm_device *dev = intel_crtc->base.dev;
3198 struct drm_i915_private *dev_priv = dev->dev_private;
3199 int pipe = intel_crtc->pipe;
3200 u32 reg, temp;
3201
3202
3203 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3204 reg = FDI_RX_CTL(pipe);
3205 temp = I915_READ(reg);
3206 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3207 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3208 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3209 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3210
3211 POSTING_READ(reg);
3212 udelay(200);
3213
3214 /* Switch from Rawclk to PCDclk */
3215 temp = I915_READ(reg);
3216 I915_WRITE(reg, temp | FDI_PCDCLK);
3217
3218 POSTING_READ(reg);
3219 udelay(200);
3220
3221 /* Enable CPU FDI TX PLL, always on for Ironlake */
3222 reg = FDI_TX_CTL(pipe);
3223 temp = I915_READ(reg);
3224 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3225 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3226
3227 POSTING_READ(reg);
3228 udelay(100);
3229 }
3230 }
3231
3232 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3233 {
3234 struct drm_device *dev = intel_crtc->base.dev;
3235 struct drm_i915_private *dev_priv = dev->dev_private;
3236 int pipe = intel_crtc->pipe;
3237 u32 reg, temp;
3238
3239 /* Switch from PCDclk to Rawclk */
3240 reg = FDI_RX_CTL(pipe);
3241 temp = I915_READ(reg);
3242 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3243
3244 /* Disable CPU FDI TX PLL */
3245 reg = FDI_TX_CTL(pipe);
3246 temp = I915_READ(reg);
3247 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3248
3249 POSTING_READ(reg);
3250 udelay(100);
3251
3252 reg = FDI_RX_CTL(pipe);
3253 temp = I915_READ(reg);
3254 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3255
3256 /* Wait for the clocks to turn off. */
3257 POSTING_READ(reg);
3258 udelay(100);
3259 }
3260
3261 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3262 {
3263 struct drm_device *dev = crtc->dev;
3264 struct drm_i915_private *dev_priv = dev->dev_private;
3265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3266 int pipe = intel_crtc->pipe;
3267 u32 reg, temp;
3268
3269 /* disable CPU FDI tx and PCH FDI rx */
3270 reg = FDI_TX_CTL(pipe);
3271 temp = I915_READ(reg);
3272 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3273 POSTING_READ(reg);
3274
3275 reg = FDI_RX_CTL(pipe);
3276 temp = I915_READ(reg);
3277 temp &= ~(0x7 << 16);
3278 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3279 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3280
3281 POSTING_READ(reg);
3282 udelay(100);
3283
3284 /* Ironlake workaround, disable clock pointer after downing FDI */
3285 if (HAS_PCH_IBX(dev))
3286 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3287
3288 /* still set train pattern 1 */
3289 reg = FDI_TX_CTL(pipe);
3290 temp = I915_READ(reg);
3291 temp &= ~FDI_LINK_TRAIN_NONE;
3292 temp |= FDI_LINK_TRAIN_PATTERN_1;
3293 I915_WRITE(reg, temp);
3294
3295 reg = FDI_RX_CTL(pipe);
3296 temp = I915_READ(reg);
3297 if (HAS_PCH_CPT(dev)) {
3298 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3299 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3300 } else {
3301 temp &= ~FDI_LINK_TRAIN_NONE;
3302 temp |= FDI_LINK_TRAIN_PATTERN_1;
3303 }
3304 /* BPC in FDI rx is consistent with that in PIPECONF */
3305 temp &= ~(0x07 << 16);
3306 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3307 I915_WRITE(reg, temp);
3308
3309 POSTING_READ(reg);
3310 udelay(100);
3311 }
3312
3313 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3314 {
3315 struct intel_crtc *crtc;
3316
3317 /* Note that we don't need to be called with mode_config.lock here
3318 * as our list of CRTC objects is static for the lifetime of the
3319 * device and so cannot disappear as we iterate. Similarly, we can
3320 * happily treat the predicates as racy, atomic checks as userspace
3321 * cannot claim and pin a new fb without at least acquring the
3322 * struct_mutex and so serialising with us.
3323 */
3324 for_each_intel_crtc(dev, crtc) {
3325 if (atomic_read(&crtc->unpin_work_count) == 0)
3326 continue;
3327
3328 if (crtc->unpin_work)
3329 intel_wait_for_vblank(dev, crtc->pipe);
3330
3331 return true;
3332 }
3333
3334 return false;
3335 }
3336
3337 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3338 {
3339 struct drm_device *dev = crtc->dev;
3340 struct drm_i915_private *dev_priv = dev->dev_private;
3341
3342 if (crtc->primary->fb == NULL)
3343 return;
3344
3345 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3346
3347 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3348 !intel_crtc_has_pending_flip(crtc),
3349 60*HZ) == 0);
3350
3351 mutex_lock(&dev->struct_mutex);
3352 intel_finish_fb(crtc->primary->fb);
3353 mutex_unlock(&dev->struct_mutex);
3354 }
3355
3356 /* Program iCLKIP clock to the desired frequency */
3357 static void lpt_program_iclkip(struct drm_crtc *crtc)
3358 {
3359 struct drm_device *dev = crtc->dev;
3360 struct drm_i915_private *dev_priv = dev->dev_private;
3361 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3362 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3363 u32 temp;
3364
3365 mutex_lock(&dev_priv->dpio_lock);
3366
3367 /* It is necessary to ungate the pixclk gate prior to programming
3368 * the divisors, and gate it back when it is done.
3369 */
3370 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3371
3372 /* Disable SSCCTL */
3373 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3374 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3375 SBI_SSCCTL_DISABLE,
3376 SBI_ICLK);
3377
3378 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3379 if (clock == 20000) {
3380 auxdiv = 1;
3381 divsel = 0x41;
3382 phaseinc = 0x20;
3383 } else {
3384 /* The iCLK virtual clock root frequency is in MHz,
3385 * but the adjusted_mode->crtc_clock in in KHz. To get the
3386 * divisors, it is necessary to divide one by another, so we
3387 * convert the virtual clock precision to KHz here for higher
3388 * precision.
3389 */
3390 u32 iclk_virtual_root_freq = 172800 * 1000;
3391 u32 iclk_pi_range = 64;
3392 u32 desired_divisor, msb_divisor_value, pi_value;
3393
3394 desired_divisor = (iclk_virtual_root_freq / clock);
3395 msb_divisor_value = desired_divisor / iclk_pi_range;
3396 pi_value = desired_divisor % iclk_pi_range;
3397
3398 auxdiv = 0;
3399 divsel = msb_divisor_value - 2;
3400 phaseinc = pi_value;
3401 }
3402
3403 /* This should not happen with any sane values */
3404 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3405 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3406 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3407 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3408
3409 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3410 clock,
3411 auxdiv,
3412 divsel,
3413 phasedir,
3414 phaseinc);
3415
3416 /* Program SSCDIVINTPHASE6 */
3417 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3418 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3419 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3420 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3421 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3422 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3423 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3424 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3425
3426 /* Program SSCAUXDIV */
3427 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3428 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3429 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3430 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3431
3432 /* Enable modulator and associated divider */
3433 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3434 temp &= ~SBI_SSCCTL_DISABLE;
3435 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3436
3437 /* Wait for initialization time */
3438 udelay(24);
3439
3440 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3441
3442 mutex_unlock(&dev_priv->dpio_lock);
3443 }
3444
3445 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3446 enum pipe pch_transcoder)
3447 {
3448 struct drm_device *dev = crtc->base.dev;
3449 struct drm_i915_private *dev_priv = dev->dev_private;
3450 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3451
3452 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3453 I915_READ(HTOTAL(cpu_transcoder)));
3454 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3455 I915_READ(HBLANK(cpu_transcoder)));
3456 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3457 I915_READ(HSYNC(cpu_transcoder)));
3458
3459 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3460 I915_READ(VTOTAL(cpu_transcoder)));
3461 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3462 I915_READ(VBLANK(cpu_transcoder)));
3463 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3464 I915_READ(VSYNC(cpu_transcoder)));
3465 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3466 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3467 }
3468
3469 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3470 {
3471 struct drm_i915_private *dev_priv = dev->dev_private;
3472 uint32_t temp;
3473
3474 temp = I915_READ(SOUTH_CHICKEN1);
3475 if (temp & FDI_BC_BIFURCATION_SELECT)
3476 return;
3477
3478 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3479 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3480
3481 temp |= FDI_BC_BIFURCATION_SELECT;
3482 DRM_DEBUG_KMS("enabling fdi C rx\n");
3483 I915_WRITE(SOUTH_CHICKEN1, temp);
3484 POSTING_READ(SOUTH_CHICKEN1);
3485 }
3486
3487 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3488 {
3489 struct drm_device *dev = intel_crtc->base.dev;
3490 struct drm_i915_private *dev_priv = dev->dev_private;
3491
3492 switch (intel_crtc->pipe) {
3493 case PIPE_A:
3494 break;
3495 case PIPE_B:
3496 if (intel_crtc->config.fdi_lanes > 2)
3497 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3498 else
3499 cpt_enable_fdi_bc_bifurcation(dev);
3500
3501 break;
3502 case PIPE_C:
3503 cpt_enable_fdi_bc_bifurcation(dev);
3504
3505 break;
3506 default:
3507 BUG();
3508 }
3509 }
3510
3511 /*
3512 * Enable PCH resources required for PCH ports:
3513 * - PCH PLLs
3514 * - FDI training & RX/TX
3515 * - update transcoder timings
3516 * - DP transcoding bits
3517 * - transcoder
3518 */
3519 static void ironlake_pch_enable(struct drm_crtc *crtc)
3520 {
3521 struct drm_device *dev = crtc->dev;
3522 struct drm_i915_private *dev_priv = dev->dev_private;
3523 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3524 int pipe = intel_crtc->pipe;
3525 u32 reg, temp;
3526
3527 assert_pch_transcoder_disabled(dev_priv, pipe);
3528
3529 if (IS_IVYBRIDGE(dev))
3530 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3531
3532 /* Write the TU size bits before fdi link training, so that error
3533 * detection works. */
3534 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3535 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3536
3537 /* For PCH output, training FDI link */
3538 dev_priv->display.fdi_link_train(crtc);
3539
3540 /* We need to program the right clock selection before writing the pixel
3541 * mutliplier into the DPLL. */
3542 if (HAS_PCH_CPT(dev)) {
3543 u32 sel;
3544
3545 temp = I915_READ(PCH_DPLL_SEL);
3546 temp |= TRANS_DPLL_ENABLE(pipe);
3547 sel = TRANS_DPLLB_SEL(pipe);
3548 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3549 temp |= sel;
3550 else
3551 temp &= ~sel;
3552 I915_WRITE(PCH_DPLL_SEL, temp);
3553 }
3554
3555 /* XXX: pch pll's can be enabled any time before we enable the PCH
3556 * transcoder, and we actually should do this to not upset any PCH
3557 * transcoder that already use the clock when we share it.
3558 *
3559 * Note that enable_shared_dpll tries to do the right thing, but
3560 * get_shared_dpll unconditionally resets the pll - we need that to have
3561 * the right LVDS enable sequence. */
3562 intel_enable_shared_dpll(intel_crtc);
3563
3564 /* set transcoder timing, panel must allow it */
3565 assert_panel_unlocked(dev_priv, pipe);
3566 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3567
3568 intel_fdi_normal_train(crtc);
3569
3570 /* For PCH DP, enable TRANS_DP_CTL */
3571 if (HAS_PCH_CPT(dev) &&
3572 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3573 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3574 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3575 reg = TRANS_DP_CTL(pipe);
3576 temp = I915_READ(reg);
3577 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3578 TRANS_DP_SYNC_MASK |
3579 TRANS_DP_BPC_MASK);
3580 temp |= (TRANS_DP_OUTPUT_ENABLE |
3581 TRANS_DP_ENH_FRAMING);
3582 temp |= bpc << 9; /* same format but at 11:9 */
3583
3584 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3585 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3586 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3587 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3588
3589 switch (intel_trans_dp_port_sel(crtc)) {
3590 case PCH_DP_B:
3591 temp |= TRANS_DP_PORT_SEL_B;
3592 break;
3593 case PCH_DP_C:
3594 temp |= TRANS_DP_PORT_SEL_C;
3595 break;
3596 case PCH_DP_D:
3597 temp |= TRANS_DP_PORT_SEL_D;
3598 break;
3599 default:
3600 BUG();
3601 }
3602
3603 I915_WRITE(reg, temp);
3604 }
3605
3606 ironlake_enable_pch_transcoder(dev_priv, pipe);
3607 }
3608
3609 static void lpt_pch_enable(struct drm_crtc *crtc)
3610 {
3611 struct drm_device *dev = crtc->dev;
3612 struct drm_i915_private *dev_priv = dev->dev_private;
3613 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3614 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3615
3616 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3617
3618 lpt_program_iclkip(crtc);
3619
3620 /* Set transcoder timing. */
3621 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3622
3623 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3624 }
3625
3626 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3627 {
3628 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3629
3630 if (pll == NULL)
3631 return;
3632
3633 if (pll->refcount == 0) {
3634 WARN(1, "bad %s refcount\n", pll->name);
3635 return;
3636 }
3637
3638 if (--pll->refcount == 0) {
3639 WARN_ON(pll->on);
3640 WARN_ON(pll->active);
3641 }
3642
3643 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3644 }
3645
3646 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3647 {
3648 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3649 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3650 enum intel_dpll_id i;
3651
3652 if (pll) {
3653 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3654 crtc->base.base.id, pll->name);
3655 intel_put_shared_dpll(crtc);
3656 }
3657
3658 if (HAS_PCH_IBX(dev_priv->dev)) {
3659 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3660 i = (enum intel_dpll_id) crtc->pipe;
3661 pll = &dev_priv->shared_dplls[i];
3662
3663 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3664 crtc->base.base.id, pll->name);
3665
3666 WARN_ON(pll->refcount);
3667
3668 goto found;
3669 }
3670
3671 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3672 pll = &dev_priv->shared_dplls[i];
3673
3674 /* Only want to check enabled timings first */
3675 if (pll->refcount == 0)
3676 continue;
3677
3678 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3679 sizeof(pll->hw_state)) == 0) {
3680 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3681 crtc->base.base.id,
3682 pll->name, pll->refcount, pll->active);
3683
3684 goto found;
3685 }
3686 }
3687
3688 /* Ok no matching timings, maybe there's a free one? */
3689 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3690 pll = &dev_priv->shared_dplls[i];
3691 if (pll->refcount == 0) {
3692 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3693 crtc->base.base.id, pll->name);
3694 goto found;
3695 }
3696 }
3697
3698 return NULL;
3699
3700 found:
3701 if (pll->refcount == 0)
3702 pll->hw_state = crtc->config.dpll_hw_state;
3703
3704 crtc->config.shared_dpll = i;
3705 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3706 pipe_name(crtc->pipe));
3707
3708 pll->refcount++;
3709
3710 return pll;
3711 }
3712
3713 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3714 {
3715 struct drm_i915_private *dev_priv = dev->dev_private;
3716 int dslreg = PIPEDSL(pipe);
3717 u32 temp;
3718
3719 temp = I915_READ(dslreg);
3720 udelay(500);
3721 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3722 if (wait_for(I915_READ(dslreg) != temp, 5))
3723 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3724 }
3725 }
3726
3727 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3728 {
3729 struct drm_device *dev = crtc->base.dev;
3730 struct drm_i915_private *dev_priv = dev->dev_private;
3731 int pipe = crtc->pipe;
3732
3733 if (crtc->config.pch_pfit.enabled) {
3734 /* Force use of hard-coded filter coefficients
3735 * as some pre-programmed values are broken,
3736 * e.g. x201.
3737 */
3738 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3739 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3740 PF_PIPE_SEL_IVB(pipe));
3741 else
3742 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3743 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3744 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3745 }
3746 }
3747
3748 static void intel_enable_planes(struct drm_crtc *crtc)
3749 {
3750 struct drm_device *dev = crtc->dev;
3751 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3752 struct drm_plane *plane;
3753 struct intel_plane *intel_plane;
3754
3755 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3756 intel_plane = to_intel_plane(plane);
3757 if (intel_plane->pipe == pipe)
3758 intel_plane_restore(&intel_plane->base);
3759 }
3760 }
3761
3762 static void intel_disable_planes(struct drm_crtc *crtc)
3763 {
3764 struct drm_device *dev = crtc->dev;
3765 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3766 struct drm_plane *plane;
3767 struct intel_plane *intel_plane;
3768
3769 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3770 intel_plane = to_intel_plane(plane);
3771 if (intel_plane->pipe == pipe)
3772 intel_plane_disable(&intel_plane->base);
3773 }
3774 }
3775
3776 void hsw_enable_ips(struct intel_crtc *crtc)
3777 {
3778 struct drm_device *dev = crtc->base.dev;
3779 struct drm_i915_private *dev_priv = dev->dev_private;
3780
3781 if (!crtc->config.ips_enabled)
3782 return;
3783
3784 /* We can only enable IPS after we enable a plane and wait for a vblank */
3785 intel_wait_for_vblank(dev, crtc->pipe);
3786
3787 assert_plane_enabled(dev_priv, crtc->plane);
3788 if (IS_BROADWELL(dev)) {
3789 mutex_lock(&dev_priv->rps.hw_lock);
3790 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3791 mutex_unlock(&dev_priv->rps.hw_lock);
3792 /* Quoting Art Runyan: "its not safe to expect any particular
3793 * value in IPS_CTL bit 31 after enabling IPS through the
3794 * mailbox." Moreover, the mailbox may return a bogus state,
3795 * so we need to just enable it and continue on.
3796 */
3797 } else {
3798 I915_WRITE(IPS_CTL, IPS_ENABLE);
3799 /* The bit only becomes 1 in the next vblank, so this wait here
3800 * is essentially intel_wait_for_vblank. If we don't have this
3801 * and don't wait for vblanks until the end of crtc_enable, then
3802 * the HW state readout code will complain that the expected
3803 * IPS_CTL value is not the one we read. */
3804 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3805 DRM_ERROR("Timed out waiting for IPS enable\n");
3806 }
3807 }
3808
3809 void hsw_disable_ips(struct intel_crtc *crtc)
3810 {
3811 struct drm_device *dev = crtc->base.dev;
3812 struct drm_i915_private *dev_priv = dev->dev_private;
3813
3814 if (!crtc->config.ips_enabled)
3815 return;
3816
3817 assert_plane_enabled(dev_priv, crtc->plane);
3818 if (IS_BROADWELL(dev)) {
3819 mutex_lock(&dev_priv->rps.hw_lock);
3820 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3821 mutex_unlock(&dev_priv->rps.hw_lock);
3822 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3823 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3824 DRM_ERROR("Timed out waiting for IPS disable\n");
3825 } else {
3826 I915_WRITE(IPS_CTL, 0);
3827 POSTING_READ(IPS_CTL);
3828 }
3829
3830 /* We need to wait for a vblank before we can disable the plane. */
3831 intel_wait_for_vblank(dev, crtc->pipe);
3832 }
3833
3834 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3835 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3836 {
3837 struct drm_device *dev = crtc->dev;
3838 struct drm_i915_private *dev_priv = dev->dev_private;
3839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3840 enum pipe pipe = intel_crtc->pipe;
3841 int palreg = PALETTE(pipe);
3842 int i;
3843 bool reenable_ips = false;
3844
3845 /* The clocks have to be on to load the palette. */
3846 if (!crtc->enabled || !intel_crtc->active)
3847 return;
3848
3849 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3850 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3851 assert_dsi_pll_enabled(dev_priv);
3852 else
3853 assert_pll_enabled(dev_priv, pipe);
3854 }
3855
3856 /* use legacy palette for Ironlake */
3857 if (HAS_PCH_SPLIT(dev))
3858 palreg = LGC_PALETTE(pipe);
3859
3860 /* Workaround : Do not read or write the pipe palette/gamma data while
3861 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3862 */
3863 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3864 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3865 GAMMA_MODE_MODE_SPLIT)) {
3866 hsw_disable_ips(intel_crtc);
3867 reenable_ips = true;
3868 }
3869
3870 for (i = 0; i < 256; i++) {
3871 I915_WRITE(palreg + 4 * i,
3872 (intel_crtc->lut_r[i] << 16) |
3873 (intel_crtc->lut_g[i] << 8) |
3874 intel_crtc->lut_b[i]);
3875 }
3876
3877 if (reenable_ips)
3878 hsw_enable_ips(intel_crtc);
3879 }
3880
3881 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3882 {
3883 if (!enable && intel_crtc->overlay) {
3884 struct drm_device *dev = intel_crtc->base.dev;
3885 struct drm_i915_private *dev_priv = dev->dev_private;
3886
3887 mutex_lock(&dev->struct_mutex);
3888 dev_priv->mm.interruptible = false;
3889 (void) intel_overlay_switch_off(intel_crtc->overlay);
3890 dev_priv->mm.interruptible = true;
3891 mutex_unlock(&dev->struct_mutex);
3892 }
3893
3894 /* Let userspace switch the overlay on again. In most cases userspace
3895 * has to recompute where to put it anyway.
3896 */
3897 }
3898
3899 /**
3900 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3901 * cursor plane briefly if not already running after enabling the display
3902 * plane.
3903 * This workaround avoids occasional blank screens when self refresh is
3904 * enabled.
3905 */
3906 static void
3907 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3908 {
3909 u32 cntl = I915_READ(CURCNTR(pipe));
3910
3911 if ((cntl & CURSOR_MODE) == 0) {
3912 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3913
3914 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3915 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3916 intel_wait_for_vblank(dev_priv->dev, pipe);
3917 I915_WRITE(CURCNTR(pipe), cntl);
3918 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3919 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3920 }
3921 }
3922
3923 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3924 {
3925 struct drm_device *dev = crtc->dev;
3926 struct drm_i915_private *dev_priv = dev->dev_private;
3927 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3928 int pipe = intel_crtc->pipe;
3929 int plane = intel_crtc->plane;
3930
3931 drm_vblank_on(dev, pipe);
3932
3933 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3934 intel_enable_planes(crtc);
3935 /* The fixup needs to happen before cursor is enabled */
3936 if (IS_G4X(dev))
3937 g4x_fixup_plane(dev_priv, pipe);
3938 intel_crtc_update_cursor(crtc, true);
3939 intel_crtc_dpms_overlay(intel_crtc, true);
3940
3941 hsw_enable_ips(intel_crtc);
3942
3943 mutex_lock(&dev->struct_mutex);
3944 intel_update_fbc(dev);
3945 mutex_unlock(&dev->struct_mutex);
3946 }
3947
3948 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3949 {
3950 struct drm_device *dev = crtc->dev;
3951 struct drm_i915_private *dev_priv = dev->dev_private;
3952 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3953 int pipe = intel_crtc->pipe;
3954 int plane = intel_crtc->plane;
3955
3956 intel_crtc_wait_for_pending_flips(crtc);
3957
3958 if (dev_priv->fbc.plane == plane)
3959 intel_disable_fbc(dev);
3960
3961 hsw_disable_ips(intel_crtc);
3962
3963 intel_crtc_dpms_overlay(intel_crtc, false);
3964 intel_crtc_update_cursor(crtc, false);
3965 intel_disable_planes(crtc);
3966 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3967
3968 drm_vblank_off(dev, pipe);
3969 }
3970
3971 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3972 {
3973 struct drm_device *dev = crtc->dev;
3974 struct drm_i915_private *dev_priv = dev->dev_private;
3975 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3976 struct intel_encoder *encoder;
3977 int pipe = intel_crtc->pipe;
3978 enum plane plane = intel_crtc->plane;
3979
3980 WARN_ON(!crtc->enabled);
3981
3982 if (intel_crtc->active)
3983 return;
3984
3985 if (intel_crtc->config.has_pch_encoder)
3986 intel_prepare_shared_dpll(intel_crtc);
3987
3988 if (intel_crtc->config.has_dp_encoder)
3989 intel_dp_set_m_n(intel_crtc);
3990
3991 intel_set_pipe_timings(intel_crtc);
3992
3993 if (intel_crtc->config.has_pch_encoder) {
3994 intel_cpu_transcoder_set_m_n(intel_crtc,
3995 &intel_crtc->config.fdi_m_n);
3996 }
3997
3998 ironlake_set_pipeconf(crtc);
3999
4000 /* Set up the display plane register */
4001 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
4002 POSTING_READ(DSPCNTR(plane));
4003
4004 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4005 crtc->x, crtc->y);
4006
4007 intel_crtc->active = true;
4008
4009 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4010 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4011
4012 for_each_encoder_on_crtc(dev, crtc, encoder)
4013 if (encoder->pre_enable)
4014 encoder->pre_enable(encoder);
4015
4016 if (intel_crtc->config.has_pch_encoder) {
4017 /* Note: FDI PLL enabling _must_ be done before we enable the
4018 * cpu pipes, hence this is separate from all the other fdi/pch
4019 * enabling. */
4020 ironlake_fdi_pll_enable(intel_crtc);
4021 } else {
4022 assert_fdi_tx_disabled(dev_priv, pipe);
4023 assert_fdi_rx_disabled(dev_priv, pipe);
4024 }
4025
4026 ironlake_pfit_enable(intel_crtc);
4027
4028 /*
4029 * On ILK+ LUT must be loaded before the pipe is running but with
4030 * clocks enabled
4031 */
4032 intel_crtc_load_lut(crtc);
4033
4034 intel_update_watermarks(crtc);
4035 intel_enable_pipe(intel_crtc);
4036
4037 if (intel_crtc->config.has_pch_encoder)
4038 ironlake_pch_enable(crtc);
4039
4040 for_each_encoder_on_crtc(dev, crtc, encoder)
4041 encoder->enable(encoder);
4042
4043 if (HAS_PCH_CPT(dev))
4044 cpt_verify_modeset(dev, intel_crtc->pipe);
4045
4046 intel_crtc_enable_planes(crtc);
4047 }
4048
4049 /* IPS only exists on ULT machines and is tied to pipe A. */
4050 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4051 {
4052 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4053 }
4054
4055 /*
4056 * This implements the workaround described in the "notes" section of the mode
4057 * set sequence documentation. When going from no pipes or single pipe to
4058 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4059 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4060 */
4061 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4062 {
4063 struct drm_device *dev = crtc->base.dev;
4064 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4065
4066 /* We want to get the other_active_crtc only if there's only 1 other
4067 * active crtc. */
4068 for_each_intel_crtc(dev, crtc_it) {
4069 if (!crtc_it->active || crtc_it == crtc)
4070 continue;
4071
4072 if (other_active_crtc)
4073 return;
4074
4075 other_active_crtc = crtc_it;
4076 }
4077 if (!other_active_crtc)
4078 return;
4079
4080 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4081 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4082 }
4083
4084 static void haswell_crtc_enable(struct drm_crtc *crtc)
4085 {
4086 struct drm_device *dev = crtc->dev;
4087 struct drm_i915_private *dev_priv = dev->dev_private;
4088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4089 struct intel_encoder *encoder;
4090 int pipe = intel_crtc->pipe;
4091 enum plane plane = intel_crtc->plane;
4092
4093 WARN_ON(!crtc->enabled);
4094
4095 if (intel_crtc->active)
4096 return;
4097
4098 if (intel_crtc->config.has_dp_encoder)
4099 intel_dp_set_m_n(intel_crtc);
4100
4101 intel_set_pipe_timings(intel_crtc);
4102
4103 if (intel_crtc->config.has_pch_encoder) {
4104 intel_cpu_transcoder_set_m_n(intel_crtc,
4105 &intel_crtc->config.fdi_m_n);
4106 }
4107
4108 haswell_set_pipeconf(crtc);
4109
4110 intel_set_pipe_csc(crtc);
4111
4112 /* Set up the display plane register */
4113 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
4114 POSTING_READ(DSPCNTR(plane));
4115
4116 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4117 crtc->x, crtc->y);
4118
4119 intel_crtc->active = true;
4120
4121 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4122 if (intel_crtc->config.has_pch_encoder)
4123 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4124
4125 if (intel_crtc->config.has_pch_encoder)
4126 dev_priv->display.fdi_link_train(crtc);
4127
4128 for_each_encoder_on_crtc(dev, crtc, encoder)
4129 if (encoder->pre_enable)
4130 encoder->pre_enable(encoder);
4131
4132 intel_ddi_enable_pipe_clock(intel_crtc);
4133
4134 ironlake_pfit_enable(intel_crtc);
4135
4136 /*
4137 * On ILK+ LUT must be loaded before the pipe is running but with
4138 * clocks enabled
4139 */
4140 intel_crtc_load_lut(crtc);
4141
4142 intel_ddi_set_pipe_settings(crtc);
4143 intel_ddi_enable_transcoder_func(crtc);
4144
4145 intel_update_watermarks(crtc);
4146 intel_enable_pipe(intel_crtc);
4147
4148 if (intel_crtc->config.has_pch_encoder)
4149 lpt_pch_enable(crtc);
4150
4151 for_each_encoder_on_crtc(dev, crtc, encoder) {
4152 encoder->enable(encoder);
4153 intel_opregion_notify_encoder(encoder, true);
4154 }
4155
4156 /* If we change the relative order between pipe/planes enabling, we need
4157 * to change the workaround. */
4158 haswell_mode_set_planes_workaround(intel_crtc);
4159 intel_crtc_enable_planes(crtc);
4160 }
4161
4162 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4163 {
4164 struct drm_device *dev = crtc->base.dev;
4165 struct drm_i915_private *dev_priv = dev->dev_private;
4166 int pipe = crtc->pipe;
4167
4168 /* To avoid upsetting the power well on haswell only disable the pfit if
4169 * it's in use. The hw state code will make sure we get this right. */
4170 if (crtc->config.pch_pfit.enabled) {
4171 I915_WRITE(PF_CTL(pipe), 0);
4172 I915_WRITE(PF_WIN_POS(pipe), 0);
4173 I915_WRITE(PF_WIN_SZ(pipe), 0);
4174 }
4175 }
4176
4177 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4178 {
4179 struct drm_device *dev = crtc->dev;
4180 struct drm_i915_private *dev_priv = dev->dev_private;
4181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4182 struct intel_encoder *encoder;
4183 int pipe = intel_crtc->pipe;
4184 u32 reg, temp;
4185
4186 if (!intel_crtc->active)
4187 return;
4188
4189 intel_crtc_disable_planes(crtc);
4190
4191 for_each_encoder_on_crtc(dev, crtc, encoder)
4192 encoder->disable(encoder);
4193
4194 if (intel_crtc->config.has_pch_encoder)
4195 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4196
4197 intel_disable_pipe(dev_priv, pipe);
4198
4199 ironlake_pfit_disable(intel_crtc);
4200
4201 for_each_encoder_on_crtc(dev, crtc, encoder)
4202 if (encoder->post_disable)
4203 encoder->post_disable(encoder);
4204
4205 if (intel_crtc->config.has_pch_encoder) {
4206 ironlake_fdi_disable(crtc);
4207
4208 ironlake_disable_pch_transcoder(dev_priv, pipe);
4209 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4210
4211 if (HAS_PCH_CPT(dev)) {
4212 /* disable TRANS_DP_CTL */
4213 reg = TRANS_DP_CTL(pipe);
4214 temp = I915_READ(reg);
4215 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4216 TRANS_DP_PORT_SEL_MASK);
4217 temp |= TRANS_DP_PORT_SEL_NONE;
4218 I915_WRITE(reg, temp);
4219
4220 /* disable DPLL_SEL */
4221 temp = I915_READ(PCH_DPLL_SEL);
4222 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4223 I915_WRITE(PCH_DPLL_SEL, temp);
4224 }
4225
4226 /* disable PCH DPLL */
4227 intel_disable_shared_dpll(intel_crtc);
4228
4229 ironlake_fdi_pll_disable(intel_crtc);
4230 }
4231
4232 intel_crtc->active = false;
4233 intel_update_watermarks(crtc);
4234
4235 mutex_lock(&dev->struct_mutex);
4236 intel_update_fbc(dev);
4237 mutex_unlock(&dev->struct_mutex);
4238 }
4239
4240 static void haswell_crtc_disable(struct drm_crtc *crtc)
4241 {
4242 struct drm_device *dev = crtc->dev;
4243 struct drm_i915_private *dev_priv = dev->dev_private;
4244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4245 struct intel_encoder *encoder;
4246 int pipe = intel_crtc->pipe;
4247 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4248
4249 if (!intel_crtc->active)
4250 return;
4251
4252 intel_crtc_disable_planes(crtc);
4253
4254 for_each_encoder_on_crtc(dev, crtc, encoder) {
4255 intel_opregion_notify_encoder(encoder, false);
4256 encoder->disable(encoder);
4257 }
4258
4259 if (intel_crtc->config.has_pch_encoder)
4260 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4261 intel_disable_pipe(dev_priv, pipe);
4262
4263 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4264
4265 ironlake_pfit_disable(intel_crtc);
4266
4267 intel_ddi_disable_pipe_clock(intel_crtc);
4268
4269 for_each_encoder_on_crtc(dev, crtc, encoder)
4270 if (encoder->post_disable)
4271 encoder->post_disable(encoder);
4272
4273 if (intel_crtc->config.has_pch_encoder) {
4274 lpt_disable_pch_transcoder(dev_priv);
4275 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4276 intel_ddi_fdi_disable(crtc);
4277 }
4278
4279 intel_crtc->active = false;
4280 intel_update_watermarks(crtc);
4281
4282 mutex_lock(&dev->struct_mutex);
4283 intel_update_fbc(dev);
4284 mutex_unlock(&dev->struct_mutex);
4285 }
4286
4287 static void ironlake_crtc_off(struct drm_crtc *crtc)
4288 {
4289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4290 intel_put_shared_dpll(intel_crtc);
4291 }
4292
4293 static void haswell_crtc_off(struct drm_crtc *crtc)
4294 {
4295 intel_ddi_put_crtc_pll(crtc);
4296 }
4297
4298 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4299 {
4300 struct drm_device *dev = crtc->base.dev;
4301 struct drm_i915_private *dev_priv = dev->dev_private;
4302 struct intel_crtc_config *pipe_config = &crtc->config;
4303
4304 if (!crtc->config.gmch_pfit.control)
4305 return;
4306
4307 /*
4308 * The panel fitter should only be adjusted whilst the pipe is disabled,
4309 * according to register description and PRM.
4310 */
4311 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4312 assert_pipe_disabled(dev_priv, crtc->pipe);
4313
4314 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4315 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4316
4317 /* Border color in case we don't scale up to the full screen. Black by
4318 * default, change to something else for debugging. */
4319 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4320 }
4321
4322 #define for_each_power_domain(domain, mask) \
4323 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4324 if ((1 << (domain)) & (mask))
4325
4326 enum intel_display_power_domain
4327 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4328 {
4329 struct drm_device *dev = intel_encoder->base.dev;
4330 struct intel_digital_port *intel_dig_port;
4331
4332 switch (intel_encoder->type) {
4333 case INTEL_OUTPUT_UNKNOWN:
4334 /* Only DDI platforms should ever use this output type */
4335 WARN_ON_ONCE(!HAS_DDI(dev));
4336 case INTEL_OUTPUT_DISPLAYPORT:
4337 case INTEL_OUTPUT_HDMI:
4338 case INTEL_OUTPUT_EDP:
4339 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4340 switch (intel_dig_port->port) {
4341 case PORT_A:
4342 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4343 case PORT_B:
4344 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4345 case PORT_C:
4346 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4347 case PORT_D:
4348 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4349 default:
4350 WARN_ON_ONCE(1);
4351 return POWER_DOMAIN_PORT_OTHER;
4352 }
4353 case INTEL_OUTPUT_ANALOG:
4354 return POWER_DOMAIN_PORT_CRT;
4355 case INTEL_OUTPUT_DSI:
4356 return POWER_DOMAIN_PORT_DSI;
4357 default:
4358 return POWER_DOMAIN_PORT_OTHER;
4359 }
4360 }
4361
4362 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4363 {
4364 struct drm_device *dev = crtc->dev;
4365 struct intel_encoder *intel_encoder;
4366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4367 enum pipe pipe = intel_crtc->pipe;
4368 bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4369 unsigned long mask;
4370 enum transcoder transcoder;
4371
4372 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4373
4374 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4375 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4376 if (pfit_enabled)
4377 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4378
4379 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4380 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4381
4382 return mask;
4383 }
4384
4385 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4386 bool enable)
4387 {
4388 if (dev_priv->power_domains.init_power_on == enable)
4389 return;
4390
4391 if (enable)
4392 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4393 else
4394 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4395
4396 dev_priv->power_domains.init_power_on = enable;
4397 }
4398
4399 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4400 {
4401 struct drm_i915_private *dev_priv = dev->dev_private;
4402 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4403 struct intel_crtc *crtc;
4404
4405 /*
4406 * First get all needed power domains, then put all unneeded, to avoid
4407 * any unnecessary toggling of the power wells.
4408 */
4409 for_each_intel_crtc(dev, crtc) {
4410 enum intel_display_power_domain domain;
4411
4412 if (!crtc->base.enabled)
4413 continue;
4414
4415 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4416
4417 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4418 intel_display_power_get(dev_priv, domain);
4419 }
4420
4421 for_each_intel_crtc(dev, crtc) {
4422 enum intel_display_power_domain domain;
4423
4424 for_each_power_domain(domain, crtc->enabled_power_domains)
4425 intel_display_power_put(dev_priv, domain);
4426
4427 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4428 }
4429
4430 intel_display_set_init_power(dev_priv, false);
4431 }
4432
4433 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4434 {
4435 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4436
4437 /* Obtain SKU information */
4438 mutex_lock(&dev_priv->dpio_lock);
4439 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4440 CCK_FUSE_HPLL_FREQ_MASK;
4441 mutex_unlock(&dev_priv->dpio_lock);
4442
4443 return vco_freq[hpll_freq];
4444 }
4445
4446 /* Adjust CDclk dividers to allow high res or save power if possible */
4447 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4448 {
4449 struct drm_i915_private *dev_priv = dev->dev_private;
4450 u32 val, cmd;
4451
4452 WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4453 dev_priv->vlv_cdclk_freq = cdclk;
4454
4455 if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4456 cmd = 2;
4457 else if (cdclk == 266)
4458 cmd = 1;
4459 else
4460 cmd = 0;
4461
4462 mutex_lock(&dev_priv->rps.hw_lock);
4463 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4464 val &= ~DSPFREQGUAR_MASK;
4465 val |= (cmd << DSPFREQGUAR_SHIFT);
4466 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4467 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4468 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4469 50)) {
4470 DRM_ERROR("timed out waiting for CDclk change\n");
4471 }
4472 mutex_unlock(&dev_priv->rps.hw_lock);
4473
4474 if (cdclk == 400) {
4475 u32 divider, vco;
4476
4477 vco = valleyview_get_vco(dev_priv);
4478 divider = ((vco << 1) / cdclk) - 1;
4479
4480 mutex_lock(&dev_priv->dpio_lock);
4481 /* adjust cdclk divider */
4482 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4483 val &= ~0xf;
4484 val |= divider;
4485 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4486 mutex_unlock(&dev_priv->dpio_lock);
4487 }
4488
4489 mutex_lock(&dev_priv->dpio_lock);
4490 /* adjust self-refresh exit latency value */
4491 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4492 val &= ~0x7f;
4493
4494 /*
4495 * For high bandwidth configs, we set a higher latency in the bunit
4496 * so that the core display fetch happens in time to avoid underruns.
4497 */
4498 if (cdclk == 400)
4499 val |= 4500 / 250; /* 4.5 usec */
4500 else
4501 val |= 3000 / 250; /* 3.0 usec */
4502 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4503 mutex_unlock(&dev_priv->dpio_lock);
4504
4505 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4506 intel_i2c_reset(dev);
4507 }
4508
4509 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4510 {
4511 int cur_cdclk, vco;
4512 int divider;
4513
4514 vco = valleyview_get_vco(dev_priv);
4515
4516 mutex_lock(&dev_priv->dpio_lock);
4517 divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4518 mutex_unlock(&dev_priv->dpio_lock);
4519
4520 divider &= 0xf;
4521
4522 cur_cdclk = (vco << 1) / (divider + 1);
4523
4524 return cur_cdclk;
4525 }
4526
4527 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4528 int max_pixclk)
4529 {
4530 /*
4531 * Really only a few cases to deal with, as only 4 CDclks are supported:
4532 * 200MHz
4533 * 267MHz
4534 * 320MHz
4535 * 400MHz
4536 * So we check to see whether we're above 90% of the lower bin and
4537 * adjust if needed.
4538 */
4539 if (max_pixclk > 288000) {
4540 return 400;
4541 } else if (max_pixclk > 240000) {
4542 return 320;
4543 } else
4544 return 266;
4545 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4546 }
4547
4548 /* compute the max pixel clock for new configuration */
4549 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4550 {
4551 struct drm_device *dev = dev_priv->dev;
4552 struct intel_crtc *intel_crtc;
4553 int max_pixclk = 0;
4554
4555 for_each_intel_crtc(dev, intel_crtc) {
4556 if (intel_crtc->new_enabled)
4557 max_pixclk = max(max_pixclk,
4558 intel_crtc->new_config->adjusted_mode.crtc_clock);
4559 }
4560
4561 return max_pixclk;
4562 }
4563
4564 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4565 unsigned *prepare_pipes)
4566 {
4567 struct drm_i915_private *dev_priv = dev->dev_private;
4568 struct intel_crtc *intel_crtc;
4569 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4570
4571 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4572 dev_priv->vlv_cdclk_freq)
4573 return;
4574
4575 /* disable/enable all currently active pipes while we change cdclk */
4576 for_each_intel_crtc(dev, intel_crtc)
4577 if (intel_crtc->base.enabled)
4578 *prepare_pipes |= (1 << intel_crtc->pipe);
4579 }
4580
4581 static void valleyview_modeset_global_resources(struct drm_device *dev)
4582 {
4583 struct drm_i915_private *dev_priv = dev->dev_private;
4584 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4585 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4586
4587 if (req_cdclk != dev_priv->vlv_cdclk_freq)
4588 valleyview_set_cdclk(dev, req_cdclk);
4589 modeset_update_crtc_power_domains(dev);
4590 }
4591
4592 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4593 {
4594 struct drm_device *dev = crtc->dev;
4595 struct drm_i915_private *dev_priv = dev->dev_private;
4596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4597 struct intel_encoder *encoder;
4598 int pipe = intel_crtc->pipe;
4599 int plane = intel_crtc->plane;
4600 bool is_dsi;
4601 u32 dspcntr;
4602
4603 WARN_ON(!crtc->enabled);
4604
4605 if (intel_crtc->active)
4606 return;
4607
4608 vlv_prepare_pll(intel_crtc);
4609
4610 /* Set up the display plane register */
4611 dspcntr = DISPPLANE_GAMMA_ENABLE;
4612
4613 if (intel_crtc->config.has_dp_encoder)
4614 intel_dp_set_m_n(intel_crtc);
4615
4616 intel_set_pipe_timings(intel_crtc);
4617
4618 /* pipesrc and dspsize control the size that is scaled from,
4619 * which should always be the user's requested size.
4620 */
4621 I915_WRITE(DSPSIZE(plane),
4622 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4623 (intel_crtc->config.pipe_src_w - 1));
4624 I915_WRITE(DSPPOS(plane), 0);
4625
4626 i9xx_set_pipeconf(intel_crtc);
4627
4628 I915_WRITE(DSPCNTR(plane), dspcntr);
4629 POSTING_READ(DSPCNTR(plane));
4630
4631 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4632 crtc->x, crtc->y);
4633
4634 intel_crtc->active = true;
4635
4636 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4637
4638 for_each_encoder_on_crtc(dev, crtc, encoder)
4639 if (encoder->pre_pll_enable)
4640 encoder->pre_pll_enable(encoder);
4641
4642 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4643
4644 if (!is_dsi) {
4645 if (IS_CHERRYVIEW(dev))
4646 chv_enable_pll(intel_crtc);
4647 else
4648 vlv_enable_pll(intel_crtc);
4649 }
4650
4651 for_each_encoder_on_crtc(dev, crtc, encoder)
4652 if (encoder->pre_enable)
4653 encoder->pre_enable(encoder);
4654
4655 i9xx_pfit_enable(intel_crtc);
4656
4657 intel_crtc_load_lut(crtc);
4658
4659 intel_update_watermarks(crtc);
4660 intel_enable_pipe(intel_crtc);
4661
4662 for_each_encoder_on_crtc(dev, crtc, encoder)
4663 encoder->enable(encoder);
4664
4665 intel_crtc_enable_planes(crtc);
4666
4667 /* Underruns don't raise interrupts, so check manually. */
4668 i9xx_check_fifo_underruns(dev);
4669 }
4670
4671 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4672 {
4673 struct drm_device *dev = crtc->base.dev;
4674 struct drm_i915_private *dev_priv = dev->dev_private;
4675
4676 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4677 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4678 }
4679
4680 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4681 {
4682 struct drm_device *dev = crtc->dev;
4683 struct drm_i915_private *dev_priv = dev->dev_private;
4684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4685 struct intel_encoder *encoder;
4686 int pipe = intel_crtc->pipe;
4687 int plane = intel_crtc->plane;
4688 u32 dspcntr;
4689
4690 WARN_ON(!crtc->enabled);
4691
4692 if (intel_crtc->active)
4693 return;
4694
4695 i9xx_set_pll_dividers(intel_crtc);
4696
4697 /* Set up the display plane register */
4698 dspcntr = DISPPLANE_GAMMA_ENABLE;
4699
4700 if (pipe == 0)
4701 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4702 else
4703 dspcntr |= DISPPLANE_SEL_PIPE_B;
4704
4705 if (intel_crtc->config.has_dp_encoder)
4706 intel_dp_set_m_n(intel_crtc);
4707
4708 intel_set_pipe_timings(intel_crtc);
4709
4710 /* pipesrc and dspsize control the size that is scaled from,
4711 * which should always be the user's requested size.
4712 */
4713 I915_WRITE(DSPSIZE(plane),
4714 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4715 (intel_crtc->config.pipe_src_w - 1));
4716 I915_WRITE(DSPPOS(plane), 0);
4717
4718 i9xx_set_pipeconf(intel_crtc);
4719
4720 I915_WRITE(DSPCNTR(plane), dspcntr);
4721 POSTING_READ(DSPCNTR(plane));
4722
4723 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4724 crtc->x, crtc->y);
4725
4726 intel_crtc->active = true;
4727
4728 if (!IS_GEN2(dev))
4729 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4730
4731 for_each_encoder_on_crtc(dev, crtc, encoder)
4732 if (encoder->pre_enable)
4733 encoder->pre_enable(encoder);
4734
4735 i9xx_enable_pll(intel_crtc);
4736
4737 i9xx_pfit_enable(intel_crtc);
4738
4739 intel_crtc_load_lut(crtc);
4740
4741 intel_update_watermarks(crtc);
4742 intel_enable_pipe(intel_crtc);
4743
4744 for_each_encoder_on_crtc(dev, crtc, encoder)
4745 encoder->enable(encoder);
4746
4747 intel_crtc_enable_planes(crtc);
4748
4749 /*
4750 * Gen2 reports pipe underruns whenever all planes are disabled.
4751 * So don't enable underrun reporting before at least some planes
4752 * are enabled.
4753 * FIXME: Need to fix the logic to work when we turn off all planes
4754 * but leave the pipe running.
4755 */
4756 if (IS_GEN2(dev))
4757 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4758
4759 /* Underruns don't raise interrupts, so check manually. */
4760 i9xx_check_fifo_underruns(dev);
4761 }
4762
4763 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4764 {
4765 struct drm_device *dev = crtc->base.dev;
4766 struct drm_i915_private *dev_priv = dev->dev_private;
4767
4768 if (!crtc->config.gmch_pfit.control)
4769 return;
4770
4771 assert_pipe_disabled(dev_priv, crtc->pipe);
4772
4773 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4774 I915_READ(PFIT_CONTROL));
4775 I915_WRITE(PFIT_CONTROL, 0);
4776 }
4777
4778 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4779 {
4780 struct drm_device *dev = crtc->dev;
4781 struct drm_i915_private *dev_priv = dev->dev_private;
4782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4783 struct intel_encoder *encoder;
4784 int pipe = intel_crtc->pipe;
4785
4786 if (!intel_crtc->active)
4787 return;
4788
4789 /*
4790 * Gen2 reports pipe underruns whenever all planes are disabled.
4791 * So diasble underrun reporting before all the planes get disabled.
4792 * FIXME: Need to fix the logic to work when we turn off all planes
4793 * but leave the pipe running.
4794 */
4795 if (IS_GEN2(dev))
4796 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4797
4798 intel_crtc_disable_planes(crtc);
4799
4800 for_each_encoder_on_crtc(dev, crtc, encoder)
4801 encoder->disable(encoder);
4802
4803 /*
4804 * On gen2 planes are double buffered but the pipe isn't, so we must
4805 * wait for planes to fully turn off before disabling the pipe.
4806 */
4807 if (IS_GEN2(dev))
4808 intel_wait_for_vblank(dev, pipe);
4809
4810 intel_disable_pipe(dev_priv, pipe);
4811
4812 i9xx_pfit_disable(intel_crtc);
4813
4814 for_each_encoder_on_crtc(dev, crtc, encoder)
4815 if (encoder->post_disable)
4816 encoder->post_disable(encoder);
4817
4818 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4819 if (IS_CHERRYVIEW(dev))
4820 chv_disable_pll(dev_priv, pipe);
4821 else if (IS_VALLEYVIEW(dev))
4822 vlv_disable_pll(dev_priv, pipe);
4823 else
4824 i9xx_disable_pll(dev_priv, pipe);
4825 }
4826
4827 if (!IS_GEN2(dev))
4828 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4829
4830 intel_crtc->active = false;
4831 intel_update_watermarks(crtc);
4832
4833 mutex_lock(&dev->struct_mutex);
4834 intel_update_fbc(dev);
4835 mutex_unlock(&dev->struct_mutex);
4836 }
4837
4838 static void i9xx_crtc_off(struct drm_crtc *crtc)
4839 {
4840 }
4841
4842 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4843 bool enabled)
4844 {
4845 struct drm_device *dev = crtc->dev;
4846 struct drm_i915_master_private *master_priv;
4847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4848 int pipe = intel_crtc->pipe;
4849
4850 if (!dev->primary->master)
4851 return;
4852
4853 master_priv = dev->primary->master->driver_priv;
4854 if (!master_priv->sarea_priv)
4855 return;
4856
4857 switch (pipe) {
4858 case 0:
4859 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4860 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4861 break;
4862 case 1:
4863 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4864 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4865 break;
4866 default:
4867 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4868 break;
4869 }
4870 }
4871
4872 /**
4873 * Sets the power management mode of the pipe and plane.
4874 */
4875 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4876 {
4877 struct drm_device *dev = crtc->dev;
4878 struct drm_i915_private *dev_priv = dev->dev_private;
4879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4880 struct intel_encoder *intel_encoder;
4881 enum intel_display_power_domain domain;
4882 unsigned long domains;
4883 bool enable = false;
4884
4885 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4886 enable |= intel_encoder->connectors_active;
4887
4888 if (enable) {
4889 if (!intel_crtc->active) {
4890 /*
4891 * FIXME: DDI plls and relevant code isn't converted
4892 * yet, so do runtime PM for DPMS only for all other
4893 * platforms for now.
4894 */
4895 if (!HAS_DDI(dev)) {
4896 domains = get_crtc_power_domains(crtc);
4897 for_each_power_domain(domain, domains)
4898 intel_display_power_get(dev_priv, domain);
4899 intel_crtc->enabled_power_domains = domains;
4900 }
4901
4902 dev_priv->display.crtc_enable(crtc);
4903 }
4904 } else {
4905 if (intel_crtc->active) {
4906 dev_priv->display.crtc_disable(crtc);
4907
4908 if (!HAS_DDI(dev)) {
4909 domains = intel_crtc->enabled_power_domains;
4910 for_each_power_domain(domain, domains)
4911 intel_display_power_put(dev_priv, domain);
4912 intel_crtc->enabled_power_domains = 0;
4913 }
4914 }
4915 }
4916
4917 intel_crtc_update_sarea(crtc, enable);
4918 }
4919
4920 static void intel_crtc_disable(struct drm_crtc *crtc)
4921 {
4922 struct drm_device *dev = crtc->dev;
4923 struct drm_connector *connector;
4924 struct drm_i915_private *dev_priv = dev->dev_private;
4925
4926 /* crtc should still be enabled when we disable it. */
4927 WARN_ON(!crtc->enabled);
4928
4929 dev_priv->display.crtc_disable(crtc);
4930 intel_crtc_update_sarea(crtc, false);
4931 dev_priv->display.off(crtc);
4932
4933 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4934 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4935 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4936
4937 if (crtc->primary->fb) {
4938 mutex_lock(&dev->struct_mutex);
4939 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
4940 mutex_unlock(&dev->struct_mutex);
4941 crtc->primary->fb = NULL;
4942 }
4943
4944 /* Update computed state. */
4945 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4946 if (!connector->encoder || !connector->encoder->crtc)
4947 continue;
4948
4949 if (connector->encoder->crtc != crtc)
4950 continue;
4951
4952 connector->dpms = DRM_MODE_DPMS_OFF;
4953 to_intel_encoder(connector->encoder)->connectors_active = false;
4954 }
4955 }
4956
4957 void intel_encoder_destroy(struct drm_encoder *encoder)
4958 {
4959 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4960
4961 drm_encoder_cleanup(encoder);
4962 kfree(intel_encoder);
4963 }
4964
4965 /* Simple dpms helper for encoders with just one connector, no cloning and only
4966 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4967 * state of the entire output pipe. */
4968 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4969 {
4970 if (mode == DRM_MODE_DPMS_ON) {
4971 encoder->connectors_active = true;
4972
4973 intel_crtc_update_dpms(encoder->base.crtc);
4974 } else {
4975 encoder->connectors_active = false;
4976
4977 intel_crtc_update_dpms(encoder->base.crtc);
4978 }
4979 }
4980
4981 /* Cross check the actual hw state with our own modeset state tracking (and it's
4982 * internal consistency). */
4983 static void intel_connector_check_state(struct intel_connector *connector)
4984 {
4985 if (connector->get_hw_state(connector)) {
4986 struct intel_encoder *encoder = connector->encoder;
4987 struct drm_crtc *crtc;
4988 bool encoder_enabled;
4989 enum pipe pipe;
4990
4991 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4992 connector->base.base.id,
4993 connector->base.name);
4994
4995 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4996 "wrong connector dpms state\n");
4997 WARN(connector->base.encoder != &encoder->base,
4998 "active connector not linked to encoder\n");
4999 WARN(!encoder->connectors_active,
5000 "encoder->connectors_active not set\n");
5001
5002 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5003 WARN(!encoder_enabled, "encoder not enabled\n");
5004 if (WARN_ON(!encoder->base.crtc))
5005 return;
5006
5007 crtc = encoder->base.crtc;
5008
5009 WARN(!crtc->enabled, "crtc not enabled\n");
5010 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5011 WARN(pipe != to_intel_crtc(crtc)->pipe,
5012 "encoder active on the wrong pipe\n");
5013 }
5014 }
5015
5016 /* Even simpler default implementation, if there's really no special case to
5017 * consider. */
5018 void intel_connector_dpms(struct drm_connector *connector, int mode)
5019 {
5020 /* All the simple cases only support two dpms states. */
5021 if (mode != DRM_MODE_DPMS_ON)
5022 mode = DRM_MODE_DPMS_OFF;
5023
5024 if (mode == connector->dpms)
5025 return;
5026
5027 connector->dpms = mode;
5028
5029 /* Only need to change hw state when actually enabled */
5030 if (connector->encoder)
5031 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5032
5033 intel_modeset_check_state(connector->dev);
5034 }
5035
5036 /* Simple connector->get_hw_state implementation for encoders that support only
5037 * one connector and no cloning and hence the encoder state determines the state
5038 * of the connector. */
5039 bool intel_connector_get_hw_state(struct intel_connector *connector)
5040 {
5041 enum pipe pipe = 0;
5042 struct intel_encoder *encoder = connector->encoder;
5043
5044 return encoder->get_hw_state(encoder, &pipe);
5045 }
5046
5047 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5048 struct intel_crtc_config *pipe_config)
5049 {
5050 struct drm_i915_private *dev_priv = dev->dev_private;
5051 struct intel_crtc *pipe_B_crtc =
5052 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5053
5054 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5055 pipe_name(pipe), pipe_config->fdi_lanes);
5056 if (pipe_config->fdi_lanes > 4) {
5057 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5058 pipe_name(pipe), pipe_config->fdi_lanes);
5059 return false;
5060 }
5061
5062 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5063 if (pipe_config->fdi_lanes > 2) {
5064 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5065 pipe_config->fdi_lanes);
5066 return false;
5067 } else {
5068 return true;
5069 }
5070 }
5071
5072 if (INTEL_INFO(dev)->num_pipes == 2)
5073 return true;
5074
5075 /* Ivybridge 3 pipe is really complicated */
5076 switch (pipe) {
5077 case PIPE_A:
5078 return true;
5079 case PIPE_B:
5080 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5081 pipe_config->fdi_lanes > 2) {
5082 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5083 pipe_name(pipe), pipe_config->fdi_lanes);
5084 return false;
5085 }
5086 return true;
5087 case PIPE_C:
5088 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5089 pipe_B_crtc->config.fdi_lanes <= 2) {
5090 if (pipe_config->fdi_lanes > 2) {
5091 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5092 pipe_name(pipe), pipe_config->fdi_lanes);
5093 return false;
5094 }
5095 } else {
5096 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5097 return false;
5098 }
5099 return true;
5100 default:
5101 BUG();
5102 }
5103 }
5104
5105 #define RETRY 1
5106 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5107 struct intel_crtc_config *pipe_config)
5108 {
5109 struct drm_device *dev = intel_crtc->base.dev;
5110 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5111 int lane, link_bw, fdi_dotclock;
5112 bool setup_ok, needs_recompute = false;
5113
5114 retry:
5115 /* FDI is a binary signal running at ~2.7GHz, encoding
5116 * each output octet as 10 bits. The actual frequency
5117 * is stored as a divider into a 100MHz clock, and the
5118 * mode pixel clock is stored in units of 1KHz.
5119 * Hence the bw of each lane in terms of the mode signal
5120 * is:
5121 */
5122 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5123
5124 fdi_dotclock = adjusted_mode->crtc_clock;
5125
5126 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5127 pipe_config->pipe_bpp);
5128
5129 pipe_config->fdi_lanes = lane;
5130
5131 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5132 link_bw, &pipe_config->fdi_m_n);
5133
5134 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5135 intel_crtc->pipe, pipe_config);
5136 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5137 pipe_config->pipe_bpp -= 2*3;
5138 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5139 pipe_config->pipe_bpp);
5140 needs_recompute = true;
5141 pipe_config->bw_constrained = true;
5142
5143 goto retry;
5144 }
5145
5146 if (needs_recompute)
5147 return RETRY;
5148
5149 return setup_ok ? 0 : -EINVAL;
5150 }
5151
5152 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5153 struct intel_crtc_config *pipe_config)
5154 {
5155 pipe_config->ips_enabled = i915.enable_ips &&
5156 hsw_crtc_supports_ips(crtc) &&
5157 pipe_config->pipe_bpp <= 24;
5158 }
5159
5160 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5161 struct intel_crtc_config *pipe_config)
5162 {
5163 struct drm_device *dev = crtc->base.dev;
5164 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5165
5166 /* FIXME should check pixel clock limits on all platforms */
5167 if (INTEL_INFO(dev)->gen < 4) {
5168 struct drm_i915_private *dev_priv = dev->dev_private;
5169 int clock_limit =
5170 dev_priv->display.get_display_clock_speed(dev);
5171
5172 /*
5173 * Enable pixel doubling when the dot clock
5174 * is > 90% of the (display) core speed.
5175 *
5176 * GDG double wide on either pipe,
5177 * otherwise pipe A only.
5178 */
5179 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5180 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5181 clock_limit *= 2;
5182 pipe_config->double_wide = true;
5183 }
5184
5185 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5186 return -EINVAL;
5187 }
5188
5189 /*
5190 * Pipe horizontal size must be even in:
5191 * - DVO ganged mode
5192 * - LVDS dual channel mode
5193 * - Double wide pipe
5194 */
5195 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5196 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5197 pipe_config->pipe_src_w &= ~1;
5198
5199 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5200 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5201 */
5202 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5203 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5204 return -EINVAL;
5205
5206 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5207 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5208 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5209 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5210 * for lvds. */
5211 pipe_config->pipe_bpp = 8*3;
5212 }
5213
5214 if (HAS_IPS(dev))
5215 hsw_compute_ips_config(crtc, pipe_config);
5216
5217 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
5218 * clock survives for now. */
5219 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5220 pipe_config->shared_dpll = crtc->config.shared_dpll;
5221
5222 if (pipe_config->has_pch_encoder)
5223 return ironlake_fdi_compute_config(crtc, pipe_config);
5224
5225 return 0;
5226 }
5227
5228 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5229 {
5230 return 400000; /* FIXME */
5231 }
5232
5233 static int i945_get_display_clock_speed(struct drm_device *dev)
5234 {
5235 return 400000;
5236 }
5237
5238 static int i915_get_display_clock_speed(struct drm_device *dev)
5239 {
5240 return 333000;
5241 }
5242
5243 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5244 {
5245 return 200000;
5246 }
5247
5248 static int pnv_get_display_clock_speed(struct drm_device *dev)
5249 {
5250 u16 gcfgc = 0;
5251
5252 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5253
5254 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5255 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5256 return 267000;
5257 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5258 return 333000;
5259 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5260 return 444000;
5261 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5262 return 200000;
5263 default:
5264 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5265 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5266 return 133000;
5267 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5268 return 167000;
5269 }
5270 }
5271
5272 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5273 {
5274 u16 gcfgc = 0;
5275
5276 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5277
5278 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5279 return 133000;
5280 else {
5281 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5282 case GC_DISPLAY_CLOCK_333_MHZ:
5283 return 333000;
5284 default:
5285 case GC_DISPLAY_CLOCK_190_200_MHZ:
5286 return 190000;
5287 }
5288 }
5289 }
5290
5291 static int i865_get_display_clock_speed(struct drm_device *dev)
5292 {
5293 return 266000;
5294 }
5295
5296 static int i855_get_display_clock_speed(struct drm_device *dev)
5297 {
5298 u16 hpllcc = 0;
5299 /* Assume that the hardware is in the high speed state. This
5300 * should be the default.
5301 */
5302 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5303 case GC_CLOCK_133_200:
5304 case GC_CLOCK_100_200:
5305 return 200000;
5306 case GC_CLOCK_166_250:
5307 return 250000;
5308 case GC_CLOCK_100_133:
5309 return 133000;
5310 }
5311
5312 /* Shouldn't happen */
5313 return 0;
5314 }
5315
5316 static int i830_get_display_clock_speed(struct drm_device *dev)
5317 {
5318 return 133000;
5319 }
5320
5321 static void
5322 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5323 {
5324 while (*num > DATA_LINK_M_N_MASK ||
5325 *den > DATA_LINK_M_N_MASK) {
5326 *num >>= 1;
5327 *den >>= 1;
5328 }
5329 }
5330
5331 static void compute_m_n(unsigned int m, unsigned int n,
5332 uint32_t *ret_m, uint32_t *ret_n)
5333 {
5334 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5335 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5336 intel_reduce_m_n_ratio(ret_m, ret_n);
5337 }
5338
5339 void
5340 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5341 int pixel_clock, int link_clock,
5342 struct intel_link_m_n *m_n)
5343 {
5344 m_n->tu = 64;
5345
5346 compute_m_n(bits_per_pixel * pixel_clock,
5347 link_clock * nlanes * 8,
5348 &m_n->gmch_m, &m_n->gmch_n);
5349
5350 compute_m_n(pixel_clock, link_clock,
5351 &m_n->link_m, &m_n->link_n);
5352 }
5353
5354 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5355 {
5356 if (i915.panel_use_ssc >= 0)
5357 return i915.panel_use_ssc != 0;
5358 return dev_priv->vbt.lvds_use_ssc
5359 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5360 }
5361
5362 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5363 {
5364 struct drm_device *dev = crtc->dev;
5365 struct drm_i915_private *dev_priv = dev->dev_private;
5366 int refclk;
5367
5368 if (IS_VALLEYVIEW(dev)) {
5369 refclk = 100000;
5370 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5371 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5372 refclk = dev_priv->vbt.lvds_ssc_freq;
5373 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5374 } else if (!IS_GEN2(dev)) {
5375 refclk = 96000;
5376 } else {
5377 refclk = 48000;
5378 }
5379
5380 return refclk;
5381 }
5382
5383 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5384 {
5385 return (1 << dpll->n) << 16 | dpll->m2;
5386 }
5387
5388 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5389 {
5390 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5391 }
5392
5393 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5394 intel_clock_t *reduced_clock)
5395 {
5396 struct drm_device *dev = crtc->base.dev;
5397 u32 fp, fp2 = 0;
5398
5399 if (IS_PINEVIEW(dev)) {
5400 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5401 if (reduced_clock)
5402 fp2 = pnv_dpll_compute_fp(reduced_clock);
5403 } else {
5404 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5405 if (reduced_clock)
5406 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5407 }
5408
5409 crtc->config.dpll_hw_state.fp0 = fp;
5410
5411 crtc->lowfreq_avail = false;
5412 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5413 reduced_clock && i915.powersave) {
5414 crtc->config.dpll_hw_state.fp1 = fp2;
5415 crtc->lowfreq_avail = true;
5416 } else {
5417 crtc->config.dpll_hw_state.fp1 = fp;
5418 }
5419 }
5420
5421 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5422 pipe)
5423 {
5424 u32 reg_val;
5425
5426 /*
5427 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5428 * and set it to a reasonable value instead.
5429 */
5430 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5431 reg_val &= 0xffffff00;
5432 reg_val |= 0x00000030;
5433 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5434
5435 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5436 reg_val &= 0x8cffffff;
5437 reg_val = 0x8c000000;
5438 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5439
5440 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5441 reg_val &= 0xffffff00;
5442 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5443
5444 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5445 reg_val &= 0x00ffffff;
5446 reg_val |= 0xb0000000;
5447 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5448 }
5449
5450 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5451 struct intel_link_m_n *m_n)
5452 {
5453 struct drm_device *dev = crtc->base.dev;
5454 struct drm_i915_private *dev_priv = dev->dev_private;
5455 int pipe = crtc->pipe;
5456
5457 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5458 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5459 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5460 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5461 }
5462
5463 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5464 struct intel_link_m_n *m_n)
5465 {
5466 struct drm_device *dev = crtc->base.dev;
5467 struct drm_i915_private *dev_priv = dev->dev_private;
5468 int pipe = crtc->pipe;
5469 enum transcoder transcoder = crtc->config.cpu_transcoder;
5470
5471 if (INTEL_INFO(dev)->gen >= 5) {
5472 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5473 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5474 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5475 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5476 } else {
5477 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5478 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5479 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5480 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5481 }
5482 }
5483
5484 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5485 {
5486 if (crtc->config.has_pch_encoder)
5487 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5488 else
5489 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5490 }
5491
5492 static void vlv_update_pll(struct intel_crtc *crtc)
5493 {
5494 u32 dpll, dpll_md;
5495
5496 /*
5497 * Enable DPIO clock input. We should never disable the reference
5498 * clock for pipe B, since VGA hotplug / manual detection depends
5499 * on it.
5500 */
5501 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5502 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5503 /* We should never disable this, set it here for state tracking */
5504 if (crtc->pipe == PIPE_B)
5505 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5506 dpll |= DPLL_VCO_ENABLE;
5507 crtc->config.dpll_hw_state.dpll = dpll;
5508
5509 dpll_md = (crtc->config.pixel_multiplier - 1)
5510 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5511 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5512 }
5513
5514 static void vlv_prepare_pll(struct intel_crtc *crtc)
5515 {
5516 struct drm_device *dev = crtc->base.dev;
5517 struct drm_i915_private *dev_priv = dev->dev_private;
5518 int pipe = crtc->pipe;
5519 u32 mdiv;
5520 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5521 u32 coreclk, reg_val;
5522
5523 mutex_lock(&dev_priv->dpio_lock);
5524
5525 bestn = crtc->config.dpll.n;
5526 bestm1 = crtc->config.dpll.m1;
5527 bestm2 = crtc->config.dpll.m2;
5528 bestp1 = crtc->config.dpll.p1;
5529 bestp2 = crtc->config.dpll.p2;
5530
5531 /* See eDP HDMI DPIO driver vbios notes doc */
5532
5533 /* PLL B needs special handling */
5534 if (pipe == PIPE_B)
5535 vlv_pllb_recal_opamp(dev_priv, pipe);
5536
5537 /* Set up Tx target for periodic Rcomp update */
5538 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5539
5540 /* Disable target IRef on PLL */
5541 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5542 reg_val &= 0x00ffffff;
5543 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5544
5545 /* Disable fast lock */
5546 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5547
5548 /* Set idtafcrecal before PLL is enabled */
5549 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5550 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5551 mdiv |= ((bestn << DPIO_N_SHIFT));
5552 mdiv |= (1 << DPIO_K_SHIFT);
5553
5554 /*
5555 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5556 * but we don't support that).
5557 * Note: don't use the DAC post divider as it seems unstable.
5558 */
5559 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5560 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5561
5562 mdiv |= DPIO_ENABLE_CALIBRATION;
5563 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5564
5565 /* Set HBR and RBR LPF coefficients */
5566 if (crtc->config.port_clock == 162000 ||
5567 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5568 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5569 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5570 0x009f0003);
5571 else
5572 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5573 0x00d0000f);
5574
5575 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5576 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5577 /* Use SSC source */
5578 if (pipe == PIPE_A)
5579 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5580 0x0df40000);
5581 else
5582 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5583 0x0df70000);
5584 } else { /* HDMI or VGA */
5585 /* Use bend source */
5586 if (pipe == PIPE_A)
5587 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5588 0x0df70000);
5589 else
5590 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5591 0x0df40000);
5592 }
5593
5594 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5595 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5596 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5597 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5598 coreclk |= 0x01000000;
5599 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5600
5601 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5602 mutex_unlock(&dev_priv->dpio_lock);
5603 }
5604
5605 static void chv_update_pll(struct intel_crtc *crtc)
5606 {
5607 struct drm_device *dev = crtc->base.dev;
5608 struct drm_i915_private *dev_priv = dev->dev_private;
5609 int pipe = crtc->pipe;
5610 int dpll_reg = DPLL(crtc->pipe);
5611 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5612 u32 loopfilter, intcoeff;
5613 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5614 int refclk;
5615
5616 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5617 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5618 DPLL_VCO_ENABLE;
5619 if (pipe != PIPE_A)
5620 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5621
5622 crtc->config.dpll_hw_state.dpll_md =
5623 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5624
5625 bestn = crtc->config.dpll.n;
5626 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5627 bestm1 = crtc->config.dpll.m1;
5628 bestm2 = crtc->config.dpll.m2 >> 22;
5629 bestp1 = crtc->config.dpll.p1;
5630 bestp2 = crtc->config.dpll.p2;
5631
5632 /*
5633 * Enable Refclk and SSC
5634 */
5635 I915_WRITE(dpll_reg,
5636 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5637
5638 mutex_lock(&dev_priv->dpio_lock);
5639
5640 /* p1 and p2 divider */
5641 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5642 5 << DPIO_CHV_S1_DIV_SHIFT |
5643 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5644 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5645 1 << DPIO_CHV_K_DIV_SHIFT);
5646
5647 /* Feedback post-divider - m2 */
5648 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5649
5650 /* Feedback refclk divider - n and m1 */
5651 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5652 DPIO_CHV_M1_DIV_BY_2 |
5653 1 << DPIO_CHV_N_DIV_SHIFT);
5654
5655 /* M2 fraction division */
5656 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5657
5658 /* M2 fraction division enable */
5659 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5660 DPIO_CHV_FRAC_DIV_EN |
5661 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5662
5663 /* Loop filter */
5664 refclk = i9xx_get_refclk(&crtc->base, 0);
5665 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5666 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5667 if (refclk == 100000)
5668 intcoeff = 11;
5669 else if (refclk == 38400)
5670 intcoeff = 10;
5671 else
5672 intcoeff = 9;
5673 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5674 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5675
5676 /* AFC Recal */
5677 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5678 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5679 DPIO_AFC_RECAL);
5680
5681 mutex_unlock(&dev_priv->dpio_lock);
5682 }
5683
5684 static void i9xx_update_pll(struct intel_crtc *crtc,
5685 intel_clock_t *reduced_clock,
5686 int num_connectors)
5687 {
5688 struct drm_device *dev = crtc->base.dev;
5689 struct drm_i915_private *dev_priv = dev->dev_private;
5690 u32 dpll;
5691 bool is_sdvo;
5692 struct dpll *clock = &crtc->config.dpll;
5693
5694 i9xx_update_pll_dividers(crtc, reduced_clock);
5695
5696 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5697 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5698
5699 dpll = DPLL_VGA_MODE_DIS;
5700
5701 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5702 dpll |= DPLLB_MODE_LVDS;
5703 else
5704 dpll |= DPLLB_MODE_DAC_SERIAL;
5705
5706 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5707 dpll |= (crtc->config.pixel_multiplier - 1)
5708 << SDVO_MULTIPLIER_SHIFT_HIRES;
5709 }
5710
5711 if (is_sdvo)
5712 dpll |= DPLL_SDVO_HIGH_SPEED;
5713
5714 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5715 dpll |= DPLL_SDVO_HIGH_SPEED;
5716
5717 /* compute bitmask from p1 value */
5718 if (IS_PINEVIEW(dev))
5719 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5720 else {
5721 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5722 if (IS_G4X(dev) && reduced_clock)
5723 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5724 }
5725 switch (clock->p2) {
5726 case 5:
5727 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5728 break;
5729 case 7:
5730 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5731 break;
5732 case 10:
5733 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5734 break;
5735 case 14:
5736 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5737 break;
5738 }
5739 if (INTEL_INFO(dev)->gen >= 4)
5740 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5741
5742 if (crtc->config.sdvo_tv_clock)
5743 dpll |= PLL_REF_INPUT_TVCLKINBC;
5744 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5745 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5746 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5747 else
5748 dpll |= PLL_REF_INPUT_DREFCLK;
5749
5750 dpll |= DPLL_VCO_ENABLE;
5751 crtc->config.dpll_hw_state.dpll = dpll;
5752
5753 if (INTEL_INFO(dev)->gen >= 4) {
5754 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5755 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5756 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5757 }
5758 }
5759
5760 static void i8xx_update_pll(struct intel_crtc *crtc,
5761 intel_clock_t *reduced_clock,
5762 int num_connectors)
5763 {
5764 struct drm_device *dev = crtc->base.dev;
5765 struct drm_i915_private *dev_priv = dev->dev_private;
5766 u32 dpll;
5767 struct dpll *clock = &crtc->config.dpll;
5768
5769 i9xx_update_pll_dividers(crtc, reduced_clock);
5770
5771 dpll = DPLL_VGA_MODE_DIS;
5772
5773 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5774 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5775 } else {
5776 if (clock->p1 == 2)
5777 dpll |= PLL_P1_DIVIDE_BY_TWO;
5778 else
5779 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5780 if (clock->p2 == 4)
5781 dpll |= PLL_P2_DIVIDE_BY_4;
5782 }
5783
5784 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5785 dpll |= DPLL_DVO_2X_MODE;
5786
5787 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5788 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5789 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5790 else
5791 dpll |= PLL_REF_INPUT_DREFCLK;
5792
5793 dpll |= DPLL_VCO_ENABLE;
5794 crtc->config.dpll_hw_state.dpll = dpll;
5795 }
5796
5797 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5798 {
5799 struct drm_device *dev = intel_crtc->base.dev;
5800 struct drm_i915_private *dev_priv = dev->dev_private;
5801 enum pipe pipe = intel_crtc->pipe;
5802 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5803 struct drm_display_mode *adjusted_mode =
5804 &intel_crtc->config.adjusted_mode;
5805 uint32_t crtc_vtotal, crtc_vblank_end;
5806 int vsyncshift = 0;
5807
5808 /* We need to be careful not to changed the adjusted mode, for otherwise
5809 * the hw state checker will get angry at the mismatch. */
5810 crtc_vtotal = adjusted_mode->crtc_vtotal;
5811 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5812
5813 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5814 /* the chip adds 2 halflines automatically */
5815 crtc_vtotal -= 1;
5816 crtc_vblank_end -= 1;
5817
5818 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5819 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5820 else
5821 vsyncshift = adjusted_mode->crtc_hsync_start -
5822 adjusted_mode->crtc_htotal / 2;
5823 if (vsyncshift < 0)
5824 vsyncshift += adjusted_mode->crtc_htotal;
5825 }
5826
5827 if (INTEL_INFO(dev)->gen > 3)
5828 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5829
5830 I915_WRITE(HTOTAL(cpu_transcoder),
5831 (adjusted_mode->crtc_hdisplay - 1) |
5832 ((adjusted_mode->crtc_htotal - 1) << 16));
5833 I915_WRITE(HBLANK(cpu_transcoder),
5834 (adjusted_mode->crtc_hblank_start - 1) |
5835 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5836 I915_WRITE(HSYNC(cpu_transcoder),
5837 (adjusted_mode->crtc_hsync_start - 1) |
5838 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5839
5840 I915_WRITE(VTOTAL(cpu_transcoder),
5841 (adjusted_mode->crtc_vdisplay - 1) |
5842 ((crtc_vtotal - 1) << 16));
5843 I915_WRITE(VBLANK(cpu_transcoder),
5844 (adjusted_mode->crtc_vblank_start - 1) |
5845 ((crtc_vblank_end - 1) << 16));
5846 I915_WRITE(VSYNC(cpu_transcoder),
5847 (adjusted_mode->crtc_vsync_start - 1) |
5848 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5849
5850 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5851 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5852 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5853 * bits. */
5854 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5855 (pipe == PIPE_B || pipe == PIPE_C))
5856 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5857
5858 /* pipesrc controls the size that is scaled from, which should
5859 * always be the user's requested size.
5860 */
5861 I915_WRITE(PIPESRC(pipe),
5862 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5863 (intel_crtc->config.pipe_src_h - 1));
5864 }
5865
5866 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5867 struct intel_crtc_config *pipe_config)
5868 {
5869 struct drm_device *dev = crtc->base.dev;
5870 struct drm_i915_private *dev_priv = dev->dev_private;
5871 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5872 uint32_t tmp;
5873
5874 tmp = I915_READ(HTOTAL(cpu_transcoder));
5875 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5876 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5877 tmp = I915_READ(HBLANK(cpu_transcoder));
5878 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5879 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5880 tmp = I915_READ(HSYNC(cpu_transcoder));
5881 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5882 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5883
5884 tmp = I915_READ(VTOTAL(cpu_transcoder));
5885 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5886 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5887 tmp = I915_READ(VBLANK(cpu_transcoder));
5888 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5889 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5890 tmp = I915_READ(VSYNC(cpu_transcoder));
5891 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5892 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5893
5894 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5895 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5896 pipe_config->adjusted_mode.crtc_vtotal += 1;
5897 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5898 }
5899
5900 tmp = I915_READ(PIPESRC(crtc->pipe));
5901 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5902 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5903
5904 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5905 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5906 }
5907
5908 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5909 struct intel_crtc_config *pipe_config)
5910 {
5911 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5912 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5913 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5914 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5915
5916 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5917 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5918 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5919 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5920
5921 mode->flags = pipe_config->adjusted_mode.flags;
5922
5923 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5924 mode->flags |= pipe_config->adjusted_mode.flags;
5925 }
5926
5927 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5928 {
5929 struct drm_device *dev = intel_crtc->base.dev;
5930 struct drm_i915_private *dev_priv = dev->dev_private;
5931 uint32_t pipeconf;
5932
5933 pipeconf = 0;
5934
5935 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5936 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5937 pipeconf |= PIPECONF_ENABLE;
5938
5939 if (intel_crtc->config.double_wide)
5940 pipeconf |= PIPECONF_DOUBLE_WIDE;
5941
5942 /* only g4x and later have fancy bpc/dither controls */
5943 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5944 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5945 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5946 pipeconf |= PIPECONF_DITHER_EN |
5947 PIPECONF_DITHER_TYPE_SP;
5948
5949 switch (intel_crtc->config.pipe_bpp) {
5950 case 18:
5951 pipeconf |= PIPECONF_6BPC;
5952 break;
5953 case 24:
5954 pipeconf |= PIPECONF_8BPC;
5955 break;
5956 case 30:
5957 pipeconf |= PIPECONF_10BPC;
5958 break;
5959 default:
5960 /* Case prevented by intel_choose_pipe_bpp_dither. */
5961 BUG();
5962 }
5963 }
5964
5965 if (HAS_PIPE_CXSR(dev)) {
5966 if (intel_crtc->lowfreq_avail) {
5967 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5968 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5969 } else {
5970 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5971 }
5972 }
5973
5974 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5975 if (INTEL_INFO(dev)->gen < 4 ||
5976 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5977 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5978 else
5979 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5980 } else
5981 pipeconf |= PIPECONF_PROGRESSIVE;
5982
5983 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5984 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5985
5986 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5987 POSTING_READ(PIPECONF(intel_crtc->pipe));
5988 }
5989
5990 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5991 int x, int y,
5992 struct drm_framebuffer *fb)
5993 {
5994 struct drm_device *dev = crtc->dev;
5995 struct drm_i915_private *dev_priv = dev->dev_private;
5996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5997 int refclk, num_connectors = 0;
5998 intel_clock_t clock, reduced_clock;
5999 bool ok, has_reduced_clock = false;
6000 bool is_lvds = false, is_dsi = false;
6001 struct intel_encoder *encoder;
6002 const intel_limit_t *limit;
6003
6004 for_each_encoder_on_crtc(dev, crtc, encoder) {
6005 switch (encoder->type) {
6006 case INTEL_OUTPUT_LVDS:
6007 is_lvds = true;
6008 break;
6009 case INTEL_OUTPUT_DSI:
6010 is_dsi = true;
6011 break;
6012 }
6013
6014 num_connectors++;
6015 }
6016
6017 if (is_dsi)
6018 return 0;
6019
6020 if (!intel_crtc->config.clock_set) {
6021 refclk = i9xx_get_refclk(crtc, num_connectors);
6022
6023 /*
6024 * Returns a set of divisors for the desired target clock with
6025 * the given refclk, or FALSE. The returned values represent
6026 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6027 * 2) / p1 / p2.
6028 */
6029 limit = intel_limit(crtc, refclk);
6030 ok = dev_priv->display.find_dpll(limit, crtc,
6031 intel_crtc->config.port_clock,
6032 refclk, NULL, &clock);
6033 if (!ok) {
6034 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6035 return -EINVAL;
6036 }
6037
6038 if (is_lvds && dev_priv->lvds_downclock_avail) {
6039 /*
6040 * Ensure we match the reduced clock's P to the target
6041 * clock. If the clocks don't match, we can't switch
6042 * the display clock by using the FP0/FP1. In such case
6043 * we will disable the LVDS downclock feature.
6044 */
6045 has_reduced_clock =
6046 dev_priv->display.find_dpll(limit, crtc,
6047 dev_priv->lvds_downclock,
6048 refclk, &clock,
6049 &reduced_clock);
6050 }
6051 /* Compat-code for transition, will disappear. */
6052 intel_crtc->config.dpll.n = clock.n;
6053 intel_crtc->config.dpll.m1 = clock.m1;
6054 intel_crtc->config.dpll.m2 = clock.m2;
6055 intel_crtc->config.dpll.p1 = clock.p1;
6056 intel_crtc->config.dpll.p2 = clock.p2;
6057 }
6058
6059 if (IS_GEN2(dev)) {
6060 i8xx_update_pll(intel_crtc,
6061 has_reduced_clock ? &reduced_clock : NULL,
6062 num_connectors);
6063 } else if (IS_CHERRYVIEW(dev)) {
6064 chv_update_pll(intel_crtc);
6065 } else if (IS_VALLEYVIEW(dev)) {
6066 vlv_update_pll(intel_crtc);
6067 } else {
6068 i9xx_update_pll(intel_crtc,
6069 has_reduced_clock ? &reduced_clock : NULL,
6070 num_connectors);
6071 }
6072
6073 return 0;
6074 }
6075
6076 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6077 struct intel_crtc_config *pipe_config)
6078 {
6079 struct drm_device *dev = crtc->base.dev;
6080 struct drm_i915_private *dev_priv = dev->dev_private;
6081 uint32_t tmp;
6082
6083 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6084 return;
6085
6086 tmp = I915_READ(PFIT_CONTROL);
6087 if (!(tmp & PFIT_ENABLE))
6088 return;
6089
6090 /* Check whether the pfit is attached to our pipe. */
6091 if (INTEL_INFO(dev)->gen < 4) {
6092 if (crtc->pipe != PIPE_B)
6093 return;
6094 } else {
6095 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6096 return;
6097 }
6098
6099 pipe_config->gmch_pfit.control = tmp;
6100 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6101 if (INTEL_INFO(dev)->gen < 5)
6102 pipe_config->gmch_pfit.lvds_border_bits =
6103 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6104 }
6105
6106 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6107 struct intel_crtc_config *pipe_config)
6108 {
6109 struct drm_device *dev = crtc->base.dev;
6110 struct drm_i915_private *dev_priv = dev->dev_private;
6111 int pipe = pipe_config->cpu_transcoder;
6112 intel_clock_t clock;
6113 u32 mdiv;
6114 int refclk = 100000;
6115
6116 mutex_lock(&dev_priv->dpio_lock);
6117 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6118 mutex_unlock(&dev_priv->dpio_lock);
6119
6120 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6121 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6122 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6123 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6124 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6125
6126 vlv_clock(refclk, &clock);
6127
6128 /* clock.dot is the fast clock */
6129 pipe_config->port_clock = clock.dot / 5;
6130 }
6131
6132 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6133 struct intel_plane_config *plane_config)
6134 {
6135 struct drm_device *dev = crtc->base.dev;
6136 struct drm_i915_private *dev_priv = dev->dev_private;
6137 u32 val, base, offset;
6138 int pipe = crtc->pipe, plane = crtc->plane;
6139 int fourcc, pixel_format;
6140 int aligned_height;
6141
6142 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6143 if (!crtc->base.primary->fb) {
6144 DRM_DEBUG_KMS("failed to alloc fb\n");
6145 return;
6146 }
6147
6148 val = I915_READ(DSPCNTR(plane));
6149
6150 if (INTEL_INFO(dev)->gen >= 4)
6151 if (val & DISPPLANE_TILED)
6152 plane_config->tiled = true;
6153
6154 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6155 fourcc = intel_format_to_fourcc(pixel_format);
6156 crtc->base.primary->fb->pixel_format = fourcc;
6157 crtc->base.primary->fb->bits_per_pixel =
6158 drm_format_plane_cpp(fourcc, 0) * 8;
6159
6160 if (INTEL_INFO(dev)->gen >= 4) {
6161 if (plane_config->tiled)
6162 offset = I915_READ(DSPTILEOFF(plane));
6163 else
6164 offset = I915_READ(DSPLINOFF(plane));
6165 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6166 } else {
6167 base = I915_READ(DSPADDR(plane));
6168 }
6169 plane_config->base = base;
6170
6171 val = I915_READ(PIPESRC(pipe));
6172 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6173 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6174
6175 val = I915_READ(DSPSTRIDE(pipe));
6176 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6177
6178 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6179 plane_config->tiled);
6180
6181 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
6182 aligned_height, PAGE_SIZE);
6183
6184 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6185 pipe, plane, crtc->base.primary->fb->width,
6186 crtc->base.primary->fb->height,
6187 crtc->base.primary->fb->bits_per_pixel, base,
6188 crtc->base.primary->fb->pitches[0],
6189 plane_config->size);
6190
6191 }
6192
6193 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6194 struct intel_crtc_config *pipe_config)
6195 {
6196 struct drm_device *dev = crtc->base.dev;
6197 struct drm_i915_private *dev_priv = dev->dev_private;
6198 int pipe = pipe_config->cpu_transcoder;
6199 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6200 intel_clock_t clock;
6201 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6202 int refclk = 100000;
6203
6204 mutex_lock(&dev_priv->dpio_lock);
6205 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6206 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6207 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6208 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6209 mutex_unlock(&dev_priv->dpio_lock);
6210
6211 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6212 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6213 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6214 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6215 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6216
6217 chv_clock(refclk, &clock);
6218
6219 /* clock.dot is the fast clock */
6220 pipe_config->port_clock = clock.dot / 5;
6221 }
6222
6223 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6224 struct intel_crtc_config *pipe_config)
6225 {
6226 struct drm_device *dev = crtc->base.dev;
6227 struct drm_i915_private *dev_priv = dev->dev_private;
6228 uint32_t tmp;
6229
6230 if (!intel_display_power_enabled(dev_priv,
6231 POWER_DOMAIN_PIPE(crtc->pipe)))
6232 return false;
6233
6234 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6235 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6236
6237 tmp = I915_READ(PIPECONF(crtc->pipe));
6238 if (!(tmp & PIPECONF_ENABLE))
6239 return false;
6240
6241 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6242 switch (tmp & PIPECONF_BPC_MASK) {
6243 case PIPECONF_6BPC:
6244 pipe_config->pipe_bpp = 18;
6245 break;
6246 case PIPECONF_8BPC:
6247 pipe_config->pipe_bpp = 24;
6248 break;
6249 case PIPECONF_10BPC:
6250 pipe_config->pipe_bpp = 30;
6251 break;
6252 default:
6253 break;
6254 }
6255 }
6256
6257 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6258 pipe_config->limited_color_range = true;
6259
6260 if (INTEL_INFO(dev)->gen < 4)
6261 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6262
6263 intel_get_pipe_timings(crtc, pipe_config);
6264
6265 i9xx_get_pfit_config(crtc, pipe_config);
6266
6267 if (INTEL_INFO(dev)->gen >= 4) {
6268 tmp = I915_READ(DPLL_MD(crtc->pipe));
6269 pipe_config->pixel_multiplier =
6270 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6271 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6272 pipe_config->dpll_hw_state.dpll_md = tmp;
6273 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6274 tmp = I915_READ(DPLL(crtc->pipe));
6275 pipe_config->pixel_multiplier =
6276 ((tmp & SDVO_MULTIPLIER_MASK)
6277 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6278 } else {
6279 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6280 * port and will be fixed up in the encoder->get_config
6281 * function. */
6282 pipe_config->pixel_multiplier = 1;
6283 }
6284 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6285 if (!IS_VALLEYVIEW(dev)) {
6286 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6287 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6288 } else {
6289 /* Mask out read-only status bits. */
6290 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6291 DPLL_PORTC_READY_MASK |
6292 DPLL_PORTB_READY_MASK);
6293 }
6294
6295 if (IS_CHERRYVIEW(dev))
6296 chv_crtc_clock_get(crtc, pipe_config);
6297 else if (IS_VALLEYVIEW(dev))
6298 vlv_crtc_clock_get(crtc, pipe_config);
6299 else
6300 i9xx_crtc_clock_get(crtc, pipe_config);
6301
6302 return true;
6303 }
6304
6305 static void ironlake_init_pch_refclk(struct drm_device *dev)
6306 {
6307 struct drm_i915_private *dev_priv = dev->dev_private;
6308 struct drm_mode_config *mode_config = &dev->mode_config;
6309 struct intel_encoder *encoder;
6310 u32 val, final;
6311 bool has_lvds = false;
6312 bool has_cpu_edp = false;
6313 bool has_panel = false;
6314 bool has_ck505 = false;
6315 bool can_ssc = false;
6316
6317 /* We need to take the global config into account */
6318 list_for_each_entry(encoder, &mode_config->encoder_list,
6319 base.head) {
6320 switch (encoder->type) {
6321 case INTEL_OUTPUT_LVDS:
6322 has_panel = true;
6323 has_lvds = true;
6324 break;
6325 case INTEL_OUTPUT_EDP:
6326 has_panel = true;
6327 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6328 has_cpu_edp = true;
6329 break;
6330 }
6331 }
6332
6333 if (HAS_PCH_IBX(dev)) {
6334 has_ck505 = dev_priv->vbt.display_clock_mode;
6335 can_ssc = has_ck505;
6336 } else {
6337 has_ck505 = false;
6338 can_ssc = true;
6339 }
6340
6341 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6342 has_panel, has_lvds, has_ck505);
6343
6344 /* Ironlake: try to setup display ref clock before DPLL
6345 * enabling. This is only under driver's control after
6346 * PCH B stepping, previous chipset stepping should be
6347 * ignoring this setting.
6348 */
6349 val = I915_READ(PCH_DREF_CONTROL);
6350
6351 /* As we must carefully and slowly disable/enable each source in turn,
6352 * compute the final state we want first and check if we need to
6353 * make any changes at all.
6354 */
6355 final = val;
6356 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6357 if (has_ck505)
6358 final |= DREF_NONSPREAD_CK505_ENABLE;
6359 else
6360 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6361
6362 final &= ~DREF_SSC_SOURCE_MASK;
6363 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6364 final &= ~DREF_SSC1_ENABLE;
6365
6366 if (has_panel) {
6367 final |= DREF_SSC_SOURCE_ENABLE;
6368
6369 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6370 final |= DREF_SSC1_ENABLE;
6371
6372 if (has_cpu_edp) {
6373 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6374 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6375 else
6376 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6377 } else
6378 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6379 } else {
6380 final |= DREF_SSC_SOURCE_DISABLE;
6381 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6382 }
6383
6384 if (final == val)
6385 return;
6386
6387 /* Always enable nonspread source */
6388 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6389
6390 if (has_ck505)
6391 val |= DREF_NONSPREAD_CK505_ENABLE;
6392 else
6393 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6394
6395 if (has_panel) {
6396 val &= ~DREF_SSC_SOURCE_MASK;
6397 val |= DREF_SSC_SOURCE_ENABLE;
6398
6399 /* SSC must be turned on before enabling the CPU output */
6400 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6401 DRM_DEBUG_KMS("Using SSC on panel\n");
6402 val |= DREF_SSC1_ENABLE;
6403 } else
6404 val &= ~DREF_SSC1_ENABLE;
6405
6406 /* Get SSC going before enabling the outputs */
6407 I915_WRITE(PCH_DREF_CONTROL, val);
6408 POSTING_READ(PCH_DREF_CONTROL);
6409 udelay(200);
6410
6411 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6412
6413 /* Enable CPU source on CPU attached eDP */
6414 if (has_cpu_edp) {
6415 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6416 DRM_DEBUG_KMS("Using SSC on eDP\n");
6417 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6418 } else
6419 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6420 } else
6421 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6422
6423 I915_WRITE(PCH_DREF_CONTROL, val);
6424 POSTING_READ(PCH_DREF_CONTROL);
6425 udelay(200);
6426 } else {
6427 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6428
6429 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6430
6431 /* Turn off CPU output */
6432 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6433
6434 I915_WRITE(PCH_DREF_CONTROL, val);
6435 POSTING_READ(PCH_DREF_CONTROL);
6436 udelay(200);
6437
6438 /* Turn off the SSC source */
6439 val &= ~DREF_SSC_SOURCE_MASK;
6440 val |= DREF_SSC_SOURCE_DISABLE;
6441
6442 /* Turn off SSC1 */
6443 val &= ~DREF_SSC1_ENABLE;
6444
6445 I915_WRITE(PCH_DREF_CONTROL, val);
6446 POSTING_READ(PCH_DREF_CONTROL);
6447 udelay(200);
6448 }
6449
6450 BUG_ON(val != final);
6451 }
6452
6453 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6454 {
6455 uint32_t tmp;
6456
6457 tmp = I915_READ(SOUTH_CHICKEN2);
6458 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6459 I915_WRITE(SOUTH_CHICKEN2, tmp);
6460
6461 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6462 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6463 DRM_ERROR("FDI mPHY reset assert timeout\n");
6464
6465 tmp = I915_READ(SOUTH_CHICKEN2);
6466 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6467 I915_WRITE(SOUTH_CHICKEN2, tmp);
6468
6469 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6470 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6471 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6472 }
6473
6474 /* WaMPhyProgramming:hsw */
6475 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6476 {
6477 uint32_t tmp;
6478
6479 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6480 tmp &= ~(0xFF << 24);
6481 tmp |= (0x12 << 24);
6482 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6483
6484 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6485 tmp |= (1 << 11);
6486 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6487
6488 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6489 tmp |= (1 << 11);
6490 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6491
6492 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6493 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6494 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6495
6496 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6497 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6498 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6499
6500 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6501 tmp &= ~(7 << 13);
6502 tmp |= (5 << 13);
6503 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6504
6505 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6506 tmp &= ~(7 << 13);
6507 tmp |= (5 << 13);
6508 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6509
6510 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6511 tmp &= ~0xFF;
6512 tmp |= 0x1C;
6513 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6514
6515 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6516 tmp &= ~0xFF;
6517 tmp |= 0x1C;
6518 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6519
6520 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6521 tmp &= ~(0xFF << 16);
6522 tmp |= (0x1C << 16);
6523 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6524
6525 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6526 tmp &= ~(0xFF << 16);
6527 tmp |= (0x1C << 16);
6528 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6529
6530 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6531 tmp |= (1 << 27);
6532 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6533
6534 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6535 tmp |= (1 << 27);
6536 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6537
6538 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6539 tmp &= ~(0xF << 28);
6540 tmp |= (4 << 28);
6541 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6542
6543 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6544 tmp &= ~(0xF << 28);
6545 tmp |= (4 << 28);
6546 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6547 }
6548
6549 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6550 * Programming" based on the parameters passed:
6551 * - Sequence to enable CLKOUT_DP
6552 * - Sequence to enable CLKOUT_DP without spread
6553 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6554 */
6555 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6556 bool with_fdi)
6557 {
6558 struct drm_i915_private *dev_priv = dev->dev_private;
6559 uint32_t reg, tmp;
6560
6561 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6562 with_spread = true;
6563 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6564 with_fdi, "LP PCH doesn't have FDI\n"))
6565 with_fdi = false;
6566
6567 mutex_lock(&dev_priv->dpio_lock);
6568
6569 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6570 tmp &= ~SBI_SSCCTL_DISABLE;
6571 tmp |= SBI_SSCCTL_PATHALT;
6572 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6573
6574 udelay(24);
6575
6576 if (with_spread) {
6577 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6578 tmp &= ~SBI_SSCCTL_PATHALT;
6579 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6580
6581 if (with_fdi) {
6582 lpt_reset_fdi_mphy(dev_priv);
6583 lpt_program_fdi_mphy(dev_priv);
6584 }
6585 }
6586
6587 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6588 SBI_GEN0 : SBI_DBUFF0;
6589 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6590 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6591 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6592
6593 mutex_unlock(&dev_priv->dpio_lock);
6594 }
6595
6596 /* Sequence to disable CLKOUT_DP */
6597 static void lpt_disable_clkout_dp(struct drm_device *dev)
6598 {
6599 struct drm_i915_private *dev_priv = dev->dev_private;
6600 uint32_t reg, tmp;
6601
6602 mutex_lock(&dev_priv->dpio_lock);
6603
6604 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6605 SBI_GEN0 : SBI_DBUFF0;
6606 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6607 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6608 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6609
6610 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6611 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6612 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6613 tmp |= SBI_SSCCTL_PATHALT;
6614 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6615 udelay(32);
6616 }
6617 tmp |= SBI_SSCCTL_DISABLE;
6618 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6619 }
6620
6621 mutex_unlock(&dev_priv->dpio_lock);
6622 }
6623
6624 static void lpt_init_pch_refclk(struct drm_device *dev)
6625 {
6626 struct drm_mode_config *mode_config = &dev->mode_config;
6627 struct intel_encoder *encoder;
6628 bool has_vga = false;
6629
6630 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6631 switch (encoder->type) {
6632 case INTEL_OUTPUT_ANALOG:
6633 has_vga = true;
6634 break;
6635 }
6636 }
6637
6638 if (has_vga)
6639 lpt_enable_clkout_dp(dev, true, true);
6640 else
6641 lpt_disable_clkout_dp(dev);
6642 }
6643
6644 /*
6645 * Initialize reference clocks when the driver loads
6646 */
6647 void intel_init_pch_refclk(struct drm_device *dev)
6648 {
6649 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6650 ironlake_init_pch_refclk(dev);
6651 else if (HAS_PCH_LPT(dev))
6652 lpt_init_pch_refclk(dev);
6653 }
6654
6655 static int ironlake_get_refclk(struct drm_crtc *crtc)
6656 {
6657 struct drm_device *dev = crtc->dev;
6658 struct drm_i915_private *dev_priv = dev->dev_private;
6659 struct intel_encoder *encoder;
6660 int num_connectors = 0;
6661 bool is_lvds = false;
6662
6663 for_each_encoder_on_crtc(dev, crtc, encoder) {
6664 switch (encoder->type) {
6665 case INTEL_OUTPUT_LVDS:
6666 is_lvds = true;
6667 break;
6668 }
6669 num_connectors++;
6670 }
6671
6672 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6673 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6674 dev_priv->vbt.lvds_ssc_freq);
6675 return dev_priv->vbt.lvds_ssc_freq;
6676 }
6677
6678 return 120000;
6679 }
6680
6681 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6682 {
6683 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6685 int pipe = intel_crtc->pipe;
6686 uint32_t val;
6687
6688 val = 0;
6689
6690 switch (intel_crtc->config.pipe_bpp) {
6691 case 18:
6692 val |= PIPECONF_6BPC;
6693 break;
6694 case 24:
6695 val |= PIPECONF_8BPC;
6696 break;
6697 case 30:
6698 val |= PIPECONF_10BPC;
6699 break;
6700 case 36:
6701 val |= PIPECONF_12BPC;
6702 break;
6703 default:
6704 /* Case prevented by intel_choose_pipe_bpp_dither. */
6705 BUG();
6706 }
6707
6708 if (intel_crtc->config.dither)
6709 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6710
6711 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6712 val |= PIPECONF_INTERLACED_ILK;
6713 else
6714 val |= PIPECONF_PROGRESSIVE;
6715
6716 if (intel_crtc->config.limited_color_range)
6717 val |= PIPECONF_COLOR_RANGE_SELECT;
6718
6719 I915_WRITE(PIPECONF(pipe), val);
6720 POSTING_READ(PIPECONF(pipe));
6721 }
6722
6723 /*
6724 * Set up the pipe CSC unit.
6725 *
6726 * Currently only full range RGB to limited range RGB conversion
6727 * is supported, but eventually this should handle various
6728 * RGB<->YCbCr scenarios as well.
6729 */
6730 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6731 {
6732 struct drm_device *dev = crtc->dev;
6733 struct drm_i915_private *dev_priv = dev->dev_private;
6734 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6735 int pipe = intel_crtc->pipe;
6736 uint16_t coeff = 0x7800; /* 1.0 */
6737
6738 /*
6739 * TODO: Check what kind of values actually come out of the pipe
6740 * with these coeff/postoff values and adjust to get the best
6741 * accuracy. Perhaps we even need to take the bpc value into
6742 * consideration.
6743 */
6744
6745 if (intel_crtc->config.limited_color_range)
6746 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6747
6748 /*
6749 * GY/GU and RY/RU should be the other way around according
6750 * to BSpec, but reality doesn't agree. Just set them up in
6751 * a way that results in the correct picture.
6752 */
6753 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6754 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6755
6756 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6757 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6758
6759 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6760 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6761
6762 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6763 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6764 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6765
6766 if (INTEL_INFO(dev)->gen > 6) {
6767 uint16_t postoff = 0;
6768
6769 if (intel_crtc->config.limited_color_range)
6770 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6771
6772 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6773 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6774 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6775
6776 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6777 } else {
6778 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6779
6780 if (intel_crtc->config.limited_color_range)
6781 mode |= CSC_BLACK_SCREEN_OFFSET;
6782
6783 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6784 }
6785 }
6786
6787 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6788 {
6789 struct drm_device *dev = crtc->dev;
6790 struct drm_i915_private *dev_priv = dev->dev_private;
6791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6792 enum pipe pipe = intel_crtc->pipe;
6793 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6794 uint32_t val;
6795
6796 val = 0;
6797
6798 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6799 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6800
6801 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6802 val |= PIPECONF_INTERLACED_ILK;
6803 else
6804 val |= PIPECONF_PROGRESSIVE;
6805
6806 I915_WRITE(PIPECONF(cpu_transcoder), val);
6807 POSTING_READ(PIPECONF(cpu_transcoder));
6808
6809 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6810 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6811
6812 if (IS_BROADWELL(dev)) {
6813 val = 0;
6814
6815 switch (intel_crtc->config.pipe_bpp) {
6816 case 18:
6817 val |= PIPEMISC_DITHER_6_BPC;
6818 break;
6819 case 24:
6820 val |= PIPEMISC_DITHER_8_BPC;
6821 break;
6822 case 30:
6823 val |= PIPEMISC_DITHER_10_BPC;
6824 break;
6825 case 36:
6826 val |= PIPEMISC_DITHER_12_BPC;
6827 break;
6828 default:
6829 /* Case prevented by pipe_config_set_bpp. */
6830 BUG();
6831 }
6832
6833 if (intel_crtc->config.dither)
6834 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6835
6836 I915_WRITE(PIPEMISC(pipe), val);
6837 }
6838 }
6839
6840 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6841 intel_clock_t *clock,
6842 bool *has_reduced_clock,
6843 intel_clock_t *reduced_clock)
6844 {
6845 struct drm_device *dev = crtc->dev;
6846 struct drm_i915_private *dev_priv = dev->dev_private;
6847 struct intel_encoder *intel_encoder;
6848 int refclk;
6849 const intel_limit_t *limit;
6850 bool ret, is_lvds = false;
6851
6852 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6853 switch (intel_encoder->type) {
6854 case INTEL_OUTPUT_LVDS:
6855 is_lvds = true;
6856 break;
6857 }
6858 }
6859
6860 refclk = ironlake_get_refclk(crtc);
6861
6862 /*
6863 * Returns a set of divisors for the desired target clock with the given
6864 * refclk, or FALSE. The returned values represent the clock equation:
6865 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6866 */
6867 limit = intel_limit(crtc, refclk);
6868 ret = dev_priv->display.find_dpll(limit, crtc,
6869 to_intel_crtc(crtc)->config.port_clock,
6870 refclk, NULL, clock);
6871 if (!ret)
6872 return false;
6873
6874 if (is_lvds && dev_priv->lvds_downclock_avail) {
6875 /*
6876 * Ensure we match the reduced clock's P to the target clock.
6877 * If the clocks don't match, we can't switch the display clock
6878 * by using the FP0/FP1. In such case we will disable the LVDS
6879 * downclock feature.
6880 */
6881 *has_reduced_clock =
6882 dev_priv->display.find_dpll(limit, crtc,
6883 dev_priv->lvds_downclock,
6884 refclk, clock,
6885 reduced_clock);
6886 }
6887
6888 return true;
6889 }
6890
6891 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6892 {
6893 /*
6894 * Account for spread spectrum to avoid
6895 * oversubscribing the link. Max center spread
6896 * is 2.5%; use 5% for safety's sake.
6897 */
6898 u32 bps = target_clock * bpp * 21 / 20;
6899 return DIV_ROUND_UP(bps, link_bw * 8);
6900 }
6901
6902 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6903 {
6904 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6905 }
6906
6907 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6908 u32 *fp,
6909 intel_clock_t *reduced_clock, u32 *fp2)
6910 {
6911 struct drm_crtc *crtc = &intel_crtc->base;
6912 struct drm_device *dev = crtc->dev;
6913 struct drm_i915_private *dev_priv = dev->dev_private;
6914 struct intel_encoder *intel_encoder;
6915 uint32_t dpll;
6916 int factor, num_connectors = 0;
6917 bool is_lvds = false, is_sdvo = false;
6918
6919 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6920 switch (intel_encoder->type) {
6921 case INTEL_OUTPUT_LVDS:
6922 is_lvds = true;
6923 break;
6924 case INTEL_OUTPUT_SDVO:
6925 case INTEL_OUTPUT_HDMI:
6926 is_sdvo = true;
6927 break;
6928 }
6929
6930 num_connectors++;
6931 }
6932
6933 /* Enable autotuning of the PLL clock (if permissible) */
6934 factor = 21;
6935 if (is_lvds) {
6936 if ((intel_panel_use_ssc(dev_priv) &&
6937 dev_priv->vbt.lvds_ssc_freq == 100000) ||
6938 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6939 factor = 25;
6940 } else if (intel_crtc->config.sdvo_tv_clock)
6941 factor = 20;
6942
6943 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6944 *fp |= FP_CB_TUNE;
6945
6946 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6947 *fp2 |= FP_CB_TUNE;
6948
6949 dpll = 0;
6950
6951 if (is_lvds)
6952 dpll |= DPLLB_MODE_LVDS;
6953 else
6954 dpll |= DPLLB_MODE_DAC_SERIAL;
6955
6956 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6957 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6958
6959 if (is_sdvo)
6960 dpll |= DPLL_SDVO_HIGH_SPEED;
6961 if (intel_crtc->config.has_dp_encoder)
6962 dpll |= DPLL_SDVO_HIGH_SPEED;
6963
6964 /* compute bitmask from p1 value */
6965 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6966 /* also FPA1 */
6967 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6968
6969 switch (intel_crtc->config.dpll.p2) {
6970 case 5:
6971 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6972 break;
6973 case 7:
6974 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6975 break;
6976 case 10:
6977 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6978 break;
6979 case 14:
6980 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6981 break;
6982 }
6983
6984 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6985 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6986 else
6987 dpll |= PLL_REF_INPUT_DREFCLK;
6988
6989 return dpll | DPLL_VCO_ENABLE;
6990 }
6991
6992 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6993 int x, int y,
6994 struct drm_framebuffer *fb)
6995 {
6996 struct drm_device *dev = crtc->dev;
6997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6998 int num_connectors = 0;
6999 intel_clock_t clock, reduced_clock;
7000 u32 dpll = 0, fp = 0, fp2 = 0;
7001 bool ok, has_reduced_clock = false;
7002 bool is_lvds = false;
7003 struct intel_encoder *encoder;
7004 struct intel_shared_dpll *pll;
7005
7006 for_each_encoder_on_crtc(dev, crtc, encoder) {
7007 switch (encoder->type) {
7008 case INTEL_OUTPUT_LVDS:
7009 is_lvds = true;
7010 break;
7011 }
7012
7013 num_connectors++;
7014 }
7015
7016 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7017 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7018
7019 ok = ironlake_compute_clocks(crtc, &clock,
7020 &has_reduced_clock, &reduced_clock);
7021 if (!ok && !intel_crtc->config.clock_set) {
7022 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7023 return -EINVAL;
7024 }
7025 /* Compat-code for transition, will disappear. */
7026 if (!intel_crtc->config.clock_set) {
7027 intel_crtc->config.dpll.n = clock.n;
7028 intel_crtc->config.dpll.m1 = clock.m1;
7029 intel_crtc->config.dpll.m2 = clock.m2;
7030 intel_crtc->config.dpll.p1 = clock.p1;
7031 intel_crtc->config.dpll.p2 = clock.p2;
7032 }
7033
7034 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7035 if (intel_crtc->config.has_pch_encoder) {
7036 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7037 if (has_reduced_clock)
7038 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7039
7040 dpll = ironlake_compute_dpll(intel_crtc,
7041 &fp, &reduced_clock,
7042 has_reduced_clock ? &fp2 : NULL);
7043
7044 intel_crtc->config.dpll_hw_state.dpll = dpll;
7045 intel_crtc->config.dpll_hw_state.fp0 = fp;
7046 if (has_reduced_clock)
7047 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7048 else
7049 intel_crtc->config.dpll_hw_state.fp1 = fp;
7050
7051 pll = intel_get_shared_dpll(intel_crtc);
7052 if (pll == NULL) {
7053 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7054 pipe_name(intel_crtc->pipe));
7055 return -EINVAL;
7056 }
7057 } else
7058 intel_put_shared_dpll(intel_crtc);
7059
7060 if (is_lvds && has_reduced_clock && i915.powersave)
7061 intel_crtc->lowfreq_avail = true;
7062 else
7063 intel_crtc->lowfreq_avail = false;
7064
7065 return 0;
7066 }
7067
7068 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7069 struct intel_link_m_n *m_n)
7070 {
7071 struct drm_device *dev = crtc->base.dev;
7072 struct drm_i915_private *dev_priv = dev->dev_private;
7073 enum pipe pipe = crtc->pipe;
7074
7075 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7076 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7077 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7078 & ~TU_SIZE_MASK;
7079 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7080 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7081 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7082 }
7083
7084 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7085 enum transcoder transcoder,
7086 struct intel_link_m_n *m_n)
7087 {
7088 struct drm_device *dev = crtc->base.dev;
7089 struct drm_i915_private *dev_priv = dev->dev_private;
7090 enum pipe pipe = crtc->pipe;
7091
7092 if (INTEL_INFO(dev)->gen >= 5) {
7093 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7094 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7095 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7096 & ~TU_SIZE_MASK;
7097 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7098 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7099 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7100 } else {
7101 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7102 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7103 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7104 & ~TU_SIZE_MASK;
7105 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7106 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7107 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7108 }
7109 }
7110
7111 void intel_dp_get_m_n(struct intel_crtc *crtc,
7112 struct intel_crtc_config *pipe_config)
7113 {
7114 if (crtc->config.has_pch_encoder)
7115 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7116 else
7117 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7118 &pipe_config->dp_m_n);
7119 }
7120
7121 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7122 struct intel_crtc_config *pipe_config)
7123 {
7124 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7125 &pipe_config->fdi_m_n);
7126 }
7127
7128 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7129 struct intel_crtc_config *pipe_config)
7130 {
7131 struct drm_device *dev = crtc->base.dev;
7132 struct drm_i915_private *dev_priv = dev->dev_private;
7133 uint32_t tmp;
7134
7135 tmp = I915_READ(PF_CTL(crtc->pipe));
7136
7137 if (tmp & PF_ENABLE) {
7138 pipe_config->pch_pfit.enabled = true;
7139 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7140 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7141
7142 /* We currently do not free assignements of panel fitters on
7143 * ivb/hsw (since we don't use the higher upscaling modes which
7144 * differentiates them) so just WARN about this case for now. */
7145 if (IS_GEN7(dev)) {
7146 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7147 PF_PIPE_SEL_IVB(crtc->pipe));
7148 }
7149 }
7150 }
7151
7152 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7153 struct intel_plane_config *plane_config)
7154 {
7155 struct drm_device *dev = crtc->base.dev;
7156 struct drm_i915_private *dev_priv = dev->dev_private;
7157 u32 val, base, offset;
7158 int pipe = crtc->pipe, plane = crtc->plane;
7159 int fourcc, pixel_format;
7160 int aligned_height;
7161
7162 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7163 if (!crtc->base.primary->fb) {
7164 DRM_DEBUG_KMS("failed to alloc fb\n");
7165 return;
7166 }
7167
7168 val = I915_READ(DSPCNTR(plane));
7169
7170 if (INTEL_INFO(dev)->gen >= 4)
7171 if (val & DISPPLANE_TILED)
7172 plane_config->tiled = true;
7173
7174 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7175 fourcc = intel_format_to_fourcc(pixel_format);
7176 crtc->base.primary->fb->pixel_format = fourcc;
7177 crtc->base.primary->fb->bits_per_pixel =
7178 drm_format_plane_cpp(fourcc, 0) * 8;
7179
7180 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7181 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7182 offset = I915_READ(DSPOFFSET(plane));
7183 } else {
7184 if (plane_config->tiled)
7185 offset = I915_READ(DSPTILEOFF(plane));
7186 else
7187 offset = I915_READ(DSPLINOFF(plane));
7188 }
7189 plane_config->base = base;
7190
7191 val = I915_READ(PIPESRC(pipe));
7192 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7193 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7194
7195 val = I915_READ(DSPSTRIDE(pipe));
7196 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7197
7198 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7199 plane_config->tiled);
7200
7201 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
7202 aligned_height, PAGE_SIZE);
7203
7204 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7205 pipe, plane, crtc->base.primary->fb->width,
7206 crtc->base.primary->fb->height,
7207 crtc->base.primary->fb->bits_per_pixel, base,
7208 crtc->base.primary->fb->pitches[0],
7209 plane_config->size);
7210 }
7211
7212 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7213 struct intel_crtc_config *pipe_config)
7214 {
7215 struct drm_device *dev = crtc->base.dev;
7216 struct drm_i915_private *dev_priv = dev->dev_private;
7217 uint32_t tmp;
7218
7219 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7220 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7221
7222 tmp = I915_READ(PIPECONF(crtc->pipe));
7223 if (!(tmp & PIPECONF_ENABLE))
7224 return false;
7225
7226 switch (tmp & PIPECONF_BPC_MASK) {
7227 case PIPECONF_6BPC:
7228 pipe_config->pipe_bpp = 18;
7229 break;
7230 case PIPECONF_8BPC:
7231 pipe_config->pipe_bpp = 24;
7232 break;
7233 case PIPECONF_10BPC:
7234 pipe_config->pipe_bpp = 30;
7235 break;
7236 case PIPECONF_12BPC:
7237 pipe_config->pipe_bpp = 36;
7238 break;
7239 default:
7240 break;
7241 }
7242
7243 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7244 pipe_config->limited_color_range = true;
7245
7246 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7247 struct intel_shared_dpll *pll;
7248
7249 pipe_config->has_pch_encoder = true;
7250
7251 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7252 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7253 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7254
7255 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7256
7257 if (HAS_PCH_IBX(dev_priv->dev)) {
7258 pipe_config->shared_dpll =
7259 (enum intel_dpll_id) crtc->pipe;
7260 } else {
7261 tmp = I915_READ(PCH_DPLL_SEL);
7262 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7263 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7264 else
7265 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7266 }
7267
7268 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7269
7270 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7271 &pipe_config->dpll_hw_state));
7272
7273 tmp = pipe_config->dpll_hw_state.dpll;
7274 pipe_config->pixel_multiplier =
7275 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7276 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7277
7278 ironlake_pch_clock_get(crtc, pipe_config);
7279 } else {
7280 pipe_config->pixel_multiplier = 1;
7281 }
7282
7283 intel_get_pipe_timings(crtc, pipe_config);
7284
7285 ironlake_get_pfit_config(crtc, pipe_config);
7286
7287 return true;
7288 }
7289
7290 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7291 {
7292 struct drm_device *dev = dev_priv->dev;
7293 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
7294 struct intel_crtc *crtc;
7295
7296 for_each_intel_crtc(dev, crtc)
7297 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7298 pipe_name(crtc->pipe));
7299
7300 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7301 WARN(plls->spll_refcount, "SPLL enabled\n");
7302 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
7303 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
7304 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7305 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7306 "CPU PWM1 enabled\n");
7307 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7308 "CPU PWM2 enabled\n");
7309 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7310 "PCH PWM1 enabled\n");
7311 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7312 "Utility pin enabled\n");
7313 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7314
7315 /*
7316 * In theory we can still leave IRQs enabled, as long as only the HPD
7317 * interrupts remain enabled. We used to check for that, but since it's
7318 * gen-specific and since we only disable LCPLL after we fully disable
7319 * the interrupts, the check below should be enough.
7320 */
7321 WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
7322 }
7323
7324 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7325 {
7326 struct drm_device *dev = dev_priv->dev;
7327
7328 if (IS_HASWELL(dev)) {
7329 mutex_lock(&dev_priv->rps.hw_lock);
7330 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7331 val))
7332 DRM_ERROR("Failed to disable D_COMP\n");
7333 mutex_unlock(&dev_priv->rps.hw_lock);
7334 } else {
7335 I915_WRITE(D_COMP, val);
7336 }
7337 POSTING_READ(D_COMP);
7338 }
7339
7340 /*
7341 * This function implements pieces of two sequences from BSpec:
7342 * - Sequence for display software to disable LCPLL
7343 * - Sequence for display software to allow package C8+
7344 * The steps implemented here are just the steps that actually touch the LCPLL
7345 * register. Callers should take care of disabling all the display engine
7346 * functions, doing the mode unset, fixing interrupts, etc.
7347 */
7348 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7349 bool switch_to_fclk, bool allow_power_down)
7350 {
7351 uint32_t val;
7352
7353 assert_can_disable_lcpll(dev_priv);
7354
7355 val = I915_READ(LCPLL_CTL);
7356
7357 if (switch_to_fclk) {
7358 val |= LCPLL_CD_SOURCE_FCLK;
7359 I915_WRITE(LCPLL_CTL, val);
7360
7361 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7362 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7363 DRM_ERROR("Switching to FCLK failed\n");
7364
7365 val = I915_READ(LCPLL_CTL);
7366 }
7367
7368 val |= LCPLL_PLL_DISABLE;
7369 I915_WRITE(LCPLL_CTL, val);
7370 POSTING_READ(LCPLL_CTL);
7371
7372 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7373 DRM_ERROR("LCPLL still locked\n");
7374
7375 val = I915_READ(D_COMP);
7376 val |= D_COMP_COMP_DISABLE;
7377 hsw_write_dcomp(dev_priv, val);
7378 ndelay(100);
7379
7380 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
7381 DRM_ERROR("D_COMP RCOMP still in progress\n");
7382
7383 if (allow_power_down) {
7384 val = I915_READ(LCPLL_CTL);
7385 val |= LCPLL_POWER_DOWN_ALLOW;
7386 I915_WRITE(LCPLL_CTL, val);
7387 POSTING_READ(LCPLL_CTL);
7388 }
7389 }
7390
7391 /*
7392 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7393 * source.
7394 */
7395 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7396 {
7397 uint32_t val;
7398 unsigned long irqflags;
7399
7400 val = I915_READ(LCPLL_CTL);
7401
7402 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7403 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7404 return;
7405
7406 /*
7407 * Make sure we're not on PC8 state before disabling PC8, otherwise
7408 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7409 *
7410 * The other problem is that hsw_restore_lcpll() is called as part of
7411 * the runtime PM resume sequence, so we can't just call
7412 * gen6_gt_force_wake_get() because that function calls
7413 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7414 * while we are on the resume sequence. So to solve this problem we have
7415 * to call special forcewake code that doesn't touch runtime PM and
7416 * doesn't enable the forcewake delayed work.
7417 */
7418 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7419 if (dev_priv->uncore.forcewake_count++ == 0)
7420 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7421 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7422
7423 if (val & LCPLL_POWER_DOWN_ALLOW) {
7424 val &= ~LCPLL_POWER_DOWN_ALLOW;
7425 I915_WRITE(LCPLL_CTL, val);
7426 POSTING_READ(LCPLL_CTL);
7427 }
7428
7429 val = I915_READ(D_COMP);
7430 val |= D_COMP_COMP_FORCE;
7431 val &= ~D_COMP_COMP_DISABLE;
7432 hsw_write_dcomp(dev_priv, val);
7433
7434 val = I915_READ(LCPLL_CTL);
7435 val &= ~LCPLL_PLL_DISABLE;
7436 I915_WRITE(LCPLL_CTL, val);
7437
7438 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7439 DRM_ERROR("LCPLL not locked yet\n");
7440
7441 if (val & LCPLL_CD_SOURCE_FCLK) {
7442 val = I915_READ(LCPLL_CTL);
7443 val &= ~LCPLL_CD_SOURCE_FCLK;
7444 I915_WRITE(LCPLL_CTL, val);
7445
7446 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7447 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7448 DRM_ERROR("Switching back to LCPLL failed\n");
7449 }
7450
7451 /* See the big comment above. */
7452 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7453 if (--dev_priv->uncore.forcewake_count == 0)
7454 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7455 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7456 }
7457
7458 /*
7459 * Package states C8 and deeper are really deep PC states that can only be
7460 * reached when all the devices on the system allow it, so even if the graphics
7461 * device allows PC8+, it doesn't mean the system will actually get to these
7462 * states. Our driver only allows PC8+ when going into runtime PM.
7463 *
7464 * The requirements for PC8+ are that all the outputs are disabled, the power
7465 * well is disabled and most interrupts are disabled, and these are also
7466 * requirements for runtime PM. When these conditions are met, we manually do
7467 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7468 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7469 * hang the machine.
7470 *
7471 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7472 * the state of some registers, so when we come back from PC8+ we need to
7473 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7474 * need to take care of the registers kept by RC6. Notice that this happens even
7475 * if we don't put the device in PCI D3 state (which is what currently happens
7476 * because of the runtime PM support).
7477 *
7478 * For more, read "Display Sequences for Package C8" on the hardware
7479 * documentation.
7480 */
7481 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7482 {
7483 struct drm_device *dev = dev_priv->dev;
7484 uint32_t val;
7485
7486 DRM_DEBUG_KMS("Enabling package C8+\n");
7487
7488 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7489 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7490 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7491 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7492 }
7493
7494 lpt_disable_clkout_dp(dev);
7495 hsw_disable_lcpll(dev_priv, true, true);
7496 }
7497
7498 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7499 {
7500 struct drm_device *dev = dev_priv->dev;
7501 uint32_t val;
7502
7503 DRM_DEBUG_KMS("Disabling package C8+\n");
7504
7505 hsw_restore_lcpll(dev_priv);
7506 lpt_init_pch_refclk(dev);
7507
7508 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7509 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7510 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7511 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7512 }
7513
7514 intel_prepare_ddi(dev);
7515 }
7516
7517 static void snb_modeset_global_resources(struct drm_device *dev)
7518 {
7519 modeset_update_crtc_power_domains(dev);
7520 }
7521
7522 static void haswell_modeset_global_resources(struct drm_device *dev)
7523 {
7524 modeset_update_crtc_power_domains(dev);
7525 }
7526
7527 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7528 int x, int y,
7529 struct drm_framebuffer *fb)
7530 {
7531 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7532
7533 if (!intel_ddi_pll_select(intel_crtc))
7534 return -EINVAL;
7535 intel_ddi_pll_enable(intel_crtc);
7536
7537 intel_crtc->lowfreq_avail = false;
7538
7539 return 0;
7540 }
7541
7542 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7543 struct intel_crtc_config *pipe_config)
7544 {
7545 struct drm_device *dev = crtc->base.dev;
7546 struct drm_i915_private *dev_priv = dev->dev_private;
7547 enum intel_display_power_domain pfit_domain;
7548 uint32_t tmp;
7549
7550 if (!intel_display_power_enabled(dev_priv,
7551 POWER_DOMAIN_PIPE(crtc->pipe)))
7552 return false;
7553
7554 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7555 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7556
7557 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7558 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7559 enum pipe trans_edp_pipe;
7560 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7561 default:
7562 WARN(1, "unknown pipe linked to edp transcoder\n");
7563 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7564 case TRANS_DDI_EDP_INPUT_A_ON:
7565 trans_edp_pipe = PIPE_A;
7566 break;
7567 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7568 trans_edp_pipe = PIPE_B;
7569 break;
7570 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7571 trans_edp_pipe = PIPE_C;
7572 break;
7573 }
7574
7575 if (trans_edp_pipe == crtc->pipe)
7576 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7577 }
7578
7579 if (!intel_display_power_enabled(dev_priv,
7580 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7581 return false;
7582
7583 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7584 if (!(tmp & PIPECONF_ENABLE))
7585 return false;
7586
7587 /*
7588 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7589 * DDI E. So just check whether this pipe is wired to DDI E and whether
7590 * the PCH transcoder is on.
7591 */
7592 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7593 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7594 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7595 pipe_config->has_pch_encoder = true;
7596
7597 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7598 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7599 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7600
7601 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7602 }
7603
7604 intel_get_pipe_timings(crtc, pipe_config);
7605
7606 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7607 if (intel_display_power_enabled(dev_priv, pfit_domain))
7608 ironlake_get_pfit_config(crtc, pipe_config);
7609
7610 if (IS_HASWELL(dev))
7611 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7612 (I915_READ(IPS_CTL) & IPS_ENABLE);
7613
7614 pipe_config->pixel_multiplier = 1;
7615
7616 return true;
7617 }
7618
7619 static struct {
7620 int clock;
7621 u32 config;
7622 } hdmi_audio_clock[] = {
7623 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7624 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7625 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7626 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7627 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7628 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7629 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7630 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7631 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7632 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7633 };
7634
7635 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7636 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7637 {
7638 int i;
7639
7640 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7641 if (mode->clock == hdmi_audio_clock[i].clock)
7642 break;
7643 }
7644
7645 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7646 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7647 i = 1;
7648 }
7649
7650 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7651 hdmi_audio_clock[i].clock,
7652 hdmi_audio_clock[i].config);
7653
7654 return hdmi_audio_clock[i].config;
7655 }
7656
7657 static bool intel_eld_uptodate(struct drm_connector *connector,
7658 int reg_eldv, uint32_t bits_eldv,
7659 int reg_elda, uint32_t bits_elda,
7660 int reg_edid)
7661 {
7662 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7663 uint8_t *eld = connector->eld;
7664 uint32_t i;
7665
7666 i = I915_READ(reg_eldv);
7667 i &= bits_eldv;
7668
7669 if (!eld[0])
7670 return !i;
7671
7672 if (!i)
7673 return false;
7674
7675 i = I915_READ(reg_elda);
7676 i &= ~bits_elda;
7677 I915_WRITE(reg_elda, i);
7678
7679 for (i = 0; i < eld[2]; i++)
7680 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7681 return false;
7682
7683 return true;
7684 }
7685
7686 static void g4x_write_eld(struct drm_connector *connector,
7687 struct drm_crtc *crtc,
7688 struct drm_display_mode *mode)
7689 {
7690 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7691 uint8_t *eld = connector->eld;
7692 uint32_t eldv;
7693 uint32_t len;
7694 uint32_t i;
7695
7696 i = I915_READ(G4X_AUD_VID_DID);
7697
7698 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7699 eldv = G4X_ELDV_DEVCL_DEVBLC;
7700 else
7701 eldv = G4X_ELDV_DEVCTG;
7702
7703 if (intel_eld_uptodate(connector,
7704 G4X_AUD_CNTL_ST, eldv,
7705 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7706 G4X_HDMIW_HDMIEDID))
7707 return;
7708
7709 i = I915_READ(G4X_AUD_CNTL_ST);
7710 i &= ~(eldv | G4X_ELD_ADDR);
7711 len = (i >> 9) & 0x1f; /* ELD buffer size */
7712 I915_WRITE(G4X_AUD_CNTL_ST, i);
7713
7714 if (!eld[0])
7715 return;
7716
7717 len = min_t(uint8_t, eld[2], len);
7718 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7719 for (i = 0; i < len; i++)
7720 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7721
7722 i = I915_READ(G4X_AUD_CNTL_ST);
7723 i |= eldv;
7724 I915_WRITE(G4X_AUD_CNTL_ST, i);
7725 }
7726
7727 static void haswell_write_eld(struct drm_connector *connector,
7728 struct drm_crtc *crtc,
7729 struct drm_display_mode *mode)
7730 {
7731 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7732 uint8_t *eld = connector->eld;
7733 uint32_t eldv;
7734 uint32_t i;
7735 int len;
7736 int pipe = to_intel_crtc(crtc)->pipe;
7737 int tmp;
7738
7739 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7740 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7741 int aud_config = HSW_AUD_CFG(pipe);
7742 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7743
7744 /* Audio output enable */
7745 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7746 tmp = I915_READ(aud_cntrl_st2);
7747 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7748 I915_WRITE(aud_cntrl_st2, tmp);
7749 POSTING_READ(aud_cntrl_st2);
7750
7751 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7752
7753 /* Set ELD valid state */
7754 tmp = I915_READ(aud_cntrl_st2);
7755 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7756 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7757 I915_WRITE(aud_cntrl_st2, tmp);
7758 tmp = I915_READ(aud_cntrl_st2);
7759 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7760
7761 /* Enable HDMI mode */
7762 tmp = I915_READ(aud_config);
7763 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7764 /* clear N_programing_enable and N_value_index */
7765 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7766 I915_WRITE(aud_config, tmp);
7767
7768 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7769
7770 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7771
7772 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7773 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7774 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7775 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7776 } else {
7777 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7778 }
7779
7780 if (intel_eld_uptodate(connector,
7781 aud_cntrl_st2, eldv,
7782 aud_cntl_st, IBX_ELD_ADDRESS,
7783 hdmiw_hdmiedid))
7784 return;
7785
7786 i = I915_READ(aud_cntrl_st2);
7787 i &= ~eldv;
7788 I915_WRITE(aud_cntrl_st2, i);
7789
7790 if (!eld[0])
7791 return;
7792
7793 i = I915_READ(aud_cntl_st);
7794 i &= ~IBX_ELD_ADDRESS;
7795 I915_WRITE(aud_cntl_st, i);
7796 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7797 DRM_DEBUG_DRIVER("port num:%d\n", i);
7798
7799 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7800 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7801 for (i = 0; i < len; i++)
7802 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7803
7804 i = I915_READ(aud_cntrl_st2);
7805 i |= eldv;
7806 I915_WRITE(aud_cntrl_st2, i);
7807
7808 }
7809
7810 static void ironlake_write_eld(struct drm_connector *connector,
7811 struct drm_crtc *crtc,
7812 struct drm_display_mode *mode)
7813 {
7814 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7815 uint8_t *eld = connector->eld;
7816 uint32_t eldv;
7817 uint32_t i;
7818 int len;
7819 int hdmiw_hdmiedid;
7820 int aud_config;
7821 int aud_cntl_st;
7822 int aud_cntrl_st2;
7823 int pipe = to_intel_crtc(crtc)->pipe;
7824
7825 if (HAS_PCH_IBX(connector->dev)) {
7826 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7827 aud_config = IBX_AUD_CFG(pipe);
7828 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7829 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7830 } else if (IS_VALLEYVIEW(connector->dev)) {
7831 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7832 aud_config = VLV_AUD_CFG(pipe);
7833 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7834 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7835 } else {
7836 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7837 aud_config = CPT_AUD_CFG(pipe);
7838 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7839 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7840 }
7841
7842 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7843
7844 if (IS_VALLEYVIEW(connector->dev)) {
7845 struct intel_encoder *intel_encoder;
7846 struct intel_digital_port *intel_dig_port;
7847
7848 intel_encoder = intel_attached_encoder(connector);
7849 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7850 i = intel_dig_port->port;
7851 } else {
7852 i = I915_READ(aud_cntl_st);
7853 i = (i >> 29) & DIP_PORT_SEL_MASK;
7854 /* DIP_Port_Select, 0x1 = PortB */
7855 }
7856
7857 if (!i) {
7858 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7859 /* operate blindly on all ports */
7860 eldv = IBX_ELD_VALIDB;
7861 eldv |= IBX_ELD_VALIDB << 4;
7862 eldv |= IBX_ELD_VALIDB << 8;
7863 } else {
7864 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7865 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7866 }
7867
7868 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7869 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7870 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7871 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7872 } else {
7873 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7874 }
7875
7876 if (intel_eld_uptodate(connector,
7877 aud_cntrl_st2, eldv,
7878 aud_cntl_st, IBX_ELD_ADDRESS,
7879 hdmiw_hdmiedid))
7880 return;
7881
7882 i = I915_READ(aud_cntrl_st2);
7883 i &= ~eldv;
7884 I915_WRITE(aud_cntrl_st2, i);
7885
7886 if (!eld[0])
7887 return;
7888
7889 i = I915_READ(aud_cntl_st);
7890 i &= ~IBX_ELD_ADDRESS;
7891 I915_WRITE(aud_cntl_st, i);
7892
7893 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7894 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7895 for (i = 0; i < len; i++)
7896 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7897
7898 i = I915_READ(aud_cntrl_st2);
7899 i |= eldv;
7900 I915_WRITE(aud_cntrl_st2, i);
7901 }
7902
7903 void intel_write_eld(struct drm_encoder *encoder,
7904 struct drm_display_mode *mode)
7905 {
7906 struct drm_crtc *crtc = encoder->crtc;
7907 struct drm_connector *connector;
7908 struct drm_device *dev = encoder->dev;
7909 struct drm_i915_private *dev_priv = dev->dev_private;
7910
7911 connector = drm_select_eld(encoder, mode);
7912 if (!connector)
7913 return;
7914
7915 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7916 connector->base.id,
7917 connector->name,
7918 connector->encoder->base.id,
7919 connector->encoder->name);
7920
7921 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7922
7923 if (dev_priv->display.write_eld)
7924 dev_priv->display.write_eld(connector, crtc, mode);
7925 }
7926
7927 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7928 {
7929 struct drm_device *dev = crtc->dev;
7930 struct drm_i915_private *dev_priv = dev->dev_private;
7931 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7932 uint32_t cntl;
7933
7934 if (base != intel_crtc->cursor_base) {
7935 /* On these chipsets we can only modify the base whilst
7936 * the cursor is disabled.
7937 */
7938 if (intel_crtc->cursor_cntl) {
7939 I915_WRITE(_CURACNTR, 0);
7940 POSTING_READ(_CURACNTR);
7941 intel_crtc->cursor_cntl = 0;
7942 }
7943
7944 I915_WRITE(_CURABASE, base);
7945 POSTING_READ(_CURABASE);
7946 }
7947
7948 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7949 cntl = 0;
7950 if (base)
7951 cntl = (CURSOR_ENABLE |
7952 CURSOR_GAMMA_ENABLE |
7953 CURSOR_FORMAT_ARGB);
7954 if (intel_crtc->cursor_cntl != cntl) {
7955 I915_WRITE(_CURACNTR, cntl);
7956 POSTING_READ(_CURACNTR);
7957 intel_crtc->cursor_cntl = cntl;
7958 }
7959 }
7960
7961 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7962 {
7963 struct drm_device *dev = crtc->dev;
7964 struct drm_i915_private *dev_priv = dev->dev_private;
7965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7966 int pipe = intel_crtc->pipe;
7967 uint32_t cntl;
7968
7969 cntl = 0;
7970 if (base) {
7971 cntl = MCURSOR_GAMMA_ENABLE;
7972 switch (intel_crtc->cursor_width) {
7973 case 64:
7974 cntl |= CURSOR_MODE_64_ARGB_AX;
7975 break;
7976 case 128:
7977 cntl |= CURSOR_MODE_128_ARGB_AX;
7978 break;
7979 case 256:
7980 cntl |= CURSOR_MODE_256_ARGB_AX;
7981 break;
7982 default:
7983 WARN_ON(1);
7984 return;
7985 }
7986 cntl |= pipe << 28; /* Connect to correct pipe */
7987 }
7988 if (intel_crtc->cursor_cntl != cntl) {
7989 I915_WRITE(CURCNTR(pipe), cntl);
7990 POSTING_READ(CURCNTR(pipe));
7991 intel_crtc->cursor_cntl = cntl;
7992 }
7993
7994 /* and commit changes on next vblank */
7995 I915_WRITE(CURBASE(pipe), base);
7996 POSTING_READ(CURBASE(pipe));
7997 }
7998
7999 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
8000 {
8001 struct drm_device *dev = crtc->dev;
8002 struct drm_i915_private *dev_priv = dev->dev_private;
8003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8004 int pipe = intel_crtc->pipe;
8005 uint32_t cntl;
8006
8007 cntl = 0;
8008 if (base) {
8009 cntl = MCURSOR_GAMMA_ENABLE;
8010 switch (intel_crtc->cursor_width) {
8011 case 64:
8012 cntl |= CURSOR_MODE_64_ARGB_AX;
8013 break;
8014 case 128:
8015 cntl |= CURSOR_MODE_128_ARGB_AX;
8016 break;
8017 case 256:
8018 cntl |= CURSOR_MODE_256_ARGB_AX;
8019 break;
8020 default:
8021 WARN_ON(1);
8022 return;
8023 }
8024 }
8025 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8026 cntl |= CURSOR_PIPE_CSC_ENABLE;
8027
8028 if (intel_crtc->cursor_cntl != cntl) {
8029 I915_WRITE(CURCNTR(pipe), cntl);
8030 POSTING_READ(CURCNTR(pipe));
8031 intel_crtc->cursor_cntl = cntl;
8032 }
8033
8034 /* and commit changes on next vblank */
8035 I915_WRITE(CURBASE(pipe), base);
8036 POSTING_READ(CURBASE(pipe));
8037 }
8038
8039 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8040 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8041 bool on)
8042 {
8043 struct drm_device *dev = crtc->dev;
8044 struct drm_i915_private *dev_priv = dev->dev_private;
8045 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8046 int pipe = intel_crtc->pipe;
8047 int x = crtc->cursor_x;
8048 int y = crtc->cursor_y;
8049 u32 base = 0, pos = 0;
8050
8051 if (on)
8052 base = intel_crtc->cursor_addr;
8053
8054 if (x >= intel_crtc->config.pipe_src_w)
8055 base = 0;
8056
8057 if (y >= intel_crtc->config.pipe_src_h)
8058 base = 0;
8059
8060 if (x < 0) {
8061 if (x + intel_crtc->cursor_width <= 0)
8062 base = 0;
8063
8064 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8065 x = -x;
8066 }
8067 pos |= x << CURSOR_X_SHIFT;
8068
8069 if (y < 0) {
8070 if (y + intel_crtc->cursor_height <= 0)
8071 base = 0;
8072
8073 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8074 y = -y;
8075 }
8076 pos |= y << CURSOR_Y_SHIFT;
8077
8078 if (base == 0 && intel_crtc->cursor_base == 0)
8079 return;
8080
8081 I915_WRITE(CURPOS(pipe), pos);
8082
8083 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
8084 ivb_update_cursor(crtc, base);
8085 else if (IS_845G(dev) || IS_I865G(dev))
8086 i845_update_cursor(crtc, base);
8087 else
8088 i9xx_update_cursor(crtc, base);
8089 intel_crtc->cursor_base = base;
8090 }
8091
8092 /*
8093 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8094 *
8095 * Note that the object's reference will be consumed if the update fails. If
8096 * the update succeeds, the reference of the old object (if any) will be
8097 * consumed.
8098 */
8099 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8100 struct drm_i915_gem_object *obj,
8101 uint32_t width, uint32_t height)
8102 {
8103 struct drm_device *dev = crtc->dev;
8104 struct drm_i915_private *dev_priv = dev->dev_private;
8105 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8106 unsigned old_width;
8107 uint32_t addr;
8108 int ret;
8109
8110 /* if we want to turn off the cursor ignore width and height */
8111 if (!obj) {
8112 DRM_DEBUG_KMS("cursor off\n");
8113 addr = 0;
8114 obj = NULL;
8115 mutex_lock(&dev->struct_mutex);
8116 goto finish;
8117 }
8118
8119 /* Check for which cursor types we support */
8120 if (!((width == 64 && height == 64) ||
8121 (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8122 (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8123 DRM_DEBUG("Cursor dimension not supported\n");
8124 return -EINVAL;
8125 }
8126
8127 if (obj->base.size < width * height * 4) {
8128 DRM_DEBUG_KMS("buffer is too small\n");
8129 ret = -ENOMEM;
8130 goto fail;
8131 }
8132
8133 /* we only need to pin inside GTT if cursor is non-phy */
8134 mutex_lock(&dev->struct_mutex);
8135 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8136 unsigned alignment;
8137
8138 if (obj->tiling_mode) {
8139 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8140 ret = -EINVAL;
8141 goto fail_locked;
8142 }
8143
8144 /* Note that the w/a also requires 2 PTE of padding following
8145 * the bo. We currently fill all unused PTE with the shadow
8146 * page and so we should always have valid PTE following the
8147 * cursor preventing the VT-d warning.
8148 */
8149 alignment = 0;
8150 if (need_vtd_wa(dev))
8151 alignment = 64*1024;
8152
8153 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8154 if (ret) {
8155 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8156 goto fail_locked;
8157 }
8158
8159 ret = i915_gem_object_put_fence(obj);
8160 if (ret) {
8161 DRM_DEBUG_KMS("failed to release fence for cursor");
8162 goto fail_unpin;
8163 }
8164
8165 addr = i915_gem_obj_ggtt_offset(obj);
8166 } else {
8167 int align = IS_I830(dev) ? 16 * 1024 : 256;
8168 ret = i915_gem_object_attach_phys(obj, align);
8169 if (ret) {
8170 DRM_DEBUG_KMS("failed to attach phys object\n");
8171 goto fail_locked;
8172 }
8173 addr = obj->phys_handle->busaddr;
8174 }
8175
8176 if (IS_GEN2(dev))
8177 I915_WRITE(CURSIZE, (height << 12) | width);
8178
8179 finish:
8180 if (intel_crtc->cursor_bo) {
8181 if (!INTEL_INFO(dev)->cursor_needs_physical)
8182 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8183 }
8184
8185 mutex_unlock(&dev->struct_mutex);
8186
8187 old_width = intel_crtc->cursor_width;
8188
8189 intel_crtc->cursor_addr = addr;
8190 intel_crtc->cursor_bo = obj;
8191 intel_crtc->cursor_width = width;
8192 intel_crtc->cursor_height = height;
8193
8194 if (intel_crtc->active) {
8195 if (old_width != width)
8196 intel_update_watermarks(crtc);
8197 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8198 }
8199
8200 return 0;
8201 fail_unpin:
8202 i915_gem_object_unpin_from_display_plane(obj);
8203 fail_locked:
8204 mutex_unlock(&dev->struct_mutex);
8205 fail:
8206 drm_gem_object_unreference_unlocked(&obj->base);
8207 return ret;
8208 }
8209
8210 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8211 u16 *blue, uint32_t start, uint32_t size)
8212 {
8213 int end = (start + size > 256) ? 256 : start + size, i;
8214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8215
8216 for (i = start; i < end; i++) {
8217 intel_crtc->lut_r[i] = red[i] >> 8;
8218 intel_crtc->lut_g[i] = green[i] >> 8;
8219 intel_crtc->lut_b[i] = blue[i] >> 8;
8220 }
8221
8222 intel_crtc_load_lut(crtc);
8223 }
8224
8225 /* VESA 640x480x72Hz mode to set on the pipe */
8226 static struct drm_display_mode load_detect_mode = {
8227 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8228 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8229 };
8230
8231 struct drm_framebuffer *
8232 __intel_framebuffer_create(struct drm_device *dev,
8233 struct drm_mode_fb_cmd2 *mode_cmd,
8234 struct drm_i915_gem_object *obj)
8235 {
8236 struct intel_framebuffer *intel_fb;
8237 int ret;
8238
8239 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8240 if (!intel_fb) {
8241 drm_gem_object_unreference_unlocked(&obj->base);
8242 return ERR_PTR(-ENOMEM);
8243 }
8244
8245 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8246 if (ret)
8247 goto err;
8248
8249 return &intel_fb->base;
8250 err:
8251 drm_gem_object_unreference_unlocked(&obj->base);
8252 kfree(intel_fb);
8253
8254 return ERR_PTR(ret);
8255 }
8256
8257 static struct drm_framebuffer *
8258 intel_framebuffer_create(struct drm_device *dev,
8259 struct drm_mode_fb_cmd2 *mode_cmd,
8260 struct drm_i915_gem_object *obj)
8261 {
8262 struct drm_framebuffer *fb;
8263 int ret;
8264
8265 ret = i915_mutex_lock_interruptible(dev);
8266 if (ret)
8267 return ERR_PTR(ret);
8268 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8269 mutex_unlock(&dev->struct_mutex);
8270
8271 return fb;
8272 }
8273
8274 static u32
8275 intel_framebuffer_pitch_for_width(int width, int bpp)
8276 {
8277 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8278 return ALIGN(pitch, 64);
8279 }
8280
8281 static u32
8282 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8283 {
8284 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8285 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
8286 }
8287
8288 static struct drm_framebuffer *
8289 intel_framebuffer_create_for_mode(struct drm_device *dev,
8290 struct drm_display_mode *mode,
8291 int depth, int bpp)
8292 {
8293 struct drm_i915_gem_object *obj;
8294 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8295
8296 obj = i915_gem_alloc_object(dev,
8297 intel_framebuffer_size_for_mode(mode, bpp));
8298 if (obj == NULL)
8299 return ERR_PTR(-ENOMEM);
8300
8301 mode_cmd.width = mode->hdisplay;
8302 mode_cmd.height = mode->vdisplay;
8303 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8304 bpp);
8305 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8306
8307 return intel_framebuffer_create(dev, &mode_cmd, obj);
8308 }
8309
8310 static struct drm_framebuffer *
8311 mode_fits_in_fbdev(struct drm_device *dev,
8312 struct drm_display_mode *mode)
8313 {
8314 #ifdef CONFIG_DRM_I915_FBDEV
8315 struct drm_i915_private *dev_priv = dev->dev_private;
8316 struct drm_i915_gem_object *obj;
8317 struct drm_framebuffer *fb;
8318
8319 if (!dev_priv->fbdev)
8320 return NULL;
8321
8322 if (!dev_priv->fbdev->fb)
8323 return NULL;
8324
8325 obj = dev_priv->fbdev->fb->obj;
8326 BUG_ON(!obj);
8327
8328 fb = &dev_priv->fbdev->fb->base;
8329 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8330 fb->bits_per_pixel))
8331 return NULL;
8332
8333 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8334 return NULL;
8335
8336 return fb;
8337 #else
8338 return NULL;
8339 #endif
8340 }
8341
8342 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8343 struct drm_display_mode *mode,
8344 struct intel_load_detect_pipe *old,
8345 struct drm_modeset_acquire_ctx *ctx)
8346 {
8347 struct intel_crtc *intel_crtc;
8348 struct intel_encoder *intel_encoder =
8349 intel_attached_encoder(connector);
8350 struct drm_crtc *possible_crtc;
8351 struct drm_encoder *encoder = &intel_encoder->base;
8352 struct drm_crtc *crtc = NULL;
8353 struct drm_device *dev = encoder->dev;
8354 struct drm_framebuffer *fb;
8355 struct drm_mode_config *config = &dev->mode_config;
8356 int ret, i = -1;
8357
8358 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8359 connector->base.id, connector->name,
8360 encoder->base.id, encoder->name);
8361
8362 drm_modeset_acquire_init(ctx, 0);
8363
8364 retry:
8365 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8366 if (ret)
8367 goto fail_unlock;
8368
8369 /*
8370 * Algorithm gets a little messy:
8371 *
8372 * - if the connector already has an assigned crtc, use it (but make
8373 * sure it's on first)
8374 *
8375 * - try to find the first unused crtc that can drive this connector,
8376 * and use that if we find one
8377 */
8378
8379 /* See if we already have a CRTC for this connector */
8380 if (encoder->crtc) {
8381 crtc = encoder->crtc;
8382
8383 ret = drm_modeset_lock(&crtc->mutex, ctx);
8384 if (ret)
8385 goto fail_unlock;
8386
8387 old->dpms_mode = connector->dpms;
8388 old->load_detect_temp = false;
8389
8390 /* Make sure the crtc and connector are running */
8391 if (connector->dpms != DRM_MODE_DPMS_ON)
8392 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8393
8394 return true;
8395 }
8396
8397 /* Find an unused one (if possible) */
8398 for_each_crtc(dev, possible_crtc) {
8399 i++;
8400 if (!(encoder->possible_crtcs & (1 << i)))
8401 continue;
8402 if (!possible_crtc->enabled) {
8403 crtc = possible_crtc;
8404 break;
8405 }
8406 }
8407
8408 /*
8409 * If we didn't find an unused CRTC, don't use any.
8410 */
8411 if (!crtc) {
8412 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8413 goto fail_unlock;
8414 }
8415
8416 ret = drm_modeset_lock(&crtc->mutex, ctx);
8417 if (ret)
8418 goto fail_unlock;
8419 intel_encoder->new_crtc = to_intel_crtc(crtc);
8420 to_intel_connector(connector)->new_encoder = intel_encoder;
8421
8422 intel_crtc = to_intel_crtc(crtc);
8423 intel_crtc->new_enabled = true;
8424 intel_crtc->new_config = &intel_crtc->config;
8425 old->dpms_mode = connector->dpms;
8426 old->load_detect_temp = true;
8427 old->release_fb = NULL;
8428
8429 if (!mode)
8430 mode = &load_detect_mode;
8431
8432 /* We need a framebuffer large enough to accommodate all accesses
8433 * that the plane may generate whilst we perform load detection.
8434 * We can not rely on the fbcon either being present (we get called
8435 * during its initialisation to detect all boot displays, or it may
8436 * not even exist) or that it is large enough to satisfy the
8437 * requested mode.
8438 */
8439 fb = mode_fits_in_fbdev(dev, mode);
8440 if (fb == NULL) {
8441 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8442 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8443 old->release_fb = fb;
8444 } else
8445 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8446 if (IS_ERR(fb)) {
8447 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8448 goto fail;
8449 }
8450
8451 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8452 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8453 if (old->release_fb)
8454 old->release_fb->funcs->destroy(old->release_fb);
8455 goto fail;
8456 }
8457
8458 /* let the connector get through one full cycle before testing */
8459 intel_wait_for_vblank(dev, intel_crtc->pipe);
8460 return true;
8461
8462 fail:
8463 intel_crtc->new_enabled = crtc->enabled;
8464 if (intel_crtc->new_enabled)
8465 intel_crtc->new_config = &intel_crtc->config;
8466 else
8467 intel_crtc->new_config = NULL;
8468 fail_unlock:
8469 if (ret == -EDEADLK) {
8470 drm_modeset_backoff(ctx);
8471 goto retry;
8472 }
8473
8474 drm_modeset_drop_locks(ctx);
8475 drm_modeset_acquire_fini(ctx);
8476
8477 return false;
8478 }
8479
8480 void intel_release_load_detect_pipe(struct drm_connector *connector,
8481 struct intel_load_detect_pipe *old,
8482 struct drm_modeset_acquire_ctx *ctx)
8483 {
8484 struct intel_encoder *intel_encoder =
8485 intel_attached_encoder(connector);
8486 struct drm_encoder *encoder = &intel_encoder->base;
8487 struct drm_crtc *crtc = encoder->crtc;
8488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8489
8490 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8491 connector->base.id, connector->name,
8492 encoder->base.id, encoder->name);
8493
8494 if (old->load_detect_temp) {
8495 to_intel_connector(connector)->new_encoder = NULL;
8496 intel_encoder->new_crtc = NULL;
8497 intel_crtc->new_enabled = false;
8498 intel_crtc->new_config = NULL;
8499 intel_set_mode(crtc, NULL, 0, 0, NULL);
8500
8501 if (old->release_fb) {
8502 drm_framebuffer_unregister_private(old->release_fb);
8503 drm_framebuffer_unreference(old->release_fb);
8504 }
8505
8506 goto unlock;
8507 return;
8508 }
8509
8510 /* Switch crtc and encoder back off if necessary */
8511 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8512 connector->funcs->dpms(connector, old->dpms_mode);
8513
8514 unlock:
8515 drm_modeset_drop_locks(ctx);
8516 drm_modeset_acquire_fini(ctx);
8517 }
8518
8519 static int i9xx_pll_refclk(struct drm_device *dev,
8520 const struct intel_crtc_config *pipe_config)
8521 {
8522 struct drm_i915_private *dev_priv = dev->dev_private;
8523 u32 dpll = pipe_config->dpll_hw_state.dpll;
8524
8525 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8526 return dev_priv->vbt.lvds_ssc_freq;
8527 else if (HAS_PCH_SPLIT(dev))
8528 return 120000;
8529 else if (!IS_GEN2(dev))
8530 return 96000;
8531 else
8532 return 48000;
8533 }
8534
8535 /* Returns the clock of the currently programmed mode of the given pipe. */
8536 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8537 struct intel_crtc_config *pipe_config)
8538 {
8539 struct drm_device *dev = crtc->base.dev;
8540 struct drm_i915_private *dev_priv = dev->dev_private;
8541 int pipe = pipe_config->cpu_transcoder;
8542 u32 dpll = pipe_config->dpll_hw_state.dpll;
8543 u32 fp;
8544 intel_clock_t clock;
8545 int refclk = i9xx_pll_refclk(dev, pipe_config);
8546
8547 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8548 fp = pipe_config->dpll_hw_state.fp0;
8549 else
8550 fp = pipe_config->dpll_hw_state.fp1;
8551
8552 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8553 if (IS_PINEVIEW(dev)) {
8554 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8555 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8556 } else {
8557 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8558 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8559 }
8560
8561 if (!IS_GEN2(dev)) {
8562 if (IS_PINEVIEW(dev))
8563 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8564 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8565 else
8566 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8567 DPLL_FPA01_P1_POST_DIV_SHIFT);
8568
8569 switch (dpll & DPLL_MODE_MASK) {
8570 case DPLLB_MODE_DAC_SERIAL:
8571 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8572 5 : 10;
8573 break;
8574 case DPLLB_MODE_LVDS:
8575 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8576 7 : 14;
8577 break;
8578 default:
8579 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8580 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8581 return;
8582 }
8583
8584 if (IS_PINEVIEW(dev))
8585 pineview_clock(refclk, &clock);
8586 else
8587 i9xx_clock(refclk, &clock);
8588 } else {
8589 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8590 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8591
8592 if (is_lvds) {
8593 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8594 DPLL_FPA01_P1_POST_DIV_SHIFT);
8595
8596 if (lvds & LVDS_CLKB_POWER_UP)
8597 clock.p2 = 7;
8598 else
8599 clock.p2 = 14;
8600 } else {
8601 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8602 clock.p1 = 2;
8603 else {
8604 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8605 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8606 }
8607 if (dpll & PLL_P2_DIVIDE_BY_4)
8608 clock.p2 = 4;
8609 else
8610 clock.p2 = 2;
8611 }
8612
8613 i9xx_clock(refclk, &clock);
8614 }
8615
8616 /*
8617 * This value includes pixel_multiplier. We will use
8618 * port_clock to compute adjusted_mode.crtc_clock in the
8619 * encoder's get_config() function.
8620 */
8621 pipe_config->port_clock = clock.dot;
8622 }
8623
8624 int intel_dotclock_calculate(int link_freq,
8625 const struct intel_link_m_n *m_n)
8626 {
8627 /*
8628 * The calculation for the data clock is:
8629 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8630 * But we want to avoid losing precison if possible, so:
8631 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8632 *
8633 * and the link clock is simpler:
8634 * link_clock = (m * link_clock) / n
8635 */
8636
8637 if (!m_n->link_n)
8638 return 0;
8639
8640 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8641 }
8642
8643 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8644 struct intel_crtc_config *pipe_config)
8645 {
8646 struct drm_device *dev = crtc->base.dev;
8647
8648 /* read out port_clock from the DPLL */
8649 i9xx_crtc_clock_get(crtc, pipe_config);
8650
8651 /*
8652 * This value does not include pixel_multiplier.
8653 * We will check that port_clock and adjusted_mode.crtc_clock
8654 * agree once we know their relationship in the encoder's
8655 * get_config() function.
8656 */
8657 pipe_config->adjusted_mode.crtc_clock =
8658 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8659 &pipe_config->fdi_m_n);
8660 }
8661
8662 /** Returns the currently programmed mode of the given pipe. */
8663 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8664 struct drm_crtc *crtc)
8665 {
8666 struct drm_i915_private *dev_priv = dev->dev_private;
8667 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8668 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8669 struct drm_display_mode *mode;
8670 struct intel_crtc_config pipe_config;
8671 int htot = I915_READ(HTOTAL(cpu_transcoder));
8672 int hsync = I915_READ(HSYNC(cpu_transcoder));
8673 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8674 int vsync = I915_READ(VSYNC(cpu_transcoder));
8675 enum pipe pipe = intel_crtc->pipe;
8676
8677 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8678 if (!mode)
8679 return NULL;
8680
8681 /*
8682 * Construct a pipe_config sufficient for getting the clock info
8683 * back out of crtc_clock_get.
8684 *
8685 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8686 * to use a real value here instead.
8687 */
8688 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8689 pipe_config.pixel_multiplier = 1;
8690 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8691 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8692 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8693 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8694
8695 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8696 mode->hdisplay = (htot & 0xffff) + 1;
8697 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8698 mode->hsync_start = (hsync & 0xffff) + 1;
8699 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8700 mode->vdisplay = (vtot & 0xffff) + 1;
8701 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8702 mode->vsync_start = (vsync & 0xffff) + 1;
8703 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8704
8705 drm_mode_set_name(mode);
8706
8707 return mode;
8708 }
8709
8710 static void intel_increase_pllclock(struct drm_crtc *crtc)
8711 {
8712 struct drm_device *dev = crtc->dev;
8713 struct drm_i915_private *dev_priv = dev->dev_private;
8714 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8715 int pipe = intel_crtc->pipe;
8716 int dpll_reg = DPLL(pipe);
8717 int dpll;
8718
8719 if (HAS_PCH_SPLIT(dev))
8720 return;
8721
8722 if (!dev_priv->lvds_downclock_avail)
8723 return;
8724
8725 dpll = I915_READ(dpll_reg);
8726 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8727 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8728
8729 assert_panel_unlocked(dev_priv, pipe);
8730
8731 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8732 I915_WRITE(dpll_reg, dpll);
8733 intel_wait_for_vblank(dev, pipe);
8734
8735 dpll = I915_READ(dpll_reg);
8736 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8737 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8738 }
8739 }
8740
8741 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8742 {
8743 struct drm_device *dev = crtc->dev;
8744 struct drm_i915_private *dev_priv = dev->dev_private;
8745 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8746
8747 if (HAS_PCH_SPLIT(dev))
8748 return;
8749
8750 if (!dev_priv->lvds_downclock_avail)
8751 return;
8752
8753 /*
8754 * Since this is called by a timer, we should never get here in
8755 * the manual case.
8756 */
8757 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8758 int pipe = intel_crtc->pipe;
8759 int dpll_reg = DPLL(pipe);
8760 int dpll;
8761
8762 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8763
8764 assert_panel_unlocked(dev_priv, pipe);
8765
8766 dpll = I915_READ(dpll_reg);
8767 dpll |= DISPLAY_RATE_SELECT_FPA1;
8768 I915_WRITE(dpll_reg, dpll);
8769 intel_wait_for_vblank(dev, pipe);
8770 dpll = I915_READ(dpll_reg);
8771 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8772 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8773 }
8774
8775 }
8776
8777 void intel_mark_busy(struct drm_device *dev)
8778 {
8779 struct drm_i915_private *dev_priv = dev->dev_private;
8780
8781 if (dev_priv->mm.busy)
8782 return;
8783
8784 intel_runtime_pm_get(dev_priv);
8785 i915_update_gfx_val(dev_priv);
8786 dev_priv->mm.busy = true;
8787 }
8788
8789 void intel_mark_idle(struct drm_device *dev)
8790 {
8791 struct drm_i915_private *dev_priv = dev->dev_private;
8792 struct drm_crtc *crtc;
8793
8794 if (!dev_priv->mm.busy)
8795 return;
8796
8797 dev_priv->mm.busy = false;
8798
8799 if (!i915.powersave)
8800 goto out;
8801
8802 for_each_crtc(dev, crtc) {
8803 if (!crtc->primary->fb)
8804 continue;
8805
8806 intel_decrease_pllclock(crtc);
8807 }
8808
8809 if (INTEL_INFO(dev)->gen >= 6)
8810 gen6_rps_idle(dev->dev_private);
8811
8812 out:
8813 intel_runtime_pm_put(dev_priv);
8814 }
8815
8816
8817 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8818 struct intel_engine_cs *ring)
8819 {
8820 struct drm_device *dev = obj->base.dev;
8821 struct drm_crtc *crtc;
8822
8823 intel_edp_psr_exit(dev);
8824
8825 if (!i915.powersave)
8826 return;
8827
8828 for_each_crtc(dev, crtc) {
8829 if (!crtc->primary->fb)
8830 continue;
8831
8832 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
8833 continue;
8834
8835 intel_increase_pllclock(crtc);
8836 if (ring && intel_fbc_enabled(dev))
8837 ring->fbc_dirty = true;
8838 }
8839 }
8840
8841 static void intel_crtc_destroy(struct drm_crtc *crtc)
8842 {
8843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8844 struct drm_device *dev = crtc->dev;
8845 struct intel_unpin_work *work;
8846 unsigned long flags;
8847
8848 spin_lock_irqsave(&dev->event_lock, flags);
8849 work = intel_crtc->unpin_work;
8850 intel_crtc->unpin_work = NULL;
8851 spin_unlock_irqrestore(&dev->event_lock, flags);
8852
8853 if (work) {
8854 cancel_work_sync(&work->work);
8855 kfree(work);
8856 }
8857
8858 drm_crtc_cleanup(crtc);
8859
8860 kfree(intel_crtc);
8861 }
8862
8863 static void intel_unpin_work_fn(struct work_struct *__work)
8864 {
8865 struct intel_unpin_work *work =
8866 container_of(__work, struct intel_unpin_work, work);
8867 struct drm_device *dev = work->crtc->dev;
8868
8869 mutex_lock(&dev->struct_mutex);
8870 intel_unpin_fb_obj(work->old_fb_obj);
8871 drm_gem_object_unreference(&work->pending_flip_obj->base);
8872 drm_gem_object_unreference(&work->old_fb_obj->base);
8873
8874 intel_update_fbc(dev);
8875 mutex_unlock(&dev->struct_mutex);
8876
8877 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8878 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8879
8880 kfree(work);
8881 }
8882
8883 static void do_intel_finish_page_flip(struct drm_device *dev,
8884 struct drm_crtc *crtc)
8885 {
8886 struct drm_i915_private *dev_priv = dev->dev_private;
8887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8888 struct intel_unpin_work *work;
8889 unsigned long flags;
8890
8891 /* Ignore early vblank irqs */
8892 if (intel_crtc == NULL)
8893 return;
8894
8895 spin_lock_irqsave(&dev->event_lock, flags);
8896 work = intel_crtc->unpin_work;
8897
8898 /* Ensure we don't miss a work->pending update ... */
8899 smp_rmb();
8900
8901 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8902 spin_unlock_irqrestore(&dev->event_lock, flags);
8903 return;
8904 }
8905
8906 /* and that the unpin work is consistent wrt ->pending. */
8907 smp_rmb();
8908
8909 intel_crtc->unpin_work = NULL;
8910
8911 if (work->event)
8912 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8913
8914 drm_crtc_vblank_put(crtc);
8915
8916 spin_unlock_irqrestore(&dev->event_lock, flags);
8917
8918 wake_up_all(&dev_priv->pending_flip_queue);
8919
8920 queue_work(dev_priv->wq, &work->work);
8921
8922 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8923 }
8924
8925 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8926 {
8927 struct drm_i915_private *dev_priv = dev->dev_private;
8928 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8929
8930 do_intel_finish_page_flip(dev, crtc);
8931 }
8932
8933 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8934 {
8935 struct drm_i915_private *dev_priv = dev->dev_private;
8936 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8937
8938 do_intel_finish_page_flip(dev, crtc);
8939 }
8940
8941 /* Is 'a' after or equal to 'b'? */
8942 static bool g4x_flip_count_after_eq(u32 a, u32 b)
8943 {
8944 return !((a - b) & 0x80000000);
8945 }
8946
8947 static bool page_flip_finished(struct intel_crtc *crtc)
8948 {
8949 struct drm_device *dev = crtc->base.dev;
8950 struct drm_i915_private *dev_priv = dev->dev_private;
8951
8952 /*
8953 * The relevant registers doen't exist on pre-ctg.
8954 * As the flip done interrupt doesn't trigger for mmio
8955 * flips on gmch platforms, a flip count check isn't
8956 * really needed there. But since ctg has the registers,
8957 * include it in the check anyway.
8958 */
8959 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
8960 return true;
8961
8962 /*
8963 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
8964 * used the same base address. In that case the mmio flip might
8965 * have completed, but the CS hasn't even executed the flip yet.
8966 *
8967 * A flip count check isn't enough as the CS might have updated
8968 * the base address just after start of vblank, but before we
8969 * managed to process the interrupt. This means we'd complete the
8970 * CS flip too soon.
8971 *
8972 * Combining both checks should get us a good enough result. It may
8973 * still happen that the CS flip has been executed, but has not
8974 * yet actually completed. But in case the base address is the same
8975 * anyway, we don't really care.
8976 */
8977 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
8978 crtc->unpin_work->gtt_offset &&
8979 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
8980 crtc->unpin_work->flip_count);
8981 }
8982
8983 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8984 {
8985 struct drm_i915_private *dev_priv = dev->dev_private;
8986 struct intel_crtc *intel_crtc =
8987 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8988 unsigned long flags;
8989
8990 /* NB: An MMIO update of the plane base pointer will also
8991 * generate a page-flip completion irq, i.e. every modeset
8992 * is also accompanied by a spurious intel_prepare_page_flip().
8993 */
8994 spin_lock_irqsave(&dev->event_lock, flags);
8995 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
8996 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8997 spin_unlock_irqrestore(&dev->event_lock, flags);
8998 }
8999
9000 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9001 {
9002 /* Ensure that the work item is consistent when activating it ... */
9003 smp_wmb();
9004 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9005 /* and that it is marked active as soon as the irq could fire. */
9006 smp_wmb();
9007 }
9008
9009 static int intel_gen2_queue_flip(struct drm_device *dev,
9010 struct drm_crtc *crtc,
9011 struct drm_framebuffer *fb,
9012 struct drm_i915_gem_object *obj,
9013 struct intel_engine_cs *ring,
9014 uint32_t flags)
9015 {
9016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9017 u32 flip_mask;
9018 int ret;
9019
9020 ret = intel_ring_begin(ring, 6);
9021 if (ret)
9022 return ret;
9023
9024 /* Can't queue multiple flips, so wait for the previous
9025 * one to finish before executing the next.
9026 */
9027 if (intel_crtc->plane)
9028 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9029 else
9030 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9031 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9032 intel_ring_emit(ring, MI_NOOP);
9033 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9034 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9035 intel_ring_emit(ring, fb->pitches[0]);
9036 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9037 intel_ring_emit(ring, 0); /* aux display base address, unused */
9038
9039 intel_mark_page_flip_active(intel_crtc);
9040 __intel_ring_advance(ring);
9041 return 0;
9042 }
9043
9044 static int intel_gen3_queue_flip(struct drm_device *dev,
9045 struct drm_crtc *crtc,
9046 struct drm_framebuffer *fb,
9047 struct drm_i915_gem_object *obj,
9048 struct intel_engine_cs *ring,
9049 uint32_t flags)
9050 {
9051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9052 u32 flip_mask;
9053 int ret;
9054
9055 ret = intel_ring_begin(ring, 6);
9056 if (ret)
9057 return ret;
9058
9059 if (intel_crtc->plane)
9060 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9061 else
9062 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9063 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9064 intel_ring_emit(ring, MI_NOOP);
9065 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9066 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9067 intel_ring_emit(ring, fb->pitches[0]);
9068 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9069 intel_ring_emit(ring, MI_NOOP);
9070
9071 intel_mark_page_flip_active(intel_crtc);
9072 __intel_ring_advance(ring);
9073 return 0;
9074 }
9075
9076 static int intel_gen4_queue_flip(struct drm_device *dev,
9077 struct drm_crtc *crtc,
9078 struct drm_framebuffer *fb,
9079 struct drm_i915_gem_object *obj,
9080 struct intel_engine_cs *ring,
9081 uint32_t flags)
9082 {
9083 struct drm_i915_private *dev_priv = dev->dev_private;
9084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9085 uint32_t pf, pipesrc;
9086 int ret;
9087
9088 ret = intel_ring_begin(ring, 4);
9089 if (ret)
9090 return ret;
9091
9092 /* i965+ uses the linear or tiled offsets from the
9093 * Display Registers (which do not change across a page-flip)
9094 * so we need only reprogram the base address.
9095 */
9096 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9097 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9098 intel_ring_emit(ring, fb->pitches[0]);
9099 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9100 obj->tiling_mode);
9101
9102 /* XXX Enabling the panel-fitter across page-flip is so far
9103 * untested on non-native modes, so ignore it for now.
9104 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9105 */
9106 pf = 0;
9107 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9108 intel_ring_emit(ring, pf | pipesrc);
9109
9110 intel_mark_page_flip_active(intel_crtc);
9111 __intel_ring_advance(ring);
9112 return 0;
9113 }
9114
9115 static int intel_gen6_queue_flip(struct drm_device *dev,
9116 struct drm_crtc *crtc,
9117 struct drm_framebuffer *fb,
9118 struct drm_i915_gem_object *obj,
9119 struct intel_engine_cs *ring,
9120 uint32_t flags)
9121 {
9122 struct drm_i915_private *dev_priv = dev->dev_private;
9123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9124 uint32_t pf, pipesrc;
9125 int ret;
9126
9127 ret = intel_ring_begin(ring, 4);
9128 if (ret)
9129 return ret;
9130
9131 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9132 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9133 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9134 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9135
9136 /* Contrary to the suggestions in the documentation,
9137 * "Enable Panel Fitter" does not seem to be required when page
9138 * flipping with a non-native mode, and worse causes a normal
9139 * modeset to fail.
9140 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9141 */
9142 pf = 0;
9143 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9144 intel_ring_emit(ring, pf | pipesrc);
9145
9146 intel_mark_page_flip_active(intel_crtc);
9147 __intel_ring_advance(ring);
9148 return 0;
9149 }
9150
9151 static int intel_gen7_queue_flip(struct drm_device *dev,
9152 struct drm_crtc *crtc,
9153 struct drm_framebuffer *fb,
9154 struct drm_i915_gem_object *obj,
9155 struct intel_engine_cs *ring,
9156 uint32_t flags)
9157 {
9158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9159 uint32_t plane_bit = 0;
9160 int len, ret;
9161
9162 switch (intel_crtc->plane) {
9163 case PLANE_A:
9164 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9165 break;
9166 case PLANE_B:
9167 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9168 break;
9169 case PLANE_C:
9170 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9171 break;
9172 default:
9173 WARN_ONCE(1, "unknown plane in flip command\n");
9174 return -ENODEV;
9175 }
9176
9177 len = 4;
9178 if (ring->id == RCS) {
9179 len += 6;
9180 /*
9181 * On Gen 8, SRM is now taking an extra dword to accommodate
9182 * 48bits addresses, and we need a NOOP for the batch size to
9183 * stay even.
9184 */
9185 if (IS_GEN8(dev))
9186 len += 2;
9187 }
9188
9189 /*
9190 * BSpec MI_DISPLAY_FLIP for IVB:
9191 * "The full packet must be contained within the same cache line."
9192 *
9193 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9194 * cacheline, if we ever start emitting more commands before
9195 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9196 * then do the cacheline alignment, and finally emit the
9197 * MI_DISPLAY_FLIP.
9198 */
9199 ret = intel_ring_cacheline_align(ring);
9200 if (ret)
9201 return ret;
9202
9203 ret = intel_ring_begin(ring, len);
9204 if (ret)
9205 return ret;
9206
9207 /* Unmask the flip-done completion message. Note that the bspec says that
9208 * we should do this for both the BCS and RCS, and that we must not unmask
9209 * more than one flip event at any time (or ensure that one flip message
9210 * can be sent by waiting for flip-done prior to queueing new flips).
9211 * Experimentation says that BCS works despite DERRMR masking all
9212 * flip-done completion events and that unmasking all planes at once
9213 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9214 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9215 */
9216 if (ring->id == RCS) {
9217 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9218 intel_ring_emit(ring, DERRMR);
9219 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9220 DERRMR_PIPEB_PRI_FLIP_DONE |
9221 DERRMR_PIPEC_PRI_FLIP_DONE));
9222 if (IS_GEN8(dev))
9223 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9224 MI_SRM_LRM_GLOBAL_GTT);
9225 else
9226 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9227 MI_SRM_LRM_GLOBAL_GTT);
9228 intel_ring_emit(ring, DERRMR);
9229 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9230 if (IS_GEN8(dev)) {
9231 intel_ring_emit(ring, 0);
9232 intel_ring_emit(ring, MI_NOOP);
9233 }
9234 }
9235
9236 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9237 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9238 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9239 intel_ring_emit(ring, (MI_NOOP));
9240
9241 intel_mark_page_flip_active(intel_crtc);
9242 __intel_ring_advance(ring);
9243 return 0;
9244 }
9245
9246 static bool use_mmio_flip(struct intel_engine_cs *ring,
9247 struct drm_i915_gem_object *obj)
9248 {
9249 /*
9250 * This is not being used for older platforms, because
9251 * non-availability of flip done interrupt forces us to use
9252 * CS flips. Older platforms derive flip done using some clever
9253 * tricks involving the flip_pending status bits and vblank irqs.
9254 * So using MMIO flips there would disrupt this mechanism.
9255 */
9256
9257 if (INTEL_INFO(ring->dev)->gen < 5)
9258 return false;
9259
9260 if (i915.use_mmio_flip < 0)
9261 return false;
9262 else if (i915.use_mmio_flip > 0)
9263 return true;
9264 else
9265 return ring != obj->ring;
9266 }
9267
9268 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9269 {
9270 struct drm_device *dev = intel_crtc->base.dev;
9271 struct drm_i915_private *dev_priv = dev->dev_private;
9272 struct intel_framebuffer *intel_fb =
9273 to_intel_framebuffer(intel_crtc->base.primary->fb);
9274 struct drm_i915_gem_object *obj = intel_fb->obj;
9275 u32 dspcntr;
9276 u32 reg;
9277
9278 intel_mark_page_flip_active(intel_crtc);
9279
9280 reg = DSPCNTR(intel_crtc->plane);
9281 dspcntr = I915_READ(reg);
9282
9283 if (INTEL_INFO(dev)->gen >= 4) {
9284 if (obj->tiling_mode != I915_TILING_NONE)
9285 dspcntr |= DISPPLANE_TILED;
9286 else
9287 dspcntr &= ~DISPPLANE_TILED;
9288 }
9289 I915_WRITE(reg, dspcntr);
9290
9291 I915_WRITE(DSPSURF(intel_crtc->plane),
9292 intel_crtc->unpin_work->gtt_offset);
9293 POSTING_READ(DSPSURF(intel_crtc->plane));
9294 }
9295
9296 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9297 {
9298 struct intel_engine_cs *ring;
9299 int ret;
9300
9301 lockdep_assert_held(&obj->base.dev->struct_mutex);
9302
9303 if (!obj->last_write_seqno)
9304 return 0;
9305
9306 ring = obj->ring;
9307
9308 if (i915_seqno_passed(ring->get_seqno(ring, true),
9309 obj->last_write_seqno))
9310 return 0;
9311
9312 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9313 if (ret)
9314 return ret;
9315
9316 if (WARN_ON(!ring->irq_get(ring)))
9317 return 0;
9318
9319 return 1;
9320 }
9321
9322 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9323 {
9324 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9325 struct intel_crtc *intel_crtc;
9326 unsigned long irq_flags;
9327 u32 seqno;
9328
9329 seqno = ring->get_seqno(ring, false);
9330
9331 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9332 for_each_intel_crtc(ring->dev, intel_crtc) {
9333 struct intel_mmio_flip *mmio_flip;
9334
9335 mmio_flip = &intel_crtc->mmio_flip;
9336 if (mmio_flip->seqno == 0)
9337 continue;
9338
9339 if (ring->id != mmio_flip->ring_id)
9340 continue;
9341
9342 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9343 intel_do_mmio_flip(intel_crtc);
9344 mmio_flip->seqno = 0;
9345 ring->irq_put(ring);
9346 }
9347 }
9348 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9349 }
9350
9351 static int intel_queue_mmio_flip(struct drm_device *dev,
9352 struct drm_crtc *crtc,
9353 struct drm_framebuffer *fb,
9354 struct drm_i915_gem_object *obj,
9355 struct intel_engine_cs *ring,
9356 uint32_t flags)
9357 {
9358 struct drm_i915_private *dev_priv = dev->dev_private;
9359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9360 unsigned long irq_flags;
9361 int ret;
9362
9363 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9364 return -EBUSY;
9365
9366 ret = intel_postpone_flip(obj);
9367 if (ret < 0)
9368 return ret;
9369 if (ret == 0) {
9370 intel_do_mmio_flip(intel_crtc);
9371 return 0;
9372 }
9373
9374 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9375 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9376 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9377 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9378
9379 /*
9380 * Double check to catch cases where irq fired before
9381 * mmio flip data was ready
9382 */
9383 intel_notify_mmio_flip(obj->ring);
9384 return 0;
9385 }
9386
9387 static int intel_default_queue_flip(struct drm_device *dev,
9388 struct drm_crtc *crtc,
9389 struct drm_framebuffer *fb,
9390 struct drm_i915_gem_object *obj,
9391 struct intel_engine_cs *ring,
9392 uint32_t flags)
9393 {
9394 return -ENODEV;
9395 }
9396
9397 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9398 struct drm_framebuffer *fb,
9399 struct drm_pending_vblank_event *event,
9400 uint32_t page_flip_flags)
9401 {
9402 struct drm_device *dev = crtc->dev;
9403 struct drm_i915_private *dev_priv = dev->dev_private;
9404 struct drm_framebuffer *old_fb = crtc->primary->fb;
9405 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
9406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9407 struct intel_unpin_work *work;
9408 struct intel_engine_cs *ring;
9409 unsigned long flags;
9410 int ret;
9411
9412 /* Can't change pixel format via MI display flips. */
9413 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9414 return -EINVAL;
9415
9416 /*
9417 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9418 * Note that pitch changes could also affect these register.
9419 */
9420 if (INTEL_INFO(dev)->gen > 3 &&
9421 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9422 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9423 return -EINVAL;
9424
9425 if (i915_terminally_wedged(&dev_priv->gpu_error))
9426 goto out_hang;
9427
9428 work = kzalloc(sizeof(*work), GFP_KERNEL);
9429 if (work == NULL)
9430 return -ENOMEM;
9431
9432 /* Exit PSR early in page flip */
9433 intel_edp_psr_exit(dev);
9434
9435 work->event = event;
9436 work->crtc = crtc;
9437 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
9438 INIT_WORK(&work->work, intel_unpin_work_fn);
9439
9440 ret = drm_crtc_vblank_get(crtc);
9441 if (ret)
9442 goto free_work;
9443
9444 /* We borrow the event spin lock for protecting unpin_work */
9445 spin_lock_irqsave(&dev->event_lock, flags);
9446 if (intel_crtc->unpin_work) {
9447 spin_unlock_irqrestore(&dev->event_lock, flags);
9448 kfree(work);
9449 drm_crtc_vblank_put(crtc);
9450
9451 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9452 return -EBUSY;
9453 }
9454 intel_crtc->unpin_work = work;
9455 spin_unlock_irqrestore(&dev->event_lock, flags);
9456
9457 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9458 flush_workqueue(dev_priv->wq);
9459
9460 ret = i915_mutex_lock_interruptible(dev);
9461 if (ret)
9462 goto cleanup;
9463
9464 /* Reference the objects for the scheduled work. */
9465 drm_gem_object_reference(&work->old_fb_obj->base);
9466 drm_gem_object_reference(&obj->base);
9467
9468 crtc->primary->fb = fb;
9469
9470 work->pending_flip_obj = obj;
9471
9472 work->enable_stall_check = true;
9473
9474 atomic_inc(&intel_crtc->unpin_work_count);
9475 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9476
9477 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9478 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(intel_crtc->pipe)) + 1;
9479
9480 if (IS_VALLEYVIEW(dev)) {
9481 ring = &dev_priv->ring[BCS];
9482 } else if (INTEL_INFO(dev)->gen >= 7) {
9483 ring = obj->ring;
9484 if (ring == NULL || ring->id != RCS)
9485 ring = &dev_priv->ring[BCS];
9486 } else {
9487 ring = &dev_priv->ring[RCS];
9488 }
9489
9490 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9491 if (ret)
9492 goto cleanup_pending;
9493
9494 work->gtt_offset =
9495 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9496
9497 if (use_mmio_flip(ring, obj))
9498 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9499 page_flip_flags);
9500 else
9501 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9502 page_flip_flags);
9503 if (ret)
9504 goto cleanup_unpin;
9505
9506 intel_disable_fbc(dev);
9507 intel_mark_fb_busy(obj, NULL);
9508 mutex_unlock(&dev->struct_mutex);
9509
9510 trace_i915_flip_request(intel_crtc->plane, obj);
9511
9512 return 0;
9513
9514 cleanup_unpin:
9515 intel_unpin_fb_obj(obj);
9516 cleanup_pending:
9517 atomic_dec(&intel_crtc->unpin_work_count);
9518 crtc->primary->fb = old_fb;
9519 drm_gem_object_unreference(&work->old_fb_obj->base);
9520 drm_gem_object_unreference(&obj->base);
9521 mutex_unlock(&dev->struct_mutex);
9522
9523 cleanup:
9524 spin_lock_irqsave(&dev->event_lock, flags);
9525 intel_crtc->unpin_work = NULL;
9526 spin_unlock_irqrestore(&dev->event_lock, flags);
9527
9528 drm_crtc_vblank_put(crtc);
9529 free_work:
9530 kfree(work);
9531
9532 if (ret == -EIO) {
9533 out_hang:
9534 intel_crtc_wait_for_pending_flips(crtc);
9535 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9536 if (ret == 0 && event)
9537 drm_send_vblank_event(dev, intel_crtc->pipe, event);
9538 }
9539 return ret;
9540 }
9541
9542 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9543 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9544 .load_lut = intel_crtc_load_lut,
9545 };
9546
9547 /**
9548 * intel_modeset_update_staged_output_state
9549 *
9550 * Updates the staged output configuration state, e.g. after we've read out the
9551 * current hw state.
9552 */
9553 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9554 {
9555 struct intel_crtc *crtc;
9556 struct intel_encoder *encoder;
9557 struct intel_connector *connector;
9558
9559 list_for_each_entry(connector, &dev->mode_config.connector_list,
9560 base.head) {
9561 connector->new_encoder =
9562 to_intel_encoder(connector->base.encoder);
9563 }
9564
9565 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9566 base.head) {
9567 encoder->new_crtc =
9568 to_intel_crtc(encoder->base.crtc);
9569 }
9570
9571 for_each_intel_crtc(dev, crtc) {
9572 crtc->new_enabled = crtc->base.enabled;
9573
9574 if (crtc->new_enabled)
9575 crtc->new_config = &crtc->config;
9576 else
9577 crtc->new_config = NULL;
9578 }
9579 }
9580
9581 /**
9582 * intel_modeset_commit_output_state
9583 *
9584 * This function copies the stage display pipe configuration to the real one.
9585 */
9586 static void intel_modeset_commit_output_state(struct drm_device *dev)
9587 {
9588 struct intel_crtc *crtc;
9589 struct intel_encoder *encoder;
9590 struct intel_connector *connector;
9591
9592 list_for_each_entry(connector, &dev->mode_config.connector_list,
9593 base.head) {
9594 connector->base.encoder = &connector->new_encoder->base;
9595 }
9596
9597 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9598 base.head) {
9599 encoder->base.crtc = &encoder->new_crtc->base;
9600 }
9601
9602 for_each_intel_crtc(dev, crtc) {
9603 crtc->base.enabled = crtc->new_enabled;
9604 }
9605 }
9606
9607 static void
9608 connected_sink_compute_bpp(struct intel_connector *connector,
9609 struct intel_crtc_config *pipe_config)
9610 {
9611 int bpp = pipe_config->pipe_bpp;
9612
9613 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9614 connector->base.base.id,
9615 connector->base.name);
9616
9617 /* Don't use an invalid EDID bpc value */
9618 if (connector->base.display_info.bpc &&
9619 connector->base.display_info.bpc * 3 < bpp) {
9620 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9621 bpp, connector->base.display_info.bpc*3);
9622 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9623 }
9624
9625 /* Clamp bpp to 8 on screens without EDID 1.4 */
9626 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9627 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9628 bpp);
9629 pipe_config->pipe_bpp = 24;
9630 }
9631 }
9632
9633 static int
9634 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9635 struct drm_framebuffer *fb,
9636 struct intel_crtc_config *pipe_config)
9637 {
9638 struct drm_device *dev = crtc->base.dev;
9639 struct intel_connector *connector;
9640 int bpp;
9641
9642 switch (fb->pixel_format) {
9643 case DRM_FORMAT_C8:
9644 bpp = 8*3; /* since we go through a colormap */
9645 break;
9646 case DRM_FORMAT_XRGB1555:
9647 case DRM_FORMAT_ARGB1555:
9648 /* checked in intel_framebuffer_init already */
9649 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9650 return -EINVAL;
9651 case DRM_FORMAT_RGB565:
9652 bpp = 6*3; /* min is 18bpp */
9653 break;
9654 case DRM_FORMAT_XBGR8888:
9655 case DRM_FORMAT_ABGR8888:
9656 /* checked in intel_framebuffer_init already */
9657 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9658 return -EINVAL;
9659 case DRM_FORMAT_XRGB8888:
9660 case DRM_FORMAT_ARGB8888:
9661 bpp = 8*3;
9662 break;
9663 case DRM_FORMAT_XRGB2101010:
9664 case DRM_FORMAT_ARGB2101010:
9665 case DRM_FORMAT_XBGR2101010:
9666 case DRM_FORMAT_ABGR2101010:
9667 /* checked in intel_framebuffer_init already */
9668 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9669 return -EINVAL;
9670 bpp = 10*3;
9671 break;
9672 /* TODO: gen4+ supports 16 bpc floating point, too. */
9673 default:
9674 DRM_DEBUG_KMS("unsupported depth\n");
9675 return -EINVAL;
9676 }
9677
9678 pipe_config->pipe_bpp = bpp;
9679
9680 /* Clamp display bpp to EDID value */
9681 list_for_each_entry(connector, &dev->mode_config.connector_list,
9682 base.head) {
9683 if (!connector->new_encoder ||
9684 connector->new_encoder->new_crtc != crtc)
9685 continue;
9686
9687 connected_sink_compute_bpp(connector, pipe_config);
9688 }
9689
9690 return bpp;
9691 }
9692
9693 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9694 {
9695 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9696 "type: 0x%x flags: 0x%x\n",
9697 mode->crtc_clock,
9698 mode->crtc_hdisplay, mode->crtc_hsync_start,
9699 mode->crtc_hsync_end, mode->crtc_htotal,
9700 mode->crtc_vdisplay, mode->crtc_vsync_start,
9701 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9702 }
9703
9704 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9705 struct intel_crtc_config *pipe_config,
9706 const char *context)
9707 {
9708 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9709 context, pipe_name(crtc->pipe));
9710
9711 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9712 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9713 pipe_config->pipe_bpp, pipe_config->dither);
9714 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9715 pipe_config->has_pch_encoder,
9716 pipe_config->fdi_lanes,
9717 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9718 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9719 pipe_config->fdi_m_n.tu);
9720 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9721 pipe_config->has_dp_encoder,
9722 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9723 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9724 pipe_config->dp_m_n.tu);
9725 DRM_DEBUG_KMS("requested mode:\n");
9726 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9727 DRM_DEBUG_KMS("adjusted mode:\n");
9728 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9729 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9730 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9731 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9732 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9733 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9734 pipe_config->gmch_pfit.control,
9735 pipe_config->gmch_pfit.pgm_ratios,
9736 pipe_config->gmch_pfit.lvds_border_bits);
9737 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9738 pipe_config->pch_pfit.pos,
9739 pipe_config->pch_pfit.size,
9740 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9741 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9742 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9743 }
9744
9745 static bool encoders_cloneable(const struct intel_encoder *a,
9746 const struct intel_encoder *b)
9747 {
9748 /* masks could be asymmetric, so check both ways */
9749 return a == b || (a->cloneable & (1 << b->type) &&
9750 b->cloneable & (1 << a->type));
9751 }
9752
9753 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9754 struct intel_encoder *encoder)
9755 {
9756 struct drm_device *dev = crtc->base.dev;
9757 struct intel_encoder *source_encoder;
9758
9759 list_for_each_entry(source_encoder,
9760 &dev->mode_config.encoder_list, base.head) {
9761 if (source_encoder->new_crtc != crtc)
9762 continue;
9763
9764 if (!encoders_cloneable(encoder, source_encoder))
9765 return false;
9766 }
9767
9768 return true;
9769 }
9770
9771 static bool check_encoder_cloning(struct intel_crtc *crtc)
9772 {
9773 struct drm_device *dev = crtc->base.dev;
9774 struct intel_encoder *encoder;
9775
9776 list_for_each_entry(encoder,
9777 &dev->mode_config.encoder_list, base.head) {
9778 if (encoder->new_crtc != crtc)
9779 continue;
9780
9781 if (!check_single_encoder_cloning(crtc, encoder))
9782 return false;
9783 }
9784
9785 return true;
9786 }
9787
9788 static struct intel_crtc_config *
9789 intel_modeset_pipe_config(struct drm_crtc *crtc,
9790 struct drm_framebuffer *fb,
9791 struct drm_display_mode *mode)
9792 {
9793 struct drm_device *dev = crtc->dev;
9794 struct intel_encoder *encoder;
9795 struct intel_crtc_config *pipe_config;
9796 int plane_bpp, ret = -EINVAL;
9797 bool retry = true;
9798
9799 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9800 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9801 return ERR_PTR(-EINVAL);
9802 }
9803
9804 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9805 if (!pipe_config)
9806 return ERR_PTR(-ENOMEM);
9807
9808 drm_mode_copy(&pipe_config->adjusted_mode, mode);
9809 drm_mode_copy(&pipe_config->requested_mode, mode);
9810
9811 pipe_config->cpu_transcoder =
9812 (enum transcoder) to_intel_crtc(crtc)->pipe;
9813 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9814
9815 /*
9816 * Sanitize sync polarity flags based on requested ones. If neither
9817 * positive or negative polarity is requested, treat this as meaning
9818 * negative polarity.
9819 */
9820 if (!(pipe_config->adjusted_mode.flags &
9821 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9822 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9823
9824 if (!(pipe_config->adjusted_mode.flags &
9825 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9826 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9827
9828 /* Compute a starting value for pipe_config->pipe_bpp taking the source
9829 * plane pixel format and any sink constraints into account. Returns the
9830 * source plane bpp so that dithering can be selected on mismatches
9831 * after encoders and crtc also have had their say. */
9832 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9833 fb, pipe_config);
9834 if (plane_bpp < 0)
9835 goto fail;
9836
9837 /*
9838 * Determine the real pipe dimensions. Note that stereo modes can
9839 * increase the actual pipe size due to the frame doubling and
9840 * insertion of additional space for blanks between the frame. This
9841 * is stored in the crtc timings. We use the requested mode to do this
9842 * computation to clearly distinguish it from the adjusted mode, which
9843 * can be changed by the connectors in the below retry loop.
9844 */
9845 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9846 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9847 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9848
9849 encoder_retry:
9850 /* Ensure the port clock defaults are reset when retrying. */
9851 pipe_config->port_clock = 0;
9852 pipe_config->pixel_multiplier = 1;
9853
9854 /* Fill in default crtc timings, allow encoders to overwrite them. */
9855 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9856
9857 /* Pass our mode to the connectors and the CRTC to give them a chance to
9858 * adjust it according to limitations or connector properties, and also
9859 * a chance to reject the mode entirely.
9860 */
9861 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9862 base.head) {
9863
9864 if (&encoder->new_crtc->base != crtc)
9865 continue;
9866
9867 if (!(encoder->compute_config(encoder, pipe_config))) {
9868 DRM_DEBUG_KMS("Encoder config failure\n");
9869 goto fail;
9870 }
9871 }
9872
9873 /* Set default port clock if not overwritten by the encoder. Needs to be
9874 * done afterwards in case the encoder adjusts the mode. */
9875 if (!pipe_config->port_clock)
9876 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9877 * pipe_config->pixel_multiplier;
9878
9879 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9880 if (ret < 0) {
9881 DRM_DEBUG_KMS("CRTC fixup failed\n");
9882 goto fail;
9883 }
9884
9885 if (ret == RETRY) {
9886 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9887 ret = -EINVAL;
9888 goto fail;
9889 }
9890
9891 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9892 retry = false;
9893 goto encoder_retry;
9894 }
9895
9896 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9897 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9898 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9899
9900 return pipe_config;
9901 fail:
9902 kfree(pipe_config);
9903 return ERR_PTR(ret);
9904 }
9905
9906 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9907 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9908 static void
9909 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9910 unsigned *prepare_pipes, unsigned *disable_pipes)
9911 {
9912 struct intel_crtc *intel_crtc;
9913 struct drm_device *dev = crtc->dev;
9914 struct intel_encoder *encoder;
9915 struct intel_connector *connector;
9916 struct drm_crtc *tmp_crtc;
9917
9918 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9919
9920 /* Check which crtcs have changed outputs connected to them, these need
9921 * to be part of the prepare_pipes mask. We don't (yet) support global
9922 * modeset across multiple crtcs, so modeset_pipes will only have one
9923 * bit set at most. */
9924 list_for_each_entry(connector, &dev->mode_config.connector_list,
9925 base.head) {
9926 if (connector->base.encoder == &connector->new_encoder->base)
9927 continue;
9928
9929 if (connector->base.encoder) {
9930 tmp_crtc = connector->base.encoder->crtc;
9931
9932 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9933 }
9934
9935 if (connector->new_encoder)
9936 *prepare_pipes |=
9937 1 << connector->new_encoder->new_crtc->pipe;
9938 }
9939
9940 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9941 base.head) {
9942 if (encoder->base.crtc == &encoder->new_crtc->base)
9943 continue;
9944
9945 if (encoder->base.crtc) {
9946 tmp_crtc = encoder->base.crtc;
9947
9948 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9949 }
9950
9951 if (encoder->new_crtc)
9952 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9953 }
9954
9955 /* Check for pipes that will be enabled/disabled ... */
9956 for_each_intel_crtc(dev, intel_crtc) {
9957 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9958 continue;
9959
9960 if (!intel_crtc->new_enabled)
9961 *disable_pipes |= 1 << intel_crtc->pipe;
9962 else
9963 *prepare_pipes |= 1 << intel_crtc->pipe;
9964 }
9965
9966
9967 /* set_mode is also used to update properties on life display pipes. */
9968 intel_crtc = to_intel_crtc(crtc);
9969 if (intel_crtc->new_enabled)
9970 *prepare_pipes |= 1 << intel_crtc->pipe;
9971
9972 /*
9973 * For simplicity do a full modeset on any pipe where the output routing
9974 * changed. We could be more clever, but that would require us to be
9975 * more careful with calling the relevant encoder->mode_set functions.
9976 */
9977 if (*prepare_pipes)
9978 *modeset_pipes = *prepare_pipes;
9979
9980 /* ... and mask these out. */
9981 *modeset_pipes &= ~(*disable_pipes);
9982 *prepare_pipes &= ~(*disable_pipes);
9983
9984 /*
9985 * HACK: We don't (yet) fully support global modesets. intel_set_config
9986 * obies this rule, but the modeset restore mode of
9987 * intel_modeset_setup_hw_state does not.
9988 */
9989 *modeset_pipes &= 1 << intel_crtc->pipe;
9990 *prepare_pipes &= 1 << intel_crtc->pipe;
9991
9992 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9993 *modeset_pipes, *prepare_pipes, *disable_pipes);
9994 }
9995
9996 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9997 {
9998 struct drm_encoder *encoder;
9999 struct drm_device *dev = crtc->dev;
10000
10001 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10002 if (encoder->crtc == crtc)
10003 return true;
10004
10005 return false;
10006 }
10007
10008 static void
10009 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10010 {
10011 struct intel_encoder *intel_encoder;
10012 struct intel_crtc *intel_crtc;
10013 struct drm_connector *connector;
10014
10015 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
10016 base.head) {
10017 if (!intel_encoder->base.crtc)
10018 continue;
10019
10020 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10021
10022 if (prepare_pipes & (1 << intel_crtc->pipe))
10023 intel_encoder->connectors_active = false;
10024 }
10025
10026 intel_modeset_commit_output_state(dev);
10027
10028 /* Double check state. */
10029 for_each_intel_crtc(dev, intel_crtc) {
10030 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10031 WARN_ON(intel_crtc->new_config &&
10032 intel_crtc->new_config != &intel_crtc->config);
10033 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10034 }
10035
10036 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10037 if (!connector->encoder || !connector->encoder->crtc)
10038 continue;
10039
10040 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10041
10042 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10043 struct drm_property *dpms_property =
10044 dev->mode_config.dpms_property;
10045
10046 connector->dpms = DRM_MODE_DPMS_ON;
10047 drm_object_property_set_value(&connector->base,
10048 dpms_property,
10049 DRM_MODE_DPMS_ON);
10050
10051 intel_encoder = to_intel_encoder(connector->encoder);
10052 intel_encoder->connectors_active = true;
10053 }
10054 }
10055
10056 }
10057
10058 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10059 {
10060 int diff;
10061
10062 if (clock1 == clock2)
10063 return true;
10064
10065 if (!clock1 || !clock2)
10066 return false;
10067
10068 diff = abs(clock1 - clock2);
10069
10070 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10071 return true;
10072
10073 return false;
10074 }
10075
10076 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10077 list_for_each_entry((intel_crtc), \
10078 &(dev)->mode_config.crtc_list, \
10079 base.head) \
10080 if (mask & (1 <<(intel_crtc)->pipe))
10081
10082 static bool
10083 intel_pipe_config_compare(struct drm_device *dev,
10084 struct intel_crtc_config *current_config,
10085 struct intel_crtc_config *pipe_config)
10086 {
10087 #define PIPE_CONF_CHECK_X(name) \
10088 if (current_config->name != pipe_config->name) { \
10089 DRM_ERROR("mismatch in " #name " " \
10090 "(expected 0x%08x, found 0x%08x)\n", \
10091 current_config->name, \
10092 pipe_config->name); \
10093 return false; \
10094 }
10095
10096 #define PIPE_CONF_CHECK_I(name) \
10097 if (current_config->name != pipe_config->name) { \
10098 DRM_ERROR("mismatch in " #name " " \
10099 "(expected %i, found %i)\n", \
10100 current_config->name, \
10101 pipe_config->name); \
10102 return false; \
10103 }
10104
10105 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10106 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10107 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10108 "(expected %i, found %i)\n", \
10109 current_config->name & (mask), \
10110 pipe_config->name & (mask)); \
10111 return false; \
10112 }
10113
10114 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10115 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10116 DRM_ERROR("mismatch in " #name " " \
10117 "(expected %i, found %i)\n", \
10118 current_config->name, \
10119 pipe_config->name); \
10120 return false; \
10121 }
10122
10123 #define PIPE_CONF_QUIRK(quirk) \
10124 ((current_config->quirks | pipe_config->quirks) & (quirk))
10125
10126 PIPE_CONF_CHECK_I(cpu_transcoder);
10127
10128 PIPE_CONF_CHECK_I(has_pch_encoder);
10129 PIPE_CONF_CHECK_I(fdi_lanes);
10130 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10131 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10132 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10133 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10134 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10135
10136 PIPE_CONF_CHECK_I(has_dp_encoder);
10137 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10138 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10139 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10140 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10141 PIPE_CONF_CHECK_I(dp_m_n.tu);
10142
10143 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10144 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10145 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10146 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10147 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10148 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10149
10150 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10151 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10152 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10153 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10154 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10155 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10156
10157 PIPE_CONF_CHECK_I(pixel_multiplier);
10158 PIPE_CONF_CHECK_I(has_hdmi_sink);
10159 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10160 IS_VALLEYVIEW(dev))
10161 PIPE_CONF_CHECK_I(limited_color_range);
10162
10163 PIPE_CONF_CHECK_I(has_audio);
10164
10165 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10166 DRM_MODE_FLAG_INTERLACE);
10167
10168 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10169 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10170 DRM_MODE_FLAG_PHSYNC);
10171 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10172 DRM_MODE_FLAG_NHSYNC);
10173 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10174 DRM_MODE_FLAG_PVSYNC);
10175 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10176 DRM_MODE_FLAG_NVSYNC);
10177 }
10178
10179 PIPE_CONF_CHECK_I(pipe_src_w);
10180 PIPE_CONF_CHECK_I(pipe_src_h);
10181
10182 /*
10183 * FIXME: BIOS likes to set up a cloned config with lvds+external
10184 * screen. Since we don't yet re-compute the pipe config when moving
10185 * just the lvds port away to another pipe the sw tracking won't match.
10186 *
10187 * Proper atomic modesets with recomputed global state will fix this.
10188 * Until then just don't check gmch state for inherited modes.
10189 */
10190 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10191 PIPE_CONF_CHECK_I(gmch_pfit.control);
10192 /* pfit ratios are autocomputed by the hw on gen4+ */
10193 if (INTEL_INFO(dev)->gen < 4)
10194 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10195 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10196 }
10197
10198 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10199 if (current_config->pch_pfit.enabled) {
10200 PIPE_CONF_CHECK_I(pch_pfit.pos);
10201 PIPE_CONF_CHECK_I(pch_pfit.size);
10202 }
10203
10204 /* BDW+ don't expose a synchronous way to read the state */
10205 if (IS_HASWELL(dev))
10206 PIPE_CONF_CHECK_I(ips_enabled);
10207
10208 PIPE_CONF_CHECK_I(double_wide);
10209
10210 PIPE_CONF_CHECK_I(shared_dpll);
10211 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10212 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10213 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10214 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10215
10216 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10217 PIPE_CONF_CHECK_I(pipe_bpp);
10218
10219 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10220 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10221
10222 #undef PIPE_CONF_CHECK_X
10223 #undef PIPE_CONF_CHECK_I
10224 #undef PIPE_CONF_CHECK_FLAGS
10225 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10226 #undef PIPE_CONF_QUIRK
10227
10228 return true;
10229 }
10230
10231 static void
10232 check_connector_state(struct drm_device *dev)
10233 {
10234 struct intel_connector *connector;
10235
10236 list_for_each_entry(connector, &dev->mode_config.connector_list,
10237 base.head) {
10238 /* This also checks the encoder/connector hw state with the
10239 * ->get_hw_state callbacks. */
10240 intel_connector_check_state(connector);
10241
10242 WARN(&connector->new_encoder->base != connector->base.encoder,
10243 "connector's staged encoder doesn't match current encoder\n");
10244 }
10245 }
10246
10247 static void
10248 check_encoder_state(struct drm_device *dev)
10249 {
10250 struct intel_encoder *encoder;
10251 struct intel_connector *connector;
10252
10253 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10254 base.head) {
10255 bool enabled = false;
10256 bool active = false;
10257 enum pipe pipe, tracked_pipe;
10258
10259 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10260 encoder->base.base.id,
10261 encoder->base.name);
10262
10263 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10264 "encoder's stage crtc doesn't match current crtc\n");
10265 WARN(encoder->connectors_active && !encoder->base.crtc,
10266 "encoder's active_connectors set, but no crtc\n");
10267
10268 list_for_each_entry(connector, &dev->mode_config.connector_list,
10269 base.head) {
10270 if (connector->base.encoder != &encoder->base)
10271 continue;
10272 enabled = true;
10273 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10274 active = true;
10275 }
10276 WARN(!!encoder->base.crtc != enabled,
10277 "encoder's enabled state mismatch "
10278 "(expected %i, found %i)\n",
10279 !!encoder->base.crtc, enabled);
10280 WARN(active && !encoder->base.crtc,
10281 "active encoder with no crtc\n");
10282
10283 WARN(encoder->connectors_active != active,
10284 "encoder's computed active state doesn't match tracked active state "
10285 "(expected %i, found %i)\n", active, encoder->connectors_active);
10286
10287 active = encoder->get_hw_state(encoder, &pipe);
10288 WARN(active != encoder->connectors_active,
10289 "encoder's hw state doesn't match sw tracking "
10290 "(expected %i, found %i)\n",
10291 encoder->connectors_active, active);
10292
10293 if (!encoder->base.crtc)
10294 continue;
10295
10296 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10297 WARN(active && pipe != tracked_pipe,
10298 "active encoder's pipe doesn't match"
10299 "(expected %i, found %i)\n",
10300 tracked_pipe, pipe);
10301
10302 }
10303 }
10304
10305 static void
10306 check_crtc_state(struct drm_device *dev)
10307 {
10308 struct drm_i915_private *dev_priv = dev->dev_private;
10309 struct intel_crtc *crtc;
10310 struct intel_encoder *encoder;
10311 struct intel_crtc_config pipe_config;
10312
10313 for_each_intel_crtc(dev, crtc) {
10314 bool enabled = false;
10315 bool active = false;
10316
10317 memset(&pipe_config, 0, sizeof(pipe_config));
10318
10319 DRM_DEBUG_KMS("[CRTC:%d]\n",
10320 crtc->base.base.id);
10321
10322 WARN(crtc->active && !crtc->base.enabled,
10323 "active crtc, but not enabled in sw tracking\n");
10324
10325 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10326 base.head) {
10327 if (encoder->base.crtc != &crtc->base)
10328 continue;
10329 enabled = true;
10330 if (encoder->connectors_active)
10331 active = true;
10332 }
10333
10334 WARN(active != crtc->active,
10335 "crtc's computed active state doesn't match tracked active state "
10336 "(expected %i, found %i)\n", active, crtc->active);
10337 WARN(enabled != crtc->base.enabled,
10338 "crtc's computed enabled state doesn't match tracked enabled state "
10339 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10340
10341 active = dev_priv->display.get_pipe_config(crtc,
10342 &pipe_config);
10343
10344 /* hw state is inconsistent with the pipe A quirk */
10345 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10346 active = crtc->active;
10347
10348 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10349 base.head) {
10350 enum pipe pipe;
10351 if (encoder->base.crtc != &crtc->base)
10352 continue;
10353 if (encoder->get_hw_state(encoder, &pipe))
10354 encoder->get_config(encoder, &pipe_config);
10355 }
10356
10357 WARN(crtc->active != active,
10358 "crtc active state doesn't match with hw state "
10359 "(expected %i, found %i)\n", crtc->active, active);
10360
10361 if (active &&
10362 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10363 WARN(1, "pipe state doesn't match!\n");
10364 intel_dump_pipe_config(crtc, &pipe_config,
10365 "[hw state]");
10366 intel_dump_pipe_config(crtc, &crtc->config,
10367 "[sw state]");
10368 }
10369 }
10370 }
10371
10372 static void
10373 check_shared_dpll_state(struct drm_device *dev)
10374 {
10375 struct drm_i915_private *dev_priv = dev->dev_private;
10376 struct intel_crtc *crtc;
10377 struct intel_dpll_hw_state dpll_hw_state;
10378 int i;
10379
10380 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10381 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10382 int enabled_crtcs = 0, active_crtcs = 0;
10383 bool active;
10384
10385 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10386
10387 DRM_DEBUG_KMS("%s\n", pll->name);
10388
10389 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10390
10391 WARN(pll->active > pll->refcount,
10392 "more active pll users than references: %i vs %i\n",
10393 pll->active, pll->refcount);
10394 WARN(pll->active && !pll->on,
10395 "pll in active use but not on in sw tracking\n");
10396 WARN(pll->on && !pll->active,
10397 "pll in on but not on in use in sw tracking\n");
10398 WARN(pll->on != active,
10399 "pll on state mismatch (expected %i, found %i)\n",
10400 pll->on, active);
10401
10402 for_each_intel_crtc(dev, crtc) {
10403 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10404 enabled_crtcs++;
10405 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10406 active_crtcs++;
10407 }
10408 WARN(pll->active != active_crtcs,
10409 "pll active crtcs mismatch (expected %i, found %i)\n",
10410 pll->active, active_crtcs);
10411 WARN(pll->refcount != enabled_crtcs,
10412 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10413 pll->refcount, enabled_crtcs);
10414
10415 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10416 sizeof(dpll_hw_state)),
10417 "pll hw state mismatch\n");
10418 }
10419 }
10420
10421 void
10422 intel_modeset_check_state(struct drm_device *dev)
10423 {
10424 check_connector_state(dev);
10425 check_encoder_state(dev);
10426 check_crtc_state(dev);
10427 check_shared_dpll_state(dev);
10428 }
10429
10430 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10431 int dotclock)
10432 {
10433 /*
10434 * FDI already provided one idea for the dotclock.
10435 * Yell if the encoder disagrees.
10436 */
10437 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10438 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10439 pipe_config->adjusted_mode.crtc_clock, dotclock);
10440 }
10441
10442 static void update_scanline_offset(struct intel_crtc *crtc)
10443 {
10444 struct drm_device *dev = crtc->base.dev;
10445
10446 /*
10447 * The scanline counter increments at the leading edge of hsync.
10448 *
10449 * On most platforms it starts counting from vtotal-1 on the
10450 * first active line. That means the scanline counter value is
10451 * always one less than what we would expect. Ie. just after
10452 * start of vblank, which also occurs at start of hsync (on the
10453 * last active line), the scanline counter will read vblank_start-1.
10454 *
10455 * On gen2 the scanline counter starts counting from 1 instead
10456 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10457 * to keep the value positive), instead of adding one.
10458 *
10459 * On HSW+ the behaviour of the scanline counter depends on the output
10460 * type. For DP ports it behaves like most other platforms, but on HDMI
10461 * there's an extra 1 line difference. So we need to add two instead of
10462 * one to the value.
10463 */
10464 if (IS_GEN2(dev)) {
10465 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10466 int vtotal;
10467
10468 vtotal = mode->crtc_vtotal;
10469 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10470 vtotal /= 2;
10471
10472 crtc->scanline_offset = vtotal - 1;
10473 } else if (HAS_DDI(dev) &&
10474 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10475 crtc->scanline_offset = 2;
10476 } else
10477 crtc->scanline_offset = 1;
10478 }
10479
10480 static int __intel_set_mode(struct drm_crtc *crtc,
10481 struct drm_display_mode *mode,
10482 int x, int y, struct drm_framebuffer *fb)
10483 {
10484 struct drm_device *dev = crtc->dev;
10485 struct drm_i915_private *dev_priv = dev->dev_private;
10486 struct drm_display_mode *saved_mode;
10487 struct intel_crtc_config *pipe_config = NULL;
10488 struct intel_crtc *intel_crtc;
10489 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10490 int ret = 0;
10491
10492 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10493 if (!saved_mode)
10494 return -ENOMEM;
10495
10496 intel_modeset_affected_pipes(crtc, &modeset_pipes,
10497 &prepare_pipes, &disable_pipes);
10498
10499 *saved_mode = crtc->mode;
10500
10501 /* Hack: Because we don't (yet) support global modeset on multiple
10502 * crtcs, we don't keep track of the new mode for more than one crtc.
10503 * Hence simply check whether any bit is set in modeset_pipes in all the
10504 * pieces of code that are not yet converted to deal with mutliple crtcs
10505 * changing their mode at the same time. */
10506 if (modeset_pipes) {
10507 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10508 if (IS_ERR(pipe_config)) {
10509 ret = PTR_ERR(pipe_config);
10510 pipe_config = NULL;
10511
10512 goto out;
10513 }
10514 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10515 "[modeset]");
10516 to_intel_crtc(crtc)->new_config = pipe_config;
10517 }
10518
10519 /*
10520 * See if the config requires any additional preparation, e.g.
10521 * to adjust global state with pipes off. We need to do this
10522 * here so we can get the modeset_pipe updated config for the new
10523 * mode set on this crtc. For other crtcs we need to use the
10524 * adjusted_mode bits in the crtc directly.
10525 */
10526 if (IS_VALLEYVIEW(dev)) {
10527 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10528
10529 /* may have added more to prepare_pipes than we should */
10530 prepare_pipes &= ~disable_pipes;
10531 }
10532
10533 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10534 intel_crtc_disable(&intel_crtc->base);
10535
10536 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10537 if (intel_crtc->base.enabled)
10538 dev_priv->display.crtc_disable(&intel_crtc->base);
10539 }
10540
10541 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10542 * to set it here already despite that we pass it down the callchain.
10543 */
10544 if (modeset_pipes) {
10545 crtc->mode = *mode;
10546 /* mode_set/enable/disable functions rely on a correct pipe
10547 * config. */
10548 to_intel_crtc(crtc)->config = *pipe_config;
10549 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10550
10551 /*
10552 * Calculate and store various constants which
10553 * are later needed by vblank and swap-completion
10554 * timestamping. They are derived from true hwmode.
10555 */
10556 drm_calc_timestamping_constants(crtc,
10557 &pipe_config->adjusted_mode);
10558 }
10559
10560 /* Only after disabling all output pipelines that will be changed can we
10561 * update the the output configuration. */
10562 intel_modeset_update_state(dev, prepare_pipes);
10563
10564 if (dev_priv->display.modeset_global_resources)
10565 dev_priv->display.modeset_global_resources(dev);
10566
10567 /* Set up the DPLL and any encoders state that needs to adjust or depend
10568 * on the DPLL.
10569 */
10570 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10571 struct drm_framebuffer *old_fb;
10572
10573 mutex_lock(&dev->struct_mutex);
10574 ret = intel_pin_and_fence_fb_obj(dev,
10575 to_intel_framebuffer(fb)->obj,
10576 NULL);
10577 if (ret != 0) {
10578 DRM_ERROR("pin & fence failed\n");
10579 mutex_unlock(&dev->struct_mutex);
10580 goto done;
10581 }
10582 old_fb = crtc->primary->fb;
10583 if (old_fb)
10584 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
10585 mutex_unlock(&dev->struct_mutex);
10586
10587 crtc->primary->fb = fb;
10588 crtc->x = x;
10589 crtc->y = y;
10590
10591 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10592 x, y, fb);
10593 if (ret)
10594 goto done;
10595 }
10596
10597 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10598 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10599 update_scanline_offset(intel_crtc);
10600
10601 dev_priv->display.crtc_enable(&intel_crtc->base);
10602 }
10603
10604 /* FIXME: add subpixel order */
10605 done:
10606 if (ret && crtc->enabled)
10607 crtc->mode = *saved_mode;
10608
10609 out:
10610 kfree(pipe_config);
10611 kfree(saved_mode);
10612 return ret;
10613 }
10614
10615 static int intel_set_mode(struct drm_crtc *crtc,
10616 struct drm_display_mode *mode,
10617 int x, int y, struct drm_framebuffer *fb)
10618 {
10619 int ret;
10620
10621 ret = __intel_set_mode(crtc, mode, x, y, fb);
10622
10623 if (ret == 0)
10624 intel_modeset_check_state(crtc->dev);
10625
10626 return ret;
10627 }
10628
10629 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10630 {
10631 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10632 }
10633
10634 #undef for_each_intel_crtc_masked
10635
10636 static void intel_set_config_free(struct intel_set_config *config)
10637 {
10638 if (!config)
10639 return;
10640
10641 kfree(config->save_connector_encoders);
10642 kfree(config->save_encoder_crtcs);
10643 kfree(config->save_crtc_enabled);
10644 kfree(config);
10645 }
10646
10647 static int intel_set_config_save_state(struct drm_device *dev,
10648 struct intel_set_config *config)
10649 {
10650 struct drm_crtc *crtc;
10651 struct drm_encoder *encoder;
10652 struct drm_connector *connector;
10653 int count;
10654
10655 config->save_crtc_enabled =
10656 kcalloc(dev->mode_config.num_crtc,
10657 sizeof(bool), GFP_KERNEL);
10658 if (!config->save_crtc_enabled)
10659 return -ENOMEM;
10660
10661 config->save_encoder_crtcs =
10662 kcalloc(dev->mode_config.num_encoder,
10663 sizeof(struct drm_crtc *), GFP_KERNEL);
10664 if (!config->save_encoder_crtcs)
10665 return -ENOMEM;
10666
10667 config->save_connector_encoders =
10668 kcalloc(dev->mode_config.num_connector,
10669 sizeof(struct drm_encoder *), GFP_KERNEL);
10670 if (!config->save_connector_encoders)
10671 return -ENOMEM;
10672
10673 /* Copy data. Note that driver private data is not affected.
10674 * Should anything bad happen only the expected state is
10675 * restored, not the drivers personal bookkeeping.
10676 */
10677 count = 0;
10678 for_each_crtc(dev, crtc) {
10679 config->save_crtc_enabled[count++] = crtc->enabled;
10680 }
10681
10682 count = 0;
10683 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10684 config->save_encoder_crtcs[count++] = encoder->crtc;
10685 }
10686
10687 count = 0;
10688 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10689 config->save_connector_encoders[count++] = connector->encoder;
10690 }
10691
10692 return 0;
10693 }
10694
10695 static void intel_set_config_restore_state(struct drm_device *dev,
10696 struct intel_set_config *config)
10697 {
10698 struct intel_crtc *crtc;
10699 struct intel_encoder *encoder;
10700 struct intel_connector *connector;
10701 int count;
10702
10703 count = 0;
10704 for_each_intel_crtc(dev, crtc) {
10705 crtc->new_enabled = config->save_crtc_enabled[count++];
10706
10707 if (crtc->new_enabled)
10708 crtc->new_config = &crtc->config;
10709 else
10710 crtc->new_config = NULL;
10711 }
10712
10713 count = 0;
10714 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10715 encoder->new_crtc =
10716 to_intel_crtc(config->save_encoder_crtcs[count++]);
10717 }
10718
10719 count = 0;
10720 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10721 connector->new_encoder =
10722 to_intel_encoder(config->save_connector_encoders[count++]);
10723 }
10724 }
10725
10726 static bool
10727 is_crtc_connector_off(struct drm_mode_set *set)
10728 {
10729 int i;
10730
10731 if (set->num_connectors == 0)
10732 return false;
10733
10734 if (WARN_ON(set->connectors == NULL))
10735 return false;
10736
10737 for (i = 0; i < set->num_connectors; i++)
10738 if (set->connectors[i]->encoder &&
10739 set->connectors[i]->encoder->crtc == set->crtc &&
10740 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10741 return true;
10742
10743 return false;
10744 }
10745
10746 static void
10747 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10748 struct intel_set_config *config)
10749 {
10750
10751 /* We should be able to check here if the fb has the same properties
10752 * and then just flip_or_move it */
10753 if (is_crtc_connector_off(set)) {
10754 config->mode_changed = true;
10755 } else if (set->crtc->primary->fb != set->fb) {
10756 /*
10757 * If we have no fb, we can only flip as long as the crtc is
10758 * active, otherwise we need a full mode set. The crtc may
10759 * be active if we've only disabled the primary plane, or
10760 * in fastboot situations.
10761 */
10762 if (set->crtc->primary->fb == NULL) {
10763 struct intel_crtc *intel_crtc =
10764 to_intel_crtc(set->crtc);
10765
10766 if (intel_crtc->active) {
10767 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10768 config->fb_changed = true;
10769 } else {
10770 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10771 config->mode_changed = true;
10772 }
10773 } else if (set->fb == NULL) {
10774 config->mode_changed = true;
10775 } else if (set->fb->pixel_format !=
10776 set->crtc->primary->fb->pixel_format) {
10777 config->mode_changed = true;
10778 } else {
10779 config->fb_changed = true;
10780 }
10781 }
10782
10783 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10784 config->fb_changed = true;
10785
10786 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10787 DRM_DEBUG_KMS("modes are different, full mode set\n");
10788 drm_mode_debug_printmodeline(&set->crtc->mode);
10789 drm_mode_debug_printmodeline(set->mode);
10790 config->mode_changed = true;
10791 }
10792
10793 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10794 set->crtc->base.id, config->mode_changed, config->fb_changed);
10795 }
10796
10797 static int
10798 intel_modeset_stage_output_state(struct drm_device *dev,
10799 struct drm_mode_set *set,
10800 struct intel_set_config *config)
10801 {
10802 struct intel_connector *connector;
10803 struct intel_encoder *encoder;
10804 struct intel_crtc *crtc;
10805 int ro;
10806
10807 /* The upper layers ensure that we either disable a crtc or have a list
10808 * of connectors. For paranoia, double-check this. */
10809 WARN_ON(!set->fb && (set->num_connectors != 0));
10810 WARN_ON(set->fb && (set->num_connectors == 0));
10811
10812 list_for_each_entry(connector, &dev->mode_config.connector_list,
10813 base.head) {
10814 /* Otherwise traverse passed in connector list and get encoders
10815 * for them. */
10816 for (ro = 0; ro < set->num_connectors; ro++) {
10817 if (set->connectors[ro] == &connector->base) {
10818 connector->new_encoder = connector->encoder;
10819 break;
10820 }
10821 }
10822
10823 /* If we disable the crtc, disable all its connectors. Also, if
10824 * the connector is on the changing crtc but not on the new
10825 * connector list, disable it. */
10826 if ((!set->fb || ro == set->num_connectors) &&
10827 connector->base.encoder &&
10828 connector->base.encoder->crtc == set->crtc) {
10829 connector->new_encoder = NULL;
10830
10831 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10832 connector->base.base.id,
10833 connector->base.name);
10834 }
10835
10836
10837 if (&connector->new_encoder->base != connector->base.encoder) {
10838 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10839 config->mode_changed = true;
10840 }
10841 }
10842 /* connector->new_encoder is now updated for all connectors. */
10843
10844 /* Update crtc of enabled connectors. */
10845 list_for_each_entry(connector, &dev->mode_config.connector_list,
10846 base.head) {
10847 struct drm_crtc *new_crtc;
10848
10849 if (!connector->new_encoder)
10850 continue;
10851
10852 new_crtc = connector->new_encoder->base.crtc;
10853
10854 for (ro = 0; ro < set->num_connectors; ro++) {
10855 if (set->connectors[ro] == &connector->base)
10856 new_crtc = set->crtc;
10857 }
10858
10859 /* Make sure the new CRTC will work with the encoder */
10860 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10861 new_crtc)) {
10862 return -EINVAL;
10863 }
10864 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10865
10866 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10867 connector->base.base.id,
10868 connector->base.name,
10869 new_crtc->base.id);
10870 }
10871
10872 /* Check for any encoders that needs to be disabled. */
10873 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10874 base.head) {
10875 int num_connectors = 0;
10876 list_for_each_entry(connector,
10877 &dev->mode_config.connector_list,
10878 base.head) {
10879 if (connector->new_encoder == encoder) {
10880 WARN_ON(!connector->new_encoder->new_crtc);
10881 num_connectors++;
10882 }
10883 }
10884
10885 if (num_connectors == 0)
10886 encoder->new_crtc = NULL;
10887 else if (num_connectors > 1)
10888 return -EINVAL;
10889
10890 /* Only now check for crtc changes so we don't miss encoders
10891 * that will be disabled. */
10892 if (&encoder->new_crtc->base != encoder->base.crtc) {
10893 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10894 config->mode_changed = true;
10895 }
10896 }
10897 /* Now we've also updated encoder->new_crtc for all encoders. */
10898
10899 for_each_intel_crtc(dev, crtc) {
10900 crtc->new_enabled = false;
10901
10902 list_for_each_entry(encoder,
10903 &dev->mode_config.encoder_list,
10904 base.head) {
10905 if (encoder->new_crtc == crtc) {
10906 crtc->new_enabled = true;
10907 break;
10908 }
10909 }
10910
10911 if (crtc->new_enabled != crtc->base.enabled) {
10912 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10913 crtc->new_enabled ? "en" : "dis");
10914 config->mode_changed = true;
10915 }
10916
10917 if (crtc->new_enabled)
10918 crtc->new_config = &crtc->config;
10919 else
10920 crtc->new_config = NULL;
10921 }
10922
10923 return 0;
10924 }
10925
10926 static void disable_crtc_nofb(struct intel_crtc *crtc)
10927 {
10928 struct drm_device *dev = crtc->base.dev;
10929 struct intel_encoder *encoder;
10930 struct intel_connector *connector;
10931
10932 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10933 pipe_name(crtc->pipe));
10934
10935 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10936 if (connector->new_encoder &&
10937 connector->new_encoder->new_crtc == crtc)
10938 connector->new_encoder = NULL;
10939 }
10940
10941 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10942 if (encoder->new_crtc == crtc)
10943 encoder->new_crtc = NULL;
10944 }
10945
10946 crtc->new_enabled = false;
10947 crtc->new_config = NULL;
10948 }
10949
10950 static int intel_crtc_set_config(struct drm_mode_set *set)
10951 {
10952 struct drm_device *dev;
10953 struct drm_mode_set save_set;
10954 struct intel_set_config *config;
10955 int ret;
10956
10957 BUG_ON(!set);
10958 BUG_ON(!set->crtc);
10959 BUG_ON(!set->crtc->helper_private);
10960
10961 /* Enforce sane interface api - has been abused by the fb helper. */
10962 BUG_ON(!set->mode && set->fb);
10963 BUG_ON(set->fb && set->num_connectors == 0);
10964
10965 if (set->fb) {
10966 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10967 set->crtc->base.id, set->fb->base.id,
10968 (int)set->num_connectors, set->x, set->y);
10969 } else {
10970 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10971 }
10972
10973 dev = set->crtc->dev;
10974
10975 ret = -ENOMEM;
10976 config = kzalloc(sizeof(*config), GFP_KERNEL);
10977 if (!config)
10978 goto out_config;
10979
10980 ret = intel_set_config_save_state(dev, config);
10981 if (ret)
10982 goto out_config;
10983
10984 save_set.crtc = set->crtc;
10985 save_set.mode = &set->crtc->mode;
10986 save_set.x = set->crtc->x;
10987 save_set.y = set->crtc->y;
10988 save_set.fb = set->crtc->primary->fb;
10989
10990 /* Compute whether we need a full modeset, only an fb base update or no
10991 * change at all. In the future we might also check whether only the
10992 * mode changed, e.g. for LVDS where we only change the panel fitter in
10993 * such cases. */
10994 intel_set_config_compute_mode_changes(set, config);
10995
10996 ret = intel_modeset_stage_output_state(dev, set, config);
10997 if (ret)
10998 goto fail;
10999
11000 if (config->mode_changed) {
11001 ret = intel_set_mode(set->crtc, set->mode,
11002 set->x, set->y, set->fb);
11003 } else if (config->fb_changed) {
11004 struct drm_i915_private *dev_priv = dev->dev_private;
11005 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11006
11007 intel_crtc_wait_for_pending_flips(set->crtc);
11008
11009 ret = intel_pipe_set_base(set->crtc,
11010 set->x, set->y, set->fb);
11011
11012 /*
11013 * We need to make sure the primary plane is re-enabled if it
11014 * has previously been turned off.
11015 */
11016 if (!intel_crtc->primary_enabled && ret == 0) {
11017 WARN_ON(!intel_crtc->active);
11018 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11019 intel_crtc->pipe);
11020 }
11021
11022 /*
11023 * In the fastboot case this may be our only check of the
11024 * state after boot. It would be better to only do it on
11025 * the first update, but we don't have a nice way of doing that
11026 * (and really, set_config isn't used much for high freq page
11027 * flipping, so increasing its cost here shouldn't be a big
11028 * deal).
11029 */
11030 if (i915.fastboot && ret == 0)
11031 intel_modeset_check_state(set->crtc->dev);
11032 }
11033
11034 if (ret) {
11035 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11036 set->crtc->base.id, ret);
11037 fail:
11038 intel_set_config_restore_state(dev, config);
11039
11040 /*
11041 * HACK: if the pipe was on, but we didn't have a framebuffer,
11042 * force the pipe off to avoid oopsing in the modeset code
11043 * due to fb==NULL. This should only happen during boot since
11044 * we don't yet reconstruct the FB from the hardware state.
11045 */
11046 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11047 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11048
11049 /* Try to restore the config */
11050 if (config->mode_changed &&
11051 intel_set_mode(save_set.crtc, save_set.mode,
11052 save_set.x, save_set.y, save_set.fb))
11053 DRM_ERROR("failed to restore config after modeset failure\n");
11054 }
11055
11056 out_config:
11057 intel_set_config_free(config);
11058 return ret;
11059 }
11060
11061 static const struct drm_crtc_funcs intel_crtc_funcs = {
11062 .gamma_set = intel_crtc_gamma_set,
11063 .set_config = intel_crtc_set_config,
11064 .destroy = intel_crtc_destroy,
11065 .page_flip = intel_crtc_page_flip,
11066 };
11067
11068 static void intel_cpu_pll_init(struct drm_device *dev)
11069 {
11070 if (HAS_DDI(dev))
11071 intel_ddi_pll_init(dev);
11072 }
11073
11074 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11075 struct intel_shared_dpll *pll,
11076 struct intel_dpll_hw_state *hw_state)
11077 {
11078 uint32_t val;
11079
11080 val = I915_READ(PCH_DPLL(pll->id));
11081 hw_state->dpll = val;
11082 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11083 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11084
11085 return val & DPLL_VCO_ENABLE;
11086 }
11087
11088 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11089 struct intel_shared_dpll *pll)
11090 {
11091 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11092 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11093 }
11094
11095 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11096 struct intel_shared_dpll *pll)
11097 {
11098 /* PCH refclock must be enabled first */
11099 ibx_assert_pch_refclk_enabled(dev_priv);
11100
11101 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11102
11103 /* Wait for the clocks to stabilize. */
11104 POSTING_READ(PCH_DPLL(pll->id));
11105 udelay(150);
11106
11107 /* The pixel multiplier can only be updated once the
11108 * DPLL is enabled and the clocks are stable.
11109 *
11110 * So write it again.
11111 */
11112 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11113 POSTING_READ(PCH_DPLL(pll->id));
11114 udelay(200);
11115 }
11116
11117 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11118 struct intel_shared_dpll *pll)
11119 {
11120 struct drm_device *dev = dev_priv->dev;
11121 struct intel_crtc *crtc;
11122
11123 /* Make sure no transcoder isn't still depending on us. */
11124 for_each_intel_crtc(dev, crtc) {
11125 if (intel_crtc_to_shared_dpll(crtc) == pll)
11126 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11127 }
11128
11129 I915_WRITE(PCH_DPLL(pll->id), 0);
11130 POSTING_READ(PCH_DPLL(pll->id));
11131 udelay(200);
11132 }
11133
11134 static char *ibx_pch_dpll_names[] = {
11135 "PCH DPLL A",
11136 "PCH DPLL B",
11137 };
11138
11139 static void ibx_pch_dpll_init(struct drm_device *dev)
11140 {
11141 struct drm_i915_private *dev_priv = dev->dev_private;
11142 int i;
11143
11144 dev_priv->num_shared_dpll = 2;
11145
11146 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11147 dev_priv->shared_dplls[i].id = i;
11148 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11149 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11150 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11151 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11152 dev_priv->shared_dplls[i].get_hw_state =
11153 ibx_pch_dpll_get_hw_state;
11154 }
11155 }
11156
11157 static void intel_shared_dpll_init(struct drm_device *dev)
11158 {
11159 struct drm_i915_private *dev_priv = dev->dev_private;
11160
11161 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11162 ibx_pch_dpll_init(dev);
11163 else
11164 dev_priv->num_shared_dpll = 0;
11165
11166 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11167 }
11168
11169 static int
11170 intel_primary_plane_disable(struct drm_plane *plane)
11171 {
11172 struct drm_device *dev = plane->dev;
11173 struct drm_i915_private *dev_priv = dev->dev_private;
11174 struct intel_plane *intel_plane = to_intel_plane(plane);
11175 struct intel_crtc *intel_crtc;
11176
11177 if (!plane->fb)
11178 return 0;
11179
11180 BUG_ON(!plane->crtc);
11181
11182 intel_crtc = to_intel_crtc(plane->crtc);
11183
11184 /*
11185 * Even though we checked plane->fb above, it's still possible that
11186 * the primary plane has been implicitly disabled because the crtc
11187 * coordinates given weren't visible, or because we detected
11188 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11189 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11190 * In either case, we need to unpin the FB and let the fb pointer get
11191 * updated, but otherwise we don't need to touch the hardware.
11192 */
11193 if (!intel_crtc->primary_enabled)
11194 goto disable_unpin;
11195
11196 intel_crtc_wait_for_pending_flips(plane->crtc);
11197 intel_disable_primary_hw_plane(dev_priv, intel_plane->plane,
11198 intel_plane->pipe);
11199
11200 disable_unpin:
11201 intel_unpin_fb_obj(to_intel_framebuffer(plane->fb)->obj);
11202 plane->fb = NULL;
11203
11204 return 0;
11205 }
11206
11207 static int
11208 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11209 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11210 unsigned int crtc_w, unsigned int crtc_h,
11211 uint32_t src_x, uint32_t src_y,
11212 uint32_t src_w, uint32_t src_h)
11213 {
11214 struct drm_device *dev = crtc->dev;
11215 struct drm_i915_private *dev_priv = dev->dev_private;
11216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11217 struct intel_plane *intel_plane = to_intel_plane(plane);
11218 struct drm_rect dest = {
11219 /* integer pixels */
11220 .x1 = crtc_x,
11221 .y1 = crtc_y,
11222 .x2 = crtc_x + crtc_w,
11223 .y2 = crtc_y + crtc_h,
11224 };
11225 struct drm_rect src = {
11226 /* 16.16 fixed point */
11227 .x1 = src_x,
11228 .y1 = src_y,
11229 .x2 = src_x + src_w,
11230 .y2 = src_y + src_h,
11231 };
11232 const struct drm_rect clip = {
11233 /* integer pixels */
11234 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11235 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11236 };
11237 bool visible;
11238 int ret;
11239
11240 ret = drm_plane_helper_check_update(plane, crtc, fb,
11241 &src, &dest, &clip,
11242 DRM_PLANE_HELPER_NO_SCALING,
11243 DRM_PLANE_HELPER_NO_SCALING,
11244 false, true, &visible);
11245
11246 if (ret)
11247 return ret;
11248
11249 /*
11250 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11251 * updating the fb pointer, and returning without touching the
11252 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11253 * turn on the display with all planes setup as desired.
11254 */
11255 if (!crtc->enabled) {
11256 /*
11257 * If we already called setplane while the crtc was disabled,
11258 * we may have an fb pinned; unpin it.
11259 */
11260 if (plane->fb)
11261 intel_unpin_fb_obj(to_intel_framebuffer(plane->fb)->obj);
11262
11263 /* Pin and return without programming hardware */
11264 return intel_pin_and_fence_fb_obj(dev,
11265 to_intel_framebuffer(fb)->obj,
11266 NULL);
11267 }
11268
11269 intel_crtc_wait_for_pending_flips(crtc);
11270
11271 /*
11272 * If clipping results in a non-visible primary plane, we'll disable
11273 * the primary plane. Note that this is a bit different than what
11274 * happens if userspace explicitly disables the plane by passing fb=0
11275 * because plane->fb still gets set and pinned.
11276 */
11277 if (!visible) {
11278 /*
11279 * Try to pin the new fb first so that we can bail out if we
11280 * fail.
11281 */
11282 if (plane->fb != fb) {
11283 ret = intel_pin_and_fence_fb_obj(dev,
11284 to_intel_framebuffer(fb)->obj,
11285 NULL);
11286 if (ret)
11287 return ret;
11288 }
11289
11290 if (intel_crtc->primary_enabled)
11291 intel_disable_primary_hw_plane(dev_priv,
11292 intel_plane->plane,
11293 intel_plane->pipe);
11294
11295
11296 if (plane->fb != fb)
11297 if (plane->fb)
11298 intel_unpin_fb_obj(to_intel_framebuffer(plane->fb)->obj);
11299
11300 return 0;
11301 }
11302
11303 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11304 if (ret)
11305 return ret;
11306
11307 if (!intel_crtc->primary_enabled)
11308 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11309 intel_crtc->pipe);
11310
11311 return 0;
11312 }
11313
11314 /* Common destruction function for both primary and cursor planes */
11315 static void intel_plane_destroy(struct drm_plane *plane)
11316 {
11317 struct intel_plane *intel_plane = to_intel_plane(plane);
11318 drm_plane_cleanup(plane);
11319 kfree(intel_plane);
11320 }
11321
11322 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11323 .update_plane = intel_primary_plane_setplane,
11324 .disable_plane = intel_primary_plane_disable,
11325 .destroy = intel_plane_destroy,
11326 };
11327
11328 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11329 int pipe)
11330 {
11331 struct intel_plane *primary;
11332 const uint32_t *intel_primary_formats;
11333 int num_formats;
11334
11335 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11336 if (primary == NULL)
11337 return NULL;
11338
11339 primary->can_scale = false;
11340 primary->max_downscale = 1;
11341 primary->pipe = pipe;
11342 primary->plane = pipe;
11343 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11344 primary->plane = !pipe;
11345
11346 if (INTEL_INFO(dev)->gen <= 3) {
11347 intel_primary_formats = intel_primary_formats_gen2;
11348 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11349 } else {
11350 intel_primary_formats = intel_primary_formats_gen4;
11351 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11352 }
11353
11354 drm_universal_plane_init(dev, &primary->base, 0,
11355 &intel_primary_plane_funcs,
11356 intel_primary_formats, num_formats,
11357 DRM_PLANE_TYPE_PRIMARY);
11358 return &primary->base;
11359 }
11360
11361 static int
11362 intel_cursor_plane_disable(struct drm_plane *plane)
11363 {
11364 if (!plane->fb)
11365 return 0;
11366
11367 BUG_ON(!plane->crtc);
11368
11369 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11370 }
11371
11372 static int
11373 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11374 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11375 unsigned int crtc_w, unsigned int crtc_h,
11376 uint32_t src_x, uint32_t src_y,
11377 uint32_t src_w, uint32_t src_h)
11378 {
11379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11380 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11381 struct drm_i915_gem_object *obj = intel_fb->obj;
11382 struct drm_rect dest = {
11383 /* integer pixels */
11384 .x1 = crtc_x,
11385 .y1 = crtc_y,
11386 .x2 = crtc_x + crtc_w,
11387 .y2 = crtc_y + crtc_h,
11388 };
11389 struct drm_rect src = {
11390 /* 16.16 fixed point */
11391 .x1 = src_x,
11392 .y1 = src_y,
11393 .x2 = src_x + src_w,
11394 .y2 = src_y + src_h,
11395 };
11396 const struct drm_rect clip = {
11397 /* integer pixels */
11398 .x2 = intel_crtc->config.pipe_src_w,
11399 .y2 = intel_crtc->config.pipe_src_h,
11400 };
11401 bool visible;
11402 int ret;
11403
11404 ret = drm_plane_helper_check_update(plane, crtc, fb,
11405 &src, &dest, &clip,
11406 DRM_PLANE_HELPER_NO_SCALING,
11407 DRM_PLANE_HELPER_NO_SCALING,
11408 true, true, &visible);
11409 if (ret)
11410 return ret;
11411
11412 crtc->cursor_x = crtc_x;
11413 crtc->cursor_y = crtc_y;
11414 if (fb != crtc->cursor->fb) {
11415 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11416 } else {
11417 intel_crtc_update_cursor(crtc, visible);
11418 return 0;
11419 }
11420 }
11421 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11422 .update_plane = intel_cursor_plane_update,
11423 .disable_plane = intel_cursor_plane_disable,
11424 .destroy = intel_plane_destroy,
11425 };
11426
11427 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11428 int pipe)
11429 {
11430 struct intel_plane *cursor;
11431
11432 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11433 if (cursor == NULL)
11434 return NULL;
11435
11436 cursor->can_scale = false;
11437 cursor->max_downscale = 1;
11438 cursor->pipe = pipe;
11439 cursor->plane = pipe;
11440
11441 drm_universal_plane_init(dev, &cursor->base, 0,
11442 &intel_cursor_plane_funcs,
11443 intel_cursor_formats,
11444 ARRAY_SIZE(intel_cursor_formats),
11445 DRM_PLANE_TYPE_CURSOR);
11446 return &cursor->base;
11447 }
11448
11449 static void intel_crtc_init(struct drm_device *dev, int pipe)
11450 {
11451 struct drm_i915_private *dev_priv = dev->dev_private;
11452 struct intel_crtc *intel_crtc;
11453 struct drm_plane *primary = NULL;
11454 struct drm_plane *cursor = NULL;
11455 int i, ret;
11456
11457 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11458 if (intel_crtc == NULL)
11459 return;
11460
11461 primary = intel_primary_plane_create(dev, pipe);
11462 if (!primary)
11463 goto fail;
11464
11465 cursor = intel_cursor_plane_create(dev, pipe);
11466 if (!cursor)
11467 goto fail;
11468
11469 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11470 cursor, &intel_crtc_funcs);
11471 if (ret)
11472 goto fail;
11473
11474 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11475 for (i = 0; i < 256; i++) {
11476 intel_crtc->lut_r[i] = i;
11477 intel_crtc->lut_g[i] = i;
11478 intel_crtc->lut_b[i] = i;
11479 }
11480
11481 /*
11482 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11483 * is hooked to pipe B. Hence we want plane A feeding pipe B.
11484 */
11485 intel_crtc->pipe = pipe;
11486 intel_crtc->plane = pipe;
11487 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11488 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11489 intel_crtc->plane = !pipe;
11490 }
11491
11492 intel_crtc->cursor_base = ~0;
11493 intel_crtc->cursor_cntl = ~0;
11494
11495 init_waitqueue_head(&intel_crtc->vbl_wait);
11496
11497 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11498 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11499 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11500 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11501
11502 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11503
11504 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11505 return;
11506
11507 fail:
11508 if (primary)
11509 drm_plane_cleanup(primary);
11510 if (cursor)
11511 drm_plane_cleanup(cursor);
11512 kfree(intel_crtc);
11513 }
11514
11515 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11516 {
11517 struct drm_encoder *encoder = connector->base.encoder;
11518 struct drm_device *dev = connector->base.dev;
11519
11520 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11521
11522 if (!encoder)
11523 return INVALID_PIPE;
11524
11525 return to_intel_crtc(encoder->crtc)->pipe;
11526 }
11527
11528 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
11529 struct drm_file *file)
11530 {
11531 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11532 struct drm_mode_object *drmmode_obj;
11533 struct intel_crtc *crtc;
11534
11535 if (!drm_core_check_feature(dev, DRIVER_MODESET))
11536 return -ENODEV;
11537
11538 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
11539 DRM_MODE_OBJECT_CRTC);
11540
11541 if (!drmmode_obj) {
11542 DRM_ERROR("no such CRTC id\n");
11543 return -ENOENT;
11544 }
11545
11546 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
11547 pipe_from_crtc_id->pipe = crtc->pipe;
11548
11549 return 0;
11550 }
11551
11552 static int intel_encoder_clones(struct intel_encoder *encoder)
11553 {
11554 struct drm_device *dev = encoder->base.dev;
11555 struct intel_encoder *source_encoder;
11556 int index_mask = 0;
11557 int entry = 0;
11558
11559 list_for_each_entry(source_encoder,
11560 &dev->mode_config.encoder_list, base.head) {
11561 if (encoders_cloneable(encoder, source_encoder))
11562 index_mask |= (1 << entry);
11563
11564 entry++;
11565 }
11566
11567 return index_mask;
11568 }
11569
11570 static bool has_edp_a(struct drm_device *dev)
11571 {
11572 struct drm_i915_private *dev_priv = dev->dev_private;
11573
11574 if (!IS_MOBILE(dev))
11575 return false;
11576
11577 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11578 return false;
11579
11580 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
11581 return false;
11582
11583 return true;
11584 }
11585
11586 const char *intel_output_name(int output)
11587 {
11588 static const char *names[] = {
11589 [INTEL_OUTPUT_UNUSED] = "Unused",
11590 [INTEL_OUTPUT_ANALOG] = "Analog",
11591 [INTEL_OUTPUT_DVO] = "DVO",
11592 [INTEL_OUTPUT_SDVO] = "SDVO",
11593 [INTEL_OUTPUT_LVDS] = "LVDS",
11594 [INTEL_OUTPUT_TVOUT] = "TV",
11595 [INTEL_OUTPUT_HDMI] = "HDMI",
11596 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
11597 [INTEL_OUTPUT_EDP] = "eDP",
11598 [INTEL_OUTPUT_DSI] = "DSI",
11599 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
11600 };
11601
11602 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11603 return "Invalid";
11604
11605 return names[output];
11606 }
11607
11608 static void intel_setup_outputs(struct drm_device *dev)
11609 {
11610 struct drm_i915_private *dev_priv = dev->dev_private;
11611 struct intel_encoder *encoder;
11612 bool dpd_is_edp = false;
11613
11614 intel_lvds_init(dev);
11615
11616 if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev) && dev_priv->vbt.int_crt_support)
11617 intel_crt_init(dev);
11618
11619 if (HAS_DDI(dev)) {
11620 int found;
11621
11622 /* Haswell uses DDI functions to detect digital outputs */
11623 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
11624 /* DDI A only supports eDP */
11625 if (found)
11626 intel_ddi_init(dev, PORT_A);
11627
11628 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11629 * register */
11630 found = I915_READ(SFUSE_STRAP);
11631
11632 if (found & SFUSE_STRAP_DDIB_DETECTED)
11633 intel_ddi_init(dev, PORT_B);
11634 if (found & SFUSE_STRAP_DDIC_DETECTED)
11635 intel_ddi_init(dev, PORT_C);
11636 if (found & SFUSE_STRAP_DDID_DETECTED)
11637 intel_ddi_init(dev, PORT_D);
11638 } else if (HAS_PCH_SPLIT(dev)) {
11639 int found;
11640 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
11641
11642 if (has_edp_a(dev))
11643 intel_dp_init(dev, DP_A, PORT_A);
11644
11645 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
11646 /* PCH SDVOB multiplex with HDMIB */
11647 found = intel_sdvo_init(dev, PCH_SDVOB, true);
11648 if (!found)
11649 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
11650 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
11651 intel_dp_init(dev, PCH_DP_B, PORT_B);
11652 }
11653
11654 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
11655 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
11656
11657 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
11658 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
11659
11660 if (I915_READ(PCH_DP_C) & DP_DETECTED)
11661 intel_dp_init(dev, PCH_DP_C, PORT_C);
11662
11663 if (I915_READ(PCH_DP_D) & DP_DETECTED)
11664 intel_dp_init(dev, PCH_DP_D, PORT_D);
11665 } else if (IS_VALLEYVIEW(dev)) {
11666 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11667 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11668 PORT_B);
11669 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11670 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11671 }
11672
11673 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11674 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11675 PORT_C);
11676 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
11677 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
11678 }
11679
11680 if (IS_CHERRYVIEW(dev)) {
11681 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
11682 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
11683 PORT_D);
11684 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
11685 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
11686 }
11687 }
11688
11689 intel_dsi_init(dev);
11690 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
11691 bool found = false;
11692
11693 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11694 DRM_DEBUG_KMS("probing SDVOB\n");
11695 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
11696 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
11697 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
11698 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
11699 }
11700
11701 if (!found && SUPPORTS_INTEGRATED_DP(dev))
11702 intel_dp_init(dev, DP_B, PORT_B);
11703 }
11704
11705 /* Before G4X SDVOC doesn't have its own detect register */
11706
11707 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11708 DRM_DEBUG_KMS("probing SDVOC\n");
11709 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
11710 }
11711
11712 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
11713
11714 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11715 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
11716 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
11717 }
11718 if (SUPPORTS_INTEGRATED_DP(dev))
11719 intel_dp_init(dev, DP_C, PORT_C);
11720 }
11721
11722 if (SUPPORTS_INTEGRATED_DP(dev) &&
11723 (I915_READ(DP_D) & DP_DETECTED))
11724 intel_dp_init(dev, DP_D, PORT_D);
11725 } else if (IS_GEN2(dev))
11726 intel_dvo_init(dev);
11727
11728 if (SUPPORTS_TV(dev))
11729 intel_tv_init(dev);
11730
11731 intel_edp_psr_init(dev);
11732
11733 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11734 encoder->base.possible_crtcs = encoder->crtc_mask;
11735 encoder->base.possible_clones =
11736 intel_encoder_clones(encoder);
11737 }
11738
11739 intel_init_pch_refclk(dev);
11740
11741 drm_helper_move_panel_connectors_to_head(dev);
11742 }
11743
11744 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11745 {
11746 struct drm_device *dev = fb->dev;
11747 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11748
11749 drm_framebuffer_cleanup(fb);
11750 mutex_lock(&dev->struct_mutex);
11751 WARN_ON(!intel_fb->obj->framebuffer_references--);
11752 drm_gem_object_unreference(&intel_fb->obj->base);
11753 mutex_unlock(&dev->struct_mutex);
11754 kfree(intel_fb);
11755 }
11756
11757 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
11758 struct drm_file *file,
11759 unsigned int *handle)
11760 {
11761 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11762 struct drm_i915_gem_object *obj = intel_fb->obj;
11763
11764 return drm_gem_handle_create(file, &obj->base, handle);
11765 }
11766
11767 static const struct drm_framebuffer_funcs intel_fb_funcs = {
11768 .destroy = intel_user_framebuffer_destroy,
11769 .create_handle = intel_user_framebuffer_create_handle,
11770 };
11771
11772 static int intel_framebuffer_init(struct drm_device *dev,
11773 struct intel_framebuffer *intel_fb,
11774 struct drm_mode_fb_cmd2 *mode_cmd,
11775 struct drm_i915_gem_object *obj)
11776 {
11777 int aligned_height;
11778 int pitch_limit;
11779 int ret;
11780
11781 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
11782
11783 if (obj->tiling_mode == I915_TILING_Y) {
11784 DRM_DEBUG("hardware does not support tiling Y\n");
11785 return -EINVAL;
11786 }
11787
11788 if (mode_cmd->pitches[0] & 63) {
11789 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
11790 mode_cmd->pitches[0]);
11791 return -EINVAL;
11792 }
11793
11794 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
11795 pitch_limit = 32*1024;
11796 } else if (INTEL_INFO(dev)->gen >= 4) {
11797 if (obj->tiling_mode)
11798 pitch_limit = 16*1024;
11799 else
11800 pitch_limit = 32*1024;
11801 } else if (INTEL_INFO(dev)->gen >= 3) {
11802 if (obj->tiling_mode)
11803 pitch_limit = 8*1024;
11804 else
11805 pitch_limit = 16*1024;
11806 } else
11807 /* XXX DSPC is limited to 4k tiled */
11808 pitch_limit = 8*1024;
11809
11810 if (mode_cmd->pitches[0] > pitch_limit) {
11811 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
11812 obj->tiling_mode ? "tiled" : "linear",
11813 mode_cmd->pitches[0], pitch_limit);
11814 return -EINVAL;
11815 }
11816
11817 if (obj->tiling_mode != I915_TILING_NONE &&
11818 mode_cmd->pitches[0] != obj->stride) {
11819 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
11820 mode_cmd->pitches[0], obj->stride);
11821 return -EINVAL;
11822 }
11823
11824 /* Reject formats not supported by any plane early. */
11825 switch (mode_cmd->pixel_format) {
11826 case DRM_FORMAT_C8:
11827 case DRM_FORMAT_RGB565:
11828 case DRM_FORMAT_XRGB8888:
11829 case DRM_FORMAT_ARGB8888:
11830 break;
11831 case DRM_FORMAT_XRGB1555:
11832 case DRM_FORMAT_ARGB1555:
11833 if (INTEL_INFO(dev)->gen > 3) {
11834 DRM_DEBUG("unsupported pixel format: %s\n",
11835 drm_get_format_name(mode_cmd->pixel_format));
11836 return -EINVAL;
11837 }
11838 break;
11839 case DRM_FORMAT_XBGR8888:
11840 case DRM_FORMAT_ABGR8888:
11841 case DRM_FORMAT_XRGB2101010:
11842 case DRM_FORMAT_ARGB2101010:
11843 case DRM_FORMAT_XBGR2101010:
11844 case DRM_FORMAT_ABGR2101010:
11845 if (INTEL_INFO(dev)->gen < 4) {
11846 DRM_DEBUG("unsupported pixel format: %s\n",
11847 drm_get_format_name(mode_cmd->pixel_format));
11848 return -EINVAL;
11849 }
11850 break;
11851 case DRM_FORMAT_YUYV:
11852 case DRM_FORMAT_UYVY:
11853 case DRM_FORMAT_YVYU:
11854 case DRM_FORMAT_VYUY:
11855 if (INTEL_INFO(dev)->gen < 5) {
11856 DRM_DEBUG("unsupported pixel format: %s\n",
11857 drm_get_format_name(mode_cmd->pixel_format));
11858 return -EINVAL;
11859 }
11860 break;
11861 default:
11862 DRM_DEBUG("unsupported pixel format: %s\n",
11863 drm_get_format_name(mode_cmd->pixel_format));
11864 return -EINVAL;
11865 }
11866
11867 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
11868 if (mode_cmd->offsets[0] != 0)
11869 return -EINVAL;
11870
11871 aligned_height = intel_align_height(dev, mode_cmd->height,
11872 obj->tiling_mode);
11873 /* FIXME drm helper for size checks (especially planar formats)? */
11874 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
11875 return -EINVAL;
11876
11877 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
11878 intel_fb->obj = obj;
11879 intel_fb->obj->framebuffer_references++;
11880
11881 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
11882 if (ret) {
11883 DRM_ERROR("framebuffer init failed %d\n", ret);
11884 return ret;
11885 }
11886
11887 return 0;
11888 }
11889
11890 static struct drm_framebuffer *
11891 intel_user_framebuffer_create(struct drm_device *dev,
11892 struct drm_file *filp,
11893 struct drm_mode_fb_cmd2 *mode_cmd)
11894 {
11895 struct drm_i915_gem_object *obj;
11896
11897 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
11898 mode_cmd->handles[0]));
11899 if (&obj->base == NULL)
11900 return ERR_PTR(-ENOENT);
11901
11902 return intel_framebuffer_create(dev, mode_cmd, obj);
11903 }
11904
11905 #ifndef CONFIG_DRM_I915_FBDEV
11906 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
11907 {
11908 }
11909 #endif
11910
11911 static const struct drm_mode_config_funcs intel_mode_funcs = {
11912 .fb_create = intel_user_framebuffer_create,
11913 .output_poll_changed = intel_fbdev_output_poll_changed,
11914 };
11915
11916 /* Set up chip specific display functions */
11917 static void intel_init_display(struct drm_device *dev)
11918 {
11919 struct drm_i915_private *dev_priv = dev->dev_private;
11920
11921 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
11922 dev_priv->display.find_dpll = g4x_find_best_dpll;
11923 else if (IS_CHERRYVIEW(dev))
11924 dev_priv->display.find_dpll = chv_find_best_dpll;
11925 else if (IS_VALLEYVIEW(dev))
11926 dev_priv->display.find_dpll = vlv_find_best_dpll;
11927 else if (IS_PINEVIEW(dev))
11928 dev_priv->display.find_dpll = pnv_find_best_dpll;
11929 else
11930 dev_priv->display.find_dpll = i9xx_find_best_dpll;
11931
11932 if (HAS_DDI(dev)) {
11933 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
11934 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11935 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
11936 dev_priv->display.crtc_enable = haswell_crtc_enable;
11937 dev_priv->display.crtc_disable = haswell_crtc_disable;
11938 dev_priv->display.off = haswell_crtc_off;
11939 dev_priv->display.update_primary_plane =
11940 ironlake_update_primary_plane;
11941 } else if (HAS_PCH_SPLIT(dev)) {
11942 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
11943 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11944 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
11945 dev_priv->display.crtc_enable = ironlake_crtc_enable;
11946 dev_priv->display.crtc_disable = ironlake_crtc_disable;
11947 dev_priv->display.off = ironlake_crtc_off;
11948 dev_priv->display.update_primary_plane =
11949 ironlake_update_primary_plane;
11950 } else if (IS_VALLEYVIEW(dev)) {
11951 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11952 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11953 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11954 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11955 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11956 dev_priv->display.off = i9xx_crtc_off;
11957 dev_priv->display.update_primary_plane =
11958 i9xx_update_primary_plane;
11959 } else {
11960 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11961 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11962 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11963 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11964 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11965 dev_priv->display.off = i9xx_crtc_off;
11966 dev_priv->display.update_primary_plane =
11967 i9xx_update_primary_plane;
11968 }
11969
11970 /* Returns the core display clock speed */
11971 if (IS_VALLEYVIEW(dev))
11972 dev_priv->display.get_display_clock_speed =
11973 valleyview_get_display_clock_speed;
11974 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11975 dev_priv->display.get_display_clock_speed =
11976 i945_get_display_clock_speed;
11977 else if (IS_I915G(dev))
11978 dev_priv->display.get_display_clock_speed =
11979 i915_get_display_clock_speed;
11980 else if (IS_I945GM(dev) || IS_845G(dev))
11981 dev_priv->display.get_display_clock_speed =
11982 i9xx_misc_get_display_clock_speed;
11983 else if (IS_PINEVIEW(dev))
11984 dev_priv->display.get_display_clock_speed =
11985 pnv_get_display_clock_speed;
11986 else if (IS_I915GM(dev))
11987 dev_priv->display.get_display_clock_speed =
11988 i915gm_get_display_clock_speed;
11989 else if (IS_I865G(dev))
11990 dev_priv->display.get_display_clock_speed =
11991 i865_get_display_clock_speed;
11992 else if (IS_I85X(dev))
11993 dev_priv->display.get_display_clock_speed =
11994 i855_get_display_clock_speed;
11995 else /* 852, 830 */
11996 dev_priv->display.get_display_clock_speed =
11997 i830_get_display_clock_speed;
11998
11999 if (HAS_PCH_SPLIT(dev)) {
12000 if (IS_GEN5(dev)) {
12001 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12002 dev_priv->display.write_eld = ironlake_write_eld;
12003 } else if (IS_GEN6(dev)) {
12004 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12005 dev_priv->display.write_eld = ironlake_write_eld;
12006 dev_priv->display.modeset_global_resources =
12007 snb_modeset_global_resources;
12008 } else if (IS_IVYBRIDGE(dev)) {
12009 /* FIXME: detect B0+ stepping and use auto training */
12010 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12011 dev_priv->display.write_eld = ironlake_write_eld;
12012 dev_priv->display.modeset_global_resources =
12013 ivb_modeset_global_resources;
12014 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
12015 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12016 dev_priv->display.write_eld = haswell_write_eld;
12017 dev_priv->display.modeset_global_resources =
12018 haswell_modeset_global_resources;
12019 }
12020 } else if (IS_G4X(dev)) {
12021 dev_priv->display.write_eld = g4x_write_eld;
12022 } else if (IS_VALLEYVIEW(dev)) {
12023 dev_priv->display.modeset_global_resources =
12024 valleyview_modeset_global_resources;
12025 dev_priv->display.write_eld = ironlake_write_eld;
12026 }
12027
12028 /* Default just returns -ENODEV to indicate unsupported */
12029 dev_priv->display.queue_flip = intel_default_queue_flip;
12030
12031 switch (INTEL_INFO(dev)->gen) {
12032 case 2:
12033 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12034 break;
12035
12036 case 3:
12037 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12038 break;
12039
12040 case 4:
12041 case 5:
12042 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12043 break;
12044
12045 case 6:
12046 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12047 break;
12048 case 7:
12049 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12050 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12051 break;
12052 }
12053
12054 intel_panel_init_backlight_funcs(dev);
12055 }
12056
12057 /*
12058 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12059 * resume, or other times. This quirk makes sure that's the case for
12060 * affected systems.
12061 */
12062 static void quirk_pipea_force(struct drm_device *dev)
12063 {
12064 struct drm_i915_private *dev_priv = dev->dev_private;
12065
12066 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12067 DRM_INFO("applying pipe a force quirk\n");
12068 }
12069
12070 /*
12071 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12072 */
12073 static void quirk_ssc_force_disable(struct drm_device *dev)
12074 {
12075 struct drm_i915_private *dev_priv = dev->dev_private;
12076 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12077 DRM_INFO("applying lvds SSC disable quirk\n");
12078 }
12079
12080 /*
12081 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12082 * brightness value
12083 */
12084 static void quirk_invert_brightness(struct drm_device *dev)
12085 {
12086 struct drm_i915_private *dev_priv = dev->dev_private;
12087 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12088 DRM_INFO("applying inverted panel brightness quirk\n");
12089 }
12090
12091 struct intel_quirk {
12092 int device;
12093 int subsystem_vendor;
12094 int subsystem_device;
12095 void (*hook)(struct drm_device *dev);
12096 };
12097
12098 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12099 struct intel_dmi_quirk {
12100 void (*hook)(struct drm_device *dev);
12101 const struct dmi_system_id (*dmi_id_list)[];
12102 };
12103
12104 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12105 {
12106 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12107 return 1;
12108 }
12109
12110 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12111 {
12112 .dmi_id_list = &(const struct dmi_system_id[]) {
12113 {
12114 .callback = intel_dmi_reverse_brightness,
12115 .ident = "NCR Corporation",
12116 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12117 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12118 },
12119 },
12120 { } /* terminating entry */
12121 },
12122 .hook = quirk_invert_brightness,
12123 },
12124 };
12125
12126 static struct intel_quirk intel_quirks[] = {
12127 /* HP Mini needs pipe A force quirk (LP: #322104) */
12128 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12129
12130 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12131 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12132
12133 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12134 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12135
12136 /* Lenovo U160 cannot use SSC on LVDS */
12137 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12138
12139 /* Sony Vaio Y cannot use SSC on LVDS */
12140 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12141
12142 /* Acer Aspire 5734Z must invert backlight brightness */
12143 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12144
12145 /* Acer/eMachines G725 */
12146 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12147
12148 /* Acer/eMachines e725 */
12149 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12150
12151 /* Acer/Packard Bell NCL20 */
12152 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12153
12154 /* Acer Aspire 4736Z */
12155 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12156
12157 /* Acer Aspire 5336 */
12158 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12159 };
12160
12161 static void intel_init_quirks(struct drm_device *dev)
12162 {
12163 struct pci_dev *d = dev->pdev;
12164 int i;
12165
12166 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12167 struct intel_quirk *q = &intel_quirks[i];
12168
12169 if (d->device == q->device &&
12170 (d->subsystem_vendor == q->subsystem_vendor ||
12171 q->subsystem_vendor == PCI_ANY_ID) &&
12172 (d->subsystem_device == q->subsystem_device ||
12173 q->subsystem_device == PCI_ANY_ID))
12174 q->hook(dev);
12175 }
12176 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12177 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12178 intel_dmi_quirks[i].hook(dev);
12179 }
12180 }
12181
12182 /* Disable the VGA plane that we never use */
12183 static void i915_disable_vga(struct drm_device *dev)
12184 {
12185 struct drm_i915_private *dev_priv = dev->dev_private;
12186 u8 sr1;
12187 u32 vga_reg = i915_vgacntrl_reg(dev);
12188
12189 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12190 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12191 outb(SR01, VGA_SR_INDEX);
12192 sr1 = inb(VGA_SR_DATA);
12193 outb(sr1 | 1<<5, VGA_SR_DATA);
12194 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12195 udelay(300);
12196
12197 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
12198 POSTING_READ(vga_reg);
12199 }
12200
12201 void intel_modeset_init_hw(struct drm_device *dev)
12202 {
12203 intel_prepare_ddi(dev);
12204
12205 intel_init_clock_gating(dev);
12206
12207 intel_reset_dpio(dev);
12208
12209 intel_enable_gt_powersave(dev);
12210 }
12211
12212 void intel_modeset_suspend_hw(struct drm_device *dev)
12213 {
12214 intel_suspend_hw(dev);
12215 }
12216
12217 void intel_modeset_init(struct drm_device *dev)
12218 {
12219 struct drm_i915_private *dev_priv = dev->dev_private;
12220 int sprite, ret;
12221 enum pipe pipe;
12222 struct intel_crtc *crtc;
12223
12224 drm_mode_config_init(dev);
12225
12226 dev->mode_config.min_width = 0;
12227 dev->mode_config.min_height = 0;
12228
12229 dev->mode_config.preferred_depth = 24;
12230 dev->mode_config.prefer_shadow = 1;
12231
12232 dev->mode_config.funcs = &intel_mode_funcs;
12233
12234 intel_init_quirks(dev);
12235
12236 intel_init_pm(dev);
12237
12238 if (INTEL_INFO(dev)->num_pipes == 0)
12239 return;
12240
12241 intel_init_display(dev);
12242
12243 if (IS_GEN2(dev)) {
12244 dev->mode_config.max_width = 2048;
12245 dev->mode_config.max_height = 2048;
12246 } else if (IS_GEN3(dev)) {
12247 dev->mode_config.max_width = 4096;
12248 dev->mode_config.max_height = 4096;
12249 } else {
12250 dev->mode_config.max_width = 8192;
12251 dev->mode_config.max_height = 8192;
12252 }
12253
12254 if (IS_GEN2(dev)) {
12255 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12256 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12257 } else {
12258 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12259 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12260 }
12261
12262 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12263
12264 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12265 INTEL_INFO(dev)->num_pipes,
12266 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12267
12268 for_each_pipe(pipe) {
12269 intel_crtc_init(dev, pipe);
12270 for_each_sprite(pipe, sprite) {
12271 ret = intel_plane_init(dev, pipe, sprite);
12272 if (ret)
12273 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12274 pipe_name(pipe), sprite_name(pipe, sprite), ret);
12275 }
12276 }
12277
12278 intel_init_dpio(dev);
12279 intel_reset_dpio(dev);
12280
12281 intel_cpu_pll_init(dev);
12282 intel_shared_dpll_init(dev);
12283
12284 /* Just disable it once at startup */
12285 i915_disable_vga(dev);
12286 intel_setup_outputs(dev);
12287
12288 /* Just in case the BIOS is doing something questionable. */
12289 intel_disable_fbc(dev);
12290
12291 drm_modeset_lock_all(dev);
12292 intel_modeset_setup_hw_state(dev, false);
12293 drm_modeset_unlock_all(dev);
12294
12295 for_each_intel_crtc(dev, crtc) {
12296 if (!crtc->active)
12297 continue;
12298
12299 /*
12300 * Note that reserving the BIOS fb up front prevents us
12301 * from stuffing other stolen allocations like the ring
12302 * on top. This prevents some ugliness at boot time, and
12303 * can even allow for smooth boot transitions if the BIOS
12304 * fb is large enough for the active pipe configuration.
12305 */
12306 if (dev_priv->display.get_plane_config) {
12307 dev_priv->display.get_plane_config(crtc,
12308 &crtc->plane_config);
12309 /*
12310 * If the fb is shared between multiple heads, we'll
12311 * just get the first one.
12312 */
12313 intel_find_plane_obj(crtc, &crtc->plane_config);
12314 }
12315 }
12316 }
12317
12318 static void intel_enable_pipe_a(struct drm_device *dev)
12319 {
12320 struct intel_connector *connector;
12321 struct drm_connector *crt = NULL;
12322 struct intel_load_detect_pipe load_detect_temp;
12323 struct drm_modeset_acquire_ctx ctx;
12324
12325 /* We can't just switch on the pipe A, we need to set things up with a
12326 * proper mode and output configuration. As a gross hack, enable pipe A
12327 * by enabling the load detect pipe once. */
12328 list_for_each_entry(connector,
12329 &dev->mode_config.connector_list,
12330 base.head) {
12331 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12332 crt = &connector->base;
12333 break;
12334 }
12335 }
12336
12337 if (!crt)
12338 return;
12339
12340 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx))
12341 intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx);
12342
12343
12344 }
12345
12346 static bool
12347 intel_check_plane_mapping(struct intel_crtc *crtc)
12348 {
12349 struct drm_device *dev = crtc->base.dev;
12350 struct drm_i915_private *dev_priv = dev->dev_private;
12351 u32 reg, val;
12352
12353 if (INTEL_INFO(dev)->num_pipes == 1)
12354 return true;
12355
12356 reg = DSPCNTR(!crtc->plane);
12357 val = I915_READ(reg);
12358
12359 if ((val & DISPLAY_PLANE_ENABLE) &&
12360 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12361 return false;
12362
12363 return true;
12364 }
12365
12366 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12367 {
12368 struct drm_device *dev = crtc->base.dev;
12369 struct drm_i915_private *dev_priv = dev->dev_private;
12370 u32 reg;
12371
12372 /* Clear any frame start delays used for debugging left by the BIOS */
12373 reg = PIPECONF(crtc->config.cpu_transcoder);
12374 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12375
12376 /* restore vblank interrupts to correct state */
12377 if (crtc->active)
12378 drm_vblank_on(dev, crtc->pipe);
12379 else
12380 drm_vblank_off(dev, crtc->pipe);
12381
12382 /* We need to sanitize the plane -> pipe mapping first because this will
12383 * disable the crtc (and hence change the state) if it is wrong. Note
12384 * that gen4+ has a fixed plane -> pipe mapping. */
12385 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12386 struct intel_connector *connector;
12387 bool plane;
12388
12389 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12390 crtc->base.base.id);
12391
12392 /* Pipe has the wrong plane attached and the plane is active.
12393 * Temporarily change the plane mapping and disable everything
12394 * ... */
12395 plane = crtc->plane;
12396 crtc->plane = !plane;
12397 dev_priv->display.crtc_disable(&crtc->base);
12398 crtc->plane = plane;
12399
12400 /* ... and break all links. */
12401 list_for_each_entry(connector, &dev->mode_config.connector_list,
12402 base.head) {
12403 if (connector->encoder->base.crtc != &crtc->base)
12404 continue;
12405
12406 connector->base.dpms = DRM_MODE_DPMS_OFF;
12407 connector->base.encoder = NULL;
12408 }
12409 /* multiple connectors may have the same encoder:
12410 * handle them and break crtc link separately */
12411 list_for_each_entry(connector, &dev->mode_config.connector_list,
12412 base.head)
12413 if (connector->encoder->base.crtc == &crtc->base) {
12414 connector->encoder->base.crtc = NULL;
12415 connector->encoder->connectors_active = false;
12416 }
12417
12418 WARN_ON(crtc->active);
12419 crtc->base.enabled = false;
12420 }
12421
12422 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12423 crtc->pipe == PIPE_A && !crtc->active) {
12424 /* BIOS forgot to enable pipe A, this mostly happens after
12425 * resume. Force-enable the pipe to fix this, the update_dpms
12426 * call below we restore the pipe to the right state, but leave
12427 * the required bits on. */
12428 intel_enable_pipe_a(dev);
12429 }
12430
12431 /* Adjust the state of the output pipe according to whether we
12432 * have active connectors/encoders. */
12433 intel_crtc_update_dpms(&crtc->base);
12434
12435 if (crtc->active != crtc->base.enabled) {
12436 struct intel_encoder *encoder;
12437
12438 /* This can happen either due to bugs in the get_hw_state
12439 * functions or because the pipe is force-enabled due to the
12440 * pipe A quirk. */
12441 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12442 crtc->base.base.id,
12443 crtc->base.enabled ? "enabled" : "disabled",
12444 crtc->active ? "enabled" : "disabled");
12445
12446 crtc->base.enabled = crtc->active;
12447
12448 /* Because we only establish the connector -> encoder ->
12449 * crtc links if something is active, this means the
12450 * crtc is now deactivated. Break the links. connector
12451 * -> encoder links are only establish when things are
12452 * actually up, hence no need to break them. */
12453 WARN_ON(crtc->active);
12454
12455 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12456 WARN_ON(encoder->connectors_active);
12457 encoder->base.crtc = NULL;
12458 }
12459 }
12460
12461 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
12462 /*
12463 * We start out with underrun reporting disabled to avoid races.
12464 * For correct bookkeeping mark this on active crtcs.
12465 *
12466 * Also on gmch platforms we dont have any hardware bits to
12467 * disable the underrun reporting. Which means we need to start
12468 * out with underrun reporting disabled also on inactive pipes,
12469 * since otherwise we'll complain about the garbage we read when
12470 * e.g. coming up after runtime pm.
12471 *
12472 * No protection against concurrent access is required - at
12473 * worst a fifo underrun happens which also sets this to false.
12474 */
12475 crtc->cpu_fifo_underrun_disabled = true;
12476 crtc->pch_fifo_underrun_disabled = true;
12477
12478 update_scanline_offset(crtc);
12479 }
12480 }
12481
12482 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12483 {
12484 struct intel_connector *connector;
12485 struct drm_device *dev = encoder->base.dev;
12486
12487 /* We need to check both for a crtc link (meaning that the
12488 * encoder is active and trying to read from a pipe) and the
12489 * pipe itself being active. */
12490 bool has_active_crtc = encoder->base.crtc &&
12491 to_intel_crtc(encoder->base.crtc)->active;
12492
12493 if (encoder->connectors_active && !has_active_crtc) {
12494 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12495 encoder->base.base.id,
12496 encoder->base.name);
12497
12498 /* Connector is active, but has no active pipe. This is
12499 * fallout from our resume register restoring. Disable
12500 * the encoder manually again. */
12501 if (encoder->base.crtc) {
12502 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12503 encoder->base.base.id,
12504 encoder->base.name);
12505 encoder->disable(encoder);
12506 }
12507 encoder->base.crtc = NULL;
12508 encoder->connectors_active = false;
12509
12510 /* Inconsistent output/port/pipe state happens presumably due to
12511 * a bug in one of the get_hw_state functions. Or someplace else
12512 * in our code, like the register restore mess on resume. Clamp
12513 * things to off as a safer default. */
12514 list_for_each_entry(connector,
12515 &dev->mode_config.connector_list,
12516 base.head) {
12517 if (connector->encoder != encoder)
12518 continue;
12519 connector->base.dpms = DRM_MODE_DPMS_OFF;
12520 connector->base.encoder = NULL;
12521 }
12522 }
12523 /* Enabled encoders without active connectors will be fixed in
12524 * the crtc fixup. */
12525 }
12526
12527 void i915_redisable_vga_power_on(struct drm_device *dev)
12528 {
12529 struct drm_i915_private *dev_priv = dev->dev_private;
12530 u32 vga_reg = i915_vgacntrl_reg(dev);
12531
12532 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
12533 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12534 i915_disable_vga(dev);
12535 }
12536 }
12537
12538 void i915_redisable_vga(struct drm_device *dev)
12539 {
12540 struct drm_i915_private *dev_priv = dev->dev_private;
12541
12542 /* This function can be called both from intel_modeset_setup_hw_state or
12543 * at a very early point in our resume sequence, where the power well
12544 * structures are not yet restored. Since this function is at a very
12545 * paranoid "someone might have enabled VGA while we were not looking"
12546 * level, just check if the power well is enabled instead of trying to
12547 * follow the "don't touch the power well if we don't need it" policy
12548 * the rest of the driver uses. */
12549 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
12550 return;
12551
12552 i915_redisable_vga_power_on(dev);
12553 }
12554
12555 static bool primary_get_hw_state(struct intel_crtc *crtc)
12556 {
12557 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
12558
12559 if (!crtc->active)
12560 return false;
12561
12562 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
12563 }
12564
12565 static void intel_modeset_readout_hw_state(struct drm_device *dev)
12566 {
12567 struct drm_i915_private *dev_priv = dev->dev_private;
12568 enum pipe pipe;
12569 struct intel_crtc *crtc;
12570 struct intel_encoder *encoder;
12571 struct intel_connector *connector;
12572 int i;
12573
12574 for_each_intel_crtc(dev, crtc) {
12575 memset(&crtc->config, 0, sizeof(crtc->config));
12576
12577 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
12578
12579 crtc->active = dev_priv->display.get_pipe_config(crtc,
12580 &crtc->config);
12581
12582 crtc->base.enabled = crtc->active;
12583 crtc->primary_enabled = primary_get_hw_state(crtc);
12584
12585 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
12586 crtc->base.base.id,
12587 crtc->active ? "enabled" : "disabled");
12588 }
12589
12590 /* FIXME: Smash this into the new shared dpll infrastructure. */
12591 if (HAS_DDI(dev))
12592 intel_ddi_setup_hw_pll_state(dev);
12593
12594 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12595 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12596
12597 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
12598 pll->active = 0;
12599 for_each_intel_crtc(dev, crtc) {
12600 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12601 pll->active++;
12602 }
12603 pll->refcount = pll->active;
12604
12605 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
12606 pll->name, pll->refcount, pll->on);
12607 }
12608
12609 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12610 base.head) {
12611 pipe = 0;
12612
12613 if (encoder->get_hw_state(encoder, &pipe)) {
12614 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12615 encoder->base.crtc = &crtc->base;
12616 encoder->get_config(encoder, &crtc->config);
12617 } else {
12618 encoder->base.crtc = NULL;
12619 }
12620
12621 encoder->connectors_active = false;
12622 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
12623 encoder->base.base.id,
12624 encoder->base.name,
12625 encoder->base.crtc ? "enabled" : "disabled",
12626 pipe_name(pipe));
12627 }
12628
12629 list_for_each_entry(connector, &dev->mode_config.connector_list,
12630 base.head) {
12631 if (connector->get_hw_state(connector)) {
12632 connector->base.dpms = DRM_MODE_DPMS_ON;
12633 connector->encoder->connectors_active = true;
12634 connector->base.encoder = &connector->encoder->base;
12635 } else {
12636 connector->base.dpms = DRM_MODE_DPMS_OFF;
12637 connector->base.encoder = NULL;
12638 }
12639 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
12640 connector->base.base.id,
12641 connector->base.name,
12642 connector->base.encoder ? "enabled" : "disabled");
12643 }
12644 }
12645
12646 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
12647 * and i915 state tracking structures. */
12648 void intel_modeset_setup_hw_state(struct drm_device *dev,
12649 bool force_restore)
12650 {
12651 struct drm_i915_private *dev_priv = dev->dev_private;
12652 enum pipe pipe;
12653 struct intel_crtc *crtc;
12654 struct intel_encoder *encoder;
12655 int i;
12656
12657 intel_modeset_readout_hw_state(dev);
12658
12659 /*
12660 * Now that we have the config, copy it to each CRTC struct
12661 * Note that this could go away if we move to using crtc_config
12662 * checking everywhere.
12663 */
12664 for_each_intel_crtc(dev, crtc) {
12665 if (crtc->active && i915.fastboot) {
12666 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
12667 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
12668 crtc->base.base.id);
12669 drm_mode_debug_printmodeline(&crtc->base.mode);
12670 }
12671 }
12672
12673 /* HW state is read out, now we need to sanitize this mess. */
12674 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12675 base.head) {
12676 intel_sanitize_encoder(encoder);
12677 }
12678
12679 for_each_pipe(pipe) {
12680 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12681 intel_sanitize_crtc(crtc);
12682 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
12683 }
12684
12685 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12686 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12687
12688 if (!pll->on || pll->active)
12689 continue;
12690
12691 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
12692
12693 pll->disable(dev_priv, pll);
12694 pll->on = false;
12695 }
12696
12697 if (HAS_PCH_SPLIT(dev))
12698 ilk_wm_get_hw_state(dev);
12699
12700 if (force_restore) {
12701 i915_redisable_vga(dev);
12702
12703 /*
12704 * We need to use raw interfaces for restoring state to avoid
12705 * checking (bogus) intermediate states.
12706 */
12707 for_each_pipe(pipe) {
12708 struct drm_crtc *crtc =
12709 dev_priv->pipe_to_crtc_mapping[pipe];
12710
12711 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
12712 crtc->primary->fb);
12713 }
12714 } else {
12715 intel_modeset_update_staged_output_state(dev);
12716 }
12717
12718 intel_modeset_check_state(dev);
12719 }
12720
12721 void intel_modeset_gem_init(struct drm_device *dev)
12722 {
12723 struct drm_crtc *c;
12724 struct intel_framebuffer *fb;
12725
12726 mutex_lock(&dev->struct_mutex);
12727 intel_init_gt_powersave(dev);
12728 mutex_unlock(&dev->struct_mutex);
12729
12730 intel_modeset_init_hw(dev);
12731
12732 intel_setup_overlay(dev);
12733
12734 /*
12735 * Make sure any fbs we allocated at startup are properly
12736 * pinned & fenced. When we do the allocation it's too early
12737 * for this.
12738 */
12739 mutex_lock(&dev->struct_mutex);
12740 for_each_crtc(dev, c) {
12741 if (!c->primary->fb)
12742 continue;
12743
12744 fb = to_intel_framebuffer(c->primary->fb);
12745 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
12746 DRM_ERROR("failed to pin boot fb on pipe %d\n",
12747 to_intel_crtc(c)->pipe);
12748 drm_framebuffer_unreference(c->primary->fb);
12749 c->primary->fb = NULL;
12750 }
12751 }
12752 mutex_unlock(&dev->struct_mutex);
12753 }
12754
12755 void intel_connector_unregister(struct intel_connector *intel_connector)
12756 {
12757 struct drm_connector *connector = &intel_connector->base;
12758
12759 intel_panel_destroy_backlight(connector);
12760 drm_sysfs_connector_remove(connector);
12761 }
12762
12763 void intel_modeset_cleanup(struct drm_device *dev)
12764 {
12765 struct drm_i915_private *dev_priv = dev->dev_private;
12766 struct drm_crtc *crtc;
12767 struct drm_connector *connector;
12768
12769 /*
12770 * Interrupts and polling as the first thing to avoid creating havoc.
12771 * Too much stuff here (turning of rps, connectors, ...) would
12772 * experience fancy races otherwise.
12773 */
12774 drm_irq_uninstall(dev);
12775 cancel_work_sync(&dev_priv->hotplug_work);
12776 /*
12777 * Due to the hpd irq storm handling the hotplug work can re-arm the
12778 * poll handlers. Hence disable polling after hpd handling is shut down.
12779 */
12780 drm_kms_helper_poll_fini(dev);
12781
12782 mutex_lock(&dev->struct_mutex);
12783
12784 intel_unregister_dsm_handler();
12785
12786 for_each_crtc(dev, crtc) {
12787 /* Skip inactive CRTCs */
12788 if (!crtc->primary->fb)
12789 continue;
12790
12791 intel_increase_pllclock(crtc);
12792 }
12793
12794 intel_disable_fbc(dev);
12795
12796 intel_disable_gt_powersave(dev);
12797
12798 ironlake_teardown_rc6(dev);
12799
12800 mutex_unlock(&dev->struct_mutex);
12801
12802 /* flush any delayed tasks or pending work */
12803 flush_scheduled_work();
12804
12805 /* destroy the backlight and sysfs files before encoders/connectors */
12806 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12807 struct intel_connector *intel_connector;
12808
12809 intel_connector = to_intel_connector(connector);
12810 intel_connector->unregister(intel_connector);
12811 }
12812
12813 drm_mode_config_cleanup(dev);
12814
12815 intel_cleanup_overlay(dev);
12816
12817 mutex_lock(&dev->struct_mutex);
12818 intel_cleanup_gt_powersave(dev);
12819 mutex_unlock(&dev->struct_mutex);
12820 }
12821
12822 /*
12823 * Return which encoder is currently attached for connector.
12824 */
12825 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
12826 {
12827 return &intel_attached_encoder(connector)->base;
12828 }
12829
12830 void intel_connector_attach_encoder(struct intel_connector *connector,
12831 struct intel_encoder *encoder)
12832 {
12833 connector->encoder = encoder;
12834 drm_mode_connector_attach_encoder(&connector->base,
12835 &encoder->base);
12836 }
12837
12838 /*
12839 * set vga decode state - true == enable VGA decode
12840 */
12841 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
12842 {
12843 struct drm_i915_private *dev_priv = dev->dev_private;
12844 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
12845 u16 gmch_ctrl;
12846
12847 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
12848 DRM_ERROR("failed to read control word\n");
12849 return -EIO;
12850 }
12851
12852 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
12853 return 0;
12854
12855 if (state)
12856 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
12857 else
12858 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
12859
12860 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
12861 DRM_ERROR("failed to write control word\n");
12862 return -EIO;
12863 }
12864
12865 return 0;
12866 }
12867
12868 struct intel_display_error_state {
12869
12870 u32 power_well_driver;
12871
12872 int num_transcoders;
12873
12874 struct intel_cursor_error_state {
12875 u32 control;
12876 u32 position;
12877 u32 base;
12878 u32 size;
12879 } cursor[I915_MAX_PIPES];
12880
12881 struct intel_pipe_error_state {
12882 bool power_domain_on;
12883 u32 source;
12884 u32 stat;
12885 } pipe[I915_MAX_PIPES];
12886
12887 struct intel_plane_error_state {
12888 u32 control;
12889 u32 stride;
12890 u32 size;
12891 u32 pos;
12892 u32 addr;
12893 u32 surface;
12894 u32 tile_offset;
12895 } plane[I915_MAX_PIPES];
12896
12897 struct intel_transcoder_error_state {
12898 bool power_domain_on;
12899 enum transcoder cpu_transcoder;
12900
12901 u32 conf;
12902
12903 u32 htotal;
12904 u32 hblank;
12905 u32 hsync;
12906 u32 vtotal;
12907 u32 vblank;
12908 u32 vsync;
12909 } transcoder[4];
12910 };
12911
12912 struct intel_display_error_state *
12913 intel_display_capture_error_state(struct drm_device *dev)
12914 {
12915 struct drm_i915_private *dev_priv = dev->dev_private;
12916 struct intel_display_error_state *error;
12917 int transcoders[] = {
12918 TRANSCODER_A,
12919 TRANSCODER_B,
12920 TRANSCODER_C,
12921 TRANSCODER_EDP,
12922 };
12923 int i;
12924
12925 if (INTEL_INFO(dev)->num_pipes == 0)
12926 return NULL;
12927
12928 error = kzalloc(sizeof(*error), GFP_ATOMIC);
12929 if (error == NULL)
12930 return NULL;
12931
12932 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12933 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
12934
12935 for_each_pipe(i) {
12936 error->pipe[i].power_domain_on =
12937 intel_display_power_enabled_sw(dev_priv,
12938 POWER_DOMAIN_PIPE(i));
12939 if (!error->pipe[i].power_domain_on)
12940 continue;
12941
12942 error->cursor[i].control = I915_READ(CURCNTR(i));
12943 error->cursor[i].position = I915_READ(CURPOS(i));
12944 error->cursor[i].base = I915_READ(CURBASE(i));
12945
12946 error->plane[i].control = I915_READ(DSPCNTR(i));
12947 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
12948 if (INTEL_INFO(dev)->gen <= 3) {
12949 error->plane[i].size = I915_READ(DSPSIZE(i));
12950 error->plane[i].pos = I915_READ(DSPPOS(i));
12951 }
12952 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12953 error->plane[i].addr = I915_READ(DSPADDR(i));
12954 if (INTEL_INFO(dev)->gen >= 4) {
12955 error->plane[i].surface = I915_READ(DSPSURF(i));
12956 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
12957 }
12958
12959 error->pipe[i].source = I915_READ(PIPESRC(i));
12960
12961 if (!HAS_PCH_SPLIT(dev))
12962 error->pipe[i].stat = I915_READ(PIPESTAT(i));
12963 }
12964
12965 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
12966 if (HAS_DDI(dev_priv->dev))
12967 error->num_transcoders++; /* Account for eDP. */
12968
12969 for (i = 0; i < error->num_transcoders; i++) {
12970 enum transcoder cpu_transcoder = transcoders[i];
12971
12972 error->transcoder[i].power_domain_on =
12973 intel_display_power_enabled_sw(dev_priv,
12974 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12975 if (!error->transcoder[i].power_domain_on)
12976 continue;
12977
12978 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12979
12980 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12981 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12982 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12983 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12984 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12985 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12986 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12987 }
12988
12989 return error;
12990 }
12991
12992 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12993
12994 void
12995 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12996 struct drm_device *dev,
12997 struct intel_display_error_state *error)
12998 {
12999 int i;
13000
13001 if (!error)
13002 return;
13003
13004 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13005 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13006 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13007 error->power_well_driver);
13008 for_each_pipe(i) {
13009 err_printf(m, "Pipe [%d]:\n", i);
13010 err_printf(m, " Power: %s\n",
13011 error->pipe[i].power_domain_on ? "on" : "off");
13012 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13013 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13014
13015 err_printf(m, "Plane [%d]:\n", i);
13016 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13017 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13018 if (INTEL_INFO(dev)->gen <= 3) {
13019 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13020 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13021 }
13022 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13023 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13024 if (INTEL_INFO(dev)->gen >= 4) {
13025 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13026 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13027 }
13028
13029 err_printf(m, "Cursor [%d]:\n", i);
13030 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13031 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13032 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13033 }
13034
13035 for (i = 0; i < error->num_transcoders; i++) {
13036 err_printf(m, "CPU transcoder: %c\n",
13037 transcoder_name(error->transcoder[i].cpu_transcoder));
13038 err_printf(m, " Power: %s\n",
13039 error->transcoder[i].power_domain_on ? "on" : "off");
13040 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13041 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13042 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13043 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13044 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13045 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13046 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13047 }
13048 }
Ubuntu Artful kernel mirror