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Merge tag 'ext4_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso...
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47 #include <linux/reservation.h>
48 #include <linux/dma-buf.h>
49
50 /* Primary plane formats for gen <= 3 */
51 static const uint32_t i8xx_primary_formats[] = {
52 DRM_FORMAT_C8,
53 DRM_FORMAT_RGB565,
54 DRM_FORMAT_XRGB1555,
55 DRM_FORMAT_XRGB8888,
56 };
57
58 /* Primary plane formats for gen >= 4 */
59 static const uint32_t i965_primary_formats[] = {
60 DRM_FORMAT_C8,
61 DRM_FORMAT_RGB565,
62 DRM_FORMAT_XRGB8888,
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_XRGB2101010,
65 DRM_FORMAT_XBGR2101010,
66 };
67
68 static const uint32_t skl_primary_formats[] = {
69 DRM_FORMAT_C8,
70 DRM_FORMAT_RGB565,
71 DRM_FORMAT_XRGB8888,
72 DRM_FORMAT_XBGR8888,
73 DRM_FORMAT_ARGB8888,
74 DRM_FORMAT_ABGR8888,
75 DRM_FORMAT_XRGB2101010,
76 DRM_FORMAT_XBGR2101010,
77 DRM_FORMAT_YUYV,
78 DRM_FORMAT_YVYU,
79 DRM_FORMAT_UYVY,
80 DRM_FORMAT_VYUY,
81 };
82
83 /* Cursor formats */
84 static const uint32_t intel_cursor_formats[] = {
85 DRM_FORMAT_ARGB8888,
86 };
87
88 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
89
90 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
91 struct intel_crtc_state *pipe_config);
92 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
93 struct intel_crtc_state *pipe_config);
94
95 static int intel_framebuffer_init(struct drm_device *dev,
96 struct intel_framebuffer *ifb,
97 struct drm_mode_fb_cmd2 *mode_cmd,
98 struct drm_i915_gem_object *obj);
99 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
100 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
101 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
102 struct intel_link_m_n *m_n,
103 struct intel_link_m_n *m2_n2);
104 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
105 static void haswell_set_pipeconf(struct drm_crtc *crtc);
106 static void intel_set_pipe_csc(struct drm_crtc *crtc);
107 static void vlv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void chv_prepare_pll(struct intel_crtc *crtc,
110 const struct intel_crtc_state *pipe_config);
111 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
112 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
113 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
114 struct intel_crtc_state *crtc_state);
115 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
116 int num_connectors);
117 static void skylake_pfit_enable(struct intel_crtc *crtc);
118 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
119 static void ironlake_pfit_enable(struct intel_crtc *crtc);
120 static void intel_modeset_setup_hw_state(struct drm_device *dev);
121 static void intel_pre_disable_primary(struct drm_crtc *crtc);
122
123 typedef struct {
124 int min, max;
125 } intel_range_t;
126
127 typedef struct {
128 int dot_limit;
129 int p2_slow, p2_fast;
130 } intel_p2_t;
131
132 typedef struct intel_limit intel_limit_t;
133 struct intel_limit {
134 intel_range_t dot, vco, n, m, m1, m2, p, p1;
135 intel_p2_t p2;
136 };
137
138 /* returns HPLL frequency in kHz */
139 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
140 {
141 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
142
143 /* Obtain SKU information */
144 mutex_lock(&dev_priv->sb_lock);
145 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
146 CCK_FUSE_HPLL_FREQ_MASK;
147 mutex_unlock(&dev_priv->sb_lock);
148
149 return vco_freq[hpll_freq] * 1000;
150 }
151
152 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
153 const char *name, u32 reg)
154 {
155 u32 val;
156 int divider;
157
158 if (dev_priv->hpll_freq == 0)
159 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
160
161 mutex_lock(&dev_priv->sb_lock);
162 val = vlv_cck_read(dev_priv, reg);
163 mutex_unlock(&dev_priv->sb_lock);
164
165 divider = val & CCK_FREQUENCY_VALUES;
166
167 WARN((val & CCK_FREQUENCY_STATUS) !=
168 (divider << CCK_FREQUENCY_STATUS_SHIFT),
169 "%s change in progress\n", name);
170
171 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
172 }
173
174 int
175 intel_pch_rawclk(struct drm_device *dev)
176 {
177 struct drm_i915_private *dev_priv = dev->dev_private;
178
179 WARN_ON(!HAS_PCH_SPLIT(dev));
180
181 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
182 }
183
184 /* hrawclock is 1/4 the FSB frequency */
185 int intel_hrawclk(struct drm_device *dev)
186 {
187 struct drm_i915_private *dev_priv = dev->dev_private;
188 uint32_t clkcfg;
189
190 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
191 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
192 return 200;
193
194 clkcfg = I915_READ(CLKCFG);
195 switch (clkcfg & CLKCFG_FSB_MASK) {
196 case CLKCFG_FSB_400:
197 return 100;
198 case CLKCFG_FSB_533:
199 return 133;
200 case CLKCFG_FSB_667:
201 return 166;
202 case CLKCFG_FSB_800:
203 return 200;
204 case CLKCFG_FSB_1067:
205 return 266;
206 case CLKCFG_FSB_1333:
207 return 333;
208 /* these two are just a guess; one of them might be right */
209 case CLKCFG_FSB_1600:
210 case CLKCFG_FSB_1600_ALT:
211 return 400;
212 default:
213 return 133;
214 }
215 }
216
217 static void intel_update_czclk(struct drm_i915_private *dev_priv)
218 {
219 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
220 return;
221
222 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
223 CCK_CZ_CLOCK_CONTROL);
224
225 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
226 }
227
228 static inline u32 /* units of 100MHz */
229 intel_fdi_link_freq(struct drm_device *dev)
230 {
231 if (IS_GEN5(dev)) {
232 struct drm_i915_private *dev_priv = dev->dev_private;
233 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
234 } else
235 return 27;
236 }
237
238 static const intel_limit_t intel_limits_i8xx_dac = {
239 .dot = { .min = 25000, .max = 350000 },
240 .vco = { .min = 908000, .max = 1512000 },
241 .n = { .min = 2, .max = 16 },
242 .m = { .min = 96, .max = 140 },
243 .m1 = { .min = 18, .max = 26 },
244 .m2 = { .min = 6, .max = 16 },
245 .p = { .min = 4, .max = 128 },
246 .p1 = { .min = 2, .max = 33 },
247 .p2 = { .dot_limit = 165000,
248 .p2_slow = 4, .p2_fast = 2 },
249 };
250
251 static const intel_limit_t intel_limits_i8xx_dvo = {
252 .dot = { .min = 25000, .max = 350000 },
253 .vco = { .min = 908000, .max = 1512000 },
254 .n = { .min = 2, .max = 16 },
255 .m = { .min = 96, .max = 140 },
256 .m1 = { .min = 18, .max = 26 },
257 .m2 = { .min = 6, .max = 16 },
258 .p = { .min = 4, .max = 128 },
259 .p1 = { .min = 2, .max = 33 },
260 .p2 = { .dot_limit = 165000,
261 .p2_slow = 4, .p2_fast = 4 },
262 };
263
264 static const intel_limit_t intel_limits_i8xx_lvds = {
265 .dot = { .min = 25000, .max = 350000 },
266 .vco = { .min = 908000, .max = 1512000 },
267 .n = { .min = 2, .max = 16 },
268 .m = { .min = 96, .max = 140 },
269 .m1 = { .min = 18, .max = 26 },
270 .m2 = { .min = 6, .max = 16 },
271 .p = { .min = 4, .max = 128 },
272 .p1 = { .min = 1, .max = 6 },
273 .p2 = { .dot_limit = 165000,
274 .p2_slow = 14, .p2_fast = 7 },
275 };
276
277 static const intel_limit_t intel_limits_i9xx_sdvo = {
278 .dot = { .min = 20000, .max = 400000 },
279 .vco = { .min = 1400000, .max = 2800000 },
280 .n = { .min = 1, .max = 6 },
281 .m = { .min = 70, .max = 120 },
282 .m1 = { .min = 8, .max = 18 },
283 .m2 = { .min = 3, .max = 7 },
284 .p = { .min = 5, .max = 80 },
285 .p1 = { .min = 1, .max = 8 },
286 .p2 = { .dot_limit = 200000,
287 .p2_slow = 10, .p2_fast = 5 },
288 };
289
290 static const intel_limit_t intel_limits_i9xx_lvds = {
291 .dot = { .min = 20000, .max = 400000 },
292 .vco = { .min = 1400000, .max = 2800000 },
293 .n = { .min = 1, .max = 6 },
294 .m = { .min = 70, .max = 120 },
295 .m1 = { .min = 8, .max = 18 },
296 .m2 = { .min = 3, .max = 7 },
297 .p = { .min = 7, .max = 98 },
298 .p1 = { .min = 1, .max = 8 },
299 .p2 = { .dot_limit = 112000,
300 .p2_slow = 14, .p2_fast = 7 },
301 };
302
303
304 static const intel_limit_t intel_limits_g4x_sdvo = {
305 .dot = { .min = 25000, .max = 270000 },
306 .vco = { .min = 1750000, .max = 3500000},
307 .n = { .min = 1, .max = 4 },
308 .m = { .min = 104, .max = 138 },
309 .m1 = { .min = 17, .max = 23 },
310 .m2 = { .min = 5, .max = 11 },
311 .p = { .min = 10, .max = 30 },
312 .p1 = { .min = 1, .max = 3},
313 .p2 = { .dot_limit = 270000,
314 .p2_slow = 10,
315 .p2_fast = 10
316 },
317 };
318
319 static const intel_limit_t intel_limits_g4x_hdmi = {
320 .dot = { .min = 22000, .max = 400000 },
321 .vco = { .min = 1750000, .max = 3500000},
322 .n = { .min = 1, .max = 4 },
323 .m = { .min = 104, .max = 138 },
324 .m1 = { .min = 16, .max = 23 },
325 .m2 = { .min = 5, .max = 11 },
326 .p = { .min = 5, .max = 80 },
327 .p1 = { .min = 1, .max = 8},
328 .p2 = { .dot_limit = 165000,
329 .p2_slow = 10, .p2_fast = 5 },
330 };
331
332 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
333 .dot = { .min = 20000, .max = 115000 },
334 .vco = { .min = 1750000, .max = 3500000 },
335 .n = { .min = 1, .max = 3 },
336 .m = { .min = 104, .max = 138 },
337 .m1 = { .min = 17, .max = 23 },
338 .m2 = { .min = 5, .max = 11 },
339 .p = { .min = 28, .max = 112 },
340 .p1 = { .min = 2, .max = 8 },
341 .p2 = { .dot_limit = 0,
342 .p2_slow = 14, .p2_fast = 14
343 },
344 };
345
346 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
347 .dot = { .min = 80000, .max = 224000 },
348 .vco = { .min = 1750000, .max = 3500000 },
349 .n = { .min = 1, .max = 3 },
350 .m = { .min = 104, .max = 138 },
351 .m1 = { .min = 17, .max = 23 },
352 .m2 = { .min = 5, .max = 11 },
353 .p = { .min = 14, .max = 42 },
354 .p1 = { .min = 2, .max = 6 },
355 .p2 = { .dot_limit = 0,
356 .p2_slow = 7, .p2_fast = 7
357 },
358 };
359
360 static const intel_limit_t intel_limits_pineview_sdvo = {
361 .dot = { .min = 20000, .max = 400000},
362 .vco = { .min = 1700000, .max = 3500000 },
363 /* Pineview's Ncounter is a ring counter */
364 .n = { .min = 3, .max = 6 },
365 .m = { .min = 2, .max = 256 },
366 /* Pineview only has one combined m divider, which we treat as m2. */
367 .m1 = { .min = 0, .max = 0 },
368 .m2 = { .min = 0, .max = 254 },
369 .p = { .min = 5, .max = 80 },
370 .p1 = { .min = 1, .max = 8 },
371 .p2 = { .dot_limit = 200000,
372 .p2_slow = 10, .p2_fast = 5 },
373 };
374
375 static const intel_limit_t intel_limits_pineview_lvds = {
376 .dot = { .min = 20000, .max = 400000 },
377 .vco = { .min = 1700000, .max = 3500000 },
378 .n = { .min = 3, .max = 6 },
379 .m = { .min = 2, .max = 256 },
380 .m1 = { .min = 0, .max = 0 },
381 .m2 = { .min = 0, .max = 254 },
382 .p = { .min = 7, .max = 112 },
383 .p1 = { .min = 1, .max = 8 },
384 .p2 = { .dot_limit = 112000,
385 .p2_slow = 14, .p2_fast = 14 },
386 };
387
388 /* Ironlake / Sandybridge
389 *
390 * We calculate clock using (register_value + 2) for N/M1/M2, so here
391 * the range value for them is (actual_value - 2).
392 */
393 static const intel_limit_t intel_limits_ironlake_dac = {
394 .dot = { .min = 25000, .max = 350000 },
395 .vco = { .min = 1760000, .max = 3510000 },
396 .n = { .min = 1, .max = 5 },
397 .m = { .min = 79, .max = 127 },
398 .m1 = { .min = 12, .max = 22 },
399 .m2 = { .min = 5, .max = 9 },
400 .p = { .min = 5, .max = 80 },
401 .p1 = { .min = 1, .max = 8 },
402 .p2 = { .dot_limit = 225000,
403 .p2_slow = 10, .p2_fast = 5 },
404 };
405
406 static const intel_limit_t intel_limits_ironlake_single_lvds = {
407 .dot = { .min = 25000, .max = 350000 },
408 .vco = { .min = 1760000, .max = 3510000 },
409 .n = { .min = 1, .max = 3 },
410 .m = { .min = 79, .max = 118 },
411 .m1 = { .min = 12, .max = 22 },
412 .m2 = { .min = 5, .max = 9 },
413 .p = { .min = 28, .max = 112 },
414 .p1 = { .min = 2, .max = 8 },
415 .p2 = { .dot_limit = 225000,
416 .p2_slow = 14, .p2_fast = 14 },
417 };
418
419 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
420 .dot = { .min = 25000, .max = 350000 },
421 .vco = { .min = 1760000, .max = 3510000 },
422 .n = { .min = 1, .max = 3 },
423 .m = { .min = 79, .max = 127 },
424 .m1 = { .min = 12, .max = 22 },
425 .m2 = { .min = 5, .max = 9 },
426 .p = { .min = 14, .max = 56 },
427 .p1 = { .min = 2, .max = 8 },
428 .p2 = { .dot_limit = 225000,
429 .p2_slow = 7, .p2_fast = 7 },
430 };
431
432 /* LVDS 100mhz refclk limits. */
433 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
434 .dot = { .min = 25000, .max = 350000 },
435 .vco = { .min = 1760000, .max = 3510000 },
436 .n = { .min = 1, .max = 2 },
437 .m = { .min = 79, .max = 126 },
438 .m1 = { .min = 12, .max = 22 },
439 .m2 = { .min = 5, .max = 9 },
440 .p = { .min = 28, .max = 112 },
441 .p1 = { .min = 2, .max = 8 },
442 .p2 = { .dot_limit = 225000,
443 .p2_slow = 14, .p2_fast = 14 },
444 };
445
446 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
447 .dot = { .min = 25000, .max = 350000 },
448 .vco = { .min = 1760000, .max = 3510000 },
449 .n = { .min = 1, .max = 3 },
450 .m = { .min = 79, .max = 126 },
451 .m1 = { .min = 12, .max = 22 },
452 .m2 = { .min = 5, .max = 9 },
453 .p = { .min = 14, .max = 42 },
454 .p1 = { .min = 2, .max = 6 },
455 .p2 = { .dot_limit = 225000,
456 .p2_slow = 7, .p2_fast = 7 },
457 };
458
459 static const intel_limit_t intel_limits_vlv = {
460 /*
461 * These are the data rate limits (measured in fast clocks)
462 * since those are the strictest limits we have. The fast
463 * clock and actual rate limits are more relaxed, so checking
464 * them would make no difference.
465 */
466 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
467 .vco = { .min = 4000000, .max = 6000000 },
468 .n = { .min = 1, .max = 7 },
469 .m1 = { .min = 2, .max = 3 },
470 .m2 = { .min = 11, .max = 156 },
471 .p1 = { .min = 2, .max = 3 },
472 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
473 };
474
475 static const intel_limit_t intel_limits_chv = {
476 /*
477 * These are the data rate limits (measured in fast clocks)
478 * since those are the strictest limits we have. The fast
479 * clock and actual rate limits are more relaxed, so checking
480 * them would make no difference.
481 */
482 .dot = { .min = 25000 * 5, .max = 540000 * 5},
483 .vco = { .min = 4800000, .max = 6480000 },
484 .n = { .min = 1, .max = 1 },
485 .m1 = { .min = 2, .max = 2 },
486 .m2 = { .min = 24 << 22, .max = 175 << 22 },
487 .p1 = { .min = 2, .max = 4 },
488 .p2 = { .p2_slow = 1, .p2_fast = 14 },
489 };
490
491 static const intel_limit_t intel_limits_bxt = {
492 /* FIXME: find real dot limits */
493 .dot = { .min = 0, .max = INT_MAX },
494 .vco = { .min = 4800000, .max = 6700000 },
495 .n = { .min = 1, .max = 1 },
496 .m1 = { .min = 2, .max = 2 },
497 /* FIXME: find real m2 limits */
498 .m2 = { .min = 2 << 22, .max = 255 << 22 },
499 .p1 = { .min = 2, .max = 4 },
500 .p2 = { .p2_slow = 1, .p2_fast = 20 },
501 };
502
503 static bool
504 needs_modeset(struct drm_crtc_state *state)
505 {
506 return drm_atomic_crtc_needs_modeset(state);
507 }
508
509 /**
510 * Returns whether any output on the specified pipe is of the specified type
511 */
512 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
513 {
514 struct drm_device *dev = crtc->base.dev;
515 struct intel_encoder *encoder;
516
517 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
518 if (encoder->type == type)
519 return true;
520
521 return false;
522 }
523
524 /**
525 * Returns whether any output on the specified pipe will have the specified
526 * type after a staged modeset is complete, i.e., the same as
527 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
528 * encoder->crtc.
529 */
530 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
531 int type)
532 {
533 struct drm_atomic_state *state = crtc_state->base.state;
534 struct drm_connector *connector;
535 struct drm_connector_state *connector_state;
536 struct intel_encoder *encoder;
537 int i, num_connectors = 0;
538
539 for_each_connector_in_state(state, connector, connector_state, i) {
540 if (connector_state->crtc != crtc_state->base.crtc)
541 continue;
542
543 num_connectors++;
544
545 encoder = to_intel_encoder(connector_state->best_encoder);
546 if (encoder->type == type)
547 return true;
548 }
549
550 WARN_ON(num_connectors == 0);
551
552 return false;
553 }
554
555 static const intel_limit_t *
556 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
557 {
558 struct drm_device *dev = crtc_state->base.crtc->dev;
559 const intel_limit_t *limit;
560
561 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
562 if (intel_is_dual_link_lvds(dev)) {
563 if (refclk == 100000)
564 limit = &intel_limits_ironlake_dual_lvds_100m;
565 else
566 limit = &intel_limits_ironlake_dual_lvds;
567 } else {
568 if (refclk == 100000)
569 limit = &intel_limits_ironlake_single_lvds_100m;
570 else
571 limit = &intel_limits_ironlake_single_lvds;
572 }
573 } else
574 limit = &intel_limits_ironlake_dac;
575
576 return limit;
577 }
578
579 static const intel_limit_t *
580 intel_g4x_limit(struct intel_crtc_state *crtc_state)
581 {
582 struct drm_device *dev = crtc_state->base.crtc->dev;
583 const intel_limit_t *limit;
584
585 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
586 if (intel_is_dual_link_lvds(dev))
587 limit = &intel_limits_g4x_dual_channel_lvds;
588 else
589 limit = &intel_limits_g4x_single_channel_lvds;
590 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
591 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
592 limit = &intel_limits_g4x_hdmi;
593 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
594 limit = &intel_limits_g4x_sdvo;
595 } else /* The option is for other outputs */
596 limit = &intel_limits_i9xx_sdvo;
597
598 return limit;
599 }
600
601 static const intel_limit_t *
602 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
603 {
604 struct drm_device *dev = crtc_state->base.crtc->dev;
605 const intel_limit_t *limit;
606
607 if (IS_BROXTON(dev))
608 limit = &intel_limits_bxt;
609 else if (HAS_PCH_SPLIT(dev))
610 limit = intel_ironlake_limit(crtc_state, refclk);
611 else if (IS_G4X(dev)) {
612 limit = intel_g4x_limit(crtc_state);
613 } else if (IS_PINEVIEW(dev)) {
614 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
615 limit = &intel_limits_pineview_lvds;
616 else
617 limit = &intel_limits_pineview_sdvo;
618 } else if (IS_CHERRYVIEW(dev)) {
619 limit = &intel_limits_chv;
620 } else if (IS_VALLEYVIEW(dev)) {
621 limit = &intel_limits_vlv;
622 } else if (!IS_GEN2(dev)) {
623 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
624 limit = &intel_limits_i9xx_lvds;
625 else
626 limit = &intel_limits_i9xx_sdvo;
627 } else {
628 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
629 limit = &intel_limits_i8xx_lvds;
630 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
631 limit = &intel_limits_i8xx_dvo;
632 else
633 limit = &intel_limits_i8xx_dac;
634 }
635 return limit;
636 }
637
638 /*
639 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
640 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
641 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
642 * The helpers' return value is the rate of the clock that is fed to the
643 * display engine's pipe which can be the above fast dot clock rate or a
644 * divided-down version of it.
645 */
646 /* m1 is reserved as 0 in Pineview, n is a ring counter */
647 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
648 {
649 clock->m = clock->m2 + 2;
650 clock->p = clock->p1 * clock->p2;
651 if (WARN_ON(clock->n == 0 || clock->p == 0))
652 return 0;
653 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
654 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
655
656 return clock->dot;
657 }
658
659 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
660 {
661 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
662 }
663
664 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
665 {
666 clock->m = i9xx_dpll_compute_m(clock);
667 clock->p = clock->p1 * clock->p2;
668 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
669 return 0;
670 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
671 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
672
673 return clock->dot;
674 }
675
676 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
677 {
678 clock->m = clock->m1 * clock->m2;
679 clock->p = clock->p1 * clock->p2;
680 if (WARN_ON(clock->n == 0 || clock->p == 0))
681 return 0;
682 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
683 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
684
685 return clock->dot / 5;
686 }
687
688 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
689 {
690 clock->m = clock->m1 * clock->m2;
691 clock->p = clock->p1 * clock->p2;
692 if (WARN_ON(clock->n == 0 || clock->p == 0))
693 return 0;
694 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
695 clock->n << 22);
696 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
697
698 return clock->dot / 5;
699 }
700
701 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
702 /**
703 * Returns whether the given set of divisors are valid for a given refclk with
704 * the given connectors.
705 */
706
707 static bool intel_PLL_is_valid(struct drm_device *dev,
708 const intel_limit_t *limit,
709 const intel_clock_t *clock)
710 {
711 if (clock->n < limit->n.min || limit->n.max < clock->n)
712 INTELPllInvalid("n out of range\n");
713 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
714 INTELPllInvalid("p1 out of range\n");
715 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
716 INTELPllInvalid("m2 out of range\n");
717 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
718 INTELPllInvalid("m1 out of range\n");
719
720 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
721 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
722 if (clock->m1 <= clock->m2)
723 INTELPllInvalid("m1 <= m2\n");
724
725 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
726 if (clock->p < limit->p.min || limit->p.max < clock->p)
727 INTELPllInvalid("p out of range\n");
728 if (clock->m < limit->m.min || limit->m.max < clock->m)
729 INTELPllInvalid("m out of range\n");
730 }
731
732 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
733 INTELPllInvalid("vco out of range\n");
734 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
735 * connector, etc., rather than just a single range.
736 */
737 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
738 INTELPllInvalid("dot out of range\n");
739
740 return true;
741 }
742
743 static int
744 i9xx_select_p2_div(const intel_limit_t *limit,
745 const struct intel_crtc_state *crtc_state,
746 int target)
747 {
748 struct drm_device *dev = crtc_state->base.crtc->dev;
749
750 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
751 /*
752 * For LVDS just rely on its current settings for dual-channel.
753 * We haven't figured out how to reliably set up different
754 * single/dual channel state, if we even can.
755 */
756 if (intel_is_dual_link_lvds(dev))
757 return limit->p2.p2_fast;
758 else
759 return limit->p2.p2_slow;
760 } else {
761 if (target < limit->p2.dot_limit)
762 return limit->p2.p2_slow;
763 else
764 return limit->p2.p2_fast;
765 }
766 }
767
768 static bool
769 i9xx_find_best_dpll(const intel_limit_t *limit,
770 struct intel_crtc_state *crtc_state,
771 int target, int refclk, intel_clock_t *match_clock,
772 intel_clock_t *best_clock)
773 {
774 struct drm_device *dev = crtc_state->base.crtc->dev;
775 intel_clock_t clock;
776 int err = target;
777
778 memset(best_clock, 0, sizeof(*best_clock));
779
780 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
781
782 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
783 clock.m1++) {
784 for (clock.m2 = limit->m2.min;
785 clock.m2 <= limit->m2.max; clock.m2++) {
786 if (clock.m2 >= clock.m1)
787 break;
788 for (clock.n = limit->n.min;
789 clock.n <= limit->n.max; clock.n++) {
790 for (clock.p1 = limit->p1.min;
791 clock.p1 <= limit->p1.max; clock.p1++) {
792 int this_err;
793
794 i9xx_calc_dpll_params(refclk, &clock);
795 if (!intel_PLL_is_valid(dev, limit,
796 &clock))
797 continue;
798 if (match_clock &&
799 clock.p != match_clock->p)
800 continue;
801
802 this_err = abs(clock.dot - target);
803 if (this_err < err) {
804 *best_clock = clock;
805 err = this_err;
806 }
807 }
808 }
809 }
810 }
811
812 return (err != target);
813 }
814
815 static bool
816 pnv_find_best_dpll(const intel_limit_t *limit,
817 struct intel_crtc_state *crtc_state,
818 int target, int refclk, intel_clock_t *match_clock,
819 intel_clock_t *best_clock)
820 {
821 struct drm_device *dev = crtc_state->base.crtc->dev;
822 intel_clock_t clock;
823 int err = target;
824
825 memset(best_clock, 0, sizeof(*best_clock));
826
827 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
828
829 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
830 clock.m1++) {
831 for (clock.m2 = limit->m2.min;
832 clock.m2 <= limit->m2.max; clock.m2++) {
833 for (clock.n = limit->n.min;
834 clock.n <= limit->n.max; clock.n++) {
835 for (clock.p1 = limit->p1.min;
836 clock.p1 <= limit->p1.max; clock.p1++) {
837 int this_err;
838
839 pnv_calc_dpll_params(refclk, &clock);
840 if (!intel_PLL_is_valid(dev, limit,
841 &clock))
842 continue;
843 if (match_clock &&
844 clock.p != match_clock->p)
845 continue;
846
847 this_err = abs(clock.dot - target);
848 if (this_err < err) {
849 *best_clock = clock;
850 err = this_err;
851 }
852 }
853 }
854 }
855 }
856
857 return (err != target);
858 }
859
860 static bool
861 g4x_find_best_dpll(const intel_limit_t *limit,
862 struct intel_crtc_state *crtc_state,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865 {
866 struct drm_device *dev = crtc_state->base.crtc->dev;
867 intel_clock_t clock;
868 int max_n;
869 bool found = false;
870 /* approximately equals target * 0.00585 */
871 int err_most = (target >> 8) + (target >> 9);
872
873 memset(best_clock, 0, sizeof(*best_clock));
874
875 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
876
877 max_n = limit->n.max;
878 /* based on hardware requirement, prefer smaller n to precision */
879 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
880 /* based on hardware requirement, prefere larger m1,m2 */
881 for (clock.m1 = limit->m1.max;
882 clock.m1 >= limit->m1.min; clock.m1--) {
883 for (clock.m2 = limit->m2.max;
884 clock.m2 >= limit->m2.min; clock.m2--) {
885 for (clock.p1 = limit->p1.max;
886 clock.p1 >= limit->p1.min; clock.p1--) {
887 int this_err;
888
889 i9xx_calc_dpll_params(refclk, &clock);
890 if (!intel_PLL_is_valid(dev, limit,
891 &clock))
892 continue;
893
894 this_err = abs(clock.dot - target);
895 if (this_err < err_most) {
896 *best_clock = clock;
897 err_most = this_err;
898 max_n = clock.n;
899 found = true;
900 }
901 }
902 }
903 }
904 }
905 return found;
906 }
907
908 /*
909 * Check if the calculated PLL configuration is more optimal compared to the
910 * best configuration and error found so far. Return the calculated error.
911 */
912 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
913 const intel_clock_t *calculated_clock,
914 const intel_clock_t *best_clock,
915 unsigned int best_error_ppm,
916 unsigned int *error_ppm)
917 {
918 /*
919 * For CHV ignore the error and consider only the P value.
920 * Prefer a bigger P value based on HW requirements.
921 */
922 if (IS_CHERRYVIEW(dev)) {
923 *error_ppm = 0;
924
925 return calculated_clock->p > best_clock->p;
926 }
927
928 if (WARN_ON_ONCE(!target_freq))
929 return false;
930
931 *error_ppm = div_u64(1000000ULL *
932 abs(target_freq - calculated_clock->dot),
933 target_freq);
934 /*
935 * Prefer a better P value over a better (smaller) error if the error
936 * is small. Ensure this preference for future configurations too by
937 * setting the error to 0.
938 */
939 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
940 *error_ppm = 0;
941
942 return true;
943 }
944
945 return *error_ppm + 10 < best_error_ppm;
946 }
947
948 static bool
949 vlv_find_best_dpll(const intel_limit_t *limit,
950 struct intel_crtc_state *crtc_state,
951 int target, int refclk, intel_clock_t *match_clock,
952 intel_clock_t *best_clock)
953 {
954 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
955 struct drm_device *dev = crtc->base.dev;
956 intel_clock_t clock;
957 unsigned int bestppm = 1000000;
958 /* min update 19.2 MHz */
959 int max_n = min(limit->n.max, refclk / 19200);
960 bool found = false;
961
962 target *= 5; /* fast clock */
963
964 memset(best_clock, 0, sizeof(*best_clock));
965
966 /* based on hardware requirement, prefer smaller n to precision */
967 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
968 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
969 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
970 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
971 clock.p = clock.p1 * clock.p2;
972 /* based on hardware requirement, prefer bigger m1,m2 values */
973 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
974 unsigned int ppm;
975
976 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
977 refclk * clock.m1);
978
979 vlv_calc_dpll_params(refclk, &clock);
980
981 if (!intel_PLL_is_valid(dev, limit,
982 &clock))
983 continue;
984
985 if (!vlv_PLL_is_optimal(dev, target,
986 &clock,
987 best_clock,
988 bestppm, &ppm))
989 continue;
990
991 *best_clock = clock;
992 bestppm = ppm;
993 found = true;
994 }
995 }
996 }
997 }
998
999 return found;
1000 }
1001
1002 static bool
1003 chv_find_best_dpll(const intel_limit_t *limit,
1004 struct intel_crtc_state *crtc_state,
1005 int target, int refclk, intel_clock_t *match_clock,
1006 intel_clock_t *best_clock)
1007 {
1008 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1009 struct drm_device *dev = crtc->base.dev;
1010 unsigned int best_error_ppm;
1011 intel_clock_t clock;
1012 uint64_t m2;
1013 int found = false;
1014
1015 memset(best_clock, 0, sizeof(*best_clock));
1016 best_error_ppm = 1000000;
1017
1018 /*
1019 * Based on hardware doc, the n always set to 1, and m1 always
1020 * set to 2. If requires to support 200Mhz refclk, we need to
1021 * revisit this because n may not 1 anymore.
1022 */
1023 clock.n = 1, clock.m1 = 2;
1024 target *= 5; /* fast clock */
1025
1026 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1027 for (clock.p2 = limit->p2.p2_fast;
1028 clock.p2 >= limit->p2.p2_slow;
1029 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1030 unsigned int error_ppm;
1031
1032 clock.p = clock.p1 * clock.p2;
1033
1034 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1035 clock.n) << 22, refclk * clock.m1);
1036
1037 if (m2 > INT_MAX/clock.m1)
1038 continue;
1039
1040 clock.m2 = m2;
1041
1042 chv_calc_dpll_params(refclk, &clock);
1043
1044 if (!intel_PLL_is_valid(dev, limit, &clock))
1045 continue;
1046
1047 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1048 best_error_ppm, &error_ppm))
1049 continue;
1050
1051 *best_clock = clock;
1052 best_error_ppm = error_ppm;
1053 found = true;
1054 }
1055 }
1056
1057 return found;
1058 }
1059
1060 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1061 intel_clock_t *best_clock)
1062 {
1063 int refclk = i9xx_get_refclk(crtc_state, 0);
1064
1065 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1066 target_clock, refclk, NULL, best_clock);
1067 }
1068
1069 bool intel_crtc_active(struct drm_crtc *crtc)
1070 {
1071 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1072
1073 /* Be paranoid as we can arrive here with only partial
1074 * state retrieved from the hardware during setup.
1075 *
1076 * We can ditch the adjusted_mode.crtc_clock check as soon
1077 * as Haswell has gained clock readout/fastboot support.
1078 *
1079 * We can ditch the crtc->primary->fb check as soon as we can
1080 * properly reconstruct framebuffers.
1081 *
1082 * FIXME: The intel_crtc->active here should be switched to
1083 * crtc->state->active once we have proper CRTC states wired up
1084 * for atomic.
1085 */
1086 return intel_crtc->active && crtc->primary->state->fb &&
1087 intel_crtc->config->base.adjusted_mode.crtc_clock;
1088 }
1089
1090 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1091 enum pipe pipe)
1092 {
1093 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1095
1096 return intel_crtc->config->cpu_transcoder;
1097 }
1098
1099 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1100 {
1101 struct drm_i915_private *dev_priv = dev->dev_private;
1102 i915_reg_t reg = PIPEDSL(pipe);
1103 u32 line1, line2;
1104 u32 line_mask;
1105
1106 if (IS_GEN2(dev))
1107 line_mask = DSL_LINEMASK_GEN2;
1108 else
1109 line_mask = DSL_LINEMASK_GEN3;
1110
1111 line1 = I915_READ(reg) & line_mask;
1112 msleep(5);
1113 line2 = I915_READ(reg) & line_mask;
1114
1115 return line1 == line2;
1116 }
1117
1118 /*
1119 * intel_wait_for_pipe_off - wait for pipe to turn off
1120 * @crtc: crtc whose pipe to wait for
1121 *
1122 * After disabling a pipe, we can't wait for vblank in the usual way,
1123 * spinning on the vblank interrupt status bit, since we won't actually
1124 * see an interrupt when the pipe is disabled.
1125 *
1126 * On Gen4 and above:
1127 * wait for the pipe register state bit to turn off
1128 *
1129 * Otherwise:
1130 * wait for the display line value to settle (it usually
1131 * ends up stopping at the start of the next frame).
1132 *
1133 */
1134 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1135 {
1136 struct drm_device *dev = crtc->base.dev;
1137 struct drm_i915_private *dev_priv = dev->dev_private;
1138 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1139 enum pipe pipe = crtc->pipe;
1140
1141 if (INTEL_INFO(dev)->gen >= 4) {
1142 i915_reg_t reg = PIPECONF(cpu_transcoder);
1143
1144 /* Wait for the Pipe State to go off */
1145 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1146 100))
1147 WARN(1, "pipe_off wait timed out\n");
1148 } else {
1149 /* Wait for the display line to settle */
1150 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1151 WARN(1, "pipe_off wait timed out\n");
1152 }
1153 }
1154
1155 static const char *state_string(bool enabled)
1156 {
1157 return enabled ? "on" : "off";
1158 }
1159
1160 /* Only for pre-ILK configs */
1161 void assert_pll(struct drm_i915_private *dev_priv,
1162 enum pipe pipe, bool state)
1163 {
1164 u32 val;
1165 bool cur_state;
1166
1167 val = I915_READ(DPLL(pipe));
1168 cur_state = !!(val & DPLL_VCO_ENABLE);
1169 I915_STATE_WARN(cur_state != state,
1170 "PLL state assertion failure (expected %s, current %s)\n",
1171 state_string(state), state_string(cur_state));
1172 }
1173
1174 /* XXX: the dsi pll is shared between MIPI DSI ports */
1175 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1176 {
1177 u32 val;
1178 bool cur_state;
1179
1180 mutex_lock(&dev_priv->sb_lock);
1181 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1182 mutex_unlock(&dev_priv->sb_lock);
1183
1184 cur_state = val & DSI_PLL_VCO_EN;
1185 I915_STATE_WARN(cur_state != state,
1186 "DSI PLL state assertion failure (expected %s, current %s)\n",
1187 state_string(state), state_string(cur_state));
1188 }
1189 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1190 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1191
1192 struct intel_shared_dpll *
1193 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1194 {
1195 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1196
1197 if (crtc->config->shared_dpll < 0)
1198 return NULL;
1199
1200 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1201 }
1202
1203 /* For ILK+ */
1204 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1205 struct intel_shared_dpll *pll,
1206 bool state)
1207 {
1208 bool cur_state;
1209 struct intel_dpll_hw_state hw_state;
1210
1211 if (WARN (!pll,
1212 "asserting DPLL %s with no DPLL\n", state_string(state)))
1213 return;
1214
1215 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1216 I915_STATE_WARN(cur_state != state,
1217 "%s assertion failure (expected %s, current %s)\n",
1218 pll->name, state_string(state), state_string(cur_state));
1219 }
1220
1221 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1222 enum pipe pipe, bool state)
1223 {
1224 bool cur_state;
1225 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1226 pipe);
1227
1228 if (HAS_DDI(dev_priv->dev)) {
1229 /* DDI does not have a specific FDI_TX register */
1230 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1231 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1232 } else {
1233 u32 val = I915_READ(FDI_TX_CTL(pipe));
1234 cur_state = !!(val & FDI_TX_ENABLE);
1235 }
1236 I915_STATE_WARN(cur_state != state,
1237 "FDI TX state assertion failure (expected %s, current %s)\n",
1238 state_string(state), state_string(cur_state));
1239 }
1240 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1241 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1242
1243 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1244 enum pipe pipe, bool state)
1245 {
1246 u32 val;
1247 bool cur_state;
1248
1249 val = I915_READ(FDI_RX_CTL(pipe));
1250 cur_state = !!(val & FDI_RX_ENABLE);
1251 I915_STATE_WARN(cur_state != state,
1252 "FDI RX state assertion failure (expected %s, current %s)\n",
1253 state_string(state), state_string(cur_state));
1254 }
1255 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1256 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1257
1258 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1259 enum pipe pipe)
1260 {
1261 u32 val;
1262
1263 /* ILK FDI PLL is always enabled */
1264 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1265 return;
1266
1267 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1268 if (HAS_DDI(dev_priv->dev))
1269 return;
1270
1271 val = I915_READ(FDI_TX_CTL(pipe));
1272 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1273 }
1274
1275 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1276 enum pipe pipe, bool state)
1277 {
1278 u32 val;
1279 bool cur_state;
1280
1281 val = I915_READ(FDI_RX_CTL(pipe));
1282 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1283 I915_STATE_WARN(cur_state != state,
1284 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1285 state_string(state), state_string(cur_state));
1286 }
1287
1288 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1289 enum pipe pipe)
1290 {
1291 struct drm_device *dev = dev_priv->dev;
1292 i915_reg_t pp_reg;
1293 u32 val;
1294 enum pipe panel_pipe = PIPE_A;
1295 bool locked = true;
1296
1297 if (WARN_ON(HAS_DDI(dev)))
1298 return;
1299
1300 if (HAS_PCH_SPLIT(dev)) {
1301 u32 port_sel;
1302
1303 pp_reg = PCH_PP_CONTROL;
1304 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1305
1306 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1307 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1308 panel_pipe = PIPE_B;
1309 /* XXX: else fix for eDP */
1310 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1311 /* presumably write lock depends on pipe, not port select */
1312 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1313 panel_pipe = pipe;
1314 } else {
1315 pp_reg = PP_CONTROL;
1316 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1317 panel_pipe = PIPE_B;
1318 }
1319
1320 val = I915_READ(pp_reg);
1321 if (!(val & PANEL_POWER_ON) ||
1322 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1323 locked = false;
1324
1325 I915_STATE_WARN(panel_pipe == pipe && locked,
1326 "panel assertion failure, pipe %c regs locked\n",
1327 pipe_name(pipe));
1328 }
1329
1330 static void assert_cursor(struct drm_i915_private *dev_priv,
1331 enum pipe pipe, bool state)
1332 {
1333 struct drm_device *dev = dev_priv->dev;
1334 bool cur_state;
1335
1336 if (IS_845G(dev) || IS_I865G(dev))
1337 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1338 else
1339 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1340
1341 I915_STATE_WARN(cur_state != state,
1342 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1343 pipe_name(pipe), state_string(state), state_string(cur_state));
1344 }
1345 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1346 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1347
1348 void assert_pipe(struct drm_i915_private *dev_priv,
1349 enum pipe pipe, bool state)
1350 {
1351 bool cur_state;
1352 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1353 pipe);
1354
1355 /* if we need the pipe quirk it must be always on */
1356 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1357 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1358 state = true;
1359
1360 if (!intel_display_power_is_enabled(dev_priv,
1361 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1362 cur_state = false;
1363 } else {
1364 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1365 cur_state = !!(val & PIPECONF_ENABLE);
1366 }
1367
1368 I915_STATE_WARN(cur_state != state,
1369 "pipe %c assertion failure (expected %s, current %s)\n",
1370 pipe_name(pipe), state_string(state), state_string(cur_state));
1371 }
1372
1373 static void assert_plane(struct drm_i915_private *dev_priv,
1374 enum plane plane, bool state)
1375 {
1376 u32 val;
1377 bool cur_state;
1378
1379 val = I915_READ(DSPCNTR(plane));
1380 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1381 I915_STATE_WARN(cur_state != state,
1382 "plane %c assertion failure (expected %s, current %s)\n",
1383 plane_name(plane), state_string(state), state_string(cur_state));
1384 }
1385
1386 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1387 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1388
1389 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1390 enum pipe pipe)
1391 {
1392 struct drm_device *dev = dev_priv->dev;
1393 int i;
1394
1395 /* Primary planes are fixed to pipes on gen4+ */
1396 if (INTEL_INFO(dev)->gen >= 4) {
1397 u32 val = I915_READ(DSPCNTR(pipe));
1398 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1399 "plane %c assertion failure, should be disabled but not\n",
1400 plane_name(pipe));
1401 return;
1402 }
1403
1404 /* Need to check both planes against the pipe */
1405 for_each_pipe(dev_priv, i) {
1406 u32 val = I915_READ(DSPCNTR(i));
1407 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1408 DISPPLANE_SEL_PIPE_SHIFT;
1409 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1410 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1411 plane_name(i), pipe_name(pipe));
1412 }
1413 }
1414
1415 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1416 enum pipe pipe)
1417 {
1418 struct drm_device *dev = dev_priv->dev;
1419 int sprite;
1420
1421 if (INTEL_INFO(dev)->gen >= 9) {
1422 for_each_sprite(dev_priv, pipe, sprite) {
1423 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1424 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1425 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1426 sprite, pipe_name(pipe));
1427 }
1428 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1429 for_each_sprite(dev_priv, pipe, sprite) {
1430 u32 val = I915_READ(SPCNTR(pipe, sprite));
1431 I915_STATE_WARN(val & SP_ENABLE,
1432 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1433 sprite_name(pipe, sprite), pipe_name(pipe));
1434 }
1435 } else if (INTEL_INFO(dev)->gen >= 7) {
1436 u32 val = I915_READ(SPRCTL(pipe));
1437 I915_STATE_WARN(val & SPRITE_ENABLE,
1438 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1439 plane_name(pipe), pipe_name(pipe));
1440 } else if (INTEL_INFO(dev)->gen >= 5) {
1441 u32 val = I915_READ(DVSCNTR(pipe));
1442 I915_STATE_WARN(val & DVS_ENABLE,
1443 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1444 plane_name(pipe), pipe_name(pipe));
1445 }
1446 }
1447
1448 static void assert_vblank_disabled(struct drm_crtc *crtc)
1449 {
1450 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1451 drm_crtc_vblank_put(crtc);
1452 }
1453
1454 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1455 {
1456 u32 val;
1457 bool enabled;
1458
1459 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1460
1461 val = I915_READ(PCH_DREF_CONTROL);
1462 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1463 DREF_SUPERSPREAD_SOURCE_MASK));
1464 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1465 }
1466
1467 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1468 enum pipe pipe)
1469 {
1470 u32 val;
1471 bool enabled;
1472
1473 val = I915_READ(PCH_TRANSCONF(pipe));
1474 enabled = !!(val & TRANS_ENABLE);
1475 I915_STATE_WARN(enabled,
1476 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1477 pipe_name(pipe));
1478 }
1479
1480 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1481 enum pipe pipe, u32 port_sel, u32 val)
1482 {
1483 if ((val & DP_PORT_EN) == 0)
1484 return false;
1485
1486 if (HAS_PCH_CPT(dev_priv->dev)) {
1487 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1488 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1489 return false;
1490 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1491 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1492 return false;
1493 } else {
1494 if ((val & DP_PIPE_MASK) != (pipe << 30))
1495 return false;
1496 }
1497 return true;
1498 }
1499
1500 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1501 enum pipe pipe, u32 val)
1502 {
1503 if ((val & SDVO_ENABLE) == 0)
1504 return false;
1505
1506 if (HAS_PCH_CPT(dev_priv->dev)) {
1507 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1508 return false;
1509 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1510 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1511 return false;
1512 } else {
1513 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1514 return false;
1515 }
1516 return true;
1517 }
1518
1519 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1520 enum pipe pipe, u32 val)
1521 {
1522 if ((val & LVDS_PORT_EN) == 0)
1523 return false;
1524
1525 if (HAS_PCH_CPT(dev_priv->dev)) {
1526 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1527 return false;
1528 } else {
1529 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1530 return false;
1531 }
1532 return true;
1533 }
1534
1535 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1536 enum pipe pipe, u32 val)
1537 {
1538 if ((val & ADPA_DAC_ENABLE) == 0)
1539 return false;
1540 if (HAS_PCH_CPT(dev_priv->dev)) {
1541 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1542 return false;
1543 } else {
1544 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1545 return false;
1546 }
1547 return true;
1548 }
1549
1550 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1551 enum pipe pipe, i915_reg_t reg,
1552 u32 port_sel)
1553 {
1554 u32 val = I915_READ(reg);
1555 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1556 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1557 i915_mmio_reg_offset(reg), pipe_name(pipe));
1558
1559 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1560 && (val & DP_PIPEB_SELECT),
1561 "IBX PCH dp port still using transcoder B\n");
1562 }
1563
1564 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1565 enum pipe pipe, i915_reg_t reg)
1566 {
1567 u32 val = I915_READ(reg);
1568 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1569 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1570 i915_mmio_reg_offset(reg), pipe_name(pipe));
1571
1572 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1573 && (val & SDVO_PIPE_B_SELECT),
1574 "IBX PCH hdmi port still using transcoder B\n");
1575 }
1576
1577 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1578 enum pipe pipe)
1579 {
1580 u32 val;
1581
1582 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1583 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1584 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1585
1586 val = I915_READ(PCH_ADPA);
1587 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1588 "PCH VGA enabled on transcoder %c, should be disabled\n",
1589 pipe_name(pipe));
1590
1591 val = I915_READ(PCH_LVDS);
1592 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1593 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1594 pipe_name(pipe));
1595
1596 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1597 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1598 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1599 }
1600
1601 static void vlv_enable_pll(struct intel_crtc *crtc,
1602 const struct intel_crtc_state *pipe_config)
1603 {
1604 struct drm_device *dev = crtc->base.dev;
1605 struct drm_i915_private *dev_priv = dev->dev_private;
1606 i915_reg_t reg = DPLL(crtc->pipe);
1607 u32 dpll = pipe_config->dpll_hw_state.dpll;
1608
1609 assert_pipe_disabled(dev_priv, crtc->pipe);
1610
1611 /* PLL is protected by panel, make sure we can write it */
1612 if (IS_MOBILE(dev_priv->dev))
1613 assert_panel_unlocked(dev_priv, crtc->pipe);
1614
1615 I915_WRITE(reg, dpll);
1616 POSTING_READ(reg);
1617 udelay(150);
1618
1619 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1620 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1621
1622 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1623 POSTING_READ(DPLL_MD(crtc->pipe));
1624
1625 /* We do this three times for luck */
1626 I915_WRITE(reg, dpll);
1627 POSTING_READ(reg);
1628 udelay(150); /* wait for warmup */
1629 I915_WRITE(reg, dpll);
1630 POSTING_READ(reg);
1631 udelay(150); /* wait for warmup */
1632 I915_WRITE(reg, dpll);
1633 POSTING_READ(reg);
1634 udelay(150); /* wait for warmup */
1635 }
1636
1637 static void chv_enable_pll(struct intel_crtc *crtc,
1638 const struct intel_crtc_state *pipe_config)
1639 {
1640 struct drm_device *dev = crtc->base.dev;
1641 struct drm_i915_private *dev_priv = dev->dev_private;
1642 int pipe = crtc->pipe;
1643 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1644 u32 tmp;
1645
1646 assert_pipe_disabled(dev_priv, crtc->pipe);
1647
1648 mutex_lock(&dev_priv->sb_lock);
1649
1650 /* Enable back the 10bit clock to display controller */
1651 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1652 tmp |= DPIO_DCLKP_EN;
1653 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1654
1655 mutex_unlock(&dev_priv->sb_lock);
1656
1657 /*
1658 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1659 */
1660 udelay(1);
1661
1662 /* Enable PLL */
1663 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1664
1665 /* Check PLL is locked */
1666 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1667 DRM_ERROR("PLL %d failed to lock\n", pipe);
1668
1669 /* not sure when this should be written */
1670 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1671 POSTING_READ(DPLL_MD(pipe));
1672 }
1673
1674 static int intel_num_dvo_pipes(struct drm_device *dev)
1675 {
1676 struct intel_crtc *crtc;
1677 int count = 0;
1678
1679 for_each_intel_crtc(dev, crtc)
1680 count += crtc->base.state->active &&
1681 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1682
1683 return count;
1684 }
1685
1686 static void i9xx_enable_pll(struct intel_crtc *crtc)
1687 {
1688 struct drm_device *dev = crtc->base.dev;
1689 struct drm_i915_private *dev_priv = dev->dev_private;
1690 i915_reg_t reg = DPLL(crtc->pipe);
1691 u32 dpll = crtc->config->dpll_hw_state.dpll;
1692
1693 assert_pipe_disabled(dev_priv, crtc->pipe);
1694
1695 /* No really, not for ILK+ */
1696 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1697
1698 /* PLL is protected by panel, make sure we can write it */
1699 if (IS_MOBILE(dev) && !IS_I830(dev))
1700 assert_panel_unlocked(dev_priv, crtc->pipe);
1701
1702 /* Enable DVO 2x clock on both PLLs if necessary */
1703 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1704 /*
1705 * It appears to be important that we don't enable this
1706 * for the current pipe before otherwise configuring the
1707 * PLL. No idea how this should be handled if multiple
1708 * DVO outputs are enabled simultaneosly.
1709 */
1710 dpll |= DPLL_DVO_2X_MODE;
1711 I915_WRITE(DPLL(!crtc->pipe),
1712 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1713 }
1714
1715 /*
1716 * Apparently we need to have VGA mode enabled prior to changing
1717 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1718 * dividers, even though the register value does change.
1719 */
1720 I915_WRITE(reg, 0);
1721
1722 I915_WRITE(reg, dpll);
1723
1724 /* Wait for the clocks to stabilize. */
1725 POSTING_READ(reg);
1726 udelay(150);
1727
1728 if (INTEL_INFO(dev)->gen >= 4) {
1729 I915_WRITE(DPLL_MD(crtc->pipe),
1730 crtc->config->dpll_hw_state.dpll_md);
1731 } else {
1732 /* The pixel multiplier can only be updated once the
1733 * DPLL is enabled and the clocks are stable.
1734 *
1735 * So write it again.
1736 */
1737 I915_WRITE(reg, dpll);
1738 }
1739
1740 /* We do this three times for luck */
1741 I915_WRITE(reg, dpll);
1742 POSTING_READ(reg);
1743 udelay(150); /* wait for warmup */
1744 I915_WRITE(reg, dpll);
1745 POSTING_READ(reg);
1746 udelay(150); /* wait for warmup */
1747 I915_WRITE(reg, dpll);
1748 POSTING_READ(reg);
1749 udelay(150); /* wait for warmup */
1750 }
1751
1752 /**
1753 * i9xx_disable_pll - disable a PLL
1754 * @dev_priv: i915 private structure
1755 * @pipe: pipe PLL to disable
1756 *
1757 * Disable the PLL for @pipe, making sure the pipe is off first.
1758 *
1759 * Note! This is for pre-ILK only.
1760 */
1761 static void i9xx_disable_pll(struct intel_crtc *crtc)
1762 {
1763 struct drm_device *dev = crtc->base.dev;
1764 struct drm_i915_private *dev_priv = dev->dev_private;
1765 enum pipe pipe = crtc->pipe;
1766
1767 /* Disable DVO 2x clock on both PLLs if necessary */
1768 if (IS_I830(dev) &&
1769 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1770 !intel_num_dvo_pipes(dev)) {
1771 I915_WRITE(DPLL(PIPE_B),
1772 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1773 I915_WRITE(DPLL(PIPE_A),
1774 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1775 }
1776
1777 /* Don't disable pipe or pipe PLLs if needed */
1778 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1779 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1780 return;
1781
1782 /* Make sure the pipe isn't still relying on us */
1783 assert_pipe_disabled(dev_priv, pipe);
1784
1785 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1786 POSTING_READ(DPLL(pipe));
1787 }
1788
1789 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1790 {
1791 u32 val;
1792
1793 /* Make sure the pipe isn't still relying on us */
1794 assert_pipe_disabled(dev_priv, pipe);
1795
1796 /*
1797 * Leave integrated clock source and reference clock enabled for pipe B.
1798 * The latter is needed for VGA hotplug / manual detection.
1799 */
1800 val = DPLL_VGA_MODE_DIS;
1801 if (pipe == PIPE_B)
1802 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1803 I915_WRITE(DPLL(pipe), val);
1804 POSTING_READ(DPLL(pipe));
1805
1806 }
1807
1808 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1809 {
1810 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1811 u32 val;
1812
1813 /* Make sure the pipe isn't still relying on us */
1814 assert_pipe_disabled(dev_priv, pipe);
1815
1816 /* Set PLL en = 0 */
1817 val = DPLL_SSC_REF_CLK_CHV |
1818 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1819 if (pipe != PIPE_A)
1820 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1821 I915_WRITE(DPLL(pipe), val);
1822 POSTING_READ(DPLL(pipe));
1823
1824 mutex_lock(&dev_priv->sb_lock);
1825
1826 /* Disable 10bit clock to display controller */
1827 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1828 val &= ~DPIO_DCLKP_EN;
1829 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1830
1831 mutex_unlock(&dev_priv->sb_lock);
1832 }
1833
1834 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1835 struct intel_digital_port *dport,
1836 unsigned int expected_mask)
1837 {
1838 u32 port_mask;
1839 i915_reg_t dpll_reg;
1840
1841 switch (dport->port) {
1842 case PORT_B:
1843 port_mask = DPLL_PORTB_READY_MASK;
1844 dpll_reg = DPLL(0);
1845 break;
1846 case PORT_C:
1847 port_mask = DPLL_PORTC_READY_MASK;
1848 dpll_reg = DPLL(0);
1849 expected_mask <<= 4;
1850 break;
1851 case PORT_D:
1852 port_mask = DPLL_PORTD_READY_MASK;
1853 dpll_reg = DPIO_PHY_STATUS;
1854 break;
1855 default:
1856 BUG();
1857 }
1858
1859 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1860 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1861 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1862 }
1863
1864 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1865 {
1866 struct drm_device *dev = crtc->base.dev;
1867 struct drm_i915_private *dev_priv = dev->dev_private;
1868 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1869
1870 if (WARN_ON(pll == NULL))
1871 return;
1872
1873 WARN_ON(!pll->config.crtc_mask);
1874 if (pll->active == 0) {
1875 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1876 WARN_ON(pll->on);
1877 assert_shared_dpll_disabled(dev_priv, pll);
1878
1879 pll->mode_set(dev_priv, pll);
1880 }
1881 }
1882
1883 /**
1884 * intel_enable_shared_dpll - enable PCH PLL
1885 * @dev_priv: i915 private structure
1886 * @pipe: pipe PLL to enable
1887 *
1888 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1889 * drives the transcoder clock.
1890 */
1891 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1892 {
1893 struct drm_device *dev = crtc->base.dev;
1894 struct drm_i915_private *dev_priv = dev->dev_private;
1895 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1896
1897 if (WARN_ON(pll == NULL))
1898 return;
1899
1900 if (WARN_ON(pll->config.crtc_mask == 0))
1901 return;
1902
1903 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1904 pll->name, pll->active, pll->on,
1905 crtc->base.base.id);
1906
1907 if (pll->active++) {
1908 WARN_ON(!pll->on);
1909 assert_shared_dpll_enabled(dev_priv, pll);
1910 return;
1911 }
1912 WARN_ON(pll->on);
1913
1914 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1915
1916 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1917 pll->enable(dev_priv, pll);
1918 pll->on = true;
1919 }
1920
1921 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1922 {
1923 struct drm_device *dev = crtc->base.dev;
1924 struct drm_i915_private *dev_priv = dev->dev_private;
1925 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1926
1927 /* PCH only available on ILK+ */
1928 if (INTEL_INFO(dev)->gen < 5)
1929 return;
1930
1931 if (pll == NULL)
1932 return;
1933
1934 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1935 return;
1936
1937 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1938 pll->name, pll->active, pll->on,
1939 crtc->base.base.id);
1940
1941 if (WARN_ON(pll->active == 0)) {
1942 assert_shared_dpll_disabled(dev_priv, pll);
1943 return;
1944 }
1945
1946 assert_shared_dpll_enabled(dev_priv, pll);
1947 WARN_ON(!pll->on);
1948 if (--pll->active)
1949 return;
1950
1951 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1952 pll->disable(dev_priv, pll);
1953 pll->on = false;
1954
1955 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1956 }
1957
1958 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1959 enum pipe pipe)
1960 {
1961 struct drm_device *dev = dev_priv->dev;
1962 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1964 i915_reg_t reg;
1965 uint32_t val, pipeconf_val;
1966
1967 /* PCH only available on ILK+ */
1968 BUG_ON(!HAS_PCH_SPLIT(dev));
1969
1970 /* Make sure PCH DPLL is enabled */
1971 assert_shared_dpll_enabled(dev_priv,
1972 intel_crtc_to_shared_dpll(intel_crtc));
1973
1974 /* FDI must be feeding us bits for PCH ports */
1975 assert_fdi_tx_enabled(dev_priv, pipe);
1976 assert_fdi_rx_enabled(dev_priv, pipe);
1977
1978 if (HAS_PCH_CPT(dev)) {
1979 /* Workaround: Set the timing override bit before enabling the
1980 * pch transcoder. */
1981 reg = TRANS_CHICKEN2(pipe);
1982 val = I915_READ(reg);
1983 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1984 I915_WRITE(reg, val);
1985 }
1986
1987 reg = PCH_TRANSCONF(pipe);
1988 val = I915_READ(reg);
1989 pipeconf_val = I915_READ(PIPECONF(pipe));
1990
1991 if (HAS_PCH_IBX(dev_priv->dev)) {
1992 /*
1993 * Make the BPC in transcoder be consistent with
1994 * that in pipeconf reg. For HDMI we must use 8bpc
1995 * here for both 8bpc and 12bpc.
1996 */
1997 val &= ~PIPECONF_BPC_MASK;
1998 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1999 val |= PIPECONF_8BPC;
2000 else
2001 val |= pipeconf_val & PIPECONF_BPC_MASK;
2002 }
2003
2004 val &= ~TRANS_INTERLACE_MASK;
2005 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2006 if (HAS_PCH_IBX(dev_priv->dev) &&
2007 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2008 val |= TRANS_LEGACY_INTERLACED_ILK;
2009 else
2010 val |= TRANS_INTERLACED;
2011 else
2012 val |= TRANS_PROGRESSIVE;
2013
2014 I915_WRITE(reg, val | TRANS_ENABLE);
2015 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2016 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2017 }
2018
2019 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2020 enum transcoder cpu_transcoder)
2021 {
2022 u32 val, pipeconf_val;
2023
2024 /* PCH only available on ILK+ */
2025 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2026
2027 /* FDI must be feeding us bits for PCH ports */
2028 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2029 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2030
2031 /* Workaround: set timing override bit. */
2032 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2033 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2034 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2035
2036 val = TRANS_ENABLE;
2037 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2038
2039 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2040 PIPECONF_INTERLACED_ILK)
2041 val |= TRANS_INTERLACED;
2042 else
2043 val |= TRANS_PROGRESSIVE;
2044
2045 I915_WRITE(LPT_TRANSCONF, val);
2046 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2047 DRM_ERROR("Failed to enable PCH transcoder\n");
2048 }
2049
2050 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2051 enum pipe pipe)
2052 {
2053 struct drm_device *dev = dev_priv->dev;
2054 i915_reg_t reg;
2055 uint32_t val;
2056
2057 /* FDI relies on the transcoder */
2058 assert_fdi_tx_disabled(dev_priv, pipe);
2059 assert_fdi_rx_disabled(dev_priv, pipe);
2060
2061 /* Ports must be off as well */
2062 assert_pch_ports_disabled(dev_priv, pipe);
2063
2064 reg = PCH_TRANSCONF(pipe);
2065 val = I915_READ(reg);
2066 val &= ~TRANS_ENABLE;
2067 I915_WRITE(reg, val);
2068 /* wait for PCH transcoder off, transcoder state */
2069 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2070 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2071
2072 if (HAS_PCH_CPT(dev)) {
2073 /* Workaround: Clear the timing override chicken bit again. */
2074 reg = TRANS_CHICKEN2(pipe);
2075 val = I915_READ(reg);
2076 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2077 I915_WRITE(reg, val);
2078 }
2079 }
2080
2081 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2082 {
2083 u32 val;
2084
2085 val = I915_READ(LPT_TRANSCONF);
2086 val &= ~TRANS_ENABLE;
2087 I915_WRITE(LPT_TRANSCONF, val);
2088 /* wait for PCH transcoder off, transcoder state */
2089 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2090 DRM_ERROR("Failed to disable PCH transcoder\n");
2091
2092 /* Workaround: clear timing override bit. */
2093 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2094 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2095 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2096 }
2097
2098 /**
2099 * intel_enable_pipe - enable a pipe, asserting requirements
2100 * @crtc: crtc responsible for the pipe
2101 *
2102 * Enable @crtc's pipe, making sure that various hardware specific requirements
2103 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2104 */
2105 static void intel_enable_pipe(struct intel_crtc *crtc)
2106 {
2107 struct drm_device *dev = crtc->base.dev;
2108 struct drm_i915_private *dev_priv = dev->dev_private;
2109 enum pipe pipe = crtc->pipe;
2110 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2111 enum pipe pch_transcoder;
2112 i915_reg_t reg;
2113 u32 val;
2114
2115 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2116
2117 assert_planes_disabled(dev_priv, pipe);
2118 assert_cursor_disabled(dev_priv, pipe);
2119 assert_sprites_disabled(dev_priv, pipe);
2120
2121 if (HAS_PCH_LPT(dev_priv->dev))
2122 pch_transcoder = TRANSCODER_A;
2123 else
2124 pch_transcoder = pipe;
2125
2126 /*
2127 * A pipe without a PLL won't actually be able to drive bits from
2128 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2129 * need the check.
2130 */
2131 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2132 if (crtc->config->has_dsi_encoder)
2133 assert_dsi_pll_enabled(dev_priv);
2134 else
2135 assert_pll_enabled(dev_priv, pipe);
2136 else {
2137 if (crtc->config->has_pch_encoder) {
2138 /* if driving the PCH, we need FDI enabled */
2139 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2140 assert_fdi_tx_pll_enabled(dev_priv,
2141 (enum pipe) cpu_transcoder);
2142 }
2143 /* FIXME: assert CPU port conditions for SNB+ */
2144 }
2145
2146 reg = PIPECONF(cpu_transcoder);
2147 val = I915_READ(reg);
2148 if (val & PIPECONF_ENABLE) {
2149 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2150 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2151 return;
2152 }
2153
2154 I915_WRITE(reg, val | PIPECONF_ENABLE);
2155 POSTING_READ(reg);
2156 }
2157
2158 /**
2159 * intel_disable_pipe - disable a pipe, asserting requirements
2160 * @crtc: crtc whose pipes is to be disabled
2161 *
2162 * Disable the pipe of @crtc, making sure that various hardware
2163 * specific requirements are met, if applicable, e.g. plane
2164 * disabled, panel fitter off, etc.
2165 *
2166 * Will wait until the pipe has shut down before returning.
2167 */
2168 static void intel_disable_pipe(struct intel_crtc *crtc)
2169 {
2170 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2171 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2172 enum pipe pipe = crtc->pipe;
2173 i915_reg_t reg;
2174 u32 val;
2175
2176 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2177
2178 /*
2179 * Make sure planes won't keep trying to pump pixels to us,
2180 * or we might hang the display.
2181 */
2182 assert_planes_disabled(dev_priv, pipe);
2183 assert_cursor_disabled(dev_priv, pipe);
2184 assert_sprites_disabled(dev_priv, pipe);
2185
2186 reg = PIPECONF(cpu_transcoder);
2187 val = I915_READ(reg);
2188 if ((val & PIPECONF_ENABLE) == 0)
2189 return;
2190
2191 /*
2192 * Double wide has implications for planes
2193 * so best keep it disabled when not needed.
2194 */
2195 if (crtc->config->double_wide)
2196 val &= ~PIPECONF_DOUBLE_WIDE;
2197
2198 /* Don't disable pipe or pipe PLLs if needed */
2199 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2200 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2201 val &= ~PIPECONF_ENABLE;
2202
2203 I915_WRITE(reg, val);
2204 if ((val & PIPECONF_ENABLE) == 0)
2205 intel_wait_for_pipe_off(crtc);
2206 }
2207
2208 static bool need_vtd_wa(struct drm_device *dev)
2209 {
2210 #ifdef CONFIG_INTEL_IOMMU
2211 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2212 return true;
2213 #endif
2214 return false;
2215 }
2216
2217 unsigned int
2218 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2219 uint64_t fb_format_modifier, unsigned int plane)
2220 {
2221 unsigned int tile_height;
2222 uint32_t pixel_bytes;
2223
2224 switch (fb_format_modifier) {
2225 case DRM_FORMAT_MOD_NONE:
2226 tile_height = 1;
2227 break;
2228 case I915_FORMAT_MOD_X_TILED:
2229 tile_height = IS_GEN2(dev) ? 16 : 8;
2230 break;
2231 case I915_FORMAT_MOD_Y_TILED:
2232 tile_height = 32;
2233 break;
2234 case I915_FORMAT_MOD_Yf_TILED:
2235 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2236 switch (pixel_bytes) {
2237 default:
2238 case 1:
2239 tile_height = 64;
2240 break;
2241 case 2:
2242 case 4:
2243 tile_height = 32;
2244 break;
2245 case 8:
2246 tile_height = 16;
2247 break;
2248 case 16:
2249 WARN_ONCE(1,
2250 "128-bit pixels are not supported for display!");
2251 tile_height = 16;
2252 break;
2253 }
2254 break;
2255 default:
2256 MISSING_CASE(fb_format_modifier);
2257 tile_height = 1;
2258 break;
2259 }
2260
2261 return tile_height;
2262 }
2263
2264 unsigned int
2265 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2266 uint32_t pixel_format, uint64_t fb_format_modifier)
2267 {
2268 return ALIGN(height, intel_tile_height(dev, pixel_format,
2269 fb_format_modifier, 0));
2270 }
2271
2272 static void
2273 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2274 const struct drm_plane_state *plane_state)
2275 {
2276 struct intel_rotation_info *info = &view->params.rotation_info;
2277 unsigned int tile_height, tile_pitch;
2278
2279 *view = i915_ggtt_view_normal;
2280
2281 if (!plane_state)
2282 return;
2283
2284 if (!intel_rotation_90_or_270(plane_state->rotation))
2285 return;
2286
2287 *view = i915_ggtt_view_rotated;
2288
2289 info->height = fb->height;
2290 info->pixel_format = fb->pixel_format;
2291 info->pitch = fb->pitches[0];
2292 info->uv_offset = fb->offsets[1];
2293 info->fb_modifier = fb->modifier[0];
2294
2295 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2296 fb->modifier[0], 0);
2297 tile_pitch = PAGE_SIZE / tile_height;
2298 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2299 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2300 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2301
2302 if (info->pixel_format == DRM_FORMAT_NV12) {
2303 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2304 fb->modifier[0], 1);
2305 tile_pitch = PAGE_SIZE / tile_height;
2306 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2307 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2308 tile_height);
2309 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2310 PAGE_SIZE;
2311 }
2312 }
2313
2314 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2315 {
2316 if (INTEL_INFO(dev_priv)->gen >= 9)
2317 return 256 * 1024;
2318 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2319 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2320 return 128 * 1024;
2321 else if (INTEL_INFO(dev_priv)->gen >= 4)
2322 return 4 * 1024;
2323 else
2324 return 0;
2325 }
2326
2327 int
2328 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2329 struct drm_framebuffer *fb,
2330 const struct drm_plane_state *plane_state)
2331 {
2332 struct drm_device *dev = fb->dev;
2333 struct drm_i915_private *dev_priv = dev->dev_private;
2334 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2335 struct i915_ggtt_view view;
2336 u32 alignment;
2337 int ret;
2338
2339 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2340
2341 switch (fb->modifier[0]) {
2342 case DRM_FORMAT_MOD_NONE:
2343 alignment = intel_linear_alignment(dev_priv);
2344 break;
2345 case I915_FORMAT_MOD_X_TILED:
2346 if (INTEL_INFO(dev)->gen >= 9)
2347 alignment = 256 * 1024;
2348 else {
2349 /* pin() will align the object as required by fence */
2350 alignment = 0;
2351 }
2352 break;
2353 case I915_FORMAT_MOD_Y_TILED:
2354 case I915_FORMAT_MOD_Yf_TILED:
2355 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2356 "Y tiling bo slipped through, driver bug!\n"))
2357 return -EINVAL;
2358 alignment = 1 * 1024 * 1024;
2359 break;
2360 default:
2361 MISSING_CASE(fb->modifier[0]);
2362 return -EINVAL;
2363 }
2364
2365 intel_fill_fb_ggtt_view(&view, fb, plane_state);
2366
2367 /* Note that the w/a also requires 64 PTE of padding following the
2368 * bo. We currently fill all unused PTE with the shadow page and so
2369 * we should always have valid PTE following the scanout preventing
2370 * the VT-d warning.
2371 */
2372 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2373 alignment = 256 * 1024;
2374
2375 /*
2376 * Global gtt pte registers are special registers which actually forward
2377 * writes to a chunk of system memory. Which means that there is no risk
2378 * that the register values disappear as soon as we call
2379 * intel_runtime_pm_put(), so it is correct to wrap only the
2380 * pin/unpin/fence and not more.
2381 */
2382 intel_runtime_pm_get(dev_priv);
2383
2384 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2385 &view);
2386 if (ret)
2387 goto err_pm;
2388
2389 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2390 * fence, whereas 965+ only requires a fence if using
2391 * framebuffer compression. For simplicity, we always install
2392 * a fence as the cost is not that onerous.
2393 */
2394 if (view.type == I915_GGTT_VIEW_NORMAL) {
2395 ret = i915_gem_object_get_fence(obj);
2396 if (ret == -EDEADLK) {
2397 /*
2398 * -EDEADLK means there are no free fences
2399 * no pending flips.
2400 *
2401 * This is propagated to atomic, but it uses
2402 * -EDEADLK to force a locking recovery, so
2403 * change the returned error to -EBUSY.
2404 */
2405 ret = -EBUSY;
2406 goto err_unpin;
2407 } else if (ret)
2408 goto err_unpin;
2409
2410 i915_gem_object_pin_fence(obj);
2411 }
2412
2413 intel_runtime_pm_put(dev_priv);
2414 return 0;
2415
2416 err_unpin:
2417 i915_gem_object_unpin_from_display_plane(obj, &view);
2418 err_pm:
2419 intel_runtime_pm_put(dev_priv);
2420 return ret;
2421 }
2422
2423 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2424 const struct drm_plane_state *plane_state)
2425 {
2426 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2427 struct i915_ggtt_view view;
2428
2429 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2430
2431 intel_fill_fb_ggtt_view(&view, fb, plane_state);
2432
2433 if (view.type == I915_GGTT_VIEW_NORMAL)
2434 i915_gem_object_unpin_fence(obj);
2435
2436 i915_gem_object_unpin_from_display_plane(obj, &view);
2437 }
2438
2439 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2440 * is assumed to be a power-of-two. */
2441 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2442 int *x, int *y,
2443 unsigned int tiling_mode,
2444 unsigned int cpp,
2445 unsigned int pitch)
2446 {
2447 if (tiling_mode != I915_TILING_NONE) {
2448 unsigned int tile_rows, tiles;
2449
2450 tile_rows = *y / 8;
2451 *y %= 8;
2452
2453 tiles = *x / (512/cpp);
2454 *x %= 512/cpp;
2455
2456 return tile_rows * pitch * 8 + tiles * 4096;
2457 } else {
2458 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2459 unsigned int offset;
2460
2461 offset = *y * pitch + *x * cpp;
2462 *y = (offset & alignment) / pitch;
2463 *x = ((offset & alignment) - *y * pitch) / cpp;
2464 return offset & ~alignment;
2465 }
2466 }
2467
2468 static int i9xx_format_to_fourcc(int format)
2469 {
2470 switch (format) {
2471 case DISPPLANE_8BPP:
2472 return DRM_FORMAT_C8;
2473 case DISPPLANE_BGRX555:
2474 return DRM_FORMAT_XRGB1555;
2475 case DISPPLANE_BGRX565:
2476 return DRM_FORMAT_RGB565;
2477 default:
2478 case DISPPLANE_BGRX888:
2479 return DRM_FORMAT_XRGB8888;
2480 case DISPPLANE_RGBX888:
2481 return DRM_FORMAT_XBGR8888;
2482 case DISPPLANE_BGRX101010:
2483 return DRM_FORMAT_XRGB2101010;
2484 case DISPPLANE_RGBX101010:
2485 return DRM_FORMAT_XBGR2101010;
2486 }
2487 }
2488
2489 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2490 {
2491 switch (format) {
2492 case PLANE_CTL_FORMAT_RGB_565:
2493 return DRM_FORMAT_RGB565;
2494 default:
2495 case PLANE_CTL_FORMAT_XRGB_8888:
2496 if (rgb_order) {
2497 if (alpha)
2498 return DRM_FORMAT_ABGR8888;
2499 else
2500 return DRM_FORMAT_XBGR8888;
2501 } else {
2502 if (alpha)
2503 return DRM_FORMAT_ARGB8888;
2504 else
2505 return DRM_FORMAT_XRGB8888;
2506 }
2507 case PLANE_CTL_FORMAT_XRGB_2101010:
2508 if (rgb_order)
2509 return DRM_FORMAT_XBGR2101010;
2510 else
2511 return DRM_FORMAT_XRGB2101010;
2512 }
2513 }
2514
2515 static bool
2516 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2517 struct intel_initial_plane_config *plane_config)
2518 {
2519 struct drm_device *dev = crtc->base.dev;
2520 struct drm_i915_private *dev_priv = to_i915(dev);
2521 struct drm_i915_gem_object *obj = NULL;
2522 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2523 struct drm_framebuffer *fb = &plane_config->fb->base;
2524 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2525 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2526 PAGE_SIZE);
2527
2528 size_aligned -= base_aligned;
2529
2530 if (plane_config->size == 0)
2531 return false;
2532
2533 /* If the FB is too big, just don't use it since fbdev is not very
2534 * important and we should probably use that space with FBC or other
2535 * features. */
2536 if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2537 return false;
2538
2539 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2540 base_aligned,
2541 base_aligned,
2542 size_aligned);
2543 if (!obj)
2544 return false;
2545
2546 obj->tiling_mode = plane_config->tiling;
2547 if (obj->tiling_mode == I915_TILING_X)
2548 obj->stride = fb->pitches[0];
2549
2550 mode_cmd.pixel_format = fb->pixel_format;
2551 mode_cmd.width = fb->width;
2552 mode_cmd.height = fb->height;
2553 mode_cmd.pitches[0] = fb->pitches[0];
2554 mode_cmd.modifier[0] = fb->modifier[0];
2555 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2556
2557 mutex_lock(&dev->struct_mutex);
2558 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2559 &mode_cmd, obj)) {
2560 DRM_DEBUG_KMS("intel fb init failed\n");
2561 goto out_unref_obj;
2562 }
2563 mutex_unlock(&dev->struct_mutex);
2564
2565 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2566 return true;
2567
2568 out_unref_obj:
2569 drm_gem_object_unreference(&obj->base);
2570 mutex_unlock(&dev->struct_mutex);
2571 return false;
2572 }
2573
2574 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2575 static void
2576 update_state_fb(struct drm_plane *plane)
2577 {
2578 if (plane->fb == plane->state->fb)
2579 return;
2580
2581 if (plane->state->fb)
2582 drm_framebuffer_unreference(plane->state->fb);
2583 plane->state->fb = plane->fb;
2584 if (plane->state->fb)
2585 drm_framebuffer_reference(plane->state->fb);
2586 }
2587
2588 static void
2589 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2590 struct intel_initial_plane_config *plane_config)
2591 {
2592 struct drm_device *dev = intel_crtc->base.dev;
2593 struct drm_i915_private *dev_priv = dev->dev_private;
2594 struct drm_crtc *c;
2595 struct intel_crtc *i;
2596 struct drm_i915_gem_object *obj;
2597 struct drm_plane *primary = intel_crtc->base.primary;
2598 struct drm_plane_state *plane_state = primary->state;
2599 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2600 struct intel_plane *intel_plane = to_intel_plane(primary);
2601 struct drm_framebuffer *fb;
2602
2603 if (!plane_config->fb)
2604 return;
2605
2606 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2607 fb = &plane_config->fb->base;
2608 goto valid_fb;
2609 }
2610
2611 kfree(plane_config->fb);
2612
2613 /*
2614 * Failed to alloc the obj, check to see if we should share
2615 * an fb with another CRTC instead
2616 */
2617 for_each_crtc(dev, c) {
2618 i = to_intel_crtc(c);
2619
2620 if (c == &intel_crtc->base)
2621 continue;
2622
2623 if (!i->active)
2624 continue;
2625
2626 fb = c->primary->fb;
2627 if (!fb)
2628 continue;
2629
2630 obj = intel_fb_obj(fb);
2631 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2632 drm_framebuffer_reference(fb);
2633 goto valid_fb;
2634 }
2635 }
2636
2637 /*
2638 * We've failed to reconstruct the BIOS FB. Current display state
2639 * indicates that the primary plane is visible, but has a NULL FB,
2640 * which will lead to problems later if we don't fix it up. The
2641 * simplest solution is to just disable the primary plane now and
2642 * pretend the BIOS never had it enabled.
2643 */
2644 to_intel_plane_state(plane_state)->visible = false;
2645 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2646 intel_pre_disable_primary(&intel_crtc->base);
2647 intel_plane->disable_plane(primary, &intel_crtc->base);
2648
2649 return;
2650
2651 valid_fb:
2652 plane_state->src_x = 0;
2653 plane_state->src_y = 0;
2654 plane_state->src_w = fb->width << 16;
2655 plane_state->src_h = fb->height << 16;
2656
2657 plane_state->crtc_x = 0;
2658 plane_state->crtc_y = 0;
2659 plane_state->crtc_w = fb->width;
2660 plane_state->crtc_h = fb->height;
2661
2662 obj = intel_fb_obj(fb);
2663 if (obj->tiling_mode != I915_TILING_NONE)
2664 dev_priv->preserve_bios_swizzle = true;
2665
2666 drm_framebuffer_reference(fb);
2667 primary->fb = primary->state->fb = fb;
2668 primary->crtc = primary->state->crtc = &intel_crtc->base;
2669 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2670 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2671 }
2672
2673 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2674 struct drm_framebuffer *fb,
2675 int x, int y)
2676 {
2677 struct drm_device *dev = crtc->dev;
2678 struct drm_i915_private *dev_priv = dev->dev_private;
2679 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2680 struct drm_plane *primary = crtc->primary;
2681 bool visible = to_intel_plane_state(primary->state)->visible;
2682 struct drm_i915_gem_object *obj;
2683 int plane = intel_crtc->plane;
2684 unsigned long linear_offset;
2685 u32 dspcntr;
2686 i915_reg_t reg = DSPCNTR(plane);
2687 int pixel_size;
2688
2689 if (!visible || !fb) {
2690 I915_WRITE(reg, 0);
2691 if (INTEL_INFO(dev)->gen >= 4)
2692 I915_WRITE(DSPSURF(plane), 0);
2693 else
2694 I915_WRITE(DSPADDR(plane), 0);
2695 POSTING_READ(reg);
2696 return;
2697 }
2698
2699 obj = intel_fb_obj(fb);
2700 if (WARN_ON(obj == NULL))
2701 return;
2702
2703 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2704
2705 dspcntr = DISPPLANE_GAMMA_ENABLE;
2706
2707 dspcntr |= DISPLAY_PLANE_ENABLE;
2708
2709 if (INTEL_INFO(dev)->gen < 4) {
2710 if (intel_crtc->pipe == PIPE_B)
2711 dspcntr |= DISPPLANE_SEL_PIPE_B;
2712
2713 /* pipesrc and dspsize control the size that is scaled from,
2714 * which should always be the user's requested size.
2715 */
2716 I915_WRITE(DSPSIZE(plane),
2717 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2718 (intel_crtc->config->pipe_src_w - 1));
2719 I915_WRITE(DSPPOS(plane), 0);
2720 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2721 I915_WRITE(PRIMSIZE(plane),
2722 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2723 (intel_crtc->config->pipe_src_w - 1));
2724 I915_WRITE(PRIMPOS(plane), 0);
2725 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2726 }
2727
2728 switch (fb->pixel_format) {
2729 case DRM_FORMAT_C8:
2730 dspcntr |= DISPPLANE_8BPP;
2731 break;
2732 case DRM_FORMAT_XRGB1555:
2733 dspcntr |= DISPPLANE_BGRX555;
2734 break;
2735 case DRM_FORMAT_RGB565:
2736 dspcntr |= DISPPLANE_BGRX565;
2737 break;
2738 case DRM_FORMAT_XRGB8888:
2739 dspcntr |= DISPPLANE_BGRX888;
2740 break;
2741 case DRM_FORMAT_XBGR8888:
2742 dspcntr |= DISPPLANE_RGBX888;
2743 break;
2744 case DRM_FORMAT_XRGB2101010:
2745 dspcntr |= DISPPLANE_BGRX101010;
2746 break;
2747 case DRM_FORMAT_XBGR2101010:
2748 dspcntr |= DISPPLANE_RGBX101010;
2749 break;
2750 default:
2751 BUG();
2752 }
2753
2754 if (INTEL_INFO(dev)->gen >= 4 &&
2755 obj->tiling_mode != I915_TILING_NONE)
2756 dspcntr |= DISPPLANE_TILED;
2757
2758 if (IS_G4X(dev))
2759 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2760
2761 linear_offset = y * fb->pitches[0] + x * pixel_size;
2762
2763 if (INTEL_INFO(dev)->gen >= 4) {
2764 intel_crtc->dspaddr_offset =
2765 intel_gen4_compute_page_offset(dev_priv,
2766 &x, &y, obj->tiling_mode,
2767 pixel_size,
2768 fb->pitches[0]);
2769 linear_offset -= intel_crtc->dspaddr_offset;
2770 } else {
2771 intel_crtc->dspaddr_offset = linear_offset;
2772 }
2773
2774 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2775 dspcntr |= DISPPLANE_ROTATE_180;
2776
2777 x += (intel_crtc->config->pipe_src_w - 1);
2778 y += (intel_crtc->config->pipe_src_h - 1);
2779
2780 /* Finding the last pixel of the last line of the display
2781 data and adding to linear_offset*/
2782 linear_offset +=
2783 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2784 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2785 }
2786
2787 intel_crtc->adjusted_x = x;
2788 intel_crtc->adjusted_y = y;
2789
2790 I915_WRITE(reg, dspcntr);
2791
2792 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2793 if (INTEL_INFO(dev)->gen >= 4) {
2794 I915_WRITE(DSPSURF(plane),
2795 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2796 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2797 I915_WRITE(DSPLINOFF(plane), linear_offset);
2798 } else
2799 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2800 POSTING_READ(reg);
2801 }
2802
2803 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2804 struct drm_framebuffer *fb,
2805 int x, int y)
2806 {
2807 struct drm_device *dev = crtc->dev;
2808 struct drm_i915_private *dev_priv = dev->dev_private;
2809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2810 struct drm_plane *primary = crtc->primary;
2811 bool visible = to_intel_plane_state(primary->state)->visible;
2812 struct drm_i915_gem_object *obj;
2813 int plane = intel_crtc->plane;
2814 unsigned long linear_offset;
2815 u32 dspcntr;
2816 i915_reg_t reg = DSPCNTR(plane);
2817 int pixel_size;
2818
2819 if (!visible || !fb) {
2820 I915_WRITE(reg, 0);
2821 I915_WRITE(DSPSURF(plane), 0);
2822 POSTING_READ(reg);
2823 return;
2824 }
2825
2826 obj = intel_fb_obj(fb);
2827 if (WARN_ON(obj == NULL))
2828 return;
2829
2830 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2831
2832 dspcntr = DISPPLANE_GAMMA_ENABLE;
2833
2834 dspcntr |= DISPLAY_PLANE_ENABLE;
2835
2836 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2837 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2838
2839 switch (fb->pixel_format) {
2840 case DRM_FORMAT_C8:
2841 dspcntr |= DISPPLANE_8BPP;
2842 break;
2843 case DRM_FORMAT_RGB565:
2844 dspcntr |= DISPPLANE_BGRX565;
2845 break;
2846 case DRM_FORMAT_XRGB8888:
2847 dspcntr |= DISPPLANE_BGRX888;
2848 break;
2849 case DRM_FORMAT_XBGR8888:
2850 dspcntr |= DISPPLANE_RGBX888;
2851 break;
2852 case DRM_FORMAT_XRGB2101010:
2853 dspcntr |= DISPPLANE_BGRX101010;
2854 break;
2855 case DRM_FORMAT_XBGR2101010:
2856 dspcntr |= DISPPLANE_RGBX101010;
2857 break;
2858 default:
2859 BUG();
2860 }
2861
2862 if (obj->tiling_mode != I915_TILING_NONE)
2863 dspcntr |= DISPPLANE_TILED;
2864
2865 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2866 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2867
2868 linear_offset = y * fb->pitches[0] + x * pixel_size;
2869 intel_crtc->dspaddr_offset =
2870 intel_gen4_compute_page_offset(dev_priv,
2871 &x, &y, obj->tiling_mode,
2872 pixel_size,
2873 fb->pitches[0]);
2874 linear_offset -= intel_crtc->dspaddr_offset;
2875 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2876 dspcntr |= DISPPLANE_ROTATE_180;
2877
2878 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2879 x += (intel_crtc->config->pipe_src_w - 1);
2880 y += (intel_crtc->config->pipe_src_h - 1);
2881
2882 /* Finding the last pixel of the last line of the display
2883 data and adding to linear_offset*/
2884 linear_offset +=
2885 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2886 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2887 }
2888 }
2889
2890 intel_crtc->adjusted_x = x;
2891 intel_crtc->adjusted_y = y;
2892
2893 I915_WRITE(reg, dspcntr);
2894
2895 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2896 I915_WRITE(DSPSURF(plane),
2897 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2898 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2899 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2900 } else {
2901 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2902 I915_WRITE(DSPLINOFF(plane), linear_offset);
2903 }
2904 POSTING_READ(reg);
2905 }
2906
2907 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2908 uint32_t pixel_format)
2909 {
2910 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2911
2912 /*
2913 * The stride is either expressed as a multiple of 64 bytes
2914 * chunks for linear buffers or in number of tiles for tiled
2915 * buffers.
2916 */
2917 switch (fb_modifier) {
2918 case DRM_FORMAT_MOD_NONE:
2919 return 64;
2920 case I915_FORMAT_MOD_X_TILED:
2921 if (INTEL_INFO(dev)->gen == 2)
2922 return 128;
2923 return 512;
2924 case I915_FORMAT_MOD_Y_TILED:
2925 /* No need to check for old gens and Y tiling since this is
2926 * about the display engine and those will be blocked before
2927 * we get here.
2928 */
2929 return 128;
2930 case I915_FORMAT_MOD_Yf_TILED:
2931 if (bits_per_pixel == 8)
2932 return 64;
2933 else
2934 return 128;
2935 default:
2936 MISSING_CASE(fb_modifier);
2937 return 64;
2938 }
2939 }
2940
2941 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2942 struct drm_i915_gem_object *obj,
2943 unsigned int plane)
2944 {
2945 struct i915_ggtt_view view;
2946 struct i915_vma *vma;
2947 u64 offset;
2948
2949 intel_fill_fb_ggtt_view(&view, intel_plane->base.fb,
2950 intel_plane->base.state);
2951
2952 vma = i915_gem_obj_to_ggtt_view(obj, &view);
2953 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2954 view.type))
2955 return -1;
2956
2957 offset = vma->node.start;
2958
2959 if (plane == 1) {
2960 offset += vma->ggtt_view.params.rotation_info.uv_start_page *
2961 PAGE_SIZE;
2962 }
2963
2964 WARN_ON(upper_32_bits(offset));
2965
2966 return lower_32_bits(offset);
2967 }
2968
2969 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2970 {
2971 struct drm_device *dev = intel_crtc->base.dev;
2972 struct drm_i915_private *dev_priv = dev->dev_private;
2973
2974 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2975 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2976 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2977 }
2978
2979 /*
2980 * This function detaches (aka. unbinds) unused scalers in hardware
2981 */
2982 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2983 {
2984 struct intel_crtc_scaler_state *scaler_state;
2985 int i;
2986
2987 scaler_state = &intel_crtc->config->scaler_state;
2988
2989 /* loop through and disable scalers that aren't in use */
2990 for (i = 0; i < intel_crtc->num_scalers; i++) {
2991 if (!scaler_state->scalers[i].in_use)
2992 skl_detach_scaler(intel_crtc, i);
2993 }
2994 }
2995
2996 u32 skl_plane_ctl_format(uint32_t pixel_format)
2997 {
2998 switch (pixel_format) {
2999 case DRM_FORMAT_C8:
3000 return PLANE_CTL_FORMAT_INDEXED;
3001 case DRM_FORMAT_RGB565:
3002 return PLANE_CTL_FORMAT_RGB_565;
3003 case DRM_FORMAT_XBGR8888:
3004 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3005 case DRM_FORMAT_XRGB8888:
3006 return PLANE_CTL_FORMAT_XRGB_8888;
3007 /*
3008 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3009 * to be already pre-multiplied. We need to add a knob (or a different
3010 * DRM_FORMAT) for user-space to configure that.
3011 */
3012 case DRM_FORMAT_ABGR8888:
3013 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3014 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3015 case DRM_FORMAT_ARGB8888:
3016 return PLANE_CTL_FORMAT_XRGB_8888 |
3017 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3018 case DRM_FORMAT_XRGB2101010:
3019 return PLANE_CTL_FORMAT_XRGB_2101010;
3020 case DRM_FORMAT_XBGR2101010:
3021 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3022 case DRM_FORMAT_YUYV:
3023 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3024 case DRM_FORMAT_YVYU:
3025 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3026 case DRM_FORMAT_UYVY:
3027 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3028 case DRM_FORMAT_VYUY:
3029 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3030 default:
3031 MISSING_CASE(pixel_format);
3032 }
3033
3034 return 0;
3035 }
3036
3037 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3038 {
3039 switch (fb_modifier) {
3040 case DRM_FORMAT_MOD_NONE:
3041 break;
3042 case I915_FORMAT_MOD_X_TILED:
3043 return PLANE_CTL_TILED_X;
3044 case I915_FORMAT_MOD_Y_TILED:
3045 return PLANE_CTL_TILED_Y;
3046 case I915_FORMAT_MOD_Yf_TILED:
3047 return PLANE_CTL_TILED_YF;
3048 default:
3049 MISSING_CASE(fb_modifier);
3050 }
3051
3052 return 0;
3053 }
3054
3055 u32 skl_plane_ctl_rotation(unsigned int rotation)
3056 {
3057 switch (rotation) {
3058 case BIT(DRM_ROTATE_0):
3059 break;
3060 /*
3061 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3062 * while i915 HW rotation is clockwise, thats why this swapping.
3063 */
3064 case BIT(DRM_ROTATE_90):
3065 return PLANE_CTL_ROTATE_270;
3066 case BIT(DRM_ROTATE_180):
3067 return PLANE_CTL_ROTATE_180;
3068 case BIT(DRM_ROTATE_270):
3069 return PLANE_CTL_ROTATE_90;
3070 default:
3071 MISSING_CASE(rotation);
3072 }
3073
3074 return 0;
3075 }
3076
3077 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3078 struct drm_framebuffer *fb,
3079 int x, int y)
3080 {
3081 struct drm_device *dev = crtc->dev;
3082 struct drm_i915_private *dev_priv = dev->dev_private;
3083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3084 struct drm_plane *plane = crtc->primary;
3085 bool visible = to_intel_plane_state(plane->state)->visible;
3086 struct drm_i915_gem_object *obj;
3087 int pipe = intel_crtc->pipe;
3088 u32 plane_ctl, stride_div, stride;
3089 u32 tile_height, plane_offset, plane_size;
3090 unsigned int rotation;
3091 int x_offset, y_offset;
3092 u32 surf_addr;
3093 struct intel_crtc_state *crtc_state = intel_crtc->config;
3094 struct intel_plane_state *plane_state;
3095 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3096 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3097 int scaler_id = -1;
3098
3099 plane_state = to_intel_plane_state(plane->state);
3100
3101 if (!visible || !fb) {
3102 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3103 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3104 POSTING_READ(PLANE_CTL(pipe, 0));
3105 return;
3106 }
3107
3108 plane_ctl = PLANE_CTL_ENABLE |
3109 PLANE_CTL_PIPE_GAMMA_ENABLE |
3110 PLANE_CTL_PIPE_CSC_ENABLE;
3111
3112 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3113 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3114 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3115
3116 rotation = plane->state->rotation;
3117 plane_ctl |= skl_plane_ctl_rotation(rotation);
3118
3119 obj = intel_fb_obj(fb);
3120 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3121 fb->pixel_format);
3122 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3123
3124 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3125
3126 scaler_id = plane_state->scaler_id;
3127 src_x = plane_state->src.x1 >> 16;
3128 src_y = plane_state->src.y1 >> 16;
3129 src_w = drm_rect_width(&plane_state->src) >> 16;
3130 src_h = drm_rect_height(&plane_state->src) >> 16;
3131 dst_x = plane_state->dst.x1;
3132 dst_y = plane_state->dst.y1;
3133 dst_w = drm_rect_width(&plane_state->dst);
3134 dst_h = drm_rect_height(&plane_state->dst);
3135
3136 WARN_ON(x != src_x || y != src_y);
3137
3138 if (intel_rotation_90_or_270(rotation)) {
3139 /* stride = Surface height in tiles */
3140 tile_height = intel_tile_height(dev, fb->pixel_format,
3141 fb->modifier[0], 0);
3142 stride = DIV_ROUND_UP(fb->height, tile_height);
3143 x_offset = stride * tile_height - y - src_h;
3144 y_offset = x;
3145 plane_size = (src_w - 1) << 16 | (src_h - 1);
3146 } else {
3147 stride = fb->pitches[0] / stride_div;
3148 x_offset = x;
3149 y_offset = y;
3150 plane_size = (src_h - 1) << 16 | (src_w - 1);
3151 }
3152 plane_offset = y_offset << 16 | x_offset;
3153
3154 intel_crtc->adjusted_x = x_offset;
3155 intel_crtc->adjusted_y = y_offset;
3156
3157 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3158 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3159 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3160 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3161
3162 if (scaler_id >= 0) {
3163 uint32_t ps_ctrl = 0;
3164
3165 WARN_ON(!dst_w || !dst_h);
3166 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3167 crtc_state->scaler_state.scalers[scaler_id].mode;
3168 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3169 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3170 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3171 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3172 I915_WRITE(PLANE_POS(pipe, 0), 0);
3173 } else {
3174 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3175 }
3176
3177 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3178
3179 POSTING_READ(PLANE_SURF(pipe, 0));
3180 }
3181
3182 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3183 static int
3184 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3185 int x, int y, enum mode_set_atomic state)
3186 {
3187 struct drm_device *dev = crtc->dev;
3188 struct drm_i915_private *dev_priv = dev->dev_private;
3189
3190 if (dev_priv->fbc.deactivate)
3191 dev_priv->fbc.deactivate(dev_priv);
3192
3193 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3194
3195 return 0;
3196 }
3197
3198 static void intel_complete_page_flips(struct drm_device *dev)
3199 {
3200 struct drm_crtc *crtc;
3201
3202 for_each_crtc(dev, crtc) {
3203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3204 enum plane plane = intel_crtc->plane;
3205
3206 intel_prepare_page_flip(dev, plane);
3207 intel_finish_page_flip_plane(dev, plane);
3208 }
3209 }
3210
3211 static void intel_update_primary_planes(struct drm_device *dev)
3212 {
3213 struct drm_crtc *crtc;
3214
3215 for_each_crtc(dev, crtc) {
3216 struct intel_plane *plane = to_intel_plane(crtc->primary);
3217 struct intel_plane_state *plane_state;
3218
3219 drm_modeset_lock_crtc(crtc, &plane->base);
3220 plane_state = to_intel_plane_state(plane->base.state);
3221
3222 if (crtc->state->active && plane_state->base.fb)
3223 plane->commit_plane(&plane->base, plane_state);
3224
3225 drm_modeset_unlock_crtc(crtc);
3226 }
3227 }
3228
3229 void intel_prepare_reset(struct drm_device *dev)
3230 {
3231 /* no reset support for gen2 */
3232 if (IS_GEN2(dev))
3233 return;
3234
3235 /* reset doesn't touch the display */
3236 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3237 return;
3238
3239 drm_modeset_lock_all(dev);
3240 /*
3241 * Disabling the crtcs gracefully seems nicer. Also the
3242 * g33 docs say we should at least disable all the planes.
3243 */
3244 intel_display_suspend(dev);
3245 }
3246
3247 void intel_finish_reset(struct drm_device *dev)
3248 {
3249 struct drm_i915_private *dev_priv = to_i915(dev);
3250
3251 /*
3252 * Flips in the rings will be nuked by the reset,
3253 * so complete all pending flips so that user space
3254 * will get its events and not get stuck.
3255 */
3256 intel_complete_page_flips(dev);
3257
3258 /* no reset support for gen2 */
3259 if (IS_GEN2(dev))
3260 return;
3261
3262 /* reset doesn't touch the display */
3263 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3264 /*
3265 * Flips in the rings have been nuked by the reset,
3266 * so update the base address of all primary
3267 * planes to the the last fb to make sure we're
3268 * showing the correct fb after a reset.
3269 *
3270 * FIXME: Atomic will make this obsolete since we won't schedule
3271 * CS-based flips (which might get lost in gpu resets) any more.
3272 */
3273 intel_update_primary_planes(dev);
3274 return;
3275 }
3276
3277 /*
3278 * The display has been reset as well,
3279 * so need a full re-initialization.
3280 */
3281 intel_runtime_pm_disable_interrupts(dev_priv);
3282 intel_runtime_pm_enable_interrupts(dev_priv);
3283
3284 intel_modeset_init_hw(dev);
3285
3286 spin_lock_irq(&dev_priv->irq_lock);
3287 if (dev_priv->display.hpd_irq_setup)
3288 dev_priv->display.hpd_irq_setup(dev);
3289 spin_unlock_irq(&dev_priv->irq_lock);
3290
3291 intel_display_resume(dev);
3292
3293 intel_hpd_init(dev_priv);
3294
3295 drm_modeset_unlock_all(dev);
3296 }
3297
3298 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3299 {
3300 struct drm_device *dev = crtc->dev;
3301 struct drm_i915_private *dev_priv = dev->dev_private;
3302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3303 bool pending;
3304
3305 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3306 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3307 return false;
3308
3309 spin_lock_irq(&dev->event_lock);
3310 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3311 spin_unlock_irq(&dev->event_lock);
3312
3313 return pending;
3314 }
3315
3316 static void intel_update_pipe_config(struct intel_crtc *crtc,
3317 struct intel_crtc_state *old_crtc_state)
3318 {
3319 struct drm_device *dev = crtc->base.dev;
3320 struct drm_i915_private *dev_priv = dev->dev_private;
3321 struct intel_crtc_state *pipe_config =
3322 to_intel_crtc_state(crtc->base.state);
3323
3324 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3325 crtc->base.mode = crtc->base.state->mode;
3326
3327 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3328 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3329 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3330
3331 if (HAS_DDI(dev))
3332 intel_set_pipe_csc(&crtc->base);
3333
3334 /*
3335 * Update pipe size and adjust fitter if needed: the reason for this is
3336 * that in compute_mode_changes we check the native mode (not the pfit
3337 * mode) to see if we can flip rather than do a full mode set. In the
3338 * fastboot case, we'll flip, but if we don't update the pipesrc and
3339 * pfit state, we'll end up with a big fb scanned out into the wrong
3340 * sized surface.
3341 */
3342
3343 I915_WRITE(PIPESRC(crtc->pipe),
3344 ((pipe_config->pipe_src_w - 1) << 16) |
3345 (pipe_config->pipe_src_h - 1));
3346
3347 /* on skylake this is done by detaching scalers */
3348 if (INTEL_INFO(dev)->gen >= 9) {
3349 skl_detach_scalers(crtc);
3350
3351 if (pipe_config->pch_pfit.enabled)
3352 skylake_pfit_enable(crtc);
3353 } else if (HAS_PCH_SPLIT(dev)) {
3354 if (pipe_config->pch_pfit.enabled)
3355 ironlake_pfit_enable(crtc);
3356 else if (old_crtc_state->pch_pfit.enabled)
3357 ironlake_pfit_disable(crtc, true);
3358 }
3359 }
3360
3361 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3362 {
3363 struct drm_device *dev = crtc->dev;
3364 struct drm_i915_private *dev_priv = dev->dev_private;
3365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3366 int pipe = intel_crtc->pipe;
3367 i915_reg_t reg;
3368 u32 temp;
3369
3370 /* enable normal train */
3371 reg = FDI_TX_CTL(pipe);
3372 temp = I915_READ(reg);
3373 if (IS_IVYBRIDGE(dev)) {
3374 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3375 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3376 } else {
3377 temp &= ~FDI_LINK_TRAIN_NONE;
3378 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3379 }
3380 I915_WRITE(reg, temp);
3381
3382 reg = FDI_RX_CTL(pipe);
3383 temp = I915_READ(reg);
3384 if (HAS_PCH_CPT(dev)) {
3385 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3386 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3387 } else {
3388 temp &= ~FDI_LINK_TRAIN_NONE;
3389 temp |= FDI_LINK_TRAIN_NONE;
3390 }
3391 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3392
3393 /* wait one idle pattern time */
3394 POSTING_READ(reg);
3395 udelay(1000);
3396
3397 /* IVB wants error correction enabled */
3398 if (IS_IVYBRIDGE(dev))
3399 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3400 FDI_FE_ERRC_ENABLE);
3401 }
3402
3403 /* The FDI link training functions for ILK/Ibexpeak. */
3404 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3405 {
3406 struct drm_device *dev = crtc->dev;
3407 struct drm_i915_private *dev_priv = dev->dev_private;
3408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3409 int pipe = intel_crtc->pipe;
3410 i915_reg_t reg;
3411 u32 temp, tries;
3412
3413 /* FDI needs bits from pipe first */
3414 assert_pipe_enabled(dev_priv, pipe);
3415
3416 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3417 for train result */
3418 reg = FDI_RX_IMR(pipe);
3419 temp = I915_READ(reg);
3420 temp &= ~FDI_RX_SYMBOL_LOCK;
3421 temp &= ~FDI_RX_BIT_LOCK;
3422 I915_WRITE(reg, temp);
3423 I915_READ(reg);
3424 udelay(150);
3425
3426 /* enable CPU FDI TX and PCH FDI RX */
3427 reg = FDI_TX_CTL(pipe);
3428 temp = I915_READ(reg);
3429 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3430 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3431 temp &= ~FDI_LINK_TRAIN_NONE;
3432 temp |= FDI_LINK_TRAIN_PATTERN_1;
3433 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3434
3435 reg = FDI_RX_CTL(pipe);
3436 temp = I915_READ(reg);
3437 temp &= ~FDI_LINK_TRAIN_NONE;
3438 temp |= FDI_LINK_TRAIN_PATTERN_1;
3439 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3440
3441 POSTING_READ(reg);
3442 udelay(150);
3443
3444 /* Ironlake workaround, enable clock pointer after FDI enable*/
3445 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3446 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3447 FDI_RX_PHASE_SYNC_POINTER_EN);
3448
3449 reg = FDI_RX_IIR(pipe);
3450 for (tries = 0; tries < 5; tries++) {
3451 temp = I915_READ(reg);
3452 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3453
3454 if ((temp & FDI_RX_BIT_LOCK)) {
3455 DRM_DEBUG_KMS("FDI train 1 done.\n");
3456 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3457 break;
3458 }
3459 }
3460 if (tries == 5)
3461 DRM_ERROR("FDI train 1 fail!\n");
3462
3463 /* Train 2 */
3464 reg = FDI_TX_CTL(pipe);
3465 temp = I915_READ(reg);
3466 temp &= ~FDI_LINK_TRAIN_NONE;
3467 temp |= FDI_LINK_TRAIN_PATTERN_2;
3468 I915_WRITE(reg, temp);
3469
3470 reg = FDI_RX_CTL(pipe);
3471 temp = I915_READ(reg);
3472 temp &= ~FDI_LINK_TRAIN_NONE;
3473 temp |= FDI_LINK_TRAIN_PATTERN_2;
3474 I915_WRITE(reg, temp);
3475
3476 POSTING_READ(reg);
3477 udelay(150);
3478
3479 reg = FDI_RX_IIR(pipe);
3480 for (tries = 0; tries < 5; tries++) {
3481 temp = I915_READ(reg);
3482 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3483
3484 if (temp & FDI_RX_SYMBOL_LOCK) {
3485 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3486 DRM_DEBUG_KMS("FDI train 2 done.\n");
3487 break;
3488 }
3489 }
3490 if (tries == 5)
3491 DRM_ERROR("FDI train 2 fail!\n");
3492
3493 DRM_DEBUG_KMS("FDI train done\n");
3494
3495 }
3496
3497 static const int snb_b_fdi_train_param[] = {
3498 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3499 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3500 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3501 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3502 };
3503
3504 /* The FDI link training functions for SNB/Cougarpoint. */
3505 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3506 {
3507 struct drm_device *dev = crtc->dev;
3508 struct drm_i915_private *dev_priv = dev->dev_private;
3509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3510 int pipe = intel_crtc->pipe;
3511 i915_reg_t reg;
3512 u32 temp, i, retry;
3513
3514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3515 for train result */
3516 reg = FDI_RX_IMR(pipe);
3517 temp = I915_READ(reg);
3518 temp &= ~FDI_RX_SYMBOL_LOCK;
3519 temp &= ~FDI_RX_BIT_LOCK;
3520 I915_WRITE(reg, temp);
3521
3522 POSTING_READ(reg);
3523 udelay(150);
3524
3525 /* enable CPU FDI TX and PCH FDI RX */
3526 reg = FDI_TX_CTL(pipe);
3527 temp = I915_READ(reg);
3528 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3529 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3530 temp &= ~FDI_LINK_TRAIN_NONE;
3531 temp |= FDI_LINK_TRAIN_PATTERN_1;
3532 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3533 /* SNB-B */
3534 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3535 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3536
3537 I915_WRITE(FDI_RX_MISC(pipe),
3538 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3539
3540 reg = FDI_RX_CTL(pipe);
3541 temp = I915_READ(reg);
3542 if (HAS_PCH_CPT(dev)) {
3543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3544 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3545 } else {
3546 temp &= ~FDI_LINK_TRAIN_NONE;
3547 temp |= FDI_LINK_TRAIN_PATTERN_1;
3548 }
3549 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3550
3551 POSTING_READ(reg);
3552 udelay(150);
3553
3554 for (i = 0; i < 4; i++) {
3555 reg = FDI_TX_CTL(pipe);
3556 temp = I915_READ(reg);
3557 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3558 temp |= snb_b_fdi_train_param[i];
3559 I915_WRITE(reg, temp);
3560
3561 POSTING_READ(reg);
3562 udelay(500);
3563
3564 for (retry = 0; retry < 5; retry++) {
3565 reg = FDI_RX_IIR(pipe);
3566 temp = I915_READ(reg);
3567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3568 if (temp & FDI_RX_BIT_LOCK) {
3569 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3570 DRM_DEBUG_KMS("FDI train 1 done.\n");
3571 break;
3572 }
3573 udelay(50);
3574 }
3575 if (retry < 5)
3576 break;
3577 }
3578 if (i == 4)
3579 DRM_ERROR("FDI train 1 fail!\n");
3580
3581 /* Train 2 */
3582 reg = FDI_TX_CTL(pipe);
3583 temp = I915_READ(reg);
3584 temp &= ~FDI_LINK_TRAIN_NONE;
3585 temp |= FDI_LINK_TRAIN_PATTERN_2;
3586 if (IS_GEN6(dev)) {
3587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3588 /* SNB-B */
3589 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3590 }
3591 I915_WRITE(reg, temp);
3592
3593 reg = FDI_RX_CTL(pipe);
3594 temp = I915_READ(reg);
3595 if (HAS_PCH_CPT(dev)) {
3596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3597 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3598 } else {
3599 temp &= ~FDI_LINK_TRAIN_NONE;
3600 temp |= FDI_LINK_TRAIN_PATTERN_2;
3601 }
3602 I915_WRITE(reg, temp);
3603
3604 POSTING_READ(reg);
3605 udelay(150);
3606
3607 for (i = 0; i < 4; i++) {
3608 reg = FDI_TX_CTL(pipe);
3609 temp = I915_READ(reg);
3610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3611 temp |= snb_b_fdi_train_param[i];
3612 I915_WRITE(reg, temp);
3613
3614 POSTING_READ(reg);
3615 udelay(500);
3616
3617 for (retry = 0; retry < 5; retry++) {
3618 reg = FDI_RX_IIR(pipe);
3619 temp = I915_READ(reg);
3620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3621 if (temp & FDI_RX_SYMBOL_LOCK) {
3622 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3623 DRM_DEBUG_KMS("FDI train 2 done.\n");
3624 break;
3625 }
3626 udelay(50);
3627 }
3628 if (retry < 5)
3629 break;
3630 }
3631 if (i == 4)
3632 DRM_ERROR("FDI train 2 fail!\n");
3633
3634 DRM_DEBUG_KMS("FDI train done.\n");
3635 }
3636
3637 /* Manual link training for Ivy Bridge A0 parts */
3638 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3639 {
3640 struct drm_device *dev = crtc->dev;
3641 struct drm_i915_private *dev_priv = dev->dev_private;
3642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3643 int pipe = intel_crtc->pipe;
3644 i915_reg_t reg;
3645 u32 temp, i, j;
3646
3647 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3648 for train result */
3649 reg = FDI_RX_IMR(pipe);
3650 temp = I915_READ(reg);
3651 temp &= ~FDI_RX_SYMBOL_LOCK;
3652 temp &= ~FDI_RX_BIT_LOCK;
3653 I915_WRITE(reg, temp);
3654
3655 POSTING_READ(reg);
3656 udelay(150);
3657
3658 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3659 I915_READ(FDI_RX_IIR(pipe)));
3660
3661 /* Try each vswing and preemphasis setting twice before moving on */
3662 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3663 /* disable first in case we need to retry */
3664 reg = FDI_TX_CTL(pipe);
3665 temp = I915_READ(reg);
3666 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3667 temp &= ~FDI_TX_ENABLE;
3668 I915_WRITE(reg, temp);
3669
3670 reg = FDI_RX_CTL(pipe);
3671 temp = I915_READ(reg);
3672 temp &= ~FDI_LINK_TRAIN_AUTO;
3673 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3674 temp &= ~FDI_RX_ENABLE;
3675 I915_WRITE(reg, temp);
3676
3677 /* enable CPU FDI TX and PCH FDI RX */
3678 reg = FDI_TX_CTL(pipe);
3679 temp = I915_READ(reg);
3680 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3681 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3682 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3683 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3684 temp |= snb_b_fdi_train_param[j/2];
3685 temp |= FDI_COMPOSITE_SYNC;
3686 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3687
3688 I915_WRITE(FDI_RX_MISC(pipe),
3689 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3690
3691 reg = FDI_RX_CTL(pipe);
3692 temp = I915_READ(reg);
3693 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3694 temp |= FDI_COMPOSITE_SYNC;
3695 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3696
3697 POSTING_READ(reg);
3698 udelay(1); /* should be 0.5us */
3699
3700 for (i = 0; i < 4; i++) {
3701 reg = FDI_RX_IIR(pipe);
3702 temp = I915_READ(reg);
3703 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3704
3705 if (temp & FDI_RX_BIT_LOCK ||
3706 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3707 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3708 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3709 i);
3710 break;
3711 }
3712 udelay(1); /* should be 0.5us */
3713 }
3714 if (i == 4) {
3715 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3716 continue;
3717 }
3718
3719 /* Train 2 */
3720 reg = FDI_TX_CTL(pipe);
3721 temp = I915_READ(reg);
3722 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3723 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3724 I915_WRITE(reg, temp);
3725
3726 reg = FDI_RX_CTL(pipe);
3727 temp = I915_READ(reg);
3728 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3729 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3730 I915_WRITE(reg, temp);
3731
3732 POSTING_READ(reg);
3733 udelay(2); /* should be 1.5us */
3734
3735 for (i = 0; i < 4; i++) {
3736 reg = FDI_RX_IIR(pipe);
3737 temp = I915_READ(reg);
3738 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3739
3740 if (temp & FDI_RX_SYMBOL_LOCK ||
3741 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3742 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3743 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3744 i);
3745 goto train_done;
3746 }
3747 udelay(2); /* should be 1.5us */
3748 }
3749 if (i == 4)
3750 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3751 }
3752
3753 train_done:
3754 DRM_DEBUG_KMS("FDI train done.\n");
3755 }
3756
3757 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3758 {
3759 struct drm_device *dev = intel_crtc->base.dev;
3760 struct drm_i915_private *dev_priv = dev->dev_private;
3761 int pipe = intel_crtc->pipe;
3762 i915_reg_t reg;
3763 u32 temp;
3764
3765 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3766 reg = FDI_RX_CTL(pipe);
3767 temp = I915_READ(reg);
3768 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3769 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3770 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3771 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3772
3773 POSTING_READ(reg);
3774 udelay(200);
3775
3776 /* Switch from Rawclk to PCDclk */
3777 temp = I915_READ(reg);
3778 I915_WRITE(reg, temp | FDI_PCDCLK);
3779
3780 POSTING_READ(reg);
3781 udelay(200);
3782
3783 /* Enable CPU FDI TX PLL, always on for Ironlake */
3784 reg = FDI_TX_CTL(pipe);
3785 temp = I915_READ(reg);
3786 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3787 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3788
3789 POSTING_READ(reg);
3790 udelay(100);
3791 }
3792 }
3793
3794 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3795 {
3796 struct drm_device *dev = intel_crtc->base.dev;
3797 struct drm_i915_private *dev_priv = dev->dev_private;
3798 int pipe = intel_crtc->pipe;
3799 i915_reg_t reg;
3800 u32 temp;
3801
3802 /* Switch from PCDclk to Rawclk */
3803 reg = FDI_RX_CTL(pipe);
3804 temp = I915_READ(reg);
3805 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3806
3807 /* Disable CPU FDI TX PLL */
3808 reg = FDI_TX_CTL(pipe);
3809 temp = I915_READ(reg);
3810 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3811
3812 POSTING_READ(reg);
3813 udelay(100);
3814
3815 reg = FDI_RX_CTL(pipe);
3816 temp = I915_READ(reg);
3817 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3818
3819 /* Wait for the clocks to turn off. */
3820 POSTING_READ(reg);
3821 udelay(100);
3822 }
3823
3824 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3825 {
3826 struct drm_device *dev = crtc->dev;
3827 struct drm_i915_private *dev_priv = dev->dev_private;
3828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3829 int pipe = intel_crtc->pipe;
3830 i915_reg_t reg;
3831 u32 temp;
3832
3833 /* disable CPU FDI tx and PCH FDI rx */
3834 reg = FDI_TX_CTL(pipe);
3835 temp = I915_READ(reg);
3836 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3837 POSTING_READ(reg);
3838
3839 reg = FDI_RX_CTL(pipe);
3840 temp = I915_READ(reg);
3841 temp &= ~(0x7 << 16);
3842 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3843 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3844
3845 POSTING_READ(reg);
3846 udelay(100);
3847
3848 /* Ironlake workaround, disable clock pointer after downing FDI */
3849 if (HAS_PCH_IBX(dev))
3850 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3851
3852 /* still set train pattern 1 */
3853 reg = FDI_TX_CTL(pipe);
3854 temp = I915_READ(reg);
3855 temp &= ~FDI_LINK_TRAIN_NONE;
3856 temp |= FDI_LINK_TRAIN_PATTERN_1;
3857 I915_WRITE(reg, temp);
3858
3859 reg = FDI_RX_CTL(pipe);
3860 temp = I915_READ(reg);
3861 if (HAS_PCH_CPT(dev)) {
3862 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3863 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3864 } else {
3865 temp &= ~FDI_LINK_TRAIN_NONE;
3866 temp |= FDI_LINK_TRAIN_PATTERN_1;
3867 }
3868 /* BPC in FDI rx is consistent with that in PIPECONF */
3869 temp &= ~(0x07 << 16);
3870 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3871 I915_WRITE(reg, temp);
3872
3873 POSTING_READ(reg);
3874 udelay(100);
3875 }
3876
3877 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3878 {
3879 struct intel_crtc *crtc;
3880
3881 /* Note that we don't need to be called with mode_config.lock here
3882 * as our list of CRTC objects is static for the lifetime of the
3883 * device and so cannot disappear as we iterate. Similarly, we can
3884 * happily treat the predicates as racy, atomic checks as userspace
3885 * cannot claim and pin a new fb without at least acquring the
3886 * struct_mutex and so serialising with us.
3887 */
3888 for_each_intel_crtc(dev, crtc) {
3889 if (atomic_read(&crtc->unpin_work_count) == 0)
3890 continue;
3891
3892 if (crtc->unpin_work)
3893 intel_wait_for_vblank(dev, crtc->pipe);
3894
3895 return true;
3896 }
3897
3898 return false;
3899 }
3900
3901 static void page_flip_completed(struct intel_crtc *intel_crtc)
3902 {
3903 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3904 struct intel_unpin_work *work = intel_crtc->unpin_work;
3905
3906 /* ensure that the unpin work is consistent wrt ->pending. */
3907 smp_rmb();
3908 intel_crtc->unpin_work = NULL;
3909
3910 if (work->event)
3911 drm_send_vblank_event(intel_crtc->base.dev,
3912 intel_crtc->pipe,
3913 work->event);
3914
3915 drm_crtc_vblank_put(&intel_crtc->base);
3916
3917 wake_up_all(&dev_priv->pending_flip_queue);
3918 queue_work(dev_priv->wq, &work->work);
3919
3920 trace_i915_flip_complete(intel_crtc->plane,
3921 work->pending_flip_obj);
3922 }
3923
3924 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3925 {
3926 struct drm_device *dev = crtc->dev;
3927 struct drm_i915_private *dev_priv = dev->dev_private;
3928 long ret;
3929
3930 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3931
3932 ret = wait_event_interruptible_timeout(
3933 dev_priv->pending_flip_queue,
3934 !intel_crtc_has_pending_flip(crtc),
3935 60*HZ);
3936
3937 if (ret < 0)
3938 return ret;
3939
3940 if (ret == 0) {
3941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3942
3943 spin_lock_irq(&dev->event_lock);
3944 if (intel_crtc->unpin_work) {
3945 WARN_ONCE(1, "Removing stuck page flip\n");
3946 page_flip_completed(intel_crtc);
3947 }
3948 spin_unlock_irq(&dev->event_lock);
3949 }
3950
3951 return 0;
3952 }
3953
3954 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3955 {
3956 u32 temp;
3957
3958 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3959
3960 mutex_lock(&dev_priv->sb_lock);
3961
3962 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3963 temp |= SBI_SSCCTL_DISABLE;
3964 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3965
3966 mutex_unlock(&dev_priv->sb_lock);
3967 }
3968
3969 /* Program iCLKIP clock to the desired frequency */
3970 static void lpt_program_iclkip(struct drm_crtc *crtc)
3971 {
3972 struct drm_device *dev = crtc->dev;
3973 struct drm_i915_private *dev_priv = dev->dev_private;
3974 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3975 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3976 u32 temp;
3977
3978 lpt_disable_iclkip(dev_priv);
3979
3980 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3981 if (clock == 20000) {
3982 auxdiv = 1;
3983 divsel = 0x41;
3984 phaseinc = 0x20;
3985 } else {
3986 /* The iCLK virtual clock root frequency is in MHz,
3987 * but the adjusted_mode->crtc_clock in in KHz. To get the
3988 * divisors, it is necessary to divide one by another, so we
3989 * convert the virtual clock precision to KHz here for higher
3990 * precision.
3991 */
3992 u32 iclk_virtual_root_freq = 172800 * 1000;
3993 u32 iclk_pi_range = 64;
3994 u32 desired_divisor, msb_divisor_value, pi_value;
3995
3996 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock);
3997 msb_divisor_value = desired_divisor / iclk_pi_range;
3998 pi_value = desired_divisor % iclk_pi_range;
3999
4000 auxdiv = 0;
4001 divsel = msb_divisor_value - 2;
4002 phaseinc = pi_value;
4003 }
4004
4005 /* This should not happen with any sane values */
4006 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4007 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4008 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4009 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4010
4011 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4012 clock,
4013 auxdiv,
4014 divsel,
4015 phasedir,
4016 phaseinc);
4017
4018 mutex_lock(&dev_priv->sb_lock);
4019
4020 /* Program SSCDIVINTPHASE6 */
4021 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4022 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4023 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4024 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4025 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4026 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4027 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4028 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4029
4030 /* Program SSCAUXDIV */
4031 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4032 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4033 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4034 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4035
4036 /* Enable modulator and associated divider */
4037 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4038 temp &= ~SBI_SSCCTL_DISABLE;
4039 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4040
4041 mutex_unlock(&dev_priv->sb_lock);
4042
4043 /* Wait for initialization time */
4044 udelay(24);
4045
4046 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4047 }
4048
4049 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4050 enum pipe pch_transcoder)
4051 {
4052 struct drm_device *dev = crtc->base.dev;
4053 struct drm_i915_private *dev_priv = dev->dev_private;
4054 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4055
4056 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4057 I915_READ(HTOTAL(cpu_transcoder)));
4058 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4059 I915_READ(HBLANK(cpu_transcoder)));
4060 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4061 I915_READ(HSYNC(cpu_transcoder)));
4062
4063 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4064 I915_READ(VTOTAL(cpu_transcoder)));
4065 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4066 I915_READ(VBLANK(cpu_transcoder)));
4067 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4068 I915_READ(VSYNC(cpu_transcoder)));
4069 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4070 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4071 }
4072
4073 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4074 {
4075 struct drm_i915_private *dev_priv = dev->dev_private;
4076 uint32_t temp;
4077
4078 temp = I915_READ(SOUTH_CHICKEN1);
4079 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4080 return;
4081
4082 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4083 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4084
4085 temp &= ~FDI_BC_BIFURCATION_SELECT;
4086 if (enable)
4087 temp |= FDI_BC_BIFURCATION_SELECT;
4088
4089 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4090 I915_WRITE(SOUTH_CHICKEN1, temp);
4091 POSTING_READ(SOUTH_CHICKEN1);
4092 }
4093
4094 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4095 {
4096 struct drm_device *dev = intel_crtc->base.dev;
4097
4098 switch (intel_crtc->pipe) {
4099 case PIPE_A:
4100 break;
4101 case PIPE_B:
4102 if (intel_crtc->config->fdi_lanes > 2)
4103 cpt_set_fdi_bc_bifurcation(dev, false);
4104 else
4105 cpt_set_fdi_bc_bifurcation(dev, true);
4106
4107 break;
4108 case PIPE_C:
4109 cpt_set_fdi_bc_bifurcation(dev, true);
4110
4111 break;
4112 default:
4113 BUG();
4114 }
4115 }
4116
4117 /* Return which DP Port should be selected for Transcoder DP control */
4118 static enum port
4119 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4120 {
4121 struct drm_device *dev = crtc->dev;
4122 struct intel_encoder *encoder;
4123
4124 for_each_encoder_on_crtc(dev, crtc, encoder) {
4125 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4126 encoder->type == INTEL_OUTPUT_EDP)
4127 return enc_to_dig_port(&encoder->base)->port;
4128 }
4129
4130 return -1;
4131 }
4132
4133 /*
4134 * Enable PCH resources required for PCH ports:
4135 * - PCH PLLs
4136 * - FDI training & RX/TX
4137 * - update transcoder timings
4138 * - DP transcoding bits
4139 * - transcoder
4140 */
4141 static void ironlake_pch_enable(struct drm_crtc *crtc)
4142 {
4143 struct drm_device *dev = crtc->dev;
4144 struct drm_i915_private *dev_priv = dev->dev_private;
4145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4146 int pipe = intel_crtc->pipe;
4147 u32 temp;
4148
4149 assert_pch_transcoder_disabled(dev_priv, pipe);
4150
4151 if (IS_IVYBRIDGE(dev))
4152 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4153
4154 /* Write the TU size bits before fdi link training, so that error
4155 * detection works. */
4156 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4157 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4158
4159 /*
4160 * Sometimes spurious CPU pipe underruns happen during FDI
4161 * training, at least with VGA+HDMI cloning. Suppress them.
4162 */
4163 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4164
4165 /* For PCH output, training FDI link */
4166 dev_priv->display.fdi_link_train(crtc);
4167
4168 /* We need to program the right clock selection before writing the pixel
4169 * mutliplier into the DPLL. */
4170 if (HAS_PCH_CPT(dev)) {
4171 u32 sel;
4172
4173 temp = I915_READ(PCH_DPLL_SEL);
4174 temp |= TRANS_DPLL_ENABLE(pipe);
4175 sel = TRANS_DPLLB_SEL(pipe);
4176 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4177 temp |= sel;
4178 else
4179 temp &= ~sel;
4180 I915_WRITE(PCH_DPLL_SEL, temp);
4181 }
4182
4183 /* XXX: pch pll's can be enabled any time before we enable the PCH
4184 * transcoder, and we actually should do this to not upset any PCH
4185 * transcoder that already use the clock when we share it.
4186 *
4187 * Note that enable_shared_dpll tries to do the right thing, but
4188 * get_shared_dpll unconditionally resets the pll - we need that to have
4189 * the right LVDS enable sequence. */
4190 intel_enable_shared_dpll(intel_crtc);
4191
4192 /* set transcoder timing, panel must allow it */
4193 assert_panel_unlocked(dev_priv, pipe);
4194 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4195
4196 intel_fdi_normal_train(crtc);
4197
4198 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4199
4200 /* For PCH DP, enable TRANS_DP_CTL */
4201 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4202 const struct drm_display_mode *adjusted_mode =
4203 &intel_crtc->config->base.adjusted_mode;
4204 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4205 i915_reg_t reg = TRANS_DP_CTL(pipe);
4206 temp = I915_READ(reg);
4207 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4208 TRANS_DP_SYNC_MASK |
4209 TRANS_DP_BPC_MASK);
4210 temp |= TRANS_DP_OUTPUT_ENABLE;
4211 temp |= bpc << 9; /* same format but at 11:9 */
4212
4213 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4214 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4215 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4216 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4217
4218 switch (intel_trans_dp_port_sel(crtc)) {
4219 case PORT_B:
4220 temp |= TRANS_DP_PORT_SEL_B;
4221 break;
4222 case PORT_C:
4223 temp |= TRANS_DP_PORT_SEL_C;
4224 break;
4225 case PORT_D:
4226 temp |= TRANS_DP_PORT_SEL_D;
4227 break;
4228 default:
4229 BUG();
4230 }
4231
4232 I915_WRITE(reg, temp);
4233 }
4234
4235 ironlake_enable_pch_transcoder(dev_priv, pipe);
4236 }
4237
4238 static void lpt_pch_enable(struct drm_crtc *crtc)
4239 {
4240 struct drm_device *dev = crtc->dev;
4241 struct drm_i915_private *dev_priv = dev->dev_private;
4242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4243 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4244
4245 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4246
4247 lpt_program_iclkip(crtc);
4248
4249 /* Set transcoder timing. */
4250 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4251
4252 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4253 }
4254
4255 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4256 struct intel_crtc_state *crtc_state)
4257 {
4258 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4259 struct intel_shared_dpll *pll;
4260 struct intel_shared_dpll_config *shared_dpll;
4261 enum intel_dpll_id i;
4262 int max = dev_priv->num_shared_dpll;
4263
4264 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4265
4266 if (HAS_PCH_IBX(dev_priv->dev)) {
4267 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4268 i = (enum intel_dpll_id) crtc->pipe;
4269 pll = &dev_priv->shared_dplls[i];
4270
4271 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4272 crtc->base.base.id, pll->name);
4273
4274 WARN_ON(shared_dpll[i].crtc_mask);
4275
4276 goto found;
4277 }
4278
4279 if (IS_BROXTON(dev_priv->dev)) {
4280 /* PLL is attached to port in bxt */
4281 struct intel_encoder *encoder;
4282 struct intel_digital_port *intel_dig_port;
4283
4284 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4285 if (WARN_ON(!encoder))
4286 return NULL;
4287
4288 intel_dig_port = enc_to_dig_port(&encoder->base);
4289 /* 1:1 mapping between ports and PLLs */
4290 i = (enum intel_dpll_id)intel_dig_port->port;
4291 pll = &dev_priv->shared_dplls[i];
4292 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4293 crtc->base.base.id, pll->name);
4294 WARN_ON(shared_dpll[i].crtc_mask);
4295
4296 goto found;
4297 } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
4298 /* Do not consider SPLL */
4299 max = 2;
4300
4301 for (i = 0; i < max; i++) {
4302 pll = &dev_priv->shared_dplls[i];
4303
4304 /* Only want to check enabled timings first */
4305 if (shared_dpll[i].crtc_mask == 0)
4306 continue;
4307
4308 if (memcmp(&crtc_state->dpll_hw_state,
4309 &shared_dpll[i].hw_state,
4310 sizeof(crtc_state->dpll_hw_state)) == 0) {
4311 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4312 crtc->base.base.id, pll->name,
4313 shared_dpll[i].crtc_mask,
4314 pll->active);
4315 goto found;
4316 }
4317 }
4318
4319 /* Ok no matching timings, maybe there's a free one? */
4320 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4321 pll = &dev_priv->shared_dplls[i];
4322 if (shared_dpll[i].crtc_mask == 0) {
4323 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4324 crtc->base.base.id, pll->name);
4325 goto found;
4326 }
4327 }
4328
4329 return NULL;
4330
4331 found:
4332 if (shared_dpll[i].crtc_mask == 0)
4333 shared_dpll[i].hw_state =
4334 crtc_state->dpll_hw_state;
4335
4336 crtc_state->shared_dpll = i;
4337 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4338 pipe_name(crtc->pipe));
4339
4340 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4341
4342 return pll;
4343 }
4344
4345 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4346 {
4347 struct drm_i915_private *dev_priv = to_i915(state->dev);
4348 struct intel_shared_dpll_config *shared_dpll;
4349 struct intel_shared_dpll *pll;
4350 enum intel_dpll_id i;
4351
4352 if (!to_intel_atomic_state(state)->dpll_set)
4353 return;
4354
4355 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4356 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4357 pll = &dev_priv->shared_dplls[i];
4358 pll->config = shared_dpll[i];
4359 }
4360 }
4361
4362 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4363 {
4364 struct drm_i915_private *dev_priv = dev->dev_private;
4365 i915_reg_t dslreg = PIPEDSL(pipe);
4366 u32 temp;
4367
4368 temp = I915_READ(dslreg);
4369 udelay(500);
4370 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4371 if (wait_for(I915_READ(dslreg) != temp, 5))
4372 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4373 }
4374 }
4375
4376 static int
4377 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4378 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4379 int src_w, int src_h, int dst_w, int dst_h)
4380 {
4381 struct intel_crtc_scaler_state *scaler_state =
4382 &crtc_state->scaler_state;
4383 struct intel_crtc *intel_crtc =
4384 to_intel_crtc(crtc_state->base.crtc);
4385 int need_scaling;
4386
4387 need_scaling = intel_rotation_90_or_270(rotation) ?
4388 (src_h != dst_w || src_w != dst_h):
4389 (src_w != dst_w || src_h != dst_h);
4390
4391 /*
4392 * if plane is being disabled or scaler is no more required or force detach
4393 * - free scaler binded to this plane/crtc
4394 * - in order to do this, update crtc->scaler_usage
4395 *
4396 * Here scaler state in crtc_state is set free so that
4397 * scaler can be assigned to other user. Actual register
4398 * update to free the scaler is done in plane/panel-fit programming.
4399 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4400 */
4401 if (force_detach || !need_scaling) {
4402 if (*scaler_id >= 0) {
4403 scaler_state->scaler_users &= ~(1 << scaler_user);
4404 scaler_state->scalers[*scaler_id].in_use = 0;
4405
4406 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4407 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4408 intel_crtc->pipe, scaler_user, *scaler_id,
4409 scaler_state->scaler_users);
4410 *scaler_id = -1;
4411 }
4412 return 0;
4413 }
4414
4415 /* range checks */
4416 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4417 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4418
4419 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4420 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4421 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4422 "size is out of scaler range\n",
4423 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4424 return -EINVAL;
4425 }
4426
4427 /* mark this plane as a scaler user in crtc_state */
4428 scaler_state->scaler_users |= (1 << scaler_user);
4429 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4430 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4431 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4432 scaler_state->scaler_users);
4433
4434 return 0;
4435 }
4436
4437 /**
4438 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4439 *
4440 * @state: crtc's scaler state
4441 *
4442 * Return
4443 * 0 - scaler_usage updated successfully
4444 * error - requested scaling cannot be supported or other error condition
4445 */
4446 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4447 {
4448 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4449 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4450
4451 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4452 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4453
4454 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4455 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4456 state->pipe_src_w, state->pipe_src_h,
4457 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4458 }
4459
4460 /**
4461 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4462 *
4463 * @state: crtc's scaler state
4464 * @plane_state: atomic plane state to update
4465 *
4466 * Return
4467 * 0 - scaler_usage updated successfully
4468 * error - requested scaling cannot be supported or other error condition
4469 */
4470 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4471 struct intel_plane_state *plane_state)
4472 {
4473
4474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4475 struct intel_plane *intel_plane =
4476 to_intel_plane(plane_state->base.plane);
4477 struct drm_framebuffer *fb = plane_state->base.fb;
4478 int ret;
4479
4480 bool force_detach = !fb || !plane_state->visible;
4481
4482 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4483 intel_plane->base.base.id, intel_crtc->pipe,
4484 drm_plane_index(&intel_plane->base));
4485
4486 ret = skl_update_scaler(crtc_state, force_detach,
4487 drm_plane_index(&intel_plane->base),
4488 &plane_state->scaler_id,
4489 plane_state->base.rotation,
4490 drm_rect_width(&plane_state->src) >> 16,
4491 drm_rect_height(&plane_state->src) >> 16,
4492 drm_rect_width(&plane_state->dst),
4493 drm_rect_height(&plane_state->dst));
4494
4495 if (ret || plane_state->scaler_id < 0)
4496 return ret;
4497
4498 /* check colorkey */
4499 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4500 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4501 intel_plane->base.base.id);
4502 return -EINVAL;
4503 }
4504
4505 /* Check src format */
4506 switch (fb->pixel_format) {
4507 case DRM_FORMAT_RGB565:
4508 case DRM_FORMAT_XBGR8888:
4509 case DRM_FORMAT_XRGB8888:
4510 case DRM_FORMAT_ABGR8888:
4511 case DRM_FORMAT_ARGB8888:
4512 case DRM_FORMAT_XRGB2101010:
4513 case DRM_FORMAT_XBGR2101010:
4514 case DRM_FORMAT_YUYV:
4515 case DRM_FORMAT_YVYU:
4516 case DRM_FORMAT_UYVY:
4517 case DRM_FORMAT_VYUY:
4518 break;
4519 default:
4520 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4521 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4522 return -EINVAL;
4523 }
4524
4525 return 0;
4526 }
4527
4528 static void skylake_scaler_disable(struct intel_crtc *crtc)
4529 {
4530 int i;
4531
4532 for (i = 0; i < crtc->num_scalers; i++)
4533 skl_detach_scaler(crtc, i);
4534 }
4535
4536 static void skylake_pfit_enable(struct intel_crtc *crtc)
4537 {
4538 struct drm_device *dev = crtc->base.dev;
4539 struct drm_i915_private *dev_priv = dev->dev_private;
4540 int pipe = crtc->pipe;
4541 struct intel_crtc_scaler_state *scaler_state =
4542 &crtc->config->scaler_state;
4543
4544 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4545
4546 if (crtc->config->pch_pfit.enabled) {
4547 int id;
4548
4549 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4550 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4551 return;
4552 }
4553
4554 id = scaler_state->scaler_id;
4555 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4556 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4557 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4558 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4559
4560 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4561 }
4562 }
4563
4564 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4565 {
4566 struct drm_device *dev = crtc->base.dev;
4567 struct drm_i915_private *dev_priv = dev->dev_private;
4568 int pipe = crtc->pipe;
4569
4570 if (crtc->config->pch_pfit.enabled) {
4571 /* Force use of hard-coded filter coefficients
4572 * as some pre-programmed values are broken,
4573 * e.g. x201.
4574 */
4575 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4576 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4577 PF_PIPE_SEL_IVB(pipe));
4578 else
4579 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4580 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4581 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4582 }
4583 }
4584
4585 void hsw_enable_ips(struct intel_crtc *crtc)
4586 {
4587 struct drm_device *dev = crtc->base.dev;
4588 struct drm_i915_private *dev_priv = dev->dev_private;
4589
4590 if (!crtc->config->ips_enabled)
4591 return;
4592
4593 /* We can only enable IPS after we enable a plane and wait for a vblank */
4594 intel_wait_for_vblank(dev, crtc->pipe);
4595
4596 assert_plane_enabled(dev_priv, crtc->plane);
4597 if (IS_BROADWELL(dev)) {
4598 mutex_lock(&dev_priv->rps.hw_lock);
4599 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4600 mutex_unlock(&dev_priv->rps.hw_lock);
4601 /* Quoting Art Runyan: "its not safe to expect any particular
4602 * value in IPS_CTL bit 31 after enabling IPS through the
4603 * mailbox." Moreover, the mailbox may return a bogus state,
4604 * so we need to just enable it and continue on.
4605 */
4606 } else {
4607 I915_WRITE(IPS_CTL, IPS_ENABLE);
4608 /* The bit only becomes 1 in the next vblank, so this wait here
4609 * is essentially intel_wait_for_vblank. If we don't have this
4610 * and don't wait for vblanks until the end of crtc_enable, then
4611 * the HW state readout code will complain that the expected
4612 * IPS_CTL value is not the one we read. */
4613 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4614 DRM_ERROR("Timed out waiting for IPS enable\n");
4615 }
4616 }
4617
4618 void hsw_disable_ips(struct intel_crtc *crtc)
4619 {
4620 struct drm_device *dev = crtc->base.dev;
4621 struct drm_i915_private *dev_priv = dev->dev_private;
4622
4623 if (!crtc->config->ips_enabled)
4624 return;
4625
4626 assert_plane_enabled(dev_priv, crtc->plane);
4627 if (IS_BROADWELL(dev)) {
4628 mutex_lock(&dev_priv->rps.hw_lock);
4629 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4630 mutex_unlock(&dev_priv->rps.hw_lock);
4631 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4632 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4633 DRM_ERROR("Timed out waiting for IPS disable\n");
4634 } else {
4635 I915_WRITE(IPS_CTL, 0);
4636 POSTING_READ(IPS_CTL);
4637 }
4638
4639 /* We need to wait for a vblank before we can disable the plane. */
4640 intel_wait_for_vblank(dev, crtc->pipe);
4641 }
4642
4643 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4644 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4645 {
4646 struct drm_device *dev = crtc->dev;
4647 struct drm_i915_private *dev_priv = dev->dev_private;
4648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4649 enum pipe pipe = intel_crtc->pipe;
4650 int i;
4651 bool reenable_ips = false;
4652
4653 /* The clocks have to be on to load the palette. */
4654 if (!crtc->state->active)
4655 return;
4656
4657 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4658 if (intel_crtc->config->has_dsi_encoder)
4659 assert_dsi_pll_enabled(dev_priv);
4660 else
4661 assert_pll_enabled(dev_priv, pipe);
4662 }
4663
4664 /* Workaround : Do not read or write the pipe palette/gamma data while
4665 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4666 */
4667 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4668 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4669 GAMMA_MODE_MODE_SPLIT)) {
4670 hsw_disable_ips(intel_crtc);
4671 reenable_ips = true;
4672 }
4673
4674 for (i = 0; i < 256; i++) {
4675 i915_reg_t palreg;
4676
4677 if (HAS_GMCH_DISPLAY(dev))
4678 palreg = PALETTE(pipe, i);
4679 else
4680 palreg = LGC_PALETTE(pipe, i);
4681
4682 I915_WRITE(palreg,
4683 (intel_crtc->lut_r[i] << 16) |
4684 (intel_crtc->lut_g[i] << 8) |
4685 intel_crtc->lut_b[i]);
4686 }
4687
4688 if (reenable_ips)
4689 hsw_enable_ips(intel_crtc);
4690 }
4691
4692 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4693 {
4694 if (intel_crtc->overlay) {
4695 struct drm_device *dev = intel_crtc->base.dev;
4696 struct drm_i915_private *dev_priv = dev->dev_private;
4697
4698 mutex_lock(&dev->struct_mutex);
4699 dev_priv->mm.interruptible = false;
4700 (void) intel_overlay_switch_off(intel_crtc->overlay);
4701 dev_priv->mm.interruptible = true;
4702 mutex_unlock(&dev->struct_mutex);
4703 }
4704
4705 /* Let userspace switch the overlay on again. In most cases userspace
4706 * has to recompute where to put it anyway.
4707 */
4708 }
4709
4710 /**
4711 * intel_post_enable_primary - Perform operations after enabling primary plane
4712 * @crtc: the CRTC whose primary plane was just enabled
4713 *
4714 * Performs potentially sleeping operations that must be done after the primary
4715 * plane is enabled, such as updating FBC and IPS. Note that this may be
4716 * called due to an explicit primary plane update, or due to an implicit
4717 * re-enable that is caused when a sprite plane is updated to no longer
4718 * completely hide the primary plane.
4719 */
4720 static void
4721 intel_post_enable_primary(struct drm_crtc *crtc)
4722 {
4723 struct drm_device *dev = crtc->dev;
4724 struct drm_i915_private *dev_priv = dev->dev_private;
4725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4726 int pipe = intel_crtc->pipe;
4727
4728 /*
4729 * FIXME IPS should be fine as long as one plane is
4730 * enabled, but in practice it seems to have problems
4731 * when going from primary only to sprite only and vice
4732 * versa.
4733 */
4734 hsw_enable_ips(intel_crtc);
4735
4736 /*
4737 * Gen2 reports pipe underruns whenever all planes are disabled.
4738 * So don't enable underrun reporting before at least some planes
4739 * are enabled.
4740 * FIXME: Need to fix the logic to work when we turn off all planes
4741 * but leave the pipe running.
4742 */
4743 if (IS_GEN2(dev))
4744 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4745
4746 /* Underruns don't always raise interrupts, so check manually. */
4747 intel_check_cpu_fifo_underruns(dev_priv);
4748 intel_check_pch_fifo_underruns(dev_priv);
4749 }
4750
4751 /**
4752 * intel_pre_disable_primary - Perform operations before disabling primary plane
4753 * @crtc: the CRTC whose primary plane is to be disabled
4754 *
4755 * Performs potentially sleeping operations that must be done before the
4756 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4757 * be called due to an explicit primary plane update, or due to an implicit
4758 * disable that is caused when a sprite plane completely hides the primary
4759 * plane.
4760 */
4761 static void
4762 intel_pre_disable_primary(struct drm_crtc *crtc)
4763 {
4764 struct drm_device *dev = crtc->dev;
4765 struct drm_i915_private *dev_priv = dev->dev_private;
4766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4767 int pipe = intel_crtc->pipe;
4768
4769 /*
4770 * Gen2 reports pipe underruns whenever all planes are disabled.
4771 * So diasble underrun reporting before all the planes get disabled.
4772 * FIXME: Need to fix the logic to work when we turn off all planes
4773 * but leave the pipe running.
4774 */
4775 if (IS_GEN2(dev))
4776 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4777
4778 /*
4779 * Vblank time updates from the shadow to live plane control register
4780 * are blocked if the memory self-refresh mode is active at that
4781 * moment. So to make sure the plane gets truly disabled, disable
4782 * first the self-refresh mode. The self-refresh enable bit in turn
4783 * will be checked/applied by the HW only at the next frame start
4784 * event which is after the vblank start event, so we need to have a
4785 * wait-for-vblank between disabling the plane and the pipe.
4786 */
4787 if (HAS_GMCH_DISPLAY(dev)) {
4788 intel_set_memory_cxsr(dev_priv, false);
4789 dev_priv->wm.vlv.cxsr = false;
4790 intel_wait_for_vblank(dev, pipe);
4791 }
4792
4793 /*
4794 * FIXME IPS should be fine as long as one plane is
4795 * enabled, but in practice it seems to have problems
4796 * when going from primary only to sprite only and vice
4797 * versa.
4798 */
4799 hsw_disable_ips(intel_crtc);
4800 }
4801
4802 static void intel_post_plane_update(struct intel_crtc *crtc)
4803 {
4804 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4805 struct intel_crtc_state *pipe_config =
4806 to_intel_crtc_state(crtc->base.state);
4807 struct drm_device *dev = crtc->base.dev;
4808
4809 if (atomic->wait_vblank)
4810 intel_wait_for_vblank(dev, crtc->pipe);
4811
4812 intel_frontbuffer_flip(dev, atomic->fb_bits);
4813
4814 crtc->wm.cxsr_allowed = true;
4815
4816 if (pipe_config->wm_changed && pipe_config->base.active)
4817 intel_update_watermarks(&crtc->base);
4818
4819 if (atomic->update_fbc)
4820 intel_fbc_update(crtc);
4821
4822 if (atomic->post_enable_primary)
4823 intel_post_enable_primary(&crtc->base);
4824
4825 memset(atomic, 0, sizeof(*atomic));
4826 }
4827
4828 static void intel_pre_plane_update(struct intel_crtc *crtc)
4829 {
4830 struct drm_device *dev = crtc->base.dev;
4831 struct drm_i915_private *dev_priv = dev->dev_private;
4832 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4833 struct intel_crtc_state *pipe_config =
4834 to_intel_crtc_state(crtc->base.state);
4835
4836 if (atomic->disable_fbc)
4837 intel_fbc_deactivate(crtc);
4838
4839 if (crtc->atomic.disable_ips)
4840 hsw_disable_ips(crtc);
4841
4842 if (atomic->pre_disable_primary)
4843 intel_pre_disable_primary(&crtc->base);
4844
4845 if (pipe_config->disable_cxsr) {
4846 crtc->wm.cxsr_allowed = false;
4847 intel_set_memory_cxsr(dev_priv, false);
4848 }
4849
4850 if (!needs_modeset(&pipe_config->base) && pipe_config->wm_changed)
4851 intel_update_watermarks(&crtc->base);
4852 }
4853
4854 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4855 {
4856 struct drm_device *dev = crtc->dev;
4857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4858 struct drm_plane *p;
4859 int pipe = intel_crtc->pipe;
4860
4861 intel_crtc_dpms_overlay_disable(intel_crtc);
4862
4863 drm_for_each_plane_mask(p, dev, plane_mask)
4864 to_intel_plane(p)->disable_plane(p, crtc);
4865
4866 /*
4867 * FIXME: Once we grow proper nuclear flip support out of this we need
4868 * to compute the mask of flip planes precisely. For the time being
4869 * consider this a flip to a NULL plane.
4870 */
4871 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4872 }
4873
4874 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4875 {
4876 struct drm_device *dev = crtc->dev;
4877 struct drm_i915_private *dev_priv = dev->dev_private;
4878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4879 struct intel_encoder *encoder;
4880 int pipe = intel_crtc->pipe;
4881
4882 if (WARN_ON(intel_crtc->active))
4883 return;
4884
4885 if (intel_crtc->config->has_pch_encoder)
4886 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4887
4888 if (intel_crtc->config->has_pch_encoder)
4889 intel_prepare_shared_dpll(intel_crtc);
4890
4891 if (intel_crtc->config->has_dp_encoder)
4892 intel_dp_set_m_n(intel_crtc, M1_N1);
4893
4894 intel_set_pipe_timings(intel_crtc);
4895
4896 if (intel_crtc->config->has_pch_encoder) {
4897 intel_cpu_transcoder_set_m_n(intel_crtc,
4898 &intel_crtc->config->fdi_m_n, NULL);
4899 }
4900
4901 ironlake_set_pipeconf(crtc);
4902
4903 intel_crtc->active = true;
4904
4905 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4906
4907 for_each_encoder_on_crtc(dev, crtc, encoder)
4908 if (encoder->pre_enable)
4909 encoder->pre_enable(encoder);
4910
4911 if (intel_crtc->config->has_pch_encoder) {
4912 /* Note: FDI PLL enabling _must_ be done before we enable the
4913 * cpu pipes, hence this is separate from all the other fdi/pch
4914 * enabling. */
4915 ironlake_fdi_pll_enable(intel_crtc);
4916 } else {
4917 assert_fdi_tx_disabled(dev_priv, pipe);
4918 assert_fdi_rx_disabled(dev_priv, pipe);
4919 }
4920
4921 ironlake_pfit_enable(intel_crtc);
4922
4923 /*
4924 * On ILK+ LUT must be loaded before the pipe is running but with
4925 * clocks enabled
4926 */
4927 intel_crtc_load_lut(crtc);
4928
4929 intel_update_watermarks(crtc);
4930 intel_enable_pipe(intel_crtc);
4931
4932 if (intel_crtc->config->has_pch_encoder)
4933 ironlake_pch_enable(crtc);
4934
4935 assert_vblank_disabled(crtc);
4936 drm_crtc_vblank_on(crtc);
4937
4938 for_each_encoder_on_crtc(dev, crtc, encoder)
4939 encoder->enable(encoder);
4940
4941 if (HAS_PCH_CPT(dev))
4942 cpt_verify_modeset(dev, intel_crtc->pipe);
4943
4944 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4945 if (intel_crtc->config->has_pch_encoder)
4946 intel_wait_for_vblank(dev, pipe);
4947 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4948
4949 intel_fbc_enable(intel_crtc);
4950 }
4951
4952 /* IPS only exists on ULT machines and is tied to pipe A. */
4953 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4954 {
4955 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4956 }
4957
4958 static void haswell_crtc_enable(struct drm_crtc *crtc)
4959 {
4960 struct drm_device *dev = crtc->dev;
4961 struct drm_i915_private *dev_priv = dev->dev_private;
4962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4963 struct intel_encoder *encoder;
4964 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4965 struct intel_crtc_state *pipe_config =
4966 to_intel_crtc_state(crtc->state);
4967
4968 if (WARN_ON(intel_crtc->active))
4969 return;
4970
4971 if (intel_crtc->config->has_pch_encoder)
4972 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4973 false);
4974
4975 if (intel_crtc_to_shared_dpll(intel_crtc))
4976 intel_enable_shared_dpll(intel_crtc);
4977
4978 if (intel_crtc->config->has_dp_encoder)
4979 intel_dp_set_m_n(intel_crtc, M1_N1);
4980
4981 intel_set_pipe_timings(intel_crtc);
4982
4983 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4984 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4985 intel_crtc->config->pixel_multiplier - 1);
4986 }
4987
4988 if (intel_crtc->config->has_pch_encoder) {
4989 intel_cpu_transcoder_set_m_n(intel_crtc,
4990 &intel_crtc->config->fdi_m_n, NULL);
4991 }
4992
4993 haswell_set_pipeconf(crtc);
4994
4995 intel_set_pipe_csc(crtc);
4996
4997 intel_crtc->active = true;
4998
4999 if (intel_crtc->config->has_pch_encoder)
5000 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5001 else
5002 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5003
5004 for_each_encoder_on_crtc(dev, crtc, encoder) {
5005 if (encoder->pre_enable)
5006 encoder->pre_enable(encoder);
5007 }
5008
5009 if (intel_crtc->config->has_pch_encoder)
5010 dev_priv->display.fdi_link_train(crtc);
5011
5012 if (!intel_crtc->config->has_dsi_encoder)
5013 intel_ddi_enable_pipe_clock(intel_crtc);
5014
5015 if (INTEL_INFO(dev)->gen >= 9)
5016 skylake_pfit_enable(intel_crtc);
5017 else
5018 ironlake_pfit_enable(intel_crtc);
5019
5020 /*
5021 * On ILK+ LUT must be loaded before the pipe is running but with
5022 * clocks enabled
5023 */
5024 intel_crtc_load_lut(crtc);
5025
5026 intel_ddi_set_pipe_settings(crtc);
5027 if (!intel_crtc->config->has_dsi_encoder)
5028 intel_ddi_enable_transcoder_func(crtc);
5029
5030 intel_update_watermarks(crtc);
5031 intel_enable_pipe(intel_crtc);
5032
5033 if (intel_crtc->config->has_pch_encoder)
5034 lpt_pch_enable(crtc);
5035
5036 if (intel_crtc->config->dp_encoder_is_mst)
5037 intel_ddi_set_vc_payload_alloc(crtc, true);
5038
5039 assert_vblank_disabled(crtc);
5040 drm_crtc_vblank_on(crtc);
5041
5042 for_each_encoder_on_crtc(dev, crtc, encoder) {
5043 encoder->enable(encoder);
5044 intel_opregion_notify_encoder(encoder, true);
5045 }
5046
5047 if (intel_crtc->config->has_pch_encoder) {
5048 intel_wait_for_vblank(dev, pipe);
5049 intel_wait_for_vblank(dev, pipe);
5050 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5051 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5052 true);
5053 }
5054
5055 /* If we change the relative order between pipe/planes enabling, we need
5056 * to change the workaround. */
5057 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5058 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5059 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5060 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5061 }
5062
5063 intel_fbc_enable(intel_crtc);
5064 }
5065
5066 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5067 {
5068 struct drm_device *dev = crtc->base.dev;
5069 struct drm_i915_private *dev_priv = dev->dev_private;
5070 int pipe = crtc->pipe;
5071
5072 /* To avoid upsetting the power well on haswell only disable the pfit if
5073 * it's in use. The hw state code will make sure we get this right. */
5074 if (force || crtc->config->pch_pfit.enabled) {
5075 I915_WRITE(PF_CTL(pipe), 0);
5076 I915_WRITE(PF_WIN_POS(pipe), 0);
5077 I915_WRITE(PF_WIN_SZ(pipe), 0);
5078 }
5079 }
5080
5081 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5082 {
5083 struct drm_device *dev = crtc->dev;
5084 struct drm_i915_private *dev_priv = dev->dev_private;
5085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5086 struct intel_encoder *encoder;
5087 int pipe = intel_crtc->pipe;
5088
5089 if (intel_crtc->config->has_pch_encoder)
5090 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5091
5092 for_each_encoder_on_crtc(dev, crtc, encoder)
5093 encoder->disable(encoder);
5094
5095 drm_crtc_vblank_off(crtc);
5096 assert_vblank_disabled(crtc);
5097
5098 /*
5099 * Sometimes spurious CPU pipe underruns happen when the
5100 * pipe is already disabled, but FDI RX/TX is still enabled.
5101 * Happens at least with VGA+HDMI cloning. Suppress them.
5102 */
5103 if (intel_crtc->config->has_pch_encoder)
5104 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5105
5106 intel_disable_pipe(intel_crtc);
5107
5108 ironlake_pfit_disable(intel_crtc, false);
5109
5110 if (intel_crtc->config->has_pch_encoder) {
5111 ironlake_fdi_disable(crtc);
5112 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5113 }
5114
5115 for_each_encoder_on_crtc(dev, crtc, encoder)
5116 if (encoder->post_disable)
5117 encoder->post_disable(encoder);
5118
5119 if (intel_crtc->config->has_pch_encoder) {
5120 ironlake_disable_pch_transcoder(dev_priv, pipe);
5121
5122 if (HAS_PCH_CPT(dev)) {
5123 i915_reg_t reg;
5124 u32 temp;
5125
5126 /* disable TRANS_DP_CTL */
5127 reg = TRANS_DP_CTL(pipe);
5128 temp = I915_READ(reg);
5129 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5130 TRANS_DP_PORT_SEL_MASK);
5131 temp |= TRANS_DP_PORT_SEL_NONE;
5132 I915_WRITE(reg, temp);
5133
5134 /* disable DPLL_SEL */
5135 temp = I915_READ(PCH_DPLL_SEL);
5136 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5137 I915_WRITE(PCH_DPLL_SEL, temp);
5138 }
5139
5140 ironlake_fdi_pll_disable(intel_crtc);
5141 }
5142
5143 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5144
5145 intel_fbc_disable_crtc(intel_crtc);
5146 }
5147
5148 static void haswell_crtc_disable(struct drm_crtc *crtc)
5149 {
5150 struct drm_device *dev = crtc->dev;
5151 struct drm_i915_private *dev_priv = dev->dev_private;
5152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5153 struct intel_encoder *encoder;
5154 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5155
5156 if (intel_crtc->config->has_pch_encoder)
5157 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5158 false);
5159
5160 for_each_encoder_on_crtc(dev, crtc, encoder) {
5161 intel_opregion_notify_encoder(encoder, false);
5162 encoder->disable(encoder);
5163 }
5164
5165 drm_crtc_vblank_off(crtc);
5166 assert_vblank_disabled(crtc);
5167
5168 intel_disable_pipe(intel_crtc);
5169
5170 if (intel_crtc->config->dp_encoder_is_mst)
5171 intel_ddi_set_vc_payload_alloc(crtc, false);
5172
5173 if (!intel_crtc->config->has_dsi_encoder)
5174 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5175
5176 if (INTEL_INFO(dev)->gen >= 9)
5177 skylake_scaler_disable(intel_crtc);
5178 else
5179 ironlake_pfit_disable(intel_crtc, false);
5180
5181 if (!intel_crtc->config->has_dsi_encoder)
5182 intel_ddi_disable_pipe_clock(intel_crtc);
5183
5184 for_each_encoder_on_crtc(dev, crtc, encoder)
5185 if (encoder->post_disable)
5186 encoder->post_disable(encoder);
5187
5188 if (intel_crtc->config->has_pch_encoder) {
5189 lpt_disable_pch_transcoder(dev_priv);
5190 lpt_disable_iclkip(dev_priv);
5191 intel_ddi_fdi_disable(crtc);
5192
5193 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5194 true);
5195 }
5196
5197 intel_fbc_disable_crtc(intel_crtc);
5198 }
5199
5200 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5201 {
5202 struct drm_device *dev = crtc->base.dev;
5203 struct drm_i915_private *dev_priv = dev->dev_private;
5204 struct intel_crtc_state *pipe_config = crtc->config;
5205
5206 if (!pipe_config->gmch_pfit.control)
5207 return;
5208
5209 /*
5210 * The panel fitter should only be adjusted whilst the pipe is disabled,
5211 * according to register description and PRM.
5212 */
5213 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5214 assert_pipe_disabled(dev_priv, crtc->pipe);
5215
5216 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5217 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5218
5219 /* Border color in case we don't scale up to the full screen. Black by
5220 * default, change to something else for debugging. */
5221 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5222 }
5223
5224 static enum intel_display_power_domain port_to_power_domain(enum port port)
5225 {
5226 switch (port) {
5227 case PORT_A:
5228 return POWER_DOMAIN_PORT_DDI_A_LANES;
5229 case PORT_B:
5230 return POWER_DOMAIN_PORT_DDI_B_LANES;
5231 case PORT_C:
5232 return POWER_DOMAIN_PORT_DDI_C_LANES;
5233 case PORT_D:
5234 return POWER_DOMAIN_PORT_DDI_D_LANES;
5235 case PORT_E:
5236 return POWER_DOMAIN_PORT_DDI_E_LANES;
5237 default:
5238 MISSING_CASE(port);
5239 return POWER_DOMAIN_PORT_OTHER;
5240 }
5241 }
5242
5243 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5244 {
5245 switch (port) {
5246 case PORT_A:
5247 return POWER_DOMAIN_AUX_A;
5248 case PORT_B:
5249 return POWER_DOMAIN_AUX_B;
5250 case PORT_C:
5251 return POWER_DOMAIN_AUX_C;
5252 case PORT_D:
5253 return POWER_DOMAIN_AUX_D;
5254 case PORT_E:
5255 /* FIXME: Check VBT for actual wiring of PORT E */
5256 return POWER_DOMAIN_AUX_D;
5257 default:
5258 MISSING_CASE(port);
5259 return POWER_DOMAIN_AUX_A;
5260 }
5261 }
5262
5263 enum intel_display_power_domain
5264 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5265 {
5266 struct drm_device *dev = intel_encoder->base.dev;
5267 struct intel_digital_port *intel_dig_port;
5268
5269 switch (intel_encoder->type) {
5270 case INTEL_OUTPUT_UNKNOWN:
5271 /* Only DDI platforms should ever use this output type */
5272 WARN_ON_ONCE(!HAS_DDI(dev));
5273 case INTEL_OUTPUT_DISPLAYPORT:
5274 case INTEL_OUTPUT_HDMI:
5275 case INTEL_OUTPUT_EDP:
5276 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5277 return port_to_power_domain(intel_dig_port->port);
5278 case INTEL_OUTPUT_DP_MST:
5279 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5280 return port_to_power_domain(intel_dig_port->port);
5281 case INTEL_OUTPUT_ANALOG:
5282 return POWER_DOMAIN_PORT_CRT;
5283 case INTEL_OUTPUT_DSI:
5284 return POWER_DOMAIN_PORT_DSI;
5285 default:
5286 return POWER_DOMAIN_PORT_OTHER;
5287 }
5288 }
5289
5290 enum intel_display_power_domain
5291 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5292 {
5293 struct drm_device *dev = intel_encoder->base.dev;
5294 struct intel_digital_port *intel_dig_port;
5295
5296 switch (intel_encoder->type) {
5297 case INTEL_OUTPUT_UNKNOWN:
5298 case INTEL_OUTPUT_HDMI:
5299 /*
5300 * Only DDI platforms should ever use these output types.
5301 * We can get here after the HDMI detect code has already set
5302 * the type of the shared encoder. Since we can't be sure
5303 * what's the status of the given connectors, play safe and
5304 * run the DP detection too.
5305 */
5306 WARN_ON_ONCE(!HAS_DDI(dev));
5307 case INTEL_OUTPUT_DISPLAYPORT:
5308 case INTEL_OUTPUT_EDP:
5309 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5310 return port_to_aux_power_domain(intel_dig_port->port);
5311 case INTEL_OUTPUT_DP_MST:
5312 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5313 return port_to_aux_power_domain(intel_dig_port->port);
5314 default:
5315 MISSING_CASE(intel_encoder->type);
5316 return POWER_DOMAIN_AUX_A;
5317 }
5318 }
5319
5320 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5321 {
5322 struct drm_device *dev = crtc->dev;
5323 struct intel_encoder *intel_encoder;
5324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5325 enum pipe pipe = intel_crtc->pipe;
5326 unsigned long mask;
5327 enum transcoder transcoder = intel_crtc->config->cpu_transcoder;
5328
5329 if (!crtc->state->active)
5330 return 0;
5331
5332 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5333 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5334 if (intel_crtc->config->pch_pfit.enabled ||
5335 intel_crtc->config->pch_pfit.force_thru)
5336 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5337
5338 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5339 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5340
5341 return mask;
5342 }
5343
5344 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5345 {
5346 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5348 enum intel_display_power_domain domain;
5349 unsigned long domains, new_domains, old_domains;
5350
5351 old_domains = intel_crtc->enabled_power_domains;
5352 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5353
5354 domains = new_domains & ~old_domains;
5355
5356 for_each_power_domain(domain, domains)
5357 intel_display_power_get(dev_priv, domain);
5358
5359 return old_domains & ~new_domains;
5360 }
5361
5362 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5363 unsigned long domains)
5364 {
5365 enum intel_display_power_domain domain;
5366
5367 for_each_power_domain(domain, domains)
5368 intel_display_power_put(dev_priv, domain);
5369 }
5370
5371 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5372 {
5373 struct drm_device *dev = state->dev;
5374 struct drm_i915_private *dev_priv = dev->dev_private;
5375 unsigned long put_domains[I915_MAX_PIPES] = {};
5376 struct drm_crtc_state *crtc_state;
5377 struct drm_crtc *crtc;
5378 int i;
5379
5380 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5381 if (needs_modeset(crtc->state))
5382 put_domains[to_intel_crtc(crtc)->pipe] =
5383 modeset_get_crtc_power_domains(crtc);
5384 }
5385
5386 if (dev_priv->display.modeset_commit_cdclk) {
5387 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5388
5389 if (cdclk != dev_priv->cdclk_freq &&
5390 !WARN_ON(!state->allow_modeset))
5391 dev_priv->display.modeset_commit_cdclk(state);
5392 }
5393
5394 for (i = 0; i < I915_MAX_PIPES; i++)
5395 if (put_domains[i])
5396 modeset_put_power_domains(dev_priv, put_domains[i]);
5397 }
5398
5399 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5400 {
5401 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5402
5403 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5404 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5405 return max_cdclk_freq;
5406 else if (IS_CHERRYVIEW(dev_priv))
5407 return max_cdclk_freq*95/100;
5408 else if (INTEL_INFO(dev_priv)->gen < 4)
5409 return 2*max_cdclk_freq*90/100;
5410 else
5411 return max_cdclk_freq*90/100;
5412 }
5413
5414 static void intel_update_max_cdclk(struct drm_device *dev)
5415 {
5416 struct drm_i915_private *dev_priv = dev->dev_private;
5417
5418 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5419 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5420
5421 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5422 dev_priv->max_cdclk_freq = 675000;
5423 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5424 dev_priv->max_cdclk_freq = 540000;
5425 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5426 dev_priv->max_cdclk_freq = 450000;
5427 else
5428 dev_priv->max_cdclk_freq = 337500;
5429 } else if (IS_BROADWELL(dev)) {
5430 /*
5431 * FIXME with extra cooling we can allow
5432 * 540 MHz for ULX and 675 Mhz for ULT.
5433 * How can we know if extra cooling is
5434 * available? PCI ID, VTB, something else?
5435 */
5436 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5437 dev_priv->max_cdclk_freq = 450000;
5438 else if (IS_BDW_ULX(dev))
5439 dev_priv->max_cdclk_freq = 450000;
5440 else if (IS_BDW_ULT(dev))
5441 dev_priv->max_cdclk_freq = 540000;
5442 else
5443 dev_priv->max_cdclk_freq = 675000;
5444 } else if (IS_CHERRYVIEW(dev)) {
5445 dev_priv->max_cdclk_freq = 320000;
5446 } else if (IS_VALLEYVIEW(dev)) {
5447 dev_priv->max_cdclk_freq = 400000;
5448 } else {
5449 /* otherwise assume cdclk is fixed */
5450 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5451 }
5452
5453 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5454
5455 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5456 dev_priv->max_cdclk_freq);
5457
5458 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5459 dev_priv->max_dotclk_freq);
5460 }
5461
5462 static void intel_update_cdclk(struct drm_device *dev)
5463 {
5464 struct drm_i915_private *dev_priv = dev->dev_private;
5465
5466 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5467 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5468 dev_priv->cdclk_freq);
5469
5470 /*
5471 * Program the gmbus_freq based on the cdclk frequency.
5472 * BSpec erroneously claims we should aim for 4MHz, but
5473 * in fact 1MHz is the correct frequency.
5474 */
5475 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5476 /*
5477 * Program the gmbus_freq based on the cdclk frequency.
5478 * BSpec erroneously claims we should aim for 4MHz, but
5479 * in fact 1MHz is the correct frequency.
5480 */
5481 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5482 }
5483
5484 if (dev_priv->max_cdclk_freq == 0)
5485 intel_update_max_cdclk(dev);
5486 }
5487
5488 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5489 {
5490 struct drm_i915_private *dev_priv = dev->dev_private;
5491 uint32_t divider;
5492 uint32_t ratio;
5493 uint32_t current_freq;
5494 int ret;
5495
5496 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5497 switch (frequency) {
5498 case 144000:
5499 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5500 ratio = BXT_DE_PLL_RATIO(60);
5501 break;
5502 case 288000:
5503 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5504 ratio = BXT_DE_PLL_RATIO(60);
5505 break;
5506 case 384000:
5507 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5508 ratio = BXT_DE_PLL_RATIO(60);
5509 break;
5510 case 576000:
5511 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5512 ratio = BXT_DE_PLL_RATIO(60);
5513 break;
5514 case 624000:
5515 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5516 ratio = BXT_DE_PLL_RATIO(65);
5517 break;
5518 case 19200:
5519 /*
5520 * Bypass frequency with DE PLL disabled. Init ratio, divider
5521 * to suppress GCC warning.
5522 */
5523 ratio = 0;
5524 divider = 0;
5525 break;
5526 default:
5527 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5528
5529 return;
5530 }
5531
5532 mutex_lock(&dev_priv->rps.hw_lock);
5533 /* Inform power controller of upcoming frequency change */
5534 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5535 0x80000000);
5536 mutex_unlock(&dev_priv->rps.hw_lock);
5537
5538 if (ret) {
5539 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5540 ret, frequency);
5541 return;
5542 }
5543
5544 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5545 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5546 current_freq = current_freq * 500 + 1000;
5547
5548 /*
5549 * DE PLL has to be disabled when
5550 * - setting to 19.2MHz (bypass, PLL isn't used)
5551 * - before setting to 624MHz (PLL needs toggling)
5552 * - before setting to any frequency from 624MHz (PLL needs toggling)
5553 */
5554 if (frequency == 19200 || frequency == 624000 ||
5555 current_freq == 624000) {
5556 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5557 /* Timeout 200us */
5558 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5559 1))
5560 DRM_ERROR("timout waiting for DE PLL unlock\n");
5561 }
5562
5563 if (frequency != 19200) {
5564 uint32_t val;
5565
5566 val = I915_READ(BXT_DE_PLL_CTL);
5567 val &= ~BXT_DE_PLL_RATIO_MASK;
5568 val |= ratio;
5569 I915_WRITE(BXT_DE_PLL_CTL, val);
5570
5571 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5572 /* Timeout 200us */
5573 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5574 DRM_ERROR("timeout waiting for DE PLL lock\n");
5575
5576 val = I915_READ(CDCLK_CTL);
5577 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5578 val |= divider;
5579 /*
5580 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5581 * enable otherwise.
5582 */
5583 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5584 if (frequency >= 500000)
5585 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5586
5587 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5588 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5589 val |= (frequency - 1000) / 500;
5590 I915_WRITE(CDCLK_CTL, val);
5591 }
5592
5593 mutex_lock(&dev_priv->rps.hw_lock);
5594 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5595 DIV_ROUND_UP(frequency, 25000));
5596 mutex_unlock(&dev_priv->rps.hw_lock);
5597
5598 if (ret) {
5599 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5600 ret, frequency);
5601 return;
5602 }
5603
5604 intel_update_cdclk(dev);
5605 }
5606
5607 void broxton_init_cdclk(struct drm_device *dev)
5608 {
5609 struct drm_i915_private *dev_priv = dev->dev_private;
5610 uint32_t val;
5611
5612 /*
5613 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5614 * or else the reset will hang because there is no PCH to respond.
5615 * Move the handshake programming to initialization sequence.
5616 * Previously was left up to BIOS.
5617 */
5618 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5619 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5620 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5621
5622 /* Enable PG1 for cdclk */
5623 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5624
5625 /* check if cd clock is enabled */
5626 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5627 DRM_DEBUG_KMS("Display already initialized\n");
5628 return;
5629 }
5630
5631 /*
5632 * FIXME:
5633 * - The initial CDCLK needs to be read from VBT.
5634 * Need to make this change after VBT has changes for BXT.
5635 * - check if setting the max (or any) cdclk freq is really necessary
5636 * here, it belongs to modeset time
5637 */
5638 broxton_set_cdclk(dev, 624000);
5639
5640 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5641 POSTING_READ(DBUF_CTL);
5642
5643 udelay(10);
5644
5645 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5646 DRM_ERROR("DBuf power enable timeout!\n");
5647 }
5648
5649 void broxton_uninit_cdclk(struct drm_device *dev)
5650 {
5651 struct drm_i915_private *dev_priv = dev->dev_private;
5652
5653 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5654 POSTING_READ(DBUF_CTL);
5655
5656 udelay(10);
5657
5658 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5659 DRM_ERROR("DBuf power disable timeout!\n");
5660
5661 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5662 broxton_set_cdclk(dev, 19200);
5663
5664 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5665 }
5666
5667 static const struct skl_cdclk_entry {
5668 unsigned int freq;
5669 unsigned int vco;
5670 } skl_cdclk_frequencies[] = {
5671 { .freq = 308570, .vco = 8640 },
5672 { .freq = 337500, .vco = 8100 },
5673 { .freq = 432000, .vco = 8640 },
5674 { .freq = 450000, .vco = 8100 },
5675 { .freq = 540000, .vco = 8100 },
5676 { .freq = 617140, .vco = 8640 },
5677 { .freq = 675000, .vco = 8100 },
5678 };
5679
5680 static unsigned int skl_cdclk_decimal(unsigned int freq)
5681 {
5682 return (freq - 1000) / 500;
5683 }
5684
5685 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5686 {
5687 unsigned int i;
5688
5689 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5690 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5691
5692 if (e->freq == freq)
5693 return e->vco;
5694 }
5695
5696 return 8100;
5697 }
5698
5699 static void
5700 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5701 {
5702 unsigned int min_freq;
5703 u32 val;
5704
5705 /* select the minimum CDCLK before enabling DPLL 0 */
5706 val = I915_READ(CDCLK_CTL);
5707 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5708 val |= CDCLK_FREQ_337_308;
5709
5710 if (required_vco == 8640)
5711 min_freq = 308570;
5712 else
5713 min_freq = 337500;
5714
5715 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5716
5717 I915_WRITE(CDCLK_CTL, val);
5718 POSTING_READ(CDCLK_CTL);
5719
5720 /*
5721 * We always enable DPLL0 with the lowest link rate possible, but still
5722 * taking into account the VCO required to operate the eDP panel at the
5723 * desired frequency. The usual DP link rates operate with a VCO of
5724 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5725 * The modeset code is responsible for the selection of the exact link
5726 * rate later on, with the constraint of choosing a frequency that
5727 * works with required_vco.
5728 */
5729 val = I915_READ(DPLL_CTRL1);
5730
5731 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5732 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5733 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5734 if (required_vco == 8640)
5735 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5736 SKL_DPLL0);
5737 else
5738 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5739 SKL_DPLL0);
5740
5741 I915_WRITE(DPLL_CTRL1, val);
5742 POSTING_READ(DPLL_CTRL1);
5743
5744 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5745
5746 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5747 DRM_ERROR("DPLL0 not locked\n");
5748 }
5749
5750 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5751 {
5752 int ret;
5753 u32 val;
5754
5755 /* inform PCU we want to change CDCLK */
5756 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5757 mutex_lock(&dev_priv->rps.hw_lock);
5758 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5759 mutex_unlock(&dev_priv->rps.hw_lock);
5760
5761 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5762 }
5763
5764 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5765 {
5766 unsigned int i;
5767
5768 for (i = 0; i < 15; i++) {
5769 if (skl_cdclk_pcu_ready(dev_priv))
5770 return true;
5771 udelay(10);
5772 }
5773
5774 return false;
5775 }
5776
5777 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5778 {
5779 struct drm_device *dev = dev_priv->dev;
5780 u32 freq_select, pcu_ack;
5781
5782 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5783
5784 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5785 DRM_ERROR("failed to inform PCU about cdclk change\n");
5786 return;
5787 }
5788
5789 /* set CDCLK_CTL */
5790 switch(freq) {
5791 case 450000:
5792 case 432000:
5793 freq_select = CDCLK_FREQ_450_432;
5794 pcu_ack = 1;
5795 break;
5796 case 540000:
5797 freq_select = CDCLK_FREQ_540;
5798 pcu_ack = 2;
5799 break;
5800 case 308570:
5801 case 337500:
5802 default:
5803 freq_select = CDCLK_FREQ_337_308;
5804 pcu_ack = 0;
5805 break;
5806 case 617140:
5807 case 675000:
5808 freq_select = CDCLK_FREQ_675_617;
5809 pcu_ack = 3;
5810 break;
5811 }
5812
5813 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5814 POSTING_READ(CDCLK_CTL);
5815
5816 /* inform PCU of the change */
5817 mutex_lock(&dev_priv->rps.hw_lock);
5818 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5819 mutex_unlock(&dev_priv->rps.hw_lock);
5820
5821 intel_update_cdclk(dev);
5822 }
5823
5824 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5825 {
5826 /* disable DBUF power */
5827 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5828 POSTING_READ(DBUF_CTL);
5829
5830 udelay(10);
5831
5832 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5833 DRM_ERROR("DBuf power disable timeout\n");
5834
5835 /* disable DPLL0 */
5836 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5837 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5838 DRM_ERROR("Couldn't disable DPLL0\n");
5839 }
5840
5841 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5842 {
5843 unsigned int required_vco;
5844
5845 /* DPLL0 not enabled (happens on early BIOS versions) */
5846 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5847 /* enable DPLL0 */
5848 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5849 skl_dpll0_enable(dev_priv, required_vco);
5850 }
5851
5852 /* set CDCLK to the frequency the BIOS chose */
5853 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5854
5855 /* enable DBUF power */
5856 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5857 POSTING_READ(DBUF_CTL);
5858
5859 udelay(10);
5860
5861 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5862 DRM_ERROR("DBuf power enable timeout\n");
5863 }
5864
5865 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5866 {
5867 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5868 uint32_t cdctl = I915_READ(CDCLK_CTL);
5869 int freq = dev_priv->skl_boot_cdclk;
5870
5871 /*
5872 * check if the pre-os intialized the display
5873 * There is SWF18 scratchpad register defined which is set by the
5874 * pre-os which can be used by the OS drivers to check the status
5875 */
5876 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5877 goto sanitize;
5878
5879 /* Is PLL enabled and locked ? */
5880 if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5881 goto sanitize;
5882
5883 /* DPLL okay; verify the cdclock
5884 *
5885 * Noticed in some instances that the freq selection is correct but
5886 * decimal part is programmed wrong from BIOS where pre-os does not
5887 * enable display. Verify the same as well.
5888 */
5889 if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5890 /* All well; nothing to sanitize */
5891 return false;
5892 sanitize:
5893 /*
5894 * As of now initialize with max cdclk till
5895 * we get dynamic cdclk support
5896 * */
5897 dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5898 skl_init_cdclk(dev_priv);
5899
5900 /* we did have to sanitize */
5901 return true;
5902 }
5903
5904 /* Adjust CDclk dividers to allow high res or save power if possible */
5905 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5906 {
5907 struct drm_i915_private *dev_priv = dev->dev_private;
5908 u32 val, cmd;
5909
5910 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5911 != dev_priv->cdclk_freq);
5912
5913 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5914 cmd = 2;
5915 else if (cdclk == 266667)
5916 cmd = 1;
5917 else
5918 cmd = 0;
5919
5920 mutex_lock(&dev_priv->rps.hw_lock);
5921 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5922 val &= ~DSPFREQGUAR_MASK;
5923 val |= (cmd << DSPFREQGUAR_SHIFT);
5924 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5925 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5926 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5927 50)) {
5928 DRM_ERROR("timed out waiting for CDclk change\n");
5929 }
5930 mutex_unlock(&dev_priv->rps.hw_lock);
5931
5932 mutex_lock(&dev_priv->sb_lock);
5933
5934 if (cdclk == 400000) {
5935 u32 divider;
5936
5937 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5938
5939 /* adjust cdclk divider */
5940 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5941 val &= ~CCK_FREQUENCY_VALUES;
5942 val |= divider;
5943 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5944
5945 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5946 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5947 50))
5948 DRM_ERROR("timed out waiting for CDclk change\n");
5949 }
5950
5951 /* adjust self-refresh exit latency value */
5952 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5953 val &= ~0x7f;
5954
5955 /*
5956 * For high bandwidth configs, we set a higher latency in the bunit
5957 * so that the core display fetch happens in time to avoid underruns.
5958 */
5959 if (cdclk == 400000)
5960 val |= 4500 / 250; /* 4.5 usec */
5961 else
5962 val |= 3000 / 250; /* 3.0 usec */
5963 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5964
5965 mutex_unlock(&dev_priv->sb_lock);
5966
5967 intel_update_cdclk(dev);
5968 }
5969
5970 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5971 {
5972 struct drm_i915_private *dev_priv = dev->dev_private;
5973 u32 val, cmd;
5974
5975 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5976 != dev_priv->cdclk_freq);
5977
5978 switch (cdclk) {
5979 case 333333:
5980 case 320000:
5981 case 266667:
5982 case 200000:
5983 break;
5984 default:
5985 MISSING_CASE(cdclk);
5986 return;
5987 }
5988
5989 /*
5990 * Specs are full of misinformation, but testing on actual
5991 * hardware has shown that we just need to write the desired
5992 * CCK divider into the Punit register.
5993 */
5994 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5995
5996 mutex_lock(&dev_priv->rps.hw_lock);
5997 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5998 val &= ~DSPFREQGUAR_MASK_CHV;
5999 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6000 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6001 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6002 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6003 50)) {
6004 DRM_ERROR("timed out waiting for CDclk change\n");
6005 }
6006 mutex_unlock(&dev_priv->rps.hw_lock);
6007
6008 intel_update_cdclk(dev);
6009 }
6010
6011 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6012 int max_pixclk)
6013 {
6014 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6015 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6016
6017 /*
6018 * Really only a few cases to deal with, as only 4 CDclks are supported:
6019 * 200MHz
6020 * 267MHz
6021 * 320/333MHz (depends on HPLL freq)
6022 * 400MHz (VLV only)
6023 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6024 * of the lower bin and adjust if needed.
6025 *
6026 * We seem to get an unstable or solid color picture at 200MHz.
6027 * Not sure what's wrong. For now use 200MHz only when all pipes
6028 * are off.
6029 */
6030 if (!IS_CHERRYVIEW(dev_priv) &&
6031 max_pixclk > freq_320*limit/100)
6032 return 400000;
6033 else if (max_pixclk > 266667*limit/100)
6034 return freq_320;
6035 else if (max_pixclk > 0)
6036 return 266667;
6037 else
6038 return 200000;
6039 }
6040
6041 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
6042 int max_pixclk)
6043 {
6044 /*
6045 * FIXME:
6046 * - remove the guardband, it's not needed on BXT
6047 * - set 19.2MHz bypass frequency if there are no active pipes
6048 */
6049 if (max_pixclk > 576000*9/10)
6050 return 624000;
6051 else if (max_pixclk > 384000*9/10)
6052 return 576000;
6053 else if (max_pixclk > 288000*9/10)
6054 return 384000;
6055 else if (max_pixclk > 144000*9/10)
6056 return 288000;
6057 else
6058 return 144000;
6059 }
6060
6061 /* Compute the max pixel clock for new configuration. Uses atomic state if
6062 * that's non-NULL, look at current state otherwise. */
6063 static int intel_mode_max_pixclk(struct drm_device *dev,
6064 struct drm_atomic_state *state)
6065 {
6066 struct intel_crtc *intel_crtc;
6067 struct intel_crtc_state *crtc_state;
6068 int max_pixclk = 0;
6069
6070 for_each_intel_crtc(dev, intel_crtc) {
6071 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6072 if (IS_ERR(crtc_state))
6073 return PTR_ERR(crtc_state);
6074
6075 if (!crtc_state->base.enable)
6076 continue;
6077
6078 max_pixclk = max(max_pixclk,
6079 crtc_state->base.adjusted_mode.crtc_clock);
6080 }
6081
6082 return max_pixclk;
6083 }
6084
6085 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6086 {
6087 struct drm_device *dev = state->dev;
6088 struct drm_i915_private *dev_priv = dev->dev_private;
6089 int max_pixclk = intel_mode_max_pixclk(dev, state);
6090
6091 if (max_pixclk < 0)
6092 return max_pixclk;
6093
6094 to_intel_atomic_state(state)->cdclk =
6095 valleyview_calc_cdclk(dev_priv, max_pixclk);
6096
6097 return 0;
6098 }
6099
6100 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6101 {
6102 struct drm_device *dev = state->dev;
6103 struct drm_i915_private *dev_priv = dev->dev_private;
6104 int max_pixclk = intel_mode_max_pixclk(dev, state);
6105
6106 if (max_pixclk < 0)
6107 return max_pixclk;
6108
6109 to_intel_atomic_state(state)->cdclk =
6110 broxton_calc_cdclk(dev_priv, max_pixclk);
6111
6112 return 0;
6113 }
6114
6115 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6116 {
6117 unsigned int credits, default_credits;
6118
6119 if (IS_CHERRYVIEW(dev_priv))
6120 default_credits = PFI_CREDIT(12);
6121 else
6122 default_credits = PFI_CREDIT(8);
6123
6124 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6125 /* CHV suggested value is 31 or 63 */
6126 if (IS_CHERRYVIEW(dev_priv))
6127 credits = PFI_CREDIT_63;
6128 else
6129 credits = PFI_CREDIT(15);
6130 } else {
6131 credits = default_credits;
6132 }
6133
6134 /*
6135 * WA - write default credits before re-programming
6136 * FIXME: should we also set the resend bit here?
6137 */
6138 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6139 default_credits);
6140
6141 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6142 credits | PFI_CREDIT_RESEND);
6143
6144 /*
6145 * FIXME is this guaranteed to clear
6146 * immediately or should we poll for it?
6147 */
6148 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6149 }
6150
6151 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6152 {
6153 struct drm_device *dev = old_state->dev;
6154 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6155 struct drm_i915_private *dev_priv = dev->dev_private;
6156
6157 /*
6158 * FIXME: We can end up here with all power domains off, yet
6159 * with a CDCLK frequency other than the minimum. To account
6160 * for this take the PIPE-A power domain, which covers the HW
6161 * blocks needed for the following programming. This can be
6162 * removed once it's guaranteed that we get here either with
6163 * the minimum CDCLK set, or the required power domains
6164 * enabled.
6165 */
6166 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6167
6168 if (IS_CHERRYVIEW(dev))
6169 cherryview_set_cdclk(dev, req_cdclk);
6170 else
6171 valleyview_set_cdclk(dev, req_cdclk);
6172
6173 vlv_program_pfi_credits(dev_priv);
6174
6175 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6176 }
6177
6178 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6179 {
6180 struct drm_device *dev = crtc->dev;
6181 struct drm_i915_private *dev_priv = to_i915(dev);
6182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6183 struct intel_encoder *encoder;
6184 int pipe = intel_crtc->pipe;
6185
6186 if (WARN_ON(intel_crtc->active))
6187 return;
6188
6189 if (intel_crtc->config->has_dp_encoder)
6190 intel_dp_set_m_n(intel_crtc, M1_N1);
6191
6192 intel_set_pipe_timings(intel_crtc);
6193
6194 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6195 struct drm_i915_private *dev_priv = dev->dev_private;
6196
6197 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6198 I915_WRITE(CHV_CANVAS(pipe), 0);
6199 }
6200
6201 i9xx_set_pipeconf(intel_crtc);
6202
6203 intel_crtc->active = true;
6204
6205 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6206
6207 for_each_encoder_on_crtc(dev, crtc, encoder)
6208 if (encoder->pre_pll_enable)
6209 encoder->pre_pll_enable(encoder);
6210
6211 if (!intel_crtc->config->has_dsi_encoder) {
6212 if (IS_CHERRYVIEW(dev)) {
6213 chv_prepare_pll(intel_crtc, intel_crtc->config);
6214 chv_enable_pll(intel_crtc, intel_crtc->config);
6215 } else {
6216 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6217 vlv_enable_pll(intel_crtc, intel_crtc->config);
6218 }
6219 }
6220
6221 for_each_encoder_on_crtc(dev, crtc, encoder)
6222 if (encoder->pre_enable)
6223 encoder->pre_enable(encoder);
6224
6225 i9xx_pfit_enable(intel_crtc);
6226
6227 intel_crtc_load_lut(crtc);
6228
6229 intel_enable_pipe(intel_crtc);
6230
6231 assert_vblank_disabled(crtc);
6232 drm_crtc_vblank_on(crtc);
6233
6234 for_each_encoder_on_crtc(dev, crtc, encoder)
6235 encoder->enable(encoder);
6236 }
6237
6238 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6239 {
6240 struct drm_device *dev = crtc->base.dev;
6241 struct drm_i915_private *dev_priv = dev->dev_private;
6242
6243 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6244 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6245 }
6246
6247 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6248 {
6249 struct drm_device *dev = crtc->dev;
6250 struct drm_i915_private *dev_priv = to_i915(dev);
6251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6252 struct intel_encoder *encoder;
6253 int pipe = intel_crtc->pipe;
6254
6255 if (WARN_ON(intel_crtc->active))
6256 return;
6257
6258 i9xx_set_pll_dividers(intel_crtc);
6259
6260 if (intel_crtc->config->has_dp_encoder)
6261 intel_dp_set_m_n(intel_crtc, M1_N1);
6262
6263 intel_set_pipe_timings(intel_crtc);
6264
6265 i9xx_set_pipeconf(intel_crtc);
6266
6267 intel_crtc->active = true;
6268
6269 if (!IS_GEN2(dev))
6270 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6271
6272 for_each_encoder_on_crtc(dev, crtc, encoder)
6273 if (encoder->pre_enable)
6274 encoder->pre_enable(encoder);
6275
6276 i9xx_enable_pll(intel_crtc);
6277
6278 i9xx_pfit_enable(intel_crtc);
6279
6280 intel_crtc_load_lut(crtc);
6281
6282 intel_update_watermarks(crtc);
6283 intel_enable_pipe(intel_crtc);
6284
6285 assert_vblank_disabled(crtc);
6286 drm_crtc_vblank_on(crtc);
6287
6288 for_each_encoder_on_crtc(dev, crtc, encoder)
6289 encoder->enable(encoder);
6290
6291 intel_fbc_enable(intel_crtc);
6292 }
6293
6294 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6295 {
6296 struct drm_device *dev = crtc->base.dev;
6297 struct drm_i915_private *dev_priv = dev->dev_private;
6298
6299 if (!crtc->config->gmch_pfit.control)
6300 return;
6301
6302 assert_pipe_disabled(dev_priv, crtc->pipe);
6303
6304 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6305 I915_READ(PFIT_CONTROL));
6306 I915_WRITE(PFIT_CONTROL, 0);
6307 }
6308
6309 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6310 {
6311 struct drm_device *dev = crtc->dev;
6312 struct drm_i915_private *dev_priv = dev->dev_private;
6313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6314 struct intel_encoder *encoder;
6315 int pipe = intel_crtc->pipe;
6316
6317 /*
6318 * On gen2 planes are double buffered but the pipe isn't, so we must
6319 * wait for planes to fully turn off before disabling the pipe.
6320 * We also need to wait on all gmch platforms because of the
6321 * self-refresh mode constraint explained above.
6322 */
6323 intel_wait_for_vblank(dev, pipe);
6324
6325 for_each_encoder_on_crtc(dev, crtc, encoder)
6326 encoder->disable(encoder);
6327
6328 drm_crtc_vblank_off(crtc);
6329 assert_vblank_disabled(crtc);
6330
6331 intel_disable_pipe(intel_crtc);
6332
6333 i9xx_pfit_disable(intel_crtc);
6334
6335 for_each_encoder_on_crtc(dev, crtc, encoder)
6336 if (encoder->post_disable)
6337 encoder->post_disable(encoder);
6338
6339 if (!intel_crtc->config->has_dsi_encoder) {
6340 if (IS_CHERRYVIEW(dev))
6341 chv_disable_pll(dev_priv, pipe);
6342 else if (IS_VALLEYVIEW(dev))
6343 vlv_disable_pll(dev_priv, pipe);
6344 else
6345 i9xx_disable_pll(intel_crtc);
6346 }
6347
6348 for_each_encoder_on_crtc(dev, crtc, encoder)
6349 if (encoder->post_pll_disable)
6350 encoder->post_pll_disable(encoder);
6351
6352 if (!IS_GEN2(dev))
6353 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6354
6355 intel_fbc_disable_crtc(intel_crtc);
6356 }
6357
6358 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6359 {
6360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6361 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6362 enum intel_display_power_domain domain;
6363 unsigned long domains;
6364
6365 if (!intel_crtc->active)
6366 return;
6367
6368 if (to_intel_plane_state(crtc->primary->state)->visible) {
6369 WARN_ON(intel_crtc->unpin_work);
6370
6371 intel_pre_disable_primary(crtc);
6372
6373 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6374 to_intel_plane_state(crtc->primary->state)->visible = false;
6375 }
6376
6377 dev_priv->display.crtc_disable(crtc);
6378 intel_crtc->active = false;
6379 intel_update_watermarks(crtc);
6380 intel_disable_shared_dpll(intel_crtc);
6381
6382 domains = intel_crtc->enabled_power_domains;
6383 for_each_power_domain(domain, domains)
6384 intel_display_power_put(dev_priv, domain);
6385 intel_crtc->enabled_power_domains = 0;
6386 }
6387
6388 /*
6389 * turn all crtc's off, but do not adjust state
6390 * This has to be paired with a call to intel_modeset_setup_hw_state.
6391 */
6392 int intel_display_suspend(struct drm_device *dev)
6393 {
6394 struct drm_mode_config *config = &dev->mode_config;
6395 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6396 struct drm_atomic_state *state;
6397 struct drm_crtc *crtc;
6398 unsigned crtc_mask = 0;
6399 int ret = 0;
6400
6401 if (WARN_ON(!ctx))
6402 return 0;
6403
6404 lockdep_assert_held(&ctx->ww_ctx);
6405 state = drm_atomic_state_alloc(dev);
6406 if (WARN_ON(!state))
6407 return -ENOMEM;
6408
6409 state->acquire_ctx = ctx;
6410 state->allow_modeset = true;
6411
6412 for_each_crtc(dev, crtc) {
6413 struct drm_crtc_state *crtc_state =
6414 drm_atomic_get_crtc_state(state, crtc);
6415
6416 ret = PTR_ERR_OR_ZERO(crtc_state);
6417 if (ret)
6418 goto free;
6419
6420 if (!crtc_state->active)
6421 continue;
6422
6423 crtc_state->active = false;
6424 crtc_mask |= 1 << drm_crtc_index(crtc);
6425 }
6426
6427 if (crtc_mask) {
6428 ret = drm_atomic_commit(state);
6429
6430 if (!ret) {
6431 for_each_crtc(dev, crtc)
6432 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6433 crtc->state->active = true;
6434
6435 return ret;
6436 }
6437 }
6438
6439 free:
6440 if (ret)
6441 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6442 drm_atomic_state_free(state);
6443 return ret;
6444 }
6445
6446 void intel_encoder_destroy(struct drm_encoder *encoder)
6447 {
6448 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6449
6450 drm_encoder_cleanup(encoder);
6451 kfree(intel_encoder);
6452 }
6453
6454 /* Cross check the actual hw state with our own modeset state tracking (and it's
6455 * internal consistency). */
6456 static void intel_connector_check_state(struct intel_connector *connector)
6457 {
6458 struct drm_crtc *crtc = connector->base.state->crtc;
6459
6460 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6461 connector->base.base.id,
6462 connector->base.name);
6463
6464 if (connector->get_hw_state(connector)) {
6465 struct intel_encoder *encoder = connector->encoder;
6466 struct drm_connector_state *conn_state = connector->base.state;
6467
6468 I915_STATE_WARN(!crtc,
6469 "connector enabled without attached crtc\n");
6470
6471 if (!crtc)
6472 return;
6473
6474 I915_STATE_WARN(!crtc->state->active,
6475 "connector is active, but attached crtc isn't\n");
6476
6477 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6478 return;
6479
6480 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6481 "atomic encoder doesn't match attached encoder\n");
6482
6483 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6484 "attached encoder crtc differs from connector crtc\n");
6485 } else {
6486 I915_STATE_WARN(crtc && crtc->state->active,
6487 "attached crtc is active, but connector isn't\n");
6488 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6489 "best encoder set without crtc!\n");
6490 }
6491 }
6492
6493 int intel_connector_init(struct intel_connector *connector)
6494 {
6495 drm_atomic_helper_connector_reset(&connector->base);
6496
6497 if (!connector->base.state)
6498 return -ENOMEM;
6499
6500 return 0;
6501 }
6502
6503 struct intel_connector *intel_connector_alloc(void)
6504 {
6505 struct intel_connector *connector;
6506
6507 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6508 if (!connector)
6509 return NULL;
6510
6511 if (intel_connector_init(connector) < 0) {
6512 kfree(connector);
6513 return NULL;
6514 }
6515
6516 return connector;
6517 }
6518
6519 /* Simple connector->get_hw_state implementation for encoders that support only
6520 * one connector and no cloning and hence the encoder state determines the state
6521 * of the connector. */
6522 bool intel_connector_get_hw_state(struct intel_connector *connector)
6523 {
6524 enum pipe pipe = 0;
6525 struct intel_encoder *encoder = connector->encoder;
6526
6527 return encoder->get_hw_state(encoder, &pipe);
6528 }
6529
6530 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6531 {
6532 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6533 return crtc_state->fdi_lanes;
6534
6535 return 0;
6536 }
6537
6538 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6539 struct intel_crtc_state *pipe_config)
6540 {
6541 struct drm_atomic_state *state = pipe_config->base.state;
6542 struct intel_crtc *other_crtc;
6543 struct intel_crtc_state *other_crtc_state;
6544
6545 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6546 pipe_name(pipe), pipe_config->fdi_lanes);
6547 if (pipe_config->fdi_lanes > 4) {
6548 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6549 pipe_name(pipe), pipe_config->fdi_lanes);
6550 return -EINVAL;
6551 }
6552
6553 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6554 if (pipe_config->fdi_lanes > 2) {
6555 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6556 pipe_config->fdi_lanes);
6557 return -EINVAL;
6558 } else {
6559 return 0;
6560 }
6561 }
6562
6563 if (INTEL_INFO(dev)->num_pipes == 2)
6564 return 0;
6565
6566 /* Ivybridge 3 pipe is really complicated */
6567 switch (pipe) {
6568 case PIPE_A:
6569 return 0;
6570 case PIPE_B:
6571 if (pipe_config->fdi_lanes <= 2)
6572 return 0;
6573
6574 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6575 other_crtc_state =
6576 intel_atomic_get_crtc_state(state, other_crtc);
6577 if (IS_ERR(other_crtc_state))
6578 return PTR_ERR(other_crtc_state);
6579
6580 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6581 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6582 pipe_name(pipe), pipe_config->fdi_lanes);
6583 return -EINVAL;
6584 }
6585 return 0;
6586 case PIPE_C:
6587 if (pipe_config->fdi_lanes > 2) {
6588 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6589 pipe_name(pipe), pipe_config->fdi_lanes);
6590 return -EINVAL;
6591 }
6592
6593 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6594 other_crtc_state =
6595 intel_atomic_get_crtc_state(state, other_crtc);
6596 if (IS_ERR(other_crtc_state))
6597 return PTR_ERR(other_crtc_state);
6598
6599 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6600 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6601 return -EINVAL;
6602 }
6603 return 0;
6604 default:
6605 BUG();
6606 }
6607 }
6608
6609 #define RETRY 1
6610 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6611 struct intel_crtc_state *pipe_config)
6612 {
6613 struct drm_device *dev = intel_crtc->base.dev;
6614 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6615 int lane, link_bw, fdi_dotclock, ret;
6616 bool needs_recompute = false;
6617
6618 retry:
6619 /* FDI is a binary signal running at ~2.7GHz, encoding
6620 * each output octet as 10 bits. The actual frequency
6621 * is stored as a divider into a 100MHz clock, and the
6622 * mode pixel clock is stored in units of 1KHz.
6623 * Hence the bw of each lane in terms of the mode signal
6624 * is:
6625 */
6626 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6627
6628 fdi_dotclock = adjusted_mode->crtc_clock;
6629
6630 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6631 pipe_config->pipe_bpp);
6632
6633 pipe_config->fdi_lanes = lane;
6634
6635 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6636 link_bw, &pipe_config->fdi_m_n);
6637
6638 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6639 intel_crtc->pipe, pipe_config);
6640 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6641 pipe_config->pipe_bpp -= 2*3;
6642 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6643 pipe_config->pipe_bpp);
6644 needs_recompute = true;
6645 pipe_config->bw_constrained = true;
6646
6647 goto retry;
6648 }
6649
6650 if (needs_recompute)
6651 return RETRY;
6652
6653 return ret;
6654 }
6655
6656 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6657 struct intel_crtc_state *pipe_config)
6658 {
6659 if (pipe_config->pipe_bpp > 24)
6660 return false;
6661
6662 /* HSW can handle pixel rate up to cdclk? */
6663 if (IS_HASWELL(dev_priv->dev))
6664 return true;
6665
6666 /*
6667 * We compare against max which means we must take
6668 * the increased cdclk requirement into account when
6669 * calculating the new cdclk.
6670 *
6671 * Should measure whether using a lower cdclk w/o IPS
6672 */
6673 return ilk_pipe_pixel_rate(pipe_config) <=
6674 dev_priv->max_cdclk_freq * 95 / 100;
6675 }
6676
6677 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6678 struct intel_crtc_state *pipe_config)
6679 {
6680 struct drm_device *dev = crtc->base.dev;
6681 struct drm_i915_private *dev_priv = dev->dev_private;
6682
6683 pipe_config->ips_enabled = i915.enable_ips &&
6684 hsw_crtc_supports_ips(crtc) &&
6685 pipe_config_supports_ips(dev_priv, pipe_config);
6686 }
6687
6688 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6689 {
6690 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6691
6692 /* GDG double wide on either pipe, otherwise pipe A only */
6693 return INTEL_INFO(dev_priv)->gen < 4 &&
6694 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6695 }
6696
6697 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6698 struct intel_crtc_state *pipe_config)
6699 {
6700 struct drm_device *dev = crtc->base.dev;
6701 struct drm_i915_private *dev_priv = dev->dev_private;
6702 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6703
6704 /* FIXME should check pixel clock limits on all platforms */
6705 if (INTEL_INFO(dev)->gen < 4) {
6706 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6707
6708 /*
6709 * Enable double wide mode when the dot clock
6710 * is > 90% of the (display) core speed.
6711 */
6712 if (intel_crtc_supports_double_wide(crtc) &&
6713 adjusted_mode->crtc_clock > clock_limit) {
6714 clock_limit *= 2;
6715 pipe_config->double_wide = true;
6716 }
6717
6718 if (adjusted_mode->crtc_clock > clock_limit) {
6719 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6720 adjusted_mode->crtc_clock, clock_limit,
6721 yesno(pipe_config->double_wide));
6722 return -EINVAL;
6723 }
6724 }
6725
6726 /*
6727 * Pipe horizontal size must be even in:
6728 * - DVO ganged mode
6729 * - LVDS dual channel mode
6730 * - Double wide pipe
6731 */
6732 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6733 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6734 pipe_config->pipe_src_w &= ~1;
6735
6736 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6737 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6738 */
6739 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6740 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6741 return -EINVAL;
6742
6743 if (HAS_IPS(dev))
6744 hsw_compute_ips_config(crtc, pipe_config);
6745
6746 if (pipe_config->has_pch_encoder)
6747 return ironlake_fdi_compute_config(crtc, pipe_config);
6748
6749 return 0;
6750 }
6751
6752 static int skylake_get_display_clock_speed(struct drm_device *dev)
6753 {
6754 struct drm_i915_private *dev_priv = to_i915(dev);
6755 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6756 uint32_t cdctl = I915_READ(CDCLK_CTL);
6757 uint32_t linkrate;
6758
6759 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6760 return 24000; /* 24MHz is the cd freq with NSSC ref */
6761
6762 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6763 return 540000;
6764
6765 linkrate = (I915_READ(DPLL_CTRL1) &
6766 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6767
6768 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6769 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6770 /* vco 8640 */
6771 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6772 case CDCLK_FREQ_450_432:
6773 return 432000;
6774 case CDCLK_FREQ_337_308:
6775 return 308570;
6776 case CDCLK_FREQ_675_617:
6777 return 617140;
6778 default:
6779 WARN(1, "Unknown cd freq selection\n");
6780 }
6781 } else {
6782 /* vco 8100 */
6783 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6784 case CDCLK_FREQ_450_432:
6785 return 450000;
6786 case CDCLK_FREQ_337_308:
6787 return 337500;
6788 case CDCLK_FREQ_675_617:
6789 return 675000;
6790 default:
6791 WARN(1, "Unknown cd freq selection\n");
6792 }
6793 }
6794
6795 /* error case, do as if DPLL0 isn't enabled */
6796 return 24000;
6797 }
6798
6799 static int broxton_get_display_clock_speed(struct drm_device *dev)
6800 {
6801 struct drm_i915_private *dev_priv = to_i915(dev);
6802 uint32_t cdctl = I915_READ(CDCLK_CTL);
6803 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6804 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6805 int cdclk;
6806
6807 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6808 return 19200;
6809
6810 cdclk = 19200 * pll_ratio / 2;
6811
6812 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6813 case BXT_CDCLK_CD2X_DIV_SEL_1:
6814 return cdclk; /* 576MHz or 624MHz */
6815 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6816 return cdclk * 2 / 3; /* 384MHz */
6817 case BXT_CDCLK_CD2X_DIV_SEL_2:
6818 return cdclk / 2; /* 288MHz */
6819 case BXT_CDCLK_CD2X_DIV_SEL_4:
6820 return cdclk / 4; /* 144MHz */
6821 }
6822
6823 /* error case, do as if DE PLL isn't enabled */
6824 return 19200;
6825 }
6826
6827 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6828 {
6829 struct drm_i915_private *dev_priv = dev->dev_private;
6830 uint32_t lcpll = I915_READ(LCPLL_CTL);
6831 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6832
6833 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6834 return 800000;
6835 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6836 return 450000;
6837 else if (freq == LCPLL_CLK_FREQ_450)
6838 return 450000;
6839 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6840 return 540000;
6841 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6842 return 337500;
6843 else
6844 return 675000;
6845 }
6846
6847 static int haswell_get_display_clock_speed(struct drm_device *dev)
6848 {
6849 struct drm_i915_private *dev_priv = dev->dev_private;
6850 uint32_t lcpll = I915_READ(LCPLL_CTL);
6851 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6852
6853 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6854 return 800000;
6855 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6856 return 450000;
6857 else if (freq == LCPLL_CLK_FREQ_450)
6858 return 450000;
6859 else if (IS_HSW_ULT(dev))
6860 return 337500;
6861 else
6862 return 540000;
6863 }
6864
6865 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6866 {
6867 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6868 CCK_DISPLAY_CLOCK_CONTROL);
6869 }
6870
6871 static int ilk_get_display_clock_speed(struct drm_device *dev)
6872 {
6873 return 450000;
6874 }
6875
6876 static int i945_get_display_clock_speed(struct drm_device *dev)
6877 {
6878 return 400000;
6879 }
6880
6881 static int i915_get_display_clock_speed(struct drm_device *dev)
6882 {
6883 return 333333;
6884 }
6885
6886 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6887 {
6888 return 200000;
6889 }
6890
6891 static int pnv_get_display_clock_speed(struct drm_device *dev)
6892 {
6893 u16 gcfgc = 0;
6894
6895 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6896
6897 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6898 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6899 return 266667;
6900 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6901 return 333333;
6902 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6903 return 444444;
6904 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6905 return 200000;
6906 default:
6907 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6908 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6909 return 133333;
6910 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6911 return 166667;
6912 }
6913 }
6914
6915 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6916 {
6917 u16 gcfgc = 0;
6918
6919 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6920
6921 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6922 return 133333;
6923 else {
6924 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6925 case GC_DISPLAY_CLOCK_333_MHZ:
6926 return 333333;
6927 default:
6928 case GC_DISPLAY_CLOCK_190_200_MHZ:
6929 return 190000;
6930 }
6931 }
6932 }
6933
6934 static int i865_get_display_clock_speed(struct drm_device *dev)
6935 {
6936 return 266667;
6937 }
6938
6939 static int i85x_get_display_clock_speed(struct drm_device *dev)
6940 {
6941 u16 hpllcc = 0;
6942
6943 /*
6944 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6945 * encoding is different :(
6946 * FIXME is this the right way to detect 852GM/852GMV?
6947 */
6948 if (dev->pdev->revision == 0x1)
6949 return 133333;
6950
6951 pci_bus_read_config_word(dev->pdev->bus,
6952 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6953
6954 /* Assume that the hardware is in the high speed state. This
6955 * should be the default.
6956 */
6957 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6958 case GC_CLOCK_133_200:
6959 case GC_CLOCK_133_200_2:
6960 case GC_CLOCK_100_200:
6961 return 200000;
6962 case GC_CLOCK_166_250:
6963 return 250000;
6964 case GC_CLOCK_100_133:
6965 return 133333;
6966 case GC_CLOCK_133_266:
6967 case GC_CLOCK_133_266_2:
6968 case GC_CLOCK_166_266:
6969 return 266667;
6970 }
6971
6972 /* Shouldn't happen */
6973 return 0;
6974 }
6975
6976 static int i830_get_display_clock_speed(struct drm_device *dev)
6977 {
6978 return 133333;
6979 }
6980
6981 static unsigned int intel_hpll_vco(struct drm_device *dev)
6982 {
6983 struct drm_i915_private *dev_priv = dev->dev_private;
6984 static const unsigned int blb_vco[8] = {
6985 [0] = 3200000,
6986 [1] = 4000000,
6987 [2] = 5333333,
6988 [3] = 4800000,
6989 [4] = 6400000,
6990 };
6991 static const unsigned int pnv_vco[8] = {
6992 [0] = 3200000,
6993 [1] = 4000000,
6994 [2] = 5333333,
6995 [3] = 4800000,
6996 [4] = 2666667,
6997 };
6998 static const unsigned int cl_vco[8] = {
6999 [0] = 3200000,
7000 [1] = 4000000,
7001 [2] = 5333333,
7002 [3] = 6400000,
7003 [4] = 3333333,
7004 [5] = 3566667,
7005 [6] = 4266667,
7006 };
7007 static const unsigned int elk_vco[8] = {
7008 [0] = 3200000,
7009 [1] = 4000000,
7010 [2] = 5333333,
7011 [3] = 4800000,
7012 };
7013 static const unsigned int ctg_vco[8] = {
7014 [0] = 3200000,
7015 [1] = 4000000,
7016 [2] = 5333333,
7017 [3] = 6400000,
7018 [4] = 2666667,
7019 [5] = 4266667,
7020 };
7021 const unsigned int *vco_table;
7022 unsigned int vco;
7023 uint8_t tmp = 0;
7024
7025 /* FIXME other chipsets? */
7026 if (IS_GM45(dev))
7027 vco_table = ctg_vco;
7028 else if (IS_G4X(dev))
7029 vco_table = elk_vco;
7030 else if (IS_CRESTLINE(dev))
7031 vco_table = cl_vco;
7032 else if (IS_PINEVIEW(dev))
7033 vco_table = pnv_vco;
7034 else if (IS_G33(dev))
7035 vco_table = blb_vco;
7036 else
7037 return 0;
7038
7039 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7040
7041 vco = vco_table[tmp & 0x7];
7042 if (vco == 0)
7043 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7044 else
7045 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7046
7047 return vco;
7048 }
7049
7050 static int gm45_get_display_clock_speed(struct drm_device *dev)
7051 {
7052 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7053 uint16_t tmp = 0;
7054
7055 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7056
7057 cdclk_sel = (tmp >> 12) & 0x1;
7058
7059 switch (vco) {
7060 case 2666667:
7061 case 4000000:
7062 case 5333333:
7063 return cdclk_sel ? 333333 : 222222;
7064 case 3200000:
7065 return cdclk_sel ? 320000 : 228571;
7066 default:
7067 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7068 return 222222;
7069 }
7070 }
7071
7072 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7073 {
7074 static const uint8_t div_3200[] = { 16, 10, 8 };
7075 static const uint8_t div_4000[] = { 20, 12, 10 };
7076 static const uint8_t div_5333[] = { 24, 16, 14 };
7077 const uint8_t *div_table;
7078 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7079 uint16_t tmp = 0;
7080
7081 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7082
7083 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7084
7085 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7086 goto fail;
7087
7088 switch (vco) {
7089 case 3200000:
7090 div_table = div_3200;
7091 break;
7092 case 4000000:
7093 div_table = div_4000;
7094 break;
7095 case 5333333:
7096 div_table = div_5333;
7097 break;
7098 default:
7099 goto fail;
7100 }
7101
7102 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7103
7104 fail:
7105 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7106 return 200000;
7107 }
7108
7109 static int g33_get_display_clock_speed(struct drm_device *dev)
7110 {
7111 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7112 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7113 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7114 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7115 const uint8_t *div_table;
7116 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7117 uint16_t tmp = 0;
7118
7119 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7120
7121 cdclk_sel = (tmp >> 4) & 0x7;
7122
7123 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7124 goto fail;
7125
7126 switch (vco) {
7127 case 3200000:
7128 div_table = div_3200;
7129 break;
7130 case 4000000:
7131 div_table = div_4000;
7132 break;
7133 case 4800000:
7134 div_table = div_4800;
7135 break;
7136 case 5333333:
7137 div_table = div_5333;
7138 break;
7139 default:
7140 goto fail;
7141 }
7142
7143 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7144
7145 fail:
7146 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7147 return 190476;
7148 }
7149
7150 static void
7151 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7152 {
7153 while (*num > DATA_LINK_M_N_MASK ||
7154 *den > DATA_LINK_M_N_MASK) {
7155 *num >>= 1;
7156 *den >>= 1;
7157 }
7158 }
7159
7160 static void compute_m_n(unsigned int m, unsigned int n,
7161 uint32_t *ret_m, uint32_t *ret_n)
7162 {
7163 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7164 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7165 intel_reduce_m_n_ratio(ret_m, ret_n);
7166 }
7167
7168 void
7169 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7170 int pixel_clock, int link_clock,
7171 struct intel_link_m_n *m_n)
7172 {
7173 m_n->tu = 64;
7174
7175 compute_m_n(bits_per_pixel * pixel_clock,
7176 link_clock * nlanes * 8,
7177 &m_n->gmch_m, &m_n->gmch_n);
7178
7179 compute_m_n(pixel_clock, link_clock,
7180 &m_n->link_m, &m_n->link_n);
7181 }
7182
7183 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7184 {
7185 if (i915.panel_use_ssc >= 0)
7186 return i915.panel_use_ssc != 0;
7187 return dev_priv->vbt.lvds_use_ssc
7188 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7189 }
7190
7191 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7192 int num_connectors)
7193 {
7194 struct drm_device *dev = crtc_state->base.crtc->dev;
7195 struct drm_i915_private *dev_priv = dev->dev_private;
7196 int refclk;
7197
7198 WARN_ON(!crtc_state->base.state);
7199
7200 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
7201 refclk = 100000;
7202 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7203 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7204 refclk = dev_priv->vbt.lvds_ssc_freq;
7205 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7206 } else if (!IS_GEN2(dev)) {
7207 refclk = 96000;
7208 } else {
7209 refclk = 48000;
7210 }
7211
7212 return refclk;
7213 }
7214
7215 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7216 {
7217 return (1 << dpll->n) << 16 | dpll->m2;
7218 }
7219
7220 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7221 {
7222 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7223 }
7224
7225 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7226 struct intel_crtc_state *crtc_state,
7227 intel_clock_t *reduced_clock)
7228 {
7229 struct drm_device *dev = crtc->base.dev;
7230 u32 fp, fp2 = 0;
7231
7232 if (IS_PINEVIEW(dev)) {
7233 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7234 if (reduced_clock)
7235 fp2 = pnv_dpll_compute_fp(reduced_clock);
7236 } else {
7237 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7238 if (reduced_clock)
7239 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7240 }
7241
7242 crtc_state->dpll_hw_state.fp0 = fp;
7243
7244 crtc->lowfreq_avail = false;
7245 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7246 reduced_clock) {
7247 crtc_state->dpll_hw_state.fp1 = fp2;
7248 crtc->lowfreq_avail = true;
7249 } else {
7250 crtc_state->dpll_hw_state.fp1 = fp;
7251 }
7252 }
7253
7254 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7255 pipe)
7256 {
7257 u32 reg_val;
7258
7259 /*
7260 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7261 * and set it to a reasonable value instead.
7262 */
7263 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7264 reg_val &= 0xffffff00;
7265 reg_val |= 0x00000030;
7266 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7267
7268 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7269 reg_val &= 0x8cffffff;
7270 reg_val = 0x8c000000;
7271 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7272
7273 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7274 reg_val &= 0xffffff00;
7275 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7276
7277 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7278 reg_val &= 0x00ffffff;
7279 reg_val |= 0xb0000000;
7280 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7281 }
7282
7283 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7284 struct intel_link_m_n *m_n)
7285 {
7286 struct drm_device *dev = crtc->base.dev;
7287 struct drm_i915_private *dev_priv = dev->dev_private;
7288 int pipe = crtc->pipe;
7289
7290 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7291 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7292 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7293 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7294 }
7295
7296 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7297 struct intel_link_m_n *m_n,
7298 struct intel_link_m_n *m2_n2)
7299 {
7300 struct drm_device *dev = crtc->base.dev;
7301 struct drm_i915_private *dev_priv = dev->dev_private;
7302 int pipe = crtc->pipe;
7303 enum transcoder transcoder = crtc->config->cpu_transcoder;
7304
7305 if (INTEL_INFO(dev)->gen >= 5) {
7306 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7307 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7308 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7309 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7310 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7311 * for gen < 8) and if DRRS is supported (to make sure the
7312 * registers are not unnecessarily accessed).
7313 */
7314 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7315 crtc->config->has_drrs) {
7316 I915_WRITE(PIPE_DATA_M2(transcoder),
7317 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7318 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7319 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7320 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7321 }
7322 } else {
7323 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7324 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7325 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7326 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7327 }
7328 }
7329
7330 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7331 {
7332 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7333
7334 if (m_n == M1_N1) {
7335 dp_m_n = &crtc->config->dp_m_n;
7336 dp_m2_n2 = &crtc->config->dp_m2_n2;
7337 } else if (m_n == M2_N2) {
7338
7339 /*
7340 * M2_N2 registers are not supported. Hence m2_n2 divider value
7341 * needs to be programmed into M1_N1.
7342 */
7343 dp_m_n = &crtc->config->dp_m2_n2;
7344 } else {
7345 DRM_ERROR("Unsupported divider value\n");
7346 return;
7347 }
7348
7349 if (crtc->config->has_pch_encoder)
7350 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7351 else
7352 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7353 }
7354
7355 static void vlv_compute_dpll(struct intel_crtc *crtc,
7356 struct intel_crtc_state *pipe_config)
7357 {
7358 u32 dpll, dpll_md;
7359
7360 /*
7361 * Enable DPIO clock input. We should never disable the reference
7362 * clock for pipe B, since VGA hotplug / manual detection depends
7363 * on it.
7364 */
7365 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7366 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7367 /* We should never disable this, set it here for state tracking */
7368 if (crtc->pipe == PIPE_B)
7369 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7370 dpll |= DPLL_VCO_ENABLE;
7371 pipe_config->dpll_hw_state.dpll = dpll;
7372
7373 dpll_md = (pipe_config->pixel_multiplier - 1)
7374 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7375 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7376 }
7377
7378 static void vlv_prepare_pll(struct intel_crtc *crtc,
7379 const struct intel_crtc_state *pipe_config)
7380 {
7381 struct drm_device *dev = crtc->base.dev;
7382 struct drm_i915_private *dev_priv = dev->dev_private;
7383 int pipe = crtc->pipe;
7384 u32 mdiv;
7385 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7386 u32 coreclk, reg_val;
7387
7388 mutex_lock(&dev_priv->sb_lock);
7389
7390 bestn = pipe_config->dpll.n;
7391 bestm1 = pipe_config->dpll.m1;
7392 bestm2 = pipe_config->dpll.m2;
7393 bestp1 = pipe_config->dpll.p1;
7394 bestp2 = pipe_config->dpll.p2;
7395
7396 /* See eDP HDMI DPIO driver vbios notes doc */
7397
7398 /* PLL B needs special handling */
7399 if (pipe == PIPE_B)
7400 vlv_pllb_recal_opamp(dev_priv, pipe);
7401
7402 /* Set up Tx target for periodic Rcomp update */
7403 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7404
7405 /* Disable target IRef on PLL */
7406 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7407 reg_val &= 0x00ffffff;
7408 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7409
7410 /* Disable fast lock */
7411 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7412
7413 /* Set idtafcrecal before PLL is enabled */
7414 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7415 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7416 mdiv |= ((bestn << DPIO_N_SHIFT));
7417 mdiv |= (1 << DPIO_K_SHIFT);
7418
7419 /*
7420 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7421 * but we don't support that).
7422 * Note: don't use the DAC post divider as it seems unstable.
7423 */
7424 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7425 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7426
7427 mdiv |= DPIO_ENABLE_CALIBRATION;
7428 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7429
7430 /* Set HBR and RBR LPF coefficients */
7431 if (pipe_config->port_clock == 162000 ||
7432 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7433 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7434 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7435 0x009f0003);
7436 else
7437 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7438 0x00d0000f);
7439
7440 if (pipe_config->has_dp_encoder) {
7441 /* Use SSC source */
7442 if (pipe == PIPE_A)
7443 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7444 0x0df40000);
7445 else
7446 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7447 0x0df70000);
7448 } else { /* HDMI or VGA */
7449 /* Use bend source */
7450 if (pipe == PIPE_A)
7451 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7452 0x0df70000);
7453 else
7454 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7455 0x0df40000);
7456 }
7457
7458 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7459 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7460 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7461 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7462 coreclk |= 0x01000000;
7463 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7464
7465 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7466 mutex_unlock(&dev_priv->sb_lock);
7467 }
7468
7469 static void chv_compute_dpll(struct intel_crtc *crtc,
7470 struct intel_crtc_state *pipe_config)
7471 {
7472 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7473 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7474 DPLL_VCO_ENABLE;
7475 if (crtc->pipe != PIPE_A)
7476 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7477
7478 pipe_config->dpll_hw_state.dpll_md =
7479 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7480 }
7481
7482 static void chv_prepare_pll(struct intel_crtc *crtc,
7483 const struct intel_crtc_state *pipe_config)
7484 {
7485 struct drm_device *dev = crtc->base.dev;
7486 struct drm_i915_private *dev_priv = dev->dev_private;
7487 int pipe = crtc->pipe;
7488 i915_reg_t dpll_reg = DPLL(crtc->pipe);
7489 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7490 u32 loopfilter, tribuf_calcntr;
7491 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7492 u32 dpio_val;
7493 int vco;
7494
7495 bestn = pipe_config->dpll.n;
7496 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7497 bestm1 = pipe_config->dpll.m1;
7498 bestm2 = pipe_config->dpll.m2 >> 22;
7499 bestp1 = pipe_config->dpll.p1;
7500 bestp2 = pipe_config->dpll.p2;
7501 vco = pipe_config->dpll.vco;
7502 dpio_val = 0;
7503 loopfilter = 0;
7504
7505 /*
7506 * Enable Refclk and SSC
7507 */
7508 I915_WRITE(dpll_reg,
7509 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7510
7511 mutex_lock(&dev_priv->sb_lock);
7512
7513 /* p1 and p2 divider */
7514 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7515 5 << DPIO_CHV_S1_DIV_SHIFT |
7516 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7517 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7518 1 << DPIO_CHV_K_DIV_SHIFT);
7519
7520 /* Feedback post-divider - m2 */
7521 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7522
7523 /* Feedback refclk divider - n and m1 */
7524 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7525 DPIO_CHV_M1_DIV_BY_2 |
7526 1 << DPIO_CHV_N_DIV_SHIFT);
7527
7528 /* M2 fraction division */
7529 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7530
7531 /* M2 fraction division enable */
7532 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7533 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7534 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7535 if (bestm2_frac)
7536 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7537 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7538
7539 /* Program digital lock detect threshold */
7540 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7541 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7542 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7543 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7544 if (!bestm2_frac)
7545 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7546 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7547
7548 /* Loop filter */
7549 if (vco == 5400000) {
7550 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7551 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7552 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7553 tribuf_calcntr = 0x9;
7554 } else if (vco <= 6200000) {
7555 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7556 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7557 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7558 tribuf_calcntr = 0x9;
7559 } else if (vco <= 6480000) {
7560 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7561 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7562 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7563 tribuf_calcntr = 0x8;
7564 } else {
7565 /* Not supported. Apply the same limits as in the max case */
7566 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7567 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7568 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7569 tribuf_calcntr = 0;
7570 }
7571 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7572
7573 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7574 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7575 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7576 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7577
7578 /* AFC Recal */
7579 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7580 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7581 DPIO_AFC_RECAL);
7582
7583 mutex_unlock(&dev_priv->sb_lock);
7584 }
7585
7586 /**
7587 * vlv_force_pll_on - forcibly enable just the PLL
7588 * @dev_priv: i915 private structure
7589 * @pipe: pipe PLL to enable
7590 * @dpll: PLL configuration
7591 *
7592 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7593 * in cases where we need the PLL enabled even when @pipe is not going to
7594 * be enabled.
7595 */
7596 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7597 const struct dpll *dpll)
7598 {
7599 struct intel_crtc *crtc =
7600 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7601 struct intel_crtc_state pipe_config = {
7602 .base.crtc = &crtc->base,
7603 .pixel_multiplier = 1,
7604 .dpll = *dpll,
7605 };
7606
7607 if (IS_CHERRYVIEW(dev)) {
7608 chv_compute_dpll(crtc, &pipe_config);
7609 chv_prepare_pll(crtc, &pipe_config);
7610 chv_enable_pll(crtc, &pipe_config);
7611 } else {
7612 vlv_compute_dpll(crtc, &pipe_config);
7613 vlv_prepare_pll(crtc, &pipe_config);
7614 vlv_enable_pll(crtc, &pipe_config);
7615 }
7616 }
7617
7618 /**
7619 * vlv_force_pll_off - forcibly disable just the PLL
7620 * @dev_priv: i915 private structure
7621 * @pipe: pipe PLL to disable
7622 *
7623 * Disable the PLL for @pipe. To be used in cases where we need
7624 * the PLL enabled even when @pipe is not going to be enabled.
7625 */
7626 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7627 {
7628 if (IS_CHERRYVIEW(dev))
7629 chv_disable_pll(to_i915(dev), pipe);
7630 else
7631 vlv_disable_pll(to_i915(dev), pipe);
7632 }
7633
7634 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7635 struct intel_crtc_state *crtc_state,
7636 intel_clock_t *reduced_clock,
7637 int num_connectors)
7638 {
7639 struct drm_device *dev = crtc->base.dev;
7640 struct drm_i915_private *dev_priv = dev->dev_private;
7641 u32 dpll;
7642 bool is_sdvo;
7643 struct dpll *clock = &crtc_state->dpll;
7644
7645 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7646
7647 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7648 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7649
7650 dpll = DPLL_VGA_MODE_DIS;
7651
7652 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7653 dpll |= DPLLB_MODE_LVDS;
7654 else
7655 dpll |= DPLLB_MODE_DAC_SERIAL;
7656
7657 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7658 dpll |= (crtc_state->pixel_multiplier - 1)
7659 << SDVO_MULTIPLIER_SHIFT_HIRES;
7660 }
7661
7662 if (is_sdvo)
7663 dpll |= DPLL_SDVO_HIGH_SPEED;
7664
7665 if (crtc_state->has_dp_encoder)
7666 dpll |= DPLL_SDVO_HIGH_SPEED;
7667
7668 /* compute bitmask from p1 value */
7669 if (IS_PINEVIEW(dev))
7670 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7671 else {
7672 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7673 if (IS_G4X(dev) && reduced_clock)
7674 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7675 }
7676 switch (clock->p2) {
7677 case 5:
7678 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7679 break;
7680 case 7:
7681 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7682 break;
7683 case 10:
7684 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7685 break;
7686 case 14:
7687 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7688 break;
7689 }
7690 if (INTEL_INFO(dev)->gen >= 4)
7691 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7692
7693 if (crtc_state->sdvo_tv_clock)
7694 dpll |= PLL_REF_INPUT_TVCLKINBC;
7695 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7696 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7697 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7698 else
7699 dpll |= PLL_REF_INPUT_DREFCLK;
7700
7701 dpll |= DPLL_VCO_ENABLE;
7702 crtc_state->dpll_hw_state.dpll = dpll;
7703
7704 if (INTEL_INFO(dev)->gen >= 4) {
7705 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7706 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7707 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7708 }
7709 }
7710
7711 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7712 struct intel_crtc_state *crtc_state,
7713 intel_clock_t *reduced_clock,
7714 int num_connectors)
7715 {
7716 struct drm_device *dev = crtc->base.dev;
7717 struct drm_i915_private *dev_priv = dev->dev_private;
7718 u32 dpll;
7719 struct dpll *clock = &crtc_state->dpll;
7720
7721 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7722
7723 dpll = DPLL_VGA_MODE_DIS;
7724
7725 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7726 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7727 } else {
7728 if (clock->p1 == 2)
7729 dpll |= PLL_P1_DIVIDE_BY_TWO;
7730 else
7731 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7732 if (clock->p2 == 4)
7733 dpll |= PLL_P2_DIVIDE_BY_4;
7734 }
7735
7736 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7737 dpll |= DPLL_DVO_2X_MODE;
7738
7739 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7740 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7741 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7742 else
7743 dpll |= PLL_REF_INPUT_DREFCLK;
7744
7745 dpll |= DPLL_VCO_ENABLE;
7746 crtc_state->dpll_hw_state.dpll = dpll;
7747 }
7748
7749 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7750 {
7751 struct drm_device *dev = intel_crtc->base.dev;
7752 struct drm_i915_private *dev_priv = dev->dev_private;
7753 enum pipe pipe = intel_crtc->pipe;
7754 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7755 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7756 uint32_t crtc_vtotal, crtc_vblank_end;
7757 int vsyncshift = 0;
7758
7759 /* We need to be careful not to changed the adjusted mode, for otherwise
7760 * the hw state checker will get angry at the mismatch. */
7761 crtc_vtotal = adjusted_mode->crtc_vtotal;
7762 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7763
7764 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7765 /* the chip adds 2 halflines automatically */
7766 crtc_vtotal -= 1;
7767 crtc_vblank_end -= 1;
7768
7769 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7770 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7771 else
7772 vsyncshift = adjusted_mode->crtc_hsync_start -
7773 adjusted_mode->crtc_htotal / 2;
7774 if (vsyncshift < 0)
7775 vsyncshift += adjusted_mode->crtc_htotal;
7776 }
7777
7778 if (INTEL_INFO(dev)->gen > 3)
7779 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7780
7781 I915_WRITE(HTOTAL(cpu_transcoder),
7782 (adjusted_mode->crtc_hdisplay - 1) |
7783 ((adjusted_mode->crtc_htotal - 1) << 16));
7784 I915_WRITE(HBLANK(cpu_transcoder),
7785 (adjusted_mode->crtc_hblank_start - 1) |
7786 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7787 I915_WRITE(HSYNC(cpu_transcoder),
7788 (adjusted_mode->crtc_hsync_start - 1) |
7789 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7790
7791 I915_WRITE(VTOTAL(cpu_transcoder),
7792 (adjusted_mode->crtc_vdisplay - 1) |
7793 ((crtc_vtotal - 1) << 16));
7794 I915_WRITE(VBLANK(cpu_transcoder),
7795 (adjusted_mode->crtc_vblank_start - 1) |
7796 ((crtc_vblank_end - 1) << 16));
7797 I915_WRITE(VSYNC(cpu_transcoder),
7798 (adjusted_mode->crtc_vsync_start - 1) |
7799 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7800
7801 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7802 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7803 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7804 * bits. */
7805 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7806 (pipe == PIPE_B || pipe == PIPE_C))
7807 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7808
7809 /* pipesrc controls the size that is scaled from, which should
7810 * always be the user's requested size.
7811 */
7812 I915_WRITE(PIPESRC(pipe),
7813 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7814 (intel_crtc->config->pipe_src_h - 1));
7815 }
7816
7817 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7818 struct intel_crtc_state *pipe_config)
7819 {
7820 struct drm_device *dev = crtc->base.dev;
7821 struct drm_i915_private *dev_priv = dev->dev_private;
7822 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7823 uint32_t tmp;
7824
7825 tmp = I915_READ(HTOTAL(cpu_transcoder));
7826 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7827 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7828 tmp = I915_READ(HBLANK(cpu_transcoder));
7829 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7830 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7831 tmp = I915_READ(HSYNC(cpu_transcoder));
7832 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7833 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7834
7835 tmp = I915_READ(VTOTAL(cpu_transcoder));
7836 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7837 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7838 tmp = I915_READ(VBLANK(cpu_transcoder));
7839 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7840 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7841 tmp = I915_READ(VSYNC(cpu_transcoder));
7842 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7843 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7844
7845 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7846 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7847 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7848 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7849 }
7850
7851 tmp = I915_READ(PIPESRC(crtc->pipe));
7852 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7853 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7854
7855 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7856 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7857 }
7858
7859 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7860 struct intel_crtc_state *pipe_config)
7861 {
7862 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7863 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7864 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7865 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7866
7867 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7868 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7869 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7870 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7871
7872 mode->flags = pipe_config->base.adjusted_mode.flags;
7873 mode->type = DRM_MODE_TYPE_DRIVER;
7874
7875 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7876 mode->flags |= pipe_config->base.adjusted_mode.flags;
7877
7878 mode->hsync = drm_mode_hsync(mode);
7879 mode->vrefresh = drm_mode_vrefresh(mode);
7880 drm_mode_set_name(mode);
7881 }
7882
7883 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7884 {
7885 struct drm_device *dev = intel_crtc->base.dev;
7886 struct drm_i915_private *dev_priv = dev->dev_private;
7887 uint32_t pipeconf;
7888
7889 pipeconf = 0;
7890
7891 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7892 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7893 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7894
7895 if (intel_crtc->config->double_wide)
7896 pipeconf |= PIPECONF_DOUBLE_WIDE;
7897
7898 /* only g4x and later have fancy bpc/dither controls */
7899 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7900 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7901 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7902 pipeconf |= PIPECONF_DITHER_EN |
7903 PIPECONF_DITHER_TYPE_SP;
7904
7905 switch (intel_crtc->config->pipe_bpp) {
7906 case 18:
7907 pipeconf |= PIPECONF_6BPC;
7908 break;
7909 case 24:
7910 pipeconf |= PIPECONF_8BPC;
7911 break;
7912 case 30:
7913 pipeconf |= PIPECONF_10BPC;
7914 break;
7915 default:
7916 /* Case prevented by intel_choose_pipe_bpp_dither. */
7917 BUG();
7918 }
7919 }
7920
7921 if (HAS_PIPE_CXSR(dev)) {
7922 if (intel_crtc->lowfreq_avail) {
7923 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7924 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7925 } else {
7926 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7927 }
7928 }
7929
7930 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7931 if (INTEL_INFO(dev)->gen < 4 ||
7932 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7933 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7934 else
7935 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7936 } else
7937 pipeconf |= PIPECONF_PROGRESSIVE;
7938
7939 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7940 intel_crtc->config->limited_color_range)
7941 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7942
7943 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7944 POSTING_READ(PIPECONF(intel_crtc->pipe));
7945 }
7946
7947 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7948 struct intel_crtc_state *crtc_state)
7949 {
7950 struct drm_device *dev = crtc->base.dev;
7951 struct drm_i915_private *dev_priv = dev->dev_private;
7952 int refclk, num_connectors = 0;
7953 intel_clock_t clock;
7954 bool ok;
7955 const intel_limit_t *limit;
7956 struct drm_atomic_state *state = crtc_state->base.state;
7957 struct drm_connector *connector;
7958 struct drm_connector_state *connector_state;
7959 int i;
7960
7961 memset(&crtc_state->dpll_hw_state, 0,
7962 sizeof(crtc_state->dpll_hw_state));
7963
7964 if (crtc_state->has_dsi_encoder)
7965 return 0;
7966
7967 for_each_connector_in_state(state, connector, connector_state, i) {
7968 if (connector_state->crtc == &crtc->base)
7969 num_connectors++;
7970 }
7971
7972 if (!crtc_state->clock_set) {
7973 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7974
7975 /*
7976 * Returns a set of divisors for the desired target clock with
7977 * the given refclk, or FALSE. The returned values represent
7978 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7979 * 2) / p1 / p2.
7980 */
7981 limit = intel_limit(crtc_state, refclk);
7982 ok = dev_priv->display.find_dpll(limit, crtc_state,
7983 crtc_state->port_clock,
7984 refclk, NULL, &clock);
7985 if (!ok) {
7986 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7987 return -EINVAL;
7988 }
7989
7990 /* Compat-code for transition, will disappear. */
7991 crtc_state->dpll.n = clock.n;
7992 crtc_state->dpll.m1 = clock.m1;
7993 crtc_state->dpll.m2 = clock.m2;
7994 crtc_state->dpll.p1 = clock.p1;
7995 crtc_state->dpll.p2 = clock.p2;
7996 }
7997
7998 if (IS_GEN2(dev)) {
7999 i8xx_compute_dpll(crtc, crtc_state, NULL,
8000 num_connectors);
8001 } else if (IS_CHERRYVIEW(dev)) {
8002 chv_compute_dpll(crtc, crtc_state);
8003 } else if (IS_VALLEYVIEW(dev)) {
8004 vlv_compute_dpll(crtc, crtc_state);
8005 } else {
8006 i9xx_compute_dpll(crtc, crtc_state, NULL,
8007 num_connectors);
8008 }
8009
8010 return 0;
8011 }
8012
8013 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8014 struct intel_crtc_state *pipe_config)
8015 {
8016 struct drm_device *dev = crtc->base.dev;
8017 struct drm_i915_private *dev_priv = dev->dev_private;
8018 uint32_t tmp;
8019
8020 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8021 return;
8022
8023 tmp = I915_READ(PFIT_CONTROL);
8024 if (!(tmp & PFIT_ENABLE))
8025 return;
8026
8027 /* Check whether the pfit is attached to our pipe. */
8028 if (INTEL_INFO(dev)->gen < 4) {
8029 if (crtc->pipe != PIPE_B)
8030 return;
8031 } else {
8032 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8033 return;
8034 }
8035
8036 pipe_config->gmch_pfit.control = tmp;
8037 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8038 if (INTEL_INFO(dev)->gen < 5)
8039 pipe_config->gmch_pfit.lvds_border_bits =
8040 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
8041 }
8042
8043 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8044 struct intel_crtc_state *pipe_config)
8045 {
8046 struct drm_device *dev = crtc->base.dev;
8047 struct drm_i915_private *dev_priv = dev->dev_private;
8048 int pipe = pipe_config->cpu_transcoder;
8049 intel_clock_t clock;
8050 u32 mdiv;
8051 int refclk = 100000;
8052
8053 /* In case of MIPI DPLL will not even be used */
8054 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8055 return;
8056
8057 mutex_lock(&dev_priv->sb_lock);
8058 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8059 mutex_unlock(&dev_priv->sb_lock);
8060
8061 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8062 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8063 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8064 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8065 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8066
8067 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8068 }
8069
8070 static void
8071 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8072 struct intel_initial_plane_config *plane_config)
8073 {
8074 struct drm_device *dev = crtc->base.dev;
8075 struct drm_i915_private *dev_priv = dev->dev_private;
8076 u32 val, base, offset;
8077 int pipe = crtc->pipe, plane = crtc->plane;
8078 int fourcc, pixel_format;
8079 unsigned int aligned_height;
8080 struct drm_framebuffer *fb;
8081 struct intel_framebuffer *intel_fb;
8082
8083 val = I915_READ(DSPCNTR(plane));
8084 if (!(val & DISPLAY_PLANE_ENABLE))
8085 return;
8086
8087 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8088 if (!intel_fb) {
8089 DRM_DEBUG_KMS("failed to alloc fb\n");
8090 return;
8091 }
8092
8093 fb = &intel_fb->base;
8094
8095 if (INTEL_INFO(dev)->gen >= 4) {
8096 if (val & DISPPLANE_TILED) {
8097 plane_config->tiling = I915_TILING_X;
8098 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8099 }
8100 }
8101
8102 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8103 fourcc = i9xx_format_to_fourcc(pixel_format);
8104 fb->pixel_format = fourcc;
8105 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8106
8107 if (INTEL_INFO(dev)->gen >= 4) {
8108 if (plane_config->tiling)
8109 offset = I915_READ(DSPTILEOFF(plane));
8110 else
8111 offset = I915_READ(DSPLINOFF(plane));
8112 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8113 } else {
8114 base = I915_READ(DSPADDR(plane));
8115 }
8116 plane_config->base = base;
8117
8118 val = I915_READ(PIPESRC(pipe));
8119 fb->width = ((val >> 16) & 0xfff) + 1;
8120 fb->height = ((val >> 0) & 0xfff) + 1;
8121
8122 val = I915_READ(DSPSTRIDE(pipe));
8123 fb->pitches[0] = val & 0xffffffc0;
8124
8125 aligned_height = intel_fb_align_height(dev, fb->height,
8126 fb->pixel_format,
8127 fb->modifier[0]);
8128
8129 plane_config->size = fb->pitches[0] * aligned_height;
8130
8131 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8132 pipe_name(pipe), plane, fb->width, fb->height,
8133 fb->bits_per_pixel, base, fb->pitches[0],
8134 plane_config->size);
8135
8136 plane_config->fb = intel_fb;
8137 }
8138
8139 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8140 struct intel_crtc_state *pipe_config)
8141 {
8142 struct drm_device *dev = crtc->base.dev;
8143 struct drm_i915_private *dev_priv = dev->dev_private;
8144 int pipe = pipe_config->cpu_transcoder;
8145 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8146 intel_clock_t clock;
8147 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8148 int refclk = 100000;
8149
8150 mutex_lock(&dev_priv->sb_lock);
8151 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8152 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8153 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8154 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8155 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8156 mutex_unlock(&dev_priv->sb_lock);
8157
8158 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8159 clock.m2 = (pll_dw0 & 0xff) << 22;
8160 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8161 clock.m2 |= pll_dw2 & 0x3fffff;
8162 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8163 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8164 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8165
8166 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8167 }
8168
8169 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8170 struct intel_crtc_state *pipe_config)
8171 {
8172 struct drm_device *dev = crtc->base.dev;
8173 struct drm_i915_private *dev_priv = dev->dev_private;
8174 uint32_t tmp;
8175
8176 if (!intel_display_power_is_enabled(dev_priv,
8177 POWER_DOMAIN_PIPE(crtc->pipe)))
8178 return false;
8179
8180 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8181 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8182
8183 tmp = I915_READ(PIPECONF(crtc->pipe));
8184 if (!(tmp & PIPECONF_ENABLE))
8185 return false;
8186
8187 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8188 switch (tmp & PIPECONF_BPC_MASK) {
8189 case PIPECONF_6BPC:
8190 pipe_config->pipe_bpp = 18;
8191 break;
8192 case PIPECONF_8BPC:
8193 pipe_config->pipe_bpp = 24;
8194 break;
8195 case PIPECONF_10BPC:
8196 pipe_config->pipe_bpp = 30;
8197 break;
8198 default:
8199 break;
8200 }
8201 }
8202
8203 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8204 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8205 pipe_config->limited_color_range = true;
8206
8207 if (INTEL_INFO(dev)->gen < 4)
8208 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8209
8210 intel_get_pipe_timings(crtc, pipe_config);
8211
8212 i9xx_get_pfit_config(crtc, pipe_config);
8213
8214 if (INTEL_INFO(dev)->gen >= 4) {
8215 tmp = I915_READ(DPLL_MD(crtc->pipe));
8216 pipe_config->pixel_multiplier =
8217 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8218 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8219 pipe_config->dpll_hw_state.dpll_md = tmp;
8220 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8221 tmp = I915_READ(DPLL(crtc->pipe));
8222 pipe_config->pixel_multiplier =
8223 ((tmp & SDVO_MULTIPLIER_MASK)
8224 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8225 } else {
8226 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8227 * port and will be fixed up in the encoder->get_config
8228 * function. */
8229 pipe_config->pixel_multiplier = 1;
8230 }
8231 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8232 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8233 /*
8234 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8235 * on 830. Filter it out here so that we don't
8236 * report errors due to that.
8237 */
8238 if (IS_I830(dev))
8239 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8240
8241 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8242 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8243 } else {
8244 /* Mask out read-only status bits. */
8245 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8246 DPLL_PORTC_READY_MASK |
8247 DPLL_PORTB_READY_MASK);
8248 }
8249
8250 if (IS_CHERRYVIEW(dev))
8251 chv_crtc_clock_get(crtc, pipe_config);
8252 else if (IS_VALLEYVIEW(dev))
8253 vlv_crtc_clock_get(crtc, pipe_config);
8254 else
8255 i9xx_crtc_clock_get(crtc, pipe_config);
8256
8257 /*
8258 * Normally the dotclock is filled in by the encoder .get_config()
8259 * but in case the pipe is enabled w/o any ports we need a sane
8260 * default.
8261 */
8262 pipe_config->base.adjusted_mode.crtc_clock =
8263 pipe_config->port_clock / pipe_config->pixel_multiplier;
8264
8265 return true;
8266 }
8267
8268 static void ironlake_init_pch_refclk(struct drm_device *dev)
8269 {
8270 struct drm_i915_private *dev_priv = dev->dev_private;
8271 struct intel_encoder *encoder;
8272 u32 val, final;
8273 bool has_lvds = false;
8274 bool has_cpu_edp = false;
8275 bool has_panel = false;
8276 bool has_ck505 = false;
8277 bool can_ssc = false;
8278
8279 /* We need to take the global config into account */
8280 for_each_intel_encoder(dev, encoder) {
8281 switch (encoder->type) {
8282 case INTEL_OUTPUT_LVDS:
8283 has_panel = true;
8284 has_lvds = true;
8285 break;
8286 case INTEL_OUTPUT_EDP:
8287 has_panel = true;
8288 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8289 has_cpu_edp = true;
8290 break;
8291 default:
8292 break;
8293 }
8294 }
8295
8296 if (HAS_PCH_IBX(dev)) {
8297 has_ck505 = dev_priv->vbt.display_clock_mode;
8298 can_ssc = has_ck505;
8299 } else {
8300 has_ck505 = false;
8301 can_ssc = true;
8302 }
8303
8304 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8305 has_panel, has_lvds, has_ck505);
8306
8307 /* Ironlake: try to setup display ref clock before DPLL
8308 * enabling. This is only under driver's control after
8309 * PCH B stepping, previous chipset stepping should be
8310 * ignoring this setting.
8311 */
8312 val = I915_READ(PCH_DREF_CONTROL);
8313
8314 /* As we must carefully and slowly disable/enable each source in turn,
8315 * compute the final state we want first and check if we need to
8316 * make any changes at all.
8317 */
8318 final = val;
8319 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8320 if (has_ck505)
8321 final |= DREF_NONSPREAD_CK505_ENABLE;
8322 else
8323 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8324
8325 final &= ~DREF_SSC_SOURCE_MASK;
8326 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8327 final &= ~DREF_SSC1_ENABLE;
8328
8329 if (has_panel) {
8330 final |= DREF_SSC_SOURCE_ENABLE;
8331
8332 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8333 final |= DREF_SSC1_ENABLE;
8334
8335 if (has_cpu_edp) {
8336 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8337 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8338 else
8339 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8340 } else
8341 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8342 } else {
8343 final |= DREF_SSC_SOURCE_DISABLE;
8344 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8345 }
8346
8347 if (final == val)
8348 return;
8349
8350 /* Always enable nonspread source */
8351 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8352
8353 if (has_ck505)
8354 val |= DREF_NONSPREAD_CK505_ENABLE;
8355 else
8356 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8357
8358 if (has_panel) {
8359 val &= ~DREF_SSC_SOURCE_MASK;
8360 val |= DREF_SSC_SOURCE_ENABLE;
8361
8362 /* SSC must be turned on before enabling the CPU output */
8363 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8364 DRM_DEBUG_KMS("Using SSC on panel\n");
8365 val |= DREF_SSC1_ENABLE;
8366 } else
8367 val &= ~DREF_SSC1_ENABLE;
8368
8369 /* Get SSC going before enabling the outputs */
8370 I915_WRITE(PCH_DREF_CONTROL, val);
8371 POSTING_READ(PCH_DREF_CONTROL);
8372 udelay(200);
8373
8374 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8375
8376 /* Enable CPU source on CPU attached eDP */
8377 if (has_cpu_edp) {
8378 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8379 DRM_DEBUG_KMS("Using SSC on eDP\n");
8380 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8381 } else
8382 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8383 } else
8384 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8385
8386 I915_WRITE(PCH_DREF_CONTROL, val);
8387 POSTING_READ(PCH_DREF_CONTROL);
8388 udelay(200);
8389 } else {
8390 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8391
8392 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8393
8394 /* Turn off CPU output */
8395 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8396
8397 I915_WRITE(PCH_DREF_CONTROL, val);
8398 POSTING_READ(PCH_DREF_CONTROL);
8399 udelay(200);
8400
8401 /* Turn off the SSC source */
8402 val &= ~DREF_SSC_SOURCE_MASK;
8403 val |= DREF_SSC_SOURCE_DISABLE;
8404
8405 /* Turn off SSC1 */
8406 val &= ~DREF_SSC1_ENABLE;
8407
8408 I915_WRITE(PCH_DREF_CONTROL, val);
8409 POSTING_READ(PCH_DREF_CONTROL);
8410 udelay(200);
8411 }
8412
8413 BUG_ON(val != final);
8414 }
8415
8416 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8417 {
8418 uint32_t tmp;
8419
8420 tmp = I915_READ(SOUTH_CHICKEN2);
8421 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8422 I915_WRITE(SOUTH_CHICKEN2, tmp);
8423
8424 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8425 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8426 DRM_ERROR("FDI mPHY reset assert timeout\n");
8427
8428 tmp = I915_READ(SOUTH_CHICKEN2);
8429 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8430 I915_WRITE(SOUTH_CHICKEN2, tmp);
8431
8432 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8433 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8434 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8435 }
8436
8437 /* WaMPhyProgramming:hsw */
8438 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8439 {
8440 uint32_t tmp;
8441
8442 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8443 tmp &= ~(0xFF << 24);
8444 tmp |= (0x12 << 24);
8445 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8446
8447 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8448 tmp |= (1 << 11);
8449 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8450
8451 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8452 tmp |= (1 << 11);
8453 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8454
8455 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8456 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8457 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8458
8459 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8460 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8461 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8462
8463 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8464 tmp &= ~(7 << 13);
8465 tmp |= (5 << 13);
8466 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8467
8468 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8469 tmp &= ~(7 << 13);
8470 tmp |= (5 << 13);
8471 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8472
8473 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8474 tmp &= ~0xFF;
8475 tmp |= 0x1C;
8476 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8477
8478 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8479 tmp &= ~0xFF;
8480 tmp |= 0x1C;
8481 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8482
8483 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8484 tmp &= ~(0xFF << 16);
8485 tmp |= (0x1C << 16);
8486 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8487
8488 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8489 tmp &= ~(0xFF << 16);
8490 tmp |= (0x1C << 16);
8491 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8492
8493 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8494 tmp |= (1 << 27);
8495 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8496
8497 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8498 tmp |= (1 << 27);
8499 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8500
8501 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8502 tmp &= ~(0xF << 28);
8503 tmp |= (4 << 28);
8504 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8505
8506 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8507 tmp &= ~(0xF << 28);
8508 tmp |= (4 << 28);
8509 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8510 }
8511
8512 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8513 * Programming" based on the parameters passed:
8514 * - Sequence to enable CLKOUT_DP
8515 * - Sequence to enable CLKOUT_DP without spread
8516 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8517 */
8518 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8519 bool with_fdi)
8520 {
8521 struct drm_i915_private *dev_priv = dev->dev_private;
8522 uint32_t reg, tmp;
8523
8524 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8525 with_spread = true;
8526 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8527 with_fdi = false;
8528
8529 mutex_lock(&dev_priv->sb_lock);
8530
8531 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8532 tmp &= ~SBI_SSCCTL_DISABLE;
8533 tmp |= SBI_SSCCTL_PATHALT;
8534 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8535
8536 udelay(24);
8537
8538 if (with_spread) {
8539 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8540 tmp &= ~SBI_SSCCTL_PATHALT;
8541 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8542
8543 if (with_fdi) {
8544 lpt_reset_fdi_mphy(dev_priv);
8545 lpt_program_fdi_mphy(dev_priv);
8546 }
8547 }
8548
8549 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8550 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8551 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8552 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8553
8554 mutex_unlock(&dev_priv->sb_lock);
8555 }
8556
8557 /* Sequence to disable CLKOUT_DP */
8558 static void lpt_disable_clkout_dp(struct drm_device *dev)
8559 {
8560 struct drm_i915_private *dev_priv = dev->dev_private;
8561 uint32_t reg, tmp;
8562
8563 mutex_lock(&dev_priv->sb_lock);
8564
8565 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8566 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8567 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8568 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8569
8570 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8571 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8572 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8573 tmp |= SBI_SSCCTL_PATHALT;
8574 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8575 udelay(32);
8576 }
8577 tmp |= SBI_SSCCTL_DISABLE;
8578 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8579 }
8580
8581 mutex_unlock(&dev_priv->sb_lock);
8582 }
8583
8584 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8585
8586 static const uint16_t sscdivintphase[] = {
8587 [BEND_IDX( 50)] = 0x3B23,
8588 [BEND_IDX( 45)] = 0x3B23,
8589 [BEND_IDX( 40)] = 0x3C23,
8590 [BEND_IDX( 35)] = 0x3C23,
8591 [BEND_IDX( 30)] = 0x3D23,
8592 [BEND_IDX( 25)] = 0x3D23,
8593 [BEND_IDX( 20)] = 0x3E23,
8594 [BEND_IDX( 15)] = 0x3E23,
8595 [BEND_IDX( 10)] = 0x3F23,
8596 [BEND_IDX( 5)] = 0x3F23,
8597 [BEND_IDX( 0)] = 0x0025,
8598 [BEND_IDX( -5)] = 0x0025,
8599 [BEND_IDX(-10)] = 0x0125,
8600 [BEND_IDX(-15)] = 0x0125,
8601 [BEND_IDX(-20)] = 0x0225,
8602 [BEND_IDX(-25)] = 0x0225,
8603 [BEND_IDX(-30)] = 0x0325,
8604 [BEND_IDX(-35)] = 0x0325,
8605 [BEND_IDX(-40)] = 0x0425,
8606 [BEND_IDX(-45)] = 0x0425,
8607 [BEND_IDX(-50)] = 0x0525,
8608 };
8609
8610 /*
8611 * Bend CLKOUT_DP
8612 * steps -50 to 50 inclusive, in steps of 5
8613 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8614 * change in clock period = -(steps / 10) * 5.787 ps
8615 */
8616 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8617 {
8618 uint32_t tmp;
8619 int idx = BEND_IDX(steps);
8620
8621 if (WARN_ON(steps % 5 != 0))
8622 return;
8623
8624 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8625 return;
8626
8627 mutex_lock(&dev_priv->sb_lock);
8628
8629 if (steps % 10 != 0)
8630 tmp = 0xAAAAAAAB;
8631 else
8632 tmp = 0x00000000;
8633 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8634
8635 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8636 tmp &= 0xffff0000;
8637 tmp |= sscdivintphase[idx];
8638 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8639
8640 mutex_unlock(&dev_priv->sb_lock);
8641 }
8642
8643 #undef BEND_IDX
8644
8645 static void lpt_init_pch_refclk(struct drm_device *dev)
8646 {
8647 struct intel_encoder *encoder;
8648 bool has_vga = false;
8649
8650 for_each_intel_encoder(dev, encoder) {
8651 switch (encoder->type) {
8652 case INTEL_OUTPUT_ANALOG:
8653 has_vga = true;
8654 break;
8655 default:
8656 break;
8657 }
8658 }
8659
8660 if (has_vga) {
8661 lpt_bend_clkout_dp(to_i915(dev), 0);
8662 lpt_enable_clkout_dp(dev, true, true);
8663 } else {
8664 lpt_disable_clkout_dp(dev);
8665 }
8666 }
8667
8668 /*
8669 * Initialize reference clocks when the driver loads
8670 */
8671 void intel_init_pch_refclk(struct drm_device *dev)
8672 {
8673 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8674 ironlake_init_pch_refclk(dev);
8675 else if (HAS_PCH_LPT(dev))
8676 lpt_init_pch_refclk(dev);
8677 }
8678
8679 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8680 {
8681 struct drm_device *dev = crtc_state->base.crtc->dev;
8682 struct drm_i915_private *dev_priv = dev->dev_private;
8683 struct drm_atomic_state *state = crtc_state->base.state;
8684 struct drm_connector *connector;
8685 struct drm_connector_state *connector_state;
8686 struct intel_encoder *encoder;
8687 int num_connectors = 0, i;
8688 bool is_lvds = false;
8689
8690 for_each_connector_in_state(state, connector, connector_state, i) {
8691 if (connector_state->crtc != crtc_state->base.crtc)
8692 continue;
8693
8694 encoder = to_intel_encoder(connector_state->best_encoder);
8695
8696 switch (encoder->type) {
8697 case INTEL_OUTPUT_LVDS:
8698 is_lvds = true;
8699 break;
8700 default:
8701 break;
8702 }
8703 num_connectors++;
8704 }
8705
8706 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8707 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8708 dev_priv->vbt.lvds_ssc_freq);
8709 return dev_priv->vbt.lvds_ssc_freq;
8710 }
8711
8712 return 120000;
8713 }
8714
8715 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8716 {
8717 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8718 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8719 int pipe = intel_crtc->pipe;
8720 uint32_t val;
8721
8722 val = 0;
8723
8724 switch (intel_crtc->config->pipe_bpp) {
8725 case 18:
8726 val |= PIPECONF_6BPC;
8727 break;
8728 case 24:
8729 val |= PIPECONF_8BPC;
8730 break;
8731 case 30:
8732 val |= PIPECONF_10BPC;
8733 break;
8734 case 36:
8735 val |= PIPECONF_12BPC;
8736 break;
8737 default:
8738 /* Case prevented by intel_choose_pipe_bpp_dither. */
8739 BUG();
8740 }
8741
8742 if (intel_crtc->config->dither)
8743 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8744
8745 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8746 val |= PIPECONF_INTERLACED_ILK;
8747 else
8748 val |= PIPECONF_PROGRESSIVE;
8749
8750 if (intel_crtc->config->limited_color_range)
8751 val |= PIPECONF_COLOR_RANGE_SELECT;
8752
8753 I915_WRITE(PIPECONF(pipe), val);
8754 POSTING_READ(PIPECONF(pipe));
8755 }
8756
8757 /*
8758 * Set up the pipe CSC unit.
8759 *
8760 * Currently only full range RGB to limited range RGB conversion
8761 * is supported, but eventually this should handle various
8762 * RGB<->YCbCr scenarios as well.
8763 */
8764 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8765 {
8766 struct drm_device *dev = crtc->dev;
8767 struct drm_i915_private *dev_priv = dev->dev_private;
8768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8769 int pipe = intel_crtc->pipe;
8770 uint16_t coeff = 0x7800; /* 1.0 */
8771
8772 /*
8773 * TODO: Check what kind of values actually come out of the pipe
8774 * with these coeff/postoff values and adjust to get the best
8775 * accuracy. Perhaps we even need to take the bpc value into
8776 * consideration.
8777 */
8778
8779 if (intel_crtc->config->limited_color_range)
8780 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8781
8782 /*
8783 * GY/GU and RY/RU should be the other way around according
8784 * to BSpec, but reality doesn't agree. Just set them up in
8785 * a way that results in the correct picture.
8786 */
8787 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8788 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8789
8790 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8791 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8792
8793 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8794 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8795
8796 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8797 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8798 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8799
8800 if (INTEL_INFO(dev)->gen > 6) {
8801 uint16_t postoff = 0;
8802
8803 if (intel_crtc->config->limited_color_range)
8804 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8805
8806 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8807 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8808 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8809
8810 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8811 } else {
8812 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8813
8814 if (intel_crtc->config->limited_color_range)
8815 mode |= CSC_BLACK_SCREEN_OFFSET;
8816
8817 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8818 }
8819 }
8820
8821 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8822 {
8823 struct drm_device *dev = crtc->dev;
8824 struct drm_i915_private *dev_priv = dev->dev_private;
8825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8826 enum pipe pipe = intel_crtc->pipe;
8827 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8828 uint32_t val;
8829
8830 val = 0;
8831
8832 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8833 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8834
8835 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8836 val |= PIPECONF_INTERLACED_ILK;
8837 else
8838 val |= PIPECONF_PROGRESSIVE;
8839
8840 I915_WRITE(PIPECONF(cpu_transcoder), val);
8841 POSTING_READ(PIPECONF(cpu_transcoder));
8842
8843 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8844 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8845
8846 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8847 val = 0;
8848
8849 switch (intel_crtc->config->pipe_bpp) {
8850 case 18:
8851 val |= PIPEMISC_DITHER_6_BPC;
8852 break;
8853 case 24:
8854 val |= PIPEMISC_DITHER_8_BPC;
8855 break;
8856 case 30:
8857 val |= PIPEMISC_DITHER_10_BPC;
8858 break;
8859 case 36:
8860 val |= PIPEMISC_DITHER_12_BPC;
8861 break;
8862 default:
8863 /* Case prevented by pipe_config_set_bpp. */
8864 BUG();
8865 }
8866
8867 if (intel_crtc->config->dither)
8868 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8869
8870 I915_WRITE(PIPEMISC(pipe), val);
8871 }
8872 }
8873
8874 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8875 struct intel_crtc_state *crtc_state,
8876 intel_clock_t *clock,
8877 bool *has_reduced_clock,
8878 intel_clock_t *reduced_clock)
8879 {
8880 struct drm_device *dev = crtc->dev;
8881 struct drm_i915_private *dev_priv = dev->dev_private;
8882 int refclk;
8883 const intel_limit_t *limit;
8884 bool ret;
8885
8886 refclk = ironlake_get_refclk(crtc_state);
8887
8888 /*
8889 * Returns a set of divisors for the desired target clock with the given
8890 * refclk, or FALSE. The returned values represent the clock equation:
8891 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8892 */
8893 limit = intel_limit(crtc_state, refclk);
8894 ret = dev_priv->display.find_dpll(limit, crtc_state,
8895 crtc_state->port_clock,
8896 refclk, NULL, clock);
8897 if (!ret)
8898 return false;
8899
8900 return true;
8901 }
8902
8903 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8904 {
8905 /*
8906 * Account for spread spectrum to avoid
8907 * oversubscribing the link. Max center spread
8908 * is 2.5%; use 5% for safety's sake.
8909 */
8910 u32 bps = target_clock * bpp * 21 / 20;
8911 return DIV_ROUND_UP(bps, link_bw * 8);
8912 }
8913
8914 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8915 {
8916 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8917 }
8918
8919 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8920 struct intel_crtc_state *crtc_state,
8921 u32 *fp,
8922 intel_clock_t *reduced_clock, u32 *fp2)
8923 {
8924 struct drm_crtc *crtc = &intel_crtc->base;
8925 struct drm_device *dev = crtc->dev;
8926 struct drm_i915_private *dev_priv = dev->dev_private;
8927 struct drm_atomic_state *state = crtc_state->base.state;
8928 struct drm_connector *connector;
8929 struct drm_connector_state *connector_state;
8930 struct intel_encoder *encoder;
8931 uint32_t dpll;
8932 int factor, num_connectors = 0, i;
8933 bool is_lvds = false, is_sdvo = false;
8934
8935 for_each_connector_in_state(state, connector, connector_state, i) {
8936 if (connector_state->crtc != crtc_state->base.crtc)
8937 continue;
8938
8939 encoder = to_intel_encoder(connector_state->best_encoder);
8940
8941 switch (encoder->type) {
8942 case INTEL_OUTPUT_LVDS:
8943 is_lvds = true;
8944 break;
8945 case INTEL_OUTPUT_SDVO:
8946 case INTEL_OUTPUT_HDMI:
8947 is_sdvo = true;
8948 break;
8949 default:
8950 break;
8951 }
8952
8953 num_connectors++;
8954 }
8955
8956 /* Enable autotuning of the PLL clock (if permissible) */
8957 factor = 21;
8958 if (is_lvds) {
8959 if ((intel_panel_use_ssc(dev_priv) &&
8960 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8961 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8962 factor = 25;
8963 } else if (crtc_state->sdvo_tv_clock)
8964 factor = 20;
8965
8966 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8967 *fp |= FP_CB_TUNE;
8968
8969 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8970 *fp2 |= FP_CB_TUNE;
8971
8972 dpll = 0;
8973
8974 if (is_lvds)
8975 dpll |= DPLLB_MODE_LVDS;
8976 else
8977 dpll |= DPLLB_MODE_DAC_SERIAL;
8978
8979 dpll |= (crtc_state->pixel_multiplier - 1)
8980 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8981
8982 if (is_sdvo)
8983 dpll |= DPLL_SDVO_HIGH_SPEED;
8984 if (crtc_state->has_dp_encoder)
8985 dpll |= DPLL_SDVO_HIGH_SPEED;
8986
8987 /* compute bitmask from p1 value */
8988 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8989 /* also FPA1 */
8990 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8991
8992 switch (crtc_state->dpll.p2) {
8993 case 5:
8994 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8995 break;
8996 case 7:
8997 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8998 break;
8999 case 10:
9000 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9001 break;
9002 case 14:
9003 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9004 break;
9005 }
9006
9007 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
9008 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9009 else
9010 dpll |= PLL_REF_INPUT_DREFCLK;
9011
9012 return dpll | DPLL_VCO_ENABLE;
9013 }
9014
9015 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9016 struct intel_crtc_state *crtc_state)
9017 {
9018 struct drm_device *dev = crtc->base.dev;
9019 intel_clock_t clock, reduced_clock;
9020 u32 dpll = 0, fp = 0, fp2 = 0;
9021 bool ok, has_reduced_clock = false;
9022 bool is_lvds = false;
9023 struct intel_shared_dpll *pll;
9024
9025 memset(&crtc_state->dpll_hw_state, 0,
9026 sizeof(crtc_state->dpll_hw_state));
9027
9028 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
9029
9030 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
9031 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
9032
9033 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
9034 &has_reduced_clock, &reduced_clock);
9035 if (!ok && !crtc_state->clock_set) {
9036 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9037 return -EINVAL;
9038 }
9039 /* Compat-code for transition, will disappear. */
9040 if (!crtc_state->clock_set) {
9041 crtc_state->dpll.n = clock.n;
9042 crtc_state->dpll.m1 = clock.m1;
9043 crtc_state->dpll.m2 = clock.m2;
9044 crtc_state->dpll.p1 = clock.p1;
9045 crtc_state->dpll.p2 = clock.p2;
9046 }
9047
9048 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9049 if (crtc_state->has_pch_encoder) {
9050 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9051 if (has_reduced_clock)
9052 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
9053
9054 dpll = ironlake_compute_dpll(crtc, crtc_state,
9055 &fp, &reduced_clock,
9056 has_reduced_clock ? &fp2 : NULL);
9057
9058 crtc_state->dpll_hw_state.dpll = dpll;
9059 crtc_state->dpll_hw_state.fp0 = fp;
9060 if (has_reduced_clock)
9061 crtc_state->dpll_hw_state.fp1 = fp2;
9062 else
9063 crtc_state->dpll_hw_state.fp1 = fp;
9064
9065 pll = intel_get_shared_dpll(crtc, crtc_state);
9066 if (pll == NULL) {
9067 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9068 pipe_name(crtc->pipe));
9069 return -EINVAL;
9070 }
9071 }
9072
9073 if (is_lvds && has_reduced_clock)
9074 crtc->lowfreq_avail = true;
9075 else
9076 crtc->lowfreq_avail = false;
9077
9078 return 0;
9079 }
9080
9081 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9082 struct intel_link_m_n *m_n)
9083 {
9084 struct drm_device *dev = crtc->base.dev;
9085 struct drm_i915_private *dev_priv = dev->dev_private;
9086 enum pipe pipe = crtc->pipe;
9087
9088 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9089 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9090 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9091 & ~TU_SIZE_MASK;
9092 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9093 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9094 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9095 }
9096
9097 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9098 enum transcoder transcoder,
9099 struct intel_link_m_n *m_n,
9100 struct intel_link_m_n *m2_n2)
9101 {
9102 struct drm_device *dev = crtc->base.dev;
9103 struct drm_i915_private *dev_priv = dev->dev_private;
9104 enum pipe pipe = crtc->pipe;
9105
9106 if (INTEL_INFO(dev)->gen >= 5) {
9107 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9108 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9109 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9110 & ~TU_SIZE_MASK;
9111 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9112 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9113 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9114 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9115 * gen < 8) and if DRRS is supported (to make sure the
9116 * registers are not unnecessarily read).
9117 */
9118 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9119 crtc->config->has_drrs) {
9120 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9121 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9122 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9123 & ~TU_SIZE_MASK;
9124 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9125 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9126 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9127 }
9128 } else {
9129 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9130 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9131 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9132 & ~TU_SIZE_MASK;
9133 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9134 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9135 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9136 }
9137 }
9138
9139 void intel_dp_get_m_n(struct intel_crtc *crtc,
9140 struct intel_crtc_state *pipe_config)
9141 {
9142 if (pipe_config->has_pch_encoder)
9143 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9144 else
9145 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9146 &pipe_config->dp_m_n,
9147 &pipe_config->dp_m2_n2);
9148 }
9149
9150 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9151 struct intel_crtc_state *pipe_config)
9152 {
9153 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9154 &pipe_config->fdi_m_n, NULL);
9155 }
9156
9157 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9158 struct intel_crtc_state *pipe_config)
9159 {
9160 struct drm_device *dev = crtc->base.dev;
9161 struct drm_i915_private *dev_priv = dev->dev_private;
9162 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9163 uint32_t ps_ctrl = 0;
9164 int id = -1;
9165 int i;
9166
9167 /* find scaler attached to this pipe */
9168 for (i = 0; i < crtc->num_scalers; i++) {
9169 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9170 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9171 id = i;
9172 pipe_config->pch_pfit.enabled = true;
9173 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9174 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9175 break;
9176 }
9177 }
9178
9179 scaler_state->scaler_id = id;
9180 if (id >= 0) {
9181 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9182 } else {
9183 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9184 }
9185 }
9186
9187 static void
9188 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9189 struct intel_initial_plane_config *plane_config)
9190 {
9191 struct drm_device *dev = crtc->base.dev;
9192 struct drm_i915_private *dev_priv = dev->dev_private;
9193 u32 val, base, offset, stride_mult, tiling;
9194 int pipe = crtc->pipe;
9195 int fourcc, pixel_format;
9196 unsigned int aligned_height;
9197 struct drm_framebuffer *fb;
9198 struct intel_framebuffer *intel_fb;
9199
9200 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9201 if (!intel_fb) {
9202 DRM_DEBUG_KMS("failed to alloc fb\n");
9203 return;
9204 }
9205
9206 fb = &intel_fb->base;
9207
9208 val = I915_READ(PLANE_CTL(pipe, 0));
9209 if (!(val & PLANE_CTL_ENABLE))
9210 goto error;
9211
9212 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9213 fourcc = skl_format_to_fourcc(pixel_format,
9214 val & PLANE_CTL_ORDER_RGBX,
9215 val & PLANE_CTL_ALPHA_MASK);
9216 fb->pixel_format = fourcc;
9217 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9218
9219 tiling = val & PLANE_CTL_TILED_MASK;
9220 switch (tiling) {
9221 case PLANE_CTL_TILED_LINEAR:
9222 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9223 break;
9224 case PLANE_CTL_TILED_X:
9225 plane_config->tiling = I915_TILING_X;
9226 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9227 break;
9228 case PLANE_CTL_TILED_Y:
9229 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9230 break;
9231 case PLANE_CTL_TILED_YF:
9232 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9233 break;
9234 default:
9235 MISSING_CASE(tiling);
9236 goto error;
9237 }
9238
9239 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9240 plane_config->base = base;
9241
9242 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9243
9244 val = I915_READ(PLANE_SIZE(pipe, 0));
9245 fb->height = ((val >> 16) & 0xfff) + 1;
9246 fb->width = ((val >> 0) & 0x1fff) + 1;
9247
9248 val = I915_READ(PLANE_STRIDE(pipe, 0));
9249 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9250 fb->pixel_format);
9251 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9252
9253 aligned_height = intel_fb_align_height(dev, fb->height,
9254 fb->pixel_format,
9255 fb->modifier[0]);
9256
9257 plane_config->size = fb->pitches[0] * aligned_height;
9258
9259 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9260 pipe_name(pipe), fb->width, fb->height,
9261 fb->bits_per_pixel, base, fb->pitches[0],
9262 plane_config->size);
9263
9264 plane_config->fb = intel_fb;
9265 return;
9266
9267 error:
9268 kfree(fb);
9269 }
9270
9271 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9272 struct intel_crtc_state *pipe_config)
9273 {
9274 struct drm_device *dev = crtc->base.dev;
9275 struct drm_i915_private *dev_priv = dev->dev_private;
9276 uint32_t tmp;
9277
9278 tmp = I915_READ(PF_CTL(crtc->pipe));
9279
9280 if (tmp & PF_ENABLE) {
9281 pipe_config->pch_pfit.enabled = true;
9282 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9283 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9284
9285 /* We currently do not free assignements of panel fitters on
9286 * ivb/hsw (since we don't use the higher upscaling modes which
9287 * differentiates them) so just WARN about this case for now. */
9288 if (IS_GEN7(dev)) {
9289 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9290 PF_PIPE_SEL_IVB(crtc->pipe));
9291 }
9292 }
9293 }
9294
9295 static void
9296 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9297 struct intel_initial_plane_config *plane_config)
9298 {
9299 struct drm_device *dev = crtc->base.dev;
9300 struct drm_i915_private *dev_priv = dev->dev_private;
9301 u32 val, base, offset;
9302 int pipe = crtc->pipe;
9303 int fourcc, pixel_format;
9304 unsigned int aligned_height;
9305 struct drm_framebuffer *fb;
9306 struct intel_framebuffer *intel_fb;
9307
9308 val = I915_READ(DSPCNTR(pipe));
9309 if (!(val & DISPLAY_PLANE_ENABLE))
9310 return;
9311
9312 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9313 if (!intel_fb) {
9314 DRM_DEBUG_KMS("failed to alloc fb\n");
9315 return;
9316 }
9317
9318 fb = &intel_fb->base;
9319
9320 if (INTEL_INFO(dev)->gen >= 4) {
9321 if (val & DISPPLANE_TILED) {
9322 plane_config->tiling = I915_TILING_X;
9323 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9324 }
9325 }
9326
9327 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9328 fourcc = i9xx_format_to_fourcc(pixel_format);
9329 fb->pixel_format = fourcc;
9330 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9331
9332 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9333 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9334 offset = I915_READ(DSPOFFSET(pipe));
9335 } else {
9336 if (plane_config->tiling)
9337 offset = I915_READ(DSPTILEOFF(pipe));
9338 else
9339 offset = I915_READ(DSPLINOFF(pipe));
9340 }
9341 plane_config->base = base;
9342
9343 val = I915_READ(PIPESRC(pipe));
9344 fb->width = ((val >> 16) & 0xfff) + 1;
9345 fb->height = ((val >> 0) & 0xfff) + 1;
9346
9347 val = I915_READ(DSPSTRIDE(pipe));
9348 fb->pitches[0] = val & 0xffffffc0;
9349
9350 aligned_height = intel_fb_align_height(dev, fb->height,
9351 fb->pixel_format,
9352 fb->modifier[0]);
9353
9354 plane_config->size = fb->pitches[0] * aligned_height;
9355
9356 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9357 pipe_name(pipe), fb->width, fb->height,
9358 fb->bits_per_pixel, base, fb->pitches[0],
9359 plane_config->size);
9360
9361 plane_config->fb = intel_fb;
9362 }
9363
9364 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9365 struct intel_crtc_state *pipe_config)
9366 {
9367 struct drm_device *dev = crtc->base.dev;
9368 struct drm_i915_private *dev_priv = dev->dev_private;
9369 uint32_t tmp;
9370
9371 if (!intel_display_power_is_enabled(dev_priv,
9372 POWER_DOMAIN_PIPE(crtc->pipe)))
9373 return false;
9374
9375 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9376 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9377
9378 tmp = I915_READ(PIPECONF(crtc->pipe));
9379 if (!(tmp & PIPECONF_ENABLE))
9380 return false;
9381
9382 switch (tmp & PIPECONF_BPC_MASK) {
9383 case PIPECONF_6BPC:
9384 pipe_config->pipe_bpp = 18;
9385 break;
9386 case PIPECONF_8BPC:
9387 pipe_config->pipe_bpp = 24;
9388 break;
9389 case PIPECONF_10BPC:
9390 pipe_config->pipe_bpp = 30;
9391 break;
9392 case PIPECONF_12BPC:
9393 pipe_config->pipe_bpp = 36;
9394 break;
9395 default:
9396 break;
9397 }
9398
9399 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9400 pipe_config->limited_color_range = true;
9401
9402 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9403 struct intel_shared_dpll *pll;
9404
9405 pipe_config->has_pch_encoder = true;
9406
9407 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9408 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9409 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9410
9411 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9412
9413 if (HAS_PCH_IBX(dev_priv->dev)) {
9414 pipe_config->shared_dpll =
9415 (enum intel_dpll_id) crtc->pipe;
9416 } else {
9417 tmp = I915_READ(PCH_DPLL_SEL);
9418 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9419 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9420 else
9421 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9422 }
9423
9424 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9425
9426 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9427 &pipe_config->dpll_hw_state));
9428
9429 tmp = pipe_config->dpll_hw_state.dpll;
9430 pipe_config->pixel_multiplier =
9431 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9432 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9433
9434 ironlake_pch_clock_get(crtc, pipe_config);
9435 } else {
9436 pipe_config->pixel_multiplier = 1;
9437 }
9438
9439 intel_get_pipe_timings(crtc, pipe_config);
9440
9441 ironlake_get_pfit_config(crtc, pipe_config);
9442
9443 return true;
9444 }
9445
9446 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9447 {
9448 struct drm_device *dev = dev_priv->dev;
9449 struct intel_crtc *crtc;
9450
9451 for_each_intel_crtc(dev, crtc)
9452 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9453 pipe_name(crtc->pipe));
9454
9455 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9456 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9457 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9458 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9459 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9460 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9461 "CPU PWM1 enabled\n");
9462 if (IS_HASWELL(dev))
9463 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9464 "CPU PWM2 enabled\n");
9465 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9466 "PCH PWM1 enabled\n");
9467 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9468 "Utility pin enabled\n");
9469 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9470
9471 /*
9472 * In theory we can still leave IRQs enabled, as long as only the HPD
9473 * interrupts remain enabled. We used to check for that, but since it's
9474 * gen-specific and since we only disable LCPLL after we fully disable
9475 * the interrupts, the check below should be enough.
9476 */
9477 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9478 }
9479
9480 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9481 {
9482 struct drm_device *dev = dev_priv->dev;
9483
9484 if (IS_HASWELL(dev))
9485 return I915_READ(D_COMP_HSW);
9486 else
9487 return I915_READ(D_COMP_BDW);
9488 }
9489
9490 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9491 {
9492 struct drm_device *dev = dev_priv->dev;
9493
9494 if (IS_HASWELL(dev)) {
9495 mutex_lock(&dev_priv->rps.hw_lock);
9496 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9497 val))
9498 DRM_ERROR("Failed to write to D_COMP\n");
9499 mutex_unlock(&dev_priv->rps.hw_lock);
9500 } else {
9501 I915_WRITE(D_COMP_BDW, val);
9502 POSTING_READ(D_COMP_BDW);
9503 }
9504 }
9505
9506 /*
9507 * This function implements pieces of two sequences from BSpec:
9508 * - Sequence for display software to disable LCPLL
9509 * - Sequence for display software to allow package C8+
9510 * The steps implemented here are just the steps that actually touch the LCPLL
9511 * register. Callers should take care of disabling all the display engine
9512 * functions, doing the mode unset, fixing interrupts, etc.
9513 */
9514 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9515 bool switch_to_fclk, bool allow_power_down)
9516 {
9517 uint32_t val;
9518
9519 assert_can_disable_lcpll(dev_priv);
9520
9521 val = I915_READ(LCPLL_CTL);
9522
9523 if (switch_to_fclk) {
9524 val |= LCPLL_CD_SOURCE_FCLK;
9525 I915_WRITE(LCPLL_CTL, val);
9526
9527 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9528 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9529 DRM_ERROR("Switching to FCLK failed\n");
9530
9531 val = I915_READ(LCPLL_CTL);
9532 }
9533
9534 val |= LCPLL_PLL_DISABLE;
9535 I915_WRITE(LCPLL_CTL, val);
9536 POSTING_READ(LCPLL_CTL);
9537
9538 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9539 DRM_ERROR("LCPLL still locked\n");
9540
9541 val = hsw_read_dcomp(dev_priv);
9542 val |= D_COMP_COMP_DISABLE;
9543 hsw_write_dcomp(dev_priv, val);
9544 ndelay(100);
9545
9546 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9547 1))
9548 DRM_ERROR("D_COMP RCOMP still in progress\n");
9549
9550 if (allow_power_down) {
9551 val = I915_READ(LCPLL_CTL);
9552 val |= LCPLL_POWER_DOWN_ALLOW;
9553 I915_WRITE(LCPLL_CTL, val);
9554 POSTING_READ(LCPLL_CTL);
9555 }
9556 }
9557
9558 /*
9559 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9560 * source.
9561 */
9562 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9563 {
9564 uint32_t val;
9565
9566 val = I915_READ(LCPLL_CTL);
9567
9568 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9569 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9570 return;
9571
9572 /*
9573 * Make sure we're not on PC8 state before disabling PC8, otherwise
9574 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9575 */
9576 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9577
9578 if (val & LCPLL_POWER_DOWN_ALLOW) {
9579 val &= ~LCPLL_POWER_DOWN_ALLOW;
9580 I915_WRITE(LCPLL_CTL, val);
9581 POSTING_READ(LCPLL_CTL);
9582 }
9583
9584 val = hsw_read_dcomp(dev_priv);
9585 val |= D_COMP_COMP_FORCE;
9586 val &= ~D_COMP_COMP_DISABLE;
9587 hsw_write_dcomp(dev_priv, val);
9588
9589 val = I915_READ(LCPLL_CTL);
9590 val &= ~LCPLL_PLL_DISABLE;
9591 I915_WRITE(LCPLL_CTL, val);
9592
9593 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9594 DRM_ERROR("LCPLL not locked yet\n");
9595
9596 if (val & LCPLL_CD_SOURCE_FCLK) {
9597 val = I915_READ(LCPLL_CTL);
9598 val &= ~LCPLL_CD_SOURCE_FCLK;
9599 I915_WRITE(LCPLL_CTL, val);
9600
9601 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9602 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9603 DRM_ERROR("Switching back to LCPLL failed\n");
9604 }
9605
9606 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9607 intel_update_cdclk(dev_priv->dev);
9608 }
9609
9610 /*
9611 * Package states C8 and deeper are really deep PC states that can only be
9612 * reached when all the devices on the system allow it, so even if the graphics
9613 * device allows PC8+, it doesn't mean the system will actually get to these
9614 * states. Our driver only allows PC8+ when going into runtime PM.
9615 *
9616 * The requirements for PC8+ are that all the outputs are disabled, the power
9617 * well is disabled and most interrupts are disabled, and these are also
9618 * requirements for runtime PM. When these conditions are met, we manually do
9619 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9620 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9621 * hang the machine.
9622 *
9623 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9624 * the state of some registers, so when we come back from PC8+ we need to
9625 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9626 * need to take care of the registers kept by RC6. Notice that this happens even
9627 * if we don't put the device in PCI D3 state (which is what currently happens
9628 * because of the runtime PM support).
9629 *
9630 * For more, read "Display Sequences for Package C8" on the hardware
9631 * documentation.
9632 */
9633 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9634 {
9635 struct drm_device *dev = dev_priv->dev;
9636 uint32_t val;
9637
9638 DRM_DEBUG_KMS("Enabling package C8+\n");
9639
9640 if (HAS_PCH_LPT_LP(dev)) {
9641 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9642 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9643 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9644 }
9645
9646 lpt_disable_clkout_dp(dev);
9647 hsw_disable_lcpll(dev_priv, true, true);
9648 }
9649
9650 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9651 {
9652 struct drm_device *dev = dev_priv->dev;
9653 uint32_t val;
9654
9655 DRM_DEBUG_KMS("Disabling package C8+\n");
9656
9657 hsw_restore_lcpll(dev_priv);
9658 lpt_init_pch_refclk(dev);
9659
9660 if (HAS_PCH_LPT_LP(dev)) {
9661 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9662 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9663 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9664 }
9665
9666 intel_prepare_ddi(dev);
9667 }
9668
9669 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9670 {
9671 struct drm_device *dev = old_state->dev;
9672 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9673
9674 broxton_set_cdclk(dev, req_cdclk);
9675 }
9676
9677 /* compute the max rate for new configuration */
9678 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9679 {
9680 struct intel_crtc *intel_crtc;
9681 struct intel_crtc_state *crtc_state;
9682 int max_pixel_rate = 0;
9683
9684 for_each_intel_crtc(state->dev, intel_crtc) {
9685 int pixel_rate;
9686
9687 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9688 if (IS_ERR(crtc_state))
9689 return PTR_ERR(crtc_state);
9690
9691 if (!crtc_state->base.enable)
9692 continue;
9693
9694 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9695
9696 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9697 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9698 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9699
9700 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9701 }
9702
9703 return max_pixel_rate;
9704 }
9705
9706 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9707 {
9708 struct drm_i915_private *dev_priv = dev->dev_private;
9709 uint32_t val, data;
9710 int ret;
9711
9712 if (WARN((I915_READ(LCPLL_CTL) &
9713 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9714 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9715 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9716 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9717 "trying to change cdclk frequency with cdclk not enabled\n"))
9718 return;
9719
9720 mutex_lock(&dev_priv->rps.hw_lock);
9721 ret = sandybridge_pcode_write(dev_priv,
9722 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9723 mutex_unlock(&dev_priv->rps.hw_lock);
9724 if (ret) {
9725 DRM_ERROR("failed to inform pcode about cdclk change\n");
9726 return;
9727 }
9728
9729 val = I915_READ(LCPLL_CTL);
9730 val |= LCPLL_CD_SOURCE_FCLK;
9731 I915_WRITE(LCPLL_CTL, val);
9732
9733 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9734 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9735 DRM_ERROR("Switching to FCLK failed\n");
9736
9737 val = I915_READ(LCPLL_CTL);
9738 val &= ~LCPLL_CLK_FREQ_MASK;
9739
9740 switch (cdclk) {
9741 case 450000:
9742 val |= LCPLL_CLK_FREQ_450;
9743 data = 0;
9744 break;
9745 case 540000:
9746 val |= LCPLL_CLK_FREQ_54O_BDW;
9747 data = 1;
9748 break;
9749 case 337500:
9750 val |= LCPLL_CLK_FREQ_337_5_BDW;
9751 data = 2;
9752 break;
9753 case 675000:
9754 val |= LCPLL_CLK_FREQ_675_BDW;
9755 data = 3;
9756 break;
9757 default:
9758 WARN(1, "invalid cdclk frequency\n");
9759 return;
9760 }
9761
9762 I915_WRITE(LCPLL_CTL, val);
9763
9764 val = I915_READ(LCPLL_CTL);
9765 val &= ~LCPLL_CD_SOURCE_FCLK;
9766 I915_WRITE(LCPLL_CTL, val);
9767
9768 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9769 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9770 DRM_ERROR("Switching back to LCPLL failed\n");
9771
9772 mutex_lock(&dev_priv->rps.hw_lock);
9773 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9774 mutex_unlock(&dev_priv->rps.hw_lock);
9775
9776 intel_update_cdclk(dev);
9777
9778 WARN(cdclk != dev_priv->cdclk_freq,
9779 "cdclk requested %d kHz but got %d kHz\n",
9780 cdclk, dev_priv->cdclk_freq);
9781 }
9782
9783 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9784 {
9785 struct drm_i915_private *dev_priv = to_i915(state->dev);
9786 int max_pixclk = ilk_max_pixel_rate(state);
9787 int cdclk;
9788
9789 /*
9790 * FIXME should also account for plane ratio
9791 * once 64bpp pixel formats are supported.
9792 */
9793 if (max_pixclk > 540000)
9794 cdclk = 675000;
9795 else if (max_pixclk > 450000)
9796 cdclk = 540000;
9797 else if (max_pixclk > 337500)
9798 cdclk = 450000;
9799 else
9800 cdclk = 337500;
9801
9802 if (cdclk > dev_priv->max_cdclk_freq) {
9803 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9804 cdclk, dev_priv->max_cdclk_freq);
9805 return -EINVAL;
9806 }
9807
9808 to_intel_atomic_state(state)->cdclk = cdclk;
9809
9810 return 0;
9811 }
9812
9813 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9814 {
9815 struct drm_device *dev = old_state->dev;
9816 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9817
9818 broadwell_set_cdclk(dev, req_cdclk);
9819 }
9820
9821 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9822 struct intel_crtc_state *crtc_state)
9823 {
9824 if (!intel_ddi_pll_select(crtc, crtc_state))
9825 return -EINVAL;
9826
9827 crtc->lowfreq_avail = false;
9828
9829 return 0;
9830 }
9831
9832 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9833 enum port port,
9834 struct intel_crtc_state *pipe_config)
9835 {
9836 switch (port) {
9837 case PORT_A:
9838 pipe_config->ddi_pll_sel = SKL_DPLL0;
9839 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9840 break;
9841 case PORT_B:
9842 pipe_config->ddi_pll_sel = SKL_DPLL1;
9843 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9844 break;
9845 case PORT_C:
9846 pipe_config->ddi_pll_sel = SKL_DPLL2;
9847 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9848 break;
9849 default:
9850 DRM_ERROR("Incorrect port type\n");
9851 }
9852 }
9853
9854 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9855 enum port port,
9856 struct intel_crtc_state *pipe_config)
9857 {
9858 u32 temp, dpll_ctl1;
9859
9860 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9861 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9862
9863 switch (pipe_config->ddi_pll_sel) {
9864 case SKL_DPLL0:
9865 /*
9866 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9867 * of the shared DPLL framework and thus needs to be read out
9868 * separately
9869 */
9870 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9871 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9872 break;
9873 case SKL_DPLL1:
9874 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9875 break;
9876 case SKL_DPLL2:
9877 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9878 break;
9879 case SKL_DPLL3:
9880 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9881 break;
9882 }
9883 }
9884
9885 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9886 enum port port,
9887 struct intel_crtc_state *pipe_config)
9888 {
9889 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9890
9891 switch (pipe_config->ddi_pll_sel) {
9892 case PORT_CLK_SEL_WRPLL1:
9893 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9894 break;
9895 case PORT_CLK_SEL_WRPLL2:
9896 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9897 break;
9898 case PORT_CLK_SEL_SPLL:
9899 pipe_config->shared_dpll = DPLL_ID_SPLL;
9900 break;
9901 }
9902 }
9903
9904 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9905 struct intel_crtc_state *pipe_config)
9906 {
9907 struct drm_device *dev = crtc->base.dev;
9908 struct drm_i915_private *dev_priv = dev->dev_private;
9909 struct intel_shared_dpll *pll;
9910 enum port port;
9911 uint32_t tmp;
9912
9913 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9914
9915 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9916
9917 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9918 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9919 else if (IS_BROXTON(dev))
9920 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9921 else
9922 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9923
9924 if (pipe_config->shared_dpll >= 0) {
9925 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9926
9927 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9928 &pipe_config->dpll_hw_state));
9929 }
9930
9931 /*
9932 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9933 * DDI E. So just check whether this pipe is wired to DDI E and whether
9934 * the PCH transcoder is on.
9935 */
9936 if (INTEL_INFO(dev)->gen < 9 &&
9937 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9938 pipe_config->has_pch_encoder = true;
9939
9940 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9941 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9942 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9943
9944 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9945 }
9946 }
9947
9948 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9949 struct intel_crtc_state *pipe_config)
9950 {
9951 struct drm_device *dev = crtc->base.dev;
9952 struct drm_i915_private *dev_priv = dev->dev_private;
9953 enum intel_display_power_domain pfit_domain;
9954 uint32_t tmp;
9955
9956 if (!intel_display_power_is_enabled(dev_priv,
9957 POWER_DOMAIN_PIPE(crtc->pipe)))
9958 return false;
9959
9960 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9961 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9962
9963 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9964 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9965 enum pipe trans_edp_pipe;
9966 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9967 default:
9968 WARN(1, "unknown pipe linked to edp transcoder\n");
9969 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9970 case TRANS_DDI_EDP_INPUT_A_ON:
9971 trans_edp_pipe = PIPE_A;
9972 break;
9973 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9974 trans_edp_pipe = PIPE_B;
9975 break;
9976 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9977 trans_edp_pipe = PIPE_C;
9978 break;
9979 }
9980
9981 if (trans_edp_pipe == crtc->pipe)
9982 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9983 }
9984
9985 if (!intel_display_power_is_enabled(dev_priv,
9986 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9987 return false;
9988
9989 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9990 if (!(tmp & PIPECONF_ENABLE))
9991 return false;
9992
9993 haswell_get_ddi_port_state(crtc, pipe_config);
9994
9995 intel_get_pipe_timings(crtc, pipe_config);
9996
9997 if (INTEL_INFO(dev)->gen >= 9) {
9998 skl_init_scalers(dev, crtc, pipe_config);
9999 }
10000
10001 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10002
10003 if (INTEL_INFO(dev)->gen >= 9) {
10004 pipe_config->scaler_state.scaler_id = -1;
10005 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10006 }
10007
10008 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
10009 if (INTEL_INFO(dev)->gen >= 9)
10010 skylake_get_pfit_config(crtc, pipe_config);
10011 else
10012 ironlake_get_pfit_config(crtc, pipe_config);
10013 }
10014
10015 if (IS_HASWELL(dev))
10016 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10017 (I915_READ(IPS_CTL) & IPS_ENABLE);
10018
10019 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
10020 pipe_config->pixel_multiplier =
10021 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10022 } else {
10023 pipe_config->pixel_multiplier = 1;
10024 }
10025
10026 return true;
10027 }
10028
10029 static void i845_update_cursor(struct drm_crtc *crtc, u32 base, bool on)
10030 {
10031 struct drm_device *dev = crtc->dev;
10032 struct drm_i915_private *dev_priv = dev->dev_private;
10033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10034 uint32_t cntl = 0, size = 0;
10035
10036 if (on) {
10037 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
10038 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
10039 unsigned int stride = roundup_pow_of_two(width) * 4;
10040
10041 switch (stride) {
10042 default:
10043 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10044 width, stride);
10045 stride = 256;
10046 /* fallthrough */
10047 case 256:
10048 case 512:
10049 case 1024:
10050 case 2048:
10051 break;
10052 }
10053
10054 cntl |= CURSOR_ENABLE |
10055 CURSOR_GAMMA_ENABLE |
10056 CURSOR_FORMAT_ARGB |
10057 CURSOR_STRIDE(stride);
10058
10059 size = (height << 12) | width;
10060 }
10061
10062 if (intel_crtc->cursor_cntl != 0 &&
10063 (intel_crtc->cursor_base != base ||
10064 intel_crtc->cursor_size != size ||
10065 intel_crtc->cursor_cntl != cntl)) {
10066 /* On these chipsets we can only modify the base/size/stride
10067 * whilst the cursor is disabled.
10068 */
10069 I915_WRITE(CURCNTR(PIPE_A), 0);
10070 POSTING_READ(CURCNTR(PIPE_A));
10071 intel_crtc->cursor_cntl = 0;
10072 }
10073
10074 if (intel_crtc->cursor_base != base) {
10075 I915_WRITE(CURBASE(PIPE_A), base);
10076 intel_crtc->cursor_base = base;
10077 }
10078
10079 if (intel_crtc->cursor_size != size) {
10080 I915_WRITE(CURSIZE, size);
10081 intel_crtc->cursor_size = size;
10082 }
10083
10084 if (intel_crtc->cursor_cntl != cntl) {
10085 I915_WRITE(CURCNTR(PIPE_A), cntl);
10086 POSTING_READ(CURCNTR(PIPE_A));
10087 intel_crtc->cursor_cntl = cntl;
10088 }
10089 }
10090
10091 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, bool on)
10092 {
10093 struct drm_device *dev = crtc->dev;
10094 struct drm_i915_private *dev_priv = dev->dev_private;
10095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10096 int pipe = intel_crtc->pipe;
10097 uint32_t cntl = 0;
10098
10099 if (on) {
10100 cntl = MCURSOR_GAMMA_ENABLE;
10101 switch (intel_crtc->base.cursor->state->crtc_w) {
10102 case 64:
10103 cntl |= CURSOR_MODE_64_ARGB_AX;
10104 break;
10105 case 128:
10106 cntl |= CURSOR_MODE_128_ARGB_AX;
10107 break;
10108 case 256:
10109 cntl |= CURSOR_MODE_256_ARGB_AX;
10110 break;
10111 default:
10112 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
10113 return;
10114 }
10115 cntl |= pipe << 28; /* Connect to correct pipe */
10116
10117 if (HAS_DDI(dev))
10118 cntl |= CURSOR_PIPE_CSC_ENABLE;
10119 }
10120
10121 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
10122 cntl |= CURSOR_ROTATE_180;
10123
10124 if (intel_crtc->cursor_cntl != cntl) {
10125 I915_WRITE(CURCNTR(pipe), cntl);
10126 POSTING_READ(CURCNTR(pipe));
10127 intel_crtc->cursor_cntl = cntl;
10128 }
10129
10130 /* and commit changes on next vblank */
10131 I915_WRITE(CURBASE(pipe), base);
10132 POSTING_READ(CURBASE(pipe));
10133
10134 intel_crtc->cursor_base = base;
10135 }
10136
10137 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10138 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10139 bool on)
10140 {
10141 struct drm_device *dev = crtc->dev;
10142 struct drm_i915_private *dev_priv = dev->dev_private;
10143 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10144 int pipe = intel_crtc->pipe;
10145 struct drm_plane_state *cursor_state = crtc->cursor->state;
10146 int x = cursor_state->crtc_x;
10147 int y = cursor_state->crtc_y;
10148 u32 base = 0, pos = 0;
10149
10150 base = intel_crtc->cursor_addr;
10151
10152 if (x >= intel_crtc->config->pipe_src_w)
10153 on = false;
10154
10155 if (y >= intel_crtc->config->pipe_src_h)
10156 on = false;
10157
10158 if (x < 0) {
10159 if (x + cursor_state->crtc_w <= 0)
10160 on = false;
10161
10162 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10163 x = -x;
10164 }
10165 pos |= x << CURSOR_X_SHIFT;
10166
10167 if (y < 0) {
10168 if (y + cursor_state->crtc_h <= 0)
10169 on = false;
10170
10171 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10172 y = -y;
10173 }
10174 pos |= y << CURSOR_Y_SHIFT;
10175
10176 I915_WRITE(CURPOS(pipe), pos);
10177
10178 /* ILK+ do this automagically */
10179 if (HAS_GMCH_DISPLAY(dev) &&
10180 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10181 base += (cursor_state->crtc_h *
10182 cursor_state->crtc_w - 1) * 4;
10183 }
10184
10185 if (IS_845G(dev) || IS_I865G(dev))
10186 i845_update_cursor(crtc, base, on);
10187 else
10188 i9xx_update_cursor(crtc, base, on);
10189 }
10190
10191 static bool cursor_size_ok(struct drm_device *dev,
10192 uint32_t width, uint32_t height)
10193 {
10194 if (width == 0 || height == 0)
10195 return false;
10196
10197 /*
10198 * 845g/865g are special in that they are only limited by
10199 * the width of their cursors, the height is arbitrary up to
10200 * the precision of the register. Everything else requires
10201 * square cursors, limited to a few power-of-two sizes.
10202 */
10203 if (IS_845G(dev) || IS_I865G(dev)) {
10204 if ((width & 63) != 0)
10205 return false;
10206
10207 if (width > (IS_845G(dev) ? 64 : 512))
10208 return false;
10209
10210 if (height > 1023)
10211 return false;
10212 } else {
10213 switch (width | height) {
10214 case 256:
10215 case 128:
10216 if (IS_GEN2(dev))
10217 return false;
10218 case 64:
10219 break;
10220 default:
10221 return false;
10222 }
10223 }
10224
10225 return true;
10226 }
10227
10228 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10229 u16 *blue, uint32_t start, uint32_t size)
10230 {
10231 int end = (start + size > 256) ? 256 : start + size, i;
10232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10233
10234 for (i = start; i < end; i++) {
10235 intel_crtc->lut_r[i] = red[i] >> 8;
10236 intel_crtc->lut_g[i] = green[i] >> 8;
10237 intel_crtc->lut_b[i] = blue[i] >> 8;
10238 }
10239
10240 intel_crtc_load_lut(crtc);
10241 }
10242
10243 /* VESA 640x480x72Hz mode to set on the pipe */
10244 static struct drm_display_mode load_detect_mode = {
10245 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10246 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10247 };
10248
10249 struct drm_framebuffer *
10250 __intel_framebuffer_create(struct drm_device *dev,
10251 struct drm_mode_fb_cmd2 *mode_cmd,
10252 struct drm_i915_gem_object *obj)
10253 {
10254 struct intel_framebuffer *intel_fb;
10255 int ret;
10256
10257 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10258 if (!intel_fb)
10259 return ERR_PTR(-ENOMEM);
10260
10261 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10262 if (ret)
10263 goto err;
10264
10265 return &intel_fb->base;
10266
10267 err:
10268 kfree(intel_fb);
10269 return ERR_PTR(ret);
10270 }
10271
10272 static struct drm_framebuffer *
10273 intel_framebuffer_create(struct drm_device *dev,
10274 struct drm_mode_fb_cmd2 *mode_cmd,
10275 struct drm_i915_gem_object *obj)
10276 {
10277 struct drm_framebuffer *fb;
10278 int ret;
10279
10280 ret = i915_mutex_lock_interruptible(dev);
10281 if (ret)
10282 return ERR_PTR(ret);
10283 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10284 mutex_unlock(&dev->struct_mutex);
10285
10286 return fb;
10287 }
10288
10289 static u32
10290 intel_framebuffer_pitch_for_width(int width, int bpp)
10291 {
10292 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10293 return ALIGN(pitch, 64);
10294 }
10295
10296 static u32
10297 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10298 {
10299 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10300 return PAGE_ALIGN(pitch * mode->vdisplay);
10301 }
10302
10303 static struct drm_framebuffer *
10304 intel_framebuffer_create_for_mode(struct drm_device *dev,
10305 struct drm_display_mode *mode,
10306 int depth, int bpp)
10307 {
10308 struct drm_framebuffer *fb;
10309 struct drm_i915_gem_object *obj;
10310 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10311
10312 obj = i915_gem_alloc_object(dev,
10313 intel_framebuffer_size_for_mode(mode, bpp));
10314 if (obj == NULL)
10315 return ERR_PTR(-ENOMEM);
10316
10317 mode_cmd.width = mode->hdisplay;
10318 mode_cmd.height = mode->vdisplay;
10319 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10320 bpp);
10321 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10322
10323 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10324 if (IS_ERR(fb))
10325 drm_gem_object_unreference_unlocked(&obj->base);
10326
10327 return fb;
10328 }
10329
10330 static struct drm_framebuffer *
10331 mode_fits_in_fbdev(struct drm_device *dev,
10332 struct drm_display_mode *mode)
10333 {
10334 #ifdef CONFIG_DRM_FBDEV_EMULATION
10335 struct drm_i915_private *dev_priv = dev->dev_private;
10336 struct drm_i915_gem_object *obj;
10337 struct drm_framebuffer *fb;
10338
10339 if (!dev_priv->fbdev)
10340 return NULL;
10341
10342 if (!dev_priv->fbdev->fb)
10343 return NULL;
10344
10345 obj = dev_priv->fbdev->fb->obj;
10346 BUG_ON(!obj);
10347
10348 fb = &dev_priv->fbdev->fb->base;
10349 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10350 fb->bits_per_pixel))
10351 return NULL;
10352
10353 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10354 return NULL;
10355
10356 return fb;
10357 #else
10358 return NULL;
10359 #endif
10360 }
10361
10362 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10363 struct drm_crtc *crtc,
10364 struct drm_display_mode *mode,
10365 struct drm_framebuffer *fb,
10366 int x, int y)
10367 {
10368 struct drm_plane_state *plane_state;
10369 int hdisplay, vdisplay;
10370 int ret;
10371
10372 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10373 if (IS_ERR(plane_state))
10374 return PTR_ERR(plane_state);
10375
10376 if (mode)
10377 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10378 else
10379 hdisplay = vdisplay = 0;
10380
10381 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10382 if (ret)
10383 return ret;
10384 drm_atomic_set_fb_for_plane(plane_state, fb);
10385 plane_state->crtc_x = 0;
10386 plane_state->crtc_y = 0;
10387 plane_state->crtc_w = hdisplay;
10388 plane_state->crtc_h = vdisplay;
10389 plane_state->src_x = x << 16;
10390 plane_state->src_y = y << 16;
10391 plane_state->src_w = hdisplay << 16;
10392 plane_state->src_h = vdisplay << 16;
10393
10394 return 0;
10395 }
10396
10397 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10398 struct drm_display_mode *mode,
10399 struct intel_load_detect_pipe *old,
10400 struct drm_modeset_acquire_ctx *ctx)
10401 {
10402 struct intel_crtc *intel_crtc;
10403 struct intel_encoder *intel_encoder =
10404 intel_attached_encoder(connector);
10405 struct drm_crtc *possible_crtc;
10406 struct drm_encoder *encoder = &intel_encoder->base;
10407 struct drm_crtc *crtc = NULL;
10408 struct drm_device *dev = encoder->dev;
10409 struct drm_framebuffer *fb;
10410 struct drm_mode_config *config = &dev->mode_config;
10411 struct drm_atomic_state *state = NULL;
10412 struct drm_connector_state *connector_state;
10413 struct intel_crtc_state *crtc_state;
10414 int ret, i = -1;
10415
10416 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10417 connector->base.id, connector->name,
10418 encoder->base.id, encoder->name);
10419
10420 retry:
10421 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10422 if (ret)
10423 goto fail;
10424
10425 /*
10426 * Algorithm gets a little messy:
10427 *
10428 * - if the connector already has an assigned crtc, use it (but make
10429 * sure it's on first)
10430 *
10431 * - try to find the first unused crtc that can drive this connector,
10432 * and use that if we find one
10433 */
10434
10435 /* See if we already have a CRTC for this connector */
10436 if (encoder->crtc) {
10437 crtc = encoder->crtc;
10438
10439 ret = drm_modeset_lock(&crtc->mutex, ctx);
10440 if (ret)
10441 goto fail;
10442 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10443 if (ret)
10444 goto fail;
10445
10446 old->dpms_mode = connector->dpms;
10447 old->load_detect_temp = false;
10448
10449 /* Make sure the crtc and connector are running */
10450 if (connector->dpms != DRM_MODE_DPMS_ON)
10451 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10452
10453 return true;
10454 }
10455
10456 /* Find an unused one (if possible) */
10457 for_each_crtc(dev, possible_crtc) {
10458 i++;
10459 if (!(encoder->possible_crtcs & (1 << i)))
10460 continue;
10461 if (possible_crtc->state->enable)
10462 continue;
10463
10464 crtc = possible_crtc;
10465 break;
10466 }
10467
10468 /*
10469 * If we didn't find an unused CRTC, don't use any.
10470 */
10471 if (!crtc) {
10472 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10473 goto fail;
10474 }
10475
10476 ret = drm_modeset_lock(&crtc->mutex, ctx);
10477 if (ret)
10478 goto fail;
10479 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10480 if (ret)
10481 goto fail;
10482
10483 intel_crtc = to_intel_crtc(crtc);
10484 old->dpms_mode = connector->dpms;
10485 old->load_detect_temp = true;
10486 old->release_fb = NULL;
10487
10488 state = drm_atomic_state_alloc(dev);
10489 if (!state)
10490 return false;
10491
10492 state->acquire_ctx = ctx;
10493
10494 connector_state = drm_atomic_get_connector_state(state, connector);
10495 if (IS_ERR(connector_state)) {
10496 ret = PTR_ERR(connector_state);
10497 goto fail;
10498 }
10499
10500 connector_state->crtc = crtc;
10501 connector_state->best_encoder = &intel_encoder->base;
10502
10503 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10504 if (IS_ERR(crtc_state)) {
10505 ret = PTR_ERR(crtc_state);
10506 goto fail;
10507 }
10508
10509 crtc_state->base.active = crtc_state->base.enable = true;
10510
10511 if (!mode)
10512 mode = &load_detect_mode;
10513
10514 /* We need a framebuffer large enough to accommodate all accesses
10515 * that the plane may generate whilst we perform load detection.
10516 * We can not rely on the fbcon either being present (we get called
10517 * during its initialisation to detect all boot displays, or it may
10518 * not even exist) or that it is large enough to satisfy the
10519 * requested mode.
10520 */
10521 fb = mode_fits_in_fbdev(dev, mode);
10522 if (fb == NULL) {
10523 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10524 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10525 old->release_fb = fb;
10526 } else
10527 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10528 if (IS_ERR(fb)) {
10529 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10530 goto fail;
10531 }
10532
10533 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10534 if (ret)
10535 goto fail;
10536
10537 drm_mode_copy(&crtc_state->base.mode, mode);
10538
10539 if (drm_atomic_commit(state)) {
10540 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10541 if (old->release_fb)
10542 old->release_fb->funcs->destroy(old->release_fb);
10543 goto fail;
10544 }
10545 crtc->primary->crtc = crtc;
10546
10547 /* let the connector get through one full cycle before testing */
10548 intel_wait_for_vblank(dev, intel_crtc->pipe);
10549 return true;
10550
10551 fail:
10552 drm_atomic_state_free(state);
10553 state = NULL;
10554
10555 if (ret == -EDEADLK) {
10556 drm_modeset_backoff(ctx);
10557 goto retry;
10558 }
10559
10560 return false;
10561 }
10562
10563 void intel_release_load_detect_pipe(struct drm_connector *connector,
10564 struct intel_load_detect_pipe *old,
10565 struct drm_modeset_acquire_ctx *ctx)
10566 {
10567 struct drm_device *dev = connector->dev;
10568 struct intel_encoder *intel_encoder =
10569 intel_attached_encoder(connector);
10570 struct drm_encoder *encoder = &intel_encoder->base;
10571 struct drm_crtc *crtc = encoder->crtc;
10572 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10573 struct drm_atomic_state *state;
10574 struct drm_connector_state *connector_state;
10575 struct intel_crtc_state *crtc_state;
10576 int ret;
10577
10578 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10579 connector->base.id, connector->name,
10580 encoder->base.id, encoder->name);
10581
10582 if (old->load_detect_temp) {
10583 state = drm_atomic_state_alloc(dev);
10584 if (!state)
10585 goto fail;
10586
10587 state->acquire_ctx = ctx;
10588
10589 connector_state = drm_atomic_get_connector_state(state, connector);
10590 if (IS_ERR(connector_state))
10591 goto fail;
10592
10593 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10594 if (IS_ERR(crtc_state))
10595 goto fail;
10596
10597 connector_state->best_encoder = NULL;
10598 connector_state->crtc = NULL;
10599
10600 crtc_state->base.enable = crtc_state->base.active = false;
10601
10602 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10603 0, 0);
10604 if (ret)
10605 goto fail;
10606
10607 ret = drm_atomic_commit(state);
10608 if (ret)
10609 goto fail;
10610
10611 if (old->release_fb) {
10612 drm_framebuffer_unregister_private(old->release_fb);
10613 drm_framebuffer_unreference(old->release_fb);
10614 }
10615
10616 return;
10617 }
10618
10619 /* Switch crtc and encoder back off if necessary */
10620 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10621 connector->funcs->dpms(connector, old->dpms_mode);
10622
10623 return;
10624 fail:
10625 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10626 drm_atomic_state_free(state);
10627 }
10628
10629 static int i9xx_pll_refclk(struct drm_device *dev,
10630 const struct intel_crtc_state *pipe_config)
10631 {
10632 struct drm_i915_private *dev_priv = dev->dev_private;
10633 u32 dpll = pipe_config->dpll_hw_state.dpll;
10634
10635 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10636 return dev_priv->vbt.lvds_ssc_freq;
10637 else if (HAS_PCH_SPLIT(dev))
10638 return 120000;
10639 else if (!IS_GEN2(dev))
10640 return 96000;
10641 else
10642 return 48000;
10643 }
10644
10645 /* Returns the clock of the currently programmed mode of the given pipe. */
10646 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10647 struct intel_crtc_state *pipe_config)
10648 {
10649 struct drm_device *dev = crtc->base.dev;
10650 struct drm_i915_private *dev_priv = dev->dev_private;
10651 int pipe = pipe_config->cpu_transcoder;
10652 u32 dpll = pipe_config->dpll_hw_state.dpll;
10653 u32 fp;
10654 intel_clock_t clock;
10655 int port_clock;
10656 int refclk = i9xx_pll_refclk(dev, pipe_config);
10657
10658 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10659 fp = pipe_config->dpll_hw_state.fp0;
10660 else
10661 fp = pipe_config->dpll_hw_state.fp1;
10662
10663 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10664 if (IS_PINEVIEW(dev)) {
10665 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10666 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10667 } else {
10668 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10669 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10670 }
10671
10672 if (!IS_GEN2(dev)) {
10673 if (IS_PINEVIEW(dev))
10674 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10675 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10676 else
10677 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10678 DPLL_FPA01_P1_POST_DIV_SHIFT);
10679
10680 switch (dpll & DPLL_MODE_MASK) {
10681 case DPLLB_MODE_DAC_SERIAL:
10682 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10683 5 : 10;
10684 break;
10685 case DPLLB_MODE_LVDS:
10686 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10687 7 : 14;
10688 break;
10689 default:
10690 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10691 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10692 return;
10693 }
10694
10695 if (IS_PINEVIEW(dev))
10696 port_clock = pnv_calc_dpll_params(refclk, &clock);
10697 else
10698 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10699 } else {
10700 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10701 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10702
10703 if (is_lvds) {
10704 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10705 DPLL_FPA01_P1_POST_DIV_SHIFT);
10706
10707 if (lvds & LVDS_CLKB_POWER_UP)
10708 clock.p2 = 7;
10709 else
10710 clock.p2 = 14;
10711 } else {
10712 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10713 clock.p1 = 2;
10714 else {
10715 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10716 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10717 }
10718 if (dpll & PLL_P2_DIVIDE_BY_4)
10719 clock.p2 = 4;
10720 else
10721 clock.p2 = 2;
10722 }
10723
10724 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10725 }
10726
10727 /*
10728 * This value includes pixel_multiplier. We will use
10729 * port_clock to compute adjusted_mode.crtc_clock in the
10730 * encoder's get_config() function.
10731 */
10732 pipe_config->port_clock = port_clock;
10733 }
10734
10735 int intel_dotclock_calculate(int link_freq,
10736 const struct intel_link_m_n *m_n)
10737 {
10738 /*
10739 * The calculation for the data clock is:
10740 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10741 * But we want to avoid losing precison if possible, so:
10742 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10743 *
10744 * and the link clock is simpler:
10745 * link_clock = (m * link_clock) / n
10746 */
10747
10748 if (!m_n->link_n)
10749 return 0;
10750
10751 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10752 }
10753
10754 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10755 struct intel_crtc_state *pipe_config)
10756 {
10757 struct drm_device *dev = crtc->base.dev;
10758
10759 /* read out port_clock from the DPLL */
10760 i9xx_crtc_clock_get(crtc, pipe_config);
10761
10762 /*
10763 * This value does not include pixel_multiplier.
10764 * We will check that port_clock and adjusted_mode.crtc_clock
10765 * agree once we know their relationship in the encoder's
10766 * get_config() function.
10767 */
10768 pipe_config->base.adjusted_mode.crtc_clock =
10769 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10770 &pipe_config->fdi_m_n);
10771 }
10772
10773 /** Returns the currently programmed mode of the given pipe. */
10774 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10775 struct drm_crtc *crtc)
10776 {
10777 struct drm_i915_private *dev_priv = dev->dev_private;
10778 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10779 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10780 struct drm_display_mode *mode;
10781 struct intel_crtc_state pipe_config;
10782 int htot = I915_READ(HTOTAL(cpu_transcoder));
10783 int hsync = I915_READ(HSYNC(cpu_transcoder));
10784 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10785 int vsync = I915_READ(VSYNC(cpu_transcoder));
10786 enum pipe pipe = intel_crtc->pipe;
10787
10788 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10789 if (!mode)
10790 return NULL;
10791
10792 /*
10793 * Construct a pipe_config sufficient for getting the clock info
10794 * back out of crtc_clock_get.
10795 *
10796 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10797 * to use a real value here instead.
10798 */
10799 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10800 pipe_config.pixel_multiplier = 1;
10801 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10802 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10803 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10804 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10805
10806 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10807 mode->hdisplay = (htot & 0xffff) + 1;
10808 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10809 mode->hsync_start = (hsync & 0xffff) + 1;
10810 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10811 mode->vdisplay = (vtot & 0xffff) + 1;
10812 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10813 mode->vsync_start = (vsync & 0xffff) + 1;
10814 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10815
10816 drm_mode_set_name(mode);
10817
10818 return mode;
10819 }
10820
10821 void intel_mark_busy(struct drm_device *dev)
10822 {
10823 struct drm_i915_private *dev_priv = dev->dev_private;
10824
10825 if (dev_priv->mm.busy)
10826 return;
10827
10828 intel_runtime_pm_get(dev_priv);
10829 i915_update_gfx_val(dev_priv);
10830 if (INTEL_INFO(dev)->gen >= 6)
10831 gen6_rps_busy(dev_priv);
10832 dev_priv->mm.busy = true;
10833 }
10834
10835 void intel_mark_idle(struct drm_device *dev)
10836 {
10837 struct drm_i915_private *dev_priv = dev->dev_private;
10838
10839 if (!dev_priv->mm.busy)
10840 return;
10841
10842 dev_priv->mm.busy = false;
10843
10844 if (INTEL_INFO(dev)->gen >= 6)
10845 gen6_rps_idle(dev->dev_private);
10846
10847 intel_runtime_pm_put(dev_priv);
10848 }
10849
10850 static void intel_crtc_destroy(struct drm_crtc *crtc)
10851 {
10852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10853 struct drm_device *dev = crtc->dev;
10854 struct intel_unpin_work *work;
10855
10856 spin_lock_irq(&dev->event_lock);
10857 work = intel_crtc->unpin_work;
10858 intel_crtc->unpin_work = NULL;
10859 spin_unlock_irq(&dev->event_lock);
10860
10861 if (work) {
10862 cancel_work_sync(&work->work);
10863 kfree(work);
10864 }
10865
10866 drm_crtc_cleanup(crtc);
10867
10868 kfree(intel_crtc);
10869 }
10870
10871 static void intel_unpin_work_fn(struct work_struct *__work)
10872 {
10873 struct intel_unpin_work *work =
10874 container_of(__work, struct intel_unpin_work, work);
10875 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10876 struct drm_device *dev = crtc->base.dev;
10877 struct drm_plane *primary = crtc->base.primary;
10878
10879 mutex_lock(&dev->struct_mutex);
10880 intel_unpin_fb_obj(work->old_fb, primary->state);
10881 drm_gem_object_unreference(&work->pending_flip_obj->base);
10882
10883 if (work->flip_queued_req)
10884 i915_gem_request_assign(&work->flip_queued_req, NULL);
10885 mutex_unlock(&dev->struct_mutex);
10886
10887 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10888 drm_framebuffer_unreference(work->old_fb);
10889
10890 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10891 atomic_dec(&crtc->unpin_work_count);
10892
10893 kfree(work);
10894 }
10895
10896 static void do_intel_finish_page_flip(struct drm_device *dev,
10897 struct drm_crtc *crtc)
10898 {
10899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10900 struct intel_unpin_work *work;
10901 unsigned long flags;
10902
10903 /* Ignore early vblank irqs */
10904 if (intel_crtc == NULL)
10905 return;
10906
10907 /*
10908 * This is called both by irq handlers and the reset code (to complete
10909 * lost pageflips) so needs the full irqsave spinlocks.
10910 */
10911 spin_lock_irqsave(&dev->event_lock, flags);
10912 work = intel_crtc->unpin_work;
10913
10914 /* Ensure we don't miss a work->pending update ... */
10915 smp_rmb();
10916
10917 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10918 spin_unlock_irqrestore(&dev->event_lock, flags);
10919 return;
10920 }
10921
10922 page_flip_completed(intel_crtc);
10923
10924 spin_unlock_irqrestore(&dev->event_lock, flags);
10925 }
10926
10927 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10928 {
10929 struct drm_i915_private *dev_priv = dev->dev_private;
10930 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10931
10932 do_intel_finish_page_flip(dev, crtc);
10933 }
10934
10935 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10936 {
10937 struct drm_i915_private *dev_priv = dev->dev_private;
10938 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10939
10940 do_intel_finish_page_flip(dev, crtc);
10941 }
10942
10943 /* Is 'a' after or equal to 'b'? */
10944 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10945 {
10946 return !((a - b) & 0x80000000);
10947 }
10948
10949 static bool page_flip_finished(struct intel_crtc *crtc)
10950 {
10951 struct drm_device *dev = crtc->base.dev;
10952 struct drm_i915_private *dev_priv = dev->dev_private;
10953
10954 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10955 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10956 return true;
10957
10958 /*
10959 * The relevant registers doen't exist on pre-ctg.
10960 * As the flip done interrupt doesn't trigger for mmio
10961 * flips on gmch platforms, a flip count check isn't
10962 * really needed there. But since ctg has the registers,
10963 * include it in the check anyway.
10964 */
10965 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10966 return true;
10967
10968 /*
10969 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10970 * used the same base address. In that case the mmio flip might
10971 * have completed, but the CS hasn't even executed the flip yet.
10972 *
10973 * A flip count check isn't enough as the CS might have updated
10974 * the base address just after start of vblank, but before we
10975 * managed to process the interrupt. This means we'd complete the
10976 * CS flip too soon.
10977 *
10978 * Combining both checks should get us a good enough result. It may
10979 * still happen that the CS flip has been executed, but has not
10980 * yet actually completed. But in case the base address is the same
10981 * anyway, we don't really care.
10982 */
10983 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10984 crtc->unpin_work->gtt_offset &&
10985 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10986 crtc->unpin_work->flip_count);
10987 }
10988
10989 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10990 {
10991 struct drm_i915_private *dev_priv = dev->dev_private;
10992 struct intel_crtc *intel_crtc =
10993 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10994 unsigned long flags;
10995
10996
10997 /*
10998 * This is called both by irq handlers and the reset code (to complete
10999 * lost pageflips) so needs the full irqsave spinlocks.
11000 *
11001 * NB: An MMIO update of the plane base pointer will also
11002 * generate a page-flip completion irq, i.e. every modeset
11003 * is also accompanied by a spurious intel_prepare_page_flip().
11004 */
11005 spin_lock_irqsave(&dev->event_lock, flags);
11006 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
11007 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
11008 spin_unlock_irqrestore(&dev->event_lock, flags);
11009 }
11010
11011 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
11012 {
11013 /* Ensure that the work item is consistent when activating it ... */
11014 smp_wmb();
11015 atomic_set(&work->pending, INTEL_FLIP_PENDING);
11016 /* and that it is marked active as soon as the irq could fire. */
11017 smp_wmb();
11018 }
11019
11020 static int intel_gen2_queue_flip(struct drm_device *dev,
11021 struct drm_crtc *crtc,
11022 struct drm_framebuffer *fb,
11023 struct drm_i915_gem_object *obj,
11024 struct drm_i915_gem_request *req,
11025 uint32_t flags)
11026 {
11027 struct intel_engine_cs *ring = req->ring;
11028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11029 u32 flip_mask;
11030 int ret;
11031
11032 ret = intel_ring_begin(req, 6);
11033 if (ret)
11034 return ret;
11035
11036 /* Can't queue multiple flips, so wait for the previous
11037 * one to finish before executing the next.
11038 */
11039 if (intel_crtc->plane)
11040 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11041 else
11042 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11043 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11044 intel_ring_emit(ring, MI_NOOP);
11045 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11046 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11047 intel_ring_emit(ring, fb->pitches[0]);
11048 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11049 intel_ring_emit(ring, 0); /* aux display base address, unused */
11050
11051 intel_mark_page_flip_active(intel_crtc->unpin_work);
11052 return 0;
11053 }
11054
11055 static int intel_gen3_queue_flip(struct drm_device *dev,
11056 struct drm_crtc *crtc,
11057 struct drm_framebuffer *fb,
11058 struct drm_i915_gem_object *obj,
11059 struct drm_i915_gem_request *req,
11060 uint32_t flags)
11061 {
11062 struct intel_engine_cs *ring = req->ring;
11063 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11064 u32 flip_mask;
11065 int ret;
11066
11067 ret = intel_ring_begin(req, 6);
11068 if (ret)
11069 return ret;
11070
11071 if (intel_crtc->plane)
11072 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11073 else
11074 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11075 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11076 intel_ring_emit(ring, MI_NOOP);
11077 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11078 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11079 intel_ring_emit(ring, fb->pitches[0]);
11080 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11081 intel_ring_emit(ring, MI_NOOP);
11082
11083 intel_mark_page_flip_active(intel_crtc->unpin_work);
11084 return 0;
11085 }
11086
11087 static int intel_gen4_queue_flip(struct drm_device *dev,
11088 struct drm_crtc *crtc,
11089 struct drm_framebuffer *fb,
11090 struct drm_i915_gem_object *obj,
11091 struct drm_i915_gem_request *req,
11092 uint32_t flags)
11093 {
11094 struct intel_engine_cs *ring = req->ring;
11095 struct drm_i915_private *dev_priv = dev->dev_private;
11096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11097 uint32_t pf, pipesrc;
11098 int ret;
11099
11100 ret = intel_ring_begin(req, 4);
11101 if (ret)
11102 return ret;
11103
11104 /* i965+ uses the linear or tiled offsets from the
11105 * Display Registers (which do not change across a page-flip)
11106 * so we need only reprogram the base address.
11107 */
11108 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11109 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11110 intel_ring_emit(ring, fb->pitches[0]);
11111 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11112 obj->tiling_mode);
11113
11114 /* XXX Enabling the panel-fitter across page-flip is so far
11115 * untested on non-native modes, so ignore it for now.
11116 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11117 */
11118 pf = 0;
11119 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11120 intel_ring_emit(ring, pf | pipesrc);
11121
11122 intel_mark_page_flip_active(intel_crtc->unpin_work);
11123 return 0;
11124 }
11125
11126 static int intel_gen6_queue_flip(struct drm_device *dev,
11127 struct drm_crtc *crtc,
11128 struct drm_framebuffer *fb,
11129 struct drm_i915_gem_object *obj,
11130 struct drm_i915_gem_request *req,
11131 uint32_t flags)
11132 {
11133 struct intel_engine_cs *ring = req->ring;
11134 struct drm_i915_private *dev_priv = dev->dev_private;
11135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11136 uint32_t pf, pipesrc;
11137 int ret;
11138
11139 ret = intel_ring_begin(req, 4);
11140 if (ret)
11141 return ret;
11142
11143 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11144 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11145 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11146 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11147
11148 /* Contrary to the suggestions in the documentation,
11149 * "Enable Panel Fitter" does not seem to be required when page
11150 * flipping with a non-native mode, and worse causes a normal
11151 * modeset to fail.
11152 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11153 */
11154 pf = 0;
11155 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11156 intel_ring_emit(ring, pf | pipesrc);
11157
11158 intel_mark_page_flip_active(intel_crtc->unpin_work);
11159 return 0;
11160 }
11161
11162 static int intel_gen7_queue_flip(struct drm_device *dev,
11163 struct drm_crtc *crtc,
11164 struct drm_framebuffer *fb,
11165 struct drm_i915_gem_object *obj,
11166 struct drm_i915_gem_request *req,
11167 uint32_t flags)
11168 {
11169 struct intel_engine_cs *ring = req->ring;
11170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11171 uint32_t plane_bit = 0;
11172 int len, ret;
11173
11174 switch (intel_crtc->plane) {
11175 case PLANE_A:
11176 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11177 break;
11178 case PLANE_B:
11179 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11180 break;
11181 case PLANE_C:
11182 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11183 break;
11184 default:
11185 WARN_ONCE(1, "unknown plane in flip command\n");
11186 return -ENODEV;
11187 }
11188
11189 len = 4;
11190 if (ring->id == RCS) {
11191 len += 6;
11192 /*
11193 * On Gen 8, SRM is now taking an extra dword to accommodate
11194 * 48bits addresses, and we need a NOOP for the batch size to
11195 * stay even.
11196 */
11197 if (IS_GEN8(dev))
11198 len += 2;
11199 }
11200
11201 /*
11202 * BSpec MI_DISPLAY_FLIP for IVB:
11203 * "The full packet must be contained within the same cache line."
11204 *
11205 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11206 * cacheline, if we ever start emitting more commands before
11207 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11208 * then do the cacheline alignment, and finally emit the
11209 * MI_DISPLAY_FLIP.
11210 */
11211 ret = intel_ring_cacheline_align(req);
11212 if (ret)
11213 return ret;
11214
11215 ret = intel_ring_begin(req, len);
11216 if (ret)
11217 return ret;
11218
11219 /* Unmask the flip-done completion message. Note that the bspec says that
11220 * we should do this for both the BCS and RCS, and that we must not unmask
11221 * more than one flip event at any time (or ensure that one flip message
11222 * can be sent by waiting for flip-done prior to queueing new flips).
11223 * Experimentation says that BCS works despite DERRMR masking all
11224 * flip-done completion events and that unmasking all planes at once
11225 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11226 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11227 */
11228 if (ring->id == RCS) {
11229 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11230 intel_ring_emit_reg(ring, DERRMR);
11231 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11232 DERRMR_PIPEB_PRI_FLIP_DONE |
11233 DERRMR_PIPEC_PRI_FLIP_DONE));
11234 if (IS_GEN8(dev))
11235 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11236 MI_SRM_LRM_GLOBAL_GTT);
11237 else
11238 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11239 MI_SRM_LRM_GLOBAL_GTT);
11240 intel_ring_emit_reg(ring, DERRMR);
11241 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11242 if (IS_GEN8(dev)) {
11243 intel_ring_emit(ring, 0);
11244 intel_ring_emit(ring, MI_NOOP);
11245 }
11246 }
11247
11248 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11249 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11250 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11251 intel_ring_emit(ring, (MI_NOOP));
11252
11253 intel_mark_page_flip_active(intel_crtc->unpin_work);
11254 return 0;
11255 }
11256
11257 static bool use_mmio_flip(struct intel_engine_cs *ring,
11258 struct drm_i915_gem_object *obj)
11259 {
11260 /*
11261 * This is not being used for older platforms, because
11262 * non-availability of flip done interrupt forces us to use
11263 * CS flips. Older platforms derive flip done using some clever
11264 * tricks involving the flip_pending status bits and vblank irqs.
11265 * So using MMIO flips there would disrupt this mechanism.
11266 */
11267
11268 if (ring == NULL)
11269 return true;
11270
11271 if (INTEL_INFO(ring->dev)->gen < 5)
11272 return false;
11273
11274 if (i915.use_mmio_flip < 0)
11275 return false;
11276 else if (i915.use_mmio_flip > 0)
11277 return true;
11278 else if (i915.enable_execlists)
11279 return true;
11280 else if (obj->base.dma_buf &&
11281 !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11282 false))
11283 return true;
11284 else
11285 return ring != i915_gem_request_get_ring(obj->last_write_req);
11286 }
11287
11288 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11289 unsigned int rotation,
11290 struct intel_unpin_work *work)
11291 {
11292 struct drm_device *dev = intel_crtc->base.dev;
11293 struct drm_i915_private *dev_priv = dev->dev_private;
11294 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11295 const enum pipe pipe = intel_crtc->pipe;
11296 u32 ctl, stride, tile_height;
11297
11298 ctl = I915_READ(PLANE_CTL(pipe, 0));
11299 ctl &= ~PLANE_CTL_TILED_MASK;
11300 switch (fb->modifier[0]) {
11301 case DRM_FORMAT_MOD_NONE:
11302 break;
11303 case I915_FORMAT_MOD_X_TILED:
11304 ctl |= PLANE_CTL_TILED_X;
11305 break;
11306 case I915_FORMAT_MOD_Y_TILED:
11307 ctl |= PLANE_CTL_TILED_Y;
11308 break;
11309 case I915_FORMAT_MOD_Yf_TILED:
11310 ctl |= PLANE_CTL_TILED_YF;
11311 break;
11312 default:
11313 MISSING_CASE(fb->modifier[0]);
11314 }
11315
11316 /*
11317 * The stride is either expressed as a multiple of 64 bytes chunks for
11318 * linear buffers or in number of tiles for tiled buffers.
11319 */
11320 if (intel_rotation_90_or_270(rotation)) {
11321 /* stride = Surface height in tiles */
11322 tile_height = intel_tile_height(dev, fb->pixel_format,
11323 fb->modifier[0], 0);
11324 stride = DIV_ROUND_UP(fb->height, tile_height);
11325 } else {
11326 stride = fb->pitches[0] /
11327 intel_fb_stride_alignment(dev, fb->modifier[0],
11328 fb->pixel_format);
11329 }
11330
11331 /*
11332 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11333 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11334 */
11335 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11336 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11337
11338 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11339 POSTING_READ(PLANE_SURF(pipe, 0));
11340 }
11341
11342 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11343 struct intel_unpin_work *work)
11344 {
11345 struct drm_device *dev = intel_crtc->base.dev;
11346 struct drm_i915_private *dev_priv = dev->dev_private;
11347 struct intel_framebuffer *intel_fb =
11348 to_intel_framebuffer(intel_crtc->base.primary->fb);
11349 struct drm_i915_gem_object *obj = intel_fb->obj;
11350 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11351 u32 dspcntr;
11352
11353 dspcntr = I915_READ(reg);
11354
11355 if (obj->tiling_mode != I915_TILING_NONE)
11356 dspcntr |= DISPPLANE_TILED;
11357 else
11358 dspcntr &= ~DISPPLANE_TILED;
11359
11360 I915_WRITE(reg, dspcntr);
11361
11362 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11363 POSTING_READ(DSPSURF(intel_crtc->plane));
11364 }
11365
11366 /*
11367 * XXX: This is the temporary way to update the plane registers until we get
11368 * around to using the usual plane update functions for MMIO flips
11369 */
11370 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11371 {
11372 struct intel_crtc *crtc = mmio_flip->crtc;
11373 struct intel_unpin_work *work;
11374
11375 spin_lock_irq(&crtc->base.dev->event_lock);
11376 work = crtc->unpin_work;
11377 spin_unlock_irq(&crtc->base.dev->event_lock);
11378 if (work == NULL)
11379 return;
11380
11381 intel_mark_page_flip_active(work);
11382
11383 intel_pipe_update_start(crtc);
11384
11385 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11386 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11387 else
11388 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11389 ilk_do_mmio_flip(crtc, work);
11390
11391 intel_pipe_update_end(crtc);
11392 }
11393
11394 static void intel_mmio_flip_work_func(struct work_struct *work)
11395 {
11396 struct intel_mmio_flip *mmio_flip =
11397 container_of(work, struct intel_mmio_flip, work);
11398 struct intel_framebuffer *intel_fb =
11399 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11400 struct drm_i915_gem_object *obj = intel_fb->obj;
11401
11402 if (mmio_flip->req) {
11403 WARN_ON(__i915_wait_request(mmio_flip->req,
11404 mmio_flip->crtc->reset_counter,
11405 false, NULL,
11406 &mmio_flip->i915->rps.mmioflips));
11407 i915_gem_request_unreference__unlocked(mmio_flip->req);
11408 }
11409
11410 /* For framebuffer backed by dmabuf, wait for fence */
11411 if (obj->base.dma_buf)
11412 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11413 false, false,
11414 MAX_SCHEDULE_TIMEOUT) < 0);
11415
11416 intel_do_mmio_flip(mmio_flip);
11417 kfree(mmio_flip);
11418 }
11419
11420 static int intel_queue_mmio_flip(struct drm_device *dev,
11421 struct drm_crtc *crtc,
11422 struct drm_i915_gem_object *obj)
11423 {
11424 struct intel_mmio_flip *mmio_flip;
11425
11426 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11427 if (mmio_flip == NULL)
11428 return -ENOMEM;
11429
11430 mmio_flip->i915 = to_i915(dev);
11431 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11432 mmio_flip->crtc = to_intel_crtc(crtc);
11433 mmio_flip->rotation = crtc->primary->state->rotation;
11434
11435 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11436 schedule_work(&mmio_flip->work);
11437
11438 return 0;
11439 }
11440
11441 static int intel_default_queue_flip(struct drm_device *dev,
11442 struct drm_crtc *crtc,
11443 struct drm_framebuffer *fb,
11444 struct drm_i915_gem_object *obj,
11445 struct drm_i915_gem_request *req,
11446 uint32_t flags)
11447 {
11448 return -ENODEV;
11449 }
11450
11451 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11452 struct drm_crtc *crtc)
11453 {
11454 struct drm_i915_private *dev_priv = dev->dev_private;
11455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11456 struct intel_unpin_work *work = intel_crtc->unpin_work;
11457 u32 addr;
11458
11459 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11460 return true;
11461
11462 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11463 return false;
11464
11465 if (!work->enable_stall_check)
11466 return false;
11467
11468 if (work->flip_ready_vblank == 0) {
11469 if (work->flip_queued_req &&
11470 !i915_gem_request_completed(work->flip_queued_req, true))
11471 return false;
11472
11473 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11474 }
11475
11476 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11477 return false;
11478
11479 /* Potential stall - if we see that the flip has happened,
11480 * assume a missed interrupt. */
11481 if (INTEL_INFO(dev)->gen >= 4)
11482 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11483 else
11484 addr = I915_READ(DSPADDR(intel_crtc->plane));
11485
11486 /* There is a potential issue here with a false positive after a flip
11487 * to the same address. We could address this by checking for a
11488 * non-incrementing frame counter.
11489 */
11490 return addr == work->gtt_offset;
11491 }
11492
11493 void intel_check_page_flip(struct drm_device *dev, int pipe)
11494 {
11495 struct drm_i915_private *dev_priv = dev->dev_private;
11496 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11498 struct intel_unpin_work *work;
11499
11500 WARN_ON(!in_interrupt());
11501
11502 if (crtc == NULL)
11503 return;
11504
11505 spin_lock(&dev->event_lock);
11506 work = intel_crtc->unpin_work;
11507 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11508 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11509 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11510 page_flip_completed(intel_crtc);
11511 work = NULL;
11512 }
11513 if (work != NULL &&
11514 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11515 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11516 spin_unlock(&dev->event_lock);
11517 }
11518
11519 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11520 struct drm_framebuffer *fb,
11521 struct drm_pending_vblank_event *event,
11522 uint32_t page_flip_flags)
11523 {
11524 struct drm_device *dev = crtc->dev;
11525 struct drm_i915_private *dev_priv = dev->dev_private;
11526 struct drm_framebuffer *old_fb = crtc->primary->fb;
11527 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11528 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11529 struct drm_plane *primary = crtc->primary;
11530 enum pipe pipe = intel_crtc->pipe;
11531 struct intel_unpin_work *work;
11532 struct intel_engine_cs *ring;
11533 bool mmio_flip;
11534 struct drm_i915_gem_request *request = NULL;
11535 int ret;
11536
11537 /*
11538 * drm_mode_page_flip_ioctl() should already catch this, but double
11539 * check to be safe. In the future we may enable pageflipping from
11540 * a disabled primary plane.
11541 */
11542 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11543 return -EBUSY;
11544
11545 /* Can't change pixel format via MI display flips. */
11546 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11547 return -EINVAL;
11548
11549 /*
11550 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11551 * Note that pitch changes could also affect these register.
11552 */
11553 if (INTEL_INFO(dev)->gen > 3 &&
11554 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11555 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11556 return -EINVAL;
11557
11558 if (i915_terminally_wedged(&dev_priv->gpu_error))
11559 goto out_hang;
11560
11561 work = kzalloc(sizeof(*work), GFP_KERNEL);
11562 if (work == NULL)
11563 return -ENOMEM;
11564
11565 work->event = event;
11566 work->crtc = crtc;
11567 work->old_fb = old_fb;
11568 INIT_WORK(&work->work, intel_unpin_work_fn);
11569
11570 ret = drm_crtc_vblank_get(crtc);
11571 if (ret)
11572 goto free_work;
11573
11574 /* We borrow the event spin lock for protecting unpin_work */
11575 spin_lock_irq(&dev->event_lock);
11576 if (intel_crtc->unpin_work) {
11577 /* Before declaring the flip queue wedged, check if
11578 * the hardware completed the operation behind our backs.
11579 */
11580 if (__intel_pageflip_stall_check(dev, crtc)) {
11581 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11582 page_flip_completed(intel_crtc);
11583 } else {
11584 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11585 spin_unlock_irq(&dev->event_lock);
11586
11587 drm_crtc_vblank_put(crtc);
11588 kfree(work);
11589 return -EBUSY;
11590 }
11591 }
11592 intel_crtc->unpin_work = work;
11593 spin_unlock_irq(&dev->event_lock);
11594
11595 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11596 flush_workqueue(dev_priv->wq);
11597
11598 /* Reference the objects for the scheduled work. */
11599 drm_framebuffer_reference(work->old_fb);
11600 drm_gem_object_reference(&obj->base);
11601
11602 crtc->primary->fb = fb;
11603 update_state_fb(crtc->primary);
11604
11605 work->pending_flip_obj = obj;
11606
11607 ret = i915_mutex_lock_interruptible(dev);
11608 if (ret)
11609 goto cleanup;
11610
11611 atomic_inc(&intel_crtc->unpin_work_count);
11612 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11613
11614 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11615 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11616
11617 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11618 ring = &dev_priv->ring[BCS];
11619 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11620 /* vlv: DISPLAY_FLIP fails to change tiling */
11621 ring = NULL;
11622 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11623 ring = &dev_priv->ring[BCS];
11624 } else if (INTEL_INFO(dev)->gen >= 7) {
11625 ring = i915_gem_request_get_ring(obj->last_write_req);
11626 if (ring == NULL || ring->id != RCS)
11627 ring = &dev_priv->ring[BCS];
11628 } else {
11629 ring = &dev_priv->ring[RCS];
11630 }
11631
11632 mmio_flip = use_mmio_flip(ring, obj);
11633
11634 /* When using CS flips, we want to emit semaphores between rings.
11635 * However, when using mmio flips we will create a task to do the
11636 * synchronisation, so all we want here is to pin the framebuffer
11637 * into the display plane and skip any waits.
11638 */
11639 if (!mmio_flip) {
11640 ret = i915_gem_object_sync(obj, ring, &request);
11641 if (ret)
11642 goto cleanup_pending;
11643 }
11644
11645 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11646 crtc->primary->state);
11647 if (ret)
11648 goto cleanup_pending;
11649
11650 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11651 obj, 0);
11652 work->gtt_offset += intel_crtc->dspaddr_offset;
11653
11654 if (mmio_flip) {
11655 ret = intel_queue_mmio_flip(dev, crtc, obj);
11656 if (ret)
11657 goto cleanup_unpin;
11658
11659 i915_gem_request_assign(&work->flip_queued_req,
11660 obj->last_write_req);
11661 } else {
11662 if (!request) {
11663 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11664 if (ret)
11665 goto cleanup_unpin;
11666 }
11667
11668 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11669 page_flip_flags);
11670 if (ret)
11671 goto cleanup_unpin;
11672
11673 i915_gem_request_assign(&work->flip_queued_req, request);
11674 }
11675
11676 if (request)
11677 i915_add_request_no_flush(request);
11678
11679 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11680 work->enable_stall_check = true;
11681
11682 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11683 to_intel_plane(primary)->frontbuffer_bit);
11684 mutex_unlock(&dev->struct_mutex);
11685
11686 intel_fbc_deactivate(intel_crtc);
11687 intel_frontbuffer_flip_prepare(dev,
11688 to_intel_plane(primary)->frontbuffer_bit);
11689
11690 trace_i915_flip_request(intel_crtc->plane, obj);
11691
11692 return 0;
11693
11694 cleanup_unpin:
11695 intel_unpin_fb_obj(fb, crtc->primary->state);
11696 cleanup_pending:
11697 if (request)
11698 i915_gem_request_cancel(request);
11699 atomic_dec(&intel_crtc->unpin_work_count);
11700 mutex_unlock(&dev->struct_mutex);
11701 cleanup:
11702 crtc->primary->fb = old_fb;
11703 update_state_fb(crtc->primary);
11704
11705 drm_gem_object_unreference_unlocked(&obj->base);
11706 drm_framebuffer_unreference(work->old_fb);
11707
11708 spin_lock_irq(&dev->event_lock);
11709 intel_crtc->unpin_work = NULL;
11710 spin_unlock_irq(&dev->event_lock);
11711
11712 drm_crtc_vblank_put(crtc);
11713 free_work:
11714 kfree(work);
11715
11716 if (ret == -EIO) {
11717 struct drm_atomic_state *state;
11718 struct drm_plane_state *plane_state;
11719
11720 out_hang:
11721 state = drm_atomic_state_alloc(dev);
11722 if (!state)
11723 return -ENOMEM;
11724 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11725
11726 retry:
11727 plane_state = drm_atomic_get_plane_state(state, primary);
11728 ret = PTR_ERR_OR_ZERO(plane_state);
11729 if (!ret) {
11730 drm_atomic_set_fb_for_plane(plane_state, fb);
11731
11732 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11733 if (!ret)
11734 ret = drm_atomic_commit(state);
11735 }
11736
11737 if (ret == -EDEADLK) {
11738 drm_modeset_backoff(state->acquire_ctx);
11739 drm_atomic_state_clear(state);
11740 goto retry;
11741 }
11742
11743 if (ret)
11744 drm_atomic_state_free(state);
11745
11746 if (ret == 0 && event) {
11747 spin_lock_irq(&dev->event_lock);
11748 drm_send_vblank_event(dev, pipe, event);
11749 spin_unlock_irq(&dev->event_lock);
11750 }
11751 }
11752 return ret;
11753 }
11754
11755
11756 /**
11757 * intel_wm_need_update - Check whether watermarks need updating
11758 * @plane: drm plane
11759 * @state: new plane state
11760 *
11761 * Check current plane state versus the new one to determine whether
11762 * watermarks need to be recalculated.
11763 *
11764 * Returns true or false.
11765 */
11766 static bool intel_wm_need_update(struct drm_plane *plane,
11767 struct drm_plane_state *state)
11768 {
11769 struct intel_plane_state *new = to_intel_plane_state(state);
11770 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11771
11772 /* Update watermarks on tiling or size changes. */
11773 if (new->visible != cur->visible)
11774 return true;
11775
11776 if (!cur->base.fb || !new->base.fb)
11777 return false;
11778
11779 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11780 cur->base.rotation != new->base.rotation ||
11781 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11782 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11783 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11784 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11785 return true;
11786
11787 return false;
11788 }
11789
11790 static bool needs_scaling(struct intel_plane_state *state)
11791 {
11792 int src_w = drm_rect_width(&state->src) >> 16;
11793 int src_h = drm_rect_height(&state->src) >> 16;
11794 int dst_w = drm_rect_width(&state->dst);
11795 int dst_h = drm_rect_height(&state->dst);
11796
11797 return (src_w != dst_w || src_h != dst_h);
11798 }
11799
11800 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11801 struct drm_plane_state *plane_state)
11802 {
11803 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11804 struct drm_crtc *crtc = crtc_state->crtc;
11805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11806 struct drm_plane *plane = plane_state->plane;
11807 struct drm_device *dev = crtc->dev;
11808 struct drm_i915_private *dev_priv = dev->dev_private;
11809 struct intel_plane_state *old_plane_state =
11810 to_intel_plane_state(plane->state);
11811 int idx = intel_crtc->base.base.id, ret;
11812 int i = drm_plane_index(plane);
11813 bool mode_changed = needs_modeset(crtc_state);
11814 bool was_crtc_enabled = crtc->state->active;
11815 bool is_crtc_enabled = crtc_state->active;
11816 bool turn_off, turn_on, visible, was_visible;
11817 struct drm_framebuffer *fb = plane_state->fb;
11818
11819 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11820 plane->type != DRM_PLANE_TYPE_CURSOR) {
11821 ret = skl_update_scaler_plane(
11822 to_intel_crtc_state(crtc_state),
11823 to_intel_plane_state(plane_state));
11824 if (ret)
11825 return ret;
11826 }
11827
11828 was_visible = old_plane_state->visible;
11829 visible = to_intel_plane_state(plane_state)->visible;
11830
11831 if (!was_crtc_enabled && WARN_ON(was_visible))
11832 was_visible = false;
11833
11834 if (!is_crtc_enabled && WARN_ON(visible))
11835 visible = false;
11836
11837 if (!was_visible && !visible)
11838 return 0;
11839
11840 turn_off = was_visible && (!visible || mode_changed);
11841 turn_on = visible && (!was_visible || mode_changed);
11842
11843 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11844 plane->base.id, fb ? fb->base.id : -1);
11845
11846 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11847 plane->base.id, was_visible, visible,
11848 turn_off, turn_on, mode_changed);
11849
11850 if (turn_on || turn_off) {
11851 pipe_config->wm_changed = true;
11852
11853 /* must disable cxsr around plane enable/disable */
11854 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11855 if (is_crtc_enabled)
11856 intel_crtc->atomic.wait_vblank = true;
11857 pipe_config->disable_cxsr = true;
11858 }
11859 } else if (intel_wm_need_update(plane, plane_state)) {
11860 pipe_config->wm_changed = true;
11861 }
11862
11863 if (visible || was_visible)
11864 intel_crtc->atomic.fb_bits |=
11865 to_intel_plane(plane)->frontbuffer_bit;
11866
11867 switch (plane->type) {
11868 case DRM_PLANE_TYPE_PRIMARY:
11869 intel_crtc->atomic.pre_disable_primary = turn_off;
11870 intel_crtc->atomic.post_enable_primary = turn_on;
11871
11872 if (turn_off) {
11873 /*
11874 * FIXME: Actually if we will still have any other
11875 * plane enabled on the pipe we could let IPS enabled
11876 * still, but for now lets consider that when we make
11877 * primary invisible by setting DSPCNTR to 0 on
11878 * update_primary_plane function IPS needs to be
11879 * disable.
11880 */
11881 intel_crtc->atomic.disable_ips = true;
11882
11883 intel_crtc->atomic.disable_fbc = true;
11884 }
11885
11886 /*
11887 * FBC does not work on some platforms for rotated
11888 * planes, so disable it when rotation is not 0 and
11889 * update it when rotation is set back to 0.
11890 *
11891 * FIXME: This is redundant with the fbc update done in
11892 * the primary plane enable function except that that
11893 * one is done too late. We eventually need to unify
11894 * this.
11895 */
11896
11897 if (visible &&
11898 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11899 dev_priv->fbc.crtc == intel_crtc &&
11900 plane_state->rotation != BIT(DRM_ROTATE_0))
11901 intel_crtc->atomic.disable_fbc = true;
11902
11903 /*
11904 * BDW signals flip done immediately if the plane
11905 * is disabled, even if the plane enable is already
11906 * armed to occur at the next vblank :(
11907 */
11908 if (turn_on && IS_BROADWELL(dev))
11909 intel_crtc->atomic.wait_vblank = true;
11910
11911 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11912 break;
11913 case DRM_PLANE_TYPE_CURSOR:
11914 break;
11915 case DRM_PLANE_TYPE_OVERLAY:
11916 /*
11917 * WaCxSRDisabledForSpriteScaling:ivb
11918 *
11919 * cstate->update_wm was already set above, so this flag will
11920 * take effect when we commit and program watermarks.
11921 */
11922 if (IS_IVYBRIDGE(dev) &&
11923 needs_scaling(to_intel_plane_state(plane_state)) &&
11924 !needs_scaling(old_plane_state)) {
11925 to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
11926 } else if (turn_off && !mode_changed) {
11927 intel_crtc->atomic.wait_vblank = true;
11928 intel_crtc->atomic.update_sprite_watermarks |=
11929 1 << i;
11930 }
11931
11932 break;
11933 }
11934 return 0;
11935 }
11936
11937 static bool encoders_cloneable(const struct intel_encoder *a,
11938 const struct intel_encoder *b)
11939 {
11940 /* masks could be asymmetric, so check both ways */
11941 return a == b || (a->cloneable & (1 << b->type) &&
11942 b->cloneable & (1 << a->type));
11943 }
11944
11945 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11946 struct intel_crtc *crtc,
11947 struct intel_encoder *encoder)
11948 {
11949 struct intel_encoder *source_encoder;
11950 struct drm_connector *connector;
11951 struct drm_connector_state *connector_state;
11952 int i;
11953
11954 for_each_connector_in_state(state, connector, connector_state, i) {
11955 if (connector_state->crtc != &crtc->base)
11956 continue;
11957
11958 source_encoder =
11959 to_intel_encoder(connector_state->best_encoder);
11960 if (!encoders_cloneable(encoder, source_encoder))
11961 return false;
11962 }
11963
11964 return true;
11965 }
11966
11967 static bool check_encoder_cloning(struct drm_atomic_state *state,
11968 struct intel_crtc *crtc)
11969 {
11970 struct intel_encoder *encoder;
11971 struct drm_connector *connector;
11972 struct drm_connector_state *connector_state;
11973 int i;
11974
11975 for_each_connector_in_state(state, connector, connector_state, i) {
11976 if (connector_state->crtc != &crtc->base)
11977 continue;
11978
11979 encoder = to_intel_encoder(connector_state->best_encoder);
11980 if (!check_single_encoder_cloning(state, crtc, encoder))
11981 return false;
11982 }
11983
11984 return true;
11985 }
11986
11987 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11988 struct drm_crtc_state *crtc_state)
11989 {
11990 struct drm_device *dev = crtc->dev;
11991 struct drm_i915_private *dev_priv = dev->dev_private;
11992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11993 struct intel_crtc_state *pipe_config =
11994 to_intel_crtc_state(crtc_state);
11995 struct drm_atomic_state *state = crtc_state->state;
11996 int ret;
11997 bool mode_changed = needs_modeset(crtc_state);
11998
11999 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
12000 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12001 return -EINVAL;
12002 }
12003
12004 if (mode_changed && !crtc_state->active)
12005 pipe_config->wm_changed = true;
12006
12007 if (mode_changed && crtc_state->enable &&
12008 dev_priv->display.crtc_compute_clock &&
12009 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
12010 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12011 pipe_config);
12012 if (ret)
12013 return ret;
12014 }
12015
12016 ret = 0;
12017 if (dev_priv->display.compute_pipe_wm) {
12018 ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
12019 if (ret)
12020 return ret;
12021 }
12022
12023 if (INTEL_INFO(dev)->gen >= 9) {
12024 if (mode_changed)
12025 ret = skl_update_scaler_crtc(pipe_config);
12026
12027 if (!ret)
12028 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12029 pipe_config);
12030 }
12031
12032 return ret;
12033 }
12034
12035 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12036 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12037 .load_lut = intel_crtc_load_lut,
12038 .atomic_begin = intel_begin_crtc_commit,
12039 .atomic_flush = intel_finish_crtc_commit,
12040 .atomic_check = intel_crtc_atomic_check,
12041 };
12042
12043 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12044 {
12045 struct intel_connector *connector;
12046
12047 for_each_intel_connector(dev, connector) {
12048 if (connector->base.encoder) {
12049 connector->base.state->best_encoder =
12050 connector->base.encoder;
12051 connector->base.state->crtc =
12052 connector->base.encoder->crtc;
12053 } else {
12054 connector->base.state->best_encoder = NULL;
12055 connector->base.state->crtc = NULL;
12056 }
12057 }
12058 }
12059
12060 static void
12061 connected_sink_compute_bpp(struct intel_connector *connector,
12062 struct intel_crtc_state *pipe_config)
12063 {
12064 int bpp = pipe_config->pipe_bpp;
12065
12066 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12067 connector->base.base.id,
12068 connector->base.name);
12069
12070 /* Don't use an invalid EDID bpc value */
12071 if (connector->base.display_info.bpc &&
12072 connector->base.display_info.bpc * 3 < bpp) {
12073 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12074 bpp, connector->base.display_info.bpc*3);
12075 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12076 }
12077
12078 /* Clamp bpp to 8 on screens without EDID 1.4 */
12079 if (connector->base.display_info.bpc == 0 && bpp > 24) {
12080 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12081 bpp);
12082 pipe_config->pipe_bpp = 24;
12083 }
12084 }
12085
12086 static int
12087 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12088 struct intel_crtc_state *pipe_config)
12089 {
12090 struct drm_device *dev = crtc->base.dev;
12091 struct drm_atomic_state *state;
12092 struct drm_connector *connector;
12093 struct drm_connector_state *connector_state;
12094 int bpp, i;
12095
12096 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12097 bpp = 10*3;
12098 else if (INTEL_INFO(dev)->gen >= 5)
12099 bpp = 12*3;
12100 else
12101 bpp = 8*3;
12102
12103
12104 pipe_config->pipe_bpp = bpp;
12105
12106 state = pipe_config->base.state;
12107
12108 /* Clamp display bpp to EDID value */
12109 for_each_connector_in_state(state, connector, connector_state, i) {
12110 if (connector_state->crtc != &crtc->base)
12111 continue;
12112
12113 connected_sink_compute_bpp(to_intel_connector(connector),
12114 pipe_config);
12115 }
12116
12117 return bpp;
12118 }
12119
12120 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12121 {
12122 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12123 "type: 0x%x flags: 0x%x\n",
12124 mode->crtc_clock,
12125 mode->crtc_hdisplay, mode->crtc_hsync_start,
12126 mode->crtc_hsync_end, mode->crtc_htotal,
12127 mode->crtc_vdisplay, mode->crtc_vsync_start,
12128 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12129 }
12130
12131 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12132 struct intel_crtc_state *pipe_config,
12133 const char *context)
12134 {
12135 struct drm_device *dev = crtc->base.dev;
12136 struct drm_plane *plane;
12137 struct intel_plane *intel_plane;
12138 struct intel_plane_state *state;
12139 struct drm_framebuffer *fb;
12140
12141 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12142 context, pipe_config, pipe_name(crtc->pipe));
12143
12144 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12145 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12146 pipe_config->pipe_bpp, pipe_config->dither);
12147 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12148 pipe_config->has_pch_encoder,
12149 pipe_config->fdi_lanes,
12150 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12151 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12152 pipe_config->fdi_m_n.tu);
12153 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12154 pipe_config->has_dp_encoder,
12155 pipe_config->lane_count,
12156 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12157 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12158 pipe_config->dp_m_n.tu);
12159
12160 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12161 pipe_config->has_dp_encoder,
12162 pipe_config->lane_count,
12163 pipe_config->dp_m2_n2.gmch_m,
12164 pipe_config->dp_m2_n2.gmch_n,
12165 pipe_config->dp_m2_n2.link_m,
12166 pipe_config->dp_m2_n2.link_n,
12167 pipe_config->dp_m2_n2.tu);
12168
12169 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12170 pipe_config->has_audio,
12171 pipe_config->has_infoframe);
12172
12173 DRM_DEBUG_KMS("requested mode:\n");
12174 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12175 DRM_DEBUG_KMS("adjusted mode:\n");
12176 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12177 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12178 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12179 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12180 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12181 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12182 crtc->num_scalers,
12183 pipe_config->scaler_state.scaler_users,
12184 pipe_config->scaler_state.scaler_id);
12185 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12186 pipe_config->gmch_pfit.control,
12187 pipe_config->gmch_pfit.pgm_ratios,
12188 pipe_config->gmch_pfit.lvds_border_bits);
12189 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12190 pipe_config->pch_pfit.pos,
12191 pipe_config->pch_pfit.size,
12192 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12193 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12194 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12195
12196 if (IS_BROXTON(dev)) {
12197 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12198 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12199 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12200 pipe_config->ddi_pll_sel,
12201 pipe_config->dpll_hw_state.ebb0,
12202 pipe_config->dpll_hw_state.ebb4,
12203 pipe_config->dpll_hw_state.pll0,
12204 pipe_config->dpll_hw_state.pll1,
12205 pipe_config->dpll_hw_state.pll2,
12206 pipe_config->dpll_hw_state.pll3,
12207 pipe_config->dpll_hw_state.pll6,
12208 pipe_config->dpll_hw_state.pll8,
12209 pipe_config->dpll_hw_state.pll9,
12210 pipe_config->dpll_hw_state.pll10,
12211 pipe_config->dpll_hw_state.pcsdw12);
12212 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12213 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12214 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12215 pipe_config->ddi_pll_sel,
12216 pipe_config->dpll_hw_state.ctrl1,
12217 pipe_config->dpll_hw_state.cfgcr1,
12218 pipe_config->dpll_hw_state.cfgcr2);
12219 } else if (HAS_DDI(dev)) {
12220 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12221 pipe_config->ddi_pll_sel,
12222 pipe_config->dpll_hw_state.wrpll,
12223 pipe_config->dpll_hw_state.spll);
12224 } else {
12225 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12226 "fp0: 0x%x, fp1: 0x%x\n",
12227 pipe_config->dpll_hw_state.dpll,
12228 pipe_config->dpll_hw_state.dpll_md,
12229 pipe_config->dpll_hw_state.fp0,
12230 pipe_config->dpll_hw_state.fp1);
12231 }
12232
12233 DRM_DEBUG_KMS("planes on this crtc\n");
12234 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12235 intel_plane = to_intel_plane(plane);
12236 if (intel_plane->pipe != crtc->pipe)
12237 continue;
12238
12239 state = to_intel_plane_state(plane->state);
12240 fb = state->base.fb;
12241 if (!fb) {
12242 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12243 "disabled, scaler_id = %d\n",
12244 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12245 plane->base.id, intel_plane->pipe,
12246 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12247 drm_plane_index(plane), state->scaler_id);
12248 continue;
12249 }
12250
12251 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12252 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12253 plane->base.id, intel_plane->pipe,
12254 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12255 drm_plane_index(plane));
12256 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12257 fb->base.id, fb->width, fb->height, fb->pixel_format);
12258 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12259 state->scaler_id,
12260 state->src.x1 >> 16, state->src.y1 >> 16,
12261 drm_rect_width(&state->src) >> 16,
12262 drm_rect_height(&state->src) >> 16,
12263 state->dst.x1, state->dst.y1,
12264 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12265 }
12266 }
12267
12268 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12269 {
12270 struct drm_device *dev = state->dev;
12271 struct drm_connector *connector;
12272 unsigned int used_ports = 0;
12273
12274 /*
12275 * Walk the connector list instead of the encoder
12276 * list to detect the problem on ddi platforms
12277 * where there's just one encoder per digital port.
12278 */
12279 drm_for_each_connector(connector, dev) {
12280 struct drm_connector_state *connector_state;
12281 struct intel_encoder *encoder;
12282
12283 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12284 if (!connector_state)
12285 connector_state = connector->state;
12286
12287 if (!connector_state->best_encoder)
12288 continue;
12289
12290 encoder = to_intel_encoder(connector_state->best_encoder);
12291
12292 WARN_ON(!connector_state->crtc);
12293
12294 switch (encoder->type) {
12295 unsigned int port_mask;
12296 case INTEL_OUTPUT_UNKNOWN:
12297 if (WARN_ON(!HAS_DDI(dev)))
12298 break;
12299 case INTEL_OUTPUT_DISPLAYPORT:
12300 case INTEL_OUTPUT_HDMI:
12301 case INTEL_OUTPUT_EDP:
12302 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12303
12304 /* the same port mustn't appear more than once */
12305 if (used_ports & port_mask)
12306 return false;
12307
12308 used_ports |= port_mask;
12309 default:
12310 break;
12311 }
12312 }
12313
12314 return true;
12315 }
12316
12317 static void
12318 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12319 {
12320 struct drm_crtc_state tmp_state;
12321 struct intel_crtc_scaler_state scaler_state;
12322 struct intel_dpll_hw_state dpll_hw_state;
12323 enum intel_dpll_id shared_dpll;
12324 uint32_t ddi_pll_sel;
12325 bool force_thru;
12326
12327 /* FIXME: before the switch to atomic started, a new pipe_config was
12328 * kzalloc'd. Code that depends on any field being zero should be
12329 * fixed, so that the crtc_state can be safely duplicated. For now,
12330 * only fields that are know to not cause problems are preserved. */
12331
12332 tmp_state = crtc_state->base;
12333 scaler_state = crtc_state->scaler_state;
12334 shared_dpll = crtc_state->shared_dpll;
12335 dpll_hw_state = crtc_state->dpll_hw_state;
12336 ddi_pll_sel = crtc_state->ddi_pll_sel;
12337 force_thru = crtc_state->pch_pfit.force_thru;
12338
12339 memset(crtc_state, 0, sizeof *crtc_state);
12340
12341 crtc_state->base = tmp_state;
12342 crtc_state->scaler_state = scaler_state;
12343 crtc_state->shared_dpll = shared_dpll;
12344 crtc_state->dpll_hw_state = dpll_hw_state;
12345 crtc_state->ddi_pll_sel = ddi_pll_sel;
12346 crtc_state->pch_pfit.force_thru = force_thru;
12347 }
12348
12349 static int
12350 intel_modeset_pipe_config(struct drm_crtc *crtc,
12351 struct intel_crtc_state *pipe_config)
12352 {
12353 struct drm_atomic_state *state = pipe_config->base.state;
12354 struct intel_encoder *encoder;
12355 struct drm_connector *connector;
12356 struct drm_connector_state *connector_state;
12357 int base_bpp, ret = -EINVAL;
12358 int i;
12359 bool retry = true;
12360
12361 clear_intel_crtc_state(pipe_config);
12362
12363 pipe_config->cpu_transcoder =
12364 (enum transcoder) to_intel_crtc(crtc)->pipe;
12365
12366 /*
12367 * Sanitize sync polarity flags based on requested ones. If neither
12368 * positive or negative polarity is requested, treat this as meaning
12369 * negative polarity.
12370 */
12371 if (!(pipe_config->base.adjusted_mode.flags &
12372 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12373 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12374
12375 if (!(pipe_config->base.adjusted_mode.flags &
12376 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12377 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12378
12379 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12380 pipe_config);
12381 if (base_bpp < 0)
12382 goto fail;
12383
12384 /*
12385 * Determine the real pipe dimensions. Note that stereo modes can
12386 * increase the actual pipe size due to the frame doubling and
12387 * insertion of additional space for blanks between the frame. This
12388 * is stored in the crtc timings. We use the requested mode to do this
12389 * computation to clearly distinguish it from the adjusted mode, which
12390 * can be changed by the connectors in the below retry loop.
12391 */
12392 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12393 &pipe_config->pipe_src_w,
12394 &pipe_config->pipe_src_h);
12395
12396 encoder_retry:
12397 /* Ensure the port clock defaults are reset when retrying. */
12398 pipe_config->port_clock = 0;
12399 pipe_config->pixel_multiplier = 1;
12400
12401 /* Fill in default crtc timings, allow encoders to overwrite them. */
12402 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12403 CRTC_STEREO_DOUBLE);
12404
12405 /* Pass our mode to the connectors and the CRTC to give them a chance to
12406 * adjust it according to limitations or connector properties, and also
12407 * a chance to reject the mode entirely.
12408 */
12409 for_each_connector_in_state(state, connector, connector_state, i) {
12410 if (connector_state->crtc != crtc)
12411 continue;
12412
12413 encoder = to_intel_encoder(connector_state->best_encoder);
12414
12415 if (!(encoder->compute_config(encoder, pipe_config))) {
12416 DRM_DEBUG_KMS("Encoder config failure\n");
12417 goto fail;
12418 }
12419 }
12420
12421 /* Set default port clock if not overwritten by the encoder. Needs to be
12422 * done afterwards in case the encoder adjusts the mode. */
12423 if (!pipe_config->port_clock)
12424 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12425 * pipe_config->pixel_multiplier;
12426
12427 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12428 if (ret < 0) {
12429 DRM_DEBUG_KMS("CRTC fixup failed\n");
12430 goto fail;
12431 }
12432
12433 if (ret == RETRY) {
12434 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12435 ret = -EINVAL;
12436 goto fail;
12437 }
12438
12439 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12440 retry = false;
12441 goto encoder_retry;
12442 }
12443
12444 /* Dithering seems to not pass-through bits correctly when it should, so
12445 * only enable it on 6bpc panels. */
12446 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12447 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12448 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12449
12450 fail:
12451 return ret;
12452 }
12453
12454 static void
12455 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12456 {
12457 struct drm_crtc *crtc;
12458 struct drm_crtc_state *crtc_state;
12459 int i;
12460
12461 /* Double check state. */
12462 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12463 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12464
12465 /* Update hwmode for vblank functions */
12466 if (crtc->state->active)
12467 crtc->hwmode = crtc->state->adjusted_mode;
12468 else
12469 crtc->hwmode.crtc_clock = 0;
12470
12471 /*
12472 * Update legacy state to satisfy fbc code. This can
12473 * be removed when fbc uses the atomic state.
12474 */
12475 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12476 struct drm_plane_state *plane_state = crtc->primary->state;
12477
12478 crtc->primary->fb = plane_state->fb;
12479 crtc->x = plane_state->src_x >> 16;
12480 crtc->y = plane_state->src_y >> 16;
12481 }
12482 }
12483 }
12484
12485 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12486 {
12487 int diff;
12488
12489 if (clock1 == clock2)
12490 return true;
12491
12492 if (!clock1 || !clock2)
12493 return false;
12494
12495 diff = abs(clock1 - clock2);
12496
12497 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12498 return true;
12499
12500 return false;
12501 }
12502
12503 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12504 list_for_each_entry((intel_crtc), \
12505 &(dev)->mode_config.crtc_list, \
12506 base.head) \
12507 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12508
12509 static bool
12510 intel_compare_m_n(unsigned int m, unsigned int n,
12511 unsigned int m2, unsigned int n2,
12512 bool exact)
12513 {
12514 if (m == m2 && n == n2)
12515 return true;
12516
12517 if (exact || !m || !n || !m2 || !n2)
12518 return false;
12519
12520 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12521
12522 if (m > m2) {
12523 while (m > m2) {
12524 m2 <<= 1;
12525 n2 <<= 1;
12526 }
12527 } else if (m < m2) {
12528 while (m < m2) {
12529 m <<= 1;
12530 n <<= 1;
12531 }
12532 }
12533
12534 return m == m2 && n == n2;
12535 }
12536
12537 static bool
12538 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12539 struct intel_link_m_n *m2_n2,
12540 bool adjust)
12541 {
12542 if (m_n->tu == m2_n2->tu &&
12543 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12544 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12545 intel_compare_m_n(m_n->link_m, m_n->link_n,
12546 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12547 if (adjust)
12548 *m2_n2 = *m_n;
12549
12550 return true;
12551 }
12552
12553 return false;
12554 }
12555
12556 static bool
12557 intel_pipe_config_compare(struct drm_device *dev,
12558 struct intel_crtc_state *current_config,
12559 struct intel_crtc_state *pipe_config,
12560 bool adjust)
12561 {
12562 bool ret = true;
12563
12564 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12565 do { \
12566 if (!adjust) \
12567 DRM_ERROR(fmt, ##__VA_ARGS__); \
12568 else \
12569 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12570 } while (0)
12571
12572 #define PIPE_CONF_CHECK_X(name) \
12573 if (current_config->name != pipe_config->name) { \
12574 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12575 "(expected 0x%08x, found 0x%08x)\n", \
12576 current_config->name, \
12577 pipe_config->name); \
12578 ret = false; \
12579 }
12580
12581 #define PIPE_CONF_CHECK_I(name) \
12582 if (current_config->name != pipe_config->name) { \
12583 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12584 "(expected %i, found %i)\n", \
12585 current_config->name, \
12586 pipe_config->name); \
12587 ret = false; \
12588 }
12589
12590 #define PIPE_CONF_CHECK_M_N(name) \
12591 if (!intel_compare_link_m_n(&current_config->name, \
12592 &pipe_config->name,\
12593 adjust)) { \
12594 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12595 "(expected tu %i gmch %i/%i link %i/%i, " \
12596 "found tu %i, gmch %i/%i link %i/%i)\n", \
12597 current_config->name.tu, \
12598 current_config->name.gmch_m, \
12599 current_config->name.gmch_n, \
12600 current_config->name.link_m, \
12601 current_config->name.link_n, \
12602 pipe_config->name.tu, \
12603 pipe_config->name.gmch_m, \
12604 pipe_config->name.gmch_n, \
12605 pipe_config->name.link_m, \
12606 pipe_config->name.link_n); \
12607 ret = false; \
12608 }
12609
12610 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12611 if (!intel_compare_link_m_n(&current_config->name, \
12612 &pipe_config->name, adjust) && \
12613 !intel_compare_link_m_n(&current_config->alt_name, \
12614 &pipe_config->name, adjust)) { \
12615 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12616 "(expected tu %i gmch %i/%i link %i/%i, " \
12617 "or tu %i gmch %i/%i link %i/%i, " \
12618 "found tu %i, gmch %i/%i link %i/%i)\n", \
12619 current_config->name.tu, \
12620 current_config->name.gmch_m, \
12621 current_config->name.gmch_n, \
12622 current_config->name.link_m, \
12623 current_config->name.link_n, \
12624 current_config->alt_name.tu, \
12625 current_config->alt_name.gmch_m, \
12626 current_config->alt_name.gmch_n, \
12627 current_config->alt_name.link_m, \
12628 current_config->alt_name.link_n, \
12629 pipe_config->name.tu, \
12630 pipe_config->name.gmch_m, \
12631 pipe_config->name.gmch_n, \
12632 pipe_config->name.link_m, \
12633 pipe_config->name.link_n); \
12634 ret = false; \
12635 }
12636
12637 /* This is required for BDW+ where there is only one set of registers for
12638 * switching between high and low RR.
12639 * This macro can be used whenever a comparison has to be made between one
12640 * hw state and multiple sw state variables.
12641 */
12642 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12643 if ((current_config->name != pipe_config->name) && \
12644 (current_config->alt_name != pipe_config->name)) { \
12645 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12646 "(expected %i or %i, found %i)\n", \
12647 current_config->name, \
12648 current_config->alt_name, \
12649 pipe_config->name); \
12650 ret = false; \
12651 }
12652
12653 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12654 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12655 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12656 "(expected %i, found %i)\n", \
12657 current_config->name & (mask), \
12658 pipe_config->name & (mask)); \
12659 ret = false; \
12660 }
12661
12662 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12663 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12664 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12665 "(expected %i, found %i)\n", \
12666 current_config->name, \
12667 pipe_config->name); \
12668 ret = false; \
12669 }
12670
12671 #define PIPE_CONF_QUIRK(quirk) \
12672 ((current_config->quirks | pipe_config->quirks) & (quirk))
12673
12674 PIPE_CONF_CHECK_I(cpu_transcoder);
12675
12676 PIPE_CONF_CHECK_I(has_pch_encoder);
12677 PIPE_CONF_CHECK_I(fdi_lanes);
12678 PIPE_CONF_CHECK_M_N(fdi_m_n);
12679
12680 PIPE_CONF_CHECK_I(has_dp_encoder);
12681 PIPE_CONF_CHECK_I(lane_count);
12682
12683 if (INTEL_INFO(dev)->gen < 8) {
12684 PIPE_CONF_CHECK_M_N(dp_m_n);
12685
12686 if (current_config->has_drrs)
12687 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12688 } else
12689 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12690
12691 PIPE_CONF_CHECK_I(has_dsi_encoder);
12692
12693 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12694 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12695 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12696 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12697 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12698 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12699
12700 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12701 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12702 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12703 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12704 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12705 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12706
12707 PIPE_CONF_CHECK_I(pixel_multiplier);
12708 PIPE_CONF_CHECK_I(has_hdmi_sink);
12709 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12710 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12711 PIPE_CONF_CHECK_I(limited_color_range);
12712 PIPE_CONF_CHECK_I(has_infoframe);
12713
12714 PIPE_CONF_CHECK_I(has_audio);
12715
12716 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12717 DRM_MODE_FLAG_INTERLACE);
12718
12719 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12720 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12721 DRM_MODE_FLAG_PHSYNC);
12722 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12723 DRM_MODE_FLAG_NHSYNC);
12724 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12725 DRM_MODE_FLAG_PVSYNC);
12726 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12727 DRM_MODE_FLAG_NVSYNC);
12728 }
12729
12730 PIPE_CONF_CHECK_X(gmch_pfit.control);
12731 /* pfit ratios are autocomputed by the hw on gen4+ */
12732 if (INTEL_INFO(dev)->gen < 4)
12733 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12734 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12735
12736 if (!adjust) {
12737 PIPE_CONF_CHECK_I(pipe_src_w);
12738 PIPE_CONF_CHECK_I(pipe_src_h);
12739
12740 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12741 if (current_config->pch_pfit.enabled) {
12742 PIPE_CONF_CHECK_X(pch_pfit.pos);
12743 PIPE_CONF_CHECK_X(pch_pfit.size);
12744 }
12745
12746 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12747 }
12748
12749 /* BDW+ don't expose a synchronous way to read the state */
12750 if (IS_HASWELL(dev))
12751 PIPE_CONF_CHECK_I(ips_enabled);
12752
12753 PIPE_CONF_CHECK_I(double_wide);
12754
12755 PIPE_CONF_CHECK_X(ddi_pll_sel);
12756
12757 PIPE_CONF_CHECK_I(shared_dpll);
12758 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12759 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12760 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12761 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12762 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12763 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12764 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12765 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12766 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12767
12768 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12769 PIPE_CONF_CHECK_I(pipe_bpp);
12770
12771 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12772 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12773
12774 #undef PIPE_CONF_CHECK_X
12775 #undef PIPE_CONF_CHECK_I
12776 #undef PIPE_CONF_CHECK_I_ALT
12777 #undef PIPE_CONF_CHECK_FLAGS
12778 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12779 #undef PIPE_CONF_QUIRK
12780 #undef INTEL_ERR_OR_DBG_KMS
12781
12782 return ret;
12783 }
12784
12785 static void check_wm_state(struct drm_device *dev)
12786 {
12787 struct drm_i915_private *dev_priv = dev->dev_private;
12788 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12789 struct intel_crtc *intel_crtc;
12790 int plane;
12791
12792 if (INTEL_INFO(dev)->gen < 9)
12793 return;
12794
12795 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12796 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12797
12798 for_each_intel_crtc(dev, intel_crtc) {
12799 struct skl_ddb_entry *hw_entry, *sw_entry;
12800 const enum pipe pipe = intel_crtc->pipe;
12801
12802 if (!intel_crtc->active)
12803 continue;
12804
12805 /* planes */
12806 for_each_plane(dev_priv, pipe, plane) {
12807 hw_entry = &hw_ddb.plane[pipe][plane];
12808 sw_entry = &sw_ddb->plane[pipe][plane];
12809
12810 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12811 continue;
12812
12813 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12814 "(expected (%u,%u), found (%u,%u))\n",
12815 pipe_name(pipe), plane + 1,
12816 sw_entry->start, sw_entry->end,
12817 hw_entry->start, hw_entry->end);
12818 }
12819
12820 /* cursor */
12821 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12822 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12823
12824 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12825 continue;
12826
12827 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12828 "(expected (%u,%u), found (%u,%u))\n",
12829 pipe_name(pipe),
12830 sw_entry->start, sw_entry->end,
12831 hw_entry->start, hw_entry->end);
12832 }
12833 }
12834
12835 static void
12836 check_connector_state(struct drm_device *dev,
12837 struct drm_atomic_state *old_state)
12838 {
12839 struct drm_connector_state *old_conn_state;
12840 struct drm_connector *connector;
12841 int i;
12842
12843 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12844 struct drm_encoder *encoder = connector->encoder;
12845 struct drm_connector_state *state = connector->state;
12846
12847 /* This also checks the encoder/connector hw state with the
12848 * ->get_hw_state callbacks. */
12849 intel_connector_check_state(to_intel_connector(connector));
12850
12851 I915_STATE_WARN(state->best_encoder != encoder,
12852 "connector's atomic encoder doesn't match legacy encoder\n");
12853 }
12854 }
12855
12856 static void
12857 check_encoder_state(struct drm_device *dev)
12858 {
12859 struct intel_encoder *encoder;
12860 struct intel_connector *connector;
12861
12862 for_each_intel_encoder(dev, encoder) {
12863 bool enabled = false;
12864 enum pipe pipe;
12865
12866 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12867 encoder->base.base.id,
12868 encoder->base.name);
12869
12870 for_each_intel_connector(dev, connector) {
12871 if (connector->base.state->best_encoder != &encoder->base)
12872 continue;
12873 enabled = true;
12874
12875 I915_STATE_WARN(connector->base.state->crtc !=
12876 encoder->base.crtc,
12877 "connector's crtc doesn't match encoder crtc\n");
12878 }
12879
12880 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12881 "encoder's enabled state mismatch "
12882 "(expected %i, found %i)\n",
12883 !!encoder->base.crtc, enabled);
12884
12885 if (!encoder->base.crtc) {
12886 bool active;
12887
12888 active = encoder->get_hw_state(encoder, &pipe);
12889 I915_STATE_WARN(active,
12890 "encoder detached but still enabled on pipe %c.\n",
12891 pipe_name(pipe));
12892 }
12893 }
12894 }
12895
12896 static void
12897 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12898 {
12899 struct drm_i915_private *dev_priv = dev->dev_private;
12900 struct intel_encoder *encoder;
12901 struct drm_crtc_state *old_crtc_state;
12902 struct drm_crtc *crtc;
12903 int i;
12904
12905 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12906 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12907 struct intel_crtc_state *pipe_config, *sw_config;
12908 bool active;
12909
12910 if (!needs_modeset(crtc->state) &&
12911 !to_intel_crtc_state(crtc->state)->update_pipe)
12912 continue;
12913
12914 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12915 pipe_config = to_intel_crtc_state(old_crtc_state);
12916 memset(pipe_config, 0, sizeof(*pipe_config));
12917 pipe_config->base.crtc = crtc;
12918 pipe_config->base.state = old_state;
12919
12920 DRM_DEBUG_KMS("[CRTC:%d]\n",
12921 crtc->base.id);
12922
12923 active = dev_priv->display.get_pipe_config(intel_crtc,
12924 pipe_config);
12925
12926 /* hw state is inconsistent with the pipe quirk */
12927 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12928 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12929 active = crtc->state->active;
12930
12931 I915_STATE_WARN(crtc->state->active != active,
12932 "crtc active state doesn't match with hw state "
12933 "(expected %i, found %i)\n", crtc->state->active, active);
12934
12935 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12936 "transitional active state does not match atomic hw state "
12937 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12938
12939 for_each_encoder_on_crtc(dev, crtc, encoder) {
12940 enum pipe pipe;
12941
12942 active = encoder->get_hw_state(encoder, &pipe);
12943 I915_STATE_WARN(active != crtc->state->active,
12944 "[ENCODER:%i] active %i with crtc active %i\n",
12945 encoder->base.base.id, active, crtc->state->active);
12946
12947 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12948 "Encoder connected to wrong pipe %c\n",
12949 pipe_name(pipe));
12950
12951 if (active)
12952 encoder->get_config(encoder, pipe_config);
12953 }
12954
12955 if (!crtc->state->active)
12956 continue;
12957
12958 sw_config = to_intel_crtc_state(crtc->state);
12959 if (!intel_pipe_config_compare(dev, sw_config,
12960 pipe_config, false)) {
12961 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12962 intel_dump_pipe_config(intel_crtc, pipe_config,
12963 "[hw state]");
12964 intel_dump_pipe_config(intel_crtc, sw_config,
12965 "[sw state]");
12966 }
12967 }
12968 }
12969
12970 static void
12971 check_shared_dpll_state(struct drm_device *dev)
12972 {
12973 struct drm_i915_private *dev_priv = dev->dev_private;
12974 struct intel_crtc *crtc;
12975 struct intel_dpll_hw_state dpll_hw_state;
12976 int i;
12977
12978 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12979 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12980 int enabled_crtcs = 0, active_crtcs = 0;
12981 bool active;
12982
12983 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12984
12985 DRM_DEBUG_KMS("%s\n", pll->name);
12986
12987 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12988
12989 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12990 "more active pll users than references: %i vs %i\n",
12991 pll->active, hweight32(pll->config.crtc_mask));
12992 I915_STATE_WARN(pll->active && !pll->on,
12993 "pll in active use but not on in sw tracking\n");
12994 I915_STATE_WARN(pll->on && !pll->active,
12995 "pll in on but not on in use in sw tracking\n");
12996 I915_STATE_WARN(pll->on != active,
12997 "pll on state mismatch (expected %i, found %i)\n",
12998 pll->on, active);
12999
13000 for_each_intel_crtc(dev, crtc) {
13001 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
13002 enabled_crtcs++;
13003 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13004 active_crtcs++;
13005 }
13006 I915_STATE_WARN(pll->active != active_crtcs,
13007 "pll active crtcs mismatch (expected %i, found %i)\n",
13008 pll->active, active_crtcs);
13009 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
13010 "pll enabled crtcs mismatch (expected %i, found %i)\n",
13011 hweight32(pll->config.crtc_mask), enabled_crtcs);
13012
13013 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
13014 sizeof(dpll_hw_state)),
13015 "pll hw state mismatch\n");
13016 }
13017 }
13018
13019 static void
13020 intel_modeset_check_state(struct drm_device *dev,
13021 struct drm_atomic_state *old_state)
13022 {
13023 check_wm_state(dev);
13024 check_connector_state(dev, old_state);
13025 check_encoder_state(dev);
13026 check_crtc_state(dev, old_state);
13027 check_shared_dpll_state(dev);
13028 }
13029
13030 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
13031 int dotclock)
13032 {
13033 /*
13034 * FDI already provided one idea for the dotclock.
13035 * Yell if the encoder disagrees.
13036 */
13037 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
13038 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13039 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
13040 }
13041
13042 static void update_scanline_offset(struct intel_crtc *crtc)
13043 {
13044 struct drm_device *dev = crtc->base.dev;
13045
13046 /*
13047 * The scanline counter increments at the leading edge of hsync.
13048 *
13049 * On most platforms it starts counting from vtotal-1 on the
13050 * first active line. That means the scanline counter value is
13051 * always one less than what we would expect. Ie. just after
13052 * start of vblank, which also occurs at start of hsync (on the
13053 * last active line), the scanline counter will read vblank_start-1.
13054 *
13055 * On gen2 the scanline counter starts counting from 1 instead
13056 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13057 * to keep the value positive), instead of adding one.
13058 *
13059 * On HSW+ the behaviour of the scanline counter depends on the output
13060 * type. For DP ports it behaves like most other platforms, but on HDMI
13061 * there's an extra 1 line difference. So we need to add two instead of
13062 * one to the value.
13063 */
13064 if (IS_GEN2(dev)) {
13065 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13066 int vtotal;
13067
13068 vtotal = adjusted_mode->crtc_vtotal;
13069 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13070 vtotal /= 2;
13071
13072 crtc->scanline_offset = vtotal - 1;
13073 } else if (HAS_DDI(dev) &&
13074 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13075 crtc->scanline_offset = 2;
13076 } else
13077 crtc->scanline_offset = 1;
13078 }
13079
13080 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13081 {
13082 struct drm_device *dev = state->dev;
13083 struct drm_i915_private *dev_priv = to_i915(dev);
13084 struct intel_shared_dpll_config *shared_dpll = NULL;
13085 struct intel_crtc *intel_crtc;
13086 struct intel_crtc_state *intel_crtc_state;
13087 struct drm_crtc *crtc;
13088 struct drm_crtc_state *crtc_state;
13089 int i;
13090
13091 if (!dev_priv->display.crtc_compute_clock)
13092 return;
13093
13094 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13095 int dpll;
13096
13097 intel_crtc = to_intel_crtc(crtc);
13098 intel_crtc_state = to_intel_crtc_state(crtc_state);
13099 dpll = intel_crtc_state->shared_dpll;
13100
13101 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
13102 continue;
13103
13104 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
13105
13106 if (!shared_dpll)
13107 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13108
13109 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13110 }
13111 }
13112
13113 /*
13114 * This implements the workaround described in the "notes" section of the mode
13115 * set sequence documentation. When going from no pipes or single pipe to
13116 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13117 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13118 */
13119 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13120 {
13121 struct drm_crtc_state *crtc_state;
13122 struct intel_crtc *intel_crtc;
13123 struct drm_crtc *crtc;
13124 struct intel_crtc_state *first_crtc_state = NULL;
13125 struct intel_crtc_state *other_crtc_state = NULL;
13126 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13127 int i;
13128
13129 /* look at all crtc's that are going to be enabled in during modeset */
13130 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13131 intel_crtc = to_intel_crtc(crtc);
13132
13133 if (!crtc_state->active || !needs_modeset(crtc_state))
13134 continue;
13135
13136 if (first_crtc_state) {
13137 other_crtc_state = to_intel_crtc_state(crtc_state);
13138 break;
13139 } else {
13140 first_crtc_state = to_intel_crtc_state(crtc_state);
13141 first_pipe = intel_crtc->pipe;
13142 }
13143 }
13144
13145 /* No workaround needed? */
13146 if (!first_crtc_state)
13147 return 0;
13148
13149 /* w/a possibly needed, check how many crtc's are already enabled. */
13150 for_each_intel_crtc(state->dev, intel_crtc) {
13151 struct intel_crtc_state *pipe_config;
13152
13153 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13154 if (IS_ERR(pipe_config))
13155 return PTR_ERR(pipe_config);
13156
13157 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13158
13159 if (!pipe_config->base.active ||
13160 needs_modeset(&pipe_config->base))
13161 continue;
13162
13163 /* 2 or more enabled crtcs means no need for w/a */
13164 if (enabled_pipe != INVALID_PIPE)
13165 return 0;
13166
13167 enabled_pipe = intel_crtc->pipe;
13168 }
13169
13170 if (enabled_pipe != INVALID_PIPE)
13171 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13172 else if (other_crtc_state)
13173 other_crtc_state->hsw_workaround_pipe = first_pipe;
13174
13175 return 0;
13176 }
13177
13178 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13179 {
13180 struct drm_crtc *crtc;
13181 struct drm_crtc_state *crtc_state;
13182 int ret = 0;
13183
13184 /* add all active pipes to the state */
13185 for_each_crtc(state->dev, crtc) {
13186 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13187 if (IS_ERR(crtc_state))
13188 return PTR_ERR(crtc_state);
13189
13190 if (!crtc_state->active || needs_modeset(crtc_state))
13191 continue;
13192
13193 crtc_state->mode_changed = true;
13194
13195 ret = drm_atomic_add_affected_connectors(state, crtc);
13196 if (ret)
13197 break;
13198
13199 ret = drm_atomic_add_affected_planes(state, crtc);
13200 if (ret)
13201 break;
13202 }
13203
13204 return ret;
13205 }
13206
13207 static int intel_modeset_checks(struct drm_atomic_state *state)
13208 {
13209 struct drm_device *dev = state->dev;
13210 struct drm_i915_private *dev_priv = dev->dev_private;
13211 int ret;
13212
13213 if (!check_digital_port_conflicts(state)) {
13214 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13215 return -EINVAL;
13216 }
13217
13218 /*
13219 * See if the config requires any additional preparation, e.g.
13220 * to adjust global state with pipes off. We need to do this
13221 * here so we can get the modeset_pipe updated config for the new
13222 * mode set on this crtc. For other crtcs we need to use the
13223 * adjusted_mode bits in the crtc directly.
13224 */
13225 if (dev_priv->display.modeset_calc_cdclk) {
13226 unsigned int cdclk;
13227
13228 ret = dev_priv->display.modeset_calc_cdclk(state);
13229
13230 cdclk = to_intel_atomic_state(state)->cdclk;
13231 if (!ret && cdclk != dev_priv->cdclk_freq)
13232 ret = intel_modeset_all_pipes(state);
13233
13234 if (ret < 0)
13235 return ret;
13236 } else
13237 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13238
13239 intel_modeset_clear_plls(state);
13240
13241 if (IS_HASWELL(dev))
13242 return haswell_mode_set_planes_workaround(state);
13243
13244 return 0;
13245 }
13246
13247 /*
13248 * Handle calculation of various watermark data at the end of the atomic check
13249 * phase. The code here should be run after the per-crtc and per-plane 'check'
13250 * handlers to ensure that all derived state has been updated.
13251 */
13252 static void calc_watermark_data(struct drm_atomic_state *state)
13253 {
13254 struct drm_device *dev = state->dev;
13255 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13256 struct drm_crtc *crtc;
13257 struct drm_crtc_state *cstate;
13258 struct drm_plane *plane;
13259 struct drm_plane_state *pstate;
13260
13261 /*
13262 * Calculate watermark configuration details now that derived
13263 * plane/crtc state is all properly updated.
13264 */
13265 drm_for_each_crtc(crtc, dev) {
13266 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13267 crtc->state;
13268
13269 if (cstate->active)
13270 intel_state->wm_config.num_pipes_active++;
13271 }
13272 drm_for_each_legacy_plane(plane, dev) {
13273 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13274 plane->state;
13275
13276 if (!to_intel_plane_state(pstate)->visible)
13277 continue;
13278
13279 intel_state->wm_config.sprites_enabled = true;
13280 if (pstate->crtc_w != pstate->src_w >> 16 ||
13281 pstate->crtc_h != pstate->src_h >> 16)
13282 intel_state->wm_config.sprites_scaled = true;
13283 }
13284 }
13285
13286 /**
13287 * intel_atomic_check - validate state object
13288 * @dev: drm device
13289 * @state: state to validate
13290 */
13291 static int intel_atomic_check(struct drm_device *dev,
13292 struct drm_atomic_state *state)
13293 {
13294 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13295 struct drm_crtc *crtc;
13296 struct drm_crtc_state *crtc_state;
13297 int ret, i;
13298 bool any_ms = false;
13299
13300 ret = drm_atomic_helper_check_modeset(dev, state);
13301 if (ret)
13302 return ret;
13303
13304 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13305 struct intel_crtc_state *pipe_config =
13306 to_intel_crtc_state(crtc_state);
13307
13308 memset(&to_intel_crtc(crtc)->atomic, 0,
13309 sizeof(struct intel_crtc_atomic_commit));
13310
13311 /* Catch I915_MODE_FLAG_INHERITED */
13312 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13313 crtc_state->mode_changed = true;
13314
13315 if (!crtc_state->enable) {
13316 if (needs_modeset(crtc_state))
13317 any_ms = true;
13318 continue;
13319 }
13320
13321 if (!needs_modeset(crtc_state))
13322 continue;
13323
13324 /* FIXME: For only active_changed we shouldn't need to do any
13325 * state recomputation at all. */
13326
13327 ret = drm_atomic_add_affected_connectors(state, crtc);
13328 if (ret)
13329 return ret;
13330
13331 ret = intel_modeset_pipe_config(crtc, pipe_config);
13332 if (ret)
13333 return ret;
13334
13335 if (i915.fastboot &&
13336 intel_pipe_config_compare(state->dev,
13337 to_intel_crtc_state(crtc->state),
13338 pipe_config, true)) {
13339 crtc_state->mode_changed = false;
13340 to_intel_crtc_state(crtc_state)->update_pipe = true;
13341 }
13342
13343 if (needs_modeset(crtc_state)) {
13344 any_ms = true;
13345
13346 ret = drm_atomic_add_affected_planes(state, crtc);
13347 if (ret)
13348 return ret;
13349 }
13350
13351 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13352 needs_modeset(crtc_state) ?
13353 "[modeset]" : "[fastset]");
13354 }
13355
13356 if (any_ms) {
13357 ret = intel_modeset_checks(state);
13358
13359 if (ret)
13360 return ret;
13361 } else
13362 intel_state->cdclk = to_i915(state->dev)->cdclk_freq;
13363
13364 ret = drm_atomic_helper_check_planes(state->dev, state);
13365 if (ret)
13366 return ret;
13367
13368 calc_watermark_data(state);
13369
13370 return 0;
13371 }
13372
13373 static int intel_atomic_prepare_commit(struct drm_device *dev,
13374 struct drm_atomic_state *state,
13375 bool async)
13376 {
13377 struct drm_i915_private *dev_priv = dev->dev_private;
13378 struct drm_plane_state *plane_state;
13379 struct drm_crtc_state *crtc_state;
13380 struct drm_plane *plane;
13381 struct drm_crtc *crtc;
13382 int i, ret;
13383
13384 if (async) {
13385 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13386 return -EINVAL;
13387 }
13388
13389 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13390 ret = intel_crtc_wait_for_pending_flips(crtc);
13391 if (ret)
13392 return ret;
13393
13394 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13395 flush_workqueue(dev_priv->wq);
13396 }
13397
13398 ret = mutex_lock_interruptible(&dev->struct_mutex);
13399 if (ret)
13400 return ret;
13401
13402 ret = drm_atomic_helper_prepare_planes(dev, state);
13403 if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13404 u32 reset_counter;
13405
13406 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13407 mutex_unlock(&dev->struct_mutex);
13408
13409 for_each_plane_in_state(state, plane, plane_state, i) {
13410 struct intel_plane_state *intel_plane_state =
13411 to_intel_plane_state(plane_state);
13412
13413 if (!intel_plane_state->wait_req)
13414 continue;
13415
13416 ret = __i915_wait_request(intel_plane_state->wait_req,
13417 reset_counter, true,
13418 NULL, NULL);
13419
13420 /* Swallow -EIO errors to allow updates during hw lockup. */
13421 if (ret == -EIO)
13422 ret = 0;
13423
13424 if (ret)
13425 break;
13426 }
13427
13428 if (!ret)
13429 return 0;
13430
13431 mutex_lock(&dev->struct_mutex);
13432 drm_atomic_helper_cleanup_planes(dev, state);
13433 }
13434
13435 mutex_unlock(&dev->struct_mutex);
13436 return ret;
13437 }
13438
13439 /**
13440 * intel_atomic_commit - commit validated state object
13441 * @dev: DRM device
13442 * @state: the top-level driver state object
13443 * @async: asynchronous commit
13444 *
13445 * This function commits a top-level state object that has been validated
13446 * with drm_atomic_helper_check().
13447 *
13448 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13449 * we can only handle plane-related operations and do not yet support
13450 * asynchronous commit.
13451 *
13452 * RETURNS
13453 * Zero for success or -errno.
13454 */
13455 static int intel_atomic_commit(struct drm_device *dev,
13456 struct drm_atomic_state *state,
13457 bool async)
13458 {
13459 struct drm_i915_private *dev_priv = dev->dev_private;
13460 struct drm_crtc_state *crtc_state;
13461 struct drm_crtc *crtc;
13462 int ret = 0;
13463 int i;
13464 bool any_ms = false;
13465
13466 ret = intel_atomic_prepare_commit(dev, state, async);
13467 if (ret) {
13468 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13469 return ret;
13470 }
13471
13472 drm_atomic_helper_swap_state(dev, state);
13473 dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
13474
13475 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13477
13478 if (!needs_modeset(crtc->state))
13479 continue;
13480
13481 any_ms = true;
13482 intel_pre_plane_update(intel_crtc);
13483
13484 if (crtc_state->active) {
13485 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13486 dev_priv->display.crtc_disable(crtc);
13487 intel_crtc->active = false;
13488 intel_disable_shared_dpll(intel_crtc);
13489
13490 /*
13491 * Underruns don't always raise
13492 * interrupts, so check manually.
13493 */
13494 intel_check_cpu_fifo_underruns(dev_priv);
13495 intel_check_pch_fifo_underruns(dev_priv);
13496
13497 if (!crtc->state->active)
13498 intel_update_watermarks(crtc);
13499 }
13500 }
13501
13502 /* Only after disabling all output pipelines that will be changed can we
13503 * update the the output configuration. */
13504 intel_modeset_update_crtc_state(state);
13505
13506 if (any_ms) {
13507 intel_shared_dpll_commit(state);
13508
13509 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13510 modeset_update_crtc_power_domains(state);
13511 }
13512
13513 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13514 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13516 bool modeset = needs_modeset(crtc->state);
13517 bool update_pipe = !modeset &&
13518 to_intel_crtc_state(crtc->state)->update_pipe;
13519 unsigned long put_domains = 0;
13520
13521 if (modeset)
13522 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13523
13524 if (modeset && crtc->state->active) {
13525 update_scanline_offset(to_intel_crtc(crtc));
13526 dev_priv->display.crtc_enable(crtc);
13527 }
13528
13529 if (update_pipe) {
13530 put_domains = modeset_get_crtc_power_domains(crtc);
13531
13532 /* make sure intel_modeset_check_state runs */
13533 any_ms = true;
13534 }
13535
13536 if (!modeset)
13537 intel_pre_plane_update(intel_crtc);
13538
13539 if (crtc->state->active &&
13540 (crtc->state->planes_changed || update_pipe))
13541 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13542
13543 if (put_domains)
13544 modeset_put_power_domains(dev_priv, put_domains);
13545
13546 intel_post_plane_update(intel_crtc);
13547
13548 if (modeset)
13549 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13550 }
13551
13552 /* FIXME: add subpixel order */
13553
13554 drm_atomic_helper_wait_for_vblanks(dev, state);
13555
13556 mutex_lock(&dev->struct_mutex);
13557 drm_atomic_helper_cleanup_planes(dev, state);
13558 mutex_unlock(&dev->struct_mutex);
13559
13560 if (any_ms)
13561 intel_modeset_check_state(dev, state);
13562
13563 drm_atomic_state_free(state);
13564
13565 return 0;
13566 }
13567
13568 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13569 {
13570 struct drm_device *dev = crtc->dev;
13571 struct drm_atomic_state *state;
13572 struct drm_crtc_state *crtc_state;
13573 int ret;
13574
13575 state = drm_atomic_state_alloc(dev);
13576 if (!state) {
13577 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13578 crtc->base.id);
13579 return;
13580 }
13581
13582 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13583
13584 retry:
13585 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13586 ret = PTR_ERR_OR_ZERO(crtc_state);
13587 if (!ret) {
13588 if (!crtc_state->active)
13589 goto out;
13590
13591 crtc_state->mode_changed = true;
13592 ret = drm_atomic_commit(state);
13593 }
13594
13595 if (ret == -EDEADLK) {
13596 drm_atomic_state_clear(state);
13597 drm_modeset_backoff(state->acquire_ctx);
13598 goto retry;
13599 }
13600
13601 if (ret)
13602 out:
13603 drm_atomic_state_free(state);
13604 }
13605
13606 #undef for_each_intel_crtc_masked
13607
13608 static const struct drm_crtc_funcs intel_crtc_funcs = {
13609 .gamma_set = intel_crtc_gamma_set,
13610 .set_config = drm_atomic_helper_set_config,
13611 .destroy = intel_crtc_destroy,
13612 .page_flip = intel_crtc_page_flip,
13613 .atomic_duplicate_state = intel_crtc_duplicate_state,
13614 .atomic_destroy_state = intel_crtc_destroy_state,
13615 };
13616
13617 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13618 struct intel_shared_dpll *pll,
13619 struct intel_dpll_hw_state *hw_state)
13620 {
13621 uint32_t val;
13622
13623 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13624 return false;
13625
13626 val = I915_READ(PCH_DPLL(pll->id));
13627 hw_state->dpll = val;
13628 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13629 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13630
13631 return val & DPLL_VCO_ENABLE;
13632 }
13633
13634 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13635 struct intel_shared_dpll *pll)
13636 {
13637 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13638 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13639 }
13640
13641 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13642 struct intel_shared_dpll *pll)
13643 {
13644 /* PCH refclock must be enabled first */
13645 ibx_assert_pch_refclk_enabled(dev_priv);
13646
13647 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13648
13649 /* Wait for the clocks to stabilize. */
13650 POSTING_READ(PCH_DPLL(pll->id));
13651 udelay(150);
13652
13653 /* The pixel multiplier can only be updated once the
13654 * DPLL is enabled and the clocks are stable.
13655 *
13656 * So write it again.
13657 */
13658 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13659 POSTING_READ(PCH_DPLL(pll->id));
13660 udelay(200);
13661 }
13662
13663 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13664 struct intel_shared_dpll *pll)
13665 {
13666 struct drm_device *dev = dev_priv->dev;
13667 struct intel_crtc *crtc;
13668
13669 /* Make sure no transcoder isn't still depending on us. */
13670 for_each_intel_crtc(dev, crtc) {
13671 if (intel_crtc_to_shared_dpll(crtc) == pll)
13672 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13673 }
13674
13675 I915_WRITE(PCH_DPLL(pll->id), 0);
13676 POSTING_READ(PCH_DPLL(pll->id));
13677 udelay(200);
13678 }
13679
13680 static char *ibx_pch_dpll_names[] = {
13681 "PCH DPLL A",
13682 "PCH DPLL B",
13683 };
13684
13685 static void ibx_pch_dpll_init(struct drm_device *dev)
13686 {
13687 struct drm_i915_private *dev_priv = dev->dev_private;
13688 int i;
13689
13690 dev_priv->num_shared_dpll = 2;
13691
13692 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13693 dev_priv->shared_dplls[i].id = i;
13694 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13695 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13696 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13697 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13698 dev_priv->shared_dplls[i].get_hw_state =
13699 ibx_pch_dpll_get_hw_state;
13700 }
13701 }
13702
13703 static void intel_shared_dpll_init(struct drm_device *dev)
13704 {
13705 struct drm_i915_private *dev_priv = dev->dev_private;
13706
13707 if (HAS_DDI(dev))
13708 intel_ddi_pll_init(dev);
13709 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13710 ibx_pch_dpll_init(dev);
13711 else
13712 dev_priv->num_shared_dpll = 0;
13713
13714 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13715 }
13716
13717 /**
13718 * intel_prepare_plane_fb - Prepare fb for usage on plane
13719 * @plane: drm plane to prepare for
13720 * @fb: framebuffer to prepare for presentation
13721 *
13722 * Prepares a framebuffer for usage on a display plane. Generally this
13723 * involves pinning the underlying object and updating the frontbuffer tracking
13724 * bits. Some older platforms need special physical address handling for
13725 * cursor planes.
13726 *
13727 * Must be called with struct_mutex held.
13728 *
13729 * Returns 0 on success, negative error code on failure.
13730 */
13731 int
13732 intel_prepare_plane_fb(struct drm_plane *plane,
13733 const struct drm_plane_state *new_state)
13734 {
13735 struct drm_device *dev = plane->dev;
13736 struct drm_framebuffer *fb = new_state->fb;
13737 struct intel_plane *intel_plane = to_intel_plane(plane);
13738 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13739 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13740 int ret = 0;
13741
13742 if (!obj && !old_obj)
13743 return 0;
13744
13745 if (old_obj) {
13746 struct drm_crtc_state *crtc_state =
13747 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13748
13749 /* Big Hammer, we also need to ensure that any pending
13750 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13751 * current scanout is retired before unpinning the old
13752 * framebuffer. Note that we rely on userspace rendering
13753 * into the buffer attached to the pipe they are waiting
13754 * on. If not, userspace generates a GPU hang with IPEHR
13755 * point to the MI_WAIT_FOR_EVENT.
13756 *
13757 * This should only fail upon a hung GPU, in which case we
13758 * can safely continue.
13759 */
13760 if (needs_modeset(crtc_state))
13761 ret = i915_gem_object_wait_rendering(old_obj, true);
13762
13763 /* Swallow -EIO errors to allow updates during hw lockup. */
13764 if (ret && ret != -EIO)
13765 return ret;
13766 }
13767
13768 /* For framebuffer backed by dmabuf, wait for fence */
13769 if (obj && obj->base.dma_buf) {
13770 long lret;
13771
13772 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13773 false, true,
13774 MAX_SCHEDULE_TIMEOUT);
13775 if (lret == -ERESTARTSYS)
13776 return lret;
13777
13778 WARN(lret < 0, "waiting returns %li\n", lret);
13779 }
13780
13781 if (!obj) {
13782 ret = 0;
13783 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13784 INTEL_INFO(dev)->cursor_needs_physical) {
13785 int align = IS_I830(dev) ? 16 * 1024 : 256;
13786 ret = i915_gem_object_attach_phys(obj, align);
13787 if (ret)
13788 DRM_DEBUG_KMS("failed to attach phys object\n");
13789 } else {
13790 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state);
13791 }
13792
13793 if (ret == 0) {
13794 if (obj) {
13795 struct intel_plane_state *plane_state =
13796 to_intel_plane_state(new_state);
13797
13798 i915_gem_request_assign(&plane_state->wait_req,
13799 obj->last_write_req);
13800 }
13801
13802 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13803 }
13804
13805 return ret;
13806 }
13807
13808 /**
13809 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13810 * @plane: drm plane to clean up for
13811 * @fb: old framebuffer that was on plane
13812 *
13813 * Cleans up a framebuffer that has just been removed from a plane.
13814 *
13815 * Must be called with struct_mutex held.
13816 */
13817 void
13818 intel_cleanup_plane_fb(struct drm_plane *plane,
13819 const struct drm_plane_state *old_state)
13820 {
13821 struct drm_device *dev = plane->dev;
13822 struct intel_plane *intel_plane = to_intel_plane(plane);
13823 struct intel_plane_state *old_intel_state;
13824 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13825 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13826
13827 old_intel_state = to_intel_plane_state(old_state);
13828
13829 if (!obj && !old_obj)
13830 return;
13831
13832 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13833 !INTEL_INFO(dev)->cursor_needs_physical))
13834 intel_unpin_fb_obj(old_state->fb, old_state);
13835
13836 /* prepare_fb aborted? */
13837 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13838 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13839 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13840
13841 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13842
13843 }
13844
13845 int
13846 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13847 {
13848 int max_scale;
13849 struct drm_device *dev;
13850 struct drm_i915_private *dev_priv;
13851 int crtc_clock, cdclk;
13852
13853 if (!intel_crtc || !crtc_state)
13854 return DRM_PLANE_HELPER_NO_SCALING;
13855
13856 dev = intel_crtc->base.dev;
13857 dev_priv = dev->dev_private;
13858 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13859 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13860
13861 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13862 return DRM_PLANE_HELPER_NO_SCALING;
13863
13864 /*
13865 * skl max scale is lower of:
13866 * close to 3 but not 3, -1 is for that purpose
13867 * or
13868 * cdclk/crtc_clock
13869 */
13870 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13871
13872 return max_scale;
13873 }
13874
13875 static int
13876 intel_check_primary_plane(struct drm_plane *plane,
13877 struct intel_crtc_state *crtc_state,
13878 struct intel_plane_state *state)
13879 {
13880 struct drm_crtc *crtc = state->base.crtc;
13881 struct drm_framebuffer *fb = state->base.fb;
13882 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13883 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13884 bool can_position = false;
13885
13886 /* use scaler when colorkey is not required */
13887 if (INTEL_INFO(plane->dev)->gen >= 9 &&
13888 state->ckey.flags == I915_SET_COLORKEY_NONE) {
13889 min_scale = 1;
13890 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13891 can_position = true;
13892 }
13893
13894 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13895 &state->dst, &state->clip,
13896 min_scale, max_scale,
13897 can_position, true,
13898 &state->visible);
13899 }
13900
13901 static void
13902 intel_commit_primary_plane(struct drm_plane *plane,
13903 struct intel_plane_state *state)
13904 {
13905 struct drm_crtc *crtc = state->base.crtc;
13906 struct drm_framebuffer *fb = state->base.fb;
13907 struct drm_device *dev = plane->dev;
13908 struct drm_i915_private *dev_priv = dev->dev_private;
13909
13910 crtc = crtc ? crtc : plane->crtc;
13911
13912 dev_priv->display.update_primary_plane(crtc, fb,
13913 state->src.x1 >> 16,
13914 state->src.y1 >> 16);
13915 }
13916
13917 static void
13918 intel_disable_primary_plane(struct drm_plane *plane,
13919 struct drm_crtc *crtc)
13920 {
13921 struct drm_device *dev = plane->dev;
13922 struct drm_i915_private *dev_priv = dev->dev_private;
13923
13924 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13925 }
13926
13927 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13928 struct drm_crtc_state *old_crtc_state)
13929 {
13930 struct drm_device *dev = crtc->dev;
13931 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13932 struct intel_crtc_state *old_intel_state =
13933 to_intel_crtc_state(old_crtc_state);
13934 bool modeset = needs_modeset(crtc->state);
13935
13936 /* Perform vblank evasion around commit operation */
13937 intel_pipe_update_start(intel_crtc);
13938
13939 if (modeset)
13940 return;
13941
13942 if (to_intel_crtc_state(crtc->state)->update_pipe)
13943 intel_update_pipe_config(intel_crtc, old_intel_state);
13944 else if (INTEL_INFO(dev)->gen >= 9)
13945 skl_detach_scalers(intel_crtc);
13946 }
13947
13948 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13949 struct drm_crtc_state *old_crtc_state)
13950 {
13951 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13952
13953 intel_pipe_update_end(intel_crtc);
13954 }
13955
13956 /**
13957 * intel_plane_destroy - destroy a plane
13958 * @plane: plane to destroy
13959 *
13960 * Common destruction function for all types of planes (primary, cursor,
13961 * sprite).
13962 */
13963 void intel_plane_destroy(struct drm_plane *plane)
13964 {
13965 struct intel_plane *intel_plane = to_intel_plane(plane);
13966 drm_plane_cleanup(plane);
13967 kfree(intel_plane);
13968 }
13969
13970 const struct drm_plane_funcs intel_plane_funcs = {
13971 .update_plane = drm_atomic_helper_update_plane,
13972 .disable_plane = drm_atomic_helper_disable_plane,
13973 .destroy = intel_plane_destroy,
13974 .set_property = drm_atomic_helper_plane_set_property,
13975 .atomic_get_property = intel_plane_atomic_get_property,
13976 .atomic_set_property = intel_plane_atomic_set_property,
13977 .atomic_duplicate_state = intel_plane_duplicate_state,
13978 .atomic_destroy_state = intel_plane_destroy_state,
13979
13980 };
13981
13982 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13983 int pipe)
13984 {
13985 struct intel_plane *primary;
13986 struct intel_plane_state *state;
13987 const uint32_t *intel_primary_formats;
13988 unsigned int num_formats;
13989
13990 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13991 if (primary == NULL)
13992 return NULL;
13993
13994 state = intel_create_plane_state(&primary->base);
13995 if (!state) {
13996 kfree(primary);
13997 return NULL;
13998 }
13999 primary->base.state = &state->base;
14000
14001 primary->can_scale = false;
14002 primary->max_downscale = 1;
14003 if (INTEL_INFO(dev)->gen >= 9) {
14004 primary->can_scale = true;
14005 state->scaler_id = -1;
14006 }
14007 primary->pipe = pipe;
14008 primary->plane = pipe;
14009 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14010 primary->check_plane = intel_check_primary_plane;
14011 primary->commit_plane = intel_commit_primary_plane;
14012 primary->disable_plane = intel_disable_primary_plane;
14013 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14014 primary->plane = !pipe;
14015
14016 if (INTEL_INFO(dev)->gen >= 9) {
14017 intel_primary_formats = skl_primary_formats;
14018 num_formats = ARRAY_SIZE(skl_primary_formats);
14019 } else if (INTEL_INFO(dev)->gen >= 4) {
14020 intel_primary_formats = i965_primary_formats;
14021 num_formats = ARRAY_SIZE(i965_primary_formats);
14022 } else {
14023 intel_primary_formats = i8xx_primary_formats;
14024 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14025 }
14026
14027 drm_universal_plane_init(dev, &primary->base, 0,
14028 &intel_plane_funcs,
14029 intel_primary_formats, num_formats,
14030 DRM_PLANE_TYPE_PRIMARY, NULL);
14031
14032 if (INTEL_INFO(dev)->gen >= 4)
14033 intel_create_rotation_property(dev, primary);
14034
14035 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14036
14037 return &primary->base;
14038 }
14039
14040 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14041 {
14042 if (!dev->mode_config.rotation_property) {
14043 unsigned long flags = BIT(DRM_ROTATE_0) |
14044 BIT(DRM_ROTATE_180);
14045
14046 if (INTEL_INFO(dev)->gen >= 9)
14047 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14048
14049 dev->mode_config.rotation_property =
14050 drm_mode_create_rotation_property(dev, flags);
14051 }
14052 if (dev->mode_config.rotation_property)
14053 drm_object_attach_property(&plane->base.base,
14054 dev->mode_config.rotation_property,
14055 plane->base.state->rotation);
14056 }
14057
14058 static int
14059 intel_check_cursor_plane(struct drm_plane *plane,
14060 struct intel_crtc_state *crtc_state,
14061 struct intel_plane_state *state)
14062 {
14063 struct drm_crtc *crtc = crtc_state->base.crtc;
14064 struct drm_framebuffer *fb = state->base.fb;
14065 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14066 enum pipe pipe = to_intel_plane(plane)->pipe;
14067 unsigned stride;
14068 int ret;
14069
14070 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14071 &state->dst, &state->clip,
14072 DRM_PLANE_HELPER_NO_SCALING,
14073 DRM_PLANE_HELPER_NO_SCALING,
14074 true, true, &state->visible);
14075 if (ret)
14076 return ret;
14077
14078 /* if we want to turn off the cursor ignore width and height */
14079 if (!obj)
14080 return 0;
14081
14082 /* Check for which cursor types we support */
14083 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14084 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14085 state->base.crtc_w, state->base.crtc_h);
14086 return -EINVAL;
14087 }
14088
14089 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14090 if (obj->base.size < stride * state->base.crtc_h) {
14091 DRM_DEBUG_KMS("buffer is too small\n");
14092 return -ENOMEM;
14093 }
14094
14095 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14096 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14097 return -EINVAL;
14098 }
14099
14100 /*
14101 * There's something wrong with the cursor on CHV pipe C.
14102 * If it straddles the left edge of the screen then
14103 * moving it away from the edge or disabling it often
14104 * results in a pipe underrun, and often that can lead to
14105 * dead pipe (constant underrun reported, and it scans
14106 * out just a solid color). To recover from that, the
14107 * display power well must be turned off and on again.
14108 * Refuse the put the cursor into that compromised position.
14109 */
14110 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14111 state->visible && state->base.crtc_x < 0) {
14112 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14113 return -EINVAL;
14114 }
14115
14116 return 0;
14117 }
14118
14119 static void
14120 intel_disable_cursor_plane(struct drm_plane *plane,
14121 struct drm_crtc *crtc)
14122 {
14123 intel_crtc_update_cursor(crtc, false);
14124 }
14125
14126 static void
14127 intel_commit_cursor_plane(struct drm_plane *plane,
14128 struct intel_plane_state *state)
14129 {
14130 struct drm_crtc *crtc = state->base.crtc;
14131 struct drm_device *dev = plane->dev;
14132 struct intel_crtc *intel_crtc;
14133 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14134 uint32_t addr;
14135
14136 crtc = crtc ? crtc : plane->crtc;
14137 intel_crtc = to_intel_crtc(crtc);
14138
14139 if (!obj)
14140 addr = 0;
14141 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14142 addr = i915_gem_obj_ggtt_offset(obj);
14143 else
14144 addr = obj->phys_handle->busaddr;
14145
14146 intel_crtc->cursor_addr = addr;
14147
14148 if (crtc->state->active)
14149 intel_crtc_update_cursor(crtc, state->visible);
14150 }
14151
14152 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14153 int pipe)
14154 {
14155 struct intel_plane *cursor;
14156 struct intel_plane_state *state;
14157
14158 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14159 if (cursor == NULL)
14160 return NULL;
14161
14162 state = intel_create_plane_state(&cursor->base);
14163 if (!state) {
14164 kfree(cursor);
14165 return NULL;
14166 }
14167 cursor->base.state = &state->base;
14168
14169 cursor->can_scale = false;
14170 cursor->max_downscale = 1;
14171 cursor->pipe = pipe;
14172 cursor->plane = pipe;
14173 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14174 cursor->check_plane = intel_check_cursor_plane;
14175 cursor->commit_plane = intel_commit_cursor_plane;
14176 cursor->disable_plane = intel_disable_cursor_plane;
14177
14178 drm_universal_plane_init(dev, &cursor->base, 0,
14179 &intel_plane_funcs,
14180 intel_cursor_formats,
14181 ARRAY_SIZE(intel_cursor_formats),
14182 DRM_PLANE_TYPE_CURSOR, NULL);
14183
14184 if (INTEL_INFO(dev)->gen >= 4) {
14185 if (!dev->mode_config.rotation_property)
14186 dev->mode_config.rotation_property =
14187 drm_mode_create_rotation_property(dev,
14188 BIT(DRM_ROTATE_0) |
14189 BIT(DRM_ROTATE_180));
14190 if (dev->mode_config.rotation_property)
14191 drm_object_attach_property(&cursor->base.base,
14192 dev->mode_config.rotation_property,
14193 state->base.rotation);
14194 }
14195
14196 if (INTEL_INFO(dev)->gen >=9)
14197 state->scaler_id = -1;
14198
14199 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14200
14201 return &cursor->base;
14202 }
14203
14204 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14205 struct intel_crtc_state *crtc_state)
14206 {
14207 int i;
14208 struct intel_scaler *intel_scaler;
14209 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14210
14211 for (i = 0; i < intel_crtc->num_scalers; i++) {
14212 intel_scaler = &scaler_state->scalers[i];
14213 intel_scaler->in_use = 0;
14214 intel_scaler->mode = PS_SCALER_MODE_DYN;
14215 }
14216
14217 scaler_state->scaler_id = -1;
14218 }
14219
14220 static void intel_crtc_init(struct drm_device *dev, int pipe)
14221 {
14222 struct drm_i915_private *dev_priv = dev->dev_private;
14223 struct intel_crtc *intel_crtc;
14224 struct intel_crtc_state *crtc_state = NULL;
14225 struct drm_plane *primary = NULL;
14226 struct drm_plane *cursor = NULL;
14227 int i, ret;
14228
14229 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14230 if (intel_crtc == NULL)
14231 return;
14232
14233 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14234 if (!crtc_state)
14235 goto fail;
14236 intel_crtc->config = crtc_state;
14237 intel_crtc->base.state = &crtc_state->base;
14238 crtc_state->base.crtc = &intel_crtc->base;
14239
14240 /* initialize shared scalers */
14241 if (INTEL_INFO(dev)->gen >= 9) {
14242 if (pipe == PIPE_C)
14243 intel_crtc->num_scalers = 1;
14244 else
14245 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14246
14247 skl_init_scalers(dev, intel_crtc, crtc_state);
14248 }
14249
14250 primary = intel_primary_plane_create(dev, pipe);
14251 if (!primary)
14252 goto fail;
14253
14254 cursor = intel_cursor_plane_create(dev, pipe);
14255 if (!cursor)
14256 goto fail;
14257
14258 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14259 cursor, &intel_crtc_funcs, NULL);
14260 if (ret)
14261 goto fail;
14262
14263 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14264 for (i = 0; i < 256; i++) {
14265 intel_crtc->lut_r[i] = i;
14266 intel_crtc->lut_g[i] = i;
14267 intel_crtc->lut_b[i] = i;
14268 }
14269
14270 /*
14271 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14272 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14273 */
14274 intel_crtc->pipe = pipe;
14275 intel_crtc->plane = pipe;
14276 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14277 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14278 intel_crtc->plane = !pipe;
14279 }
14280
14281 intel_crtc->cursor_base = ~0;
14282 intel_crtc->cursor_cntl = ~0;
14283 intel_crtc->cursor_size = ~0;
14284
14285 intel_crtc->wm.cxsr_allowed = true;
14286
14287 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14288 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14289 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14290 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14291
14292 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14293
14294 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14295 return;
14296
14297 fail:
14298 if (primary)
14299 drm_plane_cleanup(primary);
14300 if (cursor)
14301 drm_plane_cleanup(cursor);
14302 kfree(crtc_state);
14303 kfree(intel_crtc);
14304 }
14305
14306 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14307 {
14308 struct drm_encoder *encoder = connector->base.encoder;
14309 struct drm_device *dev = connector->base.dev;
14310
14311 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14312
14313 if (!encoder || WARN_ON(!encoder->crtc))
14314 return INVALID_PIPE;
14315
14316 return to_intel_crtc(encoder->crtc)->pipe;
14317 }
14318
14319 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14320 struct drm_file *file)
14321 {
14322 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14323 struct drm_crtc *drmmode_crtc;
14324 struct intel_crtc *crtc;
14325
14326 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14327
14328 if (!drmmode_crtc) {
14329 DRM_ERROR("no such CRTC id\n");
14330 return -ENOENT;
14331 }
14332
14333 crtc = to_intel_crtc(drmmode_crtc);
14334 pipe_from_crtc_id->pipe = crtc->pipe;
14335
14336 return 0;
14337 }
14338
14339 static int intel_encoder_clones(struct intel_encoder *encoder)
14340 {
14341 struct drm_device *dev = encoder->base.dev;
14342 struct intel_encoder *source_encoder;
14343 int index_mask = 0;
14344 int entry = 0;
14345
14346 for_each_intel_encoder(dev, source_encoder) {
14347 if (encoders_cloneable(encoder, source_encoder))
14348 index_mask |= (1 << entry);
14349
14350 entry++;
14351 }
14352
14353 return index_mask;
14354 }
14355
14356 static bool has_edp_a(struct drm_device *dev)
14357 {
14358 struct drm_i915_private *dev_priv = dev->dev_private;
14359
14360 if (!IS_MOBILE(dev))
14361 return false;
14362
14363 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14364 return false;
14365
14366 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14367 return false;
14368
14369 return true;
14370 }
14371
14372 static bool intel_crt_present(struct drm_device *dev)
14373 {
14374 struct drm_i915_private *dev_priv = dev->dev_private;
14375
14376 if (INTEL_INFO(dev)->gen >= 9)
14377 return false;
14378
14379 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14380 return false;
14381
14382 if (IS_CHERRYVIEW(dev))
14383 return false;
14384
14385 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14386 return false;
14387
14388 /* DDI E can't be used if DDI A requires 4 lanes */
14389 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14390 return false;
14391
14392 if (!dev_priv->vbt.int_crt_support)
14393 return false;
14394
14395 return true;
14396 }
14397
14398 static void intel_setup_outputs(struct drm_device *dev)
14399 {
14400 struct drm_i915_private *dev_priv = dev->dev_private;
14401 struct intel_encoder *encoder;
14402 bool dpd_is_edp = false;
14403
14404 intel_lvds_init(dev);
14405
14406 if (intel_crt_present(dev))
14407 intel_crt_init(dev);
14408
14409 if (IS_BROXTON(dev)) {
14410 /*
14411 * FIXME: Broxton doesn't support port detection via the
14412 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14413 * detect the ports.
14414 */
14415 intel_ddi_init(dev, PORT_A);
14416 intel_ddi_init(dev, PORT_B);
14417 intel_ddi_init(dev, PORT_C);
14418 } else if (HAS_DDI(dev)) {
14419 int found;
14420
14421 /*
14422 * Haswell uses DDI functions to detect digital outputs.
14423 * On SKL pre-D0 the strap isn't connected, so we assume
14424 * it's there.
14425 */
14426 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14427 /* WaIgnoreDDIAStrap: skl */
14428 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14429 intel_ddi_init(dev, PORT_A);
14430
14431 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14432 * register */
14433 found = I915_READ(SFUSE_STRAP);
14434
14435 if (found & SFUSE_STRAP_DDIB_DETECTED)
14436 intel_ddi_init(dev, PORT_B);
14437 if (found & SFUSE_STRAP_DDIC_DETECTED)
14438 intel_ddi_init(dev, PORT_C);
14439 if (found & SFUSE_STRAP_DDID_DETECTED)
14440 intel_ddi_init(dev, PORT_D);
14441 /*
14442 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14443 */
14444 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14445 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14446 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14447 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14448 intel_ddi_init(dev, PORT_E);
14449
14450 } else if (HAS_PCH_SPLIT(dev)) {
14451 int found;
14452 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14453
14454 if (has_edp_a(dev))
14455 intel_dp_init(dev, DP_A, PORT_A);
14456
14457 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14458 /* PCH SDVOB multiplex with HDMIB */
14459 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14460 if (!found)
14461 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14462 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14463 intel_dp_init(dev, PCH_DP_B, PORT_B);
14464 }
14465
14466 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14467 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14468
14469 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14470 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14471
14472 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14473 intel_dp_init(dev, PCH_DP_C, PORT_C);
14474
14475 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14476 intel_dp_init(dev, PCH_DP_D, PORT_D);
14477 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14478 /*
14479 * The DP_DETECTED bit is the latched state of the DDC
14480 * SDA pin at boot. However since eDP doesn't require DDC
14481 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14482 * eDP ports may have been muxed to an alternate function.
14483 * Thus we can't rely on the DP_DETECTED bit alone to detect
14484 * eDP ports. Consult the VBT as well as DP_DETECTED to
14485 * detect eDP ports.
14486 */
14487 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14488 !intel_dp_is_edp(dev, PORT_B))
14489 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14490 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14491 intel_dp_is_edp(dev, PORT_B))
14492 intel_dp_init(dev, VLV_DP_B, PORT_B);
14493
14494 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14495 !intel_dp_is_edp(dev, PORT_C))
14496 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14497 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14498 intel_dp_is_edp(dev, PORT_C))
14499 intel_dp_init(dev, VLV_DP_C, PORT_C);
14500
14501 if (IS_CHERRYVIEW(dev)) {
14502 /* eDP not supported on port D, so don't check VBT */
14503 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14504 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14505 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14506 intel_dp_init(dev, CHV_DP_D, PORT_D);
14507 }
14508
14509 intel_dsi_init(dev);
14510 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14511 bool found = false;
14512
14513 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14514 DRM_DEBUG_KMS("probing SDVOB\n");
14515 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14516 if (!found && IS_G4X(dev)) {
14517 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14518 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14519 }
14520
14521 if (!found && IS_G4X(dev))
14522 intel_dp_init(dev, DP_B, PORT_B);
14523 }
14524
14525 /* Before G4X SDVOC doesn't have its own detect register */
14526
14527 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14528 DRM_DEBUG_KMS("probing SDVOC\n");
14529 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14530 }
14531
14532 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14533
14534 if (IS_G4X(dev)) {
14535 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14536 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14537 }
14538 if (IS_G4X(dev))
14539 intel_dp_init(dev, DP_C, PORT_C);
14540 }
14541
14542 if (IS_G4X(dev) &&
14543 (I915_READ(DP_D) & DP_DETECTED))
14544 intel_dp_init(dev, DP_D, PORT_D);
14545 } else if (IS_GEN2(dev))
14546 intel_dvo_init(dev);
14547
14548 if (SUPPORTS_TV(dev))
14549 intel_tv_init(dev);
14550
14551 intel_psr_init(dev);
14552
14553 for_each_intel_encoder(dev, encoder) {
14554 encoder->base.possible_crtcs = encoder->crtc_mask;
14555 encoder->base.possible_clones =
14556 intel_encoder_clones(encoder);
14557 }
14558
14559 intel_init_pch_refclk(dev);
14560
14561 drm_helper_move_panel_connectors_to_head(dev);
14562 }
14563
14564 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14565 {
14566 struct drm_device *dev = fb->dev;
14567 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14568
14569 drm_framebuffer_cleanup(fb);
14570 mutex_lock(&dev->struct_mutex);
14571 WARN_ON(!intel_fb->obj->framebuffer_references--);
14572 drm_gem_object_unreference(&intel_fb->obj->base);
14573 mutex_unlock(&dev->struct_mutex);
14574 kfree(intel_fb);
14575 }
14576
14577 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14578 struct drm_file *file,
14579 unsigned int *handle)
14580 {
14581 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14582 struct drm_i915_gem_object *obj = intel_fb->obj;
14583
14584 if (obj->userptr.mm) {
14585 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14586 return -EINVAL;
14587 }
14588
14589 return drm_gem_handle_create(file, &obj->base, handle);
14590 }
14591
14592 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14593 struct drm_file *file,
14594 unsigned flags, unsigned color,
14595 struct drm_clip_rect *clips,
14596 unsigned num_clips)
14597 {
14598 struct drm_device *dev = fb->dev;
14599 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14600 struct drm_i915_gem_object *obj = intel_fb->obj;
14601
14602 mutex_lock(&dev->struct_mutex);
14603 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14604 mutex_unlock(&dev->struct_mutex);
14605
14606 return 0;
14607 }
14608
14609 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14610 .destroy = intel_user_framebuffer_destroy,
14611 .create_handle = intel_user_framebuffer_create_handle,
14612 .dirty = intel_user_framebuffer_dirty,
14613 };
14614
14615 static
14616 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14617 uint32_t pixel_format)
14618 {
14619 u32 gen = INTEL_INFO(dev)->gen;
14620
14621 if (gen >= 9) {
14622 /* "The stride in bytes must not exceed the of the size of 8K
14623 * pixels and 32K bytes."
14624 */
14625 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14626 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14627 return 32*1024;
14628 } else if (gen >= 4) {
14629 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14630 return 16*1024;
14631 else
14632 return 32*1024;
14633 } else if (gen >= 3) {
14634 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14635 return 8*1024;
14636 else
14637 return 16*1024;
14638 } else {
14639 /* XXX DSPC is limited to 4k tiled */
14640 return 8*1024;
14641 }
14642 }
14643
14644 static int intel_framebuffer_init(struct drm_device *dev,
14645 struct intel_framebuffer *intel_fb,
14646 struct drm_mode_fb_cmd2 *mode_cmd,
14647 struct drm_i915_gem_object *obj)
14648 {
14649 unsigned int aligned_height;
14650 int ret;
14651 u32 pitch_limit, stride_alignment;
14652
14653 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14654
14655 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14656 /* Enforce that fb modifier and tiling mode match, but only for
14657 * X-tiled. This is needed for FBC. */
14658 if (!!(obj->tiling_mode == I915_TILING_X) !=
14659 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14660 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14661 return -EINVAL;
14662 }
14663 } else {
14664 if (obj->tiling_mode == I915_TILING_X)
14665 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14666 else if (obj->tiling_mode == I915_TILING_Y) {
14667 DRM_DEBUG("No Y tiling for legacy addfb\n");
14668 return -EINVAL;
14669 }
14670 }
14671
14672 /* Passed in modifier sanity checking. */
14673 switch (mode_cmd->modifier[0]) {
14674 case I915_FORMAT_MOD_Y_TILED:
14675 case I915_FORMAT_MOD_Yf_TILED:
14676 if (INTEL_INFO(dev)->gen < 9) {
14677 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14678 mode_cmd->modifier[0]);
14679 return -EINVAL;
14680 }
14681 case DRM_FORMAT_MOD_NONE:
14682 case I915_FORMAT_MOD_X_TILED:
14683 break;
14684 default:
14685 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14686 mode_cmd->modifier[0]);
14687 return -EINVAL;
14688 }
14689
14690 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14691 mode_cmd->pixel_format);
14692 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14693 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14694 mode_cmd->pitches[0], stride_alignment);
14695 return -EINVAL;
14696 }
14697
14698 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14699 mode_cmd->pixel_format);
14700 if (mode_cmd->pitches[0] > pitch_limit) {
14701 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14702 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14703 "tiled" : "linear",
14704 mode_cmd->pitches[0], pitch_limit);
14705 return -EINVAL;
14706 }
14707
14708 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14709 mode_cmd->pitches[0] != obj->stride) {
14710 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14711 mode_cmd->pitches[0], obj->stride);
14712 return -EINVAL;
14713 }
14714
14715 /* Reject formats not supported by any plane early. */
14716 switch (mode_cmd->pixel_format) {
14717 case DRM_FORMAT_C8:
14718 case DRM_FORMAT_RGB565:
14719 case DRM_FORMAT_XRGB8888:
14720 case DRM_FORMAT_ARGB8888:
14721 break;
14722 case DRM_FORMAT_XRGB1555:
14723 if (INTEL_INFO(dev)->gen > 3) {
14724 DRM_DEBUG("unsupported pixel format: %s\n",
14725 drm_get_format_name(mode_cmd->pixel_format));
14726 return -EINVAL;
14727 }
14728 break;
14729 case DRM_FORMAT_ABGR8888:
14730 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14731 INTEL_INFO(dev)->gen < 9) {
14732 DRM_DEBUG("unsupported pixel format: %s\n",
14733 drm_get_format_name(mode_cmd->pixel_format));
14734 return -EINVAL;
14735 }
14736 break;
14737 case DRM_FORMAT_XBGR8888:
14738 case DRM_FORMAT_XRGB2101010:
14739 case DRM_FORMAT_XBGR2101010:
14740 if (INTEL_INFO(dev)->gen < 4) {
14741 DRM_DEBUG("unsupported pixel format: %s\n",
14742 drm_get_format_name(mode_cmd->pixel_format));
14743 return -EINVAL;
14744 }
14745 break;
14746 case DRM_FORMAT_ABGR2101010:
14747 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14748 DRM_DEBUG("unsupported pixel format: %s\n",
14749 drm_get_format_name(mode_cmd->pixel_format));
14750 return -EINVAL;
14751 }
14752 break;
14753 case DRM_FORMAT_YUYV:
14754 case DRM_FORMAT_UYVY:
14755 case DRM_FORMAT_YVYU:
14756 case DRM_FORMAT_VYUY:
14757 if (INTEL_INFO(dev)->gen < 5) {
14758 DRM_DEBUG("unsupported pixel format: %s\n",
14759 drm_get_format_name(mode_cmd->pixel_format));
14760 return -EINVAL;
14761 }
14762 break;
14763 default:
14764 DRM_DEBUG("unsupported pixel format: %s\n",
14765 drm_get_format_name(mode_cmd->pixel_format));
14766 return -EINVAL;
14767 }
14768
14769 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14770 if (mode_cmd->offsets[0] != 0)
14771 return -EINVAL;
14772
14773 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14774 mode_cmd->pixel_format,
14775 mode_cmd->modifier[0]);
14776 /* FIXME drm helper for size checks (especially planar formats)? */
14777 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14778 return -EINVAL;
14779
14780 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14781 intel_fb->obj = obj;
14782 intel_fb->obj->framebuffer_references++;
14783
14784 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14785 if (ret) {
14786 DRM_ERROR("framebuffer init failed %d\n", ret);
14787 return ret;
14788 }
14789
14790 return 0;
14791 }
14792
14793 static struct drm_framebuffer *
14794 intel_user_framebuffer_create(struct drm_device *dev,
14795 struct drm_file *filp,
14796 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14797 {
14798 struct drm_framebuffer *fb;
14799 struct drm_i915_gem_object *obj;
14800 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14801
14802 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14803 mode_cmd.handles[0]));
14804 if (&obj->base == NULL)
14805 return ERR_PTR(-ENOENT);
14806
14807 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14808 if (IS_ERR(fb))
14809 drm_gem_object_unreference_unlocked(&obj->base);
14810
14811 return fb;
14812 }
14813
14814 #ifndef CONFIG_DRM_FBDEV_EMULATION
14815 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14816 {
14817 }
14818 #endif
14819
14820 static const struct drm_mode_config_funcs intel_mode_funcs = {
14821 .fb_create = intel_user_framebuffer_create,
14822 .output_poll_changed = intel_fbdev_output_poll_changed,
14823 .atomic_check = intel_atomic_check,
14824 .atomic_commit = intel_atomic_commit,
14825 .atomic_state_alloc = intel_atomic_state_alloc,
14826 .atomic_state_clear = intel_atomic_state_clear,
14827 };
14828
14829 /* Set up chip specific display functions */
14830 static void intel_init_display(struct drm_device *dev)
14831 {
14832 struct drm_i915_private *dev_priv = dev->dev_private;
14833
14834 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14835 dev_priv->display.find_dpll = g4x_find_best_dpll;
14836 else if (IS_CHERRYVIEW(dev))
14837 dev_priv->display.find_dpll = chv_find_best_dpll;
14838 else if (IS_VALLEYVIEW(dev))
14839 dev_priv->display.find_dpll = vlv_find_best_dpll;
14840 else if (IS_PINEVIEW(dev))
14841 dev_priv->display.find_dpll = pnv_find_best_dpll;
14842 else
14843 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14844
14845 if (INTEL_INFO(dev)->gen >= 9) {
14846 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14847 dev_priv->display.get_initial_plane_config =
14848 skylake_get_initial_plane_config;
14849 dev_priv->display.crtc_compute_clock =
14850 haswell_crtc_compute_clock;
14851 dev_priv->display.crtc_enable = haswell_crtc_enable;
14852 dev_priv->display.crtc_disable = haswell_crtc_disable;
14853 dev_priv->display.update_primary_plane =
14854 skylake_update_primary_plane;
14855 } else if (HAS_DDI(dev)) {
14856 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14857 dev_priv->display.get_initial_plane_config =
14858 ironlake_get_initial_plane_config;
14859 dev_priv->display.crtc_compute_clock =
14860 haswell_crtc_compute_clock;
14861 dev_priv->display.crtc_enable = haswell_crtc_enable;
14862 dev_priv->display.crtc_disable = haswell_crtc_disable;
14863 dev_priv->display.update_primary_plane =
14864 ironlake_update_primary_plane;
14865 } else if (HAS_PCH_SPLIT(dev)) {
14866 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14867 dev_priv->display.get_initial_plane_config =
14868 ironlake_get_initial_plane_config;
14869 dev_priv->display.crtc_compute_clock =
14870 ironlake_crtc_compute_clock;
14871 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14872 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14873 dev_priv->display.update_primary_plane =
14874 ironlake_update_primary_plane;
14875 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14876 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14877 dev_priv->display.get_initial_plane_config =
14878 i9xx_get_initial_plane_config;
14879 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14880 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14881 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14882 dev_priv->display.update_primary_plane =
14883 i9xx_update_primary_plane;
14884 } else {
14885 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14886 dev_priv->display.get_initial_plane_config =
14887 i9xx_get_initial_plane_config;
14888 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14889 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14890 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14891 dev_priv->display.update_primary_plane =
14892 i9xx_update_primary_plane;
14893 }
14894
14895 /* Returns the core display clock speed */
14896 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14897 dev_priv->display.get_display_clock_speed =
14898 skylake_get_display_clock_speed;
14899 else if (IS_BROXTON(dev))
14900 dev_priv->display.get_display_clock_speed =
14901 broxton_get_display_clock_speed;
14902 else if (IS_BROADWELL(dev))
14903 dev_priv->display.get_display_clock_speed =
14904 broadwell_get_display_clock_speed;
14905 else if (IS_HASWELL(dev))
14906 dev_priv->display.get_display_clock_speed =
14907 haswell_get_display_clock_speed;
14908 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
14909 dev_priv->display.get_display_clock_speed =
14910 valleyview_get_display_clock_speed;
14911 else if (IS_GEN5(dev))
14912 dev_priv->display.get_display_clock_speed =
14913 ilk_get_display_clock_speed;
14914 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14915 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14916 dev_priv->display.get_display_clock_speed =
14917 i945_get_display_clock_speed;
14918 else if (IS_GM45(dev))
14919 dev_priv->display.get_display_clock_speed =
14920 gm45_get_display_clock_speed;
14921 else if (IS_CRESTLINE(dev))
14922 dev_priv->display.get_display_clock_speed =
14923 i965gm_get_display_clock_speed;
14924 else if (IS_PINEVIEW(dev))
14925 dev_priv->display.get_display_clock_speed =
14926 pnv_get_display_clock_speed;
14927 else if (IS_G33(dev) || IS_G4X(dev))
14928 dev_priv->display.get_display_clock_speed =
14929 g33_get_display_clock_speed;
14930 else if (IS_I915G(dev))
14931 dev_priv->display.get_display_clock_speed =
14932 i915_get_display_clock_speed;
14933 else if (IS_I945GM(dev) || IS_845G(dev))
14934 dev_priv->display.get_display_clock_speed =
14935 i9xx_misc_get_display_clock_speed;
14936 else if (IS_I915GM(dev))
14937 dev_priv->display.get_display_clock_speed =
14938 i915gm_get_display_clock_speed;
14939 else if (IS_I865G(dev))
14940 dev_priv->display.get_display_clock_speed =
14941 i865_get_display_clock_speed;
14942 else if (IS_I85X(dev))
14943 dev_priv->display.get_display_clock_speed =
14944 i85x_get_display_clock_speed;
14945 else { /* 830 */
14946 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14947 dev_priv->display.get_display_clock_speed =
14948 i830_get_display_clock_speed;
14949 }
14950
14951 if (IS_GEN5(dev)) {
14952 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14953 } else if (IS_GEN6(dev)) {
14954 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14955 } else if (IS_IVYBRIDGE(dev)) {
14956 /* FIXME: detect B0+ stepping and use auto training */
14957 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14958 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14959 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14960 if (IS_BROADWELL(dev)) {
14961 dev_priv->display.modeset_commit_cdclk =
14962 broadwell_modeset_commit_cdclk;
14963 dev_priv->display.modeset_calc_cdclk =
14964 broadwell_modeset_calc_cdclk;
14965 }
14966 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14967 dev_priv->display.modeset_commit_cdclk =
14968 valleyview_modeset_commit_cdclk;
14969 dev_priv->display.modeset_calc_cdclk =
14970 valleyview_modeset_calc_cdclk;
14971 } else if (IS_BROXTON(dev)) {
14972 dev_priv->display.modeset_commit_cdclk =
14973 broxton_modeset_commit_cdclk;
14974 dev_priv->display.modeset_calc_cdclk =
14975 broxton_modeset_calc_cdclk;
14976 }
14977
14978 switch (INTEL_INFO(dev)->gen) {
14979 case 2:
14980 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14981 break;
14982
14983 case 3:
14984 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14985 break;
14986
14987 case 4:
14988 case 5:
14989 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14990 break;
14991
14992 case 6:
14993 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14994 break;
14995 case 7:
14996 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14997 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14998 break;
14999 case 9:
15000 /* Drop through - unsupported since execlist only. */
15001 default:
15002 /* Default just returns -ENODEV to indicate unsupported */
15003 dev_priv->display.queue_flip = intel_default_queue_flip;
15004 }
15005
15006 mutex_init(&dev_priv->pps_mutex);
15007 }
15008
15009 /*
15010 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15011 * resume, or other times. This quirk makes sure that's the case for
15012 * affected systems.
15013 */
15014 static void quirk_pipea_force(struct drm_device *dev)
15015 {
15016 struct drm_i915_private *dev_priv = dev->dev_private;
15017
15018 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15019 DRM_INFO("applying pipe a force quirk\n");
15020 }
15021
15022 static void quirk_pipeb_force(struct drm_device *dev)
15023 {
15024 struct drm_i915_private *dev_priv = dev->dev_private;
15025
15026 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15027 DRM_INFO("applying pipe b force quirk\n");
15028 }
15029
15030 /*
15031 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15032 */
15033 static void quirk_ssc_force_disable(struct drm_device *dev)
15034 {
15035 struct drm_i915_private *dev_priv = dev->dev_private;
15036 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15037 DRM_INFO("applying lvds SSC disable quirk\n");
15038 }
15039
15040 /*
15041 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15042 * brightness value
15043 */
15044 static void quirk_invert_brightness(struct drm_device *dev)
15045 {
15046 struct drm_i915_private *dev_priv = dev->dev_private;
15047 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15048 DRM_INFO("applying inverted panel brightness quirk\n");
15049 }
15050
15051 /* Some VBT's incorrectly indicate no backlight is present */
15052 static void quirk_backlight_present(struct drm_device *dev)
15053 {
15054 struct drm_i915_private *dev_priv = dev->dev_private;
15055 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15056 DRM_INFO("applying backlight present quirk\n");
15057 }
15058
15059 struct intel_quirk {
15060 int device;
15061 int subsystem_vendor;
15062 int subsystem_device;
15063 void (*hook)(struct drm_device *dev);
15064 };
15065
15066 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15067 struct intel_dmi_quirk {
15068 void (*hook)(struct drm_device *dev);
15069 const struct dmi_system_id (*dmi_id_list)[];
15070 };
15071
15072 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15073 {
15074 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15075 return 1;
15076 }
15077
15078 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15079 {
15080 .dmi_id_list = &(const struct dmi_system_id[]) {
15081 {
15082 .callback = intel_dmi_reverse_brightness,
15083 .ident = "NCR Corporation",
15084 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15085 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15086 },
15087 },
15088 { } /* terminating entry */
15089 },
15090 .hook = quirk_invert_brightness,
15091 },
15092 };
15093
15094 static struct intel_quirk intel_quirks[] = {
15095 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15096 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15097
15098 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15099 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15100
15101 /* 830 needs to leave pipe A & dpll A up */
15102 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15103
15104 /* 830 needs to leave pipe B & dpll B up */
15105 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15106
15107 /* Lenovo U160 cannot use SSC on LVDS */
15108 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15109
15110 /* Sony Vaio Y cannot use SSC on LVDS */
15111 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15112
15113 /* Acer Aspire 5734Z must invert backlight brightness */
15114 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15115
15116 /* Acer/eMachines G725 */
15117 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15118
15119 /* Acer/eMachines e725 */
15120 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15121
15122 /* Acer/Packard Bell NCL20 */
15123 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15124
15125 /* Acer Aspire 4736Z */
15126 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15127
15128 /* Acer Aspire 5336 */
15129 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15130
15131 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15132 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15133
15134 /* Acer C720 Chromebook (Core i3 4005U) */
15135 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15136
15137 /* Apple Macbook 2,1 (Core 2 T7400) */
15138 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15139
15140 /* Apple Macbook 4,1 */
15141 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15142
15143 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15144 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15145
15146 /* HP Chromebook 14 (Celeron 2955U) */
15147 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15148
15149 /* Dell Chromebook 11 */
15150 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15151
15152 /* Dell Chromebook 11 (2015 version) */
15153 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15154 };
15155
15156 static void intel_init_quirks(struct drm_device *dev)
15157 {
15158 struct pci_dev *d = dev->pdev;
15159 int i;
15160
15161 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15162 struct intel_quirk *q = &intel_quirks[i];
15163
15164 if (d->device == q->device &&
15165 (d->subsystem_vendor == q->subsystem_vendor ||
15166 q->subsystem_vendor == PCI_ANY_ID) &&
15167 (d->subsystem_device == q->subsystem_device ||
15168 q->subsystem_device == PCI_ANY_ID))
15169 q->hook(dev);
15170 }
15171 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15172 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15173 intel_dmi_quirks[i].hook(dev);
15174 }
15175 }
15176
15177 /* Disable the VGA plane that we never use */
15178 static void i915_disable_vga(struct drm_device *dev)
15179 {
15180 struct drm_i915_private *dev_priv = dev->dev_private;
15181 u8 sr1;
15182 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15183
15184 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15185 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15186 outb(SR01, VGA_SR_INDEX);
15187 sr1 = inb(VGA_SR_DATA);
15188 outb(sr1 | 1<<5, VGA_SR_DATA);
15189 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15190 udelay(300);
15191
15192 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15193 POSTING_READ(vga_reg);
15194 }
15195
15196 void intel_modeset_init_hw(struct drm_device *dev)
15197 {
15198 intel_update_cdclk(dev);
15199 intel_prepare_ddi(dev);
15200 intel_init_clock_gating(dev);
15201 intel_enable_gt_powersave(dev);
15202 }
15203
15204 void intel_modeset_init(struct drm_device *dev)
15205 {
15206 struct drm_i915_private *dev_priv = dev->dev_private;
15207 int sprite, ret;
15208 enum pipe pipe;
15209 struct intel_crtc *crtc;
15210
15211 drm_mode_config_init(dev);
15212
15213 dev->mode_config.min_width = 0;
15214 dev->mode_config.min_height = 0;
15215
15216 dev->mode_config.preferred_depth = 24;
15217 dev->mode_config.prefer_shadow = 1;
15218
15219 dev->mode_config.allow_fb_modifiers = true;
15220
15221 dev->mode_config.funcs = &intel_mode_funcs;
15222
15223 intel_init_quirks(dev);
15224
15225 intel_init_pm(dev);
15226
15227 if (INTEL_INFO(dev)->num_pipes == 0)
15228 return;
15229
15230 /*
15231 * There may be no VBT; and if the BIOS enabled SSC we can
15232 * just keep using it to avoid unnecessary flicker. Whereas if the
15233 * BIOS isn't using it, don't assume it will work even if the VBT
15234 * indicates as much.
15235 */
15236 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15237 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15238 DREF_SSC1_ENABLE);
15239
15240 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15241 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15242 bios_lvds_use_ssc ? "en" : "dis",
15243 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15244 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15245 }
15246 }
15247
15248 intel_init_display(dev);
15249 intel_init_audio(dev);
15250
15251 if (IS_GEN2(dev)) {
15252 dev->mode_config.max_width = 2048;
15253 dev->mode_config.max_height = 2048;
15254 } else if (IS_GEN3(dev)) {
15255 dev->mode_config.max_width = 4096;
15256 dev->mode_config.max_height = 4096;
15257 } else {
15258 dev->mode_config.max_width = 8192;
15259 dev->mode_config.max_height = 8192;
15260 }
15261
15262 if (IS_845G(dev) || IS_I865G(dev)) {
15263 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15264 dev->mode_config.cursor_height = 1023;
15265 } else if (IS_GEN2(dev)) {
15266 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15267 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15268 } else {
15269 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15270 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15271 }
15272
15273 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15274
15275 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15276 INTEL_INFO(dev)->num_pipes,
15277 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15278
15279 for_each_pipe(dev_priv, pipe) {
15280 intel_crtc_init(dev, pipe);
15281 for_each_sprite(dev_priv, pipe, sprite) {
15282 ret = intel_plane_init(dev, pipe, sprite);
15283 if (ret)
15284 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15285 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15286 }
15287 }
15288
15289 intel_update_czclk(dev_priv);
15290 intel_update_cdclk(dev);
15291
15292 intel_shared_dpll_init(dev);
15293
15294 /* Just disable it once at startup */
15295 i915_disable_vga(dev);
15296 intel_setup_outputs(dev);
15297
15298 drm_modeset_lock_all(dev);
15299 intel_modeset_setup_hw_state(dev);
15300 drm_modeset_unlock_all(dev);
15301
15302 for_each_intel_crtc(dev, crtc) {
15303 struct intel_initial_plane_config plane_config = {};
15304
15305 if (!crtc->active)
15306 continue;
15307
15308 /*
15309 * Note that reserving the BIOS fb up front prevents us
15310 * from stuffing other stolen allocations like the ring
15311 * on top. This prevents some ugliness at boot time, and
15312 * can even allow for smooth boot transitions if the BIOS
15313 * fb is large enough for the active pipe configuration.
15314 */
15315 dev_priv->display.get_initial_plane_config(crtc,
15316 &plane_config);
15317
15318 /*
15319 * If the fb is shared between multiple heads, we'll
15320 * just get the first one.
15321 */
15322 intel_find_initial_plane_obj(crtc, &plane_config);
15323 }
15324 }
15325
15326 static void intel_enable_pipe_a(struct drm_device *dev)
15327 {
15328 struct intel_connector *connector;
15329 struct drm_connector *crt = NULL;
15330 struct intel_load_detect_pipe load_detect_temp;
15331 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15332
15333 /* We can't just switch on the pipe A, we need to set things up with a
15334 * proper mode and output configuration. As a gross hack, enable pipe A
15335 * by enabling the load detect pipe once. */
15336 for_each_intel_connector(dev, connector) {
15337 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15338 crt = &connector->base;
15339 break;
15340 }
15341 }
15342
15343 if (!crt)
15344 return;
15345
15346 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15347 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15348 }
15349
15350 static bool
15351 intel_check_plane_mapping(struct intel_crtc *crtc)
15352 {
15353 struct drm_device *dev = crtc->base.dev;
15354 struct drm_i915_private *dev_priv = dev->dev_private;
15355 u32 val;
15356
15357 if (INTEL_INFO(dev)->num_pipes == 1)
15358 return true;
15359
15360 val = I915_READ(DSPCNTR(!crtc->plane));
15361
15362 if ((val & DISPLAY_PLANE_ENABLE) &&
15363 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15364 return false;
15365
15366 return true;
15367 }
15368
15369 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15370 {
15371 struct drm_device *dev = crtc->base.dev;
15372 struct intel_encoder *encoder;
15373
15374 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15375 return true;
15376
15377 return false;
15378 }
15379
15380 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15381 {
15382 struct drm_device *dev = crtc->base.dev;
15383 struct drm_i915_private *dev_priv = dev->dev_private;
15384 i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder);
15385
15386 /* Clear any frame start delays used for debugging left by the BIOS */
15387 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15388
15389 /* restore vblank interrupts to correct state */
15390 drm_crtc_vblank_reset(&crtc->base);
15391 if (crtc->active) {
15392 struct intel_plane *plane;
15393
15394 drm_crtc_vblank_on(&crtc->base);
15395
15396 /* Disable everything but the primary plane */
15397 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15398 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15399 continue;
15400
15401 plane->disable_plane(&plane->base, &crtc->base);
15402 }
15403 }
15404
15405 /* We need to sanitize the plane -> pipe mapping first because this will
15406 * disable the crtc (and hence change the state) if it is wrong. Note
15407 * that gen4+ has a fixed plane -> pipe mapping. */
15408 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15409 bool plane;
15410
15411 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15412 crtc->base.base.id);
15413
15414 /* Pipe has the wrong plane attached and the plane is active.
15415 * Temporarily change the plane mapping and disable everything
15416 * ... */
15417 plane = crtc->plane;
15418 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15419 crtc->plane = !plane;
15420 intel_crtc_disable_noatomic(&crtc->base);
15421 crtc->plane = plane;
15422 }
15423
15424 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15425 crtc->pipe == PIPE_A && !crtc->active) {
15426 /* BIOS forgot to enable pipe A, this mostly happens after
15427 * resume. Force-enable the pipe to fix this, the update_dpms
15428 * call below we restore the pipe to the right state, but leave
15429 * the required bits on. */
15430 intel_enable_pipe_a(dev);
15431 }
15432
15433 /* Adjust the state of the output pipe according to whether we
15434 * have active connectors/encoders. */
15435 if (!intel_crtc_has_encoders(crtc))
15436 intel_crtc_disable_noatomic(&crtc->base);
15437
15438 if (crtc->active != crtc->base.state->active) {
15439 struct intel_encoder *encoder;
15440
15441 /* This can happen either due to bugs in the get_hw_state
15442 * functions or because of calls to intel_crtc_disable_noatomic,
15443 * or because the pipe is force-enabled due to the
15444 * pipe A quirk. */
15445 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15446 crtc->base.base.id,
15447 crtc->base.state->enable ? "enabled" : "disabled",
15448 crtc->active ? "enabled" : "disabled");
15449
15450 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15451 crtc->base.state->active = crtc->active;
15452 crtc->base.enabled = crtc->active;
15453 crtc->base.state->connector_mask = 0;
15454
15455 /* Because we only establish the connector -> encoder ->
15456 * crtc links if something is active, this means the
15457 * crtc is now deactivated. Break the links. connector
15458 * -> encoder links are only establish when things are
15459 * actually up, hence no need to break them. */
15460 WARN_ON(crtc->active);
15461
15462 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15463 encoder->base.crtc = NULL;
15464 }
15465
15466 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15467 /*
15468 * We start out with underrun reporting disabled to avoid races.
15469 * For correct bookkeeping mark this on active crtcs.
15470 *
15471 * Also on gmch platforms we dont have any hardware bits to
15472 * disable the underrun reporting. Which means we need to start
15473 * out with underrun reporting disabled also on inactive pipes,
15474 * since otherwise we'll complain about the garbage we read when
15475 * e.g. coming up after runtime pm.
15476 *
15477 * No protection against concurrent access is required - at
15478 * worst a fifo underrun happens which also sets this to false.
15479 */
15480 crtc->cpu_fifo_underrun_disabled = true;
15481 crtc->pch_fifo_underrun_disabled = true;
15482 }
15483 }
15484
15485 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15486 {
15487 struct intel_connector *connector;
15488 struct drm_device *dev = encoder->base.dev;
15489 bool active = false;
15490
15491 /* We need to check both for a crtc link (meaning that the
15492 * encoder is active and trying to read from a pipe) and the
15493 * pipe itself being active. */
15494 bool has_active_crtc = encoder->base.crtc &&
15495 to_intel_crtc(encoder->base.crtc)->active;
15496
15497 for_each_intel_connector(dev, connector) {
15498 if (connector->base.encoder != &encoder->base)
15499 continue;
15500
15501 active = true;
15502 break;
15503 }
15504
15505 if (active && !has_active_crtc) {
15506 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15507 encoder->base.base.id,
15508 encoder->base.name);
15509
15510 /* Connector is active, but has no active pipe. This is
15511 * fallout from our resume register restoring. Disable
15512 * the encoder manually again. */
15513 if (encoder->base.crtc) {
15514 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15515 encoder->base.base.id,
15516 encoder->base.name);
15517 encoder->disable(encoder);
15518 if (encoder->post_disable)
15519 encoder->post_disable(encoder);
15520 }
15521 encoder->base.crtc = NULL;
15522
15523 /* Inconsistent output/port/pipe state happens presumably due to
15524 * a bug in one of the get_hw_state functions. Or someplace else
15525 * in our code, like the register restore mess on resume. Clamp
15526 * things to off as a safer default. */
15527 for_each_intel_connector(dev, connector) {
15528 if (connector->encoder != encoder)
15529 continue;
15530 connector->base.dpms = DRM_MODE_DPMS_OFF;
15531 connector->base.encoder = NULL;
15532 }
15533 }
15534 /* Enabled encoders without active connectors will be fixed in
15535 * the crtc fixup. */
15536 }
15537
15538 void i915_redisable_vga_power_on(struct drm_device *dev)
15539 {
15540 struct drm_i915_private *dev_priv = dev->dev_private;
15541 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15542
15543 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15544 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15545 i915_disable_vga(dev);
15546 }
15547 }
15548
15549 void i915_redisable_vga(struct drm_device *dev)
15550 {
15551 struct drm_i915_private *dev_priv = dev->dev_private;
15552
15553 /* This function can be called both from intel_modeset_setup_hw_state or
15554 * at a very early point in our resume sequence, where the power well
15555 * structures are not yet restored. Since this function is at a very
15556 * paranoid "someone might have enabled VGA while we were not looking"
15557 * level, just check if the power well is enabled instead of trying to
15558 * follow the "don't touch the power well if we don't need it" policy
15559 * the rest of the driver uses. */
15560 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15561 return;
15562
15563 i915_redisable_vga_power_on(dev);
15564 }
15565
15566 static bool primary_get_hw_state(struct intel_plane *plane)
15567 {
15568 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15569
15570 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15571 }
15572
15573 /* FIXME read out full plane state for all planes */
15574 static void readout_plane_state(struct intel_crtc *crtc)
15575 {
15576 struct drm_plane *primary = crtc->base.primary;
15577 struct intel_plane_state *plane_state =
15578 to_intel_plane_state(primary->state);
15579
15580 plane_state->visible = crtc->active &&
15581 primary_get_hw_state(to_intel_plane(primary));
15582
15583 if (plane_state->visible)
15584 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15585 }
15586
15587 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15588 {
15589 struct drm_i915_private *dev_priv = dev->dev_private;
15590 enum pipe pipe;
15591 struct intel_crtc *crtc;
15592 struct intel_encoder *encoder;
15593 struct intel_connector *connector;
15594 int i;
15595
15596 for_each_intel_crtc(dev, crtc) {
15597 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15598 memset(crtc->config, 0, sizeof(*crtc->config));
15599 crtc->config->base.crtc = &crtc->base;
15600
15601 crtc->active = dev_priv->display.get_pipe_config(crtc,
15602 crtc->config);
15603
15604 crtc->base.state->active = crtc->active;
15605 crtc->base.enabled = crtc->active;
15606
15607 readout_plane_state(crtc);
15608
15609 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15610 crtc->base.base.id,
15611 crtc->active ? "enabled" : "disabled");
15612 }
15613
15614 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15615 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15616
15617 pll->on = pll->get_hw_state(dev_priv, pll,
15618 &pll->config.hw_state);
15619 pll->active = 0;
15620 pll->config.crtc_mask = 0;
15621 for_each_intel_crtc(dev, crtc) {
15622 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15623 pll->active++;
15624 pll->config.crtc_mask |= 1 << crtc->pipe;
15625 }
15626 }
15627
15628 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15629 pll->name, pll->config.crtc_mask, pll->on);
15630
15631 if (pll->config.crtc_mask)
15632 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15633 }
15634
15635 for_each_intel_encoder(dev, encoder) {
15636 pipe = 0;
15637
15638 if (encoder->get_hw_state(encoder, &pipe)) {
15639 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15640 encoder->base.crtc = &crtc->base;
15641 encoder->get_config(encoder, crtc->config);
15642 } else {
15643 encoder->base.crtc = NULL;
15644 }
15645
15646 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15647 encoder->base.base.id,
15648 encoder->base.name,
15649 encoder->base.crtc ? "enabled" : "disabled",
15650 pipe_name(pipe));
15651 }
15652
15653 for_each_intel_connector(dev, connector) {
15654 if (connector->get_hw_state(connector)) {
15655 connector->base.dpms = DRM_MODE_DPMS_ON;
15656
15657 encoder = connector->encoder;
15658 connector->base.encoder = &encoder->base;
15659
15660 if (encoder->base.crtc &&
15661 encoder->base.crtc->state->active) {
15662 /*
15663 * This has to be done during hardware readout
15664 * because anything calling .crtc_disable may
15665 * rely on the connector_mask being accurate.
15666 */
15667 encoder->base.crtc->state->connector_mask |=
15668 1 << drm_connector_index(&connector->base);
15669 }
15670
15671 } else {
15672 connector->base.dpms = DRM_MODE_DPMS_OFF;
15673 connector->base.encoder = NULL;
15674 }
15675 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15676 connector->base.base.id,
15677 connector->base.name,
15678 connector->base.encoder ? "enabled" : "disabled");
15679 }
15680
15681 for_each_intel_crtc(dev, crtc) {
15682 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15683
15684 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15685 if (crtc->base.state->active) {
15686 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15687 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15688 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15689
15690 /*
15691 * The initial mode needs to be set in order to keep
15692 * the atomic core happy. It wants a valid mode if the
15693 * crtc's enabled, so we do the above call.
15694 *
15695 * At this point some state updated by the connectors
15696 * in their ->detect() callback has not run yet, so
15697 * no recalculation can be done yet.
15698 *
15699 * Even if we could do a recalculation and modeset
15700 * right now it would cause a double modeset if
15701 * fbdev or userspace chooses a different initial mode.
15702 *
15703 * If that happens, someone indicated they wanted a
15704 * mode change, which means it's safe to do a full
15705 * recalculation.
15706 */
15707 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15708
15709 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15710 update_scanline_offset(crtc);
15711 }
15712 }
15713 }
15714
15715 /* Scan out the current hw modeset state,
15716 * and sanitizes it to the current state
15717 */
15718 static void
15719 intel_modeset_setup_hw_state(struct drm_device *dev)
15720 {
15721 struct drm_i915_private *dev_priv = dev->dev_private;
15722 enum pipe pipe;
15723 struct intel_crtc *crtc;
15724 struct intel_encoder *encoder;
15725 int i;
15726
15727 intel_modeset_readout_hw_state(dev);
15728
15729 /* HW state is read out, now we need to sanitize this mess. */
15730 for_each_intel_encoder(dev, encoder) {
15731 intel_sanitize_encoder(encoder);
15732 }
15733
15734 for_each_pipe(dev_priv, pipe) {
15735 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15736 intel_sanitize_crtc(crtc);
15737 intel_dump_pipe_config(crtc, crtc->config,
15738 "[setup_hw_state]");
15739 }
15740
15741 intel_modeset_update_connector_atomic_state(dev);
15742
15743 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15744 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15745
15746 if (!pll->on || pll->active)
15747 continue;
15748
15749 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15750
15751 pll->disable(dev_priv, pll);
15752 pll->on = false;
15753 }
15754
15755 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15756 vlv_wm_get_hw_state(dev);
15757 else if (IS_GEN9(dev))
15758 skl_wm_get_hw_state(dev);
15759 else if (HAS_PCH_SPLIT(dev))
15760 ilk_wm_get_hw_state(dev);
15761
15762 for_each_intel_crtc(dev, crtc) {
15763 unsigned long put_domains;
15764
15765 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15766 if (WARN_ON(put_domains))
15767 modeset_put_power_domains(dev_priv, put_domains);
15768 }
15769 intel_display_set_init_power(dev_priv, false);
15770 }
15771
15772 void intel_display_resume(struct drm_device *dev)
15773 {
15774 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15775 struct intel_connector *conn;
15776 struct intel_plane *plane;
15777 struct drm_crtc *crtc;
15778 int ret;
15779
15780 if (!state)
15781 return;
15782
15783 state->acquire_ctx = dev->mode_config.acquire_ctx;
15784
15785 /* preserve complete old state, including dpll */
15786 intel_atomic_get_shared_dpll_state(state);
15787
15788 for_each_crtc(dev, crtc) {
15789 struct drm_crtc_state *crtc_state =
15790 drm_atomic_get_crtc_state(state, crtc);
15791
15792 ret = PTR_ERR_OR_ZERO(crtc_state);
15793 if (ret)
15794 goto err;
15795
15796 /* force a restore */
15797 crtc_state->mode_changed = true;
15798 }
15799
15800 for_each_intel_plane(dev, plane) {
15801 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15802 if (ret)
15803 goto err;
15804 }
15805
15806 for_each_intel_connector(dev, conn) {
15807 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15808 if (ret)
15809 goto err;
15810 }
15811
15812 intel_modeset_setup_hw_state(dev);
15813
15814 i915_redisable_vga(dev);
15815 ret = drm_atomic_commit(state);
15816 if (!ret)
15817 return;
15818
15819 err:
15820 DRM_ERROR("Restoring old state failed with %i\n", ret);
15821 drm_atomic_state_free(state);
15822 }
15823
15824 void intel_modeset_gem_init(struct drm_device *dev)
15825 {
15826 struct drm_crtc *c;
15827 struct drm_i915_gem_object *obj;
15828 int ret;
15829
15830 mutex_lock(&dev->struct_mutex);
15831 intel_init_gt_powersave(dev);
15832 mutex_unlock(&dev->struct_mutex);
15833
15834 intel_modeset_init_hw(dev);
15835
15836 intel_setup_overlay(dev);
15837
15838 /*
15839 * Make sure any fbs we allocated at startup are properly
15840 * pinned & fenced. When we do the allocation it's too early
15841 * for this.
15842 */
15843 for_each_crtc(dev, c) {
15844 obj = intel_fb_obj(c->primary->fb);
15845 if (obj == NULL)
15846 continue;
15847
15848 mutex_lock(&dev->struct_mutex);
15849 ret = intel_pin_and_fence_fb_obj(c->primary,
15850 c->primary->fb,
15851 c->primary->state);
15852 mutex_unlock(&dev->struct_mutex);
15853 if (ret) {
15854 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15855 to_intel_crtc(c)->pipe);
15856 drm_framebuffer_unreference(c->primary->fb);
15857 c->primary->fb = NULL;
15858 c->primary->crtc = c->primary->state->crtc = NULL;
15859 update_state_fb(c->primary);
15860 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15861 }
15862 }
15863
15864 intel_backlight_register(dev);
15865 }
15866
15867 void intel_connector_unregister(struct intel_connector *intel_connector)
15868 {
15869 struct drm_connector *connector = &intel_connector->base;
15870
15871 intel_panel_destroy_backlight(connector);
15872 drm_connector_unregister(connector);
15873 }
15874
15875 void intel_modeset_cleanup(struct drm_device *dev)
15876 {
15877 struct drm_i915_private *dev_priv = dev->dev_private;
15878 struct intel_connector *connector;
15879
15880 intel_disable_gt_powersave(dev);
15881
15882 intel_backlight_unregister(dev);
15883
15884 /*
15885 * Interrupts and polling as the first thing to avoid creating havoc.
15886 * Too much stuff here (turning of connectors, ...) would
15887 * experience fancy races otherwise.
15888 */
15889 intel_irq_uninstall(dev_priv);
15890
15891 /*
15892 * Due to the hpd irq storm handling the hotplug work can re-arm the
15893 * poll handlers. Hence disable polling after hpd handling is shut down.
15894 */
15895 drm_kms_helper_poll_fini(dev);
15896
15897 intel_unregister_dsm_handler();
15898
15899 intel_fbc_disable(dev_priv);
15900
15901 /* flush any delayed tasks or pending work */
15902 flush_scheduled_work();
15903
15904 /* destroy the backlight and sysfs files before encoders/connectors */
15905 for_each_intel_connector(dev, connector)
15906 connector->unregister(connector);
15907
15908 drm_mode_config_cleanup(dev);
15909
15910 intel_cleanup_overlay(dev);
15911
15912 mutex_lock(&dev->struct_mutex);
15913 intel_cleanup_gt_powersave(dev);
15914 mutex_unlock(&dev->struct_mutex);
15915
15916 intel_teardown_gmbus(dev);
15917 }
15918
15919 /*
15920 * Return which encoder is currently attached for connector.
15921 */
15922 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15923 {
15924 return &intel_attached_encoder(connector)->base;
15925 }
15926
15927 void intel_connector_attach_encoder(struct intel_connector *connector,
15928 struct intel_encoder *encoder)
15929 {
15930 connector->encoder = encoder;
15931 drm_mode_connector_attach_encoder(&connector->base,
15932 &encoder->base);
15933 }
15934
15935 /*
15936 * set vga decode state - true == enable VGA decode
15937 */
15938 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15939 {
15940 struct drm_i915_private *dev_priv = dev->dev_private;
15941 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15942 u16 gmch_ctrl;
15943
15944 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15945 DRM_ERROR("failed to read control word\n");
15946 return -EIO;
15947 }
15948
15949 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15950 return 0;
15951
15952 if (state)
15953 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15954 else
15955 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15956
15957 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15958 DRM_ERROR("failed to write control word\n");
15959 return -EIO;
15960 }
15961
15962 return 0;
15963 }
15964
15965 struct intel_display_error_state {
15966
15967 u32 power_well_driver;
15968
15969 int num_transcoders;
15970
15971 struct intel_cursor_error_state {
15972 u32 control;
15973 u32 position;
15974 u32 base;
15975 u32 size;
15976 } cursor[I915_MAX_PIPES];
15977
15978 struct intel_pipe_error_state {
15979 bool power_domain_on;
15980 u32 source;
15981 u32 stat;
15982 } pipe[I915_MAX_PIPES];
15983
15984 struct intel_plane_error_state {
15985 u32 control;
15986 u32 stride;
15987 u32 size;
15988 u32 pos;
15989 u32 addr;
15990 u32 surface;
15991 u32 tile_offset;
15992 } plane[I915_MAX_PIPES];
15993
15994 struct intel_transcoder_error_state {
15995 bool power_domain_on;
15996 enum transcoder cpu_transcoder;
15997
15998 u32 conf;
15999
16000 u32 htotal;
16001 u32 hblank;
16002 u32 hsync;
16003 u32 vtotal;
16004 u32 vblank;
16005 u32 vsync;
16006 } transcoder[4];
16007 };
16008
16009 struct intel_display_error_state *
16010 intel_display_capture_error_state(struct drm_device *dev)
16011 {
16012 struct drm_i915_private *dev_priv = dev->dev_private;
16013 struct intel_display_error_state *error;
16014 int transcoders[] = {
16015 TRANSCODER_A,
16016 TRANSCODER_B,
16017 TRANSCODER_C,
16018 TRANSCODER_EDP,
16019 };
16020 int i;
16021
16022 if (INTEL_INFO(dev)->num_pipes == 0)
16023 return NULL;
16024
16025 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16026 if (error == NULL)
16027 return NULL;
16028
16029 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16030 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16031
16032 for_each_pipe(dev_priv, i) {
16033 error->pipe[i].power_domain_on =
16034 __intel_display_power_is_enabled(dev_priv,
16035 POWER_DOMAIN_PIPE(i));
16036 if (!error->pipe[i].power_domain_on)
16037 continue;
16038
16039 error->cursor[i].control = I915_READ(CURCNTR(i));
16040 error->cursor[i].position = I915_READ(CURPOS(i));
16041 error->cursor[i].base = I915_READ(CURBASE(i));
16042
16043 error->plane[i].control = I915_READ(DSPCNTR(i));
16044 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16045 if (INTEL_INFO(dev)->gen <= 3) {
16046 error->plane[i].size = I915_READ(DSPSIZE(i));
16047 error->plane[i].pos = I915_READ(DSPPOS(i));
16048 }
16049 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16050 error->plane[i].addr = I915_READ(DSPADDR(i));
16051 if (INTEL_INFO(dev)->gen >= 4) {
16052 error->plane[i].surface = I915_READ(DSPSURF(i));
16053 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16054 }
16055
16056 error->pipe[i].source = I915_READ(PIPESRC(i));
16057
16058 if (HAS_GMCH_DISPLAY(dev))
16059 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16060 }
16061
16062 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
16063 if (HAS_DDI(dev_priv->dev))
16064 error->num_transcoders++; /* Account for eDP. */
16065
16066 for (i = 0; i < error->num_transcoders; i++) {
16067 enum transcoder cpu_transcoder = transcoders[i];
16068
16069 error->transcoder[i].power_domain_on =
16070 __intel_display_power_is_enabled(dev_priv,
16071 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16072 if (!error->transcoder[i].power_domain_on)
16073 continue;
16074
16075 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16076
16077 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16078 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16079 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16080 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16081 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16082 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16083 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16084 }
16085
16086 return error;
16087 }
16088
16089 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16090
16091 void
16092 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16093 struct drm_device *dev,
16094 struct intel_display_error_state *error)
16095 {
16096 struct drm_i915_private *dev_priv = dev->dev_private;
16097 int i;
16098
16099 if (!error)
16100 return;
16101
16102 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16103 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16104 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16105 error->power_well_driver);
16106 for_each_pipe(dev_priv, i) {
16107 err_printf(m, "Pipe [%d]:\n", i);
16108 err_printf(m, " Power: %s\n",
16109 error->pipe[i].power_domain_on ? "on" : "off");
16110 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16111 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16112
16113 err_printf(m, "Plane [%d]:\n", i);
16114 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16115 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16116 if (INTEL_INFO(dev)->gen <= 3) {
16117 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16118 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16119 }
16120 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16121 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16122 if (INTEL_INFO(dev)->gen >= 4) {
16123 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16124 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16125 }
16126
16127 err_printf(m, "Cursor [%d]:\n", i);
16128 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16129 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16130 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16131 }
16132
16133 for (i = 0; i < error->num_transcoders; i++) {
16134 err_printf(m, "CPU transcoder: %c\n",
16135 transcoder_name(error->transcoder[i].cpu_transcoder));
16136 err_printf(m, " Power: %s\n",
16137 error->transcoder[i].power_domain_on ? "on" : "off");
16138 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16139 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16140 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16141 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16142 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16143 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16144 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16145 }
16146 }
16147
16148 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
16149 {
16150 struct intel_crtc *crtc;
16151
16152 for_each_intel_crtc(dev, crtc) {
16153 struct intel_unpin_work *work;
16154
16155 spin_lock_irq(&dev->event_lock);
16156
16157 work = crtc->unpin_work;
16158
16159 if (work && work->event &&
16160 work->event->base.file_priv == file) {
16161 kfree(work->event);
16162 work->event = NULL;
16163 }
16164
16165 spin_unlock_irq(&dev->event_lock);
16166 }
16167 }
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