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drm/i915: Prune the reservation shared fence array
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "i915_gem_clflush.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
51
52 /* Primary plane formats for gen <= 3 */
53 static const uint32_t i8xx_primary_formats[] = {
54 DRM_FORMAT_C8,
55 DRM_FORMAT_RGB565,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_XRGB8888,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t i965_primary_formats[] = {
62 DRM_FORMAT_C8,
63 DRM_FORMAT_RGB565,
64 DRM_FORMAT_XRGB8888,
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_XRGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 };
69
70 static const uint64_t i9xx_format_modifiers[] = {
71 I915_FORMAT_MOD_X_TILED,
72 DRM_FORMAT_MOD_LINEAR,
73 DRM_FORMAT_MOD_INVALID
74 };
75
76 static const uint32_t skl_primary_formats[] = {
77 DRM_FORMAT_C8,
78 DRM_FORMAT_RGB565,
79 DRM_FORMAT_XRGB8888,
80 DRM_FORMAT_XBGR8888,
81 DRM_FORMAT_ARGB8888,
82 DRM_FORMAT_ABGR8888,
83 DRM_FORMAT_XRGB2101010,
84 DRM_FORMAT_XBGR2101010,
85 DRM_FORMAT_YUYV,
86 DRM_FORMAT_YVYU,
87 DRM_FORMAT_UYVY,
88 DRM_FORMAT_VYUY,
89 };
90
91 static const uint64_t skl_format_modifiers_noccs[] = {
92 I915_FORMAT_MOD_Yf_TILED,
93 I915_FORMAT_MOD_Y_TILED,
94 I915_FORMAT_MOD_X_TILED,
95 DRM_FORMAT_MOD_LINEAR,
96 DRM_FORMAT_MOD_INVALID
97 };
98
99 static const uint64_t skl_format_modifiers_ccs[] = {
100 I915_FORMAT_MOD_Yf_TILED_CCS,
101 I915_FORMAT_MOD_Y_TILED_CCS,
102 I915_FORMAT_MOD_Yf_TILED,
103 I915_FORMAT_MOD_Y_TILED,
104 I915_FORMAT_MOD_X_TILED,
105 DRM_FORMAT_MOD_LINEAR,
106 DRM_FORMAT_MOD_INVALID
107 };
108
109 /* Cursor formats */
110 static const uint32_t intel_cursor_formats[] = {
111 DRM_FORMAT_ARGB8888,
112 };
113
114 static const uint64_t cursor_format_modifiers[] = {
115 DRM_FORMAT_MOD_LINEAR,
116 DRM_FORMAT_MOD_INVALID
117 };
118
119 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
120 struct intel_crtc_state *pipe_config);
121 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
122 struct intel_crtc_state *pipe_config);
123
124 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
125 struct drm_i915_gem_object *obj,
126 struct drm_mode_fb_cmd2 *mode_cmd);
127 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
128 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
129 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
130 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
131 struct intel_link_m_n *m_n,
132 struct intel_link_m_n *m2_n2);
133 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
134 static void haswell_set_pipeconf(struct drm_crtc *crtc);
135 static void haswell_set_pipemisc(struct drm_crtc *crtc);
136 static void vlv_prepare_pll(struct intel_crtc *crtc,
137 const struct intel_crtc_state *pipe_config);
138 static void chv_prepare_pll(struct intel_crtc *crtc,
139 const struct intel_crtc_state *pipe_config);
140 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
141 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
142 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
143 struct intel_crtc_state *crtc_state);
144 static void skylake_pfit_enable(struct intel_crtc *crtc);
145 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
146 static void ironlake_pfit_enable(struct intel_crtc *crtc);
147 static void intel_modeset_setup_hw_state(struct drm_device *dev,
148 struct drm_modeset_acquire_ctx *ctx);
149 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
150
151 struct intel_limit {
152 struct {
153 int min, max;
154 } dot, vco, n, m, m1, m2, p, p1;
155
156 struct {
157 int dot_limit;
158 int p2_slow, p2_fast;
159 } p2;
160 };
161
162 /* returns HPLL frequency in kHz */
163 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
164 {
165 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
166
167 /* Obtain SKU information */
168 mutex_lock(&dev_priv->sb_lock);
169 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
170 CCK_FUSE_HPLL_FREQ_MASK;
171 mutex_unlock(&dev_priv->sb_lock);
172
173 return vco_freq[hpll_freq] * 1000;
174 }
175
176 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
177 const char *name, u32 reg, int ref_freq)
178 {
179 u32 val;
180 int divider;
181
182 mutex_lock(&dev_priv->sb_lock);
183 val = vlv_cck_read(dev_priv, reg);
184 mutex_unlock(&dev_priv->sb_lock);
185
186 divider = val & CCK_FREQUENCY_VALUES;
187
188 WARN((val & CCK_FREQUENCY_STATUS) !=
189 (divider << CCK_FREQUENCY_STATUS_SHIFT),
190 "%s change in progress\n", name);
191
192 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
193 }
194
195 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
196 const char *name, u32 reg)
197 {
198 if (dev_priv->hpll_freq == 0)
199 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
200
201 return vlv_get_cck_clock(dev_priv, name, reg,
202 dev_priv->hpll_freq);
203 }
204
205 static void intel_update_czclk(struct drm_i915_private *dev_priv)
206 {
207 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
208 return;
209
210 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
211 CCK_CZ_CLOCK_CONTROL);
212
213 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
214 }
215
216 static inline u32 /* units of 100MHz */
217 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
218 const struct intel_crtc_state *pipe_config)
219 {
220 if (HAS_DDI(dev_priv))
221 return pipe_config->port_clock; /* SPLL */
222 else if (IS_GEN5(dev_priv))
223 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
224 else
225 return 270000;
226 }
227
228 static const struct intel_limit intel_limits_i8xx_dac = {
229 .dot = { .min = 25000, .max = 350000 },
230 .vco = { .min = 908000, .max = 1512000 },
231 .n = { .min = 2, .max = 16 },
232 .m = { .min = 96, .max = 140 },
233 .m1 = { .min = 18, .max = 26 },
234 .m2 = { .min = 6, .max = 16 },
235 .p = { .min = 4, .max = 128 },
236 .p1 = { .min = 2, .max = 33 },
237 .p2 = { .dot_limit = 165000,
238 .p2_slow = 4, .p2_fast = 2 },
239 };
240
241 static const struct intel_limit intel_limits_i8xx_dvo = {
242 .dot = { .min = 25000, .max = 350000 },
243 .vco = { .min = 908000, .max = 1512000 },
244 .n = { .min = 2, .max = 16 },
245 .m = { .min = 96, .max = 140 },
246 .m1 = { .min = 18, .max = 26 },
247 .m2 = { .min = 6, .max = 16 },
248 .p = { .min = 4, .max = 128 },
249 .p1 = { .min = 2, .max = 33 },
250 .p2 = { .dot_limit = 165000,
251 .p2_slow = 4, .p2_fast = 4 },
252 };
253
254 static const struct intel_limit intel_limits_i8xx_lvds = {
255 .dot = { .min = 25000, .max = 350000 },
256 .vco = { .min = 908000, .max = 1512000 },
257 .n = { .min = 2, .max = 16 },
258 .m = { .min = 96, .max = 140 },
259 .m1 = { .min = 18, .max = 26 },
260 .m2 = { .min = 6, .max = 16 },
261 .p = { .min = 4, .max = 128 },
262 .p1 = { .min = 1, .max = 6 },
263 .p2 = { .dot_limit = 165000,
264 .p2_slow = 14, .p2_fast = 7 },
265 };
266
267 static const struct intel_limit intel_limits_i9xx_sdvo = {
268 .dot = { .min = 20000, .max = 400000 },
269 .vco = { .min = 1400000, .max = 2800000 },
270 .n = { .min = 1, .max = 6 },
271 .m = { .min = 70, .max = 120 },
272 .m1 = { .min = 8, .max = 18 },
273 .m2 = { .min = 3, .max = 7 },
274 .p = { .min = 5, .max = 80 },
275 .p1 = { .min = 1, .max = 8 },
276 .p2 = { .dot_limit = 200000,
277 .p2_slow = 10, .p2_fast = 5 },
278 };
279
280 static const struct intel_limit intel_limits_i9xx_lvds = {
281 .dot = { .min = 20000, .max = 400000 },
282 .vco = { .min = 1400000, .max = 2800000 },
283 .n = { .min = 1, .max = 6 },
284 .m = { .min = 70, .max = 120 },
285 .m1 = { .min = 8, .max = 18 },
286 .m2 = { .min = 3, .max = 7 },
287 .p = { .min = 7, .max = 98 },
288 .p1 = { .min = 1, .max = 8 },
289 .p2 = { .dot_limit = 112000,
290 .p2_slow = 14, .p2_fast = 7 },
291 };
292
293
294 static const struct intel_limit intel_limits_g4x_sdvo = {
295 .dot = { .min = 25000, .max = 270000 },
296 .vco = { .min = 1750000, .max = 3500000},
297 .n = { .min = 1, .max = 4 },
298 .m = { .min = 104, .max = 138 },
299 .m1 = { .min = 17, .max = 23 },
300 .m2 = { .min = 5, .max = 11 },
301 .p = { .min = 10, .max = 30 },
302 .p1 = { .min = 1, .max = 3},
303 .p2 = { .dot_limit = 270000,
304 .p2_slow = 10,
305 .p2_fast = 10
306 },
307 };
308
309 static const struct intel_limit intel_limits_g4x_hdmi = {
310 .dot = { .min = 22000, .max = 400000 },
311 .vco = { .min = 1750000, .max = 3500000},
312 .n = { .min = 1, .max = 4 },
313 .m = { .min = 104, .max = 138 },
314 .m1 = { .min = 16, .max = 23 },
315 .m2 = { .min = 5, .max = 11 },
316 .p = { .min = 5, .max = 80 },
317 .p1 = { .min = 1, .max = 8},
318 .p2 = { .dot_limit = 165000,
319 .p2_slow = 10, .p2_fast = 5 },
320 };
321
322 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
323 .dot = { .min = 20000, .max = 115000 },
324 .vco = { .min = 1750000, .max = 3500000 },
325 .n = { .min = 1, .max = 3 },
326 .m = { .min = 104, .max = 138 },
327 .m1 = { .min = 17, .max = 23 },
328 .m2 = { .min = 5, .max = 11 },
329 .p = { .min = 28, .max = 112 },
330 .p1 = { .min = 2, .max = 8 },
331 .p2 = { .dot_limit = 0,
332 .p2_slow = 14, .p2_fast = 14
333 },
334 };
335
336 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
337 .dot = { .min = 80000, .max = 224000 },
338 .vco = { .min = 1750000, .max = 3500000 },
339 .n = { .min = 1, .max = 3 },
340 .m = { .min = 104, .max = 138 },
341 .m1 = { .min = 17, .max = 23 },
342 .m2 = { .min = 5, .max = 11 },
343 .p = { .min = 14, .max = 42 },
344 .p1 = { .min = 2, .max = 6 },
345 .p2 = { .dot_limit = 0,
346 .p2_slow = 7, .p2_fast = 7
347 },
348 };
349
350 static const struct intel_limit intel_limits_pineview_sdvo = {
351 .dot = { .min = 20000, .max = 400000},
352 .vco = { .min = 1700000, .max = 3500000 },
353 /* Pineview's Ncounter is a ring counter */
354 .n = { .min = 3, .max = 6 },
355 .m = { .min = 2, .max = 256 },
356 /* Pineview only has one combined m divider, which we treat as m2. */
357 .m1 = { .min = 0, .max = 0 },
358 .m2 = { .min = 0, .max = 254 },
359 .p = { .min = 5, .max = 80 },
360 .p1 = { .min = 1, .max = 8 },
361 .p2 = { .dot_limit = 200000,
362 .p2_slow = 10, .p2_fast = 5 },
363 };
364
365 static const struct intel_limit intel_limits_pineview_lvds = {
366 .dot = { .min = 20000, .max = 400000 },
367 .vco = { .min = 1700000, .max = 3500000 },
368 .n = { .min = 3, .max = 6 },
369 .m = { .min = 2, .max = 256 },
370 .m1 = { .min = 0, .max = 0 },
371 .m2 = { .min = 0, .max = 254 },
372 .p = { .min = 7, .max = 112 },
373 .p1 = { .min = 1, .max = 8 },
374 .p2 = { .dot_limit = 112000,
375 .p2_slow = 14, .p2_fast = 14 },
376 };
377
378 /* Ironlake / Sandybridge
379 *
380 * We calculate clock using (register_value + 2) for N/M1/M2, so here
381 * the range value for them is (actual_value - 2).
382 */
383 static const struct intel_limit intel_limits_ironlake_dac = {
384 .dot = { .min = 25000, .max = 350000 },
385 .vco = { .min = 1760000, .max = 3510000 },
386 .n = { .min = 1, .max = 5 },
387 .m = { .min = 79, .max = 127 },
388 .m1 = { .min = 12, .max = 22 },
389 .m2 = { .min = 5, .max = 9 },
390 .p = { .min = 5, .max = 80 },
391 .p1 = { .min = 1, .max = 8 },
392 .p2 = { .dot_limit = 225000,
393 .p2_slow = 10, .p2_fast = 5 },
394 };
395
396 static const struct intel_limit intel_limits_ironlake_single_lvds = {
397 .dot = { .min = 25000, .max = 350000 },
398 .vco = { .min = 1760000, .max = 3510000 },
399 .n = { .min = 1, .max = 3 },
400 .m = { .min = 79, .max = 118 },
401 .m1 = { .min = 12, .max = 22 },
402 .m2 = { .min = 5, .max = 9 },
403 .p = { .min = 28, .max = 112 },
404 .p1 = { .min = 2, .max = 8 },
405 .p2 = { .dot_limit = 225000,
406 .p2_slow = 14, .p2_fast = 14 },
407 };
408
409 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
410 .dot = { .min = 25000, .max = 350000 },
411 .vco = { .min = 1760000, .max = 3510000 },
412 .n = { .min = 1, .max = 3 },
413 .m = { .min = 79, .max = 127 },
414 .m1 = { .min = 12, .max = 22 },
415 .m2 = { .min = 5, .max = 9 },
416 .p = { .min = 14, .max = 56 },
417 .p1 = { .min = 2, .max = 8 },
418 .p2 = { .dot_limit = 225000,
419 .p2_slow = 7, .p2_fast = 7 },
420 };
421
422 /* LVDS 100mhz refclk limits. */
423 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
424 .dot = { .min = 25000, .max = 350000 },
425 .vco = { .min = 1760000, .max = 3510000 },
426 .n = { .min = 1, .max = 2 },
427 .m = { .min = 79, .max = 126 },
428 .m1 = { .min = 12, .max = 22 },
429 .m2 = { .min = 5, .max = 9 },
430 .p = { .min = 28, .max = 112 },
431 .p1 = { .min = 2, .max = 8 },
432 .p2 = { .dot_limit = 225000,
433 .p2_slow = 14, .p2_fast = 14 },
434 };
435
436 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
437 .dot = { .min = 25000, .max = 350000 },
438 .vco = { .min = 1760000, .max = 3510000 },
439 .n = { .min = 1, .max = 3 },
440 .m = { .min = 79, .max = 126 },
441 .m1 = { .min = 12, .max = 22 },
442 .m2 = { .min = 5, .max = 9 },
443 .p = { .min = 14, .max = 42 },
444 .p1 = { .min = 2, .max = 6 },
445 .p2 = { .dot_limit = 225000,
446 .p2_slow = 7, .p2_fast = 7 },
447 };
448
449 static const struct intel_limit intel_limits_vlv = {
450 /*
451 * These are the data rate limits (measured in fast clocks)
452 * since those are the strictest limits we have. The fast
453 * clock and actual rate limits are more relaxed, so checking
454 * them would make no difference.
455 */
456 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
457 .vco = { .min = 4000000, .max = 6000000 },
458 .n = { .min = 1, .max = 7 },
459 .m1 = { .min = 2, .max = 3 },
460 .m2 = { .min = 11, .max = 156 },
461 .p1 = { .min = 2, .max = 3 },
462 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
463 };
464
465 static const struct intel_limit intel_limits_chv = {
466 /*
467 * These are the data rate limits (measured in fast clocks)
468 * since those are the strictest limits we have. The fast
469 * clock and actual rate limits are more relaxed, so checking
470 * them would make no difference.
471 */
472 .dot = { .min = 25000 * 5, .max = 540000 * 5},
473 .vco = { .min = 4800000, .max = 6480000 },
474 .n = { .min = 1, .max = 1 },
475 .m1 = { .min = 2, .max = 2 },
476 .m2 = { .min = 24 << 22, .max = 175 << 22 },
477 .p1 = { .min = 2, .max = 4 },
478 .p2 = { .p2_slow = 1, .p2_fast = 14 },
479 };
480
481 static const struct intel_limit intel_limits_bxt = {
482 /* FIXME: find real dot limits */
483 .dot = { .min = 0, .max = INT_MAX },
484 .vco = { .min = 4800000, .max = 6700000 },
485 .n = { .min = 1, .max = 1 },
486 .m1 = { .min = 2, .max = 2 },
487 /* FIXME: find real m2 limits */
488 .m2 = { .min = 2 << 22, .max = 255 << 22 },
489 .p1 = { .min = 2, .max = 4 },
490 .p2 = { .p2_slow = 1, .p2_fast = 20 },
491 };
492
493 static bool
494 needs_modeset(struct drm_crtc_state *state)
495 {
496 return drm_atomic_crtc_needs_modeset(state);
497 }
498
499 /*
500 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
501 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
502 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
503 * The helpers' return value is the rate of the clock that is fed to the
504 * display engine's pipe which can be the above fast dot clock rate or a
505 * divided-down version of it.
506 */
507 /* m1 is reserved as 0 in Pineview, n is a ring counter */
508 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
509 {
510 clock->m = clock->m2 + 2;
511 clock->p = clock->p1 * clock->p2;
512 if (WARN_ON(clock->n == 0 || clock->p == 0))
513 return 0;
514 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
515 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
516
517 return clock->dot;
518 }
519
520 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
521 {
522 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
523 }
524
525 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
526 {
527 clock->m = i9xx_dpll_compute_m(clock);
528 clock->p = clock->p1 * clock->p2;
529 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
530 return 0;
531 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
532 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
533
534 return clock->dot;
535 }
536
537 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
538 {
539 clock->m = clock->m1 * clock->m2;
540 clock->p = clock->p1 * clock->p2;
541 if (WARN_ON(clock->n == 0 || clock->p == 0))
542 return 0;
543 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
544 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
545
546 return clock->dot / 5;
547 }
548
549 int chv_calc_dpll_params(int refclk, struct dpll *clock)
550 {
551 clock->m = clock->m1 * clock->m2;
552 clock->p = clock->p1 * clock->p2;
553 if (WARN_ON(clock->n == 0 || clock->p == 0))
554 return 0;
555 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
556 clock->n << 22);
557 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
558
559 return clock->dot / 5;
560 }
561
562 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
563 /**
564 * Returns whether the given set of divisors are valid for a given refclk with
565 * the given connectors.
566 */
567
568 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
569 const struct intel_limit *limit,
570 const struct dpll *clock)
571 {
572 if (clock->n < limit->n.min || limit->n.max < clock->n)
573 INTELPllInvalid("n out of range\n");
574 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
575 INTELPllInvalid("p1 out of range\n");
576 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
577 INTELPllInvalid("m2 out of range\n");
578 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
579 INTELPllInvalid("m1 out of range\n");
580
581 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
582 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
583 if (clock->m1 <= clock->m2)
584 INTELPllInvalid("m1 <= m2\n");
585
586 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
587 !IS_GEN9_LP(dev_priv)) {
588 if (clock->p < limit->p.min || limit->p.max < clock->p)
589 INTELPllInvalid("p out of range\n");
590 if (clock->m < limit->m.min || limit->m.max < clock->m)
591 INTELPllInvalid("m out of range\n");
592 }
593
594 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
595 INTELPllInvalid("vco out of range\n");
596 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
597 * connector, etc., rather than just a single range.
598 */
599 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
600 INTELPllInvalid("dot out of range\n");
601
602 return true;
603 }
604
605 static int
606 i9xx_select_p2_div(const struct intel_limit *limit,
607 const struct intel_crtc_state *crtc_state,
608 int target)
609 {
610 struct drm_device *dev = crtc_state->base.crtc->dev;
611
612 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
613 /*
614 * For LVDS just rely on its current settings for dual-channel.
615 * We haven't figured out how to reliably set up different
616 * single/dual channel state, if we even can.
617 */
618 if (intel_is_dual_link_lvds(dev))
619 return limit->p2.p2_fast;
620 else
621 return limit->p2.p2_slow;
622 } else {
623 if (target < limit->p2.dot_limit)
624 return limit->p2.p2_slow;
625 else
626 return limit->p2.p2_fast;
627 }
628 }
629
630 /*
631 * Returns a set of divisors for the desired target clock with the given
632 * refclk, or FALSE. The returned values represent the clock equation:
633 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
634 *
635 * Target and reference clocks are specified in kHz.
636 *
637 * If match_clock is provided, then best_clock P divider must match the P
638 * divider from @match_clock used for LVDS downclocking.
639 */
640 static bool
641 i9xx_find_best_dpll(const struct intel_limit *limit,
642 struct intel_crtc_state *crtc_state,
643 int target, int refclk, struct dpll *match_clock,
644 struct dpll *best_clock)
645 {
646 struct drm_device *dev = crtc_state->base.crtc->dev;
647 struct dpll clock;
648 int err = target;
649
650 memset(best_clock, 0, sizeof(*best_clock));
651
652 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
653
654 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
655 clock.m1++) {
656 for (clock.m2 = limit->m2.min;
657 clock.m2 <= limit->m2.max; clock.m2++) {
658 if (clock.m2 >= clock.m1)
659 break;
660 for (clock.n = limit->n.min;
661 clock.n <= limit->n.max; clock.n++) {
662 for (clock.p1 = limit->p1.min;
663 clock.p1 <= limit->p1.max; clock.p1++) {
664 int this_err;
665
666 i9xx_calc_dpll_params(refclk, &clock);
667 if (!intel_PLL_is_valid(to_i915(dev),
668 limit,
669 &clock))
670 continue;
671 if (match_clock &&
672 clock.p != match_clock->p)
673 continue;
674
675 this_err = abs(clock.dot - target);
676 if (this_err < err) {
677 *best_clock = clock;
678 err = this_err;
679 }
680 }
681 }
682 }
683 }
684
685 return (err != target);
686 }
687
688 /*
689 * Returns a set of divisors for the desired target clock with the given
690 * refclk, or FALSE. The returned values represent the clock equation:
691 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
692 *
693 * Target and reference clocks are specified in kHz.
694 *
695 * If match_clock is provided, then best_clock P divider must match the P
696 * divider from @match_clock used for LVDS downclocking.
697 */
698 static bool
699 pnv_find_best_dpll(const struct intel_limit *limit,
700 struct intel_crtc_state *crtc_state,
701 int target, int refclk, struct dpll *match_clock,
702 struct dpll *best_clock)
703 {
704 struct drm_device *dev = crtc_state->base.crtc->dev;
705 struct dpll clock;
706 int err = target;
707
708 memset(best_clock, 0, sizeof(*best_clock));
709
710 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
711
712 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
713 clock.m1++) {
714 for (clock.m2 = limit->m2.min;
715 clock.m2 <= limit->m2.max; clock.m2++) {
716 for (clock.n = limit->n.min;
717 clock.n <= limit->n.max; clock.n++) {
718 for (clock.p1 = limit->p1.min;
719 clock.p1 <= limit->p1.max; clock.p1++) {
720 int this_err;
721
722 pnv_calc_dpll_params(refclk, &clock);
723 if (!intel_PLL_is_valid(to_i915(dev),
724 limit,
725 &clock))
726 continue;
727 if (match_clock &&
728 clock.p != match_clock->p)
729 continue;
730
731 this_err = abs(clock.dot - target);
732 if (this_err < err) {
733 *best_clock = clock;
734 err = this_err;
735 }
736 }
737 }
738 }
739 }
740
741 return (err != target);
742 }
743
744 /*
745 * Returns a set of divisors for the desired target clock with the given
746 * refclk, or FALSE. The returned values represent the clock equation:
747 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
748 *
749 * Target and reference clocks are specified in kHz.
750 *
751 * If match_clock is provided, then best_clock P divider must match the P
752 * divider from @match_clock used for LVDS downclocking.
753 */
754 static bool
755 g4x_find_best_dpll(const struct intel_limit *limit,
756 struct intel_crtc_state *crtc_state,
757 int target, int refclk, struct dpll *match_clock,
758 struct dpll *best_clock)
759 {
760 struct drm_device *dev = crtc_state->base.crtc->dev;
761 struct dpll clock;
762 int max_n;
763 bool found = false;
764 /* approximately equals target * 0.00585 */
765 int err_most = (target >> 8) + (target >> 9);
766
767 memset(best_clock, 0, sizeof(*best_clock));
768
769 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
770
771 max_n = limit->n.max;
772 /* based on hardware requirement, prefer smaller n to precision */
773 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
774 /* based on hardware requirement, prefere larger m1,m2 */
775 for (clock.m1 = limit->m1.max;
776 clock.m1 >= limit->m1.min; clock.m1--) {
777 for (clock.m2 = limit->m2.max;
778 clock.m2 >= limit->m2.min; clock.m2--) {
779 for (clock.p1 = limit->p1.max;
780 clock.p1 >= limit->p1.min; clock.p1--) {
781 int this_err;
782
783 i9xx_calc_dpll_params(refclk, &clock);
784 if (!intel_PLL_is_valid(to_i915(dev),
785 limit,
786 &clock))
787 continue;
788
789 this_err = abs(clock.dot - target);
790 if (this_err < err_most) {
791 *best_clock = clock;
792 err_most = this_err;
793 max_n = clock.n;
794 found = true;
795 }
796 }
797 }
798 }
799 }
800 return found;
801 }
802
803 /*
804 * Check if the calculated PLL configuration is more optimal compared to the
805 * best configuration and error found so far. Return the calculated error.
806 */
807 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
808 const struct dpll *calculated_clock,
809 const struct dpll *best_clock,
810 unsigned int best_error_ppm,
811 unsigned int *error_ppm)
812 {
813 /*
814 * For CHV ignore the error and consider only the P value.
815 * Prefer a bigger P value based on HW requirements.
816 */
817 if (IS_CHERRYVIEW(to_i915(dev))) {
818 *error_ppm = 0;
819
820 return calculated_clock->p > best_clock->p;
821 }
822
823 if (WARN_ON_ONCE(!target_freq))
824 return false;
825
826 *error_ppm = div_u64(1000000ULL *
827 abs(target_freq - calculated_clock->dot),
828 target_freq);
829 /*
830 * Prefer a better P value over a better (smaller) error if the error
831 * is small. Ensure this preference for future configurations too by
832 * setting the error to 0.
833 */
834 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
835 *error_ppm = 0;
836
837 return true;
838 }
839
840 return *error_ppm + 10 < best_error_ppm;
841 }
842
843 /*
844 * Returns a set of divisors for the desired target clock with the given
845 * refclk, or FALSE. The returned values represent the clock equation:
846 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
847 */
848 static bool
849 vlv_find_best_dpll(const struct intel_limit *limit,
850 struct intel_crtc_state *crtc_state,
851 int target, int refclk, struct dpll *match_clock,
852 struct dpll *best_clock)
853 {
854 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
855 struct drm_device *dev = crtc->base.dev;
856 struct dpll clock;
857 unsigned int bestppm = 1000000;
858 /* min update 19.2 MHz */
859 int max_n = min(limit->n.max, refclk / 19200);
860 bool found = false;
861
862 target *= 5; /* fast clock */
863
864 memset(best_clock, 0, sizeof(*best_clock));
865
866 /* based on hardware requirement, prefer smaller n to precision */
867 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
868 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
869 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
870 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
871 clock.p = clock.p1 * clock.p2;
872 /* based on hardware requirement, prefer bigger m1,m2 values */
873 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
874 unsigned int ppm;
875
876 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
877 refclk * clock.m1);
878
879 vlv_calc_dpll_params(refclk, &clock);
880
881 if (!intel_PLL_is_valid(to_i915(dev),
882 limit,
883 &clock))
884 continue;
885
886 if (!vlv_PLL_is_optimal(dev, target,
887 &clock,
888 best_clock,
889 bestppm, &ppm))
890 continue;
891
892 *best_clock = clock;
893 bestppm = ppm;
894 found = true;
895 }
896 }
897 }
898 }
899
900 return found;
901 }
902
903 /*
904 * Returns a set of divisors for the desired target clock with the given
905 * refclk, or FALSE. The returned values represent the clock equation:
906 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
907 */
908 static bool
909 chv_find_best_dpll(const struct intel_limit *limit,
910 struct intel_crtc_state *crtc_state,
911 int target, int refclk, struct dpll *match_clock,
912 struct dpll *best_clock)
913 {
914 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
915 struct drm_device *dev = crtc->base.dev;
916 unsigned int best_error_ppm;
917 struct dpll clock;
918 uint64_t m2;
919 int found = false;
920
921 memset(best_clock, 0, sizeof(*best_clock));
922 best_error_ppm = 1000000;
923
924 /*
925 * Based on hardware doc, the n always set to 1, and m1 always
926 * set to 2. If requires to support 200Mhz refclk, we need to
927 * revisit this because n may not 1 anymore.
928 */
929 clock.n = 1, clock.m1 = 2;
930 target *= 5; /* fast clock */
931
932 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
933 for (clock.p2 = limit->p2.p2_fast;
934 clock.p2 >= limit->p2.p2_slow;
935 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
936 unsigned int error_ppm;
937
938 clock.p = clock.p1 * clock.p2;
939
940 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
941 clock.n) << 22, refclk * clock.m1);
942
943 if (m2 > INT_MAX/clock.m1)
944 continue;
945
946 clock.m2 = m2;
947
948 chv_calc_dpll_params(refclk, &clock);
949
950 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
951 continue;
952
953 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
954 best_error_ppm, &error_ppm))
955 continue;
956
957 *best_clock = clock;
958 best_error_ppm = error_ppm;
959 found = true;
960 }
961 }
962
963 return found;
964 }
965
966 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
967 struct dpll *best_clock)
968 {
969 int refclk = 100000;
970 const struct intel_limit *limit = &intel_limits_bxt;
971
972 return chv_find_best_dpll(limit, crtc_state,
973 target_clock, refclk, NULL, best_clock);
974 }
975
976 bool intel_crtc_active(struct intel_crtc *crtc)
977 {
978 /* Be paranoid as we can arrive here with only partial
979 * state retrieved from the hardware during setup.
980 *
981 * We can ditch the adjusted_mode.crtc_clock check as soon
982 * as Haswell has gained clock readout/fastboot support.
983 *
984 * We can ditch the crtc->primary->fb check as soon as we can
985 * properly reconstruct framebuffers.
986 *
987 * FIXME: The intel_crtc->active here should be switched to
988 * crtc->state->active once we have proper CRTC states wired up
989 * for atomic.
990 */
991 return crtc->active && crtc->base.primary->state->fb &&
992 crtc->config->base.adjusted_mode.crtc_clock;
993 }
994
995 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
996 enum pipe pipe)
997 {
998 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
999
1000 return crtc->config->cpu_transcoder;
1001 }
1002
1003 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
1004 {
1005 i915_reg_t reg = PIPEDSL(pipe);
1006 u32 line1, line2;
1007 u32 line_mask;
1008
1009 if (IS_GEN2(dev_priv))
1010 line_mask = DSL_LINEMASK_GEN2;
1011 else
1012 line_mask = DSL_LINEMASK_GEN3;
1013
1014 line1 = I915_READ(reg) & line_mask;
1015 msleep(5);
1016 line2 = I915_READ(reg) & line_mask;
1017
1018 return line1 == line2;
1019 }
1020
1021 /*
1022 * intel_wait_for_pipe_off - wait for pipe to turn off
1023 * @crtc: crtc whose pipe to wait for
1024 *
1025 * After disabling a pipe, we can't wait for vblank in the usual way,
1026 * spinning on the vblank interrupt status bit, since we won't actually
1027 * see an interrupt when the pipe is disabled.
1028 *
1029 * On Gen4 and above:
1030 * wait for the pipe register state bit to turn off
1031 *
1032 * Otherwise:
1033 * wait for the display line value to settle (it usually
1034 * ends up stopping at the start of the next frame).
1035 *
1036 */
1037 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1038 {
1039 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1040 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1041 enum pipe pipe = crtc->pipe;
1042
1043 if (INTEL_GEN(dev_priv) >= 4) {
1044 i915_reg_t reg = PIPECONF(cpu_transcoder);
1045
1046 /* Wait for the Pipe State to go off */
1047 if (intel_wait_for_register(dev_priv,
1048 reg, I965_PIPECONF_ACTIVE, 0,
1049 100))
1050 WARN(1, "pipe_off wait timed out\n");
1051 } else {
1052 /* Wait for the display line to settle */
1053 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1054 WARN(1, "pipe_off wait timed out\n");
1055 }
1056 }
1057
1058 /* Only for pre-ILK configs */
1059 void assert_pll(struct drm_i915_private *dev_priv,
1060 enum pipe pipe, bool state)
1061 {
1062 u32 val;
1063 bool cur_state;
1064
1065 val = I915_READ(DPLL(pipe));
1066 cur_state = !!(val & DPLL_VCO_ENABLE);
1067 I915_STATE_WARN(cur_state != state,
1068 "PLL state assertion failure (expected %s, current %s)\n",
1069 onoff(state), onoff(cur_state));
1070 }
1071
1072 /* XXX: the dsi pll is shared between MIPI DSI ports */
1073 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1074 {
1075 u32 val;
1076 bool cur_state;
1077
1078 mutex_lock(&dev_priv->sb_lock);
1079 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1080 mutex_unlock(&dev_priv->sb_lock);
1081
1082 cur_state = val & DSI_PLL_VCO_EN;
1083 I915_STATE_WARN(cur_state != state,
1084 "DSI PLL state assertion failure (expected %s, current %s)\n",
1085 onoff(state), onoff(cur_state));
1086 }
1087
1088 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1089 enum pipe pipe, bool state)
1090 {
1091 bool cur_state;
1092 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1093 pipe);
1094
1095 if (HAS_DDI(dev_priv)) {
1096 /* DDI does not have a specific FDI_TX register */
1097 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1098 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1099 } else {
1100 u32 val = I915_READ(FDI_TX_CTL(pipe));
1101 cur_state = !!(val & FDI_TX_ENABLE);
1102 }
1103 I915_STATE_WARN(cur_state != state,
1104 "FDI TX state assertion failure (expected %s, current %s)\n",
1105 onoff(state), onoff(cur_state));
1106 }
1107 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1108 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1109
1110 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1111 enum pipe pipe, bool state)
1112 {
1113 u32 val;
1114 bool cur_state;
1115
1116 val = I915_READ(FDI_RX_CTL(pipe));
1117 cur_state = !!(val & FDI_RX_ENABLE);
1118 I915_STATE_WARN(cur_state != state,
1119 "FDI RX state assertion failure (expected %s, current %s)\n",
1120 onoff(state), onoff(cur_state));
1121 }
1122 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1123 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1124
1125 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1126 enum pipe pipe)
1127 {
1128 u32 val;
1129
1130 /* ILK FDI PLL is always enabled */
1131 if (IS_GEN5(dev_priv))
1132 return;
1133
1134 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1135 if (HAS_DDI(dev_priv))
1136 return;
1137
1138 val = I915_READ(FDI_TX_CTL(pipe));
1139 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1140 }
1141
1142 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1143 enum pipe pipe, bool state)
1144 {
1145 u32 val;
1146 bool cur_state;
1147
1148 val = I915_READ(FDI_RX_CTL(pipe));
1149 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1150 I915_STATE_WARN(cur_state != state,
1151 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1152 onoff(state), onoff(cur_state));
1153 }
1154
1155 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1156 {
1157 i915_reg_t pp_reg;
1158 u32 val;
1159 enum pipe panel_pipe = PIPE_A;
1160 bool locked = true;
1161
1162 if (WARN_ON(HAS_DDI(dev_priv)))
1163 return;
1164
1165 if (HAS_PCH_SPLIT(dev_priv)) {
1166 u32 port_sel;
1167
1168 pp_reg = PP_CONTROL(0);
1169 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1170
1171 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1172 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1173 panel_pipe = PIPE_B;
1174 /* XXX: else fix for eDP */
1175 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1176 /* presumably write lock depends on pipe, not port select */
1177 pp_reg = PP_CONTROL(pipe);
1178 panel_pipe = pipe;
1179 } else {
1180 pp_reg = PP_CONTROL(0);
1181 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1182 panel_pipe = PIPE_B;
1183 }
1184
1185 val = I915_READ(pp_reg);
1186 if (!(val & PANEL_POWER_ON) ||
1187 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1188 locked = false;
1189
1190 I915_STATE_WARN(panel_pipe == pipe && locked,
1191 "panel assertion failure, pipe %c regs locked\n",
1192 pipe_name(pipe));
1193 }
1194
1195 static void assert_cursor(struct drm_i915_private *dev_priv,
1196 enum pipe pipe, bool state)
1197 {
1198 bool cur_state;
1199
1200 if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1201 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1202 else
1203 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1204
1205 I915_STATE_WARN(cur_state != state,
1206 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1207 pipe_name(pipe), onoff(state), onoff(cur_state));
1208 }
1209 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1210 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1211
1212 void assert_pipe(struct drm_i915_private *dev_priv,
1213 enum pipe pipe, bool state)
1214 {
1215 bool cur_state;
1216 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1217 pipe);
1218 enum intel_display_power_domain power_domain;
1219
1220 /* we keep both pipes enabled on 830 */
1221 if (IS_I830(dev_priv))
1222 state = true;
1223
1224 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1225 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1226 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1227 cur_state = !!(val & PIPECONF_ENABLE);
1228
1229 intel_display_power_put(dev_priv, power_domain);
1230 } else {
1231 cur_state = false;
1232 }
1233
1234 I915_STATE_WARN(cur_state != state,
1235 "pipe %c assertion failure (expected %s, current %s)\n",
1236 pipe_name(pipe), onoff(state), onoff(cur_state));
1237 }
1238
1239 static void assert_plane(struct drm_i915_private *dev_priv,
1240 enum plane plane, bool state)
1241 {
1242 u32 val;
1243 bool cur_state;
1244
1245 val = I915_READ(DSPCNTR(plane));
1246 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1247 I915_STATE_WARN(cur_state != state,
1248 "plane %c assertion failure (expected %s, current %s)\n",
1249 plane_name(plane), onoff(state), onoff(cur_state));
1250 }
1251
1252 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1253 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1254
1255 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1256 enum pipe pipe)
1257 {
1258 int i;
1259
1260 /* Primary planes are fixed to pipes on gen4+ */
1261 if (INTEL_GEN(dev_priv) >= 4) {
1262 u32 val = I915_READ(DSPCNTR(pipe));
1263 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1264 "plane %c assertion failure, should be disabled but not\n",
1265 plane_name(pipe));
1266 return;
1267 }
1268
1269 /* Need to check both planes against the pipe */
1270 for_each_pipe(dev_priv, i) {
1271 u32 val = I915_READ(DSPCNTR(i));
1272 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1273 DISPPLANE_SEL_PIPE_SHIFT;
1274 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1275 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1276 plane_name(i), pipe_name(pipe));
1277 }
1278 }
1279
1280 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1281 enum pipe pipe)
1282 {
1283 int sprite;
1284
1285 if (INTEL_GEN(dev_priv) >= 9) {
1286 for_each_sprite(dev_priv, pipe, sprite) {
1287 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1288 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1289 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1290 sprite, pipe_name(pipe));
1291 }
1292 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1293 for_each_sprite(dev_priv, pipe, sprite) {
1294 u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1295 I915_STATE_WARN(val & SP_ENABLE,
1296 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1297 sprite_name(pipe, sprite), pipe_name(pipe));
1298 }
1299 } else if (INTEL_GEN(dev_priv) >= 7) {
1300 u32 val = I915_READ(SPRCTL(pipe));
1301 I915_STATE_WARN(val & SPRITE_ENABLE,
1302 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1303 plane_name(pipe), pipe_name(pipe));
1304 } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
1305 u32 val = I915_READ(DVSCNTR(pipe));
1306 I915_STATE_WARN(val & DVS_ENABLE,
1307 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1308 plane_name(pipe), pipe_name(pipe));
1309 }
1310 }
1311
1312 static void assert_vblank_disabled(struct drm_crtc *crtc)
1313 {
1314 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1315 drm_crtc_vblank_put(crtc);
1316 }
1317
1318 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1319 enum pipe pipe)
1320 {
1321 u32 val;
1322 bool enabled;
1323
1324 val = I915_READ(PCH_TRANSCONF(pipe));
1325 enabled = !!(val & TRANS_ENABLE);
1326 I915_STATE_WARN(enabled,
1327 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328 pipe_name(pipe));
1329 }
1330
1331 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332 enum pipe pipe, u32 port_sel, u32 val)
1333 {
1334 if ((val & DP_PORT_EN) == 0)
1335 return false;
1336
1337 if (HAS_PCH_CPT(dev_priv)) {
1338 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1339 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1340 return false;
1341 } else if (IS_CHERRYVIEW(dev_priv)) {
1342 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1343 return false;
1344 } else {
1345 if ((val & DP_PIPE_MASK) != (pipe << 30))
1346 return false;
1347 }
1348 return true;
1349 }
1350
1351 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1352 enum pipe pipe, u32 val)
1353 {
1354 if ((val & SDVO_ENABLE) == 0)
1355 return false;
1356
1357 if (HAS_PCH_CPT(dev_priv)) {
1358 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1359 return false;
1360 } else if (IS_CHERRYVIEW(dev_priv)) {
1361 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1362 return false;
1363 } else {
1364 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1365 return false;
1366 }
1367 return true;
1368 }
1369
1370 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1371 enum pipe pipe, u32 val)
1372 {
1373 if ((val & LVDS_PORT_EN) == 0)
1374 return false;
1375
1376 if (HAS_PCH_CPT(dev_priv)) {
1377 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1378 return false;
1379 } else {
1380 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1381 return false;
1382 }
1383 return true;
1384 }
1385
1386 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1387 enum pipe pipe, u32 val)
1388 {
1389 if ((val & ADPA_DAC_ENABLE) == 0)
1390 return false;
1391 if (HAS_PCH_CPT(dev_priv)) {
1392 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1393 return false;
1394 } else {
1395 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1396 return false;
1397 }
1398 return true;
1399 }
1400
1401 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1402 enum pipe pipe, i915_reg_t reg,
1403 u32 port_sel)
1404 {
1405 u32 val = I915_READ(reg);
1406 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1407 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1408 i915_mmio_reg_offset(reg), pipe_name(pipe));
1409
1410 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1411 && (val & DP_PIPEB_SELECT),
1412 "IBX PCH dp port still using transcoder B\n");
1413 }
1414
1415 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1416 enum pipe pipe, i915_reg_t reg)
1417 {
1418 u32 val = I915_READ(reg);
1419 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1420 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1421 i915_mmio_reg_offset(reg), pipe_name(pipe));
1422
1423 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1424 && (val & SDVO_PIPE_B_SELECT),
1425 "IBX PCH hdmi port still using transcoder B\n");
1426 }
1427
1428 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1429 enum pipe pipe)
1430 {
1431 u32 val;
1432
1433 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1434 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1435 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1436
1437 val = I915_READ(PCH_ADPA);
1438 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1439 "PCH VGA enabled on transcoder %c, should be disabled\n",
1440 pipe_name(pipe));
1441
1442 val = I915_READ(PCH_LVDS);
1443 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1444 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1445 pipe_name(pipe));
1446
1447 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1448 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1449 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1450 }
1451
1452 static void _vlv_enable_pll(struct intel_crtc *crtc,
1453 const struct intel_crtc_state *pipe_config)
1454 {
1455 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1456 enum pipe pipe = crtc->pipe;
1457
1458 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1459 POSTING_READ(DPLL(pipe));
1460 udelay(150);
1461
1462 if (intel_wait_for_register(dev_priv,
1463 DPLL(pipe),
1464 DPLL_LOCK_VLV,
1465 DPLL_LOCK_VLV,
1466 1))
1467 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1468 }
1469
1470 static void vlv_enable_pll(struct intel_crtc *crtc,
1471 const struct intel_crtc_state *pipe_config)
1472 {
1473 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1474 enum pipe pipe = crtc->pipe;
1475
1476 assert_pipe_disabled(dev_priv, pipe);
1477
1478 /* PLL is protected by panel, make sure we can write it */
1479 assert_panel_unlocked(dev_priv, pipe);
1480
1481 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1482 _vlv_enable_pll(crtc, pipe_config);
1483
1484 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1485 POSTING_READ(DPLL_MD(pipe));
1486 }
1487
1488
1489 static void _chv_enable_pll(struct intel_crtc *crtc,
1490 const struct intel_crtc_state *pipe_config)
1491 {
1492 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1493 enum pipe pipe = crtc->pipe;
1494 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1495 u32 tmp;
1496
1497 mutex_lock(&dev_priv->sb_lock);
1498
1499 /* Enable back the 10bit clock to display controller */
1500 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1501 tmp |= DPIO_DCLKP_EN;
1502 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1503
1504 mutex_unlock(&dev_priv->sb_lock);
1505
1506 /*
1507 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1508 */
1509 udelay(1);
1510
1511 /* Enable PLL */
1512 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1513
1514 /* Check PLL is locked */
1515 if (intel_wait_for_register(dev_priv,
1516 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1517 1))
1518 DRM_ERROR("PLL %d failed to lock\n", pipe);
1519 }
1520
1521 static void chv_enable_pll(struct intel_crtc *crtc,
1522 const struct intel_crtc_state *pipe_config)
1523 {
1524 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1525 enum pipe pipe = crtc->pipe;
1526
1527 assert_pipe_disabled(dev_priv, pipe);
1528
1529 /* PLL is protected by panel, make sure we can write it */
1530 assert_panel_unlocked(dev_priv, pipe);
1531
1532 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1533 _chv_enable_pll(crtc, pipe_config);
1534
1535 if (pipe != PIPE_A) {
1536 /*
1537 * WaPixelRepeatModeFixForC0:chv
1538 *
1539 * DPLLCMD is AWOL. Use chicken bits to propagate
1540 * the value from DPLLBMD to either pipe B or C.
1541 */
1542 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1543 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1544 I915_WRITE(CBR4_VLV, 0);
1545 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1546
1547 /*
1548 * DPLLB VGA mode also seems to cause problems.
1549 * We should always have it disabled.
1550 */
1551 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1552 } else {
1553 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1554 POSTING_READ(DPLL_MD(pipe));
1555 }
1556 }
1557
1558 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1559 {
1560 struct intel_crtc *crtc;
1561 int count = 0;
1562
1563 for_each_intel_crtc(&dev_priv->drm, crtc) {
1564 count += crtc->base.state->active &&
1565 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1566 }
1567
1568 return count;
1569 }
1570
1571 static void i9xx_enable_pll(struct intel_crtc *crtc,
1572 const struct intel_crtc_state *crtc_state)
1573 {
1574 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1575 i915_reg_t reg = DPLL(crtc->pipe);
1576 u32 dpll = crtc_state->dpll_hw_state.dpll;
1577 int i;
1578
1579 assert_pipe_disabled(dev_priv, crtc->pipe);
1580
1581 /* PLL is protected by panel, make sure we can write it */
1582 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1583 assert_panel_unlocked(dev_priv, crtc->pipe);
1584
1585 /* Enable DVO 2x clock on both PLLs if necessary */
1586 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1587 /*
1588 * It appears to be important that we don't enable this
1589 * for the current pipe before otherwise configuring the
1590 * PLL. No idea how this should be handled if multiple
1591 * DVO outputs are enabled simultaneosly.
1592 */
1593 dpll |= DPLL_DVO_2X_MODE;
1594 I915_WRITE(DPLL(!crtc->pipe),
1595 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1596 }
1597
1598 /*
1599 * Apparently we need to have VGA mode enabled prior to changing
1600 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1601 * dividers, even though the register value does change.
1602 */
1603 I915_WRITE(reg, 0);
1604
1605 I915_WRITE(reg, dpll);
1606
1607 /* Wait for the clocks to stabilize. */
1608 POSTING_READ(reg);
1609 udelay(150);
1610
1611 if (INTEL_GEN(dev_priv) >= 4) {
1612 I915_WRITE(DPLL_MD(crtc->pipe),
1613 crtc_state->dpll_hw_state.dpll_md);
1614 } else {
1615 /* The pixel multiplier can only be updated once the
1616 * DPLL is enabled and the clocks are stable.
1617 *
1618 * So write it again.
1619 */
1620 I915_WRITE(reg, dpll);
1621 }
1622
1623 /* We do this three times for luck */
1624 for (i = 0; i < 3; i++) {
1625 I915_WRITE(reg, dpll);
1626 POSTING_READ(reg);
1627 udelay(150); /* wait for warmup */
1628 }
1629 }
1630
1631 static void i9xx_disable_pll(struct intel_crtc *crtc)
1632 {
1633 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1634 enum pipe pipe = crtc->pipe;
1635
1636 /* Disable DVO 2x clock on both PLLs if necessary */
1637 if (IS_I830(dev_priv) &&
1638 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1639 !intel_num_dvo_pipes(dev_priv)) {
1640 I915_WRITE(DPLL(PIPE_B),
1641 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1642 I915_WRITE(DPLL(PIPE_A),
1643 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1644 }
1645
1646 /* Don't disable pipe or pipe PLLs if needed */
1647 if (IS_I830(dev_priv))
1648 return;
1649
1650 /* Make sure the pipe isn't still relying on us */
1651 assert_pipe_disabled(dev_priv, pipe);
1652
1653 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1654 POSTING_READ(DPLL(pipe));
1655 }
1656
1657 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1658 {
1659 u32 val;
1660
1661 /* Make sure the pipe isn't still relying on us */
1662 assert_pipe_disabled(dev_priv, pipe);
1663
1664 val = DPLL_INTEGRATED_REF_CLK_VLV |
1665 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1666 if (pipe != PIPE_A)
1667 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1668
1669 I915_WRITE(DPLL(pipe), val);
1670 POSTING_READ(DPLL(pipe));
1671 }
1672
1673 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1674 {
1675 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1676 u32 val;
1677
1678 /* Make sure the pipe isn't still relying on us */
1679 assert_pipe_disabled(dev_priv, pipe);
1680
1681 val = DPLL_SSC_REF_CLK_CHV |
1682 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1683 if (pipe != PIPE_A)
1684 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1685
1686 I915_WRITE(DPLL(pipe), val);
1687 POSTING_READ(DPLL(pipe));
1688
1689 mutex_lock(&dev_priv->sb_lock);
1690
1691 /* Disable 10bit clock to display controller */
1692 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1693 val &= ~DPIO_DCLKP_EN;
1694 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1695
1696 mutex_unlock(&dev_priv->sb_lock);
1697 }
1698
1699 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1700 struct intel_digital_port *dport,
1701 unsigned int expected_mask)
1702 {
1703 u32 port_mask;
1704 i915_reg_t dpll_reg;
1705
1706 switch (dport->port) {
1707 case PORT_B:
1708 port_mask = DPLL_PORTB_READY_MASK;
1709 dpll_reg = DPLL(0);
1710 break;
1711 case PORT_C:
1712 port_mask = DPLL_PORTC_READY_MASK;
1713 dpll_reg = DPLL(0);
1714 expected_mask <<= 4;
1715 break;
1716 case PORT_D:
1717 port_mask = DPLL_PORTD_READY_MASK;
1718 dpll_reg = DPIO_PHY_STATUS;
1719 break;
1720 default:
1721 BUG();
1722 }
1723
1724 if (intel_wait_for_register(dev_priv,
1725 dpll_reg, port_mask, expected_mask,
1726 1000))
1727 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1728 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1729 }
1730
1731 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1732 enum pipe pipe)
1733 {
1734 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1735 pipe);
1736 i915_reg_t reg;
1737 uint32_t val, pipeconf_val;
1738
1739 /* Make sure PCH DPLL is enabled */
1740 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1741
1742 /* FDI must be feeding us bits for PCH ports */
1743 assert_fdi_tx_enabled(dev_priv, pipe);
1744 assert_fdi_rx_enabled(dev_priv, pipe);
1745
1746 if (HAS_PCH_CPT(dev_priv)) {
1747 /* Workaround: Set the timing override bit before enabling the
1748 * pch transcoder. */
1749 reg = TRANS_CHICKEN2(pipe);
1750 val = I915_READ(reg);
1751 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1752 I915_WRITE(reg, val);
1753 }
1754
1755 reg = PCH_TRANSCONF(pipe);
1756 val = I915_READ(reg);
1757 pipeconf_val = I915_READ(PIPECONF(pipe));
1758
1759 if (HAS_PCH_IBX(dev_priv)) {
1760 /*
1761 * Make the BPC in transcoder be consistent with
1762 * that in pipeconf reg. For HDMI we must use 8bpc
1763 * here for both 8bpc and 12bpc.
1764 */
1765 val &= ~PIPECONF_BPC_MASK;
1766 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1767 val |= PIPECONF_8BPC;
1768 else
1769 val |= pipeconf_val & PIPECONF_BPC_MASK;
1770 }
1771
1772 val &= ~TRANS_INTERLACE_MASK;
1773 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1774 if (HAS_PCH_IBX(dev_priv) &&
1775 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1776 val |= TRANS_LEGACY_INTERLACED_ILK;
1777 else
1778 val |= TRANS_INTERLACED;
1779 else
1780 val |= TRANS_PROGRESSIVE;
1781
1782 I915_WRITE(reg, val | TRANS_ENABLE);
1783 if (intel_wait_for_register(dev_priv,
1784 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1785 100))
1786 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1787 }
1788
1789 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1790 enum transcoder cpu_transcoder)
1791 {
1792 u32 val, pipeconf_val;
1793
1794 /* FDI must be feeding us bits for PCH ports */
1795 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1796 assert_fdi_rx_enabled(dev_priv, PIPE_A);
1797
1798 /* Workaround: set timing override bit. */
1799 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1800 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1801 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1802
1803 val = TRANS_ENABLE;
1804 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1805
1806 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1807 PIPECONF_INTERLACED_ILK)
1808 val |= TRANS_INTERLACED;
1809 else
1810 val |= TRANS_PROGRESSIVE;
1811
1812 I915_WRITE(LPT_TRANSCONF, val);
1813 if (intel_wait_for_register(dev_priv,
1814 LPT_TRANSCONF,
1815 TRANS_STATE_ENABLE,
1816 TRANS_STATE_ENABLE,
1817 100))
1818 DRM_ERROR("Failed to enable PCH transcoder\n");
1819 }
1820
1821 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1822 enum pipe pipe)
1823 {
1824 i915_reg_t reg;
1825 uint32_t val;
1826
1827 /* FDI relies on the transcoder */
1828 assert_fdi_tx_disabled(dev_priv, pipe);
1829 assert_fdi_rx_disabled(dev_priv, pipe);
1830
1831 /* Ports must be off as well */
1832 assert_pch_ports_disabled(dev_priv, pipe);
1833
1834 reg = PCH_TRANSCONF(pipe);
1835 val = I915_READ(reg);
1836 val &= ~TRANS_ENABLE;
1837 I915_WRITE(reg, val);
1838 /* wait for PCH transcoder off, transcoder state */
1839 if (intel_wait_for_register(dev_priv,
1840 reg, TRANS_STATE_ENABLE, 0,
1841 50))
1842 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1843
1844 if (HAS_PCH_CPT(dev_priv)) {
1845 /* Workaround: Clear the timing override chicken bit again. */
1846 reg = TRANS_CHICKEN2(pipe);
1847 val = I915_READ(reg);
1848 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1849 I915_WRITE(reg, val);
1850 }
1851 }
1852
1853 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1854 {
1855 u32 val;
1856
1857 val = I915_READ(LPT_TRANSCONF);
1858 val &= ~TRANS_ENABLE;
1859 I915_WRITE(LPT_TRANSCONF, val);
1860 /* wait for PCH transcoder off, transcoder state */
1861 if (intel_wait_for_register(dev_priv,
1862 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1863 50))
1864 DRM_ERROR("Failed to disable PCH transcoder\n");
1865
1866 /* Workaround: clear timing override bit. */
1867 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1868 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1869 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1870 }
1871
1872 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1873 {
1874 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1875
1876 WARN_ON(!crtc->config->has_pch_encoder);
1877
1878 if (HAS_PCH_LPT(dev_priv))
1879 return PIPE_A;
1880 else
1881 return crtc->pipe;
1882 }
1883
1884 /**
1885 * intel_enable_pipe - enable a pipe, asserting requirements
1886 * @crtc: crtc responsible for the pipe
1887 *
1888 * Enable @crtc's pipe, making sure that various hardware specific requirements
1889 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1890 */
1891 static void intel_enable_pipe(struct intel_crtc *crtc)
1892 {
1893 struct drm_device *dev = crtc->base.dev;
1894 struct drm_i915_private *dev_priv = to_i915(dev);
1895 enum pipe pipe = crtc->pipe;
1896 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1897 i915_reg_t reg;
1898 u32 val;
1899
1900 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1901
1902 assert_planes_disabled(dev_priv, pipe);
1903 assert_cursor_disabled(dev_priv, pipe);
1904 assert_sprites_disabled(dev_priv, pipe);
1905
1906 /*
1907 * A pipe without a PLL won't actually be able to drive bits from
1908 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1909 * need the check.
1910 */
1911 if (HAS_GMCH_DISPLAY(dev_priv)) {
1912 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1913 assert_dsi_pll_enabled(dev_priv);
1914 else
1915 assert_pll_enabled(dev_priv, pipe);
1916 } else {
1917 if (crtc->config->has_pch_encoder) {
1918 /* if driving the PCH, we need FDI enabled */
1919 assert_fdi_rx_pll_enabled(dev_priv,
1920 intel_crtc_pch_transcoder(crtc));
1921 assert_fdi_tx_pll_enabled(dev_priv,
1922 (enum pipe) cpu_transcoder);
1923 }
1924 /* FIXME: assert CPU port conditions for SNB+ */
1925 }
1926
1927 reg = PIPECONF(cpu_transcoder);
1928 val = I915_READ(reg);
1929 if (val & PIPECONF_ENABLE) {
1930 /* we keep both pipes enabled on 830 */
1931 WARN_ON(!IS_I830(dev_priv));
1932 return;
1933 }
1934
1935 I915_WRITE(reg, val | PIPECONF_ENABLE);
1936 POSTING_READ(reg);
1937
1938 /*
1939 * Until the pipe starts DSL will read as 0, which would cause
1940 * an apparent vblank timestamp jump, which messes up also the
1941 * frame count when it's derived from the timestamps. So let's
1942 * wait for the pipe to start properly before we call
1943 * drm_crtc_vblank_on()
1944 */
1945 if (dev->max_vblank_count == 0 &&
1946 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1947 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1948 }
1949
1950 /**
1951 * intel_disable_pipe - disable a pipe, asserting requirements
1952 * @crtc: crtc whose pipes is to be disabled
1953 *
1954 * Disable the pipe of @crtc, making sure that various hardware
1955 * specific requirements are met, if applicable, e.g. plane
1956 * disabled, panel fitter off, etc.
1957 *
1958 * Will wait until the pipe has shut down before returning.
1959 */
1960 static void intel_disable_pipe(struct intel_crtc *crtc)
1961 {
1962 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1963 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1964 enum pipe pipe = crtc->pipe;
1965 i915_reg_t reg;
1966 u32 val;
1967
1968 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1969
1970 /*
1971 * Make sure planes won't keep trying to pump pixels to us,
1972 * or we might hang the display.
1973 */
1974 assert_planes_disabled(dev_priv, pipe);
1975 assert_cursor_disabled(dev_priv, pipe);
1976 assert_sprites_disabled(dev_priv, pipe);
1977
1978 reg = PIPECONF(cpu_transcoder);
1979 val = I915_READ(reg);
1980 if ((val & PIPECONF_ENABLE) == 0)
1981 return;
1982
1983 /*
1984 * Double wide has implications for planes
1985 * so best keep it disabled when not needed.
1986 */
1987 if (crtc->config->double_wide)
1988 val &= ~PIPECONF_DOUBLE_WIDE;
1989
1990 /* Don't disable pipe or pipe PLLs if needed */
1991 if (!IS_I830(dev_priv))
1992 val &= ~PIPECONF_ENABLE;
1993
1994 I915_WRITE(reg, val);
1995 if ((val & PIPECONF_ENABLE) == 0)
1996 intel_wait_for_pipe_off(crtc);
1997 }
1998
1999 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2000 {
2001 return IS_GEN2(dev_priv) ? 2048 : 4096;
2002 }
2003
2004 static unsigned int
2005 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
2006 {
2007 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2008 unsigned int cpp = fb->format->cpp[plane];
2009
2010 switch (fb->modifier) {
2011 case DRM_FORMAT_MOD_LINEAR:
2012 return cpp;
2013 case I915_FORMAT_MOD_X_TILED:
2014 if (IS_GEN2(dev_priv))
2015 return 128;
2016 else
2017 return 512;
2018 case I915_FORMAT_MOD_Y_TILED_CCS:
2019 if (plane == 1)
2020 return 128;
2021 /* fall through */
2022 case I915_FORMAT_MOD_Y_TILED:
2023 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2024 return 128;
2025 else
2026 return 512;
2027 case I915_FORMAT_MOD_Yf_TILED_CCS:
2028 if (plane == 1)
2029 return 128;
2030 /* fall through */
2031 case I915_FORMAT_MOD_Yf_TILED:
2032 switch (cpp) {
2033 case 1:
2034 return 64;
2035 case 2:
2036 case 4:
2037 return 128;
2038 case 8:
2039 case 16:
2040 return 256;
2041 default:
2042 MISSING_CASE(cpp);
2043 return cpp;
2044 }
2045 break;
2046 default:
2047 MISSING_CASE(fb->modifier);
2048 return cpp;
2049 }
2050 }
2051
2052 static unsigned int
2053 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2054 {
2055 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
2056 return 1;
2057 else
2058 return intel_tile_size(to_i915(fb->dev)) /
2059 intel_tile_width_bytes(fb, plane);
2060 }
2061
2062 /* Return the tile dimensions in pixel units */
2063 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2064 unsigned int *tile_width,
2065 unsigned int *tile_height)
2066 {
2067 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2068 unsigned int cpp = fb->format->cpp[plane];
2069
2070 *tile_width = tile_width_bytes / cpp;
2071 *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2072 }
2073
2074 unsigned int
2075 intel_fb_align_height(const struct drm_framebuffer *fb,
2076 int plane, unsigned int height)
2077 {
2078 unsigned int tile_height = intel_tile_height(fb, plane);
2079
2080 return ALIGN(height, tile_height);
2081 }
2082
2083 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2084 {
2085 unsigned int size = 0;
2086 int i;
2087
2088 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2089 size += rot_info->plane[i].width * rot_info->plane[i].height;
2090
2091 return size;
2092 }
2093
2094 static void
2095 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2096 const struct drm_framebuffer *fb,
2097 unsigned int rotation)
2098 {
2099 view->type = I915_GGTT_VIEW_NORMAL;
2100 if (drm_rotation_90_or_270(rotation)) {
2101 view->type = I915_GGTT_VIEW_ROTATED;
2102 view->rotated = to_intel_framebuffer(fb)->rot_info;
2103 }
2104 }
2105
2106 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2107 {
2108 if (IS_I830(dev_priv))
2109 return 16 * 1024;
2110 else if (IS_I85X(dev_priv))
2111 return 256;
2112 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2113 return 32;
2114 else
2115 return 4 * 1024;
2116 }
2117
2118 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2119 {
2120 if (INTEL_INFO(dev_priv)->gen >= 9)
2121 return 256 * 1024;
2122 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2123 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2124 return 128 * 1024;
2125 else if (INTEL_INFO(dev_priv)->gen >= 4)
2126 return 4 * 1024;
2127 else
2128 return 0;
2129 }
2130
2131 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2132 int plane)
2133 {
2134 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2135
2136 /* AUX_DIST needs only 4K alignment */
2137 if (plane == 1)
2138 return 4096;
2139
2140 switch (fb->modifier) {
2141 case DRM_FORMAT_MOD_LINEAR:
2142 return intel_linear_alignment(dev_priv);
2143 case I915_FORMAT_MOD_X_TILED:
2144 if (INTEL_GEN(dev_priv) >= 9)
2145 return 256 * 1024;
2146 return 0;
2147 case I915_FORMAT_MOD_Y_TILED_CCS:
2148 case I915_FORMAT_MOD_Yf_TILED_CCS:
2149 case I915_FORMAT_MOD_Y_TILED:
2150 case I915_FORMAT_MOD_Yf_TILED:
2151 return 1 * 1024 * 1024;
2152 default:
2153 MISSING_CASE(fb->modifier);
2154 return 0;
2155 }
2156 }
2157
2158 struct i915_vma *
2159 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2160 {
2161 struct drm_device *dev = fb->dev;
2162 struct drm_i915_private *dev_priv = to_i915(dev);
2163 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2164 struct i915_ggtt_view view;
2165 struct i915_vma *vma;
2166 u32 alignment;
2167
2168 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2169
2170 alignment = intel_surf_alignment(fb, 0);
2171
2172 intel_fill_fb_ggtt_view(&view, fb, rotation);
2173
2174 /* Note that the w/a also requires 64 PTE of padding following the
2175 * bo. We currently fill all unused PTE with the shadow page and so
2176 * we should always have valid PTE following the scanout preventing
2177 * the VT-d warning.
2178 */
2179 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2180 alignment = 256 * 1024;
2181
2182 /*
2183 * Global gtt pte registers are special registers which actually forward
2184 * writes to a chunk of system memory. Which means that there is no risk
2185 * that the register values disappear as soon as we call
2186 * intel_runtime_pm_put(), so it is correct to wrap only the
2187 * pin/unpin/fence and not more.
2188 */
2189 intel_runtime_pm_get(dev_priv);
2190
2191 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2192
2193 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2194 if (IS_ERR(vma))
2195 goto err;
2196
2197 if (i915_vma_is_map_and_fenceable(vma)) {
2198 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2199 * fence, whereas 965+ only requires a fence if using
2200 * framebuffer compression. For simplicity, we always, when
2201 * possible, install a fence as the cost is not that onerous.
2202 *
2203 * If we fail to fence the tiled scanout, then either the
2204 * modeset will reject the change (which is highly unlikely as
2205 * the affected systems, all but one, do not have unmappable
2206 * space) or we will not be able to enable full powersaving
2207 * techniques (also likely not to apply due to various limits
2208 * FBC and the like impose on the size of the buffer, which
2209 * presumably we violated anyway with this unmappable buffer).
2210 * Anyway, it is presumably better to stumble onwards with
2211 * something and try to run the system in a "less than optimal"
2212 * mode that matches the user configuration.
2213 */
2214 i915_vma_pin_fence(vma);
2215 }
2216
2217 i915_vma_get(vma);
2218 err:
2219 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2220
2221 intel_runtime_pm_put(dev_priv);
2222 return vma;
2223 }
2224
2225 void intel_unpin_fb_vma(struct i915_vma *vma)
2226 {
2227 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2228
2229 i915_vma_unpin_fence(vma);
2230 i915_gem_object_unpin_from_display_plane(vma);
2231 i915_vma_put(vma);
2232 }
2233
2234 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2235 unsigned int rotation)
2236 {
2237 if (drm_rotation_90_or_270(rotation))
2238 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2239 else
2240 return fb->pitches[plane];
2241 }
2242
2243 /*
2244 * Convert the x/y offsets into a linear offset.
2245 * Only valid with 0/180 degree rotation, which is fine since linear
2246 * offset is only used with linear buffers on pre-hsw and tiled buffers
2247 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2248 */
2249 u32 intel_fb_xy_to_linear(int x, int y,
2250 const struct intel_plane_state *state,
2251 int plane)
2252 {
2253 const struct drm_framebuffer *fb = state->base.fb;
2254 unsigned int cpp = fb->format->cpp[plane];
2255 unsigned int pitch = fb->pitches[plane];
2256
2257 return y * pitch + x * cpp;
2258 }
2259
2260 /*
2261 * Add the x/y offsets derived from fb->offsets[] to the user
2262 * specified plane src x/y offsets. The resulting x/y offsets
2263 * specify the start of scanout from the beginning of the gtt mapping.
2264 */
2265 void intel_add_fb_offsets(int *x, int *y,
2266 const struct intel_plane_state *state,
2267 int plane)
2268
2269 {
2270 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2271 unsigned int rotation = state->base.rotation;
2272
2273 if (drm_rotation_90_or_270(rotation)) {
2274 *x += intel_fb->rotated[plane].x;
2275 *y += intel_fb->rotated[plane].y;
2276 } else {
2277 *x += intel_fb->normal[plane].x;
2278 *y += intel_fb->normal[plane].y;
2279 }
2280 }
2281
2282 static u32 __intel_adjust_tile_offset(int *x, int *y,
2283 unsigned int tile_width,
2284 unsigned int tile_height,
2285 unsigned int tile_size,
2286 unsigned int pitch_tiles,
2287 u32 old_offset,
2288 u32 new_offset)
2289 {
2290 unsigned int pitch_pixels = pitch_tiles * tile_width;
2291 unsigned int tiles;
2292
2293 WARN_ON(old_offset & (tile_size - 1));
2294 WARN_ON(new_offset & (tile_size - 1));
2295 WARN_ON(new_offset > old_offset);
2296
2297 tiles = (old_offset - new_offset) / tile_size;
2298
2299 *y += tiles / pitch_tiles * tile_height;
2300 *x += tiles % pitch_tiles * tile_width;
2301
2302 /* minimize x in case it got needlessly big */
2303 *y += *x / pitch_pixels * tile_height;
2304 *x %= pitch_pixels;
2305
2306 return new_offset;
2307 }
2308
2309 static u32 _intel_adjust_tile_offset(int *x, int *y,
2310 const struct drm_framebuffer *fb, int plane,
2311 unsigned int rotation,
2312 u32 old_offset, u32 new_offset)
2313 {
2314 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2315 unsigned int cpp = fb->format->cpp[plane];
2316 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2317
2318 WARN_ON(new_offset > old_offset);
2319
2320 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2321 unsigned int tile_size, tile_width, tile_height;
2322 unsigned int pitch_tiles;
2323
2324 tile_size = intel_tile_size(dev_priv);
2325 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2326
2327 if (drm_rotation_90_or_270(rotation)) {
2328 pitch_tiles = pitch / tile_height;
2329 swap(tile_width, tile_height);
2330 } else {
2331 pitch_tiles = pitch / (tile_width * cpp);
2332 }
2333
2334 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2335 tile_size, pitch_tiles,
2336 old_offset, new_offset);
2337 } else {
2338 old_offset += *y * pitch + *x * cpp;
2339
2340 *y = (old_offset - new_offset) / pitch;
2341 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2342 }
2343
2344 return new_offset;
2345 }
2346
2347 /*
2348 * Adjust the tile offset by moving the difference into
2349 * the x/y offsets.
2350 */
2351 static u32 intel_adjust_tile_offset(int *x, int *y,
2352 const struct intel_plane_state *state, int plane,
2353 u32 old_offset, u32 new_offset)
2354 {
2355 return _intel_adjust_tile_offset(x, y, state->base.fb, plane,
2356 state->base.rotation,
2357 old_offset, new_offset);
2358 }
2359
2360 /*
2361 * Computes the linear offset to the base tile and adjusts
2362 * x, y. bytes per pixel is assumed to be a power-of-two.
2363 *
2364 * In the 90/270 rotated case, x and y are assumed
2365 * to be already rotated to match the rotated GTT view, and
2366 * pitch is the tile_height aligned framebuffer height.
2367 *
2368 * This function is used when computing the derived information
2369 * under intel_framebuffer, so using any of that information
2370 * here is not allowed. Anything under drm_framebuffer can be
2371 * used. This is why the user has to pass in the pitch since it
2372 * is specified in the rotated orientation.
2373 */
2374 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2375 int *x, int *y,
2376 const struct drm_framebuffer *fb, int plane,
2377 unsigned int pitch,
2378 unsigned int rotation,
2379 u32 alignment)
2380 {
2381 uint64_t fb_modifier = fb->modifier;
2382 unsigned int cpp = fb->format->cpp[plane];
2383 u32 offset, offset_aligned;
2384
2385 if (alignment)
2386 alignment--;
2387
2388 if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2389 unsigned int tile_size, tile_width, tile_height;
2390 unsigned int tile_rows, tiles, pitch_tiles;
2391
2392 tile_size = intel_tile_size(dev_priv);
2393 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2394
2395 if (drm_rotation_90_or_270(rotation)) {
2396 pitch_tiles = pitch / tile_height;
2397 swap(tile_width, tile_height);
2398 } else {
2399 pitch_tiles = pitch / (tile_width * cpp);
2400 }
2401
2402 tile_rows = *y / tile_height;
2403 *y %= tile_height;
2404
2405 tiles = *x / tile_width;
2406 *x %= tile_width;
2407
2408 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2409 offset_aligned = offset & ~alignment;
2410
2411 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2412 tile_size, pitch_tiles,
2413 offset, offset_aligned);
2414 } else {
2415 offset = *y * pitch + *x * cpp;
2416 offset_aligned = offset & ~alignment;
2417
2418 *y = (offset & alignment) / pitch;
2419 *x = ((offset & alignment) - *y * pitch) / cpp;
2420 }
2421
2422 return offset_aligned;
2423 }
2424
2425 u32 intel_compute_tile_offset(int *x, int *y,
2426 const struct intel_plane_state *state,
2427 int plane)
2428 {
2429 struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2430 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2431 const struct drm_framebuffer *fb = state->base.fb;
2432 unsigned int rotation = state->base.rotation;
2433 int pitch = intel_fb_pitch(fb, plane, rotation);
2434 u32 alignment;
2435
2436 if (intel_plane->id == PLANE_CURSOR)
2437 alignment = intel_cursor_alignment(dev_priv);
2438 else
2439 alignment = intel_surf_alignment(fb, plane);
2440
2441 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2442 rotation, alignment);
2443 }
2444
2445 /* Convert the fb->offset[] into x/y offsets */
2446 static int intel_fb_offset_to_xy(int *x, int *y,
2447 const struct drm_framebuffer *fb, int plane)
2448 {
2449 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2450
2451 if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2452 fb->offsets[plane] % intel_tile_size(dev_priv))
2453 return -EINVAL;
2454
2455 *x = 0;
2456 *y = 0;
2457
2458 _intel_adjust_tile_offset(x, y,
2459 fb, plane, DRM_MODE_ROTATE_0,
2460 fb->offsets[plane], 0);
2461
2462 return 0;
2463 }
2464
2465 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2466 {
2467 switch (fb_modifier) {
2468 case I915_FORMAT_MOD_X_TILED:
2469 return I915_TILING_X;
2470 case I915_FORMAT_MOD_Y_TILED:
2471 case I915_FORMAT_MOD_Y_TILED_CCS:
2472 return I915_TILING_Y;
2473 default:
2474 return I915_TILING_NONE;
2475 }
2476 }
2477
2478 static const struct drm_format_info ccs_formats[] = {
2479 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2480 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2481 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2482 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2483 };
2484
2485 static const struct drm_format_info *
2486 lookup_format_info(const struct drm_format_info formats[],
2487 int num_formats, u32 format)
2488 {
2489 int i;
2490
2491 for (i = 0; i < num_formats; i++) {
2492 if (formats[i].format == format)
2493 return &formats[i];
2494 }
2495
2496 return NULL;
2497 }
2498
2499 static const struct drm_format_info *
2500 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2501 {
2502 switch (cmd->modifier[0]) {
2503 case I915_FORMAT_MOD_Y_TILED_CCS:
2504 case I915_FORMAT_MOD_Yf_TILED_CCS:
2505 return lookup_format_info(ccs_formats,
2506 ARRAY_SIZE(ccs_formats),
2507 cmd->pixel_format);
2508 default:
2509 return NULL;
2510 }
2511 }
2512
2513 static int
2514 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2515 struct drm_framebuffer *fb)
2516 {
2517 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2518 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2519 u32 gtt_offset_rotated = 0;
2520 unsigned int max_size = 0;
2521 int i, num_planes = fb->format->num_planes;
2522 unsigned int tile_size = intel_tile_size(dev_priv);
2523
2524 for (i = 0; i < num_planes; i++) {
2525 unsigned int width, height;
2526 unsigned int cpp, size;
2527 u32 offset;
2528 int x, y;
2529 int ret;
2530
2531 cpp = fb->format->cpp[i];
2532 width = drm_framebuffer_plane_width(fb->width, fb, i);
2533 height = drm_framebuffer_plane_height(fb->height, fb, i);
2534
2535 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2536 if (ret) {
2537 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2538 i, fb->offsets[i]);
2539 return ret;
2540 }
2541
2542 if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2543 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) {
2544 int hsub = fb->format->hsub;
2545 int vsub = fb->format->vsub;
2546 int tile_width, tile_height;
2547 int main_x, main_y;
2548 int ccs_x, ccs_y;
2549
2550 intel_tile_dims(fb, i, &tile_width, &tile_height);
2551 tile_width *= hsub;
2552 tile_height *= vsub;
2553
2554 ccs_x = (x * hsub) % tile_width;
2555 ccs_y = (y * vsub) % tile_height;
2556 main_x = intel_fb->normal[0].x % tile_width;
2557 main_y = intel_fb->normal[0].y % tile_height;
2558
2559 /*
2560 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2561 * x/y offsets must match between CCS and the main surface.
2562 */
2563 if (main_x != ccs_x || main_y != ccs_y) {
2564 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2565 main_x, main_y,
2566 ccs_x, ccs_y,
2567 intel_fb->normal[0].x,
2568 intel_fb->normal[0].y,
2569 x, y);
2570 return -EINVAL;
2571 }
2572 }
2573
2574 /*
2575 * The fence (if used) is aligned to the start of the object
2576 * so having the framebuffer wrap around across the edge of the
2577 * fenced region doesn't really work. We have no API to configure
2578 * the fence start offset within the object (nor could we probably
2579 * on gen2/3). So it's just easier if we just require that the
2580 * fb layout agrees with the fence layout. We already check that the
2581 * fb stride matches the fence stride elsewhere.
2582 */
2583 if (i == 0 && i915_gem_object_is_tiled(intel_fb->obj) &&
2584 (x + width) * cpp > fb->pitches[i]) {
2585 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2586 i, fb->offsets[i]);
2587 return -EINVAL;
2588 }
2589
2590 /*
2591 * First pixel of the framebuffer from
2592 * the start of the normal gtt mapping.
2593 */
2594 intel_fb->normal[i].x = x;
2595 intel_fb->normal[i].y = y;
2596
2597 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2598 fb, i, fb->pitches[i],
2599 DRM_MODE_ROTATE_0, tile_size);
2600 offset /= tile_size;
2601
2602 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2603 unsigned int tile_width, tile_height;
2604 unsigned int pitch_tiles;
2605 struct drm_rect r;
2606
2607 intel_tile_dims(fb, i, &tile_width, &tile_height);
2608
2609 rot_info->plane[i].offset = offset;
2610 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2611 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2612 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2613
2614 intel_fb->rotated[i].pitch =
2615 rot_info->plane[i].height * tile_height;
2616
2617 /* how many tiles does this plane need */
2618 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2619 /*
2620 * If the plane isn't horizontally tile aligned,
2621 * we need one more tile.
2622 */
2623 if (x != 0)
2624 size++;
2625
2626 /* rotate the x/y offsets to match the GTT view */
2627 r.x1 = x;
2628 r.y1 = y;
2629 r.x2 = x + width;
2630 r.y2 = y + height;
2631 drm_rect_rotate(&r,
2632 rot_info->plane[i].width * tile_width,
2633 rot_info->plane[i].height * tile_height,
2634 DRM_MODE_ROTATE_270);
2635 x = r.x1;
2636 y = r.y1;
2637
2638 /* rotate the tile dimensions to match the GTT view */
2639 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2640 swap(tile_width, tile_height);
2641
2642 /*
2643 * We only keep the x/y offsets, so push all of the
2644 * gtt offset into the x/y offsets.
2645 */
2646 __intel_adjust_tile_offset(&x, &y,
2647 tile_width, tile_height,
2648 tile_size, pitch_tiles,
2649 gtt_offset_rotated * tile_size, 0);
2650
2651 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2652
2653 /*
2654 * First pixel of the framebuffer from
2655 * the start of the rotated gtt mapping.
2656 */
2657 intel_fb->rotated[i].x = x;
2658 intel_fb->rotated[i].y = y;
2659 } else {
2660 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2661 x * cpp, tile_size);
2662 }
2663
2664 /* how many tiles in total needed in the bo */
2665 max_size = max(max_size, offset + size);
2666 }
2667
2668 if (max_size * tile_size > intel_fb->obj->base.size) {
2669 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2670 max_size * tile_size, intel_fb->obj->base.size);
2671 return -EINVAL;
2672 }
2673
2674 return 0;
2675 }
2676
2677 static int i9xx_format_to_fourcc(int format)
2678 {
2679 switch (format) {
2680 case DISPPLANE_8BPP:
2681 return DRM_FORMAT_C8;
2682 case DISPPLANE_BGRX555:
2683 return DRM_FORMAT_XRGB1555;
2684 case DISPPLANE_BGRX565:
2685 return DRM_FORMAT_RGB565;
2686 default:
2687 case DISPPLANE_BGRX888:
2688 return DRM_FORMAT_XRGB8888;
2689 case DISPPLANE_RGBX888:
2690 return DRM_FORMAT_XBGR8888;
2691 case DISPPLANE_BGRX101010:
2692 return DRM_FORMAT_XRGB2101010;
2693 case DISPPLANE_RGBX101010:
2694 return DRM_FORMAT_XBGR2101010;
2695 }
2696 }
2697
2698 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2699 {
2700 switch (format) {
2701 case PLANE_CTL_FORMAT_RGB_565:
2702 return DRM_FORMAT_RGB565;
2703 default:
2704 case PLANE_CTL_FORMAT_XRGB_8888:
2705 if (rgb_order) {
2706 if (alpha)
2707 return DRM_FORMAT_ABGR8888;
2708 else
2709 return DRM_FORMAT_XBGR8888;
2710 } else {
2711 if (alpha)
2712 return DRM_FORMAT_ARGB8888;
2713 else
2714 return DRM_FORMAT_XRGB8888;
2715 }
2716 case PLANE_CTL_FORMAT_XRGB_2101010:
2717 if (rgb_order)
2718 return DRM_FORMAT_XBGR2101010;
2719 else
2720 return DRM_FORMAT_XRGB2101010;
2721 }
2722 }
2723
2724 static bool
2725 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2726 struct intel_initial_plane_config *plane_config)
2727 {
2728 struct drm_device *dev = crtc->base.dev;
2729 struct drm_i915_private *dev_priv = to_i915(dev);
2730 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2731 struct drm_i915_gem_object *obj = NULL;
2732 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2733 struct drm_framebuffer *fb = &plane_config->fb->base;
2734 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2735 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2736 PAGE_SIZE);
2737
2738 size_aligned -= base_aligned;
2739
2740 if (plane_config->size == 0)
2741 return false;
2742
2743 /* If the FB is too big, just don't use it since fbdev is not very
2744 * important and we should probably use that space with FBC or other
2745 * features. */
2746 if (size_aligned * 2 > ggtt->stolen_usable_size)
2747 return false;
2748
2749 mutex_lock(&dev->struct_mutex);
2750 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2751 base_aligned,
2752 base_aligned,
2753 size_aligned);
2754 mutex_unlock(&dev->struct_mutex);
2755 if (!obj)
2756 return false;
2757
2758 if (plane_config->tiling == I915_TILING_X)
2759 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2760
2761 mode_cmd.pixel_format = fb->format->format;
2762 mode_cmd.width = fb->width;
2763 mode_cmd.height = fb->height;
2764 mode_cmd.pitches[0] = fb->pitches[0];
2765 mode_cmd.modifier[0] = fb->modifier;
2766 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2767
2768 if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2769 DRM_DEBUG_KMS("intel fb init failed\n");
2770 goto out_unref_obj;
2771 }
2772
2773
2774 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2775 return true;
2776
2777 out_unref_obj:
2778 i915_gem_object_put(obj);
2779 return false;
2780 }
2781
2782 static void
2783 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2784 struct intel_plane_state *plane_state,
2785 bool visible)
2786 {
2787 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2788
2789 plane_state->base.visible = visible;
2790
2791 /* FIXME pre-g4x don't work like this */
2792 if (visible) {
2793 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2794 crtc_state->active_planes |= BIT(plane->id);
2795 } else {
2796 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2797 crtc_state->active_planes &= ~BIT(plane->id);
2798 }
2799
2800 DRM_DEBUG_KMS("%s active planes 0x%x\n",
2801 crtc_state->base.crtc->name,
2802 crtc_state->active_planes);
2803 }
2804
2805 static void
2806 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2807 struct intel_initial_plane_config *plane_config)
2808 {
2809 struct drm_device *dev = intel_crtc->base.dev;
2810 struct drm_i915_private *dev_priv = to_i915(dev);
2811 struct drm_crtc *c;
2812 struct drm_i915_gem_object *obj;
2813 struct drm_plane *primary = intel_crtc->base.primary;
2814 struct drm_plane_state *plane_state = primary->state;
2815 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2816 struct intel_plane *intel_plane = to_intel_plane(primary);
2817 struct intel_plane_state *intel_state =
2818 to_intel_plane_state(plane_state);
2819 struct drm_framebuffer *fb;
2820
2821 if (!plane_config->fb)
2822 return;
2823
2824 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2825 fb = &plane_config->fb->base;
2826 goto valid_fb;
2827 }
2828
2829 kfree(plane_config->fb);
2830
2831 /*
2832 * Failed to alloc the obj, check to see if we should share
2833 * an fb with another CRTC instead
2834 */
2835 for_each_crtc(dev, c) {
2836 struct intel_plane_state *state;
2837
2838 if (c == &intel_crtc->base)
2839 continue;
2840
2841 if (!to_intel_crtc(c)->active)
2842 continue;
2843
2844 state = to_intel_plane_state(c->primary->state);
2845 if (!state->vma)
2846 continue;
2847
2848 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2849 fb = c->primary->fb;
2850 drm_framebuffer_get(fb);
2851 goto valid_fb;
2852 }
2853 }
2854
2855 /*
2856 * We've failed to reconstruct the BIOS FB. Current display state
2857 * indicates that the primary plane is visible, but has a NULL FB,
2858 * which will lead to problems later if we don't fix it up. The
2859 * simplest solution is to just disable the primary plane now and
2860 * pretend the BIOS never had it enabled.
2861 */
2862 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2863 to_intel_plane_state(plane_state),
2864 false);
2865 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2866 trace_intel_disable_plane(primary, intel_crtc);
2867 intel_plane->disable_plane(intel_plane, intel_crtc);
2868
2869 return;
2870
2871 valid_fb:
2872 mutex_lock(&dev->struct_mutex);
2873 intel_state->vma =
2874 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2875 mutex_unlock(&dev->struct_mutex);
2876 if (IS_ERR(intel_state->vma)) {
2877 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2878 intel_crtc->pipe, PTR_ERR(intel_state->vma));
2879
2880 intel_state->vma = NULL;
2881 drm_framebuffer_put(fb);
2882 return;
2883 }
2884
2885 plane_state->src_x = 0;
2886 plane_state->src_y = 0;
2887 plane_state->src_w = fb->width << 16;
2888 plane_state->src_h = fb->height << 16;
2889
2890 plane_state->crtc_x = 0;
2891 plane_state->crtc_y = 0;
2892 plane_state->crtc_w = fb->width;
2893 plane_state->crtc_h = fb->height;
2894
2895 intel_state->base.src = drm_plane_state_src(plane_state);
2896 intel_state->base.dst = drm_plane_state_dest(plane_state);
2897
2898 obj = intel_fb_obj(fb);
2899 if (i915_gem_object_is_tiled(obj))
2900 dev_priv->preserve_bios_swizzle = true;
2901
2902 drm_framebuffer_get(fb);
2903 primary->fb = primary->state->fb = fb;
2904 primary->crtc = primary->state->crtc = &intel_crtc->base;
2905
2906 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2907 to_intel_plane_state(plane_state),
2908 true);
2909
2910 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2911 &obj->frontbuffer_bits);
2912 }
2913
2914 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2915 unsigned int rotation)
2916 {
2917 int cpp = fb->format->cpp[plane];
2918
2919 switch (fb->modifier) {
2920 case DRM_FORMAT_MOD_LINEAR:
2921 case I915_FORMAT_MOD_X_TILED:
2922 switch (cpp) {
2923 case 8:
2924 return 4096;
2925 case 4:
2926 case 2:
2927 case 1:
2928 return 8192;
2929 default:
2930 MISSING_CASE(cpp);
2931 break;
2932 }
2933 break;
2934 case I915_FORMAT_MOD_Y_TILED_CCS:
2935 case I915_FORMAT_MOD_Yf_TILED_CCS:
2936 /* FIXME AUX plane? */
2937 case I915_FORMAT_MOD_Y_TILED:
2938 case I915_FORMAT_MOD_Yf_TILED:
2939 switch (cpp) {
2940 case 8:
2941 return 2048;
2942 case 4:
2943 return 4096;
2944 case 2:
2945 case 1:
2946 return 8192;
2947 default:
2948 MISSING_CASE(cpp);
2949 break;
2950 }
2951 break;
2952 default:
2953 MISSING_CASE(fb->modifier);
2954 }
2955
2956 return 2048;
2957 }
2958
2959 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
2960 int main_x, int main_y, u32 main_offset)
2961 {
2962 const struct drm_framebuffer *fb = plane_state->base.fb;
2963 int hsub = fb->format->hsub;
2964 int vsub = fb->format->vsub;
2965 int aux_x = plane_state->aux.x;
2966 int aux_y = plane_state->aux.y;
2967 u32 aux_offset = plane_state->aux.offset;
2968 u32 alignment = intel_surf_alignment(fb, 1);
2969
2970 while (aux_offset >= main_offset && aux_y <= main_y) {
2971 int x, y;
2972
2973 if (aux_x == main_x && aux_y == main_y)
2974 break;
2975
2976 if (aux_offset == 0)
2977 break;
2978
2979 x = aux_x / hsub;
2980 y = aux_y / vsub;
2981 aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1,
2982 aux_offset, aux_offset - alignment);
2983 aux_x = x * hsub + aux_x % hsub;
2984 aux_y = y * vsub + aux_y % vsub;
2985 }
2986
2987 if (aux_x != main_x || aux_y != main_y)
2988 return false;
2989
2990 plane_state->aux.offset = aux_offset;
2991 plane_state->aux.x = aux_x;
2992 plane_state->aux.y = aux_y;
2993
2994 return true;
2995 }
2996
2997 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2998 {
2999 const struct drm_framebuffer *fb = plane_state->base.fb;
3000 unsigned int rotation = plane_state->base.rotation;
3001 int x = plane_state->base.src.x1 >> 16;
3002 int y = plane_state->base.src.y1 >> 16;
3003 int w = drm_rect_width(&plane_state->base.src) >> 16;
3004 int h = drm_rect_height(&plane_state->base.src) >> 16;
3005 int max_width = skl_max_plane_width(fb, 0, rotation);
3006 int max_height = 4096;
3007 u32 alignment, offset, aux_offset = plane_state->aux.offset;
3008
3009 if (w > max_width || h > max_height) {
3010 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3011 w, h, max_width, max_height);
3012 return -EINVAL;
3013 }
3014
3015 intel_add_fb_offsets(&x, &y, plane_state, 0);
3016 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
3017 alignment = intel_surf_alignment(fb, 0);
3018
3019 /*
3020 * AUX surface offset is specified as the distance from the
3021 * main surface offset, and it must be non-negative. Make
3022 * sure that is what we will get.
3023 */
3024 if (offset > aux_offset)
3025 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3026 offset, aux_offset & ~(alignment - 1));
3027
3028 /*
3029 * When using an X-tiled surface, the plane blows up
3030 * if the x offset + width exceed the stride.
3031 *
3032 * TODO: linear and Y-tiled seem fine, Yf untested,
3033 */
3034 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3035 int cpp = fb->format->cpp[0];
3036
3037 while ((x + w) * cpp > fb->pitches[0]) {
3038 if (offset == 0) {
3039 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3040 return -EINVAL;
3041 }
3042
3043 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3044 offset, offset - alignment);
3045 }
3046 }
3047
3048 /*
3049 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3050 * they match with the main surface x/y offsets.
3051 */
3052 if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3053 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3054 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3055 if (offset == 0)
3056 break;
3057
3058 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3059 offset, offset - alignment);
3060 }
3061
3062 if (x != plane_state->aux.x || y != plane_state->aux.y) {
3063 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3064 return -EINVAL;
3065 }
3066 }
3067
3068 plane_state->main.offset = offset;
3069 plane_state->main.x = x;
3070 plane_state->main.y = y;
3071
3072 return 0;
3073 }
3074
3075 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3076 {
3077 const struct drm_framebuffer *fb = plane_state->base.fb;
3078 unsigned int rotation = plane_state->base.rotation;
3079 int max_width = skl_max_plane_width(fb, 1, rotation);
3080 int max_height = 4096;
3081 int x = plane_state->base.src.x1 >> 17;
3082 int y = plane_state->base.src.y1 >> 17;
3083 int w = drm_rect_width(&plane_state->base.src) >> 17;
3084 int h = drm_rect_height(&plane_state->base.src) >> 17;
3085 u32 offset;
3086
3087 intel_add_fb_offsets(&x, &y, plane_state, 1);
3088 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3089
3090 /* FIXME not quite sure how/if these apply to the chroma plane */
3091 if (w > max_width || h > max_height) {
3092 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3093 w, h, max_width, max_height);
3094 return -EINVAL;
3095 }
3096
3097 plane_state->aux.offset = offset;
3098 plane_state->aux.x = x;
3099 plane_state->aux.y = y;
3100
3101 return 0;
3102 }
3103
3104 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3105 {
3106 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
3107 struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
3108 const struct drm_framebuffer *fb = plane_state->base.fb;
3109 int src_x = plane_state->base.src.x1 >> 16;
3110 int src_y = plane_state->base.src.y1 >> 16;
3111 int hsub = fb->format->hsub;
3112 int vsub = fb->format->vsub;
3113 int x = src_x / hsub;
3114 int y = src_y / vsub;
3115 u32 offset;
3116
3117 switch (plane->id) {
3118 case PLANE_PRIMARY:
3119 case PLANE_SPRITE0:
3120 break;
3121 default:
3122 DRM_DEBUG_KMS("RC support only on plane 1 and 2\n");
3123 return -EINVAL;
3124 }
3125
3126 if (crtc->pipe == PIPE_C) {
3127 DRM_DEBUG_KMS("No RC support on pipe C\n");
3128 return -EINVAL;
3129 }
3130
3131 if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) {
3132 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n",
3133 plane_state->base.rotation);
3134 return -EINVAL;
3135 }
3136
3137 intel_add_fb_offsets(&x, &y, plane_state, 1);
3138 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3139
3140 plane_state->aux.offset = offset;
3141 plane_state->aux.x = x * hsub + src_x % hsub;
3142 plane_state->aux.y = y * vsub + src_y % vsub;
3143
3144 return 0;
3145 }
3146
3147 int skl_check_plane_surface(struct intel_plane_state *plane_state)
3148 {
3149 const struct drm_framebuffer *fb = plane_state->base.fb;
3150 unsigned int rotation = plane_state->base.rotation;
3151 int ret;
3152
3153 if (!plane_state->base.visible)
3154 return 0;
3155
3156 /* Rotate src coordinates to match rotated GTT view */
3157 if (drm_rotation_90_or_270(rotation))
3158 drm_rect_rotate(&plane_state->base.src,
3159 fb->width << 16, fb->height << 16,
3160 DRM_MODE_ROTATE_270);
3161
3162 /*
3163 * Handle the AUX surface first since
3164 * the main surface setup depends on it.
3165 */
3166 if (fb->format->format == DRM_FORMAT_NV12) {
3167 ret = skl_check_nv12_aux_surface(plane_state);
3168 if (ret)
3169 return ret;
3170 } else if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3171 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3172 ret = skl_check_ccs_aux_surface(plane_state);
3173 if (ret)
3174 return ret;
3175 } else {
3176 plane_state->aux.offset = ~0xfff;
3177 plane_state->aux.x = 0;
3178 plane_state->aux.y = 0;
3179 }
3180
3181 ret = skl_check_main_surface(plane_state);
3182 if (ret)
3183 return ret;
3184
3185 return 0;
3186 }
3187
3188 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3189 const struct intel_plane_state *plane_state)
3190 {
3191 struct drm_i915_private *dev_priv =
3192 to_i915(plane_state->base.plane->dev);
3193 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3194 const struct drm_framebuffer *fb = plane_state->base.fb;
3195 unsigned int rotation = plane_state->base.rotation;
3196 u32 dspcntr;
3197
3198 dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
3199
3200 if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
3201 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
3202 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3203
3204 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3205 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3206
3207 if (INTEL_GEN(dev_priv) < 4)
3208 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3209
3210 switch (fb->format->format) {
3211 case DRM_FORMAT_C8:
3212 dspcntr |= DISPPLANE_8BPP;
3213 break;
3214 case DRM_FORMAT_XRGB1555:
3215 dspcntr |= DISPPLANE_BGRX555;
3216 break;
3217 case DRM_FORMAT_RGB565:
3218 dspcntr |= DISPPLANE_BGRX565;
3219 break;
3220 case DRM_FORMAT_XRGB8888:
3221 dspcntr |= DISPPLANE_BGRX888;
3222 break;
3223 case DRM_FORMAT_XBGR8888:
3224 dspcntr |= DISPPLANE_RGBX888;
3225 break;
3226 case DRM_FORMAT_XRGB2101010:
3227 dspcntr |= DISPPLANE_BGRX101010;
3228 break;
3229 case DRM_FORMAT_XBGR2101010:
3230 dspcntr |= DISPPLANE_RGBX101010;
3231 break;
3232 default:
3233 MISSING_CASE(fb->format->format);
3234 return 0;
3235 }
3236
3237 if (INTEL_GEN(dev_priv) >= 4 &&
3238 fb->modifier == I915_FORMAT_MOD_X_TILED)
3239 dspcntr |= DISPPLANE_TILED;
3240
3241 if (rotation & DRM_MODE_ROTATE_180)
3242 dspcntr |= DISPPLANE_ROTATE_180;
3243
3244 if (rotation & DRM_MODE_REFLECT_X)
3245 dspcntr |= DISPPLANE_MIRROR;
3246
3247 return dspcntr;
3248 }
3249
3250 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3251 {
3252 struct drm_i915_private *dev_priv =
3253 to_i915(plane_state->base.plane->dev);
3254 int src_x = plane_state->base.src.x1 >> 16;
3255 int src_y = plane_state->base.src.y1 >> 16;
3256 u32 offset;
3257
3258 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3259
3260 if (INTEL_GEN(dev_priv) >= 4)
3261 offset = intel_compute_tile_offset(&src_x, &src_y,
3262 plane_state, 0);
3263 else
3264 offset = 0;
3265
3266 /* HSW/BDW do this automagically in hardware */
3267 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3268 unsigned int rotation = plane_state->base.rotation;
3269 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3270 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3271
3272 if (rotation & DRM_MODE_ROTATE_180) {
3273 src_x += src_w - 1;
3274 src_y += src_h - 1;
3275 } else if (rotation & DRM_MODE_REFLECT_X) {
3276 src_x += src_w - 1;
3277 }
3278 }
3279
3280 plane_state->main.offset = offset;
3281 plane_state->main.x = src_x;
3282 plane_state->main.y = src_y;
3283
3284 return 0;
3285 }
3286
3287 static void i9xx_update_primary_plane(struct intel_plane *primary,
3288 const struct intel_crtc_state *crtc_state,
3289 const struct intel_plane_state *plane_state)
3290 {
3291 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3292 const struct drm_framebuffer *fb = plane_state->base.fb;
3293 enum plane plane = primary->plane;
3294 u32 linear_offset;
3295 u32 dspcntr = plane_state->ctl;
3296 i915_reg_t reg = DSPCNTR(plane);
3297 int x = plane_state->main.x;
3298 int y = plane_state->main.y;
3299 unsigned long irqflags;
3300 u32 dspaddr_offset;
3301
3302 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3303
3304 if (INTEL_GEN(dev_priv) >= 4)
3305 dspaddr_offset = plane_state->main.offset;
3306 else
3307 dspaddr_offset = linear_offset;
3308
3309 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3310
3311 if (INTEL_GEN(dev_priv) < 4) {
3312 /* pipesrc and dspsize control the size that is scaled from,
3313 * which should always be the user's requested size.
3314 */
3315 I915_WRITE_FW(DSPSIZE(plane),
3316 ((crtc_state->pipe_src_h - 1) << 16) |
3317 (crtc_state->pipe_src_w - 1));
3318 I915_WRITE_FW(DSPPOS(plane), 0);
3319 } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3320 I915_WRITE_FW(PRIMSIZE(plane),
3321 ((crtc_state->pipe_src_h - 1) << 16) |
3322 (crtc_state->pipe_src_w - 1));
3323 I915_WRITE_FW(PRIMPOS(plane), 0);
3324 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3325 }
3326
3327 I915_WRITE_FW(reg, dspcntr);
3328
3329 I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3330 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3331 I915_WRITE_FW(DSPSURF(plane),
3332 intel_plane_ggtt_offset(plane_state) +
3333 dspaddr_offset);
3334 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3335 } else if (INTEL_GEN(dev_priv) >= 4) {
3336 I915_WRITE_FW(DSPSURF(plane),
3337 intel_plane_ggtt_offset(plane_state) +
3338 dspaddr_offset);
3339 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3340 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3341 } else {
3342 I915_WRITE_FW(DSPADDR(plane),
3343 intel_plane_ggtt_offset(plane_state) +
3344 dspaddr_offset);
3345 }
3346 POSTING_READ_FW(reg);
3347
3348 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3349 }
3350
3351 static void i9xx_disable_primary_plane(struct intel_plane *primary,
3352 struct intel_crtc *crtc)
3353 {
3354 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3355 enum plane plane = primary->plane;
3356 unsigned long irqflags;
3357
3358 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3359
3360 I915_WRITE_FW(DSPCNTR(plane), 0);
3361 if (INTEL_INFO(dev_priv)->gen >= 4)
3362 I915_WRITE_FW(DSPSURF(plane), 0);
3363 else
3364 I915_WRITE_FW(DSPADDR(plane), 0);
3365 POSTING_READ_FW(DSPCNTR(plane));
3366
3367 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3368 }
3369
3370 static u32
3371 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3372 {
3373 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3374 return 64;
3375 else
3376 return intel_tile_width_bytes(fb, plane);
3377 }
3378
3379 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3380 {
3381 struct drm_device *dev = intel_crtc->base.dev;
3382 struct drm_i915_private *dev_priv = to_i915(dev);
3383
3384 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3385 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3386 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3387 }
3388
3389 /*
3390 * This function detaches (aka. unbinds) unused scalers in hardware
3391 */
3392 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3393 {
3394 struct intel_crtc_scaler_state *scaler_state;
3395 int i;
3396
3397 scaler_state = &intel_crtc->config->scaler_state;
3398
3399 /* loop through and disable scalers that aren't in use */
3400 for (i = 0; i < intel_crtc->num_scalers; i++) {
3401 if (!scaler_state->scalers[i].in_use)
3402 skl_detach_scaler(intel_crtc, i);
3403 }
3404 }
3405
3406 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3407 unsigned int rotation)
3408 {
3409 u32 stride;
3410
3411 if (plane >= fb->format->num_planes)
3412 return 0;
3413
3414 stride = intel_fb_pitch(fb, plane, rotation);
3415
3416 /*
3417 * The stride is either expressed as a multiple of 64 bytes chunks for
3418 * linear buffers or in number of tiles for tiled buffers.
3419 */
3420 if (drm_rotation_90_or_270(rotation))
3421 stride /= intel_tile_height(fb, plane);
3422 else
3423 stride /= intel_fb_stride_alignment(fb, plane);
3424
3425 return stride;
3426 }
3427
3428 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3429 {
3430 switch (pixel_format) {
3431 case DRM_FORMAT_C8:
3432 return PLANE_CTL_FORMAT_INDEXED;
3433 case DRM_FORMAT_RGB565:
3434 return PLANE_CTL_FORMAT_RGB_565;
3435 case DRM_FORMAT_XBGR8888:
3436 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3437 case DRM_FORMAT_XRGB8888:
3438 return PLANE_CTL_FORMAT_XRGB_8888;
3439 /*
3440 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3441 * to be already pre-multiplied. We need to add a knob (or a different
3442 * DRM_FORMAT) for user-space to configure that.
3443 */
3444 case DRM_FORMAT_ABGR8888:
3445 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3446 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3447 case DRM_FORMAT_ARGB8888:
3448 return PLANE_CTL_FORMAT_XRGB_8888 |
3449 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3450 case DRM_FORMAT_XRGB2101010:
3451 return PLANE_CTL_FORMAT_XRGB_2101010;
3452 case DRM_FORMAT_XBGR2101010:
3453 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3454 case DRM_FORMAT_YUYV:
3455 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3456 case DRM_FORMAT_YVYU:
3457 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3458 case DRM_FORMAT_UYVY:
3459 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3460 case DRM_FORMAT_VYUY:
3461 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3462 default:
3463 MISSING_CASE(pixel_format);
3464 }
3465
3466 return 0;
3467 }
3468
3469 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3470 {
3471 switch (fb_modifier) {
3472 case DRM_FORMAT_MOD_LINEAR:
3473 break;
3474 case I915_FORMAT_MOD_X_TILED:
3475 return PLANE_CTL_TILED_X;
3476 case I915_FORMAT_MOD_Y_TILED:
3477 return PLANE_CTL_TILED_Y;
3478 case I915_FORMAT_MOD_Y_TILED_CCS:
3479 return PLANE_CTL_TILED_Y | PLANE_CTL_DECOMPRESSION_ENABLE;
3480 case I915_FORMAT_MOD_Yf_TILED:
3481 return PLANE_CTL_TILED_YF;
3482 case I915_FORMAT_MOD_Yf_TILED_CCS:
3483 return PLANE_CTL_TILED_YF | PLANE_CTL_DECOMPRESSION_ENABLE;
3484 default:
3485 MISSING_CASE(fb_modifier);
3486 }
3487
3488 return 0;
3489 }
3490
3491 static u32 skl_plane_ctl_rotation(unsigned int rotation)
3492 {
3493 switch (rotation) {
3494 case DRM_MODE_ROTATE_0:
3495 break;
3496 /*
3497 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3498 * while i915 HW rotation is clockwise, thats why this swapping.
3499 */
3500 case DRM_MODE_ROTATE_90:
3501 return PLANE_CTL_ROTATE_270;
3502 case DRM_MODE_ROTATE_180:
3503 return PLANE_CTL_ROTATE_180;
3504 case DRM_MODE_ROTATE_270:
3505 return PLANE_CTL_ROTATE_90;
3506 default:
3507 MISSING_CASE(rotation);
3508 }
3509
3510 return 0;
3511 }
3512
3513 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3514 const struct intel_plane_state *plane_state)
3515 {
3516 struct drm_i915_private *dev_priv =
3517 to_i915(plane_state->base.plane->dev);
3518 const struct drm_framebuffer *fb = plane_state->base.fb;
3519 unsigned int rotation = plane_state->base.rotation;
3520 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3521 u32 plane_ctl;
3522
3523 plane_ctl = PLANE_CTL_ENABLE;
3524
3525 if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
3526 plane_ctl |=
3527 PLANE_CTL_PIPE_GAMMA_ENABLE |
3528 PLANE_CTL_PIPE_CSC_ENABLE |
3529 PLANE_CTL_PLANE_GAMMA_DISABLE;
3530 }
3531
3532 plane_ctl |= skl_plane_ctl_format(fb->format->format);
3533 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3534 plane_ctl |= skl_plane_ctl_rotation(rotation);
3535
3536 if (key->flags & I915_SET_COLORKEY_DESTINATION)
3537 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3538 else if (key->flags & I915_SET_COLORKEY_SOURCE)
3539 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3540
3541 return plane_ctl;
3542 }
3543
3544 static int
3545 __intel_display_resume(struct drm_device *dev,
3546 struct drm_atomic_state *state,
3547 struct drm_modeset_acquire_ctx *ctx)
3548 {
3549 struct drm_crtc_state *crtc_state;
3550 struct drm_crtc *crtc;
3551 int i, ret;
3552
3553 intel_modeset_setup_hw_state(dev, ctx);
3554 i915_redisable_vga(to_i915(dev));
3555
3556 if (!state)
3557 return 0;
3558
3559 /*
3560 * We've duplicated the state, pointers to the old state are invalid.
3561 *
3562 * Don't attempt to use the old state until we commit the duplicated state.
3563 */
3564 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3565 /*
3566 * Force recalculation even if we restore
3567 * current state. With fast modeset this may not result
3568 * in a modeset when the state is compatible.
3569 */
3570 crtc_state->mode_changed = true;
3571 }
3572
3573 /* ignore any reset values/BIOS leftovers in the WM registers */
3574 if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3575 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3576
3577 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3578
3579 WARN_ON(ret == -EDEADLK);
3580 return ret;
3581 }
3582
3583 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3584 {
3585 return intel_has_gpu_reset(dev_priv) &&
3586 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3587 }
3588
3589 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3590 {
3591 struct drm_device *dev = &dev_priv->drm;
3592 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3593 struct drm_atomic_state *state;
3594 int ret;
3595
3596
3597 /* reset doesn't touch the display */
3598 if (!i915_modparams.force_reset_modeset_test &&
3599 !gpu_reset_clobbers_display(dev_priv))
3600 return;
3601
3602 /* We have a modeset vs reset deadlock, defensively unbreak it. */
3603 set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3604 wake_up_all(&dev_priv->gpu_error.wait_queue);
3605
3606 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
3607 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
3608 i915_gem_set_wedged(dev_priv);
3609 }
3610
3611 /*
3612 * Need mode_config.mutex so that we don't
3613 * trample ongoing ->detect() and whatnot.
3614 */
3615 mutex_lock(&dev->mode_config.mutex);
3616 drm_modeset_acquire_init(ctx, 0);
3617 while (1) {
3618 ret = drm_modeset_lock_all_ctx(dev, ctx);
3619 if (ret != -EDEADLK)
3620 break;
3621
3622 drm_modeset_backoff(ctx);
3623 }
3624 /*
3625 * Disabling the crtcs gracefully seems nicer. Also the
3626 * g33 docs say we should at least disable all the planes.
3627 */
3628 state = drm_atomic_helper_duplicate_state(dev, ctx);
3629 if (IS_ERR(state)) {
3630 ret = PTR_ERR(state);
3631 DRM_ERROR("Duplicating state failed with %i\n", ret);
3632 return;
3633 }
3634
3635 ret = drm_atomic_helper_disable_all(dev, ctx);
3636 if (ret) {
3637 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3638 drm_atomic_state_put(state);
3639 return;
3640 }
3641
3642 dev_priv->modeset_restore_state = state;
3643 state->acquire_ctx = ctx;
3644 }
3645
3646 void intel_finish_reset(struct drm_i915_private *dev_priv)
3647 {
3648 struct drm_device *dev = &dev_priv->drm;
3649 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3650 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3651 int ret;
3652
3653 /* reset doesn't touch the display */
3654 if (!i915_modparams.force_reset_modeset_test &&
3655 !gpu_reset_clobbers_display(dev_priv))
3656 return;
3657
3658 if (!state)
3659 goto unlock;
3660
3661 dev_priv->modeset_restore_state = NULL;
3662
3663 /* reset doesn't touch the display */
3664 if (!gpu_reset_clobbers_display(dev_priv)) {
3665 /* for testing only restore the display */
3666 ret = __intel_display_resume(dev, state, ctx);
3667 if (ret)
3668 DRM_ERROR("Restoring old state failed with %i\n", ret);
3669 } else {
3670 /*
3671 * The display has been reset as well,
3672 * so need a full re-initialization.
3673 */
3674 intel_runtime_pm_disable_interrupts(dev_priv);
3675 intel_runtime_pm_enable_interrupts(dev_priv);
3676
3677 intel_pps_unlock_regs_wa(dev_priv);
3678 intel_modeset_init_hw(dev);
3679
3680 spin_lock_irq(&dev_priv->irq_lock);
3681 if (dev_priv->display.hpd_irq_setup)
3682 dev_priv->display.hpd_irq_setup(dev_priv);
3683 spin_unlock_irq(&dev_priv->irq_lock);
3684
3685 ret = __intel_display_resume(dev, state, ctx);
3686 if (ret)
3687 DRM_ERROR("Restoring old state failed with %i\n", ret);
3688
3689 intel_hpd_init(dev_priv);
3690 }
3691
3692 drm_atomic_state_put(state);
3693 unlock:
3694 drm_modeset_drop_locks(ctx);
3695 drm_modeset_acquire_fini(ctx);
3696 mutex_unlock(&dev->mode_config.mutex);
3697
3698 clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3699 }
3700
3701 static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
3702 const struct intel_crtc_state *new_crtc_state)
3703 {
3704 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
3705 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3706
3707 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3708 crtc->base.mode = new_crtc_state->base.mode;
3709
3710 /*
3711 * Update pipe size and adjust fitter if needed: the reason for this is
3712 * that in compute_mode_changes we check the native mode (not the pfit
3713 * mode) to see if we can flip rather than do a full mode set. In the
3714 * fastboot case, we'll flip, but if we don't update the pipesrc and
3715 * pfit state, we'll end up with a big fb scanned out into the wrong
3716 * sized surface.
3717 */
3718
3719 I915_WRITE(PIPESRC(crtc->pipe),
3720 ((new_crtc_state->pipe_src_w - 1) << 16) |
3721 (new_crtc_state->pipe_src_h - 1));
3722
3723 /* on skylake this is done by detaching scalers */
3724 if (INTEL_GEN(dev_priv) >= 9) {
3725 skl_detach_scalers(crtc);
3726
3727 if (new_crtc_state->pch_pfit.enabled)
3728 skylake_pfit_enable(crtc);
3729 } else if (HAS_PCH_SPLIT(dev_priv)) {
3730 if (new_crtc_state->pch_pfit.enabled)
3731 ironlake_pfit_enable(crtc);
3732 else if (old_crtc_state->pch_pfit.enabled)
3733 ironlake_pfit_disable(crtc, true);
3734 }
3735 }
3736
3737 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3738 {
3739 struct drm_device *dev = crtc->base.dev;
3740 struct drm_i915_private *dev_priv = to_i915(dev);
3741 int pipe = crtc->pipe;
3742 i915_reg_t reg;
3743 u32 temp;
3744
3745 /* enable normal train */
3746 reg = FDI_TX_CTL(pipe);
3747 temp = I915_READ(reg);
3748 if (IS_IVYBRIDGE(dev_priv)) {
3749 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3750 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3751 } else {
3752 temp &= ~FDI_LINK_TRAIN_NONE;
3753 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3754 }
3755 I915_WRITE(reg, temp);
3756
3757 reg = FDI_RX_CTL(pipe);
3758 temp = I915_READ(reg);
3759 if (HAS_PCH_CPT(dev_priv)) {
3760 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3761 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3762 } else {
3763 temp &= ~FDI_LINK_TRAIN_NONE;
3764 temp |= FDI_LINK_TRAIN_NONE;
3765 }
3766 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3767
3768 /* wait one idle pattern time */
3769 POSTING_READ(reg);
3770 udelay(1000);
3771
3772 /* IVB wants error correction enabled */
3773 if (IS_IVYBRIDGE(dev_priv))
3774 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3775 FDI_FE_ERRC_ENABLE);
3776 }
3777
3778 /* The FDI link training functions for ILK/Ibexpeak. */
3779 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3780 const struct intel_crtc_state *crtc_state)
3781 {
3782 struct drm_device *dev = crtc->base.dev;
3783 struct drm_i915_private *dev_priv = to_i915(dev);
3784 int pipe = crtc->pipe;
3785 i915_reg_t reg;
3786 u32 temp, tries;
3787
3788 /* FDI needs bits from pipe first */
3789 assert_pipe_enabled(dev_priv, pipe);
3790
3791 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3792 for train result */
3793 reg = FDI_RX_IMR(pipe);
3794 temp = I915_READ(reg);
3795 temp &= ~FDI_RX_SYMBOL_LOCK;
3796 temp &= ~FDI_RX_BIT_LOCK;
3797 I915_WRITE(reg, temp);
3798 I915_READ(reg);
3799 udelay(150);
3800
3801 /* enable CPU FDI TX and PCH FDI RX */
3802 reg = FDI_TX_CTL(pipe);
3803 temp = I915_READ(reg);
3804 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3805 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3806 temp &= ~FDI_LINK_TRAIN_NONE;
3807 temp |= FDI_LINK_TRAIN_PATTERN_1;
3808 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3809
3810 reg = FDI_RX_CTL(pipe);
3811 temp = I915_READ(reg);
3812 temp &= ~FDI_LINK_TRAIN_NONE;
3813 temp |= FDI_LINK_TRAIN_PATTERN_1;
3814 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3815
3816 POSTING_READ(reg);
3817 udelay(150);
3818
3819 /* Ironlake workaround, enable clock pointer after FDI enable*/
3820 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3821 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3822 FDI_RX_PHASE_SYNC_POINTER_EN);
3823
3824 reg = FDI_RX_IIR(pipe);
3825 for (tries = 0; tries < 5; tries++) {
3826 temp = I915_READ(reg);
3827 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3828
3829 if ((temp & FDI_RX_BIT_LOCK)) {
3830 DRM_DEBUG_KMS("FDI train 1 done.\n");
3831 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3832 break;
3833 }
3834 }
3835 if (tries == 5)
3836 DRM_ERROR("FDI train 1 fail!\n");
3837
3838 /* Train 2 */
3839 reg = FDI_TX_CTL(pipe);
3840 temp = I915_READ(reg);
3841 temp &= ~FDI_LINK_TRAIN_NONE;
3842 temp |= FDI_LINK_TRAIN_PATTERN_2;
3843 I915_WRITE(reg, temp);
3844
3845 reg = FDI_RX_CTL(pipe);
3846 temp = I915_READ(reg);
3847 temp &= ~FDI_LINK_TRAIN_NONE;
3848 temp |= FDI_LINK_TRAIN_PATTERN_2;
3849 I915_WRITE(reg, temp);
3850
3851 POSTING_READ(reg);
3852 udelay(150);
3853
3854 reg = FDI_RX_IIR(pipe);
3855 for (tries = 0; tries < 5; tries++) {
3856 temp = I915_READ(reg);
3857 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3858
3859 if (temp & FDI_RX_SYMBOL_LOCK) {
3860 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3861 DRM_DEBUG_KMS("FDI train 2 done.\n");
3862 break;
3863 }
3864 }
3865 if (tries == 5)
3866 DRM_ERROR("FDI train 2 fail!\n");
3867
3868 DRM_DEBUG_KMS("FDI train done\n");
3869
3870 }
3871
3872 static const int snb_b_fdi_train_param[] = {
3873 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3874 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3875 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3876 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3877 };
3878
3879 /* The FDI link training functions for SNB/Cougarpoint. */
3880 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3881 const struct intel_crtc_state *crtc_state)
3882 {
3883 struct drm_device *dev = crtc->base.dev;
3884 struct drm_i915_private *dev_priv = to_i915(dev);
3885 int pipe = crtc->pipe;
3886 i915_reg_t reg;
3887 u32 temp, i, retry;
3888
3889 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3890 for train result */
3891 reg = FDI_RX_IMR(pipe);
3892 temp = I915_READ(reg);
3893 temp &= ~FDI_RX_SYMBOL_LOCK;
3894 temp &= ~FDI_RX_BIT_LOCK;
3895 I915_WRITE(reg, temp);
3896
3897 POSTING_READ(reg);
3898 udelay(150);
3899
3900 /* enable CPU FDI TX and PCH FDI RX */
3901 reg = FDI_TX_CTL(pipe);
3902 temp = I915_READ(reg);
3903 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3904 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3905 temp &= ~FDI_LINK_TRAIN_NONE;
3906 temp |= FDI_LINK_TRAIN_PATTERN_1;
3907 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3908 /* SNB-B */
3909 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3910 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3911
3912 I915_WRITE(FDI_RX_MISC(pipe),
3913 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3914
3915 reg = FDI_RX_CTL(pipe);
3916 temp = I915_READ(reg);
3917 if (HAS_PCH_CPT(dev_priv)) {
3918 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3919 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3920 } else {
3921 temp &= ~FDI_LINK_TRAIN_NONE;
3922 temp |= FDI_LINK_TRAIN_PATTERN_1;
3923 }
3924 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3925
3926 POSTING_READ(reg);
3927 udelay(150);
3928
3929 for (i = 0; i < 4; i++) {
3930 reg = FDI_TX_CTL(pipe);
3931 temp = I915_READ(reg);
3932 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3933 temp |= snb_b_fdi_train_param[i];
3934 I915_WRITE(reg, temp);
3935
3936 POSTING_READ(reg);
3937 udelay(500);
3938
3939 for (retry = 0; retry < 5; retry++) {
3940 reg = FDI_RX_IIR(pipe);
3941 temp = I915_READ(reg);
3942 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3943 if (temp & FDI_RX_BIT_LOCK) {
3944 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3945 DRM_DEBUG_KMS("FDI train 1 done.\n");
3946 break;
3947 }
3948 udelay(50);
3949 }
3950 if (retry < 5)
3951 break;
3952 }
3953 if (i == 4)
3954 DRM_ERROR("FDI train 1 fail!\n");
3955
3956 /* Train 2 */
3957 reg = FDI_TX_CTL(pipe);
3958 temp = I915_READ(reg);
3959 temp &= ~FDI_LINK_TRAIN_NONE;
3960 temp |= FDI_LINK_TRAIN_PATTERN_2;
3961 if (IS_GEN6(dev_priv)) {
3962 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3963 /* SNB-B */
3964 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3965 }
3966 I915_WRITE(reg, temp);
3967
3968 reg = FDI_RX_CTL(pipe);
3969 temp = I915_READ(reg);
3970 if (HAS_PCH_CPT(dev_priv)) {
3971 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3972 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3973 } else {
3974 temp &= ~FDI_LINK_TRAIN_NONE;
3975 temp |= FDI_LINK_TRAIN_PATTERN_2;
3976 }
3977 I915_WRITE(reg, temp);
3978
3979 POSTING_READ(reg);
3980 udelay(150);
3981
3982 for (i = 0; i < 4; i++) {
3983 reg = FDI_TX_CTL(pipe);
3984 temp = I915_READ(reg);
3985 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3986 temp |= snb_b_fdi_train_param[i];
3987 I915_WRITE(reg, temp);
3988
3989 POSTING_READ(reg);
3990 udelay(500);
3991
3992 for (retry = 0; retry < 5; retry++) {
3993 reg = FDI_RX_IIR(pipe);
3994 temp = I915_READ(reg);
3995 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3996 if (temp & FDI_RX_SYMBOL_LOCK) {
3997 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3998 DRM_DEBUG_KMS("FDI train 2 done.\n");
3999 break;
4000 }
4001 udelay(50);
4002 }
4003 if (retry < 5)
4004 break;
4005 }
4006 if (i == 4)
4007 DRM_ERROR("FDI train 2 fail!\n");
4008
4009 DRM_DEBUG_KMS("FDI train done.\n");
4010 }
4011
4012 /* Manual link training for Ivy Bridge A0 parts */
4013 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4014 const struct intel_crtc_state *crtc_state)
4015 {
4016 struct drm_device *dev = crtc->base.dev;
4017 struct drm_i915_private *dev_priv = to_i915(dev);
4018 int pipe = crtc->pipe;
4019 i915_reg_t reg;
4020 u32 temp, i, j;
4021
4022 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4023 for train result */
4024 reg = FDI_RX_IMR(pipe);
4025 temp = I915_READ(reg);
4026 temp &= ~FDI_RX_SYMBOL_LOCK;
4027 temp &= ~FDI_RX_BIT_LOCK;
4028 I915_WRITE(reg, temp);
4029
4030 POSTING_READ(reg);
4031 udelay(150);
4032
4033 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4034 I915_READ(FDI_RX_IIR(pipe)));
4035
4036 /* Try each vswing and preemphasis setting twice before moving on */
4037 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4038 /* disable first in case we need to retry */
4039 reg = FDI_TX_CTL(pipe);
4040 temp = I915_READ(reg);
4041 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4042 temp &= ~FDI_TX_ENABLE;
4043 I915_WRITE(reg, temp);
4044
4045 reg = FDI_RX_CTL(pipe);
4046 temp = I915_READ(reg);
4047 temp &= ~FDI_LINK_TRAIN_AUTO;
4048 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4049 temp &= ~FDI_RX_ENABLE;
4050 I915_WRITE(reg, temp);
4051
4052 /* enable CPU FDI TX and PCH FDI RX */
4053 reg = FDI_TX_CTL(pipe);
4054 temp = I915_READ(reg);
4055 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4056 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4057 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4058 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4059 temp |= snb_b_fdi_train_param[j/2];
4060 temp |= FDI_COMPOSITE_SYNC;
4061 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4062
4063 I915_WRITE(FDI_RX_MISC(pipe),
4064 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4065
4066 reg = FDI_RX_CTL(pipe);
4067 temp = I915_READ(reg);
4068 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4069 temp |= FDI_COMPOSITE_SYNC;
4070 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4071
4072 POSTING_READ(reg);
4073 udelay(1); /* should be 0.5us */
4074
4075 for (i = 0; i < 4; i++) {
4076 reg = FDI_RX_IIR(pipe);
4077 temp = I915_READ(reg);
4078 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4079
4080 if (temp & FDI_RX_BIT_LOCK ||
4081 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4082 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4083 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4084 i);
4085 break;
4086 }
4087 udelay(1); /* should be 0.5us */
4088 }
4089 if (i == 4) {
4090 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4091 continue;
4092 }
4093
4094 /* Train 2 */
4095 reg = FDI_TX_CTL(pipe);
4096 temp = I915_READ(reg);
4097 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4098 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4099 I915_WRITE(reg, temp);
4100
4101 reg = FDI_RX_CTL(pipe);
4102 temp = I915_READ(reg);
4103 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4104 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4105 I915_WRITE(reg, temp);
4106
4107 POSTING_READ(reg);
4108 udelay(2); /* should be 1.5us */
4109
4110 for (i = 0; i < 4; i++) {
4111 reg = FDI_RX_IIR(pipe);
4112 temp = I915_READ(reg);
4113 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4114
4115 if (temp & FDI_RX_SYMBOL_LOCK ||
4116 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4117 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4118 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4119 i);
4120 goto train_done;
4121 }
4122 udelay(2); /* should be 1.5us */
4123 }
4124 if (i == 4)
4125 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4126 }
4127
4128 train_done:
4129 DRM_DEBUG_KMS("FDI train done.\n");
4130 }
4131
4132 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4133 {
4134 struct drm_device *dev = intel_crtc->base.dev;
4135 struct drm_i915_private *dev_priv = to_i915(dev);
4136 int pipe = intel_crtc->pipe;
4137 i915_reg_t reg;
4138 u32 temp;
4139
4140 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4141 reg = FDI_RX_CTL(pipe);
4142 temp = I915_READ(reg);
4143 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4144 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4145 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4146 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4147
4148 POSTING_READ(reg);
4149 udelay(200);
4150
4151 /* Switch from Rawclk to PCDclk */
4152 temp = I915_READ(reg);
4153 I915_WRITE(reg, temp | FDI_PCDCLK);
4154
4155 POSTING_READ(reg);
4156 udelay(200);
4157
4158 /* Enable CPU FDI TX PLL, always on for Ironlake */
4159 reg = FDI_TX_CTL(pipe);
4160 temp = I915_READ(reg);
4161 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4162 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4163
4164 POSTING_READ(reg);
4165 udelay(100);
4166 }
4167 }
4168
4169 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4170 {
4171 struct drm_device *dev = intel_crtc->base.dev;
4172 struct drm_i915_private *dev_priv = to_i915(dev);
4173 int pipe = intel_crtc->pipe;
4174 i915_reg_t reg;
4175 u32 temp;
4176
4177 /* Switch from PCDclk to Rawclk */
4178 reg = FDI_RX_CTL(pipe);
4179 temp = I915_READ(reg);
4180 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4181
4182 /* Disable CPU FDI TX PLL */
4183 reg = FDI_TX_CTL(pipe);
4184 temp = I915_READ(reg);
4185 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4186
4187 POSTING_READ(reg);
4188 udelay(100);
4189
4190 reg = FDI_RX_CTL(pipe);
4191 temp = I915_READ(reg);
4192 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4193
4194 /* Wait for the clocks to turn off. */
4195 POSTING_READ(reg);
4196 udelay(100);
4197 }
4198
4199 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4200 {
4201 struct drm_device *dev = crtc->dev;
4202 struct drm_i915_private *dev_priv = to_i915(dev);
4203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4204 int pipe = intel_crtc->pipe;
4205 i915_reg_t reg;
4206 u32 temp;
4207
4208 /* disable CPU FDI tx and PCH FDI rx */
4209 reg = FDI_TX_CTL(pipe);
4210 temp = I915_READ(reg);
4211 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4212 POSTING_READ(reg);
4213
4214 reg = FDI_RX_CTL(pipe);
4215 temp = I915_READ(reg);
4216 temp &= ~(0x7 << 16);
4217 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4218 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4219
4220 POSTING_READ(reg);
4221 udelay(100);
4222
4223 /* Ironlake workaround, disable clock pointer after downing FDI */
4224 if (HAS_PCH_IBX(dev_priv))
4225 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4226
4227 /* still set train pattern 1 */
4228 reg = FDI_TX_CTL(pipe);
4229 temp = I915_READ(reg);
4230 temp &= ~FDI_LINK_TRAIN_NONE;
4231 temp |= FDI_LINK_TRAIN_PATTERN_1;
4232 I915_WRITE(reg, temp);
4233
4234 reg = FDI_RX_CTL(pipe);
4235 temp = I915_READ(reg);
4236 if (HAS_PCH_CPT(dev_priv)) {
4237 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4238 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4239 } else {
4240 temp &= ~FDI_LINK_TRAIN_NONE;
4241 temp |= FDI_LINK_TRAIN_PATTERN_1;
4242 }
4243 /* BPC in FDI rx is consistent with that in PIPECONF */
4244 temp &= ~(0x07 << 16);
4245 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4246 I915_WRITE(reg, temp);
4247
4248 POSTING_READ(reg);
4249 udelay(100);
4250 }
4251
4252 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4253 {
4254 struct drm_crtc *crtc;
4255 bool cleanup_done;
4256
4257 drm_for_each_crtc(crtc, &dev_priv->drm) {
4258 struct drm_crtc_commit *commit;
4259 spin_lock(&crtc->commit_lock);
4260 commit = list_first_entry_or_null(&crtc->commit_list,
4261 struct drm_crtc_commit, commit_entry);
4262 cleanup_done = commit ?
4263 try_wait_for_completion(&commit->cleanup_done) : true;
4264 spin_unlock(&crtc->commit_lock);
4265
4266 if (cleanup_done)
4267 continue;
4268
4269 drm_crtc_wait_one_vblank(crtc);
4270
4271 return true;
4272 }
4273
4274 return false;
4275 }
4276
4277 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4278 {
4279 u32 temp;
4280
4281 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4282
4283 mutex_lock(&dev_priv->sb_lock);
4284
4285 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4286 temp |= SBI_SSCCTL_DISABLE;
4287 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4288
4289 mutex_unlock(&dev_priv->sb_lock);
4290 }
4291
4292 /* Program iCLKIP clock to the desired frequency */
4293 static void lpt_program_iclkip(struct intel_crtc *crtc)
4294 {
4295 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4296 int clock = crtc->config->base.adjusted_mode.crtc_clock;
4297 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4298 u32 temp;
4299
4300 lpt_disable_iclkip(dev_priv);
4301
4302 /* The iCLK virtual clock root frequency is in MHz,
4303 * but the adjusted_mode->crtc_clock in in KHz. To get the
4304 * divisors, it is necessary to divide one by another, so we
4305 * convert the virtual clock precision to KHz here for higher
4306 * precision.
4307 */
4308 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4309 u32 iclk_virtual_root_freq = 172800 * 1000;
4310 u32 iclk_pi_range = 64;
4311 u32 desired_divisor;
4312
4313 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4314 clock << auxdiv);
4315 divsel = (desired_divisor / iclk_pi_range) - 2;
4316 phaseinc = desired_divisor % iclk_pi_range;
4317
4318 /*
4319 * Near 20MHz is a corner case which is
4320 * out of range for the 7-bit divisor
4321 */
4322 if (divsel <= 0x7f)
4323 break;
4324 }
4325
4326 /* This should not happen with any sane values */
4327 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4328 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4329 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4330 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4331
4332 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4333 clock,
4334 auxdiv,
4335 divsel,
4336 phasedir,
4337 phaseinc);
4338
4339 mutex_lock(&dev_priv->sb_lock);
4340
4341 /* Program SSCDIVINTPHASE6 */
4342 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4343 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4344 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4345 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4346 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4347 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4348 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4349 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4350
4351 /* Program SSCAUXDIV */
4352 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4353 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4354 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4355 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4356
4357 /* Enable modulator and associated divider */
4358 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4359 temp &= ~SBI_SSCCTL_DISABLE;
4360 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4361
4362 mutex_unlock(&dev_priv->sb_lock);
4363
4364 /* Wait for initialization time */
4365 udelay(24);
4366
4367 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4368 }
4369
4370 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4371 {
4372 u32 divsel, phaseinc, auxdiv;
4373 u32 iclk_virtual_root_freq = 172800 * 1000;
4374 u32 iclk_pi_range = 64;
4375 u32 desired_divisor;
4376 u32 temp;
4377
4378 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4379 return 0;
4380
4381 mutex_lock(&dev_priv->sb_lock);
4382
4383 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4384 if (temp & SBI_SSCCTL_DISABLE) {
4385 mutex_unlock(&dev_priv->sb_lock);
4386 return 0;
4387 }
4388
4389 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4390 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4391 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4392 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4393 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4394
4395 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4396 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4397 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4398
4399 mutex_unlock(&dev_priv->sb_lock);
4400
4401 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4402
4403 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4404 desired_divisor << auxdiv);
4405 }
4406
4407 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4408 enum pipe pch_transcoder)
4409 {
4410 struct drm_device *dev = crtc->base.dev;
4411 struct drm_i915_private *dev_priv = to_i915(dev);
4412 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4413
4414 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4415 I915_READ(HTOTAL(cpu_transcoder)));
4416 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4417 I915_READ(HBLANK(cpu_transcoder)));
4418 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4419 I915_READ(HSYNC(cpu_transcoder)));
4420
4421 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4422 I915_READ(VTOTAL(cpu_transcoder)));
4423 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4424 I915_READ(VBLANK(cpu_transcoder)));
4425 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4426 I915_READ(VSYNC(cpu_transcoder)));
4427 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4428 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4429 }
4430
4431 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4432 {
4433 struct drm_i915_private *dev_priv = to_i915(dev);
4434 uint32_t temp;
4435
4436 temp = I915_READ(SOUTH_CHICKEN1);
4437 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4438 return;
4439
4440 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4441 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4442
4443 temp &= ~FDI_BC_BIFURCATION_SELECT;
4444 if (enable)
4445 temp |= FDI_BC_BIFURCATION_SELECT;
4446
4447 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4448 I915_WRITE(SOUTH_CHICKEN1, temp);
4449 POSTING_READ(SOUTH_CHICKEN1);
4450 }
4451
4452 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4453 {
4454 struct drm_device *dev = intel_crtc->base.dev;
4455
4456 switch (intel_crtc->pipe) {
4457 case PIPE_A:
4458 break;
4459 case PIPE_B:
4460 if (intel_crtc->config->fdi_lanes > 2)
4461 cpt_set_fdi_bc_bifurcation(dev, false);
4462 else
4463 cpt_set_fdi_bc_bifurcation(dev, true);
4464
4465 break;
4466 case PIPE_C:
4467 cpt_set_fdi_bc_bifurcation(dev, true);
4468
4469 break;
4470 default:
4471 BUG();
4472 }
4473 }
4474
4475 /* Return which DP Port should be selected for Transcoder DP control */
4476 static enum port
4477 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4478 {
4479 struct drm_device *dev = crtc->base.dev;
4480 struct intel_encoder *encoder;
4481
4482 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4483 if (encoder->type == INTEL_OUTPUT_DP ||
4484 encoder->type == INTEL_OUTPUT_EDP)
4485 return enc_to_dig_port(&encoder->base)->port;
4486 }
4487
4488 return -1;
4489 }
4490
4491 /*
4492 * Enable PCH resources required for PCH ports:
4493 * - PCH PLLs
4494 * - FDI training & RX/TX
4495 * - update transcoder timings
4496 * - DP transcoding bits
4497 * - transcoder
4498 */
4499 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4500 {
4501 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4502 struct drm_device *dev = crtc->base.dev;
4503 struct drm_i915_private *dev_priv = to_i915(dev);
4504 int pipe = crtc->pipe;
4505 u32 temp;
4506
4507 assert_pch_transcoder_disabled(dev_priv, pipe);
4508
4509 if (IS_IVYBRIDGE(dev_priv))
4510 ivybridge_update_fdi_bc_bifurcation(crtc);
4511
4512 /* Write the TU size bits before fdi link training, so that error
4513 * detection works. */
4514 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4515 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4516
4517 /* For PCH output, training FDI link */
4518 dev_priv->display.fdi_link_train(crtc, crtc_state);
4519
4520 /* We need to program the right clock selection before writing the pixel
4521 * mutliplier into the DPLL. */
4522 if (HAS_PCH_CPT(dev_priv)) {
4523 u32 sel;
4524
4525 temp = I915_READ(PCH_DPLL_SEL);
4526 temp |= TRANS_DPLL_ENABLE(pipe);
4527 sel = TRANS_DPLLB_SEL(pipe);
4528 if (crtc_state->shared_dpll ==
4529 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4530 temp |= sel;
4531 else
4532 temp &= ~sel;
4533 I915_WRITE(PCH_DPLL_SEL, temp);
4534 }
4535
4536 /* XXX: pch pll's can be enabled any time before we enable the PCH
4537 * transcoder, and we actually should do this to not upset any PCH
4538 * transcoder that already use the clock when we share it.
4539 *
4540 * Note that enable_shared_dpll tries to do the right thing, but
4541 * get_shared_dpll unconditionally resets the pll - we need that to have
4542 * the right LVDS enable sequence. */
4543 intel_enable_shared_dpll(crtc);
4544
4545 /* set transcoder timing, panel must allow it */
4546 assert_panel_unlocked(dev_priv, pipe);
4547 ironlake_pch_transcoder_set_timings(crtc, pipe);
4548
4549 intel_fdi_normal_train(crtc);
4550
4551 /* For PCH DP, enable TRANS_DP_CTL */
4552 if (HAS_PCH_CPT(dev_priv) &&
4553 intel_crtc_has_dp_encoder(crtc_state)) {
4554 const struct drm_display_mode *adjusted_mode =
4555 &crtc_state->base.adjusted_mode;
4556 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4557 i915_reg_t reg = TRANS_DP_CTL(pipe);
4558 temp = I915_READ(reg);
4559 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4560 TRANS_DP_SYNC_MASK |
4561 TRANS_DP_BPC_MASK);
4562 temp |= TRANS_DP_OUTPUT_ENABLE;
4563 temp |= bpc << 9; /* same format but at 11:9 */
4564
4565 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4566 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4567 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4568 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4569
4570 switch (intel_trans_dp_port_sel(crtc)) {
4571 case PORT_B:
4572 temp |= TRANS_DP_PORT_SEL_B;
4573 break;
4574 case PORT_C:
4575 temp |= TRANS_DP_PORT_SEL_C;
4576 break;
4577 case PORT_D:
4578 temp |= TRANS_DP_PORT_SEL_D;
4579 break;
4580 default:
4581 BUG();
4582 }
4583
4584 I915_WRITE(reg, temp);
4585 }
4586
4587 ironlake_enable_pch_transcoder(dev_priv, pipe);
4588 }
4589
4590 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4591 {
4592 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4593 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4594 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4595
4596 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4597
4598 lpt_program_iclkip(crtc);
4599
4600 /* Set transcoder timing. */
4601 ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4602
4603 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4604 }
4605
4606 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4607 {
4608 struct drm_i915_private *dev_priv = to_i915(dev);
4609 i915_reg_t dslreg = PIPEDSL(pipe);
4610 u32 temp;
4611
4612 temp = I915_READ(dslreg);
4613 udelay(500);
4614 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4615 if (wait_for(I915_READ(dslreg) != temp, 5))
4616 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4617 }
4618 }
4619
4620 static int
4621 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4622 unsigned int scaler_user, int *scaler_id,
4623 int src_w, int src_h, int dst_w, int dst_h)
4624 {
4625 struct intel_crtc_scaler_state *scaler_state =
4626 &crtc_state->scaler_state;
4627 struct intel_crtc *intel_crtc =
4628 to_intel_crtc(crtc_state->base.crtc);
4629 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4630 const struct drm_display_mode *adjusted_mode =
4631 &crtc_state->base.adjusted_mode;
4632 int need_scaling;
4633
4634 /*
4635 * Src coordinates are already rotated by 270 degrees for
4636 * the 90/270 degree plane rotation cases (to match the
4637 * GTT mapping), hence no need to account for rotation here.
4638 */
4639 need_scaling = src_w != dst_w || src_h != dst_h;
4640
4641 if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
4642 need_scaling = true;
4643
4644 /*
4645 * Scaling/fitting not supported in IF-ID mode in GEN9+
4646 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4647 * Once NV12 is enabled, handle it here while allocating scaler
4648 * for NV12.
4649 */
4650 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
4651 need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4652 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4653 return -EINVAL;
4654 }
4655
4656 /*
4657 * if plane is being disabled or scaler is no more required or force detach
4658 * - free scaler binded to this plane/crtc
4659 * - in order to do this, update crtc->scaler_usage
4660 *
4661 * Here scaler state in crtc_state is set free so that
4662 * scaler can be assigned to other user. Actual register
4663 * update to free the scaler is done in plane/panel-fit programming.
4664 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4665 */
4666 if (force_detach || !need_scaling) {
4667 if (*scaler_id >= 0) {
4668 scaler_state->scaler_users &= ~(1 << scaler_user);
4669 scaler_state->scalers[*scaler_id].in_use = 0;
4670
4671 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4672 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4673 intel_crtc->pipe, scaler_user, *scaler_id,
4674 scaler_state->scaler_users);
4675 *scaler_id = -1;
4676 }
4677 return 0;
4678 }
4679
4680 /* range checks */
4681 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4682 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4683
4684 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4685 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4686 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4687 "size is out of scaler range\n",
4688 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4689 return -EINVAL;
4690 }
4691
4692 /* mark this plane as a scaler user in crtc_state */
4693 scaler_state->scaler_users |= (1 << scaler_user);
4694 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4695 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4696 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4697 scaler_state->scaler_users);
4698
4699 return 0;
4700 }
4701
4702 /**
4703 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4704 *
4705 * @state: crtc's scaler state
4706 *
4707 * Return
4708 * 0 - scaler_usage updated successfully
4709 * error - requested scaling cannot be supported or other error condition
4710 */
4711 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4712 {
4713 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4714
4715 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4716 &state->scaler_state.scaler_id,
4717 state->pipe_src_w, state->pipe_src_h,
4718 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4719 }
4720
4721 /**
4722 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4723 *
4724 * @state: crtc's scaler state
4725 * @plane_state: atomic plane state to update
4726 *
4727 * Return
4728 * 0 - scaler_usage updated successfully
4729 * error - requested scaling cannot be supported or other error condition
4730 */
4731 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4732 struct intel_plane_state *plane_state)
4733 {
4734
4735 struct intel_plane *intel_plane =
4736 to_intel_plane(plane_state->base.plane);
4737 struct drm_framebuffer *fb = plane_state->base.fb;
4738 int ret;
4739
4740 bool force_detach = !fb || !plane_state->base.visible;
4741
4742 ret = skl_update_scaler(crtc_state, force_detach,
4743 drm_plane_index(&intel_plane->base),
4744 &plane_state->scaler_id,
4745 drm_rect_width(&plane_state->base.src) >> 16,
4746 drm_rect_height(&plane_state->base.src) >> 16,
4747 drm_rect_width(&plane_state->base.dst),
4748 drm_rect_height(&plane_state->base.dst));
4749
4750 if (ret || plane_state->scaler_id < 0)
4751 return ret;
4752
4753 /* check colorkey */
4754 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4755 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4756 intel_plane->base.base.id,
4757 intel_plane->base.name);
4758 return -EINVAL;
4759 }
4760
4761 /* Check src format */
4762 switch (fb->format->format) {
4763 case DRM_FORMAT_RGB565:
4764 case DRM_FORMAT_XBGR8888:
4765 case DRM_FORMAT_XRGB8888:
4766 case DRM_FORMAT_ABGR8888:
4767 case DRM_FORMAT_ARGB8888:
4768 case DRM_FORMAT_XRGB2101010:
4769 case DRM_FORMAT_XBGR2101010:
4770 case DRM_FORMAT_YUYV:
4771 case DRM_FORMAT_YVYU:
4772 case DRM_FORMAT_UYVY:
4773 case DRM_FORMAT_VYUY:
4774 break;
4775 default:
4776 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4777 intel_plane->base.base.id, intel_plane->base.name,
4778 fb->base.id, fb->format->format);
4779 return -EINVAL;
4780 }
4781
4782 return 0;
4783 }
4784
4785 static void skylake_scaler_disable(struct intel_crtc *crtc)
4786 {
4787 int i;
4788
4789 for (i = 0; i < crtc->num_scalers; i++)
4790 skl_detach_scaler(crtc, i);
4791 }
4792
4793 static void skylake_pfit_enable(struct intel_crtc *crtc)
4794 {
4795 struct drm_device *dev = crtc->base.dev;
4796 struct drm_i915_private *dev_priv = to_i915(dev);
4797 int pipe = crtc->pipe;
4798 struct intel_crtc_scaler_state *scaler_state =
4799 &crtc->config->scaler_state;
4800
4801 if (crtc->config->pch_pfit.enabled) {
4802 int id;
4803
4804 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4805 return;
4806
4807 id = scaler_state->scaler_id;
4808 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4809 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4810 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4811 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4812 }
4813 }
4814
4815 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4816 {
4817 struct drm_device *dev = crtc->base.dev;
4818 struct drm_i915_private *dev_priv = to_i915(dev);
4819 int pipe = crtc->pipe;
4820
4821 if (crtc->config->pch_pfit.enabled) {
4822 /* Force use of hard-coded filter coefficients
4823 * as some pre-programmed values are broken,
4824 * e.g. x201.
4825 */
4826 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4827 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4828 PF_PIPE_SEL_IVB(pipe));
4829 else
4830 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4831 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4832 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4833 }
4834 }
4835
4836 void hsw_enable_ips(struct intel_crtc *crtc)
4837 {
4838 struct drm_device *dev = crtc->base.dev;
4839 struct drm_i915_private *dev_priv = to_i915(dev);
4840
4841 if (!crtc->config->ips_enabled)
4842 return;
4843
4844 /*
4845 * We can only enable IPS after we enable a plane and wait for a vblank
4846 * This function is called from post_plane_update, which is run after
4847 * a vblank wait.
4848 */
4849
4850 assert_plane_enabled(dev_priv, crtc->plane);
4851 if (IS_BROADWELL(dev_priv)) {
4852 mutex_lock(&dev_priv->pcu_lock);
4853 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
4854 IPS_ENABLE | IPS_PCODE_CONTROL));
4855 mutex_unlock(&dev_priv->pcu_lock);
4856 /* Quoting Art Runyan: "its not safe to expect any particular
4857 * value in IPS_CTL bit 31 after enabling IPS through the
4858 * mailbox." Moreover, the mailbox may return a bogus state,
4859 * so we need to just enable it and continue on.
4860 */
4861 } else {
4862 I915_WRITE(IPS_CTL, IPS_ENABLE);
4863 /* The bit only becomes 1 in the next vblank, so this wait here
4864 * is essentially intel_wait_for_vblank. If we don't have this
4865 * and don't wait for vblanks until the end of crtc_enable, then
4866 * the HW state readout code will complain that the expected
4867 * IPS_CTL value is not the one we read. */
4868 if (intel_wait_for_register(dev_priv,
4869 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4870 50))
4871 DRM_ERROR("Timed out waiting for IPS enable\n");
4872 }
4873 }
4874
4875 void hsw_disable_ips(struct intel_crtc *crtc)
4876 {
4877 struct drm_device *dev = crtc->base.dev;
4878 struct drm_i915_private *dev_priv = to_i915(dev);
4879
4880 if (!crtc->config->ips_enabled)
4881 return;
4882
4883 assert_plane_enabled(dev_priv, crtc->plane);
4884 if (IS_BROADWELL(dev_priv)) {
4885 mutex_lock(&dev_priv->pcu_lock);
4886 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4887 mutex_unlock(&dev_priv->pcu_lock);
4888 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4889 if (intel_wait_for_register(dev_priv,
4890 IPS_CTL, IPS_ENABLE, 0,
4891 42))
4892 DRM_ERROR("Timed out waiting for IPS disable\n");
4893 } else {
4894 I915_WRITE(IPS_CTL, 0);
4895 POSTING_READ(IPS_CTL);
4896 }
4897
4898 /* We need to wait for a vblank before we can disable the plane. */
4899 intel_wait_for_vblank(dev_priv, crtc->pipe);
4900 }
4901
4902 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4903 {
4904 if (intel_crtc->overlay) {
4905 struct drm_device *dev = intel_crtc->base.dev;
4906
4907 mutex_lock(&dev->struct_mutex);
4908 (void) intel_overlay_switch_off(intel_crtc->overlay);
4909 mutex_unlock(&dev->struct_mutex);
4910 }
4911
4912 /* Let userspace switch the overlay on again. In most cases userspace
4913 * has to recompute where to put it anyway.
4914 */
4915 }
4916
4917 /**
4918 * intel_post_enable_primary - Perform operations after enabling primary plane
4919 * @crtc: the CRTC whose primary plane was just enabled
4920 *
4921 * Performs potentially sleeping operations that must be done after the primary
4922 * plane is enabled, such as updating FBC and IPS. Note that this may be
4923 * called due to an explicit primary plane update, or due to an implicit
4924 * re-enable that is caused when a sprite plane is updated to no longer
4925 * completely hide the primary plane.
4926 */
4927 static void
4928 intel_post_enable_primary(struct drm_crtc *crtc)
4929 {
4930 struct drm_device *dev = crtc->dev;
4931 struct drm_i915_private *dev_priv = to_i915(dev);
4932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4933 int pipe = intel_crtc->pipe;
4934
4935 /*
4936 * FIXME IPS should be fine as long as one plane is
4937 * enabled, but in practice it seems to have problems
4938 * when going from primary only to sprite only and vice
4939 * versa.
4940 */
4941 hsw_enable_ips(intel_crtc);
4942
4943 /*
4944 * Gen2 reports pipe underruns whenever all planes are disabled.
4945 * So don't enable underrun reporting before at least some planes
4946 * are enabled.
4947 * FIXME: Need to fix the logic to work when we turn off all planes
4948 * but leave the pipe running.
4949 */
4950 if (IS_GEN2(dev_priv))
4951 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4952
4953 /* Underruns don't always raise interrupts, so check manually. */
4954 intel_check_cpu_fifo_underruns(dev_priv);
4955 intel_check_pch_fifo_underruns(dev_priv);
4956 }
4957
4958 /* FIXME move all this to pre_plane_update() with proper state tracking */
4959 static void
4960 intel_pre_disable_primary(struct drm_crtc *crtc)
4961 {
4962 struct drm_device *dev = crtc->dev;
4963 struct drm_i915_private *dev_priv = to_i915(dev);
4964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4965 int pipe = intel_crtc->pipe;
4966
4967 /*
4968 * Gen2 reports pipe underruns whenever all planes are disabled.
4969 * So diasble underrun reporting before all the planes get disabled.
4970 * FIXME: Need to fix the logic to work when we turn off all planes
4971 * but leave the pipe running.
4972 */
4973 if (IS_GEN2(dev_priv))
4974 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4975
4976 /*
4977 * FIXME IPS should be fine as long as one plane is
4978 * enabled, but in practice it seems to have problems
4979 * when going from primary only to sprite only and vice
4980 * versa.
4981 */
4982 hsw_disable_ips(intel_crtc);
4983 }
4984
4985 /* FIXME get rid of this and use pre_plane_update */
4986 static void
4987 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4988 {
4989 struct drm_device *dev = crtc->dev;
4990 struct drm_i915_private *dev_priv = to_i915(dev);
4991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4992 int pipe = intel_crtc->pipe;
4993
4994 intel_pre_disable_primary(crtc);
4995
4996 /*
4997 * Vblank time updates from the shadow to live plane control register
4998 * are blocked if the memory self-refresh mode is active at that
4999 * moment. So to make sure the plane gets truly disabled, disable
5000 * first the self-refresh mode. The self-refresh enable bit in turn
5001 * will be checked/applied by the HW only at the next frame start
5002 * event which is after the vblank start event, so we need to have a
5003 * wait-for-vblank between disabling the plane and the pipe.
5004 */
5005 if (HAS_GMCH_DISPLAY(dev_priv) &&
5006 intel_set_memory_cxsr(dev_priv, false))
5007 intel_wait_for_vblank(dev_priv, pipe);
5008 }
5009
5010 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5011 {
5012 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5013 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5014 struct intel_crtc_state *pipe_config =
5015 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
5016 crtc);
5017 struct drm_plane *primary = crtc->base.primary;
5018 struct drm_plane_state *old_pri_state =
5019 drm_atomic_get_existing_plane_state(old_state, primary);
5020
5021 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5022
5023 if (pipe_config->update_wm_post && pipe_config->base.active)
5024 intel_update_watermarks(crtc);
5025
5026 if (old_pri_state) {
5027 struct intel_plane_state *primary_state =
5028 intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state),
5029 to_intel_plane(primary));
5030 struct intel_plane_state *old_primary_state =
5031 to_intel_plane_state(old_pri_state);
5032
5033 intel_fbc_post_update(crtc);
5034
5035 if (primary_state->base.visible &&
5036 (needs_modeset(&pipe_config->base) ||
5037 !old_primary_state->base.visible))
5038 intel_post_enable_primary(&crtc->base);
5039 }
5040 }
5041
5042 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5043 struct intel_crtc_state *pipe_config)
5044 {
5045 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5046 struct drm_device *dev = crtc->base.dev;
5047 struct drm_i915_private *dev_priv = to_i915(dev);
5048 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5049 struct drm_plane *primary = crtc->base.primary;
5050 struct drm_plane_state *old_pri_state =
5051 drm_atomic_get_existing_plane_state(old_state, primary);
5052 bool modeset = needs_modeset(&pipe_config->base);
5053 struct intel_atomic_state *old_intel_state =
5054 to_intel_atomic_state(old_state);
5055
5056 if (old_pri_state) {
5057 struct intel_plane_state *primary_state =
5058 intel_atomic_get_new_plane_state(old_intel_state,
5059 to_intel_plane(primary));
5060 struct intel_plane_state *old_primary_state =
5061 to_intel_plane_state(old_pri_state);
5062
5063 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5064
5065 if (old_primary_state->base.visible &&
5066 (modeset || !primary_state->base.visible))
5067 intel_pre_disable_primary(&crtc->base);
5068 }
5069
5070 /*
5071 * Vblank time updates from the shadow to live plane control register
5072 * are blocked if the memory self-refresh mode is active at that
5073 * moment. So to make sure the plane gets truly disabled, disable
5074 * first the self-refresh mode. The self-refresh enable bit in turn
5075 * will be checked/applied by the HW only at the next frame start
5076 * event which is after the vblank start event, so we need to have a
5077 * wait-for-vblank between disabling the plane and the pipe.
5078 */
5079 if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5080 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5081 intel_wait_for_vblank(dev_priv, crtc->pipe);
5082
5083 /*
5084 * IVB workaround: must disable low power watermarks for at least
5085 * one frame before enabling scaling. LP watermarks can be re-enabled
5086 * when scaling is disabled.
5087 *
5088 * WaCxSRDisabledForSpriteScaling:ivb
5089 */
5090 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5091 intel_wait_for_vblank(dev_priv, crtc->pipe);
5092
5093 /*
5094 * If we're doing a modeset, we're done. No need to do any pre-vblank
5095 * watermark programming here.
5096 */
5097 if (needs_modeset(&pipe_config->base))
5098 return;
5099
5100 /*
5101 * For platforms that support atomic watermarks, program the
5102 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5103 * will be the intermediate values that are safe for both pre- and
5104 * post- vblank; when vblank happens, the 'active' values will be set
5105 * to the final 'target' values and we'll do this again to get the
5106 * optimal watermarks. For gen9+ platforms, the values we program here
5107 * will be the final target values which will get automatically latched
5108 * at vblank time; no further programming will be necessary.
5109 *
5110 * If a platform hasn't been transitioned to atomic watermarks yet,
5111 * we'll continue to update watermarks the old way, if flags tell
5112 * us to.
5113 */
5114 if (dev_priv->display.initial_watermarks != NULL)
5115 dev_priv->display.initial_watermarks(old_intel_state,
5116 pipe_config);
5117 else if (pipe_config->update_wm_pre)
5118 intel_update_watermarks(crtc);
5119 }
5120
5121 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5122 {
5123 struct drm_device *dev = crtc->dev;
5124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5125 struct drm_plane *p;
5126 int pipe = intel_crtc->pipe;
5127
5128 intel_crtc_dpms_overlay_disable(intel_crtc);
5129
5130 drm_for_each_plane_mask(p, dev, plane_mask)
5131 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
5132
5133 /*
5134 * FIXME: Once we grow proper nuclear flip support out of this we need
5135 * to compute the mask of flip planes precisely. For the time being
5136 * consider this a flip to a NULL plane.
5137 */
5138 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5139 }
5140
5141 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5142 struct intel_crtc_state *crtc_state,
5143 struct drm_atomic_state *old_state)
5144 {
5145 struct drm_connector_state *conn_state;
5146 struct drm_connector *conn;
5147 int i;
5148
5149 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5150 struct intel_encoder *encoder =
5151 to_intel_encoder(conn_state->best_encoder);
5152
5153 if (conn_state->crtc != crtc)
5154 continue;
5155
5156 if (encoder->pre_pll_enable)
5157 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5158 }
5159 }
5160
5161 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5162 struct intel_crtc_state *crtc_state,
5163 struct drm_atomic_state *old_state)
5164 {
5165 struct drm_connector_state *conn_state;
5166 struct drm_connector *conn;
5167 int i;
5168
5169 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5170 struct intel_encoder *encoder =
5171 to_intel_encoder(conn_state->best_encoder);
5172
5173 if (conn_state->crtc != crtc)
5174 continue;
5175
5176 if (encoder->pre_enable)
5177 encoder->pre_enable(encoder, crtc_state, conn_state);
5178 }
5179 }
5180
5181 static void intel_encoders_enable(struct drm_crtc *crtc,
5182 struct intel_crtc_state *crtc_state,
5183 struct drm_atomic_state *old_state)
5184 {
5185 struct drm_connector_state *conn_state;
5186 struct drm_connector *conn;
5187 int i;
5188
5189 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5190 struct intel_encoder *encoder =
5191 to_intel_encoder(conn_state->best_encoder);
5192
5193 if (conn_state->crtc != crtc)
5194 continue;
5195
5196 encoder->enable(encoder, crtc_state, conn_state);
5197 intel_opregion_notify_encoder(encoder, true);
5198 }
5199 }
5200
5201 static void intel_encoders_disable(struct drm_crtc *crtc,
5202 struct intel_crtc_state *old_crtc_state,
5203 struct drm_atomic_state *old_state)
5204 {
5205 struct drm_connector_state *old_conn_state;
5206 struct drm_connector *conn;
5207 int i;
5208
5209 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5210 struct intel_encoder *encoder =
5211 to_intel_encoder(old_conn_state->best_encoder);
5212
5213 if (old_conn_state->crtc != crtc)
5214 continue;
5215
5216 intel_opregion_notify_encoder(encoder, false);
5217 encoder->disable(encoder, old_crtc_state, old_conn_state);
5218 }
5219 }
5220
5221 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5222 struct intel_crtc_state *old_crtc_state,
5223 struct drm_atomic_state *old_state)
5224 {
5225 struct drm_connector_state *old_conn_state;
5226 struct drm_connector *conn;
5227 int i;
5228
5229 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5230 struct intel_encoder *encoder =
5231 to_intel_encoder(old_conn_state->best_encoder);
5232
5233 if (old_conn_state->crtc != crtc)
5234 continue;
5235
5236 if (encoder->post_disable)
5237 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5238 }
5239 }
5240
5241 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5242 struct intel_crtc_state *old_crtc_state,
5243 struct drm_atomic_state *old_state)
5244 {
5245 struct drm_connector_state *old_conn_state;
5246 struct drm_connector *conn;
5247 int i;
5248
5249 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5250 struct intel_encoder *encoder =
5251 to_intel_encoder(old_conn_state->best_encoder);
5252
5253 if (old_conn_state->crtc != crtc)
5254 continue;
5255
5256 if (encoder->post_pll_disable)
5257 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5258 }
5259 }
5260
5261 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5262 struct drm_atomic_state *old_state)
5263 {
5264 struct drm_crtc *crtc = pipe_config->base.crtc;
5265 struct drm_device *dev = crtc->dev;
5266 struct drm_i915_private *dev_priv = to_i915(dev);
5267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5268 int pipe = intel_crtc->pipe;
5269 struct intel_atomic_state *old_intel_state =
5270 to_intel_atomic_state(old_state);
5271
5272 if (WARN_ON(intel_crtc->active))
5273 return;
5274
5275 /*
5276 * Sometimes spurious CPU pipe underruns happen during FDI
5277 * training, at least with VGA+HDMI cloning. Suppress them.
5278 *
5279 * On ILK we get an occasional spurious CPU pipe underruns
5280 * between eDP port A enable and vdd enable. Also PCH port
5281 * enable seems to result in the occasional CPU pipe underrun.
5282 *
5283 * Spurious PCH underruns also occur during PCH enabling.
5284 */
5285 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5286 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5287 if (intel_crtc->config->has_pch_encoder)
5288 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5289
5290 if (intel_crtc->config->has_pch_encoder)
5291 intel_prepare_shared_dpll(intel_crtc);
5292
5293 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5294 intel_dp_set_m_n(intel_crtc, M1_N1);
5295
5296 intel_set_pipe_timings(intel_crtc);
5297 intel_set_pipe_src_size(intel_crtc);
5298
5299 if (intel_crtc->config->has_pch_encoder) {
5300 intel_cpu_transcoder_set_m_n(intel_crtc,
5301 &intel_crtc->config->fdi_m_n, NULL);
5302 }
5303
5304 ironlake_set_pipeconf(crtc);
5305
5306 intel_crtc->active = true;
5307
5308 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5309
5310 if (intel_crtc->config->has_pch_encoder) {
5311 /* Note: FDI PLL enabling _must_ be done before we enable the
5312 * cpu pipes, hence this is separate from all the other fdi/pch
5313 * enabling. */
5314 ironlake_fdi_pll_enable(intel_crtc);
5315 } else {
5316 assert_fdi_tx_disabled(dev_priv, pipe);
5317 assert_fdi_rx_disabled(dev_priv, pipe);
5318 }
5319
5320 ironlake_pfit_enable(intel_crtc);
5321
5322 /*
5323 * On ILK+ LUT must be loaded before the pipe is running but with
5324 * clocks enabled
5325 */
5326 intel_color_load_luts(&pipe_config->base);
5327
5328 if (dev_priv->display.initial_watermarks != NULL)
5329 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5330 intel_enable_pipe(intel_crtc);
5331
5332 if (intel_crtc->config->has_pch_encoder)
5333 ironlake_pch_enable(pipe_config);
5334
5335 assert_vblank_disabled(crtc);
5336 drm_crtc_vblank_on(crtc);
5337
5338 intel_encoders_enable(crtc, pipe_config, old_state);
5339
5340 if (HAS_PCH_CPT(dev_priv))
5341 cpt_verify_modeset(dev, intel_crtc->pipe);
5342
5343 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5344 if (intel_crtc->config->has_pch_encoder)
5345 intel_wait_for_vblank(dev_priv, pipe);
5346 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5347 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5348 }
5349
5350 /* IPS only exists on ULT machines and is tied to pipe A. */
5351 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5352 {
5353 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5354 }
5355
5356 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
5357 enum pipe pipe, bool apply)
5358 {
5359 u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
5360 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
5361
5362 if (apply)
5363 val |= mask;
5364 else
5365 val &= ~mask;
5366
5367 I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
5368 }
5369
5370 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5371 struct drm_atomic_state *old_state)
5372 {
5373 struct drm_crtc *crtc = pipe_config->base.crtc;
5374 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5376 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5377 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5378 struct intel_atomic_state *old_intel_state =
5379 to_intel_atomic_state(old_state);
5380 bool psl_clkgate_wa;
5381
5382 if (WARN_ON(intel_crtc->active))
5383 return;
5384
5385 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5386
5387 if (intel_crtc->config->shared_dpll)
5388 intel_enable_shared_dpll(intel_crtc);
5389
5390 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5391 intel_dp_set_m_n(intel_crtc, M1_N1);
5392
5393 if (!transcoder_is_dsi(cpu_transcoder))
5394 intel_set_pipe_timings(intel_crtc);
5395
5396 intel_set_pipe_src_size(intel_crtc);
5397
5398 if (cpu_transcoder != TRANSCODER_EDP &&
5399 !transcoder_is_dsi(cpu_transcoder)) {
5400 I915_WRITE(PIPE_MULT(cpu_transcoder),
5401 intel_crtc->config->pixel_multiplier - 1);
5402 }
5403
5404 if (intel_crtc->config->has_pch_encoder) {
5405 intel_cpu_transcoder_set_m_n(intel_crtc,
5406 &intel_crtc->config->fdi_m_n, NULL);
5407 }
5408
5409 if (!transcoder_is_dsi(cpu_transcoder))
5410 haswell_set_pipeconf(crtc);
5411
5412 haswell_set_pipemisc(crtc);
5413
5414 intel_color_set_csc(&pipe_config->base);
5415
5416 intel_crtc->active = true;
5417
5418 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5419
5420 if (!transcoder_is_dsi(cpu_transcoder))
5421 intel_ddi_enable_pipe_clock(pipe_config);
5422
5423 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
5424 psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
5425 intel_crtc->config->pch_pfit.enabled;
5426 if (psl_clkgate_wa)
5427 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
5428
5429 if (INTEL_GEN(dev_priv) >= 9)
5430 skylake_pfit_enable(intel_crtc);
5431 else
5432 ironlake_pfit_enable(intel_crtc);
5433
5434 /*
5435 * On ILK+ LUT must be loaded before the pipe is running but with
5436 * clocks enabled
5437 */
5438 intel_color_load_luts(&pipe_config->base);
5439
5440 intel_ddi_set_pipe_settings(pipe_config);
5441 if (!transcoder_is_dsi(cpu_transcoder))
5442 intel_ddi_enable_transcoder_func(pipe_config);
5443
5444 if (dev_priv->display.initial_watermarks != NULL)
5445 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5446
5447 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5448 if (!transcoder_is_dsi(cpu_transcoder))
5449 intel_enable_pipe(intel_crtc);
5450
5451 if (intel_crtc->config->has_pch_encoder)
5452 lpt_pch_enable(pipe_config);
5453
5454 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5455 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5456
5457 assert_vblank_disabled(crtc);
5458 drm_crtc_vblank_on(crtc);
5459
5460 intel_encoders_enable(crtc, pipe_config, old_state);
5461
5462 if (psl_clkgate_wa) {
5463 intel_wait_for_vblank(dev_priv, pipe);
5464 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
5465 }
5466
5467 /* If we change the relative order between pipe/planes enabling, we need
5468 * to change the workaround. */
5469 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5470 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5471 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5472 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5473 }
5474 }
5475
5476 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5477 {
5478 struct drm_device *dev = crtc->base.dev;
5479 struct drm_i915_private *dev_priv = to_i915(dev);
5480 int pipe = crtc->pipe;
5481
5482 /* To avoid upsetting the power well on haswell only disable the pfit if
5483 * it's in use. The hw state code will make sure we get this right. */
5484 if (force || crtc->config->pch_pfit.enabled) {
5485 I915_WRITE(PF_CTL(pipe), 0);
5486 I915_WRITE(PF_WIN_POS(pipe), 0);
5487 I915_WRITE(PF_WIN_SZ(pipe), 0);
5488 }
5489 }
5490
5491 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5492 struct drm_atomic_state *old_state)
5493 {
5494 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5495 struct drm_device *dev = crtc->dev;
5496 struct drm_i915_private *dev_priv = to_i915(dev);
5497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5498 int pipe = intel_crtc->pipe;
5499
5500 /*
5501 * Sometimes spurious CPU pipe underruns happen when the
5502 * pipe is already disabled, but FDI RX/TX is still enabled.
5503 * Happens at least with VGA+HDMI cloning. Suppress them.
5504 */
5505 if (intel_crtc->config->has_pch_encoder) {
5506 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5507 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5508 }
5509
5510 intel_encoders_disable(crtc, old_crtc_state, old_state);
5511
5512 drm_crtc_vblank_off(crtc);
5513 assert_vblank_disabled(crtc);
5514
5515 intel_disable_pipe(intel_crtc);
5516
5517 ironlake_pfit_disable(intel_crtc, false);
5518
5519 if (intel_crtc->config->has_pch_encoder)
5520 ironlake_fdi_disable(crtc);
5521
5522 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5523
5524 if (intel_crtc->config->has_pch_encoder) {
5525 ironlake_disable_pch_transcoder(dev_priv, pipe);
5526
5527 if (HAS_PCH_CPT(dev_priv)) {
5528 i915_reg_t reg;
5529 u32 temp;
5530
5531 /* disable TRANS_DP_CTL */
5532 reg = TRANS_DP_CTL(pipe);
5533 temp = I915_READ(reg);
5534 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5535 TRANS_DP_PORT_SEL_MASK);
5536 temp |= TRANS_DP_PORT_SEL_NONE;
5537 I915_WRITE(reg, temp);
5538
5539 /* disable DPLL_SEL */
5540 temp = I915_READ(PCH_DPLL_SEL);
5541 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5542 I915_WRITE(PCH_DPLL_SEL, temp);
5543 }
5544
5545 ironlake_fdi_pll_disable(intel_crtc);
5546 }
5547
5548 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5549 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5550 }
5551
5552 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5553 struct drm_atomic_state *old_state)
5554 {
5555 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5556 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5558 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5559
5560 intel_encoders_disable(crtc, old_crtc_state, old_state);
5561
5562 drm_crtc_vblank_off(crtc);
5563 assert_vblank_disabled(crtc);
5564
5565 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5566 if (!transcoder_is_dsi(cpu_transcoder))
5567 intel_disable_pipe(intel_crtc);
5568
5569 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5570 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5571
5572 if (!transcoder_is_dsi(cpu_transcoder))
5573 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5574
5575 if (INTEL_GEN(dev_priv) >= 9)
5576 skylake_scaler_disable(intel_crtc);
5577 else
5578 ironlake_pfit_disable(intel_crtc, false);
5579
5580 if (!transcoder_is_dsi(cpu_transcoder))
5581 intel_ddi_disable_pipe_clock(intel_crtc->config);
5582
5583 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5584 }
5585
5586 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5587 {
5588 struct drm_device *dev = crtc->base.dev;
5589 struct drm_i915_private *dev_priv = to_i915(dev);
5590 struct intel_crtc_state *pipe_config = crtc->config;
5591
5592 if (!pipe_config->gmch_pfit.control)
5593 return;
5594
5595 /*
5596 * The panel fitter should only be adjusted whilst the pipe is disabled,
5597 * according to register description and PRM.
5598 */
5599 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5600 assert_pipe_disabled(dev_priv, crtc->pipe);
5601
5602 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5603 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5604
5605 /* Border color in case we don't scale up to the full screen. Black by
5606 * default, change to something else for debugging. */
5607 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5608 }
5609
5610 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5611 {
5612 switch (port) {
5613 case PORT_A:
5614 return POWER_DOMAIN_PORT_DDI_A_LANES;
5615 case PORT_B:
5616 return POWER_DOMAIN_PORT_DDI_B_LANES;
5617 case PORT_C:
5618 return POWER_DOMAIN_PORT_DDI_C_LANES;
5619 case PORT_D:
5620 return POWER_DOMAIN_PORT_DDI_D_LANES;
5621 case PORT_E:
5622 return POWER_DOMAIN_PORT_DDI_E_LANES;
5623 default:
5624 MISSING_CASE(port);
5625 return POWER_DOMAIN_PORT_OTHER;
5626 }
5627 }
5628
5629 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5630 struct intel_crtc_state *crtc_state)
5631 {
5632 struct drm_device *dev = crtc->dev;
5633 struct drm_i915_private *dev_priv = to_i915(dev);
5634 struct drm_encoder *encoder;
5635 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5636 enum pipe pipe = intel_crtc->pipe;
5637 u64 mask;
5638 enum transcoder transcoder = crtc_state->cpu_transcoder;
5639
5640 if (!crtc_state->base.active)
5641 return 0;
5642
5643 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5644 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5645 if (crtc_state->pch_pfit.enabled ||
5646 crtc_state->pch_pfit.force_thru)
5647 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5648
5649 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5650 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5651
5652 mask |= BIT_ULL(intel_encoder->power_domain);
5653 }
5654
5655 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5656 mask |= BIT(POWER_DOMAIN_AUDIO);
5657
5658 if (crtc_state->shared_dpll)
5659 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5660
5661 return mask;
5662 }
5663
5664 static u64
5665 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5666 struct intel_crtc_state *crtc_state)
5667 {
5668 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5669 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5670 enum intel_display_power_domain domain;
5671 u64 domains, new_domains, old_domains;
5672
5673 old_domains = intel_crtc->enabled_power_domains;
5674 intel_crtc->enabled_power_domains = new_domains =
5675 get_crtc_power_domains(crtc, crtc_state);
5676
5677 domains = new_domains & ~old_domains;
5678
5679 for_each_power_domain(domain, domains)
5680 intel_display_power_get(dev_priv, domain);
5681
5682 return old_domains & ~new_domains;
5683 }
5684
5685 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5686 u64 domains)
5687 {
5688 enum intel_display_power_domain domain;
5689
5690 for_each_power_domain(domain, domains)
5691 intel_display_power_put(dev_priv, domain);
5692 }
5693
5694 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5695 struct drm_atomic_state *old_state)
5696 {
5697 struct intel_atomic_state *old_intel_state =
5698 to_intel_atomic_state(old_state);
5699 struct drm_crtc *crtc = pipe_config->base.crtc;
5700 struct drm_device *dev = crtc->dev;
5701 struct drm_i915_private *dev_priv = to_i915(dev);
5702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5703 int pipe = intel_crtc->pipe;
5704
5705 if (WARN_ON(intel_crtc->active))
5706 return;
5707
5708 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5709 intel_dp_set_m_n(intel_crtc, M1_N1);
5710
5711 intel_set_pipe_timings(intel_crtc);
5712 intel_set_pipe_src_size(intel_crtc);
5713
5714 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5715 struct drm_i915_private *dev_priv = to_i915(dev);
5716
5717 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5718 I915_WRITE(CHV_CANVAS(pipe), 0);
5719 }
5720
5721 i9xx_set_pipeconf(intel_crtc);
5722
5723 intel_crtc->active = true;
5724
5725 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5726
5727 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5728
5729 if (IS_CHERRYVIEW(dev_priv)) {
5730 chv_prepare_pll(intel_crtc, intel_crtc->config);
5731 chv_enable_pll(intel_crtc, intel_crtc->config);
5732 } else {
5733 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5734 vlv_enable_pll(intel_crtc, intel_crtc->config);
5735 }
5736
5737 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5738
5739 i9xx_pfit_enable(intel_crtc);
5740
5741 intel_color_load_luts(&pipe_config->base);
5742
5743 dev_priv->display.initial_watermarks(old_intel_state,
5744 pipe_config);
5745 intel_enable_pipe(intel_crtc);
5746
5747 assert_vblank_disabled(crtc);
5748 drm_crtc_vblank_on(crtc);
5749
5750 intel_encoders_enable(crtc, pipe_config, old_state);
5751 }
5752
5753 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5754 {
5755 struct drm_device *dev = crtc->base.dev;
5756 struct drm_i915_private *dev_priv = to_i915(dev);
5757
5758 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5759 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5760 }
5761
5762 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5763 struct drm_atomic_state *old_state)
5764 {
5765 struct intel_atomic_state *old_intel_state =
5766 to_intel_atomic_state(old_state);
5767 struct drm_crtc *crtc = pipe_config->base.crtc;
5768 struct drm_device *dev = crtc->dev;
5769 struct drm_i915_private *dev_priv = to_i915(dev);
5770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5771 enum pipe pipe = intel_crtc->pipe;
5772
5773 if (WARN_ON(intel_crtc->active))
5774 return;
5775
5776 i9xx_set_pll_dividers(intel_crtc);
5777
5778 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5779 intel_dp_set_m_n(intel_crtc, M1_N1);
5780
5781 intel_set_pipe_timings(intel_crtc);
5782 intel_set_pipe_src_size(intel_crtc);
5783
5784 i9xx_set_pipeconf(intel_crtc);
5785
5786 intel_crtc->active = true;
5787
5788 if (!IS_GEN2(dev_priv))
5789 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5790
5791 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5792
5793 i9xx_enable_pll(intel_crtc, pipe_config);
5794
5795 i9xx_pfit_enable(intel_crtc);
5796
5797 intel_color_load_luts(&pipe_config->base);
5798
5799 if (dev_priv->display.initial_watermarks != NULL)
5800 dev_priv->display.initial_watermarks(old_intel_state,
5801 intel_crtc->config);
5802 else
5803 intel_update_watermarks(intel_crtc);
5804 intel_enable_pipe(intel_crtc);
5805
5806 assert_vblank_disabled(crtc);
5807 drm_crtc_vblank_on(crtc);
5808
5809 intel_encoders_enable(crtc, pipe_config, old_state);
5810 }
5811
5812 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5813 {
5814 struct drm_device *dev = crtc->base.dev;
5815 struct drm_i915_private *dev_priv = to_i915(dev);
5816
5817 if (!crtc->config->gmch_pfit.control)
5818 return;
5819
5820 assert_pipe_disabled(dev_priv, crtc->pipe);
5821
5822 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5823 I915_READ(PFIT_CONTROL));
5824 I915_WRITE(PFIT_CONTROL, 0);
5825 }
5826
5827 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5828 struct drm_atomic_state *old_state)
5829 {
5830 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5831 struct drm_device *dev = crtc->dev;
5832 struct drm_i915_private *dev_priv = to_i915(dev);
5833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5834 int pipe = intel_crtc->pipe;
5835
5836 /*
5837 * On gen2 planes are double buffered but the pipe isn't, so we must
5838 * wait for planes to fully turn off before disabling the pipe.
5839 */
5840 if (IS_GEN2(dev_priv))
5841 intel_wait_for_vblank(dev_priv, pipe);
5842
5843 intel_encoders_disable(crtc, old_crtc_state, old_state);
5844
5845 drm_crtc_vblank_off(crtc);
5846 assert_vblank_disabled(crtc);
5847
5848 intel_disable_pipe(intel_crtc);
5849
5850 i9xx_pfit_disable(intel_crtc);
5851
5852 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5853
5854 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5855 if (IS_CHERRYVIEW(dev_priv))
5856 chv_disable_pll(dev_priv, pipe);
5857 else if (IS_VALLEYVIEW(dev_priv))
5858 vlv_disable_pll(dev_priv, pipe);
5859 else
5860 i9xx_disable_pll(intel_crtc);
5861 }
5862
5863 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5864
5865 if (!IS_GEN2(dev_priv))
5866 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5867
5868 if (!dev_priv->display.initial_watermarks)
5869 intel_update_watermarks(intel_crtc);
5870
5871 /* clock the pipe down to 640x480@60 to potentially save power */
5872 if (IS_I830(dev_priv))
5873 i830_enable_pipe(dev_priv, pipe);
5874 }
5875
5876 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
5877 struct drm_modeset_acquire_ctx *ctx)
5878 {
5879 struct intel_encoder *encoder;
5880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5881 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5882 enum intel_display_power_domain domain;
5883 u64 domains;
5884 struct drm_atomic_state *state;
5885 struct intel_crtc_state *crtc_state;
5886 int ret;
5887
5888 if (!intel_crtc->active)
5889 return;
5890
5891 if (crtc->primary->state->visible) {
5892 intel_pre_disable_primary_noatomic(crtc);
5893
5894 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5895 crtc->primary->state->visible = false;
5896 }
5897
5898 state = drm_atomic_state_alloc(crtc->dev);
5899 if (!state) {
5900 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5901 crtc->base.id, crtc->name);
5902 return;
5903 }
5904
5905 state->acquire_ctx = ctx;
5906
5907 /* Everything's already locked, -EDEADLK can't happen. */
5908 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5909 ret = drm_atomic_add_affected_connectors(state, crtc);
5910
5911 WARN_ON(IS_ERR(crtc_state) || ret);
5912
5913 dev_priv->display.crtc_disable(crtc_state, state);
5914
5915 drm_atomic_state_put(state);
5916
5917 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5918 crtc->base.id, crtc->name);
5919
5920 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5921 crtc->state->active = false;
5922 intel_crtc->active = false;
5923 crtc->enabled = false;
5924 crtc->state->connector_mask = 0;
5925 crtc->state->encoder_mask = 0;
5926
5927 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5928 encoder->base.crtc = NULL;
5929
5930 intel_fbc_disable(intel_crtc);
5931 intel_update_watermarks(intel_crtc);
5932 intel_disable_shared_dpll(intel_crtc);
5933
5934 domains = intel_crtc->enabled_power_domains;
5935 for_each_power_domain(domain, domains)
5936 intel_display_power_put(dev_priv, domain);
5937 intel_crtc->enabled_power_domains = 0;
5938
5939 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5940 dev_priv->min_cdclk[intel_crtc->pipe] = 0;
5941 }
5942
5943 /*
5944 * turn all crtc's off, but do not adjust state
5945 * This has to be paired with a call to intel_modeset_setup_hw_state.
5946 */
5947 int intel_display_suspend(struct drm_device *dev)
5948 {
5949 struct drm_i915_private *dev_priv = to_i915(dev);
5950 struct drm_atomic_state *state;
5951 int ret;
5952
5953 state = drm_atomic_helper_suspend(dev);
5954 ret = PTR_ERR_OR_ZERO(state);
5955 if (ret)
5956 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5957 else
5958 dev_priv->modeset_restore_state = state;
5959 return ret;
5960 }
5961
5962 void intel_encoder_destroy(struct drm_encoder *encoder)
5963 {
5964 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5965
5966 drm_encoder_cleanup(encoder);
5967 kfree(intel_encoder);
5968 }
5969
5970 /* Cross check the actual hw state with our own modeset state tracking (and it's
5971 * internal consistency). */
5972 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
5973 struct drm_connector_state *conn_state)
5974 {
5975 struct intel_connector *connector = to_intel_connector(conn_state->connector);
5976
5977 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5978 connector->base.base.id,
5979 connector->base.name);
5980
5981 if (connector->get_hw_state(connector)) {
5982 struct intel_encoder *encoder = connector->encoder;
5983
5984 I915_STATE_WARN(!crtc_state,
5985 "connector enabled without attached crtc\n");
5986
5987 if (!crtc_state)
5988 return;
5989
5990 I915_STATE_WARN(!crtc_state->active,
5991 "connector is active, but attached crtc isn't\n");
5992
5993 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
5994 return;
5995
5996 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
5997 "atomic encoder doesn't match attached encoder\n");
5998
5999 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6000 "attached encoder crtc differs from connector crtc\n");
6001 } else {
6002 I915_STATE_WARN(crtc_state && crtc_state->active,
6003 "attached crtc is active, but connector isn't\n");
6004 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
6005 "best encoder set without crtc!\n");
6006 }
6007 }
6008
6009 int intel_connector_init(struct intel_connector *connector)
6010 {
6011 struct intel_digital_connector_state *conn_state;
6012
6013 /*
6014 * Allocate enough memory to hold intel_digital_connector_state,
6015 * This might be a few bytes too many, but for connectors that don't
6016 * need it we'll free the state and allocate a smaller one on the first
6017 * succesful commit anyway.
6018 */
6019 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
6020 if (!conn_state)
6021 return -ENOMEM;
6022
6023 __drm_atomic_helper_connector_reset(&connector->base,
6024 &conn_state->base);
6025
6026 return 0;
6027 }
6028
6029 struct intel_connector *intel_connector_alloc(void)
6030 {
6031 struct intel_connector *connector;
6032
6033 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6034 if (!connector)
6035 return NULL;
6036
6037 if (intel_connector_init(connector) < 0) {
6038 kfree(connector);
6039 return NULL;
6040 }
6041
6042 return connector;
6043 }
6044
6045 /*
6046 * Free the bits allocated by intel_connector_alloc.
6047 * This should only be used after intel_connector_alloc has returned
6048 * successfully, and before drm_connector_init returns successfully.
6049 * Otherwise the destroy callbacks for the connector and the state should
6050 * take care of proper cleanup/free
6051 */
6052 void intel_connector_free(struct intel_connector *connector)
6053 {
6054 kfree(to_intel_digital_connector_state(connector->base.state));
6055 kfree(connector);
6056 }
6057
6058 /* Simple connector->get_hw_state implementation for encoders that support only
6059 * one connector and no cloning and hence the encoder state determines the state
6060 * of the connector. */
6061 bool intel_connector_get_hw_state(struct intel_connector *connector)
6062 {
6063 enum pipe pipe = 0;
6064 struct intel_encoder *encoder = connector->encoder;
6065
6066 return encoder->get_hw_state(encoder, &pipe);
6067 }
6068
6069 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6070 {
6071 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6072 return crtc_state->fdi_lanes;
6073
6074 return 0;
6075 }
6076
6077 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6078 struct intel_crtc_state *pipe_config)
6079 {
6080 struct drm_i915_private *dev_priv = to_i915(dev);
6081 struct drm_atomic_state *state = pipe_config->base.state;
6082 struct intel_crtc *other_crtc;
6083 struct intel_crtc_state *other_crtc_state;
6084
6085 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6086 pipe_name(pipe), pipe_config->fdi_lanes);
6087 if (pipe_config->fdi_lanes > 4) {
6088 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6089 pipe_name(pipe), pipe_config->fdi_lanes);
6090 return -EINVAL;
6091 }
6092
6093 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6094 if (pipe_config->fdi_lanes > 2) {
6095 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6096 pipe_config->fdi_lanes);
6097 return -EINVAL;
6098 } else {
6099 return 0;
6100 }
6101 }
6102
6103 if (INTEL_INFO(dev_priv)->num_pipes == 2)
6104 return 0;
6105
6106 /* Ivybridge 3 pipe is really complicated */
6107 switch (pipe) {
6108 case PIPE_A:
6109 return 0;
6110 case PIPE_B:
6111 if (pipe_config->fdi_lanes <= 2)
6112 return 0;
6113
6114 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6115 other_crtc_state =
6116 intel_atomic_get_crtc_state(state, other_crtc);
6117 if (IS_ERR(other_crtc_state))
6118 return PTR_ERR(other_crtc_state);
6119
6120 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6121 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6122 pipe_name(pipe), pipe_config->fdi_lanes);
6123 return -EINVAL;
6124 }
6125 return 0;
6126 case PIPE_C:
6127 if (pipe_config->fdi_lanes > 2) {
6128 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6129 pipe_name(pipe), pipe_config->fdi_lanes);
6130 return -EINVAL;
6131 }
6132
6133 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6134 other_crtc_state =
6135 intel_atomic_get_crtc_state(state, other_crtc);
6136 if (IS_ERR(other_crtc_state))
6137 return PTR_ERR(other_crtc_state);
6138
6139 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6140 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6141 return -EINVAL;
6142 }
6143 return 0;
6144 default:
6145 BUG();
6146 }
6147 }
6148
6149 #define RETRY 1
6150 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6151 struct intel_crtc_state *pipe_config)
6152 {
6153 struct drm_device *dev = intel_crtc->base.dev;
6154 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6155 int lane, link_bw, fdi_dotclock, ret;
6156 bool needs_recompute = false;
6157
6158 retry:
6159 /* FDI is a binary signal running at ~2.7GHz, encoding
6160 * each output octet as 10 bits. The actual frequency
6161 * is stored as a divider into a 100MHz clock, and the
6162 * mode pixel clock is stored in units of 1KHz.
6163 * Hence the bw of each lane in terms of the mode signal
6164 * is:
6165 */
6166 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6167
6168 fdi_dotclock = adjusted_mode->crtc_clock;
6169
6170 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6171 pipe_config->pipe_bpp);
6172
6173 pipe_config->fdi_lanes = lane;
6174
6175 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6176 link_bw, &pipe_config->fdi_m_n, false);
6177
6178 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6179 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6180 pipe_config->pipe_bpp -= 2*3;
6181 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6182 pipe_config->pipe_bpp);
6183 needs_recompute = true;
6184 pipe_config->bw_constrained = true;
6185
6186 goto retry;
6187 }
6188
6189 if (needs_recompute)
6190 return RETRY;
6191
6192 return ret;
6193 }
6194
6195 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6196 struct intel_crtc_state *pipe_config)
6197 {
6198 if (pipe_config->ips_force_disable)
6199 return false;
6200
6201 if (pipe_config->pipe_bpp > 24)
6202 return false;
6203
6204 /* HSW can handle pixel rate up to cdclk? */
6205 if (IS_HASWELL(dev_priv))
6206 return true;
6207
6208 /*
6209 * We compare against max which means we must take
6210 * the increased cdclk requirement into account when
6211 * calculating the new cdclk.
6212 *
6213 * Should measure whether using a lower cdclk w/o IPS
6214 */
6215 return pipe_config->pixel_rate <=
6216 dev_priv->max_cdclk_freq * 95 / 100;
6217 }
6218
6219 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6220 struct intel_crtc_state *pipe_config)
6221 {
6222 struct drm_device *dev = crtc->base.dev;
6223 struct drm_i915_private *dev_priv = to_i915(dev);
6224
6225 pipe_config->ips_enabled = i915_modparams.enable_ips &&
6226 hsw_crtc_supports_ips(crtc) &&
6227 pipe_config_supports_ips(dev_priv, pipe_config);
6228 }
6229
6230 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6231 {
6232 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6233
6234 /* GDG double wide on either pipe, otherwise pipe A only */
6235 return INTEL_INFO(dev_priv)->gen < 4 &&
6236 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6237 }
6238
6239 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6240 {
6241 uint32_t pixel_rate;
6242
6243 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6244
6245 /*
6246 * We only use IF-ID interlacing. If we ever use
6247 * PF-ID we'll need to adjust the pixel_rate here.
6248 */
6249
6250 if (pipe_config->pch_pfit.enabled) {
6251 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6252 uint32_t pfit_size = pipe_config->pch_pfit.size;
6253
6254 pipe_w = pipe_config->pipe_src_w;
6255 pipe_h = pipe_config->pipe_src_h;
6256
6257 pfit_w = (pfit_size >> 16) & 0xFFFF;
6258 pfit_h = pfit_size & 0xFFFF;
6259 if (pipe_w < pfit_w)
6260 pipe_w = pfit_w;
6261 if (pipe_h < pfit_h)
6262 pipe_h = pfit_h;
6263
6264 if (WARN_ON(!pfit_w || !pfit_h))
6265 return pixel_rate;
6266
6267 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6268 pfit_w * pfit_h);
6269 }
6270
6271 return pixel_rate;
6272 }
6273
6274 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6275 {
6276 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6277
6278 if (HAS_GMCH_DISPLAY(dev_priv))
6279 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6280 crtc_state->pixel_rate =
6281 crtc_state->base.adjusted_mode.crtc_clock;
6282 else
6283 crtc_state->pixel_rate =
6284 ilk_pipe_pixel_rate(crtc_state);
6285 }
6286
6287 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6288 struct intel_crtc_state *pipe_config)
6289 {
6290 struct drm_device *dev = crtc->base.dev;
6291 struct drm_i915_private *dev_priv = to_i915(dev);
6292 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6293 int clock_limit = dev_priv->max_dotclk_freq;
6294
6295 if (INTEL_GEN(dev_priv) < 4) {
6296 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6297
6298 /*
6299 * Enable double wide mode when the dot clock
6300 * is > 90% of the (display) core speed.
6301 */
6302 if (intel_crtc_supports_double_wide(crtc) &&
6303 adjusted_mode->crtc_clock > clock_limit) {
6304 clock_limit = dev_priv->max_dotclk_freq;
6305 pipe_config->double_wide = true;
6306 }
6307 }
6308
6309 if (adjusted_mode->crtc_clock > clock_limit) {
6310 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6311 adjusted_mode->crtc_clock, clock_limit,
6312 yesno(pipe_config->double_wide));
6313 return -EINVAL;
6314 }
6315
6316 if (pipe_config->ycbcr420 && pipe_config->base.ctm) {
6317 /*
6318 * There is only one pipe CSC unit per pipe, and we need that
6319 * for output conversion from RGB->YCBCR. So if CTM is already
6320 * applied we can't support YCBCR420 output.
6321 */
6322 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
6323 return -EINVAL;
6324 }
6325
6326 /*
6327 * Pipe horizontal size must be even in:
6328 * - DVO ganged mode
6329 * - LVDS dual channel mode
6330 * - Double wide pipe
6331 */
6332 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6333 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6334 pipe_config->pipe_src_w &= ~1;
6335
6336 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6337 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6338 */
6339 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6340 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6341 return -EINVAL;
6342
6343 intel_crtc_compute_pixel_rate(pipe_config);
6344
6345 if (HAS_IPS(dev_priv))
6346 hsw_compute_ips_config(crtc, pipe_config);
6347
6348 if (pipe_config->has_pch_encoder)
6349 return ironlake_fdi_compute_config(crtc, pipe_config);
6350
6351 return 0;
6352 }
6353
6354 static void
6355 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6356 {
6357 while (*num > DATA_LINK_M_N_MASK ||
6358 *den > DATA_LINK_M_N_MASK) {
6359 *num >>= 1;
6360 *den >>= 1;
6361 }
6362 }
6363
6364 static void compute_m_n(unsigned int m, unsigned int n,
6365 uint32_t *ret_m, uint32_t *ret_n,
6366 bool reduce_m_n)
6367 {
6368 /*
6369 * Reduce M/N as much as possible without loss in precision. Several DP
6370 * dongles in particular seem to be fussy about too large *link* M/N
6371 * values. The passed in values are more likely to have the least
6372 * significant bits zero than M after rounding below, so do this first.
6373 */
6374 if (reduce_m_n) {
6375 while ((m & 1) == 0 && (n & 1) == 0) {
6376 m >>= 1;
6377 n >>= 1;
6378 }
6379 }
6380
6381 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6382 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6383 intel_reduce_m_n_ratio(ret_m, ret_n);
6384 }
6385
6386 void
6387 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6388 int pixel_clock, int link_clock,
6389 struct intel_link_m_n *m_n,
6390 bool reduce_m_n)
6391 {
6392 m_n->tu = 64;
6393
6394 compute_m_n(bits_per_pixel * pixel_clock,
6395 link_clock * nlanes * 8,
6396 &m_n->gmch_m, &m_n->gmch_n,
6397 reduce_m_n);
6398
6399 compute_m_n(pixel_clock, link_clock,
6400 &m_n->link_m, &m_n->link_n,
6401 reduce_m_n);
6402 }
6403
6404 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6405 {
6406 if (i915_modparams.panel_use_ssc >= 0)
6407 return i915_modparams.panel_use_ssc != 0;
6408 return dev_priv->vbt.lvds_use_ssc
6409 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6410 }
6411
6412 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6413 {
6414 return (1 << dpll->n) << 16 | dpll->m2;
6415 }
6416
6417 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6418 {
6419 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6420 }
6421
6422 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6423 struct intel_crtc_state *crtc_state,
6424 struct dpll *reduced_clock)
6425 {
6426 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6427 u32 fp, fp2 = 0;
6428
6429 if (IS_PINEVIEW(dev_priv)) {
6430 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6431 if (reduced_clock)
6432 fp2 = pnv_dpll_compute_fp(reduced_clock);
6433 } else {
6434 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6435 if (reduced_clock)
6436 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6437 }
6438
6439 crtc_state->dpll_hw_state.fp0 = fp;
6440
6441 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6442 reduced_clock) {
6443 crtc_state->dpll_hw_state.fp1 = fp2;
6444 } else {
6445 crtc_state->dpll_hw_state.fp1 = fp;
6446 }
6447 }
6448
6449 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6450 pipe)
6451 {
6452 u32 reg_val;
6453
6454 /*
6455 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6456 * and set it to a reasonable value instead.
6457 */
6458 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6459 reg_val &= 0xffffff00;
6460 reg_val |= 0x00000030;
6461 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6462
6463 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6464 reg_val &= 0x00ffffff;
6465 reg_val |= 0x8c000000;
6466 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6467
6468 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6469 reg_val &= 0xffffff00;
6470 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6471
6472 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6473 reg_val &= 0x00ffffff;
6474 reg_val |= 0xb0000000;
6475 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6476 }
6477
6478 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6479 struct intel_link_m_n *m_n)
6480 {
6481 struct drm_device *dev = crtc->base.dev;
6482 struct drm_i915_private *dev_priv = to_i915(dev);
6483 int pipe = crtc->pipe;
6484
6485 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6486 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6487 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6488 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6489 }
6490
6491 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6492 struct intel_link_m_n *m_n,
6493 struct intel_link_m_n *m2_n2)
6494 {
6495 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6496 int pipe = crtc->pipe;
6497 enum transcoder transcoder = crtc->config->cpu_transcoder;
6498
6499 if (INTEL_GEN(dev_priv) >= 5) {
6500 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6501 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6502 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6503 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6504 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6505 * for gen < 8) and if DRRS is supported (to make sure the
6506 * registers are not unnecessarily accessed).
6507 */
6508 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6509 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6510 I915_WRITE(PIPE_DATA_M2(transcoder),
6511 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6512 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6513 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6514 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6515 }
6516 } else {
6517 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6518 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6519 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6520 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6521 }
6522 }
6523
6524 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6525 {
6526 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6527
6528 if (m_n == M1_N1) {
6529 dp_m_n = &crtc->config->dp_m_n;
6530 dp_m2_n2 = &crtc->config->dp_m2_n2;
6531 } else if (m_n == M2_N2) {
6532
6533 /*
6534 * M2_N2 registers are not supported. Hence m2_n2 divider value
6535 * needs to be programmed into M1_N1.
6536 */
6537 dp_m_n = &crtc->config->dp_m2_n2;
6538 } else {
6539 DRM_ERROR("Unsupported divider value\n");
6540 return;
6541 }
6542
6543 if (crtc->config->has_pch_encoder)
6544 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6545 else
6546 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6547 }
6548
6549 static void vlv_compute_dpll(struct intel_crtc *crtc,
6550 struct intel_crtc_state *pipe_config)
6551 {
6552 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6553 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6554 if (crtc->pipe != PIPE_A)
6555 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6556
6557 /* DPLL not used with DSI, but still need the rest set up */
6558 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6559 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6560 DPLL_EXT_BUFFER_ENABLE_VLV;
6561
6562 pipe_config->dpll_hw_state.dpll_md =
6563 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6564 }
6565
6566 static void chv_compute_dpll(struct intel_crtc *crtc,
6567 struct intel_crtc_state *pipe_config)
6568 {
6569 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6570 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6571 if (crtc->pipe != PIPE_A)
6572 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6573
6574 /* DPLL not used with DSI, but still need the rest set up */
6575 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6576 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6577
6578 pipe_config->dpll_hw_state.dpll_md =
6579 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6580 }
6581
6582 static void vlv_prepare_pll(struct intel_crtc *crtc,
6583 const struct intel_crtc_state *pipe_config)
6584 {
6585 struct drm_device *dev = crtc->base.dev;
6586 struct drm_i915_private *dev_priv = to_i915(dev);
6587 enum pipe pipe = crtc->pipe;
6588 u32 mdiv;
6589 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6590 u32 coreclk, reg_val;
6591
6592 /* Enable Refclk */
6593 I915_WRITE(DPLL(pipe),
6594 pipe_config->dpll_hw_state.dpll &
6595 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6596
6597 /* No need to actually set up the DPLL with DSI */
6598 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6599 return;
6600
6601 mutex_lock(&dev_priv->sb_lock);
6602
6603 bestn = pipe_config->dpll.n;
6604 bestm1 = pipe_config->dpll.m1;
6605 bestm2 = pipe_config->dpll.m2;
6606 bestp1 = pipe_config->dpll.p1;
6607 bestp2 = pipe_config->dpll.p2;
6608
6609 /* See eDP HDMI DPIO driver vbios notes doc */
6610
6611 /* PLL B needs special handling */
6612 if (pipe == PIPE_B)
6613 vlv_pllb_recal_opamp(dev_priv, pipe);
6614
6615 /* Set up Tx target for periodic Rcomp update */
6616 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6617
6618 /* Disable target IRef on PLL */
6619 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6620 reg_val &= 0x00ffffff;
6621 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6622
6623 /* Disable fast lock */
6624 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6625
6626 /* Set idtafcrecal before PLL is enabled */
6627 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6628 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6629 mdiv |= ((bestn << DPIO_N_SHIFT));
6630 mdiv |= (1 << DPIO_K_SHIFT);
6631
6632 /*
6633 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6634 * but we don't support that).
6635 * Note: don't use the DAC post divider as it seems unstable.
6636 */
6637 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6638 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6639
6640 mdiv |= DPIO_ENABLE_CALIBRATION;
6641 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6642
6643 /* Set HBR and RBR LPF coefficients */
6644 if (pipe_config->port_clock == 162000 ||
6645 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6646 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6647 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6648 0x009f0003);
6649 else
6650 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6651 0x00d0000f);
6652
6653 if (intel_crtc_has_dp_encoder(pipe_config)) {
6654 /* Use SSC source */
6655 if (pipe == PIPE_A)
6656 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6657 0x0df40000);
6658 else
6659 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6660 0x0df70000);
6661 } else { /* HDMI or VGA */
6662 /* Use bend source */
6663 if (pipe == PIPE_A)
6664 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6665 0x0df70000);
6666 else
6667 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6668 0x0df40000);
6669 }
6670
6671 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6672 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6673 if (intel_crtc_has_dp_encoder(crtc->config))
6674 coreclk |= 0x01000000;
6675 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6676
6677 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6678 mutex_unlock(&dev_priv->sb_lock);
6679 }
6680
6681 static void chv_prepare_pll(struct intel_crtc *crtc,
6682 const struct intel_crtc_state *pipe_config)
6683 {
6684 struct drm_device *dev = crtc->base.dev;
6685 struct drm_i915_private *dev_priv = to_i915(dev);
6686 enum pipe pipe = crtc->pipe;
6687 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6688 u32 loopfilter, tribuf_calcntr;
6689 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6690 u32 dpio_val;
6691 int vco;
6692
6693 /* Enable Refclk and SSC */
6694 I915_WRITE(DPLL(pipe),
6695 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6696
6697 /* No need to actually set up the DPLL with DSI */
6698 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6699 return;
6700
6701 bestn = pipe_config->dpll.n;
6702 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6703 bestm1 = pipe_config->dpll.m1;
6704 bestm2 = pipe_config->dpll.m2 >> 22;
6705 bestp1 = pipe_config->dpll.p1;
6706 bestp2 = pipe_config->dpll.p2;
6707 vco = pipe_config->dpll.vco;
6708 dpio_val = 0;
6709 loopfilter = 0;
6710
6711 mutex_lock(&dev_priv->sb_lock);
6712
6713 /* p1 and p2 divider */
6714 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6715 5 << DPIO_CHV_S1_DIV_SHIFT |
6716 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6717 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6718 1 << DPIO_CHV_K_DIV_SHIFT);
6719
6720 /* Feedback post-divider - m2 */
6721 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6722
6723 /* Feedback refclk divider - n and m1 */
6724 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6725 DPIO_CHV_M1_DIV_BY_2 |
6726 1 << DPIO_CHV_N_DIV_SHIFT);
6727
6728 /* M2 fraction division */
6729 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6730
6731 /* M2 fraction division enable */
6732 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6733 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6734 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6735 if (bestm2_frac)
6736 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6737 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6738
6739 /* Program digital lock detect threshold */
6740 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6741 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6742 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6743 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6744 if (!bestm2_frac)
6745 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6746 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6747
6748 /* Loop filter */
6749 if (vco == 5400000) {
6750 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6751 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6752 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6753 tribuf_calcntr = 0x9;
6754 } else if (vco <= 6200000) {
6755 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6756 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6757 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6758 tribuf_calcntr = 0x9;
6759 } else if (vco <= 6480000) {
6760 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6761 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6762 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6763 tribuf_calcntr = 0x8;
6764 } else {
6765 /* Not supported. Apply the same limits as in the max case */
6766 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6767 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6768 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6769 tribuf_calcntr = 0;
6770 }
6771 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6772
6773 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6774 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6775 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6776 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6777
6778 /* AFC Recal */
6779 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6780 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6781 DPIO_AFC_RECAL);
6782
6783 mutex_unlock(&dev_priv->sb_lock);
6784 }
6785
6786 /**
6787 * vlv_force_pll_on - forcibly enable just the PLL
6788 * @dev_priv: i915 private structure
6789 * @pipe: pipe PLL to enable
6790 * @dpll: PLL configuration
6791 *
6792 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6793 * in cases where we need the PLL enabled even when @pipe is not going to
6794 * be enabled.
6795 */
6796 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6797 const struct dpll *dpll)
6798 {
6799 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6800 struct intel_crtc_state *pipe_config;
6801
6802 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6803 if (!pipe_config)
6804 return -ENOMEM;
6805
6806 pipe_config->base.crtc = &crtc->base;
6807 pipe_config->pixel_multiplier = 1;
6808 pipe_config->dpll = *dpll;
6809
6810 if (IS_CHERRYVIEW(dev_priv)) {
6811 chv_compute_dpll(crtc, pipe_config);
6812 chv_prepare_pll(crtc, pipe_config);
6813 chv_enable_pll(crtc, pipe_config);
6814 } else {
6815 vlv_compute_dpll(crtc, pipe_config);
6816 vlv_prepare_pll(crtc, pipe_config);
6817 vlv_enable_pll(crtc, pipe_config);
6818 }
6819
6820 kfree(pipe_config);
6821
6822 return 0;
6823 }
6824
6825 /**
6826 * vlv_force_pll_off - forcibly disable just the PLL
6827 * @dev_priv: i915 private structure
6828 * @pipe: pipe PLL to disable
6829 *
6830 * Disable the PLL for @pipe. To be used in cases where we need
6831 * the PLL enabled even when @pipe is not going to be enabled.
6832 */
6833 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6834 {
6835 if (IS_CHERRYVIEW(dev_priv))
6836 chv_disable_pll(dev_priv, pipe);
6837 else
6838 vlv_disable_pll(dev_priv, pipe);
6839 }
6840
6841 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6842 struct intel_crtc_state *crtc_state,
6843 struct dpll *reduced_clock)
6844 {
6845 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6846 u32 dpll;
6847 struct dpll *clock = &crtc_state->dpll;
6848
6849 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6850
6851 dpll = DPLL_VGA_MODE_DIS;
6852
6853 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6854 dpll |= DPLLB_MODE_LVDS;
6855 else
6856 dpll |= DPLLB_MODE_DAC_SERIAL;
6857
6858 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6859 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6860 dpll |= (crtc_state->pixel_multiplier - 1)
6861 << SDVO_MULTIPLIER_SHIFT_HIRES;
6862 }
6863
6864 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6865 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6866 dpll |= DPLL_SDVO_HIGH_SPEED;
6867
6868 if (intel_crtc_has_dp_encoder(crtc_state))
6869 dpll |= DPLL_SDVO_HIGH_SPEED;
6870
6871 /* compute bitmask from p1 value */
6872 if (IS_PINEVIEW(dev_priv))
6873 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6874 else {
6875 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6876 if (IS_G4X(dev_priv) && reduced_clock)
6877 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6878 }
6879 switch (clock->p2) {
6880 case 5:
6881 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6882 break;
6883 case 7:
6884 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6885 break;
6886 case 10:
6887 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6888 break;
6889 case 14:
6890 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6891 break;
6892 }
6893 if (INTEL_GEN(dev_priv) >= 4)
6894 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6895
6896 if (crtc_state->sdvo_tv_clock)
6897 dpll |= PLL_REF_INPUT_TVCLKINBC;
6898 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6899 intel_panel_use_ssc(dev_priv))
6900 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6901 else
6902 dpll |= PLL_REF_INPUT_DREFCLK;
6903
6904 dpll |= DPLL_VCO_ENABLE;
6905 crtc_state->dpll_hw_state.dpll = dpll;
6906
6907 if (INTEL_GEN(dev_priv) >= 4) {
6908 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6909 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6910 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6911 }
6912 }
6913
6914 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6915 struct intel_crtc_state *crtc_state,
6916 struct dpll *reduced_clock)
6917 {
6918 struct drm_device *dev = crtc->base.dev;
6919 struct drm_i915_private *dev_priv = to_i915(dev);
6920 u32 dpll;
6921 struct dpll *clock = &crtc_state->dpll;
6922
6923 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6924
6925 dpll = DPLL_VGA_MODE_DIS;
6926
6927 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6928 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6929 } else {
6930 if (clock->p1 == 2)
6931 dpll |= PLL_P1_DIVIDE_BY_TWO;
6932 else
6933 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6934 if (clock->p2 == 4)
6935 dpll |= PLL_P2_DIVIDE_BY_4;
6936 }
6937
6938 if (!IS_I830(dev_priv) &&
6939 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6940 dpll |= DPLL_DVO_2X_MODE;
6941
6942 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6943 intel_panel_use_ssc(dev_priv))
6944 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6945 else
6946 dpll |= PLL_REF_INPUT_DREFCLK;
6947
6948 dpll |= DPLL_VCO_ENABLE;
6949 crtc_state->dpll_hw_state.dpll = dpll;
6950 }
6951
6952 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6953 {
6954 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6955 enum pipe pipe = intel_crtc->pipe;
6956 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6957 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6958 uint32_t crtc_vtotal, crtc_vblank_end;
6959 int vsyncshift = 0;
6960
6961 /* We need to be careful not to changed the adjusted mode, for otherwise
6962 * the hw state checker will get angry at the mismatch. */
6963 crtc_vtotal = adjusted_mode->crtc_vtotal;
6964 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6965
6966 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6967 /* the chip adds 2 halflines automatically */
6968 crtc_vtotal -= 1;
6969 crtc_vblank_end -= 1;
6970
6971 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6972 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6973 else
6974 vsyncshift = adjusted_mode->crtc_hsync_start -
6975 adjusted_mode->crtc_htotal / 2;
6976 if (vsyncshift < 0)
6977 vsyncshift += adjusted_mode->crtc_htotal;
6978 }
6979
6980 if (INTEL_GEN(dev_priv) > 3)
6981 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6982
6983 I915_WRITE(HTOTAL(cpu_transcoder),
6984 (adjusted_mode->crtc_hdisplay - 1) |
6985 ((adjusted_mode->crtc_htotal - 1) << 16));
6986 I915_WRITE(HBLANK(cpu_transcoder),
6987 (adjusted_mode->crtc_hblank_start - 1) |
6988 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6989 I915_WRITE(HSYNC(cpu_transcoder),
6990 (adjusted_mode->crtc_hsync_start - 1) |
6991 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6992
6993 I915_WRITE(VTOTAL(cpu_transcoder),
6994 (adjusted_mode->crtc_vdisplay - 1) |
6995 ((crtc_vtotal - 1) << 16));
6996 I915_WRITE(VBLANK(cpu_transcoder),
6997 (adjusted_mode->crtc_vblank_start - 1) |
6998 ((crtc_vblank_end - 1) << 16));
6999 I915_WRITE(VSYNC(cpu_transcoder),
7000 (adjusted_mode->crtc_vsync_start - 1) |
7001 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7002
7003 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7004 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7005 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7006 * bits. */
7007 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
7008 (pipe == PIPE_B || pipe == PIPE_C))
7009 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7010
7011 }
7012
7013 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7014 {
7015 struct drm_device *dev = intel_crtc->base.dev;
7016 struct drm_i915_private *dev_priv = to_i915(dev);
7017 enum pipe pipe = intel_crtc->pipe;
7018
7019 /* pipesrc controls the size that is scaled from, which should
7020 * always be the user's requested size.
7021 */
7022 I915_WRITE(PIPESRC(pipe),
7023 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7024 (intel_crtc->config->pipe_src_h - 1));
7025 }
7026
7027 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7028 struct intel_crtc_state *pipe_config)
7029 {
7030 struct drm_device *dev = crtc->base.dev;
7031 struct drm_i915_private *dev_priv = to_i915(dev);
7032 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7033 uint32_t tmp;
7034
7035 tmp = I915_READ(HTOTAL(cpu_transcoder));
7036 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7037 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7038 tmp = I915_READ(HBLANK(cpu_transcoder));
7039 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7040 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7041 tmp = I915_READ(HSYNC(cpu_transcoder));
7042 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7043 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7044
7045 tmp = I915_READ(VTOTAL(cpu_transcoder));
7046 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7047 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7048 tmp = I915_READ(VBLANK(cpu_transcoder));
7049 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7050 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7051 tmp = I915_READ(VSYNC(cpu_transcoder));
7052 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7053 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7054
7055 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7056 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7057 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7058 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7059 }
7060 }
7061
7062 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7063 struct intel_crtc_state *pipe_config)
7064 {
7065 struct drm_device *dev = crtc->base.dev;
7066 struct drm_i915_private *dev_priv = to_i915(dev);
7067 u32 tmp;
7068
7069 tmp = I915_READ(PIPESRC(crtc->pipe));
7070 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7071 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7072
7073 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7074 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7075 }
7076
7077 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7078 struct intel_crtc_state *pipe_config)
7079 {
7080 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7081 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7082 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7083 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7084
7085 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7086 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7087 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7088 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7089
7090 mode->flags = pipe_config->base.adjusted_mode.flags;
7091 mode->type = DRM_MODE_TYPE_DRIVER;
7092
7093 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7094
7095 mode->hsync = drm_mode_hsync(mode);
7096 mode->vrefresh = drm_mode_vrefresh(mode);
7097 drm_mode_set_name(mode);
7098 }
7099
7100 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7101 {
7102 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7103 uint32_t pipeconf;
7104
7105 pipeconf = 0;
7106
7107 /* we keep both pipes enabled on 830 */
7108 if (IS_I830(dev_priv))
7109 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7110
7111 if (intel_crtc->config->double_wide)
7112 pipeconf |= PIPECONF_DOUBLE_WIDE;
7113
7114 /* only g4x and later have fancy bpc/dither controls */
7115 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7116 IS_CHERRYVIEW(dev_priv)) {
7117 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7118 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7119 pipeconf |= PIPECONF_DITHER_EN |
7120 PIPECONF_DITHER_TYPE_SP;
7121
7122 switch (intel_crtc->config->pipe_bpp) {
7123 case 18:
7124 pipeconf |= PIPECONF_6BPC;
7125 break;
7126 case 24:
7127 pipeconf |= PIPECONF_8BPC;
7128 break;
7129 case 30:
7130 pipeconf |= PIPECONF_10BPC;
7131 break;
7132 default:
7133 /* Case prevented by intel_choose_pipe_bpp_dither. */
7134 BUG();
7135 }
7136 }
7137
7138 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7139 if (INTEL_GEN(dev_priv) < 4 ||
7140 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7141 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7142 else
7143 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7144 } else
7145 pipeconf |= PIPECONF_PROGRESSIVE;
7146
7147 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7148 intel_crtc->config->limited_color_range)
7149 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7150
7151 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7152 POSTING_READ(PIPECONF(intel_crtc->pipe));
7153 }
7154
7155 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7156 struct intel_crtc_state *crtc_state)
7157 {
7158 struct drm_device *dev = crtc->base.dev;
7159 struct drm_i915_private *dev_priv = to_i915(dev);
7160 const struct intel_limit *limit;
7161 int refclk = 48000;
7162
7163 memset(&crtc_state->dpll_hw_state, 0,
7164 sizeof(crtc_state->dpll_hw_state));
7165
7166 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7167 if (intel_panel_use_ssc(dev_priv)) {
7168 refclk = dev_priv->vbt.lvds_ssc_freq;
7169 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7170 }
7171
7172 limit = &intel_limits_i8xx_lvds;
7173 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7174 limit = &intel_limits_i8xx_dvo;
7175 } else {
7176 limit = &intel_limits_i8xx_dac;
7177 }
7178
7179 if (!crtc_state->clock_set &&
7180 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7181 refclk, NULL, &crtc_state->dpll)) {
7182 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7183 return -EINVAL;
7184 }
7185
7186 i8xx_compute_dpll(crtc, crtc_state, NULL);
7187
7188 return 0;
7189 }
7190
7191 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7192 struct intel_crtc_state *crtc_state)
7193 {
7194 struct drm_device *dev = crtc->base.dev;
7195 struct drm_i915_private *dev_priv = to_i915(dev);
7196 const struct intel_limit *limit;
7197 int refclk = 96000;
7198
7199 memset(&crtc_state->dpll_hw_state, 0,
7200 sizeof(crtc_state->dpll_hw_state));
7201
7202 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7203 if (intel_panel_use_ssc(dev_priv)) {
7204 refclk = dev_priv->vbt.lvds_ssc_freq;
7205 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7206 }
7207
7208 if (intel_is_dual_link_lvds(dev))
7209 limit = &intel_limits_g4x_dual_channel_lvds;
7210 else
7211 limit = &intel_limits_g4x_single_channel_lvds;
7212 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7213 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7214 limit = &intel_limits_g4x_hdmi;
7215 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7216 limit = &intel_limits_g4x_sdvo;
7217 } else {
7218 /* The option is for other outputs */
7219 limit = &intel_limits_i9xx_sdvo;
7220 }
7221
7222 if (!crtc_state->clock_set &&
7223 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7224 refclk, NULL, &crtc_state->dpll)) {
7225 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7226 return -EINVAL;
7227 }
7228
7229 i9xx_compute_dpll(crtc, crtc_state, NULL);
7230
7231 return 0;
7232 }
7233
7234 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7235 struct intel_crtc_state *crtc_state)
7236 {
7237 struct drm_device *dev = crtc->base.dev;
7238 struct drm_i915_private *dev_priv = to_i915(dev);
7239 const struct intel_limit *limit;
7240 int refclk = 96000;
7241
7242 memset(&crtc_state->dpll_hw_state, 0,
7243 sizeof(crtc_state->dpll_hw_state));
7244
7245 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7246 if (intel_panel_use_ssc(dev_priv)) {
7247 refclk = dev_priv->vbt.lvds_ssc_freq;
7248 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7249 }
7250
7251 limit = &intel_limits_pineview_lvds;
7252 } else {
7253 limit = &intel_limits_pineview_sdvo;
7254 }
7255
7256 if (!crtc_state->clock_set &&
7257 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7258 refclk, NULL, &crtc_state->dpll)) {
7259 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7260 return -EINVAL;
7261 }
7262
7263 i9xx_compute_dpll(crtc, crtc_state, NULL);
7264
7265 return 0;
7266 }
7267
7268 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7269 struct intel_crtc_state *crtc_state)
7270 {
7271 struct drm_device *dev = crtc->base.dev;
7272 struct drm_i915_private *dev_priv = to_i915(dev);
7273 const struct intel_limit *limit;
7274 int refclk = 96000;
7275
7276 memset(&crtc_state->dpll_hw_state, 0,
7277 sizeof(crtc_state->dpll_hw_state));
7278
7279 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7280 if (intel_panel_use_ssc(dev_priv)) {
7281 refclk = dev_priv->vbt.lvds_ssc_freq;
7282 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7283 }
7284
7285 limit = &intel_limits_i9xx_lvds;
7286 } else {
7287 limit = &intel_limits_i9xx_sdvo;
7288 }
7289
7290 if (!crtc_state->clock_set &&
7291 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7292 refclk, NULL, &crtc_state->dpll)) {
7293 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7294 return -EINVAL;
7295 }
7296
7297 i9xx_compute_dpll(crtc, crtc_state, NULL);
7298
7299 return 0;
7300 }
7301
7302 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7303 struct intel_crtc_state *crtc_state)
7304 {
7305 int refclk = 100000;
7306 const struct intel_limit *limit = &intel_limits_chv;
7307
7308 memset(&crtc_state->dpll_hw_state, 0,
7309 sizeof(crtc_state->dpll_hw_state));
7310
7311 if (!crtc_state->clock_set &&
7312 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7313 refclk, NULL, &crtc_state->dpll)) {
7314 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7315 return -EINVAL;
7316 }
7317
7318 chv_compute_dpll(crtc, crtc_state);
7319
7320 return 0;
7321 }
7322
7323 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7324 struct intel_crtc_state *crtc_state)
7325 {
7326 int refclk = 100000;
7327 const struct intel_limit *limit = &intel_limits_vlv;
7328
7329 memset(&crtc_state->dpll_hw_state, 0,
7330 sizeof(crtc_state->dpll_hw_state));
7331
7332 if (!crtc_state->clock_set &&
7333 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7334 refclk, NULL, &crtc_state->dpll)) {
7335 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7336 return -EINVAL;
7337 }
7338
7339 vlv_compute_dpll(crtc, crtc_state);
7340
7341 return 0;
7342 }
7343
7344 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7345 struct intel_crtc_state *pipe_config)
7346 {
7347 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7348 uint32_t tmp;
7349
7350 if (INTEL_GEN(dev_priv) <= 3 &&
7351 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7352 return;
7353
7354 tmp = I915_READ(PFIT_CONTROL);
7355 if (!(tmp & PFIT_ENABLE))
7356 return;
7357
7358 /* Check whether the pfit is attached to our pipe. */
7359 if (INTEL_GEN(dev_priv) < 4) {
7360 if (crtc->pipe != PIPE_B)
7361 return;
7362 } else {
7363 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7364 return;
7365 }
7366
7367 pipe_config->gmch_pfit.control = tmp;
7368 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7369 }
7370
7371 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7372 struct intel_crtc_state *pipe_config)
7373 {
7374 struct drm_device *dev = crtc->base.dev;
7375 struct drm_i915_private *dev_priv = to_i915(dev);
7376 int pipe = pipe_config->cpu_transcoder;
7377 struct dpll clock;
7378 u32 mdiv;
7379 int refclk = 100000;
7380
7381 /* In case of DSI, DPLL will not be used */
7382 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7383 return;
7384
7385 mutex_lock(&dev_priv->sb_lock);
7386 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7387 mutex_unlock(&dev_priv->sb_lock);
7388
7389 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7390 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7391 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7392 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7393 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7394
7395 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7396 }
7397
7398 static void
7399 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7400 struct intel_initial_plane_config *plane_config)
7401 {
7402 struct drm_device *dev = crtc->base.dev;
7403 struct drm_i915_private *dev_priv = to_i915(dev);
7404 u32 val, base, offset;
7405 int pipe = crtc->pipe, plane = crtc->plane;
7406 int fourcc, pixel_format;
7407 unsigned int aligned_height;
7408 struct drm_framebuffer *fb;
7409 struct intel_framebuffer *intel_fb;
7410
7411 val = I915_READ(DSPCNTR(plane));
7412 if (!(val & DISPLAY_PLANE_ENABLE))
7413 return;
7414
7415 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7416 if (!intel_fb) {
7417 DRM_DEBUG_KMS("failed to alloc fb\n");
7418 return;
7419 }
7420
7421 fb = &intel_fb->base;
7422
7423 fb->dev = dev;
7424
7425 if (INTEL_GEN(dev_priv) >= 4) {
7426 if (val & DISPPLANE_TILED) {
7427 plane_config->tiling = I915_TILING_X;
7428 fb->modifier = I915_FORMAT_MOD_X_TILED;
7429 }
7430 }
7431
7432 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7433 fourcc = i9xx_format_to_fourcc(pixel_format);
7434 fb->format = drm_format_info(fourcc);
7435
7436 if (INTEL_GEN(dev_priv) >= 4) {
7437 if (plane_config->tiling)
7438 offset = I915_READ(DSPTILEOFF(plane));
7439 else
7440 offset = I915_READ(DSPLINOFF(plane));
7441 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7442 } else {
7443 base = I915_READ(DSPADDR(plane));
7444 }
7445 plane_config->base = base;
7446
7447 val = I915_READ(PIPESRC(pipe));
7448 fb->width = ((val >> 16) & 0xfff) + 1;
7449 fb->height = ((val >> 0) & 0xfff) + 1;
7450
7451 val = I915_READ(DSPSTRIDE(pipe));
7452 fb->pitches[0] = val & 0xffffffc0;
7453
7454 aligned_height = intel_fb_align_height(fb, 0, fb->height);
7455
7456 plane_config->size = fb->pitches[0] * aligned_height;
7457
7458 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7459 pipe_name(pipe), plane, fb->width, fb->height,
7460 fb->format->cpp[0] * 8, base, fb->pitches[0],
7461 plane_config->size);
7462
7463 plane_config->fb = intel_fb;
7464 }
7465
7466 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7467 struct intel_crtc_state *pipe_config)
7468 {
7469 struct drm_device *dev = crtc->base.dev;
7470 struct drm_i915_private *dev_priv = to_i915(dev);
7471 int pipe = pipe_config->cpu_transcoder;
7472 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7473 struct dpll clock;
7474 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7475 int refclk = 100000;
7476
7477 /* In case of DSI, DPLL will not be used */
7478 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7479 return;
7480
7481 mutex_lock(&dev_priv->sb_lock);
7482 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7483 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7484 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7485 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7486 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7487 mutex_unlock(&dev_priv->sb_lock);
7488
7489 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7490 clock.m2 = (pll_dw0 & 0xff) << 22;
7491 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7492 clock.m2 |= pll_dw2 & 0x3fffff;
7493 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7494 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7495 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7496
7497 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7498 }
7499
7500 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7501 struct intel_crtc_state *pipe_config)
7502 {
7503 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7504 enum intel_display_power_domain power_domain;
7505 uint32_t tmp;
7506 bool ret;
7507
7508 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7509 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7510 return false;
7511
7512 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7513 pipe_config->shared_dpll = NULL;
7514
7515 ret = false;
7516
7517 tmp = I915_READ(PIPECONF(crtc->pipe));
7518 if (!(tmp & PIPECONF_ENABLE))
7519 goto out;
7520
7521 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7522 IS_CHERRYVIEW(dev_priv)) {
7523 switch (tmp & PIPECONF_BPC_MASK) {
7524 case PIPECONF_6BPC:
7525 pipe_config->pipe_bpp = 18;
7526 break;
7527 case PIPECONF_8BPC:
7528 pipe_config->pipe_bpp = 24;
7529 break;
7530 case PIPECONF_10BPC:
7531 pipe_config->pipe_bpp = 30;
7532 break;
7533 default:
7534 break;
7535 }
7536 }
7537
7538 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7539 (tmp & PIPECONF_COLOR_RANGE_SELECT))
7540 pipe_config->limited_color_range = true;
7541
7542 if (INTEL_GEN(dev_priv) < 4)
7543 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7544
7545 intel_get_pipe_timings(crtc, pipe_config);
7546 intel_get_pipe_src_size(crtc, pipe_config);
7547
7548 i9xx_get_pfit_config(crtc, pipe_config);
7549
7550 if (INTEL_GEN(dev_priv) >= 4) {
7551 /* No way to read it out on pipes B and C */
7552 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7553 tmp = dev_priv->chv_dpll_md[crtc->pipe];
7554 else
7555 tmp = I915_READ(DPLL_MD(crtc->pipe));
7556 pipe_config->pixel_multiplier =
7557 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7558 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7559 pipe_config->dpll_hw_state.dpll_md = tmp;
7560 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7561 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7562 tmp = I915_READ(DPLL(crtc->pipe));
7563 pipe_config->pixel_multiplier =
7564 ((tmp & SDVO_MULTIPLIER_MASK)
7565 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7566 } else {
7567 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7568 * port and will be fixed up in the encoder->get_config
7569 * function. */
7570 pipe_config->pixel_multiplier = 1;
7571 }
7572 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7573 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7574 /*
7575 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7576 * on 830. Filter it out here so that we don't
7577 * report errors due to that.
7578 */
7579 if (IS_I830(dev_priv))
7580 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7581
7582 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7583 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7584 } else {
7585 /* Mask out read-only status bits. */
7586 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7587 DPLL_PORTC_READY_MASK |
7588 DPLL_PORTB_READY_MASK);
7589 }
7590
7591 if (IS_CHERRYVIEW(dev_priv))
7592 chv_crtc_clock_get(crtc, pipe_config);
7593 else if (IS_VALLEYVIEW(dev_priv))
7594 vlv_crtc_clock_get(crtc, pipe_config);
7595 else
7596 i9xx_crtc_clock_get(crtc, pipe_config);
7597
7598 /*
7599 * Normally the dotclock is filled in by the encoder .get_config()
7600 * but in case the pipe is enabled w/o any ports we need a sane
7601 * default.
7602 */
7603 pipe_config->base.adjusted_mode.crtc_clock =
7604 pipe_config->port_clock / pipe_config->pixel_multiplier;
7605
7606 ret = true;
7607
7608 out:
7609 intel_display_power_put(dev_priv, power_domain);
7610
7611 return ret;
7612 }
7613
7614 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7615 {
7616 struct intel_encoder *encoder;
7617 int i;
7618 u32 val, final;
7619 bool has_lvds = false;
7620 bool has_cpu_edp = false;
7621 bool has_panel = false;
7622 bool has_ck505 = false;
7623 bool can_ssc = false;
7624 bool using_ssc_source = false;
7625
7626 /* We need to take the global config into account */
7627 for_each_intel_encoder(&dev_priv->drm, encoder) {
7628 switch (encoder->type) {
7629 case INTEL_OUTPUT_LVDS:
7630 has_panel = true;
7631 has_lvds = true;
7632 break;
7633 case INTEL_OUTPUT_EDP:
7634 has_panel = true;
7635 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7636 has_cpu_edp = true;
7637 break;
7638 default:
7639 break;
7640 }
7641 }
7642
7643 if (HAS_PCH_IBX(dev_priv)) {
7644 has_ck505 = dev_priv->vbt.display_clock_mode;
7645 can_ssc = has_ck505;
7646 } else {
7647 has_ck505 = false;
7648 can_ssc = true;
7649 }
7650
7651 /* Check if any DPLLs are using the SSC source */
7652 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7653 u32 temp = I915_READ(PCH_DPLL(i));
7654
7655 if (!(temp & DPLL_VCO_ENABLE))
7656 continue;
7657
7658 if ((temp & PLL_REF_INPUT_MASK) ==
7659 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7660 using_ssc_source = true;
7661 break;
7662 }
7663 }
7664
7665 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7666 has_panel, has_lvds, has_ck505, using_ssc_source);
7667
7668 /* Ironlake: try to setup display ref clock before DPLL
7669 * enabling. This is only under driver's control after
7670 * PCH B stepping, previous chipset stepping should be
7671 * ignoring this setting.
7672 */
7673 val = I915_READ(PCH_DREF_CONTROL);
7674
7675 /* As we must carefully and slowly disable/enable each source in turn,
7676 * compute the final state we want first and check if we need to
7677 * make any changes at all.
7678 */
7679 final = val;
7680 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7681 if (has_ck505)
7682 final |= DREF_NONSPREAD_CK505_ENABLE;
7683 else
7684 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7685
7686 final &= ~DREF_SSC_SOURCE_MASK;
7687 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7688 final &= ~DREF_SSC1_ENABLE;
7689
7690 if (has_panel) {
7691 final |= DREF_SSC_SOURCE_ENABLE;
7692
7693 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7694 final |= DREF_SSC1_ENABLE;
7695
7696 if (has_cpu_edp) {
7697 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7698 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7699 else
7700 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7701 } else
7702 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7703 } else if (using_ssc_source) {
7704 final |= DREF_SSC_SOURCE_ENABLE;
7705 final |= DREF_SSC1_ENABLE;
7706 }
7707
7708 if (final == val)
7709 return;
7710
7711 /* Always enable nonspread source */
7712 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7713
7714 if (has_ck505)
7715 val |= DREF_NONSPREAD_CK505_ENABLE;
7716 else
7717 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7718
7719 if (has_panel) {
7720 val &= ~DREF_SSC_SOURCE_MASK;
7721 val |= DREF_SSC_SOURCE_ENABLE;
7722
7723 /* SSC must be turned on before enabling the CPU output */
7724 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7725 DRM_DEBUG_KMS("Using SSC on panel\n");
7726 val |= DREF_SSC1_ENABLE;
7727 } else
7728 val &= ~DREF_SSC1_ENABLE;
7729
7730 /* Get SSC going before enabling the outputs */
7731 I915_WRITE(PCH_DREF_CONTROL, val);
7732 POSTING_READ(PCH_DREF_CONTROL);
7733 udelay(200);
7734
7735 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7736
7737 /* Enable CPU source on CPU attached eDP */
7738 if (has_cpu_edp) {
7739 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7740 DRM_DEBUG_KMS("Using SSC on eDP\n");
7741 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7742 } else
7743 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7744 } else
7745 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7746
7747 I915_WRITE(PCH_DREF_CONTROL, val);
7748 POSTING_READ(PCH_DREF_CONTROL);
7749 udelay(200);
7750 } else {
7751 DRM_DEBUG_KMS("Disabling CPU source output\n");
7752
7753 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7754
7755 /* Turn off CPU output */
7756 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7757
7758 I915_WRITE(PCH_DREF_CONTROL, val);
7759 POSTING_READ(PCH_DREF_CONTROL);
7760 udelay(200);
7761
7762 if (!using_ssc_source) {
7763 DRM_DEBUG_KMS("Disabling SSC source\n");
7764
7765 /* Turn off the SSC source */
7766 val &= ~DREF_SSC_SOURCE_MASK;
7767 val |= DREF_SSC_SOURCE_DISABLE;
7768
7769 /* Turn off SSC1 */
7770 val &= ~DREF_SSC1_ENABLE;
7771
7772 I915_WRITE(PCH_DREF_CONTROL, val);
7773 POSTING_READ(PCH_DREF_CONTROL);
7774 udelay(200);
7775 }
7776 }
7777
7778 BUG_ON(val != final);
7779 }
7780
7781 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7782 {
7783 uint32_t tmp;
7784
7785 tmp = I915_READ(SOUTH_CHICKEN2);
7786 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7787 I915_WRITE(SOUTH_CHICKEN2, tmp);
7788
7789 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7790 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7791 DRM_ERROR("FDI mPHY reset assert timeout\n");
7792
7793 tmp = I915_READ(SOUTH_CHICKEN2);
7794 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7795 I915_WRITE(SOUTH_CHICKEN2, tmp);
7796
7797 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7798 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7799 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7800 }
7801
7802 /* WaMPhyProgramming:hsw */
7803 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7804 {
7805 uint32_t tmp;
7806
7807 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7808 tmp &= ~(0xFF << 24);
7809 tmp |= (0x12 << 24);
7810 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7811
7812 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7813 tmp |= (1 << 11);
7814 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7815
7816 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7817 tmp |= (1 << 11);
7818 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7819
7820 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7821 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7822 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7823
7824 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7825 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7826 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7827
7828 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7829 tmp &= ~(7 << 13);
7830 tmp |= (5 << 13);
7831 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7832
7833 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7834 tmp &= ~(7 << 13);
7835 tmp |= (5 << 13);
7836 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7837
7838 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7839 tmp &= ~0xFF;
7840 tmp |= 0x1C;
7841 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7842
7843 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7844 tmp &= ~0xFF;
7845 tmp |= 0x1C;
7846 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7847
7848 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7849 tmp &= ~(0xFF << 16);
7850 tmp |= (0x1C << 16);
7851 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7852
7853 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7854 tmp &= ~(0xFF << 16);
7855 tmp |= (0x1C << 16);
7856 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7857
7858 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7859 tmp |= (1 << 27);
7860 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7861
7862 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7863 tmp |= (1 << 27);
7864 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7865
7866 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7867 tmp &= ~(0xF << 28);
7868 tmp |= (4 << 28);
7869 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7870
7871 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7872 tmp &= ~(0xF << 28);
7873 tmp |= (4 << 28);
7874 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7875 }
7876
7877 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7878 * Programming" based on the parameters passed:
7879 * - Sequence to enable CLKOUT_DP
7880 * - Sequence to enable CLKOUT_DP without spread
7881 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7882 */
7883 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7884 bool with_spread, bool with_fdi)
7885 {
7886 uint32_t reg, tmp;
7887
7888 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7889 with_spread = true;
7890 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7891 with_fdi, "LP PCH doesn't have FDI\n"))
7892 with_fdi = false;
7893
7894 mutex_lock(&dev_priv->sb_lock);
7895
7896 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7897 tmp &= ~SBI_SSCCTL_DISABLE;
7898 tmp |= SBI_SSCCTL_PATHALT;
7899 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7900
7901 udelay(24);
7902
7903 if (with_spread) {
7904 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7905 tmp &= ~SBI_SSCCTL_PATHALT;
7906 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7907
7908 if (with_fdi) {
7909 lpt_reset_fdi_mphy(dev_priv);
7910 lpt_program_fdi_mphy(dev_priv);
7911 }
7912 }
7913
7914 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7915 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7916 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7917 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7918
7919 mutex_unlock(&dev_priv->sb_lock);
7920 }
7921
7922 /* Sequence to disable CLKOUT_DP */
7923 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7924 {
7925 uint32_t reg, tmp;
7926
7927 mutex_lock(&dev_priv->sb_lock);
7928
7929 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7930 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7931 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7932 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7933
7934 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7935 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7936 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7937 tmp |= SBI_SSCCTL_PATHALT;
7938 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7939 udelay(32);
7940 }
7941 tmp |= SBI_SSCCTL_DISABLE;
7942 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7943 }
7944
7945 mutex_unlock(&dev_priv->sb_lock);
7946 }
7947
7948 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7949
7950 static const uint16_t sscdivintphase[] = {
7951 [BEND_IDX( 50)] = 0x3B23,
7952 [BEND_IDX( 45)] = 0x3B23,
7953 [BEND_IDX( 40)] = 0x3C23,
7954 [BEND_IDX( 35)] = 0x3C23,
7955 [BEND_IDX( 30)] = 0x3D23,
7956 [BEND_IDX( 25)] = 0x3D23,
7957 [BEND_IDX( 20)] = 0x3E23,
7958 [BEND_IDX( 15)] = 0x3E23,
7959 [BEND_IDX( 10)] = 0x3F23,
7960 [BEND_IDX( 5)] = 0x3F23,
7961 [BEND_IDX( 0)] = 0x0025,
7962 [BEND_IDX( -5)] = 0x0025,
7963 [BEND_IDX(-10)] = 0x0125,
7964 [BEND_IDX(-15)] = 0x0125,
7965 [BEND_IDX(-20)] = 0x0225,
7966 [BEND_IDX(-25)] = 0x0225,
7967 [BEND_IDX(-30)] = 0x0325,
7968 [BEND_IDX(-35)] = 0x0325,
7969 [BEND_IDX(-40)] = 0x0425,
7970 [BEND_IDX(-45)] = 0x0425,
7971 [BEND_IDX(-50)] = 0x0525,
7972 };
7973
7974 /*
7975 * Bend CLKOUT_DP
7976 * steps -50 to 50 inclusive, in steps of 5
7977 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7978 * change in clock period = -(steps / 10) * 5.787 ps
7979 */
7980 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
7981 {
7982 uint32_t tmp;
7983 int idx = BEND_IDX(steps);
7984
7985 if (WARN_ON(steps % 5 != 0))
7986 return;
7987
7988 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
7989 return;
7990
7991 mutex_lock(&dev_priv->sb_lock);
7992
7993 if (steps % 10 != 0)
7994 tmp = 0xAAAAAAAB;
7995 else
7996 tmp = 0x00000000;
7997 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
7998
7999 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8000 tmp &= 0xffff0000;
8001 tmp |= sscdivintphase[idx];
8002 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8003
8004 mutex_unlock(&dev_priv->sb_lock);
8005 }
8006
8007 #undef BEND_IDX
8008
8009 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
8010 {
8011 struct intel_encoder *encoder;
8012 bool has_vga = false;
8013
8014 for_each_intel_encoder(&dev_priv->drm, encoder) {
8015 switch (encoder->type) {
8016 case INTEL_OUTPUT_ANALOG:
8017 has_vga = true;
8018 break;
8019 default:
8020 break;
8021 }
8022 }
8023
8024 if (has_vga) {
8025 lpt_bend_clkout_dp(dev_priv, 0);
8026 lpt_enable_clkout_dp(dev_priv, true, true);
8027 } else {
8028 lpt_disable_clkout_dp(dev_priv);
8029 }
8030 }
8031
8032 /*
8033 * Initialize reference clocks when the driver loads
8034 */
8035 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8036 {
8037 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8038 ironlake_init_pch_refclk(dev_priv);
8039 else if (HAS_PCH_LPT(dev_priv))
8040 lpt_init_pch_refclk(dev_priv);
8041 }
8042
8043 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8044 {
8045 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8046 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8047 int pipe = intel_crtc->pipe;
8048 uint32_t val;
8049
8050 val = 0;
8051
8052 switch (intel_crtc->config->pipe_bpp) {
8053 case 18:
8054 val |= PIPECONF_6BPC;
8055 break;
8056 case 24:
8057 val |= PIPECONF_8BPC;
8058 break;
8059 case 30:
8060 val |= PIPECONF_10BPC;
8061 break;
8062 case 36:
8063 val |= PIPECONF_12BPC;
8064 break;
8065 default:
8066 /* Case prevented by intel_choose_pipe_bpp_dither. */
8067 BUG();
8068 }
8069
8070 if (intel_crtc->config->dither)
8071 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8072
8073 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8074 val |= PIPECONF_INTERLACED_ILK;
8075 else
8076 val |= PIPECONF_PROGRESSIVE;
8077
8078 if (intel_crtc->config->limited_color_range)
8079 val |= PIPECONF_COLOR_RANGE_SELECT;
8080
8081 I915_WRITE(PIPECONF(pipe), val);
8082 POSTING_READ(PIPECONF(pipe));
8083 }
8084
8085 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8086 {
8087 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8089 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8090 u32 val = 0;
8091
8092 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8093 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8094
8095 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8096 val |= PIPECONF_INTERLACED_ILK;
8097 else
8098 val |= PIPECONF_PROGRESSIVE;
8099
8100 I915_WRITE(PIPECONF(cpu_transcoder), val);
8101 POSTING_READ(PIPECONF(cpu_transcoder));
8102 }
8103
8104 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8105 {
8106 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8108 struct intel_crtc_state *config = intel_crtc->config;
8109
8110 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8111 u32 val = 0;
8112
8113 switch (intel_crtc->config->pipe_bpp) {
8114 case 18:
8115 val |= PIPEMISC_DITHER_6_BPC;
8116 break;
8117 case 24:
8118 val |= PIPEMISC_DITHER_8_BPC;
8119 break;
8120 case 30:
8121 val |= PIPEMISC_DITHER_10_BPC;
8122 break;
8123 case 36:
8124 val |= PIPEMISC_DITHER_12_BPC;
8125 break;
8126 default:
8127 /* Case prevented by pipe_config_set_bpp. */
8128 BUG();
8129 }
8130
8131 if (intel_crtc->config->dither)
8132 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8133
8134 if (config->ycbcr420) {
8135 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV |
8136 PIPEMISC_YUV420_ENABLE |
8137 PIPEMISC_YUV420_MODE_FULL_BLEND;
8138 }
8139
8140 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8141 }
8142 }
8143
8144 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8145 {
8146 /*
8147 * Account for spread spectrum to avoid
8148 * oversubscribing the link. Max center spread
8149 * is 2.5%; use 5% for safety's sake.
8150 */
8151 u32 bps = target_clock * bpp * 21 / 20;
8152 return DIV_ROUND_UP(bps, link_bw * 8);
8153 }
8154
8155 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8156 {
8157 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8158 }
8159
8160 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8161 struct intel_crtc_state *crtc_state,
8162 struct dpll *reduced_clock)
8163 {
8164 struct drm_crtc *crtc = &intel_crtc->base;
8165 struct drm_device *dev = crtc->dev;
8166 struct drm_i915_private *dev_priv = to_i915(dev);
8167 u32 dpll, fp, fp2;
8168 int factor;
8169
8170 /* Enable autotuning of the PLL clock (if permissible) */
8171 factor = 21;
8172 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8173 if ((intel_panel_use_ssc(dev_priv) &&
8174 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8175 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8176 factor = 25;
8177 } else if (crtc_state->sdvo_tv_clock)
8178 factor = 20;
8179
8180 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8181
8182 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8183 fp |= FP_CB_TUNE;
8184
8185 if (reduced_clock) {
8186 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8187
8188 if (reduced_clock->m < factor * reduced_clock->n)
8189 fp2 |= FP_CB_TUNE;
8190 } else {
8191 fp2 = fp;
8192 }
8193
8194 dpll = 0;
8195
8196 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8197 dpll |= DPLLB_MODE_LVDS;
8198 else
8199 dpll |= DPLLB_MODE_DAC_SERIAL;
8200
8201 dpll |= (crtc_state->pixel_multiplier - 1)
8202 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8203
8204 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8205 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8206 dpll |= DPLL_SDVO_HIGH_SPEED;
8207
8208 if (intel_crtc_has_dp_encoder(crtc_state))
8209 dpll |= DPLL_SDVO_HIGH_SPEED;
8210
8211 /*
8212 * The high speed IO clock is only really required for
8213 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8214 * possible to share the DPLL between CRT and HDMI. Enabling
8215 * the clock needlessly does no real harm, except use up a
8216 * bit of power potentially.
8217 *
8218 * We'll limit this to IVB with 3 pipes, since it has only two
8219 * DPLLs and so DPLL sharing is the only way to get three pipes
8220 * driving PCH ports at the same time. On SNB we could do this,
8221 * and potentially avoid enabling the second DPLL, but it's not
8222 * clear if it''s a win or loss power wise. No point in doing
8223 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8224 */
8225 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8226 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8227 dpll |= DPLL_SDVO_HIGH_SPEED;
8228
8229 /* compute bitmask from p1 value */
8230 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8231 /* also FPA1 */
8232 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8233
8234 switch (crtc_state->dpll.p2) {
8235 case 5:
8236 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8237 break;
8238 case 7:
8239 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8240 break;
8241 case 10:
8242 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8243 break;
8244 case 14:
8245 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8246 break;
8247 }
8248
8249 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8250 intel_panel_use_ssc(dev_priv))
8251 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8252 else
8253 dpll |= PLL_REF_INPUT_DREFCLK;
8254
8255 dpll |= DPLL_VCO_ENABLE;
8256
8257 crtc_state->dpll_hw_state.dpll = dpll;
8258 crtc_state->dpll_hw_state.fp0 = fp;
8259 crtc_state->dpll_hw_state.fp1 = fp2;
8260 }
8261
8262 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8263 struct intel_crtc_state *crtc_state)
8264 {
8265 struct drm_device *dev = crtc->base.dev;
8266 struct drm_i915_private *dev_priv = to_i915(dev);
8267 const struct intel_limit *limit;
8268 int refclk = 120000;
8269
8270 memset(&crtc_state->dpll_hw_state, 0,
8271 sizeof(crtc_state->dpll_hw_state));
8272
8273 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8274 if (!crtc_state->has_pch_encoder)
8275 return 0;
8276
8277 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8278 if (intel_panel_use_ssc(dev_priv)) {
8279 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8280 dev_priv->vbt.lvds_ssc_freq);
8281 refclk = dev_priv->vbt.lvds_ssc_freq;
8282 }
8283
8284 if (intel_is_dual_link_lvds(dev)) {
8285 if (refclk == 100000)
8286 limit = &intel_limits_ironlake_dual_lvds_100m;
8287 else
8288 limit = &intel_limits_ironlake_dual_lvds;
8289 } else {
8290 if (refclk == 100000)
8291 limit = &intel_limits_ironlake_single_lvds_100m;
8292 else
8293 limit = &intel_limits_ironlake_single_lvds;
8294 }
8295 } else {
8296 limit = &intel_limits_ironlake_dac;
8297 }
8298
8299 if (!crtc_state->clock_set &&
8300 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8301 refclk, NULL, &crtc_state->dpll)) {
8302 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8303 return -EINVAL;
8304 }
8305
8306 ironlake_compute_dpll(crtc, crtc_state, NULL);
8307
8308 if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8309 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8310 pipe_name(crtc->pipe));
8311 return -EINVAL;
8312 }
8313
8314 return 0;
8315 }
8316
8317 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8318 struct intel_link_m_n *m_n)
8319 {
8320 struct drm_device *dev = crtc->base.dev;
8321 struct drm_i915_private *dev_priv = to_i915(dev);
8322 enum pipe pipe = crtc->pipe;
8323
8324 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8325 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8326 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8327 & ~TU_SIZE_MASK;
8328 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8329 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8330 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8331 }
8332
8333 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8334 enum transcoder transcoder,
8335 struct intel_link_m_n *m_n,
8336 struct intel_link_m_n *m2_n2)
8337 {
8338 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8339 enum pipe pipe = crtc->pipe;
8340
8341 if (INTEL_GEN(dev_priv) >= 5) {
8342 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8343 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8344 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8345 & ~TU_SIZE_MASK;
8346 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8347 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8348 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8349 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8350 * gen < 8) and if DRRS is supported (to make sure the
8351 * registers are not unnecessarily read).
8352 */
8353 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8354 crtc->config->has_drrs) {
8355 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8356 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8357 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8358 & ~TU_SIZE_MASK;
8359 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8360 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8361 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8362 }
8363 } else {
8364 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8365 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8366 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8367 & ~TU_SIZE_MASK;
8368 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8369 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8370 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8371 }
8372 }
8373
8374 void intel_dp_get_m_n(struct intel_crtc *crtc,
8375 struct intel_crtc_state *pipe_config)
8376 {
8377 if (pipe_config->has_pch_encoder)
8378 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8379 else
8380 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8381 &pipe_config->dp_m_n,
8382 &pipe_config->dp_m2_n2);
8383 }
8384
8385 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8386 struct intel_crtc_state *pipe_config)
8387 {
8388 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8389 &pipe_config->fdi_m_n, NULL);
8390 }
8391
8392 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8393 struct intel_crtc_state *pipe_config)
8394 {
8395 struct drm_device *dev = crtc->base.dev;
8396 struct drm_i915_private *dev_priv = to_i915(dev);
8397 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8398 uint32_t ps_ctrl = 0;
8399 int id = -1;
8400 int i;
8401
8402 /* find scaler attached to this pipe */
8403 for (i = 0; i < crtc->num_scalers; i++) {
8404 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8405 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8406 id = i;
8407 pipe_config->pch_pfit.enabled = true;
8408 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8409 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8410 break;
8411 }
8412 }
8413
8414 scaler_state->scaler_id = id;
8415 if (id >= 0) {
8416 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8417 } else {
8418 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8419 }
8420 }
8421
8422 static void
8423 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8424 struct intel_initial_plane_config *plane_config)
8425 {
8426 struct drm_device *dev = crtc->base.dev;
8427 struct drm_i915_private *dev_priv = to_i915(dev);
8428 u32 val, base, offset, stride_mult, tiling;
8429 int pipe = crtc->pipe;
8430 int fourcc, pixel_format;
8431 unsigned int aligned_height;
8432 struct drm_framebuffer *fb;
8433 struct intel_framebuffer *intel_fb;
8434
8435 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8436 if (!intel_fb) {
8437 DRM_DEBUG_KMS("failed to alloc fb\n");
8438 return;
8439 }
8440
8441 fb = &intel_fb->base;
8442
8443 fb->dev = dev;
8444
8445 val = I915_READ(PLANE_CTL(pipe, 0));
8446 if (!(val & PLANE_CTL_ENABLE))
8447 goto error;
8448
8449 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8450 fourcc = skl_format_to_fourcc(pixel_format,
8451 val & PLANE_CTL_ORDER_RGBX,
8452 val & PLANE_CTL_ALPHA_MASK);
8453 fb->format = drm_format_info(fourcc);
8454
8455 tiling = val & PLANE_CTL_TILED_MASK;
8456 switch (tiling) {
8457 case PLANE_CTL_TILED_LINEAR:
8458 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8459 break;
8460 case PLANE_CTL_TILED_X:
8461 plane_config->tiling = I915_TILING_X;
8462 fb->modifier = I915_FORMAT_MOD_X_TILED;
8463 break;
8464 case PLANE_CTL_TILED_Y:
8465 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8466 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
8467 else
8468 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8469 break;
8470 case PLANE_CTL_TILED_YF:
8471 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8472 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
8473 else
8474 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8475 break;
8476 default:
8477 MISSING_CASE(tiling);
8478 goto error;
8479 }
8480
8481 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8482 plane_config->base = base;
8483
8484 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8485
8486 val = I915_READ(PLANE_SIZE(pipe, 0));
8487 fb->height = ((val >> 16) & 0xfff) + 1;
8488 fb->width = ((val >> 0) & 0x1fff) + 1;
8489
8490 val = I915_READ(PLANE_STRIDE(pipe, 0));
8491 stride_mult = intel_fb_stride_alignment(fb, 0);
8492 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8493
8494 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8495
8496 plane_config->size = fb->pitches[0] * aligned_height;
8497
8498 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8499 pipe_name(pipe), fb->width, fb->height,
8500 fb->format->cpp[0] * 8, base, fb->pitches[0],
8501 plane_config->size);
8502
8503 plane_config->fb = intel_fb;
8504 return;
8505
8506 error:
8507 kfree(intel_fb);
8508 }
8509
8510 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8511 struct intel_crtc_state *pipe_config)
8512 {
8513 struct drm_device *dev = crtc->base.dev;
8514 struct drm_i915_private *dev_priv = to_i915(dev);
8515 uint32_t tmp;
8516
8517 tmp = I915_READ(PF_CTL(crtc->pipe));
8518
8519 if (tmp & PF_ENABLE) {
8520 pipe_config->pch_pfit.enabled = true;
8521 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8522 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8523
8524 /* We currently do not free assignements of panel fitters on
8525 * ivb/hsw (since we don't use the higher upscaling modes which
8526 * differentiates them) so just WARN about this case for now. */
8527 if (IS_GEN7(dev_priv)) {
8528 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8529 PF_PIPE_SEL_IVB(crtc->pipe));
8530 }
8531 }
8532 }
8533
8534 static void
8535 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8536 struct intel_initial_plane_config *plane_config)
8537 {
8538 struct drm_device *dev = crtc->base.dev;
8539 struct drm_i915_private *dev_priv = to_i915(dev);
8540 u32 val, base, offset;
8541 int pipe = crtc->pipe;
8542 int fourcc, pixel_format;
8543 unsigned int aligned_height;
8544 struct drm_framebuffer *fb;
8545 struct intel_framebuffer *intel_fb;
8546
8547 val = I915_READ(DSPCNTR(pipe));
8548 if (!(val & DISPLAY_PLANE_ENABLE))
8549 return;
8550
8551 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8552 if (!intel_fb) {
8553 DRM_DEBUG_KMS("failed to alloc fb\n");
8554 return;
8555 }
8556
8557 fb = &intel_fb->base;
8558
8559 fb->dev = dev;
8560
8561 if (INTEL_GEN(dev_priv) >= 4) {
8562 if (val & DISPPLANE_TILED) {
8563 plane_config->tiling = I915_TILING_X;
8564 fb->modifier = I915_FORMAT_MOD_X_TILED;
8565 }
8566 }
8567
8568 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8569 fourcc = i9xx_format_to_fourcc(pixel_format);
8570 fb->format = drm_format_info(fourcc);
8571
8572 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8573 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8574 offset = I915_READ(DSPOFFSET(pipe));
8575 } else {
8576 if (plane_config->tiling)
8577 offset = I915_READ(DSPTILEOFF(pipe));
8578 else
8579 offset = I915_READ(DSPLINOFF(pipe));
8580 }
8581 plane_config->base = base;
8582
8583 val = I915_READ(PIPESRC(pipe));
8584 fb->width = ((val >> 16) & 0xfff) + 1;
8585 fb->height = ((val >> 0) & 0xfff) + 1;
8586
8587 val = I915_READ(DSPSTRIDE(pipe));
8588 fb->pitches[0] = val & 0xffffffc0;
8589
8590 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8591
8592 plane_config->size = fb->pitches[0] * aligned_height;
8593
8594 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8595 pipe_name(pipe), fb->width, fb->height,
8596 fb->format->cpp[0] * 8, base, fb->pitches[0],
8597 plane_config->size);
8598
8599 plane_config->fb = intel_fb;
8600 }
8601
8602 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8603 struct intel_crtc_state *pipe_config)
8604 {
8605 struct drm_device *dev = crtc->base.dev;
8606 struct drm_i915_private *dev_priv = to_i915(dev);
8607 enum intel_display_power_domain power_domain;
8608 uint32_t tmp;
8609 bool ret;
8610
8611 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8612 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8613 return false;
8614
8615 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8616 pipe_config->shared_dpll = NULL;
8617
8618 ret = false;
8619 tmp = I915_READ(PIPECONF(crtc->pipe));
8620 if (!(tmp & PIPECONF_ENABLE))
8621 goto out;
8622
8623 switch (tmp & PIPECONF_BPC_MASK) {
8624 case PIPECONF_6BPC:
8625 pipe_config->pipe_bpp = 18;
8626 break;
8627 case PIPECONF_8BPC:
8628 pipe_config->pipe_bpp = 24;
8629 break;
8630 case PIPECONF_10BPC:
8631 pipe_config->pipe_bpp = 30;
8632 break;
8633 case PIPECONF_12BPC:
8634 pipe_config->pipe_bpp = 36;
8635 break;
8636 default:
8637 break;
8638 }
8639
8640 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8641 pipe_config->limited_color_range = true;
8642
8643 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8644 struct intel_shared_dpll *pll;
8645 enum intel_dpll_id pll_id;
8646
8647 pipe_config->has_pch_encoder = true;
8648
8649 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8650 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8651 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8652
8653 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8654
8655 if (HAS_PCH_IBX(dev_priv)) {
8656 /*
8657 * The pipe->pch transcoder and pch transcoder->pll
8658 * mapping is fixed.
8659 */
8660 pll_id = (enum intel_dpll_id) crtc->pipe;
8661 } else {
8662 tmp = I915_READ(PCH_DPLL_SEL);
8663 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8664 pll_id = DPLL_ID_PCH_PLL_B;
8665 else
8666 pll_id= DPLL_ID_PCH_PLL_A;
8667 }
8668
8669 pipe_config->shared_dpll =
8670 intel_get_shared_dpll_by_id(dev_priv, pll_id);
8671 pll = pipe_config->shared_dpll;
8672
8673 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8674 &pipe_config->dpll_hw_state));
8675
8676 tmp = pipe_config->dpll_hw_state.dpll;
8677 pipe_config->pixel_multiplier =
8678 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8679 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8680
8681 ironlake_pch_clock_get(crtc, pipe_config);
8682 } else {
8683 pipe_config->pixel_multiplier = 1;
8684 }
8685
8686 intel_get_pipe_timings(crtc, pipe_config);
8687 intel_get_pipe_src_size(crtc, pipe_config);
8688
8689 ironlake_get_pfit_config(crtc, pipe_config);
8690
8691 ret = true;
8692
8693 out:
8694 intel_display_power_put(dev_priv, power_domain);
8695
8696 return ret;
8697 }
8698
8699 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8700 {
8701 struct drm_device *dev = &dev_priv->drm;
8702 struct intel_crtc *crtc;
8703
8704 for_each_intel_crtc(dev, crtc)
8705 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8706 pipe_name(crtc->pipe));
8707
8708 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)),
8709 "Display power well on\n");
8710 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8711 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8712 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8713 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8714 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8715 "CPU PWM1 enabled\n");
8716 if (IS_HASWELL(dev_priv))
8717 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8718 "CPU PWM2 enabled\n");
8719 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8720 "PCH PWM1 enabled\n");
8721 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8722 "Utility pin enabled\n");
8723 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8724
8725 /*
8726 * In theory we can still leave IRQs enabled, as long as only the HPD
8727 * interrupts remain enabled. We used to check for that, but since it's
8728 * gen-specific and since we only disable LCPLL after we fully disable
8729 * the interrupts, the check below should be enough.
8730 */
8731 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8732 }
8733
8734 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8735 {
8736 if (IS_HASWELL(dev_priv))
8737 return I915_READ(D_COMP_HSW);
8738 else
8739 return I915_READ(D_COMP_BDW);
8740 }
8741
8742 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8743 {
8744 if (IS_HASWELL(dev_priv)) {
8745 mutex_lock(&dev_priv->pcu_lock);
8746 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8747 val))
8748 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8749 mutex_unlock(&dev_priv->pcu_lock);
8750 } else {
8751 I915_WRITE(D_COMP_BDW, val);
8752 POSTING_READ(D_COMP_BDW);
8753 }
8754 }
8755
8756 /*
8757 * This function implements pieces of two sequences from BSpec:
8758 * - Sequence for display software to disable LCPLL
8759 * - Sequence for display software to allow package C8+
8760 * The steps implemented here are just the steps that actually touch the LCPLL
8761 * register. Callers should take care of disabling all the display engine
8762 * functions, doing the mode unset, fixing interrupts, etc.
8763 */
8764 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8765 bool switch_to_fclk, bool allow_power_down)
8766 {
8767 uint32_t val;
8768
8769 assert_can_disable_lcpll(dev_priv);
8770
8771 val = I915_READ(LCPLL_CTL);
8772
8773 if (switch_to_fclk) {
8774 val |= LCPLL_CD_SOURCE_FCLK;
8775 I915_WRITE(LCPLL_CTL, val);
8776
8777 if (wait_for_us(I915_READ(LCPLL_CTL) &
8778 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8779 DRM_ERROR("Switching to FCLK failed\n");
8780
8781 val = I915_READ(LCPLL_CTL);
8782 }
8783
8784 val |= LCPLL_PLL_DISABLE;
8785 I915_WRITE(LCPLL_CTL, val);
8786 POSTING_READ(LCPLL_CTL);
8787
8788 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8789 DRM_ERROR("LCPLL still locked\n");
8790
8791 val = hsw_read_dcomp(dev_priv);
8792 val |= D_COMP_COMP_DISABLE;
8793 hsw_write_dcomp(dev_priv, val);
8794 ndelay(100);
8795
8796 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8797 1))
8798 DRM_ERROR("D_COMP RCOMP still in progress\n");
8799
8800 if (allow_power_down) {
8801 val = I915_READ(LCPLL_CTL);
8802 val |= LCPLL_POWER_DOWN_ALLOW;
8803 I915_WRITE(LCPLL_CTL, val);
8804 POSTING_READ(LCPLL_CTL);
8805 }
8806 }
8807
8808 /*
8809 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8810 * source.
8811 */
8812 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8813 {
8814 uint32_t val;
8815
8816 val = I915_READ(LCPLL_CTL);
8817
8818 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8819 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8820 return;
8821
8822 /*
8823 * Make sure we're not on PC8 state before disabling PC8, otherwise
8824 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8825 */
8826 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8827
8828 if (val & LCPLL_POWER_DOWN_ALLOW) {
8829 val &= ~LCPLL_POWER_DOWN_ALLOW;
8830 I915_WRITE(LCPLL_CTL, val);
8831 POSTING_READ(LCPLL_CTL);
8832 }
8833
8834 val = hsw_read_dcomp(dev_priv);
8835 val |= D_COMP_COMP_FORCE;
8836 val &= ~D_COMP_COMP_DISABLE;
8837 hsw_write_dcomp(dev_priv, val);
8838
8839 val = I915_READ(LCPLL_CTL);
8840 val &= ~LCPLL_PLL_DISABLE;
8841 I915_WRITE(LCPLL_CTL, val);
8842
8843 if (intel_wait_for_register(dev_priv,
8844 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8845 5))
8846 DRM_ERROR("LCPLL not locked yet\n");
8847
8848 if (val & LCPLL_CD_SOURCE_FCLK) {
8849 val = I915_READ(LCPLL_CTL);
8850 val &= ~LCPLL_CD_SOURCE_FCLK;
8851 I915_WRITE(LCPLL_CTL, val);
8852
8853 if (wait_for_us((I915_READ(LCPLL_CTL) &
8854 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8855 DRM_ERROR("Switching back to LCPLL failed\n");
8856 }
8857
8858 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8859 intel_update_cdclk(dev_priv);
8860 }
8861
8862 /*
8863 * Package states C8 and deeper are really deep PC states that can only be
8864 * reached when all the devices on the system allow it, so even if the graphics
8865 * device allows PC8+, it doesn't mean the system will actually get to these
8866 * states. Our driver only allows PC8+ when going into runtime PM.
8867 *
8868 * The requirements for PC8+ are that all the outputs are disabled, the power
8869 * well is disabled and most interrupts are disabled, and these are also
8870 * requirements for runtime PM. When these conditions are met, we manually do
8871 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8872 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8873 * hang the machine.
8874 *
8875 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8876 * the state of some registers, so when we come back from PC8+ we need to
8877 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8878 * need to take care of the registers kept by RC6. Notice that this happens even
8879 * if we don't put the device in PCI D3 state (which is what currently happens
8880 * because of the runtime PM support).
8881 *
8882 * For more, read "Display Sequences for Package C8" on the hardware
8883 * documentation.
8884 */
8885 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8886 {
8887 uint32_t val;
8888
8889 DRM_DEBUG_KMS("Enabling package C8+\n");
8890
8891 if (HAS_PCH_LPT_LP(dev_priv)) {
8892 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8893 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8894 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8895 }
8896
8897 lpt_disable_clkout_dp(dev_priv);
8898 hsw_disable_lcpll(dev_priv, true, true);
8899 }
8900
8901 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8902 {
8903 uint32_t val;
8904
8905 DRM_DEBUG_KMS("Disabling package C8+\n");
8906
8907 hsw_restore_lcpll(dev_priv);
8908 lpt_init_pch_refclk(dev_priv);
8909
8910 if (HAS_PCH_LPT_LP(dev_priv)) {
8911 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8912 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8913 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8914 }
8915 }
8916
8917 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8918 struct intel_crtc_state *crtc_state)
8919 {
8920 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8921 struct intel_encoder *encoder =
8922 intel_ddi_get_crtc_new_encoder(crtc_state);
8923
8924 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
8925 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8926 pipe_name(crtc->pipe));
8927 return -EINVAL;
8928 }
8929 }
8930
8931 return 0;
8932 }
8933
8934 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
8935 enum port port,
8936 struct intel_crtc_state *pipe_config)
8937 {
8938 enum intel_dpll_id id;
8939 u32 temp;
8940
8941 temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
8942 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
8943
8944 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
8945 return;
8946
8947 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8948 }
8949
8950 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8951 enum port port,
8952 struct intel_crtc_state *pipe_config)
8953 {
8954 enum intel_dpll_id id;
8955
8956 switch (port) {
8957 case PORT_A:
8958 id = DPLL_ID_SKL_DPLL0;
8959 break;
8960 case PORT_B:
8961 id = DPLL_ID_SKL_DPLL1;
8962 break;
8963 case PORT_C:
8964 id = DPLL_ID_SKL_DPLL2;
8965 break;
8966 default:
8967 DRM_ERROR("Incorrect port type\n");
8968 return;
8969 }
8970
8971 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8972 }
8973
8974 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8975 enum port port,
8976 struct intel_crtc_state *pipe_config)
8977 {
8978 enum intel_dpll_id id;
8979 u32 temp;
8980
8981 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8982 id = temp >> (port * 3 + 1);
8983
8984 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
8985 return;
8986
8987 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8988 }
8989
8990 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8991 enum port port,
8992 struct intel_crtc_state *pipe_config)
8993 {
8994 enum intel_dpll_id id;
8995 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8996
8997 switch (ddi_pll_sel) {
8998 case PORT_CLK_SEL_WRPLL1:
8999 id = DPLL_ID_WRPLL1;
9000 break;
9001 case PORT_CLK_SEL_WRPLL2:
9002 id = DPLL_ID_WRPLL2;
9003 break;
9004 case PORT_CLK_SEL_SPLL:
9005 id = DPLL_ID_SPLL;
9006 break;
9007 case PORT_CLK_SEL_LCPLL_810:
9008 id = DPLL_ID_LCPLL_810;
9009 break;
9010 case PORT_CLK_SEL_LCPLL_1350:
9011 id = DPLL_ID_LCPLL_1350;
9012 break;
9013 case PORT_CLK_SEL_LCPLL_2700:
9014 id = DPLL_ID_LCPLL_2700;
9015 break;
9016 default:
9017 MISSING_CASE(ddi_pll_sel);
9018 /* fall through */
9019 case PORT_CLK_SEL_NONE:
9020 return;
9021 }
9022
9023 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9024 }
9025
9026 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9027 struct intel_crtc_state *pipe_config,
9028 u64 *power_domain_mask)
9029 {
9030 struct drm_device *dev = crtc->base.dev;
9031 struct drm_i915_private *dev_priv = to_i915(dev);
9032 enum intel_display_power_domain power_domain;
9033 u32 tmp;
9034
9035 /*
9036 * The pipe->transcoder mapping is fixed with the exception of the eDP
9037 * transcoder handled below.
9038 */
9039 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9040
9041 /*
9042 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9043 * consistency and less surprising code; it's in always on power).
9044 */
9045 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9046 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9047 enum pipe trans_edp_pipe;
9048 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9049 default:
9050 WARN(1, "unknown pipe linked to edp transcoder\n");
9051 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9052 case TRANS_DDI_EDP_INPUT_A_ON:
9053 trans_edp_pipe = PIPE_A;
9054 break;
9055 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9056 trans_edp_pipe = PIPE_B;
9057 break;
9058 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9059 trans_edp_pipe = PIPE_C;
9060 break;
9061 }
9062
9063 if (trans_edp_pipe == crtc->pipe)
9064 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9065 }
9066
9067 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9068 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9069 return false;
9070 *power_domain_mask |= BIT_ULL(power_domain);
9071
9072 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9073
9074 return tmp & PIPECONF_ENABLE;
9075 }
9076
9077 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9078 struct intel_crtc_state *pipe_config,
9079 u64 *power_domain_mask)
9080 {
9081 struct drm_device *dev = crtc->base.dev;
9082 struct drm_i915_private *dev_priv = to_i915(dev);
9083 enum intel_display_power_domain power_domain;
9084 enum port port;
9085 enum transcoder cpu_transcoder;
9086 u32 tmp;
9087
9088 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9089 if (port == PORT_A)
9090 cpu_transcoder = TRANSCODER_DSI_A;
9091 else
9092 cpu_transcoder = TRANSCODER_DSI_C;
9093
9094 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9095 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9096 continue;
9097 *power_domain_mask |= BIT_ULL(power_domain);
9098
9099 /*
9100 * The PLL needs to be enabled with a valid divider
9101 * configuration, otherwise accessing DSI registers will hang
9102 * the machine. See BSpec North Display Engine
9103 * registers/MIPI[BXT]. We can break out here early, since we
9104 * need the same DSI PLL to be enabled for both DSI ports.
9105 */
9106 if (!intel_dsi_pll_is_enabled(dev_priv))
9107 break;
9108
9109 /* XXX: this works for video mode only */
9110 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9111 if (!(tmp & DPI_ENABLE))
9112 continue;
9113
9114 tmp = I915_READ(MIPI_CTRL(port));
9115 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9116 continue;
9117
9118 pipe_config->cpu_transcoder = cpu_transcoder;
9119 break;
9120 }
9121
9122 return transcoder_is_dsi(pipe_config->cpu_transcoder);
9123 }
9124
9125 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9126 struct intel_crtc_state *pipe_config)
9127 {
9128 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9129 struct intel_shared_dpll *pll;
9130 enum port port;
9131 uint32_t tmp;
9132
9133 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9134
9135 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9136
9137 if (IS_CANNONLAKE(dev_priv))
9138 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9139 else if (IS_GEN9_BC(dev_priv))
9140 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9141 else if (IS_GEN9_LP(dev_priv))
9142 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9143 else
9144 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9145
9146 pll = pipe_config->shared_dpll;
9147 if (pll) {
9148 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9149 &pipe_config->dpll_hw_state));
9150 }
9151
9152 /*
9153 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9154 * DDI E. So just check whether this pipe is wired to DDI E and whether
9155 * the PCH transcoder is on.
9156 */
9157 if (INTEL_GEN(dev_priv) < 9 &&
9158 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9159 pipe_config->has_pch_encoder = true;
9160
9161 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9162 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9163 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9164
9165 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9166 }
9167 }
9168
9169 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9170 struct intel_crtc_state *pipe_config)
9171 {
9172 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9173 enum intel_display_power_domain power_domain;
9174 u64 power_domain_mask;
9175 bool active;
9176
9177 intel_crtc_init_scalers(crtc, pipe_config);
9178
9179 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9180 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9181 return false;
9182 power_domain_mask = BIT_ULL(power_domain);
9183
9184 pipe_config->shared_dpll = NULL;
9185
9186 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9187
9188 if (IS_GEN9_LP(dev_priv) &&
9189 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9190 WARN_ON(active);
9191 active = true;
9192 }
9193
9194 if (!active)
9195 goto out;
9196
9197 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9198 haswell_get_ddi_port_state(crtc, pipe_config);
9199 intel_get_pipe_timings(crtc, pipe_config);
9200 }
9201
9202 intel_get_pipe_src_size(crtc, pipe_config);
9203
9204 pipe_config->gamma_mode =
9205 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9206
9207 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
9208 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
9209 bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
9210
9211 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
9212 bool blend_mode_420 = tmp &
9213 PIPEMISC_YUV420_MODE_FULL_BLEND;
9214
9215 pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE;
9216 if (pipe_config->ycbcr420 != clrspace_yuv ||
9217 pipe_config->ycbcr420 != blend_mode_420)
9218 DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp);
9219 } else if (clrspace_yuv) {
9220 DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n");
9221 }
9222 }
9223
9224 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9225 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9226 power_domain_mask |= BIT_ULL(power_domain);
9227 if (INTEL_GEN(dev_priv) >= 9)
9228 skylake_get_pfit_config(crtc, pipe_config);
9229 else
9230 ironlake_get_pfit_config(crtc, pipe_config);
9231 }
9232
9233 if (IS_HASWELL(dev_priv))
9234 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9235 (I915_READ(IPS_CTL) & IPS_ENABLE);
9236
9237 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9238 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9239 pipe_config->pixel_multiplier =
9240 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9241 } else {
9242 pipe_config->pixel_multiplier = 1;
9243 }
9244
9245 out:
9246 for_each_power_domain(power_domain, power_domain_mask)
9247 intel_display_power_put(dev_priv, power_domain);
9248
9249 return active;
9250 }
9251
9252 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9253 {
9254 struct drm_i915_private *dev_priv =
9255 to_i915(plane_state->base.plane->dev);
9256 const struct drm_framebuffer *fb = plane_state->base.fb;
9257 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9258 u32 base;
9259
9260 if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9261 base = obj->phys_handle->busaddr;
9262 else
9263 base = intel_plane_ggtt_offset(plane_state);
9264
9265 base += plane_state->main.offset;
9266
9267 /* ILK+ do this automagically */
9268 if (HAS_GMCH_DISPLAY(dev_priv) &&
9269 plane_state->base.rotation & DRM_MODE_ROTATE_180)
9270 base += (plane_state->base.crtc_h *
9271 plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9272
9273 return base;
9274 }
9275
9276 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9277 {
9278 int x = plane_state->base.crtc_x;
9279 int y = plane_state->base.crtc_y;
9280 u32 pos = 0;
9281
9282 if (x < 0) {
9283 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9284 x = -x;
9285 }
9286 pos |= x << CURSOR_X_SHIFT;
9287
9288 if (y < 0) {
9289 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9290 y = -y;
9291 }
9292 pos |= y << CURSOR_Y_SHIFT;
9293
9294 return pos;
9295 }
9296
9297 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9298 {
9299 const struct drm_mode_config *config =
9300 &plane_state->base.plane->dev->mode_config;
9301 int width = plane_state->base.crtc_w;
9302 int height = plane_state->base.crtc_h;
9303
9304 return width > 0 && width <= config->cursor_width &&
9305 height > 0 && height <= config->cursor_height;
9306 }
9307
9308 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9309 struct intel_plane_state *plane_state)
9310 {
9311 const struct drm_framebuffer *fb = plane_state->base.fb;
9312 int src_x, src_y;
9313 u32 offset;
9314 int ret;
9315
9316 ret = drm_plane_helper_check_state(&plane_state->base,
9317 &plane_state->clip,
9318 DRM_PLANE_HELPER_NO_SCALING,
9319 DRM_PLANE_HELPER_NO_SCALING,
9320 true, true);
9321 if (ret)
9322 return ret;
9323
9324 if (!fb)
9325 return 0;
9326
9327 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9328 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9329 return -EINVAL;
9330 }
9331
9332 src_x = plane_state->base.src_x >> 16;
9333 src_y = plane_state->base.src_y >> 16;
9334
9335 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9336 offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9337
9338 if (src_x != 0 || src_y != 0) {
9339 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9340 return -EINVAL;
9341 }
9342
9343 plane_state->main.offset = offset;
9344
9345 return 0;
9346 }
9347
9348 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9349 const struct intel_plane_state *plane_state)
9350 {
9351 const struct drm_framebuffer *fb = plane_state->base.fb;
9352
9353 return CURSOR_ENABLE |
9354 CURSOR_GAMMA_ENABLE |
9355 CURSOR_FORMAT_ARGB |
9356 CURSOR_STRIDE(fb->pitches[0]);
9357 }
9358
9359 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9360 {
9361 int width = plane_state->base.crtc_w;
9362
9363 /*
9364 * 845g/865g are only limited by the width of their cursors,
9365 * the height is arbitrary up to the precision of the register.
9366 */
9367 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9368 }
9369
9370 static int i845_check_cursor(struct intel_plane *plane,
9371 struct intel_crtc_state *crtc_state,
9372 struct intel_plane_state *plane_state)
9373 {
9374 const struct drm_framebuffer *fb = plane_state->base.fb;
9375 int ret;
9376
9377 ret = intel_check_cursor(crtc_state, plane_state);
9378 if (ret)
9379 return ret;
9380
9381 /* if we want to turn off the cursor ignore width and height */
9382 if (!fb)
9383 return 0;
9384
9385 /* Check for which cursor types we support */
9386 if (!i845_cursor_size_ok(plane_state)) {
9387 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9388 plane_state->base.crtc_w,
9389 plane_state->base.crtc_h);
9390 return -EINVAL;
9391 }
9392
9393 switch (fb->pitches[0]) {
9394 case 256:
9395 case 512:
9396 case 1024:
9397 case 2048:
9398 break;
9399 default:
9400 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9401 fb->pitches[0]);
9402 return -EINVAL;
9403 }
9404
9405 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9406
9407 return 0;
9408 }
9409
9410 static void i845_update_cursor(struct intel_plane *plane,
9411 const struct intel_crtc_state *crtc_state,
9412 const struct intel_plane_state *plane_state)
9413 {
9414 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9415 u32 cntl = 0, base = 0, pos = 0, size = 0;
9416 unsigned long irqflags;
9417
9418 if (plane_state && plane_state->base.visible) {
9419 unsigned int width = plane_state->base.crtc_w;
9420 unsigned int height = plane_state->base.crtc_h;
9421
9422 cntl = plane_state->ctl;
9423 size = (height << 12) | width;
9424
9425 base = intel_cursor_base(plane_state);
9426 pos = intel_cursor_position(plane_state);
9427 }
9428
9429 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9430
9431 /* On these chipsets we can only modify the base/size/stride
9432 * whilst the cursor is disabled.
9433 */
9434 if (plane->cursor.base != base ||
9435 plane->cursor.size != size ||
9436 plane->cursor.cntl != cntl) {
9437 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9438 I915_WRITE_FW(CURBASE(PIPE_A), base);
9439 I915_WRITE_FW(CURSIZE, size);
9440 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9441 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9442
9443 plane->cursor.base = base;
9444 plane->cursor.size = size;
9445 plane->cursor.cntl = cntl;
9446 } else {
9447 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9448 }
9449
9450 POSTING_READ_FW(CURCNTR(PIPE_A));
9451
9452 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9453 }
9454
9455 static void i845_disable_cursor(struct intel_plane *plane,
9456 struct intel_crtc *crtc)
9457 {
9458 i845_update_cursor(plane, NULL, NULL);
9459 }
9460
9461 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9462 const struct intel_plane_state *plane_state)
9463 {
9464 struct drm_i915_private *dev_priv =
9465 to_i915(plane_state->base.plane->dev);
9466 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9467 u32 cntl;
9468
9469 cntl = MCURSOR_GAMMA_ENABLE;
9470
9471 if (HAS_DDI(dev_priv))
9472 cntl |= CURSOR_PIPE_CSC_ENABLE;
9473
9474 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9475
9476 switch (plane_state->base.crtc_w) {
9477 case 64:
9478 cntl |= CURSOR_MODE_64_ARGB_AX;
9479 break;
9480 case 128:
9481 cntl |= CURSOR_MODE_128_ARGB_AX;
9482 break;
9483 case 256:
9484 cntl |= CURSOR_MODE_256_ARGB_AX;
9485 break;
9486 default:
9487 MISSING_CASE(plane_state->base.crtc_w);
9488 return 0;
9489 }
9490
9491 if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9492 cntl |= CURSOR_ROTATE_180;
9493
9494 return cntl;
9495 }
9496
9497 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9498 {
9499 struct drm_i915_private *dev_priv =
9500 to_i915(plane_state->base.plane->dev);
9501 int width = plane_state->base.crtc_w;
9502 int height = plane_state->base.crtc_h;
9503
9504 if (!intel_cursor_size_ok(plane_state))
9505 return false;
9506
9507 /* Cursor width is limited to a few power-of-two sizes */
9508 switch (width) {
9509 case 256:
9510 case 128:
9511 case 64:
9512 break;
9513 default:
9514 return false;
9515 }
9516
9517 /*
9518 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9519 * height from 8 lines up to the cursor width, when the
9520 * cursor is not rotated. Everything else requires square
9521 * cursors.
9522 */
9523 if (HAS_CUR_FBC(dev_priv) &&
9524 plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9525 if (height < 8 || height > width)
9526 return false;
9527 } else {
9528 if (height != width)
9529 return false;
9530 }
9531
9532 return true;
9533 }
9534
9535 static int i9xx_check_cursor(struct intel_plane *plane,
9536 struct intel_crtc_state *crtc_state,
9537 struct intel_plane_state *plane_state)
9538 {
9539 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9540 const struct drm_framebuffer *fb = plane_state->base.fb;
9541 enum pipe pipe = plane->pipe;
9542 int ret;
9543
9544 ret = intel_check_cursor(crtc_state, plane_state);
9545 if (ret)
9546 return ret;
9547
9548 /* if we want to turn off the cursor ignore width and height */
9549 if (!fb)
9550 return 0;
9551
9552 /* Check for which cursor types we support */
9553 if (!i9xx_cursor_size_ok(plane_state)) {
9554 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9555 plane_state->base.crtc_w,
9556 plane_state->base.crtc_h);
9557 return -EINVAL;
9558 }
9559
9560 if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9561 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9562 fb->pitches[0], plane_state->base.crtc_w);
9563 return -EINVAL;
9564 }
9565
9566 /*
9567 * There's something wrong with the cursor on CHV pipe C.
9568 * If it straddles the left edge of the screen then
9569 * moving it away from the edge or disabling it often
9570 * results in a pipe underrun, and often that can lead to
9571 * dead pipe (constant underrun reported, and it scans
9572 * out just a solid color). To recover from that, the
9573 * display power well must be turned off and on again.
9574 * Refuse the put the cursor into that compromised position.
9575 */
9576 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9577 plane_state->base.visible && plane_state->base.crtc_x < 0) {
9578 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9579 return -EINVAL;
9580 }
9581
9582 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9583
9584 return 0;
9585 }
9586
9587 static void i9xx_update_cursor(struct intel_plane *plane,
9588 const struct intel_crtc_state *crtc_state,
9589 const struct intel_plane_state *plane_state)
9590 {
9591 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9592 enum pipe pipe = plane->pipe;
9593 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9594 unsigned long irqflags;
9595
9596 if (plane_state && plane_state->base.visible) {
9597 cntl = plane_state->ctl;
9598
9599 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9600 fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9601
9602 base = intel_cursor_base(plane_state);
9603 pos = intel_cursor_position(plane_state);
9604 }
9605
9606 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9607
9608 /*
9609 * On some platforms writing CURCNTR first will also
9610 * cause CURPOS to be armed by the CURBASE write.
9611 * Without the CURCNTR write the CURPOS write would
9612 * arm itself. Thus we always start the full update
9613 * with a CURCNTR write.
9614 *
9615 * On other platforms CURPOS always requires the
9616 * CURBASE write to arm the update. Additonally
9617 * a write to any of the cursor register will cancel
9618 * an already armed cursor update. Thus leaving out
9619 * the CURBASE write after CURPOS could lead to a
9620 * cursor that doesn't appear to move, or even change
9621 * shape. Thus we always write CURBASE.
9622 *
9623 * CURCNTR and CUR_FBC_CTL are always
9624 * armed by the CURBASE write only.
9625 */
9626 if (plane->cursor.base != base ||
9627 plane->cursor.size != fbc_ctl ||
9628 plane->cursor.cntl != cntl) {
9629 I915_WRITE_FW(CURCNTR(pipe), cntl);
9630 if (HAS_CUR_FBC(dev_priv))
9631 I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
9632 I915_WRITE_FW(CURPOS(pipe), pos);
9633 I915_WRITE_FW(CURBASE(pipe), base);
9634
9635 plane->cursor.base = base;
9636 plane->cursor.size = fbc_ctl;
9637 plane->cursor.cntl = cntl;
9638 } else {
9639 I915_WRITE_FW(CURPOS(pipe), pos);
9640 I915_WRITE_FW(CURBASE(pipe), base);
9641 }
9642
9643 POSTING_READ_FW(CURBASE(pipe));
9644
9645 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9646 }
9647
9648 static void i9xx_disable_cursor(struct intel_plane *plane,
9649 struct intel_crtc *crtc)
9650 {
9651 i9xx_update_cursor(plane, NULL, NULL);
9652 }
9653
9654
9655 /* VESA 640x480x72Hz mode to set on the pipe */
9656 static const struct drm_display_mode load_detect_mode = {
9657 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9658 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9659 };
9660
9661 struct drm_framebuffer *
9662 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9663 struct drm_mode_fb_cmd2 *mode_cmd)
9664 {
9665 struct intel_framebuffer *intel_fb;
9666 int ret;
9667
9668 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9669 if (!intel_fb)
9670 return ERR_PTR(-ENOMEM);
9671
9672 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9673 if (ret)
9674 goto err;
9675
9676 return &intel_fb->base;
9677
9678 err:
9679 kfree(intel_fb);
9680 return ERR_PTR(ret);
9681 }
9682
9683 static u32
9684 intel_framebuffer_pitch_for_width(int width, int bpp)
9685 {
9686 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9687 return ALIGN(pitch, 64);
9688 }
9689
9690 static u32
9691 intel_framebuffer_size_for_mode(const struct drm_display_mode *mode, int bpp)
9692 {
9693 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9694 return PAGE_ALIGN(pitch * mode->vdisplay);
9695 }
9696
9697 static struct drm_framebuffer *
9698 intel_framebuffer_create_for_mode(struct drm_device *dev,
9699 const struct drm_display_mode *mode,
9700 int depth, int bpp)
9701 {
9702 struct drm_framebuffer *fb;
9703 struct drm_i915_gem_object *obj;
9704 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9705
9706 obj = i915_gem_object_create(to_i915(dev),
9707 intel_framebuffer_size_for_mode(mode, bpp));
9708 if (IS_ERR(obj))
9709 return ERR_CAST(obj);
9710
9711 mode_cmd.width = mode->hdisplay;
9712 mode_cmd.height = mode->vdisplay;
9713 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9714 bpp);
9715 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9716
9717 fb = intel_framebuffer_create(obj, &mode_cmd);
9718 if (IS_ERR(fb))
9719 i915_gem_object_put(obj);
9720
9721 return fb;
9722 }
9723
9724 static struct drm_framebuffer *
9725 mode_fits_in_fbdev(struct drm_device *dev,
9726 const struct drm_display_mode *mode)
9727 {
9728 #ifdef CONFIG_DRM_FBDEV_EMULATION
9729 struct drm_i915_private *dev_priv = to_i915(dev);
9730 struct drm_i915_gem_object *obj;
9731 struct drm_framebuffer *fb;
9732
9733 if (!dev_priv->fbdev)
9734 return NULL;
9735
9736 if (!dev_priv->fbdev->fb)
9737 return NULL;
9738
9739 obj = dev_priv->fbdev->fb->obj;
9740 BUG_ON(!obj);
9741
9742 fb = &dev_priv->fbdev->fb->base;
9743 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9744 fb->format->cpp[0] * 8))
9745 return NULL;
9746
9747 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9748 return NULL;
9749
9750 drm_framebuffer_get(fb);
9751 return fb;
9752 #else
9753 return NULL;
9754 #endif
9755 }
9756
9757 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9758 struct drm_crtc *crtc,
9759 const struct drm_display_mode *mode,
9760 struct drm_framebuffer *fb,
9761 int x, int y)
9762 {
9763 struct drm_plane_state *plane_state;
9764 int hdisplay, vdisplay;
9765 int ret;
9766
9767 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9768 if (IS_ERR(plane_state))
9769 return PTR_ERR(plane_state);
9770
9771 if (mode)
9772 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9773 else
9774 hdisplay = vdisplay = 0;
9775
9776 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9777 if (ret)
9778 return ret;
9779 drm_atomic_set_fb_for_plane(plane_state, fb);
9780 plane_state->crtc_x = 0;
9781 plane_state->crtc_y = 0;
9782 plane_state->crtc_w = hdisplay;
9783 plane_state->crtc_h = vdisplay;
9784 plane_state->src_x = x << 16;
9785 plane_state->src_y = y << 16;
9786 plane_state->src_w = hdisplay << 16;
9787 plane_state->src_h = vdisplay << 16;
9788
9789 return 0;
9790 }
9791
9792 int intel_get_load_detect_pipe(struct drm_connector *connector,
9793 const struct drm_display_mode *mode,
9794 struct intel_load_detect_pipe *old,
9795 struct drm_modeset_acquire_ctx *ctx)
9796 {
9797 struct intel_crtc *intel_crtc;
9798 struct intel_encoder *intel_encoder =
9799 intel_attached_encoder(connector);
9800 struct drm_crtc *possible_crtc;
9801 struct drm_encoder *encoder = &intel_encoder->base;
9802 struct drm_crtc *crtc = NULL;
9803 struct drm_device *dev = encoder->dev;
9804 struct drm_i915_private *dev_priv = to_i915(dev);
9805 struct drm_framebuffer *fb;
9806 struct drm_mode_config *config = &dev->mode_config;
9807 struct drm_atomic_state *state = NULL, *restore_state = NULL;
9808 struct drm_connector_state *connector_state;
9809 struct intel_crtc_state *crtc_state;
9810 int ret, i = -1;
9811
9812 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9813 connector->base.id, connector->name,
9814 encoder->base.id, encoder->name);
9815
9816 old->restore_state = NULL;
9817
9818 WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
9819
9820 /*
9821 * Algorithm gets a little messy:
9822 *
9823 * - if the connector already has an assigned crtc, use it (but make
9824 * sure it's on first)
9825 *
9826 * - try to find the first unused crtc that can drive this connector,
9827 * and use that if we find one
9828 */
9829
9830 /* See if we already have a CRTC for this connector */
9831 if (connector->state->crtc) {
9832 crtc = connector->state->crtc;
9833
9834 ret = drm_modeset_lock(&crtc->mutex, ctx);
9835 if (ret)
9836 goto fail;
9837
9838 /* Make sure the crtc and connector are running */
9839 goto found;
9840 }
9841
9842 /* Find an unused one (if possible) */
9843 for_each_crtc(dev, possible_crtc) {
9844 i++;
9845 if (!(encoder->possible_crtcs & (1 << i)))
9846 continue;
9847
9848 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9849 if (ret)
9850 goto fail;
9851
9852 if (possible_crtc->state->enable) {
9853 drm_modeset_unlock(&possible_crtc->mutex);
9854 continue;
9855 }
9856
9857 crtc = possible_crtc;
9858 break;
9859 }
9860
9861 /*
9862 * If we didn't find an unused CRTC, don't use any.
9863 */
9864 if (!crtc) {
9865 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9866 ret = -ENODEV;
9867 goto fail;
9868 }
9869
9870 found:
9871 intel_crtc = to_intel_crtc(crtc);
9872
9873 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9874 if (ret)
9875 goto fail;
9876
9877 state = drm_atomic_state_alloc(dev);
9878 restore_state = drm_atomic_state_alloc(dev);
9879 if (!state || !restore_state) {
9880 ret = -ENOMEM;
9881 goto fail;
9882 }
9883
9884 state->acquire_ctx = ctx;
9885 restore_state->acquire_ctx = ctx;
9886
9887 connector_state = drm_atomic_get_connector_state(state, connector);
9888 if (IS_ERR(connector_state)) {
9889 ret = PTR_ERR(connector_state);
9890 goto fail;
9891 }
9892
9893 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9894 if (ret)
9895 goto fail;
9896
9897 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9898 if (IS_ERR(crtc_state)) {
9899 ret = PTR_ERR(crtc_state);
9900 goto fail;
9901 }
9902
9903 crtc_state->base.active = crtc_state->base.enable = true;
9904
9905 if (!mode)
9906 mode = &load_detect_mode;
9907
9908 /* We need a framebuffer large enough to accommodate all accesses
9909 * that the plane may generate whilst we perform load detection.
9910 * We can not rely on the fbcon either being present (we get called
9911 * during its initialisation to detect all boot displays, or it may
9912 * not even exist) or that it is large enough to satisfy the
9913 * requested mode.
9914 */
9915 fb = mode_fits_in_fbdev(dev, mode);
9916 if (fb == NULL) {
9917 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9918 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9919 } else
9920 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9921 if (IS_ERR(fb)) {
9922 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9923 ret = PTR_ERR(fb);
9924 goto fail;
9925 }
9926
9927 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9928 if (ret)
9929 goto fail;
9930
9931 drm_framebuffer_put(fb);
9932
9933 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9934 if (ret)
9935 goto fail;
9936
9937 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9938 if (!ret)
9939 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9940 if (!ret)
9941 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9942 if (ret) {
9943 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9944 goto fail;
9945 }
9946
9947 ret = drm_atomic_commit(state);
9948 if (ret) {
9949 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9950 goto fail;
9951 }
9952
9953 old->restore_state = restore_state;
9954 drm_atomic_state_put(state);
9955
9956 /* let the connector get through one full cycle before testing */
9957 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9958 return true;
9959
9960 fail:
9961 if (state) {
9962 drm_atomic_state_put(state);
9963 state = NULL;
9964 }
9965 if (restore_state) {
9966 drm_atomic_state_put(restore_state);
9967 restore_state = NULL;
9968 }
9969
9970 if (ret == -EDEADLK)
9971 return ret;
9972
9973 return false;
9974 }
9975
9976 void intel_release_load_detect_pipe(struct drm_connector *connector,
9977 struct intel_load_detect_pipe *old,
9978 struct drm_modeset_acquire_ctx *ctx)
9979 {
9980 struct intel_encoder *intel_encoder =
9981 intel_attached_encoder(connector);
9982 struct drm_encoder *encoder = &intel_encoder->base;
9983 struct drm_atomic_state *state = old->restore_state;
9984 int ret;
9985
9986 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9987 connector->base.id, connector->name,
9988 encoder->base.id, encoder->name);
9989
9990 if (!state)
9991 return;
9992
9993 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
9994 if (ret)
9995 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
9996 drm_atomic_state_put(state);
9997 }
9998
9999 static int i9xx_pll_refclk(struct drm_device *dev,
10000 const struct intel_crtc_state *pipe_config)
10001 {
10002 struct drm_i915_private *dev_priv = to_i915(dev);
10003 u32 dpll = pipe_config->dpll_hw_state.dpll;
10004
10005 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10006 return dev_priv->vbt.lvds_ssc_freq;
10007 else if (HAS_PCH_SPLIT(dev_priv))
10008 return 120000;
10009 else if (!IS_GEN2(dev_priv))
10010 return 96000;
10011 else
10012 return 48000;
10013 }
10014
10015 /* Returns the clock of the currently programmed mode of the given pipe. */
10016 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10017 struct intel_crtc_state *pipe_config)
10018 {
10019 struct drm_device *dev = crtc->base.dev;
10020 struct drm_i915_private *dev_priv = to_i915(dev);
10021 int pipe = pipe_config->cpu_transcoder;
10022 u32 dpll = pipe_config->dpll_hw_state.dpll;
10023 u32 fp;
10024 struct dpll clock;
10025 int port_clock;
10026 int refclk = i9xx_pll_refclk(dev, pipe_config);
10027
10028 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10029 fp = pipe_config->dpll_hw_state.fp0;
10030 else
10031 fp = pipe_config->dpll_hw_state.fp1;
10032
10033 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10034 if (IS_PINEVIEW(dev_priv)) {
10035 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10036 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10037 } else {
10038 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10039 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10040 }
10041
10042 if (!IS_GEN2(dev_priv)) {
10043 if (IS_PINEVIEW(dev_priv))
10044 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10045 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10046 else
10047 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10048 DPLL_FPA01_P1_POST_DIV_SHIFT);
10049
10050 switch (dpll & DPLL_MODE_MASK) {
10051 case DPLLB_MODE_DAC_SERIAL:
10052 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10053 5 : 10;
10054 break;
10055 case DPLLB_MODE_LVDS:
10056 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10057 7 : 14;
10058 break;
10059 default:
10060 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10061 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10062 return;
10063 }
10064
10065 if (IS_PINEVIEW(dev_priv))
10066 port_clock = pnv_calc_dpll_params(refclk, &clock);
10067 else
10068 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10069 } else {
10070 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
10071 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10072
10073 if (is_lvds) {
10074 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10075 DPLL_FPA01_P1_POST_DIV_SHIFT);
10076
10077 if (lvds & LVDS_CLKB_POWER_UP)
10078 clock.p2 = 7;
10079 else
10080 clock.p2 = 14;
10081 } else {
10082 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10083 clock.p1 = 2;
10084 else {
10085 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10086 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10087 }
10088 if (dpll & PLL_P2_DIVIDE_BY_4)
10089 clock.p2 = 4;
10090 else
10091 clock.p2 = 2;
10092 }
10093
10094 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10095 }
10096
10097 /*
10098 * This value includes pixel_multiplier. We will use
10099 * port_clock to compute adjusted_mode.crtc_clock in the
10100 * encoder's get_config() function.
10101 */
10102 pipe_config->port_clock = port_clock;
10103 }
10104
10105 int intel_dotclock_calculate(int link_freq,
10106 const struct intel_link_m_n *m_n)
10107 {
10108 /*
10109 * The calculation for the data clock is:
10110 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10111 * But we want to avoid losing precison if possible, so:
10112 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10113 *
10114 * and the link clock is simpler:
10115 * link_clock = (m * link_clock) / n
10116 */
10117
10118 if (!m_n->link_n)
10119 return 0;
10120
10121 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
10122 }
10123
10124 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10125 struct intel_crtc_state *pipe_config)
10126 {
10127 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10128
10129 /* read out port_clock from the DPLL */
10130 i9xx_crtc_clock_get(crtc, pipe_config);
10131
10132 /*
10133 * In case there is an active pipe without active ports,
10134 * we may need some idea for the dotclock anyway.
10135 * Calculate one based on the FDI configuration.
10136 */
10137 pipe_config->base.adjusted_mode.crtc_clock =
10138 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10139 &pipe_config->fdi_m_n);
10140 }
10141
10142 /* Returns the currently programmed mode of the given encoder. */
10143 struct drm_display_mode *
10144 intel_encoder_current_mode(struct intel_encoder *encoder)
10145 {
10146 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
10147 struct intel_crtc_state *crtc_state;
10148 struct drm_display_mode *mode;
10149 struct intel_crtc *crtc;
10150 enum pipe pipe;
10151
10152 if (!encoder->get_hw_state(encoder, &pipe))
10153 return NULL;
10154
10155 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10156
10157 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10158 if (!mode)
10159 return NULL;
10160
10161 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
10162 if (!crtc_state) {
10163 kfree(mode);
10164 return NULL;
10165 }
10166
10167 crtc_state->base.crtc = &crtc->base;
10168
10169 if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
10170 kfree(crtc_state);
10171 kfree(mode);
10172 return NULL;
10173 }
10174
10175 encoder->get_config(encoder, crtc_state);
10176
10177 intel_mode_from_pipe_config(mode, crtc_state);
10178
10179 kfree(crtc_state);
10180
10181 return mode;
10182 }
10183
10184 static void intel_crtc_destroy(struct drm_crtc *crtc)
10185 {
10186 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10187
10188 drm_crtc_cleanup(crtc);
10189 kfree(intel_crtc);
10190 }
10191
10192 /**
10193 * intel_wm_need_update - Check whether watermarks need updating
10194 * @plane: drm plane
10195 * @state: new plane state
10196 *
10197 * Check current plane state versus the new one to determine whether
10198 * watermarks need to be recalculated.
10199 *
10200 * Returns true or false.
10201 */
10202 static bool intel_wm_need_update(struct drm_plane *plane,
10203 struct drm_plane_state *state)
10204 {
10205 struct intel_plane_state *new = to_intel_plane_state(state);
10206 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10207
10208 /* Update watermarks on tiling or size changes. */
10209 if (new->base.visible != cur->base.visible)
10210 return true;
10211
10212 if (!cur->base.fb || !new->base.fb)
10213 return false;
10214
10215 if (cur->base.fb->modifier != new->base.fb->modifier ||
10216 cur->base.rotation != new->base.rotation ||
10217 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10218 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10219 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10220 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10221 return true;
10222
10223 return false;
10224 }
10225
10226 static bool needs_scaling(const struct intel_plane_state *state)
10227 {
10228 int src_w = drm_rect_width(&state->base.src) >> 16;
10229 int src_h = drm_rect_height(&state->base.src) >> 16;
10230 int dst_w = drm_rect_width(&state->base.dst);
10231 int dst_h = drm_rect_height(&state->base.dst);
10232
10233 return (src_w != dst_w || src_h != dst_h);
10234 }
10235
10236 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
10237 struct drm_crtc_state *crtc_state,
10238 const struct intel_plane_state *old_plane_state,
10239 struct drm_plane_state *plane_state)
10240 {
10241 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10242 struct drm_crtc *crtc = crtc_state->crtc;
10243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10244 struct intel_plane *plane = to_intel_plane(plane_state->plane);
10245 struct drm_device *dev = crtc->dev;
10246 struct drm_i915_private *dev_priv = to_i915(dev);
10247 bool mode_changed = needs_modeset(crtc_state);
10248 bool was_crtc_enabled = old_crtc_state->base.active;
10249 bool is_crtc_enabled = crtc_state->active;
10250 bool turn_off, turn_on, visible, was_visible;
10251 struct drm_framebuffer *fb = plane_state->fb;
10252 int ret;
10253
10254 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10255 ret = skl_update_scaler_plane(
10256 to_intel_crtc_state(crtc_state),
10257 to_intel_plane_state(plane_state));
10258 if (ret)
10259 return ret;
10260 }
10261
10262 was_visible = old_plane_state->base.visible;
10263 visible = plane_state->visible;
10264
10265 if (!was_crtc_enabled && WARN_ON(was_visible))
10266 was_visible = false;
10267
10268 /*
10269 * Visibility is calculated as if the crtc was on, but
10270 * after scaler setup everything depends on it being off
10271 * when the crtc isn't active.
10272 *
10273 * FIXME this is wrong for watermarks. Watermarks should also
10274 * be computed as if the pipe would be active. Perhaps move
10275 * per-plane wm computation to the .check_plane() hook, and
10276 * only combine the results from all planes in the current place?
10277 */
10278 if (!is_crtc_enabled) {
10279 plane_state->visible = visible = false;
10280 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10281 }
10282
10283 if (!was_visible && !visible)
10284 return 0;
10285
10286 if (fb != old_plane_state->base.fb)
10287 pipe_config->fb_changed = true;
10288
10289 turn_off = was_visible && (!visible || mode_changed);
10290 turn_on = visible && (!was_visible || mode_changed);
10291
10292 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10293 intel_crtc->base.base.id, intel_crtc->base.name,
10294 plane->base.base.id, plane->base.name,
10295 fb ? fb->base.id : -1);
10296
10297 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10298 plane->base.base.id, plane->base.name,
10299 was_visible, visible,
10300 turn_off, turn_on, mode_changed);
10301
10302 if (turn_on) {
10303 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10304 pipe_config->update_wm_pre = true;
10305
10306 /* must disable cxsr around plane enable/disable */
10307 if (plane->id != PLANE_CURSOR)
10308 pipe_config->disable_cxsr = true;
10309 } else if (turn_off) {
10310 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10311 pipe_config->update_wm_post = true;
10312
10313 /* must disable cxsr around plane enable/disable */
10314 if (plane->id != PLANE_CURSOR)
10315 pipe_config->disable_cxsr = true;
10316 } else if (intel_wm_need_update(&plane->base, plane_state)) {
10317 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
10318 /* FIXME bollocks */
10319 pipe_config->update_wm_pre = true;
10320 pipe_config->update_wm_post = true;
10321 }
10322 }
10323
10324 if (visible || was_visible)
10325 pipe_config->fb_bits |= plane->frontbuffer_bit;
10326
10327 /*
10328 * WaCxSRDisabledForSpriteScaling:ivb
10329 *
10330 * cstate->update_wm was already set above, so this flag will
10331 * take effect when we commit and program watermarks.
10332 */
10333 if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10334 needs_scaling(to_intel_plane_state(plane_state)) &&
10335 !needs_scaling(old_plane_state))
10336 pipe_config->disable_lp_wm = true;
10337
10338 return 0;
10339 }
10340
10341 static bool encoders_cloneable(const struct intel_encoder *a,
10342 const struct intel_encoder *b)
10343 {
10344 /* masks could be asymmetric, so check both ways */
10345 return a == b || (a->cloneable & (1 << b->type) &&
10346 b->cloneable & (1 << a->type));
10347 }
10348
10349 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10350 struct intel_crtc *crtc,
10351 struct intel_encoder *encoder)
10352 {
10353 struct intel_encoder *source_encoder;
10354 struct drm_connector *connector;
10355 struct drm_connector_state *connector_state;
10356 int i;
10357
10358 for_each_new_connector_in_state(state, connector, connector_state, i) {
10359 if (connector_state->crtc != &crtc->base)
10360 continue;
10361
10362 source_encoder =
10363 to_intel_encoder(connector_state->best_encoder);
10364 if (!encoders_cloneable(encoder, source_encoder))
10365 return false;
10366 }
10367
10368 return true;
10369 }
10370
10371 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10372 struct drm_crtc_state *crtc_state)
10373 {
10374 struct drm_device *dev = crtc->dev;
10375 struct drm_i915_private *dev_priv = to_i915(dev);
10376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10377 struct intel_crtc_state *pipe_config =
10378 to_intel_crtc_state(crtc_state);
10379 struct drm_atomic_state *state = crtc_state->state;
10380 int ret;
10381 bool mode_changed = needs_modeset(crtc_state);
10382
10383 if (mode_changed && !crtc_state->active)
10384 pipe_config->update_wm_post = true;
10385
10386 if (mode_changed && crtc_state->enable &&
10387 dev_priv->display.crtc_compute_clock &&
10388 !WARN_ON(pipe_config->shared_dpll)) {
10389 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10390 pipe_config);
10391 if (ret)
10392 return ret;
10393 }
10394
10395 if (crtc_state->color_mgmt_changed) {
10396 ret = intel_color_check(crtc, crtc_state);
10397 if (ret)
10398 return ret;
10399
10400 /*
10401 * Changing color management on Intel hardware is
10402 * handled as part of planes update.
10403 */
10404 crtc_state->planes_changed = true;
10405 }
10406
10407 ret = 0;
10408 if (dev_priv->display.compute_pipe_wm) {
10409 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10410 if (ret) {
10411 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10412 return ret;
10413 }
10414 }
10415
10416 if (dev_priv->display.compute_intermediate_wm &&
10417 !to_intel_atomic_state(state)->skip_intermediate_wm) {
10418 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10419 return 0;
10420
10421 /*
10422 * Calculate 'intermediate' watermarks that satisfy both the
10423 * old state and the new state. We can program these
10424 * immediately.
10425 */
10426 ret = dev_priv->display.compute_intermediate_wm(dev,
10427 intel_crtc,
10428 pipe_config);
10429 if (ret) {
10430 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10431 return ret;
10432 }
10433 } else if (dev_priv->display.compute_intermediate_wm) {
10434 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10435 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10436 }
10437
10438 if (INTEL_GEN(dev_priv) >= 9) {
10439 if (mode_changed)
10440 ret = skl_update_scaler_crtc(pipe_config);
10441
10442 if (!ret)
10443 ret = skl_check_pipe_max_pixel_rate(intel_crtc,
10444 pipe_config);
10445 if (!ret)
10446 ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
10447 pipe_config);
10448 }
10449
10450 return ret;
10451 }
10452
10453 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
10454 .atomic_begin = intel_begin_crtc_commit,
10455 .atomic_flush = intel_finish_crtc_commit,
10456 .atomic_check = intel_crtc_atomic_check,
10457 };
10458
10459 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10460 {
10461 struct intel_connector *connector;
10462 struct drm_connector_list_iter conn_iter;
10463
10464 drm_connector_list_iter_begin(dev, &conn_iter);
10465 for_each_intel_connector_iter(connector, &conn_iter) {
10466 if (connector->base.state->crtc)
10467 drm_connector_unreference(&connector->base);
10468
10469 if (connector->base.encoder) {
10470 connector->base.state->best_encoder =
10471 connector->base.encoder;
10472 connector->base.state->crtc =
10473 connector->base.encoder->crtc;
10474
10475 drm_connector_reference(&connector->base);
10476 } else {
10477 connector->base.state->best_encoder = NULL;
10478 connector->base.state->crtc = NULL;
10479 }
10480 }
10481 drm_connector_list_iter_end(&conn_iter);
10482 }
10483
10484 static void
10485 connected_sink_compute_bpp(struct intel_connector *connector,
10486 struct intel_crtc_state *pipe_config)
10487 {
10488 const struct drm_display_info *info = &connector->base.display_info;
10489 int bpp = pipe_config->pipe_bpp;
10490
10491 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10492 connector->base.base.id,
10493 connector->base.name);
10494
10495 /* Don't use an invalid EDID bpc value */
10496 if (info->bpc != 0 && info->bpc * 3 < bpp) {
10497 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10498 bpp, info->bpc * 3);
10499 pipe_config->pipe_bpp = info->bpc * 3;
10500 }
10501
10502 /* Clamp bpp to 8 on screens without EDID 1.4 */
10503 if (info->bpc == 0 && bpp > 24) {
10504 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10505 bpp);
10506 pipe_config->pipe_bpp = 24;
10507 }
10508 }
10509
10510 static int
10511 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10512 struct intel_crtc_state *pipe_config)
10513 {
10514 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10515 struct drm_atomic_state *state;
10516 struct drm_connector *connector;
10517 struct drm_connector_state *connector_state;
10518 int bpp, i;
10519
10520 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
10521 IS_CHERRYVIEW(dev_priv)))
10522 bpp = 10*3;
10523 else if (INTEL_GEN(dev_priv) >= 5)
10524 bpp = 12*3;
10525 else
10526 bpp = 8*3;
10527
10528
10529 pipe_config->pipe_bpp = bpp;
10530
10531 state = pipe_config->base.state;
10532
10533 /* Clamp display bpp to EDID value */
10534 for_each_new_connector_in_state(state, connector, connector_state, i) {
10535 if (connector_state->crtc != &crtc->base)
10536 continue;
10537
10538 connected_sink_compute_bpp(to_intel_connector(connector),
10539 pipe_config);
10540 }
10541
10542 return bpp;
10543 }
10544
10545 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10546 {
10547 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10548 "type: 0x%x flags: 0x%x\n",
10549 mode->crtc_clock,
10550 mode->crtc_hdisplay, mode->crtc_hsync_start,
10551 mode->crtc_hsync_end, mode->crtc_htotal,
10552 mode->crtc_vdisplay, mode->crtc_vsync_start,
10553 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10554 }
10555
10556 static inline void
10557 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
10558 unsigned int lane_count, struct intel_link_m_n *m_n)
10559 {
10560 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10561 id, lane_count,
10562 m_n->gmch_m, m_n->gmch_n,
10563 m_n->link_m, m_n->link_n, m_n->tu);
10564 }
10565
10566 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
10567
10568 static const char * const output_type_str[] = {
10569 OUTPUT_TYPE(UNUSED),
10570 OUTPUT_TYPE(ANALOG),
10571 OUTPUT_TYPE(DVO),
10572 OUTPUT_TYPE(SDVO),
10573 OUTPUT_TYPE(LVDS),
10574 OUTPUT_TYPE(TVOUT),
10575 OUTPUT_TYPE(HDMI),
10576 OUTPUT_TYPE(DP),
10577 OUTPUT_TYPE(EDP),
10578 OUTPUT_TYPE(DSI),
10579 OUTPUT_TYPE(UNKNOWN),
10580 OUTPUT_TYPE(DP_MST),
10581 };
10582
10583 #undef OUTPUT_TYPE
10584
10585 static void snprintf_output_types(char *buf, size_t len,
10586 unsigned int output_types)
10587 {
10588 char *str = buf;
10589 int i;
10590
10591 str[0] = '\0';
10592
10593 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
10594 int r;
10595
10596 if ((output_types & BIT(i)) == 0)
10597 continue;
10598
10599 r = snprintf(str, len, "%s%s",
10600 str != buf ? "," : "", output_type_str[i]);
10601 if (r >= len)
10602 break;
10603 str += r;
10604 len -= r;
10605
10606 output_types &= ~BIT(i);
10607 }
10608
10609 WARN_ON_ONCE(output_types != 0);
10610 }
10611
10612 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10613 struct intel_crtc_state *pipe_config,
10614 const char *context)
10615 {
10616 struct drm_device *dev = crtc->base.dev;
10617 struct drm_i915_private *dev_priv = to_i915(dev);
10618 struct drm_plane *plane;
10619 struct intel_plane *intel_plane;
10620 struct intel_plane_state *state;
10621 struct drm_framebuffer *fb;
10622 char buf[64];
10623
10624 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
10625 crtc->base.base.id, crtc->base.name, context);
10626
10627 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
10628 DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
10629 buf, pipe_config->output_types);
10630
10631 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
10632 transcoder_name(pipe_config->cpu_transcoder),
10633 pipe_config->pipe_bpp, pipe_config->dither);
10634
10635 if (pipe_config->has_pch_encoder)
10636 intel_dump_m_n_config(pipe_config, "fdi",
10637 pipe_config->fdi_lanes,
10638 &pipe_config->fdi_m_n);
10639
10640 if (pipe_config->ycbcr420)
10641 DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n");
10642
10643 if (intel_crtc_has_dp_encoder(pipe_config)) {
10644 intel_dump_m_n_config(pipe_config, "dp m_n",
10645 pipe_config->lane_count, &pipe_config->dp_m_n);
10646 if (pipe_config->has_drrs)
10647 intel_dump_m_n_config(pipe_config, "dp m2_n2",
10648 pipe_config->lane_count,
10649 &pipe_config->dp_m2_n2);
10650 }
10651
10652 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10653 pipe_config->has_audio, pipe_config->has_infoframe);
10654
10655 DRM_DEBUG_KMS("requested mode:\n");
10656 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10657 DRM_DEBUG_KMS("adjusted mode:\n");
10658 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10659 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10660 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
10661 pipe_config->port_clock,
10662 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
10663 pipe_config->pixel_rate);
10664
10665 if (INTEL_GEN(dev_priv) >= 9)
10666 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
10667 crtc->num_scalers,
10668 pipe_config->scaler_state.scaler_users,
10669 pipe_config->scaler_state.scaler_id);
10670
10671 if (HAS_GMCH_DISPLAY(dev_priv))
10672 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10673 pipe_config->gmch_pfit.control,
10674 pipe_config->gmch_pfit.pgm_ratios,
10675 pipe_config->gmch_pfit.lvds_border_bits);
10676 else
10677 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10678 pipe_config->pch_pfit.pos,
10679 pipe_config->pch_pfit.size,
10680 enableddisabled(pipe_config->pch_pfit.enabled));
10681
10682 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
10683 pipe_config->ips_enabled, pipe_config->double_wide);
10684
10685 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
10686
10687 DRM_DEBUG_KMS("planes on this crtc\n");
10688 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
10689 struct drm_format_name_buf format_name;
10690 intel_plane = to_intel_plane(plane);
10691 if (intel_plane->pipe != crtc->pipe)
10692 continue;
10693
10694 state = to_intel_plane_state(plane->state);
10695 fb = state->base.fb;
10696 if (!fb) {
10697 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
10698 plane->base.id, plane->name, state->scaler_id);
10699 continue;
10700 }
10701
10702 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
10703 plane->base.id, plane->name,
10704 fb->base.id, fb->width, fb->height,
10705 drm_get_format_name(fb->format->format, &format_name));
10706 if (INTEL_GEN(dev_priv) >= 9)
10707 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
10708 state->scaler_id,
10709 state->base.src.x1 >> 16,
10710 state->base.src.y1 >> 16,
10711 drm_rect_width(&state->base.src) >> 16,
10712 drm_rect_height(&state->base.src) >> 16,
10713 state->base.dst.x1, state->base.dst.y1,
10714 drm_rect_width(&state->base.dst),
10715 drm_rect_height(&state->base.dst));
10716 }
10717 }
10718
10719 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
10720 {
10721 struct drm_device *dev = state->dev;
10722 struct drm_connector *connector;
10723 struct drm_connector_list_iter conn_iter;
10724 unsigned int used_ports = 0;
10725 unsigned int used_mst_ports = 0;
10726
10727 /*
10728 * Walk the connector list instead of the encoder
10729 * list to detect the problem on ddi platforms
10730 * where there's just one encoder per digital port.
10731 */
10732 drm_connector_list_iter_begin(dev, &conn_iter);
10733 drm_for_each_connector_iter(connector, &conn_iter) {
10734 struct drm_connector_state *connector_state;
10735 struct intel_encoder *encoder;
10736
10737 connector_state = drm_atomic_get_existing_connector_state(state, connector);
10738 if (!connector_state)
10739 connector_state = connector->state;
10740
10741 if (!connector_state->best_encoder)
10742 continue;
10743
10744 encoder = to_intel_encoder(connector_state->best_encoder);
10745
10746 WARN_ON(!connector_state->crtc);
10747
10748 switch (encoder->type) {
10749 unsigned int port_mask;
10750 case INTEL_OUTPUT_UNKNOWN:
10751 if (WARN_ON(!HAS_DDI(to_i915(dev))))
10752 break;
10753 case INTEL_OUTPUT_DP:
10754 case INTEL_OUTPUT_HDMI:
10755 case INTEL_OUTPUT_EDP:
10756 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10757
10758 /* the same port mustn't appear more than once */
10759 if (used_ports & port_mask)
10760 return false;
10761
10762 used_ports |= port_mask;
10763 break;
10764 case INTEL_OUTPUT_DP_MST:
10765 used_mst_ports |=
10766 1 << enc_to_mst(&encoder->base)->primary->port;
10767 break;
10768 default:
10769 break;
10770 }
10771 }
10772 drm_connector_list_iter_end(&conn_iter);
10773
10774 /* can't mix MST and SST/HDMI on the same port */
10775 if (used_ports & used_mst_ports)
10776 return false;
10777
10778 return true;
10779 }
10780
10781 static void
10782 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10783 {
10784 struct drm_i915_private *dev_priv =
10785 to_i915(crtc_state->base.crtc->dev);
10786 struct intel_crtc_scaler_state scaler_state;
10787 struct intel_dpll_hw_state dpll_hw_state;
10788 struct intel_shared_dpll *shared_dpll;
10789 struct intel_crtc_wm_state wm_state;
10790 bool force_thru, ips_force_disable;
10791
10792 /* FIXME: before the switch to atomic started, a new pipe_config was
10793 * kzalloc'd. Code that depends on any field being zero should be
10794 * fixed, so that the crtc_state can be safely duplicated. For now,
10795 * only fields that are know to not cause problems are preserved. */
10796
10797 scaler_state = crtc_state->scaler_state;
10798 shared_dpll = crtc_state->shared_dpll;
10799 dpll_hw_state = crtc_state->dpll_hw_state;
10800 force_thru = crtc_state->pch_pfit.force_thru;
10801 ips_force_disable = crtc_state->ips_force_disable;
10802 if (IS_G4X(dev_priv) ||
10803 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10804 wm_state = crtc_state->wm;
10805
10806 /* Keep base drm_crtc_state intact, only clear our extended struct */
10807 BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
10808 memset(&crtc_state->base + 1, 0,
10809 sizeof(*crtc_state) - sizeof(crtc_state->base));
10810
10811 crtc_state->scaler_state = scaler_state;
10812 crtc_state->shared_dpll = shared_dpll;
10813 crtc_state->dpll_hw_state = dpll_hw_state;
10814 crtc_state->pch_pfit.force_thru = force_thru;
10815 crtc_state->ips_force_disable = ips_force_disable;
10816 if (IS_G4X(dev_priv) ||
10817 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10818 crtc_state->wm = wm_state;
10819 }
10820
10821 static int
10822 intel_modeset_pipe_config(struct drm_crtc *crtc,
10823 struct intel_crtc_state *pipe_config)
10824 {
10825 struct drm_atomic_state *state = pipe_config->base.state;
10826 struct intel_encoder *encoder;
10827 struct drm_connector *connector;
10828 struct drm_connector_state *connector_state;
10829 int base_bpp, ret = -EINVAL;
10830 int i;
10831 bool retry = true;
10832
10833 clear_intel_crtc_state(pipe_config);
10834
10835 pipe_config->cpu_transcoder =
10836 (enum transcoder) to_intel_crtc(crtc)->pipe;
10837
10838 /*
10839 * Sanitize sync polarity flags based on requested ones. If neither
10840 * positive or negative polarity is requested, treat this as meaning
10841 * negative polarity.
10842 */
10843 if (!(pipe_config->base.adjusted_mode.flags &
10844 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10845 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10846
10847 if (!(pipe_config->base.adjusted_mode.flags &
10848 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10849 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10850
10851 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10852 pipe_config);
10853 if (base_bpp < 0)
10854 goto fail;
10855
10856 /*
10857 * Determine the real pipe dimensions. Note that stereo modes can
10858 * increase the actual pipe size due to the frame doubling and
10859 * insertion of additional space for blanks between the frame. This
10860 * is stored in the crtc timings. We use the requested mode to do this
10861 * computation to clearly distinguish it from the adjusted mode, which
10862 * can be changed by the connectors in the below retry loop.
10863 */
10864 drm_mode_get_hv_timing(&pipe_config->base.mode,
10865 &pipe_config->pipe_src_w,
10866 &pipe_config->pipe_src_h);
10867
10868 for_each_new_connector_in_state(state, connector, connector_state, i) {
10869 if (connector_state->crtc != crtc)
10870 continue;
10871
10872 encoder = to_intel_encoder(connector_state->best_encoder);
10873
10874 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
10875 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10876 goto fail;
10877 }
10878
10879 /*
10880 * Determine output_types before calling the .compute_config()
10881 * hooks so that the hooks can use this information safely.
10882 */
10883 pipe_config->output_types |= 1 << encoder->type;
10884 }
10885
10886 encoder_retry:
10887 /* Ensure the port clock defaults are reset when retrying. */
10888 pipe_config->port_clock = 0;
10889 pipe_config->pixel_multiplier = 1;
10890
10891 /* Fill in default crtc timings, allow encoders to overwrite them. */
10892 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10893 CRTC_STEREO_DOUBLE);
10894
10895 /* Pass our mode to the connectors and the CRTC to give them a chance to
10896 * adjust it according to limitations or connector properties, and also
10897 * a chance to reject the mode entirely.
10898 */
10899 for_each_new_connector_in_state(state, connector, connector_state, i) {
10900 if (connector_state->crtc != crtc)
10901 continue;
10902
10903 encoder = to_intel_encoder(connector_state->best_encoder);
10904
10905 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
10906 DRM_DEBUG_KMS("Encoder config failure\n");
10907 goto fail;
10908 }
10909 }
10910
10911 /* Set default port clock if not overwritten by the encoder. Needs to be
10912 * done afterwards in case the encoder adjusts the mode. */
10913 if (!pipe_config->port_clock)
10914 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10915 * pipe_config->pixel_multiplier;
10916
10917 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10918 if (ret < 0) {
10919 DRM_DEBUG_KMS("CRTC fixup failed\n");
10920 goto fail;
10921 }
10922
10923 if (ret == RETRY) {
10924 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10925 ret = -EINVAL;
10926 goto fail;
10927 }
10928
10929 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10930 retry = false;
10931 goto encoder_retry;
10932 }
10933
10934 /* Dithering seems to not pass-through bits correctly when it should, so
10935 * only enable it on 6bpc panels and when its not a compliance
10936 * test requesting 6bpc video pattern.
10937 */
10938 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
10939 !pipe_config->dither_force_disable;
10940 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
10941 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10942
10943 fail:
10944 return ret;
10945 }
10946
10947 static void
10948 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
10949 {
10950 struct drm_crtc *crtc;
10951 struct drm_crtc_state *new_crtc_state;
10952 int i;
10953
10954 /* Double check state. */
10955 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10956 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
10957
10958 /*
10959 * Update legacy state to satisfy fbc code. This can
10960 * be removed when fbc uses the atomic state.
10961 */
10962 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
10963 struct drm_plane_state *plane_state = crtc->primary->state;
10964
10965 crtc->primary->fb = plane_state->fb;
10966 crtc->x = plane_state->src_x >> 16;
10967 crtc->y = plane_state->src_y >> 16;
10968 }
10969 }
10970 }
10971
10972 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10973 {
10974 int diff;
10975
10976 if (clock1 == clock2)
10977 return true;
10978
10979 if (!clock1 || !clock2)
10980 return false;
10981
10982 diff = abs(clock1 - clock2);
10983
10984 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10985 return true;
10986
10987 return false;
10988 }
10989
10990 static bool
10991 intel_compare_m_n(unsigned int m, unsigned int n,
10992 unsigned int m2, unsigned int n2,
10993 bool exact)
10994 {
10995 if (m == m2 && n == n2)
10996 return true;
10997
10998 if (exact || !m || !n || !m2 || !n2)
10999 return false;
11000
11001 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11002
11003 if (n > n2) {
11004 while (n > n2) {
11005 m2 <<= 1;
11006 n2 <<= 1;
11007 }
11008 } else if (n < n2) {
11009 while (n < n2) {
11010 m <<= 1;
11011 n <<= 1;
11012 }
11013 }
11014
11015 if (n != n2)
11016 return false;
11017
11018 return intel_fuzzy_clock_check(m, m2);
11019 }
11020
11021 static bool
11022 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11023 struct intel_link_m_n *m2_n2,
11024 bool adjust)
11025 {
11026 if (m_n->tu == m2_n2->tu &&
11027 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11028 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11029 intel_compare_m_n(m_n->link_m, m_n->link_n,
11030 m2_n2->link_m, m2_n2->link_n, !adjust)) {
11031 if (adjust)
11032 *m2_n2 = *m_n;
11033
11034 return true;
11035 }
11036
11037 return false;
11038 }
11039
11040 static void __printf(3, 4)
11041 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11042 {
11043 char *level;
11044 unsigned int category;
11045 struct va_format vaf;
11046 va_list args;
11047
11048 if (adjust) {
11049 level = KERN_DEBUG;
11050 category = DRM_UT_KMS;
11051 } else {
11052 level = KERN_ERR;
11053 category = DRM_UT_NONE;
11054 }
11055
11056 va_start(args, format);
11057 vaf.fmt = format;
11058 vaf.va = &args;
11059
11060 drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11061
11062 va_end(args);
11063 }
11064
11065 static bool
11066 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11067 struct intel_crtc_state *current_config,
11068 struct intel_crtc_state *pipe_config,
11069 bool adjust)
11070 {
11071 bool ret = true;
11072
11073 #define PIPE_CONF_CHECK_X(name) \
11074 if (current_config->name != pipe_config->name) { \
11075 pipe_config_err(adjust, __stringify(name), \
11076 "(expected 0x%08x, found 0x%08x)\n", \
11077 current_config->name, \
11078 pipe_config->name); \
11079 ret = false; \
11080 }
11081
11082 #define PIPE_CONF_CHECK_I(name) \
11083 if (current_config->name != pipe_config->name) { \
11084 pipe_config_err(adjust, __stringify(name), \
11085 "(expected %i, found %i)\n", \
11086 current_config->name, \
11087 pipe_config->name); \
11088 ret = false; \
11089 }
11090
11091 #define PIPE_CONF_CHECK_P(name) \
11092 if (current_config->name != pipe_config->name) { \
11093 pipe_config_err(adjust, __stringify(name), \
11094 "(expected %p, found %p)\n", \
11095 current_config->name, \
11096 pipe_config->name); \
11097 ret = false; \
11098 }
11099
11100 #define PIPE_CONF_CHECK_M_N(name) \
11101 if (!intel_compare_link_m_n(&current_config->name, \
11102 &pipe_config->name,\
11103 adjust)) { \
11104 pipe_config_err(adjust, __stringify(name), \
11105 "(expected tu %i gmch %i/%i link %i/%i, " \
11106 "found tu %i, gmch %i/%i link %i/%i)\n", \
11107 current_config->name.tu, \
11108 current_config->name.gmch_m, \
11109 current_config->name.gmch_n, \
11110 current_config->name.link_m, \
11111 current_config->name.link_n, \
11112 pipe_config->name.tu, \
11113 pipe_config->name.gmch_m, \
11114 pipe_config->name.gmch_n, \
11115 pipe_config->name.link_m, \
11116 pipe_config->name.link_n); \
11117 ret = false; \
11118 }
11119
11120 /* This is required for BDW+ where there is only one set of registers for
11121 * switching between high and low RR.
11122 * This macro can be used whenever a comparison has to be made between one
11123 * hw state and multiple sw state variables.
11124 */
11125 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11126 if (!intel_compare_link_m_n(&current_config->name, \
11127 &pipe_config->name, adjust) && \
11128 !intel_compare_link_m_n(&current_config->alt_name, \
11129 &pipe_config->name, adjust)) { \
11130 pipe_config_err(adjust, __stringify(name), \
11131 "(expected tu %i gmch %i/%i link %i/%i, " \
11132 "or tu %i gmch %i/%i link %i/%i, " \
11133 "found tu %i, gmch %i/%i link %i/%i)\n", \
11134 current_config->name.tu, \
11135 current_config->name.gmch_m, \
11136 current_config->name.gmch_n, \
11137 current_config->name.link_m, \
11138 current_config->name.link_n, \
11139 current_config->alt_name.tu, \
11140 current_config->alt_name.gmch_m, \
11141 current_config->alt_name.gmch_n, \
11142 current_config->alt_name.link_m, \
11143 current_config->alt_name.link_n, \
11144 pipe_config->name.tu, \
11145 pipe_config->name.gmch_m, \
11146 pipe_config->name.gmch_n, \
11147 pipe_config->name.link_m, \
11148 pipe_config->name.link_n); \
11149 ret = false; \
11150 }
11151
11152 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11153 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11154 pipe_config_err(adjust, __stringify(name), \
11155 "(%x) (expected %i, found %i)\n", \
11156 (mask), \
11157 current_config->name & (mask), \
11158 pipe_config->name & (mask)); \
11159 ret = false; \
11160 }
11161
11162 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11163 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11164 pipe_config_err(adjust, __stringify(name), \
11165 "(expected %i, found %i)\n", \
11166 current_config->name, \
11167 pipe_config->name); \
11168 ret = false; \
11169 }
11170
11171 #define PIPE_CONF_QUIRK(quirk) \
11172 ((current_config->quirks | pipe_config->quirks) & (quirk))
11173
11174 PIPE_CONF_CHECK_I(cpu_transcoder);
11175
11176 PIPE_CONF_CHECK_I(has_pch_encoder);
11177 PIPE_CONF_CHECK_I(fdi_lanes);
11178 PIPE_CONF_CHECK_M_N(fdi_m_n);
11179
11180 PIPE_CONF_CHECK_I(lane_count);
11181 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11182
11183 if (INTEL_GEN(dev_priv) < 8) {
11184 PIPE_CONF_CHECK_M_N(dp_m_n);
11185
11186 if (current_config->has_drrs)
11187 PIPE_CONF_CHECK_M_N(dp_m2_n2);
11188 } else
11189 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11190
11191 PIPE_CONF_CHECK_X(output_types);
11192
11193 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11194 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11195 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11196 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11197 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11198 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11199
11200 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11201 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11202 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11203 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11204 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11205 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11206
11207 PIPE_CONF_CHECK_I(pixel_multiplier);
11208 PIPE_CONF_CHECK_I(has_hdmi_sink);
11209 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11210 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11211 PIPE_CONF_CHECK_I(limited_color_range);
11212
11213 PIPE_CONF_CHECK_I(hdmi_scrambling);
11214 PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio);
11215 PIPE_CONF_CHECK_I(has_infoframe);
11216 PIPE_CONF_CHECK_I(ycbcr420);
11217
11218 PIPE_CONF_CHECK_I(has_audio);
11219
11220 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11221 DRM_MODE_FLAG_INTERLACE);
11222
11223 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11224 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11225 DRM_MODE_FLAG_PHSYNC);
11226 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11227 DRM_MODE_FLAG_NHSYNC);
11228 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11229 DRM_MODE_FLAG_PVSYNC);
11230 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11231 DRM_MODE_FLAG_NVSYNC);
11232 }
11233
11234 PIPE_CONF_CHECK_X(gmch_pfit.control);
11235 /* pfit ratios are autocomputed by the hw on gen4+ */
11236 if (INTEL_GEN(dev_priv) < 4)
11237 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11238 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11239
11240 if (!adjust) {
11241 PIPE_CONF_CHECK_I(pipe_src_w);
11242 PIPE_CONF_CHECK_I(pipe_src_h);
11243
11244 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11245 if (current_config->pch_pfit.enabled) {
11246 PIPE_CONF_CHECK_X(pch_pfit.pos);
11247 PIPE_CONF_CHECK_X(pch_pfit.size);
11248 }
11249
11250 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11251 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11252 }
11253
11254 /* BDW+ don't expose a synchronous way to read the state */
11255 if (IS_HASWELL(dev_priv))
11256 PIPE_CONF_CHECK_I(ips_enabled);
11257
11258 PIPE_CONF_CHECK_I(double_wide);
11259
11260 PIPE_CONF_CHECK_P(shared_dpll);
11261 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11262 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11263 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11264 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11265 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11266 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11267 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11268 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11269 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11270 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
11271 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
11272 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
11273 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
11274 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
11275 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
11276 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
11277 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
11278 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
11279 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
11280 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
11281 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
11282
11283 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11284 PIPE_CONF_CHECK_X(dsi_pll.div);
11285
11286 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11287 PIPE_CONF_CHECK_I(pipe_bpp);
11288
11289 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11290 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11291
11292 #undef PIPE_CONF_CHECK_X
11293 #undef PIPE_CONF_CHECK_I
11294 #undef PIPE_CONF_CHECK_P
11295 #undef PIPE_CONF_CHECK_FLAGS
11296 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11297 #undef PIPE_CONF_QUIRK
11298
11299 return ret;
11300 }
11301
11302 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11303 const struct intel_crtc_state *pipe_config)
11304 {
11305 if (pipe_config->has_pch_encoder) {
11306 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11307 &pipe_config->fdi_m_n);
11308 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11309
11310 /*
11311 * FDI already provided one idea for the dotclock.
11312 * Yell if the encoder disagrees.
11313 */
11314 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11315 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11316 fdi_dotclock, dotclock);
11317 }
11318 }
11319
11320 static void verify_wm_state(struct drm_crtc *crtc,
11321 struct drm_crtc_state *new_state)
11322 {
11323 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11324 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11325 struct skl_pipe_wm hw_wm, *sw_wm;
11326 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11327 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11329 const enum pipe pipe = intel_crtc->pipe;
11330 int plane, level, max_level = ilk_wm_max_level(dev_priv);
11331
11332 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11333 return;
11334
11335 skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11336 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11337
11338 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11339 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11340
11341 /* planes */
11342 for_each_universal_plane(dev_priv, pipe, plane) {
11343 hw_plane_wm = &hw_wm.planes[plane];
11344 sw_plane_wm = &sw_wm->planes[plane];
11345
11346 /* Watermarks */
11347 for (level = 0; level <= max_level; level++) {
11348 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11349 &sw_plane_wm->wm[level]))
11350 continue;
11351
11352 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11353 pipe_name(pipe), plane + 1, level,
11354 sw_plane_wm->wm[level].plane_en,
11355 sw_plane_wm->wm[level].plane_res_b,
11356 sw_plane_wm->wm[level].plane_res_l,
11357 hw_plane_wm->wm[level].plane_en,
11358 hw_plane_wm->wm[level].plane_res_b,
11359 hw_plane_wm->wm[level].plane_res_l);
11360 }
11361
11362 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11363 &sw_plane_wm->trans_wm)) {
11364 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11365 pipe_name(pipe), plane + 1,
11366 sw_plane_wm->trans_wm.plane_en,
11367 sw_plane_wm->trans_wm.plane_res_b,
11368 sw_plane_wm->trans_wm.plane_res_l,
11369 hw_plane_wm->trans_wm.plane_en,
11370 hw_plane_wm->trans_wm.plane_res_b,
11371 hw_plane_wm->trans_wm.plane_res_l);
11372 }
11373
11374 /* DDB */
11375 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11376 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11377
11378 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11379 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11380 pipe_name(pipe), plane + 1,
11381 sw_ddb_entry->start, sw_ddb_entry->end,
11382 hw_ddb_entry->start, hw_ddb_entry->end);
11383 }
11384 }
11385
11386 /*
11387 * cursor
11388 * If the cursor plane isn't active, we may not have updated it's ddb
11389 * allocation. In that case since the ddb allocation will be updated
11390 * once the plane becomes visible, we can skip this check
11391 */
11392 if (1) {
11393 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11394 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11395
11396 /* Watermarks */
11397 for (level = 0; level <= max_level; level++) {
11398 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11399 &sw_plane_wm->wm[level]))
11400 continue;
11401
11402 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11403 pipe_name(pipe), level,
11404 sw_plane_wm->wm[level].plane_en,
11405 sw_plane_wm->wm[level].plane_res_b,
11406 sw_plane_wm->wm[level].plane_res_l,
11407 hw_plane_wm->wm[level].plane_en,
11408 hw_plane_wm->wm[level].plane_res_b,
11409 hw_plane_wm->wm[level].plane_res_l);
11410 }
11411
11412 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11413 &sw_plane_wm->trans_wm)) {
11414 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11415 pipe_name(pipe),
11416 sw_plane_wm->trans_wm.plane_en,
11417 sw_plane_wm->trans_wm.plane_res_b,
11418 sw_plane_wm->trans_wm.plane_res_l,
11419 hw_plane_wm->trans_wm.plane_en,
11420 hw_plane_wm->trans_wm.plane_res_b,
11421 hw_plane_wm->trans_wm.plane_res_l);
11422 }
11423
11424 /* DDB */
11425 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11426 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11427
11428 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11429 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11430 pipe_name(pipe),
11431 sw_ddb_entry->start, sw_ddb_entry->end,
11432 hw_ddb_entry->start, hw_ddb_entry->end);
11433 }
11434 }
11435 }
11436
11437 static void
11438 verify_connector_state(struct drm_device *dev,
11439 struct drm_atomic_state *state,
11440 struct drm_crtc *crtc)
11441 {
11442 struct drm_connector *connector;
11443 struct drm_connector_state *new_conn_state;
11444 int i;
11445
11446 for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11447 struct drm_encoder *encoder = connector->encoder;
11448 struct drm_crtc_state *crtc_state = NULL;
11449
11450 if (new_conn_state->crtc != crtc)
11451 continue;
11452
11453 if (crtc)
11454 crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
11455
11456 intel_connector_verify_state(crtc_state, new_conn_state);
11457
11458 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11459 "connector's atomic encoder doesn't match legacy encoder\n");
11460 }
11461 }
11462
11463 static void
11464 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11465 {
11466 struct intel_encoder *encoder;
11467 struct drm_connector *connector;
11468 struct drm_connector_state *old_conn_state, *new_conn_state;
11469 int i;
11470
11471 for_each_intel_encoder(dev, encoder) {
11472 bool enabled = false, found = false;
11473 enum pipe pipe;
11474
11475 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11476 encoder->base.base.id,
11477 encoder->base.name);
11478
11479 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11480 new_conn_state, i) {
11481 if (old_conn_state->best_encoder == &encoder->base)
11482 found = true;
11483
11484 if (new_conn_state->best_encoder != &encoder->base)
11485 continue;
11486 found = enabled = true;
11487
11488 I915_STATE_WARN(new_conn_state->crtc !=
11489 encoder->base.crtc,
11490 "connector's crtc doesn't match encoder crtc\n");
11491 }
11492
11493 if (!found)
11494 continue;
11495
11496 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11497 "encoder's enabled state mismatch "
11498 "(expected %i, found %i)\n",
11499 !!encoder->base.crtc, enabled);
11500
11501 if (!encoder->base.crtc) {
11502 bool active;
11503
11504 active = encoder->get_hw_state(encoder, &pipe);
11505 I915_STATE_WARN(active,
11506 "encoder detached but still enabled on pipe %c.\n",
11507 pipe_name(pipe));
11508 }
11509 }
11510 }
11511
11512 static void
11513 verify_crtc_state(struct drm_crtc *crtc,
11514 struct drm_crtc_state *old_crtc_state,
11515 struct drm_crtc_state *new_crtc_state)
11516 {
11517 struct drm_device *dev = crtc->dev;
11518 struct drm_i915_private *dev_priv = to_i915(dev);
11519 struct intel_encoder *encoder;
11520 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11521 struct intel_crtc_state *pipe_config, *sw_config;
11522 struct drm_atomic_state *old_state;
11523 bool active;
11524
11525 old_state = old_crtc_state->state;
11526 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
11527 pipe_config = to_intel_crtc_state(old_crtc_state);
11528 memset(pipe_config, 0, sizeof(*pipe_config));
11529 pipe_config->base.crtc = crtc;
11530 pipe_config->base.state = old_state;
11531
11532 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
11533
11534 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
11535
11536 /* we keep both pipes enabled on 830 */
11537 if (IS_I830(dev_priv))
11538 active = new_crtc_state->active;
11539
11540 I915_STATE_WARN(new_crtc_state->active != active,
11541 "crtc active state doesn't match with hw state "
11542 "(expected %i, found %i)\n", new_crtc_state->active, active);
11543
11544 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
11545 "transitional active state does not match atomic hw state "
11546 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
11547
11548 for_each_encoder_on_crtc(dev, crtc, encoder) {
11549 enum pipe pipe;
11550
11551 active = encoder->get_hw_state(encoder, &pipe);
11552 I915_STATE_WARN(active != new_crtc_state->active,
11553 "[ENCODER:%i] active %i with crtc active %i\n",
11554 encoder->base.base.id, active, new_crtc_state->active);
11555
11556 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
11557 "Encoder connected to wrong pipe %c\n",
11558 pipe_name(pipe));
11559
11560 if (active) {
11561 pipe_config->output_types |= 1 << encoder->type;
11562 encoder->get_config(encoder, pipe_config);
11563 }
11564 }
11565
11566 intel_crtc_compute_pixel_rate(pipe_config);
11567
11568 if (!new_crtc_state->active)
11569 return;
11570
11571 intel_pipe_config_sanity_check(dev_priv, pipe_config);
11572
11573 sw_config = to_intel_crtc_state(new_crtc_state);
11574 if (!intel_pipe_config_compare(dev_priv, sw_config,
11575 pipe_config, false)) {
11576 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11577 intel_dump_pipe_config(intel_crtc, pipe_config,
11578 "[hw state]");
11579 intel_dump_pipe_config(intel_crtc, sw_config,
11580 "[sw state]");
11581 }
11582 }
11583
11584 static void
11585 verify_single_dpll_state(struct drm_i915_private *dev_priv,
11586 struct intel_shared_dpll *pll,
11587 struct drm_crtc *crtc,
11588 struct drm_crtc_state *new_state)
11589 {
11590 struct intel_dpll_hw_state dpll_hw_state;
11591 unsigned crtc_mask;
11592 bool active;
11593
11594 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11595
11596 DRM_DEBUG_KMS("%s\n", pll->name);
11597
11598 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
11599
11600 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
11601 I915_STATE_WARN(!pll->on && pll->active_mask,
11602 "pll in active use but not on in sw tracking\n");
11603 I915_STATE_WARN(pll->on && !pll->active_mask,
11604 "pll is on but not used by any active crtc\n");
11605 I915_STATE_WARN(pll->on != active,
11606 "pll on state mismatch (expected %i, found %i)\n",
11607 pll->on, active);
11608 }
11609
11610 if (!crtc) {
11611 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
11612 "more active pll users than references: %x vs %x\n",
11613 pll->active_mask, pll->state.crtc_mask);
11614
11615 return;
11616 }
11617
11618 crtc_mask = 1 << drm_crtc_index(crtc);
11619
11620 if (new_state->active)
11621 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
11622 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
11623 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11624 else
11625 I915_STATE_WARN(pll->active_mask & crtc_mask,
11626 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
11627 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11628
11629 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
11630 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
11631 crtc_mask, pll->state.crtc_mask);
11632
11633 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
11634 &dpll_hw_state,
11635 sizeof(dpll_hw_state)),
11636 "pll hw state mismatch\n");
11637 }
11638
11639 static void
11640 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
11641 struct drm_crtc_state *old_crtc_state,
11642 struct drm_crtc_state *new_crtc_state)
11643 {
11644 struct drm_i915_private *dev_priv = to_i915(dev);
11645 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
11646 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
11647
11648 if (new_state->shared_dpll)
11649 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
11650
11651 if (old_state->shared_dpll &&
11652 old_state->shared_dpll != new_state->shared_dpll) {
11653 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
11654 struct intel_shared_dpll *pll = old_state->shared_dpll;
11655
11656 I915_STATE_WARN(pll->active_mask & crtc_mask,
11657 "pll active mismatch (didn't expect pipe %c in active mask)\n",
11658 pipe_name(drm_crtc_index(crtc)));
11659 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
11660 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
11661 pipe_name(drm_crtc_index(crtc)));
11662 }
11663 }
11664
11665 static void
11666 intel_modeset_verify_crtc(struct drm_crtc *crtc,
11667 struct drm_atomic_state *state,
11668 struct drm_crtc_state *old_state,
11669 struct drm_crtc_state *new_state)
11670 {
11671 if (!needs_modeset(new_state) &&
11672 !to_intel_crtc_state(new_state)->update_pipe)
11673 return;
11674
11675 verify_wm_state(crtc, new_state);
11676 verify_connector_state(crtc->dev, state, crtc);
11677 verify_crtc_state(crtc, old_state, new_state);
11678 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
11679 }
11680
11681 static void
11682 verify_disabled_dpll_state(struct drm_device *dev)
11683 {
11684 struct drm_i915_private *dev_priv = to_i915(dev);
11685 int i;
11686
11687 for (i = 0; i < dev_priv->num_shared_dpll; i++)
11688 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
11689 }
11690
11691 static void
11692 intel_modeset_verify_disabled(struct drm_device *dev,
11693 struct drm_atomic_state *state)
11694 {
11695 verify_encoder_state(dev, state);
11696 verify_connector_state(dev, state, NULL);
11697 verify_disabled_dpll_state(dev);
11698 }
11699
11700 static void update_scanline_offset(struct intel_crtc *crtc)
11701 {
11702 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11703
11704 /*
11705 * The scanline counter increments at the leading edge of hsync.
11706 *
11707 * On most platforms it starts counting from vtotal-1 on the
11708 * first active line. That means the scanline counter value is
11709 * always one less than what we would expect. Ie. just after
11710 * start of vblank, which also occurs at start of hsync (on the
11711 * last active line), the scanline counter will read vblank_start-1.
11712 *
11713 * On gen2 the scanline counter starts counting from 1 instead
11714 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11715 * to keep the value positive), instead of adding one.
11716 *
11717 * On HSW+ the behaviour of the scanline counter depends on the output
11718 * type. For DP ports it behaves like most other platforms, but on HDMI
11719 * there's an extra 1 line difference. So we need to add two instead of
11720 * one to the value.
11721 *
11722 * On VLV/CHV DSI the scanline counter would appear to increment
11723 * approx. 1/3 of a scanline before start of vblank. Unfortunately
11724 * that means we can't tell whether we're in vblank or not while
11725 * we're on that particular line. We must still set scanline_offset
11726 * to 1 so that the vblank timestamps come out correct when we query
11727 * the scanline counter from within the vblank interrupt handler.
11728 * However if queried just before the start of vblank we'll get an
11729 * answer that's slightly in the future.
11730 */
11731 if (IS_GEN2(dev_priv)) {
11732 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
11733 int vtotal;
11734
11735 vtotal = adjusted_mode->crtc_vtotal;
11736 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
11737 vtotal /= 2;
11738
11739 crtc->scanline_offset = vtotal - 1;
11740 } else if (HAS_DDI(dev_priv) &&
11741 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
11742 crtc->scanline_offset = 2;
11743 } else
11744 crtc->scanline_offset = 1;
11745 }
11746
11747 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
11748 {
11749 struct drm_device *dev = state->dev;
11750 struct drm_i915_private *dev_priv = to_i915(dev);
11751 struct drm_crtc *crtc;
11752 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11753 int i;
11754
11755 if (!dev_priv->display.crtc_compute_clock)
11756 return;
11757
11758 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11760 struct intel_shared_dpll *old_dpll =
11761 to_intel_crtc_state(old_crtc_state)->shared_dpll;
11762
11763 if (!needs_modeset(new_crtc_state))
11764 continue;
11765
11766 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
11767
11768 if (!old_dpll)
11769 continue;
11770
11771 intel_release_shared_dpll(old_dpll, intel_crtc, state);
11772 }
11773 }
11774
11775 /*
11776 * This implements the workaround described in the "notes" section of the mode
11777 * set sequence documentation. When going from no pipes or single pipe to
11778 * multiple pipes, and planes are enabled after the pipe, we need to wait at
11779 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
11780 */
11781 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
11782 {
11783 struct drm_crtc_state *crtc_state;
11784 struct intel_crtc *intel_crtc;
11785 struct drm_crtc *crtc;
11786 struct intel_crtc_state *first_crtc_state = NULL;
11787 struct intel_crtc_state *other_crtc_state = NULL;
11788 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
11789 int i;
11790
11791 /* look at all crtc's that are going to be enabled in during modeset */
11792 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
11793 intel_crtc = to_intel_crtc(crtc);
11794
11795 if (!crtc_state->active || !needs_modeset(crtc_state))
11796 continue;
11797
11798 if (first_crtc_state) {
11799 other_crtc_state = to_intel_crtc_state(crtc_state);
11800 break;
11801 } else {
11802 first_crtc_state = to_intel_crtc_state(crtc_state);
11803 first_pipe = intel_crtc->pipe;
11804 }
11805 }
11806
11807 /* No workaround needed? */
11808 if (!first_crtc_state)
11809 return 0;
11810
11811 /* w/a possibly needed, check how many crtc's are already enabled. */
11812 for_each_intel_crtc(state->dev, intel_crtc) {
11813 struct intel_crtc_state *pipe_config;
11814
11815 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
11816 if (IS_ERR(pipe_config))
11817 return PTR_ERR(pipe_config);
11818
11819 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
11820
11821 if (!pipe_config->base.active ||
11822 needs_modeset(&pipe_config->base))
11823 continue;
11824
11825 /* 2 or more enabled crtcs means no need for w/a */
11826 if (enabled_pipe != INVALID_PIPE)
11827 return 0;
11828
11829 enabled_pipe = intel_crtc->pipe;
11830 }
11831
11832 if (enabled_pipe != INVALID_PIPE)
11833 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
11834 else if (other_crtc_state)
11835 other_crtc_state->hsw_workaround_pipe = first_pipe;
11836
11837 return 0;
11838 }
11839
11840 static int intel_lock_all_pipes(struct drm_atomic_state *state)
11841 {
11842 struct drm_crtc *crtc;
11843
11844 /* Add all pipes to the state */
11845 for_each_crtc(state->dev, crtc) {
11846 struct drm_crtc_state *crtc_state;
11847
11848 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11849 if (IS_ERR(crtc_state))
11850 return PTR_ERR(crtc_state);
11851 }
11852
11853 return 0;
11854 }
11855
11856 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
11857 {
11858 struct drm_crtc *crtc;
11859
11860 /*
11861 * Add all pipes to the state, and force
11862 * a modeset on all the active ones.
11863 */
11864 for_each_crtc(state->dev, crtc) {
11865 struct drm_crtc_state *crtc_state;
11866 int ret;
11867
11868 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11869 if (IS_ERR(crtc_state))
11870 return PTR_ERR(crtc_state);
11871
11872 if (!crtc_state->active || needs_modeset(crtc_state))
11873 continue;
11874
11875 crtc_state->mode_changed = true;
11876
11877 ret = drm_atomic_add_affected_connectors(state, crtc);
11878 if (ret)
11879 return ret;
11880
11881 ret = drm_atomic_add_affected_planes(state, crtc);
11882 if (ret)
11883 return ret;
11884 }
11885
11886 return 0;
11887 }
11888
11889 static int intel_modeset_checks(struct drm_atomic_state *state)
11890 {
11891 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
11892 struct drm_i915_private *dev_priv = to_i915(state->dev);
11893 struct drm_crtc *crtc;
11894 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11895 int ret = 0, i;
11896
11897 if (!check_digital_port_conflicts(state)) {
11898 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11899 return -EINVAL;
11900 }
11901
11902 intel_state->modeset = true;
11903 intel_state->active_crtcs = dev_priv->active_crtcs;
11904 intel_state->cdclk.logical = dev_priv->cdclk.logical;
11905 intel_state->cdclk.actual = dev_priv->cdclk.actual;
11906
11907 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11908 if (new_crtc_state->active)
11909 intel_state->active_crtcs |= 1 << i;
11910 else
11911 intel_state->active_crtcs &= ~(1 << i);
11912
11913 if (old_crtc_state->active != new_crtc_state->active)
11914 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
11915 }
11916
11917 /*
11918 * See if the config requires any additional preparation, e.g.
11919 * to adjust global state with pipes off. We need to do this
11920 * here so we can get the modeset_pipe updated config for the new
11921 * mode set on this crtc. For other crtcs we need to use the
11922 * adjusted_mode bits in the crtc directly.
11923 */
11924 if (dev_priv->display.modeset_calc_cdclk) {
11925 ret = dev_priv->display.modeset_calc_cdclk(state);
11926 if (ret < 0)
11927 return ret;
11928
11929 /*
11930 * Writes to dev_priv->cdclk.logical must protected by
11931 * holding all the crtc locks, even if we don't end up
11932 * touching the hardware
11933 */
11934 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
11935 &intel_state->cdclk.logical)) {
11936 ret = intel_lock_all_pipes(state);
11937 if (ret < 0)
11938 return ret;
11939 }
11940
11941 /* All pipes must be switched off while we change the cdclk. */
11942 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
11943 &intel_state->cdclk.actual)) {
11944 ret = intel_modeset_all_pipes(state);
11945 if (ret < 0)
11946 return ret;
11947 }
11948
11949 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
11950 intel_state->cdclk.logical.cdclk,
11951 intel_state->cdclk.actual.cdclk);
11952 } else {
11953 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
11954 }
11955
11956 intel_modeset_clear_plls(state);
11957
11958 if (IS_HASWELL(dev_priv))
11959 return haswell_mode_set_planes_workaround(state);
11960
11961 return 0;
11962 }
11963
11964 /*
11965 * Handle calculation of various watermark data at the end of the atomic check
11966 * phase. The code here should be run after the per-crtc and per-plane 'check'
11967 * handlers to ensure that all derived state has been updated.
11968 */
11969 static int calc_watermark_data(struct drm_atomic_state *state)
11970 {
11971 struct drm_device *dev = state->dev;
11972 struct drm_i915_private *dev_priv = to_i915(dev);
11973
11974 /* Is there platform-specific watermark information to calculate? */
11975 if (dev_priv->display.compute_global_watermarks)
11976 return dev_priv->display.compute_global_watermarks(state);
11977
11978 return 0;
11979 }
11980
11981 /**
11982 * intel_atomic_check - validate state object
11983 * @dev: drm device
11984 * @state: state to validate
11985 */
11986 static int intel_atomic_check(struct drm_device *dev,
11987 struct drm_atomic_state *state)
11988 {
11989 struct drm_i915_private *dev_priv = to_i915(dev);
11990 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
11991 struct drm_crtc *crtc;
11992 struct drm_crtc_state *old_crtc_state, *crtc_state;
11993 int ret, i;
11994 bool any_ms = false;
11995
11996 ret = drm_atomic_helper_check_modeset(dev, state);
11997 if (ret)
11998 return ret;
11999
12000 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12001 struct intel_crtc_state *pipe_config =
12002 to_intel_crtc_state(crtc_state);
12003
12004 /* Catch I915_MODE_FLAG_INHERITED */
12005 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
12006 crtc_state->mode_changed = true;
12007
12008 if (!needs_modeset(crtc_state))
12009 continue;
12010
12011 if (!crtc_state->enable) {
12012 any_ms = true;
12013 continue;
12014 }
12015
12016 /* FIXME: For only active_changed we shouldn't need to do any
12017 * state recomputation at all. */
12018
12019 ret = drm_atomic_add_affected_connectors(state, crtc);
12020 if (ret)
12021 return ret;
12022
12023 ret = intel_modeset_pipe_config(crtc, pipe_config);
12024 if (ret) {
12025 intel_dump_pipe_config(to_intel_crtc(crtc),
12026 pipe_config, "[failed]");
12027 return ret;
12028 }
12029
12030 if (i915_modparams.fastboot &&
12031 intel_pipe_config_compare(dev_priv,
12032 to_intel_crtc_state(old_crtc_state),
12033 pipe_config, true)) {
12034 crtc_state->mode_changed = false;
12035 pipe_config->update_pipe = true;
12036 }
12037
12038 if (needs_modeset(crtc_state))
12039 any_ms = true;
12040
12041 ret = drm_atomic_add_affected_planes(state, crtc);
12042 if (ret)
12043 return ret;
12044
12045 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12046 needs_modeset(crtc_state) ?
12047 "[modeset]" : "[fastset]");
12048 }
12049
12050 if (any_ms) {
12051 ret = intel_modeset_checks(state);
12052
12053 if (ret)
12054 return ret;
12055 } else {
12056 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12057 }
12058
12059 ret = drm_atomic_helper_check_planes(dev, state);
12060 if (ret)
12061 return ret;
12062
12063 intel_fbc_choose_crtc(dev_priv, state);
12064 return calc_watermark_data(state);
12065 }
12066
12067 static int intel_atomic_prepare_commit(struct drm_device *dev,
12068 struct drm_atomic_state *state)
12069 {
12070 return drm_atomic_helper_prepare_planes(dev, state);
12071 }
12072
12073 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12074 {
12075 struct drm_device *dev = crtc->base.dev;
12076
12077 if (!dev->max_vblank_count)
12078 return drm_crtc_accurate_vblank_count(&crtc->base);
12079
12080 return dev->driver->get_vblank_counter(dev, crtc->pipe);
12081 }
12082
12083 static void intel_update_crtc(struct drm_crtc *crtc,
12084 struct drm_atomic_state *state,
12085 struct drm_crtc_state *old_crtc_state,
12086 struct drm_crtc_state *new_crtc_state)
12087 {
12088 struct drm_device *dev = crtc->dev;
12089 struct drm_i915_private *dev_priv = to_i915(dev);
12090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12091 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12092 bool modeset = needs_modeset(new_crtc_state);
12093
12094 if (modeset) {
12095 update_scanline_offset(intel_crtc);
12096 dev_priv->display.crtc_enable(pipe_config, state);
12097 } else {
12098 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12099 pipe_config);
12100 }
12101
12102 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12103 intel_fbc_enable(
12104 intel_crtc, pipe_config,
12105 to_intel_plane_state(crtc->primary->state));
12106 }
12107
12108 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12109 }
12110
12111 static void intel_update_crtcs(struct drm_atomic_state *state)
12112 {
12113 struct drm_crtc *crtc;
12114 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12115 int i;
12116
12117 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12118 if (!new_crtc_state->active)
12119 continue;
12120
12121 intel_update_crtc(crtc, state, old_crtc_state,
12122 new_crtc_state);
12123 }
12124 }
12125
12126 static void skl_update_crtcs(struct drm_atomic_state *state)
12127 {
12128 struct drm_i915_private *dev_priv = to_i915(state->dev);
12129 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12130 struct drm_crtc *crtc;
12131 struct intel_crtc *intel_crtc;
12132 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12133 struct intel_crtc_state *cstate;
12134 unsigned int updated = 0;
12135 bool progress;
12136 enum pipe pipe;
12137 int i;
12138
12139 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12140
12141 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12142 /* ignore allocations for crtc's that have been turned off. */
12143 if (new_crtc_state->active)
12144 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12145
12146 /*
12147 * Whenever the number of active pipes changes, we need to make sure we
12148 * update the pipes in the right order so that their ddb allocations
12149 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12150 * cause pipe underruns and other bad stuff.
12151 */
12152 do {
12153 progress = false;
12154
12155 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12156 bool vbl_wait = false;
12157 unsigned int cmask = drm_crtc_mask(crtc);
12158
12159 intel_crtc = to_intel_crtc(crtc);
12160 cstate = to_intel_crtc_state(new_crtc_state);
12161 pipe = intel_crtc->pipe;
12162
12163 if (updated & cmask || !cstate->base.active)
12164 continue;
12165
12166 if (skl_ddb_allocation_overlaps(dev_priv,
12167 entries,
12168 &cstate->wm.skl.ddb,
12169 i))
12170 continue;
12171
12172 updated |= cmask;
12173 entries[i] = &cstate->wm.skl.ddb;
12174
12175 /*
12176 * If this is an already active pipe, it's DDB changed,
12177 * and this isn't the last pipe that needs updating
12178 * then we need to wait for a vblank to pass for the
12179 * new ddb allocation to take effect.
12180 */
12181 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12182 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12183 !new_crtc_state->active_changed &&
12184 intel_state->wm_results.dirty_pipes != updated)
12185 vbl_wait = true;
12186
12187 intel_update_crtc(crtc, state, old_crtc_state,
12188 new_crtc_state);
12189
12190 if (vbl_wait)
12191 intel_wait_for_vblank(dev_priv, pipe);
12192
12193 progress = true;
12194 }
12195 } while (progress);
12196 }
12197
12198 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12199 {
12200 struct intel_atomic_state *state, *next;
12201 struct llist_node *freed;
12202
12203 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12204 llist_for_each_entry_safe(state, next, freed, freed)
12205 drm_atomic_state_put(&state->base);
12206 }
12207
12208 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12209 {
12210 struct drm_i915_private *dev_priv =
12211 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12212
12213 intel_atomic_helper_free_state(dev_priv);
12214 }
12215
12216 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
12217 {
12218 struct wait_queue_entry wait_fence, wait_reset;
12219 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
12220
12221 init_wait_entry(&wait_fence, 0);
12222 init_wait_entry(&wait_reset, 0);
12223 for (;;) {
12224 prepare_to_wait(&intel_state->commit_ready.wait,
12225 &wait_fence, TASK_UNINTERRUPTIBLE);
12226 prepare_to_wait(&dev_priv->gpu_error.wait_queue,
12227 &wait_reset, TASK_UNINTERRUPTIBLE);
12228
12229
12230 if (i915_sw_fence_done(&intel_state->commit_ready)
12231 || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
12232 break;
12233
12234 schedule();
12235 }
12236 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
12237 finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset);
12238 }
12239
12240 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12241 {
12242 struct drm_device *dev = state->dev;
12243 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12244 struct drm_i915_private *dev_priv = to_i915(dev);
12245 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12246 struct drm_crtc *crtc;
12247 struct intel_crtc_state *intel_cstate;
12248 u64 put_domains[I915_MAX_PIPES] = {};
12249 int i;
12250
12251 intel_atomic_commit_fence_wait(intel_state);
12252
12253 drm_atomic_helper_wait_for_dependencies(state);
12254
12255 if (intel_state->modeset)
12256 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12257
12258 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12260
12261 if (needs_modeset(new_crtc_state) ||
12262 to_intel_crtc_state(new_crtc_state)->update_pipe) {
12263
12264 put_domains[to_intel_crtc(crtc)->pipe] =
12265 modeset_get_crtc_power_domains(crtc,
12266 to_intel_crtc_state(new_crtc_state));
12267 }
12268
12269 if (!needs_modeset(new_crtc_state))
12270 continue;
12271
12272 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12273 to_intel_crtc_state(new_crtc_state));
12274
12275 if (old_crtc_state->active) {
12276 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12277 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12278 intel_crtc->active = false;
12279 intel_fbc_disable(intel_crtc);
12280 intel_disable_shared_dpll(intel_crtc);
12281
12282 /*
12283 * Underruns don't always raise
12284 * interrupts, so check manually.
12285 */
12286 intel_check_cpu_fifo_underruns(dev_priv);
12287 intel_check_pch_fifo_underruns(dev_priv);
12288
12289 if (!new_crtc_state->active) {
12290 /*
12291 * Make sure we don't call initial_watermarks
12292 * for ILK-style watermark updates.
12293 *
12294 * No clue what this is supposed to achieve.
12295 */
12296 if (INTEL_GEN(dev_priv) >= 9)
12297 dev_priv->display.initial_watermarks(intel_state,
12298 to_intel_crtc_state(new_crtc_state));
12299 }
12300 }
12301 }
12302
12303 /* Only after disabling all output pipelines that will be changed can we
12304 * update the the output configuration. */
12305 intel_modeset_update_crtc_state(state);
12306
12307 if (intel_state->modeset) {
12308 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12309
12310 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12311
12312 /*
12313 * SKL workaround: bspec recommends we disable the SAGV when we
12314 * have more then one pipe enabled
12315 */
12316 if (!intel_can_enable_sagv(state))
12317 intel_disable_sagv(dev_priv);
12318
12319 intel_modeset_verify_disabled(dev, state);
12320 }
12321
12322 /* Complete the events for pipes that have now been disabled */
12323 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12324 bool modeset = needs_modeset(new_crtc_state);
12325
12326 /* Complete events for now disable pipes here. */
12327 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12328 spin_lock_irq(&dev->event_lock);
12329 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12330 spin_unlock_irq(&dev->event_lock);
12331
12332 new_crtc_state->event = NULL;
12333 }
12334 }
12335
12336 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12337 dev_priv->display.update_crtcs(state);
12338
12339 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12340 * already, but still need the state for the delayed optimization. To
12341 * fix this:
12342 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12343 * - schedule that vblank worker _before_ calling hw_done
12344 * - at the start of commit_tail, cancel it _synchrously
12345 * - switch over to the vblank wait helper in the core after that since
12346 * we don't need out special handling any more.
12347 */
12348 drm_atomic_helper_wait_for_flip_done(dev, state);
12349
12350 /*
12351 * Now that the vblank has passed, we can go ahead and program the
12352 * optimal watermarks on platforms that need two-step watermark
12353 * programming.
12354 *
12355 * TODO: Move this (and other cleanup) to an async worker eventually.
12356 */
12357 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12358 intel_cstate = to_intel_crtc_state(new_crtc_state);
12359
12360 if (dev_priv->display.optimize_watermarks)
12361 dev_priv->display.optimize_watermarks(intel_state,
12362 intel_cstate);
12363 }
12364
12365 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12366 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12367
12368 if (put_domains[i])
12369 modeset_put_power_domains(dev_priv, put_domains[i]);
12370
12371 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12372 }
12373
12374 if (intel_state->modeset && intel_can_enable_sagv(state))
12375 intel_enable_sagv(dev_priv);
12376
12377 drm_atomic_helper_commit_hw_done(state);
12378
12379 if (intel_state->modeset) {
12380 /* As one of the primary mmio accessors, KMS has a high
12381 * likelihood of triggering bugs in unclaimed access. After we
12382 * finish modesetting, see if an error has been flagged, and if
12383 * so enable debugging for the next modeset - and hope we catch
12384 * the culprit.
12385 */
12386 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12387 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12388 }
12389
12390 drm_atomic_helper_cleanup_planes(dev, state);
12391
12392 drm_atomic_helper_commit_cleanup_done(state);
12393
12394 drm_atomic_state_put(state);
12395
12396 intel_atomic_helper_free_state(dev_priv);
12397 }
12398
12399 static void intel_atomic_commit_work(struct work_struct *work)
12400 {
12401 struct drm_atomic_state *state =
12402 container_of(work, struct drm_atomic_state, commit_work);
12403
12404 intel_atomic_commit_tail(state);
12405 }
12406
12407 static int __i915_sw_fence_call
12408 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12409 enum i915_sw_fence_notify notify)
12410 {
12411 struct intel_atomic_state *state =
12412 container_of(fence, struct intel_atomic_state, commit_ready);
12413
12414 switch (notify) {
12415 case FENCE_COMPLETE:
12416 /* we do blocking waits in the worker, nothing to do here */
12417 break;
12418 case FENCE_FREE:
12419 {
12420 struct intel_atomic_helper *helper =
12421 &to_i915(state->base.dev)->atomic_helper;
12422
12423 if (llist_add(&state->freed, &helper->free_list))
12424 schedule_work(&helper->free_work);
12425 break;
12426 }
12427 }
12428
12429 return NOTIFY_DONE;
12430 }
12431
12432 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12433 {
12434 struct drm_plane_state *old_plane_state, *new_plane_state;
12435 struct drm_plane *plane;
12436 int i;
12437
12438 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
12439 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
12440 intel_fb_obj(new_plane_state->fb),
12441 to_intel_plane(plane)->frontbuffer_bit);
12442 }
12443
12444 /**
12445 * intel_atomic_commit - commit validated state object
12446 * @dev: DRM device
12447 * @state: the top-level driver state object
12448 * @nonblock: nonblocking commit
12449 *
12450 * This function commits a top-level state object that has been validated
12451 * with drm_atomic_helper_check().
12452 *
12453 * RETURNS
12454 * Zero for success or -errno.
12455 */
12456 static int intel_atomic_commit(struct drm_device *dev,
12457 struct drm_atomic_state *state,
12458 bool nonblock)
12459 {
12460 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12461 struct drm_i915_private *dev_priv = to_i915(dev);
12462 int ret = 0;
12463
12464 drm_atomic_state_get(state);
12465 i915_sw_fence_init(&intel_state->commit_ready,
12466 intel_atomic_commit_ready);
12467
12468 /*
12469 * The intel_legacy_cursor_update() fast path takes care
12470 * of avoiding the vblank waits for simple cursor
12471 * movement and flips. For cursor on/off and size changes,
12472 * we want to perform the vblank waits so that watermark
12473 * updates happen during the correct frames. Gen9+ have
12474 * double buffered watermarks and so shouldn't need this.
12475 *
12476 * Unset state->legacy_cursor_update before the call to
12477 * drm_atomic_helper_setup_commit() because otherwise
12478 * drm_atomic_helper_wait_for_flip_done() is a noop and
12479 * we get FIFO underruns because we didn't wait
12480 * for vblank.
12481 *
12482 * FIXME doing watermarks and fb cleanup from a vblank worker
12483 * (assuming we had any) would solve these problems.
12484 */
12485 if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
12486 struct intel_crtc_state *new_crtc_state;
12487 struct intel_crtc *crtc;
12488 int i;
12489
12490 for_each_new_intel_crtc_in_state(intel_state, crtc, new_crtc_state, i)
12491 if (new_crtc_state->wm.need_postvbl_update ||
12492 new_crtc_state->update_wm_post)
12493 state->legacy_cursor_update = false;
12494 }
12495
12496 ret = intel_atomic_prepare_commit(dev, state);
12497 if (ret) {
12498 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
12499 i915_sw_fence_commit(&intel_state->commit_ready);
12500 return ret;
12501 }
12502
12503 ret = drm_atomic_helper_setup_commit(state, nonblock);
12504 if (!ret)
12505 ret = drm_atomic_helper_swap_state(state, true);
12506
12507 if (ret) {
12508 i915_sw_fence_commit(&intel_state->commit_ready);
12509
12510 drm_atomic_helper_cleanup_planes(dev, state);
12511 return ret;
12512 }
12513 dev_priv->wm.distrust_bios_wm = false;
12514 intel_shared_dpll_swap_state(state);
12515 intel_atomic_track_fbs(state);
12516
12517 if (intel_state->modeset) {
12518 memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
12519 sizeof(intel_state->min_cdclk));
12520 dev_priv->active_crtcs = intel_state->active_crtcs;
12521 dev_priv->cdclk.logical = intel_state->cdclk.logical;
12522 dev_priv->cdclk.actual = intel_state->cdclk.actual;
12523 }
12524
12525 drm_atomic_state_get(state);
12526 INIT_WORK(&state->commit_work, intel_atomic_commit_work);
12527
12528 i915_sw_fence_commit(&intel_state->commit_ready);
12529 if (nonblock)
12530 queue_work(system_unbound_wq, &state->commit_work);
12531 else
12532 intel_atomic_commit_tail(state);
12533
12534
12535 return 0;
12536 }
12537
12538 static const struct drm_crtc_funcs intel_crtc_funcs = {
12539 .gamma_set = drm_atomic_helper_legacy_gamma_set,
12540 .set_config = drm_atomic_helper_set_config,
12541 .destroy = intel_crtc_destroy,
12542 .page_flip = drm_atomic_helper_page_flip,
12543 .atomic_duplicate_state = intel_crtc_duplicate_state,
12544 .atomic_destroy_state = intel_crtc_destroy_state,
12545 .set_crc_source = intel_crtc_set_crc_source,
12546 };
12547
12548 struct wait_rps_boost {
12549 struct wait_queue_entry wait;
12550
12551 struct drm_crtc *crtc;
12552 struct drm_i915_gem_request *request;
12553 };
12554
12555 static int do_rps_boost(struct wait_queue_entry *_wait,
12556 unsigned mode, int sync, void *key)
12557 {
12558 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
12559 struct drm_i915_gem_request *rq = wait->request;
12560
12561 gen6_rps_boost(rq, NULL);
12562 i915_gem_request_put(rq);
12563
12564 drm_crtc_vblank_put(wait->crtc);
12565
12566 list_del(&wait->wait.entry);
12567 kfree(wait);
12568 return 1;
12569 }
12570
12571 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
12572 struct dma_fence *fence)
12573 {
12574 struct wait_rps_boost *wait;
12575
12576 if (!dma_fence_is_i915(fence))
12577 return;
12578
12579 if (INTEL_GEN(to_i915(crtc->dev)) < 6)
12580 return;
12581
12582 if (drm_crtc_vblank_get(crtc))
12583 return;
12584
12585 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
12586 if (!wait) {
12587 drm_crtc_vblank_put(crtc);
12588 return;
12589 }
12590
12591 wait->request = to_request(dma_fence_get(fence));
12592 wait->crtc = crtc;
12593
12594 wait->wait.func = do_rps_boost;
12595 wait->wait.flags = 0;
12596
12597 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
12598 }
12599
12600 /**
12601 * intel_prepare_plane_fb - Prepare fb for usage on plane
12602 * @plane: drm plane to prepare for
12603 * @fb: framebuffer to prepare for presentation
12604 *
12605 * Prepares a framebuffer for usage on a display plane. Generally this
12606 * involves pinning the underlying object and updating the frontbuffer tracking
12607 * bits. Some older platforms need special physical address handling for
12608 * cursor planes.
12609 *
12610 * Must be called with struct_mutex held.
12611 *
12612 * Returns 0 on success, negative error code on failure.
12613 */
12614 int
12615 intel_prepare_plane_fb(struct drm_plane *plane,
12616 struct drm_plane_state *new_state)
12617 {
12618 struct intel_atomic_state *intel_state =
12619 to_intel_atomic_state(new_state->state);
12620 struct drm_i915_private *dev_priv = to_i915(plane->dev);
12621 struct drm_framebuffer *fb = new_state->fb;
12622 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12623 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
12624 int ret;
12625
12626 if (old_obj) {
12627 struct drm_crtc_state *crtc_state =
12628 drm_atomic_get_existing_crtc_state(new_state->state,
12629 plane->state->crtc);
12630
12631 /* Big Hammer, we also need to ensure that any pending
12632 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
12633 * current scanout is retired before unpinning the old
12634 * framebuffer. Note that we rely on userspace rendering
12635 * into the buffer attached to the pipe they are waiting
12636 * on. If not, userspace generates a GPU hang with IPEHR
12637 * point to the MI_WAIT_FOR_EVENT.
12638 *
12639 * This should only fail upon a hung GPU, in which case we
12640 * can safely continue.
12641 */
12642 if (needs_modeset(crtc_state)) {
12643 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12644 old_obj->resv, NULL,
12645 false, 0,
12646 GFP_KERNEL);
12647 if (ret < 0)
12648 return ret;
12649 }
12650 }
12651
12652 if (new_state->fence) { /* explicit fencing */
12653 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
12654 new_state->fence,
12655 I915_FENCE_TIMEOUT,
12656 GFP_KERNEL);
12657 if (ret < 0)
12658 return ret;
12659 }
12660
12661 if (!obj)
12662 return 0;
12663
12664 ret = i915_gem_object_pin_pages(obj);
12665 if (ret)
12666 return ret;
12667
12668 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
12669 if (ret) {
12670 i915_gem_object_unpin_pages(obj);
12671 return ret;
12672 }
12673
12674 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12675 INTEL_INFO(dev_priv)->cursor_needs_physical) {
12676 const int align = intel_cursor_alignment(dev_priv);
12677
12678 ret = i915_gem_object_attach_phys(obj, align);
12679 } else {
12680 struct i915_vma *vma;
12681
12682 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
12683 if (!IS_ERR(vma))
12684 to_intel_plane_state(new_state)->vma = vma;
12685 else
12686 ret = PTR_ERR(vma);
12687 }
12688
12689 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
12690
12691 mutex_unlock(&dev_priv->drm.struct_mutex);
12692 i915_gem_object_unpin_pages(obj);
12693 if (ret)
12694 return ret;
12695
12696 if (!new_state->fence) { /* implicit fencing */
12697 struct dma_fence *fence;
12698
12699 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12700 obj->resv, NULL,
12701 false, I915_FENCE_TIMEOUT,
12702 GFP_KERNEL);
12703 if (ret < 0)
12704 return ret;
12705
12706 fence = reservation_object_get_excl_rcu(obj->resv);
12707 if (fence) {
12708 add_rps_boost_after_vblank(new_state->crtc, fence);
12709 dma_fence_put(fence);
12710 }
12711 } else {
12712 add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
12713 }
12714
12715 return 0;
12716 }
12717
12718 /**
12719 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12720 * @plane: drm plane to clean up for
12721 * @fb: old framebuffer that was on plane
12722 *
12723 * Cleans up a framebuffer that has just been removed from a plane.
12724 *
12725 * Must be called with struct_mutex held.
12726 */
12727 void
12728 intel_cleanup_plane_fb(struct drm_plane *plane,
12729 struct drm_plane_state *old_state)
12730 {
12731 struct i915_vma *vma;
12732
12733 /* Should only be called after a successful intel_prepare_plane_fb()! */
12734 vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
12735 if (vma) {
12736 mutex_lock(&plane->dev->struct_mutex);
12737 intel_unpin_fb_vma(vma);
12738 mutex_unlock(&plane->dev->struct_mutex);
12739 }
12740 }
12741
12742 int
12743 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
12744 {
12745 struct drm_i915_private *dev_priv;
12746 int max_scale;
12747 int crtc_clock, max_dotclk;
12748
12749 if (!intel_crtc || !crtc_state->base.enable)
12750 return DRM_PLANE_HELPER_NO_SCALING;
12751
12752 dev_priv = to_i915(intel_crtc->base.dev);
12753
12754 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
12755 max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
12756
12757 if (IS_GEMINILAKE(dev_priv))
12758 max_dotclk *= 2;
12759
12760 if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
12761 return DRM_PLANE_HELPER_NO_SCALING;
12762
12763 /*
12764 * skl max scale is lower of:
12765 * close to 3 but not 3, -1 is for that purpose
12766 * or
12767 * cdclk/crtc_clock
12768 */
12769 max_scale = min((1 << 16) * 3 - 1,
12770 (1 << 8) * ((max_dotclk << 8) / crtc_clock));
12771
12772 return max_scale;
12773 }
12774
12775 static int
12776 intel_check_primary_plane(struct intel_plane *plane,
12777 struct intel_crtc_state *crtc_state,
12778 struct intel_plane_state *state)
12779 {
12780 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
12781 struct drm_crtc *crtc = state->base.crtc;
12782 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
12783 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
12784 bool can_position = false;
12785 int ret;
12786
12787 if (INTEL_GEN(dev_priv) >= 9) {
12788 /* use scaler when colorkey is not required */
12789 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
12790 min_scale = 1;
12791 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
12792 }
12793 can_position = true;
12794 }
12795
12796 ret = drm_plane_helper_check_state(&state->base,
12797 &state->clip,
12798 min_scale, max_scale,
12799 can_position, true);
12800 if (ret)
12801 return ret;
12802
12803 if (!state->base.fb)
12804 return 0;
12805
12806 if (INTEL_GEN(dev_priv) >= 9) {
12807 ret = skl_check_plane_surface(state);
12808 if (ret)
12809 return ret;
12810
12811 state->ctl = skl_plane_ctl(crtc_state, state);
12812 } else {
12813 ret = i9xx_check_plane_surface(state);
12814 if (ret)
12815 return ret;
12816
12817 state->ctl = i9xx_plane_ctl(crtc_state, state);
12818 }
12819
12820 return 0;
12821 }
12822
12823 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
12824 struct drm_crtc_state *old_crtc_state)
12825 {
12826 struct drm_device *dev = crtc->dev;
12827 struct drm_i915_private *dev_priv = to_i915(dev);
12828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12829 struct intel_crtc_state *old_intel_cstate =
12830 to_intel_crtc_state(old_crtc_state);
12831 struct intel_atomic_state *old_intel_state =
12832 to_intel_atomic_state(old_crtc_state->state);
12833 struct intel_crtc_state *intel_cstate =
12834 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
12835 bool modeset = needs_modeset(&intel_cstate->base);
12836
12837 if (!modeset &&
12838 (intel_cstate->base.color_mgmt_changed ||
12839 intel_cstate->update_pipe)) {
12840 intel_color_set_csc(&intel_cstate->base);
12841 intel_color_load_luts(&intel_cstate->base);
12842 }
12843
12844 /* Perform vblank evasion around commit operation */
12845 intel_pipe_update_start(intel_cstate);
12846
12847 if (modeset)
12848 goto out;
12849
12850 if (intel_cstate->update_pipe)
12851 intel_update_pipe_config(old_intel_cstate, intel_cstate);
12852 else if (INTEL_GEN(dev_priv) >= 9)
12853 skl_detach_scalers(intel_crtc);
12854
12855 out:
12856 if (dev_priv->display.atomic_update_watermarks)
12857 dev_priv->display.atomic_update_watermarks(old_intel_state,
12858 intel_cstate);
12859 }
12860
12861 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
12862 struct drm_crtc_state *old_crtc_state)
12863 {
12864 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12865 struct intel_atomic_state *old_intel_state =
12866 to_intel_atomic_state(old_crtc_state->state);
12867 struct intel_crtc_state *new_crtc_state =
12868 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
12869
12870 intel_pipe_update_end(new_crtc_state);
12871 }
12872
12873 /**
12874 * intel_plane_destroy - destroy a plane
12875 * @plane: plane to destroy
12876 *
12877 * Common destruction function for all types of planes (primary, cursor,
12878 * sprite).
12879 */
12880 void intel_plane_destroy(struct drm_plane *plane)
12881 {
12882 drm_plane_cleanup(plane);
12883 kfree(to_intel_plane(plane));
12884 }
12885
12886 static bool i8xx_mod_supported(uint32_t format, uint64_t modifier)
12887 {
12888 switch (format) {
12889 case DRM_FORMAT_C8:
12890 case DRM_FORMAT_RGB565:
12891 case DRM_FORMAT_XRGB1555:
12892 case DRM_FORMAT_XRGB8888:
12893 return modifier == DRM_FORMAT_MOD_LINEAR ||
12894 modifier == I915_FORMAT_MOD_X_TILED;
12895 default:
12896 return false;
12897 }
12898 }
12899
12900 static bool i965_mod_supported(uint32_t format, uint64_t modifier)
12901 {
12902 switch (format) {
12903 case DRM_FORMAT_C8:
12904 case DRM_FORMAT_RGB565:
12905 case DRM_FORMAT_XRGB8888:
12906 case DRM_FORMAT_XBGR8888:
12907 case DRM_FORMAT_XRGB2101010:
12908 case DRM_FORMAT_XBGR2101010:
12909 return modifier == DRM_FORMAT_MOD_LINEAR ||
12910 modifier == I915_FORMAT_MOD_X_TILED;
12911 default:
12912 return false;
12913 }
12914 }
12915
12916 static bool skl_mod_supported(uint32_t format, uint64_t modifier)
12917 {
12918 switch (format) {
12919 case DRM_FORMAT_XRGB8888:
12920 case DRM_FORMAT_XBGR8888:
12921 case DRM_FORMAT_ARGB8888:
12922 case DRM_FORMAT_ABGR8888:
12923 if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
12924 modifier == I915_FORMAT_MOD_Y_TILED_CCS)
12925 return true;
12926 /* fall through */
12927 case DRM_FORMAT_RGB565:
12928 case DRM_FORMAT_XRGB2101010:
12929 case DRM_FORMAT_XBGR2101010:
12930 case DRM_FORMAT_YUYV:
12931 case DRM_FORMAT_YVYU:
12932 case DRM_FORMAT_UYVY:
12933 case DRM_FORMAT_VYUY:
12934 if (modifier == I915_FORMAT_MOD_Yf_TILED)
12935 return true;
12936 /* fall through */
12937 case DRM_FORMAT_C8:
12938 if (modifier == DRM_FORMAT_MOD_LINEAR ||
12939 modifier == I915_FORMAT_MOD_X_TILED ||
12940 modifier == I915_FORMAT_MOD_Y_TILED)
12941 return true;
12942 /* fall through */
12943 default:
12944 return false;
12945 }
12946 }
12947
12948 static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane,
12949 uint32_t format,
12950 uint64_t modifier)
12951 {
12952 struct drm_i915_private *dev_priv = to_i915(plane->dev);
12953
12954 if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
12955 return false;
12956
12957 if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL &&
12958 modifier != DRM_FORMAT_MOD_LINEAR)
12959 return false;
12960
12961 if (INTEL_GEN(dev_priv) >= 9)
12962 return skl_mod_supported(format, modifier);
12963 else if (INTEL_GEN(dev_priv) >= 4)
12964 return i965_mod_supported(format, modifier);
12965 else
12966 return i8xx_mod_supported(format, modifier);
12967
12968 unreachable();
12969 }
12970
12971 static bool intel_cursor_plane_format_mod_supported(struct drm_plane *plane,
12972 uint32_t format,
12973 uint64_t modifier)
12974 {
12975 if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
12976 return false;
12977
12978 return modifier == DRM_FORMAT_MOD_LINEAR && format == DRM_FORMAT_ARGB8888;
12979 }
12980
12981 static struct drm_plane_funcs intel_plane_funcs = {
12982 .update_plane = drm_atomic_helper_update_plane,
12983 .disable_plane = drm_atomic_helper_disable_plane,
12984 .destroy = intel_plane_destroy,
12985 .atomic_get_property = intel_plane_atomic_get_property,
12986 .atomic_set_property = intel_plane_atomic_set_property,
12987 .atomic_duplicate_state = intel_plane_duplicate_state,
12988 .atomic_destroy_state = intel_plane_destroy_state,
12989 .format_mod_supported = intel_primary_plane_format_mod_supported,
12990 };
12991
12992 static int
12993 intel_legacy_cursor_update(struct drm_plane *plane,
12994 struct drm_crtc *crtc,
12995 struct drm_framebuffer *fb,
12996 int crtc_x, int crtc_y,
12997 unsigned int crtc_w, unsigned int crtc_h,
12998 uint32_t src_x, uint32_t src_y,
12999 uint32_t src_w, uint32_t src_h,
13000 struct drm_modeset_acquire_ctx *ctx)
13001 {
13002 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13003 int ret;
13004 struct drm_plane_state *old_plane_state, *new_plane_state;
13005 struct intel_plane *intel_plane = to_intel_plane(plane);
13006 struct drm_framebuffer *old_fb;
13007 struct drm_crtc_state *crtc_state = crtc->state;
13008 struct i915_vma *old_vma, *vma;
13009
13010 /*
13011 * When crtc is inactive or there is a modeset pending,
13012 * wait for it to complete in the slowpath
13013 */
13014 if (!crtc_state->active || needs_modeset(crtc_state) ||
13015 to_intel_crtc_state(crtc_state)->update_pipe)
13016 goto slow;
13017
13018 old_plane_state = plane->state;
13019 /*
13020 * Don't do an async update if there is an outstanding commit modifying
13021 * the plane. This prevents our async update's changes from getting
13022 * overridden by a previous synchronous update's state.
13023 */
13024 if (old_plane_state->commit &&
13025 !try_wait_for_completion(&old_plane_state->commit->hw_done))
13026 goto slow;
13027
13028 /*
13029 * If any parameters change that may affect watermarks,
13030 * take the slowpath. Only changing fb or position should be
13031 * in the fastpath.
13032 */
13033 if (old_plane_state->crtc != crtc ||
13034 old_plane_state->src_w != src_w ||
13035 old_plane_state->src_h != src_h ||
13036 old_plane_state->crtc_w != crtc_w ||
13037 old_plane_state->crtc_h != crtc_h ||
13038 !old_plane_state->fb != !fb)
13039 goto slow;
13040
13041 new_plane_state = intel_plane_duplicate_state(plane);
13042 if (!new_plane_state)
13043 return -ENOMEM;
13044
13045 drm_atomic_set_fb_for_plane(new_plane_state, fb);
13046
13047 new_plane_state->src_x = src_x;
13048 new_plane_state->src_y = src_y;
13049 new_plane_state->src_w = src_w;
13050 new_plane_state->src_h = src_h;
13051 new_plane_state->crtc_x = crtc_x;
13052 new_plane_state->crtc_y = crtc_y;
13053 new_plane_state->crtc_w = crtc_w;
13054 new_plane_state->crtc_h = crtc_h;
13055
13056 ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13057 to_intel_crtc_state(crtc->state), /* FIXME need a new crtc state? */
13058 to_intel_plane_state(plane->state),
13059 to_intel_plane_state(new_plane_state));
13060 if (ret)
13061 goto out_free;
13062
13063 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13064 if (ret)
13065 goto out_free;
13066
13067 if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13068 int align = intel_cursor_alignment(dev_priv);
13069
13070 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13071 if (ret) {
13072 DRM_DEBUG_KMS("failed to attach phys object\n");
13073 goto out_unlock;
13074 }
13075 } else {
13076 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13077 if (IS_ERR(vma)) {
13078 DRM_DEBUG_KMS("failed to pin object\n");
13079
13080 ret = PTR_ERR(vma);
13081 goto out_unlock;
13082 }
13083
13084 to_intel_plane_state(new_plane_state)->vma = vma;
13085 }
13086
13087 old_fb = old_plane_state->fb;
13088
13089 i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13090 intel_plane->frontbuffer_bit);
13091
13092 /* Swap plane state */
13093 plane->state = new_plane_state;
13094
13095 if (plane->state->visible) {
13096 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13097 intel_plane->update_plane(intel_plane,
13098 to_intel_crtc_state(crtc->state),
13099 to_intel_plane_state(plane->state));
13100 } else {
13101 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13102 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
13103 }
13104
13105 old_vma = fetch_and_zero(&to_intel_plane_state(old_plane_state)->vma);
13106 if (old_vma)
13107 intel_unpin_fb_vma(old_vma);
13108
13109 out_unlock:
13110 mutex_unlock(&dev_priv->drm.struct_mutex);
13111 out_free:
13112 if (ret)
13113 intel_plane_destroy_state(plane, new_plane_state);
13114 else
13115 intel_plane_destroy_state(plane, old_plane_state);
13116 return ret;
13117
13118 slow:
13119 return drm_atomic_helper_update_plane(plane, crtc, fb,
13120 crtc_x, crtc_y, crtc_w, crtc_h,
13121 src_x, src_y, src_w, src_h, ctx);
13122 }
13123
13124 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13125 .update_plane = intel_legacy_cursor_update,
13126 .disable_plane = drm_atomic_helper_disable_plane,
13127 .destroy = intel_plane_destroy,
13128 .atomic_get_property = intel_plane_atomic_get_property,
13129 .atomic_set_property = intel_plane_atomic_set_property,
13130 .atomic_duplicate_state = intel_plane_duplicate_state,
13131 .atomic_destroy_state = intel_plane_destroy_state,
13132 .format_mod_supported = intel_cursor_plane_format_mod_supported,
13133 };
13134
13135 static struct intel_plane *
13136 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13137 {
13138 struct intel_plane *primary = NULL;
13139 struct intel_plane_state *state = NULL;
13140 const uint32_t *intel_primary_formats;
13141 unsigned int supported_rotations;
13142 unsigned int num_formats;
13143 const uint64_t *modifiers;
13144 int ret;
13145
13146 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13147 if (!primary) {
13148 ret = -ENOMEM;
13149 goto fail;
13150 }
13151
13152 state = intel_create_plane_state(&primary->base);
13153 if (!state) {
13154 ret = -ENOMEM;
13155 goto fail;
13156 }
13157
13158 primary->base.state = &state->base;
13159
13160 primary->can_scale = false;
13161 primary->max_downscale = 1;
13162 if (INTEL_GEN(dev_priv) >= 9) {
13163 primary->can_scale = true;
13164 state->scaler_id = -1;
13165 }
13166 primary->pipe = pipe;
13167 /*
13168 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13169 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13170 */
13171 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13172 primary->plane = (enum plane) !pipe;
13173 else
13174 primary->plane = (enum plane) pipe;
13175 primary->id = PLANE_PRIMARY;
13176 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13177 primary->check_plane = intel_check_primary_plane;
13178
13179 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
13180 intel_primary_formats = skl_primary_formats;
13181 num_formats = ARRAY_SIZE(skl_primary_formats);
13182 modifiers = skl_format_modifiers_ccs;
13183
13184 primary->update_plane = skl_update_plane;
13185 primary->disable_plane = skl_disable_plane;
13186 } else if (INTEL_GEN(dev_priv) >= 9) {
13187 intel_primary_formats = skl_primary_formats;
13188 num_formats = ARRAY_SIZE(skl_primary_formats);
13189 if (pipe < PIPE_C)
13190 modifiers = skl_format_modifiers_ccs;
13191 else
13192 modifiers = skl_format_modifiers_noccs;
13193
13194 primary->update_plane = skl_update_plane;
13195 primary->disable_plane = skl_disable_plane;
13196 } else if (INTEL_GEN(dev_priv) >= 4) {
13197 intel_primary_formats = i965_primary_formats;
13198 num_formats = ARRAY_SIZE(i965_primary_formats);
13199 modifiers = i9xx_format_modifiers;
13200
13201 primary->update_plane = i9xx_update_primary_plane;
13202 primary->disable_plane = i9xx_disable_primary_plane;
13203 } else {
13204 intel_primary_formats = i8xx_primary_formats;
13205 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13206 modifiers = i9xx_format_modifiers;
13207
13208 primary->update_plane = i9xx_update_primary_plane;
13209 primary->disable_plane = i9xx_disable_primary_plane;
13210 }
13211
13212 if (INTEL_GEN(dev_priv) >= 9)
13213 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13214 0, &intel_plane_funcs,
13215 intel_primary_formats, num_formats,
13216 modifiers,
13217 DRM_PLANE_TYPE_PRIMARY,
13218 "plane 1%c", pipe_name(pipe));
13219 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13220 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13221 0, &intel_plane_funcs,
13222 intel_primary_formats, num_formats,
13223 modifiers,
13224 DRM_PLANE_TYPE_PRIMARY,
13225 "primary %c", pipe_name(pipe));
13226 else
13227 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13228 0, &intel_plane_funcs,
13229 intel_primary_formats, num_formats,
13230 modifiers,
13231 DRM_PLANE_TYPE_PRIMARY,
13232 "plane %c", plane_name(primary->plane));
13233 if (ret)
13234 goto fail;
13235
13236 if (INTEL_GEN(dev_priv) >= 9) {
13237 supported_rotations =
13238 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13239 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
13240 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13241 supported_rotations =
13242 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
13243 DRM_MODE_REFLECT_X;
13244 } else if (INTEL_GEN(dev_priv) >= 4) {
13245 supported_rotations =
13246 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
13247 } else {
13248 supported_rotations = DRM_MODE_ROTATE_0;
13249 }
13250
13251 if (INTEL_GEN(dev_priv) >= 4)
13252 drm_plane_create_rotation_property(&primary->base,
13253 DRM_MODE_ROTATE_0,
13254 supported_rotations);
13255
13256 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13257
13258 return primary;
13259
13260 fail:
13261 kfree(state);
13262 kfree(primary);
13263
13264 return ERR_PTR(ret);
13265 }
13266
13267 static struct intel_plane *
13268 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13269 enum pipe pipe)
13270 {
13271 struct intel_plane *cursor = NULL;
13272 struct intel_plane_state *state = NULL;
13273 int ret;
13274
13275 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13276 if (!cursor) {
13277 ret = -ENOMEM;
13278 goto fail;
13279 }
13280
13281 state = intel_create_plane_state(&cursor->base);
13282 if (!state) {
13283 ret = -ENOMEM;
13284 goto fail;
13285 }
13286
13287 cursor->base.state = &state->base;
13288
13289 cursor->can_scale = false;
13290 cursor->max_downscale = 1;
13291 cursor->pipe = pipe;
13292 cursor->plane = pipe;
13293 cursor->id = PLANE_CURSOR;
13294 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13295
13296 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
13297 cursor->update_plane = i845_update_cursor;
13298 cursor->disable_plane = i845_disable_cursor;
13299 cursor->check_plane = i845_check_cursor;
13300 } else {
13301 cursor->update_plane = i9xx_update_cursor;
13302 cursor->disable_plane = i9xx_disable_cursor;
13303 cursor->check_plane = i9xx_check_cursor;
13304 }
13305
13306 cursor->cursor.base = ~0;
13307 cursor->cursor.cntl = ~0;
13308
13309 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
13310 cursor->cursor.size = ~0;
13311
13312 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13313 0, &intel_cursor_plane_funcs,
13314 intel_cursor_formats,
13315 ARRAY_SIZE(intel_cursor_formats),
13316 cursor_format_modifiers,
13317 DRM_PLANE_TYPE_CURSOR,
13318 "cursor %c", pipe_name(pipe));
13319 if (ret)
13320 goto fail;
13321
13322 if (INTEL_GEN(dev_priv) >= 4)
13323 drm_plane_create_rotation_property(&cursor->base,
13324 DRM_MODE_ROTATE_0,
13325 DRM_MODE_ROTATE_0 |
13326 DRM_MODE_ROTATE_180);
13327
13328 if (INTEL_GEN(dev_priv) >= 9)
13329 state->scaler_id = -1;
13330
13331 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13332
13333 return cursor;
13334
13335 fail:
13336 kfree(state);
13337 kfree(cursor);
13338
13339 return ERR_PTR(ret);
13340 }
13341
13342 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13343 struct intel_crtc_state *crtc_state)
13344 {
13345 struct intel_crtc_scaler_state *scaler_state =
13346 &crtc_state->scaler_state;
13347 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13348 int i;
13349
13350 crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13351 if (!crtc->num_scalers)
13352 return;
13353
13354 for (i = 0; i < crtc->num_scalers; i++) {
13355 struct intel_scaler *scaler = &scaler_state->scalers[i];
13356
13357 scaler->in_use = 0;
13358 scaler->mode = PS_SCALER_MODE_DYN;
13359 }
13360
13361 scaler_state->scaler_id = -1;
13362 }
13363
13364 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13365 {
13366 struct intel_crtc *intel_crtc;
13367 struct intel_crtc_state *crtc_state = NULL;
13368 struct intel_plane *primary = NULL;
13369 struct intel_plane *cursor = NULL;
13370 int sprite, ret;
13371
13372 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13373 if (!intel_crtc)
13374 return -ENOMEM;
13375
13376 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13377 if (!crtc_state) {
13378 ret = -ENOMEM;
13379 goto fail;
13380 }
13381 intel_crtc->config = crtc_state;
13382 intel_crtc->base.state = &crtc_state->base;
13383 crtc_state->base.crtc = &intel_crtc->base;
13384
13385 primary = intel_primary_plane_create(dev_priv, pipe);
13386 if (IS_ERR(primary)) {
13387 ret = PTR_ERR(primary);
13388 goto fail;
13389 }
13390 intel_crtc->plane_ids_mask |= BIT(primary->id);
13391
13392 for_each_sprite(dev_priv, pipe, sprite) {
13393 struct intel_plane *plane;
13394
13395 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13396 if (IS_ERR(plane)) {
13397 ret = PTR_ERR(plane);
13398 goto fail;
13399 }
13400 intel_crtc->plane_ids_mask |= BIT(plane->id);
13401 }
13402
13403 cursor = intel_cursor_plane_create(dev_priv, pipe);
13404 if (IS_ERR(cursor)) {
13405 ret = PTR_ERR(cursor);
13406 goto fail;
13407 }
13408 intel_crtc->plane_ids_mask |= BIT(cursor->id);
13409
13410 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13411 &primary->base, &cursor->base,
13412 &intel_crtc_funcs,
13413 "pipe %c", pipe_name(pipe));
13414 if (ret)
13415 goto fail;
13416
13417 intel_crtc->pipe = pipe;
13418 intel_crtc->plane = primary->plane;
13419
13420 /* initialize shared scalers */
13421 intel_crtc_init_scalers(intel_crtc, crtc_state);
13422
13423 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13424 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13425 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13426 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13427
13428 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13429
13430 intel_color_init(&intel_crtc->base);
13431
13432 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13433
13434 return 0;
13435
13436 fail:
13437 /*
13438 * drm_mode_config_cleanup() will free up any
13439 * crtcs/planes already initialized.
13440 */
13441 kfree(crtc_state);
13442 kfree(intel_crtc);
13443
13444 return ret;
13445 }
13446
13447 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13448 {
13449 struct drm_device *dev = connector->base.dev;
13450
13451 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13452
13453 if (!connector->base.state->crtc)
13454 return INVALID_PIPE;
13455
13456 return to_intel_crtc(connector->base.state->crtc)->pipe;
13457 }
13458
13459 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13460 struct drm_file *file)
13461 {
13462 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13463 struct drm_crtc *drmmode_crtc;
13464 struct intel_crtc *crtc;
13465
13466 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
13467 if (!drmmode_crtc)
13468 return -ENOENT;
13469
13470 crtc = to_intel_crtc(drmmode_crtc);
13471 pipe_from_crtc_id->pipe = crtc->pipe;
13472
13473 return 0;
13474 }
13475
13476 static int intel_encoder_clones(struct intel_encoder *encoder)
13477 {
13478 struct drm_device *dev = encoder->base.dev;
13479 struct intel_encoder *source_encoder;
13480 int index_mask = 0;
13481 int entry = 0;
13482
13483 for_each_intel_encoder(dev, source_encoder) {
13484 if (encoders_cloneable(encoder, source_encoder))
13485 index_mask |= (1 << entry);
13486
13487 entry++;
13488 }
13489
13490 return index_mask;
13491 }
13492
13493 static bool has_edp_a(struct drm_i915_private *dev_priv)
13494 {
13495 if (!IS_MOBILE(dev_priv))
13496 return false;
13497
13498 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13499 return false;
13500
13501 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13502 return false;
13503
13504 return true;
13505 }
13506
13507 static bool intel_crt_present(struct drm_i915_private *dev_priv)
13508 {
13509 if (INTEL_GEN(dev_priv) >= 9)
13510 return false;
13511
13512 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
13513 return false;
13514
13515 if (IS_CHERRYVIEW(dev_priv))
13516 return false;
13517
13518 if (HAS_PCH_LPT_H(dev_priv) &&
13519 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
13520 return false;
13521
13522 /* DDI E can't be used if DDI A requires 4 lanes */
13523 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
13524 return false;
13525
13526 if (!dev_priv->vbt.int_crt_support)
13527 return false;
13528
13529 return true;
13530 }
13531
13532 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
13533 {
13534 int pps_num;
13535 int pps_idx;
13536
13537 if (HAS_DDI(dev_priv))
13538 return;
13539 /*
13540 * This w/a is needed at least on CPT/PPT, but to be sure apply it
13541 * everywhere where registers can be write protected.
13542 */
13543 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13544 pps_num = 2;
13545 else
13546 pps_num = 1;
13547
13548 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
13549 u32 val = I915_READ(PP_CONTROL(pps_idx));
13550
13551 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
13552 I915_WRITE(PP_CONTROL(pps_idx), val);
13553 }
13554 }
13555
13556 static void intel_pps_init(struct drm_i915_private *dev_priv)
13557 {
13558 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
13559 dev_priv->pps_mmio_base = PCH_PPS_BASE;
13560 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13561 dev_priv->pps_mmio_base = VLV_PPS_BASE;
13562 else
13563 dev_priv->pps_mmio_base = PPS_BASE;
13564
13565 intel_pps_unlock_regs_wa(dev_priv);
13566 }
13567
13568 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
13569 {
13570 struct intel_encoder *encoder;
13571 bool dpd_is_edp = false;
13572
13573 intel_pps_init(dev_priv);
13574
13575 /*
13576 * intel_edp_init_connector() depends on this completing first, to
13577 * prevent the registeration of both eDP and LVDS and the incorrect
13578 * sharing of the PPS.
13579 */
13580 intel_lvds_init(dev_priv);
13581
13582 if (intel_crt_present(dev_priv))
13583 intel_crt_init(dev_priv);
13584
13585 if (IS_GEN9_LP(dev_priv)) {
13586 /*
13587 * FIXME: Broxton doesn't support port detection via the
13588 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13589 * detect the ports.
13590 */
13591 intel_ddi_init(dev_priv, PORT_A);
13592 intel_ddi_init(dev_priv, PORT_B);
13593 intel_ddi_init(dev_priv, PORT_C);
13594
13595 intel_dsi_init(dev_priv);
13596 } else if (HAS_DDI(dev_priv)) {
13597 int found;
13598
13599 /*
13600 * Haswell uses DDI functions to detect digital outputs.
13601 * On SKL pre-D0 the strap isn't connected, so we assume
13602 * it's there.
13603 */
13604 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13605 /* WaIgnoreDDIAStrap: skl */
13606 if (found || IS_GEN9_BC(dev_priv))
13607 intel_ddi_init(dev_priv, PORT_A);
13608
13609 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13610 * register */
13611 found = I915_READ(SFUSE_STRAP);
13612
13613 if (found & SFUSE_STRAP_DDIB_DETECTED)
13614 intel_ddi_init(dev_priv, PORT_B);
13615 if (found & SFUSE_STRAP_DDIC_DETECTED)
13616 intel_ddi_init(dev_priv, PORT_C);
13617 if (found & SFUSE_STRAP_DDID_DETECTED)
13618 intel_ddi_init(dev_priv, PORT_D);
13619 /*
13620 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13621 */
13622 if (IS_GEN9_BC(dev_priv) &&
13623 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13624 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13625 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13626 intel_ddi_init(dev_priv, PORT_E);
13627
13628 } else if (HAS_PCH_SPLIT(dev_priv)) {
13629 int found;
13630 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
13631
13632 if (has_edp_a(dev_priv))
13633 intel_dp_init(dev_priv, DP_A, PORT_A);
13634
13635 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13636 /* PCH SDVOB multiplex with HDMIB */
13637 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
13638 if (!found)
13639 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
13640 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13641 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
13642 }
13643
13644 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13645 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
13646
13647 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13648 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
13649
13650 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13651 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
13652
13653 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13654 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
13655 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
13656 bool has_edp, has_port;
13657
13658 /*
13659 * The DP_DETECTED bit is the latched state of the DDC
13660 * SDA pin at boot. However since eDP doesn't require DDC
13661 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13662 * eDP ports may have been muxed to an alternate function.
13663 * Thus we can't rely on the DP_DETECTED bit alone to detect
13664 * eDP ports. Consult the VBT as well as DP_DETECTED to
13665 * detect eDP ports.
13666 *
13667 * Sadly the straps seem to be missing sometimes even for HDMI
13668 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
13669 * and VBT for the presence of the port. Additionally we can't
13670 * trust the port type the VBT declares as we've seen at least
13671 * HDMI ports that the VBT claim are DP or eDP.
13672 */
13673 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
13674 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
13675 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
13676 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
13677 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
13678 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
13679
13680 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
13681 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
13682 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
13683 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
13684 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
13685 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
13686
13687 if (IS_CHERRYVIEW(dev_priv)) {
13688 /*
13689 * eDP not supported on port D,
13690 * so no need to worry about it
13691 */
13692 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
13693 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
13694 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
13695 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
13696 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
13697 }
13698
13699 intel_dsi_init(dev_priv);
13700 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
13701 bool found = false;
13702
13703 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13704 DRM_DEBUG_KMS("probing SDVOB\n");
13705 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
13706 if (!found && IS_G4X(dev_priv)) {
13707 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13708 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
13709 }
13710
13711 if (!found && IS_G4X(dev_priv))
13712 intel_dp_init(dev_priv, DP_B, PORT_B);
13713 }
13714
13715 /* Before G4X SDVOC doesn't have its own detect register */
13716
13717 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13718 DRM_DEBUG_KMS("probing SDVOC\n");
13719 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
13720 }
13721
13722 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13723
13724 if (IS_G4X(dev_priv)) {
13725 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13726 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
13727 }
13728 if (IS_G4X(dev_priv))
13729 intel_dp_init(dev_priv, DP_C, PORT_C);
13730 }
13731
13732 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
13733 intel_dp_init(dev_priv, DP_D, PORT_D);
13734 } else if (IS_GEN2(dev_priv))
13735 intel_dvo_init(dev_priv);
13736
13737 if (SUPPORTS_TV(dev_priv))
13738 intel_tv_init(dev_priv);
13739
13740 intel_psr_init(dev_priv);
13741
13742 for_each_intel_encoder(&dev_priv->drm, encoder) {
13743 encoder->base.possible_crtcs = encoder->crtc_mask;
13744 encoder->base.possible_clones =
13745 intel_encoder_clones(encoder);
13746 }
13747
13748 intel_init_pch_refclk(dev_priv);
13749
13750 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
13751 }
13752
13753 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13754 {
13755 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13756
13757 drm_framebuffer_cleanup(fb);
13758
13759 i915_gem_object_lock(intel_fb->obj);
13760 WARN_ON(!intel_fb->obj->framebuffer_references--);
13761 i915_gem_object_unlock(intel_fb->obj);
13762
13763 i915_gem_object_put(intel_fb->obj);
13764
13765 kfree(intel_fb);
13766 }
13767
13768 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13769 struct drm_file *file,
13770 unsigned int *handle)
13771 {
13772 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13773 struct drm_i915_gem_object *obj = intel_fb->obj;
13774
13775 if (obj->userptr.mm) {
13776 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
13777 return -EINVAL;
13778 }
13779
13780 return drm_gem_handle_create(file, &obj->base, handle);
13781 }
13782
13783 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
13784 struct drm_file *file,
13785 unsigned flags, unsigned color,
13786 struct drm_clip_rect *clips,
13787 unsigned num_clips)
13788 {
13789 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13790
13791 i915_gem_object_flush_if_display(obj);
13792 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
13793
13794 return 0;
13795 }
13796
13797 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13798 .destroy = intel_user_framebuffer_destroy,
13799 .create_handle = intel_user_framebuffer_create_handle,
13800 .dirty = intel_user_framebuffer_dirty,
13801 };
13802
13803 static
13804 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
13805 uint64_t fb_modifier, uint32_t pixel_format)
13806 {
13807 u32 gen = INTEL_GEN(dev_priv);
13808
13809 if (gen >= 9) {
13810 int cpp = drm_format_plane_cpp(pixel_format, 0);
13811
13812 /* "The stride in bytes must not exceed the of the size of 8K
13813 * pixels and 32K bytes."
13814 */
13815 return min(8192 * cpp, 32768);
13816 } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
13817 return 32*1024;
13818 } else if (gen >= 4) {
13819 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13820 return 16*1024;
13821 else
13822 return 32*1024;
13823 } else if (gen >= 3) {
13824 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13825 return 8*1024;
13826 else
13827 return 16*1024;
13828 } else {
13829 /* XXX DSPC is limited to 4k tiled */
13830 return 8*1024;
13831 }
13832 }
13833
13834 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
13835 struct drm_i915_gem_object *obj,
13836 struct drm_mode_fb_cmd2 *mode_cmd)
13837 {
13838 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
13839 struct drm_framebuffer *fb = &intel_fb->base;
13840 struct drm_format_name_buf format_name;
13841 u32 pitch_limit;
13842 unsigned int tiling, stride;
13843 int ret = -EINVAL;
13844 int i;
13845
13846 i915_gem_object_lock(obj);
13847 obj->framebuffer_references++;
13848 tiling = i915_gem_object_get_tiling(obj);
13849 stride = i915_gem_object_get_stride(obj);
13850 i915_gem_object_unlock(obj);
13851
13852 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13853 /*
13854 * If there's a fence, enforce that
13855 * the fb modifier and tiling mode match.
13856 */
13857 if (tiling != I915_TILING_NONE &&
13858 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13859 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
13860 goto err;
13861 }
13862 } else {
13863 if (tiling == I915_TILING_X) {
13864 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13865 } else if (tiling == I915_TILING_Y) {
13866 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
13867 goto err;
13868 }
13869 }
13870
13871 /* Passed in modifier sanity checking. */
13872 switch (mode_cmd->modifier[0]) {
13873 case I915_FORMAT_MOD_Y_TILED_CCS:
13874 case I915_FORMAT_MOD_Yf_TILED_CCS:
13875 switch (mode_cmd->pixel_format) {
13876 case DRM_FORMAT_XBGR8888:
13877 case DRM_FORMAT_ABGR8888:
13878 case DRM_FORMAT_XRGB8888:
13879 case DRM_FORMAT_ARGB8888:
13880 break;
13881 default:
13882 DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n");
13883 goto err;
13884 }
13885 /* fall through */
13886 case I915_FORMAT_MOD_Y_TILED:
13887 case I915_FORMAT_MOD_Yf_TILED:
13888 if (INTEL_GEN(dev_priv) < 9) {
13889 DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
13890 mode_cmd->modifier[0]);
13891 goto err;
13892 }
13893 case DRM_FORMAT_MOD_LINEAR:
13894 case I915_FORMAT_MOD_X_TILED:
13895 break;
13896 default:
13897 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
13898 mode_cmd->modifier[0]);
13899 goto err;
13900 }
13901
13902 /*
13903 * gen2/3 display engine uses the fence if present,
13904 * so the tiling mode must match the fb modifier exactly.
13905 */
13906 if (INTEL_INFO(dev_priv)->gen < 4 &&
13907 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13908 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
13909 goto err;
13910 }
13911
13912 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
13913 mode_cmd->pixel_format);
13914 if (mode_cmd->pitches[0] > pitch_limit) {
13915 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
13916 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
13917 "tiled" : "linear",
13918 mode_cmd->pitches[0], pitch_limit);
13919 goto err;
13920 }
13921
13922 /*
13923 * If there's a fence, enforce that
13924 * the fb pitch and fence stride match.
13925 */
13926 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
13927 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
13928 mode_cmd->pitches[0], stride);
13929 goto err;
13930 }
13931
13932 /* Reject formats not supported by any plane early. */
13933 switch (mode_cmd->pixel_format) {
13934 case DRM_FORMAT_C8:
13935 case DRM_FORMAT_RGB565:
13936 case DRM_FORMAT_XRGB8888:
13937 case DRM_FORMAT_ARGB8888:
13938 break;
13939 case DRM_FORMAT_XRGB1555:
13940 if (INTEL_GEN(dev_priv) > 3) {
13941 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13942 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13943 goto err;
13944 }
13945 break;
13946 case DRM_FORMAT_ABGR8888:
13947 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
13948 INTEL_GEN(dev_priv) < 9) {
13949 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13950 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13951 goto err;
13952 }
13953 break;
13954 case DRM_FORMAT_XBGR8888:
13955 case DRM_FORMAT_XRGB2101010:
13956 case DRM_FORMAT_XBGR2101010:
13957 if (INTEL_GEN(dev_priv) < 4) {
13958 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13959 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13960 goto err;
13961 }
13962 break;
13963 case DRM_FORMAT_ABGR2101010:
13964 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
13965 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13966 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13967 goto err;
13968 }
13969 break;
13970 case DRM_FORMAT_YUYV:
13971 case DRM_FORMAT_UYVY:
13972 case DRM_FORMAT_YVYU:
13973 case DRM_FORMAT_VYUY:
13974 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
13975 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13976 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13977 goto err;
13978 }
13979 break;
13980 default:
13981 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13982 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13983 goto err;
13984 }
13985
13986 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13987 if (mode_cmd->offsets[0] != 0)
13988 goto err;
13989
13990 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
13991
13992 for (i = 0; i < fb->format->num_planes; i++) {
13993 u32 stride_alignment;
13994
13995 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
13996 DRM_DEBUG_KMS("bad plane %d handle\n", i);
13997 goto err;
13998 }
13999
14000 stride_alignment = intel_fb_stride_alignment(fb, i);
14001
14002 /*
14003 * Display WA #0531: skl,bxt,kbl,glk
14004 *
14005 * Render decompression and plane width > 3840
14006 * combined with horizontal panning requires the
14007 * plane stride to be a multiple of 4. We'll just
14008 * require the entire fb to accommodate that to avoid
14009 * potential runtime errors at plane configuration time.
14010 */
14011 if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 &&
14012 (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
14013 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS))
14014 stride_alignment *= 4;
14015
14016 if (fb->pitches[i] & (stride_alignment - 1)) {
14017 DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
14018 i, fb->pitches[i], stride_alignment);
14019 goto err;
14020 }
14021 }
14022
14023 intel_fb->obj = obj;
14024
14025 ret = intel_fill_fb_info(dev_priv, fb);
14026 if (ret)
14027 goto err;
14028
14029 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
14030 if (ret) {
14031 DRM_ERROR("framebuffer init failed %d\n", ret);
14032 goto err;
14033 }
14034
14035 return 0;
14036
14037 err:
14038 i915_gem_object_lock(obj);
14039 obj->framebuffer_references--;
14040 i915_gem_object_unlock(obj);
14041 return ret;
14042 }
14043
14044 static struct drm_framebuffer *
14045 intel_user_framebuffer_create(struct drm_device *dev,
14046 struct drm_file *filp,
14047 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14048 {
14049 struct drm_framebuffer *fb;
14050 struct drm_i915_gem_object *obj;
14051 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14052
14053 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14054 if (!obj)
14055 return ERR_PTR(-ENOENT);
14056
14057 fb = intel_framebuffer_create(obj, &mode_cmd);
14058 if (IS_ERR(fb))
14059 i915_gem_object_put(obj);
14060
14061 return fb;
14062 }
14063
14064 static void intel_atomic_state_free(struct drm_atomic_state *state)
14065 {
14066 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14067
14068 drm_atomic_state_default_release(state);
14069
14070 i915_sw_fence_fini(&intel_state->commit_ready);
14071
14072 kfree(state);
14073 }
14074
14075 static const struct drm_mode_config_funcs intel_mode_funcs = {
14076 .fb_create = intel_user_framebuffer_create,
14077 .get_format_info = intel_get_format_info,
14078 .output_poll_changed = intel_fbdev_output_poll_changed,
14079 .atomic_check = intel_atomic_check,
14080 .atomic_commit = intel_atomic_commit,
14081 .atomic_state_alloc = intel_atomic_state_alloc,
14082 .atomic_state_clear = intel_atomic_state_clear,
14083 .atomic_state_free = intel_atomic_state_free,
14084 };
14085
14086 /**
14087 * intel_init_display_hooks - initialize the display modesetting hooks
14088 * @dev_priv: device private
14089 */
14090 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14091 {
14092 intel_init_cdclk_hooks(dev_priv);
14093
14094 if (INTEL_INFO(dev_priv)->gen >= 9) {
14095 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14096 dev_priv->display.get_initial_plane_config =
14097 skylake_get_initial_plane_config;
14098 dev_priv->display.crtc_compute_clock =
14099 haswell_crtc_compute_clock;
14100 dev_priv->display.crtc_enable = haswell_crtc_enable;
14101 dev_priv->display.crtc_disable = haswell_crtc_disable;
14102 } else if (HAS_DDI(dev_priv)) {
14103 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14104 dev_priv->display.get_initial_plane_config =
14105 ironlake_get_initial_plane_config;
14106 dev_priv->display.crtc_compute_clock =
14107 haswell_crtc_compute_clock;
14108 dev_priv->display.crtc_enable = haswell_crtc_enable;
14109 dev_priv->display.crtc_disable = haswell_crtc_disable;
14110 } else if (HAS_PCH_SPLIT(dev_priv)) {
14111 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14112 dev_priv->display.get_initial_plane_config =
14113 ironlake_get_initial_plane_config;
14114 dev_priv->display.crtc_compute_clock =
14115 ironlake_crtc_compute_clock;
14116 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14117 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14118 } else if (IS_CHERRYVIEW(dev_priv)) {
14119 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14120 dev_priv->display.get_initial_plane_config =
14121 i9xx_get_initial_plane_config;
14122 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14123 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14124 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14125 } else if (IS_VALLEYVIEW(dev_priv)) {
14126 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14127 dev_priv->display.get_initial_plane_config =
14128 i9xx_get_initial_plane_config;
14129 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14130 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14131 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14132 } else if (IS_G4X(dev_priv)) {
14133 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14134 dev_priv->display.get_initial_plane_config =
14135 i9xx_get_initial_plane_config;
14136 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14137 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14138 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14139 } else if (IS_PINEVIEW(dev_priv)) {
14140 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14141 dev_priv->display.get_initial_plane_config =
14142 i9xx_get_initial_plane_config;
14143 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14144 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14145 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14146 } else if (!IS_GEN2(dev_priv)) {
14147 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14148 dev_priv->display.get_initial_plane_config =
14149 i9xx_get_initial_plane_config;
14150 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14151 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14152 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14153 } else {
14154 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14155 dev_priv->display.get_initial_plane_config =
14156 i9xx_get_initial_plane_config;
14157 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14158 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14159 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14160 }
14161
14162 if (IS_GEN5(dev_priv)) {
14163 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14164 } else if (IS_GEN6(dev_priv)) {
14165 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14166 } else if (IS_IVYBRIDGE(dev_priv)) {
14167 /* FIXME: detect B0+ stepping and use auto training */
14168 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14169 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14170 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14171 }
14172
14173 if (INTEL_GEN(dev_priv) >= 9)
14174 dev_priv->display.update_crtcs = skl_update_crtcs;
14175 else
14176 dev_priv->display.update_crtcs = intel_update_crtcs;
14177 }
14178
14179 /*
14180 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14181 */
14182 static void quirk_ssc_force_disable(struct drm_device *dev)
14183 {
14184 struct drm_i915_private *dev_priv = to_i915(dev);
14185 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14186 DRM_INFO("applying lvds SSC disable quirk\n");
14187 }
14188
14189 /*
14190 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14191 * brightness value
14192 */
14193 static void quirk_invert_brightness(struct drm_device *dev)
14194 {
14195 struct drm_i915_private *dev_priv = to_i915(dev);
14196 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14197 DRM_INFO("applying inverted panel brightness quirk\n");
14198 }
14199
14200 /* Some VBT's incorrectly indicate no backlight is present */
14201 static void quirk_backlight_present(struct drm_device *dev)
14202 {
14203 struct drm_i915_private *dev_priv = to_i915(dev);
14204 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14205 DRM_INFO("applying backlight present quirk\n");
14206 }
14207
14208 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
14209 * which is 300 ms greater than eDP spec T12 min.
14210 */
14211 static void quirk_increase_t12_delay(struct drm_device *dev)
14212 {
14213 struct drm_i915_private *dev_priv = to_i915(dev);
14214
14215 dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY;
14216 DRM_INFO("Applying T12 delay quirk\n");
14217 }
14218
14219 struct intel_quirk {
14220 int device;
14221 int subsystem_vendor;
14222 int subsystem_device;
14223 void (*hook)(struct drm_device *dev);
14224 };
14225
14226 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14227 struct intel_dmi_quirk {
14228 void (*hook)(struct drm_device *dev);
14229 const struct dmi_system_id (*dmi_id_list)[];
14230 };
14231
14232 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14233 {
14234 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14235 return 1;
14236 }
14237
14238 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14239 {
14240 .dmi_id_list = &(const struct dmi_system_id[]) {
14241 {
14242 .callback = intel_dmi_reverse_brightness,
14243 .ident = "NCR Corporation",
14244 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14245 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14246 },
14247 },
14248 { } /* terminating entry */
14249 },
14250 .hook = quirk_invert_brightness,
14251 },
14252 };
14253
14254 static struct intel_quirk intel_quirks[] = {
14255 /* Lenovo U160 cannot use SSC on LVDS */
14256 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14257
14258 /* Sony Vaio Y cannot use SSC on LVDS */
14259 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14260
14261 /* Acer Aspire 5734Z must invert backlight brightness */
14262 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14263
14264 /* Acer/eMachines G725 */
14265 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14266
14267 /* Acer/eMachines e725 */
14268 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14269
14270 /* Acer/Packard Bell NCL20 */
14271 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14272
14273 /* Acer Aspire 4736Z */
14274 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14275
14276 /* Acer Aspire 5336 */
14277 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14278
14279 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14280 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14281
14282 /* Acer C720 Chromebook (Core i3 4005U) */
14283 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14284
14285 /* Apple Macbook 2,1 (Core 2 T7400) */
14286 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14287
14288 /* Apple Macbook 4,1 */
14289 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14290
14291 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14292 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14293
14294 /* HP Chromebook 14 (Celeron 2955U) */
14295 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14296
14297 /* Dell Chromebook 11 */
14298 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14299
14300 /* Dell Chromebook 11 (2015 version) */
14301 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14302
14303 /* Toshiba Satellite P50-C-18C */
14304 { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
14305 };
14306
14307 static void intel_init_quirks(struct drm_device *dev)
14308 {
14309 struct pci_dev *d = dev->pdev;
14310 int i;
14311
14312 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14313 struct intel_quirk *q = &intel_quirks[i];
14314
14315 if (d->device == q->device &&
14316 (d->subsystem_vendor == q->subsystem_vendor ||
14317 q->subsystem_vendor == PCI_ANY_ID) &&
14318 (d->subsystem_device == q->subsystem_device ||
14319 q->subsystem_device == PCI_ANY_ID))
14320 q->hook(dev);
14321 }
14322 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14323 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14324 intel_dmi_quirks[i].hook(dev);
14325 }
14326 }
14327
14328 /* Disable the VGA plane that we never use */
14329 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14330 {
14331 struct pci_dev *pdev = dev_priv->drm.pdev;
14332 u8 sr1;
14333 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14334
14335 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14336 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14337 outb(SR01, VGA_SR_INDEX);
14338 sr1 = inb(VGA_SR_DATA);
14339 outb(sr1 | 1<<5, VGA_SR_DATA);
14340 vga_put(pdev, VGA_RSRC_LEGACY_IO);
14341 udelay(300);
14342
14343 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14344 POSTING_READ(vga_reg);
14345 }
14346
14347 void intel_modeset_init_hw(struct drm_device *dev)
14348 {
14349 struct drm_i915_private *dev_priv = to_i915(dev);
14350
14351 intel_update_cdclk(dev_priv);
14352 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14353
14354 intel_init_clock_gating(dev_priv);
14355 }
14356
14357 /*
14358 * Calculate what we think the watermarks should be for the state we've read
14359 * out of the hardware and then immediately program those watermarks so that
14360 * we ensure the hardware settings match our internal state.
14361 *
14362 * We can calculate what we think WM's should be by creating a duplicate of the
14363 * current state (which was constructed during hardware readout) and running it
14364 * through the atomic check code to calculate new watermark values in the
14365 * state object.
14366 */
14367 static void sanitize_watermarks(struct drm_device *dev)
14368 {
14369 struct drm_i915_private *dev_priv = to_i915(dev);
14370 struct drm_atomic_state *state;
14371 struct intel_atomic_state *intel_state;
14372 struct drm_crtc *crtc;
14373 struct drm_crtc_state *cstate;
14374 struct drm_modeset_acquire_ctx ctx;
14375 int ret;
14376 int i;
14377
14378 /* Only supported on platforms that use atomic watermark design */
14379 if (!dev_priv->display.optimize_watermarks)
14380 return;
14381
14382 /*
14383 * We need to hold connection_mutex before calling duplicate_state so
14384 * that the connector loop is protected.
14385 */
14386 drm_modeset_acquire_init(&ctx, 0);
14387 retry:
14388 ret = drm_modeset_lock_all_ctx(dev, &ctx);
14389 if (ret == -EDEADLK) {
14390 drm_modeset_backoff(&ctx);
14391 goto retry;
14392 } else if (WARN_ON(ret)) {
14393 goto fail;
14394 }
14395
14396 state = drm_atomic_helper_duplicate_state(dev, &ctx);
14397 if (WARN_ON(IS_ERR(state)))
14398 goto fail;
14399
14400 intel_state = to_intel_atomic_state(state);
14401
14402 /*
14403 * Hardware readout is the only time we don't want to calculate
14404 * intermediate watermarks (since we don't trust the current
14405 * watermarks).
14406 */
14407 if (!HAS_GMCH_DISPLAY(dev_priv))
14408 intel_state->skip_intermediate_wm = true;
14409
14410 ret = intel_atomic_check(dev, state);
14411 if (ret) {
14412 /*
14413 * If we fail here, it means that the hardware appears to be
14414 * programmed in a way that shouldn't be possible, given our
14415 * understanding of watermark requirements. This might mean a
14416 * mistake in the hardware readout code or a mistake in the
14417 * watermark calculations for a given platform. Raise a WARN
14418 * so that this is noticeable.
14419 *
14420 * If this actually happens, we'll have to just leave the
14421 * BIOS-programmed watermarks untouched and hope for the best.
14422 */
14423 WARN(true, "Could not determine valid watermarks for inherited state\n");
14424 goto put_state;
14425 }
14426
14427 /* Write calculated watermark values back */
14428 for_each_new_crtc_in_state(state, crtc, cstate, i) {
14429 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14430
14431 cs->wm.need_postvbl_update = true;
14432 dev_priv->display.optimize_watermarks(intel_state, cs);
14433 }
14434
14435 put_state:
14436 drm_atomic_state_put(state);
14437 fail:
14438 drm_modeset_drop_locks(&ctx);
14439 drm_modeset_acquire_fini(&ctx);
14440 }
14441
14442 int intel_modeset_init(struct drm_device *dev)
14443 {
14444 struct drm_i915_private *dev_priv = to_i915(dev);
14445 struct i915_ggtt *ggtt = &dev_priv->ggtt;
14446 enum pipe pipe;
14447 struct intel_crtc *crtc;
14448
14449 drm_mode_config_init(dev);
14450
14451 dev->mode_config.min_width = 0;
14452 dev->mode_config.min_height = 0;
14453
14454 dev->mode_config.preferred_depth = 24;
14455 dev->mode_config.prefer_shadow = 1;
14456
14457 dev->mode_config.allow_fb_modifiers = true;
14458
14459 dev->mode_config.funcs = &intel_mode_funcs;
14460
14461 init_llist_head(&dev_priv->atomic_helper.free_list);
14462 INIT_WORK(&dev_priv->atomic_helper.free_work,
14463 intel_atomic_helper_free_state_worker);
14464
14465 intel_init_quirks(dev);
14466
14467 intel_init_pm(dev_priv);
14468
14469 if (INTEL_INFO(dev_priv)->num_pipes == 0)
14470 return 0;
14471
14472 /*
14473 * There may be no VBT; and if the BIOS enabled SSC we can
14474 * just keep using it to avoid unnecessary flicker. Whereas if the
14475 * BIOS isn't using it, don't assume it will work even if the VBT
14476 * indicates as much.
14477 */
14478 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
14479 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14480 DREF_SSC1_ENABLE);
14481
14482 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14483 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14484 bios_lvds_use_ssc ? "en" : "dis",
14485 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14486 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14487 }
14488 }
14489
14490 if (IS_GEN2(dev_priv)) {
14491 dev->mode_config.max_width = 2048;
14492 dev->mode_config.max_height = 2048;
14493 } else if (IS_GEN3(dev_priv)) {
14494 dev->mode_config.max_width = 4096;
14495 dev->mode_config.max_height = 4096;
14496 } else {
14497 dev->mode_config.max_width = 8192;
14498 dev->mode_config.max_height = 8192;
14499 }
14500
14501 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14502 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
14503 dev->mode_config.cursor_height = 1023;
14504 } else if (IS_GEN2(dev_priv)) {
14505 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14506 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14507 } else {
14508 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14509 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14510 }
14511
14512 dev->mode_config.fb_base = ggtt->mappable_base;
14513
14514 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14515 INTEL_INFO(dev_priv)->num_pipes,
14516 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
14517
14518 for_each_pipe(dev_priv, pipe) {
14519 int ret;
14520
14521 ret = intel_crtc_init(dev_priv, pipe);
14522 if (ret) {
14523 drm_mode_config_cleanup(dev);
14524 return ret;
14525 }
14526 }
14527
14528 intel_shared_dpll_init(dev);
14529
14530 intel_update_czclk(dev_priv);
14531 intel_modeset_init_hw(dev);
14532
14533 if (dev_priv->max_cdclk_freq == 0)
14534 intel_update_max_cdclk(dev_priv);
14535
14536 /* Just disable it once at startup */
14537 i915_disable_vga(dev_priv);
14538 intel_setup_outputs(dev_priv);
14539
14540 drm_modeset_lock_all(dev);
14541 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
14542 drm_modeset_unlock_all(dev);
14543
14544 for_each_intel_crtc(dev, crtc) {
14545 struct intel_initial_plane_config plane_config = {};
14546
14547 if (!crtc->active)
14548 continue;
14549
14550 /*
14551 * Note that reserving the BIOS fb up front prevents us
14552 * from stuffing other stolen allocations like the ring
14553 * on top. This prevents some ugliness at boot time, and
14554 * can even allow for smooth boot transitions if the BIOS
14555 * fb is large enough for the active pipe configuration.
14556 */
14557 dev_priv->display.get_initial_plane_config(crtc,
14558 &plane_config);
14559
14560 /*
14561 * If the fb is shared between multiple heads, we'll
14562 * just get the first one.
14563 */
14564 intel_find_initial_plane_obj(crtc, &plane_config);
14565 }
14566
14567 /*
14568 * Make sure hardware watermarks really match the state we read out.
14569 * Note that we need to do this after reconstructing the BIOS fb's
14570 * since the watermark calculation done here will use pstate->fb.
14571 */
14572 if (!HAS_GMCH_DISPLAY(dev_priv))
14573 sanitize_watermarks(dev);
14574
14575 return 0;
14576 }
14577
14578 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14579 {
14580 /* 640x480@60Hz, ~25175 kHz */
14581 struct dpll clock = {
14582 .m1 = 18,
14583 .m2 = 7,
14584 .p1 = 13,
14585 .p2 = 4,
14586 .n = 2,
14587 };
14588 u32 dpll, fp;
14589 int i;
14590
14591 WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
14592
14593 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
14594 pipe_name(pipe), clock.vco, clock.dot);
14595
14596 fp = i9xx_dpll_compute_fp(&clock);
14597 dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
14598 DPLL_VGA_MODE_DIS |
14599 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
14600 PLL_P2_DIVIDE_BY_4 |
14601 PLL_REF_INPUT_DREFCLK |
14602 DPLL_VCO_ENABLE;
14603
14604 I915_WRITE(FP0(pipe), fp);
14605 I915_WRITE(FP1(pipe), fp);
14606
14607 I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
14608 I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
14609 I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
14610 I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
14611 I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
14612 I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
14613 I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
14614
14615 /*
14616 * Apparently we need to have VGA mode enabled prior to changing
14617 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
14618 * dividers, even though the register value does change.
14619 */
14620 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
14621 I915_WRITE(DPLL(pipe), dpll);
14622
14623 /* Wait for the clocks to stabilize. */
14624 POSTING_READ(DPLL(pipe));
14625 udelay(150);
14626
14627 /* The pixel multiplier can only be updated once the
14628 * DPLL is enabled and the clocks are stable.
14629 *
14630 * So write it again.
14631 */
14632 I915_WRITE(DPLL(pipe), dpll);
14633
14634 /* We do this three times for luck */
14635 for (i = 0; i < 3 ; i++) {
14636 I915_WRITE(DPLL(pipe), dpll);
14637 POSTING_READ(DPLL(pipe));
14638 udelay(150); /* wait for warmup */
14639 }
14640
14641 I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
14642 POSTING_READ(PIPECONF(pipe));
14643 }
14644
14645 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14646 {
14647 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
14648 pipe_name(pipe));
14649
14650 assert_plane_disabled(dev_priv, PLANE_A);
14651 assert_plane_disabled(dev_priv, PLANE_B);
14652
14653 I915_WRITE(PIPECONF(pipe), 0);
14654 POSTING_READ(PIPECONF(pipe));
14655
14656 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
14657 DRM_ERROR("pipe %c off wait timed out\n", pipe_name(pipe));
14658
14659 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
14660 POSTING_READ(DPLL(pipe));
14661 }
14662
14663 static bool
14664 intel_check_plane_mapping(struct intel_crtc *crtc)
14665 {
14666 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14667 u32 val;
14668
14669 if (INTEL_INFO(dev_priv)->num_pipes == 1)
14670 return true;
14671
14672 val = I915_READ(DSPCNTR(!crtc->plane));
14673
14674 if ((val & DISPLAY_PLANE_ENABLE) &&
14675 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14676 return false;
14677
14678 return true;
14679 }
14680
14681 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14682 {
14683 struct drm_device *dev = crtc->base.dev;
14684 struct intel_encoder *encoder;
14685
14686 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14687 return true;
14688
14689 return false;
14690 }
14691
14692 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
14693 {
14694 struct drm_device *dev = encoder->base.dev;
14695 struct intel_connector *connector;
14696
14697 for_each_connector_on_encoder(dev, &encoder->base, connector)
14698 return connector;
14699
14700 return NULL;
14701 }
14702
14703 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
14704 enum pipe pch_transcoder)
14705 {
14706 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
14707 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
14708 }
14709
14710 static void intel_sanitize_crtc(struct intel_crtc *crtc,
14711 struct drm_modeset_acquire_ctx *ctx)
14712 {
14713 struct drm_device *dev = crtc->base.dev;
14714 struct drm_i915_private *dev_priv = to_i915(dev);
14715 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
14716
14717 /* Clear any frame start delays used for debugging left by the BIOS */
14718 if (!transcoder_is_dsi(cpu_transcoder)) {
14719 i915_reg_t reg = PIPECONF(cpu_transcoder);
14720
14721 I915_WRITE(reg,
14722 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14723 }
14724
14725 /* restore vblank interrupts to correct state */
14726 drm_crtc_vblank_reset(&crtc->base);
14727 if (crtc->active) {
14728 struct intel_plane *plane;
14729
14730 drm_crtc_vblank_on(&crtc->base);
14731
14732 /* Disable everything but the primary plane */
14733 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14734 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14735 continue;
14736
14737 trace_intel_disable_plane(&plane->base, crtc);
14738 plane->disable_plane(plane, crtc);
14739 }
14740 }
14741
14742 /* We need to sanitize the plane -> pipe mapping first because this will
14743 * disable the crtc (and hence change the state) if it is wrong. Note
14744 * that gen4+ has a fixed plane -> pipe mapping. */
14745 if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
14746 bool plane;
14747
14748 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
14749 crtc->base.base.id, crtc->base.name);
14750
14751 /* Pipe has the wrong plane attached and the plane is active.
14752 * Temporarily change the plane mapping and disable everything
14753 * ... */
14754 plane = crtc->plane;
14755 crtc->base.primary->state->visible = true;
14756 crtc->plane = !plane;
14757 intel_crtc_disable_noatomic(&crtc->base, ctx);
14758 crtc->plane = plane;
14759 }
14760
14761 /* Adjust the state of the output pipe according to whether we
14762 * have active connectors/encoders. */
14763 if (crtc->active && !intel_crtc_has_encoders(crtc))
14764 intel_crtc_disable_noatomic(&crtc->base, ctx);
14765
14766 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
14767 /*
14768 * We start out with underrun reporting disabled to avoid races.
14769 * For correct bookkeeping mark this on active crtcs.
14770 *
14771 * Also on gmch platforms we dont have any hardware bits to
14772 * disable the underrun reporting. Which means we need to start
14773 * out with underrun reporting disabled also on inactive pipes,
14774 * since otherwise we'll complain about the garbage we read when
14775 * e.g. coming up after runtime pm.
14776 *
14777 * No protection against concurrent access is required - at
14778 * worst a fifo underrun happens which also sets this to false.
14779 */
14780 crtc->cpu_fifo_underrun_disabled = true;
14781 /*
14782 * We track the PCH trancoder underrun reporting state
14783 * within the crtc. With crtc for pipe A housing the underrun
14784 * reporting state for PCH transcoder A, crtc for pipe B housing
14785 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
14786 * and marking underrun reporting as disabled for the non-existing
14787 * PCH transcoders B and C would prevent enabling the south
14788 * error interrupt (see cpt_can_enable_serr_int()).
14789 */
14790 if (has_pch_trancoder(dev_priv, crtc->pipe))
14791 crtc->pch_fifo_underrun_disabled = true;
14792 }
14793 }
14794
14795 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14796 {
14797 struct intel_connector *connector;
14798
14799 /* We need to check both for a crtc link (meaning that the
14800 * encoder is active and trying to read from a pipe) and the
14801 * pipe itself being active. */
14802 bool has_active_crtc = encoder->base.crtc &&
14803 to_intel_crtc(encoder->base.crtc)->active;
14804
14805 connector = intel_encoder_find_connector(encoder);
14806 if (connector && !has_active_crtc) {
14807 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14808 encoder->base.base.id,
14809 encoder->base.name);
14810
14811 /* Connector is active, but has no active pipe. This is
14812 * fallout from our resume register restoring. Disable
14813 * the encoder manually again. */
14814 if (encoder->base.crtc) {
14815 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
14816
14817 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14818 encoder->base.base.id,
14819 encoder->base.name);
14820 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14821 if (encoder->post_disable)
14822 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14823 }
14824 encoder->base.crtc = NULL;
14825
14826 /* Inconsistent output/port/pipe state happens presumably due to
14827 * a bug in one of the get_hw_state functions. Or someplace else
14828 * in our code, like the register restore mess on resume. Clamp
14829 * things to off as a safer default. */
14830
14831 connector->base.dpms = DRM_MODE_DPMS_OFF;
14832 connector->base.encoder = NULL;
14833 }
14834 /* Enabled encoders without active connectors will be fixed in
14835 * the crtc fixup. */
14836 }
14837
14838 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
14839 {
14840 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14841
14842 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14843 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14844 i915_disable_vga(dev_priv);
14845 }
14846 }
14847
14848 void i915_redisable_vga(struct drm_i915_private *dev_priv)
14849 {
14850 /* This function can be called both from intel_modeset_setup_hw_state or
14851 * at a very early point in our resume sequence, where the power well
14852 * structures are not yet restored. Since this function is at a very
14853 * paranoid "someone might have enabled VGA while we were not looking"
14854 * level, just check if the power well is enabled instead of trying to
14855 * follow the "don't touch the power well if we don't need it" policy
14856 * the rest of the driver uses. */
14857 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
14858 return;
14859
14860 i915_redisable_vga_power_on(dev_priv);
14861
14862 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
14863 }
14864
14865 static bool primary_get_hw_state(struct intel_plane *plane)
14866 {
14867 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
14868
14869 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
14870 }
14871
14872 /* FIXME read out full plane state for all planes */
14873 static void readout_plane_state(struct intel_crtc *crtc)
14874 {
14875 struct intel_plane *primary = to_intel_plane(crtc->base.primary);
14876 bool visible;
14877
14878 visible = crtc->active && primary_get_hw_state(primary);
14879
14880 intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
14881 to_intel_plane_state(primary->base.state),
14882 visible);
14883 }
14884
14885 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14886 {
14887 struct drm_i915_private *dev_priv = to_i915(dev);
14888 enum pipe pipe;
14889 struct intel_crtc *crtc;
14890 struct intel_encoder *encoder;
14891 struct intel_connector *connector;
14892 struct drm_connector_list_iter conn_iter;
14893 int i;
14894
14895 dev_priv->active_crtcs = 0;
14896
14897 for_each_intel_crtc(dev, crtc) {
14898 struct intel_crtc_state *crtc_state =
14899 to_intel_crtc_state(crtc->base.state);
14900
14901 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
14902 memset(crtc_state, 0, sizeof(*crtc_state));
14903 crtc_state->base.crtc = &crtc->base;
14904
14905 crtc_state->base.active = crtc_state->base.enable =
14906 dev_priv->display.get_pipe_config(crtc, crtc_state);
14907
14908 crtc->base.enabled = crtc_state->base.enable;
14909 crtc->active = crtc_state->base.active;
14910
14911 if (crtc_state->base.active)
14912 dev_priv->active_crtcs |= 1 << crtc->pipe;
14913
14914 readout_plane_state(crtc);
14915
14916 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
14917 crtc->base.base.id, crtc->base.name,
14918 enableddisabled(crtc_state->base.active));
14919 }
14920
14921 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14922 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14923
14924 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
14925 &pll->state.hw_state);
14926 pll->state.crtc_mask = 0;
14927 for_each_intel_crtc(dev, crtc) {
14928 struct intel_crtc_state *crtc_state =
14929 to_intel_crtc_state(crtc->base.state);
14930
14931 if (crtc_state->base.active &&
14932 crtc_state->shared_dpll == pll)
14933 pll->state.crtc_mask |= 1 << crtc->pipe;
14934 }
14935 pll->active_mask = pll->state.crtc_mask;
14936
14937 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14938 pll->name, pll->state.crtc_mask, pll->on);
14939 }
14940
14941 for_each_intel_encoder(dev, encoder) {
14942 pipe = 0;
14943
14944 if (encoder->get_hw_state(encoder, &pipe)) {
14945 struct intel_crtc_state *crtc_state;
14946
14947 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
14948 crtc_state = to_intel_crtc_state(crtc->base.state);
14949
14950 encoder->base.crtc = &crtc->base;
14951 crtc_state->output_types |= 1 << encoder->type;
14952 encoder->get_config(encoder, crtc_state);
14953 } else {
14954 encoder->base.crtc = NULL;
14955 }
14956
14957 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14958 encoder->base.base.id, encoder->base.name,
14959 enableddisabled(encoder->base.crtc),
14960 pipe_name(pipe));
14961 }
14962
14963 drm_connector_list_iter_begin(dev, &conn_iter);
14964 for_each_intel_connector_iter(connector, &conn_iter) {
14965 if (connector->get_hw_state(connector)) {
14966 connector->base.dpms = DRM_MODE_DPMS_ON;
14967
14968 encoder = connector->encoder;
14969 connector->base.encoder = &encoder->base;
14970
14971 if (encoder->base.crtc &&
14972 encoder->base.crtc->state->active) {
14973 /*
14974 * This has to be done during hardware readout
14975 * because anything calling .crtc_disable may
14976 * rely on the connector_mask being accurate.
14977 */
14978 encoder->base.crtc->state->connector_mask |=
14979 1 << drm_connector_index(&connector->base);
14980 encoder->base.crtc->state->encoder_mask |=
14981 1 << drm_encoder_index(&encoder->base);
14982 }
14983
14984 } else {
14985 connector->base.dpms = DRM_MODE_DPMS_OFF;
14986 connector->base.encoder = NULL;
14987 }
14988 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14989 connector->base.base.id, connector->base.name,
14990 enableddisabled(connector->base.encoder));
14991 }
14992 drm_connector_list_iter_end(&conn_iter);
14993
14994 for_each_intel_crtc(dev, crtc) {
14995 struct intel_crtc_state *crtc_state =
14996 to_intel_crtc_state(crtc->base.state);
14997 int min_cdclk = 0;
14998
14999 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15000 if (crtc_state->base.active) {
15001 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15002 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15003 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15004
15005 /*
15006 * The initial mode needs to be set in order to keep
15007 * the atomic core happy. It wants a valid mode if the
15008 * crtc's enabled, so we do the above call.
15009 *
15010 * But we don't set all the derived state fully, hence
15011 * set a flag to indicate that a full recalculation is
15012 * needed on the next commit.
15013 */
15014 crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15015
15016 intel_crtc_compute_pixel_rate(crtc_state);
15017
15018 if (dev_priv->display.modeset_calc_cdclk) {
15019 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
15020 if (WARN_ON(min_cdclk < 0))
15021 min_cdclk = 0;
15022 }
15023
15024 drm_calc_timestamping_constants(&crtc->base,
15025 &crtc_state->base.adjusted_mode);
15026 update_scanline_offset(crtc);
15027 }
15028
15029 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
15030
15031 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15032 }
15033 }
15034
15035 static void
15036 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15037 {
15038 struct intel_encoder *encoder;
15039
15040 for_each_intel_encoder(&dev_priv->drm, encoder) {
15041 u64 get_domains;
15042 enum intel_display_power_domain domain;
15043
15044 if (!encoder->get_power_domains)
15045 continue;
15046
15047 get_domains = encoder->get_power_domains(encoder);
15048 for_each_power_domain(domain, get_domains)
15049 intel_display_power_get(dev_priv, domain);
15050 }
15051 }
15052
15053 /* Scan out the current hw modeset state,
15054 * and sanitizes it to the current state
15055 */
15056 static void
15057 intel_modeset_setup_hw_state(struct drm_device *dev,
15058 struct drm_modeset_acquire_ctx *ctx)
15059 {
15060 struct drm_i915_private *dev_priv = to_i915(dev);
15061 enum pipe pipe;
15062 struct intel_crtc *crtc;
15063 struct intel_encoder *encoder;
15064 int i;
15065
15066 intel_modeset_readout_hw_state(dev);
15067
15068 /* HW state is read out, now we need to sanitize this mess. */
15069 get_encoder_power_domains(dev_priv);
15070
15071 for_each_intel_encoder(dev, encoder) {
15072 intel_sanitize_encoder(encoder);
15073 }
15074
15075 for_each_pipe(dev_priv, pipe) {
15076 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15077
15078 intel_sanitize_crtc(crtc, ctx);
15079 intel_dump_pipe_config(crtc, crtc->config,
15080 "[setup_hw_state]");
15081 }
15082
15083 intel_modeset_update_connector_atomic_state(dev);
15084
15085 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15086 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15087
15088 if (!pll->on || pll->active_mask)
15089 continue;
15090
15091 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15092
15093 pll->funcs.disable(dev_priv, pll);
15094 pll->on = false;
15095 }
15096
15097 if (IS_G4X(dev_priv)) {
15098 g4x_wm_get_hw_state(dev);
15099 g4x_wm_sanitize(dev_priv);
15100 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15101 vlv_wm_get_hw_state(dev);
15102 vlv_wm_sanitize(dev_priv);
15103 } else if (INTEL_GEN(dev_priv) >= 9) {
15104 skl_wm_get_hw_state(dev);
15105 } else if (HAS_PCH_SPLIT(dev_priv)) {
15106 ilk_wm_get_hw_state(dev);
15107 }
15108
15109 for_each_intel_crtc(dev, crtc) {
15110 u64 put_domains;
15111
15112 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15113 if (WARN_ON(put_domains))
15114 modeset_put_power_domains(dev_priv, put_domains);
15115 }
15116 intel_display_set_init_power(dev_priv, false);
15117
15118 intel_power_domains_verify_state(dev_priv);
15119
15120 intel_fbc_init_pipe_state(dev_priv);
15121 }
15122
15123 void intel_display_resume(struct drm_device *dev)
15124 {
15125 struct drm_i915_private *dev_priv = to_i915(dev);
15126 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15127 struct drm_modeset_acquire_ctx ctx;
15128 int ret;
15129
15130 dev_priv->modeset_restore_state = NULL;
15131 if (state)
15132 state->acquire_ctx = &ctx;
15133
15134 drm_modeset_acquire_init(&ctx, 0);
15135
15136 while (1) {
15137 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15138 if (ret != -EDEADLK)
15139 break;
15140
15141 drm_modeset_backoff(&ctx);
15142 }
15143
15144 if (!ret)
15145 ret = __intel_display_resume(dev, state, &ctx);
15146
15147 intel_enable_ipc(dev_priv);
15148 drm_modeset_drop_locks(&ctx);
15149 drm_modeset_acquire_fini(&ctx);
15150
15151 if (ret)
15152 DRM_ERROR("Restoring old state failed with %i\n", ret);
15153 if (state)
15154 drm_atomic_state_put(state);
15155 }
15156
15157 void intel_modeset_gem_init(struct drm_device *dev)
15158 {
15159 struct drm_i915_private *dev_priv = to_i915(dev);
15160
15161 intel_init_gt_powersave(dev_priv);
15162
15163 intel_setup_overlay(dev_priv);
15164 }
15165
15166 int intel_connector_register(struct drm_connector *connector)
15167 {
15168 struct intel_connector *intel_connector = to_intel_connector(connector);
15169 int ret;
15170
15171 ret = intel_backlight_device_register(intel_connector);
15172 if (ret)
15173 goto err;
15174
15175 return 0;
15176
15177 err:
15178 return ret;
15179 }
15180
15181 void intel_connector_unregister(struct drm_connector *connector)
15182 {
15183 struct intel_connector *intel_connector = to_intel_connector(connector);
15184
15185 intel_backlight_device_unregister(intel_connector);
15186 intel_panel_destroy_backlight(connector);
15187 }
15188
15189 void intel_modeset_cleanup(struct drm_device *dev)
15190 {
15191 struct drm_i915_private *dev_priv = to_i915(dev);
15192
15193 flush_work(&dev_priv->atomic_helper.free_work);
15194 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15195
15196 intel_disable_gt_powersave(dev_priv);
15197
15198 /*
15199 * Interrupts and polling as the first thing to avoid creating havoc.
15200 * Too much stuff here (turning of connectors, ...) would
15201 * experience fancy races otherwise.
15202 */
15203 intel_irq_uninstall(dev_priv);
15204
15205 /*
15206 * Due to the hpd irq storm handling the hotplug work can re-arm the
15207 * poll handlers. Hence disable polling after hpd handling is shut down.
15208 */
15209 drm_kms_helper_poll_fini(dev);
15210
15211 /* poll work can call into fbdev, hence clean that up afterwards */
15212 intel_fbdev_fini(dev_priv);
15213
15214 intel_unregister_dsm_handler();
15215
15216 intel_fbc_global_disable(dev_priv);
15217
15218 /* flush any delayed tasks or pending work */
15219 flush_scheduled_work();
15220
15221 drm_mode_config_cleanup(dev);
15222
15223 intel_cleanup_overlay(dev_priv);
15224
15225 intel_cleanup_gt_powersave(dev_priv);
15226
15227 intel_teardown_gmbus(dev_priv);
15228 }
15229
15230 void intel_connector_attach_encoder(struct intel_connector *connector,
15231 struct intel_encoder *encoder)
15232 {
15233 connector->encoder = encoder;
15234 drm_mode_connector_attach_encoder(&connector->base,
15235 &encoder->base);
15236 }
15237
15238 /*
15239 * set vga decode state - true == enable VGA decode
15240 */
15241 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15242 {
15243 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15244 u16 gmch_ctrl;
15245
15246 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15247 DRM_ERROR("failed to read control word\n");
15248 return -EIO;
15249 }
15250
15251 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15252 return 0;
15253
15254 if (state)
15255 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15256 else
15257 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15258
15259 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15260 DRM_ERROR("failed to write control word\n");
15261 return -EIO;
15262 }
15263
15264 return 0;
15265 }
15266
15267 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15268
15269 struct intel_display_error_state {
15270
15271 u32 power_well_driver;
15272
15273 int num_transcoders;
15274
15275 struct intel_cursor_error_state {
15276 u32 control;
15277 u32 position;
15278 u32 base;
15279 u32 size;
15280 } cursor[I915_MAX_PIPES];
15281
15282 struct intel_pipe_error_state {
15283 bool power_domain_on;
15284 u32 source;
15285 u32 stat;
15286 } pipe[I915_MAX_PIPES];
15287
15288 struct intel_plane_error_state {
15289 u32 control;
15290 u32 stride;
15291 u32 size;
15292 u32 pos;
15293 u32 addr;
15294 u32 surface;
15295 u32 tile_offset;
15296 } plane[I915_MAX_PIPES];
15297
15298 struct intel_transcoder_error_state {
15299 bool power_domain_on;
15300 enum transcoder cpu_transcoder;
15301
15302 u32 conf;
15303
15304 u32 htotal;
15305 u32 hblank;
15306 u32 hsync;
15307 u32 vtotal;
15308 u32 vblank;
15309 u32 vsync;
15310 } transcoder[4];
15311 };
15312
15313 struct intel_display_error_state *
15314 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15315 {
15316 struct intel_display_error_state *error;
15317 int transcoders[] = {
15318 TRANSCODER_A,
15319 TRANSCODER_B,
15320 TRANSCODER_C,
15321 TRANSCODER_EDP,
15322 };
15323 int i;
15324
15325 if (INTEL_INFO(dev_priv)->num_pipes == 0)
15326 return NULL;
15327
15328 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15329 if (error == NULL)
15330 return NULL;
15331
15332 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15333 error->power_well_driver =
15334 I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL));
15335
15336 for_each_pipe(dev_priv, i) {
15337 error->pipe[i].power_domain_on =
15338 __intel_display_power_is_enabled(dev_priv,
15339 POWER_DOMAIN_PIPE(i));
15340 if (!error->pipe[i].power_domain_on)
15341 continue;
15342
15343 error->cursor[i].control = I915_READ(CURCNTR(i));
15344 error->cursor[i].position = I915_READ(CURPOS(i));
15345 error->cursor[i].base = I915_READ(CURBASE(i));
15346
15347 error->plane[i].control = I915_READ(DSPCNTR(i));
15348 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15349 if (INTEL_GEN(dev_priv) <= 3) {
15350 error->plane[i].size = I915_READ(DSPSIZE(i));
15351 error->plane[i].pos = I915_READ(DSPPOS(i));
15352 }
15353 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15354 error->plane[i].addr = I915_READ(DSPADDR(i));
15355 if (INTEL_GEN(dev_priv) >= 4) {
15356 error->plane[i].surface = I915_READ(DSPSURF(i));
15357 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15358 }
15359
15360 error->pipe[i].source = I915_READ(PIPESRC(i));
15361
15362 if (HAS_GMCH_DISPLAY(dev_priv))
15363 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15364 }
15365
15366 /* Note: this does not include DSI transcoders. */
15367 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15368 if (HAS_DDI(dev_priv))
15369 error->num_transcoders++; /* Account for eDP. */
15370
15371 for (i = 0; i < error->num_transcoders; i++) {
15372 enum transcoder cpu_transcoder = transcoders[i];
15373
15374 error->transcoder[i].power_domain_on =
15375 __intel_display_power_is_enabled(dev_priv,
15376 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15377 if (!error->transcoder[i].power_domain_on)
15378 continue;
15379
15380 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15381
15382 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15383 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15384 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15385 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15386 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15387 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15388 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15389 }
15390
15391 return error;
15392 }
15393
15394 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15395
15396 void
15397 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15398 struct intel_display_error_state *error)
15399 {
15400 struct drm_i915_private *dev_priv = m->i915;
15401 int i;
15402
15403 if (!error)
15404 return;
15405
15406 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15407 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15408 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15409 error->power_well_driver);
15410 for_each_pipe(dev_priv, i) {
15411 err_printf(m, "Pipe [%d]:\n", i);
15412 err_printf(m, " Power: %s\n",
15413 onoff(error->pipe[i].power_domain_on));
15414 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15415 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15416
15417 err_printf(m, "Plane [%d]:\n", i);
15418 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15419 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15420 if (INTEL_GEN(dev_priv) <= 3) {
15421 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15422 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15423 }
15424 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15425 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15426 if (INTEL_GEN(dev_priv) >= 4) {
15427 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15428 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15429 }
15430
15431 err_printf(m, "Cursor [%d]:\n", i);
15432 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15433 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15434 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15435 }
15436
15437 for (i = 0; i < error->num_transcoders; i++) {
15438 err_printf(m, "CPU transcoder: %s\n",
15439 transcoder_name(error->transcoder[i].cpu_transcoder));
15440 err_printf(m, " Power: %s\n",
15441 onoff(error->transcoder[i].power_domain_on));
15442 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15443 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15444 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15445 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15446 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15447 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15448 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15449 }
15450 }
15451
15452 #endif
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