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Merge tag 'spi-nor/for-4.11-v2' of git://github.com/spi-nor/linux
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "intel_dsi.h"
41 #include "i915_trace.h"
42 #include <drm/drm_atomic.h>
43 #include <drm/drm_atomic_helper.h>
44 #include <drm/drm_dp_helper.h>
45 #include <drm/drm_crtc_helper.h>
46 #include <drm/drm_plane_helper.h>
47 #include <drm/drm_rect.h>
48 #include <linux/dma_remapping.h>
49 #include <linux/reservation.h>
50
51 static bool is_mmio_work(struct intel_flip_work *work)
52 {
53 return work->mmio_work.func;
54 }
55
56 /* Primary plane formats for gen <= 3 */
57 static const uint32_t i8xx_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB1555,
61 DRM_FORMAT_XRGB8888,
62 };
63
64 /* Primary plane formats for gen >= 4 */
65 static const uint32_t i965_primary_formats[] = {
66 DRM_FORMAT_C8,
67 DRM_FORMAT_RGB565,
68 DRM_FORMAT_XRGB8888,
69 DRM_FORMAT_XBGR8888,
70 DRM_FORMAT_XRGB2101010,
71 DRM_FORMAT_XBGR2101010,
72 };
73
74 static const uint32_t skl_primary_formats[] = {
75 DRM_FORMAT_C8,
76 DRM_FORMAT_RGB565,
77 DRM_FORMAT_XRGB8888,
78 DRM_FORMAT_XBGR8888,
79 DRM_FORMAT_ARGB8888,
80 DRM_FORMAT_ABGR8888,
81 DRM_FORMAT_XRGB2101010,
82 DRM_FORMAT_XBGR2101010,
83 DRM_FORMAT_YUYV,
84 DRM_FORMAT_YVYU,
85 DRM_FORMAT_UYVY,
86 DRM_FORMAT_VYUY,
87 };
88
89 /* Cursor formats */
90 static const uint32_t intel_cursor_formats[] = {
91 DRM_FORMAT_ARGB8888,
92 };
93
94 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
95 struct intel_crtc_state *pipe_config);
96 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
97 struct intel_crtc_state *pipe_config);
98
99 static int intel_framebuffer_init(struct drm_device *dev,
100 struct intel_framebuffer *ifb,
101 struct drm_mode_fb_cmd2 *mode_cmd,
102 struct drm_i915_gem_object *obj);
103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
107 struct intel_link_m_n *m_n,
108 struct intel_link_m_n *m2_n2);
109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
112 static void vlv_prepare_pll(struct intel_crtc *crtc,
113 const struct intel_crtc_state *pipe_config);
114 static void chv_prepare_pll(struct intel_crtc *crtc,
115 const struct intel_crtc_state *pipe_config);
116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void skl_init_scalers(struct drm_i915_private *dev_priv,
119 struct intel_crtc *crtc,
120 struct intel_crtc_state *crtc_state);
121 static void skylake_pfit_enable(struct intel_crtc *crtc);
122 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
123 static void ironlake_pfit_enable(struct intel_crtc *crtc);
124 static void intel_modeset_setup_hw_state(struct drm_device *dev);
125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
126 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
127 static int bxt_calc_cdclk(int max_pixclk);
128
129 struct intel_limit {
130 struct {
131 int min, max;
132 } dot, vco, n, m, m1, m2, p, p1;
133
134 struct {
135 int dot_limit;
136 int p2_slow, p2_fast;
137 } p2;
138 };
139
140 /* returns HPLL frequency in kHz */
141 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
142 {
143 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
144
145 /* Obtain SKU information */
146 mutex_lock(&dev_priv->sb_lock);
147 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
148 CCK_FUSE_HPLL_FREQ_MASK;
149 mutex_unlock(&dev_priv->sb_lock);
150
151 return vco_freq[hpll_freq] * 1000;
152 }
153
154 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
155 const char *name, u32 reg, int ref_freq)
156 {
157 u32 val;
158 int divider;
159
160 mutex_lock(&dev_priv->sb_lock);
161 val = vlv_cck_read(dev_priv, reg);
162 mutex_unlock(&dev_priv->sb_lock);
163
164 divider = val & CCK_FREQUENCY_VALUES;
165
166 WARN((val & CCK_FREQUENCY_STATUS) !=
167 (divider << CCK_FREQUENCY_STATUS_SHIFT),
168 "%s change in progress\n", name);
169
170 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
171 }
172
173 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
174 const char *name, u32 reg)
175 {
176 if (dev_priv->hpll_freq == 0)
177 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
178
179 return vlv_get_cck_clock(dev_priv, name, reg,
180 dev_priv->hpll_freq);
181 }
182
183 static int
184 intel_pch_rawclk(struct drm_i915_private *dev_priv)
185 {
186 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
187 }
188
189 static int
190 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
191 {
192 /* RAWCLK_FREQ_VLV register updated from power well code */
193 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
194 CCK_DISPLAY_REF_CLOCK_CONTROL);
195 }
196
197 static int
198 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
199 {
200 uint32_t clkcfg;
201
202 /* hrawclock is 1/4 the FSB frequency */
203 clkcfg = I915_READ(CLKCFG);
204 switch (clkcfg & CLKCFG_FSB_MASK) {
205 case CLKCFG_FSB_400:
206 return 100000;
207 case CLKCFG_FSB_533:
208 return 133333;
209 case CLKCFG_FSB_667:
210 return 166667;
211 case CLKCFG_FSB_800:
212 return 200000;
213 case CLKCFG_FSB_1067:
214 return 266667;
215 case CLKCFG_FSB_1333:
216 return 333333;
217 /* these two are just a guess; one of them might be right */
218 case CLKCFG_FSB_1600:
219 case CLKCFG_FSB_1600_ALT:
220 return 400000;
221 default:
222 return 133333;
223 }
224 }
225
226 void intel_update_rawclk(struct drm_i915_private *dev_priv)
227 {
228 if (HAS_PCH_SPLIT(dev_priv))
229 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
230 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
231 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
232 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
233 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
234 else
235 return; /* no rawclk on other platforms, or no need to know it */
236
237 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
238 }
239
240 static void intel_update_czclk(struct drm_i915_private *dev_priv)
241 {
242 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
243 return;
244
245 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
246 CCK_CZ_CLOCK_CONTROL);
247
248 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
249 }
250
251 static inline u32 /* units of 100MHz */
252 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
253 const struct intel_crtc_state *pipe_config)
254 {
255 if (HAS_DDI(dev_priv))
256 return pipe_config->port_clock; /* SPLL */
257 else if (IS_GEN5(dev_priv))
258 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
259 else
260 return 270000;
261 }
262
263 static const struct intel_limit intel_limits_i8xx_dac = {
264 .dot = { .min = 25000, .max = 350000 },
265 .vco = { .min = 908000, .max = 1512000 },
266 .n = { .min = 2, .max = 16 },
267 .m = { .min = 96, .max = 140 },
268 .m1 = { .min = 18, .max = 26 },
269 .m2 = { .min = 6, .max = 16 },
270 .p = { .min = 4, .max = 128 },
271 .p1 = { .min = 2, .max = 33 },
272 .p2 = { .dot_limit = 165000,
273 .p2_slow = 4, .p2_fast = 2 },
274 };
275
276 static const struct intel_limit intel_limits_i8xx_dvo = {
277 .dot = { .min = 25000, .max = 350000 },
278 .vco = { .min = 908000, .max = 1512000 },
279 .n = { .min = 2, .max = 16 },
280 .m = { .min = 96, .max = 140 },
281 .m1 = { .min = 18, .max = 26 },
282 .m2 = { .min = 6, .max = 16 },
283 .p = { .min = 4, .max = 128 },
284 .p1 = { .min = 2, .max = 33 },
285 .p2 = { .dot_limit = 165000,
286 .p2_slow = 4, .p2_fast = 4 },
287 };
288
289 static const struct intel_limit intel_limits_i8xx_lvds = {
290 .dot = { .min = 25000, .max = 350000 },
291 .vco = { .min = 908000, .max = 1512000 },
292 .n = { .min = 2, .max = 16 },
293 .m = { .min = 96, .max = 140 },
294 .m1 = { .min = 18, .max = 26 },
295 .m2 = { .min = 6, .max = 16 },
296 .p = { .min = 4, .max = 128 },
297 .p1 = { .min = 1, .max = 6 },
298 .p2 = { .dot_limit = 165000,
299 .p2_slow = 14, .p2_fast = 7 },
300 };
301
302 static const struct intel_limit intel_limits_i9xx_sdvo = {
303 .dot = { .min = 20000, .max = 400000 },
304 .vco = { .min = 1400000, .max = 2800000 },
305 .n = { .min = 1, .max = 6 },
306 .m = { .min = 70, .max = 120 },
307 .m1 = { .min = 8, .max = 18 },
308 .m2 = { .min = 3, .max = 7 },
309 .p = { .min = 5, .max = 80 },
310 .p1 = { .min = 1, .max = 8 },
311 .p2 = { .dot_limit = 200000,
312 .p2_slow = 10, .p2_fast = 5 },
313 };
314
315 static const struct intel_limit intel_limits_i9xx_lvds = {
316 .dot = { .min = 20000, .max = 400000 },
317 .vco = { .min = 1400000, .max = 2800000 },
318 .n = { .min = 1, .max = 6 },
319 .m = { .min = 70, .max = 120 },
320 .m1 = { .min = 8, .max = 18 },
321 .m2 = { .min = 3, .max = 7 },
322 .p = { .min = 7, .max = 98 },
323 .p1 = { .min = 1, .max = 8 },
324 .p2 = { .dot_limit = 112000,
325 .p2_slow = 14, .p2_fast = 7 },
326 };
327
328
329 static const struct intel_limit intel_limits_g4x_sdvo = {
330 .dot = { .min = 25000, .max = 270000 },
331 .vco = { .min = 1750000, .max = 3500000},
332 .n = { .min = 1, .max = 4 },
333 .m = { .min = 104, .max = 138 },
334 .m1 = { .min = 17, .max = 23 },
335 .m2 = { .min = 5, .max = 11 },
336 .p = { .min = 10, .max = 30 },
337 .p1 = { .min = 1, .max = 3},
338 .p2 = { .dot_limit = 270000,
339 .p2_slow = 10,
340 .p2_fast = 10
341 },
342 };
343
344 static const struct intel_limit intel_limits_g4x_hdmi = {
345 .dot = { .min = 22000, .max = 400000 },
346 .vco = { .min = 1750000, .max = 3500000},
347 .n = { .min = 1, .max = 4 },
348 .m = { .min = 104, .max = 138 },
349 .m1 = { .min = 16, .max = 23 },
350 .m2 = { .min = 5, .max = 11 },
351 .p = { .min = 5, .max = 80 },
352 .p1 = { .min = 1, .max = 8},
353 .p2 = { .dot_limit = 165000,
354 .p2_slow = 10, .p2_fast = 5 },
355 };
356
357 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
358 .dot = { .min = 20000, .max = 115000 },
359 .vco = { .min = 1750000, .max = 3500000 },
360 .n = { .min = 1, .max = 3 },
361 .m = { .min = 104, .max = 138 },
362 .m1 = { .min = 17, .max = 23 },
363 .m2 = { .min = 5, .max = 11 },
364 .p = { .min = 28, .max = 112 },
365 .p1 = { .min = 2, .max = 8 },
366 .p2 = { .dot_limit = 0,
367 .p2_slow = 14, .p2_fast = 14
368 },
369 };
370
371 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
372 .dot = { .min = 80000, .max = 224000 },
373 .vco = { .min = 1750000, .max = 3500000 },
374 .n = { .min = 1, .max = 3 },
375 .m = { .min = 104, .max = 138 },
376 .m1 = { .min = 17, .max = 23 },
377 .m2 = { .min = 5, .max = 11 },
378 .p = { .min = 14, .max = 42 },
379 .p1 = { .min = 2, .max = 6 },
380 .p2 = { .dot_limit = 0,
381 .p2_slow = 7, .p2_fast = 7
382 },
383 };
384
385 static const struct intel_limit intel_limits_pineview_sdvo = {
386 .dot = { .min = 20000, .max = 400000},
387 .vco = { .min = 1700000, .max = 3500000 },
388 /* Pineview's Ncounter is a ring counter */
389 .n = { .min = 3, .max = 6 },
390 .m = { .min = 2, .max = 256 },
391 /* Pineview only has one combined m divider, which we treat as m2. */
392 .m1 = { .min = 0, .max = 0 },
393 .m2 = { .min = 0, .max = 254 },
394 .p = { .min = 5, .max = 80 },
395 .p1 = { .min = 1, .max = 8 },
396 .p2 = { .dot_limit = 200000,
397 .p2_slow = 10, .p2_fast = 5 },
398 };
399
400 static const struct intel_limit intel_limits_pineview_lvds = {
401 .dot = { .min = 20000, .max = 400000 },
402 .vco = { .min = 1700000, .max = 3500000 },
403 .n = { .min = 3, .max = 6 },
404 .m = { .min = 2, .max = 256 },
405 .m1 = { .min = 0, .max = 0 },
406 .m2 = { .min = 0, .max = 254 },
407 .p = { .min = 7, .max = 112 },
408 .p1 = { .min = 1, .max = 8 },
409 .p2 = { .dot_limit = 112000,
410 .p2_slow = 14, .p2_fast = 14 },
411 };
412
413 /* Ironlake / Sandybridge
414 *
415 * We calculate clock using (register_value + 2) for N/M1/M2, so here
416 * the range value for them is (actual_value - 2).
417 */
418 static const struct intel_limit intel_limits_ironlake_dac = {
419 .dot = { .min = 25000, .max = 350000 },
420 .vco = { .min = 1760000, .max = 3510000 },
421 .n = { .min = 1, .max = 5 },
422 .m = { .min = 79, .max = 127 },
423 .m1 = { .min = 12, .max = 22 },
424 .m2 = { .min = 5, .max = 9 },
425 .p = { .min = 5, .max = 80 },
426 .p1 = { .min = 1, .max = 8 },
427 .p2 = { .dot_limit = 225000,
428 .p2_slow = 10, .p2_fast = 5 },
429 };
430
431 static const struct intel_limit intel_limits_ironlake_single_lvds = {
432 .dot = { .min = 25000, .max = 350000 },
433 .vco = { .min = 1760000, .max = 3510000 },
434 .n = { .min = 1, .max = 3 },
435 .m = { .min = 79, .max = 118 },
436 .m1 = { .min = 12, .max = 22 },
437 .m2 = { .min = 5, .max = 9 },
438 .p = { .min = 28, .max = 112 },
439 .p1 = { .min = 2, .max = 8 },
440 .p2 = { .dot_limit = 225000,
441 .p2_slow = 14, .p2_fast = 14 },
442 };
443
444 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
445 .dot = { .min = 25000, .max = 350000 },
446 .vco = { .min = 1760000, .max = 3510000 },
447 .n = { .min = 1, .max = 3 },
448 .m = { .min = 79, .max = 127 },
449 .m1 = { .min = 12, .max = 22 },
450 .m2 = { .min = 5, .max = 9 },
451 .p = { .min = 14, .max = 56 },
452 .p1 = { .min = 2, .max = 8 },
453 .p2 = { .dot_limit = 225000,
454 .p2_slow = 7, .p2_fast = 7 },
455 };
456
457 /* LVDS 100mhz refclk limits. */
458 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
459 .dot = { .min = 25000, .max = 350000 },
460 .vco = { .min = 1760000, .max = 3510000 },
461 .n = { .min = 1, .max = 2 },
462 .m = { .min = 79, .max = 126 },
463 .m1 = { .min = 12, .max = 22 },
464 .m2 = { .min = 5, .max = 9 },
465 .p = { .min = 28, .max = 112 },
466 .p1 = { .min = 2, .max = 8 },
467 .p2 = { .dot_limit = 225000,
468 .p2_slow = 14, .p2_fast = 14 },
469 };
470
471 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
472 .dot = { .min = 25000, .max = 350000 },
473 .vco = { .min = 1760000, .max = 3510000 },
474 .n = { .min = 1, .max = 3 },
475 .m = { .min = 79, .max = 126 },
476 .m1 = { .min = 12, .max = 22 },
477 .m2 = { .min = 5, .max = 9 },
478 .p = { .min = 14, .max = 42 },
479 .p1 = { .min = 2, .max = 6 },
480 .p2 = { .dot_limit = 225000,
481 .p2_slow = 7, .p2_fast = 7 },
482 };
483
484 static const struct intel_limit intel_limits_vlv = {
485 /*
486 * These are the data rate limits (measured in fast clocks)
487 * since those are the strictest limits we have. The fast
488 * clock and actual rate limits are more relaxed, so checking
489 * them would make no difference.
490 */
491 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
492 .vco = { .min = 4000000, .max = 6000000 },
493 .n = { .min = 1, .max = 7 },
494 .m1 = { .min = 2, .max = 3 },
495 .m2 = { .min = 11, .max = 156 },
496 .p1 = { .min = 2, .max = 3 },
497 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
498 };
499
500 static const struct intel_limit intel_limits_chv = {
501 /*
502 * These are the data rate limits (measured in fast clocks)
503 * since those are the strictest limits we have. The fast
504 * clock and actual rate limits are more relaxed, so checking
505 * them would make no difference.
506 */
507 .dot = { .min = 25000 * 5, .max = 540000 * 5},
508 .vco = { .min = 4800000, .max = 6480000 },
509 .n = { .min = 1, .max = 1 },
510 .m1 = { .min = 2, .max = 2 },
511 .m2 = { .min = 24 << 22, .max = 175 << 22 },
512 .p1 = { .min = 2, .max = 4 },
513 .p2 = { .p2_slow = 1, .p2_fast = 14 },
514 };
515
516 static const struct intel_limit intel_limits_bxt = {
517 /* FIXME: find real dot limits */
518 .dot = { .min = 0, .max = INT_MAX },
519 .vco = { .min = 4800000, .max = 6700000 },
520 .n = { .min = 1, .max = 1 },
521 .m1 = { .min = 2, .max = 2 },
522 /* FIXME: find real m2 limits */
523 .m2 = { .min = 2 << 22, .max = 255 << 22 },
524 .p1 = { .min = 2, .max = 4 },
525 .p2 = { .p2_slow = 1, .p2_fast = 20 },
526 };
527
528 static bool
529 needs_modeset(struct drm_crtc_state *state)
530 {
531 return drm_atomic_crtc_needs_modeset(state);
532 }
533
534 /*
535 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
536 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
537 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
538 * The helpers' return value is the rate of the clock that is fed to the
539 * display engine's pipe which can be the above fast dot clock rate or a
540 * divided-down version of it.
541 */
542 /* m1 is reserved as 0 in Pineview, n is a ring counter */
543 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
544 {
545 clock->m = clock->m2 + 2;
546 clock->p = clock->p1 * clock->p2;
547 if (WARN_ON(clock->n == 0 || clock->p == 0))
548 return 0;
549 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
550 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
551
552 return clock->dot;
553 }
554
555 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
556 {
557 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
558 }
559
560 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
561 {
562 clock->m = i9xx_dpll_compute_m(clock);
563 clock->p = clock->p1 * clock->p2;
564 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
565 return 0;
566 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
567 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
568
569 return clock->dot;
570 }
571
572 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
573 {
574 clock->m = clock->m1 * clock->m2;
575 clock->p = clock->p1 * clock->p2;
576 if (WARN_ON(clock->n == 0 || clock->p == 0))
577 return 0;
578 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
579 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
580
581 return clock->dot / 5;
582 }
583
584 int chv_calc_dpll_params(int refclk, struct dpll *clock)
585 {
586 clock->m = clock->m1 * clock->m2;
587 clock->p = clock->p1 * clock->p2;
588 if (WARN_ON(clock->n == 0 || clock->p == 0))
589 return 0;
590 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
591 clock->n << 22);
592 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
593
594 return clock->dot / 5;
595 }
596
597 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
598 /**
599 * Returns whether the given set of divisors are valid for a given refclk with
600 * the given connectors.
601 */
602
603 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
604 const struct intel_limit *limit,
605 const struct dpll *clock)
606 {
607 if (clock->n < limit->n.min || limit->n.max < clock->n)
608 INTELPllInvalid("n out of range\n");
609 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
610 INTELPllInvalid("p1 out of range\n");
611 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
612 INTELPllInvalid("m2 out of range\n");
613 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
614 INTELPllInvalid("m1 out of range\n");
615
616 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
617 !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv))
618 if (clock->m1 <= clock->m2)
619 INTELPllInvalid("m1 <= m2\n");
620
621 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
622 !IS_BROXTON(dev_priv)) {
623 if (clock->p < limit->p.min || limit->p.max < clock->p)
624 INTELPllInvalid("p out of range\n");
625 if (clock->m < limit->m.min || limit->m.max < clock->m)
626 INTELPllInvalid("m out of range\n");
627 }
628
629 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
630 INTELPllInvalid("vco out of range\n");
631 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
632 * connector, etc., rather than just a single range.
633 */
634 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
635 INTELPllInvalid("dot out of range\n");
636
637 return true;
638 }
639
640 static int
641 i9xx_select_p2_div(const struct intel_limit *limit,
642 const struct intel_crtc_state *crtc_state,
643 int target)
644 {
645 struct drm_device *dev = crtc_state->base.crtc->dev;
646
647 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
648 /*
649 * For LVDS just rely on its current settings for dual-channel.
650 * We haven't figured out how to reliably set up different
651 * single/dual channel state, if we even can.
652 */
653 if (intel_is_dual_link_lvds(dev))
654 return limit->p2.p2_fast;
655 else
656 return limit->p2.p2_slow;
657 } else {
658 if (target < limit->p2.dot_limit)
659 return limit->p2.p2_slow;
660 else
661 return limit->p2.p2_fast;
662 }
663 }
664
665 /*
666 * Returns a set of divisors for the desired target clock with the given
667 * refclk, or FALSE. The returned values represent the clock equation:
668 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
669 *
670 * Target and reference clocks are specified in kHz.
671 *
672 * If match_clock is provided, then best_clock P divider must match the P
673 * divider from @match_clock used for LVDS downclocking.
674 */
675 static bool
676 i9xx_find_best_dpll(const struct intel_limit *limit,
677 struct intel_crtc_state *crtc_state,
678 int target, int refclk, struct dpll *match_clock,
679 struct dpll *best_clock)
680 {
681 struct drm_device *dev = crtc_state->base.crtc->dev;
682 struct dpll clock;
683 int err = target;
684
685 memset(best_clock, 0, sizeof(*best_clock));
686
687 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
688
689 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
690 clock.m1++) {
691 for (clock.m2 = limit->m2.min;
692 clock.m2 <= limit->m2.max; clock.m2++) {
693 if (clock.m2 >= clock.m1)
694 break;
695 for (clock.n = limit->n.min;
696 clock.n <= limit->n.max; clock.n++) {
697 for (clock.p1 = limit->p1.min;
698 clock.p1 <= limit->p1.max; clock.p1++) {
699 int this_err;
700
701 i9xx_calc_dpll_params(refclk, &clock);
702 if (!intel_PLL_is_valid(to_i915(dev),
703 limit,
704 &clock))
705 continue;
706 if (match_clock &&
707 clock.p != match_clock->p)
708 continue;
709
710 this_err = abs(clock.dot - target);
711 if (this_err < err) {
712 *best_clock = clock;
713 err = this_err;
714 }
715 }
716 }
717 }
718 }
719
720 return (err != target);
721 }
722
723 /*
724 * Returns a set of divisors for the desired target clock with the given
725 * refclk, or FALSE. The returned values represent the clock equation:
726 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
727 *
728 * Target and reference clocks are specified in kHz.
729 *
730 * If match_clock is provided, then best_clock P divider must match the P
731 * divider from @match_clock used for LVDS downclocking.
732 */
733 static bool
734 pnv_find_best_dpll(const struct intel_limit *limit,
735 struct intel_crtc_state *crtc_state,
736 int target, int refclk, struct dpll *match_clock,
737 struct dpll *best_clock)
738 {
739 struct drm_device *dev = crtc_state->base.crtc->dev;
740 struct dpll clock;
741 int err = target;
742
743 memset(best_clock, 0, sizeof(*best_clock));
744
745 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
746
747 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
748 clock.m1++) {
749 for (clock.m2 = limit->m2.min;
750 clock.m2 <= limit->m2.max; clock.m2++) {
751 for (clock.n = limit->n.min;
752 clock.n <= limit->n.max; clock.n++) {
753 for (clock.p1 = limit->p1.min;
754 clock.p1 <= limit->p1.max; clock.p1++) {
755 int this_err;
756
757 pnv_calc_dpll_params(refclk, &clock);
758 if (!intel_PLL_is_valid(to_i915(dev),
759 limit,
760 &clock))
761 continue;
762 if (match_clock &&
763 clock.p != match_clock->p)
764 continue;
765
766 this_err = abs(clock.dot - target);
767 if (this_err < err) {
768 *best_clock = clock;
769 err = this_err;
770 }
771 }
772 }
773 }
774 }
775
776 return (err != target);
777 }
778
779 /*
780 * Returns a set of divisors for the desired target clock with the given
781 * refclk, or FALSE. The returned values represent the clock equation:
782 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
783 *
784 * Target and reference clocks are specified in kHz.
785 *
786 * If match_clock is provided, then best_clock P divider must match the P
787 * divider from @match_clock used for LVDS downclocking.
788 */
789 static bool
790 g4x_find_best_dpll(const struct intel_limit *limit,
791 struct intel_crtc_state *crtc_state,
792 int target, int refclk, struct dpll *match_clock,
793 struct dpll *best_clock)
794 {
795 struct drm_device *dev = crtc_state->base.crtc->dev;
796 struct dpll clock;
797 int max_n;
798 bool found = false;
799 /* approximately equals target * 0.00585 */
800 int err_most = (target >> 8) + (target >> 9);
801
802 memset(best_clock, 0, sizeof(*best_clock));
803
804 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
805
806 max_n = limit->n.max;
807 /* based on hardware requirement, prefer smaller n to precision */
808 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
809 /* based on hardware requirement, prefere larger m1,m2 */
810 for (clock.m1 = limit->m1.max;
811 clock.m1 >= limit->m1.min; clock.m1--) {
812 for (clock.m2 = limit->m2.max;
813 clock.m2 >= limit->m2.min; clock.m2--) {
814 for (clock.p1 = limit->p1.max;
815 clock.p1 >= limit->p1.min; clock.p1--) {
816 int this_err;
817
818 i9xx_calc_dpll_params(refclk, &clock);
819 if (!intel_PLL_is_valid(to_i915(dev),
820 limit,
821 &clock))
822 continue;
823
824 this_err = abs(clock.dot - target);
825 if (this_err < err_most) {
826 *best_clock = clock;
827 err_most = this_err;
828 max_n = clock.n;
829 found = true;
830 }
831 }
832 }
833 }
834 }
835 return found;
836 }
837
838 /*
839 * Check if the calculated PLL configuration is more optimal compared to the
840 * best configuration and error found so far. Return the calculated error.
841 */
842 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
843 const struct dpll *calculated_clock,
844 const struct dpll *best_clock,
845 unsigned int best_error_ppm,
846 unsigned int *error_ppm)
847 {
848 /*
849 * For CHV ignore the error and consider only the P value.
850 * Prefer a bigger P value based on HW requirements.
851 */
852 if (IS_CHERRYVIEW(to_i915(dev))) {
853 *error_ppm = 0;
854
855 return calculated_clock->p > best_clock->p;
856 }
857
858 if (WARN_ON_ONCE(!target_freq))
859 return false;
860
861 *error_ppm = div_u64(1000000ULL *
862 abs(target_freq - calculated_clock->dot),
863 target_freq);
864 /*
865 * Prefer a better P value over a better (smaller) error if the error
866 * is small. Ensure this preference for future configurations too by
867 * setting the error to 0.
868 */
869 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
870 *error_ppm = 0;
871
872 return true;
873 }
874
875 return *error_ppm + 10 < best_error_ppm;
876 }
877
878 /*
879 * Returns a set of divisors for the desired target clock with the given
880 * refclk, or FALSE. The returned values represent the clock equation:
881 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
882 */
883 static bool
884 vlv_find_best_dpll(const struct intel_limit *limit,
885 struct intel_crtc_state *crtc_state,
886 int target, int refclk, struct dpll *match_clock,
887 struct dpll *best_clock)
888 {
889 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
890 struct drm_device *dev = crtc->base.dev;
891 struct dpll clock;
892 unsigned int bestppm = 1000000;
893 /* min update 19.2 MHz */
894 int max_n = min(limit->n.max, refclk / 19200);
895 bool found = false;
896
897 target *= 5; /* fast clock */
898
899 memset(best_clock, 0, sizeof(*best_clock));
900
901 /* based on hardware requirement, prefer smaller n to precision */
902 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
903 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
904 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
905 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
906 clock.p = clock.p1 * clock.p2;
907 /* based on hardware requirement, prefer bigger m1,m2 values */
908 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
909 unsigned int ppm;
910
911 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
912 refclk * clock.m1);
913
914 vlv_calc_dpll_params(refclk, &clock);
915
916 if (!intel_PLL_is_valid(to_i915(dev),
917 limit,
918 &clock))
919 continue;
920
921 if (!vlv_PLL_is_optimal(dev, target,
922 &clock,
923 best_clock,
924 bestppm, &ppm))
925 continue;
926
927 *best_clock = clock;
928 bestppm = ppm;
929 found = true;
930 }
931 }
932 }
933 }
934
935 return found;
936 }
937
938 /*
939 * Returns a set of divisors for the desired target clock with the given
940 * refclk, or FALSE. The returned values represent the clock equation:
941 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
942 */
943 static bool
944 chv_find_best_dpll(const struct intel_limit *limit,
945 struct intel_crtc_state *crtc_state,
946 int target, int refclk, struct dpll *match_clock,
947 struct dpll *best_clock)
948 {
949 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
950 struct drm_device *dev = crtc->base.dev;
951 unsigned int best_error_ppm;
952 struct dpll clock;
953 uint64_t m2;
954 int found = false;
955
956 memset(best_clock, 0, sizeof(*best_clock));
957 best_error_ppm = 1000000;
958
959 /*
960 * Based on hardware doc, the n always set to 1, and m1 always
961 * set to 2. If requires to support 200Mhz refclk, we need to
962 * revisit this because n may not 1 anymore.
963 */
964 clock.n = 1, clock.m1 = 2;
965 target *= 5; /* fast clock */
966
967 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
968 for (clock.p2 = limit->p2.p2_fast;
969 clock.p2 >= limit->p2.p2_slow;
970 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
971 unsigned int error_ppm;
972
973 clock.p = clock.p1 * clock.p2;
974
975 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
976 clock.n) << 22, refclk * clock.m1);
977
978 if (m2 > INT_MAX/clock.m1)
979 continue;
980
981 clock.m2 = m2;
982
983 chv_calc_dpll_params(refclk, &clock);
984
985 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
986 continue;
987
988 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
989 best_error_ppm, &error_ppm))
990 continue;
991
992 *best_clock = clock;
993 best_error_ppm = error_ppm;
994 found = true;
995 }
996 }
997
998 return found;
999 }
1000
1001 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1002 struct dpll *best_clock)
1003 {
1004 int refclk = 100000;
1005 const struct intel_limit *limit = &intel_limits_bxt;
1006
1007 return chv_find_best_dpll(limit, crtc_state,
1008 target_clock, refclk, NULL, best_clock);
1009 }
1010
1011 bool intel_crtc_active(struct intel_crtc *crtc)
1012 {
1013 /* Be paranoid as we can arrive here with only partial
1014 * state retrieved from the hardware during setup.
1015 *
1016 * We can ditch the adjusted_mode.crtc_clock check as soon
1017 * as Haswell has gained clock readout/fastboot support.
1018 *
1019 * We can ditch the crtc->primary->fb check as soon as we can
1020 * properly reconstruct framebuffers.
1021 *
1022 * FIXME: The intel_crtc->active here should be switched to
1023 * crtc->state->active once we have proper CRTC states wired up
1024 * for atomic.
1025 */
1026 return crtc->active && crtc->base.primary->state->fb &&
1027 crtc->config->base.adjusted_mode.crtc_clock;
1028 }
1029
1030 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1031 enum pipe pipe)
1032 {
1033 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1034
1035 return crtc->config->cpu_transcoder;
1036 }
1037
1038 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
1039 {
1040 i915_reg_t reg = PIPEDSL(pipe);
1041 u32 line1, line2;
1042 u32 line_mask;
1043
1044 if (IS_GEN2(dev_priv))
1045 line_mask = DSL_LINEMASK_GEN2;
1046 else
1047 line_mask = DSL_LINEMASK_GEN3;
1048
1049 line1 = I915_READ(reg) & line_mask;
1050 msleep(5);
1051 line2 = I915_READ(reg) & line_mask;
1052
1053 return line1 == line2;
1054 }
1055
1056 /*
1057 * intel_wait_for_pipe_off - wait for pipe to turn off
1058 * @crtc: crtc whose pipe to wait for
1059 *
1060 * After disabling a pipe, we can't wait for vblank in the usual way,
1061 * spinning on the vblank interrupt status bit, since we won't actually
1062 * see an interrupt when the pipe is disabled.
1063 *
1064 * On Gen4 and above:
1065 * wait for the pipe register state bit to turn off
1066 *
1067 * Otherwise:
1068 * wait for the display line value to settle (it usually
1069 * ends up stopping at the start of the next frame).
1070 *
1071 */
1072 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1073 {
1074 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1075 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1076 enum pipe pipe = crtc->pipe;
1077
1078 if (INTEL_GEN(dev_priv) >= 4) {
1079 i915_reg_t reg = PIPECONF(cpu_transcoder);
1080
1081 /* Wait for the Pipe State to go off */
1082 if (intel_wait_for_register(dev_priv,
1083 reg, I965_PIPECONF_ACTIVE, 0,
1084 100))
1085 WARN(1, "pipe_off wait timed out\n");
1086 } else {
1087 /* Wait for the display line to settle */
1088 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1089 WARN(1, "pipe_off wait timed out\n");
1090 }
1091 }
1092
1093 /* Only for pre-ILK configs */
1094 void assert_pll(struct drm_i915_private *dev_priv,
1095 enum pipe pipe, bool state)
1096 {
1097 u32 val;
1098 bool cur_state;
1099
1100 val = I915_READ(DPLL(pipe));
1101 cur_state = !!(val & DPLL_VCO_ENABLE);
1102 I915_STATE_WARN(cur_state != state,
1103 "PLL state assertion failure (expected %s, current %s)\n",
1104 onoff(state), onoff(cur_state));
1105 }
1106
1107 /* XXX: the dsi pll is shared between MIPI DSI ports */
1108 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1109 {
1110 u32 val;
1111 bool cur_state;
1112
1113 mutex_lock(&dev_priv->sb_lock);
1114 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1115 mutex_unlock(&dev_priv->sb_lock);
1116
1117 cur_state = val & DSI_PLL_VCO_EN;
1118 I915_STATE_WARN(cur_state != state,
1119 "DSI PLL state assertion failure (expected %s, current %s)\n",
1120 onoff(state), onoff(cur_state));
1121 }
1122
1123 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1124 enum pipe pipe, bool state)
1125 {
1126 bool cur_state;
1127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128 pipe);
1129
1130 if (HAS_DDI(dev_priv)) {
1131 /* DDI does not have a specific FDI_TX register */
1132 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1133 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1134 } else {
1135 u32 val = I915_READ(FDI_TX_CTL(pipe));
1136 cur_state = !!(val & FDI_TX_ENABLE);
1137 }
1138 I915_STATE_WARN(cur_state != state,
1139 "FDI TX state assertion failure (expected %s, current %s)\n",
1140 onoff(state), onoff(cur_state));
1141 }
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146 enum pipe pipe, bool state)
1147 {
1148 u32 val;
1149 bool cur_state;
1150
1151 val = I915_READ(FDI_RX_CTL(pipe));
1152 cur_state = !!(val & FDI_RX_ENABLE);
1153 I915_STATE_WARN(cur_state != state,
1154 "FDI RX state assertion failure (expected %s, current %s)\n",
1155 onoff(state), onoff(cur_state));
1156 }
1157 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1158 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1159
1160 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1161 enum pipe pipe)
1162 {
1163 u32 val;
1164
1165 /* ILK FDI PLL is always enabled */
1166 if (IS_GEN5(dev_priv))
1167 return;
1168
1169 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1170 if (HAS_DDI(dev_priv))
1171 return;
1172
1173 val = I915_READ(FDI_TX_CTL(pipe));
1174 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178 enum pipe pipe, bool state)
1179 {
1180 u32 val;
1181 bool cur_state;
1182
1183 val = I915_READ(FDI_RX_CTL(pipe));
1184 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1185 I915_STATE_WARN(cur_state != state,
1186 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1187 onoff(state), onoff(cur_state));
1188 }
1189
1190 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1191 {
1192 i915_reg_t pp_reg;
1193 u32 val;
1194 enum pipe panel_pipe = PIPE_A;
1195 bool locked = true;
1196
1197 if (WARN_ON(HAS_DDI(dev_priv)))
1198 return;
1199
1200 if (HAS_PCH_SPLIT(dev_priv)) {
1201 u32 port_sel;
1202
1203 pp_reg = PP_CONTROL(0);
1204 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1205
1206 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1207 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1208 panel_pipe = PIPE_B;
1209 /* XXX: else fix for eDP */
1210 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1211 /* presumably write lock depends on pipe, not port select */
1212 pp_reg = PP_CONTROL(pipe);
1213 panel_pipe = pipe;
1214 } else {
1215 pp_reg = PP_CONTROL(0);
1216 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1217 panel_pipe = PIPE_B;
1218 }
1219
1220 val = I915_READ(pp_reg);
1221 if (!(val & PANEL_POWER_ON) ||
1222 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1223 locked = false;
1224
1225 I915_STATE_WARN(panel_pipe == pipe && locked,
1226 "panel assertion failure, pipe %c regs locked\n",
1227 pipe_name(pipe));
1228 }
1229
1230 static void assert_cursor(struct drm_i915_private *dev_priv,
1231 enum pipe pipe, bool state)
1232 {
1233 bool cur_state;
1234
1235 if (IS_845G(dev_priv) || IS_I865G(dev_priv))
1236 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1237 else
1238 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1239
1240 I915_STATE_WARN(cur_state != state,
1241 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1242 pipe_name(pipe), onoff(state), onoff(cur_state));
1243 }
1244 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1245 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1246
1247 void assert_pipe(struct drm_i915_private *dev_priv,
1248 enum pipe pipe, bool state)
1249 {
1250 bool cur_state;
1251 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1252 pipe);
1253 enum intel_display_power_domain power_domain;
1254
1255 /* if we need the pipe quirk it must be always on */
1256 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1257 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1258 state = true;
1259
1260 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1261 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1262 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1263 cur_state = !!(val & PIPECONF_ENABLE);
1264
1265 intel_display_power_put(dev_priv, power_domain);
1266 } else {
1267 cur_state = false;
1268 }
1269
1270 I915_STATE_WARN(cur_state != state,
1271 "pipe %c assertion failure (expected %s, current %s)\n",
1272 pipe_name(pipe), onoff(state), onoff(cur_state));
1273 }
1274
1275 static void assert_plane(struct drm_i915_private *dev_priv,
1276 enum plane plane, bool state)
1277 {
1278 u32 val;
1279 bool cur_state;
1280
1281 val = I915_READ(DSPCNTR(plane));
1282 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1283 I915_STATE_WARN(cur_state != state,
1284 "plane %c assertion failure (expected %s, current %s)\n",
1285 plane_name(plane), onoff(state), onoff(cur_state));
1286 }
1287
1288 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1289 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1290
1291 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293 {
1294 int i;
1295
1296 /* Primary planes are fixed to pipes on gen4+ */
1297 if (INTEL_GEN(dev_priv) >= 4) {
1298 u32 val = I915_READ(DSPCNTR(pipe));
1299 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1300 "plane %c assertion failure, should be disabled but not\n",
1301 plane_name(pipe));
1302 return;
1303 }
1304
1305 /* Need to check both planes against the pipe */
1306 for_each_pipe(dev_priv, i) {
1307 u32 val = I915_READ(DSPCNTR(i));
1308 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1309 DISPPLANE_SEL_PIPE_SHIFT;
1310 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1311 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1312 plane_name(i), pipe_name(pipe));
1313 }
1314 }
1315
1316 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1317 enum pipe pipe)
1318 {
1319 int sprite;
1320
1321 if (INTEL_GEN(dev_priv) >= 9) {
1322 for_each_sprite(dev_priv, pipe, sprite) {
1323 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1324 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1325 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1326 sprite, pipe_name(pipe));
1327 }
1328 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1329 for_each_sprite(dev_priv, pipe, sprite) {
1330 u32 val = I915_READ(SPCNTR(pipe, sprite));
1331 I915_STATE_WARN(val & SP_ENABLE,
1332 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1333 sprite_name(pipe, sprite), pipe_name(pipe));
1334 }
1335 } else if (INTEL_GEN(dev_priv) >= 7) {
1336 u32 val = I915_READ(SPRCTL(pipe));
1337 I915_STATE_WARN(val & SPRITE_ENABLE,
1338 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1339 plane_name(pipe), pipe_name(pipe));
1340 } else if (INTEL_GEN(dev_priv) >= 5) {
1341 u32 val = I915_READ(DVSCNTR(pipe));
1342 I915_STATE_WARN(val & DVS_ENABLE,
1343 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344 plane_name(pipe), pipe_name(pipe));
1345 }
1346 }
1347
1348 static void assert_vblank_disabled(struct drm_crtc *crtc)
1349 {
1350 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1351 drm_crtc_vblank_put(crtc);
1352 }
1353
1354 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1355 enum pipe pipe)
1356 {
1357 u32 val;
1358 bool enabled;
1359
1360 val = I915_READ(PCH_TRANSCONF(pipe));
1361 enabled = !!(val & TRANS_ENABLE);
1362 I915_STATE_WARN(enabled,
1363 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1364 pipe_name(pipe));
1365 }
1366
1367 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1368 enum pipe pipe, u32 port_sel, u32 val)
1369 {
1370 if ((val & DP_PORT_EN) == 0)
1371 return false;
1372
1373 if (HAS_PCH_CPT(dev_priv)) {
1374 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1375 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1376 return false;
1377 } else if (IS_CHERRYVIEW(dev_priv)) {
1378 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1379 return false;
1380 } else {
1381 if ((val & DP_PIPE_MASK) != (pipe << 30))
1382 return false;
1383 }
1384 return true;
1385 }
1386
1387 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1388 enum pipe pipe, u32 val)
1389 {
1390 if ((val & SDVO_ENABLE) == 0)
1391 return false;
1392
1393 if (HAS_PCH_CPT(dev_priv)) {
1394 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1395 return false;
1396 } else if (IS_CHERRYVIEW(dev_priv)) {
1397 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1398 return false;
1399 } else {
1400 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1401 return false;
1402 }
1403 return true;
1404 }
1405
1406 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1407 enum pipe pipe, u32 val)
1408 {
1409 if ((val & LVDS_PORT_EN) == 0)
1410 return false;
1411
1412 if (HAS_PCH_CPT(dev_priv)) {
1413 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1414 return false;
1415 } else {
1416 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1417 return false;
1418 }
1419 return true;
1420 }
1421
1422 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1423 enum pipe pipe, u32 val)
1424 {
1425 if ((val & ADPA_DAC_ENABLE) == 0)
1426 return false;
1427 if (HAS_PCH_CPT(dev_priv)) {
1428 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1429 return false;
1430 } else {
1431 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1432 return false;
1433 }
1434 return true;
1435 }
1436
1437 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1438 enum pipe pipe, i915_reg_t reg,
1439 u32 port_sel)
1440 {
1441 u32 val = I915_READ(reg);
1442 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1443 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1444 i915_mmio_reg_offset(reg), pipe_name(pipe));
1445
1446 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1447 && (val & DP_PIPEB_SELECT),
1448 "IBX PCH dp port still using transcoder B\n");
1449 }
1450
1451 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1452 enum pipe pipe, i915_reg_t reg)
1453 {
1454 u32 val = I915_READ(reg);
1455 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1456 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1457 i915_mmio_reg_offset(reg), pipe_name(pipe));
1458
1459 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1460 && (val & SDVO_PIPE_B_SELECT),
1461 "IBX PCH hdmi port still using transcoder B\n");
1462 }
1463
1464 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1465 enum pipe pipe)
1466 {
1467 u32 val;
1468
1469 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1470 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1471 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1472
1473 val = I915_READ(PCH_ADPA);
1474 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1475 "PCH VGA enabled on transcoder %c, should be disabled\n",
1476 pipe_name(pipe));
1477
1478 val = I915_READ(PCH_LVDS);
1479 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1480 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1481 pipe_name(pipe));
1482
1483 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1484 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1485 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1486 }
1487
1488 static void _vlv_enable_pll(struct intel_crtc *crtc,
1489 const struct intel_crtc_state *pipe_config)
1490 {
1491 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1492 enum pipe pipe = crtc->pipe;
1493
1494 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1495 POSTING_READ(DPLL(pipe));
1496 udelay(150);
1497
1498 if (intel_wait_for_register(dev_priv,
1499 DPLL(pipe),
1500 DPLL_LOCK_VLV,
1501 DPLL_LOCK_VLV,
1502 1))
1503 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1504 }
1505
1506 static void vlv_enable_pll(struct intel_crtc *crtc,
1507 const struct intel_crtc_state *pipe_config)
1508 {
1509 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1510 enum pipe pipe = crtc->pipe;
1511
1512 assert_pipe_disabled(dev_priv, pipe);
1513
1514 /* PLL is protected by panel, make sure we can write it */
1515 assert_panel_unlocked(dev_priv, pipe);
1516
1517 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1518 _vlv_enable_pll(crtc, pipe_config);
1519
1520 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1521 POSTING_READ(DPLL_MD(pipe));
1522 }
1523
1524
1525 static void _chv_enable_pll(struct intel_crtc *crtc,
1526 const struct intel_crtc_state *pipe_config)
1527 {
1528 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1529 enum pipe pipe = crtc->pipe;
1530 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1531 u32 tmp;
1532
1533 mutex_lock(&dev_priv->sb_lock);
1534
1535 /* Enable back the 10bit clock to display controller */
1536 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1537 tmp |= DPIO_DCLKP_EN;
1538 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1539
1540 mutex_unlock(&dev_priv->sb_lock);
1541
1542 /*
1543 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1544 */
1545 udelay(1);
1546
1547 /* Enable PLL */
1548 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1549
1550 /* Check PLL is locked */
1551 if (intel_wait_for_register(dev_priv,
1552 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1553 1))
1554 DRM_ERROR("PLL %d failed to lock\n", pipe);
1555 }
1556
1557 static void chv_enable_pll(struct intel_crtc *crtc,
1558 const struct intel_crtc_state *pipe_config)
1559 {
1560 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1561 enum pipe pipe = crtc->pipe;
1562
1563 assert_pipe_disabled(dev_priv, pipe);
1564
1565 /* PLL is protected by panel, make sure we can write it */
1566 assert_panel_unlocked(dev_priv, pipe);
1567
1568 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1569 _chv_enable_pll(crtc, pipe_config);
1570
1571 if (pipe != PIPE_A) {
1572 /*
1573 * WaPixelRepeatModeFixForC0:chv
1574 *
1575 * DPLLCMD is AWOL. Use chicken bits to propagate
1576 * the value from DPLLBMD to either pipe B or C.
1577 */
1578 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1579 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1580 I915_WRITE(CBR4_VLV, 0);
1581 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1582
1583 /*
1584 * DPLLB VGA mode also seems to cause problems.
1585 * We should always have it disabled.
1586 */
1587 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1588 } else {
1589 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1590 POSTING_READ(DPLL_MD(pipe));
1591 }
1592 }
1593
1594 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1595 {
1596 struct intel_crtc *crtc;
1597 int count = 0;
1598
1599 for_each_intel_crtc(&dev_priv->drm, crtc) {
1600 count += crtc->base.state->active &&
1601 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1602 }
1603
1604 return count;
1605 }
1606
1607 static void i9xx_enable_pll(struct intel_crtc *crtc)
1608 {
1609 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1610 i915_reg_t reg = DPLL(crtc->pipe);
1611 u32 dpll = crtc->config->dpll_hw_state.dpll;
1612
1613 assert_pipe_disabled(dev_priv, crtc->pipe);
1614
1615 /* PLL is protected by panel, make sure we can write it */
1616 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1617 assert_panel_unlocked(dev_priv, crtc->pipe);
1618
1619 /* Enable DVO 2x clock on both PLLs if necessary */
1620 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1621 /*
1622 * It appears to be important that we don't enable this
1623 * for the current pipe before otherwise configuring the
1624 * PLL. No idea how this should be handled if multiple
1625 * DVO outputs are enabled simultaneosly.
1626 */
1627 dpll |= DPLL_DVO_2X_MODE;
1628 I915_WRITE(DPLL(!crtc->pipe),
1629 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1630 }
1631
1632 /*
1633 * Apparently we need to have VGA mode enabled prior to changing
1634 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1635 * dividers, even though the register value does change.
1636 */
1637 I915_WRITE(reg, 0);
1638
1639 I915_WRITE(reg, dpll);
1640
1641 /* Wait for the clocks to stabilize. */
1642 POSTING_READ(reg);
1643 udelay(150);
1644
1645 if (INTEL_GEN(dev_priv) >= 4) {
1646 I915_WRITE(DPLL_MD(crtc->pipe),
1647 crtc->config->dpll_hw_state.dpll_md);
1648 } else {
1649 /* The pixel multiplier can only be updated once the
1650 * DPLL is enabled and the clocks are stable.
1651 *
1652 * So write it again.
1653 */
1654 I915_WRITE(reg, dpll);
1655 }
1656
1657 /* We do this three times for luck */
1658 I915_WRITE(reg, dpll);
1659 POSTING_READ(reg);
1660 udelay(150); /* wait for warmup */
1661 I915_WRITE(reg, dpll);
1662 POSTING_READ(reg);
1663 udelay(150); /* wait for warmup */
1664 I915_WRITE(reg, dpll);
1665 POSTING_READ(reg);
1666 udelay(150); /* wait for warmup */
1667 }
1668
1669 /**
1670 * i9xx_disable_pll - disable a PLL
1671 * @dev_priv: i915 private structure
1672 * @pipe: pipe PLL to disable
1673 *
1674 * Disable the PLL for @pipe, making sure the pipe is off first.
1675 *
1676 * Note! This is for pre-ILK only.
1677 */
1678 static void i9xx_disable_pll(struct intel_crtc *crtc)
1679 {
1680 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1681 enum pipe pipe = crtc->pipe;
1682
1683 /* Disable DVO 2x clock on both PLLs if necessary */
1684 if (IS_I830(dev_priv) &&
1685 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1686 !intel_num_dvo_pipes(dev_priv)) {
1687 I915_WRITE(DPLL(PIPE_B),
1688 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1689 I915_WRITE(DPLL(PIPE_A),
1690 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1691 }
1692
1693 /* Don't disable pipe or pipe PLLs if needed */
1694 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1695 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1696 return;
1697
1698 /* Make sure the pipe isn't still relying on us */
1699 assert_pipe_disabled(dev_priv, pipe);
1700
1701 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1702 POSTING_READ(DPLL(pipe));
1703 }
1704
1705 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1706 {
1707 u32 val;
1708
1709 /* Make sure the pipe isn't still relying on us */
1710 assert_pipe_disabled(dev_priv, pipe);
1711
1712 val = DPLL_INTEGRATED_REF_CLK_VLV |
1713 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1714 if (pipe != PIPE_A)
1715 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1716
1717 I915_WRITE(DPLL(pipe), val);
1718 POSTING_READ(DPLL(pipe));
1719 }
1720
1721 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1722 {
1723 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1724 u32 val;
1725
1726 /* Make sure the pipe isn't still relying on us */
1727 assert_pipe_disabled(dev_priv, pipe);
1728
1729 val = DPLL_SSC_REF_CLK_CHV |
1730 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1731 if (pipe != PIPE_A)
1732 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1733
1734 I915_WRITE(DPLL(pipe), val);
1735 POSTING_READ(DPLL(pipe));
1736
1737 mutex_lock(&dev_priv->sb_lock);
1738
1739 /* Disable 10bit clock to display controller */
1740 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1741 val &= ~DPIO_DCLKP_EN;
1742 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1743
1744 mutex_unlock(&dev_priv->sb_lock);
1745 }
1746
1747 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1748 struct intel_digital_port *dport,
1749 unsigned int expected_mask)
1750 {
1751 u32 port_mask;
1752 i915_reg_t dpll_reg;
1753
1754 switch (dport->port) {
1755 case PORT_B:
1756 port_mask = DPLL_PORTB_READY_MASK;
1757 dpll_reg = DPLL(0);
1758 break;
1759 case PORT_C:
1760 port_mask = DPLL_PORTC_READY_MASK;
1761 dpll_reg = DPLL(0);
1762 expected_mask <<= 4;
1763 break;
1764 case PORT_D:
1765 port_mask = DPLL_PORTD_READY_MASK;
1766 dpll_reg = DPIO_PHY_STATUS;
1767 break;
1768 default:
1769 BUG();
1770 }
1771
1772 if (intel_wait_for_register(dev_priv,
1773 dpll_reg, port_mask, expected_mask,
1774 1000))
1775 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1776 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1777 }
1778
1779 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1780 enum pipe pipe)
1781 {
1782 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1783 pipe);
1784 i915_reg_t reg;
1785 uint32_t val, pipeconf_val;
1786
1787 /* Make sure PCH DPLL is enabled */
1788 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1789
1790 /* FDI must be feeding us bits for PCH ports */
1791 assert_fdi_tx_enabled(dev_priv, pipe);
1792 assert_fdi_rx_enabled(dev_priv, pipe);
1793
1794 if (HAS_PCH_CPT(dev_priv)) {
1795 /* Workaround: Set the timing override bit before enabling the
1796 * pch transcoder. */
1797 reg = TRANS_CHICKEN2(pipe);
1798 val = I915_READ(reg);
1799 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1800 I915_WRITE(reg, val);
1801 }
1802
1803 reg = PCH_TRANSCONF(pipe);
1804 val = I915_READ(reg);
1805 pipeconf_val = I915_READ(PIPECONF(pipe));
1806
1807 if (HAS_PCH_IBX(dev_priv)) {
1808 /*
1809 * Make the BPC in transcoder be consistent with
1810 * that in pipeconf reg. For HDMI we must use 8bpc
1811 * here for both 8bpc and 12bpc.
1812 */
1813 val &= ~PIPECONF_BPC_MASK;
1814 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1815 val |= PIPECONF_8BPC;
1816 else
1817 val |= pipeconf_val & PIPECONF_BPC_MASK;
1818 }
1819
1820 val &= ~TRANS_INTERLACE_MASK;
1821 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1822 if (HAS_PCH_IBX(dev_priv) &&
1823 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1824 val |= TRANS_LEGACY_INTERLACED_ILK;
1825 else
1826 val |= TRANS_INTERLACED;
1827 else
1828 val |= TRANS_PROGRESSIVE;
1829
1830 I915_WRITE(reg, val | TRANS_ENABLE);
1831 if (intel_wait_for_register(dev_priv,
1832 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1833 100))
1834 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1835 }
1836
1837 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1838 enum transcoder cpu_transcoder)
1839 {
1840 u32 val, pipeconf_val;
1841
1842 /* FDI must be feeding us bits for PCH ports */
1843 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1844 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1845
1846 /* Workaround: set timing override bit. */
1847 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1848 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1849 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1850
1851 val = TRANS_ENABLE;
1852 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1853
1854 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1855 PIPECONF_INTERLACED_ILK)
1856 val |= TRANS_INTERLACED;
1857 else
1858 val |= TRANS_PROGRESSIVE;
1859
1860 I915_WRITE(LPT_TRANSCONF, val);
1861 if (intel_wait_for_register(dev_priv,
1862 LPT_TRANSCONF,
1863 TRANS_STATE_ENABLE,
1864 TRANS_STATE_ENABLE,
1865 100))
1866 DRM_ERROR("Failed to enable PCH transcoder\n");
1867 }
1868
1869 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1870 enum pipe pipe)
1871 {
1872 i915_reg_t reg;
1873 uint32_t val;
1874
1875 /* FDI relies on the transcoder */
1876 assert_fdi_tx_disabled(dev_priv, pipe);
1877 assert_fdi_rx_disabled(dev_priv, pipe);
1878
1879 /* Ports must be off as well */
1880 assert_pch_ports_disabled(dev_priv, pipe);
1881
1882 reg = PCH_TRANSCONF(pipe);
1883 val = I915_READ(reg);
1884 val &= ~TRANS_ENABLE;
1885 I915_WRITE(reg, val);
1886 /* wait for PCH transcoder off, transcoder state */
1887 if (intel_wait_for_register(dev_priv,
1888 reg, TRANS_STATE_ENABLE, 0,
1889 50))
1890 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1891
1892 if (HAS_PCH_CPT(dev_priv)) {
1893 /* Workaround: Clear the timing override chicken bit again. */
1894 reg = TRANS_CHICKEN2(pipe);
1895 val = I915_READ(reg);
1896 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1897 I915_WRITE(reg, val);
1898 }
1899 }
1900
1901 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1902 {
1903 u32 val;
1904
1905 val = I915_READ(LPT_TRANSCONF);
1906 val &= ~TRANS_ENABLE;
1907 I915_WRITE(LPT_TRANSCONF, val);
1908 /* wait for PCH transcoder off, transcoder state */
1909 if (intel_wait_for_register(dev_priv,
1910 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1911 50))
1912 DRM_ERROR("Failed to disable PCH transcoder\n");
1913
1914 /* Workaround: clear timing override bit. */
1915 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1916 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1917 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1918 }
1919
1920 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1921 {
1922 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1923
1924 WARN_ON(!crtc->config->has_pch_encoder);
1925
1926 if (HAS_PCH_LPT(dev_priv))
1927 return TRANSCODER_A;
1928 else
1929 return (enum transcoder) crtc->pipe;
1930 }
1931
1932 /**
1933 * intel_enable_pipe - enable a pipe, asserting requirements
1934 * @crtc: crtc responsible for the pipe
1935 *
1936 * Enable @crtc's pipe, making sure that various hardware specific requirements
1937 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1938 */
1939 static void intel_enable_pipe(struct intel_crtc *crtc)
1940 {
1941 struct drm_device *dev = crtc->base.dev;
1942 struct drm_i915_private *dev_priv = to_i915(dev);
1943 enum pipe pipe = crtc->pipe;
1944 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1945 i915_reg_t reg;
1946 u32 val;
1947
1948 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1949
1950 assert_planes_disabled(dev_priv, pipe);
1951 assert_cursor_disabled(dev_priv, pipe);
1952 assert_sprites_disabled(dev_priv, pipe);
1953
1954 /*
1955 * A pipe without a PLL won't actually be able to drive bits from
1956 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1957 * need the check.
1958 */
1959 if (HAS_GMCH_DISPLAY(dev_priv)) {
1960 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1961 assert_dsi_pll_enabled(dev_priv);
1962 else
1963 assert_pll_enabled(dev_priv, pipe);
1964 } else {
1965 if (crtc->config->has_pch_encoder) {
1966 /* if driving the PCH, we need FDI enabled */
1967 assert_fdi_rx_pll_enabled(dev_priv,
1968 (enum pipe) intel_crtc_pch_transcoder(crtc));
1969 assert_fdi_tx_pll_enabled(dev_priv,
1970 (enum pipe) cpu_transcoder);
1971 }
1972 /* FIXME: assert CPU port conditions for SNB+ */
1973 }
1974
1975 reg = PIPECONF(cpu_transcoder);
1976 val = I915_READ(reg);
1977 if (val & PIPECONF_ENABLE) {
1978 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1979 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1980 return;
1981 }
1982
1983 I915_WRITE(reg, val | PIPECONF_ENABLE);
1984 POSTING_READ(reg);
1985
1986 /*
1987 * Until the pipe starts DSL will read as 0, which would cause
1988 * an apparent vblank timestamp jump, which messes up also the
1989 * frame count when it's derived from the timestamps. So let's
1990 * wait for the pipe to start properly before we call
1991 * drm_crtc_vblank_on()
1992 */
1993 if (dev->max_vblank_count == 0 &&
1994 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1995 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1996 }
1997
1998 /**
1999 * intel_disable_pipe - disable a pipe, asserting requirements
2000 * @crtc: crtc whose pipes is to be disabled
2001 *
2002 * Disable the pipe of @crtc, making sure that various hardware
2003 * specific requirements are met, if applicable, e.g. plane
2004 * disabled, panel fitter off, etc.
2005 *
2006 * Will wait until the pipe has shut down before returning.
2007 */
2008 static void intel_disable_pipe(struct intel_crtc *crtc)
2009 {
2010 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2011 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2012 enum pipe pipe = crtc->pipe;
2013 i915_reg_t reg;
2014 u32 val;
2015
2016 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2017
2018 /*
2019 * Make sure planes won't keep trying to pump pixels to us,
2020 * or we might hang the display.
2021 */
2022 assert_planes_disabled(dev_priv, pipe);
2023 assert_cursor_disabled(dev_priv, pipe);
2024 assert_sprites_disabled(dev_priv, pipe);
2025
2026 reg = PIPECONF(cpu_transcoder);
2027 val = I915_READ(reg);
2028 if ((val & PIPECONF_ENABLE) == 0)
2029 return;
2030
2031 /*
2032 * Double wide has implications for planes
2033 * so best keep it disabled when not needed.
2034 */
2035 if (crtc->config->double_wide)
2036 val &= ~PIPECONF_DOUBLE_WIDE;
2037
2038 /* Don't disable pipe or pipe PLLs if needed */
2039 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2040 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2041 val &= ~PIPECONF_ENABLE;
2042
2043 I915_WRITE(reg, val);
2044 if ((val & PIPECONF_ENABLE) == 0)
2045 intel_wait_for_pipe_off(crtc);
2046 }
2047
2048 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2049 {
2050 return IS_GEN2(dev_priv) ? 2048 : 4096;
2051 }
2052
2053 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2054 uint64_t fb_modifier, unsigned int cpp)
2055 {
2056 switch (fb_modifier) {
2057 case DRM_FORMAT_MOD_NONE:
2058 return cpp;
2059 case I915_FORMAT_MOD_X_TILED:
2060 if (IS_GEN2(dev_priv))
2061 return 128;
2062 else
2063 return 512;
2064 case I915_FORMAT_MOD_Y_TILED:
2065 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2066 return 128;
2067 else
2068 return 512;
2069 case I915_FORMAT_MOD_Yf_TILED:
2070 switch (cpp) {
2071 case 1:
2072 return 64;
2073 case 2:
2074 case 4:
2075 return 128;
2076 case 8:
2077 case 16:
2078 return 256;
2079 default:
2080 MISSING_CASE(cpp);
2081 return cpp;
2082 }
2083 break;
2084 default:
2085 MISSING_CASE(fb_modifier);
2086 return cpp;
2087 }
2088 }
2089
2090 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2091 uint64_t fb_modifier, unsigned int cpp)
2092 {
2093 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2094 return 1;
2095 else
2096 return intel_tile_size(dev_priv) /
2097 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2098 }
2099
2100 /* Return the tile dimensions in pixel units */
2101 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2102 unsigned int *tile_width,
2103 unsigned int *tile_height,
2104 uint64_t fb_modifier,
2105 unsigned int cpp)
2106 {
2107 unsigned int tile_width_bytes =
2108 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2109
2110 *tile_width = tile_width_bytes / cpp;
2111 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2112 }
2113
2114 unsigned int
2115 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2116 uint32_t pixel_format, uint64_t fb_modifier)
2117 {
2118 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2119 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2120
2121 return ALIGN(height, tile_height);
2122 }
2123
2124 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2125 {
2126 unsigned int size = 0;
2127 int i;
2128
2129 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2130 size += rot_info->plane[i].width * rot_info->plane[i].height;
2131
2132 return size;
2133 }
2134
2135 static void
2136 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2137 const struct drm_framebuffer *fb,
2138 unsigned int rotation)
2139 {
2140 if (drm_rotation_90_or_270(rotation)) {
2141 *view = i915_ggtt_view_rotated;
2142 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2143 } else {
2144 *view = i915_ggtt_view_normal;
2145 }
2146 }
2147
2148 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2149 {
2150 if (INTEL_INFO(dev_priv)->gen >= 9)
2151 return 256 * 1024;
2152 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2153 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2154 return 128 * 1024;
2155 else if (INTEL_INFO(dev_priv)->gen >= 4)
2156 return 4 * 1024;
2157 else
2158 return 0;
2159 }
2160
2161 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2162 uint64_t fb_modifier)
2163 {
2164 switch (fb_modifier) {
2165 case DRM_FORMAT_MOD_NONE:
2166 return intel_linear_alignment(dev_priv);
2167 case I915_FORMAT_MOD_X_TILED:
2168 if (INTEL_INFO(dev_priv)->gen >= 9)
2169 return 256 * 1024;
2170 return 0;
2171 case I915_FORMAT_MOD_Y_TILED:
2172 case I915_FORMAT_MOD_Yf_TILED:
2173 return 1 * 1024 * 1024;
2174 default:
2175 MISSING_CASE(fb_modifier);
2176 return 0;
2177 }
2178 }
2179
2180 struct i915_vma *
2181 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2182 {
2183 struct drm_device *dev = fb->dev;
2184 struct drm_i915_private *dev_priv = to_i915(dev);
2185 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2186 struct i915_ggtt_view view;
2187 struct i915_vma *vma;
2188 u32 alignment;
2189
2190 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2191
2192 alignment = intel_surf_alignment(dev_priv, fb->modifier);
2193
2194 intel_fill_fb_ggtt_view(&view, fb, rotation);
2195
2196 /* Note that the w/a also requires 64 PTE of padding following the
2197 * bo. We currently fill all unused PTE with the shadow page and so
2198 * we should always have valid PTE following the scanout preventing
2199 * the VT-d warning.
2200 */
2201 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2202 alignment = 256 * 1024;
2203
2204 /*
2205 * Global gtt pte registers are special registers which actually forward
2206 * writes to a chunk of system memory. Which means that there is no risk
2207 * that the register values disappear as soon as we call
2208 * intel_runtime_pm_put(), so it is correct to wrap only the
2209 * pin/unpin/fence and not more.
2210 */
2211 intel_runtime_pm_get(dev_priv);
2212
2213 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2214 if (IS_ERR(vma))
2215 goto err;
2216
2217 if (i915_vma_is_map_and_fenceable(vma)) {
2218 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2219 * fence, whereas 965+ only requires a fence if using
2220 * framebuffer compression. For simplicity, we always, when
2221 * possible, install a fence as the cost is not that onerous.
2222 *
2223 * If we fail to fence the tiled scanout, then either the
2224 * modeset will reject the change (which is highly unlikely as
2225 * the affected systems, all but one, do not have unmappable
2226 * space) or we will not be able to enable full powersaving
2227 * techniques (also likely not to apply due to various limits
2228 * FBC and the like impose on the size of the buffer, which
2229 * presumably we violated anyway with this unmappable buffer).
2230 * Anyway, it is presumably better to stumble onwards with
2231 * something and try to run the system in a "less than optimal"
2232 * mode that matches the user configuration.
2233 */
2234 if (i915_vma_get_fence(vma) == 0)
2235 i915_vma_pin_fence(vma);
2236 }
2237
2238 err:
2239 intel_runtime_pm_put(dev_priv);
2240 return vma;
2241 }
2242
2243 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2244 {
2245 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2246 struct i915_ggtt_view view;
2247 struct i915_vma *vma;
2248
2249 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2250
2251 intel_fill_fb_ggtt_view(&view, fb, rotation);
2252 vma = i915_gem_object_to_ggtt(obj, &view);
2253
2254 if (WARN_ON_ONCE(!vma))
2255 return;
2256
2257 i915_vma_unpin_fence(vma);
2258 i915_gem_object_unpin_from_display_plane(vma);
2259 }
2260
2261 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2262 unsigned int rotation)
2263 {
2264 if (drm_rotation_90_or_270(rotation))
2265 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2266 else
2267 return fb->pitches[plane];
2268 }
2269
2270 /*
2271 * Convert the x/y offsets into a linear offset.
2272 * Only valid with 0/180 degree rotation, which is fine since linear
2273 * offset is only used with linear buffers on pre-hsw and tiled buffers
2274 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2275 */
2276 u32 intel_fb_xy_to_linear(int x, int y,
2277 const struct intel_plane_state *state,
2278 int plane)
2279 {
2280 const struct drm_framebuffer *fb = state->base.fb;
2281 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2282 unsigned int pitch = fb->pitches[plane];
2283
2284 return y * pitch + x * cpp;
2285 }
2286
2287 /*
2288 * Add the x/y offsets derived from fb->offsets[] to the user
2289 * specified plane src x/y offsets. The resulting x/y offsets
2290 * specify the start of scanout from the beginning of the gtt mapping.
2291 */
2292 void intel_add_fb_offsets(int *x, int *y,
2293 const struct intel_plane_state *state,
2294 int plane)
2295
2296 {
2297 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2298 unsigned int rotation = state->base.rotation;
2299
2300 if (drm_rotation_90_or_270(rotation)) {
2301 *x += intel_fb->rotated[plane].x;
2302 *y += intel_fb->rotated[plane].y;
2303 } else {
2304 *x += intel_fb->normal[plane].x;
2305 *y += intel_fb->normal[plane].y;
2306 }
2307 }
2308
2309 /*
2310 * Input tile dimensions and pitch must already be
2311 * rotated to match x and y, and in pixel units.
2312 */
2313 static u32 _intel_adjust_tile_offset(int *x, int *y,
2314 unsigned int tile_width,
2315 unsigned int tile_height,
2316 unsigned int tile_size,
2317 unsigned int pitch_tiles,
2318 u32 old_offset,
2319 u32 new_offset)
2320 {
2321 unsigned int pitch_pixels = pitch_tiles * tile_width;
2322 unsigned int tiles;
2323
2324 WARN_ON(old_offset & (tile_size - 1));
2325 WARN_ON(new_offset & (tile_size - 1));
2326 WARN_ON(new_offset > old_offset);
2327
2328 tiles = (old_offset - new_offset) / tile_size;
2329
2330 *y += tiles / pitch_tiles * tile_height;
2331 *x += tiles % pitch_tiles * tile_width;
2332
2333 /* minimize x in case it got needlessly big */
2334 *y += *x / pitch_pixels * tile_height;
2335 *x %= pitch_pixels;
2336
2337 return new_offset;
2338 }
2339
2340 /*
2341 * Adjust the tile offset by moving the difference into
2342 * the x/y offsets.
2343 */
2344 static u32 intel_adjust_tile_offset(int *x, int *y,
2345 const struct intel_plane_state *state, int plane,
2346 u32 old_offset, u32 new_offset)
2347 {
2348 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2349 const struct drm_framebuffer *fb = state->base.fb;
2350 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2351 unsigned int rotation = state->base.rotation;
2352 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2353
2354 WARN_ON(new_offset > old_offset);
2355
2356 if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2357 unsigned int tile_size, tile_width, tile_height;
2358 unsigned int pitch_tiles;
2359
2360 tile_size = intel_tile_size(dev_priv);
2361 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2362 fb->modifier, cpp);
2363
2364 if (drm_rotation_90_or_270(rotation)) {
2365 pitch_tiles = pitch / tile_height;
2366 swap(tile_width, tile_height);
2367 } else {
2368 pitch_tiles = pitch / (tile_width * cpp);
2369 }
2370
2371 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2372 tile_size, pitch_tiles,
2373 old_offset, new_offset);
2374 } else {
2375 old_offset += *y * pitch + *x * cpp;
2376
2377 *y = (old_offset - new_offset) / pitch;
2378 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2379 }
2380
2381 return new_offset;
2382 }
2383
2384 /*
2385 * Computes the linear offset to the base tile and adjusts
2386 * x, y. bytes per pixel is assumed to be a power-of-two.
2387 *
2388 * In the 90/270 rotated case, x and y are assumed
2389 * to be already rotated to match the rotated GTT view, and
2390 * pitch is the tile_height aligned framebuffer height.
2391 *
2392 * This function is used when computing the derived information
2393 * under intel_framebuffer, so using any of that information
2394 * here is not allowed. Anything under drm_framebuffer can be
2395 * used. This is why the user has to pass in the pitch since it
2396 * is specified in the rotated orientation.
2397 */
2398 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2399 int *x, int *y,
2400 const struct drm_framebuffer *fb, int plane,
2401 unsigned int pitch,
2402 unsigned int rotation,
2403 u32 alignment)
2404 {
2405 uint64_t fb_modifier = fb->modifier;
2406 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2407 u32 offset, offset_aligned;
2408
2409 if (alignment)
2410 alignment--;
2411
2412 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2413 unsigned int tile_size, tile_width, tile_height;
2414 unsigned int tile_rows, tiles, pitch_tiles;
2415
2416 tile_size = intel_tile_size(dev_priv);
2417 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2418 fb_modifier, cpp);
2419
2420 if (drm_rotation_90_or_270(rotation)) {
2421 pitch_tiles = pitch / tile_height;
2422 swap(tile_width, tile_height);
2423 } else {
2424 pitch_tiles = pitch / (tile_width * cpp);
2425 }
2426
2427 tile_rows = *y / tile_height;
2428 *y %= tile_height;
2429
2430 tiles = *x / tile_width;
2431 *x %= tile_width;
2432
2433 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2434 offset_aligned = offset & ~alignment;
2435
2436 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2437 tile_size, pitch_tiles,
2438 offset, offset_aligned);
2439 } else {
2440 offset = *y * pitch + *x * cpp;
2441 offset_aligned = offset & ~alignment;
2442
2443 *y = (offset & alignment) / pitch;
2444 *x = ((offset & alignment) - *y * pitch) / cpp;
2445 }
2446
2447 return offset_aligned;
2448 }
2449
2450 u32 intel_compute_tile_offset(int *x, int *y,
2451 const struct intel_plane_state *state,
2452 int plane)
2453 {
2454 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2455 const struct drm_framebuffer *fb = state->base.fb;
2456 unsigned int rotation = state->base.rotation;
2457 int pitch = intel_fb_pitch(fb, plane, rotation);
2458 u32 alignment;
2459
2460 /* AUX_DIST needs only 4K alignment */
2461 if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1)
2462 alignment = 4096;
2463 else
2464 alignment = intel_surf_alignment(dev_priv, fb->modifier);
2465
2466 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2467 rotation, alignment);
2468 }
2469
2470 /* Convert the fb->offset[] linear offset into x/y offsets */
2471 static void intel_fb_offset_to_xy(int *x, int *y,
2472 const struct drm_framebuffer *fb, int plane)
2473 {
2474 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2475 unsigned int pitch = fb->pitches[plane];
2476 u32 linear_offset = fb->offsets[plane];
2477
2478 *y = linear_offset / pitch;
2479 *x = linear_offset % pitch / cpp;
2480 }
2481
2482 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2483 {
2484 switch (fb_modifier) {
2485 case I915_FORMAT_MOD_X_TILED:
2486 return I915_TILING_X;
2487 case I915_FORMAT_MOD_Y_TILED:
2488 return I915_TILING_Y;
2489 default:
2490 return I915_TILING_NONE;
2491 }
2492 }
2493
2494 static int
2495 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2496 struct drm_framebuffer *fb)
2497 {
2498 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2499 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2500 u32 gtt_offset_rotated = 0;
2501 unsigned int max_size = 0;
2502 uint32_t format = fb->pixel_format;
2503 int i, num_planes = drm_format_num_planes(format);
2504 unsigned int tile_size = intel_tile_size(dev_priv);
2505
2506 for (i = 0; i < num_planes; i++) {
2507 unsigned int width, height;
2508 unsigned int cpp, size;
2509 u32 offset;
2510 int x, y;
2511
2512 cpp = drm_format_plane_cpp(format, i);
2513 width = drm_format_plane_width(fb->width, format, i);
2514 height = drm_format_plane_height(fb->height, format, i);
2515
2516 intel_fb_offset_to_xy(&x, &y, fb, i);
2517
2518 /*
2519 * The fence (if used) is aligned to the start of the object
2520 * so having the framebuffer wrap around across the edge of the
2521 * fenced region doesn't really work. We have no API to configure
2522 * the fence start offset within the object (nor could we probably
2523 * on gen2/3). So it's just easier if we just require that the
2524 * fb layout agrees with the fence layout. We already check that the
2525 * fb stride matches the fence stride elsewhere.
2526 */
2527 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2528 (x + width) * cpp > fb->pitches[i]) {
2529 DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2530 i, fb->offsets[i]);
2531 return -EINVAL;
2532 }
2533
2534 /*
2535 * First pixel of the framebuffer from
2536 * the start of the normal gtt mapping.
2537 */
2538 intel_fb->normal[i].x = x;
2539 intel_fb->normal[i].y = y;
2540
2541 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2542 fb, 0, fb->pitches[i],
2543 DRM_ROTATE_0, tile_size);
2544 offset /= tile_size;
2545
2546 if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2547 unsigned int tile_width, tile_height;
2548 unsigned int pitch_tiles;
2549 struct drm_rect r;
2550
2551 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2552 fb->modifier, cpp);
2553
2554 rot_info->plane[i].offset = offset;
2555 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2556 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2557 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2558
2559 intel_fb->rotated[i].pitch =
2560 rot_info->plane[i].height * tile_height;
2561
2562 /* how many tiles does this plane need */
2563 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2564 /*
2565 * If the plane isn't horizontally tile aligned,
2566 * we need one more tile.
2567 */
2568 if (x != 0)
2569 size++;
2570
2571 /* rotate the x/y offsets to match the GTT view */
2572 r.x1 = x;
2573 r.y1 = y;
2574 r.x2 = x + width;
2575 r.y2 = y + height;
2576 drm_rect_rotate(&r,
2577 rot_info->plane[i].width * tile_width,
2578 rot_info->plane[i].height * tile_height,
2579 DRM_ROTATE_270);
2580 x = r.x1;
2581 y = r.y1;
2582
2583 /* rotate the tile dimensions to match the GTT view */
2584 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2585 swap(tile_width, tile_height);
2586
2587 /*
2588 * We only keep the x/y offsets, so push all of the
2589 * gtt offset into the x/y offsets.
2590 */
2591 _intel_adjust_tile_offset(&x, &y,
2592 tile_width, tile_height,
2593 tile_size, pitch_tiles,
2594 gtt_offset_rotated * tile_size, 0);
2595
2596 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2597
2598 /*
2599 * First pixel of the framebuffer from
2600 * the start of the rotated gtt mapping.
2601 */
2602 intel_fb->rotated[i].x = x;
2603 intel_fb->rotated[i].y = y;
2604 } else {
2605 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2606 x * cpp, tile_size);
2607 }
2608
2609 /* how many tiles in total needed in the bo */
2610 max_size = max(max_size, offset + size);
2611 }
2612
2613 if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2614 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2615 max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2616 return -EINVAL;
2617 }
2618
2619 return 0;
2620 }
2621
2622 static int i9xx_format_to_fourcc(int format)
2623 {
2624 switch (format) {
2625 case DISPPLANE_8BPP:
2626 return DRM_FORMAT_C8;
2627 case DISPPLANE_BGRX555:
2628 return DRM_FORMAT_XRGB1555;
2629 case DISPPLANE_BGRX565:
2630 return DRM_FORMAT_RGB565;
2631 default:
2632 case DISPPLANE_BGRX888:
2633 return DRM_FORMAT_XRGB8888;
2634 case DISPPLANE_RGBX888:
2635 return DRM_FORMAT_XBGR8888;
2636 case DISPPLANE_BGRX101010:
2637 return DRM_FORMAT_XRGB2101010;
2638 case DISPPLANE_RGBX101010:
2639 return DRM_FORMAT_XBGR2101010;
2640 }
2641 }
2642
2643 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2644 {
2645 switch (format) {
2646 case PLANE_CTL_FORMAT_RGB_565:
2647 return DRM_FORMAT_RGB565;
2648 default:
2649 case PLANE_CTL_FORMAT_XRGB_8888:
2650 if (rgb_order) {
2651 if (alpha)
2652 return DRM_FORMAT_ABGR8888;
2653 else
2654 return DRM_FORMAT_XBGR8888;
2655 } else {
2656 if (alpha)
2657 return DRM_FORMAT_ARGB8888;
2658 else
2659 return DRM_FORMAT_XRGB8888;
2660 }
2661 case PLANE_CTL_FORMAT_XRGB_2101010:
2662 if (rgb_order)
2663 return DRM_FORMAT_XBGR2101010;
2664 else
2665 return DRM_FORMAT_XRGB2101010;
2666 }
2667 }
2668
2669 static bool
2670 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2671 struct intel_initial_plane_config *plane_config)
2672 {
2673 struct drm_device *dev = crtc->base.dev;
2674 struct drm_i915_private *dev_priv = to_i915(dev);
2675 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2676 struct drm_i915_gem_object *obj = NULL;
2677 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2678 struct drm_framebuffer *fb = &plane_config->fb->base;
2679 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2680 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2681 PAGE_SIZE);
2682
2683 size_aligned -= base_aligned;
2684
2685 if (plane_config->size == 0)
2686 return false;
2687
2688 /* If the FB is too big, just don't use it since fbdev is not very
2689 * important and we should probably use that space with FBC or other
2690 * features. */
2691 if (size_aligned * 2 > ggtt->stolen_usable_size)
2692 return false;
2693
2694 mutex_lock(&dev->struct_mutex);
2695
2696 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2697 base_aligned,
2698 base_aligned,
2699 size_aligned);
2700 if (!obj) {
2701 mutex_unlock(&dev->struct_mutex);
2702 return false;
2703 }
2704
2705 if (plane_config->tiling == I915_TILING_X)
2706 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2707
2708 mode_cmd.pixel_format = fb->pixel_format;
2709 mode_cmd.width = fb->width;
2710 mode_cmd.height = fb->height;
2711 mode_cmd.pitches[0] = fb->pitches[0];
2712 mode_cmd.modifier[0] = fb->modifier;
2713 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2714
2715 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2716 &mode_cmd, obj)) {
2717 DRM_DEBUG_KMS("intel fb init failed\n");
2718 goto out_unref_obj;
2719 }
2720
2721 mutex_unlock(&dev->struct_mutex);
2722
2723 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2724 return true;
2725
2726 out_unref_obj:
2727 i915_gem_object_put(obj);
2728 mutex_unlock(&dev->struct_mutex);
2729 return false;
2730 }
2731
2732 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2733 static void
2734 update_state_fb(struct drm_plane *plane)
2735 {
2736 if (plane->fb == plane->state->fb)
2737 return;
2738
2739 if (plane->state->fb)
2740 drm_framebuffer_unreference(plane->state->fb);
2741 plane->state->fb = plane->fb;
2742 if (plane->state->fb)
2743 drm_framebuffer_reference(plane->state->fb);
2744 }
2745
2746 static void
2747 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2748 struct intel_initial_plane_config *plane_config)
2749 {
2750 struct drm_device *dev = intel_crtc->base.dev;
2751 struct drm_i915_private *dev_priv = to_i915(dev);
2752 struct drm_crtc *c;
2753 struct intel_crtc *i;
2754 struct drm_i915_gem_object *obj;
2755 struct drm_plane *primary = intel_crtc->base.primary;
2756 struct drm_plane_state *plane_state = primary->state;
2757 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2758 struct intel_plane *intel_plane = to_intel_plane(primary);
2759 struct intel_plane_state *intel_state =
2760 to_intel_plane_state(plane_state);
2761 struct drm_framebuffer *fb;
2762
2763 if (!plane_config->fb)
2764 return;
2765
2766 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2767 fb = &plane_config->fb->base;
2768 goto valid_fb;
2769 }
2770
2771 kfree(plane_config->fb);
2772
2773 /*
2774 * Failed to alloc the obj, check to see if we should share
2775 * an fb with another CRTC instead
2776 */
2777 for_each_crtc(dev, c) {
2778 i = to_intel_crtc(c);
2779
2780 if (c == &intel_crtc->base)
2781 continue;
2782
2783 if (!i->active)
2784 continue;
2785
2786 fb = c->primary->fb;
2787 if (!fb)
2788 continue;
2789
2790 obj = intel_fb_obj(fb);
2791 if (i915_gem_object_ggtt_offset(obj, NULL) == plane_config->base) {
2792 drm_framebuffer_reference(fb);
2793 goto valid_fb;
2794 }
2795 }
2796
2797 /*
2798 * We've failed to reconstruct the BIOS FB. Current display state
2799 * indicates that the primary plane is visible, but has a NULL FB,
2800 * which will lead to problems later if we don't fix it up. The
2801 * simplest solution is to just disable the primary plane now and
2802 * pretend the BIOS never had it enabled.
2803 */
2804 to_intel_plane_state(plane_state)->base.visible = false;
2805 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2806 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2807 intel_plane->disable_plane(primary, &intel_crtc->base);
2808
2809 return;
2810
2811 valid_fb:
2812 plane_state->src_x = 0;
2813 plane_state->src_y = 0;
2814 plane_state->src_w = fb->width << 16;
2815 plane_state->src_h = fb->height << 16;
2816
2817 plane_state->crtc_x = 0;
2818 plane_state->crtc_y = 0;
2819 plane_state->crtc_w = fb->width;
2820 plane_state->crtc_h = fb->height;
2821
2822 intel_state->base.src = drm_plane_state_src(plane_state);
2823 intel_state->base.dst = drm_plane_state_dest(plane_state);
2824
2825 obj = intel_fb_obj(fb);
2826 if (i915_gem_object_is_tiled(obj))
2827 dev_priv->preserve_bios_swizzle = true;
2828
2829 drm_framebuffer_reference(fb);
2830 primary->fb = primary->state->fb = fb;
2831 primary->crtc = primary->state->crtc = &intel_crtc->base;
2832 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2833 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2834 &obj->frontbuffer_bits);
2835 }
2836
2837 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2838 unsigned int rotation)
2839 {
2840 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2841
2842 switch (fb->modifier) {
2843 case DRM_FORMAT_MOD_NONE:
2844 case I915_FORMAT_MOD_X_TILED:
2845 switch (cpp) {
2846 case 8:
2847 return 4096;
2848 case 4:
2849 case 2:
2850 case 1:
2851 return 8192;
2852 default:
2853 MISSING_CASE(cpp);
2854 break;
2855 }
2856 break;
2857 case I915_FORMAT_MOD_Y_TILED:
2858 case I915_FORMAT_MOD_Yf_TILED:
2859 switch (cpp) {
2860 case 8:
2861 return 2048;
2862 case 4:
2863 return 4096;
2864 case 2:
2865 case 1:
2866 return 8192;
2867 default:
2868 MISSING_CASE(cpp);
2869 break;
2870 }
2871 break;
2872 default:
2873 MISSING_CASE(fb->modifier);
2874 }
2875
2876 return 2048;
2877 }
2878
2879 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2880 {
2881 const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2882 const struct drm_framebuffer *fb = plane_state->base.fb;
2883 unsigned int rotation = plane_state->base.rotation;
2884 int x = plane_state->base.src.x1 >> 16;
2885 int y = plane_state->base.src.y1 >> 16;
2886 int w = drm_rect_width(&plane_state->base.src) >> 16;
2887 int h = drm_rect_height(&plane_state->base.src) >> 16;
2888 int max_width = skl_max_plane_width(fb, 0, rotation);
2889 int max_height = 4096;
2890 u32 alignment, offset, aux_offset = plane_state->aux.offset;
2891
2892 if (w > max_width || h > max_height) {
2893 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2894 w, h, max_width, max_height);
2895 return -EINVAL;
2896 }
2897
2898 intel_add_fb_offsets(&x, &y, plane_state, 0);
2899 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2900
2901 alignment = intel_surf_alignment(dev_priv, fb->modifier);
2902
2903 /*
2904 * AUX surface offset is specified as the distance from the
2905 * main surface offset, and it must be non-negative. Make
2906 * sure that is what we will get.
2907 */
2908 if (offset > aux_offset)
2909 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2910 offset, aux_offset & ~(alignment - 1));
2911
2912 /*
2913 * When using an X-tiled surface, the plane blows up
2914 * if the x offset + width exceed the stride.
2915 *
2916 * TODO: linear and Y-tiled seem fine, Yf untested,
2917 */
2918 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2919 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2920
2921 while ((x + w) * cpp > fb->pitches[0]) {
2922 if (offset == 0) {
2923 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2924 return -EINVAL;
2925 }
2926
2927 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2928 offset, offset - alignment);
2929 }
2930 }
2931
2932 plane_state->main.offset = offset;
2933 plane_state->main.x = x;
2934 plane_state->main.y = y;
2935
2936 return 0;
2937 }
2938
2939 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2940 {
2941 const struct drm_framebuffer *fb = plane_state->base.fb;
2942 unsigned int rotation = plane_state->base.rotation;
2943 int max_width = skl_max_plane_width(fb, 1, rotation);
2944 int max_height = 4096;
2945 int x = plane_state->base.src.x1 >> 17;
2946 int y = plane_state->base.src.y1 >> 17;
2947 int w = drm_rect_width(&plane_state->base.src) >> 17;
2948 int h = drm_rect_height(&plane_state->base.src) >> 17;
2949 u32 offset;
2950
2951 intel_add_fb_offsets(&x, &y, plane_state, 1);
2952 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2953
2954 /* FIXME not quite sure how/if these apply to the chroma plane */
2955 if (w > max_width || h > max_height) {
2956 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2957 w, h, max_width, max_height);
2958 return -EINVAL;
2959 }
2960
2961 plane_state->aux.offset = offset;
2962 plane_state->aux.x = x;
2963 plane_state->aux.y = y;
2964
2965 return 0;
2966 }
2967
2968 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2969 {
2970 const struct drm_framebuffer *fb = plane_state->base.fb;
2971 unsigned int rotation = plane_state->base.rotation;
2972 int ret;
2973
2974 if (!plane_state->base.visible)
2975 return 0;
2976
2977 /* Rotate src coordinates to match rotated GTT view */
2978 if (drm_rotation_90_or_270(rotation))
2979 drm_rect_rotate(&plane_state->base.src,
2980 fb->width << 16, fb->height << 16,
2981 DRM_ROTATE_270);
2982
2983 /*
2984 * Handle the AUX surface first since
2985 * the main surface setup depends on it.
2986 */
2987 if (fb->pixel_format == DRM_FORMAT_NV12) {
2988 ret = skl_check_nv12_aux_surface(plane_state);
2989 if (ret)
2990 return ret;
2991 } else {
2992 plane_state->aux.offset = ~0xfff;
2993 plane_state->aux.x = 0;
2994 plane_state->aux.y = 0;
2995 }
2996
2997 ret = skl_check_main_surface(plane_state);
2998 if (ret)
2999 return ret;
3000
3001 return 0;
3002 }
3003
3004 static void i9xx_update_primary_plane(struct drm_plane *primary,
3005 const struct intel_crtc_state *crtc_state,
3006 const struct intel_plane_state *plane_state)
3007 {
3008 struct drm_i915_private *dev_priv = to_i915(primary->dev);
3009 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3010 struct drm_framebuffer *fb = plane_state->base.fb;
3011 int plane = intel_crtc->plane;
3012 u32 linear_offset;
3013 u32 dspcntr;
3014 i915_reg_t reg = DSPCNTR(plane);
3015 unsigned int rotation = plane_state->base.rotation;
3016 int x = plane_state->base.src.x1 >> 16;
3017 int y = plane_state->base.src.y1 >> 16;
3018
3019 dspcntr = DISPPLANE_GAMMA_ENABLE;
3020
3021 dspcntr |= DISPLAY_PLANE_ENABLE;
3022
3023 if (INTEL_GEN(dev_priv) < 4) {
3024 if (intel_crtc->pipe == PIPE_B)
3025 dspcntr |= DISPPLANE_SEL_PIPE_B;
3026
3027 /* pipesrc and dspsize control the size that is scaled from,
3028 * which should always be the user's requested size.
3029 */
3030 I915_WRITE(DSPSIZE(plane),
3031 ((crtc_state->pipe_src_h - 1) << 16) |
3032 (crtc_state->pipe_src_w - 1));
3033 I915_WRITE(DSPPOS(plane), 0);
3034 } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3035 I915_WRITE(PRIMSIZE(plane),
3036 ((crtc_state->pipe_src_h - 1) << 16) |
3037 (crtc_state->pipe_src_w - 1));
3038 I915_WRITE(PRIMPOS(plane), 0);
3039 I915_WRITE(PRIMCNSTALPHA(plane), 0);
3040 }
3041
3042 switch (fb->pixel_format) {
3043 case DRM_FORMAT_C8:
3044 dspcntr |= DISPPLANE_8BPP;
3045 break;
3046 case DRM_FORMAT_XRGB1555:
3047 dspcntr |= DISPPLANE_BGRX555;
3048 break;
3049 case DRM_FORMAT_RGB565:
3050 dspcntr |= DISPPLANE_BGRX565;
3051 break;
3052 case DRM_FORMAT_XRGB8888:
3053 dspcntr |= DISPPLANE_BGRX888;
3054 break;
3055 case DRM_FORMAT_XBGR8888:
3056 dspcntr |= DISPPLANE_RGBX888;
3057 break;
3058 case DRM_FORMAT_XRGB2101010:
3059 dspcntr |= DISPPLANE_BGRX101010;
3060 break;
3061 case DRM_FORMAT_XBGR2101010:
3062 dspcntr |= DISPPLANE_RGBX101010;
3063 break;
3064 default:
3065 BUG();
3066 }
3067
3068 if (INTEL_GEN(dev_priv) >= 4 &&
3069 fb->modifier == I915_FORMAT_MOD_X_TILED)
3070 dspcntr |= DISPPLANE_TILED;
3071
3072 if (rotation & DRM_ROTATE_180)
3073 dspcntr |= DISPPLANE_ROTATE_180;
3074
3075 if (rotation & DRM_REFLECT_X)
3076 dspcntr |= DISPPLANE_MIRROR;
3077
3078 if (IS_G4X(dev_priv))
3079 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3080
3081 intel_add_fb_offsets(&x, &y, plane_state, 0);
3082
3083 if (INTEL_GEN(dev_priv) >= 4)
3084 intel_crtc->dspaddr_offset =
3085 intel_compute_tile_offset(&x, &y, plane_state, 0);
3086
3087 if (rotation & DRM_ROTATE_180) {
3088 x += crtc_state->pipe_src_w - 1;
3089 y += crtc_state->pipe_src_h - 1;
3090 } else if (rotation & DRM_REFLECT_X) {
3091 x += crtc_state->pipe_src_w - 1;
3092 }
3093
3094 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3095
3096 if (INTEL_GEN(dev_priv) < 4)
3097 intel_crtc->dspaddr_offset = linear_offset;
3098
3099 intel_crtc->adjusted_x = x;
3100 intel_crtc->adjusted_y = y;
3101
3102 I915_WRITE(reg, dspcntr);
3103
3104 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3105 if (INTEL_GEN(dev_priv) >= 4) {
3106 I915_WRITE(DSPSURF(plane),
3107 intel_fb_gtt_offset(fb, rotation) +
3108 intel_crtc->dspaddr_offset);
3109 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3110 I915_WRITE(DSPLINOFF(plane), linear_offset);
3111 } else {
3112 I915_WRITE(DSPADDR(plane),
3113 intel_fb_gtt_offset(fb, rotation) +
3114 intel_crtc->dspaddr_offset);
3115 }
3116 POSTING_READ(reg);
3117 }
3118
3119 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3120 struct drm_crtc *crtc)
3121 {
3122 struct drm_device *dev = crtc->dev;
3123 struct drm_i915_private *dev_priv = to_i915(dev);
3124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3125 int plane = intel_crtc->plane;
3126
3127 I915_WRITE(DSPCNTR(plane), 0);
3128 if (INTEL_INFO(dev_priv)->gen >= 4)
3129 I915_WRITE(DSPSURF(plane), 0);
3130 else
3131 I915_WRITE(DSPADDR(plane), 0);
3132 POSTING_READ(DSPCNTR(plane));
3133 }
3134
3135 static void ironlake_update_primary_plane(struct drm_plane *primary,
3136 const struct intel_crtc_state *crtc_state,
3137 const struct intel_plane_state *plane_state)
3138 {
3139 struct drm_device *dev = primary->dev;
3140 struct drm_i915_private *dev_priv = to_i915(dev);
3141 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3142 struct drm_framebuffer *fb = plane_state->base.fb;
3143 int plane = intel_crtc->plane;
3144 u32 linear_offset;
3145 u32 dspcntr;
3146 i915_reg_t reg = DSPCNTR(plane);
3147 unsigned int rotation = plane_state->base.rotation;
3148 int x = plane_state->base.src.x1 >> 16;
3149 int y = plane_state->base.src.y1 >> 16;
3150
3151 dspcntr = DISPPLANE_GAMMA_ENABLE;
3152 dspcntr |= DISPLAY_PLANE_ENABLE;
3153
3154 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3155 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3156
3157 switch (fb->pixel_format) {
3158 case DRM_FORMAT_C8:
3159 dspcntr |= DISPPLANE_8BPP;
3160 break;
3161 case DRM_FORMAT_RGB565:
3162 dspcntr |= DISPPLANE_BGRX565;
3163 break;
3164 case DRM_FORMAT_XRGB8888:
3165 dspcntr |= DISPPLANE_BGRX888;
3166 break;
3167 case DRM_FORMAT_XBGR8888:
3168 dspcntr |= DISPPLANE_RGBX888;
3169 break;
3170 case DRM_FORMAT_XRGB2101010:
3171 dspcntr |= DISPPLANE_BGRX101010;
3172 break;
3173 case DRM_FORMAT_XBGR2101010:
3174 dspcntr |= DISPPLANE_RGBX101010;
3175 break;
3176 default:
3177 BUG();
3178 }
3179
3180 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
3181 dspcntr |= DISPPLANE_TILED;
3182
3183 if (rotation & DRM_ROTATE_180)
3184 dspcntr |= DISPPLANE_ROTATE_180;
3185
3186 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv))
3187 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3188
3189 intel_add_fb_offsets(&x, &y, plane_state, 0);
3190
3191 intel_crtc->dspaddr_offset =
3192 intel_compute_tile_offset(&x, &y, plane_state, 0);
3193
3194 /* HSW+ does this automagically in hardware */
3195 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) &&
3196 rotation & DRM_ROTATE_180) {
3197 x += crtc_state->pipe_src_w - 1;
3198 y += crtc_state->pipe_src_h - 1;
3199 }
3200
3201 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3202
3203 intel_crtc->adjusted_x = x;
3204 intel_crtc->adjusted_y = y;
3205
3206 I915_WRITE(reg, dspcntr);
3207
3208 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3209 I915_WRITE(DSPSURF(plane),
3210 intel_fb_gtt_offset(fb, rotation) +
3211 intel_crtc->dspaddr_offset);
3212 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3213 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3214 } else {
3215 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3216 I915_WRITE(DSPLINOFF(plane), linear_offset);
3217 }
3218 POSTING_READ(reg);
3219 }
3220
3221 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3222 uint64_t fb_modifier, uint32_t pixel_format)
3223 {
3224 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3225 return 64;
3226 } else {
3227 int cpp = drm_format_plane_cpp(pixel_format, 0);
3228
3229 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3230 }
3231 }
3232
3233 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb,
3234 unsigned int rotation)
3235 {
3236 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3237 struct i915_ggtt_view view;
3238 struct i915_vma *vma;
3239
3240 intel_fill_fb_ggtt_view(&view, fb, rotation);
3241
3242 vma = i915_gem_object_to_ggtt(obj, &view);
3243 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
3244 view.type))
3245 return -1;
3246
3247 return i915_ggtt_offset(vma);
3248 }
3249
3250 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3251 {
3252 struct drm_device *dev = intel_crtc->base.dev;
3253 struct drm_i915_private *dev_priv = to_i915(dev);
3254
3255 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3256 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3257 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3258 }
3259
3260 /*
3261 * This function detaches (aka. unbinds) unused scalers in hardware
3262 */
3263 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3264 {
3265 struct intel_crtc_scaler_state *scaler_state;
3266 int i;
3267
3268 scaler_state = &intel_crtc->config->scaler_state;
3269
3270 /* loop through and disable scalers that aren't in use */
3271 for (i = 0; i < intel_crtc->num_scalers; i++) {
3272 if (!scaler_state->scalers[i].in_use)
3273 skl_detach_scaler(intel_crtc, i);
3274 }
3275 }
3276
3277 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3278 unsigned int rotation)
3279 {
3280 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3281 u32 stride = intel_fb_pitch(fb, plane, rotation);
3282
3283 /*
3284 * The stride is either expressed as a multiple of 64 bytes chunks for
3285 * linear buffers or in number of tiles for tiled buffers.
3286 */
3287 if (drm_rotation_90_or_270(rotation)) {
3288 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
3289
3290 stride /= intel_tile_height(dev_priv, fb->modifier, cpp);
3291 } else {
3292 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier,
3293 fb->pixel_format);
3294 }
3295
3296 return stride;
3297 }
3298
3299 u32 skl_plane_ctl_format(uint32_t pixel_format)
3300 {
3301 switch (pixel_format) {
3302 case DRM_FORMAT_C8:
3303 return PLANE_CTL_FORMAT_INDEXED;
3304 case DRM_FORMAT_RGB565:
3305 return PLANE_CTL_FORMAT_RGB_565;
3306 case DRM_FORMAT_XBGR8888:
3307 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3308 case DRM_FORMAT_XRGB8888:
3309 return PLANE_CTL_FORMAT_XRGB_8888;
3310 /*
3311 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3312 * to be already pre-multiplied. We need to add a knob (or a different
3313 * DRM_FORMAT) for user-space to configure that.
3314 */
3315 case DRM_FORMAT_ABGR8888:
3316 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3317 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3318 case DRM_FORMAT_ARGB8888:
3319 return PLANE_CTL_FORMAT_XRGB_8888 |
3320 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3321 case DRM_FORMAT_XRGB2101010:
3322 return PLANE_CTL_FORMAT_XRGB_2101010;
3323 case DRM_FORMAT_XBGR2101010:
3324 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3325 case DRM_FORMAT_YUYV:
3326 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3327 case DRM_FORMAT_YVYU:
3328 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3329 case DRM_FORMAT_UYVY:
3330 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3331 case DRM_FORMAT_VYUY:
3332 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3333 default:
3334 MISSING_CASE(pixel_format);
3335 }
3336
3337 return 0;
3338 }
3339
3340 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3341 {
3342 switch (fb_modifier) {
3343 case DRM_FORMAT_MOD_NONE:
3344 break;
3345 case I915_FORMAT_MOD_X_TILED:
3346 return PLANE_CTL_TILED_X;
3347 case I915_FORMAT_MOD_Y_TILED:
3348 return PLANE_CTL_TILED_Y;
3349 case I915_FORMAT_MOD_Yf_TILED:
3350 return PLANE_CTL_TILED_YF;
3351 default:
3352 MISSING_CASE(fb_modifier);
3353 }
3354
3355 return 0;
3356 }
3357
3358 u32 skl_plane_ctl_rotation(unsigned int rotation)
3359 {
3360 switch (rotation) {
3361 case DRM_ROTATE_0:
3362 break;
3363 /*
3364 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3365 * while i915 HW rotation is clockwise, thats why this swapping.
3366 */
3367 case DRM_ROTATE_90:
3368 return PLANE_CTL_ROTATE_270;
3369 case DRM_ROTATE_180:
3370 return PLANE_CTL_ROTATE_180;
3371 case DRM_ROTATE_270:
3372 return PLANE_CTL_ROTATE_90;
3373 default:
3374 MISSING_CASE(rotation);
3375 }
3376
3377 return 0;
3378 }
3379
3380 static void skylake_update_primary_plane(struct drm_plane *plane,
3381 const struct intel_crtc_state *crtc_state,
3382 const struct intel_plane_state *plane_state)
3383 {
3384 struct drm_device *dev = plane->dev;
3385 struct drm_i915_private *dev_priv = to_i915(dev);
3386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3387 struct drm_framebuffer *fb = plane_state->base.fb;
3388 int pipe = intel_crtc->pipe;
3389 u32 plane_ctl;
3390 unsigned int rotation = plane_state->base.rotation;
3391 u32 stride = skl_plane_stride(fb, 0, rotation);
3392 u32 surf_addr = plane_state->main.offset;
3393 int scaler_id = plane_state->scaler_id;
3394 int src_x = plane_state->main.x;
3395 int src_y = plane_state->main.y;
3396 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3397 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3398 int dst_x = plane_state->base.dst.x1;
3399 int dst_y = plane_state->base.dst.y1;
3400 int dst_w = drm_rect_width(&plane_state->base.dst);
3401 int dst_h = drm_rect_height(&plane_state->base.dst);
3402
3403 plane_ctl = PLANE_CTL_ENABLE |
3404 PLANE_CTL_PIPE_GAMMA_ENABLE |
3405 PLANE_CTL_PIPE_CSC_ENABLE;
3406
3407 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3408 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3409 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3410 plane_ctl |= skl_plane_ctl_rotation(rotation);
3411
3412 /* Sizes are 0 based */
3413 src_w--;
3414 src_h--;
3415 dst_w--;
3416 dst_h--;
3417
3418 intel_crtc->dspaddr_offset = surf_addr;
3419
3420 intel_crtc->adjusted_x = src_x;
3421 intel_crtc->adjusted_y = src_y;
3422
3423 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3424 I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
3425 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3426 I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w);
3427
3428 if (scaler_id >= 0) {
3429 uint32_t ps_ctrl = 0;
3430
3431 WARN_ON(!dst_w || !dst_h);
3432 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3433 crtc_state->scaler_state.scalers[scaler_id].mode;
3434 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3435 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3436 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3437 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3438 I915_WRITE(PLANE_POS(pipe, 0), 0);
3439 } else {
3440 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3441 }
3442
3443 I915_WRITE(PLANE_SURF(pipe, 0),
3444 intel_fb_gtt_offset(fb, rotation) + surf_addr);
3445
3446 POSTING_READ(PLANE_SURF(pipe, 0));
3447 }
3448
3449 static void skylake_disable_primary_plane(struct drm_plane *primary,
3450 struct drm_crtc *crtc)
3451 {
3452 struct drm_device *dev = crtc->dev;
3453 struct drm_i915_private *dev_priv = to_i915(dev);
3454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3455 int pipe = intel_crtc->pipe;
3456
3457 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3458 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3459 POSTING_READ(PLANE_SURF(pipe, 0));
3460 }
3461
3462 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3463 static int
3464 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3465 int x, int y, enum mode_set_atomic state)
3466 {
3467 /* Support for kgdboc is disabled, this needs a major rework. */
3468 DRM_ERROR("legacy panic handler not supported any more.\n");
3469
3470 return -ENODEV;
3471 }
3472
3473 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3474 {
3475 struct intel_crtc *crtc;
3476
3477 for_each_intel_crtc(&dev_priv->drm, crtc)
3478 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3479 }
3480
3481 static void intel_update_primary_planes(struct drm_device *dev)
3482 {
3483 struct drm_crtc *crtc;
3484
3485 for_each_crtc(dev, crtc) {
3486 struct intel_plane *plane = to_intel_plane(crtc->primary);
3487 struct intel_plane_state *plane_state =
3488 to_intel_plane_state(plane->base.state);
3489
3490 if (plane_state->base.visible)
3491 plane->update_plane(&plane->base,
3492 to_intel_crtc_state(crtc->state),
3493 plane_state);
3494 }
3495 }
3496
3497 static int
3498 __intel_display_resume(struct drm_device *dev,
3499 struct drm_atomic_state *state)
3500 {
3501 struct drm_crtc_state *crtc_state;
3502 struct drm_crtc *crtc;
3503 int i, ret;
3504
3505 intel_modeset_setup_hw_state(dev);
3506 i915_redisable_vga(to_i915(dev));
3507
3508 if (!state)
3509 return 0;
3510
3511 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3512 /*
3513 * Force recalculation even if we restore
3514 * current state. With fast modeset this may not result
3515 * in a modeset when the state is compatible.
3516 */
3517 crtc_state->mode_changed = true;
3518 }
3519
3520 /* ignore any reset values/BIOS leftovers in the WM registers */
3521 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3522
3523 ret = drm_atomic_commit(state);
3524
3525 WARN_ON(ret == -EDEADLK);
3526 return ret;
3527 }
3528
3529 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3530 {
3531 return intel_has_gpu_reset(dev_priv) &&
3532 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3533 }
3534
3535 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3536 {
3537 struct drm_device *dev = &dev_priv->drm;
3538 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3539 struct drm_atomic_state *state;
3540 int ret;
3541
3542 /*
3543 * Need mode_config.mutex so that we don't
3544 * trample ongoing ->detect() and whatnot.
3545 */
3546 mutex_lock(&dev->mode_config.mutex);
3547 drm_modeset_acquire_init(ctx, 0);
3548 while (1) {
3549 ret = drm_modeset_lock_all_ctx(dev, ctx);
3550 if (ret != -EDEADLK)
3551 break;
3552
3553 drm_modeset_backoff(ctx);
3554 }
3555
3556 /* reset doesn't touch the display, but flips might get nuked anyway, */
3557 if (!i915.force_reset_modeset_test &&
3558 !gpu_reset_clobbers_display(dev_priv))
3559 return;
3560
3561 /*
3562 * Disabling the crtcs gracefully seems nicer. Also the
3563 * g33 docs say we should at least disable all the planes.
3564 */
3565 state = drm_atomic_helper_duplicate_state(dev, ctx);
3566 if (IS_ERR(state)) {
3567 ret = PTR_ERR(state);
3568 state = NULL;
3569 DRM_ERROR("Duplicating state failed with %i\n", ret);
3570 goto err;
3571 }
3572
3573 ret = drm_atomic_helper_disable_all(dev, ctx);
3574 if (ret) {
3575 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3576 goto err;
3577 }
3578
3579 dev_priv->modeset_restore_state = state;
3580 state->acquire_ctx = ctx;
3581 return;
3582
3583 err:
3584 drm_atomic_state_put(state);
3585 }
3586
3587 void intel_finish_reset(struct drm_i915_private *dev_priv)
3588 {
3589 struct drm_device *dev = &dev_priv->drm;
3590 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3591 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3592 int ret;
3593
3594 /*
3595 * Flips in the rings will be nuked by the reset,
3596 * so complete all pending flips so that user space
3597 * will get its events and not get stuck.
3598 */
3599 intel_complete_page_flips(dev_priv);
3600
3601 dev_priv->modeset_restore_state = NULL;
3602
3603 /* reset doesn't touch the display */
3604 if (!gpu_reset_clobbers_display(dev_priv)) {
3605 if (!state) {
3606 /*
3607 * Flips in the rings have been nuked by the reset,
3608 * so update the base address of all primary
3609 * planes to the the last fb to make sure we're
3610 * showing the correct fb after a reset.
3611 *
3612 * FIXME: Atomic will make this obsolete since we won't schedule
3613 * CS-based flips (which might get lost in gpu resets) any more.
3614 */
3615 intel_update_primary_planes(dev);
3616 } else {
3617 ret = __intel_display_resume(dev, state);
3618 if (ret)
3619 DRM_ERROR("Restoring old state failed with %i\n", ret);
3620 }
3621 } else {
3622 /*
3623 * The display has been reset as well,
3624 * so need a full re-initialization.
3625 */
3626 intel_runtime_pm_disable_interrupts(dev_priv);
3627 intel_runtime_pm_enable_interrupts(dev_priv);
3628
3629 intel_pps_unlock_regs_wa(dev_priv);
3630 intel_modeset_init_hw(dev);
3631
3632 spin_lock_irq(&dev_priv->irq_lock);
3633 if (dev_priv->display.hpd_irq_setup)
3634 dev_priv->display.hpd_irq_setup(dev_priv);
3635 spin_unlock_irq(&dev_priv->irq_lock);
3636
3637 ret = __intel_display_resume(dev, state);
3638 if (ret)
3639 DRM_ERROR("Restoring old state failed with %i\n", ret);
3640
3641 intel_hpd_init(dev_priv);
3642 }
3643
3644 if (state)
3645 drm_atomic_state_put(state);
3646 drm_modeset_drop_locks(ctx);
3647 drm_modeset_acquire_fini(ctx);
3648 mutex_unlock(&dev->mode_config.mutex);
3649 }
3650
3651 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3652 {
3653 struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3654
3655 if (i915_reset_in_progress(error))
3656 return true;
3657
3658 if (crtc->reset_count != i915_reset_count(error))
3659 return true;
3660
3661 return false;
3662 }
3663
3664 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3665 {
3666 struct drm_device *dev = crtc->dev;
3667 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3668 bool pending;
3669
3670 if (abort_flip_on_reset(intel_crtc))
3671 return false;
3672
3673 spin_lock_irq(&dev->event_lock);
3674 pending = to_intel_crtc(crtc)->flip_work != NULL;
3675 spin_unlock_irq(&dev->event_lock);
3676
3677 return pending;
3678 }
3679
3680 static void intel_update_pipe_config(struct intel_crtc *crtc,
3681 struct intel_crtc_state *old_crtc_state)
3682 {
3683 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3684 struct intel_crtc_state *pipe_config =
3685 to_intel_crtc_state(crtc->base.state);
3686
3687 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3688 crtc->base.mode = crtc->base.state->mode;
3689
3690 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3691 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3692 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3693
3694 /*
3695 * Update pipe size and adjust fitter if needed: the reason for this is
3696 * that in compute_mode_changes we check the native mode (not the pfit
3697 * mode) to see if we can flip rather than do a full mode set. In the
3698 * fastboot case, we'll flip, but if we don't update the pipesrc and
3699 * pfit state, we'll end up with a big fb scanned out into the wrong
3700 * sized surface.
3701 */
3702
3703 I915_WRITE(PIPESRC(crtc->pipe),
3704 ((pipe_config->pipe_src_w - 1) << 16) |
3705 (pipe_config->pipe_src_h - 1));
3706
3707 /* on skylake this is done by detaching scalers */
3708 if (INTEL_GEN(dev_priv) >= 9) {
3709 skl_detach_scalers(crtc);
3710
3711 if (pipe_config->pch_pfit.enabled)
3712 skylake_pfit_enable(crtc);
3713 } else if (HAS_PCH_SPLIT(dev_priv)) {
3714 if (pipe_config->pch_pfit.enabled)
3715 ironlake_pfit_enable(crtc);
3716 else if (old_crtc_state->pch_pfit.enabled)
3717 ironlake_pfit_disable(crtc, true);
3718 }
3719 }
3720
3721 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3722 {
3723 struct drm_device *dev = crtc->dev;
3724 struct drm_i915_private *dev_priv = to_i915(dev);
3725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3726 int pipe = intel_crtc->pipe;
3727 i915_reg_t reg;
3728 u32 temp;
3729
3730 /* enable normal train */
3731 reg = FDI_TX_CTL(pipe);
3732 temp = I915_READ(reg);
3733 if (IS_IVYBRIDGE(dev_priv)) {
3734 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3735 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3736 } else {
3737 temp &= ~FDI_LINK_TRAIN_NONE;
3738 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3739 }
3740 I915_WRITE(reg, temp);
3741
3742 reg = FDI_RX_CTL(pipe);
3743 temp = I915_READ(reg);
3744 if (HAS_PCH_CPT(dev_priv)) {
3745 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3746 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3747 } else {
3748 temp &= ~FDI_LINK_TRAIN_NONE;
3749 temp |= FDI_LINK_TRAIN_NONE;
3750 }
3751 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3752
3753 /* wait one idle pattern time */
3754 POSTING_READ(reg);
3755 udelay(1000);
3756
3757 /* IVB wants error correction enabled */
3758 if (IS_IVYBRIDGE(dev_priv))
3759 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3760 FDI_FE_ERRC_ENABLE);
3761 }
3762
3763 /* The FDI link training functions for ILK/Ibexpeak. */
3764 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3765 {
3766 struct drm_device *dev = crtc->dev;
3767 struct drm_i915_private *dev_priv = to_i915(dev);
3768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3769 int pipe = intel_crtc->pipe;
3770 i915_reg_t reg;
3771 u32 temp, tries;
3772
3773 /* FDI needs bits from pipe first */
3774 assert_pipe_enabled(dev_priv, pipe);
3775
3776 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3777 for train result */
3778 reg = FDI_RX_IMR(pipe);
3779 temp = I915_READ(reg);
3780 temp &= ~FDI_RX_SYMBOL_LOCK;
3781 temp &= ~FDI_RX_BIT_LOCK;
3782 I915_WRITE(reg, temp);
3783 I915_READ(reg);
3784 udelay(150);
3785
3786 /* enable CPU FDI TX and PCH FDI RX */
3787 reg = FDI_TX_CTL(pipe);
3788 temp = I915_READ(reg);
3789 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3790 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3791 temp &= ~FDI_LINK_TRAIN_NONE;
3792 temp |= FDI_LINK_TRAIN_PATTERN_1;
3793 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3794
3795 reg = FDI_RX_CTL(pipe);
3796 temp = I915_READ(reg);
3797 temp &= ~FDI_LINK_TRAIN_NONE;
3798 temp |= FDI_LINK_TRAIN_PATTERN_1;
3799 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3800
3801 POSTING_READ(reg);
3802 udelay(150);
3803
3804 /* Ironlake workaround, enable clock pointer after FDI enable*/
3805 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3806 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3807 FDI_RX_PHASE_SYNC_POINTER_EN);
3808
3809 reg = FDI_RX_IIR(pipe);
3810 for (tries = 0; tries < 5; tries++) {
3811 temp = I915_READ(reg);
3812 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3813
3814 if ((temp & FDI_RX_BIT_LOCK)) {
3815 DRM_DEBUG_KMS("FDI train 1 done.\n");
3816 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3817 break;
3818 }
3819 }
3820 if (tries == 5)
3821 DRM_ERROR("FDI train 1 fail!\n");
3822
3823 /* Train 2 */
3824 reg = FDI_TX_CTL(pipe);
3825 temp = I915_READ(reg);
3826 temp &= ~FDI_LINK_TRAIN_NONE;
3827 temp |= FDI_LINK_TRAIN_PATTERN_2;
3828 I915_WRITE(reg, temp);
3829
3830 reg = FDI_RX_CTL(pipe);
3831 temp = I915_READ(reg);
3832 temp &= ~FDI_LINK_TRAIN_NONE;
3833 temp |= FDI_LINK_TRAIN_PATTERN_2;
3834 I915_WRITE(reg, temp);
3835
3836 POSTING_READ(reg);
3837 udelay(150);
3838
3839 reg = FDI_RX_IIR(pipe);
3840 for (tries = 0; tries < 5; tries++) {
3841 temp = I915_READ(reg);
3842 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3843
3844 if (temp & FDI_RX_SYMBOL_LOCK) {
3845 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3846 DRM_DEBUG_KMS("FDI train 2 done.\n");
3847 break;
3848 }
3849 }
3850 if (tries == 5)
3851 DRM_ERROR("FDI train 2 fail!\n");
3852
3853 DRM_DEBUG_KMS("FDI train done\n");
3854
3855 }
3856
3857 static const int snb_b_fdi_train_param[] = {
3858 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3859 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3860 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3861 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3862 };
3863
3864 /* The FDI link training functions for SNB/Cougarpoint. */
3865 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3866 {
3867 struct drm_device *dev = crtc->dev;
3868 struct drm_i915_private *dev_priv = to_i915(dev);
3869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3870 int pipe = intel_crtc->pipe;
3871 i915_reg_t reg;
3872 u32 temp, i, retry;
3873
3874 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3875 for train result */
3876 reg = FDI_RX_IMR(pipe);
3877 temp = I915_READ(reg);
3878 temp &= ~FDI_RX_SYMBOL_LOCK;
3879 temp &= ~FDI_RX_BIT_LOCK;
3880 I915_WRITE(reg, temp);
3881
3882 POSTING_READ(reg);
3883 udelay(150);
3884
3885 /* enable CPU FDI TX and PCH FDI RX */
3886 reg = FDI_TX_CTL(pipe);
3887 temp = I915_READ(reg);
3888 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3889 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3890 temp &= ~FDI_LINK_TRAIN_NONE;
3891 temp |= FDI_LINK_TRAIN_PATTERN_1;
3892 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3893 /* SNB-B */
3894 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3895 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3896
3897 I915_WRITE(FDI_RX_MISC(pipe),
3898 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3899
3900 reg = FDI_RX_CTL(pipe);
3901 temp = I915_READ(reg);
3902 if (HAS_PCH_CPT(dev_priv)) {
3903 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3904 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3905 } else {
3906 temp &= ~FDI_LINK_TRAIN_NONE;
3907 temp |= FDI_LINK_TRAIN_PATTERN_1;
3908 }
3909 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3910
3911 POSTING_READ(reg);
3912 udelay(150);
3913
3914 for (i = 0; i < 4; i++) {
3915 reg = FDI_TX_CTL(pipe);
3916 temp = I915_READ(reg);
3917 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3918 temp |= snb_b_fdi_train_param[i];
3919 I915_WRITE(reg, temp);
3920
3921 POSTING_READ(reg);
3922 udelay(500);
3923
3924 for (retry = 0; retry < 5; retry++) {
3925 reg = FDI_RX_IIR(pipe);
3926 temp = I915_READ(reg);
3927 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3928 if (temp & FDI_RX_BIT_LOCK) {
3929 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3930 DRM_DEBUG_KMS("FDI train 1 done.\n");
3931 break;
3932 }
3933 udelay(50);
3934 }
3935 if (retry < 5)
3936 break;
3937 }
3938 if (i == 4)
3939 DRM_ERROR("FDI train 1 fail!\n");
3940
3941 /* Train 2 */
3942 reg = FDI_TX_CTL(pipe);
3943 temp = I915_READ(reg);
3944 temp &= ~FDI_LINK_TRAIN_NONE;
3945 temp |= FDI_LINK_TRAIN_PATTERN_2;
3946 if (IS_GEN6(dev_priv)) {
3947 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3948 /* SNB-B */
3949 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3950 }
3951 I915_WRITE(reg, temp);
3952
3953 reg = FDI_RX_CTL(pipe);
3954 temp = I915_READ(reg);
3955 if (HAS_PCH_CPT(dev_priv)) {
3956 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3957 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3958 } else {
3959 temp &= ~FDI_LINK_TRAIN_NONE;
3960 temp |= FDI_LINK_TRAIN_PATTERN_2;
3961 }
3962 I915_WRITE(reg, temp);
3963
3964 POSTING_READ(reg);
3965 udelay(150);
3966
3967 for (i = 0; i < 4; i++) {
3968 reg = FDI_TX_CTL(pipe);
3969 temp = I915_READ(reg);
3970 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3971 temp |= snb_b_fdi_train_param[i];
3972 I915_WRITE(reg, temp);
3973
3974 POSTING_READ(reg);
3975 udelay(500);
3976
3977 for (retry = 0; retry < 5; retry++) {
3978 reg = FDI_RX_IIR(pipe);
3979 temp = I915_READ(reg);
3980 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3981 if (temp & FDI_RX_SYMBOL_LOCK) {
3982 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3983 DRM_DEBUG_KMS("FDI train 2 done.\n");
3984 break;
3985 }
3986 udelay(50);
3987 }
3988 if (retry < 5)
3989 break;
3990 }
3991 if (i == 4)
3992 DRM_ERROR("FDI train 2 fail!\n");
3993
3994 DRM_DEBUG_KMS("FDI train done.\n");
3995 }
3996
3997 /* Manual link training for Ivy Bridge A0 parts */
3998 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3999 {
4000 struct drm_device *dev = crtc->dev;
4001 struct drm_i915_private *dev_priv = to_i915(dev);
4002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4003 int pipe = intel_crtc->pipe;
4004 i915_reg_t reg;
4005 u32 temp, i, j;
4006
4007 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4008 for train result */
4009 reg = FDI_RX_IMR(pipe);
4010 temp = I915_READ(reg);
4011 temp &= ~FDI_RX_SYMBOL_LOCK;
4012 temp &= ~FDI_RX_BIT_LOCK;
4013 I915_WRITE(reg, temp);
4014
4015 POSTING_READ(reg);
4016 udelay(150);
4017
4018 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4019 I915_READ(FDI_RX_IIR(pipe)));
4020
4021 /* Try each vswing and preemphasis setting twice before moving on */
4022 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4023 /* disable first in case we need to retry */
4024 reg = FDI_TX_CTL(pipe);
4025 temp = I915_READ(reg);
4026 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4027 temp &= ~FDI_TX_ENABLE;
4028 I915_WRITE(reg, temp);
4029
4030 reg = FDI_RX_CTL(pipe);
4031 temp = I915_READ(reg);
4032 temp &= ~FDI_LINK_TRAIN_AUTO;
4033 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4034 temp &= ~FDI_RX_ENABLE;
4035 I915_WRITE(reg, temp);
4036
4037 /* enable CPU FDI TX and PCH FDI RX */
4038 reg = FDI_TX_CTL(pipe);
4039 temp = I915_READ(reg);
4040 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4041 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4042 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4043 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4044 temp |= snb_b_fdi_train_param[j/2];
4045 temp |= FDI_COMPOSITE_SYNC;
4046 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4047
4048 I915_WRITE(FDI_RX_MISC(pipe),
4049 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4050
4051 reg = FDI_RX_CTL(pipe);
4052 temp = I915_READ(reg);
4053 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4054 temp |= FDI_COMPOSITE_SYNC;
4055 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4056
4057 POSTING_READ(reg);
4058 udelay(1); /* should be 0.5us */
4059
4060 for (i = 0; i < 4; i++) {
4061 reg = FDI_RX_IIR(pipe);
4062 temp = I915_READ(reg);
4063 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4064
4065 if (temp & FDI_RX_BIT_LOCK ||
4066 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4067 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4068 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4069 i);
4070 break;
4071 }
4072 udelay(1); /* should be 0.5us */
4073 }
4074 if (i == 4) {
4075 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4076 continue;
4077 }
4078
4079 /* Train 2 */
4080 reg = FDI_TX_CTL(pipe);
4081 temp = I915_READ(reg);
4082 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4083 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4084 I915_WRITE(reg, temp);
4085
4086 reg = FDI_RX_CTL(pipe);
4087 temp = I915_READ(reg);
4088 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4089 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4090 I915_WRITE(reg, temp);
4091
4092 POSTING_READ(reg);
4093 udelay(2); /* should be 1.5us */
4094
4095 for (i = 0; i < 4; i++) {
4096 reg = FDI_RX_IIR(pipe);
4097 temp = I915_READ(reg);
4098 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4099
4100 if (temp & FDI_RX_SYMBOL_LOCK ||
4101 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4102 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4103 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4104 i);
4105 goto train_done;
4106 }
4107 udelay(2); /* should be 1.5us */
4108 }
4109 if (i == 4)
4110 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4111 }
4112
4113 train_done:
4114 DRM_DEBUG_KMS("FDI train done.\n");
4115 }
4116
4117 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4118 {
4119 struct drm_device *dev = intel_crtc->base.dev;
4120 struct drm_i915_private *dev_priv = to_i915(dev);
4121 int pipe = intel_crtc->pipe;
4122 i915_reg_t reg;
4123 u32 temp;
4124
4125 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4126 reg = FDI_RX_CTL(pipe);
4127 temp = I915_READ(reg);
4128 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4129 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4130 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4131 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4132
4133 POSTING_READ(reg);
4134 udelay(200);
4135
4136 /* Switch from Rawclk to PCDclk */
4137 temp = I915_READ(reg);
4138 I915_WRITE(reg, temp | FDI_PCDCLK);
4139
4140 POSTING_READ(reg);
4141 udelay(200);
4142
4143 /* Enable CPU FDI TX PLL, always on for Ironlake */
4144 reg = FDI_TX_CTL(pipe);
4145 temp = I915_READ(reg);
4146 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4147 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4148
4149 POSTING_READ(reg);
4150 udelay(100);
4151 }
4152 }
4153
4154 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4155 {
4156 struct drm_device *dev = intel_crtc->base.dev;
4157 struct drm_i915_private *dev_priv = to_i915(dev);
4158 int pipe = intel_crtc->pipe;
4159 i915_reg_t reg;
4160 u32 temp;
4161
4162 /* Switch from PCDclk to Rawclk */
4163 reg = FDI_RX_CTL(pipe);
4164 temp = I915_READ(reg);
4165 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4166
4167 /* Disable CPU FDI TX PLL */
4168 reg = FDI_TX_CTL(pipe);
4169 temp = I915_READ(reg);
4170 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4171
4172 POSTING_READ(reg);
4173 udelay(100);
4174
4175 reg = FDI_RX_CTL(pipe);
4176 temp = I915_READ(reg);
4177 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4178
4179 /* Wait for the clocks to turn off. */
4180 POSTING_READ(reg);
4181 udelay(100);
4182 }
4183
4184 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4185 {
4186 struct drm_device *dev = crtc->dev;
4187 struct drm_i915_private *dev_priv = to_i915(dev);
4188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4189 int pipe = intel_crtc->pipe;
4190 i915_reg_t reg;
4191 u32 temp;
4192
4193 /* disable CPU FDI tx and PCH FDI rx */
4194 reg = FDI_TX_CTL(pipe);
4195 temp = I915_READ(reg);
4196 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4197 POSTING_READ(reg);
4198
4199 reg = FDI_RX_CTL(pipe);
4200 temp = I915_READ(reg);
4201 temp &= ~(0x7 << 16);
4202 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4203 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4204
4205 POSTING_READ(reg);
4206 udelay(100);
4207
4208 /* Ironlake workaround, disable clock pointer after downing FDI */
4209 if (HAS_PCH_IBX(dev_priv))
4210 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4211
4212 /* still set train pattern 1 */
4213 reg = FDI_TX_CTL(pipe);
4214 temp = I915_READ(reg);
4215 temp &= ~FDI_LINK_TRAIN_NONE;
4216 temp |= FDI_LINK_TRAIN_PATTERN_1;
4217 I915_WRITE(reg, temp);
4218
4219 reg = FDI_RX_CTL(pipe);
4220 temp = I915_READ(reg);
4221 if (HAS_PCH_CPT(dev_priv)) {
4222 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4223 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4224 } else {
4225 temp &= ~FDI_LINK_TRAIN_NONE;
4226 temp |= FDI_LINK_TRAIN_PATTERN_1;
4227 }
4228 /* BPC in FDI rx is consistent with that in PIPECONF */
4229 temp &= ~(0x07 << 16);
4230 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4231 I915_WRITE(reg, temp);
4232
4233 POSTING_READ(reg);
4234 udelay(100);
4235 }
4236
4237 bool intel_has_pending_fb_unpin(struct drm_device *dev)
4238 {
4239 struct drm_i915_private *dev_priv = to_i915(dev);
4240 struct intel_crtc *crtc;
4241
4242 /* Note that we don't need to be called with mode_config.lock here
4243 * as our list of CRTC objects is static for the lifetime of the
4244 * device and so cannot disappear as we iterate. Similarly, we can
4245 * happily treat the predicates as racy, atomic checks as userspace
4246 * cannot claim and pin a new fb without at least acquring the
4247 * struct_mutex and so serialising with us.
4248 */
4249 for_each_intel_crtc(dev, crtc) {
4250 if (atomic_read(&crtc->unpin_work_count) == 0)
4251 continue;
4252
4253 if (crtc->flip_work)
4254 intel_wait_for_vblank(dev_priv, crtc->pipe);
4255
4256 return true;
4257 }
4258
4259 return false;
4260 }
4261
4262 static void page_flip_completed(struct intel_crtc *intel_crtc)
4263 {
4264 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4265 struct intel_flip_work *work = intel_crtc->flip_work;
4266
4267 intel_crtc->flip_work = NULL;
4268
4269 if (work->event)
4270 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4271
4272 drm_crtc_vblank_put(&intel_crtc->base);
4273
4274 wake_up_all(&dev_priv->pending_flip_queue);
4275 queue_work(dev_priv->wq, &work->unpin_work);
4276
4277 trace_i915_flip_complete(intel_crtc->plane,
4278 work->pending_flip_obj);
4279 }
4280
4281 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4282 {
4283 struct drm_device *dev = crtc->dev;
4284 struct drm_i915_private *dev_priv = to_i915(dev);
4285 long ret;
4286
4287 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4288
4289 ret = wait_event_interruptible_timeout(
4290 dev_priv->pending_flip_queue,
4291 !intel_crtc_has_pending_flip(crtc),
4292 60*HZ);
4293
4294 if (ret < 0)
4295 return ret;
4296
4297 if (ret == 0) {
4298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4299 struct intel_flip_work *work;
4300
4301 spin_lock_irq(&dev->event_lock);
4302 work = intel_crtc->flip_work;
4303 if (work && !is_mmio_work(work)) {
4304 WARN_ONCE(1, "Removing stuck page flip\n");
4305 page_flip_completed(intel_crtc);
4306 }
4307 spin_unlock_irq(&dev->event_lock);
4308 }
4309
4310 return 0;
4311 }
4312
4313 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4314 {
4315 u32 temp;
4316
4317 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4318
4319 mutex_lock(&dev_priv->sb_lock);
4320
4321 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4322 temp |= SBI_SSCCTL_DISABLE;
4323 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4324
4325 mutex_unlock(&dev_priv->sb_lock);
4326 }
4327
4328 /* Program iCLKIP clock to the desired frequency */
4329 static void lpt_program_iclkip(struct drm_crtc *crtc)
4330 {
4331 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4332 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
4333 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4334 u32 temp;
4335
4336 lpt_disable_iclkip(dev_priv);
4337
4338 /* The iCLK virtual clock root frequency is in MHz,
4339 * but the adjusted_mode->crtc_clock in in KHz. To get the
4340 * divisors, it is necessary to divide one by another, so we
4341 * convert the virtual clock precision to KHz here for higher
4342 * precision.
4343 */
4344 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4345 u32 iclk_virtual_root_freq = 172800 * 1000;
4346 u32 iclk_pi_range = 64;
4347 u32 desired_divisor;
4348
4349 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4350 clock << auxdiv);
4351 divsel = (desired_divisor / iclk_pi_range) - 2;
4352 phaseinc = desired_divisor % iclk_pi_range;
4353
4354 /*
4355 * Near 20MHz is a corner case which is
4356 * out of range for the 7-bit divisor
4357 */
4358 if (divsel <= 0x7f)
4359 break;
4360 }
4361
4362 /* This should not happen with any sane values */
4363 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4364 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4365 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4366 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4367
4368 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4369 clock,
4370 auxdiv,
4371 divsel,
4372 phasedir,
4373 phaseinc);
4374
4375 mutex_lock(&dev_priv->sb_lock);
4376
4377 /* Program SSCDIVINTPHASE6 */
4378 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4379 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4380 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4381 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4382 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4383 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4384 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4385 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4386
4387 /* Program SSCAUXDIV */
4388 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4389 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4390 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4391 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4392
4393 /* Enable modulator and associated divider */
4394 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4395 temp &= ~SBI_SSCCTL_DISABLE;
4396 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4397
4398 mutex_unlock(&dev_priv->sb_lock);
4399
4400 /* Wait for initialization time */
4401 udelay(24);
4402
4403 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4404 }
4405
4406 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4407 {
4408 u32 divsel, phaseinc, auxdiv;
4409 u32 iclk_virtual_root_freq = 172800 * 1000;
4410 u32 iclk_pi_range = 64;
4411 u32 desired_divisor;
4412 u32 temp;
4413
4414 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4415 return 0;
4416
4417 mutex_lock(&dev_priv->sb_lock);
4418
4419 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4420 if (temp & SBI_SSCCTL_DISABLE) {
4421 mutex_unlock(&dev_priv->sb_lock);
4422 return 0;
4423 }
4424
4425 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4426 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4427 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4428 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4429 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4430
4431 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4432 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4433 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4434
4435 mutex_unlock(&dev_priv->sb_lock);
4436
4437 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4438
4439 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4440 desired_divisor << auxdiv);
4441 }
4442
4443 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4444 enum pipe pch_transcoder)
4445 {
4446 struct drm_device *dev = crtc->base.dev;
4447 struct drm_i915_private *dev_priv = to_i915(dev);
4448 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4449
4450 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4451 I915_READ(HTOTAL(cpu_transcoder)));
4452 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4453 I915_READ(HBLANK(cpu_transcoder)));
4454 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4455 I915_READ(HSYNC(cpu_transcoder)));
4456
4457 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4458 I915_READ(VTOTAL(cpu_transcoder)));
4459 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4460 I915_READ(VBLANK(cpu_transcoder)));
4461 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4462 I915_READ(VSYNC(cpu_transcoder)));
4463 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4464 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4465 }
4466
4467 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4468 {
4469 struct drm_i915_private *dev_priv = to_i915(dev);
4470 uint32_t temp;
4471
4472 temp = I915_READ(SOUTH_CHICKEN1);
4473 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4474 return;
4475
4476 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4477 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4478
4479 temp &= ~FDI_BC_BIFURCATION_SELECT;
4480 if (enable)
4481 temp |= FDI_BC_BIFURCATION_SELECT;
4482
4483 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4484 I915_WRITE(SOUTH_CHICKEN1, temp);
4485 POSTING_READ(SOUTH_CHICKEN1);
4486 }
4487
4488 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4489 {
4490 struct drm_device *dev = intel_crtc->base.dev;
4491
4492 switch (intel_crtc->pipe) {
4493 case PIPE_A:
4494 break;
4495 case PIPE_B:
4496 if (intel_crtc->config->fdi_lanes > 2)
4497 cpt_set_fdi_bc_bifurcation(dev, false);
4498 else
4499 cpt_set_fdi_bc_bifurcation(dev, true);
4500
4501 break;
4502 case PIPE_C:
4503 cpt_set_fdi_bc_bifurcation(dev, true);
4504
4505 break;
4506 default:
4507 BUG();
4508 }
4509 }
4510
4511 /* Return which DP Port should be selected for Transcoder DP control */
4512 static enum port
4513 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4514 {
4515 struct drm_device *dev = crtc->dev;
4516 struct intel_encoder *encoder;
4517
4518 for_each_encoder_on_crtc(dev, crtc, encoder) {
4519 if (encoder->type == INTEL_OUTPUT_DP ||
4520 encoder->type == INTEL_OUTPUT_EDP)
4521 return enc_to_dig_port(&encoder->base)->port;
4522 }
4523
4524 return -1;
4525 }
4526
4527 /*
4528 * Enable PCH resources required for PCH ports:
4529 * - PCH PLLs
4530 * - FDI training & RX/TX
4531 * - update transcoder timings
4532 * - DP transcoding bits
4533 * - transcoder
4534 */
4535 static void ironlake_pch_enable(struct drm_crtc *crtc)
4536 {
4537 struct drm_device *dev = crtc->dev;
4538 struct drm_i915_private *dev_priv = to_i915(dev);
4539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4540 int pipe = intel_crtc->pipe;
4541 u32 temp;
4542
4543 assert_pch_transcoder_disabled(dev_priv, pipe);
4544
4545 if (IS_IVYBRIDGE(dev_priv))
4546 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4547
4548 /* Write the TU size bits before fdi link training, so that error
4549 * detection works. */
4550 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4551 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4552
4553 /* For PCH output, training FDI link */
4554 dev_priv->display.fdi_link_train(crtc);
4555
4556 /* We need to program the right clock selection before writing the pixel
4557 * mutliplier into the DPLL. */
4558 if (HAS_PCH_CPT(dev_priv)) {
4559 u32 sel;
4560
4561 temp = I915_READ(PCH_DPLL_SEL);
4562 temp |= TRANS_DPLL_ENABLE(pipe);
4563 sel = TRANS_DPLLB_SEL(pipe);
4564 if (intel_crtc->config->shared_dpll ==
4565 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4566 temp |= sel;
4567 else
4568 temp &= ~sel;
4569 I915_WRITE(PCH_DPLL_SEL, temp);
4570 }
4571
4572 /* XXX: pch pll's can be enabled any time before we enable the PCH
4573 * transcoder, and we actually should do this to not upset any PCH
4574 * transcoder that already use the clock when we share it.
4575 *
4576 * Note that enable_shared_dpll tries to do the right thing, but
4577 * get_shared_dpll unconditionally resets the pll - we need that to have
4578 * the right LVDS enable sequence. */
4579 intel_enable_shared_dpll(intel_crtc);
4580
4581 /* set transcoder timing, panel must allow it */
4582 assert_panel_unlocked(dev_priv, pipe);
4583 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4584
4585 intel_fdi_normal_train(crtc);
4586
4587 /* For PCH DP, enable TRANS_DP_CTL */
4588 if (HAS_PCH_CPT(dev_priv) &&
4589 intel_crtc_has_dp_encoder(intel_crtc->config)) {
4590 const struct drm_display_mode *adjusted_mode =
4591 &intel_crtc->config->base.adjusted_mode;
4592 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4593 i915_reg_t reg = TRANS_DP_CTL(pipe);
4594 temp = I915_READ(reg);
4595 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4596 TRANS_DP_SYNC_MASK |
4597 TRANS_DP_BPC_MASK);
4598 temp |= TRANS_DP_OUTPUT_ENABLE;
4599 temp |= bpc << 9; /* same format but at 11:9 */
4600
4601 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4602 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4603 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4604 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4605
4606 switch (intel_trans_dp_port_sel(crtc)) {
4607 case PORT_B:
4608 temp |= TRANS_DP_PORT_SEL_B;
4609 break;
4610 case PORT_C:
4611 temp |= TRANS_DP_PORT_SEL_C;
4612 break;
4613 case PORT_D:
4614 temp |= TRANS_DP_PORT_SEL_D;
4615 break;
4616 default:
4617 BUG();
4618 }
4619
4620 I915_WRITE(reg, temp);
4621 }
4622
4623 ironlake_enable_pch_transcoder(dev_priv, pipe);
4624 }
4625
4626 static void lpt_pch_enable(struct drm_crtc *crtc)
4627 {
4628 struct drm_device *dev = crtc->dev;
4629 struct drm_i915_private *dev_priv = to_i915(dev);
4630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4631 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4632
4633 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4634
4635 lpt_program_iclkip(crtc);
4636
4637 /* Set transcoder timing. */
4638 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4639
4640 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4641 }
4642
4643 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4644 {
4645 struct drm_i915_private *dev_priv = to_i915(dev);
4646 i915_reg_t dslreg = PIPEDSL(pipe);
4647 u32 temp;
4648
4649 temp = I915_READ(dslreg);
4650 udelay(500);
4651 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4652 if (wait_for(I915_READ(dslreg) != temp, 5))
4653 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4654 }
4655 }
4656
4657 static int
4658 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4659 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4660 int src_w, int src_h, int dst_w, int dst_h)
4661 {
4662 struct intel_crtc_scaler_state *scaler_state =
4663 &crtc_state->scaler_state;
4664 struct intel_crtc *intel_crtc =
4665 to_intel_crtc(crtc_state->base.crtc);
4666 int need_scaling;
4667
4668 need_scaling = drm_rotation_90_or_270(rotation) ?
4669 (src_h != dst_w || src_w != dst_h):
4670 (src_w != dst_w || src_h != dst_h);
4671
4672 /*
4673 * if plane is being disabled or scaler is no more required or force detach
4674 * - free scaler binded to this plane/crtc
4675 * - in order to do this, update crtc->scaler_usage
4676 *
4677 * Here scaler state in crtc_state is set free so that
4678 * scaler can be assigned to other user. Actual register
4679 * update to free the scaler is done in plane/panel-fit programming.
4680 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4681 */
4682 if (force_detach || !need_scaling) {
4683 if (*scaler_id >= 0) {
4684 scaler_state->scaler_users &= ~(1 << scaler_user);
4685 scaler_state->scalers[*scaler_id].in_use = 0;
4686
4687 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4688 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4689 intel_crtc->pipe, scaler_user, *scaler_id,
4690 scaler_state->scaler_users);
4691 *scaler_id = -1;
4692 }
4693 return 0;
4694 }
4695
4696 /* range checks */
4697 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4698 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4699
4700 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4701 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4702 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4703 "size is out of scaler range\n",
4704 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4705 return -EINVAL;
4706 }
4707
4708 /* mark this plane as a scaler user in crtc_state */
4709 scaler_state->scaler_users |= (1 << scaler_user);
4710 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4711 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4712 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4713 scaler_state->scaler_users);
4714
4715 return 0;
4716 }
4717
4718 /**
4719 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4720 *
4721 * @state: crtc's scaler state
4722 *
4723 * Return
4724 * 0 - scaler_usage updated successfully
4725 * error - requested scaling cannot be supported or other error condition
4726 */
4727 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4728 {
4729 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4730
4731 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4732 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4733 state->pipe_src_w, state->pipe_src_h,
4734 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4735 }
4736
4737 /**
4738 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4739 *
4740 * @state: crtc's scaler state
4741 * @plane_state: atomic plane state to update
4742 *
4743 * Return
4744 * 0 - scaler_usage updated successfully
4745 * error - requested scaling cannot be supported or other error condition
4746 */
4747 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4748 struct intel_plane_state *plane_state)
4749 {
4750
4751 struct intel_plane *intel_plane =
4752 to_intel_plane(plane_state->base.plane);
4753 struct drm_framebuffer *fb = plane_state->base.fb;
4754 int ret;
4755
4756 bool force_detach = !fb || !plane_state->base.visible;
4757
4758 ret = skl_update_scaler(crtc_state, force_detach,
4759 drm_plane_index(&intel_plane->base),
4760 &plane_state->scaler_id,
4761 plane_state->base.rotation,
4762 drm_rect_width(&plane_state->base.src) >> 16,
4763 drm_rect_height(&plane_state->base.src) >> 16,
4764 drm_rect_width(&plane_state->base.dst),
4765 drm_rect_height(&plane_state->base.dst));
4766
4767 if (ret || plane_state->scaler_id < 0)
4768 return ret;
4769
4770 /* check colorkey */
4771 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4772 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4773 intel_plane->base.base.id,
4774 intel_plane->base.name);
4775 return -EINVAL;
4776 }
4777
4778 /* Check src format */
4779 switch (fb->pixel_format) {
4780 case DRM_FORMAT_RGB565:
4781 case DRM_FORMAT_XBGR8888:
4782 case DRM_FORMAT_XRGB8888:
4783 case DRM_FORMAT_ABGR8888:
4784 case DRM_FORMAT_ARGB8888:
4785 case DRM_FORMAT_XRGB2101010:
4786 case DRM_FORMAT_XBGR2101010:
4787 case DRM_FORMAT_YUYV:
4788 case DRM_FORMAT_YVYU:
4789 case DRM_FORMAT_UYVY:
4790 case DRM_FORMAT_VYUY:
4791 break;
4792 default:
4793 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4794 intel_plane->base.base.id, intel_plane->base.name,
4795 fb->base.id, fb->pixel_format);
4796 return -EINVAL;
4797 }
4798
4799 return 0;
4800 }
4801
4802 static void skylake_scaler_disable(struct intel_crtc *crtc)
4803 {
4804 int i;
4805
4806 for (i = 0; i < crtc->num_scalers; i++)
4807 skl_detach_scaler(crtc, i);
4808 }
4809
4810 static void skylake_pfit_enable(struct intel_crtc *crtc)
4811 {
4812 struct drm_device *dev = crtc->base.dev;
4813 struct drm_i915_private *dev_priv = to_i915(dev);
4814 int pipe = crtc->pipe;
4815 struct intel_crtc_scaler_state *scaler_state =
4816 &crtc->config->scaler_state;
4817
4818 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4819
4820 if (crtc->config->pch_pfit.enabled) {
4821 int id;
4822
4823 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4824 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4825 return;
4826 }
4827
4828 id = scaler_state->scaler_id;
4829 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4830 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4831 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4832 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4833
4834 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4835 }
4836 }
4837
4838 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4839 {
4840 struct drm_device *dev = crtc->base.dev;
4841 struct drm_i915_private *dev_priv = to_i915(dev);
4842 int pipe = crtc->pipe;
4843
4844 if (crtc->config->pch_pfit.enabled) {
4845 /* Force use of hard-coded filter coefficients
4846 * as some pre-programmed values are broken,
4847 * e.g. x201.
4848 */
4849 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4850 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4851 PF_PIPE_SEL_IVB(pipe));
4852 else
4853 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4854 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4855 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4856 }
4857 }
4858
4859 void hsw_enable_ips(struct intel_crtc *crtc)
4860 {
4861 struct drm_device *dev = crtc->base.dev;
4862 struct drm_i915_private *dev_priv = to_i915(dev);
4863
4864 if (!crtc->config->ips_enabled)
4865 return;
4866
4867 /*
4868 * We can only enable IPS after we enable a plane and wait for a vblank
4869 * This function is called from post_plane_update, which is run after
4870 * a vblank wait.
4871 */
4872
4873 assert_plane_enabled(dev_priv, crtc->plane);
4874 if (IS_BROADWELL(dev_priv)) {
4875 mutex_lock(&dev_priv->rps.hw_lock);
4876 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4877 mutex_unlock(&dev_priv->rps.hw_lock);
4878 /* Quoting Art Runyan: "its not safe to expect any particular
4879 * value in IPS_CTL bit 31 after enabling IPS through the
4880 * mailbox." Moreover, the mailbox may return a bogus state,
4881 * so we need to just enable it and continue on.
4882 */
4883 } else {
4884 I915_WRITE(IPS_CTL, IPS_ENABLE);
4885 /* The bit only becomes 1 in the next vblank, so this wait here
4886 * is essentially intel_wait_for_vblank. If we don't have this
4887 * and don't wait for vblanks until the end of crtc_enable, then
4888 * the HW state readout code will complain that the expected
4889 * IPS_CTL value is not the one we read. */
4890 if (intel_wait_for_register(dev_priv,
4891 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4892 50))
4893 DRM_ERROR("Timed out waiting for IPS enable\n");
4894 }
4895 }
4896
4897 void hsw_disable_ips(struct intel_crtc *crtc)
4898 {
4899 struct drm_device *dev = crtc->base.dev;
4900 struct drm_i915_private *dev_priv = to_i915(dev);
4901
4902 if (!crtc->config->ips_enabled)
4903 return;
4904
4905 assert_plane_enabled(dev_priv, crtc->plane);
4906 if (IS_BROADWELL(dev_priv)) {
4907 mutex_lock(&dev_priv->rps.hw_lock);
4908 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4909 mutex_unlock(&dev_priv->rps.hw_lock);
4910 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4911 if (intel_wait_for_register(dev_priv,
4912 IPS_CTL, IPS_ENABLE, 0,
4913 42))
4914 DRM_ERROR("Timed out waiting for IPS disable\n");
4915 } else {
4916 I915_WRITE(IPS_CTL, 0);
4917 POSTING_READ(IPS_CTL);
4918 }
4919
4920 /* We need to wait for a vblank before we can disable the plane. */
4921 intel_wait_for_vblank(dev_priv, crtc->pipe);
4922 }
4923
4924 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4925 {
4926 if (intel_crtc->overlay) {
4927 struct drm_device *dev = intel_crtc->base.dev;
4928 struct drm_i915_private *dev_priv = to_i915(dev);
4929
4930 mutex_lock(&dev->struct_mutex);
4931 dev_priv->mm.interruptible = false;
4932 (void) intel_overlay_switch_off(intel_crtc->overlay);
4933 dev_priv->mm.interruptible = true;
4934 mutex_unlock(&dev->struct_mutex);
4935 }
4936
4937 /* Let userspace switch the overlay on again. In most cases userspace
4938 * has to recompute where to put it anyway.
4939 */
4940 }
4941
4942 /**
4943 * intel_post_enable_primary - Perform operations after enabling primary plane
4944 * @crtc: the CRTC whose primary plane was just enabled
4945 *
4946 * Performs potentially sleeping operations that must be done after the primary
4947 * plane is enabled, such as updating FBC and IPS. Note that this may be
4948 * called due to an explicit primary plane update, or due to an implicit
4949 * re-enable that is caused when a sprite plane is updated to no longer
4950 * completely hide the primary plane.
4951 */
4952 static void
4953 intel_post_enable_primary(struct drm_crtc *crtc)
4954 {
4955 struct drm_device *dev = crtc->dev;
4956 struct drm_i915_private *dev_priv = to_i915(dev);
4957 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4958 int pipe = intel_crtc->pipe;
4959
4960 /*
4961 * FIXME IPS should be fine as long as one plane is
4962 * enabled, but in practice it seems to have problems
4963 * when going from primary only to sprite only and vice
4964 * versa.
4965 */
4966 hsw_enable_ips(intel_crtc);
4967
4968 /*
4969 * Gen2 reports pipe underruns whenever all planes are disabled.
4970 * So don't enable underrun reporting before at least some planes
4971 * are enabled.
4972 * FIXME: Need to fix the logic to work when we turn off all planes
4973 * but leave the pipe running.
4974 */
4975 if (IS_GEN2(dev_priv))
4976 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4977
4978 /* Underruns don't always raise interrupts, so check manually. */
4979 intel_check_cpu_fifo_underruns(dev_priv);
4980 intel_check_pch_fifo_underruns(dev_priv);
4981 }
4982
4983 /* FIXME move all this to pre_plane_update() with proper state tracking */
4984 static void
4985 intel_pre_disable_primary(struct drm_crtc *crtc)
4986 {
4987 struct drm_device *dev = crtc->dev;
4988 struct drm_i915_private *dev_priv = to_i915(dev);
4989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4990 int pipe = intel_crtc->pipe;
4991
4992 /*
4993 * Gen2 reports pipe underruns whenever all planes are disabled.
4994 * So diasble underrun reporting before all the planes get disabled.
4995 * FIXME: Need to fix the logic to work when we turn off all planes
4996 * but leave the pipe running.
4997 */
4998 if (IS_GEN2(dev_priv))
4999 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5000
5001 /*
5002 * FIXME IPS should be fine as long as one plane is
5003 * enabled, but in practice it seems to have problems
5004 * when going from primary only to sprite only and vice
5005 * versa.
5006 */
5007 hsw_disable_ips(intel_crtc);
5008 }
5009
5010 /* FIXME get rid of this and use pre_plane_update */
5011 static void
5012 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5013 {
5014 struct drm_device *dev = crtc->dev;
5015 struct drm_i915_private *dev_priv = to_i915(dev);
5016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5017 int pipe = intel_crtc->pipe;
5018
5019 intel_pre_disable_primary(crtc);
5020
5021 /*
5022 * Vblank time updates from the shadow to live plane control register
5023 * are blocked if the memory self-refresh mode is active at that
5024 * moment. So to make sure the plane gets truly disabled, disable
5025 * first the self-refresh mode. The self-refresh enable bit in turn
5026 * will be checked/applied by the HW only at the next frame start
5027 * event which is after the vblank start event, so we need to have a
5028 * wait-for-vblank between disabling the plane and the pipe.
5029 */
5030 if (HAS_GMCH_DISPLAY(dev_priv)) {
5031 intel_set_memory_cxsr(dev_priv, false);
5032 dev_priv->wm.vlv.cxsr = false;
5033 intel_wait_for_vblank(dev_priv, pipe);
5034 }
5035 }
5036
5037 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5038 {
5039 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5040 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5041 struct intel_crtc_state *pipe_config =
5042 to_intel_crtc_state(crtc->base.state);
5043 struct drm_plane *primary = crtc->base.primary;
5044 struct drm_plane_state *old_pri_state =
5045 drm_atomic_get_existing_plane_state(old_state, primary);
5046
5047 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5048
5049 crtc->wm.cxsr_allowed = true;
5050
5051 if (pipe_config->update_wm_post && pipe_config->base.active)
5052 intel_update_watermarks(crtc);
5053
5054 if (old_pri_state) {
5055 struct intel_plane_state *primary_state =
5056 to_intel_plane_state(primary->state);
5057 struct intel_plane_state *old_primary_state =
5058 to_intel_plane_state(old_pri_state);
5059
5060 intel_fbc_post_update(crtc);
5061
5062 if (primary_state->base.visible &&
5063 (needs_modeset(&pipe_config->base) ||
5064 !old_primary_state->base.visible))
5065 intel_post_enable_primary(&crtc->base);
5066 }
5067 }
5068
5069 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
5070 {
5071 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5072 struct drm_device *dev = crtc->base.dev;
5073 struct drm_i915_private *dev_priv = to_i915(dev);
5074 struct intel_crtc_state *pipe_config =
5075 to_intel_crtc_state(crtc->base.state);
5076 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5077 struct drm_plane *primary = crtc->base.primary;
5078 struct drm_plane_state *old_pri_state =
5079 drm_atomic_get_existing_plane_state(old_state, primary);
5080 bool modeset = needs_modeset(&pipe_config->base);
5081 struct intel_atomic_state *old_intel_state =
5082 to_intel_atomic_state(old_state);
5083
5084 if (old_pri_state) {
5085 struct intel_plane_state *primary_state =
5086 to_intel_plane_state(primary->state);
5087 struct intel_plane_state *old_primary_state =
5088 to_intel_plane_state(old_pri_state);
5089
5090 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5091
5092 if (old_primary_state->base.visible &&
5093 (modeset || !primary_state->base.visible))
5094 intel_pre_disable_primary(&crtc->base);
5095 }
5096
5097 if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) {
5098 crtc->wm.cxsr_allowed = false;
5099
5100 /*
5101 * Vblank time updates from the shadow to live plane control register
5102 * are blocked if the memory self-refresh mode is active at that
5103 * moment. So to make sure the plane gets truly disabled, disable
5104 * first the self-refresh mode. The self-refresh enable bit in turn
5105 * will be checked/applied by the HW only at the next frame start
5106 * event which is after the vblank start event, so we need to have a
5107 * wait-for-vblank between disabling the plane and the pipe.
5108 */
5109 if (old_crtc_state->base.active) {
5110 intel_set_memory_cxsr(dev_priv, false);
5111 dev_priv->wm.vlv.cxsr = false;
5112 intel_wait_for_vblank(dev_priv, crtc->pipe);
5113 }
5114 }
5115
5116 /*
5117 * IVB workaround: must disable low power watermarks for at least
5118 * one frame before enabling scaling. LP watermarks can be re-enabled
5119 * when scaling is disabled.
5120 *
5121 * WaCxSRDisabledForSpriteScaling:ivb
5122 */
5123 if (pipe_config->disable_lp_wm) {
5124 ilk_disable_lp_wm(dev);
5125 intel_wait_for_vblank(dev_priv, crtc->pipe);
5126 }
5127
5128 /*
5129 * If we're doing a modeset, we're done. No need to do any pre-vblank
5130 * watermark programming here.
5131 */
5132 if (needs_modeset(&pipe_config->base))
5133 return;
5134
5135 /*
5136 * For platforms that support atomic watermarks, program the
5137 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5138 * will be the intermediate values that are safe for both pre- and
5139 * post- vblank; when vblank happens, the 'active' values will be set
5140 * to the final 'target' values and we'll do this again to get the
5141 * optimal watermarks. For gen9+ platforms, the values we program here
5142 * will be the final target values which will get automatically latched
5143 * at vblank time; no further programming will be necessary.
5144 *
5145 * If a platform hasn't been transitioned to atomic watermarks yet,
5146 * we'll continue to update watermarks the old way, if flags tell
5147 * us to.
5148 */
5149 if (dev_priv->display.initial_watermarks != NULL)
5150 dev_priv->display.initial_watermarks(old_intel_state,
5151 pipe_config);
5152 else if (pipe_config->update_wm_pre)
5153 intel_update_watermarks(crtc);
5154 }
5155
5156 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5157 {
5158 struct drm_device *dev = crtc->dev;
5159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5160 struct drm_plane *p;
5161 int pipe = intel_crtc->pipe;
5162
5163 intel_crtc_dpms_overlay_disable(intel_crtc);
5164
5165 drm_for_each_plane_mask(p, dev, plane_mask)
5166 to_intel_plane(p)->disable_plane(p, crtc);
5167
5168 /*
5169 * FIXME: Once we grow proper nuclear flip support out of this we need
5170 * to compute the mask of flip planes precisely. For the time being
5171 * consider this a flip to a NULL plane.
5172 */
5173 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5174 }
5175
5176 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5177 struct intel_crtc_state *crtc_state,
5178 struct drm_atomic_state *old_state)
5179 {
5180 struct drm_connector_state *old_conn_state;
5181 struct drm_connector *conn;
5182 int i;
5183
5184 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5185 struct drm_connector_state *conn_state = conn->state;
5186 struct intel_encoder *encoder =
5187 to_intel_encoder(conn_state->best_encoder);
5188
5189 if (conn_state->crtc != crtc)
5190 continue;
5191
5192 if (encoder->pre_pll_enable)
5193 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5194 }
5195 }
5196
5197 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5198 struct intel_crtc_state *crtc_state,
5199 struct drm_atomic_state *old_state)
5200 {
5201 struct drm_connector_state *old_conn_state;
5202 struct drm_connector *conn;
5203 int i;
5204
5205 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5206 struct drm_connector_state *conn_state = conn->state;
5207 struct intel_encoder *encoder =
5208 to_intel_encoder(conn_state->best_encoder);
5209
5210 if (conn_state->crtc != crtc)
5211 continue;
5212
5213 if (encoder->pre_enable)
5214 encoder->pre_enable(encoder, crtc_state, conn_state);
5215 }
5216 }
5217
5218 static void intel_encoders_enable(struct drm_crtc *crtc,
5219 struct intel_crtc_state *crtc_state,
5220 struct drm_atomic_state *old_state)
5221 {
5222 struct drm_connector_state *old_conn_state;
5223 struct drm_connector *conn;
5224 int i;
5225
5226 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5227 struct drm_connector_state *conn_state = conn->state;
5228 struct intel_encoder *encoder =
5229 to_intel_encoder(conn_state->best_encoder);
5230
5231 if (conn_state->crtc != crtc)
5232 continue;
5233
5234 encoder->enable(encoder, crtc_state, conn_state);
5235 intel_opregion_notify_encoder(encoder, true);
5236 }
5237 }
5238
5239 static void intel_encoders_disable(struct drm_crtc *crtc,
5240 struct intel_crtc_state *old_crtc_state,
5241 struct drm_atomic_state *old_state)
5242 {
5243 struct drm_connector_state *old_conn_state;
5244 struct drm_connector *conn;
5245 int i;
5246
5247 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5248 struct intel_encoder *encoder =
5249 to_intel_encoder(old_conn_state->best_encoder);
5250
5251 if (old_conn_state->crtc != crtc)
5252 continue;
5253
5254 intel_opregion_notify_encoder(encoder, false);
5255 encoder->disable(encoder, old_crtc_state, old_conn_state);
5256 }
5257 }
5258
5259 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5260 struct intel_crtc_state *old_crtc_state,
5261 struct drm_atomic_state *old_state)
5262 {
5263 struct drm_connector_state *old_conn_state;
5264 struct drm_connector *conn;
5265 int i;
5266
5267 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5268 struct intel_encoder *encoder =
5269 to_intel_encoder(old_conn_state->best_encoder);
5270
5271 if (old_conn_state->crtc != crtc)
5272 continue;
5273
5274 if (encoder->post_disable)
5275 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5276 }
5277 }
5278
5279 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5280 struct intel_crtc_state *old_crtc_state,
5281 struct drm_atomic_state *old_state)
5282 {
5283 struct drm_connector_state *old_conn_state;
5284 struct drm_connector *conn;
5285 int i;
5286
5287 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5288 struct intel_encoder *encoder =
5289 to_intel_encoder(old_conn_state->best_encoder);
5290
5291 if (old_conn_state->crtc != crtc)
5292 continue;
5293
5294 if (encoder->post_pll_disable)
5295 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5296 }
5297 }
5298
5299 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5300 struct drm_atomic_state *old_state)
5301 {
5302 struct drm_crtc *crtc = pipe_config->base.crtc;
5303 struct drm_device *dev = crtc->dev;
5304 struct drm_i915_private *dev_priv = to_i915(dev);
5305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5306 int pipe = intel_crtc->pipe;
5307 struct intel_atomic_state *old_intel_state =
5308 to_intel_atomic_state(old_state);
5309
5310 if (WARN_ON(intel_crtc->active))
5311 return;
5312
5313 /*
5314 * Sometimes spurious CPU pipe underruns happen during FDI
5315 * training, at least with VGA+HDMI cloning. Suppress them.
5316 *
5317 * On ILK we get an occasional spurious CPU pipe underruns
5318 * between eDP port A enable and vdd enable. Also PCH port
5319 * enable seems to result in the occasional CPU pipe underrun.
5320 *
5321 * Spurious PCH underruns also occur during PCH enabling.
5322 */
5323 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5324 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5325 if (intel_crtc->config->has_pch_encoder)
5326 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5327
5328 if (intel_crtc->config->has_pch_encoder)
5329 intel_prepare_shared_dpll(intel_crtc);
5330
5331 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5332 intel_dp_set_m_n(intel_crtc, M1_N1);
5333
5334 intel_set_pipe_timings(intel_crtc);
5335 intel_set_pipe_src_size(intel_crtc);
5336
5337 if (intel_crtc->config->has_pch_encoder) {
5338 intel_cpu_transcoder_set_m_n(intel_crtc,
5339 &intel_crtc->config->fdi_m_n, NULL);
5340 }
5341
5342 ironlake_set_pipeconf(crtc);
5343
5344 intel_crtc->active = true;
5345
5346 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5347
5348 if (intel_crtc->config->has_pch_encoder) {
5349 /* Note: FDI PLL enabling _must_ be done before we enable the
5350 * cpu pipes, hence this is separate from all the other fdi/pch
5351 * enabling. */
5352 ironlake_fdi_pll_enable(intel_crtc);
5353 } else {
5354 assert_fdi_tx_disabled(dev_priv, pipe);
5355 assert_fdi_rx_disabled(dev_priv, pipe);
5356 }
5357
5358 ironlake_pfit_enable(intel_crtc);
5359
5360 /*
5361 * On ILK+ LUT must be loaded before the pipe is running but with
5362 * clocks enabled
5363 */
5364 intel_color_load_luts(&pipe_config->base);
5365
5366 if (dev_priv->display.initial_watermarks != NULL)
5367 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5368 intel_enable_pipe(intel_crtc);
5369
5370 if (intel_crtc->config->has_pch_encoder)
5371 ironlake_pch_enable(crtc);
5372
5373 assert_vblank_disabled(crtc);
5374 drm_crtc_vblank_on(crtc);
5375
5376 intel_encoders_enable(crtc, pipe_config, old_state);
5377
5378 if (HAS_PCH_CPT(dev_priv))
5379 cpt_verify_modeset(dev, intel_crtc->pipe);
5380
5381 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5382 if (intel_crtc->config->has_pch_encoder)
5383 intel_wait_for_vblank(dev_priv, pipe);
5384 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5385 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5386 }
5387
5388 /* IPS only exists on ULT machines and is tied to pipe A. */
5389 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5390 {
5391 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5392 }
5393
5394 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5395 struct drm_atomic_state *old_state)
5396 {
5397 struct drm_crtc *crtc = pipe_config->base.crtc;
5398 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5400 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5401 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5402 struct intel_atomic_state *old_intel_state =
5403 to_intel_atomic_state(old_state);
5404
5405 if (WARN_ON(intel_crtc->active))
5406 return;
5407
5408 if (intel_crtc->config->has_pch_encoder)
5409 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5410 false);
5411
5412 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5413
5414 if (intel_crtc->config->shared_dpll)
5415 intel_enable_shared_dpll(intel_crtc);
5416
5417 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5418 intel_dp_set_m_n(intel_crtc, M1_N1);
5419
5420 if (!transcoder_is_dsi(cpu_transcoder))
5421 intel_set_pipe_timings(intel_crtc);
5422
5423 intel_set_pipe_src_size(intel_crtc);
5424
5425 if (cpu_transcoder != TRANSCODER_EDP &&
5426 !transcoder_is_dsi(cpu_transcoder)) {
5427 I915_WRITE(PIPE_MULT(cpu_transcoder),
5428 intel_crtc->config->pixel_multiplier - 1);
5429 }
5430
5431 if (intel_crtc->config->has_pch_encoder) {
5432 intel_cpu_transcoder_set_m_n(intel_crtc,
5433 &intel_crtc->config->fdi_m_n, NULL);
5434 }
5435
5436 if (!transcoder_is_dsi(cpu_transcoder))
5437 haswell_set_pipeconf(crtc);
5438
5439 haswell_set_pipemisc(crtc);
5440
5441 intel_color_set_csc(&pipe_config->base);
5442
5443 intel_crtc->active = true;
5444
5445 if (intel_crtc->config->has_pch_encoder)
5446 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5447 else
5448 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5449
5450 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5451
5452 if (intel_crtc->config->has_pch_encoder)
5453 dev_priv->display.fdi_link_train(crtc);
5454
5455 if (!transcoder_is_dsi(cpu_transcoder))
5456 intel_ddi_enable_pipe_clock(intel_crtc);
5457
5458 if (INTEL_GEN(dev_priv) >= 9)
5459 skylake_pfit_enable(intel_crtc);
5460 else
5461 ironlake_pfit_enable(intel_crtc);
5462
5463 /*
5464 * On ILK+ LUT must be loaded before the pipe is running but with
5465 * clocks enabled
5466 */
5467 intel_color_load_luts(&pipe_config->base);
5468
5469 intel_ddi_set_pipe_settings(crtc);
5470 if (!transcoder_is_dsi(cpu_transcoder))
5471 intel_ddi_enable_transcoder_func(crtc);
5472
5473 if (dev_priv->display.initial_watermarks != NULL)
5474 dev_priv->display.initial_watermarks(old_intel_state,
5475 pipe_config);
5476 else
5477 intel_update_watermarks(intel_crtc);
5478
5479 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5480 if (!transcoder_is_dsi(cpu_transcoder))
5481 intel_enable_pipe(intel_crtc);
5482
5483 if (intel_crtc->config->has_pch_encoder)
5484 lpt_pch_enable(crtc);
5485
5486 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5487 intel_ddi_set_vc_payload_alloc(crtc, true);
5488
5489 assert_vblank_disabled(crtc);
5490 drm_crtc_vblank_on(crtc);
5491
5492 intel_encoders_enable(crtc, pipe_config, old_state);
5493
5494 if (intel_crtc->config->has_pch_encoder) {
5495 intel_wait_for_vblank(dev_priv, pipe);
5496 intel_wait_for_vblank(dev_priv, pipe);
5497 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5498 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5499 true);
5500 }
5501
5502 /* If we change the relative order between pipe/planes enabling, we need
5503 * to change the workaround. */
5504 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5505 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5506 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5507 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5508 }
5509 }
5510
5511 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5512 {
5513 struct drm_device *dev = crtc->base.dev;
5514 struct drm_i915_private *dev_priv = to_i915(dev);
5515 int pipe = crtc->pipe;
5516
5517 /* To avoid upsetting the power well on haswell only disable the pfit if
5518 * it's in use. The hw state code will make sure we get this right. */
5519 if (force || crtc->config->pch_pfit.enabled) {
5520 I915_WRITE(PF_CTL(pipe), 0);
5521 I915_WRITE(PF_WIN_POS(pipe), 0);
5522 I915_WRITE(PF_WIN_SZ(pipe), 0);
5523 }
5524 }
5525
5526 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5527 struct drm_atomic_state *old_state)
5528 {
5529 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5530 struct drm_device *dev = crtc->dev;
5531 struct drm_i915_private *dev_priv = to_i915(dev);
5532 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5533 int pipe = intel_crtc->pipe;
5534
5535 /*
5536 * Sometimes spurious CPU pipe underruns happen when the
5537 * pipe is already disabled, but FDI RX/TX is still enabled.
5538 * Happens at least with VGA+HDMI cloning. Suppress them.
5539 */
5540 if (intel_crtc->config->has_pch_encoder) {
5541 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5542 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5543 }
5544
5545 intel_encoders_disable(crtc, old_crtc_state, old_state);
5546
5547 drm_crtc_vblank_off(crtc);
5548 assert_vblank_disabled(crtc);
5549
5550 intel_disable_pipe(intel_crtc);
5551
5552 ironlake_pfit_disable(intel_crtc, false);
5553
5554 if (intel_crtc->config->has_pch_encoder)
5555 ironlake_fdi_disable(crtc);
5556
5557 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5558
5559 if (intel_crtc->config->has_pch_encoder) {
5560 ironlake_disable_pch_transcoder(dev_priv, pipe);
5561
5562 if (HAS_PCH_CPT(dev_priv)) {
5563 i915_reg_t reg;
5564 u32 temp;
5565
5566 /* disable TRANS_DP_CTL */
5567 reg = TRANS_DP_CTL(pipe);
5568 temp = I915_READ(reg);
5569 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5570 TRANS_DP_PORT_SEL_MASK);
5571 temp |= TRANS_DP_PORT_SEL_NONE;
5572 I915_WRITE(reg, temp);
5573
5574 /* disable DPLL_SEL */
5575 temp = I915_READ(PCH_DPLL_SEL);
5576 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5577 I915_WRITE(PCH_DPLL_SEL, temp);
5578 }
5579
5580 ironlake_fdi_pll_disable(intel_crtc);
5581 }
5582
5583 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5584 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5585 }
5586
5587 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5588 struct drm_atomic_state *old_state)
5589 {
5590 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5591 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5592 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5593 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5594
5595 if (intel_crtc->config->has_pch_encoder)
5596 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5597 false);
5598
5599 intel_encoders_disable(crtc, old_crtc_state, old_state);
5600
5601 drm_crtc_vblank_off(crtc);
5602 assert_vblank_disabled(crtc);
5603
5604 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5605 if (!transcoder_is_dsi(cpu_transcoder))
5606 intel_disable_pipe(intel_crtc);
5607
5608 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5609 intel_ddi_set_vc_payload_alloc(crtc, false);
5610
5611 if (!transcoder_is_dsi(cpu_transcoder))
5612 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5613
5614 if (INTEL_GEN(dev_priv) >= 9)
5615 skylake_scaler_disable(intel_crtc);
5616 else
5617 ironlake_pfit_disable(intel_crtc, false);
5618
5619 if (!transcoder_is_dsi(cpu_transcoder))
5620 intel_ddi_disable_pipe_clock(intel_crtc);
5621
5622 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5623
5624 if (old_crtc_state->has_pch_encoder)
5625 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5626 true);
5627 }
5628
5629 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5630 {
5631 struct drm_device *dev = crtc->base.dev;
5632 struct drm_i915_private *dev_priv = to_i915(dev);
5633 struct intel_crtc_state *pipe_config = crtc->config;
5634
5635 if (!pipe_config->gmch_pfit.control)
5636 return;
5637
5638 /*
5639 * The panel fitter should only be adjusted whilst the pipe is disabled,
5640 * according to register description and PRM.
5641 */
5642 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5643 assert_pipe_disabled(dev_priv, crtc->pipe);
5644
5645 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5646 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5647
5648 /* Border color in case we don't scale up to the full screen. Black by
5649 * default, change to something else for debugging. */
5650 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5651 }
5652
5653 static enum intel_display_power_domain port_to_power_domain(enum port port)
5654 {
5655 switch (port) {
5656 case PORT_A:
5657 return POWER_DOMAIN_PORT_DDI_A_LANES;
5658 case PORT_B:
5659 return POWER_DOMAIN_PORT_DDI_B_LANES;
5660 case PORT_C:
5661 return POWER_DOMAIN_PORT_DDI_C_LANES;
5662 case PORT_D:
5663 return POWER_DOMAIN_PORT_DDI_D_LANES;
5664 case PORT_E:
5665 return POWER_DOMAIN_PORT_DDI_E_LANES;
5666 default:
5667 MISSING_CASE(port);
5668 return POWER_DOMAIN_PORT_OTHER;
5669 }
5670 }
5671
5672 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5673 {
5674 switch (port) {
5675 case PORT_A:
5676 return POWER_DOMAIN_AUX_A;
5677 case PORT_B:
5678 return POWER_DOMAIN_AUX_B;
5679 case PORT_C:
5680 return POWER_DOMAIN_AUX_C;
5681 case PORT_D:
5682 return POWER_DOMAIN_AUX_D;
5683 case PORT_E:
5684 /* FIXME: Check VBT for actual wiring of PORT E */
5685 return POWER_DOMAIN_AUX_D;
5686 default:
5687 MISSING_CASE(port);
5688 return POWER_DOMAIN_AUX_A;
5689 }
5690 }
5691
5692 enum intel_display_power_domain
5693 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5694 {
5695 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5696 struct intel_digital_port *intel_dig_port;
5697
5698 switch (intel_encoder->type) {
5699 case INTEL_OUTPUT_UNKNOWN:
5700 /* Only DDI platforms should ever use this output type */
5701 WARN_ON_ONCE(!HAS_DDI(dev_priv));
5702 case INTEL_OUTPUT_DP:
5703 case INTEL_OUTPUT_HDMI:
5704 case INTEL_OUTPUT_EDP:
5705 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5706 return port_to_power_domain(intel_dig_port->port);
5707 case INTEL_OUTPUT_DP_MST:
5708 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5709 return port_to_power_domain(intel_dig_port->port);
5710 case INTEL_OUTPUT_ANALOG:
5711 return POWER_DOMAIN_PORT_CRT;
5712 case INTEL_OUTPUT_DSI:
5713 return POWER_DOMAIN_PORT_DSI;
5714 default:
5715 return POWER_DOMAIN_PORT_OTHER;
5716 }
5717 }
5718
5719 enum intel_display_power_domain
5720 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5721 {
5722 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5723 struct intel_digital_port *intel_dig_port;
5724
5725 switch (intel_encoder->type) {
5726 case INTEL_OUTPUT_UNKNOWN:
5727 case INTEL_OUTPUT_HDMI:
5728 /*
5729 * Only DDI platforms should ever use these output types.
5730 * We can get here after the HDMI detect code has already set
5731 * the type of the shared encoder. Since we can't be sure
5732 * what's the status of the given connectors, play safe and
5733 * run the DP detection too.
5734 */
5735 WARN_ON_ONCE(!HAS_DDI(dev_priv));
5736 case INTEL_OUTPUT_DP:
5737 case INTEL_OUTPUT_EDP:
5738 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5739 return port_to_aux_power_domain(intel_dig_port->port);
5740 case INTEL_OUTPUT_DP_MST:
5741 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5742 return port_to_aux_power_domain(intel_dig_port->port);
5743 default:
5744 MISSING_CASE(intel_encoder->type);
5745 return POWER_DOMAIN_AUX_A;
5746 }
5747 }
5748
5749 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5750 struct intel_crtc_state *crtc_state)
5751 {
5752 struct drm_device *dev = crtc->dev;
5753 struct drm_encoder *encoder;
5754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5755 enum pipe pipe = intel_crtc->pipe;
5756 unsigned long mask;
5757 enum transcoder transcoder = crtc_state->cpu_transcoder;
5758
5759 if (!crtc_state->base.active)
5760 return 0;
5761
5762 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5763 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5764 if (crtc_state->pch_pfit.enabled ||
5765 crtc_state->pch_pfit.force_thru)
5766 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5767
5768 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5769 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5770
5771 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5772 }
5773
5774 if (crtc_state->shared_dpll)
5775 mask |= BIT(POWER_DOMAIN_PLLS);
5776
5777 return mask;
5778 }
5779
5780 static unsigned long
5781 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5782 struct intel_crtc_state *crtc_state)
5783 {
5784 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5786 enum intel_display_power_domain domain;
5787 unsigned long domains, new_domains, old_domains;
5788
5789 old_domains = intel_crtc->enabled_power_domains;
5790 intel_crtc->enabled_power_domains = new_domains =
5791 get_crtc_power_domains(crtc, crtc_state);
5792
5793 domains = new_domains & ~old_domains;
5794
5795 for_each_power_domain(domain, domains)
5796 intel_display_power_get(dev_priv, domain);
5797
5798 return old_domains & ~new_domains;
5799 }
5800
5801 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5802 unsigned long domains)
5803 {
5804 enum intel_display_power_domain domain;
5805
5806 for_each_power_domain(domain, domains)
5807 intel_display_power_put(dev_priv, domain);
5808 }
5809
5810 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5811 {
5812 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5813
5814 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5815 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5816 return max_cdclk_freq;
5817 else if (IS_CHERRYVIEW(dev_priv))
5818 return max_cdclk_freq*95/100;
5819 else if (INTEL_INFO(dev_priv)->gen < 4)
5820 return 2*max_cdclk_freq*90/100;
5821 else
5822 return max_cdclk_freq*90/100;
5823 }
5824
5825 static int skl_calc_cdclk(int max_pixclk, int vco);
5826
5827 static void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
5828 {
5829 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5830 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5831 int max_cdclk, vco;
5832
5833 vco = dev_priv->skl_preferred_vco_freq;
5834 WARN_ON(vco != 8100000 && vco != 8640000);
5835
5836 /*
5837 * Use the lower (vco 8640) cdclk values as a
5838 * first guess. skl_calc_cdclk() will correct it
5839 * if the preferred vco is 8100 instead.
5840 */
5841 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5842 max_cdclk = 617143;
5843 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5844 max_cdclk = 540000;
5845 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5846 max_cdclk = 432000;
5847 else
5848 max_cdclk = 308571;
5849
5850 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5851 } else if (IS_BROXTON(dev_priv)) {
5852 dev_priv->max_cdclk_freq = 624000;
5853 } else if (IS_BROADWELL(dev_priv)) {
5854 /*
5855 * FIXME with extra cooling we can allow
5856 * 540 MHz for ULX and 675 Mhz for ULT.
5857 * How can we know if extra cooling is
5858 * available? PCI ID, VTB, something else?
5859 */
5860 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5861 dev_priv->max_cdclk_freq = 450000;
5862 else if (IS_BDW_ULX(dev_priv))
5863 dev_priv->max_cdclk_freq = 450000;
5864 else if (IS_BDW_ULT(dev_priv))
5865 dev_priv->max_cdclk_freq = 540000;
5866 else
5867 dev_priv->max_cdclk_freq = 675000;
5868 } else if (IS_CHERRYVIEW(dev_priv)) {
5869 dev_priv->max_cdclk_freq = 320000;
5870 } else if (IS_VALLEYVIEW(dev_priv)) {
5871 dev_priv->max_cdclk_freq = 400000;
5872 } else {
5873 /* otherwise assume cdclk is fixed */
5874 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5875 }
5876
5877 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5878
5879 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5880 dev_priv->max_cdclk_freq);
5881
5882 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5883 dev_priv->max_dotclk_freq);
5884 }
5885
5886 static void intel_update_cdclk(struct drm_i915_private *dev_priv)
5887 {
5888 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev_priv);
5889
5890 if (INTEL_GEN(dev_priv) >= 9)
5891 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5892 dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5893 dev_priv->cdclk_pll.ref);
5894 else
5895 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5896 dev_priv->cdclk_freq);
5897
5898 /*
5899 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5900 * Programmng [sic] note: bit[9:2] should be programmed to the number
5901 * of cdclk that generates 4MHz reference clock freq which is used to
5902 * generate GMBus clock. This will vary with the cdclk freq.
5903 */
5904 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5905 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5906 }
5907
5908 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5909 static int skl_cdclk_decimal(int cdclk)
5910 {
5911 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5912 }
5913
5914 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5915 {
5916 int ratio;
5917
5918 if (cdclk == dev_priv->cdclk_pll.ref)
5919 return 0;
5920
5921 switch (cdclk) {
5922 default:
5923 MISSING_CASE(cdclk);
5924 case 144000:
5925 case 288000:
5926 case 384000:
5927 case 576000:
5928 ratio = 60;
5929 break;
5930 case 624000:
5931 ratio = 65;
5932 break;
5933 }
5934
5935 return dev_priv->cdclk_pll.ref * ratio;
5936 }
5937
5938 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5939 {
5940 I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5941
5942 /* Timeout 200us */
5943 if (intel_wait_for_register(dev_priv,
5944 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5945 1))
5946 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5947
5948 dev_priv->cdclk_pll.vco = 0;
5949 }
5950
5951 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5952 {
5953 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5954 u32 val;
5955
5956 val = I915_READ(BXT_DE_PLL_CTL);
5957 val &= ~BXT_DE_PLL_RATIO_MASK;
5958 val |= BXT_DE_PLL_RATIO(ratio);
5959 I915_WRITE(BXT_DE_PLL_CTL, val);
5960
5961 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5962
5963 /* Timeout 200us */
5964 if (intel_wait_for_register(dev_priv,
5965 BXT_DE_PLL_ENABLE,
5966 BXT_DE_PLL_LOCK,
5967 BXT_DE_PLL_LOCK,
5968 1))
5969 DRM_ERROR("timeout waiting for DE PLL lock\n");
5970
5971 dev_priv->cdclk_pll.vco = vco;
5972 }
5973
5974 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5975 {
5976 u32 val, divider;
5977 int vco, ret;
5978
5979 vco = bxt_de_pll_vco(dev_priv, cdclk);
5980
5981 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5982
5983 /* cdclk = vco / 2 / div{1,1.5,2,4} */
5984 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5985 case 8:
5986 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5987 break;
5988 case 4:
5989 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5990 break;
5991 case 3:
5992 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5993 break;
5994 case 2:
5995 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5996 break;
5997 default:
5998 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
5999 WARN_ON(vco != 0);
6000
6001 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6002 break;
6003 }
6004
6005 /* Inform power controller of upcoming frequency change */
6006 mutex_lock(&dev_priv->rps.hw_lock);
6007 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6008 0x80000000);
6009 mutex_unlock(&dev_priv->rps.hw_lock);
6010
6011 if (ret) {
6012 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
6013 ret, cdclk);
6014 return;
6015 }
6016
6017 if (dev_priv->cdclk_pll.vco != 0 &&
6018 dev_priv->cdclk_pll.vco != vco)
6019 bxt_de_pll_disable(dev_priv);
6020
6021 if (dev_priv->cdclk_pll.vco != vco)
6022 bxt_de_pll_enable(dev_priv, vco);
6023
6024 val = divider | skl_cdclk_decimal(cdclk);
6025 /*
6026 * FIXME if only the cd2x divider needs changing, it could be done
6027 * without shutting off the pipe (if only one pipe is active).
6028 */
6029 val |= BXT_CDCLK_CD2X_PIPE_NONE;
6030 /*
6031 * Disable SSA Precharge when CD clock frequency < 500 MHz,
6032 * enable otherwise.
6033 */
6034 if (cdclk >= 500000)
6035 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6036 I915_WRITE(CDCLK_CTL, val);
6037
6038 mutex_lock(&dev_priv->rps.hw_lock);
6039 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6040 DIV_ROUND_UP(cdclk, 25000));
6041 mutex_unlock(&dev_priv->rps.hw_lock);
6042
6043 if (ret) {
6044 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
6045 ret, cdclk);
6046 return;
6047 }
6048
6049 intel_update_cdclk(dev_priv);
6050 }
6051
6052 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
6053 {
6054 u32 cdctl, expected;
6055
6056 intel_update_cdclk(dev_priv);
6057
6058 if (dev_priv->cdclk_pll.vco == 0 ||
6059 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6060 goto sanitize;
6061
6062 /* DPLL okay; verify the cdclock
6063 *
6064 * Some BIOS versions leave an incorrect decimal frequency value and
6065 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
6066 * so sanitize this register.
6067 */
6068 cdctl = I915_READ(CDCLK_CTL);
6069 /*
6070 * Let's ignore the pipe field, since BIOS could have configured the
6071 * dividers both synching to an active pipe, or asynchronously
6072 * (PIPE_NONE).
6073 */
6074 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
6075
6076 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
6077 skl_cdclk_decimal(dev_priv->cdclk_freq);
6078 /*
6079 * Disable SSA Precharge when CD clock frequency < 500 MHz,
6080 * enable otherwise.
6081 */
6082 if (dev_priv->cdclk_freq >= 500000)
6083 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6084
6085 if (cdctl == expected)
6086 /* All well; nothing to sanitize */
6087 return;
6088
6089 sanitize:
6090 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6091
6092 /* force cdclk programming */
6093 dev_priv->cdclk_freq = 0;
6094
6095 /* force full PLL disable + enable */
6096 dev_priv->cdclk_pll.vco = -1;
6097 }
6098
6099 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
6100 {
6101 bxt_sanitize_cdclk(dev_priv);
6102
6103 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
6104 return;
6105
6106 /*
6107 * FIXME:
6108 * - The initial CDCLK needs to be read from VBT.
6109 * Need to make this change after VBT has changes for BXT.
6110 */
6111 bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
6112 }
6113
6114 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
6115 {
6116 bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
6117 }
6118
6119 static int skl_calc_cdclk(int max_pixclk, int vco)
6120 {
6121 if (vco == 8640000) {
6122 if (max_pixclk > 540000)
6123 return 617143;
6124 else if (max_pixclk > 432000)
6125 return 540000;
6126 else if (max_pixclk > 308571)
6127 return 432000;
6128 else
6129 return 308571;
6130 } else {
6131 if (max_pixclk > 540000)
6132 return 675000;
6133 else if (max_pixclk > 450000)
6134 return 540000;
6135 else if (max_pixclk > 337500)
6136 return 450000;
6137 else
6138 return 337500;
6139 }
6140 }
6141
6142 static void
6143 skl_dpll0_update(struct drm_i915_private *dev_priv)
6144 {
6145 u32 val;
6146
6147 dev_priv->cdclk_pll.ref = 24000;
6148 dev_priv->cdclk_pll.vco = 0;
6149
6150 val = I915_READ(LCPLL1_CTL);
6151 if ((val & LCPLL_PLL_ENABLE) == 0)
6152 return;
6153
6154 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
6155 return;
6156
6157 val = I915_READ(DPLL_CTRL1);
6158
6159 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
6160 DPLL_CTRL1_SSC(SKL_DPLL0) |
6161 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
6162 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
6163 return;
6164
6165 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
6166 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
6167 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
6168 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
6169 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
6170 dev_priv->cdclk_pll.vco = 8100000;
6171 break;
6172 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
6173 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
6174 dev_priv->cdclk_pll.vco = 8640000;
6175 break;
6176 default:
6177 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6178 break;
6179 }
6180 }
6181
6182 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
6183 {
6184 bool changed = dev_priv->skl_preferred_vco_freq != vco;
6185
6186 dev_priv->skl_preferred_vco_freq = vco;
6187
6188 if (changed)
6189 intel_update_max_cdclk(dev_priv);
6190 }
6191
6192 static void
6193 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
6194 {
6195 int min_cdclk = skl_calc_cdclk(0, vco);
6196 u32 val;
6197
6198 WARN_ON(vco != 8100000 && vco != 8640000);
6199
6200 /* select the minimum CDCLK before enabling DPLL 0 */
6201 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
6202 I915_WRITE(CDCLK_CTL, val);
6203 POSTING_READ(CDCLK_CTL);
6204
6205 /*
6206 * We always enable DPLL0 with the lowest link rate possible, but still
6207 * taking into account the VCO required to operate the eDP panel at the
6208 * desired frequency. The usual DP link rates operate with a VCO of
6209 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
6210 * The modeset code is responsible for the selection of the exact link
6211 * rate later on, with the constraint of choosing a frequency that
6212 * works with vco.
6213 */
6214 val = I915_READ(DPLL_CTRL1);
6215
6216 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
6217 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6218 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
6219 if (vco == 8640000)
6220 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
6221 SKL_DPLL0);
6222 else
6223 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
6224 SKL_DPLL0);
6225
6226 I915_WRITE(DPLL_CTRL1, val);
6227 POSTING_READ(DPLL_CTRL1);
6228
6229 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
6230
6231 if (intel_wait_for_register(dev_priv,
6232 LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
6233 5))
6234 DRM_ERROR("DPLL0 not locked\n");
6235
6236 dev_priv->cdclk_pll.vco = vco;
6237
6238 /* We'll want to keep using the current vco from now on. */
6239 skl_set_preferred_cdclk_vco(dev_priv, vco);
6240 }
6241
6242 static void
6243 skl_dpll0_disable(struct drm_i915_private *dev_priv)
6244 {
6245 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
6246 if (intel_wait_for_register(dev_priv,
6247 LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
6248 1))
6249 DRM_ERROR("Couldn't disable DPLL0\n");
6250
6251 dev_priv->cdclk_pll.vco = 0;
6252 }
6253
6254 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
6255 {
6256 u32 freq_select, pcu_ack;
6257 int ret;
6258
6259 WARN_ON((cdclk == 24000) != (vco == 0));
6260
6261 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
6262
6263 mutex_lock(&dev_priv->rps.hw_lock);
6264 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
6265 SKL_CDCLK_PREPARE_FOR_CHANGE,
6266 SKL_CDCLK_READY_FOR_CHANGE,
6267 SKL_CDCLK_READY_FOR_CHANGE, 3);
6268 mutex_unlock(&dev_priv->rps.hw_lock);
6269 if (ret) {
6270 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
6271 ret);
6272 return;
6273 }
6274
6275 /* set CDCLK_CTL */
6276 switch (cdclk) {
6277 case 450000:
6278 case 432000:
6279 freq_select = CDCLK_FREQ_450_432;
6280 pcu_ack = 1;
6281 break;
6282 case 540000:
6283 freq_select = CDCLK_FREQ_540;
6284 pcu_ack = 2;
6285 break;
6286 case 308571:
6287 case 337500:
6288 default:
6289 freq_select = CDCLK_FREQ_337_308;
6290 pcu_ack = 0;
6291 break;
6292 case 617143:
6293 case 675000:
6294 freq_select = CDCLK_FREQ_675_617;
6295 pcu_ack = 3;
6296 break;
6297 }
6298
6299 if (dev_priv->cdclk_pll.vco != 0 &&
6300 dev_priv->cdclk_pll.vco != vco)
6301 skl_dpll0_disable(dev_priv);
6302
6303 if (dev_priv->cdclk_pll.vco != vco)
6304 skl_dpll0_enable(dev_priv, vco);
6305
6306 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
6307 POSTING_READ(CDCLK_CTL);
6308
6309 /* inform PCU of the change */
6310 mutex_lock(&dev_priv->rps.hw_lock);
6311 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
6312 mutex_unlock(&dev_priv->rps.hw_lock);
6313
6314 intel_update_cdclk(dev_priv);
6315 }
6316
6317 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
6318
6319 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
6320 {
6321 skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
6322 }
6323
6324 void skl_init_cdclk(struct drm_i915_private *dev_priv)
6325 {
6326 int cdclk, vco;
6327
6328 skl_sanitize_cdclk(dev_priv);
6329
6330 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
6331 /*
6332 * Use the current vco as our initial
6333 * guess as to what the preferred vco is.
6334 */
6335 if (dev_priv->skl_preferred_vco_freq == 0)
6336 skl_set_preferred_cdclk_vco(dev_priv,
6337 dev_priv->cdclk_pll.vco);
6338 return;
6339 }
6340
6341 vco = dev_priv->skl_preferred_vco_freq;
6342 if (vco == 0)
6343 vco = 8100000;
6344 cdclk = skl_calc_cdclk(0, vco);
6345
6346 skl_set_cdclk(dev_priv, cdclk, vco);
6347 }
6348
6349 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
6350 {
6351 uint32_t cdctl, expected;
6352
6353 /*
6354 * check if the pre-os intialized the display
6355 * There is SWF18 scratchpad register defined which is set by the
6356 * pre-os which can be used by the OS drivers to check the status
6357 */
6358 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
6359 goto sanitize;
6360
6361 intel_update_cdclk(dev_priv);
6362 /* Is PLL enabled and locked ? */
6363 if (dev_priv->cdclk_pll.vco == 0 ||
6364 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6365 goto sanitize;
6366
6367 /* DPLL okay; verify the cdclock
6368 *
6369 * Noticed in some instances that the freq selection is correct but
6370 * decimal part is programmed wrong from BIOS where pre-os does not
6371 * enable display. Verify the same as well.
6372 */
6373 cdctl = I915_READ(CDCLK_CTL);
6374 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
6375 skl_cdclk_decimal(dev_priv->cdclk_freq);
6376 if (cdctl == expected)
6377 /* All well; nothing to sanitize */
6378 return;
6379
6380 sanitize:
6381 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6382
6383 /* force cdclk programming */
6384 dev_priv->cdclk_freq = 0;
6385 /* force full PLL disable + enable */
6386 dev_priv->cdclk_pll.vco = -1;
6387 }
6388
6389 /* Adjust CDclk dividers to allow high res or save power if possible */
6390 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
6391 {
6392 struct drm_i915_private *dev_priv = to_i915(dev);
6393 u32 val, cmd;
6394
6395 WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv)
6396 != dev_priv->cdclk_freq);
6397
6398 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
6399 cmd = 2;
6400 else if (cdclk == 266667)
6401 cmd = 1;
6402 else
6403 cmd = 0;
6404
6405 mutex_lock(&dev_priv->rps.hw_lock);
6406 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6407 val &= ~DSPFREQGUAR_MASK;
6408 val |= (cmd << DSPFREQGUAR_SHIFT);
6409 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6410 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6411 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
6412 50)) {
6413 DRM_ERROR("timed out waiting for CDclk change\n");
6414 }
6415 mutex_unlock(&dev_priv->rps.hw_lock);
6416
6417 mutex_lock(&dev_priv->sb_lock);
6418
6419 if (cdclk == 400000) {
6420 u32 divider;
6421
6422 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6423
6424 /* adjust cdclk divider */
6425 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6426 val &= ~CCK_FREQUENCY_VALUES;
6427 val |= divider;
6428 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
6429
6430 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
6431 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
6432 50))
6433 DRM_ERROR("timed out waiting for CDclk change\n");
6434 }
6435
6436 /* adjust self-refresh exit latency value */
6437 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
6438 val &= ~0x7f;
6439
6440 /*
6441 * For high bandwidth configs, we set a higher latency in the bunit
6442 * so that the core display fetch happens in time to avoid underruns.
6443 */
6444 if (cdclk == 400000)
6445 val |= 4500 / 250; /* 4.5 usec */
6446 else
6447 val |= 3000 / 250; /* 3.0 usec */
6448 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
6449
6450 mutex_unlock(&dev_priv->sb_lock);
6451
6452 intel_update_cdclk(dev_priv);
6453 }
6454
6455 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
6456 {
6457 struct drm_i915_private *dev_priv = to_i915(dev);
6458 u32 val, cmd;
6459
6460 WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv)
6461 != dev_priv->cdclk_freq);
6462
6463 switch (cdclk) {
6464 case 333333:
6465 case 320000:
6466 case 266667:
6467 case 200000:
6468 break;
6469 default:
6470 MISSING_CASE(cdclk);
6471 return;
6472 }
6473
6474 /*
6475 * Specs are full of misinformation, but testing on actual
6476 * hardware has shown that we just need to write the desired
6477 * CCK divider into the Punit register.
6478 */
6479 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6480
6481 mutex_lock(&dev_priv->rps.hw_lock);
6482 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6483 val &= ~DSPFREQGUAR_MASK_CHV;
6484 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6485 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6486 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6487 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6488 50)) {
6489 DRM_ERROR("timed out waiting for CDclk change\n");
6490 }
6491 mutex_unlock(&dev_priv->rps.hw_lock);
6492
6493 intel_update_cdclk(dev_priv);
6494 }
6495
6496 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6497 int max_pixclk)
6498 {
6499 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6500 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6501
6502 /*
6503 * Really only a few cases to deal with, as only 4 CDclks are supported:
6504 * 200MHz
6505 * 267MHz
6506 * 320/333MHz (depends on HPLL freq)
6507 * 400MHz (VLV only)
6508 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6509 * of the lower bin and adjust if needed.
6510 *
6511 * We seem to get an unstable or solid color picture at 200MHz.
6512 * Not sure what's wrong. For now use 200MHz only when all pipes
6513 * are off.
6514 */
6515 if (!IS_CHERRYVIEW(dev_priv) &&
6516 max_pixclk > freq_320*limit/100)
6517 return 400000;
6518 else if (max_pixclk > 266667*limit/100)
6519 return freq_320;
6520 else if (max_pixclk > 0)
6521 return 266667;
6522 else
6523 return 200000;
6524 }
6525
6526 static int bxt_calc_cdclk(int max_pixclk)
6527 {
6528 if (max_pixclk > 576000)
6529 return 624000;
6530 else if (max_pixclk > 384000)
6531 return 576000;
6532 else if (max_pixclk > 288000)
6533 return 384000;
6534 else if (max_pixclk > 144000)
6535 return 288000;
6536 else
6537 return 144000;
6538 }
6539
6540 /* Compute the max pixel clock for new configuration. */
6541 static int intel_mode_max_pixclk(struct drm_device *dev,
6542 struct drm_atomic_state *state)
6543 {
6544 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6545 struct drm_i915_private *dev_priv = to_i915(dev);
6546 struct drm_crtc *crtc;
6547 struct drm_crtc_state *crtc_state;
6548 unsigned max_pixclk = 0, i;
6549 enum pipe pipe;
6550
6551 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6552 sizeof(intel_state->min_pixclk));
6553
6554 for_each_crtc_in_state(state, crtc, crtc_state, i) {
6555 int pixclk = 0;
6556
6557 if (crtc_state->enable)
6558 pixclk = crtc_state->adjusted_mode.crtc_clock;
6559
6560 intel_state->min_pixclk[i] = pixclk;
6561 }
6562
6563 for_each_pipe(dev_priv, pipe)
6564 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6565
6566 return max_pixclk;
6567 }
6568
6569 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6570 {
6571 struct drm_device *dev = state->dev;
6572 struct drm_i915_private *dev_priv = to_i915(dev);
6573 int max_pixclk = intel_mode_max_pixclk(dev, state);
6574 struct intel_atomic_state *intel_state =
6575 to_intel_atomic_state(state);
6576
6577 intel_state->cdclk = intel_state->dev_cdclk =
6578 valleyview_calc_cdclk(dev_priv, max_pixclk);
6579
6580 if (!intel_state->active_crtcs)
6581 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6582
6583 return 0;
6584 }
6585
6586 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6587 {
6588 int max_pixclk = ilk_max_pixel_rate(state);
6589 struct intel_atomic_state *intel_state =
6590 to_intel_atomic_state(state);
6591
6592 intel_state->cdclk = intel_state->dev_cdclk =
6593 bxt_calc_cdclk(max_pixclk);
6594
6595 if (!intel_state->active_crtcs)
6596 intel_state->dev_cdclk = bxt_calc_cdclk(0);
6597
6598 return 0;
6599 }
6600
6601 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6602 {
6603 unsigned int credits, default_credits;
6604
6605 if (IS_CHERRYVIEW(dev_priv))
6606 default_credits = PFI_CREDIT(12);
6607 else
6608 default_credits = PFI_CREDIT(8);
6609
6610 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6611 /* CHV suggested value is 31 or 63 */
6612 if (IS_CHERRYVIEW(dev_priv))
6613 credits = PFI_CREDIT_63;
6614 else
6615 credits = PFI_CREDIT(15);
6616 } else {
6617 credits = default_credits;
6618 }
6619
6620 /*
6621 * WA - write default credits before re-programming
6622 * FIXME: should we also set the resend bit here?
6623 */
6624 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6625 default_credits);
6626
6627 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6628 credits | PFI_CREDIT_RESEND);
6629
6630 /*
6631 * FIXME is this guaranteed to clear
6632 * immediately or should we poll for it?
6633 */
6634 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6635 }
6636
6637 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6638 {
6639 struct drm_device *dev = old_state->dev;
6640 struct drm_i915_private *dev_priv = to_i915(dev);
6641 struct intel_atomic_state *old_intel_state =
6642 to_intel_atomic_state(old_state);
6643 unsigned req_cdclk = old_intel_state->dev_cdclk;
6644
6645 /*
6646 * FIXME: We can end up here with all power domains off, yet
6647 * with a CDCLK frequency other than the minimum. To account
6648 * for this take the PIPE-A power domain, which covers the HW
6649 * blocks needed for the following programming. This can be
6650 * removed once it's guaranteed that we get here either with
6651 * the minimum CDCLK set, or the required power domains
6652 * enabled.
6653 */
6654 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6655
6656 if (IS_CHERRYVIEW(dev_priv))
6657 cherryview_set_cdclk(dev, req_cdclk);
6658 else
6659 valleyview_set_cdclk(dev, req_cdclk);
6660
6661 vlv_program_pfi_credits(dev_priv);
6662
6663 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6664 }
6665
6666 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6667 struct drm_atomic_state *old_state)
6668 {
6669 struct drm_crtc *crtc = pipe_config->base.crtc;
6670 struct drm_device *dev = crtc->dev;
6671 struct drm_i915_private *dev_priv = to_i915(dev);
6672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6673 int pipe = intel_crtc->pipe;
6674
6675 if (WARN_ON(intel_crtc->active))
6676 return;
6677
6678 if (intel_crtc_has_dp_encoder(intel_crtc->config))
6679 intel_dp_set_m_n(intel_crtc, M1_N1);
6680
6681 intel_set_pipe_timings(intel_crtc);
6682 intel_set_pipe_src_size(intel_crtc);
6683
6684 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
6685 struct drm_i915_private *dev_priv = to_i915(dev);
6686
6687 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6688 I915_WRITE(CHV_CANVAS(pipe), 0);
6689 }
6690
6691 i9xx_set_pipeconf(intel_crtc);
6692
6693 intel_crtc->active = true;
6694
6695 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6696
6697 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6698
6699 if (IS_CHERRYVIEW(dev_priv)) {
6700 chv_prepare_pll(intel_crtc, intel_crtc->config);
6701 chv_enable_pll(intel_crtc, intel_crtc->config);
6702 } else {
6703 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6704 vlv_enable_pll(intel_crtc, intel_crtc->config);
6705 }
6706
6707 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6708
6709 i9xx_pfit_enable(intel_crtc);
6710
6711 intel_color_load_luts(&pipe_config->base);
6712
6713 intel_update_watermarks(intel_crtc);
6714 intel_enable_pipe(intel_crtc);
6715
6716 assert_vblank_disabled(crtc);
6717 drm_crtc_vblank_on(crtc);
6718
6719 intel_encoders_enable(crtc, pipe_config, old_state);
6720 }
6721
6722 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6723 {
6724 struct drm_device *dev = crtc->base.dev;
6725 struct drm_i915_private *dev_priv = to_i915(dev);
6726
6727 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6728 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6729 }
6730
6731 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6732 struct drm_atomic_state *old_state)
6733 {
6734 struct drm_crtc *crtc = pipe_config->base.crtc;
6735 struct drm_device *dev = crtc->dev;
6736 struct drm_i915_private *dev_priv = to_i915(dev);
6737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6738 enum pipe pipe = intel_crtc->pipe;
6739
6740 if (WARN_ON(intel_crtc->active))
6741 return;
6742
6743 i9xx_set_pll_dividers(intel_crtc);
6744
6745 if (intel_crtc_has_dp_encoder(intel_crtc->config))
6746 intel_dp_set_m_n(intel_crtc, M1_N1);
6747
6748 intel_set_pipe_timings(intel_crtc);
6749 intel_set_pipe_src_size(intel_crtc);
6750
6751 i9xx_set_pipeconf(intel_crtc);
6752
6753 intel_crtc->active = true;
6754
6755 if (!IS_GEN2(dev_priv))
6756 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6757
6758 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6759
6760 i9xx_enable_pll(intel_crtc);
6761
6762 i9xx_pfit_enable(intel_crtc);
6763
6764 intel_color_load_luts(&pipe_config->base);
6765
6766 intel_update_watermarks(intel_crtc);
6767 intel_enable_pipe(intel_crtc);
6768
6769 assert_vblank_disabled(crtc);
6770 drm_crtc_vblank_on(crtc);
6771
6772 intel_encoders_enable(crtc, pipe_config, old_state);
6773 }
6774
6775 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6776 {
6777 struct drm_device *dev = crtc->base.dev;
6778 struct drm_i915_private *dev_priv = to_i915(dev);
6779
6780 if (!crtc->config->gmch_pfit.control)
6781 return;
6782
6783 assert_pipe_disabled(dev_priv, crtc->pipe);
6784
6785 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6786 I915_READ(PFIT_CONTROL));
6787 I915_WRITE(PFIT_CONTROL, 0);
6788 }
6789
6790 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6791 struct drm_atomic_state *old_state)
6792 {
6793 struct drm_crtc *crtc = old_crtc_state->base.crtc;
6794 struct drm_device *dev = crtc->dev;
6795 struct drm_i915_private *dev_priv = to_i915(dev);
6796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6797 int pipe = intel_crtc->pipe;
6798
6799 /*
6800 * On gen2 planes are double buffered but the pipe isn't, so we must
6801 * wait for planes to fully turn off before disabling the pipe.
6802 */
6803 if (IS_GEN2(dev_priv))
6804 intel_wait_for_vblank(dev_priv, pipe);
6805
6806 intel_encoders_disable(crtc, old_crtc_state, old_state);
6807
6808 drm_crtc_vblank_off(crtc);
6809 assert_vblank_disabled(crtc);
6810
6811 intel_disable_pipe(intel_crtc);
6812
6813 i9xx_pfit_disable(intel_crtc);
6814
6815 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6816
6817 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6818 if (IS_CHERRYVIEW(dev_priv))
6819 chv_disable_pll(dev_priv, pipe);
6820 else if (IS_VALLEYVIEW(dev_priv))
6821 vlv_disable_pll(dev_priv, pipe);
6822 else
6823 i9xx_disable_pll(intel_crtc);
6824 }
6825
6826 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6827
6828 if (!IS_GEN2(dev_priv))
6829 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6830 }
6831
6832 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6833 {
6834 struct intel_encoder *encoder;
6835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6836 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6837 enum intel_display_power_domain domain;
6838 unsigned long domains;
6839 struct drm_atomic_state *state;
6840 struct intel_crtc_state *crtc_state;
6841 int ret;
6842
6843 if (!intel_crtc->active)
6844 return;
6845
6846 if (to_intel_plane_state(crtc->primary->state)->base.visible) {
6847 WARN_ON(intel_crtc->flip_work);
6848
6849 intel_pre_disable_primary_noatomic(crtc);
6850
6851 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6852 to_intel_plane_state(crtc->primary->state)->base.visible = false;
6853 }
6854
6855 state = drm_atomic_state_alloc(crtc->dev);
6856 if (!state) {
6857 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
6858 crtc->base.id, crtc->name);
6859 return;
6860 }
6861
6862 state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
6863
6864 /* Everything's already locked, -EDEADLK can't happen. */
6865 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6866 ret = drm_atomic_add_affected_connectors(state, crtc);
6867
6868 WARN_ON(IS_ERR(crtc_state) || ret);
6869
6870 dev_priv->display.crtc_disable(crtc_state, state);
6871
6872 drm_atomic_state_put(state);
6873
6874 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6875 crtc->base.id, crtc->name);
6876
6877 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6878 crtc->state->active = false;
6879 intel_crtc->active = false;
6880 crtc->enabled = false;
6881 crtc->state->connector_mask = 0;
6882 crtc->state->encoder_mask = 0;
6883
6884 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6885 encoder->base.crtc = NULL;
6886
6887 intel_fbc_disable(intel_crtc);
6888 intel_update_watermarks(intel_crtc);
6889 intel_disable_shared_dpll(intel_crtc);
6890
6891 domains = intel_crtc->enabled_power_domains;
6892 for_each_power_domain(domain, domains)
6893 intel_display_power_put(dev_priv, domain);
6894 intel_crtc->enabled_power_domains = 0;
6895
6896 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6897 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6898 }
6899
6900 /*
6901 * turn all crtc's off, but do not adjust state
6902 * This has to be paired with a call to intel_modeset_setup_hw_state.
6903 */
6904 int intel_display_suspend(struct drm_device *dev)
6905 {
6906 struct drm_i915_private *dev_priv = to_i915(dev);
6907 struct drm_atomic_state *state;
6908 int ret;
6909
6910 state = drm_atomic_helper_suspend(dev);
6911 ret = PTR_ERR_OR_ZERO(state);
6912 if (ret)
6913 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6914 else
6915 dev_priv->modeset_restore_state = state;
6916 return ret;
6917 }
6918
6919 void intel_encoder_destroy(struct drm_encoder *encoder)
6920 {
6921 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6922
6923 drm_encoder_cleanup(encoder);
6924 kfree(intel_encoder);
6925 }
6926
6927 /* Cross check the actual hw state with our own modeset state tracking (and it's
6928 * internal consistency). */
6929 static void intel_connector_verify_state(struct intel_connector *connector)
6930 {
6931 struct drm_crtc *crtc = connector->base.state->crtc;
6932
6933 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6934 connector->base.base.id,
6935 connector->base.name);
6936
6937 if (connector->get_hw_state(connector)) {
6938 struct intel_encoder *encoder = connector->encoder;
6939 struct drm_connector_state *conn_state = connector->base.state;
6940
6941 I915_STATE_WARN(!crtc,
6942 "connector enabled without attached crtc\n");
6943
6944 if (!crtc)
6945 return;
6946
6947 I915_STATE_WARN(!crtc->state->active,
6948 "connector is active, but attached crtc isn't\n");
6949
6950 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6951 return;
6952
6953 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6954 "atomic encoder doesn't match attached encoder\n");
6955
6956 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6957 "attached encoder crtc differs from connector crtc\n");
6958 } else {
6959 I915_STATE_WARN(crtc && crtc->state->active,
6960 "attached crtc is active, but connector isn't\n");
6961 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6962 "best encoder set without crtc!\n");
6963 }
6964 }
6965
6966 int intel_connector_init(struct intel_connector *connector)
6967 {
6968 drm_atomic_helper_connector_reset(&connector->base);
6969
6970 if (!connector->base.state)
6971 return -ENOMEM;
6972
6973 return 0;
6974 }
6975
6976 struct intel_connector *intel_connector_alloc(void)
6977 {
6978 struct intel_connector *connector;
6979
6980 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6981 if (!connector)
6982 return NULL;
6983
6984 if (intel_connector_init(connector) < 0) {
6985 kfree(connector);
6986 return NULL;
6987 }
6988
6989 return connector;
6990 }
6991
6992 /* Simple connector->get_hw_state implementation for encoders that support only
6993 * one connector and no cloning and hence the encoder state determines the state
6994 * of the connector. */
6995 bool intel_connector_get_hw_state(struct intel_connector *connector)
6996 {
6997 enum pipe pipe = 0;
6998 struct intel_encoder *encoder = connector->encoder;
6999
7000 return encoder->get_hw_state(encoder, &pipe);
7001 }
7002
7003 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7004 {
7005 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
7006 return crtc_state->fdi_lanes;
7007
7008 return 0;
7009 }
7010
7011 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7012 struct intel_crtc_state *pipe_config)
7013 {
7014 struct drm_i915_private *dev_priv = to_i915(dev);
7015 struct drm_atomic_state *state = pipe_config->base.state;
7016 struct intel_crtc *other_crtc;
7017 struct intel_crtc_state *other_crtc_state;
7018
7019 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7020 pipe_name(pipe), pipe_config->fdi_lanes);
7021 if (pipe_config->fdi_lanes > 4) {
7022 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7023 pipe_name(pipe), pipe_config->fdi_lanes);
7024 return -EINVAL;
7025 }
7026
7027 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7028 if (pipe_config->fdi_lanes > 2) {
7029 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7030 pipe_config->fdi_lanes);
7031 return -EINVAL;
7032 } else {
7033 return 0;
7034 }
7035 }
7036
7037 if (INTEL_INFO(dev_priv)->num_pipes == 2)
7038 return 0;
7039
7040 /* Ivybridge 3 pipe is really complicated */
7041 switch (pipe) {
7042 case PIPE_A:
7043 return 0;
7044 case PIPE_B:
7045 if (pipe_config->fdi_lanes <= 2)
7046 return 0;
7047
7048 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
7049 other_crtc_state =
7050 intel_atomic_get_crtc_state(state, other_crtc);
7051 if (IS_ERR(other_crtc_state))
7052 return PTR_ERR(other_crtc_state);
7053
7054 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7055 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7056 pipe_name(pipe), pipe_config->fdi_lanes);
7057 return -EINVAL;
7058 }
7059 return 0;
7060 case PIPE_C:
7061 if (pipe_config->fdi_lanes > 2) {
7062 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7063 pipe_name(pipe), pipe_config->fdi_lanes);
7064 return -EINVAL;
7065 }
7066
7067 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
7068 other_crtc_state =
7069 intel_atomic_get_crtc_state(state, other_crtc);
7070 if (IS_ERR(other_crtc_state))
7071 return PTR_ERR(other_crtc_state);
7072
7073 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7074 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7075 return -EINVAL;
7076 }
7077 return 0;
7078 default:
7079 BUG();
7080 }
7081 }
7082
7083 #define RETRY 1
7084 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
7085 struct intel_crtc_state *pipe_config)
7086 {
7087 struct drm_device *dev = intel_crtc->base.dev;
7088 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7089 int lane, link_bw, fdi_dotclock, ret;
7090 bool needs_recompute = false;
7091
7092 retry:
7093 /* FDI is a binary signal running at ~2.7GHz, encoding
7094 * each output octet as 10 bits. The actual frequency
7095 * is stored as a divider into a 100MHz clock, and the
7096 * mode pixel clock is stored in units of 1KHz.
7097 * Hence the bw of each lane in terms of the mode signal
7098 * is:
7099 */
7100 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
7101
7102 fdi_dotclock = adjusted_mode->crtc_clock;
7103
7104 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7105 pipe_config->pipe_bpp);
7106
7107 pipe_config->fdi_lanes = lane;
7108
7109 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7110 link_bw, &pipe_config->fdi_m_n);
7111
7112 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7113 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7114 pipe_config->pipe_bpp -= 2*3;
7115 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7116 pipe_config->pipe_bpp);
7117 needs_recompute = true;
7118 pipe_config->bw_constrained = true;
7119
7120 goto retry;
7121 }
7122
7123 if (needs_recompute)
7124 return RETRY;
7125
7126 return ret;
7127 }
7128
7129 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
7130 struct intel_crtc_state *pipe_config)
7131 {
7132 if (pipe_config->pipe_bpp > 24)
7133 return false;
7134
7135 /* HSW can handle pixel rate up to cdclk? */
7136 if (IS_HASWELL(dev_priv))
7137 return true;
7138
7139 /*
7140 * We compare against max which means we must take
7141 * the increased cdclk requirement into account when
7142 * calculating the new cdclk.
7143 *
7144 * Should measure whether using a lower cdclk w/o IPS
7145 */
7146 return ilk_pipe_pixel_rate(pipe_config) <=
7147 dev_priv->max_cdclk_freq * 95 / 100;
7148 }
7149
7150 static void hsw_compute_ips_config(struct intel_crtc *crtc,
7151 struct intel_crtc_state *pipe_config)
7152 {
7153 struct drm_device *dev = crtc->base.dev;
7154 struct drm_i915_private *dev_priv = to_i915(dev);
7155
7156 pipe_config->ips_enabled = i915.enable_ips &&
7157 hsw_crtc_supports_ips(crtc) &&
7158 pipe_config_supports_ips(dev_priv, pipe_config);
7159 }
7160
7161 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7162 {
7163 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7164
7165 /* GDG double wide on either pipe, otherwise pipe A only */
7166 return INTEL_INFO(dev_priv)->gen < 4 &&
7167 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7168 }
7169
7170 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7171 struct intel_crtc_state *pipe_config)
7172 {
7173 struct drm_device *dev = crtc->base.dev;
7174 struct drm_i915_private *dev_priv = to_i915(dev);
7175 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7176 int clock_limit = dev_priv->max_dotclk_freq;
7177
7178 if (INTEL_GEN(dev_priv) < 4) {
7179 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7180
7181 /*
7182 * Enable double wide mode when the dot clock
7183 * is > 90% of the (display) core speed.
7184 */
7185 if (intel_crtc_supports_double_wide(crtc) &&
7186 adjusted_mode->crtc_clock > clock_limit) {
7187 clock_limit = dev_priv->max_dotclk_freq;
7188 pipe_config->double_wide = true;
7189 }
7190 }
7191
7192 if (adjusted_mode->crtc_clock > clock_limit) {
7193 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7194 adjusted_mode->crtc_clock, clock_limit,
7195 yesno(pipe_config->double_wide));
7196 return -EINVAL;
7197 }
7198
7199 /*
7200 * Pipe horizontal size must be even in:
7201 * - DVO ganged mode
7202 * - LVDS dual channel mode
7203 * - Double wide pipe
7204 */
7205 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7206 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
7207 pipe_config->pipe_src_w &= ~1;
7208
7209 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7210 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7211 */
7212 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
7213 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7214 return -EINVAL;
7215
7216 if (HAS_IPS(dev_priv))
7217 hsw_compute_ips_config(crtc, pipe_config);
7218
7219 if (pipe_config->has_pch_encoder)
7220 return ironlake_fdi_compute_config(crtc, pipe_config);
7221
7222 return 0;
7223 }
7224
7225 static int skylake_get_display_clock_speed(struct drm_i915_private *dev_priv)
7226 {
7227 u32 cdctl;
7228
7229 skl_dpll0_update(dev_priv);
7230
7231 if (dev_priv->cdclk_pll.vco == 0)
7232 return dev_priv->cdclk_pll.ref;
7233
7234 cdctl = I915_READ(CDCLK_CTL);
7235
7236 if (dev_priv->cdclk_pll.vco == 8640000) {
7237 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7238 case CDCLK_FREQ_450_432:
7239 return 432000;
7240 case CDCLK_FREQ_337_308:
7241 return 308571;
7242 case CDCLK_FREQ_540:
7243 return 540000;
7244 case CDCLK_FREQ_675_617:
7245 return 617143;
7246 default:
7247 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7248 }
7249 } else {
7250 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7251 case CDCLK_FREQ_450_432:
7252 return 450000;
7253 case CDCLK_FREQ_337_308:
7254 return 337500;
7255 case CDCLK_FREQ_540:
7256 return 540000;
7257 case CDCLK_FREQ_675_617:
7258 return 675000;
7259 default:
7260 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7261 }
7262 }
7263
7264 return dev_priv->cdclk_pll.ref;
7265 }
7266
7267 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
7268 {
7269 u32 val;
7270
7271 dev_priv->cdclk_pll.ref = 19200;
7272 dev_priv->cdclk_pll.vco = 0;
7273
7274 val = I915_READ(BXT_DE_PLL_ENABLE);
7275 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
7276 return;
7277
7278 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
7279 return;
7280
7281 val = I915_READ(BXT_DE_PLL_CTL);
7282 dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
7283 dev_priv->cdclk_pll.ref;
7284 }
7285
7286 static int broxton_get_display_clock_speed(struct drm_i915_private *dev_priv)
7287 {
7288 u32 divider;
7289 int div, vco;
7290
7291 bxt_de_pll_update(dev_priv);
7292
7293 vco = dev_priv->cdclk_pll.vco;
7294 if (vco == 0)
7295 return dev_priv->cdclk_pll.ref;
7296
7297 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
7298
7299 switch (divider) {
7300 case BXT_CDCLK_CD2X_DIV_SEL_1:
7301 div = 2;
7302 break;
7303 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
7304 div = 3;
7305 break;
7306 case BXT_CDCLK_CD2X_DIV_SEL_2:
7307 div = 4;
7308 break;
7309 case BXT_CDCLK_CD2X_DIV_SEL_4:
7310 div = 8;
7311 break;
7312 default:
7313 MISSING_CASE(divider);
7314 return dev_priv->cdclk_pll.ref;
7315 }
7316
7317 return DIV_ROUND_CLOSEST(vco, div);
7318 }
7319
7320 static int broadwell_get_display_clock_speed(struct drm_i915_private *dev_priv)
7321 {
7322 uint32_t lcpll = I915_READ(LCPLL_CTL);
7323 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7324
7325 if (lcpll & LCPLL_CD_SOURCE_FCLK)
7326 return 800000;
7327 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7328 return 450000;
7329 else if (freq == LCPLL_CLK_FREQ_450)
7330 return 450000;
7331 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
7332 return 540000;
7333 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
7334 return 337500;
7335 else
7336 return 675000;
7337 }
7338
7339 static int haswell_get_display_clock_speed(struct drm_i915_private *dev_priv)
7340 {
7341 uint32_t lcpll = I915_READ(LCPLL_CTL);
7342 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7343
7344 if (lcpll & LCPLL_CD_SOURCE_FCLK)
7345 return 800000;
7346 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7347 return 450000;
7348 else if (freq == LCPLL_CLK_FREQ_450)
7349 return 450000;
7350 else if (IS_HSW_ULT(dev_priv))
7351 return 337500;
7352 else
7353 return 540000;
7354 }
7355
7356 static int valleyview_get_display_clock_speed(struct drm_i915_private *dev_priv)
7357 {
7358 return vlv_get_cck_clock_hpll(dev_priv, "cdclk",
7359 CCK_DISPLAY_CLOCK_CONTROL);
7360 }
7361
7362 static int ilk_get_display_clock_speed(struct drm_i915_private *dev_priv)
7363 {
7364 return 450000;
7365 }
7366
7367 static int i945_get_display_clock_speed(struct drm_i915_private *dev_priv)
7368 {
7369 return 400000;
7370 }
7371
7372 static int i915_get_display_clock_speed(struct drm_i915_private *dev_priv)
7373 {
7374 return 333333;
7375 }
7376
7377 static int i9xx_misc_get_display_clock_speed(struct drm_i915_private *dev_priv)
7378 {
7379 return 200000;
7380 }
7381
7382 static int pnv_get_display_clock_speed(struct drm_i915_private *dev_priv)
7383 {
7384 struct pci_dev *pdev = dev_priv->drm.pdev;
7385 u16 gcfgc = 0;
7386
7387 pci_read_config_word(pdev, GCFGC, &gcfgc);
7388
7389 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7390 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
7391 return 266667;
7392 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
7393 return 333333;
7394 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
7395 return 444444;
7396 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
7397 return 200000;
7398 default:
7399 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
7400 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
7401 return 133333;
7402 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
7403 return 166667;
7404 }
7405 }
7406
7407 static int i915gm_get_display_clock_speed(struct drm_i915_private *dev_priv)
7408 {
7409 struct pci_dev *pdev = dev_priv->drm.pdev;
7410 u16 gcfgc = 0;
7411
7412 pci_read_config_word(pdev, GCFGC, &gcfgc);
7413
7414 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
7415 return 133333;
7416 else {
7417 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7418 case GC_DISPLAY_CLOCK_333_MHZ:
7419 return 333333;
7420 default:
7421 case GC_DISPLAY_CLOCK_190_200_MHZ:
7422 return 190000;
7423 }
7424 }
7425 }
7426
7427 static int i865_get_display_clock_speed(struct drm_i915_private *dev_priv)
7428 {
7429 return 266667;
7430 }
7431
7432 static int i85x_get_display_clock_speed(struct drm_i915_private *dev_priv)
7433 {
7434 struct pci_dev *pdev = dev_priv->drm.pdev;
7435 u16 hpllcc = 0;
7436
7437 /*
7438 * 852GM/852GMV only supports 133 MHz and the HPLLCC
7439 * encoding is different :(
7440 * FIXME is this the right way to detect 852GM/852GMV?
7441 */
7442 if (pdev->revision == 0x1)
7443 return 133333;
7444
7445 pci_bus_read_config_word(pdev->bus,
7446 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
7447
7448 /* Assume that the hardware is in the high speed state. This
7449 * should be the default.
7450 */
7451 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
7452 case GC_CLOCK_133_200:
7453 case GC_CLOCK_133_200_2:
7454 case GC_CLOCK_100_200:
7455 return 200000;
7456 case GC_CLOCK_166_250:
7457 return 250000;
7458 case GC_CLOCK_100_133:
7459 return 133333;
7460 case GC_CLOCK_133_266:
7461 case GC_CLOCK_133_266_2:
7462 case GC_CLOCK_166_266:
7463 return 266667;
7464 }
7465
7466 /* Shouldn't happen */
7467 return 0;
7468 }
7469
7470 static int i830_get_display_clock_speed(struct drm_i915_private *dev_priv)
7471 {
7472 return 133333;
7473 }
7474
7475 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
7476 {
7477 static const unsigned int blb_vco[8] = {
7478 [0] = 3200000,
7479 [1] = 4000000,
7480 [2] = 5333333,
7481 [3] = 4800000,
7482 [4] = 6400000,
7483 };
7484 static const unsigned int pnv_vco[8] = {
7485 [0] = 3200000,
7486 [1] = 4000000,
7487 [2] = 5333333,
7488 [3] = 4800000,
7489 [4] = 2666667,
7490 };
7491 static const unsigned int cl_vco[8] = {
7492 [0] = 3200000,
7493 [1] = 4000000,
7494 [2] = 5333333,
7495 [3] = 6400000,
7496 [4] = 3333333,
7497 [5] = 3566667,
7498 [6] = 4266667,
7499 };
7500 static const unsigned int elk_vco[8] = {
7501 [0] = 3200000,
7502 [1] = 4000000,
7503 [2] = 5333333,
7504 [3] = 4800000,
7505 };
7506 static const unsigned int ctg_vco[8] = {
7507 [0] = 3200000,
7508 [1] = 4000000,
7509 [2] = 5333333,
7510 [3] = 6400000,
7511 [4] = 2666667,
7512 [5] = 4266667,
7513 };
7514 const unsigned int *vco_table;
7515 unsigned int vco;
7516 uint8_t tmp = 0;
7517
7518 /* FIXME other chipsets? */
7519 if (IS_GM45(dev_priv))
7520 vco_table = ctg_vco;
7521 else if (IS_G4X(dev_priv))
7522 vco_table = elk_vco;
7523 else if (IS_CRESTLINE(dev_priv))
7524 vco_table = cl_vco;
7525 else if (IS_PINEVIEW(dev_priv))
7526 vco_table = pnv_vco;
7527 else if (IS_G33(dev_priv))
7528 vco_table = blb_vco;
7529 else
7530 return 0;
7531
7532 tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
7533
7534 vco = vco_table[tmp & 0x7];
7535 if (vco == 0)
7536 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7537 else
7538 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7539
7540 return vco;
7541 }
7542
7543 static int gm45_get_display_clock_speed(struct drm_i915_private *dev_priv)
7544 {
7545 struct pci_dev *pdev = dev_priv->drm.pdev;
7546 unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7547 uint16_t tmp = 0;
7548
7549 pci_read_config_word(pdev, GCFGC, &tmp);
7550
7551 cdclk_sel = (tmp >> 12) & 0x1;
7552
7553 switch (vco) {
7554 case 2666667:
7555 case 4000000:
7556 case 5333333:
7557 return cdclk_sel ? 333333 : 222222;
7558 case 3200000:
7559 return cdclk_sel ? 320000 : 228571;
7560 default:
7561 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7562 return 222222;
7563 }
7564 }
7565
7566 static int i965gm_get_display_clock_speed(struct drm_i915_private *dev_priv)
7567 {
7568 struct pci_dev *pdev = dev_priv->drm.pdev;
7569 static const uint8_t div_3200[] = { 16, 10, 8 };
7570 static const uint8_t div_4000[] = { 20, 12, 10 };
7571 static const uint8_t div_5333[] = { 24, 16, 14 };
7572 const uint8_t *div_table;
7573 unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7574 uint16_t tmp = 0;
7575
7576 pci_read_config_word(pdev, GCFGC, &tmp);
7577
7578 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7579
7580 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7581 goto fail;
7582
7583 switch (vco) {
7584 case 3200000:
7585 div_table = div_3200;
7586 break;
7587 case 4000000:
7588 div_table = div_4000;
7589 break;
7590 case 5333333:
7591 div_table = div_5333;
7592 break;
7593 default:
7594 goto fail;
7595 }
7596
7597 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7598
7599 fail:
7600 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7601 return 200000;
7602 }
7603
7604 static int g33_get_display_clock_speed(struct drm_i915_private *dev_priv)
7605 {
7606 struct pci_dev *pdev = dev_priv->drm.pdev;
7607 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7608 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7609 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7610 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7611 const uint8_t *div_table;
7612 unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7613 uint16_t tmp = 0;
7614
7615 pci_read_config_word(pdev, GCFGC, &tmp);
7616
7617 cdclk_sel = (tmp >> 4) & 0x7;
7618
7619 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7620 goto fail;
7621
7622 switch (vco) {
7623 case 3200000:
7624 div_table = div_3200;
7625 break;
7626 case 4000000:
7627 div_table = div_4000;
7628 break;
7629 case 4800000:
7630 div_table = div_4800;
7631 break;
7632 case 5333333:
7633 div_table = div_5333;
7634 break;
7635 default:
7636 goto fail;
7637 }
7638
7639 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7640
7641 fail:
7642 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7643 return 190476;
7644 }
7645
7646 static void
7647 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7648 {
7649 while (*num > DATA_LINK_M_N_MASK ||
7650 *den > DATA_LINK_M_N_MASK) {
7651 *num >>= 1;
7652 *den >>= 1;
7653 }
7654 }
7655
7656 static void compute_m_n(unsigned int m, unsigned int n,
7657 uint32_t *ret_m, uint32_t *ret_n)
7658 {
7659 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7660 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7661 intel_reduce_m_n_ratio(ret_m, ret_n);
7662 }
7663
7664 void
7665 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7666 int pixel_clock, int link_clock,
7667 struct intel_link_m_n *m_n)
7668 {
7669 m_n->tu = 64;
7670
7671 compute_m_n(bits_per_pixel * pixel_clock,
7672 link_clock * nlanes * 8,
7673 &m_n->gmch_m, &m_n->gmch_n);
7674
7675 compute_m_n(pixel_clock, link_clock,
7676 &m_n->link_m, &m_n->link_n);
7677 }
7678
7679 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7680 {
7681 if (i915.panel_use_ssc >= 0)
7682 return i915.panel_use_ssc != 0;
7683 return dev_priv->vbt.lvds_use_ssc
7684 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7685 }
7686
7687 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7688 {
7689 return (1 << dpll->n) << 16 | dpll->m2;
7690 }
7691
7692 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7693 {
7694 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7695 }
7696
7697 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7698 struct intel_crtc_state *crtc_state,
7699 struct dpll *reduced_clock)
7700 {
7701 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7702 u32 fp, fp2 = 0;
7703
7704 if (IS_PINEVIEW(dev_priv)) {
7705 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7706 if (reduced_clock)
7707 fp2 = pnv_dpll_compute_fp(reduced_clock);
7708 } else {
7709 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7710 if (reduced_clock)
7711 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7712 }
7713
7714 crtc_state->dpll_hw_state.fp0 = fp;
7715
7716 crtc->lowfreq_avail = false;
7717 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7718 reduced_clock) {
7719 crtc_state->dpll_hw_state.fp1 = fp2;
7720 crtc->lowfreq_avail = true;
7721 } else {
7722 crtc_state->dpll_hw_state.fp1 = fp;
7723 }
7724 }
7725
7726 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7727 pipe)
7728 {
7729 u32 reg_val;
7730
7731 /*
7732 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7733 * and set it to a reasonable value instead.
7734 */
7735 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7736 reg_val &= 0xffffff00;
7737 reg_val |= 0x00000030;
7738 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7739
7740 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7741 reg_val &= 0x8cffffff;
7742 reg_val = 0x8c000000;
7743 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7744
7745 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7746 reg_val &= 0xffffff00;
7747 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7748
7749 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7750 reg_val &= 0x00ffffff;
7751 reg_val |= 0xb0000000;
7752 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7753 }
7754
7755 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7756 struct intel_link_m_n *m_n)
7757 {
7758 struct drm_device *dev = crtc->base.dev;
7759 struct drm_i915_private *dev_priv = to_i915(dev);
7760 int pipe = crtc->pipe;
7761
7762 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7763 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7764 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7765 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7766 }
7767
7768 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7769 struct intel_link_m_n *m_n,
7770 struct intel_link_m_n *m2_n2)
7771 {
7772 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7773 int pipe = crtc->pipe;
7774 enum transcoder transcoder = crtc->config->cpu_transcoder;
7775
7776 if (INTEL_GEN(dev_priv) >= 5) {
7777 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7778 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7779 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7780 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7781 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7782 * for gen < 8) and if DRRS is supported (to make sure the
7783 * registers are not unnecessarily accessed).
7784 */
7785 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
7786 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
7787 I915_WRITE(PIPE_DATA_M2(transcoder),
7788 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7789 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7790 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7791 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7792 }
7793 } else {
7794 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7795 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7796 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7797 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7798 }
7799 }
7800
7801 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7802 {
7803 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7804
7805 if (m_n == M1_N1) {
7806 dp_m_n = &crtc->config->dp_m_n;
7807 dp_m2_n2 = &crtc->config->dp_m2_n2;
7808 } else if (m_n == M2_N2) {
7809
7810 /*
7811 * M2_N2 registers are not supported. Hence m2_n2 divider value
7812 * needs to be programmed into M1_N1.
7813 */
7814 dp_m_n = &crtc->config->dp_m2_n2;
7815 } else {
7816 DRM_ERROR("Unsupported divider value\n");
7817 return;
7818 }
7819
7820 if (crtc->config->has_pch_encoder)
7821 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7822 else
7823 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7824 }
7825
7826 static void vlv_compute_dpll(struct intel_crtc *crtc,
7827 struct intel_crtc_state *pipe_config)
7828 {
7829 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7830 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7831 if (crtc->pipe != PIPE_A)
7832 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7833
7834 /* DPLL not used with DSI, but still need the rest set up */
7835 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7836 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7837 DPLL_EXT_BUFFER_ENABLE_VLV;
7838
7839 pipe_config->dpll_hw_state.dpll_md =
7840 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7841 }
7842
7843 static void chv_compute_dpll(struct intel_crtc *crtc,
7844 struct intel_crtc_state *pipe_config)
7845 {
7846 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7847 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7848 if (crtc->pipe != PIPE_A)
7849 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7850
7851 /* DPLL not used with DSI, but still need the rest set up */
7852 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7853 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7854
7855 pipe_config->dpll_hw_state.dpll_md =
7856 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7857 }
7858
7859 static void vlv_prepare_pll(struct intel_crtc *crtc,
7860 const struct intel_crtc_state *pipe_config)
7861 {
7862 struct drm_device *dev = crtc->base.dev;
7863 struct drm_i915_private *dev_priv = to_i915(dev);
7864 enum pipe pipe = crtc->pipe;
7865 u32 mdiv;
7866 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7867 u32 coreclk, reg_val;
7868
7869 /* Enable Refclk */
7870 I915_WRITE(DPLL(pipe),
7871 pipe_config->dpll_hw_state.dpll &
7872 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7873
7874 /* No need to actually set up the DPLL with DSI */
7875 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7876 return;
7877
7878 mutex_lock(&dev_priv->sb_lock);
7879
7880 bestn = pipe_config->dpll.n;
7881 bestm1 = pipe_config->dpll.m1;
7882 bestm2 = pipe_config->dpll.m2;
7883 bestp1 = pipe_config->dpll.p1;
7884 bestp2 = pipe_config->dpll.p2;
7885
7886 /* See eDP HDMI DPIO driver vbios notes doc */
7887
7888 /* PLL B needs special handling */
7889 if (pipe == PIPE_B)
7890 vlv_pllb_recal_opamp(dev_priv, pipe);
7891
7892 /* Set up Tx target for periodic Rcomp update */
7893 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7894
7895 /* Disable target IRef on PLL */
7896 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7897 reg_val &= 0x00ffffff;
7898 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7899
7900 /* Disable fast lock */
7901 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7902
7903 /* Set idtafcrecal before PLL is enabled */
7904 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7905 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7906 mdiv |= ((bestn << DPIO_N_SHIFT));
7907 mdiv |= (1 << DPIO_K_SHIFT);
7908
7909 /*
7910 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7911 * but we don't support that).
7912 * Note: don't use the DAC post divider as it seems unstable.
7913 */
7914 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7915 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7916
7917 mdiv |= DPIO_ENABLE_CALIBRATION;
7918 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7919
7920 /* Set HBR and RBR LPF coefficients */
7921 if (pipe_config->port_clock == 162000 ||
7922 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
7923 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
7924 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7925 0x009f0003);
7926 else
7927 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7928 0x00d0000f);
7929
7930 if (intel_crtc_has_dp_encoder(pipe_config)) {
7931 /* Use SSC source */
7932 if (pipe == PIPE_A)
7933 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7934 0x0df40000);
7935 else
7936 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7937 0x0df70000);
7938 } else { /* HDMI or VGA */
7939 /* Use bend source */
7940 if (pipe == PIPE_A)
7941 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7942 0x0df70000);
7943 else
7944 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7945 0x0df40000);
7946 }
7947
7948 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7949 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7950 if (intel_crtc_has_dp_encoder(crtc->config))
7951 coreclk |= 0x01000000;
7952 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7953
7954 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7955 mutex_unlock(&dev_priv->sb_lock);
7956 }
7957
7958 static void chv_prepare_pll(struct intel_crtc *crtc,
7959 const struct intel_crtc_state *pipe_config)
7960 {
7961 struct drm_device *dev = crtc->base.dev;
7962 struct drm_i915_private *dev_priv = to_i915(dev);
7963 enum pipe pipe = crtc->pipe;
7964 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7965 u32 loopfilter, tribuf_calcntr;
7966 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7967 u32 dpio_val;
7968 int vco;
7969
7970 /* Enable Refclk and SSC */
7971 I915_WRITE(DPLL(pipe),
7972 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7973
7974 /* No need to actually set up the DPLL with DSI */
7975 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7976 return;
7977
7978 bestn = pipe_config->dpll.n;
7979 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7980 bestm1 = pipe_config->dpll.m1;
7981 bestm2 = pipe_config->dpll.m2 >> 22;
7982 bestp1 = pipe_config->dpll.p1;
7983 bestp2 = pipe_config->dpll.p2;
7984 vco = pipe_config->dpll.vco;
7985 dpio_val = 0;
7986 loopfilter = 0;
7987
7988 mutex_lock(&dev_priv->sb_lock);
7989
7990 /* p1 and p2 divider */
7991 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7992 5 << DPIO_CHV_S1_DIV_SHIFT |
7993 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7994 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7995 1 << DPIO_CHV_K_DIV_SHIFT);
7996
7997 /* Feedback post-divider - m2 */
7998 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7999
8000 /* Feedback refclk divider - n and m1 */
8001 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8002 DPIO_CHV_M1_DIV_BY_2 |
8003 1 << DPIO_CHV_N_DIV_SHIFT);
8004
8005 /* M2 fraction division */
8006 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8007
8008 /* M2 fraction division enable */
8009 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8010 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8011 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8012 if (bestm2_frac)
8013 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8014 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8015
8016 /* Program digital lock detect threshold */
8017 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8018 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8019 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8020 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8021 if (!bestm2_frac)
8022 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8023 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8024
8025 /* Loop filter */
8026 if (vco == 5400000) {
8027 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8028 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8029 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8030 tribuf_calcntr = 0x9;
8031 } else if (vco <= 6200000) {
8032 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8033 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8034 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8035 tribuf_calcntr = 0x9;
8036 } else if (vco <= 6480000) {
8037 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8038 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8039 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8040 tribuf_calcntr = 0x8;
8041 } else {
8042 /* Not supported. Apply the same limits as in the max case */
8043 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8044 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8045 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8046 tribuf_calcntr = 0;
8047 }
8048 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8049
8050 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8051 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8052 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8053 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8054
8055 /* AFC Recal */
8056 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8057 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8058 DPIO_AFC_RECAL);
8059
8060 mutex_unlock(&dev_priv->sb_lock);
8061 }
8062
8063 /**
8064 * vlv_force_pll_on - forcibly enable just the PLL
8065 * @dev_priv: i915 private structure
8066 * @pipe: pipe PLL to enable
8067 * @dpll: PLL configuration
8068 *
8069 * Enable the PLL for @pipe using the supplied @dpll config. To be used
8070 * in cases where we need the PLL enabled even when @pipe is not going to
8071 * be enabled.
8072 */
8073 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
8074 const struct dpll *dpll)
8075 {
8076 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
8077 struct intel_crtc_state *pipe_config;
8078
8079 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8080 if (!pipe_config)
8081 return -ENOMEM;
8082
8083 pipe_config->base.crtc = &crtc->base;
8084 pipe_config->pixel_multiplier = 1;
8085 pipe_config->dpll = *dpll;
8086
8087 if (IS_CHERRYVIEW(dev_priv)) {
8088 chv_compute_dpll(crtc, pipe_config);
8089 chv_prepare_pll(crtc, pipe_config);
8090 chv_enable_pll(crtc, pipe_config);
8091 } else {
8092 vlv_compute_dpll(crtc, pipe_config);
8093 vlv_prepare_pll(crtc, pipe_config);
8094 vlv_enable_pll(crtc, pipe_config);
8095 }
8096
8097 kfree(pipe_config);
8098
8099 return 0;
8100 }
8101
8102 /**
8103 * vlv_force_pll_off - forcibly disable just the PLL
8104 * @dev_priv: i915 private structure
8105 * @pipe: pipe PLL to disable
8106 *
8107 * Disable the PLL for @pipe. To be used in cases where we need
8108 * the PLL enabled even when @pipe is not going to be enabled.
8109 */
8110 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
8111 {
8112 if (IS_CHERRYVIEW(dev_priv))
8113 chv_disable_pll(dev_priv, pipe);
8114 else
8115 vlv_disable_pll(dev_priv, pipe);
8116 }
8117
8118 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8119 struct intel_crtc_state *crtc_state,
8120 struct dpll *reduced_clock)
8121 {
8122 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8123 u32 dpll;
8124 struct dpll *clock = &crtc_state->dpll;
8125
8126 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8127
8128 dpll = DPLL_VGA_MODE_DIS;
8129
8130 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8131 dpll |= DPLLB_MODE_LVDS;
8132 else
8133 dpll |= DPLLB_MODE_DAC_SERIAL;
8134
8135 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || IS_G33(dev_priv)) {
8136 dpll |= (crtc_state->pixel_multiplier - 1)
8137 << SDVO_MULTIPLIER_SHIFT_HIRES;
8138 }
8139
8140 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8141 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8142 dpll |= DPLL_SDVO_HIGH_SPEED;
8143
8144 if (intel_crtc_has_dp_encoder(crtc_state))
8145 dpll |= DPLL_SDVO_HIGH_SPEED;
8146
8147 /* compute bitmask from p1 value */
8148 if (IS_PINEVIEW(dev_priv))
8149 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8150 else {
8151 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8152 if (IS_G4X(dev_priv) && reduced_clock)
8153 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8154 }
8155 switch (clock->p2) {
8156 case 5:
8157 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8158 break;
8159 case 7:
8160 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8161 break;
8162 case 10:
8163 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8164 break;
8165 case 14:
8166 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8167 break;
8168 }
8169 if (INTEL_GEN(dev_priv) >= 4)
8170 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8171
8172 if (crtc_state->sdvo_tv_clock)
8173 dpll |= PLL_REF_INPUT_TVCLKINBC;
8174 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8175 intel_panel_use_ssc(dev_priv))
8176 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8177 else
8178 dpll |= PLL_REF_INPUT_DREFCLK;
8179
8180 dpll |= DPLL_VCO_ENABLE;
8181 crtc_state->dpll_hw_state.dpll = dpll;
8182
8183 if (INTEL_GEN(dev_priv) >= 4) {
8184 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8185 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8186 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8187 }
8188 }
8189
8190 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8191 struct intel_crtc_state *crtc_state,
8192 struct dpll *reduced_clock)
8193 {
8194 struct drm_device *dev = crtc->base.dev;
8195 struct drm_i915_private *dev_priv = to_i915(dev);
8196 u32 dpll;
8197 struct dpll *clock = &crtc_state->dpll;
8198
8199 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8200
8201 dpll = DPLL_VGA_MODE_DIS;
8202
8203 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8204 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8205 } else {
8206 if (clock->p1 == 2)
8207 dpll |= PLL_P1_DIVIDE_BY_TWO;
8208 else
8209 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8210 if (clock->p2 == 4)
8211 dpll |= PLL_P2_DIVIDE_BY_4;
8212 }
8213
8214 if (!IS_I830(dev_priv) &&
8215 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8216 dpll |= DPLL_DVO_2X_MODE;
8217
8218 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8219 intel_panel_use_ssc(dev_priv))
8220 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8221 else
8222 dpll |= PLL_REF_INPUT_DREFCLK;
8223
8224 dpll |= DPLL_VCO_ENABLE;
8225 crtc_state->dpll_hw_state.dpll = dpll;
8226 }
8227
8228 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
8229 {
8230 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
8231 enum pipe pipe = intel_crtc->pipe;
8232 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8233 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
8234 uint32_t crtc_vtotal, crtc_vblank_end;
8235 int vsyncshift = 0;
8236
8237 /* We need to be careful not to changed the adjusted mode, for otherwise
8238 * the hw state checker will get angry at the mismatch. */
8239 crtc_vtotal = adjusted_mode->crtc_vtotal;
8240 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8241
8242 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8243 /* the chip adds 2 halflines automatically */
8244 crtc_vtotal -= 1;
8245 crtc_vblank_end -= 1;
8246
8247 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8248 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8249 else
8250 vsyncshift = adjusted_mode->crtc_hsync_start -
8251 adjusted_mode->crtc_htotal / 2;
8252 if (vsyncshift < 0)
8253 vsyncshift += adjusted_mode->crtc_htotal;
8254 }
8255
8256 if (INTEL_GEN(dev_priv) > 3)
8257 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8258
8259 I915_WRITE(HTOTAL(cpu_transcoder),
8260 (adjusted_mode->crtc_hdisplay - 1) |
8261 ((adjusted_mode->crtc_htotal - 1) << 16));
8262 I915_WRITE(HBLANK(cpu_transcoder),
8263 (adjusted_mode->crtc_hblank_start - 1) |
8264 ((adjusted_mode->crtc_hblank_end - 1) << 16));
8265 I915_WRITE(HSYNC(cpu_transcoder),
8266 (adjusted_mode->crtc_hsync_start - 1) |
8267 ((adjusted_mode->crtc_hsync_end - 1) << 16));
8268
8269 I915_WRITE(VTOTAL(cpu_transcoder),
8270 (adjusted_mode->crtc_vdisplay - 1) |
8271 ((crtc_vtotal - 1) << 16));
8272 I915_WRITE(VBLANK(cpu_transcoder),
8273 (adjusted_mode->crtc_vblank_start - 1) |
8274 ((crtc_vblank_end - 1) << 16));
8275 I915_WRITE(VSYNC(cpu_transcoder),
8276 (adjusted_mode->crtc_vsync_start - 1) |
8277 ((adjusted_mode->crtc_vsync_end - 1) << 16));
8278
8279 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8280 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8281 * documented on the DDI_FUNC_CTL register description, EDP Input Select
8282 * bits. */
8283 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8284 (pipe == PIPE_B || pipe == PIPE_C))
8285 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8286
8287 }
8288
8289 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
8290 {
8291 struct drm_device *dev = intel_crtc->base.dev;
8292 struct drm_i915_private *dev_priv = to_i915(dev);
8293 enum pipe pipe = intel_crtc->pipe;
8294
8295 /* pipesrc controls the size that is scaled from, which should
8296 * always be the user's requested size.
8297 */
8298 I915_WRITE(PIPESRC(pipe),
8299 ((intel_crtc->config->pipe_src_w - 1) << 16) |
8300 (intel_crtc->config->pipe_src_h - 1));
8301 }
8302
8303 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8304 struct intel_crtc_state *pipe_config)
8305 {
8306 struct drm_device *dev = crtc->base.dev;
8307 struct drm_i915_private *dev_priv = to_i915(dev);
8308 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8309 uint32_t tmp;
8310
8311 tmp = I915_READ(HTOTAL(cpu_transcoder));
8312 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8313 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8314 tmp = I915_READ(HBLANK(cpu_transcoder));
8315 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
8316 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
8317 tmp = I915_READ(HSYNC(cpu_transcoder));
8318 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8319 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8320
8321 tmp = I915_READ(VTOTAL(cpu_transcoder));
8322 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8323 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8324 tmp = I915_READ(VBLANK(cpu_transcoder));
8325 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
8326 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
8327 tmp = I915_READ(VSYNC(cpu_transcoder));
8328 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8329 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8330
8331 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
8332 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8333 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
8334 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
8335 }
8336 }
8337
8338 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8339 struct intel_crtc_state *pipe_config)
8340 {
8341 struct drm_device *dev = crtc->base.dev;
8342 struct drm_i915_private *dev_priv = to_i915(dev);
8343 u32 tmp;
8344
8345 tmp = I915_READ(PIPESRC(crtc->pipe));
8346 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8347 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8348
8349 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
8350 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
8351 }
8352
8353 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8354 struct intel_crtc_state *pipe_config)
8355 {
8356 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
8357 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
8358 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
8359 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
8360
8361 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
8362 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
8363 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
8364 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
8365
8366 mode->flags = pipe_config->base.adjusted_mode.flags;
8367 mode->type = DRM_MODE_TYPE_DRIVER;
8368
8369 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
8370 mode->flags |= pipe_config->base.adjusted_mode.flags;
8371
8372 mode->hsync = drm_mode_hsync(mode);
8373 mode->vrefresh = drm_mode_vrefresh(mode);
8374 drm_mode_set_name(mode);
8375 }
8376
8377 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
8378 {
8379 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
8380 uint32_t pipeconf;
8381
8382 pipeconf = 0;
8383
8384 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
8385 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8386 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
8387
8388 if (intel_crtc->config->double_wide)
8389 pipeconf |= PIPECONF_DOUBLE_WIDE;
8390
8391 /* only g4x and later have fancy bpc/dither controls */
8392 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8393 IS_CHERRYVIEW(dev_priv)) {
8394 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8395 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
8396 pipeconf |= PIPECONF_DITHER_EN |
8397 PIPECONF_DITHER_TYPE_SP;
8398
8399 switch (intel_crtc->config->pipe_bpp) {
8400 case 18:
8401 pipeconf |= PIPECONF_6BPC;
8402 break;
8403 case 24:
8404 pipeconf |= PIPECONF_8BPC;
8405 break;
8406 case 30:
8407 pipeconf |= PIPECONF_10BPC;
8408 break;
8409 default:
8410 /* Case prevented by intel_choose_pipe_bpp_dither. */
8411 BUG();
8412 }
8413 }
8414
8415 if (HAS_PIPE_CXSR(dev_priv)) {
8416 if (intel_crtc->lowfreq_avail) {
8417 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
8418 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
8419 } else {
8420 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
8421 }
8422 }
8423
8424 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8425 if (INTEL_GEN(dev_priv) < 4 ||
8426 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8427 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8428 else
8429 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8430 } else
8431 pipeconf |= PIPECONF_PROGRESSIVE;
8432
8433 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8434 intel_crtc->config->limited_color_range)
8435 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8436
8437 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
8438 POSTING_READ(PIPECONF(intel_crtc->pipe));
8439 }
8440
8441 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8442 struct intel_crtc_state *crtc_state)
8443 {
8444 struct drm_device *dev = crtc->base.dev;
8445 struct drm_i915_private *dev_priv = to_i915(dev);
8446 const struct intel_limit *limit;
8447 int refclk = 48000;
8448
8449 memset(&crtc_state->dpll_hw_state, 0,
8450 sizeof(crtc_state->dpll_hw_state));
8451
8452 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8453 if (intel_panel_use_ssc(dev_priv)) {
8454 refclk = dev_priv->vbt.lvds_ssc_freq;
8455 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8456 }
8457
8458 limit = &intel_limits_i8xx_lvds;
8459 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8460 limit = &intel_limits_i8xx_dvo;
8461 } else {
8462 limit = &intel_limits_i8xx_dac;
8463 }
8464
8465 if (!crtc_state->clock_set &&
8466 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8467 refclk, NULL, &crtc_state->dpll)) {
8468 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8469 return -EINVAL;
8470 }
8471
8472 i8xx_compute_dpll(crtc, crtc_state, NULL);
8473
8474 return 0;
8475 }
8476
8477 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8478 struct intel_crtc_state *crtc_state)
8479 {
8480 struct drm_device *dev = crtc->base.dev;
8481 struct drm_i915_private *dev_priv = to_i915(dev);
8482 const struct intel_limit *limit;
8483 int refclk = 96000;
8484
8485 memset(&crtc_state->dpll_hw_state, 0,
8486 sizeof(crtc_state->dpll_hw_state));
8487
8488 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8489 if (intel_panel_use_ssc(dev_priv)) {
8490 refclk = dev_priv->vbt.lvds_ssc_freq;
8491 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8492 }
8493
8494 if (intel_is_dual_link_lvds(dev))
8495 limit = &intel_limits_g4x_dual_channel_lvds;
8496 else
8497 limit = &intel_limits_g4x_single_channel_lvds;
8498 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8499 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8500 limit = &intel_limits_g4x_hdmi;
8501 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8502 limit = &intel_limits_g4x_sdvo;
8503 } else {
8504 /* The option is for other outputs */
8505 limit = &intel_limits_i9xx_sdvo;
8506 }
8507
8508 if (!crtc_state->clock_set &&
8509 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8510 refclk, NULL, &crtc_state->dpll)) {
8511 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8512 return -EINVAL;
8513 }
8514
8515 i9xx_compute_dpll(crtc, crtc_state, NULL);
8516
8517 return 0;
8518 }
8519
8520 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8521 struct intel_crtc_state *crtc_state)
8522 {
8523 struct drm_device *dev = crtc->base.dev;
8524 struct drm_i915_private *dev_priv = to_i915(dev);
8525 const struct intel_limit *limit;
8526 int refclk = 96000;
8527
8528 memset(&crtc_state->dpll_hw_state, 0,
8529 sizeof(crtc_state->dpll_hw_state));
8530
8531 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8532 if (intel_panel_use_ssc(dev_priv)) {
8533 refclk = dev_priv->vbt.lvds_ssc_freq;
8534 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8535 }
8536
8537 limit = &intel_limits_pineview_lvds;
8538 } else {
8539 limit = &intel_limits_pineview_sdvo;
8540 }
8541
8542 if (!crtc_state->clock_set &&
8543 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8544 refclk, NULL, &crtc_state->dpll)) {
8545 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8546 return -EINVAL;
8547 }
8548
8549 i9xx_compute_dpll(crtc, crtc_state, NULL);
8550
8551 return 0;
8552 }
8553
8554 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8555 struct intel_crtc_state *crtc_state)
8556 {
8557 struct drm_device *dev = crtc->base.dev;
8558 struct drm_i915_private *dev_priv = to_i915(dev);
8559 const struct intel_limit *limit;
8560 int refclk = 96000;
8561
8562 memset(&crtc_state->dpll_hw_state, 0,
8563 sizeof(crtc_state->dpll_hw_state));
8564
8565 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8566 if (intel_panel_use_ssc(dev_priv)) {
8567 refclk = dev_priv->vbt.lvds_ssc_freq;
8568 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8569 }
8570
8571 limit = &intel_limits_i9xx_lvds;
8572 } else {
8573 limit = &intel_limits_i9xx_sdvo;
8574 }
8575
8576 if (!crtc_state->clock_set &&
8577 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8578 refclk, NULL, &crtc_state->dpll)) {
8579 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8580 return -EINVAL;
8581 }
8582
8583 i9xx_compute_dpll(crtc, crtc_state, NULL);
8584
8585 return 0;
8586 }
8587
8588 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8589 struct intel_crtc_state *crtc_state)
8590 {
8591 int refclk = 100000;
8592 const struct intel_limit *limit = &intel_limits_chv;
8593
8594 memset(&crtc_state->dpll_hw_state, 0,
8595 sizeof(crtc_state->dpll_hw_state));
8596
8597 if (!crtc_state->clock_set &&
8598 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8599 refclk, NULL, &crtc_state->dpll)) {
8600 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8601 return -EINVAL;
8602 }
8603
8604 chv_compute_dpll(crtc, crtc_state);
8605
8606 return 0;
8607 }
8608
8609 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8610 struct intel_crtc_state *crtc_state)
8611 {
8612 int refclk = 100000;
8613 const struct intel_limit *limit = &intel_limits_vlv;
8614
8615 memset(&crtc_state->dpll_hw_state, 0,
8616 sizeof(crtc_state->dpll_hw_state));
8617
8618 if (!crtc_state->clock_set &&
8619 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8620 refclk, NULL, &crtc_state->dpll)) {
8621 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8622 return -EINVAL;
8623 }
8624
8625 vlv_compute_dpll(crtc, crtc_state);
8626
8627 return 0;
8628 }
8629
8630 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8631 struct intel_crtc_state *pipe_config)
8632 {
8633 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8634 uint32_t tmp;
8635
8636 if (INTEL_GEN(dev_priv) <= 3 &&
8637 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
8638 return;
8639
8640 tmp = I915_READ(PFIT_CONTROL);
8641 if (!(tmp & PFIT_ENABLE))
8642 return;
8643
8644 /* Check whether the pfit is attached to our pipe. */
8645 if (INTEL_GEN(dev_priv) < 4) {
8646 if (crtc->pipe != PIPE_B)
8647 return;
8648 } else {
8649 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8650 return;
8651 }
8652
8653 pipe_config->gmch_pfit.control = tmp;
8654 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8655 }
8656
8657 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8658 struct intel_crtc_state *pipe_config)
8659 {
8660 struct drm_device *dev = crtc->base.dev;
8661 struct drm_i915_private *dev_priv = to_i915(dev);
8662 int pipe = pipe_config->cpu_transcoder;
8663 struct dpll clock;
8664 u32 mdiv;
8665 int refclk = 100000;
8666
8667 /* In case of DSI, DPLL will not be used */
8668 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8669 return;
8670
8671 mutex_lock(&dev_priv->sb_lock);
8672 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8673 mutex_unlock(&dev_priv->sb_lock);
8674
8675 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8676 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8677 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8678 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8679 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8680
8681 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8682 }
8683
8684 static void
8685 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8686 struct intel_initial_plane_config *plane_config)
8687 {
8688 struct drm_device *dev = crtc->base.dev;
8689 struct drm_i915_private *dev_priv = to_i915(dev);
8690 u32 val, base, offset;
8691 int pipe = crtc->pipe, plane = crtc->plane;
8692 int fourcc, pixel_format;
8693 unsigned int aligned_height;
8694 struct drm_framebuffer *fb;
8695 struct intel_framebuffer *intel_fb;
8696
8697 val = I915_READ(DSPCNTR(plane));
8698 if (!(val & DISPLAY_PLANE_ENABLE))
8699 return;
8700
8701 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8702 if (!intel_fb) {
8703 DRM_DEBUG_KMS("failed to alloc fb\n");
8704 return;
8705 }
8706
8707 fb = &intel_fb->base;
8708
8709 if (INTEL_GEN(dev_priv) >= 4) {
8710 if (val & DISPPLANE_TILED) {
8711 plane_config->tiling = I915_TILING_X;
8712 fb->modifier = I915_FORMAT_MOD_X_TILED;
8713 }
8714 }
8715
8716 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8717 fourcc = i9xx_format_to_fourcc(pixel_format);
8718 fb->pixel_format = fourcc;
8719 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8720
8721 if (INTEL_GEN(dev_priv) >= 4) {
8722 if (plane_config->tiling)
8723 offset = I915_READ(DSPTILEOFF(plane));
8724 else
8725 offset = I915_READ(DSPLINOFF(plane));
8726 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8727 } else {
8728 base = I915_READ(DSPADDR(plane));
8729 }
8730 plane_config->base = base;
8731
8732 val = I915_READ(PIPESRC(pipe));
8733 fb->width = ((val >> 16) & 0xfff) + 1;
8734 fb->height = ((val >> 0) & 0xfff) + 1;
8735
8736 val = I915_READ(DSPSTRIDE(pipe));
8737 fb->pitches[0] = val & 0xffffffc0;
8738
8739 aligned_height = intel_fb_align_height(dev, fb->height,
8740 fb->pixel_format,
8741 fb->modifier);
8742
8743 plane_config->size = fb->pitches[0] * aligned_height;
8744
8745 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8746 pipe_name(pipe), plane, fb->width, fb->height,
8747 fb->bits_per_pixel, base, fb->pitches[0],
8748 plane_config->size);
8749
8750 plane_config->fb = intel_fb;
8751 }
8752
8753 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8754 struct intel_crtc_state *pipe_config)
8755 {
8756 struct drm_device *dev = crtc->base.dev;
8757 struct drm_i915_private *dev_priv = to_i915(dev);
8758 int pipe = pipe_config->cpu_transcoder;
8759 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8760 struct dpll clock;
8761 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8762 int refclk = 100000;
8763
8764 /* In case of DSI, DPLL will not be used */
8765 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8766 return;
8767
8768 mutex_lock(&dev_priv->sb_lock);
8769 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8770 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8771 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8772 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8773 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8774 mutex_unlock(&dev_priv->sb_lock);
8775
8776 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8777 clock.m2 = (pll_dw0 & 0xff) << 22;
8778 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8779 clock.m2 |= pll_dw2 & 0x3fffff;
8780 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8781 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8782 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8783
8784 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8785 }
8786
8787 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8788 struct intel_crtc_state *pipe_config)
8789 {
8790 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8791 enum intel_display_power_domain power_domain;
8792 uint32_t tmp;
8793 bool ret;
8794
8795 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8796 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8797 return false;
8798
8799 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8800 pipe_config->shared_dpll = NULL;
8801
8802 ret = false;
8803
8804 tmp = I915_READ(PIPECONF(crtc->pipe));
8805 if (!(tmp & PIPECONF_ENABLE))
8806 goto out;
8807
8808 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8809 IS_CHERRYVIEW(dev_priv)) {
8810 switch (tmp & PIPECONF_BPC_MASK) {
8811 case PIPECONF_6BPC:
8812 pipe_config->pipe_bpp = 18;
8813 break;
8814 case PIPECONF_8BPC:
8815 pipe_config->pipe_bpp = 24;
8816 break;
8817 case PIPECONF_10BPC:
8818 pipe_config->pipe_bpp = 30;
8819 break;
8820 default:
8821 break;
8822 }
8823 }
8824
8825 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8826 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8827 pipe_config->limited_color_range = true;
8828
8829 if (INTEL_GEN(dev_priv) < 4)
8830 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8831
8832 intel_get_pipe_timings(crtc, pipe_config);
8833 intel_get_pipe_src_size(crtc, pipe_config);
8834
8835 i9xx_get_pfit_config(crtc, pipe_config);
8836
8837 if (INTEL_GEN(dev_priv) >= 4) {
8838 /* No way to read it out on pipes B and C */
8839 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
8840 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8841 else
8842 tmp = I915_READ(DPLL_MD(crtc->pipe));
8843 pipe_config->pixel_multiplier =
8844 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8845 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8846 pipe_config->dpll_hw_state.dpll_md = tmp;
8847 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8848 IS_G33(dev_priv)) {
8849 tmp = I915_READ(DPLL(crtc->pipe));
8850 pipe_config->pixel_multiplier =
8851 ((tmp & SDVO_MULTIPLIER_MASK)
8852 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8853 } else {
8854 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8855 * port and will be fixed up in the encoder->get_config
8856 * function. */
8857 pipe_config->pixel_multiplier = 1;
8858 }
8859 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8860 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
8861 /*
8862 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8863 * on 830. Filter it out here so that we don't
8864 * report errors due to that.
8865 */
8866 if (IS_I830(dev_priv))
8867 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8868
8869 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8870 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8871 } else {
8872 /* Mask out read-only status bits. */
8873 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8874 DPLL_PORTC_READY_MASK |
8875 DPLL_PORTB_READY_MASK);
8876 }
8877
8878 if (IS_CHERRYVIEW(dev_priv))
8879 chv_crtc_clock_get(crtc, pipe_config);
8880 else if (IS_VALLEYVIEW(dev_priv))
8881 vlv_crtc_clock_get(crtc, pipe_config);
8882 else
8883 i9xx_crtc_clock_get(crtc, pipe_config);
8884
8885 /*
8886 * Normally the dotclock is filled in by the encoder .get_config()
8887 * but in case the pipe is enabled w/o any ports we need a sane
8888 * default.
8889 */
8890 pipe_config->base.adjusted_mode.crtc_clock =
8891 pipe_config->port_clock / pipe_config->pixel_multiplier;
8892
8893 ret = true;
8894
8895 out:
8896 intel_display_power_put(dev_priv, power_domain);
8897
8898 return ret;
8899 }
8900
8901 static void ironlake_init_pch_refclk(struct drm_device *dev)
8902 {
8903 struct drm_i915_private *dev_priv = to_i915(dev);
8904 struct intel_encoder *encoder;
8905 int i;
8906 u32 val, final;
8907 bool has_lvds = false;
8908 bool has_cpu_edp = false;
8909 bool has_panel = false;
8910 bool has_ck505 = false;
8911 bool can_ssc = false;
8912 bool using_ssc_source = false;
8913
8914 /* We need to take the global config into account */
8915 for_each_intel_encoder(dev, encoder) {
8916 switch (encoder->type) {
8917 case INTEL_OUTPUT_LVDS:
8918 has_panel = true;
8919 has_lvds = true;
8920 break;
8921 case INTEL_OUTPUT_EDP:
8922 has_panel = true;
8923 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8924 has_cpu_edp = true;
8925 break;
8926 default:
8927 break;
8928 }
8929 }
8930
8931 if (HAS_PCH_IBX(dev_priv)) {
8932 has_ck505 = dev_priv->vbt.display_clock_mode;
8933 can_ssc = has_ck505;
8934 } else {
8935 has_ck505 = false;
8936 can_ssc = true;
8937 }
8938
8939 /* Check if any DPLLs are using the SSC source */
8940 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8941 u32 temp = I915_READ(PCH_DPLL(i));
8942
8943 if (!(temp & DPLL_VCO_ENABLE))
8944 continue;
8945
8946 if ((temp & PLL_REF_INPUT_MASK) ==
8947 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8948 using_ssc_source = true;
8949 break;
8950 }
8951 }
8952
8953 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8954 has_panel, has_lvds, has_ck505, using_ssc_source);
8955
8956 /* Ironlake: try to setup display ref clock before DPLL
8957 * enabling. This is only under driver's control after
8958 * PCH B stepping, previous chipset stepping should be
8959 * ignoring this setting.
8960 */
8961 val = I915_READ(PCH_DREF_CONTROL);
8962
8963 /* As we must carefully and slowly disable/enable each source in turn,
8964 * compute the final state we want first and check if we need to
8965 * make any changes at all.
8966 */
8967 final = val;
8968 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8969 if (has_ck505)
8970 final |= DREF_NONSPREAD_CK505_ENABLE;
8971 else
8972 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8973
8974 final &= ~DREF_SSC_SOURCE_MASK;
8975 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8976 final &= ~DREF_SSC1_ENABLE;
8977
8978 if (has_panel) {
8979 final |= DREF_SSC_SOURCE_ENABLE;
8980
8981 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8982 final |= DREF_SSC1_ENABLE;
8983
8984 if (has_cpu_edp) {
8985 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8986 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8987 else
8988 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8989 } else
8990 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8991 } else if (using_ssc_source) {
8992 final |= DREF_SSC_SOURCE_ENABLE;
8993 final |= DREF_SSC1_ENABLE;
8994 }
8995
8996 if (final == val)
8997 return;
8998
8999 /* Always enable nonspread source */
9000 val &= ~DREF_NONSPREAD_SOURCE_MASK;
9001
9002 if (has_ck505)
9003 val |= DREF_NONSPREAD_CK505_ENABLE;
9004 else
9005 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9006
9007 if (has_panel) {
9008 val &= ~DREF_SSC_SOURCE_MASK;
9009 val |= DREF_SSC_SOURCE_ENABLE;
9010
9011 /* SSC must be turned on before enabling the CPU output */
9012 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9013 DRM_DEBUG_KMS("Using SSC on panel\n");
9014 val |= DREF_SSC1_ENABLE;
9015 } else
9016 val &= ~DREF_SSC1_ENABLE;
9017
9018 /* Get SSC going before enabling the outputs */
9019 I915_WRITE(PCH_DREF_CONTROL, val);
9020 POSTING_READ(PCH_DREF_CONTROL);
9021 udelay(200);
9022
9023 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9024
9025 /* Enable CPU source on CPU attached eDP */
9026 if (has_cpu_edp) {
9027 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9028 DRM_DEBUG_KMS("Using SSC on eDP\n");
9029 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9030 } else
9031 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9032 } else
9033 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9034
9035 I915_WRITE(PCH_DREF_CONTROL, val);
9036 POSTING_READ(PCH_DREF_CONTROL);
9037 udelay(200);
9038 } else {
9039 DRM_DEBUG_KMS("Disabling CPU source output\n");
9040
9041 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9042
9043 /* Turn off CPU output */
9044 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9045
9046 I915_WRITE(PCH_DREF_CONTROL, val);
9047 POSTING_READ(PCH_DREF_CONTROL);
9048 udelay(200);
9049
9050 if (!using_ssc_source) {
9051 DRM_DEBUG_KMS("Disabling SSC source\n");
9052
9053 /* Turn off the SSC source */
9054 val &= ~DREF_SSC_SOURCE_MASK;
9055 val |= DREF_SSC_SOURCE_DISABLE;
9056
9057 /* Turn off SSC1 */
9058 val &= ~DREF_SSC1_ENABLE;
9059
9060 I915_WRITE(PCH_DREF_CONTROL, val);
9061 POSTING_READ(PCH_DREF_CONTROL);
9062 udelay(200);
9063 }
9064 }
9065
9066 BUG_ON(val != final);
9067 }
9068
9069 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9070 {
9071 uint32_t tmp;
9072
9073 tmp = I915_READ(SOUTH_CHICKEN2);
9074 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9075 I915_WRITE(SOUTH_CHICKEN2, tmp);
9076
9077 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
9078 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9079 DRM_ERROR("FDI mPHY reset assert timeout\n");
9080
9081 tmp = I915_READ(SOUTH_CHICKEN2);
9082 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9083 I915_WRITE(SOUTH_CHICKEN2, tmp);
9084
9085 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
9086 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9087 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9088 }
9089
9090 /* WaMPhyProgramming:hsw */
9091 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9092 {
9093 uint32_t tmp;
9094
9095 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9096 tmp &= ~(0xFF << 24);
9097 tmp |= (0x12 << 24);
9098 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9099
9100 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9101 tmp |= (1 << 11);
9102 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9103
9104 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9105 tmp |= (1 << 11);
9106 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9107
9108 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9109 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9110 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9111
9112 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9113 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9114 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9115
9116 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9117 tmp &= ~(7 << 13);
9118 tmp |= (5 << 13);
9119 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9120
9121 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9122 tmp &= ~(7 << 13);
9123 tmp |= (5 << 13);
9124 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9125
9126 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9127 tmp &= ~0xFF;
9128 tmp |= 0x1C;
9129 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9130
9131 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9132 tmp &= ~0xFF;
9133 tmp |= 0x1C;
9134 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9135
9136 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9137 tmp &= ~(0xFF << 16);
9138 tmp |= (0x1C << 16);
9139 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9140
9141 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9142 tmp &= ~(0xFF << 16);
9143 tmp |= (0x1C << 16);
9144 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9145
9146 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9147 tmp |= (1 << 27);
9148 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9149
9150 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9151 tmp |= (1 << 27);
9152 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9153
9154 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9155 tmp &= ~(0xF << 28);
9156 tmp |= (4 << 28);
9157 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9158
9159 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9160 tmp &= ~(0xF << 28);
9161 tmp |= (4 << 28);
9162 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9163 }
9164
9165 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9166 * Programming" based on the parameters passed:
9167 * - Sequence to enable CLKOUT_DP
9168 * - Sequence to enable CLKOUT_DP without spread
9169 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9170 */
9171 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
9172 bool with_fdi)
9173 {
9174 struct drm_i915_private *dev_priv = to_i915(dev);
9175 uint32_t reg, tmp;
9176
9177 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9178 with_spread = true;
9179 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
9180 with_fdi, "LP PCH doesn't have FDI\n"))
9181 with_fdi = false;
9182
9183 mutex_lock(&dev_priv->sb_lock);
9184
9185 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9186 tmp &= ~SBI_SSCCTL_DISABLE;
9187 tmp |= SBI_SSCCTL_PATHALT;
9188 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9189
9190 udelay(24);
9191
9192 if (with_spread) {
9193 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9194 tmp &= ~SBI_SSCCTL_PATHALT;
9195 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9196
9197 if (with_fdi) {
9198 lpt_reset_fdi_mphy(dev_priv);
9199 lpt_program_fdi_mphy(dev_priv);
9200 }
9201 }
9202
9203 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9204 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9205 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9206 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9207
9208 mutex_unlock(&dev_priv->sb_lock);
9209 }
9210
9211 /* Sequence to disable CLKOUT_DP */
9212 static void lpt_disable_clkout_dp(struct drm_device *dev)
9213 {
9214 struct drm_i915_private *dev_priv = to_i915(dev);
9215 uint32_t reg, tmp;
9216
9217 mutex_lock(&dev_priv->sb_lock);
9218
9219 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9220 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9221 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9222 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9223
9224 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9225 if (!(tmp & SBI_SSCCTL_DISABLE)) {
9226 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9227 tmp |= SBI_SSCCTL_PATHALT;
9228 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9229 udelay(32);
9230 }
9231 tmp |= SBI_SSCCTL_DISABLE;
9232 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9233 }
9234
9235 mutex_unlock(&dev_priv->sb_lock);
9236 }
9237
9238 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9239
9240 static const uint16_t sscdivintphase[] = {
9241 [BEND_IDX( 50)] = 0x3B23,
9242 [BEND_IDX( 45)] = 0x3B23,
9243 [BEND_IDX( 40)] = 0x3C23,
9244 [BEND_IDX( 35)] = 0x3C23,
9245 [BEND_IDX( 30)] = 0x3D23,
9246 [BEND_IDX( 25)] = 0x3D23,
9247 [BEND_IDX( 20)] = 0x3E23,
9248 [BEND_IDX( 15)] = 0x3E23,
9249 [BEND_IDX( 10)] = 0x3F23,
9250 [BEND_IDX( 5)] = 0x3F23,
9251 [BEND_IDX( 0)] = 0x0025,
9252 [BEND_IDX( -5)] = 0x0025,
9253 [BEND_IDX(-10)] = 0x0125,
9254 [BEND_IDX(-15)] = 0x0125,
9255 [BEND_IDX(-20)] = 0x0225,
9256 [BEND_IDX(-25)] = 0x0225,
9257 [BEND_IDX(-30)] = 0x0325,
9258 [BEND_IDX(-35)] = 0x0325,
9259 [BEND_IDX(-40)] = 0x0425,
9260 [BEND_IDX(-45)] = 0x0425,
9261 [BEND_IDX(-50)] = 0x0525,
9262 };
9263
9264 /*
9265 * Bend CLKOUT_DP
9266 * steps -50 to 50 inclusive, in steps of 5
9267 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9268 * change in clock period = -(steps / 10) * 5.787 ps
9269 */
9270 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9271 {
9272 uint32_t tmp;
9273 int idx = BEND_IDX(steps);
9274
9275 if (WARN_ON(steps % 5 != 0))
9276 return;
9277
9278 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9279 return;
9280
9281 mutex_lock(&dev_priv->sb_lock);
9282
9283 if (steps % 10 != 0)
9284 tmp = 0xAAAAAAAB;
9285 else
9286 tmp = 0x00000000;
9287 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9288
9289 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9290 tmp &= 0xffff0000;
9291 tmp |= sscdivintphase[idx];
9292 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9293
9294 mutex_unlock(&dev_priv->sb_lock);
9295 }
9296
9297 #undef BEND_IDX
9298
9299 static void lpt_init_pch_refclk(struct drm_device *dev)
9300 {
9301 struct intel_encoder *encoder;
9302 bool has_vga = false;
9303
9304 for_each_intel_encoder(dev, encoder) {
9305 switch (encoder->type) {
9306 case INTEL_OUTPUT_ANALOG:
9307 has_vga = true;
9308 break;
9309 default:
9310 break;
9311 }
9312 }
9313
9314 if (has_vga) {
9315 lpt_bend_clkout_dp(to_i915(dev), 0);
9316 lpt_enable_clkout_dp(dev, true, true);
9317 } else {
9318 lpt_disable_clkout_dp(dev);
9319 }
9320 }
9321
9322 /*
9323 * Initialize reference clocks when the driver loads
9324 */
9325 void intel_init_pch_refclk(struct drm_device *dev)
9326 {
9327 struct drm_i915_private *dev_priv = to_i915(dev);
9328
9329 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
9330 ironlake_init_pch_refclk(dev);
9331 else if (HAS_PCH_LPT(dev_priv))
9332 lpt_init_pch_refclk(dev);
9333 }
9334
9335 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
9336 {
9337 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9338 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9339 int pipe = intel_crtc->pipe;
9340 uint32_t val;
9341
9342 val = 0;
9343
9344 switch (intel_crtc->config->pipe_bpp) {
9345 case 18:
9346 val |= PIPECONF_6BPC;
9347 break;
9348 case 24:
9349 val |= PIPECONF_8BPC;
9350 break;
9351 case 30:
9352 val |= PIPECONF_10BPC;
9353 break;
9354 case 36:
9355 val |= PIPECONF_12BPC;
9356 break;
9357 default:
9358 /* Case prevented by intel_choose_pipe_bpp_dither. */
9359 BUG();
9360 }
9361
9362 if (intel_crtc->config->dither)
9363 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9364
9365 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9366 val |= PIPECONF_INTERLACED_ILK;
9367 else
9368 val |= PIPECONF_PROGRESSIVE;
9369
9370 if (intel_crtc->config->limited_color_range)
9371 val |= PIPECONF_COLOR_RANGE_SELECT;
9372
9373 I915_WRITE(PIPECONF(pipe), val);
9374 POSTING_READ(PIPECONF(pipe));
9375 }
9376
9377 static void haswell_set_pipeconf(struct drm_crtc *crtc)
9378 {
9379 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9380 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9381 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9382 u32 val = 0;
9383
9384 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
9385 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9386
9387 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9388 val |= PIPECONF_INTERLACED_ILK;
9389 else
9390 val |= PIPECONF_PROGRESSIVE;
9391
9392 I915_WRITE(PIPECONF(cpu_transcoder), val);
9393 POSTING_READ(PIPECONF(cpu_transcoder));
9394 }
9395
9396 static void haswell_set_pipemisc(struct drm_crtc *crtc)
9397 {
9398 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9400
9401 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
9402 u32 val = 0;
9403
9404 switch (intel_crtc->config->pipe_bpp) {
9405 case 18:
9406 val |= PIPEMISC_DITHER_6_BPC;
9407 break;
9408 case 24:
9409 val |= PIPEMISC_DITHER_8_BPC;
9410 break;
9411 case 30:
9412 val |= PIPEMISC_DITHER_10_BPC;
9413 break;
9414 case 36:
9415 val |= PIPEMISC_DITHER_12_BPC;
9416 break;
9417 default:
9418 /* Case prevented by pipe_config_set_bpp. */
9419 BUG();
9420 }
9421
9422 if (intel_crtc->config->dither)
9423 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9424
9425 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
9426 }
9427 }
9428
9429 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9430 {
9431 /*
9432 * Account for spread spectrum to avoid
9433 * oversubscribing the link. Max center spread
9434 * is 2.5%; use 5% for safety's sake.
9435 */
9436 u32 bps = target_clock * bpp * 21 / 20;
9437 return DIV_ROUND_UP(bps, link_bw * 8);
9438 }
9439
9440 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9441 {
9442 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9443 }
9444
9445 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
9446 struct intel_crtc_state *crtc_state,
9447 struct dpll *reduced_clock)
9448 {
9449 struct drm_crtc *crtc = &intel_crtc->base;
9450 struct drm_device *dev = crtc->dev;
9451 struct drm_i915_private *dev_priv = to_i915(dev);
9452 u32 dpll, fp, fp2;
9453 int factor;
9454
9455 /* Enable autotuning of the PLL clock (if permissible) */
9456 factor = 21;
9457 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9458 if ((intel_panel_use_ssc(dev_priv) &&
9459 dev_priv->vbt.lvds_ssc_freq == 100000) ||
9460 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
9461 factor = 25;
9462 } else if (crtc_state->sdvo_tv_clock)
9463 factor = 20;
9464
9465 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9466
9467 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9468 fp |= FP_CB_TUNE;
9469
9470 if (reduced_clock) {
9471 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9472
9473 if (reduced_clock->m < factor * reduced_clock->n)
9474 fp2 |= FP_CB_TUNE;
9475 } else {
9476 fp2 = fp;
9477 }
9478
9479 dpll = 0;
9480
9481 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9482 dpll |= DPLLB_MODE_LVDS;
9483 else
9484 dpll |= DPLLB_MODE_DAC_SERIAL;
9485
9486 dpll |= (crtc_state->pixel_multiplier - 1)
9487 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9488
9489 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9490 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9491 dpll |= DPLL_SDVO_HIGH_SPEED;
9492
9493 if (intel_crtc_has_dp_encoder(crtc_state))
9494 dpll |= DPLL_SDVO_HIGH_SPEED;
9495
9496 /*
9497 * The high speed IO clock is only really required for
9498 * SDVO/HDMI/DP, but we also enable it for CRT to make it
9499 * possible to share the DPLL between CRT and HDMI. Enabling
9500 * the clock needlessly does no real harm, except use up a
9501 * bit of power potentially.
9502 *
9503 * We'll limit this to IVB with 3 pipes, since it has only two
9504 * DPLLs and so DPLL sharing is the only way to get three pipes
9505 * driving PCH ports at the same time. On SNB we could do this,
9506 * and potentially avoid enabling the second DPLL, but it's not
9507 * clear if it''s a win or loss power wise. No point in doing
9508 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9509 */
9510 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
9511 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
9512 dpll |= DPLL_SDVO_HIGH_SPEED;
9513
9514 /* compute bitmask from p1 value */
9515 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9516 /* also FPA1 */
9517 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9518
9519 switch (crtc_state->dpll.p2) {
9520 case 5:
9521 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9522 break;
9523 case 7:
9524 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9525 break;
9526 case 10:
9527 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9528 break;
9529 case 14:
9530 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9531 break;
9532 }
9533
9534 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9535 intel_panel_use_ssc(dev_priv))
9536 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9537 else
9538 dpll |= PLL_REF_INPUT_DREFCLK;
9539
9540 dpll |= DPLL_VCO_ENABLE;
9541
9542 crtc_state->dpll_hw_state.dpll = dpll;
9543 crtc_state->dpll_hw_state.fp0 = fp;
9544 crtc_state->dpll_hw_state.fp1 = fp2;
9545 }
9546
9547 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9548 struct intel_crtc_state *crtc_state)
9549 {
9550 struct drm_device *dev = crtc->base.dev;
9551 struct drm_i915_private *dev_priv = to_i915(dev);
9552 struct dpll reduced_clock;
9553 bool has_reduced_clock = false;
9554 struct intel_shared_dpll *pll;
9555 const struct intel_limit *limit;
9556 int refclk = 120000;
9557
9558 memset(&crtc_state->dpll_hw_state, 0,
9559 sizeof(crtc_state->dpll_hw_state));
9560
9561 crtc->lowfreq_avail = false;
9562
9563 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9564 if (!crtc_state->has_pch_encoder)
9565 return 0;
9566
9567 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9568 if (intel_panel_use_ssc(dev_priv)) {
9569 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9570 dev_priv->vbt.lvds_ssc_freq);
9571 refclk = dev_priv->vbt.lvds_ssc_freq;
9572 }
9573
9574 if (intel_is_dual_link_lvds(dev)) {
9575 if (refclk == 100000)
9576 limit = &intel_limits_ironlake_dual_lvds_100m;
9577 else
9578 limit = &intel_limits_ironlake_dual_lvds;
9579 } else {
9580 if (refclk == 100000)
9581 limit = &intel_limits_ironlake_single_lvds_100m;
9582 else
9583 limit = &intel_limits_ironlake_single_lvds;
9584 }
9585 } else {
9586 limit = &intel_limits_ironlake_dac;
9587 }
9588
9589 if (!crtc_state->clock_set &&
9590 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9591 refclk, NULL, &crtc_state->dpll)) {
9592 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9593 return -EINVAL;
9594 }
9595
9596 ironlake_compute_dpll(crtc, crtc_state,
9597 has_reduced_clock ? &reduced_clock : NULL);
9598
9599 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9600 if (pll == NULL) {
9601 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9602 pipe_name(crtc->pipe));
9603 return -EINVAL;
9604 }
9605
9606 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9607 has_reduced_clock)
9608 crtc->lowfreq_avail = true;
9609
9610 return 0;
9611 }
9612
9613 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9614 struct intel_link_m_n *m_n)
9615 {
9616 struct drm_device *dev = crtc->base.dev;
9617 struct drm_i915_private *dev_priv = to_i915(dev);
9618 enum pipe pipe = crtc->pipe;
9619
9620 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9621 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9622 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9623 & ~TU_SIZE_MASK;
9624 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9625 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9626 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9627 }
9628
9629 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9630 enum transcoder transcoder,
9631 struct intel_link_m_n *m_n,
9632 struct intel_link_m_n *m2_n2)
9633 {
9634 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9635 enum pipe pipe = crtc->pipe;
9636
9637 if (INTEL_GEN(dev_priv) >= 5) {
9638 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9639 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9640 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9641 & ~TU_SIZE_MASK;
9642 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9643 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9644 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9645 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9646 * gen < 8) and if DRRS is supported (to make sure the
9647 * registers are not unnecessarily read).
9648 */
9649 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
9650 crtc->config->has_drrs) {
9651 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9652 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9653 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9654 & ~TU_SIZE_MASK;
9655 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9656 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9657 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9658 }
9659 } else {
9660 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9661 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9662 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9663 & ~TU_SIZE_MASK;
9664 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9665 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9666 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9667 }
9668 }
9669
9670 void intel_dp_get_m_n(struct intel_crtc *crtc,
9671 struct intel_crtc_state *pipe_config)
9672 {
9673 if (pipe_config->has_pch_encoder)
9674 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9675 else
9676 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9677 &pipe_config->dp_m_n,
9678 &pipe_config->dp_m2_n2);
9679 }
9680
9681 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9682 struct intel_crtc_state *pipe_config)
9683 {
9684 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9685 &pipe_config->fdi_m_n, NULL);
9686 }
9687
9688 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9689 struct intel_crtc_state *pipe_config)
9690 {
9691 struct drm_device *dev = crtc->base.dev;
9692 struct drm_i915_private *dev_priv = to_i915(dev);
9693 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9694 uint32_t ps_ctrl = 0;
9695 int id = -1;
9696 int i;
9697
9698 /* find scaler attached to this pipe */
9699 for (i = 0; i < crtc->num_scalers; i++) {
9700 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9701 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9702 id = i;
9703 pipe_config->pch_pfit.enabled = true;
9704 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9705 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9706 break;
9707 }
9708 }
9709
9710 scaler_state->scaler_id = id;
9711 if (id >= 0) {
9712 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9713 } else {
9714 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9715 }
9716 }
9717
9718 static void
9719 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9720 struct intel_initial_plane_config *plane_config)
9721 {
9722 struct drm_device *dev = crtc->base.dev;
9723 struct drm_i915_private *dev_priv = to_i915(dev);
9724 u32 val, base, offset, stride_mult, tiling;
9725 int pipe = crtc->pipe;
9726 int fourcc, pixel_format;
9727 unsigned int aligned_height;
9728 struct drm_framebuffer *fb;
9729 struct intel_framebuffer *intel_fb;
9730
9731 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9732 if (!intel_fb) {
9733 DRM_DEBUG_KMS("failed to alloc fb\n");
9734 return;
9735 }
9736
9737 fb = &intel_fb->base;
9738
9739 val = I915_READ(PLANE_CTL(pipe, 0));
9740 if (!(val & PLANE_CTL_ENABLE))
9741 goto error;
9742
9743 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9744 fourcc = skl_format_to_fourcc(pixel_format,
9745 val & PLANE_CTL_ORDER_RGBX,
9746 val & PLANE_CTL_ALPHA_MASK);
9747 fb->pixel_format = fourcc;
9748 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9749
9750 tiling = val & PLANE_CTL_TILED_MASK;
9751 switch (tiling) {
9752 case PLANE_CTL_TILED_LINEAR:
9753 fb->modifier = DRM_FORMAT_MOD_NONE;
9754 break;
9755 case PLANE_CTL_TILED_X:
9756 plane_config->tiling = I915_TILING_X;
9757 fb->modifier = I915_FORMAT_MOD_X_TILED;
9758 break;
9759 case PLANE_CTL_TILED_Y:
9760 fb->modifier = I915_FORMAT_MOD_Y_TILED;
9761 break;
9762 case PLANE_CTL_TILED_YF:
9763 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
9764 break;
9765 default:
9766 MISSING_CASE(tiling);
9767 goto error;
9768 }
9769
9770 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9771 plane_config->base = base;
9772
9773 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9774
9775 val = I915_READ(PLANE_SIZE(pipe, 0));
9776 fb->height = ((val >> 16) & 0xfff) + 1;
9777 fb->width = ((val >> 0) & 0x1fff) + 1;
9778
9779 val = I915_READ(PLANE_STRIDE(pipe, 0));
9780 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier,
9781 fb->pixel_format);
9782 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9783
9784 aligned_height = intel_fb_align_height(dev, fb->height,
9785 fb->pixel_format,
9786 fb->modifier);
9787
9788 plane_config->size = fb->pitches[0] * aligned_height;
9789
9790 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9791 pipe_name(pipe), fb->width, fb->height,
9792 fb->bits_per_pixel, base, fb->pitches[0],
9793 plane_config->size);
9794
9795 plane_config->fb = intel_fb;
9796 return;
9797
9798 error:
9799 kfree(intel_fb);
9800 }
9801
9802 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9803 struct intel_crtc_state *pipe_config)
9804 {
9805 struct drm_device *dev = crtc->base.dev;
9806 struct drm_i915_private *dev_priv = to_i915(dev);
9807 uint32_t tmp;
9808
9809 tmp = I915_READ(PF_CTL(crtc->pipe));
9810
9811 if (tmp & PF_ENABLE) {
9812 pipe_config->pch_pfit.enabled = true;
9813 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9814 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9815
9816 /* We currently do not free assignements of panel fitters on
9817 * ivb/hsw (since we don't use the higher upscaling modes which
9818 * differentiates them) so just WARN about this case for now. */
9819 if (IS_GEN7(dev_priv)) {
9820 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9821 PF_PIPE_SEL_IVB(crtc->pipe));
9822 }
9823 }
9824 }
9825
9826 static void
9827 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9828 struct intel_initial_plane_config *plane_config)
9829 {
9830 struct drm_device *dev = crtc->base.dev;
9831 struct drm_i915_private *dev_priv = to_i915(dev);
9832 u32 val, base, offset;
9833 int pipe = crtc->pipe;
9834 int fourcc, pixel_format;
9835 unsigned int aligned_height;
9836 struct drm_framebuffer *fb;
9837 struct intel_framebuffer *intel_fb;
9838
9839 val = I915_READ(DSPCNTR(pipe));
9840 if (!(val & DISPLAY_PLANE_ENABLE))
9841 return;
9842
9843 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9844 if (!intel_fb) {
9845 DRM_DEBUG_KMS("failed to alloc fb\n");
9846 return;
9847 }
9848
9849 fb = &intel_fb->base;
9850
9851 if (INTEL_GEN(dev_priv) >= 4) {
9852 if (val & DISPPLANE_TILED) {
9853 plane_config->tiling = I915_TILING_X;
9854 fb->modifier = I915_FORMAT_MOD_X_TILED;
9855 }
9856 }
9857
9858 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9859 fourcc = i9xx_format_to_fourcc(pixel_format);
9860 fb->pixel_format = fourcc;
9861 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9862
9863 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9864 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
9865 offset = I915_READ(DSPOFFSET(pipe));
9866 } else {
9867 if (plane_config->tiling)
9868 offset = I915_READ(DSPTILEOFF(pipe));
9869 else
9870 offset = I915_READ(DSPLINOFF(pipe));
9871 }
9872 plane_config->base = base;
9873
9874 val = I915_READ(PIPESRC(pipe));
9875 fb->width = ((val >> 16) & 0xfff) + 1;
9876 fb->height = ((val >> 0) & 0xfff) + 1;
9877
9878 val = I915_READ(DSPSTRIDE(pipe));
9879 fb->pitches[0] = val & 0xffffffc0;
9880
9881 aligned_height = intel_fb_align_height(dev, fb->height,
9882 fb->pixel_format,
9883 fb->modifier);
9884
9885 plane_config->size = fb->pitches[0] * aligned_height;
9886
9887 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9888 pipe_name(pipe), fb->width, fb->height,
9889 fb->bits_per_pixel, base, fb->pitches[0],
9890 plane_config->size);
9891
9892 plane_config->fb = intel_fb;
9893 }
9894
9895 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9896 struct intel_crtc_state *pipe_config)
9897 {
9898 struct drm_device *dev = crtc->base.dev;
9899 struct drm_i915_private *dev_priv = to_i915(dev);
9900 enum intel_display_power_domain power_domain;
9901 uint32_t tmp;
9902 bool ret;
9903
9904 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9905 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9906 return false;
9907
9908 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9909 pipe_config->shared_dpll = NULL;
9910
9911 ret = false;
9912 tmp = I915_READ(PIPECONF(crtc->pipe));
9913 if (!(tmp & PIPECONF_ENABLE))
9914 goto out;
9915
9916 switch (tmp & PIPECONF_BPC_MASK) {
9917 case PIPECONF_6BPC:
9918 pipe_config->pipe_bpp = 18;
9919 break;
9920 case PIPECONF_8BPC:
9921 pipe_config->pipe_bpp = 24;
9922 break;
9923 case PIPECONF_10BPC:
9924 pipe_config->pipe_bpp = 30;
9925 break;
9926 case PIPECONF_12BPC:
9927 pipe_config->pipe_bpp = 36;
9928 break;
9929 default:
9930 break;
9931 }
9932
9933 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9934 pipe_config->limited_color_range = true;
9935
9936 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9937 struct intel_shared_dpll *pll;
9938 enum intel_dpll_id pll_id;
9939
9940 pipe_config->has_pch_encoder = true;
9941
9942 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9943 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9944 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9945
9946 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9947
9948 if (HAS_PCH_IBX(dev_priv)) {
9949 /*
9950 * The pipe->pch transcoder and pch transcoder->pll
9951 * mapping is fixed.
9952 */
9953 pll_id = (enum intel_dpll_id) crtc->pipe;
9954 } else {
9955 tmp = I915_READ(PCH_DPLL_SEL);
9956 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9957 pll_id = DPLL_ID_PCH_PLL_B;
9958 else
9959 pll_id= DPLL_ID_PCH_PLL_A;
9960 }
9961
9962 pipe_config->shared_dpll =
9963 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9964 pll = pipe_config->shared_dpll;
9965
9966 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9967 &pipe_config->dpll_hw_state));
9968
9969 tmp = pipe_config->dpll_hw_state.dpll;
9970 pipe_config->pixel_multiplier =
9971 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9972 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9973
9974 ironlake_pch_clock_get(crtc, pipe_config);
9975 } else {
9976 pipe_config->pixel_multiplier = 1;
9977 }
9978
9979 intel_get_pipe_timings(crtc, pipe_config);
9980 intel_get_pipe_src_size(crtc, pipe_config);
9981
9982 ironlake_get_pfit_config(crtc, pipe_config);
9983
9984 ret = true;
9985
9986 out:
9987 intel_display_power_put(dev_priv, power_domain);
9988
9989 return ret;
9990 }
9991
9992 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9993 {
9994 struct drm_device *dev = &dev_priv->drm;
9995 struct intel_crtc *crtc;
9996
9997 for_each_intel_crtc(dev, crtc)
9998 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9999 pipe_name(crtc->pipe));
10000
10001 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
10002 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
10003 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
10004 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
10005 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
10006 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
10007 "CPU PWM1 enabled\n");
10008 if (IS_HASWELL(dev_priv))
10009 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
10010 "CPU PWM2 enabled\n");
10011 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
10012 "PCH PWM1 enabled\n");
10013 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
10014 "Utility pin enabled\n");
10015 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
10016
10017 /*
10018 * In theory we can still leave IRQs enabled, as long as only the HPD
10019 * interrupts remain enabled. We used to check for that, but since it's
10020 * gen-specific and since we only disable LCPLL after we fully disable
10021 * the interrupts, the check below should be enough.
10022 */
10023 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
10024 }
10025
10026 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
10027 {
10028 if (IS_HASWELL(dev_priv))
10029 return I915_READ(D_COMP_HSW);
10030 else
10031 return I915_READ(D_COMP_BDW);
10032 }
10033
10034 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
10035 {
10036 if (IS_HASWELL(dev_priv)) {
10037 mutex_lock(&dev_priv->rps.hw_lock);
10038 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
10039 val))
10040 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
10041 mutex_unlock(&dev_priv->rps.hw_lock);
10042 } else {
10043 I915_WRITE(D_COMP_BDW, val);
10044 POSTING_READ(D_COMP_BDW);
10045 }
10046 }
10047
10048 /*
10049 * This function implements pieces of two sequences from BSpec:
10050 * - Sequence for display software to disable LCPLL
10051 * - Sequence for display software to allow package C8+
10052 * The steps implemented here are just the steps that actually touch the LCPLL
10053 * register. Callers should take care of disabling all the display engine
10054 * functions, doing the mode unset, fixing interrupts, etc.
10055 */
10056 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
10057 bool switch_to_fclk, bool allow_power_down)
10058 {
10059 uint32_t val;
10060
10061 assert_can_disable_lcpll(dev_priv);
10062
10063 val = I915_READ(LCPLL_CTL);
10064
10065 if (switch_to_fclk) {
10066 val |= LCPLL_CD_SOURCE_FCLK;
10067 I915_WRITE(LCPLL_CTL, val);
10068
10069 if (wait_for_us(I915_READ(LCPLL_CTL) &
10070 LCPLL_CD_SOURCE_FCLK_DONE, 1))
10071 DRM_ERROR("Switching to FCLK failed\n");
10072
10073 val = I915_READ(LCPLL_CTL);
10074 }
10075
10076 val |= LCPLL_PLL_DISABLE;
10077 I915_WRITE(LCPLL_CTL, val);
10078 POSTING_READ(LCPLL_CTL);
10079
10080 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
10081 DRM_ERROR("LCPLL still locked\n");
10082
10083 val = hsw_read_dcomp(dev_priv);
10084 val |= D_COMP_COMP_DISABLE;
10085 hsw_write_dcomp(dev_priv, val);
10086 ndelay(100);
10087
10088 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
10089 1))
10090 DRM_ERROR("D_COMP RCOMP still in progress\n");
10091
10092 if (allow_power_down) {
10093 val = I915_READ(LCPLL_CTL);
10094 val |= LCPLL_POWER_DOWN_ALLOW;
10095 I915_WRITE(LCPLL_CTL, val);
10096 POSTING_READ(LCPLL_CTL);
10097 }
10098 }
10099
10100 /*
10101 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
10102 * source.
10103 */
10104 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
10105 {
10106 uint32_t val;
10107
10108 val = I915_READ(LCPLL_CTL);
10109
10110 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
10111 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
10112 return;
10113
10114 /*
10115 * Make sure we're not on PC8 state before disabling PC8, otherwise
10116 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
10117 */
10118 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
10119
10120 if (val & LCPLL_POWER_DOWN_ALLOW) {
10121 val &= ~LCPLL_POWER_DOWN_ALLOW;
10122 I915_WRITE(LCPLL_CTL, val);
10123 POSTING_READ(LCPLL_CTL);
10124 }
10125
10126 val = hsw_read_dcomp(dev_priv);
10127 val |= D_COMP_COMP_FORCE;
10128 val &= ~D_COMP_COMP_DISABLE;
10129 hsw_write_dcomp(dev_priv, val);
10130
10131 val = I915_READ(LCPLL_CTL);
10132 val &= ~LCPLL_PLL_DISABLE;
10133 I915_WRITE(LCPLL_CTL, val);
10134
10135 if (intel_wait_for_register(dev_priv,
10136 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
10137 5))
10138 DRM_ERROR("LCPLL not locked yet\n");
10139
10140 if (val & LCPLL_CD_SOURCE_FCLK) {
10141 val = I915_READ(LCPLL_CTL);
10142 val &= ~LCPLL_CD_SOURCE_FCLK;
10143 I915_WRITE(LCPLL_CTL, val);
10144
10145 if (wait_for_us((I915_READ(LCPLL_CTL) &
10146 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10147 DRM_ERROR("Switching back to LCPLL failed\n");
10148 }
10149
10150 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
10151 intel_update_cdclk(dev_priv);
10152 }
10153
10154 /*
10155 * Package states C8 and deeper are really deep PC states that can only be
10156 * reached when all the devices on the system allow it, so even if the graphics
10157 * device allows PC8+, it doesn't mean the system will actually get to these
10158 * states. Our driver only allows PC8+ when going into runtime PM.
10159 *
10160 * The requirements for PC8+ are that all the outputs are disabled, the power
10161 * well is disabled and most interrupts are disabled, and these are also
10162 * requirements for runtime PM. When these conditions are met, we manually do
10163 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
10164 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
10165 * hang the machine.
10166 *
10167 * When we really reach PC8 or deeper states (not just when we allow it) we lose
10168 * the state of some registers, so when we come back from PC8+ we need to
10169 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
10170 * need to take care of the registers kept by RC6. Notice that this happens even
10171 * if we don't put the device in PCI D3 state (which is what currently happens
10172 * because of the runtime PM support).
10173 *
10174 * For more, read "Display Sequences for Package C8" on the hardware
10175 * documentation.
10176 */
10177 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
10178 {
10179 struct drm_device *dev = &dev_priv->drm;
10180 uint32_t val;
10181
10182 DRM_DEBUG_KMS("Enabling package C8+\n");
10183
10184 if (HAS_PCH_LPT_LP(dev_priv)) {
10185 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10186 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
10187 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10188 }
10189
10190 lpt_disable_clkout_dp(dev);
10191 hsw_disable_lcpll(dev_priv, true, true);
10192 }
10193
10194 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
10195 {
10196 struct drm_device *dev = &dev_priv->drm;
10197 uint32_t val;
10198
10199 DRM_DEBUG_KMS("Disabling package C8+\n");
10200
10201 hsw_restore_lcpll(dev_priv);
10202 lpt_init_pch_refclk(dev);
10203
10204 if (HAS_PCH_LPT_LP(dev_priv)) {
10205 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10206 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
10207 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10208 }
10209 }
10210
10211 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10212 {
10213 struct drm_device *dev = old_state->dev;
10214 struct intel_atomic_state *old_intel_state =
10215 to_intel_atomic_state(old_state);
10216 unsigned int req_cdclk = old_intel_state->dev_cdclk;
10217
10218 bxt_set_cdclk(to_i915(dev), req_cdclk);
10219 }
10220
10221 static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
10222 int pixel_rate)
10223 {
10224 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
10225
10226 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
10227 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
10228 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
10229
10230 /* BSpec says "Do not use DisplayPort with CDCLK less than
10231 * 432 MHz, audio enabled, port width x4, and link rate
10232 * HBR2 (5.4 GHz), or else there may be audio corruption or
10233 * screen corruption."
10234 */
10235 if (intel_crtc_has_dp_encoder(crtc_state) &&
10236 crtc_state->has_audio &&
10237 crtc_state->port_clock >= 540000 &&
10238 crtc_state->lane_count == 4)
10239 pixel_rate = max(432000, pixel_rate);
10240
10241 return pixel_rate;
10242 }
10243
10244 /* compute the max rate for new configuration */
10245 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
10246 {
10247 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10248 struct drm_i915_private *dev_priv = to_i915(state->dev);
10249 struct drm_crtc *crtc;
10250 struct drm_crtc_state *cstate;
10251 struct intel_crtc_state *crtc_state;
10252 unsigned max_pixel_rate = 0, i;
10253 enum pipe pipe;
10254
10255 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
10256 sizeof(intel_state->min_pixclk));
10257
10258 for_each_crtc_in_state(state, crtc, cstate, i) {
10259 int pixel_rate;
10260
10261 crtc_state = to_intel_crtc_state(cstate);
10262 if (!crtc_state->base.enable) {
10263 intel_state->min_pixclk[i] = 0;
10264 continue;
10265 }
10266
10267 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
10268
10269 if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
10270 pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
10271 pixel_rate);
10272
10273 intel_state->min_pixclk[i] = pixel_rate;
10274 }
10275
10276 for_each_pipe(dev_priv, pipe)
10277 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
10278
10279 return max_pixel_rate;
10280 }
10281
10282 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
10283 {
10284 struct drm_i915_private *dev_priv = to_i915(dev);
10285 uint32_t val, data;
10286 int ret;
10287
10288 if (WARN((I915_READ(LCPLL_CTL) &
10289 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
10290 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
10291 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
10292 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
10293 "trying to change cdclk frequency with cdclk not enabled\n"))
10294 return;
10295
10296 mutex_lock(&dev_priv->rps.hw_lock);
10297 ret = sandybridge_pcode_write(dev_priv,
10298 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
10299 mutex_unlock(&dev_priv->rps.hw_lock);
10300 if (ret) {
10301 DRM_ERROR("failed to inform pcode about cdclk change\n");
10302 return;
10303 }
10304
10305 val = I915_READ(LCPLL_CTL);
10306 val |= LCPLL_CD_SOURCE_FCLK;
10307 I915_WRITE(LCPLL_CTL, val);
10308
10309 if (wait_for_us(I915_READ(LCPLL_CTL) &
10310 LCPLL_CD_SOURCE_FCLK_DONE, 1))
10311 DRM_ERROR("Switching to FCLK failed\n");
10312
10313 val = I915_READ(LCPLL_CTL);
10314 val &= ~LCPLL_CLK_FREQ_MASK;
10315
10316 switch (cdclk) {
10317 case 450000:
10318 val |= LCPLL_CLK_FREQ_450;
10319 data = 0;
10320 break;
10321 case 540000:
10322 val |= LCPLL_CLK_FREQ_54O_BDW;
10323 data = 1;
10324 break;
10325 case 337500:
10326 val |= LCPLL_CLK_FREQ_337_5_BDW;
10327 data = 2;
10328 break;
10329 case 675000:
10330 val |= LCPLL_CLK_FREQ_675_BDW;
10331 data = 3;
10332 break;
10333 default:
10334 WARN(1, "invalid cdclk frequency\n");
10335 return;
10336 }
10337
10338 I915_WRITE(LCPLL_CTL, val);
10339
10340 val = I915_READ(LCPLL_CTL);
10341 val &= ~LCPLL_CD_SOURCE_FCLK;
10342 I915_WRITE(LCPLL_CTL, val);
10343
10344 if (wait_for_us((I915_READ(LCPLL_CTL) &
10345 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10346 DRM_ERROR("Switching back to LCPLL failed\n");
10347
10348 mutex_lock(&dev_priv->rps.hw_lock);
10349 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
10350 mutex_unlock(&dev_priv->rps.hw_lock);
10351
10352 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
10353
10354 intel_update_cdclk(dev_priv);
10355
10356 WARN(cdclk != dev_priv->cdclk_freq,
10357 "cdclk requested %d kHz but got %d kHz\n",
10358 cdclk, dev_priv->cdclk_freq);
10359 }
10360
10361 static int broadwell_calc_cdclk(int max_pixclk)
10362 {
10363 if (max_pixclk > 540000)
10364 return 675000;
10365 else if (max_pixclk > 450000)
10366 return 540000;
10367 else if (max_pixclk > 337500)
10368 return 450000;
10369 else
10370 return 337500;
10371 }
10372
10373 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
10374 {
10375 struct drm_i915_private *dev_priv = to_i915(state->dev);
10376 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10377 int max_pixclk = ilk_max_pixel_rate(state);
10378 int cdclk;
10379
10380 /*
10381 * FIXME should also account for plane ratio
10382 * once 64bpp pixel formats are supported.
10383 */
10384 cdclk = broadwell_calc_cdclk(max_pixclk);
10385
10386 if (cdclk > dev_priv->max_cdclk_freq) {
10387 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10388 cdclk, dev_priv->max_cdclk_freq);
10389 return -EINVAL;
10390 }
10391
10392 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10393 if (!intel_state->active_crtcs)
10394 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
10395
10396 return 0;
10397 }
10398
10399 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10400 {
10401 struct drm_device *dev = old_state->dev;
10402 struct intel_atomic_state *old_intel_state =
10403 to_intel_atomic_state(old_state);
10404 unsigned req_cdclk = old_intel_state->dev_cdclk;
10405
10406 broadwell_set_cdclk(dev, req_cdclk);
10407 }
10408
10409 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
10410 {
10411 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10412 struct drm_i915_private *dev_priv = to_i915(state->dev);
10413 const int max_pixclk = ilk_max_pixel_rate(state);
10414 int vco = intel_state->cdclk_pll_vco;
10415 int cdclk;
10416
10417 /*
10418 * FIXME should also account for plane ratio
10419 * once 64bpp pixel formats are supported.
10420 */
10421 cdclk = skl_calc_cdclk(max_pixclk, vco);
10422
10423 /*
10424 * FIXME move the cdclk caclulation to
10425 * compute_config() so we can fail gracegully.
10426 */
10427 if (cdclk > dev_priv->max_cdclk_freq) {
10428 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10429 cdclk, dev_priv->max_cdclk_freq);
10430 cdclk = dev_priv->max_cdclk_freq;
10431 }
10432
10433 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10434 if (!intel_state->active_crtcs)
10435 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
10436
10437 return 0;
10438 }
10439
10440 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10441 {
10442 struct drm_i915_private *dev_priv = to_i915(old_state->dev);
10443 struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
10444 unsigned int req_cdclk = intel_state->dev_cdclk;
10445 unsigned int req_vco = intel_state->cdclk_pll_vco;
10446
10447 skl_set_cdclk(dev_priv, req_cdclk, req_vco);
10448 }
10449
10450 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10451 struct intel_crtc_state *crtc_state)
10452 {
10453 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
10454 if (!intel_ddi_pll_select(crtc, crtc_state))
10455 return -EINVAL;
10456 }
10457
10458 crtc->lowfreq_avail = false;
10459
10460 return 0;
10461 }
10462
10463 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10464 enum port port,
10465 struct intel_crtc_state *pipe_config)
10466 {
10467 enum intel_dpll_id id;
10468
10469 switch (port) {
10470 case PORT_A:
10471 id = DPLL_ID_SKL_DPLL0;
10472 break;
10473 case PORT_B:
10474 id = DPLL_ID_SKL_DPLL1;
10475 break;
10476 case PORT_C:
10477 id = DPLL_ID_SKL_DPLL2;
10478 break;
10479 default:
10480 DRM_ERROR("Incorrect port type\n");
10481 return;
10482 }
10483
10484 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10485 }
10486
10487 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10488 enum port port,
10489 struct intel_crtc_state *pipe_config)
10490 {
10491 enum intel_dpll_id id;
10492 u32 temp;
10493
10494 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10495 id = temp >> (port * 3 + 1);
10496
10497 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
10498 return;
10499
10500 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10501 }
10502
10503 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10504 enum port port,
10505 struct intel_crtc_state *pipe_config)
10506 {
10507 enum intel_dpll_id id;
10508 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10509
10510 switch (ddi_pll_sel) {
10511 case PORT_CLK_SEL_WRPLL1:
10512 id = DPLL_ID_WRPLL1;
10513 break;
10514 case PORT_CLK_SEL_WRPLL2:
10515 id = DPLL_ID_WRPLL2;
10516 break;
10517 case PORT_CLK_SEL_SPLL:
10518 id = DPLL_ID_SPLL;
10519 break;
10520 case PORT_CLK_SEL_LCPLL_810:
10521 id = DPLL_ID_LCPLL_810;
10522 break;
10523 case PORT_CLK_SEL_LCPLL_1350:
10524 id = DPLL_ID_LCPLL_1350;
10525 break;
10526 case PORT_CLK_SEL_LCPLL_2700:
10527 id = DPLL_ID_LCPLL_2700;
10528 break;
10529 default:
10530 MISSING_CASE(ddi_pll_sel);
10531 /* fall through */
10532 case PORT_CLK_SEL_NONE:
10533 return;
10534 }
10535
10536 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10537 }
10538
10539 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10540 struct intel_crtc_state *pipe_config,
10541 unsigned long *power_domain_mask)
10542 {
10543 struct drm_device *dev = crtc->base.dev;
10544 struct drm_i915_private *dev_priv = to_i915(dev);
10545 enum intel_display_power_domain power_domain;
10546 u32 tmp;
10547
10548 /*
10549 * The pipe->transcoder mapping is fixed with the exception of the eDP
10550 * transcoder handled below.
10551 */
10552 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10553
10554 /*
10555 * XXX: Do intel_display_power_get_if_enabled before reading this (for
10556 * consistency and less surprising code; it's in always on power).
10557 */
10558 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10559 if (tmp & TRANS_DDI_FUNC_ENABLE) {
10560 enum pipe trans_edp_pipe;
10561 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10562 default:
10563 WARN(1, "unknown pipe linked to edp transcoder\n");
10564 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10565 case TRANS_DDI_EDP_INPUT_A_ON:
10566 trans_edp_pipe = PIPE_A;
10567 break;
10568 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10569 trans_edp_pipe = PIPE_B;
10570 break;
10571 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10572 trans_edp_pipe = PIPE_C;
10573 break;
10574 }
10575
10576 if (trans_edp_pipe == crtc->pipe)
10577 pipe_config->cpu_transcoder = TRANSCODER_EDP;
10578 }
10579
10580 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10581 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10582 return false;
10583 *power_domain_mask |= BIT(power_domain);
10584
10585 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10586
10587 return tmp & PIPECONF_ENABLE;
10588 }
10589
10590 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10591 struct intel_crtc_state *pipe_config,
10592 unsigned long *power_domain_mask)
10593 {
10594 struct drm_device *dev = crtc->base.dev;
10595 struct drm_i915_private *dev_priv = to_i915(dev);
10596 enum intel_display_power_domain power_domain;
10597 enum port port;
10598 enum transcoder cpu_transcoder;
10599 u32 tmp;
10600
10601 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10602 if (port == PORT_A)
10603 cpu_transcoder = TRANSCODER_DSI_A;
10604 else
10605 cpu_transcoder = TRANSCODER_DSI_C;
10606
10607 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10608 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10609 continue;
10610 *power_domain_mask |= BIT(power_domain);
10611
10612 /*
10613 * The PLL needs to be enabled with a valid divider
10614 * configuration, otherwise accessing DSI registers will hang
10615 * the machine. See BSpec North Display Engine
10616 * registers/MIPI[BXT]. We can break out here early, since we
10617 * need the same DSI PLL to be enabled for both DSI ports.
10618 */
10619 if (!intel_dsi_pll_is_enabled(dev_priv))
10620 break;
10621
10622 /* XXX: this works for video mode only */
10623 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10624 if (!(tmp & DPI_ENABLE))
10625 continue;
10626
10627 tmp = I915_READ(MIPI_CTRL(port));
10628 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10629 continue;
10630
10631 pipe_config->cpu_transcoder = cpu_transcoder;
10632 break;
10633 }
10634
10635 return transcoder_is_dsi(pipe_config->cpu_transcoder);
10636 }
10637
10638 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10639 struct intel_crtc_state *pipe_config)
10640 {
10641 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10642 struct intel_shared_dpll *pll;
10643 enum port port;
10644 uint32_t tmp;
10645
10646 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10647
10648 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10649
10650 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
10651 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10652 else if (IS_BROXTON(dev_priv))
10653 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10654 else
10655 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10656
10657 pll = pipe_config->shared_dpll;
10658 if (pll) {
10659 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10660 &pipe_config->dpll_hw_state));
10661 }
10662
10663 /*
10664 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10665 * DDI E. So just check whether this pipe is wired to DDI E and whether
10666 * the PCH transcoder is on.
10667 */
10668 if (INTEL_GEN(dev_priv) < 9 &&
10669 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10670 pipe_config->has_pch_encoder = true;
10671
10672 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10673 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10674 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10675
10676 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10677 }
10678 }
10679
10680 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10681 struct intel_crtc_state *pipe_config)
10682 {
10683 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10684 enum intel_display_power_domain power_domain;
10685 unsigned long power_domain_mask;
10686 bool active;
10687
10688 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10689 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10690 return false;
10691 power_domain_mask = BIT(power_domain);
10692
10693 pipe_config->shared_dpll = NULL;
10694
10695 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10696
10697 if (IS_BROXTON(dev_priv) &&
10698 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
10699 WARN_ON(active);
10700 active = true;
10701 }
10702
10703 if (!active)
10704 goto out;
10705
10706 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10707 haswell_get_ddi_port_state(crtc, pipe_config);
10708 intel_get_pipe_timings(crtc, pipe_config);
10709 }
10710
10711 intel_get_pipe_src_size(crtc, pipe_config);
10712
10713 pipe_config->gamma_mode =
10714 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10715
10716 if (INTEL_GEN(dev_priv) >= 9) {
10717 skl_init_scalers(dev_priv, crtc, pipe_config);
10718
10719 pipe_config->scaler_state.scaler_id = -1;
10720 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10721 }
10722
10723 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10724 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10725 power_domain_mask |= BIT(power_domain);
10726 if (INTEL_GEN(dev_priv) >= 9)
10727 skylake_get_pfit_config(crtc, pipe_config);
10728 else
10729 ironlake_get_pfit_config(crtc, pipe_config);
10730 }
10731
10732 if (IS_HASWELL(dev_priv))
10733 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10734 (I915_READ(IPS_CTL) & IPS_ENABLE);
10735
10736 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10737 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10738 pipe_config->pixel_multiplier =
10739 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10740 } else {
10741 pipe_config->pixel_multiplier = 1;
10742 }
10743
10744 out:
10745 for_each_power_domain(power_domain, power_domain_mask)
10746 intel_display_power_put(dev_priv, power_domain);
10747
10748 return active;
10749 }
10750
10751 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10752 const struct intel_plane_state *plane_state)
10753 {
10754 struct drm_device *dev = crtc->dev;
10755 struct drm_i915_private *dev_priv = to_i915(dev);
10756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10757 uint32_t cntl = 0, size = 0;
10758
10759 if (plane_state && plane_state->base.visible) {
10760 unsigned int width = plane_state->base.crtc_w;
10761 unsigned int height = plane_state->base.crtc_h;
10762 unsigned int stride = roundup_pow_of_two(width) * 4;
10763
10764 switch (stride) {
10765 default:
10766 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10767 width, stride);
10768 stride = 256;
10769 /* fallthrough */
10770 case 256:
10771 case 512:
10772 case 1024:
10773 case 2048:
10774 break;
10775 }
10776
10777 cntl |= CURSOR_ENABLE |
10778 CURSOR_GAMMA_ENABLE |
10779 CURSOR_FORMAT_ARGB |
10780 CURSOR_STRIDE(stride);
10781
10782 size = (height << 12) | width;
10783 }
10784
10785 if (intel_crtc->cursor_cntl != 0 &&
10786 (intel_crtc->cursor_base != base ||
10787 intel_crtc->cursor_size != size ||
10788 intel_crtc->cursor_cntl != cntl)) {
10789 /* On these chipsets we can only modify the base/size/stride
10790 * whilst the cursor is disabled.
10791 */
10792 I915_WRITE(CURCNTR(PIPE_A), 0);
10793 POSTING_READ(CURCNTR(PIPE_A));
10794 intel_crtc->cursor_cntl = 0;
10795 }
10796
10797 if (intel_crtc->cursor_base != base) {
10798 I915_WRITE(CURBASE(PIPE_A), base);
10799 intel_crtc->cursor_base = base;
10800 }
10801
10802 if (intel_crtc->cursor_size != size) {
10803 I915_WRITE(CURSIZE, size);
10804 intel_crtc->cursor_size = size;
10805 }
10806
10807 if (intel_crtc->cursor_cntl != cntl) {
10808 I915_WRITE(CURCNTR(PIPE_A), cntl);
10809 POSTING_READ(CURCNTR(PIPE_A));
10810 intel_crtc->cursor_cntl = cntl;
10811 }
10812 }
10813
10814 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10815 const struct intel_plane_state *plane_state)
10816 {
10817 struct drm_device *dev = crtc->dev;
10818 struct drm_i915_private *dev_priv = to_i915(dev);
10819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10820 int pipe = intel_crtc->pipe;
10821 uint32_t cntl = 0;
10822
10823 if (plane_state && plane_state->base.visible) {
10824 cntl = MCURSOR_GAMMA_ENABLE;
10825 switch (plane_state->base.crtc_w) {
10826 case 64:
10827 cntl |= CURSOR_MODE_64_ARGB_AX;
10828 break;
10829 case 128:
10830 cntl |= CURSOR_MODE_128_ARGB_AX;
10831 break;
10832 case 256:
10833 cntl |= CURSOR_MODE_256_ARGB_AX;
10834 break;
10835 default:
10836 MISSING_CASE(plane_state->base.crtc_w);
10837 return;
10838 }
10839 cntl |= pipe << 28; /* Connect to correct pipe */
10840
10841 if (HAS_DDI(dev_priv))
10842 cntl |= CURSOR_PIPE_CSC_ENABLE;
10843
10844 if (plane_state->base.rotation & DRM_ROTATE_180)
10845 cntl |= CURSOR_ROTATE_180;
10846 }
10847
10848 if (intel_crtc->cursor_cntl != cntl) {
10849 I915_WRITE(CURCNTR(pipe), cntl);
10850 POSTING_READ(CURCNTR(pipe));
10851 intel_crtc->cursor_cntl = cntl;
10852 }
10853
10854 /* and commit changes on next vblank */
10855 I915_WRITE(CURBASE(pipe), base);
10856 POSTING_READ(CURBASE(pipe));
10857
10858 intel_crtc->cursor_base = base;
10859 }
10860
10861 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10862 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10863 const struct intel_plane_state *plane_state)
10864 {
10865 struct drm_device *dev = crtc->dev;
10866 struct drm_i915_private *dev_priv = to_i915(dev);
10867 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10868 int pipe = intel_crtc->pipe;
10869 u32 base = intel_crtc->cursor_addr;
10870 u32 pos = 0;
10871
10872 if (plane_state) {
10873 int x = plane_state->base.crtc_x;
10874 int y = plane_state->base.crtc_y;
10875
10876 if (x < 0) {
10877 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10878 x = -x;
10879 }
10880 pos |= x << CURSOR_X_SHIFT;
10881
10882 if (y < 0) {
10883 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10884 y = -y;
10885 }
10886 pos |= y << CURSOR_Y_SHIFT;
10887
10888 /* ILK+ do this automagically */
10889 if (HAS_GMCH_DISPLAY(dev_priv) &&
10890 plane_state->base.rotation & DRM_ROTATE_180) {
10891 base += (plane_state->base.crtc_h *
10892 plane_state->base.crtc_w - 1) * 4;
10893 }
10894 }
10895
10896 I915_WRITE(CURPOS(pipe), pos);
10897
10898 if (IS_845G(dev_priv) || IS_I865G(dev_priv))
10899 i845_update_cursor(crtc, base, plane_state);
10900 else
10901 i9xx_update_cursor(crtc, base, plane_state);
10902 }
10903
10904 static bool cursor_size_ok(struct drm_i915_private *dev_priv,
10905 uint32_t width, uint32_t height)
10906 {
10907 if (width == 0 || height == 0)
10908 return false;
10909
10910 /*
10911 * 845g/865g are special in that they are only limited by
10912 * the width of their cursors, the height is arbitrary up to
10913 * the precision of the register. Everything else requires
10914 * square cursors, limited to a few power-of-two sizes.
10915 */
10916 if (IS_845G(dev_priv) || IS_I865G(dev_priv)) {
10917 if ((width & 63) != 0)
10918 return false;
10919
10920 if (width > (IS_845G(dev_priv) ? 64 : 512))
10921 return false;
10922
10923 if (height > 1023)
10924 return false;
10925 } else {
10926 switch (width | height) {
10927 case 256:
10928 case 128:
10929 if (IS_GEN2(dev_priv))
10930 return false;
10931 case 64:
10932 break;
10933 default:
10934 return false;
10935 }
10936 }
10937
10938 return true;
10939 }
10940
10941 /* VESA 640x480x72Hz mode to set on the pipe */
10942 static struct drm_display_mode load_detect_mode = {
10943 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10944 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10945 };
10946
10947 struct drm_framebuffer *
10948 __intel_framebuffer_create(struct drm_device *dev,
10949 struct drm_mode_fb_cmd2 *mode_cmd,
10950 struct drm_i915_gem_object *obj)
10951 {
10952 struct intel_framebuffer *intel_fb;
10953 int ret;
10954
10955 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10956 if (!intel_fb)
10957 return ERR_PTR(-ENOMEM);
10958
10959 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10960 if (ret)
10961 goto err;
10962
10963 return &intel_fb->base;
10964
10965 err:
10966 kfree(intel_fb);
10967 return ERR_PTR(ret);
10968 }
10969
10970 static struct drm_framebuffer *
10971 intel_framebuffer_create(struct drm_device *dev,
10972 struct drm_mode_fb_cmd2 *mode_cmd,
10973 struct drm_i915_gem_object *obj)
10974 {
10975 struct drm_framebuffer *fb;
10976 int ret;
10977
10978 ret = i915_mutex_lock_interruptible(dev);
10979 if (ret)
10980 return ERR_PTR(ret);
10981 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10982 mutex_unlock(&dev->struct_mutex);
10983
10984 return fb;
10985 }
10986
10987 static u32
10988 intel_framebuffer_pitch_for_width(int width, int bpp)
10989 {
10990 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10991 return ALIGN(pitch, 64);
10992 }
10993
10994 static u32
10995 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10996 {
10997 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10998 return PAGE_ALIGN(pitch * mode->vdisplay);
10999 }
11000
11001 static struct drm_framebuffer *
11002 intel_framebuffer_create_for_mode(struct drm_device *dev,
11003 struct drm_display_mode *mode,
11004 int depth, int bpp)
11005 {
11006 struct drm_framebuffer *fb;
11007 struct drm_i915_gem_object *obj;
11008 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
11009
11010 obj = i915_gem_object_create(dev,
11011 intel_framebuffer_size_for_mode(mode, bpp));
11012 if (IS_ERR(obj))
11013 return ERR_CAST(obj);
11014
11015 mode_cmd.width = mode->hdisplay;
11016 mode_cmd.height = mode->vdisplay;
11017 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
11018 bpp);
11019 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
11020
11021 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
11022 if (IS_ERR(fb))
11023 i915_gem_object_put(obj);
11024
11025 return fb;
11026 }
11027
11028 static struct drm_framebuffer *
11029 mode_fits_in_fbdev(struct drm_device *dev,
11030 struct drm_display_mode *mode)
11031 {
11032 #ifdef CONFIG_DRM_FBDEV_EMULATION
11033 struct drm_i915_private *dev_priv = to_i915(dev);
11034 struct drm_i915_gem_object *obj;
11035 struct drm_framebuffer *fb;
11036
11037 if (!dev_priv->fbdev)
11038 return NULL;
11039
11040 if (!dev_priv->fbdev->fb)
11041 return NULL;
11042
11043 obj = dev_priv->fbdev->fb->obj;
11044 BUG_ON(!obj);
11045
11046 fb = &dev_priv->fbdev->fb->base;
11047 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
11048 fb->bits_per_pixel))
11049 return NULL;
11050
11051 if (obj->base.size < mode->vdisplay * fb->pitches[0])
11052 return NULL;
11053
11054 drm_framebuffer_reference(fb);
11055 return fb;
11056 #else
11057 return NULL;
11058 #endif
11059 }
11060
11061 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
11062 struct drm_crtc *crtc,
11063 struct drm_display_mode *mode,
11064 struct drm_framebuffer *fb,
11065 int x, int y)
11066 {
11067 struct drm_plane_state *plane_state;
11068 int hdisplay, vdisplay;
11069 int ret;
11070
11071 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
11072 if (IS_ERR(plane_state))
11073 return PTR_ERR(plane_state);
11074
11075 if (mode)
11076 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11077 else
11078 hdisplay = vdisplay = 0;
11079
11080 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
11081 if (ret)
11082 return ret;
11083 drm_atomic_set_fb_for_plane(plane_state, fb);
11084 plane_state->crtc_x = 0;
11085 plane_state->crtc_y = 0;
11086 plane_state->crtc_w = hdisplay;
11087 plane_state->crtc_h = vdisplay;
11088 plane_state->src_x = x << 16;
11089 plane_state->src_y = y << 16;
11090 plane_state->src_w = hdisplay << 16;
11091 plane_state->src_h = vdisplay << 16;
11092
11093 return 0;
11094 }
11095
11096 bool intel_get_load_detect_pipe(struct drm_connector *connector,
11097 struct drm_display_mode *mode,
11098 struct intel_load_detect_pipe *old,
11099 struct drm_modeset_acquire_ctx *ctx)
11100 {
11101 struct intel_crtc *intel_crtc;
11102 struct intel_encoder *intel_encoder =
11103 intel_attached_encoder(connector);
11104 struct drm_crtc *possible_crtc;
11105 struct drm_encoder *encoder = &intel_encoder->base;
11106 struct drm_crtc *crtc = NULL;
11107 struct drm_device *dev = encoder->dev;
11108 struct drm_i915_private *dev_priv = to_i915(dev);
11109 struct drm_framebuffer *fb;
11110 struct drm_mode_config *config = &dev->mode_config;
11111 struct drm_atomic_state *state = NULL, *restore_state = NULL;
11112 struct drm_connector_state *connector_state;
11113 struct intel_crtc_state *crtc_state;
11114 int ret, i = -1;
11115
11116 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11117 connector->base.id, connector->name,
11118 encoder->base.id, encoder->name);
11119
11120 old->restore_state = NULL;
11121
11122 retry:
11123 ret = drm_modeset_lock(&config->connection_mutex, ctx);
11124 if (ret)
11125 goto fail;
11126
11127 /*
11128 * Algorithm gets a little messy:
11129 *
11130 * - if the connector already has an assigned crtc, use it (but make
11131 * sure it's on first)
11132 *
11133 * - try to find the first unused crtc that can drive this connector,
11134 * and use that if we find one
11135 */
11136
11137 /* See if we already have a CRTC for this connector */
11138 if (connector->state->crtc) {
11139 crtc = connector->state->crtc;
11140
11141 ret = drm_modeset_lock(&crtc->mutex, ctx);
11142 if (ret)
11143 goto fail;
11144
11145 /* Make sure the crtc and connector are running */
11146 goto found;
11147 }
11148
11149 /* Find an unused one (if possible) */
11150 for_each_crtc(dev, possible_crtc) {
11151 i++;
11152 if (!(encoder->possible_crtcs & (1 << i)))
11153 continue;
11154
11155 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11156 if (ret)
11157 goto fail;
11158
11159 if (possible_crtc->state->enable) {
11160 drm_modeset_unlock(&possible_crtc->mutex);
11161 continue;
11162 }
11163
11164 crtc = possible_crtc;
11165 break;
11166 }
11167
11168 /*
11169 * If we didn't find an unused CRTC, don't use any.
11170 */
11171 if (!crtc) {
11172 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11173 goto fail;
11174 }
11175
11176 found:
11177 intel_crtc = to_intel_crtc(crtc);
11178
11179 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
11180 if (ret)
11181 goto fail;
11182
11183 state = drm_atomic_state_alloc(dev);
11184 restore_state = drm_atomic_state_alloc(dev);
11185 if (!state || !restore_state) {
11186 ret = -ENOMEM;
11187 goto fail;
11188 }
11189
11190 state->acquire_ctx = ctx;
11191 restore_state->acquire_ctx = ctx;
11192
11193 connector_state = drm_atomic_get_connector_state(state, connector);
11194 if (IS_ERR(connector_state)) {
11195 ret = PTR_ERR(connector_state);
11196 goto fail;
11197 }
11198
11199 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11200 if (ret)
11201 goto fail;
11202
11203 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11204 if (IS_ERR(crtc_state)) {
11205 ret = PTR_ERR(crtc_state);
11206 goto fail;
11207 }
11208
11209 crtc_state->base.active = crtc_state->base.enable = true;
11210
11211 if (!mode)
11212 mode = &load_detect_mode;
11213
11214 /* We need a framebuffer large enough to accommodate all accesses
11215 * that the plane may generate whilst we perform load detection.
11216 * We can not rely on the fbcon either being present (we get called
11217 * during its initialisation to detect all boot displays, or it may
11218 * not even exist) or that it is large enough to satisfy the
11219 * requested mode.
11220 */
11221 fb = mode_fits_in_fbdev(dev, mode);
11222 if (fb == NULL) {
11223 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
11224 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
11225 } else
11226 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
11227 if (IS_ERR(fb)) {
11228 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
11229 goto fail;
11230 }
11231
11232 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
11233 if (ret)
11234 goto fail;
11235
11236 drm_framebuffer_unreference(fb);
11237
11238 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
11239 if (ret)
11240 goto fail;
11241
11242 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11243 if (!ret)
11244 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11245 if (!ret)
11246 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
11247 if (ret) {
11248 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11249 goto fail;
11250 }
11251
11252 ret = drm_atomic_commit(state);
11253 if (ret) {
11254 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11255 goto fail;
11256 }
11257
11258 old->restore_state = restore_state;
11259 drm_atomic_state_put(state);
11260
11261 /* let the connector get through one full cycle before testing */
11262 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
11263 return true;
11264
11265 fail:
11266 if (state) {
11267 drm_atomic_state_put(state);
11268 state = NULL;
11269 }
11270 if (restore_state) {
11271 drm_atomic_state_put(restore_state);
11272 restore_state = NULL;
11273 }
11274
11275 if (ret == -EDEADLK) {
11276 drm_modeset_backoff(ctx);
11277 goto retry;
11278 }
11279
11280 return false;
11281 }
11282
11283 void intel_release_load_detect_pipe(struct drm_connector *connector,
11284 struct intel_load_detect_pipe *old,
11285 struct drm_modeset_acquire_ctx *ctx)
11286 {
11287 struct intel_encoder *intel_encoder =
11288 intel_attached_encoder(connector);
11289 struct drm_encoder *encoder = &intel_encoder->base;
11290 struct drm_atomic_state *state = old->restore_state;
11291 int ret;
11292
11293 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11294 connector->base.id, connector->name,
11295 encoder->base.id, encoder->name);
11296
11297 if (!state)
11298 return;
11299
11300 ret = drm_atomic_commit(state);
11301 if (ret)
11302 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11303 drm_atomic_state_put(state);
11304 }
11305
11306 static int i9xx_pll_refclk(struct drm_device *dev,
11307 const struct intel_crtc_state *pipe_config)
11308 {
11309 struct drm_i915_private *dev_priv = to_i915(dev);
11310 u32 dpll = pipe_config->dpll_hw_state.dpll;
11311
11312 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11313 return dev_priv->vbt.lvds_ssc_freq;
11314 else if (HAS_PCH_SPLIT(dev_priv))
11315 return 120000;
11316 else if (!IS_GEN2(dev_priv))
11317 return 96000;
11318 else
11319 return 48000;
11320 }
11321
11322 /* Returns the clock of the currently programmed mode of the given pipe. */
11323 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11324 struct intel_crtc_state *pipe_config)
11325 {
11326 struct drm_device *dev = crtc->base.dev;
11327 struct drm_i915_private *dev_priv = to_i915(dev);
11328 int pipe = pipe_config->cpu_transcoder;
11329 u32 dpll = pipe_config->dpll_hw_state.dpll;
11330 u32 fp;
11331 struct dpll clock;
11332 int port_clock;
11333 int refclk = i9xx_pll_refclk(dev, pipe_config);
11334
11335 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11336 fp = pipe_config->dpll_hw_state.fp0;
11337 else
11338 fp = pipe_config->dpll_hw_state.fp1;
11339
11340 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11341 if (IS_PINEVIEW(dev_priv)) {
11342 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11343 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11344 } else {
11345 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11346 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11347 }
11348
11349 if (!IS_GEN2(dev_priv)) {
11350 if (IS_PINEVIEW(dev_priv))
11351 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11352 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11353 else
11354 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11355 DPLL_FPA01_P1_POST_DIV_SHIFT);
11356
11357 switch (dpll & DPLL_MODE_MASK) {
11358 case DPLLB_MODE_DAC_SERIAL:
11359 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11360 5 : 10;
11361 break;
11362 case DPLLB_MODE_LVDS:
11363 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11364 7 : 14;
11365 break;
11366 default:
11367 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11368 "mode\n", (int)(dpll & DPLL_MODE_MASK));
11369 return;
11370 }
11371
11372 if (IS_PINEVIEW(dev_priv))
11373 port_clock = pnv_calc_dpll_params(refclk, &clock);
11374 else
11375 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11376 } else {
11377 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
11378 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11379
11380 if (is_lvds) {
11381 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11382 DPLL_FPA01_P1_POST_DIV_SHIFT);
11383
11384 if (lvds & LVDS_CLKB_POWER_UP)
11385 clock.p2 = 7;
11386 else
11387 clock.p2 = 14;
11388 } else {
11389 if (dpll & PLL_P1_DIVIDE_BY_TWO)
11390 clock.p1 = 2;
11391 else {
11392 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11393 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11394 }
11395 if (dpll & PLL_P2_DIVIDE_BY_4)
11396 clock.p2 = 4;
11397 else
11398 clock.p2 = 2;
11399 }
11400
11401 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11402 }
11403
11404 /*
11405 * This value includes pixel_multiplier. We will use
11406 * port_clock to compute adjusted_mode.crtc_clock in the
11407 * encoder's get_config() function.
11408 */
11409 pipe_config->port_clock = port_clock;
11410 }
11411
11412 int intel_dotclock_calculate(int link_freq,
11413 const struct intel_link_m_n *m_n)
11414 {
11415 /*
11416 * The calculation for the data clock is:
11417 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11418 * But we want to avoid losing precison if possible, so:
11419 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11420 *
11421 * and the link clock is simpler:
11422 * link_clock = (m * link_clock) / n
11423 */
11424
11425 if (!m_n->link_n)
11426 return 0;
11427
11428 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
11429 }
11430
11431 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11432 struct intel_crtc_state *pipe_config)
11433 {
11434 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11435
11436 /* read out port_clock from the DPLL */
11437 i9xx_crtc_clock_get(crtc, pipe_config);
11438
11439 /*
11440 * In case there is an active pipe without active ports,
11441 * we may need some idea for the dotclock anyway.
11442 * Calculate one based on the FDI configuration.
11443 */
11444 pipe_config->base.adjusted_mode.crtc_clock =
11445 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11446 &pipe_config->fdi_m_n);
11447 }
11448
11449 /** Returns the currently programmed mode of the given pipe. */
11450 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
11451 struct drm_crtc *crtc)
11452 {
11453 struct drm_i915_private *dev_priv = to_i915(dev);
11454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11455 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
11456 struct drm_display_mode *mode;
11457 struct intel_crtc_state *pipe_config;
11458 int htot = I915_READ(HTOTAL(cpu_transcoder));
11459 int hsync = I915_READ(HSYNC(cpu_transcoder));
11460 int vtot = I915_READ(VTOTAL(cpu_transcoder));
11461 int vsync = I915_READ(VSYNC(cpu_transcoder));
11462 enum pipe pipe = intel_crtc->pipe;
11463
11464 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11465 if (!mode)
11466 return NULL;
11467
11468 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
11469 if (!pipe_config) {
11470 kfree(mode);
11471 return NULL;
11472 }
11473
11474 /*
11475 * Construct a pipe_config sufficient for getting the clock info
11476 * back out of crtc_clock_get.
11477 *
11478 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
11479 * to use a real value here instead.
11480 */
11481 pipe_config->cpu_transcoder = (enum transcoder) pipe;
11482 pipe_config->pixel_multiplier = 1;
11483 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
11484 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
11485 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
11486 i9xx_crtc_clock_get(intel_crtc, pipe_config);
11487
11488 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
11489 mode->hdisplay = (htot & 0xffff) + 1;
11490 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
11491 mode->hsync_start = (hsync & 0xffff) + 1;
11492 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
11493 mode->vdisplay = (vtot & 0xffff) + 1;
11494 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
11495 mode->vsync_start = (vsync & 0xffff) + 1;
11496 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
11497
11498 drm_mode_set_name(mode);
11499
11500 kfree(pipe_config);
11501
11502 return mode;
11503 }
11504
11505 static void intel_crtc_destroy(struct drm_crtc *crtc)
11506 {
11507 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11508 struct drm_device *dev = crtc->dev;
11509 struct intel_flip_work *work;
11510
11511 spin_lock_irq(&dev->event_lock);
11512 work = intel_crtc->flip_work;
11513 intel_crtc->flip_work = NULL;
11514 spin_unlock_irq(&dev->event_lock);
11515
11516 if (work) {
11517 cancel_work_sync(&work->mmio_work);
11518 cancel_work_sync(&work->unpin_work);
11519 kfree(work);
11520 }
11521
11522 drm_crtc_cleanup(crtc);
11523
11524 kfree(intel_crtc);
11525 }
11526
11527 static void intel_unpin_work_fn(struct work_struct *__work)
11528 {
11529 struct intel_flip_work *work =
11530 container_of(__work, struct intel_flip_work, unpin_work);
11531 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11532 struct drm_device *dev = crtc->base.dev;
11533 struct drm_plane *primary = crtc->base.primary;
11534
11535 if (is_mmio_work(work))
11536 flush_work(&work->mmio_work);
11537
11538 mutex_lock(&dev->struct_mutex);
11539 intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
11540 i915_gem_object_put(work->pending_flip_obj);
11541 mutex_unlock(&dev->struct_mutex);
11542
11543 i915_gem_request_put(work->flip_queued_req);
11544
11545 intel_frontbuffer_flip_complete(to_i915(dev),
11546 to_intel_plane(primary)->frontbuffer_bit);
11547 intel_fbc_post_update(crtc);
11548 drm_framebuffer_unreference(work->old_fb);
11549
11550 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11551 atomic_dec(&crtc->unpin_work_count);
11552
11553 kfree(work);
11554 }
11555
11556 /* Is 'a' after or equal to 'b'? */
11557 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11558 {
11559 return !((a - b) & 0x80000000);
11560 }
11561
11562 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11563 struct intel_flip_work *work)
11564 {
11565 struct drm_device *dev = crtc->base.dev;
11566 struct drm_i915_private *dev_priv = to_i915(dev);
11567
11568 if (abort_flip_on_reset(crtc))
11569 return true;
11570
11571 /*
11572 * The relevant registers doen't exist on pre-ctg.
11573 * As the flip done interrupt doesn't trigger for mmio
11574 * flips on gmch platforms, a flip count check isn't
11575 * really needed there. But since ctg has the registers,
11576 * include it in the check anyway.
11577 */
11578 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11579 return true;
11580
11581 /*
11582 * BDW signals flip done immediately if the plane
11583 * is disabled, even if the plane enable is already
11584 * armed to occur at the next vblank :(
11585 */
11586
11587 /*
11588 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11589 * used the same base address. In that case the mmio flip might
11590 * have completed, but the CS hasn't even executed the flip yet.
11591 *
11592 * A flip count check isn't enough as the CS might have updated
11593 * the base address just after start of vblank, but before we
11594 * managed to process the interrupt. This means we'd complete the
11595 * CS flip too soon.
11596 *
11597 * Combining both checks should get us a good enough result. It may
11598 * still happen that the CS flip has been executed, but has not
11599 * yet actually completed. But in case the base address is the same
11600 * anyway, we don't really care.
11601 */
11602 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11603 crtc->flip_work->gtt_offset &&
11604 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11605 crtc->flip_work->flip_count);
11606 }
11607
11608 static bool
11609 __pageflip_finished_mmio(struct intel_crtc *crtc,
11610 struct intel_flip_work *work)
11611 {
11612 /*
11613 * MMIO work completes when vblank is different from
11614 * flip_queued_vblank.
11615 *
11616 * Reset counter value doesn't matter, this is handled by
11617 * i915_wait_request finishing early, so no need to handle
11618 * reset here.
11619 */
11620 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11621 }
11622
11623
11624 static bool pageflip_finished(struct intel_crtc *crtc,
11625 struct intel_flip_work *work)
11626 {
11627 if (!atomic_read(&work->pending))
11628 return false;
11629
11630 smp_rmb();
11631
11632 if (is_mmio_work(work))
11633 return __pageflip_finished_mmio(crtc, work);
11634 else
11635 return __pageflip_finished_cs(crtc, work);
11636 }
11637
11638 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11639 {
11640 struct drm_device *dev = &dev_priv->drm;
11641 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
11642 struct intel_flip_work *work;
11643 unsigned long flags;
11644
11645 /* Ignore early vblank irqs */
11646 if (!crtc)
11647 return;
11648
11649 /*
11650 * This is called both by irq handlers and the reset code (to complete
11651 * lost pageflips) so needs the full irqsave spinlocks.
11652 */
11653 spin_lock_irqsave(&dev->event_lock, flags);
11654 work = crtc->flip_work;
11655
11656 if (work != NULL &&
11657 !is_mmio_work(work) &&
11658 pageflip_finished(crtc, work))
11659 page_flip_completed(crtc);
11660
11661 spin_unlock_irqrestore(&dev->event_lock, flags);
11662 }
11663
11664 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11665 {
11666 struct drm_device *dev = &dev_priv->drm;
11667 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
11668 struct intel_flip_work *work;
11669 unsigned long flags;
11670
11671 /* Ignore early vblank irqs */
11672 if (!crtc)
11673 return;
11674
11675 /*
11676 * This is called both by irq handlers and the reset code (to complete
11677 * lost pageflips) so needs the full irqsave spinlocks.
11678 */
11679 spin_lock_irqsave(&dev->event_lock, flags);
11680 work = crtc->flip_work;
11681
11682 if (work != NULL &&
11683 is_mmio_work(work) &&
11684 pageflip_finished(crtc, work))
11685 page_flip_completed(crtc);
11686
11687 spin_unlock_irqrestore(&dev->event_lock, flags);
11688 }
11689
11690 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11691 struct intel_flip_work *work)
11692 {
11693 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11694
11695 /* Ensure that the work item is consistent when activating it ... */
11696 smp_mb__before_atomic();
11697 atomic_set(&work->pending, 1);
11698 }
11699
11700 static int intel_gen2_queue_flip(struct drm_device *dev,
11701 struct drm_crtc *crtc,
11702 struct drm_framebuffer *fb,
11703 struct drm_i915_gem_object *obj,
11704 struct drm_i915_gem_request *req,
11705 uint32_t flags)
11706 {
11707 struct intel_ring *ring = req->ring;
11708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11709 u32 flip_mask;
11710 int ret;
11711
11712 ret = intel_ring_begin(req, 6);
11713 if (ret)
11714 return ret;
11715
11716 /* Can't queue multiple flips, so wait for the previous
11717 * one to finish before executing the next.
11718 */
11719 if (intel_crtc->plane)
11720 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11721 else
11722 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11723 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11724 intel_ring_emit(ring, MI_NOOP);
11725 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11726 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11727 intel_ring_emit(ring, fb->pitches[0]);
11728 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11729 intel_ring_emit(ring, 0); /* aux display base address, unused */
11730
11731 return 0;
11732 }
11733
11734 static int intel_gen3_queue_flip(struct drm_device *dev,
11735 struct drm_crtc *crtc,
11736 struct drm_framebuffer *fb,
11737 struct drm_i915_gem_object *obj,
11738 struct drm_i915_gem_request *req,
11739 uint32_t flags)
11740 {
11741 struct intel_ring *ring = req->ring;
11742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11743 u32 flip_mask;
11744 int ret;
11745
11746 ret = intel_ring_begin(req, 6);
11747 if (ret)
11748 return ret;
11749
11750 if (intel_crtc->plane)
11751 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11752 else
11753 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11754 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11755 intel_ring_emit(ring, MI_NOOP);
11756 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11757 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11758 intel_ring_emit(ring, fb->pitches[0]);
11759 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11760 intel_ring_emit(ring, MI_NOOP);
11761
11762 return 0;
11763 }
11764
11765 static int intel_gen4_queue_flip(struct drm_device *dev,
11766 struct drm_crtc *crtc,
11767 struct drm_framebuffer *fb,
11768 struct drm_i915_gem_object *obj,
11769 struct drm_i915_gem_request *req,
11770 uint32_t flags)
11771 {
11772 struct intel_ring *ring = req->ring;
11773 struct drm_i915_private *dev_priv = to_i915(dev);
11774 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11775 uint32_t pf, pipesrc;
11776 int ret;
11777
11778 ret = intel_ring_begin(req, 4);
11779 if (ret)
11780 return ret;
11781
11782 /* i965+ uses the linear or tiled offsets from the
11783 * Display Registers (which do not change across a page-flip)
11784 * so we need only reprogram the base address.
11785 */
11786 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11787 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11788 intel_ring_emit(ring, fb->pitches[0]);
11789 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset |
11790 intel_fb_modifier_to_tiling(fb->modifier));
11791
11792 /* XXX Enabling the panel-fitter across page-flip is so far
11793 * untested on non-native modes, so ignore it for now.
11794 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11795 */
11796 pf = 0;
11797 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11798 intel_ring_emit(ring, pf | pipesrc);
11799
11800 return 0;
11801 }
11802
11803 static int intel_gen6_queue_flip(struct drm_device *dev,
11804 struct drm_crtc *crtc,
11805 struct drm_framebuffer *fb,
11806 struct drm_i915_gem_object *obj,
11807 struct drm_i915_gem_request *req,
11808 uint32_t flags)
11809 {
11810 struct intel_ring *ring = req->ring;
11811 struct drm_i915_private *dev_priv = to_i915(dev);
11812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11813 uint32_t pf, pipesrc;
11814 int ret;
11815
11816 ret = intel_ring_begin(req, 4);
11817 if (ret)
11818 return ret;
11819
11820 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11821 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11822 intel_ring_emit(ring, fb->pitches[0] |
11823 intel_fb_modifier_to_tiling(fb->modifier));
11824 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11825
11826 /* Contrary to the suggestions in the documentation,
11827 * "Enable Panel Fitter" does not seem to be required when page
11828 * flipping with a non-native mode, and worse causes a normal
11829 * modeset to fail.
11830 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11831 */
11832 pf = 0;
11833 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11834 intel_ring_emit(ring, pf | pipesrc);
11835
11836 return 0;
11837 }
11838
11839 static int intel_gen7_queue_flip(struct drm_device *dev,
11840 struct drm_crtc *crtc,
11841 struct drm_framebuffer *fb,
11842 struct drm_i915_gem_object *obj,
11843 struct drm_i915_gem_request *req,
11844 uint32_t flags)
11845 {
11846 struct drm_i915_private *dev_priv = to_i915(dev);
11847 struct intel_ring *ring = req->ring;
11848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11849 uint32_t plane_bit = 0;
11850 int len, ret;
11851
11852 switch (intel_crtc->plane) {
11853 case PLANE_A:
11854 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11855 break;
11856 case PLANE_B:
11857 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11858 break;
11859 case PLANE_C:
11860 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11861 break;
11862 default:
11863 WARN_ONCE(1, "unknown plane in flip command\n");
11864 return -ENODEV;
11865 }
11866
11867 len = 4;
11868 if (req->engine->id == RCS) {
11869 len += 6;
11870 /*
11871 * On Gen 8, SRM is now taking an extra dword to accommodate
11872 * 48bits addresses, and we need a NOOP for the batch size to
11873 * stay even.
11874 */
11875 if (IS_GEN8(dev_priv))
11876 len += 2;
11877 }
11878
11879 /*
11880 * BSpec MI_DISPLAY_FLIP for IVB:
11881 * "The full packet must be contained within the same cache line."
11882 *
11883 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11884 * cacheline, if we ever start emitting more commands before
11885 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11886 * then do the cacheline alignment, and finally emit the
11887 * MI_DISPLAY_FLIP.
11888 */
11889 ret = intel_ring_cacheline_align(req);
11890 if (ret)
11891 return ret;
11892
11893 ret = intel_ring_begin(req, len);
11894 if (ret)
11895 return ret;
11896
11897 /* Unmask the flip-done completion message. Note that the bspec says that
11898 * we should do this for both the BCS and RCS, and that we must not unmask
11899 * more than one flip event at any time (or ensure that one flip message
11900 * can be sent by waiting for flip-done prior to queueing new flips).
11901 * Experimentation says that BCS works despite DERRMR masking all
11902 * flip-done completion events and that unmasking all planes at once
11903 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11904 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11905 */
11906 if (req->engine->id == RCS) {
11907 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11908 intel_ring_emit_reg(ring, DERRMR);
11909 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11910 DERRMR_PIPEB_PRI_FLIP_DONE |
11911 DERRMR_PIPEC_PRI_FLIP_DONE));
11912 if (IS_GEN8(dev_priv))
11913 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11914 MI_SRM_LRM_GLOBAL_GTT);
11915 else
11916 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11917 MI_SRM_LRM_GLOBAL_GTT);
11918 intel_ring_emit_reg(ring, DERRMR);
11919 intel_ring_emit(ring,
11920 i915_ggtt_offset(req->engine->scratch) + 256);
11921 if (IS_GEN8(dev_priv)) {
11922 intel_ring_emit(ring, 0);
11923 intel_ring_emit(ring, MI_NOOP);
11924 }
11925 }
11926
11927 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11928 intel_ring_emit(ring, fb->pitches[0] |
11929 intel_fb_modifier_to_tiling(fb->modifier));
11930 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11931 intel_ring_emit(ring, (MI_NOOP));
11932
11933 return 0;
11934 }
11935
11936 static bool use_mmio_flip(struct intel_engine_cs *engine,
11937 struct drm_i915_gem_object *obj)
11938 {
11939 /*
11940 * This is not being used for older platforms, because
11941 * non-availability of flip done interrupt forces us to use
11942 * CS flips. Older platforms derive flip done using some clever
11943 * tricks involving the flip_pending status bits and vblank irqs.
11944 * So using MMIO flips there would disrupt this mechanism.
11945 */
11946
11947 if (engine == NULL)
11948 return true;
11949
11950 if (INTEL_GEN(engine->i915) < 5)
11951 return false;
11952
11953 if (i915.use_mmio_flip < 0)
11954 return false;
11955 else if (i915.use_mmio_flip > 0)
11956 return true;
11957 else if (i915.enable_execlists)
11958 return true;
11959
11960 return engine != i915_gem_object_last_write_engine(obj);
11961 }
11962
11963 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11964 unsigned int rotation,
11965 struct intel_flip_work *work)
11966 {
11967 struct drm_device *dev = intel_crtc->base.dev;
11968 struct drm_i915_private *dev_priv = to_i915(dev);
11969 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11970 const enum pipe pipe = intel_crtc->pipe;
11971 u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
11972
11973 ctl = I915_READ(PLANE_CTL(pipe, 0));
11974 ctl &= ~PLANE_CTL_TILED_MASK;
11975 switch (fb->modifier) {
11976 case DRM_FORMAT_MOD_NONE:
11977 break;
11978 case I915_FORMAT_MOD_X_TILED:
11979 ctl |= PLANE_CTL_TILED_X;
11980 break;
11981 case I915_FORMAT_MOD_Y_TILED:
11982 ctl |= PLANE_CTL_TILED_Y;
11983 break;
11984 case I915_FORMAT_MOD_Yf_TILED:
11985 ctl |= PLANE_CTL_TILED_YF;
11986 break;
11987 default:
11988 MISSING_CASE(fb->modifier);
11989 }
11990
11991 /*
11992 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11993 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11994 */
11995 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11996 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11997
11998 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11999 POSTING_READ(PLANE_SURF(pipe, 0));
12000 }
12001
12002 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
12003 struct intel_flip_work *work)
12004 {
12005 struct drm_device *dev = intel_crtc->base.dev;
12006 struct drm_i915_private *dev_priv = to_i915(dev);
12007 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
12008 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
12009 u32 dspcntr;
12010
12011 dspcntr = I915_READ(reg);
12012
12013 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
12014 dspcntr |= DISPPLANE_TILED;
12015 else
12016 dspcntr &= ~DISPPLANE_TILED;
12017
12018 I915_WRITE(reg, dspcntr);
12019
12020 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
12021 POSTING_READ(DSPSURF(intel_crtc->plane));
12022 }
12023
12024 static void intel_mmio_flip_work_func(struct work_struct *w)
12025 {
12026 struct intel_flip_work *work =
12027 container_of(w, struct intel_flip_work, mmio_work);
12028 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
12029 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12030 struct intel_framebuffer *intel_fb =
12031 to_intel_framebuffer(crtc->base.primary->fb);
12032 struct drm_i915_gem_object *obj = intel_fb->obj;
12033
12034 WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
12035
12036 intel_pipe_update_start(crtc);
12037
12038 if (INTEL_GEN(dev_priv) >= 9)
12039 skl_do_mmio_flip(crtc, work->rotation, work);
12040 else
12041 /* use_mmio_flip() retricts MMIO flips to ilk+ */
12042 ilk_do_mmio_flip(crtc, work);
12043
12044 intel_pipe_update_end(crtc, work);
12045 }
12046
12047 static int intel_default_queue_flip(struct drm_device *dev,
12048 struct drm_crtc *crtc,
12049 struct drm_framebuffer *fb,
12050 struct drm_i915_gem_object *obj,
12051 struct drm_i915_gem_request *req,
12052 uint32_t flags)
12053 {
12054 return -ENODEV;
12055 }
12056
12057 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
12058 struct intel_crtc *intel_crtc,
12059 struct intel_flip_work *work)
12060 {
12061 u32 addr, vblank;
12062
12063 if (!atomic_read(&work->pending))
12064 return false;
12065
12066 smp_rmb();
12067
12068 vblank = intel_crtc_get_vblank_counter(intel_crtc);
12069 if (work->flip_ready_vblank == 0) {
12070 if (work->flip_queued_req &&
12071 !i915_gem_request_completed(work->flip_queued_req))
12072 return false;
12073
12074 work->flip_ready_vblank = vblank;
12075 }
12076
12077 if (vblank - work->flip_ready_vblank < 3)
12078 return false;
12079
12080 /* Potential stall - if we see that the flip has happened,
12081 * assume a missed interrupt. */
12082 if (INTEL_GEN(dev_priv) >= 4)
12083 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
12084 else
12085 addr = I915_READ(DSPADDR(intel_crtc->plane));
12086
12087 /* There is a potential issue here with a false positive after a flip
12088 * to the same address. We could address this by checking for a
12089 * non-incrementing frame counter.
12090 */
12091 return addr == work->gtt_offset;
12092 }
12093
12094 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
12095 {
12096 struct drm_device *dev = &dev_priv->drm;
12097 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12098 struct intel_flip_work *work;
12099
12100 WARN_ON(!in_interrupt());
12101
12102 if (crtc == NULL)
12103 return;
12104
12105 spin_lock(&dev->event_lock);
12106 work = crtc->flip_work;
12107
12108 if (work != NULL && !is_mmio_work(work) &&
12109 __pageflip_stall_check_cs(dev_priv, crtc, work)) {
12110 WARN_ONCE(1,
12111 "Kicking stuck page flip: queued at %d, now %d\n",
12112 work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
12113 page_flip_completed(crtc);
12114 work = NULL;
12115 }
12116
12117 if (work != NULL && !is_mmio_work(work) &&
12118 intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
12119 intel_queue_rps_boost_for_request(work->flip_queued_req);
12120 spin_unlock(&dev->event_lock);
12121 }
12122
12123 static int intel_crtc_page_flip(struct drm_crtc *crtc,
12124 struct drm_framebuffer *fb,
12125 struct drm_pending_vblank_event *event,
12126 uint32_t page_flip_flags)
12127 {
12128 struct drm_device *dev = crtc->dev;
12129 struct drm_i915_private *dev_priv = to_i915(dev);
12130 struct drm_framebuffer *old_fb = crtc->primary->fb;
12131 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12133 struct drm_plane *primary = crtc->primary;
12134 enum pipe pipe = intel_crtc->pipe;
12135 struct intel_flip_work *work;
12136 struct intel_engine_cs *engine;
12137 bool mmio_flip;
12138 struct drm_i915_gem_request *request;
12139 struct i915_vma *vma;
12140 int ret;
12141
12142 /*
12143 * drm_mode_page_flip_ioctl() should already catch this, but double
12144 * check to be safe. In the future we may enable pageflipping from
12145 * a disabled primary plane.
12146 */
12147 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
12148 return -EBUSY;
12149
12150 /* Can't change pixel format via MI display flips. */
12151 if (fb->pixel_format != crtc->primary->fb->pixel_format)
12152 return -EINVAL;
12153
12154 /*
12155 * TILEOFF/LINOFF registers can't be changed via MI display flips.
12156 * Note that pitch changes could also affect these register.
12157 */
12158 if (INTEL_GEN(dev_priv) > 3 &&
12159 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
12160 fb->pitches[0] != crtc->primary->fb->pitches[0]))
12161 return -EINVAL;
12162
12163 if (i915_terminally_wedged(&dev_priv->gpu_error))
12164 goto out_hang;
12165
12166 work = kzalloc(sizeof(*work), GFP_KERNEL);
12167 if (work == NULL)
12168 return -ENOMEM;
12169
12170 work->event = event;
12171 work->crtc = crtc;
12172 work->old_fb = old_fb;
12173 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
12174
12175 ret = drm_crtc_vblank_get(crtc);
12176 if (ret)
12177 goto free_work;
12178
12179 /* We borrow the event spin lock for protecting flip_work */
12180 spin_lock_irq(&dev->event_lock);
12181 if (intel_crtc->flip_work) {
12182 /* Before declaring the flip queue wedged, check if
12183 * the hardware completed the operation behind our backs.
12184 */
12185 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
12186 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
12187 page_flip_completed(intel_crtc);
12188 } else {
12189 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
12190 spin_unlock_irq(&dev->event_lock);
12191
12192 drm_crtc_vblank_put(crtc);
12193 kfree(work);
12194 return -EBUSY;
12195 }
12196 }
12197 intel_crtc->flip_work = work;
12198 spin_unlock_irq(&dev->event_lock);
12199
12200 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
12201 flush_workqueue(dev_priv->wq);
12202
12203 /* Reference the objects for the scheduled work. */
12204 drm_framebuffer_reference(work->old_fb);
12205
12206 crtc->primary->fb = fb;
12207 update_state_fb(crtc->primary);
12208
12209 work->pending_flip_obj = i915_gem_object_get(obj);
12210
12211 ret = i915_mutex_lock_interruptible(dev);
12212 if (ret)
12213 goto cleanup;
12214
12215 intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
12216 if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) {
12217 ret = -EIO;
12218 goto unlock;
12219 }
12220
12221 atomic_inc(&intel_crtc->unpin_work_count);
12222
12223 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
12224 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
12225
12226 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
12227 engine = dev_priv->engine[BCS];
12228 if (fb->modifier != old_fb->modifier)
12229 /* vlv: DISPLAY_FLIP fails to change tiling */
12230 engine = NULL;
12231 } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
12232 engine = dev_priv->engine[BCS];
12233 } else if (INTEL_GEN(dev_priv) >= 7) {
12234 engine = i915_gem_object_last_write_engine(obj);
12235 if (engine == NULL || engine->id != RCS)
12236 engine = dev_priv->engine[BCS];
12237 } else {
12238 engine = dev_priv->engine[RCS];
12239 }
12240
12241 mmio_flip = use_mmio_flip(engine, obj);
12242
12243 vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
12244 if (IS_ERR(vma)) {
12245 ret = PTR_ERR(vma);
12246 goto cleanup_pending;
12247 }
12248
12249 work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation);
12250 work->gtt_offset += intel_crtc->dspaddr_offset;
12251 work->rotation = crtc->primary->state->rotation;
12252
12253 /*
12254 * There's the potential that the next frame will not be compatible with
12255 * FBC, so we want to call pre_update() before the actual page flip.
12256 * The problem is that pre_update() caches some information about the fb
12257 * object, so we want to do this only after the object is pinned. Let's
12258 * be on the safe side and do this immediately before scheduling the
12259 * flip.
12260 */
12261 intel_fbc_pre_update(intel_crtc, intel_crtc->config,
12262 to_intel_plane_state(primary->state));
12263
12264 if (mmio_flip) {
12265 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
12266 queue_work(system_unbound_wq, &work->mmio_work);
12267 } else {
12268 request = i915_gem_request_alloc(engine, engine->last_context);
12269 if (IS_ERR(request)) {
12270 ret = PTR_ERR(request);
12271 goto cleanup_unpin;
12272 }
12273
12274 ret = i915_gem_request_await_object(request, obj, false);
12275 if (ret)
12276 goto cleanup_request;
12277
12278 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
12279 page_flip_flags);
12280 if (ret)
12281 goto cleanup_request;
12282
12283 intel_mark_page_flip_active(intel_crtc, work);
12284
12285 work->flip_queued_req = i915_gem_request_get(request);
12286 i915_add_request_no_flush(request);
12287 }
12288
12289 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
12290 i915_gem_track_fb(intel_fb_obj(old_fb), obj,
12291 to_intel_plane(primary)->frontbuffer_bit);
12292 mutex_unlock(&dev->struct_mutex);
12293
12294 intel_frontbuffer_flip_prepare(to_i915(dev),
12295 to_intel_plane(primary)->frontbuffer_bit);
12296
12297 trace_i915_flip_request(intel_crtc->plane, obj);
12298
12299 return 0;
12300
12301 cleanup_request:
12302 i915_add_request_no_flush(request);
12303 cleanup_unpin:
12304 intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
12305 cleanup_pending:
12306 atomic_dec(&intel_crtc->unpin_work_count);
12307 unlock:
12308 mutex_unlock(&dev->struct_mutex);
12309 cleanup:
12310 crtc->primary->fb = old_fb;
12311 update_state_fb(crtc->primary);
12312
12313 i915_gem_object_put(obj);
12314 drm_framebuffer_unreference(work->old_fb);
12315
12316 spin_lock_irq(&dev->event_lock);
12317 intel_crtc->flip_work = NULL;
12318 spin_unlock_irq(&dev->event_lock);
12319
12320 drm_crtc_vblank_put(crtc);
12321 free_work:
12322 kfree(work);
12323
12324 if (ret == -EIO) {
12325 struct drm_atomic_state *state;
12326 struct drm_plane_state *plane_state;
12327
12328 out_hang:
12329 state = drm_atomic_state_alloc(dev);
12330 if (!state)
12331 return -ENOMEM;
12332 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
12333
12334 retry:
12335 plane_state = drm_atomic_get_plane_state(state, primary);
12336 ret = PTR_ERR_OR_ZERO(plane_state);
12337 if (!ret) {
12338 drm_atomic_set_fb_for_plane(plane_state, fb);
12339
12340 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
12341 if (!ret)
12342 ret = drm_atomic_commit(state);
12343 }
12344
12345 if (ret == -EDEADLK) {
12346 drm_modeset_backoff(state->acquire_ctx);
12347 drm_atomic_state_clear(state);
12348 goto retry;
12349 }
12350
12351 drm_atomic_state_put(state);
12352
12353 if (ret == 0 && event) {
12354 spin_lock_irq(&dev->event_lock);
12355 drm_crtc_send_vblank_event(crtc, event);
12356 spin_unlock_irq(&dev->event_lock);
12357 }
12358 }
12359 return ret;
12360 }
12361
12362
12363 /**
12364 * intel_wm_need_update - Check whether watermarks need updating
12365 * @plane: drm plane
12366 * @state: new plane state
12367 *
12368 * Check current plane state versus the new one to determine whether
12369 * watermarks need to be recalculated.
12370 *
12371 * Returns true or false.
12372 */
12373 static bool intel_wm_need_update(struct drm_plane *plane,
12374 struct drm_plane_state *state)
12375 {
12376 struct intel_plane_state *new = to_intel_plane_state(state);
12377 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
12378
12379 /* Update watermarks on tiling or size changes. */
12380 if (new->base.visible != cur->base.visible)
12381 return true;
12382
12383 if (!cur->base.fb || !new->base.fb)
12384 return false;
12385
12386 if (cur->base.fb->modifier != new->base.fb->modifier ||
12387 cur->base.rotation != new->base.rotation ||
12388 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
12389 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
12390 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
12391 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
12392 return true;
12393
12394 return false;
12395 }
12396
12397 static bool needs_scaling(struct intel_plane_state *state)
12398 {
12399 int src_w = drm_rect_width(&state->base.src) >> 16;
12400 int src_h = drm_rect_height(&state->base.src) >> 16;
12401 int dst_w = drm_rect_width(&state->base.dst);
12402 int dst_h = drm_rect_height(&state->base.dst);
12403
12404 return (src_w != dst_w || src_h != dst_h);
12405 }
12406
12407 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
12408 struct drm_plane_state *plane_state)
12409 {
12410 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
12411 struct drm_crtc *crtc = crtc_state->crtc;
12412 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12413 struct drm_plane *plane = plane_state->plane;
12414 struct drm_device *dev = crtc->dev;
12415 struct drm_i915_private *dev_priv = to_i915(dev);
12416 struct intel_plane_state *old_plane_state =
12417 to_intel_plane_state(plane->state);
12418 bool mode_changed = needs_modeset(crtc_state);
12419 bool was_crtc_enabled = crtc->state->active;
12420 bool is_crtc_enabled = crtc_state->active;
12421 bool turn_off, turn_on, visible, was_visible;
12422 struct drm_framebuffer *fb = plane_state->fb;
12423 int ret;
12424
12425 if (INTEL_GEN(dev_priv) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
12426 ret = skl_update_scaler_plane(
12427 to_intel_crtc_state(crtc_state),
12428 to_intel_plane_state(plane_state));
12429 if (ret)
12430 return ret;
12431 }
12432
12433 was_visible = old_plane_state->base.visible;
12434 visible = to_intel_plane_state(plane_state)->base.visible;
12435
12436 if (!was_crtc_enabled && WARN_ON(was_visible))
12437 was_visible = false;
12438
12439 /*
12440 * Visibility is calculated as if the crtc was on, but
12441 * after scaler setup everything depends on it being off
12442 * when the crtc isn't active.
12443 *
12444 * FIXME this is wrong for watermarks. Watermarks should also
12445 * be computed as if the pipe would be active. Perhaps move
12446 * per-plane wm computation to the .check_plane() hook, and
12447 * only combine the results from all planes in the current place?
12448 */
12449 if (!is_crtc_enabled)
12450 to_intel_plane_state(plane_state)->base.visible = visible = false;
12451
12452 if (!was_visible && !visible)
12453 return 0;
12454
12455 if (fb != old_plane_state->base.fb)
12456 pipe_config->fb_changed = true;
12457
12458 turn_off = was_visible && (!visible || mode_changed);
12459 turn_on = visible && (!was_visible || mode_changed);
12460
12461 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
12462 intel_crtc->base.base.id,
12463 intel_crtc->base.name,
12464 plane->base.id, plane->name,
12465 fb ? fb->base.id : -1);
12466
12467 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12468 plane->base.id, plane->name,
12469 was_visible, visible,
12470 turn_off, turn_on, mode_changed);
12471
12472 if (turn_on) {
12473 pipe_config->update_wm_pre = true;
12474
12475 /* must disable cxsr around plane enable/disable */
12476 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12477 pipe_config->disable_cxsr = true;
12478 } else if (turn_off) {
12479 pipe_config->update_wm_post = true;
12480
12481 /* must disable cxsr around plane enable/disable */
12482 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12483 pipe_config->disable_cxsr = true;
12484 } else if (intel_wm_need_update(plane, plane_state)) {
12485 /* FIXME bollocks */
12486 pipe_config->update_wm_pre = true;
12487 pipe_config->update_wm_post = true;
12488 }
12489
12490 /* Pre-gen9 platforms need two-step watermark updates */
12491 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12492 INTEL_GEN(dev_priv) < 9 && dev_priv->display.optimize_watermarks)
12493 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12494
12495 if (visible || was_visible)
12496 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
12497
12498 /*
12499 * WaCxSRDisabledForSpriteScaling:ivb
12500 *
12501 * cstate->update_wm was already set above, so this flag will
12502 * take effect when we commit and program watermarks.
12503 */
12504 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev_priv) &&
12505 needs_scaling(to_intel_plane_state(plane_state)) &&
12506 !needs_scaling(old_plane_state))
12507 pipe_config->disable_lp_wm = true;
12508
12509 return 0;
12510 }
12511
12512 static bool encoders_cloneable(const struct intel_encoder *a,
12513 const struct intel_encoder *b)
12514 {
12515 /* masks could be asymmetric, so check both ways */
12516 return a == b || (a->cloneable & (1 << b->type) &&
12517 b->cloneable & (1 << a->type));
12518 }
12519
12520 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12521 struct intel_crtc *crtc,
12522 struct intel_encoder *encoder)
12523 {
12524 struct intel_encoder *source_encoder;
12525 struct drm_connector *connector;
12526 struct drm_connector_state *connector_state;
12527 int i;
12528
12529 for_each_connector_in_state(state, connector, connector_state, i) {
12530 if (connector_state->crtc != &crtc->base)
12531 continue;
12532
12533 source_encoder =
12534 to_intel_encoder(connector_state->best_encoder);
12535 if (!encoders_cloneable(encoder, source_encoder))
12536 return false;
12537 }
12538
12539 return true;
12540 }
12541
12542 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12543 struct drm_crtc_state *crtc_state)
12544 {
12545 struct drm_device *dev = crtc->dev;
12546 struct drm_i915_private *dev_priv = to_i915(dev);
12547 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12548 struct intel_crtc_state *pipe_config =
12549 to_intel_crtc_state(crtc_state);
12550 struct drm_atomic_state *state = crtc_state->state;
12551 int ret;
12552 bool mode_changed = needs_modeset(crtc_state);
12553
12554 if (mode_changed && !crtc_state->active)
12555 pipe_config->update_wm_post = true;
12556
12557 if (mode_changed && crtc_state->enable &&
12558 dev_priv->display.crtc_compute_clock &&
12559 !WARN_ON(pipe_config->shared_dpll)) {
12560 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12561 pipe_config);
12562 if (ret)
12563 return ret;
12564 }
12565
12566 if (crtc_state->color_mgmt_changed) {
12567 ret = intel_color_check(crtc, crtc_state);
12568 if (ret)
12569 return ret;
12570
12571 /*
12572 * Changing color management on Intel hardware is
12573 * handled as part of planes update.
12574 */
12575 crtc_state->planes_changed = true;
12576 }
12577
12578 ret = 0;
12579 if (dev_priv->display.compute_pipe_wm) {
12580 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12581 if (ret) {
12582 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12583 return ret;
12584 }
12585 }
12586
12587 if (dev_priv->display.compute_intermediate_wm &&
12588 !to_intel_atomic_state(state)->skip_intermediate_wm) {
12589 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12590 return 0;
12591
12592 /*
12593 * Calculate 'intermediate' watermarks that satisfy both the
12594 * old state and the new state. We can program these
12595 * immediately.
12596 */
12597 ret = dev_priv->display.compute_intermediate_wm(dev,
12598 intel_crtc,
12599 pipe_config);
12600 if (ret) {
12601 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12602 return ret;
12603 }
12604 } else if (dev_priv->display.compute_intermediate_wm) {
12605 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12606 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12607 }
12608
12609 if (INTEL_GEN(dev_priv) >= 9) {
12610 if (mode_changed)
12611 ret = skl_update_scaler_crtc(pipe_config);
12612
12613 if (!ret)
12614 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12615 pipe_config);
12616 }
12617
12618 return ret;
12619 }
12620
12621 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12622 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12623 .atomic_begin = intel_begin_crtc_commit,
12624 .atomic_flush = intel_finish_crtc_commit,
12625 .atomic_check = intel_crtc_atomic_check,
12626 };
12627
12628 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12629 {
12630 struct intel_connector *connector;
12631
12632 for_each_intel_connector(dev, connector) {
12633 if (connector->base.state->crtc)
12634 drm_connector_unreference(&connector->base);
12635
12636 if (connector->base.encoder) {
12637 connector->base.state->best_encoder =
12638 connector->base.encoder;
12639 connector->base.state->crtc =
12640 connector->base.encoder->crtc;
12641
12642 drm_connector_reference(&connector->base);
12643 } else {
12644 connector->base.state->best_encoder = NULL;
12645 connector->base.state->crtc = NULL;
12646 }
12647 }
12648 }
12649
12650 static void
12651 connected_sink_compute_bpp(struct intel_connector *connector,
12652 struct intel_crtc_state *pipe_config)
12653 {
12654 const struct drm_display_info *info = &connector->base.display_info;
12655 int bpp = pipe_config->pipe_bpp;
12656
12657 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12658 connector->base.base.id,
12659 connector->base.name);
12660
12661 /* Don't use an invalid EDID bpc value */
12662 if (info->bpc != 0 && info->bpc * 3 < bpp) {
12663 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12664 bpp, info->bpc * 3);
12665 pipe_config->pipe_bpp = info->bpc * 3;
12666 }
12667
12668 /* Clamp bpp to 8 on screens without EDID 1.4 */
12669 if (info->bpc == 0 && bpp > 24) {
12670 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12671 bpp);
12672 pipe_config->pipe_bpp = 24;
12673 }
12674 }
12675
12676 static int
12677 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12678 struct intel_crtc_state *pipe_config)
12679 {
12680 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12681 struct drm_atomic_state *state;
12682 struct drm_connector *connector;
12683 struct drm_connector_state *connector_state;
12684 int bpp, i;
12685
12686 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
12687 IS_CHERRYVIEW(dev_priv)))
12688 bpp = 10*3;
12689 else if (INTEL_GEN(dev_priv) >= 5)
12690 bpp = 12*3;
12691 else
12692 bpp = 8*3;
12693
12694
12695 pipe_config->pipe_bpp = bpp;
12696
12697 state = pipe_config->base.state;
12698
12699 /* Clamp display bpp to EDID value */
12700 for_each_connector_in_state(state, connector, connector_state, i) {
12701 if (connector_state->crtc != &crtc->base)
12702 continue;
12703
12704 connected_sink_compute_bpp(to_intel_connector(connector),
12705 pipe_config);
12706 }
12707
12708 return bpp;
12709 }
12710
12711 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12712 {
12713 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12714 "type: 0x%x flags: 0x%x\n",
12715 mode->crtc_clock,
12716 mode->crtc_hdisplay, mode->crtc_hsync_start,
12717 mode->crtc_hsync_end, mode->crtc_htotal,
12718 mode->crtc_vdisplay, mode->crtc_vsync_start,
12719 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12720 }
12721
12722 static inline void
12723 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
12724 unsigned int lane_count, struct intel_link_m_n *m_n)
12725 {
12726 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12727 id, lane_count,
12728 m_n->gmch_m, m_n->gmch_n,
12729 m_n->link_m, m_n->link_n, m_n->tu);
12730 }
12731
12732 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12733 struct intel_crtc_state *pipe_config,
12734 const char *context)
12735 {
12736 struct drm_device *dev = crtc->base.dev;
12737 struct drm_i915_private *dev_priv = to_i915(dev);
12738 struct drm_plane *plane;
12739 struct intel_plane *intel_plane;
12740 struct intel_plane_state *state;
12741 struct drm_framebuffer *fb;
12742
12743 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
12744 crtc->base.base.id, crtc->base.name, context);
12745
12746 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
12747 transcoder_name(pipe_config->cpu_transcoder),
12748 pipe_config->pipe_bpp, pipe_config->dither);
12749
12750 if (pipe_config->has_pch_encoder)
12751 intel_dump_m_n_config(pipe_config, "fdi",
12752 pipe_config->fdi_lanes,
12753 &pipe_config->fdi_m_n);
12754
12755 if (intel_crtc_has_dp_encoder(pipe_config)) {
12756 intel_dump_m_n_config(pipe_config, "dp m_n",
12757 pipe_config->lane_count, &pipe_config->dp_m_n);
12758 if (pipe_config->has_drrs)
12759 intel_dump_m_n_config(pipe_config, "dp m2_n2",
12760 pipe_config->lane_count,
12761 &pipe_config->dp_m2_n2);
12762 }
12763
12764 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12765 pipe_config->has_audio, pipe_config->has_infoframe);
12766
12767 DRM_DEBUG_KMS("requested mode:\n");
12768 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12769 DRM_DEBUG_KMS("adjusted mode:\n");
12770 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12771 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12772 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d\n",
12773 pipe_config->port_clock,
12774 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12775
12776 if (INTEL_GEN(dev_priv) >= 9)
12777 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12778 crtc->num_scalers,
12779 pipe_config->scaler_state.scaler_users,
12780 pipe_config->scaler_state.scaler_id);
12781
12782 if (HAS_GMCH_DISPLAY(dev_priv))
12783 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12784 pipe_config->gmch_pfit.control,
12785 pipe_config->gmch_pfit.pgm_ratios,
12786 pipe_config->gmch_pfit.lvds_border_bits);
12787 else
12788 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12789 pipe_config->pch_pfit.pos,
12790 pipe_config->pch_pfit.size,
12791 enableddisabled(pipe_config->pch_pfit.enabled));
12792
12793 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
12794 pipe_config->ips_enabled, pipe_config->double_wide);
12795
12796 if (IS_BROXTON(dev_priv)) {
12797 DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12798 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12799 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12800 pipe_config->dpll_hw_state.ebb0,
12801 pipe_config->dpll_hw_state.ebb4,
12802 pipe_config->dpll_hw_state.pll0,
12803 pipe_config->dpll_hw_state.pll1,
12804 pipe_config->dpll_hw_state.pll2,
12805 pipe_config->dpll_hw_state.pll3,
12806 pipe_config->dpll_hw_state.pll6,
12807 pipe_config->dpll_hw_state.pll8,
12808 pipe_config->dpll_hw_state.pll9,
12809 pipe_config->dpll_hw_state.pll10,
12810 pipe_config->dpll_hw_state.pcsdw12);
12811 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
12812 DRM_DEBUG_KMS("dpll_hw_state: "
12813 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12814 pipe_config->dpll_hw_state.ctrl1,
12815 pipe_config->dpll_hw_state.cfgcr1,
12816 pipe_config->dpll_hw_state.cfgcr2);
12817 } else if (HAS_DDI(dev_priv)) {
12818 DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12819 pipe_config->dpll_hw_state.wrpll,
12820 pipe_config->dpll_hw_state.spll);
12821 } else {
12822 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12823 "fp0: 0x%x, fp1: 0x%x\n",
12824 pipe_config->dpll_hw_state.dpll,
12825 pipe_config->dpll_hw_state.dpll_md,
12826 pipe_config->dpll_hw_state.fp0,
12827 pipe_config->dpll_hw_state.fp1);
12828 }
12829
12830 DRM_DEBUG_KMS("planes on this crtc\n");
12831 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12832 struct drm_format_name_buf format_name;
12833 intel_plane = to_intel_plane(plane);
12834 if (intel_plane->pipe != crtc->pipe)
12835 continue;
12836
12837 state = to_intel_plane_state(plane->state);
12838 fb = state->base.fb;
12839 if (!fb) {
12840 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12841 plane->base.id, plane->name, state->scaler_id);
12842 continue;
12843 }
12844
12845 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
12846 plane->base.id, plane->name,
12847 fb->base.id, fb->width, fb->height,
12848 drm_get_format_name(fb->pixel_format, &format_name));
12849 if (INTEL_GEN(dev_priv) >= 9)
12850 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12851 state->scaler_id,
12852 state->base.src.x1 >> 16,
12853 state->base.src.y1 >> 16,
12854 drm_rect_width(&state->base.src) >> 16,
12855 drm_rect_height(&state->base.src) >> 16,
12856 state->base.dst.x1, state->base.dst.y1,
12857 drm_rect_width(&state->base.dst),
12858 drm_rect_height(&state->base.dst));
12859 }
12860 }
12861
12862 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12863 {
12864 struct drm_device *dev = state->dev;
12865 struct drm_connector *connector;
12866 unsigned int used_ports = 0;
12867 unsigned int used_mst_ports = 0;
12868
12869 /*
12870 * Walk the connector list instead of the encoder
12871 * list to detect the problem on ddi platforms
12872 * where there's just one encoder per digital port.
12873 */
12874 drm_for_each_connector(connector, dev) {
12875 struct drm_connector_state *connector_state;
12876 struct intel_encoder *encoder;
12877
12878 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12879 if (!connector_state)
12880 connector_state = connector->state;
12881
12882 if (!connector_state->best_encoder)
12883 continue;
12884
12885 encoder = to_intel_encoder(connector_state->best_encoder);
12886
12887 WARN_ON(!connector_state->crtc);
12888
12889 switch (encoder->type) {
12890 unsigned int port_mask;
12891 case INTEL_OUTPUT_UNKNOWN:
12892 if (WARN_ON(!HAS_DDI(to_i915(dev))))
12893 break;
12894 case INTEL_OUTPUT_DP:
12895 case INTEL_OUTPUT_HDMI:
12896 case INTEL_OUTPUT_EDP:
12897 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12898
12899 /* the same port mustn't appear more than once */
12900 if (used_ports & port_mask)
12901 return false;
12902
12903 used_ports |= port_mask;
12904 break;
12905 case INTEL_OUTPUT_DP_MST:
12906 used_mst_ports |=
12907 1 << enc_to_mst(&encoder->base)->primary->port;
12908 break;
12909 default:
12910 break;
12911 }
12912 }
12913
12914 /* can't mix MST and SST/HDMI on the same port */
12915 if (used_ports & used_mst_ports)
12916 return false;
12917
12918 return true;
12919 }
12920
12921 static void
12922 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12923 {
12924 struct drm_crtc_state tmp_state;
12925 struct intel_crtc_scaler_state scaler_state;
12926 struct intel_dpll_hw_state dpll_hw_state;
12927 struct intel_shared_dpll *shared_dpll;
12928 bool force_thru;
12929
12930 /* FIXME: before the switch to atomic started, a new pipe_config was
12931 * kzalloc'd. Code that depends on any field being zero should be
12932 * fixed, so that the crtc_state can be safely duplicated. For now,
12933 * only fields that are know to not cause problems are preserved. */
12934
12935 tmp_state = crtc_state->base;
12936 scaler_state = crtc_state->scaler_state;
12937 shared_dpll = crtc_state->shared_dpll;
12938 dpll_hw_state = crtc_state->dpll_hw_state;
12939 force_thru = crtc_state->pch_pfit.force_thru;
12940
12941 memset(crtc_state, 0, sizeof *crtc_state);
12942
12943 crtc_state->base = tmp_state;
12944 crtc_state->scaler_state = scaler_state;
12945 crtc_state->shared_dpll = shared_dpll;
12946 crtc_state->dpll_hw_state = dpll_hw_state;
12947 crtc_state->pch_pfit.force_thru = force_thru;
12948 }
12949
12950 static int
12951 intel_modeset_pipe_config(struct drm_crtc *crtc,
12952 struct intel_crtc_state *pipe_config)
12953 {
12954 struct drm_atomic_state *state = pipe_config->base.state;
12955 struct intel_encoder *encoder;
12956 struct drm_connector *connector;
12957 struct drm_connector_state *connector_state;
12958 int base_bpp, ret = -EINVAL;
12959 int i;
12960 bool retry = true;
12961
12962 clear_intel_crtc_state(pipe_config);
12963
12964 pipe_config->cpu_transcoder =
12965 (enum transcoder) to_intel_crtc(crtc)->pipe;
12966
12967 /*
12968 * Sanitize sync polarity flags based on requested ones. If neither
12969 * positive or negative polarity is requested, treat this as meaning
12970 * negative polarity.
12971 */
12972 if (!(pipe_config->base.adjusted_mode.flags &
12973 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12974 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12975
12976 if (!(pipe_config->base.adjusted_mode.flags &
12977 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12978 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12979
12980 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12981 pipe_config);
12982 if (base_bpp < 0)
12983 goto fail;
12984
12985 /*
12986 * Determine the real pipe dimensions. Note that stereo modes can
12987 * increase the actual pipe size due to the frame doubling and
12988 * insertion of additional space for blanks between the frame. This
12989 * is stored in the crtc timings. We use the requested mode to do this
12990 * computation to clearly distinguish it from the adjusted mode, which
12991 * can be changed by the connectors in the below retry loop.
12992 */
12993 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12994 &pipe_config->pipe_src_w,
12995 &pipe_config->pipe_src_h);
12996
12997 for_each_connector_in_state(state, connector, connector_state, i) {
12998 if (connector_state->crtc != crtc)
12999 continue;
13000
13001 encoder = to_intel_encoder(connector_state->best_encoder);
13002
13003 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
13004 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
13005 goto fail;
13006 }
13007
13008 /*
13009 * Determine output_types before calling the .compute_config()
13010 * hooks so that the hooks can use this information safely.
13011 */
13012 pipe_config->output_types |= 1 << encoder->type;
13013 }
13014
13015 encoder_retry:
13016 /* Ensure the port clock defaults are reset when retrying. */
13017 pipe_config->port_clock = 0;
13018 pipe_config->pixel_multiplier = 1;
13019
13020 /* Fill in default crtc timings, allow encoders to overwrite them. */
13021 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
13022 CRTC_STEREO_DOUBLE);
13023
13024 /* Pass our mode to the connectors and the CRTC to give them a chance to
13025 * adjust it according to limitations or connector properties, and also
13026 * a chance to reject the mode entirely.
13027 */
13028 for_each_connector_in_state(state, connector, connector_state, i) {
13029 if (connector_state->crtc != crtc)
13030 continue;
13031
13032 encoder = to_intel_encoder(connector_state->best_encoder);
13033
13034 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
13035 DRM_DEBUG_KMS("Encoder config failure\n");
13036 goto fail;
13037 }
13038 }
13039
13040 /* Set default port clock if not overwritten by the encoder. Needs to be
13041 * done afterwards in case the encoder adjusts the mode. */
13042 if (!pipe_config->port_clock)
13043 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
13044 * pipe_config->pixel_multiplier;
13045
13046 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13047 if (ret < 0) {
13048 DRM_DEBUG_KMS("CRTC fixup failed\n");
13049 goto fail;
13050 }
13051
13052 if (ret == RETRY) {
13053 if (WARN(!retry, "loop in pipe configuration computation\n")) {
13054 ret = -EINVAL;
13055 goto fail;
13056 }
13057
13058 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
13059 retry = false;
13060 goto encoder_retry;
13061 }
13062
13063 /* Dithering seems to not pass-through bits correctly when it should, so
13064 * only enable it on 6bpc panels. */
13065 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
13066 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13067 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13068
13069 fail:
13070 return ret;
13071 }
13072
13073 static void
13074 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
13075 {
13076 struct drm_crtc *crtc;
13077 struct drm_crtc_state *crtc_state;
13078 int i;
13079
13080 /* Double check state. */
13081 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13082 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
13083
13084 /* Update hwmode for vblank functions */
13085 if (crtc->state->active)
13086 crtc->hwmode = crtc->state->adjusted_mode;
13087 else
13088 crtc->hwmode.crtc_clock = 0;
13089
13090 /*
13091 * Update legacy state to satisfy fbc code. This can
13092 * be removed when fbc uses the atomic state.
13093 */
13094 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
13095 struct drm_plane_state *plane_state = crtc->primary->state;
13096
13097 crtc->primary->fb = plane_state->fb;
13098 crtc->x = plane_state->src_x >> 16;
13099 crtc->y = plane_state->src_y >> 16;
13100 }
13101 }
13102 }
13103
13104 static bool intel_fuzzy_clock_check(int clock1, int clock2)
13105 {
13106 int diff;
13107
13108 if (clock1 == clock2)
13109 return true;
13110
13111 if (!clock1 || !clock2)
13112 return false;
13113
13114 diff = abs(clock1 - clock2);
13115
13116 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13117 return true;
13118
13119 return false;
13120 }
13121
13122 static bool
13123 intel_compare_m_n(unsigned int m, unsigned int n,
13124 unsigned int m2, unsigned int n2,
13125 bool exact)
13126 {
13127 if (m == m2 && n == n2)
13128 return true;
13129
13130 if (exact || !m || !n || !m2 || !n2)
13131 return false;
13132
13133 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13134
13135 if (n > n2) {
13136 while (n > n2) {
13137 m2 <<= 1;
13138 n2 <<= 1;
13139 }
13140 } else if (n < n2) {
13141 while (n < n2) {
13142 m <<= 1;
13143 n <<= 1;
13144 }
13145 }
13146
13147 if (n != n2)
13148 return false;
13149
13150 return intel_fuzzy_clock_check(m, m2);
13151 }
13152
13153 static bool
13154 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13155 struct intel_link_m_n *m2_n2,
13156 bool adjust)
13157 {
13158 if (m_n->tu == m2_n2->tu &&
13159 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13160 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
13161 intel_compare_m_n(m_n->link_m, m_n->link_n,
13162 m2_n2->link_m, m2_n2->link_n, !adjust)) {
13163 if (adjust)
13164 *m2_n2 = *m_n;
13165
13166 return true;
13167 }
13168
13169 return false;
13170 }
13171
13172 static bool
13173 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
13174 struct intel_crtc_state *current_config,
13175 struct intel_crtc_state *pipe_config,
13176 bool adjust)
13177 {
13178 bool ret = true;
13179
13180 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
13181 do { \
13182 if (!adjust) \
13183 DRM_ERROR(fmt, ##__VA_ARGS__); \
13184 else \
13185 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
13186 } while (0)
13187
13188 #define PIPE_CONF_CHECK_X(name) \
13189 if (current_config->name != pipe_config->name) { \
13190 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13191 "(expected 0x%08x, found 0x%08x)\n", \
13192 current_config->name, \
13193 pipe_config->name); \
13194 ret = false; \
13195 }
13196
13197 #define PIPE_CONF_CHECK_I(name) \
13198 if (current_config->name != pipe_config->name) { \
13199 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13200 "(expected %i, found %i)\n", \
13201 current_config->name, \
13202 pipe_config->name); \
13203 ret = false; \
13204 }
13205
13206 #define PIPE_CONF_CHECK_P(name) \
13207 if (current_config->name != pipe_config->name) { \
13208 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13209 "(expected %p, found %p)\n", \
13210 current_config->name, \
13211 pipe_config->name); \
13212 ret = false; \
13213 }
13214
13215 #define PIPE_CONF_CHECK_M_N(name) \
13216 if (!intel_compare_link_m_n(&current_config->name, \
13217 &pipe_config->name,\
13218 adjust)) { \
13219 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13220 "(expected tu %i gmch %i/%i link %i/%i, " \
13221 "found tu %i, gmch %i/%i link %i/%i)\n", \
13222 current_config->name.tu, \
13223 current_config->name.gmch_m, \
13224 current_config->name.gmch_n, \
13225 current_config->name.link_m, \
13226 current_config->name.link_n, \
13227 pipe_config->name.tu, \
13228 pipe_config->name.gmch_m, \
13229 pipe_config->name.gmch_n, \
13230 pipe_config->name.link_m, \
13231 pipe_config->name.link_n); \
13232 ret = false; \
13233 }
13234
13235 /* This is required for BDW+ where there is only one set of registers for
13236 * switching between high and low RR.
13237 * This macro can be used whenever a comparison has to be made between one
13238 * hw state and multiple sw state variables.
13239 */
13240 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
13241 if (!intel_compare_link_m_n(&current_config->name, \
13242 &pipe_config->name, adjust) && \
13243 !intel_compare_link_m_n(&current_config->alt_name, \
13244 &pipe_config->name, adjust)) { \
13245 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13246 "(expected tu %i gmch %i/%i link %i/%i, " \
13247 "or tu %i gmch %i/%i link %i/%i, " \
13248 "found tu %i, gmch %i/%i link %i/%i)\n", \
13249 current_config->name.tu, \
13250 current_config->name.gmch_m, \
13251 current_config->name.gmch_n, \
13252 current_config->name.link_m, \
13253 current_config->name.link_n, \
13254 current_config->alt_name.tu, \
13255 current_config->alt_name.gmch_m, \
13256 current_config->alt_name.gmch_n, \
13257 current_config->alt_name.link_m, \
13258 current_config->alt_name.link_n, \
13259 pipe_config->name.tu, \
13260 pipe_config->name.gmch_m, \
13261 pipe_config->name.gmch_n, \
13262 pipe_config->name.link_m, \
13263 pipe_config->name.link_n); \
13264 ret = false; \
13265 }
13266
13267 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
13268 if ((current_config->name ^ pipe_config->name) & (mask)) { \
13269 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
13270 "(expected %i, found %i)\n", \
13271 current_config->name & (mask), \
13272 pipe_config->name & (mask)); \
13273 ret = false; \
13274 }
13275
13276 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
13277 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13278 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13279 "(expected %i, found %i)\n", \
13280 current_config->name, \
13281 pipe_config->name); \
13282 ret = false; \
13283 }
13284
13285 #define PIPE_CONF_QUIRK(quirk) \
13286 ((current_config->quirks | pipe_config->quirks) & (quirk))
13287
13288 PIPE_CONF_CHECK_I(cpu_transcoder);
13289
13290 PIPE_CONF_CHECK_I(has_pch_encoder);
13291 PIPE_CONF_CHECK_I(fdi_lanes);
13292 PIPE_CONF_CHECK_M_N(fdi_m_n);
13293
13294 PIPE_CONF_CHECK_I(lane_count);
13295 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13296
13297 if (INTEL_GEN(dev_priv) < 8) {
13298 PIPE_CONF_CHECK_M_N(dp_m_n);
13299
13300 if (current_config->has_drrs)
13301 PIPE_CONF_CHECK_M_N(dp_m2_n2);
13302 } else
13303 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13304
13305 PIPE_CONF_CHECK_X(output_types);
13306
13307 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
13308 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
13309 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
13310 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
13311 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
13312 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
13313
13314 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
13315 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
13316 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
13317 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
13318 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
13319 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
13320
13321 PIPE_CONF_CHECK_I(pixel_multiplier);
13322 PIPE_CONF_CHECK_I(has_hdmi_sink);
13323 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
13324 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13325 PIPE_CONF_CHECK_I(limited_color_range);
13326 PIPE_CONF_CHECK_I(has_infoframe);
13327
13328 PIPE_CONF_CHECK_I(has_audio);
13329
13330 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13331 DRM_MODE_FLAG_INTERLACE);
13332
13333 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13334 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13335 DRM_MODE_FLAG_PHSYNC);
13336 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13337 DRM_MODE_FLAG_NHSYNC);
13338 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13339 DRM_MODE_FLAG_PVSYNC);
13340 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13341 DRM_MODE_FLAG_NVSYNC);
13342 }
13343
13344 PIPE_CONF_CHECK_X(gmch_pfit.control);
13345 /* pfit ratios are autocomputed by the hw on gen4+ */
13346 if (INTEL_GEN(dev_priv) < 4)
13347 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13348 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13349
13350 if (!adjust) {
13351 PIPE_CONF_CHECK_I(pipe_src_w);
13352 PIPE_CONF_CHECK_I(pipe_src_h);
13353
13354 PIPE_CONF_CHECK_I(pch_pfit.enabled);
13355 if (current_config->pch_pfit.enabled) {
13356 PIPE_CONF_CHECK_X(pch_pfit.pos);
13357 PIPE_CONF_CHECK_X(pch_pfit.size);
13358 }
13359
13360 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13361 }
13362
13363 /* BDW+ don't expose a synchronous way to read the state */
13364 if (IS_HASWELL(dev_priv))
13365 PIPE_CONF_CHECK_I(ips_enabled);
13366
13367 PIPE_CONF_CHECK_I(double_wide);
13368
13369 PIPE_CONF_CHECK_P(shared_dpll);
13370 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13371 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13372 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13373 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13374 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13375 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13376 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13377 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13378 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13379
13380 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13381 PIPE_CONF_CHECK_X(dsi_pll.div);
13382
13383 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
13384 PIPE_CONF_CHECK_I(pipe_bpp);
13385
13386 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
13387 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13388
13389 #undef PIPE_CONF_CHECK_X
13390 #undef PIPE_CONF_CHECK_I
13391 #undef PIPE_CONF_CHECK_P
13392 #undef PIPE_CONF_CHECK_FLAGS
13393 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13394 #undef PIPE_CONF_QUIRK
13395 #undef INTEL_ERR_OR_DBG_KMS
13396
13397 return ret;
13398 }
13399
13400 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13401 const struct intel_crtc_state *pipe_config)
13402 {
13403 if (pipe_config->has_pch_encoder) {
13404 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13405 &pipe_config->fdi_m_n);
13406 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
13407
13408 /*
13409 * FDI already provided one idea for the dotclock.
13410 * Yell if the encoder disagrees.
13411 */
13412 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13413 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13414 fdi_dotclock, dotclock);
13415 }
13416 }
13417
13418 static void verify_wm_state(struct drm_crtc *crtc,
13419 struct drm_crtc_state *new_state)
13420 {
13421 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13422 struct skl_ddb_allocation hw_ddb, *sw_ddb;
13423 struct skl_pipe_wm hw_wm, *sw_wm;
13424 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
13425 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
13426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13427 const enum pipe pipe = intel_crtc->pipe;
13428 int plane, level, max_level = ilk_wm_max_level(dev_priv);
13429
13430 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
13431 return;
13432
13433 skl_pipe_wm_get_hw_state(crtc, &hw_wm);
13434 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
13435
13436 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
13437 sw_ddb = &dev_priv->wm.skl_hw.ddb;
13438
13439 /* planes */
13440 for_each_universal_plane(dev_priv, pipe, plane) {
13441 hw_plane_wm = &hw_wm.planes[plane];
13442 sw_plane_wm = &sw_wm->planes[plane];
13443
13444 /* Watermarks */
13445 for (level = 0; level <= max_level; level++) {
13446 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13447 &sw_plane_wm->wm[level]))
13448 continue;
13449
13450 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13451 pipe_name(pipe), plane + 1, level,
13452 sw_plane_wm->wm[level].plane_en,
13453 sw_plane_wm->wm[level].plane_res_b,
13454 sw_plane_wm->wm[level].plane_res_l,
13455 hw_plane_wm->wm[level].plane_en,
13456 hw_plane_wm->wm[level].plane_res_b,
13457 hw_plane_wm->wm[level].plane_res_l);
13458 }
13459
13460 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13461 &sw_plane_wm->trans_wm)) {
13462 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13463 pipe_name(pipe), plane + 1,
13464 sw_plane_wm->trans_wm.plane_en,
13465 sw_plane_wm->trans_wm.plane_res_b,
13466 sw_plane_wm->trans_wm.plane_res_l,
13467 hw_plane_wm->trans_wm.plane_en,
13468 hw_plane_wm->trans_wm.plane_res_b,
13469 hw_plane_wm->trans_wm.plane_res_l);
13470 }
13471
13472 /* DDB */
13473 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
13474 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
13475
13476 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13477 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
13478 pipe_name(pipe), plane + 1,
13479 sw_ddb_entry->start, sw_ddb_entry->end,
13480 hw_ddb_entry->start, hw_ddb_entry->end);
13481 }
13482 }
13483
13484 /*
13485 * cursor
13486 * If the cursor plane isn't active, we may not have updated it's ddb
13487 * allocation. In that case since the ddb allocation will be updated
13488 * once the plane becomes visible, we can skip this check
13489 */
13490 if (intel_crtc->cursor_addr) {
13491 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
13492 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
13493
13494 /* Watermarks */
13495 for (level = 0; level <= max_level; level++) {
13496 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13497 &sw_plane_wm->wm[level]))
13498 continue;
13499
13500 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13501 pipe_name(pipe), level,
13502 sw_plane_wm->wm[level].plane_en,
13503 sw_plane_wm->wm[level].plane_res_b,
13504 sw_plane_wm->wm[level].plane_res_l,
13505 hw_plane_wm->wm[level].plane_en,
13506 hw_plane_wm->wm[level].plane_res_b,
13507 hw_plane_wm->wm[level].plane_res_l);
13508 }
13509
13510 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13511 &sw_plane_wm->trans_wm)) {
13512 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13513 pipe_name(pipe),
13514 sw_plane_wm->trans_wm.plane_en,
13515 sw_plane_wm->trans_wm.plane_res_b,
13516 sw_plane_wm->trans_wm.plane_res_l,
13517 hw_plane_wm->trans_wm.plane_en,
13518 hw_plane_wm->trans_wm.plane_res_b,
13519 hw_plane_wm->trans_wm.plane_res_l);
13520 }
13521
13522 /* DDB */
13523 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
13524 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
13525
13526 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13527 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
13528 pipe_name(pipe),
13529 sw_ddb_entry->start, sw_ddb_entry->end,
13530 hw_ddb_entry->start, hw_ddb_entry->end);
13531 }
13532 }
13533 }
13534
13535 static void
13536 verify_connector_state(struct drm_device *dev,
13537 struct drm_atomic_state *state,
13538 struct drm_crtc *crtc)
13539 {
13540 struct drm_connector *connector;
13541 struct drm_connector_state *old_conn_state;
13542 int i;
13543
13544 for_each_connector_in_state(state, connector, old_conn_state, i) {
13545 struct drm_encoder *encoder = connector->encoder;
13546 struct drm_connector_state *state = connector->state;
13547
13548 if (state->crtc != crtc)
13549 continue;
13550
13551 intel_connector_verify_state(to_intel_connector(connector));
13552
13553 I915_STATE_WARN(state->best_encoder != encoder,
13554 "connector's atomic encoder doesn't match legacy encoder\n");
13555 }
13556 }
13557
13558 static void
13559 verify_encoder_state(struct drm_device *dev)
13560 {
13561 struct intel_encoder *encoder;
13562 struct intel_connector *connector;
13563
13564 for_each_intel_encoder(dev, encoder) {
13565 bool enabled = false;
13566 enum pipe pipe;
13567
13568 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13569 encoder->base.base.id,
13570 encoder->base.name);
13571
13572 for_each_intel_connector(dev, connector) {
13573 if (connector->base.state->best_encoder != &encoder->base)
13574 continue;
13575 enabled = true;
13576
13577 I915_STATE_WARN(connector->base.state->crtc !=
13578 encoder->base.crtc,
13579 "connector's crtc doesn't match encoder crtc\n");
13580 }
13581
13582 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13583 "encoder's enabled state mismatch "
13584 "(expected %i, found %i)\n",
13585 !!encoder->base.crtc, enabled);
13586
13587 if (!encoder->base.crtc) {
13588 bool active;
13589
13590 active = encoder->get_hw_state(encoder, &pipe);
13591 I915_STATE_WARN(active,
13592 "encoder detached but still enabled on pipe %c.\n",
13593 pipe_name(pipe));
13594 }
13595 }
13596 }
13597
13598 static void
13599 verify_crtc_state(struct drm_crtc *crtc,
13600 struct drm_crtc_state *old_crtc_state,
13601 struct drm_crtc_state *new_crtc_state)
13602 {
13603 struct drm_device *dev = crtc->dev;
13604 struct drm_i915_private *dev_priv = to_i915(dev);
13605 struct intel_encoder *encoder;
13606 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13607 struct intel_crtc_state *pipe_config, *sw_config;
13608 struct drm_atomic_state *old_state;
13609 bool active;
13610
13611 old_state = old_crtc_state->state;
13612 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
13613 pipe_config = to_intel_crtc_state(old_crtc_state);
13614 memset(pipe_config, 0, sizeof(*pipe_config));
13615 pipe_config->base.crtc = crtc;
13616 pipe_config->base.state = old_state;
13617
13618 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
13619
13620 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
13621
13622 /* hw state is inconsistent with the pipe quirk */
13623 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13624 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13625 active = new_crtc_state->active;
13626
13627 I915_STATE_WARN(new_crtc_state->active != active,
13628 "crtc active state doesn't match with hw state "
13629 "(expected %i, found %i)\n", new_crtc_state->active, active);
13630
13631 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13632 "transitional active state does not match atomic hw state "
13633 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13634
13635 for_each_encoder_on_crtc(dev, crtc, encoder) {
13636 enum pipe pipe;
13637
13638 active = encoder->get_hw_state(encoder, &pipe);
13639 I915_STATE_WARN(active != new_crtc_state->active,
13640 "[ENCODER:%i] active %i with crtc active %i\n",
13641 encoder->base.base.id, active, new_crtc_state->active);
13642
13643 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13644 "Encoder connected to wrong pipe %c\n",
13645 pipe_name(pipe));
13646
13647 if (active) {
13648 pipe_config->output_types |= 1 << encoder->type;
13649 encoder->get_config(encoder, pipe_config);
13650 }
13651 }
13652
13653 if (!new_crtc_state->active)
13654 return;
13655
13656 intel_pipe_config_sanity_check(dev_priv, pipe_config);
13657
13658 sw_config = to_intel_crtc_state(crtc->state);
13659 if (!intel_pipe_config_compare(dev_priv, sw_config,
13660 pipe_config, false)) {
13661 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13662 intel_dump_pipe_config(intel_crtc, pipe_config,
13663 "[hw state]");
13664 intel_dump_pipe_config(intel_crtc, sw_config,
13665 "[sw state]");
13666 }
13667 }
13668
13669 static void
13670 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13671 struct intel_shared_dpll *pll,
13672 struct drm_crtc *crtc,
13673 struct drm_crtc_state *new_state)
13674 {
13675 struct intel_dpll_hw_state dpll_hw_state;
13676 unsigned crtc_mask;
13677 bool active;
13678
13679 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13680
13681 DRM_DEBUG_KMS("%s\n", pll->name);
13682
13683 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13684
13685 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13686 I915_STATE_WARN(!pll->on && pll->active_mask,
13687 "pll in active use but not on in sw tracking\n");
13688 I915_STATE_WARN(pll->on && !pll->active_mask,
13689 "pll is on but not used by any active crtc\n");
13690 I915_STATE_WARN(pll->on != active,
13691 "pll on state mismatch (expected %i, found %i)\n",
13692 pll->on, active);
13693 }
13694
13695 if (!crtc) {
13696 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13697 "more active pll users than references: %x vs %x\n",
13698 pll->active_mask, pll->config.crtc_mask);
13699
13700 return;
13701 }
13702
13703 crtc_mask = 1 << drm_crtc_index(crtc);
13704
13705 if (new_state->active)
13706 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13707 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13708 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13709 else
13710 I915_STATE_WARN(pll->active_mask & crtc_mask,
13711 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13712 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13713
13714 I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13715 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13716 crtc_mask, pll->config.crtc_mask);
13717
13718 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13719 &dpll_hw_state,
13720 sizeof(dpll_hw_state)),
13721 "pll hw state mismatch\n");
13722 }
13723
13724 static void
13725 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13726 struct drm_crtc_state *old_crtc_state,
13727 struct drm_crtc_state *new_crtc_state)
13728 {
13729 struct drm_i915_private *dev_priv = to_i915(dev);
13730 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13731 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13732
13733 if (new_state->shared_dpll)
13734 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13735
13736 if (old_state->shared_dpll &&
13737 old_state->shared_dpll != new_state->shared_dpll) {
13738 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13739 struct intel_shared_dpll *pll = old_state->shared_dpll;
13740
13741 I915_STATE_WARN(pll->active_mask & crtc_mask,
13742 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13743 pipe_name(drm_crtc_index(crtc)));
13744 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13745 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13746 pipe_name(drm_crtc_index(crtc)));
13747 }
13748 }
13749
13750 static void
13751 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13752 struct drm_atomic_state *state,
13753 struct drm_crtc_state *old_state,
13754 struct drm_crtc_state *new_state)
13755 {
13756 if (!needs_modeset(new_state) &&
13757 !to_intel_crtc_state(new_state)->update_pipe)
13758 return;
13759
13760 verify_wm_state(crtc, new_state);
13761 verify_connector_state(crtc->dev, state, crtc);
13762 verify_crtc_state(crtc, old_state, new_state);
13763 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13764 }
13765
13766 static void
13767 verify_disabled_dpll_state(struct drm_device *dev)
13768 {
13769 struct drm_i915_private *dev_priv = to_i915(dev);
13770 int i;
13771
13772 for (i = 0; i < dev_priv->num_shared_dpll; i++)
13773 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13774 }
13775
13776 static void
13777 intel_modeset_verify_disabled(struct drm_device *dev,
13778 struct drm_atomic_state *state)
13779 {
13780 verify_encoder_state(dev);
13781 verify_connector_state(dev, state, NULL);
13782 verify_disabled_dpll_state(dev);
13783 }
13784
13785 static void update_scanline_offset(struct intel_crtc *crtc)
13786 {
13787 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13788
13789 /*
13790 * The scanline counter increments at the leading edge of hsync.
13791 *
13792 * On most platforms it starts counting from vtotal-1 on the
13793 * first active line. That means the scanline counter value is
13794 * always one less than what we would expect. Ie. just after
13795 * start of vblank, which also occurs at start of hsync (on the
13796 * last active line), the scanline counter will read vblank_start-1.
13797 *
13798 * On gen2 the scanline counter starts counting from 1 instead
13799 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13800 * to keep the value positive), instead of adding one.
13801 *
13802 * On HSW+ the behaviour of the scanline counter depends on the output
13803 * type. For DP ports it behaves like most other platforms, but on HDMI
13804 * there's an extra 1 line difference. So we need to add two instead of
13805 * one to the value.
13806 */
13807 if (IS_GEN2(dev_priv)) {
13808 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13809 int vtotal;
13810
13811 vtotal = adjusted_mode->crtc_vtotal;
13812 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13813 vtotal /= 2;
13814
13815 crtc->scanline_offset = vtotal - 1;
13816 } else if (HAS_DDI(dev_priv) &&
13817 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
13818 crtc->scanline_offset = 2;
13819 } else
13820 crtc->scanline_offset = 1;
13821 }
13822
13823 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13824 {
13825 struct drm_device *dev = state->dev;
13826 struct drm_i915_private *dev_priv = to_i915(dev);
13827 struct intel_shared_dpll_config *shared_dpll = NULL;
13828 struct drm_crtc *crtc;
13829 struct drm_crtc_state *crtc_state;
13830 int i;
13831
13832 if (!dev_priv->display.crtc_compute_clock)
13833 return;
13834
13835 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13837 struct intel_shared_dpll *old_dpll =
13838 to_intel_crtc_state(crtc->state)->shared_dpll;
13839
13840 if (!needs_modeset(crtc_state))
13841 continue;
13842
13843 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13844
13845 if (!old_dpll)
13846 continue;
13847
13848 if (!shared_dpll)
13849 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13850
13851 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13852 }
13853 }
13854
13855 /*
13856 * This implements the workaround described in the "notes" section of the mode
13857 * set sequence documentation. When going from no pipes or single pipe to
13858 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13859 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13860 */
13861 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13862 {
13863 struct drm_crtc_state *crtc_state;
13864 struct intel_crtc *intel_crtc;
13865 struct drm_crtc *crtc;
13866 struct intel_crtc_state *first_crtc_state = NULL;
13867 struct intel_crtc_state *other_crtc_state = NULL;
13868 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13869 int i;
13870
13871 /* look at all crtc's that are going to be enabled in during modeset */
13872 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13873 intel_crtc = to_intel_crtc(crtc);
13874
13875 if (!crtc_state->active || !needs_modeset(crtc_state))
13876 continue;
13877
13878 if (first_crtc_state) {
13879 other_crtc_state = to_intel_crtc_state(crtc_state);
13880 break;
13881 } else {
13882 first_crtc_state = to_intel_crtc_state(crtc_state);
13883 first_pipe = intel_crtc->pipe;
13884 }
13885 }
13886
13887 /* No workaround needed? */
13888 if (!first_crtc_state)
13889 return 0;
13890
13891 /* w/a possibly needed, check how many crtc's are already enabled. */
13892 for_each_intel_crtc(state->dev, intel_crtc) {
13893 struct intel_crtc_state *pipe_config;
13894
13895 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13896 if (IS_ERR(pipe_config))
13897 return PTR_ERR(pipe_config);
13898
13899 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13900
13901 if (!pipe_config->base.active ||
13902 needs_modeset(&pipe_config->base))
13903 continue;
13904
13905 /* 2 or more enabled crtcs means no need for w/a */
13906 if (enabled_pipe != INVALID_PIPE)
13907 return 0;
13908
13909 enabled_pipe = intel_crtc->pipe;
13910 }
13911
13912 if (enabled_pipe != INVALID_PIPE)
13913 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13914 else if (other_crtc_state)
13915 other_crtc_state->hsw_workaround_pipe = first_pipe;
13916
13917 return 0;
13918 }
13919
13920 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13921 {
13922 struct drm_crtc *crtc;
13923 struct drm_crtc_state *crtc_state;
13924 int ret = 0;
13925
13926 /* add all active pipes to the state */
13927 for_each_crtc(state->dev, crtc) {
13928 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13929 if (IS_ERR(crtc_state))
13930 return PTR_ERR(crtc_state);
13931
13932 if (!crtc_state->active || needs_modeset(crtc_state))
13933 continue;
13934
13935 crtc_state->mode_changed = true;
13936
13937 ret = drm_atomic_add_affected_connectors(state, crtc);
13938 if (ret)
13939 break;
13940
13941 ret = drm_atomic_add_affected_planes(state, crtc);
13942 if (ret)
13943 break;
13944 }
13945
13946 return ret;
13947 }
13948
13949 static int intel_modeset_checks(struct drm_atomic_state *state)
13950 {
13951 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13952 struct drm_i915_private *dev_priv = to_i915(state->dev);
13953 struct drm_crtc *crtc;
13954 struct drm_crtc_state *crtc_state;
13955 int ret = 0, i;
13956
13957 if (!check_digital_port_conflicts(state)) {
13958 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13959 return -EINVAL;
13960 }
13961
13962 intel_state->modeset = true;
13963 intel_state->active_crtcs = dev_priv->active_crtcs;
13964
13965 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13966 if (crtc_state->active)
13967 intel_state->active_crtcs |= 1 << i;
13968 else
13969 intel_state->active_crtcs &= ~(1 << i);
13970
13971 if (crtc_state->active != crtc->state->active)
13972 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13973 }
13974
13975 /*
13976 * See if the config requires any additional preparation, e.g.
13977 * to adjust global state with pipes off. We need to do this
13978 * here so we can get the modeset_pipe updated config for the new
13979 * mode set on this crtc. For other crtcs we need to use the
13980 * adjusted_mode bits in the crtc directly.
13981 */
13982 if (dev_priv->display.modeset_calc_cdclk) {
13983 if (!intel_state->cdclk_pll_vco)
13984 intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
13985 if (!intel_state->cdclk_pll_vco)
13986 intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
13987
13988 ret = dev_priv->display.modeset_calc_cdclk(state);
13989 if (ret < 0)
13990 return ret;
13991
13992 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13993 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
13994 ret = intel_modeset_all_pipes(state);
13995
13996 if (ret < 0)
13997 return ret;
13998
13999 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
14000 intel_state->cdclk, intel_state->dev_cdclk);
14001 } else {
14002 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
14003 }
14004
14005 intel_modeset_clear_plls(state);
14006
14007 if (IS_HASWELL(dev_priv))
14008 return haswell_mode_set_planes_workaround(state);
14009
14010 return 0;
14011 }
14012
14013 /*
14014 * Handle calculation of various watermark data at the end of the atomic check
14015 * phase. The code here should be run after the per-crtc and per-plane 'check'
14016 * handlers to ensure that all derived state has been updated.
14017 */
14018 static int calc_watermark_data(struct drm_atomic_state *state)
14019 {
14020 struct drm_device *dev = state->dev;
14021 struct drm_i915_private *dev_priv = to_i915(dev);
14022
14023 /* Is there platform-specific watermark information to calculate? */
14024 if (dev_priv->display.compute_global_watermarks)
14025 return dev_priv->display.compute_global_watermarks(state);
14026
14027 return 0;
14028 }
14029
14030 /**
14031 * intel_atomic_check - validate state object
14032 * @dev: drm device
14033 * @state: state to validate
14034 */
14035 static int intel_atomic_check(struct drm_device *dev,
14036 struct drm_atomic_state *state)
14037 {
14038 struct drm_i915_private *dev_priv = to_i915(dev);
14039 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14040 struct drm_crtc *crtc;
14041 struct drm_crtc_state *crtc_state;
14042 int ret, i;
14043 bool any_ms = false;
14044
14045 ret = drm_atomic_helper_check_modeset(dev, state);
14046 if (ret)
14047 return ret;
14048
14049 for_each_crtc_in_state(state, crtc, crtc_state, i) {
14050 struct intel_crtc_state *pipe_config =
14051 to_intel_crtc_state(crtc_state);
14052
14053 /* Catch I915_MODE_FLAG_INHERITED */
14054 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
14055 crtc_state->mode_changed = true;
14056
14057 if (!needs_modeset(crtc_state))
14058 continue;
14059
14060 if (!crtc_state->enable) {
14061 any_ms = true;
14062 continue;
14063 }
14064
14065 /* FIXME: For only active_changed we shouldn't need to do any
14066 * state recomputation at all. */
14067
14068 ret = drm_atomic_add_affected_connectors(state, crtc);
14069 if (ret)
14070 return ret;
14071
14072 ret = intel_modeset_pipe_config(crtc, pipe_config);
14073 if (ret) {
14074 intel_dump_pipe_config(to_intel_crtc(crtc),
14075 pipe_config, "[failed]");
14076 return ret;
14077 }
14078
14079 if (i915.fastboot &&
14080 intel_pipe_config_compare(dev_priv,
14081 to_intel_crtc_state(crtc->state),
14082 pipe_config, true)) {
14083 crtc_state->mode_changed = false;
14084 to_intel_crtc_state(crtc_state)->update_pipe = true;
14085 }
14086
14087 if (needs_modeset(crtc_state))
14088 any_ms = true;
14089
14090 ret = drm_atomic_add_affected_planes(state, crtc);
14091 if (ret)
14092 return ret;
14093
14094 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
14095 needs_modeset(crtc_state) ?
14096 "[modeset]" : "[fastset]");
14097 }
14098
14099 if (any_ms) {
14100 ret = intel_modeset_checks(state);
14101
14102 if (ret)
14103 return ret;
14104 } else {
14105 intel_state->cdclk = dev_priv->atomic_cdclk_freq;
14106 }
14107
14108 ret = drm_atomic_helper_check_planes(dev, state);
14109 if (ret)
14110 return ret;
14111
14112 intel_fbc_choose_crtc(dev_priv, state);
14113 return calc_watermark_data(state);
14114 }
14115
14116 static int intel_atomic_prepare_commit(struct drm_device *dev,
14117 struct drm_atomic_state *state)
14118 {
14119 struct drm_i915_private *dev_priv = to_i915(dev);
14120 struct drm_crtc_state *crtc_state;
14121 struct drm_crtc *crtc;
14122 int i, ret;
14123
14124 for_each_crtc_in_state(state, crtc, crtc_state, i) {
14125 if (state->legacy_cursor_update)
14126 continue;
14127
14128 ret = intel_crtc_wait_for_pending_flips(crtc);
14129 if (ret)
14130 return ret;
14131
14132 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
14133 flush_workqueue(dev_priv->wq);
14134 }
14135
14136 ret = mutex_lock_interruptible(&dev->struct_mutex);
14137 if (ret)
14138 return ret;
14139
14140 ret = drm_atomic_helper_prepare_planes(dev, state);
14141 mutex_unlock(&dev->struct_mutex);
14142
14143 return ret;
14144 }
14145
14146 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14147 {
14148 struct drm_device *dev = crtc->base.dev;
14149
14150 if (!dev->max_vblank_count)
14151 return drm_accurate_vblank_count(&crtc->base);
14152
14153 return dev->driver->get_vblank_counter(dev, crtc->pipe);
14154 }
14155
14156 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
14157 struct drm_i915_private *dev_priv,
14158 unsigned crtc_mask)
14159 {
14160 unsigned last_vblank_count[I915_MAX_PIPES];
14161 enum pipe pipe;
14162 int ret;
14163
14164 if (!crtc_mask)
14165 return;
14166
14167 for_each_pipe(dev_priv, pipe) {
14168 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
14169 pipe);
14170
14171 if (!((1 << pipe) & crtc_mask))
14172 continue;
14173
14174 ret = drm_crtc_vblank_get(&crtc->base);
14175 if (WARN_ON(ret != 0)) {
14176 crtc_mask &= ~(1 << pipe);
14177 continue;
14178 }
14179
14180 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
14181 }
14182
14183 for_each_pipe(dev_priv, pipe) {
14184 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
14185 pipe);
14186 long lret;
14187
14188 if (!((1 << pipe) & crtc_mask))
14189 continue;
14190
14191 lret = wait_event_timeout(dev->vblank[pipe].queue,
14192 last_vblank_count[pipe] !=
14193 drm_crtc_vblank_count(&crtc->base),
14194 msecs_to_jiffies(50));
14195
14196 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
14197
14198 drm_crtc_vblank_put(&crtc->base);
14199 }
14200 }
14201
14202 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
14203 {
14204 /* fb updated, need to unpin old fb */
14205 if (crtc_state->fb_changed)
14206 return true;
14207
14208 /* wm changes, need vblank before final wm's */
14209 if (crtc_state->update_wm_post)
14210 return true;
14211
14212 /*
14213 * cxsr is re-enabled after vblank.
14214 * This is already handled by crtc_state->update_wm_post,
14215 * but added for clarity.
14216 */
14217 if (crtc_state->disable_cxsr)
14218 return true;
14219
14220 return false;
14221 }
14222
14223 static void intel_update_crtc(struct drm_crtc *crtc,
14224 struct drm_atomic_state *state,
14225 struct drm_crtc_state *old_crtc_state,
14226 unsigned int *crtc_vblank_mask)
14227 {
14228 struct drm_device *dev = crtc->dev;
14229 struct drm_i915_private *dev_priv = to_i915(dev);
14230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14231 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state);
14232 bool modeset = needs_modeset(crtc->state);
14233
14234 if (modeset) {
14235 update_scanline_offset(intel_crtc);
14236 dev_priv->display.crtc_enable(pipe_config, state);
14237 } else {
14238 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14239 }
14240
14241 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
14242 intel_fbc_enable(
14243 intel_crtc, pipe_config,
14244 to_intel_plane_state(crtc->primary->state));
14245 }
14246
14247 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
14248
14249 if (needs_vblank_wait(pipe_config))
14250 *crtc_vblank_mask |= drm_crtc_mask(crtc);
14251 }
14252
14253 static void intel_update_crtcs(struct drm_atomic_state *state,
14254 unsigned int *crtc_vblank_mask)
14255 {
14256 struct drm_crtc *crtc;
14257 struct drm_crtc_state *old_crtc_state;
14258 int i;
14259
14260 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14261 if (!crtc->state->active)
14262 continue;
14263
14264 intel_update_crtc(crtc, state, old_crtc_state,
14265 crtc_vblank_mask);
14266 }
14267 }
14268
14269 static void skl_update_crtcs(struct drm_atomic_state *state,
14270 unsigned int *crtc_vblank_mask)
14271 {
14272 struct drm_i915_private *dev_priv = to_i915(state->dev);
14273 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14274 struct drm_crtc *crtc;
14275 struct intel_crtc *intel_crtc;
14276 struct drm_crtc_state *old_crtc_state;
14277 struct intel_crtc_state *cstate;
14278 unsigned int updated = 0;
14279 bool progress;
14280 enum pipe pipe;
14281 int i;
14282
14283 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
14284
14285 for_each_crtc_in_state(state, crtc, old_crtc_state, i)
14286 /* ignore allocations for crtc's that have been turned off. */
14287 if (crtc->state->active)
14288 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
14289
14290 /*
14291 * Whenever the number of active pipes changes, we need to make sure we
14292 * update the pipes in the right order so that their ddb allocations
14293 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14294 * cause pipe underruns and other bad stuff.
14295 */
14296 do {
14297 progress = false;
14298
14299 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14300 bool vbl_wait = false;
14301 unsigned int cmask = drm_crtc_mask(crtc);
14302
14303 intel_crtc = to_intel_crtc(crtc);
14304 cstate = to_intel_crtc_state(crtc->state);
14305 pipe = intel_crtc->pipe;
14306
14307 if (updated & cmask || !cstate->base.active)
14308 continue;
14309
14310 if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
14311 continue;
14312
14313 updated |= cmask;
14314 entries[i] = &cstate->wm.skl.ddb;
14315
14316 /*
14317 * If this is an already active pipe, it's DDB changed,
14318 * and this isn't the last pipe that needs updating
14319 * then we need to wait for a vblank to pass for the
14320 * new ddb allocation to take effect.
14321 */
14322 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
14323 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
14324 !crtc->state->active_changed &&
14325 intel_state->wm_results.dirty_pipes != updated)
14326 vbl_wait = true;
14327
14328 intel_update_crtc(crtc, state, old_crtc_state,
14329 crtc_vblank_mask);
14330
14331 if (vbl_wait)
14332 intel_wait_for_vblank(dev_priv, pipe);
14333
14334 progress = true;
14335 }
14336 } while (progress);
14337 }
14338
14339 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
14340 {
14341 struct drm_device *dev = state->dev;
14342 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14343 struct drm_i915_private *dev_priv = to_i915(dev);
14344 struct drm_crtc_state *old_crtc_state;
14345 struct drm_crtc *crtc;
14346 struct intel_crtc_state *intel_cstate;
14347 bool hw_check = intel_state->modeset;
14348 unsigned long put_domains[I915_MAX_PIPES] = {};
14349 unsigned crtc_vblank_mask = 0;
14350 int i;
14351
14352 drm_atomic_helper_wait_for_dependencies(state);
14353
14354 if (intel_state->modeset)
14355 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14356
14357 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14359
14360 if (needs_modeset(crtc->state) ||
14361 to_intel_crtc_state(crtc->state)->update_pipe) {
14362 hw_check = true;
14363
14364 put_domains[to_intel_crtc(crtc)->pipe] =
14365 modeset_get_crtc_power_domains(crtc,
14366 to_intel_crtc_state(crtc->state));
14367 }
14368
14369 if (!needs_modeset(crtc->state))
14370 continue;
14371
14372 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14373
14374 if (old_crtc_state->active) {
14375 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
14376 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
14377 intel_crtc->active = false;
14378 intel_fbc_disable(intel_crtc);
14379 intel_disable_shared_dpll(intel_crtc);
14380
14381 /*
14382 * Underruns don't always raise
14383 * interrupts, so check manually.
14384 */
14385 intel_check_cpu_fifo_underruns(dev_priv);
14386 intel_check_pch_fifo_underruns(dev_priv);
14387
14388 if (!crtc->state->active) {
14389 /*
14390 * Make sure we don't call initial_watermarks
14391 * for ILK-style watermark updates.
14392 */
14393 if (dev_priv->display.atomic_update_watermarks)
14394 dev_priv->display.initial_watermarks(intel_state,
14395 to_intel_crtc_state(crtc->state));
14396 else
14397 intel_update_watermarks(intel_crtc);
14398 }
14399 }
14400 }
14401
14402 /* Only after disabling all output pipelines that will be changed can we
14403 * update the the output configuration. */
14404 intel_modeset_update_crtc_state(state);
14405
14406 if (intel_state->modeset) {
14407 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
14408
14409 if (dev_priv->display.modeset_commit_cdclk &&
14410 (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
14411 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
14412 dev_priv->display.modeset_commit_cdclk(state);
14413
14414 /*
14415 * SKL workaround: bspec recommends we disable the SAGV when we
14416 * have more then one pipe enabled
14417 */
14418 if (!intel_can_enable_sagv(state))
14419 intel_disable_sagv(dev_priv);
14420
14421 intel_modeset_verify_disabled(dev, state);
14422 }
14423
14424 /* Complete the events for pipes that have now been disabled */
14425 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14426 bool modeset = needs_modeset(crtc->state);
14427
14428 /* Complete events for now disable pipes here. */
14429 if (modeset && !crtc->state->active && crtc->state->event) {
14430 spin_lock_irq(&dev->event_lock);
14431 drm_crtc_send_vblank_event(crtc, crtc->state->event);
14432 spin_unlock_irq(&dev->event_lock);
14433
14434 crtc->state->event = NULL;
14435 }
14436 }
14437
14438 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14439 dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
14440
14441 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14442 * already, but still need the state for the delayed optimization. To
14443 * fix this:
14444 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14445 * - schedule that vblank worker _before_ calling hw_done
14446 * - at the start of commit_tail, cancel it _synchrously
14447 * - switch over to the vblank wait helper in the core after that since
14448 * we don't need out special handling any more.
14449 */
14450 if (!state->legacy_cursor_update)
14451 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
14452
14453 /*
14454 * Now that the vblank has passed, we can go ahead and program the
14455 * optimal watermarks on platforms that need two-step watermark
14456 * programming.
14457 *
14458 * TODO: Move this (and other cleanup) to an async worker eventually.
14459 */
14460 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14461 intel_cstate = to_intel_crtc_state(crtc->state);
14462
14463 if (dev_priv->display.optimize_watermarks)
14464 dev_priv->display.optimize_watermarks(intel_state,
14465 intel_cstate);
14466 }
14467
14468 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14469 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
14470
14471 if (put_domains[i])
14472 modeset_put_power_domains(dev_priv, put_domains[i]);
14473
14474 intel_modeset_verify_crtc(crtc, state, old_crtc_state, crtc->state);
14475 }
14476
14477 if (intel_state->modeset && intel_can_enable_sagv(state))
14478 intel_enable_sagv(dev_priv);
14479
14480 drm_atomic_helper_commit_hw_done(state);
14481
14482 if (intel_state->modeset)
14483 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
14484
14485 mutex_lock(&dev->struct_mutex);
14486 drm_atomic_helper_cleanup_planes(dev, state);
14487 mutex_unlock(&dev->struct_mutex);
14488
14489 drm_atomic_helper_commit_cleanup_done(state);
14490
14491 drm_atomic_state_put(state);
14492
14493 /* As one of the primary mmio accessors, KMS has a high likelihood
14494 * of triggering bugs in unclaimed access. After we finish
14495 * modesetting, see if an error has been flagged, and if so
14496 * enable debugging for the next modeset - and hope we catch
14497 * the culprit.
14498 *
14499 * XXX note that we assume display power is on at this point.
14500 * This might hold true now but we need to add pm helper to check
14501 * unclaimed only when the hardware is on, as atomic commits
14502 * can happen also when the device is completely off.
14503 */
14504 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
14505 }
14506
14507 static void intel_atomic_commit_work(struct work_struct *work)
14508 {
14509 struct drm_atomic_state *state =
14510 container_of(work, struct drm_atomic_state, commit_work);
14511
14512 intel_atomic_commit_tail(state);
14513 }
14514
14515 static int __i915_sw_fence_call
14516 intel_atomic_commit_ready(struct i915_sw_fence *fence,
14517 enum i915_sw_fence_notify notify)
14518 {
14519 struct intel_atomic_state *state =
14520 container_of(fence, struct intel_atomic_state, commit_ready);
14521
14522 switch (notify) {
14523 case FENCE_COMPLETE:
14524 if (state->base.commit_work.func)
14525 queue_work(system_unbound_wq, &state->base.commit_work);
14526 break;
14527
14528 case FENCE_FREE:
14529 {
14530 struct intel_atomic_helper *helper =
14531 &to_i915(state->base.dev)->atomic_helper;
14532
14533 if (llist_add(&state->freed, &helper->free_list))
14534 schedule_work(&helper->free_work);
14535 break;
14536 }
14537 }
14538
14539 return NOTIFY_DONE;
14540 }
14541
14542 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
14543 {
14544 struct drm_plane_state *old_plane_state;
14545 struct drm_plane *plane;
14546 int i;
14547
14548 for_each_plane_in_state(state, plane, old_plane_state, i)
14549 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
14550 intel_fb_obj(plane->state->fb),
14551 to_intel_plane(plane)->frontbuffer_bit);
14552 }
14553
14554 /**
14555 * intel_atomic_commit - commit validated state object
14556 * @dev: DRM device
14557 * @state: the top-level driver state object
14558 * @nonblock: nonblocking commit
14559 *
14560 * This function commits a top-level state object that has been validated
14561 * with drm_atomic_helper_check().
14562 *
14563 * RETURNS
14564 * Zero for success or -errno.
14565 */
14566 static int intel_atomic_commit(struct drm_device *dev,
14567 struct drm_atomic_state *state,
14568 bool nonblock)
14569 {
14570 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14571 struct drm_i915_private *dev_priv = to_i915(dev);
14572 int ret = 0;
14573
14574 ret = drm_atomic_helper_setup_commit(state, nonblock);
14575 if (ret)
14576 return ret;
14577
14578 drm_atomic_state_get(state);
14579 i915_sw_fence_init(&intel_state->commit_ready,
14580 intel_atomic_commit_ready);
14581
14582 ret = intel_atomic_prepare_commit(dev, state);
14583 if (ret) {
14584 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14585 i915_sw_fence_commit(&intel_state->commit_ready);
14586 return ret;
14587 }
14588
14589 drm_atomic_helper_swap_state(state, true);
14590 dev_priv->wm.distrust_bios_wm = false;
14591 intel_shared_dpll_commit(state);
14592 intel_atomic_track_fbs(state);
14593
14594 if (intel_state->modeset) {
14595 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
14596 sizeof(intel_state->min_pixclk));
14597 dev_priv->active_crtcs = intel_state->active_crtcs;
14598 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
14599 }
14600
14601 drm_atomic_state_get(state);
14602 INIT_WORK(&state->commit_work,
14603 nonblock ? intel_atomic_commit_work : NULL);
14604
14605 i915_sw_fence_commit(&intel_state->commit_ready);
14606 if (!nonblock) {
14607 i915_sw_fence_wait(&intel_state->commit_ready);
14608 intel_atomic_commit_tail(state);
14609 }
14610
14611 return 0;
14612 }
14613
14614 void intel_crtc_restore_mode(struct drm_crtc *crtc)
14615 {
14616 struct drm_device *dev = crtc->dev;
14617 struct drm_atomic_state *state;
14618 struct drm_crtc_state *crtc_state;
14619 int ret;
14620
14621 state = drm_atomic_state_alloc(dev);
14622 if (!state) {
14623 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
14624 crtc->base.id, crtc->name);
14625 return;
14626 }
14627
14628 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
14629
14630 retry:
14631 crtc_state = drm_atomic_get_crtc_state(state, crtc);
14632 ret = PTR_ERR_OR_ZERO(crtc_state);
14633 if (!ret) {
14634 if (!crtc_state->active)
14635 goto out;
14636
14637 crtc_state->mode_changed = true;
14638 ret = drm_atomic_commit(state);
14639 }
14640
14641 if (ret == -EDEADLK) {
14642 drm_atomic_state_clear(state);
14643 drm_modeset_backoff(state->acquire_ctx);
14644 goto retry;
14645 }
14646
14647 out:
14648 drm_atomic_state_put(state);
14649 }
14650
14651 /*
14652 * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
14653 * drm_atomic_helper_legacy_gamma_set() directly.
14654 */
14655 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
14656 u16 *red, u16 *green, u16 *blue,
14657 uint32_t size)
14658 {
14659 struct drm_device *dev = crtc->dev;
14660 struct drm_mode_config *config = &dev->mode_config;
14661 struct drm_crtc_state *state;
14662 int ret;
14663
14664 ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
14665 if (ret)
14666 return ret;
14667
14668 /*
14669 * Make sure we update the legacy properties so this works when
14670 * atomic is not enabled.
14671 */
14672
14673 state = crtc->state;
14674
14675 drm_object_property_set_value(&crtc->base,
14676 config->degamma_lut_property,
14677 (state->degamma_lut) ?
14678 state->degamma_lut->base.id : 0);
14679
14680 drm_object_property_set_value(&crtc->base,
14681 config->ctm_property,
14682 (state->ctm) ?
14683 state->ctm->base.id : 0);
14684
14685 drm_object_property_set_value(&crtc->base,
14686 config->gamma_lut_property,
14687 (state->gamma_lut) ?
14688 state->gamma_lut->base.id : 0);
14689
14690 return 0;
14691 }
14692
14693 static const struct drm_crtc_funcs intel_crtc_funcs = {
14694 .gamma_set = intel_atomic_legacy_gamma_set,
14695 .set_config = drm_atomic_helper_set_config,
14696 .set_property = drm_atomic_helper_crtc_set_property,
14697 .destroy = intel_crtc_destroy,
14698 .page_flip = intel_crtc_page_flip,
14699 .atomic_duplicate_state = intel_crtc_duplicate_state,
14700 .atomic_destroy_state = intel_crtc_destroy_state,
14701 };
14702
14703 /**
14704 * intel_prepare_plane_fb - Prepare fb for usage on plane
14705 * @plane: drm plane to prepare for
14706 * @fb: framebuffer to prepare for presentation
14707 *
14708 * Prepares a framebuffer for usage on a display plane. Generally this
14709 * involves pinning the underlying object and updating the frontbuffer tracking
14710 * bits. Some older platforms need special physical address handling for
14711 * cursor planes.
14712 *
14713 * Must be called with struct_mutex held.
14714 *
14715 * Returns 0 on success, negative error code on failure.
14716 */
14717 int
14718 intel_prepare_plane_fb(struct drm_plane *plane,
14719 struct drm_plane_state *new_state)
14720 {
14721 struct intel_atomic_state *intel_state =
14722 to_intel_atomic_state(new_state->state);
14723 struct drm_i915_private *dev_priv = to_i915(plane->dev);
14724 struct drm_framebuffer *fb = new_state->fb;
14725 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14726 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
14727 int ret;
14728
14729 if (!obj && !old_obj)
14730 return 0;
14731
14732 if (old_obj) {
14733 struct drm_crtc_state *crtc_state =
14734 drm_atomic_get_existing_crtc_state(new_state->state,
14735 plane->state->crtc);
14736
14737 /* Big Hammer, we also need to ensure that any pending
14738 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14739 * current scanout is retired before unpinning the old
14740 * framebuffer. Note that we rely on userspace rendering
14741 * into the buffer attached to the pipe they are waiting
14742 * on. If not, userspace generates a GPU hang with IPEHR
14743 * point to the MI_WAIT_FOR_EVENT.
14744 *
14745 * This should only fail upon a hung GPU, in which case we
14746 * can safely continue.
14747 */
14748 if (needs_modeset(crtc_state)) {
14749 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
14750 old_obj->resv, NULL,
14751 false, 0,
14752 GFP_KERNEL);
14753 if (ret < 0)
14754 return ret;
14755 }
14756 }
14757
14758 if (new_state->fence) { /* explicit fencing */
14759 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
14760 new_state->fence,
14761 I915_FENCE_TIMEOUT,
14762 GFP_KERNEL);
14763 if (ret < 0)
14764 return ret;
14765 }
14766
14767 if (!obj)
14768 return 0;
14769
14770 if (!new_state->fence) { /* implicit fencing */
14771 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
14772 obj->resv, NULL,
14773 false, I915_FENCE_TIMEOUT,
14774 GFP_KERNEL);
14775 if (ret < 0)
14776 return ret;
14777
14778 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
14779 }
14780
14781 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14782 INTEL_INFO(dev_priv)->cursor_needs_physical) {
14783 int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
14784 ret = i915_gem_object_attach_phys(obj, align);
14785 if (ret) {
14786 DRM_DEBUG_KMS("failed to attach phys object\n");
14787 return ret;
14788 }
14789 } else {
14790 struct i915_vma *vma;
14791
14792 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14793 if (IS_ERR(vma)) {
14794 DRM_DEBUG_KMS("failed to pin object\n");
14795 return PTR_ERR(vma);
14796 }
14797 }
14798
14799 return 0;
14800 }
14801
14802 /**
14803 * intel_cleanup_plane_fb - Cleans up an fb after plane use
14804 * @plane: drm plane to clean up for
14805 * @fb: old framebuffer that was on plane
14806 *
14807 * Cleans up a framebuffer that has just been removed from a plane.
14808 *
14809 * Must be called with struct_mutex held.
14810 */
14811 void
14812 intel_cleanup_plane_fb(struct drm_plane *plane,
14813 struct drm_plane_state *old_state)
14814 {
14815 struct drm_i915_private *dev_priv = to_i915(plane->dev);
14816 struct intel_plane_state *old_intel_state;
14817 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14818 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14819
14820 old_intel_state = to_intel_plane_state(old_state);
14821
14822 if (!obj && !old_obj)
14823 return;
14824
14825 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14826 !INTEL_INFO(dev_priv)->cursor_needs_physical))
14827 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14828 }
14829
14830 int
14831 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14832 {
14833 int max_scale;
14834 int crtc_clock, cdclk;
14835
14836 if (!intel_crtc || !crtc_state->base.enable)
14837 return DRM_PLANE_HELPER_NO_SCALING;
14838
14839 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14840 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14841
14842 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14843 return DRM_PLANE_HELPER_NO_SCALING;
14844
14845 /*
14846 * skl max scale is lower of:
14847 * close to 3 but not 3, -1 is for that purpose
14848 * or
14849 * cdclk/crtc_clock
14850 */
14851 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14852
14853 return max_scale;
14854 }
14855
14856 static int
14857 intel_check_primary_plane(struct drm_plane *plane,
14858 struct intel_crtc_state *crtc_state,
14859 struct intel_plane_state *state)
14860 {
14861 struct drm_i915_private *dev_priv = to_i915(plane->dev);
14862 struct drm_crtc *crtc = state->base.crtc;
14863 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14864 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14865 bool can_position = false;
14866 int ret;
14867
14868 if (INTEL_GEN(dev_priv) >= 9) {
14869 /* use scaler when colorkey is not required */
14870 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14871 min_scale = 1;
14872 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14873 }
14874 can_position = true;
14875 }
14876
14877 ret = drm_plane_helper_check_state(&state->base,
14878 &state->clip,
14879 min_scale, max_scale,
14880 can_position, true);
14881 if (ret)
14882 return ret;
14883
14884 if (!state->base.fb)
14885 return 0;
14886
14887 if (INTEL_GEN(dev_priv) >= 9) {
14888 ret = skl_check_plane_surface(state);
14889 if (ret)
14890 return ret;
14891 }
14892
14893 return 0;
14894 }
14895
14896 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14897 struct drm_crtc_state *old_crtc_state)
14898 {
14899 struct drm_device *dev = crtc->dev;
14900 struct drm_i915_private *dev_priv = to_i915(dev);
14901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14902 struct intel_crtc_state *intel_cstate =
14903 to_intel_crtc_state(crtc->state);
14904 struct intel_crtc_state *old_intel_cstate =
14905 to_intel_crtc_state(old_crtc_state);
14906 struct intel_atomic_state *old_intel_state =
14907 to_intel_atomic_state(old_crtc_state->state);
14908 bool modeset = needs_modeset(crtc->state);
14909
14910 /* Perform vblank evasion around commit operation */
14911 intel_pipe_update_start(intel_crtc);
14912
14913 if (modeset)
14914 goto out;
14915
14916 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14917 intel_color_set_csc(crtc->state);
14918 intel_color_load_luts(crtc->state);
14919 }
14920
14921 if (intel_cstate->update_pipe)
14922 intel_update_pipe_config(intel_crtc, old_intel_cstate);
14923 else if (INTEL_GEN(dev_priv) >= 9)
14924 skl_detach_scalers(intel_crtc);
14925
14926 out:
14927 if (dev_priv->display.atomic_update_watermarks)
14928 dev_priv->display.atomic_update_watermarks(old_intel_state,
14929 intel_cstate);
14930 }
14931
14932 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14933 struct drm_crtc_state *old_crtc_state)
14934 {
14935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14936
14937 intel_pipe_update_end(intel_crtc, NULL);
14938 }
14939
14940 /**
14941 * intel_plane_destroy - destroy a plane
14942 * @plane: plane to destroy
14943 *
14944 * Common destruction function for all types of planes (primary, cursor,
14945 * sprite).
14946 */
14947 void intel_plane_destroy(struct drm_plane *plane)
14948 {
14949 drm_plane_cleanup(plane);
14950 kfree(to_intel_plane(plane));
14951 }
14952
14953 const struct drm_plane_funcs intel_plane_funcs = {
14954 .update_plane = drm_atomic_helper_update_plane,
14955 .disable_plane = drm_atomic_helper_disable_plane,
14956 .destroy = intel_plane_destroy,
14957 .set_property = drm_atomic_helper_plane_set_property,
14958 .atomic_get_property = intel_plane_atomic_get_property,
14959 .atomic_set_property = intel_plane_atomic_set_property,
14960 .atomic_duplicate_state = intel_plane_duplicate_state,
14961 .atomic_destroy_state = intel_plane_destroy_state,
14962 };
14963
14964 static struct intel_plane *
14965 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
14966 {
14967 struct intel_plane *primary = NULL;
14968 struct intel_plane_state *state = NULL;
14969 const uint32_t *intel_primary_formats;
14970 unsigned int supported_rotations;
14971 unsigned int num_formats;
14972 int ret;
14973
14974 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14975 if (!primary) {
14976 ret = -ENOMEM;
14977 goto fail;
14978 }
14979
14980 state = intel_create_plane_state(&primary->base);
14981 if (!state) {
14982 ret = -ENOMEM;
14983 goto fail;
14984 }
14985
14986 primary->base.state = &state->base;
14987
14988 primary->can_scale = false;
14989 primary->max_downscale = 1;
14990 if (INTEL_GEN(dev_priv) >= 9) {
14991 primary->can_scale = true;
14992 state->scaler_id = -1;
14993 }
14994 primary->pipe = pipe;
14995 /*
14996 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
14997 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
14998 */
14999 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
15000 primary->plane = (enum plane) !pipe;
15001 else
15002 primary->plane = (enum plane) pipe;
15003 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
15004 primary->check_plane = intel_check_primary_plane;
15005
15006 if (INTEL_GEN(dev_priv) >= 9) {
15007 intel_primary_formats = skl_primary_formats;
15008 num_formats = ARRAY_SIZE(skl_primary_formats);
15009
15010 primary->update_plane = skylake_update_primary_plane;
15011 primary->disable_plane = skylake_disable_primary_plane;
15012 } else if (HAS_PCH_SPLIT(dev_priv)) {
15013 intel_primary_formats = i965_primary_formats;
15014 num_formats = ARRAY_SIZE(i965_primary_formats);
15015
15016 primary->update_plane = ironlake_update_primary_plane;
15017 primary->disable_plane = i9xx_disable_primary_plane;
15018 } else if (INTEL_GEN(dev_priv) >= 4) {
15019 intel_primary_formats = i965_primary_formats;
15020 num_formats = ARRAY_SIZE(i965_primary_formats);
15021
15022 primary->update_plane = i9xx_update_primary_plane;
15023 primary->disable_plane = i9xx_disable_primary_plane;
15024 } else {
15025 intel_primary_formats = i8xx_primary_formats;
15026 num_formats = ARRAY_SIZE(i8xx_primary_formats);
15027
15028 primary->update_plane = i9xx_update_primary_plane;
15029 primary->disable_plane = i9xx_disable_primary_plane;
15030 }
15031
15032 if (INTEL_GEN(dev_priv) >= 9)
15033 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
15034 0, &intel_plane_funcs,
15035 intel_primary_formats, num_formats,
15036 DRM_PLANE_TYPE_PRIMARY,
15037 "plane 1%c", pipe_name(pipe));
15038 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
15039 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
15040 0, &intel_plane_funcs,
15041 intel_primary_formats, num_formats,
15042 DRM_PLANE_TYPE_PRIMARY,
15043 "primary %c", pipe_name(pipe));
15044 else
15045 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
15046 0, &intel_plane_funcs,
15047 intel_primary_formats, num_formats,
15048 DRM_PLANE_TYPE_PRIMARY,
15049 "plane %c", plane_name(primary->plane));
15050 if (ret)
15051 goto fail;
15052
15053 if (INTEL_GEN(dev_priv) >= 9) {
15054 supported_rotations =
15055 DRM_ROTATE_0 | DRM_ROTATE_90 |
15056 DRM_ROTATE_180 | DRM_ROTATE_270;
15057 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
15058 supported_rotations =
15059 DRM_ROTATE_0 | DRM_ROTATE_180 |
15060 DRM_REFLECT_X;
15061 } else if (INTEL_GEN(dev_priv) >= 4) {
15062 supported_rotations =
15063 DRM_ROTATE_0 | DRM_ROTATE_180;
15064 } else {
15065 supported_rotations = DRM_ROTATE_0;
15066 }
15067
15068 if (INTEL_GEN(dev_priv) >= 4)
15069 drm_plane_create_rotation_property(&primary->base,
15070 DRM_ROTATE_0,
15071 supported_rotations);
15072
15073 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
15074
15075 return primary;
15076
15077 fail:
15078 kfree(state);
15079 kfree(primary);
15080
15081 return ERR_PTR(ret);
15082 }
15083
15084 static int
15085 intel_check_cursor_plane(struct drm_plane *plane,
15086 struct intel_crtc_state *crtc_state,
15087 struct intel_plane_state *state)
15088 {
15089 struct drm_framebuffer *fb = state->base.fb;
15090 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15091 enum pipe pipe = to_intel_plane(plane)->pipe;
15092 unsigned stride;
15093 int ret;
15094
15095 ret = drm_plane_helper_check_state(&state->base,
15096 &state->clip,
15097 DRM_PLANE_HELPER_NO_SCALING,
15098 DRM_PLANE_HELPER_NO_SCALING,
15099 true, true);
15100 if (ret)
15101 return ret;
15102
15103 /* if we want to turn off the cursor ignore width and height */
15104 if (!obj)
15105 return 0;
15106
15107 /* Check for which cursor types we support */
15108 if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w,
15109 state->base.crtc_h)) {
15110 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
15111 state->base.crtc_w, state->base.crtc_h);
15112 return -EINVAL;
15113 }
15114
15115 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
15116 if (obj->base.size < stride * state->base.crtc_h) {
15117 DRM_DEBUG_KMS("buffer is too small\n");
15118 return -ENOMEM;
15119 }
15120
15121 if (fb->modifier != DRM_FORMAT_MOD_NONE) {
15122 DRM_DEBUG_KMS("cursor cannot be tiled\n");
15123 return -EINVAL;
15124 }
15125
15126 /*
15127 * There's something wrong with the cursor on CHV pipe C.
15128 * If it straddles the left edge of the screen then
15129 * moving it away from the edge or disabling it often
15130 * results in a pipe underrun, and often that can lead to
15131 * dead pipe (constant underrun reported, and it scans
15132 * out just a solid color). To recover from that, the
15133 * display power well must be turned off and on again.
15134 * Refuse the put the cursor into that compromised position.
15135 */
15136 if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C &&
15137 state->base.visible && state->base.crtc_x < 0) {
15138 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
15139 return -EINVAL;
15140 }
15141
15142 return 0;
15143 }
15144
15145 static void
15146 intel_disable_cursor_plane(struct drm_plane *plane,
15147 struct drm_crtc *crtc)
15148 {
15149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15150
15151 intel_crtc->cursor_addr = 0;
15152 intel_crtc_update_cursor(crtc, NULL);
15153 }
15154
15155 static void
15156 intel_update_cursor_plane(struct drm_plane *plane,
15157 const struct intel_crtc_state *crtc_state,
15158 const struct intel_plane_state *state)
15159 {
15160 struct drm_crtc *crtc = crtc_state->base.crtc;
15161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15162 struct drm_i915_private *dev_priv = to_i915(plane->dev);
15163 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
15164 uint32_t addr;
15165
15166 if (!obj)
15167 addr = 0;
15168 else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
15169 addr = i915_gem_object_ggtt_offset(obj, NULL);
15170 else
15171 addr = obj->phys_handle->busaddr;
15172
15173 intel_crtc->cursor_addr = addr;
15174 intel_crtc_update_cursor(crtc, state);
15175 }
15176
15177 static struct intel_plane *
15178 intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
15179 {
15180 struct intel_plane *cursor = NULL;
15181 struct intel_plane_state *state = NULL;
15182 int ret;
15183
15184 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
15185 if (!cursor) {
15186 ret = -ENOMEM;
15187 goto fail;
15188 }
15189
15190 state = intel_create_plane_state(&cursor->base);
15191 if (!state) {
15192 ret = -ENOMEM;
15193 goto fail;
15194 }
15195
15196 cursor->base.state = &state->base;
15197
15198 cursor->can_scale = false;
15199 cursor->max_downscale = 1;
15200 cursor->pipe = pipe;
15201 cursor->plane = pipe;
15202 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
15203 cursor->check_plane = intel_check_cursor_plane;
15204 cursor->update_plane = intel_update_cursor_plane;
15205 cursor->disable_plane = intel_disable_cursor_plane;
15206
15207 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
15208 0, &intel_plane_funcs,
15209 intel_cursor_formats,
15210 ARRAY_SIZE(intel_cursor_formats),
15211 DRM_PLANE_TYPE_CURSOR,
15212 "cursor %c", pipe_name(pipe));
15213 if (ret)
15214 goto fail;
15215
15216 if (INTEL_GEN(dev_priv) >= 4)
15217 drm_plane_create_rotation_property(&cursor->base,
15218 DRM_ROTATE_0,
15219 DRM_ROTATE_0 |
15220 DRM_ROTATE_180);
15221
15222 if (INTEL_GEN(dev_priv) >= 9)
15223 state->scaler_id = -1;
15224
15225 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
15226
15227 return cursor;
15228
15229 fail:
15230 kfree(state);
15231 kfree(cursor);
15232
15233 return ERR_PTR(ret);
15234 }
15235
15236 static void skl_init_scalers(struct drm_i915_private *dev_priv,
15237 struct intel_crtc *crtc,
15238 struct intel_crtc_state *crtc_state)
15239 {
15240 struct intel_crtc_scaler_state *scaler_state =
15241 &crtc_state->scaler_state;
15242 int i;
15243
15244 for (i = 0; i < crtc->num_scalers; i++) {
15245 struct intel_scaler *scaler = &scaler_state->scalers[i];
15246
15247 scaler->in_use = 0;
15248 scaler->mode = PS_SCALER_MODE_DYN;
15249 }
15250
15251 scaler_state->scaler_id = -1;
15252 }
15253
15254 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
15255 {
15256 struct intel_crtc *intel_crtc;
15257 struct intel_crtc_state *crtc_state = NULL;
15258 struct intel_plane *primary = NULL;
15259 struct intel_plane *cursor = NULL;
15260 int sprite, ret;
15261
15262 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
15263 if (!intel_crtc)
15264 return -ENOMEM;
15265
15266 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
15267 if (!crtc_state) {
15268 ret = -ENOMEM;
15269 goto fail;
15270 }
15271 intel_crtc->config = crtc_state;
15272 intel_crtc->base.state = &crtc_state->base;
15273 crtc_state->base.crtc = &intel_crtc->base;
15274
15275 /* initialize shared scalers */
15276 if (INTEL_GEN(dev_priv) >= 9) {
15277 if (pipe == PIPE_C)
15278 intel_crtc->num_scalers = 1;
15279 else
15280 intel_crtc->num_scalers = SKL_NUM_SCALERS;
15281
15282 skl_init_scalers(dev_priv, intel_crtc, crtc_state);
15283 }
15284
15285 primary = intel_primary_plane_create(dev_priv, pipe);
15286 if (IS_ERR(primary)) {
15287 ret = PTR_ERR(primary);
15288 goto fail;
15289 }
15290
15291 for_each_sprite(dev_priv, pipe, sprite) {
15292 struct intel_plane *plane;
15293
15294 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
15295 if (IS_ERR(plane)) {
15296 ret = PTR_ERR(plane);
15297 goto fail;
15298 }
15299 }
15300
15301 cursor = intel_cursor_plane_create(dev_priv, pipe);
15302 if (IS_ERR(cursor)) {
15303 ret = PTR_ERR(cursor);
15304 goto fail;
15305 }
15306
15307 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
15308 &primary->base, &cursor->base,
15309 &intel_crtc_funcs,
15310 "pipe %c", pipe_name(pipe));
15311 if (ret)
15312 goto fail;
15313
15314 intel_crtc->pipe = pipe;
15315 intel_crtc->plane = primary->plane;
15316
15317 intel_crtc->cursor_base = ~0;
15318 intel_crtc->cursor_cntl = ~0;
15319 intel_crtc->cursor_size = ~0;
15320
15321 intel_crtc->wm.cxsr_allowed = true;
15322
15323 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15324 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
15325 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
15326 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
15327
15328 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
15329
15330 intel_color_init(&intel_crtc->base);
15331
15332 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15333
15334 return 0;
15335
15336 fail:
15337 /*
15338 * drm_mode_config_cleanup() will free up any
15339 * crtcs/planes already initialized.
15340 */
15341 kfree(crtc_state);
15342 kfree(intel_crtc);
15343
15344 return ret;
15345 }
15346
15347 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
15348 {
15349 struct drm_encoder *encoder = connector->base.encoder;
15350 struct drm_device *dev = connector->base.dev;
15351
15352 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
15353
15354 if (!encoder || WARN_ON(!encoder->crtc))
15355 return INVALID_PIPE;
15356
15357 return to_intel_crtc(encoder->crtc)->pipe;
15358 }
15359
15360 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
15361 struct drm_file *file)
15362 {
15363 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15364 struct drm_crtc *drmmode_crtc;
15365 struct intel_crtc *crtc;
15366
15367 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
15368 if (!drmmode_crtc)
15369 return -ENOENT;
15370
15371 crtc = to_intel_crtc(drmmode_crtc);
15372 pipe_from_crtc_id->pipe = crtc->pipe;
15373
15374 return 0;
15375 }
15376
15377 static int intel_encoder_clones(struct intel_encoder *encoder)
15378 {
15379 struct drm_device *dev = encoder->base.dev;
15380 struct intel_encoder *source_encoder;
15381 int index_mask = 0;
15382 int entry = 0;
15383
15384 for_each_intel_encoder(dev, source_encoder) {
15385 if (encoders_cloneable(encoder, source_encoder))
15386 index_mask |= (1 << entry);
15387
15388 entry++;
15389 }
15390
15391 return index_mask;
15392 }
15393
15394 static bool has_edp_a(struct drm_i915_private *dev_priv)
15395 {
15396 if (!IS_MOBILE(dev_priv))
15397 return false;
15398
15399 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15400 return false;
15401
15402 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
15403 return false;
15404
15405 return true;
15406 }
15407
15408 static bool intel_crt_present(struct drm_i915_private *dev_priv)
15409 {
15410 if (INTEL_GEN(dev_priv) >= 9)
15411 return false;
15412
15413 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
15414 return false;
15415
15416 if (IS_CHERRYVIEW(dev_priv))
15417 return false;
15418
15419 if (HAS_PCH_LPT_H(dev_priv) &&
15420 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15421 return false;
15422
15423 /* DDI E can't be used if DDI A requires 4 lanes */
15424 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15425 return false;
15426
15427 if (!dev_priv->vbt.int_crt_support)
15428 return false;
15429
15430 return true;
15431 }
15432
15433 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15434 {
15435 int pps_num;
15436 int pps_idx;
15437
15438 if (HAS_DDI(dev_priv))
15439 return;
15440 /*
15441 * This w/a is needed at least on CPT/PPT, but to be sure apply it
15442 * everywhere where registers can be write protected.
15443 */
15444 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15445 pps_num = 2;
15446 else
15447 pps_num = 1;
15448
15449 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
15450 u32 val = I915_READ(PP_CONTROL(pps_idx));
15451
15452 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
15453 I915_WRITE(PP_CONTROL(pps_idx), val);
15454 }
15455 }
15456
15457 static void intel_pps_init(struct drm_i915_private *dev_priv)
15458 {
15459 if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv))
15460 dev_priv->pps_mmio_base = PCH_PPS_BASE;
15461 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15462 dev_priv->pps_mmio_base = VLV_PPS_BASE;
15463 else
15464 dev_priv->pps_mmio_base = PPS_BASE;
15465
15466 intel_pps_unlock_regs_wa(dev_priv);
15467 }
15468
15469 static void intel_setup_outputs(struct drm_device *dev)
15470 {
15471 struct drm_i915_private *dev_priv = to_i915(dev);
15472 struct intel_encoder *encoder;
15473 bool dpd_is_edp = false;
15474
15475 intel_pps_init(dev_priv);
15476
15477 /*
15478 * intel_edp_init_connector() depends on this completing first, to
15479 * prevent the registeration of both eDP and LVDS and the incorrect
15480 * sharing of the PPS.
15481 */
15482 intel_lvds_init(dev);
15483
15484 if (intel_crt_present(dev_priv))
15485 intel_crt_init(dev);
15486
15487 if (IS_BROXTON(dev_priv)) {
15488 /*
15489 * FIXME: Broxton doesn't support port detection via the
15490 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
15491 * detect the ports.
15492 */
15493 intel_ddi_init(dev, PORT_A);
15494 intel_ddi_init(dev, PORT_B);
15495 intel_ddi_init(dev, PORT_C);
15496
15497 intel_dsi_init(dev);
15498 } else if (HAS_DDI(dev_priv)) {
15499 int found;
15500
15501 /*
15502 * Haswell uses DDI functions to detect digital outputs.
15503 * On SKL pre-D0 the strap isn't connected, so we assume
15504 * it's there.
15505 */
15506 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
15507 /* WaIgnoreDDIAStrap: skl */
15508 if (found || IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15509 intel_ddi_init(dev, PORT_A);
15510
15511 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
15512 * register */
15513 found = I915_READ(SFUSE_STRAP);
15514
15515 if (found & SFUSE_STRAP_DDIB_DETECTED)
15516 intel_ddi_init(dev, PORT_B);
15517 if (found & SFUSE_STRAP_DDIC_DETECTED)
15518 intel_ddi_init(dev, PORT_C);
15519 if (found & SFUSE_STRAP_DDID_DETECTED)
15520 intel_ddi_init(dev, PORT_D);
15521 /*
15522 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
15523 */
15524 if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
15525 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
15526 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
15527 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
15528 intel_ddi_init(dev, PORT_E);
15529
15530 } else if (HAS_PCH_SPLIT(dev_priv)) {
15531 int found;
15532 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
15533
15534 if (has_edp_a(dev_priv))
15535 intel_dp_init(dev, DP_A, PORT_A);
15536
15537 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
15538 /* PCH SDVOB multiplex with HDMIB */
15539 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
15540 if (!found)
15541 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
15542 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
15543 intel_dp_init(dev, PCH_DP_B, PORT_B);
15544 }
15545
15546 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
15547 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
15548
15549 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
15550 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
15551
15552 if (I915_READ(PCH_DP_C) & DP_DETECTED)
15553 intel_dp_init(dev, PCH_DP_C, PORT_C);
15554
15555 if (I915_READ(PCH_DP_D) & DP_DETECTED)
15556 intel_dp_init(dev, PCH_DP_D, PORT_D);
15557 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15558 bool has_edp, has_port;
15559
15560 /*
15561 * The DP_DETECTED bit is the latched state of the DDC
15562 * SDA pin at boot. However since eDP doesn't require DDC
15563 * (no way to plug in a DP->HDMI dongle) the DDC pins for
15564 * eDP ports may have been muxed to an alternate function.
15565 * Thus we can't rely on the DP_DETECTED bit alone to detect
15566 * eDP ports. Consult the VBT as well as DP_DETECTED to
15567 * detect eDP ports.
15568 *
15569 * Sadly the straps seem to be missing sometimes even for HDMI
15570 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
15571 * and VBT for the presence of the port. Additionally we can't
15572 * trust the port type the VBT declares as we've seen at least
15573 * HDMI ports that the VBT claim are DP or eDP.
15574 */
15575 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
15576 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
15577 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
15578 has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
15579 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
15580 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
15581
15582 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
15583 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
15584 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
15585 has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
15586 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
15587 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
15588
15589 if (IS_CHERRYVIEW(dev_priv)) {
15590 /*
15591 * eDP not supported on port D,
15592 * so no need to worry about it
15593 */
15594 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
15595 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
15596 intel_dp_init(dev, CHV_DP_D, PORT_D);
15597 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
15598 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
15599 }
15600
15601 intel_dsi_init(dev);
15602 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
15603 bool found = false;
15604
15605 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15606 DRM_DEBUG_KMS("probing SDVOB\n");
15607 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
15608 if (!found && IS_G4X(dev_priv)) {
15609 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
15610 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
15611 }
15612
15613 if (!found && IS_G4X(dev_priv))
15614 intel_dp_init(dev, DP_B, PORT_B);
15615 }
15616
15617 /* Before G4X SDVOC doesn't have its own detect register */
15618
15619 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15620 DRM_DEBUG_KMS("probing SDVOC\n");
15621 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
15622 }
15623
15624 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
15625
15626 if (IS_G4X(dev_priv)) {
15627 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
15628 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
15629 }
15630 if (IS_G4X(dev_priv))
15631 intel_dp_init(dev, DP_C, PORT_C);
15632 }
15633
15634 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
15635 intel_dp_init(dev, DP_D, PORT_D);
15636 } else if (IS_GEN2(dev_priv))
15637 intel_dvo_init(dev);
15638
15639 if (SUPPORTS_TV(dev_priv))
15640 intel_tv_init(dev);
15641
15642 intel_psr_init(dev);
15643
15644 for_each_intel_encoder(dev, encoder) {
15645 encoder->base.possible_crtcs = encoder->crtc_mask;
15646 encoder->base.possible_clones =
15647 intel_encoder_clones(encoder);
15648 }
15649
15650 intel_init_pch_refclk(dev);
15651
15652 drm_helper_move_panel_connectors_to_head(dev);
15653 }
15654
15655 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
15656 {
15657 struct drm_device *dev = fb->dev;
15658 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15659
15660 drm_framebuffer_cleanup(fb);
15661 mutex_lock(&dev->struct_mutex);
15662 WARN_ON(!intel_fb->obj->framebuffer_references--);
15663 i915_gem_object_put(intel_fb->obj);
15664 mutex_unlock(&dev->struct_mutex);
15665 kfree(intel_fb);
15666 }
15667
15668 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
15669 struct drm_file *file,
15670 unsigned int *handle)
15671 {
15672 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15673 struct drm_i915_gem_object *obj = intel_fb->obj;
15674
15675 if (obj->userptr.mm) {
15676 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15677 return -EINVAL;
15678 }
15679
15680 return drm_gem_handle_create(file, &obj->base, handle);
15681 }
15682
15683 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
15684 struct drm_file *file,
15685 unsigned flags, unsigned color,
15686 struct drm_clip_rect *clips,
15687 unsigned num_clips)
15688 {
15689 struct drm_device *dev = fb->dev;
15690 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15691 struct drm_i915_gem_object *obj = intel_fb->obj;
15692
15693 mutex_lock(&dev->struct_mutex);
15694 if (obj->pin_display && obj->cache_dirty)
15695 i915_gem_clflush_object(obj, true);
15696 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
15697 mutex_unlock(&dev->struct_mutex);
15698
15699 return 0;
15700 }
15701
15702 static const struct drm_framebuffer_funcs intel_fb_funcs = {
15703 .destroy = intel_user_framebuffer_destroy,
15704 .create_handle = intel_user_framebuffer_create_handle,
15705 .dirty = intel_user_framebuffer_dirty,
15706 };
15707
15708 static
15709 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
15710 uint64_t fb_modifier, uint32_t pixel_format)
15711 {
15712 u32 gen = INTEL_INFO(dev_priv)->gen;
15713
15714 if (gen >= 9) {
15715 int cpp = drm_format_plane_cpp(pixel_format, 0);
15716
15717 /* "The stride in bytes must not exceed the of the size of 8K
15718 * pixels and 32K bytes."
15719 */
15720 return min(8192 * cpp, 32768);
15721 } else if (gen >= 5 && !IS_VALLEYVIEW(dev_priv) &&
15722 !IS_CHERRYVIEW(dev_priv)) {
15723 return 32*1024;
15724 } else if (gen >= 4) {
15725 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15726 return 16*1024;
15727 else
15728 return 32*1024;
15729 } else if (gen >= 3) {
15730 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15731 return 8*1024;
15732 else
15733 return 16*1024;
15734 } else {
15735 /* XXX DSPC is limited to 4k tiled */
15736 return 8*1024;
15737 }
15738 }
15739
15740 static int intel_framebuffer_init(struct drm_device *dev,
15741 struct intel_framebuffer *intel_fb,
15742 struct drm_mode_fb_cmd2 *mode_cmd,
15743 struct drm_i915_gem_object *obj)
15744 {
15745 struct drm_i915_private *dev_priv = to_i915(dev);
15746 unsigned int tiling = i915_gem_object_get_tiling(obj);
15747 int ret;
15748 u32 pitch_limit, stride_alignment;
15749 struct drm_format_name_buf format_name;
15750
15751 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
15752
15753 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
15754 /*
15755 * If there's a fence, enforce that
15756 * the fb modifier and tiling mode match.
15757 */
15758 if (tiling != I915_TILING_NONE &&
15759 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15760 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
15761 return -EINVAL;
15762 }
15763 } else {
15764 if (tiling == I915_TILING_X) {
15765 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15766 } else if (tiling == I915_TILING_Y) {
15767 DRM_DEBUG("No Y tiling for legacy addfb\n");
15768 return -EINVAL;
15769 }
15770 }
15771
15772 /* Passed in modifier sanity checking. */
15773 switch (mode_cmd->modifier[0]) {
15774 case I915_FORMAT_MOD_Y_TILED:
15775 case I915_FORMAT_MOD_Yf_TILED:
15776 if (INTEL_GEN(dev_priv) < 9) {
15777 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15778 mode_cmd->modifier[0]);
15779 return -EINVAL;
15780 }
15781 case DRM_FORMAT_MOD_NONE:
15782 case I915_FORMAT_MOD_X_TILED:
15783 break;
15784 default:
15785 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15786 mode_cmd->modifier[0]);
15787 return -EINVAL;
15788 }
15789
15790 /*
15791 * gen2/3 display engine uses the fence if present,
15792 * so the tiling mode must match the fb modifier exactly.
15793 */
15794 if (INTEL_INFO(dev_priv)->gen < 4 &&
15795 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15796 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
15797 return -EINVAL;
15798 }
15799
15800 stride_alignment = intel_fb_stride_alignment(dev_priv,
15801 mode_cmd->modifier[0],
15802 mode_cmd->pixel_format);
15803 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
15804 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15805 mode_cmd->pitches[0], stride_alignment);
15806 return -EINVAL;
15807 }
15808
15809 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
15810 mode_cmd->pixel_format);
15811 if (mode_cmd->pitches[0] > pitch_limit) {
15812 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15813 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
15814 "tiled" : "linear",
15815 mode_cmd->pitches[0], pitch_limit);
15816 return -EINVAL;
15817 }
15818
15819 /*
15820 * If there's a fence, enforce that
15821 * the fb pitch and fence stride match.
15822 */
15823 if (tiling != I915_TILING_NONE &&
15824 mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) {
15825 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
15826 mode_cmd->pitches[0],
15827 i915_gem_object_get_stride(obj));
15828 return -EINVAL;
15829 }
15830
15831 /* Reject formats not supported by any plane early. */
15832 switch (mode_cmd->pixel_format) {
15833 case DRM_FORMAT_C8:
15834 case DRM_FORMAT_RGB565:
15835 case DRM_FORMAT_XRGB8888:
15836 case DRM_FORMAT_ARGB8888:
15837 break;
15838 case DRM_FORMAT_XRGB1555:
15839 if (INTEL_GEN(dev_priv) > 3) {
15840 DRM_DEBUG("unsupported pixel format: %s\n",
15841 drm_get_format_name(mode_cmd->pixel_format, &format_name));
15842 return -EINVAL;
15843 }
15844 break;
15845 case DRM_FORMAT_ABGR8888:
15846 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
15847 INTEL_GEN(dev_priv) < 9) {
15848 DRM_DEBUG("unsupported pixel format: %s\n",
15849 drm_get_format_name(mode_cmd->pixel_format, &format_name));
15850 return -EINVAL;
15851 }
15852 break;
15853 case DRM_FORMAT_XBGR8888:
15854 case DRM_FORMAT_XRGB2101010:
15855 case DRM_FORMAT_XBGR2101010:
15856 if (INTEL_GEN(dev_priv) < 4) {
15857 DRM_DEBUG("unsupported pixel format: %s\n",
15858 drm_get_format_name(mode_cmd->pixel_format, &format_name));
15859 return -EINVAL;
15860 }
15861 break;
15862 case DRM_FORMAT_ABGR2101010:
15863 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
15864 DRM_DEBUG("unsupported pixel format: %s\n",
15865 drm_get_format_name(mode_cmd->pixel_format, &format_name));
15866 return -EINVAL;
15867 }
15868 break;
15869 case DRM_FORMAT_YUYV:
15870 case DRM_FORMAT_UYVY:
15871 case DRM_FORMAT_YVYU:
15872 case DRM_FORMAT_VYUY:
15873 if (INTEL_GEN(dev_priv) < 5) {
15874 DRM_DEBUG("unsupported pixel format: %s\n",
15875 drm_get_format_name(mode_cmd->pixel_format, &format_name));
15876 return -EINVAL;
15877 }
15878 break;
15879 default:
15880 DRM_DEBUG("unsupported pixel format: %s\n",
15881 drm_get_format_name(mode_cmd->pixel_format, &format_name));
15882 return -EINVAL;
15883 }
15884
15885 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15886 if (mode_cmd->offsets[0] != 0)
15887 return -EINVAL;
15888
15889 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15890 intel_fb->obj = obj;
15891
15892 ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
15893 if (ret)
15894 return ret;
15895
15896 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15897 if (ret) {
15898 DRM_ERROR("framebuffer init failed %d\n", ret);
15899 return ret;
15900 }
15901
15902 intel_fb->obj->framebuffer_references++;
15903
15904 return 0;
15905 }
15906
15907 static struct drm_framebuffer *
15908 intel_user_framebuffer_create(struct drm_device *dev,
15909 struct drm_file *filp,
15910 const struct drm_mode_fb_cmd2 *user_mode_cmd)
15911 {
15912 struct drm_framebuffer *fb;
15913 struct drm_i915_gem_object *obj;
15914 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15915
15916 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
15917 if (!obj)
15918 return ERR_PTR(-ENOENT);
15919
15920 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15921 if (IS_ERR(fb))
15922 i915_gem_object_put(obj);
15923
15924 return fb;
15925 }
15926
15927 static const struct drm_mode_config_funcs intel_mode_funcs = {
15928 .fb_create = intel_user_framebuffer_create,
15929 .output_poll_changed = intel_fbdev_output_poll_changed,
15930 .atomic_check = intel_atomic_check,
15931 .atomic_commit = intel_atomic_commit,
15932 .atomic_state_alloc = intel_atomic_state_alloc,
15933 .atomic_state_clear = intel_atomic_state_clear,
15934 };
15935
15936 /**
15937 * intel_init_display_hooks - initialize the display modesetting hooks
15938 * @dev_priv: device private
15939 */
15940 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15941 {
15942 if (INTEL_INFO(dev_priv)->gen >= 9) {
15943 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15944 dev_priv->display.get_initial_plane_config =
15945 skylake_get_initial_plane_config;
15946 dev_priv->display.crtc_compute_clock =
15947 haswell_crtc_compute_clock;
15948 dev_priv->display.crtc_enable = haswell_crtc_enable;
15949 dev_priv->display.crtc_disable = haswell_crtc_disable;
15950 } else if (HAS_DDI(dev_priv)) {
15951 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15952 dev_priv->display.get_initial_plane_config =
15953 ironlake_get_initial_plane_config;
15954 dev_priv->display.crtc_compute_clock =
15955 haswell_crtc_compute_clock;
15956 dev_priv->display.crtc_enable = haswell_crtc_enable;
15957 dev_priv->display.crtc_disable = haswell_crtc_disable;
15958 } else if (HAS_PCH_SPLIT(dev_priv)) {
15959 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15960 dev_priv->display.get_initial_plane_config =
15961 ironlake_get_initial_plane_config;
15962 dev_priv->display.crtc_compute_clock =
15963 ironlake_crtc_compute_clock;
15964 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15965 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15966 } else if (IS_CHERRYVIEW(dev_priv)) {
15967 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15968 dev_priv->display.get_initial_plane_config =
15969 i9xx_get_initial_plane_config;
15970 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15971 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15972 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15973 } else if (IS_VALLEYVIEW(dev_priv)) {
15974 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15975 dev_priv->display.get_initial_plane_config =
15976 i9xx_get_initial_plane_config;
15977 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15978 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15979 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15980 } else if (IS_G4X(dev_priv)) {
15981 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15982 dev_priv->display.get_initial_plane_config =
15983 i9xx_get_initial_plane_config;
15984 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15985 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15986 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15987 } else if (IS_PINEVIEW(dev_priv)) {
15988 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15989 dev_priv->display.get_initial_plane_config =
15990 i9xx_get_initial_plane_config;
15991 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15992 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15993 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15994 } else if (!IS_GEN2(dev_priv)) {
15995 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15996 dev_priv->display.get_initial_plane_config =
15997 i9xx_get_initial_plane_config;
15998 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15999 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16000 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16001 } else {
16002 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16003 dev_priv->display.get_initial_plane_config =
16004 i9xx_get_initial_plane_config;
16005 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
16006 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16007 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16008 }
16009
16010 /* Returns the core display clock speed */
16011 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
16012 dev_priv->display.get_display_clock_speed =
16013 skylake_get_display_clock_speed;
16014 else if (IS_BROXTON(dev_priv))
16015 dev_priv->display.get_display_clock_speed =
16016 broxton_get_display_clock_speed;
16017 else if (IS_BROADWELL(dev_priv))
16018 dev_priv->display.get_display_clock_speed =
16019 broadwell_get_display_clock_speed;
16020 else if (IS_HASWELL(dev_priv))
16021 dev_priv->display.get_display_clock_speed =
16022 haswell_get_display_clock_speed;
16023 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16024 dev_priv->display.get_display_clock_speed =
16025 valleyview_get_display_clock_speed;
16026 else if (IS_GEN5(dev_priv))
16027 dev_priv->display.get_display_clock_speed =
16028 ilk_get_display_clock_speed;
16029 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
16030 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
16031 dev_priv->display.get_display_clock_speed =
16032 i945_get_display_clock_speed;
16033 else if (IS_GM45(dev_priv))
16034 dev_priv->display.get_display_clock_speed =
16035 gm45_get_display_clock_speed;
16036 else if (IS_CRESTLINE(dev_priv))
16037 dev_priv->display.get_display_clock_speed =
16038 i965gm_get_display_clock_speed;
16039 else if (IS_PINEVIEW(dev_priv))
16040 dev_priv->display.get_display_clock_speed =
16041 pnv_get_display_clock_speed;
16042 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
16043 dev_priv->display.get_display_clock_speed =
16044 g33_get_display_clock_speed;
16045 else if (IS_I915G(dev_priv))
16046 dev_priv->display.get_display_clock_speed =
16047 i915_get_display_clock_speed;
16048 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
16049 dev_priv->display.get_display_clock_speed =
16050 i9xx_misc_get_display_clock_speed;
16051 else if (IS_I915GM(dev_priv))
16052 dev_priv->display.get_display_clock_speed =
16053 i915gm_get_display_clock_speed;
16054 else if (IS_I865G(dev_priv))
16055 dev_priv->display.get_display_clock_speed =
16056 i865_get_display_clock_speed;
16057 else if (IS_I85X(dev_priv))
16058 dev_priv->display.get_display_clock_speed =
16059 i85x_get_display_clock_speed;
16060 else { /* 830 */
16061 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
16062 dev_priv->display.get_display_clock_speed =
16063 i830_get_display_clock_speed;
16064 }
16065
16066 if (IS_GEN5(dev_priv)) {
16067 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
16068 } else if (IS_GEN6(dev_priv)) {
16069 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
16070 } else if (IS_IVYBRIDGE(dev_priv)) {
16071 /* FIXME: detect B0+ stepping and use auto training */
16072 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
16073 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
16074 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
16075 }
16076
16077 if (IS_BROADWELL(dev_priv)) {
16078 dev_priv->display.modeset_commit_cdclk =
16079 broadwell_modeset_commit_cdclk;
16080 dev_priv->display.modeset_calc_cdclk =
16081 broadwell_modeset_calc_cdclk;
16082 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16083 dev_priv->display.modeset_commit_cdclk =
16084 valleyview_modeset_commit_cdclk;
16085 dev_priv->display.modeset_calc_cdclk =
16086 valleyview_modeset_calc_cdclk;
16087 } else if (IS_BROXTON(dev_priv)) {
16088 dev_priv->display.modeset_commit_cdclk =
16089 bxt_modeset_commit_cdclk;
16090 dev_priv->display.modeset_calc_cdclk =
16091 bxt_modeset_calc_cdclk;
16092 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
16093 dev_priv->display.modeset_commit_cdclk =
16094 skl_modeset_commit_cdclk;
16095 dev_priv->display.modeset_calc_cdclk =
16096 skl_modeset_calc_cdclk;
16097 }
16098
16099 if (dev_priv->info.gen >= 9)
16100 dev_priv->display.update_crtcs = skl_update_crtcs;
16101 else
16102 dev_priv->display.update_crtcs = intel_update_crtcs;
16103
16104 switch (INTEL_INFO(dev_priv)->gen) {
16105 case 2:
16106 dev_priv->display.queue_flip = intel_gen2_queue_flip;
16107 break;
16108
16109 case 3:
16110 dev_priv->display.queue_flip = intel_gen3_queue_flip;
16111 break;
16112
16113 case 4:
16114 case 5:
16115 dev_priv->display.queue_flip = intel_gen4_queue_flip;
16116 break;
16117
16118 case 6:
16119 dev_priv->display.queue_flip = intel_gen6_queue_flip;
16120 break;
16121 case 7:
16122 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
16123 dev_priv->display.queue_flip = intel_gen7_queue_flip;
16124 break;
16125 case 9:
16126 /* Drop through - unsupported since execlist only. */
16127 default:
16128 /* Default just returns -ENODEV to indicate unsupported */
16129 dev_priv->display.queue_flip = intel_default_queue_flip;
16130 }
16131 }
16132
16133 /*
16134 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
16135 * resume, or other times. This quirk makes sure that's the case for
16136 * affected systems.
16137 */
16138 static void quirk_pipea_force(struct drm_device *dev)
16139 {
16140 struct drm_i915_private *dev_priv = to_i915(dev);
16141
16142 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
16143 DRM_INFO("applying pipe a force quirk\n");
16144 }
16145
16146 static void quirk_pipeb_force(struct drm_device *dev)
16147 {
16148 struct drm_i915_private *dev_priv = to_i915(dev);
16149
16150 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
16151 DRM_INFO("applying pipe b force quirk\n");
16152 }
16153
16154 /*
16155 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
16156 */
16157 static void quirk_ssc_force_disable(struct drm_device *dev)
16158 {
16159 struct drm_i915_private *dev_priv = to_i915(dev);
16160 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
16161 DRM_INFO("applying lvds SSC disable quirk\n");
16162 }
16163
16164 /*
16165 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
16166 * brightness value
16167 */
16168 static void quirk_invert_brightness(struct drm_device *dev)
16169 {
16170 struct drm_i915_private *dev_priv = to_i915(dev);
16171 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
16172 DRM_INFO("applying inverted panel brightness quirk\n");
16173 }
16174
16175 /* Some VBT's incorrectly indicate no backlight is present */
16176 static void quirk_backlight_present(struct drm_device *dev)
16177 {
16178 struct drm_i915_private *dev_priv = to_i915(dev);
16179 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
16180 DRM_INFO("applying backlight present quirk\n");
16181 }
16182
16183 struct intel_quirk {
16184 int device;
16185 int subsystem_vendor;
16186 int subsystem_device;
16187 void (*hook)(struct drm_device *dev);
16188 };
16189
16190 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
16191 struct intel_dmi_quirk {
16192 void (*hook)(struct drm_device *dev);
16193 const struct dmi_system_id (*dmi_id_list)[];
16194 };
16195
16196 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
16197 {
16198 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
16199 return 1;
16200 }
16201
16202 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
16203 {
16204 .dmi_id_list = &(const struct dmi_system_id[]) {
16205 {
16206 .callback = intel_dmi_reverse_brightness,
16207 .ident = "NCR Corporation",
16208 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
16209 DMI_MATCH(DMI_PRODUCT_NAME, ""),
16210 },
16211 },
16212 { } /* terminating entry */
16213 },
16214 .hook = quirk_invert_brightness,
16215 },
16216 };
16217
16218 static struct intel_quirk intel_quirks[] = {
16219 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
16220 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
16221
16222 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
16223 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
16224
16225 /* 830 needs to leave pipe A & dpll A up */
16226 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
16227
16228 /* 830 needs to leave pipe B & dpll B up */
16229 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
16230
16231 /* Lenovo U160 cannot use SSC on LVDS */
16232 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
16233
16234 /* Sony Vaio Y cannot use SSC on LVDS */
16235 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
16236
16237 /* Acer Aspire 5734Z must invert backlight brightness */
16238 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
16239
16240 /* Acer/eMachines G725 */
16241 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
16242
16243 /* Acer/eMachines e725 */
16244 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
16245
16246 /* Acer/Packard Bell NCL20 */
16247 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
16248
16249 /* Acer Aspire 4736Z */
16250 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
16251
16252 /* Acer Aspire 5336 */
16253 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
16254
16255 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
16256 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
16257
16258 /* Acer C720 Chromebook (Core i3 4005U) */
16259 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
16260
16261 /* Apple Macbook 2,1 (Core 2 T7400) */
16262 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
16263
16264 /* Apple Macbook 4,1 */
16265 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
16266
16267 /* Toshiba CB35 Chromebook (Celeron 2955U) */
16268 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
16269
16270 /* HP Chromebook 14 (Celeron 2955U) */
16271 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
16272
16273 /* Dell Chromebook 11 */
16274 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
16275
16276 /* Dell Chromebook 11 (2015 version) */
16277 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
16278 };
16279
16280 static void intel_init_quirks(struct drm_device *dev)
16281 {
16282 struct pci_dev *d = dev->pdev;
16283 int i;
16284
16285 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
16286 struct intel_quirk *q = &intel_quirks[i];
16287
16288 if (d->device == q->device &&
16289 (d->subsystem_vendor == q->subsystem_vendor ||
16290 q->subsystem_vendor == PCI_ANY_ID) &&
16291 (d->subsystem_device == q->subsystem_device ||
16292 q->subsystem_device == PCI_ANY_ID))
16293 q->hook(dev);
16294 }
16295 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
16296 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
16297 intel_dmi_quirks[i].hook(dev);
16298 }
16299 }
16300
16301 /* Disable the VGA plane that we never use */
16302 static void i915_disable_vga(struct drm_i915_private *dev_priv)
16303 {
16304 struct pci_dev *pdev = dev_priv->drm.pdev;
16305 u8 sr1;
16306 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
16307
16308 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
16309 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
16310 outb(SR01, VGA_SR_INDEX);
16311 sr1 = inb(VGA_SR_DATA);
16312 outb(sr1 | 1<<5, VGA_SR_DATA);
16313 vga_put(pdev, VGA_RSRC_LEGACY_IO);
16314 udelay(300);
16315
16316 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
16317 POSTING_READ(vga_reg);
16318 }
16319
16320 void intel_modeset_init_hw(struct drm_device *dev)
16321 {
16322 struct drm_i915_private *dev_priv = to_i915(dev);
16323
16324 intel_update_cdclk(dev_priv);
16325
16326 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16327
16328 intel_init_clock_gating(dev_priv);
16329 }
16330
16331 /*
16332 * Calculate what we think the watermarks should be for the state we've read
16333 * out of the hardware and then immediately program those watermarks so that
16334 * we ensure the hardware settings match our internal state.
16335 *
16336 * We can calculate what we think WM's should be by creating a duplicate of the
16337 * current state (which was constructed during hardware readout) and running it
16338 * through the atomic check code to calculate new watermark values in the
16339 * state object.
16340 */
16341 static void sanitize_watermarks(struct drm_device *dev)
16342 {
16343 struct drm_i915_private *dev_priv = to_i915(dev);
16344 struct drm_atomic_state *state;
16345 struct intel_atomic_state *intel_state;
16346 struct drm_crtc *crtc;
16347 struct drm_crtc_state *cstate;
16348 struct drm_modeset_acquire_ctx ctx;
16349 int ret;
16350 int i;
16351
16352 /* Only supported on platforms that use atomic watermark design */
16353 if (!dev_priv->display.optimize_watermarks)
16354 return;
16355
16356 /*
16357 * We need to hold connection_mutex before calling duplicate_state so
16358 * that the connector loop is protected.
16359 */
16360 drm_modeset_acquire_init(&ctx, 0);
16361 retry:
16362 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16363 if (ret == -EDEADLK) {
16364 drm_modeset_backoff(&ctx);
16365 goto retry;
16366 } else if (WARN_ON(ret)) {
16367 goto fail;
16368 }
16369
16370 state = drm_atomic_helper_duplicate_state(dev, &ctx);
16371 if (WARN_ON(IS_ERR(state)))
16372 goto fail;
16373
16374 intel_state = to_intel_atomic_state(state);
16375
16376 /*
16377 * Hardware readout is the only time we don't want to calculate
16378 * intermediate watermarks (since we don't trust the current
16379 * watermarks).
16380 */
16381 intel_state->skip_intermediate_wm = true;
16382
16383 ret = intel_atomic_check(dev, state);
16384 if (ret) {
16385 /*
16386 * If we fail here, it means that the hardware appears to be
16387 * programmed in a way that shouldn't be possible, given our
16388 * understanding of watermark requirements. This might mean a
16389 * mistake in the hardware readout code or a mistake in the
16390 * watermark calculations for a given platform. Raise a WARN
16391 * so that this is noticeable.
16392 *
16393 * If this actually happens, we'll have to just leave the
16394 * BIOS-programmed watermarks untouched and hope for the best.
16395 */
16396 WARN(true, "Could not determine valid watermarks for inherited state\n");
16397 goto put_state;
16398 }
16399
16400 /* Write calculated watermark values back */
16401 for_each_crtc_in_state(state, crtc, cstate, i) {
16402 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
16403
16404 cs->wm.need_postvbl_update = true;
16405 dev_priv->display.optimize_watermarks(intel_state, cs);
16406 }
16407
16408 put_state:
16409 drm_atomic_state_put(state);
16410 fail:
16411 drm_modeset_drop_locks(&ctx);
16412 drm_modeset_acquire_fini(&ctx);
16413 }
16414
16415 static void intel_atomic_helper_free_state(struct work_struct *work)
16416 {
16417 struct drm_i915_private *dev_priv =
16418 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
16419 struct intel_atomic_state *state, *next;
16420 struct llist_node *freed;
16421
16422 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
16423 llist_for_each_entry_safe(state, next, freed, freed)
16424 drm_atomic_state_put(&state->base);
16425 }
16426
16427 int intel_modeset_init(struct drm_device *dev)
16428 {
16429 struct drm_i915_private *dev_priv = to_i915(dev);
16430 struct i915_ggtt *ggtt = &dev_priv->ggtt;
16431 enum pipe pipe;
16432 struct intel_crtc *crtc;
16433
16434 drm_mode_config_init(dev);
16435
16436 dev->mode_config.min_width = 0;
16437 dev->mode_config.min_height = 0;
16438
16439 dev->mode_config.preferred_depth = 24;
16440 dev->mode_config.prefer_shadow = 1;
16441
16442 dev->mode_config.allow_fb_modifiers = true;
16443
16444 dev->mode_config.funcs = &intel_mode_funcs;
16445
16446 INIT_WORK(&dev_priv->atomic_helper.free_work,
16447 intel_atomic_helper_free_state);
16448
16449 intel_init_quirks(dev);
16450
16451 intel_init_pm(dev_priv);
16452
16453 if (INTEL_INFO(dev_priv)->num_pipes == 0)
16454 return 0;
16455
16456 /*
16457 * There may be no VBT; and if the BIOS enabled SSC we can
16458 * just keep using it to avoid unnecessary flicker. Whereas if the
16459 * BIOS isn't using it, don't assume it will work even if the VBT
16460 * indicates as much.
16461 */
16462 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
16463 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
16464 DREF_SSC1_ENABLE);
16465
16466 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
16467 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
16468 bios_lvds_use_ssc ? "en" : "dis",
16469 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
16470 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
16471 }
16472 }
16473
16474 if (IS_GEN2(dev_priv)) {
16475 dev->mode_config.max_width = 2048;
16476 dev->mode_config.max_height = 2048;
16477 } else if (IS_GEN3(dev_priv)) {
16478 dev->mode_config.max_width = 4096;
16479 dev->mode_config.max_height = 4096;
16480 } else {
16481 dev->mode_config.max_width = 8192;
16482 dev->mode_config.max_height = 8192;
16483 }
16484
16485 if (IS_845G(dev_priv) || IS_I865G(dev_priv)) {
16486 dev->mode_config.cursor_width = IS_845G(dev_priv) ? 64 : 512;
16487 dev->mode_config.cursor_height = 1023;
16488 } else if (IS_GEN2(dev_priv)) {
16489 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
16490 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
16491 } else {
16492 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
16493 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
16494 }
16495
16496 dev->mode_config.fb_base = ggtt->mappable_base;
16497
16498 DRM_DEBUG_KMS("%d display pipe%s available.\n",
16499 INTEL_INFO(dev_priv)->num_pipes,
16500 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
16501
16502 for_each_pipe(dev_priv, pipe) {
16503 int ret;
16504
16505 ret = intel_crtc_init(dev_priv, pipe);
16506 if (ret) {
16507 drm_mode_config_cleanup(dev);
16508 return ret;
16509 }
16510 }
16511
16512 intel_update_czclk(dev_priv);
16513 intel_update_cdclk(dev_priv);
16514 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16515
16516 intel_shared_dpll_init(dev);
16517
16518 if (dev_priv->max_cdclk_freq == 0)
16519 intel_update_max_cdclk(dev_priv);
16520
16521 /* Just disable it once at startup */
16522 i915_disable_vga(dev_priv);
16523 intel_setup_outputs(dev);
16524
16525 drm_modeset_lock_all(dev);
16526 intel_modeset_setup_hw_state(dev);
16527 drm_modeset_unlock_all(dev);
16528
16529 for_each_intel_crtc(dev, crtc) {
16530 struct intel_initial_plane_config plane_config = {};
16531
16532 if (!crtc->active)
16533 continue;
16534
16535 /*
16536 * Note that reserving the BIOS fb up front prevents us
16537 * from stuffing other stolen allocations like the ring
16538 * on top. This prevents some ugliness at boot time, and
16539 * can even allow for smooth boot transitions if the BIOS
16540 * fb is large enough for the active pipe configuration.
16541 */
16542 dev_priv->display.get_initial_plane_config(crtc,
16543 &plane_config);
16544
16545 /*
16546 * If the fb is shared between multiple heads, we'll
16547 * just get the first one.
16548 */
16549 intel_find_initial_plane_obj(crtc, &plane_config);
16550 }
16551
16552 /*
16553 * Make sure hardware watermarks really match the state we read out.
16554 * Note that we need to do this after reconstructing the BIOS fb's
16555 * since the watermark calculation done here will use pstate->fb.
16556 */
16557 sanitize_watermarks(dev);
16558
16559 return 0;
16560 }
16561
16562 static void intel_enable_pipe_a(struct drm_device *dev)
16563 {
16564 struct intel_connector *connector;
16565 struct drm_connector *crt = NULL;
16566 struct intel_load_detect_pipe load_detect_temp;
16567 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
16568
16569 /* We can't just switch on the pipe A, we need to set things up with a
16570 * proper mode and output configuration. As a gross hack, enable pipe A
16571 * by enabling the load detect pipe once. */
16572 for_each_intel_connector(dev, connector) {
16573 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
16574 crt = &connector->base;
16575 break;
16576 }
16577 }
16578
16579 if (!crt)
16580 return;
16581
16582 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
16583 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
16584 }
16585
16586 static bool
16587 intel_check_plane_mapping(struct intel_crtc *crtc)
16588 {
16589 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
16590 u32 val;
16591
16592 if (INTEL_INFO(dev_priv)->num_pipes == 1)
16593 return true;
16594
16595 val = I915_READ(DSPCNTR(!crtc->plane));
16596
16597 if ((val & DISPLAY_PLANE_ENABLE) &&
16598 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
16599 return false;
16600
16601 return true;
16602 }
16603
16604 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
16605 {
16606 struct drm_device *dev = crtc->base.dev;
16607 struct intel_encoder *encoder;
16608
16609 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
16610 return true;
16611
16612 return false;
16613 }
16614
16615 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
16616 {
16617 struct drm_device *dev = encoder->base.dev;
16618 struct intel_connector *connector;
16619
16620 for_each_connector_on_encoder(dev, &encoder->base, connector)
16621 return connector;
16622
16623 return NULL;
16624 }
16625
16626 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
16627 enum transcoder pch_transcoder)
16628 {
16629 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
16630 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
16631 }
16632
16633 static void intel_sanitize_crtc(struct intel_crtc *crtc)
16634 {
16635 struct drm_device *dev = crtc->base.dev;
16636 struct drm_i915_private *dev_priv = to_i915(dev);
16637 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
16638
16639 /* Clear any frame start delays used for debugging left by the BIOS */
16640 if (!transcoder_is_dsi(cpu_transcoder)) {
16641 i915_reg_t reg = PIPECONF(cpu_transcoder);
16642
16643 I915_WRITE(reg,
16644 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
16645 }
16646
16647 /* restore vblank interrupts to correct state */
16648 drm_crtc_vblank_reset(&crtc->base);
16649 if (crtc->active) {
16650 struct intel_plane *plane;
16651
16652 drm_crtc_vblank_on(&crtc->base);
16653
16654 /* Disable everything but the primary plane */
16655 for_each_intel_plane_on_crtc(dev, crtc, plane) {
16656 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
16657 continue;
16658
16659 plane->disable_plane(&plane->base, &crtc->base);
16660 }
16661 }
16662
16663 /* We need to sanitize the plane -> pipe mapping first because this will
16664 * disable the crtc (and hence change the state) if it is wrong. Note
16665 * that gen4+ has a fixed plane -> pipe mapping. */
16666 if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
16667 bool plane;
16668
16669 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
16670 crtc->base.base.id, crtc->base.name);
16671
16672 /* Pipe has the wrong plane attached and the plane is active.
16673 * Temporarily change the plane mapping and disable everything
16674 * ... */
16675 plane = crtc->plane;
16676 to_intel_plane_state(crtc->base.primary->state)->base.visible = true;
16677 crtc->plane = !plane;
16678 intel_crtc_disable_noatomic(&crtc->base);
16679 crtc->plane = plane;
16680 }
16681
16682 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
16683 crtc->pipe == PIPE_A && !crtc->active) {
16684 /* BIOS forgot to enable pipe A, this mostly happens after
16685 * resume. Force-enable the pipe to fix this, the update_dpms
16686 * call below we restore the pipe to the right state, but leave
16687 * the required bits on. */
16688 intel_enable_pipe_a(dev);
16689 }
16690
16691 /* Adjust the state of the output pipe according to whether we
16692 * have active connectors/encoders. */
16693 if (crtc->active && !intel_crtc_has_encoders(crtc))
16694 intel_crtc_disable_noatomic(&crtc->base);
16695
16696 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
16697 /*
16698 * We start out with underrun reporting disabled to avoid races.
16699 * For correct bookkeeping mark this on active crtcs.
16700 *
16701 * Also on gmch platforms we dont have any hardware bits to
16702 * disable the underrun reporting. Which means we need to start
16703 * out with underrun reporting disabled also on inactive pipes,
16704 * since otherwise we'll complain about the garbage we read when
16705 * e.g. coming up after runtime pm.
16706 *
16707 * No protection against concurrent access is required - at
16708 * worst a fifo underrun happens which also sets this to false.
16709 */
16710 crtc->cpu_fifo_underrun_disabled = true;
16711 /*
16712 * We track the PCH trancoder underrun reporting state
16713 * within the crtc. With crtc for pipe A housing the underrun
16714 * reporting state for PCH transcoder A, crtc for pipe B housing
16715 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16716 * and marking underrun reporting as disabled for the non-existing
16717 * PCH transcoders B and C would prevent enabling the south
16718 * error interrupt (see cpt_can_enable_serr_int()).
16719 */
16720 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
16721 crtc->pch_fifo_underrun_disabled = true;
16722 }
16723 }
16724
16725 static void intel_sanitize_encoder(struct intel_encoder *encoder)
16726 {
16727 struct intel_connector *connector;
16728
16729 /* We need to check both for a crtc link (meaning that the
16730 * encoder is active and trying to read from a pipe) and the
16731 * pipe itself being active. */
16732 bool has_active_crtc = encoder->base.crtc &&
16733 to_intel_crtc(encoder->base.crtc)->active;
16734
16735 connector = intel_encoder_find_connector(encoder);
16736 if (connector && !has_active_crtc) {
16737 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16738 encoder->base.base.id,
16739 encoder->base.name);
16740
16741 /* Connector is active, but has no active pipe. This is
16742 * fallout from our resume register restoring. Disable
16743 * the encoder manually again. */
16744 if (encoder->base.crtc) {
16745 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
16746
16747 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16748 encoder->base.base.id,
16749 encoder->base.name);
16750 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16751 if (encoder->post_disable)
16752 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16753 }
16754 encoder->base.crtc = NULL;
16755
16756 /* Inconsistent output/port/pipe state happens presumably due to
16757 * a bug in one of the get_hw_state functions. Or someplace else
16758 * in our code, like the register restore mess on resume. Clamp
16759 * things to off as a safer default. */
16760
16761 connector->base.dpms = DRM_MODE_DPMS_OFF;
16762 connector->base.encoder = NULL;
16763 }
16764 /* Enabled encoders without active connectors will be fixed in
16765 * the crtc fixup. */
16766 }
16767
16768 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
16769 {
16770 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
16771
16772 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
16773 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16774 i915_disable_vga(dev_priv);
16775 }
16776 }
16777
16778 void i915_redisable_vga(struct drm_i915_private *dev_priv)
16779 {
16780 /* This function can be called both from intel_modeset_setup_hw_state or
16781 * at a very early point in our resume sequence, where the power well
16782 * structures are not yet restored. Since this function is at a very
16783 * paranoid "someone might have enabled VGA while we were not looking"
16784 * level, just check if the power well is enabled instead of trying to
16785 * follow the "don't touch the power well if we don't need it" policy
16786 * the rest of the driver uses. */
16787 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
16788 return;
16789
16790 i915_redisable_vga_power_on(dev_priv);
16791
16792 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
16793 }
16794
16795 static bool primary_get_hw_state(struct intel_plane *plane)
16796 {
16797 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16798
16799 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
16800 }
16801
16802 /* FIXME read out full plane state for all planes */
16803 static void readout_plane_state(struct intel_crtc *crtc)
16804 {
16805 struct drm_plane *primary = crtc->base.primary;
16806 struct intel_plane_state *plane_state =
16807 to_intel_plane_state(primary->state);
16808
16809 plane_state->base.visible = crtc->active &&
16810 primary_get_hw_state(to_intel_plane(primary));
16811
16812 if (plane_state->base.visible)
16813 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
16814 }
16815
16816 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16817 {
16818 struct drm_i915_private *dev_priv = to_i915(dev);
16819 enum pipe pipe;
16820 struct intel_crtc *crtc;
16821 struct intel_encoder *encoder;
16822 struct intel_connector *connector;
16823 int i;
16824
16825 dev_priv->active_crtcs = 0;
16826
16827 for_each_intel_crtc(dev, crtc) {
16828 struct intel_crtc_state *crtc_state = crtc->config;
16829
16830 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16831 memset(crtc_state, 0, sizeof(*crtc_state));
16832 crtc_state->base.crtc = &crtc->base;
16833
16834 crtc_state->base.active = crtc_state->base.enable =
16835 dev_priv->display.get_pipe_config(crtc, crtc_state);
16836
16837 crtc->base.enabled = crtc_state->base.enable;
16838 crtc->active = crtc_state->base.active;
16839
16840 if (crtc_state->base.active)
16841 dev_priv->active_crtcs |= 1 << crtc->pipe;
16842
16843 readout_plane_state(crtc);
16844
16845 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16846 crtc->base.base.id, crtc->base.name,
16847 enableddisabled(crtc->active));
16848 }
16849
16850 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16851 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16852
16853 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16854 &pll->config.hw_state);
16855 pll->config.crtc_mask = 0;
16856 for_each_intel_crtc(dev, crtc) {
16857 if (crtc->active && crtc->config->shared_dpll == pll)
16858 pll->config.crtc_mask |= 1 << crtc->pipe;
16859 }
16860 pll->active_mask = pll->config.crtc_mask;
16861
16862 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16863 pll->name, pll->config.crtc_mask, pll->on);
16864 }
16865
16866 for_each_intel_encoder(dev, encoder) {
16867 pipe = 0;
16868
16869 if (encoder->get_hw_state(encoder, &pipe)) {
16870 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
16871
16872 encoder->base.crtc = &crtc->base;
16873 crtc->config->output_types |= 1 << encoder->type;
16874 encoder->get_config(encoder, crtc->config);
16875 } else {
16876 encoder->base.crtc = NULL;
16877 }
16878
16879 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16880 encoder->base.base.id, encoder->base.name,
16881 enableddisabled(encoder->base.crtc),
16882 pipe_name(pipe));
16883 }
16884
16885 for_each_intel_connector(dev, connector) {
16886 if (connector->get_hw_state(connector)) {
16887 connector->base.dpms = DRM_MODE_DPMS_ON;
16888
16889 encoder = connector->encoder;
16890 connector->base.encoder = &encoder->base;
16891
16892 if (encoder->base.crtc &&
16893 encoder->base.crtc->state->active) {
16894 /*
16895 * This has to be done during hardware readout
16896 * because anything calling .crtc_disable may
16897 * rely on the connector_mask being accurate.
16898 */
16899 encoder->base.crtc->state->connector_mask |=
16900 1 << drm_connector_index(&connector->base);
16901 encoder->base.crtc->state->encoder_mask |=
16902 1 << drm_encoder_index(&encoder->base);
16903 }
16904
16905 } else {
16906 connector->base.dpms = DRM_MODE_DPMS_OFF;
16907 connector->base.encoder = NULL;
16908 }
16909 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16910 connector->base.base.id, connector->base.name,
16911 enableddisabled(connector->base.encoder));
16912 }
16913
16914 for_each_intel_crtc(dev, crtc) {
16915 int pixclk = 0;
16916
16917 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16918
16919 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16920 if (crtc->base.state->active) {
16921 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16922 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16923 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16924
16925 /*
16926 * The initial mode needs to be set in order to keep
16927 * the atomic core happy. It wants a valid mode if the
16928 * crtc's enabled, so we do the above call.
16929 *
16930 * At this point some state updated by the connectors
16931 * in their ->detect() callback has not run yet, so
16932 * no recalculation can be done yet.
16933 *
16934 * Even if we could do a recalculation and modeset
16935 * right now it would cause a double modeset if
16936 * fbdev or userspace chooses a different initial mode.
16937 *
16938 * If that happens, someone indicated they wanted a
16939 * mode change, which means it's safe to do a full
16940 * recalculation.
16941 */
16942 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16943
16944 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
16945 pixclk = ilk_pipe_pixel_rate(crtc->config);
16946 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16947 pixclk = crtc->config->base.adjusted_mode.crtc_clock;
16948 else
16949 WARN_ON(dev_priv->display.modeset_calc_cdclk);
16950
16951 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
16952 if (IS_BROADWELL(dev_priv) && crtc->config->ips_enabled)
16953 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
16954
16955 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16956 update_scanline_offset(crtc);
16957 }
16958
16959 dev_priv->min_pixclk[crtc->pipe] = pixclk;
16960
16961 intel_pipe_config_sanity_check(dev_priv, crtc->config);
16962 }
16963 }
16964
16965 /* Scan out the current hw modeset state,
16966 * and sanitizes it to the current state
16967 */
16968 static void
16969 intel_modeset_setup_hw_state(struct drm_device *dev)
16970 {
16971 struct drm_i915_private *dev_priv = to_i915(dev);
16972 enum pipe pipe;
16973 struct intel_crtc *crtc;
16974 struct intel_encoder *encoder;
16975 int i;
16976
16977 intel_modeset_readout_hw_state(dev);
16978
16979 /* HW state is read out, now we need to sanitize this mess. */
16980 for_each_intel_encoder(dev, encoder) {
16981 intel_sanitize_encoder(encoder);
16982 }
16983
16984 for_each_pipe(dev_priv, pipe) {
16985 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
16986
16987 intel_sanitize_crtc(crtc);
16988 intel_dump_pipe_config(crtc, crtc->config,
16989 "[setup_hw_state]");
16990 }
16991
16992 intel_modeset_update_connector_atomic_state(dev);
16993
16994 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16995 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16996
16997 if (!pll->on || pll->active_mask)
16998 continue;
16999
17000 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
17001
17002 pll->funcs.disable(dev_priv, pll);
17003 pll->on = false;
17004 }
17005
17006 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
17007 vlv_wm_get_hw_state(dev);
17008 else if (IS_GEN9(dev_priv))
17009 skl_wm_get_hw_state(dev);
17010 else if (HAS_PCH_SPLIT(dev_priv))
17011 ilk_wm_get_hw_state(dev);
17012
17013 for_each_intel_crtc(dev, crtc) {
17014 unsigned long put_domains;
17015
17016 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
17017 if (WARN_ON(put_domains))
17018 modeset_put_power_domains(dev_priv, put_domains);
17019 }
17020 intel_display_set_init_power(dev_priv, false);
17021
17022 intel_fbc_init_pipe_state(dev_priv);
17023 }
17024
17025 void intel_display_resume(struct drm_device *dev)
17026 {
17027 struct drm_i915_private *dev_priv = to_i915(dev);
17028 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
17029 struct drm_modeset_acquire_ctx ctx;
17030 int ret;
17031
17032 dev_priv->modeset_restore_state = NULL;
17033 if (state)
17034 state->acquire_ctx = &ctx;
17035
17036 /*
17037 * This is a cludge because with real atomic modeset mode_config.mutex
17038 * won't be taken. Unfortunately some probed state like
17039 * audio_codec_enable is still protected by mode_config.mutex, so lock
17040 * it here for now.
17041 */
17042 mutex_lock(&dev->mode_config.mutex);
17043 drm_modeset_acquire_init(&ctx, 0);
17044
17045 while (1) {
17046 ret = drm_modeset_lock_all_ctx(dev, &ctx);
17047 if (ret != -EDEADLK)
17048 break;
17049
17050 drm_modeset_backoff(&ctx);
17051 }
17052
17053 if (!ret)
17054 ret = __intel_display_resume(dev, state);
17055
17056 drm_modeset_drop_locks(&ctx);
17057 drm_modeset_acquire_fini(&ctx);
17058 mutex_unlock(&dev->mode_config.mutex);
17059
17060 if (ret)
17061 DRM_ERROR("Restoring old state failed with %i\n", ret);
17062 if (state)
17063 drm_atomic_state_put(state);
17064 }
17065
17066 void intel_modeset_gem_init(struct drm_device *dev)
17067 {
17068 struct drm_i915_private *dev_priv = to_i915(dev);
17069 struct drm_crtc *c;
17070 struct drm_i915_gem_object *obj;
17071
17072 intel_init_gt_powersave(dev_priv);
17073
17074 intel_modeset_init_hw(dev);
17075
17076 intel_setup_overlay(dev_priv);
17077
17078 /*
17079 * Make sure any fbs we allocated at startup are properly
17080 * pinned & fenced. When we do the allocation it's too early
17081 * for this.
17082 */
17083 for_each_crtc(dev, c) {
17084 struct i915_vma *vma;
17085
17086 obj = intel_fb_obj(c->primary->fb);
17087 if (obj == NULL)
17088 continue;
17089
17090 mutex_lock(&dev->struct_mutex);
17091 vma = intel_pin_and_fence_fb_obj(c->primary->fb,
17092 c->primary->state->rotation);
17093 mutex_unlock(&dev->struct_mutex);
17094 if (IS_ERR(vma)) {
17095 DRM_ERROR("failed to pin boot fb on pipe %d\n",
17096 to_intel_crtc(c)->pipe);
17097 drm_framebuffer_unreference(c->primary->fb);
17098 c->primary->fb = NULL;
17099 c->primary->crtc = c->primary->state->crtc = NULL;
17100 update_state_fb(c->primary);
17101 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
17102 }
17103 }
17104 }
17105
17106 int intel_connector_register(struct drm_connector *connector)
17107 {
17108 struct intel_connector *intel_connector = to_intel_connector(connector);
17109 int ret;
17110
17111 ret = intel_backlight_device_register(intel_connector);
17112 if (ret)
17113 goto err;
17114
17115 return 0;
17116
17117 err:
17118 return ret;
17119 }
17120
17121 void intel_connector_unregister(struct drm_connector *connector)
17122 {
17123 struct intel_connector *intel_connector = to_intel_connector(connector);
17124
17125 intel_backlight_device_unregister(intel_connector);
17126 intel_panel_destroy_backlight(connector);
17127 }
17128
17129 void intel_modeset_cleanup(struct drm_device *dev)
17130 {
17131 struct drm_i915_private *dev_priv = to_i915(dev);
17132
17133 flush_work(&dev_priv->atomic_helper.free_work);
17134 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
17135
17136 intel_disable_gt_powersave(dev_priv);
17137
17138 /*
17139 * Interrupts and polling as the first thing to avoid creating havoc.
17140 * Too much stuff here (turning of connectors, ...) would
17141 * experience fancy races otherwise.
17142 */
17143 intel_irq_uninstall(dev_priv);
17144
17145 /*
17146 * Due to the hpd irq storm handling the hotplug work can re-arm the
17147 * poll handlers. Hence disable polling after hpd handling is shut down.
17148 */
17149 drm_kms_helper_poll_fini(dev);
17150
17151 intel_unregister_dsm_handler();
17152
17153 intel_fbc_global_disable(dev_priv);
17154
17155 /* flush any delayed tasks or pending work */
17156 flush_scheduled_work();
17157
17158 drm_mode_config_cleanup(dev);
17159
17160 intel_cleanup_overlay(dev_priv);
17161
17162 intel_cleanup_gt_powersave(dev_priv);
17163
17164 intel_teardown_gmbus(dev);
17165 }
17166
17167 void intel_connector_attach_encoder(struct intel_connector *connector,
17168 struct intel_encoder *encoder)
17169 {
17170 connector->encoder = encoder;
17171 drm_mode_connector_attach_encoder(&connector->base,
17172 &encoder->base);
17173 }
17174
17175 /*
17176 * set vga decode state - true == enable VGA decode
17177 */
17178 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
17179 {
17180 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
17181 u16 gmch_ctrl;
17182
17183 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
17184 DRM_ERROR("failed to read control word\n");
17185 return -EIO;
17186 }
17187
17188 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
17189 return 0;
17190
17191 if (state)
17192 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
17193 else
17194 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
17195
17196 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
17197 DRM_ERROR("failed to write control word\n");
17198 return -EIO;
17199 }
17200
17201 return 0;
17202 }
17203
17204 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
17205
17206 struct intel_display_error_state {
17207
17208 u32 power_well_driver;
17209
17210 int num_transcoders;
17211
17212 struct intel_cursor_error_state {
17213 u32 control;
17214 u32 position;
17215 u32 base;
17216 u32 size;
17217 } cursor[I915_MAX_PIPES];
17218
17219 struct intel_pipe_error_state {
17220 bool power_domain_on;
17221 u32 source;
17222 u32 stat;
17223 } pipe[I915_MAX_PIPES];
17224
17225 struct intel_plane_error_state {
17226 u32 control;
17227 u32 stride;
17228 u32 size;
17229 u32 pos;
17230 u32 addr;
17231 u32 surface;
17232 u32 tile_offset;
17233 } plane[I915_MAX_PIPES];
17234
17235 struct intel_transcoder_error_state {
17236 bool power_domain_on;
17237 enum transcoder cpu_transcoder;
17238
17239 u32 conf;
17240
17241 u32 htotal;
17242 u32 hblank;
17243 u32 hsync;
17244 u32 vtotal;
17245 u32 vblank;
17246 u32 vsync;
17247 } transcoder[4];
17248 };
17249
17250 struct intel_display_error_state *
17251 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
17252 {
17253 struct intel_display_error_state *error;
17254 int transcoders[] = {
17255 TRANSCODER_A,
17256 TRANSCODER_B,
17257 TRANSCODER_C,
17258 TRANSCODER_EDP,
17259 };
17260 int i;
17261
17262 if (INTEL_INFO(dev_priv)->num_pipes == 0)
17263 return NULL;
17264
17265 error = kzalloc(sizeof(*error), GFP_ATOMIC);
17266 if (error == NULL)
17267 return NULL;
17268
17269 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17270 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
17271
17272 for_each_pipe(dev_priv, i) {
17273 error->pipe[i].power_domain_on =
17274 __intel_display_power_is_enabled(dev_priv,
17275 POWER_DOMAIN_PIPE(i));
17276 if (!error->pipe[i].power_domain_on)
17277 continue;
17278
17279 error->cursor[i].control = I915_READ(CURCNTR(i));
17280 error->cursor[i].position = I915_READ(CURPOS(i));
17281 error->cursor[i].base = I915_READ(CURBASE(i));
17282
17283 error->plane[i].control = I915_READ(DSPCNTR(i));
17284 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
17285 if (INTEL_GEN(dev_priv) <= 3) {
17286 error->plane[i].size = I915_READ(DSPSIZE(i));
17287 error->plane[i].pos = I915_READ(DSPPOS(i));
17288 }
17289 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17290 error->plane[i].addr = I915_READ(DSPADDR(i));
17291 if (INTEL_GEN(dev_priv) >= 4) {
17292 error->plane[i].surface = I915_READ(DSPSURF(i));
17293 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
17294 }
17295
17296 error->pipe[i].source = I915_READ(PIPESRC(i));
17297
17298 if (HAS_GMCH_DISPLAY(dev_priv))
17299 error->pipe[i].stat = I915_READ(PIPESTAT(i));
17300 }
17301
17302 /* Note: this does not include DSI transcoders. */
17303 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
17304 if (HAS_DDI(dev_priv))
17305 error->num_transcoders++; /* Account for eDP. */
17306
17307 for (i = 0; i < error->num_transcoders; i++) {
17308 enum transcoder cpu_transcoder = transcoders[i];
17309
17310 error->transcoder[i].power_domain_on =
17311 __intel_display_power_is_enabled(dev_priv,
17312 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
17313 if (!error->transcoder[i].power_domain_on)
17314 continue;
17315
17316 error->transcoder[i].cpu_transcoder = cpu_transcoder;
17317
17318 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
17319 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
17320 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
17321 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
17322 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
17323 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
17324 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
17325 }
17326
17327 return error;
17328 }
17329
17330 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
17331
17332 void
17333 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
17334 struct drm_i915_private *dev_priv,
17335 struct intel_display_error_state *error)
17336 {
17337 int i;
17338
17339 if (!error)
17340 return;
17341
17342 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
17343 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17344 err_printf(m, "PWR_WELL_CTL2: %08x\n",
17345 error->power_well_driver);
17346 for_each_pipe(dev_priv, i) {
17347 err_printf(m, "Pipe [%d]:\n", i);
17348 err_printf(m, " Power: %s\n",
17349 onoff(error->pipe[i].power_domain_on));
17350 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
17351 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
17352
17353 err_printf(m, "Plane [%d]:\n", i);
17354 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
17355 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
17356 if (INTEL_GEN(dev_priv) <= 3) {
17357 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
17358 err_printf(m, " POS: %08x\n", error->plane[i].pos);
17359 }
17360 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17361 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
17362 if (INTEL_GEN(dev_priv) >= 4) {
17363 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
17364 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
17365 }
17366
17367 err_printf(m, "Cursor [%d]:\n", i);
17368 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
17369 err_printf(m, " POS: %08x\n", error->cursor[i].position);
17370 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
17371 }
17372
17373 for (i = 0; i < error->num_transcoders; i++) {
17374 err_printf(m, "CPU transcoder: %s\n",
17375 transcoder_name(error->transcoder[i].cpu_transcoder));
17376 err_printf(m, " Power: %s\n",
17377 onoff(error->transcoder[i].power_domain_on));
17378 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
17379 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
17380 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
17381 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
17382 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
17383 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
17384 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
17385 }
17386 }
17387
17388 #endif
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