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Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
45 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
46
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
49
50 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
52 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
53 struct intel_crtc_config *pipe_config);
54
55 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
56 int x, int y, struct drm_framebuffer *old_fb);
57 static int intel_framebuffer_init(struct drm_device *dev,
58 struct intel_framebuffer *ifb,
59 struct drm_mode_fb_cmd2 *mode_cmd,
60 struct drm_i915_gem_object *obj);
61 static void intel_dp_set_m_n(struct intel_crtc *crtc);
62 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
63 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
64 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
65 struct intel_link_m_n *m_n);
66 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
67 static void haswell_set_pipeconf(struct drm_crtc *crtc);
68 static void intel_set_pipe_csc(struct drm_crtc *crtc);
69 static void vlv_prepare_pll(struct intel_crtc *crtc);
70
71 typedef struct {
72 int min, max;
73 } intel_range_t;
74
75 typedef struct {
76 int dot_limit;
77 int p2_slow, p2_fast;
78 } intel_p2_t;
79
80 typedef struct intel_limit intel_limit_t;
81 struct intel_limit {
82 intel_range_t dot, vco, n, m, m1, m2, p, p1;
83 intel_p2_t p2;
84 };
85
86 int
87 intel_pch_rawclk(struct drm_device *dev)
88 {
89 struct drm_i915_private *dev_priv = dev->dev_private;
90
91 WARN_ON(!HAS_PCH_SPLIT(dev));
92
93 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
94 }
95
96 static inline u32 /* units of 100MHz */
97 intel_fdi_link_freq(struct drm_device *dev)
98 {
99 if (IS_GEN5(dev)) {
100 struct drm_i915_private *dev_priv = dev->dev_private;
101 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
102 } else
103 return 27;
104 }
105
106 static const intel_limit_t intel_limits_i8xx_dac = {
107 .dot = { .min = 25000, .max = 350000 },
108 .vco = { .min = 908000, .max = 1512000 },
109 .n = { .min = 2, .max = 16 },
110 .m = { .min = 96, .max = 140 },
111 .m1 = { .min = 18, .max = 26 },
112 .m2 = { .min = 6, .max = 16 },
113 .p = { .min = 4, .max = 128 },
114 .p1 = { .min = 2, .max = 33 },
115 .p2 = { .dot_limit = 165000,
116 .p2_slow = 4, .p2_fast = 2 },
117 };
118
119 static const intel_limit_t intel_limits_i8xx_dvo = {
120 .dot = { .min = 25000, .max = 350000 },
121 .vco = { .min = 908000, .max = 1512000 },
122 .n = { .min = 2, .max = 16 },
123 .m = { .min = 96, .max = 140 },
124 .m1 = { .min = 18, .max = 26 },
125 .m2 = { .min = 6, .max = 16 },
126 .p = { .min = 4, .max = 128 },
127 .p1 = { .min = 2, .max = 33 },
128 .p2 = { .dot_limit = 165000,
129 .p2_slow = 4, .p2_fast = 4 },
130 };
131
132 static const intel_limit_t intel_limits_i8xx_lvds = {
133 .dot = { .min = 25000, .max = 350000 },
134 .vco = { .min = 908000, .max = 1512000 },
135 .n = { .min = 2, .max = 16 },
136 .m = { .min = 96, .max = 140 },
137 .m1 = { .min = 18, .max = 26 },
138 .m2 = { .min = 6, .max = 16 },
139 .p = { .min = 4, .max = 128 },
140 .p1 = { .min = 1, .max = 6 },
141 .p2 = { .dot_limit = 165000,
142 .p2_slow = 14, .p2_fast = 7 },
143 };
144
145 static const intel_limit_t intel_limits_i9xx_sdvo = {
146 .dot = { .min = 20000, .max = 400000 },
147 .vco = { .min = 1400000, .max = 2800000 },
148 .n = { .min = 1, .max = 6 },
149 .m = { .min = 70, .max = 120 },
150 .m1 = { .min = 8, .max = 18 },
151 .m2 = { .min = 3, .max = 7 },
152 .p = { .min = 5, .max = 80 },
153 .p1 = { .min = 1, .max = 8 },
154 .p2 = { .dot_limit = 200000,
155 .p2_slow = 10, .p2_fast = 5 },
156 };
157
158 static const intel_limit_t intel_limits_i9xx_lvds = {
159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 8, .max = 18 },
164 .m2 = { .min = 3, .max = 7 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
169 };
170
171
172 static const intel_limit_t intel_limits_g4x_sdvo = {
173 .dot = { .min = 25000, .max = 270000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 17, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 10, .max = 30 },
180 .p1 = { .min = 1, .max = 3},
181 .p2 = { .dot_limit = 270000,
182 .p2_slow = 10,
183 .p2_fast = 10
184 },
185 };
186
187 static const intel_limit_t intel_limits_g4x_hdmi = {
188 .dot = { .min = 22000, .max = 400000 },
189 .vco = { .min = 1750000, .max = 3500000},
190 .n = { .min = 1, .max = 4 },
191 .m = { .min = 104, .max = 138 },
192 .m1 = { .min = 16, .max = 23 },
193 .m2 = { .min = 5, .max = 11 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8},
196 .p2 = { .dot_limit = 165000,
197 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
201 .dot = { .min = 20000, .max = 115000 },
202 .vco = { .min = 1750000, .max = 3500000 },
203 .n = { .min = 1, .max = 3 },
204 .m = { .min = 104, .max = 138 },
205 .m1 = { .min = 17, .max = 23 },
206 .m2 = { .min = 5, .max = 11 },
207 .p = { .min = 28, .max = 112 },
208 .p1 = { .min = 2, .max = 8 },
209 .p2 = { .dot_limit = 0,
210 .p2_slow = 14, .p2_fast = 14
211 },
212 };
213
214 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
215 .dot = { .min = 80000, .max = 224000 },
216 .vco = { .min = 1750000, .max = 3500000 },
217 .n = { .min = 1, .max = 3 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 14, .max = 42 },
222 .p1 = { .min = 2, .max = 6 },
223 .p2 = { .dot_limit = 0,
224 .p2_slow = 7, .p2_fast = 7
225 },
226 };
227
228 static const intel_limit_t intel_limits_pineview_sdvo = {
229 .dot = { .min = 20000, .max = 400000},
230 .vco = { .min = 1700000, .max = 3500000 },
231 /* Pineview's Ncounter is a ring counter */
232 .n = { .min = 3, .max = 6 },
233 .m = { .min = 2, .max = 256 },
234 /* Pineview only has one combined m divider, which we treat as m2. */
235 .m1 = { .min = 0, .max = 0 },
236 .m2 = { .min = 0, .max = 254 },
237 .p = { .min = 5, .max = 80 },
238 .p1 = { .min = 1, .max = 8 },
239 .p2 = { .dot_limit = 200000,
240 .p2_slow = 10, .p2_fast = 5 },
241 };
242
243 static const intel_limit_t intel_limits_pineview_lvds = {
244 .dot = { .min = 20000, .max = 400000 },
245 .vco = { .min = 1700000, .max = 3500000 },
246 .n = { .min = 3, .max = 6 },
247 .m = { .min = 2, .max = 256 },
248 .m1 = { .min = 0, .max = 0 },
249 .m2 = { .min = 0, .max = 254 },
250 .p = { .min = 7, .max = 112 },
251 .p1 = { .min = 1, .max = 8 },
252 .p2 = { .dot_limit = 112000,
253 .p2_slow = 14, .p2_fast = 14 },
254 };
255
256 /* Ironlake / Sandybridge
257 *
258 * We calculate clock using (register_value + 2) for N/M1/M2, so here
259 * the range value for them is (actual_value - 2).
260 */
261 static const intel_limit_t intel_limits_ironlake_dac = {
262 .dot = { .min = 25000, .max = 350000 },
263 .vco = { .min = 1760000, .max = 3510000 },
264 .n = { .min = 1, .max = 5 },
265 .m = { .min = 79, .max = 127 },
266 .m1 = { .min = 12, .max = 22 },
267 .m2 = { .min = 5, .max = 9 },
268 .p = { .min = 5, .max = 80 },
269 .p1 = { .min = 1, .max = 8 },
270 .p2 = { .dot_limit = 225000,
271 .p2_slow = 10, .p2_fast = 5 },
272 };
273
274 static const intel_limit_t intel_limits_ironlake_single_lvds = {
275 .dot = { .min = 25000, .max = 350000 },
276 .vco = { .min = 1760000, .max = 3510000 },
277 .n = { .min = 1, .max = 3 },
278 .m = { .min = 79, .max = 118 },
279 .m1 = { .min = 12, .max = 22 },
280 .m2 = { .min = 5, .max = 9 },
281 .p = { .min = 28, .max = 112 },
282 .p1 = { .min = 2, .max = 8 },
283 .p2 = { .dot_limit = 225000,
284 .p2_slow = 14, .p2_fast = 14 },
285 };
286
287 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 3 },
291 .m = { .min = 79, .max = 127 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 14, .max = 56 },
295 .p1 = { .min = 2, .max = 8 },
296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 7, .p2_fast = 7 },
298 };
299
300 /* LVDS 100mhz refclk limits. */
301 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
302 .dot = { .min = 25000, .max = 350000 },
303 .vco = { .min = 1760000, .max = 3510000 },
304 .n = { .min = 1, .max = 2 },
305 .m = { .min = 79, .max = 126 },
306 .m1 = { .min = 12, .max = 22 },
307 .m2 = { .min = 5, .max = 9 },
308 .p = { .min = 28, .max = 112 },
309 .p1 = { .min = 2, .max = 8 },
310 .p2 = { .dot_limit = 225000,
311 .p2_slow = 14, .p2_fast = 14 },
312 };
313
314 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 3 },
318 .m = { .min = 79, .max = 126 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 14, .max = 42 },
322 .p1 = { .min = 2, .max = 6 },
323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 7, .p2_fast = 7 },
325 };
326
327 static const intel_limit_t intel_limits_vlv = {
328 /*
329 * These are the data rate limits (measured in fast clocks)
330 * since those are the strictest limits we have. The fast
331 * clock and actual rate limits are more relaxed, so checking
332 * them would make no difference.
333 */
334 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
335 .vco = { .min = 4000000, .max = 6000000 },
336 .n = { .min = 1, .max = 7 },
337 .m1 = { .min = 2, .max = 3 },
338 .m2 = { .min = 11, .max = 156 },
339 .p1 = { .min = 2, .max = 3 },
340 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
341 };
342
343 static const intel_limit_t intel_limits_chv = {
344 /*
345 * These are the data rate limits (measured in fast clocks)
346 * since those are the strictest limits we have. The fast
347 * clock and actual rate limits are more relaxed, so checking
348 * them would make no difference.
349 */
350 .dot = { .min = 25000 * 5, .max = 540000 * 5},
351 .vco = { .min = 4860000, .max = 6700000 },
352 .n = { .min = 1, .max = 1 },
353 .m1 = { .min = 2, .max = 2 },
354 .m2 = { .min = 24 << 22, .max = 175 << 22 },
355 .p1 = { .min = 2, .max = 4 },
356 .p2 = { .p2_slow = 1, .p2_fast = 14 },
357 };
358
359 static void vlv_clock(int refclk, intel_clock_t *clock)
360 {
361 clock->m = clock->m1 * clock->m2;
362 clock->p = clock->p1 * clock->p2;
363 if (WARN_ON(clock->n == 0 || clock->p == 0))
364 return;
365 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
366 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
367 }
368
369 /**
370 * Returns whether any output on the specified pipe is of the specified type
371 */
372 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
373 {
374 struct drm_device *dev = crtc->dev;
375 struct intel_encoder *encoder;
376
377 for_each_encoder_on_crtc(dev, crtc, encoder)
378 if (encoder->type == type)
379 return true;
380
381 return false;
382 }
383
384 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
385 int refclk)
386 {
387 struct drm_device *dev = crtc->dev;
388 const intel_limit_t *limit;
389
390 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
391 if (intel_is_dual_link_lvds(dev)) {
392 if (refclk == 100000)
393 limit = &intel_limits_ironlake_dual_lvds_100m;
394 else
395 limit = &intel_limits_ironlake_dual_lvds;
396 } else {
397 if (refclk == 100000)
398 limit = &intel_limits_ironlake_single_lvds_100m;
399 else
400 limit = &intel_limits_ironlake_single_lvds;
401 }
402 } else
403 limit = &intel_limits_ironlake_dac;
404
405 return limit;
406 }
407
408 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
409 {
410 struct drm_device *dev = crtc->dev;
411 const intel_limit_t *limit;
412
413 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
414 if (intel_is_dual_link_lvds(dev))
415 limit = &intel_limits_g4x_dual_channel_lvds;
416 else
417 limit = &intel_limits_g4x_single_channel_lvds;
418 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
419 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
420 limit = &intel_limits_g4x_hdmi;
421 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
422 limit = &intel_limits_g4x_sdvo;
423 } else /* The option is for other outputs */
424 limit = &intel_limits_i9xx_sdvo;
425
426 return limit;
427 }
428
429 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
430 {
431 struct drm_device *dev = crtc->dev;
432 const intel_limit_t *limit;
433
434 if (HAS_PCH_SPLIT(dev))
435 limit = intel_ironlake_limit(crtc, refclk);
436 else if (IS_G4X(dev)) {
437 limit = intel_g4x_limit(crtc);
438 } else if (IS_PINEVIEW(dev)) {
439 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
440 limit = &intel_limits_pineview_lvds;
441 else
442 limit = &intel_limits_pineview_sdvo;
443 } else if (IS_CHERRYVIEW(dev)) {
444 limit = &intel_limits_chv;
445 } else if (IS_VALLEYVIEW(dev)) {
446 limit = &intel_limits_vlv;
447 } else if (!IS_GEN2(dev)) {
448 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
449 limit = &intel_limits_i9xx_lvds;
450 else
451 limit = &intel_limits_i9xx_sdvo;
452 } else {
453 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
454 limit = &intel_limits_i8xx_lvds;
455 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
456 limit = &intel_limits_i8xx_dvo;
457 else
458 limit = &intel_limits_i8xx_dac;
459 }
460 return limit;
461 }
462
463 /* m1 is reserved as 0 in Pineview, n is a ring counter */
464 static void pineview_clock(int refclk, intel_clock_t *clock)
465 {
466 clock->m = clock->m2 + 2;
467 clock->p = clock->p1 * clock->p2;
468 if (WARN_ON(clock->n == 0 || clock->p == 0))
469 return;
470 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
471 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
472 }
473
474 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
475 {
476 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
477 }
478
479 static void i9xx_clock(int refclk, intel_clock_t *clock)
480 {
481 clock->m = i9xx_dpll_compute_m(clock);
482 clock->p = clock->p1 * clock->p2;
483 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
484 return;
485 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
486 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
487 }
488
489 static void chv_clock(int refclk, intel_clock_t *clock)
490 {
491 clock->m = clock->m1 * clock->m2;
492 clock->p = clock->p1 * clock->p2;
493 if (WARN_ON(clock->n == 0 || clock->p == 0))
494 return;
495 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
496 clock->n << 22);
497 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
498 }
499
500 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
501 /**
502 * Returns whether the given set of divisors are valid for a given refclk with
503 * the given connectors.
504 */
505
506 static bool intel_PLL_is_valid(struct drm_device *dev,
507 const intel_limit_t *limit,
508 const intel_clock_t *clock)
509 {
510 if (clock->n < limit->n.min || limit->n.max < clock->n)
511 INTELPllInvalid("n out of range\n");
512 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
513 INTELPllInvalid("p1 out of range\n");
514 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
515 INTELPllInvalid("m2 out of range\n");
516 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
517 INTELPllInvalid("m1 out of range\n");
518
519 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
520 if (clock->m1 <= clock->m2)
521 INTELPllInvalid("m1 <= m2\n");
522
523 if (!IS_VALLEYVIEW(dev)) {
524 if (clock->p < limit->p.min || limit->p.max < clock->p)
525 INTELPllInvalid("p out of range\n");
526 if (clock->m < limit->m.min || limit->m.max < clock->m)
527 INTELPllInvalid("m out of range\n");
528 }
529
530 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
531 INTELPllInvalid("vco out of range\n");
532 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
533 * connector, etc., rather than just a single range.
534 */
535 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
536 INTELPllInvalid("dot out of range\n");
537
538 return true;
539 }
540
541 static bool
542 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
543 int target, int refclk, intel_clock_t *match_clock,
544 intel_clock_t *best_clock)
545 {
546 struct drm_device *dev = crtc->dev;
547 intel_clock_t clock;
548 int err = target;
549
550 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
551 /*
552 * For LVDS just rely on its current settings for dual-channel.
553 * We haven't figured out how to reliably set up different
554 * single/dual channel state, if we even can.
555 */
556 if (intel_is_dual_link_lvds(dev))
557 clock.p2 = limit->p2.p2_fast;
558 else
559 clock.p2 = limit->p2.p2_slow;
560 } else {
561 if (target < limit->p2.dot_limit)
562 clock.p2 = limit->p2.p2_slow;
563 else
564 clock.p2 = limit->p2.p2_fast;
565 }
566
567 memset(best_clock, 0, sizeof(*best_clock));
568
569 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
570 clock.m1++) {
571 for (clock.m2 = limit->m2.min;
572 clock.m2 <= limit->m2.max; clock.m2++) {
573 if (clock.m2 >= clock.m1)
574 break;
575 for (clock.n = limit->n.min;
576 clock.n <= limit->n.max; clock.n++) {
577 for (clock.p1 = limit->p1.min;
578 clock.p1 <= limit->p1.max; clock.p1++) {
579 int this_err;
580
581 i9xx_clock(refclk, &clock);
582 if (!intel_PLL_is_valid(dev, limit,
583 &clock))
584 continue;
585 if (match_clock &&
586 clock.p != match_clock->p)
587 continue;
588
589 this_err = abs(clock.dot - target);
590 if (this_err < err) {
591 *best_clock = clock;
592 err = this_err;
593 }
594 }
595 }
596 }
597 }
598
599 return (err != target);
600 }
601
602 static bool
603 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
604 int target, int refclk, intel_clock_t *match_clock,
605 intel_clock_t *best_clock)
606 {
607 struct drm_device *dev = crtc->dev;
608 intel_clock_t clock;
609 int err = target;
610
611 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
612 /*
613 * For LVDS just rely on its current settings for dual-channel.
614 * We haven't figured out how to reliably set up different
615 * single/dual channel state, if we even can.
616 */
617 if (intel_is_dual_link_lvds(dev))
618 clock.p2 = limit->p2.p2_fast;
619 else
620 clock.p2 = limit->p2.p2_slow;
621 } else {
622 if (target < limit->p2.dot_limit)
623 clock.p2 = limit->p2.p2_slow;
624 else
625 clock.p2 = limit->p2.p2_fast;
626 }
627
628 memset(best_clock, 0, sizeof(*best_clock));
629
630 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
631 clock.m1++) {
632 for (clock.m2 = limit->m2.min;
633 clock.m2 <= limit->m2.max; clock.m2++) {
634 for (clock.n = limit->n.min;
635 clock.n <= limit->n.max; clock.n++) {
636 for (clock.p1 = limit->p1.min;
637 clock.p1 <= limit->p1.max; clock.p1++) {
638 int this_err;
639
640 pineview_clock(refclk, &clock);
641 if (!intel_PLL_is_valid(dev, limit,
642 &clock))
643 continue;
644 if (match_clock &&
645 clock.p != match_clock->p)
646 continue;
647
648 this_err = abs(clock.dot - target);
649 if (this_err < err) {
650 *best_clock = clock;
651 err = this_err;
652 }
653 }
654 }
655 }
656 }
657
658 return (err != target);
659 }
660
661 static bool
662 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
663 int target, int refclk, intel_clock_t *match_clock,
664 intel_clock_t *best_clock)
665 {
666 struct drm_device *dev = crtc->dev;
667 intel_clock_t clock;
668 int max_n;
669 bool found;
670 /* approximately equals target * 0.00585 */
671 int err_most = (target >> 8) + (target >> 9);
672 found = false;
673
674 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
675 if (intel_is_dual_link_lvds(dev))
676 clock.p2 = limit->p2.p2_fast;
677 else
678 clock.p2 = limit->p2.p2_slow;
679 } else {
680 if (target < limit->p2.dot_limit)
681 clock.p2 = limit->p2.p2_slow;
682 else
683 clock.p2 = limit->p2.p2_fast;
684 }
685
686 memset(best_clock, 0, sizeof(*best_clock));
687 max_n = limit->n.max;
688 /* based on hardware requirement, prefer smaller n to precision */
689 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
690 /* based on hardware requirement, prefere larger m1,m2 */
691 for (clock.m1 = limit->m1.max;
692 clock.m1 >= limit->m1.min; clock.m1--) {
693 for (clock.m2 = limit->m2.max;
694 clock.m2 >= limit->m2.min; clock.m2--) {
695 for (clock.p1 = limit->p1.max;
696 clock.p1 >= limit->p1.min; clock.p1--) {
697 int this_err;
698
699 i9xx_clock(refclk, &clock);
700 if (!intel_PLL_is_valid(dev, limit,
701 &clock))
702 continue;
703
704 this_err = abs(clock.dot - target);
705 if (this_err < err_most) {
706 *best_clock = clock;
707 err_most = this_err;
708 max_n = clock.n;
709 found = true;
710 }
711 }
712 }
713 }
714 }
715 return found;
716 }
717
718 static bool
719 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
720 int target, int refclk, intel_clock_t *match_clock,
721 intel_clock_t *best_clock)
722 {
723 struct drm_device *dev = crtc->dev;
724 intel_clock_t clock;
725 unsigned int bestppm = 1000000;
726 /* min update 19.2 MHz */
727 int max_n = min(limit->n.max, refclk / 19200);
728 bool found = false;
729
730 target *= 5; /* fast clock */
731
732 memset(best_clock, 0, sizeof(*best_clock));
733
734 /* based on hardware requirement, prefer smaller n to precision */
735 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
736 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
737 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
738 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
739 clock.p = clock.p1 * clock.p2;
740 /* based on hardware requirement, prefer bigger m1,m2 values */
741 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
742 unsigned int ppm, diff;
743
744 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
745 refclk * clock.m1);
746
747 vlv_clock(refclk, &clock);
748
749 if (!intel_PLL_is_valid(dev, limit,
750 &clock))
751 continue;
752
753 diff = abs(clock.dot - target);
754 ppm = div_u64(1000000ULL * diff, target);
755
756 if (ppm < 100 && clock.p > best_clock->p) {
757 bestppm = 0;
758 *best_clock = clock;
759 found = true;
760 }
761
762 if (bestppm >= 10 && ppm < bestppm - 10) {
763 bestppm = ppm;
764 *best_clock = clock;
765 found = true;
766 }
767 }
768 }
769 }
770 }
771
772 return found;
773 }
774
775 static bool
776 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
777 int target, int refclk, intel_clock_t *match_clock,
778 intel_clock_t *best_clock)
779 {
780 struct drm_device *dev = crtc->dev;
781 intel_clock_t clock;
782 uint64_t m2;
783 int found = false;
784
785 memset(best_clock, 0, sizeof(*best_clock));
786
787 /*
788 * Based on hardware doc, the n always set to 1, and m1 always
789 * set to 2. If requires to support 200Mhz refclk, we need to
790 * revisit this because n may not 1 anymore.
791 */
792 clock.n = 1, clock.m1 = 2;
793 target *= 5; /* fast clock */
794
795 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
796 for (clock.p2 = limit->p2.p2_fast;
797 clock.p2 >= limit->p2.p2_slow;
798 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
799
800 clock.p = clock.p1 * clock.p2;
801
802 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
803 clock.n) << 22, refclk * clock.m1);
804
805 if (m2 > INT_MAX/clock.m1)
806 continue;
807
808 clock.m2 = m2;
809
810 chv_clock(refclk, &clock);
811
812 if (!intel_PLL_is_valid(dev, limit, &clock))
813 continue;
814
815 /* based on hardware requirement, prefer bigger p
816 */
817 if (clock.p > best_clock->p) {
818 *best_clock = clock;
819 found = true;
820 }
821 }
822 }
823
824 return found;
825 }
826
827 bool intel_crtc_active(struct drm_crtc *crtc)
828 {
829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
830
831 /* Be paranoid as we can arrive here with only partial
832 * state retrieved from the hardware during setup.
833 *
834 * We can ditch the adjusted_mode.crtc_clock check as soon
835 * as Haswell has gained clock readout/fastboot support.
836 *
837 * We can ditch the crtc->primary->fb check as soon as we can
838 * properly reconstruct framebuffers.
839 */
840 return intel_crtc->active && crtc->primary->fb &&
841 intel_crtc->config.adjusted_mode.crtc_clock;
842 }
843
844 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
845 enum pipe pipe)
846 {
847 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
849
850 return intel_crtc->config.cpu_transcoder;
851 }
852
853 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
854 {
855 struct drm_i915_private *dev_priv = dev->dev_private;
856 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
857
858 frame = I915_READ(frame_reg);
859
860 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
861 WARN(1, "vblank wait timed out\n");
862 }
863
864 /**
865 * intel_wait_for_vblank - wait for vblank on a given pipe
866 * @dev: drm device
867 * @pipe: pipe to wait for
868 *
869 * Wait for vblank to occur on a given pipe. Needed for various bits of
870 * mode setting code.
871 */
872 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
873 {
874 struct drm_i915_private *dev_priv = dev->dev_private;
875 int pipestat_reg = PIPESTAT(pipe);
876
877 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
878 g4x_wait_for_vblank(dev, pipe);
879 return;
880 }
881
882 /* Clear existing vblank status. Note this will clear any other
883 * sticky status fields as well.
884 *
885 * This races with i915_driver_irq_handler() with the result
886 * that either function could miss a vblank event. Here it is not
887 * fatal, as we will either wait upon the next vblank interrupt or
888 * timeout. Generally speaking intel_wait_for_vblank() is only
889 * called during modeset at which time the GPU should be idle and
890 * should *not* be performing page flips and thus not waiting on
891 * vblanks...
892 * Currently, the result of us stealing a vblank from the irq
893 * handler is that a single frame will be skipped during swapbuffers.
894 */
895 I915_WRITE(pipestat_reg,
896 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
897
898 /* Wait for vblank interrupt bit to set */
899 if (wait_for(I915_READ(pipestat_reg) &
900 PIPE_VBLANK_INTERRUPT_STATUS,
901 50))
902 DRM_DEBUG_KMS("vblank wait timed out\n");
903 }
904
905 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
906 {
907 struct drm_i915_private *dev_priv = dev->dev_private;
908 u32 reg = PIPEDSL(pipe);
909 u32 line1, line2;
910 u32 line_mask;
911
912 if (IS_GEN2(dev))
913 line_mask = DSL_LINEMASK_GEN2;
914 else
915 line_mask = DSL_LINEMASK_GEN3;
916
917 line1 = I915_READ(reg) & line_mask;
918 mdelay(5);
919 line2 = I915_READ(reg) & line_mask;
920
921 return line1 == line2;
922 }
923
924 /*
925 * intel_wait_for_pipe_off - wait for pipe to turn off
926 * @dev: drm device
927 * @pipe: pipe to wait for
928 *
929 * After disabling a pipe, we can't wait for vblank in the usual way,
930 * spinning on the vblank interrupt status bit, since we won't actually
931 * see an interrupt when the pipe is disabled.
932 *
933 * On Gen4 and above:
934 * wait for the pipe register state bit to turn off
935 *
936 * Otherwise:
937 * wait for the display line value to settle (it usually
938 * ends up stopping at the start of the next frame).
939 *
940 */
941 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
942 {
943 struct drm_i915_private *dev_priv = dev->dev_private;
944 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
945 pipe);
946
947 if (INTEL_INFO(dev)->gen >= 4) {
948 int reg = PIPECONF(cpu_transcoder);
949
950 /* Wait for the Pipe State to go off */
951 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
952 100))
953 WARN(1, "pipe_off wait timed out\n");
954 } else {
955 /* Wait for the display line to settle */
956 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
957 WARN(1, "pipe_off wait timed out\n");
958 }
959 }
960
961 /*
962 * ibx_digital_port_connected - is the specified port connected?
963 * @dev_priv: i915 private structure
964 * @port: the port to test
965 *
966 * Returns true if @port is connected, false otherwise.
967 */
968 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
969 struct intel_digital_port *port)
970 {
971 u32 bit;
972
973 if (HAS_PCH_IBX(dev_priv->dev)) {
974 switch (port->port) {
975 case PORT_B:
976 bit = SDE_PORTB_HOTPLUG;
977 break;
978 case PORT_C:
979 bit = SDE_PORTC_HOTPLUG;
980 break;
981 case PORT_D:
982 bit = SDE_PORTD_HOTPLUG;
983 break;
984 default:
985 return true;
986 }
987 } else {
988 switch (port->port) {
989 case PORT_B:
990 bit = SDE_PORTB_HOTPLUG_CPT;
991 break;
992 case PORT_C:
993 bit = SDE_PORTC_HOTPLUG_CPT;
994 break;
995 case PORT_D:
996 bit = SDE_PORTD_HOTPLUG_CPT;
997 break;
998 default:
999 return true;
1000 }
1001 }
1002
1003 return I915_READ(SDEISR) & bit;
1004 }
1005
1006 static const char *state_string(bool enabled)
1007 {
1008 return enabled ? "on" : "off";
1009 }
1010
1011 /* Only for pre-ILK configs */
1012 void assert_pll(struct drm_i915_private *dev_priv,
1013 enum pipe pipe, bool state)
1014 {
1015 int reg;
1016 u32 val;
1017 bool cur_state;
1018
1019 reg = DPLL(pipe);
1020 val = I915_READ(reg);
1021 cur_state = !!(val & DPLL_VCO_ENABLE);
1022 WARN(cur_state != state,
1023 "PLL state assertion failure (expected %s, current %s)\n",
1024 state_string(state), state_string(cur_state));
1025 }
1026
1027 /* XXX: the dsi pll is shared between MIPI DSI ports */
1028 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1029 {
1030 u32 val;
1031 bool cur_state;
1032
1033 mutex_lock(&dev_priv->dpio_lock);
1034 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1035 mutex_unlock(&dev_priv->dpio_lock);
1036
1037 cur_state = val & DSI_PLL_VCO_EN;
1038 WARN(cur_state != state,
1039 "DSI PLL state assertion failure (expected %s, current %s)\n",
1040 state_string(state), state_string(cur_state));
1041 }
1042 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1043 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1044
1045 struct intel_shared_dpll *
1046 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1047 {
1048 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1049
1050 if (crtc->config.shared_dpll < 0)
1051 return NULL;
1052
1053 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1054 }
1055
1056 /* For ILK+ */
1057 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1058 struct intel_shared_dpll *pll,
1059 bool state)
1060 {
1061 bool cur_state;
1062 struct intel_dpll_hw_state hw_state;
1063
1064 if (HAS_PCH_LPT(dev_priv->dev)) {
1065 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1066 return;
1067 }
1068
1069 if (WARN (!pll,
1070 "asserting DPLL %s with no DPLL\n", state_string(state)))
1071 return;
1072
1073 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1074 WARN(cur_state != state,
1075 "%s assertion failure (expected %s, current %s)\n",
1076 pll->name, state_string(state), state_string(cur_state));
1077 }
1078
1079 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080 enum pipe pipe, bool state)
1081 {
1082 int reg;
1083 u32 val;
1084 bool cur_state;
1085 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086 pipe);
1087
1088 if (HAS_DDI(dev_priv->dev)) {
1089 /* DDI does not have a specific FDI_TX register */
1090 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1091 val = I915_READ(reg);
1092 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1093 } else {
1094 reg = FDI_TX_CTL(pipe);
1095 val = I915_READ(reg);
1096 cur_state = !!(val & FDI_TX_ENABLE);
1097 }
1098 WARN(cur_state != state,
1099 "FDI TX state assertion failure (expected %s, current %s)\n",
1100 state_string(state), state_string(cur_state));
1101 }
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106 enum pipe pipe, bool state)
1107 {
1108 int reg;
1109 u32 val;
1110 bool cur_state;
1111
1112 reg = FDI_RX_CTL(pipe);
1113 val = I915_READ(reg);
1114 cur_state = !!(val & FDI_RX_ENABLE);
1115 WARN(cur_state != state,
1116 "FDI RX state assertion failure (expected %s, current %s)\n",
1117 state_string(state), state_string(cur_state));
1118 }
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123 enum pipe pipe)
1124 {
1125 int reg;
1126 u32 val;
1127
1128 /* ILK FDI PLL is always enabled */
1129 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1130 return;
1131
1132 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133 if (HAS_DDI(dev_priv->dev))
1134 return;
1135
1136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139 }
1140
1141 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1143 {
1144 int reg;
1145 u32 val;
1146 bool cur_state;
1147
1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151 WARN(cur_state != state,
1152 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154 }
1155
1156 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157 enum pipe pipe)
1158 {
1159 int pp_reg, lvds_reg;
1160 u32 val;
1161 enum pipe panel_pipe = PIPE_A;
1162 bool locked = true;
1163
1164 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1165 pp_reg = PCH_PP_CONTROL;
1166 lvds_reg = PCH_LVDS;
1167 } else {
1168 pp_reg = PP_CONTROL;
1169 lvds_reg = LVDS;
1170 }
1171
1172 val = I915_READ(pp_reg);
1173 if (!(val & PANEL_POWER_ON) ||
1174 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1175 locked = false;
1176
1177 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1178 panel_pipe = PIPE_B;
1179
1180 WARN(panel_pipe == pipe && locked,
1181 "panel assertion failure, pipe %c regs locked\n",
1182 pipe_name(pipe));
1183 }
1184
1185 static void assert_cursor(struct drm_i915_private *dev_priv,
1186 enum pipe pipe, bool state)
1187 {
1188 struct drm_device *dev = dev_priv->dev;
1189 bool cur_state;
1190
1191 if (IS_845G(dev) || IS_I865G(dev))
1192 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1193 else
1194 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1195
1196 WARN(cur_state != state,
1197 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1198 pipe_name(pipe), state_string(state), state_string(cur_state));
1199 }
1200 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1201 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1202
1203 void assert_pipe(struct drm_i915_private *dev_priv,
1204 enum pipe pipe, bool state)
1205 {
1206 int reg;
1207 u32 val;
1208 bool cur_state;
1209 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1210 pipe);
1211
1212 /* if we need the pipe A quirk it must be always on */
1213 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1214 state = true;
1215
1216 if (!intel_display_power_enabled(dev_priv,
1217 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1218 cur_state = false;
1219 } else {
1220 reg = PIPECONF(cpu_transcoder);
1221 val = I915_READ(reg);
1222 cur_state = !!(val & PIPECONF_ENABLE);
1223 }
1224
1225 WARN(cur_state != state,
1226 "pipe %c assertion failure (expected %s, current %s)\n",
1227 pipe_name(pipe), state_string(state), state_string(cur_state));
1228 }
1229
1230 static void assert_plane(struct drm_i915_private *dev_priv,
1231 enum plane plane, bool state)
1232 {
1233 int reg;
1234 u32 val;
1235 bool cur_state;
1236
1237 reg = DSPCNTR(plane);
1238 val = I915_READ(reg);
1239 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1240 WARN(cur_state != state,
1241 "plane %c assertion failure (expected %s, current %s)\n",
1242 plane_name(plane), state_string(state), state_string(cur_state));
1243 }
1244
1245 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1246 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1247
1248 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1249 enum pipe pipe)
1250 {
1251 struct drm_device *dev = dev_priv->dev;
1252 int reg, i;
1253 u32 val;
1254 int cur_pipe;
1255
1256 /* Primary planes are fixed to pipes on gen4+ */
1257 if (INTEL_INFO(dev)->gen >= 4) {
1258 reg = DSPCNTR(pipe);
1259 val = I915_READ(reg);
1260 WARN(val & DISPLAY_PLANE_ENABLE,
1261 "plane %c assertion failure, should be disabled but not\n",
1262 plane_name(pipe));
1263 return;
1264 }
1265
1266 /* Need to check both planes against the pipe */
1267 for_each_pipe(i) {
1268 reg = DSPCNTR(i);
1269 val = I915_READ(reg);
1270 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1271 DISPPLANE_SEL_PIPE_SHIFT;
1272 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1273 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1274 plane_name(i), pipe_name(pipe));
1275 }
1276 }
1277
1278 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1279 enum pipe pipe)
1280 {
1281 struct drm_device *dev = dev_priv->dev;
1282 int reg, sprite;
1283 u32 val;
1284
1285 if (IS_VALLEYVIEW(dev)) {
1286 for_each_sprite(pipe, sprite) {
1287 reg = SPCNTR(pipe, sprite);
1288 val = I915_READ(reg);
1289 WARN(val & SP_ENABLE,
1290 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1291 sprite_name(pipe, sprite), pipe_name(pipe));
1292 }
1293 } else if (INTEL_INFO(dev)->gen >= 7) {
1294 reg = SPRCTL(pipe);
1295 val = I915_READ(reg);
1296 WARN(val & SPRITE_ENABLE,
1297 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1298 plane_name(pipe), pipe_name(pipe));
1299 } else if (INTEL_INFO(dev)->gen >= 5) {
1300 reg = DVSCNTR(pipe);
1301 val = I915_READ(reg);
1302 WARN(val & DVS_ENABLE,
1303 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1304 plane_name(pipe), pipe_name(pipe));
1305 }
1306 }
1307
1308 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1309 {
1310 u32 val;
1311 bool enabled;
1312
1313 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1314
1315 val = I915_READ(PCH_DREF_CONTROL);
1316 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1317 DREF_SUPERSPREAD_SOURCE_MASK));
1318 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1319 }
1320
1321 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1322 enum pipe pipe)
1323 {
1324 int reg;
1325 u32 val;
1326 bool enabled;
1327
1328 reg = PCH_TRANSCONF(pipe);
1329 val = I915_READ(reg);
1330 enabled = !!(val & TRANS_ENABLE);
1331 WARN(enabled,
1332 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1333 pipe_name(pipe));
1334 }
1335
1336 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1337 enum pipe pipe, u32 port_sel, u32 val)
1338 {
1339 if ((val & DP_PORT_EN) == 0)
1340 return false;
1341
1342 if (HAS_PCH_CPT(dev_priv->dev)) {
1343 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1344 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1345 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1346 return false;
1347 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1348 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1349 return false;
1350 } else {
1351 if ((val & DP_PIPE_MASK) != (pipe << 30))
1352 return false;
1353 }
1354 return true;
1355 }
1356
1357 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1358 enum pipe pipe, u32 val)
1359 {
1360 if ((val & SDVO_ENABLE) == 0)
1361 return false;
1362
1363 if (HAS_PCH_CPT(dev_priv->dev)) {
1364 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1365 return false;
1366 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1367 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1368 return false;
1369 } else {
1370 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1371 return false;
1372 }
1373 return true;
1374 }
1375
1376 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1377 enum pipe pipe, u32 val)
1378 {
1379 if ((val & LVDS_PORT_EN) == 0)
1380 return false;
1381
1382 if (HAS_PCH_CPT(dev_priv->dev)) {
1383 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1384 return false;
1385 } else {
1386 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1387 return false;
1388 }
1389 return true;
1390 }
1391
1392 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1393 enum pipe pipe, u32 val)
1394 {
1395 if ((val & ADPA_DAC_ENABLE) == 0)
1396 return false;
1397 if (HAS_PCH_CPT(dev_priv->dev)) {
1398 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1399 return false;
1400 } else {
1401 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1402 return false;
1403 }
1404 return true;
1405 }
1406
1407 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1408 enum pipe pipe, int reg, u32 port_sel)
1409 {
1410 u32 val = I915_READ(reg);
1411 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1412 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1413 reg, pipe_name(pipe));
1414
1415 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1416 && (val & DP_PIPEB_SELECT),
1417 "IBX PCH dp port still using transcoder B\n");
1418 }
1419
1420 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1421 enum pipe pipe, int reg)
1422 {
1423 u32 val = I915_READ(reg);
1424 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1425 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1426 reg, pipe_name(pipe));
1427
1428 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1429 && (val & SDVO_PIPE_B_SELECT),
1430 "IBX PCH hdmi port still using transcoder B\n");
1431 }
1432
1433 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1434 enum pipe pipe)
1435 {
1436 int reg;
1437 u32 val;
1438
1439 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1440 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1441 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1442
1443 reg = PCH_ADPA;
1444 val = I915_READ(reg);
1445 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1446 "PCH VGA enabled on transcoder %c, should be disabled\n",
1447 pipe_name(pipe));
1448
1449 reg = PCH_LVDS;
1450 val = I915_READ(reg);
1451 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1452 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1453 pipe_name(pipe));
1454
1455 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1456 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1457 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1458 }
1459
1460 static void intel_init_dpio(struct drm_device *dev)
1461 {
1462 struct drm_i915_private *dev_priv = dev->dev_private;
1463
1464 if (!IS_VALLEYVIEW(dev))
1465 return;
1466
1467 /*
1468 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1469 * CHV x1 PHY (DP/HDMI D)
1470 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1471 */
1472 if (IS_CHERRYVIEW(dev)) {
1473 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1474 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1475 } else {
1476 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1477 }
1478 }
1479
1480 static void intel_reset_dpio(struct drm_device *dev)
1481 {
1482 struct drm_i915_private *dev_priv = dev->dev_private;
1483
1484 if (!IS_VALLEYVIEW(dev))
1485 return;
1486
1487 if (IS_CHERRYVIEW(dev)) {
1488 enum dpio_phy phy;
1489 u32 val;
1490
1491 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1492 /* Poll for phypwrgood signal */
1493 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1494 PHY_POWERGOOD(phy), 1))
1495 DRM_ERROR("Display PHY %d is not power up\n", phy);
1496
1497 /*
1498 * Deassert common lane reset for PHY.
1499 *
1500 * This should only be done on init and resume from S3
1501 * with both PLLs disabled, or we risk losing DPIO and
1502 * PLL synchronization.
1503 */
1504 val = I915_READ(DISPLAY_PHY_CONTROL);
1505 I915_WRITE(DISPLAY_PHY_CONTROL,
1506 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1507 }
1508
1509 } else {
1510 /*
1511 * If DPIO has already been reset, e.g. by BIOS, just skip all
1512 * this.
1513 */
1514 if (I915_READ(DPIO_CTL) & DPIO_CMNRST)
1515 return;
1516
1517 /*
1518 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
1519 * Need to assert and de-assert PHY SB reset by gating the
1520 * common lane power, then un-gating it.
1521 * Simply ungating isn't enough to reset the PHY enough to get
1522 * ports and lanes running.
1523 */
1524 __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC,
1525 false);
1526 __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC,
1527 true);
1528 }
1529 }
1530
1531 static void vlv_enable_pll(struct intel_crtc *crtc)
1532 {
1533 struct drm_device *dev = crtc->base.dev;
1534 struct drm_i915_private *dev_priv = dev->dev_private;
1535 int reg = DPLL(crtc->pipe);
1536 u32 dpll = crtc->config.dpll_hw_state.dpll;
1537
1538 assert_pipe_disabled(dev_priv, crtc->pipe);
1539
1540 /* No really, not for ILK+ */
1541 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1542
1543 /* PLL is protected by panel, make sure we can write it */
1544 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1545 assert_panel_unlocked(dev_priv, crtc->pipe);
1546
1547 I915_WRITE(reg, dpll);
1548 POSTING_READ(reg);
1549 udelay(150);
1550
1551 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1552 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1553
1554 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1555 POSTING_READ(DPLL_MD(crtc->pipe));
1556
1557 /* We do this three times for luck */
1558 I915_WRITE(reg, dpll);
1559 POSTING_READ(reg);
1560 udelay(150); /* wait for warmup */
1561 I915_WRITE(reg, dpll);
1562 POSTING_READ(reg);
1563 udelay(150); /* wait for warmup */
1564 I915_WRITE(reg, dpll);
1565 POSTING_READ(reg);
1566 udelay(150); /* wait for warmup */
1567 }
1568
1569 static void chv_enable_pll(struct intel_crtc *crtc)
1570 {
1571 struct drm_device *dev = crtc->base.dev;
1572 struct drm_i915_private *dev_priv = dev->dev_private;
1573 int pipe = crtc->pipe;
1574 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1575 u32 tmp;
1576
1577 assert_pipe_disabled(dev_priv, crtc->pipe);
1578
1579 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1580
1581 mutex_lock(&dev_priv->dpio_lock);
1582
1583 /* Enable back the 10bit clock to display controller */
1584 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1585 tmp |= DPIO_DCLKP_EN;
1586 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1587
1588 /*
1589 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1590 */
1591 udelay(1);
1592
1593 /* Enable PLL */
1594 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1595
1596 /* Check PLL is locked */
1597 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1598 DRM_ERROR("PLL %d failed to lock\n", pipe);
1599
1600 /* not sure when this should be written */
1601 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1602 POSTING_READ(DPLL_MD(pipe));
1603
1604 mutex_unlock(&dev_priv->dpio_lock);
1605 }
1606
1607 static void i9xx_enable_pll(struct intel_crtc *crtc)
1608 {
1609 struct drm_device *dev = crtc->base.dev;
1610 struct drm_i915_private *dev_priv = dev->dev_private;
1611 int reg = DPLL(crtc->pipe);
1612 u32 dpll = crtc->config.dpll_hw_state.dpll;
1613
1614 assert_pipe_disabled(dev_priv, crtc->pipe);
1615
1616 /* No really, not for ILK+ */
1617 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1618
1619 /* PLL is protected by panel, make sure we can write it */
1620 if (IS_MOBILE(dev) && !IS_I830(dev))
1621 assert_panel_unlocked(dev_priv, crtc->pipe);
1622
1623 I915_WRITE(reg, dpll);
1624
1625 /* Wait for the clocks to stabilize. */
1626 POSTING_READ(reg);
1627 udelay(150);
1628
1629 if (INTEL_INFO(dev)->gen >= 4) {
1630 I915_WRITE(DPLL_MD(crtc->pipe),
1631 crtc->config.dpll_hw_state.dpll_md);
1632 } else {
1633 /* The pixel multiplier can only be updated once the
1634 * DPLL is enabled and the clocks are stable.
1635 *
1636 * So write it again.
1637 */
1638 I915_WRITE(reg, dpll);
1639 }
1640
1641 /* We do this three times for luck */
1642 I915_WRITE(reg, dpll);
1643 POSTING_READ(reg);
1644 udelay(150); /* wait for warmup */
1645 I915_WRITE(reg, dpll);
1646 POSTING_READ(reg);
1647 udelay(150); /* wait for warmup */
1648 I915_WRITE(reg, dpll);
1649 POSTING_READ(reg);
1650 udelay(150); /* wait for warmup */
1651 }
1652
1653 /**
1654 * i9xx_disable_pll - disable a PLL
1655 * @dev_priv: i915 private structure
1656 * @pipe: pipe PLL to disable
1657 *
1658 * Disable the PLL for @pipe, making sure the pipe is off first.
1659 *
1660 * Note! This is for pre-ILK only.
1661 */
1662 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1663 {
1664 /* Don't disable pipe A or pipe A PLLs if needed */
1665 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1666 return;
1667
1668 /* Make sure the pipe isn't still relying on us */
1669 assert_pipe_disabled(dev_priv, pipe);
1670
1671 I915_WRITE(DPLL(pipe), 0);
1672 POSTING_READ(DPLL(pipe));
1673 }
1674
1675 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1676 {
1677 u32 val = 0;
1678
1679 /* Make sure the pipe isn't still relying on us */
1680 assert_pipe_disabled(dev_priv, pipe);
1681
1682 /*
1683 * Leave integrated clock source and reference clock enabled for pipe B.
1684 * The latter is needed for VGA hotplug / manual detection.
1685 */
1686 if (pipe == PIPE_B)
1687 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1688 I915_WRITE(DPLL(pipe), val);
1689 POSTING_READ(DPLL(pipe));
1690
1691 }
1692
1693 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1694 {
1695 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1696 u32 val;
1697
1698 /* Make sure the pipe isn't still relying on us */
1699 assert_pipe_disabled(dev_priv, pipe);
1700
1701 /* Set PLL en = 0 */
1702 val = DPLL_SSC_REF_CLOCK_CHV;
1703 if (pipe != PIPE_A)
1704 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1705 I915_WRITE(DPLL(pipe), val);
1706 POSTING_READ(DPLL(pipe));
1707
1708 mutex_lock(&dev_priv->dpio_lock);
1709
1710 /* Disable 10bit clock to display controller */
1711 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1712 val &= ~DPIO_DCLKP_EN;
1713 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1714
1715 mutex_unlock(&dev_priv->dpio_lock);
1716 }
1717
1718 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1719 struct intel_digital_port *dport)
1720 {
1721 u32 port_mask;
1722 int dpll_reg;
1723
1724 switch (dport->port) {
1725 case PORT_B:
1726 port_mask = DPLL_PORTB_READY_MASK;
1727 dpll_reg = DPLL(0);
1728 break;
1729 case PORT_C:
1730 port_mask = DPLL_PORTC_READY_MASK;
1731 dpll_reg = DPLL(0);
1732 break;
1733 case PORT_D:
1734 port_mask = DPLL_PORTD_READY_MASK;
1735 dpll_reg = DPIO_PHY_STATUS;
1736 break;
1737 default:
1738 BUG();
1739 }
1740
1741 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1742 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1743 port_name(dport->port), I915_READ(dpll_reg));
1744 }
1745
1746 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1747 {
1748 struct drm_device *dev = crtc->base.dev;
1749 struct drm_i915_private *dev_priv = dev->dev_private;
1750 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1751
1752 WARN_ON(!pll->refcount);
1753 if (pll->active == 0) {
1754 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1755 WARN_ON(pll->on);
1756 assert_shared_dpll_disabled(dev_priv, pll);
1757
1758 pll->mode_set(dev_priv, pll);
1759 }
1760 }
1761
1762 /**
1763 * intel_enable_shared_dpll - enable PCH PLL
1764 * @dev_priv: i915 private structure
1765 * @pipe: pipe PLL to enable
1766 *
1767 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1768 * drives the transcoder clock.
1769 */
1770 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1771 {
1772 struct drm_device *dev = crtc->base.dev;
1773 struct drm_i915_private *dev_priv = dev->dev_private;
1774 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1775
1776 if (WARN_ON(pll == NULL))
1777 return;
1778
1779 if (WARN_ON(pll->refcount == 0))
1780 return;
1781
1782 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1783 pll->name, pll->active, pll->on,
1784 crtc->base.base.id);
1785
1786 if (pll->active++) {
1787 WARN_ON(!pll->on);
1788 assert_shared_dpll_enabled(dev_priv, pll);
1789 return;
1790 }
1791 WARN_ON(pll->on);
1792
1793 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1794 pll->enable(dev_priv, pll);
1795 pll->on = true;
1796 }
1797
1798 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1799 {
1800 struct drm_device *dev = crtc->base.dev;
1801 struct drm_i915_private *dev_priv = dev->dev_private;
1802 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1803
1804 /* PCH only available on ILK+ */
1805 BUG_ON(INTEL_INFO(dev)->gen < 5);
1806 if (WARN_ON(pll == NULL))
1807 return;
1808
1809 if (WARN_ON(pll->refcount == 0))
1810 return;
1811
1812 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1813 pll->name, pll->active, pll->on,
1814 crtc->base.base.id);
1815
1816 if (WARN_ON(pll->active == 0)) {
1817 assert_shared_dpll_disabled(dev_priv, pll);
1818 return;
1819 }
1820
1821 assert_shared_dpll_enabled(dev_priv, pll);
1822 WARN_ON(!pll->on);
1823 if (--pll->active)
1824 return;
1825
1826 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1827 pll->disable(dev_priv, pll);
1828 pll->on = false;
1829 }
1830
1831 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1832 enum pipe pipe)
1833 {
1834 struct drm_device *dev = dev_priv->dev;
1835 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1837 uint32_t reg, val, pipeconf_val;
1838
1839 /* PCH only available on ILK+ */
1840 BUG_ON(INTEL_INFO(dev)->gen < 5);
1841
1842 /* Make sure PCH DPLL is enabled */
1843 assert_shared_dpll_enabled(dev_priv,
1844 intel_crtc_to_shared_dpll(intel_crtc));
1845
1846 /* FDI must be feeding us bits for PCH ports */
1847 assert_fdi_tx_enabled(dev_priv, pipe);
1848 assert_fdi_rx_enabled(dev_priv, pipe);
1849
1850 if (HAS_PCH_CPT(dev)) {
1851 /* Workaround: Set the timing override bit before enabling the
1852 * pch transcoder. */
1853 reg = TRANS_CHICKEN2(pipe);
1854 val = I915_READ(reg);
1855 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1856 I915_WRITE(reg, val);
1857 }
1858
1859 reg = PCH_TRANSCONF(pipe);
1860 val = I915_READ(reg);
1861 pipeconf_val = I915_READ(PIPECONF(pipe));
1862
1863 if (HAS_PCH_IBX(dev_priv->dev)) {
1864 /*
1865 * make the BPC in transcoder be consistent with
1866 * that in pipeconf reg.
1867 */
1868 val &= ~PIPECONF_BPC_MASK;
1869 val |= pipeconf_val & PIPECONF_BPC_MASK;
1870 }
1871
1872 val &= ~TRANS_INTERLACE_MASK;
1873 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1874 if (HAS_PCH_IBX(dev_priv->dev) &&
1875 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1876 val |= TRANS_LEGACY_INTERLACED_ILK;
1877 else
1878 val |= TRANS_INTERLACED;
1879 else
1880 val |= TRANS_PROGRESSIVE;
1881
1882 I915_WRITE(reg, val | TRANS_ENABLE);
1883 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1884 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1885 }
1886
1887 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1888 enum transcoder cpu_transcoder)
1889 {
1890 u32 val, pipeconf_val;
1891
1892 /* PCH only available on ILK+ */
1893 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1894
1895 /* FDI must be feeding us bits for PCH ports */
1896 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1897 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1898
1899 /* Workaround: set timing override bit. */
1900 val = I915_READ(_TRANSA_CHICKEN2);
1901 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1902 I915_WRITE(_TRANSA_CHICKEN2, val);
1903
1904 val = TRANS_ENABLE;
1905 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1906
1907 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1908 PIPECONF_INTERLACED_ILK)
1909 val |= TRANS_INTERLACED;
1910 else
1911 val |= TRANS_PROGRESSIVE;
1912
1913 I915_WRITE(LPT_TRANSCONF, val);
1914 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1915 DRM_ERROR("Failed to enable PCH transcoder\n");
1916 }
1917
1918 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1919 enum pipe pipe)
1920 {
1921 struct drm_device *dev = dev_priv->dev;
1922 uint32_t reg, val;
1923
1924 /* FDI relies on the transcoder */
1925 assert_fdi_tx_disabled(dev_priv, pipe);
1926 assert_fdi_rx_disabled(dev_priv, pipe);
1927
1928 /* Ports must be off as well */
1929 assert_pch_ports_disabled(dev_priv, pipe);
1930
1931 reg = PCH_TRANSCONF(pipe);
1932 val = I915_READ(reg);
1933 val &= ~TRANS_ENABLE;
1934 I915_WRITE(reg, val);
1935 /* wait for PCH transcoder off, transcoder state */
1936 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1937 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1938
1939 if (!HAS_PCH_IBX(dev)) {
1940 /* Workaround: Clear the timing override chicken bit again. */
1941 reg = TRANS_CHICKEN2(pipe);
1942 val = I915_READ(reg);
1943 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1944 I915_WRITE(reg, val);
1945 }
1946 }
1947
1948 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1949 {
1950 u32 val;
1951
1952 val = I915_READ(LPT_TRANSCONF);
1953 val &= ~TRANS_ENABLE;
1954 I915_WRITE(LPT_TRANSCONF, val);
1955 /* wait for PCH transcoder off, transcoder state */
1956 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1957 DRM_ERROR("Failed to disable PCH transcoder\n");
1958
1959 /* Workaround: clear timing override bit. */
1960 val = I915_READ(_TRANSA_CHICKEN2);
1961 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1962 I915_WRITE(_TRANSA_CHICKEN2, val);
1963 }
1964
1965 /**
1966 * intel_enable_pipe - enable a pipe, asserting requirements
1967 * @crtc: crtc responsible for the pipe
1968 *
1969 * Enable @crtc's pipe, making sure that various hardware specific requirements
1970 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1971 */
1972 static void intel_enable_pipe(struct intel_crtc *crtc)
1973 {
1974 struct drm_device *dev = crtc->base.dev;
1975 struct drm_i915_private *dev_priv = dev->dev_private;
1976 enum pipe pipe = crtc->pipe;
1977 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1978 pipe);
1979 enum pipe pch_transcoder;
1980 int reg;
1981 u32 val;
1982
1983 assert_planes_disabled(dev_priv, pipe);
1984 assert_cursor_disabled(dev_priv, pipe);
1985 assert_sprites_disabled(dev_priv, pipe);
1986
1987 if (HAS_PCH_LPT(dev_priv->dev))
1988 pch_transcoder = TRANSCODER_A;
1989 else
1990 pch_transcoder = pipe;
1991
1992 /*
1993 * A pipe without a PLL won't actually be able to drive bits from
1994 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1995 * need the check.
1996 */
1997 if (!HAS_PCH_SPLIT(dev_priv->dev))
1998 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1999 assert_dsi_pll_enabled(dev_priv);
2000 else
2001 assert_pll_enabled(dev_priv, pipe);
2002 else {
2003 if (crtc->config.has_pch_encoder) {
2004 /* if driving the PCH, we need FDI enabled */
2005 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2006 assert_fdi_tx_pll_enabled(dev_priv,
2007 (enum pipe) cpu_transcoder);
2008 }
2009 /* FIXME: assert CPU port conditions for SNB+ */
2010 }
2011
2012 reg = PIPECONF(cpu_transcoder);
2013 val = I915_READ(reg);
2014 if (val & PIPECONF_ENABLE) {
2015 WARN_ON(!(pipe == PIPE_A &&
2016 dev_priv->quirks & QUIRK_PIPEA_FORCE));
2017 return;
2018 }
2019
2020 I915_WRITE(reg, val | PIPECONF_ENABLE);
2021 POSTING_READ(reg);
2022 }
2023
2024 /**
2025 * intel_disable_pipe - disable a pipe, asserting requirements
2026 * @dev_priv: i915 private structure
2027 * @pipe: pipe to disable
2028 *
2029 * Disable @pipe, making sure that various hardware specific requirements
2030 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2031 *
2032 * @pipe should be %PIPE_A or %PIPE_B.
2033 *
2034 * Will wait until the pipe has shut down before returning.
2035 */
2036 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2037 enum pipe pipe)
2038 {
2039 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2040 pipe);
2041 int reg;
2042 u32 val;
2043
2044 /*
2045 * Make sure planes won't keep trying to pump pixels to us,
2046 * or we might hang the display.
2047 */
2048 assert_planes_disabled(dev_priv, pipe);
2049 assert_cursor_disabled(dev_priv, pipe);
2050 assert_sprites_disabled(dev_priv, pipe);
2051
2052 /* Don't disable pipe A or pipe A PLLs if needed */
2053 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2054 return;
2055
2056 reg = PIPECONF(cpu_transcoder);
2057 val = I915_READ(reg);
2058 if ((val & PIPECONF_ENABLE) == 0)
2059 return;
2060
2061 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2062 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2063 }
2064
2065 /*
2066 * Plane regs are double buffered, going from enabled->disabled needs a
2067 * trigger in order to latch. The display address reg provides this.
2068 */
2069 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2070 enum plane plane)
2071 {
2072 struct drm_device *dev = dev_priv->dev;
2073 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2074
2075 I915_WRITE(reg, I915_READ(reg));
2076 POSTING_READ(reg);
2077 }
2078
2079 /**
2080 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2081 * @dev_priv: i915 private structure
2082 * @plane: plane to enable
2083 * @pipe: pipe being fed
2084 *
2085 * Enable @plane on @pipe, making sure that @pipe is running first.
2086 */
2087 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2088 enum plane plane, enum pipe pipe)
2089 {
2090 struct intel_crtc *intel_crtc =
2091 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2092 int reg;
2093 u32 val;
2094
2095 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2096 assert_pipe_enabled(dev_priv, pipe);
2097
2098 if (intel_crtc->primary_enabled)
2099 return;
2100
2101 intel_crtc->primary_enabled = true;
2102
2103 reg = DSPCNTR(plane);
2104 val = I915_READ(reg);
2105 WARN_ON(val & DISPLAY_PLANE_ENABLE);
2106
2107 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2108 intel_flush_primary_plane(dev_priv, plane);
2109 }
2110
2111 /**
2112 * intel_disable_primary_hw_plane - disable the primary hardware plane
2113 * @dev_priv: i915 private structure
2114 * @plane: plane to disable
2115 * @pipe: pipe consuming the data
2116 *
2117 * Disable @plane; should be an independent operation.
2118 */
2119 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2120 enum plane plane, enum pipe pipe)
2121 {
2122 struct intel_crtc *intel_crtc =
2123 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2124 int reg;
2125 u32 val;
2126
2127 if (!intel_crtc->primary_enabled)
2128 return;
2129
2130 intel_crtc->primary_enabled = false;
2131
2132 reg = DSPCNTR(plane);
2133 val = I915_READ(reg);
2134 WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2135
2136 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2137 intel_flush_primary_plane(dev_priv, plane);
2138 }
2139
2140 static bool need_vtd_wa(struct drm_device *dev)
2141 {
2142 #ifdef CONFIG_INTEL_IOMMU
2143 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2144 return true;
2145 #endif
2146 return false;
2147 }
2148
2149 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2150 {
2151 int tile_height;
2152
2153 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2154 return ALIGN(height, tile_height);
2155 }
2156
2157 int
2158 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2159 struct drm_i915_gem_object *obj,
2160 struct intel_engine_cs *pipelined)
2161 {
2162 struct drm_i915_private *dev_priv = dev->dev_private;
2163 u32 alignment;
2164 int ret;
2165
2166 switch (obj->tiling_mode) {
2167 case I915_TILING_NONE:
2168 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2169 alignment = 128 * 1024;
2170 else if (INTEL_INFO(dev)->gen >= 4)
2171 alignment = 4 * 1024;
2172 else
2173 alignment = 64 * 1024;
2174 break;
2175 case I915_TILING_X:
2176 /* pin() will align the object as required by fence */
2177 alignment = 0;
2178 break;
2179 case I915_TILING_Y:
2180 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2181 return -EINVAL;
2182 default:
2183 BUG();
2184 }
2185
2186 /* Note that the w/a also requires 64 PTE of padding following the
2187 * bo. We currently fill all unused PTE with the shadow page and so
2188 * we should always have valid PTE following the scanout preventing
2189 * the VT-d warning.
2190 */
2191 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2192 alignment = 256 * 1024;
2193
2194 dev_priv->mm.interruptible = false;
2195 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2196 if (ret)
2197 goto err_interruptible;
2198
2199 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2200 * fence, whereas 965+ only requires a fence if using
2201 * framebuffer compression. For simplicity, we always install
2202 * a fence as the cost is not that onerous.
2203 */
2204 ret = i915_gem_object_get_fence(obj);
2205 if (ret)
2206 goto err_unpin;
2207
2208 i915_gem_object_pin_fence(obj);
2209
2210 dev_priv->mm.interruptible = true;
2211 return 0;
2212
2213 err_unpin:
2214 i915_gem_object_unpin_from_display_plane(obj);
2215 err_interruptible:
2216 dev_priv->mm.interruptible = true;
2217 return ret;
2218 }
2219
2220 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2221 {
2222 i915_gem_object_unpin_fence(obj);
2223 i915_gem_object_unpin_from_display_plane(obj);
2224 }
2225
2226 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2227 * is assumed to be a power-of-two. */
2228 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2229 unsigned int tiling_mode,
2230 unsigned int cpp,
2231 unsigned int pitch)
2232 {
2233 if (tiling_mode != I915_TILING_NONE) {
2234 unsigned int tile_rows, tiles;
2235
2236 tile_rows = *y / 8;
2237 *y %= 8;
2238
2239 tiles = *x / (512/cpp);
2240 *x %= 512/cpp;
2241
2242 return tile_rows * pitch * 8 + tiles * 4096;
2243 } else {
2244 unsigned int offset;
2245
2246 offset = *y * pitch + *x * cpp;
2247 *y = 0;
2248 *x = (offset & 4095) / cpp;
2249 return offset & -4096;
2250 }
2251 }
2252
2253 int intel_format_to_fourcc(int format)
2254 {
2255 switch (format) {
2256 case DISPPLANE_8BPP:
2257 return DRM_FORMAT_C8;
2258 case DISPPLANE_BGRX555:
2259 return DRM_FORMAT_XRGB1555;
2260 case DISPPLANE_BGRX565:
2261 return DRM_FORMAT_RGB565;
2262 default:
2263 case DISPPLANE_BGRX888:
2264 return DRM_FORMAT_XRGB8888;
2265 case DISPPLANE_RGBX888:
2266 return DRM_FORMAT_XBGR8888;
2267 case DISPPLANE_BGRX101010:
2268 return DRM_FORMAT_XRGB2101010;
2269 case DISPPLANE_RGBX101010:
2270 return DRM_FORMAT_XBGR2101010;
2271 }
2272 }
2273
2274 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2275 struct intel_plane_config *plane_config)
2276 {
2277 struct drm_device *dev = crtc->base.dev;
2278 struct drm_i915_gem_object *obj = NULL;
2279 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2280 u32 base = plane_config->base;
2281
2282 if (plane_config->size == 0)
2283 return false;
2284
2285 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2286 plane_config->size);
2287 if (!obj)
2288 return false;
2289
2290 if (plane_config->tiled) {
2291 obj->tiling_mode = I915_TILING_X;
2292 obj->stride = crtc->base.primary->fb->pitches[0];
2293 }
2294
2295 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2296 mode_cmd.width = crtc->base.primary->fb->width;
2297 mode_cmd.height = crtc->base.primary->fb->height;
2298 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2299
2300 mutex_lock(&dev->struct_mutex);
2301
2302 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2303 &mode_cmd, obj)) {
2304 DRM_DEBUG_KMS("intel fb init failed\n");
2305 goto out_unref_obj;
2306 }
2307
2308 mutex_unlock(&dev->struct_mutex);
2309
2310 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2311 return true;
2312
2313 out_unref_obj:
2314 drm_gem_object_unreference(&obj->base);
2315 mutex_unlock(&dev->struct_mutex);
2316 return false;
2317 }
2318
2319 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2320 struct intel_plane_config *plane_config)
2321 {
2322 struct drm_device *dev = intel_crtc->base.dev;
2323 struct drm_crtc *c;
2324 struct intel_crtc *i;
2325 struct intel_framebuffer *fb;
2326
2327 if (!intel_crtc->base.primary->fb)
2328 return;
2329
2330 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2331 return;
2332
2333 kfree(intel_crtc->base.primary->fb);
2334 intel_crtc->base.primary->fb = NULL;
2335
2336 /*
2337 * Failed to alloc the obj, check to see if we should share
2338 * an fb with another CRTC instead
2339 */
2340 for_each_crtc(dev, c) {
2341 i = to_intel_crtc(c);
2342
2343 if (c == &intel_crtc->base)
2344 continue;
2345
2346 if (!i->active || !c->primary->fb)
2347 continue;
2348
2349 fb = to_intel_framebuffer(c->primary->fb);
2350 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2351 drm_framebuffer_reference(c->primary->fb);
2352 intel_crtc->base.primary->fb = c->primary->fb;
2353 break;
2354 }
2355 }
2356 }
2357
2358 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2359 struct drm_framebuffer *fb,
2360 int x, int y)
2361 {
2362 struct drm_device *dev = crtc->dev;
2363 struct drm_i915_private *dev_priv = dev->dev_private;
2364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2365 struct intel_framebuffer *intel_fb;
2366 struct drm_i915_gem_object *obj;
2367 int plane = intel_crtc->plane;
2368 unsigned long linear_offset;
2369 u32 dspcntr;
2370 u32 reg;
2371
2372 intel_fb = to_intel_framebuffer(fb);
2373 obj = intel_fb->obj;
2374
2375 reg = DSPCNTR(plane);
2376 dspcntr = I915_READ(reg);
2377 /* Mask out pixel format bits in case we change it */
2378 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2379 switch (fb->pixel_format) {
2380 case DRM_FORMAT_C8:
2381 dspcntr |= DISPPLANE_8BPP;
2382 break;
2383 case DRM_FORMAT_XRGB1555:
2384 case DRM_FORMAT_ARGB1555:
2385 dspcntr |= DISPPLANE_BGRX555;
2386 break;
2387 case DRM_FORMAT_RGB565:
2388 dspcntr |= DISPPLANE_BGRX565;
2389 break;
2390 case DRM_FORMAT_XRGB8888:
2391 case DRM_FORMAT_ARGB8888:
2392 dspcntr |= DISPPLANE_BGRX888;
2393 break;
2394 case DRM_FORMAT_XBGR8888:
2395 case DRM_FORMAT_ABGR8888:
2396 dspcntr |= DISPPLANE_RGBX888;
2397 break;
2398 case DRM_FORMAT_XRGB2101010:
2399 case DRM_FORMAT_ARGB2101010:
2400 dspcntr |= DISPPLANE_BGRX101010;
2401 break;
2402 case DRM_FORMAT_XBGR2101010:
2403 case DRM_FORMAT_ABGR2101010:
2404 dspcntr |= DISPPLANE_RGBX101010;
2405 break;
2406 default:
2407 BUG();
2408 }
2409
2410 if (INTEL_INFO(dev)->gen >= 4) {
2411 if (obj->tiling_mode != I915_TILING_NONE)
2412 dspcntr |= DISPPLANE_TILED;
2413 else
2414 dspcntr &= ~DISPPLANE_TILED;
2415 }
2416
2417 if (IS_G4X(dev))
2418 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2419
2420 I915_WRITE(reg, dspcntr);
2421
2422 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2423
2424 if (INTEL_INFO(dev)->gen >= 4) {
2425 intel_crtc->dspaddr_offset =
2426 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2427 fb->bits_per_pixel / 8,
2428 fb->pitches[0]);
2429 linear_offset -= intel_crtc->dspaddr_offset;
2430 } else {
2431 intel_crtc->dspaddr_offset = linear_offset;
2432 }
2433
2434 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2435 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2436 fb->pitches[0]);
2437 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2438 if (INTEL_INFO(dev)->gen >= 4) {
2439 I915_WRITE(DSPSURF(plane),
2440 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2441 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2442 I915_WRITE(DSPLINOFF(plane), linear_offset);
2443 } else
2444 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2445 POSTING_READ(reg);
2446 }
2447
2448 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2449 struct drm_framebuffer *fb,
2450 int x, int y)
2451 {
2452 struct drm_device *dev = crtc->dev;
2453 struct drm_i915_private *dev_priv = dev->dev_private;
2454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2455 struct intel_framebuffer *intel_fb;
2456 struct drm_i915_gem_object *obj;
2457 int plane = intel_crtc->plane;
2458 unsigned long linear_offset;
2459 u32 dspcntr;
2460 u32 reg;
2461
2462 intel_fb = to_intel_framebuffer(fb);
2463 obj = intel_fb->obj;
2464
2465 reg = DSPCNTR(plane);
2466 dspcntr = I915_READ(reg);
2467 /* Mask out pixel format bits in case we change it */
2468 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2469 switch (fb->pixel_format) {
2470 case DRM_FORMAT_C8:
2471 dspcntr |= DISPPLANE_8BPP;
2472 break;
2473 case DRM_FORMAT_RGB565:
2474 dspcntr |= DISPPLANE_BGRX565;
2475 break;
2476 case DRM_FORMAT_XRGB8888:
2477 case DRM_FORMAT_ARGB8888:
2478 dspcntr |= DISPPLANE_BGRX888;
2479 break;
2480 case DRM_FORMAT_XBGR8888:
2481 case DRM_FORMAT_ABGR8888:
2482 dspcntr |= DISPPLANE_RGBX888;
2483 break;
2484 case DRM_FORMAT_XRGB2101010:
2485 case DRM_FORMAT_ARGB2101010:
2486 dspcntr |= DISPPLANE_BGRX101010;
2487 break;
2488 case DRM_FORMAT_XBGR2101010:
2489 case DRM_FORMAT_ABGR2101010:
2490 dspcntr |= DISPPLANE_RGBX101010;
2491 break;
2492 default:
2493 BUG();
2494 }
2495
2496 if (obj->tiling_mode != I915_TILING_NONE)
2497 dspcntr |= DISPPLANE_TILED;
2498 else
2499 dspcntr &= ~DISPPLANE_TILED;
2500
2501 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2502 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2503 else
2504 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2505
2506 I915_WRITE(reg, dspcntr);
2507
2508 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2509 intel_crtc->dspaddr_offset =
2510 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2511 fb->bits_per_pixel / 8,
2512 fb->pitches[0]);
2513 linear_offset -= intel_crtc->dspaddr_offset;
2514
2515 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2516 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2517 fb->pitches[0]);
2518 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2519 I915_WRITE(DSPSURF(plane),
2520 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2521 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2522 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2523 } else {
2524 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2525 I915_WRITE(DSPLINOFF(plane), linear_offset);
2526 }
2527 POSTING_READ(reg);
2528 }
2529
2530 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2531 static int
2532 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2533 int x, int y, enum mode_set_atomic state)
2534 {
2535 struct drm_device *dev = crtc->dev;
2536 struct drm_i915_private *dev_priv = dev->dev_private;
2537
2538 if (dev_priv->display.disable_fbc)
2539 dev_priv->display.disable_fbc(dev);
2540 intel_increase_pllclock(crtc);
2541
2542 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2543
2544 return 0;
2545 }
2546
2547 void intel_display_handle_reset(struct drm_device *dev)
2548 {
2549 struct drm_i915_private *dev_priv = dev->dev_private;
2550 struct drm_crtc *crtc;
2551
2552 /*
2553 * Flips in the rings have been nuked by the reset,
2554 * so complete all pending flips so that user space
2555 * will get its events and not get stuck.
2556 *
2557 * Also update the base address of all primary
2558 * planes to the the last fb to make sure we're
2559 * showing the correct fb after a reset.
2560 *
2561 * Need to make two loops over the crtcs so that we
2562 * don't try to grab a crtc mutex before the
2563 * pending_flip_queue really got woken up.
2564 */
2565
2566 for_each_crtc(dev, crtc) {
2567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2568 enum plane plane = intel_crtc->plane;
2569
2570 intel_prepare_page_flip(dev, plane);
2571 intel_finish_page_flip_plane(dev, plane);
2572 }
2573
2574 for_each_crtc(dev, crtc) {
2575 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2576
2577 drm_modeset_lock(&crtc->mutex, NULL);
2578 /*
2579 * FIXME: Once we have proper support for primary planes (and
2580 * disabling them without disabling the entire crtc) allow again
2581 * a NULL crtc->primary->fb.
2582 */
2583 if (intel_crtc->active && crtc->primary->fb)
2584 dev_priv->display.update_primary_plane(crtc,
2585 crtc->primary->fb,
2586 crtc->x,
2587 crtc->y);
2588 drm_modeset_unlock(&crtc->mutex);
2589 }
2590 }
2591
2592 static int
2593 intel_finish_fb(struct drm_framebuffer *old_fb)
2594 {
2595 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2596 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2597 bool was_interruptible = dev_priv->mm.interruptible;
2598 int ret;
2599
2600 /* Big Hammer, we also need to ensure that any pending
2601 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2602 * current scanout is retired before unpinning the old
2603 * framebuffer.
2604 *
2605 * This should only fail upon a hung GPU, in which case we
2606 * can safely continue.
2607 */
2608 dev_priv->mm.interruptible = false;
2609 ret = i915_gem_object_finish_gpu(obj);
2610 dev_priv->mm.interruptible = was_interruptible;
2611
2612 return ret;
2613 }
2614
2615 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2616 {
2617 struct drm_device *dev = crtc->dev;
2618 struct drm_i915_private *dev_priv = dev->dev_private;
2619 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2620 unsigned long flags;
2621 bool pending;
2622
2623 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2624 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2625 return false;
2626
2627 spin_lock_irqsave(&dev->event_lock, flags);
2628 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2629 spin_unlock_irqrestore(&dev->event_lock, flags);
2630
2631 return pending;
2632 }
2633
2634 static int
2635 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2636 struct drm_framebuffer *fb)
2637 {
2638 struct drm_device *dev = crtc->dev;
2639 struct drm_i915_private *dev_priv = dev->dev_private;
2640 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2641 struct drm_framebuffer *old_fb;
2642 int ret;
2643
2644 if (intel_crtc_has_pending_flip(crtc)) {
2645 DRM_ERROR("pipe is still busy with an old pageflip\n");
2646 return -EBUSY;
2647 }
2648
2649 /* no fb bound */
2650 if (!fb) {
2651 DRM_ERROR("No FB bound\n");
2652 return 0;
2653 }
2654
2655 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2656 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2657 plane_name(intel_crtc->plane),
2658 INTEL_INFO(dev)->num_pipes);
2659 return -EINVAL;
2660 }
2661
2662 mutex_lock(&dev->struct_mutex);
2663 ret = intel_pin_and_fence_fb_obj(dev,
2664 to_intel_framebuffer(fb)->obj,
2665 NULL);
2666 mutex_unlock(&dev->struct_mutex);
2667 if (ret != 0) {
2668 DRM_ERROR("pin & fence failed\n");
2669 return ret;
2670 }
2671
2672 /*
2673 * Update pipe size and adjust fitter if needed: the reason for this is
2674 * that in compute_mode_changes we check the native mode (not the pfit
2675 * mode) to see if we can flip rather than do a full mode set. In the
2676 * fastboot case, we'll flip, but if we don't update the pipesrc and
2677 * pfit state, we'll end up with a big fb scanned out into the wrong
2678 * sized surface.
2679 *
2680 * To fix this properly, we need to hoist the checks up into
2681 * compute_mode_changes (or above), check the actual pfit state and
2682 * whether the platform allows pfit disable with pipe active, and only
2683 * then update the pipesrc and pfit state, even on the flip path.
2684 */
2685 if (i915.fastboot) {
2686 const struct drm_display_mode *adjusted_mode =
2687 &intel_crtc->config.adjusted_mode;
2688
2689 I915_WRITE(PIPESRC(intel_crtc->pipe),
2690 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2691 (adjusted_mode->crtc_vdisplay - 1));
2692 if (!intel_crtc->config.pch_pfit.enabled &&
2693 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2694 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2695 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2696 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2697 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2698 }
2699 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2700 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2701 }
2702
2703 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2704
2705 old_fb = crtc->primary->fb;
2706 crtc->primary->fb = fb;
2707 crtc->x = x;
2708 crtc->y = y;
2709
2710 if (old_fb) {
2711 if (intel_crtc->active && old_fb != fb)
2712 intel_wait_for_vblank(dev, intel_crtc->pipe);
2713 mutex_lock(&dev->struct_mutex);
2714 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2715 mutex_unlock(&dev->struct_mutex);
2716 }
2717
2718 mutex_lock(&dev->struct_mutex);
2719 intel_update_fbc(dev);
2720 intel_edp_psr_update(dev);
2721 mutex_unlock(&dev->struct_mutex);
2722
2723 return 0;
2724 }
2725
2726 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2727 {
2728 struct drm_device *dev = crtc->dev;
2729 struct drm_i915_private *dev_priv = dev->dev_private;
2730 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2731 int pipe = intel_crtc->pipe;
2732 u32 reg, temp;
2733
2734 /* enable normal train */
2735 reg = FDI_TX_CTL(pipe);
2736 temp = I915_READ(reg);
2737 if (IS_IVYBRIDGE(dev)) {
2738 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2739 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2740 } else {
2741 temp &= ~FDI_LINK_TRAIN_NONE;
2742 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2743 }
2744 I915_WRITE(reg, temp);
2745
2746 reg = FDI_RX_CTL(pipe);
2747 temp = I915_READ(reg);
2748 if (HAS_PCH_CPT(dev)) {
2749 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2750 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2751 } else {
2752 temp &= ~FDI_LINK_TRAIN_NONE;
2753 temp |= FDI_LINK_TRAIN_NONE;
2754 }
2755 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2756
2757 /* wait one idle pattern time */
2758 POSTING_READ(reg);
2759 udelay(1000);
2760
2761 /* IVB wants error correction enabled */
2762 if (IS_IVYBRIDGE(dev))
2763 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2764 FDI_FE_ERRC_ENABLE);
2765 }
2766
2767 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2768 {
2769 return crtc->base.enabled && crtc->active &&
2770 crtc->config.has_pch_encoder;
2771 }
2772
2773 static void ivb_modeset_global_resources(struct drm_device *dev)
2774 {
2775 struct drm_i915_private *dev_priv = dev->dev_private;
2776 struct intel_crtc *pipe_B_crtc =
2777 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2778 struct intel_crtc *pipe_C_crtc =
2779 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2780 uint32_t temp;
2781
2782 /*
2783 * When everything is off disable fdi C so that we could enable fdi B
2784 * with all lanes. Note that we don't care about enabled pipes without
2785 * an enabled pch encoder.
2786 */
2787 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2788 !pipe_has_enabled_pch(pipe_C_crtc)) {
2789 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2790 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2791
2792 temp = I915_READ(SOUTH_CHICKEN1);
2793 temp &= ~FDI_BC_BIFURCATION_SELECT;
2794 DRM_DEBUG_KMS("disabling fdi C rx\n");
2795 I915_WRITE(SOUTH_CHICKEN1, temp);
2796 }
2797 }
2798
2799 /* The FDI link training functions for ILK/Ibexpeak. */
2800 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2801 {
2802 struct drm_device *dev = crtc->dev;
2803 struct drm_i915_private *dev_priv = dev->dev_private;
2804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2805 int pipe = intel_crtc->pipe;
2806 u32 reg, temp, tries;
2807
2808 /* FDI needs bits from pipe first */
2809 assert_pipe_enabled(dev_priv, pipe);
2810
2811 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2812 for train result */
2813 reg = FDI_RX_IMR(pipe);
2814 temp = I915_READ(reg);
2815 temp &= ~FDI_RX_SYMBOL_LOCK;
2816 temp &= ~FDI_RX_BIT_LOCK;
2817 I915_WRITE(reg, temp);
2818 I915_READ(reg);
2819 udelay(150);
2820
2821 /* enable CPU FDI TX and PCH FDI RX */
2822 reg = FDI_TX_CTL(pipe);
2823 temp = I915_READ(reg);
2824 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2825 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2826 temp &= ~FDI_LINK_TRAIN_NONE;
2827 temp |= FDI_LINK_TRAIN_PATTERN_1;
2828 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2829
2830 reg = FDI_RX_CTL(pipe);
2831 temp = I915_READ(reg);
2832 temp &= ~FDI_LINK_TRAIN_NONE;
2833 temp |= FDI_LINK_TRAIN_PATTERN_1;
2834 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2835
2836 POSTING_READ(reg);
2837 udelay(150);
2838
2839 /* Ironlake workaround, enable clock pointer after FDI enable*/
2840 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2841 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2842 FDI_RX_PHASE_SYNC_POINTER_EN);
2843
2844 reg = FDI_RX_IIR(pipe);
2845 for (tries = 0; tries < 5; tries++) {
2846 temp = I915_READ(reg);
2847 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2848
2849 if ((temp & FDI_RX_BIT_LOCK)) {
2850 DRM_DEBUG_KMS("FDI train 1 done.\n");
2851 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2852 break;
2853 }
2854 }
2855 if (tries == 5)
2856 DRM_ERROR("FDI train 1 fail!\n");
2857
2858 /* Train 2 */
2859 reg = FDI_TX_CTL(pipe);
2860 temp = I915_READ(reg);
2861 temp &= ~FDI_LINK_TRAIN_NONE;
2862 temp |= FDI_LINK_TRAIN_PATTERN_2;
2863 I915_WRITE(reg, temp);
2864
2865 reg = FDI_RX_CTL(pipe);
2866 temp = I915_READ(reg);
2867 temp &= ~FDI_LINK_TRAIN_NONE;
2868 temp |= FDI_LINK_TRAIN_PATTERN_2;
2869 I915_WRITE(reg, temp);
2870
2871 POSTING_READ(reg);
2872 udelay(150);
2873
2874 reg = FDI_RX_IIR(pipe);
2875 for (tries = 0; tries < 5; tries++) {
2876 temp = I915_READ(reg);
2877 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2878
2879 if (temp & FDI_RX_SYMBOL_LOCK) {
2880 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2881 DRM_DEBUG_KMS("FDI train 2 done.\n");
2882 break;
2883 }
2884 }
2885 if (tries == 5)
2886 DRM_ERROR("FDI train 2 fail!\n");
2887
2888 DRM_DEBUG_KMS("FDI train done\n");
2889
2890 }
2891
2892 static const int snb_b_fdi_train_param[] = {
2893 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2894 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2895 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2896 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2897 };
2898
2899 /* The FDI link training functions for SNB/Cougarpoint. */
2900 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2901 {
2902 struct drm_device *dev = crtc->dev;
2903 struct drm_i915_private *dev_priv = dev->dev_private;
2904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2905 int pipe = intel_crtc->pipe;
2906 u32 reg, temp, i, retry;
2907
2908 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2909 for train result */
2910 reg = FDI_RX_IMR(pipe);
2911 temp = I915_READ(reg);
2912 temp &= ~FDI_RX_SYMBOL_LOCK;
2913 temp &= ~FDI_RX_BIT_LOCK;
2914 I915_WRITE(reg, temp);
2915
2916 POSTING_READ(reg);
2917 udelay(150);
2918
2919 /* enable CPU FDI TX and PCH FDI RX */
2920 reg = FDI_TX_CTL(pipe);
2921 temp = I915_READ(reg);
2922 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2923 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2924 temp &= ~FDI_LINK_TRAIN_NONE;
2925 temp |= FDI_LINK_TRAIN_PATTERN_1;
2926 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2927 /* SNB-B */
2928 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2929 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2930
2931 I915_WRITE(FDI_RX_MISC(pipe),
2932 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2933
2934 reg = FDI_RX_CTL(pipe);
2935 temp = I915_READ(reg);
2936 if (HAS_PCH_CPT(dev)) {
2937 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2938 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2939 } else {
2940 temp &= ~FDI_LINK_TRAIN_NONE;
2941 temp |= FDI_LINK_TRAIN_PATTERN_1;
2942 }
2943 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2944
2945 POSTING_READ(reg);
2946 udelay(150);
2947
2948 for (i = 0; i < 4; i++) {
2949 reg = FDI_TX_CTL(pipe);
2950 temp = I915_READ(reg);
2951 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2952 temp |= snb_b_fdi_train_param[i];
2953 I915_WRITE(reg, temp);
2954
2955 POSTING_READ(reg);
2956 udelay(500);
2957
2958 for (retry = 0; retry < 5; retry++) {
2959 reg = FDI_RX_IIR(pipe);
2960 temp = I915_READ(reg);
2961 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2962 if (temp & FDI_RX_BIT_LOCK) {
2963 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2964 DRM_DEBUG_KMS("FDI train 1 done.\n");
2965 break;
2966 }
2967 udelay(50);
2968 }
2969 if (retry < 5)
2970 break;
2971 }
2972 if (i == 4)
2973 DRM_ERROR("FDI train 1 fail!\n");
2974
2975 /* Train 2 */
2976 reg = FDI_TX_CTL(pipe);
2977 temp = I915_READ(reg);
2978 temp &= ~FDI_LINK_TRAIN_NONE;
2979 temp |= FDI_LINK_TRAIN_PATTERN_2;
2980 if (IS_GEN6(dev)) {
2981 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2982 /* SNB-B */
2983 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2984 }
2985 I915_WRITE(reg, temp);
2986
2987 reg = FDI_RX_CTL(pipe);
2988 temp = I915_READ(reg);
2989 if (HAS_PCH_CPT(dev)) {
2990 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2991 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2992 } else {
2993 temp &= ~FDI_LINK_TRAIN_NONE;
2994 temp |= FDI_LINK_TRAIN_PATTERN_2;
2995 }
2996 I915_WRITE(reg, temp);
2997
2998 POSTING_READ(reg);
2999 udelay(150);
3000
3001 for (i = 0; i < 4; i++) {
3002 reg = FDI_TX_CTL(pipe);
3003 temp = I915_READ(reg);
3004 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3005 temp |= snb_b_fdi_train_param[i];
3006 I915_WRITE(reg, temp);
3007
3008 POSTING_READ(reg);
3009 udelay(500);
3010
3011 for (retry = 0; retry < 5; retry++) {
3012 reg = FDI_RX_IIR(pipe);
3013 temp = I915_READ(reg);
3014 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3015 if (temp & FDI_RX_SYMBOL_LOCK) {
3016 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3017 DRM_DEBUG_KMS("FDI train 2 done.\n");
3018 break;
3019 }
3020 udelay(50);
3021 }
3022 if (retry < 5)
3023 break;
3024 }
3025 if (i == 4)
3026 DRM_ERROR("FDI train 2 fail!\n");
3027
3028 DRM_DEBUG_KMS("FDI train done.\n");
3029 }
3030
3031 /* Manual link training for Ivy Bridge A0 parts */
3032 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3033 {
3034 struct drm_device *dev = crtc->dev;
3035 struct drm_i915_private *dev_priv = dev->dev_private;
3036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3037 int pipe = intel_crtc->pipe;
3038 u32 reg, temp, i, j;
3039
3040 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3041 for train result */
3042 reg = FDI_RX_IMR(pipe);
3043 temp = I915_READ(reg);
3044 temp &= ~FDI_RX_SYMBOL_LOCK;
3045 temp &= ~FDI_RX_BIT_LOCK;
3046 I915_WRITE(reg, temp);
3047
3048 POSTING_READ(reg);
3049 udelay(150);
3050
3051 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3052 I915_READ(FDI_RX_IIR(pipe)));
3053
3054 /* Try each vswing and preemphasis setting twice before moving on */
3055 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3056 /* disable first in case we need to retry */
3057 reg = FDI_TX_CTL(pipe);
3058 temp = I915_READ(reg);
3059 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3060 temp &= ~FDI_TX_ENABLE;
3061 I915_WRITE(reg, temp);
3062
3063 reg = FDI_RX_CTL(pipe);
3064 temp = I915_READ(reg);
3065 temp &= ~FDI_LINK_TRAIN_AUTO;
3066 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3067 temp &= ~FDI_RX_ENABLE;
3068 I915_WRITE(reg, temp);
3069
3070 /* enable CPU FDI TX and PCH FDI RX */
3071 reg = FDI_TX_CTL(pipe);
3072 temp = I915_READ(reg);
3073 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3074 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3075 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3076 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3077 temp |= snb_b_fdi_train_param[j/2];
3078 temp |= FDI_COMPOSITE_SYNC;
3079 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3080
3081 I915_WRITE(FDI_RX_MISC(pipe),
3082 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3083
3084 reg = FDI_RX_CTL(pipe);
3085 temp = I915_READ(reg);
3086 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3087 temp |= FDI_COMPOSITE_SYNC;
3088 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3089
3090 POSTING_READ(reg);
3091 udelay(1); /* should be 0.5us */
3092
3093 for (i = 0; i < 4; i++) {
3094 reg = FDI_RX_IIR(pipe);
3095 temp = I915_READ(reg);
3096 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3097
3098 if (temp & FDI_RX_BIT_LOCK ||
3099 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3100 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3101 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3102 i);
3103 break;
3104 }
3105 udelay(1); /* should be 0.5us */
3106 }
3107 if (i == 4) {
3108 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3109 continue;
3110 }
3111
3112 /* Train 2 */
3113 reg = FDI_TX_CTL(pipe);
3114 temp = I915_READ(reg);
3115 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3116 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3117 I915_WRITE(reg, temp);
3118
3119 reg = FDI_RX_CTL(pipe);
3120 temp = I915_READ(reg);
3121 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3122 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3123 I915_WRITE(reg, temp);
3124
3125 POSTING_READ(reg);
3126 udelay(2); /* should be 1.5us */
3127
3128 for (i = 0; i < 4; i++) {
3129 reg = FDI_RX_IIR(pipe);
3130 temp = I915_READ(reg);
3131 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3132
3133 if (temp & FDI_RX_SYMBOL_LOCK ||
3134 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3135 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3136 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3137 i);
3138 goto train_done;
3139 }
3140 udelay(2); /* should be 1.5us */
3141 }
3142 if (i == 4)
3143 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3144 }
3145
3146 train_done:
3147 DRM_DEBUG_KMS("FDI train done.\n");
3148 }
3149
3150 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3151 {
3152 struct drm_device *dev = intel_crtc->base.dev;
3153 struct drm_i915_private *dev_priv = dev->dev_private;
3154 int pipe = intel_crtc->pipe;
3155 u32 reg, temp;
3156
3157
3158 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3159 reg = FDI_RX_CTL(pipe);
3160 temp = I915_READ(reg);
3161 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3162 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3163 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3164 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3165
3166 POSTING_READ(reg);
3167 udelay(200);
3168
3169 /* Switch from Rawclk to PCDclk */
3170 temp = I915_READ(reg);
3171 I915_WRITE(reg, temp | FDI_PCDCLK);
3172
3173 POSTING_READ(reg);
3174 udelay(200);
3175
3176 /* Enable CPU FDI TX PLL, always on for Ironlake */
3177 reg = FDI_TX_CTL(pipe);
3178 temp = I915_READ(reg);
3179 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3180 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3181
3182 POSTING_READ(reg);
3183 udelay(100);
3184 }
3185 }
3186
3187 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3188 {
3189 struct drm_device *dev = intel_crtc->base.dev;
3190 struct drm_i915_private *dev_priv = dev->dev_private;
3191 int pipe = intel_crtc->pipe;
3192 u32 reg, temp;
3193
3194 /* Switch from PCDclk to Rawclk */
3195 reg = FDI_RX_CTL(pipe);
3196 temp = I915_READ(reg);
3197 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3198
3199 /* Disable CPU FDI TX PLL */
3200 reg = FDI_TX_CTL(pipe);
3201 temp = I915_READ(reg);
3202 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3203
3204 POSTING_READ(reg);
3205 udelay(100);
3206
3207 reg = FDI_RX_CTL(pipe);
3208 temp = I915_READ(reg);
3209 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3210
3211 /* Wait for the clocks to turn off. */
3212 POSTING_READ(reg);
3213 udelay(100);
3214 }
3215
3216 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3217 {
3218 struct drm_device *dev = crtc->dev;
3219 struct drm_i915_private *dev_priv = dev->dev_private;
3220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3221 int pipe = intel_crtc->pipe;
3222 u32 reg, temp;
3223
3224 /* disable CPU FDI tx and PCH FDI rx */
3225 reg = FDI_TX_CTL(pipe);
3226 temp = I915_READ(reg);
3227 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3228 POSTING_READ(reg);
3229
3230 reg = FDI_RX_CTL(pipe);
3231 temp = I915_READ(reg);
3232 temp &= ~(0x7 << 16);
3233 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3234 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3235
3236 POSTING_READ(reg);
3237 udelay(100);
3238
3239 /* Ironlake workaround, disable clock pointer after downing FDI */
3240 if (HAS_PCH_IBX(dev))
3241 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3242
3243 /* still set train pattern 1 */
3244 reg = FDI_TX_CTL(pipe);
3245 temp = I915_READ(reg);
3246 temp &= ~FDI_LINK_TRAIN_NONE;
3247 temp |= FDI_LINK_TRAIN_PATTERN_1;
3248 I915_WRITE(reg, temp);
3249
3250 reg = FDI_RX_CTL(pipe);
3251 temp = I915_READ(reg);
3252 if (HAS_PCH_CPT(dev)) {
3253 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3254 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3255 } else {
3256 temp &= ~FDI_LINK_TRAIN_NONE;
3257 temp |= FDI_LINK_TRAIN_PATTERN_1;
3258 }
3259 /* BPC in FDI rx is consistent with that in PIPECONF */
3260 temp &= ~(0x07 << 16);
3261 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3262 I915_WRITE(reg, temp);
3263
3264 POSTING_READ(reg);
3265 udelay(100);
3266 }
3267
3268 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3269 {
3270 struct intel_crtc *crtc;
3271
3272 /* Note that we don't need to be called with mode_config.lock here
3273 * as our list of CRTC objects is static for the lifetime of the
3274 * device and so cannot disappear as we iterate. Similarly, we can
3275 * happily treat the predicates as racy, atomic checks as userspace
3276 * cannot claim and pin a new fb without at least acquring the
3277 * struct_mutex and so serialising with us.
3278 */
3279 for_each_intel_crtc(dev, crtc) {
3280 if (atomic_read(&crtc->unpin_work_count) == 0)
3281 continue;
3282
3283 if (crtc->unpin_work)
3284 intel_wait_for_vblank(dev, crtc->pipe);
3285
3286 return true;
3287 }
3288
3289 return false;
3290 }
3291
3292 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3293 {
3294 struct drm_device *dev = crtc->dev;
3295 struct drm_i915_private *dev_priv = dev->dev_private;
3296
3297 if (crtc->primary->fb == NULL)
3298 return;
3299
3300 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3301
3302 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3303 !intel_crtc_has_pending_flip(crtc),
3304 60*HZ) == 0);
3305
3306 mutex_lock(&dev->struct_mutex);
3307 intel_finish_fb(crtc->primary->fb);
3308 mutex_unlock(&dev->struct_mutex);
3309 }
3310
3311 /* Program iCLKIP clock to the desired frequency */
3312 static void lpt_program_iclkip(struct drm_crtc *crtc)
3313 {
3314 struct drm_device *dev = crtc->dev;
3315 struct drm_i915_private *dev_priv = dev->dev_private;
3316 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3317 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3318 u32 temp;
3319
3320 mutex_lock(&dev_priv->dpio_lock);
3321
3322 /* It is necessary to ungate the pixclk gate prior to programming
3323 * the divisors, and gate it back when it is done.
3324 */
3325 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3326
3327 /* Disable SSCCTL */
3328 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3329 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3330 SBI_SSCCTL_DISABLE,
3331 SBI_ICLK);
3332
3333 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3334 if (clock == 20000) {
3335 auxdiv = 1;
3336 divsel = 0x41;
3337 phaseinc = 0x20;
3338 } else {
3339 /* The iCLK virtual clock root frequency is in MHz,
3340 * but the adjusted_mode->crtc_clock in in KHz. To get the
3341 * divisors, it is necessary to divide one by another, so we
3342 * convert the virtual clock precision to KHz here for higher
3343 * precision.
3344 */
3345 u32 iclk_virtual_root_freq = 172800 * 1000;
3346 u32 iclk_pi_range = 64;
3347 u32 desired_divisor, msb_divisor_value, pi_value;
3348
3349 desired_divisor = (iclk_virtual_root_freq / clock);
3350 msb_divisor_value = desired_divisor / iclk_pi_range;
3351 pi_value = desired_divisor % iclk_pi_range;
3352
3353 auxdiv = 0;
3354 divsel = msb_divisor_value - 2;
3355 phaseinc = pi_value;
3356 }
3357
3358 /* This should not happen with any sane values */
3359 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3360 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3361 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3362 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3363
3364 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3365 clock,
3366 auxdiv,
3367 divsel,
3368 phasedir,
3369 phaseinc);
3370
3371 /* Program SSCDIVINTPHASE6 */
3372 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3373 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3374 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3375 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3376 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3377 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3378 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3379 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3380
3381 /* Program SSCAUXDIV */
3382 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3383 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3384 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3385 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3386
3387 /* Enable modulator and associated divider */
3388 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3389 temp &= ~SBI_SSCCTL_DISABLE;
3390 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3391
3392 /* Wait for initialization time */
3393 udelay(24);
3394
3395 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3396
3397 mutex_unlock(&dev_priv->dpio_lock);
3398 }
3399
3400 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3401 enum pipe pch_transcoder)
3402 {
3403 struct drm_device *dev = crtc->base.dev;
3404 struct drm_i915_private *dev_priv = dev->dev_private;
3405 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3406
3407 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3408 I915_READ(HTOTAL(cpu_transcoder)));
3409 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3410 I915_READ(HBLANK(cpu_transcoder)));
3411 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3412 I915_READ(HSYNC(cpu_transcoder)));
3413
3414 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3415 I915_READ(VTOTAL(cpu_transcoder)));
3416 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3417 I915_READ(VBLANK(cpu_transcoder)));
3418 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3419 I915_READ(VSYNC(cpu_transcoder)));
3420 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3421 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3422 }
3423
3424 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3425 {
3426 struct drm_i915_private *dev_priv = dev->dev_private;
3427 uint32_t temp;
3428
3429 temp = I915_READ(SOUTH_CHICKEN1);
3430 if (temp & FDI_BC_BIFURCATION_SELECT)
3431 return;
3432
3433 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3434 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3435
3436 temp |= FDI_BC_BIFURCATION_SELECT;
3437 DRM_DEBUG_KMS("enabling fdi C rx\n");
3438 I915_WRITE(SOUTH_CHICKEN1, temp);
3439 POSTING_READ(SOUTH_CHICKEN1);
3440 }
3441
3442 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3443 {
3444 struct drm_device *dev = intel_crtc->base.dev;
3445 struct drm_i915_private *dev_priv = dev->dev_private;
3446
3447 switch (intel_crtc->pipe) {
3448 case PIPE_A:
3449 break;
3450 case PIPE_B:
3451 if (intel_crtc->config.fdi_lanes > 2)
3452 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3453 else
3454 cpt_enable_fdi_bc_bifurcation(dev);
3455
3456 break;
3457 case PIPE_C:
3458 cpt_enable_fdi_bc_bifurcation(dev);
3459
3460 break;
3461 default:
3462 BUG();
3463 }
3464 }
3465
3466 /*
3467 * Enable PCH resources required for PCH ports:
3468 * - PCH PLLs
3469 * - FDI training & RX/TX
3470 * - update transcoder timings
3471 * - DP transcoding bits
3472 * - transcoder
3473 */
3474 static void ironlake_pch_enable(struct drm_crtc *crtc)
3475 {
3476 struct drm_device *dev = crtc->dev;
3477 struct drm_i915_private *dev_priv = dev->dev_private;
3478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3479 int pipe = intel_crtc->pipe;
3480 u32 reg, temp;
3481
3482 assert_pch_transcoder_disabled(dev_priv, pipe);
3483
3484 if (IS_IVYBRIDGE(dev))
3485 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3486
3487 /* Write the TU size bits before fdi link training, so that error
3488 * detection works. */
3489 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3490 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3491
3492 /* For PCH output, training FDI link */
3493 dev_priv->display.fdi_link_train(crtc);
3494
3495 /* We need to program the right clock selection before writing the pixel
3496 * mutliplier into the DPLL. */
3497 if (HAS_PCH_CPT(dev)) {
3498 u32 sel;
3499
3500 temp = I915_READ(PCH_DPLL_SEL);
3501 temp |= TRANS_DPLL_ENABLE(pipe);
3502 sel = TRANS_DPLLB_SEL(pipe);
3503 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3504 temp |= sel;
3505 else
3506 temp &= ~sel;
3507 I915_WRITE(PCH_DPLL_SEL, temp);
3508 }
3509
3510 /* XXX: pch pll's can be enabled any time before we enable the PCH
3511 * transcoder, and we actually should do this to not upset any PCH
3512 * transcoder that already use the clock when we share it.
3513 *
3514 * Note that enable_shared_dpll tries to do the right thing, but
3515 * get_shared_dpll unconditionally resets the pll - we need that to have
3516 * the right LVDS enable sequence. */
3517 intel_enable_shared_dpll(intel_crtc);
3518
3519 /* set transcoder timing, panel must allow it */
3520 assert_panel_unlocked(dev_priv, pipe);
3521 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3522
3523 intel_fdi_normal_train(crtc);
3524
3525 /* For PCH DP, enable TRANS_DP_CTL */
3526 if (HAS_PCH_CPT(dev) &&
3527 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3528 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3529 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3530 reg = TRANS_DP_CTL(pipe);
3531 temp = I915_READ(reg);
3532 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3533 TRANS_DP_SYNC_MASK |
3534 TRANS_DP_BPC_MASK);
3535 temp |= (TRANS_DP_OUTPUT_ENABLE |
3536 TRANS_DP_ENH_FRAMING);
3537 temp |= bpc << 9; /* same format but at 11:9 */
3538
3539 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3540 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3541 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3542 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3543
3544 switch (intel_trans_dp_port_sel(crtc)) {
3545 case PCH_DP_B:
3546 temp |= TRANS_DP_PORT_SEL_B;
3547 break;
3548 case PCH_DP_C:
3549 temp |= TRANS_DP_PORT_SEL_C;
3550 break;
3551 case PCH_DP_D:
3552 temp |= TRANS_DP_PORT_SEL_D;
3553 break;
3554 default:
3555 BUG();
3556 }
3557
3558 I915_WRITE(reg, temp);
3559 }
3560
3561 ironlake_enable_pch_transcoder(dev_priv, pipe);
3562 }
3563
3564 static void lpt_pch_enable(struct drm_crtc *crtc)
3565 {
3566 struct drm_device *dev = crtc->dev;
3567 struct drm_i915_private *dev_priv = dev->dev_private;
3568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3569 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3570
3571 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3572
3573 lpt_program_iclkip(crtc);
3574
3575 /* Set transcoder timing. */
3576 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3577
3578 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3579 }
3580
3581 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3582 {
3583 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3584
3585 if (pll == NULL)
3586 return;
3587
3588 if (pll->refcount == 0) {
3589 WARN(1, "bad %s refcount\n", pll->name);
3590 return;
3591 }
3592
3593 if (--pll->refcount == 0) {
3594 WARN_ON(pll->on);
3595 WARN_ON(pll->active);
3596 }
3597
3598 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3599 }
3600
3601 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3602 {
3603 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3604 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3605 enum intel_dpll_id i;
3606
3607 if (pll) {
3608 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3609 crtc->base.base.id, pll->name);
3610 intel_put_shared_dpll(crtc);
3611 }
3612
3613 if (HAS_PCH_IBX(dev_priv->dev)) {
3614 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3615 i = (enum intel_dpll_id) crtc->pipe;
3616 pll = &dev_priv->shared_dplls[i];
3617
3618 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3619 crtc->base.base.id, pll->name);
3620
3621 WARN_ON(pll->refcount);
3622
3623 goto found;
3624 }
3625
3626 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3627 pll = &dev_priv->shared_dplls[i];
3628
3629 /* Only want to check enabled timings first */
3630 if (pll->refcount == 0)
3631 continue;
3632
3633 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3634 sizeof(pll->hw_state)) == 0) {
3635 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3636 crtc->base.base.id,
3637 pll->name, pll->refcount, pll->active);
3638
3639 goto found;
3640 }
3641 }
3642
3643 /* Ok no matching timings, maybe there's a free one? */
3644 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3645 pll = &dev_priv->shared_dplls[i];
3646 if (pll->refcount == 0) {
3647 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3648 crtc->base.base.id, pll->name);
3649 goto found;
3650 }
3651 }
3652
3653 return NULL;
3654
3655 found:
3656 if (pll->refcount == 0)
3657 pll->hw_state = crtc->config.dpll_hw_state;
3658
3659 crtc->config.shared_dpll = i;
3660 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3661 pipe_name(crtc->pipe));
3662
3663 pll->refcount++;
3664
3665 return pll;
3666 }
3667
3668 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3669 {
3670 struct drm_i915_private *dev_priv = dev->dev_private;
3671 int dslreg = PIPEDSL(pipe);
3672 u32 temp;
3673
3674 temp = I915_READ(dslreg);
3675 udelay(500);
3676 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3677 if (wait_for(I915_READ(dslreg) != temp, 5))
3678 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3679 }
3680 }
3681
3682 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3683 {
3684 struct drm_device *dev = crtc->base.dev;
3685 struct drm_i915_private *dev_priv = dev->dev_private;
3686 int pipe = crtc->pipe;
3687
3688 if (crtc->config.pch_pfit.enabled) {
3689 /* Force use of hard-coded filter coefficients
3690 * as some pre-programmed values are broken,
3691 * e.g. x201.
3692 */
3693 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3694 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3695 PF_PIPE_SEL_IVB(pipe));
3696 else
3697 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3698 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3699 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3700 }
3701 }
3702
3703 static void intel_enable_planes(struct drm_crtc *crtc)
3704 {
3705 struct drm_device *dev = crtc->dev;
3706 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3707 struct drm_plane *plane;
3708 struct intel_plane *intel_plane;
3709
3710 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3711 intel_plane = to_intel_plane(plane);
3712 if (intel_plane->pipe == pipe)
3713 intel_plane_restore(&intel_plane->base);
3714 }
3715 }
3716
3717 static void intel_disable_planes(struct drm_crtc *crtc)
3718 {
3719 struct drm_device *dev = crtc->dev;
3720 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3721 struct drm_plane *plane;
3722 struct intel_plane *intel_plane;
3723
3724 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3725 intel_plane = to_intel_plane(plane);
3726 if (intel_plane->pipe == pipe)
3727 intel_plane_disable(&intel_plane->base);
3728 }
3729 }
3730
3731 void hsw_enable_ips(struct intel_crtc *crtc)
3732 {
3733 struct drm_device *dev = crtc->base.dev;
3734 struct drm_i915_private *dev_priv = dev->dev_private;
3735
3736 if (!crtc->config.ips_enabled)
3737 return;
3738
3739 /* We can only enable IPS after we enable a plane and wait for a vblank */
3740 intel_wait_for_vblank(dev, crtc->pipe);
3741
3742 assert_plane_enabled(dev_priv, crtc->plane);
3743 if (IS_BROADWELL(dev)) {
3744 mutex_lock(&dev_priv->rps.hw_lock);
3745 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3746 mutex_unlock(&dev_priv->rps.hw_lock);
3747 /* Quoting Art Runyan: "its not safe to expect any particular
3748 * value in IPS_CTL bit 31 after enabling IPS through the
3749 * mailbox." Moreover, the mailbox may return a bogus state,
3750 * so we need to just enable it and continue on.
3751 */
3752 } else {
3753 I915_WRITE(IPS_CTL, IPS_ENABLE);
3754 /* The bit only becomes 1 in the next vblank, so this wait here
3755 * is essentially intel_wait_for_vblank. If we don't have this
3756 * and don't wait for vblanks until the end of crtc_enable, then
3757 * the HW state readout code will complain that the expected
3758 * IPS_CTL value is not the one we read. */
3759 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3760 DRM_ERROR("Timed out waiting for IPS enable\n");
3761 }
3762 }
3763
3764 void hsw_disable_ips(struct intel_crtc *crtc)
3765 {
3766 struct drm_device *dev = crtc->base.dev;
3767 struct drm_i915_private *dev_priv = dev->dev_private;
3768
3769 if (!crtc->config.ips_enabled)
3770 return;
3771
3772 assert_plane_enabled(dev_priv, crtc->plane);
3773 if (IS_BROADWELL(dev)) {
3774 mutex_lock(&dev_priv->rps.hw_lock);
3775 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3776 mutex_unlock(&dev_priv->rps.hw_lock);
3777 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3778 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3779 DRM_ERROR("Timed out waiting for IPS disable\n");
3780 } else {
3781 I915_WRITE(IPS_CTL, 0);
3782 POSTING_READ(IPS_CTL);
3783 }
3784
3785 /* We need to wait for a vblank before we can disable the plane. */
3786 intel_wait_for_vblank(dev, crtc->pipe);
3787 }
3788
3789 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3790 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3791 {
3792 struct drm_device *dev = crtc->dev;
3793 struct drm_i915_private *dev_priv = dev->dev_private;
3794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3795 enum pipe pipe = intel_crtc->pipe;
3796 int palreg = PALETTE(pipe);
3797 int i;
3798 bool reenable_ips = false;
3799
3800 /* The clocks have to be on to load the palette. */
3801 if (!crtc->enabled || !intel_crtc->active)
3802 return;
3803
3804 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3805 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3806 assert_dsi_pll_enabled(dev_priv);
3807 else
3808 assert_pll_enabled(dev_priv, pipe);
3809 }
3810
3811 /* use legacy palette for Ironlake */
3812 if (HAS_PCH_SPLIT(dev))
3813 palreg = LGC_PALETTE(pipe);
3814
3815 /* Workaround : Do not read or write the pipe palette/gamma data while
3816 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3817 */
3818 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3819 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3820 GAMMA_MODE_MODE_SPLIT)) {
3821 hsw_disable_ips(intel_crtc);
3822 reenable_ips = true;
3823 }
3824
3825 for (i = 0; i < 256; i++) {
3826 I915_WRITE(palreg + 4 * i,
3827 (intel_crtc->lut_r[i] << 16) |
3828 (intel_crtc->lut_g[i] << 8) |
3829 intel_crtc->lut_b[i]);
3830 }
3831
3832 if (reenable_ips)
3833 hsw_enable_ips(intel_crtc);
3834 }
3835
3836 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3837 {
3838 if (!enable && intel_crtc->overlay) {
3839 struct drm_device *dev = intel_crtc->base.dev;
3840 struct drm_i915_private *dev_priv = dev->dev_private;
3841
3842 mutex_lock(&dev->struct_mutex);
3843 dev_priv->mm.interruptible = false;
3844 (void) intel_overlay_switch_off(intel_crtc->overlay);
3845 dev_priv->mm.interruptible = true;
3846 mutex_unlock(&dev->struct_mutex);
3847 }
3848
3849 /* Let userspace switch the overlay on again. In most cases userspace
3850 * has to recompute where to put it anyway.
3851 */
3852 }
3853
3854 /**
3855 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3856 * cursor plane briefly if not already running after enabling the display
3857 * plane.
3858 * This workaround avoids occasional blank screens when self refresh is
3859 * enabled.
3860 */
3861 static void
3862 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3863 {
3864 u32 cntl = I915_READ(CURCNTR(pipe));
3865
3866 if ((cntl & CURSOR_MODE) == 0) {
3867 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3868
3869 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3870 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3871 intel_wait_for_vblank(dev_priv->dev, pipe);
3872 I915_WRITE(CURCNTR(pipe), cntl);
3873 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3874 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3875 }
3876 }
3877
3878 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3879 {
3880 struct drm_device *dev = crtc->dev;
3881 struct drm_i915_private *dev_priv = dev->dev_private;
3882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3883 int pipe = intel_crtc->pipe;
3884 int plane = intel_crtc->plane;
3885
3886 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3887 intel_enable_planes(crtc);
3888 /* The fixup needs to happen before cursor is enabled */
3889 if (IS_G4X(dev))
3890 g4x_fixup_plane(dev_priv, pipe);
3891 intel_crtc_update_cursor(crtc, true);
3892 intel_crtc_dpms_overlay(intel_crtc, true);
3893
3894 hsw_enable_ips(intel_crtc);
3895
3896 mutex_lock(&dev->struct_mutex);
3897 intel_update_fbc(dev);
3898 intel_edp_psr_update(dev);
3899 mutex_unlock(&dev->struct_mutex);
3900 }
3901
3902 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3903 {
3904 struct drm_device *dev = crtc->dev;
3905 struct drm_i915_private *dev_priv = dev->dev_private;
3906 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3907 int pipe = intel_crtc->pipe;
3908 int plane = intel_crtc->plane;
3909
3910 intel_crtc_wait_for_pending_flips(crtc);
3911 drm_crtc_vblank_off(crtc);
3912
3913 if (dev_priv->fbc.plane == plane)
3914 intel_disable_fbc(dev);
3915
3916 hsw_disable_ips(intel_crtc);
3917
3918 intel_crtc_dpms_overlay(intel_crtc, false);
3919 intel_crtc_update_cursor(crtc, false);
3920 intel_disable_planes(crtc);
3921 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3922 }
3923
3924 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3925 {
3926 struct drm_device *dev = crtc->dev;
3927 struct drm_i915_private *dev_priv = dev->dev_private;
3928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3929 struct intel_encoder *encoder;
3930 int pipe = intel_crtc->pipe;
3931 enum plane plane = intel_crtc->plane;
3932
3933 WARN_ON(!crtc->enabled);
3934
3935 if (intel_crtc->active)
3936 return;
3937
3938 if (intel_crtc->config.has_pch_encoder)
3939 intel_prepare_shared_dpll(intel_crtc);
3940
3941 if (intel_crtc->config.has_dp_encoder)
3942 intel_dp_set_m_n(intel_crtc);
3943
3944 intel_set_pipe_timings(intel_crtc);
3945
3946 if (intel_crtc->config.has_pch_encoder) {
3947 intel_cpu_transcoder_set_m_n(intel_crtc,
3948 &intel_crtc->config.fdi_m_n);
3949 }
3950
3951 ironlake_set_pipeconf(crtc);
3952
3953 /* Set up the display plane register */
3954 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
3955 POSTING_READ(DSPCNTR(plane));
3956
3957 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
3958 crtc->x, crtc->y);
3959
3960 intel_crtc->active = true;
3961
3962 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3963 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3964
3965 for_each_encoder_on_crtc(dev, crtc, encoder)
3966 if (encoder->pre_enable)
3967 encoder->pre_enable(encoder);
3968
3969 if (intel_crtc->config.has_pch_encoder) {
3970 /* Note: FDI PLL enabling _must_ be done before we enable the
3971 * cpu pipes, hence this is separate from all the other fdi/pch
3972 * enabling. */
3973 ironlake_fdi_pll_enable(intel_crtc);
3974 } else {
3975 assert_fdi_tx_disabled(dev_priv, pipe);
3976 assert_fdi_rx_disabled(dev_priv, pipe);
3977 }
3978
3979 ironlake_pfit_enable(intel_crtc);
3980
3981 /*
3982 * On ILK+ LUT must be loaded before the pipe is running but with
3983 * clocks enabled
3984 */
3985 intel_crtc_load_lut(crtc);
3986
3987 intel_update_watermarks(crtc);
3988 intel_enable_pipe(intel_crtc);
3989
3990 if (intel_crtc->config.has_pch_encoder)
3991 ironlake_pch_enable(crtc);
3992
3993 for_each_encoder_on_crtc(dev, crtc, encoder)
3994 encoder->enable(encoder);
3995
3996 if (HAS_PCH_CPT(dev))
3997 cpt_verify_modeset(dev, intel_crtc->pipe);
3998
3999 intel_crtc_enable_planes(crtc);
4000
4001 drm_crtc_vblank_on(crtc);
4002 }
4003
4004 /* IPS only exists on ULT machines and is tied to pipe A. */
4005 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4006 {
4007 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4008 }
4009
4010 /*
4011 * This implements the workaround described in the "notes" section of the mode
4012 * set sequence documentation. When going from no pipes or single pipe to
4013 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4014 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4015 */
4016 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4017 {
4018 struct drm_device *dev = crtc->base.dev;
4019 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4020
4021 /* We want to get the other_active_crtc only if there's only 1 other
4022 * active crtc. */
4023 for_each_intel_crtc(dev, crtc_it) {
4024 if (!crtc_it->active || crtc_it == crtc)
4025 continue;
4026
4027 if (other_active_crtc)
4028 return;
4029
4030 other_active_crtc = crtc_it;
4031 }
4032 if (!other_active_crtc)
4033 return;
4034
4035 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4036 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4037 }
4038
4039 static void haswell_crtc_enable(struct drm_crtc *crtc)
4040 {
4041 struct drm_device *dev = crtc->dev;
4042 struct drm_i915_private *dev_priv = dev->dev_private;
4043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4044 struct intel_encoder *encoder;
4045 int pipe = intel_crtc->pipe;
4046 enum plane plane = intel_crtc->plane;
4047
4048 WARN_ON(!crtc->enabled);
4049
4050 if (intel_crtc->active)
4051 return;
4052
4053 if (intel_crtc->config.has_dp_encoder)
4054 intel_dp_set_m_n(intel_crtc);
4055
4056 intel_set_pipe_timings(intel_crtc);
4057
4058 if (intel_crtc->config.has_pch_encoder) {
4059 intel_cpu_transcoder_set_m_n(intel_crtc,
4060 &intel_crtc->config.fdi_m_n);
4061 }
4062
4063 haswell_set_pipeconf(crtc);
4064
4065 intel_set_pipe_csc(crtc);
4066
4067 /* Set up the display plane register */
4068 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
4069 POSTING_READ(DSPCNTR(plane));
4070
4071 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4072 crtc->x, crtc->y);
4073
4074 intel_crtc->active = true;
4075
4076 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4077 if (intel_crtc->config.has_pch_encoder)
4078 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4079
4080 if (intel_crtc->config.has_pch_encoder)
4081 dev_priv->display.fdi_link_train(crtc);
4082
4083 for_each_encoder_on_crtc(dev, crtc, encoder)
4084 if (encoder->pre_enable)
4085 encoder->pre_enable(encoder);
4086
4087 intel_ddi_enable_pipe_clock(intel_crtc);
4088
4089 ironlake_pfit_enable(intel_crtc);
4090
4091 /*
4092 * On ILK+ LUT must be loaded before the pipe is running but with
4093 * clocks enabled
4094 */
4095 intel_crtc_load_lut(crtc);
4096
4097 intel_ddi_set_pipe_settings(crtc);
4098 intel_ddi_enable_transcoder_func(crtc);
4099
4100 intel_update_watermarks(crtc);
4101 intel_enable_pipe(intel_crtc);
4102
4103 if (intel_crtc->config.has_pch_encoder)
4104 lpt_pch_enable(crtc);
4105
4106 for_each_encoder_on_crtc(dev, crtc, encoder) {
4107 encoder->enable(encoder);
4108 intel_opregion_notify_encoder(encoder, true);
4109 }
4110
4111 /* If we change the relative order between pipe/planes enabling, we need
4112 * to change the workaround. */
4113 haswell_mode_set_planes_workaround(intel_crtc);
4114 intel_crtc_enable_planes(crtc);
4115
4116 drm_crtc_vblank_on(crtc);
4117 }
4118
4119 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4120 {
4121 struct drm_device *dev = crtc->base.dev;
4122 struct drm_i915_private *dev_priv = dev->dev_private;
4123 int pipe = crtc->pipe;
4124
4125 /* To avoid upsetting the power well on haswell only disable the pfit if
4126 * it's in use. The hw state code will make sure we get this right. */
4127 if (crtc->config.pch_pfit.enabled) {
4128 I915_WRITE(PF_CTL(pipe), 0);
4129 I915_WRITE(PF_WIN_POS(pipe), 0);
4130 I915_WRITE(PF_WIN_SZ(pipe), 0);
4131 }
4132 }
4133
4134 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4135 {
4136 struct drm_device *dev = crtc->dev;
4137 struct drm_i915_private *dev_priv = dev->dev_private;
4138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4139 struct intel_encoder *encoder;
4140 int pipe = intel_crtc->pipe;
4141 u32 reg, temp;
4142
4143 if (!intel_crtc->active)
4144 return;
4145
4146 intel_crtc_disable_planes(crtc);
4147
4148 for_each_encoder_on_crtc(dev, crtc, encoder)
4149 encoder->disable(encoder);
4150
4151 if (intel_crtc->config.has_pch_encoder)
4152 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4153
4154 intel_disable_pipe(dev_priv, pipe);
4155
4156 ironlake_pfit_disable(intel_crtc);
4157
4158 for_each_encoder_on_crtc(dev, crtc, encoder)
4159 if (encoder->post_disable)
4160 encoder->post_disable(encoder);
4161
4162 if (intel_crtc->config.has_pch_encoder) {
4163 ironlake_fdi_disable(crtc);
4164
4165 ironlake_disable_pch_transcoder(dev_priv, pipe);
4166 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4167
4168 if (HAS_PCH_CPT(dev)) {
4169 /* disable TRANS_DP_CTL */
4170 reg = TRANS_DP_CTL(pipe);
4171 temp = I915_READ(reg);
4172 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4173 TRANS_DP_PORT_SEL_MASK);
4174 temp |= TRANS_DP_PORT_SEL_NONE;
4175 I915_WRITE(reg, temp);
4176
4177 /* disable DPLL_SEL */
4178 temp = I915_READ(PCH_DPLL_SEL);
4179 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4180 I915_WRITE(PCH_DPLL_SEL, temp);
4181 }
4182
4183 /* disable PCH DPLL */
4184 intel_disable_shared_dpll(intel_crtc);
4185
4186 ironlake_fdi_pll_disable(intel_crtc);
4187 }
4188
4189 intel_crtc->active = false;
4190 intel_update_watermarks(crtc);
4191
4192 mutex_lock(&dev->struct_mutex);
4193 intel_update_fbc(dev);
4194 intel_edp_psr_update(dev);
4195 mutex_unlock(&dev->struct_mutex);
4196 }
4197
4198 static void haswell_crtc_disable(struct drm_crtc *crtc)
4199 {
4200 struct drm_device *dev = crtc->dev;
4201 struct drm_i915_private *dev_priv = dev->dev_private;
4202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4203 struct intel_encoder *encoder;
4204 int pipe = intel_crtc->pipe;
4205 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4206
4207 if (!intel_crtc->active)
4208 return;
4209
4210 intel_crtc_disable_planes(crtc);
4211
4212 for_each_encoder_on_crtc(dev, crtc, encoder) {
4213 intel_opregion_notify_encoder(encoder, false);
4214 encoder->disable(encoder);
4215 }
4216
4217 if (intel_crtc->config.has_pch_encoder)
4218 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4219 intel_disable_pipe(dev_priv, pipe);
4220
4221 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4222
4223 ironlake_pfit_disable(intel_crtc);
4224
4225 intel_ddi_disable_pipe_clock(intel_crtc);
4226
4227 for_each_encoder_on_crtc(dev, crtc, encoder)
4228 if (encoder->post_disable)
4229 encoder->post_disable(encoder);
4230
4231 if (intel_crtc->config.has_pch_encoder) {
4232 lpt_disable_pch_transcoder(dev_priv);
4233 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4234 intel_ddi_fdi_disable(crtc);
4235 }
4236
4237 intel_crtc->active = false;
4238 intel_update_watermarks(crtc);
4239
4240 mutex_lock(&dev->struct_mutex);
4241 intel_update_fbc(dev);
4242 intel_edp_psr_update(dev);
4243 mutex_unlock(&dev->struct_mutex);
4244 }
4245
4246 static void ironlake_crtc_off(struct drm_crtc *crtc)
4247 {
4248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4249 intel_put_shared_dpll(intel_crtc);
4250 }
4251
4252 static void haswell_crtc_off(struct drm_crtc *crtc)
4253 {
4254 intel_ddi_put_crtc_pll(crtc);
4255 }
4256
4257 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4258 {
4259 struct drm_device *dev = crtc->base.dev;
4260 struct drm_i915_private *dev_priv = dev->dev_private;
4261 struct intel_crtc_config *pipe_config = &crtc->config;
4262
4263 if (!crtc->config.gmch_pfit.control)
4264 return;
4265
4266 /*
4267 * The panel fitter should only be adjusted whilst the pipe is disabled,
4268 * according to register description and PRM.
4269 */
4270 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4271 assert_pipe_disabled(dev_priv, crtc->pipe);
4272
4273 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4274 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4275
4276 /* Border color in case we don't scale up to the full screen. Black by
4277 * default, change to something else for debugging. */
4278 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4279 }
4280
4281 #define for_each_power_domain(domain, mask) \
4282 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4283 if ((1 << (domain)) & (mask))
4284
4285 enum intel_display_power_domain
4286 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4287 {
4288 struct drm_device *dev = intel_encoder->base.dev;
4289 struct intel_digital_port *intel_dig_port;
4290
4291 switch (intel_encoder->type) {
4292 case INTEL_OUTPUT_UNKNOWN:
4293 /* Only DDI platforms should ever use this output type */
4294 WARN_ON_ONCE(!HAS_DDI(dev));
4295 case INTEL_OUTPUT_DISPLAYPORT:
4296 case INTEL_OUTPUT_HDMI:
4297 case INTEL_OUTPUT_EDP:
4298 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4299 switch (intel_dig_port->port) {
4300 case PORT_A:
4301 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4302 case PORT_B:
4303 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4304 case PORT_C:
4305 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4306 case PORT_D:
4307 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4308 default:
4309 WARN_ON_ONCE(1);
4310 return POWER_DOMAIN_PORT_OTHER;
4311 }
4312 case INTEL_OUTPUT_ANALOG:
4313 return POWER_DOMAIN_PORT_CRT;
4314 case INTEL_OUTPUT_DSI:
4315 return POWER_DOMAIN_PORT_DSI;
4316 default:
4317 return POWER_DOMAIN_PORT_OTHER;
4318 }
4319 }
4320
4321 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4322 {
4323 struct drm_device *dev = crtc->dev;
4324 struct intel_encoder *intel_encoder;
4325 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4326 enum pipe pipe = intel_crtc->pipe;
4327 bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4328 unsigned long mask;
4329 enum transcoder transcoder;
4330
4331 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4332
4333 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4334 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4335 if (pfit_enabled)
4336 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4337
4338 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4339 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4340
4341 return mask;
4342 }
4343
4344 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4345 bool enable)
4346 {
4347 if (dev_priv->power_domains.init_power_on == enable)
4348 return;
4349
4350 if (enable)
4351 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4352 else
4353 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4354
4355 dev_priv->power_domains.init_power_on = enable;
4356 }
4357
4358 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4359 {
4360 struct drm_i915_private *dev_priv = dev->dev_private;
4361 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4362 struct intel_crtc *crtc;
4363
4364 /*
4365 * First get all needed power domains, then put all unneeded, to avoid
4366 * any unnecessary toggling of the power wells.
4367 */
4368 for_each_intel_crtc(dev, crtc) {
4369 enum intel_display_power_domain domain;
4370
4371 if (!crtc->base.enabled)
4372 continue;
4373
4374 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4375
4376 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4377 intel_display_power_get(dev_priv, domain);
4378 }
4379
4380 for_each_intel_crtc(dev, crtc) {
4381 enum intel_display_power_domain domain;
4382
4383 for_each_power_domain(domain, crtc->enabled_power_domains)
4384 intel_display_power_put(dev_priv, domain);
4385
4386 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4387 }
4388
4389 intel_display_set_init_power(dev_priv, false);
4390 }
4391
4392 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4393 {
4394 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4395
4396 /* Obtain SKU information */
4397 mutex_lock(&dev_priv->dpio_lock);
4398 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4399 CCK_FUSE_HPLL_FREQ_MASK;
4400 mutex_unlock(&dev_priv->dpio_lock);
4401
4402 return vco_freq[hpll_freq];
4403 }
4404
4405 /* Adjust CDclk dividers to allow high res or save power if possible */
4406 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4407 {
4408 struct drm_i915_private *dev_priv = dev->dev_private;
4409 u32 val, cmd;
4410
4411 WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4412 dev_priv->vlv_cdclk_freq = cdclk;
4413
4414 if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4415 cmd = 2;
4416 else if (cdclk == 266)
4417 cmd = 1;
4418 else
4419 cmd = 0;
4420
4421 mutex_lock(&dev_priv->rps.hw_lock);
4422 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4423 val &= ~DSPFREQGUAR_MASK;
4424 val |= (cmd << DSPFREQGUAR_SHIFT);
4425 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4426 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4427 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4428 50)) {
4429 DRM_ERROR("timed out waiting for CDclk change\n");
4430 }
4431 mutex_unlock(&dev_priv->rps.hw_lock);
4432
4433 if (cdclk == 400) {
4434 u32 divider, vco;
4435
4436 vco = valleyview_get_vco(dev_priv);
4437 divider = ((vco << 1) / cdclk) - 1;
4438
4439 mutex_lock(&dev_priv->dpio_lock);
4440 /* adjust cdclk divider */
4441 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4442 val &= ~0xf;
4443 val |= divider;
4444 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4445 mutex_unlock(&dev_priv->dpio_lock);
4446 }
4447
4448 mutex_lock(&dev_priv->dpio_lock);
4449 /* adjust self-refresh exit latency value */
4450 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4451 val &= ~0x7f;
4452
4453 /*
4454 * For high bandwidth configs, we set a higher latency in the bunit
4455 * so that the core display fetch happens in time to avoid underruns.
4456 */
4457 if (cdclk == 400)
4458 val |= 4500 / 250; /* 4.5 usec */
4459 else
4460 val |= 3000 / 250; /* 3.0 usec */
4461 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4462 mutex_unlock(&dev_priv->dpio_lock);
4463
4464 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4465 intel_i2c_reset(dev);
4466 }
4467
4468 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4469 {
4470 int cur_cdclk, vco;
4471 int divider;
4472
4473 vco = valleyview_get_vco(dev_priv);
4474
4475 mutex_lock(&dev_priv->dpio_lock);
4476 divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4477 mutex_unlock(&dev_priv->dpio_lock);
4478
4479 divider &= 0xf;
4480
4481 cur_cdclk = (vco << 1) / (divider + 1);
4482
4483 return cur_cdclk;
4484 }
4485
4486 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4487 int max_pixclk)
4488 {
4489 /*
4490 * Really only a few cases to deal with, as only 4 CDclks are supported:
4491 * 200MHz
4492 * 267MHz
4493 * 320MHz
4494 * 400MHz
4495 * So we check to see whether we're above 90% of the lower bin and
4496 * adjust if needed.
4497 */
4498 if (max_pixclk > 288000) {
4499 return 400;
4500 } else if (max_pixclk > 240000) {
4501 return 320;
4502 } else
4503 return 266;
4504 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4505 }
4506
4507 /* compute the max pixel clock for new configuration */
4508 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4509 {
4510 struct drm_device *dev = dev_priv->dev;
4511 struct intel_crtc *intel_crtc;
4512 int max_pixclk = 0;
4513
4514 for_each_intel_crtc(dev, intel_crtc) {
4515 if (intel_crtc->new_enabled)
4516 max_pixclk = max(max_pixclk,
4517 intel_crtc->new_config->adjusted_mode.crtc_clock);
4518 }
4519
4520 return max_pixclk;
4521 }
4522
4523 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4524 unsigned *prepare_pipes)
4525 {
4526 struct drm_i915_private *dev_priv = dev->dev_private;
4527 struct intel_crtc *intel_crtc;
4528 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4529
4530 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4531 dev_priv->vlv_cdclk_freq)
4532 return;
4533
4534 /* disable/enable all currently active pipes while we change cdclk */
4535 for_each_intel_crtc(dev, intel_crtc)
4536 if (intel_crtc->base.enabled)
4537 *prepare_pipes |= (1 << intel_crtc->pipe);
4538 }
4539
4540 static void valleyview_modeset_global_resources(struct drm_device *dev)
4541 {
4542 struct drm_i915_private *dev_priv = dev->dev_private;
4543 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4544 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4545
4546 if (req_cdclk != dev_priv->vlv_cdclk_freq)
4547 valleyview_set_cdclk(dev, req_cdclk);
4548 modeset_update_crtc_power_domains(dev);
4549 }
4550
4551 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4552 {
4553 struct drm_device *dev = crtc->dev;
4554 struct drm_i915_private *dev_priv = dev->dev_private;
4555 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4556 struct intel_encoder *encoder;
4557 int pipe = intel_crtc->pipe;
4558 int plane = intel_crtc->plane;
4559 bool is_dsi;
4560 u32 dspcntr;
4561
4562 WARN_ON(!crtc->enabled);
4563
4564 if (intel_crtc->active)
4565 return;
4566
4567 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4568
4569 if (!is_dsi && !IS_CHERRYVIEW(dev))
4570 vlv_prepare_pll(intel_crtc);
4571
4572 /* Set up the display plane register */
4573 dspcntr = DISPPLANE_GAMMA_ENABLE;
4574
4575 if (intel_crtc->config.has_dp_encoder)
4576 intel_dp_set_m_n(intel_crtc);
4577
4578 intel_set_pipe_timings(intel_crtc);
4579
4580 /* pipesrc and dspsize control the size that is scaled from,
4581 * which should always be the user's requested size.
4582 */
4583 I915_WRITE(DSPSIZE(plane),
4584 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4585 (intel_crtc->config.pipe_src_w - 1));
4586 I915_WRITE(DSPPOS(plane), 0);
4587
4588 i9xx_set_pipeconf(intel_crtc);
4589
4590 I915_WRITE(DSPCNTR(plane), dspcntr);
4591 POSTING_READ(DSPCNTR(plane));
4592
4593 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4594 crtc->x, crtc->y);
4595
4596 intel_crtc->active = true;
4597
4598 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4599
4600 for_each_encoder_on_crtc(dev, crtc, encoder)
4601 if (encoder->pre_pll_enable)
4602 encoder->pre_pll_enable(encoder);
4603
4604 if (!is_dsi) {
4605 if (IS_CHERRYVIEW(dev))
4606 chv_enable_pll(intel_crtc);
4607 else
4608 vlv_enable_pll(intel_crtc);
4609 }
4610
4611 for_each_encoder_on_crtc(dev, crtc, encoder)
4612 if (encoder->pre_enable)
4613 encoder->pre_enable(encoder);
4614
4615 i9xx_pfit_enable(intel_crtc);
4616
4617 intel_crtc_load_lut(crtc);
4618
4619 intel_update_watermarks(crtc);
4620 intel_enable_pipe(intel_crtc);
4621
4622 for_each_encoder_on_crtc(dev, crtc, encoder)
4623 encoder->enable(encoder);
4624
4625 intel_crtc_enable_planes(crtc);
4626
4627 drm_crtc_vblank_on(crtc);
4628
4629 /* Underruns don't raise interrupts, so check manually. */
4630 i9xx_check_fifo_underruns(dev);
4631 }
4632
4633 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4634 {
4635 struct drm_device *dev = crtc->base.dev;
4636 struct drm_i915_private *dev_priv = dev->dev_private;
4637
4638 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4639 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4640 }
4641
4642 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4643 {
4644 struct drm_device *dev = crtc->dev;
4645 struct drm_i915_private *dev_priv = dev->dev_private;
4646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4647 struct intel_encoder *encoder;
4648 int pipe = intel_crtc->pipe;
4649 int plane = intel_crtc->plane;
4650 u32 dspcntr;
4651
4652 WARN_ON(!crtc->enabled);
4653
4654 if (intel_crtc->active)
4655 return;
4656
4657 i9xx_set_pll_dividers(intel_crtc);
4658
4659 /* Set up the display plane register */
4660 dspcntr = DISPPLANE_GAMMA_ENABLE;
4661
4662 if (pipe == 0)
4663 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4664 else
4665 dspcntr |= DISPPLANE_SEL_PIPE_B;
4666
4667 if (intel_crtc->config.has_dp_encoder)
4668 intel_dp_set_m_n(intel_crtc);
4669
4670 intel_set_pipe_timings(intel_crtc);
4671
4672 /* pipesrc and dspsize control the size that is scaled from,
4673 * which should always be the user's requested size.
4674 */
4675 I915_WRITE(DSPSIZE(plane),
4676 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4677 (intel_crtc->config.pipe_src_w - 1));
4678 I915_WRITE(DSPPOS(plane), 0);
4679
4680 i9xx_set_pipeconf(intel_crtc);
4681
4682 I915_WRITE(DSPCNTR(plane), dspcntr);
4683 POSTING_READ(DSPCNTR(plane));
4684
4685 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4686 crtc->x, crtc->y);
4687
4688 intel_crtc->active = true;
4689
4690 if (!IS_GEN2(dev))
4691 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4692
4693 for_each_encoder_on_crtc(dev, crtc, encoder)
4694 if (encoder->pre_enable)
4695 encoder->pre_enable(encoder);
4696
4697 i9xx_enable_pll(intel_crtc);
4698
4699 i9xx_pfit_enable(intel_crtc);
4700
4701 intel_crtc_load_lut(crtc);
4702
4703 intel_update_watermarks(crtc);
4704 intel_enable_pipe(intel_crtc);
4705
4706 for_each_encoder_on_crtc(dev, crtc, encoder)
4707 encoder->enable(encoder);
4708
4709 intel_crtc_enable_planes(crtc);
4710
4711 /*
4712 * Gen2 reports pipe underruns whenever all planes are disabled.
4713 * So don't enable underrun reporting before at least some planes
4714 * are enabled.
4715 * FIXME: Need to fix the logic to work when we turn off all planes
4716 * but leave the pipe running.
4717 */
4718 if (IS_GEN2(dev))
4719 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4720
4721 drm_crtc_vblank_on(crtc);
4722
4723 /* Underruns don't raise interrupts, so check manually. */
4724 i9xx_check_fifo_underruns(dev);
4725 }
4726
4727 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4728 {
4729 struct drm_device *dev = crtc->base.dev;
4730 struct drm_i915_private *dev_priv = dev->dev_private;
4731
4732 if (!crtc->config.gmch_pfit.control)
4733 return;
4734
4735 assert_pipe_disabled(dev_priv, crtc->pipe);
4736
4737 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4738 I915_READ(PFIT_CONTROL));
4739 I915_WRITE(PFIT_CONTROL, 0);
4740 }
4741
4742 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4743 {
4744 struct drm_device *dev = crtc->dev;
4745 struct drm_i915_private *dev_priv = dev->dev_private;
4746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4747 struct intel_encoder *encoder;
4748 int pipe = intel_crtc->pipe;
4749
4750 if (!intel_crtc->active)
4751 return;
4752
4753 /*
4754 * Gen2 reports pipe underruns whenever all planes are disabled.
4755 * So diasble underrun reporting before all the planes get disabled.
4756 * FIXME: Need to fix the logic to work when we turn off all planes
4757 * but leave the pipe running.
4758 */
4759 if (IS_GEN2(dev))
4760 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4761
4762 intel_crtc_disable_planes(crtc);
4763
4764 for_each_encoder_on_crtc(dev, crtc, encoder)
4765 encoder->disable(encoder);
4766
4767 /*
4768 * On gen2 planes are double buffered but the pipe isn't, so we must
4769 * wait for planes to fully turn off before disabling the pipe.
4770 */
4771 if (IS_GEN2(dev))
4772 intel_wait_for_vblank(dev, pipe);
4773
4774 intel_disable_pipe(dev_priv, pipe);
4775
4776 i9xx_pfit_disable(intel_crtc);
4777
4778 for_each_encoder_on_crtc(dev, crtc, encoder)
4779 if (encoder->post_disable)
4780 encoder->post_disable(encoder);
4781
4782 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4783 if (IS_CHERRYVIEW(dev))
4784 chv_disable_pll(dev_priv, pipe);
4785 else if (IS_VALLEYVIEW(dev))
4786 vlv_disable_pll(dev_priv, pipe);
4787 else
4788 i9xx_disable_pll(dev_priv, pipe);
4789 }
4790
4791 if (!IS_GEN2(dev))
4792 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4793
4794 intel_crtc->active = false;
4795 intel_update_watermarks(crtc);
4796
4797 mutex_lock(&dev->struct_mutex);
4798 intel_update_fbc(dev);
4799 intel_edp_psr_update(dev);
4800 mutex_unlock(&dev->struct_mutex);
4801 }
4802
4803 static void i9xx_crtc_off(struct drm_crtc *crtc)
4804 {
4805 }
4806
4807 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4808 bool enabled)
4809 {
4810 struct drm_device *dev = crtc->dev;
4811 struct drm_i915_master_private *master_priv;
4812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4813 int pipe = intel_crtc->pipe;
4814
4815 if (!dev->primary->master)
4816 return;
4817
4818 master_priv = dev->primary->master->driver_priv;
4819 if (!master_priv->sarea_priv)
4820 return;
4821
4822 switch (pipe) {
4823 case 0:
4824 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4825 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4826 break;
4827 case 1:
4828 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4829 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4830 break;
4831 default:
4832 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4833 break;
4834 }
4835 }
4836
4837 /**
4838 * Sets the power management mode of the pipe and plane.
4839 */
4840 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4841 {
4842 struct drm_device *dev = crtc->dev;
4843 struct drm_i915_private *dev_priv = dev->dev_private;
4844 struct intel_encoder *intel_encoder;
4845 bool enable = false;
4846
4847 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4848 enable |= intel_encoder->connectors_active;
4849
4850 if (enable)
4851 dev_priv->display.crtc_enable(crtc);
4852 else
4853 dev_priv->display.crtc_disable(crtc);
4854
4855 intel_crtc_update_sarea(crtc, enable);
4856 }
4857
4858 static void intel_crtc_disable(struct drm_crtc *crtc)
4859 {
4860 struct drm_device *dev = crtc->dev;
4861 struct drm_connector *connector;
4862 struct drm_i915_private *dev_priv = dev->dev_private;
4863
4864 /* crtc should still be enabled when we disable it. */
4865 WARN_ON(!crtc->enabled);
4866
4867 dev_priv->display.crtc_disable(crtc);
4868 intel_crtc_update_sarea(crtc, false);
4869 dev_priv->display.off(crtc);
4870
4871 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4872 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4873 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4874
4875 if (crtc->primary->fb) {
4876 mutex_lock(&dev->struct_mutex);
4877 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
4878 mutex_unlock(&dev->struct_mutex);
4879 crtc->primary->fb = NULL;
4880 }
4881
4882 /* Update computed state. */
4883 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4884 if (!connector->encoder || !connector->encoder->crtc)
4885 continue;
4886
4887 if (connector->encoder->crtc != crtc)
4888 continue;
4889
4890 connector->dpms = DRM_MODE_DPMS_OFF;
4891 to_intel_encoder(connector->encoder)->connectors_active = false;
4892 }
4893 }
4894
4895 void intel_encoder_destroy(struct drm_encoder *encoder)
4896 {
4897 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4898
4899 drm_encoder_cleanup(encoder);
4900 kfree(intel_encoder);
4901 }
4902
4903 /* Simple dpms helper for encoders with just one connector, no cloning and only
4904 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4905 * state of the entire output pipe. */
4906 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4907 {
4908 if (mode == DRM_MODE_DPMS_ON) {
4909 encoder->connectors_active = true;
4910
4911 intel_crtc_update_dpms(encoder->base.crtc);
4912 } else {
4913 encoder->connectors_active = false;
4914
4915 intel_crtc_update_dpms(encoder->base.crtc);
4916 }
4917 }
4918
4919 /* Cross check the actual hw state with our own modeset state tracking (and it's
4920 * internal consistency). */
4921 static void intel_connector_check_state(struct intel_connector *connector)
4922 {
4923 if (connector->get_hw_state(connector)) {
4924 struct intel_encoder *encoder = connector->encoder;
4925 struct drm_crtc *crtc;
4926 bool encoder_enabled;
4927 enum pipe pipe;
4928
4929 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4930 connector->base.base.id,
4931 connector->base.name);
4932
4933 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4934 "wrong connector dpms state\n");
4935 WARN(connector->base.encoder != &encoder->base,
4936 "active connector not linked to encoder\n");
4937 WARN(!encoder->connectors_active,
4938 "encoder->connectors_active not set\n");
4939
4940 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4941 WARN(!encoder_enabled, "encoder not enabled\n");
4942 if (WARN_ON(!encoder->base.crtc))
4943 return;
4944
4945 crtc = encoder->base.crtc;
4946
4947 WARN(!crtc->enabled, "crtc not enabled\n");
4948 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4949 WARN(pipe != to_intel_crtc(crtc)->pipe,
4950 "encoder active on the wrong pipe\n");
4951 }
4952 }
4953
4954 /* Even simpler default implementation, if there's really no special case to
4955 * consider. */
4956 void intel_connector_dpms(struct drm_connector *connector, int mode)
4957 {
4958 /* All the simple cases only support two dpms states. */
4959 if (mode != DRM_MODE_DPMS_ON)
4960 mode = DRM_MODE_DPMS_OFF;
4961
4962 if (mode == connector->dpms)
4963 return;
4964
4965 connector->dpms = mode;
4966
4967 /* Only need to change hw state when actually enabled */
4968 if (connector->encoder)
4969 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4970
4971 intel_modeset_check_state(connector->dev);
4972 }
4973
4974 /* Simple connector->get_hw_state implementation for encoders that support only
4975 * one connector and no cloning and hence the encoder state determines the state
4976 * of the connector. */
4977 bool intel_connector_get_hw_state(struct intel_connector *connector)
4978 {
4979 enum pipe pipe = 0;
4980 struct intel_encoder *encoder = connector->encoder;
4981
4982 return encoder->get_hw_state(encoder, &pipe);
4983 }
4984
4985 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4986 struct intel_crtc_config *pipe_config)
4987 {
4988 struct drm_i915_private *dev_priv = dev->dev_private;
4989 struct intel_crtc *pipe_B_crtc =
4990 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4991
4992 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4993 pipe_name(pipe), pipe_config->fdi_lanes);
4994 if (pipe_config->fdi_lanes > 4) {
4995 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4996 pipe_name(pipe), pipe_config->fdi_lanes);
4997 return false;
4998 }
4999
5000 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5001 if (pipe_config->fdi_lanes > 2) {
5002 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5003 pipe_config->fdi_lanes);
5004 return false;
5005 } else {
5006 return true;
5007 }
5008 }
5009
5010 if (INTEL_INFO(dev)->num_pipes == 2)
5011 return true;
5012
5013 /* Ivybridge 3 pipe is really complicated */
5014 switch (pipe) {
5015 case PIPE_A:
5016 return true;
5017 case PIPE_B:
5018 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5019 pipe_config->fdi_lanes > 2) {
5020 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5021 pipe_name(pipe), pipe_config->fdi_lanes);
5022 return false;
5023 }
5024 return true;
5025 case PIPE_C:
5026 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5027 pipe_B_crtc->config.fdi_lanes <= 2) {
5028 if (pipe_config->fdi_lanes > 2) {
5029 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5030 pipe_name(pipe), pipe_config->fdi_lanes);
5031 return false;
5032 }
5033 } else {
5034 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5035 return false;
5036 }
5037 return true;
5038 default:
5039 BUG();
5040 }
5041 }
5042
5043 #define RETRY 1
5044 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5045 struct intel_crtc_config *pipe_config)
5046 {
5047 struct drm_device *dev = intel_crtc->base.dev;
5048 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5049 int lane, link_bw, fdi_dotclock;
5050 bool setup_ok, needs_recompute = false;
5051
5052 retry:
5053 /* FDI is a binary signal running at ~2.7GHz, encoding
5054 * each output octet as 10 bits. The actual frequency
5055 * is stored as a divider into a 100MHz clock, and the
5056 * mode pixel clock is stored in units of 1KHz.
5057 * Hence the bw of each lane in terms of the mode signal
5058 * is:
5059 */
5060 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5061
5062 fdi_dotclock = adjusted_mode->crtc_clock;
5063
5064 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5065 pipe_config->pipe_bpp);
5066
5067 pipe_config->fdi_lanes = lane;
5068
5069 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5070 link_bw, &pipe_config->fdi_m_n);
5071
5072 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5073 intel_crtc->pipe, pipe_config);
5074 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5075 pipe_config->pipe_bpp -= 2*3;
5076 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5077 pipe_config->pipe_bpp);
5078 needs_recompute = true;
5079 pipe_config->bw_constrained = true;
5080
5081 goto retry;
5082 }
5083
5084 if (needs_recompute)
5085 return RETRY;
5086
5087 return setup_ok ? 0 : -EINVAL;
5088 }
5089
5090 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5091 struct intel_crtc_config *pipe_config)
5092 {
5093 pipe_config->ips_enabled = i915.enable_ips &&
5094 hsw_crtc_supports_ips(crtc) &&
5095 pipe_config->pipe_bpp <= 24;
5096 }
5097
5098 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5099 struct intel_crtc_config *pipe_config)
5100 {
5101 struct drm_device *dev = crtc->base.dev;
5102 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5103
5104 /* FIXME should check pixel clock limits on all platforms */
5105 if (INTEL_INFO(dev)->gen < 4) {
5106 struct drm_i915_private *dev_priv = dev->dev_private;
5107 int clock_limit =
5108 dev_priv->display.get_display_clock_speed(dev);
5109
5110 /*
5111 * Enable pixel doubling when the dot clock
5112 * is > 90% of the (display) core speed.
5113 *
5114 * GDG double wide on either pipe,
5115 * otherwise pipe A only.
5116 */
5117 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5118 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5119 clock_limit *= 2;
5120 pipe_config->double_wide = true;
5121 }
5122
5123 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5124 return -EINVAL;
5125 }
5126
5127 /*
5128 * Pipe horizontal size must be even in:
5129 * - DVO ganged mode
5130 * - LVDS dual channel mode
5131 * - Double wide pipe
5132 */
5133 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5134 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5135 pipe_config->pipe_src_w &= ~1;
5136
5137 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5138 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5139 */
5140 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5141 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5142 return -EINVAL;
5143
5144 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5145 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5146 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5147 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5148 * for lvds. */
5149 pipe_config->pipe_bpp = 8*3;
5150 }
5151
5152 if (HAS_IPS(dev))
5153 hsw_compute_ips_config(crtc, pipe_config);
5154
5155 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
5156 * clock survives for now. */
5157 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5158 pipe_config->shared_dpll = crtc->config.shared_dpll;
5159
5160 if (pipe_config->has_pch_encoder)
5161 return ironlake_fdi_compute_config(crtc, pipe_config);
5162
5163 return 0;
5164 }
5165
5166 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5167 {
5168 return 400000; /* FIXME */
5169 }
5170
5171 static int i945_get_display_clock_speed(struct drm_device *dev)
5172 {
5173 return 400000;
5174 }
5175
5176 static int i915_get_display_clock_speed(struct drm_device *dev)
5177 {
5178 return 333000;
5179 }
5180
5181 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5182 {
5183 return 200000;
5184 }
5185
5186 static int pnv_get_display_clock_speed(struct drm_device *dev)
5187 {
5188 u16 gcfgc = 0;
5189
5190 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5191
5192 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5193 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5194 return 267000;
5195 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5196 return 333000;
5197 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5198 return 444000;
5199 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5200 return 200000;
5201 default:
5202 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5203 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5204 return 133000;
5205 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5206 return 167000;
5207 }
5208 }
5209
5210 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5211 {
5212 u16 gcfgc = 0;
5213
5214 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5215
5216 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5217 return 133000;
5218 else {
5219 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5220 case GC_DISPLAY_CLOCK_333_MHZ:
5221 return 333000;
5222 default:
5223 case GC_DISPLAY_CLOCK_190_200_MHZ:
5224 return 190000;
5225 }
5226 }
5227 }
5228
5229 static int i865_get_display_clock_speed(struct drm_device *dev)
5230 {
5231 return 266000;
5232 }
5233
5234 static int i855_get_display_clock_speed(struct drm_device *dev)
5235 {
5236 u16 hpllcc = 0;
5237 /* Assume that the hardware is in the high speed state. This
5238 * should be the default.
5239 */
5240 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5241 case GC_CLOCK_133_200:
5242 case GC_CLOCK_100_200:
5243 return 200000;
5244 case GC_CLOCK_166_250:
5245 return 250000;
5246 case GC_CLOCK_100_133:
5247 return 133000;
5248 }
5249
5250 /* Shouldn't happen */
5251 return 0;
5252 }
5253
5254 static int i830_get_display_clock_speed(struct drm_device *dev)
5255 {
5256 return 133000;
5257 }
5258
5259 static void
5260 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5261 {
5262 while (*num > DATA_LINK_M_N_MASK ||
5263 *den > DATA_LINK_M_N_MASK) {
5264 *num >>= 1;
5265 *den >>= 1;
5266 }
5267 }
5268
5269 static void compute_m_n(unsigned int m, unsigned int n,
5270 uint32_t *ret_m, uint32_t *ret_n)
5271 {
5272 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5273 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5274 intel_reduce_m_n_ratio(ret_m, ret_n);
5275 }
5276
5277 void
5278 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5279 int pixel_clock, int link_clock,
5280 struct intel_link_m_n *m_n)
5281 {
5282 m_n->tu = 64;
5283
5284 compute_m_n(bits_per_pixel * pixel_clock,
5285 link_clock * nlanes * 8,
5286 &m_n->gmch_m, &m_n->gmch_n);
5287
5288 compute_m_n(pixel_clock, link_clock,
5289 &m_n->link_m, &m_n->link_n);
5290 }
5291
5292 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5293 {
5294 if (i915.panel_use_ssc >= 0)
5295 return i915.panel_use_ssc != 0;
5296 return dev_priv->vbt.lvds_use_ssc
5297 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5298 }
5299
5300 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5301 {
5302 struct drm_device *dev = crtc->dev;
5303 struct drm_i915_private *dev_priv = dev->dev_private;
5304 int refclk;
5305
5306 if (IS_VALLEYVIEW(dev)) {
5307 refclk = 100000;
5308 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5309 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5310 refclk = dev_priv->vbt.lvds_ssc_freq;
5311 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5312 } else if (!IS_GEN2(dev)) {
5313 refclk = 96000;
5314 } else {
5315 refclk = 48000;
5316 }
5317
5318 return refclk;
5319 }
5320
5321 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5322 {
5323 return (1 << dpll->n) << 16 | dpll->m2;
5324 }
5325
5326 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5327 {
5328 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5329 }
5330
5331 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5332 intel_clock_t *reduced_clock)
5333 {
5334 struct drm_device *dev = crtc->base.dev;
5335 u32 fp, fp2 = 0;
5336
5337 if (IS_PINEVIEW(dev)) {
5338 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5339 if (reduced_clock)
5340 fp2 = pnv_dpll_compute_fp(reduced_clock);
5341 } else {
5342 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5343 if (reduced_clock)
5344 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5345 }
5346
5347 crtc->config.dpll_hw_state.fp0 = fp;
5348
5349 crtc->lowfreq_avail = false;
5350 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5351 reduced_clock && i915.powersave) {
5352 crtc->config.dpll_hw_state.fp1 = fp2;
5353 crtc->lowfreq_avail = true;
5354 } else {
5355 crtc->config.dpll_hw_state.fp1 = fp;
5356 }
5357 }
5358
5359 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5360 pipe)
5361 {
5362 u32 reg_val;
5363
5364 /*
5365 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5366 * and set it to a reasonable value instead.
5367 */
5368 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5369 reg_val &= 0xffffff00;
5370 reg_val |= 0x00000030;
5371 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5372
5373 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5374 reg_val &= 0x8cffffff;
5375 reg_val = 0x8c000000;
5376 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5377
5378 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5379 reg_val &= 0xffffff00;
5380 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5381
5382 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5383 reg_val &= 0x00ffffff;
5384 reg_val |= 0xb0000000;
5385 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5386 }
5387
5388 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5389 struct intel_link_m_n *m_n)
5390 {
5391 struct drm_device *dev = crtc->base.dev;
5392 struct drm_i915_private *dev_priv = dev->dev_private;
5393 int pipe = crtc->pipe;
5394
5395 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5396 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5397 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5398 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5399 }
5400
5401 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5402 struct intel_link_m_n *m_n)
5403 {
5404 struct drm_device *dev = crtc->base.dev;
5405 struct drm_i915_private *dev_priv = dev->dev_private;
5406 int pipe = crtc->pipe;
5407 enum transcoder transcoder = crtc->config.cpu_transcoder;
5408
5409 if (INTEL_INFO(dev)->gen >= 5) {
5410 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5411 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5412 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5413 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5414 } else {
5415 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5416 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5417 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5418 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5419 }
5420 }
5421
5422 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5423 {
5424 if (crtc->config.has_pch_encoder)
5425 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5426 else
5427 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5428 }
5429
5430 static void vlv_update_pll(struct intel_crtc *crtc)
5431 {
5432 u32 dpll, dpll_md;
5433
5434 /*
5435 * Enable DPIO clock input. We should never disable the reference
5436 * clock for pipe B, since VGA hotplug / manual detection depends
5437 * on it.
5438 */
5439 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5440 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5441 /* We should never disable this, set it here for state tracking */
5442 if (crtc->pipe == PIPE_B)
5443 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5444 dpll |= DPLL_VCO_ENABLE;
5445 crtc->config.dpll_hw_state.dpll = dpll;
5446
5447 dpll_md = (crtc->config.pixel_multiplier - 1)
5448 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5449 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5450 }
5451
5452 static void vlv_prepare_pll(struct intel_crtc *crtc)
5453 {
5454 struct drm_device *dev = crtc->base.dev;
5455 struct drm_i915_private *dev_priv = dev->dev_private;
5456 int pipe = crtc->pipe;
5457 u32 mdiv;
5458 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5459 u32 coreclk, reg_val;
5460
5461 mutex_lock(&dev_priv->dpio_lock);
5462
5463 bestn = crtc->config.dpll.n;
5464 bestm1 = crtc->config.dpll.m1;
5465 bestm2 = crtc->config.dpll.m2;
5466 bestp1 = crtc->config.dpll.p1;
5467 bestp2 = crtc->config.dpll.p2;
5468
5469 /* See eDP HDMI DPIO driver vbios notes doc */
5470
5471 /* PLL B needs special handling */
5472 if (pipe == PIPE_B)
5473 vlv_pllb_recal_opamp(dev_priv, pipe);
5474
5475 /* Set up Tx target for periodic Rcomp update */
5476 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5477
5478 /* Disable target IRef on PLL */
5479 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5480 reg_val &= 0x00ffffff;
5481 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5482
5483 /* Disable fast lock */
5484 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5485
5486 /* Set idtafcrecal before PLL is enabled */
5487 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5488 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5489 mdiv |= ((bestn << DPIO_N_SHIFT));
5490 mdiv |= (1 << DPIO_K_SHIFT);
5491
5492 /*
5493 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5494 * but we don't support that).
5495 * Note: don't use the DAC post divider as it seems unstable.
5496 */
5497 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5498 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5499
5500 mdiv |= DPIO_ENABLE_CALIBRATION;
5501 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5502
5503 /* Set HBR and RBR LPF coefficients */
5504 if (crtc->config.port_clock == 162000 ||
5505 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5506 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5507 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5508 0x009f0003);
5509 else
5510 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5511 0x00d0000f);
5512
5513 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5514 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5515 /* Use SSC source */
5516 if (pipe == PIPE_A)
5517 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5518 0x0df40000);
5519 else
5520 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5521 0x0df70000);
5522 } else { /* HDMI or VGA */
5523 /* Use bend source */
5524 if (pipe == PIPE_A)
5525 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5526 0x0df70000);
5527 else
5528 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5529 0x0df40000);
5530 }
5531
5532 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5533 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5534 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5535 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5536 coreclk |= 0x01000000;
5537 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5538
5539 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5540 mutex_unlock(&dev_priv->dpio_lock);
5541 }
5542
5543 static void chv_update_pll(struct intel_crtc *crtc)
5544 {
5545 struct drm_device *dev = crtc->base.dev;
5546 struct drm_i915_private *dev_priv = dev->dev_private;
5547 int pipe = crtc->pipe;
5548 int dpll_reg = DPLL(crtc->pipe);
5549 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5550 u32 loopfilter, intcoeff;
5551 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5552 int refclk;
5553
5554 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5555 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5556 DPLL_VCO_ENABLE;
5557 if (pipe != PIPE_A)
5558 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5559
5560 crtc->config.dpll_hw_state.dpll_md =
5561 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5562
5563 bestn = crtc->config.dpll.n;
5564 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5565 bestm1 = crtc->config.dpll.m1;
5566 bestm2 = crtc->config.dpll.m2 >> 22;
5567 bestp1 = crtc->config.dpll.p1;
5568 bestp2 = crtc->config.dpll.p2;
5569
5570 /*
5571 * Enable Refclk and SSC
5572 */
5573 I915_WRITE(dpll_reg,
5574 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5575
5576 mutex_lock(&dev_priv->dpio_lock);
5577
5578 /* p1 and p2 divider */
5579 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5580 5 << DPIO_CHV_S1_DIV_SHIFT |
5581 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5582 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5583 1 << DPIO_CHV_K_DIV_SHIFT);
5584
5585 /* Feedback post-divider - m2 */
5586 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5587
5588 /* Feedback refclk divider - n and m1 */
5589 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5590 DPIO_CHV_M1_DIV_BY_2 |
5591 1 << DPIO_CHV_N_DIV_SHIFT);
5592
5593 /* M2 fraction division */
5594 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5595
5596 /* M2 fraction division enable */
5597 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5598 DPIO_CHV_FRAC_DIV_EN |
5599 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5600
5601 /* Loop filter */
5602 refclk = i9xx_get_refclk(&crtc->base, 0);
5603 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5604 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5605 if (refclk == 100000)
5606 intcoeff = 11;
5607 else if (refclk == 38400)
5608 intcoeff = 10;
5609 else
5610 intcoeff = 9;
5611 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5612 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5613
5614 /* AFC Recal */
5615 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5616 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5617 DPIO_AFC_RECAL);
5618
5619 mutex_unlock(&dev_priv->dpio_lock);
5620 }
5621
5622 static void i9xx_update_pll(struct intel_crtc *crtc,
5623 intel_clock_t *reduced_clock,
5624 int num_connectors)
5625 {
5626 struct drm_device *dev = crtc->base.dev;
5627 struct drm_i915_private *dev_priv = dev->dev_private;
5628 u32 dpll;
5629 bool is_sdvo;
5630 struct dpll *clock = &crtc->config.dpll;
5631
5632 i9xx_update_pll_dividers(crtc, reduced_clock);
5633
5634 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5635 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5636
5637 dpll = DPLL_VGA_MODE_DIS;
5638
5639 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5640 dpll |= DPLLB_MODE_LVDS;
5641 else
5642 dpll |= DPLLB_MODE_DAC_SERIAL;
5643
5644 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5645 dpll |= (crtc->config.pixel_multiplier - 1)
5646 << SDVO_MULTIPLIER_SHIFT_HIRES;
5647 }
5648
5649 if (is_sdvo)
5650 dpll |= DPLL_SDVO_HIGH_SPEED;
5651
5652 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5653 dpll |= DPLL_SDVO_HIGH_SPEED;
5654
5655 /* compute bitmask from p1 value */
5656 if (IS_PINEVIEW(dev))
5657 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5658 else {
5659 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5660 if (IS_G4X(dev) && reduced_clock)
5661 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5662 }
5663 switch (clock->p2) {
5664 case 5:
5665 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5666 break;
5667 case 7:
5668 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5669 break;
5670 case 10:
5671 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5672 break;
5673 case 14:
5674 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5675 break;
5676 }
5677 if (INTEL_INFO(dev)->gen >= 4)
5678 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5679
5680 if (crtc->config.sdvo_tv_clock)
5681 dpll |= PLL_REF_INPUT_TVCLKINBC;
5682 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5683 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5684 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5685 else
5686 dpll |= PLL_REF_INPUT_DREFCLK;
5687
5688 dpll |= DPLL_VCO_ENABLE;
5689 crtc->config.dpll_hw_state.dpll = dpll;
5690
5691 if (INTEL_INFO(dev)->gen >= 4) {
5692 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5693 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5694 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5695 }
5696 }
5697
5698 static void i8xx_update_pll(struct intel_crtc *crtc,
5699 intel_clock_t *reduced_clock,
5700 int num_connectors)
5701 {
5702 struct drm_device *dev = crtc->base.dev;
5703 struct drm_i915_private *dev_priv = dev->dev_private;
5704 u32 dpll;
5705 struct dpll *clock = &crtc->config.dpll;
5706
5707 i9xx_update_pll_dividers(crtc, reduced_clock);
5708
5709 dpll = DPLL_VGA_MODE_DIS;
5710
5711 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5712 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5713 } else {
5714 if (clock->p1 == 2)
5715 dpll |= PLL_P1_DIVIDE_BY_TWO;
5716 else
5717 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5718 if (clock->p2 == 4)
5719 dpll |= PLL_P2_DIVIDE_BY_4;
5720 }
5721
5722 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5723 dpll |= DPLL_DVO_2X_MODE;
5724
5725 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5726 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5727 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5728 else
5729 dpll |= PLL_REF_INPUT_DREFCLK;
5730
5731 dpll |= DPLL_VCO_ENABLE;
5732 crtc->config.dpll_hw_state.dpll = dpll;
5733 }
5734
5735 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5736 {
5737 struct drm_device *dev = intel_crtc->base.dev;
5738 struct drm_i915_private *dev_priv = dev->dev_private;
5739 enum pipe pipe = intel_crtc->pipe;
5740 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5741 struct drm_display_mode *adjusted_mode =
5742 &intel_crtc->config.adjusted_mode;
5743 uint32_t crtc_vtotal, crtc_vblank_end;
5744 int vsyncshift = 0;
5745
5746 /* We need to be careful not to changed the adjusted mode, for otherwise
5747 * the hw state checker will get angry at the mismatch. */
5748 crtc_vtotal = adjusted_mode->crtc_vtotal;
5749 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5750
5751 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5752 /* the chip adds 2 halflines automatically */
5753 crtc_vtotal -= 1;
5754 crtc_vblank_end -= 1;
5755
5756 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5757 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5758 else
5759 vsyncshift = adjusted_mode->crtc_hsync_start -
5760 adjusted_mode->crtc_htotal / 2;
5761 if (vsyncshift < 0)
5762 vsyncshift += adjusted_mode->crtc_htotal;
5763 }
5764
5765 if (INTEL_INFO(dev)->gen > 3)
5766 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5767
5768 I915_WRITE(HTOTAL(cpu_transcoder),
5769 (adjusted_mode->crtc_hdisplay - 1) |
5770 ((adjusted_mode->crtc_htotal - 1) << 16));
5771 I915_WRITE(HBLANK(cpu_transcoder),
5772 (adjusted_mode->crtc_hblank_start - 1) |
5773 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5774 I915_WRITE(HSYNC(cpu_transcoder),
5775 (adjusted_mode->crtc_hsync_start - 1) |
5776 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5777
5778 I915_WRITE(VTOTAL(cpu_transcoder),
5779 (adjusted_mode->crtc_vdisplay - 1) |
5780 ((crtc_vtotal - 1) << 16));
5781 I915_WRITE(VBLANK(cpu_transcoder),
5782 (adjusted_mode->crtc_vblank_start - 1) |
5783 ((crtc_vblank_end - 1) << 16));
5784 I915_WRITE(VSYNC(cpu_transcoder),
5785 (adjusted_mode->crtc_vsync_start - 1) |
5786 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5787
5788 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5789 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5790 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5791 * bits. */
5792 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5793 (pipe == PIPE_B || pipe == PIPE_C))
5794 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5795
5796 /* pipesrc controls the size that is scaled from, which should
5797 * always be the user's requested size.
5798 */
5799 I915_WRITE(PIPESRC(pipe),
5800 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5801 (intel_crtc->config.pipe_src_h - 1));
5802 }
5803
5804 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5805 struct intel_crtc_config *pipe_config)
5806 {
5807 struct drm_device *dev = crtc->base.dev;
5808 struct drm_i915_private *dev_priv = dev->dev_private;
5809 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5810 uint32_t tmp;
5811
5812 tmp = I915_READ(HTOTAL(cpu_transcoder));
5813 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5814 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5815 tmp = I915_READ(HBLANK(cpu_transcoder));
5816 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5817 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5818 tmp = I915_READ(HSYNC(cpu_transcoder));
5819 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5820 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5821
5822 tmp = I915_READ(VTOTAL(cpu_transcoder));
5823 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5824 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5825 tmp = I915_READ(VBLANK(cpu_transcoder));
5826 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5827 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5828 tmp = I915_READ(VSYNC(cpu_transcoder));
5829 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5830 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5831
5832 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5833 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5834 pipe_config->adjusted_mode.crtc_vtotal += 1;
5835 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5836 }
5837
5838 tmp = I915_READ(PIPESRC(crtc->pipe));
5839 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5840 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5841
5842 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5843 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5844 }
5845
5846 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5847 struct intel_crtc_config *pipe_config)
5848 {
5849 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5850 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5851 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5852 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5853
5854 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5855 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5856 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5857 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5858
5859 mode->flags = pipe_config->adjusted_mode.flags;
5860
5861 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5862 mode->flags |= pipe_config->adjusted_mode.flags;
5863 }
5864
5865 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5866 {
5867 struct drm_device *dev = intel_crtc->base.dev;
5868 struct drm_i915_private *dev_priv = dev->dev_private;
5869 uint32_t pipeconf;
5870
5871 pipeconf = 0;
5872
5873 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5874 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5875 pipeconf |= PIPECONF_ENABLE;
5876
5877 if (intel_crtc->config.double_wide)
5878 pipeconf |= PIPECONF_DOUBLE_WIDE;
5879
5880 /* only g4x and later have fancy bpc/dither controls */
5881 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5882 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5883 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5884 pipeconf |= PIPECONF_DITHER_EN |
5885 PIPECONF_DITHER_TYPE_SP;
5886
5887 switch (intel_crtc->config.pipe_bpp) {
5888 case 18:
5889 pipeconf |= PIPECONF_6BPC;
5890 break;
5891 case 24:
5892 pipeconf |= PIPECONF_8BPC;
5893 break;
5894 case 30:
5895 pipeconf |= PIPECONF_10BPC;
5896 break;
5897 default:
5898 /* Case prevented by intel_choose_pipe_bpp_dither. */
5899 BUG();
5900 }
5901 }
5902
5903 if (HAS_PIPE_CXSR(dev)) {
5904 if (intel_crtc->lowfreq_avail) {
5905 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5906 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5907 } else {
5908 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5909 }
5910 }
5911
5912 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5913 if (INTEL_INFO(dev)->gen < 4 ||
5914 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5915 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5916 else
5917 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5918 } else
5919 pipeconf |= PIPECONF_PROGRESSIVE;
5920
5921 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5922 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5923
5924 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5925 POSTING_READ(PIPECONF(intel_crtc->pipe));
5926 }
5927
5928 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5929 int x, int y,
5930 struct drm_framebuffer *fb)
5931 {
5932 struct drm_device *dev = crtc->dev;
5933 struct drm_i915_private *dev_priv = dev->dev_private;
5934 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5935 int refclk, num_connectors = 0;
5936 intel_clock_t clock, reduced_clock;
5937 bool ok, has_reduced_clock = false;
5938 bool is_lvds = false, is_dsi = false;
5939 struct intel_encoder *encoder;
5940 const intel_limit_t *limit;
5941
5942 for_each_encoder_on_crtc(dev, crtc, encoder) {
5943 switch (encoder->type) {
5944 case INTEL_OUTPUT_LVDS:
5945 is_lvds = true;
5946 break;
5947 case INTEL_OUTPUT_DSI:
5948 is_dsi = true;
5949 break;
5950 }
5951
5952 num_connectors++;
5953 }
5954
5955 if (is_dsi)
5956 return 0;
5957
5958 if (!intel_crtc->config.clock_set) {
5959 refclk = i9xx_get_refclk(crtc, num_connectors);
5960
5961 /*
5962 * Returns a set of divisors for the desired target clock with
5963 * the given refclk, or FALSE. The returned values represent
5964 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5965 * 2) / p1 / p2.
5966 */
5967 limit = intel_limit(crtc, refclk);
5968 ok = dev_priv->display.find_dpll(limit, crtc,
5969 intel_crtc->config.port_clock,
5970 refclk, NULL, &clock);
5971 if (!ok) {
5972 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5973 return -EINVAL;
5974 }
5975
5976 if (is_lvds && dev_priv->lvds_downclock_avail) {
5977 /*
5978 * Ensure we match the reduced clock's P to the target
5979 * clock. If the clocks don't match, we can't switch
5980 * the display clock by using the FP0/FP1. In such case
5981 * we will disable the LVDS downclock feature.
5982 */
5983 has_reduced_clock =
5984 dev_priv->display.find_dpll(limit, crtc,
5985 dev_priv->lvds_downclock,
5986 refclk, &clock,
5987 &reduced_clock);
5988 }
5989 /* Compat-code for transition, will disappear. */
5990 intel_crtc->config.dpll.n = clock.n;
5991 intel_crtc->config.dpll.m1 = clock.m1;
5992 intel_crtc->config.dpll.m2 = clock.m2;
5993 intel_crtc->config.dpll.p1 = clock.p1;
5994 intel_crtc->config.dpll.p2 = clock.p2;
5995 }
5996
5997 if (IS_GEN2(dev)) {
5998 i8xx_update_pll(intel_crtc,
5999 has_reduced_clock ? &reduced_clock : NULL,
6000 num_connectors);
6001 } else if (IS_CHERRYVIEW(dev)) {
6002 chv_update_pll(intel_crtc);
6003 } else if (IS_VALLEYVIEW(dev)) {
6004 vlv_update_pll(intel_crtc);
6005 } else {
6006 i9xx_update_pll(intel_crtc,
6007 has_reduced_clock ? &reduced_clock : NULL,
6008 num_connectors);
6009 }
6010
6011 return 0;
6012 }
6013
6014 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6015 struct intel_crtc_config *pipe_config)
6016 {
6017 struct drm_device *dev = crtc->base.dev;
6018 struct drm_i915_private *dev_priv = dev->dev_private;
6019 uint32_t tmp;
6020
6021 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6022 return;
6023
6024 tmp = I915_READ(PFIT_CONTROL);
6025 if (!(tmp & PFIT_ENABLE))
6026 return;
6027
6028 /* Check whether the pfit is attached to our pipe. */
6029 if (INTEL_INFO(dev)->gen < 4) {
6030 if (crtc->pipe != PIPE_B)
6031 return;
6032 } else {
6033 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6034 return;
6035 }
6036
6037 pipe_config->gmch_pfit.control = tmp;
6038 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6039 if (INTEL_INFO(dev)->gen < 5)
6040 pipe_config->gmch_pfit.lvds_border_bits =
6041 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6042 }
6043
6044 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6045 struct intel_crtc_config *pipe_config)
6046 {
6047 struct drm_device *dev = crtc->base.dev;
6048 struct drm_i915_private *dev_priv = dev->dev_private;
6049 int pipe = pipe_config->cpu_transcoder;
6050 intel_clock_t clock;
6051 u32 mdiv;
6052 int refclk = 100000;
6053
6054 mutex_lock(&dev_priv->dpio_lock);
6055 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6056 mutex_unlock(&dev_priv->dpio_lock);
6057
6058 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6059 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6060 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6061 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6062 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6063
6064 vlv_clock(refclk, &clock);
6065
6066 /* clock.dot is the fast clock */
6067 pipe_config->port_clock = clock.dot / 5;
6068 }
6069
6070 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6071 struct intel_plane_config *plane_config)
6072 {
6073 struct drm_device *dev = crtc->base.dev;
6074 struct drm_i915_private *dev_priv = dev->dev_private;
6075 u32 val, base, offset;
6076 int pipe = crtc->pipe, plane = crtc->plane;
6077 int fourcc, pixel_format;
6078 int aligned_height;
6079
6080 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6081 if (!crtc->base.primary->fb) {
6082 DRM_DEBUG_KMS("failed to alloc fb\n");
6083 return;
6084 }
6085
6086 val = I915_READ(DSPCNTR(plane));
6087
6088 if (INTEL_INFO(dev)->gen >= 4)
6089 if (val & DISPPLANE_TILED)
6090 plane_config->tiled = true;
6091
6092 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6093 fourcc = intel_format_to_fourcc(pixel_format);
6094 crtc->base.primary->fb->pixel_format = fourcc;
6095 crtc->base.primary->fb->bits_per_pixel =
6096 drm_format_plane_cpp(fourcc, 0) * 8;
6097
6098 if (INTEL_INFO(dev)->gen >= 4) {
6099 if (plane_config->tiled)
6100 offset = I915_READ(DSPTILEOFF(plane));
6101 else
6102 offset = I915_READ(DSPLINOFF(plane));
6103 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6104 } else {
6105 base = I915_READ(DSPADDR(plane));
6106 }
6107 plane_config->base = base;
6108
6109 val = I915_READ(PIPESRC(pipe));
6110 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6111 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6112
6113 val = I915_READ(DSPSTRIDE(pipe));
6114 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6115
6116 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6117 plane_config->tiled);
6118
6119 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
6120 aligned_height, PAGE_SIZE);
6121
6122 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6123 pipe, plane, crtc->base.primary->fb->width,
6124 crtc->base.primary->fb->height,
6125 crtc->base.primary->fb->bits_per_pixel, base,
6126 crtc->base.primary->fb->pitches[0],
6127 plane_config->size);
6128
6129 }
6130
6131 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6132 struct intel_crtc_config *pipe_config)
6133 {
6134 struct drm_device *dev = crtc->base.dev;
6135 struct drm_i915_private *dev_priv = dev->dev_private;
6136 int pipe = pipe_config->cpu_transcoder;
6137 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6138 intel_clock_t clock;
6139 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6140 int refclk = 100000;
6141
6142 mutex_lock(&dev_priv->dpio_lock);
6143 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6144 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6145 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6146 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6147 mutex_unlock(&dev_priv->dpio_lock);
6148
6149 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6150 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6151 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6152 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6153 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6154
6155 chv_clock(refclk, &clock);
6156
6157 /* clock.dot is the fast clock */
6158 pipe_config->port_clock = clock.dot / 5;
6159 }
6160
6161 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6162 struct intel_crtc_config *pipe_config)
6163 {
6164 struct drm_device *dev = crtc->base.dev;
6165 struct drm_i915_private *dev_priv = dev->dev_private;
6166 uint32_t tmp;
6167
6168 if (!intel_display_power_enabled(dev_priv,
6169 POWER_DOMAIN_PIPE(crtc->pipe)))
6170 return false;
6171
6172 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6173 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6174
6175 tmp = I915_READ(PIPECONF(crtc->pipe));
6176 if (!(tmp & PIPECONF_ENABLE))
6177 return false;
6178
6179 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6180 switch (tmp & PIPECONF_BPC_MASK) {
6181 case PIPECONF_6BPC:
6182 pipe_config->pipe_bpp = 18;
6183 break;
6184 case PIPECONF_8BPC:
6185 pipe_config->pipe_bpp = 24;
6186 break;
6187 case PIPECONF_10BPC:
6188 pipe_config->pipe_bpp = 30;
6189 break;
6190 default:
6191 break;
6192 }
6193 }
6194
6195 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6196 pipe_config->limited_color_range = true;
6197
6198 if (INTEL_INFO(dev)->gen < 4)
6199 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6200
6201 intel_get_pipe_timings(crtc, pipe_config);
6202
6203 i9xx_get_pfit_config(crtc, pipe_config);
6204
6205 if (INTEL_INFO(dev)->gen >= 4) {
6206 tmp = I915_READ(DPLL_MD(crtc->pipe));
6207 pipe_config->pixel_multiplier =
6208 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6209 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6210 pipe_config->dpll_hw_state.dpll_md = tmp;
6211 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6212 tmp = I915_READ(DPLL(crtc->pipe));
6213 pipe_config->pixel_multiplier =
6214 ((tmp & SDVO_MULTIPLIER_MASK)
6215 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6216 } else {
6217 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6218 * port and will be fixed up in the encoder->get_config
6219 * function. */
6220 pipe_config->pixel_multiplier = 1;
6221 }
6222 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6223 if (!IS_VALLEYVIEW(dev)) {
6224 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6225 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6226 } else {
6227 /* Mask out read-only status bits. */
6228 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6229 DPLL_PORTC_READY_MASK |
6230 DPLL_PORTB_READY_MASK);
6231 }
6232
6233 if (IS_CHERRYVIEW(dev))
6234 chv_crtc_clock_get(crtc, pipe_config);
6235 else if (IS_VALLEYVIEW(dev))
6236 vlv_crtc_clock_get(crtc, pipe_config);
6237 else
6238 i9xx_crtc_clock_get(crtc, pipe_config);
6239
6240 return true;
6241 }
6242
6243 static void ironlake_init_pch_refclk(struct drm_device *dev)
6244 {
6245 struct drm_i915_private *dev_priv = dev->dev_private;
6246 struct drm_mode_config *mode_config = &dev->mode_config;
6247 struct intel_encoder *encoder;
6248 u32 val, final;
6249 bool has_lvds = false;
6250 bool has_cpu_edp = false;
6251 bool has_panel = false;
6252 bool has_ck505 = false;
6253 bool can_ssc = false;
6254
6255 /* We need to take the global config into account */
6256 list_for_each_entry(encoder, &mode_config->encoder_list,
6257 base.head) {
6258 switch (encoder->type) {
6259 case INTEL_OUTPUT_LVDS:
6260 has_panel = true;
6261 has_lvds = true;
6262 break;
6263 case INTEL_OUTPUT_EDP:
6264 has_panel = true;
6265 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6266 has_cpu_edp = true;
6267 break;
6268 }
6269 }
6270
6271 if (HAS_PCH_IBX(dev)) {
6272 has_ck505 = dev_priv->vbt.display_clock_mode;
6273 can_ssc = has_ck505;
6274 } else {
6275 has_ck505 = false;
6276 can_ssc = true;
6277 }
6278
6279 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6280 has_panel, has_lvds, has_ck505);
6281
6282 /* Ironlake: try to setup display ref clock before DPLL
6283 * enabling. This is only under driver's control after
6284 * PCH B stepping, previous chipset stepping should be
6285 * ignoring this setting.
6286 */
6287 val = I915_READ(PCH_DREF_CONTROL);
6288
6289 /* As we must carefully and slowly disable/enable each source in turn,
6290 * compute the final state we want first and check if we need to
6291 * make any changes at all.
6292 */
6293 final = val;
6294 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6295 if (has_ck505)
6296 final |= DREF_NONSPREAD_CK505_ENABLE;
6297 else
6298 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6299
6300 final &= ~DREF_SSC_SOURCE_MASK;
6301 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6302 final &= ~DREF_SSC1_ENABLE;
6303
6304 if (has_panel) {
6305 final |= DREF_SSC_SOURCE_ENABLE;
6306
6307 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6308 final |= DREF_SSC1_ENABLE;
6309
6310 if (has_cpu_edp) {
6311 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6312 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6313 else
6314 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6315 } else
6316 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6317 } else {
6318 final |= DREF_SSC_SOURCE_DISABLE;
6319 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6320 }
6321
6322 if (final == val)
6323 return;
6324
6325 /* Always enable nonspread source */
6326 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6327
6328 if (has_ck505)
6329 val |= DREF_NONSPREAD_CK505_ENABLE;
6330 else
6331 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6332
6333 if (has_panel) {
6334 val &= ~DREF_SSC_SOURCE_MASK;
6335 val |= DREF_SSC_SOURCE_ENABLE;
6336
6337 /* SSC must be turned on before enabling the CPU output */
6338 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6339 DRM_DEBUG_KMS("Using SSC on panel\n");
6340 val |= DREF_SSC1_ENABLE;
6341 } else
6342 val &= ~DREF_SSC1_ENABLE;
6343
6344 /* Get SSC going before enabling the outputs */
6345 I915_WRITE(PCH_DREF_CONTROL, val);
6346 POSTING_READ(PCH_DREF_CONTROL);
6347 udelay(200);
6348
6349 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6350
6351 /* Enable CPU source on CPU attached eDP */
6352 if (has_cpu_edp) {
6353 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6354 DRM_DEBUG_KMS("Using SSC on eDP\n");
6355 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6356 } else
6357 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6358 } else
6359 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6360
6361 I915_WRITE(PCH_DREF_CONTROL, val);
6362 POSTING_READ(PCH_DREF_CONTROL);
6363 udelay(200);
6364 } else {
6365 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6366
6367 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6368
6369 /* Turn off CPU output */
6370 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6371
6372 I915_WRITE(PCH_DREF_CONTROL, val);
6373 POSTING_READ(PCH_DREF_CONTROL);
6374 udelay(200);
6375
6376 /* Turn off the SSC source */
6377 val &= ~DREF_SSC_SOURCE_MASK;
6378 val |= DREF_SSC_SOURCE_DISABLE;
6379
6380 /* Turn off SSC1 */
6381 val &= ~DREF_SSC1_ENABLE;
6382
6383 I915_WRITE(PCH_DREF_CONTROL, val);
6384 POSTING_READ(PCH_DREF_CONTROL);
6385 udelay(200);
6386 }
6387
6388 BUG_ON(val != final);
6389 }
6390
6391 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6392 {
6393 uint32_t tmp;
6394
6395 tmp = I915_READ(SOUTH_CHICKEN2);
6396 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6397 I915_WRITE(SOUTH_CHICKEN2, tmp);
6398
6399 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6400 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6401 DRM_ERROR("FDI mPHY reset assert timeout\n");
6402
6403 tmp = I915_READ(SOUTH_CHICKEN2);
6404 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6405 I915_WRITE(SOUTH_CHICKEN2, tmp);
6406
6407 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6408 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6409 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6410 }
6411
6412 /* WaMPhyProgramming:hsw */
6413 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6414 {
6415 uint32_t tmp;
6416
6417 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6418 tmp &= ~(0xFF << 24);
6419 tmp |= (0x12 << 24);
6420 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6421
6422 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6423 tmp |= (1 << 11);
6424 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6425
6426 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6427 tmp |= (1 << 11);
6428 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6429
6430 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6431 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6432 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6433
6434 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6435 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6436 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6437
6438 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6439 tmp &= ~(7 << 13);
6440 tmp |= (5 << 13);
6441 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6442
6443 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6444 tmp &= ~(7 << 13);
6445 tmp |= (5 << 13);
6446 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6447
6448 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6449 tmp &= ~0xFF;
6450 tmp |= 0x1C;
6451 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6452
6453 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6454 tmp &= ~0xFF;
6455 tmp |= 0x1C;
6456 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6457
6458 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6459 tmp &= ~(0xFF << 16);
6460 tmp |= (0x1C << 16);
6461 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6462
6463 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6464 tmp &= ~(0xFF << 16);
6465 tmp |= (0x1C << 16);
6466 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6467
6468 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6469 tmp |= (1 << 27);
6470 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6471
6472 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6473 tmp |= (1 << 27);
6474 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6475
6476 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6477 tmp &= ~(0xF << 28);
6478 tmp |= (4 << 28);
6479 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6480
6481 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6482 tmp &= ~(0xF << 28);
6483 tmp |= (4 << 28);
6484 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6485 }
6486
6487 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6488 * Programming" based on the parameters passed:
6489 * - Sequence to enable CLKOUT_DP
6490 * - Sequence to enable CLKOUT_DP without spread
6491 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6492 */
6493 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6494 bool with_fdi)
6495 {
6496 struct drm_i915_private *dev_priv = dev->dev_private;
6497 uint32_t reg, tmp;
6498
6499 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6500 with_spread = true;
6501 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6502 with_fdi, "LP PCH doesn't have FDI\n"))
6503 with_fdi = false;
6504
6505 mutex_lock(&dev_priv->dpio_lock);
6506
6507 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6508 tmp &= ~SBI_SSCCTL_DISABLE;
6509 tmp |= SBI_SSCCTL_PATHALT;
6510 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6511
6512 udelay(24);
6513
6514 if (with_spread) {
6515 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6516 tmp &= ~SBI_SSCCTL_PATHALT;
6517 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6518
6519 if (with_fdi) {
6520 lpt_reset_fdi_mphy(dev_priv);
6521 lpt_program_fdi_mphy(dev_priv);
6522 }
6523 }
6524
6525 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6526 SBI_GEN0 : SBI_DBUFF0;
6527 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6528 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6529 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6530
6531 mutex_unlock(&dev_priv->dpio_lock);
6532 }
6533
6534 /* Sequence to disable CLKOUT_DP */
6535 static void lpt_disable_clkout_dp(struct drm_device *dev)
6536 {
6537 struct drm_i915_private *dev_priv = dev->dev_private;
6538 uint32_t reg, tmp;
6539
6540 mutex_lock(&dev_priv->dpio_lock);
6541
6542 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6543 SBI_GEN0 : SBI_DBUFF0;
6544 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6545 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6546 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6547
6548 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6549 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6550 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6551 tmp |= SBI_SSCCTL_PATHALT;
6552 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6553 udelay(32);
6554 }
6555 tmp |= SBI_SSCCTL_DISABLE;
6556 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6557 }
6558
6559 mutex_unlock(&dev_priv->dpio_lock);
6560 }
6561
6562 static void lpt_init_pch_refclk(struct drm_device *dev)
6563 {
6564 struct drm_mode_config *mode_config = &dev->mode_config;
6565 struct intel_encoder *encoder;
6566 bool has_vga = false;
6567
6568 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6569 switch (encoder->type) {
6570 case INTEL_OUTPUT_ANALOG:
6571 has_vga = true;
6572 break;
6573 }
6574 }
6575
6576 if (has_vga)
6577 lpt_enable_clkout_dp(dev, true, true);
6578 else
6579 lpt_disable_clkout_dp(dev);
6580 }
6581
6582 /*
6583 * Initialize reference clocks when the driver loads
6584 */
6585 void intel_init_pch_refclk(struct drm_device *dev)
6586 {
6587 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6588 ironlake_init_pch_refclk(dev);
6589 else if (HAS_PCH_LPT(dev))
6590 lpt_init_pch_refclk(dev);
6591 }
6592
6593 static int ironlake_get_refclk(struct drm_crtc *crtc)
6594 {
6595 struct drm_device *dev = crtc->dev;
6596 struct drm_i915_private *dev_priv = dev->dev_private;
6597 struct intel_encoder *encoder;
6598 int num_connectors = 0;
6599 bool is_lvds = false;
6600
6601 for_each_encoder_on_crtc(dev, crtc, encoder) {
6602 switch (encoder->type) {
6603 case INTEL_OUTPUT_LVDS:
6604 is_lvds = true;
6605 break;
6606 }
6607 num_connectors++;
6608 }
6609
6610 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6611 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6612 dev_priv->vbt.lvds_ssc_freq);
6613 return dev_priv->vbt.lvds_ssc_freq;
6614 }
6615
6616 return 120000;
6617 }
6618
6619 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6620 {
6621 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6623 int pipe = intel_crtc->pipe;
6624 uint32_t val;
6625
6626 val = 0;
6627
6628 switch (intel_crtc->config.pipe_bpp) {
6629 case 18:
6630 val |= PIPECONF_6BPC;
6631 break;
6632 case 24:
6633 val |= PIPECONF_8BPC;
6634 break;
6635 case 30:
6636 val |= PIPECONF_10BPC;
6637 break;
6638 case 36:
6639 val |= PIPECONF_12BPC;
6640 break;
6641 default:
6642 /* Case prevented by intel_choose_pipe_bpp_dither. */
6643 BUG();
6644 }
6645
6646 if (intel_crtc->config.dither)
6647 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6648
6649 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6650 val |= PIPECONF_INTERLACED_ILK;
6651 else
6652 val |= PIPECONF_PROGRESSIVE;
6653
6654 if (intel_crtc->config.limited_color_range)
6655 val |= PIPECONF_COLOR_RANGE_SELECT;
6656
6657 I915_WRITE(PIPECONF(pipe), val);
6658 POSTING_READ(PIPECONF(pipe));
6659 }
6660
6661 /*
6662 * Set up the pipe CSC unit.
6663 *
6664 * Currently only full range RGB to limited range RGB conversion
6665 * is supported, but eventually this should handle various
6666 * RGB<->YCbCr scenarios as well.
6667 */
6668 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6669 {
6670 struct drm_device *dev = crtc->dev;
6671 struct drm_i915_private *dev_priv = dev->dev_private;
6672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6673 int pipe = intel_crtc->pipe;
6674 uint16_t coeff = 0x7800; /* 1.0 */
6675
6676 /*
6677 * TODO: Check what kind of values actually come out of the pipe
6678 * with these coeff/postoff values and adjust to get the best
6679 * accuracy. Perhaps we even need to take the bpc value into
6680 * consideration.
6681 */
6682
6683 if (intel_crtc->config.limited_color_range)
6684 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6685
6686 /*
6687 * GY/GU and RY/RU should be the other way around according
6688 * to BSpec, but reality doesn't agree. Just set them up in
6689 * a way that results in the correct picture.
6690 */
6691 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6692 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6693
6694 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6695 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6696
6697 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6698 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6699
6700 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6701 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6702 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6703
6704 if (INTEL_INFO(dev)->gen > 6) {
6705 uint16_t postoff = 0;
6706
6707 if (intel_crtc->config.limited_color_range)
6708 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6709
6710 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6711 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6712 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6713
6714 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6715 } else {
6716 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6717
6718 if (intel_crtc->config.limited_color_range)
6719 mode |= CSC_BLACK_SCREEN_OFFSET;
6720
6721 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6722 }
6723 }
6724
6725 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6726 {
6727 struct drm_device *dev = crtc->dev;
6728 struct drm_i915_private *dev_priv = dev->dev_private;
6729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6730 enum pipe pipe = intel_crtc->pipe;
6731 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6732 uint32_t val;
6733
6734 val = 0;
6735
6736 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6737 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6738
6739 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6740 val |= PIPECONF_INTERLACED_ILK;
6741 else
6742 val |= PIPECONF_PROGRESSIVE;
6743
6744 I915_WRITE(PIPECONF(cpu_transcoder), val);
6745 POSTING_READ(PIPECONF(cpu_transcoder));
6746
6747 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6748 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6749
6750 if (IS_BROADWELL(dev)) {
6751 val = 0;
6752
6753 switch (intel_crtc->config.pipe_bpp) {
6754 case 18:
6755 val |= PIPEMISC_DITHER_6_BPC;
6756 break;
6757 case 24:
6758 val |= PIPEMISC_DITHER_8_BPC;
6759 break;
6760 case 30:
6761 val |= PIPEMISC_DITHER_10_BPC;
6762 break;
6763 case 36:
6764 val |= PIPEMISC_DITHER_12_BPC;
6765 break;
6766 default:
6767 /* Case prevented by pipe_config_set_bpp. */
6768 BUG();
6769 }
6770
6771 if (intel_crtc->config.dither)
6772 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6773
6774 I915_WRITE(PIPEMISC(pipe), val);
6775 }
6776 }
6777
6778 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6779 intel_clock_t *clock,
6780 bool *has_reduced_clock,
6781 intel_clock_t *reduced_clock)
6782 {
6783 struct drm_device *dev = crtc->dev;
6784 struct drm_i915_private *dev_priv = dev->dev_private;
6785 struct intel_encoder *intel_encoder;
6786 int refclk;
6787 const intel_limit_t *limit;
6788 bool ret, is_lvds = false;
6789
6790 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6791 switch (intel_encoder->type) {
6792 case INTEL_OUTPUT_LVDS:
6793 is_lvds = true;
6794 break;
6795 }
6796 }
6797
6798 refclk = ironlake_get_refclk(crtc);
6799
6800 /*
6801 * Returns a set of divisors for the desired target clock with the given
6802 * refclk, or FALSE. The returned values represent the clock equation:
6803 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6804 */
6805 limit = intel_limit(crtc, refclk);
6806 ret = dev_priv->display.find_dpll(limit, crtc,
6807 to_intel_crtc(crtc)->config.port_clock,
6808 refclk, NULL, clock);
6809 if (!ret)
6810 return false;
6811
6812 if (is_lvds && dev_priv->lvds_downclock_avail) {
6813 /*
6814 * Ensure we match the reduced clock's P to the target clock.
6815 * If the clocks don't match, we can't switch the display clock
6816 * by using the FP0/FP1. In such case we will disable the LVDS
6817 * downclock feature.
6818 */
6819 *has_reduced_clock =
6820 dev_priv->display.find_dpll(limit, crtc,
6821 dev_priv->lvds_downclock,
6822 refclk, clock,
6823 reduced_clock);
6824 }
6825
6826 return true;
6827 }
6828
6829 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6830 {
6831 /*
6832 * Account for spread spectrum to avoid
6833 * oversubscribing the link. Max center spread
6834 * is 2.5%; use 5% for safety's sake.
6835 */
6836 u32 bps = target_clock * bpp * 21 / 20;
6837 return DIV_ROUND_UP(bps, link_bw * 8);
6838 }
6839
6840 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6841 {
6842 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6843 }
6844
6845 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6846 u32 *fp,
6847 intel_clock_t *reduced_clock, u32 *fp2)
6848 {
6849 struct drm_crtc *crtc = &intel_crtc->base;
6850 struct drm_device *dev = crtc->dev;
6851 struct drm_i915_private *dev_priv = dev->dev_private;
6852 struct intel_encoder *intel_encoder;
6853 uint32_t dpll;
6854 int factor, num_connectors = 0;
6855 bool is_lvds = false, is_sdvo = false;
6856
6857 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6858 switch (intel_encoder->type) {
6859 case INTEL_OUTPUT_LVDS:
6860 is_lvds = true;
6861 break;
6862 case INTEL_OUTPUT_SDVO:
6863 case INTEL_OUTPUT_HDMI:
6864 is_sdvo = true;
6865 break;
6866 }
6867
6868 num_connectors++;
6869 }
6870
6871 /* Enable autotuning of the PLL clock (if permissible) */
6872 factor = 21;
6873 if (is_lvds) {
6874 if ((intel_panel_use_ssc(dev_priv) &&
6875 dev_priv->vbt.lvds_ssc_freq == 100000) ||
6876 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6877 factor = 25;
6878 } else if (intel_crtc->config.sdvo_tv_clock)
6879 factor = 20;
6880
6881 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6882 *fp |= FP_CB_TUNE;
6883
6884 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6885 *fp2 |= FP_CB_TUNE;
6886
6887 dpll = 0;
6888
6889 if (is_lvds)
6890 dpll |= DPLLB_MODE_LVDS;
6891 else
6892 dpll |= DPLLB_MODE_DAC_SERIAL;
6893
6894 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6895 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6896
6897 if (is_sdvo)
6898 dpll |= DPLL_SDVO_HIGH_SPEED;
6899 if (intel_crtc->config.has_dp_encoder)
6900 dpll |= DPLL_SDVO_HIGH_SPEED;
6901
6902 /* compute bitmask from p1 value */
6903 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6904 /* also FPA1 */
6905 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6906
6907 switch (intel_crtc->config.dpll.p2) {
6908 case 5:
6909 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6910 break;
6911 case 7:
6912 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6913 break;
6914 case 10:
6915 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6916 break;
6917 case 14:
6918 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6919 break;
6920 }
6921
6922 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6923 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6924 else
6925 dpll |= PLL_REF_INPUT_DREFCLK;
6926
6927 return dpll | DPLL_VCO_ENABLE;
6928 }
6929
6930 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6931 int x, int y,
6932 struct drm_framebuffer *fb)
6933 {
6934 struct drm_device *dev = crtc->dev;
6935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6936 int num_connectors = 0;
6937 intel_clock_t clock, reduced_clock;
6938 u32 dpll = 0, fp = 0, fp2 = 0;
6939 bool ok, has_reduced_clock = false;
6940 bool is_lvds = false;
6941 struct intel_encoder *encoder;
6942 struct intel_shared_dpll *pll;
6943
6944 for_each_encoder_on_crtc(dev, crtc, encoder) {
6945 switch (encoder->type) {
6946 case INTEL_OUTPUT_LVDS:
6947 is_lvds = true;
6948 break;
6949 }
6950
6951 num_connectors++;
6952 }
6953
6954 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6955 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6956
6957 ok = ironlake_compute_clocks(crtc, &clock,
6958 &has_reduced_clock, &reduced_clock);
6959 if (!ok && !intel_crtc->config.clock_set) {
6960 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6961 return -EINVAL;
6962 }
6963 /* Compat-code for transition, will disappear. */
6964 if (!intel_crtc->config.clock_set) {
6965 intel_crtc->config.dpll.n = clock.n;
6966 intel_crtc->config.dpll.m1 = clock.m1;
6967 intel_crtc->config.dpll.m2 = clock.m2;
6968 intel_crtc->config.dpll.p1 = clock.p1;
6969 intel_crtc->config.dpll.p2 = clock.p2;
6970 }
6971
6972 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6973 if (intel_crtc->config.has_pch_encoder) {
6974 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6975 if (has_reduced_clock)
6976 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6977
6978 dpll = ironlake_compute_dpll(intel_crtc,
6979 &fp, &reduced_clock,
6980 has_reduced_clock ? &fp2 : NULL);
6981
6982 intel_crtc->config.dpll_hw_state.dpll = dpll;
6983 intel_crtc->config.dpll_hw_state.fp0 = fp;
6984 if (has_reduced_clock)
6985 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6986 else
6987 intel_crtc->config.dpll_hw_state.fp1 = fp;
6988
6989 pll = intel_get_shared_dpll(intel_crtc);
6990 if (pll == NULL) {
6991 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6992 pipe_name(intel_crtc->pipe));
6993 return -EINVAL;
6994 }
6995 } else
6996 intel_put_shared_dpll(intel_crtc);
6997
6998 if (is_lvds && has_reduced_clock && i915.powersave)
6999 intel_crtc->lowfreq_avail = true;
7000 else
7001 intel_crtc->lowfreq_avail = false;
7002
7003 return 0;
7004 }
7005
7006 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7007 struct intel_link_m_n *m_n)
7008 {
7009 struct drm_device *dev = crtc->base.dev;
7010 struct drm_i915_private *dev_priv = dev->dev_private;
7011 enum pipe pipe = crtc->pipe;
7012
7013 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7014 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7015 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7016 & ~TU_SIZE_MASK;
7017 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7018 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7019 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7020 }
7021
7022 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7023 enum transcoder transcoder,
7024 struct intel_link_m_n *m_n)
7025 {
7026 struct drm_device *dev = crtc->base.dev;
7027 struct drm_i915_private *dev_priv = dev->dev_private;
7028 enum pipe pipe = crtc->pipe;
7029
7030 if (INTEL_INFO(dev)->gen >= 5) {
7031 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7032 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7033 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7034 & ~TU_SIZE_MASK;
7035 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7036 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7037 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7038 } else {
7039 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7040 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7041 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7042 & ~TU_SIZE_MASK;
7043 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7044 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7045 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7046 }
7047 }
7048
7049 void intel_dp_get_m_n(struct intel_crtc *crtc,
7050 struct intel_crtc_config *pipe_config)
7051 {
7052 if (crtc->config.has_pch_encoder)
7053 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7054 else
7055 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7056 &pipe_config->dp_m_n);
7057 }
7058
7059 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7060 struct intel_crtc_config *pipe_config)
7061 {
7062 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7063 &pipe_config->fdi_m_n);
7064 }
7065
7066 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7067 struct intel_crtc_config *pipe_config)
7068 {
7069 struct drm_device *dev = crtc->base.dev;
7070 struct drm_i915_private *dev_priv = dev->dev_private;
7071 uint32_t tmp;
7072
7073 tmp = I915_READ(PF_CTL(crtc->pipe));
7074
7075 if (tmp & PF_ENABLE) {
7076 pipe_config->pch_pfit.enabled = true;
7077 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7078 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7079
7080 /* We currently do not free assignements of panel fitters on
7081 * ivb/hsw (since we don't use the higher upscaling modes which
7082 * differentiates them) so just WARN about this case for now. */
7083 if (IS_GEN7(dev)) {
7084 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7085 PF_PIPE_SEL_IVB(crtc->pipe));
7086 }
7087 }
7088 }
7089
7090 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7091 struct intel_plane_config *plane_config)
7092 {
7093 struct drm_device *dev = crtc->base.dev;
7094 struct drm_i915_private *dev_priv = dev->dev_private;
7095 u32 val, base, offset;
7096 int pipe = crtc->pipe, plane = crtc->plane;
7097 int fourcc, pixel_format;
7098 int aligned_height;
7099
7100 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7101 if (!crtc->base.primary->fb) {
7102 DRM_DEBUG_KMS("failed to alloc fb\n");
7103 return;
7104 }
7105
7106 val = I915_READ(DSPCNTR(plane));
7107
7108 if (INTEL_INFO(dev)->gen >= 4)
7109 if (val & DISPPLANE_TILED)
7110 plane_config->tiled = true;
7111
7112 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7113 fourcc = intel_format_to_fourcc(pixel_format);
7114 crtc->base.primary->fb->pixel_format = fourcc;
7115 crtc->base.primary->fb->bits_per_pixel =
7116 drm_format_plane_cpp(fourcc, 0) * 8;
7117
7118 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7119 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7120 offset = I915_READ(DSPOFFSET(plane));
7121 } else {
7122 if (plane_config->tiled)
7123 offset = I915_READ(DSPTILEOFF(plane));
7124 else
7125 offset = I915_READ(DSPLINOFF(plane));
7126 }
7127 plane_config->base = base;
7128
7129 val = I915_READ(PIPESRC(pipe));
7130 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7131 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7132
7133 val = I915_READ(DSPSTRIDE(pipe));
7134 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7135
7136 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7137 plane_config->tiled);
7138
7139 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
7140 aligned_height, PAGE_SIZE);
7141
7142 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7143 pipe, plane, crtc->base.primary->fb->width,
7144 crtc->base.primary->fb->height,
7145 crtc->base.primary->fb->bits_per_pixel, base,
7146 crtc->base.primary->fb->pitches[0],
7147 plane_config->size);
7148 }
7149
7150 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7151 struct intel_crtc_config *pipe_config)
7152 {
7153 struct drm_device *dev = crtc->base.dev;
7154 struct drm_i915_private *dev_priv = dev->dev_private;
7155 uint32_t tmp;
7156
7157 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7158 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7159
7160 tmp = I915_READ(PIPECONF(crtc->pipe));
7161 if (!(tmp & PIPECONF_ENABLE))
7162 return false;
7163
7164 switch (tmp & PIPECONF_BPC_MASK) {
7165 case PIPECONF_6BPC:
7166 pipe_config->pipe_bpp = 18;
7167 break;
7168 case PIPECONF_8BPC:
7169 pipe_config->pipe_bpp = 24;
7170 break;
7171 case PIPECONF_10BPC:
7172 pipe_config->pipe_bpp = 30;
7173 break;
7174 case PIPECONF_12BPC:
7175 pipe_config->pipe_bpp = 36;
7176 break;
7177 default:
7178 break;
7179 }
7180
7181 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7182 pipe_config->limited_color_range = true;
7183
7184 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7185 struct intel_shared_dpll *pll;
7186
7187 pipe_config->has_pch_encoder = true;
7188
7189 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7190 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7191 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7192
7193 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7194
7195 if (HAS_PCH_IBX(dev_priv->dev)) {
7196 pipe_config->shared_dpll =
7197 (enum intel_dpll_id) crtc->pipe;
7198 } else {
7199 tmp = I915_READ(PCH_DPLL_SEL);
7200 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7201 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7202 else
7203 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7204 }
7205
7206 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7207
7208 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7209 &pipe_config->dpll_hw_state));
7210
7211 tmp = pipe_config->dpll_hw_state.dpll;
7212 pipe_config->pixel_multiplier =
7213 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7214 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7215
7216 ironlake_pch_clock_get(crtc, pipe_config);
7217 } else {
7218 pipe_config->pixel_multiplier = 1;
7219 }
7220
7221 intel_get_pipe_timings(crtc, pipe_config);
7222
7223 ironlake_get_pfit_config(crtc, pipe_config);
7224
7225 return true;
7226 }
7227
7228 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7229 {
7230 struct drm_device *dev = dev_priv->dev;
7231 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
7232 struct intel_crtc *crtc;
7233
7234 for_each_intel_crtc(dev, crtc)
7235 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7236 pipe_name(crtc->pipe));
7237
7238 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7239 WARN(plls->spll_refcount, "SPLL enabled\n");
7240 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
7241 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
7242 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7243 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7244 "CPU PWM1 enabled\n");
7245 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7246 "CPU PWM2 enabled\n");
7247 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7248 "PCH PWM1 enabled\n");
7249 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7250 "Utility pin enabled\n");
7251 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7252
7253 /*
7254 * In theory we can still leave IRQs enabled, as long as only the HPD
7255 * interrupts remain enabled. We used to check for that, but since it's
7256 * gen-specific and since we only disable LCPLL after we fully disable
7257 * the interrupts, the check below should be enough.
7258 */
7259 WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
7260 }
7261
7262 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7263 {
7264 struct drm_device *dev = dev_priv->dev;
7265
7266 if (IS_HASWELL(dev)) {
7267 mutex_lock(&dev_priv->rps.hw_lock);
7268 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7269 val))
7270 DRM_ERROR("Failed to disable D_COMP\n");
7271 mutex_unlock(&dev_priv->rps.hw_lock);
7272 } else {
7273 I915_WRITE(D_COMP, val);
7274 }
7275 POSTING_READ(D_COMP);
7276 }
7277
7278 /*
7279 * This function implements pieces of two sequences from BSpec:
7280 * - Sequence for display software to disable LCPLL
7281 * - Sequence for display software to allow package C8+
7282 * The steps implemented here are just the steps that actually touch the LCPLL
7283 * register. Callers should take care of disabling all the display engine
7284 * functions, doing the mode unset, fixing interrupts, etc.
7285 */
7286 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7287 bool switch_to_fclk, bool allow_power_down)
7288 {
7289 uint32_t val;
7290
7291 assert_can_disable_lcpll(dev_priv);
7292
7293 val = I915_READ(LCPLL_CTL);
7294
7295 if (switch_to_fclk) {
7296 val |= LCPLL_CD_SOURCE_FCLK;
7297 I915_WRITE(LCPLL_CTL, val);
7298
7299 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7300 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7301 DRM_ERROR("Switching to FCLK failed\n");
7302
7303 val = I915_READ(LCPLL_CTL);
7304 }
7305
7306 val |= LCPLL_PLL_DISABLE;
7307 I915_WRITE(LCPLL_CTL, val);
7308 POSTING_READ(LCPLL_CTL);
7309
7310 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7311 DRM_ERROR("LCPLL still locked\n");
7312
7313 val = I915_READ(D_COMP);
7314 val |= D_COMP_COMP_DISABLE;
7315 hsw_write_dcomp(dev_priv, val);
7316 ndelay(100);
7317
7318 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
7319 DRM_ERROR("D_COMP RCOMP still in progress\n");
7320
7321 if (allow_power_down) {
7322 val = I915_READ(LCPLL_CTL);
7323 val |= LCPLL_POWER_DOWN_ALLOW;
7324 I915_WRITE(LCPLL_CTL, val);
7325 POSTING_READ(LCPLL_CTL);
7326 }
7327 }
7328
7329 /*
7330 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7331 * source.
7332 */
7333 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7334 {
7335 uint32_t val;
7336 unsigned long irqflags;
7337
7338 val = I915_READ(LCPLL_CTL);
7339
7340 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7341 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7342 return;
7343
7344 /*
7345 * Make sure we're not on PC8 state before disabling PC8, otherwise
7346 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7347 *
7348 * The other problem is that hsw_restore_lcpll() is called as part of
7349 * the runtime PM resume sequence, so we can't just call
7350 * gen6_gt_force_wake_get() because that function calls
7351 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7352 * while we are on the resume sequence. So to solve this problem we have
7353 * to call special forcewake code that doesn't touch runtime PM and
7354 * doesn't enable the forcewake delayed work.
7355 */
7356 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7357 if (dev_priv->uncore.forcewake_count++ == 0)
7358 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7359 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7360
7361 if (val & LCPLL_POWER_DOWN_ALLOW) {
7362 val &= ~LCPLL_POWER_DOWN_ALLOW;
7363 I915_WRITE(LCPLL_CTL, val);
7364 POSTING_READ(LCPLL_CTL);
7365 }
7366
7367 val = I915_READ(D_COMP);
7368 val |= D_COMP_COMP_FORCE;
7369 val &= ~D_COMP_COMP_DISABLE;
7370 hsw_write_dcomp(dev_priv, val);
7371
7372 val = I915_READ(LCPLL_CTL);
7373 val &= ~LCPLL_PLL_DISABLE;
7374 I915_WRITE(LCPLL_CTL, val);
7375
7376 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7377 DRM_ERROR("LCPLL not locked yet\n");
7378
7379 if (val & LCPLL_CD_SOURCE_FCLK) {
7380 val = I915_READ(LCPLL_CTL);
7381 val &= ~LCPLL_CD_SOURCE_FCLK;
7382 I915_WRITE(LCPLL_CTL, val);
7383
7384 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7385 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7386 DRM_ERROR("Switching back to LCPLL failed\n");
7387 }
7388
7389 /* See the big comment above. */
7390 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7391 if (--dev_priv->uncore.forcewake_count == 0)
7392 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7393 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7394 }
7395
7396 /*
7397 * Package states C8 and deeper are really deep PC states that can only be
7398 * reached when all the devices on the system allow it, so even if the graphics
7399 * device allows PC8+, it doesn't mean the system will actually get to these
7400 * states. Our driver only allows PC8+ when going into runtime PM.
7401 *
7402 * The requirements for PC8+ are that all the outputs are disabled, the power
7403 * well is disabled and most interrupts are disabled, and these are also
7404 * requirements for runtime PM. When these conditions are met, we manually do
7405 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7406 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7407 * hang the machine.
7408 *
7409 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7410 * the state of some registers, so when we come back from PC8+ we need to
7411 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7412 * need to take care of the registers kept by RC6. Notice that this happens even
7413 * if we don't put the device in PCI D3 state (which is what currently happens
7414 * because of the runtime PM support).
7415 *
7416 * For more, read "Display Sequences for Package C8" on the hardware
7417 * documentation.
7418 */
7419 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7420 {
7421 struct drm_device *dev = dev_priv->dev;
7422 uint32_t val;
7423
7424 DRM_DEBUG_KMS("Enabling package C8+\n");
7425
7426 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7427 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7428 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7429 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7430 }
7431
7432 lpt_disable_clkout_dp(dev);
7433 hsw_disable_lcpll(dev_priv, true, true);
7434 }
7435
7436 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7437 {
7438 struct drm_device *dev = dev_priv->dev;
7439 uint32_t val;
7440
7441 DRM_DEBUG_KMS("Disabling package C8+\n");
7442
7443 hsw_restore_lcpll(dev_priv);
7444 lpt_init_pch_refclk(dev);
7445
7446 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7447 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7448 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7449 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7450 }
7451
7452 intel_prepare_ddi(dev);
7453 }
7454
7455 static void snb_modeset_global_resources(struct drm_device *dev)
7456 {
7457 modeset_update_crtc_power_domains(dev);
7458 }
7459
7460 static void haswell_modeset_global_resources(struct drm_device *dev)
7461 {
7462 modeset_update_crtc_power_domains(dev);
7463 }
7464
7465 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7466 int x, int y,
7467 struct drm_framebuffer *fb)
7468 {
7469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7470
7471 if (!intel_ddi_pll_select(intel_crtc))
7472 return -EINVAL;
7473 intel_ddi_pll_enable(intel_crtc);
7474
7475 intel_crtc->lowfreq_avail = false;
7476
7477 return 0;
7478 }
7479
7480 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7481 struct intel_crtc_config *pipe_config)
7482 {
7483 struct drm_device *dev = crtc->base.dev;
7484 struct drm_i915_private *dev_priv = dev->dev_private;
7485 enum intel_display_power_domain pfit_domain;
7486 uint32_t tmp;
7487
7488 if (!intel_display_power_enabled(dev_priv,
7489 POWER_DOMAIN_PIPE(crtc->pipe)))
7490 return false;
7491
7492 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7493 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7494
7495 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7496 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7497 enum pipe trans_edp_pipe;
7498 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7499 default:
7500 WARN(1, "unknown pipe linked to edp transcoder\n");
7501 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7502 case TRANS_DDI_EDP_INPUT_A_ON:
7503 trans_edp_pipe = PIPE_A;
7504 break;
7505 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7506 trans_edp_pipe = PIPE_B;
7507 break;
7508 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7509 trans_edp_pipe = PIPE_C;
7510 break;
7511 }
7512
7513 if (trans_edp_pipe == crtc->pipe)
7514 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7515 }
7516
7517 if (!intel_display_power_enabled(dev_priv,
7518 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7519 return false;
7520
7521 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7522 if (!(tmp & PIPECONF_ENABLE))
7523 return false;
7524
7525 /*
7526 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7527 * DDI E. So just check whether this pipe is wired to DDI E and whether
7528 * the PCH transcoder is on.
7529 */
7530 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7531 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7532 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7533 pipe_config->has_pch_encoder = true;
7534
7535 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7536 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7537 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7538
7539 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7540 }
7541
7542 intel_get_pipe_timings(crtc, pipe_config);
7543
7544 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7545 if (intel_display_power_enabled(dev_priv, pfit_domain))
7546 ironlake_get_pfit_config(crtc, pipe_config);
7547
7548 if (IS_HASWELL(dev))
7549 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7550 (I915_READ(IPS_CTL) & IPS_ENABLE);
7551
7552 pipe_config->pixel_multiplier = 1;
7553
7554 return true;
7555 }
7556
7557 static struct {
7558 int clock;
7559 u32 config;
7560 } hdmi_audio_clock[] = {
7561 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7562 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7563 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7564 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7565 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7566 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7567 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7568 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7569 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7570 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7571 };
7572
7573 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7574 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7575 {
7576 int i;
7577
7578 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7579 if (mode->clock == hdmi_audio_clock[i].clock)
7580 break;
7581 }
7582
7583 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7584 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7585 i = 1;
7586 }
7587
7588 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7589 hdmi_audio_clock[i].clock,
7590 hdmi_audio_clock[i].config);
7591
7592 return hdmi_audio_clock[i].config;
7593 }
7594
7595 static bool intel_eld_uptodate(struct drm_connector *connector,
7596 int reg_eldv, uint32_t bits_eldv,
7597 int reg_elda, uint32_t bits_elda,
7598 int reg_edid)
7599 {
7600 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7601 uint8_t *eld = connector->eld;
7602 uint32_t i;
7603
7604 i = I915_READ(reg_eldv);
7605 i &= bits_eldv;
7606
7607 if (!eld[0])
7608 return !i;
7609
7610 if (!i)
7611 return false;
7612
7613 i = I915_READ(reg_elda);
7614 i &= ~bits_elda;
7615 I915_WRITE(reg_elda, i);
7616
7617 for (i = 0; i < eld[2]; i++)
7618 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7619 return false;
7620
7621 return true;
7622 }
7623
7624 static void g4x_write_eld(struct drm_connector *connector,
7625 struct drm_crtc *crtc,
7626 struct drm_display_mode *mode)
7627 {
7628 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7629 uint8_t *eld = connector->eld;
7630 uint32_t eldv;
7631 uint32_t len;
7632 uint32_t i;
7633
7634 i = I915_READ(G4X_AUD_VID_DID);
7635
7636 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7637 eldv = G4X_ELDV_DEVCL_DEVBLC;
7638 else
7639 eldv = G4X_ELDV_DEVCTG;
7640
7641 if (intel_eld_uptodate(connector,
7642 G4X_AUD_CNTL_ST, eldv,
7643 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7644 G4X_HDMIW_HDMIEDID))
7645 return;
7646
7647 i = I915_READ(G4X_AUD_CNTL_ST);
7648 i &= ~(eldv | G4X_ELD_ADDR);
7649 len = (i >> 9) & 0x1f; /* ELD buffer size */
7650 I915_WRITE(G4X_AUD_CNTL_ST, i);
7651
7652 if (!eld[0])
7653 return;
7654
7655 len = min_t(uint8_t, eld[2], len);
7656 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7657 for (i = 0; i < len; i++)
7658 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7659
7660 i = I915_READ(G4X_AUD_CNTL_ST);
7661 i |= eldv;
7662 I915_WRITE(G4X_AUD_CNTL_ST, i);
7663 }
7664
7665 static void haswell_write_eld(struct drm_connector *connector,
7666 struct drm_crtc *crtc,
7667 struct drm_display_mode *mode)
7668 {
7669 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7670 uint8_t *eld = connector->eld;
7671 uint32_t eldv;
7672 uint32_t i;
7673 int len;
7674 int pipe = to_intel_crtc(crtc)->pipe;
7675 int tmp;
7676
7677 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7678 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7679 int aud_config = HSW_AUD_CFG(pipe);
7680 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7681
7682 /* Audio output enable */
7683 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7684 tmp = I915_READ(aud_cntrl_st2);
7685 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7686 I915_WRITE(aud_cntrl_st2, tmp);
7687 POSTING_READ(aud_cntrl_st2);
7688
7689 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7690
7691 /* Set ELD valid state */
7692 tmp = I915_READ(aud_cntrl_st2);
7693 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7694 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7695 I915_WRITE(aud_cntrl_st2, tmp);
7696 tmp = I915_READ(aud_cntrl_st2);
7697 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7698
7699 /* Enable HDMI mode */
7700 tmp = I915_READ(aud_config);
7701 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7702 /* clear N_programing_enable and N_value_index */
7703 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7704 I915_WRITE(aud_config, tmp);
7705
7706 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7707
7708 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7709
7710 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7711 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7712 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7713 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7714 } else {
7715 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7716 }
7717
7718 if (intel_eld_uptodate(connector,
7719 aud_cntrl_st2, eldv,
7720 aud_cntl_st, IBX_ELD_ADDRESS,
7721 hdmiw_hdmiedid))
7722 return;
7723
7724 i = I915_READ(aud_cntrl_st2);
7725 i &= ~eldv;
7726 I915_WRITE(aud_cntrl_st2, i);
7727
7728 if (!eld[0])
7729 return;
7730
7731 i = I915_READ(aud_cntl_st);
7732 i &= ~IBX_ELD_ADDRESS;
7733 I915_WRITE(aud_cntl_st, i);
7734 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7735 DRM_DEBUG_DRIVER("port num:%d\n", i);
7736
7737 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7738 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7739 for (i = 0; i < len; i++)
7740 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7741
7742 i = I915_READ(aud_cntrl_st2);
7743 i |= eldv;
7744 I915_WRITE(aud_cntrl_st2, i);
7745
7746 }
7747
7748 static void ironlake_write_eld(struct drm_connector *connector,
7749 struct drm_crtc *crtc,
7750 struct drm_display_mode *mode)
7751 {
7752 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7753 uint8_t *eld = connector->eld;
7754 uint32_t eldv;
7755 uint32_t i;
7756 int len;
7757 int hdmiw_hdmiedid;
7758 int aud_config;
7759 int aud_cntl_st;
7760 int aud_cntrl_st2;
7761 int pipe = to_intel_crtc(crtc)->pipe;
7762
7763 if (HAS_PCH_IBX(connector->dev)) {
7764 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7765 aud_config = IBX_AUD_CFG(pipe);
7766 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7767 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7768 } else if (IS_VALLEYVIEW(connector->dev)) {
7769 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7770 aud_config = VLV_AUD_CFG(pipe);
7771 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7772 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7773 } else {
7774 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7775 aud_config = CPT_AUD_CFG(pipe);
7776 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7777 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7778 }
7779
7780 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7781
7782 if (IS_VALLEYVIEW(connector->dev)) {
7783 struct intel_encoder *intel_encoder;
7784 struct intel_digital_port *intel_dig_port;
7785
7786 intel_encoder = intel_attached_encoder(connector);
7787 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7788 i = intel_dig_port->port;
7789 } else {
7790 i = I915_READ(aud_cntl_st);
7791 i = (i >> 29) & DIP_PORT_SEL_MASK;
7792 /* DIP_Port_Select, 0x1 = PortB */
7793 }
7794
7795 if (!i) {
7796 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7797 /* operate blindly on all ports */
7798 eldv = IBX_ELD_VALIDB;
7799 eldv |= IBX_ELD_VALIDB << 4;
7800 eldv |= IBX_ELD_VALIDB << 8;
7801 } else {
7802 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7803 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7804 }
7805
7806 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7807 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7808 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7809 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7810 } else {
7811 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7812 }
7813
7814 if (intel_eld_uptodate(connector,
7815 aud_cntrl_st2, eldv,
7816 aud_cntl_st, IBX_ELD_ADDRESS,
7817 hdmiw_hdmiedid))
7818 return;
7819
7820 i = I915_READ(aud_cntrl_st2);
7821 i &= ~eldv;
7822 I915_WRITE(aud_cntrl_st2, i);
7823
7824 if (!eld[0])
7825 return;
7826
7827 i = I915_READ(aud_cntl_st);
7828 i &= ~IBX_ELD_ADDRESS;
7829 I915_WRITE(aud_cntl_st, i);
7830
7831 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7832 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7833 for (i = 0; i < len; i++)
7834 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7835
7836 i = I915_READ(aud_cntrl_st2);
7837 i |= eldv;
7838 I915_WRITE(aud_cntrl_st2, i);
7839 }
7840
7841 void intel_write_eld(struct drm_encoder *encoder,
7842 struct drm_display_mode *mode)
7843 {
7844 struct drm_crtc *crtc = encoder->crtc;
7845 struct drm_connector *connector;
7846 struct drm_device *dev = encoder->dev;
7847 struct drm_i915_private *dev_priv = dev->dev_private;
7848
7849 connector = drm_select_eld(encoder, mode);
7850 if (!connector)
7851 return;
7852
7853 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7854 connector->base.id,
7855 connector->name,
7856 connector->encoder->base.id,
7857 connector->encoder->name);
7858
7859 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7860
7861 if (dev_priv->display.write_eld)
7862 dev_priv->display.write_eld(connector, crtc, mode);
7863 }
7864
7865 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7866 {
7867 struct drm_device *dev = crtc->dev;
7868 struct drm_i915_private *dev_priv = dev->dev_private;
7869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7870 uint32_t cntl;
7871
7872 if (base != intel_crtc->cursor_base) {
7873 /* On these chipsets we can only modify the base whilst
7874 * the cursor is disabled.
7875 */
7876 if (intel_crtc->cursor_cntl) {
7877 I915_WRITE(_CURACNTR, 0);
7878 POSTING_READ(_CURACNTR);
7879 intel_crtc->cursor_cntl = 0;
7880 }
7881
7882 I915_WRITE(_CURABASE, base);
7883 POSTING_READ(_CURABASE);
7884 }
7885
7886 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7887 cntl = 0;
7888 if (base)
7889 cntl = (CURSOR_ENABLE |
7890 CURSOR_GAMMA_ENABLE |
7891 CURSOR_FORMAT_ARGB);
7892 if (intel_crtc->cursor_cntl != cntl) {
7893 I915_WRITE(_CURACNTR, cntl);
7894 POSTING_READ(_CURACNTR);
7895 intel_crtc->cursor_cntl = cntl;
7896 }
7897 }
7898
7899 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7900 {
7901 struct drm_device *dev = crtc->dev;
7902 struct drm_i915_private *dev_priv = dev->dev_private;
7903 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7904 int pipe = intel_crtc->pipe;
7905 uint32_t cntl;
7906
7907 cntl = 0;
7908 if (base) {
7909 cntl = MCURSOR_GAMMA_ENABLE;
7910 switch (intel_crtc->cursor_width) {
7911 case 64:
7912 cntl |= CURSOR_MODE_64_ARGB_AX;
7913 break;
7914 case 128:
7915 cntl |= CURSOR_MODE_128_ARGB_AX;
7916 break;
7917 case 256:
7918 cntl |= CURSOR_MODE_256_ARGB_AX;
7919 break;
7920 default:
7921 WARN_ON(1);
7922 return;
7923 }
7924 cntl |= pipe << 28; /* Connect to correct pipe */
7925 }
7926 if (intel_crtc->cursor_cntl != cntl) {
7927 I915_WRITE(CURCNTR(pipe), cntl);
7928 POSTING_READ(CURCNTR(pipe));
7929 intel_crtc->cursor_cntl = cntl;
7930 }
7931
7932 /* and commit changes on next vblank */
7933 I915_WRITE(CURBASE(pipe), base);
7934 POSTING_READ(CURBASE(pipe));
7935 }
7936
7937 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7938 {
7939 struct drm_device *dev = crtc->dev;
7940 struct drm_i915_private *dev_priv = dev->dev_private;
7941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7942 int pipe = intel_crtc->pipe;
7943 uint32_t cntl;
7944
7945 cntl = 0;
7946 if (base) {
7947 cntl = MCURSOR_GAMMA_ENABLE;
7948 switch (intel_crtc->cursor_width) {
7949 case 64:
7950 cntl |= CURSOR_MODE_64_ARGB_AX;
7951 break;
7952 case 128:
7953 cntl |= CURSOR_MODE_128_ARGB_AX;
7954 break;
7955 case 256:
7956 cntl |= CURSOR_MODE_256_ARGB_AX;
7957 break;
7958 default:
7959 WARN_ON(1);
7960 return;
7961 }
7962 }
7963 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
7964 cntl |= CURSOR_PIPE_CSC_ENABLE;
7965
7966 if (intel_crtc->cursor_cntl != cntl) {
7967 I915_WRITE(CURCNTR(pipe), cntl);
7968 POSTING_READ(CURCNTR(pipe));
7969 intel_crtc->cursor_cntl = cntl;
7970 }
7971
7972 /* and commit changes on next vblank */
7973 I915_WRITE(CURBASE(pipe), base);
7974 POSTING_READ(CURBASE(pipe));
7975 }
7976
7977 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7978 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7979 bool on)
7980 {
7981 struct drm_device *dev = crtc->dev;
7982 struct drm_i915_private *dev_priv = dev->dev_private;
7983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7984 int pipe = intel_crtc->pipe;
7985 int x = intel_crtc->cursor_x;
7986 int y = intel_crtc->cursor_y;
7987 u32 base = 0, pos = 0;
7988
7989 if (on)
7990 base = intel_crtc->cursor_addr;
7991
7992 if (x >= intel_crtc->config.pipe_src_w)
7993 base = 0;
7994
7995 if (y >= intel_crtc->config.pipe_src_h)
7996 base = 0;
7997
7998 if (x < 0) {
7999 if (x + intel_crtc->cursor_width <= 0)
8000 base = 0;
8001
8002 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8003 x = -x;
8004 }
8005 pos |= x << CURSOR_X_SHIFT;
8006
8007 if (y < 0) {
8008 if (y + intel_crtc->cursor_height <= 0)
8009 base = 0;
8010
8011 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8012 y = -y;
8013 }
8014 pos |= y << CURSOR_Y_SHIFT;
8015
8016 if (base == 0 && intel_crtc->cursor_base == 0)
8017 return;
8018
8019 I915_WRITE(CURPOS(pipe), pos);
8020
8021 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
8022 ivb_update_cursor(crtc, base);
8023 else if (IS_845G(dev) || IS_I865G(dev))
8024 i845_update_cursor(crtc, base);
8025 else
8026 i9xx_update_cursor(crtc, base);
8027 intel_crtc->cursor_base = base;
8028 }
8029
8030 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
8031 struct drm_file *file,
8032 uint32_t handle,
8033 uint32_t width, uint32_t height)
8034 {
8035 struct drm_device *dev = crtc->dev;
8036 struct drm_i915_private *dev_priv = dev->dev_private;
8037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8038 struct drm_i915_gem_object *obj;
8039 unsigned old_width;
8040 uint32_t addr;
8041 int ret;
8042
8043 /* if we want to turn off the cursor ignore width and height */
8044 if (!handle) {
8045 DRM_DEBUG_KMS("cursor off\n");
8046 addr = 0;
8047 obj = NULL;
8048 mutex_lock(&dev->struct_mutex);
8049 goto finish;
8050 }
8051
8052 /* Check for which cursor types we support */
8053 if (!((width == 64 && height == 64) ||
8054 (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8055 (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8056 DRM_DEBUG("Cursor dimension not supported\n");
8057 return -EINVAL;
8058 }
8059
8060 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
8061 if (&obj->base == NULL)
8062 return -ENOENT;
8063
8064 if (obj->base.size < width * height * 4) {
8065 DRM_DEBUG_KMS("buffer is to small\n");
8066 ret = -ENOMEM;
8067 goto fail;
8068 }
8069
8070 /* we only need to pin inside GTT if cursor is non-phy */
8071 mutex_lock(&dev->struct_mutex);
8072 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8073 unsigned alignment;
8074
8075 if (obj->tiling_mode) {
8076 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8077 ret = -EINVAL;
8078 goto fail_locked;
8079 }
8080
8081 /* Note that the w/a also requires 2 PTE of padding following
8082 * the bo. We currently fill all unused PTE with the shadow
8083 * page and so we should always have valid PTE following the
8084 * cursor preventing the VT-d warning.
8085 */
8086 alignment = 0;
8087 if (need_vtd_wa(dev))
8088 alignment = 64*1024;
8089
8090 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8091 if (ret) {
8092 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8093 goto fail_locked;
8094 }
8095
8096 ret = i915_gem_object_put_fence(obj);
8097 if (ret) {
8098 DRM_DEBUG_KMS("failed to release fence for cursor");
8099 goto fail_unpin;
8100 }
8101
8102 addr = i915_gem_obj_ggtt_offset(obj);
8103 } else {
8104 int align = IS_I830(dev) ? 16 * 1024 : 256;
8105 ret = i915_gem_object_attach_phys(obj, align);
8106 if (ret) {
8107 DRM_DEBUG_KMS("failed to attach phys object\n");
8108 goto fail_locked;
8109 }
8110 addr = obj->phys_handle->busaddr;
8111 }
8112
8113 if (IS_GEN2(dev))
8114 I915_WRITE(CURSIZE, (height << 12) | width);
8115
8116 finish:
8117 if (intel_crtc->cursor_bo) {
8118 if (!INTEL_INFO(dev)->cursor_needs_physical)
8119 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8120 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
8121 }
8122
8123 mutex_unlock(&dev->struct_mutex);
8124
8125 old_width = intel_crtc->cursor_width;
8126
8127 intel_crtc->cursor_addr = addr;
8128 intel_crtc->cursor_bo = obj;
8129 intel_crtc->cursor_width = width;
8130 intel_crtc->cursor_height = height;
8131
8132 if (intel_crtc->active) {
8133 if (old_width != width)
8134 intel_update_watermarks(crtc);
8135 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8136 }
8137
8138 return 0;
8139 fail_unpin:
8140 i915_gem_object_unpin_from_display_plane(obj);
8141 fail_locked:
8142 mutex_unlock(&dev->struct_mutex);
8143 fail:
8144 drm_gem_object_unreference_unlocked(&obj->base);
8145 return ret;
8146 }
8147
8148 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
8149 {
8150 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8151
8152 intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
8153 intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
8154
8155 if (intel_crtc->active)
8156 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8157
8158 return 0;
8159 }
8160
8161 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8162 u16 *blue, uint32_t start, uint32_t size)
8163 {
8164 int end = (start + size > 256) ? 256 : start + size, i;
8165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8166
8167 for (i = start; i < end; i++) {
8168 intel_crtc->lut_r[i] = red[i] >> 8;
8169 intel_crtc->lut_g[i] = green[i] >> 8;
8170 intel_crtc->lut_b[i] = blue[i] >> 8;
8171 }
8172
8173 intel_crtc_load_lut(crtc);
8174 }
8175
8176 /* VESA 640x480x72Hz mode to set on the pipe */
8177 static struct drm_display_mode load_detect_mode = {
8178 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8179 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8180 };
8181
8182 struct drm_framebuffer *
8183 __intel_framebuffer_create(struct drm_device *dev,
8184 struct drm_mode_fb_cmd2 *mode_cmd,
8185 struct drm_i915_gem_object *obj)
8186 {
8187 struct intel_framebuffer *intel_fb;
8188 int ret;
8189
8190 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8191 if (!intel_fb) {
8192 drm_gem_object_unreference_unlocked(&obj->base);
8193 return ERR_PTR(-ENOMEM);
8194 }
8195
8196 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8197 if (ret)
8198 goto err;
8199
8200 return &intel_fb->base;
8201 err:
8202 drm_gem_object_unreference_unlocked(&obj->base);
8203 kfree(intel_fb);
8204
8205 return ERR_PTR(ret);
8206 }
8207
8208 static struct drm_framebuffer *
8209 intel_framebuffer_create(struct drm_device *dev,
8210 struct drm_mode_fb_cmd2 *mode_cmd,
8211 struct drm_i915_gem_object *obj)
8212 {
8213 struct drm_framebuffer *fb;
8214 int ret;
8215
8216 ret = i915_mutex_lock_interruptible(dev);
8217 if (ret)
8218 return ERR_PTR(ret);
8219 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8220 mutex_unlock(&dev->struct_mutex);
8221
8222 return fb;
8223 }
8224
8225 static u32
8226 intel_framebuffer_pitch_for_width(int width, int bpp)
8227 {
8228 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8229 return ALIGN(pitch, 64);
8230 }
8231
8232 static u32
8233 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8234 {
8235 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8236 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
8237 }
8238
8239 static struct drm_framebuffer *
8240 intel_framebuffer_create_for_mode(struct drm_device *dev,
8241 struct drm_display_mode *mode,
8242 int depth, int bpp)
8243 {
8244 struct drm_i915_gem_object *obj;
8245 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8246
8247 obj = i915_gem_alloc_object(dev,
8248 intel_framebuffer_size_for_mode(mode, bpp));
8249 if (obj == NULL)
8250 return ERR_PTR(-ENOMEM);
8251
8252 mode_cmd.width = mode->hdisplay;
8253 mode_cmd.height = mode->vdisplay;
8254 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8255 bpp);
8256 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8257
8258 return intel_framebuffer_create(dev, &mode_cmd, obj);
8259 }
8260
8261 static struct drm_framebuffer *
8262 mode_fits_in_fbdev(struct drm_device *dev,
8263 struct drm_display_mode *mode)
8264 {
8265 #ifdef CONFIG_DRM_I915_FBDEV
8266 struct drm_i915_private *dev_priv = dev->dev_private;
8267 struct drm_i915_gem_object *obj;
8268 struct drm_framebuffer *fb;
8269
8270 if (!dev_priv->fbdev)
8271 return NULL;
8272
8273 if (!dev_priv->fbdev->fb)
8274 return NULL;
8275
8276 obj = dev_priv->fbdev->fb->obj;
8277 BUG_ON(!obj);
8278
8279 fb = &dev_priv->fbdev->fb->base;
8280 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8281 fb->bits_per_pixel))
8282 return NULL;
8283
8284 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8285 return NULL;
8286
8287 return fb;
8288 #else
8289 return NULL;
8290 #endif
8291 }
8292
8293 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8294 struct drm_display_mode *mode,
8295 struct intel_load_detect_pipe *old,
8296 struct drm_modeset_acquire_ctx *ctx)
8297 {
8298 struct intel_crtc *intel_crtc;
8299 struct intel_encoder *intel_encoder =
8300 intel_attached_encoder(connector);
8301 struct drm_crtc *possible_crtc;
8302 struct drm_encoder *encoder = &intel_encoder->base;
8303 struct drm_crtc *crtc = NULL;
8304 struct drm_device *dev = encoder->dev;
8305 struct drm_framebuffer *fb;
8306 struct drm_mode_config *config = &dev->mode_config;
8307 int ret, i = -1;
8308
8309 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8310 connector->base.id, connector->name,
8311 encoder->base.id, encoder->name);
8312
8313 drm_modeset_acquire_init(ctx, 0);
8314
8315 retry:
8316 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8317 if (ret)
8318 goto fail_unlock;
8319
8320 /*
8321 * Algorithm gets a little messy:
8322 *
8323 * - if the connector already has an assigned crtc, use it (but make
8324 * sure it's on first)
8325 *
8326 * - try to find the first unused crtc that can drive this connector,
8327 * and use that if we find one
8328 */
8329
8330 /* See if we already have a CRTC for this connector */
8331 if (encoder->crtc) {
8332 crtc = encoder->crtc;
8333
8334 ret = drm_modeset_lock(&crtc->mutex, ctx);
8335 if (ret)
8336 goto fail_unlock;
8337
8338 old->dpms_mode = connector->dpms;
8339 old->load_detect_temp = false;
8340
8341 /* Make sure the crtc and connector are running */
8342 if (connector->dpms != DRM_MODE_DPMS_ON)
8343 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8344
8345 return true;
8346 }
8347
8348 /* Find an unused one (if possible) */
8349 for_each_crtc(dev, possible_crtc) {
8350 i++;
8351 if (!(encoder->possible_crtcs & (1 << i)))
8352 continue;
8353 if (!possible_crtc->enabled) {
8354 crtc = possible_crtc;
8355 break;
8356 }
8357 }
8358
8359 /*
8360 * If we didn't find an unused CRTC, don't use any.
8361 */
8362 if (!crtc) {
8363 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8364 goto fail_unlock;
8365 }
8366
8367 ret = drm_modeset_lock(&crtc->mutex, ctx);
8368 if (ret)
8369 goto fail_unlock;
8370 intel_encoder->new_crtc = to_intel_crtc(crtc);
8371 to_intel_connector(connector)->new_encoder = intel_encoder;
8372
8373 intel_crtc = to_intel_crtc(crtc);
8374 intel_crtc->new_enabled = true;
8375 intel_crtc->new_config = &intel_crtc->config;
8376 old->dpms_mode = connector->dpms;
8377 old->load_detect_temp = true;
8378 old->release_fb = NULL;
8379
8380 if (!mode)
8381 mode = &load_detect_mode;
8382
8383 /* We need a framebuffer large enough to accommodate all accesses
8384 * that the plane may generate whilst we perform load detection.
8385 * We can not rely on the fbcon either being present (we get called
8386 * during its initialisation to detect all boot displays, or it may
8387 * not even exist) or that it is large enough to satisfy the
8388 * requested mode.
8389 */
8390 fb = mode_fits_in_fbdev(dev, mode);
8391 if (fb == NULL) {
8392 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8393 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8394 old->release_fb = fb;
8395 } else
8396 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8397 if (IS_ERR(fb)) {
8398 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8399 goto fail;
8400 }
8401
8402 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8403 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8404 if (old->release_fb)
8405 old->release_fb->funcs->destroy(old->release_fb);
8406 goto fail;
8407 }
8408
8409 /* let the connector get through one full cycle before testing */
8410 intel_wait_for_vblank(dev, intel_crtc->pipe);
8411 return true;
8412
8413 fail:
8414 intel_crtc->new_enabled = crtc->enabled;
8415 if (intel_crtc->new_enabled)
8416 intel_crtc->new_config = &intel_crtc->config;
8417 else
8418 intel_crtc->new_config = NULL;
8419 fail_unlock:
8420 if (ret == -EDEADLK) {
8421 drm_modeset_backoff(ctx);
8422 goto retry;
8423 }
8424
8425 drm_modeset_drop_locks(ctx);
8426 drm_modeset_acquire_fini(ctx);
8427
8428 return false;
8429 }
8430
8431 void intel_release_load_detect_pipe(struct drm_connector *connector,
8432 struct intel_load_detect_pipe *old,
8433 struct drm_modeset_acquire_ctx *ctx)
8434 {
8435 struct intel_encoder *intel_encoder =
8436 intel_attached_encoder(connector);
8437 struct drm_encoder *encoder = &intel_encoder->base;
8438 struct drm_crtc *crtc = encoder->crtc;
8439 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8440
8441 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8442 connector->base.id, connector->name,
8443 encoder->base.id, encoder->name);
8444
8445 if (old->load_detect_temp) {
8446 to_intel_connector(connector)->new_encoder = NULL;
8447 intel_encoder->new_crtc = NULL;
8448 intel_crtc->new_enabled = false;
8449 intel_crtc->new_config = NULL;
8450 intel_set_mode(crtc, NULL, 0, 0, NULL);
8451
8452 if (old->release_fb) {
8453 drm_framebuffer_unregister_private(old->release_fb);
8454 drm_framebuffer_unreference(old->release_fb);
8455 }
8456
8457 goto unlock;
8458 return;
8459 }
8460
8461 /* Switch crtc and encoder back off if necessary */
8462 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8463 connector->funcs->dpms(connector, old->dpms_mode);
8464
8465 unlock:
8466 drm_modeset_drop_locks(ctx);
8467 drm_modeset_acquire_fini(ctx);
8468 }
8469
8470 static int i9xx_pll_refclk(struct drm_device *dev,
8471 const struct intel_crtc_config *pipe_config)
8472 {
8473 struct drm_i915_private *dev_priv = dev->dev_private;
8474 u32 dpll = pipe_config->dpll_hw_state.dpll;
8475
8476 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8477 return dev_priv->vbt.lvds_ssc_freq;
8478 else if (HAS_PCH_SPLIT(dev))
8479 return 120000;
8480 else if (!IS_GEN2(dev))
8481 return 96000;
8482 else
8483 return 48000;
8484 }
8485
8486 /* Returns the clock of the currently programmed mode of the given pipe. */
8487 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8488 struct intel_crtc_config *pipe_config)
8489 {
8490 struct drm_device *dev = crtc->base.dev;
8491 struct drm_i915_private *dev_priv = dev->dev_private;
8492 int pipe = pipe_config->cpu_transcoder;
8493 u32 dpll = pipe_config->dpll_hw_state.dpll;
8494 u32 fp;
8495 intel_clock_t clock;
8496 int refclk = i9xx_pll_refclk(dev, pipe_config);
8497
8498 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8499 fp = pipe_config->dpll_hw_state.fp0;
8500 else
8501 fp = pipe_config->dpll_hw_state.fp1;
8502
8503 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8504 if (IS_PINEVIEW(dev)) {
8505 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8506 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8507 } else {
8508 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8509 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8510 }
8511
8512 if (!IS_GEN2(dev)) {
8513 if (IS_PINEVIEW(dev))
8514 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8515 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8516 else
8517 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8518 DPLL_FPA01_P1_POST_DIV_SHIFT);
8519
8520 switch (dpll & DPLL_MODE_MASK) {
8521 case DPLLB_MODE_DAC_SERIAL:
8522 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8523 5 : 10;
8524 break;
8525 case DPLLB_MODE_LVDS:
8526 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8527 7 : 14;
8528 break;
8529 default:
8530 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8531 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8532 return;
8533 }
8534
8535 if (IS_PINEVIEW(dev))
8536 pineview_clock(refclk, &clock);
8537 else
8538 i9xx_clock(refclk, &clock);
8539 } else {
8540 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8541 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8542
8543 if (is_lvds) {
8544 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8545 DPLL_FPA01_P1_POST_DIV_SHIFT);
8546
8547 if (lvds & LVDS_CLKB_POWER_UP)
8548 clock.p2 = 7;
8549 else
8550 clock.p2 = 14;
8551 } else {
8552 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8553 clock.p1 = 2;
8554 else {
8555 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8556 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8557 }
8558 if (dpll & PLL_P2_DIVIDE_BY_4)
8559 clock.p2 = 4;
8560 else
8561 clock.p2 = 2;
8562 }
8563
8564 i9xx_clock(refclk, &clock);
8565 }
8566
8567 /*
8568 * This value includes pixel_multiplier. We will use
8569 * port_clock to compute adjusted_mode.crtc_clock in the
8570 * encoder's get_config() function.
8571 */
8572 pipe_config->port_clock = clock.dot;
8573 }
8574
8575 int intel_dotclock_calculate(int link_freq,
8576 const struct intel_link_m_n *m_n)
8577 {
8578 /*
8579 * The calculation for the data clock is:
8580 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8581 * But we want to avoid losing precison if possible, so:
8582 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8583 *
8584 * and the link clock is simpler:
8585 * link_clock = (m * link_clock) / n
8586 */
8587
8588 if (!m_n->link_n)
8589 return 0;
8590
8591 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8592 }
8593
8594 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8595 struct intel_crtc_config *pipe_config)
8596 {
8597 struct drm_device *dev = crtc->base.dev;
8598
8599 /* read out port_clock from the DPLL */
8600 i9xx_crtc_clock_get(crtc, pipe_config);
8601
8602 /*
8603 * This value does not include pixel_multiplier.
8604 * We will check that port_clock and adjusted_mode.crtc_clock
8605 * agree once we know their relationship in the encoder's
8606 * get_config() function.
8607 */
8608 pipe_config->adjusted_mode.crtc_clock =
8609 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8610 &pipe_config->fdi_m_n);
8611 }
8612
8613 /** Returns the currently programmed mode of the given pipe. */
8614 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8615 struct drm_crtc *crtc)
8616 {
8617 struct drm_i915_private *dev_priv = dev->dev_private;
8618 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8619 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8620 struct drm_display_mode *mode;
8621 struct intel_crtc_config pipe_config;
8622 int htot = I915_READ(HTOTAL(cpu_transcoder));
8623 int hsync = I915_READ(HSYNC(cpu_transcoder));
8624 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8625 int vsync = I915_READ(VSYNC(cpu_transcoder));
8626 enum pipe pipe = intel_crtc->pipe;
8627
8628 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8629 if (!mode)
8630 return NULL;
8631
8632 /*
8633 * Construct a pipe_config sufficient for getting the clock info
8634 * back out of crtc_clock_get.
8635 *
8636 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8637 * to use a real value here instead.
8638 */
8639 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8640 pipe_config.pixel_multiplier = 1;
8641 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8642 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8643 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8644 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8645
8646 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8647 mode->hdisplay = (htot & 0xffff) + 1;
8648 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8649 mode->hsync_start = (hsync & 0xffff) + 1;
8650 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8651 mode->vdisplay = (vtot & 0xffff) + 1;
8652 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8653 mode->vsync_start = (vsync & 0xffff) + 1;
8654 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8655
8656 drm_mode_set_name(mode);
8657
8658 return mode;
8659 }
8660
8661 static void intel_increase_pllclock(struct drm_crtc *crtc)
8662 {
8663 struct drm_device *dev = crtc->dev;
8664 struct drm_i915_private *dev_priv = dev->dev_private;
8665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8666 int pipe = intel_crtc->pipe;
8667 int dpll_reg = DPLL(pipe);
8668 int dpll;
8669
8670 if (HAS_PCH_SPLIT(dev))
8671 return;
8672
8673 if (!dev_priv->lvds_downclock_avail)
8674 return;
8675
8676 dpll = I915_READ(dpll_reg);
8677 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8678 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8679
8680 assert_panel_unlocked(dev_priv, pipe);
8681
8682 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8683 I915_WRITE(dpll_reg, dpll);
8684 intel_wait_for_vblank(dev, pipe);
8685
8686 dpll = I915_READ(dpll_reg);
8687 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8688 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8689 }
8690 }
8691
8692 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8693 {
8694 struct drm_device *dev = crtc->dev;
8695 struct drm_i915_private *dev_priv = dev->dev_private;
8696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8697
8698 if (HAS_PCH_SPLIT(dev))
8699 return;
8700
8701 if (!dev_priv->lvds_downclock_avail)
8702 return;
8703
8704 /*
8705 * Since this is called by a timer, we should never get here in
8706 * the manual case.
8707 */
8708 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8709 int pipe = intel_crtc->pipe;
8710 int dpll_reg = DPLL(pipe);
8711 int dpll;
8712
8713 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8714
8715 assert_panel_unlocked(dev_priv, pipe);
8716
8717 dpll = I915_READ(dpll_reg);
8718 dpll |= DISPLAY_RATE_SELECT_FPA1;
8719 I915_WRITE(dpll_reg, dpll);
8720 intel_wait_for_vblank(dev, pipe);
8721 dpll = I915_READ(dpll_reg);
8722 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8723 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8724 }
8725
8726 }
8727
8728 void intel_mark_busy(struct drm_device *dev)
8729 {
8730 struct drm_i915_private *dev_priv = dev->dev_private;
8731
8732 if (dev_priv->mm.busy)
8733 return;
8734
8735 intel_runtime_pm_get(dev_priv);
8736 i915_update_gfx_val(dev_priv);
8737 dev_priv->mm.busy = true;
8738 }
8739
8740 void intel_mark_idle(struct drm_device *dev)
8741 {
8742 struct drm_i915_private *dev_priv = dev->dev_private;
8743 struct drm_crtc *crtc;
8744
8745 if (!dev_priv->mm.busy)
8746 return;
8747
8748 dev_priv->mm.busy = false;
8749
8750 if (!i915.powersave)
8751 goto out;
8752
8753 for_each_crtc(dev, crtc) {
8754 if (!crtc->primary->fb)
8755 continue;
8756
8757 intel_decrease_pllclock(crtc);
8758 }
8759
8760 if (INTEL_INFO(dev)->gen >= 6)
8761 gen6_rps_idle(dev->dev_private);
8762
8763 out:
8764 intel_runtime_pm_put(dev_priv);
8765 }
8766
8767 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8768 struct intel_engine_cs *ring)
8769 {
8770 struct drm_device *dev = obj->base.dev;
8771 struct drm_crtc *crtc;
8772
8773 if (!i915.powersave)
8774 return;
8775
8776 for_each_crtc(dev, crtc) {
8777 if (!crtc->primary->fb)
8778 continue;
8779
8780 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
8781 continue;
8782
8783 intel_increase_pllclock(crtc);
8784 if (ring && intel_fbc_enabled(dev))
8785 ring->fbc_dirty = true;
8786 }
8787 }
8788
8789 static void intel_crtc_destroy(struct drm_crtc *crtc)
8790 {
8791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8792 struct drm_device *dev = crtc->dev;
8793 struct intel_unpin_work *work;
8794 unsigned long flags;
8795
8796 spin_lock_irqsave(&dev->event_lock, flags);
8797 work = intel_crtc->unpin_work;
8798 intel_crtc->unpin_work = NULL;
8799 spin_unlock_irqrestore(&dev->event_lock, flags);
8800
8801 if (work) {
8802 cancel_work_sync(&work->work);
8803 kfree(work);
8804 }
8805
8806 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8807
8808 drm_crtc_cleanup(crtc);
8809
8810 kfree(intel_crtc);
8811 }
8812
8813 static void intel_unpin_work_fn(struct work_struct *__work)
8814 {
8815 struct intel_unpin_work *work =
8816 container_of(__work, struct intel_unpin_work, work);
8817 struct drm_device *dev = work->crtc->dev;
8818
8819 mutex_lock(&dev->struct_mutex);
8820 intel_unpin_fb_obj(work->old_fb_obj);
8821 drm_gem_object_unreference(&work->pending_flip_obj->base);
8822 drm_gem_object_unreference(&work->old_fb_obj->base);
8823
8824 intel_update_fbc(dev);
8825 mutex_unlock(&dev->struct_mutex);
8826
8827 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8828 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8829
8830 kfree(work);
8831 }
8832
8833 static void do_intel_finish_page_flip(struct drm_device *dev,
8834 struct drm_crtc *crtc)
8835 {
8836 struct drm_i915_private *dev_priv = dev->dev_private;
8837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8838 struct intel_unpin_work *work;
8839 unsigned long flags;
8840
8841 /* Ignore early vblank irqs */
8842 if (intel_crtc == NULL)
8843 return;
8844
8845 spin_lock_irqsave(&dev->event_lock, flags);
8846 work = intel_crtc->unpin_work;
8847
8848 /* Ensure we don't miss a work->pending update ... */
8849 smp_rmb();
8850
8851 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8852 spin_unlock_irqrestore(&dev->event_lock, flags);
8853 return;
8854 }
8855
8856 /* and that the unpin work is consistent wrt ->pending. */
8857 smp_rmb();
8858
8859 intel_crtc->unpin_work = NULL;
8860
8861 if (work->event)
8862 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8863
8864 drm_crtc_vblank_put(crtc);
8865
8866 spin_unlock_irqrestore(&dev->event_lock, flags);
8867
8868 wake_up_all(&dev_priv->pending_flip_queue);
8869
8870 queue_work(dev_priv->wq, &work->work);
8871
8872 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8873 }
8874
8875 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8876 {
8877 struct drm_i915_private *dev_priv = dev->dev_private;
8878 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8879
8880 do_intel_finish_page_flip(dev, crtc);
8881 }
8882
8883 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8884 {
8885 struct drm_i915_private *dev_priv = dev->dev_private;
8886 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8887
8888 do_intel_finish_page_flip(dev, crtc);
8889 }
8890
8891 /* Is 'a' after or equal to 'b'? */
8892 static bool g4x_flip_count_after_eq(u32 a, u32 b)
8893 {
8894 return !((a - b) & 0x80000000);
8895 }
8896
8897 static bool page_flip_finished(struct intel_crtc *crtc)
8898 {
8899 struct drm_device *dev = crtc->base.dev;
8900 struct drm_i915_private *dev_priv = dev->dev_private;
8901
8902 /*
8903 * The relevant registers doen't exist on pre-ctg.
8904 * As the flip done interrupt doesn't trigger for mmio
8905 * flips on gmch platforms, a flip count check isn't
8906 * really needed there. But since ctg has the registers,
8907 * include it in the check anyway.
8908 */
8909 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
8910 return true;
8911
8912 /*
8913 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
8914 * used the same base address. In that case the mmio flip might
8915 * have completed, but the CS hasn't even executed the flip yet.
8916 *
8917 * A flip count check isn't enough as the CS might have updated
8918 * the base address just after start of vblank, but before we
8919 * managed to process the interrupt. This means we'd complete the
8920 * CS flip too soon.
8921 *
8922 * Combining both checks should get us a good enough result. It may
8923 * still happen that the CS flip has been executed, but has not
8924 * yet actually completed. But in case the base address is the same
8925 * anyway, we don't really care.
8926 */
8927 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
8928 crtc->unpin_work->gtt_offset &&
8929 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
8930 crtc->unpin_work->flip_count);
8931 }
8932
8933 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8934 {
8935 struct drm_i915_private *dev_priv = dev->dev_private;
8936 struct intel_crtc *intel_crtc =
8937 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8938 unsigned long flags;
8939
8940 /* NB: An MMIO update of the plane base pointer will also
8941 * generate a page-flip completion irq, i.e. every modeset
8942 * is also accompanied by a spurious intel_prepare_page_flip().
8943 */
8944 spin_lock_irqsave(&dev->event_lock, flags);
8945 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
8946 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8947 spin_unlock_irqrestore(&dev->event_lock, flags);
8948 }
8949
8950 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8951 {
8952 /* Ensure that the work item is consistent when activating it ... */
8953 smp_wmb();
8954 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8955 /* and that it is marked active as soon as the irq could fire. */
8956 smp_wmb();
8957 }
8958
8959 static int intel_gen2_queue_flip(struct drm_device *dev,
8960 struct drm_crtc *crtc,
8961 struct drm_framebuffer *fb,
8962 struct drm_i915_gem_object *obj,
8963 struct intel_engine_cs *ring,
8964 uint32_t flags)
8965 {
8966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8967 u32 flip_mask;
8968 int ret;
8969
8970 ret = intel_ring_begin(ring, 6);
8971 if (ret)
8972 return ret;
8973
8974 /* Can't queue multiple flips, so wait for the previous
8975 * one to finish before executing the next.
8976 */
8977 if (intel_crtc->plane)
8978 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8979 else
8980 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8981 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8982 intel_ring_emit(ring, MI_NOOP);
8983 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8984 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8985 intel_ring_emit(ring, fb->pitches[0]);
8986 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8987 intel_ring_emit(ring, 0); /* aux display base address, unused */
8988
8989 intel_mark_page_flip_active(intel_crtc);
8990 __intel_ring_advance(ring);
8991 return 0;
8992 }
8993
8994 static int intel_gen3_queue_flip(struct drm_device *dev,
8995 struct drm_crtc *crtc,
8996 struct drm_framebuffer *fb,
8997 struct drm_i915_gem_object *obj,
8998 struct intel_engine_cs *ring,
8999 uint32_t flags)
9000 {
9001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9002 u32 flip_mask;
9003 int ret;
9004
9005 ret = intel_ring_begin(ring, 6);
9006 if (ret)
9007 return ret;
9008
9009 if (intel_crtc->plane)
9010 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9011 else
9012 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9013 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9014 intel_ring_emit(ring, MI_NOOP);
9015 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9016 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9017 intel_ring_emit(ring, fb->pitches[0]);
9018 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9019 intel_ring_emit(ring, MI_NOOP);
9020
9021 intel_mark_page_flip_active(intel_crtc);
9022 __intel_ring_advance(ring);
9023 return 0;
9024 }
9025
9026 static int intel_gen4_queue_flip(struct drm_device *dev,
9027 struct drm_crtc *crtc,
9028 struct drm_framebuffer *fb,
9029 struct drm_i915_gem_object *obj,
9030 struct intel_engine_cs *ring,
9031 uint32_t flags)
9032 {
9033 struct drm_i915_private *dev_priv = dev->dev_private;
9034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9035 uint32_t pf, pipesrc;
9036 int ret;
9037
9038 ret = intel_ring_begin(ring, 4);
9039 if (ret)
9040 return ret;
9041
9042 /* i965+ uses the linear or tiled offsets from the
9043 * Display Registers (which do not change across a page-flip)
9044 * so we need only reprogram the base address.
9045 */
9046 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9047 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9048 intel_ring_emit(ring, fb->pitches[0]);
9049 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9050 obj->tiling_mode);
9051
9052 /* XXX Enabling the panel-fitter across page-flip is so far
9053 * untested on non-native modes, so ignore it for now.
9054 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9055 */
9056 pf = 0;
9057 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9058 intel_ring_emit(ring, pf | pipesrc);
9059
9060 intel_mark_page_flip_active(intel_crtc);
9061 __intel_ring_advance(ring);
9062 return 0;
9063 }
9064
9065 static int intel_gen6_queue_flip(struct drm_device *dev,
9066 struct drm_crtc *crtc,
9067 struct drm_framebuffer *fb,
9068 struct drm_i915_gem_object *obj,
9069 struct intel_engine_cs *ring,
9070 uint32_t flags)
9071 {
9072 struct drm_i915_private *dev_priv = dev->dev_private;
9073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9074 uint32_t pf, pipesrc;
9075 int ret;
9076
9077 ret = intel_ring_begin(ring, 4);
9078 if (ret)
9079 return ret;
9080
9081 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9082 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9083 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9084 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9085
9086 /* Contrary to the suggestions in the documentation,
9087 * "Enable Panel Fitter" does not seem to be required when page
9088 * flipping with a non-native mode, and worse causes a normal
9089 * modeset to fail.
9090 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9091 */
9092 pf = 0;
9093 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9094 intel_ring_emit(ring, pf | pipesrc);
9095
9096 intel_mark_page_flip_active(intel_crtc);
9097 __intel_ring_advance(ring);
9098 return 0;
9099 }
9100
9101 static int intel_gen7_queue_flip(struct drm_device *dev,
9102 struct drm_crtc *crtc,
9103 struct drm_framebuffer *fb,
9104 struct drm_i915_gem_object *obj,
9105 struct intel_engine_cs *ring,
9106 uint32_t flags)
9107 {
9108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9109 uint32_t plane_bit = 0;
9110 int len, ret;
9111
9112 switch (intel_crtc->plane) {
9113 case PLANE_A:
9114 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9115 break;
9116 case PLANE_B:
9117 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9118 break;
9119 case PLANE_C:
9120 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9121 break;
9122 default:
9123 WARN_ONCE(1, "unknown plane in flip command\n");
9124 return -ENODEV;
9125 }
9126
9127 len = 4;
9128 if (ring->id == RCS) {
9129 len += 6;
9130 /*
9131 * On Gen 8, SRM is now taking an extra dword to accommodate
9132 * 48bits addresses, and we need a NOOP for the batch size to
9133 * stay even.
9134 */
9135 if (IS_GEN8(dev))
9136 len += 2;
9137 }
9138
9139 /*
9140 * BSpec MI_DISPLAY_FLIP for IVB:
9141 * "The full packet must be contained within the same cache line."
9142 *
9143 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9144 * cacheline, if we ever start emitting more commands before
9145 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9146 * then do the cacheline alignment, and finally emit the
9147 * MI_DISPLAY_FLIP.
9148 */
9149 ret = intel_ring_cacheline_align(ring);
9150 if (ret)
9151 return ret;
9152
9153 ret = intel_ring_begin(ring, len);
9154 if (ret)
9155 return ret;
9156
9157 /* Unmask the flip-done completion message. Note that the bspec says that
9158 * we should do this for both the BCS and RCS, and that we must not unmask
9159 * more than one flip event at any time (or ensure that one flip message
9160 * can be sent by waiting for flip-done prior to queueing new flips).
9161 * Experimentation says that BCS works despite DERRMR masking all
9162 * flip-done completion events and that unmasking all planes at once
9163 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9164 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9165 */
9166 if (ring->id == RCS) {
9167 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9168 intel_ring_emit(ring, DERRMR);
9169 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9170 DERRMR_PIPEB_PRI_FLIP_DONE |
9171 DERRMR_PIPEC_PRI_FLIP_DONE));
9172 if (IS_GEN8(dev))
9173 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9174 MI_SRM_LRM_GLOBAL_GTT);
9175 else
9176 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9177 MI_SRM_LRM_GLOBAL_GTT);
9178 intel_ring_emit(ring, DERRMR);
9179 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9180 if (IS_GEN8(dev)) {
9181 intel_ring_emit(ring, 0);
9182 intel_ring_emit(ring, MI_NOOP);
9183 }
9184 }
9185
9186 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9187 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9188 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9189 intel_ring_emit(ring, (MI_NOOP));
9190
9191 intel_mark_page_flip_active(intel_crtc);
9192 __intel_ring_advance(ring);
9193 return 0;
9194 }
9195
9196 static int intel_default_queue_flip(struct drm_device *dev,
9197 struct drm_crtc *crtc,
9198 struct drm_framebuffer *fb,
9199 struct drm_i915_gem_object *obj,
9200 struct intel_engine_cs *ring,
9201 uint32_t flags)
9202 {
9203 return -ENODEV;
9204 }
9205
9206 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9207 struct drm_framebuffer *fb,
9208 struct drm_pending_vblank_event *event,
9209 uint32_t page_flip_flags)
9210 {
9211 struct drm_device *dev = crtc->dev;
9212 struct drm_i915_private *dev_priv = dev->dev_private;
9213 struct drm_framebuffer *old_fb = crtc->primary->fb;
9214 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
9215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9216 struct intel_unpin_work *work;
9217 struct intel_engine_cs *ring;
9218 unsigned long flags;
9219 int ret;
9220
9221 /* Can't change pixel format via MI display flips. */
9222 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9223 return -EINVAL;
9224
9225 /*
9226 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9227 * Note that pitch changes could also affect these register.
9228 */
9229 if (INTEL_INFO(dev)->gen > 3 &&
9230 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9231 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9232 return -EINVAL;
9233
9234 if (i915_terminally_wedged(&dev_priv->gpu_error))
9235 goto out_hang;
9236
9237 work = kzalloc(sizeof(*work), GFP_KERNEL);
9238 if (work == NULL)
9239 return -ENOMEM;
9240
9241 work->event = event;
9242 work->crtc = crtc;
9243 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
9244 INIT_WORK(&work->work, intel_unpin_work_fn);
9245
9246 ret = drm_crtc_vblank_get(crtc);
9247 if (ret)
9248 goto free_work;
9249
9250 /* We borrow the event spin lock for protecting unpin_work */
9251 spin_lock_irqsave(&dev->event_lock, flags);
9252 if (intel_crtc->unpin_work) {
9253 spin_unlock_irqrestore(&dev->event_lock, flags);
9254 kfree(work);
9255 drm_crtc_vblank_put(crtc);
9256
9257 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9258 return -EBUSY;
9259 }
9260 intel_crtc->unpin_work = work;
9261 spin_unlock_irqrestore(&dev->event_lock, flags);
9262
9263 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9264 flush_workqueue(dev_priv->wq);
9265
9266 ret = i915_mutex_lock_interruptible(dev);
9267 if (ret)
9268 goto cleanup;
9269
9270 /* Reference the objects for the scheduled work. */
9271 drm_gem_object_reference(&work->old_fb_obj->base);
9272 drm_gem_object_reference(&obj->base);
9273
9274 crtc->primary->fb = fb;
9275
9276 work->pending_flip_obj = obj;
9277
9278 work->enable_stall_check = true;
9279
9280 atomic_inc(&intel_crtc->unpin_work_count);
9281 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9282
9283 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9284 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(intel_crtc->pipe)) + 1;
9285
9286 if (IS_VALLEYVIEW(dev)) {
9287 ring = &dev_priv->ring[BCS];
9288 } else if (INTEL_INFO(dev)->gen >= 7) {
9289 ring = obj->ring;
9290 if (ring == NULL || ring->id != RCS)
9291 ring = &dev_priv->ring[BCS];
9292 } else {
9293 ring = &dev_priv->ring[RCS];
9294 }
9295
9296 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9297 if (ret)
9298 goto cleanup_pending;
9299
9300 work->gtt_offset =
9301 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9302
9303 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, page_flip_flags);
9304 if (ret)
9305 goto cleanup_unpin;
9306
9307 intel_disable_fbc(dev);
9308 intel_mark_fb_busy(obj, NULL);
9309 mutex_unlock(&dev->struct_mutex);
9310
9311 trace_i915_flip_request(intel_crtc->plane, obj);
9312
9313 return 0;
9314
9315 cleanup_unpin:
9316 intel_unpin_fb_obj(obj);
9317 cleanup_pending:
9318 atomic_dec(&intel_crtc->unpin_work_count);
9319 crtc->primary->fb = old_fb;
9320 drm_gem_object_unreference(&work->old_fb_obj->base);
9321 drm_gem_object_unreference(&obj->base);
9322 mutex_unlock(&dev->struct_mutex);
9323
9324 cleanup:
9325 spin_lock_irqsave(&dev->event_lock, flags);
9326 intel_crtc->unpin_work = NULL;
9327 spin_unlock_irqrestore(&dev->event_lock, flags);
9328
9329 drm_crtc_vblank_put(crtc);
9330 free_work:
9331 kfree(work);
9332
9333 if (ret == -EIO) {
9334 out_hang:
9335 intel_crtc_wait_for_pending_flips(crtc);
9336 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9337 if (ret == 0 && event)
9338 drm_send_vblank_event(dev, intel_crtc->pipe, event);
9339 }
9340 return ret;
9341 }
9342
9343 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9344 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9345 .load_lut = intel_crtc_load_lut,
9346 };
9347
9348 /**
9349 * intel_modeset_update_staged_output_state
9350 *
9351 * Updates the staged output configuration state, e.g. after we've read out the
9352 * current hw state.
9353 */
9354 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9355 {
9356 struct intel_crtc *crtc;
9357 struct intel_encoder *encoder;
9358 struct intel_connector *connector;
9359
9360 list_for_each_entry(connector, &dev->mode_config.connector_list,
9361 base.head) {
9362 connector->new_encoder =
9363 to_intel_encoder(connector->base.encoder);
9364 }
9365
9366 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9367 base.head) {
9368 encoder->new_crtc =
9369 to_intel_crtc(encoder->base.crtc);
9370 }
9371
9372 for_each_intel_crtc(dev, crtc) {
9373 crtc->new_enabled = crtc->base.enabled;
9374
9375 if (crtc->new_enabled)
9376 crtc->new_config = &crtc->config;
9377 else
9378 crtc->new_config = NULL;
9379 }
9380 }
9381
9382 /**
9383 * intel_modeset_commit_output_state
9384 *
9385 * This function copies the stage display pipe configuration to the real one.
9386 */
9387 static void intel_modeset_commit_output_state(struct drm_device *dev)
9388 {
9389 struct intel_crtc *crtc;
9390 struct intel_encoder *encoder;
9391 struct intel_connector *connector;
9392
9393 list_for_each_entry(connector, &dev->mode_config.connector_list,
9394 base.head) {
9395 connector->base.encoder = &connector->new_encoder->base;
9396 }
9397
9398 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9399 base.head) {
9400 encoder->base.crtc = &encoder->new_crtc->base;
9401 }
9402
9403 for_each_intel_crtc(dev, crtc) {
9404 crtc->base.enabled = crtc->new_enabled;
9405 }
9406 }
9407
9408 static void
9409 connected_sink_compute_bpp(struct intel_connector *connector,
9410 struct intel_crtc_config *pipe_config)
9411 {
9412 int bpp = pipe_config->pipe_bpp;
9413
9414 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9415 connector->base.base.id,
9416 connector->base.name);
9417
9418 /* Don't use an invalid EDID bpc value */
9419 if (connector->base.display_info.bpc &&
9420 connector->base.display_info.bpc * 3 < bpp) {
9421 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9422 bpp, connector->base.display_info.bpc*3);
9423 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9424 }
9425
9426 /* Clamp bpp to 8 on screens without EDID 1.4 */
9427 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9428 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9429 bpp);
9430 pipe_config->pipe_bpp = 24;
9431 }
9432 }
9433
9434 static int
9435 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9436 struct drm_framebuffer *fb,
9437 struct intel_crtc_config *pipe_config)
9438 {
9439 struct drm_device *dev = crtc->base.dev;
9440 struct intel_connector *connector;
9441 int bpp;
9442
9443 switch (fb->pixel_format) {
9444 case DRM_FORMAT_C8:
9445 bpp = 8*3; /* since we go through a colormap */
9446 break;
9447 case DRM_FORMAT_XRGB1555:
9448 case DRM_FORMAT_ARGB1555:
9449 /* checked in intel_framebuffer_init already */
9450 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9451 return -EINVAL;
9452 case DRM_FORMAT_RGB565:
9453 bpp = 6*3; /* min is 18bpp */
9454 break;
9455 case DRM_FORMAT_XBGR8888:
9456 case DRM_FORMAT_ABGR8888:
9457 /* checked in intel_framebuffer_init already */
9458 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9459 return -EINVAL;
9460 case DRM_FORMAT_XRGB8888:
9461 case DRM_FORMAT_ARGB8888:
9462 bpp = 8*3;
9463 break;
9464 case DRM_FORMAT_XRGB2101010:
9465 case DRM_FORMAT_ARGB2101010:
9466 case DRM_FORMAT_XBGR2101010:
9467 case DRM_FORMAT_ABGR2101010:
9468 /* checked in intel_framebuffer_init already */
9469 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9470 return -EINVAL;
9471 bpp = 10*3;
9472 break;
9473 /* TODO: gen4+ supports 16 bpc floating point, too. */
9474 default:
9475 DRM_DEBUG_KMS("unsupported depth\n");
9476 return -EINVAL;
9477 }
9478
9479 pipe_config->pipe_bpp = bpp;
9480
9481 /* Clamp display bpp to EDID value */
9482 list_for_each_entry(connector, &dev->mode_config.connector_list,
9483 base.head) {
9484 if (!connector->new_encoder ||
9485 connector->new_encoder->new_crtc != crtc)
9486 continue;
9487
9488 connected_sink_compute_bpp(connector, pipe_config);
9489 }
9490
9491 return bpp;
9492 }
9493
9494 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9495 {
9496 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9497 "type: 0x%x flags: 0x%x\n",
9498 mode->crtc_clock,
9499 mode->crtc_hdisplay, mode->crtc_hsync_start,
9500 mode->crtc_hsync_end, mode->crtc_htotal,
9501 mode->crtc_vdisplay, mode->crtc_vsync_start,
9502 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9503 }
9504
9505 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9506 struct intel_crtc_config *pipe_config,
9507 const char *context)
9508 {
9509 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9510 context, pipe_name(crtc->pipe));
9511
9512 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9513 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9514 pipe_config->pipe_bpp, pipe_config->dither);
9515 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9516 pipe_config->has_pch_encoder,
9517 pipe_config->fdi_lanes,
9518 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9519 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9520 pipe_config->fdi_m_n.tu);
9521 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9522 pipe_config->has_dp_encoder,
9523 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9524 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9525 pipe_config->dp_m_n.tu);
9526 DRM_DEBUG_KMS("requested mode:\n");
9527 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9528 DRM_DEBUG_KMS("adjusted mode:\n");
9529 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9530 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9531 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9532 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9533 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9534 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9535 pipe_config->gmch_pfit.control,
9536 pipe_config->gmch_pfit.pgm_ratios,
9537 pipe_config->gmch_pfit.lvds_border_bits);
9538 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9539 pipe_config->pch_pfit.pos,
9540 pipe_config->pch_pfit.size,
9541 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9542 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9543 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9544 }
9545
9546 static bool encoders_cloneable(const struct intel_encoder *a,
9547 const struct intel_encoder *b)
9548 {
9549 /* masks could be asymmetric, so check both ways */
9550 return a == b || (a->cloneable & (1 << b->type) &&
9551 b->cloneable & (1 << a->type));
9552 }
9553
9554 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9555 struct intel_encoder *encoder)
9556 {
9557 struct drm_device *dev = crtc->base.dev;
9558 struct intel_encoder *source_encoder;
9559
9560 list_for_each_entry(source_encoder,
9561 &dev->mode_config.encoder_list, base.head) {
9562 if (source_encoder->new_crtc != crtc)
9563 continue;
9564
9565 if (!encoders_cloneable(encoder, source_encoder))
9566 return false;
9567 }
9568
9569 return true;
9570 }
9571
9572 static bool check_encoder_cloning(struct intel_crtc *crtc)
9573 {
9574 struct drm_device *dev = crtc->base.dev;
9575 struct intel_encoder *encoder;
9576
9577 list_for_each_entry(encoder,
9578 &dev->mode_config.encoder_list, base.head) {
9579 if (encoder->new_crtc != crtc)
9580 continue;
9581
9582 if (!check_single_encoder_cloning(crtc, encoder))
9583 return false;
9584 }
9585
9586 return true;
9587 }
9588
9589 static struct intel_crtc_config *
9590 intel_modeset_pipe_config(struct drm_crtc *crtc,
9591 struct drm_framebuffer *fb,
9592 struct drm_display_mode *mode)
9593 {
9594 struct drm_device *dev = crtc->dev;
9595 struct intel_encoder *encoder;
9596 struct intel_crtc_config *pipe_config;
9597 int plane_bpp, ret = -EINVAL;
9598 bool retry = true;
9599
9600 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9601 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9602 return ERR_PTR(-EINVAL);
9603 }
9604
9605 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9606 if (!pipe_config)
9607 return ERR_PTR(-ENOMEM);
9608
9609 drm_mode_copy(&pipe_config->adjusted_mode, mode);
9610 drm_mode_copy(&pipe_config->requested_mode, mode);
9611
9612 pipe_config->cpu_transcoder =
9613 (enum transcoder) to_intel_crtc(crtc)->pipe;
9614 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9615
9616 /*
9617 * Sanitize sync polarity flags based on requested ones. If neither
9618 * positive or negative polarity is requested, treat this as meaning
9619 * negative polarity.
9620 */
9621 if (!(pipe_config->adjusted_mode.flags &
9622 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9623 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9624
9625 if (!(pipe_config->adjusted_mode.flags &
9626 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9627 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9628
9629 /* Compute a starting value for pipe_config->pipe_bpp taking the source
9630 * plane pixel format and any sink constraints into account. Returns the
9631 * source plane bpp so that dithering can be selected on mismatches
9632 * after encoders and crtc also have had their say. */
9633 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9634 fb, pipe_config);
9635 if (plane_bpp < 0)
9636 goto fail;
9637
9638 /*
9639 * Determine the real pipe dimensions. Note that stereo modes can
9640 * increase the actual pipe size due to the frame doubling and
9641 * insertion of additional space for blanks between the frame. This
9642 * is stored in the crtc timings. We use the requested mode to do this
9643 * computation to clearly distinguish it from the adjusted mode, which
9644 * can be changed by the connectors in the below retry loop.
9645 */
9646 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9647 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9648 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9649
9650 encoder_retry:
9651 /* Ensure the port clock defaults are reset when retrying. */
9652 pipe_config->port_clock = 0;
9653 pipe_config->pixel_multiplier = 1;
9654
9655 /* Fill in default crtc timings, allow encoders to overwrite them. */
9656 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9657
9658 /* Pass our mode to the connectors and the CRTC to give them a chance to
9659 * adjust it according to limitations or connector properties, and also
9660 * a chance to reject the mode entirely.
9661 */
9662 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9663 base.head) {
9664
9665 if (&encoder->new_crtc->base != crtc)
9666 continue;
9667
9668 if (!(encoder->compute_config(encoder, pipe_config))) {
9669 DRM_DEBUG_KMS("Encoder config failure\n");
9670 goto fail;
9671 }
9672 }
9673
9674 /* Set default port clock if not overwritten by the encoder. Needs to be
9675 * done afterwards in case the encoder adjusts the mode. */
9676 if (!pipe_config->port_clock)
9677 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9678 * pipe_config->pixel_multiplier;
9679
9680 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9681 if (ret < 0) {
9682 DRM_DEBUG_KMS("CRTC fixup failed\n");
9683 goto fail;
9684 }
9685
9686 if (ret == RETRY) {
9687 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9688 ret = -EINVAL;
9689 goto fail;
9690 }
9691
9692 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9693 retry = false;
9694 goto encoder_retry;
9695 }
9696
9697 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9698 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9699 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9700
9701 return pipe_config;
9702 fail:
9703 kfree(pipe_config);
9704 return ERR_PTR(ret);
9705 }
9706
9707 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9708 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9709 static void
9710 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9711 unsigned *prepare_pipes, unsigned *disable_pipes)
9712 {
9713 struct intel_crtc *intel_crtc;
9714 struct drm_device *dev = crtc->dev;
9715 struct intel_encoder *encoder;
9716 struct intel_connector *connector;
9717 struct drm_crtc *tmp_crtc;
9718
9719 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9720
9721 /* Check which crtcs have changed outputs connected to them, these need
9722 * to be part of the prepare_pipes mask. We don't (yet) support global
9723 * modeset across multiple crtcs, so modeset_pipes will only have one
9724 * bit set at most. */
9725 list_for_each_entry(connector, &dev->mode_config.connector_list,
9726 base.head) {
9727 if (connector->base.encoder == &connector->new_encoder->base)
9728 continue;
9729
9730 if (connector->base.encoder) {
9731 tmp_crtc = connector->base.encoder->crtc;
9732
9733 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9734 }
9735
9736 if (connector->new_encoder)
9737 *prepare_pipes |=
9738 1 << connector->new_encoder->new_crtc->pipe;
9739 }
9740
9741 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9742 base.head) {
9743 if (encoder->base.crtc == &encoder->new_crtc->base)
9744 continue;
9745
9746 if (encoder->base.crtc) {
9747 tmp_crtc = encoder->base.crtc;
9748
9749 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9750 }
9751
9752 if (encoder->new_crtc)
9753 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9754 }
9755
9756 /* Check for pipes that will be enabled/disabled ... */
9757 for_each_intel_crtc(dev, intel_crtc) {
9758 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9759 continue;
9760
9761 if (!intel_crtc->new_enabled)
9762 *disable_pipes |= 1 << intel_crtc->pipe;
9763 else
9764 *prepare_pipes |= 1 << intel_crtc->pipe;
9765 }
9766
9767
9768 /* set_mode is also used to update properties on life display pipes. */
9769 intel_crtc = to_intel_crtc(crtc);
9770 if (intel_crtc->new_enabled)
9771 *prepare_pipes |= 1 << intel_crtc->pipe;
9772
9773 /*
9774 * For simplicity do a full modeset on any pipe where the output routing
9775 * changed. We could be more clever, but that would require us to be
9776 * more careful with calling the relevant encoder->mode_set functions.
9777 */
9778 if (*prepare_pipes)
9779 *modeset_pipes = *prepare_pipes;
9780
9781 /* ... and mask these out. */
9782 *modeset_pipes &= ~(*disable_pipes);
9783 *prepare_pipes &= ~(*disable_pipes);
9784
9785 /*
9786 * HACK: We don't (yet) fully support global modesets. intel_set_config
9787 * obies this rule, but the modeset restore mode of
9788 * intel_modeset_setup_hw_state does not.
9789 */
9790 *modeset_pipes &= 1 << intel_crtc->pipe;
9791 *prepare_pipes &= 1 << intel_crtc->pipe;
9792
9793 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9794 *modeset_pipes, *prepare_pipes, *disable_pipes);
9795 }
9796
9797 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9798 {
9799 struct drm_encoder *encoder;
9800 struct drm_device *dev = crtc->dev;
9801
9802 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9803 if (encoder->crtc == crtc)
9804 return true;
9805
9806 return false;
9807 }
9808
9809 static void
9810 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9811 {
9812 struct intel_encoder *intel_encoder;
9813 struct intel_crtc *intel_crtc;
9814 struct drm_connector *connector;
9815
9816 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9817 base.head) {
9818 if (!intel_encoder->base.crtc)
9819 continue;
9820
9821 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9822
9823 if (prepare_pipes & (1 << intel_crtc->pipe))
9824 intel_encoder->connectors_active = false;
9825 }
9826
9827 intel_modeset_commit_output_state(dev);
9828
9829 /* Double check state. */
9830 for_each_intel_crtc(dev, intel_crtc) {
9831 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9832 WARN_ON(intel_crtc->new_config &&
9833 intel_crtc->new_config != &intel_crtc->config);
9834 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9835 }
9836
9837 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9838 if (!connector->encoder || !connector->encoder->crtc)
9839 continue;
9840
9841 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9842
9843 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9844 struct drm_property *dpms_property =
9845 dev->mode_config.dpms_property;
9846
9847 connector->dpms = DRM_MODE_DPMS_ON;
9848 drm_object_property_set_value(&connector->base,
9849 dpms_property,
9850 DRM_MODE_DPMS_ON);
9851
9852 intel_encoder = to_intel_encoder(connector->encoder);
9853 intel_encoder->connectors_active = true;
9854 }
9855 }
9856
9857 }
9858
9859 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9860 {
9861 int diff;
9862
9863 if (clock1 == clock2)
9864 return true;
9865
9866 if (!clock1 || !clock2)
9867 return false;
9868
9869 diff = abs(clock1 - clock2);
9870
9871 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9872 return true;
9873
9874 return false;
9875 }
9876
9877 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9878 list_for_each_entry((intel_crtc), \
9879 &(dev)->mode_config.crtc_list, \
9880 base.head) \
9881 if (mask & (1 <<(intel_crtc)->pipe))
9882
9883 static bool
9884 intel_pipe_config_compare(struct drm_device *dev,
9885 struct intel_crtc_config *current_config,
9886 struct intel_crtc_config *pipe_config)
9887 {
9888 #define PIPE_CONF_CHECK_X(name) \
9889 if (current_config->name != pipe_config->name) { \
9890 DRM_ERROR("mismatch in " #name " " \
9891 "(expected 0x%08x, found 0x%08x)\n", \
9892 current_config->name, \
9893 pipe_config->name); \
9894 return false; \
9895 }
9896
9897 #define PIPE_CONF_CHECK_I(name) \
9898 if (current_config->name != pipe_config->name) { \
9899 DRM_ERROR("mismatch in " #name " " \
9900 "(expected %i, found %i)\n", \
9901 current_config->name, \
9902 pipe_config->name); \
9903 return false; \
9904 }
9905
9906 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
9907 if ((current_config->name ^ pipe_config->name) & (mask)) { \
9908 DRM_ERROR("mismatch in " #name "(" #mask ") " \
9909 "(expected %i, found %i)\n", \
9910 current_config->name & (mask), \
9911 pipe_config->name & (mask)); \
9912 return false; \
9913 }
9914
9915 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9916 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9917 DRM_ERROR("mismatch in " #name " " \
9918 "(expected %i, found %i)\n", \
9919 current_config->name, \
9920 pipe_config->name); \
9921 return false; \
9922 }
9923
9924 #define PIPE_CONF_QUIRK(quirk) \
9925 ((current_config->quirks | pipe_config->quirks) & (quirk))
9926
9927 PIPE_CONF_CHECK_I(cpu_transcoder);
9928
9929 PIPE_CONF_CHECK_I(has_pch_encoder);
9930 PIPE_CONF_CHECK_I(fdi_lanes);
9931 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9932 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9933 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9934 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9935 PIPE_CONF_CHECK_I(fdi_m_n.tu);
9936
9937 PIPE_CONF_CHECK_I(has_dp_encoder);
9938 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9939 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9940 PIPE_CONF_CHECK_I(dp_m_n.link_m);
9941 PIPE_CONF_CHECK_I(dp_m_n.link_n);
9942 PIPE_CONF_CHECK_I(dp_m_n.tu);
9943
9944 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9945 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9946 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9947 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9948 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9949 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9950
9951 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9952 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9953 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9954 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9955 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9956 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9957
9958 PIPE_CONF_CHECK_I(pixel_multiplier);
9959 PIPE_CONF_CHECK_I(has_hdmi_sink);
9960 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
9961 IS_VALLEYVIEW(dev))
9962 PIPE_CONF_CHECK_I(limited_color_range);
9963
9964 PIPE_CONF_CHECK_I(has_audio);
9965
9966 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9967 DRM_MODE_FLAG_INTERLACE);
9968
9969 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9970 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9971 DRM_MODE_FLAG_PHSYNC);
9972 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9973 DRM_MODE_FLAG_NHSYNC);
9974 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9975 DRM_MODE_FLAG_PVSYNC);
9976 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9977 DRM_MODE_FLAG_NVSYNC);
9978 }
9979
9980 PIPE_CONF_CHECK_I(pipe_src_w);
9981 PIPE_CONF_CHECK_I(pipe_src_h);
9982
9983 /*
9984 * FIXME: BIOS likes to set up a cloned config with lvds+external
9985 * screen. Since we don't yet re-compute the pipe config when moving
9986 * just the lvds port away to another pipe the sw tracking won't match.
9987 *
9988 * Proper atomic modesets with recomputed global state will fix this.
9989 * Until then just don't check gmch state for inherited modes.
9990 */
9991 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
9992 PIPE_CONF_CHECK_I(gmch_pfit.control);
9993 /* pfit ratios are autocomputed by the hw on gen4+ */
9994 if (INTEL_INFO(dev)->gen < 4)
9995 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9996 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9997 }
9998
9999 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10000 if (current_config->pch_pfit.enabled) {
10001 PIPE_CONF_CHECK_I(pch_pfit.pos);
10002 PIPE_CONF_CHECK_I(pch_pfit.size);
10003 }
10004
10005 /* BDW+ don't expose a synchronous way to read the state */
10006 if (IS_HASWELL(dev))
10007 PIPE_CONF_CHECK_I(ips_enabled);
10008
10009 PIPE_CONF_CHECK_I(double_wide);
10010
10011 PIPE_CONF_CHECK_I(shared_dpll);
10012 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10013 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10014 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10015 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10016
10017 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10018 PIPE_CONF_CHECK_I(pipe_bpp);
10019
10020 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10021 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10022
10023 #undef PIPE_CONF_CHECK_X
10024 #undef PIPE_CONF_CHECK_I
10025 #undef PIPE_CONF_CHECK_FLAGS
10026 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10027 #undef PIPE_CONF_QUIRK
10028
10029 return true;
10030 }
10031
10032 static void
10033 check_connector_state(struct drm_device *dev)
10034 {
10035 struct intel_connector *connector;
10036
10037 list_for_each_entry(connector, &dev->mode_config.connector_list,
10038 base.head) {
10039 /* This also checks the encoder/connector hw state with the
10040 * ->get_hw_state callbacks. */
10041 intel_connector_check_state(connector);
10042
10043 WARN(&connector->new_encoder->base != connector->base.encoder,
10044 "connector's staged encoder doesn't match current encoder\n");
10045 }
10046 }
10047
10048 static void
10049 check_encoder_state(struct drm_device *dev)
10050 {
10051 struct intel_encoder *encoder;
10052 struct intel_connector *connector;
10053
10054 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10055 base.head) {
10056 bool enabled = false;
10057 bool active = false;
10058 enum pipe pipe, tracked_pipe;
10059
10060 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10061 encoder->base.base.id,
10062 encoder->base.name);
10063
10064 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10065 "encoder's stage crtc doesn't match current crtc\n");
10066 WARN(encoder->connectors_active && !encoder->base.crtc,
10067 "encoder's active_connectors set, but no crtc\n");
10068
10069 list_for_each_entry(connector, &dev->mode_config.connector_list,
10070 base.head) {
10071 if (connector->base.encoder != &encoder->base)
10072 continue;
10073 enabled = true;
10074 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10075 active = true;
10076 }
10077 WARN(!!encoder->base.crtc != enabled,
10078 "encoder's enabled state mismatch "
10079 "(expected %i, found %i)\n",
10080 !!encoder->base.crtc, enabled);
10081 WARN(active && !encoder->base.crtc,
10082 "active encoder with no crtc\n");
10083
10084 WARN(encoder->connectors_active != active,
10085 "encoder's computed active state doesn't match tracked active state "
10086 "(expected %i, found %i)\n", active, encoder->connectors_active);
10087
10088 active = encoder->get_hw_state(encoder, &pipe);
10089 WARN(active != encoder->connectors_active,
10090 "encoder's hw state doesn't match sw tracking "
10091 "(expected %i, found %i)\n",
10092 encoder->connectors_active, active);
10093
10094 if (!encoder->base.crtc)
10095 continue;
10096
10097 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10098 WARN(active && pipe != tracked_pipe,
10099 "active encoder's pipe doesn't match"
10100 "(expected %i, found %i)\n",
10101 tracked_pipe, pipe);
10102
10103 }
10104 }
10105
10106 static void
10107 check_crtc_state(struct drm_device *dev)
10108 {
10109 struct drm_i915_private *dev_priv = dev->dev_private;
10110 struct intel_crtc *crtc;
10111 struct intel_encoder *encoder;
10112 struct intel_crtc_config pipe_config;
10113
10114 for_each_intel_crtc(dev, crtc) {
10115 bool enabled = false;
10116 bool active = false;
10117
10118 memset(&pipe_config, 0, sizeof(pipe_config));
10119
10120 DRM_DEBUG_KMS("[CRTC:%d]\n",
10121 crtc->base.base.id);
10122
10123 WARN(crtc->active && !crtc->base.enabled,
10124 "active crtc, but not enabled in sw tracking\n");
10125
10126 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10127 base.head) {
10128 if (encoder->base.crtc != &crtc->base)
10129 continue;
10130 enabled = true;
10131 if (encoder->connectors_active)
10132 active = true;
10133 }
10134
10135 WARN(active != crtc->active,
10136 "crtc's computed active state doesn't match tracked active state "
10137 "(expected %i, found %i)\n", active, crtc->active);
10138 WARN(enabled != crtc->base.enabled,
10139 "crtc's computed enabled state doesn't match tracked enabled state "
10140 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10141
10142 active = dev_priv->display.get_pipe_config(crtc,
10143 &pipe_config);
10144
10145 /* hw state is inconsistent with the pipe A quirk */
10146 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10147 active = crtc->active;
10148
10149 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10150 base.head) {
10151 enum pipe pipe;
10152 if (encoder->base.crtc != &crtc->base)
10153 continue;
10154 if (encoder->get_hw_state(encoder, &pipe))
10155 encoder->get_config(encoder, &pipe_config);
10156 }
10157
10158 WARN(crtc->active != active,
10159 "crtc active state doesn't match with hw state "
10160 "(expected %i, found %i)\n", crtc->active, active);
10161
10162 if (active &&
10163 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10164 WARN(1, "pipe state doesn't match!\n");
10165 intel_dump_pipe_config(crtc, &pipe_config,
10166 "[hw state]");
10167 intel_dump_pipe_config(crtc, &crtc->config,
10168 "[sw state]");
10169 }
10170 }
10171 }
10172
10173 static void
10174 check_shared_dpll_state(struct drm_device *dev)
10175 {
10176 struct drm_i915_private *dev_priv = dev->dev_private;
10177 struct intel_crtc *crtc;
10178 struct intel_dpll_hw_state dpll_hw_state;
10179 int i;
10180
10181 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10182 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10183 int enabled_crtcs = 0, active_crtcs = 0;
10184 bool active;
10185
10186 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10187
10188 DRM_DEBUG_KMS("%s\n", pll->name);
10189
10190 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10191
10192 WARN(pll->active > pll->refcount,
10193 "more active pll users than references: %i vs %i\n",
10194 pll->active, pll->refcount);
10195 WARN(pll->active && !pll->on,
10196 "pll in active use but not on in sw tracking\n");
10197 WARN(pll->on && !pll->active,
10198 "pll in on but not on in use in sw tracking\n");
10199 WARN(pll->on != active,
10200 "pll on state mismatch (expected %i, found %i)\n",
10201 pll->on, active);
10202
10203 for_each_intel_crtc(dev, crtc) {
10204 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10205 enabled_crtcs++;
10206 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10207 active_crtcs++;
10208 }
10209 WARN(pll->active != active_crtcs,
10210 "pll active crtcs mismatch (expected %i, found %i)\n",
10211 pll->active, active_crtcs);
10212 WARN(pll->refcount != enabled_crtcs,
10213 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10214 pll->refcount, enabled_crtcs);
10215
10216 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10217 sizeof(dpll_hw_state)),
10218 "pll hw state mismatch\n");
10219 }
10220 }
10221
10222 void
10223 intel_modeset_check_state(struct drm_device *dev)
10224 {
10225 check_connector_state(dev);
10226 check_encoder_state(dev);
10227 check_crtc_state(dev);
10228 check_shared_dpll_state(dev);
10229 }
10230
10231 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10232 int dotclock)
10233 {
10234 /*
10235 * FDI already provided one idea for the dotclock.
10236 * Yell if the encoder disagrees.
10237 */
10238 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10239 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10240 pipe_config->adjusted_mode.crtc_clock, dotclock);
10241 }
10242
10243 static void update_scanline_offset(struct intel_crtc *crtc)
10244 {
10245 struct drm_device *dev = crtc->base.dev;
10246
10247 /*
10248 * The scanline counter increments at the leading edge of hsync.
10249 *
10250 * On most platforms it starts counting from vtotal-1 on the
10251 * first active line. That means the scanline counter value is
10252 * always one less than what we would expect. Ie. just after
10253 * start of vblank, which also occurs at start of hsync (on the
10254 * last active line), the scanline counter will read vblank_start-1.
10255 *
10256 * On gen2 the scanline counter starts counting from 1 instead
10257 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10258 * to keep the value positive), instead of adding one.
10259 *
10260 * On HSW+ the behaviour of the scanline counter depends on the output
10261 * type. For DP ports it behaves like most other platforms, but on HDMI
10262 * there's an extra 1 line difference. So we need to add two instead of
10263 * one to the value.
10264 */
10265 if (IS_GEN2(dev)) {
10266 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10267 int vtotal;
10268
10269 vtotal = mode->crtc_vtotal;
10270 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10271 vtotal /= 2;
10272
10273 crtc->scanline_offset = vtotal - 1;
10274 } else if (HAS_DDI(dev) &&
10275 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10276 crtc->scanline_offset = 2;
10277 } else
10278 crtc->scanline_offset = 1;
10279 }
10280
10281 static int __intel_set_mode(struct drm_crtc *crtc,
10282 struct drm_display_mode *mode,
10283 int x, int y, struct drm_framebuffer *fb)
10284 {
10285 struct drm_device *dev = crtc->dev;
10286 struct drm_i915_private *dev_priv = dev->dev_private;
10287 struct drm_display_mode *saved_mode;
10288 struct intel_crtc_config *pipe_config = NULL;
10289 struct intel_crtc *intel_crtc;
10290 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10291 int ret = 0;
10292
10293 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10294 if (!saved_mode)
10295 return -ENOMEM;
10296
10297 intel_modeset_affected_pipes(crtc, &modeset_pipes,
10298 &prepare_pipes, &disable_pipes);
10299
10300 *saved_mode = crtc->mode;
10301
10302 /* Hack: Because we don't (yet) support global modeset on multiple
10303 * crtcs, we don't keep track of the new mode for more than one crtc.
10304 * Hence simply check whether any bit is set in modeset_pipes in all the
10305 * pieces of code that are not yet converted to deal with mutliple crtcs
10306 * changing their mode at the same time. */
10307 if (modeset_pipes) {
10308 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10309 if (IS_ERR(pipe_config)) {
10310 ret = PTR_ERR(pipe_config);
10311 pipe_config = NULL;
10312
10313 goto out;
10314 }
10315 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10316 "[modeset]");
10317 to_intel_crtc(crtc)->new_config = pipe_config;
10318 }
10319
10320 /*
10321 * See if the config requires any additional preparation, e.g.
10322 * to adjust global state with pipes off. We need to do this
10323 * here so we can get the modeset_pipe updated config for the new
10324 * mode set on this crtc. For other crtcs we need to use the
10325 * adjusted_mode bits in the crtc directly.
10326 */
10327 if (IS_VALLEYVIEW(dev)) {
10328 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10329
10330 /* may have added more to prepare_pipes than we should */
10331 prepare_pipes &= ~disable_pipes;
10332 }
10333
10334 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10335 intel_crtc_disable(&intel_crtc->base);
10336
10337 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10338 if (intel_crtc->base.enabled)
10339 dev_priv->display.crtc_disable(&intel_crtc->base);
10340 }
10341
10342 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10343 * to set it here already despite that we pass it down the callchain.
10344 */
10345 if (modeset_pipes) {
10346 crtc->mode = *mode;
10347 /* mode_set/enable/disable functions rely on a correct pipe
10348 * config. */
10349 to_intel_crtc(crtc)->config = *pipe_config;
10350 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10351
10352 /*
10353 * Calculate and store various constants which
10354 * are later needed by vblank and swap-completion
10355 * timestamping. They are derived from true hwmode.
10356 */
10357 drm_calc_timestamping_constants(crtc,
10358 &pipe_config->adjusted_mode);
10359 }
10360
10361 /* Only after disabling all output pipelines that will be changed can we
10362 * update the the output configuration. */
10363 intel_modeset_update_state(dev, prepare_pipes);
10364
10365 if (dev_priv->display.modeset_global_resources)
10366 dev_priv->display.modeset_global_resources(dev);
10367
10368 /* Set up the DPLL and any encoders state that needs to adjust or depend
10369 * on the DPLL.
10370 */
10371 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10372 struct drm_framebuffer *old_fb;
10373
10374 mutex_lock(&dev->struct_mutex);
10375 ret = intel_pin_and_fence_fb_obj(dev,
10376 to_intel_framebuffer(fb)->obj,
10377 NULL);
10378 if (ret != 0) {
10379 DRM_ERROR("pin & fence failed\n");
10380 mutex_unlock(&dev->struct_mutex);
10381 goto done;
10382 }
10383 old_fb = crtc->primary->fb;
10384 if (old_fb)
10385 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
10386 mutex_unlock(&dev->struct_mutex);
10387
10388 crtc->primary->fb = fb;
10389 crtc->x = x;
10390 crtc->y = y;
10391
10392 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10393 x, y, fb);
10394 if (ret)
10395 goto done;
10396 }
10397
10398 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10399 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10400 update_scanline_offset(intel_crtc);
10401
10402 dev_priv->display.crtc_enable(&intel_crtc->base);
10403 }
10404
10405 /* FIXME: add subpixel order */
10406 done:
10407 if (ret && crtc->enabled)
10408 crtc->mode = *saved_mode;
10409
10410 out:
10411 kfree(pipe_config);
10412 kfree(saved_mode);
10413 return ret;
10414 }
10415
10416 static int intel_set_mode(struct drm_crtc *crtc,
10417 struct drm_display_mode *mode,
10418 int x, int y, struct drm_framebuffer *fb)
10419 {
10420 int ret;
10421
10422 ret = __intel_set_mode(crtc, mode, x, y, fb);
10423
10424 if (ret == 0)
10425 intel_modeset_check_state(crtc->dev);
10426
10427 return ret;
10428 }
10429
10430 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10431 {
10432 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10433 }
10434
10435 #undef for_each_intel_crtc_masked
10436
10437 static void intel_set_config_free(struct intel_set_config *config)
10438 {
10439 if (!config)
10440 return;
10441
10442 kfree(config->save_connector_encoders);
10443 kfree(config->save_encoder_crtcs);
10444 kfree(config->save_crtc_enabled);
10445 kfree(config);
10446 }
10447
10448 static int intel_set_config_save_state(struct drm_device *dev,
10449 struct intel_set_config *config)
10450 {
10451 struct drm_crtc *crtc;
10452 struct drm_encoder *encoder;
10453 struct drm_connector *connector;
10454 int count;
10455
10456 config->save_crtc_enabled =
10457 kcalloc(dev->mode_config.num_crtc,
10458 sizeof(bool), GFP_KERNEL);
10459 if (!config->save_crtc_enabled)
10460 return -ENOMEM;
10461
10462 config->save_encoder_crtcs =
10463 kcalloc(dev->mode_config.num_encoder,
10464 sizeof(struct drm_crtc *), GFP_KERNEL);
10465 if (!config->save_encoder_crtcs)
10466 return -ENOMEM;
10467
10468 config->save_connector_encoders =
10469 kcalloc(dev->mode_config.num_connector,
10470 sizeof(struct drm_encoder *), GFP_KERNEL);
10471 if (!config->save_connector_encoders)
10472 return -ENOMEM;
10473
10474 /* Copy data. Note that driver private data is not affected.
10475 * Should anything bad happen only the expected state is
10476 * restored, not the drivers personal bookkeeping.
10477 */
10478 count = 0;
10479 for_each_crtc(dev, crtc) {
10480 config->save_crtc_enabled[count++] = crtc->enabled;
10481 }
10482
10483 count = 0;
10484 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10485 config->save_encoder_crtcs[count++] = encoder->crtc;
10486 }
10487
10488 count = 0;
10489 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10490 config->save_connector_encoders[count++] = connector->encoder;
10491 }
10492
10493 return 0;
10494 }
10495
10496 static void intel_set_config_restore_state(struct drm_device *dev,
10497 struct intel_set_config *config)
10498 {
10499 struct intel_crtc *crtc;
10500 struct intel_encoder *encoder;
10501 struct intel_connector *connector;
10502 int count;
10503
10504 count = 0;
10505 for_each_intel_crtc(dev, crtc) {
10506 crtc->new_enabled = config->save_crtc_enabled[count++];
10507
10508 if (crtc->new_enabled)
10509 crtc->new_config = &crtc->config;
10510 else
10511 crtc->new_config = NULL;
10512 }
10513
10514 count = 0;
10515 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10516 encoder->new_crtc =
10517 to_intel_crtc(config->save_encoder_crtcs[count++]);
10518 }
10519
10520 count = 0;
10521 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10522 connector->new_encoder =
10523 to_intel_encoder(config->save_connector_encoders[count++]);
10524 }
10525 }
10526
10527 static bool
10528 is_crtc_connector_off(struct drm_mode_set *set)
10529 {
10530 int i;
10531
10532 if (set->num_connectors == 0)
10533 return false;
10534
10535 if (WARN_ON(set->connectors == NULL))
10536 return false;
10537
10538 for (i = 0; i < set->num_connectors; i++)
10539 if (set->connectors[i]->encoder &&
10540 set->connectors[i]->encoder->crtc == set->crtc &&
10541 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10542 return true;
10543
10544 return false;
10545 }
10546
10547 static void
10548 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10549 struct intel_set_config *config)
10550 {
10551
10552 /* We should be able to check here if the fb has the same properties
10553 * and then just flip_or_move it */
10554 if (is_crtc_connector_off(set)) {
10555 config->mode_changed = true;
10556 } else if (set->crtc->primary->fb != set->fb) {
10557 /* If we have no fb then treat it as a full mode set */
10558 if (set->crtc->primary->fb == NULL) {
10559 struct intel_crtc *intel_crtc =
10560 to_intel_crtc(set->crtc);
10561
10562 if (intel_crtc->active && i915.fastboot) {
10563 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10564 config->fb_changed = true;
10565 } else {
10566 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10567 config->mode_changed = true;
10568 }
10569 } else if (set->fb == NULL) {
10570 config->mode_changed = true;
10571 } else if (set->fb->pixel_format !=
10572 set->crtc->primary->fb->pixel_format) {
10573 config->mode_changed = true;
10574 } else {
10575 config->fb_changed = true;
10576 }
10577 }
10578
10579 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10580 config->fb_changed = true;
10581
10582 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10583 DRM_DEBUG_KMS("modes are different, full mode set\n");
10584 drm_mode_debug_printmodeline(&set->crtc->mode);
10585 drm_mode_debug_printmodeline(set->mode);
10586 config->mode_changed = true;
10587 }
10588
10589 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10590 set->crtc->base.id, config->mode_changed, config->fb_changed);
10591 }
10592
10593 static int
10594 intel_modeset_stage_output_state(struct drm_device *dev,
10595 struct drm_mode_set *set,
10596 struct intel_set_config *config)
10597 {
10598 struct intel_connector *connector;
10599 struct intel_encoder *encoder;
10600 struct intel_crtc *crtc;
10601 int ro;
10602
10603 /* The upper layers ensure that we either disable a crtc or have a list
10604 * of connectors. For paranoia, double-check this. */
10605 WARN_ON(!set->fb && (set->num_connectors != 0));
10606 WARN_ON(set->fb && (set->num_connectors == 0));
10607
10608 list_for_each_entry(connector, &dev->mode_config.connector_list,
10609 base.head) {
10610 /* Otherwise traverse passed in connector list and get encoders
10611 * for them. */
10612 for (ro = 0; ro < set->num_connectors; ro++) {
10613 if (set->connectors[ro] == &connector->base) {
10614 connector->new_encoder = connector->encoder;
10615 break;
10616 }
10617 }
10618
10619 /* If we disable the crtc, disable all its connectors. Also, if
10620 * the connector is on the changing crtc but not on the new
10621 * connector list, disable it. */
10622 if ((!set->fb || ro == set->num_connectors) &&
10623 connector->base.encoder &&
10624 connector->base.encoder->crtc == set->crtc) {
10625 connector->new_encoder = NULL;
10626
10627 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10628 connector->base.base.id,
10629 connector->base.name);
10630 }
10631
10632
10633 if (&connector->new_encoder->base != connector->base.encoder) {
10634 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10635 config->mode_changed = true;
10636 }
10637 }
10638 /* connector->new_encoder is now updated for all connectors. */
10639
10640 /* Update crtc of enabled connectors. */
10641 list_for_each_entry(connector, &dev->mode_config.connector_list,
10642 base.head) {
10643 struct drm_crtc *new_crtc;
10644
10645 if (!connector->new_encoder)
10646 continue;
10647
10648 new_crtc = connector->new_encoder->base.crtc;
10649
10650 for (ro = 0; ro < set->num_connectors; ro++) {
10651 if (set->connectors[ro] == &connector->base)
10652 new_crtc = set->crtc;
10653 }
10654
10655 /* Make sure the new CRTC will work with the encoder */
10656 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10657 new_crtc)) {
10658 return -EINVAL;
10659 }
10660 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10661
10662 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10663 connector->base.base.id,
10664 connector->base.name,
10665 new_crtc->base.id);
10666 }
10667
10668 /* Check for any encoders that needs to be disabled. */
10669 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10670 base.head) {
10671 int num_connectors = 0;
10672 list_for_each_entry(connector,
10673 &dev->mode_config.connector_list,
10674 base.head) {
10675 if (connector->new_encoder == encoder) {
10676 WARN_ON(!connector->new_encoder->new_crtc);
10677 num_connectors++;
10678 }
10679 }
10680
10681 if (num_connectors == 0)
10682 encoder->new_crtc = NULL;
10683 else if (num_connectors > 1)
10684 return -EINVAL;
10685
10686 /* Only now check for crtc changes so we don't miss encoders
10687 * that will be disabled. */
10688 if (&encoder->new_crtc->base != encoder->base.crtc) {
10689 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10690 config->mode_changed = true;
10691 }
10692 }
10693 /* Now we've also updated encoder->new_crtc for all encoders. */
10694
10695 for_each_intel_crtc(dev, crtc) {
10696 crtc->new_enabled = false;
10697
10698 list_for_each_entry(encoder,
10699 &dev->mode_config.encoder_list,
10700 base.head) {
10701 if (encoder->new_crtc == crtc) {
10702 crtc->new_enabled = true;
10703 break;
10704 }
10705 }
10706
10707 if (crtc->new_enabled != crtc->base.enabled) {
10708 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10709 crtc->new_enabled ? "en" : "dis");
10710 config->mode_changed = true;
10711 }
10712
10713 if (crtc->new_enabled)
10714 crtc->new_config = &crtc->config;
10715 else
10716 crtc->new_config = NULL;
10717 }
10718
10719 return 0;
10720 }
10721
10722 static void disable_crtc_nofb(struct intel_crtc *crtc)
10723 {
10724 struct drm_device *dev = crtc->base.dev;
10725 struct intel_encoder *encoder;
10726 struct intel_connector *connector;
10727
10728 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10729 pipe_name(crtc->pipe));
10730
10731 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10732 if (connector->new_encoder &&
10733 connector->new_encoder->new_crtc == crtc)
10734 connector->new_encoder = NULL;
10735 }
10736
10737 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10738 if (encoder->new_crtc == crtc)
10739 encoder->new_crtc = NULL;
10740 }
10741
10742 crtc->new_enabled = false;
10743 crtc->new_config = NULL;
10744 }
10745
10746 static int intel_crtc_set_config(struct drm_mode_set *set)
10747 {
10748 struct drm_device *dev;
10749 struct drm_mode_set save_set;
10750 struct intel_set_config *config;
10751 int ret;
10752
10753 BUG_ON(!set);
10754 BUG_ON(!set->crtc);
10755 BUG_ON(!set->crtc->helper_private);
10756
10757 /* Enforce sane interface api - has been abused by the fb helper. */
10758 BUG_ON(!set->mode && set->fb);
10759 BUG_ON(set->fb && set->num_connectors == 0);
10760
10761 if (set->fb) {
10762 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10763 set->crtc->base.id, set->fb->base.id,
10764 (int)set->num_connectors, set->x, set->y);
10765 } else {
10766 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10767 }
10768
10769 dev = set->crtc->dev;
10770
10771 ret = -ENOMEM;
10772 config = kzalloc(sizeof(*config), GFP_KERNEL);
10773 if (!config)
10774 goto out_config;
10775
10776 ret = intel_set_config_save_state(dev, config);
10777 if (ret)
10778 goto out_config;
10779
10780 save_set.crtc = set->crtc;
10781 save_set.mode = &set->crtc->mode;
10782 save_set.x = set->crtc->x;
10783 save_set.y = set->crtc->y;
10784 save_set.fb = set->crtc->primary->fb;
10785
10786 /* Compute whether we need a full modeset, only an fb base update or no
10787 * change at all. In the future we might also check whether only the
10788 * mode changed, e.g. for LVDS where we only change the panel fitter in
10789 * such cases. */
10790 intel_set_config_compute_mode_changes(set, config);
10791
10792 ret = intel_modeset_stage_output_state(dev, set, config);
10793 if (ret)
10794 goto fail;
10795
10796 if (config->mode_changed) {
10797 ret = intel_set_mode(set->crtc, set->mode,
10798 set->x, set->y, set->fb);
10799 } else if (config->fb_changed) {
10800 intel_crtc_wait_for_pending_flips(set->crtc);
10801
10802 ret = intel_pipe_set_base(set->crtc,
10803 set->x, set->y, set->fb);
10804 /*
10805 * In the fastboot case this may be our only check of the
10806 * state after boot. It would be better to only do it on
10807 * the first update, but we don't have a nice way of doing that
10808 * (and really, set_config isn't used much for high freq page
10809 * flipping, so increasing its cost here shouldn't be a big
10810 * deal).
10811 */
10812 if (i915.fastboot && ret == 0)
10813 intel_modeset_check_state(set->crtc->dev);
10814 }
10815
10816 if (ret) {
10817 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10818 set->crtc->base.id, ret);
10819 fail:
10820 intel_set_config_restore_state(dev, config);
10821
10822 /*
10823 * HACK: if the pipe was on, but we didn't have a framebuffer,
10824 * force the pipe off to avoid oopsing in the modeset code
10825 * due to fb==NULL. This should only happen during boot since
10826 * we don't yet reconstruct the FB from the hardware state.
10827 */
10828 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10829 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10830
10831 /* Try to restore the config */
10832 if (config->mode_changed &&
10833 intel_set_mode(save_set.crtc, save_set.mode,
10834 save_set.x, save_set.y, save_set.fb))
10835 DRM_ERROR("failed to restore config after modeset failure\n");
10836 }
10837
10838 out_config:
10839 intel_set_config_free(config);
10840 return ret;
10841 }
10842
10843 static const struct drm_crtc_funcs intel_crtc_funcs = {
10844 .cursor_set = intel_crtc_cursor_set,
10845 .cursor_move = intel_crtc_cursor_move,
10846 .gamma_set = intel_crtc_gamma_set,
10847 .set_config = intel_crtc_set_config,
10848 .destroy = intel_crtc_destroy,
10849 .page_flip = intel_crtc_page_flip,
10850 };
10851
10852 static void intel_cpu_pll_init(struct drm_device *dev)
10853 {
10854 if (HAS_DDI(dev))
10855 intel_ddi_pll_init(dev);
10856 }
10857
10858 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10859 struct intel_shared_dpll *pll,
10860 struct intel_dpll_hw_state *hw_state)
10861 {
10862 uint32_t val;
10863
10864 val = I915_READ(PCH_DPLL(pll->id));
10865 hw_state->dpll = val;
10866 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10867 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10868
10869 return val & DPLL_VCO_ENABLE;
10870 }
10871
10872 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10873 struct intel_shared_dpll *pll)
10874 {
10875 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10876 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10877 }
10878
10879 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10880 struct intel_shared_dpll *pll)
10881 {
10882 /* PCH refclock must be enabled first */
10883 ibx_assert_pch_refclk_enabled(dev_priv);
10884
10885 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10886
10887 /* Wait for the clocks to stabilize. */
10888 POSTING_READ(PCH_DPLL(pll->id));
10889 udelay(150);
10890
10891 /* The pixel multiplier can only be updated once the
10892 * DPLL is enabled and the clocks are stable.
10893 *
10894 * So write it again.
10895 */
10896 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10897 POSTING_READ(PCH_DPLL(pll->id));
10898 udelay(200);
10899 }
10900
10901 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10902 struct intel_shared_dpll *pll)
10903 {
10904 struct drm_device *dev = dev_priv->dev;
10905 struct intel_crtc *crtc;
10906
10907 /* Make sure no transcoder isn't still depending on us. */
10908 for_each_intel_crtc(dev, crtc) {
10909 if (intel_crtc_to_shared_dpll(crtc) == pll)
10910 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10911 }
10912
10913 I915_WRITE(PCH_DPLL(pll->id), 0);
10914 POSTING_READ(PCH_DPLL(pll->id));
10915 udelay(200);
10916 }
10917
10918 static char *ibx_pch_dpll_names[] = {
10919 "PCH DPLL A",
10920 "PCH DPLL B",
10921 };
10922
10923 static void ibx_pch_dpll_init(struct drm_device *dev)
10924 {
10925 struct drm_i915_private *dev_priv = dev->dev_private;
10926 int i;
10927
10928 dev_priv->num_shared_dpll = 2;
10929
10930 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10931 dev_priv->shared_dplls[i].id = i;
10932 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10933 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10934 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10935 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10936 dev_priv->shared_dplls[i].get_hw_state =
10937 ibx_pch_dpll_get_hw_state;
10938 }
10939 }
10940
10941 static void intel_shared_dpll_init(struct drm_device *dev)
10942 {
10943 struct drm_i915_private *dev_priv = dev->dev_private;
10944
10945 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10946 ibx_pch_dpll_init(dev);
10947 else
10948 dev_priv->num_shared_dpll = 0;
10949
10950 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10951 }
10952
10953 static void intel_crtc_init(struct drm_device *dev, int pipe)
10954 {
10955 struct drm_i915_private *dev_priv = dev->dev_private;
10956 struct intel_crtc *intel_crtc;
10957 int i;
10958
10959 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10960 if (intel_crtc == NULL)
10961 return;
10962
10963 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10964
10965 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10966 for (i = 0; i < 256; i++) {
10967 intel_crtc->lut_r[i] = i;
10968 intel_crtc->lut_g[i] = i;
10969 intel_crtc->lut_b[i] = i;
10970 }
10971
10972 /*
10973 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10974 * is hooked to plane B. Hence we want plane A feeding pipe B.
10975 */
10976 intel_crtc->pipe = pipe;
10977 intel_crtc->plane = pipe;
10978 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10979 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10980 intel_crtc->plane = !pipe;
10981 }
10982
10983 intel_crtc->cursor_base = ~0;
10984 intel_crtc->cursor_cntl = ~0;
10985
10986 init_waitqueue_head(&intel_crtc->vbl_wait);
10987
10988 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10989 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10990 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10991 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10992
10993 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10994
10995 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
10996 }
10997
10998 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10999 {
11000 struct drm_encoder *encoder = connector->base.encoder;
11001 struct drm_device *dev = connector->base.dev;
11002
11003 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11004
11005 if (!encoder)
11006 return INVALID_PIPE;
11007
11008 return to_intel_crtc(encoder->crtc)->pipe;
11009 }
11010
11011 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
11012 struct drm_file *file)
11013 {
11014 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11015 struct drm_mode_object *drmmode_obj;
11016 struct intel_crtc *crtc;
11017
11018 if (!drm_core_check_feature(dev, DRIVER_MODESET))
11019 return -ENODEV;
11020
11021 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
11022 DRM_MODE_OBJECT_CRTC);
11023
11024 if (!drmmode_obj) {
11025 DRM_ERROR("no such CRTC id\n");
11026 return -ENOENT;
11027 }
11028
11029 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
11030 pipe_from_crtc_id->pipe = crtc->pipe;
11031
11032 return 0;
11033 }
11034
11035 static int intel_encoder_clones(struct intel_encoder *encoder)
11036 {
11037 struct drm_device *dev = encoder->base.dev;
11038 struct intel_encoder *source_encoder;
11039 int index_mask = 0;
11040 int entry = 0;
11041
11042 list_for_each_entry(source_encoder,
11043 &dev->mode_config.encoder_list, base.head) {
11044 if (encoders_cloneable(encoder, source_encoder))
11045 index_mask |= (1 << entry);
11046
11047 entry++;
11048 }
11049
11050 return index_mask;
11051 }
11052
11053 static bool has_edp_a(struct drm_device *dev)
11054 {
11055 struct drm_i915_private *dev_priv = dev->dev_private;
11056
11057 if (!IS_MOBILE(dev))
11058 return false;
11059
11060 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11061 return false;
11062
11063 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
11064 return false;
11065
11066 return true;
11067 }
11068
11069 const char *intel_output_name(int output)
11070 {
11071 static const char *names[] = {
11072 [INTEL_OUTPUT_UNUSED] = "Unused",
11073 [INTEL_OUTPUT_ANALOG] = "Analog",
11074 [INTEL_OUTPUT_DVO] = "DVO",
11075 [INTEL_OUTPUT_SDVO] = "SDVO",
11076 [INTEL_OUTPUT_LVDS] = "LVDS",
11077 [INTEL_OUTPUT_TVOUT] = "TV",
11078 [INTEL_OUTPUT_HDMI] = "HDMI",
11079 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
11080 [INTEL_OUTPUT_EDP] = "eDP",
11081 [INTEL_OUTPUT_DSI] = "DSI",
11082 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
11083 };
11084
11085 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11086 return "Invalid";
11087
11088 return names[output];
11089 }
11090
11091 static void intel_setup_outputs(struct drm_device *dev)
11092 {
11093 struct drm_i915_private *dev_priv = dev->dev_private;
11094 struct intel_encoder *encoder;
11095 bool dpd_is_edp = false;
11096
11097 intel_lvds_init(dev);
11098
11099 if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev) && dev_priv->vbt.int_crt_support)
11100 intel_crt_init(dev);
11101
11102 if (HAS_DDI(dev)) {
11103 int found;
11104
11105 /* Haswell uses DDI functions to detect digital outputs */
11106 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
11107 /* DDI A only supports eDP */
11108 if (found)
11109 intel_ddi_init(dev, PORT_A);
11110
11111 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11112 * register */
11113 found = I915_READ(SFUSE_STRAP);
11114
11115 if (found & SFUSE_STRAP_DDIB_DETECTED)
11116 intel_ddi_init(dev, PORT_B);
11117 if (found & SFUSE_STRAP_DDIC_DETECTED)
11118 intel_ddi_init(dev, PORT_C);
11119 if (found & SFUSE_STRAP_DDID_DETECTED)
11120 intel_ddi_init(dev, PORT_D);
11121 } else if (HAS_PCH_SPLIT(dev)) {
11122 int found;
11123 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
11124
11125 if (has_edp_a(dev))
11126 intel_dp_init(dev, DP_A, PORT_A);
11127
11128 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
11129 /* PCH SDVOB multiplex with HDMIB */
11130 found = intel_sdvo_init(dev, PCH_SDVOB, true);
11131 if (!found)
11132 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
11133 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
11134 intel_dp_init(dev, PCH_DP_B, PORT_B);
11135 }
11136
11137 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
11138 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
11139
11140 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
11141 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
11142
11143 if (I915_READ(PCH_DP_C) & DP_DETECTED)
11144 intel_dp_init(dev, PCH_DP_C, PORT_C);
11145
11146 if (I915_READ(PCH_DP_D) & DP_DETECTED)
11147 intel_dp_init(dev, PCH_DP_D, PORT_D);
11148 } else if (IS_VALLEYVIEW(dev)) {
11149 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11150 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11151 PORT_B);
11152 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11153 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11154 }
11155
11156 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11157 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11158 PORT_C);
11159 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
11160 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
11161 }
11162
11163 if (IS_CHERRYVIEW(dev)) {
11164 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
11165 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
11166 PORT_D);
11167 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
11168 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
11169 }
11170 }
11171
11172 intel_dsi_init(dev);
11173 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
11174 bool found = false;
11175
11176 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11177 DRM_DEBUG_KMS("probing SDVOB\n");
11178 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
11179 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
11180 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
11181 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
11182 }
11183
11184 if (!found && SUPPORTS_INTEGRATED_DP(dev))
11185 intel_dp_init(dev, DP_B, PORT_B);
11186 }
11187
11188 /* Before G4X SDVOC doesn't have its own detect register */
11189
11190 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11191 DRM_DEBUG_KMS("probing SDVOC\n");
11192 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
11193 }
11194
11195 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
11196
11197 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11198 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
11199 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
11200 }
11201 if (SUPPORTS_INTEGRATED_DP(dev))
11202 intel_dp_init(dev, DP_C, PORT_C);
11203 }
11204
11205 if (SUPPORTS_INTEGRATED_DP(dev) &&
11206 (I915_READ(DP_D) & DP_DETECTED))
11207 intel_dp_init(dev, DP_D, PORT_D);
11208 } else if (IS_GEN2(dev))
11209 intel_dvo_init(dev);
11210
11211 if (SUPPORTS_TV(dev))
11212 intel_tv_init(dev);
11213
11214 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11215 encoder->base.possible_crtcs = encoder->crtc_mask;
11216 encoder->base.possible_clones =
11217 intel_encoder_clones(encoder);
11218 }
11219
11220 intel_init_pch_refclk(dev);
11221
11222 drm_helper_move_panel_connectors_to_head(dev);
11223 }
11224
11225 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11226 {
11227 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11228
11229 drm_framebuffer_cleanup(fb);
11230 WARN_ON(!intel_fb->obj->framebuffer_references--);
11231 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
11232 kfree(intel_fb);
11233 }
11234
11235 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
11236 struct drm_file *file,
11237 unsigned int *handle)
11238 {
11239 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11240 struct drm_i915_gem_object *obj = intel_fb->obj;
11241
11242 return drm_gem_handle_create(file, &obj->base, handle);
11243 }
11244
11245 static const struct drm_framebuffer_funcs intel_fb_funcs = {
11246 .destroy = intel_user_framebuffer_destroy,
11247 .create_handle = intel_user_framebuffer_create_handle,
11248 };
11249
11250 static int intel_framebuffer_init(struct drm_device *dev,
11251 struct intel_framebuffer *intel_fb,
11252 struct drm_mode_fb_cmd2 *mode_cmd,
11253 struct drm_i915_gem_object *obj)
11254 {
11255 int aligned_height;
11256 int pitch_limit;
11257 int ret;
11258
11259 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
11260
11261 if (obj->tiling_mode == I915_TILING_Y) {
11262 DRM_DEBUG("hardware does not support tiling Y\n");
11263 return -EINVAL;
11264 }
11265
11266 if (mode_cmd->pitches[0] & 63) {
11267 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
11268 mode_cmd->pitches[0]);
11269 return -EINVAL;
11270 }
11271
11272 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
11273 pitch_limit = 32*1024;
11274 } else if (INTEL_INFO(dev)->gen >= 4) {
11275 if (obj->tiling_mode)
11276 pitch_limit = 16*1024;
11277 else
11278 pitch_limit = 32*1024;
11279 } else if (INTEL_INFO(dev)->gen >= 3) {
11280 if (obj->tiling_mode)
11281 pitch_limit = 8*1024;
11282 else
11283 pitch_limit = 16*1024;
11284 } else
11285 /* XXX DSPC is limited to 4k tiled */
11286 pitch_limit = 8*1024;
11287
11288 if (mode_cmd->pitches[0] > pitch_limit) {
11289 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
11290 obj->tiling_mode ? "tiled" : "linear",
11291 mode_cmd->pitches[0], pitch_limit);
11292 return -EINVAL;
11293 }
11294
11295 if (obj->tiling_mode != I915_TILING_NONE &&
11296 mode_cmd->pitches[0] != obj->stride) {
11297 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
11298 mode_cmd->pitches[0], obj->stride);
11299 return -EINVAL;
11300 }
11301
11302 /* Reject formats not supported by any plane early. */
11303 switch (mode_cmd->pixel_format) {
11304 case DRM_FORMAT_C8:
11305 case DRM_FORMAT_RGB565:
11306 case DRM_FORMAT_XRGB8888:
11307 case DRM_FORMAT_ARGB8888:
11308 break;
11309 case DRM_FORMAT_XRGB1555:
11310 case DRM_FORMAT_ARGB1555:
11311 if (INTEL_INFO(dev)->gen > 3) {
11312 DRM_DEBUG("unsupported pixel format: %s\n",
11313 drm_get_format_name(mode_cmd->pixel_format));
11314 return -EINVAL;
11315 }
11316 break;
11317 case DRM_FORMAT_XBGR8888:
11318 case DRM_FORMAT_ABGR8888:
11319 case DRM_FORMAT_XRGB2101010:
11320 case DRM_FORMAT_ARGB2101010:
11321 case DRM_FORMAT_XBGR2101010:
11322 case DRM_FORMAT_ABGR2101010:
11323 if (INTEL_INFO(dev)->gen < 4) {
11324 DRM_DEBUG("unsupported pixel format: %s\n",
11325 drm_get_format_name(mode_cmd->pixel_format));
11326 return -EINVAL;
11327 }
11328 break;
11329 case DRM_FORMAT_YUYV:
11330 case DRM_FORMAT_UYVY:
11331 case DRM_FORMAT_YVYU:
11332 case DRM_FORMAT_VYUY:
11333 if (INTEL_INFO(dev)->gen < 5) {
11334 DRM_DEBUG("unsupported pixel format: %s\n",
11335 drm_get_format_name(mode_cmd->pixel_format));
11336 return -EINVAL;
11337 }
11338 break;
11339 default:
11340 DRM_DEBUG("unsupported pixel format: %s\n",
11341 drm_get_format_name(mode_cmd->pixel_format));
11342 return -EINVAL;
11343 }
11344
11345 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
11346 if (mode_cmd->offsets[0] != 0)
11347 return -EINVAL;
11348
11349 aligned_height = intel_align_height(dev, mode_cmd->height,
11350 obj->tiling_mode);
11351 /* FIXME drm helper for size checks (especially planar formats)? */
11352 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
11353 return -EINVAL;
11354
11355 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
11356 intel_fb->obj = obj;
11357 intel_fb->obj->framebuffer_references++;
11358
11359 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
11360 if (ret) {
11361 DRM_ERROR("framebuffer init failed %d\n", ret);
11362 return ret;
11363 }
11364
11365 return 0;
11366 }
11367
11368 static struct drm_framebuffer *
11369 intel_user_framebuffer_create(struct drm_device *dev,
11370 struct drm_file *filp,
11371 struct drm_mode_fb_cmd2 *mode_cmd)
11372 {
11373 struct drm_i915_gem_object *obj;
11374
11375 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
11376 mode_cmd->handles[0]));
11377 if (&obj->base == NULL)
11378 return ERR_PTR(-ENOENT);
11379
11380 return intel_framebuffer_create(dev, mode_cmd, obj);
11381 }
11382
11383 #ifndef CONFIG_DRM_I915_FBDEV
11384 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
11385 {
11386 }
11387 #endif
11388
11389 static const struct drm_mode_config_funcs intel_mode_funcs = {
11390 .fb_create = intel_user_framebuffer_create,
11391 .output_poll_changed = intel_fbdev_output_poll_changed,
11392 };
11393
11394 /* Set up chip specific display functions */
11395 static void intel_init_display(struct drm_device *dev)
11396 {
11397 struct drm_i915_private *dev_priv = dev->dev_private;
11398
11399 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
11400 dev_priv->display.find_dpll = g4x_find_best_dpll;
11401 else if (IS_CHERRYVIEW(dev))
11402 dev_priv->display.find_dpll = chv_find_best_dpll;
11403 else if (IS_VALLEYVIEW(dev))
11404 dev_priv->display.find_dpll = vlv_find_best_dpll;
11405 else if (IS_PINEVIEW(dev))
11406 dev_priv->display.find_dpll = pnv_find_best_dpll;
11407 else
11408 dev_priv->display.find_dpll = i9xx_find_best_dpll;
11409
11410 if (HAS_DDI(dev)) {
11411 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
11412 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11413 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
11414 dev_priv->display.crtc_enable = haswell_crtc_enable;
11415 dev_priv->display.crtc_disable = haswell_crtc_disable;
11416 dev_priv->display.off = haswell_crtc_off;
11417 dev_priv->display.update_primary_plane =
11418 ironlake_update_primary_plane;
11419 } else if (HAS_PCH_SPLIT(dev)) {
11420 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
11421 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11422 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
11423 dev_priv->display.crtc_enable = ironlake_crtc_enable;
11424 dev_priv->display.crtc_disable = ironlake_crtc_disable;
11425 dev_priv->display.off = ironlake_crtc_off;
11426 dev_priv->display.update_primary_plane =
11427 ironlake_update_primary_plane;
11428 } else if (IS_VALLEYVIEW(dev)) {
11429 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11430 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11431 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11432 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11433 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11434 dev_priv->display.off = i9xx_crtc_off;
11435 dev_priv->display.update_primary_plane =
11436 i9xx_update_primary_plane;
11437 } else {
11438 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11439 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11440 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11441 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11442 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11443 dev_priv->display.off = i9xx_crtc_off;
11444 dev_priv->display.update_primary_plane =
11445 i9xx_update_primary_plane;
11446 }
11447
11448 /* Returns the core display clock speed */
11449 if (IS_VALLEYVIEW(dev))
11450 dev_priv->display.get_display_clock_speed =
11451 valleyview_get_display_clock_speed;
11452 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11453 dev_priv->display.get_display_clock_speed =
11454 i945_get_display_clock_speed;
11455 else if (IS_I915G(dev))
11456 dev_priv->display.get_display_clock_speed =
11457 i915_get_display_clock_speed;
11458 else if (IS_I945GM(dev) || IS_845G(dev))
11459 dev_priv->display.get_display_clock_speed =
11460 i9xx_misc_get_display_clock_speed;
11461 else if (IS_PINEVIEW(dev))
11462 dev_priv->display.get_display_clock_speed =
11463 pnv_get_display_clock_speed;
11464 else if (IS_I915GM(dev))
11465 dev_priv->display.get_display_clock_speed =
11466 i915gm_get_display_clock_speed;
11467 else if (IS_I865G(dev))
11468 dev_priv->display.get_display_clock_speed =
11469 i865_get_display_clock_speed;
11470 else if (IS_I85X(dev))
11471 dev_priv->display.get_display_clock_speed =
11472 i855_get_display_clock_speed;
11473 else /* 852, 830 */
11474 dev_priv->display.get_display_clock_speed =
11475 i830_get_display_clock_speed;
11476
11477 if (HAS_PCH_SPLIT(dev)) {
11478 if (IS_GEN5(dev)) {
11479 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
11480 dev_priv->display.write_eld = ironlake_write_eld;
11481 } else if (IS_GEN6(dev)) {
11482 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
11483 dev_priv->display.write_eld = ironlake_write_eld;
11484 dev_priv->display.modeset_global_resources =
11485 snb_modeset_global_resources;
11486 } else if (IS_IVYBRIDGE(dev)) {
11487 /* FIXME: detect B0+ stepping and use auto training */
11488 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
11489 dev_priv->display.write_eld = ironlake_write_eld;
11490 dev_priv->display.modeset_global_resources =
11491 ivb_modeset_global_resources;
11492 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
11493 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
11494 dev_priv->display.write_eld = haswell_write_eld;
11495 dev_priv->display.modeset_global_resources =
11496 haswell_modeset_global_resources;
11497 }
11498 } else if (IS_G4X(dev)) {
11499 dev_priv->display.write_eld = g4x_write_eld;
11500 } else if (IS_VALLEYVIEW(dev)) {
11501 dev_priv->display.modeset_global_resources =
11502 valleyview_modeset_global_resources;
11503 dev_priv->display.write_eld = ironlake_write_eld;
11504 }
11505
11506 /* Default just returns -ENODEV to indicate unsupported */
11507 dev_priv->display.queue_flip = intel_default_queue_flip;
11508
11509 switch (INTEL_INFO(dev)->gen) {
11510 case 2:
11511 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11512 break;
11513
11514 case 3:
11515 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11516 break;
11517
11518 case 4:
11519 case 5:
11520 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11521 break;
11522
11523 case 6:
11524 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11525 break;
11526 case 7:
11527 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11528 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11529 break;
11530 }
11531
11532 intel_panel_init_backlight_funcs(dev);
11533 }
11534
11535 /*
11536 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11537 * resume, or other times. This quirk makes sure that's the case for
11538 * affected systems.
11539 */
11540 static void quirk_pipea_force(struct drm_device *dev)
11541 {
11542 struct drm_i915_private *dev_priv = dev->dev_private;
11543
11544 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11545 DRM_INFO("applying pipe a force quirk\n");
11546 }
11547
11548 /*
11549 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11550 */
11551 static void quirk_ssc_force_disable(struct drm_device *dev)
11552 {
11553 struct drm_i915_private *dev_priv = dev->dev_private;
11554 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11555 DRM_INFO("applying lvds SSC disable quirk\n");
11556 }
11557
11558 /*
11559 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11560 * brightness value
11561 */
11562 static void quirk_invert_brightness(struct drm_device *dev)
11563 {
11564 struct drm_i915_private *dev_priv = dev->dev_private;
11565 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11566 DRM_INFO("applying inverted panel brightness quirk\n");
11567 }
11568
11569 struct intel_quirk {
11570 int device;
11571 int subsystem_vendor;
11572 int subsystem_device;
11573 void (*hook)(struct drm_device *dev);
11574 };
11575
11576 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11577 struct intel_dmi_quirk {
11578 void (*hook)(struct drm_device *dev);
11579 const struct dmi_system_id (*dmi_id_list)[];
11580 };
11581
11582 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11583 {
11584 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11585 return 1;
11586 }
11587
11588 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11589 {
11590 .dmi_id_list = &(const struct dmi_system_id[]) {
11591 {
11592 .callback = intel_dmi_reverse_brightness,
11593 .ident = "NCR Corporation",
11594 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11595 DMI_MATCH(DMI_PRODUCT_NAME, ""),
11596 },
11597 },
11598 { } /* terminating entry */
11599 },
11600 .hook = quirk_invert_brightness,
11601 },
11602 };
11603
11604 static struct intel_quirk intel_quirks[] = {
11605 /* HP Mini needs pipe A force quirk (LP: #322104) */
11606 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11607
11608 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11609 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11610
11611 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11612 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11613
11614 /* Lenovo U160 cannot use SSC on LVDS */
11615 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11616
11617 /* Sony Vaio Y cannot use SSC on LVDS */
11618 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
11619
11620 /* Acer Aspire 5734Z must invert backlight brightness */
11621 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11622
11623 /* Acer/eMachines G725 */
11624 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11625
11626 /* Acer/eMachines e725 */
11627 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11628
11629 /* Acer/Packard Bell NCL20 */
11630 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11631
11632 /* Acer Aspire 4736Z */
11633 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
11634
11635 /* Acer Aspire 5336 */
11636 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11637 };
11638
11639 static void intel_init_quirks(struct drm_device *dev)
11640 {
11641 struct pci_dev *d = dev->pdev;
11642 int i;
11643
11644 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11645 struct intel_quirk *q = &intel_quirks[i];
11646
11647 if (d->device == q->device &&
11648 (d->subsystem_vendor == q->subsystem_vendor ||
11649 q->subsystem_vendor == PCI_ANY_ID) &&
11650 (d->subsystem_device == q->subsystem_device ||
11651 q->subsystem_device == PCI_ANY_ID))
11652 q->hook(dev);
11653 }
11654 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11655 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11656 intel_dmi_quirks[i].hook(dev);
11657 }
11658 }
11659
11660 /* Disable the VGA plane that we never use */
11661 static void i915_disable_vga(struct drm_device *dev)
11662 {
11663 struct drm_i915_private *dev_priv = dev->dev_private;
11664 u8 sr1;
11665 u32 vga_reg = i915_vgacntrl_reg(dev);
11666
11667 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11668 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11669 outb(SR01, VGA_SR_INDEX);
11670 sr1 = inb(VGA_SR_DATA);
11671 outb(sr1 | 1<<5, VGA_SR_DATA);
11672 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11673 udelay(300);
11674
11675 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11676 POSTING_READ(vga_reg);
11677 }
11678
11679 void intel_modeset_init_hw(struct drm_device *dev)
11680 {
11681 intel_prepare_ddi(dev);
11682
11683 intel_init_clock_gating(dev);
11684
11685 intel_reset_dpio(dev);
11686
11687 intel_enable_gt_powersave(dev);
11688 }
11689
11690 void intel_modeset_suspend_hw(struct drm_device *dev)
11691 {
11692 intel_suspend_hw(dev);
11693 }
11694
11695 void intel_modeset_init(struct drm_device *dev)
11696 {
11697 struct drm_i915_private *dev_priv = dev->dev_private;
11698 int sprite, ret;
11699 enum pipe pipe;
11700 struct intel_crtc *crtc;
11701
11702 drm_mode_config_init(dev);
11703
11704 dev->mode_config.min_width = 0;
11705 dev->mode_config.min_height = 0;
11706
11707 dev->mode_config.preferred_depth = 24;
11708 dev->mode_config.prefer_shadow = 1;
11709
11710 dev->mode_config.funcs = &intel_mode_funcs;
11711
11712 intel_init_quirks(dev);
11713
11714 intel_init_pm(dev);
11715
11716 if (INTEL_INFO(dev)->num_pipes == 0)
11717 return;
11718
11719 intel_init_display(dev);
11720
11721 if (IS_GEN2(dev)) {
11722 dev->mode_config.max_width = 2048;
11723 dev->mode_config.max_height = 2048;
11724 } else if (IS_GEN3(dev)) {
11725 dev->mode_config.max_width = 4096;
11726 dev->mode_config.max_height = 4096;
11727 } else {
11728 dev->mode_config.max_width = 8192;
11729 dev->mode_config.max_height = 8192;
11730 }
11731
11732 if (IS_GEN2(dev)) {
11733 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
11734 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
11735 } else {
11736 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
11737 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
11738 }
11739
11740 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11741
11742 DRM_DEBUG_KMS("%d display pipe%s available.\n",
11743 INTEL_INFO(dev)->num_pipes,
11744 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11745
11746 for_each_pipe(pipe) {
11747 intel_crtc_init(dev, pipe);
11748 for_each_sprite(pipe, sprite) {
11749 ret = intel_plane_init(dev, pipe, sprite);
11750 if (ret)
11751 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11752 pipe_name(pipe), sprite_name(pipe, sprite), ret);
11753 }
11754 }
11755
11756 intel_init_dpio(dev);
11757 intel_reset_dpio(dev);
11758
11759 intel_cpu_pll_init(dev);
11760 intel_shared_dpll_init(dev);
11761
11762 /* Just disable it once at startup */
11763 i915_disable_vga(dev);
11764 intel_setup_outputs(dev);
11765
11766 /* Just in case the BIOS is doing something questionable. */
11767 intel_disable_fbc(dev);
11768
11769 drm_modeset_lock_all(dev);
11770 intel_modeset_setup_hw_state(dev, false);
11771 drm_modeset_unlock_all(dev);
11772
11773 for_each_intel_crtc(dev, crtc) {
11774 if (!crtc->active)
11775 continue;
11776
11777 /*
11778 * Note that reserving the BIOS fb up front prevents us
11779 * from stuffing other stolen allocations like the ring
11780 * on top. This prevents some ugliness at boot time, and
11781 * can even allow for smooth boot transitions if the BIOS
11782 * fb is large enough for the active pipe configuration.
11783 */
11784 if (dev_priv->display.get_plane_config) {
11785 dev_priv->display.get_plane_config(crtc,
11786 &crtc->plane_config);
11787 /*
11788 * If the fb is shared between multiple heads, we'll
11789 * just get the first one.
11790 */
11791 intel_find_plane_obj(crtc, &crtc->plane_config);
11792 }
11793 }
11794 }
11795
11796 static void intel_enable_pipe_a(struct drm_device *dev)
11797 {
11798 struct intel_connector *connector;
11799 struct drm_connector *crt = NULL;
11800 struct intel_load_detect_pipe load_detect_temp;
11801 struct drm_modeset_acquire_ctx ctx;
11802
11803 /* We can't just switch on the pipe A, we need to set things up with a
11804 * proper mode and output configuration. As a gross hack, enable pipe A
11805 * by enabling the load detect pipe once. */
11806 list_for_each_entry(connector,
11807 &dev->mode_config.connector_list,
11808 base.head) {
11809 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11810 crt = &connector->base;
11811 break;
11812 }
11813 }
11814
11815 if (!crt)
11816 return;
11817
11818 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx))
11819 intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx);
11820
11821
11822 }
11823
11824 static bool
11825 intel_check_plane_mapping(struct intel_crtc *crtc)
11826 {
11827 struct drm_device *dev = crtc->base.dev;
11828 struct drm_i915_private *dev_priv = dev->dev_private;
11829 u32 reg, val;
11830
11831 if (INTEL_INFO(dev)->num_pipes == 1)
11832 return true;
11833
11834 reg = DSPCNTR(!crtc->plane);
11835 val = I915_READ(reg);
11836
11837 if ((val & DISPLAY_PLANE_ENABLE) &&
11838 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11839 return false;
11840
11841 return true;
11842 }
11843
11844 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11845 {
11846 struct drm_device *dev = crtc->base.dev;
11847 struct drm_i915_private *dev_priv = dev->dev_private;
11848 u32 reg;
11849
11850 /* Clear any frame start delays used for debugging left by the BIOS */
11851 reg = PIPECONF(crtc->config.cpu_transcoder);
11852 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11853
11854 /* restore vblank interrupts to correct state */
11855 if (crtc->active)
11856 drm_vblank_on(dev, crtc->pipe);
11857 else
11858 drm_vblank_off(dev, crtc->pipe);
11859
11860 /* We need to sanitize the plane -> pipe mapping first because this will
11861 * disable the crtc (and hence change the state) if it is wrong. Note
11862 * that gen4+ has a fixed plane -> pipe mapping. */
11863 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11864 struct intel_connector *connector;
11865 bool plane;
11866
11867 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11868 crtc->base.base.id);
11869
11870 /* Pipe has the wrong plane attached and the plane is active.
11871 * Temporarily change the plane mapping and disable everything
11872 * ... */
11873 plane = crtc->plane;
11874 crtc->plane = !plane;
11875 dev_priv->display.crtc_disable(&crtc->base);
11876 crtc->plane = plane;
11877
11878 /* ... and break all links. */
11879 list_for_each_entry(connector, &dev->mode_config.connector_list,
11880 base.head) {
11881 if (connector->encoder->base.crtc != &crtc->base)
11882 continue;
11883
11884 connector->base.dpms = DRM_MODE_DPMS_OFF;
11885 connector->base.encoder = NULL;
11886 }
11887 /* multiple connectors may have the same encoder:
11888 * handle them and break crtc link separately */
11889 list_for_each_entry(connector, &dev->mode_config.connector_list,
11890 base.head)
11891 if (connector->encoder->base.crtc == &crtc->base) {
11892 connector->encoder->base.crtc = NULL;
11893 connector->encoder->connectors_active = false;
11894 }
11895
11896 WARN_ON(crtc->active);
11897 crtc->base.enabled = false;
11898 }
11899
11900 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11901 crtc->pipe == PIPE_A && !crtc->active) {
11902 /* BIOS forgot to enable pipe A, this mostly happens after
11903 * resume. Force-enable the pipe to fix this, the update_dpms
11904 * call below we restore the pipe to the right state, but leave
11905 * the required bits on. */
11906 intel_enable_pipe_a(dev);
11907 }
11908
11909 /* Adjust the state of the output pipe according to whether we
11910 * have active connectors/encoders. */
11911 intel_crtc_update_dpms(&crtc->base);
11912
11913 if (crtc->active != crtc->base.enabled) {
11914 struct intel_encoder *encoder;
11915
11916 /* This can happen either due to bugs in the get_hw_state
11917 * functions or because the pipe is force-enabled due to the
11918 * pipe A quirk. */
11919 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11920 crtc->base.base.id,
11921 crtc->base.enabled ? "enabled" : "disabled",
11922 crtc->active ? "enabled" : "disabled");
11923
11924 crtc->base.enabled = crtc->active;
11925
11926 /* Because we only establish the connector -> encoder ->
11927 * crtc links if something is active, this means the
11928 * crtc is now deactivated. Break the links. connector
11929 * -> encoder links are only establish when things are
11930 * actually up, hence no need to break them. */
11931 WARN_ON(crtc->active);
11932
11933 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11934 WARN_ON(encoder->connectors_active);
11935 encoder->base.crtc = NULL;
11936 }
11937 }
11938
11939 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
11940 /*
11941 * We start out with underrun reporting disabled to avoid races.
11942 * For correct bookkeeping mark this on active crtcs.
11943 *
11944 * Also on gmch platforms we dont have any hardware bits to
11945 * disable the underrun reporting. Which means we need to start
11946 * out with underrun reporting disabled also on inactive pipes,
11947 * since otherwise we'll complain about the garbage we read when
11948 * e.g. coming up after runtime pm.
11949 *
11950 * No protection against concurrent access is required - at
11951 * worst a fifo underrun happens which also sets this to false.
11952 */
11953 crtc->cpu_fifo_underrun_disabled = true;
11954 crtc->pch_fifo_underrun_disabled = true;
11955
11956 update_scanline_offset(crtc);
11957 }
11958 }
11959
11960 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11961 {
11962 struct intel_connector *connector;
11963 struct drm_device *dev = encoder->base.dev;
11964
11965 /* We need to check both for a crtc link (meaning that the
11966 * encoder is active and trying to read from a pipe) and the
11967 * pipe itself being active. */
11968 bool has_active_crtc = encoder->base.crtc &&
11969 to_intel_crtc(encoder->base.crtc)->active;
11970
11971 if (encoder->connectors_active && !has_active_crtc) {
11972 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11973 encoder->base.base.id,
11974 encoder->base.name);
11975
11976 /* Connector is active, but has no active pipe. This is
11977 * fallout from our resume register restoring. Disable
11978 * the encoder manually again. */
11979 if (encoder->base.crtc) {
11980 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11981 encoder->base.base.id,
11982 encoder->base.name);
11983 encoder->disable(encoder);
11984 }
11985 encoder->base.crtc = NULL;
11986 encoder->connectors_active = false;
11987
11988 /* Inconsistent output/port/pipe state happens presumably due to
11989 * a bug in one of the get_hw_state functions. Or someplace else
11990 * in our code, like the register restore mess on resume. Clamp
11991 * things to off as a safer default. */
11992 list_for_each_entry(connector,
11993 &dev->mode_config.connector_list,
11994 base.head) {
11995 if (connector->encoder != encoder)
11996 continue;
11997 connector->base.dpms = DRM_MODE_DPMS_OFF;
11998 connector->base.encoder = NULL;
11999 }
12000 }
12001 /* Enabled encoders without active connectors will be fixed in
12002 * the crtc fixup. */
12003 }
12004
12005 void i915_redisable_vga_power_on(struct drm_device *dev)
12006 {
12007 struct drm_i915_private *dev_priv = dev->dev_private;
12008 u32 vga_reg = i915_vgacntrl_reg(dev);
12009
12010 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
12011 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12012 i915_disable_vga(dev);
12013 }
12014 }
12015
12016 void i915_redisable_vga(struct drm_device *dev)
12017 {
12018 struct drm_i915_private *dev_priv = dev->dev_private;
12019
12020 /* This function can be called both from intel_modeset_setup_hw_state or
12021 * at a very early point in our resume sequence, where the power well
12022 * structures are not yet restored. Since this function is at a very
12023 * paranoid "someone might have enabled VGA while we were not looking"
12024 * level, just check if the power well is enabled instead of trying to
12025 * follow the "don't touch the power well if we don't need it" policy
12026 * the rest of the driver uses. */
12027 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
12028 return;
12029
12030 i915_redisable_vga_power_on(dev);
12031 }
12032
12033 static bool primary_get_hw_state(struct intel_crtc *crtc)
12034 {
12035 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
12036
12037 if (!crtc->active)
12038 return false;
12039
12040 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
12041 }
12042
12043 static void intel_modeset_readout_hw_state(struct drm_device *dev)
12044 {
12045 struct drm_i915_private *dev_priv = dev->dev_private;
12046 enum pipe pipe;
12047 struct intel_crtc *crtc;
12048 struct intel_encoder *encoder;
12049 struct intel_connector *connector;
12050 int i;
12051
12052 for_each_intel_crtc(dev, crtc) {
12053 memset(&crtc->config, 0, sizeof(crtc->config));
12054
12055 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
12056
12057 crtc->active = dev_priv->display.get_pipe_config(crtc,
12058 &crtc->config);
12059
12060 crtc->base.enabled = crtc->active;
12061 crtc->primary_enabled = primary_get_hw_state(crtc);
12062
12063 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
12064 crtc->base.base.id,
12065 crtc->active ? "enabled" : "disabled");
12066 }
12067
12068 /* FIXME: Smash this into the new shared dpll infrastructure. */
12069 if (HAS_DDI(dev))
12070 intel_ddi_setup_hw_pll_state(dev);
12071
12072 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12073 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12074
12075 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
12076 pll->active = 0;
12077 for_each_intel_crtc(dev, crtc) {
12078 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12079 pll->active++;
12080 }
12081 pll->refcount = pll->active;
12082
12083 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
12084 pll->name, pll->refcount, pll->on);
12085 }
12086
12087 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12088 base.head) {
12089 pipe = 0;
12090
12091 if (encoder->get_hw_state(encoder, &pipe)) {
12092 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12093 encoder->base.crtc = &crtc->base;
12094 encoder->get_config(encoder, &crtc->config);
12095 } else {
12096 encoder->base.crtc = NULL;
12097 }
12098
12099 encoder->connectors_active = false;
12100 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
12101 encoder->base.base.id,
12102 encoder->base.name,
12103 encoder->base.crtc ? "enabled" : "disabled",
12104 pipe_name(pipe));
12105 }
12106
12107 list_for_each_entry(connector, &dev->mode_config.connector_list,
12108 base.head) {
12109 if (connector->get_hw_state(connector)) {
12110 connector->base.dpms = DRM_MODE_DPMS_ON;
12111 connector->encoder->connectors_active = true;
12112 connector->base.encoder = &connector->encoder->base;
12113 } else {
12114 connector->base.dpms = DRM_MODE_DPMS_OFF;
12115 connector->base.encoder = NULL;
12116 }
12117 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
12118 connector->base.base.id,
12119 connector->base.name,
12120 connector->base.encoder ? "enabled" : "disabled");
12121 }
12122 }
12123
12124 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
12125 * and i915 state tracking structures. */
12126 void intel_modeset_setup_hw_state(struct drm_device *dev,
12127 bool force_restore)
12128 {
12129 struct drm_i915_private *dev_priv = dev->dev_private;
12130 enum pipe pipe;
12131 struct intel_crtc *crtc;
12132 struct intel_encoder *encoder;
12133 int i;
12134
12135 intel_modeset_readout_hw_state(dev);
12136
12137 /*
12138 * Now that we have the config, copy it to each CRTC struct
12139 * Note that this could go away if we move to using crtc_config
12140 * checking everywhere.
12141 */
12142 for_each_intel_crtc(dev, crtc) {
12143 if (crtc->active && i915.fastboot) {
12144 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
12145 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
12146 crtc->base.base.id);
12147 drm_mode_debug_printmodeline(&crtc->base.mode);
12148 }
12149 }
12150
12151 /* HW state is read out, now we need to sanitize this mess. */
12152 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12153 base.head) {
12154 intel_sanitize_encoder(encoder);
12155 }
12156
12157 for_each_pipe(pipe) {
12158 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12159 intel_sanitize_crtc(crtc);
12160 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
12161 }
12162
12163 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12164 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12165
12166 if (!pll->on || pll->active)
12167 continue;
12168
12169 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
12170
12171 pll->disable(dev_priv, pll);
12172 pll->on = false;
12173 }
12174
12175 if (HAS_PCH_SPLIT(dev))
12176 ilk_wm_get_hw_state(dev);
12177
12178 if (force_restore) {
12179 i915_redisable_vga(dev);
12180
12181 /*
12182 * We need to use raw interfaces for restoring state to avoid
12183 * checking (bogus) intermediate states.
12184 */
12185 for_each_pipe(pipe) {
12186 struct drm_crtc *crtc =
12187 dev_priv->pipe_to_crtc_mapping[pipe];
12188
12189 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
12190 crtc->primary->fb);
12191 }
12192 } else {
12193 intel_modeset_update_staged_output_state(dev);
12194 }
12195
12196 intel_modeset_check_state(dev);
12197 }
12198
12199 void intel_modeset_gem_init(struct drm_device *dev)
12200 {
12201 struct drm_crtc *c;
12202 struct intel_framebuffer *fb;
12203
12204 mutex_lock(&dev->struct_mutex);
12205 intel_init_gt_powersave(dev);
12206 mutex_unlock(&dev->struct_mutex);
12207
12208 intel_modeset_init_hw(dev);
12209
12210 intel_setup_overlay(dev);
12211
12212 /*
12213 * Make sure any fbs we allocated at startup are properly
12214 * pinned & fenced. When we do the allocation it's too early
12215 * for this.
12216 */
12217 mutex_lock(&dev->struct_mutex);
12218 for_each_crtc(dev, c) {
12219 if (!c->primary->fb)
12220 continue;
12221
12222 fb = to_intel_framebuffer(c->primary->fb);
12223 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
12224 DRM_ERROR("failed to pin boot fb on pipe %d\n",
12225 to_intel_crtc(c)->pipe);
12226 drm_framebuffer_unreference(c->primary->fb);
12227 c->primary->fb = NULL;
12228 }
12229 }
12230 mutex_unlock(&dev->struct_mutex);
12231 }
12232
12233 void intel_connector_unregister(struct intel_connector *intel_connector)
12234 {
12235 struct drm_connector *connector = &intel_connector->base;
12236
12237 intel_panel_destroy_backlight(connector);
12238 drm_sysfs_connector_remove(connector);
12239 }
12240
12241 void intel_modeset_cleanup(struct drm_device *dev)
12242 {
12243 struct drm_i915_private *dev_priv = dev->dev_private;
12244 struct drm_crtc *crtc;
12245 struct drm_connector *connector;
12246
12247 /*
12248 * Interrupts and polling as the first thing to avoid creating havoc.
12249 * Too much stuff here (turning of rps, connectors, ...) would
12250 * experience fancy races otherwise.
12251 */
12252 drm_irq_uninstall(dev);
12253 cancel_work_sync(&dev_priv->hotplug_work);
12254 /*
12255 * Due to the hpd irq storm handling the hotplug work can re-arm the
12256 * poll handlers. Hence disable polling after hpd handling is shut down.
12257 */
12258 drm_kms_helper_poll_fini(dev);
12259
12260 mutex_lock(&dev->struct_mutex);
12261
12262 intel_unregister_dsm_handler();
12263
12264 for_each_crtc(dev, crtc) {
12265 /* Skip inactive CRTCs */
12266 if (!crtc->primary->fb)
12267 continue;
12268
12269 intel_increase_pllclock(crtc);
12270 }
12271
12272 intel_disable_fbc(dev);
12273
12274 intel_disable_gt_powersave(dev);
12275
12276 ironlake_teardown_rc6(dev);
12277
12278 mutex_unlock(&dev->struct_mutex);
12279
12280 /* flush any delayed tasks or pending work */
12281 flush_scheduled_work();
12282
12283 /* destroy the backlight and sysfs files before encoders/connectors */
12284 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12285 struct intel_connector *intel_connector;
12286
12287 intel_connector = to_intel_connector(connector);
12288 intel_connector->unregister(intel_connector);
12289 }
12290
12291 drm_mode_config_cleanup(dev);
12292
12293 intel_cleanup_overlay(dev);
12294
12295 mutex_lock(&dev->struct_mutex);
12296 intel_cleanup_gt_powersave(dev);
12297 mutex_unlock(&dev->struct_mutex);
12298 }
12299
12300 /*
12301 * Return which encoder is currently attached for connector.
12302 */
12303 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
12304 {
12305 return &intel_attached_encoder(connector)->base;
12306 }
12307
12308 void intel_connector_attach_encoder(struct intel_connector *connector,
12309 struct intel_encoder *encoder)
12310 {
12311 connector->encoder = encoder;
12312 drm_mode_connector_attach_encoder(&connector->base,
12313 &encoder->base);
12314 }
12315
12316 /*
12317 * set vga decode state - true == enable VGA decode
12318 */
12319 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
12320 {
12321 struct drm_i915_private *dev_priv = dev->dev_private;
12322 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
12323 u16 gmch_ctrl;
12324
12325 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
12326 DRM_ERROR("failed to read control word\n");
12327 return -EIO;
12328 }
12329
12330 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
12331 return 0;
12332
12333 if (state)
12334 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
12335 else
12336 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
12337
12338 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
12339 DRM_ERROR("failed to write control word\n");
12340 return -EIO;
12341 }
12342
12343 return 0;
12344 }
12345
12346 struct intel_display_error_state {
12347
12348 u32 power_well_driver;
12349
12350 int num_transcoders;
12351
12352 struct intel_cursor_error_state {
12353 u32 control;
12354 u32 position;
12355 u32 base;
12356 u32 size;
12357 } cursor[I915_MAX_PIPES];
12358
12359 struct intel_pipe_error_state {
12360 bool power_domain_on;
12361 u32 source;
12362 u32 stat;
12363 } pipe[I915_MAX_PIPES];
12364
12365 struct intel_plane_error_state {
12366 u32 control;
12367 u32 stride;
12368 u32 size;
12369 u32 pos;
12370 u32 addr;
12371 u32 surface;
12372 u32 tile_offset;
12373 } plane[I915_MAX_PIPES];
12374
12375 struct intel_transcoder_error_state {
12376 bool power_domain_on;
12377 enum transcoder cpu_transcoder;
12378
12379 u32 conf;
12380
12381 u32 htotal;
12382 u32 hblank;
12383 u32 hsync;
12384 u32 vtotal;
12385 u32 vblank;
12386 u32 vsync;
12387 } transcoder[4];
12388 };
12389
12390 struct intel_display_error_state *
12391 intel_display_capture_error_state(struct drm_device *dev)
12392 {
12393 struct drm_i915_private *dev_priv = dev->dev_private;
12394 struct intel_display_error_state *error;
12395 int transcoders[] = {
12396 TRANSCODER_A,
12397 TRANSCODER_B,
12398 TRANSCODER_C,
12399 TRANSCODER_EDP,
12400 };
12401 int i;
12402
12403 if (INTEL_INFO(dev)->num_pipes == 0)
12404 return NULL;
12405
12406 error = kzalloc(sizeof(*error), GFP_ATOMIC);
12407 if (error == NULL)
12408 return NULL;
12409
12410 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12411 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
12412
12413 for_each_pipe(i) {
12414 error->pipe[i].power_domain_on =
12415 intel_display_power_enabled_unlocked(dev_priv,
12416 POWER_DOMAIN_PIPE(i));
12417 if (!error->pipe[i].power_domain_on)
12418 continue;
12419
12420 error->cursor[i].control = I915_READ(CURCNTR(i));
12421 error->cursor[i].position = I915_READ(CURPOS(i));
12422 error->cursor[i].base = I915_READ(CURBASE(i));
12423
12424 error->plane[i].control = I915_READ(DSPCNTR(i));
12425 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
12426 if (INTEL_INFO(dev)->gen <= 3) {
12427 error->plane[i].size = I915_READ(DSPSIZE(i));
12428 error->plane[i].pos = I915_READ(DSPPOS(i));
12429 }
12430 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12431 error->plane[i].addr = I915_READ(DSPADDR(i));
12432 if (INTEL_INFO(dev)->gen >= 4) {
12433 error->plane[i].surface = I915_READ(DSPSURF(i));
12434 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
12435 }
12436
12437 error->pipe[i].source = I915_READ(PIPESRC(i));
12438
12439 if (!HAS_PCH_SPLIT(dev))
12440 error->pipe[i].stat = I915_READ(PIPESTAT(i));
12441 }
12442
12443 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
12444 if (HAS_DDI(dev_priv->dev))
12445 error->num_transcoders++; /* Account for eDP. */
12446
12447 for (i = 0; i < error->num_transcoders; i++) {
12448 enum transcoder cpu_transcoder = transcoders[i];
12449
12450 error->transcoder[i].power_domain_on =
12451 intel_display_power_enabled_unlocked(dev_priv,
12452 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12453 if (!error->transcoder[i].power_domain_on)
12454 continue;
12455
12456 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12457
12458 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12459 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12460 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12461 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12462 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12463 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12464 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12465 }
12466
12467 return error;
12468 }
12469
12470 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12471
12472 void
12473 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12474 struct drm_device *dev,
12475 struct intel_display_error_state *error)
12476 {
12477 int i;
12478
12479 if (!error)
12480 return;
12481
12482 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
12483 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12484 err_printf(m, "PWR_WELL_CTL2: %08x\n",
12485 error->power_well_driver);
12486 for_each_pipe(i) {
12487 err_printf(m, "Pipe [%d]:\n", i);
12488 err_printf(m, " Power: %s\n",
12489 error->pipe[i].power_domain_on ? "on" : "off");
12490 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
12491 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
12492
12493 err_printf(m, "Plane [%d]:\n", i);
12494 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
12495 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
12496 if (INTEL_INFO(dev)->gen <= 3) {
12497 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
12498 err_printf(m, " POS: %08x\n", error->plane[i].pos);
12499 }
12500 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12501 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
12502 if (INTEL_INFO(dev)->gen >= 4) {
12503 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
12504 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
12505 }
12506
12507 err_printf(m, "Cursor [%d]:\n", i);
12508 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
12509 err_printf(m, " POS: %08x\n", error->cursor[i].position);
12510 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
12511 }
12512
12513 for (i = 0; i < error->num_transcoders; i++) {
12514 err_printf(m, "CPU transcoder: %c\n",
12515 transcoder_name(error->transcoder[i].cpu_transcoder));
12516 err_printf(m, " Power: %s\n",
12517 error->transcoder[i].power_domain_on ? "on" : "off");
12518 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
12519 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
12520 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
12521 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
12522 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
12523 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
12524 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
12525 }
12526 }
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