2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
33 #include "intel_drv.h"
36 #include "drm_dp_helper.h"
38 #include "drm_crtc_helper.h"
40 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
42 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
);
43 static void intel_update_watermarks(struct drm_device
*dev
);
44 static void intel_increase_pllclock(struct drm_crtc
*crtc
, bool schedule
);
67 #define INTEL_P2_NUM 2
68 typedef struct intel_limit intel_limit_t
;
70 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
72 bool (* find_pll
)(const intel_limit_t
*, struct drm_crtc
*,
73 int, int, intel_clock_t
*);
76 #define I8XX_DOT_MIN 25000
77 #define I8XX_DOT_MAX 350000
78 #define I8XX_VCO_MIN 930000
79 #define I8XX_VCO_MAX 1400000
83 #define I8XX_M_MAX 140
84 #define I8XX_M1_MIN 18
85 #define I8XX_M1_MAX 26
87 #define I8XX_M2_MAX 16
89 #define I8XX_P_MAX 128
91 #define I8XX_P1_MAX 33
92 #define I8XX_P1_LVDS_MIN 1
93 #define I8XX_P1_LVDS_MAX 6
94 #define I8XX_P2_SLOW 4
95 #define I8XX_P2_FAST 2
96 #define I8XX_P2_LVDS_SLOW 14
97 #define I8XX_P2_LVDS_FAST 7
98 #define I8XX_P2_SLOW_LIMIT 165000
100 #define I9XX_DOT_MIN 20000
101 #define I9XX_DOT_MAX 400000
102 #define I9XX_VCO_MIN 1400000
103 #define I9XX_VCO_MAX 2800000
104 #define PINEVIEW_VCO_MIN 1700000
105 #define PINEVIEW_VCO_MAX 3500000
108 /* Pineview's Ncounter is a ring counter */
109 #define PINEVIEW_N_MIN 3
110 #define PINEVIEW_N_MAX 6
111 #define I9XX_M_MIN 70
112 #define I9XX_M_MAX 120
113 #define PINEVIEW_M_MIN 2
114 #define PINEVIEW_M_MAX 256
115 #define I9XX_M1_MIN 10
116 #define I9XX_M1_MAX 22
117 #define I9XX_M2_MIN 5
118 #define I9XX_M2_MAX 9
119 /* Pineview M1 is reserved, and must be 0 */
120 #define PINEVIEW_M1_MIN 0
121 #define PINEVIEW_M1_MAX 0
122 #define PINEVIEW_M2_MIN 0
123 #define PINEVIEW_M2_MAX 254
124 #define I9XX_P_SDVO_DAC_MIN 5
125 #define I9XX_P_SDVO_DAC_MAX 80
126 #define I9XX_P_LVDS_MIN 7
127 #define I9XX_P_LVDS_MAX 98
128 #define PINEVIEW_P_LVDS_MIN 7
129 #define PINEVIEW_P_LVDS_MAX 112
130 #define I9XX_P1_MIN 1
131 #define I9XX_P1_MAX 8
132 #define I9XX_P2_SDVO_DAC_SLOW 10
133 #define I9XX_P2_SDVO_DAC_FAST 5
134 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
135 #define I9XX_P2_LVDS_SLOW 14
136 #define I9XX_P2_LVDS_FAST 7
137 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
139 /*The parameter is for SDVO on G4x platform*/
140 #define G4X_DOT_SDVO_MIN 25000
141 #define G4X_DOT_SDVO_MAX 270000
142 #define G4X_VCO_MIN 1750000
143 #define G4X_VCO_MAX 3500000
144 #define G4X_N_SDVO_MIN 1
145 #define G4X_N_SDVO_MAX 4
146 #define G4X_M_SDVO_MIN 104
147 #define G4X_M_SDVO_MAX 138
148 #define G4X_M1_SDVO_MIN 17
149 #define G4X_M1_SDVO_MAX 23
150 #define G4X_M2_SDVO_MIN 5
151 #define G4X_M2_SDVO_MAX 11
152 #define G4X_P_SDVO_MIN 10
153 #define G4X_P_SDVO_MAX 30
154 #define G4X_P1_SDVO_MIN 1
155 #define G4X_P1_SDVO_MAX 3
156 #define G4X_P2_SDVO_SLOW 10
157 #define G4X_P2_SDVO_FAST 10
158 #define G4X_P2_SDVO_LIMIT 270000
160 /*The parameter is for HDMI_DAC on G4x platform*/
161 #define G4X_DOT_HDMI_DAC_MIN 22000
162 #define G4X_DOT_HDMI_DAC_MAX 400000
163 #define G4X_N_HDMI_DAC_MIN 1
164 #define G4X_N_HDMI_DAC_MAX 4
165 #define G4X_M_HDMI_DAC_MIN 104
166 #define G4X_M_HDMI_DAC_MAX 138
167 #define G4X_M1_HDMI_DAC_MIN 16
168 #define G4X_M1_HDMI_DAC_MAX 23
169 #define G4X_M2_HDMI_DAC_MIN 5
170 #define G4X_M2_HDMI_DAC_MAX 11
171 #define G4X_P_HDMI_DAC_MIN 5
172 #define G4X_P_HDMI_DAC_MAX 80
173 #define G4X_P1_HDMI_DAC_MIN 1
174 #define G4X_P1_HDMI_DAC_MAX 8
175 #define G4X_P2_HDMI_DAC_SLOW 10
176 #define G4X_P2_HDMI_DAC_FAST 5
177 #define G4X_P2_HDMI_DAC_LIMIT 165000
179 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
182 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
183 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
184 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
185 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
190 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
191 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
194 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
195 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
196 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
198 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
201 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
202 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
203 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
204 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
205 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
206 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
207 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
208 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
209 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
210 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
211 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
212 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
213 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
214 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
215 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
217 /*The parameter is for DISPLAY PORT on G4x platform*/
218 #define G4X_DOT_DISPLAY_PORT_MIN 161670
219 #define G4X_DOT_DISPLAY_PORT_MAX 227000
220 #define G4X_N_DISPLAY_PORT_MIN 1
221 #define G4X_N_DISPLAY_PORT_MAX 2
222 #define G4X_M_DISPLAY_PORT_MIN 97
223 #define G4X_M_DISPLAY_PORT_MAX 108
224 #define G4X_M1_DISPLAY_PORT_MIN 0x10
225 #define G4X_M1_DISPLAY_PORT_MAX 0x12
226 #define G4X_M2_DISPLAY_PORT_MIN 0x05
227 #define G4X_M2_DISPLAY_PORT_MAX 0x06
228 #define G4X_P_DISPLAY_PORT_MIN 10
229 #define G4X_P_DISPLAY_PORT_MAX 20
230 #define G4X_P1_DISPLAY_PORT_MIN 1
231 #define G4X_P1_DISPLAY_PORT_MAX 2
232 #define G4X_P2_DISPLAY_PORT_SLOW 10
233 #define G4X_P2_DISPLAY_PORT_FAST 10
234 #define G4X_P2_DISPLAY_PORT_LIMIT 0
236 /* Ironlake / Sandybridge */
237 /* as we calculate clock using (register_value + 2) for
238 N/M1/M2, so here the range value for them is (actual_value-2).
240 #define IRONLAKE_DOT_MIN 25000
241 #define IRONLAKE_DOT_MAX 350000
242 #define IRONLAKE_VCO_MIN 1760000
243 #define IRONLAKE_VCO_MAX 3510000
244 #define IRONLAKE_M1_MIN 12
245 #define IRONLAKE_M1_MAX 22
246 #define IRONLAKE_M2_MIN 5
247 #define IRONLAKE_M2_MAX 9
248 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
250 /* We have parameter ranges for different type of outputs. */
252 /* DAC & HDMI Refclk 120Mhz */
253 #define IRONLAKE_DAC_N_MIN 1
254 #define IRONLAKE_DAC_N_MAX 5
255 #define IRONLAKE_DAC_M_MIN 79
256 #define IRONLAKE_DAC_M_MAX 127
257 #define IRONLAKE_DAC_P_MIN 5
258 #define IRONLAKE_DAC_P_MAX 80
259 #define IRONLAKE_DAC_P1_MIN 1
260 #define IRONLAKE_DAC_P1_MAX 8
261 #define IRONLAKE_DAC_P2_SLOW 10
262 #define IRONLAKE_DAC_P2_FAST 5
264 /* LVDS single-channel 120Mhz refclk */
265 #define IRONLAKE_LVDS_S_N_MIN 1
266 #define IRONLAKE_LVDS_S_N_MAX 3
267 #define IRONLAKE_LVDS_S_M_MIN 79
268 #define IRONLAKE_LVDS_S_M_MAX 118
269 #define IRONLAKE_LVDS_S_P_MIN 28
270 #define IRONLAKE_LVDS_S_P_MAX 112
271 #define IRONLAKE_LVDS_S_P1_MIN 2
272 #define IRONLAKE_LVDS_S_P1_MAX 8
273 #define IRONLAKE_LVDS_S_P2_SLOW 14
274 #define IRONLAKE_LVDS_S_P2_FAST 14
276 /* LVDS dual-channel 120Mhz refclk */
277 #define IRONLAKE_LVDS_D_N_MIN 1
278 #define IRONLAKE_LVDS_D_N_MAX 3
279 #define IRONLAKE_LVDS_D_M_MIN 79
280 #define IRONLAKE_LVDS_D_M_MAX 127
281 #define IRONLAKE_LVDS_D_P_MIN 14
282 #define IRONLAKE_LVDS_D_P_MAX 56
283 #define IRONLAKE_LVDS_D_P1_MIN 2
284 #define IRONLAKE_LVDS_D_P1_MAX 8
285 #define IRONLAKE_LVDS_D_P2_SLOW 7
286 #define IRONLAKE_LVDS_D_P2_FAST 7
288 /* LVDS single-channel 100Mhz refclk */
289 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
290 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
291 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
292 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
293 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
294 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
295 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
296 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
297 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
298 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
300 /* LVDS dual-channel 100Mhz refclk */
301 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
302 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
303 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
304 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
305 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
306 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
307 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
308 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
309 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
310 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
313 #define IRONLAKE_DP_N_MIN 1
314 #define IRONLAKE_DP_N_MAX 2
315 #define IRONLAKE_DP_M_MIN 81
316 #define IRONLAKE_DP_M_MAX 90
317 #define IRONLAKE_DP_P_MIN 10
318 #define IRONLAKE_DP_P_MAX 20
319 #define IRONLAKE_DP_P2_FAST 10
320 #define IRONLAKE_DP_P2_SLOW 10
321 #define IRONLAKE_DP_P2_LIMIT 0
322 #define IRONLAKE_DP_P1_MIN 1
323 #define IRONLAKE_DP_P1_MAX 2
326 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
327 int target
, int refclk
, intel_clock_t
*best_clock
);
329 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
330 int target
, int refclk
, intel_clock_t
*best_clock
);
333 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
334 int target
, int refclk
, intel_clock_t
*best_clock
);
336 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
337 int target
, int refclk
, intel_clock_t
*best_clock
);
339 static const intel_limit_t intel_limits_i8xx_dvo
= {
340 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
341 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
342 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
343 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
344 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
345 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
346 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
347 .p1
= { .min
= I8XX_P1_MIN
, .max
= I8XX_P1_MAX
},
348 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
349 .p2_slow
= I8XX_P2_SLOW
, .p2_fast
= I8XX_P2_FAST
},
350 .find_pll
= intel_find_best_PLL
,
353 static const intel_limit_t intel_limits_i8xx_lvds
= {
354 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
355 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
356 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
357 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
358 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
359 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
360 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
361 .p1
= { .min
= I8XX_P1_LVDS_MIN
, .max
= I8XX_P1_LVDS_MAX
},
362 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
363 .p2_slow
= I8XX_P2_LVDS_SLOW
, .p2_fast
= I8XX_P2_LVDS_FAST
},
364 .find_pll
= intel_find_best_PLL
,
367 static const intel_limit_t intel_limits_i9xx_sdvo
= {
368 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
369 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
370 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
371 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
372 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
373 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
374 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
375 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
376 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
377 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
378 .find_pll
= intel_find_best_PLL
,
381 static const intel_limit_t intel_limits_i9xx_lvds
= {
382 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
383 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
384 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
385 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
386 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
387 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
388 .p
= { .min
= I9XX_P_LVDS_MIN
, .max
= I9XX_P_LVDS_MAX
},
389 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
390 /* The single-channel range is 25-112Mhz, and dual-channel
391 * is 80-224Mhz. Prefer single channel as much as possible.
393 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
394 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_FAST
},
395 .find_pll
= intel_find_best_PLL
,
398 /* below parameter and function is for G4X Chipset Family*/
399 static const intel_limit_t intel_limits_g4x_sdvo
= {
400 .dot
= { .min
= G4X_DOT_SDVO_MIN
, .max
= G4X_DOT_SDVO_MAX
},
401 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
402 .n
= { .min
= G4X_N_SDVO_MIN
, .max
= G4X_N_SDVO_MAX
},
403 .m
= { .min
= G4X_M_SDVO_MIN
, .max
= G4X_M_SDVO_MAX
},
404 .m1
= { .min
= G4X_M1_SDVO_MIN
, .max
= G4X_M1_SDVO_MAX
},
405 .m2
= { .min
= G4X_M2_SDVO_MIN
, .max
= G4X_M2_SDVO_MAX
},
406 .p
= { .min
= G4X_P_SDVO_MIN
, .max
= G4X_P_SDVO_MAX
},
407 .p1
= { .min
= G4X_P1_SDVO_MIN
, .max
= G4X_P1_SDVO_MAX
},
408 .p2
= { .dot_limit
= G4X_P2_SDVO_LIMIT
,
409 .p2_slow
= G4X_P2_SDVO_SLOW
,
410 .p2_fast
= G4X_P2_SDVO_FAST
412 .find_pll
= intel_g4x_find_best_PLL
,
415 static const intel_limit_t intel_limits_g4x_hdmi
= {
416 .dot
= { .min
= G4X_DOT_HDMI_DAC_MIN
, .max
= G4X_DOT_HDMI_DAC_MAX
},
417 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
418 .n
= { .min
= G4X_N_HDMI_DAC_MIN
, .max
= G4X_N_HDMI_DAC_MAX
},
419 .m
= { .min
= G4X_M_HDMI_DAC_MIN
, .max
= G4X_M_HDMI_DAC_MAX
},
420 .m1
= { .min
= G4X_M1_HDMI_DAC_MIN
, .max
= G4X_M1_HDMI_DAC_MAX
},
421 .m2
= { .min
= G4X_M2_HDMI_DAC_MIN
, .max
= G4X_M2_HDMI_DAC_MAX
},
422 .p
= { .min
= G4X_P_HDMI_DAC_MIN
, .max
= G4X_P_HDMI_DAC_MAX
},
423 .p1
= { .min
= G4X_P1_HDMI_DAC_MIN
, .max
= G4X_P1_HDMI_DAC_MAX
},
424 .p2
= { .dot_limit
= G4X_P2_HDMI_DAC_LIMIT
,
425 .p2_slow
= G4X_P2_HDMI_DAC_SLOW
,
426 .p2_fast
= G4X_P2_HDMI_DAC_FAST
428 .find_pll
= intel_g4x_find_best_PLL
,
431 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
432 .dot
= { .min
= G4X_DOT_SINGLE_CHANNEL_LVDS_MIN
,
433 .max
= G4X_DOT_SINGLE_CHANNEL_LVDS_MAX
},
434 .vco
= { .min
= G4X_VCO_MIN
,
435 .max
= G4X_VCO_MAX
},
436 .n
= { .min
= G4X_N_SINGLE_CHANNEL_LVDS_MIN
,
437 .max
= G4X_N_SINGLE_CHANNEL_LVDS_MAX
},
438 .m
= { .min
= G4X_M_SINGLE_CHANNEL_LVDS_MIN
,
439 .max
= G4X_M_SINGLE_CHANNEL_LVDS_MAX
},
440 .m1
= { .min
= G4X_M1_SINGLE_CHANNEL_LVDS_MIN
,
441 .max
= G4X_M1_SINGLE_CHANNEL_LVDS_MAX
},
442 .m2
= { .min
= G4X_M2_SINGLE_CHANNEL_LVDS_MIN
,
443 .max
= G4X_M2_SINGLE_CHANNEL_LVDS_MAX
},
444 .p
= { .min
= G4X_P_SINGLE_CHANNEL_LVDS_MIN
,
445 .max
= G4X_P_SINGLE_CHANNEL_LVDS_MAX
},
446 .p1
= { .min
= G4X_P1_SINGLE_CHANNEL_LVDS_MIN
,
447 .max
= G4X_P1_SINGLE_CHANNEL_LVDS_MAX
},
448 .p2
= { .dot_limit
= G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT
,
449 .p2_slow
= G4X_P2_SINGLE_CHANNEL_LVDS_SLOW
,
450 .p2_fast
= G4X_P2_SINGLE_CHANNEL_LVDS_FAST
452 .find_pll
= intel_g4x_find_best_PLL
,
455 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
456 .dot
= { .min
= G4X_DOT_DUAL_CHANNEL_LVDS_MIN
,
457 .max
= G4X_DOT_DUAL_CHANNEL_LVDS_MAX
},
458 .vco
= { .min
= G4X_VCO_MIN
,
459 .max
= G4X_VCO_MAX
},
460 .n
= { .min
= G4X_N_DUAL_CHANNEL_LVDS_MIN
,
461 .max
= G4X_N_DUAL_CHANNEL_LVDS_MAX
},
462 .m
= { .min
= G4X_M_DUAL_CHANNEL_LVDS_MIN
,
463 .max
= G4X_M_DUAL_CHANNEL_LVDS_MAX
},
464 .m1
= { .min
= G4X_M1_DUAL_CHANNEL_LVDS_MIN
,
465 .max
= G4X_M1_DUAL_CHANNEL_LVDS_MAX
},
466 .m2
= { .min
= G4X_M2_DUAL_CHANNEL_LVDS_MIN
,
467 .max
= G4X_M2_DUAL_CHANNEL_LVDS_MAX
},
468 .p
= { .min
= G4X_P_DUAL_CHANNEL_LVDS_MIN
,
469 .max
= G4X_P_DUAL_CHANNEL_LVDS_MAX
},
470 .p1
= { .min
= G4X_P1_DUAL_CHANNEL_LVDS_MIN
,
471 .max
= G4X_P1_DUAL_CHANNEL_LVDS_MAX
},
472 .p2
= { .dot_limit
= G4X_P2_DUAL_CHANNEL_LVDS_LIMIT
,
473 .p2_slow
= G4X_P2_DUAL_CHANNEL_LVDS_SLOW
,
474 .p2_fast
= G4X_P2_DUAL_CHANNEL_LVDS_FAST
476 .find_pll
= intel_g4x_find_best_PLL
,
479 static const intel_limit_t intel_limits_g4x_display_port
= {
480 .dot
= { .min
= G4X_DOT_DISPLAY_PORT_MIN
,
481 .max
= G4X_DOT_DISPLAY_PORT_MAX
},
482 .vco
= { .min
= G4X_VCO_MIN
,
484 .n
= { .min
= G4X_N_DISPLAY_PORT_MIN
,
485 .max
= G4X_N_DISPLAY_PORT_MAX
},
486 .m
= { .min
= G4X_M_DISPLAY_PORT_MIN
,
487 .max
= G4X_M_DISPLAY_PORT_MAX
},
488 .m1
= { .min
= G4X_M1_DISPLAY_PORT_MIN
,
489 .max
= G4X_M1_DISPLAY_PORT_MAX
},
490 .m2
= { .min
= G4X_M2_DISPLAY_PORT_MIN
,
491 .max
= G4X_M2_DISPLAY_PORT_MAX
},
492 .p
= { .min
= G4X_P_DISPLAY_PORT_MIN
,
493 .max
= G4X_P_DISPLAY_PORT_MAX
},
494 .p1
= { .min
= G4X_P1_DISPLAY_PORT_MIN
,
495 .max
= G4X_P1_DISPLAY_PORT_MAX
},
496 .p2
= { .dot_limit
= G4X_P2_DISPLAY_PORT_LIMIT
,
497 .p2_slow
= G4X_P2_DISPLAY_PORT_SLOW
,
498 .p2_fast
= G4X_P2_DISPLAY_PORT_FAST
},
499 .find_pll
= intel_find_pll_g4x_dp
,
502 static const intel_limit_t intel_limits_pineview_sdvo
= {
503 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
504 .vco
= { .min
= PINEVIEW_VCO_MIN
, .max
= PINEVIEW_VCO_MAX
},
505 .n
= { .min
= PINEVIEW_N_MIN
, .max
= PINEVIEW_N_MAX
},
506 .m
= { .min
= PINEVIEW_M_MIN
, .max
= PINEVIEW_M_MAX
},
507 .m1
= { .min
= PINEVIEW_M1_MIN
, .max
= PINEVIEW_M1_MAX
},
508 .m2
= { .min
= PINEVIEW_M2_MIN
, .max
= PINEVIEW_M2_MAX
},
509 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
510 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
511 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
512 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
513 .find_pll
= intel_find_best_PLL
,
516 static const intel_limit_t intel_limits_pineview_lvds
= {
517 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
518 .vco
= { .min
= PINEVIEW_VCO_MIN
, .max
= PINEVIEW_VCO_MAX
},
519 .n
= { .min
= PINEVIEW_N_MIN
, .max
= PINEVIEW_N_MAX
},
520 .m
= { .min
= PINEVIEW_M_MIN
, .max
= PINEVIEW_M_MAX
},
521 .m1
= { .min
= PINEVIEW_M1_MIN
, .max
= PINEVIEW_M1_MAX
},
522 .m2
= { .min
= PINEVIEW_M2_MIN
, .max
= PINEVIEW_M2_MAX
},
523 .p
= { .min
= PINEVIEW_P_LVDS_MIN
, .max
= PINEVIEW_P_LVDS_MAX
},
524 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
525 /* Pineview only supports single-channel mode. */
526 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
527 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_SLOW
},
528 .find_pll
= intel_find_best_PLL
,
531 static const intel_limit_t intel_limits_ironlake_dac
= {
532 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
533 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
534 .n
= { .min
= IRONLAKE_DAC_N_MIN
, .max
= IRONLAKE_DAC_N_MAX
},
535 .m
= { .min
= IRONLAKE_DAC_M_MIN
, .max
= IRONLAKE_DAC_M_MAX
},
536 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
537 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
538 .p
= { .min
= IRONLAKE_DAC_P_MIN
, .max
= IRONLAKE_DAC_P_MAX
},
539 .p1
= { .min
= IRONLAKE_DAC_P1_MIN
, .max
= IRONLAKE_DAC_P1_MAX
},
540 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
541 .p2_slow
= IRONLAKE_DAC_P2_SLOW
,
542 .p2_fast
= IRONLAKE_DAC_P2_FAST
},
543 .find_pll
= intel_g4x_find_best_PLL
,
546 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
547 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
548 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
549 .n
= { .min
= IRONLAKE_LVDS_S_N_MIN
, .max
= IRONLAKE_LVDS_S_N_MAX
},
550 .m
= { .min
= IRONLAKE_LVDS_S_M_MIN
, .max
= IRONLAKE_LVDS_S_M_MAX
},
551 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
552 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
553 .p
= { .min
= IRONLAKE_LVDS_S_P_MIN
, .max
= IRONLAKE_LVDS_S_P_MAX
},
554 .p1
= { .min
= IRONLAKE_LVDS_S_P1_MIN
, .max
= IRONLAKE_LVDS_S_P1_MAX
},
555 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
556 .p2_slow
= IRONLAKE_LVDS_S_P2_SLOW
,
557 .p2_fast
= IRONLAKE_LVDS_S_P2_FAST
},
558 .find_pll
= intel_g4x_find_best_PLL
,
561 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
562 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
563 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
564 .n
= { .min
= IRONLAKE_LVDS_D_N_MIN
, .max
= IRONLAKE_LVDS_D_N_MAX
},
565 .m
= { .min
= IRONLAKE_LVDS_D_M_MIN
, .max
= IRONLAKE_LVDS_D_M_MAX
},
566 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
567 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
568 .p
= { .min
= IRONLAKE_LVDS_D_P_MIN
, .max
= IRONLAKE_LVDS_D_P_MAX
},
569 .p1
= { .min
= IRONLAKE_LVDS_D_P1_MIN
, .max
= IRONLAKE_LVDS_D_P1_MAX
},
570 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
571 .p2_slow
= IRONLAKE_LVDS_D_P2_SLOW
,
572 .p2_fast
= IRONLAKE_LVDS_D_P2_FAST
},
573 .find_pll
= intel_g4x_find_best_PLL
,
576 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
577 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
578 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
579 .n
= { .min
= IRONLAKE_LVDS_S_SSC_N_MIN
, .max
= IRONLAKE_LVDS_S_SSC_N_MAX
},
580 .m
= { .min
= IRONLAKE_LVDS_S_SSC_M_MIN
, .max
= IRONLAKE_LVDS_S_SSC_M_MAX
},
581 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
582 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
583 .p
= { .min
= IRONLAKE_LVDS_S_SSC_P_MIN
, .max
= IRONLAKE_LVDS_S_SSC_P_MAX
},
584 .p1
= { .min
= IRONLAKE_LVDS_S_SSC_P1_MIN
,.max
= IRONLAKE_LVDS_S_SSC_P1_MAX
},
585 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
586 .p2_slow
= IRONLAKE_LVDS_S_SSC_P2_SLOW
,
587 .p2_fast
= IRONLAKE_LVDS_S_SSC_P2_FAST
},
588 .find_pll
= intel_g4x_find_best_PLL
,
591 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
592 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
593 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
594 .n
= { .min
= IRONLAKE_LVDS_D_SSC_N_MIN
, .max
= IRONLAKE_LVDS_D_SSC_N_MAX
},
595 .m
= { .min
= IRONLAKE_LVDS_D_SSC_M_MIN
, .max
= IRONLAKE_LVDS_D_SSC_M_MAX
},
596 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
597 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
598 .p
= { .min
= IRONLAKE_LVDS_D_SSC_P_MIN
, .max
= IRONLAKE_LVDS_D_SSC_P_MAX
},
599 .p1
= { .min
= IRONLAKE_LVDS_D_SSC_P1_MIN
,.max
= IRONLAKE_LVDS_D_SSC_P1_MAX
},
600 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
601 .p2_slow
= IRONLAKE_LVDS_D_SSC_P2_SLOW
,
602 .p2_fast
= IRONLAKE_LVDS_D_SSC_P2_FAST
},
603 .find_pll
= intel_g4x_find_best_PLL
,
606 static const intel_limit_t intel_limits_ironlake_display_port
= {
607 .dot
= { .min
= IRONLAKE_DOT_MIN
,
608 .max
= IRONLAKE_DOT_MAX
},
609 .vco
= { .min
= IRONLAKE_VCO_MIN
,
610 .max
= IRONLAKE_VCO_MAX
},
611 .n
= { .min
= IRONLAKE_DP_N_MIN
,
612 .max
= IRONLAKE_DP_N_MAX
},
613 .m
= { .min
= IRONLAKE_DP_M_MIN
,
614 .max
= IRONLAKE_DP_M_MAX
},
615 .m1
= { .min
= IRONLAKE_M1_MIN
,
616 .max
= IRONLAKE_M1_MAX
},
617 .m2
= { .min
= IRONLAKE_M2_MIN
,
618 .max
= IRONLAKE_M2_MAX
},
619 .p
= { .min
= IRONLAKE_DP_P_MIN
,
620 .max
= IRONLAKE_DP_P_MAX
},
621 .p1
= { .min
= IRONLAKE_DP_P1_MIN
,
622 .max
= IRONLAKE_DP_P1_MAX
},
623 .p2
= { .dot_limit
= IRONLAKE_DP_P2_LIMIT
,
624 .p2_slow
= IRONLAKE_DP_P2_SLOW
,
625 .p2_fast
= IRONLAKE_DP_P2_FAST
},
626 .find_pll
= intel_find_pll_ironlake_dp
,
629 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
)
631 struct drm_device
*dev
= crtc
->dev
;
632 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
633 const intel_limit_t
*limit
;
636 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
637 if (dev_priv
->lvds_use_ssc
&& dev_priv
->lvds_ssc_freq
== 100)
640 if ((I915_READ(PCH_LVDS
) & LVDS_CLKB_POWER_MASK
) ==
641 LVDS_CLKB_POWER_UP
) {
642 /* LVDS dual channel */
644 limit
= &intel_limits_ironlake_dual_lvds_100m
;
646 limit
= &intel_limits_ironlake_dual_lvds
;
649 limit
= &intel_limits_ironlake_single_lvds_100m
;
651 limit
= &intel_limits_ironlake_single_lvds
;
653 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
655 limit
= &intel_limits_ironlake_display_port
;
657 limit
= &intel_limits_ironlake_dac
;
662 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
664 struct drm_device
*dev
= crtc
->dev
;
665 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
666 const intel_limit_t
*limit
;
668 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
669 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
671 /* LVDS with dual channel */
672 limit
= &intel_limits_g4x_dual_channel_lvds
;
674 /* LVDS with dual channel */
675 limit
= &intel_limits_g4x_single_channel_lvds
;
676 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
677 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
678 limit
= &intel_limits_g4x_hdmi
;
679 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
680 limit
= &intel_limits_g4x_sdvo
;
681 } else if (intel_pipe_has_type (crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
682 limit
= &intel_limits_g4x_display_port
;
683 } else /* The option is for other outputs */
684 limit
= &intel_limits_i9xx_sdvo
;
689 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
)
691 struct drm_device
*dev
= crtc
->dev
;
692 const intel_limit_t
*limit
;
694 if (HAS_PCH_SPLIT(dev
))
695 limit
= intel_ironlake_limit(crtc
);
696 else if (IS_G4X(dev
)) {
697 limit
= intel_g4x_limit(crtc
);
698 } else if (IS_I9XX(dev
) && !IS_PINEVIEW(dev
)) {
699 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
700 limit
= &intel_limits_i9xx_lvds
;
702 limit
= &intel_limits_i9xx_sdvo
;
703 } else if (IS_PINEVIEW(dev
)) {
704 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
705 limit
= &intel_limits_pineview_lvds
;
707 limit
= &intel_limits_pineview_sdvo
;
709 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
710 limit
= &intel_limits_i8xx_lvds
;
712 limit
= &intel_limits_i8xx_dvo
;
717 /* m1 is reserved as 0 in Pineview, n is a ring counter */
718 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
720 clock
->m
= clock
->m2
+ 2;
721 clock
->p
= clock
->p1
* clock
->p2
;
722 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
723 clock
->dot
= clock
->vco
/ clock
->p
;
726 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
728 if (IS_PINEVIEW(dev
)) {
729 pineview_clock(refclk
, clock
);
732 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
733 clock
->p
= clock
->p1
* clock
->p2
;
734 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
735 clock
->dot
= clock
->vco
/ clock
->p
;
739 * Returns whether any output on the specified pipe is of the specified type
741 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
)
743 struct drm_device
*dev
= crtc
->dev
;
744 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
745 struct drm_encoder
*l_entry
;
747 list_for_each_entry(l_entry
, &mode_config
->encoder_list
, head
) {
748 if (l_entry
&& l_entry
->crtc
== crtc
) {
749 struct intel_encoder
*intel_encoder
= enc_to_intel_encoder(l_entry
);
750 if (intel_encoder
->type
== type
)
757 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
759 * Returns whether the given set of divisors are valid for a given refclk with
760 * the given connectors.
763 static bool intel_PLL_is_valid(struct drm_crtc
*crtc
, intel_clock_t
*clock
)
765 const intel_limit_t
*limit
= intel_limit (crtc
);
766 struct drm_device
*dev
= crtc
->dev
;
768 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
769 INTELPllInvalid ("p1 out of range\n");
770 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
771 INTELPllInvalid ("p out of range\n");
772 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
773 INTELPllInvalid ("m2 out of range\n");
774 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
775 INTELPllInvalid ("m1 out of range\n");
776 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
777 INTELPllInvalid ("m1 <= m2\n");
778 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
779 INTELPllInvalid ("m out of range\n");
780 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
781 INTELPllInvalid ("n out of range\n");
782 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
783 INTELPllInvalid ("vco out of range\n");
784 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
785 * connector, etc., rather than just a single range.
787 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
788 INTELPllInvalid ("dot out of range\n");
794 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
795 int target
, int refclk
, intel_clock_t
*best_clock
)
798 struct drm_device
*dev
= crtc
->dev
;
799 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
803 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
804 (I915_READ(LVDS
)) != 0) {
806 * For LVDS, if the panel is on, just rely on its current
807 * settings for dual-channel. We haven't figured out how to
808 * reliably set up different single/dual channel state, if we
811 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
813 clock
.p2
= limit
->p2
.p2_fast
;
815 clock
.p2
= limit
->p2
.p2_slow
;
817 if (target
< limit
->p2
.dot_limit
)
818 clock
.p2
= limit
->p2
.p2_slow
;
820 clock
.p2
= limit
->p2
.p2_fast
;
823 memset (best_clock
, 0, sizeof (*best_clock
));
825 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
827 for (clock
.m2
= limit
->m2
.min
;
828 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
829 /* m1 is always 0 in Pineview */
830 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
832 for (clock
.n
= limit
->n
.min
;
833 clock
.n
<= limit
->n
.max
; clock
.n
++) {
834 for (clock
.p1
= limit
->p1
.min
;
835 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
838 intel_clock(dev
, refclk
, &clock
);
840 if (!intel_PLL_is_valid(crtc
, &clock
))
843 this_err
= abs(clock
.dot
- target
);
844 if (this_err
< err
) {
853 return (err
!= target
);
857 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
858 int target
, int refclk
, intel_clock_t
*best_clock
)
860 struct drm_device
*dev
= crtc
->dev
;
861 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
865 /* approximately equals target * 0.00488 */
866 int err_most
= (target
>> 8) + (target
>> 10);
869 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
872 if (HAS_PCH_SPLIT(dev
))
876 if ((I915_READ(lvds_reg
) & LVDS_CLKB_POWER_MASK
) ==
878 clock
.p2
= limit
->p2
.p2_fast
;
880 clock
.p2
= limit
->p2
.p2_slow
;
882 if (target
< limit
->p2
.dot_limit
)
883 clock
.p2
= limit
->p2
.p2_slow
;
885 clock
.p2
= limit
->p2
.p2_fast
;
888 memset(best_clock
, 0, sizeof(*best_clock
));
889 max_n
= limit
->n
.max
;
890 /* based on hardware requirement, prefer smaller n to precision */
891 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
892 /* based on hardware requirement, prefere larger m1,m2 */
893 for (clock
.m1
= limit
->m1
.max
;
894 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
895 for (clock
.m2
= limit
->m2
.max
;
896 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
897 for (clock
.p1
= limit
->p1
.max
;
898 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
901 intel_clock(dev
, refclk
, &clock
);
902 if (!intel_PLL_is_valid(crtc
, &clock
))
904 this_err
= abs(clock
.dot
- target
) ;
905 if (this_err
< err_most
) {
919 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
920 int target
, int refclk
, intel_clock_t
*best_clock
)
922 struct drm_device
*dev
= crtc
->dev
;
925 /* return directly when it is eDP */
929 if (target
< 200000) {
942 intel_clock(dev
, refclk
, &clock
);
943 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
947 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
949 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
950 int target
, int refclk
, intel_clock_t
*best_clock
)
953 if (target
< 200000) {
966 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
967 clock
.p
= (clock
.p1
* clock
.p2
);
968 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
970 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
975 intel_wait_for_vblank(struct drm_device
*dev
)
977 /* Wait for 20ms, i.e. one cycle at 50hz. */
981 /* Parameters have changed, update FBC info */
982 static void i8xx_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
984 struct drm_device
*dev
= crtc
->dev
;
985 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
986 struct drm_framebuffer
*fb
= crtc
->fb
;
987 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
988 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(intel_fb
->obj
);
989 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
991 u32 fbc_ctl
, fbc_ctl2
;
993 dev_priv
->cfb_pitch
= dev_priv
->cfb_size
/ FBC_LL_SIZE
;
995 if (fb
->pitch
< dev_priv
->cfb_pitch
)
996 dev_priv
->cfb_pitch
= fb
->pitch
;
998 /* FBC_CTL wants 64B units */
999 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1000 dev_priv
->cfb_fence
= obj_priv
->fence_reg
;
1001 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1002 plane
= dev_priv
->cfb_plane
== 0 ? FBC_CTL_PLANEA
: FBC_CTL_PLANEB
;
1004 /* Clear old tags */
1005 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
1006 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
1009 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| plane
;
1010 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1011 fbc_ctl2
|= FBC_CTL_CPU_FENCE
;
1012 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
1013 I915_WRITE(FBC_FENCE_OFF
, crtc
->y
);
1016 fbc_ctl
= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
1018 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
1019 fbc_ctl
|= (dev_priv
->cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
1020 fbc_ctl
|= (interval
& 0x2fff) << FBC_CTL_INTERVAL_SHIFT
;
1021 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1022 fbc_ctl
|= dev_priv
->cfb_fence
;
1023 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
1025 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1026 dev_priv
->cfb_pitch
, crtc
->y
, dev_priv
->cfb_plane
);
1029 void i8xx_disable_fbc(struct drm_device
*dev
)
1031 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1032 unsigned long timeout
= jiffies
+ msecs_to_jiffies(1);
1035 if (!I915_HAS_FBC(dev
))
1038 if (!(I915_READ(FBC_CONTROL
) & FBC_CTL_EN
))
1039 return; /* Already off, just return */
1041 /* Disable compression */
1042 fbc_ctl
= I915_READ(FBC_CONTROL
);
1043 fbc_ctl
&= ~FBC_CTL_EN
;
1044 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
1046 /* Wait for compressing bit to clear */
1047 while (I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
) {
1048 if (time_after(jiffies
, timeout
)) {
1049 DRM_DEBUG_DRIVER("FBC idle timed out\n");
1055 intel_wait_for_vblank(dev
);
1057 DRM_DEBUG_KMS("disabled FBC\n");
1060 static bool i8xx_fbc_enabled(struct drm_device
*dev
)
1062 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1064 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
1067 static void g4x_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1069 struct drm_device
*dev
= crtc
->dev
;
1070 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1071 struct drm_framebuffer
*fb
= crtc
->fb
;
1072 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1073 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(intel_fb
->obj
);
1074 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1075 int plane
= (intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
:
1077 unsigned long stall_watermark
= 200;
1080 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1081 dev_priv
->cfb_fence
= obj_priv
->fence_reg
;
1082 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1084 dpfc_ctl
= plane
| DPFC_SR_EN
| DPFC_CTL_LIMIT_1X
;
1085 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1086 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| dev_priv
->cfb_fence
;
1087 I915_WRITE(DPFC_CHICKEN
, DPFC_HT_MODIFY
);
1089 I915_WRITE(DPFC_CHICKEN
, ~DPFC_HT_MODIFY
);
1092 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
1093 I915_WRITE(DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
1094 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
1095 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
1096 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->y
);
1099 I915_WRITE(DPFC_CONTROL
, I915_READ(DPFC_CONTROL
) | DPFC_CTL_EN
);
1101 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
1104 void g4x_disable_fbc(struct drm_device
*dev
)
1106 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1109 /* Disable compression */
1110 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
1111 dpfc_ctl
&= ~DPFC_CTL_EN
;
1112 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
1113 intel_wait_for_vblank(dev
);
1115 DRM_DEBUG_KMS("disabled FBC\n");
1118 static bool g4x_fbc_enabled(struct drm_device
*dev
)
1120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1122 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
1125 bool intel_fbc_enabled(struct drm_device
*dev
)
1127 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1129 if (!dev_priv
->display
.fbc_enabled
)
1132 return dev_priv
->display
.fbc_enabled(dev
);
1135 void intel_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1137 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1139 if (!dev_priv
->display
.enable_fbc
)
1142 dev_priv
->display
.enable_fbc(crtc
, interval
);
1145 void intel_disable_fbc(struct drm_device
*dev
)
1147 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1149 if (!dev_priv
->display
.disable_fbc
)
1152 dev_priv
->display
.disable_fbc(dev
);
1156 * intel_update_fbc - enable/disable FBC as needed
1157 * @crtc: CRTC to point the compressor at
1158 * @mode: mode in use
1160 * Set up the framebuffer compression hardware at mode set time. We
1161 * enable it if possible:
1162 * - plane A only (on pre-965)
1163 * - no pixel mulitply/line duplication
1164 * - no alpha buffer discard
1166 * - framebuffer <= 2048 in width, 1536 in height
1168 * We can't assume that any compression will take place (worst case),
1169 * so the compressed buffer has to be the same size as the uncompressed
1170 * one. It also must reside (along with the line length buffer) in
1173 * We need to enable/disable FBC on a global basis.
1175 static void intel_update_fbc(struct drm_crtc
*crtc
,
1176 struct drm_display_mode
*mode
)
1178 struct drm_device
*dev
= crtc
->dev
;
1179 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1180 struct drm_framebuffer
*fb
= crtc
->fb
;
1181 struct intel_framebuffer
*intel_fb
;
1182 struct drm_i915_gem_object
*obj_priv
;
1183 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1184 int plane
= intel_crtc
->plane
;
1186 if (!i915_powersave
)
1189 if (!I915_HAS_FBC(dev
))
1195 intel_fb
= to_intel_framebuffer(fb
);
1196 obj_priv
= to_intel_bo(intel_fb
->obj
);
1199 * If FBC is already on, we just have to verify that we can
1200 * keep it that way...
1201 * Need to disable if:
1202 * - changing FBC params (stride, fence, mode)
1203 * - new fb is too large to fit in compressed buffer
1204 * - going to an unsupported config (interlace, pixel multiply, etc.)
1206 if (intel_fb
->obj
->size
> dev_priv
->cfb_size
) {
1207 DRM_DEBUG_KMS("framebuffer too large, disabling "
1209 dev_priv
->no_fbc_reason
= FBC_STOLEN_TOO_SMALL
;
1212 if ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
) ||
1213 (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)) {
1214 DRM_DEBUG_KMS("mode incompatible with compression, "
1216 dev_priv
->no_fbc_reason
= FBC_UNSUPPORTED_MODE
;
1219 if ((mode
->hdisplay
> 2048) ||
1220 (mode
->vdisplay
> 1536)) {
1221 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1222 dev_priv
->no_fbc_reason
= FBC_MODE_TOO_LARGE
;
1225 if ((IS_I915GM(dev
) || IS_I945GM(dev
)) && plane
!= 0) {
1226 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1227 dev_priv
->no_fbc_reason
= FBC_BAD_PLANE
;
1230 if (obj_priv
->tiling_mode
!= I915_TILING_X
) {
1231 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1232 dev_priv
->no_fbc_reason
= FBC_NOT_TILED
;
1236 if (intel_fbc_enabled(dev
)) {
1237 /* We can re-enable it in this case, but need to update pitch */
1238 if ((fb
->pitch
> dev_priv
->cfb_pitch
) ||
1239 (obj_priv
->fence_reg
!= dev_priv
->cfb_fence
) ||
1240 (plane
!= dev_priv
->cfb_plane
))
1241 intel_disable_fbc(dev
);
1244 /* Now try to turn it back on if possible */
1245 if (!intel_fbc_enabled(dev
))
1246 intel_enable_fbc(crtc
, 500);
1251 /* Multiple disables should be harmless */
1252 if (intel_fbc_enabled(dev
)) {
1253 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1254 intel_disable_fbc(dev
);
1259 intel_pin_and_fence_fb_obj(struct drm_device
*dev
, struct drm_gem_object
*obj
)
1261 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1265 switch (obj_priv
->tiling_mode
) {
1266 case I915_TILING_NONE
:
1267 alignment
= 64 * 1024;
1270 /* pin() will align the object as required by fence */
1274 /* FIXME: Is this true? */
1275 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1281 ret
= i915_gem_object_pin(obj
, alignment
);
1285 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1286 * fence, whereas 965+ only requires a fence if using
1287 * framebuffer compression. For simplicity, we always install
1288 * a fence as the cost is not that onerous.
1290 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
&&
1291 obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1292 ret
= i915_gem_object_get_fence_reg(obj
);
1294 i915_gem_object_unpin(obj
);
1303 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
1304 struct drm_framebuffer
*old_fb
)
1306 struct drm_device
*dev
= crtc
->dev
;
1307 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1308 struct drm_i915_master_private
*master_priv
;
1309 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1310 struct intel_framebuffer
*intel_fb
;
1311 struct drm_i915_gem_object
*obj_priv
;
1312 struct drm_gem_object
*obj
;
1313 int pipe
= intel_crtc
->pipe
;
1314 int plane
= intel_crtc
->plane
;
1315 unsigned long Start
, Offset
;
1316 int dspbase
= (plane
== 0 ? DSPAADDR
: DSPBADDR
);
1317 int dspsurf
= (plane
== 0 ? DSPASURF
: DSPBSURF
);
1318 int dspstride
= (plane
== 0) ? DSPASTRIDE
: DSPBSTRIDE
;
1319 int dsptileoff
= (plane
== 0 ? DSPATILEOFF
: DSPBTILEOFF
);
1320 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
1326 DRM_DEBUG_KMS("No FB bound\n");
1335 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
1339 intel_fb
= to_intel_framebuffer(crtc
->fb
);
1340 obj
= intel_fb
->obj
;
1341 obj_priv
= to_intel_bo(obj
);
1343 mutex_lock(&dev
->struct_mutex
);
1344 ret
= intel_pin_and_fence_fb_obj(dev
, obj
);
1346 mutex_unlock(&dev
->struct_mutex
);
1350 ret
= i915_gem_object_set_to_display_plane(obj
);
1352 i915_gem_object_unpin(obj
);
1353 mutex_unlock(&dev
->struct_mutex
);
1357 dspcntr
= I915_READ(dspcntr_reg
);
1358 /* Mask out pixel format bits in case we change it */
1359 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
1360 switch (crtc
->fb
->bits_per_pixel
) {
1362 dspcntr
|= DISPPLANE_8BPP
;
1365 if (crtc
->fb
->depth
== 15)
1366 dspcntr
|= DISPPLANE_15_16BPP
;
1368 dspcntr
|= DISPPLANE_16BPP
;
1372 if (crtc
->fb
->depth
== 30)
1373 dspcntr
|= DISPPLANE_32BPP_30BIT_NO_ALPHA
;
1375 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
1378 DRM_ERROR("Unknown color depth\n");
1379 i915_gem_object_unpin(obj
);
1380 mutex_unlock(&dev
->struct_mutex
);
1383 if (IS_I965G(dev
)) {
1384 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1385 dspcntr
|= DISPPLANE_TILED
;
1387 dspcntr
&= ~DISPPLANE_TILED
;
1390 if (HAS_PCH_SPLIT(dev
))
1392 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
1394 I915_WRITE(dspcntr_reg
, dspcntr
);
1396 Start
= obj_priv
->gtt_offset
;
1397 Offset
= y
* crtc
->fb
->pitch
+ x
* (crtc
->fb
->bits_per_pixel
/ 8);
1399 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1400 Start
, Offset
, x
, y
, crtc
->fb
->pitch
);
1401 I915_WRITE(dspstride
, crtc
->fb
->pitch
);
1402 if (IS_I965G(dev
)) {
1403 I915_WRITE(dspbase
, Offset
);
1405 I915_WRITE(dspsurf
, Start
);
1407 I915_WRITE(dsptileoff
, (y
<< 16) | x
);
1409 I915_WRITE(dspbase
, Start
+ Offset
);
1413 if ((IS_I965G(dev
) || plane
== 0))
1414 intel_update_fbc(crtc
, &crtc
->mode
);
1416 intel_wait_for_vblank(dev
);
1419 intel_fb
= to_intel_framebuffer(old_fb
);
1420 obj_priv
= to_intel_bo(intel_fb
->obj
);
1421 i915_gem_object_unpin(intel_fb
->obj
);
1423 intel_increase_pllclock(crtc
, true);
1425 mutex_unlock(&dev
->struct_mutex
);
1427 if (!dev
->primary
->master
)
1430 master_priv
= dev
->primary
->master
->driver_priv
;
1431 if (!master_priv
->sarea_priv
)
1435 master_priv
->sarea_priv
->pipeB_x
= x
;
1436 master_priv
->sarea_priv
->pipeB_y
= y
;
1438 master_priv
->sarea_priv
->pipeA_x
= x
;
1439 master_priv
->sarea_priv
->pipeA_y
= y
;
1445 /* Disable the VGA plane that we never use */
1446 static void i915_disable_vga (struct drm_device
*dev
)
1448 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1452 if (HAS_PCH_SPLIT(dev
))
1453 vga_reg
= CPU_VGACNTRL
;
1457 if (I915_READ(vga_reg
) & VGA_DISP_DISABLE
)
1460 I915_WRITE8(VGA_SR_INDEX
, 1);
1461 sr1
= I915_READ8(VGA_SR_DATA
);
1462 I915_WRITE8(VGA_SR_DATA
, sr1
| (1 << 5));
1465 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
1468 static void ironlake_disable_pll_edp (struct drm_crtc
*crtc
)
1470 struct drm_device
*dev
= crtc
->dev
;
1471 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1474 DRM_DEBUG_KMS("\n");
1475 dpa_ctl
= I915_READ(DP_A
);
1476 dpa_ctl
&= ~DP_PLL_ENABLE
;
1477 I915_WRITE(DP_A
, dpa_ctl
);
1480 static void ironlake_enable_pll_edp (struct drm_crtc
*crtc
)
1482 struct drm_device
*dev
= crtc
->dev
;
1483 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1486 dpa_ctl
= I915_READ(DP_A
);
1487 dpa_ctl
|= DP_PLL_ENABLE
;
1488 I915_WRITE(DP_A
, dpa_ctl
);
1493 static void ironlake_set_pll_edp (struct drm_crtc
*crtc
, int clock
)
1495 struct drm_device
*dev
= crtc
->dev
;
1496 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1499 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock
);
1500 dpa_ctl
= I915_READ(DP_A
);
1501 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1503 if (clock
< 200000) {
1505 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1506 /* workaround for 160Mhz:
1507 1) program 0x4600c bits 15:0 = 0x8124
1508 2) program 0x46010 bit 0 = 1
1509 3) program 0x46034 bit 24 = 1
1510 4) program 0x64000 bit 14 = 1
1512 temp
= I915_READ(0x4600c);
1514 I915_WRITE(0x4600c, temp
| 0x8124);
1516 temp
= I915_READ(0x46010);
1517 I915_WRITE(0x46010, temp
| 1);
1519 temp
= I915_READ(0x46034);
1520 I915_WRITE(0x46034, temp
| (1 << 24));
1522 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1524 I915_WRITE(DP_A
, dpa_ctl
);
1529 /* The FDI link training functions for ILK/Ibexpeak. */
1530 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
1532 struct drm_device
*dev
= crtc
->dev
;
1533 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1534 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1535 int pipe
= intel_crtc
->pipe
;
1536 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
1537 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
1538 int fdi_rx_iir_reg
= (pipe
== 0) ? FDI_RXA_IIR
: FDI_RXB_IIR
;
1539 int fdi_rx_imr_reg
= (pipe
== 0) ? FDI_RXA_IMR
: FDI_RXB_IMR
;
1540 u32 temp
, tries
= 0;
1542 /* enable CPU FDI TX and PCH FDI RX */
1543 temp
= I915_READ(fdi_tx_reg
);
1544 temp
|= FDI_TX_ENABLE
;
1546 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
1547 temp
&= ~FDI_LINK_TRAIN_NONE
;
1548 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1549 I915_WRITE(fdi_tx_reg
, temp
);
1550 I915_READ(fdi_tx_reg
);
1552 temp
= I915_READ(fdi_rx_reg
);
1553 temp
&= ~FDI_LINK_TRAIN_NONE
;
1554 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1555 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_ENABLE
);
1556 I915_READ(fdi_rx_reg
);
1559 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1561 temp
= I915_READ(fdi_rx_imr_reg
);
1562 temp
&= ~FDI_RX_SYMBOL_LOCK
;
1563 temp
&= ~FDI_RX_BIT_LOCK
;
1564 I915_WRITE(fdi_rx_imr_reg
, temp
);
1565 I915_READ(fdi_rx_imr_reg
);
1569 temp
= I915_READ(fdi_rx_iir_reg
);
1570 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1572 if ((temp
& FDI_RX_BIT_LOCK
)) {
1573 DRM_DEBUG_KMS("FDI train 1 done.\n");
1574 I915_WRITE(fdi_rx_iir_reg
,
1575 temp
| FDI_RX_BIT_LOCK
);
1582 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1588 temp
= I915_READ(fdi_tx_reg
);
1589 temp
&= ~FDI_LINK_TRAIN_NONE
;
1590 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1591 I915_WRITE(fdi_tx_reg
, temp
);
1593 temp
= I915_READ(fdi_rx_reg
);
1594 temp
&= ~FDI_LINK_TRAIN_NONE
;
1595 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1596 I915_WRITE(fdi_rx_reg
, temp
);
1602 temp
= I915_READ(fdi_rx_iir_reg
);
1603 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1605 if (temp
& FDI_RX_SYMBOL_LOCK
) {
1606 I915_WRITE(fdi_rx_iir_reg
,
1607 temp
| FDI_RX_SYMBOL_LOCK
);
1608 DRM_DEBUG_KMS("FDI train 2 done.\n");
1615 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1620 DRM_DEBUG_KMS("FDI train done\n");
1623 static int snb_b_fdi_train_param
[] = {
1624 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
1625 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
1626 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
1627 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
1630 /* The FDI link training functions for SNB/Cougarpoint. */
1631 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
1633 struct drm_device
*dev
= crtc
->dev
;
1634 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1635 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1636 int pipe
= intel_crtc
->pipe
;
1637 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
1638 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
1639 int fdi_rx_iir_reg
= (pipe
== 0) ? FDI_RXA_IIR
: FDI_RXB_IIR
;
1640 int fdi_rx_imr_reg
= (pipe
== 0) ? FDI_RXA_IMR
: FDI_RXB_IMR
;
1643 /* enable CPU FDI TX and PCH FDI RX */
1644 temp
= I915_READ(fdi_tx_reg
);
1645 temp
|= FDI_TX_ENABLE
;
1647 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
1648 temp
&= ~FDI_LINK_TRAIN_NONE
;
1649 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1650 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1652 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
1653 I915_WRITE(fdi_tx_reg
, temp
);
1654 I915_READ(fdi_tx_reg
);
1656 temp
= I915_READ(fdi_rx_reg
);
1657 if (HAS_PCH_CPT(dev
)) {
1658 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
1659 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
1661 temp
&= ~FDI_LINK_TRAIN_NONE
;
1662 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1664 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_ENABLE
);
1665 I915_READ(fdi_rx_reg
);
1668 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1670 temp
= I915_READ(fdi_rx_imr_reg
);
1671 temp
&= ~FDI_RX_SYMBOL_LOCK
;
1672 temp
&= ~FDI_RX_BIT_LOCK
;
1673 I915_WRITE(fdi_rx_imr_reg
, temp
);
1674 I915_READ(fdi_rx_imr_reg
);
1677 for (i
= 0; i
< 4; i
++ ) {
1678 temp
= I915_READ(fdi_tx_reg
);
1679 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1680 temp
|= snb_b_fdi_train_param
[i
];
1681 I915_WRITE(fdi_tx_reg
, temp
);
1684 temp
= I915_READ(fdi_rx_iir_reg
);
1685 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1687 if (temp
& FDI_RX_BIT_LOCK
) {
1688 I915_WRITE(fdi_rx_iir_reg
,
1689 temp
| FDI_RX_BIT_LOCK
);
1690 DRM_DEBUG_KMS("FDI train 1 done.\n");
1695 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1698 temp
= I915_READ(fdi_tx_reg
);
1699 temp
&= ~FDI_LINK_TRAIN_NONE
;
1700 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1702 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1704 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
1706 I915_WRITE(fdi_tx_reg
, temp
);
1708 temp
= I915_READ(fdi_rx_reg
);
1709 if (HAS_PCH_CPT(dev
)) {
1710 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
1711 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
1713 temp
&= ~FDI_LINK_TRAIN_NONE
;
1714 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1716 I915_WRITE(fdi_rx_reg
, temp
);
1719 for (i
= 0; i
< 4; i
++ ) {
1720 temp
= I915_READ(fdi_tx_reg
);
1721 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1722 temp
|= snb_b_fdi_train_param
[i
];
1723 I915_WRITE(fdi_tx_reg
, temp
);
1726 temp
= I915_READ(fdi_rx_iir_reg
);
1727 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1729 if (temp
& FDI_RX_SYMBOL_LOCK
) {
1730 I915_WRITE(fdi_rx_iir_reg
,
1731 temp
| FDI_RX_SYMBOL_LOCK
);
1732 DRM_DEBUG_KMS("FDI train 2 done.\n");
1737 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1739 DRM_DEBUG_KMS("FDI train done.\n");
1742 static void ironlake_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
1744 struct drm_device
*dev
= crtc
->dev
;
1745 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1746 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1747 int pipe
= intel_crtc
->pipe
;
1748 int plane
= intel_crtc
->plane
;
1749 int pch_dpll_reg
= (pipe
== 0) ? PCH_DPLL_A
: PCH_DPLL_B
;
1750 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
1751 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
1752 int dspbase_reg
= (plane
== 0) ? DSPAADDR
: DSPBADDR
;
1753 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
1754 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
1755 int transconf_reg
= (pipe
== 0) ? TRANSACONF
: TRANSBCONF
;
1756 int pf_ctl_reg
= (pipe
== 0) ? PFA_CTL_1
: PFB_CTL_1
;
1757 int pf_win_size
= (pipe
== 0) ? PFA_WIN_SZ
: PFB_WIN_SZ
;
1758 int pf_win_pos
= (pipe
== 0) ? PFA_WIN_POS
: PFB_WIN_POS
;
1759 int cpu_htot_reg
= (pipe
== 0) ? HTOTAL_A
: HTOTAL_B
;
1760 int cpu_hblank_reg
= (pipe
== 0) ? HBLANK_A
: HBLANK_B
;
1761 int cpu_hsync_reg
= (pipe
== 0) ? HSYNC_A
: HSYNC_B
;
1762 int cpu_vtot_reg
= (pipe
== 0) ? VTOTAL_A
: VTOTAL_B
;
1763 int cpu_vblank_reg
= (pipe
== 0) ? VBLANK_A
: VBLANK_B
;
1764 int cpu_vsync_reg
= (pipe
== 0) ? VSYNC_A
: VSYNC_B
;
1765 int trans_htot_reg
= (pipe
== 0) ? TRANS_HTOTAL_A
: TRANS_HTOTAL_B
;
1766 int trans_hblank_reg
= (pipe
== 0) ? TRANS_HBLANK_A
: TRANS_HBLANK_B
;
1767 int trans_hsync_reg
= (pipe
== 0) ? TRANS_HSYNC_A
: TRANS_HSYNC_B
;
1768 int trans_vtot_reg
= (pipe
== 0) ? TRANS_VTOTAL_A
: TRANS_VTOTAL_B
;
1769 int trans_vblank_reg
= (pipe
== 0) ? TRANS_VBLANK_A
: TRANS_VBLANK_B
;
1770 int trans_vsync_reg
= (pipe
== 0) ? TRANS_VSYNC_A
: TRANS_VSYNC_B
;
1771 int trans_dpll_sel
= (pipe
== 0) ? 0 : 1;
1776 temp
= I915_READ(pipeconf_reg
);
1777 pipe_bpc
= temp
& PIPE_BPC_MASK
;
1779 /* XXX: When our outputs are all unaware of DPMS modes other than off
1780 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1783 case DRM_MODE_DPMS_ON
:
1784 case DRM_MODE_DPMS_STANDBY
:
1785 case DRM_MODE_DPMS_SUSPEND
:
1786 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe
);
1788 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
1789 temp
= I915_READ(PCH_LVDS
);
1790 if ((temp
& LVDS_PORT_EN
) == 0) {
1791 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
1792 POSTING_READ(PCH_LVDS
);
1797 /* enable eDP PLL */
1798 ironlake_enable_pll_edp(crtc
);
1801 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1802 temp
= I915_READ(fdi_rx_reg
);
1804 * make the BPC in FDI Rx be consistent with that in
1807 temp
&= ~(0x7 << 16);
1808 temp
|= (pipe_bpc
<< 11);
1810 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
1811 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_PLL_ENABLE
);
1812 I915_READ(fdi_rx_reg
);
1815 /* Switch from Rawclk to PCDclk */
1816 temp
= I915_READ(fdi_rx_reg
);
1817 I915_WRITE(fdi_rx_reg
, temp
| FDI_SEL_PCDCLK
);
1818 I915_READ(fdi_rx_reg
);
1821 /* Enable CPU FDI TX PLL, always on for Ironlake */
1822 temp
= I915_READ(fdi_tx_reg
);
1823 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
1824 I915_WRITE(fdi_tx_reg
, temp
| FDI_TX_PLL_ENABLE
);
1825 I915_READ(fdi_tx_reg
);
1830 /* Enable panel fitting for LVDS */
1831 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
1832 temp
= I915_READ(pf_ctl_reg
);
1833 I915_WRITE(pf_ctl_reg
, temp
| PF_ENABLE
| PF_FILTER_MED_3x3
);
1835 /* currently full aspect */
1836 I915_WRITE(pf_win_pos
, 0);
1838 I915_WRITE(pf_win_size
,
1839 (dev_priv
->panel_fixed_mode
->hdisplay
<< 16) |
1840 (dev_priv
->panel_fixed_mode
->vdisplay
));
1843 /* Enable CPU pipe */
1844 temp
= I915_READ(pipeconf_reg
);
1845 if ((temp
& PIPEACONF_ENABLE
) == 0) {
1846 I915_WRITE(pipeconf_reg
, temp
| PIPEACONF_ENABLE
);
1847 I915_READ(pipeconf_reg
);
1851 /* configure and enable CPU plane */
1852 temp
= I915_READ(dspcntr_reg
);
1853 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
1854 I915_WRITE(dspcntr_reg
, temp
| DISPLAY_PLANE_ENABLE
);
1855 /* Flush the plane changes */
1856 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
1860 /* For PCH output, training FDI link */
1862 gen6_fdi_link_train(crtc
);
1864 ironlake_fdi_link_train(crtc
);
1866 /* enable PCH DPLL */
1867 temp
= I915_READ(pch_dpll_reg
);
1868 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
1869 I915_WRITE(pch_dpll_reg
, temp
| DPLL_VCO_ENABLE
);
1870 I915_READ(pch_dpll_reg
);
1874 if (HAS_PCH_CPT(dev
)) {
1875 /* Be sure PCH DPLL SEL is set */
1876 temp
= I915_READ(PCH_DPLL_SEL
);
1877 if (trans_dpll_sel
== 0 &&
1878 (temp
& TRANSA_DPLL_ENABLE
) == 0)
1879 temp
|= (TRANSA_DPLL_ENABLE
| TRANSA_DPLLA_SEL
);
1880 else if (trans_dpll_sel
== 1 &&
1881 (temp
& TRANSB_DPLL_ENABLE
) == 0)
1882 temp
|= (TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
1883 I915_WRITE(PCH_DPLL_SEL
, temp
);
1884 I915_READ(PCH_DPLL_SEL
);
1887 /* set transcoder timing */
1888 I915_WRITE(trans_htot_reg
, I915_READ(cpu_htot_reg
));
1889 I915_WRITE(trans_hblank_reg
, I915_READ(cpu_hblank_reg
));
1890 I915_WRITE(trans_hsync_reg
, I915_READ(cpu_hsync_reg
));
1892 I915_WRITE(trans_vtot_reg
, I915_READ(cpu_vtot_reg
));
1893 I915_WRITE(trans_vblank_reg
, I915_READ(cpu_vblank_reg
));
1894 I915_WRITE(trans_vsync_reg
, I915_READ(cpu_vsync_reg
));
1896 /* enable normal train */
1897 temp
= I915_READ(fdi_tx_reg
);
1898 temp
&= ~FDI_LINK_TRAIN_NONE
;
1899 I915_WRITE(fdi_tx_reg
, temp
| FDI_LINK_TRAIN_NONE
|
1900 FDI_TX_ENHANCE_FRAME_ENABLE
);
1901 I915_READ(fdi_tx_reg
);
1903 temp
= I915_READ(fdi_rx_reg
);
1904 if (HAS_PCH_CPT(dev
)) {
1905 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
1906 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
1908 temp
&= ~FDI_LINK_TRAIN_NONE
;
1909 temp
|= FDI_LINK_TRAIN_NONE
;
1911 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
1912 I915_READ(fdi_rx_reg
);
1914 /* wait one idle pattern time */
1917 /* For PCH DP, enable TRANS_DP_CTL */
1918 if (HAS_PCH_CPT(dev
) &&
1919 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
1920 int trans_dp_ctl
= (pipe
== 0) ? TRANS_DP_CTL_A
: TRANS_DP_CTL_B
;
1923 reg
= I915_READ(trans_dp_ctl
);
1924 reg
&= ~TRANS_DP_PORT_SEL_MASK
;
1925 reg
= TRANS_DP_OUTPUT_ENABLE
|
1926 TRANS_DP_ENH_FRAMING
|
1927 TRANS_DP_VSYNC_ACTIVE_HIGH
|
1928 TRANS_DP_HSYNC_ACTIVE_HIGH
;
1930 switch (intel_trans_dp_port_sel(crtc
)) {
1932 reg
|= TRANS_DP_PORT_SEL_B
;
1935 reg
|= TRANS_DP_PORT_SEL_C
;
1938 reg
|= TRANS_DP_PORT_SEL_D
;
1941 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
1942 reg
|= TRANS_DP_PORT_SEL_B
;
1946 I915_WRITE(trans_dp_ctl
, reg
);
1947 POSTING_READ(trans_dp_ctl
);
1950 /* enable PCH transcoder */
1951 temp
= I915_READ(transconf_reg
);
1953 * make the BPC in transcoder be consistent with
1954 * that in pipeconf reg.
1956 temp
&= ~PIPE_BPC_MASK
;
1958 I915_WRITE(transconf_reg
, temp
| TRANS_ENABLE
);
1959 I915_READ(transconf_reg
);
1961 while ((I915_READ(transconf_reg
) & TRANS_STATE_ENABLE
) == 0)
1966 intel_crtc_load_lut(crtc
);
1969 case DRM_MODE_DPMS_OFF
:
1970 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe
);
1972 drm_vblank_off(dev
, pipe
);
1973 /* Disable display plane */
1974 temp
= I915_READ(dspcntr_reg
);
1975 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
1976 I915_WRITE(dspcntr_reg
, temp
& ~DISPLAY_PLANE_ENABLE
);
1977 /* Flush the plane changes */
1978 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
1979 I915_READ(dspbase_reg
);
1982 i915_disable_vga(dev
);
1984 /* disable cpu pipe, disable after all planes disabled */
1985 temp
= I915_READ(pipeconf_reg
);
1986 if ((temp
& PIPEACONF_ENABLE
) != 0) {
1987 I915_WRITE(pipeconf_reg
, temp
& ~PIPEACONF_ENABLE
);
1988 I915_READ(pipeconf_reg
);
1990 /* wait for cpu pipe off, pipe state */
1991 while ((I915_READ(pipeconf_reg
) & I965_PIPECONF_ACTIVE
) != 0) {
1997 DRM_DEBUG_KMS("pipe %d off delay\n",
2003 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
2008 temp
= I915_READ(pf_ctl_reg
);
2009 if ((temp
& PF_ENABLE
) != 0) {
2010 I915_WRITE(pf_ctl_reg
, temp
& ~PF_ENABLE
);
2011 I915_READ(pf_ctl_reg
);
2013 I915_WRITE(pf_win_size
, 0);
2014 POSTING_READ(pf_win_size
);
2017 /* disable CPU FDI tx and PCH FDI rx */
2018 temp
= I915_READ(fdi_tx_reg
);
2019 I915_WRITE(fdi_tx_reg
, temp
& ~FDI_TX_ENABLE
);
2020 I915_READ(fdi_tx_reg
);
2022 temp
= I915_READ(fdi_rx_reg
);
2023 /* BPC in FDI rx is consistent with that in pipeconf */
2024 temp
&= ~(0x07 << 16);
2025 temp
|= (pipe_bpc
<< 11);
2026 I915_WRITE(fdi_rx_reg
, temp
& ~FDI_RX_ENABLE
);
2027 I915_READ(fdi_rx_reg
);
2031 /* still set train pattern 1 */
2032 temp
= I915_READ(fdi_tx_reg
);
2033 temp
&= ~FDI_LINK_TRAIN_NONE
;
2034 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2035 I915_WRITE(fdi_tx_reg
, temp
);
2036 POSTING_READ(fdi_tx_reg
);
2038 temp
= I915_READ(fdi_rx_reg
);
2039 if (HAS_PCH_CPT(dev
)) {
2040 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2041 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2043 temp
&= ~FDI_LINK_TRAIN_NONE
;
2044 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2046 I915_WRITE(fdi_rx_reg
, temp
);
2047 POSTING_READ(fdi_rx_reg
);
2051 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
2052 temp
= I915_READ(PCH_LVDS
);
2053 I915_WRITE(PCH_LVDS
, temp
& ~LVDS_PORT_EN
);
2054 I915_READ(PCH_LVDS
);
2058 /* disable PCH transcoder */
2059 temp
= I915_READ(transconf_reg
);
2060 if ((temp
& TRANS_ENABLE
) != 0) {
2061 I915_WRITE(transconf_reg
, temp
& ~TRANS_ENABLE
);
2062 I915_READ(transconf_reg
);
2064 /* wait for PCH transcoder off, transcoder state */
2065 while ((I915_READ(transconf_reg
) & TRANS_STATE_ENABLE
) != 0) {
2071 DRM_DEBUG_KMS("transcoder %d off "
2078 temp
= I915_READ(transconf_reg
);
2079 /* BPC in transcoder is consistent with that in pipeconf */
2080 temp
&= ~PIPE_BPC_MASK
;
2082 I915_WRITE(transconf_reg
, temp
);
2083 I915_READ(transconf_reg
);
2086 if (HAS_PCH_CPT(dev
)) {
2087 /* disable TRANS_DP_CTL */
2088 int trans_dp_ctl
= (pipe
== 0) ? TRANS_DP_CTL_A
: TRANS_DP_CTL_B
;
2091 reg
= I915_READ(trans_dp_ctl
);
2092 reg
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
2093 I915_WRITE(trans_dp_ctl
, reg
);
2094 POSTING_READ(trans_dp_ctl
);
2096 /* disable DPLL_SEL */
2097 temp
= I915_READ(PCH_DPLL_SEL
);
2098 if (trans_dpll_sel
== 0)
2099 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLB_SEL
);
2101 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
2102 I915_WRITE(PCH_DPLL_SEL
, temp
);
2103 I915_READ(PCH_DPLL_SEL
);
2107 /* disable PCH DPLL */
2108 temp
= I915_READ(pch_dpll_reg
);
2109 I915_WRITE(pch_dpll_reg
, temp
& ~DPLL_VCO_ENABLE
);
2110 I915_READ(pch_dpll_reg
);
2113 ironlake_disable_pll_edp(crtc
);
2116 /* Switch from PCDclk to Rawclk */
2117 temp
= I915_READ(fdi_rx_reg
);
2118 temp
&= ~FDI_SEL_PCDCLK
;
2119 I915_WRITE(fdi_rx_reg
, temp
);
2120 I915_READ(fdi_rx_reg
);
2122 /* Disable CPU FDI TX PLL */
2123 temp
= I915_READ(fdi_tx_reg
);
2124 I915_WRITE(fdi_tx_reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2125 I915_READ(fdi_tx_reg
);
2128 temp
= I915_READ(fdi_rx_reg
);
2129 temp
&= ~FDI_RX_PLL_ENABLE
;
2130 I915_WRITE(fdi_rx_reg
, temp
);
2131 I915_READ(fdi_rx_reg
);
2133 /* Wait for the clocks to turn off. */
2139 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
2141 struct intel_overlay
*overlay
;
2144 if (!enable
&& intel_crtc
->overlay
) {
2145 overlay
= intel_crtc
->overlay
;
2146 mutex_lock(&overlay
->dev
->struct_mutex
);
2148 ret
= intel_overlay_switch_off(overlay
);
2152 ret
= intel_overlay_recover_from_interrupt(overlay
, 0);
2154 /* overlay doesn't react anymore. Usually
2155 * results in a black screen and an unkillable
2158 overlay
->hw_wedged
= HW_WEDGED
;
2162 mutex_unlock(&overlay
->dev
->struct_mutex
);
2164 /* Let userspace switch the overlay on again. In most cases userspace
2165 * has to recompute where to put it anyway. */
2170 static void i9xx_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2172 struct drm_device
*dev
= crtc
->dev
;
2173 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2174 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2175 int pipe
= intel_crtc
->pipe
;
2176 int plane
= intel_crtc
->plane
;
2177 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
2178 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
2179 int dspbase_reg
= (plane
== 0) ? DSPAADDR
: DSPBADDR
;
2180 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
2183 /* XXX: When our outputs are all unaware of DPMS modes other than off
2184 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2187 case DRM_MODE_DPMS_ON
:
2188 case DRM_MODE_DPMS_STANDBY
:
2189 case DRM_MODE_DPMS_SUSPEND
:
2190 intel_update_watermarks(dev
);
2192 /* Enable the DPLL */
2193 temp
= I915_READ(dpll_reg
);
2194 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
2195 I915_WRITE(dpll_reg
, temp
);
2196 I915_READ(dpll_reg
);
2197 /* Wait for the clocks to stabilize. */
2199 I915_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
2200 I915_READ(dpll_reg
);
2201 /* Wait for the clocks to stabilize. */
2203 I915_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
2204 I915_READ(dpll_reg
);
2205 /* Wait for the clocks to stabilize. */
2209 /* Enable the pipe */
2210 temp
= I915_READ(pipeconf_reg
);
2211 if ((temp
& PIPEACONF_ENABLE
) == 0)
2212 I915_WRITE(pipeconf_reg
, temp
| PIPEACONF_ENABLE
);
2214 /* Enable the plane */
2215 temp
= I915_READ(dspcntr_reg
);
2216 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
2217 I915_WRITE(dspcntr_reg
, temp
| DISPLAY_PLANE_ENABLE
);
2218 /* Flush the plane changes */
2219 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
2222 intel_crtc_load_lut(crtc
);
2224 if ((IS_I965G(dev
) || plane
== 0))
2225 intel_update_fbc(crtc
, &crtc
->mode
);
2227 /* Give the overlay scaler a chance to enable if it's on this pipe */
2228 intel_crtc_dpms_overlay(intel_crtc
, true);
2230 case DRM_MODE_DPMS_OFF
:
2231 intel_update_watermarks(dev
);
2233 /* Give the overlay scaler a chance to disable if it's on this pipe */
2234 intel_crtc_dpms_overlay(intel_crtc
, false);
2235 drm_vblank_off(dev
, pipe
);
2237 if (dev_priv
->cfb_plane
== plane
&&
2238 dev_priv
->display
.disable_fbc
)
2239 dev_priv
->display
.disable_fbc(dev
);
2241 /* Disable the VGA plane that we never use */
2242 i915_disable_vga(dev
);
2244 /* Disable display plane */
2245 temp
= I915_READ(dspcntr_reg
);
2246 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
2247 I915_WRITE(dspcntr_reg
, temp
& ~DISPLAY_PLANE_ENABLE
);
2248 /* Flush the plane changes */
2249 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
2250 I915_READ(dspbase_reg
);
2253 if (!IS_I9XX(dev
)) {
2254 /* Wait for vblank for the disable to take effect */
2255 intel_wait_for_vblank(dev
);
2258 /* Next, disable display pipes */
2259 temp
= I915_READ(pipeconf_reg
);
2260 if ((temp
& PIPEACONF_ENABLE
) != 0) {
2261 I915_WRITE(pipeconf_reg
, temp
& ~PIPEACONF_ENABLE
);
2262 I915_READ(pipeconf_reg
);
2265 /* Wait for vblank for the disable to take effect. */
2266 intel_wait_for_vblank(dev
);
2268 temp
= I915_READ(dpll_reg
);
2269 if ((temp
& DPLL_VCO_ENABLE
) != 0) {
2270 I915_WRITE(dpll_reg
, temp
& ~DPLL_VCO_ENABLE
);
2271 I915_READ(dpll_reg
);
2274 /* Wait for the clocks to turn off. */
2281 * Sets the power management mode of the pipe and plane.
2283 * This code should probably grow support for turning the cursor off and back
2284 * on appropriately at the same time as we're turning the pipe off/on.
2286 static void intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2288 struct drm_device
*dev
= crtc
->dev
;
2289 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2290 struct drm_i915_master_private
*master_priv
;
2291 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2292 int pipe
= intel_crtc
->pipe
;
2295 dev_priv
->display
.dpms(crtc
, mode
);
2297 intel_crtc
->dpms_mode
= mode
;
2299 if (!dev
->primary
->master
)
2302 master_priv
= dev
->primary
->master
->driver_priv
;
2303 if (!master_priv
->sarea_priv
)
2306 enabled
= crtc
->enabled
&& mode
!= DRM_MODE_DPMS_OFF
;
2310 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
2311 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
2314 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
2315 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
2318 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe
);
2323 static void intel_crtc_prepare (struct drm_crtc
*crtc
)
2325 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
2326 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
2329 static void intel_crtc_commit (struct drm_crtc
*crtc
)
2331 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
2332 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
2335 void intel_encoder_prepare (struct drm_encoder
*encoder
)
2337 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
2338 /* lvds has its own version of prepare see intel_lvds_prepare */
2339 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
2342 void intel_encoder_commit (struct drm_encoder
*encoder
)
2344 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
2345 /* lvds has its own version of commit see intel_lvds_commit */
2346 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
2349 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
2350 struct drm_display_mode
*mode
,
2351 struct drm_display_mode
*adjusted_mode
)
2353 struct drm_device
*dev
= crtc
->dev
;
2354 if (HAS_PCH_SPLIT(dev
)) {
2355 /* FDI link clock is fixed at 2.7G */
2356 if (mode
->clock
* 3 > 27000 * 4)
2357 return MODE_CLOCK_HIGH
;
2360 drm_mode_set_crtcinfo(adjusted_mode
, 0);
2364 static int i945_get_display_clock_speed(struct drm_device
*dev
)
2369 static int i915_get_display_clock_speed(struct drm_device
*dev
)
2374 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
2379 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
2383 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
2385 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
2388 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
2389 case GC_DISPLAY_CLOCK_333_MHZ
:
2392 case GC_DISPLAY_CLOCK_190_200_MHZ
:
2398 static int i865_get_display_clock_speed(struct drm_device
*dev
)
2403 static int i855_get_display_clock_speed(struct drm_device
*dev
)
2406 /* Assume that the hardware is in the high speed state. This
2407 * should be the default.
2409 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
2410 case GC_CLOCK_133_200
:
2411 case GC_CLOCK_100_200
:
2413 case GC_CLOCK_166_250
:
2415 case GC_CLOCK_100_133
:
2419 /* Shouldn't happen */
2423 static int i830_get_display_clock_speed(struct drm_device
*dev
)
2429 * Return the pipe currently connected to the panel fitter,
2430 * or -1 if the panel fitter is not present or not in use
2432 int intel_panel_fitter_pipe (struct drm_device
*dev
)
2434 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2437 /* i830 doesn't have a panel fitter */
2441 pfit_control
= I915_READ(PFIT_CONTROL
);
2443 /* See if the panel fitter is in use */
2444 if ((pfit_control
& PFIT_ENABLE
) == 0)
2447 /* 965 can place panel fitter on either pipe */
2449 return (pfit_control
>> 29) & 0x3;
2451 /* older chips can only use pipe 1 */
2464 fdi_reduce_ratio(u32
*num
, u32
*den
)
2466 while (*num
> 0xffffff || *den
> 0xffffff) {
2472 #define DATA_N 0x800000
2473 #define LINK_N 0x80000
2476 ironlake_compute_m_n(int bits_per_pixel
, int nlanes
, int pixel_clock
,
2477 int link_clock
, struct fdi_m_n
*m_n
)
2481 m_n
->tu
= 64; /* default size */
2483 temp
= (u64
) DATA_N
* pixel_clock
;
2484 temp
= div_u64(temp
, link_clock
);
2485 m_n
->gmch_m
= div_u64(temp
* bits_per_pixel
, nlanes
);
2486 m_n
->gmch_m
>>= 3; /* convert to bytes_per_pixel */
2487 m_n
->gmch_n
= DATA_N
;
2488 fdi_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
2490 temp
= (u64
) LINK_N
* pixel_clock
;
2491 m_n
->link_m
= div_u64(temp
, link_clock
);
2492 m_n
->link_n
= LINK_N
;
2493 fdi_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
2497 struct intel_watermark_params
{
2498 unsigned long fifo_size
;
2499 unsigned long max_wm
;
2500 unsigned long default_wm
;
2501 unsigned long guard_size
;
2502 unsigned long cacheline_size
;
2505 /* Pineview has different values for various configs */
2506 static struct intel_watermark_params pineview_display_wm
= {
2507 PINEVIEW_DISPLAY_FIFO
,
2511 PINEVIEW_FIFO_LINE_SIZE
2513 static struct intel_watermark_params pineview_display_hplloff_wm
= {
2514 PINEVIEW_DISPLAY_FIFO
,
2516 PINEVIEW_DFT_HPLLOFF_WM
,
2518 PINEVIEW_FIFO_LINE_SIZE
2520 static struct intel_watermark_params pineview_cursor_wm
= {
2521 PINEVIEW_CURSOR_FIFO
,
2522 PINEVIEW_CURSOR_MAX_WM
,
2523 PINEVIEW_CURSOR_DFT_WM
,
2524 PINEVIEW_CURSOR_GUARD_WM
,
2525 PINEVIEW_FIFO_LINE_SIZE
,
2527 static struct intel_watermark_params pineview_cursor_hplloff_wm
= {
2528 PINEVIEW_CURSOR_FIFO
,
2529 PINEVIEW_CURSOR_MAX_WM
,
2530 PINEVIEW_CURSOR_DFT_WM
,
2531 PINEVIEW_CURSOR_GUARD_WM
,
2532 PINEVIEW_FIFO_LINE_SIZE
2534 static struct intel_watermark_params g4x_wm_info
= {
2541 static struct intel_watermark_params i945_wm_info
= {
2548 static struct intel_watermark_params i915_wm_info
= {
2555 static struct intel_watermark_params i855_wm_info
= {
2562 static struct intel_watermark_params i830_wm_info
= {
2570 static struct intel_watermark_params ironlake_display_wm_info
= {
2578 static struct intel_watermark_params ironlake_display_srwm_info
= {
2579 ILK_DISPLAY_SR_FIFO
,
2580 ILK_DISPLAY_MAX_SRWM
,
2581 ILK_DISPLAY_DFT_SRWM
,
2586 static struct intel_watermark_params ironlake_cursor_srwm_info
= {
2588 ILK_CURSOR_MAX_SRWM
,
2589 ILK_CURSOR_DFT_SRWM
,
2595 * intel_calculate_wm - calculate watermark level
2596 * @clock_in_khz: pixel clock
2597 * @wm: chip FIFO params
2598 * @pixel_size: display pixel size
2599 * @latency_ns: memory latency for the platform
2601 * Calculate the watermark level (the level at which the display plane will
2602 * start fetching from memory again). Each chip has a different display
2603 * FIFO size and allocation, so the caller needs to figure that out and pass
2604 * in the correct intel_watermark_params structure.
2606 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2607 * on the pixel size. When it reaches the watermark level, it'll start
2608 * fetching FIFO line sized based chunks from memory until the FIFO fills
2609 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2610 * will occur, and a display engine hang could result.
2612 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
2613 struct intel_watermark_params
*wm
,
2615 unsigned long latency_ns
)
2617 long entries_required
, wm_size
;
2620 * Note: we need to make sure we don't overflow for various clock &
2622 * clocks go from a few thousand to several hundred thousand.
2623 * latency is usually a few thousand
2625 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
2627 entries_required
/= wm
->cacheline_size
;
2629 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required
);
2631 wm_size
= wm
->fifo_size
- (entries_required
+ wm
->guard_size
);
2633 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size
);
2635 /* Don't promote wm_size to unsigned... */
2636 if (wm_size
> (long)wm
->max_wm
)
2637 wm_size
= wm
->max_wm
;
2639 wm_size
= wm
->default_wm
;
2643 struct cxsr_latency
{
2646 unsigned long fsb_freq
;
2647 unsigned long mem_freq
;
2648 unsigned long display_sr
;
2649 unsigned long display_hpll_disable
;
2650 unsigned long cursor_sr
;
2651 unsigned long cursor_hpll_disable
;
2654 static struct cxsr_latency cxsr_latency_table
[] = {
2655 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2656 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2657 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2658 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2659 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2661 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2662 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2663 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2664 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2665 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2667 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2668 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2669 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2670 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2671 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2673 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2674 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2675 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2676 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2677 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2679 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2680 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2681 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2682 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2683 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2685 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2686 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2687 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2688 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2689 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2692 static struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
, int is_ddr3
,
2696 struct cxsr_latency
*latency
;
2698 if (fsb
== 0 || mem
== 0)
2701 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
2702 latency
= &cxsr_latency_table
[i
];
2703 if (is_desktop
== latency
->is_desktop
&&
2704 is_ddr3
== latency
->is_ddr3
&&
2705 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
2709 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2714 static void pineview_disable_cxsr(struct drm_device
*dev
)
2716 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2719 /* deactivate cxsr */
2720 reg
= I915_READ(DSPFW3
);
2721 reg
&= ~(PINEVIEW_SELF_REFRESH_EN
);
2722 I915_WRITE(DSPFW3
, reg
);
2723 DRM_INFO("Big FIFO is disabled\n");
2727 * Latency for FIFO fetches is dependent on several factors:
2728 * - memory configuration (speed, channels)
2730 * - current MCH state
2731 * It can be fairly high in some situations, so here we assume a fairly
2732 * pessimal value. It's a tradeoff between extra memory fetches (if we
2733 * set this value too high, the FIFO will fetch frequently to stay full)
2734 * and power consumption (set it too low to save power and we might see
2735 * FIFO underruns and display "flicker").
2737 * A value of 5us seems to be a good balance; safe for very low end
2738 * platforms but not overly aggressive on lower latency configs.
2740 static const int latency_ns
= 5000;
2742 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
2744 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2745 uint32_t dsparb
= I915_READ(DSPARB
);
2749 size
= dsparb
& 0x7f;
2751 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) -
2754 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2755 plane
? "B" : "A", size
);
2760 static int i85x_get_fifo_size(struct drm_device
*dev
, int plane
)
2762 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2763 uint32_t dsparb
= I915_READ(DSPARB
);
2767 size
= dsparb
& 0x1ff;
2769 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) -
2771 size
>>= 1; /* Convert to cachelines */
2773 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2774 plane
? "B" : "A", size
);
2779 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
2781 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2782 uint32_t dsparb
= I915_READ(DSPARB
);
2785 size
= dsparb
& 0x7f;
2786 size
>>= 2; /* Convert to cachelines */
2788 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2795 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
2797 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2798 uint32_t dsparb
= I915_READ(DSPARB
);
2801 size
= dsparb
& 0x7f;
2802 size
>>= 1; /* Convert to cachelines */
2804 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2805 plane
? "B" : "A", size
);
2810 static void pineview_update_wm(struct drm_device
*dev
, int planea_clock
,
2811 int planeb_clock
, int sr_hdisplay
, int pixel_size
)
2813 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2816 struct cxsr_latency
*latency
;
2819 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
2820 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
2822 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2823 pineview_disable_cxsr(dev
);
2827 if (!planea_clock
|| !planeb_clock
) {
2828 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
2831 wm
= intel_calculate_wm(sr_clock
, &pineview_display_wm
,
2832 pixel_size
, latency
->display_sr
);
2833 reg
= I915_READ(DSPFW1
);
2834 reg
&= ~DSPFW_SR_MASK
;
2835 reg
|= wm
<< DSPFW_SR_SHIFT
;
2836 I915_WRITE(DSPFW1
, reg
);
2837 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
2840 wm
= intel_calculate_wm(sr_clock
, &pineview_cursor_wm
,
2841 pixel_size
, latency
->cursor_sr
);
2842 reg
= I915_READ(DSPFW3
);
2843 reg
&= ~DSPFW_CURSOR_SR_MASK
;
2844 reg
|= (wm
& 0x3f) << DSPFW_CURSOR_SR_SHIFT
;
2845 I915_WRITE(DSPFW3
, reg
);
2847 /* Display HPLL off SR */
2848 wm
= intel_calculate_wm(sr_clock
, &pineview_display_hplloff_wm
,
2849 pixel_size
, latency
->display_hpll_disable
);
2850 reg
= I915_READ(DSPFW3
);
2851 reg
&= ~DSPFW_HPLL_SR_MASK
;
2852 reg
|= wm
& DSPFW_HPLL_SR_MASK
;
2853 I915_WRITE(DSPFW3
, reg
);
2855 /* cursor HPLL off SR */
2856 wm
= intel_calculate_wm(sr_clock
, &pineview_cursor_hplloff_wm
,
2857 pixel_size
, latency
->cursor_hpll_disable
);
2858 reg
= I915_READ(DSPFW3
);
2859 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
2860 reg
|= (wm
& 0x3f) << DSPFW_HPLL_CURSOR_SHIFT
;
2861 I915_WRITE(DSPFW3
, reg
);
2862 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
2865 reg
= I915_READ(DSPFW3
);
2866 reg
|= PINEVIEW_SELF_REFRESH_EN
;
2867 I915_WRITE(DSPFW3
, reg
);
2868 DRM_DEBUG_KMS("Self-refresh is enabled\n");
2870 pineview_disable_cxsr(dev
);
2871 DRM_DEBUG_KMS("Self-refresh is disabled\n");
2875 static void g4x_update_wm(struct drm_device
*dev
, int planea_clock
,
2876 int planeb_clock
, int sr_hdisplay
, int pixel_size
)
2878 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2879 int total_size
, cacheline_size
;
2880 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
, cursor_sr
;
2881 struct intel_watermark_params planea_params
, planeb_params
;
2882 unsigned long line_time_us
;
2883 int sr_clock
, sr_entries
= 0, entries_required
;
2885 /* Create copies of the base settings for each pipe */
2886 planea_params
= planeb_params
= g4x_wm_info
;
2888 /* Grab a couple of global values before we overwrite them */
2889 total_size
= planea_params
.fifo_size
;
2890 cacheline_size
= planea_params
.cacheline_size
;
2893 * Note: we need to make sure we don't overflow for various clock &
2895 * clocks go from a few thousand to several hundred thousand.
2896 * latency is usually a few thousand
2898 entries_required
= ((planea_clock
/ 1000) * pixel_size
* latency_ns
) /
2900 entries_required
/= G4X_FIFO_LINE_SIZE
;
2901 planea_wm
= entries_required
+ planea_params
.guard_size
;
2903 entries_required
= ((planeb_clock
/ 1000) * pixel_size
* latency_ns
) /
2905 entries_required
/= G4X_FIFO_LINE_SIZE
;
2906 planeb_wm
= entries_required
+ planeb_params
.guard_size
;
2908 cursora_wm
= cursorb_wm
= 16;
2911 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
2913 /* Calc sr entries for one plane configs */
2914 if (sr_hdisplay
&& (!planea_clock
|| !planeb_clock
)) {
2915 /* self-refresh has much higher latency */
2916 static const int sr_latency_ns
= 12000;
2918 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
2919 line_time_us
= ((sr_hdisplay
* 1000) / sr_clock
);
2921 /* Use ns/us then divide to preserve precision */
2922 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1) *
2923 pixel_size
* sr_hdisplay
) / 1000;
2924 sr_entries
= roundup(sr_entries
/ cacheline_size
, 1);
2925 DRM_DEBUG("self-refresh entries: %d\n", sr_entries
);
2926 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
2928 /* Turn off self refresh if both pipes are enabled */
2929 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
2933 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2934 planea_wm
, planeb_wm
, sr_entries
);
2939 I915_WRITE(DSPFW1
, (sr_entries
<< DSPFW_SR_SHIFT
) |
2940 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
2941 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) | planea_wm
);
2942 I915_WRITE(DSPFW2
, (I915_READ(DSPFW2
) & DSPFW_CURSORA_MASK
) |
2943 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
2944 /* HPLL off in SR has some issues on G4x... disable it */
2945 I915_WRITE(DSPFW3
, (I915_READ(DSPFW3
) & ~DSPFW_HPLL_SR_EN
) |
2946 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
2949 static void i965_update_wm(struct drm_device
*dev
, int planea_clock
,
2950 int planeb_clock
, int sr_hdisplay
, int pixel_size
)
2952 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2953 unsigned long line_time_us
;
2954 int sr_clock
, sr_entries
, srwm
= 1;
2956 /* Calc sr entries for one plane configs */
2957 if (sr_hdisplay
&& (!planea_clock
|| !planeb_clock
)) {
2958 /* self-refresh has much higher latency */
2959 static const int sr_latency_ns
= 12000;
2961 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
2962 line_time_us
= ((sr_hdisplay
* 1000) / sr_clock
);
2964 /* Use ns/us then divide to preserve precision */
2965 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1) *
2966 pixel_size
* sr_hdisplay
) / 1000;
2967 sr_entries
= roundup(sr_entries
/ I915_FIFO_LINE_SIZE
, 1);
2968 DRM_DEBUG("self-refresh entries: %d\n", sr_entries
);
2969 srwm
= I945_FIFO_SIZE
- sr_entries
;
2973 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
2975 /* Turn off self refresh if both pipes are enabled */
2976 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
2980 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2983 /* 965 has limitations... */
2984 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) | (8 << 16) | (8 << 8) |
2986 I915_WRITE(DSPFW2
, (8 << 8) | (8 << 0));
2989 static void i9xx_update_wm(struct drm_device
*dev
, int planea_clock
,
2990 int planeb_clock
, int sr_hdisplay
, int pixel_size
)
2992 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2995 int total_size
, cacheline_size
, cwm
, srwm
= 1;
2996 int planea_wm
, planeb_wm
;
2997 struct intel_watermark_params planea_params
, planeb_params
;
2998 unsigned long line_time_us
;
2999 int sr_clock
, sr_entries
= 0;
3001 /* Create copies of the base settings for each pipe */
3002 if (IS_I965GM(dev
) || IS_I945GM(dev
))
3003 planea_params
= planeb_params
= i945_wm_info
;
3004 else if (IS_I9XX(dev
))
3005 planea_params
= planeb_params
= i915_wm_info
;
3007 planea_params
= planeb_params
= i855_wm_info
;
3009 /* Grab a couple of global values before we overwrite them */
3010 total_size
= planea_params
.fifo_size
;
3011 cacheline_size
= planea_params
.cacheline_size
;
3013 /* Update per-plane FIFO sizes */
3014 planea_params
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
3015 planeb_params
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
3017 planea_wm
= intel_calculate_wm(planea_clock
, &planea_params
,
3018 pixel_size
, latency_ns
);
3019 planeb_wm
= intel_calculate_wm(planeb_clock
, &planeb_params
,
3020 pixel_size
, latency_ns
);
3021 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
3024 * Overlay gets an aggressive default since video jitter is bad.
3028 /* Calc sr entries for one plane configs */
3029 if (HAS_FW_BLC(dev
) && sr_hdisplay
&&
3030 (!planea_clock
|| !planeb_clock
)) {
3031 /* self-refresh has much higher latency */
3032 static const int sr_latency_ns
= 6000;
3034 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3035 line_time_us
= ((sr_hdisplay
* 1000) / sr_clock
);
3037 /* Use ns/us then divide to preserve precision */
3038 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1) *
3039 pixel_size
* sr_hdisplay
) / 1000;
3040 sr_entries
= roundup(sr_entries
/ cacheline_size
, 1);
3041 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries
);
3042 srwm
= total_size
- sr_entries
;
3046 if (IS_I945G(dev
) || IS_I945GM(dev
))
3047 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
3048 else if (IS_I915GM(dev
)) {
3049 /* 915M has a smaller SRWM field */
3050 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
3051 I915_WRITE(INSTPM
, I915_READ(INSTPM
) | INSTPM_SELF_EN
);
3054 /* Turn off self refresh if both pipes are enabled */
3055 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
3056 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
3058 } else if (IS_I915GM(dev
)) {
3059 I915_WRITE(INSTPM
, I915_READ(INSTPM
) & ~INSTPM_SELF_EN
);
3063 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3064 planea_wm
, planeb_wm
, cwm
, srwm
);
3066 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
3067 fwater_hi
= (cwm
& 0x1f);
3069 /* Set request length to 8 cachelines per fetch */
3070 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
3071 fwater_hi
= fwater_hi
| (1 << 8);
3073 I915_WRITE(FW_BLC
, fwater_lo
);
3074 I915_WRITE(FW_BLC2
, fwater_hi
);
3077 static void i830_update_wm(struct drm_device
*dev
, int planea_clock
, int unused
,
3078 int unused2
, int pixel_size
)
3080 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3081 uint32_t fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
3084 i830_wm_info
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
3086 planea_wm
= intel_calculate_wm(planea_clock
, &i830_wm_info
,
3087 pixel_size
, latency_ns
);
3088 fwater_lo
|= (3<<8) | planea_wm
;
3090 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
3092 I915_WRITE(FW_BLC
, fwater_lo
);
3095 #define ILK_LP0_PLANE_LATENCY 700
3097 static void ironlake_update_wm(struct drm_device
*dev
, int planea_clock
,
3098 int planeb_clock
, int sr_hdisplay
, int pixel_size
)
3100 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3101 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
3102 int sr_wm
, cursor_wm
;
3103 unsigned long line_time_us
;
3104 int sr_clock
, entries_required
;
3107 /* Calculate and update the watermark for plane A */
3109 entries_required
= ((planea_clock
/ 1000) * pixel_size
*
3110 ILK_LP0_PLANE_LATENCY
) / 1000;
3111 entries_required
= DIV_ROUND_UP(entries_required
,
3112 ironlake_display_wm_info
.cacheline_size
);
3113 planea_wm
= entries_required
+
3114 ironlake_display_wm_info
.guard_size
;
3116 if (planea_wm
> (int)ironlake_display_wm_info
.max_wm
)
3117 planea_wm
= ironlake_display_wm_info
.max_wm
;
3120 reg_value
= I915_READ(WM0_PIPEA_ILK
);
3121 reg_value
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
3122 reg_value
|= (planea_wm
<< WM0_PIPE_PLANE_SHIFT
) |
3123 (cursora_wm
& WM0_PIPE_CURSOR_MASK
);
3124 I915_WRITE(WM0_PIPEA_ILK
, reg_value
);
3125 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3126 "cursor: %d\n", planea_wm
, cursora_wm
);
3128 /* Calculate and update the watermark for plane B */
3130 entries_required
= ((planeb_clock
/ 1000) * pixel_size
*
3131 ILK_LP0_PLANE_LATENCY
) / 1000;
3132 entries_required
= DIV_ROUND_UP(entries_required
,
3133 ironlake_display_wm_info
.cacheline_size
);
3134 planeb_wm
= entries_required
+
3135 ironlake_display_wm_info
.guard_size
;
3137 if (planeb_wm
> (int)ironlake_display_wm_info
.max_wm
)
3138 planeb_wm
= ironlake_display_wm_info
.max_wm
;
3141 reg_value
= I915_READ(WM0_PIPEB_ILK
);
3142 reg_value
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
3143 reg_value
|= (planeb_wm
<< WM0_PIPE_PLANE_SHIFT
) |
3144 (cursorb_wm
& WM0_PIPE_CURSOR_MASK
);
3145 I915_WRITE(WM0_PIPEB_ILK
, reg_value
);
3146 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3147 "cursor: %d\n", planeb_wm
, cursorb_wm
);
3151 * Calculate and update the self-refresh watermark only when one
3152 * display plane is used.
3154 if (!planea_clock
|| !planeb_clock
) {
3156 /* Read the self-refresh latency. The unit is 0.5us */
3157 int ilk_sr_latency
= I915_READ(MLTR_ILK
) & ILK_SRLT_MASK
;
3159 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3160 line_time_us
= ((sr_hdisplay
* 1000) / sr_clock
);
3162 /* Use ns/us then divide to preserve precision */
3163 line_count
= ((ilk_sr_latency
* 500) / line_time_us
+ 1000)
3166 /* calculate the self-refresh watermark for display plane */
3167 entries_required
= line_count
* sr_hdisplay
* pixel_size
;
3168 entries_required
= DIV_ROUND_UP(entries_required
,
3169 ironlake_display_srwm_info
.cacheline_size
);
3170 sr_wm
= entries_required
+
3171 ironlake_display_srwm_info
.guard_size
;
3173 /* calculate the self-refresh watermark for display cursor */
3174 entries_required
= line_count
* pixel_size
* 64;
3175 entries_required
= DIV_ROUND_UP(entries_required
,
3176 ironlake_cursor_srwm_info
.cacheline_size
);
3177 cursor_wm
= entries_required
+
3178 ironlake_cursor_srwm_info
.guard_size
;
3180 /* configure watermark and enable self-refresh */
3181 reg_value
= I915_READ(WM1_LP_ILK
);
3182 reg_value
&= ~(WM1_LP_LATENCY_MASK
| WM1_LP_SR_MASK
|
3183 WM1_LP_CURSOR_MASK
);
3184 reg_value
|= WM1_LP_SR_EN
|
3185 (ilk_sr_latency
<< WM1_LP_LATENCY_SHIFT
) |
3186 (sr_wm
<< WM1_LP_SR_SHIFT
) | cursor_wm
;
3188 I915_WRITE(WM1_LP_ILK
, reg_value
);
3189 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3190 "cursor %d\n", sr_wm
, cursor_wm
);
3193 /* Turn off self refresh if both pipes are enabled */
3194 I915_WRITE(WM1_LP_ILK
, I915_READ(WM1_LP_ILK
) & ~WM1_LP_SR_EN
);
3198 * intel_update_watermarks - update FIFO watermark values based on current modes
3200 * Calculate watermark values for the various WM regs based on current mode
3201 * and plane configuration.
3203 * There are several cases to deal with here:
3204 * - normal (i.e. non-self-refresh)
3205 * - self-refresh (SR) mode
3206 * - lines are large relative to FIFO size (buffer can hold up to 2)
3207 * - lines are small relative to FIFO size (buffer can hold more than 2
3208 * lines), so need to account for TLB latency
3210 * The normal calculation is:
3211 * watermark = dotclock * bytes per pixel * latency
3212 * where latency is platform & configuration dependent (we assume pessimal
3215 * The SR calculation is:
3216 * watermark = (trunc(latency/line time)+1) * surface width *
3219 * line time = htotal / dotclock
3220 * and latency is assumed to be high, as above.
3222 * The final value programmed to the register should always be rounded up,
3223 * and include an extra 2 entries to account for clock crossings.
3225 * We don't use the sprite, so we can ignore that. And on Crestline we have
3226 * to set the non-SR watermarks to 8.
3228 static void intel_update_watermarks(struct drm_device
*dev
)
3230 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3231 struct drm_crtc
*crtc
;
3232 struct intel_crtc
*intel_crtc
;
3233 int sr_hdisplay
= 0;
3234 unsigned long planea_clock
= 0, planeb_clock
= 0, sr_clock
= 0;
3235 int enabled
= 0, pixel_size
= 0;
3237 if (!dev_priv
->display
.update_wm
)
3240 /* Get the clock config from both planes */
3241 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3242 intel_crtc
= to_intel_crtc(crtc
);
3243 if (crtc
->enabled
) {
3245 if (intel_crtc
->plane
== 0) {
3246 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3247 intel_crtc
->pipe
, crtc
->mode
.clock
);
3248 planea_clock
= crtc
->mode
.clock
;
3250 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3251 intel_crtc
->pipe
, crtc
->mode
.clock
);
3252 planeb_clock
= crtc
->mode
.clock
;
3254 sr_hdisplay
= crtc
->mode
.hdisplay
;
3255 sr_clock
= crtc
->mode
.clock
;
3257 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
3259 pixel_size
= 4; /* by default */
3266 dev_priv
->display
.update_wm(dev
, planea_clock
, planeb_clock
,
3267 sr_hdisplay
, pixel_size
);
3270 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
3271 struct drm_display_mode
*mode
,
3272 struct drm_display_mode
*adjusted_mode
,
3274 struct drm_framebuffer
*old_fb
)
3276 struct drm_device
*dev
= crtc
->dev
;
3277 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3278 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3279 int pipe
= intel_crtc
->pipe
;
3280 int plane
= intel_crtc
->plane
;
3281 int fp_reg
= (pipe
== 0) ? FPA0
: FPB0
;
3282 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
3283 int dpll_md_reg
= (intel_crtc
->pipe
== 0) ? DPLL_A_MD
: DPLL_B_MD
;
3284 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
3285 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
3286 int htot_reg
= (pipe
== 0) ? HTOTAL_A
: HTOTAL_B
;
3287 int hblank_reg
= (pipe
== 0) ? HBLANK_A
: HBLANK_B
;
3288 int hsync_reg
= (pipe
== 0) ? HSYNC_A
: HSYNC_B
;
3289 int vtot_reg
= (pipe
== 0) ? VTOTAL_A
: VTOTAL_B
;
3290 int vblank_reg
= (pipe
== 0) ? VBLANK_A
: VBLANK_B
;
3291 int vsync_reg
= (pipe
== 0) ? VSYNC_A
: VSYNC_B
;
3292 int dspsize_reg
= (plane
== 0) ? DSPASIZE
: DSPBSIZE
;
3293 int dsppos_reg
= (plane
== 0) ? DSPAPOS
: DSPBPOS
;
3294 int pipesrc_reg
= (pipe
== 0) ? PIPEASRC
: PIPEBSRC
;
3295 int refclk
, num_connectors
= 0;
3296 intel_clock_t clock
, reduced_clock
;
3297 u32 dpll
= 0, fp
= 0, fp2
= 0, dspcntr
, pipeconf
;
3298 bool ok
, has_reduced_clock
= false, is_sdvo
= false, is_dvo
= false;
3299 bool is_crt
= false, is_lvds
= false, is_tv
= false, is_dp
= false;
3300 bool is_edp
= false;
3301 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3302 struct drm_encoder
*encoder
;
3303 struct intel_encoder
*intel_encoder
= NULL
;
3304 const intel_limit_t
*limit
;
3306 struct fdi_m_n m_n
= {0};
3307 int data_m1_reg
= (pipe
== 0) ? PIPEA_DATA_M1
: PIPEB_DATA_M1
;
3308 int data_n1_reg
= (pipe
== 0) ? PIPEA_DATA_N1
: PIPEB_DATA_N1
;
3309 int link_m1_reg
= (pipe
== 0) ? PIPEA_LINK_M1
: PIPEB_LINK_M1
;
3310 int link_n1_reg
= (pipe
== 0) ? PIPEA_LINK_N1
: PIPEB_LINK_N1
;
3311 int pch_fp_reg
= (pipe
== 0) ? PCH_FPA0
: PCH_FPB0
;
3312 int pch_dpll_reg
= (pipe
== 0) ? PCH_DPLL_A
: PCH_DPLL_B
;
3313 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
3314 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
3315 int trans_dpll_sel
= (pipe
== 0) ? 0 : 1;
3316 int lvds_reg
= LVDS
;
3318 int sdvo_pixel_multiply
;
3321 drm_vblank_pre_modeset(dev
, pipe
);
3323 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
3325 if (!encoder
|| encoder
->crtc
!= crtc
)
3328 intel_encoder
= enc_to_intel_encoder(encoder
);
3330 switch (intel_encoder
->type
) {
3331 case INTEL_OUTPUT_LVDS
:
3334 case INTEL_OUTPUT_SDVO
:
3335 case INTEL_OUTPUT_HDMI
:
3337 if (intel_encoder
->needs_tv_clock
)
3340 case INTEL_OUTPUT_DVO
:
3343 case INTEL_OUTPUT_TVOUT
:
3346 case INTEL_OUTPUT_ANALOG
:
3349 case INTEL_OUTPUT_DISPLAYPORT
:
3352 case INTEL_OUTPUT_EDP
:
3360 if (is_lvds
&& dev_priv
->lvds_use_ssc
&& num_connectors
< 2) {
3361 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
3362 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3364 } else if (IS_I9XX(dev
)) {
3366 if (HAS_PCH_SPLIT(dev
))
3367 refclk
= 120000; /* 120Mhz refclk */
3374 * Returns a set of divisors for the desired target clock with the given
3375 * refclk, or FALSE. The returned values represent the clock equation:
3376 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3378 limit
= intel_limit(crtc
);
3379 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, &clock
);
3381 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3382 drm_vblank_post_modeset(dev
, pipe
);
3386 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
3387 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
3388 dev_priv
->lvds_downclock
,
3391 if (has_reduced_clock
&& (clock
.p
!= reduced_clock
.p
)) {
3393 * If the different P is found, it means that we can't
3394 * switch the display clock by using the FP0/FP1.
3395 * In such case we will disable the LVDS downclock
3398 DRM_DEBUG_KMS("Different P is found for "
3399 "LVDS clock/downclock\n");
3400 has_reduced_clock
= 0;
3403 /* SDVO TV has fixed PLL values depend on its clock range,
3404 this mirrors vbios setting. */
3405 if (is_sdvo
&& is_tv
) {
3406 if (adjusted_mode
->clock
>= 100000
3407 && adjusted_mode
->clock
< 140500) {
3413 } else if (adjusted_mode
->clock
>= 140500
3414 && adjusted_mode
->clock
<= 200000) {
3424 if (HAS_PCH_SPLIT(dev
)) {
3425 int lane
= 0, link_bw
, bpp
;
3426 /* eDP doesn't require FDI link, so just set DP M/N
3427 according to current link config */
3429 target_clock
= mode
->clock
;
3430 intel_edp_link_config(intel_encoder
,
3433 /* DP over FDI requires target mode clock
3434 instead of link clock */
3436 target_clock
= mode
->clock
;
3438 target_clock
= adjusted_mode
->clock
;
3442 /* determine panel color depth */
3443 temp
= I915_READ(pipeconf_reg
);
3444 temp
&= ~PIPE_BPC_MASK
;
3446 int lvds_reg
= I915_READ(PCH_LVDS
);
3447 /* the BPC will be 6 if it is 18-bit LVDS panel */
3448 if ((lvds_reg
& LVDS_A3_POWER_MASK
) == LVDS_A3_POWER_UP
)
3452 } else if (is_edp
) {
3453 switch (dev_priv
->edp_bpp
/3) {
3469 I915_WRITE(pipeconf_reg
, temp
);
3470 I915_READ(pipeconf_reg
);
3472 switch (temp
& PIPE_BPC_MASK
) {
3486 DRM_ERROR("unknown pipe bpc value\n");
3492 * Account for spread spectrum to avoid
3493 * oversubscribing the link. Max center spread
3494 * is 2.5%; use 5% for safety's sake.
3496 u32 bps
= target_clock
* bpp
* 21 / 20;
3497 lane
= bps
/ (link_bw
* 8) + 1;
3500 intel_crtc
->fdi_lanes
= lane
;
3502 ironlake_compute_m_n(bpp
, lane
, target_clock
, link_bw
, &m_n
);
3505 /* Ironlake: try to setup display ref clock before DPLL
3506 * enabling. This is only under driver's control after
3507 * PCH B stepping, previous chipset stepping should be
3508 * ignoring this setting.
3510 if (HAS_PCH_SPLIT(dev
)) {
3511 temp
= I915_READ(PCH_DREF_CONTROL
);
3512 /* Always enable nonspread source */
3513 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
3514 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
3515 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3516 POSTING_READ(PCH_DREF_CONTROL
);
3518 temp
&= ~DREF_SSC_SOURCE_MASK
;
3519 temp
|= DREF_SSC_SOURCE_ENABLE
;
3520 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3521 POSTING_READ(PCH_DREF_CONTROL
);
3526 if (dev_priv
->lvds_use_ssc
) {
3527 temp
|= DREF_SSC1_ENABLE
;
3528 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3529 POSTING_READ(PCH_DREF_CONTROL
);
3533 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
3534 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
3535 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3536 POSTING_READ(PCH_DREF_CONTROL
);
3538 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
3539 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3540 POSTING_READ(PCH_DREF_CONTROL
);
3545 if (IS_PINEVIEW(dev
)) {
3546 fp
= (1 << clock
.n
) << 16 | clock
.m1
<< 8 | clock
.m2
;
3547 if (has_reduced_clock
)
3548 fp2
= (1 << reduced_clock
.n
) << 16 |
3549 reduced_clock
.m1
<< 8 | reduced_clock
.m2
;
3551 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
3552 if (has_reduced_clock
)
3553 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
3557 if (!HAS_PCH_SPLIT(dev
))
3558 dpll
= DPLL_VGA_MODE_DIS
;
3562 dpll
|= DPLLB_MODE_LVDS
;
3564 dpll
|= DPLLB_MODE_DAC_SERIAL
;
3566 dpll
|= DPLL_DVO_HIGH_SPEED
;
3567 sdvo_pixel_multiply
= adjusted_mode
->clock
/ mode
->clock
;
3568 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
3569 dpll
|= (sdvo_pixel_multiply
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
3570 else if (HAS_PCH_SPLIT(dev
))
3571 dpll
|= (sdvo_pixel_multiply
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
3574 dpll
|= DPLL_DVO_HIGH_SPEED
;
3576 /* compute bitmask from p1 value */
3577 if (IS_PINEVIEW(dev
))
3578 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
3580 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3582 if (HAS_PCH_SPLIT(dev
))
3583 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
3584 if (IS_G4X(dev
) && has_reduced_clock
)
3585 dpll
|= (1 << (reduced_clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
3589 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
3592 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
3595 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
3598 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
3601 if (IS_I965G(dev
) && !HAS_PCH_SPLIT(dev
))
3602 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
3605 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3608 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
3610 dpll
|= (clock
.p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3612 dpll
|= PLL_P2_DIVIDE_BY_4
;
3616 if (is_sdvo
&& is_tv
)
3617 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
3619 /* XXX: just matching BIOS for now */
3620 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3622 else if (is_lvds
&& dev_priv
->lvds_use_ssc
&& num_connectors
< 2)
3623 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
3625 dpll
|= PLL_REF_INPUT_DREFCLK
;
3627 /* setup pipeconf */
3628 pipeconf
= I915_READ(pipeconf_reg
);
3630 /* Set up the display plane register */
3631 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
3633 /* Ironlake's plane is forced to pipe, bit 24 is to
3634 enable color space conversion */
3635 if (!HAS_PCH_SPLIT(dev
)) {
3637 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
3639 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
3642 if (pipe
== 0 && !IS_I965G(dev
)) {
3643 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3646 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3650 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
3651 pipeconf
|= PIPEACONF_DOUBLE_WIDE
;
3653 pipeconf
&= ~PIPEACONF_DOUBLE_WIDE
;
3656 dspcntr
|= DISPLAY_PLANE_ENABLE
;
3657 pipeconf
|= PIPEACONF_ENABLE
;
3658 dpll
|= DPLL_VCO_ENABLE
;
3661 /* Disable the panel fitter if it was on our pipe */
3662 if (!HAS_PCH_SPLIT(dev
) && intel_panel_fitter_pipe(dev
) == pipe
)
3663 I915_WRITE(PFIT_CONTROL
, 0);
3665 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
3666 drm_mode_debug_printmodeline(mode
);
3668 /* assign to Ironlake registers */
3669 if (HAS_PCH_SPLIT(dev
)) {
3670 fp_reg
= pch_fp_reg
;
3671 dpll_reg
= pch_dpll_reg
;
3675 ironlake_disable_pll_edp(crtc
);
3676 } else if ((dpll
& DPLL_VCO_ENABLE
)) {
3677 I915_WRITE(fp_reg
, fp
);
3678 I915_WRITE(dpll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3679 I915_READ(dpll_reg
);
3683 /* enable transcoder DPLL */
3684 if (HAS_PCH_CPT(dev
)) {
3685 temp
= I915_READ(PCH_DPLL_SEL
);
3686 if (trans_dpll_sel
== 0)
3687 temp
|= (TRANSA_DPLL_ENABLE
| TRANSA_DPLLA_SEL
);
3689 temp
|= (TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
3690 I915_WRITE(PCH_DPLL_SEL
, temp
);
3691 I915_READ(PCH_DPLL_SEL
);
3695 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3696 * This is an exception to the general rule that mode_set doesn't turn
3702 if (HAS_PCH_SPLIT(dev
))
3703 lvds_reg
= PCH_LVDS
;
3705 lvds
= I915_READ(lvds_reg
);
3706 lvds
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
3708 if (HAS_PCH_CPT(dev
))
3709 lvds
|= PORT_TRANS_B_SEL_CPT
;
3711 lvds
|= LVDS_PIPEB_SELECT
;
3713 if (HAS_PCH_CPT(dev
))
3714 lvds
&= ~PORT_TRANS_SEL_MASK
;
3716 lvds
&= ~LVDS_PIPEB_SELECT
;
3718 /* set the corresponsding LVDS_BORDER bit */
3719 lvds
|= dev_priv
->lvds_border_bits
;
3720 /* Set the B0-B3 data pairs corresponding to whether we're going to
3721 * set the DPLLs for dual-channel mode or not.
3724 lvds
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
3726 lvds
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
3728 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3729 * appropriately here, but we need to look more thoroughly into how
3730 * panels behave in the two modes.
3732 /* set the dithering flag */
3733 if (IS_I965G(dev
)) {
3734 if (dev_priv
->lvds_dither
) {
3735 if (HAS_PCH_SPLIT(dev
)) {
3736 pipeconf
|= PIPE_ENABLE_DITHER
;
3737 pipeconf
|= PIPE_DITHER_TYPE_ST01
;
3739 lvds
|= LVDS_ENABLE_DITHER
;
3741 if (HAS_PCH_SPLIT(dev
)) {
3742 pipeconf
&= ~PIPE_ENABLE_DITHER
;
3743 pipeconf
&= ~PIPE_DITHER_TYPE_MASK
;
3745 lvds
&= ~LVDS_ENABLE_DITHER
;
3748 I915_WRITE(lvds_reg
, lvds
);
3749 I915_READ(lvds_reg
);
3752 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
3753 else if (HAS_PCH_SPLIT(dev
)) {
3754 /* For non-DP output, clear any trans DP clock recovery setting.*/
3756 I915_WRITE(TRANSA_DATA_M1
, 0);
3757 I915_WRITE(TRANSA_DATA_N1
, 0);
3758 I915_WRITE(TRANSA_DP_LINK_M1
, 0);
3759 I915_WRITE(TRANSA_DP_LINK_N1
, 0);
3761 I915_WRITE(TRANSB_DATA_M1
, 0);
3762 I915_WRITE(TRANSB_DATA_N1
, 0);
3763 I915_WRITE(TRANSB_DP_LINK_M1
, 0);
3764 I915_WRITE(TRANSB_DP_LINK_N1
, 0);
3769 I915_WRITE(fp_reg
, fp
);
3770 I915_WRITE(dpll_reg
, dpll
);
3771 I915_READ(dpll_reg
);
3772 /* Wait for the clocks to stabilize. */
3775 if (IS_I965G(dev
) && !HAS_PCH_SPLIT(dev
)) {
3777 sdvo_pixel_multiply
= adjusted_mode
->clock
/ mode
->clock
;
3778 I915_WRITE(dpll_md_reg
, (0 << DPLL_MD_UDI_DIVIDER_SHIFT
) |
3779 ((sdvo_pixel_multiply
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
));
3781 I915_WRITE(dpll_md_reg
, 0);
3783 /* write it again -- the BIOS does, after all */
3784 I915_WRITE(dpll_reg
, dpll
);
3786 I915_READ(dpll_reg
);
3787 /* Wait for the clocks to stabilize. */
3791 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
3792 I915_WRITE(fp_reg
+ 4, fp2
);
3793 intel_crtc
->lowfreq_avail
= true;
3794 if (HAS_PIPE_CXSR(dev
)) {
3795 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3796 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
3799 I915_WRITE(fp_reg
+ 4, fp
);
3800 intel_crtc
->lowfreq_avail
= false;
3801 if (HAS_PIPE_CXSR(dev
)) {
3802 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3803 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
3807 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
3808 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
3809 /* the chip adds 2 halflines automatically */
3810 adjusted_mode
->crtc_vdisplay
-= 1;
3811 adjusted_mode
->crtc_vtotal
-= 1;
3812 adjusted_mode
->crtc_vblank_start
-= 1;
3813 adjusted_mode
->crtc_vblank_end
-= 1;
3814 adjusted_mode
->crtc_vsync_end
-= 1;
3815 adjusted_mode
->crtc_vsync_start
-= 1;
3817 pipeconf
&= ~PIPECONF_INTERLACE_W_FIELD_INDICATION
; /* progressive */
3819 I915_WRITE(htot_reg
, (adjusted_mode
->crtc_hdisplay
- 1) |
3820 ((adjusted_mode
->crtc_htotal
- 1) << 16));
3821 I915_WRITE(hblank_reg
, (adjusted_mode
->crtc_hblank_start
- 1) |
3822 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
3823 I915_WRITE(hsync_reg
, (adjusted_mode
->crtc_hsync_start
- 1) |
3824 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
3825 I915_WRITE(vtot_reg
, (adjusted_mode
->crtc_vdisplay
- 1) |
3826 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
3827 I915_WRITE(vblank_reg
, (adjusted_mode
->crtc_vblank_start
- 1) |
3828 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
3829 I915_WRITE(vsync_reg
, (adjusted_mode
->crtc_vsync_start
- 1) |
3830 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
3831 /* pipesrc and dspsize control the size that is scaled from, which should
3832 * always be the user's requested size.
3834 if (!HAS_PCH_SPLIT(dev
)) {
3835 I915_WRITE(dspsize_reg
, ((mode
->vdisplay
- 1) << 16) |
3836 (mode
->hdisplay
- 1));
3837 I915_WRITE(dsppos_reg
, 0);
3839 I915_WRITE(pipesrc_reg
, ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
3841 if (HAS_PCH_SPLIT(dev
)) {
3842 I915_WRITE(data_m1_reg
, TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
3843 I915_WRITE(data_n1_reg
, TU_SIZE(m_n
.tu
) | m_n
.gmch_n
);
3844 I915_WRITE(link_m1_reg
, m_n
.link_m
);
3845 I915_WRITE(link_n1_reg
, m_n
.link_n
);
3848 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
3850 /* enable FDI RX PLL too */
3851 temp
= I915_READ(fdi_rx_reg
);
3852 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_PLL_ENABLE
);
3853 I915_READ(fdi_rx_reg
);
3856 /* enable FDI TX PLL too */
3857 temp
= I915_READ(fdi_tx_reg
);
3858 I915_WRITE(fdi_tx_reg
, temp
| FDI_TX_PLL_ENABLE
);
3859 I915_READ(fdi_tx_reg
);
3861 /* enable FDI RX PCDCLK */
3862 temp
= I915_READ(fdi_rx_reg
);
3863 I915_WRITE(fdi_rx_reg
, temp
| FDI_SEL_PCDCLK
);
3864 I915_READ(fdi_rx_reg
);
3869 I915_WRITE(pipeconf_reg
, pipeconf
);
3870 I915_READ(pipeconf_reg
);
3872 intel_wait_for_vblank(dev
);
3874 if (IS_IRONLAKE(dev
)) {
3875 /* enable address swizzle for tiling buffer */
3876 temp
= I915_READ(DISP_ARB_CTL
);
3877 I915_WRITE(DISP_ARB_CTL
, temp
| DISP_TILE_SURFACE_SWIZZLING
);
3880 I915_WRITE(dspcntr_reg
, dspcntr
);
3882 /* Flush the plane changes */
3883 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
3885 if ((IS_I965G(dev
) || plane
== 0))
3886 intel_update_fbc(crtc
, &crtc
->mode
);
3888 intel_update_watermarks(dev
);
3890 drm_vblank_post_modeset(dev
, pipe
);
3895 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3896 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
3898 struct drm_device
*dev
= crtc
->dev
;
3899 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3900 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3901 int palreg
= (intel_crtc
->pipe
== 0) ? PALETTE_A
: PALETTE_B
;
3904 /* The clocks have to be on to load the palette. */
3908 /* use legacy palette for Ironlake */
3909 if (HAS_PCH_SPLIT(dev
))
3910 palreg
= (intel_crtc
->pipe
== 0) ? LGC_PALETTE_A
:
3913 for (i
= 0; i
< 256; i
++) {
3914 I915_WRITE(palreg
+ 4 * i
,
3915 (intel_crtc
->lut_r
[i
] << 16) |
3916 (intel_crtc
->lut_g
[i
] << 8) |
3917 intel_crtc
->lut_b
[i
]);
3921 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
3922 struct drm_file
*file_priv
,
3924 uint32_t width
, uint32_t height
)
3926 struct drm_device
*dev
= crtc
->dev
;
3927 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3928 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3929 struct drm_gem_object
*bo
;
3930 struct drm_i915_gem_object
*obj_priv
;
3931 int pipe
= intel_crtc
->pipe
;
3932 uint32_t control
= (pipe
== 0) ? CURACNTR
: CURBCNTR
;
3933 uint32_t base
= (pipe
== 0) ? CURABASE
: CURBBASE
;
3934 uint32_t temp
= I915_READ(control
);
3938 DRM_DEBUG_KMS("\n");
3940 /* if we want to turn off the cursor ignore width and height */
3942 DRM_DEBUG_KMS("cursor off\n");
3943 if (IS_MOBILE(dev
) || IS_I9XX(dev
)) {
3944 temp
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
3945 temp
|= CURSOR_MODE_DISABLE
;
3947 temp
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
3951 mutex_lock(&dev
->struct_mutex
);
3955 /* Currently we only support 64x64 cursors */
3956 if (width
!= 64 || height
!= 64) {
3957 DRM_ERROR("we currently only support 64x64 cursors\n");
3961 bo
= drm_gem_object_lookup(dev
, file_priv
, handle
);
3965 obj_priv
= to_intel_bo(bo
);
3967 if (bo
->size
< width
* height
* 4) {
3968 DRM_ERROR("buffer is to small\n");
3973 /* we only need to pin inside GTT if cursor is non-phy */
3974 mutex_lock(&dev
->struct_mutex
);
3975 if (!dev_priv
->info
->cursor_needs_physical
) {
3976 ret
= i915_gem_object_pin(bo
, PAGE_SIZE
);
3978 DRM_ERROR("failed to pin cursor bo\n");
3982 ret
= i915_gem_object_set_to_gtt_domain(bo
, 0);
3984 DRM_ERROR("failed to move cursor bo into the GTT\n");
3988 addr
= obj_priv
->gtt_offset
;
3990 ret
= i915_gem_attach_phys_object(dev
, bo
, (pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
);
3992 DRM_ERROR("failed to attach phys object\n");
3995 addr
= obj_priv
->phys_obj
->handle
->busaddr
;
3999 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
4001 /* Hooray for CUR*CNTR differences */
4002 if (IS_MOBILE(dev
) || IS_I9XX(dev
)) {
4003 temp
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
4004 temp
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
4005 temp
|= (pipe
<< 28); /* Connect to correct pipe */
4007 temp
&= ~(CURSOR_FORMAT_MASK
);
4008 temp
|= CURSOR_ENABLE
;
4009 temp
|= CURSOR_FORMAT_ARGB
| CURSOR_GAMMA_ENABLE
;
4013 I915_WRITE(control
, temp
);
4014 I915_WRITE(base
, addr
);
4016 if (intel_crtc
->cursor_bo
) {
4017 if (dev_priv
->info
->cursor_needs_physical
) {
4018 if (intel_crtc
->cursor_bo
!= bo
)
4019 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
4021 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
4022 drm_gem_object_unreference(intel_crtc
->cursor_bo
);
4025 mutex_unlock(&dev
->struct_mutex
);
4027 intel_crtc
->cursor_addr
= addr
;
4028 intel_crtc
->cursor_bo
= bo
;
4032 i915_gem_object_unpin(bo
);
4034 mutex_unlock(&dev
->struct_mutex
);
4036 drm_gem_object_unreference_unlocked(bo
);
4040 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
4042 struct drm_device
*dev
= crtc
->dev
;
4043 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4044 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4045 struct intel_framebuffer
*intel_fb
;
4046 int pipe
= intel_crtc
->pipe
;
4051 intel_fb
= to_intel_framebuffer(crtc
->fb
);
4052 intel_mark_busy(dev
, intel_fb
->obj
);
4056 temp
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
4060 temp
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
4064 temp
|= x
<< CURSOR_X_SHIFT
;
4065 temp
|= y
<< CURSOR_Y_SHIFT
;
4067 adder
= intel_crtc
->cursor_addr
;
4068 I915_WRITE((pipe
== 0) ? CURAPOS
: CURBPOS
, temp
);
4069 I915_WRITE((pipe
== 0) ? CURABASE
: CURBBASE
, adder
);
4074 /** Sets the color ramps on behalf of RandR */
4075 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
4076 u16 blue
, int regno
)
4078 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4080 intel_crtc
->lut_r
[regno
] = red
>> 8;
4081 intel_crtc
->lut_g
[regno
] = green
>> 8;
4082 intel_crtc
->lut_b
[regno
] = blue
>> 8;
4085 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
4086 u16
*blue
, int regno
)
4088 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4090 *red
= intel_crtc
->lut_r
[regno
] << 8;
4091 *green
= intel_crtc
->lut_g
[regno
] << 8;
4092 *blue
= intel_crtc
->lut_b
[regno
] << 8;
4095 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
4096 u16
*blue
, uint32_t size
)
4098 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4104 for (i
= 0; i
< 256; i
++) {
4105 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
4106 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
4107 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
4110 intel_crtc_load_lut(crtc
);
4114 * Get a pipe with a simple mode set on it for doing load-based monitor
4117 * It will be up to the load-detect code to adjust the pipe as appropriate for
4118 * its requirements. The pipe will be connected to no other encoders.
4120 * Currently this code will only succeed if there is a pipe with no encoders
4121 * configured for it. In the future, it could choose to temporarily disable
4122 * some outputs to free up a pipe for its use.
4124 * \return crtc, or NULL if no pipes are available.
4127 /* VESA 640x480x72Hz mode to set on the pipe */
4128 static struct drm_display_mode load_detect_mode
= {
4129 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
4130 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
4133 struct drm_crtc
*intel_get_load_detect_pipe(struct intel_encoder
*intel_encoder
,
4134 struct drm_connector
*connector
,
4135 struct drm_display_mode
*mode
,
4138 struct intel_crtc
*intel_crtc
;
4139 struct drm_crtc
*possible_crtc
;
4140 struct drm_crtc
*supported_crtc
=NULL
;
4141 struct drm_encoder
*encoder
= &intel_encoder
->enc
;
4142 struct drm_crtc
*crtc
= NULL
;
4143 struct drm_device
*dev
= encoder
->dev
;
4144 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
4145 struct drm_crtc_helper_funcs
*crtc_funcs
;
4149 * Algorithm gets a little messy:
4150 * - if the connector already has an assigned crtc, use it (but make
4151 * sure it's on first)
4152 * - try to find the first unused crtc that can drive this connector,
4153 * and use that if we find one
4154 * - if there are no unused crtcs available, try to use the first
4155 * one we found that supports the connector
4158 /* See if we already have a CRTC for this connector */
4159 if (encoder
->crtc
) {
4160 crtc
= encoder
->crtc
;
4161 /* Make sure the crtc and connector are running */
4162 intel_crtc
= to_intel_crtc(crtc
);
4163 *dpms_mode
= intel_crtc
->dpms_mode
;
4164 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
4165 crtc_funcs
= crtc
->helper_private
;
4166 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
4167 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
4172 /* Find an unused one (if possible) */
4173 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
4175 if (!(encoder
->possible_crtcs
& (1 << i
)))
4177 if (!possible_crtc
->enabled
) {
4178 crtc
= possible_crtc
;
4181 if (!supported_crtc
)
4182 supported_crtc
= possible_crtc
;
4186 * If we didn't find an unused CRTC, don't use any.
4192 encoder
->crtc
= crtc
;
4193 connector
->encoder
= encoder
;
4194 intel_encoder
->load_detect_temp
= true;
4196 intel_crtc
= to_intel_crtc(crtc
);
4197 *dpms_mode
= intel_crtc
->dpms_mode
;
4199 if (!crtc
->enabled
) {
4201 mode
= &load_detect_mode
;
4202 drm_crtc_helper_set_mode(crtc
, mode
, 0, 0, crtc
->fb
);
4204 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
4205 crtc_funcs
= crtc
->helper_private
;
4206 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
4209 /* Add this connector to the crtc */
4210 encoder_funcs
->mode_set(encoder
, &crtc
->mode
, &crtc
->mode
);
4211 encoder_funcs
->commit(encoder
);
4213 /* let the connector get through one full cycle before testing */
4214 intel_wait_for_vblank(dev
);
4219 void intel_release_load_detect_pipe(struct intel_encoder
*intel_encoder
,
4220 struct drm_connector
*connector
, int dpms_mode
)
4222 struct drm_encoder
*encoder
= &intel_encoder
->enc
;
4223 struct drm_device
*dev
= encoder
->dev
;
4224 struct drm_crtc
*crtc
= encoder
->crtc
;
4225 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
4226 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
4228 if (intel_encoder
->load_detect_temp
) {
4229 encoder
->crtc
= NULL
;
4230 connector
->encoder
= NULL
;
4231 intel_encoder
->load_detect_temp
= false;
4232 crtc
->enabled
= drm_helper_crtc_in_use(crtc
);
4233 drm_helper_disable_unused_functions(dev
);
4236 /* Switch crtc and encoder back off if necessary */
4237 if (crtc
->enabled
&& dpms_mode
!= DRM_MODE_DPMS_ON
) {
4238 if (encoder
->crtc
== crtc
)
4239 encoder_funcs
->dpms(encoder
, dpms_mode
);
4240 crtc_funcs
->dpms(crtc
, dpms_mode
);
4244 /* Returns the clock of the currently programmed mode of the given pipe. */
4245 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
4247 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4248 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4249 int pipe
= intel_crtc
->pipe
;
4250 u32 dpll
= I915_READ((pipe
== 0) ? DPLL_A
: DPLL_B
);
4252 intel_clock_t clock
;
4254 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
4255 fp
= I915_READ((pipe
== 0) ? FPA0
: FPB0
);
4257 fp
= I915_READ((pipe
== 0) ? FPA1
: FPB1
);
4259 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
4260 if (IS_PINEVIEW(dev
)) {
4261 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
4262 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
4264 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
4265 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
4269 if (IS_PINEVIEW(dev
))
4270 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
4271 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
4273 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
4274 DPLL_FPA01_P1_POST_DIV_SHIFT
);
4276 switch (dpll
& DPLL_MODE_MASK
) {
4277 case DPLLB_MODE_DAC_SERIAL
:
4278 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
4281 case DPLLB_MODE_LVDS
:
4282 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
4286 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4287 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
4291 /* XXX: Handle the 100Mhz refclk */
4292 intel_clock(dev
, 96000, &clock
);
4294 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
4297 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
4298 DPLL_FPA01_P1_POST_DIV_SHIFT
);
4301 if ((dpll
& PLL_REF_INPUT_MASK
) ==
4302 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
4303 /* XXX: might not be 66MHz */
4304 intel_clock(dev
, 66000, &clock
);
4306 intel_clock(dev
, 48000, &clock
);
4308 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
4311 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
4312 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
4314 if (dpll
& PLL_P2_DIVIDE_BY_4
)
4319 intel_clock(dev
, 48000, &clock
);
4323 /* XXX: It would be nice to validate the clocks, but we can't reuse
4324 * i830PllIsValid() because it relies on the xf86_config connector
4325 * configuration being accurate, which it isn't necessarily.
4331 /** Returns the currently programmed mode of the given pipe. */
4332 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
4333 struct drm_crtc
*crtc
)
4335 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4336 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4337 int pipe
= intel_crtc
->pipe
;
4338 struct drm_display_mode
*mode
;
4339 int htot
= I915_READ((pipe
== 0) ? HTOTAL_A
: HTOTAL_B
);
4340 int hsync
= I915_READ((pipe
== 0) ? HSYNC_A
: HSYNC_B
);
4341 int vtot
= I915_READ((pipe
== 0) ? VTOTAL_A
: VTOTAL_B
);
4342 int vsync
= I915_READ((pipe
== 0) ? VSYNC_A
: VSYNC_B
);
4344 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
4348 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
4349 mode
->hdisplay
= (htot
& 0xffff) + 1;
4350 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
4351 mode
->hsync_start
= (hsync
& 0xffff) + 1;
4352 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
4353 mode
->vdisplay
= (vtot
& 0xffff) + 1;
4354 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
4355 mode
->vsync_start
= (vsync
& 0xffff) + 1;
4356 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
4358 drm_mode_set_name(mode
);
4359 drm_mode_set_crtcinfo(mode
, 0);
4364 #define GPU_IDLE_TIMEOUT 500 /* ms */
4366 /* When this timer fires, we've been idle for awhile */
4367 static void intel_gpu_idle_timer(unsigned long arg
)
4369 struct drm_device
*dev
= (struct drm_device
*)arg
;
4370 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4372 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4374 dev_priv
->busy
= false;
4376 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
4379 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4381 static void intel_crtc_idle_timer(unsigned long arg
)
4383 struct intel_crtc
*intel_crtc
= (struct intel_crtc
*)arg
;
4384 struct drm_crtc
*crtc
= &intel_crtc
->base
;
4385 drm_i915_private_t
*dev_priv
= crtc
->dev
->dev_private
;
4387 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4389 intel_crtc
->busy
= false;
4391 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
4394 static void intel_increase_pllclock(struct drm_crtc
*crtc
, bool schedule
)
4396 struct drm_device
*dev
= crtc
->dev
;
4397 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4398 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4399 int pipe
= intel_crtc
->pipe
;
4400 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
4401 int dpll
= I915_READ(dpll_reg
);
4403 if (HAS_PCH_SPLIT(dev
))
4406 if (!dev_priv
->lvds_downclock_avail
)
4409 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
4410 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4412 /* Unlock panel regs */
4413 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) | (0xabcd << 16));
4415 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
4416 I915_WRITE(dpll_reg
, dpll
);
4417 dpll
= I915_READ(dpll_reg
);
4418 intel_wait_for_vblank(dev
);
4419 dpll
= I915_READ(dpll_reg
);
4420 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
4421 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4423 /* ...and lock them again */
4424 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) & 0x3);
4427 /* Schedule downclock */
4429 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
4430 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
4433 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
4435 struct drm_device
*dev
= crtc
->dev
;
4436 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4437 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4438 int pipe
= intel_crtc
->pipe
;
4439 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
4440 int dpll
= I915_READ(dpll_reg
);
4442 if (HAS_PCH_SPLIT(dev
))
4445 if (!dev_priv
->lvds_downclock_avail
)
4449 * Since this is called by a timer, we should never get here in
4452 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
4453 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4455 /* Unlock panel regs */
4456 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) | (0xabcd << 16));
4458 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
4459 I915_WRITE(dpll_reg
, dpll
);
4460 dpll
= I915_READ(dpll_reg
);
4461 intel_wait_for_vblank(dev
);
4462 dpll
= I915_READ(dpll_reg
);
4463 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
4464 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4466 /* ...and lock them again */
4467 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) & 0x3);
4473 * intel_idle_update - adjust clocks for idleness
4474 * @work: work struct
4476 * Either the GPU or display (or both) went idle. Check the busy status
4477 * here and adjust the CRTC and GPU clocks as necessary.
4479 static void intel_idle_update(struct work_struct
*work
)
4481 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
4483 struct drm_device
*dev
= dev_priv
->dev
;
4484 struct drm_crtc
*crtc
;
4485 struct intel_crtc
*intel_crtc
;
4487 if (!i915_powersave
)
4490 mutex_lock(&dev
->struct_mutex
);
4492 i915_update_gfx_val(dev_priv
);
4494 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
4495 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4496 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN_MASK
| FW_BLC_SELF_EN
);
4499 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4500 /* Skip inactive CRTCs */
4504 intel_crtc
= to_intel_crtc(crtc
);
4505 if (!intel_crtc
->busy
)
4506 intel_decrease_pllclock(crtc
);
4509 mutex_unlock(&dev
->struct_mutex
);
4513 * intel_mark_busy - mark the GPU and possibly the display busy
4515 * @obj: object we're operating on
4517 * Callers can use this function to indicate that the GPU is busy processing
4518 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4519 * buffer), we'll also mark the display as busy, so we know to increase its
4522 void intel_mark_busy(struct drm_device
*dev
, struct drm_gem_object
*obj
)
4524 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4525 struct drm_crtc
*crtc
= NULL
;
4526 struct intel_framebuffer
*intel_fb
;
4527 struct intel_crtc
*intel_crtc
;
4529 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4532 if (!dev_priv
->busy
) {
4533 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
4536 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4537 fw_blc_self
= I915_READ(FW_BLC_SELF
);
4538 fw_blc_self
&= ~FW_BLC_SELF_EN
;
4539 I915_WRITE(FW_BLC_SELF
, fw_blc_self
| FW_BLC_SELF_EN_MASK
);
4541 dev_priv
->busy
= true;
4543 mod_timer(&dev_priv
->idle_timer
, jiffies
+
4544 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
4546 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4550 intel_crtc
= to_intel_crtc(crtc
);
4551 intel_fb
= to_intel_framebuffer(crtc
->fb
);
4552 if (intel_fb
->obj
== obj
) {
4553 if (!intel_crtc
->busy
) {
4554 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
4557 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4558 fw_blc_self
= I915_READ(FW_BLC_SELF
);
4559 fw_blc_self
&= ~FW_BLC_SELF_EN
;
4560 I915_WRITE(FW_BLC_SELF
, fw_blc_self
| FW_BLC_SELF_EN_MASK
);
4562 /* Non-busy -> busy, upclock */
4563 intel_increase_pllclock(crtc
, true);
4564 intel_crtc
->busy
= true;
4566 /* Busy -> busy, put off timer */
4567 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
4568 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
4574 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
4576 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4578 drm_crtc_cleanup(crtc
);
4582 struct intel_unpin_work
{
4583 struct work_struct work
;
4584 struct drm_device
*dev
;
4585 struct drm_gem_object
*old_fb_obj
;
4586 struct drm_gem_object
*pending_flip_obj
;
4587 struct drm_pending_vblank_event
*event
;
4591 static void intel_unpin_work_fn(struct work_struct
*__work
)
4593 struct intel_unpin_work
*work
=
4594 container_of(__work
, struct intel_unpin_work
, work
);
4596 mutex_lock(&work
->dev
->struct_mutex
);
4597 i915_gem_object_unpin(work
->old_fb_obj
);
4598 drm_gem_object_unreference(work
->pending_flip_obj
);
4599 drm_gem_object_unreference(work
->old_fb_obj
);
4600 mutex_unlock(&work
->dev
->struct_mutex
);
4604 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
4606 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4607 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
4608 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4609 struct intel_unpin_work
*work
;
4610 struct drm_i915_gem_object
*obj_priv
;
4611 struct drm_pending_vblank_event
*e
;
4613 unsigned long flags
;
4615 /* Ignore early vblank irqs */
4616 if (intel_crtc
== NULL
)
4619 spin_lock_irqsave(&dev
->event_lock
, flags
);
4620 work
= intel_crtc
->unpin_work
;
4621 if (work
== NULL
|| !work
->pending
) {
4622 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4626 intel_crtc
->unpin_work
= NULL
;
4627 drm_vblank_put(dev
, intel_crtc
->pipe
);
4631 do_gettimeofday(&now
);
4632 e
->event
.sequence
= drm_vblank_count(dev
, intel_crtc
->pipe
);
4633 e
->event
.tv_sec
= now
.tv_sec
;
4634 e
->event
.tv_usec
= now
.tv_usec
;
4635 list_add_tail(&e
->base
.link
,
4636 &e
->base
.file_priv
->event_list
);
4637 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
4640 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4642 obj_priv
= to_intel_bo(work
->pending_flip_obj
);
4644 /* Initial scanout buffer will have a 0 pending flip count */
4645 if ((atomic_read(&obj_priv
->pending_flip
) == 0) ||
4646 atomic_dec_and_test(&obj_priv
->pending_flip
))
4647 DRM_WAKEUP(&dev_priv
->pending_flip_queue
);
4648 schedule_work(&work
->work
);
4651 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
4653 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4654 struct intel_crtc
*intel_crtc
=
4655 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
4656 unsigned long flags
;
4658 spin_lock_irqsave(&dev
->event_lock
, flags
);
4659 if (intel_crtc
->unpin_work
) {
4660 intel_crtc
->unpin_work
->pending
= 1;
4662 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4664 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4667 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
4668 struct drm_framebuffer
*fb
,
4669 struct drm_pending_vblank_event
*event
)
4671 struct drm_device
*dev
= crtc
->dev
;
4672 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4673 struct intel_framebuffer
*intel_fb
;
4674 struct drm_i915_gem_object
*obj_priv
;
4675 struct drm_gem_object
*obj
;
4676 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4677 struct intel_unpin_work
*work
;
4678 unsigned long flags
;
4679 int pipesrc_reg
= (intel_crtc
->pipe
== 0) ? PIPEASRC
: PIPEBSRC
;
4682 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
4686 work
->event
= event
;
4687 work
->dev
= crtc
->dev
;
4688 intel_fb
= to_intel_framebuffer(crtc
->fb
);
4689 work
->old_fb_obj
= intel_fb
->obj
;
4690 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
4692 /* We borrow the event spin lock for protecting unpin_work */
4693 spin_lock_irqsave(&dev
->event_lock
, flags
);
4694 if (intel_crtc
->unpin_work
) {
4695 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4698 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4701 intel_crtc
->unpin_work
= work
;
4702 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4704 intel_fb
= to_intel_framebuffer(fb
);
4705 obj
= intel_fb
->obj
;
4707 mutex_lock(&dev
->struct_mutex
);
4708 ret
= intel_pin_and_fence_fb_obj(dev
, obj
);
4710 mutex_unlock(&dev
->struct_mutex
);
4712 spin_lock_irqsave(&dev
->event_lock
, flags
);
4713 intel_crtc
->unpin_work
= NULL
;
4714 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4718 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
4723 /* Reference the objects for the scheduled work. */
4724 drm_gem_object_reference(work
->old_fb_obj
);
4725 drm_gem_object_reference(obj
);
4728 i915_gem_object_flush_write_domain(obj
);
4729 drm_vblank_get(dev
, intel_crtc
->pipe
);
4730 obj_priv
= to_intel_bo(obj
);
4731 atomic_inc(&obj_priv
->pending_flip
);
4732 work
->pending_flip_obj
= obj
;
4735 OUT_RING(MI_DISPLAY_FLIP
|
4736 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
4737 OUT_RING(fb
->pitch
);
4738 if (IS_I965G(dev
)) {
4739 OUT_RING(obj_priv
->gtt_offset
| obj_priv
->tiling_mode
);
4740 pipesrc
= I915_READ(pipesrc_reg
);
4741 OUT_RING(pipesrc
& 0x0fff0fff);
4743 OUT_RING(obj_priv
->gtt_offset
);
4748 mutex_unlock(&dev
->struct_mutex
);
4753 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
4754 .dpms
= intel_crtc_dpms
,
4755 .mode_fixup
= intel_crtc_mode_fixup
,
4756 .mode_set
= intel_crtc_mode_set
,
4757 .mode_set_base
= intel_pipe_set_base
,
4758 .prepare
= intel_crtc_prepare
,
4759 .commit
= intel_crtc_commit
,
4760 .load_lut
= intel_crtc_load_lut
,
4763 static const struct drm_crtc_funcs intel_crtc_funcs
= {
4764 .cursor_set
= intel_crtc_cursor_set
,
4765 .cursor_move
= intel_crtc_cursor_move
,
4766 .gamma_set
= intel_crtc_gamma_set
,
4767 .set_config
= drm_crtc_helper_set_config
,
4768 .destroy
= intel_crtc_destroy
,
4769 .page_flip
= intel_crtc_page_flip
,
4773 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
4775 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4776 struct intel_crtc
*intel_crtc
;
4779 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
4780 if (intel_crtc
== NULL
)
4783 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
4785 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
4786 intel_crtc
->pipe
= pipe
;
4787 intel_crtc
->plane
= pipe
;
4788 for (i
= 0; i
< 256; i
++) {
4789 intel_crtc
->lut_r
[i
] = i
;
4790 intel_crtc
->lut_g
[i
] = i
;
4791 intel_crtc
->lut_b
[i
] = i
;
4794 /* Swap pipes & planes for FBC on pre-965 */
4795 intel_crtc
->pipe
= pipe
;
4796 intel_crtc
->plane
= pipe
;
4797 if (IS_MOBILE(dev
) && (IS_I9XX(dev
) && !IS_I965G(dev
))) {
4798 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4799 intel_crtc
->plane
= ((pipe
== 0) ? 1 : 0);
4802 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
4803 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
4804 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
4805 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
4807 intel_crtc
->cursor_addr
= 0;
4808 intel_crtc
->dpms_mode
= DRM_MODE_DPMS_OFF
;
4809 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
4811 intel_crtc
->busy
= false;
4813 setup_timer(&intel_crtc
->idle_timer
, intel_crtc_idle_timer
,
4814 (unsigned long)intel_crtc
);
4817 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
4818 struct drm_file
*file_priv
)
4820 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4821 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
4822 struct drm_mode_object
*drmmode_obj
;
4823 struct intel_crtc
*crtc
;
4826 DRM_ERROR("called with no initialization\n");
4830 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
4831 DRM_MODE_OBJECT_CRTC
);
4834 DRM_ERROR("no such CRTC id\n");
4838 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
4839 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
4844 struct drm_crtc
*intel_get_crtc_from_pipe(struct drm_device
*dev
, int pipe
)
4846 struct drm_crtc
*crtc
= NULL
;
4848 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4849 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4850 if (intel_crtc
->pipe
== pipe
)
4856 static int intel_encoder_clones(struct drm_device
*dev
, int type_mask
)
4859 struct drm_encoder
*encoder
;
4862 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
4863 struct intel_encoder
*intel_encoder
= enc_to_intel_encoder(encoder
);
4864 if (type_mask
& intel_encoder
->clone_mask
)
4865 index_mask
|= (1 << entry
);
4872 static void intel_setup_outputs(struct drm_device
*dev
)
4874 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4875 struct drm_encoder
*encoder
;
4877 intel_crt_init(dev
);
4879 /* Set up integrated LVDS */
4880 if (IS_MOBILE(dev
) && !IS_I830(dev
))
4881 intel_lvds_init(dev
);
4883 if (HAS_PCH_SPLIT(dev
)) {
4886 if (IS_MOBILE(dev
) && (I915_READ(DP_A
) & DP_DETECTED
))
4887 intel_dp_init(dev
, DP_A
);
4889 if (I915_READ(HDMIB
) & PORT_DETECTED
) {
4890 /* PCH SDVOB multiplex with HDMIB */
4891 found
= intel_sdvo_init(dev
, PCH_SDVOB
);
4893 intel_hdmi_init(dev
, HDMIB
);
4894 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
4895 intel_dp_init(dev
, PCH_DP_B
);
4898 if (I915_READ(HDMIC
) & PORT_DETECTED
)
4899 intel_hdmi_init(dev
, HDMIC
);
4901 if (I915_READ(HDMID
) & PORT_DETECTED
)
4902 intel_hdmi_init(dev
, HDMID
);
4904 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
4905 intel_dp_init(dev
, PCH_DP_C
);
4907 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
4908 intel_dp_init(dev
, PCH_DP_D
);
4910 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
4913 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
4914 DRM_DEBUG_KMS("probing SDVOB\n");
4915 found
= intel_sdvo_init(dev
, SDVOB
);
4916 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
4917 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4918 intel_hdmi_init(dev
, SDVOB
);
4921 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
4922 DRM_DEBUG_KMS("probing DP_B\n");
4923 intel_dp_init(dev
, DP_B
);
4927 /* Before G4X SDVOC doesn't have its own detect register */
4929 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
4930 DRM_DEBUG_KMS("probing SDVOC\n");
4931 found
= intel_sdvo_init(dev
, SDVOC
);
4934 if (!found
&& (I915_READ(SDVOC
) & SDVO_DETECTED
)) {
4936 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
4937 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4938 intel_hdmi_init(dev
, SDVOC
);
4940 if (SUPPORTS_INTEGRATED_DP(dev
)) {
4941 DRM_DEBUG_KMS("probing DP_C\n");
4942 intel_dp_init(dev
, DP_C
);
4946 if (SUPPORTS_INTEGRATED_DP(dev
) &&
4947 (I915_READ(DP_D
) & DP_DETECTED
)) {
4948 DRM_DEBUG_KMS("probing DP_D\n");
4949 intel_dp_init(dev
, DP_D
);
4951 } else if (IS_GEN2(dev
))
4952 intel_dvo_init(dev
);
4954 if (SUPPORTS_TV(dev
))
4957 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
4958 struct intel_encoder
*intel_encoder
= enc_to_intel_encoder(encoder
);
4960 encoder
->possible_crtcs
= intel_encoder
->crtc_mask
;
4961 encoder
->possible_clones
= intel_encoder_clones(dev
,
4962 intel_encoder
->clone_mask
);
4966 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
4968 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
4970 drm_framebuffer_cleanup(fb
);
4971 drm_gem_object_unreference_unlocked(intel_fb
->obj
);
4976 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
4977 struct drm_file
*file_priv
,
4978 unsigned int *handle
)
4980 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
4981 struct drm_gem_object
*object
= intel_fb
->obj
;
4983 return drm_gem_handle_create(file_priv
, object
, handle
);
4986 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
4987 .destroy
= intel_user_framebuffer_destroy
,
4988 .create_handle
= intel_user_framebuffer_create_handle
,
4991 int intel_framebuffer_init(struct drm_device
*dev
,
4992 struct intel_framebuffer
*intel_fb
,
4993 struct drm_mode_fb_cmd
*mode_cmd
,
4994 struct drm_gem_object
*obj
)
4998 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
5000 DRM_ERROR("framebuffer init failed %d\n", ret
);
5004 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
5005 intel_fb
->obj
= obj
;
5009 static struct drm_framebuffer
*
5010 intel_user_framebuffer_create(struct drm_device
*dev
,
5011 struct drm_file
*filp
,
5012 struct drm_mode_fb_cmd
*mode_cmd
)
5014 struct drm_gem_object
*obj
;
5015 struct intel_framebuffer
*intel_fb
;
5018 obj
= drm_gem_object_lookup(dev
, filp
, mode_cmd
->handle
);
5022 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
5026 ret
= intel_framebuffer_init(dev
, intel_fb
,
5029 drm_gem_object_unreference_unlocked(obj
);
5034 return &intel_fb
->base
;
5037 static const struct drm_mode_config_funcs intel_mode_funcs
= {
5038 .fb_create
= intel_user_framebuffer_create
,
5039 .output_poll_changed
= intel_fb_output_poll_changed
,
5042 static struct drm_gem_object
*
5043 intel_alloc_power_context(struct drm_device
*dev
)
5045 struct drm_gem_object
*pwrctx
;
5048 pwrctx
= i915_gem_alloc_object(dev
, 4096);
5050 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5054 mutex_lock(&dev
->struct_mutex
);
5055 ret
= i915_gem_object_pin(pwrctx
, 4096);
5057 DRM_ERROR("failed to pin power context: %d\n", ret
);
5061 ret
= i915_gem_object_set_to_gtt_domain(pwrctx
, 1);
5063 DRM_ERROR("failed to set-domain on power context: %d\n", ret
);
5066 mutex_unlock(&dev
->struct_mutex
);
5071 i915_gem_object_unpin(pwrctx
);
5073 drm_gem_object_unreference(pwrctx
);
5074 mutex_unlock(&dev
->struct_mutex
);
5078 bool ironlake_set_drps(struct drm_device
*dev
, u8 val
)
5080 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5083 rgvswctl
= I915_READ16(MEMSWCTL
);
5084 if (rgvswctl
& MEMCTL_CMD_STS
) {
5085 DRM_DEBUG("gpu busy, RCS change rejected\n");
5086 return false; /* still busy with another command */
5089 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
5090 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
5091 I915_WRITE16(MEMSWCTL
, rgvswctl
);
5092 POSTING_READ16(MEMSWCTL
);
5094 rgvswctl
|= MEMCTL_CMD_STS
;
5095 I915_WRITE16(MEMSWCTL
, rgvswctl
);
5100 void ironlake_enable_drps(struct drm_device
*dev
)
5102 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5103 u32 rgvmodectl
= I915_READ(MEMMODECTL
);
5104 u8 fmax
, fmin
, fstart
, vstart
;
5107 /* 100ms RC evaluation intervals */
5108 I915_WRITE(RCUPEI
, 100000);
5109 I915_WRITE(RCDNEI
, 100000);
5111 /* Set max/min thresholds to 90ms and 80ms respectively */
5112 I915_WRITE(RCBMAXAVG
, 90000);
5113 I915_WRITE(RCBMINAVG
, 80000);
5115 I915_WRITE(MEMIHYST
, 1);
5117 /* Set up min, max, and cur for interrupt handling */
5118 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
5119 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
5120 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
5121 MEMMODE_FSTART_SHIFT
;
5124 vstart
= (I915_READ(PXVFREQ_BASE
+ (fstart
* 4)) & PXVFREQ_PX_MASK
) >>
5127 dev_priv
->fmax
= fstart
; /* IPS callback will increase this */
5128 dev_priv
->fstart
= fstart
;
5130 dev_priv
->max_delay
= fmax
;
5131 dev_priv
->min_delay
= fmin
;
5132 dev_priv
->cur_delay
= fstart
;
5134 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax
, fmin
,
5137 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
5140 * Interrupts will be enabled in ironlake_irq_postinstall
5143 I915_WRITE(VIDSTART
, vstart
);
5144 POSTING_READ(VIDSTART
);
5146 rgvmodectl
|= MEMMODE_SWMODE_EN
;
5147 I915_WRITE(MEMMODECTL
, rgvmodectl
);
5149 while (I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) {
5151 DRM_ERROR("stuck trying to change perf mode\n");
5158 ironlake_set_drps(dev
, fstart
);
5160 dev_priv
->last_count1
= I915_READ(0x112e4) + I915_READ(0x112e8) +
5162 dev_priv
->last_time1
= jiffies_to_msecs(jiffies
);
5163 dev_priv
->last_count2
= I915_READ(0x112f4);
5164 getrawmonotonic(&dev_priv
->last_time2
);
5167 void ironlake_disable_drps(struct drm_device
*dev
)
5169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5170 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
5172 /* Ack interrupts, disable EFC interrupt */
5173 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
5174 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
5175 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
5176 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
5177 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
5179 /* Go back to the starting frequency */
5180 ironlake_set_drps(dev
, dev_priv
->fstart
);
5182 rgvswctl
|= MEMCTL_CMD_STS
;
5183 I915_WRITE(MEMSWCTL
, rgvswctl
);
5188 static unsigned long intel_pxfreq(u32 vidfreq
)
5191 int div
= (vidfreq
& 0x3f0000) >> 16;
5192 int post
= (vidfreq
& 0x3000) >> 12;
5193 int pre
= (vidfreq
& 0x7);
5198 freq
= ((div
* 133333) / ((1<<post
) * pre
));
5203 void intel_init_emon(struct drm_device
*dev
)
5205 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5210 /* Disable to program */
5214 /* Program energy weights for various events */
5215 I915_WRITE(SDEW
, 0x15040d00);
5216 I915_WRITE(CSIEW0
, 0x007f0000);
5217 I915_WRITE(CSIEW1
, 0x1e220004);
5218 I915_WRITE(CSIEW2
, 0x04000004);
5220 for (i
= 0; i
< 5; i
++)
5221 I915_WRITE(PEW
+ (i
* 4), 0);
5222 for (i
= 0; i
< 3; i
++)
5223 I915_WRITE(DEW
+ (i
* 4), 0);
5225 /* Program P-state weights to account for frequency power adjustment */
5226 for (i
= 0; i
< 16; i
++) {
5227 u32 pxvidfreq
= I915_READ(PXVFREQ_BASE
+ (i
* 4));
5228 unsigned long freq
= intel_pxfreq(pxvidfreq
);
5229 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
5234 val
*= (freq
/ 1000);
5236 val
/= (127*127*900);
5238 DRM_ERROR("bad pxval: %ld\n", val
);
5241 /* Render standby states get 0 weight */
5245 for (i
= 0; i
< 4; i
++) {
5246 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
5247 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
5248 I915_WRITE(PXW
+ (i
* 4), val
);
5251 /* Adjust magic regs to magic values (more experimental results) */
5252 I915_WRITE(OGW0
, 0);
5253 I915_WRITE(OGW1
, 0);
5254 I915_WRITE(EG0
, 0x00007f00);
5255 I915_WRITE(EG1
, 0x0000000e);
5256 I915_WRITE(EG2
, 0x000e0000);
5257 I915_WRITE(EG3
, 0x68000300);
5258 I915_WRITE(EG4
, 0x42000000);
5259 I915_WRITE(EG5
, 0x00140031);
5263 for (i
= 0; i
< 8; i
++)
5264 I915_WRITE(PXWL
+ (i
* 4), 0);
5266 /* Enable PMON + select events */
5267 I915_WRITE(ECR
, 0x80000019);
5269 lcfuse
= I915_READ(LCFUSE02
);
5271 dev_priv
->corr
= (lcfuse
& LCFUSE_HIV_MASK
);
5274 void intel_init_clock_gating(struct drm_device
*dev
)
5276 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5279 * Disable clock gating reported to work incorrectly according to the
5280 * specs, but enable as much else as we can.
5282 if (HAS_PCH_SPLIT(dev
)) {
5283 uint32_t dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
;
5285 if (IS_IRONLAKE(dev
)) {
5286 /* Required for FBC */
5287 dspclk_gate
|= DPFDUNIT_CLOCK_GATE_DISABLE
;
5288 /* Required for CxSR */
5289 dspclk_gate
|= DPARBUNIT_CLOCK_GATE_DISABLE
;
5291 I915_WRITE(PCH_3DCGDIS0
,
5292 MARIUNIT_CLOCK_GATE_DISABLE
|
5293 SVSMUNIT_CLOCK_GATE_DISABLE
);
5296 I915_WRITE(PCH_DSPCLK_GATE_D
, dspclk_gate
);
5299 * According to the spec the following bits should be set in
5300 * order to enable memory self-refresh
5301 * The bit 22/21 of 0x42004
5302 * The bit 5 of 0x42020
5303 * The bit 15 of 0x45000
5305 if (IS_IRONLAKE(dev
)) {
5306 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5307 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
5308 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
5309 I915_WRITE(ILK_DSPCLK_GATE
,
5310 (I915_READ(ILK_DSPCLK_GATE
) |
5311 ILK_DPARB_CLK_GATE
));
5312 I915_WRITE(DISP_ARB_CTL
,
5313 (I915_READ(DISP_ARB_CTL
) |
5317 } else if (IS_G4X(dev
)) {
5318 uint32_t dspclk_gate
;
5319 I915_WRITE(RENCLK_GATE_D1
, 0);
5320 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
5321 GS_UNIT_CLOCK_GATE_DISABLE
|
5322 CL_UNIT_CLOCK_GATE_DISABLE
);
5323 I915_WRITE(RAMCLK_GATE_D
, 0);
5324 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
5325 OVRUNIT_CLOCK_GATE_DISABLE
|
5326 OVCUNIT_CLOCK_GATE_DISABLE
;
5328 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
5329 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
5330 } else if (IS_I965GM(dev
)) {
5331 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
5332 I915_WRITE(RENCLK_GATE_D2
, 0);
5333 I915_WRITE(DSPCLK_GATE_D
, 0);
5334 I915_WRITE(RAMCLK_GATE_D
, 0);
5335 I915_WRITE16(DEUC
, 0);
5336 } else if (IS_I965G(dev
)) {
5337 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
5338 I965_RCC_CLOCK_GATE_DISABLE
|
5339 I965_RCPB_CLOCK_GATE_DISABLE
|
5340 I965_ISC_CLOCK_GATE_DISABLE
|
5341 I965_FBC_CLOCK_GATE_DISABLE
);
5342 I915_WRITE(RENCLK_GATE_D2
, 0);
5343 } else if (IS_I9XX(dev
)) {
5344 u32 dstate
= I915_READ(D_STATE
);
5346 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
5347 DSTATE_DOT_CLOCK_GATING
;
5348 I915_WRITE(D_STATE
, dstate
);
5349 } else if (IS_I85X(dev
) || IS_I865G(dev
)) {
5350 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
5351 } else if (IS_I830(dev
)) {
5352 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
5356 * GPU can automatically power down the render unit if given a page
5359 if (I915_HAS_RC6(dev
) && drm_core_check_feature(dev
, DRIVER_MODESET
)) {
5360 struct drm_i915_gem_object
*obj_priv
= NULL
;
5362 if (dev_priv
->pwrctx
) {
5363 obj_priv
= to_intel_bo(dev_priv
->pwrctx
);
5365 struct drm_gem_object
*pwrctx
;
5367 pwrctx
= intel_alloc_power_context(dev
);
5369 dev_priv
->pwrctx
= pwrctx
;
5370 obj_priv
= to_intel_bo(pwrctx
);
5375 I915_WRITE(PWRCTXA
, obj_priv
->gtt_offset
| PWRCTX_EN
);
5376 I915_WRITE(MCHBAR_RENDER_STANDBY
,
5377 I915_READ(MCHBAR_RENDER_STANDBY
) & ~RCX_SW_EXIT
);
5382 /* Set up chip specific display functions */
5383 static void intel_init_display(struct drm_device
*dev
)
5385 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5387 /* We always want a DPMS function */
5388 if (HAS_PCH_SPLIT(dev
))
5389 dev_priv
->display
.dpms
= ironlake_crtc_dpms
;
5391 dev_priv
->display
.dpms
= i9xx_crtc_dpms
;
5393 if (I915_HAS_FBC(dev
)) {
5395 dev_priv
->display
.fbc_enabled
= g4x_fbc_enabled
;
5396 dev_priv
->display
.enable_fbc
= g4x_enable_fbc
;
5397 dev_priv
->display
.disable_fbc
= g4x_disable_fbc
;
5398 } else if (IS_I965GM(dev
)) {
5399 dev_priv
->display
.fbc_enabled
= i8xx_fbc_enabled
;
5400 dev_priv
->display
.enable_fbc
= i8xx_enable_fbc
;
5401 dev_priv
->display
.disable_fbc
= i8xx_disable_fbc
;
5403 /* 855GM needs testing */
5406 /* Returns the core display clock speed */
5407 if (IS_I945G(dev
) || (IS_G33(dev
) && ! IS_PINEVIEW_M(dev
)))
5408 dev_priv
->display
.get_display_clock_speed
=
5409 i945_get_display_clock_speed
;
5410 else if (IS_I915G(dev
))
5411 dev_priv
->display
.get_display_clock_speed
=
5412 i915_get_display_clock_speed
;
5413 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
5414 dev_priv
->display
.get_display_clock_speed
=
5415 i9xx_misc_get_display_clock_speed
;
5416 else if (IS_I915GM(dev
))
5417 dev_priv
->display
.get_display_clock_speed
=
5418 i915gm_get_display_clock_speed
;
5419 else if (IS_I865G(dev
))
5420 dev_priv
->display
.get_display_clock_speed
=
5421 i865_get_display_clock_speed
;
5422 else if (IS_I85X(dev
))
5423 dev_priv
->display
.get_display_clock_speed
=
5424 i855_get_display_clock_speed
;
5426 dev_priv
->display
.get_display_clock_speed
=
5427 i830_get_display_clock_speed
;
5429 /* For FIFO watermark updates */
5430 if (HAS_PCH_SPLIT(dev
)) {
5431 if (IS_IRONLAKE(dev
)) {
5432 if (I915_READ(MLTR_ILK
) & ILK_SRLT_MASK
)
5433 dev_priv
->display
.update_wm
= ironlake_update_wm
;
5435 DRM_DEBUG_KMS("Failed to get proper latency. "
5437 dev_priv
->display
.update_wm
= NULL
;
5440 dev_priv
->display
.update_wm
= NULL
;
5441 } else if (IS_PINEVIEW(dev
)) {
5442 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
5445 dev_priv
->mem_freq
)) {
5446 DRM_INFO("failed to find known CxSR latency "
5447 "(found ddr%s fsb freq %d, mem freq %d), "
5449 (dev_priv
->is_ddr3
== 1) ? "3": "2",
5450 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
5451 /* Disable CxSR and never update its watermark again */
5452 pineview_disable_cxsr(dev
);
5453 dev_priv
->display
.update_wm
= NULL
;
5455 dev_priv
->display
.update_wm
= pineview_update_wm
;
5456 } else if (IS_G4X(dev
))
5457 dev_priv
->display
.update_wm
= g4x_update_wm
;
5458 else if (IS_I965G(dev
))
5459 dev_priv
->display
.update_wm
= i965_update_wm
;
5460 else if (IS_I9XX(dev
)) {
5461 dev_priv
->display
.update_wm
= i9xx_update_wm
;
5462 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
5463 } else if (IS_I85X(dev
)) {
5464 dev_priv
->display
.update_wm
= i9xx_update_wm
;
5465 dev_priv
->display
.get_fifo_size
= i85x_get_fifo_size
;
5467 dev_priv
->display
.update_wm
= i830_update_wm
;
5469 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
5471 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
5475 void intel_modeset_init(struct drm_device
*dev
)
5477 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5480 drm_mode_config_init(dev
);
5482 dev
->mode_config
.min_width
= 0;
5483 dev
->mode_config
.min_height
= 0;
5485 dev
->mode_config
.funcs
= (void *)&intel_mode_funcs
;
5487 intel_init_display(dev
);
5489 if (IS_I965G(dev
)) {
5490 dev
->mode_config
.max_width
= 8192;
5491 dev
->mode_config
.max_height
= 8192;
5492 } else if (IS_I9XX(dev
)) {
5493 dev
->mode_config
.max_width
= 4096;
5494 dev
->mode_config
.max_height
= 4096;
5496 dev
->mode_config
.max_width
= 2048;
5497 dev
->mode_config
.max_height
= 2048;
5500 /* set memory base */
5502 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 2);
5504 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 0);
5506 if (IS_MOBILE(dev
) || IS_I9XX(dev
))
5507 dev_priv
->num_pipe
= 2;
5509 dev_priv
->num_pipe
= 1;
5510 DRM_DEBUG_KMS("%d display pipe%s available.\n",
5511 dev_priv
->num_pipe
, dev_priv
->num_pipe
> 1 ? "s" : "");
5513 for (i
= 0; i
< dev_priv
->num_pipe
; i
++) {
5514 intel_crtc_init(dev
, i
);
5517 intel_setup_outputs(dev
);
5519 intel_init_clock_gating(dev
);
5521 if (IS_IRONLAKE_M(dev
)) {
5522 ironlake_enable_drps(dev
);
5523 intel_init_emon(dev
);
5526 INIT_WORK(&dev_priv
->idle_work
, intel_idle_update
);
5527 setup_timer(&dev_priv
->idle_timer
, intel_gpu_idle_timer
,
5528 (unsigned long)dev
);
5530 intel_setup_overlay(dev
);
5533 void intel_modeset_cleanup(struct drm_device
*dev
)
5535 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5536 struct drm_crtc
*crtc
;
5537 struct intel_crtc
*intel_crtc
;
5539 mutex_lock(&dev
->struct_mutex
);
5541 drm_kms_helper_poll_fini(dev
);
5542 intel_fbdev_fini(dev
);
5544 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
5545 /* Skip inactive CRTCs */
5549 intel_crtc
= to_intel_crtc(crtc
);
5550 intel_increase_pllclock(crtc
, false);
5551 del_timer_sync(&intel_crtc
->idle_timer
);
5554 del_timer_sync(&dev_priv
->idle_timer
);
5556 if (dev_priv
->display
.disable_fbc
)
5557 dev_priv
->display
.disable_fbc(dev
);
5559 if (dev_priv
->pwrctx
) {
5560 struct drm_i915_gem_object
*obj_priv
;
5562 obj_priv
= to_intel_bo(dev_priv
->pwrctx
);
5563 I915_WRITE(PWRCTXA
, obj_priv
->gtt_offset
&~ PWRCTX_EN
);
5565 i915_gem_object_unpin(dev_priv
->pwrctx
);
5566 drm_gem_object_unreference(dev_priv
->pwrctx
);
5569 if (IS_IRONLAKE_M(dev
))
5570 ironlake_disable_drps(dev
);
5572 mutex_unlock(&dev
->struct_mutex
);
5574 drm_mode_config_cleanup(dev
);
5579 * Return which encoder is currently attached for connector.
5581 struct drm_encoder
*intel_attached_encoder (struct drm_connector
*connector
)
5583 struct drm_mode_object
*obj
;
5584 struct drm_encoder
*encoder
;
5587 for (i
= 0; i
< DRM_CONNECTOR_MAX_ENCODER
; i
++) {
5588 if (connector
->encoder_ids
[i
] == 0)
5591 obj
= drm_mode_object_find(connector
->dev
,
5592 connector
->encoder_ids
[i
],
5593 DRM_MODE_OBJECT_ENCODER
);
5597 encoder
= obj_to_encoder(obj
);
5604 * set vga decode state - true == enable VGA decode
5606 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
5608 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5611 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
5613 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
5615 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
5616 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);