2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
);
45 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
46 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t
;
72 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
85 * Returns true on success, false on failure.
87 bool (*find_pll
)(const intel_limit_t
*limit
,
88 struct drm_crtc
*crtc
,
89 int target
, int refclk
,
90 intel_clock_t
*match_clock
,
91 intel_clock_t
*best_clock
);
95 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
98 intel_pch_rawclk(struct drm_device
*dev
)
100 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
102 WARN_ON(!HAS_PCH_SPLIT(dev
));
104 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
108 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
109 int target
, int refclk
, intel_clock_t
*match_clock
,
110 intel_clock_t
*best_clock
);
112 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
113 int target
, int refclk
, intel_clock_t
*match_clock
,
114 intel_clock_t
*best_clock
);
117 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
118 int target
, int refclk
, intel_clock_t
*match_clock
,
119 intel_clock_t
*best_clock
);
121 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
122 int target
, int refclk
, intel_clock_t
*match_clock
,
123 intel_clock_t
*best_clock
);
126 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
127 int target
, int refclk
, intel_clock_t
*match_clock
,
128 intel_clock_t
*best_clock
);
130 static inline u32
/* units of 100MHz */
131 intel_fdi_link_freq(struct drm_device
*dev
)
134 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
135 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
140 static const intel_limit_t intel_limits_i8xx_dvo
= {
141 .dot
= { .min
= 25000, .max
= 350000 },
142 .vco
= { .min
= 930000, .max
= 1400000 },
143 .n
= { .min
= 3, .max
= 16 },
144 .m
= { .min
= 96, .max
= 140 },
145 .m1
= { .min
= 18, .max
= 26 },
146 .m2
= { .min
= 6, .max
= 16 },
147 .p
= { .min
= 4, .max
= 128 },
148 .p1
= { .min
= 2, .max
= 33 },
149 .p2
= { .dot_limit
= 165000,
150 .p2_slow
= 4, .p2_fast
= 2 },
151 .find_pll
= intel_find_best_PLL
,
154 static const intel_limit_t intel_limits_i8xx_lvds
= {
155 .dot
= { .min
= 25000, .max
= 350000 },
156 .vco
= { .min
= 930000, .max
= 1400000 },
157 .n
= { .min
= 3, .max
= 16 },
158 .m
= { .min
= 96, .max
= 140 },
159 .m1
= { .min
= 18, .max
= 26 },
160 .m2
= { .min
= 6, .max
= 16 },
161 .p
= { .min
= 4, .max
= 128 },
162 .p1
= { .min
= 1, .max
= 6 },
163 .p2
= { .dot_limit
= 165000,
164 .p2_slow
= 14, .p2_fast
= 7 },
165 .find_pll
= intel_find_best_PLL
,
168 static const intel_limit_t intel_limits_i9xx_sdvo
= {
169 .dot
= { .min
= 20000, .max
= 400000 },
170 .vco
= { .min
= 1400000, .max
= 2800000 },
171 .n
= { .min
= 1, .max
= 6 },
172 .m
= { .min
= 70, .max
= 120 },
173 .m1
= { .min
= 8, .max
= 18 },
174 .m2
= { .min
= 3, .max
= 7 },
175 .p
= { .min
= 5, .max
= 80 },
176 .p1
= { .min
= 1, .max
= 8 },
177 .p2
= { .dot_limit
= 200000,
178 .p2_slow
= 10, .p2_fast
= 5 },
179 .find_pll
= intel_find_best_PLL
,
182 static const intel_limit_t intel_limits_i9xx_lvds
= {
183 .dot
= { .min
= 20000, .max
= 400000 },
184 .vco
= { .min
= 1400000, .max
= 2800000 },
185 .n
= { .min
= 1, .max
= 6 },
186 .m
= { .min
= 70, .max
= 120 },
187 .m1
= { .min
= 8, .max
= 18 },
188 .m2
= { .min
= 3, .max
= 7 },
189 .p
= { .min
= 7, .max
= 98 },
190 .p1
= { .min
= 1, .max
= 8 },
191 .p2
= { .dot_limit
= 112000,
192 .p2_slow
= 14, .p2_fast
= 7 },
193 .find_pll
= intel_find_best_PLL
,
197 static const intel_limit_t intel_limits_g4x_sdvo
= {
198 .dot
= { .min
= 25000, .max
= 270000 },
199 .vco
= { .min
= 1750000, .max
= 3500000},
200 .n
= { .min
= 1, .max
= 4 },
201 .m
= { .min
= 104, .max
= 138 },
202 .m1
= { .min
= 17, .max
= 23 },
203 .m2
= { .min
= 5, .max
= 11 },
204 .p
= { .min
= 10, .max
= 30 },
205 .p1
= { .min
= 1, .max
= 3},
206 .p2
= { .dot_limit
= 270000,
210 .find_pll
= intel_g4x_find_best_PLL
,
213 static const intel_limit_t intel_limits_g4x_hdmi
= {
214 .dot
= { .min
= 22000, .max
= 400000 },
215 .vco
= { .min
= 1750000, .max
= 3500000},
216 .n
= { .min
= 1, .max
= 4 },
217 .m
= { .min
= 104, .max
= 138 },
218 .m1
= { .min
= 16, .max
= 23 },
219 .m2
= { .min
= 5, .max
= 11 },
220 .p
= { .min
= 5, .max
= 80 },
221 .p1
= { .min
= 1, .max
= 8},
222 .p2
= { .dot_limit
= 165000,
223 .p2_slow
= 10, .p2_fast
= 5 },
224 .find_pll
= intel_g4x_find_best_PLL
,
227 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
228 .dot
= { .min
= 20000, .max
= 115000 },
229 .vco
= { .min
= 1750000, .max
= 3500000 },
230 .n
= { .min
= 1, .max
= 3 },
231 .m
= { .min
= 104, .max
= 138 },
232 .m1
= { .min
= 17, .max
= 23 },
233 .m2
= { .min
= 5, .max
= 11 },
234 .p
= { .min
= 28, .max
= 112 },
235 .p1
= { .min
= 2, .max
= 8 },
236 .p2
= { .dot_limit
= 0,
237 .p2_slow
= 14, .p2_fast
= 14
239 .find_pll
= intel_g4x_find_best_PLL
,
242 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
243 .dot
= { .min
= 80000, .max
= 224000 },
244 .vco
= { .min
= 1750000, .max
= 3500000 },
245 .n
= { .min
= 1, .max
= 3 },
246 .m
= { .min
= 104, .max
= 138 },
247 .m1
= { .min
= 17, .max
= 23 },
248 .m2
= { .min
= 5, .max
= 11 },
249 .p
= { .min
= 14, .max
= 42 },
250 .p1
= { .min
= 2, .max
= 6 },
251 .p2
= { .dot_limit
= 0,
252 .p2_slow
= 7, .p2_fast
= 7
254 .find_pll
= intel_g4x_find_best_PLL
,
257 static const intel_limit_t intel_limits_g4x_display_port
= {
258 .dot
= { .min
= 161670, .max
= 227000 },
259 .vco
= { .min
= 1750000, .max
= 3500000},
260 .n
= { .min
= 1, .max
= 2 },
261 .m
= { .min
= 97, .max
= 108 },
262 .m1
= { .min
= 0x10, .max
= 0x12 },
263 .m2
= { .min
= 0x05, .max
= 0x06 },
264 .p
= { .min
= 10, .max
= 20 },
265 .p1
= { .min
= 1, .max
= 2},
266 .p2
= { .dot_limit
= 0,
267 .p2_slow
= 10, .p2_fast
= 10 },
268 .find_pll
= intel_find_pll_g4x_dp
,
271 static const intel_limit_t intel_limits_pineview_sdvo
= {
272 .dot
= { .min
= 20000, .max
= 400000},
273 .vco
= { .min
= 1700000, .max
= 3500000 },
274 /* Pineview's Ncounter is a ring counter */
275 .n
= { .min
= 3, .max
= 6 },
276 .m
= { .min
= 2, .max
= 256 },
277 /* Pineview only has one combined m divider, which we treat as m2. */
278 .m1
= { .min
= 0, .max
= 0 },
279 .m2
= { .min
= 0, .max
= 254 },
280 .p
= { .min
= 5, .max
= 80 },
281 .p1
= { .min
= 1, .max
= 8 },
282 .p2
= { .dot_limit
= 200000,
283 .p2_slow
= 10, .p2_fast
= 5 },
284 .find_pll
= intel_find_best_PLL
,
287 static const intel_limit_t intel_limits_pineview_lvds
= {
288 .dot
= { .min
= 20000, .max
= 400000 },
289 .vco
= { .min
= 1700000, .max
= 3500000 },
290 .n
= { .min
= 3, .max
= 6 },
291 .m
= { .min
= 2, .max
= 256 },
292 .m1
= { .min
= 0, .max
= 0 },
293 .m2
= { .min
= 0, .max
= 254 },
294 .p
= { .min
= 7, .max
= 112 },
295 .p1
= { .min
= 1, .max
= 8 },
296 .p2
= { .dot_limit
= 112000,
297 .p2_slow
= 14, .p2_fast
= 14 },
298 .find_pll
= intel_find_best_PLL
,
301 /* Ironlake / Sandybridge
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
306 static const intel_limit_t intel_limits_ironlake_dac
= {
307 .dot
= { .min
= 25000, .max
= 350000 },
308 .vco
= { .min
= 1760000, .max
= 3510000 },
309 .n
= { .min
= 1, .max
= 5 },
310 .m
= { .min
= 79, .max
= 127 },
311 .m1
= { .min
= 12, .max
= 22 },
312 .m2
= { .min
= 5, .max
= 9 },
313 .p
= { .min
= 5, .max
= 80 },
314 .p1
= { .min
= 1, .max
= 8 },
315 .p2
= { .dot_limit
= 225000,
316 .p2_slow
= 10, .p2_fast
= 5 },
317 .find_pll
= intel_g4x_find_best_PLL
,
320 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
321 .dot
= { .min
= 25000, .max
= 350000 },
322 .vco
= { .min
= 1760000, .max
= 3510000 },
323 .n
= { .min
= 1, .max
= 3 },
324 .m
= { .min
= 79, .max
= 118 },
325 .m1
= { .min
= 12, .max
= 22 },
326 .m2
= { .min
= 5, .max
= 9 },
327 .p
= { .min
= 28, .max
= 112 },
328 .p1
= { .min
= 2, .max
= 8 },
329 .p2
= { .dot_limit
= 225000,
330 .p2_slow
= 14, .p2_fast
= 14 },
331 .find_pll
= intel_g4x_find_best_PLL
,
334 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
335 .dot
= { .min
= 25000, .max
= 350000 },
336 .vco
= { .min
= 1760000, .max
= 3510000 },
337 .n
= { .min
= 1, .max
= 3 },
338 .m
= { .min
= 79, .max
= 127 },
339 .m1
= { .min
= 12, .max
= 22 },
340 .m2
= { .min
= 5, .max
= 9 },
341 .p
= { .min
= 14, .max
= 56 },
342 .p1
= { .min
= 2, .max
= 8 },
343 .p2
= { .dot_limit
= 225000,
344 .p2_slow
= 7, .p2_fast
= 7 },
345 .find_pll
= intel_g4x_find_best_PLL
,
348 /* LVDS 100mhz refclk limits. */
349 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
350 .dot
= { .min
= 25000, .max
= 350000 },
351 .vco
= { .min
= 1760000, .max
= 3510000 },
352 .n
= { .min
= 1, .max
= 2 },
353 .m
= { .min
= 79, .max
= 126 },
354 .m1
= { .min
= 12, .max
= 22 },
355 .m2
= { .min
= 5, .max
= 9 },
356 .p
= { .min
= 28, .max
= 112 },
357 .p1
= { .min
= 2, .max
= 8 },
358 .p2
= { .dot_limit
= 225000,
359 .p2_slow
= 14, .p2_fast
= 14 },
360 .find_pll
= intel_g4x_find_best_PLL
,
363 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
364 .dot
= { .min
= 25000, .max
= 350000 },
365 .vco
= { .min
= 1760000, .max
= 3510000 },
366 .n
= { .min
= 1, .max
= 3 },
367 .m
= { .min
= 79, .max
= 126 },
368 .m1
= { .min
= 12, .max
= 22 },
369 .m2
= { .min
= 5, .max
= 9 },
370 .p
= { .min
= 14, .max
= 42 },
371 .p1
= { .min
= 2, .max
= 6 },
372 .p2
= { .dot_limit
= 225000,
373 .p2_slow
= 7, .p2_fast
= 7 },
374 .find_pll
= intel_g4x_find_best_PLL
,
377 static const intel_limit_t intel_limits_ironlake_display_port
= {
378 .dot
= { .min
= 25000, .max
= 350000 },
379 .vco
= { .min
= 1760000, .max
= 3510000},
380 .n
= { .min
= 1, .max
= 2 },
381 .m
= { .min
= 81, .max
= 90 },
382 .m1
= { .min
= 12, .max
= 22 },
383 .m2
= { .min
= 5, .max
= 9 },
384 .p
= { .min
= 10, .max
= 20 },
385 .p1
= { .min
= 1, .max
= 2},
386 .p2
= { .dot_limit
= 0,
387 .p2_slow
= 10, .p2_fast
= 10 },
388 .find_pll
= intel_find_pll_ironlake_dp
,
391 static const intel_limit_t intel_limits_vlv_dac
= {
392 .dot
= { .min
= 25000, .max
= 270000 },
393 .vco
= { .min
= 4000000, .max
= 6000000 },
394 .n
= { .min
= 1, .max
= 7 },
395 .m
= { .min
= 22, .max
= 450 }, /* guess */
396 .m1
= { .min
= 2, .max
= 3 },
397 .m2
= { .min
= 11, .max
= 156 },
398 .p
= { .min
= 10, .max
= 30 },
399 .p1
= { .min
= 2, .max
= 3 },
400 .p2
= { .dot_limit
= 270000,
401 .p2_slow
= 2, .p2_fast
= 20 },
402 .find_pll
= intel_vlv_find_best_pll
,
405 static const intel_limit_t intel_limits_vlv_hdmi
= {
406 .dot
= { .min
= 20000, .max
= 165000 },
407 .vco
= { .min
= 4000000, .max
= 5994000},
408 .n
= { .min
= 1, .max
= 7 },
409 .m
= { .min
= 60, .max
= 300 }, /* guess */
410 .m1
= { .min
= 2, .max
= 3 },
411 .m2
= { .min
= 11, .max
= 156 },
412 .p
= { .min
= 10, .max
= 30 },
413 .p1
= { .min
= 2, .max
= 3 },
414 .p2
= { .dot_limit
= 270000,
415 .p2_slow
= 2, .p2_fast
= 20 },
416 .find_pll
= intel_vlv_find_best_pll
,
419 static const intel_limit_t intel_limits_vlv_dp
= {
420 .dot
= { .min
= 25000, .max
= 270000 },
421 .vco
= { .min
= 4000000, .max
= 6000000 },
422 .n
= { .min
= 1, .max
= 7 },
423 .m
= { .min
= 22, .max
= 450 },
424 .m1
= { .min
= 2, .max
= 3 },
425 .m2
= { .min
= 11, .max
= 156 },
426 .p
= { .min
= 10, .max
= 30 },
427 .p1
= { .min
= 2, .max
= 3 },
428 .p2
= { .dot_limit
= 270000,
429 .p2_slow
= 2, .p2_fast
= 20 },
430 .find_pll
= intel_vlv_find_best_pll
,
433 u32
intel_dpio_read(struct drm_i915_private
*dev_priv
, int reg
)
435 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
437 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
442 I915_WRITE(DPIO_REG
, reg
);
443 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_READ
| DPIO_PORTID
|
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
450 return I915_READ(DPIO_DATA
);
453 static void intel_dpio_write(struct drm_i915_private
*dev_priv
, int reg
,
456 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
458 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
459 DRM_ERROR("DPIO idle wait timed out\n");
463 I915_WRITE(DPIO_DATA
, val
);
464 I915_WRITE(DPIO_REG
, reg
);
465 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_WRITE
| DPIO_PORTID
|
467 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100))
468 DRM_ERROR("DPIO write wait timed out\n");
471 static void vlv_init_dpio(struct drm_device
*dev
)
473 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
475 /* Reset the DPIO config */
476 I915_WRITE(DPIO_CTL
, 0);
477 POSTING_READ(DPIO_CTL
);
478 I915_WRITE(DPIO_CTL
, 1);
479 POSTING_READ(DPIO_CTL
);
482 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
485 struct drm_device
*dev
= crtc
->dev
;
486 const intel_limit_t
*limit
;
488 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
489 if (intel_is_dual_link_lvds(dev
)) {
490 if (refclk
== 100000)
491 limit
= &intel_limits_ironlake_dual_lvds_100m
;
493 limit
= &intel_limits_ironlake_dual_lvds
;
495 if (refclk
== 100000)
496 limit
= &intel_limits_ironlake_single_lvds_100m
;
498 limit
= &intel_limits_ironlake_single_lvds
;
500 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
501 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
502 limit
= &intel_limits_ironlake_display_port
;
504 limit
= &intel_limits_ironlake_dac
;
509 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
511 struct drm_device
*dev
= crtc
->dev
;
512 const intel_limit_t
*limit
;
514 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
515 if (intel_is_dual_link_lvds(dev
))
516 limit
= &intel_limits_g4x_dual_channel_lvds
;
518 limit
= &intel_limits_g4x_single_channel_lvds
;
519 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
520 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
521 limit
= &intel_limits_g4x_hdmi
;
522 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
523 limit
= &intel_limits_g4x_sdvo
;
524 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
525 limit
= &intel_limits_g4x_display_port
;
526 } else /* The option is for other outputs */
527 limit
= &intel_limits_i9xx_sdvo
;
532 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
534 struct drm_device
*dev
= crtc
->dev
;
535 const intel_limit_t
*limit
;
537 if (HAS_PCH_SPLIT(dev
))
538 limit
= intel_ironlake_limit(crtc
, refclk
);
539 else if (IS_G4X(dev
)) {
540 limit
= intel_g4x_limit(crtc
);
541 } else if (IS_PINEVIEW(dev
)) {
542 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
543 limit
= &intel_limits_pineview_lvds
;
545 limit
= &intel_limits_pineview_sdvo
;
546 } else if (IS_VALLEYVIEW(dev
)) {
547 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
))
548 limit
= &intel_limits_vlv_dac
;
549 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
550 limit
= &intel_limits_vlv_hdmi
;
552 limit
= &intel_limits_vlv_dp
;
553 } else if (!IS_GEN2(dev
)) {
554 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
555 limit
= &intel_limits_i9xx_lvds
;
557 limit
= &intel_limits_i9xx_sdvo
;
559 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
560 limit
= &intel_limits_i8xx_lvds
;
562 limit
= &intel_limits_i8xx_dvo
;
567 /* m1 is reserved as 0 in Pineview, n is a ring counter */
568 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
570 clock
->m
= clock
->m2
+ 2;
571 clock
->p
= clock
->p1
* clock
->p2
;
572 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
573 clock
->dot
= clock
->vco
/ clock
->p
;
576 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
578 if (IS_PINEVIEW(dev
)) {
579 pineview_clock(refclk
, clock
);
582 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
583 clock
->p
= clock
->p1
* clock
->p2
;
584 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
585 clock
->dot
= clock
->vco
/ clock
->p
;
589 * Returns whether any output on the specified pipe is of the specified type
591 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
593 struct drm_device
*dev
= crtc
->dev
;
594 struct intel_encoder
*encoder
;
596 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
597 if (encoder
->type
== type
)
603 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
609 static bool intel_PLL_is_valid(struct drm_device
*dev
,
610 const intel_limit_t
*limit
,
611 const intel_clock_t
*clock
)
613 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
614 INTELPllInvalid("p1 out of range\n");
615 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
616 INTELPllInvalid("p out of range\n");
617 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
618 INTELPllInvalid("m2 out of range\n");
619 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
620 INTELPllInvalid("m1 out of range\n");
621 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
622 INTELPllInvalid("m1 <= m2\n");
623 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
624 INTELPllInvalid("m out of range\n");
625 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
626 INTELPllInvalid("n out of range\n");
627 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
628 INTELPllInvalid("vco out of range\n");
629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
632 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
633 INTELPllInvalid("dot out of range\n");
639 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
640 int target
, int refclk
, intel_clock_t
*match_clock
,
641 intel_clock_t
*best_clock
)
644 struct drm_device
*dev
= crtc
->dev
;
648 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
654 if (intel_is_dual_link_lvds(dev
))
655 clock
.p2
= limit
->p2
.p2_fast
;
657 clock
.p2
= limit
->p2
.p2_slow
;
659 if (target
< limit
->p2
.dot_limit
)
660 clock
.p2
= limit
->p2
.p2_slow
;
662 clock
.p2
= limit
->p2
.p2_fast
;
665 memset(best_clock
, 0, sizeof(*best_clock
));
667 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
669 for (clock
.m2
= limit
->m2
.min
;
670 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
671 /* m1 is always 0 in Pineview */
672 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
674 for (clock
.n
= limit
->n
.min
;
675 clock
.n
<= limit
->n
.max
; clock
.n
++) {
676 for (clock
.p1
= limit
->p1
.min
;
677 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
680 intel_clock(dev
, refclk
, &clock
);
681 if (!intel_PLL_is_valid(dev
, limit
,
685 clock
.p
!= match_clock
->p
)
688 this_err
= abs(clock
.dot
- target
);
689 if (this_err
< err
) {
698 return (err
!= target
);
702 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
703 int target
, int refclk
, intel_clock_t
*match_clock
,
704 intel_clock_t
*best_clock
)
706 struct drm_device
*dev
= crtc
->dev
;
710 /* approximately equals target * 0.00585 */
711 int err_most
= (target
>> 8) + (target
>> 9);
714 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
717 if (HAS_PCH_SPLIT(dev
))
721 if (intel_is_dual_link_lvds(dev
))
722 clock
.p2
= limit
->p2
.p2_fast
;
724 clock
.p2
= limit
->p2
.p2_slow
;
726 if (target
< limit
->p2
.dot_limit
)
727 clock
.p2
= limit
->p2
.p2_slow
;
729 clock
.p2
= limit
->p2
.p2_fast
;
732 memset(best_clock
, 0, sizeof(*best_clock
));
733 max_n
= limit
->n
.max
;
734 /* based on hardware requirement, prefer smaller n to precision */
735 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
736 /* based on hardware requirement, prefere larger m1,m2 */
737 for (clock
.m1
= limit
->m1
.max
;
738 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
739 for (clock
.m2
= limit
->m2
.max
;
740 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
741 for (clock
.p1
= limit
->p1
.max
;
742 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
745 intel_clock(dev
, refclk
, &clock
);
746 if (!intel_PLL_is_valid(dev
, limit
,
750 clock
.p
!= match_clock
->p
)
753 this_err
= abs(clock
.dot
- target
);
754 if (this_err
< err_most
) {
768 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
769 int target
, int refclk
, intel_clock_t
*match_clock
,
770 intel_clock_t
*best_clock
)
772 struct drm_device
*dev
= crtc
->dev
;
775 if (target
< 200000) {
788 intel_clock(dev
, refclk
, &clock
);
789 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
793 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
795 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
796 int target
, int refclk
, intel_clock_t
*match_clock
,
797 intel_clock_t
*best_clock
)
800 if (target
< 200000) {
813 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
814 clock
.p
= (clock
.p1
* clock
.p2
);
815 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
817 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
821 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
822 int target
, int refclk
, intel_clock_t
*match_clock
,
823 intel_clock_t
*best_clock
)
825 u32 p1
, p2
, m1
, m2
, vco
, bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
827 u32 updrate
, minupdate
, fracbits
, p
;
828 unsigned long bestppm
, ppm
, absppm
;
832 dotclk
= target
* 1000;
835 fastclk
= dotclk
/ (2*100);
839 n
= p
= p1
= p2
= m
= m1
= m2
= vco
= bestn
= 0;
840 bestm1
= bestm2
= bestp1
= bestp2
= 0;
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (n
= limit
->n
.min
; n
<= ((refclk
) / minupdate
); n
++) {
844 updrate
= refclk
/ n
;
845 for (p1
= limit
->p1
.max
; p1
> limit
->p1
.min
; p1
--) {
846 for (p2
= limit
->p2
.p2_fast
+1; p2
> 0; p2
--) {
850 /* based on hardware requirement, prefer bigger m1,m2 values */
851 for (m1
= limit
->m1
.min
; m1
<= limit
->m1
.max
; m1
++) {
852 m2
= (((2*(fastclk
* p
* n
/ m1
)) +
853 refclk
) / (2*refclk
));
856 if (vco
>= limit
->vco
.min
&& vco
< limit
->vco
.max
) {
857 ppm
= 1000000 * ((vco
/ p
) - fastclk
) / fastclk
;
858 absppm
= (ppm
> 0) ? ppm
: (-ppm
);
859 if (absppm
< 100 && ((p1
* p2
) > (bestp1
* bestp2
))) {
863 if (absppm
< bestppm
- 10) {
880 best_clock
->n
= bestn
;
881 best_clock
->m1
= bestm1
;
882 best_clock
->m2
= bestm2
;
883 best_clock
->p1
= bestp1
;
884 best_clock
->p2
= bestp2
;
889 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
892 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
893 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
895 return intel_crtc
->cpu_transcoder
;
898 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
900 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
901 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
903 frame
= I915_READ(frame_reg
);
905 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
906 DRM_DEBUG_KMS("vblank wait timed out\n");
910 * intel_wait_for_vblank - wait for vblank on a given pipe
912 * @pipe: pipe to wait for
914 * Wait for vblank to occur on a given pipe. Needed for various bits of
917 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
919 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
920 int pipestat_reg
= PIPESTAT(pipe
);
922 if (INTEL_INFO(dev
)->gen
>= 5) {
923 ironlake_wait_for_vblank(dev
, pipe
);
927 /* Clear existing vblank status. Note this will clear any other
928 * sticky status fields as well.
930 * This races with i915_driver_irq_handler() with the result
931 * that either function could miss a vblank event. Here it is not
932 * fatal, as we will either wait upon the next vblank interrupt or
933 * timeout. Generally speaking intel_wait_for_vblank() is only
934 * called during modeset at which time the GPU should be idle and
935 * should *not* be performing page flips and thus not waiting on
937 * Currently, the result of us stealing a vblank from the irq
938 * handler is that a single frame will be skipped during swapbuffers.
940 I915_WRITE(pipestat_reg
,
941 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
943 /* Wait for vblank interrupt bit to set */
944 if (wait_for(I915_READ(pipestat_reg
) &
945 PIPE_VBLANK_INTERRUPT_STATUS
,
947 DRM_DEBUG_KMS("vblank wait timed out\n");
951 * intel_wait_for_pipe_off - wait for pipe to turn off
953 * @pipe: pipe to wait for
955 * After disabling a pipe, we can't wait for vblank in the usual way,
956 * spinning on the vblank interrupt status bit, since we won't actually
957 * see an interrupt when the pipe is disabled.
960 * wait for the pipe register state bit to turn off
963 * wait for the display line value to settle (it usually
964 * ends up stopping at the start of the next frame).
967 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
969 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
970 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
973 if (INTEL_INFO(dev
)->gen
>= 4) {
974 int reg
= PIPECONF(cpu_transcoder
);
976 /* Wait for the Pipe State to go off */
977 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
979 WARN(1, "pipe_off wait timed out\n");
981 u32 last_line
, line_mask
;
982 int reg
= PIPEDSL(pipe
);
983 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
986 line_mask
= DSL_LINEMASK_GEN2
;
988 line_mask
= DSL_LINEMASK_GEN3
;
990 /* Wait for the display line to settle */
992 last_line
= I915_READ(reg
) & line_mask
;
994 } while (((I915_READ(reg
) & line_mask
) != last_line
) &&
995 time_after(timeout
, jiffies
));
996 if (time_after(jiffies
, timeout
))
997 WARN(1, "pipe_off wait timed out\n");
1002 * ibx_digital_port_connected - is the specified port connected?
1003 * @dev_priv: i915 private structure
1004 * @port: the port to test
1006 * Returns true if @port is connected, false otherwise.
1008 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
1009 struct intel_digital_port
*port
)
1013 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1014 switch(port
->port
) {
1016 bit
= SDE_PORTB_HOTPLUG
;
1019 bit
= SDE_PORTC_HOTPLUG
;
1022 bit
= SDE_PORTD_HOTPLUG
;
1028 switch(port
->port
) {
1030 bit
= SDE_PORTB_HOTPLUG_CPT
;
1033 bit
= SDE_PORTC_HOTPLUG_CPT
;
1036 bit
= SDE_PORTD_HOTPLUG_CPT
;
1043 return I915_READ(SDEISR
) & bit
;
1046 static const char *state_string(bool enabled
)
1048 return enabled
? "on" : "off";
1051 /* Only for pre-ILK configs */
1052 static void assert_pll(struct drm_i915_private
*dev_priv
,
1053 enum pipe pipe
, bool state
)
1060 val
= I915_READ(reg
);
1061 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1062 WARN(cur_state
!= state
,
1063 "PLL state assertion failure (expected %s, current %s)\n",
1064 state_string(state
), state_string(cur_state
));
1066 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1070 static void assert_pch_pll(struct drm_i915_private
*dev_priv
,
1071 struct intel_pch_pll
*pll
,
1072 struct intel_crtc
*crtc
,
1078 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1079 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1084 "asserting PCH PLL %s with no PLL\n", state_string(state
)))
1087 val
= I915_READ(pll
->pll_reg
);
1088 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1089 WARN(cur_state
!= state
,
1090 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1091 pll
->pll_reg
, state_string(state
), state_string(cur_state
), val
);
1093 /* Make sure the selected PLL is correctly attached to the transcoder */
1094 if (crtc
&& HAS_PCH_CPT(dev_priv
->dev
)) {
1097 pch_dpll
= I915_READ(PCH_DPLL_SEL
);
1098 cur_state
= pll
->pll_reg
== _PCH_DPLL_B
;
1099 if (!WARN(((pch_dpll
>> (4 * crtc
->pipe
)) & 1) != cur_state
,
1100 "PLL[%d] not attached to this transcoder %d: %08x\n",
1101 cur_state
, crtc
->pipe
, pch_dpll
)) {
1102 cur_state
= !!(val
>> (4*crtc
->pipe
+ 3));
1103 WARN(cur_state
!= state
,
1104 "PLL[%d] not %s on this transcoder %d: %08x\n",
1105 pll
->pll_reg
== _PCH_DPLL_B
,
1106 state_string(state
),
1112 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1113 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1115 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1116 enum pipe pipe
, bool state
)
1121 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1124 if (HAS_DDI(dev_priv
->dev
)) {
1125 /* DDI does not have a specific FDI_TX register */
1126 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1127 val
= I915_READ(reg
);
1128 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1130 reg
= FDI_TX_CTL(pipe
);
1131 val
= I915_READ(reg
);
1132 cur_state
= !!(val
& FDI_TX_ENABLE
);
1134 WARN(cur_state
!= state
,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state
), state_string(cur_state
));
1138 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1141 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1142 enum pipe pipe
, bool state
)
1148 reg
= FDI_RX_CTL(pipe
);
1149 val
= I915_READ(reg
);
1150 cur_state
= !!(val
& FDI_RX_ENABLE
);
1151 WARN(cur_state
!= state
,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state
), state_string(cur_state
));
1155 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1158 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1164 /* ILK FDI PLL is always enabled */
1165 if (dev_priv
->info
->gen
== 5)
1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1169 if (HAS_DDI(dev_priv
->dev
))
1172 reg
= FDI_TX_CTL(pipe
);
1173 val
= I915_READ(reg
);
1174 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1177 static void assert_fdi_rx_pll_enabled(struct drm_i915_private
*dev_priv
,
1183 reg
= FDI_RX_CTL(pipe
);
1184 val
= I915_READ(reg
);
1185 WARN(!(val
& FDI_RX_PLL_ENABLE
), "FDI RX PLL assertion failure, should be active but is disabled\n");
1188 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1191 int pp_reg
, lvds_reg
;
1193 enum pipe panel_pipe
= PIPE_A
;
1196 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1197 pp_reg
= PCH_PP_CONTROL
;
1198 lvds_reg
= PCH_LVDS
;
1200 pp_reg
= PP_CONTROL
;
1204 val
= I915_READ(pp_reg
);
1205 if (!(val
& PANEL_POWER_ON
) ||
1206 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1209 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1210 panel_pipe
= PIPE_B
;
1212 WARN(panel_pipe
== pipe
&& locked
,
1213 "panel assertion failure, pipe %c regs locked\n",
1217 void assert_pipe(struct drm_i915_private
*dev_priv
,
1218 enum pipe pipe
, bool state
)
1223 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1226 /* if we need the pipe A quirk it must be always on */
1227 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1230 if (IS_HASWELL(dev_priv
->dev
) && cpu_transcoder
!= TRANSCODER_EDP
&&
1231 !(I915_READ(HSW_PWR_WELL_DRIVER
) & HSW_PWR_WELL_ENABLE
)) {
1234 reg
= PIPECONF(cpu_transcoder
);
1235 val
= I915_READ(reg
);
1236 cur_state
= !!(val
& PIPECONF_ENABLE
);
1239 WARN(cur_state
!= state
,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
1241 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1244 static void assert_plane(struct drm_i915_private
*dev_priv
,
1245 enum plane plane
, bool state
)
1251 reg
= DSPCNTR(plane
);
1252 val
= I915_READ(reg
);
1253 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1254 WARN(cur_state
!= state
,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane
), state_string(state
), state_string(cur_state
));
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1262 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1269 /* Planes are fixed to pipes on ILK+ */
1270 if (HAS_PCH_SPLIT(dev_priv
->dev
) || IS_VALLEYVIEW(dev_priv
->dev
)) {
1271 reg
= DSPCNTR(pipe
);
1272 val
= I915_READ(reg
);
1273 WARN((val
& DISPLAY_PLANE_ENABLE
),
1274 "plane %c assertion failure, should be disabled but not\n",
1279 /* Need to check both planes against the pipe */
1280 for (i
= 0; i
< 2; i
++) {
1282 val
= I915_READ(reg
);
1283 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1284 DISPPLANE_SEL_PIPE_SHIFT
;
1285 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1286 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1287 plane_name(i
), pipe_name(pipe
));
1291 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1296 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1297 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1301 val
= I915_READ(PCH_DREF_CONTROL
);
1302 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1303 DREF_SUPERSPREAD_SOURCE_MASK
));
1304 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1307 static void assert_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1314 reg
= TRANSCONF(pipe
);
1315 val
= I915_READ(reg
);
1316 enabled
= !!(val
& TRANS_ENABLE
);
1318 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1322 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1323 enum pipe pipe
, u32 port_sel
, u32 val
)
1325 if ((val
& DP_PORT_EN
) == 0)
1328 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1329 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1330 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1331 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1334 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1340 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1341 enum pipe pipe
, u32 val
)
1343 if ((val
& SDVO_ENABLE
) == 0)
1346 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1347 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1350 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1356 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1357 enum pipe pipe
, u32 val
)
1359 if ((val
& LVDS_PORT_EN
) == 0)
1362 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1363 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1366 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1372 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1373 enum pipe pipe
, u32 val
)
1375 if ((val
& ADPA_DAC_ENABLE
) == 0)
1377 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1378 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1381 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1387 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1388 enum pipe pipe
, int reg
, u32 port_sel
)
1390 u32 val
= I915_READ(reg
);
1391 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1392 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1393 reg
, pipe_name(pipe
));
1395 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1396 && (val
& DP_PIPEB_SELECT
),
1397 "IBX PCH dp port still using transcoder B\n");
1400 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1401 enum pipe pipe
, int reg
)
1403 u32 val
= I915_READ(reg
);
1404 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1405 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1406 reg
, pipe_name(pipe
));
1408 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1409 && (val
& SDVO_PIPE_B_SELECT
),
1410 "IBX PCH hdmi port still using transcoder B\n");
1413 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1419 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1420 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1421 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1424 val
= I915_READ(reg
);
1425 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1426 "PCH VGA enabled on transcoder %c, should be disabled\n",
1430 val
= I915_READ(reg
);
1431 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1432 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1435 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1436 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1437 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1441 * intel_enable_pll - enable a PLL
1442 * @dev_priv: i915 private structure
1443 * @pipe: pipe PLL to enable
1445 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1446 * make sure the PLL reg is writable first though, since the panel write
1447 * protect mechanism may be enabled.
1449 * Note! This is for pre-ILK only.
1451 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1453 static void intel_enable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1458 /* No really, not for ILK+ */
1459 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
) && dev_priv
->info
->gen
>= 5);
1461 /* PLL is protected by panel, make sure we can write it */
1462 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1463 assert_panel_unlocked(dev_priv
, pipe
);
1466 val
= I915_READ(reg
);
1467 val
|= DPLL_VCO_ENABLE
;
1469 /* We do this three times for luck */
1470 I915_WRITE(reg
, val
);
1472 udelay(150); /* wait for warmup */
1473 I915_WRITE(reg
, val
);
1475 udelay(150); /* wait for warmup */
1476 I915_WRITE(reg
, val
);
1478 udelay(150); /* wait for warmup */
1482 * intel_disable_pll - disable a PLL
1483 * @dev_priv: i915 private structure
1484 * @pipe: pipe PLL to disable
1486 * Disable the PLL for @pipe, making sure the pipe is off first.
1488 * Note! This is for pre-ILK only.
1490 static void intel_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1495 /* Don't disable pipe A or pipe A PLLs if needed */
1496 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1499 /* Make sure the pipe isn't still relying on us */
1500 assert_pipe_disabled(dev_priv
, pipe
);
1503 val
= I915_READ(reg
);
1504 val
&= ~DPLL_VCO_ENABLE
;
1505 I915_WRITE(reg
, val
);
1511 intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
1512 enum intel_sbi_destination destination
)
1516 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
1518 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1520 DRM_ERROR("timeout waiting for SBI to become ready\n");
1524 I915_WRITE(SBI_ADDR
, (reg
<< 16));
1525 I915_WRITE(SBI_DATA
, value
);
1527 if (destination
== SBI_ICLK
)
1528 tmp
= SBI_CTL_DEST_ICLK
| SBI_CTL_OP_CRWR
;
1530 tmp
= SBI_CTL_DEST_MPHY
| SBI_CTL_OP_IOWR
;
1531 I915_WRITE(SBI_CTL_STAT
, SBI_BUSY
| tmp
);
1533 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1535 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1541 intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
1542 enum intel_sbi_destination destination
)
1545 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
1547 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1549 DRM_ERROR("timeout waiting for SBI to become ready\n");
1553 I915_WRITE(SBI_ADDR
, (reg
<< 16));
1555 if (destination
== SBI_ICLK
)
1556 value
= SBI_CTL_DEST_ICLK
| SBI_CTL_OP_CRRD
;
1558 value
= SBI_CTL_DEST_MPHY
| SBI_CTL_OP_IORD
;
1559 I915_WRITE(SBI_CTL_STAT
, value
| SBI_BUSY
);
1561 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1563 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1567 return I915_READ(SBI_DATA
);
1571 * ironlake_enable_pch_pll - enable PCH PLL
1572 * @dev_priv: i915 private structure
1573 * @pipe: pipe PLL to enable
1575 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1576 * drives the transcoder clock.
1578 static void ironlake_enable_pch_pll(struct intel_crtc
*intel_crtc
)
1580 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1581 struct intel_pch_pll
*pll
;
1585 /* PCH PLLs only available on ILK, SNB and IVB */
1586 BUG_ON(dev_priv
->info
->gen
< 5);
1587 pll
= intel_crtc
->pch_pll
;
1591 if (WARN_ON(pll
->refcount
== 0))
1594 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1595 pll
->pll_reg
, pll
->active
, pll
->on
,
1596 intel_crtc
->base
.base
.id
);
1598 /* PCH refclock must be enabled first */
1599 assert_pch_refclk_enabled(dev_priv
);
1601 if (pll
->active
++ && pll
->on
) {
1602 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1606 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll
->pll_reg
);
1609 val
= I915_READ(reg
);
1610 val
|= DPLL_VCO_ENABLE
;
1611 I915_WRITE(reg
, val
);
1618 static void intel_disable_pch_pll(struct intel_crtc
*intel_crtc
)
1620 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1621 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
1625 /* PCH only available on ILK+ */
1626 BUG_ON(dev_priv
->info
->gen
< 5);
1630 if (WARN_ON(pll
->refcount
== 0))
1633 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1634 pll
->pll_reg
, pll
->active
, pll
->on
,
1635 intel_crtc
->base
.base
.id
);
1637 if (WARN_ON(pll
->active
== 0)) {
1638 assert_pch_pll_disabled(dev_priv
, pll
, NULL
);
1642 if (--pll
->active
) {
1643 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1647 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll
->pll_reg
);
1649 /* Make sure transcoder isn't still depending on us */
1650 assert_transcoder_disabled(dev_priv
, intel_crtc
->pipe
);
1653 val
= I915_READ(reg
);
1654 val
&= ~DPLL_VCO_ENABLE
;
1655 I915_WRITE(reg
, val
);
1662 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1665 struct drm_device
*dev
= dev_priv
->dev
;
1666 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1667 uint32_t reg
, val
, pipeconf_val
;
1669 /* PCH only available on ILK+ */
1670 BUG_ON(dev_priv
->info
->gen
< 5);
1672 /* Make sure PCH DPLL is enabled */
1673 assert_pch_pll_enabled(dev_priv
,
1674 to_intel_crtc(crtc
)->pch_pll
,
1675 to_intel_crtc(crtc
));
1677 /* FDI must be feeding us bits for PCH ports */
1678 assert_fdi_tx_enabled(dev_priv
, pipe
);
1679 assert_fdi_rx_enabled(dev_priv
, pipe
);
1681 if (HAS_PCH_CPT(dev
)) {
1682 /* Workaround: Set the timing override bit before enabling the
1683 * pch transcoder. */
1684 reg
= TRANS_CHICKEN2(pipe
);
1685 val
= I915_READ(reg
);
1686 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1687 I915_WRITE(reg
, val
);
1690 reg
= TRANSCONF(pipe
);
1691 val
= I915_READ(reg
);
1692 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1694 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1696 * make the BPC in transcoder be consistent with
1697 * that in pipeconf reg.
1699 val
&= ~PIPECONF_BPC_MASK
;
1700 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1703 val
&= ~TRANS_INTERLACE_MASK
;
1704 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1705 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1706 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1707 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1709 val
|= TRANS_INTERLACED
;
1711 val
|= TRANS_PROGRESSIVE
;
1713 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1714 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1715 DRM_ERROR("failed to enable transcoder %d\n", pipe
);
1718 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1719 enum transcoder cpu_transcoder
)
1721 u32 val
, pipeconf_val
;
1723 /* PCH only available on ILK+ */
1724 BUG_ON(dev_priv
->info
->gen
< 5);
1726 /* FDI must be feeding us bits for PCH ports */
1727 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1728 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1730 /* Workaround: set timing override bit. */
1731 val
= I915_READ(_TRANSA_CHICKEN2
);
1732 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1733 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1736 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1738 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1739 PIPECONF_INTERLACED_ILK
)
1740 val
|= TRANS_INTERLACED
;
1742 val
|= TRANS_PROGRESSIVE
;
1744 I915_WRITE(TRANSCONF(TRANSCODER_A
), val
);
1745 if (wait_for(I915_READ(_TRANSACONF
) & TRANS_STATE_ENABLE
, 100))
1746 DRM_ERROR("Failed to enable PCH transcoder\n");
1749 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1752 struct drm_device
*dev
= dev_priv
->dev
;
1755 /* FDI relies on the transcoder */
1756 assert_fdi_tx_disabled(dev_priv
, pipe
);
1757 assert_fdi_rx_disabled(dev_priv
, pipe
);
1759 /* Ports must be off as well */
1760 assert_pch_ports_disabled(dev_priv
, pipe
);
1762 reg
= TRANSCONF(pipe
);
1763 val
= I915_READ(reg
);
1764 val
&= ~TRANS_ENABLE
;
1765 I915_WRITE(reg
, val
);
1766 /* wait for PCH transcoder off, transcoder state */
1767 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1768 DRM_ERROR("failed to disable transcoder %d\n", pipe
);
1770 if (!HAS_PCH_IBX(dev
)) {
1771 /* Workaround: Clear the timing override chicken bit again. */
1772 reg
= TRANS_CHICKEN2(pipe
);
1773 val
= I915_READ(reg
);
1774 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1775 I915_WRITE(reg
, val
);
1779 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1783 val
= I915_READ(_TRANSACONF
);
1784 val
&= ~TRANS_ENABLE
;
1785 I915_WRITE(_TRANSACONF
, val
);
1786 /* wait for PCH transcoder off, transcoder state */
1787 if (wait_for((I915_READ(_TRANSACONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1788 DRM_ERROR("Failed to disable PCH transcoder\n");
1790 /* Workaround: clear timing override bit. */
1791 val
= I915_READ(_TRANSA_CHICKEN2
);
1792 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1793 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1797 * intel_enable_pipe - enable a pipe, asserting requirements
1798 * @dev_priv: i915 private structure
1799 * @pipe: pipe to enable
1800 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1802 * Enable @pipe, making sure that various hardware specific requirements
1803 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1805 * @pipe should be %PIPE_A or %PIPE_B.
1807 * Will wait until the pipe is actually running (i.e. first vblank) before
1810 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1813 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1815 enum pipe pch_transcoder
;
1819 if (HAS_PCH_LPT(dev_priv
->dev
))
1820 pch_transcoder
= TRANSCODER_A
;
1822 pch_transcoder
= pipe
;
1825 * A pipe without a PLL won't actually be able to drive bits from
1826 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1829 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1830 assert_pll_enabled(dev_priv
, pipe
);
1833 /* if driving the PCH, we need FDI enabled */
1834 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1835 assert_fdi_tx_pll_enabled(dev_priv
,
1836 (enum pipe
) cpu_transcoder
);
1838 /* FIXME: assert CPU port conditions for SNB+ */
1841 reg
= PIPECONF(cpu_transcoder
);
1842 val
= I915_READ(reg
);
1843 if (val
& PIPECONF_ENABLE
)
1846 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1847 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1851 * intel_disable_pipe - disable a pipe, asserting requirements
1852 * @dev_priv: i915 private structure
1853 * @pipe: pipe to disable
1855 * Disable @pipe, making sure that various hardware specific requirements
1856 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1858 * @pipe should be %PIPE_A or %PIPE_B.
1860 * Will wait until the pipe has shut down before returning.
1862 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1865 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1871 * Make sure planes won't keep trying to pump pixels to us,
1872 * or we might hang the display.
1874 assert_planes_disabled(dev_priv
, pipe
);
1876 /* Don't disable pipe A or pipe A PLLs if needed */
1877 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1880 reg
= PIPECONF(cpu_transcoder
);
1881 val
= I915_READ(reg
);
1882 if ((val
& PIPECONF_ENABLE
) == 0)
1885 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1886 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1890 * Plane regs are double buffered, going from enabled->disabled needs a
1891 * trigger in order to latch. The display address reg provides this.
1893 void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1896 if (dev_priv
->info
->gen
>= 4)
1897 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1899 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1903 * intel_enable_plane - enable a display plane on a given pipe
1904 * @dev_priv: i915 private structure
1905 * @plane: plane to enable
1906 * @pipe: pipe being fed
1908 * Enable @plane on @pipe, making sure that @pipe is running first.
1910 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1911 enum plane plane
, enum pipe pipe
)
1916 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1917 assert_pipe_enabled(dev_priv
, pipe
);
1919 reg
= DSPCNTR(plane
);
1920 val
= I915_READ(reg
);
1921 if (val
& DISPLAY_PLANE_ENABLE
)
1924 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1925 intel_flush_display_plane(dev_priv
, plane
);
1926 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1930 * intel_disable_plane - disable a display plane
1931 * @dev_priv: i915 private structure
1932 * @plane: plane to disable
1933 * @pipe: pipe consuming the data
1935 * Disable @plane; should be an independent operation.
1937 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1938 enum plane plane
, enum pipe pipe
)
1943 reg
= DSPCNTR(plane
);
1944 val
= I915_READ(reg
);
1945 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1948 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1949 intel_flush_display_plane(dev_priv
, plane
);
1950 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1954 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1955 struct drm_i915_gem_object
*obj
,
1956 struct intel_ring_buffer
*pipelined
)
1958 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1962 switch (obj
->tiling_mode
) {
1963 case I915_TILING_NONE
:
1964 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1965 alignment
= 128 * 1024;
1966 else if (INTEL_INFO(dev
)->gen
>= 4)
1967 alignment
= 4 * 1024;
1969 alignment
= 64 * 1024;
1972 /* pin() will align the object as required by fence */
1976 /* FIXME: Is this true? */
1977 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1983 dev_priv
->mm
.interruptible
= false;
1984 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
1986 goto err_interruptible
;
1988 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1989 * fence, whereas 965+ only requires a fence if using
1990 * framebuffer compression. For simplicity, we always install
1991 * a fence as the cost is not that onerous.
1993 ret
= i915_gem_object_get_fence(obj
);
1997 i915_gem_object_pin_fence(obj
);
1999 dev_priv
->mm
.interruptible
= true;
2003 i915_gem_object_unpin(obj
);
2005 dev_priv
->mm
.interruptible
= true;
2009 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
2011 i915_gem_object_unpin_fence(obj
);
2012 i915_gem_object_unpin(obj
);
2015 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2016 * is assumed to be a power-of-two. */
2017 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2018 unsigned int tiling_mode
,
2022 if (tiling_mode
!= I915_TILING_NONE
) {
2023 unsigned int tile_rows
, tiles
;
2028 tiles
= *x
/ (512/cpp
);
2031 return tile_rows
* pitch
* 8 + tiles
* 4096;
2033 unsigned int offset
;
2035 offset
= *y
* pitch
+ *x
* cpp
;
2037 *x
= (offset
& 4095) / cpp
;
2038 return offset
& -4096;
2042 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2045 struct drm_device
*dev
= crtc
->dev
;
2046 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2047 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2048 struct intel_framebuffer
*intel_fb
;
2049 struct drm_i915_gem_object
*obj
;
2050 int plane
= intel_crtc
->plane
;
2051 unsigned long linear_offset
;
2060 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2064 intel_fb
= to_intel_framebuffer(fb
);
2065 obj
= intel_fb
->obj
;
2067 reg
= DSPCNTR(plane
);
2068 dspcntr
= I915_READ(reg
);
2069 /* Mask out pixel format bits in case we change it */
2070 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2071 switch (fb
->pixel_format
) {
2073 dspcntr
|= DISPPLANE_8BPP
;
2075 case DRM_FORMAT_XRGB1555
:
2076 case DRM_FORMAT_ARGB1555
:
2077 dspcntr
|= DISPPLANE_BGRX555
;
2079 case DRM_FORMAT_RGB565
:
2080 dspcntr
|= DISPPLANE_BGRX565
;
2082 case DRM_FORMAT_XRGB8888
:
2083 case DRM_FORMAT_ARGB8888
:
2084 dspcntr
|= DISPPLANE_BGRX888
;
2086 case DRM_FORMAT_XBGR8888
:
2087 case DRM_FORMAT_ABGR8888
:
2088 dspcntr
|= DISPPLANE_RGBX888
;
2090 case DRM_FORMAT_XRGB2101010
:
2091 case DRM_FORMAT_ARGB2101010
:
2092 dspcntr
|= DISPPLANE_BGRX101010
;
2094 case DRM_FORMAT_XBGR2101010
:
2095 case DRM_FORMAT_ABGR2101010
:
2096 dspcntr
|= DISPPLANE_RGBX101010
;
2099 DRM_ERROR("Unknown pixel format 0x%08x\n", fb
->pixel_format
);
2103 if (INTEL_INFO(dev
)->gen
>= 4) {
2104 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2105 dspcntr
|= DISPPLANE_TILED
;
2107 dspcntr
&= ~DISPPLANE_TILED
;
2110 I915_WRITE(reg
, dspcntr
);
2112 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2114 if (INTEL_INFO(dev
)->gen
>= 4) {
2115 intel_crtc
->dspaddr_offset
=
2116 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2117 fb
->bits_per_pixel
/ 8,
2119 linear_offset
-= intel_crtc
->dspaddr_offset
;
2121 intel_crtc
->dspaddr_offset
= linear_offset
;
2124 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2125 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2126 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2127 if (INTEL_INFO(dev
)->gen
>= 4) {
2128 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2129 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2130 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2131 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2133 I915_WRITE(DSPADDR(plane
), obj
->gtt_offset
+ linear_offset
);
2139 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2140 struct drm_framebuffer
*fb
, int x
, int y
)
2142 struct drm_device
*dev
= crtc
->dev
;
2143 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2144 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2145 struct intel_framebuffer
*intel_fb
;
2146 struct drm_i915_gem_object
*obj
;
2147 int plane
= intel_crtc
->plane
;
2148 unsigned long linear_offset
;
2158 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2162 intel_fb
= to_intel_framebuffer(fb
);
2163 obj
= intel_fb
->obj
;
2165 reg
= DSPCNTR(plane
);
2166 dspcntr
= I915_READ(reg
);
2167 /* Mask out pixel format bits in case we change it */
2168 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2169 switch (fb
->pixel_format
) {
2171 dspcntr
|= DISPPLANE_8BPP
;
2173 case DRM_FORMAT_RGB565
:
2174 dspcntr
|= DISPPLANE_BGRX565
;
2176 case DRM_FORMAT_XRGB8888
:
2177 case DRM_FORMAT_ARGB8888
:
2178 dspcntr
|= DISPPLANE_BGRX888
;
2180 case DRM_FORMAT_XBGR8888
:
2181 case DRM_FORMAT_ABGR8888
:
2182 dspcntr
|= DISPPLANE_RGBX888
;
2184 case DRM_FORMAT_XRGB2101010
:
2185 case DRM_FORMAT_ARGB2101010
:
2186 dspcntr
|= DISPPLANE_BGRX101010
;
2188 case DRM_FORMAT_XBGR2101010
:
2189 case DRM_FORMAT_ABGR2101010
:
2190 dspcntr
|= DISPPLANE_RGBX101010
;
2193 DRM_ERROR("Unknown pixel format 0x%08x\n", fb
->pixel_format
);
2197 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2198 dspcntr
|= DISPPLANE_TILED
;
2200 dspcntr
&= ~DISPPLANE_TILED
;
2203 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2205 I915_WRITE(reg
, dspcntr
);
2207 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2208 intel_crtc
->dspaddr_offset
=
2209 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2210 fb
->bits_per_pixel
/ 8,
2212 linear_offset
-= intel_crtc
->dspaddr_offset
;
2214 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2215 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2216 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2217 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2218 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2219 if (IS_HASWELL(dev
)) {
2220 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2222 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2223 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2230 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2232 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2233 int x
, int y
, enum mode_set_atomic state
)
2235 struct drm_device
*dev
= crtc
->dev
;
2236 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2238 if (dev_priv
->display
.disable_fbc
)
2239 dev_priv
->display
.disable_fbc(dev
);
2240 intel_increase_pllclock(crtc
);
2242 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2245 void intel_display_handle_reset(struct drm_device
*dev
)
2247 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2248 struct drm_crtc
*crtc
;
2251 * Flips in the rings have been nuked by the reset,
2252 * so complete all pending flips so that user space
2253 * will get its events and not get stuck.
2255 * Also update the base address of all primary
2256 * planes to the the last fb to make sure we're
2257 * showing the correct fb after a reset.
2259 * Need to make two loops over the crtcs so that we
2260 * don't try to grab a crtc mutex before the
2261 * pending_flip_queue really got woken up.
2264 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2265 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2266 enum plane plane
= intel_crtc
->plane
;
2268 intel_prepare_page_flip(dev
, plane
);
2269 intel_finish_page_flip_plane(dev
, plane
);
2272 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2273 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2275 mutex_lock(&crtc
->mutex
);
2276 if (intel_crtc
->active
)
2277 dev_priv
->display
.update_plane(crtc
, crtc
->fb
,
2279 mutex_unlock(&crtc
->mutex
);
2284 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2286 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2287 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2288 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2291 /* Big Hammer, we also need to ensure that any pending
2292 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2293 * current scanout is retired before unpinning the old
2296 * This should only fail upon a hung GPU, in which case we
2297 * can safely continue.
2299 dev_priv
->mm
.interruptible
= false;
2300 ret
= i915_gem_object_finish_gpu(obj
);
2301 dev_priv
->mm
.interruptible
= was_interruptible
;
2306 static void intel_crtc_update_sarea_pos(struct drm_crtc
*crtc
, int x
, int y
)
2308 struct drm_device
*dev
= crtc
->dev
;
2309 struct drm_i915_master_private
*master_priv
;
2310 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2312 if (!dev
->primary
->master
)
2315 master_priv
= dev
->primary
->master
->driver_priv
;
2316 if (!master_priv
->sarea_priv
)
2319 switch (intel_crtc
->pipe
) {
2321 master_priv
->sarea_priv
->pipeA_x
= x
;
2322 master_priv
->sarea_priv
->pipeA_y
= y
;
2325 master_priv
->sarea_priv
->pipeB_x
= x
;
2326 master_priv
->sarea_priv
->pipeB_y
= y
;
2334 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2335 struct drm_framebuffer
*fb
)
2337 struct drm_device
*dev
= crtc
->dev
;
2338 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2339 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2340 struct drm_framebuffer
*old_fb
;
2345 DRM_ERROR("No FB bound\n");
2349 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2350 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2352 INTEL_INFO(dev
)->num_pipes
);
2356 mutex_lock(&dev
->struct_mutex
);
2357 ret
= intel_pin_and_fence_fb_obj(dev
,
2358 to_intel_framebuffer(fb
)->obj
,
2361 mutex_unlock(&dev
->struct_mutex
);
2362 DRM_ERROR("pin & fence failed\n");
2366 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2368 intel_unpin_fb_obj(to_intel_framebuffer(fb
)->obj
);
2369 mutex_unlock(&dev
->struct_mutex
);
2370 DRM_ERROR("failed to update base address\n");
2380 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2381 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2384 intel_update_fbc(dev
);
2385 mutex_unlock(&dev
->struct_mutex
);
2387 intel_crtc_update_sarea_pos(crtc
, x
, y
);
2392 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2394 struct drm_device
*dev
= crtc
->dev
;
2395 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2396 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2397 int pipe
= intel_crtc
->pipe
;
2400 /* enable normal train */
2401 reg
= FDI_TX_CTL(pipe
);
2402 temp
= I915_READ(reg
);
2403 if (IS_IVYBRIDGE(dev
)) {
2404 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2405 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2407 temp
&= ~FDI_LINK_TRAIN_NONE
;
2408 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2410 I915_WRITE(reg
, temp
);
2412 reg
= FDI_RX_CTL(pipe
);
2413 temp
= I915_READ(reg
);
2414 if (HAS_PCH_CPT(dev
)) {
2415 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2416 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2418 temp
&= ~FDI_LINK_TRAIN_NONE
;
2419 temp
|= FDI_LINK_TRAIN_NONE
;
2421 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2423 /* wait one idle pattern time */
2427 /* IVB wants error correction enabled */
2428 if (IS_IVYBRIDGE(dev
))
2429 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2430 FDI_FE_ERRC_ENABLE
);
2433 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2435 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2436 struct intel_crtc
*pipe_B_crtc
=
2437 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2438 struct intel_crtc
*pipe_C_crtc
=
2439 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2442 /* When everything is off disable fdi C so that we could enable fdi B
2443 * with all lanes. XXX: This misses the case where a pipe is not using
2444 * any pch resources and so doesn't need any fdi lanes. */
2445 if (!pipe_B_crtc
->base
.enabled
&& !pipe_C_crtc
->base
.enabled
) {
2446 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2447 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2449 temp
= I915_READ(SOUTH_CHICKEN1
);
2450 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2451 DRM_DEBUG_KMS("disabling fdi C rx\n");
2452 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2456 /* The FDI link training functions for ILK/Ibexpeak. */
2457 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2459 struct drm_device
*dev
= crtc
->dev
;
2460 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2461 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2462 int pipe
= intel_crtc
->pipe
;
2463 int plane
= intel_crtc
->plane
;
2464 u32 reg
, temp
, tries
;
2466 /* FDI needs bits from pipe & plane first */
2467 assert_pipe_enabled(dev_priv
, pipe
);
2468 assert_plane_enabled(dev_priv
, plane
);
2470 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2472 reg
= FDI_RX_IMR(pipe
);
2473 temp
= I915_READ(reg
);
2474 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2475 temp
&= ~FDI_RX_BIT_LOCK
;
2476 I915_WRITE(reg
, temp
);
2480 /* enable CPU FDI TX and PCH FDI RX */
2481 reg
= FDI_TX_CTL(pipe
);
2482 temp
= I915_READ(reg
);
2484 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2485 temp
&= ~FDI_LINK_TRAIN_NONE
;
2486 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2487 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2489 reg
= FDI_RX_CTL(pipe
);
2490 temp
= I915_READ(reg
);
2491 temp
&= ~FDI_LINK_TRAIN_NONE
;
2492 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2493 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2498 /* Ironlake workaround, enable clock pointer after FDI enable*/
2499 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2500 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2501 FDI_RX_PHASE_SYNC_POINTER_EN
);
2503 reg
= FDI_RX_IIR(pipe
);
2504 for (tries
= 0; tries
< 5; tries
++) {
2505 temp
= I915_READ(reg
);
2506 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2508 if ((temp
& FDI_RX_BIT_LOCK
)) {
2509 DRM_DEBUG_KMS("FDI train 1 done.\n");
2510 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2515 DRM_ERROR("FDI train 1 fail!\n");
2518 reg
= FDI_TX_CTL(pipe
);
2519 temp
= I915_READ(reg
);
2520 temp
&= ~FDI_LINK_TRAIN_NONE
;
2521 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2522 I915_WRITE(reg
, temp
);
2524 reg
= FDI_RX_CTL(pipe
);
2525 temp
= I915_READ(reg
);
2526 temp
&= ~FDI_LINK_TRAIN_NONE
;
2527 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2528 I915_WRITE(reg
, temp
);
2533 reg
= FDI_RX_IIR(pipe
);
2534 for (tries
= 0; tries
< 5; tries
++) {
2535 temp
= I915_READ(reg
);
2536 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2538 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2539 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2540 DRM_DEBUG_KMS("FDI train 2 done.\n");
2545 DRM_ERROR("FDI train 2 fail!\n");
2547 DRM_DEBUG_KMS("FDI train done\n");
2551 static const int snb_b_fdi_train_param
[] = {
2552 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2553 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2554 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2555 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2558 /* The FDI link training functions for SNB/Cougarpoint. */
2559 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2561 struct drm_device
*dev
= crtc
->dev
;
2562 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2563 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2564 int pipe
= intel_crtc
->pipe
;
2565 u32 reg
, temp
, i
, retry
;
2567 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2569 reg
= FDI_RX_IMR(pipe
);
2570 temp
= I915_READ(reg
);
2571 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2572 temp
&= ~FDI_RX_BIT_LOCK
;
2573 I915_WRITE(reg
, temp
);
2578 /* enable CPU FDI TX and PCH FDI RX */
2579 reg
= FDI_TX_CTL(pipe
);
2580 temp
= I915_READ(reg
);
2582 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2583 temp
&= ~FDI_LINK_TRAIN_NONE
;
2584 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2585 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2587 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2588 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2590 I915_WRITE(FDI_RX_MISC(pipe
),
2591 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2593 reg
= FDI_RX_CTL(pipe
);
2594 temp
= I915_READ(reg
);
2595 if (HAS_PCH_CPT(dev
)) {
2596 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2597 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2599 temp
&= ~FDI_LINK_TRAIN_NONE
;
2600 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2602 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2607 for (i
= 0; i
< 4; i
++) {
2608 reg
= FDI_TX_CTL(pipe
);
2609 temp
= I915_READ(reg
);
2610 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2611 temp
|= snb_b_fdi_train_param
[i
];
2612 I915_WRITE(reg
, temp
);
2617 for (retry
= 0; retry
< 5; retry
++) {
2618 reg
= FDI_RX_IIR(pipe
);
2619 temp
= I915_READ(reg
);
2620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2621 if (temp
& FDI_RX_BIT_LOCK
) {
2622 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2623 DRM_DEBUG_KMS("FDI train 1 done.\n");
2632 DRM_ERROR("FDI train 1 fail!\n");
2635 reg
= FDI_TX_CTL(pipe
);
2636 temp
= I915_READ(reg
);
2637 temp
&= ~FDI_LINK_TRAIN_NONE
;
2638 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2640 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2642 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2644 I915_WRITE(reg
, temp
);
2646 reg
= FDI_RX_CTL(pipe
);
2647 temp
= I915_READ(reg
);
2648 if (HAS_PCH_CPT(dev
)) {
2649 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2650 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2652 temp
&= ~FDI_LINK_TRAIN_NONE
;
2653 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2655 I915_WRITE(reg
, temp
);
2660 for (i
= 0; i
< 4; i
++) {
2661 reg
= FDI_TX_CTL(pipe
);
2662 temp
= I915_READ(reg
);
2663 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2664 temp
|= snb_b_fdi_train_param
[i
];
2665 I915_WRITE(reg
, temp
);
2670 for (retry
= 0; retry
< 5; retry
++) {
2671 reg
= FDI_RX_IIR(pipe
);
2672 temp
= I915_READ(reg
);
2673 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2674 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2675 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2676 DRM_DEBUG_KMS("FDI train 2 done.\n");
2685 DRM_ERROR("FDI train 2 fail!\n");
2687 DRM_DEBUG_KMS("FDI train done.\n");
2690 /* Manual link training for Ivy Bridge A0 parts */
2691 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2693 struct drm_device
*dev
= crtc
->dev
;
2694 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2695 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2696 int pipe
= intel_crtc
->pipe
;
2699 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2701 reg
= FDI_RX_IMR(pipe
);
2702 temp
= I915_READ(reg
);
2703 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2704 temp
&= ~FDI_RX_BIT_LOCK
;
2705 I915_WRITE(reg
, temp
);
2710 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2711 I915_READ(FDI_RX_IIR(pipe
)));
2713 /* enable CPU FDI TX and PCH FDI RX */
2714 reg
= FDI_TX_CTL(pipe
);
2715 temp
= I915_READ(reg
);
2717 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2718 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2719 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2720 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2721 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2722 temp
|= FDI_COMPOSITE_SYNC
;
2723 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2725 I915_WRITE(FDI_RX_MISC(pipe
),
2726 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2728 reg
= FDI_RX_CTL(pipe
);
2729 temp
= I915_READ(reg
);
2730 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2731 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2732 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2733 temp
|= FDI_COMPOSITE_SYNC
;
2734 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2739 for (i
= 0; i
< 4; i
++) {
2740 reg
= FDI_TX_CTL(pipe
);
2741 temp
= I915_READ(reg
);
2742 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2743 temp
|= snb_b_fdi_train_param
[i
];
2744 I915_WRITE(reg
, temp
);
2749 reg
= FDI_RX_IIR(pipe
);
2750 temp
= I915_READ(reg
);
2751 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2753 if (temp
& FDI_RX_BIT_LOCK
||
2754 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2755 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2756 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i
);
2761 DRM_ERROR("FDI train 1 fail!\n");
2764 reg
= FDI_TX_CTL(pipe
);
2765 temp
= I915_READ(reg
);
2766 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2767 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2768 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2769 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2770 I915_WRITE(reg
, temp
);
2772 reg
= FDI_RX_CTL(pipe
);
2773 temp
= I915_READ(reg
);
2774 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2775 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2776 I915_WRITE(reg
, temp
);
2781 for (i
= 0; i
< 4; i
++) {
2782 reg
= FDI_TX_CTL(pipe
);
2783 temp
= I915_READ(reg
);
2784 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2785 temp
|= snb_b_fdi_train_param
[i
];
2786 I915_WRITE(reg
, temp
);
2791 reg
= FDI_RX_IIR(pipe
);
2792 temp
= I915_READ(reg
);
2793 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2795 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2796 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2797 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i
);
2802 DRM_ERROR("FDI train 2 fail!\n");
2804 DRM_DEBUG_KMS("FDI train done.\n");
2807 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
2809 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2810 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2811 int pipe
= intel_crtc
->pipe
;
2815 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2816 reg
= FDI_RX_CTL(pipe
);
2817 temp
= I915_READ(reg
);
2818 temp
&= ~((0x7 << 19) | (0x7 << 16));
2819 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2820 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2821 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2826 /* Switch from Rawclk to PCDclk */
2827 temp
= I915_READ(reg
);
2828 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2833 /* Enable CPU FDI TX PLL, always on for Ironlake */
2834 reg
= FDI_TX_CTL(pipe
);
2835 temp
= I915_READ(reg
);
2836 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2837 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2844 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
2846 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2847 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2848 int pipe
= intel_crtc
->pipe
;
2851 /* Switch from PCDclk to Rawclk */
2852 reg
= FDI_RX_CTL(pipe
);
2853 temp
= I915_READ(reg
);
2854 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2856 /* Disable CPU FDI TX PLL */
2857 reg
= FDI_TX_CTL(pipe
);
2858 temp
= I915_READ(reg
);
2859 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2864 reg
= FDI_RX_CTL(pipe
);
2865 temp
= I915_READ(reg
);
2866 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2868 /* Wait for the clocks to turn off. */
2873 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2875 struct drm_device
*dev
= crtc
->dev
;
2876 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2877 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2878 int pipe
= intel_crtc
->pipe
;
2881 /* disable CPU FDI tx and PCH FDI rx */
2882 reg
= FDI_TX_CTL(pipe
);
2883 temp
= I915_READ(reg
);
2884 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2887 reg
= FDI_RX_CTL(pipe
);
2888 temp
= I915_READ(reg
);
2889 temp
&= ~(0x7 << 16);
2890 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2891 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2896 /* Ironlake workaround, disable clock pointer after downing FDI */
2897 if (HAS_PCH_IBX(dev
)) {
2898 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2901 /* still set train pattern 1 */
2902 reg
= FDI_TX_CTL(pipe
);
2903 temp
= I915_READ(reg
);
2904 temp
&= ~FDI_LINK_TRAIN_NONE
;
2905 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2906 I915_WRITE(reg
, temp
);
2908 reg
= FDI_RX_CTL(pipe
);
2909 temp
= I915_READ(reg
);
2910 if (HAS_PCH_CPT(dev
)) {
2911 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2912 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2914 temp
&= ~FDI_LINK_TRAIN_NONE
;
2915 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2917 /* BPC in FDI rx is consistent with that in PIPECONF */
2918 temp
&= ~(0x07 << 16);
2919 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2920 I915_WRITE(reg
, temp
);
2926 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2928 struct drm_device
*dev
= crtc
->dev
;
2929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2930 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2931 unsigned long flags
;
2934 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2935 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2938 spin_lock_irqsave(&dev
->event_lock
, flags
);
2939 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2940 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2945 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2947 struct drm_device
*dev
= crtc
->dev
;
2948 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2950 if (crtc
->fb
== NULL
)
2953 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
2955 wait_event(dev_priv
->pending_flip_queue
,
2956 !intel_crtc_has_pending_flip(crtc
));
2958 mutex_lock(&dev
->struct_mutex
);
2959 intel_finish_fb(crtc
->fb
);
2960 mutex_unlock(&dev
->struct_mutex
);
2963 static bool ironlake_crtc_driving_pch(struct drm_crtc
*crtc
)
2965 struct drm_device
*dev
= crtc
->dev
;
2966 struct intel_encoder
*intel_encoder
;
2969 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2970 * must be driven by its own crtc; no sharing is possible.
2972 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
2973 switch (intel_encoder
->type
) {
2974 case INTEL_OUTPUT_EDP
:
2975 if (!intel_encoder_is_pch_edp(&intel_encoder
->base
))
2984 static bool haswell_crtc_driving_pch(struct drm_crtc
*crtc
)
2986 return intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
);
2989 /* Program iCLKIP clock to the desired frequency */
2990 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
2992 struct drm_device
*dev
= crtc
->dev
;
2993 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2994 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
2997 mutex_lock(&dev_priv
->dpio_lock
);
2999 /* It is necessary to ungate the pixclk gate prior to programming
3000 * the divisors, and gate it back when it is done.
3002 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3004 /* Disable SSCCTL */
3005 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3006 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3010 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3011 if (crtc
->mode
.clock
== 20000) {
3016 /* The iCLK virtual clock root frequency is in MHz,
3017 * but the crtc->mode.clock in in KHz. To get the divisors,
3018 * it is necessary to divide one by another, so we
3019 * convert the virtual clock precision to KHz here for higher
3022 u32 iclk_virtual_root_freq
= 172800 * 1000;
3023 u32 iclk_pi_range
= 64;
3024 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3026 desired_divisor
= (iclk_virtual_root_freq
/ crtc
->mode
.clock
);
3027 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3028 pi_value
= desired_divisor
% iclk_pi_range
;
3031 divsel
= msb_divisor_value
- 2;
3032 phaseinc
= pi_value
;
3035 /* This should not happen with any sane values */
3036 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3037 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3038 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3039 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3041 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3048 /* Program SSCDIVINTPHASE6 */
3049 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3050 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3051 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3052 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3053 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3054 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3055 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3056 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3058 /* Program SSCAUXDIV */
3059 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3060 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3061 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3062 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3064 /* Enable modulator and associated divider */
3065 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3066 temp
&= ~SBI_SSCCTL_DISABLE
;
3067 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3069 /* Wait for initialization time */
3072 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3074 mutex_unlock(&dev_priv
->dpio_lock
);
3078 * Enable PCH resources required for PCH ports:
3080 * - FDI training & RX/TX
3081 * - update transcoder timings
3082 * - DP transcoding bits
3085 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3087 struct drm_device
*dev
= crtc
->dev
;
3088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3089 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3090 int pipe
= intel_crtc
->pipe
;
3093 assert_transcoder_disabled(dev_priv
, pipe
);
3095 /* Write the TU size bits before fdi link training, so that error
3096 * detection works. */
3097 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3098 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3100 /* For PCH output, training FDI link */
3101 dev_priv
->display
.fdi_link_train(crtc
);
3103 /* XXX: pch pll's can be enabled any time before we enable the PCH
3104 * transcoder, and we actually should do this to not upset any PCH
3105 * transcoder that already use the clock when we share it.
3107 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3108 * unconditionally resets the pll - we need that to have the right LVDS
3109 * enable sequence. */
3110 ironlake_enable_pch_pll(intel_crtc
);
3112 if (HAS_PCH_CPT(dev
)) {
3115 temp
= I915_READ(PCH_DPLL_SEL
);
3119 temp
|= TRANSA_DPLL_ENABLE
;
3120 sel
= TRANSA_DPLLB_SEL
;
3123 temp
|= TRANSB_DPLL_ENABLE
;
3124 sel
= TRANSB_DPLLB_SEL
;
3127 temp
|= TRANSC_DPLL_ENABLE
;
3128 sel
= TRANSC_DPLLB_SEL
;
3131 if (intel_crtc
->pch_pll
->pll_reg
== _PCH_DPLL_B
)
3135 I915_WRITE(PCH_DPLL_SEL
, temp
);
3138 /* set transcoder timing, panel must allow it */
3139 assert_panel_unlocked(dev_priv
, pipe
);
3140 I915_WRITE(TRANS_HTOTAL(pipe
), I915_READ(HTOTAL(pipe
)));
3141 I915_WRITE(TRANS_HBLANK(pipe
), I915_READ(HBLANK(pipe
)));
3142 I915_WRITE(TRANS_HSYNC(pipe
), I915_READ(HSYNC(pipe
)));
3144 I915_WRITE(TRANS_VTOTAL(pipe
), I915_READ(VTOTAL(pipe
)));
3145 I915_WRITE(TRANS_VBLANK(pipe
), I915_READ(VBLANK(pipe
)));
3146 I915_WRITE(TRANS_VSYNC(pipe
), I915_READ(VSYNC(pipe
)));
3147 I915_WRITE(TRANS_VSYNCSHIFT(pipe
), I915_READ(VSYNCSHIFT(pipe
)));
3149 intel_fdi_normal_train(crtc
);
3151 /* For PCH DP, enable TRANS_DP_CTL */
3152 if (HAS_PCH_CPT(dev
) &&
3153 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3154 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3155 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3156 reg
= TRANS_DP_CTL(pipe
);
3157 temp
= I915_READ(reg
);
3158 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3159 TRANS_DP_SYNC_MASK
|
3161 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3162 TRANS_DP_ENH_FRAMING
);
3163 temp
|= bpc
<< 9; /* same format but at 11:9 */
3165 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3166 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3167 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3168 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3170 switch (intel_trans_dp_port_sel(crtc
)) {
3172 temp
|= TRANS_DP_PORT_SEL_B
;
3175 temp
|= TRANS_DP_PORT_SEL_C
;
3178 temp
|= TRANS_DP_PORT_SEL_D
;
3184 I915_WRITE(reg
, temp
);
3187 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3190 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3192 struct drm_device
*dev
= crtc
->dev
;
3193 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3194 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3195 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
3197 assert_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3199 lpt_program_iclkip(crtc
);
3201 /* Set transcoder timing. */
3202 I915_WRITE(_TRANS_HTOTAL_A
, I915_READ(HTOTAL(cpu_transcoder
)));
3203 I915_WRITE(_TRANS_HBLANK_A
, I915_READ(HBLANK(cpu_transcoder
)));
3204 I915_WRITE(_TRANS_HSYNC_A
, I915_READ(HSYNC(cpu_transcoder
)));
3206 I915_WRITE(_TRANS_VTOTAL_A
, I915_READ(VTOTAL(cpu_transcoder
)));
3207 I915_WRITE(_TRANS_VBLANK_A
, I915_READ(VBLANK(cpu_transcoder
)));
3208 I915_WRITE(_TRANS_VSYNC_A
, I915_READ(VSYNC(cpu_transcoder
)));
3209 I915_WRITE(_TRANS_VSYNCSHIFT_A
, I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3211 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3214 static void intel_put_pch_pll(struct intel_crtc
*intel_crtc
)
3216 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
3221 if (pll
->refcount
== 0) {
3222 WARN(1, "bad PCH PLL refcount\n");
3227 intel_crtc
->pch_pll
= NULL
;
3230 static struct intel_pch_pll
*intel_get_pch_pll(struct intel_crtc
*intel_crtc
, u32 dpll
, u32 fp
)
3232 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
3233 struct intel_pch_pll
*pll
;
3236 pll
= intel_crtc
->pch_pll
;
3238 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3239 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3243 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3244 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3245 i
= intel_crtc
->pipe
;
3246 pll
= &dev_priv
->pch_plls
[i
];
3248 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3249 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3254 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3255 pll
= &dev_priv
->pch_plls
[i
];
3257 /* Only want to check enabled timings first */
3258 if (pll
->refcount
== 0)
3261 if (dpll
== (I915_READ(pll
->pll_reg
) & 0x7fffffff) &&
3262 fp
== I915_READ(pll
->fp0_reg
)) {
3263 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3264 intel_crtc
->base
.base
.id
,
3265 pll
->pll_reg
, pll
->refcount
, pll
->active
);
3271 /* Ok no matching timings, maybe there's a free one? */
3272 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3273 pll
= &dev_priv
->pch_plls
[i
];
3274 if (pll
->refcount
== 0) {
3275 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3276 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3284 intel_crtc
->pch_pll
= pll
;
3286 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i
, intel_crtc
->pipe
);
3287 prepare
: /* separate function? */
3288 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll
->pll_reg
);
3290 /* Wait for the clocks to stabilize before rewriting the regs */
3291 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3292 POSTING_READ(pll
->pll_reg
);
3295 I915_WRITE(pll
->fp0_reg
, fp
);
3296 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3301 void intel_cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3304 int dslreg
= PIPEDSL(pipe
);
3307 temp
= I915_READ(dslreg
);
3309 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3310 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3311 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe
);
3315 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3317 struct drm_device
*dev
= crtc
->dev
;
3318 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3319 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3320 struct intel_encoder
*encoder
;
3321 int pipe
= intel_crtc
->pipe
;
3322 int plane
= intel_crtc
->plane
;
3326 WARN_ON(!crtc
->enabled
);
3328 if (intel_crtc
->active
)
3331 intel_crtc
->active
= true;
3332 intel_update_watermarks(dev
);
3334 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
3335 temp
= I915_READ(PCH_LVDS
);
3336 if ((temp
& LVDS_PORT_EN
) == 0)
3337 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
3340 is_pch_port
= ironlake_crtc_driving_pch(crtc
);
3343 /* Note: FDI PLL enabling _must_ be done before we enable the
3344 * cpu pipes, hence this is separate from all the other fdi/pch
3346 ironlake_fdi_pll_enable(intel_crtc
);
3348 assert_fdi_tx_disabled(dev_priv
, pipe
);
3349 assert_fdi_rx_disabled(dev_priv
, pipe
);
3352 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3353 if (encoder
->pre_enable
)
3354 encoder
->pre_enable(encoder
);
3356 /* Enable panel fitting for LVDS */
3357 if (dev_priv
->pch_pf_size
&&
3358 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
3359 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3360 /* Force use of hard-coded filter coefficients
3361 * as some pre-programmed values are broken,
3364 if (IS_IVYBRIDGE(dev
))
3365 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3366 PF_PIPE_SEL_IVB(pipe
));
3368 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3369 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3370 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3374 * On ILK+ LUT must be loaded before the pipe is running but with
3377 intel_crtc_load_lut(crtc
);
3379 intel_enable_pipe(dev_priv
, pipe
, is_pch_port
);
3380 intel_enable_plane(dev_priv
, plane
, pipe
);
3383 ironlake_pch_enable(crtc
);
3385 mutex_lock(&dev
->struct_mutex
);
3386 intel_update_fbc(dev
);
3387 mutex_unlock(&dev
->struct_mutex
);
3389 intel_crtc_update_cursor(crtc
, true);
3391 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3392 encoder
->enable(encoder
);
3394 if (HAS_PCH_CPT(dev
))
3395 intel_cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3398 * There seems to be a race in PCH platform hw (at least on some
3399 * outputs) where an enabled pipe still completes any pageflip right
3400 * away (as if the pipe is off) instead of waiting for vblank. As soon
3401 * as the first vblank happend, everything works as expected. Hence just
3402 * wait for one vblank before returning to avoid strange things
3405 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3408 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
3410 struct drm_device
*dev
= crtc
->dev
;
3411 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3412 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3413 struct intel_encoder
*encoder
;
3414 int pipe
= intel_crtc
->pipe
;
3415 int plane
= intel_crtc
->plane
;
3418 WARN_ON(!crtc
->enabled
);
3420 if (intel_crtc
->active
)
3423 intel_crtc
->active
= true;
3424 intel_update_watermarks(dev
);
3426 is_pch_port
= haswell_crtc_driving_pch(crtc
);
3429 dev_priv
->display
.fdi_link_train(crtc
);
3431 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3432 if (encoder
->pre_enable
)
3433 encoder
->pre_enable(encoder
);
3435 intel_ddi_enable_pipe_clock(intel_crtc
);
3437 /* Enable panel fitting for eDP */
3438 if (dev_priv
->pch_pf_size
&&
3439 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
3440 /* Force use of hard-coded filter coefficients
3441 * as some pre-programmed values are broken,
3444 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3445 PF_PIPE_SEL_IVB(pipe
));
3446 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3447 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3451 * On ILK+ LUT must be loaded before the pipe is running but with
3454 intel_crtc_load_lut(crtc
);
3456 intel_ddi_set_pipe_settings(crtc
);
3457 intel_ddi_enable_pipe_func(crtc
);
3459 intel_enable_pipe(dev_priv
, pipe
, is_pch_port
);
3460 intel_enable_plane(dev_priv
, plane
, pipe
);
3463 lpt_pch_enable(crtc
);
3465 mutex_lock(&dev
->struct_mutex
);
3466 intel_update_fbc(dev
);
3467 mutex_unlock(&dev
->struct_mutex
);
3469 intel_crtc_update_cursor(crtc
, true);
3471 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3472 encoder
->enable(encoder
);
3475 * There seems to be a race in PCH platform hw (at least on some
3476 * outputs) where an enabled pipe still completes any pageflip right
3477 * away (as if the pipe is off) instead of waiting for vblank. As soon
3478 * as the first vblank happend, everything works as expected. Hence just
3479 * wait for one vblank before returning to avoid strange things
3482 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3485 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3487 struct drm_device
*dev
= crtc
->dev
;
3488 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3489 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3490 struct intel_encoder
*encoder
;
3491 int pipe
= intel_crtc
->pipe
;
3492 int plane
= intel_crtc
->plane
;
3496 if (!intel_crtc
->active
)
3499 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3500 encoder
->disable(encoder
);
3502 intel_crtc_wait_for_pending_flips(crtc
);
3503 drm_vblank_off(dev
, pipe
);
3504 intel_crtc_update_cursor(crtc
, false);
3506 intel_disable_plane(dev_priv
, plane
, pipe
);
3508 if (dev_priv
->cfb_plane
== plane
)
3509 intel_disable_fbc(dev
);
3511 intel_disable_pipe(dev_priv
, pipe
);
3514 I915_WRITE(PF_CTL(pipe
), 0);
3515 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3517 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3518 if (encoder
->post_disable
)
3519 encoder
->post_disable(encoder
);
3521 ironlake_fdi_disable(crtc
);
3523 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
3525 if (HAS_PCH_CPT(dev
)) {
3526 /* disable TRANS_DP_CTL */
3527 reg
= TRANS_DP_CTL(pipe
);
3528 temp
= I915_READ(reg
);
3529 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
3530 temp
|= TRANS_DP_PORT_SEL_NONE
;
3531 I915_WRITE(reg
, temp
);
3533 /* disable DPLL_SEL */
3534 temp
= I915_READ(PCH_DPLL_SEL
);
3537 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLB_SEL
);
3540 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
3543 /* C shares PLL A or B */
3544 temp
&= ~(TRANSC_DPLL_ENABLE
| TRANSC_DPLLB_SEL
);
3549 I915_WRITE(PCH_DPLL_SEL
, temp
);
3552 /* disable PCH DPLL */
3553 intel_disable_pch_pll(intel_crtc
);
3555 ironlake_fdi_pll_disable(intel_crtc
);
3557 intel_crtc
->active
= false;
3558 intel_update_watermarks(dev
);
3560 mutex_lock(&dev
->struct_mutex
);
3561 intel_update_fbc(dev
);
3562 mutex_unlock(&dev
->struct_mutex
);
3565 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
3567 struct drm_device
*dev
= crtc
->dev
;
3568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3569 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3570 struct intel_encoder
*encoder
;
3571 int pipe
= intel_crtc
->pipe
;
3572 int plane
= intel_crtc
->plane
;
3573 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
3576 if (!intel_crtc
->active
)
3579 is_pch_port
= haswell_crtc_driving_pch(crtc
);
3581 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3582 encoder
->disable(encoder
);
3584 intel_crtc_wait_for_pending_flips(crtc
);
3585 drm_vblank_off(dev
, pipe
);
3586 intel_crtc_update_cursor(crtc
, false);
3588 intel_disable_plane(dev_priv
, plane
, pipe
);
3590 if (dev_priv
->cfb_plane
== plane
)
3591 intel_disable_fbc(dev
);
3593 intel_disable_pipe(dev_priv
, pipe
);
3595 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
3598 I915_WRITE(PF_CTL(pipe
), 0);
3599 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3601 intel_ddi_disable_pipe_clock(intel_crtc
);
3603 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3604 if (encoder
->post_disable
)
3605 encoder
->post_disable(encoder
);
3608 lpt_disable_pch_transcoder(dev_priv
);
3609 intel_ddi_fdi_disable(crtc
);
3612 intel_crtc
->active
= false;
3613 intel_update_watermarks(dev
);
3615 mutex_lock(&dev
->struct_mutex
);
3616 intel_update_fbc(dev
);
3617 mutex_unlock(&dev
->struct_mutex
);
3620 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3622 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3623 intel_put_pch_pll(intel_crtc
);
3626 static void haswell_crtc_off(struct drm_crtc
*crtc
)
3628 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3630 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3631 * start using it. */
3632 intel_crtc
->cpu_transcoder
= (enum transcoder
) intel_crtc
->pipe
;
3634 intel_ddi_put_crtc_pll(crtc
);
3637 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3639 if (!enable
&& intel_crtc
->overlay
) {
3640 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3641 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3643 mutex_lock(&dev
->struct_mutex
);
3644 dev_priv
->mm
.interruptible
= false;
3645 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3646 dev_priv
->mm
.interruptible
= true;
3647 mutex_unlock(&dev
->struct_mutex
);
3650 /* Let userspace switch the overlay on again. In most cases userspace
3651 * has to recompute where to put it anyway.
3656 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3657 * cursor plane briefly if not already running after enabling the display
3659 * This workaround avoids occasional blank screens when self refresh is
3663 g4x_fixup_plane(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
3665 u32 cntl
= I915_READ(CURCNTR(pipe
));
3667 if ((cntl
& CURSOR_MODE
) == 0) {
3668 u32 fw_bcl_self
= I915_READ(FW_BLC_SELF
);
3670 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
& ~FW_BLC_SELF_EN
);
3671 I915_WRITE(CURCNTR(pipe
), CURSOR_MODE_64_ARGB_AX
);
3672 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
3673 I915_WRITE(CURCNTR(pipe
), cntl
);
3674 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3675 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
);
3679 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3681 struct drm_device
*dev
= crtc
->dev
;
3682 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3683 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3684 struct intel_encoder
*encoder
;
3685 int pipe
= intel_crtc
->pipe
;
3686 int plane
= intel_crtc
->plane
;
3688 WARN_ON(!crtc
->enabled
);
3690 if (intel_crtc
->active
)
3693 intel_crtc
->active
= true;
3694 intel_update_watermarks(dev
);
3696 intel_enable_pll(dev_priv
, pipe
);
3698 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3699 if (encoder
->pre_enable
)
3700 encoder
->pre_enable(encoder
);
3702 intel_enable_pipe(dev_priv
, pipe
, false);
3703 intel_enable_plane(dev_priv
, plane
, pipe
);
3705 g4x_fixup_plane(dev_priv
, pipe
);
3707 intel_crtc_load_lut(crtc
);
3708 intel_update_fbc(dev
);
3710 /* Give the overlay scaler a chance to enable if it's on this pipe */
3711 intel_crtc_dpms_overlay(intel_crtc
, true);
3712 intel_crtc_update_cursor(crtc
, true);
3714 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3715 encoder
->enable(encoder
);
3718 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3720 struct drm_device
*dev
= crtc
->dev
;
3721 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3722 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3723 struct intel_encoder
*encoder
;
3724 int pipe
= intel_crtc
->pipe
;
3725 int plane
= intel_crtc
->plane
;
3729 if (!intel_crtc
->active
)
3732 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3733 encoder
->disable(encoder
);
3735 /* Give the overlay scaler a chance to disable if it's on this pipe */
3736 intel_crtc_wait_for_pending_flips(crtc
);
3737 drm_vblank_off(dev
, pipe
);
3738 intel_crtc_dpms_overlay(intel_crtc
, false);
3739 intel_crtc_update_cursor(crtc
, false);
3741 if (dev_priv
->cfb_plane
== plane
)
3742 intel_disable_fbc(dev
);
3744 intel_disable_plane(dev_priv
, plane
, pipe
);
3745 intel_disable_pipe(dev_priv
, pipe
);
3747 /* Disable pannel fitter if it is on this pipe. */
3748 pctl
= I915_READ(PFIT_CONTROL
);
3749 if ((pctl
& PFIT_ENABLE
) &&
3750 ((pctl
& PFIT_PIPE_MASK
) >> PFIT_PIPE_SHIFT
) == pipe
)
3751 I915_WRITE(PFIT_CONTROL
, 0);
3753 intel_disable_pll(dev_priv
, pipe
);
3755 intel_crtc
->active
= false;
3756 intel_update_fbc(dev
);
3757 intel_update_watermarks(dev
);
3760 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
3764 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
3767 struct drm_device
*dev
= crtc
->dev
;
3768 struct drm_i915_master_private
*master_priv
;
3769 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3770 int pipe
= intel_crtc
->pipe
;
3772 if (!dev
->primary
->master
)
3775 master_priv
= dev
->primary
->master
->driver_priv
;
3776 if (!master_priv
->sarea_priv
)
3781 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3782 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3785 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3786 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3789 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3795 * Sets the power management mode of the pipe and plane.
3797 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
3799 struct drm_device
*dev
= crtc
->dev
;
3800 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3801 struct intel_encoder
*intel_encoder
;
3802 bool enable
= false;
3804 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
3805 enable
|= intel_encoder
->connectors_active
;
3808 dev_priv
->display
.crtc_enable(crtc
);
3810 dev_priv
->display
.crtc_disable(crtc
);
3812 intel_crtc_update_sarea(crtc
, enable
);
3815 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3817 struct drm_device
*dev
= crtc
->dev
;
3818 struct drm_connector
*connector
;
3819 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3820 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3822 /* crtc should still be enabled when we disable it. */
3823 WARN_ON(!crtc
->enabled
);
3825 intel_crtc
->eld_vld
= false;
3826 dev_priv
->display
.crtc_disable(crtc
);
3827 intel_crtc_update_sarea(crtc
, false);
3828 dev_priv
->display
.off(crtc
);
3830 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
3831 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
3834 mutex_lock(&dev
->struct_mutex
);
3835 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
3836 mutex_unlock(&dev
->struct_mutex
);
3840 /* Update computed state. */
3841 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3842 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
3845 if (connector
->encoder
->crtc
!= crtc
)
3848 connector
->dpms
= DRM_MODE_DPMS_OFF
;
3849 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
3853 void intel_modeset_disable(struct drm_device
*dev
)
3855 struct drm_crtc
*crtc
;
3857 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3859 intel_crtc_disable(crtc
);
3863 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3865 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3867 drm_encoder_cleanup(encoder
);
3868 kfree(intel_encoder
);
3871 /* Simple dpms helper for encodres with just one connector, no cloning and only
3872 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3873 * state of the entire output pipe. */
3874 void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
3876 if (mode
== DRM_MODE_DPMS_ON
) {
3877 encoder
->connectors_active
= true;
3879 intel_crtc_update_dpms(encoder
->base
.crtc
);
3881 encoder
->connectors_active
= false;
3883 intel_crtc_update_dpms(encoder
->base
.crtc
);
3887 /* Cross check the actual hw state with our own modeset state tracking (and it's
3888 * internal consistency). */
3889 static void intel_connector_check_state(struct intel_connector
*connector
)
3891 if (connector
->get_hw_state(connector
)) {
3892 struct intel_encoder
*encoder
= connector
->encoder
;
3893 struct drm_crtc
*crtc
;
3894 bool encoder_enabled
;
3897 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3898 connector
->base
.base
.id
,
3899 drm_get_connector_name(&connector
->base
));
3901 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
3902 "wrong connector dpms state\n");
3903 WARN(connector
->base
.encoder
!= &encoder
->base
,
3904 "active connector not linked to encoder\n");
3905 WARN(!encoder
->connectors_active
,
3906 "encoder->connectors_active not set\n");
3908 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
3909 WARN(!encoder_enabled
, "encoder not enabled\n");
3910 if (WARN_ON(!encoder
->base
.crtc
))
3913 crtc
= encoder
->base
.crtc
;
3915 WARN(!crtc
->enabled
, "crtc not enabled\n");
3916 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
3917 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
3918 "encoder active on the wrong pipe\n");
3922 /* Even simpler default implementation, if there's really no special case to
3924 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
3926 struct intel_encoder
*encoder
= intel_attached_encoder(connector
);
3928 /* All the simple cases only support two dpms states. */
3929 if (mode
!= DRM_MODE_DPMS_ON
)
3930 mode
= DRM_MODE_DPMS_OFF
;
3932 if (mode
== connector
->dpms
)
3935 connector
->dpms
= mode
;
3937 /* Only need to change hw state when actually enabled */
3938 if (encoder
->base
.crtc
)
3939 intel_encoder_dpms(encoder
, mode
);
3941 WARN_ON(encoder
->connectors_active
!= false);
3943 intel_modeset_check_state(connector
->dev
);
3946 /* Simple connector->get_hw_state implementation for encoders that support only
3947 * one connector and no cloning and hence the encoder state determines the state
3948 * of the connector. */
3949 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
3952 struct intel_encoder
*encoder
= connector
->encoder
;
3954 return encoder
->get_hw_state(encoder
, &pipe
);
3957 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
3958 const struct drm_display_mode
*mode
,
3959 struct drm_display_mode
*adjusted_mode
)
3961 struct drm_device
*dev
= crtc
->dev
;
3963 if (HAS_PCH_SPLIT(dev
)) {
3964 /* FDI link clock is fixed at 2.7G */
3965 if (mode
->clock
* 3 > IRONLAKE_FDI_FREQ
* 4)
3969 /* All interlaced capable intel hw wants timings in frames. Note though
3970 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3971 * timings, so we need to be careful not to clobber these.*/
3972 if (!(adjusted_mode
->private_flags
& INTEL_MODE_CRTC_TIMINGS_SET
))
3973 drm_mode_set_crtcinfo(adjusted_mode
, 0);
3975 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3976 * with a hsync front porch of 0.
3978 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
3979 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
3985 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
3987 return 400000; /* FIXME */
3990 static int i945_get_display_clock_speed(struct drm_device
*dev
)
3995 static int i915_get_display_clock_speed(struct drm_device
*dev
)
4000 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
4005 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
4009 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4011 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
4014 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4015 case GC_DISPLAY_CLOCK_333_MHZ
:
4018 case GC_DISPLAY_CLOCK_190_200_MHZ
:
4024 static int i865_get_display_clock_speed(struct drm_device
*dev
)
4029 static int i855_get_display_clock_speed(struct drm_device
*dev
)
4032 /* Assume that the hardware is in the high speed state. This
4033 * should be the default.
4035 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
4036 case GC_CLOCK_133_200
:
4037 case GC_CLOCK_100_200
:
4039 case GC_CLOCK_166_250
:
4041 case GC_CLOCK_100_133
:
4045 /* Shouldn't happen */
4049 static int i830_get_display_clock_speed(struct drm_device
*dev
)
4055 intel_reduce_ratio(uint32_t *num
, uint32_t *den
)
4057 while (*num
> 0xffffff || *den
> 0xffffff) {
4064 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
4065 int pixel_clock
, int link_clock
,
4066 struct intel_link_m_n
*m_n
)
4069 m_n
->gmch_m
= bits_per_pixel
* pixel_clock
;
4070 m_n
->gmch_n
= link_clock
* nlanes
* 8;
4071 intel_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
4072 m_n
->link_m
= pixel_clock
;
4073 m_n
->link_n
= link_clock
;
4074 intel_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
4077 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
4079 if (i915_panel_use_ssc
>= 0)
4080 return i915_panel_use_ssc
!= 0;
4081 return dev_priv
->lvds_use_ssc
4082 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
4086 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4087 * @crtc: CRTC structure
4088 * @mode: requested mode
4090 * A pipe may be connected to one or more outputs. Based on the depth of the
4091 * attached framebuffer, choose a good color depth to use on the pipe.
4093 * If possible, match the pipe depth to the fb depth. In some cases, this
4094 * isn't ideal, because the connected output supports a lesser or restricted
4095 * set of depths. Resolve that here:
4096 * LVDS typically supports only 6bpc, so clamp down in that case
4097 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4098 * Displays may support a restricted set as well, check EDID and clamp as
4100 * DP may want to dither down to 6bpc to fit larger modes
4103 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4104 * true if they don't match).
4106 static bool intel_choose_pipe_bpp_dither(struct drm_crtc
*crtc
,
4107 struct drm_framebuffer
*fb
,
4108 unsigned int *pipe_bpp
,
4109 struct drm_display_mode
*mode
)
4111 struct drm_device
*dev
= crtc
->dev
;
4112 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4113 struct drm_connector
*connector
;
4114 struct intel_encoder
*intel_encoder
;
4115 unsigned int display_bpc
= UINT_MAX
, bpc
;
4117 /* Walk the encoders & connectors on this crtc, get min bpc */
4118 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4120 if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
) {
4121 unsigned int lvds_bpc
;
4123 if ((I915_READ(PCH_LVDS
) & LVDS_A3_POWER_MASK
) ==
4129 if (lvds_bpc
< display_bpc
) {
4130 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc
, lvds_bpc
);
4131 display_bpc
= lvds_bpc
;
4136 /* Not one of the known troublemakers, check the EDID */
4137 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
4139 if (connector
->encoder
!= &intel_encoder
->base
)
4142 /* Don't use an invalid EDID bpc value */
4143 if (connector
->display_info
.bpc
&&
4144 connector
->display_info
.bpc
< display_bpc
) {
4145 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc
, connector
->display_info
.bpc
);
4146 display_bpc
= connector
->display_info
.bpc
;
4150 if (intel_encoder
->type
== INTEL_OUTPUT_EDP
) {
4151 /* Use VBT settings if we have an eDP panel */
4152 unsigned int edp_bpc
= dev_priv
->edp
.bpp
/ 3;
4154 if (edp_bpc
&& edp_bpc
< display_bpc
) {
4155 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc
, edp_bpc
);
4156 display_bpc
= edp_bpc
;
4162 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4163 * through, clamp it down. (Note: >12bpc will be caught below.)
4165 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
4166 if (display_bpc
> 8 && display_bpc
< 12) {
4167 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4170 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4176 if (mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
4177 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4182 * We could just drive the pipe at the highest bpc all the time and
4183 * enable dithering as needed, but that costs bandwidth. So choose
4184 * the minimum value that expresses the full color range of the fb but
4185 * also stays within the max display bpc discovered above.
4188 switch (fb
->depth
) {
4190 bpc
= 8; /* since we go through a colormap */
4194 bpc
= 6; /* min is 18bpp */
4206 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4207 bpc
= min((unsigned int)8, display_bpc
);
4211 display_bpc
= min(display_bpc
, bpc
);
4213 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4216 *pipe_bpp
= display_bpc
* 3;
4218 return display_bpc
!= bpc
;
4221 static int vlv_get_refclk(struct drm_crtc
*crtc
)
4223 struct drm_device
*dev
= crtc
->dev
;
4224 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4225 int refclk
= 27000; /* for DP & HDMI */
4227 return 100000; /* only one validated so far */
4229 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
4231 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4232 if (intel_panel_use_ssc(dev_priv
))
4236 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
4243 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
4245 struct drm_device
*dev
= crtc
->dev
;
4246 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4249 if (IS_VALLEYVIEW(dev
)) {
4250 refclk
= vlv_get_refclk(crtc
);
4251 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4252 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4253 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
4254 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4256 } else if (!IS_GEN2(dev
)) {
4265 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode
*adjusted_mode
,
4266 intel_clock_t
*clock
)
4268 /* SDVO TV has fixed PLL values depend on its clock range,
4269 this mirrors vbios setting. */
4270 if (adjusted_mode
->clock
>= 100000
4271 && adjusted_mode
->clock
< 140500) {
4277 } else if (adjusted_mode
->clock
>= 140500
4278 && adjusted_mode
->clock
<= 200000) {
4287 static void i9xx_update_pll_dividers(struct drm_crtc
*crtc
,
4288 intel_clock_t
*clock
,
4289 intel_clock_t
*reduced_clock
)
4291 struct drm_device
*dev
= crtc
->dev
;
4292 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4293 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4294 int pipe
= intel_crtc
->pipe
;
4297 if (IS_PINEVIEW(dev
)) {
4298 fp
= (1 << clock
->n
) << 16 | clock
->m1
<< 8 | clock
->m2
;
4300 fp2
= (1 << reduced_clock
->n
) << 16 |
4301 reduced_clock
->m1
<< 8 | reduced_clock
->m2
;
4303 fp
= clock
->n
<< 16 | clock
->m1
<< 8 | clock
->m2
;
4305 fp2
= reduced_clock
->n
<< 16 | reduced_clock
->m1
<< 8 |
4309 I915_WRITE(FP0(pipe
), fp
);
4311 intel_crtc
->lowfreq_avail
= false;
4312 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4313 reduced_clock
&& i915_powersave
) {
4314 I915_WRITE(FP1(pipe
), fp2
);
4315 intel_crtc
->lowfreq_avail
= true;
4317 I915_WRITE(FP1(pipe
), fp
);
4321 static void vlv_update_pll(struct drm_crtc
*crtc
,
4322 struct drm_display_mode
*mode
,
4323 struct drm_display_mode
*adjusted_mode
,
4324 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4327 struct drm_device
*dev
= crtc
->dev
;
4328 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4329 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4330 int pipe
= intel_crtc
->pipe
;
4331 u32 dpll
, mdiv
, pdiv
;
4332 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4336 mutex_lock(&dev_priv
->dpio_lock
);
4338 is_sdvo
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
) ||
4339 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
);
4341 dpll
= DPLL_VGA_MODE_DIS
;
4342 dpll
|= DPLL_EXT_BUFFER_ENABLE_VLV
;
4343 dpll
|= DPLL_REFA_CLK_ENABLE_VLV
;
4344 dpll
|= DPLL_INTEGRATED_CLOCK_VLV
;
4346 I915_WRITE(DPLL(pipe
), dpll
);
4347 POSTING_READ(DPLL(pipe
));
4356 * In Valleyview PLL and program lane counter registers are exposed
4357 * through DPIO interface
4359 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4360 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4361 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4362 mdiv
|= (1 << DPIO_POST_DIV_SHIFT
);
4363 mdiv
|= (1 << DPIO_K_SHIFT
);
4364 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4365 intel_dpio_write(dev_priv
, DPIO_DIV(pipe
), mdiv
);
4367 intel_dpio_write(dev_priv
, DPIO_CORE_CLK(pipe
), 0x01000000);
4369 pdiv
= (1 << DPIO_REFSEL_OVERRIDE
) | (5 << DPIO_PLL_MODESEL_SHIFT
) |
4370 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT
) | (1<<20) |
4371 (7 << DPIO_PLL_REFCLK_SEL_SHIFT
) | (8 << DPIO_DRIVER_CTL_SHIFT
) |
4372 (5 << DPIO_CLK_BIAS_CTL_SHIFT
);
4373 intel_dpio_write(dev_priv
, DPIO_REFSFR(pipe
), pdiv
);
4375 intel_dpio_write(dev_priv
, DPIO_LFP_COEFF(pipe
), 0x005f003b);
4377 dpll
|= DPLL_VCO_ENABLE
;
4378 I915_WRITE(DPLL(pipe
), dpll
);
4379 POSTING_READ(DPLL(pipe
));
4380 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
4381 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
4383 intel_dpio_write(dev_priv
, DPIO_FASTCLK_DISABLE
, 0x620);
4385 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4386 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4388 I915_WRITE(DPLL(pipe
), dpll
);
4390 /* Wait for the clocks to stabilize. */
4391 POSTING_READ(DPLL(pipe
));
4396 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4398 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4402 I915_WRITE(DPLL_MD(pipe
), temp
);
4403 POSTING_READ(DPLL_MD(pipe
));
4405 /* Now program lane control registers */
4406 if(intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)
4407 || intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
4412 intel_dpio_write(dev_priv
, DPIO_DATA_CHANNEL1
, temp
);
4414 if(intel_pipe_has_type(crtc
,INTEL_OUTPUT_EDP
))
4419 intel_dpio_write(dev_priv
, DPIO_DATA_CHANNEL2
, temp
);
4422 mutex_unlock(&dev_priv
->dpio_lock
);
4425 static void i9xx_update_pll(struct drm_crtc
*crtc
,
4426 struct drm_display_mode
*mode
,
4427 struct drm_display_mode
*adjusted_mode
,
4428 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4431 struct drm_device
*dev
= crtc
->dev
;
4432 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4433 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4434 struct intel_encoder
*encoder
;
4435 int pipe
= intel_crtc
->pipe
;
4439 i9xx_update_pll_dividers(crtc
, clock
, reduced_clock
);
4441 is_sdvo
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
) ||
4442 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
);
4444 dpll
= DPLL_VGA_MODE_DIS
;
4446 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
4447 dpll
|= DPLLB_MODE_LVDS
;
4449 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4451 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4452 if (pixel_multiplier
> 1) {
4453 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4454 dpll
|= (pixel_multiplier
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
4456 dpll
|= DPLL_DVO_HIGH_SPEED
;
4458 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4459 dpll
|= DPLL_DVO_HIGH_SPEED
;
4461 /* compute bitmask from p1 value */
4462 if (IS_PINEVIEW(dev
))
4463 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4465 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4466 if (IS_G4X(dev
) && reduced_clock
)
4467 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4469 switch (clock
->p2
) {
4471 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4474 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4477 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4480 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4483 if (INTEL_INFO(dev
)->gen
>= 4)
4484 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4486 if (is_sdvo
&& intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4487 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4488 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4489 /* XXX: just matching BIOS for now */
4490 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4492 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4493 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4494 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4496 dpll
|= PLL_REF_INPUT_DREFCLK
;
4498 dpll
|= DPLL_VCO_ENABLE
;
4499 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4500 POSTING_READ(DPLL(pipe
));
4503 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4504 if (encoder
->pre_pll_enable
)
4505 encoder
->pre_pll_enable(encoder
);
4507 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4508 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4510 I915_WRITE(DPLL(pipe
), dpll
);
4512 /* Wait for the clocks to stabilize. */
4513 POSTING_READ(DPLL(pipe
));
4516 if (INTEL_INFO(dev
)->gen
>= 4) {
4519 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4521 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4525 I915_WRITE(DPLL_MD(pipe
), temp
);
4527 /* The pixel multiplier can only be updated once the
4528 * DPLL is enabled and the clocks are stable.
4530 * So write it again.
4532 I915_WRITE(DPLL(pipe
), dpll
);
4536 static void i8xx_update_pll(struct drm_crtc
*crtc
,
4537 struct drm_display_mode
*adjusted_mode
,
4538 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4541 struct drm_device
*dev
= crtc
->dev
;
4542 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4543 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4544 struct intel_encoder
*encoder
;
4545 int pipe
= intel_crtc
->pipe
;
4548 i9xx_update_pll_dividers(crtc
, clock
, reduced_clock
);
4550 dpll
= DPLL_VGA_MODE_DIS
;
4552 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4553 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4556 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4558 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4560 dpll
|= PLL_P2_DIVIDE_BY_4
;
4563 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4564 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4565 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4567 dpll
|= PLL_REF_INPUT_DREFCLK
;
4569 dpll
|= DPLL_VCO_ENABLE
;
4570 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4571 POSTING_READ(DPLL(pipe
));
4574 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4575 if (encoder
->pre_pll_enable
)
4576 encoder
->pre_pll_enable(encoder
);
4578 I915_WRITE(DPLL(pipe
), dpll
);
4580 /* Wait for the clocks to stabilize. */
4581 POSTING_READ(DPLL(pipe
));
4584 /* The pixel multiplier can only be updated once the
4585 * DPLL is enabled and the clocks are stable.
4587 * So write it again.
4589 I915_WRITE(DPLL(pipe
), dpll
);
4592 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
,
4593 struct drm_display_mode
*mode
,
4594 struct drm_display_mode
*adjusted_mode
)
4596 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4597 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4598 enum pipe pipe
= intel_crtc
->pipe
;
4599 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
4600 uint32_t vsyncshift
;
4602 if (!IS_GEN2(dev
) && adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4603 /* the chip adds 2 halflines automatically */
4604 adjusted_mode
->crtc_vtotal
-= 1;
4605 adjusted_mode
->crtc_vblank_end
-= 1;
4606 vsyncshift
= adjusted_mode
->crtc_hsync_start
4607 - adjusted_mode
->crtc_htotal
/ 2;
4612 if (INTEL_INFO(dev
)->gen
> 3)
4613 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
4615 I915_WRITE(HTOTAL(cpu_transcoder
),
4616 (adjusted_mode
->crtc_hdisplay
- 1) |
4617 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4618 I915_WRITE(HBLANK(cpu_transcoder
),
4619 (adjusted_mode
->crtc_hblank_start
- 1) |
4620 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4621 I915_WRITE(HSYNC(cpu_transcoder
),
4622 (adjusted_mode
->crtc_hsync_start
- 1) |
4623 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4625 I915_WRITE(VTOTAL(cpu_transcoder
),
4626 (adjusted_mode
->crtc_vdisplay
- 1) |
4627 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
4628 I915_WRITE(VBLANK(cpu_transcoder
),
4629 (adjusted_mode
->crtc_vblank_start
- 1) |
4630 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
4631 I915_WRITE(VSYNC(cpu_transcoder
),
4632 (adjusted_mode
->crtc_vsync_start
- 1) |
4633 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4635 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4636 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4637 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4639 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
4640 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
4641 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
4643 /* pipesrc controls the size that is scaled from, which should
4644 * always be the user's requested size.
4646 I915_WRITE(PIPESRC(pipe
),
4647 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4650 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
4651 struct drm_display_mode
*mode
,
4652 struct drm_display_mode
*adjusted_mode
,
4654 struct drm_framebuffer
*fb
)
4656 struct drm_device
*dev
= crtc
->dev
;
4657 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4658 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4659 int pipe
= intel_crtc
->pipe
;
4660 int plane
= intel_crtc
->plane
;
4661 int refclk
, num_connectors
= 0;
4662 intel_clock_t clock
, reduced_clock
;
4663 u32 dspcntr
, pipeconf
;
4664 bool ok
, has_reduced_clock
= false, is_sdvo
= false;
4665 bool is_lvds
= false, is_tv
= false, is_dp
= false;
4666 struct intel_encoder
*encoder
;
4667 const intel_limit_t
*limit
;
4670 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4671 switch (encoder
->type
) {
4672 case INTEL_OUTPUT_LVDS
:
4675 case INTEL_OUTPUT_SDVO
:
4676 case INTEL_OUTPUT_HDMI
:
4678 if (encoder
->needs_tv_clock
)
4681 case INTEL_OUTPUT_TVOUT
:
4684 case INTEL_OUTPUT_DISPLAYPORT
:
4692 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
4695 * Returns a set of divisors for the desired target clock with the given
4696 * refclk, or FALSE. The returned values represent the clock equation:
4697 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4699 limit
= intel_limit(crtc
, refclk
);
4700 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
4703 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4707 /* Ensure that the cursor is valid for the new mode before changing... */
4708 intel_crtc_update_cursor(crtc
, true);
4710 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4712 * Ensure we match the reduced clock's P to the target clock.
4713 * If the clocks don't match, we can't switch the display clock
4714 * by using the FP0/FP1. In such case we will disable the LVDS
4715 * downclock feature.
4717 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
4718 dev_priv
->lvds_downclock
,
4724 if (is_sdvo
&& is_tv
)
4725 i9xx_adjust_sdvo_tv_clock(adjusted_mode
, &clock
);
4728 i8xx_update_pll(crtc
, adjusted_mode
, &clock
,
4729 has_reduced_clock
? &reduced_clock
: NULL
,
4731 else if (IS_VALLEYVIEW(dev
))
4732 vlv_update_pll(crtc
, mode
, adjusted_mode
, &clock
,
4733 has_reduced_clock
? &reduced_clock
: NULL
,
4736 i9xx_update_pll(crtc
, mode
, adjusted_mode
, &clock
,
4737 has_reduced_clock
? &reduced_clock
: NULL
,
4740 /* setup pipeconf */
4741 pipeconf
= I915_READ(PIPECONF(pipe
));
4743 /* Set up the display plane register */
4744 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4746 if (!IS_VALLEYVIEW(dev
)) {
4748 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4750 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4753 if (pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
4754 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4757 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4761 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
4762 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4764 pipeconf
&= ~PIPECONF_DOUBLE_WIDE
;
4767 /* default to 8bpc */
4768 pipeconf
&= ~(PIPECONF_BPC_MASK
| PIPECONF_DITHER_EN
);
4770 if (adjusted_mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
4771 pipeconf
|= PIPECONF_6BPC
|
4772 PIPECONF_DITHER_EN
|
4773 PIPECONF_DITHER_TYPE_SP
;
4777 if (IS_VALLEYVIEW(dev
) && intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
4778 if (adjusted_mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
4779 pipeconf
|= PIPECONF_6BPC
|
4781 I965_PIPECONF_ACTIVE
;
4785 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
4786 drm_mode_debug_printmodeline(mode
);
4788 if (HAS_PIPE_CXSR(dev
)) {
4789 if (intel_crtc
->lowfreq_avail
) {
4790 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4791 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4793 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4794 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
4798 pipeconf
&= ~PIPECONF_INTERLACE_MASK
;
4799 if (!IS_GEN2(dev
) &&
4800 adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
4801 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4803 pipeconf
|= PIPECONF_PROGRESSIVE
;
4805 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
4807 /* pipesrc and dspsize control the size that is scaled from,
4808 * which should always be the user's requested size.
4810 I915_WRITE(DSPSIZE(plane
),
4811 ((mode
->vdisplay
- 1) << 16) |
4812 (mode
->hdisplay
- 1));
4813 I915_WRITE(DSPPOS(plane
), 0);
4815 I915_WRITE(PIPECONF(pipe
), pipeconf
);
4816 POSTING_READ(PIPECONF(pipe
));
4817 intel_enable_pipe(dev_priv
, pipe
, false);
4819 intel_wait_for_vblank(dev
, pipe
);
4821 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4822 POSTING_READ(DSPCNTR(plane
));
4824 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
4826 intel_update_watermarks(dev
);
4831 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
4833 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4834 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4835 struct intel_encoder
*encoder
;
4837 bool has_lvds
= false;
4838 bool has_cpu_edp
= false;
4839 bool has_pch_edp
= false;
4840 bool has_panel
= false;
4841 bool has_ck505
= false;
4842 bool can_ssc
= false;
4844 /* We need to take the global config into account */
4845 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
4847 switch (encoder
->type
) {
4848 case INTEL_OUTPUT_LVDS
:
4852 case INTEL_OUTPUT_EDP
:
4854 if (intel_encoder_is_pch_edp(&encoder
->base
))
4862 if (HAS_PCH_IBX(dev
)) {
4863 has_ck505
= dev_priv
->display_clock_mode
;
4864 can_ssc
= has_ck505
;
4870 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4871 has_panel
, has_lvds
, has_pch_edp
, has_cpu_edp
,
4874 /* Ironlake: try to setup display ref clock before DPLL
4875 * enabling. This is only under driver's control after
4876 * PCH B stepping, previous chipset stepping should be
4877 * ignoring this setting.
4879 temp
= I915_READ(PCH_DREF_CONTROL
);
4880 /* Always enable nonspread source */
4881 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
4884 temp
|= DREF_NONSPREAD_CK505_ENABLE
;
4886 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
4889 temp
&= ~DREF_SSC_SOURCE_MASK
;
4890 temp
|= DREF_SSC_SOURCE_ENABLE
;
4892 /* SSC must be turned on before enabling the CPU output */
4893 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4894 DRM_DEBUG_KMS("Using SSC on panel\n");
4895 temp
|= DREF_SSC1_ENABLE
;
4897 temp
&= ~DREF_SSC1_ENABLE
;
4899 /* Get SSC going before enabling the outputs */
4900 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4901 POSTING_READ(PCH_DREF_CONTROL
);
4904 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4906 /* Enable CPU source on CPU attached eDP */
4908 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4909 DRM_DEBUG_KMS("Using SSC on eDP\n");
4910 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
4913 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
4915 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4917 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4918 POSTING_READ(PCH_DREF_CONTROL
);
4921 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4923 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4925 /* Turn off CPU output */
4926 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4928 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4929 POSTING_READ(PCH_DREF_CONTROL
);
4932 /* Turn off the SSC source */
4933 temp
&= ~DREF_SSC_SOURCE_MASK
;
4934 temp
|= DREF_SSC_SOURCE_DISABLE
;
4937 temp
&= ~ DREF_SSC1_ENABLE
;
4939 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4940 POSTING_READ(PCH_DREF_CONTROL
);
4945 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4946 static void lpt_init_pch_refclk(struct drm_device
*dev
)
4948 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4949 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4950 struct intel_encoder
*encoder
;
4951 bool has_vga
= false;
4952 bool is_sdv
= false;
4955 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
4956 switch (encoder
->type
) {
4957 case INTEL_OUTPUT_ANALOG
:
4966 mutex_lock(&dev_priv
->dpio_lock
);
4968 /* XXX: Rip out SDV support once Haswell ships for real. */
4969 if (IS_HASWELL(dev
) && (dev
->pci_device
& 0xFF00) == 0x0C00)
4972 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
4973 tmp
&= ~SBI_SSCCTL_DISABLE
;
4974 tmp
|= SBI_SSCCTL_PATHALT
;
4975 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
4979 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
4980 tmp
&= ~SBI_SSCCTL_PATHALT
;
4981 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
4984 tmp
= I915_READ(SOUTH_CHICKEN2
);
4985 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
4986 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
4988 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
4989 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
4990 DRM_ERROR("FDI mPHY reset assert timeout\n");
4992 tmp
= I915_READ(SOUTH_CHICKEN2
);
4993 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
4994 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
4996 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
4997 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0,
4999 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5002 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
5003 tmp
&= ~(0xFF << 24);
5004 tmp
|= (0x12 << 24);
5005 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
5008 tmp
= intel_sbi_read(dev_priv
, 0x808C, SBI_MPHY
);
5010 tmp
|= (1 << 6) | (1 << 0);
5011 intel_sbi_write(dev_priv
, 0x808C, tmp
, SBI_MPHY
);
5015 tmp
= intel_sbi_read(dev_priv
, 0x800C, SBI_MPHY
);
5017 intel_sbi_write(dev_priv
, 0x800C, tmp
, SBI_MPHY
);
5020 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
5022 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
5024 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
5026 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
5029 tmp
= intel_sbi_read(dev_priv
, 0x2038, SBI_MPHY
);
5030 tmp
|= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5031 intel_sbi_write(dev_priv
, 0x2038, tmp
, SBI_MPHY
);
5033 tmp
= intel_sbi_read(dev_priv
, 0x2138, SBI_MPHY
);
5034 tmp
|= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5035 intel_sbi_write(dev_priv
, 0x2138, tmp
, SBI_MPHY
);
5037 tmp
= intel_sbi_read(dev_priv
, 0x203C, SBI_MPHY
);
5039 intel_sbi_write(dev_priv
, 0x203C, tmp
, SBI_MPHY
);
5041 tmp
= intel_sbi_read(dev_priv
, 0x213C, SBI_MPHY
);
5043 intel_sbi_write(dev_priv
, 0x213C, tmp
, SBI_MPHY
);
5046 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
5047 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5048 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
5050 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
5051 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5052 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
5055 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
5058 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
5060 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
5063 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
5066 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
5069 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
5071 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
5074 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
5076 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
5077 tmp
&= ~(0xFF << 16);
5078 tmp
|= (0x1C << 16);
5079 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
5081 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
5082 tmp
&= ~(0xFF << 16);
5083 tmp
|= (0x1C << 16);
5084 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
5087 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
5089 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
5091 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
5093 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
5095 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
5096 tmp
&= ~(0xF << 28);
5098 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
5100 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
5101 tmp
&= ~(0xF << 28);
5103 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
5106 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5107 tmp
= intel_sbi_read(dev_priv
, SBI_DBUFF0
, SBI_ICLK
);
5108 tmp
|= SBI_DBUFF0_ENABLE
;
5109 intel_sbi_write(dev_priv
, SBI_DBUFF0
, tmp
, SBI_ICLK
);
5111 mutex_unlock(&dev_priv
->dpio_lock
);
5115 * Initialize reference clocks when the driver loads
5117 void intel_init_pch_refclk(struct drm_device
*dev
)
5119 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
5120 ironlake_init_pch_refclk(dev
);
5121 else if (HAS_PCH_LPT(dev
))
5122 lpt_init_pch_refclk(dev
);
5125 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
5127 struct drm_device
*dev
= crtc
->dev
;
5128 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5129 struct intel_encoder
*encoder
;
5130 struct intel_encoder
*edp_encoder
= NULL
;
5131 int num_connectors
= 0;
5132 bool is_lvds
= false;
5134 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5135 switch (encoder
->type
) {
5136 case INTEL_OUTPUT_LVDS
:
5139 case INTEL_OUTPUT_EDP
:
5140 edp_encoder
= encoder
;
5146 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5147 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5148 dev_priv
->lvds_ssc_freq
);
5149 return dev_priv
->lvds_ssc_freq
* 1000;
5155 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
,
5156 struct drm_display_mode
*adjusted_mode
,
5159 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5160 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5161 int pipe
= intel_crtc
->pipe
;
5164 val
= I915_READ(PIPECONF(pipe
));
5166 val
&= ~PIPECONF_BPC_MASK
;
5167 switch (intel_crtc
->bpp
) {
5169 val
|= PIPECONF_6BPC
;
5172 val
|= PIPECONF_8BPC
;
5175 val
|= PIPECONF_10BPC
;
5178 val
|= PIPECONF_12BPC
;
5181 /* Case prevented by intel_choose_pipe_bpp_dither. */
5185 val
&= ~(PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_MASK
);
5187 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5189 val
&= ~PIPECONF_INTERLACE_MASK
;
5190 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
5191 val
|= PIPECONF_INTERLACED_ILK
;
5193 val
|= PIPECONF_PROGRESSIVE
;
5195 if (adjusted_mode
->private_flags
& INTEL_MODE_LIMITED_COLOR_RANGE
)
5196 val
|= PIPECONF_COLOR_RANGE_SELECT
;
5198 val
&= ~PIPECONF_COLOR_RANGE_SELECT
;
5200 I915_WRITE(PIPECONF(pipe
), val
);
5201 POSTING_READ(PIPECONF(pipe
));
5205 * Set up the pipe CSC unit.
5207 * Currently only full range RGB to limited range RGB conversion
5208 * is supported, but eventually this should handle various
5209 * RGB<->YCbCr scenarios as well.
5211 static void intel_set_pipe_csc(struct drm_crtc
*crtc
,
5212 const struct drm_display_mode
*adjusted_mode
)
5214 struct drm_device
*dev
= crtc
->dev
;
5215 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5216 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5217 int pipe
= intel_crtc
->pipe
;
5218 uint16_t coeff
= 0x7800; /* 1.0 */
5221 * TODO: Check what kind of values actually come out of the pipe
5222 * with these coeff/postoff values and adjust to get the best
5223 * accuracy. Perhaps we even need to take the bpc value into
5227 if (adjusted_mode
->private_flags
& INTEL_MODE_LIMITED_COLOR_RANGE
)
5228 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5231 * GY/GU and RY/RU should be the other way around according
5232 * to BSpec, but reality doesn't agree. Just set them up in
5233 * a way that results in the correct picture.
5235 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
5236 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
5238 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
5239 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
5241 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
5242 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
5244 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
5245 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
5246 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
5248 if (INTEL_INFO(dev
)->gen
> 6) {
5249 uint16_t postoff
= 0;
5251 if (adjusted_mode
->private_flags
& INTEL_MODE_LIMITED_COLOR_RANGE
)
5252 postoff
= (16 * (1 << 13) / 255) & 0x1fff;
5254 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
5255 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
5256 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
5258 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
5260 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
5262 if (adjusted_mode
->private_flags
& INTEL_MODE_LIMITED_COLOR_RANGE
)
5263 mode
|= CSC_BLACK_SCREEN_OFFSET
;
5265 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
5269 static void haswell_set_pipeconf(struct drm_crtc
*crtc
,
5270 struct drm_display_mode
*adjusted_mode
,
5273 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5274 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5275 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
5278 val
= I915_READ(PIPECONF(cpu_transcoder
));
5280 val
&= ~(PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_MASK
);
5282 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5284 val
&= ~PIPECONF_INTERLACE_MASK_HSW
;
5285 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
5286 val
|= PIPECONF_INTERLACED_ILK
;
5288 val
|= PIPECONF_PROGRESSIVE
;
5290 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
5291 POSTING_READ(PIPECONF(cpu_transcoder
));
5294 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
5295 struct drm_display_mode
*adjusted_mode
,
5296 intel_clock_t
*clock
,
5297 bool *has_reduced_clock
,
5298 intel_clock_t
*reduced_clock
)
5300 struct drm_device
*dev
= crtc
->dev
;
5301 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5302 struct intel_encoder
*intel_encoder
;
5304 const intel_limit_t
*limit
;
5305 bool ret
, is_sdvo
= false, is_tv
= false, is_lvds
= false;
5307 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5308 switch (intel_encoder
->type
) {
5309 case INTEL_OUTPUT_LVDS
:
5312 case INTEL_OUTPUT_SDVO
:
5313 case INTEL_OUTPUT_HDMI
:
5315 if (intel_encoder
->needs_tv_clock
)
5318 case INTEL_OUTPUT_TVOUT
:
5324 refclk
= ironlake_get_refclk(crtc
);
5327 * Returns a set of divisors for the desired target clock with the given
5328 * refclk, or FALSE. The returned values represent the clock equation:
5329 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5331 limit
= intel_limit(crtc
, refclk
);
5332 ret
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
5337 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5339 * Ensure we match the reduced clock's P to the target clock.
5340 * If the clocks don't match, we can't switch the display clock
5341 * by using the FP0/FP1. In such case we will disable the LVDS
5342 * downclock feature.
5344 *has_reduced_clock
= limit
->find_pll(limit
, crtc
,
5345 dev_priv
->lvds_downclock
,
5351 if (is_sdvo
&& is_tv
)
5352 i9xx_adjust_sdvo_tv_clock(adjusted_mode
, clock
);
5357 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
5359 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5362 temp
= I915_READ(SOUTH_CHICKEN1
);
5363 if (temp
& FDI_BC_BIFURCATION_SELECT
)
5366 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
5367 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
5369 temp
|= FDI_BC_BIFURCATION_SELECT
;
5370 DRM_DEBUG_KMS("enabling fdi C rx\n");
5371 I915_WRITE(SOUTH_CHICKEN1
, temp
);
5372 POSTING_READ(SOUTH_CHICKEN1
);
5375 static bool ironlake_check_fdi_lanes(struct intel_crtc
*intel_crtc
)
5377 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5378 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5379 struct intel_crtc
*pipe_B_crtc
=
5380 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
5382 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5383 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5384 if (intel_crtc
->fdi_lanes
> 4) {
5385 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5386 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5387 /* Clamp lanes to avoid programming the hw with bogus values. */
5388 intel_crtc
->fdi_lanes
= 4;
5393 if (INTEL_INFO(dev
)->num_pipes
== 2)
5396 switch (intel_crtc
->pipe
) {
5400 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
5401 intel_crtc
->fdi_lanes
> 2) {
5402 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5403 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5404 /* Clamp lanes to avoid programming the hw with bogus values. */
5405 intel_crtc
->fdi_lanes
= 2;
5410 if (intel_crtc
->fdi_lanes
> 2)
5411 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
5413 cpt_enable_fdi_bc_bifurcation(dev
);
5417 if (!pipe_B_crtc
->base
.enabled
|| pipe_B_crtc
->fdi_lanes
<= 2) {
5418 if (intel_crtc
->fdi_lanes
> 2) {
5419 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5420 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5421 /* Clamp lanes to avoid programming the hw with bogus values. */
5422 intel_crtc
->fdi_lanes
= 2;
5427 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5431 cpt_enable_fdi_bc_bifurcation(dev
);
5439 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
5442 * Account for spread spectrum to avoid
5443 * oversubscribing the link. Max center spread
5444 * is 2.5%; use 5% for safety's sake.
5446 u32 bps
= target_clock
* bpp
* 21 / 20;
5447 return bps
/ (link_bw
* 8) + 1;
5450 static void ironlake_set_m_n(struct drm_crtc
*crtc
,
5451 struct drm_display_mode
*mode
,
5452 struct drm_display_mode
*adjusted_mode
)
5454 struct drm_device
*dev
= crtc
->dev
;
5455 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5456 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5457 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
5458 struct intel_encoder
*intel_encoder
, *edp_encoder
= NULL
;
5459 struct intel_link_m_n m_n
= {0};
5460 int target_clock
, pixel_multiplier
, lane
, link_bw
;
5461 bool is_dp
= false, is_cpu_edp
= false;
5463 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5464 switch (intel_encoder
->type
) {
5465 case INTEL_OUTPUT_DISPLAYPORT
:
5468 case INTEL_OUTPUT_EDP
:
5470 if (!intel_encoder_is_pch_edp(&intel_encoder
->base
))
5472 edp_encoder
= intel_encoder
;
5478 pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
5480 /* CPU eDP doesn't require FDI link, so just set DP M/N
5481 according to current link config */
5483 intel_edp_link_config(edp_encoder
, &lane
, &link_bw
);
5485 /* FDI is a binary signal running at ~2.7GHz, encoding
5486 * each output octet as 10 bits. The actual frequency
5487 * is stored as a divider into a 100MHz clock, and the
5488 * mode pixel clock is stored in units of 1KHz.
5489 * Hence the bw of each lane in terms of the mode signal
5492 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5495 /* [e]DP over FDI requires target mode clock instead of link clock. */
5497 target_clock
= intel_edp_target_clock(edp_encoder
, mode
);
5499 target_clock
= mode
->clock
;
5501 target_clock
= adjusted_mode
->clock
;
5504 lane
= ironlake_get_lanes_required(target_clock
, link_bw
,
5507 intel_crtc
->fdi_lanes
= lane
;
5509 if (pixel_multiplier
> 1)
5510 link_bw
*= pixel_multiplier
;
5511 intel_link_compute_m_n(intel_crtc
->bpp
, lane
, target_clock
, link_bw
, &m_n
);
5513 I915_WRITE(PIPE_DATA_M1(cpu_transcoder
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
5514 I915_WRITE(PIPE_DATA_N1(cpu_transcoder
), m_n
.gmch_n
);
5515 I915_WRITE(PIPE_LINK_M1(cpu_transcoder
), m_n
.link_m
);
5516 I915_WRITE(PIPE_LINK_N1(cpu_transcoder
), m_n
.link_n
);
5519 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
5520 struct drm_display_mode
*adjusted_mode
,
5521 intel_clock_t
*clock
, u32 fp
)
5523 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5524 struct drm_device
*dev
= crtc
->dev
;
5525 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5526 struct intel_encoder
*intel_encoder
;
5528 int factor
, pixel_multiplier
, num_connectors
= 0;
5529 bool is_lvds
= false, is_sdvo
= false, is_tv
= false;
5530 bool is_dp
= false, is_cpu_edp
= false;
5532 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5533 switch (intel_encoder
->type
) {
5534 case INTEL_OUTPUT_LVDS
:
5537 case INTEL_OUTPUT_SDVO
:
5538 case INTEL_OUTPUT_HDMI
:
5540 if (intel_encoder
->needs_tv_clock
)
5543 case INTEL_OUTPUT_TVOUT
:
5546 case INTEL_OUTPUT_DISPLAYPORT
:
5549 case INTEL_OUTPUT_EDP
:
5551 if (!intel_encoder_is_pch_edp(&intel_encoder
->base
))
5559 /* Enable autotuning of the PLL clock (if permissible) */
5562 if ((intel_panel_use_ssc(dev_priv
) &&
5563 dev_priv
->lvds_ssc_freq
== 100) ||
5564 intel_is_dual_link_lvds(dev
))
5566 } else if (is_sdvo
&& is_tv
)
5569 if (clock
->m
< factor
* clock
->n
)
5575 dpll
|= DPLLB_MODE_LVDS
;
5577 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5579 pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
5580 if (pixel_multiplier
> 1) {
5581 dpll
|= (pixel_multiplier
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
5583 dpll
|= DPLL_DVO_HIGH_SPEED
;
5585 if (is_dp
&& !is_cpu_edp
)
5586 dpll
|= DPLL_DVO_HIGH_SPEED
;
5588 /* compute bitmask from p1 value */
5589 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5591 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5593 switch (clock
->p2
) {
5595 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5598 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5601 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5604 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5608 if (is_sdvo
&& is_tv
)
5609 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
5611 /* XXX: just matching BIOS for now */
5612 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5614 else if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5615 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5617 dpll
|= PLL_REF_INPUT_DREFCLK
;
5622 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
5623 struct drm_display_mode
*mode
,
5624 struct drm_display_mode
*adjusted_mode
,
5626 struct drm_framebuffer
*fb
)
5628 struct drm_device
*dev
= crtc
->dev
;
5629 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5630 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5631 int pipe
= intel_crtc
->pipe
;
5632 int plane
= intel_crtc
->plane
;
5633 int num_connectors
= 0;
5634 intel_clock_t clock
, reduced_clock
;
5635 u32 dpll
, fp
= 0, fp2
= 0;
5636 bool ok
, has_reduced_clock
= false;
5637 bool is_lvds
= false, is_dp
= false, is_cpu_edp
= false;
5638 struct intel_encoder
*encoder
;
5640 bool dither
, fdi_config_ok
;
5642 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5643 switch (encoder
->type
) {
5644 case INTEL_OUTPUT_LVDS
:
5647 case INTEL_OUTPUT_DISPLAYPORT
:
5650 case INTEL_OUTPUT_EDP
:
5652 if (!intel_encoder_is_pch_edp(&encoder
->base
))
5660 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
5661 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
5663 ok
= ironlake_compute_clocks(crtc
, adjusted_mode
, &clock
,
5664 &has_reduced_clock
, &reduced_clock
);
5666 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5670 /* Ensure that the cursor is valid for the new mode before changing... */
5671 intel_crtc_update_cursor(crtc
, true);
5673 /* determine panel color depth */
5674 dither
= intel_choose_pipe_bpp_dither(crtc
, fb
, &intel_crtc
->bpp
,
5676 if (is_lvds
&& dev_priv
->lvds_dither
)
5679 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
5680 if (has_reduced_clock
)
5681 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
5684 dpll
= ironlake_compute_dpll(intel_crtc
, adjusted_mode
, &clock
, fp
);
5686 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe
);
5687 drm_mode_debug_printmodeline(mode
);
5689 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5691 struct intel_pch_pll
*pll
;
5693 pll
= intel_get_pch_pll(intel_crtc
, dpll
, fp
);
5695 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5700 intel_put_pch_pll(intel_crtc
);
5702 if (is_dp
&& !is_cpu_edp
)
5703 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
5705 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5706 if (encoder
->pre_pll_enable
)
5707 encoder
->pre_pll_enable(encoder
);
5709 if (intel_crtc
->pch_pll
) {
5710 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5712 /* Wait for the clocks to stabilize. */
5713 POSTING_READ(intel_crtc
->pch_pll
->pll_reg
);
5716 /* The pixel multiplier can only be updated once the
5717 * DPLL is enabled and the clocks are stable.
5719 * So write it again.
5721 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5724 intel_crtc
->lowfreq_avail
= false;
5725 if (intel_crtc
->pch_pll
) {
5726 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
5727 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp2
);
5728 intel_crtc
->lowfreq_avail
= true;
5730 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp
);
5734 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
5736 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5737 * ironlake_check_fdi_lanes. */
5738 ironlake_set_m_n(crtc
, mode
, adjusted_mode
);
5740 fdi_config_ok
= ironlake_check_fdi_lanes(intel_crtc
);
5742 ironlake_set_pipeconf(crtc
, adjusted_mode
, dither
);
5744 intel_wait_for_vblank(dev
, pipe
);
5746 /* Set up the display plane register */
5747 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
5748 POSTING_READ(DSPCNTR(plane
));
5750 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5752 intel_update_watermarks(dev
);
5754 intel_update_linetime_watermarks(dev
, pipe
, adjusted_mode
);
5756 return fdi_config_ok
? ret
: -EINVAL
;
5759 static void haswell_modeset_global_resources(struct drm_device
*dev
)
5761 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5762 bool enable
= false;
5763 struct intel_crtc
*crtc
;
5764 struct intel_encoder
*encoder
;
5766 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
5767 if (crtc
->pipe
!= PIPE_A
&& crtc
->base
.enabled
)
5769 /* XXX: Should check for edp transcoder here, but thanks to init
5770 * sequence that's not yet available. Just in case desktop eDP
5771 * on PORT D is possible on haswell, too. */
5774 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
5776 if (encoder
->type
!= INTEL_OUTPUT_EDP
&&
5777 encoder
->connectors_active
)
5781 /* Even the eDP panel fitter is outside the always-on well. */
5782 if (dev_priv
->pch_pf_size
)
5785 intel_set_power_well(dev
, enable
);
5788 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
5789 struct drm_display_mode
*mode
,
5790 struct drm_display_mode
*adjusted_mode
,
5792 struct drm_framebuffer
*fb
)
5794 struct drm_device
*dev
= crtc
->dev
;
5795 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5796 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5797 int pipe
= intel_crtc
->pipe
;
5798 int plane
= intel_crtc
->plane
;
5799 int num_connectors
= 0;
5800 bool is_dp
= false, is_cpu_edp
= false;
5801 struct intel_encoder
*encoder
;
5805 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5806 switch (encoder
->type
) {
5807 case INTEL_OUTPUT_DISPLAYPORT
:
5810 case INTEL_OUTPUT_EDP
:
5812 if (!intel_encoder_is_pch_edp(&encoder
->base
))
5820 /* We are not sure yet this won't happen. */
5821 WARN(!HAS_PCH_LPT(dev
), "Unexpected PCH type %d\n",
5822 INTEL_PCH_TYPE(dev
));
5824 WARN(num_connectors
!= 1, "%d connectors attached to pipe %c\n",
5825 num_connectors
, pipe_name(pipe
));
5827 WARN_ON(I915_READ(PIPECONF(intel_crtc
->cpu_transcoder
)) &
5828 (PIPECONF_ENABLE
| I965_PIPECONF_ACTIVE
));
5830 WARN_ON(I915_READ(DSPCNTR(plane
)) & DISPLAY_PLANE_ENABLE
);
5832 if (!intel_ddi_pll_mode_set(crtc
, adjusted_mode
->clock
))
5835 /* Ensure that the cursor is valid for the new mode before changing... */
5836 intel_crtc_update_cursor(crtc
, true);
5838 /* determine panel color depth */
5839 dither
= intel_choose_pipe_bpp_dither(crtc
, fb
, &intel_crtc
->bpp
,
5842 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe
);
5843 drm_mode_debug_printmodeline(mode
);
5845 if (is_dp
&& !is_cpu_edp
)
5846 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
5848 intel_crtc
->lowfreq_avail
= false;
5850 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
5852 if (!is_dp
|| is_cpu_edp
)
5853 ironlake_set_m_n(crtc
, mode
, adjusted_mode
);
5855 haswell_set_pipeconf(crtc
, adjusted_mode
, dither
);
5857 intel_set_pipe_csc(crtc
, adjusted_mode
);
5859 /* Set up the display plane register */
5860 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
| DISPPLANE_PIPE_CSC_ENABLE
);
5861 POSTING_READ(DSPCNTR(plane
));
5863 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5865 intel_update_watermarks(dev
);
5867 intel_update_linetime_watermarks(dev
, pipe
, adjusted_mode
);
5872 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
5873 struct drm_display_mode
*mode
,
5874 struct drm_display_mode
*adjusted_mode
,
5876 struct drm_framebuffer
*fb
)
5878 struct drm_device
*dev
= crtc
->dev
;
5879 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5880 struct drm_encoder_helper_funcs
*encoder_funcs
;
5881 struct intel_encoder
*encoder
;
5882 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5883 int pipe
= intel_crtc
->pipe
;
5886 if (IS_HASWELL(dev
) && intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
5887 intel_crtc
->cpu_transcoder
= TRANSCODER_EDP
;
5889 intel_crtc
->cpu_transcoder
= pipe
;
5891 drm_vblank_pre_modeset(dev
, pipe
);
5893 ret
= dev_priv
->display
.crtc_mode_set(crtc
, mode
, adjusted_mode
,
5895 drm_vblank_post_modeset(dev
, pipe
);
5900 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5901 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5902 encoder
->base
.base
.id
,
5903 drm_get_encoder_name(&encoder
->base
),
5904 mode
->base
.id
, mode
->name
);
5905 encoder_funcs
= encoder
->base
.helper_private
;
5906 encoder_funcs
->mode_set(&encoder
->base
, mode
, adjusted_mode
);
5912 static bool intel_eld_uptodate(struct drm_connector
*connector
,
5913 int reg_eldv
, uint32_t bits_eldv
,
5914 int reg_elda
, uint32_t bits_elda
,
5917 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5918 uint8_t *eld
= connector
->eld
;
5921 i
= I915_READ(reg_eldv
);
5930 i
= I915_READ(reg_elda
);
5932 I915_WRITE(reg_elda
, i
);
5934 for (i
= 0; i
< eld
[2]; i
++)
5935 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
5941 static void g4x_write_eld(struct drm_connector
*connector
,
5942 struct drm_crtc
*crtc
)
5944 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5945 uint8_t *eld
= connector
->eld
;
5950 i
= I915_READ(G4X_AUD_VID_DID
);
5952 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
5953 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
5955 eldv
= G4X_ELDV_DEVCTG
;
5957 if (intel_eld_uptodate(connector
,
5958 G4X_AUD_CNTL_ST
, eldv
,
5959 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
5960 G4X_HDMIW_HDMIEDID
))
5963 i
= I915_READ(G4X_AUD_CNTL_ST
);
5964 i
&= ~(eldv
| G4X_ELD_ADDR
);
5965 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
5966 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5971 len
= min_t(uint8_t, eld
[2], len
);
5972 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5973 for (i
= 0; i
< len
; i
++)
5974 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
5976 i
= I915_READ(G4X_AUD_CNTL_ST
);
5978 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5981 static void haswell_write_eld(struct drm_connector
*connector
,
5982 struct drm_crtc
*crtc
)
5984 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5985 uint8_t *eld
= connector
->eld
;
5986 struct drm_device
*dev
= crtc
->dev
;
5987 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5991 int pipe
= to_intel_crtc(crtc
)->pipe
;
5994 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
5995 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
5996 int aud_config
= HSW_AUD_CFG(pipe
);
5997 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
6000 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6002 /* Audio output enable */
6003 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6004 tmp
= I915_READ(aud_cntrl_st2
);
6005 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
6006 I915_WRITE(aud_cntrl_st2
, tmp
);
6008 /* Wait for 1 vertical blank */
6009 intel_wait_for_vblank(dev
, pipe
);
6011 /* Set ELD valid state */
6012 tmp
= I915_READ(aud_cntrl_st2
);
6013 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp
);
6014 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
6015 I915_WRITE(aud_cntrl_st2
, tmp
);
6016 tmp
= I915_READ(aud_cntrl_st2
);
6017 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp
);
6019 /* Enable HDMI mode */
6020 tmp
= I915_READ(aud_config
);
6021 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp
);
6022 /* clear N_programing_enable and N_value_index */
6023 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
6024 I915_WRITE(aud_config
, tmp
);
6026 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6028 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
6029 intel_crtc
->eld_vld
= true;
6031 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6032 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6033 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6034 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6036 I915_WRITE(aud_config
, 0);
6038 if (intel_eld_uptodate(connector
,
6039 aud_cntrl_st2
, eldv
,
6040 aud_cntl_st
, IBX_ELD_ADDRESS
,
6044 i
= I915_READ(aud_cntrl_st2
);
6046 I915_WRITE(aud_cntrl_st2
, i
);
6051 i
= I915_READ(aud_cntl_st
);
6052 i
&= ~IBX_ELD_ADDRESS
;
6053 I915_WRITE(aud_cntl_st
, i
);
6054 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6055 DRM_DEBUG_DRIVER("port num:%d\n", i
);
6057 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6058 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6059 for (i
= 0; i
< len
; i
++)
6060 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6062 i
= I915_READ(aud_cntrl_st2
);
6064 I915_WRITE(aud_cntrl_st2
, i
);
6068 static void ironlake_write_eld(struct drm_connector
*connector
,
6069 struct drm_crtc
*crtc
)
6071 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6072 uint8_t *eld
= connector
->eld
;
6080 int pipe
= to_intel_crtc(crtc
)->pipe
;
6082 if (HAS_PCH_IBX(connector
->dev
)) {
6083 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
6084 aud_config
= IBX_AUD_CFG(pipe
);
6085 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
6086 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
6088 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
6089 aud_config
= CPT_AUD_CFG(pipe
);
6090 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
6091 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
6094 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6096 i
= I915_READ(aud_cntl_st
);
6097 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6099 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6100 /* operate blindly on all ports */
6101 eldv
= IBX_ELD_VALIDB
;
6102 eldv
|= IBX_ELD_VALIDB
<< 4;
6103 eldv
|= IBX_ELD_VALIDB
<< 8;
6105 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i
);
6106 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
6109 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6110 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6111 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6112 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6114 I915_WRITE(aud_config
, 0);
6116 if (intel_eld_uptodate(connector
,
6117 aud_cntrl_st2
, eldv
,
6118 aud_cntl_st
, IBX_ELD_ADDRESS
,
6122 i
= I915_READ(aud_cntrl_st2
);
6124 I915_WRITE(aud_cntrl_st2
, i
);
6129 i
= I915_READ(aud_cntl_st
);
6130 i
&= ~IBX_ELD_ADDRESS
;
6131 I915_WRITE(aud_cntl_st
, i
);
6133 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6134 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6135 for (i
= 0; i
< len
; i
++)
6136 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6138 i
= I915_READ(aud_cntrl_st2
);
6140 I915_WRITE(aud_cntrl_st2
, i
);
6143 void intel_write_eld(struct drm_encoder
*encoder
,
6144 struct drm_display_mode
*mode
)
6146 struct drm_crtc
*crtc
= encoder
->crtc
;
6147 struct drm_connector
*connector
;
6148 struct drm_device
*dev
= encoder
->dev
;
6149 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6151 connector
= drm_select_eld(encoder
, mode
);
6155 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6157 drm_get_connector_name(connector
),
6158 connector
->encoder
->base
.id
,
6159 drm_get_encoder_name(connector
->encoder
));
6161 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
6163 if (dev_priv
->display
.write_eld
)
6164 dev_priv
->display
.write_eld(connector
, crtc
);
6167 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6168 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
6170 struct drm_device
*dev
= crtc
->dev
;
6171 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6172 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6173 int palreg
= PALETTE(intel_crtc
->pipe
);
6176 /* The clocks have to be on to load the palette. */
6177 if (!crtc
->enabled
|| !intel_crtc
->active
)
6180 /* use legacy palette for Ironlake */
6181 if (HAS_PCH_SPLIT(dev
))
6182 palreg
= LGC_PALETTE(intel_crtc
->pipe
);
6184 for (i
= 0; i
< 256; i
++) {
6185 I915_WRITE(palreg
+ 4 * i
,
6186 (intel_crtc
->lut_r
[i
] << 16) |
6187 (intel_crtc
->lut_g
[i
] << 8) |
6188 intel_crtc
->lut_b
[i
]);
6192 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6194 struct drm_device
*dev
= crtc
->dev
;
6195 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6196 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6197 bool visible
= base
!= 0;
6200 if (intel_crtc
->cursor_visible
== visible
)
6203 cntl
= I915_READ(_CURACNTR
);
6205 /* On these chipsets we can only modify the base whilst
6206 * the cursor is disabled.
6208 I915_WRITE(_CURABASE
, base
);
6210 cntl
&= ~(CURSOR_FORMAT_MASK
);
6211 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6212 cntl
|= CURSOR_ENABLE
|
6213 CURSOR_GAMMA_ENABLE
|
6216 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
6217 I915_WRITE(_CURACNTR
, cntl
);
6219 intel_crtc
->cursor_visible
= visible
;
6222 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6224 struct drm_device
*dev
= crtc
->dev
;
6225 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6226 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6227 int pipe
= intel_crtc
->pipe
;
6228 bool visible
= base
!= 0;
6230 if (intel_crtc
->cursor_visible
!= visible
) {
6231 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
6233 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
6234 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6235 cntl
|= pipe
<< 28; /* Connect to correct pipe */
6237 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6238 cntl
|= CURSOR_MODE_DISABLE
;
6240 I915_WRITE(CURCNTR(pipe
), cntl
);
6242 intel_crtc
->cursor_visible
= visible
;
6244 /* and commit changes on next vblank */
6245 I915_WRITE(CURBASE(pipe
), base
);
6248 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6250 struct drm_device
*dev
= crtc
->dev
;
6251 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6252 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6253 int pipe
= intel_crtc
->pipe
;
6254 bool visible
= base
!= 0;
6256 if (intel_crtc
->cursor_visible
!= visible
) {
6257 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
6259 cntl
&= ~CURSOR_MODE
;
6260 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6262 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6263 cntl
|= CURSOR_MODE_DISABLE
;
6265 if (IS_HASWELL(dev
))
6266 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
6267 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
6269 intel_crtc
->cursor_visible
= visible
;
6271 /* and commit changes on next vblank */
6272 I915_WRITE(CURBASE_IVB(pipe
), base
);
6275 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6276 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
6279 struct drm_device
*dev
= crtc
->dev
;
6280 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6281 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6282 int pipe
= intel_crtc
->pipe
;
6283 int x
= intel_crtc
->cursor_x
;
6284 int y
= intel_crtc
->cursor_y
;
6290 if (on
&& crtc
->enabled
&& crtc
->fb
) {
6291 base
= intel_crtc
->cursor_addr
;
6292 if (x
> (int) crtc
->fb
->width
)
6295 if (y
> (int) crtc
->fb
->height
)
6301 if (x
+ intel_crtc
->cursor_width
< 0)
6304 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
6307 pos
|= x
<< CURSOR_X_SHIFT
;
6310 if (y
+ intel_crtc
->cursor_height
< 0)
6313 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
6316 pos
|= y
<< CURSOR_Y_SHIFT
;
6318 visible
= base
!= 0;
6319 if (!visible
&& !intel_crtc
->cursor_visible
)
6322 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
6323 I915_WRITE(CURPOS_IVB(pipe
), pos
);
6324 ivb_update_cursor(crtc
, base
);
6326 I915_WRITE(CURPOS(pipe
), pos
);
6327 if (IS_845G(dev
) || IS_I865G(dev
))
6328 i845_update_cursor(crtc
, base
);
6330 i9xx_update_cursor(crtc
, base
);
6334 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
6335 struct drm_file
*file
,
6337 uint32_t width
, uint32_t height
)
6339 struct drm_device
*dev
= crtc
->dev
;
6340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6341 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6342 struct drm_i915_gem_object
*obj
;
6346 /* if we want to turn off the cursor ignore width and height */
6348 DRM_DEBUG_KMS("cursor off\n");
6351 mutex_lock(&dev
->struct_mutex
);
6355 /* Currently we only support 64x64 cursors */
6356 if (width
!= 64 || height
!= 64) {
6357 DRM_ERROR("we currently only support 64x64 cursors\n");
6361 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
6362 if (&obj
->base
== NULL
)
6365 if (obj
->base
.size
< width
* height
* 4) {
6366 DRM_ERROR("buffer is to small\n");
6371 /* we only need to pin inside GTT if cursor is non-phy */
6372 mutex_lock(&dev
->struct_mutex
);
6373 if (!dev_priv
->info
->cursor_needs_physical
) {
6374 if (obj
->tiling_mode
) {
6375 DRM_ERROR("cursor cannot be tiled\n");
6380 ret
= i915_gem_object_pin_to_display_plane(obj
, 0, NULL
);
6382 DRM_ERROR("failed to move cursor bo into the GTT\n");
6386 ret
= i915_gem_object_put_fence(obj
);
6388 DRM_ERROR("failed to release fence for cursor");
6392 addr
= obj
->gtt_offset
;
6394 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
6395 ret
= i915_gem_attach_phys_object(dev
, obj
,
6396 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
6399 DRM_ERROR("failed to attach phys object\n");
6402 addr
= obj
->phys_obj
->handle
->busaddr
;
6406 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
6409 if (intel_crtc
->cursor_bo
) {
6410 if (dev_priv
->info
->cursor_needs_physical
) {
6411 if (intel_crtc
->cursor_bo
!= obj
)
6412 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
6414 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
6415 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
6418 mutex_unlock(&dev
->struct_mutex
);
6420 intel_crtc
->cursor_addr
= addr
;
6421 intel_crtc
->cursor_bo
= obj
;
6422 intel_crtc
->cursor_width
= width
;
6423 intel_crtc
->cursor_height
= height
;
6425 intel_crtc_update_cursor(crtc
, true);
6429 i915_gem_object_unpin(obj
);
6431 mutex_unlock(&dev
->struct_mutex
);
6433 drm_gem_object_unreference_unlocked(&obj
->base
);
6437 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
6439 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6441 intel_crtc
->cursor_x
= x
;
6442 intel_crtc
->cursor_y
= y
;
6444 intel_crtc_update_cursor(crtc
, true);
6449 /** Sets the color ramps on behalf of RandR */
6450 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
6451 u16 blue
, int regno
)
6453 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6455 intel_crtc
->lut_r
[regno
] = red
>> 8;
6456 intel_crtc
->lut_g
[regno
] = green
>> 8;
6457 intel_crtc
->lut_b
[regno
] = blue
>> 8;
6460 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6461 u16
*blue
, int regno
)
6463 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6465 *red
= intel_crtc
->lut_r
[regno
] << 8;
6466 *green
= intel_crtc
->lut_g
[regno
] << 8;
6467 *blue
= intel_crtc
->lut_b
[regno
] << 8;
6470 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6471 u16
*blue
, uint32_t start
, uint32_t size
)
6473 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
6474 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6476 for (i
= start
; i
< end
; i
++) {
6477 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
6478 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
6479 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
6482 intel_crtc_load_lut(crtc
);
6485 /* VESA 640x480x72Hz mode to set on the pipe */
6486 static struct drm_display_mode load_detect_mode
= {
6487 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
6488 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
6491 static struct drm_framebuffer
*
6492 intel_framebuffer_create(struct drm_device
*dev
,
6493 struct drm_mode_fb_cmd2
*mode_cmd
,
6494 struct drm_i915_gem_object
*obj
)
6496 struct intel_framebuffer
*intel_fb
;
6499 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
6501 drm_gem_object_unreference_unlocked(&obj
->base
);
6502 return ERR_PTR(-ENOMEM
);
6505 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
6507 drm_gem_object_unreference_unlocked(&obj
->base
);
6509 return ERR_PTR(ret
);
6512 return &intel_fb
->base
;
6516 intel_framebuffer_pitch_for_width(int width
, int bpp
)
6518 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
6519 return ALIGN(pitch
, 64);
6523 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
6525 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
6526 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
6529 static struct drm_framebuffer
*
6530 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
6531 struct drm_display_mode
*mode
,
6534 struct drm_i915_gem_object
*obj
;
6535 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
6537 obj
= i915_gem_alloc_object(dev
,
6538 intel_framebuffer_size_for_mode(mode
, bpp
));
6540 return ERR_PTR(-ENOMEM
);
6542 mode_cmd
.width
= mode
->hdisplay
;
6543 mode_cmd
.height
= mode
->vdisplay
;
6544 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
6546 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
6548 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
6551 static struct drm_framebuffer
*
6552 mode_fits_in_fbdev(struct drm_device
*dev
,
6553 struct drm_display_mode
*mode
)
6555 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6556 struct drm_i915_gem_object
*obj
;
6557 struct drm_framebuffer
*fb
;
6559 if (dev_priv
->fbdev
== NULL
)
6562 obj
= dev_priv
->fbdev
->ifb
.obj
;
6566 fb
= &dev_priv
->fbdev
->ifb
.base
;
6567 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
6568 fb
->bits_per_pixel
))
6571 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
6577 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
6578 struct drm_display_mode
*mode
,
6579 struct intel_load_detect_pipe
*old
)
6581 struct intel_crtc
*intel_crtc
;
6582 struct intel_encoder
*intel_encoder
=
6583 intel_attached_encoder(connector
);
6584 struct drm_crtc
*possible_crtc
;
6585 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6586 struct drm_crtc
*crtc
= NULL
;
6587 struct drm_device
*dev
= encoder
->dev
;
6588 struct drm_framebuffer
*fb
;
6591 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6592 connector
->base
.id
, drm_get_connector_name(connector
),
6593 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6596 * Algorithm gets a little messy:
6598 * - if the connector already has an assigned crtc, use it (but make
6599 * sure it's on first)
6601 * - try to find the first unused crtc that can drive this connector,
6602 * and use that if we find one
6605 /* See if we already have a CRTC for this connector */
6606 if (encoder
->crtc
) {
6607 crtc
= encoder
->crtc
;
6609 mutex_lock(&crtc
->mutex
);
6611 old
->dpms_mode
= connector
->dpms
;
6612 old
->load_detect_temp
= false;
6614 /* Make sure the crtc and connector are running */
6615 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
6616 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
6621 /* Find an unused one (if possible) */
6622 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
6624 if (!(encoder
->possible_crtcs
& (1 << i
)))
6626 if (!possible_crtc
->enabled
) {
6627 crtc
= possible_crtc
;
6633 * If we didn't find an unused CRTC, don't use any.
6636 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6640 mutex_lock(&crtc
->mutex
);
6641 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
6642 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
6644 intel_crtc
= to_intel_crtc(crtc
);
6645 old
->dpms_mode
= connector
->dpms
;
6646 old
->load_detect_temp
= true;
6647 old
->release_fb
= NULL
;
6650 mode
= &load_detect_mode
;
6652 /* We need a framebuffer large enough to accommodate all accesses
6653 * that the plane may generate whilst we perform load detection.
6654 * We can not rely on the fbcon either being present (we get called
6655 * during its initialisation to detect all boot displays, or it may
6656 * not even exist) or that it is large enough to satisfy the
6659 fb
= mode_fits_in_fbdev(dev
, mode
);
6661 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6662 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
6663 old
->release_fb
= fb
;
6665 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6667 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6668 mutex_unlock(&crtc
->mutex
);
6672 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
6673 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6674 if (old
->release_fb
)
6675 old
->release_fb
->funcs
->destroy(old
->release_fb
);
6676 mutex_unlock(&crtc
->mutex
);
6680 /* let the connector get through one full cycle before testing */
6681 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
6685 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
6686 struct intel_load_detect_pipe
*old
)
6688 struct intel_encoder
*intel_encoder
=
6689 intel_attached_encoder(connector
);
6690 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6691 struct drm_crtc
*crtc
= encoder
->crtc
;
6693 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6694 connector
->base
.id
, drm_get_connector_name(connector
),
6695 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6697 if (old
->load_detect_temp
) {
6698 to_intel_connector(connector
)->new_encoder
= NULL
;
6699 intel_encoder
->new_crtc
= NULL
;
6700 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
6702 if (old
->release_fb
) {
6703 drm_framebuffer_unregister_private(old
->release_fb
);
6704 drm_framebuffer_unreference(old
->release_fb
);
6707 mutex_unlock(&crtc
->mutex
);
6711 /* Switch crtc and encoder back off if necessary */
6712 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
6713 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
6715 mutex_unlock(&crtc
->mutex
);
6718 /* Returns the clock of the currently programmed mode of the given pipe. */
6719 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
6721 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6722 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6723 int pipe
= intel_crtc
->pipe
;
6724 u32 dpll
= I915_READ(DPLL(pipe
));
6726 intel_clock_t clock
;
6728 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
6729 fp
= I915_READ(FP0(pipe
));
6731 fp
= I915_READ(FP1(pipe
));
6733 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
6734 if (IS_PINEVIEW(dev
)) {
6735 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
6736 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6738 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
6739 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6742 if (!IS_GEN2(dev
)) {
6743 if (IS_PINEVIEW(dev
))
6744 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
6745 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
6747 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
6748 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6750 switch (dpll
& DPLL_MODE_MASK
) {
6751 case DPLLB_MODE_DAC_SERIAL
:
6752 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
6755 case DPLLB_MODE_LVDS
:
6756 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
6760 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6761 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
6765 /* XXX: Handle the 100Mhz refclk */
6766 intel_clock(dev
, 96000, &clock
);
6768 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
6771 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
6772 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6775 if ((dpll
& PLL_REF_INPUT_MASK
) ==
6776 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
6777 /* XXX: might not be 66MHz */
6778 intel_clock(dev
, 66000, &clock
);
6780 intel_clock(dev
, 48000, &clock
);
6782 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
6785 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
6786 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
6788 if (dpll
& PLL_P2_DIVIDE_BY_4
)
6793 intel_clock(dev
, 48000, &clock
);
6797 /* XXX: It would be nice to validate the clocks, but we can't reuse
6798 * i830PllIsValid() because it relies on the xf86_config connector
6799 * configuration being accurate, which it isn't necessarily.
6805 /** Returns the currently programmed mode of the given pipe. */
6806 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
6807 struct drm_crtc
*crtc
)
6809 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6810 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6811 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
6812 struct drm_display_mode
*mode
;
6813 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
6814 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
6815 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
6816 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
6818 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
6822 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
6823 mode
->hdisplay
= (htot
& 0xffff) + 1;
6824 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
6825 mode
->hsync_start
= (hsync
& 0xffff) + 1;
6826 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
6827 mode
->vdisplay
= (vtot
& 0xffff) + 1;
6828 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
6829 mode
->vsync_start
= (vsync
& 0xffff) + 1;
6830 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
6832 drm_mode_set_name(mode
);
6837 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
6839 struct drm_device
*dev
= crtc
->dev
;
6840 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6841 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6842 int pipe
= intel_crtc
->pipe
;
6843 int dpll_reg
= DPLL(pipe
);
6846 if (HAS_PCH_SPLIT(dev
))
6849 if (!dev_priv
->lvds_downclock_avail
)
6852 dpll
= I915_READ(dpll_reg
);
6853 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
6854 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6856 assert_panel_unlocked(dev_priv
, pipe
);
6858 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
6859 I915_WRITE(dpll_reg
, dpll
);
6860 intel_wait_for_vblank(dev
, pipe
);
6862 dpll
= I915_READ(dpll_reg
);
6863 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
6864 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6868 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
6870 struct drm_device
*dev
= crtc
->dev
;
6871 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6872 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6874 if (HAS_PCH_SPLIT(dev
))
6877 if (!dev_priv
->lvds_downclock_avail
)
6881 * Since this is called by a timer, we should never get here in
6884 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
6885 int pipe
= intel_crtc
->pipe
;
6886 int dpll_reg
= DPLL(pipe
);
6889 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6891 assert_panel_unlocked(dev_priv
, pipe
);
6893 dpll
= I915_READ(dpll_reg
);
6894 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
6895 I915_WRITE(dpll_reg
, dpll
);
6896 intel_wait_for_vblank(dev
, pipe
);
6897 dpll
= I915_READ(dpll_reg
);
6898 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
6899 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6904 void intel_mark_busy(struct drm_device
*dev
)
6906 i915_update_gfx_val(dev
->dev_private
);
6909 void intel_mark_idle(struct drm_device
*dev
)
6911 struct drm_crtc
*crtc
;
6913 if (!i915_powersave
)
6916 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6920 intel_decrease_pllclock(crtc
);
6924 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
)
6926 struct drm_device
*dev
= obj
->base
.dev
;
6927 struct drm_crtc
*crtc
;
6929 if (!i915_powersave
)
6932 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6936 if (to_intel_framebuffer(crtc
->fb
)->obj
== obj
)
6937 intel_increase_pllclock(crtc
);
6941 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
6943 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6944 struct drm_device
*dev
= crtc
->dev
;
6945 struct intel_unpin_work
*work
;
6946 unsigned long flags
;
6948 spin_lock_irqsave(&dev
->event_lock
, flags
);
6949 work
= intel_crtc
->unpin_work
;
6950 intel_crtc
->unpin_work
= NULL
;
6951 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6954 cancel_work_sync(&work
->work
);
6958 drm_crtc_cleanup(crtc
);
6963 static void intel_unpin_work_fn(struct work_struct
*__work
)
6965 struct intel_unpin_work
*work
=
6966 container_of(__work
, struct intel_unpin_work
, work
);
6967 struct drm_device
*dev
= work
->crtc
->dev
;
6969 mutex_lock(&dev
->struct_mutex
);
6970 intel_unpin_fb_obj(work
->old_fb_obj
);
6971 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
6972 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
6974 intel_update_fbc(dev
);
6975 mutex_unlock(&dev
->struct_mutex
);
6977 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
6978 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
6983 static void do_intel_finish_page_flip(struct drm_device
*dev
,
6984 struct drm_crtc
*crtc
)
6986 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6987 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6988 struct intel_unpin_work
*work
;
6989 unsigned long flags
;
6991 /* Ignore early vblank irqs */
6992 if (intel_crtc
== NULL
)
6995 spin_lock_irqsave(&dev
->event_lock
, flags
);
6996 work
= intel_crtc
->unpin_work
;
6998 /* Ensure we don't miss a work->pending update ... */
7001 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
7002 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7006 /* and that the unpin work is consistent wrt ->pending. */
7009 intel_crtc
->unpin_work
= NULL
;
7012 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
7014 drm_vblank_put(dev
, intel_crtc
->pipe
);
7016 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7018 wake_up_all(&dev_priv
->pending_flip_queue
);
7020 queue_work(dev_priv
->wq
, &work
->work
);
7022 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
7025 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
7027 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7028 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
7030 do_intel_finish_page_flip(dev
, crtc
);
7033 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
7035 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7036 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
7038 do_intel_finish_page_flip(dev
, crtc
);
7041 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
7043 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7044 struct intel_crtc
*intel_crtc
=
7045 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
7046 unsigned long flags
;
7048 /* NB: An MMIO update of the plane base pointer will also
7049 * generate a page-flip completion irq, i.e. every modeset
7050 * is also accompanied by a spurious intel_prepare_page_flip().
7052 spin_lock_irqsave(&dev
->event_lock
, flags
);
7053 if (intel_crtc
->unpin_work
)
7054 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
7055 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7058 inline static void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
7060 /* Ensure that the work item is consistent when activating it ... */
7062 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
7063 /* and that it is marked active as soon as the irq could fire. */
7067 static int intel_gen2_queue_flip(struct drm_device
*dev
,
7068 struct drm_crtc
*crtc
,
7069 struct drm_framebuffer
*fb
,
7070 struct drm_i915_gem_object
*obj
)
7072 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7073 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7075 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7078 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7082 ret
= intel_ring_begin(ring
, 6);
7086 /* Can't queue multiple flips, so wait for the previous
7087 * one to finish before executing the next.
7089 if (intel_crtc
->plane
)
7090 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7092 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7093 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7094 intel_ring_emit(ring
, MI_NOOP
);
7095 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7096 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7097 intel_ring_emit(ring
, fb
->pitches
[0]);
7098 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7099 intel_ring_emit(ring
, 0); /* aux display base address, unused */
7101 intel_mark_page_flip_active(intel_crtc
);
7102 intel_ring_advance(ring
);
7106 intel_unpin_fb_obj(obj
);
7111 static int intel_gen3_queue_flip(struct drm_device
*dev
,
7112 struct drm_crtc
*crtc
,
7113 struct drm_framebuffer
*fb
,
7114 struct drm_i915_gem_object
*obj
)
7116 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7117 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7119 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7122 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7126 ret
= intel_ring_begin(ring
, 6);
7130 if (intel_crtc
->plane
)
7131 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7133 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7134 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7135 intel_ring_emit(ring
, MI_NOOP
);
7136 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
7137 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7138 intel_ring_emit(ring
, fb
->pitches
[0]);
7139 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7140 intel_ring_emit(ring
, MI_NOOP
);
7142 intel_mark_page_flip_active(intel_crtc
);
7143 intel_ring_advance(ring
);
7147 intel_unpin_fb_obj(obj
);
7152 static int intel_gen4_queue_flip(struct drm_device
*dev
,
7153 struct drm_crtc
*crtc
,
7154 struct drm_framebuffer
*fb
,
7155 struct drm_i915_gem_object
*obj
)
7157 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7158 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7159 uint32_t pf
, pipesrc
;
7160 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7163 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7167 ret
= intel_ring_begin(ring
, 4);
7171 /* i965+ uses the linear or tiled offsets from the
7172 * Display Registers (which do not change across a page-flip)
7173 * so we need only reprogram the base address.
7175 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7176 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7177 intel_ring_emit(ring
, fb
->pitches
[0]);
7178 intel_ring_emit(ring
,
7179 (obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
) |
7182 /* XXX Enabling the panel-fitter across page-flip is so far
7183 * untested on non-native modes, so ignore it for now.
7184 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7187 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7188 intel_ring_emit(ring
, pf
| pipesrc
);
7190 intel_mark_page_flip_active(intel_crtc
);
7191 intel_ring_advance(ring
);
7195 intel_unpin_fb_obj(obj
);
7200 static int intel_gen6_queue_flip(struct drm_device
*dev
,
7201 struct drm_crtc
*crtc
,
7202 struct drm_framebuffer
*fb
,
7203 struct drm_i915_gem_object
*obj
)
7205 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7206 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7207 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7208 uint32_t pf
, pipesrc
;
7211 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7215 ret
= intel_ring_begin(ring
, 4);
7219 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7220 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7221 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
7222 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7224 /* Contrary to the suggestions in the documentation,
7225 * "Enable Panel Fitter" does not seem to be required when page
7226 * flipping with a non-native mode, and worse causes a normal
7228 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7231 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7232 intel_ring_emit(ring
, pf
| pipesrc
);
7234 intel_mark_page_flip_active(intel_crtc
);
7235 intel_ring_advance(ring
);
7239 intel_unpin_fb_obj(obj
);
7245 * On gen7 we currently use the blit ring because (in early silicon at least)
7246 * the render ring doesn't give us interrpts for page flip completion, which
7247 * means clients will hang after the first flip is queued. Fortunately the
7248 * blit ring generates interrupts properly, so use it instead.
7250 static int intel_gen7_queue_flip(struct drm_device
*dev
,
7251 struct drm_crtc
*crtc
,
7252 struct drm_framebuffer
*fb
,
7253 struct drm_i915_gem_object
*obj
)
7255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7256 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7257 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
7258 uint32_t plane_bit
= 0;
7261 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7265 switch(intel_crtc
->plane
) {
7267 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
7270 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
7273 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
7276 WARN_ONCE(1, "unknown plane in flip command\n");
7281 ret
= intel_ring_begin(ring
, 4);
7285 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
7286 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
7287 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7288 intel_ring_emit(ring
, (MI_NOOP
));
7290 intel_mark_page_flip_active(intel_crtc
);
7291 intel_ring_advance(ring
);
7295 intel_unpin_fb_obj(obj
);
7300 static int intel_default_queue_flip(struct drm_device
*dev
,
7301 struct drm_crtc
*crtc
,
7302 struct drm_framebuffer
*fb
,
7303 struct drm_i915_gem_object
*obj
)
7308 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
7309 struct drm_framebuffer
*fb
,
7310 struct drm_pending_vblank_event
*event
)
7312 struct drm_device
*dev
= crtc
->dev
;
7313 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7314 struct drm_framebuffer
*old_fb
= crtc
->fb
;
7315 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(fb
)->obj
;
7316 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7317 struct intel_unpin_work
*work
;
7318 unsigned long flags
;
7321 /* Can't change pixel format via MI display flips. */
7322 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
7326 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7327 * Note that pitch changes could also affect these register.
7329 if (INTEL_INFO(dev
)->gen
> 3 &&
7330 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
7331 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
7334 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
7338 work
->event
= event
;
7340 work
->old_fb_obj
= to_intel_framebuffer(old_fb
)->obj
;
7341 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
7343 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
7347 /* We borrow the event spin lock for protecting unpin_work */
7348 spin_lock_irqsave(&dev
->event_lock
, flags
);
7349 if (intel_crtc
->unpin_work
) {
7350 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7352 drm_vblank_put(dev
, intel_crtc
->pipe
);
7354 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7357 intel_crtc
->unpin_work
= work
;
7358 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7360 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
7361 flush_workqueue(dev_priv
->wq
);
7363 ret
= i915_mutex_lock_interruptible(dev
);
7367 /* Reference the objects for the scheduled work. */
7368 drm_gem_object_reference(&work
->old_fb_obj
->base
);
7369 drm_gem_object_reference(&obj
->base
);
7373 work
->pending_flip_obj
= obj
;
7375 work
->enable_stall_check
= true;
7377 atomic_inc(&intel_crtc
->unpin_work_count
);
7378 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
7380 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
);
7382 goto cleanup_pending
;
7384 intel_disable_fbc(dev
);
7385 intel_mark_fb_busy(obj
);
7386 mutex_unlock(&dev
->struct_mutex
);
7388 trace_i915_flip_request(intel_crtc
->plane
, obj
);
7393 atomic_dec(&intel_crtc
->unpin_work_count
);
7395 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7396 drm_gem_object_unreference(&obj
->base
);
7397 mutex_unlock(&dev
->struct_mutex
);
7400 spin_lock_irqsave(&dev
->event_lock
, flags
);
7401 intel_crtc
->unpin_work
= NULL
;
7402 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7404 drm_vblank_put(dev
, intel_crtc
->pipe
);
7411 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
7412 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
7413 .load_lut
= intel_crtc_load_lut
,
7416 bool intel_encoder_check_is_cloned(struct intel_encoder
*encoder
)
7418 struct intel_encoder
*other_encoder
;
7419 struct drm_crtc
*crtc
= &encoder
->new_crtc
->base
;
7424 list_for_each_entry(other_encoder
,
7425 &crtc
->dev
->mode_config
.encoder_list
,
7428 if (&other_encoder
->new_crtc
->base
!= crtc
||
7429 encoder
== other_encoder
)
7438 static bool intel_encoder_crtc_ok(struct drm_encoder
*encoder
,
7439 struct drm_crtc
*crtc
)
7441 struct drm_device
*dev
;
7442 struct drm_crtc
*tmp
;
7445 WARN(!crtc
, "checking null crtc?\n");
7449 list_for_each_entry(tmp
, &dev
->mode_config
.crtc_list
, head
) {
7455 if (encoder
->possible_crtcs
& crtc_mask
)
7461 * intel_modeset_update_staged_output_state
7463 * Updates the staged output configuration state, e.g. after we've read out the
7466 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
7468 struct intel_encoder
*encoder
;
7469 struct intel_connector
*connector
;
7471 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7473 connector
->new_encoder
=
7474 to_intel_encoder(connector
->base
.encoder
);
7477 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7480 to_intel_crtc(encoder
->base
.crtc
);
7485 * intel_modeset_commit_output_state
7487 * This function copies the stage display pipe configuration to the real one.
7489 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
7491 struct intel_encoder
*encoder
;
7492 struct intel_connector
*connector
;
7494 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7496 connector
->base
.encoder
= &connector
->new_encoder
->base
;
7499 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7501 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
7505 static struct drm_display_mode
*
7506 intel_modeset_adjusted_mode(struct drm_crtc
*crtc
,
7507 struct drm_display_mode
*mode
)
7509 struct drm_device
*dev
= crtc
->dev
;
7510 struct drm_display_mode
*adjusted_mode
;
7511 struct drm_encoder_helper_funcs
*encoder_funcs
;
7512 struct intel_encoder
*encoder
;
7514 adjusted_mode
= drm_mode_duplicate(dev
, mode
);
7516 return ERR_PTR(-ENOMEM
);
7518 /* Pass our mode to the connectors and the CRTC to give them a chance to
7519 * adjust it according to limitations or connector properties, and also
7520 * a chance to reject the mode entirely.
7522 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7525 if (&encoder
->new_crtc
->base
!= crtc
)
7527 encoder_funcs
= encoder
->base
.helper_private
;
7528 if (!(encoder_funcs
->mode_fixup(&encoder
->base
, mode
,
7530 DRM_DEBUG_KMS("Encoder fixup failed\n");
7535 if (!(intel_crtc_mode_fixup(crtc
, mode
, adjusted_mode
))) {
7536 DRM_DEBUG_KMS("CRTC fixup failed\n");
7539 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc
->base
.id
);
7541 return adjusted_mode
;
7543 drm_mode_destroy(dev
, adjusted_mode
);
7544 return ERR_PTR(-EINVAL
);
7547 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7548 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7550 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
7551 unsigned *prepare_pipes
, unsigned *disable_pipes
)
7553 struct intel_crtc
*intel_crtc
;
7554 struct drm_device
*dev
= crtc
->dev
;
7555 struct intel_encoder
*encoder
;
7556 struct intel_connector
*connector
;
7557 struct drm_crtc
*tmp_crtc
;
7559 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
7561 /* Check which crtcs have changed outputs connected to them, these need
7562 * to be part of the prepare_pipes mask. We don't (yet) support global
7563 * modeset across multiple crtcs, so modeset_pipes will only have one
7564 * bit set at most. */
7565 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7567 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
7570 if (connector
->base
.encoder
) {
7571 tmp_crtc
= connector
->base
.encoder
->crtc
;
7573 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
7576 if (connector
->new_encoder
)
7578 1 << connector
->new_encoder
->new_crtc
->pipe
;
7581 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7583 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
7586 if (encoder
->base
.crtc
) {
7587 tmp_crtc
= encoder
->base
.crtc
;
7589 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
7592 if (encoder
->new_crtc
)
7593 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
7596 /* Check for any pipes that will be fully disabled ... */
7597 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
7601 /* Don't try to disable disabled crtcs. */
7602 if (!intel_crtc
->base
.enabled
)
7605 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7607 if (encoder
->new_crtc
== intel_crtc
)
7612 *disable_pipes
|= 1 << intel_crtc
->pipe
;
7616 /* set_mode is also used to update properties on life display pipes. */
7617 intel_crtc
= to_intel_crtc(crtc
);
7619 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
7621 /* We only support modeset on one single crtc, hence we need to do that
7622 * only for the passed in crtc iff we change anything else than just
7625 * This is actually not true, to be fully compatible with the old crtc
7626 * helper we automatically disable _any_ output (i.e. doesn't need to be
7627 * connected to the crtc we're modesetting on) if it's disconnected.
7628 * Which is a rather nutty api (since changed the output configuration
7629 * without userspace's explicit request can lead to confusion), but
7630 * alas. Hence we currently need to modeset on all pipes we prepare. */
7632 *modeset_pipes
= *prepare_pipes
;
7634 /* ... and mask these out. */
7635 *modeset_pipes
&= ~(*disable_pipes
);
7636 *prepare_pipes
&= ~(*disable_pipes
);
7639 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
7641 struct drm_encoder
*encoder
;
7642 struct drm_device
*dev
= crtc
->dev
;
7644 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
7645 if (encoder
->crtc
== crtc
)
7652 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
7654 struct intel_encoder
*intel_encoder
;
7655 struct intel_crtc
*intel_crtc
;
7656 struct drm_connector
*connector
;
7658 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
7660 if (!intel_encoder
->base
.crtc
)
7663 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
7665 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
7666 intel_encoder
->connectors_active
= false;
7669 intel_modeset_commit_output_state(dev
);
7671 /* Update computed state. */
7672 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
7674 intel_crtc
->base
.enabled
= intel_crtc_in_use(&intel_crtc
->base
);
7677 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
7678 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
7681 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
7683 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
7684 struct drm_property
*dpms_property
=
7685 dev
->mode_config
.dpms_property
;
7687 connector
->dpms
= DRM_MODE_DPMS_ON
;
7688 drm_object_property_set_value(&connector
->base
,
7692 intel_encoder
= to_intel_encoder(connector
->encoder
);
7693 intel_encoder
->connectors_active
= true;
7699 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7700 list_for_each_entry((intel_crtc), \
7701 &(dev)->mode_config.crtc_list, \
7703 if (mask & (1 <<(intel_crtc)->pipe)) \
7706 intel_modeset_check_state(struct drm_device
*dev
)
7708 struct intel_crtc
*crtc
;
7709 struct intel_encoder
*encoder
;
7710 struct intel_connector
*connector
;
7712 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7714 /* This also checks the encoder/connector hw state with the
7715 * ->get_hw_state callbacks. */
7716 intel_connector_check_state(connector
);
7718 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
7719 "connector's staged encoder doesn't match current encoder\n");
7722 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7724 bool enabled
= false;
7725 bool active
= false;
7726 enum pipe pipe
, tracked_pipe
;
7728 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7729 encoder
->base
.base
.id
,
7730 drm_get_encoder_name(&encoder
->base
));
7732 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
7733 "encoder's stage crtc doesn't match current crtc\n");
7734 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
7735 "encoder's active_connectors set, but no crtc\n");
7737 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7739 if (connector
->base
.encoder
!= &encoder
->base
)
7742 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
7745 WARN(!!encoder
->base
.crtc
!= enabled
,
7746 "encoder's enabled state mismatch "
7747 "(expected %i, found %i)\n",
7748 !!encoder
->base
.crtc
, enabled
);
7749 WARN(active
&& !encoder
->base
.crtc
,
7750 "active encoder with no crtc\n");
7752 WARN(encoder
->connectors_active
!= active
,
7753 "encoder's computed active state doesn't match tracked active state "
7754 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
7756 active
= encoder
->get_hw_state(encoder
, &pipe
);
7757 WARN(active
!= encoder
->connectors_active
,
7758 "encoder's hw state doesn't match sw tracking "
7759 "(expected %i, found %i)\n",
7760 encoder
->connectors_active
, active
);
7762 if (!encoder
->base
.crtc
)
7765 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
7766 WARN(active
&& pipe
!= tracked_pipe
,
7767 "active encoder's pipe doesn't match"
7768 "(expected %i, found %i)\n",
7769 tracked_pipe
, pipe
);
7773 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
7775 bool enabled
= false;
7776 bool active
= false;
7778 DRM_DEBUG_KMS("[CRTC:%d]\n",
7779 crtc
->base
.base
.id
);
7781 WARN(crtc
->active
&& !crtc
->base
.enabled
,
7782 "active crtc, but not enabled in sw tracking\n");
7784 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7786 if (encoder
->base
.crtc
!= &crtc
->base
)
7789 if (encoder
->connectors_active
)
7792 WARN(active
!= crtc
->active
,
7793 "crtc's computed active state doesn't match tracked active state "
7794 "(expected %i, found %i)\n", active
, crtc
->active
);
7795 WARN(enabled
!= crtc
->base
.enabled
,
7796 "crtc's computed enabled state doesn't match tracked enabled state "
7797 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
7799 assert_pipe(dev
->dev_private
, crtc
->pipe
, crtc
->active
);
7803 int intel_set_mode(struct drm_crtc
*crtc
,
7804 struct drm_display_mode
*mode
,
7805 int x
, int y
, struct drm_framebuffer
*fb
)
7807 struct drm_device
*dev
= crtc
->dev
;
7808 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7809 struct drm_display_mode
*adjusted_mode
, *saved_mode
, *saved_hwmode
;
7810 struct intel_crtc
*intel_crtc
;
7811 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
7814 saved_mode
= kmalloc(2 * sizeof(*saved_mode
), GFP_KERNEL
);
7817 saved_hwmode
= saved_mode
+ 1;
7819 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
7820 &prepare_pipes
, &disable_pipes
);
7822 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7823 modeset_pipes
, prepare_pipes
, disable_pipes
);
7825 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
7826 intel_crtc_disable(&intel_crtc
->base
);
7828 *saved_hwmode
= crtc
->hwmode
;
7829 *saved_mode
= crtc
->mode
;
7831 /* Hack: Because we don't (yet) support global modeset on multiple
7832 * crtcs, we don't keep track of the new mode for more than one crtc.
7833 * Hence simply check whether any bit is set in modeset_pipes in all the
7834 * pieces of code that are not yet converted to deal with mutliple crtcs
7835 * changing their mode at the same time. */
7836 adjusted_mode
= NULL
;
7837 if (modeset_pipes
) {
7838 adjusted_mode
= intel_modeset_adjusted_mode(crtc
, mode
);
7839 if (IS_ERR(adjusted_mode
)) {
7840 ret
= PTR_ERR(adjusted_mode
);
7845 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
7846 if (intel_crtc
->base
.enabled
)
7847 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
7850 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7851 * to set it here already despite that we pass it down the callchain.
7856 /* Only after disabling all output pipelines that will be changed can we
7857 * update the the output configuration. */
7858 intel_modeset_update_state(dev
, prepare_pipes
);
7860 if (dev_priv
->display
.modeset_global_resources
)
7861 dev_priv
->display
.modeset_global_resources(dev
);
7863 /* Set up the DPLL and any encoders state that needs to adjust or depend
7866 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
7867 ret
= intel_crtc_mode_set(&intel_crtc
->base
,
7868 mode
, adjusted_mode
,
7874 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7875 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
)
7876 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
7878 if (modeset_pipes
) {
7879 /* Store real post-adjustment hardware mode. */
7880 crtc
->hwmode
= *adjusted_mode
;
7882 /* Calculate and store various constants which
7883 * are later needed by vblank and swap-completion
7884 * timestamping. They are derived from true hwmode.
7886 drm_calc_timestamping_constants(crtc
);
7889 /* FIXME: add subpixel order */
7891 drm_mode_destroy(dev
, adjusted_mode
);
7892 if (ret
&& crtc
->enabled
) {
7893 crtc
->hwmode
= *saved_hwmode
;
7894 crtc
->mode
= *saved_mode
;
7896 intel_modeset_check_state(dev
);
7904 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
7906 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->fb
);
7909 #undef for_each_intel_crtc_masked
7911 static void intel_set_config_free(struct intel_set_config
*config
)
7916 kfree(config
->save_connector_encoders
);
7917 kfree(config
->save_encoder_crtcs
);
7921 static int intel_set_config_save_state(struct drm_device
*dev
,
7922 struct intel_set_config
*config
)
7924 struct drm_encoder
*encoder
;
7925 struct drm_connector
*connector
;
7928 config
->save_encoder_crtcs
=
7929 kcalloc(dev
->mode_config
.num_encoder
,
7930 sizeof(struct drm_crtc
*), GFP_KERNEL
);
7931 if (!config
->save_encoder_crtcs
)
7934 config
->save_connector_encoders
=
7935 kcalloc(dev
->mode_config
.num_connector
,
7936 sizeof(struct drm_encoder
*), GFP_KERNEL
);
7937 if (!config
->save_connector_encoders
)
7940 /* Copy data. Note that driver private data is not affected.
7941 * Should anything bad happen only the expected state is
7942 * restored, not the drivers personal bookkeeping.
7945 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
7946 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
7950 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
7951 config
->save_connector_encoders
[count
++] = connector
->encoder
;
7957 static void intel_set_config_restore_state(struct drm_device
*dev
,
7958 struct intel_set_config
*config
)
7960 struct intel_encoder
*encoder
;
7961 struct intel_connector
*connector
;
7965 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
7967 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
7971 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
7972 connector
->new_encoder
=
7973 to_intel_encoder(config
->save_connector_encoders
[count
++]);
7978 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
7979 struct intel_set_config
*config
)
7982 /* We should be able to check here if the fb has the same properties
7983 * and then just flip_or_move it */
7984 if (set
->crtc
->fb
!= set
->fb
) {
7985 /* If we have no fb then treat it as a full mode set */
7986 if (set
->crtc
->fb
== NULL
) {
7987 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7988 config
->mode_changed
= true;
7989 } else if (set
->fb
== NULL
) {
7990 config
->mode_changed
= true;
7991 } else if (set
->fb
->depth
!= set
->crtc
->fb
->depth
) {
7992 config
->mode_changed
= true;
7993 } else if (set
->fb
->bits_per_pixel
!=
7994 set
->crtc
->fb
->bits_per_pixel
) {
7995 config
->mode_changed
= true;
7997 config
->fb_changed
= true;
8000 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
8001 config
->fb_changed
= true;
8003 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
8004 DRM_DEBUG_KMS("modes are different, full mode set\n");
8005 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
8006 drm_mode_debug_printmodeline(set
->mode
);
8007 config
->mode_changed
= true;
8012 intel_modeset_stage_output_state(struct drm_device
*dev
,
8013 struct drm_mode_set
*set
,
8014 struct intel_set_config
*config
)
8016 struct drm_crtc
*new_crtc
;
8017 struct intel_connector
*connector
;
8018 struct intel_encoder
*encoder
;
8021 /* The upper layers ensure that we either disable a crtc or have a list
8022 * of connectors. For paranoia, double-check this. */
8023 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
8024 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
8027 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8029 /* Otherwise traverse passed in connector list and get encoders
8031 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
8032 if (set
->connectors
[ro
] == &connector
->base
) {
8033 connector
->new_encoder
= connector
->encoder
;
8038 /* If we disable the crtc, disable all its connectors. Also, if
8039 * the connector is on the changing crtc but not on the new
8040 * connector list, disable it. */
8041 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
8042 connector
->base
.encoder
&&
8043 connector
->base
.encoder
->crtc
== set
->crtc
) {
8044 connector
->new_encoder
= NULL
;
8046 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8047 connector
->base
.base
.id
,
8048 drm_get_connector_name(&connector
->base
));
8052 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
8053 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8054 config
->mode_changed
= true;
8057 /* connector->new_encoder is now updated for all connectors. */
8059 /* Update crtc of enabled connectors. */
8061 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8063 if (!connector
->new_encoder
)
8066 new_crtc
= connector
->new_encoder
->base
.crtc
;
8068 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
8069 if (set
->connectors
[ro
] == &connector
->base
)
8070 new_crtc
= set
->crtc
;
8073 /* Make sure the new CRTC will work with the encoder */
8074 if (!intel_encoder_crtc_ok(&connector
->new_encoder
->base
,
8078 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
8080 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8081 connector
->base
.base
.id
,
8082 drm_get_connector_name(&connector
->base
),
8086 /* Check for any encoders that needs to be disabled. */
8087 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8089 list_for_each_entry(connector
,
8090 &dev
->mode_config
.connector_list
,
8092 if (connector
->new_encoder
== encoder
) {
8093 WARN_ON(!connector
->new_encoder
->new_crtc
);
8098 encoder
->new_crtc
= NULL
;
8100 /* Only now check for crtc changes so we don't miss encoders
8101 * that will be disabled. */
8102 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
8103 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8104 config
->mode_changed
= true;
8107 /* Now we've also updated encoder->new_crtc for all encoders. */
8112 static int intel_crtc_set_config(struct drm_mode_set
*set
)
8114 struct drm_device
*dev
;
8115 struct drm_mode_set save_set
;
8116 struct intel_set_config
*config
;
8121 BUG_ON(!set
->crtc
->helper_private
);
8123 /* Enforce sane interface api - has been abused by the fb helper. */
8124 BUG_ON(!set
->mode
&& set
->fb
);
8125 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
8128 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8129 set
->crtc
->base
.id
, set
->fb
->base
.id
,
8130 (int)set
->num_connectors
, set
->x
, set
->y
);
8132 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
8135 dev
= set
->crtc
->dev
;
8138 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
8142 ret
= intel_set_config_save_state(dev
, config
);
8146 save_set
.crtc
= set
->crtc
;
8147 save_set
.mode
= &set
->crtc
->mode
;
8148 save_set
.x
= set
->crtc
->x
;
8149 save_set
.y
= set
->crtc
->y
;
8150 save_set
.fb
= set
->crtc
->fb
;
8152 /* Compute whether we need a full modeset, only an fb base update or no
8153 * change at all. In the future we might also check whether only the
8154 * mode changed, e.g. for LVDS where we only change the panel fitter in
8156 intel_set_config_compute_mode_changes(set
, config
);
8158 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
8162 if (config
->mode_changed
) {
8164 DRM_DEBUG_KMS("attempting to set mode from"
8166 drm_mode_debug_printmodeline(set
->mode
);
8169 ret
= intel_set_mode(set
->crtc
, set
->mode
,
8170 set
->x
, set
->y
, set
->fb
);
8172 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8173 set
->crtc
->base
.id
, ret
);
8176 } else if (config
->fb_changed
) {
8177 intel_crtc_wait_for_pending_flips(set
->crtc
);
8179 ret
= intel_pipe_set_base(set
->crtc
,
8180 set
->x
, set
->y
, set
->fb
);
8183 intel_set_config_free(config
);
8188 intel_set_config_restore_state(dev
, config
);
8190 /* Try to restore the config */
8191 if (config
->mode_changed
&&
8192 intel_set_mode(save_set
.crtc
, save_set
.mode
,
8193 save_set
.x
, save_set
.y
, save_set
.fb
))
8194 DRM_ERROR("failed to restore config after modeset failure\n");
8197 intel_set_config_free(config
);
8201 static const struct drm_crtc_funcs intel_crtc_funcs
= {
8202 .cursor_set
= intel_crtc_cursor_set
,
8203 .cursor_move
= intel_crtc_cursor_move
,
8204 .gamma_set
= intel_crtc_gamma_set
,
8205 .set_config
= intel_crtc_set_config
,
8206 .destroy
= intel_crtc_destroy
,
8207 .page_flip
= intel_crtc_page_flip
,
8210 static void intel_cpu_pll_init(struct drm_device
*dev
)
8213 intel_ddi_pll_init(dev
);
8216 static void intel_pch_pll_init(struct drm_device
*dev
)
8218 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8221 if (dev_priv
->num_pch_pll
== 0) {
8222 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8226 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
8227 dev_priv
->pch_plls
[i
].pll_reg
= _PCH_DPLL(i
);
8228 dev_priv
->pch_plls
[i
].fp0_reg
= _PCH_FP0(i
);
8229 dev_priv
->pch_plls
[i
].fp1_reg
= _PCH_FP1(i
);
8233 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
8235 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8236 struct intel_crtc
*intel_crtc
;
8239 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
8240 if (intel_crtc
== NULL
)
8243 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
8245 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
8246 for (i
= 0; i
< 256; i
++) {
8247 intel_crtc
->lut_r
[i
] = i
;
8248 intel_crtc
->lut_g
[i
] = i
;
8249 intel_crtc
->lut_b
[i
] = i
;
8252 /* Swap pipes & planes for FBC on pre-965 */
8253 intel_crtc
->pipe
= pipe
;
8254 intel_crtc
->plane
= pipe
;
8255 intel_crtc
->cpu_transcoder
= pipe
;
8256 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
8257 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8258 intel_crtc
->plane
= !pipe
;
8261 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
8262 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
8263 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
8264 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
8266 intel_crtc
->bpp
= 24; /* default for pre-Ironlake */
8268 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
8271 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
8272 struct drm_file
*file
)
8274 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
8275 struct drm_mode_object
*drmmode_obj
;
8276 struct intel_crtc
*crtc
;
8278 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
8281 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
8282 DRM_MODE_OBJECT_CRTC
);
8285 DRM_ERROR("no such CRTC id\n");
8289 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
8290 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
8295 static int intel_encoder_clones(struct intel_encoder
*encoder
)
8297 struct drm_device
*dev
= encoder
->base
.dev
;
8298 struct intel_encoder
*source_encoder
;
8302 list_for_each_entry(source_encoder
,
8303 &dev
->mode_config
.encoder_list
, base
.head
) {
8305 if (encoder
== source_encoder
)
8306 index_mask
|= (1 << entry
);
8308 /* Intel hw has only one MUX where enocoders could be cloned. */
8309 if (encoder
->cloneable
&& source_encoder
->cloneable
)
8310 index_mask
|= (1 << entry
);
8318 static bool has_edp_a(struct drm_device
*dev
)
8320 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8322 if (!IS_MOBILE(dev
))
8325 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
8329 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
8335 static void intel_setup_outputs(struct drm_device
*dev
)
8337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8338 struct intel_encoder
*encoder
;
8339 bool dpd_is_edp
= false;
8342 has_lvds
= intel_lvds_init(dev
);
8343 if (!has_lvds
&& !HAS_PCH_SPLIT(dev
)) {
8344 /* disable the panel fitter on everything but LVDS */
8345 I915_WRITE(PFIT_CONTROL
, 0);
8348 if (!(HAS_DDI(dev
) && (I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_A_4_LANES
)))
8349 intel_crt_init(dev
);
8354 /* Haswell uses DDI functions to detect digital outputs */
8355 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
8356 /* DDI A only supports eDP */
8358 intel_ddi_init(dev
, PORT_A
);
8360 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8362 found
= I915_READ(SFUSE_STRAP
);
8364 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
8365 intel_ddi_init(dev
, PORT_B
);
8366 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
8367 intel_ddi_init(dev
, PORT_C
);
8368 if (found
& SFUSE_STRAP_DDID_DETECTED
)
8369 intel_ddi_init(dev
, PORT_D
);
8370 } else if (HAS_PCH_SPLIT(dev
)) {
8372 dpd_is_edp
= intel_dpd_is_edp(dev
);
8375 intel_dp_init(dev
, DP_A
, PORT_A
);
8377 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
8378 /* PCH SDVOB multiplex with HDMIB */
8379 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
8381 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
8382 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
8383 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
8386 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
8387 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
8389 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
8390 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
8392 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
8393 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
8395 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
8396 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
8397 } else if (IS_VALLEYVIEW(dev
)) {
8398 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8399 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
8400 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
8402 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
8403 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
8405 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
8406 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
8408 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
8411 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
8412 DRM_DEBUG_KMS("probing SDVOB\n");
8413 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
8414 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
8415 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8416 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
8419 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
8420 DRM_DEBUG_KMS("probing DP_B\n");
8421 intel_dp_init(dev
, DP_B
, PORT_B
);
8425 /* Before G4X SDVOC doesn't have its own detect register */
8427 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
8428 DRM_DEBUG_KMS("probing SDVOC\n");
8429 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
8432 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
8434 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
8435 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8436 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
8438 if (SUPPORTS_INTEGRATED_DP(dev
)) {
8439 DRM_DEBUG_KMS("probing DP_C\n");
8440 intel_dp_init(dev
, DP_C
, PORT_C
);
8444 if (SUPPORTS_INTEGRATED_DP(dev
) &&
8445 (I915_READ(DP_D
) & DP_DETECTED
)) {
8446 DRM_DEBUG_KMS("probing DP_D\n");
8447 intel_dp_init(dev
, DP_D
, PORT_D
);
8449 } else if (IS_GEN2(dev
))
8450 intel_dvo_init(dev
);
8452 if (SUPPORTS_TV(dev
))
8455 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
8456 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
8457 encoder
->base
.possible_clones
=
8458 intel_encoder_clones(encoder
);
8461 intel_init_pch_refclk(dev
);
8463 drm_helper_move_panel_connectors_to_head(dev
);
8466 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
8468 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
8470 drm_framebuffer_cleanup(fb
);
8471 drm_gem_object_unreference_unlocked(&intel_fb
->obj
->base
);
8476 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
8477 struct drm_file
*file
,
8478 unsigned int *handle
)
8480 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
8481 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
8483 return drm_gem_handle_create(file
, &obj
->base
, handle
);
8486 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
8487 .destroy
= intel_user_framebuffer_destroy
,
8488 .create_handle
= intel_user_framebuffer_create_handle
,
8491 int intel_framebuffer_init(struct drm_device
*dev
,
8492 struct intel_framebuffer
*intel_fb
,
8493 struct drm_mode_fb_cmd2
*mode_cmd
,
8494 struct drm_i915_gem_object
*obj
)
8498 if (obj
->tiling_mode
== I915_TILING_Y
) {
8499 DRM_DEBUG("hardware does not support tiling Y\n");
8503 if (mode_cmd
->pitches
[0] & 63) {
8504 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8505 mode_cmd
->pitches
[0]);
8509 /* FIXME <= Gen4 stride limits are bit unclear */
8510 if (mode_cmd
->pitches
[0] > 32768) {
8511 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8512 mode_cmd
->pitches
[0]);
8516 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
8517 mode_cmd
->pitches
[0] != obj
->stride
) {
8518 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8519 mode_cmd
->pitches
[0], obj
->stride
);
8523 /* Reject formats not supported by any plane early. */
8524 switch (mode_cmd
->pixel_format
) {
8526 case DRM_FORMAT_RGB565
:
8527 case DRM_FORMAT_XRGB8888
:
8528 case DRM_FORMAT_ARGB8888
:
8530 case DRM_FORMAT_XRGB1555
:
8531 case DRM_FORMAT_ARGB1555
:
8532 if (INTEL_INFO(dev
)->gen
> 3) {
8533 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd
->pixel_format
);
8537 case DRM_FORMAT_XBGR8888
:
8538 case DRM_FORMAT_ABGR8888
:
8539 case DRM_FORMAT_XRGB2101010
:
8540 case DRM_FORMAT_ARGB2101010
:
8541 case DRM_FORMAT_XBGR2101010
:
8542 case DRM_FORMAT_ABGR2101010
:
8543 if (INTEL_INFO(dev
)->gen
< 4) {
8544 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd
->pixel_format
);
8548 case DRM_FORMAT_YUYV
:
8549 case DRM_FORMAT_UYVY
:
8550 case DRM_FORMAT_YVYU
:
8551 case DRM_FORMAT_VYUY
:
8552 if (INTEL_INFO(dev
)->gen
< 5) {
8553 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd
->pixel_format
);
8558 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd
->pixel_format
);
8562 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8563 if (mode_cmd
->offsets
[0] != 0)
8566 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
8567 intel_fb
->obj
= obj
;
8569 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
8571 DRM_ERROR("framebuffer init failed %d\n", ret
);
8578 static struct drm_framebuffer
*
8579 intel_user_framebuffer_create(struct drm_device
*dev
,
8580 struct drm_file
*filp
,
8581 struct drm_mode_fb_cmd2
*mode_cmd
)
8583 struct drm_i915_gem_object
*obj
;
8585 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
8586 mode_cmd
->handles
[0]));
8587 if (&obj
->base
== NULL
)
8588 return ERR_PTR(-ENOENT
);
8590 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
8593 static const struct drm_mode_config_funcs intel_mode_funcs
= {
8594 .fb_create
= intel_user_framebuffer_create
,
8595 .output_poll_changed
= intel_fb_output_poll_changed
,
8598 /* Set up chip specific display functions */
8599 static void intel_init_display(struct drm_device
*dev
)
8601 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8604 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
8605 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
8606 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
8607 dev_priv
->display
.off
= haswell_crtc_off
;
8608 dev_priv
->display
.update_plane
= ironlake_update_plane
;
8609 } else if (HAS_PCH_SPLIT(dev
)) {
8610 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
8611 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
8612 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
8613 dev_priv
->display
.off
= ironlake_crtc_off
;
8614 dev_priv
->display
.update_plane
= ironlake_update_plane
;
8616 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
8617 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
8618 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
8619 dev_priv
->display
.off
= i9xx_crtc_off
;
8620 dev_priv
->display
.update_plane
= i9xx_update_plane
;
8623 /* Returns the core display clock speed */
8624 if (IS_VALLEYVIEW(dev
))
8625 dev_priv
->display
.get_display_clock_speed
=
8626 valleyview_get_display_clock_speed
;
8627 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
8628 dev_priv
->display
.get_display_clock_speed
=
8629 i945_get_display_clock_speed
;
8630 else if (IS_I915G(dev
))
8631 dev_priv
->display
.get_display_clock_speed
=
8632 i915_get_display_clock_speed
;
8633 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
8634 dev_priv
->display
.get_display_clock_speed
=
8635 i9xx_misc_get_display_clock_speed
;
8636 else if (IS_I915GM(dev
))
8637 dev_priv
->display
.get_display_clock_speed
=
8638 i915gm_get_display_clock_speed
;
8639 else if (IS_I865G(dev
))
8640 dev_priv
->display
.get_display_clock_speed
=
8641 i865_get_display_clock_speed
;
8642 else if (IS_I85X(dev
))
8643 dev_priv
->display
.get_display_clock_speed
=
8644 i855_get_display_clock_speed
;
8646 dev_priv
->display
.get_display_clock_speed
=
8647 i830_get_display_clock_speed
;
8649 if (HAS_PCH_SPLIT(dev
)) {
8651 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
8652 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8653 } else if (IS_GEN6(dev
)) {
8654 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
8655 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8656 } else if (IS_IVYBRIDGE(dev
)) {
8657 /* FIXME: detect B0+ stepping and use auto training */
8658 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
8659 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8660 dev_priv
->display
.modeset_global_resources
=
8661 ivb_modeset_global_resources
;
8662 } else if (IS_HASWELL(dev
)) {
8663 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
8664 dev_priv
->display
.write_eld
= haswell_write_eld
;
8665 dev_priv
->display
.modeset_global_resources
=
8666 haswell_modeset_global_resources
;
8668 } else if (IS_G4X(dev
)) {
8669 dev_priv
->display
.write_eld
= g4x_write_eld
;
8672 /* Default just returns -ENODEV to indicate unsupported */
8673 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
8675 switch (INTEL_INFO(dev
)->gen
) {
8677 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
8681 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
8686 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
8690 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
8693 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
8699 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8700 * resume, or other times. This quirk makes sure that's the case for
8703 static void quirk_pipea_force(struct drm_device
*dev
)
8705 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8707 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
8708 DRM_INFO("applying pipe a force quirk\n");
8712 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8714 static void quirk_ssc_force_disable(struct drm_device
*dev
)
8716 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8717 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
8718 DRM_INFO("applying lvds SSC disable quirk\n");
8722 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8725 static void quirk_invert_brightness(struct drm_device
*dev
)
8727 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8728 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
8729 DRM_INFO("applying inverted panel brightness quirk\n");
8732 struct intel_quirk
{
8734 int subsystem_vendor
;
8735 int subsystem_device
;
8736 void (*hook
)(struct drm_device
*dev
);
8739 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8740 struct intel_dmi_quirk
{
8741 void (*hook
)(struct drm_device
*dev
);
8742 const struct dmi_system_id (*dmi_id_list
)[];
8745 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
8747 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
8751 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
8753 .dmi_id_list
= &(const struct dmi_system_id
[]) {
8755 .callback
= intel_dmi_reverse_brightness
,
8756 .ident
= "NCR Corporation",
8757 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
8758 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
8761 { } /* terminating entry */
8763 .hook
= quirk_invert_brightness
,
8767 static struct intel_quirk intel_quirks
[] = {
8768 /* HP Mini needs pipe A force quirk (LP: #322104) */
8769 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
8771 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8772 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
8774 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8775 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
8777 /* 830/845 need to leave pipe A & dpll A up */
8778 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
8779 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
8781 /* Lenovo U160 cannot use SSC on LVDS */
8782 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
8784 /* Sony Vaio Y cannot use SSC on LVDS */
8785 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
8787 /* Acer Aspire 5734Z must invert backlight brightness */
8788 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
8790 /* Acer/eMachines G725 */
8791 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
8793 /* Acer/eMachines e725 */
8794 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
8796 /* Acer/Packard Bell NCL20 */
8797 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
8799 /* Acer Aspire 4736Z */
8800 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
8803 static void intel_init_quirks(struct drm_device
*dev
)
8805 struct pci_dev
*d
= dev
->pdev
;
8808 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
8809 struct intel_quirk
*q
= &intel_quirks
[i
];
8811 if (d
->device
== q
->device
&&
8812 (d
->subsystem_vendor
== q
->subsystem_vendor
||
8813 q
->subsystem_vendor
== PCI_ANY_ID
) &&
8814 (d
->subsystem_device
== q
->subsystem_device
||
8815 q
->subsystem_device
== PCI_ANY_ID
))
8818 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
8819 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
8820 intel_dmi_quirks
[i
].hook(dev
);
8824 /* Disable the VGA plane that we never use */
8825 static void i915_disable_vga(struct drm_device
*dev
)
8827 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8829 u32 vga_reg
= i915_vgacntrl_reg(dev
);
8831 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
8832 outb(SR01
, VGA_SR_INDEX
);
8833 sr1
= inb(VGA_SR_DATA
);
8834 outb(sr1
| 1<<5, VGA_SR_DATA
);
8835 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
8838 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
8839 POSTING_READ(vga_reg
);
8842 void intel_modeset_init_hw(struct drm_device
*dev
)
8844 intel_init_power_well(dev
);
8846 intel_prepare_ddi(dev
);
8848 intel_init_clock_gating(dev
);
8850 mutex_lock(&dev
->struct_mutex
);
8851 intel_enable_gt_powersave(dev
);
8852 mutex_unlock(&dev
->struct_mutex
);
8855 void intel_modeset_init(struct drm_device
*dev
)
8857 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8860 drm_mode_config_init(dev
);
8862 dev
->mode_config
.min_width
= 0;
8863 dev
->mode_config
.min_height
= 0;
8865 dev
->mode_config
.preferred_depth
= 24;
8866 dev
->mode_config
.prefer_shadow
= 1;
8868 dev
->mode_config
.funcs
= &intel_mode_funcs
;
8870 intel_init_quirks(dev
);
8874 intel_init_display(dev
);
8877 dev
->mode_config
.max_width
= 2048;
8878 dev
->mode_config
.max_height
= 2048;
8879 } else if (IS_GEN3(dev
)) {
8880 dev
->mode_config
.max_width
= 4096;
8881 dev
->mode_config
.max_height
= 4096;
8883 dev
->mode_config
.max_width
= 8192;
8884 dev
->mode_config
.max_height
= 8192;
8886 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
8888 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8889 INTEL_INFO(dev
)->num_pipes
,
8890 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
8892 for (i
= 0; i
< INTEL_INFO(dev
)->num_pipes
; i
++) {
8893 intel_crtc_init(dev
, i
);
8894 ret
= intel_plane_init(dev
, i
);
8896 DRM_DEBUG_KMS("plane %d init failed: %d\n", i
, ret
);
8899 intel_cpu_pll_init(dev
);
8900 intel_pch_pll_init(dev
);
8902 /* Just disable it once at startup */
8903 i915_disable_vga(dev
);
8904 intel_setup_outputs(dev
);
8906 /* Just in case the BIOS is doing something questionable. */
8907 intel_disable_fbc(dev
);
8911 intel_connector_break_all_links(struct intel_connector
*connector
)
8913 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
8914 connector
->base
.encoder
= NULL
;
8915 connector
->encoder
->connectors_active
= false;
8916 connector
->encoder
->base
.crtc
= NULL
;
8919 static void intel_enable_pipe_a(struct drm_device
*dev
)
8921 struct intel_connector
*connector
;
8922 struct drm_connector
*crt
= NULL
;
8923 struct intel_load_detect_pipe load_detect_temp
;
8925 /* We can't just switch on the pipe A, we need to set things up with a
8926 * proper mode and output configuration. As a gross hack, enable pipe A
8927 * by enabling the load detect pipe once. */
8928 list_for_each_entry(connector
,
8929 &dev
->mode_config
.connector_list
,
8931 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
8932 crt
= &connector
->base
;
8940 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
))
8941 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
8947 intel_check_plane_mapping(struct intel_crtc
*crtc
)
8949 struct drm_device
*dev
= crtc
->base
.dev
;
8950 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8953 if (INTEL_INFO(dev
)->num_pipes
== 1)
8956 reg
= DSPCNTR(!crtc
->plane
);
8957 val
= I915_READ(reg
);
8959 if ((val
& DISPLAY_PLANE_ENABLE
) &&
8960 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
8966 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
8968 struct drm_device
*dev
= crtc
->base
.dev
;
8969 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8972 /* Clear any frame start delays used for debugging left by the BIOS */
8973 reg
= PIPECONF(crtc
->cpu_transcoder
);
8974 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
8976 /* We need to sanitize the plane -> pipe mapping first because this will
8977 * disable the crtc (and hence change the state) if it is wrong. Note
8978 * that gen4+ has a fixed plane -> pipe mapping. */
8979 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
8980 struct intel_connector
*connector
;
8983 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8984 crtc
->base
.base
.id
);
8986 /* Pipe has the wrong plane attached and the plane is active.
8987 * Temporarily change the plane mapping and disable everything
8989 plane
= crtc
->plane
;
8990 crtc
->plane
= !plane
;
8991 dev_priv
->display
.crtc_disable(&crtc
->base
);
8992 crtc
->plane
= plane
;
8994 /* ... and break all links. */
8995 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8997 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
9000 intel_connector_break_all_links(connector
);
9003 WARN_ON(crtc
->active
);
9004 crtc
->base
.enabled
= false;
9007 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
9008 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
9009 /* BIOS forgot to enable pipe A, this mostly happens after
9010 * resume. Force-enable the pipe to fix this, the update_dpms
9011 * call below we restore the pipe to the right state, but leave
9012 * the required bits on. */
9013 intel_enable_pipe_a(dev
);
9016 /* Adjust the state of the output pipe according to whether we
9017 * have active connectors/encoders. */
9018 intel_crtc_update_dpms(&crtc
->base
);
9020 if (crtc
->active
!= crtc
->base
.enabled
) {
9021 struct intel_encoder
*encoder
;
9023 /* This can happen either due to bugs in the get_hw_state
9024 * functions or because the pipe is force-enabled due to the
9026 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9028 crtc
->base
.enabled
? "enabled" : "disabled",
9029 crtc
->active
? "enabled" : "disabled");
9031 crtc
->base
.enabled
= crtc
->active
;
9033 /* Because we only establish the connector -> encoder ->
9034 * crtc links if something is active, this means the
9035 * crtc is now deactivated. Break the links. connector
9036 * -> encoder links are only establish when things are
9037 * actually up, hence no need to break them. */
9038 WARN_ON(crtc
->active
);
9040 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
9041 WARN_ON(encoder
->connectors_active
);
9042 encoder
->base
.crtc
= NULL
;
9047 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
9049 struct intel_connector
*connector
;
9050 struct drm_device
*dev
= encoder
->base
.dev
;
9052 /* We need to check both for a crtc link (meaning that the
9053 * encoder is active and trying to read from a pipe) and the
9054 * pipe itself being active. */
9055 bool has_active_crtc
= encoder
->base
.crtc
&&
9056 to_intel_crtc(encoder
->base
.crtc
)->active
;
9058 if (encoder
->connectors_active
&& !has_active_crtc
) {
9059 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9060 encoder
->base
.base
.id
,
9061 drm_get_encoder_name(&encoder
->base
));
9063 /* Connector is active, but has no active pipe. This is
9064 * fallout from our resume register restoring. Disable
9065 * the encoder manually again. */
9066 if (encoder
->base
.crtc
) {
9067 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9068 encoder
->base
.base
.id
,
9069 drm_get_encoder_name(&encoder
->base
));
9070 encoder
->disable(encoder
);
9073 /* Inconsistent output/port/pipe state happens presumably due to
9074 * a bug in one of the get_hw_state functions. Or someplace else
9075 * in our code, like the register restore mess on resume. Clamp
9076 * things to off as a safer default. */
9077 list_for_each_entry(connector
,
9078 &dev
->mode_config
.connector_list
,
9080 if (connector
->encoder
!= encoder
)
9083 intel_connector_break_all_links(connector
);
9086 /* Enabled encoders without active connectors will be fixed in
9087 * the crtc fixup. */
9090 void i915_redisable_vga(struct drm_device
*dev
)
9092 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9093 u32 vga_reg
= i915_vgacntrl_reg(dev
);
9095 if (I915_READ(vga_reg
) != VGA_DISP_DISABLE
) {
9096 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9097 i915_disable_vga(dev
);
9101 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9102 * and i915 state tracking structures. */
9103 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
9106 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9109 struct intel_crtc
*crtc
;
9110 struct intel_encoder
*encoder
;
9111 struct intel_connector
*connector
;
9114 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
9116 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
9117 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
9118 case TRANS_DDI_EDP_INPUT_A_ON
:
9119 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
9122 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
9125 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
9130 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9131 crtc
->cpu_transcoder
= TRANSCODER_EDP
;
9133 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9138 for_each_pipe(pipe
) {
9139 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9141 tmp
= I915_READ(PIPECONF(crtc
->cpu_transcoder
));
9142 if (tmp
& PIPECONF_ENABLE
)
9143 crtc
->active
= true;
9145 crtc
->active
= false;
9147 crtc
->base
.enabled
= crtc
->active
;
9149 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9151 crtc
->active
? "enabled" : "disabled");
9155 intel_ddi_setup_hw_pll_state(dev
);
9157 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9161 if (encoder
->get_hw_state(encoder
, &pipe
)) {
9162 encoder
->base
.crtc
=
9163 dev_priv
->pipe_to_crtc_mapping
[pipe
];
9165 encoder
->base
.crtc
= NULL
;
9168 encoder
->connectors_active
= false;
9169 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9170 encoder
->base
.base
.id
,
9171 drm_get_encoder_name(&encoder
->base
),
9172 encoder
->base
.crtc
? "enabled" : "disabled",
9176 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9178 if (connector
->get_hw_state(connector
)) {
9179 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
9180 connector
->encoder
->connectors_active
= true;
9181 connector
->base
.encoder
= &connector
->encoder
->base
;
9183 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
9184 connector
->base
.encoder
= NULL
;
9186 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9187 connector
->base
.base
.id
,
9188 drm_get_connector_name(&connector
->base
),
9189 connector
->base
.encoder
? "enabled" : "disabled");
9192 /* HW state is read out, now we need to sanitize this mess. */
9193 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9195 intel_sanitize_encoder(encoder
);
9198 for_each_pipe(pipe
) {
9199 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9200 intel_sanitize_crtc(crtc
);
9203 if (force_restore
) {
9204 for_each_pipe(pipe
) {
9205 intel_crtc_restore_mode(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9208 i915_redisable_vga(dev
);
9210 intel_modeset_update_staged_output_state(dev
);
9213 intel_modeset_check_state(dev
);
9215 drm_mode_config_reset(dev
);
9218 void intel_modeset_gem_init(struct drm_device
*dev
)
9220 intel_modeset_init_hw(dev
);
9222 intel_setup_overlay(dev
);
9224 intel_modeset_setup_hw_state(dev
, false);
9227 void intel_modeset_cleanup(struct drm_device
*dev
)
9229 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9230 struct drm_crtc
*crtc
;
9231 struct intel_crtc
*intel_crtc
;
9233 drm_kms_helper_poll_fini(dev
);
9234 mutex_lock(&dev
->struct_mutex
);
9236 intel_unregister_dsm_handler();
9239 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
9240 /* Skip inactive CRTCs */
9244 intel_crtc
= to_intel_crtc(crtc
);
9245 intel_increase_pllclock(crtc
);
9248 intel_disable_fbc(dev
);
9250 intel_disable_gt_powersave(dev
);
9252 ironlake_teardown_rc6(dev
);
9254 if (IS_VALLEYVIEW(dev
))
9257 mutex_unlock(&dev
->struct_mutex
);
9259 /* Disable the irq before mode object teardown, for the irq might
9260 * enqueue unpin/hotplug work. */
9261 drm_irq_uninstall(dev
);
9262 cancel_work_sync(&dev_priv
->hotplug_work
);
9263 cancel_work_sync(&dev_priv
->rps
.work
);
9265 /* flush any delayed tasks or pending work */
9266 flush_scheduled_work();
9268 drm_mode_config_cleanup(dev
);
9270 intel_cleanup_overlay(dev
);
9274 * Return which encoder is currently attached for connector.
9276 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
9278 return &intel_attached_encoder(connector
)->base
;
9281 void intel_connector_attach_encoder(struct intel_connector
*connector
,
9282 struct intel_encoder
*encoder
)
9284 connector
->encoder
= encoder
;
9285 drm_mode_connector_attach_encoder(&connector
->base
,
9290 * set vga decode state - true == enable VGA decode
9292 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
9294 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9297 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
9299 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
9301 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
9302 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
9306 #ifdef CONFIG_DEBUG_FS
9307 #include <linux/seq_file.h>
9309 struct intel_display_error_state
{
9310 struct intel_cursor_error_state
{
9315 } cursor
[I915_MAX_PIPES
];
9317 struct intel_pipe_error_state
{
9327 } pipe
[I915_MAX_PIPES
];
9329 struct intel_plane_error_state
{
9337 } plane
[I915_MAX_PIPES
];
9340 struct intel_display_error_state
*
9341 intel_display_capture_error_state(struct drm_device
*dev
)
9343 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9344 struct intel_display_error_state
*error
;
9345 enum transcoder cpu_transcoder
;
9348 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
9353 cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
, i
);
9355 if (INTEL_INFO(dev
)->gen
<= 6 || IS_VALLEYVIEW(dev
)) {
9356 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
9357 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
9358 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
9360 error
->cursor
[i
].control
= I915_READ(CURCNTR_IVB(i
));
9361 error
->cursor
[i
].position
= I915_READ(CURPOS_IVB(i
));
9362 error
->cursor
[i
].base
= I915_READ(CURBASE_IVB(i
));
9365 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
9366 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
9367 if (INTEL_INFO(dev
)->gen
<= 3)
9368 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
9369 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
9370 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
9371 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
9372 if (INTEL_INFO(dev
)->gen
>= 4) {
9373 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
9374 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
9377 error
->pipe
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
9378 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
9379 error
->pipe
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
9380 error
->pipe
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
9381 error
->pipe
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
9382 error
->pipe
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
9383 error
->pipe
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
9384 error
->pipe
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
9391 intel_display_print_error_state(struct seq_file
*m
,
9392 struct drm_device
*dev
,
9393 struct intel_display_error_state
*error
)
9397 seq_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
9399 seq_printf(m
, "Pipe [%d]:\n", i
);
9400 seq_printf(m
, " CONF: %08x\n", error
->pipe
[i
].conf
);
9401 seq_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
9402 seq_printf(m
, " HTOTAL: %08x\n", error
->pipe
[i
].htotal
);
9403 seq_printf(m
, " HBLANK: %08x\n", error
->pipe
[i
].hblank
);
9404 seq_printf(m
, " HSYNC: %08x\n", error
->pipe
[i
].hsync
);
9405 seq_printf(m
, " VTOTAL: %08x\n", error
->pipe
[i
].vtotal
);
9406 seq_printf(m
, " VBLANK: %08x\n", error
->pipe
[i
].vblank
);
9407 seq_printf(m
, " VSYNC: %08x\n", error
->pipe
[i
].vsync
);
9409 seq_printf(m
, "Plane [%d]:\n", i
);
9410 seq_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
9411 seq_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
9412 if (INTEL_INFO(dev
)->gen
<= 3)
9413 seq_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
9414 seq_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
9415 if (!IS_HASWELL(dev
))
9416 seq_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
9417 if (INTEL_INFO(dev
)->gen
>= 4) {
9418 seq_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
9419 seq_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
9422 seq_printf(m
, "Cursor [%d]:\n", i
);
9423 seq_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
9424 seq_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
9425 seq_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);