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Merge tag 'sunxi-fixes-for-4.9-2' of https://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "i915_gem_dmabuf.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
51
52 static bool is_mmio_work(struct intel_flip_work *work)
53 {
54 return work->mmio_work.func;
55 }
56
57 /* Primary plane formats for gen <= 3 */
58 static const uint32_t i8xx_primary_formats[] = {
59 DRM_FORMAT_C8,
60 DRM_FORMAT_RGB565,
61 DRM_FORMAT_XRGB1555,
62 DRM_FORMAT_XRGB8888,
63 };
64
65 /* Primary plane formats for gen >= 4 */
66 static const uint32_t i965_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_XRGB2101010,
72 DRM_FORMAT_XBGR2101010,
73 };
74
75 static const uint32_t skl_primary_formats[] = {
76 DRM_FORMAT_C8,
77 DRM_FORMAT_RGB565,
78 DRM_FORMAT_XRGB8888,
79 DRM_FORMAT_XBGR8888,
80 DRM_FORMAT_ARGB8888,
81 DRM_FORMAT_ABGR8888,
82 DRM_FORMAT_XRGB2101010,
83 DRM_FORMAT_XBGR2101010,
84 DRM_FORMAT_YUYV,
85 DRM_FORMAT_YVYU,
86 DRM_FORMAT_UYVY,
87 DRM_FORMAT_VYUY,
88 };
89
90 /* Cursor formats */
91 static const uint32_t intel_cursor_formats[] = {
92 DRM_FORMAT_ARGB8888,
93 };
94
95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
96 struct intel_crtc_state *pipe_config);
97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
98 struct intel_crtc_state *pipe_config);
99
100 static int intel_framebuffer_init(struct drm_device *dev,
101 struct intel_framebuffer *ifb,
102 struct drm_mode_fb_cmd2 *mode_cmd,
103 struct drm_i915_gem_object *obj);
104 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
106 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
107 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
108 struct intel_link_m_n *m_n,
109 struct intel_link_m_n *m2_n2);
110 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipeconf(struct drm_crtc *crtc);
112 static void haswell_set_pipemisc(struct drm_crtc *crtc);
113 static void vlv_prepare_pll(struct intel_crtc *crtc,
114 const struct intel_crtc_state *pipe_config);
115 static void chv_prepare_pll(struct intel_crtc *crtc,
116 const struct intel_crtc_state *pipe_config);
117 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
119 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
120 struct intel_crtc_state *crtc_state);
121 static void skylake_pfit_enable(struct intel_crtc *crtc);
122 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
123 static void ironlake_pfit_enable(struct intel_crtc *crtc);
124 static void intel_modeset_setup_hw_state(struct drm_device *dev);
125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
126 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
127 static int bxt_calc_cdclk(int max_pixclk);
128
129 struct intel_limit {
130 struct {
131 int min, max;
132 } dot, vco, n, m, m1, m2, p, p1;
133
134 struct {
135 int dot_limit;
136 int p2_slow, p2_fast;
137 } p2;
138 };
139
140 /* returns HPLL frequency in kHz */
141 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
142 {
143 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
144
145 /* Obtain SKU information */
146 mutex_lock(&dev_priv->sb_lock);
147 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
148 CCK_FUSE_HPLL_FREQ_MASK;
149 mutex_unlock(&dev_priv->sb_lock);
150
151 return vco_freq[hpll_freq] * 1000;
152 }
153
154 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
155 const char *name, u32 reg, int ref_freq)
156 {
157 u32 val;
158 int divider;
159
160 mutex_lock(&dev_priv->sb_lock);
161 val = vlv_cck_read(dev_priv, reg);
162 mutex_unlock(&dev_priv->sb_lock);
163
164 divider = val & CCK_FREQUENCY_VALUES;
165
166 WARN((val & CCK_FREQUENCY_STATUS) !=
167 (divider << CCK_FREQUENCY_STATUS_SHIFT),
168 "%s change in progress\n", name);
169
170 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
171 }
172
173 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
174 const char *name, u32 reg)
175 {
176 if (dev_priv->hpll_freq == 0)
177 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
178
179 return vlv_get_cck_clock(dev_priv, name, reg,
180 dev_priv->hpll_freq);
181 }
182
183 static int
184 intel_pch_rawclk(struct drm_i915_private *dev_priv)
185 {
186 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
187 }
188
189 static int
190 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
191 {
192 /* RAWCLK_FREQ_VLV register updated from power well code */
193 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
194 CCK_DISPLAY_REF_CLOCK_CONTROL);
195 }
196
197 static int
198 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
199 {
200 uint32_t clkcfg;
201
202 /* hrawclock is 1/4 the FSB frequency */
203 clkcfg = I915_READ(CLKCFG);
204 switch (clkcfg & CLKCFG_FSB_MASK) {
205 case CLKCFG_FSB_400:
206 return 100000;
207 case CLKCFG_FSB_533:
208 return 133333;
209 case CLKCFG_FSB_667:
210 return 166667;
211 case CLKCFG_FSB_800:
212 return 200000;
213 case CLKCFG_FSB_1067:
214 return 266667;
215 case CLKCFG_FSB_1333:
216 return 333333;
217 /* these two are just a guess; one of them might be right */
218 case CLKCFG_FSB_1600:
219 case CLKCFG_FSB_1600_ALT:
220 return 400000;
221 default:
222 return 133333;
223 }
224 }
225
226 void intel_update_rawclk(struct drm_i915_private *dev_priv)
227 {
228 if (HAS_PCH_SPLIT(dev_priv))
229 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
230 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
231 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
232 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
233 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
234 else
235 return; /* no rawclk on other platforms, or no need to know it */
236
237 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
238 }
239
240 static void intel_update_czclk(struct drm_i915_private *dev_priv)
241 {
242 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
243 return;
244
245 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
246 CCK_CZ_CLOCK_CONTROL);
247
248 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
249 }
250
251 static inline u32 /* units of 100MHz */
252 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
253 const struct intel_crtc_state *pipe_config)
254 {
255 if (HAS_DDI(dev_priv))
256 return pipe_config->port_clock; /* SPLL */
257 else if (IS_GEN5(dev_priv))
258 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
259 else
260 return 270000;
261 }
262
263 static const struct intel_limit intel_limits_i8xx_dac = {
264 .dot = { .min = 25000, .max = 350000 },
265 .vco = { .min = 908000, .max = 1512000 },
266 .n = { .min = 2, .max = 16 },
267 .m = { .min = 96, .max = 140 },
268 .m1 = { .min = 18, .max = 26 },
269 .m2 = { .min = 6, .max = 16 },
270 .p = { .min = 4, .max = 128 },
271 .p1 = { .min = 2, .max = 33 },
272 .p2 = { .dot_limit = 165000,
273 .p2_slow = 4, .p2_fast = 2 },
274 };
275
276 static const struct intel_limit intel_limits_i8xx_dvo = {
277 .dot = { .min = 25000, .max = 350000 },
278 .vco = { .min = 908000, .max = 1512000 },
279 .n = { .min = 2, .max = 16 },
280 .m = { .min = 96, .max = 140 },
281 .m1 = { .min = 18, .max = 26 },
282 .m2 = { .min = 6, .max = 16 },
283 .p = { .min = 4, .max = 128 },
284 .p1 = { .min = 2, .max = 33 },
285 .p2 = { .dot_limit = 165000,
286 .p2_slow = 4, .p2_fast = 4 },
287 };
288
289 static const struct intel_limit intel_limits_i8xx_lvds = {
290 .dot = { .min = 25000, .max = 350000 },
291 .vco = { .min = 908000, .max = 1512000 },
292 .n = { .min = 2, .max = 16 },
293 .m = { .min = 96, .max = 140 },
294 .m1 = { .min = 18, .max = 26 },
295 .m2 = { .min = 6, .max = 16 },
296 .p = { .min = 4, .max = 128 },
297 .p1 = { .min = 1, .max = 6 },
298 .p2 = { .dot_limit = 165000,
299 .p2_slow = 14, .p2_fast = 7 },
300 };
301
302 static const struct intel_limit intel_limits_i9xx_sdvo = {
303 .dot = { .min = 20000, .max = 400000 },
304 .vco = { .min = 1400000, .max = 2800000 },
305 .n = { .min = 1, .max = 6 },
306 .m = { .min = 70, .max = 120 },
307 .m1 = { .min = 8, .max = 18 },
308 .m2 = { .min = 3, .max = 7 },
309 .p = { .min = 5, .max = 80 },
310 .p1 = { .min = 1, .max = 8 },
311 .p2 = { .dot_limit = 200000,
312 .p2_slow = 10, .p2_fast = 5 },
313 };
314
315 static const struct intel_limit intel_limits_i9xx_lvds = {
316 .dot = { .min = 20000, .max = 400000 },
317 .vco = { .min = 1400000, .max = 2800000 },
318 .n = { .min = 1, .max = 6 },
319 .m = { .min = 70, .max = 120 },
320 .m1 = { .min = 8, .max = 18 },
321 .m2 = { .min = 3, .max = 7 },
322 .p = { .min = 7, .max = 98 },
323 .p1 = { .min = 1, .max = 8 },
324 .p2 = { .dot_limit = 112000,
325 .p2_slow = 14, .p2_fast = 7 },
326 };
327
328
329 static const struct intel_limit intel_limits_g4x_sdvo = {
330 .dot = { .min = 25000, .max = 270000 },
331 .vco = { .min = 1750000, .max = 3500000},
332 .n = { .min = 1, .max = 4 },
333 .m = { .min = 104, .max = 138 },
334 .m1 = { .min = 17, .max = 23 },
335 .m2 = { .min = 5, .max = 11 },
336 .p = { .min = 10, .max = 30 },
337 .p1 = { .min = 1, .max = 3},
338 .p2 = { .dot_limit = 270000,
339 .p2_slow = 10,
340 .p2_fast = 10
341 },
342 };
343
344 static const struct intel_limit intel_limits_g4x_hdmi = {
345 .dot = { .min = 22000, .max = 400000 },
346 .vco = { .min = 1750000, .max = 3500000},
347 .n = { .min = 1, .max = 4 },
348 .m = { .min = 104, .max = 138 },
349 .m1 = { .min = 16, .max = 23 },
350 .m2 = { .min = 5, .max = 11 },
351 .p = { .min = 5, .max = 80 },
352 .p1 = { .min = 1, .max = 8},
353 .p2 = { .dot_limit = 165000,
354 .p2_slow = 10, .p2_fast = 5 },
355 };
356
357 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
358 .dot = { .min = 20000, .max = 115000 },
359 .vco = { .min = 1750000, .max = 3500000 },
360 .n = { .min = 1, .max = 3 },
361 .m = { .min = 104, .max = 138 },
362 .m1 = { .min = 17, .max = 23 },
363 .m2 = { .min = 5, .max = 11 },
364 .p = { .min = 28, .max = 112 },
365 .p1 = { .min = 2, .max = 8 },
366 .p2 = { .dot_limit = 0,
367 .p2_slow = 14, .p2_fast = 14
368 },
369 };
370
371 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
372 .dot = { .min = 80000, .max = 224000 },
373 .vco = { .min = 1750000, .max = 3500000 },
374 .n = { .min = 1, .max = 3 },
375 .m = { .min = 104, .max = 138 },
376 .m1 = { .min = 17, .max = 23 },
377 .m2 = { .min = 5, .max = 11 },
378 .p = { .min = 14, .max = 42 },
379 .p1 = { .min = 2, .max = 6 },
380 .p2 = { .dot_limit = 0,
381 .p2_slow = 7, .p2_fast = 7
382 },
383 };
384
385 static const struct intel_limit intel_limits_pineview_sdvo = {
386 .dot = { .min = 20000, .max = 400000},
387 .vco = { .min = 1700000, .max = 3500000 },
388 /* Pineview's Ncounter is a ring counter */
389 .n = { .min = 3, .max = 6 },
390 .m = { .min = 2, .max = 256 },
391 /* Pineview only has one combined m divider, which we treat as m2. */
392 .m1 = { .min = 0, .max = 0 },
393 .m2 = { .min = 0, .max = 254 },
394 .p = { .min = 5, .max = 80 },
395 .p1 = { .min = 1, .max = 8 },
396 .p2 = { .dot_limit = 200000,
397 .p2_slow = 10, .p2_fast = 5 },
398 };
399
400 static const struct intel_limit intel_limits_pineview_lvds = {
401 .dot = { .min = 20000, .max = 400000 },
402 .vco = { .min = 1700000, .max = 3500000 },
403 .n = { .min = 3, .max = 6 },
404 .m = { .min = 2, .max = 256 },
405 .m1 = { .min = 0, .max = 0 },
406 .m2 = { .min = 0, .max = 254 },
407 .p = { .min = 7, .max = 112 },
408 .p1 = { .min = 1, .max = 8 },
409 .p2 = { .dot_limit = 112000,
410 .p2_slow = 14, .p2_fast = 14 },
411 };
412
413 /* Ironlake / Sandybridge
414 *
415 * We calculate clock using (register_value + 2) for N/M1/M2, so here
416 * the range value for them is (actual_value - 2).
417 */
418 static const struct intel_limit intel_limits_ironlake_dac = {
419 .dot = { .min = 25000, .max = 350000 },
420 .vco = { .min = 1760000, .max = 3510000 },
421 .n = { .min = 1, .max = 5 },
422 .m = { .min = 79, .max = 127 },
423 .m1 = { .min = 12, .max = 22 },
424 .m2 = { .min = 5, .max = 9 },
425 .p = { .min = 5, .max = 80 },
426 .p1 = { .min = 1, .max = 8 },
427 .p2 = { .dot_limit = 225000,
428 .p2_slow = 10, .p2_fast = 5 },
429 };
430
431 static const struct intel_limit intel_limits_ironlake_single_lvds = {
432 .dot = { .min = 25000, .max = 350000 },
433 .vco = { .min = 1760000, .max = 3510000 },
434 .n = { .min = 1, .max = 3 },
435 .m = { .min = 79, .max = 118 },
436 .m1 = { .min = 12, .max = 22 },
437 .m2 = { .min = 5, .max = 9 },
438 .p = { .min = 28, .max = 112 },
439 .p1 = { .min = 2, .max = 8 },
440 .p2 = { .dot_limit = 225000,
441 .p2_slow = 14, .p2_fast = 14 },
442 };
443
444 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
445 .dot = { .min = 25000, .max = 350000 },
446 .vco = { .min = 1760000, .max = 3510000 },
447 .n = { .min = 1, .max = 3 },
448 .m = { .min = 79, .max = 127 },
449 .m1 = { .min = 12, .max = 22 },
450 .m2 = { .min = 5, .max = 9 },
451 .p = { .min = 14, .max = 56 },
452 .p1 = { .min = 2, .max = 8 },
453 .p2 = { .dot_limit = 225000,
454 .p2_slow = 7, .p2_fast = 7 },
455 };
456
457 /* LVDS 100mhz refclk limits. */
458 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
459 .dot = { .min = 25000, .max = 350000 },
460 .vco = { .min = 1760000, .max = 3510000 },
461 .n = { .min = 1, .max = 2 },
462 .m = { .min = 79, .max = 126 },
463 .m1 = { .min = 12, .max = 22 },
464 .m2 = { .min = 5, .max = 9 },
465 .p = { .min = 28, .max = 112 },
466 .p1 = { .min = 2, .max = 8 },
467 .p2 = { .dot_limit = 225000,
468 .p2_slow = 14, .p2_fast = 14 },
469 };
470
471 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
472 .dot = { .min = 25000, .max = 350000 },
473 .vco = { .min = 1760000, .max = 3510000 },
474 .n = { .min = 1, .max = 3 },
475 .m = { .min = 79, .max = 126 },
476 .m1 = { .min = 12, .max = 22 },
477 .m2 = { .min = 5, .max = 9 },
478 .p = { .min = 14, .max = 42 },
479 .p1 = { .min = 2, .max = 6 },
480 .p2 = { .dot_limit = 225000,
481 .p2_slow = 7, .p2_fast = 7 },
482 };
483
484 static const struct intel_limit intel_limits_vlv = {
485 /*
486 * These are the data rate limits (measured in fast clocks)
487 * since those are the strictest limits we have. The fast
488 * clock and actual rate limits are more relaxed, so checking
489 * them would make no difference.
490 */
491 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
492 .vco = { .min = 4000000, .max = 6000000 },
493 .n = { .min = 1, .max = 7 },
494 .m1 = { .min = 2, .max = 3 },
495 .m2 = { .min = 11, .max = 156 },
496 .p1 = { .min = 2, .max = 3 },
497 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
498 };
499
500 static const struct intel_limit intel_limits_chv = {
501 /*
502 * These are the data rate limits (measured in fast clocks)
503 * since those are the strictest limits we have. The fast
504 * clock and actual rate limits are more relaxed, so checking
505 * them would make no difference.
506 */
507 .dot = { .min = 25000 * 5, .max = 540000 * 5},
508 .vco = { .min = 4800000, .max = 6480000 },
509 .n = { .min = 1, .max = 1 },
510 .m1 = { .min = 2, .max = 2 },
511 .m2 = { .min = 24 << 22, .max = 175 << 22 },
512 .p1 = { .min = 2, .max = 4 },
513 .p2 = { .p2_slow = 1, .p2_fast = 14 },
514 };
515
516 static const struct intel_limit intel_limits_bxt = {
517 /* FIXME: find real dot limits */
518 .dot = { .min = 0, .max = INT_MAX },
519 .vco = { .min = 4800000, .max = 6700000 },
520 .n = { .min = 1, .max = 1 },
521 .m1 = { .min = 2, .max = 2 },
522 /* FIXME: find real m2 limits */
523 .m2 = { .min = 2 << 22, .max = 255 << 22 },
524 .p1 = { .min = 2, .max = 4 },
525 .p2 = { .p2_slow = 1, .p2_fast = 20 },
526 };
527
528 static bool
529 needs_modeset(struct drm_crtc_state *state)
530 {
531 return drm_atomic_crtc_needs_modeset(state);
532 }
533
534 /*
535 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
536 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
537 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
538 * The helpers' return value is the rate of the clock that is fed to the
539 * display engine's pipe which can be the above fast dot clock rate or a
540 * divided-down version of it.
541 */
542 /* m1 is reserved as 0 in Pineview, n is a ring counter */
543 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
544 {
545 clock->m = clock->m2 + 2;
546 clock->p = clock->p1 * clock->p2;
547 if (WARN_ON(clock->n == 0 || clock->p == 0))
548 return 0;
549 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
550 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
551
552 return clock->dot;
553 }
554
555 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
556 {
557 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
558 }
559
560 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
561 {
562 clock->m = i9xx_dpll_compute_m(clock);
563 clock->p = clock->p1 * clock->p2;
564 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
565 return 0;
566 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
567 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
568
569 return clock->dot;
570 }
571
572 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
573 {
574 clock->m = clock->m1 * clock->m2;
575 clock->p = clock->p1 * clock->p2;
576 if (WARN_ON(clock->n == 0 || clock->p == 0))
577 return 0;
578 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
579 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
580
581 return clock->dot / 5;
582 }
583
584 int chv_calc_dpll_params(int refclk, struct dpll *clock)
585 {
586 clock->m = clock->m1 * clock->m2;
587 clock->p = clock->p1 * clock->p2;
588 if (WARN_ON(clock->n == 0 || clock->p == 0))
589 return 0;
590 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
591 clock->n << 22);
592 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
593
594 return clock->dot / 5;
595 }
596
597 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
598 /**
599 * Returns whether the given set of divisors are valid for a given refclk with
600 * the given connectors.
601 */
602
603 static bool intel_PLL_is_valid(struct drm_device *dev,
604 const struct intel_limit *limit,
605 const struct dpll *clock)
606 {
607 if (clock->n < limit->n.min || limit->n.max < clock->n)
608 INTELPllInvalid("n out of range\n");
609 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
610 INTELPllInvalid("p1 out of range\n");
611 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
612 INTELPllInvalid("m2 out of range\n");
613 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
614 INTELPllInvalid("m1 out of range\n");
615
616 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
617 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
618 if (clock->m1 <= clock->m2)
619 INTELPllInvalid("m1 <= m2\n");
620
621 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
622 if (clock->p < limit->p.min || limit->p.max < clock->p)
623 INTELPllInvalid("p out of range\n");
624 if (clock->m < limit->m.min || limit->m.max < clock->m)
625 INTELPllInvalid("m out of range\n");
626 }
627
628 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
629 INTELPllInvalid("vco out of range\n");
630 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
631 * connector, etc., rather than just a single range.
632 */
633 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
634 INTELPllInvalid("dot out of range\n");
635
636 return true;
637 }
638
639 static int
640 i9xx_select_p2_div(const struct intel_limit *limit,
641 const struct intel_crtc_state *crtc_state,
642 int target)
643 {
644 struct drm_device *dev = crtc_state->base.crtc->dev;
645
646 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
647 /*
648 * For LVDS just rely on its current settings for dual-channel.
649 * We haven't figured out how to reliably set up different
650 * single/dual channel state, if we even can.
651 */
652 if (intel_is_dual_link_lvds(dev))
653 return limit->p2.p2_fast;
654 else
655 return limit->p2.p2_slow;
656 } else {
657 if (target < limit->p2.dot_limit)
658 return limit->p2.p2_slow;
659 else
660 return limit->p2.p2_fast;
661 }
662 }
663
664 /*
665 * Returns a set of divisors for the desired target clock with the given
666 * refclk, or FALSE. The returned values represent the clock equation:
667 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
668 *
669 * Target and reference clocks are specified in kHz.
670 *
671 * If match_clock is provided, then best_clock P divider must match the P
672 * divider from @match_clock used for LVDS downclocking.
673 */
674 static bool
675 i9xx_find_best_dpll(const struct intel_limit *limit,
676 struct intel_crtc_state *crtc_state,
677 int target, int refclk, struct dpll *match_clock,
678 struct dpll *best_clock)
679 {
680 struct drm_device *dev = crtc_state->base.crtc->dev;
681 struct dpll clock;
682 int err = target;
683
684 memset(best_clock, 0, sizeof(*best_clock));
685
686 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
687
688 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
689 clock.m1++) {
690 for (clock.m2 = limit->m2.min;
691 clock.m2 <= limit->m2.max; clock.m2++) {
692 if (clock.m2 >= clock.m1)
693 break;
694 for (clock.n = limit->n.min;
695 clock.n <= limit->n.max; clock.n++) {
696 for (clock.p1 = limit->p1.min;
697 clock.p1 <= limit->p1.max; clock.p1++) {
698 int this_err;
699
700 i9xx_calc_dpll_params(refclk, &clock);
701 if (!intel_PLL_is_valid(dev, limit,
702 &clock))
703 continue;
704 if (match_clock &&
705 clock.p != match_clock->p)
706 continue;
707
708 this_err = abs(clock.dot - target);
709 if (this_err < err) {
710 *best_clock = clock;
711 err = this_err;
712 }
713 }
714 }
715 }
716 }
717
718 return (err != target);
719 }
720
721 /*
722 * Returns a set of divisors for the desired target clock with the given
723 * refclk, or FALSE. The returned values represent the clock equation:
724 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
725 *
726 * Target and reference clocks are specified in kHz.
727 *
728 * If match_clock is provided, then best_clock P divider must match the P
729 * divider from @match_clock used for LVDS downclocking.
730 */
731 static bool
732 pnv_find_best_dpll(const struct intel_limit *limit,
733 struct intel_crtc_state *crtc_state,
734 int target, int refclk, struct dpll *match_clock,
735 struct dpll *best_clock)
736 {
737 struct drm_device *dev = crtc_state->base.crtc->dev;
738 struct dpll clock;
739 int err = target;
740
741 memset(best_clock, 0, sizeof(*best_clock));
742
743 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
744
745 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
746 clock.m1++) {
747 for (clock.m2 = limit->m2.min;
748 clock.m2 <= limit->m2.max; clock.m2++) {
749 for (clock.n = limit->n.min;
750 clock.n <= limit->n.max; clock.n++) {
751 for (clock.p1 = limit->p1.min;
752 clock.p1 <= limit->p1.max; clock.p1++) {
753 int this_err;
754
755 pnv_calc_dpll_params(refclk, &clock);
756 if (!intel_PLL_is_valid(dev, limit,
757 &clock))
758 continue;
759 if (match_clock &&
760 clock.p != match_clock->p)
761 continue;
762
763 this_err = abs(clock.dot - target);
764 if (this_err < err) {
765 *best_clock = clock;
766 err = this_err;
767 }
768 }
769 }
770 }
771 }
772
773 return (err != target);
774 }
775
776 /*
777 * Returns a set of divisors for the desired target clock with the given
778 * refclk, or FALSE. The returned values represent the clock equation:
779 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
780 *
781 * Target and reference clocks are specified in kHz.
782 *
783 * If match_clock is provided, then best_clock P divider must match the P
784 * divider from @match_clock used for LVDS downclocking.
785 */
786 static bool
787 g4x_find_best_dpll(const struct intel_limit *limit,
788 struct intel_crtc_state *crtc_state,
789 int target, int refclk, struct dpll *match_clock,
790 struct dpll *best_clock)
791 {
792 struct drm_device *dev = crtc_state->base.crtc->dev;
793 struct dpll clock;
794 int max_n;
795 bool found = false;
796 /* approximately equals target * 0.00585 */
797 int err_most = (target >> 8) + (target >> 9);
798
799 memset(best_clock, 0, sizeof(*best_clock));
800
801 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
802
803 max_n = limit->n.max;
804 /* based on hardware requirement, prefer smaller n to precision */
805 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
806 /* based on hardware requirement, prefere larger m1,m2 */
807 for (clock.m1 = limit->m1.max;
808 clock.m1 >= limit->m1.min; clock.m1--) {
809 for (clock.m2 = limit->m2.max;
810 clock.m2 >= limit->m2.min; clock.m2--) {
811 for (clock.p1 = limit->p1.max;
812 clock.p1 >= limit->p1.min; clock.p1--) {
813 int this_err;
814
815 i9xx_calc_dpll_params(refclk, &clock);
816 if (!intel_PLL_is_valid(dev, limit,
817 &clock))
818 continue;
819
820 this_err = abs(clock.dot - target);
821 if (this_err < err_most) {
822 *best_clock = clock;
823 err_most = this_err;
824 max_n = clock.n;
825 found = true;
826 }
827 }
828 }
829 }
830 }
831 return found;
832 }
833
834 /*
835 * Check if the calculated PLL configuration is more optimal compared to the
836 * best configuration and error found so far. Return the calculated error.
837 */
838 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
839 const struct dpll *calculated_clock,
840 const struct dpll *best_clock,
841 unsigned int best_error_ppm,
842 unsigned int *error_ppm)
843 {
844 /*
845 * For CHV ignore the error and consider only the P value.
846 * Prefer a bigger P value based on HW requirements.
847 */
848 if (IS_CHERRYVIEW(dev)) {
849 *error_ppm = 0;
850
851 return calculated_clock->p > best_clock->p;
852 }
853
854 if (WARN_ON_ONCE(!target_freq))
855 return false;
856
857 *error_ppm = div_u64(1000000ULL *
858 abs(target_freq - calculated_clock->dot),
859 target_freq);
860 /*
861 * Prefer a better P value over a better (smaller) error if the error
862 * is small. Ensure this preference for future configurations too by
863 * setting the error to 0.
864 */
865 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
866 *error_ppm = 0;
867
868 return true;
869 }
870
871 return *error_ppm + 10 < best_error_ppm;
872 }
873
874 /*
875 * Returns a set of divisors for the desired target clock with the given
876 * refclk, or FALSE. The returned values represent the clock equation:
877 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
878 */
879 static bool
880 vlv_find_best_dpll(const struct intel_limit *limit,
881 struct intel_crtc_state *crtc_state,
882 int target, int refclk, struct dpll *match_clock,
883 struct dpll *best_clock)
884 {
885 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
886 struct drm_device *dev = crtc->base.dev;
887 struct dpll clock;
888 unsigned int bestppm = 1000000;
889 /* min update 19.2 MHz */
890 int max_n = min(limit->n.max, refclk / 19200);
891 bool found = false;
892
893 target *= 5; /* fast clock */
894
895 memset(best_clock, 0, sizeof(*best_clock));
896
897 /* based on hardware requirement, prefer smaller n to precision */
898 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
899 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
900 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
901 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
902 clock.p = clock.p1 * clock.p2;
903 /* based on hardware requirement, prefer bigger m1,m2 values */
904 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
905 unsigned int ppm;
906
907 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
908 refclk * clock.m1);
909
910 vlv_calc_dpll_params(refclk, &clock);
911
912 if (!intel_PLL_is_valid(dev, limit,
913 &clock))
914 continue;
915
916 if (!vlv_PLL_is_optimal(dev, target,
917 &clock,
918 best_clock,
919 bestppm, &ppm))
920 continue;
921
922 *best_clock = clock;
923 bestppm = ppm;
924 found = true;
925 }
926 }
927 }
928 }
929
930 return found;
931 }
932
933 /*
934 * Returns a set of divisors for the desired target clock with the given
935 * refclk, or FALSE. The returned values represent the clock equation:
936 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
937 */
938 static bool
939 chv_find_best_dpll(const struct intel_limit *limit,
940 struct intel_crtc_state *crtc_state,
941 int target, int refclk, struct dpll *match_clock,
942 struct dpll *best_clock)
943 {
944 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
945 struct drm_device *dev = crtc->base.dev;
946 unsigned int best_error_ppm;
947 struct dpll clock;
948 uint64_t m2;
949 int found = false;
950
951 memset(best_clock, 0, sizeof(*best_clock));
952 best_error_ppm = 1000000;
953
954 /*
955 * Based on hardware doc, the n always set to 1, and m1 always
956 * set to 2. If requires to support 200Mhz refclk, we need to
957 * revisit this because n may not 1 anymore.
958 */
959 clock.n = 1, clock.m1 = 2;
960 target *= 5; /* fast clock */
961
962 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
963 for (clock.p2 = limit->p2.p2_fast;
964 clock.p2 >= limit->p2.p2_slow;
965 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
966 unsigned int error_ppm;
967
968 clock.p = clock.p1 * clock.p2;
969
970 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
971 clock.n) << 22, refclk * clock.m1);
972
973 if (m2 > INT_MAX/clock.m1)
974 continue;
975
976 clock.m2 = m2;
977
978 chv_calc_dpll_params(refclk, &clock);
979
980 if (!intel_PLL_is_valid(dev, limit, &clock))
981 continue;
982
983 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
984 best_error_ppm, &error_ppm))
985 continue;
986
987 *best_clock = clock;
988 best_error_ppm = error_ppm;
989 found = true;
990 }
991 }
992
993 return found;
994 }
995
996 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
997 struct dpll *best_clock)
998 {
999 int refclk = 100000;
1000 const struct intel_limit *limit = &intel_limits_bxt;
1001
1002 return chv_find_best_dpll(limit, crtc_state,
1003 target_clock, refclk, NULL, best_clock);
1004 }
1005
1006 bool intel_crtc_active(struct drm_crtc *crtc)
1007 {
1008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1009
1010 /* Be paranoid as we can arrive here with only partial
1011 * state retrieved from the hardware during setup.
1012 *
1013 * We can ditch the adjusted_mode.crtc_clock check as soon
1014 * as Haswell has gained clock readout/fastboot support.
1015 *
1016 * We can ditch the crtc->primary->fb check as soon as we can
1017 * properly reconstruct framebuffers.
1018 *
1019 * FIXME: The intel_crtc->active here should be switched to
1020 * crtc->state->active once we have proper CRTC states wired up
1021 * for atomic.
1022 */
1023 return intel_crtc->active && crtc->primary->state->fb &&
1024 intel_crtc->config->base.adjusted_mode.crtc_clock;
1025 }
1026
1027 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1028 enum pipe pipe)
1029 {
1030 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1032
1033 return intel_crtc->config->cpu_transcoder;
1034 }
1035
1036 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1037 {
1038 struct drm_i915_private *dev_priv = to_i915(dev);
1039 i915_reg_t reg = PIPEDSL(pipe);
1040 u32 line1, line2;
1041 u32 line_mask;
1042
1043 if (IS_GEN2(dev))
1044 line_mask = DSL_LINEMASK_GEN2;
1045 else
1046 line_mask = DSL_LINEMASK_GEN3;
1047
1048 line1 = I915_READ(reg) & line_mask;
1049 msleep(5);
1050 line2 = I915_READ(reg) & line_mask;
1051
1052 return line1 == line2;
1053 }
1054
1055 /*
1056 * intel_wait_for_pipe_off - wait for pipe to turn off
1057 * @crtc: crtc whose pipe to wait for
1058 *
1059 * After disabling a pipe, we can't wait for vblank in the usual way,
1060 * spinning on the vblank interrupt status bit, since we won't actually
1061 * see an interrupt when the pipe is disabled.
1062 *
1063 * On Gen4 and above:
1064 * wait for the pipe register state bit to turn off
1065 *
1066 * Otherwise:
1067 * wait for the display line value to settle (it usually
1068 * ends up stopping at the start of the next frame).
1069 *
1070 */
1071 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1072 {
1073 struct drm_device *dev = crtc->base.dev;
1074 struct drm_i915_private *dev_priv = to_i915(dev);
1075 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1076 enum pipe pipe = crtc->pipe;
1077
1078 if (INTEL_INFO(dev)->gen >= 4) {
1079 i915_reg_t reg = PIPECONF(cpu_transcoder);
1080
1081 /* Wait for the Pipe State to go off */
1082 if (intel_wait_for_register(dev_priv,
1083 reg, I965_PIPECONF_ACTIVE, 0,
1084 100))
1085 WARN(1, "pipe_off wait timed out\n");
1086 } else {
1087 /* Wait for the display line to settle */
1088 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1089 WARN(1, "pipe_off wait timed out\n");
1090 }
1091 }
1092
1093 /* Only for pre-ILK configs */
1094 void assert_pll(struct drm_i915_private *dev_priv,
1095 enum pipe pipe, bool state)
1096 {
1097 u32 val;
1098 bool cur_state;
1099
1100 val = I915_READ(DPLL(pipe));
1101 cur_state = !!(val & DPLL_VCO_ENABLE);
1102 I915_STATE_WARN(cur_state != state,
1103 "PLL state assertion failure (expected %s, current %s)\n",
1104 onoff(state), onoff(cur_state));
1105 }
1106
1107 /* XXX: the dsi pll is shared between MIPI DSI ports */
1108 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1109 {
1110 u32 val;
1111 bool cur_state;
1112
1113 mutex_lock(&dev_priv->sb_lock);
1114 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1115 mutex_unlock(&dev_priv->sb_lock);
1116
1117 cur_state = val & DSI_PLL_VCO_EN;
1118 I915_STATE_WARN(cur_state != state,
1119 "DSI PLL state assertion failure (expected %s, current %s)\n",
1120 onoff(state), onoff(cur_state));
1121 }
1122
1123 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1124 enum pipe pipe, bool state)
1125 {
1126 bool cur_state;
1127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128 pipe);
1129
1130 if (HAS_DDI(dev_priv)) {
1131 /* DDI does not have a specific FDI_TX register */
1132 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1133 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1134 } else {
1135 u32 val = I915_READ(FDI_TX_CTL(pipe));
1136 cur_state = !!(val & FDI_TX_ENABLE);
1137 }
1138 I915_STATE_WARN(cur_state != state,
1139 "FDI TX state assertion failure (expected %s, current %s)\n",
1140 onoff(state), onoff(cur_state));
1141 }
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146 enum pipe pipe, bool state)
1147 {
1148 u32 val;
1149 bool cur_state;
1150
1151 val = I915_READ(FDI_RX_CTL(pipe));
1152 cur_state = !!(val & FDI_RX_ENABLE);
1153 I915_STATE_WARN(cur_state != state,
1154 "FDI RX state assertion failure (expected %s, current %s)\n",
1155 onoff(state), onoff(cur_state));
1156 }
1157 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1158 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1159
1160 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1161 enum pipe pipe)
1162 {
1163 u32 val;
1164
1165 /* ILK FDI PLL is always enabled */
1166 if (IS_GEN5(dev_priv))
1167 return;
1168
1169 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1170 if (HAS_DDI(dev_priv))
1171 return;
1172
1173 val = I915_READ(FDI_TX_CTL(pipe));
1174 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178 enum pipe pipe, bool state)
1179 {
1180 u32 val;
1181 bool cur_state;
1182
1183 val = I915_READ(FDI_RX_CTL(pipe));
1184 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1185 I915_STATE_WARN(cur_state != state,
1186 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1187 onoff(state), onoff(cur_state));
1188 }
1189
1190 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1191 enum pipe pipe)
1192 {
1193 struct drm_device *dev = &dev_priv->drm;
1194 i915_reg_t pp_reg;
1195 u32 val;
1196 enum pipe panel_pipe = PIPE_A;
1197 bool locked = true;
1198
1199 if (WARN_ON(HAS_DDI(dev)))
1200 return;
1201
1202 if (HAS_PCH_SPLIT(dev)) {
1203 u32 port_sel;
1204
1205 pp_reg = PP_CONTROL(0);
1206 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1207
1208 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1209 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1211 /* XXX: else fix for eDP */
1212 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1213 /* presumably write lock depends on pipe, not port select */
1214 pp_reg = PP_CONTROL(pipe);
1215 panel_pipe = pipe;
1216 } else {
1217 pp_reg = PP_CONTROL(0);
1218 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1219 panel_pipe = PIPE_B;
1220 }
1221
1222 val = I915_READ(pp_reg);
1223 if (!(val & PANEL_POWER_ON) ||
1224 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1225 locked = false;
1226
1227 I915_STATE_WARN(panel_pipe == pipe && locked,
1228 "panel assertion failure, pipe %c regs locked\n",
1229 pipe_name(pipe));
1230 }
1231
1232 static void assert_cursor(struct drm_i915_private *dev_priv,
1233 enum pipe pipe, bool state)
1234 {
1235 struct drm_device *dev = &dev_priv->drm;
1236 bool cur_state;
1237
1238 if (IS_845G(dev) || IS_I865G(dev))
1239 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1240 else
1241 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1242
1243 I915_STATE_WARN(cur_state != state,
1244 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1245 pipe_name(pipe), onoff(state), onoff(cur_state));
1246 }
1247 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1248 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1249
1250 void assert_pipe(struct drm_i915_private *dev_priv,
1251 enum pipe pipe, bool state)
1252 {
1253 bool cur_state;
1254 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1255 pipe);
1256 enum intel_display_power_domain power_domain;
1257
1258 /* if we need the pipe quirk it must be always on */
1259 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1260 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1261 state = true;
1262
1263 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1264 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1265 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1266 cur_state = !!(val & PIPECONF_ENABLE);
1267
1268 intel_display_power_put(dev_priv, power_domain);
1269 } else {
1270 cur_state = false;
1271 }
1272
1273 I915_STATE_WARN(cur_state != state,
1274 "pipe %c assertion failure (expected %s, current %s)\n",
1275 pipe_name(pipe), onoff(state), onoff(cur_state));
1276 }
1277
1278 static void assert_plane(struct drm_i915_private *dev_priv,
1279 enum plane plane, bool state)
1280 {
1281 u32 val;
1282 bool cur_state;
1283
1284 val = I915_READ(DSPCNTR(plane));
1285 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1286 I915_STATE_WARN(cur_state != state,
1287 "plane %c assertion failure (expected %s, current %s)\n",
1288 plane_name(plane), onoff(state), onoff(cur_state));
1289 }
1290
1291 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1292 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1293
1294 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1295 enum pipe pipe)
1296 {
1297 struct drm_device *dev = &dev_priv->drm;
1298 int i;
1299
1300 /* Primary planes are fixed to pipes on gen4+ */
1301 if (INTEL_INFO(dev)->gen >= 4) {
1302 u32 val = I915_READ(DSPCNTR(pipe));
1303 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1304 "plane %c assertion failure, should be disabled but not\n",
1305 plane_name(pipe));
1306 return;
1307 }
1308
1309 /* Need to check both planes against the pipe */
1310 for_each_pipe(dev_priv, i) {
1311 u32 val = I915_READ(DSPCNTR(i));
1312 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1313 DISPPLANE_SEL_PIPE_SHIFT;
1314 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1315 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1316 plane_name(i), pipe_name(pipe));
1317 }
1318 }
1319
1320 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1321 enum pipe pipe)
1322 {
1323 struct drm_device *dev = &dev_priv->drm;
1324 int sprite;
1325
1326 if (INTEL_INFO(dev)->gen >= 9) {
1327 for_each_sprite(dev_priv, pipe, sprite) {
1328 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1329 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1330 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1331 sprite, pipe_name(pipe));
1332 }
1333 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1334 for_each_sprite(dev_priv, pipe, sprite) {
1335 u32 val = I915_READ(SPCNTR(pipe, sprite));
1336 I915_STATE_WARN(val & SP_ENABLE,
1337 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1338 sprite_name(pipe, sprite), pipe_name(pipe));
1339 }
1340 } else if (INTEL_INFO(dev)->gen >= 7) {
1341 u32 val = I915_READ(SPRCTL(pipe));
1342 I915_STATE_WARN(val & SPRITE_ENABLE,
1343 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344 plane_name(pipe), pipe_name(pipe));
1345 } else if (INTEL_INFO(dev)->gen >= 5) {
1346 u32 val = I915_READ(DVSCNTR(pipe));
1347 I915_STATE_WARN(val & DVS_ENABLE,
1348 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1349 plane_name(pipe), pipe_name(pipe));
1350 }
1351 }
1352
1353 static void assert_vblank_disabled(struct drm_crtc *crtc)
1354 {
1355 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1356 drm_crtc_vblank_put(crtc);
1357 }
1358
1359 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1360 enum pipe pipe)
1361 {
1362 u32 val;
1363 bool enabled;
1364
1365 val = I915_READ(PCH_TRANSCONF(pipe));
1366 enabled = !!(val & TRANS_ENABLE);
1367 I915_STATE_WARN(enabled,
1368 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1369 pipe_name(pipe));
1370 }
1371
1372 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe, u32 port_sel, u32 val)
1374 {
1375 if ((val & DP_PORT_EN) == 0)
1376 return false;
1377
1378 if (HAS_PCH_CPT(dev_priv)) {
1379 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1380 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1381 return false;
1382 } else if (IS_CHERRYVIEW(dev_priv)) {
1383 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1384 return false;
1385 } else {
1386 if ((val & DP_PIPE_MASK) != (pipe << 30))
1387 return false;
1388 }
1389 return true;
1390 }
1391
1392 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1393 enum pipe pipe, u32 val)
1394 {
1395 if ((val & SDVO_ENABLE) == 0)
1396 return false;
1397
1398 if (HAS_PCH_CPT(dev_priv)) {
1399 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1400 return false;
1401 } else if (IS_CHERRYVIEW(dev_priv)) {
1402 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1403 return false;
1404 } else {
1405 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1406 return false;
1407 }
1408 return true;
1409 }
1410
1411 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1412 enum pipe pipe, u32 val)
1413 {
1414 if ((val & LVDS_PORT_EN) == 0)
1415 return false;
1416
1417 if (HAS_PCH_CPT(dev_priv)) {
1418 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1419 return false;
1420 } else {
1421 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1422 return false;
1423 }
1424 return true;
1425 }
1426
1427 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1428 enum pipe pipe, u32 val)
1429 {
1430 if ((val & ADPA_DAC_ENABLE) == 0)
1431 return false;
1432 if (HAS_PCH_CPT(dev_priv)) {
1433 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1434 return false;
1435 } else {
1436 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1437 return false;
1438 }
1439 return true;
1440 }
1441
1442 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1443 enum pipe pipe, i915_reg_t reg,
1444 u32 port_sel)
1445 {
1446 u32 val = I915_READ(reg);
1447 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1448 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1449 i915_mmio_reg_offset(reg), pipe_name(pipe));
1450
1451 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1452 && (val & DP_PIPEB_SELECT),
1453 "IBX PCH dp port still using transcoder B\n");
1454 }
1455
1456 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1457 enum pipe pipe, i915_reg_t reg)
1458 {
1459 u32 val = I915_READ(reg);
1460 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1461 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1462 i915_mmio_reg_offset(reg), pipe_name(pipe));
1463
1464 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1465 && (val & SDVO_PIPE_B_SELECT),
1466 "IBX PCH hdmi port still using transcoder B\n");
1467 }
1468
1469 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1470 enum pipe pipe)
1471 {
1472 u32 val;
1473
1474 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1475 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1476 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1477
1478 val = I915_READ(PCH_ADPA);
1479 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1480 "PCH VGA enabled on transcoder %c, should be disabled\n",
1481 pipe_name(pipe));
1482
1483 val = I915_READ(PCH_LVDS);
1484 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1485 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1486 pipe_name(pipe));
1487
1488 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1489 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1490 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1491 }
1492
1493 static void _vlv_enable_pll(struct intel_crtc *crtc,
1494 const struct intel_crtc_state *pipe_config)
1495 {
1496 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1497 enum pipe pipe = crtc->pipe;
1498
1499 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1500 POSTING_READ(DPLL(pipe));
1501 udelay(150);
1502
1503 if (intel_wait_for_register(dev_priv,
1504 DPLL(pipe),
1505 DPLL_LOCK_VLV,
1506 DPLL_LOCK_VLV,
1507 1))
1508 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1509 }
1510
1511 static void vlv_enable_pll(struct intel_crtc *crtc,
1512 const struct intel_crtc_state *pipe_config)
1513 {
1514 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1515 enum pipe pipe = crtc->pipe;
1516
1517 assert_pipe_disabled(dev_priv, pipe);
1518
1519 /* PLL is protected by panel, make sure we can write it */
1520 assert_panel_unlocked(dev_priv, pipe);
1521
1522 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1523 _vlv_enable_pll(crtc, pipe_config);
1524
1525 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1526 POSTING_READ(DPLL_MD(pipe));
1527 }
1528
1529
1530 static void _chv_enable_pll(struct intel_crtc *crtc,
1531 const struct intel_crtc_state *pipe_config)
1532 {
1533 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1534 enum pipe pipe = crtc->pipe;
1535 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1536 u32 tmp;
1537
1538 mutex_lock(&dev_priv->sb_lock);
1539
1540 /* Enable back the 10bit clock to display controller */
1541 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1542 tmp |= DPIO_DCLKP_EN;
1543 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1544
1545 mutex_unlock(&dev_priv->sb_lock);
1546
1547 /*
1548 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1549 */
1550 udelay(1);
1551
1552 /* Enable PLL */
1553 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1554
1555 /* Check PLL is locked */
1556 if (intel_wait_for_register(dev_priv,
1557 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1558 1))
1559 DRM_ERROR("PLL %d failed to lock\n", pipe);
1560 }
1561
1562 static void chv_enable_pll(struct intel_crtc *crtc,
1563 const struct intel_crtc_state *pipe_config)
1564 {
1565 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1566 enum pipe pipe = crtc->pipe;
1567
1568 assert_pipe_disabled(dev_priv, pipe);
1569
1570 /* PLL is protected by panel, make sure we can write it */
1571 assert_panel_unlocked(dev_priv, pipe);
1572
1573 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1574 _chv_enable_pll(crtc, pipe_config);
1575
1576 if (pipe != PIPE_A) {
1577 /*
1578 * WaPixelRepeatModeFixForC0:chv
1579 *
1580 * DPLLCMD is AWOL. Use chicken bits to propagate
1581 * the value from DPLLBMD to either pipe B or C.
1582 */
1583 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1584 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1585 I915_WRITE(CBR4_VLV, 0);
1586 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1587
1588 /*
1589 * DPLLB VGA mode also seems to cause problems.
1590 * We should always have it disabled.
1591 */
1592 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1593 } else {
1594 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1595 POSTING_READ(DPLL_MD(pipe));
1596 }
1597 }
1598
1599 static int intel_num_dvo_pipes(struct drm_device *dev)
1600 {
1601 struct intel_crtc *crtc;
1602 int count = 0;
1603
1604 for_each_intel_crtc(dev, crtc) {
1605 count += crtc->base.state->active &&
1606 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1607 }
1608
1609 return count;
1610 }
1611
1612 static void i9xx_enable_pll(struct intel_crtc *crtc)
1613 {
1614 struct drm_device *dev = crtc->base.dev;
1615 struct drm_i915_private *dev_priv = to_i915(dev);
1616 i915_reg_t reg = DPLL(crtc->pipe);
1617 u32 dpll = crtc->config->dpll_hw_state.dpll;
1618
1619 assert_pipe_disabled(dev_priv, crtc->pipe);
1620
1621 /* PLL is protected by panel, make sure we can write it */
1622 if (IS_MOBILE(dev) && !IS_I830(dev))
1623 assert_panel_unlocked(dev_priv, crtc->pipe);
1624
1625 /* Enable DVO 2x clock on both PLLs if necessary */
1626 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1627 /*
1628 * It appears to be important that we don't enable this
1629 * for the current pipe before otherwise configuring the
1630 * PLL. No idea how this should be handled if multiple
1631 * DVO outputs are enabled simultaneosly.
1632 */
1633 dpll |= DPLL_DVO_2X_MODE;
1634 I915_WRITE(DPLL(!crtc->pipe),
1635 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1636 }
1637
1638 /*
1639 * Apparently we need to have VGA mode enabled prior to changing
1640 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1641 * dividers, even though the register value does change.
1642 */
1643 I915_WRITE(reg, 0);
1644
1645 I915_WRITE(reg, dpll);
1646
1647 /* Wait for the clocks to stabilize. */
1648 POSTING_READ(reg);
1649 udelay(150);
1650
1651 if (INTEL_INFO(dev)->gen >= 4) {
1652 I915_WRITE(DPLL_MD(crtc->pipe),
1653 crtc->config->dpll_hw_state.dpll_md);
1654 } else {
1655 /* The pixel multiplier can only be updated once the
1656 * DPLL is enabled and the clocks are stable.
1657 *
1658 * So write it again.
1659 */
1660 I915_WRITE(reg, dpll);
1661 }
1662
1663 /* We do this three times for luck */
1664 I915_WRITE(reg, dpll);
1665 POSTING_READ(reg);
1666 udelay(150); /* wait for warmup */
1667 I915_WRITE(reg, dpll);
1668 POSTING_READ(reg);
1669 udelay(150); /* wait for warmup */
1670 I915_WRITE(reg, dpll);
1671 POSTING_READ(reg);
1672 udelay(150); /* wait for warmup */
1673 }
1674
1675 /**
1676 * i9xx_disable_pll - disable a PLL
1677 * @dev_priv: i915 private structure
1678 * @pipe: pipe PLL to disable
1679 *
1680 * Disable the PLL for @pipe, making sure the pipe is off first.
1681 *
1682 * Note! This is for pre-ILK only.
1683 */
1684 static void i9xx_disable_pll(struct intel_crtc *crtc)
1685 {
1686 struct drm_device *dev = crtc->base.dev;
1687 struct drm_i915_private *dev_priv = to_i915(dev);
1688 enum pipe pipe = crtc->pipe;
1689
1690 /* Disable DVO 2x clock on both PLLs if necessary */
1691 if (IS_I830(dev) &&
1692 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1693 !intel_num_dvo_pipes(dev)) {
1694 I915_WRITE(DPLL(PIPE_B),
1695 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1696 I915_WRITE(DPLL(PIPE_A),
1697 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1698 }
1699
1700 /* Don't disable pipe or pipe PLLs if needed */
1701 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1702 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1703 return;
1704
1705 /* Make sure the pipe isn't still relying on us */
1706 assert_pipe_disabled(dev_priv, pipe);
1707
1708 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1709 POSTING_READ(DPLL(pipe));
1710 }
1711
1712 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1713 {
1714 u32 val;
1715
1716 /* Make sure the pipe isn't still relying on us */
1717 assert_pipe_disabled(dev_priv, pipe);
1718
1719 val = DPLL_INTEGRATED_REF_CLK_VLV |
1720 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1721 if (pipe != PIPE_A)
1722 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1723
1724 I915_WRITE(DPLL(pipe), val);
1725 POSTING_READ(DPLL(pipe));
1726 }
1727
1728 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1729 {
1730 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1731 u32 val;
1732
1733 /* Make sure the pipe isn't still relying on us */
1734 assert_pipe_disabled(dev_priv, pipe);
1735
1736 val = DPLL_SSC_REF_CLK_CHV |
1737 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1738 if (pipe != PIPE_A)
1739 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1740
1741 I915_WRITE(DPLL(pipe), val);
1742 POSTING_READ(DPLL(pipe));
1743
1744 mutex_lock(&dev_priv->sb_lock);
1745
1746 /* Disable 10bit clock to display controller */
1747 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1748 val &= ~DPIO_DCLKP_EN;
1749 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1750
1751 mutex_unlock(&dev_priv->sb_lock);
1752 }
1753
1754 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1755 struct intel_digital_port *dport,
1756 unsigned int expected_mask)
1757 {
1758 u32 port_mask;
1759 i915_reg_t dpll_reg;
1760
1761 switch (dport->port) {
1762 case PORT_B:
1763 port_mask = DPLL_PORTB_READY_MASK;
1764 dpll_reg = DPLL(0);
1765 break;
1766 case PORT_C:
1767 port_mask = DPLL_PORTC_READY_MASK;
1768 dpll_reg = DPLL(0);
1769 expected_mask <<= 4;
1770 break;
1771 case PORT_D:
1772 port_mask = DPLL_PORTD_READY_MASK;
1773 dpll_reg = DPIO_PHY_STATUS;
1774 break;
1775 default:
1776 BUG();
1777 }
1778
1779 if (intel_wait_for_register(dev_priv,
1780 dpll_reg, port_mask, expected_mask,
1781 1000))
1782 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1783 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1784 }
1785
1786 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1787 enum pipe pipe)
1788 {
1789 struct drm_device *dev = &dev_priv->drm;
1790 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1792 i915_reg_t reg;
1793 uint32_t val, pipeconf_val;
1794
1795 /* Make sure PCH DPLL is enabled */
1796 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1797
1798 /* FDI must be feeding us bits for PCH ports */
1799 assert_fdi_tx_enabled(dev_priv, pipe);
1800 assert_fdi_rx_enabled(dev_priv, pipe);
1801
1802 if (HAS_PCH_CPT(dev)) {
1803 /* Workaround: Set the timing override bit before enabling the
1804 * pch transcoder. */
1805 reg = TRANS_CHICKEN2(pipe);
1806 val = I915_READ(reg);
1807 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1808 I915_WRITE(reg, val);
1809 }
1810
1811 reg = PCH_TRANSCONF(pipe);
1812 val = I915_READ(reg);
1813 pipeconf_val = I915_READ(PIPECONF(pipe));
1814
1815 if (HAS_PCH_IBX(dev_priv)) {
1816 /*
1817 * Make the BPC in transcoder be consistent with
1818 * that in pipeconf reg. For HDMI we must use 8bpc
1819 * here for both 8bpc and 12bpc.
1820 */
1821 val &= ~PIPECONF_BPC_MASK;
1822 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1823 val |= PIPECONF_8BPC;
1824 else
1825 val |= pipeconf_val & PIPECONF_BPC_MASK;
1826 }
1827
1828 val &= ~TRANS_INTERLACE_MASK;
1829 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1830 if (HAS_PCH_IBX(dev_priv) &&
1831 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1832 val |= TRANS_LEGACY_INTERLACED_ILK;
1833 else
1834 val |= TRANS_INTERLACED;
1835 else
1836 val |= TRANS_PROGRESSIVE;
1837
1838 I915_WRITE(reg, val | TRANS_ENABLE);
1839 if (intel_wait_for_register(dev_priv,
1840 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1841 100))
1842 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1843 }
1844
1845 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1846 enum transcoder cpu_transcoder)
1847 {
1848 u32 val, pipeconf_val;
1849
1850 /* FDI must be feeding us bits for PCH ports */
1851 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1852 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1853
1854 /* Workaround: set timing override bit. */
1855 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1856 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1857 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1858
1859 val = TRANS_ENABLE;
1860 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1861
1862 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1863 PIPECONF_INTERLACED_ILK)
1864 val |= TRANS_INTERLACED;
1865 else
1866 val |= TRANS_PROGRESSIVE;
1867
1868 I915_WRITE(LPT_TRANSCONF, val);
1869 if (intel_wait_for_register(dev_priv,
1870 LPT_TRANSCONF,
1871 TRANS_STATE_ENABLE,
1872 TRANS_STATE_ENABLE,
1873 100))
1874 DRM_ERROR("Failed to enable PCH transcoder\n");
1875 }
1876
1877 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1878 enum pipe pipe)
1879 {
1880 struct drm_device *dev = &dev_priv->drm;
1881 i915_reg_t reg;
1882 uint32_t val;
1883
1884 /* FDI relies on the transcoder */
1885 assert_fdi_tx_disabled(dev_priv, pipe);
1886 assert_fdi_rx_disabled(dev_priv, pipe);
1887
1888 /* Ports must be off as well */
1889 assert_pch_ports_disabled(dev_priv, pipe);
1890
1891 reg = PCH_TRANSCONF(pipe);
1892 val = I915_READ(reg);
1893 val &= ~TRANS_ENABLE;
1894 I915_WRITE(reg, val);
1895 /* wait for PCH transcoder off, transcoder state */
1896 if (intel_wait_for_register(dev_priv,
1897 reg, TRANS_STATE_ENABLE, 0,
1898 50))
1899 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1900
1901 if (HAS_PCH_CPT(dev)) {
1902 /* Workaround: Clear the timing override chicken bit again. */
1903 reg = TRANS_CHICKEN2(pipe);
1904 val = I915_READ(reg);
1905 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1906 I915_WRITE(reg, val);
1907 }
1908 }
1909
1910 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1911 {
1912 u32 val;
1913
1914 val = I915_READ(LPT_TRANSCONF);
1915 val &= ~TRANS_ENABLE;
1916 I915_WRITE(LPT_TRANSCONF, val);
1917 /* wait for PCH transcoder off, transcoder state */
1918 if (intel_wait_for_register(dev_priv,
1919 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1920 50))
1921 DRM_ERROR("Failed to disable PCH transcoder\n");
1922
1923 /* Workaround: clear timing override bit. */
1924 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1925 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1926 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1927 }
1928
1929 /**
1930 * intel_enable_pipe - enable a pipe, asserting requirements
1931 * @crtc: crtc responsible for the pipe
1932 *
1933 * Enable @crtc's pipe, making sure that various hardware specific requirements
1934 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1935 */
1936 static void intel_enable_pipe(struct intel_crtc *crtc)
1937 {
1938 struct drm_device *dev = crtc->base.dev;
1939 struct drm_i915_private *dev_priv = to_i915(dev);
1940 enum pipe pipe = crtc->pipe;
1941 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1942 enum pipe pch_transcoder;
1943 i915_reg_t reg;
1944 u32 val;
1945
1946 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1947
1948 assert_planes_disabled(dev_priv, pipe);
1949 assert_cursor_disabled(dev_priv, pipe);
1950 assert_sprites_disabled(dev_priv, pipe);
1951
1952 if (HAS_PCH_LPT(dev_priv))
1953 pch_transcoder = TRANSCODER_A;
1954 else
1955 pch_transcoder = pipe;
1956
1957 /*
1958 * A pipe without a PLL won't actually be able to drive bits from
1959 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1960 * need the check.
1961 */
1962 if (HAS_GMCH_DISPLAY(dev_priv)) {
1963 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1964 assert_dsi_pll_enabled(dev_priv);
1965 else
1966 assert_pll_enabled(dev_priv, pipe);
1967 } else {
1968 if (crtc->config->has_pch_encoder) {
1969 /* if driving the PCH, we need FDI enabled */
1970 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1971 assert_fdi_tx_pll_enabled(dev_priv,
1972 (enum pipe) cpu_transcoder);
1973 }
1974 /* FIXME: assert CPU port conditions for SNB+ */
1975 }
1976
1977 reg = PIPECONF(cpu_transcoder);
1978 val = I915_READ(reg);
1979 if (val & PIPECONF_ENABLE) {
1980 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1981 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1982 return;
1983 }
1984
1985 I915_WRITE(reg, val | PIPECONF_ENABLE);
1986 POSTING_READ(reg);
1987
1988 /*
1989 * Until the pipe starts DSL will read as 0, which would cause
1990 * an apparent vblank timestamp jump, which messes up also the
1991 * frame count when it's derived from the timestamps. So let's
1992 * wait for the pipe to start properly before we call
1993 * drm_crtc_vblank_on()
1994 */
1995 if (dev->max_vblank_count == 0 &&
1996 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1997 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1998 }
1999
2000 /**
2001 * intel_disable_pipe - disable a pipe, asserting requirements
2002 * @crtc: crtc whose pipes is to be disabled
2003 *
2004 * Disable the pipe of @crtc, making sure that various hardware
2005 * specific requirements are met, if applicable, e.g. plane
2006 * disabled, panel fitter off, etc.
2007 *
2008 * Will wait until the pipe has shut down before returning.
2009 */
2010 static void intel_disable_pipe(struct intel_crtc *crtc)
2011 {
2012 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2013 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2014 enum pipe pipe = crtc->pipe;
2015 i915_reg_t reg;
2016 u32 val;
2017
2018 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2019
2020 /*
2021 * Make sure planes won't keep trying to pump pixels to us,
2022 * or we might hang the display.
2023 */
2024 assert_planes_disabled(dev_priv, pipe);
2025 assert_cursor_disabled(dev_priv, pipe);
2026 assert_sprites_disabled(dev_priv, pipe);
2027
2028 reg = PIPECONF(cpu_transcoder);
2029 val = I915_READ(reg);
2030 if ((val & PIPECONF_ENABLE) == 0)
2031 return;
2032
2033 /*
2034 * Double wide has implications for planes
2035 * so best keep it disabled when not needed.
2036 */
2037 if (crtc->config->double_wide)
2038 val &= ~PIPECONF_DOUBLE_WIDE;
2039
2040 /* Don't disable pipe or pipe PLLs if needed */
2041 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2042 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2043 val &= ~PIPECONF_ENABLE;
2044
2045 I915_WRITE(reg, val);
2046 if ((val & PIPECONF_ENABLE) == 0)
2047 intel_wait_for_pipe_off(crtc);
2048 }
2049
2050 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2051 {
2052 return IS_GEN2(dev_priv) ? 2048 : 4096;
2053 }
2054
2055 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2056 uint64_t fb_modifier, unsigned int cpp)
2057 {
2058 switch (fb_modifier) {
2059 case DRM_FORMAT_MOD_NONE:
2060 return cpp;
2061 case I915_FORMAT_MOD_X_TILED:
2062 if (IS_GEN2(dev_priv))
2063 return 128;
2064 else
2065 return 512;
2066 case I915_FORMAT_MOD_Y_TILED:
2067 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2068 return 128;
2069 else
2070 return 512;
2071 case I915_FORMAT_MOD_Yf_TILED:
2072 switch (cpp) {
2073 case 1:
2074 return 64;
2075 case 2:
2076 case 4:
2077 return 128;
2078 case 8:
2079 case 16:
2080 return 256;
2081 default:
2082 MISSING_CASE(cpp);
2083 return cpp;
2084 }
2085 break;
2086 default:
2087 MISSING_CASE(fb_modifier);
2088 return cpp;
2089 }
2090 }
2091
2092 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2093 uint64_t fb_modifier, unsigned int cpp)
2094 {
2095 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2096 return 1;
2097 else
2098 return intel_tile_size(dev_priv) /
2099 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2100 }
2101
2102 /* Return the tile dimensions in pixel units */
2103 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2104 unsigned int *tile_width,
2105 unsigned int *tile_height,
2106 uint64_t fb_modifier,
2107 unsigned int cpp)
2108 {
2109 unsigned int tile_width_bytes =
2110 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2111
2112 *tile_width = tile_width_bytes / cpp;
2113 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2114 }
2115
2116 unsigned int
2117 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2118 uint32_t pixel_format, uint64_t fb_modifier)
2119 {
2120 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2121 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2122
2123 return ALIGN(height, tile_height);
2124 }
2125
2126 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2127 {
2128 unsigned int size = 0;
2129 int i;
2130
2131 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2132 size += rot_info->plane[i].width * rot_info->plane[i].height;
2133
2134 return size;
2135 }
2136
2137 static void
2138 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2139 const struct drm_framebuffer *fb,
2140 unsigned int rotation)
2141 {
2142 if (intel_rotation_90_or_270(rotation)) {
2143 *view = i915_ggtt_view_rotated;
2144 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2145 } else {
2146 *view = i915_ggtt_view_normal;
2147 }
2148 }
2149
2150 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2151 {
2152 if (INTEL_INFO(dev_priv)->gen >= 9)
2153 return 256 * 1024;
2154 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2155 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2156 return 128 * 1024;
2157 else if (INTEL_INFO(dev_priv)->gen >= 4)
2158 return 4 * 1024;
2159 else
2160 return 0;
2161 }
2162
2163 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2164 uint64_t fb_modifier)
2165 {
2166 switch (fb_modifier) {
2167 case DRM_FORMAT_MOD_NONE:
2168 return intel_linear_alignment(dev_priv);
2169 case I915_FORMAT_MOD_X_TILED:
2170 if (INTEL_INFO(dev_priv)->gen >= 9)
2171 return 256 * 1024;
2172 return 0;
2173 case I915_FORMAT_MOD_Y_TILED:
2174 case I915_FORMAT_MOD_Yf_TILED:
2175 return 1 * 1024 * 1024;
2176 default:
2177 MISSING_CASE(fb_modifier);
2178 return 0;
2179 }
2180 }
2181
2182 struct i915_vma *
2183 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2184 {
2185 struct drm_device *dev = fb->dev;
2186 struct drm_i915_private *dev_priv = to_i915(dev);
2187 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2188 struct i915_ggtt_view view;
2189 struct i915_vma *vma;
2190 u32 alignment;
2191
2192 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2193
2194 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2195
2196 intel_fill_fb_ggtt_view(&view, fb, rotation);
2197
2198 /* Note that the w/a also requires 64 PTE of padding following the
2199 * bo. We currently fill all unused PTE with the shadow page and so
2200 * we should always have valid PTE following the scanout preventing
2201 * the VT-d warning.
2202 */
2203 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2204 alignment = 256 * 1024;
2205
2206 /*
2207 * Global gtt pte registers are special registers which actually forward
2208 * writes to a chunk of system memory. Which means that there is no risk
2209 * that the register values disappear as soon as we call
2210 * intel_runtime_pm_put(), so it is correct to wrap only the
2211 * pin/unpin/fence and not more.
2212 */
2213 intel_runtime_pm_get(dev_priv);
2214
2215 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2216 if (IS_ERR(vma))
2217 goto err;
2218
2219 if (i915_vma_is_map_and_fenceable(vma)) {
2220 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2221 * fence, whereas 965+ only requires a fence if using
2222 * framebuffer compression. For simplicity, we always, when
2223 * possible, install a fence as the cost is not that onerous.
2224 *
2225 * If we fail to fence the tiled scanout, then either the
2226 * modeset will reject the change (which is highly unlikely as
2227 * the affected systems, all but one, do not have unmappable
2228 * space) or we will not be able to enable full powersaving
2229 * techniques (also likely not to apply due to various limits
2230 * FBC and the like impose on the size of the buffer, which
2231 * presumably we violated anyway with this unmappable buffer).
2232 * Anyway, it is presumably better to stumble onwards with
2233 * something and try to run the system in a "less than optimal"
2234 * mode that matches the user configuration.
2235 */
2236 if (i915_vma_get_fence(vma) == 0)
2237 i915_vma_pin_fence(vma);
2238 }
2239
2240 err:
2241 intel_runtime_pm_put(dev_priv);
2242 return vma;
2243 }
2244
2245 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2246 {
2247 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2248 struct i915_ggtt_view view;
2249 struct i915_vma *vma;
2250
2251 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2252
2253 intel_fill_fb_ggtt_view(&view, fb, rotation);
2254 vma = i915_gem_object_to_ggtt(obj, &view);
2255
2256 i915_vma_unpin_fence(vma);
2257 i915_gem_object_unpin_from_display_plane(vma);
2258 }
2259
2260 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2261 unsigned int rotation)
2262 {
2263 if (intel_rotation_90_or_270(rotation))
2264 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2265 else
2266 return fb->pitches[plane];
2267 }
2268
2269 /*
2270 * Convert the x/y offsets into a linear offset.
2271 * Only valid with 0/180 degree rotation, which is fine since linear
2272 * offset is only used with linear buffers on pre-hsw and tiled buffers
2273 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2274 */
2275 u32 intel_fb_xy_to_linear(int x, int y,
2276 const struct intel_plane_state *state,
2277 int plane)
2278 {
2279 const struct drm_framebuffer *fb = state->base.fb;
2280 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2281 unsigned int pitch = fb->pitches[plane];
2282
2283 return y * pitch + x * cpp;
2284 }
2285
2286 /*
2287 * Add the x/y offsets derived from fb->offsets[] to the user
2288 * specified plane src x/y offsets. The resulting x/y offsets
2289 * specify the start of scanout from the beginning of the gtt mapping.
2290 */
2291 void intel_add_fb_offsets(int *x, int *y,
2292 const struct intel_plane_state *state,
2293 int plane)
2294
2295 {
2296 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2297 unsigned int rotation = state->base.rotation;
2298
2299 if (intel_rotation_90_or_270(rotation)) {
2300 *x += intel_fb->rotated[plane].x;
2301 *y += intel_fb->rotated[plane].y;
2302 } else {
2303 *x += intel_fb->normal[plane].x;
2304 *y += intel_fb->normal[plane].y;
2305 }
2306 }
2307
2308 /*
2309 * Input tile dimensions and pitch must already be
2310 * rotated to match x and y, and in pixel units.
2311 */
2312 static u32 _intel_adjust_tile_offset(int *x, int *y,
2313 unsigned int tile_width,
2314 unsigned int tile_height,
2315 unsigned int tile_size,
2316 unsigned int pitch_tiles,
2317 u32 old_offset,
2318 u32 new_offset)
2319 {
2320 unsigned int pitch_pixels = pitch_tiles * tile_width;
2321 unsigned int tiles;
2322
2323 WARN_ON(old_offset & (tile_size - 1));
2324 WARN_ON(new_offset & (tile_size - 1));
2325 WARN_ON(new_offset > old_offset);
2326
2327 tiles = (old_offset - new_offset) / tile_size;
2328
2329 *y += tiles / pitch_tiles * tile_height;
2330 *x += tiles % pitch_tiles * tile_width;
2331
2332 /* minimize x in case it got needlessly big */
2333 *y += *x / pitch_pixels * tile_height;
2334 *x %= pitch_pixels;
2335
2336 return new_offset;
2337 }
2338
2339 /*
2340 * Adjust the tile offset by moving the difference into
2341 * the x/y offsets.
2342 */
2343 static u32 intel_adjust_tile_offset(int *x, int *y,
2344 const struct intel_plane_state *state, int plane,
2345 u32 old_offset, u32 new_offset)
2346 {
2347 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2348 const struct drm_framebuffer *fb = state->base.fb;
2349 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2350 unsigned int rotation = state->base.rotation;
2351 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2352
2353 WARN_ON(new_offset > old_offset);
2354
2355 if (fb->modifier[plane] != DRM_FORMAT_MOD_NONE) {
2356 unsigned int tile_size, tile_width, tile_height;
2357 unsigned int pitch_tiles;
2358
2359 tile_size = intel_tile_size(dev_priv);
2360 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2361 fb->modifier[plane], cpp);
2362
2363 if (intel_rotation_90_or_270(rotation)) {
2364 pitch_tiles = pitch / tile_height;
2365 swap(tile_width, tile_height);
2366 } else {
2367 pitch_tiles = pitch / (tile_width * cpp);
2368 }
2369
2370 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2371 tile_size, pitch_tiles,
2372 old_offset, new_offset);
2373 } else {
2374 old_offset += *y * pitch + *x * cpp;
2375
2376 *y = (old_offset - new_offset) / pitch;
2377 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2378 }
2379
2380 return new_offset;
2381 }
2382
2383 /*
2384 * Computes the linear offset to the base tile and adjusts
2385 * x, y. bytes per pixel is assumed to be a power-of-two.
2386 *
2387 * In the 90/270 rotated case, x and y are assumed
2388 * to be already rotated to match the rotated GTT view, and
2389 * pitch is the tile_height aligned framebuffer height.
2390 *
2391 * This function is used when computing the derived information
2392 * under intel_framebuffer, so using any of that information
2393 * here is not allowed. Anything under drm_framebuffer can be
2394 * used. This is why the user has to pass in the pitch since it
2395 * is specified in the rotated orientation.
2396 */
2397 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2398 int *x, int *y,
2399 const struct drm_framebuffer *fb, int plane,
2400 unsigned int pitch,
2401 unsigned int rotation,
2402 u32 alignment)
2403 {
2404 uint64_t fb_modifier = fb->modifier[plane];
2405 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2406 u32 offset, offset_aligned;
2407
2408 if (alignment)
2409 alignment--;
2410
2411 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2412 unsigned int tile_size, tile_width, tile_height;
2413 unsigned int tile_rows, tiles, pitch_tiles;
2414
2415 tile_size = intel_tile_size(dev_priv);
2416 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2417 fb_modifier, cpp);
2418
2419 if (intel_rotation_90_or_270(rotation)) {
2420 pitch_tiles = pitch / tile_height;
2421 swap(tile_width, tile_height);
2422 } else {
2423 pitch_tiles = pitch / (tile_width * cpp);
2424 }
2425
2426 tile_rows = *y / tile_height;
2427 *y %= tile_height;
2428
2429 tiles = *x / tile_width;
2430 *x %= tile_width;
2431
2432 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2433 offset_aligned = offset & ~alignment;
2434
2435 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2436 tile_size, pitch_tiles,
2437 offset, offset_aligned);
2438 } else {
2439 offset = *y * pitch + *x * cpp;
2440 offset_aligned = offset & ~alignment;
2441
2442 *y = (offset & alignment) / pitch;
2443 *x = ((offset & alignment) - *y * pitch) / cpp;
2444 }
2445
2446 return offset_aligned;
2447 }
2448
2449 u32 intel_compute_tile_offset(int *x, int *y,
2450 const struct intel_plane_state *state,
2451 int plane)
2452 {
2453 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2454 const struct drm_framebuffer *fb = state->base.fb;
2455 unsigned int rotation = state->base.rotation;
2456 int pitch = intel_fb_pitch(fb, plane, rotation);
2457 u32 alignment;
2458
2459 /* AUX_DIST needs only 4K alignment */
2460 if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1)
2461 alignment = 4096;
2462 else
2463 alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]);
2464
2465 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2466 rotation, alignment);
2467 }
2468
2469 /* Convert the fb->offset[] linear offset into x/y offsets */
2470 static void intel_fb_offset_to_xy(int *x, int *y,
2471 const struct drm_framebuffer *fb, int plane)
2472 {
2473 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2474 unsigned int pitch = fb->pitches[plane];
2475 u32 linear_offset = fb->offsets[plane];
2476
2477 *y = linear_offset / pitch;
2478 *x = linear_offset % pitch / cpp;
2479 }
2480
2481 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2482 {
2483 switch (fb_modifier) {
2484 case I915_FORMAT_MOD_X_TILED:
2485 return I915_TILING_X;
2486 case I915_FORMAT_MOD_Y_TILED:
2487 return I915_TILING_Y;
2488 default:
2489 return I915_TILING_NONE;
2490 }
2491 }
2492
2493 static int
2494 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2495 struct drm_framebuffer *fb)
2496 {
2497 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2498 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2499 u32 gtt_offset_rotated = 0;
2500 unsigned int max_size = 0;
2501 uint32_t format = fb->pixel_format;
2502 int i, num_planes = drm_format_num_planes(format);
2503 unsigned int tile_size = intel_tile_size(dev_priv);
2504
2505 for (i = 0; i < num_planes; i++) {
2506 unsigned int width, height;
2507 unsigned int cpp, size;
2508 u32 offset;
2509 int x, y;
2510
2511 cpp = drm_format_plane_cpp(format, i);
2512 width = drm_format_plane_width(fb->width, format, i);
2513 height = drm_format_plane_height(fb->height, format, i);
2514
2515 intel_fb_offset_to_xy(&x, &y, fb, i);
2516
2517 /*
2518 * The fence (if used) is aligned to the start of the object
2519 * so having the framebuffer wrap around across the edge of the
2520 * fenced region doesn't really work. We have no API to configure
2521 * the fence start offset within the object (nor could we probably
2522 * on gen2/3). So it's just easier if we just require that the
2523 * fb layout agrees with the fence layout. We already check that the
2524 * fb stride matches the fence stride elsewhere.
2525 */
2526 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2527 (x + width) * cpp > fb->pitches[i]) {
2528 DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2529 i, fb->offsets[i]);
2530 return -EINVAL;
2531 }
2532
2533 /*
2534 * First pixel of the framebuffer from
2535 * the start of the normal gtt mapping.
2536 */
2537 intel_fb->normal[i].x = x;
2538 intel_fb->normal[i].y = y;
2539
2540 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2541 fb, 0, fb->pitches[i],
2542 DRM_ROTATE_0, tile_size);
2543 offset /= tile_size;
2544
2545 if (fb->modifier[i] != DRM_FORMAT_MOD_NONE) {
2546 unsigned int tile_width, tile_height;
2547 unsigned int pitch_tiles;
2548 struct drm_rect r;
2549
2550 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2551 fb->modifier[i], cpp);
2552
2553 rot_info->plane[i].offset = offset;
2554 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2555 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2556 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2557
2558 intel_fb->rotated[i].pitch =
2559 rot_info->plane[i].height * tile_height;
2560
2561 /* how many tiles does this plane need */
2562 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2563 /*
2564 * If the plane isn't horizontally tile aligned,
2565 * we need one more tile.
2566 */
2567 if (x != 0)
2568 size++;
2569
2570 /* rotate the x/y offsets to match the GTT view */
2571 r.x1 = x;
2572 r.y1 = y;
2573 r.x2 = x + width;
2574 r.y2 = y + height;
2575 drm_rect_rotate(&r,
2576 rot_info->plane[i].width * tile_width,
2577 rot_info->plane[i].height * tile_height,
2578 DRM_ROTATE_270);
2579 x = r.x1;
2580 y = r.y1;
2581
2582 /* rotate the tile dimensions to match the GTT view */
2583 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2584 swap(tile_width, tile_height);
2585
2586 /*
2587 * We only keep the x/y offsets, so push all of the
2588 * gtt offset into the x/y offsets.
2589 */
2590 _intel_adjust_tile_offset(&x, &y, tile_size,
2591 tile_width, tile_height, pitch_tiles,
2592 gtt_offset_rotated * tile_size, 0);
2593
2594 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2595
2596 /*
2597 * First pixel of the framebuffer from
2598 * the start of the rotated gtt mapping.
2599 */
2600 intel_fb->rotated[i].x = x;
2601 intel_fb->rotated[i].y = y;
2602 } else {
2603 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2604 x * cpp, tile_size);
2605 }
2606
2607 /* how many tiles in total needed in the bo */
2608 max_size = max(max_size, offset + size);
2609 }
2610
2611 if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2612 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2613 max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2614 return -EINVAL;
2615 }
2616
2617 return 0;
2618 }
2619
2620 static int i9xx_format_to_fourcc(int format)
2621 {
2622 switch (format) {
2623 case DISPPLANE_8BPP:
2624 return DRM_FORMAT_C8;
2625 case DISPPLANE_BGRX555:
2626 return DRM_FORMAT_XRGB1555;
2627 case DISPPLANE_BGRX565:
2628 return DRM_FORMAT_RGB565;
2629 default:
2630 case DISPPLANE_BGRX888:
2631 return DRM_FORMAT_XRGB8888;
2632 case DISPPLANE_RGBX888:
2633 return DRM_FORMAT_XBGR8888;
2634 case DISPPLANE_BGRX101010:
2635 return DRM_FORMAT_XRGB2101010;
2636 case DISPPLANE_RGBX101010:
2637 return DRM_FORMAT_XBGR2101010;
2638 }
2639 }
2640
2641 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2642 {
2643 switch (format) {
2644 case PLANE_CTL_FORMAT_RGB_565:
2645 return DRM_FORMAT_RGB565;
2646 default:
2647 case PLANE_CTL_FORMAT_XRGB_8888:
2648 if (rgb_order) {
2649 if (alpha)
2650 return DRM_FORMAT_ABGR8888;
2651 else
2652 return DRM_FORMAT_XBGR8888;
2653 } else {
2654 if (alpha)
2655 return DRM_FORMAT_ARGB8888;
2656 else
2657 return DRM_FORMAT_XRGB8888;
2658 }
2659 case PLANE_CTL_FORMAT_XRGB_2101010:
2660 if (rgb_order)
2661 return DRM_FORMAT_XBGR2101010;
2662 else
2663 return DRM_FORMAT_XRGB2101010;
2664 }
2665 }
2666
2667 static bool
2668 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2669 struct intel_initial_plane_config *plane_config)
2670 {
2671 struct drm_device *dev = crtc->base.dev;
2672 struct drm_i915_private *dev_priv = to_i915(dev);
2673 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2674 struct drm_i915_gem_object *obj = NULL;
2675 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2676 struct drm_framebuffer *fb = &plane_config->fb->base;
2677 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2678 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2679 PAGE_SIZE);
2680
2681 size_aligned -= base_aligned;
2682
2683 if (plane_config->size == 0)
2684 return false;
2685
2686 /* If the FB is too big, just don't use it since fbdev is not very
2687 * important and we should probably use that space with FBC or other
2688 * features. */
2689 if (size_aligned * 2 > ggtt->stolen_usable_size)
2690 return false;
2691
2692 mutex_lock(&dev->struct_mutex);
2693
2694 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2695 base_aligned,
2696 base_aligned,
2697 size_aligned);
2698 if (!obj) {
2699 mutex_unlock(&dev->struct_mutex);
2700 return false;
2701 }
2702
2703 if (plane_config->tiling == I915_TILING_X)
2704 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2705
2706 mode_cmd.pixel_format = fb->pixel_format;
2707 mode_cmd.width = fb->width;
2708 mode_cmd.height = fb->height;
2709 mode_cmd.pitches[0] = fb->pitches[0];
2710 mode_cmd.modifier[0] = fb->modifier[0];
2711 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2712
2713 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2714 &mode_cmd, obj)) {
2715 DRM_DEBUG_KMS("intel fb init failed\n");
2716 goto out_unref_obj;
2717 }
2718
2719 mutex_unlock(&dev->struct_mutex);
2720
2721 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2722 return true;
2723
2724 out_unref_obj:
2725 i915_gem_object_put(obj);
2726 mutex_unlock(&dev->struct_mutex);
2727 return false;
2728 }
2729
2730 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2731 static void
2732 update_state_fb(struct drm_plane *plane)
2733 {
2734 if (plane->fb == plane->state->fb)
2735 return;
2736
2737 if (plane->state->fb)
2738 drm_framebuffer_unreference(plane->state->fb);
2739 plane->state->fb = plane->fb;
2740 if (plane->state->fb)
2741 drm_framebuffer_reference(plane->state->fb);
2742 }
2743
2744 static void
2745 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2746 struct intel_initial_plane_config *plane_config)
2747 {
2748 struct drm_device *dev = intel_crtc->base.dev;
2749 struct drm_i915_private *dev_priv = to_i915(dev);
2750 struct drm_crtc *c;
2751 struct intel_crtc *i;
2752 struct drm_i915_gem_object *obj;
2753 struct drm_plane *primary = intel_crtc->base.primary;
2754 struct drm_plane_state *plane_state = primary->state;
2755 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2756 struct intel_plane *intel_plane = to_intel_plane(primary);
2757 struct intel_plane_state *intel_state =
2758 to_intel_plane_state(plane_state);
2759 struct drm_framebuffer *fb;
2760
2761 if (!plane_config->fb)
2762 return;
2763
2764 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2765 fb = &plane_config->fb->base;
2766 goto valid_fb;
2767 }
2768
2769 kfree(plane_config->fb);
2770
2771 /*
2772 * Failed to alloc the obj, check to see if we should share
2773 * an fb with another CRTC instead
2774 */
2775 for_each_crtc(dev, c) {
2776 i = to_intel_crtc(c);
2777
2778 if (c == &intel_crtc->base)
2779 continue;
2780
2781 if (!i->active)
2782 continue;
2783
2784 fb = c->primary->fb;
2785 if (!fb)
2786 continue;
2787
2788 obj = intel_fb_obj(fb);
2789 if (i915_gem_object_ggtt_offset(obj, NULL) == plane_config->base) {
2790 drm_framebuffer_reference(fb);
2791 goto valid_fb;
2792 }
2793 }
2794
2795 /*
2796 * We've failed to reconstruct the BIOS FB. Current display state
2797 * indicates that the primary plane is visible, but has a NULL FB,
2798 * which will lead to problems later if we don't fix it up. The
2799 * simplest solution is to just disable the primary plane now and
2800 * pretend the BIOS never had it enabled.
2801 */
2802 to_intel_plane_state(plane_state)->base.visible = false;
2803 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2804 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2805 intel_plane->disable_plane(primary, &intel_crtc->base);
2806
2807 return;
2808
2809 valid_fb:
2810 plane_state->src_x = 0;
2811 plane_state->src_y = 0;
2812 plane_state->src_w = fb->width << 16;
2813 plane_state->src_h = fb->height << 16;
2814
2815 plane_state->crtc_x = 0;
2816 plane_state->crtc_y = 0;
2817 plane_state->crtc_w = fb->width;
2818 plane_state->crtc_h = fb->height;
2819
2820 intel_state->base.src.x1 = plane_state->src_x;
2821 intel_state->base.src.y1 = plane_state->src_y;
2822 intel_state->base.src.x2 = plane_state->src_x + plane_state->src_w;
2823 intel_state->base.src.y2 = plane_state->src_y + plane_state->src_h;
2824 intel_state->base.dst.x1 = plane_state->crtc_x;
2825 intel_state->base.dst.y1 = plane_state->crtc_y;
2826 intel_state->base.dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2827 intel_state->base.dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2828
2829 obj = intel_fb_obj(fb);
2830 if (i915_gem_object_is_tiled(obj))
2831 dev_priv->preserve_bios_swizzle = true;
2832
2833 drm_framebuffer_reference(fb);
2834 primary->fb = primary->state->fb = fb;
2835 primary->crtc = primary->state->crtc = &intel_crtc->base;
2836 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2837 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2838 &obj->frontbuffer_bits);
2839 }
2840
2841 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2842 unsigned int rotation)
2843 {
2844 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2845
2846 switch (fb->modifier[plane]) {
2847 case DRM_FORMAT_MOD_NONE:
2848 case I915_FORMAT_MOD_X_TILED:
2849 switch (cpp) {
2850 case 8:
2851 return 4096;
2852 case 4:
2853 case 2:
2854 case 1:
2855 return 8192;
2856 default:
2857 MISSING_CASE(cpp);
2858 break;
2859 }
2860 break;
2861 case I915_FORMAT_MOD_Y_TILED:
2862 case I915_FORMAT_MOD_Yf_TILED:
2863 switch (cpp) {
2864 case 8:
2865 return 2048;
2866 case 4:
2867 return 4096;
2868 case 2:
2869 case 1:
2870 return 8192;
2871 default:
2872 MISSING_CASE(cpp);
2873 break;
2874 }
2875 break;
2876 default:
2877 MISSING_CASE(fb->modifier[plane]);
2878 }
2879
2880 return 2048;
2881 }
2882
2883 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2884 {
2885 const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2886 const struct drm_framebuffer *fb = plane_state->base.fb;
2887 unsigned int rotation = plane_state->base.rotation;
2888 int x = plane_state->base.src.x1 >> 16;
2889 int y = plane_state->base.src.y1 >> 16;
2890 int w = drm_rect_width(&plane_state->base.src) >> 16;
2891 int h = drm_rect_height(&plane_state->base.src) >> 16;
2892 int max_width = skl_max_plane_width(fb, 0, rotation);
2893 int max_height = 4096;
2894 u32 alignment, offset, aux_offset = plane_state->aux.offset;
2895
2896 if (w > max_width || h > max_height) {
2897 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2898 w, h, max_width, max_height);
2899 return -EINVAL;
2900 }
2901
2902 intel_add_fb_offsets(&x, &y, plane_state, 0);
2903 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2904
2905 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2906
2907 /*
2908 * AUX surface offset is specified as the distance from the
2909 * main surface offset, and it must be non-negative. Make
2910 * sure that is what we will get.
2911 */
2912 if (offset > aux_offset)
2913 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2914 offset, aux_offset & ~(alignment - 1));
2915
2916 /*
2917 * When using an X-tiled surface, the plane blows up
2918 * if the x offset + width exceed the stride.
2919 *
2920 * TODO: linear and Y-tiled seem fine, Yf untested,
2921 */
2922 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) {
2923 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2924
2925 while ((x + w) * cpp > fb->pitches[0]) {
2926 if (offset == 0) {
2927 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2928 return -EINVAL;
2929 }
2930
2931 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2932 offset, offset - alignment);
2933 }
2934 }
2935
2936 plane_state->main.offset = offset;
2937 plane_state->main.x = x;
2938 plane_state->main.y = y;
2939
2940 return 0;
2941 }
2942
2943 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2944 {
2945 const struct drm_framebuffer *fb = plane_state->base.fb;
2946 unsigned int rotation = plane_state->base.rotation;
2947 int max_width = skl_max_plane_width(fb, 1, rotation);
2948 int max_height = 4096;
2949 int x = plane_state->base.src.x1 >> 17;
2950 int y = plane_state->base.src.y1 >> 17;
2951 int w = drm_rect_width(&plane_state->base.src) >> 17;
2952 int h = drm_rect_height(&plane_state->base.src) >> 17;
2953 u32 offset;
2954
2955 intel_add_fb_offsets(&x, &y, plane_state, 1);
2956 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2957
2958 /* FIXME not quite sure how/if these apply to the chroma plane */
2959 if (w > max_width || h > max_height) {
2960 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2961 w, h, max_width, max_height);
2962 return -EINVAL;
2963 }
2964
2965 plane_state->aux.offset = offset;
2966 plane_state->aux.x = x;
2967 plane_state->aux.y = y;
2968
2969 return 0;
2970 }
2971
2972 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2973 {
2974 const struct drm_framebuffer *fb = plane_state->base.fb;
2975 unsigned int rotation = plane_state->base.rotation;
2976 int ret;
2977
2978 /* Rotate src coordinates to match rotated GTT view */
2979 if (intel_rotation_90_or_270(rotation))
2980 drm_rect_rotate(&plane_state->base.src,
2981 fb->width << 16, fb->height << 16,
2982 DRM_ROTATE_270);
2983
2984 /*
2985 * Handle the AUX surface first since
2986 * the main surface setup depends on it.
2987 */
2988 if (fb->pixel_format == DRM_FORMAT_NV12) {
2989 ret = skl_check_nv12_aux_surface(plane_state);
2990 if (ret)
2991 return ret;
2992 } else {
2993 plane_state->aux.offset = ~0xfff;
2994 plane_state->aux.x = 0;
2995 plane_state->aux.y = 0;
2996 }
2997
2998 ret = skl_check_main_surface(plane_state);
2999 if (ret)
3000 return ret;
3001
3002 return 0;
3003 }
3004
3005 static void i9xx_update_primary_plane(struct drm_plane *primary,
3006 const struct intel_crtc_state *crtc_state,
3007 const struct intel_plane_state *plane_state)
3008 {
3009 struct drm_device *dev = primary->dev;
3010 struct drm_i915_private *dev_priv = to_i915(dev);
3011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3012 struct drm_framebuffer *fb = plane_state->base.fb;
3013 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3014 int plane = intel_crtc->plane;
3015 u32 linear_offset;
3016 u32 dspcntr;
3017 i915_reg_t reg = DSPCNTR(plane);
3018 unsigned int rotation = plane_state->base.rotation;
3019 int x = plane_state->base.src.x1 >> 16;
3020 int y = plane_state->base.src.y1 >> 16;
3021
3022 dspcntr = DISPPLANE_GAMMA_ENABLE;
3023
3024 dspcntr |= DISPLAY_PLANE_ENABLE;
3025
3026 if (INTEL_INFO(dev)->gen < 4) {
3027 if (intel_crtc->pipe == PIPE_B)
3028 dspcntr |= DISPPLANE_SEL_PIPE_B;
3029
3030 /* pipesrc and dspsize control the size that is scaled from,
3031 * which should always be the user's requested size.
3032 */
3033 I915_WRITE(DSPSIZE(plane),
3034 ((crtc_state->pipe_src_h - 1) << 16) |
3035 (crtc_state->pipe_src_w - 1));
3036 I915_WRITE(DSPPOS(plane), 0);
3037 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
3038 I915_WRITE(PRIMSIZE(plane),
3039 ((crtc_state->pipe_src_h - 1) << 16) |
3040 (crtc_state->pipe_src_w - 1));
3041 I915_WRITE(PRIMPOS(plane), 0);
3042 I915_WRITE(PRIMCNSTALPHA(plane), 0);
3043 }
3044
3045 switch (fb->pixel_format) {
3046 case DRM_FORMAT_C8:
3047 dspcntr |= DISPPLANE_8BPP;
3048 break;
3049 case DRM_FORMAT_XRGB1555:
3050 dspcntr |= DISPPLANE_BGRX555;
3051 break;
3052 case DRM_FORMAT_RGB565:
3053 dspcntr |= DISPPLANE_BGRX565;
3054 break;
3055 case DRM_FORMAT_XRGB8888:
3056 dspcntr |= DISPPLANE_BGRX888;
3057 break;
3058 case DRM_FORMAT_XBGR8888:
3059 dspcntr |= DISPPLANE_RGBX888;
3060 break;
3061 case DRM_FORMAT_XRGB2101010:
3062 dspcntr |= DISPPLANE_BGRX101010;
3063 break;
3064 case DRM_FORMAT_XBGR2101010:
3065 dspcntr |= DISPPLANE_RGBX101010;
3066 break;
3067 default:
3068 BUG();
3069 }
3070
3071 if (INTEL_GEN(dev_priv) >= 4 &&
3072 fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3073 dspcntr |= DISPPLANE_TILED;
3074
3075 if (IS_G4X(dev))
3076 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3077
3078 intel_add_fb_offsets(&x, &y, plane_state, 0);
3079
3080 if (INTEL_INFO(dev)->gen >= 4)
3081 intel_crtc->dspaddr_offset =
3082 intel_compute_tile_offset(&x, &y, plane_state, 0);
3083
3084 if (rotation == DRM_ROTATE_180) {
3085 dspcntr |= DISPPLANE_ROTATE_180;
3086
3087 x += (crtc_state->pipe_src_w - 1);
3088 y += (crtc_state->pipe_src_h - 1);
3089 }
3090
3091 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3092
3093 if (INTEL_INFO(dev)->gen < 4)
3094 intel_crtc->dspaddr_offset = linear_offset;
3095
3096 intel_crtc->adjusted_x = x;
3097 intel_crtc->adjusted_y = y;
3098
3099 I915_WRITE(reg, dspcntr);
3100
3101 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3102 if (INTEL_INFO(dev)->gen >= 4) {
3103 I915_WRITE(DSPSURF(plane),
3104 intel_fb_gtt_offset(fb, rotation) +
3105 intel_crtc->dspaddr_offset);
3106 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3107 I915_WRITE(DSPLINOFF(plane), linear_offset);
3108 } else
3109 I915_WRITE(DSPADDR(plane), i915_gem_object_ggtt_offset(obj, NULL) + linear_offset);
3110 POSTING_READ(reg);
3111 }
3112
3113 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3114 struct drm_crtc *crtc)
3115 {
3116 struct drm_device *dev = crtc->dev;
3117 struct drm_i915_private *dev_priv = to_i915(dev);
3118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3119 int plane = intel_crtc->plane;
3120
3121 I915_WRITE(DSPCNTR(plane), 0);
3122 if (INTEL_INFO(dev_priv)->gen >= 4)
3123 I915_WRITE(DSPSURF(plane), 0);
3124 else
3125 I915_WRITE(DSPADDR(plane), 0);
3126 POSTING_READ(DSPCNTR(plane));
3127 }
3128
3129 static void ironlake_update_primary_plane(struct drm_plane *primary,
3130 const struct intel_crtc_state *crtc_state,
3131 const struct intel_plane_state *plane_state)
3132 {
3133 struct drm_device *dev = primary->dev;
3134 struct drm_i915_private *dev_priv = to_i915(dev);
3135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3136 struct drm_framebuffer *fb = plane_state->base.fb;
3137 int plane = intel_crtc->plane;
3138 u32 linear_offset;
3139 u32 dspcntr;
3140 i915_reg_t reg = DSPCNTR(plane);
3141 unsigned int rotation = plane_state->base.rotation;
3142 int x = plane_state->base.src.x1 >> 16;
3143 int y = plane_state->base.src.y1 >> 16;
3144
3145 dspcntr = DISPPLANE_GAMMA_ENABLE;
3146 dspcntr |= DISPLAY_PLANE_ENABLE;
3147
3148 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3149 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3150
3151 switch (fb->pixel_format) {
3152 case DRM_FORMAT_C8:
3153 dspcntr |= DISPPLANE_8BPP;
3154 break;
3155 case DRM_FORMAT_RGB565:
3156 dspcntr |= DISPPLANE_BGRX565;
3157 break;
3158 case DRM_FORMAT_XRGB8888:
3159 dspcntr |= DISPPLANE_BGRX888;
3160 break;
3161 case DRM_FORMAT_XBGR8888:
3162 dspcntr |= DISPPLANE_RGBX888;
3163 break;
3164 case DRM_FORMAT_XRGB2101010:
3165 dspcntr |= DISPPLANE_BGRX101010;
3166 break;
3167 case DRM_FORMAT_XBGR2101010:
3168 dspcntr |= DISPPLANE_RGBX101010;
3169 break;
3170 default:
3171 BUG();
3172 }
3173
3174 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3175 dspcntr |= DISPPLANE_TILED;
3176
3177 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
3178 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3179
3180 intel_add_fb_offsets(&x, &y, plane_state, 0);
3181
3182 intel_crtc->dspaddr_offset =
3183 intel_compute_tile_offset(&x, &y, plane_state, 0);
3184
3185 if (rotation == DRM_ROTATE_180) {
3186 dspcntr |= DISPPLANE_ROTATE_180;
3187
3188 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
3189 x += (crtc_state->pipe_src_w - 1);
3190 y += (crtc_state->pipe_src_h - 1);
3191 }
3192 }
3193
3194 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3195
3196 intel_crtc->adjusted_x = x;
3197 intel_crtc->adjusted_y = y;
3198
3199 I915_WRITE(reg, dspcntr);
3200
3201 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3202 I915_WRITE(DSPSURF(plane),
3203 intel_fb_gtt_offset(fb, rotation) +
3204 intel_crtc->dspaddr_offset);
3205 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3206 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3207 } else {
3208 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3209 I915_WRITE(DSPLINOFF(plane), linear_offset);
3210 }
3211 POSTING_READ(reg);
3212 }
3213
3214 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3215 uint64_t fb_modifier, uint32_t pixel_format)
3216 {
3217 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3218 return 64;
3219 } else {
3220 int cpp = drm_format_plane_cpp(pixel_format, 0);
3221
3222 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3223 }
3224 }
3225
3226 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb,
3227 unsigned int rotation)
3228 {
3229 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3230 struct i915_ggtt_view view;
3231 struct i915_vma *vma;
3232
3233 intel_fill_fb_ggtt_view(&view, fb, rotation);
3234
3235 vma = i915_gem_object_to_ggtt(obj, &view);
3236 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
3237 view.type))
3238 return -1;
3239
3240 return i915_ggtt_offset(vma);
3241 }
3242
3243 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3244 {
3245 struct drm_device *dev = intel_crtc->base.dev;
3246 struct drm_i915_private *dev_priv = to_i915(dev);
3247
3248 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3249 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3250 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3251 }
3252
3253 /*
3254 * This function detaches (aka. unbinds) unused scalers in hardware
3255 */
3256 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3257 {
3258 struct intel_crtc_scaler_state *scaler_state;
3259 int i;
3260
3261 scaler_state = &intel_crtc->config->scaler_state;
3262
3263 /* loop through and disable scalers that aren't in use */
3264 for (i = 0; i < intel_crtc->num_scalers; i++) {
3265 if (!scaler_state->scalers[i].in_use)
3266 skl_detach_scaler(intel_crtc, i);
3267 }
3268 }
3269
3270 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3271 unsigned int rotation)
3272 {
3273 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3274 u32 stride = intel_fb_pitch(fb, plane, rotation);
3275
3276 /*
3277 * The stride is either expressed as a multiple of 64 bytes chunks for
3278 * linear buffers or in number of tiles for tiled buffers.
3279 */
3280 if (intel_rotation_90_or_270(rotation)) {
3281 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
3282
3283 stride /= intel_tile_height(dev_priv, fb->modifier[0], cpp);
3284 } else {
3285 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3286 fb->pixel_format);
3287 }
3288
3289 return stride;
3290 }
3291
3292 u32 skl_plane_ctl_format(uint32_t pixel_format)
3293 {
3294 switch (pixel_format) {
3295 case DRM_FORMAT_C8:
3296 return PLANE_CTL_FORMAT_INDEXED;
3297 case DRM_FORMAT_RGB565:
3298 return PLANE_CTL_FORMAT_RGB_565;
3299 case DRM_FORMAT_XBGR8888:
3300 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3301 case DRM_FORMAT_XRGB8888:
3302 return PLANE_CTL_FORMAT_XRGB_8888;
3303 /*
3304 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3305 * to be already pre-multiplied. We need to add a knob (or a different
3306 * DRM_FORMAT) for user-space to configure that.
3307 */
3308 case DRM_FORMAT_ABGR8888:
3309 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3310 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3311 case DRM_FORMAT_ARGB8888:
3312 return PLANE_CTL_FORMAT_XRGB_8888 |
3313 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3314 case DRM_FORMAT_XRGB2101010:
3315 return PLANE_CTL_FORMAT_XRGB_2101010;
3316 case DRM_FORMAT_XBGR2101010:
3317 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3318 case DRM_FORMAT_YUYV:
3319 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3320 case DRM_FORMAT_YVYU:
3321 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3322 case DRM_FORMAT_UYVY:
3323 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3324 case DRM_FORMAT_VYUY:
3325 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3326 default:
3327 MISSING_CASE(pixel_format);
3328 }
3329
3330 return 0;
3331 }
3332
3333 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3334 {
3335 switch (fb_modifier) {
3336 case DRM_FORMAT_MOD_NONE:
3337 break;
3338 case I915_FORMAT_MOD_X_TILED:
3339 return PLANE_CTL_TILED_X;
3340 case I915_FORMAT_MOD_Y_TILED:
3341 return PLANE_CTL_TILED_Y;
3342 case I915_FORMAT_MOD_Yf_TILED:
3343 return PLANE_CTL_TILED_YF;
3344 default:
3345 MISSING_CASE(fb_modifier);
3346 }
3347
3348 return 0;
3349 }
3350
3351 u32 skl_plane_ctl_rotation(unsigned int rotation)
3352 {
3353 switch (rotation) {
3354 case DRM_ROTATE_0:
3355 break;
3356 /*
3357 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3358 * while i915 HW rotation is clockwise, thats why this swapping.
3359 */
3360 case DRM_ROTATE_90:
3361 return PLANE_CTL_ROTATE_270;
3362 case DRM_ROTATE_180:
3363 return PLANE_CTL_ROTATE_180;
3364 case DRM_ROTATE_270:
3365 return PLANE_CTL_ROTATE_90;
3366 default:
3367 MISSING_CASE(rotation);
3368 }
3369
3370 return 0;
3371 }
3372
3373 static void skylake_update_primary_plane(struct drm_plane *plane,
3374 const struct intel_crtc_state *crtc_state,
3375 const struct intel_plane_state *plane_state)
3376 {
3377 struct drm_device *dev = plane->dev;
3378 struct drm_i915_private *dev_priv = to_i915(dev);
3379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3380 struct drm_framebuffer *fb = plane_state->base.fb;
3381 const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
3382 int pipe = intel_crtc->pipe;
3383 u32 plane_ctl;
3384 unsigned int rotation = plane_state->base.rotation;
3385 u32 stride = skl_plane_stride(fb, 0, rotation);
3386 u32 surf_addr = plane_state->main.offset;
3387 int scaler_id = plane_state->scaler_id;
3388 int src_x = plane_state->main.x;
3389 int src_y = plane_state->main.y;
3390 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3391 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3392 int dst_x = plane_state->base.dst.x1;
3393 int dst_y = plane_state->base.dst.y1;
3394 int dst_w = drm_rect_width(&plane_state->base.dst);
3395 int dst_h = drm_rect_height(&plane_state->base.dst);
3396
3397 plane_ctl = PLANE_CTL_ENABLE |
3398 PLANE_CTL_PIPE_GAMMA_ENABLE |
3399 PLANE_CTL_PIPE_CSC_ENABLE;
3400
3401 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3402 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3403 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3404 plane_ctl |= skl_plane_ctl_rotation(rotation);
3405
3406 /* Sizes are 0 based */
3407 src_w--;
3408 src_h--;
3409 dst_w--;
3410 dst_h--;
3411
3412 intel_crtc->dspaddr_offset = surf_addr;
3413
3414 intel_crtc->adjusted_x = src_x;
3415 intel_crtc->adjusted_y = src_y;
3416
3417 if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base))
3418 skl_write_plane_wm(intel_crtc, wm, 0);
3419
3420 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3421 I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
3422 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3423 I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w);
3424
3425 if (scaler_id >= 0) {
3426 uint32_t ps_ctrl = 0;
3427
3428 WARN_ON(!dst_w || !dst_h);
3429 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3430 crtc_state->scaler_state.scalers[scaler_id].mode;
3431 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3432 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3433 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3434 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3435 I915_WRITE(PLANE_POS(pipe, 0), 0);
3436 } else {
3437 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3438 }
3439
3440 I915_WRITE(PLANE_SURF(pipe, 0),
3441 intel_fb_gtt_offset(fb, rotation) + surf_addr);
3442
3443 POSTING_READ(PLANE_SURF(pipe, 0));
3444 }
3445
3446 static void skylake_disable_primary_plane(struct drm_plane *primary,
3447 struct drm_crtc *crtc)
3448 {
3449 struct drm_device *dev = crtc->dev;
3450 struct drm_i915_private *dev_priv = to_i915(dev);
3451 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3452 int pipe = intel_crtc->pipe;
3453
3454 /*
3455 * We only populate skl_results on watermark updates, and if the
3456 * plane's visiblity isn't actually changing neither is its watermarks.
3457 */
3458 if (!crtc->primary->state->visible)
3459 skl_write_plane_wm(intel_crtc, &dev_priv->wm.skl_results, 0);
3460
3461 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3462 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3463 POSTING_READ(PLANE_SURF(pipe, 0));
3464 }
3465
3466 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3467 static int
3468 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3469 int x, int y, enum mode_set_atomic state)
3470 {
3471 /* Support for kgdboc is disabled, this needs a major rework. */
3472 DRM_ERROR("legacy panic handler not supported any more.\n");
3473
3474 return -ENODEV;
3475 }
3476
3477 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3478 {
3479 struct intel_crtc *crtc;
3480
3481 for_each_intel_crtc(&dev_priv->drm, crtc)
3482 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3483 }
3484
3485 static void intel_update_primary_planes(struct drm_device *dev)
3486 {
3487 struct drm_crtc *crtc;
3488
3489 for_each_crtc(dev, crtc) {
3490 struct intel_plane *plane = to_intel_plane(crtc->primary);
3491 struct intel_plane_state *plane_state =
3492 to_intel_plane_state(plane->base.state);
3493
3494 if (plane_state->base.visible)
3495 plane->update_plane(&plane->base,
3496 to_intel_crtc_state(crtc->state),
3497 plane_state);
3498 }
3499 }
3500
3501 static int
3502 __intel_display_resume(struct drm_device *dev,
3503 struct drm_atomic_state *state)
3504 {
3505 struct drm_crtc_state *crtc_state;
3506 struct drm_crtc *crtc;
3507 int i, ret;
3508
3509 intel_modeset_setup_hw_state(dev);
3510 i915_redisable_vga(dev);
3511
3512 if (!state)
3513 return 0;
3514
3515 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3516 /*
3517 * Force recalculation even if we restore
3518 * current state. With fast modeset this may not result
3519 * in a modeset when the state is compatible.
3520 */
3521 crtc_state->mode_changed = true;
3522 }
3523
3524 /* ignore any reset values/BIOS leftovers in the WM registers */
3525 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3526
3527 ret = drm_atomic_commit(state);
3528
3529 WARN_ON(ret == -EDEADLK);
3530 return ret;
3531 }
3532
3533 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3534 {
3535 return intel_has_gpu_reset(dev_priv) &&
3536 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3537 }
3538
3539 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3540 {
3541 struct drm_device *dev = &dev_priv->drm;
3542 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3543 struct drm_atomic_state *state;
3544 int ret;
3545
3546 /*
3547 * Need mode_config.mutex so that we don't
3548 * trample ongoing ->detect() and whatnot.
3549 */
3550 mutex_lock(&dev->mode_config.mutex);
3551 drm_modeset_acquire_init(ctx, 0);
3552 while (1) {
3553 ret = drm_modeset_lock_all_ctx(dev, ctx);
3554 if (ret != -EDEADLK)
3555 break;
3556
3557 drm_modeset_backoff(ctx);
3558 }
3559
3560 /* reset doesn't touch the display, but flips might get nuked anyway, */
3561 if (!i915.force_reset_modeset_test &&
3562 !gpu_reset_clobbers_display(dev_priv))
3563 return;
3564
3565 /*
3566 * Disabling the crtcs gracefully seems nicer. Also the
3567 * g33 docs say we should at least disable all the planes.
3568 */
3569 state = drm_atomic_helper_duplicate_state(dev, ctx);
3570 if (IS_ERR(state)) {
3571 ret = PTR_ERR(state);
3572 state = NULL;
3573 DRM_ERROR("Duplicating state failed with %i\n", ret);
3574 goto err;
3575 }
3576
3577 ret = drm_atomic_helper_disable_all(dev, ctx);
3578 if (ret) {
3579 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3580 goto err;
3581 }
3582
3583 dev_priv->modeset_restore_state = state;
3584 state->acquire_ctx = ctx;
3585 return;
3586
3587 err:
3588 drm_atomic_state_free(state);
3589 }
3590
3591 void intel_finish_reset(struct drm_i915_private *dev_priv)
3592 {
3593 struct drm_device *dev = &dev_priv->drm;
3594 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3595 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3596 int ret;
3597
3598 /*
3599 * Flips in the rings will be nuked by the reset,
3600 * so complete all pending flips so that user space
3601 * will get its events and not get stuck.
3602 */
3603 intel_complete_page_flips(dev_priv);
3604
3605 dev_priv->modeset_restore_state = NULL;
3606
3607 dev_priv->modeset_restore_state = NULL;
3608
3609 /* reset doesn't touch the display */
3610 if (!gpu_reset_clobbers_display(dev_priv)) {
3611 if (!state) {
3612 /*
3613 * Flips in the rings have been nuked by the reset,
3614 * so update the base address of all primary
3615 * planes to the the last fb to make sure we're
3616 * showing the correct fb after a reset.
3617 *
3618 * FIXME: Atomic will make this obsolete since we won't schedule
3619 * CS-based flips (which might get lost in gpu resets) any more.
3620 */
3621 intel_update_primary_planes(dev);
3622 } else {
3623 ret = __intel_display_resume(dev, state);
3624 if (ret)
3625 DRM_ERROR("Restoring old state failed with %i\n", ret);
3626 }
3627 } else {
3628 /*
3629 * The display has been reset as well,
3630 * so need a full re-initialization.
3631 */
3632 intel_runtime_pm_disable_interrupts(dev_priv);
3633 intel_runtime_pm_enable_interrupts(dev_priv);
3634
3635 intel_pps_unlock_regs_wa(dev_priv);
3636 intel_modeset_init_hw(dev);
3637
3638 spin_lock_irq(&dev_priv->irq_lock);
3639 if (dev_priv->display.hpd_irq_setup)
3640 dev_priv->display.hpd_irq_setup(dev_priv);
3641 spin_unlock_irq(&dev_priv->irq_lock);
3642
3643 ret = __intel_display_resume(dev, state);
3644 if (ret)
3645 DRM_ERROR("Restoring old state failed with %i\n", ret);
3646
3647 intel_hpd_init(dev_priv);
3648 }
3649
3650 drm_modeset_drop_locks(ctx);
3651 drm_modeset_acquire_fini(ctx);
3652 mutex_unlock(&dev->mode_config.mutex);
3653 }
3654
3655 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3656 {
3657 struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3658
3659 if (i915_reset_in_progress(error))
3660 return true;
3661
3662 if (crtc->reset_count != i915_reset_count(error))
3663 return true;
3664
3665 return false;
3666 }
3667
3668 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3669 {
3670 struct drm_device *dev = crtc->dev;
3671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3672 bool pending;
3673
3674 if (abort_flip_on_reset(intel_crtc))
3675 return false;
3676
3677 spin_lock_irq(&dev->event_lock);
3678 pending = to_intel_crtc(crtc)->flip_work != NULL;
3679 spin_unlock_irq(&dev->event_lock);
3680
3681 return pending;
3682 }
3683
3684 static void intel_update_pipe_config(struct intel_crtc *crtc,
3685 struct intel_crtc_state *old_crtc_state)
3686 {
3687 struct drm_device *dev = crtc->base.dev;
3688 struct drm_i915_private *dev_priv = to_i915(dev);
3689 struct intel_crtc_state *pipe_config =
3690 to_intel_crtc_state(crtc->base.state);
3691
3692 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3693 crtc->base.mode = crtc->base.state->mode;
3694
3695 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3696 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3697 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3698
3699 /*
3700 * Update pipe size and adjust fitter if needed: the reason for this is
3701 * that in compute_mode_changes we check the native mode (not the pfit
3702 * mode) to see if we can flip rather than do a full mode set. In the
3703 * fastboot case, we'll flip, but if we don't update the pipesrc and
3704 * pfit state, we'll end up with a big fb scanned out into the wrong
3705 * sized surface.
3706 */
3707
3708 I915_WRITE(PIPESRC(crtc->pipe),
3709 ((pipe_config->pipe_src_w - 1) << 16) |
3710 (pipe_config->pipe_src_h - 1));
3711
3712 /* on skylake this is done by detaching scalers */
3713 if (INTEL_INFO(dev)->gen >= 9) {
3714 skl_detach_scalers(crtc);
3715
3716 if (pipe_config->pch_pfit.enabled)
3717 skylake_pfit_enable(crtc);
3718 } else if (HAS_PCH_SPLIT(dev)) {
3719 if (pipe_config->pch_pfit.enabled)
3720 ironlake_pfit_enable(crtc);
3721 else if (old_crtc_state->pch_pfit.enabled)
3722 ironlake_pfit_disable(crtc, true);
3723 }
3724 }
3725
3726 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3727 {
3728 struct drm_device *dev = crtc->dev;
3729 struct drm_i915_private *dev_priv = to_i915(dev);
3730 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3731 int pipe = intel_crtc->pipe;
3732 i915_reg_t reg;
3733 u32 temp;
3734
3735 /* enable normal train */
3736 reg = FDI_TX_CTL(pipe);
3737 temp = I915_READ(reg);
3738 if (IS_IVYBRIDGE(dev)) {
3739 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3740 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3741 } else {
3742 temp &= ~FDI_LINK_TRAIN_NONE;
3743 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3744 }
3745 I915_WRITE(reg, temp);
3746
3747 reg = FDI_RX_CTL(pipe);
3748 temp = I915_READ(reg);
3749 if (HAS_PCH_CPT(dev)) {
3750 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3751 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3752 } else {
3753 temp &= ~FDI_LINK_TRAIN_NONE;
3754 temp |= FDI_LINK_TRAIN_NONE;
3755 }
3756 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3757
3758 /* wait one idle pattern time */
3759 POSTING_READ(reg);
3760 udelay(1000);
3761
3762 /* IVB wants error correction enabled */
3763 if (IS_IVYBRIDGE(dev))
3764 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3765 FDI_FE_ERRC_ENABLE);
3766 }
3767
3768 /* The FDI link training functions for ILK/Ibexpeak. */
3769 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3770 {
3771 struct drm_device *dev = crtc->dev;
3772 struct drm_i915_private *dev_priv = to_i915(dev);
3773 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3774 int pipe = intel_crtc->pipe;
3775 i915_reg_t reg;
3776 u32 temp, tries;
3777
3778 /* FDI needs bits from pipe first */
3779 assert_pipe_enabled(dev_priv, pipe);
3780
3781 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3782 for train result */
3783 reg = FDI_RX_IMR(pipe);
3784 temp = I915_READ(reg);
3785 temp &= ~FDI_RX_SYMBOL_LOCK;
3786 temp &= ~FDI_RX_BIT_LOCK;
3787 I915_WRITE(reg, temp);
3788 I915_READ(reg);
3789 udelay(150);
3790
3791 /* enable CPU FDI TX and PCH FDI RX */
3792 reg = FDI_TX_CTL(pipe);
3793 temp = I915_READ(reg);
3794 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3795 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3796 temp &= ~FDI_LINK_TRAIN_NONE;
3797 temp |= FDI_LINK_TRAIN_PATTERN_1;
3798 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3799
3800 reg = FDI_RX_CTL(pipe);
3801 temp = I915_READ(reg);
3802 temp &= ~FDI_LINK_TRAIN_NONE;
3803 temp |= FDI_LINK_TRAIN_PATTERN_1;
3804 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3805
3806 POSTING_READ(reg);
3807 udelay(150);
3808
3809 /* Ironlake workaround, enable clock pointer after FDI enable*/
3810 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3811 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3812 FDI_RX_PHASE_SYNC_POINTER_EN);
3813
3814 reg = FDI_RX_IIR(pipe);
3815 for (tries = 0; tries < 5; tries++) {
3816 temp = I915_READ(reg);
3817 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3818
3819 if ((temp & FDI_RX_BIT_LOCK)) {
3820 DRM_DEBUG_KMS("FDI train 1 done.\n");
3821 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3822 break;
3823 }
3824 }
3825 if (tries == 5)
3826 DRM_ERROR("FDI train 1 fail!\n");
3827
3828 /* Train 2 */
3829 reg = FDI_TX_CTL(pipe);
3830 temp = I915_READ(reg);
3831 temp &= ~FDI_LINK_TRAIN_NONE;
3832 temp |= FDI_LINK_TRAIN_PATTERN_2;
3833 I915_WRITE(reg, temp);
3834
3835 reg = FDI_RX_CTL(pipe);
3836 temp = I915_READ(reg);
3837 temp &= ~FDI_LINK_TRAIN_NONE;
3838 temp |= FDI_LINK_TRAIN_PATTERN_2;
3839 I915_WRITE(reg, temp);
3840
3841 POSTING_READ(reg);
3842 udelay(150);
3843
3844 reg = FDI_RX_IIR(pipe);
3845 for (tries = 0; tries < 5; tries++) {
3846 temp = I915_READ(reg);
3847 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3848
3849 if (temp & FDI_RX_SYMBOL_LOCK) {
3850 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3851 DRM_DEBUG_KMS("FDI train 2 done.\n");
3852 break;
3853 }
3854 }
3855 if (tries == 5)
3856 DRM_ERROR("FDI train 2 fail!\n");
3857
3858 DRM_DEBUG_KMS("FDI train done\n");
3859
3860 }
3861
3862 static const int snb_b_fdi_train_param[] = {
3863 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3864 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3865 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3866 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3867 };
3868
3869 /* The FDI link training functions for SNB/Cougarpoint. */
3870 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3871 {
3872 struct drm_device *dev = crtc->dev;
3873 struct drm_i915_private *dev_priv = to_i915(dev);
3874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3875 int pipe = intel_crtc->pipe;
3876 i915_reg_t reg;
3877 u32 temp, i, retry;
3878
3879 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3880 for train result */
3881 reg = FDI_RX_IMR(pipe);
3882 temp = I915_READ(reg);
3883 temp &= ~FDI_RX_SYMBOL_LOCK;
3884 temp &= ~FDI_RX_BIT_LOCK;
3885 I915_WRITE(reg, temp);
3886
3887 POSTING_READ(reg);
3888 udelay(150);
3889
3890 /* enable CPU FDI TX and PCH FDI RX */
3891 reg = FDI_TX_CTL(pipe);
3892 temp = I915_READ(reg);
3893 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3894 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3895 temp &= ~FDI_LINK_TRAIN_NONE;
3896 temp |= FDI_LINK_TRAIN_PATTERN_1;
3897 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3898 /* SNB-B */
3899 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3900 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3901
3902 I915_WRITE(FDI_RX_MISC(pipe),
3903 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3904
3905 reg = FDI_RX_CTL(pipe);
3906 temp = I915_READ(reg);
3907 if (HAS_PCH_CPT(dev)) {
3908 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3909 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3910 } else {
3911 temp &= ~FDI_LINK_TRAIN_NONE;
3912 temp |= FDI_LINK_TRAIN_PATTERN_1;
3913 }
3914 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3915
3916 POSTING_READ(reg);
3917 udelay(150);
3918
3919 for (i = 0; i < 4; i++) {
3920 reg = FDI_TX_CTL(pipe);
3921 temp = I915_READ(reg);
3922 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3923 temp |= snb_b_fdi_train_param[i];
3924 I915_WRITE(reg, temp);
3925
3926 POSTING_READ(reg);
3927 udelay(500);
3928
3929 for (retry = 0; retry < 5; retry++) {
3930 reg = FDI_RX_IIR(pipe);
3931 temp = I915_READ(reg);
3932 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3933 if (temp & FDI_RX_BIT_LOCK) {
3934 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3935 DRM_DEBUG_KMS("FDI train 1 done.\n");
3936 break;
3937 }
3938 udelay(50);
3939 }
3940 if (retry < 5)
3941 break;
3942 }
3943 if (i == 4)
3944 DRM_ERROR("FDI train 1 fail!\n");
3945
3946 /* Train 2 */
3947 reg = FDI_TX_CTL(pipe);
3948 temp = I915_READ(reg);
3949 temp &= ~FDI_LINK_TRAIN_NONE;
3950 temp |= FDI_LINK_TRAIN_PATTERN_2;
3951 if (IS_GEN6(dev)) {
3952 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3953 /* SNB-B */
3954 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3955 }
3956 I915_WRITE(reg, temp);
3957
3958 reg = FDI_RX_CTL(pipe);
3959 temp = I915_READ(reg);
3960 if (HAS_PCH_CPT(dev)) {
3961 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3962 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3963 } else {
3964 temp &= ~FDI_LINK_TRAIN_NONE;
3965 temp |= FDI_LINK_TRAIN_PATTERN_2;
3966 }
3967 I915_WRITE(reg, temp);
3968
3969 POSTING_READ(reg);
3970 udelay(150);
3971
3972 for (i = 0; i < 4; i++) {
3973 reg = FDI_TX_CTL(pipe);
3974 temp = I915_READ(reg);
3975 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3976 temp |= snb_b_fdi_train_param[i];
3977 I915_WRITE(reg, temp);
3978
3979 POSTING_READ(reg);
3980 udelay(500);
3981
3982 for (retry = 0; retry < 5; retry++) {
3983 reg = FDI_RX_IIR(pipe);
3984 temp = I915_READ(reg);
3985 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3986 if (temp & FDI_RX_SYMBOL_LOCK) {
3987 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3988 DRM_DEBUG_KMS("FDI train 2 done.\n");
3989 break;
3990 }
3991 udelay(50);
3992 }
3993 if (retry < 5)
3994 break;
3995 }
3996 if (i == 4)
3997 DRM_ERROR("FDI train 2 fail!\n");
3998
3999 DRM_DEBUG_KMS("FDI train done.\n");
4000 }
4001
4002 /* Manual link training for Ivy Bridge A0 parts */
4003 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
4004 {
4005 struct drm_device *dev = crtc->dev;
4006 struct drm_i915_private *dev_priv = to_i915(dev);
4007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4008 int pipe = intel_crtc->pipe;
4009 i915_reg_t reg;
4010 u32 temp, i, j;
4011
4012 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4013 for train result */
4014 reg = FDI_RX_IMR(pipe);
4015 temp = I915_READ(reg);
4016 temp &= ~FDI_RX_SYMBOL_LOCK;
4017 temp &= ~FDI_RX_BIT_LOCK;
4018 I915_WRITE(reg, temp);
4019
4020 POSTING_READ(reg);
4021 udelay(150);
4022
4023 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4024 I915_READ(FDI_RX_IIR(pipe)));
4025
4026 /* Try each vswing and preemphasis setting twice before moving on */
4027 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4028 /* disable first in case we need to retry */
4029 reg = FDI_TX_CTL(pipe);
4030 temp = I915_READ(reg);
4031 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4032 temp &= ~FDI_TX_ENABLE;
4033 I915_WRITE(reg, temp);
4034
4035 reg = FDI_RX_CTL(pipe);
4036 temp = I915_READ(reg);
4037 temp &= ~FDI_LINK_TRAIN_AUTO;
4038 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4039 temp &= ~FDI_RX_ENABLE;
4040 I915_WRITE(reg, temp);
4041
4042 /* enable CPU FDI TX and PCH FDI RX */
4043 reg = FDI_TX_CTL(pipe);
4044 temp = I915_READ(reg);
4045 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4046 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4047 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4048 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4049 temp |= snb_b_fdi_train_param[j/2];
4050 temp |= FDI_COMPOSITE_SYNC;
4051 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4052
4053 I915_WRITE(FDI_RX_MISC(pipe),
4054 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4055
4056 reg = FDI_RX_CTL(pipe);
4057 temp = I915_READ(reg);
4058 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4059 temp |= FDI_COMPOSITE_SYNC;
4060 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4061
4062 POSTING_READ(reg);
4063 udelay(1); /* should be 0.5us */
4064
4065 for (i = 0; i < 4; i++) {
4066 reg = FDI_RX_IIR(pipe);
4067 temp = I915_READ(reg);
4068 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4069
4070 if (temp & FDI_RX_BIT_LOCK ||
4071 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4072 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4073 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4074 i);
4075 break;
4076 }
4077 udelay(1); /* should be 0.5us */
4078 }
4079 if (i == 4) {
4080 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4081 continue;
4082 }
4083
4084 /* Train 2 */
4085 reg = FDI_TX_CTL(pipe);
4086 temp = I915_READ(reg);
4087 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4088 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4089 I915_WRITE(reg, temp);
4090
4091 reg = FDI_RX_CTL(pipe);
4092 temp = I915_READ(reg);
4093 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4094 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4095 I915_WRITE(reg, temp);
4096
4097 POSTING_READ(reg);
4098 udelay(2); /* should be 1.5us */
4099
4100 for (i = 0; i < 4; i++) {
4101 reg = FDI_RX_IIR(pipe);
4102 temp = I915_READ(reg);
4103 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4104
4105 if (temp & FDI_RX_SYMBOL_LOCK ||
4106 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4107 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4108 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4109 i);
4110 goto train_done;
4111 }
4112 udelay(2); /* should be 1.5us */
4113 }
4114 if (i == 4)
4115 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4116 }
4117
4118 train_done:
4119 DRM_DEBUG_KMS("FDI train done.\n");
4120 }
4121
4122 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4123 {
4124 struct drm_device *dev = intel_crtc->base.dev;
4125 struct drm_i915_private *dev_priv = to_i915(dev);
4126 int pipe = intel_crtc->pipe;
4127 i915_reg_t reg;
4128 u32 temp;
4129
4130 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4131 reg = FDI_RX_CTL(pipe);
4132 temp = I915_READ(reg);
4133 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4134 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4135 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4136 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4137
4138 POSTING_READ(reg);
4139 udelay(200);
4140
4141 /* Switch from Rawclk to PCDclk */
4142 temp = I915_READ(reg);
4143 I915_WRITE(reg, temp | FDI_PCDCLK);
4144
4145 POSTING_READ(reg);
4146 udelay(200);
4147
4148 /* Enable CPU FDI TX PLL, always on for Ironlake */
4149 reg = FDI_TX_CTL(pipe);
4150 temp = I915_READ(reg);
4151 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4152 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4153
4154 POSTING_READ(reg);
4155 udelay(100);
4156 }
4157 }
4158
4159 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4160 {
4161 struct drm_device *dev = intel_crtc->base.dev;
4162 struct drm_i915_private *dev_priv = to_i915(dev);
4163 int pipe = intel_crtc->pipe;
4164 i915_reg_t reg;
4165 u32 temp;
4166
4167 /* Switch from PCDclk to Rawclk */
4168 reg = FDI_RX_CTL(pipe);
4169 temp = I915_READ(reg);
4170 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4171
4172 /* Disable CPU FDI TX PLL */
4173 reg = FDI_TX_CTL(pipe);
4174 temp = I915_READ(reg);
4175 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4176
4177 POSTING_READ(reg);
4178 udelay(100);
4179
4180 reg = FDI_RX_CTL(pipe);
4181 temp = I915_READ(reg);
4182 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4183
4184 /* Wait for the clocks to turn off. */
4185 POSTING_READ(reg);
4186 udelay(100);
4187 }
4188
4189 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4190 {
4191 struct drm_device *dev = crtc->dev;
4192 struct drm_i915_private *dev_priv = to_i915(dev);
4193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4194 int pipe = intel_crtc->pipe;
4195 i915_reg_t reg;
4196 u32 temp;
4197
4198 /* disable CPU FDI tx and PCH FDI rx */
4199 reg = FDI_TX_CTL(pipe);
4200 temp = I915_READ(reg);
4201 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4202 POSTING_READ(reg);
4203
4204 reg = FDI_RX_CTL(pipe);
4205 temp = I915_READ(reg);
4206 temp &= ~(0x7 << 16);
4207 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4208 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4209
4210 POSTING_READ(reg);
4211 udelay(100);
4212
4213 /* Ironlake workaround, disable clock pointer after downing FDI */
4214 if (HAS_PCH_IBX(dev))
4215 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4216
4217 /* still set train pattern 1 */
4218 reg = FDI_TX_CTL(pipe);
4219 temp = I915_READ(reg);
4220 temp &= ~FDI_LINK_TRAIN_NONE;
4221 temp |= FDI_LINK_TRAIN_PATTERN_1;
4222 I915_WRITE(reg, temp);
4223
4224 reg = FDI_RX_CTL(pipe);
4225 temp = I915_READ(reg);
4226 if (HAS_PCH_CPT(dev)) {
4227 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4228 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4229 } else {
4230 temp &= ~FDI_LINK_TRAIN_NONE;
4231 temp |= FDI_LINK_TRAIN_PATTERN_1;
4232 }
4233 /* BPC in FDI rx is consistent with that in PIPECONF */
4234 temp &= ~(0x07 << 16);
4235 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4236 I915_WRITE(reg, temp);
4237
4238 POSTING_READ(reg);
4239 udelay(100);
4240 }
4241
4242 bool intel_has_pending_fb_unpin(struct drm_device *dev)
4243 {
4244 struct intel_crtc *crtc;
4245
4246 /* Note that we don't need to be called with mode_config.lock here
4247 * as our list of CRTC objects is static for the lifetime of the
4248 * device and so cannot disappear as we iterate. Similarly, we can
4249 * happily treat the predicates as racy, atomic checks as userspace
4250 * cannot claim and pin a new fb without at least acquring the
4251 * struct_mutex and so serialising with us.
4252 */
4253 for_each_intel_crtc(dev, crtc) {
4254 if (atomic_read(&crtc->unpin_work_count) == 0)
4255 continue;
4256
4257 if (crtc->flip_work)
4258 intel_wait_for_vblank(dev, crtc->pipe);
4259
4260 return true;
4261 }
4262
4263 return false;
4264 }
4265
4266 static void page_flip_completed(struct intel_crtc *intel_crtc)
4267 {
4268 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4269 struct intel_flip_work *work = intel_crtc->flip_work;
4270
4271 intel_crtc->flip_work = NULL;
4272
4273 if (work->event)
4274 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4275
4276 drm_crtc_vblank_put(&intel_crtc->base);
4277
4278 wake_up_all(&dev_priv->pending_flip_queue);
4279 queue_work(dev_priv->wq, &work->unpin_work);
4280
4281 trace_i915_flip_complete(intel_crtc->plane,
4282 work->pending_flip_obj);
4283 }
4284
4285 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4286 {
4287 struct drm_device *dev = crtc->dev;
4288 struct drm_i915_private *dev_priv = to_i915(dev);
4289 long ret;
4290
4291 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4292
4293 ret = wait_event_interruptible_timeout(
4294 dev_priv->pending_flip_queue,
4295 !intel_crtc_has_pending_flip(crtc),
4296 60*HZ);
4297
4298 if (ret < 0)
4299 return ret;
4300
4301 if (ret == 0) {
4302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4303 struct intel_flip_work *work;
4304
4305 spin_lock_irq(&dev->event_lock);
4306 work = intel_crtc->flip_work;
4307 if (work && !is_mmio_work(work)) {
4308 WARN_ONCE(1, "Removing stuck page flip\n");
4309 page_flip_completed(intel_crtc);
4310 }
4311 spin_unlock_irq(&dev->event_lock);
4312 }
4313
4314 return 0;
4315 }
4316
4317 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4318 {
4319 u32 temp;
4320
4321 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4322
4323 mutex_lock(&dev_priv->sb_lock);
4324
4325 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4326 temp |= SBI_SSCCTL_DISABLE;
4327 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4328
4329 mutex_unlock(&dev_priv->sb_lock);
4330 }
4331
4332 /* Program iCLKIP clock to the desired frequency */
4333 static void lpt_program_iclkip(struct drm_crtc *crtc)
4334 {
4335 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4336 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
4337 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4338 u32 temp;
4339
4340 lpt_disable_iclkip(dev_priv);
4341
4342 /* The iCLK virtual clock root frequency is in MHz,
4343 * but the adjusted_mode->crtc_clock in in KHz. To get the
4344 * divisors, it is necessary to divide one by another, so we
4345 * convert the virtual clock precision to KHz here for higher
4346 * precision.
4347 */
4348 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4349 u32 iclk_virtual_root_freq = 172800 * 1000;
4350 u32 iclk_pi_range = 64;
4351 u32 desired_divisor;
4352
4353 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4354 clock << auxdiv);
4355 divsel = (desired_divisor / iclk_pi_range) - 2;
4356 phaseinc = desired_divisor % iclk_pi_range;
4357
4358 /*
4359 * Near 20MHz is a corner case which is
4360 * out of range for the 7-bit divisor
4361 */
4362 if (divsel <= 0x7f)
4363 break;
4364 }
4365
4366 /* This should not happen with any sane values */
4367 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4368 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4369 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4370 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4371
4372 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4373 clock,
4374 auxdiv,
4375 divsel,
4376 phasedir,
4377 phaseinc);
4378
4379 mutex_lock(&dev_priv->sb_lock);
4380
4381 /* Program SSCDIVINTPHASE6 */
4382 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4383 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4384 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4385 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4386 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4387 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4388 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4389 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4390
4391 /* Program SSCAUXDIV */
4392 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4393 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4394 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4395 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4396
4397 /* Enable modulator and associated divider */
4398 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4399 temp &= ~SBI_SSCCTL_DISABLE;
4400 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4401
4402 mutex_unlock(&dev_priv->sb_lock);
4403
4404 /* Wait for initialization time */
4405 udelay(24);
4406
4407 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4408 }
4409
4410 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4411 {
4412 u32 divsel, phaseinc, auxdiv;
4413 u32 iclk_virtual_root_freq = 172800 * 1000;
4414 u32 iclk_pi_range = 64;
4415 u32 desired_divisor;
4416 u32 temp;
4417
4418 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4419 return 0;
4420
4421 mutex_lock(&dev_priv->sb_lock);
4422
4423 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4424 if (temp & SBI_SSCCTL_DISABLE) {
4425 mutex_unlock(&dev_priv->sb_lock);
4426 return 0;
4427 }
4428
4429 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4430 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4431 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4432 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4433 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4434
4435 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4436 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4437 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4438
4439 mutex_unlock(&dev_priv->sb_lock);
4440
4441 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4442
4443 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4444 desired_divisor << auxdiv);
4445 }
4446
4447 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4448 enum pipe pch_transcoder)
4449 {
4450 struct drm_device *dev = crtc->base.dev;
4451 struct drm_i915_private *dev_priv = to_i915(dev);
4452 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4453
4454 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4455 I915_READ(HTOTAL(cpu_transcoder)));
4456 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4457 I915_READ(HBLANK(cpu_transcoder)));
4458 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4459 I915_READ(HSYNC(cpu_transcoder)));
4460
4461 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4462 I915_READ(VTOTAL(cpu_transcoder)));
4463 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4464 I915_READ(VBLANK(cpu_transcoder)));
4465 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4466 I915_READ(VSYNC(cpu_transcoder)));
4467 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4468 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4469 }
4470
4471 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4472 {
4473 struct drm_i915_private *dev_priv = to_i915(dev);
4474 uint32_t temp;
4475
4476 temp = I915_READ(SOUTH_CHICKEN1);
4477 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4478 return;
4479
4480 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4481 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4482
4483 temp &= ~FDI_BC_BIFURCATION_SELECT;
4484 if (enable)
4485 temp |= FDI_BC_BIFURCATION_SELECT;
4486
4487 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4488 I915_WRITE(SOUTH_CHICKEN1, temp);
4489 POSTING_READ(SOUTH_CHICKEN1);
4490 }
4491
4492 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4493 {
4494 struct drm_device *dev = intel_crtc->base.dev;
4495
4496 switch (intel_crtc->pipe) {
4497 case PIPE_A:
4498 break;
4499 case PIPE_B:
4500 if (intel_crtc->config->fdi_lanes > 2)
4501 cpt_set_fdi_bc_bifurcation(dev, false);
4502 else
4503 cpt_set_fdi_bc_bifurcation(dev, true);
4504
4505 break;
4506 case PIPE_C:
4507 cpt_set_fdi_bc_bifurcation(dev, true);
4508
4509 break;
4510 default:
4511 BUG();
4512 }
4513 }
4514
4515 /* Return which DP Port should be selected for Transcoder DP control */
4516 static enum port
4517 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4518 {
4519 struct drm_device *dev = crtc->dev;
4520 struct intel_encoder *encoder;
4521
4522 for_each_encoder_on_crtc(dev, crtc, encoder) {
4523 if (encoder->type == INTEL_OUTPUT_DP ||
4524 encoder->type == INTEL_OUTPUT_EDP)
4525 return enc_to_dig_port(&encoder->base)->port;
4526 }
4527
4528 return -1;
4529 }
4530
4531 /*
4532 * Enable PCH resources required for PCH ports:
4533 * - PCH PLLs
4534 * - FDI training & RX/TX
4535 * - update transcoder timings
4536 * - DP transcoding bits
4537 * - transcoder
4538 */
4539 static void ironlake_pch_enable(struct drm_crtc *crtc)
4540 {
4541 struct drm_device *dev = crtc->dev;
4542 struct drm_i915_private *dev_priv = to_i915(dev);
4543 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4544 int pipe = intel_crtc->pipe;
4545 u32 temp;
4546
4547 assert_pch_transcoder_disabled(dev_priv, pipe);
4548
4549 if (IS_IVYBRIDGE(dev))
4550 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4551
4552 /* Write the TU size bits before fdi link training, so that error
4553 * detection works. */
4554 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4555 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4556
4557 /* For PCH output, training FDI link */
4558 dev_priv->display.fdi_link_train(crtc);
4559
4560 /* We need to program the right clock selection before writing the pixel
4561 * mutliplier into the DPLL. */
4562 if (HAS_PCH_CPT(dev)) {
4563 u32 sel;
4564
4565 temp = I915_READ(PCH_DPLL_SEL);
4566 temp |= TRANS_DPLL_ENABLE(pipe);
4567 sel = TRANS_DPLLB_SEL(pipe);
4568 if (intel_crtc->config->shared_dpll ==
4569 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4570 temp |= sel;
4571 else
4572 temp &= ~sel;
4573 I915_WRITE(PCH_DPLL_SEL, temp);
4574 }
4575
4576 /* XXX: pch pll's can be enabled any time before we enable the PCH
4577 * transcoder, and we actually should do this to not upset any PCH
4578 * transcoder that already use the clock when we share it.
4579 *
4580 * Note that enable_shared_dpll tries to do the right thing, but
4581 * get_shared_dpll unconditionally resets the pll - we need that to have
4582 * the right LVDS enable sequence. */
4583 intel_enable_shared_dpll(intel_crtc);
4584
4585 /* set transcoder timing, panel must allow it */
4586 assert_panel_unlocked(dev_priv, pipe);
4587 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4588
4589 intel_fdi_normal_train(crtc);
4590
4591 /* For PCH DP, enable TRANS_DP_CTL */
4592 if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) {
4593 const struct drm_display_mode *adjusted_mode =
4594 &intel_crtc->config->base.adjusted_mode;
4595 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4596 i915_reg_t reg = TRANS_DP_CTL(pipe);
4597 temp = I915_READ(reg);
4598 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4599 TRANS_DP_SYNC_MASK |
4600 TRANS_DP_BPC_MASK);
4601 temp |= TRANS_DP_OUTPUT_ENABLE;
4602 temp |= bpc << 9; /* same format but at 11:9 */
4603
4604 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4605 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4606 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4607 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4608
4609 switch (intel_trans_dp_port_sel(crtc)) {
4610 case PORT_B:
4611 temp |= TRANS_DP_PORT_SEL_B;
4612 break;
4613 case PORT_C:
4614 temp |= TRANS_DP_PORT_SEL_C;
4615 break;
4616 case PORT_D:
4617 temp |= TRANS_DP_PORT_SEL_D;
4618 break;
4619 default:
4620 BUG();
4621 }
4622
4623 I915_WRITE(reg, temp);
4624 }
4625
4626 ironlake_enable_pch_transcoder(dev_priv, pipe);
4627 }
4628
4629 static void lpt_pch_enable(struct drm_crtc *crtc)
4630 {
4631 struct drm_device *dev = crtc->dev;
4632 struct drm_i915_private *dev_priv = to_i915(dev);
4633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4634 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4635
4636 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4637
4638 lpt_program_iclkip(crtc);
4639
4640 /* Set transcoder timing. */
4641 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4642
4643 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4644 }
4645
4646 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4647 {
4648 struct drm_i915_private *dev_priv = to_i915(dev);
4649 i915_reg_t dslreg = PIPEDSL(pipe);
4650 u32 temp;
4651
4652 temp = I915_READ(dslreg);
4653 udelay(500);
4654 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4655 if (wait_for(I915_READ(dslreg) != temp, 5))
4656 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4657 }
4658 }
4659
4660 static int
4661 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4662 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4663 int src_w, int src_h, int dst_w, int dst_h)
4664 {
4665 struct intel_crtc_scaler_state *scaler_state =
4666 &crtc_state->scaler_state;
4667 struct intel_crtc *intel_crtc =
4668 to_intel_crtc(crtc_state->base.crtc);
4669 int need_scaling;
4670
4671 need_scaling = intel_rotation_90_or_270(rotation) ?
4672 (src_h != dst_w || src_w != dst_h):
4673 (src_w != dst_w || src_h != dst_h);
4674
4675 /*
4676 * if plane is being disabled or scaler is no more required or force detach
4677 * - free scaler binded to this plane/crtc
4678 * - in order to do this, update crtc->scaler_usage
4679 *
4680 * Here scaler state in crtc_state is set free so that
4681 * scaler can be assigned to other user. Actual register
4682 * update to free the scaler is done in plane/panel-fit programming.
4683 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4684 */
4685 if (force_detach || !need_scaling) {
4686 if (*scaler_id >= 0) {
4687 scaler_state->scaler_users &= ~(1 << scaler_user);
4688 scaler_state->scalers[*scaler_id].in_use = 0;
4689
4690 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4691 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4692 intel_crtc->pipe, scaler_user, *scaler_id,
4693 scaler_state->scaler_users);
4694 *scaler_id = -1;
4695 }
4696 return 0;
4697 }
4698
4699 /* range checks */
4700 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4701 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4702
4703 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4704 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4705 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4706 "size is out of scaler range\n",
4707 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4708 return -EINVAL;
4709 }
4710
4711 /* mark this plane as a scaler user in crtc_state */
4712 scaler_state->scaler_users |= (1 << scaler_user);
4713 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4714 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4715 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4716 scaler_state->scaler_users);
4717
4718 return 0;
4719 }
4720
4721 /**
4722 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4723 *
4724 * @state: crtc's scaler state
4725 *
4726 * Return
4727 * 0 - scaler_usage updated successfully
4728 * error - requested scaling cannot be supported or other error condition
4729 */
4730 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4731 {
4732 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4733 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4734
4735 DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4736 intel_crtc->base.base.id, intel_crtc->base.name,
4737 intel_crtc->pipe, SKL_CRTC_INDEX);
4738
4739 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4740 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4741 state->pipe_src_w, state->pipe_src_h,
4742 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4743 }
4744
4745 /**
4746 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4747 *
4748 * @state: crtc's scaler state
4749 * @plane_state: atomic plane state to update
4750 *
4751 * Return
4752 * 0 - scaler_usage updated successfully
4753 * error - requested scaling cannot be supported or other error condition
4754 */
4755 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4756 struct intel_plane_state *plane_state)
4757 {
4758
4759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4760 struct intel_plane *intel_plane =
4761 to_intel_plane(plane_state->base.plane);
4762 struct drm_framebuffer *fb = plane_state->base.fb;
4763 int ret;
4764
4765 bool force_detach = !fb || !plane_state->base.visible;
4766
4767 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4768 intel_plane->base.base.id, intel_plane->base.name,
4769 intel_crtc->pipe, drm_plane_index(&intel_plane->base));
4770
4771 ret = skl_update_scaler(crtc_state, force_detach,
4772 drm_plane_index(&intel_plane->base),
4773 &plane_state->scaler_id,
4774 plane_state->base.rotation,
4775 drm_rect_width(&plane_state->base.src) >> 16,
4776 drm_rect_height(&plane_state->base.src) >> 16,
4777 drm_rect_width(&plane_state->base.dst),
4778 drm_rect_height(&plane_state->base.dst));
4779
4780 if (ret || plane_state->scaler_id < 0)
4781 return ret;
4782
4783 /* check colorkey */
4784 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4785 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4786 intel_plane->base.base.id,
4787 intel_plane->base.name);
4788 return -EINVAL;
4789 }
4790
4791 /* Check src format */
4792 switch (fb->pixel_format) {
4793 case DRM_FORMAT_RGB565:
4794 case DRM_FORMAT_XBGR8888:
4795 case DRM_FORMAT_XRGB8888:
4796 case DRM_FORMAT_ABGR8888:
4797 case DRM_FORMAT_ARGB8888:
4798 case DRM_FORMAT_XRGB2101010:
4799 case DRM_FORMAT_XBGR2101010:
4800 case DRM_FORMAT_YUYV:
4801 case DRM_FORMAT_YVYU:
4802 case DRM_FORMAT_UYVY:
4803 case DRM_FORMAT_VYUY:
4804 break;
4805 default:
4806 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4807 intel_plane->base.base.id, intel_plane->base.name,
4808 fb->base.id, fb->pixel_format);
4809 return -EINVAL;
4810 }
4811
4812 return 0;
4813 }
4814
4815 static void skylake_scaler_disable(struct intel_crtc *crtc)
4816 {
4817 int i;
4818
4819 for (i = 0; i < crtc->num_scalers; i++)
4820 skl_detach_scaler(crtc, i);
4821 }
4822
4823 static void skylake_pfit_enable(struct intel_crtc *crtc)
4824 {
4825 struct drm_device *dev = crtc->base.dev;
4826 struct drm_i915_private *dev_priv = to_i915(dev);
4827 int pipe = crtc->pipe;
4828 struct intel_crtc_scaler_state *scaler_state =
4829 &crtc->config->scaler_state;
4830
4831 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4832
4833 if (crtc->config->pch_pfit.enabled) {
4834 int id;
4835
4836 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4837 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4838 return;
4839 }
4840
4841 id = scaler_state->scaler_id;
4842 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4843 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4844 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4845 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4846
4847 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4848 }
4849 }
4850
4851 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4852 {
4853 struct drm_device *dev = crtc->base.dev;
4854 struct drm_i915_private *dev_priv = to_i915(dev);
4855 int pipe = crtc->pipe;
4856
4857 if (crtc->config->pch_pfit.enabled) {
4858 /* Force use of hard-coded filter coefficients
4859 * as some pre-programmed values are broken,
4860 * e.g. x201.
4861 */
4862 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4863 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4864 PF_PIPE_SEL_IVB(pipe));
4865 else
4866 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4867 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4868 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4869 }
4870 }
4871
4872 void hsw_enable_ips(struct intel_crtc *crtc)
4873 {
4874 struct drm_device *dev = crtc->base.dev;
4875 struct drm_i915_private *dev_priv = to_i915(dev);
4876
4877 if (!crtc->config->ips_enabled)
4878 return;
4879
4880 /*
4881 * We can only enable IPS after we enable a plane and wait for a vblank
4882 * This function is called from post_plane_update, which is run after
4883 * a vblank wait.
4884 */
4885
4886 assert_plane_enabled(dev_priv, crtc->plane);
4887 if (IS_BROADWELL(dev)) {
4888 mutex_lock(&dev_priv->rps.hw_lock);
4889 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4890 mutex_unlock(&dev_priv->rps.hw_lock);
4891 /* Quoting Art Runyan: "its not safe to expect any particular
4892 * value in IPS_CTL bit 31 after enabling IPS through the
4893 * mailbox." Moreover, the mailbox may return a bogus state,
4894 * so we need to just enable it and continue on.
4895 */
4896 } else {
4897 I915_WRITE(IPS_CTL, IPS_ENABLE);
4898 /* The bit only becomes 1 in the next vblank, so this wait here
4899 * is essentially intel_wait_for_vblank. If we don't have this
4900 * and don't wait for vblanks until the end of crtc_enable, then
4901 * the HW state readout code will complain that the expected
4902 * IPS_CTL value is not the one we read. */
4903 if (intel_wait_for_register(dev_priv,
4904 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4905 50))
4906 DRM_ERROR("Timed out waiting for IPS enable\n");
4907 }
4908 }
4909
4910 void hsw_disable_ips(struct intel_crtc *crtc)
4911 {
4912 struct drm_device *dev = crtc->base.dev;
4913 struct drm_i915_private *dev_priv = to_i915(dev);
4914
4915 if (!crtc->config->ips_enabled)
4916 return;
4917
4918 assert_plane_enabled(dev_priv, crtc->plane);
4919 if (IS_BROADWELL(dev)) {
4920 mutex_lock(&dev_priv->rps.hw_lock);
4921 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4922 mutex_unlock(&dev_priv->rps.hw_lock);
4923 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4924 if (intel_wait_for_register(dev_priv,
4925 IPS_CTL, IPS_ENABLE, 0,
4926 42))
4927 DRM_ERROR("Timed out waiting for IPS disable\n");
4928 } else {
4929 I915_WRITE(IPS_CTL, 0);
4930 POSTING_READ(IPS_CTL);
4931 }
4932
4933 /* We need to wait for a vblank before we can disable the plane. */
4934 intel_wait_for_vblank(dev, crtc->pipe);
4935 }
4936
4937 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4938 {
4939 if (intel_crtc->overlay) {
4940 struct drm_device *dev = intel_crtc->base.dev;
4941 struct drm_i915_private *dev_priv = to_i915(dev);
4942
4943 mutex_lock(&dev->struct_mutex);
4944 dev_priv->mm.interruptible = false;
4945 (void) intel_overlay_switch_off(intel_crtc->overlay);
4946 dev_priv->mm.interruptible = true;
4947 mutex_unlock(&dev->struct_mutex);
4948 }
4949
4950 /* Let userspace switch the overlay on again. In most cases userspace
4951 * has to recompute where to put it anyway.
4952 */
4953 }
4954
4955 /**
4956 * intel_post_enable_primary - Perform operations after enabling primary plane
4957 * @crtc: the CRTC whose primary plane was just enabled
4958 *
4959 * Performs potentially sleeping operations that must be done after the primary
4960 * plane is enabled, such as updating FBC and IPS. Note that this may be
4961 * called due to an explicit primary plane update, or due to an implicit
4962 * re-enable that is caused when a sprite plane is updated to no longer
4963 * completely hide the primary plane.
4964 */
4965 static void
4966 intel_post_enable_primary(struct drm_crtc *crtc)
4967 {
4968 struct drm_device *dev = crtc->dev;
4969 struct drm_i915_private *dev_priv = to_i915(dev);
4970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4971 int pipe = intel_crtc->pipe;
4972
4973 /*
4974 * FIXME IPS should be fine as long as one plane is
4975 * enabled, but in practice it seems to have problems
4976 * when going from primary only to sprite only and vice
4977 * versa.
4978 */
4979 hsw_enable_ips(intel_crtc);
4980
4981 /*
4982 * Gen2 reports pipe underruns whenever all planes are disabled.
4983 * So don't enable underrun reporting before at least some planes
4984 * are enabled.
4985 * FIXME: Need to fix the logic to work when we turn off all planes
4986 * but leave the pipe running.
4987 */
4988 if (IS_GEN2(dev))
4989 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4990
4991 /* Underruns don't always raise interrupts, so check manually. */
4992 intel_check_cpu_fifo_underruns(dev_priv);
4993 intel_check_pch_fifo_underruns(dev_priv);
4994 }
4995
4996 /* FIXME move all this to pre_plane_update() with proper state tracking */
4997 static void
4998 intel_pre_disable_primary(struct drm_crtc *crtc)
4999 {
5000 struct drm_device *dev = crtc->dev;
5001 struct drm_i915_private *dev_priv = to_i915(dev);
5002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5003 int pipe = intel_crtc->pipe;
5004
5005 /*
5006 * Gen2 reports pipe underruns whenever all planes are disabled.
5007 * So diasble underrun reporting before all the planes get disabled.
5008 * FIXME: Need to fix the logic to work when we turn off all planes
5009 * but leave the pipe running.
5010 */
5011 if (IS_GEN2(dev))
5012 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5013
5014 /*
5015 * FIXME IPS should be fine as long as one plane is
5016 * enabled, but in practice it seems to have problems
5017 * when going from primary only to sprite only and vice
5018 * versa.
5019 */
5020 hsw_disable_ips(intel_crtc);
5021 }
5022
5023 /* FIXME get rid of this and use pre_plane_update */
5024 static void
5025 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5026 {
5027 struct drm_device *dev = crtc->dev;
5028 struct drm_i915_private *dev_priv = to_i915(dev);
5029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5030 int pipe = intel_crtc->pipe;
5031
5032 intel_pre_disable_primary(crtc);
5033
5034 /*
5035 * Vblank time updates from the shadow to live plane control register
5036 * are blocked if the memory self-refresh mode is active at that
5037 * moment. So to make sure the plane gets truly disabled, disable
5038 * first the self-refresh mode. The self-refresh enable bit in turn
5039 * will be checked/applied by the HW only at the next frame start
5040 * event which is after the vblank start event, so we need to have a
5041 * wait-for-vblank between disabling the plane and the pipe.
5042 */
5043 if (HAS_GMCH_DISPLAY(dev)) {
5044 intel_set_memory_cxsr(dev_priv, false);
5045 dev_priv->wm.vlv.cxsr = false;
5046 intel_wait_for_vblank(dev, pipe);
5047 }
5048 }
5049
5050 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5051 {
5052 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5053 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5054 struct intel_crtc_state *pipe_config =
5055 to_intel_crtc_state(crtc->base.state);
5056 struct drm_plane *primary = crtc->base.primary;
5057 struct drm_plane_state *old_pri_state =
5058 drm_atomic_get_existing_plane_state(old_state, primary);
5059
5060 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5061
5062 crtc->wm.cxsr_allowed = true;
5063
5064 if (pipe_config->update_wm_post && pipe_config->base.active)
5065 intel_update_watermarks(&crtc->base);
5066
5067 if (old_pri_state) {
5068 struct intel_plane_state *primary_state =
5069 to_intel_plane_state(primary->state);
5070 struct intel_plane_state *old_primary_state =
5071 to_intel_plane_state(old_pri_state);
5072
5073 intel_fbc_post_update(crtc);
5074
5075 if (primary_state->base.visible &&
5076 (needs_modeset(&pipe_config->base) ||
5077 !old_primary_state->base.visible))
5078 intel_post_enable_primary(&crtc->base);
5079 }
5080 }
5081
5082 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
5083 {
5084 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5085 struct drm_device *dev = crtc->base.dev;
5086 struct drm_i915_private *dev_priv = to_i915(dev);
5087 struct intel_crtc_state *pipe_config =
5088 to_intel_crtc_state(crtc->base.state);
5089 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5090 struct drm_plane *primary = crtc->base.primary;
5091 struct drm_plane_state *old_pri_state =
5092 drm_atomic_get_existing_plane_state(old_state, primary);
5093 bool modeset = needs_modeset(&pipe_config->base);
5094
5095 if (old_pri_state) {
5096 struct intel_plane_state *primary_state =
5097 to_intel_plane_state(primary->state);
5098 struct intel_plane_state *old_primary_state =
5099 to_intel_plane_state(old_pri_state);
5100
5101 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5102
5103 if (old_primary_state->base.visible &&
5104 (modeset || !primary_state->base.visible))
5105 intel_pre_disable_primary(&crtc->base);
5106 }
5107
5108 if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
5109 crtc->wm.cxsr_allowed = false;
5110
5111 /*
5112 * Vblank time updates from the shadow to live plane control register
5113 * are blocked if the memory self-refresh mode is active at that
5114 * moment. So to make sure the plane gets truly disabled, disable
5115 * first the self-refresh mode. The self-refresh enable bit in turn
5116 * will be checked/applied by the HW only at the next frame start
5117 * event which is after the vblank start event, so we need to have a
5118 * wait-for-vblank between disabling the plane and the pipe.
5119 */
5120 if (old_crtc_state->base.active) {
5121 intel_set_memory_cxsr(dev_priv, false);
5122 dev_priv->wm.vlv.cxsr = false;
5123 intel_wait_for_vblank(dev, crtc->pipe);
5124 }
5125 }
5126
5127 /*
5128 * IVB workaround: must disable low power watermarks for at least
5129 * one frame before enabling scaling. LP watermarks can be re-enabled
5130 * when scaling is disabled.
5131 *
5132 * WaCxSRDisabledForSpriteScaling:ivb
5133 */
5134 if (pipe_config->disable_lp_wm) {
5135 ilk_disable_lp_wm(dev);
5136 intel_wait_for_vblank(dev, crtc->pipe);
5137 }
5138
5139 /*
5140 * If we're doing a modeset, we're done. No need to do any pre-vblank
5141 * watermark programming here.
5142 */
5143 if (needs_modeset(&pipe_config->base))
5144 return;
5145
5146 /*
5147 * For platforms that support atomic watermarks, program the
5148 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5149 * will be the intermediate values that are safe for both pre- and
5150 * post- vblank; when vblank happens, the 'active' values will be set
5151 * to the final 'target' values and we'll do this again to get the
5152 * optimal watermarks. For gen9+ platforms, the values we program here
5153 * will be the final target values which will get automatically latched
5154 * at vblank time; no further programming will be necessary.
5155 *
5156 * If a platform hasn't been transitioned to atomic watermarks yet,
5157 * we'll continue to update watermarks the old way, if flags tell
5158 * us to.
5159 */
5160 if (dev_priv->display.initial_watermarks != NULL)
5161 dev_priv->display.initial_watermarks(pipe_config);
5162 else if (pipe_config->update_wm_pre)
5163 intel_update_watermarks(&crtc->base);
5164 }
5165
5166 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5167 {
5168 struct drm_device *dev = crtc->dev;
5169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5170 struct drm_plane *p;
5171 int pipe = intel_crtc->pipe;
5172
5173 intel_crtc_dpms_overlay_disable(intel_crtc);
5174
5175 drm_for_each_plane_mask(p, dev, plane_mask)
5176 to_intel_plane(p)->disable_plane(p, crtc);
5177
5178 /*
5179 * FIXME: Once we grow proper nuclear flip support out of this we need
5180 * to compute the mask of flip planes precisely. For the time being
5181 * consider this a flip to a NULL plane.
5182 */
5183 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5184 }
5185
5186 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5187 struct intel_crtc_state *crtc_state,
5188 struct drm_atomic_state *old_state)
5189 {
5190 struct drm_connector_state *old_conn_state;
5191 struct drm_connector *conn;
5192 int i;
5193
5194 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5195 struct drm_connector_state *conn_state = conn->state;
5196 struct intel_encoder *encoder =
5197 to_intel_encoder(conn_state->best_encoder);
5198
5199 if (conn_state->crtc != crtc)
5200 continue;
5201
5202 if (encoder->pre_pll_enable)
5203 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5204 }
5205 }
5206
5207 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5208 struct intel_crtc_state *crtc_state,
5209 struct drm_atomic_state *old_state)
5210 {
5211 struct drm_connector_state *old_conn_state;
5212 struct drm_connector *conn;
5213 int i;
5214
5215 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5216 struct drm_connector_state *conn_state = conn->state;
5217 struct intel_encoder *encoder =
5218 to_intel_encoder(conn_state->best_encoder);
5219
5220 if (conn_state->crtc != crtc)
5221 continue;
5222
5223 if (encoder->pre_enable)
5224 encoder->pre_enable(encoder, crtc_state, conn_state);
5225 }
5226 }
5227
5228 static void intel_encoders_enable(struct drm_crtc *crtc,
5229 struct intel_crtc_state *crtc_state,
5230 struct drm_atomic_state *old_state)
5231 {
5232 struct drm_connector_state *old_conn_state;
5233 struct drm_connector *conn;
5234 int i;
5235
5236 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5237 struct drm_connector_state *conn_state = conn->state;
5238 struct intel_encoder *encoder =
5239 to_intel_encoder(conn_state->best_encoder);
5240
5241 if (conn_state->crtc != crtc)
5242 continue;
5243
5244 encoder->enable(encoder, crtc_state, conn_state);
5245 intel_opregion_notify_encoder(encoder, true);
5246 }
5247 }
5248
5249 static void intel_encoders_disable(struct drm_crtc *crtc,
5250 struct intel_crtc_state *old_crtc_state,
5251 struct drm_atomic_state *old_state)
5252 {
5253 struct drm_connector_state *old_conn_state;
5254 struct drm_connector *conn;
5255 int i;
5256
5257 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5258 struct intel_encoder *encoder =
5259 to_intel_encoder(old_conn_state->best_encoder);
5260
5261 if (old_conn_state->crtc != crtc)
5262 continue;
5263
5264 intel_opregion_notify_encoder(encoder, false);
5265 encoder->disable(encoder, old_crtc_state, old_conn_state);
5266 }
5267 }
5268
5269 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5270 struct intel_crtc_state *old_crtc_state,
5271 struct drm_atomic_state *old_state)
5272 {
5273 struct drm_connector_state *old_conn_state;
5274 struct drm_connector *conn;
5275 int i;
5276
5277 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5278 struct intel_encoder *encoder =
5279 to_intel_encoder(old_conn_state->best_encoder);
5280
5281 if (old_conn_state->crtc != crtc)
5282 continue;
5283
5284 if (encoder->post_disable)
5285 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5286 }
5287 }
5288
5289 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5290 struct intel_crtc_state *old_crtc_state,
5291 struct drm_atomic_state *old_state)
5292 {
5293 struct drm_connector_state *old_conn_state;
5294 struct drm_connector *conn;
5295 int i;
5296
5297 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5298 struct intel_encoder *encoder =
5299 to_intel_encoder(old_conn_state->best_encoder);
5300
5301 if (old_conn_state->crtc != crtc)
5302 continue;
5303
5304 if (encoder->post_pll_disable)
5305 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5306 }
5307 }
5308
5309 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5310 struct drm_atomic_state *old_state)
5311 {
5312 struct drm_crtc *crtc = pipe_config->base.crtc;
5313 struct drm_device *dev = crtc->dev;
5314 struct drm_i915_private *dev_priv = to_i915(dev);
5315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5316 int pipe = intel_crtc->pipe;
5317
5318 if (WARN_ON(intel_crtc->active))
5319 return;
5320
5321 /*
5322 * Sometimes spurious CPU pipe underruns happen during FDI
5323 * training, at least with VGA+HDMI cloning. Suppress them.
5324 *
5325 * On ILK we get an occasional spurious CPU pipe underruns
5326 * between eDP port A enable and vdd enable. Also PCH port
5327 * enable seems to result in the occasional CPU pipe underrun.
5328 *
5329 * Spurious PCH underruns also occur during PCH enabling.
5330 */
5331 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5332 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5333 if (intel_crtc->config->has_pch_encoder)
5334 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5335
5336 if (intel_crtc->config->has_pch_encoder)
5337 intel_prepare_shared_dpll(intel_crtc);
5338
5339 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5340 intel_dp_set_m_n(intel_crtc, M1_N1);
5341
5342 intel_set_pipe_timings(intel_crtc);
5343 intel_set_pipe_src_size(intel_crtc);
5344
5345 if (intel_crtc->config->has_pch_encoder) {
5346 intel_cpu_transcoder_set_m_n(intel_crtc,
5347 &intel_crtc->config->fdi_m_n, NULL);
5348 }
5349
5350 ironlake_set_pipeconf(crtc);
5351
5352 intel_crtc->active = true;
5353
5354 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5355
5356 if (intel_crtc->config->has_pch_encoder) {
5357 /* Note: FDI PLL enabling _must_ be done before we enable the
5358 * cpu pipes, hence this is separate from all the other fdi/pch
5359 * enabling. */
5360 ironlake_fdi_pll_enable(intel_crtc);
5361 } else {
5362 assert_fdi_tx_disabled(dev_priv, pipe);
5363 assert_fdi_rx_disabled(dev_priv, pipe);
5364 }
5365
5366 ironlake_pfit_enable(intel_crtc);
5367
5368 /*
5369 * On ILK+ LUT must be loaded before the pipe is running but with
5370 * clocks enabled
5371 */
5372 intel_color_load_luts(&pipe_config->base);
5373
5374 if (dev_priv->display.initial_watermarks != NULL)
5375 dev_priv->display.initial_watermarks(intel_crtc->config);
5376 intel_enable_pipe(intel_crtc);
5377
5378 if (intel_crtc->config->has_pch_encoder)
5379 ironlake_pch_enable(crtc);
5380
5381 assert_vblank_disabled(crtc);
5382 drm_crtc_vblank_on(crtc);
5383
5384 intel_encoders_enable(crtc, pipe_config, old_state);
5385
5386 if (HAS_PCH_CPT(dev))
5387 cpt_verify_modeset(dev, intel_crtc->pipe);
5388
5389 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5390 if (intel_crtc->config->has_pch_encoder)
5391 intel_wait_for_vblank(dev, pipe);
5392 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5393 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5394 }
5395
5396 /* IPS only exists on ULT machines and is tied to pipe A. */
5397 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5398 {
5399 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
5400 }
5401
5402 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5403 struct drm_atomic_state *old_state)
5404 {
5405 struct drm_crtc *crtc = pipe_config->base.crtc;
5406 struct drm_device *dev = crtc->dev;
5407 struct drm_i915_private *dev_priv = to_i915(dev);
5408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5409 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5410 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5411
5412 if (WARN_ON(intel_crtc->active))
5413 return;
5414
5415 if (intel_crtc->config->has_pch_encoder)
5416 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5417 false);
5418
5419 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5420
5421 if (intel_crtc->config->shared_dpll)
5422 intel_enable_shared_dpll(intel_crtc);
5423
5424 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5425 intel_dp_set_m_n(intel_crtc, M1_N1);
5426
5427 if (!transcoder_is_dsi(cpu_transcoder))
5428 intel_set_pipe_timings(intel_crtc);
5429
5430 intel_set_pipe_src_size(intel_crtc);
5431
5432 if (cpu_transcoder != TRANSCODER_EDP &&
5433 !transcoder_is_dsi(cpu_transcoder)) {
5434 I915_WRITE(PIPE_MULT(cpu_transcoder),
5435 intel_crtc->config->pixel_multiplier - 1);
5436 }
5437
5438 if (intel_crtc->config->has_pch_encoder) {
5439 intel_cpu_transcoder_set_m_n(intel_crtc,
5440 &intel_crtc->config->fdi_m_n, NULL);
5441 }
5442
5443 if (!transcoder_is_dsi(cpu_transcoder))
5444 haswell_set_pipeconf(crtc);
5445
5446 haswell_set_pipemisc(crtc);
5447
5448 intel_color_set_csc(&pipe_config->base);
5449
5450 intel_crtc->active = true;
5451
5452 if (intel_crtc->config->has_pch_encoder)
5453 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5454 else
5455 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5456
5457 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5458
5459 if (intel_crtc->config->has_pch_encoder)
5460 dev_priv->display.fdi_link_train(crtc);
5461
5462 if (!transcoder_is_dsi(cpu_transcoder))
5463 intel_ddi_enable_pipe_clock(intel_crtc);
5464
5465 if (INTEL_INFO(dev)->gen >= 9)
5466 skylake_pfit_enable(intel_crtc);
5467 else
5468 ironlake_pfit_enable(intel_crtc);
5469
5470 /*
5471 * On ILK+ LUT must be loaded before the pipe is running but with
5472 * clocks enabled
5473 */
5474 intel_color_load_luts(&pipe_config->base);
5475
5476 intel_ddi_set_pipe_settings(crtc);
5477 if (!transcoder_is_dsi(cpu_transcoder))
5478 intel_ddi_enable_transcoder_func(crtc);
5479
5480 if (dev_priv->display.initial_watermarks != NULL)
5481 dev_priv->display.initial_watermarks(pipe_config);
5482 else
5483 intel_update_watermarks(crtc);
5484
5485 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5486 if (!transcoder_is_dsi(cpu_transcoder))
5487 intel_enable_pipe(intel_crtc);
5488
5489 if (intel_crtc->config->has_pch_encoder)
5490 lpt_pch_enable(crtc);
5491
5492 if (intel_crtc->config->dp_encoder_is_mst)
5493 intel_ddi_set_vc_payload_alloc(crtc, true);
5494
5495 assert_vblank_disabled(crtc);
5496 drm_crtc_vblank_on(crtc);
5497
5498 intel_encoders_enable(crtc, pipe_config, old_state);
5499
5500 if (intel_crtc->config->has_pch_encoder) {
5501 intel_wait_for_vblank(dev, pipe);
5502 intel_wait_for_vblank(dev, pipe);
5503 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5504 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5505 true);
5506 }
5507
5508 /* If we change the relative order between pipe/planes enabling, we need
5509 * to change the workaround. */
5510 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5511 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5512 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5513 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5514 }
5515 }
5516
5517 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5518 {
5519 struct drm_device *dev = crtc->base.dev;
5520 struct drm_i915_private *dev_priv = to_i915(dev);
5521 int pipe = crtc->pipe;
5522
5523 /* To avoid upsetting the power well on haswell only disable the pfit if
5524 * it's in use. The hw state code will make sure we get this right. */
5525 if (force || crtc->config->pch_pfit.enabled) {
5526 I915_WRITE(PF_CTL(pipe), 0);
5527 I915_WRITE(PF_WIN_POS(pipe), 0);
5528 I915_WRITE(PF_WIN_SZ(pipe), 0);
5529 }
5530 }
5531
5532 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5533 struct drm_atomic_state *old_state)
5534 {
5535 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5536 struct drm_device *dev = crtc->dev;
5537 struct drm_i915_private *dev_priv = to_i915(dev);
5538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5539 int pipe = intel_crtc->pipe;
5540
5541 /*
5542 * Sometimes spurious CPU pipe underruns happen when the
5543 * pipe is already disabled, but FDI RX/TX is still enabled.
5544 * Happens at least with VGA+HDMI cloning. Suppress them.
5545 */
5546 if (intel_crtc->config->has_pch_encoder) {
5547 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5548 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5549 }
5550
5551 intel_encoders_disable(crtc, old_crtc_state, old_state);
5552
5553 drm_crtc_vblank_off(crtc);
5554 assert_vblank_disabled(crtc);
5555
5556 intel_disable_pipe(intel_crtc);
5557
5558 ironlake_pfit_disable(intel_crtc, false);
5559
5560 if (intel_crtc->config->has_pch_encoder)
5561 ironlake_fdi_disable(crtc);
5562
5563 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5564
5565 if (intel_crtc->config->has_pch_encoder) {
5566 ironlake_disable_pch_transcoder(dev_priv, pipe);
5567
5568 if (HAS_PCH_CPT(dev)) {
5569 i915_reg_t reg;
5570 u32 temp;
5571
5572 /* disable TRANS_DP_CTL */
5573 reg = TRANS_DP_CTL(pipe);
5574 temp = I915_READ(reg);
5575 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5576 TRANS_DP_PORT_SEL_MASK);
5577 temp |= TRANS_DP_PORT_SEL_NONE;
5578 I915_WRITE(reg, temp);
5579
5580 /* disable DPLL_SEL */
5581 temp = I915_READ(PCH_DPLL_SEL);
5582 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5583 I915_WRITE(PCH_DPLL_SEL, temp);
5584 }
5585
5586 ironlake_fdi_pll_disable(intel_crtc);
5587 }
5588
5589 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5590 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5591 }
5592
5593 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5594 struct drm_atomic_state *old_state)
5595 {
5596 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5597 struct drm_device *dev = crtc->dev;
5598 struct drm_i915_private *dev_priv = to_i915(dev);
5599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5600 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5601
5602 if (intel_crtc->config->has_pch_encoder)
5603 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5604 false);
5605
5606 intel_encoders_disable(crtc, old_crtc_state, old_state);
5607
5608 drm_crtc_vblank_off(crtc);
5609 assert_vblank_disabled(crtc);
5610
5611 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5612 if (!transcoder_is_dsi(cpu_transcoder))
5613 intel_disable_pipe(intel_crtc);
5614
5615 if (intel_crtc->config->dp_encoder_is_mst)
5616 intel_ddi_set_vc_payload_alloc(crtc, false);
5617
5618 if (!transcoder_is_dsi(cpu_transcoder))
5619 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5620
5621 if (INTEL_INFO(dev)->gen >= 9)
5622 skylake_scaler_disable(intel_crtc);
5623 else
5624 ironlake_pfit_disable(intel_crtc, false);
5625
5626 if (!transcoder_is_dsi(cpu_transcoder))
5627 intel_ddi_disable_pipe_clock(intel_crtc);
5628
5629 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5630
5631 if (old_crtc_state->has_pch_encoder)
5632 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5633 true);
5634 }
5635
5636 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5637 {
5638 struct drm_device *dev = crtc->base.dev;
5639 struct drm_i915_private *dev_priv = to_i915(dev);
5640 struct intel_crtc_state *pipe_config = crtc->config;
5641
5642 if (!pipe_config->gmch_pfit.control)
5643 return;
5644
5645 /*
5646 * The panel fitter should only be adjusted whilst the pipe is disabled,
5647 * according to register description and PRM.
5648 */
5649 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5650 assert_pipe_disabled(dev_priv, crtc->pipe);
5651
5652 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5653 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5654
5655 /* Border color in case we don't scale up to the full screen. Black by
5656 * default, change to something else for debugging. */
5657 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5658 }
5659
5660 static enum intel_display_power_domain port_to_power_domain(enum port port)
5661 {
5662 switch (port) {
5663 case PORT_A:
5664 return POWER_DOMAIN_PORT_DDI_A_LANES;
5665 case PORT_B:
5666 return POWER_DOMAIN_PORT_DDI_B_LANES;
5667 case PORT_C:
5668 return POWER_DOMAIN_PORT_DDI_C_LANES;
5669 case PORT_D:
5670 return POWER_DOMAIN_PORT_DDI_D_LANES;
5671 case PORT_E:
5672 return POWER_DOMAIN_PORT_DDI_E_LANES;
5673 default:
5674 MISSING_CASE(port);
5675 return POWER_DOMAIN_PORT_OTHER;
5676 }
5677 }
5678
5679 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5680 {
5681 switch (port) {
5682 case PORT_A:
5683 return POWER_DOMAIN_AUX_A;
5684 case PORT_B:
5685 return POWER_DOMAIN_AUX_B;
5686 case PORT_C:
5687 return POWER_DOMAIN_AUX_C;
5688 case PORT_D:
5689 return POWER_DOMAIN_AUX_D;
5690 case PORT_E:
5691 /* FIXME: Check VBT for actual wiring of PORT E */
5692 return POWER_DOMAIN_AUX_D;
5693 default:
5694 MISSING_CASE(port);
5695 return POWER_DOMAIN_AUX_A;
5696 }
5697 }
5698
5699 enum intel_display_power_domain
5700 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5701 {
5702 struct drm_device *dev = intel_encoder->base.dev;
5703 struct intel_digital_port *intel_dig_port;
5704
5705 switch (intel_encoder->type) {
5706 case INTEL_OUTPUT_UNKNOWN:
5707 /* Only DDI platforms should ever use this output type */
5708 WARN_ON_ONCE(!HAS_DDI(dev));
5709 case INTEL_OUTPUT_DP:
5710 case INTEL_OUTPUT_HDMI:
5711 case INTEL_OUTPUT_EDP:
5712 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5713 return port_to_power_domain(intel_dig_port->port);
5714 case INTEL_OUTPUT_DP_MST:
5715 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5716 return port_to_power_domain(intel_dig_port->port);
5717 case INTEL_OUTPUT_ANALOG:
5718 return POWER_DOMAIN_PORT_CRT;
5719 case INTEL_OUTPUT_DSI:
5720 return POWER_DOMAIN_PORT_DSI;
5721 default:
5722 return POWER_DOMAIN_PORT_OTHER;
5723 }
5724 }
5725
5726 enum intel_display_power_domain
5727 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5728 {
5729 struct drm_device *dev = intel_encoder->base.dev;
5730 struct intel_digital_port *intel_dig_port;
5731
5732 switch (intel_encoder->type) {
5733 case INTEL_OUTPUT_UNKNOWN:
5734 case INTEL_OUTPUT_HDMI:
5735 /*
5736 * Only DDI platforms should ever use these output types.
5737 * We can get here after the HDMI detect code has already set
5738 * the type of the shared encoder. Since we can't be sure
5739 * what's the status of the given connectors, play safe and
5740 * run the DP detection too.
5741 */
5742 WARN_ON_ONCE(!HAS_DDI(dev));
5743 case INTEL_OUTPUT_DP:
5744 case INTEL_OUTPUT_EDP:
5745 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5746 return port_to_aux_power_domain(intel_dig_port->port);
5747 case INTEL_OUTPUT_DP_MST:
5748 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5749 return port_to_aux_power_domain(intel_dig_port->port);
5750 default:
5751 MISSING_CASE(intel_encoder->type);
5752 return POWER_DOMAIN_AUX_A;
5753 }
5754 }
5755
5756 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5757 struct intel_crtc_state *crtc_state)
5758 {
5759 struct drm_device *dev = crtc->dev;
5760 struct drm_encoder *encoder;
5761 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5762 enum pipe pipe = intel_crtc->pipe;
5763 unsigned long mask;
5764 enum transcoder transcoder = crtc_state->cpu_transcoder;
5765
5766 if (!crtc_state->base.active)
5767 return 0;
5768
5769 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5770 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5771 if (crtc_state->pch_pfit.enabled ||
5772 crtc_state->pch_pfit.force_thru)
5773 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5774
5775 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5776 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5777
5778 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5779 }
5780
5781 if (crtc_state->shared_dpll)
5782 mask |= BIT(POWER_DOMAIN_PLLS);
5783
5784 return mask;
5785 }
5786
5787 static unsigned long
5788 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5789 struct intel_crtc_state *crtc_state)
5790 {
5791 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5793 enum intel_display_power_domain domain;
5794 unsigned long domains, new_domains, old_domains;
5795
5796 old_domains = intel_crtc->enabled_power_domains;
5797 intel_crtc->enabled_power_domains = new_domains =
5798 get_crtc_power_domains(crtc, crtc_state);
5799
5800 domains = new_domains & ~old_domains;
5801
5802 for_each_power_domain(domain, domains)
5803 intel_display_power_get(dev_priv, domain);
5804
5805 return old_domains & ~new_domains;
5806 }
5807
5808 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5809 unsigned long domains)
5810 {
5811 enum intel_display_power_domain domain;
5812
5813 for_each_power_domain(domain, domains)
5814 intel_display_power_put(dev_priv, domain);
5815 }
5816
5817 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5818 {
5819 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5820
5821 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5822 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5823 return max_cdclk_freq;
5824 else if (IS_CHERRYVIEW(dev_priv))
5825 return max_cdclk_freq*95/100;
5826 else if (INTEL_INFO(dev_priv)->gen < 4)
5827 return 2*max_cdclk_freq*90/100;
5828 else
5829 return max_cdclk_freq*90/100;
5830 }
5831
5832 static int skl_calc_cdclk(int max_pixclk, int vco);
5833
5834 static void intel_update_max_cdclk(struct drm_device *dev)
5835 {
5836 struct drm_i915_private *dev_priv = to_i915(dev);
5837
5838 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5839 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5840 int max_cdclk, vco;
5841
5842 vco = dev_priv->skl_preferred_vco_freq;
5843 WARN_ON(vco != 8100000 && vco != 8640000);
5844
5845 /*
5846 * Use the lower (vco 8640) cdclk values as a
5847 * first guess. skl_calc_cdclk() will correct it
5848 * if the preferred vco is 8100 instead.
5849 */
5850 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5851 max_cdclk = 617143;
5852 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5853 max_cdclk = 540000;
5854 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5855 max_cdclk = 432000;
5856 else
5857 max_cdclk = 308571;
5858
5859 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5860 } else if (IS_BROXTON(dev)) {
5861 dev_priv->max_cdclk_freq = 624000;
5862 } else if (IS_BROADWELL(dev)) {
5863 /*
5864 * FIXME with extra cooling we can allow
5865 * 540 MHz for ULX and 675 Mhz for ULT.
5866 * How can we know if extra cooling is
5867 * available? PCI ID, VTB, something else?
5868 */
5869 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5870 dev_priv->max_cdclk_freq = 450000;
5871 else if (IS_BDW_ULX(dev))
5872 dev_priv->max_cdclk_freq = 450000;
5873 else if (IS_BDW_ULT(dev))
5874 dev_priv->max_cdclk_freq = 540000;
5875 else
5876 dev_priv->max_cdclk_freq = 675000;
5877 } else if (IS_CHERRYVIEW(dev)) {
5878 dev_priv->max_cdclk_freq = 320000;
5879 } else if (IS_VALLEYVIEW(dev)) {
5880 dev_priv->max_cdclk_freq = 400000;
5881 } else {
5882 /* otherwise assume cdclk is fixed */
5883 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5884 }
5885
5886 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5887
5888 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5889 dev_priv->max_cdclk_freq);
5890
5891 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5892 dev_priv->max_dotclk_freq);
5893 }
5894
5895 static void intel_update_cdclk(struct drm_device *dev)
5896 {
5897 struct drm_i915_private *dev_priv = to_i915(dev);
5898
5899 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5900
5901 if (INTEL_GEN(dev_priv) >= 9)
5902 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5903 dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5904 dev_priv->cdclk_pll.ref);
5905 else
5906 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5907 dev_priv->cdclk_freq);
5908
5909 /*
5910 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5911 * Programmng [sic] note: bit[9:2] should be programmed to the number
5912 * of cdclk that generates 4MHz reference clock freq which is used to
5913 * generate GMBus clock. This will vary with the cdclk freq.
5914 */
5915 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5916 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5917 }
5918
5919 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5920 static int skl_cdclk_decimal(int cdclk)
5921 {
5922 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5923 }
5924
5925 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5926 {
5927 int ratio;
5928
5929 if (cdclk == dev_priv->cdclk_pll.ref)
5930 return 0;
5931
5932 switch (cdclk) {
5933 default:
5934 MISSING_CASE(cdclk);
5935 case 144000:
5936 case 288000:
5937 case 384000:
5938 case 576000:
5939 ratio = 60;
5940 break;
5941 case 624000:
5942 ratio = 65;
5943 break;
5944 }
5945
5946 return dev_priv->cdclk_pll.ref * ratio;
5947 }
5948
5949 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5950 {
5951 I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5952
5953 /* Timeout 200us */
5954 if (intel_wait_for_register(dev_priv,
5955 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5956 1))
5957 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5958
5959 dev_priv->cdclk_pll.vco = 0;
5960 }
5961
5962 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5963 {
5964 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5965 u32 val;
5966
5967 val = I915_READ(BXT_DE_PLL_CTL);
5968 val &= ~BXT_DE_PLL_RATIO_MASK;
5969 val |= BXT_DE_PLL_RATIO(ratio);
5970 I915_WRITE(BXT_DE_PLL_CTL, val);
5971
5972 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5973
5974 /* Timeout 200us */
5975 if (intel_wait_for_register(dev_priv,
5976 BXT_DE_PLL_ENABLE,
5977 BXT_DE_PLL_LOCK,
5978 BXT_DE_PLL_LOCK,
5979 1))
5980 DRM_ERROR("timeout waiting for DE PLL lock\n");
5981
5982 dev_priv->cdclk_pll.vco = vco;
5983 }
5984
5985 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5986 {
5987 u32 val, divider;
5988 int vco, ret;
5989
5990 vco = bxt_de_pll_vco(dev_priv, cdclk);
5991
5992 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5993
5994 /* cdclk = vco / 2 / div{1,1.5,2,4} */
5995 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5996 case 8:
5997 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5998 break;
5999 case 4:
6000 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
6001 break;
6002 case 3:
6003 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
6004 break;
6005 case 2:
6006 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6007 break;
6008 default:
6009 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
6010 WARN_ON(vco != 0);
6011
6012 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6013 break;
6014 }
6015
6016 /* Inform power controller of upcoming frequency change */
6017 mutex_lock(&dev_priv->rps.hw_lock);
6018 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6019 0x80000000);
6020 mutex_unlock(&dev_priv->rps.hw_lock);
6021
6022 if (ret) {
6023 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
6024 ret, cdclk);
6025 return;
6026 }
6027
6028 if (dev_priv->cdclk_pll.vco != 0 &&
6029 dev_priv->cdclk_pll.vco != vco)
6030 bxt_de_pll_disable(dev_priv);
6031
6032 if (dev_priv->cdclk_pll.vco != vco)
6033 bxt_de_pll_enable(dev_priv, vco);
6034
6035 val = divider | skl_cdclk_decimal(cdclk);
6036 /*
6037 * FIXME if only the cd2x divider needs changing, it could be done
6038 * without shutting off the pipe (if only one pipe is active).
6039 */
6040 val |= BXT_CDCLK_CD2X_PIPE_NONE;
6041 /*
6042 * Disable SSA Precharge when CD clock frequency < 500 MHz,
6043 * enable otherwise.
6044 */
6045 if (cdclk >= 500000)
6046 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6047 I915_WRITE(CDCLK_CTL, val);
6048
6049 mutex_lock(&dev_priv->rps.hw_lock);
6050 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6051 DIV_ROUND_UP(cdclk, 25000));
6052 mutex_unlock(&dev_priv->rps.hw_lock);
6053
6054 if (ret) {
6055 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
6056 ret, cdclk);
6057 return;
6058 }
6059
6060 intel_update_cdclk(&dev_priv->drm);
6061 }
6062
6063 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
6064 {
6065 u32 cdctl, expected;
6066
6067 intel_update_cdclk(&dev_priv->drm);
6068
6069 if (dev_priv->cdclk_pll.vco == 0 ||
6070 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6071 goto sanitize;
6072
6073 /* DPLL okay; verify the cdclock
6074 *
6075 * Some BIOS versions leave an incorrect decimal frequency value and
6076 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
6077 * so sanitize this register.
6078 */
6079 cdctl = I915_READ(CDCLK_CTL);
6080 /*
6081 * Let's ignore the pipe field, since BIOS could have configured the
6082 * dividers both synching to an active pipe, or asynchronously
6083 * (PIPE_NONE).
6084 */
6085 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
6086
6087 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
6088 skl_cdclk_decimal(dev_priv->cdclk_freq);
6089 /*
6090 * Disable SSA Precharge when CD clock frequency < 500 MHz,
6091 * enable otherwise.
6092 */
6093 if (dev_priv->cdclk_freq >= 500000)
6094 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6095
6096 if (cdctl == expected)
6097 /* All well; nothing to sanitize */
6098 return;
6099
6100 sanitize:
6101 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6102
6103 /* force cdclk programming */
6104 dev_priv->cdclk_freq = 0;
6105
6106 /* force full PLL disable + enable */
6107 dev_priv->cdclk_pll.vco = -1;
6108 }
6109
6110 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
6111 {
6112 bxt_sanitize_cdclk(dev_priv);
6113
6114 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
6115 return;
6116
6117 /*
6118 * FIXME:
6119 * - The initial CDCLK needs to be read from VBT.
6120 * Need to make this change after VBT has changes for BXT.
6121 */
6122 bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
6123 }
6124
6125 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
6126 {
6127 bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
6128 }
6129
6130 static int skl_calc_cdclk(int max_pixclk, int vco)
6131 {
6132 if (vco == 8640000) {
6133 if (max_pixclk > 540000)
6134 return 617143;
6135 else if (max_pixclk > 432000)
6136 return 540000;
6137 else if (max_pixclk > 308571)
6138 return 432000;
6139 else
6140 return 308571;
6141 } else {
6142 if (max_pixclk > 540000)
6143 return 675000;
6144 else if (max_pixclk > 450000)
6145 return 540000;
6146 else if (max_pixclk > 337500)
6147 return 450000;
6148 else
6149 return 337500;
6150 }
6151 }
6152
6153 static void
6154 skl_dpll0_update(struct drm_i915_private *dev_priv)
6155 {
6156 u32 val;
6157
6158 dev_priv->cdclk_pll.ref = 24000;
6159 dev_priv->cdclk_pll.vco = 0;
6160
6161 val = I915_READ(LCPLL1_CTL);
6162 if ((val & LCPLL_PLL_ENABLE) == 0)
6163 return;
6164
6165 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
6166 return;
6167
6168 val = I915_READ(DPLL_CTRL1);
6169
6170 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
6171 DPLL_CTRL1_SSC(SKL_DPLL0) |
6172 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
6173 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
6174 return;
6175
6176 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
6177 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
6178 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
6179 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
6180 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
6181 dev_priv->cdclk_pll.vco = 8100000;
6182 break;
6183 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
6184 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
6185 dev_priv->cdclk_pll.vco = 8640000;
6186 break;
6187 default:
6188 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6189 break;
6190 }
6191 }
6192
6193 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
6194 {
6195 bool changed = dev_priv->skl_preferred_vco_freq != vco;
6196
6197 dev_priv->skl_preferred_vco_freq = vco;
6198
6199 if (changed)
6200 intel_update_max_cdclk(&dev_priv->drm);
6201 }
6202
6203 static void
6204 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
6205 {
6206 int min_cdclk = skl_calc_cdclk(0, vco);
6207 u32 val;
6208
6209 WARN_ON(vco != 8100000 && vco != 8640000);
6210
6211 /* select the minimum CDCLK before enabling DPLL 0 */
6212 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
6213 I915_WRITE(CDCLK_CTL, val);
6214 POSTING_READ(CDCLK_CTL);
6215
6216 /*
6217 * We always enable DPLL0 with the lowest link rate possible, but still
6218 * taking into account the VCO required to operate the eDP panel at the
6219 * desired frequency. The usual DP link rates operate with a VCO of
6220 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
6221 * The modeset code is responsible for the selection of the exact link
6222 * rate later on, with the constraint of choosing a frequency that
6223 * works with vco.
6224 */
6225 val = I915_READ(DPLL_CTRL1);
6226
6227 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
6228 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6229 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
6230 if (vco == 8640000)
6231 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
6232 SKL_DPLL0);
6233 else
6234 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
6235 SKL_DPLL0);
6236
6237 I915_WRITE(DPLL_CTRL1, val);
6238 POSTING_READ(DPLL_CTRL1);
6239
6240 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
6241
6242 if (intel_wait_for_register(dev_priv,
6243 LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
6244 5))
6245 DRM_ERROR("DPLL0 not locked\n");
6246
6247 dev_priv->cdclk_pll.vco = vco;
6248
6249 /* We'll want to keep using the current vco from now on. */
6250 skl_set_preferred_cdclk_vco(dev_priv, vco);
6251 }
6252
6253 static void
6254 skl_dpll0_disable(struct drm_i915_private *dev_priv)
6255 {
6256 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
6257 if (intel_wait_for_register(dev_priv,
6258 LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
6259 1))
6260 DRM_ERROR("Couldn't disable DPLL0\n");
6261
6262 dev_priv->cdclk_pll.vco = 0;
6263 }
6264
6265 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
6266 {
6267 int ret;
6268 u32 val;
6269
6270 /* inform PCU we want to change CDCLK */
6271 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
6272 mutex_lock(&dev_priv->rps.hw_lock);
6273 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
6274 mutex_unlock(&dev_priv->rps.hw_lock);
6275
6276 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
6277 }
6278
6279 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
6280 {
6281 return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0;
6282 }
6283
6284 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
6285 {
6286 struct drm_device *dev = &dev_priv->drm;
6287 u32 freq_select, pcu_ack;
6288
6289 WARN_ON((cdclk == 24000) != (vco == 0));
6290
6291 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
6292
6293 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
6294 DRM_ERROR("failed to inform PCU about cdclk change\n");
6295 return;
6296 }
6297
6298 /* set CDCLK_CTL */
6299 switch (cdclk) {
6300 case 450000:
6301 case 432000:
6302 freq_select = CDCLK_FREQ_450_432;
6303 pcu_ack = 1;
6304 break;
6305 case 540000:
6306 freq_select = CDCLK_FREQ_540;
6307 pcu_ack = 2;
6308 break;
6309 case 308571:
6310 case 337500:
6311 default:
6312 freq_select = CDCLK_FREQ_337_308;
6313 pcu_ack = 0;
6314 break;
6315 case 617143:
6316 case 675000:
6317 freq_select = CDCLK_FREQ_675_617;
6318 pcu_ack = 3;
6319 break;
6320 }
6321
6322 if (dev_priv->cdclk_pll.vco != 0 &&
6323 dev_priv->cdclk_pll.vco != vco)
6324 skl_dpll0_disable(dev_priv);
6325
6326 if (dev_priv->cdclk_pll.vco != vco)
6327 skl_dpll0_enable(dev_priv, vco);
6328
6329 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
6330 POSTING_READ(CDCLK_CTL);
6331
6332 /* inform PCU of the change */
6333 mutex_lock(&dev_priv->rps.hw_lock);
6334 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
6335 mutex_unlock(&dev_priv->rps.hw_lock);
6336
6337 intel_update_cdclk(dev);
6338 }
6339
6340 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
6341
6342 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
6343 {
6344 skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
6345 }
6346
6347 void skl_init_cdclk(struct drm_i915_private *dev_priv)
6348 {
6349 int cdclk, vco;
6350
6351 skl_sanitize_cdclk(dev_priv);
6352
6353 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
6354 /*
6355 * Use the current vco as our initial
6356 * guess as to what the preferred vco is.
6357 */
6358 if (dev_priv->skl_preferred_vco_freq == 0)
6359 skl_set_preferred_cdclk_vco(dev_priv,
6360 dev_priv->cdclk_pll.vco);
6361 return;
6362 }
6363
6364 vco = dev_priv->skl_preferred_vco_freq;
6365 if (vco == 0)
6366 vco = 8100000;
6367 cdclk = skl_calc_cdclk(0, vco);
6368
6369 skl_set_cdclk(dev_priv, cdclk, vco);
6370 }
6371
6372 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
6373 {
6374 uint32_t cdctl, expected;
6375
6376 /*
6377 * check if the pre-os intialized the display
6378 * There is SWF18 scratchpad register defined which is set by the
6379 * pre-os which can be used by the OS drivers to check the status
6380 */
6381 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
6382 goto sanitize;
6383
6384 intel_update_cdclk(&dev_priv->drm);
6385 /* Is PLL enabled and locked ? */
6386 if (dev_priv->cdclk_pll.vco == 0 ||
6387 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6388 goto sanitize;
6389
6390 /* DPLL okay; verify the cdclock
6391 *
6392 * Noticed in some instances that the freq selection is correct but
6393 * decimal part is programmed wrong from BIOS where pre-os does not
6394 * enable display. Verify the same as well.
6395 */
6396 cdctl = I915_READ(CDCLK_CTL);
6397 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
6398 skl_cdclk_decimal(dev_priv->cdclk_freq);
6399 if (cdctl == expected)
6400 /* All well; nothing to sanitize */
6401 return;
6402
6403 sanitize:
6404 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6405
6406 /* force cdclk programming */
6407 dev_priv->cdclk_freq = 0;
6408 /* force full PLL disable + enable */
6409 dev_priv->cdclk_pll.vco = -1;
6410 }
6411
6412 /* Adjust CDclk dividers to allow high res or save power if possible */
6413 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
6414 {
6415 struct drm_i915_private *dev_priv = to_i915(dev);
6416 u32 val, cmd;
6417
6418 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6419 != dev_priv->cdclk_freq);
6420
6421 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
6422 cmd = 2;
6423 else if (cdclk == 266667)
6424 cmd = 1;
6425 else
6426 cmd = 0;
6427
6428 mutex_lock(&dev_priv->rps.hw_lock);
6429 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6430 val &= ~DSPFREQGUAR_MASK;
6431 val |= (cmd << DSPFREQGUAR_SHIFT);
6432 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6433 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6434 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
6435 50)) {
6436 DRM_ERROR("timed out waiting for CDclk change\n");
6437 }
6438 mutex_unlock(&dev_priv->rps.hw_lock);
6439
6440 mutex_lock(&dev_priv->sb_lock);
6441
6442 if (cdclk == 400000) {
6443 u32 divider;
6444
6445 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6446
6447 /* adjust cdclk divider */
6448 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6449 val &= ~CCK_FREQUENCY_VALUES;
6450 val |= divider;
6451 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
6452
6453 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
6454 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
6455 50))
6456 DRM_ERROR("timed out waiting for CDclk change\n");
6457 }
6458
6459 /* adjust self-refresh exit latency value */
6460 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
6461 val &= ~0x7f;
6462
6463 /*
6464 * For high bandwidth configs, we set a higher latency in the bunit
6465 * so that the core display fetch happens in time to avoid underruns.
6466 */
6467 if (cdclk == 400000)
6468 val |= 4500 / 250; /* 4.5 usec */
6469 else
6470 val |= 3000 / 250; /* 3.0 usec */
6471 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
6472
6473 mutex_unlock(&dev_priv->sb_lock);
6474
6475 intel_update_cdclk(dev);
6476 }
6477
6478 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
6479 {
6480 struct drm_i915_private *dev_priv = to_i915(dev);
6481 u32 val, cmd;
6482
6483 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6484 != dev_priv->cdclk_freq);
6485
6486 switch (cdclk) {
6487 case 333333:
6488 case 320000:
6489 case 266667:
6490 case 200000:
6491 break;
6492 default:
6493 MISSING_CASE(cdclk);
6494 return;
6495 }
6496
6497 /*
6498 * Specs are full of misinformation, but testing on actual
6499 * hardware has shown that we just need to write the desired
6500 * CCK divider into the Punit register.
6501 */
6502 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6503
6504 mutex_lock(&dev_priv->rps.hw_lock);
6505 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6506 val &= ~DSPFREQGUAR_MASK_CHV;
6507 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6508 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6509 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6510 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6511 50)) {
6512 DRM_ERROR("timed out waiting for CDclk change\n");
6513 }
6514 mutex_unlock(&dev_priv->rps.hw_lock);
6515
6516 intel_update_cdclk(dev);
6517 }
6518
6519 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6520 int max_pixclk)
6521 {
6522 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6523 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6524
6525 /*
6526 * Really only a few cases to deal with, as only 4 CDclks are supported:
6527 * 200MHz
6528 * 267MHz
6529 * 320/333MHz (depends on HPLL freq)
6530 * 400MHz (VLV only)
6531 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6532 * of the lower bin and adjust if needed.
6533 *
6534 * We seem to get an unstable or solid color picture at 200MHz.
6535 * Not sure what's wrong. For now use 200MHz only when all pipes
6536 * are off.
6537 */
6538 if (!IS_CHERRYVIEW(dev_priv) &&
6539 max_pixclk > freq_320*limit/100)
6540 return 400000;
6541 else if (max_pixclk > 266667*limit/100)
6542 return freq_320;
6543 else if (max_pixclk > 0)
6544 return 266667;
6545 else
6546 return 200000;
6547 }
6548
6549 static int bxt_calc_cdclk(int max_pixclk)
6550 {
6551 if (max_pixclk > 576000)
6552 return 624000;
6553 else if (max_pixclk > 384000)
6554 return 576000;
6555 else if (max_pixclk > 288000)
6556 return 384000;
6557 else if (max_pixclk > 144000)
6558 return 288000;
6559 else
6560 return 144000;
6561 }
6562
6563 /* Compute the max pixel clock for new configuration. */
6564 static int intel_mode_max_pixclk(struct drm_device *dev,
6565 struct drm_atomic_state *state)
6566 {
6567 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6568 struct drm_i915_private *dev_priv = to_i915(dev);
6569 struct drm_crtc *crtc;
6570 struct drm_crtc_state *crtc_state;
6571 unsigned max_pixclk = 0, i;
6572 enum pipe pipe;
6573
6574 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6575 sizeof(intel_state->min_pixclk));
6576
6577 for_each_crtc_in_state(state, crtc, crtc_state, i) {
6578 int pixclk = 0;
6579
6580 if (crtc_state->enable)
6581 pixclk = crtc_state->adjusted_mode.crtc_clock;
6582
6583 intel_state->min_pixclk[i] = pixclk;
6584 }
6585
6586 for_each_pipe(dev_priv, pipe)
6587 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6588
6589 return max_pixclk;
6590 }
6591
6592 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6593 {
6594 struct drm_device *dev = state->dev;
6595 struct drm_i915_private *dev_priv = to_i915(dev);
6596 int max_pixclk = intel_mode_max_pixclk(dev, state);
6597 struct intel_atomic_state *intel_state =
6598 to_intel_atomic_state(state);
6599
6600 intel_state->cdclk = intel_state->dev_cdclk =
6601 valleyview_calc_cdclk(dev_priv, max_pixclk);
6602
6603 if (!intel_state->active_crtcs)
6604 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6605
6606 return 0;
6607 }
6608
6609 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6610 {
6611 int max_pixclk = ilk_max_pixel_rate(state);
6612 struct intel_atomic_state *intel_state =
6613 to_intel_atomic_state(state);
6614
6615 intel_state->cdclk = intel_state->dev_cdclk =
6616 bxt_calc_cdclk(max_pixclk);
6617
6618 if (!intel_state->active_crtcs)
6619 intel_state->dev_cdclk = bxt_calc_cdclk(0);
6620
6621 return 0;
6622 }
6623
6624 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6625 {
6626 unsigned int credits, default_credits;
6627
6628 if (IS_CHERRYVIEW(dev_priv))
6629 default_credits = PFI_CREDIT(12);
6630 else
6631 default_credits = PFI_CREDIT(8);
6632
6633 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6634 /* CHV suggested value is 31 or 63 */
6635 if (IS_CHERRYVIEW(dev_priv))
6636 credits = PFI_CREDIT_63;
6637 else
6638 credits = PFI_CREDIT(15);
6639 } else {
6640 credits = default_credits;
6641 }
6642
6643 /*
6644 * WA - write default credits before re-programming
6645 * FIXME: should we also set the resend bit here?
6646 */
6647 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6648 default_credits);
6649
6650 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6651 credits | PFI_CREDIT_RESEND);
6652
6653 /*
6654 * FIXME is this guaranteed to clear
6655 * immediately or should we poll for it?
6656 */
6657 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6658 }
6659
6660 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6661 {
6662 struct drm_device *dev = old_state->dev;
6663 struct drm_i915_private *dev_priv = to_i915(dev);
6664 struct intel_atomic_state *old_intel_state =
6665 to_intel_atomic_state(old_state);
6666 unsigned req_cdclk = old_intel_state->dev_cdclk;
6667
6668 /*
6669 * FIXME: We can end up here with all power domains off, yet
6670 * with a CDCLK frequency other than the minimum. To account
6671 * for this take the PIPE-A power domain, which covers the HW
6672 * blocks needed for the following programming. This can be
6673 * removed once it's guaranteed that we get here either with
6674 * the minimum CDCLK set, or the required power domains
6675 * enabled.
6676 */
6677 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6678
6679 if (IS_CHERRYVIEW(dev))
6680 cherryview_set_cdclk(dev, req_cdclk);
6681 else
6682 valleyview_set_cdclk(dev, req_cdclk);
6683
6684 vlv_program_pfi_credits(dev_priv);
6685
6686 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6687 }
6688
6689 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6690 struct drm_atomic_state *old_state)
6691 {
6692 struct drm_crtc *crtc = pipe_config->base.crtc;
6693 struct drm_device *dev = crtc->dev;
6694 struct drm_i915_private *dev_priv = to_i915(dev);
6695 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6696 int pipe = intel_crtc->pipe;
6697
6698 if (WARN_ON(intel_crtc->active))
6699 return;
6700
6701 if (intel_crtc_has_dp_encoder(intel_crtc->config))
6702 intel_dp_set_m_n(intel_crtc, M1_N1);
6703
6704 intel_set_pipe_timings(intel_crtc);
6705 intel_set_pipe_src_size(intel_crtc);
6706
6707 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6708 struct drm_i915_private *dev_priv = to_i915(dev);
6709
6710 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6711 I915_WRITE(CHV_CANVAS(pipe), 0);
6712 }
6713
6714 i9xx_set_pipeconf(intel_crtc);
6715
6716 intel_crtc->active = true;
6717
6718 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6719
6720 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6721
6722 if (IS_CHERRYVIEW(dev)) {
6723 chv_prepare_pll(intel_crtc, intel_crtc->config);
6724 chv_enable_pll(intel_crtc, intel_crtc->config);
6725 } else {
6726 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6727 vlv_enable_pll(intel_crtc, intel_crtc->config);
6728 }
6729
6730 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6731
6732 i9xx_pfit_enable(intel_crtc);
6733
6734 intel_color_load_luts(&pipe_config->base);
6735
6736 intel_update_watermarks(crtc);
6737 intel_enable_pipe(intel_crtc);
6738
6739 assert_vblank_disabled(crtc);
6740 drm_crtc_vblank_on(crtc);
6741
6742 intel_encoders_enable(crtc, pipe_config, old_state);
6743 }
6744
6745 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6746 {
6747 struct drm_device *dev = crtc->base.dev;
6748 struct drm_i915_private *dev_priv = to_i915(dev);
6749
6750 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6751 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6752 }
6753
6754 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6755 struct drm_atomic_state *old_state)
6756 {
6757 struct drm_crtc *crtc = pipe_config->base.crtc;
6758 struct drm_device *dev = crtc->dev;
6759 struct drm_i915_private *dev_priv = to_i915(dev);
6760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6761 enum pipe pipe = intel_crtc->pipe;
6762
6763 if (WARN_ON(intel_crtc->active))
6764 return;
6765
6766 i9xx_set_pll_dividers(intel_crtc);
6767
6768 if (intel_crtc_has_dp_encoder(intel_crtc->config))
6769 intel_dp_set_m_n(intel_crtc, M1_N1);
6770
6771 intel_set_pipe_timings(intel_crtc);
6772 intel_set_pipe_src_size(intel_crtc);
6773
6774 i9xx_set_pipeconf(intel_crtc);
6775
6776 intel_crtc->active = true;
6777
6778 if (!IS_GEN2(dev))
6779 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6780
6781 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6782
6783 i9xx_enable_pll(intel_crtc);
6784
6785 i9xx_pfit_enable(intel_crtc);
6786
6787 intel_color_load_luts(&pipe_config->base);
6788
6789 intel_update_watermarks(crtc);
6790 intel_enable_pipe(intel_crtc);
6791
6792 assert_vblank_disabled(crtc);
6793 drm_crtc_vblank_on(crtc);
6794
6795 intel_encoders_enable(crtc, pipe_config, old_state);
6796 }
6797
6798 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6799 {
6800 struct drm_device *dev = crtc->base.dev;
6801 struct drm_i915_private *dev_priv = to_i915(dev);
6802
6803 if (!crtc->config->gmch_pfit.control)
6804 return;
6805
6806 assert_pipe_disabled(dev_priv, crtc->pipe);
6807
6808 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6809 I915_READ(PFIT_CONTROL));
6810 I915_WRITE(PFIT_CONTROL, 0);
6811 }
6812
6813 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6814 struct drm_atomic_state *old_state)
6815 {
6816 struct drm_crtc *crtc = old_crtc_state->base.crtc;
6817 struct drm_device *dev = crtc->dev;
6818 struct drm_i915_private *dev_priv = to_i915(dev);
6819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6820 int pipe = intel_crtc->pipe;
6821
6822 /*
6823 * On gen2 planes are double buffered but the pipe isn't, so we must
6824 * wait for planes to fully turn off before disabling the pipe.
6825 */
6826 if (IS_GEN2(dev))
6827 intel_wait_for_vblank(dev, pipe);
6828
6829 intel_encoders_disable(crtc, old_crtc_state, old_state);
6830
6831 drm_crtc_vblank_off(crtc);
6832 assert_vblank_disabled(crtc);
6833
6834 intel_disable_pipe(intel_crtc);
6835
6836 i9xx_pfit_disable(intel_crtc);
6837
6838 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6839
6840 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6841 if (IS_CHERRYVIEW(dev))
6842 chv_disable_pll(dev_priv, pipe);
6843 else if (IS_VALLEYVIEW(dev))
6844 vlv_disable_pll(dev_priv, pipe);
6845 else
6846 i9xx_disable_pll(intel_crtc);
6847 }
6848
6849 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6850
6851 if (!IS_GEN2(dev))
6852 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6853 }
6854
6855 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6856 {
6857 struct intel_encoder *encoder;
6858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6859 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6860 enum intel_display_power_domain domain;
6861 unsigned long domains;
6862 struct drm_atomic_state *state;
6863 struct intel_crtc_state *crtc_state;
6864 int ret;
6865
6866 if (!intel_crtc->active)
6867 return;
6868
6869 if (to_intel_plane_state(crtc->primary->state)->base.visible) {
6870 WARN_ON(intel_crtc->flip_work);
6871
6872 intel_pre_disable_primary_noatomic(crtc);
6873
6874 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6875 to_intel_plane_state(crtc->primary->state)->base.visible = false;
6876 }
6877
6878 state = drm_atomic_state_alloc(crtc->dev);
6879 state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
6880
6881 /* Everything's already locked, -EDEADLK can't happen. */
6882 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6883 ret = drm_atomic_add_affected_connectors(state, crtc);
6884
6885 WARN_ON(IS_ERR(crtc_state) || ret);
6886
6887 dev_priv->display.crtc_disable(crtc_state, state);
6888
6889 drm_atomic_state_free(state);
6890
6891 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6892 crtc->base.id, crtc->name);
6893
6894 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6895 crtc->state->active = false;
6896 intel_crtc->active = false;
6897 crtc->enabled = false;
6898 crtc->state->connector_mask = 0;
6899 crtc->state->encoder_mask = 0;
6900
6901 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6902 encoder->base.crtc = NULL;
6903
6904 intel_fbc_disable(intel_crtc);
6905 intel_update_watermarks(crtc);
6906 intel_disable_shared_dpll(intel_crtc);
6907
6908 domains = intel_crtc->enabled_power_domains;
6909 for_each_power_domain(domain, domains)
6910 intel_display_power_put(dev_priv, domain);
6911 intel_crtc->enabled_power_domains = 0;
6912
6913 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6914 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6915 }
6916
6917 /*
6918 * turn all crtc's off, but do not adjust state
6919 * This has to be paired with a call to intel_modeset_setup_hw_state.
6920 */
6921 int intel_display_suspend(struct drm_device *dev)
6922 {
6923 struct drm_i915_private *dev_priv = to_i915(dev);
6924 struct drm_atomic_state *state;
6925 int ret;
6926
6927 state = drm_atomic_helper_suspend(dev);
6928 ret = PTR_ERR_OR_ZERO(state);
6929 if (ret)
6930 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6931 else
6932 dev_priv->modeset_restore_state = state;
6933 return ret;
6934 }
6935
6936 void intel_encoder_destroy(struct drm_encoder *encoder)
6937 {
6938 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6939
6940 drm_encoder_cleanup(encoder);
6941 kfree(intel_encoder);
6942 }
6943
6944 /* Cross check the actual hw state with our own modeset state tracking (and it's
6945 * internal consistency). */
6946 static void intel_connector_verify_state(struct intel_connector *connector)
6947 {
6948 struct drm_crtc *crtc = connector->base.state->crtc;
6949
6950 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6951 connector->base.base.id,
6952 connector->base.name);
6953
6954 if (connector->get_hw_state(connector)) {
6955 struct intel_encoder *encoder = connector->encoder;
6956 struct drm_connector_state *conn_state = connector->base.state;
6957
6958 I915_STATE_WARN(!crtc,
6959 "connector enabled without attached crtc\n");
6960
6961 if (!crtc)
6962 return;
6963
6964 I915_STATE_WARN(!crtc->state->active,
6965 "connector is active, but attached crtc isn't\n");
6966
6967 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6968 return;
6969
6970 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6971 "atomic encoder doesn't match attached encoder\n");
6972
6973 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6974 "attached encoder crtc differs from connector crtc\n");
6975 } else {
6976 I915_STATE_WARN(crtc && crtc->state->active,
6977 "attached crtc is active, but connector isn't\n");
6978 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6979 "best encoder set without crtc!\n");
6980 }
6981 }
6982
6983 int intel_connector_init(struct intel_connector *connector)
6984 {
6985 drm_atomic_helper_connector_reset(&connector->base);
6986
6987 if (!connector->base.state)
6988 return -ENOMEM;
6989
6990 return 0;
6991 }
6992
6993 struct intel_connector *intel_connector_alloc(void)
6994 {
6995 struct intel_connector *connector;
6996
6997 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6998 if (!connector)
6999 return NULL;
7000
7001 if (intel_connector_init(connector) < 0) {
7002 kfree(connector);
7003 return NULL;
7004 }
7005
7006 return connector;
7007 }
7008
7009 /* Simple connector->get_hw_state implementation for encoders that support only
7010 * one connector and no cloning and hence the encoder state determines the state
7011 * of the connector. */
7012 bool intel_connector_get_hw_state(struct intel_connector *connector)
7013 {
7014 enum pipe pipe = 0;
7015 struct intel_encoder *encoder = connector->encoder;
7016
7017 return encoder->get_hw_state(encoder, &pipe);
7018 }
7019
7020 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7021 {
7022 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
7023 return crtc_state->fdi_lanes;
7024
7025 return 0;
7026 }
7027
7028 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7029 struct intel_crtc_state *pipe_config)
7030 {
7031 struct drm_atomic_state *state = pipe_config->base.state;
7032 struct intel_crtc *other_crtc;
7033 struct intel_crtc_state *other_crtc_state;
7034
7035 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7036 pipe_name(pipe), pipe_config->fdi_lanes);
7037 if (pipe_config->fdi_lanes > 4) {
7038 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7039 pipe_name(pipe), pipe_config->fdi_lanes);
7040 return -EINVAL;
7041 }
7042
7043 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7044 if (pipe_config->fdi_lanes > 2) {
7045 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7046 pipe_config->fdi_lanes);
7047 return -EINVAL;
7048 } else {
7049 return 0;
7050 }
7051 }
7052
7053 if (INTEL_INFO(dev)->num_pipes == 2)
7054 return 0;
7055
7056 /* Ivybridge 3 pipe is really complicated */
7057 switch (pipe) {
7058 case PIPE_A:
7059 return 0;
7060 case PIPE_B:
7061 if (pipe_config->fdi_lanes <= 2)
7062 return 0;
7063
7064 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
7065 other_crtc_state =
7066 intel_atomic_get_crtc_state(state, other_crtc);
7067 if (IS_ERR(other_crtc_state))
7068 return PTR_ERR(other_crtc_state);
7069
7070 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7071 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7072 pipe_name(pipe), pipe_config->fdi_lanes);
7073 return -EINVAL;
7074 }
7075 return 0;
7076 case PIPE_C:
7077 if (pipe_config->fdi_lanes > 2) {
7078 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7079 pipe_name(pipe), pipe_config->fdi_lanes);
7080 return -EINVAL;
7081 }
7082
7083 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
7084 other_crtc_state =
7085 intel_atomic_get_crtc_state(state, other_crtc);
7086 if (IS_ERR(other_crtc_state))
7087 return PTR_ERR(other_crtc_state);
7088
7089 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7090 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7091 return -EINVAL;
7092 }
7093 return 0;
7094 default:
7095 BUG();
7096 }
7097 }
7098
7099 #define RETRY 1
7100 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
7101 struct intel_crtc_state *pipe_config)
7102 {
7103 struct drm_device *dev = intel_crtc->base.dev;
7104 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7105 int lane, link_bw, fdi_dotclock, ret;
7106 bool needs_recompute = false;
7107
7108 retry:
7109 /* FDI is a binary signal running at ~2.7GHz, encoding
7110 * each output octet as 10 bits. The actual frequency
7111 * is stored as a divider into a 100MHz clock, and the
7112 * mode pixel clock is stored in units of 1KHz.
7113 * Hence the bw of each lane in terms of the mode signal
7114 * is:
7115 */
7116 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
7117
7118 fdi_dotclock = adjusted_mode->crtc_clock;
7119
7120 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7121 pipe_config->pipe_bpp);
7122
7123 pipe_config->fdi_lanes = lane;
7124
7125 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7126 link_bw, &pipe_config->fdi_m_n);
7127
7128 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7129 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7130 pipe_config->pipe_bpp -= 2*3;
7131 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7132 pipe_config->pipe_bpp);
7133 needs_recompute = true;
7134 pipe_config->bw_constrained = true;
7135
7136 goto retry;
7137 }
7138
7139 if (needs_recompute)
7140 return RETRY;
7141
7142 return ret;
7143 }
7144
7145 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
7146 struct intel_crtc_state *pipe_config)
7147 {
7148 if (pipe_config->pipe_bpp > 24)
7149 return false;
7150
7151 /* HSW can handle pixel rate up to cdclk? */
7152 if (IS_HASWELL(dev_priv))
7153 return true;
7154
7155 /*
7156 * We compare against max which means we must take
7157 * the increased cdclk requirement into account when
7158 * calculating the new cdclk.
7159 *
7160 * Should measure whether using a lower cdclk w/o IPS
7161 */
7162 return ilk_pipe_pixel_rate(pipe_config) <=
7163 dev_priv->max_cdclk_freq * 95 / 100;
7164 }
7165
7166 static void hsw_compute_ips_config(struct intel_crtc *crtc,
7167 struct intel_crtc_state *pipe_config)
7168 {
7169 struct drm_device *dev = crtc->base.dev;
7170 struct drm_i915_private *dev_priv = to_i915(dev);
7171
7172 pipe_config->ips_enabled = i915.enable_ips &&
7173 hsw_crtc_supports_ips(crtc) &&
7174 pipe_config_supports_ips(dev_priv, pipe_config);
7175 }
7176
7177 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7178 {
7179 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7180
7181 /* GDG double wide on either pipe, otherwise pipe A only */
7182 return INTEL_INFO(dev_priv)->gen < 4 &&
7183 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7184 }
7185
7186 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7187 struct intel_crtc_state *pipe_config)
7188 {
7189 struct drm_device *dev = crtc->base.dev;
7190 struct drm_i915_private *dev_priv = to_i915(dev);
7191 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7192 int clock_limit = dev_priv->max_dotclk_freq;
7193
7194 if (INTEL_INFO(dev)->gen < 4) {
7195 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7196
7197 /*
7198 * Enable double wide mode when the dot clock
7199 * is > 90% of the (display) core speed.
7200 */
7201 if (intel_crtc_supports_double_wide(crtc) &&
7202 adjusted_mode->crtc_clock > clock_limit) {
7203 clock_limit = dev_priv->max_dotclk_freq;
7204 pipe_config->double_wide = true;
7205 }
7206 }
7207
7208 if (adjusted_mode->crtc_clock > clock_limit) {
7209 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7210 adjusted_mode->crtc_clock, clock_limit,
7211 yesno(pipe_config->double_wide));
7212 return -EINVAL;
7213 }
7214
7215 /*
7216 * Pipe horizontal size must be even in:
7217 * - DVO ganged mode
7218 * - LVDS dual channel mode
7219 * - Double wide pipe
7220 */
7221 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7222 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
7223 pipe_config->pipe_src_w &= ~1;
7224
7225 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7226 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7227 */
7228 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
7229 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7230 return -EINVAL;
7231
7232 if (HAS_IPS(dev))
7233 hsw_compute_ips_config(crtc, pipe_config);
7234
7235 if (pipe_config->has_pch_encoder)
7236 return ironlake_fdi_compute_config(crtc, pipe_config);
7237
7238 return 0;
7239 }
7240
7241 static int skylake_get_display_clock_speed(struct drm_device *dev)
7242 {
7243 struct drm_i915_private *dev_priv = to_i915(dev);
7244 uint32_t cdctl;
7245
7246 skl_dpll0_update(dev_priv);
7247
7248 if (dev_priv->cdclk_pll.vco == 0)
7249 return dev_priv->cdclk_pll.ref;
7250
7251 cdctl = I915_READ(CDCLK_CTL);
7252
7253 if (dev_priv->cdclk_pll.vco == 8640000) {
7254 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7255 case CDCLK_FREQ_450_432:
7256 return 432000;
7257 case CDCLK_FREQ_337_308:
7258 return 308571;
7259 case CDCLK_FREQ_540:
7260 return 540000;
7261 case CDCLK_FREQ_675_617:
7262 return 617143;
7263 default:
7264 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7265 }
7266 } else {
7267 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7268 case CDCLK_FREQ_450_432:
7269 return 450000;
7270 case CDCLK_FREQ_337_308:
7271 return 337500;
7272 case CDCLK_FREQ_540:
7273 return 540000;
7274 case CDCLK_FREQ_675_617:
7275 return 675000;
7276 default:
7277 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7278 }
7279 }
7280
7281 return dev_priv->cdclk_pll.ref;
7282 }
7283
7284 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
7285 {
7286 u32 val;
7287
7288 dev_priv->cdclk_pll.ref = 19200;
7289 dev_priv->cdclk_pll.vco = 0;
7290
7291 val = I915_READ(BXT_DE_PLL_ENABLE);
7292 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
7293 return;
7294
7295 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
7296 return;
7297
7298 val = I915_READ(BXT_DE_PLL_CTL);
7299 dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
7300 dev_priv->cdclk_pll.ref;
7301 }
7302
7303 static int broxton_get_display_clock_speed(struct drm_device *dev)
7304 {
7305 struct drm_i915_private *dev_priv = to_i915(dev);
7306 u32 divider;
7307 int div, vco;
7308
7309 bxt_de_pll_update(dev_priv);
7310
7311 vco = dev_priv->cdclk_pll.vco;
7312 if (vco == 0)
7313 return dev_priv->cdclk_pll.ref;
7314
7315 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
7316
7317 switch (divider) {
7318 case BXT_CDCLK_CD2X_DIV_SEL_1:
7319 div = 2;
7320 break;
7321 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
7322 div = 3;
7323 break;
7324 case BXT_CDCLK_CD2X_DIV_SEL_2:
7325 div = 4;
7326 break;
7327 case BXT_CDCLK_CD2X_DIV_SEL_4:
7328 div = 8;
7329 break;
7330 default:
7331 MISSING_CASE(divider);
7332 return dev_priv->cdclk_pll.ref;
7333 }
7334
7335 return DIV_ROUND_CLOSEST(vco, div);
7336 }
7337
7338 static int broadwell_get_display_clock_speed(struct drm_device *dev)
7339 {
7340 struct drm_i915_private *dev_priv = to_i915(dev);
7341 uint32_t lcpll = I915_READ(LCPLL_CTL);
7342 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7343
7344 if (lcpll & LCPLL_CD_SOURCE_FCLK)
7345 return 800000;
7346 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7347 return 450000;
7348 else if (freq == LCPLL_CLK_FREQ_450)
7349 return 450000;
7350 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
7351 return 540000;
7352 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
7353 return 337500;
7354 else
7355 return 675000;
7356 }
7357
7358 static int haswell_get_display_clock_speed(struct drm_device *dev)
7359 {
7360 struct drm_i915_private *dev_priv = to_i915(dev);
7361 uint32_t lcpll = I915_READ(LCPLL_CTL);
7362 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7363
7364 if (lcpll & LCPLL_CD_SOURCE_FCLK)
7365 return 800000;
7366 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7367 return 450000;
7368 else if (freq == LCPLL_CLK_FREQ_450)
7369 return 450000;
7370 else if (IS_HSW_ULT(dev))
7371 return 337500;
7372 else
7373 return 540000;
7374 }
7375
7376 static int valleyview_get_display_clock_speed(struct drm_device *dev)
7377 {
7378 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
7379 CCK_DISPLAY_CLOCK_CONTROL);
7380 }
7381
7382 static int ilk_get_display_clock_speed(struct drm_device *dev)
7383 {
7384 return 450000;
7385 }
7386
7387 static int i945_get_display_clock_speed(struct drm_device *dev)
7388 {
7389 return 400000;
7390 }
7391
7392 static int i915_get_display_clock_speed(struct drm_device *dev)
7393 {
7394 return 333333;
7395 }
7396
7397 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
7398 {
7399 return 200000;
7400 }
7401
7402 static int pnv_get_display_clock_speed(struct drm_device *dev)
7403 {
7404 struct pci_dev *pdev = dev->pdev;
7405 u16 gcfgc = 0;
7406
7407 pci_read_config_word(pdev, GCFGC, &gcfgc);
7408
7409 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7410 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
7411 return 266667;
7412 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
7413 return 333333;
7414 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
7415 return 444444;
7416 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
7417 return 200000;
7418 default:
7419 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
7420 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
7421 return 133333;
7422 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
7423 return 166667;
7424 }
7425 }
7426
7427 static int i915gm_get_display_clock_speed(struct drm_device *dev)
7428 {
7429 struct pci_dev *pdev = dev->pdev;
7430 u16 gcfgc = 0;
7431
7432 pci_read_config_word(pdev, GCFGC, &gcfgc);
7433
7434 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
7435 return 133333;
7436 else {
7437 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7438 case GC_DISPLAY_CLOCK_333_MHZ:
7439 return 333333;
7440 default:
7441 case GC_DISPLAY_CLOCK_190_200_MHZ:
7442 return 190000;
7443 }
7444 }
7445 }
7446
7447 static int i865_get_display_clock_speed(struct drm_device *dev)
7448 {
7449 return 266667;
7450 }
7451
7452 static int i85x_get_display_clock_speed(struct drm_device *dev)
7453 {
7454 struct pci_dev *pdev = dev->pdev;
7455 u16 hpllcc = 0;
7456
7457 /*
7458 * 852GM/852GMV only supports 133 MHz and the HPLLCC
7459 * encoding is different :(
7460 * FIXME is this the right way to detect 852GM/852GMV?
7461 */
7462 if (pdev->revision == 0x1)
7463 return 133333;
7464
7465 pci_bus_read_config_word(pdev->bus,
7466 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
7467
7468 /* Assume that the hardware is in the high speed state. This
7469 * should be the default.
7470 */
7471 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
7472 case GC_CLOCK_133_200:
7473 case GC_CLOCK_133_200_2:
7474 case GC_CLOCK_100_200:
7475 return 200000;
7476 case GC_CLOCK_166_250:
7477 return 250000;
7478 case GC_CLOCK_100_133:
7479 return 133333;
7480 case GC_CLOCK_133_266:
7481 case GC_CLOCK_133_266_2:
7482 case GC_CLOCK_166_266:
7483 return 266667;
7484 }
7485
7486 /* Shouldn't happen */
7487 return 0;
7488 }
7489
7490 static int i830_get_display_clock_speed(struct drm_device *dev)
7491 {
7492 return 133333;
7493 }
7494
7495 static unsigned int intel_hpll_vco(struct drm_device *dev)
7496 {
7497 struct drm_i915_private *dev_priv = to_i915(dev);
7498 static const unsigned int blb_vco[8] = {
7499 [0] = 3200000,
7500 [1] = 4000000,
7501 [2] = 5333333,
7502 [3] = 4800000,
7503 [4] = 6400000,
7504 };
7505 static const unsigned int pnv_vco[8] = {
7506 [0] = 3200000,
7507 [1] = 4000000,
7508 [2] = 5333333,
7509 [3] = 4800000,
7510 [4] = 2666667,
7511 };
7512 static const unsigned int cl_vco[8] = {
7513 [0] = 3200000,
7514 [1] = 4000000,
7515 [2] = 5333333,
7516 [3] = 6400000,
7517 [4] = 3333333,
7518 [5] = 3566667,
7519 [6] = 4266667,
7520 };
7521 static const unsigned int elk_vco[8] = {
7522 [0] = 3200000,
7523 [1] = 4000000,
7524 [2] = 5333333,
7525 [3] = 4800000,
7526 };
7527 static const unsigned int ctg_vco[8] = {
7528 [0] = 3200000,
7529 [1] = 4000000,
7530 [2] = 5333333,
7531 [3] = 6400000,
7532 [4] = 2666667,
7533 [5] = 4266667,
7534 };
7535 const unsigned int *vco_table;
7536 unsigned int vco;
7537 uint8_t tmp = 0;
7538
7539 /* FIXME other chipsets? */
7540 if (IS_GM45(dev))
7541 vco_table = ctg_vco;
7542 else if (IS_G4X(dev))
7543 vco_table = elk_vco;
7544 else if (IS_CRESTLINE(dev))
7545 vco_table = cl_vco;
7546 else if (IS_PINEVIEW(dev))
7547 vco_table = pnv_vco;
7548 else if (IS_G33(dev))
7549 vco_table = blb_vco;
7550 else
7551 return 0;
7552
7553 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7554
7555 vco = vco_table[tmp & 0x7];
7556 if (vco == 0)
7557 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7558 else
7559 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7560
7561 return vco;
7562 }
7563
7564 static int gm45_get_display_clock_speed(struct drm_device *dev)
7565 {
7566 struct pci_dev *pdev = dev->pdev;
7567 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7568 uint16_t tmp = 0;
7569
7570 pci_read_config_word(pdev, GCFGC, &tmp);
7571
7572 cdclk_sel = (tmp >> 12) & 0x1;
7573
7574 switch (vco) {
7575 case 2666667:
7576 case 4000000:
7577 case 5333333:
7578 return cdclk_sel ? 333333 : 222222;
7579 case 3200000:
7580 return cdclk_sel ? 320000 : 228571;
7581 default:
7582 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7583 return 222222;
7584 }
7585 }
7586
7587 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7588 {
7589 struct pci_dev *pdev = dev->pdev;
7590 static const uint8_t div_3200[] = { 16, 10, 8 };
7591 static const uint8_t div_4000[] = { 20, 12, 10 };
7592 static const uint8_t div_5333[] = { 24, 16, 14 };
7593 const uint8_t *div_table;
7594 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7595 uint16_t tmp = 0;
7596
7597 pci_read_config_word(pdev, GCFGC, &tmp);
7598
7599 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7600
7601 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7602 goto fail;
7603
7604 switch (vco) {
7605 case 3200000:
7606 div_table = div_3200;
7607 break;
7608 case 4000000:
7609 div_table = div_4000;
7610 break;
7611 case 5333333:
7612 div_table = div_5333;
7613 break;
7614 default:
7615 goto fail;
7616 }
7617
7618 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7619
7620 fail:
7621 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7622 return 200000;
7623 }
7624
7625 static int g33_get_display_clock_speed(struct drm_device *dev)
7626 {
7627 struct pci_dev *pdev = dev->pdev;
7628 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7629 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7630 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7631 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7632 const uint8_t *div_table;
7633 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7634 uint16_t tmp = 0;
7635
7636 pci_read_config_word(pdev, GCFGC, &tmp);
7637
7638 cdclk_sel = (tmp >> 4) & 0x7;
7639
7640 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7641 goto fail;
7642
7643 switch (vco) {
7644 case 3200000:
7645 div_table = div_3200;
7646 break;
7647 case 4000000:
7648 div_table = div_4000;
7649 break;
7650 case 4800000:
7651 div_table = div_4800;
7652 break;
7653 case 5333333:
7654 div_table = div_5333;
7655 break;
7656 default:
7657 goto fail;
7658 }
7659
7660 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7661
7662 fail:
7663 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7664 return 190476;
7665 }
7666
7667 static void
7668 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7669 {
7670 while (*num > DATA_LINK_M_N_MASK ||
7671 *den > DATA_LINK_M_N_MASK) {
7672 *num >>= 1;
7673 *den >>= 1;
7674 }
7675 }
7676
7677 static void compute_m_n(unsigned int m, unsigned int n,
7678 uint32_t *ret_m, uint32_t *ret_n)
7679 {
7680 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7681 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7682 intel_reduce_m_n_ratio(ret_m, ret_n);
7683 }
7684
7685 void
7686 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7687 int pixel_clock, int link_clock,
7688 struct intel_link_m_n *m_n)
7689 {
7690 m_n->tu = 64;
7691
7692 compute_m_n(bits_per_pixel * pixel_clock,
7693 link_clock * nlanes * 8,
7694 &m_n->gmch_m, &m_n->gmch_n);
7695
7696 compute_m_n(pixel_clock, link_clock,
7697 &m_n->link_m, &m_n->link_n);
7698 }
7699
7700 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7701 {
7702 if (i915.panel_use_ssc >= 0)
7703 return i915.panel_use_ssc != 0;
7704 return dev_priv->vbt.lvds_use_ssc
7705 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7706 }
7707
7708 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7709 {
7710 return (1 << dpll->n) << 16 | dpll->m2;
7711 }
7712
7713 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7714 {
7715 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7716 }
7717
7718 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7719 struct intel_crtc_state *crtc_state,
7720 struct dpll *reduced_clock)
7721 {
7722 struct drm_device *dev = crtc->base.dev;
7723 u32 fp, fp2 = 0;
7724
7725 if (IS_PINEVIEW(dev)) {
7726 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7727 if (reduced_clock)
7728 fp2 = pnv_dpll_compute_fp(reduced_clock);
7729 } else {
7730 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7731 if (reduced_clock)
7732 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7733 }
7734
7735 crtc_state->dpll_hw_state.fp0 = fp;
7736
7737 crtc->lowfreq_avail = false;
7738 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7739 reduced_clock) {
7740 crtc_state->dpll_hw_state.fp1 = fp2;
7741 crtc->lowfreq_avail = true;
7742 } else {
7743 crtc_state->dpll_hw_state.fp1 = fp;
7744 }
7745 }
7746
7747 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7748 pipe)
7749 {
7750 u32 reg_val;
7751
7752 /*
7753 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7754 * and set it to a reasonable value instead.
7755 */
7756 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7757 reg_val &= 0xffffff00;
7758 reg_val |= 0x00000030;
7759 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7760
7761 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7762 reg_val &= 0x8cffffff;
7763 reg_val = 0x8c000000;
7764 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7765
7766 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7767 reg_val &= 0xffffff00;
7768 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7769
7770 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7771 reg_val &= 0x00ffffff;
7772 reg_val |= 0xb0000000;
7773 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7774 }
7775
7776 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7777 struct intel_link_m_n *m_n)
7778 {
7779 struct drm_device *dev = crtc->base.dev;
7780 struct drm_i915_private *dev_priv = to_i915(dev);
7781 int pipe = crtc->pipe;
7782
7783 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7784 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7785 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7786 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7787 }
7788
7789 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7790 struct intel_link_m_n *m_n,
7791 struct intel_link_m_n *m2_n2)
7792 {
7793 struct drm_device *dev = crtc->base.dev;
7794 struct drm_i915_private *dev_priv = to_i915(dev);
7795 int pipe = crtc->pipe;
7796 enum transcoder transcoder = crtc->config->cpu_transcoder;
7797
7798 if (INTEL_INFO(dev)->gen >= 5) {
7799 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7800 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7801 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7802 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7803 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7804 * for gen < 8) and if DRRS is supported (to make sure the
7805 * registers are not unnecessarily accessed).
7806 */
7807 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7808 crtc->config->has_drrs) {
7809 I915_WRITE(PIPE_DATA_M2(transcoder),
7810 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7811 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7812 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7813 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7814 }
7815 } else {
7816 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7817 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7818 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7819 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7820 }
7821 }
7822
7823 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7824 {
7825 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7826
7827 if (m_n == M1_N1) {
7828 dp_m_n = &crtc->config->dp_m_n;
7829 dp_m2_n2 = &crtc->config->dp_m2_n2;
7830 } else if (m_n == M2_N2) {
7831
7832 /*
7833 * M2_N2 registers are not supported. Hence m2_n2 divider value
7834 * needs to be programmed into M1_N1.
7835 */
7836 dp_m_n = &crtc->config->dp_m2_n2;
7837 } else {
7838 DRM_ERROR("Unsupported divider value\n");
7839 return;
7840 }
7841
7842 if (crtc->config->has_pch_encoder)
7843 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7844 else
7845 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7846 }
7847
7848 static void vlv_compute_dpll(struct intel_crtc *crtc,
7849 struct intel_crtc_state *pipe_config)
7850 {
7851 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7852 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7853 if (crtc->pipe != PIPE_A)
7854 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7855
7856 /* DPLL not used with DSI, but still need the rest set up */
7857 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7858 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7859 DPLL_EXT_BUFFER_ENABLE_VLV;
7860
7861 pipe_config->dpll_hw_state.dpll_md =
7862 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7863 }
7864
7865 static void chv_compute_dpll(struct intel_crtc *crtc,
7866 struct intel_crtc_state *pipe_config)
7867 {
7868 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7869 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7870 if (crtc->pipe != PIPE_A)
7871 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7872
7873 /* DPLL not used with DSI, but still need the rest set up */
7874 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7875 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7876
7877 pipe_config->dpll_hw_state.dpll_md =
7878 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7879 }
7880
7881 static void vlv_prepare_pll(struct intel_crtc *crtc,
7882 const struct intel_crtc_state *pipe_config)
7883 {
7884 struct drm_device *dev = crtc->base.dev;
7885 struct drm_i915_private *dev_priv = to_i915(dev);
7886 enum pipe pipe = crtc->pipe;
7887 u32 mdiv;
7888 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7889 u32 coreclk, reg_val;
7890
7891 /* Enable Refclk */
7892 I915_WRITE(DPLL(pipe),
7893 pipe_config->dpll_hw_state.dpll &
7894 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7895
7896 /* No need to actually set up the DPLL with DSI */
7897 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7898 return;
7899
7900 mutex_lock(&dev_priv->sb_lock);
7901
7902 bestn = pipe_config->dpll.n;
7903 bestm1 = pipe_config->dpll.m1;
7904 bestm2 = pipe_config->dpll.m2;
7905 bestp1 = pipe_config->dpll.p1;
7906 bestp2 = pipe_config->dpll.p2;
7907
7908 /* See eDP HDMI DPIO driver vbios notes doc */
7909
7910 /* PLL B needs special handling */
7911 if (pipe == PIPE_B)
7912 vlv_pllb_recal_opamp(dev_priv, pipe);
7913
7914 /* Set up Tx target for periodic Rcomp update */
7915 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7916
7917 /* Disable target IRef on PLL */
7918 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7919 reg_val &= 0x00ffffff;
7920 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7921
7922 /* Disable fast lock */
7923 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7924
7925 /* Set idtafcrecal before PLL is enabled */
7926 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7927 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7928 mdiv |= ((bestn << DPIO_N_SHIFT));
7929 mdiv |= (1 << DPIO_K_SHIFT);
7930
7931 /*
7932 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7933 * but we don't support that).
7934 * Note: don't use the DAC post divider as it seems unstable.
7935 */
7936 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7937 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7938
7939 mdiv |= DPIO_ENABLE_CALIBRATION;
7940 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7941
7942 /* Set HBR and RBR LPF coefficients */
7943 if (pipe_config->port_clock == 162000 ||
7944 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
7945 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
7946 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7947 0x009f0003);
7948 else
7949 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7950 0x00d0000f);
7951
7952 if (intel_crtc_has_dp_encoder(pipe_config)) {
7953 /* Use SSC source */
7954 if (pipe == PIPE_A)
7955 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7956 0x0df40000);
7957 else
7958 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7959 0x0df70000);
7960 } else { /* HDMI or VGA */
7961 /* Use bend source */
7962 if (pipe == PIPE_A)
7963 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7964 0x0df70000);
7965 else
7966 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7967 0x0df40000);
7968 }
7969
7970 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7971 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7972 if (intel_crtc_has_dp_encoder(crtc->config))
7973 coreclk |= 0x01000000;
7974 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7975
7976 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7977 mutex_unlock(&dev_priv->sb_lock);
7978 }
7979
7980 static void chv_prepare_pll(struct intel_crtc *crtc,
7981 const struct intel_crtc_state *pipe_config)
7982 {
7983 struct drm_device *dev = crtc->base.dev;
7984 struct drm_i915_private *dev_priv = to_i915(dev);
7985 enum pipe pipe = crtc->pipe;
7986 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7987 u32 loopfilter, tribuf_calcntr;
7988 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7989 u32 dpio_val;
7990 int vco;
7991
7992 /* Enable Refclk and SSC */
7993 I915_WRITE(DPLL(pipe),
7994 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7995
7996 /* No need to actually set up the DPLL with DSI */
7997 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7998 return;
7999
8000 bestn = pipe_config->dpll.n;
8001 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
8002 bestm1 = pipe_config->dpll.m1;
8003 bestm2 = pipe_config->dpll.m2 >> 22;
8004 bestp1 = pipe_config->dpll.p1;
8005 bestp2 = pipe_config->dpll.p2;
8006 vco = pipe_config->dpll.vco;
8007 dpio_val = 0;
8008 loopfilter = 0;
8009
8010 mutex_lock(&dev_priv->sb_lock);
8011
8012 /* p1 and p2 divider */
8013 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8014 5 << DPIO_CHV_S1_DIV_SHIFT |
8015 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8016 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8017 1 << DPIO_CHV_K_DIV_SHIFT);
8018
8019 /* Feedback post-divider - m2 */
8020 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8021
8022 /* Feedback refclk divider - n and m1 */
8023 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8024 DPIO_CHV_M1_DIV_BY_2 |
8025 1 << DPIO_CHV_N_DIV_SHIFT);
8026
8027 /* M2 fraction division */
8028 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8029
8030 /* M2 fraction division enable */
8031 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8032 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8033 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8034 if (bestm2_frac)
8035 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8036 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8037
8038 /* Program digital lock detect threshold */
8039 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8040 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8041 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8042 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8043 if (!bestm2_frac)
8044 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8045 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8046
8047 /* Loop filter */
8048 if (vco == 5400000) {
8049 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8050 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8051 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8052 tribuf_calcntr = 0x9;
8053 } else if (vco <= 6200000) {
8054 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8055 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8056 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8057 tribuf_calcntr = 0x9;
8058 } else if (vco <= 6480000) {
8059 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8060 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8061 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8062 tribuf_calcntr = 0x8;
8063 } else {
8064 /* Not supported. Apply the same limits as in the max case */
8065 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8066 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8067 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8068 tribuf_calcntr = 0;
8069 }
8070 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8071
8072 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8073 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8074 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8075 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8076
8077 /* AFC Recal */
8078 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8079 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8080 DPIO_AFC_RECAL);
8081
8082 mutex_unlock(&dev_priv->sb_lock);
8083 }
8084
8085 /**
8086 * vlv_force_pll_on - forcibly enable just the PLL
8087 * @dev_priv: i915 private structure
8088 * @pipe: pipe PLL to enable
8089 * @dpll: PLL configuration
8090 *
8091 * Enable the PLL for @pipe using the supplied @dpll config. To be used
8092 * in cases where we need the PLL enabled even when @pipe is not going to
8093 * be enabled.
8094 */
8095 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
8096 const struct dpll *dpll)
8097 {
8098 struct intel_crtc *crtc =
8099 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
8100 struct intel_crtc_state *pipe_config;
8101
8102 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8103 if (!pipe_config)
8104 return -ENOMEM;
8105
8106 pipe_config->base.crtc = &crtc->base;
8107 pipe_config->pixel_multiplier = 1;
8108 pipe_config->dpll = *dpll;
8109
8110 if (IS_CHERRYVIEW(dev)) {
8111 chv_compute_dpll(crtc, pipe_config);
8112 chv_prepare_pll(crtc, pipe_config);
8113 chv_enable_pll(crtc, pipe_config);
8114 } else {
8115 vlv_compute_dpll(crtc, pipe_config);
8116 vlv_prepare_pll(crtc, pipe_config);
8117 vlv_enable_pll(crtc, pipe_config);
8118 }
8119
8120 kfree(pipe_config);
8121
8122 return 0;
8123 }
8124
8125 /**
8126 * vlv_force_pll_off - forcibly disable just the PLL
8127 * @dev_priv: i915 private structure
8128 * @pipe: pipe PLL to disable
8129 *
8130 * Disable the PLL for @pipe. To be used in cases where we need
8131 * the PLL enabled even when @pipe is not going to be enabled.
8132 */
8133 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
8134 {
8135 if (IS_CHERRYVIEW(dev))
8136 chv_disable_pll(to_i915(dev), pipe);
8137 else
8138 vlv_disable_pll(to_i915(dev), pipe);
8139 }
8140
8141 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8142 struct intel_crtc_state *crtc_state,
8143 struct dpll *reduced_clock)
8144 {
8145 struct drm_device *dev = crtc->base.dev;
8146 struct drm_i915_private *dev_priv = to_i915(dev);
8147 u32 dpll;
8148 struct dpll *clock = &crtc_state->dpll;
8149
8150 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8151
8152 dpll = DPLL_VGA_MODE_DIS;
8153
8154 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8155 dpll |= DPLLB_MODE_LVDS;
8156 else
8157 dpll |= DPLLB_MODE_DAC_SERIAL;
8158
8159 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8160 dpll |= (crtc_state->pixel_multiplier - 1)
8161 << SDVO_MULTIPLIER_SHIFT_HIRES;
8162 }
8163
8164 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8165 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8166 dpll |= DPLL_SDVO_HIGH_SPEED;
8167
8168 if (intel_crtc_has_dp_encoder(crtc_state))
8169 dpll |= DPLL_SDVO_HIGH_SPEED;
8170
8171 /* compute bitmask from p1 value */
8172 if (IS_PINEVIEW(dev))
8173 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8174 else {
8175 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8176 if (IS_G4X(dev) && reduced_clock)
8177 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8178 }
8179 switch (clock->p2) {
8180 case 5:
8181 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8182 break;
8183 case 7:
8184 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8185 break;
8186 case 10:
8187 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8188 break;
8189 case 14:
8190 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8191 break;
8192 }
8193 if (INTEL_INFO(dev)->gen >= 4)
8194 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8195
8196 if (crtc_state->sdvo_tv_clock)
8197 dpll |= PLL_REF_INPUT_TVCLKINBC;
8198 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8199 intel_panel_use_ssc(dev_priv))
8200 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8201 else
8202 dpll |= PLL_REF_INPUT_DREFCLK;
8203
8204 dpll |= DPLL_VCO_ENABLE;
8205 crtc_state->dpll_hw_state.dpll = dpll;
8206
8207 if (INTEL_INFO(dev)->gen >= 4) {
8208 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8209 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8210 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8211 }
8212 }
8213
8214 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8215 struct intel_crtc_state *crtc_state,
8216 struct dpll *reduced_clock)
8217 {
8218 struct drm_device *dev = crtc->base.dev;
8219 struct drm_i915_private *dev_priv = to_i915(dev);
8220 u32 dpll;
8221 struct dpll *clock = &crtc_state->dpll;
8222
8223 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8224
8225 dpll = DPLL_VGA_MODE_DIS;
8226
8227 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8228 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8229 } else {
8230 if (clock->p1 == 2)
8231 dpll |= PLL_P1_DIVIDE_BY_TWO;
8232 else
8233 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8234 if (clock->p2 == 4)
8235 dpll |= PLL_P2_DIVIDE_BY_4;
8236 }
8237
8238 if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8239 dpll |= DPLL_DVO_2X_MODE;
8240
8241 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8242 intel_panel_use_ssc(dev_priv))
8243 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8244 else
8245 dpll |= PLL_REF_INPUT_DREFCLK;
8246
8247 dpll |= DPLL_VCO_ENABLE;
8248 crtc_state->dpll_hw_state.dpll = dpll;
8249 }
8250
8251 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
8252 {
8253 struct drm_device *dev = intel_crtc->base.dev;
8254 struct drm_i915_private *dev_priv = to_i915(dev);
8255 enum pipe pipe = intel_crtc->pipe;
8256 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8257 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
8258 uint32_t crtc_vtotal, crtc_vblank_end;
8259 int vsyncshift = 0;
8260
8261 /* We need to be careful not to changed the adjusted mode, for otherwise
8262 * the hw state checker will get angry at the mismatch. */
8263 crtc_vtotal = adjusted_mode->crtc_vtotal;
8264 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8265
8266 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8267 /* the chip adds 2 halflines automatically */
8268 crtc_vtotal -= 1;
8269 crtc_vblank_end -= 1;
8270
8271 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8272 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8273 else
8274 vsyncshift = adjusted_mode->crtc_hsync_start -
8275 adjusted_mode->crtc_htotal / 2;
8276 if (vsyncshift < 0)
8277 vsyncshift += adjusted_mode->crtc_htotal;
8278 }
8279
8280 if (INTEL_INFO(dev)->gen > 3)
8281 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8282
8283 I915_WRITE(HTOTAL(cpu_transcoder),
8284 (adjusted_mode->crtc_hdisplay - 1) |
8285 ((adjusted_mode->crtc_htotal - 1) << 16));
8286 I915_WRITE(HBLANK(cpu_transcoder),
8287 (adjusted_mode->crtc_hblank_start - 1) |
8288 ((adjusted_mode->crtc_hblank_end - 1) << 16));
8289 I915_WRITE(HSYNC(cpu_transcoder),
8290 (adjusted_mode->crtc_hsync_start - 1) |
8291 ((adjusted_mode->crtc_hsync_end - 1) << 16));
8292
8293 I915_WRITE(VTOTAL(cpu_transcoder),
8294 (adjusted_mode->crtc_vdisplay - 1) |
8295 ((crtc_vtotal - 1) << 16));
8296 I915_WRITE(VBLANK(cpu_transcoder),
8297 (adjusted_mode->crtc_vblank_start - 1) |
8298 ((crtc_vblank_end - 1) << 16));
8299 I915_WRITE(VSYNC(cpu_transcoder),
8300 (adjusted_mode->crtc_vsync_start - 1) |
8301 ((adjusted_mode->crtc_vsync_end - 1) << 16));
8302
8303 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8304 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8305 * documented on the DDI_FUNC_CTL register description, EDP Input Select
8306 * bits. */
8307 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
8308 (pipe == PIPE_B || pipe == PIPE_C))
8309 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8310
8311 }
8312
8313 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
8314 {
8315 struct drm_device *dev = intel_crtc->base.dev;
8316 struct drm_i915_private *dev_priv = to_i915(dev);
8317 enum pipe pipe = intel_crtc->pipe;
8318
8319 /* pipesrc controls the size that is scaled from, which should
8320 * always be the user's requested size.
8321 */
8322 I915_WRITE(PIPESRC(pipe),
8323 ((intel_crtc->config->pipe_src_w - 1) << 16) |
8324 (intel_crtc->config->pipe_src_h - 1));
8325 }
8326
8327 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8328 struct intel_crtc_state *pipe_config)
8329 {
8330 struct drm_device *dev = crtc->base.dev;
8331 struct drm_i915_private *dev_priv = to_i915(dev);
8332 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8333 uint32_t tmp;
8334
8335 tmp = I915_READ(HTOTAL(cpu_transcoder));
8336 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8337 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8338 tmp = I915_READ(HBLANK(cpu_transcoder));
8339 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
8340 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
8341 tmp = I915_READ(HSYNC(cpu_transcoder));
8342 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8343 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8344
8345 tmp = I915_READ(VTOTAL(cpu_transcoder));
8346 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8347 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8348 tmp = I915_READ(VBLANK(cpu_transcoder));
8349 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
8350 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
8351 tmp = I915_READ(VSYNC(cpu_transcoder));
8352 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8353 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8354
8355 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
8356 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8357 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
8358 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
8359 }
8360 }
8361
8362 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8363 struct intel_crtc_state *pipe_config)
8364 {
8365 struct drm_device *dev = crtc->base.dev;
8366 struct drm_i915_private *dev_priv = to_i915(dev);
8367 u32 tmp;
8368
8369 tmp = I915_READ(PIPESRC(crtc->pipe));
8370 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8371 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8372
8373 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
8374 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
8375 }
8376
8377 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8378 struct intel_crtc_state *pipe_config)
8379 {
8380 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
8381 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
8382 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
8383 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
8384
8385 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
8386 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
8387 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
8388 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
8389
8390 mode->flags = pipe_config->base.adjusted_mode.flags;
8391 mode->type = DRM_MODE_TYPE_DRIVER;
8392
8393 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
8394 mode->flags |= pipe_config->base.adjusted_mode.flags;
8395
8396 mode->hsync = drm_mode_hsync(mode);
8397 mode->vrefresh = drm_mode_vrefresh(mode);
8398 drm_mode_set_name(mode);
8399 }
8400
8401 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
8402 {
8403 struct drm_device *dev = intel_crtc->base.dev;
8404 struct drm_i915_private *dev_priv = to_i915(dev);
8405 uint32_t pipeconf;
8406
8407 pipeconf = 0;
8408
8409 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
8410 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8411 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
8412
8413 if (intel_crtc->config->double_wide)
8414 pipeconf |= PIPECONF_DOUBLE_WIDE;
8415
8416 /* only g4x and later have fancy bpc/dither controls */
8417 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8418 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8419 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
8420 pipeconf |= PIPECONF_DITHER_EN |
8421 PIPECONF_DITHER_TYPE_SP;
8422
8423 switch (intel_crtc->config->pipe_bpp) {
8424 case 18:
8425 pipeconf |= PIPECONF_6BPC;
8426 break;
8427 case 24:
8428 pipeconf |= PIPECONF_8BPC;
8429 break;
8430 case 30:
8431 pipeconf |= PIPECONF_10BPC;
8432 break;
8433 default:
8434 /* Case prevented by intel_choose_pipe_bpp_dither. */
8435 BUG();
8436 }
8437 }
8438
8439 if (HAS_PIPE_CXSR(dev)) {
8440 if (intel_crtc->lowfreq_avail) {
8441 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
8442 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
8443 } else {
8444 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
8445 }
8446 }
8447
8448 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8449 if (INTEL_INFO(dev)->gen < 4 ||
8450 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8451 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8452 else
8453 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8454 } else
8455 pipeconf |= PIPECONF_PROGRESSIVE;
8456
8457 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8458 intel_crtc->config->limited_color_range)
8459 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8460
8461 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
8462 POSTING_READ(PIPECONF(intel_crtc->pipe));
8463 }
8464
8465 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8466 struct intel_crtc_state *crtc_state)
8467 {
8468 struct drm_device *dev = crtc->base.dev;
8469 struct drm_i915_private *dev_priv = to_i915(dev);
8470 const struct intel_limit *limit;
8471 int refclk = 48000;
8472
8473 memset(&crtc_state->dpll_hw_state, 0,
8474 sizeof(crtc_state->dpll_hw_state));
8475
8476 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8477 if (intel_panel_use_ssc(dev_priv)) {
8478 refclk = dev_priv->vbt.lvds_ssc_freq;
8479 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8480 }
8481
8482 limit = &intel_limits_i8xx_lvds;
8483 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8484 limit = &intel_limits_i8xx_dvo;
8485 } else {
8486 limit = &intel_limits_i8xx_dac;
8487 }
8488
8489 if (!crtc_state->clock_set &&
8490 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8491 refclk, NULL, &crtc_state->dpll)) {
8492 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8493 return -EINVAL;
8494 }
8495
8496 i8xx_compute_dpll(crtc, crtc_state, NULL);
8497
8498 return 0;
8499 }
8500
8501 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8502 struct intel_crtc_state *crtc_state)
8503 {
8504 struct drm_device *dev = crtc->base.dev;
8505 struct drm_i915_private *dev_priv = to_i915(dev);
8506 const struct intel_limit *limit;
8507 int refclk = 96000;
8508
8509 memset(&crtc_state->dpll_hw_state, 0,
8510 sizeof(crtc_state->dpll_hw_state));
8511
8512 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8513 if (intel_panel_use_ssc(dev_priv)) {
8514 refclk = dev_priv->vbt.lvds_ssc_freq;
8515 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8516 }
8517
8518 if (intel_is_dual_link_lvds(dev))
8519 limit = &intel_limits_g4x_dual_channel_lvds;
8520 else
8521 limit = &intel_limits_g4x_single_channel_lvds;
8522 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8523 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8524 limit = &intel_limits_g4x_hdmi;
8525 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8526 limit = &intel_limits_g4x_sdvo;
8527 } else {
8528 /* The option is for other outputs */
8529 limit = &intel_limits_i9xx_sdvo;
8530 }
8531
8532 if (!crtc_state->clock_set &&
8533 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8534 refclk, NULL, &crtc_state->dpll)) {
8535 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8536 return -EINVAL;
8537 }
8538
8539 i9xx_compute_dpll(crtc, crtc_state, NULL);
8540
8541 return 0;
8542 }
8543
8544 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8545 struct intel_crtc_state *crtc_state)
8546 {
8547 struct drm_device *dev = crtc->base.dev;
8548 struct drm_i915_private *dev_priv = to_i915(dev);
8549 const struct intel_limit *limit;
8550 int refclk = 96000;
8551
8552 memset(&crtc_state->dpll_hw_state, 0,
8553 sizeof(crtc_state->dpll_hw_state));
8554
8555 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8556 if (intel_panel_use_ssc(dev_priv)) {
8557 refclk = dev_priv->vbt.lvds_ssc_freq;
8558 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8559 }
8560
8561 limit = &intel_limits_pineview_lvds;
8562 } else {
8563 limit = &intel_limits_pineview_sdvo;
8564 }
8565
8566 if (!crtc_state->clock_set &&
8567 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8568 refclk, NULL, &crtc_state->dpll)) {
8569 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8570 return -EINVAL;
8571 }
8572
8573 i9xx_compute_dpll(crtc, crtc_state, NULL);
8574
8575 return 0;
8576 }
8577
8578 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8579 struct intel_crtc_state *crtc_state)
8580 {
8581 struct drm_device *dev = crtc->base.dev;
8582 struct drm_i915_private *dev_priv = to_i915(dev);
8583 const struct intel_limit *limit;
8584 int refclk = 96000;
8585
8586 memset(&crtc_state->dpll_hw_state, 0,
8587 sizeof(crtc_state->dpll_hw_state));
8588
8589 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8590 if (intel_panel_use_ssc(dev_priv)) {
8591 refclk = dev_priv->vbt.lvds_ssc_freq;
8592 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8593 }
8594
8595 limit = &intel_limits_i9xx_lvds;
8596 } else {
8597 limit = &intel_limits_i9xx_sdvo;
8598 }
8599
8600 if (!crtc_state->clock_set &&
8601 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8602 refclk, NULL, &crtc_state->dpll)) {
8603 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8604 return -EINVAL;
8605 }
8606
8607 i9xx_compute_dpll(crtc, crtc_state, NULL);
8608
8609 return 0;
8610 }
8611
8612 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8613 struct intel_crtc_state *crtc_state)
8614 {
8615 int refclk = 100000;
8616 const struct intel_limit *limit = &intel_limits_chv;
8617
8618 memset(&crtc_state->dpll_hw_state, 0,
8619 sizeof(crtc_state->dpll_hw_state));
8620
8621 if (!crtc_state->clock_set &&
8622 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8623 refclk, NULL, &crtc_state->dpll)) {
8624 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8625 return -EINVAL;
8626 }
8627
8628 chv_compute_dpll(crtc, crtc_state);
8629
8630 return 0;
8631 }
8632
8633 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8634 struct intel_crtc_state *crtc_state)
8635 {
8636 int refclk = 100000;
8637 const struct intel_limit *limit = &intel_limits_vlv;
8638
8639 memset(&crtc_state->dpll_hw_state, 0,
8640 sizeof(crtc_state->dpll_hw_state));
8641
8642 if (!crtc_state->clock_set &&
8643 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8644 refclk, NULL, &crtc_state->dpll)) {
8645 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8646 return -EINVAL;
8647 }
8648
8649 vlv_compute_dpll(crtc, crtc_state);
8650
8651 return 0;
8652 }
8653
8654 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8655 struct intel_crtc_state *pipe_config)
8656 {
8657 struct drm_device *dev = crtc->base.dev;
8658 struct drm_i915_private *dev_priv = to_i915(dev);
8659 uint32_t tmp;
8660
8661 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8662 return;
8663
8664 tmp = I915_READ(PFIT_CONTROL);
8665 if (!(tmp & PFIT_ENABLE))
8666 return;
8667
8668 /* Check whether the pfit is attached to our pipe. */
8669 if (INTEL_INFO(dev)->gen < 4) {
8670 if (crtc->pipe != PIPE_B)
8671 return;
8672 } else {
8673 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8674 return;
8675 }
8676
8677 pipe_config->gmch_pfit.control = tmp;
8678 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8679 }
8680
8681 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8682 struct intel_crtc_state *pipe_config)
8683 {
8684 struct drm_device *dev = crtc->base.dev;
8685 struct drm_i915_private *dev_priv = to_i915(dev);
8686 int pipe = pipe_config->cpu_transcoder;
8687 struct dpll clock;
8688 u32 mdiv;
8689 int refclk = 100000;
8690
8691 /* In case of DSI, DPLL will not be used */
8692 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8693 return;
8694
8695 mutex_lock(&dev_priv->sb_lock);
8696 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8697 mutex_unlock(&dev_priv->sb_lock);
8698
8699 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8700 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8701 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8702 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8703 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8704
8705 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8706 }
8707
8708 static void
8709 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8710 struct intel_initial_plane_config *plane_config)
8711 {
8712 struct drm_device *dev = crtc->base.dev;
8713 struct drm_i915_private *dev_priv = to_i915(dev);
8714 u32 val, base, offset;
8715 int pipe = crtc->pipe, plane = crtc->plane;
8716 int fourcc, pixel_format;
8717 unsigned int aligned_height;
8718 struct drm_framebuffer *fb;
8719 struct intel_framebuffer *intel_fb;
8720
8721 val = I915_READ(DSPCNTR(plane));
8722 if (!(val & DISPLAY_PLANE_ENABLE))
8723 return;
8724
8725 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8726 if (!intel_fb) {
8727 DRM_DEBUG_KMS("failed to alloc fb\n");
8728 return;
8729 }
8730
8731 fb = &intel_fb->base;
8732
8733 if (INTEL_INFO(dev)->gen >= 4) {
8734 if (val & DISPPLANE_TILED) {
8735 plane_config->tiling = I915_TILING_X;
8736 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8737 }
8738 }
8739
8740 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8741 fourcc = i9xx_format_to_fourcc(pixel_format);
8742 fb->pixel_format = fourcc;
8743 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8744
8745 if (INTEL_INFO(dev)->gen >= 4) {
8746 if (plane_config->tiling)
8747 offset = I915_READ(DSPTILEOFF(plane));
8748 else
8749 offset = I915_READ(DSPLINOFF(plane));
8750 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8751 } else {
8752 base = I915_READ(DSPADDR(plane));
8753 }
8754 plane_config->base = base;
8755
8756 val = I915_READ(PIPESRC(pipe));
8757 fb->width = ((val >> 16) & 0xfff) + 1;
8758 fb->height = ((val >> 0) & 0xfff) + 1;
8759
8760 val = I915_READ(DSPSTRIDE(pipe));
8761 fb->pitches[0] = val & 0xffffffc0;
8762
8763 aligned_height = intel_fb_align_height(dev, fb->height,
8764 fb->pixel_format,
8765 fb->modifier[0]);
8766
8767 plane_config->size = fb->pitches[0] * aligned_height;
8768
8769 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8770 pipe_name(pipe), plane, fb->width, fb->height,
8771 fb->bits_per_pixel, base, fb->pitches[0],
8772 plane_config->size);
8773
8774 plane_config->fb = intel_fb;
8775 }
8776
8777 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8778 struct intel_crtc_state *pipe_config)
8779 {
8780 struct drm_device *dev = crtc->base.dev;
8781 struct drm_i915_private *dev_priv = to_i915(dev);
8782 int pipe = pipe_config->cpu_transcoder;
8783 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8784 struct dpll clock;
8785 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8786 int refclk = 100000;
8787
8788 /* In case of DSI, DPLL will not be used */
8789 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8790 return;
8791
8792 mutex_lock(&dev_priv->sb_lock);
8793 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8794 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8795 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8796 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8797 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8798 mutex_unlock(&dev_priv->sb_lock);
8799
8800 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8801 clock.m2 = (pll_dw0 & 0xff) << 22;
8802 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8803 clock.m2 |= pll_dw2 & 0x3fffff;
8804 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8805 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8806 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8807
8808 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8809 }
8810
8811 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8812 struct intel_crtc_state *pipe_config)
8813 {
8814 struct drm_device *dev = crtc->base.dev;
8815 struct drm_i915_private *dev_priv = to_i915(dev);
8816 enum intel_display_power_domain power_domain;
8817 uint32_t tmp;
8818 bool ret;
8819
8820 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8821 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8822 return false;
8823
8824 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8825 pipe_config->shared_dpll = NULL;
8826
8827 ret = false;
8828
8829 tmp = I915_READ(PIPECONF(crtc->pipe));
8830 if (!(tmp & PIPECONF_ENABLE))
8831 goto out;
8832
8833 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8834 switch (tmp & PIPECONF_BPC_MASK) {
8835 case PIPECONF_6BPC:
8836 pipe_config->pipe_bpp = 18;
8837 break;
8838 case PIPECONF_8BPC:
8839 pipe_config->pipe_bpp = 24;
8840 break;
8841 case PIPECONF_10BPC:
8842 pipe_config->pipe_bpp = 30;
8843 break;
8844 default:
8845 break;
8846 }
8847 }
8848
8849 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8850 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8851 pipe_config->limited_color_range = true;
8852
8853 if (INTEL_INFO(dev)->gen < 4)
8854 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8855
8856 intel_get_pipe_timings(crtc, pipe_config);
8857 intel_get_pipe_src_size(crtc, pipe_config);
8858
8859 i9xx_get_pfit_config(crtc, pipe_config);
8860
8861 if (INTEL_INFO(dev)->gen >= 4) {
8862 /* No way to read it out on pipes B and C */
8863 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8864 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8865 else
8866 tmp = I915_READ(DPLL_MD(crtc->pipe));
8867 pipe_config->pixel_multiplier =
8868 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8869 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8870 pipe_config->dpll_hw_state.dpll_md = tmp;
8871 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8872 tmp = I915_READ(DPLL(crtc->pipe));
8873 pipe_config->pixel_multiplier =
8874 ((tmp & SDVO_MULTIPLIER_MASK)
8875 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8876 } else {
8877 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8878 * port and will be fixed up in the encoder->get_config
8879 * function. */
8880 pipe_config->pixel_multiplier = 1;
8881 }
8882 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8883 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8884 /*
8885 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8886 * on 830. Filter it out here so that we don't
8887 * report errors due to that.
8888 */
8889 if (IS_I830(dev))
8890 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8891
8892 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8893 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8894 } else {
8895 /* Mask out read-only status bits. */
8896 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8897 DPLL_PORTC_READY_MASK |
8898 DPLL_PORTB_READY_MASK);
8899 }
8900
8901 if (IS_CHERRYVIEW(dev))
8902 chv_crtc_clock_get(crtc, pipe_config);
8903 else if (IS_VALLEYVIEW(dev))
8904 vlv_crtc_clock_get(crtc, pipe_config);
8905 else
8906 i9xx_crtc_clock_get(crtc, pipe_config);
8907
8908 /*
8909 * Normally the dotclock is filled in by the encoder .get_config()
8910 * but in case the pipe is enabled w/o any ports we need a sane
8911 * default.
8912 */
8913 pipe_config->base.adjusted_mode.crtc_clock =
8914 pipe_config->port_clock / pipe_config->pixel_multiplier;
8915
8916 ret = true;
8917
8918 out:
8919 intel_display_power_put(dev_priv, power_domain);
8920
8921 return ret;
8922 }
8923
8924 static void ironlake_init_pch_refclk(struct drm_device *dev)
8925 {
8926 struct drm_i915_private *dev_priv = to_i915(dev);
8927 struct intel_encoder *encoder;
8928 int i;
8929 u32 val, final;
8930 bool has_lvds = false;
8931 bool has_cpu_edp = false;
8932 bool has_panel = false;
8933 bool has_ck505 = false;
8934 bool can_ssc = false;
8935 bool using_ssc_source = false;
8936
8937 /* We need to take the global config into account */
8938 for_each_intel_encoder(dev, encoder) {
8939 switch (encoder->type) {
8940 case INTEL_OUTPUT_LVDS:
8941 has_panel = true;
8942 has_lvds = true;
8943 break;
8944 case INTEL_OUTPUT_EDP:
8945 has_panel = true;
8946 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8947 has_cpu_edp = true;
8948 break;
8949 default:
8950 break;
8951 }
8952 }
8953
8954 if (HAS_PCH_IBX(dev)) {
8955 has_ck505 = dev_priv->vbt.display_clock_mode;
8956 can_ssc = has_ck505;
8957 } else {
8958 has_ck505 = false;
8959 can_ssc = true;
8960 }
8961
8962 /* Check if any DPLLs are using the SSC source */
8963 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8964 u32 temp = I915_READ(PCH_DPLL(i));
8965
8966 if (!(temp & DPLL_VCO_ENABLE))
8967 continue;
8968
8969 if ((temp & PLL_REF_INPUT_MASK) ==
8970 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8971 using_ssc_source = true;
8972 break;
8973 }
8974 }
8975
8976 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8977 has_panel, has_lvds, has_ck505, using_ssc_source);
8978
8979 /* Ironlake: try to setup display ref clock before DPLL
8980 * enabling. This is only under driver's control after
8981 * PCH B stepping, previous chipset stepping should be
8982 * ignoring this setting.
8983 */
8984 val = I915_READ(PCH_DREF_CONTROL);
8985
8986 /* As we must carefully and slowly disable/enable each source in turn,
8987 * compute the final state we want first and check if we need to
8988 * make any changes at all.
8989 */
8990 final = val;
8991 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8992 if (has_ck505)
8993 final |= DREF_NONSPREAD_CK505_ENABLE;
8994 else
8995 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8996
8997 final &= ~DREF_SSC_SOURCE_MASK;
8998 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8999 final &= ~DREF_SSC1_ENABLE;
9000
9001 if (has_panel) {
9002 final |= DREF_SSC_SOURCE_ENABLE;
9003
9004 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9005 final |= DREF_SSC1_ENABLE;
9006
9007 if (has_cpu_edp) {
9008 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9009 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9010 else
9011 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9012 } else
9013 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9014 } else if (using_ssc_source) {
9015 final |= DREF_SSC_SOURCE_ENABLE;
9016 final |= DREF_SSC1_ENABLE;
9017 }
9018
9019 if (final == val)
9020 return;
9021
9022 /* Always enable nonspread source */
9023 val &= ~DREF_NONSPREAD_SOURCE_MASK;
9024
9025 if (has_ck505)
9026 val |= DREF_NONSPREAD_CK505_ENABLE;
9027 else
9028 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9029
9030 if (has_panel) {
9031 val &= ~DREF_SSC_SOURCE_MASK;
9032 val |= DREF_SSC_SOURCE_ENABLE;
9033
9034 /* SSC must be turned on before enabling the CPU output */
9035 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9036 DRM_DEBUG_KMS("Using SSC on panel\n");
9037 val |= DREF_SSC1_ENABLE;
9038 } else
9039 val &= ~DREF_SSC1_ENABLE;
9040
9041 /* Get SSC going before enabling the outputs */
9042 I915_WRITE(PCH_DREF_CONTROL, val);
9043 POSTING_READ(PCH_DREF_CONTROL);
9044 udelay(200);
9045
9046 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9047
9048 /* Enable CPU source on CPU attached eDP */
9049 if (has_cpu_edp) {
9050 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9051 DRM_DEBUG_KMS("Using SSC on eDP\n");
9052 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9053 } else
9054 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9055 } else
9056 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9057
9058 I915_WRITE(PCH_DREF_CONTROL, val);
9059 POSTING_READ(PCH_DREF_CONTROL);
9060 udelay(200);
9061 } else {
9062 DRM_DEBUG_KMS("Disabling CPU source output\n");
9063
9064 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9065
9066 /* Turn off CPU output */
9067 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9068
9069 I915_WRITE(PCH_DREF_CONTROL, val);
9070 POSTING_READ(PCH_DREF_CONTROL);
9071 udelay(200);
9072
9073 if (!using_ssc_source) {
9074 DRM_DEBUG_KMS("Disabling SSC source\n");
9075
9076 /* Turn off the SSC source */
9077 val &= ~DREF_SSC_SOURCE_MASK;
9078 val |= DREF_SSC_SOURCE_DISABLE;
9079
9080 /* Turn off SSC1 */
9081 val &= ~DREF_SSC1_ENABLE;
9082
9083 I915_WRITE(PCH_DREF_CONTROL, val);
9084 POSTING_READ(PCH_DREF_CONTROL);
9085 udelay(200);
9086 }
9087 }
9088
9089 BUG_ON(val != final);
9090 }
9091
9092 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9093 {
9094 uint32_t tmp;
9095
9096 tmp = I915_READ(SOUTH_CHICKEN2);
9097 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9098 I915_WRITE(SOUTH_CHICKEN2, tmp);
9099
9100 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
9101 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9102 DRM_ERROR("FDI mPHY reset assert timeout\n");
9103
9104 tmp = I915_READ(SOUTH_CHICKEN2);
9105 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9106 I915_WRITE(SOUTH_CHICKEN2, tmp);
9107
9108 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
9109 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9110 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9111 }
9112
9113 /* WaMPhyProgramming:hsw */
9114 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9115 {
9116 uint32_t tmp;
9117
9118 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9119 tmp &= ~(0xFF << 24);
9120 tmp |= (0x12 << 24);
9121 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9122
9123 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9124 tmp |= (1 << 11);
9125 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9126
9127 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9128 tmp |= (1 << 11);
9129 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9130
9131 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9132 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9133 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9134
9135 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9136 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9137 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9138
9139 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9140 tmp &= ~(7 << 13);
9141 tmp |= (5 << 13);
9142 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9143
9144 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9145 tmp &= ~(7 << 13);
9146 tmp |= (5 << 13);
9147 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9148
9149 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9150 tmp &= ~0xFF;
9151 tmp |= 0x1C;
9152 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9153
9154 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9155 tmp &= ~0xFF;
9156 tmp |= 0x1C;
9157 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9158
9159 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9160 tmp &= ~(0xFF << 16);
9161 tmp |= (0x1C << 16);
9162 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9163
9164 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9165 tmp &= ~(0xFF << 16);
9166 tmp |= (0x1C << 16);
9167 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9168
9169 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9170 tmp |= (1 << 27);
9171 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9172
9173 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9174 tmp |= (1 << 27);
9175 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9176
9177 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9178 tmp &= ~(0xF << 28);
9179 tmp |= (4 << 28);
9180 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9181
9182 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9183 tmp &= ~(0xF << 28);
9184 tmp |= (4 << 28);
9185 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9186 }
9187
9188 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9189 * Programming" based on the parameters passed:
9190 * - Sequence to enable CLKOUT_DP
9191 * - Sequence to enable CLKOUT_DP without spread
9192 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9193 */
9194 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
9195 bool with_fdi)
9196 {
9197 struct drm_i915_private *dev_priv = to_i915(dev);
9198 uint32_t reg, tmp;
9199
9200 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9201 with_spread = true;
9202 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
9203 with_fdi = false;
9204
9205 mutex_lock(&dev_priv->sb_lock);
9206
9207 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9208 tmp &= ~SBI_SSCCTL_DISABLE;
9209 tmp |= SBI_SSCCTL_PATHALT;
9210 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9211
9212 udelay(24);
9213
9214 if (with_spread) {
9215 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9216 tmp &= ~SBI_SSCCTL_PATHALT;
9217 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9218
9219 if (with_fdi) {
9220 lpt_reset_fdi_mphy(dev_priv);
9221 lpt_program_fdi_mphy(dev_priv);
9222 }
9223 }
9224
9225 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
9226 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9227 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9228 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9229
9230 mutex_unlock(&dev_priv->sb_lock);
9231 }
9232
9233 /* Sequence to disable CLKOUT_DP */
9234 static void lpt_disable_clkout_dp(struct drm_device *dev)
9235 {
9236 struct drm_i915_private *dev_priv = to_i915(dev);
9237 uint32_t reg, tmp;
9238
9239 mutex_lock(&dev_priv->sb_lock);
9240
9241 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
9242 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9243 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9244 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9245
9246 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9247 if (!(tmp & SBI_SSCCTL_DISABLE)) {
9248 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9249 tmp |= SBI_SSCCTL_PATHALT;
9250 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9251 udelay(32);
9252 }
9253 tmp |= SBI_SSCCTL_DISABLE;
9254 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9255 }
9256
9257 mutex_unlock(&dev_priv->sb_lock);
9258 }
9259
9260 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9261
9262 static const uint16_t sscdivintphase[] = {
9263 [BEND_IDX( 50)] = 0x3B23,
9264 [BEND_IDX( 45)] = 0x3B23,
9265 [BEND_IDX( 40)] = 0x3C23,
9266 [BEND_IDX( 35)] = 0x3C23,
9267 [BEND_IDX( 30)] = 0x3D23,
9268 [BEND_IDX( 25)] = 0x3D23,
9269 [BEND_IDX( 20)] = 0x3E23,
9270 [BEND_IDX( 15)] = 0x3E23,
9271 [BEND_IDX( 10)] = 0x3F23,
9272 [BEND_IDX( 5)] = 0x3F23,
9273 [BEND_IDX( 0)] = 0x0025,
9274 [BEND_IDX( -5)] = 0x0025,
9275 [BEND_IDX(-10)] = 0x0125,
9276 [BEND_IDX(-15)] = 0x0125,
9277 [BEND_IDX(-20)] = 0x0225,
9278 [BEND_IDX(-25)] = 0x0225,
9279 [BEND_IDX(-30)] = 0x0325,
9280 [BEND_IDX(-35)] = 0x0325,
9281 [BEND_IDX(-40)] = 0x0425,
9282 [BEND_IDX(-45)] = 0x0425,
9283 [BEND_IDX(-50)] = 0x0525,
9284 };
9285
9286 /*
9287 * Bend CLKOUT_DP
9288 * steps -50 to 50 inclusive, in steps of 5
9289 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9290 * change in clock period = -(steps / 10) * 5.787 ps
9291 */
9292 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9293 {
9294 uint32_t tmp;
9295 int idx = BEND_IDX(steps);
9296
9297 if (WARN_ON(steps % 5 != 0))
9298 return;
9299
9300 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9301 return;
9302
9303 mutex_lock(&dev_priv->sb_lock);
9304
9305 if (steps % 10 != 0)
9306 tmp = 0xAAAAAAAB;
9307 else
9308 tmp = 0x00000000;
9309 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9310
9311 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9312 tmp &= 0xffff0000;
9313 tmp |= sscdivintphase[idx];
9314 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9315
9316 mutex_unlock(&dev_priv->sb_lock);
9317 }
9318
9319 #undef BEND_IDX
9320
9321 static void lpt_init_pch_refclk(struct drm_device *dev)
9322 {
9323 struct intel_encoder *encoder;
9324 bool has_vga = false;
9325
9326 for_each_intel_encoder(dev, encoder) {
9327 switch (encoder->type) {
9328 case INTEL_OUTPUT_ANALOG:
9329 has_vga = true;
9330 break;
9331 default:
9332 break;
9333 }
9334 }
9335
9336 if (has_vga) {
9337 lpt_bend_clkout_dp(to_i915(dev), 0);
9338 lpt_enable_clkout_dp(dev, true, true);
9339 } else {
9340 lpt_disable_clkout_dp(dev);
9341 }
9342 }
9343
9344 /*
9345 * Initialize reference clocks when the driver loads
9346 */
9347 void intel_init_pch_refclk(struct drm_device *dev)
9348 {
9349 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9350 ironlake_init_pch_refclk(dev);
9351 else if (HAS_PCH_LPT(dev))
9352 lpt_init_pch_refclk(dev);
9353 }
9354
9355 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
9356 {
9357 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9359 int pipe = intel_crtc->pipe;
9360 uint32_t val;
9361
9362 val = 0;
9363
9364 switch (intel_crtc->config->pipe_bpp) {
9365 case 18:
9366 val |= PIPECONF_6BPC;
9367 break;
9368 case 24:
9369 val |= PIPECONF_8BPC;
9370 break;
9371 case 30:
9372 val |= PIPECONF_10BPC;
9373 break;
9374 case 36:
9375 val |= PIPECONF_12BPC;
9376 break;
9377 default:
9378 /* Case prevented by intel_choose_pipe_bpp_dither. */
9379 BUG();
9380 }
9381
9382 if (intel_crtc->config->dither)
9383 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9384
9385 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9386 val |= PIPECONF_INTERLACED_ILK;
9387 else
9388 val |= PIPECONF_PROGRESSIVE;
9389
9390 if (intel_crtc->config->limited_color_range)
9391 val |= PIPECONF_COLOR_RANGE_SELECT;
9392
9393 I915_WRITE(PIPECONF(pipe), val);
9394 POSTING_READ(PIPECONF(pipe));
9395 }
9396
9397 static void haswell_set_pipeconf(struct drm_crtc *crtc)
9398 {
9399 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9401 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9402 u32 val = 0;
9403
9404 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
9405 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9406
9407 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9408 val |= PIPECONF_INTERLACED_ILK;
9409 else
9410 val |= PIPECONF_PROGRESSIVE;
9411
9412 I915_WRITE(PIPECONF(cpu_transcoder), val);
9413 POSTING_READ(PIPECONF(cpu_transcoder));
9414 }
9415
9416 static void haswell_set_pipemisc(struct drm_crtc *crtc)
9417 {
9418 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9419 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9420
9421 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
9422 u32 val = 0;
9423
9424 switch (intel_crtc->config->pipe_bpp) {
9425 case 18:
9426 val |= PIPEMISC_DITHER_6_BPC;
9427 break;
9428 case 24:
9429 val |= PIPEMISC_DITHER_8_BPC;
9430 break;
9431 case 30:
9432 val |= PIPEMISC_DITHER_10_BPC;
9433 break;
9434 case 36:
9435 val |= PIPEMISC_DITHER_12_BPC;
9436 break;
9437 default:
9438 /* Case prevented by pipe_config_set_bpp. */
9439 BUG();
9440 }
9441
9442 if (intel_crtc->config->dither)
9443 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9444
9445 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
9446 }
9447 }
9448
9449 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9450 {
9451 /*
9452 * Account for spread spectrum to avoid
9453 * oversubscribing the link. Max center spread
9454 * is 2.5%; use 5% for safety's sake.
9455 */
9456 u32 bps = target_clock * bpp * 21 / 20;
9457 return DIV_ROUND_UP(bps, link_bw * 8);
9458 }
9459
9460 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9461 {
9462 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9463 }
9464
9465 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
9466 struct intel_crtc_state *crtc_state,
9467 struct dpll *reduced_clock)
9468 {
9469 struct drm_crtc *crtc = &intel_crtc->base;
9470 struct drm_device *dev = crtc->dev;
9471 struct drm_i915_private *dev_priv = to_i915(dev);
9472 u32 dpll, fp, fp2;
9473 int factor;
9474
9475 /* Enable autotuning of the PLL clock (if permissible) */
9476 factor = 21;
9477 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9478 if ((intel_panel_use_ssc(dev_priv) &&
9479 dev_priv->vbt.lvds_ssc_freq == 100000) ||
9480 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
9481 factor = 25;
9482 } else if (crtc_state->sdvo_tv_clock)
9483 factor = 20;
9484
9485 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9486
9487 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9488 fp |= FP_CB_TUNE;
9489
9490 if (reduced_clock) {
9491 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9492
9493 if (reduced_clock->m < factor * reduced_clock->n)
9494 fp2 |= FP_CB_TUNE;
9495 } else {
9496 fp2 = fp;
9497 }
9498
9499 dpll = 0;
9500
9501 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9502 dpll |= DPLLB_MODE_LVDS;
9503 else
9504 dpll |= DPLLB_MODE_DAC_SERIAL;
9505
9506 dpll |= (crtc_state->pixel_multiplier - 1)
9507 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9508
9509 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9510 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9511 dpll |= DPLL_SDVO_HIGH_SPEED;
9512
9513 if (intel_crtc_has_dp_encoder(crtc_state))
9514 dpll |= DPLL_SDVO_HIGH_SPEED;
9515
9516 /*
9517 * The high speed IO clock is only really required for
9518 * SDVO/HDMI/DP, but we also enable it for CRT to make it
9519 * possible to share the DPLL between CRT and HDMI. Enabling
9520 * the clock needlessly does no real harm, except use up a
9521 * bit of power potentially.
9522 *
9523 * We'll limit this to IVB with 3 pipes, since it has only two
9524 * DPLLs and so DPLL sharing is the only way to get three pipes
9525 * driving PCH ports at the same time. On SNB we could do this,
9526 * and potentially avoid enabling the second DPLL, but it's not
9527 * clear if it''s a win or loss power wise. No point in doing
9528 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9529 */
9530 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
9531 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
9532 dpll |= DPLL_SDVO_HIGH_SPEED;
9533
9534 /* compute bitmask from p1 value */
9535 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9536 /* also FPA1 */
9537 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9538
9539 switch (crtc_state->dpll.p2) {
9540 case 5:
9541 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9542 break;
9543 case 7:
9544 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9545 break;
9546 case 10:
9547 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9548 break;
9549 case 14:
9550 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9551 break;
9552 }
9553
9554 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9555 intel_panel_use_ssc(dev_priv))
9556 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9557 else
9558 dpll |= PLL_REF_INPUT_DREFCLK;
9559
9560 dpll |= DPLL_VCO_ENABLE;
9561
9562 crtc_state->dpll_hw_state.dpll = dpll;
9563 crtc_state->dpll_hw_state.fp0 = fp;
9564 crtc_state->dpll_hw_state.fp1 = fp2;
9565 }
9566
9567 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9568 struct intel_crtc_state *crtc_state)
9569 {
9570 struct drm_device *dev = crtc->base.dev;
9571 struct drm_i915_private *dev_priv = to_i915(dev);
9572 struct dpll reduced_clock;
9573 bool has_reduced_clock = false;
9574 struct intel_shared_dpll *pll;
9575 const struct intel_limit *limit;
9576 int refclk = 120000;
9577
9578 memset(&crtc_state->dpll_hw_state, 0,
9579 sizeof(crtc_state->dpll_hw_state));
9580
9581 crtc->lowfreq_avail = false;
9582
9583 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9584 if (!crtc_state->has_pch_encoder)
9585 return 0;
9586
9587 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9588 if (intel_panel_use_ssc(dev_priv)) {
9589 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9590 dev_priv->vbt.lvds_ssc_freq);
9591 refclk = dev_priv->vbt.lvds_ssc_freq;
9592 }
9593
9594 if (intel_is_dual_link_lvds(dev)) {
9595 if (refclk == 100000)
9596 limit = &intel_limits_ironlake_dual_lvds_100m;
9597 else
9598 limit = &intel_limits_ironlake_dual_lvds;
9599 } else {
9600 if (refclk == 100000)
9601 limit = &intel_limits_ironlake_single_lvds_100m;
9602 else
9603 limit = &intel_limits_ironlake_single_lvds;
9604 }
9605 } else {
9606 limit = &intel_limits_ironlake_dac;
9607 }
9608
9609 if (!crtc_state->clock_set &&
9610 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9611 refclk, NULL, &crtc_state->dpll)) {
9612 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9613 return -EINVAL;
9614 }
9615
9616 ironlake_compute_dpll(crtc, crtc_state,
9617 has_reduced_clock ? &reduced_clock : NULL);
9618
9619 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9620 if (pll == NULL) {
9621 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9622 pipe_name(crtc->pipe));
9623 return -EINVAL;
9624 }
9625
9626 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9627 has_reduced_clock)
9628 crtc->lowfreq_avail = true;
9629
9630 return 0;
9631 }
9632
9633 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9634 struct intel_link_m_n *m_n)
9635 {
9636 struct drm_device *dev = crtc->base.dev;
9637 struct drm_i915_private *dev_priv = to_i915(dev);
9638 enum pipe pipe = crtc->pipe;
9639
9640 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9641 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9642 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9643 & ~TU_SIZE_MASK;
9644 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9645 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9646 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9647 }
9648
9649 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9650 enum transcoder transcoder,
9651 struct intel_link_m_n *m_n,
9652 struct intel_link_m_n *m2_n2)
9653 {
9654 struct drm_device *dev = crtc->base.dev;
9655 struct drm_i915_private *dev_priv = to_i915(dev);
9656 enum pipe pipe = crtc->pipe;
9657
9658 if (INTEL_INFO(dev)->gen >= 5) {
9659 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9660 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9661 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9662 & ~TU_SIZE_MASK;
9663 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9664 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9665 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9666 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9667 * gen < 8) and if DRRS is supported (to make sure the
9668 * registers are not unnecessarily read).
9669 */
9670 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9671 crtc->config->has_drrs) {
9672 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9673 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9674 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9675 & ~TU_SIZE_MASK;
9676 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9677 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9678 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9679 }
9680 } else {
9681 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9682 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9683 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9684 & ~TU_SIZE_MASK;
9685 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9686 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9687 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9688 }
9689 }
9690
9691 void intel_dp_get_m_n(struct intel_crtc *crtc,
9692 struct intel_crtc_state *pipe_config)
9693 {
9694 if (pipe_config->has_pch_encoder)
9695 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9696 else
9697 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9698 &pipe_config->dp_m_n,
9699 &pipe_config->dp_m2_n2);
9700 }
9701
9702 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9703 struct intel_crtc_state *pipe_config)
9704 {
9705 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9706 &pipe_config->fdi_m_n, NULL);
9707 }
9708
9709 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9710 struct intel_crtc_state *pipe_config)
9711 {
9712 struct drm_device *dev = crtc->base.dev;
9713 struct drm_i915_private *dev_priv = to_i915(dev);
9714 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9715 uint32_t ps_ctrl = 0;
9716 int id = -1;
9717 int i;
9718
9719 /* find scaler attached to this pipe */
9720 for (i = 0; i < crtc->num_scalers; i++) {
9721 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9722 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9723 id = i;
9724 pipe_config->pch_pfit.enabled = true;
9725 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9726 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9727 break;
9728 }
9729 }
9730
9731 scaler_state->scaler_id = id;
9732 if (id >= 0) {
9733 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9734 } else {
9735 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9736 }
9737 }
9738
9739 static void
9740 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9741 struct intel_initial_plane_config *plane_config)
9742 {
9743 struct drm_device *dev = crtc->base.dev;
9744 struct drm_i915_private *dev_priv = to_i915(dev);
9745 u32 val, base, offset, stride_mult, tiling;
9746 int pipe = crtc->pipe;
9747 int fourcc, pixel_format;
9748 unsigned int aligned_height;
9749 struct drm_framebuffer *fb;
9750 struct intel_framebuffer *intel_fb;
9751
9752 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9753 if (!intel_fb) {
9754 DRM_DEBUG_KMS("failed to alloc fb\n");
9755 return;
9756 }
9757
9758 fb = &intel_fb->base;
9759
9760 val = I915_READ(PLANE_CTL(pipe, 0));
9761 if (!(val & PLANE_CTL_ENABLE))
9762 goto error;
9763
9764 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9765 fourcc = skl_format_to_fourcc(pixel_format,
9766 val & PLANE_CTL_ORDER_RGBX,
9767 val & PLANE_CTL_ALPHA_MASK);
9768 fb->pixel_format = fourcc;
9769 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9770
9771 tiling = val & PLANE_CTL_TILED_MASK;
9772 switch (tiling) {
9773 case PLANE_CTL_TILED_LINEAR:
9774 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9775 break;
9776 case PLANE_CTL_TILED_X:
9777 plane_config->tiling = I915_TILING_X;
9778 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9779 break;
9780 case PLANE_CTL_TILED_Y:
9781 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9782 break;
9783 case PLANE_CTL_TILED_YF:
9784 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9785 break;
9786 default:
9787 MISSING_CASE(tiling);
9788 goto error;
9789 }
9790
9791 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9792 plane_config->base = base;
9793
9794 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9795
9796 val = I915_READ(PLANE_SIZE(pipe, 0));
9797 fb->height = ((val >> 16) & 0xfff) + 1;
9798 fb->width = ((val >> 0) & 0x1fff) + 1;
9799
9800 val = I915_READ(PLANE_STRIDE(pipe, 0));
9801 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9802 fb->pixel_format);
9803 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9804
9805 aligned_height = intel_fb_align_height(dev, fb->height,
9806 fb->pixel_format,
9807 fb->modifier[0]);
9808
9809 plane_config->size = fb->pitches[0] * aligned_height;
9810
9811 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9812 pipe_name(pipe), fb->width, fb->height,
9813 fb->bits_per_pixel, base, fb->pitches[0],
9814 plane_config->size);
9815
9816 plane_config->fb = intel_fb;
9817 return;
9818
9819 error:
9820 kfree(intel_fb);
9821 }
9822
9823 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9824 struct intel_crtc_state *pipe_config)
9825 {
9826 struct drm_device *dev = crtc->base.dev;
9827 struct drm_i915_private *dev_priv = to_i915(dev);
9828 uint32_t tmp;
9829
9830 tmp = I915_READ(PF_CTL(crtc->pipe));
9831
9832 if (tmp & PF_ENABLE) {
9833 pipe_config->pch_pfit.enabled = true;
9834 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9835 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9836
9837 /* We currently do not free assignements of panel fitters on
9838 * ivb/hsw (since we don't use the higher upscaling modes which
9839 * differentiates them) so just WARN about this case for now. */
9840 if (IS_GEN7(dev)) {
9841 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9842 PF_PIPE_SEL_IVB(crtc->pipe));
9843 }
9844 }
9845 }
9846
9847 static void
9848 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9849 struct intel_initial_plane_config *plane_config)
9850 {
9851 struct drm_device *dev = crtc->base.dev;
9852 struct drm_i915_private *dev_priv = to_i915(dev);
9853 u32 val, base, offset;
9854 int pipe = crtc->pipe;
9855 int fourcc, pixel_format;
9856 unsigned int aligned_height;
9857 struct drm_framebuffer *fb;
9858 struct intel_framebuffer *intel_fb;
9859
9860 val = I915_READ(DSPCNTR(pipe));
9861 if (!(val & DISPLAY_PLANE_ENABLE))
9862 return;
9863
9864 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9865 if (!intel_fb) {
9866 DRM_DEBUG_KMS("failed to alloc fb\n");
9867 return;
9868 }
9869
9870 fb = &intel_fb->base;
9871
9872 if (INTEL_INFO(dev)->gen >= 4) {
9873 if (val & DISPPLANE_TILED) {
9874 plane_config->tiling = I915_TILING_X;
9875 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9876 }
9877 }
9878
9879 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9880 fourcc = i9xx_format_to_fourcc(pixel_format);
9881 fb->pixel_format = fourcc;
9882 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9883
9884 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9885 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9886 offset = I915_READ(DSPOFFSET(pipe));
9887 } else {
9888 if (plane_config->tiling)
9889 offset = I915_READ(DSPTILEOFF(pipe));
9890 else
9891 offset = I915_READ(DSPLINOFF(pipe));
9892 }
9893 plane_config->base = base;
9894
9895 val = I915_READ(PIPESRC(pipe));
9896 fb->width = ((val >> 16) & 0xfff) + 1;
9897 fb->height = ((val >> 0) & 0xfff) + 1;
9898
9899 val = I915_READ(DSPSTRIDE(pipe));
9900 fb->pitches[0] = val & 0xffffffc0;
9901
9902 aligned_height = intel_fb_align_height(dev, fb->height,
9903 fb->pixel_format,
9904 fb->modifier[0]);
9905
9906 plane_config->size = fb->pitches[0] * aligned_height;
9907
9908 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9909 pipe_name(pipe), fb->width, fb->height,
9910 fb->bits_per_pixel, base, fb->pitches[0],
9911 plane_config->size);
9912
9913 plane_config->fb = intel_fb;
9914 }
9915
9916 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9917 struct intel_crtc_state *pipe_config)
9918 {
9919 struct drm_device *dev = crtc->base.dev;
9920 struct drm_i915_private *dev_priv = to_i915(dev);
9921 enum intel_display_power_domain power_domain;
9922 uint32_t tmp;
9923 bool ret;
9924
9925 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9926 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9927 return false;
9928
9929 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9930 pipe_config->shared_dpll = NULL;
9931
9932 ret = false;
9933 tmp = I915_READ(PIPECONF(crtc->pipe));
9934 if (!(tmp & PIPECONF_ENABLE))
9935 goto out;
9936
9937 switch (tmp & PIPECONF_BPC_MASK) {
9938 case PIPECONF_6BPC:
9939 pipe_config->pipe_bpp = 18;
9940 break;
9941 case PIPECONF_8BPC:
9942 pipe_config->pipe_bpp = 24;
9943 break;
9944 case PIPECONF_10BPC:
9945 pipe_config->pipe_bpp = 30;
9946 break;
9947 case PIPECONF_12BPC:
9948 pipe_config->pipe_bpp = 36;
9949 break;
9950 default:
9951 break;
9952 }
9953
9954 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9955 pipe_config->limited_color_range = true;
9956
9957 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9958 struct intel_shared_dpll *pll;
9959 enum intel_dpll_id pll_id;
9960
9961 pipe_config->has_pch_encoder = true;
9962
9963 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9964 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9965 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9966
9967 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9968
9969 if (HAS_PCH_IBX(dev_priv)) {
9970 /*
9971 * The pipe->pch transcoder and pch transcoder->pll
9972 * mapping is fixed.
9973 */
9974 pll_id = (enum intel_dpll_id) crtc->pipe;
9975 } else {
9976 tmp = I915_READ(PCH_DPLL_SEL);
9977 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9978 pll_id = DPLL_ID_PCH_PLL_B;
9979 else
9980 pll_id= DPLL_ID_PCH_PLL_A;
9981 }
9982
9983 pipe_config->shared_dpll =
9984 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9985 pll = pipe_config->shared_dpll;
9986
9987 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9988 &pipe_config->dpll_hw_state));
9989
9990 tmp = pipe_config->dpll_hw_state.dpll;
9991 pipe_config->pixel_multiplier =
9992 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9993 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9994
9995 ironlake_pch_clock_get(crtc, pipe_config);
9996 } else {
9997 pipe_config->pixel_multiplier = 1;
9998 }
9999
10000 intel_get_pipe_timings(crtc, pipe_config);
10001 intel_get_pipe_src_size(crtc, pipe_config);
10002
10003 ironlake_get_pfit_config(crtc, pipe_config);
10004
10005 ret = true;
10006
10007 out:
10008 intel_display_power_put(dev_priv, power_domain);
10009
10010 return ret;
10011 }
10012
10013 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
10014 {
10015 struct drm_device *dev = &dev_priv->drm;
10016 struct intel_crtc *crtc;
10017
10018 for_each_intel_crtc(dev, crtc)
10019 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
10020 pipe_name(crtc->pipe));
10021
10022 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
10023 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
10024 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
10025 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
10026 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
10027 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
10028 "CPU PWM1 enabled\n");
10029 if (IS_HASWELL(dev))
10030 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
10031 "CPU PWM2 enabled\n");
10032 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
10033 "PCH PWM1 enabled\n");
10034 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
10035 "Utility pin enabled\n");
10036 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
10037
10038 /*
10039 * In theory we can still leave IRQs enabled, as long as only the HPD
10040 * interrupts remain enabled. We used to check for that, but since it's
10041 * gen-specific and since we only disable LCPLL after we fully disable
10042 * the interrupts, the check below should be enough.
10043 */
10044 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
10045 }
10046
10047 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
10048 {
10049 struct drm_device *dev = &dev_priv->drm;
10050
10051 if (IS_HASWELL(dev))
10052 return I915_READ(D_COMP_HSW);
10053 else
10054 return I915_READ(D_COMP_BDW);
10055 }
10056
10057 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
10058 {
10059 struct drm_device *dev = &dev_priv->drm;
10060
10061 if (IS_HASWELL(dev)) {
10062 mutex_lock(&dev_priv->rps.hw_lock);
10063 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
10064 val))
10065 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
10066 mutex_unlock(&dev_priv->rps.hw_lock);
10067 } else {
10068 I915_WRITE(D_COMP_BDW, val);
10069 POSTING_READ(D_COMP_BDW);
10070 }
10071 }
10072
10073 /*
10074 * This function implements pieces of two sequences from BSpec:
10075 * - Sequence for display software to disable LCPLL
10076 * - Sequence for display software to allow package C8+
10077 * The steps implemented here are just the steps that actually touch the LCPLL
10078 * register. Callers should take care of disabling all the display engine
10079 * functions, doing the mode unset, fixing interrupts, etc.
10080 */
10081 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
10082 bool switch_to_fclk, bool allow_power_down)
10083 {
10084 uint32_t val;
10085
10086 assert_can_disable_lcpll(dev_priv);
10087
10088 val = I915_READ(LCPLL_CTL);
10089
10090 if (switch_to_fclk) {
10091 val |= LCPLL_CD_SOURCE_FCLK;
10092 I915_WRITE(LCPLL_CTL, val);
10093
10094 if (wait_for_us(I915_READ(LCPLL_CTL) &
10095 LCPLL_CD_SOURCE_FCLK_DONE, 1))
10096 DRM_ERROR("Switching to FCLK failed\n");
10097
10098 val = I915_READ(LCPLL_CTL);
10099 }
10100
10101 val |= LCPLL_PLL_DISABLE;
10102 I915_WRITE(LCPLL_CTL, val);
10103 POSTING_READ(LCPLL_CTL);
10104
10105 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
10106 DRM_ERROR("LCPLL still locked\n");
10107
10108 val = hsw_read_dcomp(dev_priv);
10109 val |= D_COMP_COMP_DISABLE;
10110 hsw_write_dcomp(dev_priv, val);
10111 ndelay(100);
10112
10113 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
10114 1))
10115 DRM_ERROR("D_COMP RCOMP still in progress\n");
10116
10117 if (allow_power_down) {
10118 val = I915_READ(LCPLL_CTL);
10119 val |= LCPLL_POWER_DOWN_ALLOW;
10120 I915_WRITE(LCPLL_CTL, val);
10121 POSTING_READ(LCPLL_CTL);
10122 }
10123 }
10124
10125 /*
10126 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
10127 * source.
10128 */
10129 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
10130 {
10131 uint32_t val;
10132
10133 val = I915_READ(LCPLL_CTL);
10134
10135 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
10136 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
10137 return;
10138
10139 /*
10140 * Make sure we're not on PC8 state before disabling PC8, otherwise
10141 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
10142 */
10143 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
10144
10145 if (val & LCPLL_POWER_DOWN_ALLOW) {
10146 val &= ~LCPLL_POWER_DOWN_ALLOW;
10147 I915_WRITE(LCPLL_CTL, val);
10148 POSTING_READ(LCPLL_CTL);
10149 }
10150
10151 val = hsw_read_dcomp(dev_priv);
10152 val |= D_COMP_COMP_FORCE;
10153 val &= ~D_COMP_COMP_DISABLE;
10154 hsw_write_dcomp(dev_priv, val);
10155
10156 val = I915_READ(LCPLL_CTL);
10157 val &= ~LCPLL_PLL_DISABLE;
10158 I915_WRITE(LCPLL_CTL, val);
10159
10160 if (intel_wait_for_register(dev_priv,
10161 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
10162 5))
10163 DRM_ERROR("LCPLL not locked yet\n");
10164
10165 if (val & LCPLL_CD_SOURCE_FCLK) {
10166 val = I915_READ(LCPLL_CTL);
10167 val &= ~LCPLL_CD_SOURCE_FCLK;
10168 I915_WRITE(LCPLL_CTL, val);
10169
10170 if (wait_for_us((I915_READ(LCPLL_CTL) &
10171 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10172 DRM_ERROR("Switching back to LCPLL failed\n");
10173 }
10174
10175 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
10176 intel_update_cdclk(&dev_priv->drm);
10177 }
10178
10179 /*
10180 * Package states C8 and deeper are really deep PC states that can only be
10181 * reached when all the devices on the system allow it, so even if the graphics
10182 * device allows PC8+, it doesn't mean the system will actually get to these
10183 * states. Our driver only allows PC8+ when going into runtime PM.
10184 *
10185 * The requirements for PC8+ are that all the outputs are disabled, the power
10186 * well is disabled and most interrupts are disabled, and these are also
10187 * requirements for runtime PM. When these conditions are met, we manually do
10188 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
10189 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
10190 * hang the machine.
10191 *
10192 * When we really reach PC8 or deeper states (not just when we allow it) we lose
10193 * the state of some registers, so when we come back from PC8+ we need to
10194 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
10195 * need to take care of the registers kept by RC6. Notice that this happens even
10196 * if we don't put the device in PCI D3 state (which is what currently happens
10197 * because of the runtime PM support).
10198 *
10199 * For more, read "Display Sequences for Package C8" on the hardware
10200 * documentation.
10201 */
10202 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
10203 {
10204 struct drm_device *dev = &dev_priv->drm;
10205 uint32_t val;
10206
10207 DRM_DEBUG_KMS("Enabling package C8+\n");
10208
10209 if (HAS_PCH_LPT_LP(dev)) {
10210 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10211 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
10212 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10213 }
10214
10215 lpt_disable_clkout_dp(dev);
10216 hsw_disable_lcpll(dev_priv, true, true);
10217 }
10218
10219 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
10220 {
10221 struct drm_device *dev = &dev_priv->drm;
10222 uint32_t val;
10223
10224 DRM_DEBUG_KMS("Disabling package C8+\n");
10225
10226 hsw_restore_lcpll(dev_priv);
10227 lpt_init_pch_refclk(dev);
10228
10229 if (HAS_PCH_LPT_LP(dev)) {
10230 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10231 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
10232 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10233 }
10234 }
10235
10236 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10237 {
10238 struct drm_device *dev = old_state->dev;
10239 struct intel_atomic_state *old_intel_state =
10240 to_intel_atomic_state(old_state);
10241 unsigned int req_cdclk = old_intel_state->dev_cdclk;
10242
10243 bxt_set_cdclk(to_i915(dev), req_cdclk);
10244 }
10245
10246 static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
10247 int pixel_rate)
10248 {
10249 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
10250
10251 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
10252 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
10253 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
10254
10255 /* BSpec says "Do not use DisplayPort with CDCLK less than
10256 * 432 MHz, audio enabled, port width x4, and link rate
10257 * HBR2 (5.4 GHz), or else there may be audio corruption or
10258 * screen corruption."
10259 */
10260 if (intel_crtc_has_dp_encoder(crtc_state) &&
10261 crtc_state->has_audio &&
10262 crtc_state->port_clock >= 540000 &&
10263 crtc_state->lane_count == 4)
10264 pixel_rate = max(432000, pixel_rate);
10265
10266 return pixel_rate;
10267 }
10268
10269 /* compute the max rate for new configuration */
10270 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
10271 {
10272 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10273 struct drm_i915_private *dev_priv = to_i915(state->dev);
10274 struct drm_crtc *crtc;
10275 struct drm_crtc_state *cstate;
10276 struct intel_crtc_state *crtc_state;
10277 unsigned max_pixel_rate = 0, i;
10278 enum pipe pipe;
10279
10280 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
10281 sizeof(intel_state->min_pixclk));
10282
10283 for_each_crtc_in_state(state, crtc, cstate, i) {
10284 int pixel_rate;
10285
10286 crtc_state = to_intel_crtc_state(cstate);
10287 if (!crtc_state->base.enable) {
10288 intel_state->min_pixclk[i] = 0;
10289 continue;
10290 }
10291
10292 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
10293
10294 if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
10295 pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
10296 pixel_rate);
10297
10298 intel_state->min_pixclk[i] = pixel_rate;
10299 }
10300
10301 for_each_pipe(dev_priv, pipe)
10302 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
10303
10304 return max_pixel_rate;
10305 }
10306
10307 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
10308 {
10309 struct drm_i915_private *dev_priv = to_i915(dev);
10310 uint32_t val, data;
10311 int ret;
10312
10313 if (WARN((I915_READ(LCPLL_CTL) &
10314 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
10315 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
10316 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
10317 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
10318 "trying to change cdclk frequency with cdclk not enabled\n"))
10319 return;
10320
10321 mutex_lock(&dev_priv->rps.hw_lock);
10322 ret = sandybridge_pcode_write(dev_priv,
10323 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
10324 mutex_unlock(&dev_priv->rps.hw_lock);
10325 if (ret) {
10326 DRM_ERROR("failed to inform pcode about cdclk change\n");
10327 return;
10328 }
10329
10330 val = I915_READ(LCPLL_CTL);
10331 val |= LCPLL_CD_SOURCE_FCLK;
10332 I915_WRITE(LCPLL_CTL, val);
10333
10334 if (wait_for_us(I915_READ(LCPLL_CTL) &
10335 LCPLL_CD_SOURCE_FCLK_DONE, 1))
10336 DRM_ERROR("Switching to FCLK failed\n");
10337
10338 val = I915_READ(LCPLL_CTL);
10339 val &= ~LCPLL_CLK_FREQ_MASK;
10340
10341 switch (cdclk) {
10342 case 450000:
10343 val |= LCPLL_CLK_FREQ_450;
10344 data = 0;
10345 break;
10346 case 540000:
10347 val |= LCPLL_CLK_FREQ_54O_BDW;
10348 data = 1;
10349 break;
10350 case 337500:
10351 val |= LCPLL_CLK_FREQ_337_5_BDW;
10352 data = 2;
10353 break;
10354 case 675000:
10355 val |= LCPLL_CLK_FREQ_675_BDW;
10356 data = 3;
10357 break;
10358 default:
10359 WARN(1, "invalid cdclk frequency\n");
10360 return;
10361 }
10362
10363 I915_WRITE(LCPLL_CTL, val);
10364
10365 val = I915_READ(LCPLL_CTL);
10366 val &= ~LCPLL_CD_SOURCE_FCLK;
10367 I915_WRITE(LCPLL_CTL, val);
10368
10369 if (wait_for_us((I915_READ(LCPLL_CTL) &
10370 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10371 DRM_ERROR("Switching back to LCPLL failed\n");
10372
10373 mutex_lock(&dev_priv->rps.hw_lock);
10374 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
10375 mutex_unlock(&dev_priv->rps.hw_lock);
10376
10377 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
10378
10379 intel_update_cdclk(dev);
10380
10381 WARN(cdclk != dev_priv->cdclk_freq,
10382 "cdclk requested %d kHz but got %d kHz\n",
10383 cdclk, dev_priv->cdclk_freq);
10384 }
10385
10386 static int broadwell_calc_cdclk(int max_pixclk)
10387 {
10388 if (max_pixclk > 540000)
10389 return 675000;
10390 else if (max_pixclk > 450000)
10391 return 540000;
10392 else if (max_pixclk > 337500)
10393 return 450000;
10394 else
10395 return 337500;
10396 }
10397
10398 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
10399 {
10400 struct drm_i915_private *dev_priv = to_i915(state->dev);
10401 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10402 int max_pixclk = ilk_max_pixel_rate(state);
10403 int cdclk;
10404
10405 /*
10406 * FIXME should also account for plane ratio
10407 * once 64bpp pixel formats are supported.
10408 */
10409 cdclk = broadwell_calc_cdclk(max_pixclk);
10410
10411 if (cdclk > dev_priv->max_cdclk_freq) {
10412 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10413 cdclk, dev_priv->max_cdclk_freq);
10414 return -EINVAL;
10415 }
10416
10417 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10418 if (!intel_state->active_crtcs)
10419 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
10420
10421 return 0;
10422 }
10423
10424 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10425 {
10426 struct drm_device *dev = old_state->dev;
10427 struct intel_atomic_state *old_intel_state =
10428 to_intel_atomic_state(old_state);
10429 unsigned req_cdclk = old_intel_state->dev_cdclk;
10430
10431 broadwell_set_cdclk(dev, req_cdclk);
10432 }
10433
10434 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
10435 {
10436 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10437 struct drm_i915_private *dev_priv = to_i915(state->dev);
10438 const int max_pixclk = ilk_max_pixel_rate(state);
10439 int vco = intel_state->cdclk_pll_vco;
10440 int cdclk;
10441
10442 /*
10443 * FIXME should also account for plane ratio
10444 * once 64bpp pixel formats are supported.
10445 */
10446 cdclk = skl_calc_cdclk(max_pixclk, vco);
10447
10448 /*
10449 * FIXME move the cdclk caclulation to
10450 * compute_config() so we can fail gracegully.
10451 */
10452 if (cdclk > dev_priv->max_cdclk_freq) {
10453 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10454 cdclk, dev_priv->max_cdclk_freq);
10455 cdclk = dev_priv->max_cdclk_freq;
10456 }
10457
10458 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10459 if (!intel_state->active_crtcs)
10460 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
10461
10462 return 0;
10463 }
10464
10465 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10466 {
10467 struct drm_i915_private *dev_priv = to_i915(old_state->dev);
10468 struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
10469 unsigned int req_cdclk = intel_state->dev_cdclk;
10470 unsigned int req_vco = intel_state->cdclk_pll_vco;
10471
10472 skl_set_cdclk(dev_priv, req_cdclk, req_vco);
10473 }
10474
10475 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10476 struct intel_crtc_state *crtc_state)
10477 {
10478 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
10479 if (!intel_ddi_pll_select(crtc, crtc_state))
10480 return -EINVAL;
10481 }
10482
10483 crtc->lowfreq_avail = false;
10484
10485 return 0;
10486 }
10487
10488 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10489 enum port port,
10490 struct intel_crtc_state *pipe_config)
10491 {
10492 enum intel_dpll_id id;
10493
10494 switch (port) {
10495 case PORT_A:
10496 id = DPLL_ID_SKL_DPLL0;
10497 break;
10498 case PORT_B:
10499 id = DPLL_ID_SKL_DPLL1;
10500 break;
10501 case PORT_C:
10502 id = DPLL_ID_SKL_DPLL2;
10503 break;
10504 default:
10505 DRM_ERROR("Incorrect port type\n");
10506 return;
10507 }
10508
10509 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10510 }
10511
10512 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10513 enum port port,
10514 struct intel_crtc_state *pipe_config)
10515 {
10516 enum intel_dpll_id id;
10517 u32 temp;
10518
10519 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10520 id = temp >> (port * 3 + 1);
10521
10522 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
10523 return;
10524
10525 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10526 }
10527
10528 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10529 enum port port,
10530 struct intel_crtc_state *pipe_config)
10531 {
10532 enum intel_dpll_id id;
10533 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10534
10535 switch (ddi_pll_sel) {
10536 case PORT_CLK_SEL_WRPLL1:
10537 id = DPLL_ID_WRPLL1;
10538 break;
10539 case PORT_CLK_SEL_WRPLL2:
10540 id = DPLL_ID_WRPLL2;
10541 break;
10542 case PORT_CLK_SEL_SPLL:
10543 id = DPLL_ID_SPLL;
10544 break;
10545 case PORT_CLK_SEL_LCPLL_810:
10546 id = DPLL_ID_LCPLL_810;
10547 break;
10548 case PORT_CLK_SEL_LCPLL_1350:
10549 id = DPLL_ID_LCPLL_1350;
10550 break;
10551 case PORT_CLK_SEL_LCPLL_2700:
10552 id = DPLL_ID_LCPLL_2700;
10553 break;
10554 default:
10555 MISSING_CASE(ddi_pll_sel);
10556 /* fall through */
10557 case PORT_CLK_SEL_NONE:
10558 return;
10559 }
10560
10561 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10562 }
10563
10564 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10565 struct intel_crtc_state *pipe_config,
10566 unsigned long *power_domain_mask)
10567 {
10568 struct drm_device *dev = crtc->base.dev;
10569 struct drm_i915_private *dev_priv = to_i915(dev);
10570 enum intel_display_power_domain power_domain;
10571 u32 tmp;
10572
10573 /*
10574 * The pipe->transcoder mapping is fixed with the exception of the eDP
10575 * transcoder handled below.
10576 */
10577 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10578
10579 /*
10580 * XXX: Do intel_display_power_get_if_enabled before reading this (for
10581 * consistency and less surprising code; it's in always on power).
10582 */
10583 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10584 if (tmp & TRANS_DDI_FUNC_ENABLE) {
10585 enum pipe trans_edp_pipe;
10586 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10587 default:
10588 WARN(1, "unknown pipe linked to edp transcoder\n");
10589 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10590 case TRANS_DDI_EDP_INPUT_A_ON:
10591 trans_edp_pipe = PIPE_A;
10592 break;
10593 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10594 trans_edp_pipe = PIPE_B;
10595 break;
10596 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10597 trans_edp_pipe = PIPE_C;
10598 break;
10599 }
10600
10601 if (trans_edp_pipe == crtc->pipe)
10602 pipe_config->cpu_transcoder = TRANSCODER_EDP;
10603 }
10604
10605 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10606 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10607 return false;
10608 *power_domain_mask |= BIT(power_domain);
10609
10610 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10611
10612 return tmp & PIPECONF_ENABLE;
10613 }
10614
10615 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10616 struct intel_crtc_state *pipe_config,
10617 unsigned long *power_domain_mask)
10618 {
10619 struct drm_device *dev = crtc->base.dev;
10620 struct drm_i915_private *dev_priv = to_i915(dev);
10621 enum intel_display_power_domain power_domain;
10622 enum port port;
10623 enum transcoder cpu_transcoder;
10624 u32 tmp;
10625
10626 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10627 if (port == PORT_A)
10628 cpu_transcoder = TRANSCODER_DSI_A;
10629 else
10630 cpu_transcoder = TRANSCODER_DSI_C;
10631
10632 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10633 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10634 continue;
10635 *power_domain_mask |= BIT(power_domain);
10636
10637 /*
10638 * The PLL needs to be enabled with a valid divider
10639 * configuration, otherwise accessing DSI registers will hang
10640 * the machine. See BSpec North Display Engine
10641 * registers/MIPI[BXT]. We can break out here early, since we
10642 * need the same DSI PLL to be enabled for both DSI ports.
10643 */
10644 if (!intel_dsi_pll_is_enabled(dev_priv))
10645 break;
10646
10647 /* XXX: this works for video mode only */
10648 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10649 if (!(tmp & DPI_ENABLE))
10650 continue;
10651
10652 tmp = I915_READ(MIPI_CTRL(port));
10653 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10654 continue;
10655
10656 pipe_config->cpu_transcoder = cpu_transcoder;
10657 break;
10658 }
10659
10660 return transcoder_is_dsi(pipe_config->cpu_transcoder);
10661 }
10662
10663 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10664 struct intel_crtc_state *pipe_config)
10665 {
10666 struct drm_device *dev = crtc->base.dev;
10667 struct drm_i915_private *dev_priv = to_i915(dev);
10668 struct intel_shared_dpll *pll;
10669 enum port port;
10670 uint32_t tmp;
10671
10672 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10673
10674 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10675
10676 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
10677 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10678 else if (IS_BROXTON(dev))
10679 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10680 else
10681 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10682
10683 pll = pipe_config->shared_dpll;
10684 if (pll) {
10685 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10686 &pipe_config->dpll_hw_state));
10687 }
10688
10689 /*
10690 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10691 * DDI E. So just check whether this pipe is wired to DDI E and whether
10692 * the PCH transcoder is on.
10693 */
10694 if (INTEL_INFO(dev)->gen < 9 &&
10695 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10696 pipe_config->has_pch_encoder = true;
10697
10698 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10699 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10700 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10701
10702 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10703 }
10704 }
10705
10706 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10707 struct intel_crtc_state *pipe_config)
10708 {
10709 struct drm_device *dev = crtc->base.dev;
10710 struct drm_i915_private *dev_priv = to_i915(dev);
10711 enum intel_display_power_domain power_domain;
10712 unsigned long power_domain_mask;
10713 bool active;
10714
10715 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10716 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10717 return false;
10718 power_domain_mask = BIT(power_domain);
10719
10720 pipe_config->shared_dpll = NULL;
10721
10722 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10723
10724 if (IS_BROXTON(dev_priv) &&
10725 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
10726 WARN_ON(active);
10727 active = true;
10728 }
10729
10730 if (!active)
10731 goto out;
10732
10733 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10734 haswell_get_ddi_port_state(crtc, pipe_config);
10735 intel_get_pipe_timings(crtc, pipe_config);
10736 }
10737
10738 intel_get_pipe_src_size(crtc, pipe_config);
10739
10740 pipe_config->gamma_mode =
10741 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10742
10743 if (INTEL_INFO(dev)->gen >= 9) {
10744 skl_init_scalers(dev, crtc, pipe_config);
10745 }
10746
10747 if (INTEL_INFO(dev)->gen >= 9) {
10748 pipe_config->scaler_state.scaler_id = -1;
10749 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10750 }
10751
10752 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10753 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10754 power_domain_mask |= BIT(power_domain);
10755 if (INTEL_INFO(dev)->gen >= 9)
10756 skylake_get_pfit_config(crtc, pipe_config);
10757 else
10758 ironlake_get_pfit_config(crtc, pipe_config);
10759 }
10760
10761 if (IS_HASWELL(dev))
10762 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10763 (I915_READ(IPS_CTL) & IPS_ENABLE);
10764
10765 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10766 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10767 pipe_config->pixel_multiplier =
10768 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10769 } else {
10770 pipe_config->pixel_multiplier = 1;
10771 }
10772
10773 out:
10774 for_each_power_domain(power_domain, power_domain_mask)
10775 intel_display_power_put(dev_priv, power_domain);
10776
10777 return active;
10778 }
10779
10780 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10781 const struct intel_plane_state *plane_state)
10782 {
10783 struct drm_device *dev = crtc->dev;
10784 struct drm_i915_private *dev_priv = to_i915(dev);
10785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10786 uint32_t cntl = 0, size = 0;
10787
10788 if (plane_state && plane_state->base.visible) {
10789 unsigned int width = plane_state->base.crtc_w;
10790 unsigned int height = plane_state->base.crtc_h;
10791 unsigned int stride = roundup_pow_of_two(width) * 4;
10792
10793 switch (stride) {
10794 default:
10795 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10796 width, stride);
10797 stride = 256;
10798 /* fallthrough */
10799 case 256:
10800 case 512:
10801 case 1024:
10802 case 2048:
10803 break;
10804 }
10805
10806 cntl |= CURSOR_ENABLE |
10807 CURSOR_GAMMA_ENABLE |
10808 CURSOR_FORMAT_ARGB |
10809 CURSOR_STRIDE(stride);
10810
10811 size = (height << 12) | width;
10812 }
10813
10814 if (intel_crtc->cursor_cntl != 0 &&
10815 (intel_crtc->cursor_base != base ||
10816 intel_crtc->cursor_size != size ||
10817 intel_crtc->cursor_cntl != cntl)) {
10818 /* On these chipsets we can only modify the base/size/stride
10819 * whilst the cursor is disabled.
10820 */
10821 I915_WRITE(CURCNTR(PIPE_A), 0);
10822 POSTING_READ(CURCNTR(PIPE_A));
10823 intel_crtc->cursor_cntl = 0;
10824 }
10825
10826 if (intel_crtc->cursor_base != base) {
10827 I915_WRITE(CURBASE(PIPE_A), base);
10828 intel_crtc->cursor_base = base;
10829 }
10830
10831 if (intel_crtc->cursor_size != size) {
10832 I915_WRITE(CURSIZE, size);
10833 intel_crtc->cursor_size = size;
10834 }
10835
10836 if (intel_crtc->cursor_cntl != cntl) {
10837 I915_WRITE(CURCNTR(PIPE_A), cntl);
10838 POSTING_READ(CURCNTR(PIPE_A));
10839 intel_crtc->cursor_cntl = cntl;
10840 }
10841 }
10842
10843 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10844 const struct intel_plane_state *plane_state)
10845 {
10846 struct drm_device *dev = crtc->dev;
10847 struct drm_i915_private *dev_priv = to_i915(dev);
10848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10849 const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
10850 int pipe = intel_crtc->pipe;
10851 uint32_t cntl = 0;
10852
10853 if (INTEL_GEN(dev_priv) >= 9 && wm->dirty_pipes & drm_crtc_mask(crtc))
10854 skl_write_cursor_wm(intel_crtc, wm);
10855
10856 if (plane_state && plane_state->base.visible) {
10857 cntl = MCURSOR_GAMMA_ENABLE;
10858 switch (plane_state->base.crtc_w) {
10859 case 64:
10860 cntl |= CURSOR_MODE_64_ARGB_AX;
10861 break;
10862 case 128:
10863 cntl |= CURSOR_MODE_128_ARGB_AX;
10864 break;
10865 case 256:
10866 cntl |= CURSOR_MODE_256_ARGB_AX;
10867 break;
10868 default:
10869 MISSING_CASE(plane_state->base.crtc_w);
10870 return;
10871 }
10872 cntl |= pipe << 28; /* Connect to correct pipe */
10873
10874 if (HAS_DDI(dev))
10875 cntl |= CURSOR_PIPE_CSC_ENABLE;
10876
10877 if (plane_state->base.rotation == DRM_ROTATE_180)
10878 cntl |= CURSOR_ROTATE_180;
10879 }
10880
10881 if (intel_crtc->cursor_cntl != cntl) {
10882 I915_WRITE(CURCNTR(pipe), cntl);
10883 POSTING_READ(CURCNTR(pipe));
10884 intel_crtc->cursor_cntl = cntl;
10885 }
10886
10887 /* and commit changes on next vblank */
10888 I915_WRITE(CURBASE(pipe), base);
10889 POSTING_READ(CURBASE(pipe));
10890
10891 intel_crtc->cursor_base = base;
10892 }
10893
10894 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10895 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10896 const struct intel_plane_state *plane_state)
10897 {
10898 struct drm_device *dev = crtc->dev;
10899 struct drm_i915_private *dev_priv = to_i915(dev);
10900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10901 int pipe = intel_crtc->pipe;
10902 u32 base = intel_crtc->cursor_addr;
10903 u32 pos = 0;
10904
10905 if (plane_state) {
10906 int x = plane_state->base.crtc_x;
10907 int y = plane_state->base.crtc_y;
10908
10909 if (x < 0) {
10910 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10911 x = -x;
10912 }
10913 pos |= x << CURSOR_X_SHIFT;
10914
10915 if (y < 0) {
10916 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10917 y = -y;
10918 }
10919 pos |= y << CURSOR_Y_SHIFT;
10920
10921 /* ILK+ do this automagically */
10922 if (HAS_GMCH_DISPLAY(dev) &&
10923 plane_state->base.rotation == DRM_ROTATE_180) {
10924 base += (plane_state->base.crtc_h *
10925 plane_state->base.crtc_w - 1) * 4;
10926 }
10927 }
10928
10929 I915_WRITE(CURPOS(pipe), pos);
10930
10931 if (IS_845G(dev) || IS_I865G(dev))
10932 i845_update_cursor(crtc, base, plane_state);
10933 else
10934 i9xx_update_cursor(crtc, base, plane_state);
10935 }
10936
10937 static bool cursor_size_ok(struct drm_device *dev,
10938 uint32_t width, uint32_t height)
10939 {
10940 if (width == 0 || height == 0)
10941 return false;
10942
10943 /*
10944 * 845g/865g are special in that they are only limited by
10945 * the width of their cursors, the height is arbitrary up to
10946 * the precision of the register. Everything else requires
10947 * square cursors, limited to a few power-of-two sizes.
10948 */
10949 if (IS_845G(dev) || IS_I865G(dev)) {
10950 if ((width & 63) != 0)
10951 return false;
10952
10953 if (width > (IS_845G(dev) ? 64 : 512))
10954 return false;
10955
10956 if (height > 1023)
10957 return false;
10958 } else {
10959 switch (width | height) {
10960 case 256:
10961 case 128:
10962 if (IS_GEN2(dev))
10963 return false;
10964 case 64:
10965 break;
10966 default:
10967 return false;
10968 }
10969 }
10970
10971 return true;
10972 }
10973
10974 /* VESA 640x480x72Hz mode to set on the pipe */
10975 static struct drm_display_mode load_detect_mode = {
10976 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10977 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10978 };
10979
10980 struct drm_framebuffer *
10981 __intel_framebuffer_create(struct drm_device *dev,
10982 struct drm_mode_fb_cmd2 *mode_cmd,
10983 struct drm_i915_gem_object *obj)
10984 {
10985 struct intel_framebuffer *intel_fb;
10986 int ret;
10987
10988 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10989 if (!intel_fb)
10990 return ERR_PTR(-ENOMEM);
10991
10992 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10993 if (ret)
10994 goto err;
10995
10996 return &intel_fb->base;
10997
10998 err:
10999 kfree(intel_fb);
11000 return ERR_PTR(ret);
11001 }
11002
11003 static struct drm_framebuffer *
11004 intel_framebuffer_create(struct drm_device *dev,
11005 struct drm_mode_fb_cmd2 *mode_cmd,
11006 struct drm_i915_gem_object *obj)
11007 {
11008 struct drm_framebuffer *fb;
11009 int ret;
11010
11011 ret = i915_mutex_lock_interruptible(dev);
11012 if (ret)
11013 return ERR_PTR(ret);
11014 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
11015 mutex_unlock(&dev->struct_mutex);
11016
11017 return fb;
11018 }
11019
11020 static u32
11021 intel_framebuffer_pitch_for_width(int width, int bpp)
11022 {
11023 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
11024 return ALIGN(pitch, 64);
11025 }
11026
11027 static u32
11028 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
11029 {
11030 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
11031 return PAGE_ALIGN(pitch * mode->vdisplay);
11032 }
11033
11034 static struct drm_framebuffer *
11035 intel_framebuffer_create_for_mode(struct drm_device *dev,
11036 struct drm_display_mode *mode,
11037 int depth, int bpp)
11038 {
11039 struct drm_framebuffer *fb;
11040 struct drm_i915_gem_object *obj;
11041 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
11042
11043 obj = i915_gem_object_create(dev,
11044 intel_framebuffer_size_for_mode(mode, bpp));
11045 if (IS_ERR(obj))
11046 return ERR_CAST(obj);
11047
11048 mode_cmd.width = mode->hdisplay;
11049 mode_cmd.height = mode->vdisplay;
11050 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
11051 bpp);
11052 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
11053
11054 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
11055 if (IS_ERR(fb))
11056 i915_gem_object_put_unlocked(obj);
11057
11058 return fb;
11059 }
11060
11061 static struct drm_framebuffer *
11062 mode_fits_in_fbdev(struct drm_device *dev,
11063 struct drm_display_mode *mode)
11064 {
11065 #ifdef CONFIG_DRM_FBDEV_EMULATION
11066 struct drm_i915_private *dev_priv = to_i915(dev);
11067 struct drm_i915_gem_object *obj;
11068 struct drm_framebuffer *fb;
11069
11070 if (!dev_priv->fbdev)
11071 return NULL;
11072
11073 if (!dev_priv->fbdev->fb)
11074 return NULL;
11075
11076 obj = dev_priv->fbdev->fb->obj;
11077 BUG_ON(!obj);
11078
11079 fb = &dev_priv->fbdev->fb->base;
11080 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
11081 fb->bits_per_pixel))
11082 return NULL;
11083
11084 if (obj->base.size < mode->vdisplay * fb->pitches[0])
11085 return NULL;
11086
11087 drm_framebuffer_reference(fb);
11088 return fb;
11089 #else
11090 return NULL;
11091 #endif
11092 }
11093
11094 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
11095 struct drm_crtc *crtc,
11096 struct drm_display_mode *mode,
11097 struct drm_framebuffer *fb,
11098 int x, int y)
11099 {
11100 struct drm_plane_state *plane_state;
11101 int hdisplay, vdisplay;
11102 int ret;
11103
11104 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
11105 if (IS_ERR(plane_state))
11106 return PTR_ERR(plane_state);
11107
11108 if (mode)
11109 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11110 else
11111 hdisplay = vdisplay = 0;
11112
11113 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
11114 if (ret)
11115 return ret;
11116 drm_atomic_set_fb_for_plane(plane_state, fb);
11117 plane_state->crtc_x = 0;
11118 plane_state->crtc_y = 0;
11119 plane_state->crtc_w = hdisplay;
11120 plane_state->crtc_h = vdisplay;
11121 plane_state->src_x = x << 16;
11122 plane_state->src_y = y << 16;
11123 plane_state->src_w = hdisplay << 16;
11124 plane_state->src_h = vdisplay << 16;
11125
11126 return 0;
11127 }
11128
11129 bool intel_get_load_detect_pipe(struct drm_connector *connector,
11130 struct drm_display_mode *mode,
11131 struct intel_load_detect_pipe *old,
11132 struct drm_modeset_acquire_ctx *ctx)
11133 {
11134 struct intel_crtc *intel_crtc;
11135 struct intel_encoder *intel_encoder =
11136 intel_attached_encoder(connector);
11137 struct drm_crtc *possible_crtc;
11138 struct drm_encoder *encoder = &intel_encoder->base;
11139 struct drm_crtc *crtc = NULL;
11140 struct drm_device *dev = encoder->dev;
11141 struct drm_framebuffer *fb;
11142 struct drm_mode_config *config = &dev->mode_config;
11143 struct drm_atomic_state *state = NULL, *restore_state = NULL;
11144 struct drm_connector_state *connector_state;
11145 struct intel_crtc_state *crtc_state;
11146 int ret, i = -1;
11147
11148 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11149 connector->base.id, connector->name,
11150 encoder->base.id, encoder->name);
11151
11152 old->restore_state = NULL;
11153
11154 retry:
11155 ret = drm_modeset_lock(&config->connection_mutex, ctx);
11156 if (ret)
11157 goto fail;
11158
11159 /*
11160 * Algorithm gets a little messy:
11161 *
11162 * - if the connector already has an assigned crtc, use it (but make
11163 * sure it's on first)
11164 *
11165 * - try to find the first unused crtc that can drive this connector,
11166 * and use that if we find one
11167 */
11168
11169 /* See if we already have a CRTC for this connector */
11170 if (connector->state->crtc) {
11171 crtc = connector->state->crtc;
11172
11173 ret = drm_modeset_lock(&crtc->mutex, ctx);
11174 if (ret)
11175 goto fail;
11176
11177 /* Make sure the crtc and connector are running */
11178 goto found;
11179 }
11180
11181 /* Find an unused one (if possible) */
11182 for_each_crtc(dev, possible_crtc) {
11183 i++;
11184 if (!(encoder->possible_crtcs & (1 << i)))
11185 continue;
11186
11187 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11188 if (ret)
11189 goto fail;
11190
11191 if (possible_crtc->state->enable) {
11192 drm_modeset_unlock(&possible_crtc->mutex);
11193 continue;
11194 }
11195
11196 crtc = possible_crtc;
11197 break;
11198 }
11199
11200 /*
11201 * If we didn't find an unused CRTC, don't use any.
11202 */
11203 if (!crtc) {
11204 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11205 goto fail;
11206 }
11207
11208 found:
11209 intel_crtc = to_intel_crtc(crtc);
11210
11211 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
11212 if (ret)
11213 goto fail;
11214
11215 state = drm_atomic_state_alloc(dev);
11216 restore_state = drm_atomic_state_alloc(dev);
11217 if (!state || !restore_state) {
11218 ret = -ENOMEM;
11219 goto fail;
11220 }
11221
11222 state->acquire_ctx = ctx;
11223 restore_state->acquire_ctx = ctx;
11224
11225 connector_state = drm_atomic_get_connector_state(state, connector);
11226 if (IS_ERR(connector_state)) {
11227 ret = PTR_ERR(connector_state);
11228 goto fail;
11229 }
11230
11231 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11232 if (ret)
11233 goto fail;
11234
11235 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11236 if (IS_ERR(crtc_state)) {
11237 ret = PTR_ERR(crtc_state);
11238 goto fail;
11239 }
11240
11241 crtc_state->base.active = crtc_state->base.enable = true;
11242
11243 if (!mode)
11244 mode = &load_detect_mode;
11245
11246 /* We need a framebuffer large enough to accommodate all accesses
11247 * that the plane may generate whilst we perform load detection.
11248 * We can not rely on the fbcon either being present (we get called
11249 * during its initialisation to detect all boot displays, or it may
11250 * not even exist) or that it is large enough to satisfy the
11251 * requested mode.
11252 */
11253 fb = mode_fits_in_fbdev(dev, mode);
11254 if (fb == NULL) {
11255 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
11256 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
11257 } else
11258 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
11259 if (IS_ERR(fb)) {
11260 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
11261 goto fail;
11262 }
11263
11264 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
11265 if (ret)
11266 goto fail;
11267
11268 drm_framebuffer_unreference(fb);
11269
11270 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
11271 if (ret)
11272 goto fail;
11273
11274 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11275 if (!ret)
11276 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11277 if (!ret)
11278 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
11279 if (ret) {
11280 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11281 goto fail;
11282 }
11283
11284 ret = drm_atomic_commit(state);
11285 if (ret) {
11286 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11287 goto fail;
11288 }
11289
11290 old->restore_state = restore_state;
11291
11292 /* let the connector get through one full cycle before testing */
11293 intel_wait_for_vblank(dev, intel_crtc->pipe);
11294 return true;
11295
11296 fail:
11297 drm_atomic_state_free(state);
11298 drm_atomic_state_free(restore_state);
11299 restore_state = state = NULL;
11300
11301 if (ret == -EDEADLK) {
11302 drm_modeset_backoff(ctx);
11303 goto retry;
11304 }
11305
11306 return false;
11307 }
11308
11309 void intel_release_load_detect_pipe(struct drm_connector *connector,
11310 struct intel_load_detect_pipe *old,
11311 struct drm_modeset_acquire_ctx *ctx)
11312 {
11313 struct intel_encoder *intel_encoder =
11314 intel_attached_encoder(connector);
11315 struct drm_encoder *encoder = &intel_encoder->base;
11316 struct drm_atomic_state *state = old->restore_state;
11317 int ret;
11318
11319 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11320 connector->base.id, connector->name,
11321 encoder->base.id, encoder->name);
11322
11323 if (!state)
11324 return;
11325
11326 ret = drm_atomic_commit(state);
11327 if (ret) {
11328 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11329 drm_atomic_state_free(state);
11330 }
11331 }
11332
11333 static int i9xx_pll_refclk(struct drm_device *dev,
11334 const struct intel_crtc_state *pipe_config)
11335 {
11336 struct drm_i915_private *dev_priv = to_i915(dev);
11337 u32 dpll = pipe_config->dpll_hw_state.dpll;
11338
11339 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11340 return dev_priv->vbt.lvds_ssc_freq;
11341 else if (HAS_PCH_SPLIT(dev))
11342 return 120000;
11343 else if (!IS_GEN2(dev))
11344 return 96000;
11345 else
11346 return 48000;
11347 }
11348
11349 /* Returns the clock of the currently programmed mode of the given pipe. */
11350 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11351 struct intel_crtc_state *pipe_config)
11352 {
11353 struct drm_device *dev = crtc->base.dev;
11354 struct drm_i915_private *dev_priv = to_i915(dev);
11355 int pipe = pipe_config->cpu_transcoder;
11356 u32 dpll = pipe_config->dpll_hw_state.dpll;
11357 u32 fp;
11358 struct dpll clock;
11359 int port_clock;
11360 int refclk = i9xx_pll_refclk(dev, pipe_config);
11361
11362 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11363 fp = pipe_config->dpll_hw_state.fp0;
11364 else
11365 fp = pipe_config->dpll_hw_state.fp1;
11366
11367 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11368 if (IS_PINEVIEW(dev)) {
11369 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11370 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11371 } else {
11372 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11373 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11374 }
11375
11376 if (!IS_GEN2(dev)) {
11377 if (IS_PINEVIEW(dev))
11378 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11379 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11380 else
11381 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11382 DPLL_FPA01_P1_POST_DIV_SHIFT);
11383
11384 switch (dpll & DPLL_MODE_MASK) {
11385 case DPLLB_MODE_DAC_SERIAL:
11386 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11387 5 : 10;
11388 break;
11389 case DPLLB_MODE_LVDS:
11390 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11391 7 : 14;
11392 break;
11393 default:
11394 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11395 "mode\n", (int)(dpll & DPLL_MODE_MASK));
11396 return;
11397 }
11398
11399 if (IS_PINEVIEW(dev))
11400 port_clock = pnv_calc_dpll_params(refclk, &clock);
11401 else
11402 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11403 } else {
11404 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
11405 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11406
11407 if (is_lvds) {
11408 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11409 DPLL_FPA01_P1_POST_DIV_SHIFT);
11410
11411 if (lvds & LVDS_CLKB_POWER_UP)
11412 clock.p2 = 7;
11413 else
11414 clock.p2 = 14;
11415 } else {
11416 if (dpll & PLL_P1_DIVIDE_BY_TWO)
11417 clock.p1 = 2;
11418 else {
11419 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11420 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11421 }
11422 if (dpll & PLL_P2_DIVIDE_BY_4)
11423 clock.p2 = 4;
11424 else
11425 clock.p2 = 2;
11426 }
11427
11428 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11429 }
11430
11431 /*
11432 * This value includes pixel_multiplier. We will use
11433 * port_clock to compute adjusted_mode.crtc_clock in the
11434 * encoder's get_config() function.
11435 */
11436 pipe_config->port_clock = port_clock;
11437 }
11438
11439 int intel_dotclock_calculate(int link_freq,
11440 const struct intel_link_m_n *m_n)
11441 {
11442 /*
11443 * The calculation for the data clock is:
11444 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11445 * But we want to avoid losing precison if possible, so:
11446 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11447 *
11448 * and the link clock is simpler:
11449 * link_clock = (m * link_clock) / n
11450 */
11451
11452 if (!m_n->link_n)
11453 return 0;
11454
11455 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
11456 }
11457
11458 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11459 struct intel_crtc_state *pipe_config)
11460 {
11461 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11462
11463 /* read out port_clock from the DPLL */
11464 i9xx_crtc_clock_get(crtc, pipe_config);
11465
11466 /*
11467 * In case there is an active pipe without active ports,
11468 * we may need some idea for the dotclock anyway.
11469 * Calculate one based on the FDI configuration.
11470 */
11471 pipe_config->base.adjusted_mode.crtc_clock =
11472 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11473 &pipe_config->fdi_m_n);
11474 }
11475
11476 /** Returns the currently programmed mode of the given pipe. */
11477 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
11478 struct drm_crtc *crtc)
11479 {
11480 struct drm_i915_private *dev_priv = to_i915(dev);
11481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11482 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
11483 struct drm_display_mode *mode;
11484 struct intel_crtc_state *pipe_config;
11485 int htot = I915_READ(HTOTAL(cpu_transcoder));
11486 int hsync = I915_READ(HSYNC(cpu_transcoder));
11487 int vtot = I915_READ(VTOTAL(cpu_transcoder));
11488 int vsync = I915_READ(VSYNC(cpu_transcoder));
11489 enum pipe pipe = intel_crtc->pipe;
11490
11491 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11492 if (!mode)
11493 return NULL;
11494
11495 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
11496 if (!pipe_config) {
11497 kfree(mode);
11498 return NULL;
11499 }
11500
11501 /*
11502 * Construct a pipe_config sufficient for getting the clock info
11503 * back out of crtc_clock_get.
11504 *
11505 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
11506 * to use a real value here instead.
11507 */
11508 pipe_config->cpu_transcoder = (enum transcoder) pipe;
11509 pipe_config->pixel_multiplier = 1;
11510 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
11511 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
11512 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
11513 i9xx_crtc_clock_get(intel_crtc, pipe_config);
11514
11515 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
11516 mode->hdisplay = (htot & 0xffff) + 1;
11517 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
11518 mode->hsync_start = (hsync & 0xffff) + 1;
11519 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
11520 mode->vdisplay = (vtot & 0xffff) + 1;
11521 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
11522 mode->vsync_start = (vsync & 0xffff) + 1;
11523 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
11524
11525 drm_mode_set_name(mode);
11526
11527 kfree(pipe_config);
11528
11529 return mode;
11530 }
11531
11532 static void intel_crtc_destroy(struct drm_crtc *crtc)
11533 {
11534 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11535 struct drm_device *dev = crtc->dev;
11536 struct intel_flip_work *work;
11537
11538 spin_lock_irq(&dev->event_lock);
11539 work = intel_crtc->flip_work;
11540 intel_crtc->flip_work = NULL;
11541 spin_unlock_irq(&dev->event_lock);
11542
11543 if (work) {
11544 cancel_work_sync(&work->mmio_work);
11545 cancel_work_sync(&work->unpin_work);
11546 kfree(work);
11547 }
11548
11549 drm_crtc_cleanup(crtc);
11550
11551 kfree(intel_crtc);
11552 }
11553
11554 static void intel_unpin_work_fn(struct work_struct *__work)
11555 {
11556 struct intel_flip_work *work =
11557 container_of(__work, struct intel_flip_work, unpin_work);
11558 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11559 struct drm_device *dev = crtc->base.dev;
11560 struct drm_plane *primary = crtc->base.primary;
11561
11562 if (is_mmio_work(work))
11563 flush_work(&work->mmio_work);
11564
11565 mutex_lock(&dev->struct_mutex);
11566 intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
11567 i915_gem_object_put(work->pending_flip_obj);
11568 mutex_unlock(&dev->struct_mutex);
11569
11570 i915_gem_request_put(work->flip_queued_req);
11571
11572 intel_frontbuffer_flip_complete(to_i915(dev),
11573 to_intel_plane(primary)->frontbuffer_bit);
11574 intel_fbc_post_update(crtc);
11575 drm_framebuffer_unreference(work->old_fb);
11576
11577 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11578 atomic_dec(&crtc->unpin_work_count);
11579
11580 kfree(work);
11581 }
11582
11583 /* Is 'a' after or equal to 'b'? */
11584 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11585 {
11586 return !((a - b) & 0x80000000);
11587 }
11588
11589 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11590 struct intel_flip_work *work)
11591 {
11592 struct drm_device *dev = crtc->base.dev;
11593 struct drm_i915_private *dev_priv = to_i915(dev);
11594
11595 if (abort_flip_on_reset(crtc))
11596 return true;
11597
11598 /*
11599 * The relevant registers doen't exist on pre-ctg.
11600 * As the flip done interrupt doesn't trigger for mmio
11601 * flips on gmch platforms, a flip count check isn't
11602 * really needed there. But since ctg has the registers,
11603 * include it in the check anyway.
11604 */
11605 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
11606 return true;
11607
11608 /*
11609 * BDW signals flip done immediately if the plane
11610 * is disabled, even if the plane enable is already
11611 * armed to occur at the next vblank :(
11612 */
11613
11614 /*
11615 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11616 * used the same base address. In that case the mmio flip might
11617 * have completed, but the CS hasn't even executed the flip yet.
11618 *
11619 * A flip count check isn't enough as the CS might have updated
11620 * the base address just after start of vblank, but before we
11621 * managed to process the interrupt. This means we'd complete the
11622 * CS flip too soon.
11623 *
11624 * Combining both checks should get us a good enough result. It may
11625 * still happen that the CS flip has been executed, but has not
11626 * yet actually completed. But in case the base address is the same
11627 * anyway, we don't really care.
11628 */
11629 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11630 crtc->flip_work->gtt_offset &&
11631 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11632 crtc->flip_work->flip_count);
11633 }
11634
11635 static bool
11636 __pageflip_finished_mmio(struct intel_crtc *crtc,
11637 struct intel_flip_work *work)
11638 {
11639 /*
11640 * MMIO work completes when vblank is different from
11641 * flip_queued_vblank.
11642 *
11643 * Reset counter value doesn't matter, this is handled by
11644 * i915_wait_request finishing early, so no need to handle
11645 * reset here.
11646 */
11647 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11648 }
11649
11650
11651 static bool pageflip_finished(struct intel_crtc *crtc,
11652 struct intel_flip_work *work)
11653 {
11654 if (!atomic_read(&work->pending))
11655 return false;
11656
11657 smp_rmb();
11658
11659 if (is_mmio_work(work))
11660 return __pageflip_finished_mmio(crtc, work);
11661 else
11662 return __pageflip_finished_cs(crtc, work);
11663 }
11664
11665 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11666 {
11667 struct drm_device *dev = &dev_priv->drm;
11668 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11669 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11670 struct intel_flip_work *work;
11671 unsigned long flags;
11672
11673 /* Ignore early vblank irqs */
11674 if (!crtc)
11675 return;
11676
11677 /*
11678 * This is called both by irq handlers and the reset code (to complete
11679 * lost pageflips) so needs the full irqsave spinlocks.
11680 */
11681 spin_lock_irqsave(&dev->event_lock, flags);
11682 work = intel_crtc->flip_work;
11683
11684 if (work != NULL &&
11685 !is_mmio_work(work) &&
11686 pageflip_finished(intel_crtc, work))
11687 page_flip_completed(intel_crtc);
11688
11689 spin_unlock_irqrestore(&dev->event_lock, flags);
11690 }
11691
11692 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11693 {
11694 struct drm_device *dev = &dev_priv->drm;
11695 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11697 struct intel_flip_work *work;
11698 unsigned long flags;
11699
11700 /* Ignore early vblank irqs */
11701 if (!crtc)
11702 return;
11703
11704 /*
11705 * This is called both by irq handlers and the reset code (to complete
11706 * lost pageflips) so needs the full irqsave spinlocks.
11707 */
11708 spin_lock_irqsave(&dev->event_lock, flags);
11709 work = intel_crtc->flip_work;
11710
11711 if (work != NULL &&
11712 is_mmio_work(work) &&
11713 pageflip_finished(intel_crtc, work))
11714 page_flip_completed(intel_crtc);
11715
11716 spin_unlock_irqrestore(&dev->event_lock, flags);
11717 }
11718
11719 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11720 struct intel_flip_work *work)
11721 {
11722 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11723
11724 /* Ensure that the work item is consistent when activating it ... */
11725 smp_mb__before_atomic();
11726 atomic_set(&work->pending, 1);
11727 }
11728
11729 static int intel_gen2_queue_flip(struct drm_device *dev,
11730 struct drm_crtc *crtc,
11731 struct drm_framebuffer *fb,
11732 struct drm_i915_gem_object *obj,
11733 struct drm_i915_gem_request *req,
11734 uint32_t flags)
11735 {
11736 struct intel_ring *ring = req->ring;
11737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11738 u32 flip_mask;
11739 int ret;
11740
11741 ret = intel_ring_begin(req, 6);
11742 if (ret)
11743 return ret;
11744
11745 /* Can't queue multiple flips, so wait for the previous
11746 * one to finish before executing the next.
11747 */
11748 if (intel_crtc->plane)
11749 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11750 else
11751 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11752 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11753 intel_ring_emit(ring, MI_NOOP);
11754 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11755 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11756 intel_ring_emit(ring, fb->pitches[0]);
11757 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11758 intel_ring_emit(ring, 0); /* aux display base address, unused */
11759
11760 return 0;
11761 }
11762
11763 static int intel_gen3_queue_flip(struct drm_device *dev,
11764 struct drm_crtc *crtc,
11765 struct drm_framebuffer *fb,
11766 struct drm_i915_gem_object *obj,
11767 struct drm_i915_gem_request *req,
11768 uint32_t flags)
11769 {
11770 struct intel_ring *ring = req->ring;
11771 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11772 u32 flip_mask;
11773 int ret;
11774
11775 ret = intel_ring_begin(req, 6);
11776 if (ret)
11777 return ret;
11778
11779 if (intel_crtc->plane)
11780 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11781 else
11782 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11783 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11784 intel_ring_emit(ring, MI_NOOP);
11785 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11786 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11787 intel_ring_emit(ring, fb->pitches[0]);
11788 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11789 intel_ring_emit(ring, MI_NOOP);
11790
11791 return 0;
11792 }
11793
11794 static int intel_gen4_queue_flip(struct drm_device *dev,
11795 struct drm_crtc *crtc,
11796 struct drm_framebuffer *fb,
11797 struct drm_i915_gem_object *obj,
11798 struct drm_i915_gem_request *req,
11799 uint32_t flags)
11800 {
11801 struct intel_ring *ring = req->ring;
11802 struct drm_i915_private *dev_priv = to_i915(dev);
11803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11804 uint32_t pf, pipesrc;
11805 int ret;
11806
11807 ret = intel_ring_begin(req, 4);
11808 if (ret)
11809 return ret;
11810
11811 /* i965+ uses the linear or tiled offsets from the
11812 * Display Registers (which do not change across a page-flip)
11813 * so we need only reprogram the base address.
11814 */
11815 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11816 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11817 intel_ring_emit(ring, fb->pitches[0]);
11818 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset |
11819 intel_fb_modifier_to_tiling(fb->modifier[0]));
11820
11821 /* XXX Enabling the panel-fitter across page-flip is so far
11822 * untested on non-native modes, so ignore it for now.
11823 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11824 */
11825 pf = 0;
11826 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11827 intel_ring_emit(ring, pf | pipesrc);
11828
11829 return 0;
11830 }
11831
11832 static int intel_gen6_queue_flip(struct drm_device *dev,
11833 struct drm_crtc *crtc,
11834 struct drm_framebuffer *fb,
11835 struct drm_i915_gem_object *obj,
11836 struct drm_i915_gem_request *req,
11837 uint32_t flags)
11838 {
11839 struct intel_ring *ring = req->ring;
11840 struct drm_i915_private *dev_priv = to_i915(dev);
11841 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11842 uint32_t pf, pipesrc;
11843 int ret;
11844
11845 ret = intel_ring_begin(req, 4);
11846 if (ret)
11847 return ret;
11848
11849 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11850 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11851 intel_ring_emit(ring, fb->pitches[0] |
11852 intel_fb_modifier_to_tiling(fb->modifier[0]));
11853 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11854
11855 /* Contrary to the suggestions in the documentation,
11856 * "Enable Panel Fitter" does not seem to be required when page
11857 * flipping with a non-native mode, and worse causes a normal
11858 * modeset to fail.
11859 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11860 */
11861 pf = 0;
11862 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11863 intel_ring_emit(ring, pf | pipesrc);
11864
11865 return 0;
11866 }
11867
11868 static int intel_gen7_queue_flip(struct drm_device *dev,
11869 struct drm_crtc *crtc,
11870 struct drm_framebuffer *fb,
11871 struct drm_i915_gem_object *obj,
11872 struct drm_i915_gem_request *req,
11873 uint32_t flags)
11874 {
11875 struct intel_ring *ring = req->ring;
11876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11877 uint32_t plane_bit = 0;
11878 int len, ret;
11879
11880 switch (intel_crtc->plane) {
11881 case PLANE_A:
11882 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11883 break;
11884 case PLANE_B:
11885 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11886 break;
11887 case PLANE_C:
11888 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11889 break;
11890 default:
11891 WARN_ONCE(1, "unknown plane in flip command\n");
11892 return -ENODEV;
11893 }
11894
11895 len = 4;
11896 if (req->engine->id == RCS) {
11897 len += 6;
11898 /*
11899 * On Gen 8, SRM is now taking an extra dword to accommodate
11900 * 48bits addresses, and we need a NOOP for the batch size to
11901 * stay even.
11902 */
11903 if (IS_GEN8(dev))
11904 len += 2;
11905 }
11906
11907 /*
11908 * BSpec MI_DISPLAY_FLIP for IVB:
11909 * "The full packet must be contained within the same cache line."
11910 *
11911 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11912 * cacheline, if we ever start emitting more commands before
11913 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11914 * then do the cacheline alignment, and finally emit the
11915 * MI_DISPLAY_FLIP.
11916 */
11917 ret = intel_ring_cacheline_align(req);
11918 if (ret)
11919 return ret;
11920
11921 ret = intel_ring_begin(req, len);
11922 if (ret)
11923 return ret;
11924
11925 /* Unmask the flip-done completion message. Note that the bspec says that
11926 * we should do this for both the BCS and RCS, and that we must not unmask
11927 * more than one flip event at any time (or ensure that one flip message
11928 * can be sent by waiting for flip-done prior to queueing new flips).
11929 * Experimentation says that BCS works despite DERRMR masking all
11930 * flip-done completion events and that unmasking all planes at once
11931 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11932 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11933 */
11934 if (req->engine->id == RCS) {
11935 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11936 intel_ring_emit_reg(ring, DERRMR);
11937 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11938 DERRMR_PIPEB_PRI_FLIP_DONE |
11939 DERRMR_PIPEC_PRI_FLIP_DONE));
11940 if (IS_GEN8(dev))
11941 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11942 MI_SRM_LRM_GLOBAL_GTT);
11943 else
11944 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11945 MI_SRM_LRM_GLOBAL_GTT);
11946 intel_ring_emit_reg(ring, DERRMR);
11947 intel_ring_emit(ring,
11948 i915_ggtt_offset(req->engine->scratch) + 256);
11949 if (IS_GEN8(dev)) {
11950 intel_ring_emit(ring, 0);
11951 intel_ring_emit(ring, MI_NOOP);
11952 }
11953 }
11954
11955 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11956 intel_ring_emit(ring, fb->pitches[0] |
11957 intel_fb_modifier_to_tiling(fb->modifier[0]));
11958 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11959 intel_ring_emit(ring, (MI_NOOP));
11960
11961 return 0;
11962 }
11963
11964 static bool use_mmio_flip(struct intel_engine_cs *engine,
11965 struct drm_i915_gem_object *obj)
11966 {
11967 struct reservation_object *resv;
11968
11969 /*
11970 * This is not being used for older platforms, because
11971 * non-availability of flip done interrupt forces us to use
11972 * CS flips. Older platforms derive flip done using some clever
11973 * tricks involving the flip_pending status bits and vblank irqs.
11974 * So using MMIO flips there would disrupt this mechanism.
11975 */
11976
11977 if (engine == NULL)
11978 return true;
11979
11980 if (INTEL_GEN(engine->i915) < 5)
11981 return false;
11982
11983 if (i915.use_mmio_flip < 0)
11984 return false;
11985 else if (i915.use_mmio_flip > 0)
11986 return true;
11987 else if (i915.enable_execlists)
11988 return true;
11989
11990 resv = i915_gem_object_get_dmabuf_resv(obj);
11991 if (resv && !reservation_object_test_signaled_rcu(resv, false))
11992 return true;
11993
11994 return engine != i915_gem_active_get_engine(&obj->last_write,
11995 &obj->base.dev->struct_mutex);
11996 }
11997
11998 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11999 unsigned int rotation,
12000 struct intel_flip_work *work)
12001 {
12002 struct drm_device *dev = intel_crtc->base.dev;
12003 struct drm_i915_private *dev_priv = to_i915(dev);
12004 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
12005 const enum pipe pipe = intel_crtc->pipe;
12006 u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
12007
12008 ctl = I915_READ(PLANE_CTL(pipe, 0));
12009 ctl &= ~PLANE_CTL_TILED_MASK;
12010 switch (fb->modifier[0]) {
12011 case DRM_FORMAT_MOD_NONE:
12012 break;
12013 case I915_FORMAT_MOD_X_TILED:
12014 ctl |= PLANE_CTL_TILED_X;
12015 break;
12016 case I915_FORMAT_MOD_Y_TILED:
12017 ctl |= PLANE_CTL_TILED_Y;
12018 break;
12019 case I915_FORMAT_MOD_Yf_TILED:
12020 ctl |= PLANE_CTL_TILED_YF;
12021 break;
12022 default:
12023 MISSING_CASE(fb->modifier[0]);
12024 }
12025
12026 /*
12027 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
12028 * PLANE_SURF updates, the update is then guaranteed to be atomic.
12029 */
12030 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
12031 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
12032
12033 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
12034 POSTING_READ(PLANE_SURF(pipe, 0));
12035 }
12036
12037 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
12038 struct intel_flip_work *work)
12039 {
12040 struct drm_device *dev = intel_crtc->base.dev;
12041 struct drm_i915_private *dev_priv = to_i915(dev);
12042 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
12043 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
12044 u32 dspcntr;
12045
12046 dspcntr = I915_READ(reg);
12047
12048 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
12049 dspcntr |= DISPPLANE_TILED;
12050 else
12051 dspcntr &= ~DISPPLANE_TILED;
12052
12053 I915_WRITE(reg, dspcntr);
12054
12055 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
12056 POSTING_READ(DSPSURF(intel_crtc->plane));
12057 }
12058
12059 static void intel_mmio_flip_work_func(struct work_struct *w)
12060 {
12061 struct intel_flip_work *work =
12062 container_of(w, struct intel_flip_work, mmio_work);
12063 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
12064 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12065 struct intel_framebuffer *intel_fb =
12066 to_intel_framebuffer(crtc->base.primary->fb);
12067 struct drm_i915_gem_object *obj = intel_fb->obj;
12068 struct reservation_object *resv;
12069
12070 if (work->flip_queued_req)
12071 WARN_ON(i915_wait_request(work->flip_queued_req,
12072 0, NULL, NO_WAITBOOST));
12073
12074 /* For framebuffer backed by dmabuf, wait for fence */
12075 resv = i915_gem_object_get_dmabuf_resv(obj);
12076 if (resv)
12077 WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false,
12078 MAX_SCHEDULE_TIMEOUT) < 0);
12079
12080 intel_pipe_update_start(crtc);
12081
12082 if (INTEL_GEN(dev_priv) >= 9)
12083 skl_do_mmio_flip(crtc, work->rotation, work);
12084 else
12085 /* use_mmio_flip() retricts MMIO flips to ilk+ */
12086 ilk_do_mmio_flip(crtc, work);
12087
12088 intel_pipe_update_end(crtc, work);
12089 }
12090
12091 static int intel_default_queue_flip(struct drm_device *dev,
12092 struct drm_crtc *crtc,
12093 struct drm_framebuffer *fb,
12094 struct drm_i915_gem_object *obj,
12095 struct drm_i915_gem_request *req,
12096 uint32_t flags)
12097 {
12098 return -ENODEV;
12099 }
12100
12101 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
12102 struct intel_crtc *intel_crtc,
12103 struct intel_flip_work *work)
12104 {
12105 u32 addr, vblank;
12106
12107 if (!atomic_read(&work->pending))
12108 return false;
12109
12110 smp_rmb();
12111
12112 vblank = intel_crtc_get_vblank_counter(intel_crtc);
12113 if (work->flip_ready_vblank == 0) {
12114 if (work->flip_queued_req &&
12115 !i915_gem_request_completed(work->flip_queued_req))
12116 return false;
12117
12118 work->flip_ready_vblank = vblank;
12119 }
12120
12121 if (vblank - work->flip_ready_vblank < 3)
12122 return false;
12123
12124 /* Potential stall - if we see that the flip has happened,
12125 * assume a missed interrupt. */
12126 if (INTEL_GEN(dev_priv) >= 4)
12127 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
12128 else
12129 addr = I915_READ(DSPADDR(intel_crtc->plane));
12130
12131 /* There is a potential issue here with a false positive after a flip
12132 * to the same address. We could address this by checking for a
12133 * non-incrementing frame counter.
12134 */
12135 return addr == work->gtt_offset;
12136 }
12137
12138 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
12139 {
12140 struct drm_device *dev = &dev_priv->drm;
12141 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
12142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12143 struct intel_flip_work *work;
12144
12145 WARN_ON(!in_interrupt());
12146
12147 if (crtc == NULL)
12148 return;
12149
12150 spin_lock(&dev->event_lock);
12151 work = intel_crtc->flip_work;
12152
12153 if (work != NULL && !is_mmio_work(work) &&
12154 __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) {
12155 WARN_ONCE(1,
12156 "Kicking stuck page flip: queued at %d, now %d\n",
12157 work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc));
12158 page_flip_completed(intel_crtc);
12159 work = NULL;
12160 }
12161
12162 if (work != NULL && !is_mmio_work(work) &&
12163 intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1)
12164 intel_queue_rps_boost_for_request(work->flip_queued_req);
12165 spin_unlock(&dev->event_lock);
12166 }
12167
12168 static int intel_crtc_page_flip(struct drm_crtc *crtc,
12169 struct drm_framebuffer *fb,
12170 struct drm_pending_vblank_event *event,
12171 uint32_t page_flip_flags)
12172 {
12173 struct drm_device *dev = crtc->dev;
12174 struct drm_i915_private *dev_priv = to_i915(dev);
12175 struct drm_framebuffer *old_fb = crtc->primary->fb;
12176 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12178 struct drm_plane *primary = crtc->primary;
12179 enum pipe pipe = intel_crtc->pipe;
12180 struct intel_flip_work *work;
12181 struct intel_engine_cs *engine;
12182 bool mmio_flip;
12183 struct drm_i915_gem_request *request;
12184 struct i915_vma *vma;
12185 int ret;
12186
12187 /*
12188 * drm_mode_page_flip_ioctl() should already catch this, but double
12189 * check to be safe. In the future we may enable pageflipping from
12190 * a disabled primary plane.
12191 */
12192 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
12193 return -EBUSY;
12194
12195 /* Can't change pixel format via MI display flips. */
12196 if (fb->pixel_format != crtc->primary->fb->pixel_format)
12197 return -EINVAL;
12198
12199 /*
12200 * TILEOFF/LINOFF registers can't be changed via MI display flips.
12201 * Note that pitch changes could also affect these register.
12202 */
12203 if (INTEL_INFO(dev)->gen > 3 &&
12204 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
12205 fb->pitches[0] != crtc->primary->fb->pitches[0]))
12206 return -EINVAL;
12207
12208 if (i915_terminally_wedged(&dev_priv->gpu_error))
12209 goto out_hang;
12210
12211 work = kzalloc(sizeof(*work), GFP_KERNEL);
12212 if (work == NULL)
12213 return -ENOMEM;
12214
12215 work->event = event;
12216 work->crtc = crtc;
12217 work->old_fb = old_fb;
12218 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
12219
12220 ret = drm_crtc_vblank_get(crtc);
12221 if (ret)
12222 goto free_work;
12223
12224 /* We borrow the event spin lock for protecting flip_work */
12225 spin_lock_irq(&dev->event_lock);
12226 if (intel_crtc->flip_work) {
12227 /* Before declaring the flip queue wedged, check if
12228 * the hardware completed the operation behind our backs.
12229 */
12230 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
12231 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
12232 page_flip_completed(intel_crtc);
12233 } else {
12234 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
12235 spin_unlock_irq(&dev->event_lock);
12236
12237 drm_crtc_vblank_put(crtc);
12238 kfree(work);
12239 return -EBUSY;
12240 }
12241 }
12242 intel_crtc->flip_work = work;
12243 spin_unlock_irq(&dev->event_lock);
12244
12245 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
12246 flush_workqueue(dev_priv->wq);
12247
12248 /* Reference the objects for the scheduled work. */
12249 drm_framebuffer_reference(work->old_fb);
12250
12251 crtc->primary->fb = fb;
12252 update_state_fb(crtc->primary);
12253
12254 work->pending_flip_obj = i915_gem_object_get(obj);
12255
12256 ret = i915_mutex_lock_interruptible(dev);
12257 if (ret)
12258 goto cleanup;
12259
12260 intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
12261 if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) {
12262 ret = -EIO;
12263 goto cleanup;
12264 }
12265
12266 atomic_inc(&intel_crtc->unpin_work_count);
12267
12268 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
12269 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
12270
12271 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
12272 engine = &dev_priv->engine[BCS];
12273 if (fb->modifier[0] != old_fb->modifier[0])
12274 /* vlv: DISPLAY_FLIP fails to change tiling */
12275 engine = NULL;
12276 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
12277 engine = &dev_priv->engine[BCS];
12278 } else if (INTEL_INFO(dev)->gen >= 7) {
12279 engine = i915_gem_active_get_engine(&obj->last_write,
12280 &obj->base.dev->struct_mutex);
12281 if (engine == NULL || engine->id != RCS)
12282 engine = &dev_priv->engine[BCS];
12283 } else {
12284 engine = &dev_priv->engine[RCS];
12285 }
12286
12287 mmio_flip = use_mmio_flip(engine, obj);
12288
12289 vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
12290 if (IS_ERR(vma)) {
12291 ret = PTR_ERR(vma);
12292 goto cleanup_pending;
12293 }
12294
12295 work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation);
12296 work->gtt_offset += intel_crtc->dspaddr_offset;
12297 work->rotation = crtc->primary->state->rotation;
12298
12299 /*
12300 * There's the potential that the next frame will not be compatible with
12301 * FBC, so we want to call pre_update() before the actual page flip.
12302 * The problem is that pre_update() caches some information about the fb
12303 * object, so we want to do this only after the object is pinned. Let's
12304 * be on the safe side and do this immediately before scheduling the
12305 * flip.
12306 */
12307 intel_fbc_pre_update(intel_crtc, intel_crtc->config,
12308 to_intel_plane_state(primary->state));
12309
12310 if (mmio_flip) {
12311 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
12312
12313 work->flip_queued_req = i915_gem_active_get(&obj->last_write,
12314 &obj->base.dev->struct_mutex);
12315 schedule_work(&work->mmio_work);
12316 } else {
12317 request = i915_gem_request_alloc(engine, engine->last_context);
12318 if (IS_ERR(request)) {
12319 ret = PTR_ERR(request);
12320 goto cleanup_unpin;
12321 }
12322
12323 ret = i915_gem_request_await_object(request, obj, false);
12324 if (ret)
12325 goto cleanup_request;
12326
12327 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
12328 page_flip_flags);
12329 if (ret)
12330 goto cleanup_request;
12331
12332 intel_mark_page_flip_active(intel_crtc, work);
12333
12334 work->flip_queued_req = i915_gem_request_get(request);
12335 i915_add_request_no_flush(request);
12336 }
12337
12338 i915_gem_track_fb(intel_fb_obj(old_fb), obj,
12339 to_intel_plane(primary)->frontbuffer_bit);
12340 mutex_unlock(&dev->struct_mutex);
12341
12342 intel_frontbuffer_flip_prepare(to_i915(dev),
12343 to_intel_plane(primary)->frontbuffer_bit);
12344
12345 trace_i915_flip_request(intel_crtc->plane, obj);
12346
12347 return 0;
12348
12349 cleanup_request:
12350 i915_add_request_no_flush(request);
12351 cleanup_unpin:
12352 intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
12353 cleanup_pending:
12354 atomic_dec(&intel_crtc->unpin_work_count);
12355 mutex_unlock(&dev->struct_mutex);
12356 cleanup:
12357 crtc->primary->fb = old_fb;
12358 update_state_fb(crtc->primary);
12359
12360 i915_gem_object_put_unlocked(obj);
12361 drm_framebuffer_unreference(work->old_fb);
12362
12363 spin_lock_irq(&dev->event_lock);
12364 intel_crtc->flip_work = NULL;
12365 spin_unlock_irq(&dev->event_lock);
12366
12367 drm_crtc_vblank_put(crtc);
12368 free_work:
12369 kfree(work);
12370
12371 if (ret == -EIO) {
12372 struct drm_atomic_state *state;
12373 struct drm_plane_state *plane_state;
12374
12375 out_hang:
12376 state = drm_atomic_state_alloc(dev);
12377 if (!state)
12378 return -ENOMEM;
12379 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
12380
12381 retry:
12382 plane_state = drm_atomic_get_plane_state(state, primary);
12383 ret = PTR_ERR_OR_ZERO(plane_state);
12384 if (!ret) {
12385 drm_atomic_set_fb_for_plane(plane_state, fb);
12386
12387 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
12388 if (!ret)
12389 ret = drm_atomic_commit(state);
12390 }
12391
12392 if (ret == -EDEADLK) {
12393 drm_modeset_backoff(state->acquire_ctx);
12394 drm_atomic_state_clear(state);
12395 goto retry;
12396 }
12397
12398 if (ret)
12399 drm_atomic_state_free(state);
12400
12401 if (ret == 0 && event) {
12402 spin_lock_irq(&dev->event_lock);
12403 drm_crtc_send_vblank_event(crtc, event);
12404 spin_unlock_irq(&dev->event_lock);
12405 }
12406 }
12407 return ret;
12408 }
12409
12410
12411 /**
12412 * intel_wm_need_update - Check whether watermarks need updating
12413 * @plane: drm plane
12414 * @state: new plane state
12415 *
12416 * Check current plane state versus the new one to determine whether
12417 * watermarks need to be recalculated.
12418 *
12419 * Returns true or false.
12420 */
12421 static bool intel_wm_need_update(struct drm_plane *plane,
12422 struct drm_plane_state *state)
12423 {
12424 struct intel_plane_state *new = to_intel_plane_state(state);
12425 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
12426
12427 /* Update watermarks on tiling or size changes. */
12428 if (new->base.visible != cur->base.visible)
12429 return true;
12430
12431 if (!cur->base.fb || !new->base.fb)
12432 return false;
12433
12434 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
12435 cur->base.rotation != new->base.rotation ||
12436 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
12437 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
12438 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
12439 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
12440 return true;
12441
12442 return false;
12443 }
12444
12445 static bool needs_scaling(struct intel_plane_state *state)
12446 {
12447 int src_w = drm_rect_width(&state->base.src) >> 16;
12448 int src_h = drm_rect_height(&state->base.src) >> 16;
12449 int dst_w = drm_rect_width(&state->base.dst);
12450 int dst_h = drm_rect_height(&state->base.dst);
12451
12452 return (src_w != dst_w || src_h != dst_h);
12453 }
12454
12455 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
12456 struct drm_plane_state *plane_state)
12457 {
12458 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
12459 struct drm_crtc *crtc = crtc_state->crtc;
12460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12461 struct drm_plane *plane = plane_state->plane;
12462 struct drm_device *dev = crtc->dev;
12463 struct drm_i915_private *dev_priv = to_i915(dev);
12464 struct intel_plane_state *old_plane_state =
12465 to_intel_plane_state(plane->state);
12466 bool mode_changed = needs_modeset(crtc_state);
12467 bool was_crtc_enabled = crtc->state->active;
12468 bool is_crtc_enabled = crtc_state->active;
12469 bool turn_off, turn_on, visible, was_visible;
12470 struct drm_framebuffer *fb = plane_state->fb;
12471 int ret;
12472
12473 if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
12474 ret = skl_update_scaler_plane(
12475 to_intel_crtc_state(crtc_state),
12476 to_intel_plane_state(plane_state));
12477 if (ret)
12478 return ret;
12479 }
12480
12481 was_visible = old_plane_state->base.visible;
12482 visible = to_intel_plane_state(plane_state)->base.visible;
12483
12484 if (!was_crtc_enabled && WARN_ON(was_visible))
12485 was_visible = false;
12486
12487 /*
12488 * Visibility is calculated as if the crtc was on, but
12489 * after scaler setup everything depends on it being off
12490 * when the crtc isn't active.
12491 *
12492 * FIXME this is wrong for watermarks. Watermarks should also
12493 * be computed as if the pipe would be active. Perhaps move
12494 * per-plane wm computation to the .check_plane() hook, and
12495 * only combine the results from all planes in the current place?
12496 */
12497 if (!is_crtc_enabled)
12498 to_intel_plane_state(plane_state)->base.visible = visible = false;
12499
12500 if (!was_visible && !visible)
12501 return 0;
12502
12503 if (fb != old_plane_state->base.fb)
12504 pipe_config->fb_changed = true;
12505
12506 turn_off = was_visible && (!visible || mode_changed);
12507 turn_on = visible && (!was_visible || mode_changed);
12508
12509 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
12510 intel_crtc->base.base.id,
12511 intel_crtc->base.name,
12512 plane->base.id, plane->name,
12513 fb ? fb->base.id : -1);
12514
12515 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12516 plane->base.id, plane->name,
12517 was_visible, visible,
12518 turn_off, turn_on, mode_changed);
12519
12520 if (turn_on) {
12521 pipe_config->update_wm_pre = true;
12522
12523 /* must disable cxsr around plane enable/disable */
12524 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12525 pipe_config->disable_cxsr = true;
12526 } else if (turn_off) {
12527 pipe_config->update_wm_post = true;
12528
12529 /* must disable cxsr around plane enable/disable */
12530 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12531 pipe_config->disable_cxsr = true;
12532 } else if (intel_wm_need_update(plane, plane_state)) {
12533 /* FIXME bollocks */
12534 pipe_config->update_wm_pre = true;
12535 pipe_config->update_wm_post = true;
12536 }
12537
12538 /* Pre-gen9 platforms need two-step watermark updates */
12539 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12540 INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
12541 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12542
12543 if (visible || was_visible)
12544 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
12545
12546 /*
12547 * WaCxSRDisabledForSpriteScaling:ivb
12548 *
12549 * cstate->update_wm was already set above, so this flag will
12550 * take effect when we commit and program watermarks.
12551 */
12552 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
12553 needs_scaling(to_intel_plane_state(plane_state)) &&
12554 !needs_scaling(old_plane_state))
12555 pipe_config->disable_lp_wm = true;
12556
12557 return 0;
12558 }
12559
12560 static bool encoders_cloneable(const struct intel_encoder *a,
12561 const struct intel_encoder *b)
12562 {
12563 /* masks could be asymmetric, so check both ways */
12564 return a == b || (a->cloneable & (1 << b->type) &&
12565 b->cloneable & (1 << a->type));
12566 }
12567
12568 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12569 struct intel_crtc *crtc,
12570 struct intel_encoder *encoder)
12571 {
12572 struct intel_encoder *source_encoder;
12573 struct drm_connector *connector;
12574 struct drm_connector_state *connector_state;
12575 int i;
12576
12577 for_each_connector_in_state(state, connector, connector_state, i) {
12578 if (connector_state->crtc != &crtc->base)
12579 continue;
12580
12581 source_encoder =
12582 to_intel_encoder(connector_state->best_encoder);
12583 if (!encoders_cloneable(encoder, source_encoder))
12584 return false;
12585 }
12586
12587 return true;
12588 }
12589
12590 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12591 struct drm_crtc_state *crtc_state)
12592 {
12593 struct drm_device *dev = crtc->dev;
12594 struct drm_i915_private *dev_priv = to_i915(dev);
12595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12596 struct intel_crtc_state *pipe_config =
12597 to_intel_crtc_state(crtc_state);
12598 struct drm_atomic_state *state = crtc_state->state;
12599 int ret;
12600 bool mode_changed = needs_modeset(crtc_state);
12601
12602 if (mode_changed && !crtc_state->active)
12603 pipe_config->update_wm_post = true;
12604
12605 if (mode_changed && crtc_state->enable &&
12606 dev_priv->display.crtc_compute_clock &&
12607 !WARN_ON(pipe_config->shared_dpll)) {
12608 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12609 pipe_config);
12610 if (ret)
12611 return ret;
12612 }
12613
12614 if (crtc_state->color_mgmt_changed) {
12615 ret = intel_color_check(crtc, crtc_state);
12616 if (ret)
12617 return ret;
12618
12619 /*
12620 * Changing color management on Intel hardware is
12621 * handled as part of planes update.
12622 */
12623 crtc_state->planes_changed = true;
12624 }
12625
12626 ret = 0;
12627 if (dev_priv->display.compute_pipe_wm) {
12628 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12629 if (ret) {
12630 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12631 return ret;
12632 }
12633 }
12634
12635 if (dev_priv->display.compute_intermediate_wm &&
12636 !to_intel_atomic_state(state)->skip_intermediate_wm) {
12637 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12638 return 0;
12639
12640 /*
12641 * Calculate 'intermediate' watermarks that satisfy both the
12642 * old state and the new state. We can program these
12643 * immediately.
12644 */
12645 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12646 intel_crtc,
12647 pipe_config);
12648 if (ret) {
12649 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12650 return ret;
12651 }
12652 } else if (dev_priv->display.compute_intermediate_wm) {
12653 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12654 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12655 }
12656
12657 if (INTEL_INFO(dev)->gen >= 9) {
12658 if (mode_changed)
12659 ret = skl_update_scaler_crtc(pipe_config);
12660
12661 if (!ret)
12662 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12663 pipe_config);
12664 }
12665
12666 return ret;
12667 }
12668
12669 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12670 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12671 .atomic_begin = intel_begin_crtc_commit,
12672 .atomic_flush = intel_finish_crtc_commit,
12673 .atomic_check = intel_crtc_atomic_check,
12674 };
12675
12676 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12677 {
12678 struct intel_connector *connector;
12679
12680 for_each_intel_connector(dev, connector) {
12681 if (connector->base.state->crtc)
12682 drm_connector_unreference(&connector->base);
12683
12684 if (connector->base.encoder) {
12685 connector->base.state->best_encoder =
12686 connector->base.encoder;
12687 connector->base.state->crtc =
12688 connector->base.encoder->crtc;
12689
12690 drm_connector_reference(&connector->base);
12691 } else {
12692 connector->base.state->best_encoder = NULL;
12693 connector->base.state->crtc = NULL;
12694 }
12695 }
12696 }
12697
12698 static void
12699 connected_sink_compute_bpp(struct intel_connector *connector,
12700 struct intel_crtc_state *pipe_config)
12701 {
12702 const struct drm_display_info *info = &connector->base.display_info;
12703 int bpp = pipe_config->pipe_bpp;
12704
12705 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12706 connector->base.base.id,
12707 connector->base.name);
12708
12709 /* Don't use an invalid EDID bpc value */
12710 if (info->bpc != 0 && info->bpc * 3 < bpp) {
12711 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12712 bpp, info->bpc * 3);
12713 pipe_config->pipe_bpp = info->bpc * 3;
12714 }
12715
12716 /* Clamp bpp to 8 on screens without EDID 1.4 */
12717 if (info->bpc == 0 && bpp > 24) {
12718 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12719 bpp);
12720 pipe_config->pipe_bpp = 24;
12721 }
12722 }
12723
12724 static int
12725 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12726 struct intel_crtc_state *pipe_config)
12727 {
12728 struct drm_device *dev = crtc->base.dev;
12729 struct drm_atomic_state *state;
12730 struct drm_connector *connector;
12731 struct drm_connector_state *connector_state;
12732 int bpp, i;
12733
12734 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12735 bpp = 10*3;
12736 else if (INTEL_INFO(dev)->gen >= 5)
12737 bpp = 12*3;
12738 else
12739 bpp = 8*3;
12740
12741
12742 pipe_config->pipe_bpp = bpp;
12743
12744 state = pipe_config->base.state;
12745
12746 /* Clamp display bpp to EDID value */
12747 for_each_connector_in_state(state, connector, connector_state, i) {
12748 if (connector_state->crtc != &crtc->base)
12749 continue;
12750
12751 connected_sink_compute_bpp(to_intel_connector(connector),
12752 pipe_config);
12753 }
12754
12755 return bpp;
12756 }
12757
12758 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12759 {
12760 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12761 "type: 0x%x flags: 0x%x\n",
12762 mode->crtc_clock,
12763 mode->crtc_hdisplay, mode->crtc_hsync_start,
12764 mode->crtc_hsync_end, mode->crtc_htotal,
12765 mode->crtc_vdisplay, mode->crtc_vsync_start,
12766 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12767 }
12768
12769 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12770 struct intel_crtc_state *pipe_config,
12771 const char *context)
12772 {
12773 struct drm_device *dev = crtc->base.dev;
12774 struct drm_plane *plane;
12775 struct intel_plane *intel_plane;
12776 struct intel_plane_state *state;
12777 struct drm_framebuffer *fb;
12778
12779 DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n",
12780 crtc->base.base.id, crtc->base.name,
12781 context, pipe_config, pipe_name(crtc->pipe));
12782
12783 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12784 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12785 pipe_config->pipe_bpp, pipe_config->dither);
12786 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12787 pipe_config->has_pch_encoder,
12788 pipe_config->fdi_lanes,
12789 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12790 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12791 pipe_config->fdi_m_n.tu);
12792 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12793 intel_crtc_has_dp_encoder(pipe_config),
12794 pipe_config->lane_count,
12795 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12796 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12797 pipe_config->dp_m_n.tu);
12798
12799 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12800 intel_crtc_has_dp_encoder(pipe_config),
12801 pipe_config->lane_count,
12802 pipe_config->dp_m2_n2.gmch_m,
12803 pipe_config->dp_m2_n2.gmch_n,
12804 pipe_config->dp_m2_n2.link_m,
12805 pipe_config->dp_m2_n2.link_n,
12806 pipe_config->dp_m2_n2.tu);
12807
12808 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12809 pipe_config->has_audio,
12810 pipe_config->has_infoframe);
12811
12812 DRM_DEBUG_KMS("requested mode:\n");
12813 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12814 DRM_DEBUG_KMS("adjusted mode:\n");
12815 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12816 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12817 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12818 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12819 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12820 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12821 crtc->num_scalers,
12822 pipe_config->scaler_state.scaler_users,
12823 pipe_config->scaler_state.scaler_id);
12824 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12825 pipe_config->gmch_pfit.control,
12826 pipe_config->gmch_pfit.pgm_ratios,
12827 pipe_config->gmch_pfit.lvds_border_bits);
12828 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12829 pipe_config->pch_pfit.pos,
12830 pipe_config->pch_pfit.size,
12831 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12832 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12833 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12834
12835 if (IS_BROXTON(dev)) {
12836 DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12837 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12838 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12839 pipe_config->dpll_hw_state.ebb0,
12840 pipe_config->dpll_hw_state.ebb4,
12841 pipe_config->dpll_hw_state.pll0,
12842 pipe_config->dpll_hw_state.pll1,
12843 pipe_config->dpll_hw_state.pll2,
12844 pipe_config->dpll_hw_state.pll3,
12845 pipe_config->dpll_hw_state.pll6,
12846 pipe_config->dpll_hw_state.pll8,
12847 pipe_config->dpll_hw_state.pll9,
12848 pipe_config->dpll_hw_state.pll10,
12849 pipe_config->dpll_hw_state.pcsdw12);
12850 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12851 DRM_DEBUG_KMS("dpll_hw_state: "
12852 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12853 pipe_config->dpll_hw_state.ctrl1,
12854 pipe_config->dpll_hw_state.cfgcr1,
12855 pipe_config->dpll_hw_state.cfgcr2);
12856 } else if (HAS_DDI(dev)) {
12857 DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12858 pipe_config->dpll_hw_state.wrpll,
12859 pipe_config->dpll_hw_state.spll);
12860 } else {
12861 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12862 "fp0: 0x%x, fp1: 0x%x\n",
12863 pipe_config->dpll_hw_state.dpll,
12864 pipe_config->dpll_hw_state.dpll_md,
12865 pipe_config->dpll_hw_state.fp0,
12866 pipe_config->dpll_hw_state.fp1);
12867 }
12868
12869 DRM_DEBUG_KMS("planes on this crtc\n");
12870 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12871 char *format_name;
12872 intel_plane = to_intel_plane(plane);
12873 if (intel_plane->pipe != crtc->pipe)
12874 continue;
12875
12876 state = to_intel_plane_state(plane->state);
12877 fb = state->base.fb;
12878 if (!fb) {
12879 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12880 plane->base.id, plane->name, state->scaler_id);
12881 continue;
12882 }
12883
12884 format_name = drm_get_format_name(fb->pixel_format);
12885
12886 DRM_DEBUG_KMS("[PLANE:%d:%s] enabled",
12887 plane->base.id, plane->name);
12888 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s",
12889 fb->base.id, fb->width, fb->height, format_name);
12890 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12891 state->scaler_id,
12892 state->base.src.x1 >> 16,
12893 state->base.src.y1 >> 16,
12894 drm_rect_width(&state->base.src) >> 16,
12895 drm_rect_height(&state->base.src) >> 16,
12896 state->base.dst.x1, state->base.dst.y1,
12897 drm_rect_width(&state->base.dst),
12898 drm_rect_height(&state->base.dst));
12899
12900 kfree(format_name);
12901 }
12902 }
12903
12904 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12905 {
12906 struct drm_device *dev = state->dev;
12907 struct drm_connector *connector;
12908 unsigned int used_ports = 0;
12909 unsigned int used_mst_ports = 0;
12910
12911 /*
12912 * Walk the connector list instead of the encoder
12913 * list to detect the problem on ddi platforms
12914 * where there's just one encoder per digital port.
12915 */
12916 drm_for_each_connector(connector, dev) {
12917 struct drm_connector_state *connector_state;
12918 struct intel_encoder *encoder;
12919
12920 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12921 if (!connector_state)
12922 connector_state = connector->state;
12923
12924 if (!connector_state->best_encoder)
12925 continue;
12926
12927 encoder = to_intel_encoder(connector_state->best_encoder);
12928
12929 WARN_ON(!connector_state->crtc);
12930
12931 switch (encoder->type) {
12932 unsigned int port_mask;
12933 case INTEL_OUTPUT_UNKNOWN:
12934 if (WARN_ON(!HAS_DDI(dev)))
12935 break;
12936 case INTEL_OUTPUT_DP:
12937 case INTEL_OUTPUT_HDMI:
12938 case INTEL_OUTPUT_EDP:
12939 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12940
12941 /* the same port mustn't appear more than once */
12942 if (used_ports & port_mask)
12943 return false;
12944
12945 used_ports |= port_mask;
12946 break;
12947 case INTEL_OUTPUT_DP_MST:
12948 used_mst_ports |=
12949 1 << enc_to_mst(&encoder->base)->primary->port;
12950 break;
12951 default:
12952 break;
12953 }
12954 }
12955
12956 /* can't mix MST and SST/HDMI on the same port */
12957 if (used_ports & used_mst_ports)
12958 return false;
12959
12960 return true;
12961 }
12962
12963 static void
12964 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12965 {
12966 struct drm_crtc_state tmp_state;
12967 struct intel_crtc_scaler_state scaler_state;
12968 struct intel_dpll_hw_state dpll_hw_state;
12969 struct intel_shared_dpll *shared_dpll;
12970 bool force_thru;
12971
12972 /* FIXME: before the switch to atomic started, a new pipe_config was
12973 * kzalloc'd. Code that depends on any field being zero should be
12974 * fixed, so that the crtc_state can be safely duplicated. For now,
12975 * only fields that are know to not cause problems are preserved. */
12976
12977 tmp_state = crtc_state->base;
12978 scaler_state = crtc_state->scaler_state;
12979 shared_dpll = crtc_state->shared_dpll;
12980 dpll_hw_state = crtc_state->dpll_hw_state;
12981 force_thru = crtc_state->pch_pfit.force_thru;
12982
12983 memset(crtc_state, 0, sizeof *crtc_state);
12984
12985 crtc_state->base = tmp_state;
12986 crtc_state->scaler_state = scaler_state;
12987 crtc_state->shared_dpll = shared_dpll;
12988 crtc_state->dpll_hw_state = dpll_hw_state;
12989 crtc_state->pch_pfit.force_thru = force_thru;
12990 }
12991
12992 static int
12993 intel_modeset_pipe_config(struct drm_crtc *crtc,
12994 struct intel_crtc_state *pipe_config)
12995 {
12996 struct drm_atomic_state *state = pipe_config->base.state;
12997 struct intel_encoder *encoder;
12998 struct drm_connector *connector;
12999 struct drm_connector_state *connector_state;
13000 int base_bpp, ret = -EINVAL;
13001 int i;
13002 bool retry = true;
13003
13004 clear_intel_crtc_state(pipe_config);
13005
13006 pipe_config->cpu_transcoder =
13007 (enum transcoder) to_intel_crtc(crtc)->pipe;
13008
13009 /*
13010 * Sanitize sync polarity flags based on requested ones. If neither
13011 * positive or negative polarity is requested, treat this as meaning
13012 * negative polarity.
13013 */
13014 if (!(pipe_config->base.adjusted_mode.flags &
13015 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
13016 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
13017
13018 if (!(pipe_config->base.adjusted_mode.flags &
13019 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
13020 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
13021
13022 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
13023 pipe_config);
13024 if (base_bpp < 0)
13025 goto fail;
13026
13027 /*
13028 * Determine the real pipe dimensions. Note that stereo modes can
13029 * increase the actual pipe size due to the frame doubling and
13030 * insertion of additional space for blanks between the frame. This
13031 * is stored in the crtc timings. We use the requested mode to do this
13032 * computation to clearly distinguish it from the adjusted mode, which
13033 * can be changed by the connectors in the below retry loop.
13034 */
13035 drm_crtc_get_hv_timing(&pipe_config->base.mode,
13036 &pipe_config->pipe_src_w,
13037 &pipe_config->pipe_src_h);
13038
13039 for_each_connector_in_state(state, connector, connector_state, i) {
13040 if (connector_state->crtc != crtc)
13041 continue;
13042
13043 encoder = to_intel_encoder(connector_state->best_encoder);
13044
13045 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
13046 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
13047 goto fail;
13048 }
13049
13050 /*
13051 * Determine output_types before calling the .compute_config()
13052 * hooks so that the hooks can use this information safely.
13053 */
13054 pipe_config->output_types |= 1 << encoder->type;
13055 }
13056
13057 encoder_retry:
13058 /* Ensure the port clock defaults are reset when retrying. */
13059 pipe_config->port_clock = 0;
13060 pipe_config->pixel_multiplier = 1;
13061
13062 /* Fill in default crtc timings, allow encoders to overwrite them. */
13063 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
13064 CRTC_STEREO_DOUBLE);
13065
13066 /* Pass our mode to the connectors and the CRTC to give them a chance to
13067 * adjust it according to limitations or connector properties, and also
13068 * a chance to reject the mode entirely.
13069 */
13070 for_each_connector_in_state(state, connector, connector_state, i) {
13071 if (connector_state->crtc != crtc)
13072 continue;
13073
13074 encoder = to_intel_encoder(connector_state->best_encoder);
13075
13076 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
13077 DRM_DEBUG_KMS("Encoder config failure\n");
13078 goto fail;
13079 }
13080 }
13081
13082 /* Set default port clock if not overwritten by the encoder. Needs to be
13083 * done afterwards in case the encoder adjusts the mode. */
13084 if (!pipe_config->port_clock)
13085 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
13086 * pipe_config->pixel_multiplier;
13087
13088 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13089 if (ret < 0) {
13090 DRM_DEBUG_KMS("CRTC fixup failed\n");
13091 goto fail;
13092 }
13093
13094 if (ret == RETRY) {
13095 if (WARN(!retry, "loop in pipe configuration computation\n")) {
13096 ret = -EINVAL;
13097 goto fail;
13098 }
13099
13100 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
13101 retry = false;
13102 goto encoder_retry;
13103 }
13104
13105 /* Dithering seems to not pass-through bits correctly when it should, so
13106 * only enable it on 6bpc panels. */
13107 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
13108 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13109 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13110
13111 fail:
13112 return ret;
13113 }
13114
13115 static void
13116 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
13117 {
13118 struct drm_crtc *crtc;
13119 struct drm_crtc_state *crtc_state;
13120 int i;
13121
13122 /* Double check state. */
13123 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13124 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
13125
13126 /* Update hwmode for vblank functions */
13127 if (crtc->state->active)
13128 crtc->hwmode = crtc->state->adjusted_mode;
13129 else
13130 crtc->hwmode.crtc_clock = 0;
13131
13132 /*
13133 * Update legacy state to satisfy fbc code. This can
13134 * be removed when fbc uses the atomic state.
13135 */
13136 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
13137 struct drm_plane_state *plane_state = crtc->primary->state;
13138
13139 crtc->primary->fb = plane_state->fb;
13140 crtc->x = plane_state->src_x >> 16;
13141 crtc->y = plane_state->src_y >> 16;
13142 }
13143 }
13144 }
13145
13146 static bool intel_fuzzy_clock_check(int clock1, int clock2)
13147 {
13148 int diff;
13149
13150 if (clock1 == clock2)
13151 return true;
13152
13153 if (!clock1 || !clock2)
13154 return false;
13155
13156 diff = abs(clock1 - clock2);
13157
13158 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13159 return true;
13160
13161 return false;
13162 }
13163
13164 static bool
13165 intel_compare_m_n(unsigned int m, unsigned int n,
13166 unsigned int m2, unsigned int n2,
13167 bool exact)
13168 {
13169 if (m == m2 && n == n2)
13170 return true;
13171
13172 if (exact || !m || !n || !m2 || !n2)
13173 return false;
13174
13175 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13176
13177 if (n > n2) {
13178 while (n > n2) {
13179 m2 <<= 1;
13180 n2 <<= 1;
13181 }
13182 } else if (n < n2) {
13183 while (n < n2) {
13184 m <<= 1;
13185 n <<= 1;
13186 }
13187 }
13188
13189 if (n != n2)
13190 return false;
13191
13192 return intel_fuzzy_clock_check(m, m2);
13193 }
13194
13195 static bool
13196 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13197 struct intel_link_m_n *m2_n2,
13198 bool adjust)
13199 {
13200 if (m_n->tu == m2_n2->tu &&
13201 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13202 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
13203 intel_compare_m_n(m_n->link_m, m_n->link_n,
13204 m2_n2->link_m, m2_n2->link_n, !adjust)) {
13205 if (adjust)
13206 *m2_n2 = *m_n;
13207
13208 return true;
13209 }
13210
13211 return false;
13212 }
13213
13214 static bool
13215 intel_pipe_config_compare(struct drm_device *dev,
13216 struct intel_crtc_state *current_config,
13217 struct intel_crtc_state *pipe_config,
13218 bool adjust)
13219 {
13220 bool ret = true;
13221
13222 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
13223 do { \
13224 if (!adjust) \
13225 DRM_ERROR(fmt, ##__VA_ARGS__); \
13226 else \
13227 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
13228 } while (0)
13229
13230 #define PIPE_CONF_CHECK_X(name) \
13231 if (current_config->name != pipe_config->name) { \
13232 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13233 "(expected 0x%08x, found 0x%08x)\n", \
13234 current_config->name, \
13235 pipe_config->name); \
13236 ret = false; \
13237 }
13238
13239 #define PIPE_CONF_CHECK_I(name) \
13240 if (current_config->name != pipe_config->name) { \
13241 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13242 "(expected %i, found %i)\n", \
13243 current_config->name, \
13244 pipe_config->name); \
13245 ret = false; \
13246 }
13247
13248 #define PIPE_CONF_CHECK_P(name) \
13249 if (current_config->name != pipe_config->name) { \
13250 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13251 "(expected %p, found %p)\n", \
13252 current_config->name, \
13253 pipe_config->name); \
13254 ret = false; \
13255 }
13256
13257 #define PIPE_CONF_CHECK_M_N(name) \
13258 if (!intel_compare_link_m_n(&current_config->name, \
13259 &pipe_config->name,\
13260 adjust)) { \
13261 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13262 "(expected tu %i gmch %i/%i link %i/%i, " \
13263 "found tu %i, gmch %i/%i link %i/%i)\n", \
13264 current_config->name.tu, \
13265 current_config->name.gmch_m, \
13266 current_config->name.gmch_n, \
13267 current_config->name.link_m, \
13268 current_config->name.link_n, \
13269 pipe_config->name.tu, \
13270 pipe_config->name.gmch_m, \
13271 pipe_config->name.gmch_n, \
13272 pipe_config->name.link_m, \
13273 pipe_config->name.link_n); \
13274 ret = false; \
13275 }
13276
13277 /* This is required for BDW+ where there is only one set of registers for
13278 * switching between high and low RR.
13279 * This macro can be used whenever a comparison has to be made between one
13280 * hw state and multiple sw state variables.
13281 */
13282 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
13283 if (!intel_compare_link_m_n(&current_config->name, \
13284 &pipe_config->name, adjust) && \
13285 !intel_compare_link_m_n(&current_config->alt_name, \
13286 &pipe_config->name, adjust)) { \
13287 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13288 "(expected tu %i gmch %i/%i link %i/%i, " \
13289 "or tu %i gmch %i/%i link %i/%i, " \
13290 "found tu %i, gmch %i/%i link %i/%i)\n", \
13291 current_config->name.tu, \
13292 current_config->name.gmch_m, \
13293 current_config->name.gmch_n, \
13294 current_config->name.link_m, \
13295 current_config->name.link_n, \
13296 current_config->alt_name.tu, \
13297 current_config->alt_name.gmch_m, \
13298 current_config->alt_name.gmch_n, \
13299 current_config->alt_name.link_m, \
13300 current_config->alt_name.link_n, \
13301 pipe_config->name.tu, \
13302 pipe_config->name.gmch_m, \
13303 pipe_config->name.gmch_n, \
13304 pipe_config->name.link_m, \
13305 pipe_config->name.link_n); \
13306 ret = false; \
13307 }
13308
13309 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
13310 if ((current_config->name ^ pipe_config->name) & (mask)) { \
13311 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
13312 "(expected %i, found %i)\n", \
13313 current_config->name & (mask), \
13314 pipe_config->name & (mask)); \
13315 ret = false; \
13316 }
13317
13318 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
13319 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13320 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13321 "(expected %i, found %i)\n", \
13322 current_config->name, \
13323 pipe_config->name); \
13324 ret = false; \
13325 }
13326
13327 #define PIPE_CONF_QUIRK(quirk) \
13328 ((current_config->quirks | pipe_config->quirks) & (quirk))
13329
13330 PIPE_CONF_CHECK_I(cpu_transcoder);
13331
13332 PIPE_CONF_CHECK_I(has_pch_encoder);
13333 PIPE_CONF_CHECK_I(fdi_lanes);
13334 PIPE_CONF_CHECK_M_N(fdi_m_n);
13335
13336 PIPE_CONF_CHECK_I(lane_count);
13337 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13338
13339 if (INTEL_INFO(dev)->gen < 8) {
13340 PIPE_CONF_CHECK_M_N(dp_m_n);
13341
13342 if (current_config->has_drrs)
13343 PIPE_CONF_CHECK_M_N(dp_m2_n2);
13344 } else
13345 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13346
13347 PIPE_CONF_CHECK_X(output_types);
13348
13349 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
13350 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
13351 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
13352 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
13353 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
13354 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
13355
13356 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
13357 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
13358 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
13359 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
13360 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
13361 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
13362
13363 PIPE_CONF_CHECK_I(pixel_multiplier);
13364 PIPE_CONF_CHECK_I(has_hdmi_sink);
13365 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
13366 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
13367 PIPE_CONF_CHECK_I(limited_color_range);
13368 PIPE_CONF_CHECK_I(has_infoframe);
13369
13370 PIPE_CONF_CHECK_I(has_audio);
13371
13372 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13373 DRM_MODE_FLAG_INTERLACE);
13374
13375 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13376 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13377 DRM_MODE_FLAG_PHSYNC);
13378 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13379 DRM_MODE_FLAG_NHSYNC);
13380 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13381 DRM_MODE_FLAG_PVSYNC);
13382 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13383 DRM_MODE_FLAG_NVSYNC);
13384 }
13385
13386 PIPE_CONF_CHECK_X(gmch_pfit.control);
13387 /* pfit ratios are autocomputed by the hw on gen4+ */
13388 if (INTEL_INFO(dev)->gen < 4)
13389 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13390 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13391
13392 if (!adjust) {
13393 PIPE_CONF_CHECK_I(pipe_src_w);
13394 PIPE_CONF_CHECK_I(pipe_src_h);
13395
13396 PIPE_CONF_CHECK_I(pch_pfit.enabled);
13397 if (current_config->pch_pfit.enabled) {
13398 PIPE_CONF_CHECK_X(pch_pfit.pos);
13399 PIPE_CONF_CHECK_X(pch_pfit.size);
13400 }
13401
13402 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13403 }
13404
13405 /* BDW+ don't expose a synchronous way to read the state */
13406 if (IS_HASWELL(dev))
13407 PIPE_CONF_CHECK_I(ips_enabled);
13408
13409 PIPE_CONF_CHECK_I(double_wide);
13410
13411 PIPE_CONF_CHECK_P(shared_dpll);
13412 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13413 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13414 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13415 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13416 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13417 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13418 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13419 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13420 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13421
13422 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13423 PIPE_CONF_CHECK_X(dsi_pll.div);
13424
13425 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
13426 PIPE_CONF_CHECK_I(pipe_bpp);
13427
13428 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
13429 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13430
13431 #undef PIPE_CONF_CHECK_X
13432 #undef PIPE_CONF_CHECK_I
13433 #undef PIPE_CONF_CHECK_P
13434 #undef PIPE_CONF_CHECK_FLAGS
13435 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13436 #undef PIPE_CONF_QUIRK
13437 #undef INTEL_ERR_OR_DBG_KMS
13438
13439 return ret;
13440 }
13441
13442 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13443 const struct intel_crtc_state *pipe_config)
13444 {
13445 if (pipe_config->has_pch_encoder) {
13446 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13447 &pipe_config->fdi_m_n);
13448 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
13449
13450 /*
13451 * FDI already provided one idea for the dotclock.
13452 * Yell if the encoder disagrees.
13453 */
13454 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13455 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13456 fdi_dotclock, dotclock);
13457 }
13458 }
13459
13460 static void verify_wm_state(struct drm_crtc *crtc,
13461 struct drm_crtc_state *new_state)
13462 {
13463 struct drm_device *dev = crtc->dev;
13464 struct drm_i915_private *dev_priv = to_i915(dev);
13465 struct skl_ddb_allocation hw_ddb, *sw_ddb;
13466 struct skl_ddb_entry *hw_entry, *sw_entry;
13467 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13468 const enum pipe pipe = intel_crtc->pipe;
13469 int plane;
13470
13471 if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
13472 return;
13473
13474 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
13475 sw_ddb = &dev_priv->wm.skl_hw.ddb;
13476
13477 /* planes */
13478 for_each_plane(dev_priv, pipe, plane) {
13479 hw_entry = &hw_ddb.plane[pipe][plane];
13480 sw_entry = &sw_ddb->plane[pipe][plane];
13481
13482 if (skl_ddb_entry_equal(hw_entry, sw_entry))
13483 continue;
13484
13485 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
13486 "(expected (%u,%u), found (%u,%u))\n",
13487 pipe_name(pipe), plane + 1,
13488 sw_entry->start, sw_entry->end,
13489 hw_entry->start, hw_entry->end);
13490 }
13491
13492 /*
13493 * cursor
13494 * If the cursor plane isn't active, we may not have updated it's ddb
13495 * allocation. In that case since the ddb allocation will be updated
13496 * once the plane becomes visible, we can skip this check
13497 */
13498 if (intel_crtc->cursor_addr) {
13499 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
13500 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
13501
13502 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
13503 DRM_ERROR("mismatch in DDB state pipe %c cursor "
13504 "(expected (%u,%u), found (%u,%u))\n",
13505 pipe_name(pipe),
13506 sw_entry->start, sw_entry->end,
13507 hw_entry->start, hw_entry->end);
13508 }
13509 }
13510 }
13511
13512 static void
13513 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
13514 {
13515 struct drm_connector *connector;
13516
13517 drm_for_each_connector(connector, dev) {
13518 struct drm_encoder *encoder = connector->encoder;
13519 struct drm_connector_state *state = connector->state;
13520
13521 if (state->crtc != crtc)
13522 continue;
13523
13524 intel_connector_verify_state(to_intel_connector(connector));
13525
13526 I915_STATE_WARN(state->best_encoder != encoder,
13527 "connector's atomic encoder doesn't match legacy encoder\n");
13528 }
13529 }
13530
13531 static void
13532 verify_encoder_state(struct drm_device *dev)
13533 {
13534 struct intel_encoder *encoder;
13535 struct intel_connector *connector;
13536
13537 for_each_intel_encoder(dev, encoder) {
13538 bool enabled = false;
13539 enum pipe pipe;
13540
13541 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13542 encoder->base.base.id,
13543 encoder->base.name);
13544
13545 for_each_intel_connector(dev, connector) {
13546 if (connector->base.state->best_encoder != &encoder->base)
13547 continue;
13548 enabled = true;
13549
13550 I915_STATE_WARN(connector->base.state->crtc !=
13551 encoder->base.crtc,
13552 "connector's crtc doesn't match encoder crtc\n");
13553 }
13554
13555 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13556 "encoder's enabled state mismatch "
13557 "(expected %i, found %i)\n",
13558 !!encoder->base.crtc, enabled);
13559
13560 if (!encoder->base.crtc) {
13561 bool active;
13562
13563 active = encoder->get_hw_state(encoder, &pipe);
13564 I915_STATE_WARN(active,
13565 "encoder detached but still enabled on pipe %c.\n",
13566 pipe_name(pipe));
13567 }
13568 }
13569 }
13570
13571 static void
13572 verify_crtc_state(struct drm_crtc *crtc,
13573 struct drm_crtc_state *old_crtc_state,
13574 struct drm_crtc_state *new_crtc_state)
13575 {
13576 struct drm_device *dev = crtc->dev;
13577 struct drm_i915_private *dev_priv = to_i915(dev);
13578 struct intel_encoder *encoder;
13579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13580 struct intel_crtc_state *pipe_config, *sw_config;
13581 struct drm_atomic_state *old_state;
13582 bool active;
13583
13584 old_state = old_crtc_state->state;
13585 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
13586 pipe_config = to_intel_crtc_state(old_crtc_state);
13587 memset(pipe_config, 0, sizeof(*pipe_config));
13588 pipe_config->base.crtc = crtc;
13589 pipe_config->base.state = old_state;
13590
13591 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
13592
13593 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
13594
13595 /* hw state is inconsistent with the pipe quirk */
13596 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13597 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13598 active = new_crtc_state->active;
13599
13600 I915_STATE_WARN(new_crtc_state->active != active,
13601 "crtc active state doesn't match with hw state "
13602 "(expected %i, found %i)\n", new_crtc_state->active, active);
13603
13604 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13605 "transitional active state does not match atomic hw state "
13606 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13607
13608 for_each_encoder_on_crtc(dev, crtc, encoder) {
13609 enum pipe pipe;
13610
13611 active = encoder->get_hw_state(encoder, &pipe);
13612 I915_STATE_WARN(active != new_crtc_state->active,
13613 "[ENCODER:%i] active %i with crtc active %i\n",
13614 encoder->base.base.id, active, new_crtc_state->active);
13615
13616 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13617 "Encoder connected to wrong pipe %c\n",
13618 pipe_name(pipe));
13619
13620 if (active) {
13621 pipe_config->output_types |= 1 << encoder->type;
13622 encoder->get_config(encoder, pipe_config);
13623 }
13624 }
13625
13626 if (!new_crtc_state->active)
13627 return;
13628
13629 intel_pipe_config_sanity_check(dev_priv, pipe_config);
13630
13631 sw_config = to_intel_crtc_state(crtc->state);
13632 if (!intel_pipe_config_compare(dev, sw_config,
13633 pipe_config, false)) {
13634 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13635 intel_dump_pipe_config(intel_crtc, pipe_config,
13636 "[hw state]");
13637 intel_dump_pipe_config(intel_crtc, sw_config,
13638 "[sw state]");
13639 }
13640 }
13641
13642 static void
13643 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13644 struct intel_shared_dpll *pll,
13645 struct drm_crtc *crtc,
13646 struct drm_crtc_state *new_state)
13647 {
13648 struct intel_dpll_hw_state dpll_hw_state;
13649 unsigned crtc_mask;
13650 bool active;
13651
13652 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13653
13654 DRM_DEBUG_KMS("%s\n", pll->name);
13655
13656 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13657
13658 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13659 I915_STATE_WARN(!pll->on && pll->active_mask,
13660 "pll in active use but not on in sw tracking\n");
13661 I915_STATE_WARN(pll->on && !pll->active_mask,
13662 "pll is on but not used by any active crtc\n");
13663 I915_STATE_WARN(pll->on != active,
13664 "pll on state mismatch (expected %i, found %i)\n",
13665 pll->on, active);
13666 }
13667
13668 if (!crtc) {
13669 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13670 "more active pll users than references: %x vs %x\n",
13671 pll->active_mask, pll->config.crtc_mask);
13672
13673 return;
13674 }
13675
13676 crtc_mask = 1 << drm_crtc_index(crtc);
13677
13678 if (new_state->active)
13679 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13680 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13681 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13682 else
13683 I915_STATE_WARN(pll->active_mask & crtc_mask,
13684 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13685 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13686
13687 I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13688 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13689 crtc_mask, pll->config.crtc_mask);
13690
13691 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13692 &dpll_hw_state,
13693 sizeof(dpll_hw_state)),
13694 "pll hw state mismatch\n");
13695 }
13696
13697 static void
13698 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13699 struct drm_crtc_state *old_crtc_state,
13700 struct drm_crtc_state *new_crtc_state)
13701 {
13702 struct drm_i915_private *dev_priv = to_i915(dev);
13703 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13704 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13705
13706 if (new_state->shared_dpll)
13707 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13708
13709 if (old_state->shared_dpll &&
13710 old_state->shared_dpll != new_state->shared_dpll) {
13711 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13712 struct intel_shared_dpll *pll = old_state->shared_dpll;
13713
13714 I915_STATE_WARN(pll->active_mask & crtc_mask,
13715 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13716 pipe_name(drm_crtc_index(crtc)));
13717 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13718 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13719 pipe_name(drm_crtc_index(crtc)));
13720 }
13721 }
13722
13723 static void
13724 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13725 struct drm_crtc_state *old_state,
13726 struct drm_crtc_state *new_state)
13727 {
13728 if (!needs_modeset(new_state) &&
13729 !to_intel_crtc_state(new_state)->update_pipe)
13730 return;
13731
13732 verify_wm_state(crtc, new_state);
13733 verify_connector_state(crtc->dev, crtc);
13734 verify_crtc_state(crtc, old_state, new_state);
13735 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13736 }
13737
13738 static void
13739 verify_disabled_dpll_state(struct drm_device *dev)
13740 {
13741 struct drm_i915_private *dev_priv = to_i915(dev);
13742 int i;
13743
13744 for (i = 0; i < dev_priv->num_shared_dpll; i++)
13745 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13746 }
13747
13748 static void
13749 intel_modeset_verify_disabled(struct drm_device *dev)
13750 {
13751 verify_encoder_state(dev);
13752 verify_connector_state(dev, NULL);
13753 verify_disabled_dpll_state(dev);
13754 }
13755
13756 static void update_scanline_offset(struct intel_crtc *crtc)
13757 {
13758 struct drm_device *dev = crtc->base.dev;
13759
13760 /*
13761 * The scanline counter increments at the leading edge of hsync.
13762 *
13763 * On most platforms it starts counting from vtotal-1 on the
13764 * first active line. That means the scanline counter value is
13765 * always one less than what we would expect. Ie. just after
13766 * start of vblank, which also occurs at start of hsync (on the
13767 * last active line), the scanline counter will read vblank_start-1.
13768 *
13769 * On gen2 the scanline counter starts counting from 1 instead
13770 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13771 * to keep the value positive), instead of adding one.
13772 *
13773 * On HSW+ the behaviour of the scanline counter depends on the output
13774 * type. For DP ports it behaves like most other platforms, but on HDMI
13775 * there's an extra 1 line difference. So we need to add two instead of
13776 * one to the value.
13777 */
13778 if (IS_GEN2(dev)) {
13779 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13780 int vtotal;
13781
13782 vtotal = adjusted_mode->crtc_vtotal;
13783 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13784 vtotal /= 2;
13785
13786 crtc->scanline_offset = vtotal - 1;
13787 } else if (HAS_DDI(dev) &&
13788 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
13789 crtc->scanline_offset = 2;
13790 } else
13791 crtc->scanline_offset = 1;
13792 }
13793
13794 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13795 {
13796 struct drm_device *dev = state->dev;
13797 struct drm_i915_private *dev_priv = to_i915(dev);
13798 struct intel_shared_dpll_config *shared_dpll = NULL;
13799 struct drm_crtc *crtc;
13800 struct drm_crtc_state *crtc_state;
13801 int i;
13802
13803 if (!dev_priv->display.crtc_compute_clock)
13804 return;
13805
13806 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13808 struct intel_shared_dpll *old_dpll =
13809 to_intel_crtc_state(crtc->state)->shared_dpll;
13810
13811 if (!needs_modeset(crtc_state))
13812 continue;
13813
13814 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13815
13816 if (!old_dpll)
13817 continue;
13818
13819 if (!shared_dpll)
13820 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13821
13822 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13823 }
13824 }
13825
13826 /*
13827 * This implements the workaround described in the "notes" section of the mode
13828 * set sequence documentation. When going from no pipes or single pipe to
13829 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13830 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13831 */
13832 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13833 {
13834 struct drm_crtc_state *crtc_state;
13835 struct intel_crtc *intel_crtc;
13836 struct drm_crtc *crtc;
13837 struct intel_crtc_state *first_crtc_state = NULL;
13838 struct intel_crtc_state *other_crtc_state = NULL;
13839 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13840 int i;
13841
13842 /* look at all crtc's that are going to be enabled in during modeset */
13843 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13844 intel_crtc = to_intel_crtc(crtc);
13845
13846 if (!crtc_state->active || !needs_modeset(crtc_state))
13847 continue;
13848
13849 if (first_crtc_state) {
13850 other_crtc_state = to_intel_crtc_state(crtc_state);
13851 break;
13852 } else {
13853 first_crtc_state = to_intel_crtc_state(crtc_state);
13854 first_pipe = intel_crtc->pipe;
13855 }
13856 }
13857
13858 /* No workaround needed? */
13859 if (!first_crtc_state)
13860 return 0;
13861
13862 /* w/a possibly needed, check how many crtc's are already enabled. */
13863 for_each_intel_crtc(state->dev, intel_crtc) {
13864 struct intel_crtc_state *pipe_config;
13865
13866 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13867 if (IS_ERR(pipe_config))
13868 return PTR_ERR(pipe_config);
13869
13870 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13871
13872 if (!pipe_config->base.active ||
13873 needs_modeset(&pipe_config->base))
13874 continue;
13875
13876 /* 2 or more enabled crtcs means no need for w/a */
13877 if (enabled_pipe != INVALID_PIPE)
13878 return 0;
13879
13880 enabled_pipe = intel_crtc->pipe;
13881 }
13882
13883 if (enabled_pipe != INVALID_PIPE)
13884 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13885 else if (other_crtc_state)
13886 other_crtc_state->hsw_workaround_pipe = first_pipe;
13887
13888 return 0;
13889 }
13890
13891 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13892 {
13893 struct drm_crtc *crtc;
13894 struct drm_crtc_state *crtc_state;
13895 int ret = 0;
13896
13897 /* add all active pipes to the state */
13898 for_each_crtc(state->dev, crtc) {
13899 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13900 if (IS_ERR(crtc_state))
13901 return PTR_ERR(crtc_state);
13902
13903 if (!crtc_state->active || needs_modeset(crtc_state))
13904 continue;
13905
13906 crtc_state->mode_changed = true;
13907
13908 ret = drm_atomic_add_affected_connectors(state, crtc);
13909 if (ret)
13910 break;
13911
13912 ret = drm_atomic_add_affected_planes(state, crtc);
13913 if (ret)
13914 break;
13915 }
13916
13917 return ret;
13918 }
13919
13920 static int intel_modeset_checks(struct drm_atomic_state *state)
13921 {
13922 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13923 struct drm_i915_private *dev_priv = to_i915(state->dev);
13924 struct drm_crtc *crtc;
13925 struct drm_crtc_state *crtc_state;
13926 int ret = 0, i;
13927
13928 if (!check_digital_port_conflicts(state)) {
13929 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13930 return -EINVAL;
13931 }
13932
13933 intel_state->modeset = true;
13934 intel_state->active_crtcs = dev_priv->active_crtcs;
13935
13936 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13937 if (crtc_state->active)
13938 intel_state->active_crtcs |= 1 << i;
13939 else
13940 intel_state->active_crtcs &= ~(1 << i);
13941
13942 if (crtc_state->active != crtc->state->active)
13943 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13944 }
13945
13946 /*
13947 * See if the config requires any additional preparation, e.g.
13948 * to adjust global state with pipes off. We need to do this
13949 * here so we can get the modeset_pipe updated config for the new
13950 * mode set on this crtc. For other crtcs we need to use the
13951 * adjusted_mode bits in the crtc directly.
13952 */
13953 if (dev_priv->display.modeset_calc_cdclk) {
13954 if (!intel_state->cdclk_pll_vco)
13955 intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
13956 if (!intel_state->cdclk_pll_vco)
13957 intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
13958
13959 ret = dev_priv->display.modeset_calc_cdclk(state);
13960 if (ret < 0)
13961 return ret;
13962
13963 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13964 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
13965 ret = intel_modeset_all_pipes(state);
13966
13967 if (ret < 0)
13968 return ret;
13969
13970 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13971 intel_state->cdclk, intel_state->dev_cdclk);
13972 } else
13973 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13974
13975 intel_modeset_clear_plls(state);
13976
13977 if (IS_HASWELL(dev_priv))
13978 return haswell_mode_set_planes_workaround(state);
13979
13980 return 0;
13981 }
13982
13983 /*
13984 * Handle calculation of various watermark data at the end of the atomic check
13985 * phase. The code here should be run after the per-crtc and per-plane 'check'
13986 * handlers to ensure that all derived state has been updated.
13987 */
13988 static int calc_watermark_data(struct drm_atomic_state *state)
13989 {
13990 struct drm_device *dev = state->dev;
13991 struct drm_i915_private *dev_priv = to_i915(dev);
13992
13993 /* Is there platform-specific watermark information to calculate? */
13994 if (dev_priv->display.compute_global_watermarks)
13995 return dev_priv->display.compute_global_watermarks(state);
13996
13997 return 0;
13998 }
13999
14000 /**
14001 * intel_atomic_check - validate state object
14002 * @dev: drm device
14003 * @state: state to validate
14004 */
14005 static int intel_atomic_check(struct drm_device *dev,
14006 struct drm_atomic_state *state)
14007 {
14008 struct drm_i915_private *dev_priv = to_i915(dev);
14009 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14010 struct drm_crtc *crtc;
14011 struct drm_crtc_state *crtc_state;
14012 int ret, i;
14013 bool any_ms = false;
14014
14015 ret = drm_atomic_helper_check_modeset(dev, state);
14016 if (ret)
14017 return ret;
14018
14019 for_each_crtc_in_state(state, crtc, crtc_state, i) {
14020 struct intel_crtc_state *pipe_config =
14021 to_intel_crtc_state(crtc_state);
14022
14023 /* Catch I915_MODE_FLAG_INHERITED */
14024 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
14025 crtc_state->mode_changed = true;
14026
14027 if (!needs_modeset(crtc_state))
14028 continue;
14029
14030 if (!crtc_state->enable) {
14031 any_ms = true;
14032 continue;
14033 }
14034
14035 /* FIXME: For only active_changed we shouldn't need to do any
14036 * state recomputation at all. */
14037
14038 ret = drm_atomic_add_affected_connectors(state, crtc);
14039 if (ret)
14040 return ret;
14041
14042 ret = intel_modeset_pipe_config(crtc, pipe_config);
14043 if (ret) {
14044 intel_dump_pipe_config(to_intel_crtc(crtc),
14045 pipe_config, "[failed]");
14046 return ret;
14047 }
14048
14049 if (i915.fastboot &&
14050 intel_pipe_config_compare(dev,
14051 to_intel_crtc_state(crtc->state),
14052 pipe_config, true)) {
14053 crtc_state->mode_changed = false;
14054 to_intel_crtc_state(crtc_state)->update_pipe = true;
14055 }
14056
14057 if (needs_modeset(crtc_state))
14058 any_ms = true;
14059
14060 ret = drm_atomic_add_affected_planes(state, crtc);
14061 if (ret)
14062 return ret;
14063
14064 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
14065 needs_modeset(crtc_state) ?
14066 "[modeset]" : "[fastset]");
14067 }
14068
14069 if (any_ms) {
14070 ret = intel_modeset_checks(state);
14071
14072 if (ret)
14073 return ret;
14074 } else
14075 intel_state->cdclk = dev_priv->cdclk_freq;
14076
14077 ret = drm_atomic_helper_check_planes(dev, state);
14078 if (ret)
14079 return ret;
14080
14081 intel_fbc_choose_crtc(dev_priv, state);
14082 return calc_watermark_data(state);
14083 }
14084
14085 static int intel_atomic_prepare_commit(struct drm_device *dev,
14086 struct drm_atomic_state *state,
14087 bool nonblock)
14088 {
14089 struct drm_i915_private *dev_priv = to_i915(dev);
14090 struct drm_plane_state *plane_state;
14091 struct drm_crtc_state *crtc_state;
14092 struct drm_plane *plane;
14093 struct drm_crtc *crtc;
14094 int i, ret;
14095
14096 for_each_crtc_in_state(state, crtc, crtc_state, i) {
14097 if (state->legacy_cursor_update)
14098 continue;
14099
14100 ret = intel_crtc_wait_for_pending_flips(crtc);
14101 if (ret)
14102 return ret;
14103
14104 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
14105 flush_workqueue(dev_priv->wq);
14106 }
14107
14108 ret = mutex_lock_interruptible(&dev->struct_mutex);
14109 if (ret)
14110 return ret;
14111
14112 ret = drm_atomic_helper_prepare_planes(dev, state);
14113 mutex_unlock(&dev->struct_mutex);
14114
14115 if (!ret && !nonblock) {
14116 for_each_plane_in_state(state, plane, plane_state, i) {
14117 struct intel_plane_state *intel_plane_state =
14118 to_intel_plane_state(plane_state);
14119
14120 if (!intel_plane_state->wait_req)
14121 continue;
14122
14123 ret = i915_wait_request(intel_plane_state->wait_req,
14124 I915_WAIT_INTERRUPTIBLE,
14125 NULL, NULL);
14126 if (ret) {
14127 /* Any hang should be swallowed by the wait */
14128 WARN_ON(ret == -EIO);
14129 mutex_lock(&dev->struct_mutex);
14130 drm_atomic_helper_cleanup_planes(dev, state);
14131 mutex_unlock(&dev->struct_mutex);
14132 break;
14133 }
14134 }
14135 }
14136
14137 return ret;
14138 }
14139
14140 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14141 {
14142 struct drm_device *dev = crtc->base.dev;
14143
14144 if (!dev->max_vblank_count)
14145 return drm_accurate_vblank_count(&crtc->base);
14146
14147 return dev->driver->get_vblank_counter(dev, crtc->pipe);
14148 }
14149
14150 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
14151 struct drm_i915_private *dev_priv,
14152 unsigned crtc_mask)
14153 {
14154 unsigned last_vblank_count[I915_MAX_PIPES];
14155 enum pipe pipe;
14156 int ret;
14157
14158 if (!crtc_mask)
14159 return;
14160
14161 for_each_pipe(dev_priv, pipe) {
14162 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
14163
14164 if (!((1 << pipe) & crtc_mask))
14165 continue;
14166
14167 ret = drm_crtc_vblank_get(crtc);
14168 if (WARN_ON(ret != 0)) {
14169 crtc_mask &= ~(1 << pipe);
14170 continue;
14171 }
14172
14173 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
14174 }
14175
14176 for_each_pipe(dev_priv, pipe) {
14177 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
14178 long lret;
14179
14180 if (!((1 << pipe) & crtc_mask))
14181 continue;
14182
14183 lret = wait_event_timeout(dev->vblank[pipe].queue,
14184 last_vblank_count[pipe] !=
14185 drm_crtc_vblank_count(crtc),
14186 msecs_to_jiffies(50));
14187
14188 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
14189
14190 drm_crtc_vblank_put(crtc);
14191 }
14192 }
14193
14194 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
14195 {
14196 /* fb updated, need to unpin old fb */
14197 if (crtc_state->fb_changed)
14198 return true;
14199
14200 /* wm changes, need vblank before final wm's */
14201 if (crtc_state->update_wm_post)
14202 return true;
14203
14204 /*
14205 * cxsr is re-enabled after vblank.
14206 * This is already handled by crtc_state->update_wm_post,
14207 * but added for clarity.
14208 */
14209 if (crtc_state->disable_cxsr)
14210 return true;
14211
14212 return false;
14213 }
14214
14215 static void intel_update_crtc(struct drm_crtc *crtc,
14216 struct drm_atomic_state *state,
14217 struct drm_crtc_state *old_crtc_state,
14218 unsigned int *crtc_vblank_mask)
14219 {
14220 struct drm_device *dev = crtc->dev;
14221 struct drm_i915_private *dev_priv = to_i915(dev);
14222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14223 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state);
14224 bool modeset = needs_modeset(crtc->state);
14225
14226 if (modeset) {
14227 update_scanline_offset(intel_crtc);
14228 dev_priv->display.crtc_enable(pipe_config, state);
14229 } else {
14230 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14231 }
14232
14233 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
14234 intel_fbc_enable(
14235 intel_crtc, pipe_config,
14236 to_intel_plane_state(crtc->primary->state));
14237 }
14238
14239 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
14240
14241 if (needs_vblank_wait(pipe_config))
14242 *crtc_vblank_mask |= drm_crtc_mask(crtc);
14243 }
14244
14245 static void intel_update_crtcs(struct drm_atomic_state *state,
14246 unsigned int *crtc_vblank_mask)
14247 {
14248 struct drm_crtc *crtc;
14249 struct drm_crtc_state *old_crtc_state;
14250 int i;
14251
14252 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14253 if (!crtc->state->active)
14254 continue;
14255
14256 intel_update_crtc(crtc, state, old_crtc_state,
14257 crtc_vblank_mask);
14258 }
14259 }
14260
14261 static void skl_update_crtcs(struct drm_atomic_state *state,
14262 unsigned int *crtc_vblank_mask)
14263 {
14264 struct drm_device *dev = state->dev;
14265 struct drm_i915_private *dev_priv = to_i915(dev);
14266 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14267 struct drm_crtc *crtc;
14268 struct drm_crtc_state *old_crtc_state;
14269 struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
14270 struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
14271 unsigned int updated = 0;
14272 bool progress;
14273 enum pipe pipe;
14274
14275 /*
14276 * Whenever the number of active pipes changes, we need to make sure we
14277 * update the pipes in the right order so that their ddb allocations
14278 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14279 * cause pipe underruns and other bad stuff.
14280 */
14281 do {
14282 int i;
14283 progress = false;
14284
14285 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14286 bool vbl_wait = false;
14287 unsigned int cmask = drm_crtc_mask(crtc);
14288 pipe = to_intel_crtc(crtc)->pipe;
14289
14290 if (updated & cmask || !crtc->state->active)
14291 continue;
14292 if (skl_ddb_allocation_overlaps(state, cur_ddb, new_ddb,
14293 pipe))
14294 continue;
14295
14296 updated |= cmask;
14297
14298 /*
14299 * If this is an already active pipe, it's DDB changed,
14300 * and this isn't the last pipe that needs updating
14301 * then we need to wait for a vblank to pass for the
14302 * new ddb allocation to take effect.
14303 */
14304 if (!skl_ddb_allocation_equals(cur_ddb, new_ddb, pipe) &&
14305 !crtc->state->active_changed &&
14306 intel_state->wm_results.dirty_pipes != updated)
14307 vbl_wait = true;
14308
14309 intel_update_crtc(crtc, state, old_crtc_state,
14310 crtc_vblank_mask);
14311
14312 if (vbl_wait)
14313 intel_wait_for_vblank(dev, pipe);
14314
14315 progress = true;
14316 }
14317 } while (progress);
14318 }
14319
14320 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
14321 {
14322 struct drm_device *dev = state->dev;
14323 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14324 struct drm_i915_private *dev_priv = to_i915(dev);
14325 struct drm_crtc_state *old_crtc_state;
14326 struct drm_crtc *crtc;
14327 struct intel_crtc_state *intel_cstate;
14328 struct drm_plane *plane;
14329 struct drm_plane_state *plane_state;
14330 bool hw_check = intel_state->modeset;
14331 unsigned long put_domains[I915_MAX_PIPES] = {};
14332 unsigned crtc_vblank_mask = 0;
14333 int i, ret;
14334
14335 for_each_plane_in_state(state, plane, plane_state, i) {
14336 struct intel_plane_state *intel_plane_state =
14337 to_intel_plane_state(plane->state);
14338
14339 if (!intel_plane_state->wait_req)
14340 continue;
14341
14342 ret = i915_wait_request(intel_plane_state->wait_req,
14343 0, NULL, NULL);
14344 /* EIO should be eaten, and we can't get interrupted in the
14345 * worker, and blocking commits have waited already. */
14346 WARN_ON(ret);
14347 }
14348
14349 drm_atomic_helper_wait_for_dependencies(state);
14350
14351 if (intel_state->modeset) {
14352 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
14353 sizeof(intel_state->min_pixclk));
14354 dev_priv->active_crtcs = intel_state->active_crtcs;
14355 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
14356
14357 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14358 }
14359
14360 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14361 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14362
14363 if (needs_modeset(crtc->state) ||
14364 to_intel_crtc_state(crtc->state)->update_pipe) {
14365 hw_check = true;
14366
14367 put_domains[to_intel_crtc(crtc)->pipe] =
14368 modeset_get_crtc_power_domains(crtc,
14369 to_intel_crtc_state(crtc->state));
14370 }
14371
14372 if (!needs_modeset(crtc->state))
14373 continue;
14374
14375 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14376
14377 if (old_crtc_state->active) {
14378 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
14379 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
14380 intel_crtc->active = false;
14381 intel_fbc_disable(intel_crtc);
14382 intel_disable_shared_dpll(intel_crtc);
14383
14384 /*
14385 * Underruns don't always raise
14386 * interrupts, so check manually.
14387 */
14388 intel_check_cpu_fifo_underruns(dev_priv);
14389 intel_check_pch_fifo_underruns(dev_priv);
14390
14391 if (!crtc->state->active)
14392 intel_update_watermarks(crtc);
14393 }
14394 }
14395
14396 /* Only after disabling all output pipelines that will be changed can we
14397 * update the the output configuration. */
14398 intel_modeset_update_crtc_state(state);
14399
14400 if (intel_state->modeset) {
14401 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
14402
14403 if (dev_priv->display.modeset_commit_cdclk &&
14404 (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
14405 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
14406 dev_priv->display.modeset_commit_cdclk(state);
14407
14408 /*
14409 * SKL workaround: bspec recommends we disable the SAGV when we
14410 * have more then one pipe enabled
14411 */
14412 if (!intel_can_enable_sagv(state))
14413 intel_disable_sagv(dev_priv);
14414
14415 intel_modeset_verify_disabled(dev);
14416 }
14417
14418 /* Complete the events for pipes that have now been disabled */
14419 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14420 bool modeset = needs_modeset(crtc->state);
14421
14422 /* Complete events for now disable pipes here. */
14423 if (modeset && !crtc->state->active && crtc->state->event) {
14424 spin_lock_irq(&dev->event_lock);
14425 drm_crtc_send_vblank_event(crtc, crtc->state->event);
14426 spin_unlock_irq(&dev->event_lock);
14427
14428 crtc->state->event = NULL;
14429 }
14430 }
14431
14432 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14433 dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
14434
14435 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14436 * already, but still need the state for the delayed optimization. To
14437 * fix this:
14438 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14439 * - schedule that vblank worker _before_ calling hw_done
14440 * - at the start of commit_tail, cancel it _synchrously
14441 * - switch over to the vblank wait helper in the core after that since
14442 * we don't need out special handling any more.
14443 */
14444 if (!state->legacy_cursor_update)
14445 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
14446
14447 /*
14448 * Now that the vblank has passed, we can go ahead and program the
14449 * optimal watermarks on platforms that need two-step watermark
14450 * programming.
14451 *
14452 * TODO: Move this (and other cleanup) to an async worker eventually.
14453 */
14454 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14455 intel_cstate = to_intel_crtc_state(crtc->state);
14456
14457 if (dev_priv->display.optimize_watermarks)
14458 dev_priv->display.optimize_watermarks(intel_cstate);
14459 }
14460
14461 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14462 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
14463
14464 if (put_domains[i])
14465 modeset_put_power_domains(dev_priv, put_domains[i]);
14466
14467 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
14468 }
14469
14470 if (intel_state->modeset && intel_can_enable_sagv(state))
14471 intel_enable_sagv(dev_priv);
14472
14473 drm_atomic_helper_commit_hw_done(state);
14474
14475 if (intel_state->modeset)
14476 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
14477
14478 mutex_lock(&dev->struct_mutex);
14479 drm_atomic_helper_cleanup_planes(dev, state);
14480 mutex_unlock(&dev->struct_mutex);
14481
14482 drm_atomic_helper_commit_cleanup_done(state);
14483
14484 drm_atomic_state_free(state);
14485
14486 /* As one of the primary mmio accessors, KMS has a high likelihood
14487 * of triggering bugs in unclaimed access. After we finish
14488 * modesetting, see if an error has been flagged, and if so
14489 * enable debugging for the next modeset - and hope we catch
14490 * the culprit.
14491 *
14492 * XXX note that we assume display power is on at this point.
14493 * This might hold true now but we need to add pm helper to check
14494 * unclaimed only when the hardware is on, as atomic commits
14495 * can happen also when the device is completely off.
14496 */
14497 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
14498 }
14499
14500 static void intel_atomic_commit_work(struct work_struct *work)
14501 {
14502 struct drm_atomic_state *state = container_of(work,
14503 struct drm_atomic_state,
14504 commit_work);
14505 intel_atomic_commit_tail(state);
14506 }
14507
14508 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
14509 {
14510 struct drm_plane_state *old_plane_state;
14511 struct drm_plane *plane;
14512 int i;
14513
14514 for_each_plane_in_state(state, plane, old_plane_state, i)
14515 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
14516 intel_fb_obj(plane->state->fb),
14517 to_intel_plane(plane)->frontbuffer_bit);
14518 }
14519
14520 /**
14521 * intel_atomic_commit - commit validated state object
14522 * @dev: DRM device
14523 * @state: the top-level driver state object
14524 * @nonblock: nonblocking commit
14525 *
14526 * This function commits a top-level state object that has been validated
14527 * with drm_atomic_helper_check().
14528 *
14529 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
14530 * nonblocking commits are only safe for pure plane updates. Everything else
14531 * should work though.
14532 *
14533 * RETURNS
14534 * Zero for success or -errno.
14535 */
14536 static int intel_atomic_commit(struct drm_device *dev,
14537 struct drm_atomic_state *state,
14538 bool nonblock)
14539 {
14540 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14541 struct drm_i915_private *dev_priv = to_i915(dev);
14542 int ret = 0;
14543
14544 if (intel_state->modeset && nonblock) {
14545 DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n");
14546 return -EINVAL;
14547 }
14548
14549 ret = drm_atomic_helper_setup_commit(state, nonblock);
14550 if (ret)
14551 return ret;
14552
14553 INIT_WORK(&state->commit_work, intel_atomic_commit_work);
14554
14555 ret = intel_atomic_prepare_commit(dev, state, nonblock);
14556 if (ret) {
14557 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14558 return ret;
14559 }
14560
14561 drm_atomic_helper_swap_state(state, true);
14562 dev_priv->wm.distrust_bios_wm = false;
14563 dev_priv->wm.skl_results = intel_state->wm_results;
14564 intel_shared_dpll_commit(state);
14565 intel_atomic_track_fbs(state);
14566
14567 if (nonblock)
14568 queue_work(system_unbound_wq, &state->commit_work);
14569 else
14570 intel_atomic_commit_tail(state);
14571
14572 return 0;
14573 }
14574
14575 void intel_crtc_restore_mode(struct drm_crtc *crtc)
14576 {
14577 struct drm_device *dev = crtc->dev;
14578 struct drm_atomic_state *state;
14579 struct drm_crtc_state *crtc_state;
14580 int ret;
14581
14582 state = drm_atomic_state_alloc(dev);
14583 if (!state) {
14584 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
14585 crtc->base.id, crtc->name);
14586 return;
14587 }
14588
14589 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
14590
14591 retry:
14592 crtc_state = drm_atomic_get_crtc_state(state, crtc);
14593 ret = PTR_ERR_OR_ZERO(crtc_state);
14594 if (!ret) {
14595 if (!crtc_state->active)
14596 goto out;
14597
14598 crtc_state->mode_changed = true;
14599 ret = drm_atomic_commit(state);
14600 }
14601
14602 if (ret == -EDEADLK) {
14603 drm_atomic_state_clear(state);
14604 drm_modeset_backoff(state->acquire_ctx);
14605 goto retry;
14606 }
14607
14608 if (ret)
14609 out:
14610 drm_atomic_state_free(state);
14611 }
14612
14613 /*
14614 * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
14615 * drm_atomic_helper_legacy_gamma_set() directly.
14616 */
14617 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
14618 u16 *red, u16 *green, u16 *blue,
14619 uint32_t size)
14620 {
14621 struct drm_device *dev = crtc->dev;
14622 struct drm_mode_config *config = &dev->mode_config;
14623 struct drm_crtc_state *state;
14624 int ret;
14625
14626 ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
14627 if (ret)
14628 return ret;
14629
14630 /*
14631 * Make sure we update the legacy properties so this works when
14632 * atomic is not enabled.
14633 */
14634
14635 state = crtc->state;
14636
14637 drm_object_property_set_value(&crtc->base,
14638 config->degamma_lut_property,
14639 (state->degamma_lut) ?
14640 state->degamma_lut->base.id : 0);
14641
14642 drm_object_property_set_value(&crtc->base,
14643 config->ctm_property,
14644 (state->ctm) ?
14645 state->ctm->base.id : 0);
14646
14647 drm_object_property_set_value(&crtc->base,
14648 config->gamma_lut_property,
14649 (state->gamma_lut) ?
14650 state->gamma_lut->base.id : 0);
14651
14652 return 0;
14653 }
14654
14655 static const struct drm_crtc_funcs intel_crtc_funcs = {
14656 .gamma_set = intel_atomic_legacy_gamma_set,
14657 .set_config = drm_atomic_helper_set_config,
14658 .set_property = drm_atomic_helper_crtc_set_property,
14659 .destroy = intel_crtc_destroy,
14660 .page_flip = intel_crtc_page_flip,
14661 .atomic_duplicate_state = intel_crtc_duplicate_state,
14662 .atomic_destroy_state = intel_crtc_destroy_state,
14663 };
14664
14665 /**
14666 * intel_prepare_plane_fb - Prepare fb for usage on plane
14667 * @plane: drm plane to prepare for
14668 * @fb: framebuffer to prepare for presentation
14669 *
14670 * Prepares a framebuffer for usage on a display plane. Generally this
14671 * involves pinning the underlying object and updating the frontbuffer tracking
14672 * bits. Some older platforms need special physical address handling for
14673 * cursor planes.
14674 *
14675 * Must be called with struct_mutex held.
14676 *
14677 * Returns 0 on success, negative error code on failure.
14678 */
14679 int
14680 intel_prepare_plane_fb(struct drm_plane *plane,
14681 struct drm_plane_state *new_state)
14682 {
14683 struct drm_device *dev = plane->dev;
14684 struct drm_framebuffer *fb = new_state->fb;
14685 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14686 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
14687 struct reservation_object *resv;
14688 int ret = 0;
14689
14690 if (!obj && !old_obj)
14691 return 0;
14692
14693 if (old_obj) {
14694 struct drm_crtc_state *crtc_state =
14695 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
14696
14697 /* Big Hammer, we also need to ensure that any pending
14698 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14699 * current scanout is retired before unpinning the old
14700 * framebuffer. Note that we rely on userspace rendering
14701 * into the buffer attached to the pipe they are waiting
14702 * on. If not, userspace generates a GPU hang with IPEHR
14703 * point to the MI_WAIT_FOR_EVENT.
14704 *
14705 * This should only fail upon a hung GPU, in which case we
14706 * can safely continue.
14707 */
14708 if (needs_modeset(crtc_state))
14709 ret = i915_gem_object_wait_rendering(old_obj, true);
14710 if (ret) {
14711 /* GPU hangs should have been swallowed by the wait */
14712 WARN_ON(ret == -EIO);
14713 return ret;
14714 }
14715 }
14716
14717 if (!obj)
14718 return 0;
14719
14720 /* For framebuffer backed by dmabuf, wait for fence */
14721 resv = i915_gem_object_get_dmabuf_resv(obj);
14722 if (resv) {
14723 long lret;
14724
14725 lret = reservation_object_wait_timeout_rcu(resv, false, true,
14726 MAX_SCHEDULE_TIMEOUT);
14727 if (lret == -ERESTARTSYS)
14728 return lret;
14729
14730 WARN(lret < 0, "waiting returns %li\n", lret);
14731 }
14732
14733 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14734 INTEL_INFO(dev)->cursor_needs_physical) {
14735 int align = IS_I830(dev) ? 16 * 1024 : 256;
14736 ret = i915_gem_object_attach_phys(obj, align);
14737 if (ret)
14738 DRM_DEBUG_KMS("failed to attach phys object\n");
14739 } else {
14740 struct i915_vma *vma;
14741
14742 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14743 if (IS_ERR(vma))
14744 ret = PTR_ERR(vma);
14745 }
14746
14747 if (ret == 0) {
14748 to_intel_plane_state(new_state)->wait_req =
14749 i915_gem_active_get(&obj->last_write,
14750 &obj->base.dev->struct_mutex);
14751 }
14752
14753 return ret;
14754 }
14755
14756 /**
14757 * intel_cleanup_plane_fb - Cleans up an fb after plane use
14758 * @plane: drm plane to clean up for
14759 * @fb: old framebuffer that was on plane
14760 *
14761 * Cleans up a framebuffer that has just been removed from a plane.
14762 *
14763 * Must be called with struct_mutex held.
14764 */
14765 void
14766 intel_cleanup_plane_fb(struct drm_plane *plane,
14767 struct drm_plane_state *old_state)
14768 {
14769 struct drm_device *dev = plane->dev;
14770 struct intel_plane_state *old_intel_state;
14771 struct intel_plane_state *intel_state = to_intel_plane_state(plane->state);
14772 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14773 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14774
14775 old_intel_state = to_intel_plane_state(old_state);
14776
14777 if (!obj && !old_obj)
14778 return;
14779
14780 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14781 !INTEL_INFO(dev)->cursor_needs_physical))
14782 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14783
14784 i915_gem_request_assign(&intel_state->wait_req, NULL);
14785 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
14786 }
14787
14788 int
14789 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14790 {
14791 int max_scale;
14792 int crtc_clock, cdclk;
14793
14794 if (!intel_crtc || !crtc_state->base.enable)
14795 return DRM_PLANE_HELPER_NO_SCALING;
14796
14797 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14798 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14799
14800 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14801 return DRM_PLANE_HELPER_NO_SCALING;
14802
14803 /*
14804 * skl max scale is lower of:
14805 * close to 3 but not 3, -1 is for that purpose
14806 * or
14807 * cdclk/crtc_clock
14808 */
14809 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14810
14811 return max_scale;
14812 }
14813
14814 static int
14815 intel_check_primary_plane(struct drm_plane *plane,
14816 struct intel_crtc_state *crtc_state,
14817 struct intel_plane_state *state)
14818 {
14819 struct drm_i915_private *dev_priv = to_i915(plane->dev);
14820 struct drm_crtc *crtc = state->base.crtc;
14821 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14822 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14823 bool can_position = false;
14824 int ret;
14825
14826 if (INTEL_GEN(dev_priv) >= 9) {
14827 /* use scaler when colorkey is not required */
14828 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14829 min_scale = 1;
14830 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14831 }
14832 can_position = true;
14833 }
14834
14835 ret = drm_plane_helper_check_state(&state->base,
14836 &state->clip,
14837 min_scale, max_scale,
14838 can_position, true);
14839 if (ret)
14840 return ret;
14841
14842 if (!state->base.fb)
14843 return 0;
14844
14845 if (INTEL_GEN(dev_priv) >= 9) {
14846 ret = skl_check_plane_surface(state);
14847 if (ret)
14848 return ret;
14849 }
14850
14851 return 0;
14852 }
14853
14854 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14855 struct drm_crtc_state *old_crtc_state)
14856 {
14857 struct drm_device *dev = crtc->dev;
14858 struct drm_i915_private *dev_priv = to_i915(dev);
14859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14860 struct intel_crtc_state *old_intel_state =
14861 to_intel_crtc_state(old_crtc_state);
14862 bool modeset = needs_modeset(crtc->state);
14863 enum pipe pipe = intel_crtc->pipe;
14864
14865 /* Perform vblank evasion around commit operation */
14866 intel_pipe_update_start(intel_crtc);
14867
14868 if (modeset)
14869 return;
14870
14871 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14872 intel_color_set_csc(crtc->state);
14873 intel_color_load_luts(crtc->state);
14874 }
14875
14876 if (to_intel_crtc_state(crtc->state)->update_pipe)
14877 intel_update_pipe_config(intel_crtc, old_intel_state);
14878 else if (INTEL_GEN(dev_priv) >= 9) {
14879 skl_detach_scalers(intel_crtc);
14880
14881 I915_WRITE(PIPE_WM_LINETIME(pipe),
14882 dev_priv->wm.skl_hw.wm_linetime[pipe]);
14883 }
14884 }
14885
14886 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14887 struct drm_crtc_state *old_crtc_state)
14888 {
14889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14890
14891 intel_pipe_update_end(intel_crtc, NULL);
14892 }
14893
14894 /**
14895 * intel_plane_destroy - destroy a plane
14896 * @plane: plane to destroy
14897 *
14898 * Common destruction function for all types of planes (primary, cursor,
14899 * sprite).
14900 */
14901 void intel_plane_destroy(struct drm_plane *plane)
14902 {
14903 if (!plane)
14904 return;
14905
14906 drm_plane_cleanup(plane);
14907 kfree(to_intel_plane(plane));
14908 }
14909
14910 const struct drm_plane_funcs intel_plane_funcs = {
14911 .update_plane = drm_atomic_helper_update_plane,
14912 .disable_plane = drm_atomic_helper_disable_plane,
14913 .destroy = intel_plane_destroy,
14914 .set_property = drm_atomic_helper_plane_set_property,
14915 .atomic_get_property = intel_plane_atomic_get_property,
14916 .atomic_set_property = intel_plane_atomic_set_property,
14917 .atomic_duplicate_state = intel_plane_duplicate_state,
14918 .atomic_destroy_state = intel_plane_destroy_state,
14919
14920 };
14921
14922 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14923 int pipe)
14924 {
14925 struct intel_plane *primary = NULL;
14926 struct intel_plane_state *state = NULL;
14927 const uint32_t *intel_primary_formats;
14928 unsigned int num_formats;
14929 int ret;
14930
14931 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14932 if (!primary)
14933 goto fail;
14934
14935 state = intel_create_plane_state(&primary->base);
14936 if (!state)
14937 goto fail;
14938 primary->base.state = &state->base;
14939
14940 primary->can_scale = false;
14941 primary->max_downscale = 1;
14942 if (INTEL_INFO(dev)->gen >= 9) {
14943 primary->can_scale = true;
14944 state->scaler_id = -1;
14945 }
14946 primary->pipe = pipe;
14947 primary->plane = pipe;
14948 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14949 primary->check_plane = intel_check_primary_plane;
14950 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14951 primary->plane = !pipe;
14952
14953 if (INTEL_INFO(dev)->gen >= 9) {
14954 intel_primary_formats = skl_primary_formats;
14955 num_formats = ARRAY_SIZE(skl_primary_formats);
14956
14957 primary->update_plane = skylake_update_primary_plane;
14958 primary->disable_plane = skylake_disable_primary_plane;
14959 } else if (HAS_PCH_SPLIT(dev)) {
14960 intel_primary_formats = i965_primary_formats;
14961 num_formats = ARRAY_SIZE(i965_primary_formats);
14962
14963 primary->update_plane = ironlake_update_primary_plane;
14964 primary->disable_plane = i9xx_disable_primary_plane;
14965 } else if (INTEL_INFO(dev)->gen >= 4) {
14966 intel_primary_formats = i965_primary_formats;
14967 num_formats = ARRAY_SIZE(i965_primary_formats);
14968
14969 primary->update_plane = i9xx_update_primary_plane;
14970 primary->disable_plane = i9xx_disable_primary_plane;
14971 } else {
14972 intel_primary_formats = i8xx_primary_formats;
14973 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14974
14975 primary->update_plane = i9xx_update_primary_plane;
14976 primary->disable_plane = i9xx_disable_primary_plane;
14977 }
14978
14979 if (INTEL_INFO(dev)->gen >= 9)
14980 ret = drm_universal_plane_init(dev, &primary->base, 0,
14981 &intel_plane_funcs,
14982 intel_primary_formats, num_formats,
14983 DRM_PLANE_TYPE_PRIMARY,
14984 "plane 1%c", pipe_name(pipe));
14985 else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
14986 ret = drm_universal_plane_init(dev, &primary->base, 0,
14987 &intel_plane_funcs,
14988 intel_primary_formats, num_formats,
14989 DRM_PLANE_TYPE_PRIMARY,
14990 "primary %c", pipe_name(pipe));
14991 else
14992 ret = drm_universal_plane_init(dev, &primary->base, 0,
14993 &intel_plane_funcs,
14994 intel_primary_formats, num_formats,
14995 DRM_PLANE_TYPE_PRIMARY,
14996 "plane %c", plane_name(primary->plane));
14997 if (ret)
14998 goto fail;
14999
15000 if (INTEL_INFO(dev)->gen >= 4)
15001 intel_create_rotation_property(dev, primary);
15002
15003 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
15004
15005 return &primary->base;
15006
15007 fail:
15008 kfree(state);
15009 kfree(primary);
15010
15011 return NULL;
15012 }
15013
15014 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
15015 {
15016 if (!dev->mode_config.rotation_property) {
15017 unsigned long flags = DRM_ROTATE_0 |
15018 DRM_ROTATE_180;
15019
15020 if (INTEL_INFO(dev)->gen >= 9)
15021 flags |= DRM_ROTATE_90 | DRM_ROTATE_270;
15022
15023 dev->mode_config.rotation_property =
15024 drm_mode_create_rotation_property(dev, flags);
15025 }
15026 if (dev->mode_config.rotation_property)
15027 drm_object_attach_property(&plane->base.base,
15028 dev->mode_config.rotation_property,
15029 plane->base.state->rotation);
15030 }
15031
15032 static int
15033 intel_check_cursor_plane(struct drm_plane *plane,
15034 struct intel_crtc_state *crtc_state,
15035 struct intel_plane_state *state)
15036 {
15037 struct drm_framebuffer *fb = state->base.fb;
15038 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15039 enum pipe pipe = to_intel_plane(plane)->pipe;
15040 unsigned stride;
15041 int ret;
15042
15043 ret = drm_plane_helper_check_state(&state->base,
15044 &state->clip,
15045 DRM_PLANE_HELPER_NO_SCALING,
15046 DRM_PLANE_HELPER_NO_SCALING,
15047 true, true);
15048 if (ret)
15049 return ret;
15050
15051 /* if we want to turn off the cursor ignore width and height */
15052 if (!obj)
15053 return 0;
15054
15055 /* Check for which cursor types we support */
15056 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
15057 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
15058 state->base.crtc_w, state->base.crtc_h);
15059 return -EINVAL;
15060 }
15061
15062 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
15063 if (obj->base.size < stride * state->base.crtc_h) {
15064 DRM_DEBUG_KMS("buffer is too small\n");
15065 return -ENOMEM;
15066 }
15067
15068 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
15069 DRM_DEBUG_KMS("cursor cannot be tiled\n");
15070 return -EINVAL;
15071 }
15072
15073 /*
15074 * There's something wrong with the cursor on CHV pipe C.
15075 * If it straddles the left edge of the screen then
15076 * moving it away from the edge or disabling it often
15077 * results in a pipe underrun, and often that can lead to
15078 * dead pipe (constant underrun reported, and it scans
15079 * out just a solid color). To recover from that, the
15080 * display power well must be turned off and on again.
15081 * Refuse the put the cursor into that compromised position.
15082 */
15083 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
15084 state->base.visible && state->base.crtc_x < 0) {
15085 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
15086 return -EINVAL;
15087 }
15088
15089 return 0;
15090 }
15091
15092 static void
15093 intel_disable_cursor_plane(struct drm_plane *plane,
15094 struct drm_crtc *crtc)
15095 {
15096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15097
15098 intel_crtc->cursor_addr = 0;
15099 intel_crtc_update_cursor(crtc, NULL);
15100 }
15101
15102 static void
15103 intel_update_cursor_plane(struct drm_plane *plane,
15104 const struct intel_crtc_state *crtc_state,
15105 const struct intel_plane_state *state)
15106 {
15107 struct drm_crtc *crtc = crtc_state->base.crtc;
15108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15109 struct drm_device *dev = plane->dev;
15110 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
15111 uint32_t addr;
15112
15113 if (!obj)
15114 addr = 0;
15115 else if (!INTEL_INFO(dev)->cursor_needs_physical)
15116 addr = i915_gem_object_ggtt_offset(obj, NULL);
15117 else
15118 addr = obj->phys_handle->busaddr;
15119
15120 intel_crtc->cursor_addr = addr;
15121 intel_crtc_update_cursor(crtc, state);
15122 }
15123
15124 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
15125 int pipe)
15126 {
15127 struct intel_plane *cursor = NULL;
15128 struct intel_plane_state *state = NULL;
15129 int ret;
15130
15131 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
15132 if (!cursor)
15133 goto fail;
15134
15135 state = intel_create_plane_state(&cursor->base);
15136 if (!state)
15137 goto fail;
15138 cursor->base.state = &state->base;
15139
15140 cursor->can_scale = false;
15141 cursor->max_downscale = 1;
15142 cursor->pipe = pipe;
15143 cursor->plane = pipe;
15144 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
15145 cursor->check_plane = intel_check_cursor_plane;
15146 cursor->update_plane = intel_update_cursor_plane;
15147 cursor->disable_plane = intel_disable_cursor_plane;
15148
15149 ret = drm_universal_plane_init(dev, &cursor->base, 0,
15150 &intel_plane_funcs,
15151 intel_cursor_formats,
15152 ARRAY_SIZE(intel_cursor_formats),
15153 DRM_PLANE_TYPE_CURSOR,
15154 "cursor %c", pipe_name(pipe));
15155 if (ret)
15156 goto fail;
15157
15158 if (INTEL_INFO(dev)->gen >= 4) {
15159 if (!dev->mode_config.rotation_property)
15160 dev->mode_config.rotation_property =
15161 drm_mode_create_rotation_property(dev,
15162 DRM_ROTATE_0 |
15163 DRM_ROTATE_180);
15164 if (dev->mode_config.rotation_property)
15165 drm_object_attach_property(&cursor->base.base,
15166 dev->mode_config.rotation_property,
15167 state->base.rotation);
15168 }
15169
15170 if (INTEL_INFO(dev)->gen >=9)
15171 state->scaler_id = -1;
15172
15173 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
15174
15175 return &cursor->base;
15176
15177 fail:
15178 kfree(state);
15179 kfree(cursor);
15180
15181 return NULL;
15182 }
15183
15184 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
15185 struct intel_crtc_state *crtc_state)
15186 {
15187 int i;
15188 struct intel_scaler *intel_scaler;
15189 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
15190
15191 for (i = 0; i < intel_crtc->num_scalers; i++) {
15192 intel_scaler = &scaler_state->scalers[i];
15193 intel_scaler->in_use = 0;
15194 intel_scaler->mode = PS_SCALER_MODE_DYN;
15195 }
15196
15197 scaler_state->scaler_id = -1;
15198 }
15199
15200 static void intel_crtc_init(struct drm_device *dev, int pipe)
15201 {
15202 struct drm_i915_private *dev_priv = to_i915(dev);
15203 struct intel_crtc *intel_crtc;
15204 struct intel_crtc_state *crtc_state = NULL;
15205 struct drm_plane *primary = NULL;
15206 struct drm_plane *cursor = NULL;
15207 int ret;
15208
15209 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
15210 if (intel_crtc == NULL)
15211 return;
15212
15213 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
15214 if (!crtc_state)
15215 goto fail;
15216 intel_crtc->config = crtc_state;
15217 intel_crtc->base.state = &crtc_state->base;
15218 crtc_state->base.crtc = &intel_crtc->base;
15219
15220 /* initialize shared scalers */
15221 if (INTEL_INFO(dev)->gen >= 9) {
15222 if (pipe == PIPE_C)
15223 intel_crtc->num_scalers = 1;
15224 else
15225 intel_crtc->num_scalers = SKL_NUM_SCALERS;
15226
15227 skl_init_scalers(dev, intel_crtc, crtc_state);
15228 }
15229
15230 primary = intel_primary_plane_create(dev, pipe);
15231 if (!primary)
15232 goto fail;
15233
15234 cursor = intel_cursor_plane_create(dev, pipe);
15235 if (!cursor)
15236 goto fail;
15237
15238 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
15239 cursor, &intel_crtc_funcs,
15240 "pipe %c", pipe_name(pipe));
15241 if (ret)
15242 goto fail;
15243
15244 /*
15245 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
15246 * is hooked to pipe B. Hence we want plane A feeding pipe B.
15247 */
15248 intel_crtc->pipe = pipe;
15249 intel_crtc->plane = pipe;
15250 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
15251 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
15252 intel_crtc->plane = !pipe;
15253 }
15254
15255 intel_crtc->cursor_base = ~0;
15256 intel_crtc->cursor_cntl = ~0;
15257 intel_crtc->cursor_size = ~0;
15258
15259 intel_crtc->wm.cxsr_allowed = true;
15260
15261 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15262 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
15263 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
15264 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
15265
15266 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
15267
15268 intel_color_init(&intel_crtc->base);
15269
15270 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15271 return;
15272
15273 fail:
15274 intel_plane_destroy(primary);
15275 intel_plane_destroy(cursor);
15276 kfree(crtc_state);
15277 kfree(intel_crtc);
15278 }
15279
15280 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
15281 {
15282 struct drm_encoder *encoder = connector->base.encoder;
15283 struct drm_device *dev = connector->base.dev;
15284
15285 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
15286
15287 if (!encoder || WARN_ON(!encoder->crtc))
15288 return INVALID_PIPE;
15289
15290 return to_intel_crtc(encoder->crtc)->pipe;
15291 }
15292
15293 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
15294 struct drm_file *file)
15295 {
15296 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15297 struct drm_crtc *drmmode_crtc;
15298 struct intel_crtc *crtc;
15299
15300 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
15301 if (!drmmode_crtc)
15302 return -ENOENT;
15303
15304 crtc = to_intel_crtc(drmmode_crtc);
15305 pipe_from_crtc_id->pipe = crtc->pipe;
15306
15307 return 0;
15308 }
15309
15310 static int intel_encoder_clones(struct intel_encoder *encoder)
15311 {
15312 struct drm_device *dev = encoder->base.dev;
15313 struct intel_encoder *source_encoder;
15314 int index_mask = 0;
15315 int entry = 0;
15316
15317 for_each_intel_encoder(dev, source_encoder) {
15318 if (encoders_cloneable(encoder, source_encoder))
15319 index_mask |= (1 << entry);
15320
15321 entry++;
15322 }
15323
15324 return index_mask;
15325 }
15326
15327 static bool has_edp_a(struct drm_device *dev)
15328 {
15329 struct drm_i915_private *dev_priv = to_i915(dev);
15330
15331 if (!IS_MOBILE(dev))
15332 return false;
15333
15334 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15335 return false;
15336
15337 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
15338 return false;
15339
15340 return true;
15341 }
15342
15343 static bool intel_crt_present(struct drm_device *dev)
15344 {
15345 struct drm_i915_private *dev_priv = to_i915(dev);
15346
15347 if (INTEL_INFO(dev)->gen >= 9)
15348 return false;
15349
15350 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
15351 return false;
15352
15353 if (IS_CHERRYVIEW(dev))
15354 return false;
15355
15356 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15357 return false;
15358
15359 /* DDI E can't be used if DDI A requires 4 lanes */
15360 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15361 return false;
15362
15363 if (!dev_priv->vbt.int_crt_support)
15364 return false;
15365
15366 return true;
15367 }
15368
15369 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15370 {
15371 int pps_num;
15372 int pps_idx;
15373
15374 if (HAS_DDI(dev_priv))
15375 return;
15376 /*
15377 * This w/a is needed at least on CPT/PPT, but to be sure apply it
15378 * everywhere where registers can be write protected.
15379 */
15380 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15381 pps_num = 2;
15382 else
15383 pps_num = 1;
15384
15385 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
15386 u32 val = I915_READ(PP_CONTROL(pps_idx));
15387
15388 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
15389 I915_WRITE(PP_CONTROL(pps_idx), val);
15390 }
15391 }
15392
15393 static void intel_pps_init(struct drm_i915_private *dev_priv)
15394 {
15395 if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv))
15396 dev_priv->pps_mmio_base = PCH_PPS_BASE;
15397 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15398 dev_priv->pps_mmio_base = VLV_PPS_BASE;
15399 else
15400 dev_priv->pps_mmio_base = PPS_BASE;
15401
15402 intel_pps_unlock_regs_wa(dev_priv);
15403 }
15404
15405 static void intel_setup_outputs(struct drm_device *dev)
15406 {
15407 struct drm_i915_private *dev_priv = to_i915(dev);
15408 struct intel_encoder *encoder;
15409 bool dpd_is_edp = false;
15410
15411 intel_pps_init(dev_priv);
15412
15413 /*
15414 * intel_edp_init_connector() depends on this completing first, to
15415 * prevent the registeration of both eDP and LVDS and the incorrect
15416 * sharing of the PPS.
15417 */
15418 intel_lvds_init(dev);
15419
15420 if (intel_crt_present(dev))
15421 intel_crt_init(dev);
15422
15423 if (IS_BROXTON(dev)) {
15424 /*
15425 * FIXME: Broxton doesn't support port detection via the
15426 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
15427 * detect the ports.
15428 */
15429 intel_ddi_init(dev, PORT_A);
15430 intel_ddi_init(dev, PORT_B);
15431 intel_ddi_init(dev, PORT_C);
15432
15433 intel_dsi_init(dev);
15434 } else if (HAS_DDI(dev)) {
15435 int found;
15436
15437 /*
15438 * Haswell uses DDI functions to detect digital outputs.
15439 * On SKL pre-D0 the strap isn't connected, so we assume
15440 * it's there.
15441 */
15442 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
15443 /* WaIgnoreDDIAStrap: skl */
15444 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
15445 intel_ddi_init(dev, PORT_A);
15446
15447 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
15448 * register */
15449 found = I915_READ(SFUSE_STRAP);
15450
15451 if (found & SFUSE_STRAP_DDIB_DETECTED)
15452 intel_ddi_init(dev, PORT_B);
15453 if (found & SFUSE_STRAP_DDIC_DETECTED)
15454 intel_ddi_init(dev, PORT_C);
15455 if (found & SFUSE_STRAP_DDID_DETECTED)
15456 intel_ddi_init(dev, PORT_D);
15457 /*
15458 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
15459 */
15460 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
15461 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
15462 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
15463 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
15464 intel_ddi_init(dev, PORT_E);
15465
15466 } else if (HAS_PCH_SPLIT(dev)) {
15467 int found;
15468 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
15469
15470 if (has_edp_a(dev))
15471 intel_dp_init(dev, DP_A, PORT_A);
15472
15473 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
15474 /* PCH SDVOB multiplex with HDMIB */
15475 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
15476 if (!found)
15477 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
15478 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
15479 intel_dp_init(dev, PCH_DP_B, PORT_B);
15480 }
15481
15482 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
15483 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
15484
15485 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
15486 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
15487
15488 if (I915_READ(PCH_DP_C) & DP_DETECTED)
15489 intel_dp_init(dev, PCH_DP_C, PORT_C);
15490
15491 if (I915_READ(PCH_DP_D) & DP_DETECTED)
15492 intel_dp_init(dev, PCH_DP_D, PORT_D);
15493 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
15494 bool has_edp, has_port;
15495
15496 /*
15497 * The DP_DETECTED bit is the latched state of the DDC
15498 * SDA pin at boot. However since eDP doesn't require DDC
15499 * (no way to plug in a DP->HDMI dongle) the DDC pins for
15500 * eDP ports may have been muxed to an alternate function.
15501 * Thus we can't rely on the DP_DETECTED bit alone to detect
15502 * eDP ports. Consult the VBT as well as DP_DETECTED to
15503 * detect eDP ports.
15504 *
15505 * Sadly the straps seem to be missing sometimes even for HDMI
15506 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
15507 * and VBT for the presence of the port. Additionally we can't
15508 * trust the port type the VBT declares as we've seen at least
15509 * HDMI ports that the VBT claim are DP or eDP.
15510 */
15511 has_edp = intel_dp_is_edp(dev, PORT_B);
15512 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
15513 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
15514 has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
15515 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
15516 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
15517
15518 has_edp = intel_dp_is_edp(dev, PORT_C);
15519 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
15520 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
15521 has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
15522 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
15523 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
15524
15525 if (IS_CHERRYVIEW(dev)) {
15526 /*
15527 * eDP not supported on port D,
15528 * so no need to worry about it
15529 */
15530 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
15531 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
15532 intel_dp_init(dev, CHV_DP_D, PORT_D);
15533 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
15534 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
15535 }
15536
15537 intel_dsi_init(dev);
15538 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
15539 bool found = false;
15540
15541 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15542 DRM_DEBUG_KMS("probing SDVOB\n");
15543 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
15544 if (!found && IS_G4X(dev)) {
15545 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
15546 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
15547 }
15548
15549 if (!found && IS_G4X(dev))
15550 intel_dp_init(dev, DP_B, PORT_B);
15551 }
15552
15553 /* Before G4X SDVOC doesn't have its own detect register */
15554
15555 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15556 DRM_DEBUG_KMS("probing SDVOC\n");
15557 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
15558 }
15559
15560 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
15561
15562 if (IS_G4X(dev)) {
15563 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
15564 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
15565 }
15566 if (IS_G4X(dev))
15567 intel_dp_init(dev, DP_C, PORT_C);
15568 }
15569
15570 if (IS_G4X(dev) &&
15571 (I915_READ(DP_D) & DP_DETECTED))
15572 intel_dp_init(dev, DP_D, PORT_D);
15573 } else if (IS_GEN2(dev))
15574 intel_dvo_init(dev);
15575
15576 if (SUPPORTS_TV(dev))
15577 intel_tv_init(dev);
15578
15579 intel_psr_init(dev);
15580
15581 for_each_intel_encoder(dev, encoder) {
15582 encoder->base.possible_crtcs = encoder->crtc_mask;
15583 encoder->base.possible_clones =
15584 intel_encoder_clones(encoder);
15585 }
15586
15587 intel_init_pch_refclk(dev);
15588
15589 drm_helper_move_panel_connectors_to_head(dev);
15590 }
15591
15592 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
15593 {
15594 struct drm_device *dev = fb->dev;
15595 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15596
15597 drm_framebuffer_cleanup(fb);
15598 mutex_lock(&dev->struct_mutex);
15599 WARN_ON(!intel_fb->obj->framebuffer_references--);
15600 i915_gem_object_put(intel_fb->obj);
15601 mutex_unlock(&dev->struct_mutex);
15602 kfree(intel_fb);
15603 }
15604
15605 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
15606 struct drm_file *file,
15607 unsigned int *handle)
15608 {
15609 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15610 struct drm_i915_gem_object *obj = intel_fb->obj;
15611
15612 if (obj->userptr.mm) {
15613 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15614 return -EINVAL;
15615 }
15616
15617 return drm_gem_handle_create(file, &obj->base, handle);
15618 }
15619
15620 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
15621 struct drm_file *file,
15622 unsigned flags, unsigned color,
15623 struct drm_clip_rect *clips,
15624 unsigned num_clips)
15625 {
15626 struct drm_device *dev = fb->dev;
15627 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15628 struct drm_i915_gem_object *obj = intel_fb->obj;
15629
15630 mutex_lock(&dev->struct_mutex);
15631 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
15632 mutex_unlock(&dev->struct_mutex);
15633
15634 return 0;
15635 }
15636
15637 static const struct drm_framebuffer_funcs intel_fb_funcs = {
15638 .destroy = intel_user_framebuffer_destroy,
15639 .create_handle = intel_user_framebuffer_create_handle,
15640 .dirty = intel_user_framebuffer_dirty,
15641 };
15642
15643 static
15644 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
15645 uint32_t pixel_format)
15646 {
15647 u32 gen = INTEL_INFO(dev)->gen;
15648
15649 if (gen >= 9) {
15650 int cpp = drm_format_plane_cpp(pixel_format, 0);
15651
15652 /* "The stride in bytes must not exceed the of the size of 8K
15653 * pixels and 32K bytes."
15654 */
15655 return min(8192 * cpp, 32768);
15656 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15657 return 32*1024;
15658 } else if (gen >= 4) {
15659 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15660 return 16*1024;
15661 else
15662 return 32*1024;
15663 } else if (gen >= 3) {
15664 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15665 return 8*1024;
15666 else
15667 return 16*1024;
15668 } else {
15669 /* XXX DSPC is limited to 4k tiled */
15670 return 8*1024;
15671 }
15672 }
15673
15674 static int intel_framebuffer_init(struct drm_device *dev,
15675 struct intel_framebuffer *intel_fb,
15676 struct drm_mode_fb_cmd2 *mode_cmd,
15677 struct drm_i915_gem_object *obj)
15678 {
15679 struct drm_i915_private *dev_priv = to_i915(dev);
15680 unsigned int tiling = i915_gem_object_get_tiling(obj);
15681 int ret;
15682 u32 pitch_limit, stride_alignment;
15683 char *format_name;
15684
15685 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
15686
15687 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
15688 /*
15689 * If there's a fence, enforce that
15690 * the fb modifier and tiling mode match.
15691 */
15692 if (tiling != I915_TILING_NONE &&
15693 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15694 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
15695 return -EINVAL;
15696 }
15697 } else {
15698 if (tiling == I915_TILING_X) {
15699 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15700 } else if (tiling == I915_TILING_Y) {
15701 DRM_DEBUG("No Y tiling for legacy addfb\n");
15702 return -EINVAL;
15703 }
15704 }
15705
15706 /* Passed in modifier sanity checking. */
15707 switch (mode_cmd->modifier[0]) {
15708 case I915_FORMAT_MOD_Y_TILED:
15709 case I915_FORMAT_MOD_Yf_TILED:
15710 if (INTEL_INFO(dev)->gen < 9) {
15711 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15712 mode_cmd->modifier[0]);
15713 return -EINVAL;
15714 }
15715 case DRM_FORMAT_MOD_NONE:
15716 case I915_FORMAT_MOD_X_TILED:
15717 break;
15718 default:
15719 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15720 mode_cmd->modifier[0]);
15721 return -EINVAL;
15722 }
15723
15724 /*
15725 * gen2/3 display engine uses the fence if present,
15726 * so the tiling mode must match the fb modifier exactly.
15727 */
15728 if (INTEL_INFO(dev_priv)->gen < 4 &&
15729 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15730 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
15731 return -EINVAL;
15732 }
15733
15734 stride_alignment = intel_fb_stride_alignment(dev_priv,
15735 mode_cmd->modifier[0],
15736 mode_cmd->pixel_format);
15737 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
15738 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15739 mode_cmd->pitches[0], stride_alignment);
15740 return -EINVAL;
15741 }
15742
15743 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
15744 mode_cmd->pixel_format);
15745 if (mode_cmd->pitches[0] > pitch_limit) {
15746 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15747 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
15748 "tiled" : "linear",
15749 mode_cmd->pitches[0], pitch_limit);
15750 return -EINVAL;
15751 }
15752
15753 /*
15754 * If there's a fence, enforce that
15755 * the fb pitch and fence stride match.
15756 */
15757 if (tiling != I915_TILING_NONE &&
15758 mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) {
15759 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
15760 mode_cmd->pitches[0],
15761 i915_gem_object_get_stride(obj));
15762 return -EINVAL;
15763 }
15764
15765 /* Reject formats not supported by any plane early. */
15766 switch (mode_cmd->pixel_format) {
15767 case DRM_FORMAT_C8:
15768 case DRM_FORMAT_RGB565:
15769 case DRM_FORMAT_XRGB8888:
15770 case DRM_FORMAT_ARGB8888:
15771 break;
15772 case DRM_FORMAT_XRGB1555:
15773 if (INTEL_INFO(dev)->gen > 3) {
15774 format_name = drm_get_format_name(mode_cmd->pixel_format);
15775 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15776 kfree(format_name);
15777 return -EINVAL;
15778 }
15779 break;
15780 case DRM_FORMAT_ABGR8888:
15781 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
15782 INTEL_INFO(dev)->gen < 9) {
15783 format_name = drm_get_format_name(mode_cmd->pixel_format);
15784 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15785 kfree(format_name);
15786 return -EINVAL;
15787 }
15788 break;
15789 case DRM_FORMAT_XBGR8888:
15790 case DRM_FORMAT_XRGB2101010:
15791 case DRM_FORMAT_XBGR2101010:
15792 if (INTEL_INFO(dev)->gen < 4) {
15793 format_name = drm_get_format_name(mode_cmd->pixel_format);
15794 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15795 kfree(format_name);
15796 return -EINVAL;
15797 }
15798 break;
15799 case DRM_FORMAT_ABGR2101010:
15800 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15801 format_name = drm_get_format_name(mode_cmd->pixel_format);
15802 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15803 kfree(format_name);
15804 return -EINVAL;
15805 }
15806 break;
15807 case DRM_FORMAT_YUYV:
15808 case DRM_FORMAT_UYVY:
15809 case DRM_FORMAT_YVYU:
15810 case DRM_FORMAT_VYUY:
15811 if (INTEL_INFO(dev)->gen < 5) {
15812 format_name = drm_get_format_name(mode_cmd->pixel_format);
15813 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15814 kfree(format_name);
15815 return -EINVAL;
15816 }
15817 break;
15818 default:
15819 format_name = drm_get_format_name(mode_cmd->pixel_format);
15820 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15821 kfree(format_name);
15822 return -EINVAL;
15823 }
15824
15825 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15826 if (mode_cmd->offsets[0] != 0)
15827 return -EINVAL;
15828
15829 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15830 intel_fb->obj = obj;
15831
15832 ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
15833 if (ret)
15834 return ret;
15835
15836 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15837 if (ret) {
15838 DRM_ERROR("framebuffer init failed %d\n", ret);
15839 return ret;
15840 }
15841
15842 intel_fb->obj->framebuffer_references++;
15843
15844 return 0;
15845 }
15846
15847 static struct drm_framebuffer *
15848 intel_user_framebuffer_create(struct drm_device *dev,
15849 struct drm_file *filp,
15850 const struct drm_mode_fb_cmd2 *user_mode_cmd)
15851 {
15852 struct drm_framebuffer *fb;
15853 struct drm_i915_gem_object *obj;
15854 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15855
15856 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
15857 if (!obj)
15858 return ERR_PTR(-ENOENT);
15859
15860 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15861 if (IS_ERR(fb))
15862 i915_gem_object_put_unlocked(obj);
15863
15864 return fb;
15865 }
15866
15867 #ifndef CONFIG_DRM_FBDEV_EMULATION
15868 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
15869 {
15870 }
15871 #endif
15872
15873 static const struct drm_mode_config_funcs intel_mode_funcs = {
15874 .fb_create = intel_user_framebuffer_create,
15875 .output_poll_changed = intel_fbdev_output_poll_changed,
15876 .atomic_check = intel_atomic_check,
15877 .atomic_commit = intel_atomic_commit,
15878 .atomic_state_alloc = intel_atomic_state_alloc,
15879 .atomic_state_clear = intel_atomic_state_clear,
15880 };
15881
15882 /**
15883 * intel_init_display_hooks - initialize the display modesetting hooks
15884 * @dev_priv: device private
15885 */
15886 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15887 {
15888 if (INTEL_INFO(dev_priv)->gen >= 9) {
15889 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15890 dev_priv->display.get_initial_plane_config =
15891 skylake_get_initial_plane_config;
15892 dev_priv->display.crtc_compute_clock =
15893 haswell_crtc_compute_clock;
15894 dev_priv->display.crtc_enable = haswell_crtc_enable;
15895 dev_priv->display.crtc_disable = haswell_crtc_disable;
15896 } else if (HAS_DDI(dev_priv)) {
15897 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15898 dev_priv->display.get_initial_plane_config =
15899 ironlake_get_initial_plane_config;
15900 dev_priv->display.crtc_compute_clock =
15901 haswell_crtc_compute_clock;
15902 dev_priv->display.crtc_enable = haswell_crtc_enable;
15903 dev_priv->display.crtc_disable = haswell_crtc_disable;
15904 } else if (HAS_PCH_SPLIT(dev_priv)) {
15905 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15906 dev_priv->display.get_initial_plane_config =
15907 ironlake_get_initial_plane_config;
15908 dev_priv->display.crtc_compute_clock =
15909 ironlake_crtc_compute_clock;
15910 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15911 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15912 } else if (IS_CHERRYVIEW(dev_priv)) {
15913 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15914 dev_priv->display.get_initial_plane_config =
15915 i9xx_get_initial_plane_config;
15916 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15917 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15918 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15919 } else if (IS_VALLEYVIEW(dev_priv)) {
15920 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15921 dev_priv->display.get_initial_plane_config =
15922 i9xx_get_initial_plane_config;
15923 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15924 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15925 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15926 } else if (IS_G4X(dev_priv)) {
15927 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15928 dev_priv->display.get_initial_plane_config =
15929 i9xx_get_initial_plane_config;
15930 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15931 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15932 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15933 } else if (IS_PINEVIEW(dev_priv)) {
15934 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15935 dev_priv->display.get_initial_plane_config =
15936 i9xx_get_initial_plane_config;
15937 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15938 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15939 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15940 } else if (!IS_GEN2(dev_priv)) {
15941 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15942 dev_priv->display.get_initial_plane_config =
15943 i9xx_get_initial_plane_config;
15944 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15945 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15946 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15947 } else {
15948 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15949 dev_priv->display.get_initial_plane_config =
15950 i9xx_get_initial_plane_config;
15951 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15952 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15953 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15954 }
15955
15956 /* Returns the core display clock speed */
15957 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15958 dev_priv->display.get_display_clock_speed =
15959 skylake_get_display_clock_speed;
15960 else if (IS_BROXTON(dev_priv))
15961 dev_priv->display.get_display_clock_speed =
15962 broxton_get_display_clock_speed;
15963 else if (IS_BROADWELL(dev_priv))
15964 dev_priv->display.get_display_clock_speed =
15965 broadwell_get_display_clock_speed;
15966 else if (IS_HASWELL(dev_priv))
15967 dev_priv->display.get_display_clock_speed =
15968 haswell_get_display_clock_speed;
15969 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15970 dev_priv->display.get_display_clock_speed =
15971 valleyview_get_display_clock_speed;
15972 else if (IS_GEN5(dev_priv))
15973 dev_priv->display.get_display_clock_speed =
15974 ilk_get_display_clock_speed;
15975 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
15976 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
15977 dev_priv->display.get_display_clock_speed =
15978 i945_get_display_clock_speed;
15979 else if (IS_GM45(dev_priv))
15980 dev_priv->display.get_display_clock_speed =
15981 gm45_get_display_clock_speed;
15982 else if (IS_CRESTLINE(dev_priv))
15983 dev_priv->display.get_display_clock_speed =
15984 i965gm_get_display_clock_speed;
15985 else if (IS_PINEVIEW(dev_priv))
15986 dev_priv->display.get_display_clock_speed =
15987 pnv_get_display_clock_speed;
15988 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
15989 dev_priv->display.get_display_clock_speed =
15990 g33_get_display_clock_speed;
15991 else if (IS_I915G(dev_priv))
15992 dev_priv->display.get_display_clock_speed =
15993 i915_get_display_clock_speed;
15994 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
15995 dev_priv->display.get_display_clock_speed =
15996 i9xx_misc_get_display_clock_speed;
15997 else if (IS_I915GM(dev_priv))
15998 dev_priv->display.get_display_clock_speed =
15999 i915gm_get_display_clock_speed;
16000 else if (IS_I865G(dev_priv))
16001 dev_priv->display.get_display_clock_speed =
16002 i865_get_display_clock_speed;
16003 else if (IS_I85X(dev_priv))
16004 dev_priv->display.get_display_clock_speed =
16005 i85x_get_display_clock_speed;
16006 else { /* 830 */
16007 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
16008 dev_priv->display.get_display_clock_speed =
16009 i830_get_display_clock_speed;
16010 }
16011
16012 if (IS_GEN5(dev_priv)) {
16013 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
16014 } else if (IS_GEN6(dev_priv)) {
16015 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
16016 } else if (IS_IVYBRIDGE(dev_priv)) {
16017 /* FIXME: detect B0+ stepping and use auto training */
16018 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
16019 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
16020 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
16021 }
16022
16023 if (IS_BROADWELL(dev_priv)) {
16024 dev_priv->display.modeset_commit_cdclk =
16025 broadwell_modeset_commit_cdclk;
16026 dev_priv->display.modeset_calc_cdclk =
16027 broadwell_modeset_calc_cdclk;
16028 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16029 dev_priv->display.modeset_commit_cdclk =
16030 valleyview_modeset_commit_cdclk;
16031 dev_priv->display.modeset_calc_cdclk =
16032 valleyview_modeset_calc_cdclk;
16033 } else if (IS_BROXTON(dev_priv)) {
16034 dev_priv->display.modeset_commit_cdclk =
16035 bxt_modeset_commit_cdclk;
16036 dev_priv->display.modeset_calc_cdclk =
16037 bxt_modeset_calc_cdclk;
16038 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
16039 dev_priv->display.modeset_commit_cdclk =
16040 skl_modeset_commit_cdclk;
16041 dev_priv->display.modeset_calc_cdclk =
16042 skl_modeset_calc_cdclk;
16043 }
16044
16045 if (dev_priv->info.gen >= 9)
16046 dev_priv->display.update_crtcs = skl_update_crtcs;
16047 else
16048 dev_priv->display.update_crtcs = intel_update_crtcs;
16049
16050 switch (INTEL_INFO(dev_priv)->gen) {
16051 case 2:
16052 dev_priv->display.queue_flip = intel_gen2_queue_flip;
16053 break;
16054
16055 case 3:
16056 dev_priv->display.queue_flip = intel_gen3_queue_flip;
16057 break;
16058
16059 case 4:
16060 case 5:
16061 dev_priv->display.queue_flip = intel_gen4_queue_flip;
16062 break;
16063
16064 case 6:
16065 dev_priv->display.queue_flip = intel_gen6_queue_flip;
16066 break;
16067 case 7:
16068 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
16069 dev_priv->display.queue_flip = intel_gen7_queue_flip;
16070 break;
16071 case 9:
16072 /* Drop through - unsupported since execlist only. */
16073 default:
16074 /* Default just returns -ENODEV to indicate unsupported */
16075 dev_priv->display.queue_flip = intel_default_queue_flip;
16076 }
16077 }
16078
16079 /*
16080 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
16081 * resume, or other times. This quirk makes sure that's the case for
16082 * affected systems.
16083 */
16084 static void quirk_pipea_force(struct drm_device *dev)
16085 {
16086 struct drm_i915_private *dev_priv = to_i915(dev);
16087
16088 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
16089 DRM_INFO("applying pipe a force quirk\n");
16090 }
16091
16092 static void quirk_pipeb_force(struct drm_device *dev)
16093 {
16094 struct drm_i915_private *dev_priv = to_i915(dev);
16095
16096 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
16097 DRM_INFO("applying pipe b force quirk\n");
16098 }
16099
16100 /*
16101 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
16102 */
16103 static void quirk_ssc_force_disable(struct drm_device *dev)
16104 {
16105 struct drm_i915_private *dev_priv = to_i915(dev);
16106 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
16107 DRM_INFO("applying lvds SSC disable quirk\n");
16108 }
16109
16110 /*
16111 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
16112 * brightness value
16113 */
16114 static void quirk_invert_brightness(struct drm_device *dev)
16115 {
16116 struct drm_i915_private *dev_priv = to_i915(dev);
16117 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
16118 DRM_INFO("applying inverted panel brightness quirk\n");
16119 }
16120
16121 /* Some VBT's incorrectly indicate no backlight is present */
16122 static void quirk_backlight_present(struct drm_device *dev)
16123 {
16124 struct drm_i915_private *dev_priv = to_i915(dev);
16125 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
16126 DRM_INFO("applying backlight present quirk\n");
16127 }
16128
16129 struct intel_quirk {
16130 int device;
16131 int subsystem_vendor;
16132 int subsystem_device;
16133 void (*hook)(struct drm_device *dev);
16134 };
16135
16136 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
16137 struct intel_dmi_quirk {
16138 void (*hook)(struct drm_device *dev);
16139 const struct dmi_system_id (*dmi_id_list)[];
16140 };
16141
16142 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
16143 {
16144 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
16145 return 1;
16146 }
16147
16148 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
16149 {
16150 .dmi_id_list = &(const struct dmi_system_id[]) {
16151 {
16152 .callback = intel_dmi_reverse_brightness,
16153 .ident = "NCR Corporation",
16154 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
16155 DMI_MATCH(DMI_PRODUCT_NAME, ""),
16156 },
16157 },
16158 { } /* terminating entry */
16159 },
16160 .hook = quirk_invert_brightness,
16161 },
16162 };
16163
16164 static struct intel_quirk intel_quirks[] = {
16165 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
16166 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
16167
16168 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
16169 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
16170
16171 /* 830 needs to leave pipe A & dpll A up */
16172 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
16173
16174 /* 830 needs to leave pipe B & dpll B up */
16175 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
16176
16177 /* Lenovo U160 cannot use SSC on LVDS */
16178 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
16179
16180 /* Sony Vaio Y cannot use SSC on LVDS */
16181 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
16182
16183 /* Acer Aspire 5734Z must invert backlight brightness */
16184 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
16185
16186 /* Acer/eMachines G725 */
16187 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
16188
16189 /* Acer/eMachines e725 */
16190 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
16191
16192 /* Acer/Packard Bell NCL20 */
16193 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
16194
16195 /* Acer Aspire 4736Z */
16196 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
16197
16198 /* Acer Aspire 5336 */
16199 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
16200
16201 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
16202 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
16203
16204 /* Acer C720 Chromebook (Core i3 4005U) */
16205 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
16206
16207 /* Apple Macbook 2,1 (Core 2 T7400) */
16208 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
16209
16210 /* Apple Macbook 4,1 */
16211 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
16212
16213 /* Toshiba CB35 Chromebook (Celeron 2955U) */
16214 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
16215
16216 /* HP Chromebook 14 (Celeron 2955U) */
16217 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
16218
16219 /* Dell Chromebook 11 */
16220 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
16221
16222 /* Dell Chromebook 11 (2015 version) */
16223 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
16224 };
16225
16226 static void intel_init_quirks(struct drm_device *dev)
16227 {
16228 struct pci_dev *d = dev->pdev;
16229 int i;
16230
16231 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
16232 struct intel_quirk *q = &intel_quirks[i];
16233
16234 if (d->device == q->device &&
16235 (d->subsystem_vendor == q->subsystem_vendor ||
16236 q->subsystem_vendor == PCI_ANY_ID) &&
16237 (d->subsystem_device == q->subsystem_device ||
16238 q->subsystem_device == PCI_ANY_ID))
16239 q->hook(dev);
16240 }
16241 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
16242 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
16243 intel_dmi_quirks[i].hook(dev);
16244 }
16245 }
16246
16247 /* Disable the VGA plane that we never use */
16248 static void i915_disable_vga(struct drm_device *dev)
16249 {
16250 struct drm_i915_private *dev_priv = to_i915(dev);
16251 struct pci_dev *pdev = dev_priv->drm.pdev;
16252 u8 sr1;
16253 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
16254
16255 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
16256 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
16257 outb(SR01, VGA_SR_INDEX);
16258 sr1 = inb(VGA_SR_DATA);
16259 outb(sr1 | 1<<5, VGA_SR_DATA);
16260 vga_put(pdev, VGA_RSRC_LEGACY_IO);
16261 udelay(300);
16262
16263 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
16264 POSTING_READ(vga_reg);
16265 }
16266
16267 void intel_modeset_init_hw(struct drm_device *dev)
16268 {
16269 struct drm_i915_private *dev_priv = to_i915(dev);
16270
16271 intel_update_cdclk(dev);
16272
16273 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16274
16275 intel_init_clock_gating(dev);
16276 }
16277
16278 /*
16279 * Calculate what we think the watermarks should be for the state we've read
16280 * out of the hardware and then immediately program those watermarks so that
16281 * we ensure the hardware settings match our internal state.
16282 *
16283 * We can calculate what we think WM's should be by creating a duplicate of the
16284 * current state (which was constructed during hardware readout) and running it
16285 * through the atomic check code to calculate new watermark values in the
16286 * state object.
16287 */
16288 static void sanitize_watermarks(struct drm_device *dev)
16289 {
16290 struct drm_i915_private *dev_priv = to_i915(dev);
16291 struct drm_atomic_state *state;
16292 struct drm_crtc *crtc;
16293 struct drm_crtc_state *cstate;
16294 struct drm_modeset_acquire_ctx ctx;
16295 int ret;
16296 int i;
16297
16298 /* Only supported on platforms that use atomic watermark design */
16299 if (!dev_priv->display.optimize_watermarks)
16300 return;
16301
16302 /*
16303 * We need to hold connection_mutex before calling duplicate_state so
16304 * that the connector loop is protected.
16305 */
16306 drm_modeset_acquire_init(&ctx, 0);
16307 retry:
16308 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16309 if (ret == -EDEADLK) {
16310 drm_modeset_backoff(&ctx);
16311 goto retry;
16312 } else if (WARN_ON(ret)) {
16313 goto fail;
16314 }
16315
16316 state = drm_atomic_helper_duplicate_state(dev, &ctx);
16317 if (WARN_ON(IS_ERR(state)))
16318 goto fail;
16319
16320 /*
16321 * Hardware readout is the only time we don't want to calculate
16322 * intermediate watermarks (since we don't trust the current
16323 * watermarks).
16324 */
16325 to_intel_atomic_state(state)->skip_intermediate_wm = true;
16326
16327 ret = intel_atomic_check(dev, state);
16328 if (ret) {
16329 /*
16330 * If we fail here, it means that the hardware appears to be
16331 * programmed in a way that shouldn't be possible, given our
16332 * understanding of watermark requirements. This might mean a
16333 * mistake in the hardware readout code or a mistake in the
16334 * watermark calculations for a given platform. Raise a WARN
16335 * so that this is noticeable.
16336 *
16337 * If this actually happens, we'll have to just leave the
16338 * BIOS-programmed watermarks untouched and hope for the best.
16339 */
16340 WARN(true, "Could not determine valid watermarks for inherited state\n");
16341 goto fail;
16342 }
16343
16344 /* Write calculated watermark values back */
16345 for_each_crtc_in_state(state, crtc, cstate, i) {
16346 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
16347
16348 cs->wm.need_postvbl_update = true;
16349 dev_priv->display.optimize_watermarks(cs);
16350 }
16351
16352 drm_atomic_state_free(state);
16353 fail:
16354 drm_modeset_drop_locks(&ctx);
16355 drm_modeset_acquire_fini(&ctx);
16356 }
16357
16358 void intel_modeset_init(struct drm_device *dev)
16359 {
16360 struct drm_i915_private *dev_priv = to_i915(dev);
16361 struct i915_ggtt *ggtt = &dev_priv->ggtt;
16362 int sprite, ret;
16363 enum pipe pipe;
16364 struct intel_crtc *crtc;
16365
16366 drm_mode_config_init(dev);
16367
16368 dev->mode_config.min_width = 0;
16369 dev->mode_config.min_height = 0;
16370
16371 dev->mode_config.preferred_depth = 24;
16372 dev->mode_config.prefer_shadow = 1;
16373
16374 dev->mode_config.allow_fb_modifiers = true;
16375
16376 dev->mode_config.funcs = &intel_mode_funcs;
16377
16378 intel_init_quirks(dev);
16379
16380 intel_init_pm(dev);
16381
16382 if (INTEL_INFO(dev)->num_pipes == 0)
16383 return;
16384
16385 /*
16386 * There may be no VBT; and if the BIOS enabled SSC we can
16387 * just keep using it to avoid unnecessary flicker. Whereas if the
16388 * BIOS isn't using it, don't assume it will work even if the VBT
16389 * indicates as much.
16390 */
16391 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
16392 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
16393 DREF_SSC1_ENABLE);
16394
16395 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
16396 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
16397 bios_lvds_use_ssc ? "en" : "dis",
16398 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
16399 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
16400 }
16401 }
16402
16403 if (IS_GEN2(dev)) {
16404 dev->mode_config.max_width = 2048;
16405 dev->mode_config.max_height = 2048;
16406 } else if (IS_GEN3(dev)) {
16407 dev->mode_config.max_width = 4096;
16408 dev->mode_config.max_height = 4096;
16409 } else {
16410 dev->mode_config.max_width = 8192;
16411 dev->mode_config.max_height = 8192;
16412 }
16413
16414 if (IS_845G(dev) || IS_I865G(dev)) {
16415 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
16416 dev->mode_config.cursor_height = 1023;
16417 } else if (IS_GEN2(dev)) {
16418 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
16419 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
16420 } else {
16421 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
16422 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
16423 }
16424
16425 dev->mode_config.fb_base = ggtt->mappable_base;
16426
16427 DRM_DEBUG_KMS("%d display pipe%s available.\n",
16428 INTEL_INFO(dev)->num_pipes,
16429 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
16430
16431 for_each_pipe(dev_priv, pipe) {
16432 intel_crtc_init(dev, pipe);
16433 for_each_sprite(dev_priv, pipe, sprite) {
16434 ret = intel_plane_init(dev, pipe, sprite);
16435 if (ret)
16436 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
16437 pipe_name(pipe), sprite_name(pipe, sprite), ret);
16438 }
16439 }
16440
16441 intel_update_czclk(dev_priv);
16442 intel_update_cdclk(dev);
16443
16444 intel_shared_dpll_init(dev);
16445
16446 if (dev_priv->max_cdclk_freq == 0)
16447 intel_update_max_cdclk(dev);
16448
16449 /* Just disable it once at startup */
16450 i915_disable_vga(dev);
16451 intel_setup_outputs(dev);
16452
16453 drm_modeset_lock_all(dev);
16454 intel_modeset_setup_hw_state(dev);
16455 drm_modeset_unlock_all(dev);
16456
16457 for_each_intel_crtc(dev, crtc) {
16458 struct intel_initial_plane_config plane_config = {};
16459
16460 if (!crtc->active)
16461 continue;
16462
16463 /*
16464 * Note that reserving the BIOS fb up front prevents us
16465 * from stuffing other stolen allocations like the ring
16466 * on top. This prevents some ugliness at boot time, and
16467 * can even allow for smooth boot transitions if the BIOS
16468 * fb is large enough for the active pipe configuration.
16469 */
16470 dev_priv->display.get_initial_plane_config(crtc,
16471 &plane_config);
16472
16473 /*
16474 * If the fb is shared between multiple heads, we'll
16475 * just get the first one.
16476 */
16477 intel_find_initial_plane_obj(crtc, &plane_config);
16478 }
16479
16480 /*
16481 * Make sure hardware watermarks really match the state we read out.
16482 * Note that we need to do this after reconstructing the BIOS fb's
16483 * since the watermark calculation done here will use pstate->fb.
16484 */
16485 sanitize_watermarks(dev);
16486 }
16487
16488 static void intel_enable_pipe_a(struct drm_device *dev)
16489 {
16490 struct intel_connector *connector;
16491 struct drm_connector *crt = NULL;
16492 struct intel_load_detect_pipe load_detect_temp;
16493 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
16494
16495 /* We can't just switch on the pipe A, we need to set things up with a
16496 * proper mode and output configuration. As a gross hack, enable pipe A
16497 * by enabling the load detect pipe once. */
16498 for_each_intel_connector(dev, connector) {
16499 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
16500 crt = &connector->base;
16501 break;
16502 }
16503 }
16504
16505 if (!crt)
16506 return;
16507
16508 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
16509 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
16510 }
16511
16512 static bool
16513 intel_check_plane_mapping(struct intel_crtc *crtc)
16514 {
16515 struct drm_device *dev = crtc->base.dev;
16516 struct drm_i915_private *dev_priv = to_i915(dev);
16517 u32 val;
16518
16519 if (INTEL_INFO(dev)->num_pipes == 1)
16520 return true;
16521
16522 val = I915_READ(DSPCNTR(!crtc->plane));
16523
16524 if ((val & DISPLAY_PLANE_ENABLE) &&
16525 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
16526 return false;
16527
16528 return true;
16529 }
16530
16531 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
16532 {
16533 struct drm_device *dev = crtc->base.dev;
16534 struct intel_encoder *encoder;
16535
16536 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
16537 return true;
16538
16539 return false;
16540 }
16541
16542 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
16543 {
16544 struct drm_device *dev = encoder->base.dev;
16545 struct intel_connector *connector;
16546
16547 for_each_connector_on_encoder(dev, &encoder->base, connector)
16548 return connector;
16549
16550 return NULL;
16551 }
16552
16553 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
16554 enum transcoder pch_transcoder)
16555 {
16556 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
16557 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
16558 }
16559
16560 static void intel_sanitize_crtc(struct intel_crtc *crtc)
16561 {
16562 struct drm_device *dev = crtc->base.dev;
16563 struct drm_i915_private *dev_priv = to_i915(dev);
16564 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
16565
16566 /* Clear any frame start delays used for debugging left by the BIOS */
16567 if (!transcoder_is_dsi(cpu_transcoder)) {
16568 i915_reg_t reg = PIPECONF(cpu_transcoder);
16569
16570 I915_WRITE(reg,
16571 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
16572 }
16573
16574 /* restore vblank interrupts to correct state */
16575 drm_crtc_vblank_reset(&crtc->base);
16576 if (crtc->active) {
16577 struct intel_plane *plane;
16578
16579 drm_crtc_vblank_on(&crtc->base);
16580
16581 /* Disable everything but the primary plane */
16582 for_each_intel_plane_on_crtc(dev, crtc, plane) {
16583 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
16584 continue;
16585
16586 plane->disable_plane(&plane->base, &crtc->base);
16587 }
16588 }
16589
16590 /* We need to sanitize the plane -> pipe mapping first because this will
16591 * disable the crtc (and hence change the state) if it is wrong. Note
16592 * that gen4+ has a fixed plane -> pipe mapping. */
16593 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
16594 bool plane;
16595
16596 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
16597 crtc->base.base.id, crtc->base.name);
16598
16599 /* Pipe has the wrong plane attached and the plane is active.
16600 * Temporarily change the plane mapping and disable everything
16601 * ... */
16602 plane = crtc->plane;
16603 to_intel_plane_state(crtc->base.primary->state)->base.visible = true;
16604 crtc->plane = !plane;
16605 intel_crtc_disable_noatomic(&crtc->base);
16606 crtc->plane = plane;
16607 }
16608
16609 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
16610 crtc->pipe == PIPE_A && !crtc->active) {
16611 /* BIOS forgot to enable pipe A, this mostly happens after
16612 * resume. Force-enable the pipe to fix this, the update_dpms
16613 * call below we restore the pipe to the right state, but leave
16614 * the required bits on. */
16615 intel_enable_pipe_a(dev);
16616 }
16617
16618 /* Adjust the state of the output pipe according to whether we
16619 * have active connectors/encoders. */
16620 if (crtc->active && !intel_crtc_has_encoders(crtc))
16621 intel_crtc_disable_noatomic(&crtc->base);
16622
16623 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
16624 /*
16625 * We start out with underrun reporting disabled to avoid races.
16626 * For correct bookkeeping mark this on active crtcs.
16627 *
16628 * Also on gmch platforms we dont have any hardware bits to
16629 * disable the underrun reporting. Which means we need to start
16630 * out with underrun reporting disabled also on inactive pipes,
16631 * since otherwise we'll complain about the garbage we read when
16632 * e.g. coming up after runtime pm.
16633 *
16634 * No protection against concurrent access is required - at
16635 * worst a fifo underrun happens which also sets this to false.
16636 */
16637 crtc->cpu_fifo_underrun_disabled = true;
16638 /*
16639 * We track the PCH trancoder underrun reporting state
16640 * within the crtc. With crtc for pipe A housing the underrun
16641 * reporting state for PCH transcoder A, crtc for pipe B housing
16642 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16643 * and marking underrun reporting as disabled for the non-existing
16644 * PCH transcoders B and C would prevent enabling the south
16645 * error interrupt (see cpt_can_enable_serr_int()).
16646 */
16647 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
16648 crtc->pch_fifo_underrun_disabled = true;
16649 }
16650 }
16651
16652 static void intel_sanitize_encoder(struct intel_encoder *encoder)
16653 {
16654 struct intel_connector *connector;
16655
16656 /* We need to check both for a crtc link (meaning that the
16657 * encoder is active and trying to read from a pipe) and the
16658 * pipe itself being active. */
16659 bool has_active_crtc = encoder->base.crtc &&
16660 to_intel_crtc(encoder->base.crtc)->active;
16661
16662 connector = intel_encoder_find_connector(encoder);
16663 if (connector && !has_active_crtc) {
16664 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16665 encoder->base.base.id,
16666 encoder->base.name);
16667
16668 /* Connector is active, but has no active pipe. This is
16669 * fallout from our resume register restoring. Disable
16670 * the encoder manually again. */
16671 if (encoder->base.crtc) {
16672 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
16673
16674 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16675 encoder->base.base.id,
16676 encoder->base.name);
16677 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16678 if (encoder->post_disable)
16679 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16680 }
16681 encoder->base.crtc = NULL;
16682
16683 /* Inconsistent output/port/pipe state happens presumably due to
16684 * a bug in one of the get_hw_state functions. Or someplace else
16685 * in our code, like the register restore mess on resume. Clamp
16686 * things to off as a safer default. */
16687
16688 connector->base.dpms = DRM_MODE_DPMS_OFF;
16689 connector->base.encoder = NULL;
16690 }
16691 /* Enabled encoders without active connectors will be fixed in
16692 * the crtc fixup. */
16693 }
16694
16695 void i915_redisable_vga_power_on(struct drm_device *dev)
16696 {
16697 struct drm_i915_private *dev_priv = to_i915(dev);
16698 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
16699
16700 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
16701 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16702 i915_disable_vga(dev);
16703 }
16704 }
16705
16706 void i915_redisable_vga(struct drm_device *dev)
16707 {
16708 struct drm_i915_private *dev_priv = to_i915(dev);
16709
16710 /* This function can be called both from intel_modeset_setup_hw_state or
16711 * at a very early point in our resume sequence, where the power well
16712 * structures are not yet restored. Since this function is at a very
16713 * paranoid "someone might have enabled VGA while we were not looking"
16714 * level, just check if the power well is enabled instead of trying to
16715 * follow the "don't touch the power well if we don't need it" policy
16716 * the rest of the driver uses. */
16717 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
16718 return;
16719
16720 i915_redisable_vga_power_on(dev);
16721
16722 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
16723 }
16724
16725 static bool primary_get_hw_state(struct intel_plane *plane)
16726 {
16727 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16728
16729 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
16730 }
16731
16732 /* FIXME read out full plane state for all planes */
16733 static void readout_plane_state(struct intel_crtc *crtc)
16734 {
16735 struct drm_plane *primary = crtc->base.primary;
16736 struct intel_plane_state *plane_state =
16737 to_intel_plane_state(primary->state);
16738
16739 plane_state->base.visible = crtc->active &&
16740 primary_get_hw_state(to_intel_plane(primary));
16741
16742 if (plane_state->base.visible)
16743 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
16744 }
16745
16746 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16747 {
16748 struct drm_i915_private *dev_priv = to_i915(dev);
16749 enum pipe pipe;
16750 struct intel_crtc *crtc;
16751 struct intel_encoder *encoder;
16752 struct intel_connector *connector;
16753 int i;
16754
16755 dev_priv->active_crtcs = 0;
16756
16757 for_each_intel_crtc(dev, crtc) {
16758 struct intel_crtc_state *crtc_state = crtc->config;
16759 int pixclk = 0;
16760
16761 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16762 memset(crtc_state, 0, sizeof(*crtc_state));
16763 crtc_state->base.crtc = &crtc->base;
16764
16765 crtc_state->base.active = crtc_state->base.enable =
16766 dev_priv->display.get_pipe_config(crtc, crtc_state);
16767
16768 crtc->base.enabled = crtc_state->base.enable;
16769 crtc->active = crtc_state->base.active;
16770
16771 if (crtc_state->base.active) {
16772 dev_priv->active_crtcs |= 1 << crtc->pipe;
16773
16774 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
16775 pixclk = ilk_pipe_pixel_rate(crtc_state);
16776 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16777 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
16778 else
16779 WARN_ON(dev_priv->display.modeset_calc_cdclk);
16780
16781 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
16782 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
16783 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
16784 }
16785
16786 dev_priv->min_pixclk[crtc->pipe] = pixclk;
16787
16788 readout_plane_state(crtc);
16789
16790 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16791 crtc->base.base.id, crtc->base.name,
16792 crtc->active ? "enabled" : "disabled");
16793 }
16794
16795 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16796 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16797
16798 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16799 &pll->config.hw_state);
16800 pll->config.crtc_mask = 0;
16801 for_each_intel_crtc(dev, crtc) {
16802 if (crtc->active && crtc->config->shared_dpll == pll)
16803 pll->config.crtc_mask |= 1 << crtc->pipe;
16804 }
16805 pll->active_mask = pll->config.crtc_mask;
16806
16807 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16808 pll->name, pll->config.crtc_mask, pll->on);
16809 }
16810
16811 for_each_intel_encoder(dev, encoder) {
16812 pipe = 0;
16813
16814 if (encoder->get_hw_state(encoder, &pipe)) {
16815 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16816 encoder->base.crtc = &crtc->base;
16817 crtc->config->output_types |= 1 << encoder->type;
16818 encoder->get_config(encoder, crtc->config);
16819 } else {
16820 encoder->base.crtc = NULL;
16821 }
16822
16823 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16824 encoder->base.base.id,
16825 encoder->base.name,
16826 encoder->base.crtc ? "enabled" : "disabled",
16827 pipe_name(pipe));
16828 }
16829
16830 for_each_intel_connector(dev, connector) {
16831 if (connector->get_hw_state(connector)) {
16832 connector->base.dpms = DRM_MODE_DPMS_ON;
16833
16834 encoder = connector->encoder;
16835 connector->base.encoder = &encoder->base;
16836
16837 if (encoder->base.crtc &&
16838 encoder->base.crtc->state->active) {
16839 /*
16840 * This has to be done during hardware readout
16841 * because anything calling .crtc_disable may
16842 * rely on the connector_mask being accurate.
16843 */
16844 encoder->base.crtc->state->connector_mask |=
16845 1 << drm_connector_index(&connector->base);
16846 encoder->base.crtc->state->encoder_mask |=
16847 1 << drm_encoder_index(&encoder->base);
16848 }
16849
16850 } else {
16851 connector->base.dpms = DRM_MODE_DPMS_OFF;
16852 connector->base.encoder = NULL;
16853 }
16854 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16855 connector->base.base.id,
16856 connector->base.name,
16857 connector->base.encoder ? "enabled" : "disabled");
16858 }
16859
16860 for_each_intel_crtc(dev, crtc) {
16861 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16862
16863 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16864 if (crtc->base.state->active) {
16865 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16866 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16867 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16868
16869 /*
16870 * The initial mode needs to be set in order to keep
16871 * the atomic core happy. It wants a valid mode if the
16872 * crtc's enabled, so we do the above call.
16873 *
16874 * At this point some state updated by the connectors
16875 * in their ->detect() callback has not run yet, so
16876 * no recalculation can be done yet.
16877 *
16878 * Even if we could do a recalculation and modeset
16879 * right now it would cause a double modeset if
16880 * fbdev or userspace chooses a different initial mode.
16881 *
16882 * If that happens, someone indicated they wanted a
16883 * mode change, which means it's safe to do a full
16884 * recalculation.
16885 */
16886 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16887
16888 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16889 update_scanline_offset(crtc);
16890 }
16891
16892 intel_pipe_config_sanity_check(dev_priv, crtc->config);
16893 }
16894 }
16895
16896 /* Scan out the current hw modeset state,
16897 * and sanitizes it to the current state
16898 */
16899 static void
16900 intel_modeset_setup_hw_state(struct drm_device *dev)
16901 {
16902 struct drm_i915_private *dev_priv = to_i915(dev);
16903 enum pipe pipe;
16904 struct intel_crtc *crtc;
16905 struct intel_encoder *encoder;
16906 int i;
16907
16908 intel_modeset_readout_hw_state(dev);
16909
16910 /* HW state is read out, now we need to sanitize this mess. */
16911 for_each_intel_encoder(dev, encoder) {
16912 intel_sanitize_encoder(encoder);
16913 }
16914
16915 for_each_pipe(dev_priv, pipe) {
16916 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16917 intel_sanitize_crtc(crtc);
16918 intel_dump_pipe_config(crtc, crtc->config,
16919 "[setup_hw_state]");
16920 }
16921
16922 intel_modeset_update_connector_atomic_state(dev);
16923
16924 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16925 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16926
16927 if (!pll->on || pll->active_mask)
16928 continue;
16929
16930 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16931
16932 pll->funcs.disable(dev_priv, pll);
16933 pll->on = false;
16934 }
16935
16936 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
16937 vlv_wm_get_hw_state(dev);
16938 else if (IS_GEN9(dev))
16939 skl_wm_get_hw_state(dev);
16940 else if (HAS_PCH_SPLIT(dev))
16941 ilk_wm_get_hw_state(dev);
16942
16943 for_each_intel_crtc(dev, crtc) {
16944 unsigned long put_domains;
16945
16946 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
16947 if (WARN_ON(put_domains))
16948 modeset_put_power_domains(dev_priv, put_domains);
16949 }
16950 intel_display_set_init_power(dev_priv, false);
16951
16952 intel_fbc_init_pipe_state(dev_priv);
16953 }
16954
16955 void intel_display_resume(struct drm_device *dev)
16956 {
16957 struct drm_i915_private *dev_priv = to_i915(dev);
16958 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16959 struct drm_modeset_acquire_ctx ctx;
16960 int ret;
16961
16962 dev_priv->modeset_restore_state = NULL;
16963 if (state)
16964 state->acquire_ctx = &ctx;
16965
16966 /*
16967 * This is a cludge because with real atomic modeset mode_config.mutex
16968 * won't be taken. Unfortunately some probed state like
16969 * audio_codec_enable is still protected by mode_config.mutex, so lock
16970 * it here for now.
16971 */
16972 mutex_lock(&dev->mode_config.mutex);
16973 drm_modeset_acquire_init(&ctx, 0);
16974
16975 while (1) {
16976 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16977 if (ret != -EDEADLK)
16978 break;
16979
16980 drm_modeset_backoff(&ctx);
16981 }
16982
16983 if (!ret)
16984 ret = __intel_display_resume(dev, state);
16985
16986 drm_modeset_drop_locks(&ctx);
16987 drm_modeset_acquire_fini(&ctx);
16988 mutex_unlock(&dev->mode_config.mutex);
16989
16990 if (ret) {
16991 DRM_ERROR("Restoring old state failed with %i\n", ret);
16992 drm_atomic_state_free(state);
16993 }
16994 }
16995
16996 void intel_modeset_gem_init(struct drm_device *dev)
16997 {
16998 struct drm_i915_private *dev_priv = to_i915(dev);
16999 struct drm_crtc *c;
17000 struct drm_i915_gem_object *obj;
17001
17002 intel_init_gt_powersave(dev_priv);
17003
17004 intel_modeset_init_hw(dev);
17005
17006 intel_setup_overlay(dev_priv);
17007
17008 /*
17009 * Make sure any fbs we allocated at startup are properly
17010 * pinned & fenced. When we do the allocation it's too early
17011 * for this.
17012 */
17013 for_each_crtc(dev, c) {
17014 struct i915_vma *vma;
17015
17016 obj = intel_fb_obj(c->primary->fb);
17017 if (obj == NULL)
17018 continue;
17019
17020 mutex_lock(&dev->struct_mutex);
17021 vma = intel_pin_and_fence_fb_obj(c->primary->fb,
17022 c->primary->state->rotation);
17023 mutex_unlock(&dev->struct_mutex);
17024 if (IS_ERR(vma)) {
17025 DRM_ERROR("failed to pin boot fb on pipe %d\n",
17026 to_intel_crtc(c)->pipe);
17027 drm_framebuffer_unreference(c->primary->fb);
17028 c->primary->fb = NULL;
17029 c->primary->crtc = c->primary->state->crtc = NULL;
17030 update_state_fb(c->primary);
17031 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
17032 }
17033 }
17034 }
17035
17036 int intel_connector_register(struct drm_connector *connector)
17037 {
17038 struct intel_connector *intel_connector = to_intel_connector(connector);
17039 int ret;
17040
17041 ret = intel_backlight_device_register(intel_connector);
17042 if (ret)
17043 goto err;
17044
17045 return 0;
17046
17047 err:
17048 return ret;
17049 }
17050
17051 void intel_connector_unregister(struct drm_connector *connector)
17052 {
17053 struct intel_connector *intel_connector = to_intel_connector(connector);
17054
17055 intel_backlight_device_unregister(intel_connector);
17056 intel_panel_destroy_backlight(connector);
17057 }
17058
17059 void intel_modeset_cleanup(struct drm_device *dev)
17060 {
17061 struct drm_i915_private *dev_priv = to_i915(dev);
17062
17063 intel_disable_gt_powersave(dev_priv);
17064
17065 /*
17066 * Interrupts and polling as the first thing to avoid creating havoc.
17067 * Too much stuff here (turning of connectors, ...) would
17068 * experience fancy races otherwise.
17069 */
17070 intel_irq_uninstall(dev_priv);
17071
17072 /*
17073 * Due to the hpd irq storm handling the hotplug work can re-arm the
17074 * poll handlers. Hence disable polling after hpd handling is shut down.
17075 */
17076 drm_kms_helper_poll_fini(dev);
17077
17078 intel_unregister_dsm_handler();
17079
17080 intel_fbc_global_disable(dev_priv);
17081
17082 /* flush any delayed tasks or pending work */
17083 flush_scheduled_work();
17084
17085 drm_mode_config_cleanup(dev);
17086
17087 intel_cleanup_overlay(dev_priv);
17088
17089 intel_cleanup_gt_powersave(dev_priv);
17090
17091 intel_teardown_gmbus(dev);
17092 }
17093
17094 void intel_connector_attach_encoder(struct intel_connector *connector,
17095 struct intel_encoder *encoder)
17096 {
17097 connector->encoder = encoder;
17098 drm_mode_connector_attach_encoder(&connector->base,
17099 &encoder->base);
17100 }
17101
17102 /*
17103 * set vga decode state - true == enable VGA decode
17104 */
17105 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
17106 {
17107 struct drm_i915_private *dev_priv = to_i915(dev);
17108 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
17109 u16 gmch_ctrl;
17110
17111 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
17112 DRM_ERROR("failed to read control word\n");
17113 return -EIO;
17114 }
17115
17116 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
17117 return 0;
17118
17119 if (state)
17120 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
17121 else
17122 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
17123
17124 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
17125 DRM_ERROR("failed to write control word\n");
17126 return -EIO;
17127 }
17128
17129 return 0;
17130 }
17131
17132 struct intel_display_error_state {
17133
17134 u32 power_well_driver;
17135
17136 int num_transcoders;
17137
17138 struct intel_cursor_error_state {
17139 u32 control;
17140 u32 position;
17141 u32 base;
17142 u32 size;
17143 } cursor[I915_MAX_PIPES];
17144
17145 struct intel_pipe_error_state {
17146 bool power_domain_on;
17147 u32 source;
17148 u32 stat;
17149 } pipe[I915_MAX_PIPES];
17150
17151 struct intel_plane_error_state {
17152 u32 control;
17153 u32 stride;
17154 u32 size;
17155 u32 pos;
17156 u32 addr;
17157 u32 surface;
17158 u32 tile_offset;
17159 } plane[I915_MAX_PIPES];
17160
17161 struct intel_transcoder_error_state {
17162 bool power_domain_on;
17163 enum transcoder cpu_transcoder;
17164
17165 u32 conf;
17166
17167 u32 htotal;
17168 u32 hblank;
17169 u32 hsync;
17170 u32 vtotal;
17171 u32 vblank;
17172 u32 vsync;
17173 } transcoder[4];
17174 };
17175
17176 struct intel_display_error_state *
17177 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
17178 {
17179 struct intel_display_error_state *error;
17180 int transcoders[] = {
17181 TRANSCODER_A,
17182 TRANSCODER_B,
17183 TRANSCODER_C,
17184 TRANSCODER_EDP,
17185 };
17186 int i;
17187
17188 if (INTEL_INFO(dev_priv)->num_pipes == 0)
17189 return NULL;
17190
17191 error = kzalloc(sizeof(*error), GFP_ATOMIC);
17192 if (error == NULL)
17193 return NULL;
17194
17195 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17196 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
17197
17198 for_each_pipe(dev_priv, i) {
17199 error->pipe[i].power_domain_on =
17200 __intel_display_power_is_enabled(dev_priv,
17201 POWER_DOMAIN_PIPE(i));
17202 if (!error->pipe[i].power_domain_on)
17203 continue;
17204
17205 error->cursor[i].control = I915_READ(CURCNTR(i));
17206 error->cursor[i].position = I915_READ(CURPOS(i));
17207 error->cursor[i].base = I915_READ(CURBASE(i));
17208
17209 error->plane[i].control = I915_READ(DSPCNTR(i));
17210 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
17211 if (INTEL_GEN(dev_priv) <= 3) {
17212 error->plane[i].size = I915_READ(DSPSIZE(i));
17213 error->plane[i].pos = I915_READ(DSPPOS(i));
17214 }
17215 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17216 error->plane[i].addr = I915_READ(DSPADDR(i));
17217 if (INTEL_GEN(dev_priv) >= 4) {
17218 error->plane[i].surface = I915_READ(DSPSURF(i));
17219 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
17220 }
17221
17222 error->pipe[i].source = I915_READ(PIPESRC(i));
17223
17224 if (HAS_GMCH_DISPLAY(dev_priv))
17225 error->pipe[i].stat = I915_READ(PIPESTAT(i));
17226 }
17227
17228 /* Note: this does not include DSI transcoders. */
17229 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
17230 if (HAS_DDI(dev_priv))
17231 error->num_transcoders++; /* Account for eDP. */
17232
17233 for (i = 0; i < error->num_transcoders; i++) {
17234 enum transcoder cpu_transcoder = transcoders[i];
17235
17236 error->transcoder[i].power_domain_on =
17237 __intel_display_power_is_enabled(dev_priv,
17238 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
17239 if (!error->transcoder[i].power_domain_on)
17240 continue;
17241
17242 error->transcoder[i].cpu_transcoder = cpu_transcoder;
17243
17244 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
17245 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
17246 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
17247 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
17248 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
17249 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
17250 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
17251 }
17252
17253 return error;
17254 }
17255
17256 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
17257
17258 void
17259 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
17260 struct drm_device *dev,
17261 struct intel_display_error_state *error)
17262 {
17263 struct drm_i915_private *dev_priv = to_i915(dev);
17264 int i;
17265
17266 if (!error)
17267 return;
17268
17269 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
17270 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
17271 err_printf(m, "PWR_WELL_CTL2: %08x\n",
17272 error->power_well_driver);
17273 for_each_pipe(dev_priv, i) {
17274 err_printf(m, "Pipe [%d]:\n", i);
17275 err_printf(m, " Power: %s\n",
17276 onoff(error->pipe[i].power_domain_on));
17277 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
17278 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
17279
17280 err_printf(m, "Plane [%d]:\n", i);
17281 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
17282 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
17283 if (INTEL_INFO(dev)->gen <= 3) {
17284 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
17285 err_printf(m, " POS: %08x\n", error->plane[i].pos);
17286 }
17287 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
17288 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
17289 if (INTEL_INFO(dev)->gen >= 4) {
17290 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
17291 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
17292 }
17293
17294 err_printf(m, "Cursor [%d]:\n", i);
17295 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
17296 err_printf(m, " POS: %08x\n", error->cursor[i].position);
17297 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
17298 }
17299
17300 for (i = 0; i < error->num_transcoders; i++) {
17301 err_printf(m, "CPU transcoder: %s\n",
17302 transcoder_name(error->transcoder[i].cpu_transcoder));
17303 err_printf(m, " Power: %s\n",
17304 onoff(error->transcoder[i].power_domain_on));
17305 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
17306 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
17307 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
17308 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
17309 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
17310 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
17311 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
17312 }
17313 }
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