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drm/i915: Extract i9xx_plane_ctl() and ironlake_plane_ctl()
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "i915_gem_clflush.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
51
52 static bool is_mmio_work(struct intel_flip_work *work)
53 {
54 return work->mmio_work.func;
55 }
56
57 /* Primary plane formats for gen <= 3 */
58 static const uint32_t i8xx_primary_formats[] = {
59 DRM_FORMAT_C8,
60 DRM_FORMAT_RGB565,
61 DRM_FORMAT_XRGB1555,
62 DRM_FORMAT_XRGB8888,
63 };
64
65 /* Primary plane formats for gen >= 4 */
66 static const uint32_t i965_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_XRGB2101010,
72 DRM_FORMAT_XBGR2101010,
73 };
74
75 static const uint32_t skl_primary_formats[] = {
76 DRM_FORMAT_C8,
77 DRM_FORMAT_RGB565,
78 DRM_FORMAT_XRGB8888,
79 DRM_FORMAT_XBGR8888,
80 DRM_FORMAT_ARGB8888,
81 DRM_FORMAT_ABGR8888,
82 DRM_FORMAT_XRGB2101010,
83 DRM_FORMAT_XBGR2101010,
84 DRM_FORMAT_YUYV,
85 DRM_FORMAT_YVYU,
86 DRM_FORMAT_UYVY,
87 DRM_FORMAT_VYUY,
88 };
89
90 /* Cursor formats */
91 static const uint32_t intel_cursor_formats[] = {
92 DRM_FORMAT_ARGB8888,
93 };
94
95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
96 struct intel_crtc_state *pipe_config);
97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
98 struct intel_crtc_state *pipe_config);
99
100 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
101 struct drm_i915_gem_object *obj,
102 struct drm_mode_fb_cmd2 *mode_cmd);
103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
107 struct intel_link_m_n *m_n,
108 struct intel_link_m_n *m2_n2);
109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
112 static void vlv_prepare_pll(struct intel_crtc *crtc,
113 const struct intel_crtc_state *pipe_config);
114 static void chv_prepare_pll(struct intel_crtc *crtc,
115 const struct intel_crtc_state *pipe_config);
116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
119 struct intel_crtc_state *crtc_state);
120 static void skylake_pfit_enable(struct intel_crtc *crtc);
121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
123 static void intel_modeset_setup_hw_state(struct drm_device *dev);
124 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
125
126 struct intel_limit {
127 struct {
128 int min, max;
129 } dot, vco, n, m, m1, m2, p, p1;
130
131 struct {
132 int dot_limit;
133 int p2_slow, p2_fast;
134 } p2;
135 };
136
137 /* returns HPLL frequency in kHz */
138 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
139 {
140 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
141
142 /* Obtain SKU information */
143 mutex_lock(&dev_priv->sb_lock);
144 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
145 CCK_FUSE_HPLL_FREQ_MASK;
146 mutex_unlock(&dev_priv->sb_lock);
147
148 return vco_freq[hpll_freq] * 1000;
149 }
150
151 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
152 const char *name, u32 reg, int ref_freq)
153 {
154 u32 val;
155 int divider;
156
157 mutex_lock(&dev_priv->sb_lock);
158 val = vlv_cck_read(dev_priv, reg);
159 mutex_unlock(&dev_priv->sb_lock);
160
161 divider = val & CCK_FREQUENCY_VALUES;
162
163 WARN((val & CCK_FREQUENCY_STATUS) !=
164 (divider << CCK_FREQUENCY_STATUS_SHIFT),
165 "%s change in progress\n", name);
166
167 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
168 }
169
170 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
171 const char *name, u32 reg)
172 {
173 if (dev_priv->hpll_freq == 0)
174 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
175
176 return vlv_get_cck_clock(dev_priv, name, reg,
177 dev_priv->hpll_freq);
178 }
179
180 static void intel_update_czclk(struct drm_i915_private *dev_priv)
181 {
182 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
183 return;
184
185 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
186 CCK_CZ_CLOCK_CONTROL);
187
188 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
189 }
190
191 static inline u32 /* units of 100MHz */
192 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
193 const struct intel_crtc_state *pipe_config)
194 {
195 if (HAS_DDI(dev_priv))
196 return pipe_config->port_clock; /* SPLL */
197 else if (IS_GEN5(dev_priv))
198 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
199 else
200 return 270000;
201 }
202
203 static const struct intel_limit intel_limits_i8xx_dac = {
204 .dot = { .min = 25000, .max = 350000 },
205 .vco = { .min = 908000, .max = 1512000 },
206 .n = { .min = 2, .max = 16 },
207 .m = { .min = 96, .max = 140 },
208 .m1 = { .min = 18, .max = 26 },
209 .m2 = { .min = 6, .max = 16 },
210 .p = { .min = 4, .max = 128 },
211 .p1 = { .min = 2, .max = 33 },
212 .p2 = { .dot_limit = 165000,
213 .p2_slow = 4, .p2_fast = 2 },
214 };
215
216 static const struct intel_limit intel_limits_i8xx_dvo = {
217 .dot = { .min = 25000, .max = 350000 },
218 .vco = { .min = 908000, .max = 1512000 },
219 .n = { .min = 2, .max = 16 },
220 .m = { .min = 96, .max = 140 },
221 .m1 = { .min = 18, .max = 26 },
222 .m2 = { .min = 6, .max = 16 },
223 .p = { .min = 4, .max = 128 },
224 .p1 = { .min = 2, .max = 33 },
225 .p2 = { .dot_limit = 165000,
226 .p2_slow = 4, .p2_fast = 4 },
227 };
228
229 static const struct intel_limit intel_limits_i8xx_lvds = {
230 .dot = { .min = 25000, .max = 350000 },
231 .vco = { .min = 908000, .max = 1512000 },
232 .n = { .min = 2, .max = 16 },
233 .m = { .min = 96, .max = 140 },
234 .m1 = { .min = 18, .max = 26 },
235 .m2 = { .min = 6, .max = 16 },
236 .p = { .min = 4, .max = 128 },
237 .p1 = { .min = 1, .max = 6 },
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 14, .p2_fast = 7 },
240 };
241
242 static const struct intel_limit intel_limits_i9xx_sdvo = {
243 .dot = { .min = 20000, .max = 400000 },
244 .vco = { .min = 1400000, .max = 2800000 },
245 .n = { .min = 1, .max = 6 },
246 .m = { .min = 70, .max = 120 },
247 .m1 = { .min = 8, .max = 18 },
248 .m2 = { .min = 3, .max = 7 },
249 .p = { .min = 5, .max = 80 },
250 .p1 = { .min = 1, .max = 8 },
251 .p2 = { .dot_limit = 200000,
252 .p2_slow = 10, .p2_fast = 5 },
253 };
254
255 static const struct intel_limit intel_limits_i9xx_lvds = {
256 .dot = { .min = 20000, .max = 400000 },
257 .vco = { .min = 1400000, .max = 2800000 },
258 .n = { .min = 1, .max = 6 },
259 .m = { .min = 70, .max = 120 },
260 .m1 = { .min = 8, .max = 18 },
261 .m2 = { .min = 3, .max = 7 },
262 .p = { .min = 7, .max = 98 },
263 .p1 = { .min = 1, .max = 8 },
264 .p2 = { .dot_limit = 112000,
265 .p2_slow = 14, .p2_fast = 7 },
266 };
267
268
269 static const struct intel_limit intel_limits_g4x_sdvo = {
270 .dot = { .min = 25000, .max = 270000 },
271 .vco = { .min = 1750000, .max = 3500000},
272 .n = { .min = 1, .max = 4 },
273 .m = { .min = 104, .max = 138 },
274 .m1 = { .min = 17, .max = 23 },
275 .m2 = { .min = 5, .max = 11 },
276 .p = { .min = 10, .max = 30 },
277 .p1 = { .min = 1, .max = 3},
278 .p2 = { .dot_limit = 270000,
279 .p2_slow = 10,
280 .p2_fast = 10
281 },
282 };
283
284 static const struct intel_limit intel_limits_g4x_hdmi = {
285 .dot = { .min = 22000, .max = 400000 },
286 .vco = { .min = 1750000, .max = 3500000},
287 .n = { .min = 1, .max = 4 },
288 .m = { .min = 104, .max = 138 },
289 .m1 = { .min = 16, .max = 23 },
290 .m2 = { .min = 5, .max = 11 },
291 .p = { .min = 5, .max = 80 },
292 .p1 = { .min = 1, .max = 8},
293 .p2 = { .dot_limit = 165000,
294 .p2_slow = 10, .p2_fast = 5 },
295 };
296
297 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
298 .dot = { .min = 20000, .max = 115000 },
299 .vco = { .min = 1750000, .max = 3500000 },
300 .n = { .min = 1, .max = 3 },
301 .m = { .min = 104, .max = 138 },
302 .m1 = { .min = 17, .max = 23 },
303 .m2 = { .min = 5, .max = 11 },
304 .p = { .min = 28, .max = 112 },
305 .p1 = { .min = 2, .max = 8 },
306 .p2 = { .dot_limit = 0,
307 .p2_slow = 14, .p2_fast = 14
308 },
309 };
310
311 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
312 .dot = { .min = 80000, .max = 224000 },
313 .vco = { .min = 1750000, .max = 3500000 },
314 .n = { .min = 1, .max = 3 },
315 .m = { .min = 104, .max = 138 },
316 .m1 = { .min = 17, .max = 23 },
317 .m2 = { .min = 5, .max = 11 },
318 .p = { .min = 14, .max = 42 },
319 .p1 = { .min = 2, .max = 6 },
320 .p2 = { .dot_limit = 0,
321 .p2_slow = 7, .p2_fast = 7
322 },
323 };
324
325 static const struct intel_limit intel_limits_pineview_sdvo = {
326 .dot = { .min = 20000, .max = 400000},
327 .vco = { .min = 1700000, .max = 3500000 },
328 /* Pineview's Ncounter is a ring counter */
329 .n = { .min = 3, .max = 6 },
330 .m = { .min = 2, .max = 256 },
331 /* Pineview only has one combined m divider, which we treat as m2. */
332 .m1 = { .min = 0, .max = 0 },
333 .m2 = { .min = 0, .max = 254 },
334 .p = { .min = 5, .max = 80 },
335 .p1 = { .min = 1, .max = 8 },
336 .p2 = { .dot_limit = 200000,
337 .p2_slow = 10, .p2_fast = 5 },
338 };
339
340 static const struct intel_limit intel_limits_pineview_lvds = {
341 .dot = { .min = 20000, .max = 400000 },
342 .vco = { .min = 1700000, .max = 3500000 },
343 .n = { .min = 3, .max = 6 },
344 .m = { .min = 2, .max = 256 },
345 .m1 = { .min = 0, .max = 0 },
346 .m2 = { .min = 0, .max = 254 },
347 .p = { .min = 7, .max = 112 },
348 .p1 = { .min = 1, .max = 8 },
349 .p2 = { .dot_limit = 112000,
350 .p2_slow = 14, .p2_fast = 14 },
351 };
352
353 /* Ironlake / Sandybridge
354 *
355 * We calculate clock using (register_value + 2) for N/M1/M2, so here
356 * the range value for them is (actual_value - 2).
357 */
358 static const struct intel_limit intel_limits_ironlake_dac = {
359 .dot = { .min = 25000, .max = 350000 },
360 .vco = { .min = 1760000, .max = 3510000 },
361 .n = { .min = 1, .max = 5 },
362 .m = { .min = 79, .max = 127 },
363 .m1 = { .min = 12, .max = 22 },
364 .m2 = { .min = 5, .max = 9 },
365 .p = { .min = 5, .max = 80 },
366 .p1 = { .min = 1, .max = 8 },
367 .p2 = { .dot_limit = 225000,
368 .p2_slow = 10, .p2_fast = 5 },
369 };
370
371 static const struct intel_limit intel_limits_ironlake_single_lvds = {
372 .dot = { .min = 25000, .max = 350000 },
373 .vco = { .min = 1760000, .max = 3510000 },
374 .n = { .min = 1, .max = 3 },
375 .m = { .min = 79, .max = 118 },
376 .m1 = { .min = 12, .max = 22 },
377 .m2 = { .min = 5, .max = 9 },
378 .p = { .min = 28, .max = 112 },
379 .p1 = { .min = 2, .max = 8 },
380 .p2 = { .dot_limit = 225000,
381 .p2_slow = 14, .p2_fast = 14 },
382 };
383
384 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
385 .dot = { .min = 25000, .max = 350000 },
386 .vco = { .min = 1760000, .max = 3510000 },
387 .n = { .min = 1, .max = 3 },
388 .m = { .min = 79, .max = 127 },
389 .m1 = { .min = 12, .max = 22 },
390 .m2 = { .min = 5, .max = 9 },
391 .p = { .min = 14, .max = 56 },
392 .p1 = { .min = 2, .max = 8 },
393 .p2 = { .dot_limit = 225000,
394 .p2_slow = 7, .p2_fast = 7 },
395 };
396
397 /* LVDS 100mhz refclk limits. */
398 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
399 .dot = { .min = 25000, .max = 350000 },
400 .vco = { .min = 1760000, .max = 3510000 },
401 .n = { .min = 1, .max = 2 },
402 .m = { .min = 79, .max = 126 },
403 .m1 = { .min = 12, .max = 22 },
404 .m2 = { .min = 5, .max = 9 },
405 .p = { .min = 28, .max = 112 },
406 .p1 = { .min = 2, .max = 8 },
407 .p2 = { .dot_limit = 225000,
408 .p2_slow = 14, .p2_fast = 14 },
409 };
410
411 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
412 .dot = { .min = 25000, .max = 350000 },
413 .vco = { .min = 1760000, .max = 3510000 },
414 .n = { .min = 1, .max = 3 },
415 .m = { .min = 79, .max = 126 },
416 .m1 = { .min = 12, .max = 22 },
417 .m2 = { .min = 5, .max = 9 },
418 .p = { .min = 14, .max = 42 },
419 .p1 = { .min = 2, .max = 6 },
420 .p2 = { .dot_limit = 225000,
421 .p2_slow = 7, .p2_fast = 7 },
422 };
423
424 static const struct intel_limit intel_limits_vlv = {
425 /*
426 * These are the data rate limits (measured in fast clocks)
427 * since those are the strictest limits we have. The fast
428 * clock and actual rate limits are more relaxed, so checking
429 * them would make no difference.
430 */
431 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
432 .vco = { .min = 4000000, .max = 6000000 },
433 .n = { .min = 1, .max = 7 },
434 .m1 = { .min = 2, .max = 3 },
435 .m2 = { .min = 11, .max = 156 },
436 .p1 = { .min = 2, .max = 3 },
437 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
438 };
439
440 static const struct intel_limit intel_limits_chv = {
441 /*
442 * These are the data rate limits (measured in fast clocks)
443 * since those are the strictest limits we have. The fast
444 * clock and actual rate limits are more relaxed, so checking
445 * them would make no difference.
446 */
447 .dot = { .min = 25000 * 5, .max = 540000 * 5},
448 .vco = { .min = 4800000, .max = 6480000 },
449 .n = { .min = 1, .max = 1 },
450 .m1 = { .min = 2, .max = 2 },
451 .m2 = { .min = 24 << 22, .max = 175 << 22 },
452 .p1 = { .min = 2, .max = 4 },
453 .p2 = { .p2_slow = 1, .p2_fast = 14 },
454 };
455
456 static const struct intel_limit intel_limits_bxt = {
457 /* FIXME: find real dot limits */
458 .dot = { .min = 0, .max = INT_MAX },
459 .vco = { .min = 4800000, .max = 6700000 },
460 .n = { .min = 1, .max = 1 },
461 .m1 = { .min = 2, .max = 2 },
462 /* FIXME: find real m2 limits */
463 .m2 = { .min = 2 << 22, .max = 255 << 22 },
464 .p1 = { .min = 2, .max = 4 },
465 .p2 = { .p2_slow = 1, .p2_fast = 20 },
466 };
467
468 static bool
469 needs_modeset(struct drm_crtc_state *state)
470 {
471 return drm_atomic_crtc_needs_modeset(state);
472 }
473
474 /*
475 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
476 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
477 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
478 * The helpers' return value is the rate of the clock that is fed to the
479 * display engine's pipe which can be the above fast dot clock rate or a
480 * divided-down version of it.
481 */
482 /* m1 is reserved as 0 in Pineview, n is a ring counter */
483 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
484 {
485 clock->m = clock->m2 + 2;
486 clock->p = clock->p1 * clock->p2;
487 if (WARN_ON(clock->n == 0 || clock->p == 0))
488 return 0;
489 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
490 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
491
492 return clock->dot;
493 }
494
495 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
496 {
497 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
498 }
499
500 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
501 {
502 clock->m = i9xx_dpll_compute_m(clock);
503 clock->p = clock->p1 * clock->p2;
504 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
505 return 0;
506 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
507 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
508
509 return clock->dot;
510 }
511
512 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
513 {
514 clock->m = clock->m1 * clock->m2;
515 clock->p = clock->p1 * clock->p2;
516 if (WARN_ON(clock->n == 0 || clock->p == 0))
517 return 0;
518 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
519 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
520
521 return clock->dot / 5;
522 }
523
524 int chv_calc_dpll_params(int refclk, struct dpll *clock)
525 {
526 clock->m = clock->m1 * clock->m2;
527 clock->p = clock->p1 * clock->p2;
528 if (WARN_ON(clock->n == 0 || clock->p == 0))
529 return 0;
530 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
531 clock->n << 22);
532 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
533
534 return clock->dot / 5;
535 }
536
537 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
538 /**
539 * Returns whether the given set of divisors are valid for a given refclk with
540 * the given connectors.
541 */
542
543 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
544 const struct intel_limit *limit,
545 const struct dpll *clock)
546 {
547 if (clock->n < limit->n.min || limit->n.max < clock->n)
548 INTELPllInvalid("n out of range\n");
549 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
550 INTELPllInvalid("p1 out of range\n");
551 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
552 INTELPllInvalid("m2 out of range\n");
553 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
554 INTELPllInvalid("m1 out of range\n");
555
556 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
557 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
558 if (clock->m1 <= clock->m2)
559 INTELPllInvalid("m1 <= m2\n");
560
561 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
562 !IS_GEN9_LP(dev_priv)) {
563 if (clock->p < limit->p.min || limit->p.max < clock->p)
564 INTELPllInvalid("p out of range\n");
565 if (clock->m < limit->m.min || limit->m.max < clock->m)
566 INTELPllInvalid("m out of range\n");
567 }
568
569 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
570 INTELPllInvalid("vco out of range\n");
571 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
572 * connector, etc., rather than just a single range.
573 */
574 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
575 INTELPllInvalid("dot out of range\n");
576
577 return true;
578 }
579
580 static int
581 i9xx_select_p2_div(const struct intel_limit *limit,
582 const struct intel_crtc_state *crtc_state,
583 int target)
584 {
585 struct drm_device *dev = crtc_state->base.crtc->dev;
586
587 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
588 /*
589 * For LVDS just rely on its current settings for dual-channel.
590 * We haven't figured out how to reliably set up different
591 * single/dual channel state, if we even can.
592 */
593 if (intel_is_dual_link_lvds(dev))
594 return limit->p2.p2_fast;
595 else
596 return limit->p2.p2_slow;
597 } else {
598 if (target < limit->p2.dot_limit)
599 return limit->p2.p2_slow;
600 else
601 return limit->p2.p2_fast;
602 }
603 }
604
605 /*
606 * Returns a set of divisors for the desired target clock with the given
607 * refclk, or FALSE. The returned values represent the clock equation:
608 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
609 *
610 * Target and reference clocks are specified in kHz.
611 *
612 * If match_clock is provided, then best_clock P divider must match the P
613 * divider from @match_clock used for LVDS downclocking.
614 */
615 static bool
616 i9xx_find_best_dpll(const struct intel_limit *limit,
617 struct intel_crtc_state *crtc_state,
618 int target, int refclk, struct dpll *match_clock,
619 struct dpll *best_clock)
620 {
621 struct drm_device *dev = crtc_state->base.crtc->dev;
622 struct dpll clock;
623 int err = target;
624
625 memset(best_clock, 0, sizeof(*best_clock));
626
627 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
628
629 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
630 clock.m1++) {
631 for (clock.m2 = limit->m2.min;
632 clock.m2 <= limit->m2.max; clock.m2++) {
633 if (clock.m2 >= clock.m1)
634 break;
635 for (clock.n = limit->n.min;
636 clock.n <= limit->n.max; clock.n++) {
637 for (clock.p1 = limit->p1.min;
638 clock.p1 <= limit->p1.max; clock.p1++) {
639 int this_err;
640
641 i9xx_calc_dpll_params(refclk, &clock);
642 if (!intel_PLL_is_valid(to_i915(dev),
643 limit,
644 &clock))
645 continue;
646 if (match_clock &&
647 clock.p != match_clock->p)
648 continue;
649
650 this_err = abs(clock.dot - target);
651 if (this_err < err) {
652 *best_clock = clock;
653 err = this_err;
654 }
655 }
656 }
657 }
658 }
659
660 return (err != target);
661 }
662
663 /*
664 * Returns a set of divisors for the desired target clock with the given
665 * refclk, or FALSE. The returned values represent the clock equation:
666 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
667 *
668 * Target and reference clocks are specified in kHz.
669 *
670 * If match_clock is provided, then best_clock P divider must match the P
671 * divider from @match_clock used for LVDS downclocking.
672 */
673 static bool
674 pnv_find_best_dpll(const struct intel_limit *limit,
675 struct intel_crtc_state *crtc_state,
676 int target, int refclk, struct dpll *match_clock,
677 struct dpll *best_clock)
678 {
679 struct drm_device *dev = crtc_state->base.crtc->dev;
680 struct dpll clock;
681 int err = target;
682
683 memset(best_clock, 0, sizeof(*best_clock));
684
685 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
686
687 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
688 clock.m1++) {
689 for (clock.m2 = limit->m2.min;
690 clock.m2 <= limit->m2.max; clock.m2++) {
691 for (clock.n = limit->n.min;
692 clock.n <= limit->n.max; clock.n++) {
693 for (clock.p1 = limit->p1.min;
694 clock.p1 <= limit->p1.max; clock.p1++) {
695 int this_err;
696
697 pnv_calc_dpll_params(refclk, &clock);
698 if (!intel_PLL_is_valid(to_i915(dev),
699 limit,
700 &clock))
701 continue;
702 if (match_clock &&
703 clock.p != match_clock->p)
704 continue;
705
706 this_err = abs(clock.dot - target);
707 if (this_err < err) {
708 *best_clock = clock;
709 err = this_err;
710 }
711 }
712 }
713 }
714 }
715
716 return (err != target);
717 }
718
719 /*
720 * Returns a set of divisors for the desired target clock with the given
721 * refclk, or FALSE. The returned values represent the clock equation:
722 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
723 *
724 * Target and reference clocks are specified in kHz.
725 *
726 * If match_clock is provided, then best_clock P divider must match the P
727 * divider from @match_clock used for LVDS downclocking.
728 */
729 static bool
730 g4x_find_best_dpll(const struct intel_limit *limit,
731 struct intel_crtc_state *crtc_state,
732 int target, int refclk, struct dpll *match_clock,
733 struct dpll *best_clock)
734 {
735 struct drm_device *dev = crtc_state->base.crtc->dev;
736 struct dpll clock;
737 int max_n;
738 bool found = false;
739 /* approximately equals target * 0.00585 */
740 int err_most = (target >> 8) + (target >> 9);
741
742 memset(best_clock, 0, sizeof(*best_clock));
743
744 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
745
746 max_n = limit->n.max;
747 /* based on hardware requirement, prefer smaller n to precision */
748 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
749 /* based on hardware requirement, prefere larger m1,m2 */
750 for (clock.m1 = limit->m1.max;
751 clock.m1 >= limit->m1.min; clock.m1--) {
752 for (clock.m2 = limit->m2.max;
753 clock.m2 >= limit->m2.min; clock.m2--) {
754 for (clock.p1 = limit->p1.max;
755 clock.p1 >= limit->p1.min; clock.p1--) {
756 int this_err;
757
758 i9xx_calc_dpll_params(refclk, &clock);
759 if (!intel_PLL_is_valid(to_i915(dev),
760 limit,
761 &clock))
762 continue;
763
764 this_err = abs(clock.dot - target);
765 if (this_err < err_most) {
766 *best_clock = clock;
767 err_most = this_err;
768 max_n = clock.n;
769 found = true;
770 }
771 }
772 }
773 }
774 }
775 return found;
776 }
777
778 /*
779 * Check if the calculated PLL configuration is more optimal compared to the
780 * best configuration and error found so far. Return the calculated error.
781 */
782 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
783 const struct dpll *calculated_clock,
784 const struct dpll *best_clock,
785 unsigned int best_error_ppm,
786 unsigned int *error_ppm)
787 {
788 /*
789 * For CHV ignore the error and consider only the P value.
790 * Prefer a bigger P value based on HW requirements.
791 */
792 if (IS_CHERRYVIEW(to_i915(dev))) {
793 *error_ppm = 0;
794
795 return calculated_clock->p > best_clock->p;
796 }
797
798 if (WARN_ON_ONCE(!target_freq))
799 return false;
800
801 *error_ppm = div_u64(1000000ULL *
802 abs(target_freq - calculated_clock->dot),
803 target_freq);
804 /*
805 * Prefer a better P value over a better (smaller) error if the error
806 * is small. Ensure this preference for future configurations too by
807 * setting the error to 0.
808 */
809 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
810 *error_ppm = 0;
811
812 return true;
813 }
814
815 return *error_ppm + 10 < best_error_ppm;
816 }
817
818 /*
819 * Returns a set of divisors for the desired target clock with the given
820 * refclk, or FALSE. The returned values represent the clock equation:
821 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
822 */
823 static bool
824 vlv_find_best_dpll(const struct intel_limit *limit,
825 struct intel_crtc_state *crtc_state,
826 int target, int refclk, struct dpll *match_clock,
827 struct dpll *best_clock)
828 {
829 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
830 struct drm_device *dev = crtc->base.dev;
831 struct dpll clock;
832 unsigned int bestppm = 1000000;
833 /* min update 19.2 MHz */
834 int max_n = min(limit->n.max, refclk / 19200);
835 bool found = false;
836
837 target *= 5; /* fast clock */
838
839 memset(best_clock, 0, sizeof(*best_clock));
840
841 /* based on hardware requirement, prefer smaller n to precision */
842 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
843 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
844 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
845 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
846 clock.p = clock.p1 * clock.p2;
847 /* based on hardware requirement, prefer bigger m1,m2 values */
848 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
849 unsigned int ppm;
850
851 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
852 refclk * clock.m1);
853
854 vlv_calc_dpll_params(refclk, &clock);
855
856 if (!intel_PLL_is_valid(to_i915(dev),
857 limit,
858 &clock))
859 continue;
860
861 if (!vlv_PLL_is_optimal(dev, target,
862 &clock,
863 best_clock,
864 bestppm, &ppm))
865 continue;
866
867 *best_clock = clock;
868 bestppm = ppm;
869 found = true;
870 }
871 }
872 }
873 }
874
875 return found;
876 }
877
878 /*
879 * Returns a set of divisors for the desired target clock with the given
880 * refclk, or FALSE. The returned values represent the clock equation:
881 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
882 */
883 static bool
884 chv_find_best_dpll(const struct intel_limit *limit,
885 struct intel_crtc_state *crtc_state,
886 int target, int refclk, struct dpll *match_clock,
887 struct dpll *best_clock)
888 {
889 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
890 struct drm_device *dev = crtc->base.dev;
891 unsigned int best_error_ppm;
892 struct dpll clock;
893 uint64_t m2;
894 int found = false;
895
896 memset(best_clock, 0, sizeof(*best_clock));
897 best_error_ppm = 1000000;
898
899 /*
900 * Based on hardware doc, the n always set to 1, and m1 always
901 * set to 2. If requires to support 200Mhz refclk, we need to
902 * revisit this because n may not 1 anymore.
903 */
904 clock.n = 1, clock.m1 = 2;
905 target *= 5; /* fast clock */
906
907 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
908 for (clock.p2 = limit->p2.p2_fast;
909 clock.p2 >= limit->p2.p2_slow;
910 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
911 unsigned int error_ppm;
912
913 clock.p = clock.p1 * clock.p2;
914
915 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
916 clock.n) << 22, refclk * clock.m1);
917
918 if (m2 > INT_MAX/clock.m1)
919 continue;
920
921 clock.m2 = m2;
922
923 chv_calc_dpll_params(refclk, &clock);
924
925 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
926 continue;
927
928 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
929 best_error_ppm, &error_ppm))
930 continue;
931
932 *best_clock = clock;
933 best_error_ppm = error_ppm;
934 found = true;
935 }
936 }
937
938 return found;
939 }
940
941 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
942 struct dpll *best_clock)
943 {
944 int refclk = 100000;
945 const struct intel_limit *limit = &intel_limits_bxt;
946
947 return chv_find_best_dpll(limit, crtc_state,
948 target_clock, refclk, NULL, best_clock);
949 }
950
951 bool intel_crtc_active(struct intel_crtc *crtc)
952 {
953 /* Be paranoid as we can arrive here with only partial
954 * state retrieved from the hardware during setup.
955 *
956 * We can ditch the adjusted_mode.crtc_clock check as soon
957 * as Haswell has gained clock readout/fastboot support.
958 *
959 * We can ditch the crtc->primary->fb check as soon as we can
960 * properly reconstruct framebuffers.
961 *
962 * FIXME: The intel_crtc->active here should be switched to
963 * crtc->state->active once we have proper CRTC states wired up
964 * for atomic.
965 */
966 return crtc->active && crtc->base.primary->state->fb &&
967 crtc->config->base.adjusted_mode.crtc_clock;
968 }
969
970 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
971 enum pipe pipe)
972 {
973 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
974
975 return crtc->config->cpu_transcoder;
976 }
977
978 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
979 {
980 i915_reg_t reg = PIPEDSL(pipe);
981 u32 line1, line2;
982 u32 line_mask;
983
984 if (IS_GEN2(dev_priv))
985 line_mask = DSL_LINEMASK_GEN2;
986 else
987 line_mask = DSL_LINEMASK_GEN3;
988
989 line1 = I915_READ(reg) & line_mask;
990 msleep(5);
991 line2 = I915_READ(reg) & line_mask;
992
993 return line1 == line2;
994 }
995
996 /*
997 * intel_wait_for_pipe_off - wait for pipe to turn off
998 * @crtc: crtc whose pipe to wait for
999 *
1000 * After disabling a pipe, we can't wait for vblank in the usual way,
1001 * spinning on the vblank interrupt status bit, since we won't actually
1002 * see an interrupt when the pipe is disabled.
1003 *
1004 * On Gen4 and above:
1005 * wait for the pipe register state bit to turn off
1006 *
1007 * Otherwise:
1008 * wait for the display line value to settle (it usually
1009 * ends up stopping at the start of the next frame).
1010 *
1011 */
1012 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1013 {
1014 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1015 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1016 enum pipe pipe = crtc->pipe;
1017
1018 if (INTEL_GEN(dev_priv) >= 4) {
1019 i915_reg_t reg = PIPECONF(cpu_transcoder);
1020
1021 /* Wait for the Pipe State to go off */
1022 if (intel_wait_for_register(dev_priv,
1023 reg, I965_PIPECONF_ACTIVE, 0,
1024 100))
1025 WARN(1, "pipe_off wait timed out\n");
1026 } else {
1027 /* Wait for the display line to settle */
1028 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1029 WARN(1, "pipe_off wait timed out\n");
1030 }
1031 }
1032
1033 /* Only for pre-ILK configs */
1034 void assert_pll(struct drm_i915_private *dev_priv,
1035 enum pipe pipe, bool state)
1036 {
1037 u32 val;
1038 bool cur_state;
1039
1040 val = I915_READ(DPLL(pipe));
1041 cur_state = !!(val & DPLL_VCO_ENABLE);
1042 I915_STATE_WARN(cur_state != state,
1043 "PLL state assertion failure (expected %s, current %s)\n",
1044 onoff(state), onoff(cur_state));
1045 }
1046
1047 /* XXX: the dsi pll is shared between MIPI DSI ports */
1048 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1049 {
1050 u32 val;
1051 bool cur_state;
1052
1053 mutex_lock(&dev_priv->sb_lock);
1054 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1055 mutex_unlock(&dev_priv->sb_lock);
1056
1057 cur_state = val & DSI_PLL_VCO_EN;
1058 I915_STATE_WARN(cur_state != state,
1059 "DSI PLL state assertion failure (expected %s, current %s)\n",
1060 onoff(state), onoff(cur_state));
1061 }
1062
1063 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1064 enum pipe pipe, bool state)
1065 {
1066 bool cur_state;
1067 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1068 pipe);
1069
1070 if (HAS_DDI(dev_priv)) {
1071 /* DDI does not have a specific FDI_TX register */
1072 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1073 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1074 } else {
1075 u32 val = I915_READ(FDI_TX_CTL(pipe));
1076 cur_state = !!(val & FDI_TX_ENABLE);
1077 }
1078 I915_STATE_WARN(cur_state != state,
1079 "FDI TX state assertion failure (expected %s, current %s)\n",
1080 onoff(state), onoff(cur_state));
1081 }
1082 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1083 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1084
1085 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1086 enum pipe pipe, bool state)
1087 {
1088 u32 val;
1089 bool cur_state;
1090
1091 val = I915_READ(FDI_RX_CTL(pipe));
1092 cur_state = !!(val & FDI_RX_ENABLE);
1093 I915_STATE_WARN(cur_state != state,
1094 "FDI RX state assertion failure (expected %s, current %s)\n",
1095 onoff(state), onoff(cur_state));
1096 }
1097 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1098 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1099
1100 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1101 enum pipe pipe)
1102 {
1103 u32 val;
1104
1105 /* ILK FDI PLL is always enabled */
1106 if (IS_GEN5(dev_priv))
1107 return;
1108
1109 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1110 if (HAS_DDI(dev_priv))
1111 return;
1112
1113 val = I915_READ(FDI_TX_CTL(pipe));
1114 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1115 }
1116
1117 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1118 enum pipe pipe, bool state)
1119 {
1120 u32 val;
1121 bool cur_state;
1122
1123 val = I915_READ(FDI_RX_CTL(pipe));
1124 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1125 I915_STATE_WARN(cur_state != state,
1126 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1127 onoff(state), onoff(cur_state));
1128 }
1129
1130 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1131 {
1132 i915_reg_t pp_reg;
1133 u32 val;
1134 enum pipe panel_pipe = PIPE_A;
1135 bool locked = true;
1136
1137 if (WARN_ON(HAS_DDI(dev_priv)))
1138 return;
1139
1140 if (HAS_PCH_SPLIT(dev_priv)) {
1141 u32 port_sel;
1142
1143 pp_reg = PP_CONTROL(0);
1144 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1145
1146 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1147 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1148 panel_pipe = PIPE_B;
1149 /* XXX: else fix for eDP */
1150 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1151 /* presumably write lock depends on pipe, not port select */
1152 pp_reg = PP_CONTROL(pipe);
1153 panel_pipe = pipe;
1154 } else {
1155 pp_reg = PP_CONTROL(0);
1156 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1157 panel_pipe = PIPE_B;
1158 }
1159
1160 val = I915_READ(pp_reg);
1161 if (!(val & PANEL_POWER_ON) ||
1162 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1163 locked = false;
1164
1165 I915_STATE_WARN(panel_pipe == pipe && locked,
1166 "panel assertion failure, pipe %c regs locked\n",
1167 pipe_name(pipe));
1168 }
1169
1170 static void assert_cursor(struct drm_i915_private *dev_priv,
1171 enum pipe pipe, bool state)
1172 {
1173 bool cur_state;
1174
1175 if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1176 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1177 else
1178 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1179
1180 I915_STATE_WARN(cur_state != state,
1181 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1182 pipe_name(pipe), onoff(state), onoff(cur_state));
1183 }
1184 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1185 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1186
1187 void assert_pipe(struct drm_i915_private *dev_priv,
1188 enum pipe pipe, bool state)
1189 {
1190 bool cur_state;
1191 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1192 pipe);
1193 enum intel_display_power_domain power_domain;
1194
1195 /* if we need the pipe quirk it must be always on */
1196 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1197 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1198 state = true;
1199
1200 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1201 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1202 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1203 cur_state = !!(val & PIPECONF_ENABLE);
1204
1205 intel_display_power_put(dev_priv, power_domain);
1206 } else {
1207 cur_state = false;
1208 }
1209
1210 I915_STATE_WARN(cur_state != state,
1211 "pipe %c assertion failure (expected %s, current %s)\n",
1212 pipe_name(pipe), onoff(state), onoff(cur_state));
1213 }
1214
1215 static void assert_plane(struct drm_i915_private *dev_priv,
1216 enum plane plane, bool state)
1217 {
1218 u32 val;
1219 bool cur_state;
1220
1221 val = I915_READ(DSPCNTR(plane));
1222 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1223 I915_STATE_WARN(cur_state != state,
1224 "plane %c assertion failure (expected %s, current %s)\n",
1225 plane_name(plane), onoff(state), onoff(cur_state));
1226 }
1227
1228 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1229 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1230
1231 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1232 enum pipe pipe)
1233 {
1234 int i;
1235
1236 /* Primary planes are fixed to pipes on gen4+ */
1237 if (INTEL_GEN(dev_priv) >= 4) {
1238 u32 val = I915_READ(DSPCNTR(pipe));
1239 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1240 "plane %c assertion failure, should be disabled but not\n",
1241 plane_name(pipe));
1242 return;
1243 }
1244
1245 /* Need to check both planes against the pipe */
1246 for_each_pipe(dev_priv, i) {
1247 u32 val = I915_READ(DSPCNTR(i));
1248 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1249 DISPPLANE_SEL_PIPE_SHIFT;
1250 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1251 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1252 plane_name(i), pipe_name(pipe));
1253 }
1254 }
1255
1256 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1257 enum pipe pipe)
1258 {
1259 int sprite;
1260
1261 if (INTEL_GEN(dev_priv) >= 9) {
1262 for_each_sprite(dev_priv, pipe, sprite) {
1263 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1264 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1265 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1266 sprite, pipe_name(pipe));
1267 }
1268 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1269 for_each_sprite(dev_priv, pipe, sprite) {
1270 u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1271 I915_STATE_WARN(val & SP_ENABLE,
1272 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1273 sprite_name(pipe, sprite), pipe_name(pipe));
1274 }
1275 } else if (INTEL_GEN(dev_priv) >= 7) {
1276 u32 val = I915_READ(SPRCTL(pipe));
1277 I915_STATE_WARN(val & SPRITE_ENABLE,
1278 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1279 plane_name(pipe), pipe_name(pipe));
1280 } else if (INTEL_GEN(dev_priv) >= 5) {
1281 u32 val = I915_READ(DVSCNTR(pipe));
1282 I915_STATE_WARN(val & DVS_ENABLE,
1283 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1284 plane_name(pipe), pipe_name(pipe));
1285 }
1286 }
1287
1288 static void assert_vblank_disabled(struct drm_crtc *crtc)
1289 {
1290 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1291 drm_crtc_vblank_put(crtc);
1292 }
1293
1294 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1295 enum pipe pipe)
1296 {
1297 u32 val;
1298 bool enabled;
1299
1300 val = I915_READ(PCH_TRANSCONF(pipe));
1301 enabled = !!(val & TRANS_ENABLE);
1302 I915_STATE_WARN(enabled,
1303 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1304 pipe_name(pipe));
1305 }
1306
1307 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1308 enum pipe pipe, u32 port_sel, u32 val)
1309 {
1310 if ((val & DP_PORT_EN) == 0)
1311 return false;
1312
1313 if (HAS_PCH_CPT(dev_priv)) {
1314 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else if (IS_CHERRYVIEW(dev_priv)) {
1318 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1319 return false;
1320 } else {
1321 if ((val & DP_PIPE_MASK) != (pipe << 30))
1322 return false;
1323 }
1324 return true;
1325 }
1326
1327 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328 enum pipe pipe, u32 val)
1329 {
1330 if ((val & SDVO_ENABLE) == 0)
1331 return false;
1332
1333 if (HAS_PCH_CPT(dev_priv)) {
1334 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1335 return false;
1336 } else if (IS_CHERRYVIEW(dev_priv)) {
1337 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1338 return false;
1339 } else {
1340 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1341 return false;
1342 }
1343 return true;
1344 }
1345
1346 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1347 enum pipe pipe, u32 val)
1348 {
1349 if ((val & LVDS_PORT_EN) == 0)
1350 return false;
1351
1352 if (HAS_PCH_CPT(dev_priv)) {
1353 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1354 return false;
1355 } else {
1356 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1357 return false;
1358 }
1359 return true;
1360 }
1361
1362 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1363 enum pipe pipe, u32 val)
1364 {
1365 if ((val & ADPA_DAC_ENABLE) == 0)
1366 return false;
1367 if (HAS_PCH_CPT(dev_priv)) {
1368 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1369 return false;
1370 } else {
1371 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1372 return false;
1373 }
1374 return true;
1375 }
1376
1377 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1378 enum pipe pipe, i915_reg_t reg,
1379 u32 port_sel)
1380 {
1381 u32 val = I915_READ(reg);
1382 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1383 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1384 i915_mmio_reg_offset(reg), pipe_name(pipe));
1385
1386 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1387 && (val & DP_PIPEB_SELECT),
1388 "IBX PCH dp port still using transcoder B\n");
1389 }
1390
1391 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1392 enum pipe pipe, i915_reg_t reg)
1393 {
1394 u32 val = I915_READ(reg);
1395 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1396 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1397 i915_mmio_reg_offset(reg), pipe_name(pipe));
1398
1399 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1400 && (val & SDVO_PIPE_B_SELECT),
1401 "IBX PCH hdmi port still using transcoder B\n");
1402 }
1403
1404 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1405 enum pipe pipe)
1406 {
1407 u32 val;
1408
1409 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1410 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1411 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1412
1413 val = I915_READ(PCH_ADPA);
1414 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1415 "PCH VGA enabled on transcoder %c, should be disabled\n",
1416 pipe_name(pipe));
1417
1418 val = I915_READ(PCH_LVDS);
1419 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1420 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1421 pipe_name(pipe));
1422
1423 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1424 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1425 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1426 }
1427
1428 static void _vlv_enable_pll(struct intel_crtc *crtc,
1429 const struct intel_crtc_state *pipe_config)
1430 {
1431 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1432 enum pipe pipe = crtc->pipe;
1433
1434 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1435 POSTING_READ(DPLL(pipe));
1436 udelay(150);
1437
1438 if (intel_wait_for_register(dev_priv,
1439 DPLL(pipe),
1440 DPLL_LOCK_VLV,
1441 DPLL_LOCK_VLV,
1442 1))
1443 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1444 }
1445
1446 static void vlv_enable_pll(struct intel_crtc *crtc,
1447 const struct intel_crtc_state *pipe_config)
1448 {
1449 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1450 enum pipe pipe = crtc->pipe;
1451
1452 assert_pipe_disabled(dev_priv, pipe);
1453
1454 /* PLL is protected by panel, make sure we can write it */
1455 assert_panel_unlocked(dev_priv, pipe);
1456
1457 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1458 _vlv_enable_pll(crtc, pipe_config);
1459
1460 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1461 POSTING_READ(DPLL_MD(pipe));
1462 }
1463
1464
1465 static void _chv_enable_pll(struct intel_crtc *crtc,
1466 const struct intel_crtc_state *pipe_config)
1467 {
1468 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1469 enum pipe pipe = crtc->pipe;
1470 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1471 u32 tmp;
1472
1473 mutex_lock(&dev_priv->sb_lock);
1474
1475 /* Enable back the 10bit clock to display controller */
1476 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1477 tmp |= DPIO_DCLKP_EN;
1478 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1479
1480 mutex_unlock(&dev_priv->sb_lock);
1481
1482 /*
1483 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1484 */
1485 udelay(1);
1486
1487 /* Enable PLL */
1488 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1489
1490 /* Check PLL is locked */
1491 if (intel_wait_for_register(dev_priv,
1492 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1493 1))
1494 DRM_ERROR("PLL %d failed to lock\n", pipe);
1495 }
1496
1497 static void chv_enable_pll(struct intel_crtc *crtc,
1498 const struct intel_crtc_state *pipe_config)
1499 {
1500 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1501 enum pipe pipe = crtc->pipe;
1502
1503 assert_pipe_disabled(dev_priv, pipe);
1504
1505 /* PLL is protected by panel, make sure we can write it */
1506 assert_panel_unlocked(dev_priv, pipe);
1507
1508 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1509 _chv_enable_pll(crtc, pipe_config);
1510
1511 if (pipe != PIPE_A) {
1512 /*
1513 * WaPixelRepeatModeFixForC0:chv
1514 *
1515 * DPLLCMD is AWOL. Use chicken bits to propagate
1516 * the value from DPLLBMD to either pipe B or C.
1517 */
1518 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1519 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1520 I915_WRITE(CBR4_VLV, 0);
1521 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1522
1523 /*
1524 * DPLLB VGA mode also seems to cause problems.
1525 * We should always have it disabled.
1526 */
1527 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1528 } else {
1529 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1530 POSTING_READ(DPLL_MD(pipe));
1531 }
1532 }
1533
1534 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1535 {
1536 struct intel_crtc *crtc;
1537 int count = 0;
1538
1539 for_each_intel_crtc(&dev_priv->drm, crtc) {
1540 count += crtc->base.state->active &&
1541 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1542 }
1543
1544 return count;
1545 }
1546
1547 static void i9xx_enable_pll(struct intel_crtc *crtc)
1548 {
1549 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1550 i915_reg_t reg = DPLL(crtc->pipe);
1551 u32 dpll = crtc->config->dpll_hw_state.dpll;
1552
1553 assert_pipe_disabled(dev_priv, crtc->pipe);
1554
1555 /* PLL is protected by panel, make sure we can write it */
1556 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1557 assert_panel_unlocked(dev_priv, crtc->pipe);
1558
1559 /* Enable DVO 2x clock on both PLLs if necessary */
1560 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1561 /*
1562 * It appears to be important that we don't enable this
1563 * for the current pipe before otherwise configuring the
1564 * PLL. No idea how this should be handled if multiple
1565 * DVO outputs are enabled simultaneosly.
1566 */
1567 dpll |= DPLL_DVO_2X_MODE;
1568 I915_WRITE(DPLL(!crtc->pipe),
1569 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1570 }
1571
1572 /*
1573 * Apparently we need to have VGA mode enabled prior to changing
1574 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1575 * dividers, even though the register value does change.
1576 */
1577 I915_WRITE(reg, 0);
1578
1579 I915_WRITE(reg, dpll);
1580
1581 /* Wait for the clocks to stabilize. */
1582 POSTING_READ(reg);
1583 udelay(150);
1584
1585 if (INTEL_GEN(dev_priv) >= 4) {
1586 I915_WRITE(DPLL_MD(crtc->pipe),
1587 crtc->config->dpll_hw_state.dpll_md);
1588 } else {
1589 /* The pixel multiplier can only be updated once the
1590 * DPLL is enabled and the clocks are stable.
1591 *
1592 * So write it again.
1593 */
1594 I915_WRITE(reg, dpll);
1595 }
1596
1597 /* We do this three times for luck */
1598 I915_WRITE(reg, dpll);
1599 POSTING_READ(reg);
1600 udelay(150); /* wait for warmup */
1601 I915_WRITE(reg, dpll);
1602 POSTING_READ(reg);
1603 udelay(150); /* wait for warmup */
1604 I915_WRITE(reg, dpll);
1605 POSTING_READ(reg);
1606 udelay(150); /* wait for warmup */
1607 }
1608
1609 /**
1610 * i9xx_disable_pll - disable a PLL
1611 * @dev_priv: i915 private structure
1612 * @pipe: pipe PLL to disable
1613 *
1614 * Disable the PLL for @pipe, making sure the pipe is off first.
1615 *
1616 * Note! This is for pre-ILK only.
1617 */
1618 static void i9xx_disable_pll(struct intel_crtc *crtc)
1619 {
1620 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1621 enum pipe pipe = crtc->pipe;
1622
1623 /* Disable DVO 2x clock on both PLLs if necessary */
1624 if (IS_I830(dev_priv) &&
1625 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1626 !intel_num_dvo_pipes(dev_priv)) {
1627 I915_WRITE(DPLL(PIPE_B),
1628 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1629 I915_WRITE(DPLL(PIPE_A),
1630 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1631 }
1632
1633 /* Don't disable pipe or pipe PLLs if needed */
1634 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1635 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1636 return;
1637
1638 /* Make sure the pipe isn't still relying on us */
1639 assert_pipe_disabled(dev_priv, pipe);
1640
1641 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1642 POSTING_READ(DPLL(pipe));
1643 }
1644
1645 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1646 {
1647 u32 val;
1648
1649 /* Make sure the pipe isn't still relying on us */
1650 assert_pipe_disabled(dev_priv, pipe);
1651
1652 val = DPLL_INTEGRATED_REF_CLK_VLV |
1653 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1654 if (pipe != PIPE_A)
1655 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1656
1657 I915_WRITE(DPLL(pipe), val);
1658 POSTING_READ(DPLL(pipe));
1659 }
1660
1661 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1662 {
1663 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1664 u32 val;
1665
1666 /* Make sure the pipe isn't still relying on us */
1667 assert_pipe_disabled(dev_priv, pipe);
1668
1669 val = DPLL_SSC_REF_CLK_CHV |
1670 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1671 if (pipe != PIPE_A)
1672 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1673
1674 I915_WRITE(DPLL(pipe), val);
1675 POSTING_READ(DPLL(pipe));
1676
1677 mutex_lock(&dev_priv->sb_lock);
1678
1679 /* Disable 10bit clock to display controller */
1680 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1681 val &= ~DPIO_DCLKP_EN;
1682 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1683
1684 mutex_unlock(&dev_priv->sb_lock);
1685 }
1686
1687 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1688 struct intel_digital_port *dport,
1689 unsigned int expected_mask)
1690 {
1691 u32 port_mask;
1692 i915_reg_t dpll_reg;
1693
1694 switch (dport->port) {
1695 case PORT_B:
1696 port_mask = DPLL_PORTB_READY_MASK;
1697 dpll_reg = DPLL(0);
1698 break;
1699 case PORT_C:
1700 port_mask = DPLL_PORTC_READY_MASK;
1701 dpll_reg = DPLL(0);
1702 expected_mask <<= 4;
1703 break;
1704 case PORT_D:
1705 port_mask = DPLL_PORTD_READY_MASK;
1706 dpll_reg = DPIO_PHY_STATUS;
1707 break;
1708 default:
1709 BUG();
1710 }
1711
1712 if (intel_wait_for_register(dev_priv,
1713 dpll_reg, port_mask, expected_mask,
1714 1000))
1715 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1716 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1717 }
1718
1719 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1720 enum pipe pipe)
1721 {
1722 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1723 pipe);
1724 i915_reg_t reg;
1725 uint32_t val, pipeconf_val;
1726
1727 /* Make sure PCH DPLL is enabled */
1728 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1729
1730 /* FDI must be feeding us bits for PCH ports */
1731 assert_fdi_tx_enabled(dev_priv, pipe);
1732 assert_fdi_rx_enabled(dev_priv, pipe);
1733
1734 if (HAS_PCH_CPT(dev_priv)) {
1735 /* Workaround: Set the timing override bit before enabling the
1736 * pch transcoder. */
1737 reg = TRANS_CHICKEN2(pipe);
1738 val = I915_READ(reg);
1739 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1740 I915_WRITE(reg, val);
1741 }
1742
1743 reg = PCH_TRANSCONF(pipe);
1744 val = I915_READ(reg);
1745 pipeconf_val = I915_READ(PIPECONF(pipe));
1746
1747 if (HAS_PCH_IBX(dev_priv)) {
1748 /*
1749 * Make the BPC in transcoder be consistent with
1750 * that in pipeconf reg. For HDMI we must use 8bpc
1751 * here for both 8bpc and 12bpc.
1752 */
1753 val &= ~PIPECONF_BPC_MASK;
1754 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1755 val |= PIPECONF_8BPC;
1756 else
1757 val |= pipeconf_val & PIPECONF_BPC_MASK;
1758 }
1759
1760 val &= ~TRANS_INTERLACE_MASK;
1761 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1762 if (HAS_PCH_IBX(dev_priv) &&
1763 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1764 val |= TRANS_LEGACY_INTERLACED_ILK;
1765 else
1766 val |= TRANS_INTERLACED;
1767 else
1768 val |= TRANS_PROGRESSIVE;
1769
1770 I915_WRITE(reg, val | TRANS_ENABLE);
1771 if (intel_wait_for_register(dev_priv,
1772 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1773 100))
1774 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1775 }
1776
1777 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1778 enum transcoder cpu_transcoder)
1779 {
1780 u32 val, pipeconf_val;
1781
1782 /* FDI must be feeding us bits for PCH ports */
1783 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1784 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1785
1786 /* Workaround: set timing override bit. */
1787 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1788 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1789 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1790
1791 val = TRANS_ENABLE;
1792 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1793
1794 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1795 PIPECONF_INTERLACED_ILK)
1796 val |= TRANS_INTERLACED;
1797 else
1798 val |= TRANS_PROGRESSIVE;
1799
1800 I915_WRITE(LPT_TRANSCONF, val);
1801 if (intel_wait_for_register(dev_priv,
1802 LPT_TRANSCONF,
1803 TRANS_STATE_ENABLE,
1804 TRANS_STATE_ENABLE,
1805 100))
1806 DRM_ERROR("Failed to enable PCH transcoder\n");
1807 }
1808
1809 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1810 enum pipe pipe)
1811 {
1812 i915_reg_t reg;
1813 uint32_t val;
1814
1815 /* FDI relies on the transcoder */
1816 assert_fdi_tx_disabled(dev_priv, pipe);
1817 assert_fdi_rx_disabled(dev_priv, pipe);
1818
1819 /* Ports must be off as well */
1820 assert_pch_ports_disabled(dev_priv, pipe);
1821
1822 reg = PCH_TRANSCONF(pipe);
1823 val = I915_READ(reg);
1824 val &= ~TRANS_ENABLE;
1825 I915_WRITE(reg, val);
1826 /* wait for PCH transcoder off, transcoder state */
1827 if (intel_wait_for_register(dev_priv,
1828 reg, TRANS_STATE_ENABLE, 0,
1829 50))
1830 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1831
1832 if (HAS_PCH_CPT(dev_priv)) {
1833 /* Workaround: Clear the timing override chicken bit again. */
1834 reg = TRANS_CHICKEN2(pipe);
1835 val = I915_READ(reg);
1836 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1837 I915_WRITE(reg, val);
1838 }
1839 }
1840
1841 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1842 {
1843 u32 val;
1844
1845 val = I915_READ(LPT_TRANSCONF);
1846 val &= ~TRANS_ENABLE;
1847 I915_WRITE(LPT_TRANSCONF, val);
1848 /* wait for PCH transcoder off, transcoder state */
1849 if (intel_wait_for_register(dev_priv,
1850 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1851 50))
1852 DRM_ERROR("Failed to disable PCH transcoder\n");
1853
1854 /* Workaround: clear timing override bit. */
1855 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1856 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1857 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1858 }
1859
1860 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1861 {
1862 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1863
1864 WARN_ON(!crtc->config->has_pch_encoder);
1865
1866 if (HAS_PCH_LPT(dev_priv))
1867 return TRANSCODER_A;
1868 else
1869 return (enum transcoder) crtc->pipe;
1870 }
1871
1872 /**
1873 * intel_enable_pipe - enable a pipe, asserting requirements
1874 * @crtc: crtc responsible for the pipe
1875 *
1876 * Enable @crtc's pipe, making sure that various hardware specific requirements
1877 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1878 */
1879 static void intel_enable_pipe(struct intel_crtc *crtc)
1880 {
1881 struct drm_device *dev = crtc->base.dev;
1882 struct drm_i915_private *dev_priv = to_i915(dev);
1883 enum pipe pipe = crtc->pipe;
1884 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1885 i915_reg_t reg;
1886 u32 val;
1887
1888 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1889
1890 assert_planes_disabled(dev_priv, pipe);
1891 assert_cursor_disabled(dev_priv, pipe);
1892 assert_sprites_disabled(dev_priv, pipe);
1893
1894 /*
1895 * A pipe without a PLL won't actually be able to drive bits from
1896 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1897 * need the check.
1898 */
1899 if (HAS_GMCH_DISPLAY(dev_priv)) {
1900 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1901 assert_dsi_pll_enabled(dev_priv);
1902 else
1903 assert_pll_enabled(dev_priv, pipe);
1904 } else {
1905 if (crtc->config->has_pch_encoder) {
1906 /* if driving the PCH, we need FDI enabled */
1907 assert_fdi_rx_pll_enabled(dev_priv,
1908 (enum pipe) intel_crtc_pch_transcoder(crtc));
1909 assert_fdi_tx_pll_enabled(dev_priv,
1910 (enum pipe) cpu_transcoder);
1911 }
1912 /* FIXME: assert CPU port conditions for SNB+ */
1913 }
1914
1915 reg = PIPECONF(cpu_transcoder);
1916 val = I915_READ(reg);
1917 if (val & PIPECONF_ENABLE) {
1918 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1919 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1920 return;
1921 }
1922
1923 I915_WRITE(reg, val | PIPECONF_ENABLE);
1924 POSTING_READ(reg);
1925
1926 /*
1927 * Until the pipe starts DSL will read as 0, which would cause
1928 * an apparent vblank timestamp jump, which messes up also the
1929 * frame count when it's derived from the timestamps. So let's
1930 * wait for the pipe to start properly before we call
1931 * drm_crtc_vblank_on()
1932 */
1933 if (dev->max_vblank_count == 0 &&
1934 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1935 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1936 }
1937
1938 /**
1939 * intel_disable_pipe - disable a pipe, asserting requirements
1940 * @crtc: crtc whose pipes is to be disabled
1941 *
1942 * Disable the pipe of @crtc, making sure that various hardware
1943 * specific requirements are met, if applicable, e.g. plane
1944 * disabled, panel fitter off, etc.
1945 *
1946 * Will wait until the pipe has shut down before returning.
1947 */
1948 static void intel_disable_pipe(struct intel_crtc *crtc)
1949 {
1950 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1951 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1952 enum pipe pipe = crtc->pipe;
1953 i915_reg_t reg;
1954 u32 val;
1955
1956 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1957
1958 /*
1959 * Make sure planes won't keep trying to pump pixels to us,
1960 * or we might hang the display.
1961 */
1962 assert_planes_disabled(dev_priv, pipe);
1963 assert_cursor_disabled(dev_priv, pipe);
1964 assert_sprites_disabled(dev_priv, pipe);
1965
1966 reg = PIPECONF(cpu_transcoder);
1967 val = I915_READ(reg);
1968 if ((val & PIPECONF_ENABLE) == 0)
1969 return;
1970
1971 /*
1972 * Double wide has implications for planes
1973 * so best keep it disabled when not needed.
1974 */
1975 if (crtc->config->double_wide)
1976 val &= ~PIPECONF_DOUBLE_WIDE;
1977
1978 /* Don't disable pipe or pipe PLLs if needed */
1979 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
1980 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1981 val &= ~PIPECONF_ENABLE;
1982
1983 I915_WRITE(reg, val);
1984 if ((val & PIPECONF_ENABLE) == 0)
1985 intel_wait_for_pipe_off(crtc);
1986 }
1987
1988 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1989 {
1990 return IS_GEN2(dev_priv) ? 2048 : 4096;
1991 }
1992
1993 static unsigned int
1994 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
1995 {
1996 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1997 unsigned int cpp = fb->format->cpp[plane];
1998
1999 switch (fb->modifier) {
2000 case DRM_FORMAT_MOD_NONE:
2001 return cpp;
2002 case I915_FORMAT_MOD_X_TILED:
2003 if (IS_GEN2(dev_priv))
2004 return 128;
2005 else
2006 return 512;
2007 case I915_FORMAT_MOD_Y_TILED:
2008 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2009 return 128;
2010 else
2011 return 512;
2012 case I915_FORMAT_MOD_Yf_TILED:
2013 switch (cpp) {
2014 case 1:
2015 return 64;
2016 case 2:
2017 case 4:
2018 return 128;
2019 case 8:
2020 case 16:
2021 return 256;
2022 default:
2023 MISSING_CASE(cpp);
2024 return cpp;
2025 }
2026 break;
2027 default:
2028 MISSING_CASE(fb->modifier);
2029 return cpp;
2030 }
2031 }
2032
2033 static unsigned int
2034 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2035 {
2036 if (fb->modifier == DRM_FORMAT_MOD_NONE)
2037 return 1;
2038 else
2039 return intel_tile_size(to_i915(fb->dev)) /
2040 intel_tile_width_bytes(fb, plane);
2041 }
2042
2043 /* Return the tile dimensions in pixel units */
2044 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2045 unsigned int *tile_width,
2046 unsigned int *tile_height)
2047 {
2048 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2049 unsigned int cpp = fb->format->cpp[plane];
2050
2051 *tile_width = tile_width_bytes / cpp;
2052 *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2053 }
2054
2055 unsigned int
2056 intel_fb_align_height(const struct drm_framebuffer *fb,
2057 int plane, unsigned int height)
2058 {
2059 unsigned int tile_height = intel_tile_height(fb, plane);
2060
2061 return ALIGN(height, tile_height);
2062 }
2063
2064 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2065 {
2066 unsigned int size = 0;
2067 int i;
2068
2069 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2070 size += rot_info->plane[i].width * rot_info->plane[i].height;
2071
2072 return size;
2073 }
2074
2075 static void
2076 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2077 const struct drm_framebuffer *fb,
2078 unsigned int rotation)
2079 {
2080 view->type = I915_GGTT_VIEW_NORMAL;
2081 if (drm_rotation_90_or_270(rotation)) {
2082 view->type = I915_GGTT_VIEW_ROTATED;
2083 view->rotated = to_intel_framebuffer(fb)->rot_info;
2084 }
2085 }
2086
2087 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2088 {
2089 if (INTEL_INFO(dev_priv)->gen >= 9)
2090 return 256 * 1024;
2091 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2092 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2093 return 128 * 1024;
2094 else if (INTEL_INFO(dev_priv)->gen >= 4)
2095 return 4 * 1024;
2096 else
2097 return 0;
2098 }
2099
2100 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2101 int plane)
2102 {
2103 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2104
2105 /* AUX_DIST needs only 4K alignment */
2106 if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
2107 return 4096;
2108
2109 switch (fb->modifier) {
2110 case DRM_FORMAT_MOD_NONE:
2111 return intel_linear_alignment(dev_priv);
2112 case I915_FORMAT_MOD_X_TILED:
2113 if (INTEL_GEN(dev_priv) >= 9)
2114 return 256 * 1024;
2115 return 0;
2116 case I915_FORMAT_MOD_Y_TILED:
2117 case I915_FORMAT_MOD_Yf_TILED:
2118 return 1 * 1024 * 1024;
2119 default:
2120 MISSING_CASE(fb->modifier);
2121 return 0;
2122 }
2123 }
2124
2125 struct i915_vma *
2126 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2127 {
2128 struct drm_device *dev = fb->dev;
2129 struct drm_i915_private *dev_priv = to_i915(dev);
2130 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2131 struct i915_ggtt_view view;
2132 struct i915_vma *vma;
2133 u32 alignment;
2134
2135 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2136
2137 alignment = intel_surf_alignment(fb, 0);
2138
2139 intel_fill_fb_ggtt_view(&view, fb, rotation);
2140
2141 /* Note that the w/a also requires 64 PTE of padding following the
2142 * bo. We currently fill all unused PTE with the shadow page and so
2143 * we should always have valid PTE following the scanout preventing
2144 * the VT-d warning.
2145 */
2146 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2147 alignment = 256 * 1024;
2148
2149 /*
2150 * Global gtt pte registers are special registers which actually forward
2151 * writes to a chunk of system memory. Which means that there is no risk
2152 * that the register values disappear as soon as we call
2153 * intel_runtime_pm_put(), so it is correct to wrap only the
2154 * pin/unpin/fence and not more.
2155 */
2156 intel_runtime_pm_get(dev_priv);
2157
2158 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2159 if (IS_ERR(vma))
2160 goto err;
2161
2162 if (i915_vma_is_map_and_fenceable(vma)) {
2163 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2164 * fence, whereas 965+ only requires a fence if using
2165 * framebuffer compression. For simplicity, we always, when
2166 * possible, install a fence as the cost is not that onerous.
2167 *
2168 * If we fail to fence the tiled scanout, then either the
2169 * modeset will reject the change (which is highly unlikely as
2170 * the affected systems, all but one, do not have unmappable
2171 * space) or we will not be able to enable full powersaving
2172 * techniques (also likely not to apply due to various limits
2173 * FBC and the like impose on the size of the buffer, which
2174 * presumably we violated anyway with this unmappable buffer).
2175 * Anyway, it is presumably better to stumble onwards with
2176 * something and try to run the system in a "less than optimal"
2177 * mode that matches the user configuration.
2178 */
2179 if (i915_vma_get_fence(vma) == 0)
2180 i915_vma_pin_fence(vma);
2181 }
2182
2183 i915_vma_get(vma);
2184 err:
2185 intel_runtime_pm_put(dev_priv);
2186 return vma;
2187 }
2188
2189 void intel_unpin_fb_vma(struct i915_vma *vma)
2190 {
2191 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2192
2193 i915_vma_unpin_fence(vma);
2194 i915_gem_object_unpin_from_display_plane(vma);
2195 i915_vma_put(vma);
2196 }
2197
2198 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2199 unsigned int rotation)
2200 {
2201 if (drm_rotation_90_or_270(rotation))
2202 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2203 else
2204 return fb->pitches[plane];
2205 }
2206
2207 /*
2208 * Convert the x/y offsets into a linear offset.
2209 * Only valid with 0/180 degree rotation, which is fine since linear
2210 * offset is only used with linear buffers on pre-hsw and tiled buffers
2211 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2212 */
2213 u32 intel_fb_xy_to_linear(int x, int y,
2214 const struct intel_plane_state *state,
2215 int plane)
2216 {
2217 const struct drm_framebuffer *fb = state->base.fb;
2218 unsigned int cpp = fb->format->cpp[plane];
2219 unsigned int pitch = fb->pitches[plane];
2220
2221 return y * pitch + x * cpp;
2222 }
2223
2224 /*
2225 * Add the x/y offsets derived from fb->offsets[] to the user
2226 * specified plane src x/y offsets. The resulting x/y offsets
2227 * specify the start of scanout from the beginning of the gtt mapping.
2228 */
2229 void intel_add_fb_offsets(int *x, int *y,
2230 const struct intel_plane_state *state,
2231 int plane)
2232
2233 {
2234 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2235 unsigned int rotation = state->base.rotation;
2236
2237 if (drm_rotation_90_or_270(rotation)) {
2238 *x += intel_fb->rotated[plane].x;
2239 *y += intel_fb->rotated[plane].y;
2240 } else {
2241 *x += intel_fb->normal[plane].x;
2242 *y += intel_fb->normal[plane].y;
2243 }
2244 }
2245
2246 /*
2247 * Input tile dimensions and pitch must already be
2248 * rotated to match x and y, and in pixel units.
2249 */
2250 static u32 _intel_adjust_tile_offset(int *x, int *y,
2251 unsigned int tile_width,
2252 unsigned int tile_height,
2253 unsigned int tile_size,
2254 unsigned int pitch_tiles,
2255 u32 old_offset,
2256 u32 new_offset)
2257 {
2258 unsigned int pitch_pixels = pitch_tiles * tile_width;
2259 unsigned int tiles;
2260
2261 WARN_ON(old_offset & (tile_size - 1));
2262 WARN_ON(new_offset & (tile_size - 1));
2263 WARN_ON(new_offset > old_offset);
2264
2265 tiles = (old_offset - new_offset) / tile_size;
2266
2267 *y += tiles / pitch_tiles * tile_height;
2268 *x += tiles % pitch_tiles * tile_width;
2269
2270 /* minimize x in case it got needlessly big */
2271 *y += *x / pitch_pixels * tile_height;
2272 *x %= pitch_pixels;
2273
2274 return new_offset;
2275 }
2276
2277 /*
2278 * Adjust the tile offset by moving the difference into
2279 * the x/y offsets.
2280 */
2281 static u32 intel_adjust_tile_offset(int *x, int *y,
2282 const struct intel_plane_state *state, int plane,
2283 u32 old_offset, u32 new_offset)
2284 {
2285 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2286 const struct drm_framebuffer *fb = state->base.fb;
2287 unsigned int cpp = fb->format->cpp[plane];
2288 unsigned int rotation = state->base.rotation;
2289 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2290
2291 WARN_ON(new_offset > old_offset);
2292
2293 if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2294 unsigned int tile_size, tile_width, tile_height;
2295 unsigned int pitch_tiles;
2296
2297 tile_size = intel_tile_size(dev_priv);
2298 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2299
2300 if (drm_rotation_90_or_270(rotation)) {
2301 pitch_tiles = pitch / tile_height;
2302 swap(tile_width, tile_height);
2303 } else {
2304 pitch_tiles = pitch / (tile_width * cpp);
2305 }
2306
2307 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2308 tile_size, pitch_tiles,
2309 old_offset, new_offset);
2310 } else {
2311 old_offset += *y * pitch + *x * cpp;
2312
2313 *y = (old_offset - new_offset) / pitch;
2314 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2315 }
2316
2317 return new_offset;
2318 }
2319
2320 /*
2321 * Computes the linear offset to the base tile and adjusts
2322 * x, y. bytes per pixel is assumed to be a power-of-two.
2323 *
2324 * In the 90/270 rotated case, x and y are assumed
2325 * to be already rotated to match the rotated GTT view, and
2326 * pitch is the tile_height aligned framebuffer height.
2327 *
2328 * This function is used when computing the derived information
2329 * under intel_framebuffer, so using any of that information
2330 * here is not allowed. Anything under drm_framebuffer can be
2331 * used. This is why the user has to pass in the pitch since it
2332 * is specified in the rotated orientation.
2333 */
2334 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2335 int *x, int *y,
2336 const struct drm_framebuffer *fb, int plane,
2337 unsigned int pitch,
2338 unsigned int rotation,
2339 u32 alignment)
2340 {
2341 uint64_t fb_modifier = fb->modifier;
2342 unsigned int cpp = fb->format->cpp[plane];
2343 u32 offset, offset_aligned;
2344
2345 if (alignment)
2346 alignment--;
2347
2348 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2349 unsigned int tile_size, tile_width, tile_height;
2350 unsigned int tile_rows, tiles, pitch_tiles;
2351
2352 tile_size = intel_tile_size(dev_priv);
2353 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2354
2355 if (drm_rotation_90_or_270(rotation)) {
2356 pitch_tiles = pitch / tile_height;
2357 swap(tile_width, tile_height);
2358 } else {
2359 pitch_tiles = pitch / (tile_width * cpp);
2360 }
2361
2362 tile_rows = *y / tile_height;
2363 *y %= tile_height;
2364
2365 tiles = *x / tile_width;
2366 *x %= tile_width;
2367
2368 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2369 offset_aligned = offset & ~alignment;
2370
2371 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2372 tile_size, pitch_tiles,
2373 offset, offset_aligned);
2374 } else {
2375 offset = *y * pitch + *x * cpp;
2376 offset_aligned = offset & ~alignment;
2377
2378 *y = (offset & alignment) / pitch;
2379 *x = ((offset & alignment) - *y * pitch) / cpp;
2380 }
2381
2382 return offset_aligned;
2383 }
2384
2385 u32 intel_compute_tile_offset(int *x, int *y,
2386 const struct intel_plane_state *state,
2387 int plane)
2388 {
2389 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2390 const struct drm_framebuffer *fb = state->base.fb;
2391 unsigned int rotation = state->base.rotation;
2392 int pitch = intel_fb_pitch(fb, plane, rotation);
2393 u32 alignment = intel_surf_alignment(fb, plane);
2394
2395 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2396 rotation, alignment);
2397 }
2398
2399 /* Convert the fb->offset[] linear offset into x/y offsets */
2400 static void intel_fb_offset_to_xy(int *x, int *y,
2401 const struct drm_framebuffer *fb, int plane)
2402 {
2403 unsigned int cpp = fb->format->cpp[plane];
2404 unsigned int pitch = fb->pitches[plane];
2405 u32 linear_offset = fb->offsets[plane];
2406
2407 *y = linear_offset / pitch;
2408 *x = linear_offset % pitch / cpp;
2409 }
2410
2411 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2412 {
2413 switch (fb_modifier) {
2414 case I915_FORMAT_MOD_X_TILED:
2415 return I915_TILING_X;
2416 case I915_FORMAT_MOD_Y_TILED:
2417 return I915_TILING_Y;
2418 default:
2419 return I915_TILING_NONE;
2420 }
2421 }
2422
2423 static int
2424 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2425 struct drm_framebuffer *fb)
2426 {
2427 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2428 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2429 u32 gtt_offset_rotated = 0;
2430 unsigned int max_size = 0;
2431 int i, num_planes = fb->format->num_planes;
2432 unsigned int tile_size = intel_tile_size(dev_priv);
2433
2434 for (i = 0; i < num_planes; i++) {
2435 unsigned int width, height;
2436 unsigned int cpp, size;
2437 u32 offset;
2438 int x, y;
2439
2440 cpp = fb->format->cpp[i];
2441 width = drm_framebuffer_plane_width(fb->width, fb, i);
2442 height = drm_framebuffer_plane_height(fb->height, fb, i);
2443
2444 intel_fb_offset_to_xy(&x, &y, fb, i);
2445
2446 /*
2447 * The fence (if used) is aligned to the start of the object
2448 * so having the framebuffer wrap around across the edge of the
2449 * fenced region doesn't really work. We have no API to configure
2450 * the fence start offset within the object (nor could we probably
2451 * on gen2/3). So it's just easier if we just require that the
2452 * fb layout agrees with the fence layout. We already check that the
2453 * fb stride matches the fence stride elsewhere.
2454 */
2455 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2456 (x + width) * cpp > fb->pitches[i]) {
2457 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2458 i, fb->offsets[i]);
2459 return -EINVAL;
2460 }
2461
2462 /*
2463 * First pixel of the framebuffer from
2464 * the start of the normal gtt mapping.
2465 */
2466 intel_fb->normal[i].x = x;
2467 intel_fb->normal[i].y = y;
2468
2469 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2470 fb, i, fb->pitches[i],
2471 DRM_ROTATE_0, tile_size);
2472 offset /= tile_size;
2473
2474 if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2475 unsigned int tile_width, tile_height;
2476 unsigned int pitch_tiles;
2477 struct drm_rect r;
2478
2479 intel_tile_dims(fb, i, &tile_width, &tile_height);
2480
2481 rot_info->plane[i].offset = offset;
2482 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2483 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2484 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2485
2486 intel_fb->rotated[i].pitch =
2487 rot_info->plane[i].height * tile_height;
2488
2489 /* how many tiles does this plane need */
2490 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2491 /*
2492 * If the plane isn't horizontally tile aligned,
2493 * we need one more tile.
2494 */
2495 if (x != 0)
2496 size++;
2497
2498 /* rotate the x/y offsets to match the GTT view */
2499 r.x1 = x;
2500 r.y1 = y;
2501 r.x2 = x + width;
2502 r.y2 = y + height;
2503 drm_rect_rotate(&r,
2504 rot_info->plane[i].width * tile_width,
2505 rot_info->plane[i].height * tile_height,
2506 DRM_ROTATE_270);
2507 x = r.x1;
2508 y = r.y1;
2509
2510 /* rotate the tile dimensions to match the GTT view */
2511 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2512 swap(tile_width, tile_height);
2513
2514 /*
2515 * We only keep the x/y offsets, so push all of the
2516 * gtt offset into the x/y offsets.
2517 */
2518 _intel_adjust_tile_offset(&x, &y,
2519 tile_width, tile_height,
2520 tile_size, pitch_tiles,
2521 gtt_offset_rotated * tile_size, 0);
2522
2523 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2524
2525 /*
2526 * First pixel of the framebuffer from
2527 * the start of the rotated gtt mapping.
2528 */
2529 intel_fb->rotated[i].x = x;
2530 intel_fb->rotated[i].y = y;
2531 } else {
2532 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2533 x * cpp, tile_size);
2534 }
2535
2536 /* how many tiles in total needed in the bo */
2537 max_size = max(max_size, offset + size);
2538 }
2539
2540 if (max_size * tile_size > intel_fb->obj->base.size) {
2541 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2542 max_size * tile_size, intel_fb->obj->base.size);
2543 return -EINVAL;
2544 }
2545
2546 return 0;
2547 }
2548
2549 static int i9xx_format_to_fourcc(int format)
2550 {
2551 switch (format) {
2552 case DISPPLANE_8BPP:
2553 return DRM_FORMAT_C8;
2554 case DISPPLANE_BGRX555:
2555 return DRM_FORMAT_XRGB1555;
2556 case DISPPLANE_BGRX565:
2557 return DRM_FORMAT_RGB565;
2558 default:
2559 case DISPPLANE_BGRX888:
2560 return DRM_FORMAT_XRGB8888;
2561 case DISPPLANE_RGBX888:
2562 return DRM_FORMAT_XBGR8888;
2563 case DISPPLANE_BGRX101010:
2564 return DRM_FORMAT_XRGB2101010;
2565 case DISPPLANE_RGBX101010:
2566 return DRM_FORMAT_XBGR2101010;
2567 }
2568 }
2569
2570 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2571 {
2572 switch (format) {
2573 case PLANE_CTL_FORMAT_RGB_565:
2574 return DRM_FORMAT_RGB565;
2575 default:
2576 case PLANE_CTL_FORMAT_XRGB_8888:
2577 if (rgb_order) {
2578 if (alpha)
2579 return DRM_FORMAT_ABGR8888;
2580 else
2581 return DRM_FORMAT_XBGR8888;
2582 } else {
2583 if (alpha)
2584 return DRM_FORMAT_ARGB8888;
2585 else
2586 return DRM_FORMAT_XRGB8888;
2587 }
2588 case PLANE_CTL_FORMAT_XRGB_2101010:
2589 if (rgb_order)
2590 return DRM_FORMAT_XBGR2101010;
2591 else
2592 return DRM_FORMAT_XRGB2101010;
2593 }
2594 }
2595
2596 static bool
2597 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2598 struct intel_initial_plane_config *plane_config)
2599 {
2600 struct drm_device *dev = crtc->base.dev;
2601 struct drm_i915_private *dev_priv = to_i915(dev);
2602 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2603 struct drm_i915_gem_object *obj = NULL;
2604 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2605 struct drm_framebuffer *fb = &plane_config->fb->base;
2606 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2607 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2608 PAGE_SIZE);
2609
2610 size_aligned -= base_aligned;
2611
2612 if (plane_config->size == 0)
2613 return false;
2614
2615 /* If the FB is too big, just don't use it since fbdev is not very
2616 * important and we should probably use that space with FBC or other
2617 * features. */
2618 if (size_aligned * 2 > ggtt->stolen_usable_size)
2619 return false;
2620
2621 mutex_lock(&dev->struct_mutex);
2622 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2623 base_aligned,
2624 base_aligned,
2625 size_aligned);
2626 mutex_unlock(&dev->struct_mutex);
2627 if (!obj)
2628 return false;
2629
2630 if (plane_config->tiling == I915_TILING_X)
2631 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2632
2633 mode_cmd.pixel_format = fb->format->format;
2634 mode_cmd.width = fb->width;
2635 mode_cmd.height = fb->height;
2636 mode_cmd.pitches[0] = fb->pitches[0];
2637 mode_cmd.modifier[0] = fb->modifier;
2638 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2639
2640 if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2641 DRM_DEBUG_KMS("intel fb init failed\n");
2642 goto out_unref_obj;
2643 }
2644
2645
2646 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2647 return true;
2648
2649 out_unref_obj:
2650 i915_gem_object_put(obj);
2651 return false;
2652 }
2653
2654 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2655 static void
2656 update_state_fb(struct drm_plane *plane)
2657 {
2658 if (plane->fb == plane->state->fb)
2659 return;
2660
2661 if (plane->state->fb)
2662 drm_framebuffer_unreference(plane->state->fb);
2663 plane->state->fb = plane->fb;
2664 if (plane->state->fb)
2665 drm_framebuffer_reference(plane->state->fb);
2666 }
2667
2668 static void
2669 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2670 struct intel_plane_state *plane_state,
2671 bool visible)
2672 {
2673 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2674
2675 plane_state->base.visible = visible;
2676
2677 /* FIXME pre-g4x don't work like this */
2678 if (visible) {
2679 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2680 crtc_state->active_planes |= BIT(plane->id);
2681 } else {
2682 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2683 crtc_state->active_planes &= ~BIT(plane->id);
2684 }
2685
2686 DRM_DEBUG_KMS("%s active planes 0x%x\n",
2687 crtc_state->base.crtc->name,
2688 crtc_state->active_planes);
2689 }
2690
2691 static void
2692 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2693 struct intel_initial_plane_config *plane_config)
2694 {
2695 struct drm_device *dev = intel_crtc->base.dev;
2696 struct drm_i915_private *dev_priv = to_i915(dev);
2697 struct drm_crtc *c;
2698 struct drm_i915_gem_object *obj;
2699 struct drm_plane *primary = intel_crtc->base.primary;
2700 struct drm_plane_state *plane_state = primary->state;
2701 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2702 struct intel_plane *intel_plane = to_intel_plane(primary);
2703 struct intel_plane_state *intel_state =
2704 to_intel_plane_state(plane_state);
2705 struct drm_framebuffer *fb;
2706
2707 if (!plane_config->fb)
2708 return;
2709
2710 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2711 fb = &plane_config->fb->base;
2712 goto valid_fb;
2713 }
2714
2715 kfree(plane_config->fb);
2716
2717 /*
2718 * Failed to alloc the obj, check to see if we should share
2719 * an fb with another CRTC instead
2720 */
2721 for_each_crtc(dev, c) {
2722 struct intel_plane_state *state;
2723
2724 if (c == &intel_crtc->base)
2725 continue;
2726
2727 if (!to_intel_crtc(c)->active)
2728 continue;
2729
2730 state = to_intel_plane_state(c->primary->state);
2731 if (!state->vma)
2732 continue;
2733
2734 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2735 fb = c->primary->fb;
2736 drm_framebuffer_reference(fb);
2737 goto valid_fb;
2738 }
2739 }
2740
2741 /*
2742 * We've failed to reconstruct the BIOS FB. Current display state
2743 * indicates that the primary plane is visible, but has a NULL FB,
2744 * which will lead to problems later if we don't fix it up. The
2745 * simplest solution is to just disable the primary plane now and
2746 * pretend the BIOS never had it enabled.
2747 */
2748 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2749 to_intel_plane_state(plane_state),
2750 false);
2751 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2752 trace_intel_disable_plane(primary, intel_crtc);
2753 intel_plane->disable_plane(primary, &intel_crtc->base);
2754
2755 return;
2756
2757 valid_fb:
2758 mutex_lock(&dev->struct_mutex);
2759 intel_state->vma =
2760 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2761 mutex_unlock(&dev->struct_mutex);
2762 if (IS_ERR(intel_state->vma)) {
2763 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2764 intel_crtc->pipe, PTR_ERR(intel_state->vma));
2765
2766 intel_state->vma = NULL;
2767 drm_framebuffer_unreference(fb);
2768 return;
2769 }
2770
2771 plane_state->src_x = 0;
2772 plane_state->src_y = 0;
2773 plane_state->src_w = fb->width << 16;
2774 plane_state->src_h = fb->height << 16;
2775
2776 plane_state->crtc_x = 0;
2777 plane_state->crtc_y = 0;
2778 plane_state->crtc_w = fb->width;
2779 plane_state->crtc_h = fb->height;
2780
2781 intel_state->base.src = drm_plane_state_src(plane_state);
2782 intel_state->base.dst = drm_plane_state_dest(plane_state);
2783
2784 obj = intel_fb_obj(fb);
2785 if (i915_gem_object_is_tiled(obj))
2786 dev_priv->preserve_bios_swizzle = true;
2787
2788 drm_framebuffer_reference(fb);
2789 primary->fb = primary->state->fb = fb;
2790 primary->crtc = primary->state->crtc = &intel_crtc->base;
2791
2792 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2793 to_intel_plane_state(plane_state),
2794 true);
2795
2796 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2797 &obj->frontbuffer_bits);
2798 }
2799
2800 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2801 unsigned int rotation)
2802 {
2803 int cpp = fb->format->cpp[plane];
2804
2805 switch (fb->modifier) {
2806 case DRM_FORMAT_MOD_NONE:
2807 case I915_FORMAT_MOD_X_TILED:
2808 switch (cpp) {
2809 case 8:
2810 return 4096;
2811 case 4:
2812 case 2:
2813 case 1:
2814 return 8192;
2815 default:
2816 MISSING_CASE(cpp);
2817 break;
2818 }
2819 break;
2820 case I915_FORMAT_MOD_Y_TILED:
2821 case I915_FORMAT_MOD_Yf_TILED:
2822 switch (cpp) {
2823 case 8:
2824 return 2048;
2825 case 4:
2826 return 4096;
2827 case 2:
2828 case 1:
2829 return 8192;
2830 default:
2831 MISSING_CASE(cpp);
2832 break;
2833 }
2834 break;
2835 default:
2836 MISSING_CASE(fb->modifier);
2837 }
2838
2839 return 2048;
2840 }
2841
2842 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2843 {
2844 const struct drm_framebuffer *fb = plane_state->base.fb;
2845 unsigned int rotation = plane_state->base.rotation;
2846 int x = plane_state->base.src.x1 >> 16;
2847 int y = plane_state->base.src.y1 >> 16;
2848 int w = drm_rect_width(&plane_state->base.src) >> 16;
2849 int h = drm_rect_height(&plane_state->base.src) >> 16;
2850 int max_width = skl_max_plane_width(fb, 0, rotation);
2851 int max_height = 4096;
2852 u32 alignment, offset, aux_offset = plane_state->aux.offset;
2853
2854 if (w > max_width || h > max_height) {
2855 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2856 w, h, max_width, max_height);
2857 return -EINVAL;
2858 }
2859
2860 intel_add_fb_offsets(&x, &y, plane_state, 0);
2861 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2862 alignment = intel_surf_alignment(fb, 0);
2863
2864 /*
2865 * AUX surface offset is specified as the distance from the
2866 * main surface offset, and it must be non-negative. Make
2867 * sure that is what we will get.
2868 */
2869 if (offset > aux_offset)
2870 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2871 offset, aux_offset & ~(alignment - 1));
2872
2873 /*
2874 * When using an X-tiled surface, the plane blows up
2875 * if the x offset + width exceed the stride.
2876 *
2877 * TODO: linear and Y-tiled seem fine, Yf untested,
2878 */
2879 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2880 int cpp = fb->format->cpp[0];
2881
2882 while ((x + w) * cpp > fb->pitches[0]) {
2883 if (offset == 0) {
2884 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2885 return -EINVAL;
2886 }
2887
2888 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2889 offset, offset - alignment);
2890 }
2891 }
2892
2893 plane_state->main.offset = offset;
2894 plane_state->main.x = x;
2895 plane_state->main.y = y;
2896
2897 return 0;
2898 }
2899
2900 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2901 {
2902 const struct drm_framebuffer *fb = plane_state->base.fb;
2903 unsigned int rotation = plane_state->base.rotation;
2904 int max_width = skl_max_plane_width(fb, 1, rotation);
2905 int max_height = 4096;
2906 int x = plane_state->base.src.x1 >> 17;
2907 int y = plane_state->base.src.y1 >> 17;
2908 int w = drm_rect_width(&plane_state->base.src) >> 17;
2909 int h = drm_rect_height(&plane_state->base.src) >> 17;
2910 u32 offset;
2911
2912 intel_add_fb_offsets(&x, &y, plane_state, 1);
2913 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2914
2915 /* FIXME not quite sure how/if these apply to the chroma plane */
2916 if (w > max_width || h > max_height) {
2917 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2918 w, h, max_width, max_height);
2919 return -EINVAL;
2920 }
2921
2922 plane_state->aux.offset = offset;
2923 plane_state->aux.x = x;
2924 plane_state->aux.y = y;
2925
2926 return 0;
2927 }
2928
2929 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2930 {
2931 const struct drm_framebuffer *fb = plane_state->base.fb;
2932 unsigned int rotation = plane_state->base.rotation;
2933 int ret;
2934
2935 if (!plane_state->base.visible)
2936 return 0;
2937
2938 /* Rotate src coordinates to match rotated GTT view */
2939 if (drm_rotation_90_or_270(rotation))
2940 drm_rect_rotate(&plane_state->base.src,
2941 fb->width << 16, fb->height << 16,
2942 DRM_ROTATE_270);
2943
2944 /*
2945 * Handle the AUX surface first since
2946 * the main surface setup depends on it.
2947 */
2948 if (fb->format->format == DRM_FORMAT_NV12) {
2949 ret = skl_check_nv12_aux_surface(plane_state);
2950 if (ret)
2951 return ret;
2952 } else {
2953 plane_state->aux.offset = ~0xfff;
2954 plane_state->aux.x = 0;
2955 plane_state->aux.y = 0;
2956 }
2957
2958 ret = skl_check_main_surface(plane_state);
2959 if (ret)
2960 return ret;
2961
2962 return 0;
2963 }
2964
2965 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
2966 const struct intel_plane_state *plane_state)
2967 {
2968 struct drm_i915_private *dev_priv =
2969 to_i915(plane_state->base.plane->dev);
2970 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2971 const struct drm_framebuffer *fb = plane_state->base.fb;
2972 unsigned int rotation = plane_state->base.rotation;
2973 u32 dspcntr;
2974
2975 dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
2976
2977 if (IS_G4X(dev_priv))
2978 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2979
2980 if (INTEL_GEN(dev_priv) < 4) {
2981 if (crtc->pipe == PIPE_B)
2982 dspcntr |= DISPPLANE_SEL_PIPE_B;
2983 }
2984
2985 switch (fb->format->format) {
2986 case DRM_FORMAT_C8:
2987 dspcntr |= DISPPLANE_8BPP;
2988 break;
2989 case DRM_FORMAT_XRGB1555:
2990 dspcntr |= DISPPLANE_BGRX555;
2991 break;
2992 case DRM_FORMAT_RGB565:
2993 dspcntr |= DISPPLANE_BGRX565;
2994 break;
2995 case DRM_FORMAT_XRGB8888:
2996 dspcntr |= DISPPLANE_BGRX888;
2997 break;
2998 case DRM_FORMAT_XBGR8888:
2999 dspcntr |= DISPPLANE_RGBX888;
3000 break;
3001 case DRM_FORMAT_XRGB2101010:
3002 dspcntr |= DISPPLANE_BGRX101010;
3003 break;
3004 case DRM_FORMAT_XBGR2101010:
3005 dspcntr |= DISPPLANE_RGBX101010;
3006 break;
3007 default:
3008 MISSING_CASE(fb->format->format);
3009 return 0;
3010 }
3011
3012 if (INTEL_GEN(dev_priv) >= 4 &&
3013 fb->modifier == I915_FORMAT_MOD_X_TILED)
3014 dspcntr |= DISPPLANE_TILED;
3015
3016 if (rotation & DRM_ROTATE_180)
3017 dspcntr |= DISPPLANE_ROTATE_180;
3018
3019 if (rotation & DRM_REFLECT_X)
3020 dspcntr |= DISPPLANE_MIRROR;
3021
3022 return dspcntr;
3023 }
3024
3025 static void i9xx_update_primary_plane(struct drm_plane *primary,
3026 const struct intel_crtc_state *crtc_state,
3027 const struct intel_plane_state *plane_state)
3028 {
3029 struct drm_i915_private *dev_priv = to_i915(primary->dev);
3030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3031 struct drm_framebuffer *fb = plane_state->base.fb;
3032 int plane = intel_crtc->plane;
3033 u32 linear_offset;
3034 u32 dspcntr;
3035 i915_reg_t reg = DSPCNTR(plane);
3036 unsigned int rotation = plane_state->base.rotation;
3037 int x = plane_state->base.src.x1 >> 16;
3038 int y = plane_state->base.src.y1 >> 16;
3039 unsigned long irqflags;
3040
3041 dspcntr = i9xx_plane_ctl(crtc_state, plane_state);
3042
3043 intel_add_fb_offsets(&x, &y, plane_state, 0);
3044
3045 if (INTEL_GEN(dev_priv) >= 4)
3046 intel_crtc->dspaddr_offset =
3047 intel_compute_tile_offset(&x, &y, plane_state, 0);
3048
3049 if (rotation & DRM_ROTATE_180) {
3050 x += crtc_state->pipe_src_w - 1;
3051 y += crtc_state->pipe_src_h - 1;
3052 } else if (rotation & DRM_REFLECT_X) {
3053 x += crtc_state->pipe_src_w - 1;
3054 }
3055
3056 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3057
3058 if (INTEL_GEN(dev_priv) < 4)
3059 intel_crtc->dspaddr_offset = linear_offset;
3060
3061 intel_crtc->adjusted_x = x;
3062 intel_crtc->adjusted_y = y;
3063
3064 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3065
3066 if (INTEL_GEN(dev_priv) < 4) {
3067 /* pipesrc and dspsize control the size that is scaled from,
3068 * which should always be the user's requested size.
3069 */
3070 I915_WRITE_FW(DSPSIZE(plane),
3071 ((crtc_state->pipe_src_h - 1) << 16) |
3072 (crtc_state->pipe_src_w - 1));
3073 I915_WRITE_FW(DSPPOS(plane), 0);
3074 } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3075 I915_WRITE_FW(PRIMSIZE(plane),
3076 ((crtc_state->pipe_src_h - 1) << 16) |
3077 (crtc_state->pipe_src_w - 1));
3078 I915_WRITE_FW(PRIMPOS(plane), 0);
3079 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3080 }
3081
3082 I915_WRITE_FW(reg, dspcntr);
3083
3084 I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3085 if (INTEL_GEN(dev_priv) >= 4) {
3086 I915_WRITE_FW(DSPSURF(plane),
3087 intel_plane_ggtt_offset(plane_state) +
3088 intel_crtc->dspaddr_offset);
3089 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3090 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3091 } else {
3092 I915_WRITE_FW(DSPADDR(plane),
3093 intel_plane_ggtt_offset(plane_state) +
3094 intel_crtc->dspaddr_offset);
3095 }
3096 POSTING_READ_FW(reg);
3097
3098 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3099 }
3100
3101 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3102 struct drm_crtc *crtc)
3103 {
3104 struct drm_device *dev = crtc->dev;
3105 struct drm_i915_private *dev_priv = to_i915(dev);
3106 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3107 int plane = intel_crtc->plane;
3108 unsigned long irqflags;
3109
3110 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3111
3112 I915_WRITE_FW(DSPCNTR(plane), 0);
3113 if (INTEL_INFO(dev_priv)->gen >= 4)
3114 I915_WRITE_FW(DSPSURF(plane), 0);
3115 else
3116 I915_WRITE_FW(DSPADDR(plane), 0);
3117 POSTING_READ_FW(DSPCNTR(plane));
3118
3119 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3120 }
3121
3122 static u32 ironlake_plane_ctl(const struct intel_crtc_state *crtc_state,
3123 const struct intel_plane_state *plane_state)
3124 {
3125 struct drm_i915_private *dev_priv =
3126 to_i915(plane_state->base.plane->dev);
3127 const struct drm_framebuffer *fb = plane_state->base.fb;
3128 unsigned int rotation = plane_state->base.rotation;
3129 u32 dspcntr;
3130
3131 dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
3132
3133 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv))
3134 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3135
3136 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3137 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3138
3139 switch (fb->format->format) {
3140 case DRM_FORMAT_C8:
3141 dspcntr |= DISPPLANE_8BPP;
3142 break;
3143 case DRM_FORMAT_RGB565:
3144 dspcntr |= DISPPLANE_BGRX565;
3145 break;
3146 case DRM_FORMAT_XRGB8888:
3147 dspcntr |= DISPPLANE_BGRX888;
3148 break;
3149 case DRM_FORMAT_XBGR8888:
3150 dspcntr |= DISPPLANE_RGBX888;
3151 break;
3152 case DRM_FORMAT_XRGB2101010:
3153 dspcntr |= DISPPLANE_BGRX101010;
3154 break;
3155 case DRM_FORMAT_XBGR2101010:
3156 dspcntr |= DISPPLANE_RGBX101010;
3157 break;
3158 default:
3159 MISSING_CASE(fb->format->format);
3160 return 0;
3161 }
3162
3163 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
3164 dspcntr |= DISPPLANE_TILED;
3165
3166 if (rotation & DRM_ROTATE_180)
3167 dspcntr |= DISPPLANE_ROTATE_180;
3168
3169 return dspcntr;
3170 }
3171
3172 static void ironlake_update_primary_plane(struct drm_plane *primary,
3173 const struct intel_crtc_state *crtc_state,
3174 const struct intel_plane_state *plane_state)
3175 {
3176 struct drm_device *dev = primary->dev;
3177 struct drm_i915_private *dev_priv = to_i915(dev);
3178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3179 struct drm_framebuffer *fb = plane_state->base.fb;
3180 int plane = intel_crtc->plane;
3181 u32 linear_offset;
3182 u32 dspcntr;
3183 i915_reg_t reg = DSPCNTR(plane);
3184 unsigned int rotation = plane_state->base.rotation;
3185 int x = plane_state->base.src.x1 >> 16;
3186 int y = plane_state->base.src.y1 >> 16;
3187 unsigned long irqflags;
3188
3189 dspcntr = ironlake_plane_ctl(crtc_state, plane_state);
3190
3191 intel_add_fb_offsets(&x, &y, plane_state, 0);
3192
3193 intel_crtc->dspaddr_offset =
3194 intel_compute_tile_offset(&x, &y, plane_state, 0);
3195
3196 /* HSW+ does this automagically in hardware */
3197 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) &&
3198 rotation & DRM_ROTATE_180) {
3199 x += crtc_state->pipe_src_w - 1;
3200 y += crtc_state->pipe_src_h - 1;
3201 }
3202
3203 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3204
3205 intel_crtc->adjusted_x = x;
3206 intel_crtc->adjusted_y = y;
3207
3208 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3209
3210 I915_WRITE_FW(reg, dspcntr);
3211
3212 I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3213 I915_WRITE_FW(DSPSURF(plane),
3214 intel_plane_ggtt_offset(plane_state) +
3215 intel_crtc->dspaddr_offset);
3216 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3217 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3218 } else {
3219 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3220 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3221 }
3222 POSTING_READ_FW(reg);
3223
3224 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3225 }
3226
3227 static u32
3228 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3229 {
3230 if (fb->modifier == DRM_FORMAT_MOD_NONE)
3231 return 64;
3232 else
3233 return intel_tile_width_bytes(fb, plane);
3234 }
3235
3236 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3237 {
3238 struct drm_device *dev = intel_crtc->base.dev;
3239 struct drm_i915_private *dev_priv = to_i915(dev);
3240
3241 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3242 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3243 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3244 }
3245
3246 /*
3247 * This function detaches (aka. unbinds) unused scalers in hardware
3248 */
3249 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3250 {
3251 struct intel_crtc_scaler_state *scaler_state;
3252 int i;
3253
3254 scaler_state = &intel_crtc->config->scaler_state;
3255
3256 /* loop through and disable scalers that aren't in use */
3257 for (i = 0; i < intel_crtc->num_scalers; i++) {
3258 if (!scaler_state->scalers[i].in_use)
3259 skl_detach_scaler(intel_crtc, i);
3260 }
3261 }
3262
3263 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3264 unsigned int rotation)
3265 {
3266 u32 stride;
3267
3268 if (plane >= fb->format->num_planes)
3269 return 0;
3270
3271 stride = intel_fb_pitch(fb, plane, rotation);
3272
3273 /*
3274 * The stride is either expressed as a multiple of 64 bytes chunks for
3275 * linear buffers or in number of tiles for tiled buffers.
3276 */
3277 if (drm_rotation_90_or_270(rotation))
3278 stride /= intel_tile_height(fb, plane);
3279 else
3280 stride /= intel_fb_stride_alignment(fb, plane);
3281
3282 return stride;
3283 }
3284
3285 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3286 {
3287 switch (pixel_format) {
3288 case DRM_FORMAT_C8:
3289 return PLANE_CTL_FORMAT_INDEXED;
3290 case DRM_FORMAT_RGB565:
3291 return PLANE_CTL_FORMAT_RGB_565;
3292 case DRM_FORMAT_XBGR8888:
3293 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3294 case DRM_FORMAT_XRGB8888:
3295 return PLANE_CTL_FORMAT_XRGB_8888;
3296 /*
3297 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3298 * to be already pre-multiplied. We need to add a knob (or a different
3299 * DRM_FORMAT) for user-space to configure that.
3300 */
3301 case DRM_FORMAT_ABGR8888:
3302 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3303 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3304 case DRM_FORMAT_ARGB8888:
3305 return PLANE_CTL_FORMAT_XRGB_8888 |
3306 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3307 case DRM_FORMAT_XRGB2101010:
3308 return PLANE_CTL_FORMAT_XRGB_2101010;
3309 case DRM_FORMAT_XBGR2101010:
3310 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3311 case DRM_FORMAT_YUYV:
3312 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3313 case DRM_FORMAT_YVYU:
3314 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3315 case DRM_FORMAT_UYVY:
3316 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3317 case DRM_FORMAT_VYUY:
3318 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3319 default:
3320 MISSING_CASE(pixel_format);
3321 }
3322
3323 return 0;
3324 }
3325
3326 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3327 {
3328 switch (fb_modifier) {
3329 case DRM_FORMAT_MOD_NONE:
3330 break;
3331 case I915_FORMAT_MOD_X_TILED:
3332 return PLANE_CTL_TILED_X;
3333 case I915_FORMAT_MOD_Y_TILED:
3334 return PLANE_CTL_TILED_Y;
3335 case I915_FORMAT_MOD_Yf_TILED:
3336 return PLANE_CTL_TILED_YF;
3337 default:
3338 MISSING_CASE(fb_modifier);
3339 }
3340
3341 return 0;
3342 }
3343
3344 static u32 skl_plane_ctl_rotation(unsigned int rotation)
3345 {
3346 switch (rotation) {
3347 case DRM_ROTATE_0:
3348 break;
3349 /*
3350 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3351 * while i915 HW rotation is clockwise, thats why this swapping.
3352 */
3353 case DRM_ROTATE_90:
3354 return PLANE_CTL_ROTATE_270;
3355 case DRM_ROTATE_180:
3356 return PLANE_CTL_ROTATE_180;
3357 case DRM_ROTATE_270:
3358 return PLANE_CTL_ROTATE_90;
3359 default:
3360 MISSING_CASE(rotation);
3361 }
3362
3363 return 0;
3364 }
3365
3366 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3367 const struct intel_plane_state *plane_state)
3368 {
3369 struct drm_i915_private *dev_priv =
3370 to_i915(plane_state->base.plane->dev);
3371 const struct drm_framebuffer *fb = plane_state->base.fb;
3372 unsigned int rotation = plane_state->base.rotation;
3373 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3374 u32 plane_ctl;
3375
3376 plane_ctl = PLANE_CTL_ENABLE;
3377
3378 if (!IS_GEMINILAKE(dev_priv)) {
3379 plane_ctl |=
3380 PLANE_CTL_PIPE_GAMMA_ENABLE |
3381 PLANE_CTL_PIPE_CSC_ENABLE |
3382 PLANE_CTL_PLANE_GAMMA_DISABLE;
3383 }
3384
3385 plane_ctl |= skl_plane_ctl_format(fb->format->format);
3386 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3387 plane_ctl |= skl_plane_ctl_rotation(rotation);
3388
3389 if (key->flags & I915_SET_COLORKEY_DESTINATION)
3390 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3391 else if (key->flags & I915_SET_COLORKEY_SOURCE)
3392 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3393
3394 return plane_ctl;
3395 }
3396
3397 static void skylake_update_primary_plane(struct drm_plane *plane,
3398 const struct intel_crtc_state *crtc_state,
3399 const struct intel_plane_state *plane_state)
3400 {
3401 struct drm_device *dev = plane->dev;
3402 struct drm_i915_private *dev_priv = to_i915(dev);
3403 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3404 struct drm_framebuffer *fb = plane_state->base.fb;
3405 enum plane_id plane_id = to_intel_plane(plane)->id;
3406 enum pipe pipe = to_intel_plane(plane)->pipe;
3407 u32 plane_ctl;
3408 unsigned int rotation = plane_state->base.rotation;
3409 u32 stride = skl_plane_stride(fb, 0, rotation);
3410 u32 surf_addr = plane_state->main.offset;
3411 int scaler_id = plane_state->scaler_id;
3412 int src_x = plane_state->main.x;
3413 int src_y = plane_state->main.y;
3414 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3415 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3416 int dst_x = plane_state->base.dst.x1;
3417 int dst_y = plane_state->base.dst.y1;
3418 int dst_w = drm_rect_width(&plane_state->base.dst);
3419 int dst_h = drm_rect_height(&plane_state->base.dst);
3420 unsigned long irqflags;
3421
3422 plane_ctl = skl_plane_ctl(crtc_state, plane_state);
3423
3424 /* Sizes are 0 based */
3425 src_w--;
3426 src_h--;
3427 dst_w--;
3428 dst_h--;
3429
3430 intel_crtc->dspaddr_offset = surf_addr;
3431
3432 intel_crtc->adjusted_x = src_x;
3433 intel_crtc->adjusted_y = src_y;
3434
3435 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3436
3437 if (IS_GEMINILAKE(dev_priv)) {
3438 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
3439 PLANE_COLOR_PIPE_GAMMA_ENABLE |
3440 PLANE_COLOR_PIPE_CSC_ENABLE |
3441 PLANE_COLOR_PLANE_GAMMA_DISABLE);
3442 }
3443
3444 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
3445 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3446 I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
3447 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3448
3449 if (scaler_id >= 0) {
3450 uint32_t ps_ctrl = 0;
3451
3452 WARN_ON(!dst_w || !dst_h);
3453 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3454 crtc_state->scaler_state.scalers[scaler_id].mode;
3455 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3456 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3457 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3458 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3459 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
3460 } else {
3461 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3462 }
3463
3464 I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
3465 intel_plane_ggtt_offset(plane_state) + surf_addr);
3466
3467 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3468
3469 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3470 }
3471
3472 static void skylake_disable_primary_plane(struct drm_plane *primary,
3473 struct drm_crtc *crtc)
3474 {
3475 struct drm_device *dev = crtc->dev;
3476 struct drm_i915_private *dev_priv = to_i915(dev);
3477 enum plane_id plane_id = to_intel_plane(primary)->id;
3478 enum pipe pipe = to_intel_plane(primary)->pipe;
3479 unsigned long irqflags;
3480
3481 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3482
3483 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
3484 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
3485 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3486
3487 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3488 }
3489
3490 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3491 static int
3492 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3493 int x, int y, enum mode_set_atomic state)
3494 {
3495 /* Support for kgdboc is disabled, this needs a major rework. */
3496 DRM_ERROR("legacy panic handler not supported any more.\n");
3497
3498 return -ENODEV;
3499 }
3500
3501 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3502 {
3503 struct intel_crtc *crtc;
3504
3505 for_each_intel_crtc(&dev_priv->drm, crtc)
3506 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3507 }
3508
3509 static void intel_update_primary_planes(struct drm_device *dev)
3510 {
3511 struct drm_crtc *crtc;
3512
3513 for_each_crtc(dev, crtc) {
3514 struct intel_plane *plane = to_intel_plane(crtc->primary);
3515 struct intel_plane_state *plane_state =
3516 to_intel_plane_state(plane->base.state);
3517
3518 if (plane_state->base.visible) {
3519 trace_intel_update_plane(&plane->base,
3520 to_intel_crtc(crtc));
3521
3522 plane->update_plane(&plane->base,
3523 to_intel_crtc_state(crtc->state),
3524 plane_state);
3525 }
3526 }
3527 }
3528
3529 static int
3530 __intel_display_resume(struct drm_device *dev,
3531 struct drm_atomic_state *state,
3532 struct drm_modeset_acquire_ctx *ctx)
3533 {
3534 struct drm_crtc_state *crtc_state;
3535 struct drm_crtc *crtc;
3536 int i, ret;
3537
3538 intel_modeset_setup_hw_state(dev);
3539 i915_redisable_vga(to_i915(dev));
3540
3541 if (!state)
3542 return 0;
3543
3544 /*
3545 * We've duplicated the state, pointers to the old state are invalid.
3546 *
3547 * Don't attempt to use the old state until we commit the duplicated state.
3548 */
3549 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3550 /*
3551 * Force recalculation even if we restore
3552 * current state. With fast modeset this may not result
3553 * in a modeset when the state is compatible.
3554 */
3555 crtc_state->mode_changed = true;
3556 }
3557
3558 /* ignore any reset values/BIOS leftovers in the WM registers */
3559 if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3560 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3561
3562 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3563
3564 WARN_ON(ret == -EDEADLK);
3565 return ret;
3566 }
3567
3568 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3569 {
3570 return intel_has_gpu_reset(dev_priv) &&
3571 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3572 }
3573
3574 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3575 {
3576 struct drm_device *dev = &dev_priv->drm;
3577 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3578 struct drm_atomic_state *state;
3579 int ret;
3580
3581 /*
3582 * Need mode_config.mutex so that we don't
3583 * trample ongoing ->detect() and whatnot.
3584 */
3585 mutex_lock(&dev->mode_config.mutex);
3586 drm_modeset_acquire_init(ctx, 0);
3587 while (1) {
3588 ret = drm_modeset_lock_all_ctx(dev, ctx);
3589 if (ret != -EDEADLK)
3590 break;
3591
3592 drm_modeset_backoff(ctx);
3593 }
3594
3595 /* reset doesn't touch the display, but flips might get nuked anyway, */
3596 if (!i915.force_reset_modeset_test &&
3597 !gpu_reset_clobbers_display(dev_priv))
3598 return;
3599
3600 /*
3601 * Disabling the crtcs gracefully seems nicer. Also the
3602 * g33 docs say we should at least disable all the planes.
3603 */
3604 state = drm_atomic_helper_duplicate_state(dev, ctx);
3605 if (IS_ERR(state)) {
3606 ret = PTR_ERR(state);
3607 DRM_ERROR("Duplicating state failed with %i\n", ret);
3608 return;
3609 }
3610
3611 ret = drm_atomic_helper_disable_all(dev, ctx);
3612 if (ret) {
3613 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3614 drm_atomic_state_put(state);
3615 return;
3616 }
3617
3618 dev_priv->modeset_restore_state = state;
3619 state->acquire_ctx = ctx;
3620 }
3621
3622 void intel_finish_reset(struct drm_i915_private *dev_priv)
3623 {
3624 struct drm_device *dev = &dev_priv->drm;
3625 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3626 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3627 int ret;
3628
3629 /*
3630 * Flips in the rings will be nuked by the reset,
3631 * so complete all pending flips so that user space
3632 * will get its events and not get stuck.
3633 */
3634 intel_complete_page_flips(dev_priv);
3635
3636 dev_priv->modeset_restore_state = NULL;
3637
3638 /* reset doesn't touch the display */
3639 if (!gpu_reset_clobbers_display(dev_priv)) {
3640 if (!state) {
3641 /*
3642 * Flips in the rings have been nuked by the reset,
3643 * so update the base address of all primary
3644 * planes to the the last fb to make sure we're
3645 * showing the correct fb after a reset.
3646 *
3647 * FIXME: Atomic will make this obsolete since we won't schedule
3648 * CS-based flips (which might get lost in gpu resets) any more.
3649 */
3650 intel_update_primary_planes(dev);
3651 } else {
3652 ret = __intel_display_resume(dev, state, ctx);
3653 if (ret)
3654 DRM_ERROR("Restoring old state failed with %i\n", ret);
3655 }
3656 } else {
3657 /*
3658 * The display has been reset as well,
3659 * so need a full re-initialization.
3660 */
3661 intel_runtime_pm_disable_interrupts(dev_priv);
3662 intel_runtime_pm_enable_interrupts(dev_priv);
3663
3664 intel_pps_unlock_regs_wa(dev_priv);
3665 intel_modeset_init_hw(dev);
3666
3667 spin_lock_irq(&dev_priv->irq_lock);
3668 if (dev_priv->display.hpd_irq_setup)
3669 dev_priv->display.hpd_irq_setup(dev_priv);
3670 spin_unlock_irq(&dev_priv->irq_lock);
3671
3672 ret = __intel_display_resume(dev, state, ctx);
3673 if (ret)
3674 DRM_ERROR("Restoring old state failed with %i\n", ret);
3675
3676 intel_hpd_init(dev_priv);
3677 }
3678
3679 if (state)
3680 drm_atomic_state_put(state);
3681 drm_modeset_drop_locks(ctx);
3682 drm_modeset_acquire_fini(ctx);
3683 mutex_unlock(&dev->mode_config.mutex);
3684 }
3685
3686 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3687 {
3688 struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3689
3690 if (i915_reset_backoff(error))
3691 return true;
3692
3693 if (crtc->reset_count != i915_reset_count(error))
3694 return true;
3695
3696 return false;
3697 }
3698
3699 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3700 {
3701 struct drm_device *dev = crtc->dev;
3702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3703 bool pending;
3704
3705 if (abort_flip_on_reset(intel_crtc))
3706 return false;
3707
3708 spin_lock_irq(&dev->event_lock);
3709 pending = to_intel_crtc(crtc)->flip_work != NULL;
3710 spin_unlock_irq(&dev->event_lock);
3711
3712 return pending;
3713 }
3714
3715 static void intel_update_pipe_config(struct intel_crtc *crtc,
3716 struct intel_crtc_state *old_crtc_state)
3717 {
3718 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3719 struct intel_crtc_state *pipe_config =
3720 to_intel_crtc_state(crtc->base.state);
3721
3722 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3723 crtc->base.mode = crtc->base.state->mode;
3724
3725 /*
3726 * Update pipe size and adjust fitter if needed: the reason for this is
3727 * that in compute_mode_changes we check the native mode (not the pfit
3728 * mode) to see if we can flip rather than do a full mode set. In the
3729 * fastboot case, we'll flip, but if we don't update the pipesrc and
3730 * pfit state, we'll end up with a big fb scanned out into the wrong
3731 * sized surface.
3732 */
3733
3734 I915_WRITE(PIPESRC(crtc->pipe),
3735 ((pipe_config->pipe_src_w - 1) << 16) |
3736 (pipe_config->pipe_src_h - 1));
3737
3738 /* on skylake this is done by detaching scalers */
3739 if (INTEL_GEN(dev_priv) >= 9) {
3740 skl_detach_scalers(crtc);
3741
3742 if (pipe_config->pch_pfit.enabled)
3743 skylake_pfit_enable(crtc);
3744 } else if (HAS_PCH_SPLIT(dev_priv)) {
3745 if (pipe_config->pch_pfit.enabled)
3746 ironlake_pfit_enable(crtc);
3747 else if (old_crtc_state->pch_pfit.enabled)
3748 ironlake_pfit_disable(crtc, true);
3749 }
3750 }
3751
3752 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3753 {
3754 struct drm_device *dev = crtc->base.dev;
3755 struct drm_i915_private *dev_priv = to_i915(dev);
3756 int pipe = crtc->pipe;
3757 i915_reg_t reg;
3758 u32 temp;
3759
3760 /* enable normal train */
3761 reg = FDI_TX_CTL(pipe);
3762 temp = I915_READ(reg);
3763 if (IS_IVYBRIDGE(dev_priv)) {
3764 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3765 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3766 } else {
3767 temp &= ~FDI_LINK_TRAIN_NONE;
3768 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3769 }
3770 I915_WRITE(reg, temp);
3771
3772 reg = FDI_RX_CTL(pipe);
3773 temp = I915_READ(reg);
3774 if (HAS_PCH_CPT(dev_priv)) {
3775 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3776 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3777 } else {
3778 temp &= ~FDI_LINK_TRAIN_NONE;
3779 temp |= FDI_LINK_TRAIN_NONE;
3780 }
3781 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3782
3783 /* wait one idle pattern time */
3784 POSTING_READ(reg);
3785 udelay(1000);
3786
3787 /* IVB wants error correction enabled */
3788 if (IS_IVYBRIDGE(dev_priv))
3789 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3790 FDI_FE_ERRC_ENABLE);
3791 }
3792
3793 /* The FDI link training functions for ILK/Ibexpeak. */
3794 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3795 const struct intel_crtc_state *crtc_state)
3796 {
3797 struct drm_device *dev = crtc->base.dev;
3798 struct drm_i915_private *dev_priv = to_i915(dev);
3799 int pipe = crtc->pipe;
3800 i915_reg_t reg;
3801 u32 temp, tries;
3802
3803 /* FDI needs bits from pipe first */
3804 assert_pipe_enabled(dev_priv, pipe);
3805
3806 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3807 for train result */
3808 reg = FDI_RX_IMR(pipe);
3809 temp = I915_READ(reg);
3810 temp &= ~FDI_RX_SYMBOL_LOCK;
3811 temp &= ~FDI_RX_BIT_LOCK;
3812 I915_WRITE(reg, temp);
3813 I915_READ(reg);
3814 udelay(150);
3815
3816 /* enable CPU FDI TX and PCH FDI RX */
3817 reg = FDI_TX_CTL(pipe);
3818 temp = I915_READ(reg);
3819 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3820 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3821 temp &= ~FDI_LINK_TRAIN_NONE;
3822 temp |= FDI_LINK_TRAIN_PATTERN_1;
3823 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3824
3825 reg = FDI_RX_CTL(pipe);
3826 temp = I915_READ(reg);
3827 temp &= ~FDI_LINK_TRAIN_NONE;
3828 temp |= FDI_LINK_TRAIN_PATTERN_1;
3829 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3830
3831 POSTING_READ(reg);
3832 udelay(150);
3833
3834 /* Ironlake workaround, enable clock pointer after FDI enable*/
3835 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3836 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3837 FDI_RX_PHASE_SYNC_POINTER_EN);
3838
3839 reg = FDI_RX_IIR(pipe);
3840 for (tries = 0; tries < 5; tries++) {
3841 temp = I915_READ(reg);
3842 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3843
3844 if ((temp & FDI_RX_BIT_LOCK)) {
3845 DRM_DEBUG_KMS("FDI train 1 done.\n");
3846 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3847 break;
3848 }
3849 }
3850 if (tries == 5)
3851 DRM_ERROR("FDI train 1 fail!\n");
3852
3853 /* Train 2 */
3854 reg = FDI_TX_CTL(pipe);
3855 temp = I915_READ(reg);
3856 temp &= ~FDI_LINK_TRAIN_NONE;
3857 temp |= FDI_LINK_TRAIN_PATTERN_2;
3858 I915_WRITE(reg, temp);
3859
3860 reg = FDI_RX_CTL(pipe);
3861 temp = I915_READ(reg);
3862 temp &= ~FDI_LINK_TRAIN_NONE;
3863 temp |= FDI_LINK_TRAIN_PATTERN_2;
3864 I915_WRITE(reg, temp);
3865
3866 POSTING_READ(reg);
3867 udelay(150);
3868
3869 reg = FDI_RX_IIR(pipe);
3870 for (tries = 0; tries < 5; tries++) {
3871 temp = I915_READ(reg);
3872 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3873
3874 if (temp & FDI_RX_SYMBOL_LOCK) {
3875 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3876 DRM_DEBUG_KMS("FDI train 2 done.\n");
3877 break;
3878 }
3879 }
3880 if (tries == 5)
3881 DRM_ERROR("FDI train 2 fail!\n");
3882
3883 DRM_DEBUG_KMS("FDI train done\n");
3884
3885 }
3886
3887 static const int snb_b_fdi_train_param[] = {
3888 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3889 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3890 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3891 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3892 };
3893
3894 /* The FDI link training functions for SNB/Cougarpoint. */
3895 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3896 const struct intel_crtc_state *crtc_state)
3897 {
3898 struct drm_device *dev = crtc->base.dev;
3899 struct drm_i915_private *dev_priv = to_i915(dev);
3900 int pipe = crtc->pipe;
3901 i915_reg_t reg;
3902 u32 temp, i, retry;
3903
3904 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3905 for train result */
3906 reg = FDI_RX_IMR(pipe);
3907 temp = I915_READ(reg);
3908 temp &= ~FDI_RX_SYMBOL_LOCK;
3909 temp &= ~FDI_RX_BIT_LOCK;
3910 I915_WRITE(reg, temp);
3911
3912 POSTING_READ(reg);
3913 udelay(150);
3914
3915 /* enable CPU FDI TX and PCH FDI RX */
3916 reg = FDI_TX_CTL(pipe);
3917 temp = I915_READ(reg);
3918 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3919 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3920 temp &= ~FDI_LINK_TRAIN_NONE;
3921 temp |= FDI_LINK_TRAIN_PATTERN_1;
3922 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3923 /* SNB-B */
3924 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3925 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3926
3927 I915_WRITE(FDI_RX_MISC(pipe),
3928 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3929
3930 reg = FDI_RX_CTL(pipe);
3931 temp = I915_READ(reg);
3932 if (HAS_PCH_CPT(dev_priv)) {
3933 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3934 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3935 } else {
3936 temp &= ~FDI_LINK_TRAIN_NONE;
3937 temp |= FDI_LINK_TRAIN_PATTERN_1;
3938 }
3939 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3940
3941 POSTING_READ(reg);
3942 udelay(150);
3943
3944 for (i = 0; i < 4; i++) {
3945 reg = FDI_TX_CTL(pipe);
3946 temp = I915_READ(reg);
3947 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3948 temp |= snb_b_fdi_train_param[i];
3949 I915_WRITE(reg, temp);
3950
3951 POSTING_READ(reg);
3952 udelay(500);
3953
3954 for (retry = 0; retry < 5; retry++) {
3955 reg = FDI_RX_IIR(pipe);
3956 temp = I915_READ(reg);
3957 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3958 if (temp & FDI_RX_BIT_LOCK) {
3959 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3960 DRM_DEBUG_KMS("FDI train 1 done.\n");
3961 break;
3962 }
3963 udelay(50);
3964 }
3965 if (retry < 5)
3966 break;
3967 }
3968 if (i == 4)
3969 DRM_ERROR("FDI train 1 fail!\n");
3970
3971 /* Train 2 */
3972 reg = FDI_TX_CTL(pipe);
3973 temp = I915_READ(reg);
3974 temp &= ~FDI_LINK_TRAIN_NONE;
3975 temp |= FDI_LINK_TRAIN_PATTERN_2;
3976 if (IS_GEN6(dev_priv)) {
3977 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3978 /* SNB-B */
3979 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3980 }
3981 I915_WRITE(reg, temp);
3982
3983 reg = FDI_RX_CTL(pipe);
3984 temp = I915_READ(reg);
3985 if (HAS_PCH_CPT(dev_priv)) {
3986 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3987 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3988 } else {
3989 temp &= ~FDI_LINK_TRAIN_NONE;
3990 temp |= FDI_LINK_TRAIN_PATTERN_2;
3991 }
3992 I915_WRITE(reg, temp);
3993
3994 POSTING_READ(reg);
3995 udelay(150);
3996
3997 for (i = 0; i < 4; i++) {
3998 reg = FDI_TX_CTL(pipe);
3999 temp = I915_READ(reg);
4000 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4001 temp |= snb_b_fdi_train_param[i];
4002 I915_WRITE(reg, temp);
4003
4004 POSTING_READ(reg);
4005 udelay(500);
4006
4007 for (retry = 0; retry < 5; retry++) {
4008 reg = FDI_RX_IIR(pipe);
4009 temp = I915_READ(reg);
4010 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4011 if (temp & FDI_RX_SYMBOL_LOCK) {
4012 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4013 DRM_DEBUG_KMS("FDI train 2 done.\n");
4014 break;
4015 }
4016 udelay(50);
4017 }
4018 if (retry < 5)
4019 break;
4020 }
4021 if (i == 4)
4022 DRM_ERROR("FDI train 2 fail!\n");
4023
4024 DRM_DEBUG_KMS("FDI train done.\n");
4025 }
4026
4027 /* Manual link training for Ivy Bridge A0 parts */
4028 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4029 const struct intel_crtc_state *crtc_state)
4030 {
4031 struct drm_device *dev = crtc->base.dev;
4032 struct drm_i915_private *dev_priv = to_i915(dev);
4033 int pipe = crtc->pipe;
4034 i915_reg_t reg;
4035 u32 temp, i, j;
4036
4037 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4038 for train result */
4039 reg = FDI_RX_IMR(pipe);
4040 temp = I915_READ(reg);
4041 temp &= ~FDI_RX_SYMBOL_LOCK;
4042 temp &= ~FDI_RX_BIT_LOCK;
4043 I915_WRITE(reg, temp);
4044
4045 POSTING_READ(reg);
4046 udelay(150);
4047
4048 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4049 I915_READ(FDI_RX_IIR(pipe)));
4050
4051 /* Try each vswing and preemphasis setting twice before moving on */
4052 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4053 /* disable first in case we need to retry */
4054 reg = FDI_TX_CTL(pipe);
4055 temp = I915_READ(reg);
4056 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4057 temp &= ~FDI_TX_ENABLE;
4058 I915_WRITE(reg, temp);
4059
4060 reg = FDI_RX_CTL(pipe);
4061 temp = I915_READ(reg);
4062 temp &= ~FDI_LINK_TRAIN_AUTO;
4063 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4064 temp &= ~FDI_RX_ENABLE;
4065 I915_WRITE(reg, temp);
4066
4067 /* enable CPU FDI TX and PCH FDI RX */
4068 reg = FDI_TX_CTL(pipe);
4069 temp = I915_READ(reg);
4070 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4071 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4072 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4073 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4074 temp |= snb_b_fdi_train_param[j/2];
4075 temp |= FDI_COMPOSITE_SYNC;
4076 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4077
4078 I915_WRITE(FDI_RX_MISC(pipe),
4079 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4080
4081 reg = FDI_RX_CTL(pipe);
4082 temp = I915_READ(reg);
4083 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4084 temp |= FDI_COMPOSITE_SYNC;
4085 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4086
4087 POSTING_READ(reg);
4088 udelay(1); /* should be 0.5us */
4089
4090 for (i = 0; i < 4; i++) {
4091 reg = FDI_RX_IIR(pipe);
4092 temp = I915_READ(reg);
4093 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4094
4095 if (temp & FDI_RX_BIT_LOCK ||
4096 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4097 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4098 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4099 i);
4100 break;
4101 }
4102 udelay(1); /* should be 0.5us */
4103 }
4104 if (i == 4) {
4105 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4106 continue;
4107 }
4108
4109 /* Train 2 */
4110 reg = FDI_TX_CTL(pipe);
4111 temp = I915_READ(reg);
4112 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4113 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4114 I915_WRITE(reg, temp);
4115
4116 reg = FDI_RX_CTL(pipe);
4117 temp = I915_READ(reg);
4118 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4119 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4120 I915_WRITE(reg, temp);
4121
4122 POSTING_READ(reg);
4123 udelay(2); /* should be 1.5us */
4124
4125 for (i = 0; i < 4; i++) {
4126 reg = FDI_RX_IIR(pipe);
4127 temp = I915_READ(reg);
4128 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4129
4130 if (temp & FDI_RX_SYMBOL_LOCK ||
4131 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4132 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4133 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4134 i);
4135 goto train_done;
4136 }
4137 udelay(2); /* should be 1.5us */
4138 }
4139 if (i == 4)
4140 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4141 }
4142
4143 train_done:
4144 DRM_DEBUG_KMS("FDI train done.\n");
4145 }
4146
4147 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4148 {
4149 struct drm_device *dev = intel_crtc->base.dev;
4150 struct drm_i915_private *dev_priv = to_i915(dev);
4151 int pipe = intel_crtc->pipe;
4152 i915_reg_t reg;
4153 u32 temp;
4154
4155 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4156 reg = FDI_RX_CTL(pipe);
4157 temp = I915_READ(reg);
4158 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4159 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4160 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4161 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4162
4163 POSTING_READ(reg);
4164 udelay(200);
4165
4166 /* Switch from Rawclk to PCDclk */
4167 temp = I915_READ(reg);
4168 I915_WRITE(reg, temp | FDI_PCDCLK);
4169
4170 POSTING_READ(reg);
4171 udelay(200);
4172
4173 /* Enable CPU FDI TX PLL, always on for Ironlake */
4174 reg = FDI_TX_CTL(pipe);
4175 temp = I915_READ(reg);
4176 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4177 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4178
4179 POSTING_READ(reg);
4180 udelay(100);
4181 }
4182 }
4183
4184 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4185 {
4186 struct drm_device *dev = intel_crtc->base.dev;
4187 struct drm_i915_private *dev_priv = to_i915(dev);
4188 int pipe = intel_crtc->pipe;
4189 i915_reg_t reg;
4190 u32 temp;
4191
4192 /* Switch from PCDclk to Rawclk */
4193 reg = FDI_RX_CTL(pipe);
4194 temp = I915_READ(reg);
4195 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4196
4197 /* Disable CPU FDI TX PLL */
4198 reg = FDI_TX_CTL(pipe);
4199 temp = I915_READ(reg);
4200 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4201
4202 POSTING_READ(reg);
4203 udelay(100);
4204
4205 reg = FDI_RX_CTL(pipe);
4206 temp = I915_READ(reg);
4207 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4208
4209 /* Wait for the clocks to turn off. */
4210 POSTING_READ(reg);
4211 udelay(100);
4212 }
4213
4214 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4215 {
4216 struct drm_device *dev = crtc->dev;
4217 struct drm_i915_private *dev_priv = to_i915(dev);
4218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4219 int pipe = intel_crtc->pipe;
4220 i915_reg_t reg;
4221 u32 temp;
4222
4223 /* disable CPU FDI tx and PCH FDI rx */
4224 reg = FDI_TX_CTL(pipe);
4225 temp = I915_READ(reg);
4226 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4227 POSTING_READ(reg);
4228
4229 reg = FDI_RX_CTL(pipe);
4230 temp = I915_READ(reg);
4231 temp &= ~(0x7 << 16);
4232 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4233 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4234
4235 POSTING_READ(reg);
4236 udelay(100);
4237
4238 /* Ironlake workaround, disable clock pointer after downing FDI */
4239 if (HAS_PCH_IBX(dev_priv))
4240 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4241
4242 /* still set train pattern 1 */
4243 reg = FDI_TX_CTL(pipe);
4244 temp = I915_READ(reg);
4245 temp &= ~FDI_LINK_TRAIN_NONE;
4246 temp |= FDI_LINK_TRAIN_PATTERN_1;
4247 I915_WRITE(reg, temp);
4248
4249 reg = FDI_RX_CTL(pipe);
4250 temp = I915_READ(reg);
4251 if (HAS_PCH_CPT(dev_priv)) {
4252 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4253 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4254 } else {
4255 temp &= ~FDI_LINK_TRAIN_NONE;
4256 temp |= FDI_LINK_TRAIN_PATTERN_1;
4257 }
4258 /* BPC in FDI rx is consistent with that in PIPECONF */
4259 temp &= ~(0x07 << 16);
4260 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4261 I915_WRITE(reg, temp);
4262
4263 POSTING_READ(reg);
4264 udelay(100);
4265 }
4266
4267 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4268 {
4269 struct intel_crtc *crtc;
4270
4271 /* Note that we don't need to be called with mode_config.lock here
4272 * as our list of CRTC objects is static for the lifetime of the
4273 * device and so cannot disappear as we iterate. Similarly, we can
4274 * happily treat the predicates as racy, atomic checks as userspace
4275 * cannot claim and pin a new fb without at least acquring the
4276 * struct_mutex and so serialising with us.
4277 */
4278 for_each_intel_crtc(&dev_priv->drm, crtc) {
4279 if (atomic_read(&crtc->unpin_work_count) == 0)
4280 continue;
4281
4282 if (crtc->flip_work)
4283 intel_wait_for_vblank(dev_priv, crtc->pipe);
4284
4285 return true;
4286 }
4287
4288 return false;
4289 }
4290
4291 static void page_flip_completed(struct intel_crtc *intel_crtc)
4292 {
4293 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4294 struct intel_flip_work *work = intel_crtc->flip_work;
4295
4296 intel_crtc->flip_work = NULL;
4297
4298 if (work->event)
4299 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4300
4301 drm_crtc_vblank_put(&intel_crtc->base);
4302
4303 wake_up_all(&dev_priv->pending_flip_queue);
4304 trace_i915_flip_complete(intel_crtc->plane,
4305 work->pending_flip_obj);
4306
4307 queue_work(dev_priv->wq, &work->unpin_work);
4308 }
4309
4310 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4311 {
4312 struct drm_device *dev = crtc->dev;
4313 struct drm_i915_private *dev_priv = to_i915(dev);
4314 long ret;
4315
4316 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4317
4318 ret = wait_event_interruptible_timeout(
4319 dev_priv->pending_flip_queue,
4320 !intel_crtc_has_pending_flip(crtc),
4321 60*HZ);
4322
4323 if (ret < 0)
4324 return ret;
4325
4326 if (ret == 0) {
4327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4328 struct intel_flip_work *work;
4329
4330 spin_lock_irq(&dev->event_lock);
4331 work = intel_crtc->flip_work;
4332 if (work && !is_mmio_work(work)) {
4333 WARN_ONCE(1, "Removing stuck page flip\n");
4334 page_flip_completed(intel_crtc);
4335 }
4336 spin_unlock_irq(&dev->event_lock);
4337 }
4338
4339 return 0;
4340 }
4341
4342 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4343 {
4344 u32 temp;
4345
4346 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4347
4348 mutex_lock(&dev_priv->sb_lock);
4349
4350 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4351 temp |= SBI_SSCCTL_DISABLE;
4352 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4353
4354 mutex_unlock(&dev_priv->sb_lock);
4355 }
4356
4357 /* Program iCLKIP clock to the desired frequency */
4358 static void lpt_program_iclkip(struct intel_crtc *crtc)
4359 {
4360 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4361 int clock = crtc->config->base.adjusted_mode.crtc_clock;
4362 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4363 u32 temp;
4364
4365 lpt_disable_iclkip(dev_priv);
4366
4367 /* The iCLK virtual clock root frequency is in MHz,
4368 * but the adjusted_mode->crtc_clock in in KHz. To get the
4369 * divisors, it is necessary to divide one by another, so we
4370 * convert the virtual clock precision to KHz here for higher
4371 * precision.
4372 */
4373 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4374 u32 iclk_virtual_root_freq = 172800 * 1000;
4375 u32 iclk_pi_range = 64;
4376 u32 desired_divisor;
4377
4378 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4379 clock << auxdiv);
4380 divsel = (desired_divisor / iclk_pi_range) - 2;
4381 phaseinc = desired_divisor % iclk_pi_range;
4382
4383 /*
4384 * Near 20MHz is a corner case which is
4385 * out of range for the 7-bit divisor
4386 */
4387 if (divsel <= 0x7f)
4388 break;
4389 }
4390
4391 /* This should not happen with any sane values */
4392 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4393 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4394 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4395 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4396
4397 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4398 clock,
4399 auxdiv,
4400 divsel,
4401 phasedir,
4402 phaseinc);
4403
4404 mutex_lock(&dev_priv->sb_lock);
4405
4406 /* Program SSCDIVINTPHASE6 */
4407 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4408 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4409 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4410 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4411 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4412 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4413 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4414 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4415
4416 /* Program SSCAUXDIV */
4417 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4418 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4419 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4420 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4421
4422 /* Enable modulator and associated divider */
4423 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4424 temp &= ~SBI_SSCCTL_DISABLE;
4425 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4426
4427 mutex_unlock(&dev_priv->sb_lock);
4428
4429 /* Wait for initialization time */
4430 udelay(24);
4431
4432 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4433 }
4434
4435 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4436 {
4437 u32 divsel, phaseinc, auxdiv;
4438 u32 iclk_virtual_root_freq = 172800 * 1000;
4439 u32 iclk_pi_range = 64;
4440 u32 desired_divisor;
4441 u32 temp;
4442
4443 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4444 return 0;
4445
4446 mutex_lock(&dev_priv->sb_lock);
4447
4448 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4449 if (temp & SBI_SSCCTL_DISABLE) {
4450 mutex_unlock(&dev_priv->sb_lock);
4451 return 0;
4452 }
4453
4454 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4455 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4456 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4457 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4458 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4459
4460 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4461 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4462 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4463
4464 mutex_unlock(&dev_priv->sb_lock);
4465
4466 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4467
4468 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4469 desired_divisor << auxdiv);
4470 }
4471
4472 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4473 enum pipe pch_transcoder)
4474 {
4475 struct drm_device *dev = crtc->base.dev;
4476 struct drm_i915_private *dev_priv = to_i915(dev);
4477 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4478
4479 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4480 I915_READ(HTOTAL(cpu_transcoder)));
4481 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4482 I915_READ(HBLANK(cpu_transcoder)));
4483 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4484 I915_READ(HSYNC(cpu_transcoder)));
4485
4486 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4487 I915_READ(VTOTAL(cpu_transcoder)));
4488 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4489 I915_READ(VBLANK(cpu_transcoder)));
4490 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4491 I915_READ(VSYNC(cpu_transcoder)));
4492 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4493 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4494 }
4495
4496 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4497 {
4498 struct drm_i915_private *dev_priv = to_i915(dev);
4499 uint32_t temp;
4500
4501 temp = I915_READ(SOUTH_CHICKEN1);
4502 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4503 return;
4504
4505 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4506 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4507
4508 temp &= ~FDI_BC_BIFURCATION_SELECT;
4509 if (enable)
4510 temp |= FDI_BC_BIFURCATION_SELECT;
4511
4512 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4513 I915_WRITE(SOUTH_CHICKEN1, temp);
4514 POSTING_READ(SOUTH_CHICKEN1);
4515 }
4516
4517 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4518 {
4519 struct drm_device *dev = intel_crtc->base.dev;
4520
4521 switch (intel_crtc->pipe) {
4522 case PIPE_A:
4523 break;
4524 case PIPE_B:
4525 if (intel_crtc->config->fdi_lanes > 2)
4526 cpt_set_fdi_bc_bifurcation(dev, false);
4527 else
4528 cpt_set_fdi_bc_bifurcation(dev, true);
4529
4530 break;
4531 case PIPE_C:
4532 cpt_set_fdi_bc_bifurcation(dev, true);
4533
4534 break;
4535 default:
4536 BUG();
4537 }
4538 }
4539
4540 /* Return which DP Port should be selected for Transcoder DP control */
4541 static enum port
4542 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4543 {
4544 struct drm_device *dev = crtc->base.dev;
4545 struct intel_encoder *encoder;
4546
4547 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4548 if (encoder->type == INTEL_OUTPUT_DP ||
4549 encoder->type == INTEL_OUTPUT_EDP)
4550 return enc_to_dig_port(&encoder->base)->port;
4551 }
4552
4553 return -1;
4554 }
4555
4556 /*
4557 * Enable PCH resources required for PCH ports:
4558 * - PCH PLLs
4559 * - FDI training & RX/TX
4560 * - update transcoder timings
4561 * - DP transcoding bits
4562 * - transcoder
4563 */
4564 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4565 {
4566 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4567 struct drm_device *dev = crtc->base.dev;
4568 struct drm_i915_private *dev_priv = to_i915(dev);
4569 int pipe = crtc->pipe;
4570 u32 temp;
4571
4572 assert_pch_transcoder_disabled(dev_priv, pipe);
4573
4574 if (IS_IVYBRIDGE(dev_priv))
4575 ivybridge_update_fdi_bc_bifurcation(crtc);
4576
4577 /* Write the TU size bits before fdi link training, so that error
4578 * detection works. */
4579 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4580 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4581
4582 /* For PCH output, training FDI link */
4583 dev_priv->display.fdi_link_train(crtc, crtc_state);
4584
4585 /* We need to program the right clock selection before writing the pixel
4586 * mutliplier into the DPLL. */
4587 if (HAS_PCH_CPT(dev_priv)) {
4588 u32 sel;
4589
4590 temp = I915_READ(PCH_DPLL_SEL);
4591 temp |= TRANS_DPLL_ENABLE(pipe);
4592 sel = TRANS_DPLLB_SEL(pipe);
4593 if (crtc_state->shared_dpll ==
4594 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4595 temp |= sel;
4596 else
4597 temp &= ~sel;
4598 I915_WRITE(PCH_DPLL_SEL, temp);
4599 }
4600
4601 /* XXX: pch pll's can be enabled any time before we enable the PCH
4602 * transcoder, and we actually should do this to not upset any PCH
4603 * transcoder that already use the clock when we share it.
4604 *
4605 * Note that enable_shared_dpll tries to do the right thing, but
4606 * get_shared_dpll unconditionally resets the pll - we need that to have
4607 * the right LVDS enable sequence. */
4608 intel_enable_shared_dpll(crtc);
4609
4610 /* set transcoder timing, panel must allow it */
4611 assert_panel_unlocked(dev_priv, pipe);
4612 ironlake_pch_transcoder_set_timings(crtc, pipe);
4613
4614 intel_fdi_normal_train(crtc);
4615
4616 /* For PCH DP, enable TRANS_DP_CTL */
4617 if (HAS_PCH_CPT(dev_priv) &&
4618 intel_crtc_has_dp_encoder(crtc_state)) {
4619 const struct drm_display_mode *adjusted_mode =
4620 &crtc_state->base.adjusted_mode;
4621 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4622 i915_reg_t reg = TRANS_DP_CTL(pipe);
4623 temp = I915_READ(reg);
4624 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4625 TRANS_DP_SYNC_MASK |
4626 TRANS_DP_BPC_MASK);
4627 temp |= TRANS_DP_OUTPUT_ENABLE;
4628 temp |= bpc << 9; /* same format but at 11:9 */
4629
4630 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4631 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4632 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4633 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4634
4635 switch (intel_trans_dp_port_sel(crtc)) {
4636 case PORT_B:
4637 temp |= TRANS_DP_PORT_SEL_B;
4638 break;
4639 case PORT_C:
4640 temp |= TRANS_DP_PORT_SEL_C;
4641 break;
4642 case PORT_D:
4643 temp |= TRANS_DP_PORT_SEL_D;
4644 break;
4645 default:
4646 BUG();
4647 }
4648
4649 I915_WRITE(reg, temp);
4650 }
4651
4652 ironlake_enable_pch_transcoder(dev_priv, pipe);
4653 }
4654
4655 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4656 {
4657 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4658 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4659 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4660
4661 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4662
4663 lpt_program_iclkip(crtc);
4664
4665 /* Set transcoder timing. */
4666 ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4667
4668 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4669 }
4670
4671 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4672 {
4673 struct drm_i915_private *dev_priv = to_i915(dev);
4674 i915_reg_t dslreg = PIPEDSL(pipe);
4675 u32 temp;
4676
4677 temp = I915_READ(dslreg);
4678 udelay(500);
4679 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4680 if (wait_for(I915_READ(dslreg) != temp, 5))
4681 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4682 }
4683 }
4684
4685 static int
4686 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4687 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4688 int src_w, int src_h, int dst_w, int dst_h)
4689 {
4690 struct intel_crtc_scaler_state *scaler_state =
4691 &crtc_state->scaler_state;
4692 struct intel_crtc *intel_crtc =
4693 to_intel_crtc(crtc_state->base.crtc);
4694 int need_scaling;
4695
4696 need_scaling = drm_rotation_90_or_270(rotation) ?
4697 (src_h != dst_w || src_w != dst_h):
4698 (src_w != dst_w || src_h != dst_h);
4699
4700 /*
4701 * if plane is being disabled or scaler is no more required or force detach
4702 * - free scaler binded to this plane/crtc
4703 * - in order to do this, update crtc->scaler_usage
4704 *
4705 * Here scaler state in crtc_state is set free so that
4706 * scaler can be assigned to other user. Actual register
4707 * update to free the scaler is done in plane/panel-fit programming.
4708 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4709 */
4710 if (force_detach || !need_scaling) {
4711 if (*scaler_id >= 0) {
4712 scaler_state->scaler_users &= ~(1 << scaler_user);
4713 scaler_state->scalers[*scaler_id].in_use = 0;
4714
4715 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4716 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4717 intel_crtc->pipe, scaler_user, *scaler_id,
4718 scaler_state->scaler_users);
4719 *scaler_id = -1;
4720 }
4721 return 0;
4722 }
4723
4724 /* range checks */
4725 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4726 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4727
4728 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4729 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4730 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4731 "size is out of scaler range\n",
4732 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4733 return -EINVAL;
4734 }
4735
4736 /* mark this plane as a scaler user in crtc_state */
4737 scaler_state->scaler_users |= (1 << scaler_user);
4738 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4739 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4740 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4741 scaler_state->scaler_users);
4742
4743 return 0;
4744 }
4745
4746 /**
4747 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4748 *
4749 * @state: crtc's scaler state
4750 *
4751 * Return
4752 * 0 - scaler_usage updated successfully
4753 * error - requested scaling cannot be supported or other error condition
4754 */
4755 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4756 {
4757 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4758
4759 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4760 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4761 state->pipe_src_w, state->pipe_src_h,
4762 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4763 }
4764
4765 /**
4766 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4767 *
4768 * @state: crtc's scaler state
4769 * @plane_state: atomic plane state to update
4770 *
4771 * Return
4772 * 0 - scaler_usage updated successfully
4773 * error - requested scaling cannot be supported or other error condition
4774 */
4775 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4776 struct intel_plane_state *plane_state)
4777 {
4778
4779 struct intel_plane *intel_plane =
4780 to_intel_plane(plane_state->base.plane);
4781 struct drm_framebuffer *fb = plane_state->base.fb;
4782 int ret;
4783
4784 bool force_detach = !fb || !plane_state->base.visible;
4785
4786 ret = skl_update_scaler(crtc_state, force_detach,
4787 drm_plane_index(&intel_plane->base),
4788 &plane_state->scaler_id,
4789 plane_state->base.rotation,
4790 drm_rect_width(&plane_state->base.src) >> 16,
4791 drm_rect_height(&plane_state->base.src) >> 16,
4792 drm_rect_width(&plane_state->base.dst),
4793 drm_rect_height(&plane_state->base.dst));
4794
4795 if (ret || plane_state->scaler_id < 0)
4796 return ret;
4797
4798 /* check colorkey */
4799 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4800 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4801 intel_plane->base.base.id,
4802 intel_plane->base.name);
4803 return -EINVAL;
4804 }
4805
4806 /* Check src format */
4807 switch (fb->format->format) {
4808 case DRM_FORMAT_RGB565:
4809 case DRM_FORMAT_XBGR8888:
4810 case DRM_FORMAT_XRGB8888:
4811 case DRM_FORMAT_ABGR8888:
4812 case DRM_FORMAT_ARGB8888:
4813 case DRM_FORMAT_XRGB2101010:
4814 case DRM_FORMAT_XBGR2101010:
4815 case DRM_FORMAT_YUYV:
4816 case DRM_FORMAT_YVYU:
4817 case DRM_FORMAT_UYVY:
4818 case DRM_FORMAT_VYUY:
4819 break;
4820 default:
4821 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4822 intel_plane->base.base.id, intel_plane->base.name,
4823 fb->base.id, fb->format->format);
4824 return -EINVAL;
4825 }
4826
4827 return 0;
4828 }
4829
4830 static void skylake_scaler_disable(struct intel_crtc *crtc)
4831 {
4832 int i;
4833
4834 for (i = 0; i < crtc->num_scalers; i++)
4835 skl_detach_scaler(crtc, i);
4836 }
4837
4838 static void skylake_pfit_enable(struct intel_crtc *crtc)
4839 {
4840 struct drm_device *dev = crtc->base.dev;
4841 struct drm_i915_private *dev_priv = to_i915(dev);
4842 int pipe = crtc->pipe;
4843 struct intel_crtc_scaler_state *scaler_state =
4844 &crtc->config->scaler_state;
4845
4846 if (crtc->config->pch_pfit.enabled) {
4847 int id;
4848
4849 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4850 return;
4851
4852 id = scaler_state->scaler_id;
4853 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4854 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4855 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4856 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4857 }
4858 }
4859
4860 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4861 {
4862 struct drm_device *dev = crtc->base.dev;
4863 struct drm_i915_private *dev_priv = to_i915(dev);
4864 int pipe = crtc->pipe;
4865
4866 if (crtc->config->pch_pfit.enabled) {
4867 /* Force use of hard-coded filter coefficients
4868 * as some pre-programmed values are broken,
4869 * e.g. x201.
4870 */
4871 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4872 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4873 PF_PIPE_SEL_IVB(pipe));
4874 else
4875 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4876 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4877 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4878 }
4879 }
4880
4881 void hsw_enable_ips(struct intel_crtc *crtc)
4882 {
4883 struct drm_device *dev = crtc->base.dev;
4884 struct drm_i915_private *dev_priv = to_i915(dev);
4885
4886 if (!crtc->config->ips_enabled)
4887 return;
4888
4889 /*
4890 * We can only enable IPS after we enable a plane and wait for a vblank
4891 * This function is called from post_plane_update, which is run after
4892 * a vblank wait.
4893 */
4894
4895 assert_plane_enabled(dev_priv, crtc->plane);
4896 if (IS_BROADWELL(dev_priv)) {
4897 mutex_lock(&dev_priv->rps.hw_lock);
4898 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4899 mutex_unlock(&dev_priv->rps.hw_lock);
4900 /* Quoting Art Runyan: "its not safe to expect any particular
4901 * value in IPS_CTL bit 31 after enabling IPS through the
4902 * mailbox." Moreover, the mailbox may return a bogus state,
4903 * so we need to just enable it and continue on.
4904 */
4905 } else {
4906 I915_WRITE(IPS_CTL, IPS_ENABLE);
4907 /* The bit only becomes 1 in the next vblank, so this wait here
4908 * is essentially intel_wait_for_vblank. If we don't have this
4909 * and don't wait for vblanks until the end of crtc_enable, then
4910 * the HW state readout code will complain that the expected
4911 * IPS_CTL value is not the one we read. */
4912 if (intel_wait_for_register(dev_priv,
4913 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4914 50))
4915 DRM_ERROR("Timed out waiting for IPS enable\n");
4916 }
4917 }
4918
4919 void hsw_disable_ips(struct intel_crtc *crtc)
4920 {
4921 struct drm_device *dev = crtc->base.dev;
4922 struct drm_i915_private *dev_priv = to_i915(dev);
4923
4924 if (!crtc->config->ips_enabled)
4925 return;
4926
4927 assert_plane_enabled(dev_priv, crtc->plane);
4928 if (IS_BROADWELL(dev_priv)) {
4929 mutex_lock(&dev_priv->rps.hw_lock);
4930 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4931 mutex_unlock(&dev_priv->rps.hw_lock);
4932 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4933 if (intel_wait_for_register(dev_priv,
4934 IPS_CTL, IPS_ENABLE, 0,
4935 42))
4936 DRM_ERROR("Timed out waiting for IPS disable\n");
4937 } else {
4938 I915_WRITE(IPS_CTL, 0);
4939 POSTING_READ(IPS_CTL);
4940 }
4941
4942 /* We need to wait for a vblank before we can disable the plane. */
4943 intel_wait_for_vblank(dev_priv, crtc->pipe);
4944 }
4945
4946 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4947 {
4948 if (intel_crtc->overlay) {
4949 struct drm_device *dev = intel_crtc->base.dev;
4950 struct drm_i915_private *dev_priv = to_i915(dev);
4951
4952 mutex_lock(&dev->struct_mutex);
4953 dev_priv->mm.interruptible = false;
4954 (void) intel_overlay_switch_off(intel_crtc->overlay);
4955 dev_priv->mm.interruptible = true;
4956 mutex_unlock(&dev->struct_mutex);
4957 }
4958
4959 /* Let userspace switch the overlay on again. In most cases userspace
4960 * has to recompute where to put it anyway.
4961 */
4962 }
4963
4964 /**
4965 * intel_post_enable_primary - Perform operations after enabling primary plane
4966 * @crtc: the CRTC whose primary plane was just enabled
4967 *
4968 * Performs potentially sleeping operations that must be done after the primary
4969 * plane is enabled, such as updating FBC and IPS. Note that this may be
4970 * called due to an explicit primary plane update, or due to an implicit
4971 * re-enable that is caused when a sprite plane is updated to no longer
4972 * completely hide the primary plane.
4973 */
4974 static void
4975 intel_post_enable_primary(struct drm_crtc *crtc)
4976 {
4977 struct drm_device *dev = crtc->dev;
4978 struct drm_i915_private *dev_priv = to_i915(dev);
4979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4980 int pipe = intel_crtc->pipe;
4981
4982 /*
4983 * FIXME IPS should be fine as long as one plane is
4984 * enabled, but in practice it seems to have problems
4985 * when going from primary only to sprite only and vice
4986 * versa.
4987 */
4988 hsw_enable_ips(intel_crtc);
4989
4990 /*
4991 * Gen2 reports pipe underruns whenever all planes are disabled.
4992 * So don't enable underrun reporting before at least some planes
4993 * are enabled.
4994 * FIXME: Need to fix the logic to work when we turn off all planes
4995 * but leave the pipe running.
4996 */
4997 if (IS_GEN2(dev_priv))
4998 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4999
5000 /* Underruns don't always raise interrupts, so check manually. */
5001 intel_check_cpu_fifo_underruns(dev_priv);
5002 intel_check_pch_fifo_underruns(dev_priv);
5003 }
5004
5005 /* FIXME move all this to pre_plane_update() with proper state tracking */
5006 static void
5007 intel_pre_disable_primary(struct drm_crtc *crtc)
5008 {
5009 struct drm_device *dev = crtc->dev;
5010 struct drm_i915_private *dev_priv = to_i915(dev);
5011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5012 int pipe = intel_crtc->pipe;
5013
5014 /*
5015 * Gen2 reports pipe underruns whenever all planes are disabled.
5016 * So diasble underrun reporting before all the planes get disabled.
5017 * FIXME: Need to fix the logic to work when we turn off all planes
5018 * but leave the pipe running.
5019 */
5020 if (IS_GEN2(dev_priv))
5021 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5022
5023 /*
5024 * FIXME IPS should be fine as long as one plane is
5025 * enabled, but in practice it seems to have problems
5026 * when going from primary only to sprite only and vice
5027 * versa.
5028 */
5029 hsw_disable_ips(intel_crtc);
5030 }
5031
5032 /* FIXME get rid of this and use pre_plane_update */
5033 static void
5034 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5035 {
5036 struct drm_device *dev = crtc->dev;
5037 struct drm_i915_private *dev_priv = to_i915(dev);
5038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5039 int pipe = intel_crtc->pipe;
5040
5041 intel_pre_disable_primary(crtc);
5042
5043 /*
5044 * Vblank time updates from the shadow to live plane control register
5045 * are blocked if the memory self-refresh mode is active at that
5046 * moment. So to make sure the plane gets truly disabled, disable
5047 * first the self-refresh mode. The self-refresh enable bit in turn
5048 * will be checked/applied by the HW only at the next frame start
5049 * event which is after the vblank start event, so we need to have a
5050 * wait-for-vblank between disabling the plane and the pipe.
5051 */
5052 if (HAS_GMCH_DISPLAY(dev_priv) &&
5053 intel_set_memory_cxsr(dev_priv, false))
5054 intel_wait_for_vblank(dev_priv, pipe);
5055 }
5056
5057 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5058 {
5059 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5060 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5061 struct intel_crtc_state *pipe_config =
5062 to_intel_crtc_state(crtc->base.state);
5063 struct drm_plane *primary = crtc->base.primary;
5064 struct drm_plane_state *old_pri_state =
5065 drm_atomic_get_existing_plane_state(old_state, primary);
5066
5067 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5068
5069 if (pipe_config->update_wm_post && pipe_config->base.active)
5070 intel_update_watermarks(crtc);
5071
5072 if (old_pri_state) {
5073 struct intel_plane_state *primary_state =
5074 to_intel_plane_state(primary->state);
5075 struct intel_plane_state *old_primary_state =
5076 to_intel_plane_state(old_pri_state);
5077
5078 intel_fbc_post_update(crtc);
5079
5080 if (primary_state->base.visible &&
5081 (needs_modeset(&pipe_config->base) ||
5082 !old_primary_state->base.visible))
5083 intel_post_enable_primary(&crtc->base);
5084 }
5085 }
5086
5087 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5088 struct intel_crtc_state *pipe_config)
5089 {
5090 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5091 struct drm_device *dev = crtc->base.dev;
5092 struct drm_i915_private *dev_priv = to_i915(dev);
5093 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5094 struct drm_plane *primary = crtc->base.primary;
5095 struct drm_plane_state *old_pri_state =
5096 drm_atomic_get_existing_plane_state(old_state, primary);
5097 bool modeset = needs_modeset(&pipe_config->base);
5098 struct intel_atomic_state *old_intel_state =
5099 to_intel_atomic_state(old_state);
5100
5101 if (old_pri_state) {
5102 struct intel_plane_state *primary_state =
5103 to_intel_plane_state(primary->state);
5104 struct intel_plane_state *old_primary_state =
5105 to_intel_plane_state(old_pri_state);
5106
5107 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5108
5109 if (old_primary_state->base.visible &&
5110 (modeset || !primary_state->base.visible))
5111 intel_pre_disable_primary(&crtc->base);
5112 }
5113
5114 /*
5115 * Vblank time updates from the shadow to live plane control register
5116 * are blocked if the memory self-refresh mode is active at that
5117 * moment. So to make sure the plane gets truly disabled, disable
5118 * first the self-refresh mode. The self-refresh enable bit in turn
5119 * will be checked/applied by the HW only at the next frame start
5120 * event which is after the vblank start event, so we need to have a
5121 * wait-for-vblank between disabling the plane and the pipe.
5122 */
5123 if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5124 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5125 intel_wait_for_vblank(dev_priv, crtc->pipe);
5126
5127 /*
5128 * IVB workaround: must disable low power watermarks for at least
5129 * one frame before enabling scaling. LP watermarks can be re-enabled
5130 * when scaling is disabled.
5131 *
5132 * WaCxSRDisabledForSpriteScaling:ivb
5133 */
5134 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5135 intel_wait_for_vblank(dev_priv, crtc->pipe);
5136
5137 /*
5138 * If we're doing a modeset, we're done. No need to do any pre-vblank
5139 * watermark programming here.
5140 */
5141 if (needs_modeset(&pipe_config->base))
5142 return;
5143
5144 /*
5145 * For platforms that support atomic watermarks, program the
5146 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5147 * will be the intermediate values that are safe for both pre- and
5148 * post- vblank; when vblank happens, the 'active' values will be set
5149 * to the final 'target' values and we'll do this again to get the
5150 * optimal watermarks. For gen9+ platforms, the values we program here
5151 * will be the final target values which will get automatically latched
5152 * at vblank time; no further programming will be necessary.
5153 *
5154 * If a platform hasn't been transitioned to atomic watermarks yet,
5155 * we'll continue to update watermarks the old way, if flags tell
5156 * us to.
5157 */
5158 if (dev_priv->display.initial_watermarks != NULL)
5159 dev_priv->display.initial_watermarks(old_intel_state,
5160 pipe_config);
5161 else if (pipe_config->update_wm_pre)
5162 intel_update_watermarks(crtc);
5163 }
5164
5165 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5166 {
5167 struct drm_device *dev = crtc->dev;
5168 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5169 struct drm_plane *p;
5170 int pipe = intel_crtc->pipe;
5171
5172 intel_crtc_dpms_overlay_disable(intel_crtc);
5173
5174 drm_for_each_plane_mask(p, dev, plane_mask)
5175 to_intel_plane(p)->disable_plane(p, crtc);
5176
5177 /*
5178 * FIXME: Once we grow proper nuclear flip support out of this we need
5179 * to compute the mask of flip planes precisely. For the time being
5180 * consider this a flip to a NULL plane.
5181 */
5182 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5183 }
5184
5185 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5186 struct intel_crtc_state *crtc_state,
5187 struct drm_atomic_state *old_state)
5188 {
5189 struct drm_connector_state *conn_state;
5190 struct drm_connector *conn;
5191 int i;
5192
5193 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5194 struct intel_encoder *encoder =
5195 to_intel_encoder(conn_state->best_encoder);
5196
5197 if (conn_state->crtc != crtc)
5198 continue;
5199
5200 if (encoder->pre_pll_enable)
5201 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5202 }
5203 }
5204
5205 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5206 struct intel_crtc_state *crtc_state,
5207 struct drm_atomic_state *old_state)
5208 {
5209 struct drm_connector_state *conn_state;
5210 struct drm_connector *conn;
5211 int i;
5212
5213 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5214 struct intel_encoder *encoder =
5215 to_intel_encoder(conn_state->best_encoder);
5216
5217 if (conn_state->crtc != crtc)
5218 continue;
5219
5220 if (encoder->pre_enable)
5221 encoder->pre_enable(encoder, crtc_state, conn_state);
5222 }
5223 }
5224
5225 static void intel_encoders_enable(struct drm_crtc *crtc,
5226 struct intel_crtc_state *crtc_state,
5227 struct drm_atomic_state *old_state)
5228 {
5229 struct drm_connector_state *conn_state;
5230 struct drm_connector *conn;
5231 int i;
5232
5233 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5234 struct intel_encoder *encoder =
5235 to_intel_encoder(conn_state->best_encoder);
5236
5237 if (conn_state->crtc != crtc)
5238 continue;
5239
5240 encoder->enable(encoder, crtc_state, conn_state);
5241 intel_opregion_notify_encoder(encoder, true);
5242 }
5243 }
5244
5245 static void intel_encoders_disable(struct drm_crtc *crtc,
5246 struct intel_crtc_state *old_crtc_state,
5247 struct drm_atomic_state *old_state)
5248 {
5249 struct drm_connector_state *old_conn_state;
5250 struct drm_connector *conn;
5251 int i;
5252
5253 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5254 struct intel_encoder *encoder =
5255 to_intel_encoder(old_conn_state->best_encoder);
5256
5257 if (old_conn_state->crtc != crtc)
5258 continue;
5259
5260 intel_opregion_notify_encoder(encoder, false);
5261 encoder->disable(encoder, old_crtc_state, old_conn_state);
5262 }
5263 }
5264
5265 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5266 struct intel_crtc_state *old_crtc_state,
5267 struct drm_atomic_state *old_state)
5268 {
5269 struct drm_connector_state *old_conn_state;
5270 struct drm_connector *conn;
5271 int i;
5272
5273 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5274 struct intel_encoder *encoder =
5275 to_intel_encoder(old_conn_state->best_encoder);
5276
5277 if (old_conn_state->crtc != crtc)
5278 continue;
5279
5280 if (encoder->post_disable)
5281 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5282 }
5283 }
5284
5285 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5286 struct intel_crtc_state *old_crtc_state,
5287 struct drm_atomic_state *old_state)
5288 {
5289 struct drm_connector_state *old_conn_state;
5290 struct drm_connector *conn;
5291 int i;
5292
5293 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5294 struct intel_encoder *encoder =
5295 to_intel_encoder(old_conn_state->best_encoder);
5296
5297 if (old_conn_state->crtc != crtc)
5298 continue;
5299
5300 if (encoder->post_pll_disable)
5301 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5302 }
5303 }
5304
5305 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5306 struct drm_atomic_state *old_state)
5307 {
5308 struct drm_crtc *crtc = pipe_config->base.crtc;
5309 struct drm_device *dev = crtc->dev;
5310 struct drm_i915_private *dev_priv = to_i915(dev);
5311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5312 int pipe = intel_crtc->pipe;
5313 struct intel_atomic_state *old_intel_state =
5314 to_intel_atomic_state(old_state);
5315
5316 if (WARN_ON(intel_crtc->active))
5317 return;
5318
5319 /*
5320 * Sometimes spurious CPU pipe underruns happen during FDI
5321 * training, at least with VGA+HDMI cloning. Suppress them.
5322 *
5323 * On ILK we get an occasional spurious CPU pipe underruns
5324 * between eDP port A enable and vdd enable. Also PCH port
5325 * enable seems to result in the occasional CPU pipe underrun.
5326 *
5327 * Spurious PCH underruns also occur during PCH enabling.
5328 */
5329 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5330 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5331 if (intel_crtc->config->has_pch_encoder)
5332 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5333
5334 if (intel_crtc->config->has_pch_encoder)
5335 intel_prepare_shared_dpll(intel_crtc);
5336
5337 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5338 intel_dp_set_m_n(intel_crtc, M1_N1);
5339
5340 intel_set_pipe_timings(intel_crtc);
5341 intel_set_pipe_src_size(intel_crtc);
5342
5343 if (intel_crtc->config->has_pch_encoder) {
5344 intel_cpu_transcoder_set_m_n(intel_crtc,
5345 &intel_crtc->config->fdi_m_n, NULL);
5346 }
5347
5348 ironlake_set_pipeconf(crtc);
5349
5350 intel_crtc->active = true;
5351
5352 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5353
5354 if (intel_crtc->config->has_pch_encoder) {
5355 /* Note: FDI PLL enabling _must_ be done before we enable the
5356 * cpu pipes, hence this is separate from all the other fdi/pch
5357 * enabling. */
5358 ironlake_fdi_pll_enable(intel_crtc);
5359 } else {
5360 assert_fdi_tx_disabled(dev_priv, pipe);
5361 assert_fdi_rx_disabled(dev_priv, pipe);
5362 }
5363
5364 ironlake_pfit_enable(intel_crtc);
5365
5366 /*
5367 * On ILK+ LUT must be loaded before the pipe is running but with
5368 * clocks enabled
5369 */
5370 intel_color_load_luts(&pipe_config->base);
5371
5372 if (dev_priv->display.initial_watermarks != NULL)
5373 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5374 intel_enable_pipe(intel_crtc);
5375
5376 if (intel_crtc->config->has_pch_encoder)
5377 ironlake_pch_enable(pipe_config);
5378
5379 assert_vblank_disabled(crtc);
5380 drm_crtc_vblank_on(crtc);
5381
5382 intel_encoders_enable(crtc, pipe_config, old_state);
5383
5384 if (HAS_PCH_CPT(dev_priv))
5385 cpt_verify_modeset(dev, intel_crtc->pipe);
5386
5387 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5388 if (intel_crtc->config->has_pch_encoder)
5389 intel_wait_for_vblank(dev_priv, pipe);
5390 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5391 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5392 }
5393
5394 /* IPS only exists on ULT machines and is tied to pipe A. */
5395 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5396 {
5397 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5398 }
5399
5400 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5401 struct drm_atomic_state *old_state)
5402 {
5403 struct drm_crtc *crtc = pipe_config->base.crtc;
5404 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5406 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5407 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5408 struct intel_atomic_state *old_intel_state =
5409 to_intel_atomic_state(old_state);
5410
5411 if (WARN_ON(intel_crtc->active))
5412 return;
5413
5414 if (intel_crtc->config->has_pch_encoder)
5415 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5416 false);
5417
5418 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5419
5420 if (intel_crtc->config->shared_dpll)
5421 intel_enable_shared_dpll(intel_crtc);
5422
5423 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5424 intel_dp_set_m_n(intel_crtc, M1_N1);
5425
5426 if (!transcoder_is_dsi(cpu_transcoder))
5427 intel_set_pipe_timings(intel_crtc);
5428
5429 intel_set_pipe_src_size(intel_crtc);
5430
5431 if (cpu_transcoder != TRANSCODER_EDP &&
5432 !transcoder_is_dsi(cpu_transcoder)) {
5433 I915_WRITE(PIPE_MULT(cpu_transcoder),
5434 intel_crtc->config->pixel_multiplier - 1);
5435 }
5436
5437 if (intel_crtc->config->has_pch_encoder) {
5438 intel_cpu_transcoder_set_m_n(intel_crtc,
5439 &intel_crtc->config->fdi_m_n, NULL);
5440 }
5441
5442 if (!transcoder_is_dsi(cpu_transcoder))
5443 haswell_set_pipeconf(crtc);
5444
5445 haswell_set_pipemisc(crtc);
5446
5447 intel_color_set_csc(&pipe_config->base);
5448
5449 intel_crtc->active = true;
5450
5451 if (intel_crtc->config->has_pch_encoder)
5452 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5453 else
5454 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5455
5456 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5457
5458 if (intel_crtc->config->has_pch_encoder)
5459 dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
5460
5461 if (!transcoder_is_dsi(cpu_transcoder))
5462 intel_ddi_enable_pipe_clock(pipe_config);
5463
5464 if (INTEL_GEN(dev_priv) >= 9)
5465 skylake_pfit_enable(intel_crtc);
5466 else
5467 ironlake_pfit_enable(intel_crtc);
5468
5469 /*
5470 * On ILK+ LUT must be loaded before the pipe is running but with
5471 * clocks enabled
5472 */
5473 intel_color_load_luts(&pipe_config->base);
5474
5475 intel_ddi_set_pipe_settings(pipe_config);
5476 if (!transcoder_is_dsi(cpu_transcoder))
5477 intel_ddi_enable_transcoder_func(pipe_config);
5478
5479 if (dev_priv->display.initial_watermarks != NULL)
5480 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5481
5482 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5483 if (!transcoder_is_dsi(cpu_transcoder))
5484 intel_enable_pipe(intel_crtc);
5485
5486 if (intel_crtc->config->has_pch_encoder)
5487 lpt_pch_enable(pipe_config);
5488
5489 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5490 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5491
5492 assert_vblank_disabled(crtc);
5493 drm_crtc_vblank_on(crtc);
5494
5495 intel_encoders_enable(crtc, pipe_config, old_state);
5496
5497 if (intel_crtc->config->has_pch_encoder) {
5498 intel_wait_for_vblank(dev_priv, pipe);
5499 intel_wait_for_vblank(dev_priv, pipe);
5500 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5501 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5502 true);
5503 }
5504
5505 /* If we change the relative order between pipe/planes enabling, we need
5506 * to change the workaround. */
5507 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5508 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5509 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5510 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5511 }
5512 }
5513
5514 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5515 {
5516 struct drm_device *dev = crtc->base.dev;
5517 struct drm_i915_private *dev_priv = to_i915(dev);
5518 int pipe = crtc->pipe;
5519
5520 /* To avoid upsetting the power well on haswell only disable the pfit if
5521 * it's in use. The hw state code will make sure we get this right. */
5522 if (force || crtc->config->pch_pfit.enabled) {
5523 I915_WRITE(PF_CTL(pipe), 0);
5524 I915_WRITE(PF_WIN_POS(pipe), 0);
5525 I915_WRITE(PF_WIN_SZ(pipe), 0);
5526 }
5527 }
5528
5529 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5530 struct drm_atomic_state *old_state)
5531 {
5532 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5533 struct drm_device *dev = crtc->dev;
5534 struct drm_i915_private *dev_priv = to_i915(dev);
5535 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5536 int pipe = intel_crtc->pipe;
5537
5538 /*
5539 * Sometimes spurious CPU pipe underruns happen when the
5540 * pipe is already disabled, but FDI RX/TX is still enabled.
5541 * Happens at least with VGA+HDMI cloning. Suppress them.
5542 */
5543 if (intel_crtc->config->has_pch_encoder) {
5544 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5545 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5546 }
5547
5548 intel_encoders_disable(crtc, old_crtc_state, old_state);
5549
5550 drm_crtc_vblank_off(crtc);
5551 assert_vblank_disabled(crtc);
5552
5553 intel_disable_pipe(intel_crtc);
5554
5555 ironlake_pfit_disable(intel_crtc, false);
5556
5557 if (intel_crtc->config->has_pch_encoder)
5558 ironlake_fdi_disable(crtc);
5559
5560 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5561
5562 if (intel_crtc->config->has_pch_encoder) {
5563 ironlake_disable_pch_transcoder(dev_priv, pipe);
5564
5565 if (HAS_PCH_CPT(dev_priv)) {
5566 i915_reg_t reg;
5567 u32 temp;
5568
5569 /* disable TRANS_DP_CTL */
5570 reg = TRANS_DP_CTL(pipe);
5571 temp = I915_READ(reg);
5572 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5573 TRANS_DP_PORT_SEL_MASK);
5574 temp |= TRANS_DP_PORT_SEL_NONE;
5575 I915_WRITE(reg, temp);
5576
5577 /* disable DPLL_SEL */
5578 temp = I915_READ(PCH_DPLL_SEL);
5579 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5580 I915_WRITE(PCH_DPLL_SEL, temp);
5581 }
5582
5583 ironlake_fdi_pll_disable(intel_crtc);
5584 }
5585
5586 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5587 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5588 }
5589
5590 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5591 struct drm_atomic_state *old_state)
5592 {
5593 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5594 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5596 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5597
5598 if (intel_crtc->config->has_pch_encoder)
5599 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5600 false);
5601
5602 intel_encoders_disable(crtc, old_crtc_state, old_state);
5603
5604 drm_crtc_vblank_off(crtc);
5605 assert_vblank_disabled(crtc);
5606
5607 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5608 if (!transcoder_is_dsi(cpu_transcoder))
5609 intel_disable_pipe(intel_crtc);
5610
5611 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5612 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5613
5614 if (!transcoder_is_dsi(cpu_transcoder))
5615 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5616
5617 if (INTEL_GEN(dev_priv) >= 9)
5618 skylake_scaler_disable(intel_crtc);
5619 else
5620 ironlake_pfit_disable(intel_crtc, false);
5621
5622 if (!transcoder_is_dsi(cpu_transcoder))
5623 intel_ddi_disable_pipe_clock(intel_crtc->config);
5624
5625 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5626
5627 if (old_crtc_state->has_pch_encoder)
5628 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5629 true);
5630 }
5631
5632 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5633 {
5634 struct drm_device *dev = crtc->base.dev;
5635 struct drm_i915_private *dev_priv = to_i915(dev);
5636 struct intel_crtc_state *pipe_config = crtc->config;
5637
5638 if (!pipe_config->gmch_pfit.control)
5639 return;
5640
5641 /*
5642 * The panel fitter should only be adjusted whilst the pipe is disabled,
5643 * according to register description and PRM.
5644 */
5645 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5646 assert_pipe_disabled(dev_priv, crtc->pipe);
5647
5648 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5649 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5650
5651 /* Border color in case we don't scale up to the full screen. Black by
5652 * default, change to something else for debugging. */
5653 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5654 }
5655
5656 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5657 {
5658 switch (port) {
5659 case PORT_A:
5660 return POWER_DOMAIN_PORT_DDI_A_LANES;
5661 case PORT_B:
5662 return POWER_DOMAIN_PORT_DDI_B_LANES;
5663 case PORT_C:
5664 return POWER_DOMAIN_PORT_DDI_C_LANES;
5665 case PORT_D:
5666 return POWER_DOMAIN_PORT_DDI_D_LANES;
5667 case PORT_E:
5668 return POWER_DOMAIN_PORT_DDI_E_LANES;
5669 default:
5670 MISSING_CASE(port);
5671 return POWER_DOMAIN_PORT_OTHER;
5672 }
5673 }
5674
5675 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5676 struct intel_crtc_state *crtc_state)
5677 {
5678 struct drm_device *dev = crtc->dev;
5679 struct drm_i915_private *dev_priv = to_i915(dev);
5680 struct drm_encoder *encoder;
5681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5682 enum pipe pipe = intel_crtc->pipe;
5683 u64 mask;
5684 enum transcoder transcoder = crtc_state->cpu_transcoder;
5685
5686 if (!crtc_state->base.active)
5687 return 0;
5688
5689 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5690 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5691 if (crtc_state->pch_pfit.enabled ||
5692 crtc_state->pch_pfit.force_thru)
5693 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5694
5695 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5696 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5697
5698 mask |= BIT_ULL(intel_encoder->power_domain);
5699 }
5700
5701 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5702 mask |= BIT(POWER_DOMAIN_AUDIO);
5703
5704 if (crtc_state->shared_dpll)
5705 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5706
5707 return mask;
5708 }
5709
5710 static u64
5711 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5712 struct intel_crtc_state *crtc_state)
5713 {
5714 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5715 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5716 enum intel_display_power_domain domain;
5717 u64 domains, new_domains, old_domains;
5718
5719 old_domains = intel_crtc->enabled_power_domains;
5720 intel_crtc->enabled_power_domains = new_domains =
5721 get_crtc_power_domains(crtc, crtc_state);
5722
5723 domains = new_domains & ~old_domains;
5724
5725 for_each_power_domain(domain, domains)
5726 intel_display_power_get(dev_priv, domain);
5727
5728 return old_domains & ~new_domains;
5729 }
5730
5731 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5732 u64 domains)
5733 {
5734 enum intel_display_power_domain domain;
5735
5736 for_each_power_domain(domain, domains)
5737 intel_display_power_put(dev_priv, domain);
5738 }
5739
5740 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5741 struct drm_atomic_state *old_state)
5742 {
5743 struct intel_atomic_state *old_intel_state =
5744 to_intel_atomic_state(old_state);
5745 struct drm_crtc *crtc = pipe_config->base.crtc;
5746 struct drm_device *dev = crtc->dev;
5747 struct drm_i915_private *dev_priv = to_i915(dev);
5748 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5749 int pipe = intel_crtc->pipe;
5750
5751 if (WARN_ON(intel_crtc->active))
5752 return;
5753
5754 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5755 intel_dp_set_m_n(intel_crtc, M1_N1);
5756
5757 intel_set_pipe_timings(intel_crtc);
5758 intel_set_pipe_src_size(intel_crtc);
5759
5760 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5761 struct drm_i915_private *dev_priv = to_i915(dev);
5762
5763 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5764 I915_WRITE(CHV_CANVAS(pipe), 0);
5765 }
5766
5767 i9xx_set_pipeconf(intel_crtc);
5768
5769 intel_crtc->active = true;
5770
5771 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5772
5773 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5774
5775 if (IS_CHERRYVIEW(dev_priv)) {
5776 chv_prepare_pll(intel_crtc, intel_crtc->config);
5777 chv_enable_pll(intel_crtc, intel_crtc->config);
5778 } else {
5779 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5780 vlv_enable_pll(intel_crtc, intel_crtc->config);
5781 }
5782
5783 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5784
5785 i9xx_pfit_enable(intel_crtc);
5786
5787 intel_color_load_luts(&pipe_config->base);
5788
5789 dev_priv->display.initial_watermarks(old_intel_state,
5790 pipe_config);
5791 intel_enable_pipe(intel_crtc);
5792
5793 assert_vblank_disabled(crtc);
5794 drm_crtc_vblank_on(crtc);
5795
5796 intel_encoders_enable(crtc, pipe_config, old_state);
5797 }
5798
5799 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5800 {
5801 struct drm_device *dev = crtc->base.dev;
5802 struct drm_i915_private *dev_priv = to_i915(dev);
5803
5804 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5805 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5806 }
5807
5808 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5809 struct drm_atomic_state *old_state)
5810 {
5811 struct drm_crtc *crtc = pipe_config->base.crtc;
5812 struct drm_device *dev = crtc->dev;
5813 struct drm_i915_private *dev_priv = to_i915(dev);
5814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5815 enum pipe pipe = intel_crtc->pipe;
5816
5817 if (WARN_ON(intel_crtc->active))
5818 return;
5819
5820 i9xx_set_pll_dividers(intel_crtc);
5821
5822 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5823 intel_dp_set_m_n(intel_crtc, M1_N1);
5824
5825 intel_set_pipe_timings(intel_crtc);
5826 intel_set_pipe_src_size(intel_crtc);
5827
5828 i9xx_set_pipeconf(intel_crtc);
5829
5830 intel_crtc->active = true;
5831
5832 if (!IS_GEN2(dev_priv))
5833 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5834
5835 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5836
5837 i9xx_enable_pll(intel_crtc);
5838
5839 i9xx_pfit_enable(intel_crtc);
5840
5841 intel_color_load_luts(&pipe_config->base);
5842
5843 intel_update_watermarks(intel_crtc);
5844 intel_enable_pipe(intel_crtc);
5845
5846 assert_vblank_disabled(crtc);
5847 drm_crtc_vblank_on(crtc);
5848
5849 intel_encoders_enable(crtc, pipe_config, old_state);
5850 }
5851
5852 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5853 {
5854 struct drm_device *dev = crtc->base.dev;
5855 struct drm_i915_private *dev_priv = to_i915(dev);
5856
5857 if (!crtc->config->gmch_pfit.control)
5858 return;
5859
5860 assert_pipe_disabled(dev_priv, crtc->pipe);
5861
5862 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5863 I915_READ(PFIT_CONTROL));
5864 I915_WRITE(PFIT_CONTROL, 0);
5865 }
5866
5867 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5868 struct drm_atomic_state *old_state)
5869 {
5870 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5871 struct drm_device *dev = crtc->dev;
5872 struct drm_i915_private *dev_priv = to_i915(dev);
5873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5874 int pipe = intel_crtc->pipe;
5875
5876 /*
5877 * On gen2 planes are double buffered but the pipe isn't, so we must
5878 * wait for planes to fully turn off before disabling the pipe.
5879 */
5880 if (IS_GEN2(dev_priv))
5881 intel_wait_for_vblank(dev_priv, pipe);
5882
5883 intel_encoders_disable(crtc, old_crtc_state, old_state);
5884
5885 drm_crtc_vblank_off(crtc);
5886 assert_vblank_disabled(crtc);
5887
5888 intel_disable_pipe(intel_crtc);
5889
5890 i9xx_pfit_disable(intel_crtc);
5891
5892 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5893
5894 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5895 if (IS_CHERRYVIEW(dev_priv))
5896 chv_disable_pll(dev_priv, pipe);
5897 else if (IS_VALLEYVIEW(dev_priv))
5898 vlv_disable_pll(dev_priv, pipe);
5899 else
5900 i9xx_disable_pll(intel_crtc);
5901 }
5902
5903 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5904
5905 if (!IS_GEN2(dev_priv))
5906 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5907
5908 if (!dev_priv->display.initial_watermarks)
5909 intel_update_watermarks(intel_crtc);
5910 }
5911
5912 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
5913 {
5914 struct intel_encoder *encoder;
5915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5916 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5917 enum intel_display_power_domain domain;
5918 u64 domains;
5919 struct drm_atomic_state *state;
5920 struct intel_crtc_state *crtc_state;
5921 int ret;
5922
5923 if (!intel_crtc->active)
5924 return;
5925
5926 if (crtc->primary->state->visible) {
5927 WARN_ON(intel_crtc->flip_work);
5928
5929 intel_pre_disable_primary_noatomic(crtc);
5930
5931 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5932 crtc->primary->state->visible = false;
5933 }
5934
5935 state = drm_atomic_state_alloc(crtc->dev);
5936 if (!state) {
5937 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5938 crtc->base.id, crtc->name);
5939 return;
5940 }
5941
5942 state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
5943
5944 /* Everything's already locked, -EDEADLK can't happen. */
5945 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5946 ret = drm_atomic_add_affected_connectors(state, crtc);
5947
5948 WARN_ON(IS_ERR(crtc_state) || ret);
5949
5950 dev_priv->display.crtc_disable(crtc_state, state);
5951
5952 drm_atomic_state_put(state);
5953
5954 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5955 crtc->base.id, crtc->name);
5956
5957 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5958 crtc->state->active = false;
5959 intel_crtc->active = false;
5960 crtc->enabled = false;
5961 crtc->state->connector_mask = 0;
5962 crtc->state->encoder_mask = 0;
5963
5964 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5965 encoder->base.crtc = NULL;
5966
5967 intel_fbc_disable(intel_crtc);
5968 intel_update_watermarks(intel_crtc);
5969 intel_disable_shared_dpll(intel_crtc);
5970
5971 domains = intel_crtc->enabled_power_domains;
5972 for_each_power_domain(domain, domains)
5973 intel_display_power_put(dev_priv, domain);
5974 intel_crtc->enabled_power_domains = 0;
5975
5976 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5977 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
5978 }
5979
5980 /*
5981 * turn all crtc's off, but do not adjust state
5982 * This has to be paired with a call to intel_modeset_setup_hw_state.
5983 */
5984 int intel_display_suspend(struct drm_device *dev)
5985 {
5986 struct drm_i915_private *dev_priv = to_i915(dev);
5987 struct drm_atomic_state *state;
5988 int ret;
5989
5990 state = drm_atomic_helper_suspend(dev);
5991 ret = PTR_ERR_OR_ZERO(state);
5992 if (ret)
5993 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5994 else
5995 dev_priv->modeset_restore_state = state;
5996 return ret;
5997 }
5998
5999 void intel_encoder_destroy(struct drm_encoder *encoder)
6000 {
6001 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6002
6003 drm_encoder_cleanup(encoder);
6004 kfree(intel_encoder);
6005 }
6006
6007 /* Cross check the actual hw state with our own modeset state tracking (and it's
6008 * internal consistency). */
6009 static void intel_connector_verify_state(struct intel_connector *connector)
6010 {
6011 struct drm_crtc *crtc = connector->base.state->crtc;
6012
6013 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6014 connector->base.base.id,
6015 connector->base.name);
6016
6017 if (connector->get_hw_state(connector)) {
6018 struct intel_encoder *encoder = connector->encoder;
6019 struct drm_connector_state *conn_state = connector->base.state;
6020
6021 I915_STATE_WARN(!crtc,
6022 "connector enabled without attached crtc\n");
6023
6024 if (!crtc)
6025 return;
6026
6027 I915_STATE_WARN(!crtc->state->active,
6028 "connector is active, but attached crtc isn't\n");
6029
6030 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6031 return;
6032
6033 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6034 "atomic encoder doesn't match attached encoder\n");
6035
6036 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6037 "attached encoder crtc differs from connector crtc\n");
6038 } else {
6039 I915_STATE_WARN(crtc && crtc->state->active,
6040 "attached crtc is active, but connector isn't\n");
6041 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6042 "best encoder set without crtc!\n");
6043 }
6044 }
6045
6046 int intel_connector_init(struct intel_connector *connector)
6047 {
6048 drm_atomic_helper_connector_reset(&connector->base);
6049
6050 if (!connector->base.state)
6051 return -ENOMEM;
6052
6053 return 0;
6054 }
6055
6056 struct intel_connector *intel_connector_alloc(void)
6057 {
6058 struct intel_connector *connector;
6059
6060 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6061 if (!connector)
6062 return NULL;
6063
6064 if (intel_connector_init(connector) < 0) {
6065 kfree(connector);
6066 return NULL;
6067 }
6068
6069 return connector;
6070 }
6071
6072 /* Simple connector->get_hw_state implementation for encoders that support only
6073 * one connector and no cloning and hence the encoder state determines the state
6074 * of the connector. */
6075 bool intel_connector_get_hw_state(struct intel_connector *connector)
6076 {
6077 enum pipe pipe = 0;
6078 struct intel_encoder *encoder = connector->encoder;
6079
6080 return encoder->get_hw_state(encoder, &pipe);
6081 }
6082
6083 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6084 {
6085 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6086 return crtc_state->fdi_lanes;
6087
6088 return 0;
6089 }
6090
6091 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6092 struct intel_crtc_state *pipe_config)
6093 {
6094 struct drm_i915_private *dev_priv = to_i915(dev);
6095 struct drm_atomic_state *state = pipe_config->base.state;
6096 struct intel_crtc *other_crtc;
6097 struct intel_crtc_state *other_crtc_state;
6098
6099 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6100 pipe_name(pipe), pipe_config->fdi_lanes);
6101 if (pipe_config->fdi_lanes > 4) {
6102 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6103 pipe_name(pipe), pipe_config->fdi_lanes);
6104 return -EINVAL;
6105 }
6106
6107 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6108 if (pipe_config->fdi_lanes > 2) {
6109 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6110 pipe_config->fdi_lanes);
6111 return -EINVAL;
6112 } else {
6113 return 0;
6114 }
6115 }
6116
6117 if (INTEL_INFO(dev_priv)->num_pipes == 2)
6118 return 0;
6119
6120 /* Ivybridge 3 pipe is really complicated */
6121 switch (pipe) {
6122 case PIPE_A:
6123 return 0;
6124 case PIPE_B:
6125 if (pipe_config->fdi_lanes <= 2)
6126 return 0;
6127
6128 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6129 other_crtc_state =
6130 intel_atomic_get_crtc_state(state, other_crtc);
6131 if (IS_ERR(other_crtc_state))
6132 return PTR_ERR(other_crtc_state);
6133
6134 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6135 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6136 pipe_name(pipe), pipe_config->fdi_lanes);
6137 return -EINVAL;
6138 }
6139 return 0;
6140 case PIPE_C:
6141 if (pipe_config->fdi_lanes > 2) {
6142 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6143 pipe_name(pipe), pipe_config->fdi_lanes);
6144 return -EINVAL;
6145 }
6146
6147 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6148 other_crtc_state =
6149 intel_atomic_get_crtc_state(state, other_crtc);
6150 if (IS_ERR(other_crtc_state))
6151 return PTR_ERR(other_crtc_state);
6152
6153 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6154 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6155 return -EINVAL;
6156 }
6157 return 0;
6158 default:
6159 BUG();
6160 }
6161 }
6162
6163 #define RETRY 1
6164 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6165 struct intel_crtc_state *pipe_config)
6166 {
6167 struct drm_device *dev = intel_crtc->base.dev;
6168 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6169 int lane, link_bw, fdi_dotclock, ret;
6170 bool needs_recompute = false;
6171
6172 retry:
6173 /* FDI is a binary signal running at ~2.7GHz, encoding
6174 * each output octet as 10 bits. The actual frequency
6175 * is stored as a divider into a 100MHz clock, and the
6176 * mode pixel clock is stored in units of 1KHz.
6177 * Hence the bw of each lane in terms of the mode signal
6178 * is:
6179 */
6180 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6181
6182 fdi_dotclock = adjusted_mode->crtc_clock;
6183
6184 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6185 pipe_config->pipe_bpp);
6186
6187 pipe_config->fdi_lanes = lane;
6188
6189 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6190 link_bw, &pipe_config->fdi_m_n);
6191
6192 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6193 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6194 pipe_config->pipe_bpp -= 2*3;
6195 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6196 pipe_config->pipe_bpp);
6197 needs_recompute = true;
6198 pipe_config->bw_constrained = true;
6199
6200 goto retry;
6201 }
6202
6203 if (needs_recompute)
6204 return RETRY;
6205
6206 return ret;
6207 }
6208
6209 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6210 struct intel_crtc_state *pipe_config)
6211 {
6212 if (pipe_config->pipe_bpp > 24)
6213 return false;
6214
6215 /* HSW can handle pixel rate up to cdclk? */
6216 if (IS_HASWELL(dev_priv))
6217 return true;
6218
6219 /*
6220 * We compare against max which means we must take
6221 * the increased cdclk requirement into account when
6222 * calculating the new cdclk.
6223 *
6224 * Should measure whether using a lower cdclk w/o IPS
6225 */
6226 return pipe_config->pixel_rate <=
6227 dev_priv->max_cdclk_freq * 95 / 100;
6228 }
6229
6230 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6231 struct intel_crtc_state *pipe_config)
6232 {
6233 struct drm_device *dev = crtc->base.dev;
6234 struct drm_i915_private *dev_priv = to_i915(dev);
6235
6236 pipe_config->ips_enabled = i915.enable_ips &&
6237 hsw_crtc_supports_ips(crtc) &&
6238 pipe_config_supports_ips(dev_priv, pipe_config);
6239 }
6240
6241 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6242 {
6243 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6244
6245 /* GDG double wide on either pipe, otherwise pipe A only */
6246 return INTEL_INFO(dev_priv)->gen < 4 &&
6247 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6248 }
6249
6250 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6251 {
6252 uint32_t pixel_rate;
6253
6254 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6255
6256 /*
6257 * We only use IF-ID interlacing. If we ever use
6258 * PF-ID we'll need to adjust the pixel_rate here.
6259 */
6260
6261 if (pipe_config->pch_pfit.enabled) {
6262 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6263 uint32_t pfit_size = pipe_config->pch_pfit.size;
6264
6265 pipe_w = pipe_config->pipe_src_w;
6266 pipe_h = pipe_config->pipe_src_h;
6267
6268 pfit_w = (pfit_size >> 16) & 0xFFFF;
6269 pfit_h = pfit_size & 0xFFFF;
6270 if (pipe_w < pfit_w)
6271 pipe_w = pfit_w;
6272 if (pipe_h < pfit_h)
6273 pipe_h = pfit_h;
6274
6275 if (WARN_ON(!pfit_w || !pfit_h))
6276 return pixel_rate;
6277
6278 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6279 pfit_w * pfit_h);
6280 }
6281
6282 return pixel_rate;
6283 }
6284
6285 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6286 {
6287 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6288
6289 if (HAS_GMCH_DISPLAY(dev_priv))
6290 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6291 crtc_state->pixel_rate =
6292 crtc_state->base.adjusted_mode.crtc_clock;
6293 else
6294 crtc_state->pixel_rate =
6295 ilk_pipe_pixel_rate(crtc_state);
6296 }
6297
6298 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6299 struct intel_crtc_state *pipe_config)
6300 {
6301 struct drm_device *dev = crtc->base.dev;
6302 struct drm_i915_private *dev_priv = to_i915(dev);
6303 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6304 int clock_limit = dev_priv->max_dotclk_freq;
6305
6306 if (INTEL_GEN(dev_priv) < 4) {
6307 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6308
6309 /*
6310 * Enable double wide mode when the dot clock
6311 * is > 90% of the (display) core speed.
6312 */
6313 if (intel_crtc_supports_double_wide(crtc) &&
6314 adjusted_mode->crtc_clock > clock_limit) {
6315 clock_limit = dev_priv->max_dotclk_freq;
6316 pipe_config->double_wide = true;
6317 }
6318 }
6319
6320 if (adjusted_mode->crtc_clock > clock_limit) {
6321 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6322 adjusted_mode->crtc_clock, clock_limit,
6323 yesno(pipe_config->double_wide));
6324 return -EINVAL;
6325 }
6326
6327 /*
6328 * Pipe horizontal size must be even in:
6329 * - DVO ganged mode
6330 * - LVDS dual channel mode
6331 * - Double wide pipe
6332 */
6333 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6334 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6335 pipe_config->pipe_src_w &= ~1;
6336
6337 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6338 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6339 */
6340 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6341 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6342 return -EINVAL;
6343
6344 intel_crtc_compute_pixel_rate(pipe_config);
6345
6346 if (HAS_IPS(dev_priv))
6347 hsw_compute_ips_config(crtc, pipe_config);
6348
6349 if (pipe_config->has_pch_encoder)
6350 return ironlake_fdi_compute_config(crtc, pipe_config);
6351
6352 return 0;
6353 }
6354
6355 static void
6356 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6357 {
6358 while (*num > DATA_LINK_M_N_MASK ||
6359 *den > DATA_LINK_M_N_MASK) {
6360 *num >>= 1;
6361 *den >>= 1;
6362 }
6363 }
6364
6365 static void compute_m_n(unsigned int m, unsigned int n,
6366 uint32_t *ret_m, uint32_t *ret_n)
6367 {
6368 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6369 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6370 intel_reduce_m_n_ratio(ret_m, ret_n);
6371 }
6372
6373 void
6374 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6375 int pixel_clock, int link_clock,
6376 struct intel_link_m_n *m_n)
6377 {
6378 m_n->tu = 64;
6379
6380 compute_m_n(bits_per_pixel * pixel_clock,
6381 link_clock * nlanes * 8,
6382 &m_n->gmch_m, &m_n->gmch_n);
6383
6384 compute_m_n(pixel_clock, link_clock,
6385 &m_n->link_m, &m_n->link_n);
6386 }
6387
6388 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6389 {
6390 if (i915.panel_use_ssc >= 0)
6391 return i915.panel_use_ssc != 0;
6392 return dev_priv->vbt.lvds_use_ssc
6393 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6394 }
6395
6396 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6397 {
6398 return (1 << dpll->n) << 16 | dpll->m2;
6399 }
6400
6401 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6402 {
6403 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6404 }
6405
6406 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6407 struct intel_crtc_state *crtc_state,
6408 struct dpll *reduced_clock)
6409 {
6410 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6411 u32 fp, fp2 = 0;
6412
6413 if (IS_PINEVIEW(dev_priv)) {
6414 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6415 if (reduced_clock)
6416 fp2 = pnv_dpll_compute_fp(reduced_clock);
6417 } else {
6418 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6419 if (reduced_clock)
6420 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6421 }
6422
6423 crtc_state->dpll_hw_state.fp0 = fp;
6424
6425 crtc->lowfreq_avail = false;
6426 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6427 reduced_clock) {
6428 crtc_state->dpll_hw_state.fp1 = fp2;
6429 crtc->lowfreq_avail = true;
6430 } else {
6431 crtc_state->dpll_hw_state.fp1 = fp;
6432 }
6433 }
6434
6435 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6436 pipe)
6437 {
6438 u32 reg_val;
6439
6440 /*
6441 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6442 * and set it to a reasonable value instead.
6443 */
6444 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6445 reg_val &= 0xffffff00;
6446 reg_val |= 0x00000030;
6447 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6448
6449 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6450 reg_val &= 0x8cffffff;
6451 reg_val = 0x8c000000;
6452 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6453
6454 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6455 reg_val &= 0xffffff00;
6456 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6457
6458 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6459 reg_val &= 0x00ffffff;
6460 reg_val |= 0xb0000000;
6461 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6462 }
6463
6464 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6465 struct intel_link_m_n *m_n)
6466 {
6467 struct drm_device *dev = crtc->base.dev;
6468 struct drm_i915_private *dev_priv = to_i915(dev);
6469 int pipe = crtc->pipe;
6470
6471 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6472 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6473 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6474 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6475 }
6476
6477 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6478 struct intel_link_m_n *m_n,
6479 struct intel_link_m_n *m2_n2)
6480 {
6481 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6482 int pipe = crtc->pipe;
6483 enum transcoder transcoder = crtc->config->cpu_transcoder;
6484
6485 if (INTEL_GEN(dev_priv) >= 5) {
6486 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6487 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6488 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6489 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6490 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6491 * for gen < 8) and if DRRS is supported (to make sure the
6492 * registers are not unnecessarily accessed).
6493 */
6494 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6495 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6496 I915_WRITE(PIPE_DATA_M2(transcoder),
6497 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6498 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6499 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6500 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6501 }
6502 } else {
6503 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6504 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6505 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6506 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6507 }
6508 }
6509
6510 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6511 {
6512 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6513
6514 if (m_n == M1_N1) {
6515 dp_m_n = &crtc->config->dp_m_n;
6516 dp_m2_n2 = &crtc->config->dp_m2_n2;
6517 } else if (m_n == M2_N2) {
6518
6519 /*
6520 * M2_N2 registers are not supported. Hence m2_n2 divider value
6521 * needs to be programmed into M1_N1.
6522 */
6523 dp_m_n = &crtc->config->dp_m2_n2;
6524 } else {
6525 DRM_ERROR("Unsupported divider value\n");
6526 return;
6527 }
6528
6529 if (crtc->config->has_pch_encoder)
6530 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6531 else
6532 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6533 }
6534
6535 static void vlv_compute_dpll(struct intel_crtc *crtc,
6536 struct intel_crtc_state *pipe_config)
6537 {
6538 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6539 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6540 if (crtc->pipe != PIPE_A)
6541 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6542
6543 /* DPLL not used with DSI, but still need the rest set up */
6544 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6545 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6546 DPLL_EXT_BUFFER_ENABLE_VLV;
6547
6548 pipe_config->dpll_hw_state.dpll_md =
6549 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6550 }
6551
6552 static void chv_compute_dpll(struct intel_crtc *crtc,
6553 struct intel_crtc_state *pipe_config)
6554 {
6555 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6556 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6557 if (crtc->pipe != PIPE_A)
6558 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6559
6560 /* DPLL not used with DSI, but still need the rest set up */
6561 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6562 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6563
6564 pipe_config->dpll_hw_state.dpll_md =
6565 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6566 }
6567
6568 static void vlv_prepare_pll(struct intel_crtc *crtc,
6569 const struct intel_crtc_state *pipe_config)
6570 {
6571 struct drm_device *dev = crtc->base.dev;
6572 struct drm_i915_private *dev_priv = to_i915(dev);
6573 enum pipe pipe = crtc->pipe;
6574 u32 mdiv;
6575 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6576 u32 coreclk, reg_val;
6577
6578 /* Enable Refclk */
6579 I915_WRITE(DPLL(pipe),
6580 pipe_config->dpll_hw_state.dpll &
6581 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6582
6583 /* No need to actually set up the DPLL with DSI */
6584 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6585 return;
6586
6587 mutex_lock(&dev_priv->sb_lock);
6588
6589 bestn = pipe_config->dpll.n;
6590 bestm1 = pipe_config->dpll.m1;
6591 bestm2 = pipe_config->dpll.m2;
6592 bestp1 = pipe_config->dpll.p1;
6593 bestp2 = pipe_config->dpll.p2;
6594
6595 /* See eDP HDMI DPIO driver vbios notes doc */
6596
6597 /* PLL B needs special handling */
6598 if (pipe == PIPE_B)
6599 vlv_pllb_recal_opamp(dev_priv, pipe);
6600
6601 /* Set up Tx target for periodic Rcomp update */
6602 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6603
6604 /* Disable target IRef on PLL */
6605 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6606 reg_val &= 0x00ffffff;
6607 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6608
6609 /* Disable fast lock */
6610 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6611
6612 /* Set idtafcrecal before PLL is enabled */
6613 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6614 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6615 mdiv |= ((bestn << DPIO_N_SHIFT));
6616 mdiv |= (1 << DPIO_K_SHIFT);
6617
6618 /*
6619 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6620 * but we don't support that).
6621 * Note: don't use the DAC post divider as it seems unstable.
6622 */
6623 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6624 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6625
6626 mdiv |= DPIO_ENABLE_CALIBRATION;
6627 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6628
6629 /* Set HBR and RBR LPF coefficients */
6630 if (pipe_config->port_clock == 162000 ||
6631 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6632 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6633 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6634 0x009f0003);
6635 else
6636 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6637 0x00d0000f);
6638
6639 if (intel_crtc_has_dp_encoder(pipe_config)) {
6640 /* Use SSC source */
6641 if (pipe == PIPE_A)
6642 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6643 0x0df40000);
6644 else
6645 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6646 0x0df70000);
6647 } else { /* HDMI or VGA */
6648 /* Use bend source */
6649 if (pipe == PIPE_A)
6650 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6651 0x0df70000);
6652 else
6653 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6654 0x0df40000);
6655 }
6656
6657 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6658 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6659 if (intel_crtc_has_dp_encoder(crtc->config))
6660 coreclk |= 0x01000000;
6661 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6662
6663 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6664 mutex_unlock(&dev_priv->sb_lock);
6665 }
6666
6667 static void chv_prepare_pll(struct intel_crtc *crtc,
6668 const struct intel_crtc_state *pipe_config)
6669 {
6670 struct drm_device *dev = crtc->base.dev;
6671 struct drm_i915_private *dev_priv = to_i915(dev);
6672 enum pipe pipe = crtc->pipe;
6673 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6674 u32 loopfilter, tribuf_calcntr;
6675 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6676 u32 dpio_val;
6677 int vco;
6678
6679 /* Enable Refclk and SSC */
6680 I915_WRITE(DPLL(pipe),
6681 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6682
6683 /* No need to actually set up the DPLL with DSI */
6684 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6685 return;
6686
6687 bestn = pipe_config->dpll.n;
6688 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6689 bestm1 = pipe_config->dpll.m1;
6690 bestm2 = pipe_config->dpll.m2 >> 22;
6691 bestp1 = pipe_config->dpll.p1;
6692 bestp2 = pipe_config->dpll.p2;
6693 vco = pipe_config->dpll.vco;
6694 dpio_val = 0;
6695 loopfilter = 0;
6696
6697 mutex_lock(&dev_priv->sb_lock);
6698
6699 /* p1 and p2 divider */
6700 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6701 5 << DPIO_CHV_S1_DIV_SHIFT |
6702 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6703 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6704 1 << DPIO_CHV_K_DIV_SHIFT);
6705
6706 /* Feedback post-divider - m2 */
6707 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6708
6709 /* Feedback refclk divider - n and m1 */
6710 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6711 DPIO_CHV_M1_DIV_BY_2 |
6712 1 << DPIO_CHV_N_DIV_SHIFT);
6713
6714 /* M2 fraction division */
6715 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6716
6717 /* M2 fraction division enable */
6718 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6719 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6720 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6721 if (bestm2_frac)
6722 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6723 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6724
6725 /* Program digital lock detect threshold */
6726 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6727 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6728 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6729 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6730 if (!bestm2_frac)
6731 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6732 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6733
6734 /* Loop filter */
6735 if (vco == 5400000) {
6736 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6737 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6738 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6739 tribuf_calcntr = 0x9;
6740 } else if (vco <= 6200000) {
6741 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6742 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6743 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6744 tribuf_calcntr = 0x9;
6745 } else if (vco <= 6480000) {
6746 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6747 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6748 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6749 tribuf_calcntr = 0x8;
6750 } else {
6751 /* Not supported. Apply the same limits as in the max case */
6752 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6753 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6754 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6755 tribuf_calcntr = 0;
6756 }
6757 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6758
6759 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6760 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6761 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6762 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6763
6764 /* AFC Recal */
6765 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6766 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6767 DPIO_AFC_RECAL);
6768
6769 mutex_unlock(&dev_priv->sb_lock);
6770 }
6771
6772 /**
6773 * vlv_force_pll_on - forcibly enable just the PLL
6774 * @dev_priv: i915 private structure
6775 * @pipe: pipe PLL to enable
6776 * @dpll: PLL configuration
6777 *
6778 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6779 * in cases where we need the PLL enabled even when @pipe is not going to
6780 * be enabled.
6781 */
6782 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6783 const struct dpll *dpll)
6784 {
6785 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6786 struct intel_crtc_state *pipe_config;
6787
6788 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6789 if (!pipe_config)
6790 return -ENOMEM;
6791
6792 pipe_config->base.crtc = &crtc->base;
6793 pipe_config->pixel_multiplier = 1;
6794 pipe_config->dpll = *dpll;
6795
6796 if (IS_CHERRYVIEW(dev_priv)) {
6797 chv_compute_dpll(crtc, pipe_config);
6798 chv_prepare_pll(crtc, pipe_config);
6799 chv_enable_pll(crtc, pipe_config);
6800 } else {
6801 vlv_compute_dpll(crtc, pipe_config);
6802 vlv_prepare_pll(crtc, pipe_config);
6803 vlv_enable_pll(crtc, pipe_config);
6804 }
6805
6806 kfree(pipe_config);
6807
6808 return 0;
6809 }
6810
6811 /**
6812 * vlv_force_pll_off - forcibly disable just the PLL
6813 * @dev_priv: i915 private structure
6814 * @pipe: pipe PLL to disable
6815 *
6816 * Disable the PLL for @pipe. To be used in cases where we need
6817 * the PLL enabled even when @pipe is not going to be enabled.
6818 */
6819 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6820 {
6821 if (IS_CHERRYVIEW(dev_priv))
6822 chv_disable_pll(dev_priv, pipe);
6823 else
6824 vlv_disable_pll(dev_priv, pipe);
6825 }
6826
6827 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6828 struct intel_crtc_state *crtc_state,
6829 struct dpll *reduced_clock)
6830 {
6831 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6832 u32 dpll;
6833 struct dpll *clock = &crtc_state->dpll;
6834
6835 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6836
6837 dpll = DPLL_VGA_MODE_DIS;
6838
6839 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6840 dpll |= DPLLB_MODE_LVDS;
6841 else
6842 dpll |= DPLLB_MODE_DAC_SERIAL;
6843
6844 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6845 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6846 dpll |= (crtc_state->pixel_multiplier - 1)
6847 << SDVO_MULTIPLIER_SHIFT_HIRES;
6848 }
6849
6850 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6851 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6852 dpll |= DPLL_SDVO_HIGH_SPEED;
6853
6854 if (intel_crtc_has_dp_encoder(crtc_state))
6855 dpll |= DPLL_SDVO_HIGH_SPEED;
6856
6857 /* compute bitmask from p1 value */
6858 if (IS_PINEVIEW(dev_priv))
6859 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6860 else {
6861 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6862 if (IS_G4X(dev_priv) && reduced_clock)
6863 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6864 }
6865 switch (clock->p2) {
6866 case 5:
6867 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6868 break;
6869 case 7:
6870 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6871 break;
6872 case 10:
6873 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6874 break;
6875 case 14:
6876 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6877 break;
6878 }
6879 if (INTEL_GEN(dev_priv) >= 4)
6880 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6881
6882 if (crtc_state->sdvo_tv_clock)
6883 dpll |= PLL_REF_INPUT_TVCLKINBC;
6884 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6885 intel_panel_use_ssc(dev_priv))
6886 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6887 else
6888 dpll |= PLL_REF_INPUT_DREFCLK;
6889
6890 dpll |= DPLL_VCO_ENABLE;
6891 crtc_state->dpll_hw_state.dpll = dpll;
6892
6893 if (INTEL_GEN(dev_priv) >= 4) {
6894 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6895 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6896 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6897 }
6898 }
6899
6900 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6901 struct intel_crtc_state *crtc_state,
6902 struct dpll *reduced_clock)
6903 {
6904 struct drm_device *dev = crtc->base.dev;
6905 struct drm_i915_private *dev_priv = to_i915(dev);
6906 u32 dpll;
6907 struct dpll *clock = &crtc_state->dpll;
6908
6909 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6910
6911 dpll = DPLL_VGA_MODE_DIS;
6912
6913 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6914 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6915 } else {
6916 if (clock->p1 == 2)
6917 dpll |= PLL_P1_DIVIDE_BY_TWO;
6918 else
6919 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6920 if (clock->p2 == 4)
6921 dpll |= PLL_P2_DIVIDE_BY_4;
6922 }
6923
6924 if (!IS_I830(dev_priv) &&
6925 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6926 dpll |= DPLL_DVO_2X_MODE;
6927
6928 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6929 intel_panel_use_ssc(dev_priv))
6930 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6931 else
6932 dpll |= PLL_REF_INPUT_DREFCLK;
6933
6934 dpll |= DPLL_VCO_ENABLE;
6935 crtc_state->dpll_hw_state.dpll = dpll;
6936 }
6937
6938 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6939 {
6940 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6941 enum pipe pipe = intel_crtc->pipe;
6942 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6943 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6944 uint32_t crtc_vtotal, crtc_vblank_end;
6945 int vsyncshift = 0;
6946
6947 /* We need to be careful not to changed the adjusted mode, for otherwise
6948 * the hw state checker will get angry at the mismatch. */
6949 crtc_vtotal = adjusted_mode->crtc_vtotal;
6950 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6951
6952 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6953 /* the chip adds 2 halflines automatically */
6954 crtc_vtotal -= 1;
6955 crtc_vblank_end -= 1;
6956
6957 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6958 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6959 else
6960 vsyncshift = adjusted_mode->crtc_hsync_start -
6961 adjusted_mode->crtc_htotal / 2;
6962 if (vsyncshift < 0)
6963 vsyncshift += adjusted_mode->crtc_htotal;
6964 }
6965
6966 if (INTEL_GEN(dev_priv) > 3)
6967 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6968
6969 I915_WRITE(HTOTAL(cpu_transcoder),
6970 (adjusted_mode->crtc_hdisplay - 1) |
6971 ((adjusted_mode->crtc_htotal - 1) << 16));
6972 I915_WRITE(HBLANK(cpu_transcoder),
6973 (adjusted_mode->crtc_hblank_start - 1) |
6974 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6975 I915_WRITE(HSYNC(cpu_transcoder),
6976 (adjusted_mode->crtc_hsync_start - 1) |
6977 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6978
6979 I915_WRITE(VTOTAL(cpu_transcoder),
6980 (adjusted_mode->crtc_vdisplay - 1) |
6981 ((crtc_vtotal - 1) << 16));
6982 I915_WRITE(VBLANK(cpu_transcoder),
6983 (adjusted_mode->crtc_vblank_start - 1) |
6984 ((crtc_vblank_end - 1) << 16));
6985 I915_WRITE(VSYNC(cpu_transcoder),
6986 (adjusted_mode->crtc_vsync_start - 1) |
6987 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6988
6989 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6990 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6991 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6992 * bits. */
6993 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
6994 (pipe == PIPE_B || pipe == PIPE_C))
6995 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6996
6997 }
6998
6999 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7000 {
7001 struct drm_device *dev = intel_crtc->base.dev;
7002 struct drm_i915_private *dev_priv = to_i915(dev);
7003 enum pipe pipe = intel_crtc->pipe;
7004
7005 /* pipesrc controls the size that is scaled from, which should
7006 * always be the user's requested size.
7007 */
7008 I915_WRITE(PIPESRC(pipe),
7009 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7010 (intel_crtc->config->pipe_src_h - 1));
7011 }
7012
7013 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7014 struct intel_crtc_state *pipe_config)
7015 {
7016 struct drm_device *dev = crtc->base.dev;
7017 struct drm_i915_private *dev_priv = to_i915(dev);
7018 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7019 uint32_t tmp;
7020
7021 tmp = I915_READ(HTOTAL(cpu_transcoder));
7022 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7023 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7024 tmp = I915_READ(HBLANK(cpu_transcoder));
7025 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7026 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7027 tmp = I915_READ(HSYNC(cpu_transcoder));
7028 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7029 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7030
7031 tmp = I915_READ(VTOTAL(cpu_transcoder));
7032 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7033 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7034 tmp = I915_READ(VBLANK(cpu_transcoder));
7035 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7036 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7037 tmp = I915_READ(VSYNC(cpu_transcoder));
7038 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7039 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7040
7041 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7042 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7043 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7044 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7045 }
7046 }
7047
7048 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7049 struct intel_crtc_state *pipe_config)
7050 {
7051 struct drm_device *dev = crtc->base.dev;
7052 struct drm_i915_private *dev_priv = to_i915(dev);
7053 u32 tmp;
7054
7055 tmp = I915_READ(PIPESRC(crtc->pipe));
7056 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7057 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7058
7059 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7060 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7061 }
7062
7063 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7064 struct intel_crtc_state *pipe_config)
7065 {
7066 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7067 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7068 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7069 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7070
7071 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7072 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7073 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7074 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7075
7076 mode->flags = pipe_config->base.adjusted_mode.flags;
7077 mode->type = DRM_MODE_TYPE_DRIVER;
7078
7079 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7080
7081 mode->hsync = drm_mode_hsync(mode);
7082 mode->vrefresh = drm_mode_vrefresh(mode);
7083 drm_mode_set_name(mode);
7084 }
7085
7086 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7087 {
7088 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7089 uint32_t pipeconf;
7090
7091 pipeconf = 0;
7092
7093 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7094 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7095 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7096
7097 if (intel_crtc->config->double_wide)
7098 pipeconf |= PIPECONF_DOUBLE_WIDE;
7099
7100 /* only g4x and later have fancy bpc/dither controls */
7101 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7102 IS_CHERRYVIEW(dev_priv)) {
7103 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7104 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7105 pipeconf |= PIPECONF_DITHER_EN |
7106 PIPECONF_DITHER_TYPE_SP;
7107
7108 switch (intel_crtc->config->pipe_bpp) {
7109 case 18:
7110 pipeconf |= PIPECONF_6BPC;
7111 break;
7112 case 24:
7113 pipeconf |= PIPECONF_8BPC;
7114 break;
7115 case 30:
7116 pipeconf |= PIPECONF_10BPC;
7117 break;
7118 default:
7119 /* Case prevented by intel_choose_pipe_bpp_dither. */
7120 BUG();
7121 }
7122 }
7123
7124 if (HAS_PIPE_CXSR(dev_priv)) {
7125 if (intel_crtc->lowfreq_avail) {
7126 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7127 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7128 } else {
7129 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7130 }
7131 }
7132
7133 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7134 if (INTEL_GEN(dev_priv) < 4 ||
7135 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7136 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7137 else
7138 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7139 } else
7140 pipeconf |= PIPECONF_PROGRESSIVE;
7141
7142 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7143 intel_crtc->config->limited_color_range)
7144 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7145
7146 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7147 POSTING_READ(PIPECONF(intel_crtc->pipe));
7148 }
7149
7150 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7151 struct intel_crtc_state *crtc_state)
7152 {
7153 struct drm_device *dev = crtc->base.dev;
7154 struct drm_i915_private *dev_priv = to_i915(dev);
7155 const struct intel_limit *limit;
7156 int refclk = 48000;
7157
7158 memset(&crtc_state->dpll_hw_state, 0,
7159 sizeof(crtc_state->dpll_hw_state));
7160
7161 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7162 if (intel_panel_use_ssc(dev_priv)) {
7163 refclk = dev_priv->vbt.lvds_ssc_freq;
7164 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7165 }
7166
7167 limit = &intel_limits_i8xx_lvds;
7168 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7169 limit = &intel_limits_i8xx_dvo;
7170 } else {
7171 limit = &intel_limits_i8xx_dac;
7172 }
7173
7174 if (!crtc_state->clock_set &&
7175 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7176 refclk, NULL, &crtc_state->dpll)) {
7177 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7178 return -EINVAL;
7179 }
7180
7181 i8xx_compute_dpll(crtc, crtc_state, NULL);
7182
7183 return 0;
7184 }
7185
7186 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7187 struct intel_crtc_state *crtc_state)
7188 {
7189 struct drm_device *dev = crtc->base.dev;
7190 struct drm_i915_private *dev_priv = to_i915(dev);
7191 const struct intel_limit *limit;
7192 int refclk = 96000;
7193
7194 memset(&crtc_state->dpll_hw_state, 0,
7195 sizeof(crtc_state->dpll_hw_state));
7196
7197 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7198 if (intel_panel_use_ssc(dev_priv)) {
7199 refclk = dev_priv->vbt.lvds_ssc_freq;
7200 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7201 }
7202
7203 if (intel_is_dual_link_lvds(dev))
7204 limit = &intel_limits_g4x_dual_channel_lvds;
7205 else
7206 limit = &intel_limits_g4x_single_channel_lvds;
7207 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7208 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7209 limit = &intel_limits_g4x_hdmi;
7210 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7211 limit = &intel_limits_g4x_sdvo;
7212 } else {
7213 /* The option is for other outputs */
7214 limit = &intel_limits_i9xx_sdvo;
7215 }
7216
7217 if (!crtc_state->clock_set &&
7218 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7219 refclk, NULL, &crtc_state->dpll)) {
7220 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7221 return -EINVAL;
7222 }
7223
7224 i9xx_compute_dpll(crtc, crtc_state, NULL);
7225
7226 return 0;
7227 }
7228
7229 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7230 struct intel_crtc_state *crtc_state)
7231 {
7232 struct drm_device *dev = crtc->base.dev;
7233 struct drm_i915_private *dev_priv = to_i915(dev);
7234 const struct intel_limit *limit;
7235 int refclk = 96000;
7236
7237 memset(&crtc_state->dpll_hw_state, 0,
7238 sizeof(crtc_state->dpll_hw_state));
7239
7240 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7241 if (intel_panel_use_ssc(dev_priv)) {
7242 refclk = dev_priv->vbt.lvds_ssc_freq;
7243 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7244 }
7245
7246 limit = &intel_limits_pineview_lvds;
7247 } else {
7248 limit = &intel_limits_pineview_sdvo;
7249 }
7250
7251 if (!crtc_state->clock_set &&
7252 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7253 refclk, NULL, &crtc_state->dpll)) {
7254 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7255 return -EINVAL;
7256 }
7257
7258 i9xx_compute_dpll(crtc, crtc_state, NULL);
7259
7260 return 0;
7261 }
7262
7263 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7264 struct intel_crtc_state *crtc_state)
7265 {
7266 struct drm_device *dev = crtc->base.dev;
7267 struct drm_i915_private *dev_priv = to_i915(dev);
7268 const struct intel_limit *limit;
7269 int refclk = 96000;
7270
7271 memset(&crtc_state->dpll_hw_state, 0,
7272 sizeof(crtc_state->dpll_hw_state));
7273
7274 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7275 if (intel_panel_use_ssc(dev_priv)) {
7276 refclk = dev_priv->vbt.lvds_ssc_freq;
7277 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7278 }
7279
7280 limit = &intel_limits_i9xx_lvds;
7281 } else {
7282 limit = &intel_limits_i9xx_sdvo;
7283 }
7284
7285 if (!crtc_state->clock_set &&
7286 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7287 refclk, NULL, &crtc_state->dpll)) {
7288 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7289 return -EINVAL;
7290 }
7291
7292 i9xx_compute_dpll(crtc, crtc_state, NULL);
7293
7294 return 0;
7295 }
7296
7297 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7298 struct intel_crtc_state *crtc_state)
7299 {
7300 int refclk = 100000;
7301 const struct intel_limit *limit = &intel_limits_chv;
7302
7303 memset(&crtc_state->dpll_hw_state, 0,
7304 sizeof(crtc_state->dpll_hw_state));
7305
7306 if (!crtc_state->clock_set &&
7307 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7308 refclk, NULL, &crtc_state->dpll)) {
7309 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7310 return -EINVAL;
7311 }
7312
7313 chv_compute_dpll(crtc, crtc_state);
7314
7315 return 0;
7316 }
7317
7318 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7319 struct intel_crtc_state *crtc_state)
7320 {
7321 int refclk = 100000;
7322 const struct intel_limit *limit = &intel_limits_vlv;
7323
7324 memset(&crtc_state->dpll_hw_state, 0,
7325 sizeof(crtc_state->dpll_hw_state));
7326
7327 if (!crtc_state->clock_set &&
7328 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7329 refclk, NULL, &crtc_state->dpll)) {
7330 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7331 return -EINVAL;
7332 }
7333
7334 vlv_compute_dpll(crtc, crtc_state);
7335
7336 return 0;
7337 }
7338
7339 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7340 struct intel_crtc_state *pipe_config)
7341 {
7342 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7343 uint32_t tmp;
7344
7345 if (INTEL_GEN(dev_priv) <= 3 &&
7346 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7347 return;
7348
7349 tmp = I915_READ(PFIT_CONTROL);
7350 if (!(tmp & PFIT_ENABLE))
7351 return;
7352
7353 /* Check whether the pfit is attached to our pipe. */
7354 if (INTEL_GEN(dev_priv) < 4) {
7355 if (crtc->pipe != PIPE_B)
7356 return;
7357 } else {
7358 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7359 return;
7360 }
7361
7362 pipe_config->gmch_pfit.control = tmp;
7363 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7364 }
7365
7366 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7367 struct intel_crtc_state *pipe_config)
7368 {
7369 struct drm_device *dev = crtc->base.dev;
7370 struct drm_i915_private *dev_priv = to_i915(dev);
7371 int pipe = pipe_config->cpu_transcoder;
7372 struct dpll clock;
7373 u32 mdiv;
7374 int refclk = 100000;
7375
7376 /* In case of DSI, DPLL will not be used */
7377 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7378 return;
7379
7380 mutex_lock(&dev_priv->sb_lock);
7381 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7382 mutex_unlock(&dev_priv->sb_lock);
7383
7384 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7385 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7386 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7387 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7388 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7389
7390 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7391 }
7392
7393 static void
7394 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7395 struct intel_initial_plane_config *plane_config)
7396 {
7397 struct drm_device *dev = crtc->base.dev;
7398 struct drm_i915_private *dev_priv = to_i915(dev);
7399 u32 val, base, offset;
7400 int pipe = crtc->pipe, plane = crtc->plane;
7401 int fourcc, pixel_format;
7402 unsigned int aligned_height;
7403 struct drm_framebuffer *fb;
7404 struct intel_framebuffer *intel_fb;
7405
7406 val = I915_READ(DSPCNTR(plane));
7407 if (!(val & DISPLAY_PLANE_ENABLE))
7408 return;
7409
7410 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7411 if (!intel_fb) {
7412 DRM_DEBUG_KMS("failed to alloc fb\n");
7413 return;
7414 }
7415
7416 fb = &intel_fb->base;
7417
7418 fb->dev = dev;
7419
7420 if (INTEL_GEN(dev_priv) >= 4) {
7421 if (val & DISPPLANE_TILED) {
7422 plane_config->tiling = I915_TILING_X;
7423 fb->modifier = I915_FORMAT_MOD_X_TILED;
7424 }
7425 }
7426
7427 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7428 fourcc = i9xx_format_to_fourcc(pixel_format);
7429 fb->format = drm_format_info(fourcc);
7430
7431 if (INTEL_GEN(dev_priv) >= 4) {
7432 if (plane_config->tiling)
7433 offset = I915_READ(DSPTILEOFF(plane));
7434 else
7435 offset = I915_READ(DSPLINOFF(plane));
7436 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7437 } else {
7438 base = I915_READ(DSPADDR(plane));
7439 }
7440 plane_config->base = base;
7441
7442 val = I915_READ(PIPESRC(pipe));
7443 fb->width = ((val >> 16) & 0xfff) + 1;
7444 fb->height = ((val >> 0) & 0xfff) + 1;
7445
7446 val = I915_READ(DSPSTRIDE(pipe));
7447 fb->pitches[0] = val & 0xffffffc0;
7448
7449 aligned_height = intel_fb_align_height(fb, 0, fb->height);
7450
7451 plane_config->size = fb->pitches[0] * aligned_height;
7452
7453 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7454 pipe_name(pipe), plane, fb->width, fb->height,
7455 fb->format->cpp[0] * 8, base, fb->pitches[0],
7456 plane_config->size);
7457
7458 plane_config->fb = intel_fb;
7459 }
7460
7461 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7462 struct intel_crtc_state *pipe_config)
7463 {
7464 struct drm_device *dev = crtc->base.dev;
7465 struct drm_i915_private *dev_priv = to_i915(dev);
7466 int pipe = pipe_config->cpu_transcoder;
7467 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7468 struct dpll clock;
7469 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7470 int refclk = 100000;
7471
7472 /* In case of DSI, DPLL will not be used */
7473 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7474 return;
7475
7476 mutex_lock(&dev_priv->sb_lock);
7477 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7478 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7479 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7480 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7481 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7482 mutex_unlock(&dev_priv->sb_lock);
7483
7484 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7485 clock.m2 = (pll_dw0 & 0xff) << 22;
7486 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7487 clock.m2 |= pll_dw2 & 0x3fffff;
7488 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7489 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7490 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7491
7492 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7493 }
7494
7495 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7496 struct intel_crtc_state *pipe_config)
7497 {
7498 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7499 enum intel_display_power_domain power_domain;
7500 uint32_t tmp;
7501 bool ret;
7502
7503 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7504 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7505 return false;
7506
7507 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7508 pipe_config->shared_dpll = NULL;
7509
7510 ret = false;
7511
7512 tmp = I915_READ(PIPECONF(crtc->pipe));
7513 if (!(tmp & PIPECONF_ENABLE))
7514 goto out;
7515
7516 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7517 IS_CHERRYVIEW(dev_priv)) {
7518 switch (tmp & PIPECONF_BPC_MASK) {
7519 case PIPECONF_6BPC:
7520 pipe_config->pipe_bpp = 18;
7521 break;
7522 case PIPECONF_8BPC:
7523 pipe_config->pipe_bpp = 24;
7524 break;
7525 case PIPECONF_10BPC:
7526 pipe_config->pipe_bpp = 30;
7527 break;
7528 default:
7529 break;
7530 }
7531 }
7532
7533 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7534 (tmp & PIPECONF_COLOR_RANGE_SELECT))
7535 pipe_config->limited_color_range = true;
7536
7537 if (INTEL_GEN(dev_priv) < 4)
7538 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7539
7540 intel_get_pipe_timings(crtc, pipe_config);
7541 intel_get_pipe_src_size(crtc, pipe_config);
7542
7543 i9xx_get_pfit_config(crtc, pipe_config);
7544
7545 if (INTEL_GEN(dev_priv) >= 4) {
7546 /* No way to read it out on pipes B and C */
7547 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7548 tmp = dev_priv->chv_dpll_md[crtc->pipe];
7549 else
7550 tmp = I915_READ(DPLL_MD(crtc->pipe));
7551 pipe_config->pixel_multiplier =
7552 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7553 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7554 pipe_config->dpll_hw_state.dpll_md = tmp;
7555 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7556 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7557 tmp = I915_READ(DPLL(crtc->pipe));
7558 pipe_config->pixel_multiplier =
7559 ((tmp & SDVO_MULTIPLIER_MASK)
7560 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7561 } else {
7562 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7563 * port and will be fixed up in the encoder->get_config
7564 * function. */
7565 pipe_config->pixel_multiplier = 1;
7566 }
7567 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7568 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7569 /*
7570 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7571 * on 830. Filter it out here so that we don't
7572 * report errors due to that.
7573 */
7574 if (IS_I830(dev_priv))
7575 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7576
7577 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7578 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7579 } else {
7580 /* Mask out read-only status bits. */
7581 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7582 DPLL_PORTC_READY_MASK |
7583 DPLL_PORTB_READY_MASK);
7584 }
7585
7586 if (IS_CHERRYVIEW(dev_priv))
7587 chv_crtc_clock_get(crtc, pipe_config);
7588 else if (IS_VALLEYVIEW(dev_priv))
7589 vlv_crtc_clock_get(crtc, pipe_config);
7590 else
7591 i9xx_crtc_clock_get(crtc, pipe_config);
7592
7593 /*
7594 * Normally the dotclock is filled in by the encoder .get_config()
7595 * but in case the pipe is enabled w/o any ports we need a sane
7596 * default.
7597 */
7598 pipe_config->base.adjusted_mode.crtc_clock =
7599 pipe_config->port_clock / pipe_config->pixel_multiplier;
7600
7601 ret = true;
7602
7603 out:
7604 intel_display_power_put(dev_priv, power_domain);
7605
7606 return ret;
7607 }
7608
7609 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7610 {
7611 struct intel_encoder *encoder;
7612 int i;
7613 u32 val, final;
7614 bool has_lvds = false;
7615 bool has_cpu_edp = false;
7616 bool has_panel = false;
7617 bool has_ck505 = false;
7618 bool can_ssc = false;
7619 bool using_ssc_source = false;
7620
7621 /* We need to take the global config into account */
7622 for_each_intel_encoder(&dev_priv->drm, encoder) {
7623 switch (encoder->type) {
7624 case INTEL_OUTPUT_LVDS:
7625 has_panel = true;
7626 has_lvds = true;
7627 break;
7628 case INTEL_OUTPUT_EDP:
7629 has_panel = true;
7630 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7631 has_cpu_edp = true;
7632 break;
7633 default:
7634 break;
7635 }
7636 }
7637
7638 if (HAS_PCH_IBX(dev_priv)) {
7639 has_ck505 = dev_priv->vbt.display_clock_mode;
7640 can_ssc = has_ck505;
7641 } else {
7642 has_ck505 = false;
7643 can_ssc = true;
7644 }
7645
7646 /* Check if any DPLLs are using the SSC source */
7647 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7648 u32 temp = I915_READ(PCH_DPLL(i));
7649
7650 if (!(temp & DPLL_VCO_ENABLE))
7651 continue;
7652
7653 if ((temp & PLL_REF_INPUT_MASK) ==
7654 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7655 using_ssc_source = true;
7656 break;
7657 }
7658 }
7659
7660 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7661 has_panel, has_lvds, has_ck505, using_ssc_source);
7662
7663 /* Ironlake: try to setup display ref clock before DPLL
7664 * enabling. This is only under driver's control after
7665 * PCH B stepping, previous chipset stepping should be
7666 * ignoring this setting.
7667 */
7668 val = I915_READ(PCH_DREF_CONTROL);
7669
7670 /* As we must carefully and slowly disable/enable each source in turn,
7671 * compute the final state we want first and check if we need to
7672 * make any changes at all.
7673 */
7674 final = val;
7675 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7676 if (has_ck505)
7677 final |= DREF_NONSPREAD_CK505_ENABLE;
7678 else
7679 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7680
7681 final &= ~DREF_SSC_SOURCE_MASK;
7682 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7683 final &= ~DREF_SSC1_ENABLE;
7684
7685 if (has_panel) {
7686 final |= DREF_SSC_SOURCE_ENABLE;
7687
7688 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7689 final |= DREF_SSC1_ENABLE;
7690
7691 if (has_cpu_edp) {
7692 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7693 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7694 else
7695 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7696 } else
7697 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7698 } else if (using_ssc_source) {
7699 final |= DREF_SSC_SOURCE_ENABLE;
7700 final |= DREF_SSC1_ENABLE;
7701 }
7702
7703 if (final == val)
7704 return;
7705
7706 /* Always enable nonspread source */
7707 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7708
7709 if (has_ck505)
7710 val |= DREF_NONSPREAD_CK505_ENABLE;
7711 else
7712 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7713
7714 if (has_panel) {
7715 val &= ~DREF_SSC_SOURCE_MASK;
7716 val |= DREF_SSC_SOURCE_ENABLE;
7717
7718 /* SSC must be turned on before enabling the CPU output */
7719 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7720 DRM_DEBUG_KMS("Using SSC on panel\n");
7721 val |= DREF_SSC1_ENABLE;
7722 } else
7723 val &= ~DREF_SSC1_ENABLE;
7724
7725 /* Get SSC going before enabling the outputs */
7726 I915_WRITE(PCH_DREF_CONTROL, val);
7727 POSTING_READ(PCH_DREF_CONTROL);
7728 udelay(200);
7729
7730 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7731
7732 /* Enable CPU source on CPU attached eDP */
7733 if (has_cpu_edp) {
7734 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7735 DRM_DEBUG_KMS("Using SSC on eDP\n");
7736 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7737 } else
7738 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7739 } else
7740 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7741
7742 I915_WRITE(PCH_DREF_CONTROL, val);
7743 POSTING_READ(PCH_DREF_CONTROL);
7744 udelay(200);
7745 } else {
7746 DRM_DEBUG_KMS("Disabling CPU source output\n");
7747
7748 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7749
7750 /* Turn off CPU output */
7751 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7752
7753 I915_WRITE(PCH_DREF_CONTROL, val);
7754 POSTING_READ(PCH_DREF_CONTROL);
7755 udelay(200);
7756
7757 if (!using_ssc_source) {
7758 DRM_DEBUG_KMS("Disabling SSC source\n");
7759
7760 /* Turn off the SSC source */
7761 val &= ~DREF_SSC_SOURCE_MASK;
7762 val |= DREF_SSC_SOURCE_DISABLE;
7763
7764 /* Turn off SSC1 */
7765 val &= ~DREF_SSC1_ENABLE;
7766
7767 I915_WRITE(PCH_DREF_CONTROL, val);
7768 POSTING_READ(PCH_DREF_CONTROL);
7769 udelay(200);
7770 }
7771 }
7772
7773 BUG_ON(val != final);
7774 }
7775
7776 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7777 {
7778 uint32_t tmp;
7779
7780 tmp = I915_READ(SOUTH_CHICKEN2);
7781 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7782 I915_WRITE(SOUTH_CHICKEN2, tmp);
7783
7784 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7785 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7786 DRM_ERROR("FDI mPHY reset assert timeout\n");
7787
7788 tmp = I915_READ(SOUTH_CHICKEN2);
7789 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7790 I915_WRITE(SOUTH_CHICKEN2, tmp);
7791
7792 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7793 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7794 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7795 }
7796
7797 /* WaMPhyProgramming:hsw */
7798 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7799 {
7800 uint32_t tmp;
7801
7802 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7803 tmp &= ~(0xFF << 24);
7804 tmp |= (0x12 << 24);
7805 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7806
7807 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7808 tmp |= (1 << 11);
7809 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7810
7811 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7812 tmp |= (1 << 11);
7813 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7814
7815 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7816 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7817 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7818
7819 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7820 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7821 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7822
7823 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7824 tmp &= ~(7 << 13);
7825 tmp |= (5 << 13);
7826 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7827
7828 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7829 tmp &= ~(7 << 13);
7830 tmp |= (5 << 13);
7831 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7832
7833 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7834 tmp &= ~0xFF;
7835 tmp |= 0x1C;
7836 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7837
7838 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7839 tmp &= ~0xFF;
7840 tmp |= 0x1C;
7841 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7842
7843 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7844 tmp &= ~(0xFF << 16);
7845 tmp |= (0x1C << 16);
7846 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7847
7848 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7849 tmp &= ~(0xFF << 16);
7850 tmp |= (0x1C << 16);
7851 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7852
7853 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7854 tmp |= (1 << 27);
7855 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7856
7857 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7858 tmp |= (1 << 27);
7859 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7860
7861 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7862 tmp &= ~(0xF << 28);
7863 tmp |= (4 << 28);
7864 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7865
7866 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7867 tmp &= ~(0xF << 28);
7868 tmp |= (4 << 28);
7869 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7870 }
7871
7872 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7873 * Programming" based on the parameters passed:
7874 * - Sequence to enable CLKOUT_DP
7875 * - Sequence to enable CLKOUT_DP without spread
7876 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7877 */
7878 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7879 bool with_spread, bool with_fdi)
7880 {
7881 uint32_t reg, tmp;
7882
7883 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7884 with_spread = true;
7885 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7886 with_fdi, "LP PCH doesn't have FDI\n"))
7887 with_fdi = false;
7888
7889 mutex_lock(&dev_priv->sb_lock);
7890
7891 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7892 tmp &= ~SBI_SSCCTL_DISABLE;
7893 tmp |= SBI_SSCCTL_PATHALT;
7894 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7895
7896 udelay(24);
7897
7898 if (with_spread) {
7899 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7900 tmp &= ~SBI_SSCCTL_PATHALT;
7901 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7902
7903 if (with_fdi) {
7904 lpt_reset_fdi_mphy(dev_priv);
7905 lpt_program_fdi_mphy(dev_priv);
7906 }
7907 }
7908
7909 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7910 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7911 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7912 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7913
7914 mutex_unlock(&dev_priv->sb_lock);
7915 }
7916
7917 /* Sequence to disable CLKOUT_DP */
7918 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7919 {
7920 uint32_t reg, tmp;
7921
7922 mutex_lock(&dev_priv->sb_lock);
7923
7924 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7925 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7926 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7927 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7928
7929 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7930 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7931 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7932 tmp |= SBI_SSCCTL_PATHALT;
7933 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7934 udelay(32);
7935 }
7936 tmp |= SBI_SSCCTL_DISABLE;
7937 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7938 }
7939
7940 mutex_unlock(&dev_priv->sb_lock);
7941 }
7942
7943 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7944
7945 static const uint16_t sscdivintphase[] = {
7946 [BEND_IDX( 50)] = 0x3B23,
7947 [BEND_IDX( 45)] = 0x3B23,
7948 [BEND_IDX( 40)] = 0x3C23,
7949 [BEND_IDX( 35)] = 0x3C23,
7950 [BEND_IDX( 30)] = 0x3D23,
7951 [BEND_IDX( 25)] = 0x3D23,
7952 [BEND_IDX( 20)] = 0x3E23,
7953 [BEND_IDX( 15)] = 0x3E23,
7954 [BEND_IDX( 10)] = 0x3F23,
7955 [BEND_IDX( 5)] = 0x3F23,
7956 [BEND_IDX( 0)] = 0x0025,
7957 [BEND_IDX( -5)] = 0x0025,
7958 [BEND_IDX(-10)] = 0x0125,
7959 [BEND_IDX(-15)] = 0x0125,
7960 [BEND_IDX(-20)] = 0x0225,
7961 [BEND_IDX(-25)] = 0x0225,
7962 [BEND_IDX(-30)] = 0x0325,
7963 [BEND_IDX(-35)] = 0x0325,
7964 [BEND_IDX(-40)] = 0x0425,
7965 [BEND_IDX(-45)] = 0x0425,
7966 [BEND_IDX(-50)] = 0x0525,
7967 };
7968
7969 /*
7970 * Bend CLKOUT_DP
7971 * steps -50 to 50 inclusive, in steps of 5
7972 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7973 * change in clock period = -(steps / 10) * 5.787 ps
7974 */
7975 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
7976 {
7977 uint32_t tmp;
7978 int idx = BEND_IDX(steps);
7979
7980 if (WARN_ON(steps % 5 != 0))
7981 return;
7982
7983 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
7984 return;
7985
7986 mutex_lock(&dev_priv->sb_lock);
7987
7988 if (steps % 10 != 0)
7989 tmp = 0xAAAAAAAB;
7990 else
7991 tmp = 0x00000000;
7992 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
7993
7994 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
7995 tmp &= 0xffff0000;
7996 tmp |= sscdivintphase[idx];
7997 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
7998
7999 mutex_unlock(&dev_priv->sb_lock);
8000 }
8001
8002 #undef BEND_IDX
8003
8004 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
8005 {
8006 struct intel_encoder *encoder;
8007 bool has_vga = false;
8008
8009 for_each_intel_encoder(&dev_priv->drm, encoder) {
8010 switch (encoder->type) {
8011 case INTEL_OUTPUT_ANALOG:
8012 has_vga = true;
8013 break;
8014 default:
8015 break;
8016 }
8017 }
8018
8019 if (has_vga) {
8020 lpt_bend_clkout_dp(dev_priv, 0);
8021 lpt_enable_clkout_dp(dev_priv, true, true);
8022 } else {
8023 lpt_disable_clkout_dp(dev_priv);
8024 }
8025 }
8026
8027 /*
8028 * Initialize reference clocks when the driver loads
8029 */
8030 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8031 {
8032 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8033 ironlake_init_pch_refclk(dev_priv);
8034 else if (HAS_PCH_LPT(dev_priv))
8035 lpt_init_pch_refclk(dev_priv);
8036 }
8037
8038 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8039 {
8040 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8042 int pipe = intel_crtc->pipe;
8043 uint32_t val;
8044
8045 val = 0;
8046
8047 switch (intel_crtc->config->pipe_bpp) {
8048 case 18:
8049 val |= PIPECONF_6BPC;
8050 break;
8051 case 24:
8052 val |= PIPECONF_8BPC;
8053 break;
8054 case 30:
8055 val |= PIPECONF_10BPC;
8056 break;
8057 case 36:
8058 val |= PIPECONF_12BPC;
8059 break;
8060 default:
8061 /* Case prevented by intel_choose_pipe_bpp_dither. */
8062 BUG();
8063 }
8064
8065 if (intel_crtc->config->dither)
8066 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8067
8068 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8069 val |= PIPECONF_INTERLACED_ILK;
8070 else
8071 val |= PIPECONF_PROGRESSIVE;
8072
8073 if (intel_crtc->config->limited_color_range)
8074 val |= PIPECONF_COLOR_RANGE_SELECT;
8075
8076 I915_WRITE(PIPECONF(pipe), val);
8077 POSTING_READ(PIPECONF(pipe));
8078 }
8079
8080 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8081 {
8082 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8084 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8085 u32 val = 0;
8086
8087 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8088 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8089
8090 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8091 val |= PIPECONF_INTERLACED_ILK;
8092 else
8093 val |= PIPECONF_PROGRESSIVE;
8094
8095 I915_WRITE(PIPECONF(cpu_transcoder), val);
8096 POSTING_READ(PIPECONF(cpu_transcoder));
8097 }
8098
8099 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8100 {
8101 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8103
8104 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8105 u32 val = 0;
8106
8107 switch (intel_crtc->config->pipe_bpp) {
8108 case 18:
8109 val |= PIPEMISC_DITHER_6_BPC;
8110 break;
8111 case 24:
8112 val |= PIPEMISC_DITHER_8_BPC;
8113 break;
8114 case 30:
8115 val |= PIPEMISC_DITHER_10_BPC;
8116 break;
8117 case 36:
8118 val |= PIPEMISC_DITHER_12_BPC;
8119 break;
8120 default:
8121 /* Case prevented by pipe_config_set_bpp. */
8122 BUG();
8123 }
8124
8125 if (intel_crtc->config->dither)
8126 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8127
8128 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8129 }
8130 }
8131
8132 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8133 {
8134 /*
8135 * Account for spread spectrum to avoid
8136 * oversubscribing the link. Max center spread
8137 * is 2.5%; use 5% for safety's sake.
8138 */
8139 u32 bps = target_clock * bpp * 21 / 20;
8140 return DIV_ROUND_UP(bps, link_bw * 8);
8141 }
8142
8143 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8144 {
8145 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8146 }
8147
8148 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8149 struct intel_crtc_state *crtc_state,
8150 struct dpll *reduced_clock)
8151 {
8152 struct drm_crtc *crtc = &intel_crtc->base;
8153 struct drm_device *dev = crtc->dev;
8154 struct drm_i915_private *dev_priv = to_i915(dev);
8155 u32 dpll, fp, fp2;
8156 int factor;
8157
8158 /* Enable autotuning of the PLL clock (if permissible) */
8159 factor = 21;
8160 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8161 if ((intel_panel_use_ssc(dev_priv) &&
8162 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8163 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8164 factor = 25;
8165 } else if (crtc_state->sdvo_tv_clock)
8166 factor = 20;
8167
8168 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8169
8170 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8171 fp |= FP_CB_TUNE;
8172
8173 if (reduced_clock) {
8174 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8175
8176 if (reduced_clock->m < factor * reduced_clock->n)
8177 fp2 |= FP_CB_TUNE;
8178 } else {
8179 fp2 = fp;
8180 }
8181
8182 dpll = 0;
8183
8184 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8185 dpll |= DPLLB_MODE_LVDS;
8186 else
8187 dpll |= DPLLB_MODE_DAC_SERIAL;
8188
8189 dpll |= (crtc_state->pixel_multiplier - 1)
8190 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8191
8192 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8193 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8194 dpll |= DPLL_SDVO_HIGH_SPEED;
8195
8196 if (intel_crtc_has_dp_encoder(crtc_state))
8197 dpll |= DPLL_SDVO_HIGH_SPEED;
8198
8199 /*
8200 * The high speed IO clock is only really required for
8201 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8202 * possible to share the DPLL between CRT and HDMI. Enabling
8203 * the clock needlessly does no real harm, except use up a
8204 * bit of power potentially.
8205 *
8206 * We'll limit this to IVB with 3 pipes, since it has only two
8207 * DPLLs and so DPLL sharing is the only way to get three pipes
8208 * driving PCH ports at the same time. On SNB we could do this,
8209 * and potentially avoid enabling the second DPLL, but it's not
8210 * clear if it''s a win or loss power wise. No point in doing
8211 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8212 */
8213 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8214 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8215 dpll |= DPLL_SDVO_HIGH_SPEED;
8216
8217 /* compute bitmask from p1 value */
8218 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8219 /* also FPA1 */
8220 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8221
8222 switch (crtc_state->dpll.p2) {
8223 case 5:
8224 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8225 break;
8226 case 7:
8227 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8228 break;
8229 case 10:
8230 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8231 break;
8232 case 14:
8233 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8234 break;
8235 }
8236
8237 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8238 intel_panel_use_ssc(dev_priv))
8239 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8240 else
8241 dpll |= PLL_REF_INPUT_DREFCLK;
8242
8243 dpll |= DPLL_VCO_ENABLE;
8244
8245 crtc_state->dpll_hw_state.dpll = dpll;
8246 crtc_state->dpll_hw_state.fp0 = fp;
8247 crtc_state->dpll_hw_state.fp1 = fp2;
8248 }
8249
8250 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8251 struct intel_crtc_state *crtc_state)
8252 {
8253 struct drm_device *dev = crtc->base.dev;
8254 struct drm_i915_private *dev_priv = to_i915(dev);
8255 struct dpll reduced_clock;
8256 bool has_reduced_clock = false;
8257 struct intel_shared_dpll *pll;
8258 const struct intel_limit *limit;
8259 int refclk = 120000;
8260
8261 memset(&crtc_state->dpll_hw_state, 0,
8262 sizeof(crtc_state->dpll_hw_state));
8263
8264 crtc->lowfreq_avail = false;
8265
8266 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8267 if (!crtc_state->has_pch_encoder)
8268 return 0;
8269
8270 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8271 if (intel_panel_use_ssc(dev_priv)) {
8272 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8273 dev_priv->vbt.lvds_ssc_freq);
8274 refclk = dev_priv->vbt.lvds_ssc_freq;
8275 }
8276
8277 if (intel_is_dual_link_lvds(dev)) {
8278 if (refclk == 100000)
8279 limit = &intel_limits_ironlake_dual_lvds_100m;
8280 else
8281 limit = &intel_limits_ironlake_dual_lvds;
8282 } else {
8283 if (refclk == 100000)
8284 limit = &intel_limits_ironlake_single_lvds_100m;
8285 else
8286 limit = &intel_limits_ironlake_single_lvds;
8287 }
8288 } else {
8289 limit = &intel_limits_ironlake_dac;
8290 }
8291
8292 if (!crtc_state->clock_set &&
8293 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8294 refclk, NULL, &crtc_state->dpll)) {
8295 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8296 return -EINVAL;
8297 }
8298
8299 ironlake_compute_dpll(crtc, crtc_state,
8300 has_reduced_clock ? &reduced_clock : NULL);
8301
8302 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8303 if (pll == NULL) {
8304 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8305 pipe_name(crtc->pipe));
8306 return -EINVAL;
8307 }
8308
8309 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8310 has_reduced_clock)
8311 crtc->lowfreq_avail = true;
8312
8313 return 0;
8314 }
8315
8316 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8317 struct intel_link_m_n *m_n)
8318 {
8319 struct drm_device *dev = crtc->base.dev;
8320 struct drm_i915_private *dev_priv = to_i915(dev);
8321 enum pipe pipe = crtc->pipe;
8322
8323 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8324 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8325 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8326 & ~TU_SIZE_MASK;
8327 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8328 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8329 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8330 }
8331
8332 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8333 enum transcoder transcoder,
8334 struct intel_link_m_n *m_n,
8335 struct intel_link_m_n *m2_n2)
8336 {
8337 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8338 enum pipe pipe = crtc->pipe;
8339
8340 if (INTEL_GEN(dev_priv) >= 5) {
8341 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8342 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8343 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8344 & ~TU_SIZE_MASK;
8345 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8346 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8347 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8348 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8349 * gen < 8) and if DRRS is supported (to make sure the
8350 * registers are not unnecessarily read).
8351 */
8352 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8353 crtc->config->has_drrs) {
8354 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8355 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8356 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8357 & ~TU_SIZE_MASK;
8358 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8359 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8360 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8361 }
8362 } else {
8363 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8364 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8365 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8366 & ~TU_SIZE_MASK;
8367 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8368 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8369 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8370 }
8371 }
8372
8373 void intel_dp_get_m_n(struct intel_crtc *crtc,
8374 struct intel_crtc_state *pipe_config)
8375 {
8376 if (pipe_config->has_pch_encoder)
8377 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8378 else
8379 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8380 &pipe_config->dp_m_n,
8381 &pipe_config->dp_m2_n2);
8382 }
8383
8384 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8385 struct intel_crtc_state *pipe_config)
8386 {
8387 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8388 &pipe_config->fdi_m_n, NULL);
8389 }
8390
8391 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8392 struct intel_crtc_state *pipe_config)
8393 {
8394 struct drm_device *dev = crtc->base.dev;
8395 struct drm_i915_private *dev_priv = to_i915(dev);
8396 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8397 uint32_t ps_ctrl = 0;
8398 int id = -1;
8399 int i;
8400
8401 /* find scaler attached to this pipe */
8402 for (i = 0; i < crtc->num_scalers; i++) {
8403 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8404 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8405 id = i;
8406 pipe_config->pch_pfit.enabled = true;
8407 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8408 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8409 break;
8410 }
8411 }
8412
8413 scaler_state->scaler_id = id;
8414 if (id >= 0) {
8415 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8416 } else {
8417 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8418 }
8419 }
8420
8421 static void
8422 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8423 struct intel_initial_plane_config *plane_config)
8424 {
8425 struct drm_device *dev = crtc->base.dev;
8426 struct drm_i915_private *dev_priv = to_i915(dev);
8427 u32 val, base, offset, stride_mult, tiling;
8428 int pipe = crtc->pipe;
8429 int fourcc, pixel_format;
8430 unsigned int aligned_height;
8431 struct drm_framebuffer *fb;
8432 struct intel_framebuffer *intel_fb;
8433
8434 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8435 if (!intel_fb) {
8436 DRM_DEBUG_KMS("failed to alloc fb\n");
8437 return;
8438 }
8439
8440 fb = &intel_fb->base;
8441
8442 fb->dev = dev;
8443
8444 val = I915_READ(PLANE_CTL(pipe, 0));
8445 if (!(val & PLANE_CTL_ENABLE))
8446 goto error;
8447
8448 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8449 fourcc = skl_format_to_fourcc(pixel_format,
8450 val & PLANE_CTL_ORDER_RGBX,
8451 val & PLANE_CTL_ALPHA_MASK);
8452 fb->format = drm_format_info(fourcc);
8453
8454 tiling = val & PLANE_CTL_TILED_MASK;
8455 switch (tiling) {
8456 case PLANE_CTL_TILED_LINEAR:
8457 fb->modifier = DRM_FORMAT_MOD_NONE;
8458 break;
8459 case PLANE_CTL_TILED_X:
8460 plane_config->tiling = I915_TILING_X;
8461 fb->modifier = I915_FORMAT_MOD_X_TILED;
8462 break;
8463 case PLANE_CTL_TILED_Y:
8464 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8465 break;
8466 case PLANE_CTL_TILED_YF:
8467 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8468 break;
8469 default:
8470 MISSING_CASE(tiling);
8471 goto error;
8472 }
8473
8474 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8475 plane_config->base = base;
8476
8477 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8478
8479 val = I915_READ(PLANE_SIZE(pipe, 0));
8480 fb->height = ((val >> 16) & 0xfff) + 1;
8481 fb->width = ((val >> 0) & 0x1fff) + 1;
8482
8483 val = I915_READ(PLANE_STRIDE(pipe, 0));
8484 stride_mult = intel_fb_stride_alignment(fb, 0);
8485 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8486
8487 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8488
8489 plane_config->size = fb->pitches[0] * aligned_height;
8490
8491 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8492 pipe_name(pipe), fb->width, fb->height,
8493 fb->format->cpp[0] * 8, base, fb->pitches[0],
8494 plane_config->size);
8495
8496 plane_config->fb = intel_fb;
8497 return;
8498
8499 error:
8500 kfree(intel_fb);
8501 }
8502
8503 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8504 struct intel_crtc_state *pipe_config)
8505 {
8506 struct drm_device *dev = crtc->base.dev;
8507 struct drm_i915_private *dev_priv = to_i915(dev);
8508 uint32_t tmp;
8509
8510 tmp = I915_READ(PF_CTL(crtc->pipe));
8511
8512 if (tmp & PF_ENABLE) {
8513 pipe_config->pch_pfit.enabled = true;
8514 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8515 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8516
8517 /* We currently do not free assignements of panel fitters on
8518 * ivb/hsw (since we don't use the higher upscaling modes which
8519 * differentiates them) so just WARN about this case for now. */
8520 if (IS_GEN7(dev_priv)) {
8521 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8522 PF_PIPE_SEL_IVB(crtc->pipe));
8523 }
8524 }
8525 }
8526
8527 static void
8528 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8529 struct intel_initial_plane_config *plane_config)
8530 {
8531 struct drm_device *dev = crtc->base.dev;
8532 struct drm_i915_private *dev_priv = to_i915(dev);
8533 u32 val, base, offset;
8534 int pipe = crtc->pipe;
8535 int fourcc, pixel_format;
8536 unsigned int aligned_height;
8537 struct drm_framebuffer *fb;
8538 struct intel_framebuffer *intel_fb;
8539
8540 val = I915_READ(DSPCNTR(pipe));
8541 if (!(val & DISPLAY_PLANE_ENABLE))
8542 return;
8543
8544 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8545 if (!intel_fb) {
8546 DRM_DEBUG_KMS("failed to alloc fb\n");
8547 return;
8548 }
8549
8550 fb = &intel_fb->base;
8551
8552 fb->dev = dev;
8553
8554 if (INTEL_GEN(dev_priv) >= 4) {
8555 if (val & DISPPLANE_TILED) {
8556 plane_config->tiling = I915_TILING_X;
8557 fb->modifier = I915_FORMAT_MOD_X_TILED;
8558 }
8559 }
8560
8561 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8562 fourcc = i9xx_format_to_fourcc(pixel_format);
8563 fb->format = drm_format_info(fourcc);
8564
8565 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8566 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8567 offset = I915_READ(DSPOFFSET(pipe));
8568 } else {
8569 if (plane_config->tiling)
8570 offset = I915_READ(DSPTILEOFF(pipe));
8571 else
8572 offset = I915_READ(DSPLINOFF(pipe));
8573 }
8574 plane_config->base = base;
8575
8576 val = I915_READ(PIPESRC(pipe));
8577 fb->width = ((val >> 16) & 0xfff) + 1;
8578 fb->height = ((val >> 0) & 0xfff) + 1;
8579
8580 val = I915_READ(DSPSTRIDE(pipe));
8581 fb->pitches[0] = val & 0xffffffc0;
8582
8583 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8584
8585 plane_config->size = fb->pitches[0] * aligned_height;
8586
8587 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8588 pipe_name(pipe), fb->width, fb->height,
8589 fb->format->cpp[0] * 8, base, fb->pitches[0],
8590 plane_config->size);
8591
8592 plane_config->fb = intel_fb;
8593 }
8594
8595 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8596 struct intel_crtc_state *pipe_config)
8597 {
8598 struct drm_device *dev = crtc->base.dev;
8599 struct drm_i915_private *dev_priv = to_i915(dev);
8600 enum intel_display_power_domain power_domain;
8601 uint32_t tmp;
8602 bool ret;
8603
8604 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8605 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8606 return false;
8607
8608 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8609 pipe_config->shared_dpll = NULL;
8610
8611 ret = false;
8612 tmp = I915_READ(PIPECONF(crtc->pipe));
8613 if (!(tmp & PIPECONF_ENABLE))
8614 goto out;
8615
8616 switch (tmp & PIPECONF_BPC_MASK) {
8617 case PIPECONF_6BPC:
8618 pipe_config->pipe_bpp = 18;
8619 break;
8620 case PIPECONF_8BPC:
8621 pipe_config->pipe_bpp = 24;
8622 break;
8623 case PIPECONF_10BPC:
8624 pipe_config->pipe_bpp = 30;
8625 break;
8626 case PIPECONF_12BPC:
8627 pipe_config->pipe_bpp = 36;
8628 break;
8629 default:
8630 break;
8631 }
8632
8633 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8634 pipe_config->limited_color_range = true;
8635
8636 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8637 struct intel_shared_dpll *pll;
8638 enum intel_dpll_id pll_id;
8639
8640 pipe_config->has_pch_encoder = true;
8641
8642 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8643 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8644 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8645
8646 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8647
8648 if (HAS_PCH_IBX(dev_priv)) {
8649 /*
8650 * The pipe->pch transcoder and pch transcoder->pll
8651 * mapping is fixed.
8652 */
8653 pll_id = (enum intel_dpll_id) crtc->pipe;
8654 } else {
8655 tmp = I915_READ(PCH_DPLL_SEL);
8656 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8657 pll_id = DPLL_ID_PCH_PLL_B;
8658 else
8659 pll_id= DPLL_ID_PCH_PLL_A;
8660 }
8661
8662 pipe_config->shared_dpll =
8663 intel_get_shared_dpll_by_id(dev_priv, pll_id);
8664 pll = pipe_config->shared_dpll;
8665
8666 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8667 &pipe_config->dpll_hw_state));
8668
8669 tmp = pipe_config->dpll_hw_state.dpll;
8670 pipe_config->pixel_multiplier =
8671 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8672 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8673
8674 ironlake_pch_clock_get(crtc, pipe_config);
8675 } else {
8676 pipe_config->pixel_multiplier = 1;
8677 }
8678
8679 intel_get_pipe_timings(crtc, pipe_config);
8680 intel_get_pipe_src_size(crtc, pipe_config);
8681
8682 ironlake_get_pfit_config(crtc, pipe_config);
8683
8684 ret = true;
8685
8686 out:
8687 intel_display_power_put(dev_priv, power_domain);
8688
8689 return ret;
8690 }
8691
8692 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8693 {
8694 struct drm_device *dev = &dev_priv->drm;
8695 struct intel_crtc *crtc;
8696
8697 for_each_intel_crtc(dev, crtc)
8698 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8699 pipe_name(crtc->pipe));
8700
8701 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8702 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8703 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8704 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8705 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8706 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8707 "CPU PWM1 enabled\n");
8708 if (IS_HASWELL(dev_priv))
8709 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8710 "CPU PWM2 enabled\n");
8711 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8712 "PCH PWM1 enabled\n");
8713 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8714 "Utility pin enabled\n");
8715 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8716
8717 /*
8718 * In theory we can still leave IRQs enabled, as long as only the HPD
8719 * interrupts remain enabled. We used to check for that, but since it's
8720 * gen-specific and since we only disable LCPLL after we fully disable
8721 * the interrupts, the check below should be enough.
8722 */
8723 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8724 }
8725
8726 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8727 {
8728 if (IS_HASWELL(dev_priv))
8729 return I915_READ(D_COMP_HSW);
8730 else
8731 return I915_READ(D_COMP_BDW);
8732 }
8733
8734 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8735 {
8736 if (IS_HASWELL(dev_priv)) {
8737 mutex_lock(&dev_priv->rps.hw_lock);
8738 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8739 val))
8740 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8741 mutex_unlock(&dev_priv->rps.hw_lock);
8742 } else {
8743 I915_WRITE(D_COMP_BDW, val);
8744 POSTING_READ(D_COMP_BDW);
8745 }
8746 }
8747
8748 /*
8749 * This function implements pieces of two sequences from BSpec:
8750 * - Sequence for display software to disable LCPLL
8751 * - Sequence for display software to allow package C8+
8752 * The steps implemented here are just the steps that actually touch the LCPLL
8753 * register. Callers should take care of disabling all the display engine
8754 * functions, doing the mode unset, fixing interrupts, etc.
8755 */
8756 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8757 bool switch_to_fclk, bool allow_power_down)
8758 {
8759 uint32_t val;
8760
8761 assert_can_disable_lcpll(dev_priv);
8762
8763 val = I915_READ(LCPLL_CTL);
8764
8765 if (switch_to_fclk) {
8766 val |= LCPLL_CD_SOURCE_FCLK;
8767 I915_WRITE(LCPLL_CTL, val);
8768
8769 if (wait_for_us(I915_READ(LCPLL_CTL) &
8770 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8771 DRM_ERROR("Switching to FCLK failed\n");
8772
8773 val = I915_READ(LCPLL_CTL);
8774 }
8775
8776 val |= LCPLL_PLL_DISABLE;
8777 I915_WRITE(LCPLL_CTL, val);
8778 POSTING_READ(LCPLL_CTL);
8779
8780 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8781 DRM_ERROR("LCPLL still locked\n");
8782
8783 val = hsw_read_dcomp(dev_priv);
8784 val |= D_COMP_COMP_DISABLE;
8785 hsw_write_dcomp(dev_priv, val);
8786 ndelay(100);
8787
8788 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8789 1))
8790 DRM_ERROR("D_COMP RCOMP still in progress\n");
8791
8792 if (allow_power_down) {
8793 val = I915_READ(LCPLL_CTL);
8794 val |= LCPLL_POWER_DOWN_ALLOW;
8795 I915_WRITE(LCPLL_CTL, val);
8796 POSTING_READ(LCPLL_CTL);
8797 }
8798 }
8799
8800 /*
8801 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8802 * source.
8803 */
8804 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8805 {
8806 uint32_t val;
8807
8808 val = I915_READ(LCPLL_CTL);
8809
8810 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8811 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8812 return;
8813
8814 /*
8815 * Make sure we're not on PC8 state before disabling PC8, otherwise
8816 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8817 */
8818 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8819
8820 if (val & LCPLL_POWER_DOWN_ALLOW) {
8821 val &= ~LCPLL_POWER_DOWN_ALLOW;
8822 I915_WRITE(LCPLL_CTL, val);
8823 POSTING_READ(LCPLL_CTL);
8824 }
8825
8826 val = hsw_read_dcomp(dev_priv);
8827 val |= D_COMP_COMP_FORCE;
8828 val &= ~D_COMP_COMP_DISABLE;
8829 hsw_write_dcomp(dev_priv, val);
8830
8831 val = I915_READ(LCPLL_CTL);
8832 val &= ~LCPLL_PLL_DISABLE;
8833 I915_WRITE(LCPLL_CTL, val);
8834
8835 if (intel_wait_for_register(dev_priv,
8836 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8837 5))
8838 DRM_ERROR("LCPLL not locked yet\n");
8839
8840 if (val & LCPLL_CD_SOURCE_FCLK) {
8841 val = I915_READ(LCPLL_CTL);
8842 val &= ~LCPLL_CD_SOURCE_FCLK;
8843 I915_WRITE(LCPLL_CTL, val);
8844
8845 if (wait_for_us((I915_READ(LCPLL_CTL) &
8846 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8847 DRM_ERROR("Switching back to LCPLL failed\n");
8848 }
8849
8850 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8851 intel_update_cdclk(dev_priv);
8852 }
8853
8854 /*
8855 * Package states C8 and deeper are really deep PC states that can only be
8856 * reached when all the devices on the system allow it, so even if the graphics
8857 * device allows PC8+, it doesn't mean the system will actually get to these
8858 * states. Our driver only allows PC8+ when going into runtime PM.
8859 *
8860 * The requirements for PC8+ are that all the outputs are disabled, the power
8861 * well is disabled and most interrupts are disabled, and these are also
8862 * requirements for runtime PM. When these conditions are met, we manually do
8863 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8864 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8865 * hang the machine.
8866 *
8867 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8868 * the state of some registers, so when we come back from PC8+ we need to
8869 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8870 * need to take care of the registers kept by RC6. Notice that this happens even
8871 * if we don't put the device in PCI D3 state (which is what currently happens
8872 * because of the runtime PM support).
8873 *
8874 * For more, read "Display Sequences for Package C8" on the hardware
8875 * documentation.
8876 */
8877 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8878 {
8879 uint32_t val;
8880
8881 DRM_DEBUG_KMS("Enabling package C8+\n");
8882
8883 if (HAS_PCH_LPT_LP(dev_priv)) {
8884 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8885 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8886 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8887 }
8888
8889 lpt_disable_clkout_dp(dev_priv);
8890 hsw_disable_lcpll(dev_priv, true, true);
8891 }
8892
8893 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8894 {
8895 uint32_t val;
8896
8897 DRM_DEBUG_KMS("Disabling package C8+\n");
8898
8899 hsw_restore_lcpll(dev_priv);
8900 lpt_init_pch_refclk(dev_priv);
8901
8902 if (HAS_PCH_LPT_LP(dev_priv)) {
8903 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8904 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8905 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8906 }
8907 }
8908
8909 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8910 struct intel_crtc_state *crtc_state)
8911 {
8912 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8913 if (!intel_ddi_pll_select(crtc, crtc_state))
8914 return -EINVAL;
8915 }
8916
8917 crtc->lowfreq_avail = false;
8918
8919 return 0;
8920 }
8921
8922 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8923 enum port port,
8924 struct intel_crtc_state *pipe_config)
8925 {
8926 enum intel_dpll_id id;
8927
8928 switch (port) {
8929 case PORT_A:
8930 id = DPLL_ID_SKL_DPLL0;
8931 break;
8932 case PORT_B:
8933 id = DPLL_ID_SKL_DPLL1;
8934 break;
8935 case PORT_C:
8936 id = DPLL_ID_SKL_DPLL2;
8937 break;
8938 default:
8939 DRM_ERROR("Incorrect port type\n");
8940 return;
8941 }
8942
8943 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8944 }
8945
8946 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8947 enum port port,
8948 struct intel_crtc_state *pipe_config)
8949 {
8950 enum intel_dpll_id id;
8951 u32 temp;
8952
8953 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8954 id = temp >> (port * 3 + 1);
8955
8956 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
8957 return;
8958
8959 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8960 }
8961
8962 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8963 enum port port,
8964 struct intel_crtc_state *pipe_config)
8965 {
8966 enum intel_dpll_id id;
8967 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8968
8969 switch (ddi_pll_sel) {
8970 case PORT_CLK_SEL_WRPLL1:
8971 id = DPLL_ID_WRPLL1;
8972 break;
8973 case PORT_CLK_SEL_WRPLL2:
8974 id = DPLL_ID_WRPLL2;
8975 break;
8976 case PORT_CLK_SEL_SPLL:
8977 id = DPLL_ID_SPLL;
8978 break;
8979 case PORT_CLK_SEL_LCPLL_810:
8980 id = DPLL_ID_LCPLL_810;
8981 break;
8982 case PORT_CLK_SEL_LCPLL_1350:
8983 id = DPLL_ID_LCPLL_1350;
8984 break;
8985 case PORT_CLK_SEL_LCPLL_2700:
8986 id = DPLL_ID_LCPLL_2700;
8987 break;
8988 default:
8989 MISSING_CASE(ddi_pll_sel);
8990 /* fall through */
8991 case PORT_CLK_SEL_NONE:
8992 return;
8993 }
8994
8995 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8996 }
8997
8998 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
8999 struct intel_crtc_state *pipe_config,
9000 u64 *power_domain_mask)
9001 {
9002 struct drm_device *dev = crtc->base.dev;
9003 struct drm_i915_private *dev_priv = to_i915(dev);
9004 enum intel_display_power_domain power_domain;
9005 u32 tmp;
9006
9007 /*
9008 * The pipe->transcoder mapping is fixed with the exception of the eDP
9009 * transcoder handled below.
9010 */
9011 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9012
9013 /*
9014 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9015 * consistency and less surprising code; it's in always on power).
9016 */
9017 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9018 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9019 enum pipe trans_edp_pipe;
9020 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9021 default:
9022 WARN(1, "unknown pipe linked to edp transcoder\n");
9023 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9024 case TRANS_DDI_EDP_INPUT_A_ON:
9025 trans_edp_pipe = PIPE_A;
9026 break;
9027 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9028 trans_edp_pipe = PIPE_B;
9029 break;
9030 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9031 trans_edp_pipe = PIPE_C;
9032 break;
9033 }
9034
9035 if (trans_edp_pipe == crtc->pipe)
9036 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9037 }
9038
9039 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9040 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9041 return false;
9042 *power_domain_mask |= BIT_ULL(power_domain);
9043
9044 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9045
9046 return tmp & PIPECONF_ENABLE;
9047 }
9048
9049 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9050 struct intel_crtc_state *pipe_config,
9051 u64 *power_domain_mask)
9052 {
9053 struct drm_device *dev = crtc->base.dev;
9054 struct drm_i915_private *dev_priv = to_i915(dev);
9055 enum intel_display_power_domain power_domain;
9056 enum port port;
9057 enum transcoder cpu_transcoder;
9058 u32 tmp;
9059
9060 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9061 if (port == PORT_A)
9062 cpu_transcoder = TRANSCODER_DSI_A;
9063 else
9064 cpu_transcoder = TRANSCODER_DSI_C;
9065
9066 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9067 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9068 continue;
9069 *power_domain_mask |= BIT_ULL(power_domain);
9070
9071 /*
9072 * The PLL needs to be enabled with a valid divider
9073 * configuration, otherwise accessing DSI registers will hang
9074 * the machine. See BSpec North Display Engine
9075 * registers/MIPI[BXT]. We can break out here early, since we
9076 * need the same DSI PLL to be enabled for both DSI ports.
9077 */
9078 if (!intel_dsi_pll_is_enabled(dev_priv))
9079 break;
9080
9081 /* XXX: this works for video mode only */
9082 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9083 if (!(tmp & DPI_ENABLE))
9084 continue;
9085
9086 tmp = I915_READ(MIPI_CTRL(port));
9087 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9088 continue;
9089
9090 pipe_config->cpu_transcoder = cpu_transcoder;
9091 break;
9092 }
9093
9094 return transcoder_is_dsi(pipe_config->cpu_transcoder);
9095 }
9096
9097 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9098 struct intel_crtc_state *pipe_config)
9099 {
9100 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9101 struct intel_shared_dpll *pll;
9102 enum port port;
9103 uint32_t tmp;
9104
9105 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9106
9107 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9108
9109 if (IS_GEN9_BC(dev_priv))
9110 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9111 else if (IS_GEN9_LP(dev_priv))
9112 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9113 else
9114 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9115
9116 pll = pipe_config->shared_dpll;
9117 if (pll) {
9118 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9119 &pipe_config->dpll_hw_state));
9120 }
9121
9122 /*
9123 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9124 * DDI E. So just check whether this pipe is wired to DDI E and whether
9125 * the PCH transcoder is on.
9126 */
9127 if (INTEL_GEN(dev_priv) < 9 &&
9128 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9129 pipe_config->has_pch_encoder = true;
9130
9131 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9132 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9133 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9134
9135 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9136 }
9137 }
9138
9139 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9140 struct intel_crtc_state *pipe_config)
9141 {
9142 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9143 enum intel_display_power_domain power_domain;
9144 u64 power_domain_mask;
9145 bool active;
9146
9147 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9148 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9149 return false;
9150 power_domain_mask = BIT_ULL(power_domain);
9151
9152 pipe_config->shared_dpll = NULL;
9153
9154 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9155
9156 if (IS_GEN9_LP(dev_priv) &&
9157 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9158 WARN_ON(active);
9159 active = true;
9160 }
9161
9162 if (!active)
9163 goto out;
9164
9165 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9166 haswell_get_ddi_port_state(crtc, pipe_config);
9167 intel_get_pipe_timings(crtc, pipe_config);
9168 }
9169
9170 intel_get_pipe_src_size(crtc, pipe_config);
9171
9172 pipe_config->gamma_mode =
9173 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9174
9175 if (INTEL_GEN(dev_priv) >= 9) {
9176 intel_crtc_init_scalers(crtc, pipe_config);
9177
9178 pipe_config->scaler_state.scaler_id = -1;
9179 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9180 }
9181
9182 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9183 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9184 power_domain_mask |= BIT_ULL(power_domain);
9185 if (INTEL_GEN(dev_priv) >= 9)
9186 skylake_get_pfit_config(crtc, pipe_config);
9187 else
9188 ironlake_get_pfit_config(crtc, pipe_config);
9189 }
9190
9191 if (IS_HASWELL(dev_priv))
9192 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9193 (I915_READ(IPS_CTL) & IPS_ENABLE);
9194
9195 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9196 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9197 pipe_config->pixel_multiplier =
9198 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9199 } else {
9200 pipe_config->pixel_multiplier = 1;
9201 }
9202
9203 out:
9204 for_each_power_domain(power_domain, power_domain_mask)
9205 intel_display_power_put(dev_priv, power_domain);
9206
9207 return active;
9208 }
9209
9210 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9211 const struct intel_plane_state *plane_state)
9212 {
9213 unsigned int width = plane_state->base.crtc_w;
9214 unsigned int stride = roundup_pow_of_two(width) * 4;
9215
9216 switch (stride) {
9217 default:
9218 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9219 width, stride);
9220 stride = 256;
9221 /* fallthrough */
9222 case 256:
9223 case 512:
9224 case 1024:
9225 case 2048:
9226 break;
9227 }
9228
9229 return CURSOR_ENABLE |
9230 CURSOR_GAMMA_ENABLE |
9231 CURSOR_FORMAT_ARGB |
9232 CURSOR_STRIDE(stride);
9233 }
9234
9235 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
9236 const struct intel_crtc_state *crtc_state,
9237 const struct intel_plane_state *plane_state)
9238 {
9239 struct drm_device *dev = crtc->dev;
9240 struct drm_i915_private *dev_priv = to_i915(dev);
9241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9242 uint32_t cntl = 0, size = 0;
9243
9244 if (plane_state && plane_state->base.visible) {
9245 unsigned int width = plane_state->base.crtc_w;
9246 unsigned int height = plane_state->base.crtc_h;
9247
9248 cntl = i845_cursor_ctl(crtc_state, plane_state);
9249 size = (height << 12) | width;
9250 }
9251
9252 if (intel_crtc->cursor_cntl != 0 &&
9253 (intel_crtc->cursor_base != base ||
9254 intel_crtc->cursor_size != size ||
9255 intel_crtc->cursor_cntl != cntl)) {
9256 /* On these chipsets we can only modify the base/size/stride
9257 * whilst the cursor is disabled.
9258 */
9259 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9260 POSTING_READ_FW(CURCNTR(PIPE_A));
9261 intel_crtc->cursor_cntl = 0;
9262 }
9263
9264 if (intel_crtc->cursor_base != base) {
9265 I915_WRITE_FW(CURBASE(PIPE_A), base);
9266 intel_crtc->cursor_base = base;
9267 }
9268
9269 if (intel_crtc->cursor_size != size) {
9270 I915_WRITE_FW(CURSIZE, size);
9271 intel_crtc->cursor_size = size;
9272 }
9273
9274 if (intel_crtc->cursor_cntl != cntl) {
9275 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9276 POSTING_READ_FW(CURCNTR(PIPE_A));
9277 intel_crtc->cursor_cntl = cntl;
9278 }
9279 }
9280
9281 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9282 const struct intel_plane_state *plane_state)
9283 {
9284 struct drm_i915_private *dev_priv =
9285 to_i915(plane_state->base.plane->dev);
9286 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9287 enum pipe pipe = crtc->pipe;
9288 u32 cntl;
9289
9290 cntl = MCURSOR_GAMMA_ENABLE;
9291
9292 if (HAS_DDI(dev_priv))
9293 cntl |= CURSOR_PIPE_CSC_ENABLE;
9294
9295 cntl |= pipe << 28; /* Connect to correct pipe */
9296
9297 switch (plane_state->base.crtc_w) {
9298 case 64:
9299 cntl |= CURSOR_MODE_64_ARGB_AX;
9300 break;
9301 case 128:
9302 cntl |= CURSOR_MODE_128_ARGB_AX;
9303 break;
9304 case 256:
9305 cntl |= CURSOR_MODE_256_ARGB_AX;
9306 break;
9307 default:
9308 MISSING_CASE(plane_state->base.crtc_w);
9309 return 0;
9310 }
9311
9312 if (plane_state->base.rotation & DRM_ROTATE_180)
9313 cntl |= CURSOR_ROTATE_180;
9314
9315 return cntl;
9316 }
9317
9318 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
9319 const struct intel_crtc_state *crtc_state,
9320 const struct intel_plane_state *plane_state)
9321 {
9322 struct drm_device *dev = crtc->dev;
9323 struct drm_i915_private *dev_priv = to_i915(dev);
9324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9325 int pipe = intel_crtc->pipe;
9326 uint32_t cntl = 0;
9327
9328 if (plane_state && plane_state->base.visible)
9329 cntl = i9xx_cursor_ctl(crtc_state, plane_state);
9330
9331 if (intel_crtc->cursor_cntl != cntl) {
9332 I915_WRITE_FW(CURCNTR(pipe), cntl);
9333 POSTING_READ_FW(CURCNTR(pipe));
9334 intel_crtc->cursor_cntl = cntl;
9335 }
9336
9337 /* and commit changes on next vblank */
9338 I915_WRITE_FW(CURBASE(pipe), base);
9339 POSTING_READ_FW(CURBASE(pipe));
9340
9341 intel_crtc->cursor_base = base;
9342 }
9343
9344 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9345 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9346 const struct intel_crtc_state *crtc_state,
9347 const struct intel_plane_state *plane_state)
9348 {
9349 struct drm_device *dev = crtc->dev;
9350 struct drm_i915_private *dev_priv = to_i915(dev);
9351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9352 int pipe = intel_crtc->pipe;
9353 u32 base = intel_crtc->cursor_addr;
9354 unsigned long irqflags;
9355 u32 pos = 0;
9356
9357 if (plane_state) {
9358 int x = plane_state->base.crtc_x;
9359 int y = plane_state->base.crtc_y;
9360
9361 if (x < 0) {
9362 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9363 x = -x;
9364 }
9365 pos |= x << CURSOR_X_SHIFT;
9366
9367 if (y < 0) {
9368 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9369 y = -y;
9370 }
9371 pos |= y << CURSOR_Y_SHIFT;
9372
9373 /* ILK+ do this automagically */
9374 if (HAS_GMCH_DISPLAY(dev_priv) &&
9375 plane_state->base.rotation & DRM_ROTATE_180) {
9376 base += (plane_state->base.crtc_h *
9377 plane_state->base.crtc_w - 1) * 4;
9378 }
9379 }
9380
9381 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9382
9383 I915_WRITE_FW(CURPOS(pipe), pos);
9384
9385 if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
9386 i845_update_cursor(crtc, base, crtc_state, plane_state);
9387 else
9388 i9xx_update_cursor(crtc, base, crtc_state, plane_state);
9389
9390 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9391 }
9392
9393 static bool cursor_size_ok(struct drm_i915_private *dev_priv,
9394 uint32_t width, uint32_t height)
9395 {
9396 if (width == 0 || height == 0)
9397 return false;
9398
9399 /*
9400 * 845g/865g are special in that they are only limited by
9401 * the width of their cursors, the height is arbitrary up to
9402 * the precision of the register. Everything else requires
9403 * square cursors, limited to a few power-of-two sizes.
9404 */
9405 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
9406 if ((width & 63) != 0)
9407 return false;
9408
9409 if (width > (IS_I845G(dev_priv) ? 64 : 512))
9410 return false;
9411
9412 if (height > 1023)
9413 return false;
9414 } else {
9415 switch (width | height) {
9416 case 256:
9417 case 128:
9418 if (IS_GEN2(dev_priv))
9419 return false;
9420 case 64:
9421 break;
9422 default:
9423 return false;
9424 }
9425 }
9426
9427 return true;
9428 }
9429
9430 /* VESA 640x480x72Hz mode to set on the pipe */
9431 static struct drm_display_mode load_detect_mode = {
9432 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9433 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9434 };
9435
9436 struct drm_framebuffer *
9437 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9438 struct drm_mode_fb_cmd2 *mode_cmd)
9439 {
9440 struct intel_framebuffer *intel_fb;
9441 int ret;
9442
9443 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9444 if (!intel_fb)
9445 return ERR_PTR(-ENOMEM);
9446
9447 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9448 if (ret)
9449 goto err;
9450
9451 return &intel_fb->base;
9452
9453 err:
9454 kfree(intel_fb);
9455 return ERR_PTR(ret);
9456 }
9457
9458 static u32
9459 intel_framebuffer_pitch_for_width(int width, int bpp)
9460 {
9461 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9462 return ALIGN(pitch, 64);
9463 }
9464
9465 static u32
9466 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9467 {
9468 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9469 return PAGE_ALIGN(pitch * mode->vdisplay);
9470 }
9471
9472 static struct drm_framebuffer *
9473 intel_framebuffer_create_for_mode(struct drm_device *dev,
9474 struct drm_display_mode *mode,
9475 int depth, int bpp)
9476 {
9477 struct drm_framebuffer *fb;
9478 struct drm_i915_gem_object *obj;
9479 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9480
9481 obj = i915_gem_object_create(to_i915(dev),
9482 intel_framebuffer_size_for_mode(mode, bpp));
9483 if (IS_ERR(obj))
9484 return ERR_CAST(obj);
9485
9486 mode_cmd.width = mode->hdisplay;
9487 mode_cmd.height = mode->vdisplay;
9488 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9489 bpp);
9490 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9491
9492 fb = intel_framebuffer_create(obj, &mode_cmd);
9493 if (IS_ERR(fb))
9494 i915_gem_object_put(obj);
9495
9496 return fb;
9497 }
9498
9499 static struct drm_framebuffer *
9500 mode_fits_in_fbdev(struct drm_device *dev,
9501 struct drm_display_mode *mode)
9502 {
9503 #ifdef CONFIG_DRM_FBDEV_EMULATION
9504 struct drm_i915_private *dev_priv = to_i915(dev);
9505 struct drm_i915_gem_object *obj;
9506 struct drm_framebuffer *fb;
9507
9508 if (!dev_priv->fbdev)
9509 return NULL;
9510
9511 if (!dev_priv->fbdev->fb)
9512 return NULL;
9513
9514 obj = dev_priv->fbdev->fb->obj;
9515 BUG_ON(!obj);
9516
9517 fb = &dev_priv->fbdev->fb->base;
9518 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9519 fb->format->cpp[0] * 8))
9520 return NULL;
9521
9522 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9523 return NULL;
9524
9525 drm_framebuffer_reference(fb);
9526 return fb;
9527 #else
9528 return NULL;
9529 #endif
9530 }
9531
9532 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9533 struct drm_crtc *crtc,
9534 struct drm_display_mode *mode,
9535 struct drm_framebuffer *fb,
9536 int x, int y)
9537 {
9538 struct drm_plane_state *plane_state;
9539 int hdisplay, vdisplay;
9540 int ret;
9541
9542 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9543 if (IS_ERR(plane_state))
9544 return PTR_ERR(plane_state);
9545
9546 if (mode)
9547 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9548 else
9549 hdisplay = vdisplay = 0;
9550
9551 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9552 if (ret)
9553 return ret;
9554 drm_atomic_set_fb_for_plane(plane_state, fb);
9555 plane_state->crtc_x = 0;
9556 plane_state->crtc_y = 0;
9557 plane_state->crtc_w = hdisplay;
9558 plane_state->crtc_h = vdisplay;
9559 plane_state->src_x = x << 16;
9560 plane_state->src_y = y << 16;
9561 plane_state->src_w = hdisplay << 16;
9562 plane_state->src_h = vdisplay << 16;
9563
9564 return 0;
9565 }
9566
9567 bool intel_get_load_detect_pipe(struct drm_connector *connector,
9568 struct drm_display_mode *mode,
9569 struct intel_load_detect_pipe *old,
9570 struct drm_modeset_acquire_ctx *ctx)
9571 {
9572 struct intel_crtc *intel_crtc;
9573 struct intel_encoder *intel_encoder =
9574 intel_attached_encoder(connector);
9575 struct drm_crtc *possible_crtc;
9576 struct drm_encoder *encoder = &intel_encoder->base;
9577 struct drm_crtc *crtc = NULL;
9578 struct drm_device *dev = encoder->dev;
9579 struct drm_i915_private *dev_priv = to_i915(dev);
9580 struct drm_framebuffer *fb;
9581 struct drm_mode_config *config = &dev->mode_config;
9582 struct drm_atomic_state *state = NULL, *restore_state = NULL;
9583 struct drm_connector_state *connector_state;
9584 struct intel_crtc_state *crtc_state;
9585 int ret, i = -1;
9586
9587 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9588 connector->base.id, connector->name,
9589 encoder->base.id, encoder->name);
9590
9591 old->restore_state = NULL;
9592
9593 retry:
9594 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9595 if (ret)
9596 goto fail;
9597
9598 /*
9599 * Algorithm gets a little messy:
9600 *
9601 * - if the connector already has an assigned crtc, use it (but make
9602 * sure it's on first)
9603 *
9604 * - try to find the first unused crtc that can drive this connector,
9605 * and use that if we find one
9606 */
9607
9608 /* See if we already have a CRTC for this connector */
9609 if (connector->state->crtc) {
9610 crtc = connector->state->crtc;
9611
9612 ret = drm_modeset_lock(&crtc->mutex, ctx);
9613 if (ret)
9614 goto fail;
9615
9616 /* Make sure the crtc and connector are running */
9617 goto found;
9618 }
9619
9620 /* Find an unused one (if possible) */
9621 for_each_crtc(dev, possible_crtc) {
9622 i++;
9623 if (!(encoder->possible_crtcs & (1 << i)))
9624 continue;
9625
9626 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9627 if (ret)
9628 goto fail;
9629
9630 if (possible_crtc->state->enable) {
9631 drm_modeset_unlock(&possible_crtc->mutex);
9632 continue;
9633 }
9634
9635 crtc = possible_crtc;
9636 break;
9637 }
9638
9639 /*
9640 * If we didn't find an unused CRTC, don't use any.
9641 */
9642 if (!crtc) {
9643 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9644 goto fail;
9645 }
9646
9647 found:
9648 intel_crtc = to_intel_crtc(crtc);
9649
9650 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9651 if (ret)
9652 goto fail;
9653
9654 state = drm_atomic_state_alloc(dev);
9655 restore_state = drm_atomic_state_alloc(dev);
9656 if (!state || !restore_state) {
9657 ret = -ENOMEM;
9658 goto fail;
9659 }
9660
9661 state->acquire_ctx = ctx;
9662 restore_state->acquire_ctx = ctx;
9663
9664 connector_state = drm_atomic_get_connector_state(state, connector);
9665 if (IS_ERR(connector_state)) {
9666 ret = PTR_ERR(connector_state);
9667 goto fail;
9668 }
9669
9670 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9671 if (ret)
9672 goto fail;
9673
9674 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9675 if (IS_ERR(crtc_state)) {
9676 ret = PTR_ERR(crtc_state);
9677 goto fail;
9678 }
9679
9680 crtc_state->base.active = crtc_state->base.enable = true;
9681
9682 if (!mode)
9683 mode = &load_detect_mode;
9684
9685 /* We need a framebuffer large enough to accommodate all accesses
9686 * that the plane may generate whilst we perform load detection.
9687 * We can not rely on the fbcon either being present (we get called
9688 * during its initialisation to detect all boot displays, or it may
9689 * not even exist) or that it is large enough to satisfy the
9690 * requested mode.
9691 */
9692 fb = mode_fits_in_fbdev(dev, mode);
9693 if (fb == NULL) {
9694 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9695 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9696 } else
9697 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9698 if (IS_ERR(fb)) {
9699 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9700 goto fail;
9701 }
9702
9703 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9704 if (ret)
9705 goto fail;
9706
9707 drm_framebuffer_unreference(fb);
9708
9709 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9710 if (ret)
9711 goto fail;
9712
9713 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9714 if (!ret)
9715 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9716 if (!ret)
9717 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9718 if (ret) {
9719 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9720 goto fail;
9721 }
9722
9723 ret = drm_atomic_commit(state);
9724 if (ret) {
9725 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9726 goto fail;
9727 }
9728
9729 old->restore_state = restore_state;
9730 drm_atomic_state_put(state);
9731
9732 /* let the connector get through one full cycle before testing */
9733 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9734 return true;
9735
9736 fail:
9737 if (state) {
9738 drm_atomic_state_put(state);
9739 state = NULL;
9740 }
9741 if (restore_state) {
9742 drm_atomic_state_put(restore_state);
9743 restore_state = NULL;
9744 }
9745
9746 if (ret == -EDEADLK) {
9747 drm_modeset_backoff(ctx);
9748 goto retry;
9749 }
9750
9751 return false;
9752 }
9753
9754 void intel_release_load_detect_pipe(struct drm_connector *connector,
9755 struct intel_load_detect_pipe *old,
9756 struct drm_modeset_acquire_ctx *ctx)
9757 {
9758 struct intel_encoder *intel_encoder =
9759 intel_attached_encoder(connector);
9760 struct drm_encoder *encoder = &intel_encoder->base;
9761 struct drm_atomic_state *state = old->restore_state;
9762 int ret;
9763
9764 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9765 connector->base.id, connector->name,
9766 encoder->base.id, encoder->name);
9767
9768 if (!state)
9769 return;
9770
9771 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
9772 if (ret)
9773 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
9774 drm_atomic_state_put(state);
9775 }
9776
9777 static int i9xx_pll_refclk(struct drm_device *dev,
9778 const struct intel_crtc_state *pipe_config)
9779 {
9780 struct drm_i915_private *dev_priv = to_i915(dev);
9781 u32 dpll = pipe_config->dpll_hw_state.dpll;
9782
9783 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9784 return dev_priv->vbt.lvds_ssc_freq;
9785 else if (HAS_PCH_SPLIT(dev_priv))
9786 return 120000;
9787 else if (!IS_GEN2(dev_priv))
9788 return 96000;
9789 else
9790 return 48000;
9791 }
9792
9793 /* Returns the clock of the currently programmed mode of the given pipe. */
9794 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9795 struct intel_crtc_state *pipe_config)
9796 {
9797 struct drm_device *dev = crtc->base.dev;
9798 struct drm_i915_private *dev_priv = to_i915(dev);
9799 int pipe = pipe_config->cpu_transcoder;
9800 u32 dpll = pipe_config->dpll_hw_state.dpll;
9801 u32 fp;
9802 struct dpll clock;
9803 int port_clock;
9804 int refclk = i9xx_pll_refclk(dev, pipe_config);
9805
9806 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9807 fp = pipe_config->dpll_hw_state.fp0;
9808 else
9809 fp = pipe_config->dpll_hw_state.fp1;
9810
9811 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9812 if (IS_PINEVIEW(dev_priv)) {
9813 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9814 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9815 } else {
9816 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9817 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9818 }
9819
9820 if (!IS_GEN2(dev_priv)) {
9821 if (IS_PINEVIEW(dev_priv))
9822 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9823 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9824 else
9825 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9826 DPLL_FPA01_P1_POST_DIV_SHIFT);
9827
9828 switch (dpll & DPLL_MODE_MASK) {
9829 case DPLLB_MODE_DAC_SERIAL:
9830 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9831 5 : 10;
9832 break;
9833 case DPLLB_MODE_LVDS:
9834 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9835 7 : 14;
9836 break;
9837 default:
9838 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9839 "mode\n", (int)(dpll & DPLL_MODE_MASK));
9840 return;
9841 }
9842
9843 if (IS_PINEVIEW(dev_priv))
9844 port_clock = pnv_calc_dpll_params(refclk, &clock);
9845 else
9846 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9847 } else {
9848 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
9849 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9850
9851 if (is_lvds) {
9852 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9853 DPLL_FPA01_P1_POST_DIV_SHIFT);
9854
9855 if (lvds & LVDS_CLKB_POWER_UP)
9856 clock.p2 = 7;
9857 else
9858 clock.p2 = 14;
9859 } else {
9860 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9861 clock.p1 = 2;
9862 else {
9863 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9864 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9865 }
9866 if (dpll & PLL_P2_DIVIDE_BY_4)
9867 clock.p2 = 4;
9868 else
9869 clock.p2 = 2;
9870 }
9871
9872 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9873 }
9874
9875 /*
9876 * This value includes pixel_multiplier. We will use
9877 * port_clock to compute adjusted_mode.crtc_clock in the
9878 * encoder's get_config() function.
9879 */
9880 pipe_config->port_clock = port_clock;
9881 }
9882
9883 int intel_dotclock_calculate(int link_freq,
9884 const struct intel_link_m_n *m_n)
9885 {
9886 /*
9887 * The calculation for the data clock is:
9888 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9889 * But we want to avoid losing precison if possible, so:
9890 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9891 *
9892 * and the link clock is simpler:
9893 * link_clock = (m * link_clock) / n
9894 */
9895
9896 if (!m_n->link_n)
9897 return 0;
9898
9899 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9900 }
9901
9902 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9903 struct intel_crtc_state *pipe_config)
9904 {
9905 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9906
9907 /* read out port_clock from the DPLL */
9908 i9xx_crtc_clock_get(crtc, pipe_config);
9909
9910 /*
9911 * In case there is an active pipe without active ports,
9912 * we may need some idea for the dotclock anyway.
9913 * Calculate one based on the FDI configuration.
9914 */
9915 pipe_config->base.adjusted_mode.crtc_clock =
9916 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
9917 &pipe_config->fdi_m_n);
9918 }
9919
9920 /** Returns the currently programmed mode of the given pipe. */
9921 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9922 struct drm_crtc *crtc)
9923 {
9924 struct drm_i915_private *dev_priv = to_i915(dev);
9925 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9926 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9927 struct drm_display_mode *mode;
9928 struct intel_crtc_state *pipe_config;
9929 int htot = I915_READ(HTOTAL(cpu_transcoder));
9930 int hsync = I915_READ(HSYNC(cpu_transcoder));
9931 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9932 int vsync = I915_READ(VSYNC(cpu_transcoder));
9933 enum pipe pipe = intel_crtc->pipe;
9934
9935 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9936 if (!mode)
9937 return NULL;
9938
9939 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9940 if (!pipe_config) {
9941 kfree(mode);
9942 return NULL;
9943 }
9944
9945 /*
9946 * Construct a pipe_config sufficient for getting the clock info
9947 * back out of crtc_clock_get.
9948 *
9949 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9950 * to use a real value here instead.
9951 */
9952 pipe_config->cpu_transcoder = (enum transcoder) pipe;
9953 pipe_config->pixel_multiplier = 1;
9954 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9955 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9956 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9957 i9xx_crtc_clock_get(intel_crtc, pipe_config);
9958
9959 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
9960 mode->hdisplay = (htot & 0xffff) + 1;
9961 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9962 mode->hsync_start = (hsync & 0xffff) + 1;
9963 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9964 mode->vdisplay = (vtot & 0xffff) + 1;
9965 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9966 mode->vsync_start = (vsync & 0xffff) + 1;
9967 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9968
9969 drm_mode_set_name(mode);
9970
9971 kfree(pipe_config);
9972
9973 return mode;
9974 }
9975
9976 static void intel_crtc_destroy(struct drm_crtc *crtc)
9977 {
9978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9979 struct drm_device *dev = crtc->dev;
9980 struct intel_flip_work *work;
9981
9982 spin_lock_irq(&dev->event_lock);
9983 work = intel_crtc->flip_work;
9984 intel_crtc->flip_work = NULL;
9985 spin_unlock_irq(&dev->event_lock);
9986
9987 if (work) {
9988 cancel_work_sync(&work->mmio_work);
9989 cancel_work_sync(&work->unpin_work);
9990 kfree(work);
9991 }
9992
9993 drm_crtc_cleanup(crtc);
9994
9995 kfree(intel_crtc);
9996 }
9997
9998 static void intel_unpin_work_fn(struct work_struct *__work)
9999 {
10000 struct intel_flip_work *work =
10001 container_of(__work, struct intel_flip_work, unpin_work);
10002 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10003 struct drm_device *dev = crtc->base.dev;
10004 struct drm_plane *primary = crtc->base.primary;
10005
10006 if (is_mmio_work(work))
10007 flush_work(&work->mmio_work);
10008
10009 mutex_lock(&dev->struct_mutex);
10010 intel_unpin_fb_vma(work->old_vma);
10011 i915_gem_object_put(work->pending_flip_obj);
10012 mutex_unlock(&dev->struct_mutex);
10013
10014 i915_gem_request_put(work->flip_queued_req);
10015
10016 intel_frontbuffer_flip_complete(to_i915(dev),
10017 to_intel_plane(primary)->frontbuffer_bit);
10018 intel_fbc_post_update(crtc);
10019 drm_framebuffer_unreference(work->old_fb);
10020
10021 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10022 atomic_dec(&crtc->unpin_work_count);
10023
10024 kfree(work);
10025 }
10026
10027 /* Is 'a' after or equal to 'b'? */
10028 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10029 {
10030 return !((a - b) & 0x80000000);
10031 }
10032
10033 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
10034 struct intel_flip_work *work)
10035 {
10036 struct drm_device *dev = crtc->base.dev;
10037 struct drm_i915_private *dev_priv = to_i915(dev);
10038
10039 if (abort_flip_on_reset(crtc))
10040 return true;
10041
10042 /*
10043 * The relevant registers doen't exist on pre-ctg.
10044 * As the flip done interrupt doesn't trigger for mmio
10045 * flips on gmch platforms, a flip count check isn't
10046 * really needed there. But since ctg has the registers,
10047 * include it in the check anyway.
10048 */
10049 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10050 return true;
10051
10052 /*
10053 * BDW signals flip done immediately if the plane
10054 * is disabled, even if the plane enable is already
10055 * armed to occur at the next vblank :(
10056 */
10057
10058 /*
10059 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10060 * used the same base address. In that case the mmio flip might
10061 * have completed, but the CS hasn't even executed the flip yet.
10062 *
10063 * A flip count check isn't enough as the CS might have updated
10064 * the base address just after start of vblank, but before we
10065 * managed to process the interrupt. This means we'd complete the
10066 * CS flip too soon.
10067 *
10068 * Combining both checks should get us a good enough result. It may
10069 * still happen that the CS flip has been executed, but has not
10070 * yet actually completed. But in case the base address is the same
10071 * anyway, we don't really care.
10072 */
10073 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10074 crtc->flip_work->gtt_offset &&
10075 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10076 crtc->flip_work->flip_count);
10077 }
10078
10079 static bool
10080 __pageflip_finished_mmio(struct intel_crtc *crtc,
10081 struct intel_flip_work *work)
10082 {
10083 /*
10084 * MMIO work completes when vblank is different from
10085 * flip_queued_vblank.
10086 *
10087 * Reset counter value doesn't matter, this is handled by
10088 * i915_wait_request finishing early, so no need to handle
10089 * reset here.
10090 */
10091 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
10092 }
10093
10094
10095 static bool pageflip_finished(struct intel_crtc *crtc,
10096 struct intel_flip_work *work)
10097 {
10098 if (!atomic_read(&work->pending))
10099 return false;
10100
10101 smp_rmb();
10102
10103 if (is_mmio_work(work))
10104 return __pageflip_finished_mmio(crtc, work);
10105 else
10106 return __pageflip_finished_cs(crtc, work);
10107 }
10108
10109 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
10110 {
10111 struct drm_device *dev = &dev_priv->drm;
10112 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10113 struct intel_flip_work *work;
10114 unsigned long flags;
10115
10116 /* Ignore early vblank irqs */
10117 if (!crtc)
10118 return;
10119
10120 /*
10121 * This is called both by irq handlers and the reset code (to complete
10122 * lost pageflips) so needs the full irqsave spinlocks.
10123 */
10124 spin_lock_irqsave(&dev->event_lock, flags);
10125 work = crtc->flip_work;
10126
10127 if (work != NULL &&
10128 !is_mmio_work(work) &&
10129 pageflip_finished(crtc, work))
10130 page_flip_completed(crtc);
10131
10132 spin_unlock_irqrestore(&dev->event_lock, flags);
10133 }
10134
10135 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
10136 {
10137 struct drm_device *dev = &dev_priv->drm;
10138 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10139 struct intel_flip_work *work;
10140 unsigned long flags;
10141
10142 /* Ignore early vblank irqs */
10143 if (!crtc)
10144 return;
10145
10146 /*
10147 * This is called both by irq handlers and the reset code (to complete
10148 * lost pageflips) so needs the full irqsave spinlocks.
10149 */
10150 spin_lock_irqsave(&dev->event_lock, flags);
10151 work = crtc->flip_work;
10152
10153 if (work != NULL &&
10154 is_mmio_work(work) &&
10155 pageflip_finished(crtc, work))
10156 page_flip_completed(crtc);
10157
10158 spin_unlock_irqrestore(&dev->event_lock, flags);
10159 }
10160
10161 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
10162 struct intel_flip_work *work)
10163 {
10164 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
10165
10166 /* Ensure that the work item is consistent when activating it ... */
10167 smp_mb__before_atomic();
10168 atomic_set(&work->pending, 1);
10169 }
10170
10171 static int intel_gen2_queue_flip(struct drm_device *dev,
10172 struct drm_crtc *crtc,
10173 struct drm_framebuffer *fb,
10174 struct drm_i915_gem_object *obj,
10175 struct drm_i915_gem_request *req,
10176 uint32_t flags)
10177 {
10178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10179 u32 flip_mask, *cs;
10180
10181 cs = intel_ring_begin(req, 6);
10182 if (IS_ERR(cs))
10183 return PTR_ERR(cs);
10184
10185 /* Can't queue multiple flips, so wait for the previous
10186 * one to finish before executing the next.
10187 */
10188 if (intel_crtc->plane)
10189 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10190 else
10191 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10192 *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10193 *cs++ = MI_NOOP;
10194 *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10195 *cs++ = fb->pitches[0];
10196 *cs++ = intel_crtc->flip_work->gtt_offset;
10197 *cs++ = 0; /* aux display base address, unused */
10198
10199 return 0;
10200 }
10201
10202 static int intel_gen3_queue_flip(struct drm_device *dev,
10203 struct drm_crtc *crtc,
10204 struct drm_framebuffer *fb,
10205 struct drm_i915_gem_object *obj,
10206 struct drm_i915_gem_request *req,
10207 uint32_t flags)
10208 {
10209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10210 u32 flip_mask, *cs;
10211
10212 cs = intel_ring_begin(req, 6);
10213 if (IS_ERR(cs))
10214 return PTR_ERR(cs);
10215
10216 if (intel_crtc->plane)
10217 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10218 else
10219 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10220 *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10221 *cs++ = MI_NOOP;
10222 *cs++ = MI_DISPLAY_FLIP_I915 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10223 *cs++ = fb->pitches[0];
10224 *cs++ = intel_crtc->flip_work->gtt_offset;
10225 *cs++ = MI_NOOP;
10226
10227 return 0;
10228 }
10229
10230 static int intel_gen4_queue_flip(struct drm_device *dev,
10231 struct drm_crtc *crtc,
10232 struct drm_framebuffer *fb,
10233 struct drm_i915_gem_object *obj,
10234 struct drm_i915_gem_request *req,
10235 uint32_t flags)
10236 {
10237 struct drm_i915_private *dev_priv = to_i915(dev);
10238 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10239 u32 pf, pipesrc, *cs;
10240
10241 cs = intel_ring_begin(req, 4);
10242 if (IS_ERR(cs))
10243 return PTR_ERR(cs);
10244
10245 /* i965+ uses the linear or tiled offsets from the
10246 * Display Registers (which do not change across a page-flip)
10247 * so we need only reprogram the base address.
10248 */
10249 *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10250 *cs++ = fb->pitches[0];
10251 *cs++ = intel_crtc->flip_work->gtt_offset |
10252 intel_fb_modifier_to_tiling(fb->modifier);
10253
10254 /* XXX Enabling the panel-fitter across page-flip is so far
10255 * untested on non-native modes, so ignore it for now.
10256 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10257 */
10258 pf = 0;
10259 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10260 *cs++ = pf | pipesrc;
10261
10262 return 0;
10263 }
10264
10265 static int intel_gen6_queue_flip(struct drm_device *dev,
10266 struct drm_crtc *crtc,
10267 struct drm_framebuffer *fb,
10268 struct drm_i915_gem_object *obj,
10269 struct drm_i915_gem_request *req,
10270 uint32_t flags)
10271 {
10272 struct drm_i915_private *dev_priv = to_i915(dev);
10273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10274 u32 pf, pipesrc, *cs;
10275
10276 cs = intel_ring_begin(req, 4);
10277 if (IS_ERR(cs))
10278 return PTR_ERR(cs);
10279
10280 *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10281 *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10282 *cs++ = intel_crtc->flip_work->gtt_offset;
10283
10284 /* Contrary to the suggestions in the documentation,
10285 * "Enable Panel Fitter" does not seem to be required when page
10286 * flipping with a non-native mode, and worse causes a normal
10287 * modeset to fail.
10288 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10289 */
10290 pf = 0;
10291 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10292 *cs++ = pf | pipesrc;
10293
10294 return 0;
10295 }
10296
10297 static int intel_gen7_queue_flip(struct drm_device *dev,
10298 struct drm_crtc *crtc,
10299 struct drm_framebuffer *fb,
10300 struct drm_i915_gem_object *obj,
10301 struct drm_i915_gem_request *req,
10302 uint32_t flags)
10303 {
10304 struct drm_i915_private *dev_priv = to_i915(dev);
10305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10306 u32 *cs, plane_bit = 0;
10307 int len, ret;
10308
10309 switch (intel_crtc->plane) {
10310 case PLANE_A:
10311 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10312 break;
10313 case PLANE_B:
10314 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10315 break;
10316 case PLANE_C:
10317 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10318 break;
10319 default:
10320 WARN_ONCE(1, "unknown plane in flip command\n");
10321 return -ENODEV;
10322 }
10323
10324 len = 4;
10325 if (req->engine->id == RCS) {
10326 len += 6;
10327 /*
10328 * On Gen 8, SRM is now taking an extra dword to accommodate
10329 * 48bits addresses, and we need a NOOP for the batch size to
10330 * stay even.
10331 */
10332 if (IS_GEN8(dev_priv))
10333 len += 2;
10334 }
10335
10336 /*
10337 * BSpec MI_DISPLAY_FLIP for IVB:
10338 * "The full packet must be contained within the same cache line."
10339 *
10340 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10341 * cacheline, if we ever start emitting more commands before
10342 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10343 * then do the cacheline alignment, and finally emit the
10344 * MI_DISPLAY_FLIP.
10345 */
10346 ret = intel_ring_cacheline_align(req);
10347 if (ret)
10348 return ret;
10349
10350 cs = intel_ring_begin(req, len);
10351 if (IS_ERR(cs))
10352 return PTR_ERR(cs);
10353
10354 /* Unmask the flip-done completion message. Note that the bspec says that
10355 * we should do this for both the BCS and RCS, and that we must not unmask
10356 * more than one flip event at any time (or ensure that one flip message
10357 * can be sent by waiting for flip-done prior to queueing new flips).
10358 * Experimentation says that BCS works despite DERRMR masking all
10359 * flip-done completion events and that unmasking all planes at once
10360 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10361 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10362 */
10363 if (req->engine->id == RCS) {
10364 *cs++ = MI_LOAD_REGISTER_IMM(1);
10365 *cs++ = i915_mmio_reg_offset(DERRMR);
10366 *cs++ = ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10367 DERRMR_PIPEB_PRI_FLIP_DONE |
10368 DERRMR_PIPEC_PRI_FLIP_DONE);
10369 if (IS_GEN8(dev_priv))
10370 *cs++ = MI_STORE_REGISTER_MEM_GEN8 |
10371 MI_SRM_LRM_GLOBAL_GTT;
10372 else
10373 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
10374 *cs++ = i915_mmio_reg_offset(DERRMR);
10375 *cs++ = i915_ggtt_offset(req->engine->scratch) + 256;
10376 if (IS_GEN8(dev_priv)) {
10377 *cs++ = 0;
10378 *cs++ = MI_NOOP;
10379 }
10380 }
10381
10382 *cs++ = MI_DISPLAY_FLIP_I915 | plane_bit;
10383 *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10384 *cs++ = intel_crtc->flip_work->gtt_offset;
10385 *cs++ = MI_NOOP;
10386
10387 return 0;
10388 }
10389
10390 static bool use_mmio_flip(struct intel_engine_cs *engine,
10391 struct drm_i915_gem_object *obj)
10392 {
10393 /*
10394 * This is not being used for older platforms, because
10395 * non-availability of flip done interrupt forces us to use
10396 * CS flips. Older platforms derive flip done using some clever
10397 * tricks involving the flip_pending status bits and vblank irqs.
10398 * So using MMIO flips there would disrupt this mechanism.
10399 */
10400
10401 if (engine == NULL)
10402 return true;
10403
10404 if (INTEL_GEN(engine->i915) < 5)
10405 return false;
10406
10407 if (i915.use_mmio_flip < 0)
10408 return false;
10409 else if (i915.use_mmio_flip > 0)
10410 return true;
10411 else if (i915.enable_execlists)
10412 return true;
10413
10414 return engine != i915_gem_object_last_write_engine(obj);
10415 }
10416
10417 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
10418 unsigned int rotation,
10419 struct intel_flip_work *work)
10420 {
10421 struct drm_device *dev = intel_crtc->base.dev;
10422 struct drm_i915_private *dev_priv = to_i915(dev);
10423 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10424 const enum pipe pipe = intel_crtc->pipe;
10425 u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
10426
10427 ctl = I915_READ(PLANE_CTL(pipe, 0));
10428 ctl &= ~PLANE_CTL_TILED_MASK;
10429 switch (fb->modifier) {
10430 case DRM_FORMAT_MOD_NONE:
10431 break;
10432 case I915_FORMAT_MOD_X_TILED:
10433 ctl |= PLANE_CTL_TILED_X;
10434 break;
10435 case I915_FORMAT_MOD_Y_TILED:
10436 ctl |= PLANE_CTL_TILED_Y;
10437 break;
10438 case I915_FORMAT_MOD_Yf_TILED:
10439 ctl |= PLANE_CTL_TILED_YF;
10440 break;
10441 default:
10442 MISSING_CASE(fb->modifier);
10443 }
10444
10445 /*
10446 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10447 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10448 */
10449 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10450 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10451
10452 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
10453 POSTING_READ(PLANE_SURF(pipe, 0));
10454 }
10455
10456 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
10457 struct intel_flip_work *work)
10458 {
10459 struct drm_device *dev = intel_crtc->base.dev;
10460 struct drm_i915_private *dev_priv = to_i915(dev);
10461 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10462 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
10463 u32 dspcntr;
10464
10465 dspcntr = I915_READ(reg);
10466
10467 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
10468 dspcntr |= DISPPLANE_TILED;
10469 else
10470 dspcntr &= ~DISPPLANE_TILED;
10471
10472 I915_WRITE(reg, dspcntr);
10473
10474 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
10475 POSTING_READ(DSPSURF(intel_crtc->plane));
10476 }
10477
10478 static void intel_mmio_flip_work_func(struct work_struct *w)
10479 {
10480 struct intel_flip_work *work =
10481 container_of(w, struct intel_flip_work, mmio_work);
10482 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10483 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10484 struct intel_framebuffer *intel_fb =
10485 to_intel_framebuffer(crtc->base.primary->fb);
10486 struct drm_i915_gem_object *obj = intel_fb->obj;
10487
10488 WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
10489
10490 intel_pipe_update_start(crtc);
10491
10492 if (INTEL_GEN(dev_priv) >= 9)
10493 skl_do_mmio_flip(crtc, work->rotation, work);
10494 else
10495 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10496 ilk_do_mmio_flip(crtc, work);
10497
10498 intel_pipe_update_end(crtc, work);
10499 }
10500
10501 static int intel_default_queue_flip(struct drm_device *dev,
10502 struct drm_crtc *crtc,
10503 struct drm_framebuffer *fb,
10504 struct drm_i915_gem_object *obj,
10505 struct drm_i915_gem_request *req,
10506 uint32_t flags)
10507 {
10508 return -ENODEV;
10509 }
10510
10511 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
10512 struct intel_crtc *intel_crtc,
10513 struct intel_flip_work *work)
10514 {
10515 u32 addr, vblank;
10516
10517 if (!atomic_read(&work->pending))
10518 return false;
10519
10520 smp_rmb();
10521
10522 vblank = intel_crtc_get_vblank_counter(intel_crtc);
10523 if (work->flip_ready_vblank == 0) {
10524 if (work->flip_queued_req &&
10525 !i915_gem_request_completed(work->flip_queued_req))
10526 return false;
10527
10528 work->flip_ready_vblank = vblank;
10529 }
10530
10531 if (vblank - work->flip_ready_vblank < 3)
10532 return false;
10533
10534 /* Potential stall - if we see that the flip has happened,
10535 * assume a missed interrupt. */
10536 if (INTEL_GEN(dev_priv) >= 4)
10537 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10538 else
10539 addr = I915_READ(DSPADDR(intel_crtc->plane));
10540
10541 /* There is a potential issue here with a false positive after a flip
10542 * to the same address. We could address this by checking for a
10543 * non-incrementing frame counter.
10544 */
10545 return addr == work->gtt_offset;
10546 }
10547
10548 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
10549 {
10550 struct drm_device *dev = &dev_priv->drm;
10551 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10552 struct intel_flip_work *work;
10553
10554 WARN_ON(!in_interrupt());
10555
10556 if (crtc == NULL)
10557 return;
10558
10559 spin_lock(&dev->event_lock);
10560 work = crtc->flip_work;
10561
10562 if (work != NULL && !is_mmio_work(work) &&
10563 __pageflip_stall_check_cs(dev_priv, crtc, work)) {
10564 WARN_ONCE(1,
10565 "Kicking stuck page flip: queued at %d, now %d\n",
10566 work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
10567 page_flip_completed(crtc);
10568 work = NULL;
10569 }
10570
10571 if (work != NULL && !is_mmio_work(work) &&
10572 intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
10573 intel_queue_rps_boost_for_request(work->flip_queued_req);
10574 spin_unlock(&dev->event_lock);
10575 }
10576
10577 __maybe_unused
10578 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10579 struct drm_framebuffer *fb,
10580 struct drm_pending_vblank_event *event,
10581 uint32_t page_flip_flags)
10582 {
10583 struct drm_device *dev = crtc->dev;
10584 struct drm_i915_private *dev_priv = to_i915(dev);
10585 struct drm_framebuffer *old_fb = crtc->primary->fb;
10586 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10588 struct drm_plane *primary = crtc->primary;
10589 enum pipe pipe = intel_crtc->pipe;
10590 struct intel_flip_work *work;
10591 struct intel_engine_cs *engine;
10592 bool mmio_flip;
10593 struct drm_i915_gem_request *request;
10594 struct i915_vma *vma;
10595 int ret;
10596
10597 /*
10598 * drm_mode_page_flip_ioctl() should already catch this, but double
10599 * check to be safe. In the future we may enable pageflipping from
10600 * a disabled primary plane.
10601 */
10602 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10603 return -EBUSY;
10604
10605 /* Can't change pixel format via MI display flips. */
10606 if (fb->format != crtc->primary->fb->format)
10607 return -EINVAL;
10608
10609 /*
10610 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10611 * Note that pitch changes could also affect these register.
10612 */
10613 if (INTEL_GEN(dev_priv) > 3 &&
10614 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10615 fb->pitches[0] != crtc->primary->fb->pitches[0]))
10616 return -EINVAL;
10617
10618 if (i915_terminally_wedged(&dev_priv->gpu_error))
10619 goto out_hang;
10620
10621 work = kzalloc(sizeof(*work), GFP_KERNEL);
10622 if (work == NULL)
10623 return -ENOMEM;
10624
10625 work->event = event;
10626 work->crtc = crtc;
10627 work->old_fb = old_fb;
10628 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
10629
10630 ret = drm_crtc_vblank_get(crtc);
10631 if (ret)
10632 goto free_work;
10633
10634 /* We borrow the event spin lock for protecting flip_work */
10635 spin_lock_irq(&dev->event_lock);
10636 if (intel_crtc->flip_work) {
10637 /* Before declaring the flip queue wedged, check if
10638 * the hardware completed the operation behind our backs.
10639 */
10640 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
10641 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10642 page_flip_completed(intel_crtc);
10643 } else {
10644 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10645 spin_unlock_irq(&dev->event_lock);
10646
10647 drm_crtc_vblank_put(crtc);
10648 kfree(work);
10649 return -EBUSY;
10650 }
10651 }
10652 intel_crtc->flip_work = work;
10653 spin_unlock_irq(&dev->event_lock);
10654
10655 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10656 flush_workqueue(dev_priv->wq);
10657
10658 /* Reference the objects for the scheduled work. */
10659 drm_framebuffer_reference(work->old_fb);
10660
10661 crtc->primary->fb = fb;
10662 update_state_fb(crtc->primary);
10663
10664 work->pending_flip_obj = i915_gem_object_get(obj);
10665
10666 ret = i915_mutex_lock_interruptible(dev);
10667 if (ret)
10668 goto cleanup;
10669
10670 intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
10671 if (i915_reset_backoff_or_wedged(&dev_priv->gpu_error)) {
10672 ret = -EIO;
10673 goto unlock;
10674 }
10675
10676 atomic_inc(&intel_crtc->unpin_work_count);
10677
10678 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
10679 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
10680
10681 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
10682 engine = dev_priv->engine[BCS];
10683 if (fb->modifier != old_fb->modifier)
10684 /* vlv: DISPLAY_FLIP fails to change tiling */
10685 engine = NULL;
10686 } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
10687 engine = dev_priv->engine[BCS];
10688 } else if (INTEL_GEN(dev_priv) >= 7) {
10689 engine = i915_gem_object_last_write_engine(obj);
10690 if (engine == NULL || engine->id != RCS)
10691 engine = dev_priv->engine[BCS];
10692 } else {
10693 engine = dev_priv->engine[RCS];
10694 }
10695
10696 mmio_flip = use_mmio_flip(engine, obj);
10697
10698 vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
10699 if (IS_ERR(vma)) {
10700 ret = PTR_ERR(vma);
10701 goto cleanup_pending;
10702 }
10703
10704 work->old_vma = to_intel_plane_state(primary->state)->vma;
10705 to_intel_plane_state(primary->state)->vma = vma;
10706
10707 work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset;
10708 work->rotation = crtc->primary->state->rotation;
10709
10710 /*
10711 * There's the potential that the next frame will not be compatible with
10712 * FBC, so we want to call pre_update() before the actual page flip.
10713 * The problem is that pre_update() caches some information about the fb
10714 * object, so we want to do this only after the object is pinned. Let's
10715 * be on the safe side and do this immediately before scheduling the
10716 * flip.
10717 */
10718 intel_fbc_pre_update(intel_crtc, intel_crtc->config,
10719 to_intel_plane_state(primary->state));
10720
10721 if (mmio_flip) {
10722 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
10723 queue_work(system_unbound_wq, &work->mmio_work);
10724 } else {
10725 request = i915_gem_request_alloc(engine,
10726 dev_priv->kernel_context);
10727 if (IS_ERR(request)) {
10728 ret = PTR_ERR(request);
10729 goto cleanup_unpin;
10730 }
10731
10732 ret = i915_gem_request_await_object(request, obj, false);
10733 if (ret)
10734 goto cleanup_request;
10735
10736 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
10737 page_flip_flags);
10738 if (ret)
10739 goto cleanup_request;
10740
10741 intel_mark_page_flip_active(intel_crtc, work);
10742
10743 work->flip_queued_req = i915_gem_request_get(request);
10744 i915_add_request(request);
10745 }
10746
10747 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
10748 i915_gem_track_fb(intel_fb_obj(old_fb), obj,
10749 to_intel_plane(primary)->frontbuffer_bit);
10750 mutex_unlock(&dev->struct_mutex);
10751
10752 intel_frontbuffer_flip_prepare(to_i915(dev),
10753 to_intel_plane(primary)->frontbuffer_bit);
10754
10755 trace_i915_flip_request(intel_crtc->plane, obj);
10756
10757 return 0;
10758
10759 cleanup_request:
10760 i915_add_request(request);
10761 cleanup_unpin:
10762 to_intel_plane_state(primary->state)->vma = work->old_vma;
10763 intel_unpin_fb_vma(vma);
10764 cleanup_pending:
10765 atomic_dec(&intel_crtc->unpin_work_count);
10766 unlock:
10767 mutex_unlock(&dev->struct_mutex);
10768 cleanup:
10769 crtc->primary->fb = old_fb;
10770 update_state_fb(crtc->primary);
10771
10772 i915_gem_object_put(obj);
10773 drm_framebuffer_unreference(work->old_fb);
10774
10775 spin_lock_irq(&dev->event_lock);
10776 intel_crtc->flip_work = NULL;
10777 spin_unlock_irq(&dev->event_lock);
10778
10779 drm_crtc_vblank_put(crtc);
10780 free_work:
10781 kfree(work);
10782
10783 if (ret == -EIO) {
10784 struct drm_atomic_state *state;
10785 struct drm_plane_state *plane_state;
10786
10787 out_hang:
10788 state = drm_atomic_state_alloc(dev);
10789 if (!state)
10790 return -ENOMEM;
10791 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
10792
10793 retry:
10794 plane_state = drm_atomic_get_plane_state(state, primary);
10795 ret = PTR_ERR_OR_ZERO(plane_state);
10796 if (!ret) {
10797 drm_atomic_set_fb_for_plane(plane_state, fb);
10798
10799 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
10800 if (!ret)
10801 ret = drm_atomic_commit(state);
10802 }
10803
10804 if (ret == -EDEADLK) {
10805 drm_modeset_backoff(state->acquire_ctx);
10806 drm_atomic_state_clear(state);
10807 goto retry;
10808 }
10809
10810 drm_atomic_state_put(state);
10811
10812 if (ret == 0 && event) {
10813 spin_lock_irq(&dev->event_lock);
10814 drm_crtc_send_vblank_event(crtc, event);
10815 spin_unlock_irq(&dev->event_lock);
10816 }
10817 }
10818 return ret;
10819 }
10820
10821
10822 /**
10823 * intel_wm_need_update - Check whether watermarks need updating
10824 * @plane: drm plane
10825 * @state: new plane state
10826 *
10827 * Check current plane state versus the new one to determine whether
10828 * watermarks need to be recalculated.
10829 *
10830 * Returns true or false.
10831 */
10832 static bool intel_wm_need_update(struct drm_plane *plane,
10833 struct drm_plane_state *state)
10834 {
10835 struct intel_plane_state *new = to_intel_plane_state(state);
10836 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10837
10838 /* Update watermarks on tiling or size changes. */
10839 if (new->base.visible != cur->base.visible)
10840 return true;
10841
10842 if (!cur->base.fb || !new->base.fb)
10843 return false;
10844
10845 if (cur->base.fb->modifier != new->base.fb->modifier ||
10846 cur->base.rotation != new->base.rotation ||
10847 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10848 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10849 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10850 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10851 return true;
10852
10853 return false;
10854 }
10855
10856 static bool needs_scaling(struct intel_plane_state *state)
10857 {
10858 int src_w = drm_rect_width(&state->base.src) >> 16;
10859 int src_h = drm_rect_height(&state->base.src) >> 16;
10860 int dst_w = drm_rect_width(&state->base.dst);
10861 int dst_h = drm_rect_height(&state->base.dst);
10862
10863 return (src_w != dst_w || src_h != dst_h);
10864 }
10865
10866 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
10867 struct drm_plane_state *plane_state)
10868 {
10869 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10870 struct drm_crtc *crtc = crtc_state->crtc;
10871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10872 struct intel_plane *plane = to_intel_plane(plane_state->plane);
10873 struct drm_device *dev = crtc->dev;
10874 struct drm_i915_private *dev_priv = to_i915(dev);
10875 struct intel_plane_state *old_plane_state =
10876 to_intel_plane_state(plane->base.state);
10877 bool mode_changed = needs_modeset(crtc_state);
10878 bool was_crtc_enabled = crtc->state->active;
10879 bool is_crtc_enabled = crtc_state->active;
10880 bool turn_off, turn_on, visible, was_visible;
10881 struct drm_framebuffer *fb = plane_state->fb;
10882 int ret;
10883
10884 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10885 ret = skl_update_scaler_plane(
10886 to_intel_crtc_state(crtc_state),
10887 to_intel_plane_state(plane_state));
10888 if (ret)
10889 return ret;
10890 }
10891
10892 was_visible = old_plane_state->base.visible;
10893 visible = plane_state->visible;
10894
10895 if (!was_crtc_enabled && WARN_ON(was_visible))
10896 was_visible = false;
10897
10898 /*
10899 * Visibility is calculated as if the crtc was on, but
10900 * after scaler setup everything depends on it being off
10901 * when the crtc isn't active.
10902 *
10903 * FIXME this is wrong for watermarks. Watermarks should also
10904 * be computed as if the pipe would be active. Perhaps move
10905 * per-plane wm computation to the .check_plane() hook, and
10906 * only combine the results from all planes in the current place?
10907 */
10908 if (!is_crtc_enabled) {
10909 plane_state->visible = visible = false;
10910 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10911 }
10912
10913 if (!was_visible && !visible)
10914 return 0;
10915
10916 if (fb != old_plane_state->base.fb)
10917 pipe_config->fb_changed = true;
10918
10919 turn_off = was_visible && (!visible || mode_changed);
10920 turn_on = visible && (!was_visible || mode_changed);
10921
10922 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10923 intel_crtc->base.base.id, intel_crtc->base.name,
10924 plane->base.base.id, plane->base.name,
10925 fb ? fb->base.id : -1);
10926
10927 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10928 plane->base.base.id, plane->base.name,
10929 was_visible, visible,
10930 turn_off, turn_on, mode_changed);
10931
10932 if (turn_on) {
10933 if (INTEL_GEN(dev_priv) < 5)
10934 pipe_config->update_wm_pre = true;
10935
10936 /* must disable cxsr around plane enable/disable */
10937 if (plane->id != PLANE_CURSOR)
10938 pipe_config->disable_cxsr = true;
10939 } else if (turn_off) {
10940 if (INTEL_GEN(dev_priv) < 5)
10941 pipe_config->update_wm_post = true;
10942
10943 /* must disable cxsr around plane enable/disable */
10944 if (plane->id != PLANE_CURSOR)
10945 pipe_config->disable_cxsr = true;
10946 } else if (intel_wm_need_update(&plane->base, plane_state)) {
10947 if (INTEL_GEN(dev_priv) < 5) {
10948 /* FIXME bollocks */
10949 pipe_config->update_wm_pre = true;
10950 pipe_config->update_wm_post = true;
10951 }
10952 }
10953
10954 if (visible || was_visible)
10955 pipe_config->fb_bits |= plane->frontbuffer_bit;
10956
10957 /*
10958 * WaCxSRDisabledForSpriteScaling:ivb
10959 *
10960 * cstate->update_wm was already set above, so this flag will
10961 * take effect when we commit and program watermarks.
10962 */
10963 if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10964 needs_scaling(to_intel_plane_state(plane_state)) &&
10965 !needs_scaling(old_plane_state))
10966 pipe_config->disable_lp_wm = true;
10967
10968 return 0;
10969 }
10970
10971 static bool encoders_cloneable(const struct intel_encoder *a,
10972 const struct intel_encoder *b)
10973 {
10974 /* masks could be asymmetric, so check both ways */
10975 return a == b || (a->cloneable & (1 << b->type) &&
10976 b->cloneable & (1 << a->type));
10977 }
10978
10979 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10980 struct intel_crtc *crtc,
10981 struct intel_encoder *encoder)
10982 {
10983 struct intel_encoder *source_encoder;
10984 struct drm_connector *connector;
10985 struct drm_connector_state *connector_state;
10986 int i;
10987
10988 for_each_new_connector_in_state(state, connector, connector_state, i) {
10989 if (connector_state->crtc != &crtc->base)
10990 continue;
10991
10992 source_encoder =
10993 to_intel_encoder(connector_state->best_encoder);
10994 if (!encoders_cloneable(encoder, source_encoder))
10995 return false;
10996 }
10997
10998 return true;
10999 }
11000
11001 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11002 struct drm_crtc_state *crtc_state)
11003 {
11004 struct drm_device *dev = crtc->dev;
11005 struct drm_i915_private *dev_priv = to_i915(dev);
11006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11007 struct intel_crtc_state *pipe_config =
11008 to_intel_crtc_state(crtc_state);
11009 struct drm_atomic_state *state = crtc_state->state;
11010 int ret;
11011 bool mode_changed = needs_modeset(crtc_state);
11012
11013 if (mode_changed && !crtc_state->active)
11014 pipe_config->update_wm_post = true;
11015
11016 if (mode_changed && crtc_state->enable &&
11017 dev_priv->display.crtc_compute_clock &&
11018 !WARN_ON(pipe_config->shared_dpll)) {
11019 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11020 pipe_config);
11021 if (ret)
11022 return ret;
11023 }
11024
11025 if (crtc_state->color_mgmt_changed) {
11026 ret = intel_color_check(crtc, crtc_state);
11027 if (ret)
11028 return ret;
11029
11030 /*
11031 * Changing color management on Intel hardware is
11032 * handled as part of planes update.
11033 */
11034 crtc_state->planes_changed = true;
11035 }
11036
11037 ret = 0;
11038 if (dev_priv->display.compute_pipe_wm) {
11039 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11040 if (ret) {
11041 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11042 return ret;
11043 }
11044 }
11045
11046 if (dev_priv->display.compute_intermediate_wm &&
11047 !to_intel_atomic_state(state)->skip_intermediate_wm) {
11048 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11049 return 0;
11050
11051 /*
11052 * Calculate 'intermediate' watermarks that satisfy both the
11053 * old state and the new state. We can program these
11054 * immediately.
11055 */
11056 ret = dev_priv->display.compute_intermediate_wm(dev,
11057 intel_crtc,
11058 pipe_config);
11059 if (ret) {
11060 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11061 return ret;
11062 }
11063 } else if (dev_priv->display.compute_intermediate_wm) {
11064 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
11065 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
11066 }
11067
11068 if (INTEL_GEN(dev_priv) >= 9) {
11069 if (mode_changed)
11070 ret = skl_update_scaler_crtc(pipe_config);
11071
11072 if (!ret)
11073 ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
11074 pipe_config);
11075 }
11076
11077 return ret;
11078 }
11079
11080 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11081 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11082 .atomic_begin = intel_begin_crtc_commit,
11083 .atomic_flush = intel_finish_crtc_commit,
11084 .atomic_check = intel_crtc_atomic_check,
11085 };
11086
11087 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11088 {
11089 struct intel_connector *connector;
11090 struct drm_connector_list_iter conn_iter;
11091
11092 drm_connector_list_iter_begin(dev, &conn_iter);
11093 for_each_intel_connector_iter(connector, &conn_iter) {
11094 if (connector->base.state->crtc)
11095 drm_connector_unreference(&connector->base);
11096
11097 if (connector->base.encoder) {
11098 connector->base.state->best_encoder =
11099 connector->base.encoder;
11100 connector->base.state->crtc =
11101 connector->base.encoder->crtc;
11102
11103 drm_connector_reference(&connector->base);
11104 } else {
11105 connector->base.state->best_encoder = NULL;
11106 connector->base.state->crtc = NULL;
11107 }
11108 }
11109 drm_connector_list_iter_end(&conn_iter);
11110 }
11111
11112 static void
11113 connected_sink_compute_bpp(struct intel_connector *connector,
11114 struct intel_crtc_state *pipe_config)
11115 {
11116 const struct drm_display_info *info = &connector->base.display_info;
11117 int bpp = pipe_config->pipe_bpp;
11118
11119 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11120 connector->base.base.id,
11121 connector->base.name);
11122
11123 /* Don't use an invalid EDID bpc value */
11124 if (info->bpc != 0 && info->bpc * 3 < bpp) {
11125 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11126 bpp, info->bpc * 3);
11127 pipe_config->pipe_bpp = info->bpc * 3;
11128 }
11129
11130 /* Clamp bpp to 8 on screens without EDID 1.4 */
11131 if (info->bpc == 0 && bpp > 24) {
11132 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11133 bpp);
11134 pipe_config->pipe_bpp = 24;
11135 }
11136 }
11137
11138 static int
11139 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11140 struct intel_crtc_state *pipe_config)
11141 {
11142 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11143 struct drm_atomic_state *state;
11144 struct drm_connector *connector;
11145 struct drm_connector_state *connector_state;
11146 int bpp, i;
11147
11148 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
11149 IS_CHERRYVIEW(dev_priv)))
11150 bpp = 10*3;
11151 else if (INTEL_GEN(dev_priv) >= 5)
11152 bpp = 12*3;
11153 else
11154 bpp = 8*3;
11155
11156
11157 pipe_config->pipe_bpp = bpp;
11158
11159 state = pipe_config->base.state;
11160
11161 /* Clamp display bpp to EDID value */
11162 for_each_new_connector_in_state(state, connector, connector_state, i) {
11163 if (connector_state->crtc != &crtc->base)
11164 continue;
11165
11166 connected_sink_compute_bpp(to_intel_connector(connector),
11167 pipe_config);
11168 }
11169
11170 return bpp;
11171 }
11172
11173 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11174 {
11175 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11176 "type: 0x%x flags: 0x%x\n",
11177 mode->crtc_clock,
11178 mode->crtc_hdisplay, mode->crtc_hsync_start,
11179 mode->crtc_hsync_end, mode->crtc_htotal,
11180 mode->crtc_vdisplay, mode->crtc_vsync_start,
11181 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11182 }
11183
11184 static inline void
11185 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
11186 unsigned int lane_count, struct intel_link_m_n *m_n)
11187 {
11188 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11189 id, lane_count,
11190 m_n->gmch_m, m_n->gmch_n,
11191 m_n->link_m, m_n->link_n, m_n->tu);
11192 }
11193
11194 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11195 struct intel_crtc_state *pipe_config,
11196 const char *context)
11197 {
11198 struct drm_device *dev = crtc->base.dev;
11199 struct drm_i915_private *dev_priv = to_i915(dev);
11200 struct drm_plane *plane;
11201 struct intel_plane *intel_plane;
11202 struct intel_plane_state *state;
11203 struct drm_framebuffer *fb;
11204
11205 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
11206 crtc->base.base.id, crtc->base.name, context);
11207
11208 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
11209 transcoder_name(pipe_config->cpu_transcoder),
11210 pipe_config->pipe_bpp, pipe_config->dither);
11211
11212 if (pipe_config->has_pch_encoder)
11213 intel_dump_m_n_config(pipe_config, "fdi",
11214 pipe_config->fdi_lanes,
11215 &pipe_config->fdi_m_n);
11216
11217 if (intel_crtc_has_dp_encoder(pipe_config)) {
11218 intel_dump_m_n_config(pipe_config, "dp m_n",
11219 pipe_config->lane_count, &pipe_config->dp_m_n);
11220 if (pipe_config->has_drrs)
11221 intel_dump_m_n_config(pipe_config, "dp m2_n2",
11222 pipe_config->lane_count,
11223 &pipe_config->dp_m2_n2);
11224 }
11225
11226 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11227 pipe_config->has_audio, pipe_config->has_infoframe);
11228
11229 DRM_DEBUG_KMS("requested mode:\n");
11230 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11231 DRM_DEBUG_KMS("adjusted mode:\n");
11232 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11233 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11234 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
11235 pipe_config->port_clock,
11236 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
11237 pipe_config->pixel_rate);
11238
11239 if (INTEL_GEN(dev_priv) >= 9)
11240 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11241 crtc->num_scalers,
11242 pipe_config->scaler_state.scaler_users,
11243 pipe_config->scaler_state.scaler_id);
11244
11245 if (HAS_GMCH_DISPLAY(dev_priv))
11246 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11247 pipe_config->gmch_pfit.control,
11248 pipe_config->gmch_pfit.pgm_ratios,
11249 pipe_config->gmch_pfit.lvds_border_bits);
11250 else
11251 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11252 pipe_config->pch_pfit.pos,
11253 pipe_config->pch_pfit.size,
11254 enableddisabled(pipe_config->pch_pfit.enabled));
11255
11256 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
11257 pipe_config->ips_enabled, pipe_config->double_wide);
11258
11259 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
11260
11261 DRM_DEBUG_KMS("planes on this crtc\n");
11262 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11263 struct drm_format_name_buf format_name;
11264 intel_plane = to_intel_plane(plane);
11265 if (intel_plane->pipe != crtc->pipe)
11266 continue;
11267
11268 state = to_intel_plane_state(plane->state);
11269 fb = state->base.fb;
11270 if (!fb) {
11271 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
11272 plane->base.id, plane->name, state->scaler_id);
11273 continue;
11274 }
11275
11276 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
11277 plane->base.id, plane->name,
11278 fb->base.id, fb->width, fb->height,
11279 drm_get_format_name(fb->format->format, &format_name));
11280 if (INTEL_GEN(dev_priv) >= 9)
11281 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
11282 state->scaler_id,
11283 state->base.src.x1 >> 16,
11284 state->base.src.y1 >> 16,
11285 drm_rect_width(&state->base.src) >> 16,
11286 drm_rect_height(&state->base.src) >> 16,
11287 state->base.dst.x1, state->base.dst.y1,
11288 drm_rect_width(&state->base.dst),
11289 drm_rect_height(&state->base.dst));
11290 }
11291 }
11292
11293 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11294 {
11295 struct drm_device *dev = state->dev;
11296 struct drm_connector *connector;
11297 unsigned int used_ports = 0;
11298 unsigned int used_mst_ports = 0;
11299
11300 /*
11301 * Walk the connector list instead of the encoder
11302 * list to detect the problem on ddi platforms
11303 * where there's just one encoder per digital port.
11304 */
11305 drm_for_each_connector(connector, dev) {
11306 struct drm_connector_state *connector_state;
11307 struct intel_encoder *encoder;
11308
11309 connector_state = drm_atomic_get_existing_connector_state(state, connector);
11310 if (!connector_state)
11311 connector_state = connector->state;
11312
11313 if (!connector_state->best_encoder)
11314 continue;
11315
11316 encoder = to_intel_encoder(connector_state->best_encoder);
11317
11318 WARN_ON(!connector_state->crtc);
11319
11320 switch (encoder->type) {
11321 unsigned int port_mask;
11322 case INTEL_OUTPUT_UNKNOWN:
11323 if (WARN_ON(!HAS_DDI(to_i915(dev))))
11324 break;
11325 case INTEL_OUTPUT_DP:
11326 case INTEL_OUTPUT_HDMI:
11327 case INTEL_OUTPUT_EDP:
11328 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11329
11330 /* the same port mustn't appear more than once */
11331 if (used_ports & port_mask)
11332 return false;
11333
11334 used_ports |= port_mask;
11335 break;
11336 case INTEL_OUTPUT_DP_MST:
11337 used_mst_ports |=
11338 1 << enc_to_mst(&encoder->base)->primary->port;
11339 break;
11340 default:
11341 break;
11342 }
11343 }
11344
11345 /* can't mix MST and SST/HDMI on the same port */
11346 if (used_ports & used_mst_ports)
11347 return false;
11348
11349 return true;
11350 }
11351
11352 static void
11353 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11354 {
11355 struct drm_i915_private *dev_priv =
11356 to_i915(crtc_state->base.crtc->dev);
11357 struct intel_crtc_scaler_state scaler_state;
11358 struct intel_dpll_hw_state dpll_hw_state;
11359 struct intel_shared_dpll *shared_dpll;
11360 struct intel_crtc_wm_state wm_state;
11361 bool force_thru;
11362
11363 /* FIXME: before the switch to atomic started, a new pipe_config was
11364 * kzalloc'd. Code that depends on any field being zero should be
11365 * fixed, so that the crtc_state can be safely duplicated. For now,
11366 * only fields that are know to not cause problems are preserved. */
11367
11368 scaler_state = crtc_state->scaler_state;
11369 shared_dpll = crtc_state->shared_dpll;
11370 dpll_hw_state = crtc_state->dpll_hw_state;
11371 force_thru = crtc_state->pch_pfit.force_thru;
11372 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11373 wm_state = crtc_state->wm;
11374
11375 /* Keep base drm_crtc_state intact, only clear our extended struct */
11376 BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
11377 memset(&crtc_state->base + 1, 0,
11378 sizeof(*crtc_state) - sizeof(crtc_state->base));
11379
11380 crtc_state->scaler_state = scaler_state;
11381 crtc_state->shared_dpll = shared_dpll;
11382 crtc_state->dpll_hw_state = dpll_hw_state;
11383 crtc_state->pch_pfit.force_thru = force_thru;
11384 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11385 crtc_state->wm = wm_state;
11386 }
11387
11388 static int
11389 intel_modeset_pipe_config(struct drm_crtc *crtc,
11390 struct intel_crtc_state *pipe_config)
11391 {
11392 struct drm_atomic_state *state = pipe_config->base.state;
11393 struct intel_encoder *encoder;
11394 struct drm_connector *connector;
11395 struct drm_connector_state *connector_state;
11396 int base_bpp, ret = -EINVAL;
11397 int i;
11398 bool retry = true;
11399
11400 clear_intel_crtc_state(pipe_config);
11401
11402 pipe_config->cpu_transcoder =
11403 (enum transcoder) to_intel_crtc(crtc)->pipe;
11404
11405 /*
11406 * Sanitize sync polarity flags based on requested ones. If neither
11407 * positive or negative polarity is requested, treat this as meaning
11408 * negative polarity.
11409 */
11410 if (!(pipe_config->base.adjusted_mode.flags &
11411 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11412 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11413
11414 if (!(pipe_config->base.adjusted_mode.flags &
11415 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11416 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11417
11418 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11419 pipe_config);
11420 if (base_bpp < 0)
11421 goto fail;
11422
11423 /*
11424 * Determine the real pipe dimensions. Note that stereo modes can
11425 * increase the actual pipe size due to the frame doubling and
11426 * insertion of additional space for blanks between the frame. This
11427 * is stored in the crtc timings. We use the requested mode to do this
11428 * computation to clearly distinguish it from the adjusted mode, which
11429 * can be changed by the connectors in the below retry loop.
11430 */
11431 drm_mode_get_hv_timing(&pipe_config->base.mode,
11432 &pipe_config->pipe_src_w,
11433 &pipe_config->pipe_src_h);
11434
11435 for_each_new_connector_in_state(state, connector, connector_state, i) {
11436 if (connector_state->crtc != crtc)
11437 continue;
11438
11439 encoder = to_intel_encoder(connector_state->best_encoder);
11440
11441 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11442 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11443 goto fail;
11444 }
11445
11446 /*
11447 * Determine output_types before calling the .compute_config()
11448 * hooks so that the hooks can use this information safely.
11449 */
11450 pipe_config->output_types |= 1 << encoder->type;
11451 }
11452
11453 encoder_retry:
11454 /* Ensure the port clock defaults are reset when retrying. */
11455 pipe_config->port_clock = 0;
11456 pipe_config->pixel_multiplier = 1;
11457
11458 /* Fill in default crtc timings, allow encoders to overwrite them. */
11459 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11460 CRTC_STEREO_DOUBLE);
11461
11462 /* Pass our mode to the connectors and the CRTC to give them a chance to
11463 * adjust it according to limitations or connector properties, and also
11464 * a chance to reject the mode entirely.
11465 */
11466 for_each_new_connector_in_state(state, connector, connector_state, i) {
11467 if (connector_state->crtc != crtc)
11468 continue;
11469
11470 encoder = to_intel_encoder(connector_state->best_encoder);
11471
11472 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
11473 DRM_DEBUG_KMS("Encoder config failure\n");
11474 goto fail;
11475 }
11476 }
11477
11478 /* Set default port clock if not overwritten by the encoder. Needs to be
11479 * done afterwards in case the encoder adjusts the mode. */
11480 if (!pipe_config->port_clock)
11481 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11482 * pipe_config->pixel_multiplier;
11483
11484 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11485 if (ret < 0) {
11486 DRM_DEBUG_KMS("CRTC fixup failed\n");
11487 goto fail;
11488 }
11489
11490 if (ret == RETRY) {
11491 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11492 ret = -EINVAL;
11493 goto fail;
11494 }
11495
11496 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11497 retry = false;
11498 goto encoder_retry;
11499 }
11500
11501 /* Dithering seems to not pass-through bits correctly when it should, so
11502 * only enable it on 6bpc panels and when its not a compliance
11503 * test requesting 6bpc video pattern.
11504 */
11505 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11506 !pipe_config->dither_force_disable;
11507 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11508 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11509
11510 fail:
11511 return ret;
11512 }
11513
11514 static void
11515 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
11516 {
11517 struct drm_crtc *crtc;
11518 struct drm_crtc_state *new_crtc_state;
11519 int i;
11520
11521 /* Double check state. */
11522 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
11523 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
11524
11525 /* Update hwmode for vblank functions */
11526 if (new_crtc_state->active)
11527 crtc->hwmode = new_crtc_state->adjusted_mode;
11528 else
11529 crtc->hwmode.crtc_clock = 0;
11530
11531 /*
11532 * Update legacy state to satisfy fbc code. This can
11533 * be removed when fbc uses the atomic state.
11534 */
11535 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11536 struct drm_plane_state *plane_state = crtc->primary->state;
11537
11538 crtc->primary->fb = plane_state->fb;
11539 crtc->x = plane_state->src_x >> 16;
11540 crtc->y = plane_state->src_y >> 16;
11541 }
11542 }
11543 }
11544
11545 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11546 {
11547 int diff;
11548
11549 if (clock1 == clock2)
11550 return true;
11551
11552 if (!clock1 || !clock2)
11553 return false;
11554
11555 diff = abs(clock1 - clock2);
11556
11557 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11558 return true;
11559
11560 return false;
11561 }
11562
11563 static bool
11564 intel_compare_m_n(unsigned int m, unsigned int n,
11565 unsigned int m2, unsigned int n2,
11566 bool exact)
11567 {
11568 if (m == m2 && n == n2)
11569 return true;
11570
11571 if (exact || !m || !n || !m2 || !n2)
11572 return false;
11573
11574 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11575
11576 if (n > n2) {
11577 while (n > n2) {
11578 m2 <<= 1;
11579 n2 <<= 1;
11580 }
11581 } else if (n < n2) {
11582 while (n < n2) {
11583 m <<= 1;
11584 n <<= 1;
11585 }
11586 }
11587
11588 if (n != n2)
11589 return false;
11590
11591 return intel_fuzzy_clock_check(m, m2);
11592 }
11593
11594 static bool
11595 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11596 struct intel_link_m_n *m2_n2,
11597 bool adjust)
11598 {
11599 if (m_n->tu == m2_n2->tu &&
11600 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11601 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11602 intel_compare_m_n(m_n->link_m, m_n->link_n,
11603 m2_n2->link_m, m2_n2->link_n, !adjust)) {
11604 if (adjust)
11605 *m2_n2 = *m_n;
11606
11607 return true;
11608 }
11609
11610 return false;
11611 }
11612
11613 static void __printf(3, 4)
11614 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11615 {
11616 char *level;
11617 unsigned int category;
11618 struct va_format vaf;
11619 va_list args;
11620
11621 if (adjust) {
11622 level = KERN_DEBUG;
11623 category = DRM_UT_KMS;
11624 } else {
11625 level = KERN_ERR;
11626 category = DRM_UT_NONE;
11627 }
11628
11629 va_start(args, format);
11630 vaf.fmt = format;
11631 vaf.va = &args;
11632
11633 drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11634
11635 va_end(args);
11636 }
11637
11638 static bool
11639 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11640 struct intel_crtc_state *current_config,
11641 struct intel_crtc_state *pipe_config,
11642 bool adjust)
11643 {
11644 bool ret = true;
11645
11646 #define PIPE_CONF_CHECK_X(name) \
11647 if (current_config->name != pipe_config->name) { \
11648 pipe_config_err(adjust, __stringify(name), \
11649 "(expected 0x%08x, found 0x%08x)\n", \
11650 current_config->name, \
11651 pipe_config->name); \
11652 ret = false; \
11653 }
11654
11655 #define PIPE_CONF_CHECK_I(name) \
11656 if (current_config->name != pipe_config->name) { \
11657 pipe_config_err(adjust, __stringify(name), \
11658 "(expected %i, found %i)\n", \
11659 current_config->name, \
11660 pipe_config->name); \
11661 ret = false; \
11662 }
11663
11664 #define PIPE_CONF_CHECK_P(name) \
11665 if (current_config->name != pipe_config->name) { \
11666 pipe_config_err(adjust, __stringify(name), \
11667 "(expected %p, found %p)\n", \
11668 current_config->name, \
11669 pipe_config->name); \
11670 ret = false; \
11671 }
11672
11673 #define PIPE_CONF_CHECK_M_N(name) \
11674 if (!intel_compare_link_m_n(&current_config->name, \
11675 &pipe_config->name,\
11676 adjust)) { \
11677 pipe_config_err(adjust, __stringify(name), \
11678 "(expected tu %i gmch %i/%i link %i/%i, " \
11679 "found tu %i, gmch %i/%i link %i/%i)\n", \
11680 current_config->name.tu, \
11681 current_config->name.gmch_m, \
11682 current_config->name.gmch_n, \
11683 current_config->name.link_m, \
11684 current_config->name.link_n, \
11685 pipe_config->name.tu, \
11686 pipe_config->name.gmch_m, \
11687 pipe_config->name.gmch_n, \
11688 pipe_config->name.link_m, \
11689 pipe_config->name.link_n); \
11690 ret = false; \
11691 }
11692
11693 /* This is required for BDW+ where there is only one set of registers for
11694 * switching between high and low RR.
11695 * This macro can be used whenever a comparison has to be made between one
11696 * hw state and multiple sw state variables.
11697 */
11698 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11699 if (!intel_compare_link_m_n(&current_config->name, \
11700 &pipe_config->name, adjust) && \
11701 !intel_compare_link_m_n(&current_config->alt_name, \
11702 &pipe_config->name, adjust)) { \
11703 pipe_config_err(adjust, __stringify(name), \
11704 "(expected tu %i gmch %i/%i link %i/%i, " \
11705 "or tu %i gmch %i/%i link %i/%i, " \
11706 "found tu %i, gmch %i/%i link %i/%i)\n", \
11707 current_config->name.tu, \
11708 current_config->name.gmch_m, \
11709 current_config->name.gmch_n, \
11710 current_config->name.link_m, \
11711 current_config->name.link_n, \
11712 current_config->alt_name.tu, \
11713 current_config->alt_name.gmch_m, \
11714 current_config->alt_name.gmch_n, \
11715 current_config->alt_name.link_m, \
11716 current_config->alt_name.link_n, \
11717 pipe_config->name.tu, \
11718 pipe_config->name.gmch_m, \
11719 pipe_config->name.gmch_n, \
11720 pipe_config->name.link_m, \
11721 pipe_config->name.link_n); \
11722 ret = false; \
11723 }
11724
11725 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11726 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11727 pipe_config_err(adjust, __stringify(name), \
11728 "(%x) (expected %i, found %i)\n", \
11729 (mask), \
11730 current_config->name & (mask), \
11731 pipe_config->name & (mask)); \
11732 ret = false; \
11733 }
11734
11735 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11736 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11737 pipe_config_err(adjust, __stringify(name), \
11738 "(expected %i, found %i)\n", \
11739 current_config->name, \
11740 pipe_config->name); \
11741 ret = false; \
11742 }
11743
11744 #define PIPE_CONF_QUIRK(quirk) \
11745 ((current_config->quirks | pipe_config->quirks) & (quirk))
11746
11747 PIPE_CONF_CHECK_I(cpu_transcoder);
11748
11749 PIPE_CONF_CHECK_I(has_pch_encoder);
11750 PIPE_CONF_CHECK_I(fdi_lanes);
11751 PIPE_CONF_CHECK_M_N(fdi_m_n);
11752
11753 PIPE_CONF_CHECK_I(lane_count);
11754 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11755
11756 if (INTEL_GEN(dev_priv) < 8) {
11757 PIPE_CONF_CHECK_M_N(dp_m_n);
11758
11759 if (current_config->has_drrs)
11760 PIPE_CONF_CHECK_M_N(dp_m2_n2);
11761 } else
11762 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11763
11764 PIPE_CONF_CHECK_X(output_types);
11765
11766 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11767 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11768 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11769 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11770 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11771 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11772
11773 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11774 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11775 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11776 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11777 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11778 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11779
11780 PIPE_CONF_CHECK_I(pixel_multiplier);
11781 PIPE_CONF_CHECK_I(has_hdmi_sink);
11782 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11783 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11784 PIPE_CONF_CHECK_I(limited_color_range);
11785 PIPE_CONF_CHECK_I(has_infoframe);
11786
11787 PIPE_CONF_CHECK_I(has_audio);
11788
11789 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11790 DRM_MODE_FLAG_INTERLACE);
11791
11792 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11793 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11794 DRM_MODE_FLAG_PHSYNC);
11795 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11796 DRM_MODE_FLAG_NHSYNC);
11797 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11798 DRM_MODE_FLAG_PVSYNC);
11799 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11800 DRM_MODE_FLAG_NVSYNC);
11801 }
11802
11803 PIPE_CONF_CHECK_X(gmch_pfit.control);
11804 /* pfit ratios are autocomputed by the hw on gen4+ */
11805 if (INTEL_GEN(dev_priv) < 4)
11806 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11807 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11808
11809 if (!adjust) {
11810 PIPE_CONF_CHECK_I(pipe_src_w);
11811 PIPE_CONF_CHECK_I(pipe_src_h);
11812
11813 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11814 if (current_config->pch_pfit.enabled) {
11815 PIPE_CONF_CHECK_X(pch_pfit.pos);
11816 PIPE_CONF_CHECK_X(pch_pfit.size);
11817 }
11818
11819 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11820 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11821 }
11822
11823 /* BDW+ don't expose a synchronous way to read the state */
11824 if (IS_HASWELL(dev_priv))
11825 PIPE_CONF_CHECK_I(ips_enabled);
11826
11827 PIPE_CONF_CHECK_I(double_wide);
11828
11829 PIPE_CONF_CHECK_P(shared_dpll);
11830 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11831 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11832 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11833 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11834 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11835 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11836 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11837 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11838 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11839
11840 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11841 PIPE_CONF_CHECK_X(dsi_pll.div);
11842
11843 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11844 PIPE_CONF_CHECK_I(pipe_bpp);
11845
11846 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11847 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11848
11849 #undef PIPE_CONF_CHECK_X
11850 #undef PIPE_CONF_CHECK_I
11851 #undef PIPE_CONF_CHECK_P
11852 #undef PIPE_CONF_CHECK_FLAGS
11853 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11854 #undef PIPE_CONF_QUIRK
11855
11856 return ret;
11857 }
11858
11859 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11860 const struct intel_crtc_state *pipe_config)
11861 {
11862 if (pipe_config->has_pch_encoder) {
11863 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11864 &pipe_config->fdi_m_n);
11865 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11866
11867 /*
11868 * FDI already provided one idea for the dotclock.
11869 * Yell if the encoder disagrees.
11870 */
11871 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11872 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11873 fdi_dotclock, dotclock);
11874 }
11875 }
11876
11877 static void verify_wm_state(struct drm_crtc *crtc,
11878 struct drm_crtc_state *new_state)
11879 {
11880 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11881 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11882 struct skl_pipe_wm hw_wm, *sw_wm;
11883 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11884 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11885 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11886 const enum pipe pipe = intel_crtc->pipe;
11887 int plane, level, max_level = ilk_wm_max_level(dev_priv);
11888
11889 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11890 return;
11891
11892 skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11893 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11894
11895 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11896 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11897
11898 /* planes */
11899 for_each_universal_plane(dev_priv, pipe, plane) {
11900 hw_plane_wm = &hw_wm.planes[plane];
11901 sw_plane_wm = &sw_wm->planes[plane];
11902
11903 /* Watermarks */
11904 for (level = 0; level <= max_level; level++) {
11905 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11906 &sw_plane_wm->wm[level]))
11907 continue;
11908
11909 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11910 pipe_name(pipe), plane + 1, level,
11911 sw_plane_wm->wm[level].plane_en,
11912 sw_plane_wm->wm[level].plane_res_b,
11913 sw_plane_wm->wm[level].plane_res_l,
11914 hw_plane_wm->wm[level].plane_en,
11915 hw_plane_wm->wm[level].plane_res_b,
11916 hw_plane_wm->wm[level].plane_res_l);
11917 }
11918
11919 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11920 &sw_plane_wm->trans_wm)) {
11921 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11922 pipe_name(pipe), plane + 1,
11923 sw_plane_wm->trans_wm.plane_en,
11924 sw_plane_wm->trans_wm.plane_res_b,
11925 sw_plane_wm->trans_wm.plane_res_l,
11926 hw_plane_wm->trans_wm.plane_en,
11927 hw_plane_wm->trans_wm.plane_res_b,
11928 hw_plane_wm->trans_wm.plane_res_l);
11929 }
11930
11931 /* DDB */
11932 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11933 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11934
11935 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11936 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11937 pipe_name(pipe), plane + 1,
11938 sw_ddb_entry->start, sw_ddb_entry->end,
11939 hw_ddb_entry->start, hw_ddb_entry->end);
11940 }
11941 }
11942
11943 /*
11944 * cursor
11945 * If the cursor plane isn't active, we may not have updated it's ddb
11946 * allocation. In that case since the ddb allocation will be updated
11947 * once the plane becomes visible, we can skip this check
11948 */
11949 if (intel_crtc->cursor_addr) {
11950 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11951 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11952
11953 /* Watermarks */
11954 for (level = 0; level <= max_level; level++) {
11955 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11956 &sw_plane_wm->wm[level]))
11957 continue;
11958
11959 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11960 pipe_name(pipe), level,
11961 sw_plane_wm->wm[level].plane_en,
11962 sw_plane_wm->wm[level].plane_res_b,
11963 sw_plane_wm->wm[level].plane_res_l,
11964 hw_plane_wm->wm[level].plane_en,
11965 hw_plane_wm->wm[level].plane_res_b,
11966 hw_plane_wm->wm[level].plane_res_l);
11967 }
11968
11969 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11970 &sw_plane_wm->trans_wm)) {
11971 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11972 pipe_name(pipe),
11973 sw_plane_wm->trans_wm.plane_en,
11974 sw_plane_wm->trans_wm.plane_res_b,
11975 sw_plane_wm->trans_wm.plane_res_l,
11976 hw_plane_wm->trans_wm.plane_en,
11977 hw_plane_wm->trans_wm.plane_res_b,
11978 hw_plane_wm->trans_wm.plane_res_l);
11979 }
11980
11981 /* DDB */
11982 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11983 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11984
11985 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11986 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11987 pipe_name(pipe),
11988 sw_ddb_entry->start, sw_ddb_entry->end,
11989 hw_ddb_entry->start, hw_ddb_entry->end);
11990 }
11991 }
11992 }
11993
11994 static void
11995 verify_connector_state(struct drm_device *dev,
11996 struct drm_atomic_state *state,
11997 struct drm_crtc *crtc)
11998 {
11999 struct drm_connector *connector;
12000 struct drm_connector_state *new_conn_state;
12001 int i;
12002
12003 for_each_new_connector_in_state(state, connector, new_conn_state, i) {
12004 struct drm_encoder *encoder = connector->encoder;
12005
12006 if (new_conn_state->crtc != crtc)
12007 continue;
12008
12009 intel_connector_verify_state(to_intel_connector(connector));
12010
12011 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
12012 "connector's atomic encoder doesn't match legacy encoder\n");
12013 }
12014 }
12015
12016 static void
12017 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
12018 {
12019 struct intel_encoder *encoder;
12020 struct drm_connector *connector;
12021 struct drm_connector_state *old_conn_state, *new_conn_state;
12022 int i;
12023
12024 for_each_intel_encoder(dev, encoder) {
12025 bool enabled = false, found = false;
12026 enum pipe pipe;
12027
12028 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12029 encoder->base.base.id,
12030 encoder->base.name);
12031
12032 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
12033 new_conn_state, i) {
12034 if (old_conn_state->best_encoder == &encoder->base)
12035 found = true;
12036
12037 if (new_conn_state->best_encoder != &encoder->base)
12038 continue;
12039 found = enabled = true;
12040
12041 I915_STATE_WARN(new_conn_state->crtc !=
12042 encoder->base.crtc,
12043 "connector's crtc doesn't match encoder crtc\n");
12044 }
12045
12046 if (!found)
12047 continue;
12048
12049 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12050 "encoder's enabled state mismatch "
12051 "(expected %i, found %i)\n",
12052 !!encoder->base.crtc, enabled);
12053
12054 if (!encoder->base.crtc) {
12055 bool active;
12056
12057 active = encoder->get_hw_state(encoder, &pipe);
12058 I915_STATE_WARN(active,
12059 "encoder detached but still enabled on pipe %c.\n",
12060 pipe_name(pipe));
12061 }
12062 }
12063 }
12064
12065 static void
12066 verify_crtc_state(struct drm_crtc *crtc,
12067 struct drm_crtc_state *old_crtc_state,
12068 struct drm_crtc_state *new_crtc_state)
12069 {
12070 struct drm_device *dev = crtc->dev;
12071 struct drm_i915_private *dev_priv = to_i915(dev);
12072 struct intel_encoder *encoder;
12073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12074 struct intel_crtc_state *pipe_config, *sw_config;
12075 struct drm_atomic_state *old_state;
12076 bool active;
12077
12078 old_state = old_crtc_state->state;
12079 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
12080 pipe_config = to_intel_crtc_state(old_crtc_state);
12081 memset(pipe_config, 0, sizeof(*pipe_config));
12082 pipe_config->base.crtc = crtc;
12083 pipe_config->base.state = old_state;
12084
12085 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
12086
12087 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12088
12089 /* hw state is inconsistent with the pipe quirk */
12090 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12091 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12092 active = new_crtc_state->active;
12093
12094 I915_STATE_WARN(new_crtc_state->active != active,
12095 "crtc active state doesn't match with hw state "
12096 "(expected %i, found %i)\n", new_crtc_state->active, active);
12097
12098 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12099 "transitional active state does not match atomic hw state "
12100 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12101
12102 for_each_encoder_on_crtc(dev, crtc, encoder) {
12103 enum pipe pipe;
12104
12105 active = encoder->get_hw_state(encoder, &pipe);
12106 I915_STATE_WARN(active != new_crtc_state->active,
12107 "[ENCODER:%i] active %i with crtc active %i\n",
12108 encoder->base.base.id, active, new_crtc_state->active);
12109
12110 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12111 "Encoder connected to wrong pipe %c\n",
12112 pipe_name(pipe));
12113
12114 if (active) {
12115 pipe_config->output_types |= 1 << encoder->type;
12116 encoder->get_config(encoder, pipe_config);
12117 }
12118 }
12119
12120 intel_crtc_compute_pixel_rate(pipe_config);
12121
12122 if (!new_crtc_state->active)
12123 return;
12124
12125 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12126
12127 sw_config = to_intel_crtc_state(crtc->state);
12128 if (!intel_pipe_config_compare(dev_priv, sw_config,
12129 pipe_config, false)) {
12130 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12131 intel_dump_pipe_config(intel_crtc, pipe_config,
12132 "[hw state]");
12133 intel_dump_pipe_config(intel_crtc, sw_config,
12134 "[sw state]");
12135 }
12136 }
12137
12138 static void
12139 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12140 struct intel_shared_dpll *pll,
12141 struct drm_crtc *crtc,
12142 struct drm_crtc_state *new_state)
12143 {
12144 struct intel_dpll_hw_state dpll_hw_state;
12145 unsigned crtc_mask;
12146 bool active;
12147
12148 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12149
12150 DRM_DEBUG_KMS("%s\n", pll->name);
12151
12152 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12153
12154 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12155 I915_STATE_WARN(!pll->on && pll->active_mask,
12156 "pll in active use but not on in sw tracking\n");
12157 I915_STATE_WARN(pll->on && !pll->active_mask,
12158 "pll is on but not used by any active crtc\n");
12159 I915_STATE_WARN(pll->on != active,
12160 "pll on state mismatch (expected %i, found %i)\n",
12161 pll->on, active);
12162 }
12163
12164 if (!crtc) {
12165 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
12166 "more active pll users than references: %x vs %x\n",
12167 pll->active_mask, pll->state.crtc_mask);
12168
12169 return;
12170 }
12171
12172 crtc_mask = 1 << drm_crtc_index(crtc);
12173
12174 if (new_state->active)
12175 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12176 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12177 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12178 else
12179 I915_STATE_WARN(pll->active_mask & crtc_mask,
12180 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12181 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12182
12183 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
12184 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12185 crtc_mask, pll->state.crtc_mask);
12186
12187 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
12188 &dpll_hw_state,
12189 sizeof(dpll_hw_state)),
12190 "pll hw state mismatch\n");
12191 }
12192
12193 static void
12194 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12195 struct drm_crtc_state *old_crtc_state,
12196 struct drm_crtc_state *new_crtc_state)
12197 {
12198 struct drm_i915_private *dev_priv = to_i915(dev);
12199 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12200 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12201
12202 if (new_state->shared_dpll)
12203 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
12204
12205 if (old_state->shared_dpll &&
12206 old_state->shared_dpll != new_state->shared_dpll) {
12207 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
12208 struct intel_shared_dpll *pll = old_state->shared_dpll;
12209
12210 I915_STATE_WARN(pll->active_mask & crtc_mask,
12211 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12212 pipe_name(drm_crtc_index(crtc)));
12213 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
12214 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12215 pipe_name(drm_crtc_index(crtc)));
12216 }
12217 }
12218
12219 static void
12220 intel_modeset_verify_crtc(struct drm_crtc *crtc,
12221 struct drm_atomic_state *state,
12222 struct drm_crtc_state *old_state,
12223 struct drm_crtc_state *new_state)
12224 {
12225 if (!needs_modeset(new_state) &&
12226 !to_intel_crtc_state(new_state)->update_pipe)
12227 return;
12228
12229 verify_wm_state(crtc, new_state);
12230 verify_connector_state(crtc->dev, state, crtc);
12231 verify_crtc_state(crtc, old_state, new_state);
12232 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
12233 }
12234
12235 static void
12236 verify_disabled_dpll_state(struct drm_device *dev)
12237 {
12238 struct drm_i915_private *dev_priv = to_i915(dev);
12239 int i;
12240
12241 for (i = 0; i < dev_priv->num_shared_dpll; i++)
12242 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12243 }
12244
12245 static void
12246 intel_modeset_verify_disabled(struct drm_device *dev,
12247 struct drm_atomic_state *state)
12248 {
12249 verify_encoder_state(dev, state);
12250 verify_connector_state(dev, state, NULL);
12251 verify_disabled_dpll_state(dev);
12252 }
12253
12254 static void update_scanline_offset(struct intel_crtc *crtc)
12255 {
12256 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12257
12258 /*
12259 * The scanline counter increments at the leading edge of hsync.
12260 *
12261 * On most platforms it starts counting from vtotal-1 on the
12262 * first active line. That means the scanline counter value is
12263 * always one less than what we would expect. Ie. just after
12264 * start of vblank, which also occurs at start of hsync (on the
12265 * last active line), the scanline counter will read vblank_start-1.
12266 *
12267 * On gen2 the scanline counter starts counting from 1 instead
12268 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12269 * to keep the value positive), instead of adding one.
12270 *
12271 * On HSW+ the behaviour of the scanline counter depends on the output
12272 * type. For DP ports it behaves like most other platforms, but on HDMI
12273 * there's an extra 1 line difference. So we need to add two instead of
12274 * one to the value.
12275 */
12276 if (IS_GEN2(dev_priv)) {
12277 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12278 int vtotal;
12279
12280 vtotal = adjusted_mode->crtc_vtotal;
12281 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12282 vtotal /= 2;
12283
12284 crtc->scanline_offset = vtotal - 1;
12285 } else if (HAS_DDI(dev_priv) &&
12286 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
12287 crtc->scanline_offset = 2;
12288 } else
12289 crtc->scanline_offset = 1;
12290 }
12291
12292 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12293 {
12294 struct drm_device *dev = state->dev;
12295 struct drm_i915_private *dev_priv = to_i915(dev);
12296 struct drm_crtc *crtc;
12297 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12298 int i;
12299
12300 if (!dev_priv->display.crtc_compute_clock)
12301 return;
12302
12303 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12304 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12305 struct intel_shared_dpll *old_dpll =
12306 to_intel_crtc_state(old_crtc_state)->shared_dpll;
12307
12308 if (!needs_modeset(new_crtc_state))
12309 continue;
12310
12311 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
12312
12313 if (!old_dpll)
12314 continue;
12315
12316 intel_release_shared_dpll(old_dpll, intel_crtc, state);
12317 }
12318 }
12319
12320 /*
12321 * This implements the workaround described in the "notes" section of the mode
12322 * set sequence documentation. When going from no pipes or single pipe to
12323 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12324 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12325 */
12326 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12327 {
12328 struct drm_crtc_state *crtc_state;
12329 struct intel_crtc *intel_crtc;
12330 struct drm_crtc *crtc;
12331 struct intel_crtc_state *first_crtc_state = NULL;
12332 struct intel_crtc_state *other_crtc_state = NULL;
12333 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12334 int i;
12335
12336 /* look at all crtc's that are going to be enabled in during modeset */
12337 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12338 intel_crtc = to_intel_crtc(crtc);
12339
12340 if (!crtc_state->active || !needs_modeset(crtc_state))
12341 continue;
12342
12343 if (first_crtc_state) {
12344 other_crtc_state = to_intel_crtc_state(crtc_state);
12345 break;
12346 } else {
12347 first_crtc_state = to_intel_crtc_state(crtc_state);
12348 first_pipe = intel_crtc->pipe;
12349 }
12350 }
12351
12352 /* No workaround needed? */
12353 if (!first_crtc_state)
12354 return 0;
12355
12356 /* w/a possibly needed, check how many crtc's are already enabled. */
12357 for_each_intel_crtc(state->dev, intel_crtc) {
12358 struct intel_crtc_state *pipe_config;
12359
12360 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12361 if (IS_ERR(pipe_config))
12362 return PTR_ERR(pipe_config);
12363
12364 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12365
12366 if (!pipe_config->base.active ||
12367 needs_modeset(&pipe_config->base))
12368 continue;
12369
12370 /* 2 or more enabled crtcs means no need for w/a */
12371 if (enabled_pipe != INVALID_PIPE)
12372 return 0;
12373
12374 enabled_pipe = intel_crtc->pipe;
12375 }
12376
12377 if (enabled_pipe != INVALID_PIPE)
12378 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12379 else if (other_crtc_state)
12380 other_crtc_state->hsw_workaround_pipe = first_pipe;
12381
12382 return 0;
12383 }
12384
12385 static int intel_lock_all_pipes(struct drm_atomic_state *state)
12386 {
12387 struct drm_crtc *crtc;
12388
12389 /* Add all pipes to the state */
12390 for_each_crtc(state->dev, crtc) {
12391 struct drm_crtc_state *crtc_state;
12392
12393 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12394 if (IS_ERR(crtc_state))
12395 return PTR_ERR(crtc_state);
12396 }
12397
12398 return 0;
12399 }
12400
12401 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12402 {
12403 struct drm_crtc *crtc;
12404
12405 /*
12406 * Add all pipes to the state, and force
12407 * a modeset on all the active ones.
12408 */
12409 for_each_crtc(state->dev, crtc) {
12410 struct drm_crtc_state *crtc_state;
12411 int ret;
12412
12413 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12414 if (IS_ERR(crtc_state))
12415 return PTR_ERR(crtc_state);
12416
12417 if (!crtc_state->active || needs_modeset(crtc_state))
12418 continue;
12419
12420 crtc_state->mode_changed = true;
12421
12422 ret = drm_atomic_add_affected_connectors(state, crtc);
12423 if (ret)
12424 return ret;
12425
12426 ret = drm_atomic_add_affected_planes(state, crtc);
12427 if (ret)
12428 return ret;
12429 }
12430
12431 return 0;
12432 }
12433
12434 static int intel_modeset_checks(struct drm_atomic_state *state)
12435 {
12436 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12437 struct drm_i915_private *dev_priv = to_i915(state->dev);
12438 struct drm_crtc *crtc;
12439 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12440 int ret = 0, i;
12441
12442 if (!check_digital_port_conflicts(state)) {
12443 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12444 return -EINVAL;
12445 }
12446
12447 intel_state->modeset = true;
12448 intel_state->active_crtcs = dev_priv->active_crtcs;
12449 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12450 intel_state->cdclk.actual = dev_priv->cdclk.actual;
12451
12452 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12453 if (new_crtc_state->active)
12454 intel_state->active_crtcs |= 1 << i;
12455 else
12456 intel_state->active_crtcs &= ~(1 << i);
12457
12458 if (old_crtc_state->active != new_crtc_state->active)
12459 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12460 }
12461
12462 /*
12463 * See if the config requires any additional preparation, e.g.
12464 * to adjust global state with pipes off. We need to do this
12465 * here so we can get the modeset_pipe updated config for the new
12466 * mode set on this crtc. For other crtcs we need to use the
12467 * adjusted_mode bits in the crtc directly.
12468 */
12469 if (dev_priv->display.modeset_calc_cdclk) {
12470 ret = dev_priv->display.modeset_calc_cdclk(state);
12471 if (ret < 0)
12472 return ret;
12473
12474 /*
12475 * Writes to dev_priv->cdclk.logical must protected by
12476 * holding all the crtc locks, even if we don't end up
12477 * touching the hardware
12478 */
12479 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
12480 &intel_state->cdclk.logical)) {
12481 ret = intel_lock_all_pipes(state);
12482 if (ret < 0)
12483 return ret;
12484 }
12485
12486 /* All pipes must be switched off while we change the cdclk. */
12487 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
12488 &intel_state->cdclk.actual)) {
12489 ret = intel_modeset_all_pipes(state);
12490 if (ret < 0)
12491 return ret;
12492 }
12493
12494 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12495 intel_state->cdclk.logical.cdclk,
12496 intel_state->cdclk.actual.cdclk);
12497 } else {
12498 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12499 }
12500
12501 intel_modeset_clear_plls(state);
12502
12503 if (IS_HASWELL(dev_priv))
12504 return haswell_mode_set_planes_workaround(state);
12505
12506 return 0;
12507 }
12508
12509 /*
12510 * Handle calculation of various watermark data at the end of the atomic check
12511 * phase. The code here should be run after the per-crtc and per-plane 'check'
12512 * handlers to ensure that all derived state has been updated.
12513 */
12514 static int calc_watermark_data(struct drm_atomic_state *state)
12515 {
12516 struct drm_device *dev = state->dev;
12517 struct drm_i915_private *dev_priv = to_i915(dev);
12518
12519 /* Is there platform-specific watermark information to calculate? */
12520 if (dev_priv->display.compute_global_watermarks)
12521 return dev_priv->display.compute_global_watermarks(state);
12522
12523 return 0;
12524 }
12525
12526 /**
12527 * intel_atomic_check - validate state object
12528 * @dev: drm device
12529 * @state: state to validate
12530 */
12531 static int intel_atomic_check(struct drm_device *dev,
12532 struct drm_atomic_state *state)
12533 {
12534 struct drm_i915_private *dev_priv = to_i915(dev);
12535 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12536 struct drm_crtc *crtc;
12537 struct drm_crtc_state *old_crtc_state, *crtc_state;
12538 int ret, i;
12539 bool any_ms = false;
12540
12541 ret = drm_atomic_helper_check_modeset(dev, state);
12542 if (ret)
12543 return ret;
12544
12545 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12546 struct intel_crtc_state *pipe_config =
12547 to_intel_crtc_state(crtc_state);
12548
12549 /* Catch I915_MODE_FLAG_INHERITED */
12550 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
12551 crtc_state->mode_changed = true;
12552
12553 if (!needs_modeset(crtc_state))
12554 continue;
12555
12556 if (!crtc_state->enable) {
12557 any_ms = true;
12558 continue;
12559 }
12560
12561 /* FIXME: For only active_changed we shouldn't need to do any
12562 * state recomputation at all. */
12563
12564 ret = drm_atomic_add_affected_connectors(state, crtc);
12565 if (ret)
12566 return ret;
12567
12568 ret = intel_modeset_pipe_config(crtc, pipe_config);
12569 if (ret) {
12570 intel_dump_pipe_config(to_intel_crtc(crtc),
12571 pipe_config, "[failed]");
12572 return ret;
12573 }
12574
12575 if (i915.fastboot &&
12576 intel_pipe_config_compare(dev_priv,
12577 to_intel_crtc_state(old_crtc_state),
12578 pipe_config, true)) {
12579 crtc_state->mode_changed = false;
12580 pipe_config->update_pipe = true;
12581 }
12582
12583 if (needs_modeset(crtc_state))
12584 any_ms = true;
12585
12586 ret = drm_atomic_add_affected_planes(state, crtc);
12587 if (ret)
12588 return ret;
12589
12590 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12591 needs_modeset(crtc_state) ?
12592 "[modeset]" : "[fastset]");
12593 }
12594
12595 if (any_ms) {
12596 ret = intel_modeset_checks(state);
12597
12598 if (ret)
12599 return ret;
12600 } else {
12601 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12602 }
12603
12604 ret = drm_atomic_helper_check_planes(dev, state);
12605 if (ret)
12606 return ret;
12607
12608 intel_fbc_choose_crtc(dev_priv, state);
12609 return calc_watermark_data(state);
12610 }
12611
12612 static int intel_atomic_prepare_commit(struct drm_device *dev,
12613 struct drm_atomic_state *state)
12614 {
12615 struct drm_i915_private *dev_priv = to_i915(dev);
12616 struct drm_crtc_state *crtc_state;
12617 struct drm_crtc *crtc;
12618 int i, ret;
12619
12620 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12621 if (state->legacy_cursor_update)
12622 continue;
12623
12624 ret = intel_crtc_wait_for_pending_flips(crtc);
12625 if (ret)
12626 return ret;
12627
12628 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
12629 flush_workqueue(dev_priv->wq);
12630 }
12631
12632 ret = mutex_lock_interruptible(&dev->struct_mutex);
12633 if (ret)
12634 return ret;
12635
12636 ret = drm_atomic_helper_prepare_planes(dev, state);
12637 mutex_unlock(&dev->struct_mutex);
12638
12639 return ret;
12640 }
12641
12642 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12643 {
12644 struct drm_device *dev = crtc->base.dev;
12645
12646 if (!dev->max_vblank_count)
12647 return drm_accurate_vblank_count(&crtc->base);
12648
12649 return dev->driver->get_vblank_counter(dev, crtc->pipe);
12650 }
12651
12652 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
12653 struct drm_i915_private *dev_priv,
12654 unsigned crtc_mask)
12655 {
12656 unsigned last_vblank_count[I915_MAX_PIPES];
12657 enum pipe pipe;
12658 int ret;
12659
12660 if (!crtc_mask)
12661 return;
12662
12663 for_each_pipe(dev_priv, pipe) {
12664 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12665 pipe);
12666
12667 if (!((1 << pipe) & crtc_mask))
12668 continue;
12669
12670 ret = drm_crtc_vblank_get(&crtc->base);
12671 if (WARN_ON(ret != 0)) {
12672 crtc_mask &= ~(1 << pipe);
12673 continue;
12674 }
12675
12676 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
12677 }
12678
12679 for_each_pipe(dev_priv, pipe) {
12680 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12681 pipe);
12682 long lret;
12683
12684 if (!((1 << pipe) & crtc_mask))
12685 continue;
12686
12687 lret = wait_event_timeout(dev->vblank[pipe].queue,
12688 last_vblank_count[pipe] !=
12689 drm_crtc_vblank_count(&crtc->base),
12690 msecs_to_jiffies(50));
12691
12692 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
12693
12694 drm_crtc_vblank_put(&crtc->base);
12695 }
12696 }
12697
12698 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
12699 {
12700 /* fb updated, need to unpin old fb */
12701 if (crtc_state->fb_changed)
12702 return true;
12703
12704 /* wm changes, need vblank before final wm's */
12705 if (crtc_state->update_wm_post)
12706 return true;
12707
12708 if (crtc_state->wm.need_postvbl_update)
12709 return true;
12710
12711 return false;
12712 }
12713
12714 static void intel_update_crtc(struct drm_crtc *crtc,
12715 struct drm_atomic_state *state,
12716 struct drm_crtc_state *old_crtc_state,
12717 struct drm_crtc_state *new_crtc_state,
12718 unsigned int *crtc_vblank_mask)
12719 {
12720 struct drm_device *dev = crtc->dev;
12721 struct drm_i915_private *dev_priv = to_i915(dev);
12722 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12723 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12724 bool modeset = needs_modeset(new_crtc_state);
12725
12726 if (modeset) {
12727 update_scanline_offset(intel_crtc);
12728 dev_priv->display.crtc_enable(pipe_config, state);
12729 } else {
12730 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12731 pipe_config);
12732 }
12733
12734 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12735 intel_fbc_enable(
12736 intel_crtc, pipe_config,
12737 to_intel_plane_state(crtc->primary->state));
12738 }
12739
12740 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12741
12742 if (needs_vblank_wait(pipe_config))
12743 *crtc_vblank_mask |= drm_crtc_mask(crtc);
12744 }
12745
12746 static void intel_update_crtcs(struct drm_atomic_state *state,
12747 unsigned int *crtc_vblank_mask)
12748 {
12749 struct drm_crtc *crtc;
12750 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12751 int i;
12752
12753 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12754 if (!new_crtc_state->active)
12755 continue;
12756
12757 intel_update_crtc(crtc, state, old_crtc_state,
12758 new_crtc_state, crtc_vblank_mask);
12759 }
12760 }
12761
12762 static void skl_update_crtcs(struct drm_atomic_state *state,
12763 unsigned int *crtc_vblank_mask)
12764 {
12765 struct drm_i915_private *dev_priv = to_i915(state->dev);
12766 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12767 struct drm_crtc *crtc;
12768 struct intel_crtc *intel_crtc;
12769 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12770 struct intel_crtc_state *cstate;
12771 unsigned int updated = 0;
12772 bool progress;
12773 enum pipe pipe;
12774 int i;
12775
12776 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12777
12778 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12779 /* ignore allocations for crtc's that have been turned off. */
12780 if (new_crtc_state->active)
12781 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12782
12783 /*
12784 * Whenever the number of active pipes changes, we need to make sure we
12785 * update the pipes in the right order so that their ddb allocations
12786 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12787 * cause pipe underruns and other bad stuff.
12788 */
12789 do {
12790 progress = false;
12791
12792 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12793 bool vbl_wait = false;
12794 unsigned int cmask = drm_crtc_mask(crtc);
12795
12796 intel_crtc = to_intel_crtc(crtc);
12797 cstate = to_intel_crtc_state(crtc->state);
12798 pipe = intel_crtc->pipe;
12799
12800 if (updated & cmask || !cstate->base.active)
12801 continue;
12802
12803 if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
12804 continue;
12805
12806 updated |= cmask;
12807 entries[i] = &cstate->wm.skl.ddb;
12808
12809 /*
12810 * If this is an already active pipe, it's DDB changed,
12811 * and this isn't the last pipe that needs updating
12812 * then we need to wait for a vblank to pass for the
12813 * new ddb allocation to take effect.
12814 */
12815 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12816 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12817 !new_crtc_state->active_changed &&
12818 intel_state->wm_results.dirty_pipes != updated)
12819 vbl_wait = true;
12820
12821 intel_update_crtc(crtc, state, old_crtc_state,
12822 new_crtc_state, crtc_vblank_mask);
12823
12824 if (vbl_wait)
12825 intel_wait_for_vblank(dev_priv, pipe);
12826
12827 progress = true;
12828 }
12829 } while (progress);
12830 }
12831
12832 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12833 {
12834 struct intel_atomic_state *state, *next;
12835 struct llist_node *freed;
12836
12837 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12838 llist_for_each_entry_safe(state, next, freed, freed)
12839 drm_atomic_state_put(&state->base);
12840 }
12841
12842 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12843 {
12844 struct drm_i915_private *dev_priv =
12845 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12846
12847 intel_atomic_helper_free_state(dev_priv);
12848 }
12849
12850 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12851 {
12852 struct drm_device *dev = state->dev;
12853 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12854 struct drm_i915_private *dev_priv = to_i915(dev);
12855 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12856 struct drm_crtc *crtc;
12857 struct intel_crtc_state *intel_cstate;
12858 bool hw_check = intel_state->modeset;
12859 u64 put_domains[I915_MAX_PIPES] = {};
12860 unsigned crtc_vblank_mask = 0;
12861 int i;
12862
12863 drm_atomic_helper_wait_for_dependencies(state);
12864
12865 if (intel_state->modeset)
12866 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12867
12868 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12870
12871 if (needs_modeset(new_crtc_state) ||
12872 to_intel_crtc_state(new_crtc_state)->update_pipe) {
12873 hw_check = true;
12874
12875 put_domains[to_intel_crtc(crtc)->pipe] =
12876 modeset_get_crtc_power_domains(crtc,
12877 to_intel_crtc_state(new_crtc_state));
12878 }
12879
12880 if (!needs_modeset(new_crtc_state))
12881 continue;
12882
12883 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12884 to_intel_crtc_state(new_crtc_state));
12885
12886 if (old_crtc_state->active) {
12887 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12888 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12889 intel_crtc->active = false;
12890 intel_fbc_disable(intel_crtc);
12891 intel_disable_shared_dpll(intel_crtc);
12892
12893 /*
12894 * Underruns don't always raise
12895 * interrupts, so check manually.
12896 */
12897 intel_check_cpu_fifo_underruns(dev_priv);
12898 intel_check_pch_fifo_underruns(dev_priv);
12899
12900 if (!crtc->state->active) {
12901 /*
12902 * Make sure we don't call initial_watermarks
12903 * for ILK-style watermark updates.
12904 *
12905 * No clue what this is supposed to achieve.
12906 */
12907 if (INTEL_GEN(dev_priv) >= 9)
12908 dev_priv->display.initial_watermarks(intel_state,
12909 to_intel_crtc_state(crtc->state));
12910 }
12911 }
12912 }
12913
12914 /* Only after disabling all output pipelines that will be changed can we
12915 * update the the output configuration. */
12916 intel_modeset_update_crtc_state(state);
12917
12918 if (intel_state->modeset) {
12919 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12920
12921 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12922
12923 /*
12924 * SKL workaround: bspec recommends we disable the SAGV when we
12925 * have more then one pipe enabled
12926 */
12927 if (!intel_can_enable_sagv(state))
12928 intel_disable_sagv(dev_priv);
12929
12930 intel_modeset_verify_disabled(dev, state);
12931 }
12932
12933 /* Complete the events for pipes that have now been disabled */
12934 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12935 bool modeset = needs_modeset(new_crtc_state);
12936
12937 /* Complete events for now disable pipes here. */
12938 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12939 spin_lock_irq(&dev->event_lock);
12940 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12941 spin_unlock_irq(&dev->event_lock);
12942
12943 new_crtc_state->event = NULL;
12944 }
12945 }
12946
12947 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12948 dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
12949
12950 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12951 * already, but still need the state for the delayed optimization. To
12952 * fix this:
12953 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12954 * - schedule that vblank worker _before_ calling hw_done
12955 * - at the start of commit_tail, cancel it _synchrously
12956 * - switch over to the vblank wait helper in the core after that since
12957 * we don't need out special handling any more.
12958 */
12959 if (!state->legacy_cursor_update)
12960 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
12961
12962 /*
12963 * Now that the vblank has passed, we can go ahead and program the
12964 * optimal watermarks on platforms that need two-step watermark
12965 * programming.
12966 *
12967 * TODO: Move this (and other cleanup) to an async worker eventually.
12968 */
12969 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12970 intel_cstate = to_intel_crtc_state(new_crtc_state);
12971
12972 if (dev_priv->display.optimize_watermarks)
12973 dev_priv->display.optimize_watermarks(intel_state,
12974 intel_cstate);
12975 }
12976
12977 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12978 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12979
12980 if (put_domains[i])
12981 modeset_put_power_domains(dev_priv, put_domains[i]);
12982
12983 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12984 }
12985
12986 if (intel_state->modeset && intel_can_enable_sagv(state))
12987 intel_enable_sagv(dev_priv);
12988
12989 drm_atomic_helper_commit_hw_done(state);
12990
12991 if (intel_state->modeset)
12992 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12993
12994 mutex_lock(&dev->struct_mutex);
12995 drm_atomic_helper_cleanup_planes(dev, state);
12996 mutex_unlock(&dev->struct_mutex);
12997
12998 drm_atomic_helper_commit_cleanup_done(state);
12999
13000 drm_atomic_state_put(state);
13001
13002 /* As one of the primary mmio accessors, KMS has a high likelihood
13003 * of triggering bugs in unclaimed access. After we finish
13004 * modesetting, see if an error has been flagged, and if so
13005 * enable debugging for the next modeset - and hope we catch
13006 * the culprit.
13007 *
13008 * XXX note that we assume display power is on at this point.
13009 * This might hold true now but we need to add pm helper to check
13010 * unclaimed only when the hardware is on, as atomic commits
13011 * can happen also when the device is completely off.
13012 */
13013 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13014
13015 intel_atomic_helper_free_state(dev_priv);
13016 }
13017
13018 static void intel_atomic_commit_work(struct work_struct *work)
13019 {
13020 struct drm_atomic_state *state =
13021 container_of(work, struct drm_atomic_state, commit_work);
13022
13023 intel_atomic_commit_tail(state);
13024 }
13025
13026 static int __i915_sw_fence_call
13027 intel_atomic_commit_ready(struct i915_sw_fence *fence,
13028 enum i915_sw_fence_notify notify)
13029 {
13030 struct intel_atomic_state *state =
13031 container_of(fence, struct intel_atomic_state, commit_ready);
13032
13033 switch (notify) {
13034 case FENCE_COMPLETE:
13035 if (state->base.commit_work.func)
13036 queue_work(system_unbound_wq, &state->base.commit_work);
13037 break;
13038
13039 case FENCE_FREE:
13040 {
13041 struct intel_atomic_helper *helper =
13042 &to_i915(state->base.dev)->atomic_helper;
13043
13044 if (llist_add(&state->freed, &helper->free_list))
13045 schedule_work(&helper->free_work);
13046 break;
13047 }
13048 }
13049
13050 return NOTIFY_DONE;
13051 }
13052
13053 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
13054 {
13055 struct drm_plane_state *old_plane_state, *new_plane_state;
13056 struct drm_plane *plane;
13057 int i;
13058
13059 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
13060 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
13061 intel_fb_obj(new_plane_state->fb),
13062 to_intel_plane(plane)->frontbuffer_bit);
13063 }
13064
13065 /**
13066 * intel_atomic_commit - commit validated state object
13067 * @dev: DRM device
13068 * @state: the top-level driver state object
13069 * @nonblock: nonblocking commit
13070 *
13071 * This function commits a top-level state object that has been validated
13072 * with drm_atomic_helper_check().
13073 *
13074 * RETURNS
13075 * Zero for success or -errno.
13076 */
13077 static int intel_atomic_commit(struct drm_device *dev,
13078 struct drm_atomic_state *state,
13079 bool nonblock)
13080 {
13081 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13082 struct drm_i915_private *dev_priv = to_i915(dev);
13083 int ret = 0;
13084
13085 /*
13086 * The intel_legacy_cursor_update() fast path takes care
13087 * of avoiding the vblank waits for simple cursor
13088 * movement and flips. For cursor on/off and size changes,
13089 * we want to perform the vblank waits so that watermark
13090 * updates happen during the correct frames. Gen9+ have
13091 * double buffered watermarks and so shouldn't need this.
13092 */
13093 if (INTEL_GEN(dev_priv) < 9)
13094 state->legacy_cursor_update = false;
13095
13096 ret = drm_atomic_helper_setup_commit(state, nonblock);
13097 if (ret)
13098 return ret;
13099
13100 drm_atomic_state_get(state);
13101 i915_sw_fence_init(&intel_state->commit_ready,
13102 intel_atomic_commit_ready);
13103
13104 ret = intel_atomic_prepare_commit(dev, state);
13105 if (ret) {
13106 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13107 i915_sw_fence_commit(&intel_state->commit_ready);
13108 return ret;
13109 }
13110
13111 drm_atomic_helper_swap_state(state, true);
13112 dev_priv->wm.distrust_bios_wm = false;
13113 intel_shared_dpll_swap_state(state);
13114 intel_atomic_track_fbs(state);
13115
13116 if (intel_state->modeset) {
13117 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13118 sizeof(intel_state->min_pixclk));
13119 dev_priv->active_crtcs = intel_state->active_crtcs;
13120 dev_priv->cdclk.logical = intel_state->cdclk.logical;
13121 dev_priv->cdclk.actual = intel_state->cdclk.actual;
13122 }
13123
13124 drm_atomic_state_get(state);
13125 INIT_WORK(&state->commit_work,
13126 nonblock ? intel_atomic_commit_work : NULL);
13127
13128 i915_sw_fence_commit(&intel_state->commit_ready);
13129 if (!nonblock) {
13130 i915_sw_fence_wait(&intel_state->commit_ready);
13131 intel_atomic_commit_tail(state);
13132 }
13133
13134 return 0;
13135 }
13136
13137 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13138 {
13139 struct drm_device *dev = crtc->dev;
13140 struct drm_atomic_state *state;
13141 struct drm_crtc_state *crtc_state;
13142 int ret;
13143
13144 state = drm_atomic_state_alloc(dev);
13145 if (!state) {
13146 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
13147 crtc->base.id, crtc->name);
13148 return;
13149 }
13150
13151 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13152
13153 retry:
13154 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13155 ret = PTR_ERR_OR_ZERO(crtc_state);
13156 if (!ret) {
13157 if (!crtc_state->active)
13158 goto out;
13159
13160 crtc_state->mode_changed = true;
13161 ret = drm_atomic_commit(state);
13162 }
13163
13164 if (ret == -EDEADLK) {
13165 drm_atomic_state_clear(state);
13166 drm_modeset_backoff(state->acquire_ctx);
13167 goto retry;
13168 }
13169
13170 out:
13171 drm_atomic_state_put(state);
13172 }
13173
13174 /*
13175 * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
13176 * drm_atomic_helper_legacy_gamma_set() directly.
13177 */
13178 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
13179 u16 *red, u16 *green, u16 *blue,
13180 uint32_t size)
13181 {
13182 struct drm_device *dev = crtc->dev;
13183 struct drm_mode_config *config = &dev->mode_config;
13184 struct drm_crtc_state *state;
13185 int ret;
13186
13187 ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
13188 if (ret)
13189 return ret;
13190
13191 /*
13192 * Make sure we update the legacy properties so this works when
13193 * atomic is not enabled.
13194 */
13195
13196 state = crtc->state;
13197
13198 drm_object_property_set_value(&crtc->base,
13199 config->degamma_lut_property,
13200 (state->degamma_lut) ?
13201 state->degamma_lut->base.id : 0);
13202
13203 drm_object_property_set_value(&crtc->base,
13204 config->ctm_property,
13205 (state->ctm) ?
13206 state->ctm->base.id : 0);
13207
13208 drm_object_property_set_value(&crtc->base,
13209 config->gamma_lut_property,
13210 (state->gamma_lut) ?
13211 state->gamma_lut->base.id : 0);
13212
13213 return 0;
13214 }
13215
13216 static const struct drm_crtc_funcs intel_crtc_funcs = {
13217 .gamma_set = intel_atomic_legacy_gamma_set,
13218 .set_config = drm_atomic_helper_set_config,
13219 .set_property = drm_atomic_helper_crtc_set_property,
13220 .destroy = intel_crtc_destroy,
13221 .page_flip = drm_atomic_helper_page_flip,
13222 .atomic_duplicate_state = intel_crtc_duplicate_state,
13223 .atomic_destroy_state = intel_crtc_destroy_state,
13224 .set_crc_source = intel_crtc_set_crc_source,
13225 };
13226
13227 /**
13228 * intel_prepare_plane_fb - Prepare fb for usage on plane
13229 * @plane: drm plane to prepare for
13230 * @fb: framebuffer to prepare for presentation
13231 *
13232 * Prepares a framebuffer for usage on a display plane. Generally this
13233 * involves pinning the underlying object and updating the frontbuffer tracking
13234 * bits. Some older platforms need special physical address handling for
13235 * cursor planes.
13236 *
13237 * Must be called with struct_mutex held.
13238 *
13239 * Returns 0 on success, negative error code on failure.
13240 */
13241 int
13242 intel_prepare_plane_fb(struct drm_plane *plane,
13243 struct drm_plane_state *new_state)
13244 {
13245 struct intel_atomic_state *intel_state =
13246 to_intel_atomic_state(new_state->state);
13247 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13248 struct drm_framebuffer *fb = new_state->fb;
13249 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13250 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13251 int ret;
13252
13253 if (obj) {
13254 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13255 INTEL_INFO(dev_priv)->cursor_needs_physical) {
13256 const int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
13257
13258 ret = i915_gem_object_attach_phys(obj, align);
13259 if (ret) {
13260 DRM_DEBUG_KMS("failed to attach phys object\n");
13261 return ret;
13262 }
13263 } else {
13264 struct i915_vma *vma;
13265
13266 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13267 if (IS_ERR(vma)) {
13268 DRM_DEBUG_KMS("failed to pin object\n");
13269 return PTR_ERR(vma);
13270 }
13271
13272 to_intel_plane_state(new_state)->vma = vma;
13273 }
13274 }
13275
13276 if (!obj && !old_obj)
13277 return 0;
13278
13279 if (old_obj) {
13280 struct drm_crtc_state *crtc_state =
13281 drm_atomic_get_existing_crtc_state(new_state->state,
13282 plane->state->crtc);
13283
13284 /* Big Hammer, we also need to ensure that any pending
13285 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13286 * current scanout is retired before unpinning the old
13287 * framebuffer. Note that we rely on userspace rendering
13288 * into the buffer attached to the pipe they are waiting
13289 * on. If not, userspace generates a GPU hang with IPEHR
13290 * point to the MI_WAIT_FOR_EVENT.
13291 *
13292 * This should only fail upon a hung GPU, in which case we
13293 * can safely continue.
13294 */
13295 if (needs_modeset(crtc_state)) {
13296 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13297 old_obj->resv, NULL,
13298 false, 0,
13299 GFP_KERNEL);
13300 if (ret < 0)
13301 return ret;
13302 }
13303 }
13304
13305 if (new_state->fence) { /* explicit fencing */
13306 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
13307 new_state->fence,
13308 I915_FENCE_TIMEOUT,
13309 GFP_KERNEL);
13310 if (ret < 0)
13311 return ret;
13312 }
13313
13314 if (!obj)
13315 return 0;
13316
13317 if (!new_state->fence) { /* implicit fencing */
13318 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13319 obj->resv, NULL,
13320 false, I915_FENCE_TIMEOUT,
13321 GFP_KERNEL);
13322 if (ret < 0)
13323 return ret;
13324
13325 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
13326 }
13327
13328 return 0;
13329 }
13330
13331 /**
13332 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13333 * @plane: drm plane to clean up for
13334 * @fb: old framebuffer that was on plane
13335 *
13336 * Cleans up a framebuffer that has just been removed from a plane.
13337 *
13338 * Must be called with struct_mutex held.
13339 */
13340 void
13341 intel_cleanup_plane_fb(struct drm_plane *plane,
13342 struct drm_plane_state *old_state)
13343 {
13344 struct i915_vma *vma;
13345
13346 /* Should only be called after a successful intel_prepare_plane_fb()! */
13347 vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
13348 if (vma)
13349 intel_unpin_fb_vma(vma);
13350 }
13351
13352 int
13353 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13354 {
13355 struct drm_i915_private *dev_priv;
13356 int max_scale;
13357 int crtc_clock, max_dotclk;
13358
13359 if (!intel_crtc || !crtc_state->base.enable)
13360 return DRM_PLANE_HELPER_NO_SCALING;
13361
13362 dev_priv = to_i915(intel_crtc->base.dev);
13363
13364 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13365 max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
13366
13367 if (IS_GEMINILAKE(dev_priv))
13368 max_dotclk *= 2;
13369
13370 if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
13371 return DRM_PLANE_HELPER_NO_SCALING;
13372
13373 /*
13374 * skl max scale is lower of:
13375 * close to 3 but not 3, -1 is for that purpose
13376 * or
13377 * cdclk/crtc_clock
13378 */
13379 max_scale = min((1 << 16) * 3 - 1,
13380 (1 << 8) * ((max_dotclk << 8) / crtc_clock));
13381
13382 return max_scale;
13383 }
13384
13385 static int
13386 intel_check_primary_plane(struct drm_plane *plane,
13387 struct intel_crtc_state *crtc_state,
13388 struct intel_plane_state *state)
13389 {
13390 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13391 struct drm_crtc *crtc = state->base.crtc;
13392 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13393 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13394 bool can_position = false;
13395 int ret;
13396
13397 if (INTEL_GEN(dev_priv) >= 9) {
13398 /* use scaler when colorkey is not required */
13399 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13400 min_scale = 1;
13401 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13402 }
13403 can_position = true;
13404 }
13405
13406 ret = drm_plane_helper_check_state(&state->base,
13407 &state->clip,
13408 min_scale, max_scale,
13409 can_position, true);
13410 if (ret)
13411 return ret;
13412
13413 if (!state->base.fb)
13414 return 0;
13415
13416 if (INTEL_GEN(dev_priv) >= 9) {
13417 ret = skl_check_plane_surface(state);
13418 if (ret)
13419 return ret;
13420 }
13421
13422 return 0;
13423 }
13424
13425 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13426 struct drm_crtc_state *old_crtc_state)
13427 {
13428 struct drm_device *dev = crtc->dev;
13429 struct drm_i915_private *dev_priv = to_i915(dev);
13430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13431 struct intel_crtc_state *intel_cstate =
13432 to_intel_crtc_state(crtc->state);
13433 struct intel_crtc_state *old_intel_cstate =
13434 to_intel_crtc_state(old_crtc_state);
13435 struct intel_atomic_state *old_intel_state =
13436 to_intel_atomic_state(old_crtc_state->state);
13437 bool modeset = needs_modeset(crtc->state);
13438
13439 if (!modeset &&
13440 (intel_cstate->base.color_mgmt_changed ||
13441 intel_cstate->update_pipe)) {
13442 intel_color_set_csc(crtc->state);
13443 intel_color_load_luts(crtc->state);
13444 }
13445
13446 /* Perform vblank evasion around commit operation */
13447 intel_pipe_update_start(intel_crtc);
13448
13449 if (modeset)
13450 goto out;
13451
13452 if (intel_cstate->update_pipe)
13453 intel_update_pipe_config(intel_crtc, old_intel_cstate);
13454 else if (INTEL_GEN(dev_priv) >= 9)
13455 skl_detach_scalers(intel_crtc);
13456
13457 out:
13458 if (dev_priv->display.atomic_update_watermarks)
13459 dev_priv->display.atomic_update_watermarks(old_intel_state,
13460 intel_cstate);
13461 }
13462
13463 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13464 struct drm_crtc_state *old_crtc_state)
13465 {
13466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13467
13468 intel_pipe_update_end(intel_crtc, NULL);
13469 }
13470
13471 /**
13472 * intel_plane_destroy - destroy a plane
13473 * @plane: plane to destroy
13474 *
13475 * Common destruction function for all types of planes (primary, cursor,
13476 * sprite).
13477 */
13478 void intel_plane_destroy(struct drm_plane *plane)
13479 {
13480 drm_plane_cleanup(plane);
13481 kfree(to_intel_plane(plane));
13482 }
13483
13484 const struct drm_plane_funcs intel_plane_funcs = {
13485 .update_plane = drm_atomic_helper_update_plane,
13486 .disable_plane = drm_atomic_helper_disable_plane,
13487 .destroy = intel_plane_destroy,
13488 .set_property = drm_atomic_helper_plane_set_property,
13489 .atomic_get_property = intel_plane_atomic_get_property,
13490 .atomic_set_property = intel_plane_atomic_set_property,
13491 .atomic_duplicate_state = intel_plane_duplicate_state,
13492 .atomic_destroy_state = intel_plane_destroy_state,
13493 };
13494
13495 static int
13496 intel_legacy_cursor_update(struct drm_plane *plane,
13497 struct drm_crtc *crtc,
13498 struct drm_framebuffer *fb,
13499 int crtc_x, int crtc_y,
13500 unsigned int crtc_w, unsigned int crtc_h,
13501 uint32_t src_x, uint32_t src_y,
13502 uint32_t src_w, uint32_t src_h)
13503 {
13504 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13505 int ret;
13506 struct drm_plane_state *old_plane_state, *new_plane_state;
13507 struct intel_plane *intel_plane = to_intel_plane(plane);
13508 struct drm_framebuffer *old_fb;
13509 struct drm_crtc_state *crtc_state = crtc->state;
13510 struct i915_vma *old_vma;
13511
13512 /*
13513 * When crtc is inactive or there is a modeset pending,
13514 * wait for it to complete in the slowpath
13515 */
13516 if (!crtc_state->active || needs_modeset(crtc_state) ||
13517 to_intel_crtc_state(crtc_state)->update_pipe)
13518 goto slow;
13519
13520 old_plane_state = plane->state;
13521
13522 /*
13523 * If any parameters change that may affect watermarks,
13524 * take the slowpath. Only changing fb or position should be
13525 * in the fastpath.
13526 */
13527 if (old_plane_state->crtc != crtc ||
13528 old_plane_state->src_w != src_w ||
13529 old_plane_state->src_h != src_h ||
13530 old_plane_state->crtc_w != crtc_w ||
13531 old_plane_state->crtc_h != crtc_h ||
13532 !old_plane_state->fb != !fb)
13533 goto slow;
13534
13535 new_plane_state = intel_plane_duplicate_state(plane);
13536 if (!new_plane_state)
13537 return -ENOMEM;
13538
13539 drm_atomic_set_fb_for_plane(new_plane_state, fb);
13540
13541 new_plane_state->src_x = src_x;
13542 new_plane_state->src_y = src_y;
13543 new_plane_state->src_w = src_w;
13544 new_plane_state->src_h = src_h;
13545 new_plane_state->crtc_x = crtc_x;
13546 new_plane_state->crtc_y = crtc_y;
13547 new_plane_state->crtc_w = crtc_w;
13548 new_plane_state->crtc_h = crtc_h;
13549
13550 ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13551 to_intel_plane_state(new_plane_state));
13552 if (ret)
13553 goto out_free;
13554
13555 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13556 if (ret)
13557 goto out_free;
13558
13559 if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13560 int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
13561
13562 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13563 if (ret) {
13564 DRM_DEBUG_KMS("failed to attach phys object\n");
13565 goto out_unlock;
13566 }
13567 } else {
13568 struct i915_vma *vma;
13569
13570 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13571 if (IS_ERR(vma)) {
13572 DRM_DEBUG_KMS("failed to pin object\n");
13573
13574 ret = PTR_ERR(vma);
13575 goto out_unlock;
13576 }
13577
13578 to_intel_plane_state(new_plane_state)->vma = vma;
13579 }
13580
13581 old_fb = old_plane_state->fb;
13582 old_vma = to_intel_plane_state(old_plane_state)->vma;
13583
13584 i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13585 intel_plane->frontbuffer_bit);
13586
13587 /* Swap plane state */
13588 new_plane_state->fence = old_plane_state->fence;
13589 *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state);
13590 new_plane_state->fence = NULL;
13591 new_plane_state->fb = old_fb;
13592 to_intel_plane_state(new_plane_state)->vma = old_vma;
13593
13594 if (plane->state->visible) {
13595 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13596 intel_plane->update_plane(plane,
13597 to_intel_crtc_state(crtc->state),
13598 to_intel_plane_state(plane->state));
13599 } else {
13600 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13601 intel_plane->disable_plane(plane, crtc);
13602 }
13603
13604 intel_cleanup_plane_fb(plane, new_plane_state);
13605
13606 out_unlock:
13607 mutex_unlock(&dev_priv->drm.struct_mutex);
13608 out_free:
13609 intel_plane_destroy_state(plane, new_plane_state);
13610 return ret;
13611
13612 slow:
13613 return drm_atomic_helper_update_plane(plane, crtc, fb,
13614 crtc_x, crtc_y, crtc_w, crtc_h,
13615 src_x, src_y, src_w, src_h);
13616 }
13617
13618 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13619 .update_plane = intel_legacy_cursor_update,
13620 .disable_plane = drm_atomic_helper_disable_plane,
13621 .destroy = intel_plane_destroy,
13622 .set_property = drm_atomic_helper_plane_set_property,
13623 .atomic_get_property = intel_plane_atomic_get_property,
13624 .atomic_set_property = intel_plane_atomic_set_property,
13625 .atomic_duplicate_state = intel_plane_duplicate_state,
13626 .atomic_destroy_state = intel_plane_destroy_state,
13627 };
13628
13629 static struct intel_plane *
13630 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13631 {
13632 struct intel_plane *primary = NULL;
13633 struct intel_plane_state *state = NULL;
13634 const uint32_t *intel_primary_formats;
13635 unsigned int supported_rotations;
13636 unsigned int num_formats;
13637 int ret;
13638
13639 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13640 if (!primary) {
13641 ret = -ENOMEM;
13642 goto fail;
13643 }
13644
13645 state = intel_create_plane_state(&primary->base);
13646 if (!state) {
13647 ret = -ENOMEM;
13648 goto fail;
13649 }
13650
13651 primary->base.state = &state->base;
13652
13653 primary->can_scale = false;
13654 primary->max_downscale = 1;
13655 if (INTEL_GEN(dev_priv) >= 9) {
13656 primary->can_scale = true;
13657 state->scaler_id = -1;
13658 }
13659 primary->pipe = pipe;
13660 /*
13661 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13662 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13663 */
13664 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13665 primary->plane = (enum plane) !pipe;
13666 else
13667 primary->plane = (enum plane) pipe;
13668 primary->id = PLANE_PRIMARY;
13669 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13670 primary->check_plane = intel_check_primary_plane;
13671
13672 if (INTEL_GEN(dev_priv) >= 9) {
13673 intel_primary_formats = skl_primary_formats;
13674 num_formats = ARRAY_SIZE(skl_primary_formats);
13675
13676 primary->update_plane = skylake_update_primary_plane;
13677 primary->disable_plane = skylake_disable_primary_plane;
13678 } else if (HAS_PCH_SPLIT(dev_priv)) {
13679 intel_primary_formats = i965_primary_formats;
13680 num_formats = ARRAY_SIZE(i965_primary_formats);
13681
13682 primary->update_plane = ironlake_update_primary_plane;
13683 primary->disable_plane = i9xx_disable_primary_plane;
13684 } else if (INTEL_GEN(dev_priv) >= 4) {
13685 intel_primary_formats = i965_primary_formats;
13686 num_formats = ARRAY_SIZE(i965_primary_formats);
13687
13688 primary->update_plane = i9xx_update_primary_plane;
13689 primary->disable_plane = i9xx_disable_primary_plane;
13690 } else {
13691 intel_primary_formats = i8xx_primary_formats;
13692 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13693
13694 primary->update_plane = i9xx_update_primary_plane;
13695 primary->disable_plane = i9xx_disable_primary_plane;
13696 }
13697
13698 if (INTEL_GEN(dev_priv) >= 9)
13699 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13700 0, &intel_plane_funcs,
13701 intel_primary_formats, num_formats,
13702 DRM_PLANE_TYPE_PRIMARY,
13703 "plane 1%c", pipe_name(pipe));
13704 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13705 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13706 0, &intel_plane_funcs,
13707 intel_primary_formats, num_formats,
13708 DRM_PLANE_TYPE_PRIMARY,
13709 "primary %c", pipe_name(pipe));
13710 else
13711 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13712 0, &intel_plane_funcs,
13713 intel_primary_formats, num_formats,
13714 DRM_PLANE_TYPE_PRIMARY,
13715 "plane %c", plane_name(primary->plane));
13716 if (ret)
13717 goto fail;
13718
13719 if (INTEL_GEN(dev_priv) >= 9) {
13720 supported_rotations =
13721 DRM_ROTATE_0 | DRM_ROTATE_90 |
13722 DRM_ROTATE_180 | DRM_ROTATE_270;
13723 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13724 supported_rotations =
13725 DRM_ROTATE_0 | DRM_ROTATE_180 |
13726 DRM_REFLECT_X;
13727 } else if (INTEL_GEN(dev_priv) >= 4) {
13728 supported_rotations =
13729 DRM_ROTATE_0 | DRM_ROTATE_180;
13730 } else {
13731 supported_rotations = DRM_ROTATE_0;
13732 }
13733
13734 if (INTEL_GEN(dev_priv) >= 4)
13735 drm_plane_create_rotation_property(&primary->base,
13736 DRM_ROTATE_0,
13737 supported_rotations);
13738
13739 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13740
13741 return primary;
13742
13743 fail:
13744 kfree(state);
13745 kfree(primary);
13746
13747 return ERR_PTR(ret);
13748 }
13749
13750 static int
13751 intel_check_cursor_plane(struct drm_plane *plane,
13752 struct intel_crtc_state *crtc_state,
13753 struct intel_plane_state *state)
13754 {
13755 struct drm_framebuffer *fb = state->base.fb;
13756 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13757 enum pipe pipe = to_intel_plane(plane)->pipe;
13758 unsigned stride;
13759 int ret;
13760
13761 ret = drm_plane_helper_check_state(&state->base,
13762 &state->clip,
13763 DRM_PLANE_HELPER_NO_SCALING,
13764 DRM_PLANE_HELPER_NO_SCALING,
13765 true, true);
13766 if (ret)
13767 return ret;
13768
13769 /* if we want to turn off the cursor ignore width and height */
13770 if (!obj)
13771 return 0;
13772
13773 /* Check for which cursor types we support */
13774 if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w,
13775 state->base.crtc_h)) {
13776 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13777 state->base.crtc_w, state->base.crtc_h);
13778 return -EINVAL;
13779 }
13780
13781 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13782 if (obj->base.size < stride * state->base.crtc_h) {
13783 DRM_DEBUG_KMS("buffer is too small\n");
13784 return -ENOMEM;
13785 }
13786
13787 if (fb->modifier != DRM_FORMAT_MOD_NONE) {
13788 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13789 return -EINVAL;
13790 }
13791
13792 /*
13793 * There's something wrong with the cursor on CHV pipe C.
13794 * If it straddles the left edge of the screen then
13795 * moving it away from the edge or disabling it often
13796 * results in a pipe underrun, and often that can lead to
13797 * dead pipe (constant underrun reported, and it scans
13798 * out just a solid color). To recover from that, the
13799 * display power well must be turned off and on again.
13800 * Refuse the put the cursor into that compromised position.
13801 */
13802 if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C &&
13803 state->base.visible && state->base.crtc_x < 0) {
13804 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
13805 return -EINVAL;
13806 }
13807
13808 return 0;
13809 }
13810
13811 static void
13812 intel_disable_cursor_plane(struct drm_plane *plane,
13813 struct drm_crtc *crtc)
13814 {
13815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13816
13817 intel_crtc->cursor_addr = 0;
13818 intel_crtc_update_cursor(crtc, NULL, NULL);
13819 }
13820
13821 static void
13822 intel_update_cursor_plane(struct drm_plane *plane,
13823 const struct intel_crtc_state *crtc_state,
13824 const struct intel_plane_state *state)
13825 {
13826 struct drm_crtc *crtc = crtc_state->base.crtc;
13827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13828 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13829 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13830 uint32_t addr;
13831
13832 if (!obj)
13833 addr = 0;
13834 else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
13835 addr = intel_plane_ggtt_offset(state);
13836 else
13837 addr = obj->phys_handle->busaddr;
13838
13839 intel_crtc->cursor_addr = addr;
13840 intel_crtc_update_cursor(crtc, crtc_state, state);
13841 }
13842
13843 static struct intel_plane *
13844 intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13845 {
13846 struct intel_plane *cursor = NULL;
13847 struct intel_plane_state *state = NULL;
13848 int ret;
13849
13850 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13851 if (!cursor) {
13852 ret = -ENOMEM;
13853 goto fail;
13854 }
13855
13856 state = intel_create_plane_state(&cursor->base);
13857 if (!state) {
13858 ret = -ENOMEM;
13859 goto fail;
13860 }
13861
13862 cursor->base.state = &state->base;
13863
13864 cursor->can_scale = false;
13865 cursor->max_downscale = 1;
13866 cursor->pipe = pipe;
13867 cursor->plane = pipe;
13868 cursor->id = PLANE_CURSOR;
13869 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13870 cursor->check_plane = intel_check_cursor_plane;
13871 cursor->update_plane = intel_update_cursor_plane;
13872 cursor->disable_plane = intel_disable_cursor_plane;
13873
13874 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13875 0, &intel_cursor_plane_funcs,
13876 intel_cursor_formats,
13877 ARRAY_SIZE(intel_cursor_formats),
13878 DRM_PLANE_TYPE_CURSOR,
13879 "cursor %c", pipe_name(pipe));
13880 if (ret)
13881 goto fail;
13882
13883 if (INTEL_GEN(dev_priv) >= 4)
13884 drm_plane_create_rotation_property(&cursor->base,
13885 DRM_ROTATE_0,
13886 DRM_ROTATE_0 |
13887 DRM_ROTATE_180);
13888
13889 if (INTEL_GEN(dev_priv) >= 9)
13890 state->scaler_id = -1;
13891
13892 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13893
13894 return cursor;
13895
13896 fail:
13897 kfree(state);
13898 kfree(cursor);
13899
13900 return ERR_PTR(ret);
13901 }
13902
13903 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13904 struct intel_crtc_state *crtc_state)
13905 {
13906 struct intel_crtc_scaler_state *scaler_state =
13907 &crtc_state->scaler_state;
13908 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13909 int i;
13910
13911 crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13912 if (!crtc->num_scalers)
13913 return;
13914
13915 for (i = 0; i < crtc->num_scalers; i++) {
13916 struct intel_scaler *scaler = &scaler_state->scalers[i];
13917
13918 scaler->in_use = 0;
13919 scaler->mode = PS_SCALER_MODE_DYN;
13920 }
13921
13922 scaler_state->scaler_id = -1;
13923 }
13924
13925 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13926 {
13927 struct intel_crtc *intel_crtc;
13928 struct intel_crtc_state *crtc_state = NULL;
13929 struct intel_plane *primary = NULL;
13930 struct intel_plane *cursor = NULL;
13931 int sprite, ret;
13932
13933 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13934 if (!intel_crtc)
13935 return -ENOMEM;
13936
13937 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13938 if (!crtc_state) {
13939 ret = -ENOMEM;
13940 goto fail;
13941 }
13942 intel_crtc->config = crtc_state;
13943 intel_crtc->base.state = &crtc_state->base;
13944 crtc_state->base.crtc = &intel_crtc->base;
13945
13946 primary = intel_primary_plane_create(dev_priv, pipe);
13947 if (IS_ERR(primary)) {
13948 ret = PTR_ERR(primary);
13949 goto fail;
13950 }
13951 intel_crtc->plane_ids_mask |= BIT(primary->id);
13952
13953 for_each_sprite(dev_priv, pipe, sprite) {
13954 struct intel_plane *plane;
13955
13956 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13957 if (IS_ERR(plane)) {
13958 ret = PTR_ERR(plane);
13959 goto fail;
13960 }
13961 intel_crtc->plane_ids_mask |= BIT(plane->id);
13962 }
13963
13964 cursor = intel_cursor_plane_create(dev_priv, pipe);
13965 if (IS_ERR(cursor)) {
13966 ret = PTR_ERR(cursor);
13967 goto fail;
13968 }
13969 intel_crtc->plane_ids_mask |= BIT(cursor->id);
13970
13971 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13972 &primary->base, &cursor->base,
13973 &intel_crtc_funcs,
13974 "pipe %c", pipe_name(pipe));
13975 if (ret)
13976 goto fail;
13977
13978 intel_crtc->pipe = pipe;
13979 intel_crtc->plane = primary->plane;
13980
13981 intel_crtc->cursor_base = ~0;
13982 intel_crtc->cursor_cntl = ~0;
13983 intel_crtc->cursor_size = ~0;
13984
13985 /* initialize shared scalers */
13986 intel_crtc_init_scalers(intel_crtc, crtc_state);
13987
13988 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13989 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13990 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13991 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13992
13993 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13994
13995 intel_color_init(&intel_crtc->base);
13996
13997 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13998
13999 return 0;
14000
14001 fail:
14002 /*
14003 * drm_mode_config_cleanup() will free up any
14004 * crtcs/planes already initialized.
14005 */
14006 kfree(crtc_state);
14007 kfree(intel_crtc);
14008
14009 return ret;
14010 }
14011
14012 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14013 {
14014 struct drm_device *dev = connector->base.dev;
14015
14016 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14017
14018 if (!connector->base.state->crtc)
14019 return INVALID_PIPE;
14020
14021 return to_intel_crtc(connector->base.state->crtc)->pipe;
14022 }
14023
14024 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14025 struct drm_file *file)
14026 {
14027 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14028 struct drm_crtc *drmmode_crtc;
14029 struct intel_crtc *crtc;
14030
14031 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14032 if (!drmmode_crtc)
14033 return -ENOENT;
14034
14035 crtc = to_intel_crtc(drmmode_crtc);
14036 pipe_from_crtc_id->pipe = crtc->pipe;
14037
14038 return 0;
14039 }
14040
14041 static int intel_encoder_clones(struct intel_encoder *encoder)
14042 {
14043 struct drm_device *dev = encoder->base.dev;
14044 struct intel_encoder *source_encoder;
14045 int index_mask = 0;
14046 int entry = 0;
14047
14048 for_each_intel_encoder(dev, source_encoder) {
14049 if (encoders_cloneable(encoder, source_encoder))
14050 index_mask |= (1 << entry);
14051
14052 entry++;
14053 }
14054
14055 return index_mask;
14056 }
14057
14058 static bool has_edp_a(struct drm_i915_private *dev_priv)
14059 {
14060 if (!IS_MOBILE(dev_priv))
14061 return false;
14062
14063 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14064 return false;
14065
14066 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14067 return false;
14068
14069 return true;
14070 }
14071
14072 static bool intel_crt_present(struct drm_i915_private *dev_priv)
14073 {
14074 if (INTEL_GEN(dev_priv) >= 9)
14075 return false;
14076
14077 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
14078 return false;
14079
14080 if (IS_CHERRYVIEW(dev_priv))
14081 return false;
14082
14083 if (HAS_PCH_LPT_H(dev_priv) &&
14084 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14085 return false;
14086
14087 /* DDI E can't be used if DDI A requires 4 lanes */
14088 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14089 return false;
14090
14091 if (!dev_priv->vbt.int_crt_support)
14092 return false;
14093
14094 return true;
14095 }
14096
14097 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
14098 {
14099 int pps_num;
14100 int pps_idx;
14101
14102 if (HAS_DDI(dev_priv))
14103 return;
14104 /*
14105 * This w/a is needed at least on CPT/PPT, but to be sure apply it
14106 * everywhere where registers can be write protected.
14107 */
14108 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14109 pps_num = 2;
14110 else
14111 pps_num = 1;
14112
14113 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
14114 u32 val = I915_READ(PP_CONTROL(pps_idx));
14115
14116 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
14117 I915_WRITE(PP_CONTROL(pps_idx), val);
14118 }
14119 }
14120
14121 static void intel_pps_init(struct drm_i915_private *dev_priv)
14122 {
14123 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
14124 dev_priv->pps_mmio_base = PCH_PPS_BASE;
14125 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14126 dev_priv->pps_mmio_base = VLV_PPS_BASE;
14127 else
14128 dev_priv->pps_mmio_base = PPS_BASE;
14129
14130 intel_pps_unlock_regs_wa(dev_priv);
14131 }
14132
14133 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14134 {
14135 struct intel_encoder *encoder;
14136 bool dpd_is_edp = false;
14137
14138 intel_pps_init(dev_priv);
14139
14140 /*
14141 * intel_edp_init_connector() depends on this completing first, to
14142 * prevent the registeration of both eDP and LVDS and the incorrect
14143 * sharing of the PPS.
14144 */
14145 intel_lvds_init(dev_priv);
14146
14147 if (intel_crt_present(dev_priv))
14148 intel_crt_init(dev_priv);
14149
14150 if (IS_GEN9_LP(dev_priv)) {
14151 /*
14152 * FIXME: Broxton doesn't support port detection via the
14153 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14154 * detect the ports.
14155 */
14156 intel_ddi_init(dev_priv, PORT_A);
14157 intel_ddi_init(dev_priv, PORT_B);
14158 intel_ddi_init(dev_priv, PORT_C);
14159
14160 intel_dsi_init(dev_priv);
14161 } else if (HAS_DDI(dev_priv)) {
14162 int found;
14163
14164 /*
14165 * Haswell uses DDI functions to detect digital outputs.
14166 * On SKL pre-D0 the strap isn't connected, so we assume
14167 * it's there.
14168 */
14169 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14170 /* WaIgnoreDDIAStrap: skl */
14171 if (found || IS_GEN9_BC(dev_priv))
14172 intel_ddi_init(dev_priv, PORT_A);
14173
14174 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14175 * register */
14176 found = I915_READ(SFUSE_STRAP);
14177
14178 if (found & SFUSE_STRAP_DDIB_DETECTED)
14179 intel_ddi_init(dev_priv, PORT_B);
14180 if (found & SFUSE_STRAP_DDIC_DETECTED)
14181 intel_ddi_init(dev_priv, PORT_C);
14182 if (found & SFUSE_STRAP_DDID_DETECTED)
14183 intel_ddi_init(dev_priv, PORT_D);
14184 /*
14185 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14186 */
14187 if (IS_GEN9_BC(dev_priv) &&
14188 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14189 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14190 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14191 intel_ddi_init(dev_priv, PORT_E);
14192
14193 } else if (HAS_PCH_SPLIT(dev_priv)) {
14194 int found;
14195 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
14196
14197 if (has_edp_a(dev_priv))
14198 intel_dp_init(dev_priv, DP_A, PORT_A);
14199
14200 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14201 /* PCH SDVOB multiplex with HDMIB */
14202 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
14203 if (!found)
14204 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
14205 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14206 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
14207 }
14208
14209 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14210 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
14211
14212 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14213 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
14214
14215 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14216 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
14217
14218 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14219 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
14220 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14221 bool has_edp, has_port;
14222
14223 /*
14224 * The DP_DETECTED bit is the latched state of the DDC
14225 * SDA pin at boot. However since eDP doesn't require DDC
14226 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14227 * eDP ports may have been muxed to an alternate function.
14228 * Thus we can't rely on the DP_DETECTED bit alone to detect
14229 * eDP ports. Consult the VBT as well as DP_DETECTED to
14230 * detect eDP ports.
14231 *
14232 * Sadly the straps seem to be missing sometimes even for HDMI
14233 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14234 * and VBT for the presence of the port. Additionally we can't
14235 * trust the port type the VBT declares as we've seen at least
14236 * HDMI ports that the VBT claim are DP or eDP.
14237 */
14238 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
14239 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14240 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14241 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
14242 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14243 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
14244
14245 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
14246 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14247 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14248 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
14249 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14250 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
14251
14252 if (IS_CHERRYVIEW(dev_priv)) {
14253 /*
14254 * eDP not supported on port D,
14255 * so no need to worry about it
14256 */
14257 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14258 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14259 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
14260 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14261 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
14262 }
14263
14264 intel_dsi_init(dev_priv);
14265 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
14266 bool found = false;
14267
14268 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14269 DRM_DEBUG_KMS("probing SDVOB\n");
14270 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
14271 if (!found && IS_G4X(dev_priv)) {
14272 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14273 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
14274 }
14275
14276 if (!found && IS_G4X(dev_priv))
14277 intel_dp_init(dev_priv, DP_B, PORT_B);
14278 }
14279
14280 /* Before G4X SDVOC doesn't have its own detect register */
14281
14282 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14283 DRM_DEBUG_KMS("probing SDVOC\n");
14284 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
14285 }
14286
14287 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14288
14289 if (IS_G4X(dev_priv)) {
14290 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14291 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
14292 }
14293 if (IS_G4X(dev_priv))
14294 intel_dp_init(dev_priv, DP_C, PORT_C);
14295 }
14296
14297 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
14298 intel_dp_init(dev_priv, DP_D, PORT_D);
14299 } else if (IS_GEN2(dev_priv))
14300 intel_dvo_init(dev_priv);
14301
14302 if (SUPPORTS_TV(dev_priv))
14303 intel_tv_init(dev_priv);
14304
14305 intel_psr_init(dev_priv);
14306
14307 for_each_intel_encoder(&dev_priv->drm, encoder) {
14308 encoder->base.possible_crtcs = encoder->crtc_mask;
14309 encoder->base.possible_clones =
14310 intel_encoder_clones(encoder);
14311 }
14312
14313 intel_init_pch_refclk(dev_priv);
14314
14315 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
14316 }
14317
14318 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14319 {
14320 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14321
14322 drm_framebuffer_cleanup(fb);
14323
14324 i915_gem_object_lock(intel_fb->obj);
14325 WARN_ON(!intel_fb->obj->framebuffer_references--);
14326 i915_gem_object_unlock(intel_fb->obj);
14327
14328 i915_gem_object_put(intel_fb->obj);
14329
14330 kfree(intel_fb);
14331 }
14332
14333 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14334 struct drm_file *file,
14335 unsigned int *handle)
14336 {
14337 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14338 struct drm_i915_gem_object *obj = intel_fb->obj;
14339
14340 if (obj->userptr.mm) {
14341 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14342 return -EINVAL;
14343 }
14344
14345 return drm_gem_handle_create(file, &obj->base, handle);
14346 }
14347
14348 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14349 struct drm_file *file,
14350 unsigned flags, unsigned color,
14351 struct drm_clip_rect *clips,
14352 unsigned num_clips)
14353 {
14354 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14355
14356 i915_gem_object_flush_if_display(obj);
14357 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
14358
14359 return 0;
14360 }
14361
14362 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14363 .destroy = intel_user_framebuffer_destroy,
14364 .create_handle = intel_user_framebuffer_create_handle,
14365 .dirty = intel_user_framebuffer_dirty,
14366 };
14367
14368 static
14369 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
14370 uint64_t fb_modifier, uint32_t pixel_format)
14371 {
14372 u32 gen = INTEL_GEN(dev_priv);
14373
14374 if (gen >= 9) {
14375 int cpp = drm_format_plane_cpp(pixel_format, 0);
14376
14377 /* "The stride in bytes must not exceed the of the size of 8K
14378 * pixels and 32K bytes."
14379 */
14380 return min(8192 * cpp, 32768);
14381 } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
14382 return 32*1024;
14383 } else if (gen >= 4) {
14384 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14385 return 16*1024;
14386 else
14387 return 32*1024;
14388 } else if (gen >= 3) {
14389 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14390 return 8*1024;
14391 else
14392 return 16*1024;
14393 } else {
14394 /* XXX DSPC is limited to 4k tiled */
14395 return 8*1024;
14396 }
14397 }
14398
14399 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14400 struct drm_i915_gem_object *obj,
14401 struct drm_mode_fb_cmd2 *mode_cmd)
14402 {
14403 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14404 struct drm_format_name_buf format_name;
14405 u32 pitch_limit, stride_alignment;
14406 unsigned int tiling, stride;
14407 int ret = -EINVAL;
14408
14409 i915_gem_object_lock(obj);
14410 obj->framebuffer_references++;
14411 tiling = i915_gem_object_get_tiling(obj);
14412 stride = i915_gem_object_get_stride(obj);
14413 i915_gem_object_unlock(obj);
14414
14415 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14416 /*
14417 * If there's a fence, enforce that
14418 * the fb modifier and tiling mode match.
14419 */
14420 if (tiling != I915_TILING_NONE &&
14421 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14422 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
14423 goto err;
14424 }
14425 } else {
14426 if (tiling == I915_TILING_X) {
14427 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14428 } else if (tiling == I915_TILING_Y) {
14429 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
14430 goto err;
14431 }
14432 }
14433
14434 /* Passed in modifier sanity checking. */
14435 switch (mode_cmd->modifier[0]) {
14436 case I915_FORMAT_MOD_Y_TILED:
14437 case I915_FORMAT_MOD_Yf_TILED:
14438 if (INTEL_GEN(dev_priv) < 9) {
14439 DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
14440 mode_cmd->modifier[0]);
14441 goto err;
14442 }
14443 case DRM_FORMAT_MOD_NONE:
14444 case I915_FORMAT_MOD_X_TILED:
14445 break;
14446 default:
14447 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
14448 mode_cmd->modifier[0]);
14449 goto err;
14450 }
14451
14452 /*
14453 * gen2/3 display engine uses the fence if present,
14454 * so the tiling mode must match the fb modifier exactly.
14455 */
14456 if (INTEL_INFO(dev_priv)->gen < 4 &&
14457 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14458 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
14459 goto err;
14460 }
14461
14462 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14463 mode_cmd->pixel_format);
14464 if (mode_cmd->pitches[0] > pitch_limit) {
14465 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
14466 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14467 "tiled" : "linear",
14468 mode_cmd->pitches[0], pitch_limit);
14469 goto err;
14470 }
14471
14472 /*
14473 * If there's a fence, enforce that
14474 * the fb pitch and fence stride match.
14475 */
14476 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14477 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
14478 mode_cmd->pitches[0], stride);
14479 goto err;
14480 }
14481
14482 /* Reject formats not supported by any plane early. */
14483 switch (mode_cmd->pixel_format) {
14484 case DRM_FORMAT_C8:
14485 case DRM_FORMAT_RGB565:
14486 case DRM_FORMAT_XRGB8888:
14487 case DRM_FORMAT_ARGB8888:
14488 break;
14489 case DRM_FORMAT_XRGB1555:
14490 if (INTEL_GEN(dev_priv) > 3) {
14491 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14492 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14493 goto err;
14494 }
14495 break;
14496 case DRM_FORMAT_ABGR8888:
14497 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14498 INTEL_GEN(dev_priv) < 9) {
14499 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14500 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14501 goto err;
14502 }
14503 break;
14504 case DRM_FORMAT_XBGR8888:
14505 case DRM_FORMAT_XRGB2101010:
14506 case DRM_FORMAT_XBGR2101010:
14507 if (INTEL_GEN(dev_priv) < 4) {
14508 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14509 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14510 goto err;
14511 }
14512 break;
14513 case DRM_FORMAT_ABGR2101010:
14514 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14515 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14516 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14517 goto err;
14518 }
14519 break;
14520 case DRM_FORMAT_YUYV:
14521 case DRM_FORMAT_UYVY:
14522 case DRM_FORMAT_YVYU:
14523 case DRM_FORMAT_VYUY:
14524 if (INTEL_GEN(dev_priv) < 5) {
14525 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14526 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14527 goto err;
14528 }
14529 break;
14530 default:
14531 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14532 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14533 goto err;
14534 }
14535
14536 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14537 if (mode_cmd->offsets[0] != 0)
14538 goto err;
14539
14540 drm_helper_mode_fill_fb_struct(&dev_priv->drm,
14541 &intel_fb->base, mode_cmd);
14542
14543 stride_alignment = intel_fb_stride_alignment(&intel_fb->base, 0);
14544 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14545 DRM_DEBUG_KMS("pitch (%d) must be at least %u byte aligned\n",
14546 mode_cmd->pitches[0], stride_alignment);
14547 goto err;
14548 }
14549
14550 intel_fb->obj = obj;
14551
14552 ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
14553 if (ret)
14554 goto err;
14555
14556 ret = drm_framebuffer_init(obj->base.dev,
14557 &intel_fb->base,
14558 &intel_fb_funcs);
14559 if (ret) {
14560 DRM_ERROR("framebuffer init failed %d\n", ret);
14561 goto err;
14562 }
14563
14564 return 0;
14565
14566 err:
14567 i915_gem_object_lock(obj);
14568 obj->framebuffer_references--;
14569 i915_gem_object_unlock(obj);
14570 return ret;
14571 }
14572
14573 static struct drm_framebuffer *
14574 intel_user_framebuffer_create(struct drm_device *dev,
14575 struct drm_file *filp,
14576 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14577 {
14578 struct drm_framebuffer *fb;
14579 struct drm_i915_gem_object *obj;
14580 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14581
14582 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14583 if (!obj)
14584 return ERR_PTR(-ENOENT);
14585
14586 fb = intel_framebuffer_create(obj, &mode_cmd);
14587 if (IS_ERR(fb))
14588 i915_gem_object_put(obj);
14589
14590 return fb;
14591 }
14592
14593 static void intel_atomic_state_free(struct drm_atomic_state *state)
14594 {
14595 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14596
14597 drm_atomic_state_default_release(state);
14598
14599 i915_sw_fence_fini(&intel_state->commit_ready);
14600
14601 kfree(state);
14602 }
14603
14604 static const struct drm_mode_config_funcs intel_mode_funcs = {
14605 .fb_create = intel_user_framebuffer_create,
14606 .output_poll_changed = intel_fbdev_output_poll_changed,
14607 .atomic_check = intel_atomic_check,
14608 .atomic_commit = intel_atomic_commit,
14609 .atomic_state_alloc = intel_atomic_state_alloc,
14610 .atomic_state_clear = intel_atomic_state_clear,
14611 .atomic_state_free = intel_atomic_state_free,
14612 };
14613
14614 /**
14615 * intel_init_display_hooks - initialize the display modesetting hooks
14616 * @dev_priv: device private
14617 */
14618 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14619 {
14620 intel_init_cdclk_hooks(dev_priv);
14621
14622 if (INTEL_INFO(dev_priv)->gen >= 9) {
14623 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14624 dev_priv->display.get_initial_plane_config =
14625 skylake_get_initial_plane_config;
14626 dev_priv->display.crtc_compute_clock =
14627 haswell_crtc_compute_clock;
14628 dev_priv->display.crtc_enable = haswell_crtc_enable;
14629 dev_priv->display.crtc_disable = haswell_crtc_disable;
14630 } else if (HAS_DDI(dev_priv)) {
14631 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14632 dev_priv->display.get_initial_plane_config =
14633 ironlake_get_initial_plane_config;
14634 dev_priv->display.crtc_compute_clock =
14635 haswell_crtc_compute_clock;
14636 dev_priv->display.crtc_enable = haswell_crtc_enable;
14637 dev_priv->display.crtc_disable = haswell_crtc_disable;
14638 } else if (HAS_PCH_SPLIT(dev_priv)) {
14639 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14640 dev_priv->display.get_initial_plane_config =
14641 ironlake_get_initial_plane_config;
14642 dev_priv->display.crtc_compute_clock =
14643 ironlake_crtc_compute_clock;
14644 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14645 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14646 } else if (IS_CHERRYVIEW(dev_priv)) {
14647 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14648 dev_priv->display.get_initial_plane_config =
14649 i9xx_get_initial_plane_config;
14650 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14651 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14652 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14653 } else if (IS_VALLEYVIEW(dev_priv)) {
14654 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14655 dev_priv->display.get_initial_plane_config =
14656 i9xx_get_initial_plane_config;
14657 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14658 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14659 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14660 } else if (IS_G4X(dev_priv)) {
14661 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14662 dev_priv->display.get_initial_plane_config =
14663 i9xx_get_initial_plane_config;
14664 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14665 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14666 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14667 } else if (IS_PINEVIEW(dev_priv)) {
14668 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14669 dev_priv->display.get_initial_plane_config =
14670 i9xx_get_initial_plane_config;
14671 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14672 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14673 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14674 } else if (!IS_GEN2(dev_priv)) {
14675 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14676 dev_priv->display.get_initial_plane_config =
14677 i9xx_get_initial_plane_config;
14678 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14679 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14680 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14681 } else {
14682 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14683 dev_priv->display.get_initial_plane_config =
14684 i9xx_get_initial_plane_config;
14685 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14686 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14687 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14688 }
14689
14690 if (IS_GEN5(dev_priv)) {
14691 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14692 } else if (IS_GEN6(dev_priv)) {
14693 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14694 } else if (IS_IVYBRIDGE(dev_priv)) {
14695 /* FIXME: detect B0+ stepping and use auto training */
14696 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14697 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14698 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14699 }
14700
14701 if (dev_priv->info.gen >= 9)
14702 dev_priv->display.update_crtcs = skl_update_crtcs;
14703 else
14704 dev_priv->display.update_crtcs = intel_update_crtcs;
14705
14706 switch (INTEL_INFO(dev_priv)->gen) {
14707 case 2:
14708 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14709 break;
14710
14711 case 3:
14712 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14713 break;
14714
14715 case 4:
14716 case 5:
14717 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14718 break;
14719
14720 case 6:
14721 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14722 break;
14723 case 7:
14724 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14725 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14726 break;
14727 case 9:
14728 /* Drop through - unsupported since execlist only. */
14729 default:
14730 /* Default just returns -ENODEV to indicate unsupported */
14731 dev_priv->display.queue_flip = intel_default_queue_flip;
14732 }
14733 }
14734
14735 /*
14736 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14737 * resume, or other times. This quirk makes sure that's the case for
14738 * affected systems.
14739 */
14740 static void quirk_pipea_force(struct drm_device *dev)
14741 {
14742 struct drm_i915_private *dev_priv = to_i915(dev);
14743
14744 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14745 DRM_INFO("applying pipe a force quirk\n");
14746 }
14747
14748 static void quirk_pipeb_force(struct drm_device *dev)
14749 {
14750 struct drm_i915_private *dev_priv = to_i915(dev);
14751
14752 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14753 DRM_INFO("applying pipe b force quirk\n");
14754 }
14755
14756 /*
14757 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14758 */
14759 static void quirk_ssc_force_disable(struct drm_device *dev)
14760 {
14761 struct drm_i915_private *dev_priv = to_i915(dev);
14762 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14763 DRM_INFO("applying lvds SSC disable quirk\n");
14764 }
14765
14766 /*
14767 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14768 * brightness value
14769 */
14770 static void quirk_invert_brightness(struct drm_device *dev)
14771 {
14772 struct drm_i915_private *dev_priv = to_i915(dev);
14773 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14774 DRM_INFO("applying inverted panel brightness quirk\n");
14775 }
14776
14777 /* Some VBT's incorrectly indicate no backlight is present */
14778 static void quirk_backlight_present(struct drm_device *dev)
14779 {
14780 struct drm_i915_private *dev_priv = to_i915(dev);
14781 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14782 DRM_INFO("applying backlight present quirk\n");
14783 }
14784
14785 struct intel_quirk {
14786 int device;
14787 int subsystem_vendor;
14788 int subsystem_device;
14789 void (*hook)(struct drm_device *dev);
14790 };
14791
14792 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14793 struct intel_dmi_quirk {
14794 void (*hook)(struct drm_device *dev);
14795 const struct dmi_system_id (*dmi_id_list)[];
14796 };
14797
14798 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14799 {
14800 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14801 return 1;
14802 }
14803
14804 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14805 {
14806 .dmi_id_list = &(const struct dmi_system_id[]) {
14807 {
14808 .callback = intel_dmi_reverse_brightness,
14809 .ident = "NCR Corporation",
14810 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14811 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14812 },
14813 },
14814 { } /* terminating entry */
14815 },
14816 .hook = quirk_invert_brightness,
14817 },
14818 };
14819
14820 static struct intel_quirk intel_quirks[] = {
14821 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14822 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14823
14824 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14825 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14826
14827 /* 830 needs to leave pipe A & dpll A up */
14828 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14829
14830 /* 830 needs to leave pipe B & dpll B up */
14831 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14832
14833 /* Lenovo U160 cannot use SSC on LVDS */
14834 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14835
14836 /* Sony Vaio Y cannot use SSC on LVDS */
14837 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14838
14839 /* Acer Aspire 5734Z must invert backlight brightness */
14840 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14841
14842 /* Acer/eMachines G725 */
14843 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14844
14845 /* Acer/eMachines e725 */
14846 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14847
14848 /* Acer/Packard Bell NCL20 */
14849 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14850
14851 /* Acer Aspire 4736Z */
14852 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14853
14854 /* Acer Aspire 5336 */
14855 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14856
14857 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14858 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14859
14860 /* Acer C720 Chromebook (Core i3 4005U) */
14861 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14862
14863 /* Apple Macbook 2,1 (Core 2 T7400) */
14864 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14865
14866 /* Apple Macbook 4,1 */
14867 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14868
14869 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14870 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14871
14872 /* HP Chromebook 14 (Celeron 2955U) */
14873 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14874
14875 /* Dell Chromebook 11 */
14876 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14877
14878 /* Dell Chromebook 11 (2015 version) */
14879 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14880 };
14881
14882 static void intel_init_quirks(struct drm_device *dev)
14883 {
14884 struct pci_dev *d = dev->pdev;
14885 int i;
14886
14887 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14888 struct intel_quirk *q = &intel_quirks[i];
14889
14890 if (d->device == q->device &&
14891 (d->subsystem_vendor == q->subsystem_vendor ||
14892 q->subsystem_vendor == PCI_ANY_ID) &&
14893 (d->subsystem_device == q->subsystem_device ||
14894 q->subsystem_device == PCI_ANY_ID))
14895 q->hook(dev);
14896 }
14897 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14898 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14899 intel_dmi_quirks[i].hook(dev);
14900 }
14901 }
14902
14903 /* Disable the VGA plane that we never use */
14904 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14905 {
14906 struct pci_dev *pdev = dev_priv->drm.pdev;
14907 u8 sr1;
14908 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14909
14910 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14911 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14912 outb(SR01, VGA_SR_INDEX);
14913 sr1 = inb(VGA_SR_DATA);
14914 outb(sr1 | 1<<5, VGA_SR_DATA);
14915 vga_put(pdev, VGA_RSRC_LEGACY_IO);
14916 udelay(300);
14917
14918 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14919 POSTING_READ(vga_reg);
14920 }
14921
14922 void intel_modeset_init_hw(struct drm_device *dev)
14923 {
14924 struct drm_i915_private *dev_priv = to_i915(dev);
14925
14926 intel_update_cdclk(dev_priv);
14927 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14928
14929 intel_init_clock_gating(dev_priv);
14930 }
14931
14932 /*
14933 * Calculate what we think the watermarks should be for the state we've read
14934 * out of the hardware and then immediately program those watermarks so that
14935 * we ensure the hardware settings match our internal state.
14936 *
14937 * We can calculate what we think WM's should be by creating a duplicate of the
14938 * current state (which was constructed during hardware readout) and running it
14939 * through the atomic check code to calculate new watermark values in the
14940 * state object.
14941 */
14942 static void sanitize_watermarks(struct drm_device *dev)
14943 {
14944 struct drm_i915_private *dev_priv = to_i915(dev);
14945 struct drm_atomic_state *state;
14946 struct intel_atomic_state *intel_state;
14947 struct drm_crtc *crtc;
14948 struct drm_crtc_state *cstate;
14949 struct drm_modeset_acquire_ctx ctx;
14950 int ret;
14951 int i;
14952
14953 /* Only supported on platforms that use atomic watermark design */
14954 if (!dev_priv->display.optimize_watermarks)
14955 return;
14956
14957 /*
14958 * We need to hold connection_mutex before calling duplicate_state so
14959 * that the connector loop is protected.
14960 */
14961 drm_modeset_acquire_init(&ctx, 0);
14962 retry:
14963 ret = drm_modeset_lock_all_ctx(dev, &ctx);
14964 if (ret == -EDEADLK) {
14965 drm_modeset_backoff(&ctx);
14966 goto retry;
14967 } else if (WARN_ON(ret)) {
14968 goto fail;
14969 }
14970
14971 state = drm_atomic_helper_duplicate_state(dev, &ctx);
14972 if (WARN_ON(IS_ERR(state)))
14973 goto fail;
14974
14975 intel_state = to_intel_atomic_state(state);
14976
14977 /*
14978 * Hardware readout is the only time we don't want to calculate
14979 * intermediate watermarks (since we don't trust the current
14980 * watermarks).
14981 */
14982 if (!HAS_GMCH_DISPLAY(dev_priv))
14983 intel_state->skip_intermediate_wm = true;
14984
14985 ret = intel_atomic_check(dev, state);
14986 if (ret) {
14987 /*
14988 * If we fail here, it means that the hardware appears to be
14989 * programmed in a way that shouldn't be possible, given our
14990 * understanding of watermark requirements. This might mean a
14991 * mistake in the hardware readout code or a mistake in the
14992 * watermark calculations for a given platform. Raise a WARN
14993 * so that this is noticeable.
14994 *
14995 * If this actually happens, we'll have to just leave the
14996 * BIOS-programmed watermarks untouched and hope for the best.
14997 */
14998 WARN(true, "Could not determine valid watermarks for inherited state\n");
14999 goto put_state;
15000 }
15001
15002 /* Write calculated watermark values back */
15003 for_each_new_crtc_in_state(state, crtc, cstate, i) {
15004 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15005
15006 cs->wm.need_postvbl_update = true;
15007 dev_priv->display.optimize_watermarks(intel_state, cs);
15008 }
15009
15010 put_state:
15011 drm_atomic_state_put(state);
15012 fail:
15013 drm_modeset_drop_locks(&ctx);
15014 drm_modeset_acquire_fini(&ctx);
15015 }
15016
15017 int intel_modeset_init(struct drm_device *dev)
15018 {
15019 struct drm_i915_private *dev_priv = to_i915(dev);
15020 struct i915_ggtt *ggtt = &dev_priv->ggtt;
15021 enum pipe pipe;
15022 struct intel_crtc *crtc;
15023
15024 drm_mode_config_init(dev);
15025
15026 dev->mode_config.min_width = 0;
15027 dev->mode_config.min_height = 0;
15028
15029 dev->mode_config.preferred_depth = 24;
15030 dev->mode_config.prefer_shadow = 1;
15031
15032 dev->mode_config.allow_fb_modifiers = true;
15033
15034 dev->mode_config.funcs = &intel_mode_funcs;
15035
15036 INIT_WORK(&dev_priv->atomic_helper.free_work,
15037 intel_atomic_helper_free_state_worker);
15038
15039 intel_init_quirks(dev);
15040
15041 intel_init_pm(dev_priv);
15042
15043 if (INTEL_INFO(dev_priv)->num_pipes == 0)
15044 return 0;
15045
15046 /*
15047 * There may be no VBT; and if the BIOS enabled SSC we can
15048 * just keep using it to avoid unnecessary flicker. Whereas if the
15049 * BIOS isn't using it, don't assume it will work even if the VBT
15050 * indicates as much.
15051 */
15052 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
15053 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15054 DREF_SSC1_ENABLE);
15055
15056 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15057 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15058 bios_lvds_use_ssc ? "en" : "dis",
15059 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15060 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15061 }
15062 }
15063
15064 if (IS_GEN2(dev_priv)) {
15065 dev->mode_config.max_width = 2048;
15066 dev->mode_config.max_height = 2048;
15067 } else if (IS_GEN3(dev_priv)) {
15068 dev->mode_config.max_width = 4096;
15069 dev->mode_config.max_height = 4096;
15070 } else {
15071 dev->mode_config.max_width = 8192;
15072 dev->mode_config.max_height = 8192;
15073 }
15074
15075 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15076 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
15077 dev->mode_config.cursor_height = 1023;
15078 } else if (IS_GEN2(dev_priv)) {
15079 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15080 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15081 } else {
15082 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15083 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15084 }
15085
15086 dev->mode_config.fb_base = ggtt->mappable_base;
15087
15088 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15089 INTEL_INFO(dev_priv)->num_pipes,
15090 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
15091
15092 for_each_pipe(dev_priv, pipe) {
15093 int ret;
15094
15095 ret = intel_crtc_init(dev_priv, pipe);
15096 if (ret) {
15097 drm_mode_config_cleanup(dev);
15098 return ret;
15099 }
15100 }
15101
15102 intel_shared_dpll_init(dev);
15103
15104 intel_update_czclk(dev_priv);
15105 intel_modeset_init_hw(dev);
15106
15107 if (dev_priv->max_cdclk_freq == 0)
15108 intel_update_max_cdclk(dev_priv);
15109
15110 /* Just disable it once at startup */
15111 i915_disable_vga(dev_priv);
15112 intel_setup_outputs(dev_priv);
15113
15114 drm_modeset_lock_all(dev);
15115 intel_modeset_setup_hw_state(dev);
15116 drm_modeset_unlock_all(dev);
15117
15118 for_each_intel_crtc(dev, crtc) {
15119 struct intel_initial_plane_config plane_config = {};
15120
15121 if (!crtc->active)
15122 continue;
15123
15124 /*
15125 * Note that reserving the BIOS fb up front prevents us
15126 * from stuffing other stolen allocations like the ring
15127 * on top. This prevents some ugliness at boot time, and
15128 * can even allow for smooth boot transitions if the BIOS
15129 * fb is large enough for the active pipe configuration.
15130 */
15131 dev_priv->display.get_initial_plane_config(crtc,
15132 &plane_config);
15133
15134 /*
15135 * If the fb is shared between multiple heads, we'll
15136 * just get the first one.
15137 */
15138 intel_find_initial_plane_obj(crtc, &plane_config);
15139 }
15140
15141 /*
15142 * Make sure hardware watermarks really match the state we read out.
15143 * Note that we need to do this after reconstructing the BIOS fb's
15144 * since the watermark calculation done here will use pstate->fb.
15145 */
15146 if (!HAS_GMCH_DISPLAY(dev_priv))
15147 sanitize_watermarks(dev);
15148
15149 return 0;
15150 }
15151
15152 static void intel_enable_pipe_a(struct drm_device *dev)
15153 {
15154 struct intel_connector *connector;
15155 struct drm_connector_list_iter conn_iter;
15156 struct drm_connector *crt = NULL;
15157 struct intel_load_detect_pipe load_detect_temp;
15158 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15159
15160 /* We can't just switch on the pipe A, we need to set things up with a
15161 * proper mode and output configuration. As a gross hack, enable pipe A
15162 * by enabling the load detect pipe once. */
15163 drm_connector_list_iter_begin(dev, &conn_iter);
15164 for_each_intel_connector_iter(connector, &conn_iter) {
15165 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15166 crt = &connector->base;
15167 break;
15168 }
15169 }
15170 drm_connector_list_iter_end(&conn_iter);
15171
15172 if (!crt)
15173 return;
15174
15175 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15176 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15177 }
15178
15179 static bool
15180 intel_check_plane_mapping(struct intel_crtc *crtc)
15181 {
15182 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15183 u32 val;
15184
15185 if (INTEL_INFO(dev_priv)->num_pipes == 1)
15186 return true;
15187
15188 val = I915_READ(DSPCNTR(!crtc->plane));
15189
15190 if ((val & DISPLAY_PLANE_ENABLE) &&
15191 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15192 return false;
15193
15194 return true;
15195 }
15196
15197 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15198 {
15199 struct drm_device *dev = crtc->base.dev;
15200 struct intel_encoder *encoder;
15201
15202 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15203 return true;
15204
15205 return false;
15206 }
15207
15208 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15209 {
15210 struct drm_device *dev = encoder->base.dev;
15211 struct intel_connector *connector;
15212
15213 for_each_connector_on_encoder(dev, &encoder->base, connector)
15214 return connector;
15215
15216 return NULL;
15217 }
15218
15219 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15220 enum transcoder pch_transcoder)
15221 {
15222 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15223 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
15224 }
15225
15226 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15227 {
15228 struct drm_device *dev = crtc->base.dev;
15229 struct drm_i915_private *dev_priv = to_i915(dev);
15230 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15231
15232 /* Clear any frame start delays used for debugging left by the BIOS */
15233 if (!transcoder_is_dsi(cpu_transcoder)) {
15234 i915_reg_t reg = PIPECONF(cpu_transcoder);
15235
15236 I915_WRITE(reg,
15237 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15238 }
15239
15240 /* restore vblank interrupts to correct state */
15241 drm_crtc_vblank_reset(&crtc->base);
15242 if (crtc->active) {
15243 struct intel_plane *plane;
15244
15245 drm_crtc_vblank_on(&crtc->base);
15246
15247 /* Disable everything but the primary plane */
15248 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15249 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15250 continue;
15251
15252 trace_intel_disable_plane(&plane->base, crtc);
15253 plane->disable_plane(&plane->base, &crtc->base);
15254 }
15255 }
15256
15257 /* We need to sanitize the plane -> pipe mapping first because this will
15258 * disable the crtc (and hence change the state) if it is wrong. Note
15259 * that gen4+ has a fixed plane -> pipe mapping. */
15260 if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
15261 bool plane;
15262
15263 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15264 crtc->base.base.id, crtc->base.name);
15265
15266 /* Pipe has the wrong plane attached and the plane is active.
15267 * Temporarily change the plane mapping and disable everything
15268 * ... */
15269 plane = crtc->plane;
15270 crtc->base.primary->state->visible = true;
15271 crtc->plane = !plane;
15272 intel_crtc_disable_noatomic(&crtc->base);
15273 crtc->plane = plane;
15274 }
15275
15276 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15277 crtc->pipe == PIPE_A && !crtc->active) {
15278 /* BIOS forgot to enable pipe A, this mostly happens after
15279 * resume. Force-enable the pipe to fix this, the update_dpms
15280 * call below we restore the pipe to the right state, but leave
15281 * the required bits on. */
15282 intel_enable_pipe_a(dev);
15283 }
15284
15285 /* Adjust the state of the output pipe according to whether we
15286 * have active connectors/encoders. */
15287 if (crtc->active && !intel_crtc_has_encoders(crtc))
15288 intel_crtc_disable_noatomic(&crtc->base);
15289
15290 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
15291 /*
15292 * We start out with underrun reporting disabled to avoid races.
15293 * For correct bookkeeping mark this on active crtcs.
15294 *
15295 * Also on gmch platforms we dont have any hardware bits to
15296 * disable the underrun reporting. Which means we need to start
15297 * out with underrun reporting disabled also on inactive pipes,
15298 * since otherwise we'll complain about the garbage we read when
15299 * e.g. coming up after runtime pm.
15300 *
15301 * No protection against concurrent access is required - at
15302 * worst a fifo underrun happens which also sets this to false.
15303 */
15304 crtc->cpu_fifo_underrun_disabled = true;
15305 /*
15306 * We track the PCH trancoder underrun reporting state
15307 * within the crtc. With crtc for pipe A housing the underrun
15308 * reporting state for PCH transcoder A, crtc for pipe B housing
15309 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15310 * and marking underrun reporting as disabled for the non-existing
15311 * PCH transcoders B and C would prevent enabling the south
15312 * error interrupt (see cpt_can_enable_serr_int()).
15313 */
15314 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
15315 crtc->pch_fifo_underrun_disabled = true;
15316 }
15317 }
15318
15319 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15320 {
15321 struct intel_connector *connector;
15322
15323 /* We need to check both for a crtc link (meaning that the
15324 * encoder is active and trying to read from a pipe) and the
15325 * pipe itself being active. */
15326 bool has_active_crtc = encoder->base.crtc &&
15327 to_intel_crtc(encoder->base.crtc)->active;
15328
15329 connector = intel_encoder_find_connector(encoder);
15330 if (connector && !has_active_crtc) {
15331 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15332 encoder->base.base.id,
15333 encoder->base.name);
15334
15335 /* Connector is active, but has no active pipe. This is
15336 * fallout from our resume register restoring. Disable
15337 * the encoder manually again. */
15338 if (encoder->base.crtc) {
15339 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
15340
15341 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15342 encoder->base.base.id,
15343 encoder->base.name);
15344 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15345 if (encoder->post_disable)
15346 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15347 }
15348 encoder->base.crtc = NULL;
15349
15350 /* Inconsistent output/port/pipe state happens presumably due to
15351 * a bug in one of the get_hw_state functions. Or someplace else
15352 * in our code, like the register restore mess on resume. Clamp
15353 * things to off as a safer default. */
15354
15355 connector->base.dpms = DRM_MODE_DPMS_OFF;
15356 connector->base.encoder = NULL;
15357 }
15358 /* Enabled encoders without active connectors will be fixed in
15359 * the crtc fixup. */
15360 }
15361
15362 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
15363 {
15364 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15365
15366 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15367 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15368 i915_disable_vga(dev_priv);
15369 }
15370 }
15371
15372 void i915_redisable_vga(struct drm_i915_private *dev_priv)
15373 {
15374 /* This function can be called both from intel_modeset_setup_hw_state or
15375 * at a very early point in our resume sequence, where the power well
15376 * structures are not yet restored. Since this function is at a very
15377 * paranoid "someone might have enabled VGA while we were not looking"
15378 * level, just check if the power well is enabled instead of trying to
15379 * follow the "don't touch the power well if we don't need it" policy
15380 * the rest of the driver uses. */
15381 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15382 return;
15383
15384 i915_redisable_vga_power_on(dev_priv);
15385
15386 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15387 }
15388
15389 static bool primary_get_hw_state(struct intel_plane *plane)
15390 {
15391 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15392
15393 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15394 }
15395
15396 /* FIXME read out full plane state for all planes */
15397 static void readout_plane_state(struct intel_crtc *crtc)
15398 {
15399 struct intel_plane *primary = to_intel_plane(crtc->base.primary);
15400 bool visible;
15401
15402 visible = crtc->active && primary_get_hw_state(primary);
15403
15404 intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
15405 to_intel_plane_state(primary->base.state),
15406 visible);
15407 }
15408
15409 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15410 {
15411 struct drm_i915_private *dev_priv = to_i915(dev);
15412 enum pipe pipe;
15413 struct intel_crtc *crtc;
15414 struct intel_encoder *encoder;
15415 struct intel_connector *connector;
15416 struct drm_connector_list_iter conn_iter;
15417 int i;
15418
15419 dev_priv->active_crtcs = 0;
15420
15421 for_each_intel_crtc(dev, crtc) {
15422 struct intel_crtc_state *crtc_state =
15423 to_intel_crtc_state(crtc->base.state);
15424
15425 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15426 memset(crtc_state, 0, sizeof(*crtc_state));
15427 crtc_state->base.crtc = &crtc->base;
15428
15429 crtc_state->base.active = crtc_state->base.enable =
15430 dev_priv->display.get_pipe_config(crtc, crtc_state);
15431
15432 crtc->base.enabled = crtc_state->base.enable;
15433 crtc->active = crtc_state->base.active;
15434
15435 if (crtc_state->base.active)
15436 dev_priv->active_crtcs |= 1 << crtc->pipe;
15437
15438 readout_plane_state(crtc);
15439
15440 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15441 crtc->base.base.id, crtc->base.name,
15442 enableddisabled(crtc_state->base.active));
15443 }
15444
15445 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15446 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15447
15448 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15449 &pll->state.hw_state);
15450 pll->state.crtc_mask = 0;
15451 for_each_intel_crtc(dev, crtc) {
15452 struct intel_crtc_state *crtc_state =
15453 to_intel_crtc_state(crtc->base.state);
15454
15455 if (crtc_state->base.active &&
15456 crtc_state->shared_dpll == pll)
15457 pll->state.crtc_mask |= 1 << crtc->pipe;
15458 }
15459 pll->active_mask = pll->state.crtc_mask;
15460
15461 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15462 pll->name, pll->state.crtc_mask, pll->on);
15463 }
15464
15465 for_each_intel_encoder(dev, encoder) {
15466 pipe = 0;
15467
15468 if (encoder->get_hw_state(encoder, &pipe)) {
15469 struct intel_crtc_state *crtc_state;
15470
15471 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15472 crtc_state = to_intel_crtc_state(crtc->base.state);
15473
15474 encoder->base.crtc = &crtc->base;
15475 crtc_state->output_types |= 1 << encoder->type;
15476 encoder->get_config(encoder, crtc_state);
15477 } else {
15478 encoder->base.crtc = NULL;
15479 }
15480
15481 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15482 encoder->base.base.id, encoder->base.name,
15483 enableddisabled(encoder->base.crtc),
15484 pipe_name(pipe));
15485 }
15486
15487 drm_connector_list_iter_begin(dev, &conn_iter);
15488 for_each_intel_connector_iter(connector, &conn_iter) {
15489 if (connector->get_hw_state(connector)) {
15490 connector->base.dpms = DRM_MODE_DPMS_ON;
15491
15492 encoder = connector->encoder;
15493 connector->base.encoder = &encoder->base;
15494
15495 if (encoder->base.crtc &&
15496 encoder->base.crtc->state->active) {
15497 /*
15498 * This has to be done during hardware readout
15499 * because anything calling .crtc_disable may
15500 * rely on the connector_mask being accurate.
15501 */
15502 encoder->base.crtc->state->connector_mask |=
15503 1 << drm_connector_index(&connector->base);
15504 encoder->base.crtc->state->encoder_mask |=
15505 1 << drm_encoder_index(&encoder->base);
15506 }
15507
15508 } else {
15509 connector->base.dpms = DRM_MODE_DPMS_OFF;
15510 connector->base.encoder = NULL;
15511 }
15512 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15513 connector->base.base.id, connector->base.name,
15514 enableddisabled(connector->base.encoder));
15515 }
15516 drm_connector_list_iter_end(&conn_iter);
15517
15518 for_each_intel_crtc(dev, crtc) {
15519 struct intel_crtc_state *crtc_state =
15520 to_intel_crtc_state(crtc->base.state);
15521 int pixclk = 0;
15522
15523 crtc->base.hwmode = crtc_state->base.adjusted_mode;
15524
15525 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15526 if (crtc_state->base.active) {
15527 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15528 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15529 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15530
15531 /*
15532 * The initial mode needs to be set in order to keep
15533 * the atomic core happy. It wants a valid mode if the
15534 * crtc's enabled, so we do the above call.
15535 *
15536 * But we don't set all the derived state fully, hence
15537 * set a flag to indicate that a full recalculation is
15538 * needed on the next commit.
15539 */
15540 crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15541
15542 intel_crtc_compute_pixel_rate(crtc_state);
15543
15544 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) ||
15545 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15546 pixclk = crtc_state->pixel_rate;
15547 else
15548 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15549
15550 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15551 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
15552 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15553
15554 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15555 update_scanline_offset(crtc);
15556 }
15557
15558 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15559
15560 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15561 }
15562 }
15563
15564 static void
15565 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15566 {
15567 struct intel_encoder *encoder;
15568
15569 for_each_intel_encoder(&dev_priv->drm, encoder) {
15570 u64 get_domains;
15571 enum intel_display_power_domain domain;
15572
15573 if (!encoder->get_power_domains)
15574 continue;
15575
15576 get_domains = encoder->get_power_domains(encoder);
15577 for_each_power_domain(domain, get_domains)
15578 intel_display_power_get(dev_priv, domain);
15579 }
15580 }
15581
15582 /* Scan out the current hw modeset state,
15583 * and sanitizes it to the current state
15584 */
15585 static void
15586 intel_modeset_setup_hw_state(struct drm_device *dev)
15587 {
15588 struct drm_i915_private *dev_priv = to_i915(dev);
15589 enum pipe pipe;
15590 struct intel_crtc *crtc;
15591 struct intel_encoder *encoder;
15592 int i;
15593
15594 intel_modeset_readout_hw_state(dev);
15595
15596 /* HW state is read out, now we need to sanitize this mess. */
15597 get_encoder_power_domains(dev_priv);
15598
15599 for_each_intel_encoder(dev, encoder) {
15600 intel_sanitize_encoder(encoder);
15601 }
15602
15603 for_each_pipe(dev_priv, pipe) {
15604 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15605
15606 intel_sanitize_crtc(crtc);
15607 intel_dump_pipe_config(crtc, crtc->config,
15608 "[setup_hw_state]");
15609 }
15610
15611 intel_modeset_update_connector_atomic_state(dev);
15612
15613 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15614 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15615
15616 if (!pll->on || pll->active_mask)
15617 continue;
15618
15619 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15620
15621 pll->funcs.disable(dev_priv, pll);
15622 pll->on = false;
15623 }
15624
15625 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15626 vlv_wm_get_hw_state(dev);
15627 vlv_wm_sanitize(dev_priv);
15628 } else if (IS_GEN9(dev_priv)) {
15629 skl_wm_get_hw_state(dev);
15630 } else if (HAS_PCH_SPLIT(dev_priv)) {
15631 ilk_wm_get_hw_state(dev);
15632 }
15633
15634 for_each_intel_crtc(dev, crtc) {
15635 u64 put_domains;
15636
15637 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15638 if (WARN_ON(put_domains))
15639 modeset_put_power_domains(dev_priv, put_domains);
15640 }
15641 intel_display_set_init_power(dev_priv, false);
15642
15643 intel_power_domains_verify_state(dev_priv);
15644
15645 intel_fbc_init_pipe_state(dev_priv);
15646 }
15647
15648 void intel_display_resume(struct drm_device *dev)
15649 {
15650 struct drm_i915_private *dev_priv = to_i915(dev);
15651 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15652 struct drm_modeset_acquire_ctx ctx;
15653 int ret;
15654
15655 dev_priv->modeset_restore_state = NULL;
15656 if (state)
15657 state->acquire_ctx = &ctx;
15658
15659 /*
15660 * This is a cludge because with real atomic modeset mode_config.mutex
15661 * won't be taken. Unfortunately some probed state like
15662 * audio_codec_enable is still protected by mode_config.mutex, so lock
15663 * it here for now.
15664 */
15665 mutex_lock(&dev->mode_config.mutex);
15666 drm_modeset_acquire_init(&ctx, 0);
15667
15668 while (1) {
15669 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15670 if (ret != -EDEADLK)
15671 break;
15672
15673 drm_modeset_backoff(&ctx);
15674 }
15675
15676 if (!ret)
15677 ret = __intel_display_resume(dev, state, &ctx);
15678
15679 drm_modeset_drop_locks(&ctx);
15680 drm_modeset_acquire_fini(&ctx);
15681 mutex_unlock(&dev->mode_config.mutex);
15682
15683 if (ret)
15684 DRM_ERROR("Restoring old state failed with %i\n", ret);
15685 if (state)
15686 drm_atomic_state_put(state);
15687 }
15688
15689 void intel_modeset_gem_init(struct drm_device *dev)
15690 {
15691 struct drm_i915_private *dev_priv = to_i915(dev);
15692
15693 intel_init_gt_powersave(dev_priv);
15694
15695 intel_setup_overlay(dev_priv);
15696 }
15697
15698 int intel_connector_register(struct drm_connector *connector)
15699 {
15700 struct intel_connector *intel_connector = to_intel_connector(connector);
15701 int ret;
15702
15703 ret = intel_backlight_device_register(intel_connector);
15704 if (ret)
15705 goto err;
15706
15707 return 0;
15708
15709 err:
15710 return ret;
15711 }
15712
15713 void intel_connector_unregister(struct drm_connector *connector)
15714 {
15715 struct intel_connector *intel_connector = to_intel_connector(connector);
15716
15717 intel_backlight_device_unregister(intel_connector);
15718 intel_panel_destroy_backlight(connector);
15719 }
15720
15721 void intel_modeset_cleanup(struct drm_device *dev)
15722 {
15723 struct drm_i915_private *dev_priv = to_i915(dev);
15724
15725 flush_work(&dev_priv->atomic_helper.free_work);
15726 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15727
15728 intel_disable_gt_powersave(dev_priv);
15729
15730 /*
15731 * Interrupts and polling as the first thing to avoid creating havoc.
15732 * Too much stuff here (turning of connectors, ...) would
15733 * experience fancy races otherwise.
15734 */
15735 intel_irq_uninstall(dev_priv);
15736
15737 /*
15738 * Due to the hpd irq storm handling the hotplug work can re-arm the
15739 * poll handlers. Hence disable polling after hpd handling is shut down.
15740 */
15741 drm_kms_helper_poll_fini(dev);
15742
15743 intel_unregister_dsm_handler();
15744
15745 intel_fbc_global_disable(dev_priv);
15746
15747 /* flush any delayed tasks or pending work */
15748 flush_scheduled_work();
15749
15750 drm_mode_config_cleanup(dev);
15751
15752 intel_cleanup_overlay(dev_priv);
15753
15754 intel_cleanup_gt_powersave(dev_priv);
15755
15756 intel_teardown_gmbus(dev_priv);
15757 }
15758
15759 void intel_connector_attach_encoder(struct intel_connector *connector,
15760 struct intel_encoder *encoder)
15761 {
15762 connector->encoder = encoder;
15763 drm_mode_connector_attach_encoder(&connector->base,
15764 &encoder->base);
15765 }
15766
15767 /*
15768 * set vga decode state - true == enable VGA decode
15769 */
15770 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15771 {
15772 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15773 u16 gmch_ctrl;
15774
15775 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15776 DRM_ERROR("failed to read control word\n");
15777 return -EIO;
15778 }
15779
15780 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15781 return 0;
15782
15783 if (state)
15784 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15785 else
15786 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15787
15788 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15789 DRM_ERROR("failed to write control word\n");
15790 return -EIO;
15791 }
15792
15793 return 0;
15794 }
15795
15796 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15797
15798 struct intel_display_error_state {
15799
15800 u32 power_well_driver;
15801
15802 int num_transcoders;
15803
15804 struct intel_cursor_error_state {
15805 u32 control;
15806 u32 position;
15807 u32 base;
15808 u32 size;
15809 } cursor[I915_MAX_PIPES];
15810
15811 struct intel_pipe_error_state {
15812 bool power_domain_on;
15813 u32 source;
15814 u32 stat;
15815 } pipe[I915_MAX_PIPES];
15816
15817 struct intel_plane_error_state {
15818 u32 control;
15819 u32 stride;
15820 u32 size;
15821 u32 pos;
15822 u32 addr;
15823 u32 surface;
15824 u32 tile_offset;
15825 } plane[I915_MAX_PIPES];
15826
15827 struct intel_transcoder_error_state {
15828 bool power_domain_on;
15829 enum transcoder cpu_transcoder;
15830
15831 u32 conf;
15832
15833 u32 htotal;
15834 u32 hblank;
15835 u32 hsync;
15836 u32 vtotal;
15837 u32 vblank;
15838 u32 vsync;
15839 } transcoder[4];
15840 };
15841
15842 struct intel_display_error_state *
15843 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15844 {
15845 struct intel_display_error_state *error;
15846 int transcoders[] = {
15847 TRANSCODER_A,
15848 TRANSCODER_B,
15849 TRANSCODER_C,
15850 TRANSCODER_EDP,
15851 };
15852 int i;
15853
15854 if (INTEL_INFO(dev_priv)->num_pipes == 0)
15855 return NULL;
15856
15857 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15858 if (error == NULL)
15859 return NULL;
15860
15861 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15862 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15863
15864 for_each_pipe(dev_priv, i) {
15865 error->pipe[i].power_domain_on =
15866 __intel_display_power_is_enabled(dev_priv,
15867 POWER_DOMAIN_PIPE(i));
15868 if (!error->pipe[i].power_domain_on)
15869 continue;
15870
15871 error->cursor[i].control = I915_READ(CURCNTR(i));
15872 error->cursor[i].position = I915_READ(CURPOS(i));
15873 error->cursor[i].base = I915_READ(CURBASE(i));
15874
15875 error->plane[i].control = I915_READ(DSPCNTR(i));
15876 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15877 if (INTEL_GEN(dev_priv) <= 3) {
15878 error->plane[i].size = I915_READ(DSPSIZE(i));
15879 error->plane[i].pos = I915_READ(DSPPOS(i));
15880 }
15881 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15882 error->plane[i].addr = I915_READ(DSPADDR(i));
15883 if (INTEL_GEN(dev_priv) >= 4) {
15884 error->plane[i].surface = I915_READ(DSPSURF(i));
15885 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15886 }
15887
15888 error->pipe[i].source = I915_READ(PIPESRC(i));
15889
15890 if (HAS_GMCH_DISPLAY(dev_priv))
15891 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15892 }
15893
15894 /* Note: this does not include DSI transcoders. */
15895 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15896 if (HAS_DDI(dev_priv))
15897 error->num_transcoders++; /* Account for eDP. */
15898
15899 for (i = 0; i < error->num_transcoders; i++) {
15900 enum transcoder cpu_transcoder = transcoders[i];
15901
15902 error->transcoder[i].power_domain_on =
15903 __intel_display_power_is_enabled(dev_priv,
15904 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15905 if (!error->transcoder[i].power_domain_on)
15906 continue;
15907
15908 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15909
15910 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15911 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15912 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15913 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15914 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15915 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15916 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15917 }
15918
15919 return error;
15920 }
15921
15922 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15923
15924 void
15925 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15926 struct intel_display_error_state *error)
15927 {
15928 struct drm_i915_private *dev_priv = m->i915;
15929 int i;
15930
15931 if (!error)
15932 return;
15933
15934 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15935 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15936 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15937 error->power_well_driver);
15938 for_each_pipe(dev_priv, i) {
15939 err_printf(m, "Pipe [%d]:\n", i);
15940 err_printf(m, " Power: %s\n",
15941 onoff(error->pipe[i].power_domain_on));
15942 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15943 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15944
15945 err_printf(m, "Plane [%d]:\n", i);
15946 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15947 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15948 if (INTEL_GEN(dev_priv) <= 3) {
15949 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15950 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15951 }
15952 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15953 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15954 if (INTEL_GEN(dev_priv) >= 4) {
15955 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15956 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15957 }
15958
15959 err_printf(m, "Cursor [%d]:\n", i);
15960 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15961 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15962 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15963 }
15964
15965 for (i = 0; i < error->num_transcoders; i++) {
15966 err_printf(m, "CPU transcoder: %s\n",
15967 transcoder_name(error->transcoder[i].cpu_transcoder));
15968 err_printf(m, " Power: %s\n",
15969 onoff(error->transcoder[i].power_domain_on));
15970 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15971 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15972 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15973 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15974 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15975 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15976 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15977 }
15978 }
15979
15980 #endif
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