2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
32 #include "intel_drv.h"
35 #include "drm_dp_helper.h"
37 #include "drm_crtc_helper.h"
39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
41 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
);
42 static void intel_update_watermarks(struct drm_device
*dev
);
43 static void intel_increase_pllclock(struct drm_crtc
*crtc
, bool schedule
);
66 #define INTEL_P2_NUM 2
67 typedef struct intel_limit intel_limit_t
;
69 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
71 bool (* find_pll
)(const intel_limit_t
*, struct drm_crtc
*,
72 int, int, intel_clock_t
*);
75 #define I8XX_DOT_MIN 25000
76 #define I8XX_DOT_MAX 350000
77 #define I8XX_VCO_MIN 930000
78 #define I8XX_VCO_MAX 1400000
82 #define I8XX_M_MAX 140
83 #define I8XX_M1_MIN 18
84 #define I8XX_M1_MAX 26
86 #define I8XX_M2_MAX 16
88 #define I8XX_P_MAX 128
90 #define I8XX_P1_MAX 33
91 #define I8XX_P1_LVDS_MIN 1
92 #define I8XX_P1_LVDS_MAX 6
93 #define I8XX_P2_SLOW 4
94 #define I8XX_P2_FAST 2
95 #define I8XX_P2_LVDS_SLOW 14
96 #define I8XX_P2_LVDS_FAST 7
97 #define I8XX_P2_SLOW_LIMIT 165000
99 #define I9XX_DOT_MIN 20000
100 #define I9XX_DOT_MAX 400000
101 #define I9XX_VCO_MIN 1400000
102 #define I9XX_VCO_MAX 2800000
103 #define PINEVIEW_VCO_MIN 1700000
104 #define PINEVIEW_VCO_MAX 3500000
107 /* Pineview's Ncounter is a ring counter */
108 #define PINEVIEW_N_MIN 3
109 #define PINEVIEW_N_MAX 6
110 #define I9XX_M_MIN 70
111 #define I9XX_M_MAX 120
112 #define PINEVIEW_M_MIN 2
113 #define PINEVIEW_M_MAX 256
114 #define I9XX_M1_MIN 10
115 #define I9XX_M1_MAX 22
116 #define I9XX_M2_MIN 5
117 #define I9XX_M2_MAX 9
118 /* Pineview M1 is reserved, and must be 0 */
119 #define PINEVIEW_M1_MIN 0
120 #define PINEVIEW_M1_MAX 0
121 #define PINEVIEW_M2_MIN 0
122 #define PINEVIEW_M2_MAX 254
123 #define I9XX_P_SDVO_DAC_MIN 5
124 #define I9XX_P_SDVO_DAC_MAX 80
125 #define I9XX_P_LVDS_MIN 7
126 #define I9XX_P_LVDS_MAX 98
127 #define PINEVIEW_P_LVDS_MIN 7
128 #define PINEVIEW_P_LVDS_MAX 112
129 #define I9XX_P1_MIN 1
130 #define I9XX_P1_MAX 8
131 #define I9XX_P2_SDVO_DAC_SLOW 10
132 #define I9XX_P2_SDVO_DAC_FAST 5
133 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
134 #define I9XX_P2_LVDS_SLOW 14
135 #define I9XX_P2_LVDS_FAST 7
136 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
138 /*The parameter is for SDVO on G4x platform*/
139 #define G4X_DOT_SDVO_MIN 25000
140 #define G4X_DOT_SDVO_MAX 270000
141 #define G4X_VCO_MIN 1750000
142 #define G4X_VCO_MAX 3500000
143 #define G4X_N_SDVO_MIN 1
144 #define G4X_N_SDVO_MAX 4
145 #define G4X_M_SDVO_MIN 104
146 #define G4X_M_SDVO_MAX 138
147 #define G4X_M1_SDVO_MIN 17
148 #define G4X_M1_SDVO_MAX 23
149 #define G4X_M2_SDVO_MIN 5
150 #define G4X_M2_SDVO_MAX 11
151 #define G4X_P_SDVO_MIN 10
152 #define G4X_P_SDVO_MAX 30
153 #define G4X_P1_SDVO_MIN 1
154 #define G4X_P1_SDVO_MAX 3
155 #define G4X_P2_SDVO_SLOW 10
156 #define G4X_P2_SDVO_FAST 10
157 #define G4X_P2_SDVO_LIMIT 270000
159 /*The parameter is for HDMI_DAC on G4x platform*/
160 #define G4X_DOT_HDMI_DAC_MIN 22000
161 #define G4X_DOT_HDMI_DAC_MAX 400000
162 #define G4X_N_HDMI_DAC_MIN 1
163 #define G4X_N_HDMI_DAC_MAX 4
164 #define G4X_M_HDMI_DAC_MIN 104
165 #define G4X_M_HDMI_DAC_MAX 138
166 #define G4X_M1_HDMI_DAC_MIN 16
167 #define G4X_M1_HDMI_DAC_MAX 23
168 #define G4X_M2_HDMI_DAC_MIN 5
169 #define G4X_M2_HDMI_DAC_MAX 11
170 #define G4X_P_HDMI_DAC_MIN 5
171 #define G4X_P_HDMI_DAC_MAX 80
172 #define G4X_P1_HDMI_DAC_MIN 1
173 #define G4X_P1_HDMI_DAC_MAX 8
174 #define G4X_P2_HDMI_DAC_SLOW 10
175 #define G4X_P2_HDMI_DAC_FAST 5
176 #define G4X_P2_HDMI_DAC_LIMIT 165000
178 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
179 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
181 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
182 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
183 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
184 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
185 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
187 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
189 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
190 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
191 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
193 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
194 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
195 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
197 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
198 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
200 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
201 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
202 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
203 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
204 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
205 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
206 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
207 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
208 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
209 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
210 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
211 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
212 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
213 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
214 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
216 /*The parameter is for DISPLAY PORT on G4x platform*/
217 #define G4X_DOT_DISPLAY_PORT_MIN 161670
218 #define G4X_DOT_DISPLAY_PORT_MAX 227000
219 #define G4X_N_DISPLAY_PORT_MIN 1
220 #define G4X_N_DISPLAY_PORT_MAX 2
221 #define G4X_M_DISPLAY_PORT_MIN 97
222 #define G4X_M_DISPLAY_PORT_MAX 108
223 #define G4X_M1_DISPLAY_PORT_MIN 0x10
224 #define G4X_M1_DISPLAY_PORT_MAX 0x12
225 #define G4X_M2_DISPLAY_PORT_MIN 0x05
226 #define G4X_M2_DISPLAY_PORT_MAX 0x06
227 #define G4X_P_DISPLAY_PORT_MIN 10
228 #define G4X_P_DISPLAY_PORT_MAX 20
229 #define G4X_P1_DISPLAY_PORT_MIN 1
230 #define G4X_P1_DISPLAY_PORT_MAX 2
231 #define G4X_P2_DISPLAY_PORT_SLOW 10
232 #define G4X_P2_DISPLAY_PORT_FAST 10
233 #define G4X_P2_DISPLAY_PORT_LIMIT 0
236 /* as we calculate clock using (register_value + 2) for
237 N/M1/M2, so here the range value for them is (actual_value-2).
239 #define IRONLAKE_DOT_MIN 25000
240 #define IRONLAKE_DOT_MAX 350000
241 #define IRONLAKE_VCO_MIN 1760000
242 #define IRONLAKE_VCO_MAX 3510000
243 #define IRONLAKE_M1_MIN 12
244 #define IRONLAKE_M1_MAX 22
245 #define IRONLAKE_M2_MIN 5
246 #define IRONLAKE_M2_MAX 9
247 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
249 /* We have parameter ranges for different type of outputs. */
251 /* DAC & HDMI Refclk 120Mhz */
252 #define IRONLAKE_DAC_N_MIN 1
253 #define IRONLAKE_DAC_N_MAX 5
254 #define IRONLAKE_DAC_M_MIN 79
255 #define IRONLAKE_DAC_M_MAX 127
256 #define IRONLAKE_DAC_P_MIN 5
257 #define IRONLAKE_DAC_P_MAX 80
258 #define IRONLAKE_DAC_P1_MIN 1
259 #define IRONLAKE_DAC_P1_MAX 8
260 #define IRONLAKE_DAC_P2_SLOW 10
261 #define IRONLAKE_DAC_P2_FAST 5
263 /* LVDS single-channel 120Mhz refclk */
264 #define IRONLAKE_LVDS_S_N_MIN 1
265 #define IRONLAKE_LVDS_S_N_MAX 3
266 #define IRONLAKE_LVDS_S_M_MIN 79
267 #define IRONLAKE_LVDS_S_M_MAX 118
268 #define IRONLAKE_LVDS_S_P_MIN 28
269 #define IRONLAKE_LVDS_S_P_MAX 112
270 #define IRONLAKE_LVDS_S_P1_MIN 2
271 #define IRONLAKE_LVDS_S_P1_MAX 8
272 #define IRONLAKE_LVDS_S_P2_SLOW 14
273 #define IRONLAKE_LVDS_S_P2_FAST 14
275 /* LVDS dual-channel 120Mhz refclk */
276 #define IRONLAKE_LVDS_D_N_MIN 1
277 #define IRONLAKE_LVDS_D_N_MAX 3
278 #define IRONLAKE_LVDS_D_M_MIN 79
279 #define IRONLAKE_LVDS_D_M_MAX 127
280 #define IRONLAKE_LVDS_D_P_MIN 14
281 #define IRONLAKE_LVDS_D_P_MAX 56
282 #define IRONLAKE_LVDS_D_P1_MIN 2
283 #define IRONLAKE_LVDS_D_P1_MAX 8
284 #define IRONLAKE_LVDS_D_P2_SLOW 7
285 #define IRONLAKE_LVDS_D_P2_FAST 7
287 /* LVDS single-channel 100Mhz refclk */
288 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
289 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
290 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
291 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
292 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
293 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
294 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
295 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
296 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
297 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
299 /* LVDS dual-channel 100Mhz refclk */
300 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
301 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
302 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
303 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
304 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
305 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
306 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
307 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
308 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
309 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
312 #define IRONLAKE_DP_N_MIN 1
313 #define IRONLAKE_DP_N_MAX 2
314 #define IRONLAKE_DP_M_MIN 81
315 #define IRONLAKE_DP_M_MAX 90
316 #define IRONLAKE_DP_P_MIN 10
317 #define IRONLAKE_DP_P_MAX 20
318 #define IRONLAKE_DP_P2_FAST 10
319 #define IRONLAKE_DP_P2_SLOW 10
320 #define IRONLAKE_DP_P2_LIMIT 0
321 #define IRONLAKE_DP_P1_MIN 1
322 #define IRONLAKE_DP_P1_MAX 2
325 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
326 int target
, int refclk
, intel_clock_t
*best_clock
);
328 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
329 int target
, int refclk
, intel_clock_t
*best_clock
);
332 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
333 int target
, int refclk
, intel_clock_t
*best_clock
);
335 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
336 int target
, int refclk
, intel_clock_t
*best_clock
);
338 static const intel_limit_t intel_limits_i8xx_dvo
= {
339 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
340 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
341 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
342 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
343 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
344 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
345 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
346 .p1
= { .min
= I8XX_P1_MIN
, .max
= I8XX_P1_MAX
},
347 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
348 .p2_slow
= I8XX_P2_SLOW
, .p2_fast
= I8XX_P2_FAST
},
349 .find_pll
= intel_find_best_PLL
,
352 static const intel_limit_t intel_limits_i8xx_lvds
= {
353 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
354 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
355 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
356 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
357 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
358 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
359 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
360 .p1
= { .min
= I8XX_P1_LVDS_MIN
, .max
= I8XX_P1_LVDS_MAX
},
361 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
362 .p2_slow
= I8XX_P2_LVDS_SLOW
, .p2_fast
= I8XX_P2_LVDS_FAST
},
363 .find_pll
= intel_find_best_PLL
,
366 static const intel_limit_t intel_limits_i9xx_sdvo
= {
367 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
368 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
369 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
370 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
371 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
372 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
373 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
374 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
375 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
376 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
377 .find_pll
= intel_find_best_PLL
,
380 static const intel_limit_t intel_limits_i9xx_lvds
= {
381 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
382 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
383 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
384 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
385 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
386 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
387 .p
= { .min
= I9XX_P_LVDS_MIN
, .max
= I9XX_P_LVDS_MAX
},
388 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
389 /* The single-channel range is 25-112Mhz, and dual-channel
390 * is 80-224Mhz. Prefer single channel as much as possible.
392 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
393 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_FAST
},
394 .find_pll
= intel_find_best_PLL
,
397 /* below parameter and function is for G4X Chipset Family*/
398 static const intel_limit_t intel_limits_g4x_sdvo
= {
399 .dot
= { .min
= G4X_DOT_SDVO_MIN
, .max
= G4X_DOT_SDVO_MAX
},
400 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
401 .n
= { .min
= G4X_N_SDVO_MIN
, .max
= G4X_N_SDVO_MAX
},
402 .m
= { .min
= G4X_M_SDVO_MIN
, .max
= G4X_M_SDVO_MAX
},
403 .m1
= { .min
= G4X_M1_SDVO_MIN
, .max
= G4X_M1_SDVO_MAX
},
404 .m2
= { .min
= G4X_M2_SDVO_MIN
, .max
= G4X_M2_SDVO_MAX
},
405 .p
= { .min
= G4X_P_SDVO_MIN
, .max
= G4X_P_SDVO_MAX
},
406 .p1
= { .min
= G4X_P1_SDVO_MIN
, .max
= G4X_P1_SDVO_MAX
},
407 .p2
= { .dot_limit
= G4X_P2_SDVO_LIMIT
,
408 .p2_slow
= G4X_P2_SDVO_SLOW
,
409 .p2_fast
= G4X_P2_SDVO_FAST
411 .find_pll
= intel_g4x_find_best_PLL
,
414 static const intel_limit_t intel_limits_g4x_hdmi
= {
415 .dot
= { .min
= G4X_DOT_HDMI_DAC_MIN
, .max
= G4X_DOT_HDMI_DAC_MAX
},
416 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
417 .n
= { .min
= G4X_N_HDMI_DAC_MIN
, .max
= G4X_N_HDMI_DAC_MAX
},
418 .m
= { .min
= G4X_M_HDMI_DAC_MIN
, .max
= G4X_M_HDMI_DAC_MAX
},
419 .m1
= { .min
= G4X_M1_HDMI_DAC_MIN
, .max
= G4X_M1_HDMI_DAC_MAX
},
420 .m2
= { .min
= G4X_M2_HDMI_DAC_MIN
, .max
= G4X_M2_HDMI_DAC_MAX
},
421 .p
= { .min
= G4X_P_HDMI_DAC_MIN
, .max
= G4X_P_HDMI_DAC_MAX
},
422 .p1
= { .min
= G4X_P1_HDMI_DAC_MIN
, .max
= G4X_P1_HDMI_DAC_MAX
},
423 .p2
= { .dot_limit
= G4X_P2_HDMI_DAC_LIMIT
,
424 .p2_slow
= G4X_P2_HDMI_DAC_SLOW
,
425 .p2_fast
= G4X_P2_HDMI_DAC_FAST
427 .find_pll
= intel_g4x_find_best_PLL
,
430 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
431 .dot
= { .min
= G4X_DOT_SINGLE_CHANNEL_LVDS_MIN
,
432 .max
= G4X_DOT_SINGLE_CHANNEL_LVDS_MAX
},
433 .vco
= { .min
= G4X_VCO_MIN
,
434 .max
= G4X_VCO_MAX
},
435 .n
= { .min
= G4X_N_SINGLE_CHANNEL_LVDS_MIN
,
436 .max
= G4X_N_SINGLE_CHANNEL_LVDS_MAX
},
437 .m
= { .min
= G4X_M_SINGLE_CHANNEL_LVDS_MIN
,
438 .max
= G4X_M_SINGLE_CHANNEL_LVDS_MAX
},
439 .m1
= { .min
= G4X_M1_SINGLE_CHANNEL_LVDS_MIN
,
440 .max
= G4X_M1_SINGLE_CHANNEL_LVDS_MAX
},
441 .m2
= { .min
= G4X_M2_SINGLE_CHANNEL_LVDS_MIN
,
442 .max
= G4X_M2_SINGLE_CHANNEL_LVDS_MAX
},
443 .p
= { .min
= G4X_P_SINGLE_CHANNEL_LVDS_MIN
,
444 .max
= G4X_P_SINGLE_CHANNEL_LVDS_MAX
},
445 .p1
= { .min
= G4X_P1_SINGLE_CHANNEL_LVDS_MIN
,
446 .max
= G4X_P1_SINGLE_CHANNEL_LVDS_MAX
},
447 .p2
= { .dot_limit
= G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT
,
448 .p2_slow
= G4X_P2_SINGLE_CHANNEL_LVDS_SLOW
,
449 .p2_fast
= G4X_P2_SINGLE_CHANNEL_LVDS_FAST
451 .find_pll
= intel_g4x_find_best_PLL
,
454 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
455 .dot
= { .min
= G4X_DOT_DUAL_CHANNEL_LVDS_MIN
,
456 .max
= G4X_DOT_DUAL_CHANNEL_LVDS_MAX
},
457 .vco
= { .min
= G4X_VCO_MIN
,
458 .max
= G4X_VCO_MAX
},
459 .n
= { .min
= G4X_N_DUAL_CHANNEL_LVDS_MIN
,
460 .max
= G4X_N_DUAL_CHANNEL_LVDS_MAX
},
461 .m
= { .min
= G4X_M_DUAL_CHANNEL_LVDS_MIN
,
462 .max
= G4X_M_DUAL_CHANNEL_LVDS_MAX
},
463 .m1
= { .min
= G4X_M1_DUAL_CHANNEL_LVDS_MIN
,
464 .max
= G4X_M1_DUAL_CHANNEL_LVDS_MAX
},
465 .m2
= { .min
= G4X_M2_DUAL_CHANNEL_LVDS_MIN
,
466 .max
= G4X_M2_DUAL_CHANNEL_LVDS_MAX
},
467 .p
= { .min
= G4X_P_DUAL_CHANNEL_LVDS_MIN
,
468 .max
= G4X_P_DUAL_CHANNEL_LVDS_MAX
},
469 .p1
= { .min
= G4X_P1_DUAL_CHANNEL_LVDS_MIN
,
470 .max
= G4X_P1_DUAL_CHANNEL_LVDS_MAX
},
471 .p2
= { .dot_limit
= G4X_P2_DUAL_CHANNEL_LVDS_LIMIT
,
472 .p2_slow
= G4X_P2_DUAL_CHANNEL_LVDS_SLOW
,
473 .p2_fast
= G4X_P2_DUAL_CHANNEL_LVDS_FAST
475 .find_pll
= intel_g4x_find_best_PLL
,
478 static const intel_limit_t intel_limits_g4x_display_port
= {
479 .dot
= { .min
= G4X_DOT_DISPLAY_PORT_MIN
,
480 .max
= G4X_DOT_DISPLAY_PORT_MAX
},
481 .vco
= { .min
= G4X_VCO_MIN
,
483 .n
= { .min
= G4X_N_DISPLAY_PORT_MIN
,
484 .max
= G4X_N_DISPLAY_PORT_MAX
},
485 .m
= { .min
= G4X_M_DISPLAY_PORT_MIN
,
486 .max
= G4X_M_DISPLAY_PORT_MAX
},
487 .m1
= { .min
= G4X_M1_DISPLAY_PORT_MIN
,
488 .max
= G4X_M1_DISPLAY_PORT_MAX
},
489 .m2
= { .min
= G4X_M2_DISPLAY_PORT_MIN
,
490 .max
= G4X_M2_DISPLAY_PORT_MAX
},
491 .p
= { .min
= G4X_P_DISPLAY_PORT_MIN
,
492 .max
= G4X_P_DISPLAY_PORT_MAX
},
493 .p1
= { .min
= G4X_P1_DISPLAY_PORT_MIN
,
494 .max
= G4X_P1_DISPLAY_PORT_MAX
},
495 .p2
= { .dot_limit
= G4X_P2_DISPLAY_PORT_LIMIT
,
496 .p2_slow
= G4X_P2_DISPLAY_PORT_SLOW
,
497 .p2_fast
= G4X_P2_DISPLAY_PORT_FAST
},
498 .find_pll
= intel_find_pll_g4x_dp
,
501 static const intel_limit_t intel_limits_pineview_sdvo
= {
502 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
503 .vco
= { .min
= PINEVIEW_VCO_MIN
, .max
= PINEVIEW_VCO_MAX
},
504 .n
= { .min
= PINEVIEW_N_MIN
, .max
= PINEVIEW_N_MAX
},
505 .m
= { .min
= PINEVIEW_M_MIN
, .max
= PINEVIEW_M_MAX
},
506 .m1
= { .min
= PINEVIEW_M1_MIN
, .max
= PINEVIEW_M1_MAX
},
507 .m2
= { .min
= PINEVIEW_M2_MIN
, .max
= PINEVIEW_M2_MAX
},
508 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
509 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
510 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
511 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
512 .find_pll
= intel_find_best_PLL
,
515 static const intel_limit_t intel_limits_pineview_lvds
= {
516 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
517 .vco
= { .min
= PINEVIEW_VCO_MIN
, .max
= PINEVIEW_VCO_MAX
},
518 .n
= { .min
= PINEVIEW_N_MIN
, .max
= PINEVIEW_N_MAX
},
519 .m
= { .min
= PINEVIEW_M_MIN
, .max
= PINEVIEW_M_MAX
},
520 .m1
= { .min
= PINEVIEW_M1_MIN
, .max
= PINEVIEW_M1_MAX
},
521 .m2
= { .min
= PINEVIEW_M2_MIN
, .max
= PINEVIEW_M2_MAX
},
522 .p
= { .min
= PINEVIEW_P_LVDS_MIN
, .max
= PINEVIEW_P_LVDS_MAX
},
523 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
524 /* Pineview only supports single-channel mode. */
525 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
526 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_SLOW
},
527 .find_pll
= intel_find_best_PLL
,
530 static const intel_limit_t intel_limits_ironlake_dac
= {
531 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
532 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
533 .n
= { .min
= IRONLAKE_DAC_N_MIN
, .max
= IRONLAKE_DAC_N_MAX
},
534 .m
= { .min
= IRONLAKE_DAC_M_MIN
, .max
= IRONLAKE_DAC_M_MAX
},
535 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
536 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
537 .p
= { .min
= IRONLAKE_DAC_P_MIN
, .max
= IRONLAKE_DAC_P_MAX
},
538 .p1
= { .min
= IRONLAKE_DAC_P1_MIN
, .max
= IRONLAKE_DAC_P1_MAX
},
539 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
540 .p2_slow
= IRONLAKE_DAC_P2_SLOW
,
541 .p2_fast
= IRONLAKE_DAC_P2_FAST
},
542 .find_pll
= intel_g4x_find_best_PLL
,
545 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
546 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
547 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
548 .n
= { .min
= IRONLAKE_LVDS_S_N_MIN
, .max
= IRONLAKE_LVDS_S_N_MAX
},
549 .m
= { .min
= IRONLAKE_LVDS_S_M_MIN
, .max
= IRONLAKE_LVDS_S_M_MAX
},
550 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
551 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
552 .p
= { .min
= IRONLAKE_LVDS_S_P_MIN
, .max
= IRONLAKE_LVDS_S_P_MAX
},
553 .p1
= { .min
= IRONLAKE_LVDS_S_P1_MIN
, .max
= IRONLAKE_LVDS_S_P1_MAX
},
554 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
555 .p2_slow
= IRONLAKE_LVDS_S_P2_SLOW
,
556 .p2_fast
= IRONLAKE_LVDS_S_P2_FAST
},
557 .find_pll
= intel_g4x_find_best_PLL
,
560 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
561 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
562 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
563 .n
= { .min
= IRONLAKE_LVDS_D_N_MIN
, .max
= IRONLAKE_LVDS_D_N_MAX
},
564 .m
= { .min
= IRONLAKE_LVDS_D_M_MIN
, .max
= IRONLAKE_LVDS_D_M_MAX
},
565 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
566 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
567 .p
= { .min
= IRONLAKE_LVDS_D_P_MIN
, .max
= IRONLAKE_LVDS_D_P_MAX
},
568 .p1
= { .min
= IRONLAKE_LVDS_D_P1_MIN
, .max
= IRONLAKE_LVDS_D_P1_MAX
},
569 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
570 .p2_slow
= IRONLAKE_LVDS_D_P2_SLOW
,
571 .p2_fast
= IRONLAKE_LVDS_D_P2_FAST
},
572 .find_pll
= intel_g4x_find_best_PLL
,
575 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
576 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
577 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
578 .n
= { .min
= IRONLAKE_LVDS_S_SSC_N_MIN
, .max
= IRONLAKE_LVDS_S_SSC_N_MAX
},
579 .m
= { .min
= IRONLAKE_LVDS_S_SSC_M_MIN
, .max
= IRONLAKE_LVDS_S_SSC_M_MAX
},
580 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
581 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
582 .p
= { .min
= IRONLAKE_LVDS_S_SSC_P_MIN
, .max
= IRONLAKE_LVDS_S_SSC_P_MAX
},
583 .p1
= { .min
= IRONLAKE_LVDS_S_SSC_P1_MIN
,.max
= IRONLAKE_LVDS_S_SSC_P1_MAX
},
584 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
585 .p2_slow
= IRONLAKE_LVDS_S_SSC_P2_SLOW
,
586 .p2_fast
= IRONLAKE_LVDS_S_SSC_P2_FAST
},
587 .find_pll
= intel_g4x_find_best_PLL
,
590 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
591 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
592 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
593 .n
= { .min
= IRONLAKE_LVDS_D_SSC_N_MIN
, .max
= IRONLAKE_LVDS_D_SSC_N_MAX
},
594 .m
= { .min
= IRONLAKE_LVDS_D_SSC_M_MIN
, .max
= IRONLAKE_LVDS_D_SSC_M_MAX
},
595 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
596 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
597 .p
= { .min
= IRONLAKE_LVDS_D_SSC_P_MIN
, .max
= IRONLAKE_LVDS_D_SSC_P_MAX
},
598 .p1
= { .min
= IRONLAKE_LVDS_D_SSC_P1_MIN
,.max
= IRONLAKE_LVDS_D_SSC_P1_MAX
},
599 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
600 .p2_slow
= IRONLAKE_LVDS_D_SSC_P2_SLOW
,
601 .p2_fast
= IRONLAKE_LVDS_D_SSC_P2_FAST
},
602 .find_pll
= intel_g4x_find_best_PLL
,
605 static const intel_limit_t intel_limits_ironlake_display_port
= {
606 .dot
= { .min
= IRONLAKE_DOT_MIN
,
607 .max
= IRONLAKE_DOT_MAX
},
608 .vco
= { .min
= IRONLAKE_VCO_MIN
,
609 .max
= IRONLAKE_VCO_MAX
},
610 .n
= { .min
= IRONLAKE_DP_N_MIN
,
611 .max
= IRONLAKE_DP_N_MAX
},
612 .m
= { .min
= IRONLAKE_DP_M_MIN
,
613 .max
= IRONLAKE_DP_M_MAX
},
614 .m1
= { .min
= IRONLAKE_M1_MIN
,
615 .max
= IRONLAKE_M1_MAX
},
616 .m2
= { .min
= IRONLAKE_M2_MIN
,
617 .max
= IRONLAKE_M2_MAX
},
618 .p
= { .min
= IRONLAKE_DP_P_MIN
,
619 .max
= IRONLAKE_DP_P_MAX
},
620 .p1
= { .min
= IRONLAKE_DP_P1_MIN
,
621 .max
= IRONLAKE_DP_P1_MAX
},
622 .p2
= { .dot_limit
= IRONLAKE_DP_P2_LIMIT
,
623 .p2_slow
= IRONLAKE_DP_P2_SLOW
,
624 .p2_fast
= IRONLAKE_DP_P2_FAST
},
625 .find_pll
= intel_find_pll_ironlake_dp
,
628 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
)
630 struct drm_device
*dev
= crtc
->dev
;
631 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
632 const intel_limit_t
*limit
;
635 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
636 if (dev_priv
->lvds_use_ssc
&& dev_priv
->lvds_ssc_freq
== 100)
639 if ((I915_READ(PCH_LVDS
) & LVDS_CLKB_POWER_MASK
) ==
640 LVDS_CLKB_POWER_UP
) {
641 /* LVDS dual channel */
643 limit
= &intel_limits_ironlake_dual_lvds_100m
;
645 limit
= &intel_limits_ironlake_dual_lvds
;
648 limit
= &intel_limits_ironlake_single_lvds_100m
;
650 limit
= &intel_limits_ironlake_single_lvds
;
652 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
654 limit
= &intel_limits_ironlake_display_port
;
656 limit
= &intel_limits_ironlake_dac
;
661 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
663 struct drm_device
*dev
= crtc
->dev
;
664 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
665 const intel_limit_t
*limit
;
667 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
668 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
670 /* LVDS with dual channel */
671 limit
= &intel_limits_g4x_dual_channel_lvds
;
673 /* LVDS with dual channel */
674 limit
= &intel_limits_g4x_single_channel_lvds
;
675 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
676 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
677 limit
= &intel_limits_g4x_hdmi
;
678 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
679 limit
= &intel_limits_g4x_sdvo
;
680 } else if (intel_pipe_has_type (crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
681 limit
= &intel_limits_g4x_display_port
;
682 } else /* The option is for other outputs */
683 limit
= &intel_limits_i9xx_sdvo
;
688 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
)
690 struct drm_device
*dev
= crtc
->dev
;
691 const intel_limit_t
*limit
;
693 if (IS_IRONLAKE(dev
))
694 limit
= intel_ironlake_limit(crtc
);
695 else if (IS_G4X(dev
)) {
696 limit
= intel_g4x_limit(crtc
);
697 } else if (IS_I9XX(dev
) && !IS_PINEVIEW(dev
)) {
698 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
699 limit
= &intel_limits_i9xx_lvds
;
701 limit
= &intel_limits_i9xx_sdvo
;
702 } else if (IS_PINEVIEW(dev
)) {
703 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
704 limit
= &intel_limits_pineview_lvds
;
706 limit
= &intel_limits_pineview_sdvo
;
708 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
709 limit
= &intel_limits_i8xx_lvds
;
711 limit
= &intel_limits_i8xx_dvo
;
716 /* m1 is reserved as 0 in Pineview, n is a ring counter */
717 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
719 clock
->m
= clock
->m2
+ 2;
720 clock
->p
= clock
->p1
* clock
->p2
;
721 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
722 clock
->dot
= clock
->vco
/ clock
->p
;
725 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
727 if (IS_PINEVIEW(dev
)) {
728 pineview_clock(refclk
, clock
);
731 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
732 clock
->p
= clock
->p1
* clock
->p2
;
733 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
734 clock
->dot
= clock
->vco
/ clock
->p
;
738 * Returns whether any output on the specified pipe is of the specified type
740 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
)
742 struct drm_device
*dev
= crtc
->dev
;
743 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
744 struct drm_connector
*l_entry
;
746 list_for_each_entry(l_entry
, &mode_config
->connector_list
, head
) {
747 if (l_entry
->encoder
&&
748 l_entry
->encoder
->crtc
== crtc
) {
749 struct intel_output
*intel_output
= to_intel_output(l_entry
);
750 if (intel_output
->type
== type
)
757 struct drm_connector
*
758 intel_pipe_get_output (struct drm_crtc
*crtc
)
760 struct drm_device
*dev
= crtc
->dev
;
761 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
762 struct drm_connector
*l_entry
, *ret
= NULL
;
764 list_for_each_entry(l_entry
, &mode_config
->connector_list
, head
) {
765 if (l_entry
->encoder
&&
766 l_entry
->encoder
->crtc
== crtc
) {
774 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
776 * Returns whether the given set of divisors are valid for a given refclk with
777 * the given connectors.
780 static bool intel_PLL_is_valid(struct drm_crtc
*crtc
, intel_clock_t
*clock
)
782 const intel_limit_t
*limit
= intel_limit (crtc
);
783 struct drm_device
*dev
= crtc
->dev
;
785 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
786 INTELPllInvalid ("p1 out of range\n");
787 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
788 INTELPllInvalid ("p out of range\n");
789 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
790 INTELPllInvalid ("m2 out of range\n");
791 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
792 INTELPllInvalid ("m1 out of range\n");
793 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
794 INTELPllInvalid ("m1 <= m2\n");
795 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
796 INTELPllInvalid ("m out of range\n");
797 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
798 INTELPllInvalid ("n out of range\n");
799 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
800 INTELPllInvalid ("vco out of range\n");
801 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
802 * connector, etc., rather than just a single range.
804 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
805 INTELPllInvalid ("dot out of range\n");
811 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
812 int target
, int refclk
, intel_clock_t
*best_clock
)
815 struct drm_device
*dev
= crtc
->dev
;
816 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
820 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
821 (I915_READ(LVDS
)) != 0) {
823 * For LVDS, if the panel is on, just rely on its current
824 * settings for dual-channel. We haven't figured out how to
825 * reliably set up different single/dual channel state, if we
828 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
830 clock
.p2
= limit
->p2
.p2_fast
;
832 clock
.p2
= limit
->p2
.p2_slow
;
834 if (target
< limit
->p2
.dot_limit
)
835 clock
.p2
= limit
->p2
.p2_slow
;
837 clock
.p2
= limit
->p2
.p2_fast
;
840 memset (best_clock
, 0, sizeof (*best_clock
));
842 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
844 for (clock
.m2
= limit
->m2
.min
;
845 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
846 /* m1 is always 0 in Pineview */
847 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
849 for (clock
.n
= limit
->n
.min
;
850 clock
.n
<= limit
->n
.max
; clock
.n
++) {
851 for (clock
.p1
= limit
->p1
.min
;
852 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
855 intel_clock(dev
, refclk
, &clock
);
857 if (!intel_PLL_is_valid(crtc
, &clock
))
860 this_err
= abs(clock
.dot
- target
);
861 if (this_err
< err
) {
870 return (err
!= target
);
874 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
875 int target
, int refclk
, intel_clock_t
*best_clock
)
877 struct drm_device
*dev
= crtc
->dev
;
878 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
882 /* approximately equals target * 0.00488 */
883 int err_most
= (target
>> 8) + (target
>> 10);
886 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
889 if (IS_IRONLAKE(dev
))
893 if ((I915_READ(lvds_reg
) & LVDS_CLKB_POWER_MASK
) ==
895 clock
.p2
= limit
->p2
.p2_fast
;
897 clock
.p2
= limit
->p2
.p2_slow
;
899 if (target
< limit
->p2
.dot_limit
)
900 clock
.p2
= limit
->p2
.p2_slow
;
902 clock
.p2
= limit
->p2
.p2_fast
;
905 memset(best_clock
, 0, sizeof(*best_clock
));
906 max_n
= limit
->n
.max
;
907 /* based on hardware requriment prefer smaller n to precision */
908 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
909 /* based on hardware requirment prefere larger m1,m2 */
910 for (clock
.m1
= limit
->m1
.max
;
911 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
912 for (clock
.m2
= limit
->m2
.max
;
913 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
914 for (clock
.p1
= limit
->p1
.max
;
915 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
918 intel_clock(dev
, refclk
, &clock
);
919 if (!intel_PLL_is_valid(crtc
, &clock
))
921 this_err
= abs(clock
.dot
- target
) ;
922 if (this_err
< err_most
) {
936 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
937 int target
, int refclk
, intel_clock_t
*best_clock
)
939 struct drm_device
*dev
= crtc
->dev
;
942 /* return directly when it is eDP */
946 if (target
< 200000) {
959 intel_clock(dev
, refclk
, &clock
);
960 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
964 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
966 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
967 int target
, int refclk
, intel_clock_t
*best_clock
)
970 if (target
< 200000) {
983 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
984 clock
.p
= (clock
.p1
* clock
.p2
);
985 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
987 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
992 intel_wait_for_vblank(struct drm_device
*dev
)
994 /* Wait for 20ms, i.e. one cycle at 50hz. */
998 /* Parameters have changed, update FBC info */
999 static void i8xx_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1001 struct drm_device
*dev
= crtc
->dev
;
1002 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1003 struct drm_framebuffer
*fb
= crtc
->fb
;
1004 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1005 struct drm_i915_gem_object
*obj_priv
= intel_fb
->obj
->driver_private
;
1006 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1008 u32 fbc_ctl
, fbc_ctl2
;
1010 dev_priv
->cfb_pitch
= dev_priv
->cfb_size
/ FBC_LL_SIZE
;
1012 if (fb
->pitch
< dev_priv
->cfb_pitch
)
1013 dev_priv
->cfb_pitch
= fb
->pitch
;
1015 /* FBC_CTL wants 64B units */
1016 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1017 dev_priv
->cfb_fence
= obj_priv
->fence_reg
;
1018 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1019 plane
= dev_priv
->cfb_plane
== 0 ? FBC_CTL_PLANEA
: FBC_CTL_PLANEB
;
1021 /* Clear old tags */
1022 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
1023 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
1026 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| plane
;
1027 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1028 fbc_ctl2
|= FBC_CTL_CPU_FENCE
;
1029 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
1030 I915_WRITE(FBC_FENCE_OFF
, crtc
->y
);
1033 fbc_ctl
= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
1035 fbc_ctl
|= FBC_C3_IDLE
; /* 945 needs special SR handling */
1036 fbc_ctl
|= (dev_priv
->cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
1037 fbc_ctl
|= (interval
& 0x2fff) << FBC_CTL_INTERVAL_SHIFT
;
1038 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1039 fbc_ctl
|= dev_priv
->cfb_fence
;
1040 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
1042 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1043 dev_priv
->cfb_pitch
, crtc
->y
, dev_priv
->cfb_plane
);
1046 void i8xx_disable_fbc(struct drm_device
*dev
)
1048 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1051 if (!I915_HAS_FBC(dev
))
1054 /* Disable compression */
1055 fbc_ctl
= I915_READ(FBC_CONTROL
);
1056 fbc_ctl
&= ~FBC_CTL_EN
;
1057 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
1059 /* Wait for compressing bit to clear */
1060 while (I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
)
1063 intel_wait_for_vblank(dev
);
1065 DRM_DEBUG_KMS("disabled FBC\n");
1068 static bool i8xx_fbc_enabled(struct drm_crtc
*crtc
)
1070 struct drm_device
*dev
= crtc
->dev
;
1071 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1073 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
1076 static void g4x_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1078 struct drm_device
*dev
= crtc
->dev
;
1079 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1080 struct drm_framebuffer
*fb
= crtc
->fb
;
1081 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1082 struct drm_i915_gem_object
*obj_priv
= intel_fb
->obj
->driver_private
;
1083 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1084 int plane
= (intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
:
1086 unsigned long stall_watermark
= 200;
1089 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1090 dev_priv
->cfb_fence
= obj_priv
->fence_reg
;
1091 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1093 dpfc_ctl
= plane
| DPFC_SR_EN
| DPFC_CTL_LIMIT_1X
;
1094 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1095 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| dev_priv
->cfb_fence
;
1096 I915_WRITE(DPFC_CHICKEN
, DPFC_HT_MODIFY
);
1098 I915_WRITE(DPFC_CHICKEN
, ~DPFC_HT_MODIFY
);
1101 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
1102 I915_WRITE(DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
1103 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
1104 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
1105 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->y
);
1108 I915_WRITE(DPFC_CONTROL
, I915_READ(DPFC_CONTROL
) | DPFC_CTL_EN
);
1110 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
1113 void g4x_disable_fbc(struct drm_device
*dev
)
1115 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1118 /* Disable compression */
1119 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
1120 dpfc_ctl
&= ~DPFC_CTL_EN
;
1121 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
1122 intel_wait_for_vblank(dev
);
1124 DRM_DEBUG_KMS("disabled FBC\n");
1127 static bool g4x_fbc_enabled(struct drm_crtc
*crtc
)
1129 struct drm_device
*dev
= crtc
->dev
;
1130 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1132 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
1136 * intel_update_fbc - enable/disable FBC as needed
1137 * @crtc: CRTC to point the compressor at
1138 * @mode: mode in use
1140 * Set up the framebuffer compression hardware at mode set time. We
1141 * enable it if possible:
1142 * - plane A only (on pre-965)
1143 * - no pixel mulitply/line duplication
1144 * - no alpha buffer discard
1146 * - framebuffer <= 2048 in width, 1536 in height
1148 * We can't assume that any compression will take place (worst case),
1149 * so the compressed buffer has to be the same size as the uncompressed
1150 * one. It also must reside (along with the line length buffer) in
1153 * We need to enable/disable FBC on a global basis.
1155 static void intel_update_fbc(struct drm_crtc
*crtc
,
1156 struct drm_display_mode
*mode
)
1158 struct drm_device
*dev
= crtc
->dev
;
1159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1160 struct drm_framebuffer
*fb
= crtc
->fb
;
1161 struct intel_framebuffer
*intel_fb
;
1162 struct drm_i915_gem_object
*obj_priv
;
1163 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1164 int plane
= intel_crtc
->plane
;
1166 if (!i915_powersave
)
1169 if (!dev_priv
->display
.fbc_enabled
||
1170 !dev_priv
->display
.enable_fbc
||
1171 !dev_priv
->display
.disable_fbc
)
1177 intel_fb
= to_intel_framebuffer(fb
);
1178 obj_priv
= intel_fb
->obj
->driver_private
;
1181 * If FBC is already on, we just have to verify that we can
1182 * keep it that way...
1183 * Need to disable if:
1184 * - changing FBC params (stride, fence, mode)
1185 * - new fb is too large to fit in compressed buffer
1186 * - going to an unsupported config (interlace, pixel multiply, etc.)
1188 if (intel_fb
->obj
->size
> dev_priv
->cfb_size
) {
1189 DRM_DEBUG_KMS("framebuffer too large, disabling "
1193 if ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
) ||
1194 (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)) {
1195 DRM_DEBUG_KMS("mode incompatible with compression, "
1199 if ((mode
->hdisplay
> 2048) ||
1200 (mode
->vdisplay
> 1536)) {
1201 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1204 if ((IS_I915GM(dev
) || IS_I945GM(dev
)) && plane
!= 0) {
1205 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1208 if (obj_priv
->tiling_mode
!= I915_TILING_X
) {
1209 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1213 if (dev_priv
->display
.fbc_enabled(crtc
)) {
1214 /* We can re-enable it in this case, but need to update pitch */
1215 if (fb
->pitch
> dev_priv
->cfb_pitch
)
1216 dev_priv
->display
.disable_fbc(dev
);
1217 if (obj_priv
->fence_reg
!= dev_priv
->cfb_fence
)
1218 dev_priv
->display
.disable_fbc(dev
);
1219 if (plane
!= dev_priv
->cfb_plane
)
1220 dev_priv
->display
.disable_fbc(dev
);
1223 if (!dev_priv
->display
.fbc_enabled(crtc
)) {
1224 /* Now try to turn it back on if possible */
1225 dev_priv
->display
.enable_fbc(crtc
, 500);
1231 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1232 /* Multiple disables should be harmless */
1233 if (dev_priv
->display
.fbc_enabled(crtc
))
1234 dev_priv
->display
.disable_fbc(dev
);
1238 intel_pin_and_fence_fb_obj(struct drm_device
*dev
, struct drm_gem_object
*obj
)
1240 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1244 switch (obj_priv
->tiling_mode
) {
1245 case I915_TILING_NONE
:
1246 alignment
= 64 * 1024;
1249 /* pin() will align the object as required by fence */
1253 /* FIXME: Is this true? */
1254 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1260 ret
= i915_gem_object_pin(obj
, alignment
);
1264 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1265 * fence, whereas 965+ only requires a fence if using
1266 * framebuffer compression. For simplicity, we always install
1267 * a fence as the cost is not that onerous.
1269 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
&&
1270 obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1271 ret
= i915_gem_object_get_fence_reg(obj
);
1273 i915_gem_object_unpin(obj
);
1282 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
1283 struct drm_framebuffer
*old_fb
)
1285 struct drm_device
*dev
= crtc
->dev
;
1286 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1287 struct drm_i915_master_private
*master_priv
;
1288 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1289 struct intel_framebuffer
*intel_fb
;
1290 struct drm_i915_gem_object
*obj_priv
;
1291 struct drm_gem_object
*obj
;
1292 int pipe
= intel_crtc
->pipe
;
1293 int plane
= intel_crtc
->plane
;
1294 unsigned long Start
, Offset
;
1295 int dspbase
= (plane
== 0 ? DSPAADDR
: DSPBADDR
);
1296 int dspsurf
= (plane
== 0 ? DSPASURF
: DSPBSURF
);
1297 int dspstride
= (plane
== 0) ? DSPASTRIDE
: DSPBSTRIDE
;
1298 int dsptileoff
= (plane
== 0 ? DSPATILEOFF
: DSPBTILEOFF
);
1299 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
1305 DRM_DEBUG_KMS("No FB bound\n");
1314 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
1318 intel_fb
= to_intel_framebuffer(crtc
->fb
);
1319 obj
= intel_fb
->obj
;
1320 obj_priv
= obj
->driver_private
;
1322 mutex_lock(&dev
->struct_mutex
);
1323 ret
= intel_pin_and_fence_fb_obj(dev
, obj
);
1325 mutex_unlock(&dev
->struct_mutex
);
1329 ret
= i915_gem_object_set_to_display_plane(obj
);
1331 i915_gem_object_unpin(obj
);
1332 mutex_unlock(&dev
->struct_mutex
);
1336 dspcntr
= I915_READ(dspcntr_reg
);
1337 /* Mask out pixel format bits in case we change it */
1338 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
1339 switch (crtc
->fb
->bits_per_pixel
) {
1341 dspcntr
|= DISPPLANE_8BPP
;
1344 if (crtc
->fb
->depth
== 15)
1345 dspcntr
|= DISPPLANE_15_16BPP
;
1347 dspcntr
|= DISPPLANE_16BPP
;
1351 if (crtc
->fb
->depth
== 30)
1352 dspcntr
|= DISPPLANE_32BPP_30BIT_NO_ALPHA
;
1354 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
1357 DRM_ERROR("Unknown color depth\n");
1358 i915_gem_object_unpin(obj
);
1359 mutex_unlock(&dev
->struct_mutex
);
1362 if (IS_I965G(dev
)) {
1363 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1364 dspcntr
|= DISPPLANE_TILED
;
1366 dspcntr
&= ~DISPPLANE_TILED
;
1369 if (IS_IRONLAKE(dev
))
1371 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
1373 I915_WRITE(dspcntr_reg
, dspcntr
);
1375 Start
= obj_priv
->gtt_offset
;
1376 Offset
= y
* crtc
->fb
->pitch
+ x
* (crtc
->fb
->bits_per_pixel
/ 8);
1378 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start
, Offset
, x
, y
);
1379 I915_WRITE(dspstride
, crtc
->fb
->pitch
);
1380 if (IS_I965G(dev
)) {
1381 I915_WRITE(dspbase
, Offset
);
1383 I915_WRITE(dspsurf
, Start
);
1385 I915_WRITE(dsptileoff
, (y
<< 16) | x
);
1387 I915_WRITE(dspbase
, Start
+ Offset
);
1391 if ((IS_I965G(dev
) || plane
== 0))
1392 intel_update_fbc(crtc
, &crtc
->mode
);
1394 intel_wait_for_vblank(dev
);
1397 intel_fb
= to_intel_framebuffer(old_fb
);
1398 obj_priv
= intel_fb
->obj
->driver_private
;
1399 i915_gem_object_unpin(intel_fb
->obj
);
1401 intel_increase_pllclock(crtc
, true);
1403 mutex_unlock(&dev
->struct_mutex
);
1405 if (!dev
->primary
->master
)
1408 master_priv
= dev
->primary
->master
->driver_priv
;
1409 if (!master_priv
->sarea_priv
)
1413 master_priv
->sarea_priv
->pipeB_x
= x
;
1414 master_priv
->sarea_priv
->pipeB_y
= y
;
1416 master_priv
->sarea_priv
->pipeA_x
= x
;
1417 master_priv
->sarea_priv
->pipeA_y
= y
;
1423 /* Disable the VGA plane that we never use */
1424 static void i915_disable_vga (struct drm_device
*dev
)
1426 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1430 if (IS_IRONLAKE(dev
))
1431 vga_reg
= CPU_VGACNTRL
;
1435 if (I915_READ(vga_reg
) & VGA_DISP_DISABLE
)
1438 I915_WRITE8(VGA_SR_INDEX
, 1);
1439 sr1
= I915_READ8(VGA_SR_DATA
);
1440 I915_WRITE8(VGA_SR_DATA
, sr1
| (1 << 5));
1443 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
1446 static void ironlake_disable_pll_edp (struct drm_crtc
*crtc
)
1448 struct drm_device
*dev
= crtc
->dev
;
1449 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1452 DRM_DEBUG_KMS("\n");
1453 dpa_ctl
= I915_READ(DP_A
);
1454 dpa_ctl
&= ~DP_PLL_ENABLE
;
1455 I915_WRITE(DP_A
, dpa_ctl
);
1458 static void ironlake_enable_pll_edp (struct drm_crtc
*crtc
)
1460 struct drm_device
*dev
= crtc
->dev
;
1461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1464 dpa_ctl
= I915_READ(DP_A
);
1465 dpa_ctl
|= DP_PLL_ENABLE
;
1466 I915_WRITE(DP_A
, dpa_ctl
);
1471 static void ironlake_set_pll_edp (struct drm_crtc
*crtc
, int clock
)
1473 struct drm_device
*dev
= crtc
->dev
;
1474 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1477 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock
);
1478 dpa_ctl
= I915_READ(DP_A
);
1479 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1481 if (clock
< 200000) {
1483 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1484 /* workaround for 160Mhz:
1485 1) program 0x4600c bits 15:0 = 0x8124
1486 2) program 0x46010 bit 0 = 1
1487 3) program 0x46034 bit 24 = 1
1488 4) program 0x64000 bit 14 = 1
1490 temp
= I915_READ(0x4600c);
1492 I915_WRITE(0x4600c, temp
| 0x8124);
1494 temp
= I915_READ(0x46010);
1495 I915_WRITE(0x46010, temp
| 1);
1497 temp
= I915_READ(0x46034);
1498 I915_WRITE(0x46034, temp
| (1 << 24));
1500 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1502 I915_WRITE(DP_A
, dpa_ctl
);
1507 static void ironlake_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
1509 struct drm_device
*dev
= crtc
->dev
;
1510 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1511 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1512 int pipe
= intel_crtc
->pipe
;
1513 int plane
= intel_crtc
->plane
;
1514 int pch_dpll_reg
= (pipe
== 0) ? PCH_DPLL_A
: PCH_DPLL_B
;
1515 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
1516 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
1517 int dspbase_reg
= (plane
== 0) ? DSPAADDR
: DSPBADDR
;
1518 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
1519 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
1520 int fdi_rx_iir_reg
= (pipe
== 0) ? FDI_RXA_IIR
: FDI_RXB_IIR
;
1521 int fdi_rx_imr_reg
= (pipe
== 0) ? FDI_RXA_IMR
: FDI_RXB_IMR
;
1522 int transconf_reg
= (pipe
== 0) ? TRANSACONF
: TRANSBCONF
;
1523 int pf_ctl_reg
= (pipe
== 0) ? PFA_CTL_1
: PFB_CTL_1
;
1524 int pf_win_size
= (pipe
== 0) ? PFA_WIN_SZ
: PFB_WIN_SZ
;
1525 int pf_win_pos
= (pipe
== 0) ? PFA_WIN_POS
: PFB_WIN_POS
;
1526 int cpu_htot_reg
= (pipe
== 0) ? HTOTAL_A
: HTOTAL_B
;
1527 int cpu_hblank_reg
= (pipe
== 0) ? HBLANK_A
: HBLANK_B
;
1528 int cpu_hsync_reg
= (pipe
== 0) ? HSYNC_A
: HSYNC_B
;
1529 int cpu_vtot_reg
= (pipe
== 0) ? VTOTAL_A
: VTOTAL_B
;
1530 int cpu_vblank_reg
= (pipe
== 0) ? VBLANK_A
: VBLANK_B
;
1531 int cpu_vsync_reg
= (pipe
== 0) ? VSYNC_A
: VSYNC_B
;
1532 int trans_htot_reg
= (pipe
== 0) ? TRANS_HTOTAL_A
: TRANS_HTOTAL_B
;
1533 int trans_hblank_reg
= (pipe
== 0) ? TRANS_HBLANK_A
: TRANS_HBLANK_B
;
1534 int trans_hsync_reg
= (pipe
== 0) ? TRANS_HSYNC_A
: TRANS_HSYNC_B
;
1535 int trans_vtot_reg
= (pipe
== 0) ? TRANS_VTOTAL_A
: TRANS_VTOTAL_B
;
1536 int trans_vblank_reg
= (pipe
== 0) ? TRANS_VBLANK_A
: TRANS_VBLANK_B
;
1537 int trans_vsync_reg
= (pipe
== 0) ? TRANS_VSYNC_A
: TRANS_VSYNC_B
;
1539 int tries
= 5, j
, n
;
1542 temp
= I915_READ(pipeconf_reg
);
1543 pipe_bpc
= temp
& PIPE_BPC_MASK
;
1545 /* XXX: When our outputs are all unaware of DPMS modes other than off
1546 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1549 case DRM_MODE_DPMS_ON
:
1550 case DRM_MODE_DPMS_STANDBY
:
1551 case DRM_MODE_DPMS_SUSPEND
:
1552 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe
);
1554 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
1555 temp
= I915_READ(PCH_LVDS
);
1556 if ((temp
& LVDS_PORT_EN
) == 0) {
1557 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
1558 POSTING_READ(PCH_LVDS
);
1563 /* enable eDP PLL */
1564 ironlake_enable_pll_edp(crtc
);
1566 /* enable PCH DPLL */
1567 temp
= I915_READ(pch_dpll_reg
);
1568 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
1569 I915_WRITE(pch_dpll_reg
, temp
| DPLL_VCO_ENABLE
);
1570 I915_READ(pch_dpll_reg
);
1573 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1574 temp
= I915_READ(fdi_rx_reg
);
1576 * make the BPC in FDI Rx be consistent with that in
1579 temp
&= ~(0x7 << 16);
1580 temp
|= (pipe_bpc
<< 11);
1581 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_PLL_ENABLE
|
1583 FDI_DP_PORT_WIDTH_X4
); /* default 4 lanes */
1584 I915_READ(fdi_rx_reg
);
1587 /* Enable CPU FDI TX PLL, always on for Ironlake */
1588 temp
= I915_READ(fdi_tx_reg
);
1589 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
1590 I915_WRITE(fdi_tx_reg
, temp
| FDI_TX_PLL_ENABLE
);
1591 I915_READ(fdi_tx_reg
);
1596 /* Enable panel fitting for LVDS */
1597 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
1598 temp
= I915_READ(pf_ctl_reg
);
1599 I915_WRITE(pf_ctl_reg
, temp
| PF_ENABLE
| PF_FILTER_MED_3x3
);
1601 /* currently full aspect */
1602 I915_WRITE(pf_win_pos
, 0);
1604 I915_WRITE(pf_win_size
,
1605 (dev_priv
->panel_fixed_mode
->hdisplay
<< 16) |
1606 (dev_priv
->panel_fixed_mode
->vdisplay
));
1609 /* Enable CPU pipe */
1610 temp
= I915_READ(pipeconf_reg
);
1611 if ((temp
& PIPEACONF_ENABLE
) == 0) {
1612 I915_WRITE(pipeconf_reg
, temp
| PIPEACONF_ENABLE
);
1613 I915_READ(pipeconf_reg
);
1617 /* configure and enable CPU plane */
1618 temp
= I915_READ(dspcntr_reg
);
1619 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
1620 I915_WRITE(dspcntr_reg
, temp
| DISPLAY_PLANE_ENABLE
);
1621 /* Flush the plane changes */
1622 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
1626 /* enable CPU FDI TX and PCH FDI RX */
1627 temp
= I915_READ(fdi_tx_reg
);
1628 temp
|= FDI_TX_ENABLE
;
1629 temp
|= FDI_DP_PORT_WIDTH_X4
; /* default */
1630 temp
&= ~FDI_LINK_TRAIN_NONE
;
1631 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1632 I915_WRITE(fdi_tx_reg
, temp
);
1633 I915_READ(fdi_tx_reg
);
1635 temp
= I915_READ(fdi_rx_reg
);
1636 temp
&= ~FDI_LINK_TRAIN_NONE
;
1637 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1638 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_ENABLE
);
1639 I915_READ(fdi_rx_reg
);
1644 /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1646 temp
= I915_READ(fdi_rx_imr_reg
);
1647 temp
&= ~FDI_RX_SYMBOL_LOCK
;
1648 temp
&= ~FDI_RX_BIT_LOCK
;
1649 I915_WRITE(fdi_rx_imr_reg
, temp
);
1650 I915_READ(fdi_rx_imr_reg
);
1653 temp
= I915_READ(fdi_rx_iir_reg
);
1654 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1656 if ((temp
& FDI_RX_BIT_LOCK
) == 0) {
1657 for (j
= 0; j
< tries
; j
++) {
1658 temp
= I915_READ(fdi_rx_iir_reg
);
1659 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1661 if (temp
& FDI_RX_BIT_LOCK
)
1666 I915_WRITE(fdi_rx_iir_reg
,
1667 temp
| FDI_RX_BIT_LOCK
);
1669 DRM_DEBUG_KMS("train 1 fail\n");
1671 I915_WRITE(fdi_rx_iir_reg
,
1672 temp
| FDI_RX_BIT_LOCK
);
1673 DRM_DEBUG_KMS("train 1 ok 2!\n");
1675 temp
= I915_READ(fdi_tx_reg
);
1676 temp
&= ~FDI_LINK_TRAIN_NONE
;
1677 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1678 I915_WRITE(fdi_tx_reg
, temp
);
1680 temp
= I915_READ(fdi_rx_reg
);
1681 temp
&= ~FDI_LINK_TRAIN_NONE
;
1682 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1683 I915_WRITE(fdi_rx_reg
, temp
);
1687 temp
= I915_READ(fdi_rx_iir_reg
);
1688 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1690 if ((temp
& FDI_RX_SYMBOL_LOCK
) == 0) {
1691 for (j
= 0; j
< tries
; j
++) {
1692 temp
= I915_READ(fdi_rx_iir_reg
);
1693 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1695 if (temp
& FDI_RX_SYMBOL_LOCK
)
1700 I915_WRITE(fdi_rx_iir_reg
,
1701 temp
| FDI_RX_SYMBOL_LOCK
);
1702 DRM_DEBUG_KMS("train 2 ok 1!\n");
1704 DRM_DEBUG_KMS("train 2 fail\n");
1706 I915_WRITE(fdi_rx_iir_reg
,
1707 temp
| FDI_RX_SYMBOL_LOCK
);
1708 DRM_DEBUG_KMS("train 2 ok 2!\n");
1710 DRM_DEBUG_KMS("train done\n");
1712 /* set transcoder timing */
1713 I915_WRITE(trans_htot_reg
, I915_READ(cpu_htot_reg
));
1714 I915_WRITE(trans_hblank_reg
, I915_READ(cpu_hblank_reg
));
1715 I915_WRITE(trans_hsync_reg
, I915_READ(cpu_hsync_reg
));
1717 I915_WRITE(trans_vtot_reg
, I915_READ(cpu_vtot_reg
));
1718 I915_WRITE(trans_vblank_reg
, I915_READ(cpu_vblank_reg
));
1719 I915_WRITE(trans_vsync_reg
, I915_READ(cpu_vsync_reg
));
1721 /* enable PCH transcoder */
1722 temp
= I915_READ(transconf_reg
);
1724 * make the BPC in transcoder be consistent with
1725 * that in pipeconf reg.
1727 temp
&= ~PIPE_BPC_MASK
;
1729 I915_WRITE(transconf_reg
, temp
| TRANS_ENABLE
);
1730 I915_READ(transconf_reg
);
1732 while ((I915_READ(transconf_reg
) & TRANS_STATE_ENABLE
) == 0)
1737 temp
= I915_READ(fdi_tx_reg
);
1738 temp
&= ~FDI_LINK_TRAIN_NONE
;
1739 I915_WRITE(fdi_tx_reg
, temp
| FDI_LINK_TRAIN_NONE
|
1740 FDI_TX_ENHANCE_FRAME_ENABLE
);
1741 I915_READ(fdi_tx_reg
);
1743 temp
= I915_READ(fdi_rx_reg
);
1744 temp
&= ~FDI_LINK_TRAIN_NONE
;
1745 I915_WRITE(fdi_rx_reg
, temp
| FDI_LINK_TRAIN_NONE
|
1746 FDI_RX_ENHANCE_FRAME_ENABLE
);
1747 I915_READ(fdi_rx_reg
);
1749 /* wait one idle pattern time */
1754 intel_crtc_load_lut(crtc
);
1757 case DRM_MODE_DPMS_OFF
:
1758 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe
);
1760 drm_vblank_off(dev
, pipe
);
1761 /* Disable display plane */
1762 temp
= I915_READ(dspcntr_reg
);
1763 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
1764 I915_WRITE(dspcntr_reg
, temp
& ~DISPLAY_PLANE_ENABLE
);
1765 /* Flush the plane changes */
1766 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
1767 I915_READ(dspbase_reg
);
1770 i915_disable_vga(dev
);
1772 /* disable cpu pipe, disable after all planes disabled */
1773 temp
= I915_READ(pipeconf_reg
);
1774 if ((temp
& PIPEACONF_ENABLE
) != 0) {
1775 I915_WRITE(pipeconf_reg
, temp
& ~PIPEACONF_ENABLE
);
1776 I915_READ(pipeconf_reg
);
1778 /* wait for cpu pipe off, pipe state */
1779 while ((I915_READ(pipeconf_reg
) & I965_PIPECONF_ACTIVE
) != 0) {
1785 DRM_DEBUG_KMS("pipe %d off delay\n",
1791 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
1796 temp
= I915_READ(pf_ctl_reg
);
1797 if ((temp
& PF_ENABLE
) != 0) {
1798 I915_WRITE(pf_ctl_reg
, temp
& ~PF_ENABLE
);
1799 I915_READ(pf_ctl_reg
);
1801 I915_WRITE(pf_win_size
, 0);
1803 /* disable CPU FDI tx and PCH FDI rx */
1804 temp
= I915_READ(fdi_tx_reg
);
1805 I915_WRITE(fdi_tx_reg
, temp
& ~FDI_TX_ENABLE
);
1806 I915_READ(fdi_tx_reg
);
1808 temp
= I915_READ(fdi_rx_reg
);
1809 /* BPC in FDI rx is consistent with that in pipeconf */
1810 temp
&= ~(0x07 << 16);
1811 temp
|= (pipe_bpc
<< 11);
1812 I915_WRITE(fdi_rx_reg
, temp
& ~FDI_RX_ENABLE
);
1813 I915_READ(fdi_rx_reg
);
1817 /* still set train pattern 1 */
1818 temp
= I915_READ(fdi_tx_reg
);
1819 temp
&= ~FDI_LINK_TRAIN_NONE
;
1820 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1821 I915_WRITE(fdi_tx_reg
, temp
);
1823 temp
= I915_READ(fdi_rx_reg
);
1824 temp
&= ~FDI_LINK_TRAIN_NONE
;
1825 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1826 I915_WRITE(fdi_rx_reg
, temp
);
1830 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
1831 temp
= I915_READ(PCH_LVDS
);
1832 I915_WRITE(PCH_LVDS
, temp
& ~LVDS_PORT_EN
);
1833 I915_READ(PCH_LVDS
);
1837 /* disable PCH transcoder */
1838 temp
= I915_READ(transconf_reg
);
1839 if ((temp
& TRANS_ENABLE
) != 0) {
1840 I915_WRITE(transconf_reg
, temp
& ~TRANS_ENABLE
);
1841 I915_READ(transconf_reg
);
1843 /* wait for PCH transcoder off, transcoder state */
1844 while ((I915_READ(transconf_reg
) & TRANS_STATE_ENABLE
) != 0) {
1850 DRM_DEBUG_KMS("transcoder %d off "
1856 temp
= I915_READ(transconf_reg
);
1857 /* BPC in transcoder is consistent with that in pipeconf */
1858 temp
&= ~PIPE_BPC_MASK
;
1860 I915_WRITE(transconf_reg
, temp
);
1861 I915_READ(transconf_reg
);
1864 /* disable PCH DPLL */
1865 temp
= I915_READ(pch_dpll_reg
);
1866 if ((temp
& DPLL_VCO_ENABLE
) != 0) {
1867 I915_WRITE(pch_dpll_reg
, temp
& ~DPLL_VCO_ENABLE
);
1868 I915_READ(pch_dpll_reg
);
1872 ironlake_disable_pll_edp(crtc
);
1875 temp
= I915_READ(fdi_rx_reg
);
1876 temp
&= ~FDI_SEL_PCDCLK
;
1877 I915_WRITE(fdi_rx_reg
, temp
);
1878 I915_READ(fdi_rx_reg
);
1880 temp
= I915_READ(fdi_rx_reg
);
1881 temp
&= ~FDI_RX_PLL_ENABLE
;
1882 I915_WRITE(fdi_rx_reg
, temp
);
1883 I915_READ(fdi_rx_reg
);
1885 /* Disable CPU FDI TX PLL */
1886 temp
= I915_READ(fdi_tx_reg
);
1887 if ((temp
& FDI_TX_PLL_ENABLE
) != 0) {
1888 I915_WRITE(fdi_tx_reg
, temp
& ~FDI_TX_PLL_ENABLE
);
1889 I915_READ(fdi_tx_reg
);
1893 /* Wait for the clocks to turn off. */
1899 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
1901 struct intel_overlay
*overlay
;
1904 if (!enable
&& intel_crtc
->overlay
) {
1905 overlay
= intel_crtc
->overlay
;
1906 mutex_lock(&overlay
->dev
->struct_mutex
);
1908 ret
= intel_overlay_switch_off(overlay
);
1912 ret
= intel_overlay_recover_from_interrupt(overlay
, 0);
1914 /* overlay doesn't react anymore. Usually
1915 * results in a black screen and an unkillable
1918 overlay
->hw_wedged
= HW_WEDGED
;
1922 mutex_unlock(&overlay
->dev
->struct_mutex
);
1924 /* Let userspace switch the overlay on again. In most cases userspace
1925 * has to recompute where to put it anyway. */
1930 static void i9xx_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
1932 struct drm_device
*dev
= crtc
->dev
;
1933 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1934 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1935 int pipe
= intel_crtc
->pipe
;
1936 int plane
= intel_crtc
->plane
;
1937 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
1938 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
1939 int dspbase_reg
= (plane
== 0) ? DSPAADDR
: DSPBADDR
;
1940 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
1943 /* XXX: When our outputs are all unaware of DPMS modes other than off
1944 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1947 case DRM_MODE_DPMS_ON
:
1948 case DRM_MODE_DPMS_STANDBY
:
1949 case DRM_MODE_DPMS_SUSPEND
:
1950 intel_update_watermarks(dev
);
1952 /* Enable the DPLL */
1953 temp
= I915_READ(dpll_reg
);
1954 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
1955 I915_WRITE(dpll_reg
, temp
);
1956 I915_READ(dpll_reg
);
1957 /* Wait for the clocks to stabilize. */
1959 I915_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
1960 I915_READ(dpll_reg
);
1961 /* Wait for the clocks to stabilize. */
1963 I915_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
1964 I915_READ(dpll_reg
);
1965 /* Wait for the clocks to stabilize. */
1969 /* Enable the pipe */
1970 temp
= I915_READ(pipeconf_reg
);
1971 if ((temp
& PIPEACONF_ENABLE
) == 0)
1972 I915_WRITE(pipeconf_reg
, temp
| PIPEACONF_ENABLE
);
1974 /* Enable the plane */
1975 temp
= I915_READ(dspcntr_reg
);
1976 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
1977 I915_WRITE(dspcntr_reg
, temp
| DISPLAY_PLANE_ENABLE
);
1978 /* Flush the plane changes */
1979 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
1982 intel_crtc_load_lut(crtc
);
1984 if ((IS_I965G(dev
) || plane
== 0))
1985 intel_update_fbc(crtc
, &crtc
->mode
);
1987 /* Give the overlay scaler a chance to enable if it's on this pipe */
1988 intel_crtc_dpms_overlay(intel_crtc
, true);
1990 case DRM_MODE_DPMS_OFF
:
1991 intel_update_watermarks(dev
);
1993 /* Give the overlay scaler a chance to disable if it's on this pipe */
1994 intel_crtc_dpms_overlay(intel_crtc
, false);
1995 drm_vblank_off(dev
, pipe
);
1997 if (dev_priv
->cfb_plane
== plane
&&
1998 dev_priv
->display
.disable_fbc
)
1999 dev_priv
->display
.disable_fbc(dev
);
2001 /* Disable the VGA plane that we never use */
2002 i915_disable_vga(dev
);
2004 /* Disable display plane */
2005 temp
= I915_READ(dspcntr_reg
);
2006 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
2007 I915_WRITE(dspcntr_reg
, temp
& ~DISPLAY_PLANE_ENABLE
);
2008 /* Flush the plane changes */
2009 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
2010 I915_READ(dspbase_reg
);
2013 if (!IS_I9XX(dev
)) {
2014 /* Wait for vblank for the disable to take effect */
2015 intel_wait_for_vblank(dev
);
2018 /* Next, disable display pipes */
2019 temp
= I915_READ(pipeconf_reg
);
2020 if ((temp
& PIPEACONF_ENABLE
) != 0) {
2021 I915_WRITE(pipeconf_reg
, temp
& ~PIPEACONF_ENABLE
);
2022 I915_READ(pipeconf_reg
);
2025 /* Wait for vblank for the disable to take effect. */
2026 intel_wait_for_vblank(dev
);
2028 temp
= I915_READ(dpll_reg
);
2029 if ((temp
& DPLL_VCO_ENABLE
) != 0) {
2030 I915_WRITE(dpll_reg
, temp
& ~DPLL_VCO_ENABLE
);
2031 I915_READ(dpll_reg
);
2034 /* Wait for the clocks to turn off. */
2041 * Sets the power management mode of the pipe and plane.
2043 * This code should probably grow support for turning the cursor off and back
2044 * on appropriately at the same time as we're turning the pipe off/on.
2046 static void intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2048 struct drm_device
*dev
= crtc
->dev
;
2049 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2050 struct drm_i915_master_private
*master_priv
;
2051 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2052 int pipe
= intel_crtc
->pipe
;
2055 dev_priv
->display
.dpms(crtc
, mode
);
2057 intel_crtc
->dpms_mode
= mode
;
2059 if (!dev
->primary
->master
)
2062 master_priv
= dev
->primary
->master
->driver_priv
;
2063 if (!master_priv
->sarea_priv
)
2066 enabled
= crtc
->enabled
&& mode
!= DRM_MODE_DPMS_OFF
;
2070 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
2071 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
2074 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
2075 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
2078 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe
);
2083 static void intel_crtc_prepare (struct drm_crtc
*crtc
)
2085 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
2086 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
2089 static void intel_crtc_commit (struct drm_crtc
*crtc
)
2091 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
2092 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
2095 void intel_encoder_prepare (struct drm_encoder
*encoder
)
2097 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
2098 /* lvds has its own version of prepare see intel_lvds_prepare */
2099 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
2102 void intel_encoder_commit (struct drm_encoder
*encoder
)
2104 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
2105 /* lvds has its own version of commit see intel_lvds_commit */
2106 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
2109 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
2110 struct drm_display_mode
*mode
,
2111 struct drm_display_mode
*adjusted_mode
)
2113 struct drm_device
*dev
= crtc
->dev
;
2114 if (IS_IRONLAKE(dev
)) {
2115 /* FDI link clock is fixed at 2.7G */
2116 if (mode
->clock
* 3 > 27000 * 4)
2117 return MODE_CLOCK_HIGH
;
2122 static int i945_get_display_clock_speed(struct drm_device
*dev
)
2127 static int i915_get_display_clock_speed(struct drm_device
*dev
)
2132 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
2137 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
2141 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
2143 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
2146 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
2147 case GC_DISPLAY_CLOCK_333_MHZ
:
2150 case GC_DISPLAY_CLOCK_190_200_MHZ
:
2156 static int i865_get_display_clock_speed(struct drm_device
*dev
)
2161 static int i855_get_display_clock_speed(struct drm_device
*dev
)
2164 /* Assume that the hardware is in the high speed state. This
2165 * should be the default.
2167 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
2168 case GC_CLOCK_133_200
:
2169 case GC_CLOCK_100_200
:
2171 case GC_CLOCK_166_250
:
2173 case GC_CLOCK_100_133
:
2177 /* Shouldn't happen */
2181 static int i830_get_display_clock_speed(struct drm_device
*dev
)
2187 * Return the pipe currently connected to the panel fitter,
2188 * or -1 if the panel fitter is not present or not in use
2190 int intel_panel_fitter_pipe (struct drm_device
*dev
)
2192 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2195 /* i830 doesn't have a panel fitter */
2199 pfit_control
= I915_READ(PFIT_CONTROL
);
2201 /* See if the panel fitter is in use */
2202 if ((pfit_control
& PFIT_ENABLE
) == 0)
2205 /* 965 can place panel fitter on either pipe */
2207 return (pfit_control
>> 29) & 0x3;
2209 /* older chips can only use pipe 1 */
2222 fdi_reduce_ratio(u32
*num
, u32
*den
)
2224 while (*num
> 0xffffff || *den
> 0xffffff) {
2230 #define DATA_N 0x800000
2231 #define LINK_N 0x80000
2234 ironlake_compute_m_n(int bits_per_pixel
, int nlanes
, int pixel_clock
,
2235 int link_clock
, struct fdi_m_n
*m_n
)
2239 m_n
->tu
= 64; /* default size */
2241 temp
= (u64
) DATA_N
* pixel_clock
;
2242 temp
= div_u64(temp
, link_clock
);
2243 m_n
->gmch_m
= div_u64(temp
* bits_per_pixel
, nlanes
);
2244 m_n
->gmch_m
>>= 3; /* convert to bytes_per_pixel */
2245 m_n
->gmch_n
= DATA_N
;
2246 fdi_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
2248 temp
= (u64
) LINK_N
* pixel_clock
;
2249 m_n
->link_m
= div_u64(temp
, link_clock
);
2250 m_n
->link_n
= LINK_N
;
2251 fdi_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
2255 struct intel_watermark_params
{
2256 unsigned long fifo_size
;
2257 unsigned long max_wm
;
2258 unsigned long default_wm
;
2259 unsigned long guard_size
;
2260 unsigned long cacheline_size
;
2263 /* Pineview has different values for various configs */
2264 static struct intel_watermark_params pineview_display_wm
= {
2265 PINEVIEW_DISPLAY_FIFO
,
2269 PINEVIEW_FIFO_LINE_SIZE
2271 static struct intel_watermark_params pineview_display_hplloff_wm
= {
2272 PINEVIEW_DISPLAY_FIFO
,
2274 PINEVIEW_DFT_HPLLOFF_WM
,
2276 PINEVIEW_FIFO_LINE_SIZE
2278 static struct intel_watermark_params pineview_cursor_wm
= {
2279 PINEVIEW_CURSOR_FIFO
,
2280 PINEVIEW_CURSOR_MAX_WM
,
2281 PINEVIEW_CURSOR_DFT_WM
,
2282 PINEVIEW_CURSOR_GUARD_WM
,
2283 PINEVIEW_FIFO_LINE_SIZE
,
2285 static struct intel_watermark_params pineview_cursor_hplloff_wm
= {
2286 PINEVIEW_CURSOR_FIFO
,
2287 PINEVIEW_CURSOR_MAX_WM
,
2288 PINEVIEW_CURSOR_DFT_WM
,
2289 PINEVIEW_CURSOR_GUARD_WM
,
2290 PINEVIEW_FIFO_LINE_SIZE
2292 static struct intel_watermark_params g4x_wm_info
= {
2299 static struct intel_watermark_params i945_wm_info
= {
2306 static struct intel_watermark_params i915_wm_info
= {
2313 static struct intel_watermark_params i855_wm_info
= {
2320 static struct intel_watermark_params i830_wm_info
= {
2329 * intel_calculate_wm - calculate watermark level
2330 * @clock_in_khz: pixel clock
2331 * @wm: chip FIFO params
2332 * @pixel_size: display pixel size
2333 * @latency_ns: memory latency for the platform
2335 * Calculate the watermark level (the level at which the display plane will
2336 * start fetching from memory again). Each chip has a different display
2337 * FIFO size and allocation, so the caller needs to figure that out and pass
2338 * in the correct intel_watermark_params structure.
2340 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2341 * on the pixel size. When it reaches the watermark level, it'll start
2342 * fetching FIFO line sized based chunks from memory until the FIFO fills
2343 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2344 * will occur, and a display engine hang could result.
2346 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
2347 struct intel_watermark_params
*wm
,
2349 unsigned long latency_ns
)
2351 long entries_required
, wm_size
;
2354 * Note: we need to make sure we don't overflow for various clock &
2356 * clocks go from a few thousand to several hundred thousand.
2357 * latency is usually a few thousand
2359 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
2361 entries_required
/= wm
->cacheline_size
;
2363 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required
);
2365 wm_size
= wm
->fifo_size
- (entries_required
+ wm
->guard_size
);
2367 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size
);
2369 /* Don't promote wm_size to unsigned... */
2370 if (wm_size
> (long)wm
->max_wm
)
2371 wm_size
= wm
->max_wm
;
2373 wm_size
= wm
->default_wm
;
2377 struct cxsr_latency
{
2379 unsigned long fsb_freq
;
2380 unsigned long mem_freq
;
2381 unsigned long display_sr
;
2382 unsigned long display_hpll_disable
;
2383 unsigned long cursor_sr
;
2384 unsigned long cursor_hpll_disable
;
2387 static struct cxsr_latency cxsr_latency_table
[] = {
2388 {1, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2389 {1, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2390 {1, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2392 {1, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2393 {1, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2394 {1, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2396 {1, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2397 {1, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2398 {1, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2400 {0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2401 {0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2402 {0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2404 {0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2405 {0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2406 {0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2408 {0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2409 {0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2410 {0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2413 static struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
, int fsb
,
2417 struct cxsr_latency
*latency
;
2419 if (fsb
== 0 || mem
== 0)
2422 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
2423 latency
= &cxsr_latency_table
[i
];
2424 if (is_desktop
== latency
->is_desktop
&&
2425 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
2429 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2434 static void pineview_disable_cxsr(struct drm_device
*dev
)
2436 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2439 /* deactivate cxsr */
2440 reg
= I915_READ(DSPFW3
);
2441 reg
&= ~(PINEVIEW_SELF_REFRESH_EN
);
2442 I915_WRITE(DSPFW3
, reg
);
2443 DRM_INFO("Big FIFO is disabled\n");
2446 static void pineview_enable_cxsr(struct drm_device
*dev
, unsigned long clock
,
2449 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2452 struct cxsr_latency
*latency
;
2454 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->fsb_freq
,
2455 dev_priv
->mem_freq
);
2457 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2458 pineview_disable_cxsr(dev
);
2463 wm
= intel_calculate_wm(clock
, &pineview_display_wm
, pixel_size
,
2464 latency
->display_sr
);
2465 reg
= I915_READ(DSPFW1
);
2468 I915_WRITE(DSPFW1
, reg
);
2469 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
2472 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
, pixel_size
,
2473 latency
->cursor_sr
);
2474 reg
= I915_READ(DSPFW3
);
2475 reg
&= ~(0x3f << 24);
2476 reg
|= (wm
& 0x3f) << 24;
2477 I915_WRITE(DSPFW3
, reg
);
2479 /* Display HPLL off SR */
2480 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
2481 latency
->display_hpll_disable
, I915_FIFO_LINE_SIZE
);
2482 reg
= I915_READ(DSPFW3
);
2485 I915_WRITE(DSPFW3
, reg
);
2487 /* cursor HPLL off SR */
2488 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
, pixel_size
,
2489 latency
->cursor_hpll_disable
);
2490 reg
= I915_READ(DSPFW3
);
2491 reg
&= ~(0x3f << 16);
2492 reg
|= (wm
& 0x3f) << 16;
2493 I915_WRITE(DSPFW3
, reg
);
2494 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
2497 reg
= I915_READ(DSPFW3
);
2498 reg
|= PINEVIEW_SELF_REFRESH_EN
;
2499 I915_WRITE(DSPFW3
, reg
);
2501 DRM_INFO("Big FIFO is enabled\n");
2507 * Latency for FIFO fetches is dependent on several factors:
2508 * - memory configuration (speed, channels)
2510 * - current MCH state
2511 * It can be fairly high in some situations, so here we assume a fairly
2512 * pessimal value. It's a tradeoff between extra memory fetches (if we
2513 * set this value too high, the FIFO will fetch frequently to stay full)
2514 * and power consumption (set it too low to save power and we might see
2515 * FIFO underruns and display "flicker").
2517 * A value of 5us seems to be a good balance; safe for very low end
2518 * platforms but not overly aggressive on lower latency configs.
2520 static const int latency_ns
= 5000;
2522 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
2524 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2525 uint32_t dsparb
= I915_READ(DSPARB
);
2529 size
= dsparb
& 0x7f;
2531 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) -
2534 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2535 plane
? "B" : "A", size
);
2540 static int i85x_get_fifo_size(struct drm_device
*dev
, int plane
)
2542 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2543 uint32_t dsparb
= I915_READ(DSPARB
);
2547 size
= dsparb
& 0x1ff;
2549 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) -
2551 size
>>= 1; /* Convert to cachelines */
2553 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2554 plane
? "B" : "A", size
);
2559 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
2561 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2562 uint32_t dsparb
= I915_READ(DSPARB
);
2565 size
= dsparb
& 0x7f;
2566 size
>>= 2; /* Convert to cachelines */
2568 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2575 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
2577 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2578 uint32_t dsparb
= I915_READ(DSPARB
);
2581 size
= dsparb
& 0x7f;
2582 size
>>= 1; /* Convert to cachelines */
2584 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2585 plane
? "B" : "A", size
);
2590 static void g4x_update_wm(struct drm_device
*dev
, int planea_clock
,
2591 int planeb_clock
, int sr_hdisplay
, int pixel_size
)
2593 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2594 int total_size
, cacheline_size
;
2595 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
, cursor_sr
;
2596 struct intel_watermark_params planea_params
, planeb_params
;
2597 unsigned long line_time_us
;
2598 int sr_clock
, sr_entries
= 0, entries_required
;
2600 /* Create copies of the base settings for each pipe */
2601 planea_params
= planeb_params
= g4x_wm_info
;
2603 /* Grab a couple of global values before we overwrite them */
2604 total_size
= planea_params
.fifo_size
;
2605 cacheline_size
= planea_params
.cacheline_size
;
2608 * Note: we need to make sure we don't overflow for various clock &
2610 * clocks go from a few thousand to several hundred thousand.
2611 * latency is usually a few thousand
2613 entries_required
= ((planea_clock
/ 1000) * pixel_size
* latency_ns
) /
2615 entries_required
/= G4X_FIFO_LINE_SIZE
;
2616 planea_wm
= entries_required
+ planea_params
.guard_size
;
2618 entries_required
= ((planeb_clock
/ 1000) * pixel_size
* latency_ns
) /
2620 entries_required
/= G4X_FIFO_LINE_SIZE
;
2621 planeb_wm
= entries_required
+ planeb_params
.guard_size
;
2623 cursora_wm
= cursorb_wm
= 16;
2626 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
2628 /* Calc sr entries for one plane configs */
2629 if (sr_hdisplay
&& (!planea_clock
|| !planeb_clock
)) {
2630 /* self-refresh has much higher latency */
2631 static const int sr_latency_ns
= 12000;
2633 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
2634 line_time_us
= ((sr_hdisplay
* 1000) / sr_clock
);
2636 /* Use ns/us then divide to preserve precision */
2637 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1) *
2638 pixel_size
* sr_hdisplay
) / 1000;
2639 sr_entries
= roundup(sr_entries
/ cacheline_size
, 1);
2640 DRM_DEBUG("self-refresh entries: %d\n", sr_entries
);
2641 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
2643 /* Turn off self refresh if both pipes are enabled */
2644 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
2648 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2649 planea_wm
, planeb_wm
, sr_entries
);
2654 I915_WRITE(DSPFW1
, (sr_entries
<< DSPFW_SR_SHIFT
) |
2655 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
2656 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) | planea_wm
);
2657 I915_WRITE(DSPFW2
, (I915_READ(DSPFW2
) & DSPFW_CURSORA_MASK
) |
2658 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
2659 /* HPLL off in SR has some issues on G4x... disable it */
2660 I915_WRITE(DSPFW3
, (I915_READ(DSPFW3
) & ~DSPFW_HPLL_SR_EN
) |
2661 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
2664 static void i965_update_wm(struct drm_device
*dev
, int planea_clock
,
2665 int planeb_clock
, int sr_hdisplay
, int pixel_size
)
2667 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2668 unsigned long line_time_us
;
2669 int sr_clock
, sr_entries
, srwm
= 1;
2671 /* Calc sr entries for one plane configs */
2672 if (sr_hdisplay
&& (!planea_clock
|| !planeb_clock
)) {
2673 /* self-refresh has much higher latency */
2674 static const int sr_latency_ns
= 12000;
2676 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
2677 line_time_us
= ((sr_hdisplay
* 1000) / sr_clock
);
2679 /* Use ns/us then divide to preserve precision */
2680 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1) *
2681 pixel_size
* sr_hdisplay
) / 1000;
2682 sr_entries
= roundup(sr_entries
/ I915_FIFO_LINE_SIZE
, 1);
2683 DRM_DEBUG("self-refresh entries: %d\n", sr_entries
);
2684 srwm
= I945_FIFO_SIZE
- sr_entries
;
2688 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
2690 /* Turn off self refresh if both pipes are enabled */
2691 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
2695 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2698 /* 965 has limitations... */
2699 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) | (8 << 16) | (8 << 8) |
2701 I915_WRITE(DSPFW2
, (8 << 8) | (8 << 0));
2704 static void i9xx_update_wm(struct drm_device
*dev
, int planea_clock
,
2705 int planeb_clock
, int sr_hdisplay
, int pixel_size
)
2707 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2710 int total_size
, cacheline_size
, cwm
, srwm
= 1;
2711 int planea_wm
, planeb_wm
;
2712 struct intel_watermark_params planea_params
, planeb_params
;
2713 unsigned long line_time_us
;
2714 int sr_clock
, sr_entries
= 0;
2716 /* Create copies of the base settings for each pipe */
2717 if (IS_I965GM(dev
) || IS_I945GM(dev
))
2718 planea_params
= planeb_params
= i945_wm_info
;
2719 else if (IS_I9XX(dev
))
2720 planea_params
= planeb_params
= i915_wm_info
;
2722 planea_params
= planeb_params
= i855_wm_info
;
2724 /* Grab a couple of global values before we overwrite them */
2725 total_size
= planea_params
.fifo_size
;
2726 cacheline_size
= planea_params
.cacheline_size
;
2728 /* Update per-plane FIFO sizes */
2729 planea_params
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
2730 planeb_params
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
2732 planea_wm
= intel_calculate_wm(planea_clock
, &planea_params
,
2733 pixel_size
, latency_ns
);
2734 planeb_wm
= intel_calculate_wm(planeb_clock
, &planeb_params
,
2735 pixel_size
, latency_ns
);
2736 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
2739 * Overlay gets an aggressive default since video jitter is bad.
2743 /* Calc sr entries for one plane configs */
2744 if (HAS_FW_BLC(dev
) && sr_hdisplay
&&
2745 (!planea_clock
|| !planeb_clock
)) {
2746 /* self-refresh has much higher latency */
2747 static const int sr_latency_ns
= 6000;
2749 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
2750 line_time_us
= ((sr_hdisplay
* 1000) / sr_clock
);
2752 /* Use ns/us then divide to preserve precision */
2753 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1) *
2754 pixel_size
* sr_hdisplay
) / 1000;
2755 sr_entries
= roundup(sr_entries
/ cacheline_size
, 1);
2756 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries
);
2757 srwm
= total_size
- sr_entries
;
2760 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
| (srwm
& 0x3f));
2762 /* Turn off self refresh if both pipes are enabled */
2763 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
2767 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2768 planea_wm
, planeb_wm
, cwm
, srwm
);
2770 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
2771 fwater_hi
= (cwm
& 0x1f);
2773 /* Set request length to 8 cachelines per fetch */
2774 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
2775 fwater_hi
= fwater_hi
| (1 << 8);
2777 I915_WRITE(FW_BLC
, fwater_lo
);
2778 I915_WRITE(FW_BLC2
, fwater_hi
);
2781 static void i830_update_wm(struct drm_device
*dev
, int planea_clock
, int unused
,
2782 int unused2
, int pixel_size
)
2784 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2785 uint32_t fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
2788 i830_wm_info
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
2790 planea_wm
= intel_calculate_wm(planea_clock
, &i830_wm_info
,
2791 pixel_size
, latency_ns
);
2792 fwater_lo
|= (3<<8) | planea_wm
;
2794 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
2796 I915_WRITE(FW_BLC
, fwater_lo
);
2800 * intel_update_watermarks - update FIFO watermark values based on current modes
2802 * Calculate watermark values for the various WM regs based on current mode
2803 * and plane configuration.
2805 * There are several cases to deal with here:
2806 * - normal (i.e. non-self-refresh)
2807 * - self-refresh (SR) mode
2808 * - lines are large relative to FIFO size (buffer can hold up to 2)
2809 * - lines are small relative to FIFO size (buffer can hold more than 2
2810 * lines), so need to account for TLB latency
2812 * The normal calculation is:
2813 * watermark = dotclock * bytes per pixel * latency
2814 * where latency is platform & configuration dependent (we assume pessimal
2817 * The SR calculation is:
2818 * watermark = (trunc(latency/line time)+1) * surface width *
2821 * line time = htotal / dotclock
2822 * and latency is assumed to be high, as above.
2824 * The final value programmed to the register should always be rounded up,
2825 * and include an extra 2 entries to account for clock crossings.
2827 * We don't use the sprite, so we can ignore that. And on Crestline we have
2828 * to set the non-SR watermarks to 8.
2830 static void intel_update_watermarks(struct drm_device
*dev
)
2832 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2833 struct drm_crtc
*crtc
;
2834 struct intel_crtc
*intel_crtc
;
2835 int sr_hdisplay
= 0;
2836 unsigned long planea_clock
= 0, planeb_clock
= 0, sr_clock
= 0;
2837 int enabled
= 0, pixel_size
= 0;
2839 if (!dev_priv
->display
.update_wm
)
2842 /* Get the clock config from both planes */
2843 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2844 intel_crtc
= to_intel_crtc(crtc
);
2845 if (crtc
->enabled
) {
2847 if (intel_crtc
->plane
== 0) {
2848 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
2849 intel_crtc
->pipe
, crtc
->mode
.clock
);
2850 planea_clock
= crtc
->mode
.clock
;
2852 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
2853 intel_crtc
->pipe
, crtc
->mode
.clock
);
2854 planeb_clock
= crtc
->mode
.clock
;
2856 sr_hdisplay
= crtc
->mode
.hdisplay
;
2857 sr_clock
= crtc
->mode
.clock
;
2859 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
2861 pixel_size
= 4; /* by default */
2868 /* Single plane configs can enable self refresh */
2869 if (enabled
== 1 && IS_PINEVIEW(dev
))
2870 pineview_enable_cxsr(dev
, sr_clock
, pixel_size
);
2871 else if (IS_PINEVIEW(dev
))
2872 pineview_disable_cxsr(dev
);
2874 dev_priv
->display
.update_wm(dev
, planea_clock
, planeb_clock
,
2875 sr_hdisplay
, pixel_size
);
2878 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
2879 struct drm_display_mode
*mode
,
2880 struct drm_display_mode
*adjusted_mode
,
2882 struct drm_framebuffer
*old_fb
)
2884 struct drm_device
*dev
= crtc
->dev
;
2885 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2886 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2887 int pipe
= intel_crtc
->pipe
;
2888 int plane
= intel_crtc
->plane
;
2889 int fp_reg
= (pipe
== 0) ? FPA0
: FPB0
;
2890 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
2891 int dpll_md_reg
= (intel_crtc
->pipe
== 0) ? DPLL_A_MD
: DPLL_B_MD
;
2892 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
2893 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
2894 int htot_reg
= (pipe
== 0) ? HTOTAL_A
: HTOTAL_B
;
2895 int hblank_reg
= (pipe
== 0) ? HBLANK_A
: HBLANK_B
;
2896 int hsync_reg
= (pipe
== 0) ? HSYNC_A
: HSYNC_B
;
2897 int vtot_reg
= (pipe
== 0) ? VTOTAL_A
: VTOTAL_B
;
2898 int vblank_reg
= (pipe
== 0) ? VBLANK_A
: VBLANK_B
;
2899 int vsync_reg
= (pipe
== 0) ? VSYNC_A
: VSYNC_B
;
2900 int dspsize_reg
= (plane
== 0) ? DSPASIZE
: DSPBSIZE
;
2901 int dsppos_reg
= (plane
== 0) ? DSPAPOS
: DSPBPOS
;
2902 int pipesrc_reg
= (pipe
== 0) ? PIPEASRC
: PIPEBSRC
;
2903 int refclk
, num_outputs
= 0;
2904 intel_clock_t clock
, reduced_clock
;
2905 u32 dpll
= 0, fp
= 0, fp2
= 0, dspcntr
, pipeconf
;
2906 bool ok
, has_reduced_clock
= false, is_sdvo
= false, is_dvo
= false;
2907 bool is_crt
= false, is_lvds
= false, is_tv
= false, is_dp
= false;
2908 bool is_edp
= false;
2909 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2910 struct drm_connector
*connector
;
2911 const intel_limit_t
*limit
;
2913 struct fdi_m_n m_n
= {0};
2914 int data_m1_reg
= (pipe
== 0) ? PIPEA_DATA_M1
: PIPEB_DATA_M1
;
2915 int data_n1_reg
= (pipe
== 0) ? PIPEA_DATA_N1
: PIPEB_DATA_N1
;
2916 int link_m1_reg
= (pipe
== 0) ? PIPEA_LINK_M1
: PIPEB_LINK_M1
;
2917 int link_n1_reg
= (pipe
== 0) ? PIPEA_LINK_N1
: PIPEB_LINK_N1
;
2918 int pch_fp_reg
= (pipe
== 0) ? PCH_FPA0
: PCH_FPB0
;
2919 int pch_dpll_reg
= (pipe
== 0) ? PCH_DPLL_A
: PCH_DPLL_B
;
2920 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
2921 int lvds_reg
= LVDS
;
2923 int sdvo_pixel_multiply
;
2926 drm_vblank_pre_modeset(dev
, pipe
);
2928 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
2929 struct intel_output
*intel_output
= to_intel_output(connector
);
2931 if (!connector
->encoder
|| connector
->encoder
->crtc
!= crtc
)
2934 switch (intel_output
->type
) {
2935 case INTEL_OUTPUT_LVDS
:
2938 case INTEL_OUTPUT_SDVO
:
2939 case INTEL_OUTPUT_HDMI
:
2941 if (intel_output
->needs_tv_clock
)
2944 case INTEL_OUTPUT_DVO
:
2947 case INTEL_OUTPUT_TVOUT
:
2950 case INTEL_OUTPUT_ANALOG
:
2953 case INTEL_OUTPUT_DISPLAYPORT
:
2956 case INTEL_OUTPUT_EDP
:
2964 if (is_lvds
&& dev_priv
->lvds_use_ssc
&& num_outputs
< 2) {
2965 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
2966 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
2968 } else if (IS_I9XX(dev
)) {
2970 if (IS_IRONLAKE(dev
))
2971 refclk
= 120000; /* 120Mhz refclk */
2978 * Returns a set of divisors for the desired target clock with the given
2979 * refclk, or FALSE. The returned values represent the clock equation:
2980 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2982 limit
= intel_limit(crtc
);
2983 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, &clock
);
2985 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2986 drm_vblank_post_modeset(dev
, pipe
);
2990 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
2991 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
2992 dev_priv
->lvds_downclock
,
2995 if (has_reduced_clock
&& (clock
.p
!= reduced_clock
.p
)) {
2997 * If the different P is found, it means that we can't
2998 * switch the display clock by using the FP0/FP1.
2999 * In such case we will disable the LVDS downclock
3002 DRM_DEBUG_KMS("Different P is found for "
3003 "LVDS clock/downclock\n");
3004 has_reduced_clock
= 0;
3007 /* SDVO TV has fixed PLL values depend on its clock range,
3008 this mirrors vbios setting. */
3009 if (is_sdvo
&& is_tv
) {
3010 if (adjusted_mode
->clock
>= 100000
3011 && adjusted_mode
->clock
< 140500) {
3017 } else if (adjusted_mode
->clock
>= 140500
3018 && adjusted_mode
->clock
<= 200000) {
3028 if (IS_IRONLAKE(dev
)) {
3029 int lane
, link_bw
, bpp
;
3030 /* eDP doesn't require FDI link, so just set DP M/N
3031 according to current link config */
3033 struct drm_connector
*edp
;
3034 target_clock
= mode
->clock
;
3035 edp
= intel_pipe_get_output(crtc
);
3036 intel_edp_link_config(to_intel_output(edp
),
3039 /* DP over FDI requires target mode clock
3040 instead of link clock */
3042 target_clock
= mode
->clock
;
3044 target_clock
= adjusted_mode
->clock
;
3049 /* determine panel color depth */
3050 temp
= I915_READ(pipeconf_reg
);
3051 temp
&= ~PIPE_BPC_MASK
;
3053 int lvds_reg
= I915_READ(PCH_LVDS
);
3054 /* the BPC will be 6 if it is 18-bit LVDS panel */
3055 if ((lvds_reg
& LVDS_A3_POWER_MASK
) == LVDS_A3_POWER_UP
)
3059 } else if (is_edp
) {
3060 switch (dev_priv
->edp_bpp
/3) {
3076 I915_WRITE(pipeconf_reg
, temp
);
3077 I915_READ(pipeconf_reg
);
3079 switch (temp
& PIPE_BPC_MASK
) {
3093 DRM_ERROR("unknown pipe bpc value\n");
3097 ironlake_compute_m_n(bpp
, lane
, target_clock
, link_bw
, &m_n
);
3100 /* Ironlake: try to setup display ref clock before DPLL
3101 * enabling. This is only under driver's control after
3102 * PCH B stepping, previous chipset stepping should be
3103 * ignoring this setting.
3105 if (IS_IRONLAKE(dev
)) {
3106 temp
= I915_READ(PCH_DREF_CONTROL
);
3107 /* Always enable nonspread source */
3108 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
3109 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
3110 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3111 POSTING_READ(PCH_DREF_CONTROL
);
3113 temp
&= ~DREF_SSC_SOURCE_MASK
;
3114 temp
|= DREF_SSC_SOURCE_ENABLE
;
3115 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3116 POSTING_READ(PCH_DREF_CONTROL
);
3121 if (dev_priv
->lvds_use_ssc
) {
3122 temp
|= DREF_SSC1_ENABLE
;
3123 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3124 POSTING_READ(PCH_DREF_CONTROL
);
3128 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
3129 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
3130 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3131 POSTING_READ(PCH_DREF_CONTROL
);
3133 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
3134 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3135 POSTING_READ(PCH_DREF_CONTROL
);
3140 if (IS_PINEVIEW(dev
)) {
3141 fp
= (1 << clock
.n
) << 16 | clock
.m1
<< 8 | clock
.m2
;
3142 if (has_reduced_clock
)
3143 fp2
= (1 << reduced_clock
.n
) << 16 |
3144 reduced_clock
.m1
<< 8 | reduced_clock
.m2
;
3146 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
3147 if (has_reduced_clock
)
3148 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
3152 if (!IS_IRONLAKE(dev
))
3153 dpll
= DPLL_VGA_MODE_DIS
;
3157 dpll
|= DPLLB_MODE_LVDS
;
3159 dpll
|= DPLLB_MODE_DAC_SERIAL
;
3161 dpll
|= DPLL_DVO_HIGH_SPEED
;
3162 sdvo_pixel_multiply
= adjusted_mode
->clock
/ mode
->clock
;
3163 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
3164 dpll
|= (sdvo_pixel_multiply
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
3165 else if (IS_IRONLAKE(dev
))
3166 dpll
|= (sdvo_pixel_multiply
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
3169 dpll
|= DPLL_DVO_HIGH_SPEED
;
3171 /* compute bitmask from p1 value */
3172 if (IS_PINEVIEW(dev
))
3173 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
3175 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3177 if (IS_IRONLAKE(dev
))
3178 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
3179 if (IS_G4X(dev
) && has_reduced_clock
)
3180 dpll
|= (1 << (reduced_clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
3184 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
3187 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
3190 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
3193 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
3196 if (IS_I965G(dev
) && !IS_IRONLAKE(dev
))
3197 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
3200 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3203 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
3205 dpll
|= (clock
.p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3207 dpll
|= PLL_P2_DIVIDE_BY_4
;
3211 if (is_sdvo
&& is_tv
)
3212 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
3214 /* XXX: just matching BIOS for now */
3215 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3217 else if (is_lvds
&& dev_priv
->lvds_use_ssc
&& num_outputs
< 2)
3218 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
3220 dpll
|= PLL_REF_INPUT_DREFCLK
;
3222 /* setup pipeconf */
3223 pipeconf
= I915_READ(pipeconf_reg
);
3225 /* Set up the display plane register */
3226 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
3228 /* Ironlake's plane is forced to pipe, bit 24 is to
3229 enable color space conversion */
3230 if (!IS_IRONLAKE(dev
)) {
3232 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
3234 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
3237 if (pipe
== 0 && !IS_I965G(dev
)) {
3238 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3241 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3245 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
3246 pipeconf
|= PIPEACONF_DOUBLE_WIDE
;
3248 pipeconf
&= ~PIPEACONF_DOUBLE_WIDE
;
3251 dspcntr
|= DISPLAY_PLANE_ENABLE
;
3252 pipeconf
|= PIPEACONF_ENABLE
;
3253 dpll
|= DPLL_VCO_ENABLE
;
3256 /* Disable the panel fitter if it was on our pipe */
3257 if (!IS_IRONLAKE(dev
) && intel_panel_fitter_pipe(dev
) == pipe
)
3258 I915_WRITE(PFIT_CONTROL
, 0);
3260 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
3261 drm_mode_debug_printmodeline(mode
);
3263 /* assign to Ironlake registers */
3264 if (IS_IRONLAKE(dev
)) {
3265 fp_reg
= pch_fp_reg
;
3266 dpll_reg
= pch_dpll_reg
;
3270 ironlake_disable_pll_edp(crtc
);
3271 } else if ((dpll
& DPLL_VCO_ENABLE
)) {
3272 I915_WRITE(fp_reg
, fp
);
3273 I915_WRITE(dpll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3274 I915_READ(dpll_reg
);
3278 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3279 * This is an exception to the general rule that mode_set doesn't turn
3285 if (IS_IRONLAKE(dev
))
3286 lvds_reg
= PCH_LVDS
;
3288 lvds
= I915_READ(lvds_reg
);
3289 lvds
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
| LVDS_PIPEB_SELECT
;
3290 /* set the corresponsding LVDS_BORDER bit */
3291 lvds
|= dev_priv
->lvds_border_bits
;
3292 /* Set the B0-B3 data pairs corresponding to whether we're going to
3293 * set the DPLLs for dual-channel mode or not.
3296 lvds
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
3298 lvds
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
3300 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3301 * appropriately here, but we need to look more thoroughly into how
3302 * panels behave in the two modes.
3304 /* set the dithering flag */
3305 if (IS_I965G(dev
)) {
3306 if (dev_priv
->lvds_dither
) {
3307 if (IS_IRONLAKE(dev
))
3308 pipeconf
|= PIPE_ENABLE_DITHER
;
3310 lvds
|= LVDS_ENABLE_DITHER
;
3312 if (IS_IRONLAKE(dev
))
3313 pipeconf
&= ~PIPE_ENABLE_DITHER
;
3315 lvds
&= ~LVDS_ENABLE_DITHER
;
3318 I915_WRITE(lvds_reg
, lvds
);
3319 I915_READ(lvds_reg
);
3322 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
3325 I915_WRITE(fp_reg
, fp
);
3326 I915_WRITE(dpll_reg
, dpll
);
3327 I915_READ(dpll_reg
);
3328 /* Wait for the clocks to stabilize. */
3331 if (IS_I965G(dev
) && !IS_IRONLAKE(dev
)) {
3333 sdvo_pixel_multiply
= adjusted_mode
->clock
/ mode
->clock
;
3334 I915_WRITE(dpll_md_reg
, (0 << DPLL_MD_UDI_DIVIDER_SHIFT
) |
3335 ((sdvo_pixel_multiply
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
));
3337 I915_WRITE(dpll_md_reg
, 0);
3339 /* write it again -- the BIOS does, after all */
3340 I915_WRITE(dpll_reg
, dpll
);
3342 I915_READ(dpll_reg
);
3343 /* Wait for the clocks to stabilize. */
3347 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
3348 I915_WRITE(fp_reg
+ 4, fp2
);
3349 intel_crtc
->lowfreq_avail
= true;
3350 if (HAS_PIPE_CXSR(dev
)) {
3351 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3352 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
3355 I915_WRITE(fp_reg
+ 4, fp
);
3356 intel_crtc
->lowfreq_avail
= false;
3357 if (HAS_PIPE_CXSR(dev
)) {
3358 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3359 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
3363 I915_WRITE(htot_reg
, (adjusted_mode
->crtc_hdisplay
- 1) |
3364 ((adjusted_mode
->crtc_htotal
- 1) << 16));
3365 I915_WRITE(hblank_reg
, (adjusted_mode
->crtc_hblank_start
- 1) |
3366 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
3367 I915_WRITE(hsync_reg
, (adjusted_mode
->crtc_hsync_start
- 1) |
3368 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
3369 I915_WRITE(vtot_reg
, (adjusted_mode
->crtc_vdisplay
- 1) |
3370 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
3371 I915_WRITE(vblank_reg
, (adjusted_mode
->crtc_vblank_start
- 1) |
3372 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
3373 I915_WRITE(vsync_reg
, (adjusted_mode
->crtc_vsync_start
- 1) |
3374 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
3375 /* pipesrc and dspsize control the size that is scaled from, which should
3376 * always be the user's requested size.
3378 if (!IS_IRONLAKE(dev
)) {
3379 I915_WRITE(dspsize_reg
, ((mode
->vdisplay
- 1) << 16) |
3380 (mode
->hdisplay
- 1));
3381 I915_WRITE(dsppos_reg
, 0);
3383 I915_WRITE(pipesrc_reg
, ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
3385 if (IS_IRONLAKE(dev
)) {
3386 I915_WRITE(data_m1_reg
, TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
3387 I915_WRITE(data_n1_reg
, TU_SIZE(m_n
.tu
) | m_n
.gmch_n
);
3388 I915_WRITE(link_m1_reg
, m_n
.link_m
);
3389 I915_WRITE(link_n1_reg
, m_n
.link_n
);
3392 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
3394 /* enable FDI RX PLL too */
3395 temp
= I915_READ(fdi_rx_reg
);
3396 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_PLL_ENABLE
);
3401 I915_WRITE(pipeconf_reg
, pipeconf
);
3402 I915_READ(pipeconf_reg
);
3404 intel_wait_for_vblank(dev
);
3406 if (IS_IRONLAKE(dev
)) {
3407 /* enable address swizzle for tiling buffer */
3408 temp
= I915_READ(DISP_ARB_CTL
);
3409 I915_WRITE(DISP_ARB_CTL
, temp
| DISP_TILE_SURFACE_SWIZZLING
);
3412 I915_WRITE(dspcntr_reg
, dspcntr
);
3414 /* Flush the plane changes */
3415 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
3417 if ((IS_I965G(dev
) || plane
== 0))
3418 intel_update_fbc(crtc
, &crtc
->mode
);
3420 intel_update_watermarks(dev
);
3422 drm_vblank_post_modeset(dev
, pipe
);
3427 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3428 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
3430 struct drm_device
*dev
= crtc
->dev
;
3431 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3432 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3433 int palreg
= (intel_crtc
->pipe
== 0) ? PALETTE_A
: PALETTE_B
;
3436 /* The clocks have to be on to load the palette. */
3440 /* use legacy palette for Ironlake */
3441 if (IS_IRONLAKE(dev
))
3442 palreg
= (intel_crtc
->pipe
== 0) ? LGC_PALETTE_A
:
3445 for (i
= 0; i
< 256; i
++) {
3446 I915_WRITE(palreg
+ 4 * i
,
3447 (intel_crtc
->lut_r
[i
] << 16) |
3448 (intel_crtc
->lut_g
[i
] << 8) |
3449 intel_crtc
->lut_b
[i
]);
3453 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
3454 struct drm_file
*file_priv
,
3456 uint32_t width
, uint32_t height
)
3458 struct drm_device
*dev
= crtc
->dev
;
3459 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3460 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3461 struct drm_gem_object
*bo
;
3462 struct drm_i915_gem_object
*obj_priv
;
3463 int pipe
= intel_crtc
->pipe
;
3464 uint32_t control
= (pipe
== 0) ? CURACNTR
: CURBCNTR
;
3465 uint32_t base
= (pipe
== 0) ? CURABASE
: CURBBASE
;
3466 uint32_t temp
= I915_READ(control
);
3470 DRM_DEBUG_KMS("\n");
3472 /* if we want to turn off the cursor ignore width and height */
3474 DRM_DEBUG_KMS("cursor off\n");
3475 if (IS_MOBILE(dev
) || IS_I9XX(dev
)) {
3476 temp
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
3477 temp
|= CURSOR_MODE_DISABLE
;
3479 temp
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
3483 mutex_lock(&dev
->struct_mutex
);
3487 /* Currently we only support 64x64 cursors */
3488 if (width
!= 64 || height
!= 64) {
3489 DRM_ERROR("we currently only support 64x64 cursors\n");
3493 bo
= drm_gem_object_lookup(dev
, file_priv
, handle
);
3497 obj_priv
= bo
->driver_private
;
3499 if (bo
->size
< width
* height
* 4) {
3500 DRM_ERROR("buffer is to small\n");
3505 /* we only need to pin inside GTT if cursor is non-phy */
3506 mutex_lock(&dev
->struct_mutex
);
3507 if (!dev_priv
->info
->cursor_needs_physical
) {
3508 ret
= i915_gem_object_pin(bo
, PAGE_SIZE
);
3510 DRM_ERROR("failed to pin cursor bo\n");
3513 addr
= obj_priv
->gtt_offset
;
3515 ret
= i915_gem_attach_phys_object(dev
, bo
, (pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
);
3517 DRM_ERROR("failed to attach phys object\n");
3520 addr
= obj_priv
->phys_obj
->handle
->busaddr
;
3524 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
3526 /* Hooray for CUR*CNTR differences */
3527 if (IS_MOBILE(dev
) || IS_I9XX(dev
)) {
3528 temp
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
3529 temp
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
3530 temp
|= (pipe
<< 28); /* Connect to correct pipe */
3532 temp
&= ~(CURSOR_FORMAT_MASK
);
3533 temp
|= CURSOR_ENABLE
;
3534 temp
|= CURSOR_FORMAT_ARGB
| CURSOR_GAMMA_ENABLE
;
3538 I915_WRITE(control
, temp
);
3539 I915_WRITE(base
, addr
);
3541 if (intel_crtc
->cursor_bo
) {
3542 if (dev_priv
->info
->cursor_needs_physical
) {
3543 if (intel_crtc
->cursor_bo
!= bo
)
3544 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
3546 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
3547 drm_gem_object_unreference(intel_crtc
->cursor_bo
);
3550 mutex_unlock(&dev
->struct_mutex
);
3552 intel_crtc
->cursor_addr
= addr
;
3553 intel_crtc
->cursor_bo
= bo
;
3557 mutex_unlock(&dev
->struct_mutex
);
3559 drm_gem_object_unreference_unlocked(bo
);
3563 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
3565 struct drm_device
*dev
= crtc
->dev
;
3566 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3567 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3568 struct intel_framebuffer
*intel_fb
;
3569 int pipe
= intel_crtc
->pipe
;
3574 intel_fb
= to_intel_framebuffer(crtc
->fb
);
3575 intel_mark_busy(dev
, intel_fb
->obj
);
3579 temp
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
3583 temp
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
3587 temp
|= x
<< CURSOR_X_SHIFT
;
3588 temp
|= y
<< CURSOR_Y_SHIFT
;
3590 adder
= intel_crtc
->cursor_addr
;
3591 I915_WRITE((pipe
== 0) ? CURAPOS
: CURBPOS
, temp
);
3592 I915_WRITE((pipe
== 0) ? CURABASE
: CURBBASE
, adder
);
3597 /** Sets the color ramps on behalf of RandR */
3598 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
3599 u16 blue
, int regno
)
3601 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3603 intel_crtc
->lut_r
[regno
] = red
>> 8;
3604 intel_crtc
->lut_g
[regno
] = green
>> 8;
3605 intel_crtc
->lut_b
[regno
] = blue
>> 8;
3608 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
3609 u16
*blue
, int regno
)
3611 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3613 *red
= intel_crtc
->lut_r
[regno
] << 8;
3614 *green
= intel_crtc
->lut_g
[regno
] << 8;
3615 *blue
= intel_crtc
->lut_b
[regno
] << 8;
3618 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
3619 u16
*blue
, uint32_t size
)
3621 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3627 for (i
= 0; i
< 256; i
++) {
3628 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
3629 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
3630 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
3633 intel_crtc_load_lut(crtc
);
3637 * Get a pipe with a simple mode set on it for doing load-based monitor
3640 * It will be up to the load-detect code to adjust the pipe as appropriate for
3641 * its requirements. The pipe will be connected to no other outputs.
3643 * Currently this code will only succeed if there is a pipe with no outputs
3644 * configured for it. In the future, it could choose to temporarily disable
3645 * some outputs to free up a pipe for its use.
3647 * \return crtc, or NULL if no pipes are available.
3650 /* VESA 640x480x72Hz mode to set on the pipe */
3651 static struct drm_display_mode load_detect_mode
= {
3652 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
3653 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
3656 struct drm_crtc
*intel_get_load_detect_pipe(struct intel_output
*intel_output
,
3657 struct drm_display_mode
*mode
,
3660 struct intel_crtc
*intel_crtc
;
3661 struct drm_crtc
*possible_crtc
;
3662 struct drm_crtc
*supported_crtc
=NULL
;
3663 struct drm_encoder
*encoder
= &intel_output
->enc
;
3664 struct drm_crtc
*crtc
= NULL
;
3665 struct drm_device
*dev
= encoder
->dev
;
3666 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
3667 struct drm_crtc_helper_funcs
*crtc_funcs
;
3671 * Algorithm gets a little messy:
3672 * - if the connector already has an assigned crtc, use it (but make
3673 * sure it's on first)
3674 * - try to find the first unused crtc that can drive this connector,
3675 * and use that if we find one
3676 * - if there are no unused crtcs available, try to use the first
3677 * one we found that supports the connector
3680 /* See if we already have a CRTC for this connector */
3681 if (encoder
->crtc
) {
3682 crtc
= encoder
->crtc
;
3683 /* Make sure the crtc and connector are running */
3684 intel_crtc
= to_intel_crtc(crtc
);
3685 *dpms_mode
= intel_crtc
->dpms_mode
;
3686 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
3687 crtc_funcs
= crtc
->helper_private
;
3688 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
3689 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
3694 /* Find an unused one (if possible) */
3695 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
3697 if (!(encoder
->possible_crtcs
& (1 << i
)))
3699 if (!possible_crtc
->enabled
) {
3700 crtc
= possible_crtc
;
3703 if (!supported_crtc
)
3704 supported_crtc
= possible_crtc
;
3708 * If we didn't find an unused CRTC, don't use any.
3714 encoder
->crtc
= crtc
;
3715 intel_output
->base
.encoder
= encoder
;
3716 intel_output
->load_detect_temp
= true;
3718 intel_crtc
= to_intel_crtc(crtc
);
3719 *dpms_mode
= intel_crtc
->dpms_mode
;
3721 if (!crtc
->enabled
) {
3723 mode
= &load_detect_mode
;
3724 drm_crtc_helper_set_mode(crtc
, mode
, 0, 0, crtc
->fb
);
3726 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
3727 crtc_funcs
= crtc
->helper_private
;
3728 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
3731 /* Add this connector to the crtc */
3732 encoder_funcs
->mode_set(encoder
, &crtc
->mode
, &crtc
->mode
);
3733 encoder_funcs
->commit(encoder
);
3735 /* let the connector get through one full cycle before testing */
3736 intel_wait_for_vblank(dev
);
3741 void intel_release_load_detect_pipe(struct intel_output
*intel_output
, int dpms_mode
)
3743 struct drm_encoder
*encoder
= &intel_output
->enc
;
3744 struct drm_device
*dev
= encoder
->dev
;
3745 struct drm_crtc
*crtc
= encoder
->crtc
;
3746 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
3747 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
3749 if (intel_output
->load_detect_temp
) {
3750 encoder
->crtc
= NULL
;
3751 intel_output
->base
.encoder
= NULL
;
3752 intel_output
->load_detect_temp
= false;
3753 crtc
->enabled
= drm_helper_crtc_in_use(crtc
);
3754 drm_helper_disable_unused_functions(dev
);
3757 /* Switch crtc and output back off if necessary */
3758 if (crtc
->enabled
&& dpms_mode
!= DRM_MODE_DPMS_ON
) {
3759 if (encoder
->crtc
== crtc
)
3760 encoder_funcs
->dpms(encoder
, dpms_mode
);
3761 crtc_funcs
->dpms(crtc
, dpms_mode
);
3765 /* Returns the clock of the currently programmed mode of the given pipe. */
3766 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
3768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3769 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3770 int pipe
= intel_crtc
->pipe
;
3771 u32 dpll
= I915_READ((pipe
== 0) ? DPLL_A
: DPLL_B
);
3773 intel_clock_t clock
;
3775 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
3776 fp
= I915_READ((pipe
== 0) ? FPA0
: FPB0
);
3778 fp
= I915_READ((pipe
== 0) ? FPA1
: FPB1
);
3780 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
3781 if (IS_PINEVIEW(dev
)) {
3782 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
3783 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
3785 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
3786 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
3790 if (IS_PINEVIEW(dev
))
3791 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
3792 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
3794 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
3795 DPLL_FPA01_P1_POST_DIV_SHIFT
);
3797 switch (dpll
& DPLL_MODE_MASK
) {
3798 case DPLLB_MODE_DAC_SERIAL
:
3799 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
3802 case DPLLB_MODE_LVDS
:
3803 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
3807 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
3808 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
3812 /* XXX: Handle the 100Mhz refclk */
3813 intel_clock(dev
, 96000, &clock
);
3815 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
3818 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
3819 DPLL_FPA01_P1_POST_DIV_SHIFT
);
3822 if ((dpll
& PLL_REF_INPUT_MASK
) ==
3823 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
3824 /* XXX: might not be 66MHz */
3825 intel_clock(dev
, 66000, &clock
);
3827 intel_clock(dev
, 48000, &clock
);
3829 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
3832 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
3833 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
3835 if (dpll
& PLL_P2_DIVIDE_BY_4
)
3840 intel_clock(dev
, 48000, &clock
);
3844 /* XXX: It would be nice to validate the clocks, but we can't reuse
3845 * i830PllIsValid() because it relies on the xf86_config connector
3846 * configuration being accurate, which it isn't necessarily.
3852 /** Returns the currently programmed mode of the given pipe. */
3853 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
3854 struct drm_crtc
*crtc
)
3856 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3857 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3858 int pipe
= intel_crtc
->pipe
;
3859 struct drm_display_mode
*mode
;
3860 int htot
= I915_READ((pipe
== 0) ? HTOTAL_A
: HTOTAL_B
);
3861 int hsync
= I915_READ((pipe
== 0) ? HSYNC_A
: HSYNC_B
);
3862 int vtot
= I915_READ((pipe
== 0) ? VTOTAL_A
: VTOTAL_B
);
3863 int vsync
= I915_READ((pipe
== 0) ? VSYNC_A
: VSYNC_B
);
3865 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
3869 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
3870 mode
->hdisplay
= (htot
& 0xffff) + 1;
3871 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
3872 mode
->hsync_start
= (hsync
& 0xffff) + 1;
3873 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
3874 mode
->vdisplay
= (vtot
& 0xffff) + 1;
3875 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
3876 mode
->vsync_start
= (vsync
& 0xffff) + 1;
3877 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
3879 drm_mode_set_name(mode
);
3880 drm_mode_set_crtcinfo(mode
, 0);
3885 #define GPU_IDLE_TIMEOUT 500 /* ms */
3887 /* When this timer fires, we've been idle for awhile */
3888 static void intel_gpu_idle_timer(unsigned long arg
)
3890 struct drm_device
*dev
= (struct drm_device
*)arg
;
3891 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3893 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3895 dev_priv
->busy
= false;
3897 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
3900 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3902 static void intel_crtc_idle_timer(unsigned long arg
)
3904 struct intel_crtc
*intel_crtc
= (struct intel_crtc
*)arg
;
3905 struct drm_crtc
*crtc
= &intel_crtc
->base
;
3906 drm_i915_private_t
*dev_priv
= crtc
->dev
->dev_private
;
3908 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3910 intel_crtc
->busy
= false;
3912 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
3915 static void intel_increase_pllclock(struct drm_crtc
*crtc
, bool schedule
)
3917 struct drm_device
*dev
= crtc
->dev
;
3918 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3919 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3920 int pipe
= intel_crtc
->pipe
;
3921 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
3922 int dpll
= I915_READ(dpll_reg
);
3924 if (IS_IRONLAKE(dev
))
3927 if (!dev_priv
->lvds_downclock_avail
)
3930 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
3931 DRM_DEBUG_DRIVER("upclocking LVDS\n");
3933 /* Unlock panel regs */
3934 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) | (0xabcd << 16));
3936 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
3937 I915_WRITE(dpll_reg
, dpll
);
3938 dpll
= I915_READ(dpll_reg
);
3939 intel_wait_for_vblank(dev
);
3940 dpll
= I915_READ(dpll_reg
);
3941 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
3942 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
3944 /* ...and lock them again */
3945 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) & 0x3);
3948 /* Schedule downclock */
3950 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
3951 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
3954 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
3956 struct drm_device
*dev
= crtc
->dev
;
3957 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3958 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3959 int pipe
= intel_crtc
->pipe
;
3960 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
3961 int dpll
= I915_READ(dpll_reg
);
3963 if (IS_IRONLAKE(dev
))
3966 if (!dev_priv
->lvds_downclock_avail
)
3970 * Since this is called by a timer, we should never get here in
3973 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
3974 DRM_DEBUG_DRIVER("downclocking LVDS\n");
3976 /* Unlock panel regs */
3977 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) | (0xabcd << 16));
3979 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
3980 I915_WRITE(dpll_reg
, dpll
);
3981 dpll
= I915_READ(dpll_reg
);
3982 intel_wait_for_vblank(dev
);
3983 dpll
= I915_READ(dpll_reg
);
3984 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
3985 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
3987 /* ...and lock them again */
3988 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) & 0x3);
3994 * intel_idle_update - adjust clocks for idleness
3995 * @work: work struct
3997 * Either the GPU or display (or both) went idle. Check the busy status
3998 * here and adjust the CRTC and GPU clocks as necessary.
4000 static void intel_idle_update(struct work_struct
*work
)
4002 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
4004 struct drm_device
*dev
= dev_priv
->dev
;
4005 struct drm_crtc
*crtc
;
4006 struct intel_crtc
*intel_crtc
;
4008 if (!i915_powersave
)
4011 mutex_lock(&dev
->struct_mutex
);
4013 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4014 /* Skip inactive CRTCs */
4018 intel_crtc
= to_intel_crtc(crtc
);
4019 if (!intel_crtc
->busy
)
4020 intel_decrease_pllclock(crtc
);
4023 mutex_unlock(&dev
->struct_mutex
);
4027 * intel_mark_busy - mark the GPU and possibly the display busy
4029 * @obj: object we're operating on
4031 * Callers can use this function to indicate that the GPU is busy processing
4032 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4033 * buffer), we'll also mark the display as busy, so we know to increase its
4036 void intel_mark_busy(struct drm_device
*dev
, struct drm_gem_object
*obj
)
4038 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4039 struct drm_crtc
*crtc
= NULL
;
4040 struct intel_framebuffer
*intel_fb
;
4041 struct intel_crtc
*intel_crtc
;
4043 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4046 if (!dev_priv
->busy
)
4047 dev_priv
->busy
= true;
4049 mod_timer(&dev_priv
->idle_timer
, jiffies
+
4050 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
4052 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4056 intel_crtc
= to_intel_crtc(crtc
);
4057 intel_fb
= to_intel_framebuffer(crtc
->fb
);
4058 if (intel_fb
->obj
== obj
) {
4059 if (!intel_crtc
->busy
) {
4060 /* Non-busy -> busy, upclock */
4061 intel_increase_pllclock(crtc
, true);
4062 intel_crtc
->busy
= true;
4064 /* Busy -> busy, put off timer */
4065 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
4066 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
4072 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
4074 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4076 drm_crtc_cleanup(crtc
);
4080 struct intel_unpin_work
{
4081 struct work_struct work
;
4082 struct drm_device
*dev
;
4083 struct drm_gem_object
*old_fb_obj
;
4084 struct drm_gem_object
*pending_flip_obj
;
4085 struct drm_pending_vblank_event
*event
;
4089 static void intel_unpin_work_fn(struct work_struct
*__work
)
4091 struct intel_unpin_work
*work
=
4092 container_of(__work
, struct intel_unpin_work
, work
);
4094 mutex_lock(&work
->dev
->struct_mutex
);
4095 i915_gem_object_unpin(work
->old_fb_obj
);
4096 drm_gem_object_unreference(work
->pending_flip_obj
);
4097 drm_gem_object_unreference(work
->old_fb_obj
);
4098 mutex_unlock(&work
->dev
->struct_mutex
);
4102 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
4104 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4105 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
4106 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4107 struct intel_unpin_work
*work
;
4108 struct drm_i915_gem_object
*obj_priv
;
4109 struct drm_pending_vblank_event
*e
;
4111 unsigned long flags
;
4113 /* Ignore early vblank irqs */
4114 if (intel_crtc
== NULL
)
4117 spin_lock_irqsave(&dev
->event_lock
, flags
);
4118 work
= intel_crtc
->unpin_work
;
4119 if (work
== NULL
|| !work
->pending
) {
4120 if (work
&& !work
->pending
) {
4121 obj_priv
= work
->pending_flip_obj
->driver_private
;
4122 DRM_DEBUG_DRIVER("flip finish: %p (%d) not pending?\n",
4124 atomic_read(&obj_priv
->pending_flip
));
4126 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4130 intel_crtc
->unpin_work
= NULL
;
4131 drm_vblank_put(dev
, intel_crtc
->pipe
);
4135 do_gettimeofday(&now
);
4136 e
->event
.sequence
= drm_vblank_count(dev
, intel_crtc
->pipe
);
4137 e
->event
.tv_sec
= now
.tv_sec
;
4138 e
->event
.tv_usec
= now
.tv_usec
;
4139 list_add_tail(&e
->base
.link
,
4140 &e
->base
.file_priv
->event_list
);
4141 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
4144 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4146 obj_priv
= work
->pending_flip_obj
->driver_private
;
4148 /* Initial scanout buffer will have a 0 pending flip count */
4149 if ((atomic_read(&obj_priv
->pending_flip
) == 0) ||
4150 atomic_dec_and_test(&obj_priv
->pending_flip
))
4151 DRM_WAKEUP(&dev_priv
->pending_flip_queue
);
4152 schedule_work(&work
->work
);
4155 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
4157 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4158 struct intel_crtc
*intel_crtc
=
4159 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
4160 unsigned long flags
;
4162 spin_lock_irqsave(&dev
->event_lock
, flags
);
4163 if (intel_crtc
->unpin_work
) {
4164 intel_crtc
->unpin_work
->pending
= 1;
4166 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4168 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4171 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
4172 struct drm_framebuffer
*fb
,
4173 struct drm_pending_vblank_event
*event
)
4175 struct drm_device
*dev
= crtc
->dev
;
4176 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4177 struct intel_framebuffer
*intel_fb
;
4178 struct drm_i915_gem_object
*obj_priv
;
4179 struct drm_gem_object
*obj
;
4180 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4181 struct intel_unpin_work
*work
;
4182 unsigned long flags
;
4183 int pipesrc_reg
= (intel_crtc
->pipe
== 0) ? PIPEASRC
: PIPEBSRC
;
4187 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
4191 mutex_lock(&dev
->struct_mutex
);
4193 work
->event
= event
;
4194 work
->dev
= crtc
->dev
;
4195 intel_fb
= to_intel_framebuffer(crtc
->fb
);
4196 work
->old_fb_obj
= intel_fb
->obj
;
4197 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
4199 /* We borrow the event spin lock for protecting unpin_work */
4200 spin_lock_irqsave(&dev
->event_lock
, flags
);
4201 if (intel_crtc
->unpin_work
) {
4202 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4203 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4205 mutex_unlock(&dev
->struct_mutex
);
4208 intel_crtc
->unpin_work
= work
;
4209 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4211 intel_fb
= to_intel_framebuffer(fb
);
4212 obj
= intel_fb
->obj
;
4214 ret
= intel_pin_and_fence_fb_obj(dev
, obj
);
4216 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
4217 obj
->driver_private
);
4219 intel_crtc
->unpin_work
= NULL
;
4220 mutex_unlock(&dev
->struct_mutex
);
4224 /* Reference the objects for the scheduled work. */
4225 drm_gem_object_reference(work
->old_fb_obj
);
4226 drm_gem_object_reference(obj
);
4229 i915_gem_object_flush_write_domain(obj
);
4230 drm_vblank_get(dev
, intel_crtc
->pipe
);
4231 obj_priv
= obj
->driver_private
;
4232 atomic_inc(&obj_priv
->pending_flip
);
4233 work
->pending_flip_obj
= obj
;
4236 OUT_RING(MI_DISPLAY_FLIP
|
4237 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
4238 OUT_RING(fb
->pitch
);
4239 if (IS_I965G(dev
)) {
4240 OUT_RING(obj_priv
->gtt_offset
| obj_priv
->tiling_mode
);
4241 pipesrc
= I915_READ(pipesrc_reg
);
4242 OUT_RING(pipesrc
& 0x0fff0fff);
4244 OUT_RING(obj_priv
->gtt_offset
);
4249 mutex_unlock(&dev
->struct_mutex
);
4254 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
4255 .dpms
= intel_crtc_dpms
,
4256 .mode_fixup
= intel_crtc_mode_fixup
,
4257 .mode_set
= intel_crtc_mode_set
,
4258 .mode_set_base
= intel_pipe_set_base
,
4259 .prepare
= intel_crtc_prepare
,
4260 .commit
= intel_crtc_commit
,
4261 .load_lut
= intel_crtc_load_lut
,
4264 static const struct drm_crtc_funcs intel_crtc_funcs
= {
4265 .cursor_set
= intel_crtc_cursor_set
,
4266 .cursor_move
= intel_crtc_cursor_move
,
4267 .gamma_set
= intel_crtc_gamma_set
,
4268 .set_config
= drm_crtc_helper_set_config
,
4269 .destroy
= intel_crtc_destroy
,
4270 .page_flip
= intel_crtc_page_flip
,
4274 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
4276 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4277 struct intel_crtc
*intel_crtc
;
4280 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
4281 if (intel_crtc
== NULL
)
4284 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
4286 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
4287 intel_crtc
->pipe
= pipe
;
4288 intel_crtc
->plane
= pipe
;
4289 for (i
= 0; i
< 256; i
++) {
4290 intel_crtc
->lut_r
[i
] = i
;
4291 intel_crtc
->lut_g
[i
] = i
;
4292 intel_crtc
->lut_b
[i
] = i
;
4295 /* Swap pipes & planes for FBC on pre-965 */
4296 intel_crtc
->pipe
= pipe
;
4297 intel_crtc
->plane
= pipe
;
4298 if (IS_MOBILE(dev
) && (IS_I9XX(dev
) && !IS_I965G(dev
))) {
4299 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4300 intel_crtc
->plane
= ((pipe
== 0) ? 1 : 0);
4303 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
4304 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
4305 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
4306 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
4308 intel_crtc
->cursor_addr
= 0;
4309 intel_crtc
->dpms_mode
= DRM_MODE_DPMS_OFF
;
4310 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
4312 intel_crtc
->busy
= false;
4314 setup_timer(&intel_crtc
->idle_timer
, intel_crtc_idle_timer
,
4315 (unsigned long)intel_crtc
);
4318 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
4319 struct drm_file
*file_priv
)
4321 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4322 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
4323 struct drm_mode_object
*drmmode_obj
;
4324 struct intel_crtc
*crtc
;
4327 DRM_ERROR("called with no initialization\n");
4331 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
4332 DRM_MODE_OBJECT_CRTC
);
4335 DRM_ERROR("no such CRTC id\n");
4339 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
4340 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
4345 struct drm_crtc
*intel_get_crtc_from_pipe(struct drm_device
*dev
, int pipe
)
4347 struct drm_crtc
*crtc
= NULL
;
4349 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4350 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4351 if (intel_crtc
->pipe
== pipe
)
4357 static int intel_connector_clones(struct drm_device
*dev
, int type_mask
)
4360 struct drm_connector
*connector
;
4363 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
4364 struct intel_output
*intel_output
= to_intel_output(connector
);
4365 if (type_mask
& intel_output
->clone_mask
)
4366 index_mask
|= (1 << entry
);
4373 static void intel_setup_outputs(struct drm_device
*dev
)
4375 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4376 struct drm_connector
*connector
;
4378 intel_crt_init(dev
);
4380 /* Set up integrated LVDS */
4381 if (IS_MOBILE(dev
) && !IS_I830(dev
))
4382 intel_lvds_init(dev
);
4384 if (IS_IRONLAKE(dev
)) {
4387 if (IS_MOBILE(dev
) && (I915_READ(DP_A
) & DP_DETECTED
))
4388 intel_dp_init(dev
, DP_A
);
4390 if (I915_READ(HDMIB
) & PORT_DETECTED
) {
4392 /* found = intel_sdvo_init(dev, HDMIB); */
4395 intel_hdmi_init(dev
, HDMIB
);
4396 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
4397 intel_dp_init(dev
, PCH_DP_B
);
4400 if (I915_READ(HDMIC
) & PORT_DETECTED
)
4401 intel_hdmi_init(dev
, HDMIC
);
4403 if (I915_READ(HDMID
) & PORT_DETECTED
)
4404 intel_hdmi_init(dev
, HDMID
);
4406 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
4407 intel_dp_init(dev
, PCH_DP_C
);
4409 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
4410 intel_dp_init(dev
, PCH_DP_D
);
4412 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
4415 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
4416 DRM_DEBUG_KMS("probing SDVOB\n");
4417 found
= intel_sdvo_init(dev
, SDVOB
);
4418 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
4419 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4420 intel_hdmi_init(dev
, SDVOB
);
4423 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
4424 DRM_DEBUG_KMS("probing DP_B\n");
4425 intel_dp_init(dev
, DP_B
);
4429 /* Before G4X SDVOC doesn't have its own detect register */
4431 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
4432 DRM_DEBUG_KMS("probing SDVOC\n");
4433 found
= intel_sdvo_init(dev
, SDVOC
);
4436 if (!found
&& (I915_READ(SDVOC
) & SDVO_DETECTED
)) {
4438 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
4439 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4440 intel_hdmi_init(dev
, SDVOC
);
4442 if (SUPPORTS_INTEGRATED_DP(dev
)) {
4443 DRM_DEBUG_KMS("probing DP_C\n");
4444 intel_dp_init(dev
, DP_C
);
4448 if (SUPPORTS_INTEGRATED_DP(dev
) &&
4449 (I915_READ(DP_D
) & DP_DETECTED
)) {
4450 DRM_DEBUG_KMS("probing DP_D\n");
4451 intel_dp_init(dev
, DP_D
);
4453 } else if (IS_I8XX(dev
))
4454 intel_dvo_init(dev
);
4456 if (SUPPORTS_TV(dev
))
4459 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
4460 struct intel_output
*intel_output
= to_intel_output(connector
);
4461 struct drm_encoder
*encoder
= &intel_output
->enc
;
4463 encoder
->possible_crtcs
= intel_output
->crtc_mask
;
4464 encoder
->possible_clones
= intel_connector_clones(dev
,
4465 intel_output
->clone_mask
);
4469 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
4471 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
4472 struct drm_device
*dev
= fb
->dev
;
4475 intelfb_remove(dev
, fb
);
4477 drm_framebuffer_cleanup(fb
);
4478 drm_gem_object_unreference_unlocked(intel_fb
->obj
);
4483 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
4484 struct drm_file
*file_priv
,
4485 unsigned int *handle
)
4487 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
4488 struct drm_gem_object
*object
= intel_fb
->obj
;
4490 return drm_gem_handle_create(file_priv
, object
, handle
);
4493 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
4494 .destroy
= intel_user_framebuffer_destroy
,
4495 .create_handle
= intel_user_framebuffer_create_handle
,
4498 int intel_framebuffer_create(struct drm_device
*dev
,
4499 struct drm_mode_fb_cmd
*mode_cmd
,
4500 struct drm_framebuffer
**fb
,
4501 struct drm_gem_object
*obj
)
4503 struct intel_framebuffer
*intel_fb
;
4506 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
4510 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
4512 DRM_ERROR("framebuffer init failed %d\n", ret
);
4516 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
4518 intel_fb
->obj
= obj
;
4520 *fb
= &intel_fb
->base
;
4526 static struct drm_framebuffer
*
4527 intel_user_framebuffer_create(struct drm_device
*dev
,
4528 struct drm_file
*filp
,
4529 struct drm_mode_fb_cmd
*mode_cmd
)
4531 struct drm_gem_object
*obj
;
4532 struct drm_framebuffer
*fb
;
4535 obj
= drm_gem_object_lookup(dev
, filp
, mode_cmd
->handle
);
4539 ret
= intel_framebuffer_create(dev
, mode_cmd
, &fb
, obj
);
4541 drm_gem_object_unreference_unlocked(obj
);
4548 static const struct drm_mode_config_funcs intel_mode_funcs
= {
4549 .fb_create
= intel_user_framebuffer_create
,
4550 .fb_changed
= intelfb_probe
,
4553 static struct drm_gem_object
*
4554 intel_alloc_power_context(struct drm_device
*dev
)
4556 struct drm_gem_object
*pwrctx
;
4559 pwrctx
= drm_gem_object_alloc(dev
, 4096);
4561 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4565 mutex_lock(&dev
->struct_mutex
);
4566 ret
= i915_gem_object_pin(pwrctx
, 4096);
4568 DRM_ERROR("failed to pin power context: %d\n", ret
);
4572 ret
= i915_gem_object_set_to_gtt_domain(pwrctx
, 1);
4574 DRM_ERROR("failed to set-domain on power context: %d\n", ret
);
4577 mutex_unlock(&dev
->struct_mutex
);
4582 i915_gem_object_unpin(pwrctx
);
4584 drm_gem_object_unreference(pwrctx
);
4585 mutex_unlock(&dev
->struct_mutex
);
4589 void intel_init_clock_gating(struct drm_device
*dev
)
4591 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4594 * Disable clock gating reported to work incorrectly according to the
4595 * specs, but enable as much else as we can.
4597 if (IS_IRONLAKE(dev
)) {
4599 } else if (IS_G4X(dev
)) {
4600 uint32_t dspclk_gate
;
4601 I915_WRITE(RENCLK_GATE_D1
, 0);
4602 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
4603 GS_UNIT_CLOCK_GATE_DISABLE
|
4604 CL_UNIT_CLOCK_GATE_DISABLE
);
4605 I915_WRITE(RAMCLK_GATE_D
, 0);
4606 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
4607 OVRUNIT_CLOCK_GATE_DISABLE
|
4608 OVCUNIT_CLOCK_GATE_DISABLE
;
4610 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
4611 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
4612 } else if (IS_I965GM(dev
)) {
4613 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
4614 I915_WRITE(RENCLK_GATE_D2
, 0);
4615 I915_WRITE(DSPCLK_GATE_D
, 0);
4616 I915_WRITE(RAMCLK_GATE_D
, 0);
4617 I915_WRITE16(DEUC
, 0);
4618 } else if (IS_I965G(dev
)) {
4619 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
4620 I965_RCC_CLOCK_GATE_DISABLE
|
4621 I965_RCPB_CLOCK_GATE_DISABLE
|
4622 I965_ISC_CLOCK_GATE_DISABLE
|
4623 I965_FBC_CLOCK_GATE_DISABLE
);
4624 I915_WRITE(RENCLK_GATE_D2
, 0);
4625 } else if (IS_I9XX(dev
)) {
4626 u32 dstate
= I915_READ(D_STATE
);
4628 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
4629 DSTATE_DOT_CLOCK_GATING
;
4630 I915_WRITE(D_STATE
, dstate
);
4631 } else if (IS_I85X(dev
) || IS_I865G(dev
)) {
4632 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
4633 } else if (IS_I830(dev
)) {
4634 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
4638 * GPU can automatically power down the render unit if given a page
4641 if (I915_HAS_RC6(dev
) && drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4642 struct drm_i915_gem_object
*obj_priv
= NULL
;
4644 if (dev_priv
->pwrctx
) {
4645 obj_priv
= dev_priv
->pwrctx
->driver_private
;
4647 struct drm_gem_object
*pwrctx
;
4649 pwrctx
= intel_alloc_power_context(dev
);
4651 dev_priv
->pwrctx
= pwrctx
;
4652 obj_priv
= pwrctx
->driver_private
;
4657 I915_WRITE(PWRCTXA
, obj_priv
->gtt_offset
| PWRCTX_EN
);
4658 I915_WRITE(MCHBAR_RENDER_STANDBY
,
4659 I915_READ(MCHBAR_RENDER_STANDBY
) & ~RCX_SW_EXIT
);
4664 /* Set up chip specific display functions */
4665 static void intel_init_display(struct drm_device
*dev
)
4667 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4669 /* We always want a DPMS function */
4670 if (IS_IRONLAKE(dev
))
4671 dev_priv
->display
.dpms
= ironlake_crtc_dpms
;
4673 dev_priv
->display
.dpms
= i9xx_crtc_dpms
;
4675 /* Only mobile has FBC, leave pointers NULL for other chips */
4676 if (IS_MOBILE(dev
)) {
4678 dev_priv
->display
.fbc_enabled
= g4x_fbc_enabled
;
4679 dev_priv
->display
.enable_fbc
= g4x_enable_fbc
;
4680 dev_priv
->display
.disable_fbc
= g4x_disable_fbc
;
4681 } else if (IS_I965GM(dev
) || IS_I945GM(dev
) || IS_I915GM(dev
)) {
4682 dev_priv
->display
.fbc_enabled
= i8xx_fbc_enabled
;
4683 dev_priv
->display
.enable_fbc
= i8xx_enable_fbc
;
4684 dev_priv
->display
.disable_fbc
= i8xx_disable_fbc
;
4686 /* 855GM needs testing */
4689 /* Returns the core display clock speed */
4690 if (IS_I945G(dev
) || (IS_G33(dev
) && ! IS_PINEVIEW_M(dev
)))
4691 dev_priv
->display
.get_display_clock_speed
=
4692 i945_get_display_clock_speed
;
4693 else if (IS_I915G(dev
))
4694 dev_priv
->display
.get_display_clock_speed
=
4695 i915_get_display_clock_speed
;
4696 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
4697 dev_priv
->display
.get_display_clock_speed
=
4698 i9xx_misc_get_display_clock_speed
;
4699 else if (IS_I915GM(dev
))
4700 dev_priv
->display
.get_display_clock_speed
=
4701 i915gm_get_display_clock_speed
;
4702 else if (IS_I865G(dev
))
4703 dev_priv
->display
.get_display_clock_speed
=
4704 i865_get_display_clock_speed
;
4705 else if (IS_I85X(dev
))
4706 dev_priv
->display
.get_display_clock_speed
=
4707 i855_get_display_clock_speed
;
4709 dev_priv
->display
.get_display_clock_speed
=
4710 i830_get_display_clock_speed
;
4712 /* For FIFO watermark updates */
4713 if (IS_IRONLAKE(dev
))
4714 dev_priv
->display
.update_wm
= NULL
;
4715 else if (IS_G4X(dev
))
4716 dev_priv
->display
.update_wm
= g4x_update_wm
;
4717 else if (IS_I965G(dev
))
4718 dev_priv
->display
.update_wm
= i965_update_wm
;
4719 else if (IS_I9XX(dev
) || IS_MOBILE(dev
)) {
4720 dev_priv
->display
.update_wm
= i9xx_update_wm
;
4721 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
4724 dev_priv
->display
.get_fifo_size
= i85x_get_fifo_size
;
4725 else if (IS_845G(dev
))
4726 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
4728 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
4729 dev_priv
->display
.update_wm
= i830_update_wm
;
4733 void intel_modeset_init(struct drm_device
*dev
)
4735 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4739 drm_mode_config_init(dev
);
4741 dev
->mode_config
.min_width
= 0;
4742 dev
->mode_config
.min_height
= 0;
4744 dev
->mode_config
.funcs
= (void *)&intel_mode_funcs
;
4746 intel_init_display(dev
);
4748 if (IS_I965G(dev
)) {
4749 dev
->mode_config
.max_width
= 8192;
4750 dev
->mode_config
.max_height
= 8192;
4751 } else if (IS_I9XX(dev
)) {
4752 dev
->mode_config
.max_width
= 4096;
4753 dev
->mode_config
.max_height
= 4096;
4755 dev
->mode_config
.max_width
= 2048;
4756 dev
->mode_config
.max_height
= 2048;
4759 /* set memory base */
4761 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 2);
4763 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 0);
4765 if (IS_MOBILE(dev
) || IS_I9XX(dev
))
4769 DRM_DEBUG_KMS("%d display pipe%s available.\n",
4770 num_pipe
, num_pipe
> 1 ? "s" : "");
4773 pci_read_config_word(dev
->pdev
, HPLLCC
, &dev_priv
->orig_clock
);
4774 else if (IS_I9XX(dev
) || IS_G4X(dev
))
4775 pci_read_config_word(dev
->pdev
, GCFGC
, &dev_priv
->orig_clock
);
4777 for (i
= 0; i
< num_pipe
; i
++) {
4778 intel_crtc_init(dev
, i
);
4781 intel_setup_outputs(dev
);
4783 intel_init_clock_gating(dev
);
4785 INIT_WORK(&dev_priv
->idle_work
, intel_idle_update
);
4786 setup_timer(&dev_priv
->idle_timer
, intel_gpu_idle_timer
,
4787 (unsigned long)dev
);
4789 intel_setup_overlay(dev
);
4791 if (IS_PINEVIEW(dev
) && !intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
4793 dev_priv
->mem_freq
))
4794 DRM_INFO("failed to find known CxSR latency "
4795 "(found fsb freq %d, mem freq %d), disabling CxSR\n",
4796 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
4799 void intel_modeset_cleanup(struct drm_device
*dev
)
4801 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4802 struct drm_crtc
*crtc
;
4803 struct intel_crtc
*intel_crtc
;
4805 mutex_lock(&dev
->struct_mutex
);
4807 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4808 /* Skip inactive CRTCs */
4812 intel_crtc
= to_intel_crtc(crtc
);
4813 intel_increase_pllclock(crtc
, false);
4814 del_timer_sync(&intel_crtc
->idle_timer
);
4817 del_timer_sync(&dev_priv
->idle_timer
);
4819 if (dev_priv
->display
.disable_fbc
)
4820 dev_priv
->display
.disable_fbc(dev
);
4822 if (dev_priv
->pwrctx
) {
4823 struct drm_i915_gem_object
*obj_priv
;
4825 obj_priv
= dev_priv
->pwrctx
->driver_private
;
4826 I915_WRITE(PWRCTXA
, obj_priv
->gtt_offset
&~ PWRCTX_EN
);
4828 i915_gem_object_unpin(dev_priv
->pwrctx
);
4829 drm_gem_object_unreference(dev_priv
->pwrctx
);
4832 mutex_unlock(&dev
->struct_mutex
);
4834 drm_mode_config_cleanup(dev
);
4838 /* current intel driver doesn't take advantage of encoders
4839 always give back the encoder for the connector
4841 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
4843 struct intel_output
*intel_output
= to_intel_output(connector
);
4845 return &intel_output
->enc
;
4849 * set vga decode state - true == enable VGA decode
4851 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
4853 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4856 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
4858 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
4860 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
4861 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);