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drm/i915: Add the exclusive fence to plane_state.
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "intel_dsi.h"
40 #include "i915_trace.h"
41 #include <drm/drm_atomic.h>
42 #include <drm/drm_atomic_helper.h>
43 #include <drm/drm_dp_helper.h>
44 #include <drm/drm_crtc_helper.h>
45 #include <drm/drm_plane_helper.h>
46 #include <drm/drm_rect.h>
47 #include <linux/dma_remapping.h>
48 #include <linux/reservation.h>
49 #include <linux/dma-buf.h>
50
51 static bool is_mmio_work(struct intel_flip_work *work)
52 {
53 return work->mmio_work.func;
54 }
55
56 /* Primary plane formats for gen <= 3 */
57 static const uint32_t i8xx_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB1555,
61 DRM_FORMAT_XRGB8888,
62 };
63
64 /* Primary plane formats for gen >= 4 */
65 static const uint32_t i965_primary_formats[] = {
66 DRM_FORMAT_C8,
67 DRM_FORMAT_RGB565,
68 DRM_FORMAT_XRGB8888,
69 DRM_FORMAT_XBGR8888,
70 DRM_FORMAT_XRGB2101010,
71 DRM_FORMAT_XBGR2101010,
72 };
73
74 static const uint32_t skl_primary_formats[] = {
75 DRM_FORMAT_C8,
76 DRM_FORMAT_RGB565,
77 DRM_FORMAT_XRGB8888,
78 DRM_FORMAT_XBGR8888,
79 DRM_FORMAT_ARGB8888,
80 DRM_FORMAT_ABGR8888,
81 DRM_FORMAT_XRGB2101010,
82 DRM_FORMAT_XBGR2101010,
83 DRM_FORMAT_YUYV,
84 DRM_FORMAT_YVYU,
85 DRM_FORMAT_UYVY,
86 DRM_FORMAT_VYUY,
87 };
88
89 /* Cursor formats */
90 static const uint32_t intel_cursor_formats[] = {
91 DRM_FORMAT_ARGB8888,
92 };
93
94 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
95 struct intel_crtc_state *pipe_config);
96 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
97 struct intel_crtc_state *pipe_config);
98
99 static int intel_framebuffer_init(struct drm_device *dev,
100 struct intel_framebuffer *ifb,
101 struct drm_mode_fb_cmd2 *mode_cmd,
102 struct drm_i915_gem_object *obj);
103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
107 struct intel_link_m_n *m_n,
108 struct intel_link_m_n *m2_n2);
109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
112 static void vlv_prepare_pll(struct intel_crtc *crtc,
113 const struct intel_crtc_state *pipe_config);
114 static void chv_prepare_pll(struct intel_crtc *crtc,
115 const struct intel_crtc_state *pipe_config);
116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
119 struct intel_crtc_state *crtc_state);
120 static void skylake_pfit_enable(struct intel_crtc *crtc);
121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
123 static void intel_modeset_setup_hw_state(struct drm_device *dev);
124 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
125 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
126
127 struct intel_limit {
128 struct {
129 int min, max;
130 } dot, vco, n, m, m1, m2, p, p1;
131
132 struct {
133 int dot_limit;
134 int p2_slow, p2_fast;
135 } p2;
136 };
137
138 /* returns HPLL frequency in kHz */
139 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
140 {
141 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
142
143 /* Obtain SKU information */
144 mutex_lock(&dev_priv->sb_lock);
145 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
146 CCK_FUSE_HPLL_FREQ_MASK;
147 mutex_unlock(&dev_priv->sb_lock);
148
149 return vco_freq[hpll_freq] * 1000;
150 }
151
152 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
153 const char *name, u32 reg, int ref_freq)
154 {
155 u32 val;
156 int divider;
157
158 mutex_lock(&dev_priv->sb_lock);
159 val = vlv_cck_read(dev_priv, reg);
160 mutex_unlock(&dev_priv->sb_lock);
161
162 divider = val & CCK_FREQUENCY_VALUES;
163
164 WARN((val & CCK_FREQUENCY_STATUS) !=
165 (divider << CCK_FREQUENCY_STATUS_SHIFT),
166 "%s change in progress\n", name);
167
168 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
169 }
170
171 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
172 const char *name, u32 reg)
173 {
174 if (dev_priv->hpll_freq == 0)
175 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
176
177 return vlv_get_cck_clock(dev_priv, name, reg,
178 dev_priv->hpll_freq);
179 }
180
181 static int
182 intel_pch_rawclk(struct drm_i915_private *dev_priv)
183 {
184 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
185 }
186
187 static int
188 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
189 {
190 /* RAWCLK_FREQ_VLV register updated from power well code */
191 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
192 CCK_DISPLAY_REF_CLOCK_CONTROL);
193 }
194
195 static int
196 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
197 {
198 uint32_t clkcfg;
199
200 /* hrawclock is 1/4 the FSB frequency */
201 clkcfg = I915_READ(CLKCFG);
202 switch (clkcfg & CLKCFG_FSB_MASK) {
203 case CLKCFG_FSB_400:
204 return 100000;
205 case CLKCFG_FSB_533:
206 return 133333;
207 case CLKCFG_FSB_667:
208 return 166667;
209 case CLKCFG_FSB_800:
210 return 200000;
211 case CLKCFG_FSB_1067:
212 return 266667;
213 case CLKCFG_FSB_1333:
214 return 333333;
215 /* these two are just a guess; one of them might be right */
216 case CLKCFG_FSB_1600:
217 case CLKCFG_FSB_1600_ALT:
218 return 400000;
219 default:
220 return 133333;
221 }
222 }
223
224 void intel_update_rawclk(struct drm_i915_private *dev_priv)
225 {
226 if (HAS_PCH_SPLIT(dev_priv))
227 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
228 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
229 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
230 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
231 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
232 else
233 return; /* no rawclk on other platforms, or no need to know it */
234
235 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
236 }
237
238 static void intel_update_czclk(struct drm_i915_private *dev_priv)
239 {
240 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
241 return;
242
243 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
244 CCK_CZ_CLOCK_CONTROL);
245
246 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
247 }
248
249 static inline u32 /* units of 100MHz */
250 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
251 const struct intel_crtc_state *pipe_config)
252 {
253 if (HAS_DDI(dev_priv))
254 return pipe_config->port_clock; /* SPLL */
255 else if (IS_GEN5(dev_priv))
256 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
257 else
258 return 270000;
259 }
260
261 static const struct intel_limit intel_limits_i8xx_dac = {
262 .dot = { .min = 25000, .max = 350000 },
263 .vco = { .min = 908000, .max = 1512000 },
264 .n = { .min = 2, .max = 16 },
265 .m = { .min = 96, .max = 140 },
266 .m1 = { .min = 18, .max = 26 },
267 .m2 = { .min = 6, .max = 16 },
268 .p = { .min = 4, .max = 128 },
269 .p1 = { .min = 2, .max = 33 },
270 .p2 = { .dot_limit = 165000,
271 .p2_slow = 4, .p2_fast = 2 },
272 };
273
274 static const struct intel_limit intel_limits_i8xx_dvo = {
275 .dot = { .min = 25000, .max = 350000 },
276 .vco = { .min = 908000, .max = 1512000 },
277 .n = { .min = 2, .max = 16 },
278 .m = { .min = 96, .max = 140 },
279 .m1 = { .min = 18, .max = 26 },
280 .m2 = { .min = 6, .max = 16 },
281 .p = { .min = 4, .max = 128 },
282 .p1 = { .min = 2, .max = 33 },
283 .p2 = { .dot_limit = 165000,
284 .p2_slow = 4, .p2_fast = 4 },
285 };
286
287 static const struct intel_limit intel_limits_i8xx_lvds = {
288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 908000, .max = 1512000 },
290 .n = { .min = 2, .max = 16 },
291 .m = { .min = 96, .max = 140 },
292 .m1 = { .min = 18, .max = 26 },
293 .m2 = { .min = 6, .max = 16 },
294 .p = { .min = 4, .max = 128 },
295 .p1 = { .min = 1, .max = 6 },
296 .p2 = { .dot_limit = 165000,
297 .p2_slow = 14, .p2_fast = 7 },
298 };
299
300 static const struct intel_limit intel_limits_i9xx_sdvo = {
301 .dot = { .min = 20000, .max = 400000 },
302 .vco = { .min = 1400000, .max = 2800000 },
303 .n = { .min = 1, .max = 6 },
304 .m = { .min = 70, .max = 120 },
305 .m1 = { .min = 8, .max = 18 },
306 .m2 = { .min = 3, .max = 7 },
307 .p = { .min = 5, .max = 80 },
308 .p1 = { .min = 1, .max = 8 },
309 .p2 = { .dot_limit = 200000,
310 .p2_slow = 10, .p2_fast = 5 },
311 };
312
313 static const struct intel_limit intel_limits_i9xx_lvds = {
314 .dot = { .min = 20000, .max = 400000 },
315 .vco = { .min = 1400000, .max = 2800000 },
316 .n = { .min = 1, .max = 6 },
317 .m = { .min = 70, .max = 120 },
318 .m1 = { .min = 8, .max = 18 },
319 .m2 = { .min = 3, .max = 7 },
320 .p = { .min = 7, .max = 98 },
321 .p1 = { .min = 1, .max = 8 },
322 .p2 = { .dot_limit = 112000,
323 .p2_slow = 14, .p2_fast = 7 },
324 };
325
326
327 static const struct intel_limit intel_limits_g4x_sdvo = {
328 .dot = { .min = 25000, .max = 270000 },
329 .vco = { .min = 1750000, .max = 3500000},
330 .n = { .min = 1, .max = 4 },
331 .m = { .min = 104, .max = 138 },
332 .m1 = { .min = 17, .max = 23 },
333 .m2 = { .min = 5, .max = 11 },
334 .p = { .min = 10, .max = 30 },
335 .p1 = { .min = 1, .max = 3},
336 .p2 = { .dot_limit = 270000,
337 .p2_slow = 10,
338 .p2_fast = 10
339 },
340 };
341
342 static const struct intel_limit intel_limits_g4x_hdmi = {
343 .dot = { .min = 22000, .max = 400000 },
344 .vco = { .min = 1750000, .max = 3500000},
345 .n = { .min = 1, .max = 4 },
346 .m = { .min = 104, .max = 138 },
347 .m1 = { .min = 16, .max = 23 },
348 .m2 = { .min = 5, .max = 11 },
349 .p = { .min = 5, .max = 80 },
350 .p1 = { .min = 1, .max = 8},
351 .p2 = { .dot_limit = 165000,
352 .p2_slow = 10, .p2_fast = 5 },
353 };
354
355 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
356 .dot = { .min = 20000, .max = 115000 },
357 .vco = { .min = 1750000, .max = 3500000 },
358 .n = { .min = 1, .max = 3 },
359 .m = { .min = 104, .max = 138 },
360 .m1 = { .min = 17, .max = 23 },
361 .m2 = { .min = 5, .max = 11 },
362 .p = { .min = 28, .max = 112 },
363 .p1 = { .min = 2, .max = 8 },
364 .p2 = { .dot_limit = 0,
365 .p2_slow = 14, .p2_fast = 14
366 },
367 };
368
369 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
370 .dot = { .min = 80000, .max = 224000 },
371 .vco = { .min = 1750000, .max = 3500000 },
372 .n = { .min = 1, .max = 3 },
373 .m = { .min = 104, .max = 138 },
374 .m1 = { .min = 17, .max = 23 },
375 .m2 = { .min = 5, .max = 11 },
376 .p = { .min = 14, .max = 42 },
377 .p1 = { .min = 2, .max = 6 },
378 .p2 = { .dot_limit = 0,
379 .p2_slow = 7, .p2_fast = 7
380 },
381 };
382
383 static const struct intel_limit intel_limits_pineview_sdvo = {
384 .dot = { .min = 20000, .max = 400000},
385 .vco = { .min = 1700000, .max = 3500000 },
386 /* Pineview's Ncounter is a ring counter */
387 .n = { .min = 3, .max = 6 },
388 .m = { .min = 2, .max = 256 },
389 /* Pineview only has one combined m divider, which we treat as m2. */
390 .m1 = { .min = 0, .max = 0 },
391 .m2 = { .min = 0, .max = 254 },
392 .p = { .min = 5, .max = 80 },
393 .p1 = { .min = 1, .max = 8 },
394 .p2 = { .dot_limit = 200000,
395 .p2_slow = 10, .p2_fast = 5 },
396 };
397
398 static const struct intel_limit intel_limits_pineview_lvds = {
399 .dot = { .min = 20000, .max = 400000 },
400 .vco = { .min = 1700000, .max = 3500000 },
401 .n = { .min = 3, .max = 6 },
402 .m = { .min = 2, .max = 256 },
403 .m1 = { .min = 0, .max = 0 },
404 .m2 = { .min = 0, .max = 254 },
405 .p = { .min = 7, .max = 112 },
406 .p1 = { .min = 1, .max = 8 },
407 .p2 = { .dot_limit = 112000,
408 .p2_slow = 14, .p2_fast = 14 },
409 };
410
411 /* Ironlake / Sandybridge
412 *
413 * We calculate clock using (register_value + 2) for N/M1/M2, so here
414 * the range value for them is (actual_value - 2).
415 */
416 static const struct intel_limit intel_limits_ironlake_dac = {
417 .dot = { .min = 25000, .max = 350000 },
418 .vco = { .min = 1760000, .max = 3510000 },
419 .n = { .min = 1, .max = 5 },
420 .m = { .min = 79, .max = 127 },
421 .m1 = { .min = 12, .max = 22 },
422 .m2 = { .min = 5, .max = 9 },
423 .p = { .min = 5, .max = 80 },
424 .p1 = { .min = 1, .max = 8 },
425 .p2 = { .dot_limit = 225000,
426 .p2_slow = 10, .p2_fast = 5 },
427 };
428
429 static const struct intel_limit intel_limits_ironlake_single_lvds = {
430 .dot = { .min = 25000, .max = 350000 },
431 .vco = { .min = 1760000, .max = 3510000 },
432 .n = { .min = 1, .max = 3 },
433 .m = { .min = 79, .max = 118 },
434 .m1 = { .min = 12, .max = 22 },
435 .m2 = { .min = 5, .max = 9 },
436 .p = { .min = 28, .max = 112 },
437 .p1 = { .min = 2, .max = 8 },
438 .p2 = { .dot_limit = 225000,
439 .p2_slow = 14, .p2_fast = 14 },
440 };
441
442 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
443 .dot = { .min = 25000, .max = 350000 },
444 .vco = { .min = 1760000, .max = 3510000 },
445 .n = { .min = 1, .max = 3 },
446 .m = { .min = 79, .max = 127 },
447 .m1 = { .min = 12, .max = 22 },
448 .m2 = { .min = 5, .max = 9 },
449 .p = { .min = 14, .max = 56 },
450 .p1 = { .min = 2, .max = 8 },
451 .p2 = { .dot_limit = 225000,
452 .p2_slow = 7, .p2_fast = 7 },
453 };
454
455 /* LVDS 100mhz refclk limits. */
456 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
457 .dot = { .min = 25000, .max = 350000 },
458 .vco = { .min = 1760000, .max = 3510000 },
459 .n = { .min = 1, .max = 2 },
460 .m = { .min = 79, .max = 126 },
461 .m1 = { .min = 12, .max = 22 },
462 .m2 = { .min = 5, .max = 9 },
463 .p = { .min = 28, .max = 112 },
464 .p1 = { .min = 2, .max = 8 },
465 .p2 = { .dot_limit = 225000,
466 .p2_slow = 14, .p2_fast = 14 },
467 };
468
469 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
470 .dot = { .min = 25000, .max = 350000 },
471 .vco = { .min = 1760000, .max = 3510000 },
472 .n = { .min = 1, .max = 3 },
473 .m = { .min = 79, .max = 126 },
474 .m1 = { .min = 12, .max = 22 },
475 .m2 = { .min = 5, .max = 9 },
476 .p = { .min = 14, .max = 42 },
477 .p1 = { .min = 2, .max = 6 },
478 .p2 = { .dot_limit = 225000,
479 .p2_slow = 7, .p2_fast = 7 },
480 };
481
482 static const struct intel_limit intel_limits_vlv = {
483 /*
484 * These are the data rate limits (measured in fast clocks)
485 * since those are the strictest limits we have. The fast
486 * clock and actual rate limits are more relaxed, so checking
487 * them would make no difference.
488 */
489 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
490 .vco = { .min = 4000000, .max = 6000000 },
491 .n = { .min = 1, .max = 7 },
492 .m1 = { .min = 2, .max = 3 },
493 .m2 = { .min = 11, .max = 156 },
494 .p1 = { .min = 2, .max = 3 },
495 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
496 };
497
498 static const struct intel_limit intel_limits_chv = {
499 /*
500 * These are the data rate limits (measured in fast clocks)
501 * since those are the strictest limits we have. The fast
502 * clock and actual rate limits are more relaxed, so checking
503 * them would make no difference.
504 */
505 .dot = { .min = 25000 * 5, .max = 540000 * 5},
506 .vco = { .min = 4800000, .max = 6480000 },
507 .n = { .min = 1, .max = 1 },
508 .m1 = { .min = 2, .max = 2 },
509 .m2 = { .min = 24 << 22, .max = 175 << 22 },
510 .p1 = { .min = 2, .max = 4 },
511 .p2 = { .p2_slow = 1, .p2_fast = 14 },
512 };
513
514 static const struct intel_limit intel_limits_bxt = {
515 /* FIXME: find real dot limits */
516 .dot = { .min = 0, .max = INT_MAX },
517 .vco = { .min = 4800000, .max = 6700000 },
518 .n = { .min = 1, .max = 1 },
519 .m1 = { .min = 2, .max = 2 },
520 /* FIXME: find real m2 limits */
521 .m2 = { .min = 2 << 22, .max = 255 << 22 },
522 .p1 = { .min = 2, .max = 4 },
523 .p2 = { .p2_slow = 1, .p2_fast = 20 },
524 };
525
526 static bool
527 needs_modeset(struct drm_crtc_state *state)
528 {
529 return drm_atomic_crtc_needs_modeset(state);
530 }
531
532 /**
533 * Returns whether any output on the specified pipe is of the specified type
534 */
535 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
536 {
537 struct drm_device *dev = crtc->base.dev;
538 struct intel_encoder *encoder;
539
540 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
541 if (encoder->type == type)
542 return true;
543
544 return false;
545 }
546
547 /**
548 * Returns whether any output on the specified pipe will have the specified
549 * type after a staged modeset is complete, i.e., the same as
550 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
551 * encoder->crtc.
552 */
553 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
554 int type)
555 {
556 struct drm_atomic_state *state = crtc_state->base.state;
557 struct drm_connector *connector;
558 struct drm_connector_state *connector_state;
559 struct intel_encoder *encoder;
560 int i, num_connectors = 0;
561
562 for_each_connector_in_state(state, connector, connector_state, i) {
563 if (connector_state->crtc != crtc_state->base.crtc)
564 continue;
565
566 num_connectors++;
567
568 encoder = to_intel_encoder(connector_state->best_encoder);
569 if (encoder->type == type)
570 return true;
571 }
572
573 WARN_ON(num_connectors == 0);
574
575 return false;
576 }
577
578 /*
579 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
580 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
581 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
582 * The helpers' return value is the rate of the clock that is fed to the
583 * display engine's pipe which can be the above fast dot clock rate or a
584 * divided-down version of it.
585 */
586 /* m1 is reserved as 0 in Pineview, n is a ring counter */
587 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
588 {
589 clock->m = clock->m2 + 2;
590 clock->p = clock->p1 * clock->p2;
591 if (WARN_ON(clock->n == 0 || clock->p == 0))
592 return 0;
593 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
594 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
595
596 return clock->dot;
597 }
598
599 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
600 {
601 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
602 }
603
604 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
605 {
606 clock->m = i9xx_dpll_compute_m(clock);
607 clock->p = clock->p1 * clock->p2;
608 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
609 return 0;
610 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
611 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
612
613 return clock->dot;
614 }
615
616 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
617 {
618 clock->m = clock->m1 * clock->m2;
619 clock->p = clock->p1 * clock->p2;
620 if (WARN_ON(clock->n == 0 || clock->p == 0))
621 return 0;
622 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
623 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
624
625 return clock->dot / 5;
626 }
627
628 int chv_calc_dpll_params(int refclk, struct dpll *clock)
629 {
630 clock->m = clock->m1 * clock->m2;
631 clock->p = clock->p1 * clock->p2;
632 if (WARN_ON(clock->n == 0 || clock->p == 0))
633 return 0;
634 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
635 clock->n << 22);
636 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
637
638 return clock->dot / 5;
639 }
640
641 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
642 /**
643 * Returns whether the given set of divisors are valid for a given refclk with
644 * the given connectors.
645 */
646
647 static bool intel_PLL_is_valid(struct drm_device *dev,
648 const struct intel_limit *limit,
649 const struct dpll *clock)
650 {
651 if (clock->n < limit->n.min || limit->n.max < clock->n)
652 INTELPllInvalid("n out of range\n");
653 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
654 INTELPllInvalid("p1 out of range\n");
655 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
656 INTELPllInvalid("m2 out of range\n");
657 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
658 INTELPllInvalid("m1 out of range\n");
659
660 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
661 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
662 if (clock->m1 <= clock->m2)
663 INTELPllInvalid("m1 <= m2\n");
664
665 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
666 if (clock->p < limit->p.min || limit->p.max < clock->p)
667 INTELPllInvalid("p out of range\n");
668 if (clock->m < limit->m.min || limit->m.max < clock->m)
669 INTELPllInvalid("m out of range\n");
670 }
671
672 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
673 INTELPllInvalid("vco out of range\n");
674 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
675 * connector, etc., rather than just a single range.
676 */
677 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
678 INTELPllInvalid("dot out of range\n");
679
680 return true;
681 }
682
683 static int
684 i9xx_select_p2_div(const struct intel_limit *limit,
685 const struct intel_crtc_state *crtc_state,
686 int target)
687 {
688 struct drm_device *dev = crtc_state->base.crtc->dev;
689
690 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
691 /*
692 * For LVDS just rely on its current settings for dual-channel.
693 * We haven't figured out how to reliably set up different
694 * single/dual channel state, if we even can.
695 */
696 if (intel_is_dual_link_lvds(dev))
697 return limit->p2.p2_fast;
698 else
699 return limit->p2.p2_slow;
700 } else {
701 if (target < limit->p2.dot_limit)
702 return limit->p2.p2_slow;
703 else
704 return limit->p2.p2_fast;
705 }
706 }
707
708 /*
709 * Returns a set of divisors for the desired target clock with the given
710 * refclk, or FALSE. The returned values represent the clock equation:
711 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
712 *
713 * Target and reference clocks are specified in kHz.
714 *
715 * If match_clock is provided, then best_clock P divider must match the P
716 * divider from @match_clock used for LVDS downclocking.
717 */
718 static bool
719 i9xx_find_best_dpll(const struct intel_limit *limit,
720 struct intel_crtc_state *crtc_state,
721 int target, int refclk, struct dpll *match_clock,
722 struct dpll *best_clock)
723 {
724 struct drm_device *dev = crtc_state->base.crtc->dev;
725 struct dpll clock;
726 int err = target;
727
728 memset(best_clock, 0, sizeof(*best_clock));
729
730 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
731
732 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
733 clock.m1++) {
734 for (clock.m2 = limit->m2.min;
735 clock.m2 <= limit->m2.max; clock.m2++) {
736 if (clock.m2 >= clock.m1)
737 break;
738 for (clock.n = limit->n.min;
739 clock.n <= limit->n.max; clock.n++) {
740 for (clock.p1 = limit->p1.min;
741 clock.p1 <= limit->p1.max; clock.p1++) {
742 int this_err;
743
744 i9xx_calc_dpll_params(refclk, &clock);
745 if (!intel_PLL_is_valid(dev, limit,
746 &clock))
747 continue;
748 if (match_clock &&
749 clock.p != match_clock->p)
750 continue;
751
752 this_err = abs(clock.dot - target);
753 if (this_err < err) {
754 *best_clock = clock;
755 err = this_err;
756 }
757 }
758 }
759 }
760 }
761
762 return (err != target);
763 }
764
765 /*
766 * Returns a set of divisors for the desired target clock with the given
767 * refclk, or FALSE. The returned values represent the clock equation:
768 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
769 *
770 * Target and reference clocks are specified in kHz.
771 *
772 * If match_clock is provided, then best_clock P divider must match the P
773 * divider from @match_clock used for LVDS downclocking.
774 */
775 static bool
776 pnv_find_best_dpll(const struct intel_limit *limit,
777 struct intel_crtc_state *crtc_state,
778 int target, int refclk, struct dpll *match_clock,
779 struct dpll *best_clock)
780 {
781 struct drm_device *dev = crtc_state->base.crtc->dev;
782 struct dpll clock;
783 int err = target;
784
785 memset(best_clock, 0, sizeof(*best_clock));
786
787 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
788
789 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
790 clock.m1++) {
791 for (clock.m2 = limit->m2.min;
792 clock.m2 <= limit->m2.max; clock.m2++) {
793 for (clock.n = limit->n.min;
794 clock.n <= limit->n.max; clock.n++) {
795 for (clock.p1 = limit->p1.min;
796 clock.p1 <= limit->p1.max; clock.p1++) {
797 int this_err;
798
799 pnv_calc_dpll_params(refclk, &clock);
800 if (!intel_PLL_is_valid(dev, limit,
801 &clock))
802 continue;
803 if (match_clock &&
804 clock.p != match_clock->p)
805 continue;
806
807 this_err = abs(clock.dot - target);
808 if (this_err < err) {
809 *best_clock = clock;
810 err = this_err;
811 }
812 }
813 }
814 }
815 }
816
817 return (err != target);
818 }
819
820 /*
821 * Returns a set of divisors for the desired target clock with the given
822 * refclk, or FALSE. The returned values represent the clock equation:
823 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
824 *
825 * Target and reference clocks are specified in kHz.
826 *
827 * If match_clock is provided, then best_clock P divider must match the P
828 * divider from @match_clock used for LVDS downclocking.
829 */
830 static bool
831 g4x_find_best_dpll(const struct intel_limit *limit,
832 struct intel_crtc_state *crtc_state,
833 int target, int refclk, struct dpll *match_clock,
834 struct dpll *best_clock)
835 {
836 struct drm_device *dev = crtc_state->base.crtc->dev;
837 struct dpll clock;
838 int max_n;
839 bool found = false;
840 /* approximately equals target * 0.00585 */
841 int err_most = (target >> 8) + (target >> 9);
842
843 memset(best_clock, 0, sizeof(*best_clock));
844
845 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
846
847 max_n = limit->n.max;
848 /* based on hardware requirement, prefer smaller n to precision */
849 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
850 /* based on hardware requirement, prefere larger m1,m2 */
851 for (clock.m1 = limit->m1.max;
852 clock.m1 >= limit->m1.min; clock.m1--) {
853 for (clock.m2 = limit->m2.max;
854 clock.m2 >= limit->m2.min; clock.m2--) {
855 for (clock.p1 = limit->p1.max;
856 clock.p1 >= limit->p1.min; clock.p1--) {
857 int this_err;
858
859 i9xx_calc_dpll_params(refclk, &clock);
860 if (!intel_PLL_is_valid(dev, limit,
861 &clock))
862 continue;
863
864 this_err = abs(clock.dot - target);
865 if (this_err < err_most) {
866 *best_clock = clock;
867 err_most = this_err;
868 max_n = clock.n;
869 found = true;
870 }
871 }
872 }
873 }
874 }
875 return found;
876 }
877
878 /*
879 * Check if the calculated PLL configuration is more optimal compared to the
880 * best configuration and error found so far. Return the calculated error.
881 */
882 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
883 const struct dpll *calculated_clock,
884 const struct dpll *best_clock,
885 unsigned int best_error_ppm,
886 unsigned int *error_ppm)
887 {
888 /*
889 * For CHV ignore the error and consider only the P value.
890 * Prefer a bigger P value based on HW requirements.
891 */
892 if (IS_CHERRYVIEW(dev)) {
893 *error_ppm = 0;
894
895 return calculated_clock->p > best_clock->p;
896 }
897
898 if (WARN_ON_ONCE(!target_freq))
899 return false;
900
901 *error_ppm = div_u64(1000000ULL *
902 abs(target_freq - calculated_clock->dot),
903 target_freq);
904 /*
905 * Prefer a better P value over a better (smaller) error if the error
906 * is small. Ensure this preference for future configurations too by
907 * setting the error to 0.
908 */
909 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
910 *error_ppm = 0;
911
912 return true;
913 }
914
915 return *error_ppm + 10 < best_error_ppm;
916 }
917
918 /*
919 * Returns a set of divisors for the desired target clock with the given
920 * refclk, or FALSE. The returned values represent the clock equation:
921 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
922 */
923 static bool
924 vlv_find_best_dpll(const struct intel_limit *limit,
925 struct intel_crtc_state *crtc_state,
926 int target, int refclk, struct dpll *match_clock,
927 struct dpll *best_clock)
928 {
929 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
930 struct drm_device *dev = crtc->base.dev;
931 struct dpll clock;
932 unsigned int bestppm = 1000000;
933 /* min update 19.2 MHz */
934 int max_n = min(limit->n.max, refclk / 19200);
935 bool found = false;
936
937 target *= 5; /* fast clock */
938
939 memset(best_clock, 0, sizeof(*best_clock));
940
941 /* based on hardware requirement, prefer smaller n to precision */
942 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
943 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
944 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
945 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
946 clock.p = clock.p1 * clock.p2;
947 /* based on hardware requirement, prefer bigger m1,m2 values */
948 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
949 unsigned int ppm;
950
951 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
952 refclk * clock.m1);
953
954 vlv_calc_dpll_params(refclk, &clock);
955
956 if (!intel_PLL_is_valid(dev, limit,
957 &clock))
958 continue;
959
960 if (!vlv_PLL_is_optimal(dev, target,
961 &clock,
962 best_clock,
963 bestppm, &ppm))
964 continue;
965
966 *best_clock = clock;
967 bestppm = ppm;
968 found = true;
969 }
970 }
971 }
972 }
973
974 return found;
975 }
976
977 /*
978 * Returns a set of divisors for the desired target clock with the given
979 * refclk, or FALSE. The returned values represent the clock equation:
980 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
981 */
982 static bool
983 chv_find_best_dpll(const struct intel_limit *limit,
984 struct intel_crtc_state *crtc_state,
985 int target, int refclk, struct dpll *match_clock,
986 struct dpll *best_clock)
987 {
988 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
989 struct drm_device *dev = crtc->base.dev;
990 unsigned int best_error_ppm;
991 struct dpll clock;
992 uint64_t m2;
993 int found = false;
994
995 memset(best_clock, 0, sizeof(*best_clock));
996 best_error_ppm = 1000000;
997
998 /*
999 * Based on hardware doc, the n always set to 1, and m1 always
1000 * set to 2. If requires to support 200Mhz refclk, we need to
1001 * revisit this because n may not 1 anymore.
1002 */
1003 clock.n = 1, clock.m1 = 2;
1004 target *= 5; /* fast clock */
1005
1006 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1007 for (clock.p2 = limit->p2.p2_fast;
1008 clock.p2 >= limit->p2.p2_slow;
1009 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1010 unsigned int error_ppm;
1011
1012 clock.p = clock.p1 * clock.p2;
1013
1014 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1015 clock.n) << 22, refclk * clock.m1);
1016
1017 if (m2 > INT_MAX/clock.m1)
1018 continue;
1019
1020 clock.m2 = m2;
1021
1022 chv_calc_dpll_params(refclk, &clock);
1023
1024 if (!intel_PLL_is_valid(dev, limit, &clock))
1025 continue;
1026
1027 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1028 best_error_ppm, &error_ppm))
1029 continue;
1030
1031 *best_clock = clock;
1032 best_error_ppm = error_ppm;
1033 found = true;
1034 }
1035 }
1036
1037 return found;
1038 }
1039
1040 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1041 struct dpll *best_clock)
1042 {
1043 int refclk = 100000;
1044 const struct intel_limit *limit = &intel_limits_bxt;
1045
1046 return chv_find_best_dpll(limit, crtc_state,
1047 target_clock, refclk, NULL, best_clock);
1048 }
1049
1050 bool intel_crtc_active(struct drm_crtc *crtc)
1051 {
1052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1053
1054 /* Be paranoid as we can arrive here with only partial
1055 * state retrieved from the hardware during setup.
1056 *
1057 * We can ditch the adjusted_mode.crtc_clock check as soon
1058 * as Haswell has gained clock readout/fastboot support.
1059 *
1060 * We can ditch the crtc->primary->fb check as soon as we can
1061 * properly reconstruct framebuffers.
1062 *
1063 * FIXME: The intel_crtc->active here should be switched to
1064 * crtc->state->active once we have proper CRTC states wired up
1065 * for atomic.
1066 */
1067 return intel_crtc->active && crtc->primary->state->fb &&
1068 intel_crtc->config->base.adjusted_mode.crtc_clock;
1069 }
1070
1071 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1072 enum pipe pipe)
1073 {
1074 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1076
1077 return intel_crtc->config->cpu_transcoder;
1078 }
1079
1080 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1081 {
1082 struct drm_i915_private *dev_priv = dev->dev_private;
1083 i915_reg_t reg = PIPEDSL(pipe);
1084 u32 line1, line2;
1085 u32 line_mask;
1086
1087 if (IS_GEN2(dev))
1088 line_mask = DSL_LINEMASK_GEN2;
1089 else
1090 line_mask = DSL_LINEMASK_GEN3;
1091
1092 line1 = I915_READ(reg) & line_mask;
1093 msleep(5);
1094 line2 = I915_READ(reg) & line_mask;
1095
1096 return line1 == line2;
1097 }
1098
1099 /*
1100 * intel_wait_for_pipe_off - wait for pipe to turn off
1101 * @crtc: crtc whose pipe to wait for
1102 *
1103 * After disabling a pipe, we can't wait for vblank in the usual way,
1104 * spinning on the vblank interrupt status bit, since we won't actually
1105 * see an interrupt when the pipe is disabled.
1106 *
1107 * On Gen4 and above:
1108 * wait for the pipe register state bit to turn off
1109 *
1110 * Otherwise:
1111 * wait for the display line value to settle (it usually
1112 * ends up stopping at the start of the next frame).
1113 *
1114 */
1115 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1116 {
1117 struct drm_device *dev = crtc->base.dev;
1118 struct drm_i915_private *dev_priv = dev->dev_private;
1119 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1120 enum pipe pipe = crtc->pipe;
1121
1122 if (INTEL_INFO(dev)->gen >= 4) {
1123 i915_reg_t reg = PIPECONF(cpu_transcoder);
1124
1125 /* Wait for the Pipe State to go off */
1126 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1127 100))
1128 WARN(1, "pipe_off wait timed out\n");
1129 } else {
1130 /* Wait for the display line to settle */
1131 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1132 WARN(1, "pipe_off wait timed out\n");
1133 }
1134 }
1135
1136 /* Only for pre-ILK configs */
1137 void assert_pll(struct drm_i915_private *dev_priv,
1138 enum pipe pipe, bool state)
1139 {
1140 u32 val;
1141 bool cur_state;
1142
1143 val = I915_READ(DPLL(pipe));
1144 cur_state = !!(val & DPLL_VCO_ENABLE);
1145 I915_STATE_WARN(cur_state != state,
1146 "PLL state assertion failure (expected %s, current %s)\n",
1147 onoff(state), onoff(cur_state));
1148 }
1149
1150 /* XXX: the dsi pll is shared between MIPI DSI ports */
1151 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1152 {
1153 u32 val;
1154 bool cur_state;
1155
1156 mutex_lock(&dev_priv->sb_lock);
1157 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1158 mutex_unlock(&dev_priv->sb_lock);
1159
1160 cur_state = val & DSI_PLL_VCO_EN;
1161 I915_STATE_WARN(cur_state != state,
1162 "DSI PLL state assertion failure (expected %s, current %s)\n",
1163 onoff(state), onoff(cur_state));
1164 }
1165
1166 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1167 enum pipe pipe, bool state)
1168 {
1169 bool cur_state;
1170 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1171 pipe);
1172
1173 if (HAS_DDI(dev_priv)) {
1174 /* DDI does not have a specific FDI_TX register */
1175 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1176 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1177 } else {
1178 u32 val = I915_READ(FDI_TX_CTL(pipe));
1179 cur_state = !!(val & FDI_TX_ENABLE);
1180 }
1181 I915_STATE_WARN(cur_state != state,
1182 "FDI TX state assertion failure (expected %s, current %s)\n",
1183 onoff(state), onoff(cur_state));
1184 }
1185 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1186 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1187
1188 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1189 enum pipe pipe, bool state)
1190 {
1191 u32 val;
1192 bool cur_state;
1193
1194 val = I915_READ(FDI_RX_CTL(pipe));
1195 cur_state = !!(val & FDI_RX_ENABLE);
1196 I915_STATE_WARN(cur_state != state,
1197 "FDI RX state assertion failure (expected %s, current %s)\n",
1198 onoff(state), onoff(cur_state));
1199 }
1200 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1201 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1202
1203 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1204 enum pipe pipe)
1205 {
1206 u32 val;
1207
1208 /* ILK FDI PLL is always enabled */
1209 if (IS_GEN5(dev_priv))
1210 return;
1211
1212 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1213 if (HAS_DDI(dev_priv))
1214 return;
1215
1216 val = I915_READ(FDI_TX_CTL(pipe));
1217 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1218 }
1219
1220 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1221 enum pipe pipe, bool state)
1222 {
1223 u32 val;
1224 bool cur_state;
1225
1226 val = I915_READ(FDI_RX_CTL(pipe));
1227 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1228 I915_STATE_WARN(cur_state != state,
1229 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1230 onoff(state), onoff(cur_state));
1231 }
1232
1233 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1234 enum pipe pipe)
1235 {
1236 struct drm_device *dev = dev_priv->dev;
1237 i915_reg_t pp_reg;
1238 u32 val;
1239 enum pipe panel_pipe = PIPE_A;
1240 bool locked = true;
1241
1242 if (WARN_ON(HAS_DDI(dev)))
1243 return;
1244
1245 if (HAS_PCH_SPLIT(dev)) {
1246 u32 port_sel;
1247
1248 pp_reg = PCH_PP_CONTROL;
1249 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1250
1251 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1252 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1253 panel_pipe = PIPE_B;
1254 /* XXX: else fix for eDP */
1255 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1256 /* presumably write lock depends on pipe, not port select */
1257 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1258 panel_pipe = pipe;
1259 } else {
1260 pp_reg = PP_CONTROL;
1261 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1262 panel_pipe = PIPE_B;
1263 }
1264
1265 val = I915_READ(pp_reg);
1266 if (!(val & PANEL_POWER_ON) ||
1267 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1268 locked = false;
1269
1270 I915_STATE_WARN(panel_pipe == pipe && locked,
1271 "panel assertion failure, pipe %c regs locked\n",
1272 pipe_name(pipe));
1273 }
1274
1275 static void assert_cursor(struct drm_i915_private *dev_priv,
1276 enum pipe pipe, bool state)
1277 {
1278 struct drm_device *dev = dev_priv->dev;
1279 bool cur_state;
1280
1281 if (IS_845G(dev) || IS_I865G(dev))
1282 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1283 else
1284 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1285
1286 I915_STATE_WARN(cur_state != state,
1287 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1288 pipe_name(pipe), onoff(state), onoff(cur_state));
1289 }
1290 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1291 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1292
1293 void assert_pipe(struct drm_i915_private *dev_priv,
1294 enum pipe pipe, bool state)
1295 {
1296 bool cur_state;
1297 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1298 pipe);
1299 enum intel_display_power_domain power_domain;
1300
1301 /* if we need the pipe quirk it must be always on */
1302 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1303 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1304 state = true;
1305
1306 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1307 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1308 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1309 cur_state = !!(val & PIPECONF_ENABLE);
1310
1311 intel_display_power_put(dev_priv, power_domain);
1312 } else {
1313 cur_state = false;
1314 }
1315
1316 I915_STATE_WARN(cur_state != state,
1317 "pipe %c assertion failure (expected %s, current %s)\n",
1318 pipe_name(pipe), onoff(state), onoff(cur_state));
1319 }
1320
1321 static void assert_plane(struct drm_i915_private *dev_priv,
1322 enum plane plane, bool state)
1323 {
1324 u32 val;
1325 bool cur_state;
1326
1327 val = I915_READ(DSPCNTR(plane));
1328 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1329 I915_STATE_WARN(cur_state != state,
1330 "plane %c assertion failure (expected %s, current %s)\n",
1331 plane_name(plane), onoff(state), onoff(cur_state));
1332 }
1333
1334 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1335 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1336
1337 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1338 enum pipe pipe)
1339 {
1340 struct drm_device *dev = dev_priv->dev;
1341 int i;
1342
1343 /* Primary planes are fixed to pipes on gen4+ */
1344 if (INTEL_INFO(dev)->gen >= 4) {
1345 u32 val = I915_READ(DSPCNTR(pipe));
1346 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1347 "plane %c assertion failure, should be disabled but not\n",
1348 plane_name(pipe));
1349 return;
1350 }
1351
1352 /* Need to check both planes against the pipe */
1353 for_each_pipe(dev_priv, i) {
1354 u32 val = I915_READ(DSPCNTR(i));
1355 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1356 DISPPLANE_SEL_PIPE_SHIFT;
1357 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1358 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1359 plane_name(i), pipe_name(pipe));
1360 }
1361 }
1362
1363 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1364 enum pipe pipe)
1365 {
1366 struct drm_device *dev = dev_priv->dev;
1367 int sprite;
1368
1369 if (INTEL_INFO(dev)->gen >= 9) {
1370 for_each_sprite(dev_priv, pipe, sprite) {
1371 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1372 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1373 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1374 sprite, pipe_name(pipe));
1375 }
1376 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1377 for_each_sprite(dev_priv, pipe, sprite) {
1378 u32 val = I915_READ(SPCNTR(pipe, sprite));
1379 I915_STATE_WARN(val & SP_ENABLE,
1380 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1381 sprite_name(pipe, sprite), pipe_name(pipe));
1382 }
1383 } else if (INTEL_INFO(dev)->gen >= 7) {
1384 u32 val = I915_READ(SPRCTL(pipe));
1385 I915_STATE_WARN(val & SPRITE_ENABLE,
1386 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1387 plane_name(pipe), pipe_name(pipe));
1388 } else if (INTEL_INFO(dev)->gen >= 5) {
1389 u32 val = I915_READ(DVSCNTR(pipe));
1390 I915_STATE_WARN(val & DVS_ENABLE,
1391 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1392 plane_name(pipe), pipe_name(pipe));
1393 }
1394 }
1395
1396 static void assert_vblank_disabled(struct drm_crtc *crtc)
1397 {
1398 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1399 drm_crtc_vblank_put(crtc);
1400 }
1401
1402 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1403 enum pipe pipe)
1404 {
1405 u32 val;
1406 bool enabled;
1407
1408 val = I915_READ(PCH_TRANSCONF(pipe));
1409 enabled = !!(val & TRANS_ENABLE);
1410 I915_STATE_WARN(enabled,
1411 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1412 pipe_name(pipe));
1413 }
1414
1415 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1416 enum pipe pipe, u32 port_sel, u32 val)
1417 {
1418 if ((val & DP_PORT_EN) == 0)
1419 return false;
1420
1421 if (HAS_PCH_CPT(dev_priv)) {
1422 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1423 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1424 return false;
1425 } else if (IS_CHERRYVIEW(dev_priv)) {
1426 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1427 return false;
1428 } else {
1429 if ((val & DP_PIPE_MASK) != (pipe << 30))
1430 return false;
1431 }
1432 return true;
1433 }
1434
1435 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1436 enum pipe pipe, u32 val)
1437 {
1438 if ((val & SDVO_ENABLE) == 0)
1439 return false;
1440
1441 if (HAS_PCH_CPT(dev_priv)) {
1442 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1443 return false;
1444 } else if (IS_CHERRYVIEW(dev_priv)) {
1445 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1446 return false;
1447 } else {
1448 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1449 return false;
1450 }
1451 return true;
1452 }
1453
1454 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1455 enum pipe pipe, u32 val)
1456 {
1457 if ((val & LVDS_PORT_EN) == 0)
1458 return false;
1459
1460 if (HAS_PCH_CPT(dev_priv)) {
1461 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1462 return false;
1463 } else {
1464 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1465 return false;
1466 }
1467 return true;
1468 }
1469
1470 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1471 enum pipe pipe, u32 val)
1472 {
1473 if ((val & ADPA_DAC_ENABLE) == 0)
1474 return false;
1475 if (HAS_PCH_CPT(dev_priv)) {
1476 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1477 return false;
1478 } else {
1479 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1480 return false;
1481 }
1482 return true;
1483 }
1484
1485 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1486 enum pipe pipe, i915_reg_t reg,
1487 u32 port_sel)
1488 {
1489 u32 val = I915_READ(reg);
1490 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1491 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1492 i915_mmio_reg_offset(reg), pipe_name(pipe));
1493
1494 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1495 && (val & DP_PIPEB_SELECT),
1496 "IBX PCH dp port still using transcoder B\n");
1497 }
1498
1499 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1500 enum pipe pipe, i915_reg_t reg)
1501 {
1502 u32 val = I915_READ(reg);
1503 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1504 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1505 i915_mmio_reg_offset(reg), pipe_name(pipe));
1506
1507 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1508 && (val & SDVO_PIPE_B_SELECT),
1509 "IBX PCH hdmi port still using transcoder B\n");
1510 }
1511
1512 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1513 enum pipe pipe)
1514 {
1515 u32 val;
1516
1517 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1518 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1519 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1520
1521 val = I915_READ(PCH_ADPA);
1522 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1523 "PCH VGA enabled on transcoder %c, should be disabled\n",
1524 pipe_name(pipe));
1525
1526 val = I915_READ(PCH_LVDS);
1527 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1528 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1529 pipe_name(pipe));
1530
1531 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1532 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1533 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1534 }
1535
1536 static void _vlv_enable_pll(struct intel_crtc *crtc,
1537 const struct intel_crtc_state *pipe_config)
1538 {
1539 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1540 enum pipe pipe = crtc->pipe;
1541
1542 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1543 POSTING_READ(DPLL(pipe));
1544 udelay(150);
1545
1546 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1547 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1548 }
1549
1550 static void vlv_enable_pll(struct intel_crtc *crtc,
1551 const struct intel_crtc_state *pipe_config)
1552 {
1553 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1554 enum pipe pipe = crtc->pipe;
1555
1556 assert_pipe_disabled(dev_priv, pipe);
1557
1558 /* PLL is protected by panel, make sure we can write it */
1559 assert_panel_unlocked(dev_priv, pipe);
1560
1561 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1562 _vlv_enable_pll(crtc, pipe_config);
1563
1564 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1565 POSTING_READ(DPLL_MD(pipe));
1566 }
1567
1568
1569 static void _chv_enable_pll(struct intel_crtc *crtc,
1570 const struct intel_crtc_state *pipe_config)
1571 {
1572 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1573 enum pipe pipe = crtc->pipe;
1574 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1575 u32 tmp;
1576
1577 mutex_lock(&dev_priv->sb_lock);
1578
1579 /* Enable back the 10bit clock to display controller */
1580 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1581 tmp |= DPIO_DCLKP_EN;
1582 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1583
1584 mutex_unlock(&dev_priv->sb_lock);
1585
1586 /*
1587 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1588 */
1589 udelay(1);
1590
1591 /* Enable PLL */
1592 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1593
1594 /* Check PLL is locked */
1595 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1596 DRM_ERROR("PLL %d failed to lock\n", pipe);
1597 }
1598
1599 static void chv_enable_pll(struct intel_crtc *crtc,
1600 const struct intel_crtc_state *pipe_config)
1601 {
1602 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1603 enum pipe pipe = crtc->pipe;
1604
1605 assert_pipe_disabled(dev_priv, pipe);
1606
1607 /* PLL is protected by panel, make sure we can write it */
1608 assert_panel_unlocked(dev_priv, pipe);
1609
1610 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1611 _chv_enable_pll(crtc, pipe_config);
1612
1613 if (pipe != PIPE_A) {
1614 /*
1615 * WaPixelRepeatModeFixForC0:chv
1616 *
1617 * DPLLCMD is AWOL. Use chicken bits to propagate
1618 * the value from DPLLBMD to either pipe B or C.
1619 */
1620 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1621 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1622 I915_WRITE(CBR4_VLV, 0);
1623 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1624
1625 /*
1626 * DPLLB VGA mode also seems to cause problems.
1627 * We should always have it disabled.
1628 */
1629 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1630 } else {
1631 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1632 POSTING_READ(DPLL_MD(pipe));
1633 }
1634 }
1635
1636 static int intel_num_dvo_pipes(struct drm_device *dev)
1637 {
1638 struct intel_crtc *crtc;
1639 int count = 0;
1640
1641 for_each_intel_crtc(dev, crtc)
1642 count += crtc->base.state->active &&
1643 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1644
1645 return count;
1646 }
1647
1648 static void i9xx_enable_pll(struct intel_crtc *crtc)
1649 {
1650 struct drm_device *dev = crtc->base.dev;
1651 struct drm_i915_private *dev_priv = dev->dev_private;
1652 i915_reg_t reg = DPLL(crtc->pipe);
1653 u32 dpll = crtc->config->dpll_hw_state.dpll;
1654
1655 assert_pipe_disabled(dev_priv, crtc->pipe);
1656
1657 /* PLL is protected by panel, make sure we can write it */
1658 if (IS_MOBILE(dev) && !IS_I830(dev))
1659 assert_panel_unlocked(dev_priv, crtc->pipe);
1660
1661 /* Enable DVO 2x clock on both PLLs if necessary */
1662 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1663 /*
1664 * It appears to be important that we don't enable this
1665 * for the current pipe before otherwise configuring the
1666 * PLL. No idea how this should be handled if multiple
1667 * DVO outputs are enabled simultaneosly.
1668 */
1669 dpll |= DPLL_DVO_2X_MODE;
1670 I915_WRITE(DPLL(!crtc->pipe),
1671 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1672 }
1673
1674 /*
1675 * Apparently we need to have VGA mode enabled prior to changing
1676 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1677 * dividers, even though the register value does change.
1678 */
1679 I915_WRITE(reg, 0);
1680
1681 I915_WRITE(reg, dpll);
1682
1683 /* Wait for the clocks to stabilize. */
1684 POSTING_READ(reg);
1685 udelay(150);
1686
1687 if (INTEL_INFO(dev)->gen >= 4) {
1688 I915_WRITE(DPLL_MD(crtc->pipe),
1689 crtc->config->dpll_hw_state.dpll_md);
1690 } else {
1691 /* The pixel multiplier can only be updated once the
1692 * DPLL is enabled and the clocks are stable.
1693 *
1694 * So write it again.
1695 */
1696 I915_WRITE(reg, dpll);
1697 }
1698
1699 /* We do this three times for luck */
1700 I915_WRITE(reg, dpll);
1701 POSTING_READ(reg);
1702 udelay(150); /* wait for warmup */
1703 I915_WRITE(reg, dpll);
1704 POSTING_READ(reg);
1705 udelay(150); /* wait for warmup */
1706 I915_WRITE(reg, dpll);
1707 POSTING_READ(reg);
1708 udelay(150); /* wait for warmup */
1709 }
1710
1711 /**
1712 * i9xx_disable_pll - disable a PLL
1713 * @dev_priv: i915 private structure
1714 * @pipe: pipe PLL to disable
1715 *
1716 * Disable the PLL for @pipe, making sure the pipe is off first.
1717 *
1718 * Note! This is for pre-ILK only.
1719 */
1720 static void i9xx_disable_pll(struct intel_crtc *crtc)
1721 {
1722 struct drm_device *dev = crtc->base.dev;
1723 struct drm_i915_private *dev_priv = dev->dev_private;
1724 enum pipe pipe = crtc->pipe;
1725
1726 /* Disable DVO 2x clock on both PLLs if necessary */
1727 if (IS_I830(dev) &&
1728 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1729 !intel_num_dvo_pipes(dev)) {
1730 I915_WRITE(DPLL(PIPE_B),
1731 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1732 I915_WRITE(DPLL(PIPE_A),
1733 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1734 }
1735
1736 /* Don't disable pipe or pipe PLLs if needed */
1737 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1738 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1739 return;
1740
1741 /* Make sure the pipe isn't still relying on us */
1742 assert_pipe_disabled(dev_priv, pipe);
1743
1744 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1745 POSTING_READ(DPLL(pipe));
1746 }
1747
1748 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1749 {
1750 u32 val;
1751
1752 /* Make sure the pipe isn't still relying on us */
1753 assert_pipe_disabled(dev_priv, pipe);
1754
1755 val = DPLL_INTEGRATED_REF_CLK_VLV |
1756 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1757 if (pipe != PIPE_A)
1758 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1759
1760 I915_WRITE(DPLL(pipe), val);
1761 POSTING_READ(DPLL(pipe));
1762 }
1763
1764 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1765 {
1766 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1767 u32 val;
1768
1769 /* Make sure the pipe isn't still relying on us */
1770 assert_pipe_disabled(dev_priv, pipe);
1771
1772 val = DPLL_SSC_REF_CLK_CHV |
1773 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1774 if (pipe != PIPE_A)
1775 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1776
1777 I915_WRITE(DPLL(pipe), val);
1778 POSTING_READ(DPLL(pipe));
1779
1780 mutex_lock(&dev_priv->sb_lock);
1781
1782 /* Disable 10bit clock to display controller */
1783 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1784 val &= ~DPIO_DCLKP_EN;
1785 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1786
1787 mutex_unlock(&dev_priv->sb_lock);
1788 }
1789
1790 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1791 struct intel_digital_port *dport,
1792 unsigned int expected_mask)
1793 {
1794 u32 port_mask;
1795 i915_reg_t dpll_reg;
1796
1797 switch (dport->port) {
1798 case PORT_B:
1799 port_mask = DPLL_PORTB_READY_MASK;
1800 dpll_reg = DPLL(0);
1801 break;
1802 case PORT_C:
1803 port_mask = DPLL_PORTC_READY_MASK;
1804 dpll_reg = DPLL(0);
1805 expected_mask <<= 4;
1806 break;
1807 case PORT_D:
1808 port_mask = DPLL_PORTD_READY_MASK;
1809 dpll_reg = DPIO_PHY_STATUS;
1810 break;
1811 default:
1812 BUG();
1813 }
1814
1815 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1816 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1817 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1818 }
1819
1820 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1821 enum pipe pipe)
1822 {
1823 struct drm_device *dev = dev_priv->dev;
1824 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1826 i915_reg_t reg;
1827 uint32_t val, pipeconf_val;
1828
1829 /* Make sure PCH DPLL is enabled */
1830 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1831
1832 /* FDI must be feeding us bits for PCH ports */
1833 assert_fdi_tx_enabled(dev_priv, pipe);
1834 assert_fdi_rx_enabled(dev_priv, pipe);
1835
1836 if (HAS_PCH_CPT(dev)) {
1837 /* Workaround: Set the timing override bit before enabling the
1838 * pch transcoder. */
1839 reg = TRANS_CHICKEN2(pipe);
1840 val = I915_READ(reg);
1841 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1842 I915_WRITE(reg, val);
1843 }
1844
1845 reg = PCH_TRANSCONF(pipe);
1846 val = I915_READ(reg);
1847 pipeconf_val = I915_READ(PIPECONF(pipe));
1848
1849 if (HAS_PCH_IBX(dev_priv)) {
1850 /*
1851 * Make the BPC in transcoder be consistent with
1852 * that in pipeconf reg. For HDMI we must use 8bpc
1853 * here for both 8bpc and 12bpc.
1854 */
1855 val &= ~PIPECONF_BPC_MASK;
1856 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1857 val |= PIPECONF_8BPC;
1858 else
1859 val |= pipeconf_val & PIPECONF_BPC_MASK;
1860 }
1861
1862 val &= ~TRANS_INTERLACE_MASK;
1863 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1864 if (HAS_PCH_IBX(dev_priv) &&
1865 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1866 val |= TRANS_LEGACY_INTERLACED_ILK;
1867 else
1868 val |= TRANS_INTERLACED;
1869 else
1870 val |= TRANS_PROGRESSIVE;
1871
1872 I915_WRITE(reg, val | TRANS_ENABLE);
1873 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1874 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1875 }
1876
1877 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1878 enum transcoder cpu_transcoder)
1879 {
1880 u32 val, pipeconf_val;
1881
1882 /* FDI must be feeding us bits for PCH ports */
1883 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1884 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1885
1886 /* Workaround: set timing override bit. */
1887 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1888 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1889 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1890
1891 val = TRANS_ENABLE;
1892 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1893
1894 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1895 PIPECONF_INTERLACED_ILK)
1896 val |= TRANS_INTERLACED;
1897 else
1898 val |= TRANS_PROGRESSIVE;
1899
1900 I915_WRITE(LPT_TRANSCONF, val);
1901 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1902 DRM_ERROR("Failed to enable PCH transcoder\n");
1903 }
1904
1905 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1906 enum pipe pipe)
1907 {
1908 struct drm_device *dev = dev_priv->dev;
1909 i915_reg_t reg;
1910 uint32_t val;
1911
1912 /* FDI relies on the transcoder */
1913 assert_fdi_tx_disabled(dev_priv, pipe);
1914 assert_fdi_rx_disabled(dev_priv, pipe);
1915
1916 /* Ports must be off as well */
1917 assert_pch_ports_disabled(dev_priv, pipe);
1918
1919 reg = PCH_TRANSCONF(pipe);
1920 val = I915_READ(reg);
1921 val &= ~TRANS_ENABLE;
1922 I915_WRITE(reg, val);
1923 /* wait for PCH transcoder off, transcoder state */
1924 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1925 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1926
1927 if (HAS_PCH_CPT(dev)) {
1928 /* Workaround: Clear the timing override chicken bit again. */
1929 reg = TRANS_CHICKEN2(pipe);
1930 val = I915_READ(reg);
1931 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1932 I915_WRITE(reg, val);
1933 }
1934 }
1935
1936 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1937 {
1938 u32 val;
1939
1940 val = I915_READ(LPT_TRANSCONF);
1941 val &= ~TRANS_ENABLE;
1942 I915_WRITE(LPT_TRANSCONF, val);
1943 /* wait for PCH transcoder off, transcoder state */
1944 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1945 DRM_ERROR("Failed to disable PCH transcoder\n");
1946
1947 /* Workaround: clear timing override bit. */
1948 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1949 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1950 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1951 }
1952
1953 /**
1954 * intel_enable_pipe - enable a pipe, asserting requirements
1955 * @crtc: crtc responsible for the pipe
1956 *
1957 * Enable @crtc's pipe, making sure that various hardware specific requirements
1958 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1959 */
1960 static void intel_enable_pipe(struct intel_crtc *crtc)
1961 {
1962 struct drm_device *dev = crtc->base.dev;
1963 struct drm_i915_private *dev_priv = dev->dev_private;
1964 enum pipe pipe = crtc->pipe;
1965 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1966 enum pipe pch_transcoder;
1967 i915_reg_t reg;
1968 u32 val;
1969
1970 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1971
1972 assert_planes_disabled(dev_priv, pipe);
1973 assert_cursor_disabled(dev_priv, pipe);
1974 assert_sprites_disabled(dev_priv, pipe);
1975
1976 if (HAS_PCH_LPT(dev_priv))
1977 pch_transcoder = TRANSCODER_A;
1978 else
1979 pch_transcoder = pipe;
1980
1981 /*
1982 * A pipe without a PLL won't actually be able to drive bits from
1983 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1984 * need the check.
1985 */
1986 if (HAS_GMCH_DISPLAY(dev_priv))
1987 if (crtc->config->has_dsi_encoder)
1988 assert_dsi_pll_enabled(dev_priv);
1989 else
1990 assert_pll_enabled(dev_priv, pipe);
1991 else {
1992 if (crtc->config->has_pch_encoder) {
1993 /* if driving the PCH, we need FDI enabled */
1994 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1995 assert_fdi_tx_pll_enabled(dev_priv,
1996 (enum pipe) cpu_transcoder);
1997 }
1998 /* FIXME: assert CPU port conditions for SNB+ */
1999 }
2000
2001 reg = PIPECONF(cpu_transcoder);
2002 val = I915_READ(reg);
2003 if (val & PIPECONF_ENABLE) {
2004 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2005 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2006 return;
2007 }
2008
2009 I915_WRITE(reg, val | PIPECONF_ENABLE);
2010 POSTING_READ(reg);
2011
2012 /*
2013 * Until the pipe starts DSL will read as 0, which would cause
2014 * an apparent vblank timestamp jump, which messes up also the
2015 * frame count when it's derived from the timestamps. So let's
2016 * wait for the pipe to start properly before we call
2017 * drm_crtc_vblank_on()
2018 */
2019 if (dev->max_vblank_count == 0 &&
2020 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2021 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2022 }
2023
2024 /**
2025 * intel_disable_pipe - disable a pipe, asserting requirements
2026 * @crtc: crtc whose pipes is to be disabled
2027 *
2028 * Disable the pipe of @crtc, making sure that various hardware
2029 * specific requirements are met, if applicable, e.g. plane
2030 * disabled, panel fitter off, etc.
2031 *
2032 * Will wait until the pipe has shut down before returning.
2033 */
2034 static void intel_disable_pipe(struct intel_crtc *crtc)
2035 {
2036 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2037 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2038 enum pipe pipe = crtc->pipe;
2039 i915_reg_t reg;
2040 u32 val;
2041
2042 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2043
2044 /*
2045 * Make sure planes won't keep trying to pump pixels to us,
2046 * or we might hang the display.
2047 */
2048 assert_planes_disabled(dev_priv, pipe);
2049 assert_cursor_disabled(dev_priv, pipe);
2050 assert_sprites_disabled(dev_priv, pipe);
2051
2052 reg = PIPECONF(cpu_transcoder);
2053 val = I915_READ(reg);
2054 if ((val & PIPECONF_ENABLE) == 0)
2055 return;
2056
2057 /*
2058 * Double wide has implications for planes
2059 * so best keep it disabled when not needed.
2060 */
2061 if (crtc->config->double_wide)
2062 val &= ~PIPECONF_DOUBLE_WIDE;
2063
2064 /* Don't disable pipe or pipe PLLs if needed */
2065 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2066 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2067 val &= ~PIPECONF_ENABLE;
2068
2069 I915_WRITE(reg, val);
2070 if ((val & PIPECONF_ENABLE) == 0)
2071 intel_wait_for_pipe_off(crtc);
2072 }
2073
2074 static bool need_vtd_wa(struct drm_device *dev)
2075 {
2076 #ifdef CONFIG_INTEL_IOMMU
2077 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2078 return true;
2079 #endif
2080 return false;
2081 }
2082
2083 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2084 {
2085 return IS_GEN2(dev_priv) ? 2048 : 4096;
2086 }
2087
2088 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2089 uint64_t fb_modifier, unsigned int cpp)
2090 {
2091 switch (fb_modifier) {
2092 case DRM_FORMAT_MOD_NONE:
2093 return cpp;
2094 case I915_FORMAT_MOD_X_TILED:
2095 if (IS_GEN2(dev_priv))
2096 return 128;
2097 else
2098 return 512;
2099 case I915_FORMAT_MOD_Y_TILED:
2100 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2101 return 128;
2102 else
2103 return 512;
2104 case I915_FORMAT_MOD_Yf_TILED:
2105 switch (cpp) {
2106 case 1:
2107 return 64;
2108 case 2:
2109 case 4:
2110 return 128;
2111 case 8:
2112 case 16:
2113 return 256;
2114 default:
2115 MISSING_CASE(cpp);
2116 return cpp;
2117 }
2118 break;
2119 default:
2120 MISSING_CASE(fb_modifier);
2121 return cpp;
2122 }
2123 }
2124
2125 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2126 uint64_t fb_modifier, unsigned int cpp)
2127 {
2128 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2129 return 1;
2130 else
2131 return intel_tile_size(dev_priv) /
2132 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2133 }
2134
2135 /* Return the tile dimensions in pixel units */
2136 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2137 unsigned int *tile_width,
2138 unsigned int *tile_height,
2139 uint64_t fb_modifier,
2140 unsigned int cpp)
2141 {
2142 unsigned int tile_width_bytes =
2143 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2144
2145 *tile_width = tile_width_bytes / cpp;
2146 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2147 }
2148
2149 unsigned int
2150 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2151 uint32_t pixel_format, uint64_t fb_modifier)
2152 {
2153 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2154 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2155
2156 return ALIGN(height, tile_height);
2157 }
2158
2159 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2160 {
2161 unsigned int size = 0;
2162 int i;
2163
2164 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2165 size += rot_info->plane[i].width * rot_info->plane[i].height;
2166
2167 return size;
2168 }
2169
2170 static void
2171 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2172 const struct drm_framebuffer *fb,
2173 unsigned int rotation)
2174 {
2175 if (intel_rotation_90_or_270(rotation)) {
2176 *view = i915_ggtt_view_rotated;
2177 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2178 } else {
2179 *view = i915_ggtt_view_normal;
2180 }
2181 }
2182
2183 static void
2184 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2185 struct drm_framebuffer *fb)
2186 {
2187 struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2188 unsigned int tile_size, tile_width, tile_height, cpp;
2189
2190 tile_size = intel_tile_size(dev_priv);
2191
2192 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2193 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2194 fb->modifier[0], cpp);
2195
2196 info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2197 info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2198
2199 if (info->pixel_format == DRM_FORMAT_NV12) {
2200 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2201 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2202 fb->modifier[1], cpp);
2203
2204 info->uv_offset = fb->offsets[1];
2205 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2206 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2207 }
2208 }
2209
2210 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2211 {
2212 if (INTEL_INFO(dev_priv)->gen >= 9)
2213 return 256 * 1024;
2214 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2215 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2216 return 128 * 1024;
2217 else if (INTEL_INFO(dev_priv)->gen >= 4)
2218 return 4 * 1024;
2219 else
2220 return 0;
2221 }
2222
2223 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2224 uint64_t fb_modifier)
2225 {
2226 switch (fb_modifier) {
2227 case DRM_FORMAT_MOD_NONE:
2228 return intel_linear_alignment(dev_priv);
2229 case I915_FORMAT_MOD_X_TILED:
2230 if (INTEL_INFO(dev_priv)->gen >= 9)
2231 return 256 * 1024;
2232 return 0;
2233 case I915_FORMAT_MOD_Y_TILED:
2234 case I915_FORMAT_MOD_Yf_TILED:
2235 return 1 * 1024 * 1024;
2236 default:
2237 MISSING_CASE(fb_modifier);
2238 return 0;
2239 }
2240 }
2241
2242 int
2243 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2244 unsigned int rotation)
2245 {
2246 struct drm_device *dev = fb->dev;
2247 struct drm_i915_private *dev_priv = dev->dev_private;
2248 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2249 struct i915_ggtt_view view;
2250 u32 alignment;
2251 int ret;
2252
2253 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2254
2255 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2256
2257 intel_fill_fb_ggtt_view(&view, fb, rotation);
2258
2259 /* Note that the w/a also requires 64 PTE of padding following the
2260 * bo. We currently fill all unused PTE with the shadow page and so
2261 * we should always have valid PTE following the scanout preventing
2262 * the VT-d warning.
2263 */
2264 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2265 alignment = 256 * 1024;
2266
2267 /*
2268 * Global gtt pte registers are special registers which actually forward
2269 * writes to a chunk of system memory. Which means that there is no risk
2270 * that the register values disappear as soon as we call
2271 * intel_runtime_pm_put(), so it is correct to wrap only the
2272 * pin/unpin/fence and not more.
2273 */
2274 intel_runtime_pm_get(dev_priv);
2275
2276 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2277 &view);
2278 if (ret)
2279 goto err_pm;
2280
2281 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2282 * fence, whereas 965+ only requires a fence if using
2283 * framebuffer compression. For simplicity, we always install
2284 * a fence as the cost is not that onerous.
2285 */
2286 if (view.type == I915_GGTT_VIEW_NORMAL) {
2287 ret = i915_gem_object_get_fence(obj);
2288 if (ret == -EDEADLK) {
2289 /*
2290 * -EDEADLK means there are no free fences
2291 * no pending flips.
2292 *
2293 * This is propagated to atomic, but it uses
2294 * -EDEADLK to force a locking recovery, so
2295 * change the returned error to -EBUSY.
2296 */
2297 ret = -EBUSY;
2298 goto err_unpin;
2299 } else if (ret)
2300 goto err_unpin;
2301
2302 i915_gem_object_pin_fence(obj);
2303 }
2304
2305 intel_runtime_pm_put(dev_priv);
2306 return 0;
2307
2308 err_unpin:
2309 i915_gem_object_unpin_from_display_plane(obj, &view);
2310 err_pm:
2311 intel_runtime_pm_put(dev_priv);
2312 return ret;
2313 }
2314
2315 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2316 {
2317 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2318 struct i915_ggtt_view view;
2319
2320 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2321
2322 intel_fill_fb_ggtt_view(&view, fb, rotation);
2323
2324 if (view.type == I915_GGTT_VIEW_NORMAL)
2325 i915_gem_object_unpin_fence(obj);
2326
2327 i915_gem_object_unpin_from_display_plane(obj, &view);
2328 }
2329
2330 /*
2331 * Adjust the tile offset by moving the difference into
2332 * the x/y offsets.
2333 *
2334 * Input tile dimensions and pitch must already be
2335 * rotated to match x and y, and in pixel units.
2336 */
2337 static u32 intel_adjust_tile_offset(int *x, int *y,
2338 unsigned int tile_width,
2339 unsigned int tile_height,
2340 unsigned int tile_size,
2341 unsigned int pitch_tiles,
2342 u32 old_offset,
2343 u32 new_offset)
2344 {
2345 unsigned int tiles;
2346
2347 WARN_ON(old_offset & (tile_size - 1));
2348 WARN_ON(new_offset & (tile_size - 1));
2349 WARN_ON(new_offset > old_offset);
2350
2351 tiles = (old_offset - new_offset) / tile_size;
2352
2353 *y += tiles / pitch_tiles * tile_height;
2354 *x += tiles % pitch_tiles * tile_width;
2355
2356 return new_offset;
2357 }
2358
2359 /*
2360 * Computes the linear offset to the base tile and adjusts
2361 * x, y. bytes per pixel is assumed to be a power-of-two.
2362 *
2363 * In the 90/270 rotated case, x and y are assumed
2364 * to be already rotated to match the rotated GTT view, and
2365 * pitch is the tile_height aligned framebuffer height.
2366 */
2367 u32 intel_compute_tile_offset(int *x, int *y,
2368 const struct drm_framebuffer *fb, int plane,
2369 unsigned int pitch,
2370 unsigned int rotation)
2371 {
2372 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2373 uint64_t fb_modifier = fb->modifier[plane];
2374 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2375 u32 offset, offset_aligned, alignment;
2376
2377 alignment = intel_surf_alignment(dev_priv, fb_modifier);
2378 if (alignment)
2379 alignment--;
2380
2381 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2382 unsigned int tile_size, tile_width, tile_height;
2383 unsigned int tile_rows, tiles, pitch_tiles;
2384
2385 tile_size = intel_tile_size(dev_priv);
2386 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2387 fb_modifier, cpp);
2388
2389 if (intel_rotation_90_or_270(rotation)) {
2390 pitch_tiles = pitch / tile_height;
2391 swap(tile_width, tile_height);
2392 } else {
2393 pitch_tiles = pitch / (tile_width * cpp);
2394 }
2395
2396 tile_rows = *y / tile_height;
2397 *y %= tile_height;
2398
2399 tiles = *x / tile_width;
2400 *x %= tile_width;
2401
2402 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2403 offset_aligned = offset & ~alignment;
2404
2405 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2406 tile_size, pitch_tiles,
2407 offset, offset_aligned);
2408 } else {
2409 offset = *y * pitch + *x * cpp;
2410 offset_aligned = offset & ~alignment;
2411
2412 *y = (offset & alignment) / pitch;
2413 *x = ((offset & alignment) - *y * pitch) / cpp;
2414 }
2415
2416 return offset_aligned;
2417 }
2418
2419 static int i9xx_format_to_fourcc(int format)
2420 {
2421 switch (format) {
2422 case DISPPLANE_8BPP:
2423 return DRM_FORMAT_C8;
2424 case DISPPLANE_BGRX555:
2425 return DRM_FORMAT_XRGB1555;
2426 case DISPPLANE_BGRX565:
2427 return DRM_FORMAT_RGB565;
2428 default:
2429 case DISPPLANE_BGRX888:
2430 return DRM_FORMAT_XRGB8888;
2431 case DISPPLANE_RGBX888:
2432 return DRM_FORMAT_XBGR8888;
2433 case DISPPLANE_BGRX101010:
2434 return DRM_FORMAT_XRGB2101010;
2435 case DISPPLANE_RGBX101010:
2436 return DRM_FORMAT_XBGR2101010;
2437 }
2438 }
2439
2440 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2441 {
2442 switch (format) {
2443 case PLANE_CTL_FORMAT_RGB_565:
2444 return DRM_FORMAT_RGB565;
2445 default:
2446 case PLANE_CTL_FORMAT_XRGB_8888:
2447 if (rgb_order) {
2448 if (alpha)
2449 return DRM_FORMAT_ABGR8888;
2450 else
2451 return DRM_FORMAT_XBGR8888;
2452 } else {
2453 if (alpha)
2454 return DRM_FORMAT_ARGB8888;
2455 else
2456 return DRM_FORMAT_XRGB8888;
2457 }
2458 case PLANE_CTL_FORMAT_XRGB_2101010:
2459 if (rgb_order)
2460 return DRM_FORMAT_XBGR2101010;
2461 else
2462 return DRM_FORMAT_XRGB2101010;
2463 }
2464 }
2465
2466 static bool
2467 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2468 struct intel_initial_plane_config *plane_config)
2469 {
2470 struct drm_device *dev = crtc->base.dev;
2471 struct drm_i915_private *dev_priv = to_i915(dev);
2472 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2473 struct drm_i915_gem_object *obj = NULL;
2474 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2475 struct drm_framebuffer *fb = &plane_config->fb->base;
2476 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2477 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2478 PAGE_SIZE);
2479
2480 size_aligned -= base_aligned;
2481
2482 if (plane_config->size == 0)
2483 return false;
2484
2485 /* If the FB is too big, just don't use it since fbdev is not very
2486 * important and we should probably use that space with FBC or other
2487 * features. */
2488 if (size_aligned * 2 > ggtt->stolen_usable_size)
2489 return false;
2490
2491 mutex_lock(&dev->struct_mutex);
2492
2493 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2494 base_aligned,
2495 base_aligned,
2496 size_aligned);
2497 if (!obj) {
2498 mutex_unlock(&dev->struct_mutex);
2499 return false;
2500 }
2501
2502 obj->tiling_mode = plane_config->tiling;
2503 if (obj->tiling_mode == I915_TILING_X)
2504 obj->stride = fb->pitches[0];
2505
2506 mode_cmd.pixel_format = fb->pixel_format;
2507 mode_cmd.width = fb->width;
2508 mode_cmd.height = fb->height;
2509 mode_cmd.pitches[0] = fb->pitches[0];
2510 mode_cmd.modifier[0] = fb->modifier[0];
2511 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2512
2513 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2514 &mode_cmd, obj)) {
2515 DRM_DEBUG_KMS("intel fb init failed\n");
2516 goto out_unref_obj;
2517 }
2518
2519 mutex_unlock(&dev->struct_mutex);
2520
2521 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2522 return true;
2523
2524 out_unref_obj:
2525 drm_gem_object_unreference(&obj->base);
2526 mutex_unlock(&dev->struct_mutex);
2527 return false;
2528 }
2529
2530 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2531 static void
2532 update_state_fb(struct drm_plane *plane)
2533 {
2534 if (plane->fb == plane->state->fb)
2535 return;
2536
2537 if (plane->state->fb)
2538 drm_framebuffer_unreference(plane->state->fb);
2539 plane->state->fb = plane->fb;
2540 if (plane->state->fb)
2541 drm_framebuffer_reference(plane->state->fb);
2542 }
2543
2544 static void
2545 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2546 struct intel_initial_plane_config *plane_config)
2547 {
2548 struct drm_device *dev = intel_crtc->base.dev;
2549 struct drm_i915_private *dev_priv = dev->dev_private;
2550 struct drm_crtc *c;
2551 struct intel_crtc *i;
2552 struct drm_i915_gem_object *obj;
2553 struct drm_plane *primary = intel_crtc->base.primary;
2554 struct drm_plane_state *plane_state = primary->state;
2555 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2556 struct intel_plane *intel_plane = to_intel_plane(primary);
2557 struct intel_plane_state *intel_state =
2558 to_intel_plane_state(plane_state);
2559 struct drm_framebuffer *fb;
2560
2561 if (!plane_config->fb)
2562 return;
2563
2564 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2565 fb = &plane_config->fb->base;
2566 goto valid_fb;
2567 }
2568
2569 kfree(plane_config->fb);
2570
2571 /*
2572 * Failed to alloc the obj, check to see if we should share
2573 * an fb with another CRTC instead
2574 */
2575 for_each_crtc(dev, c) {
2576 i = to_intel_crtc(c);
2577
2578 if (c == &intel_crtc->base)
2579 continue;
2580
2581 if (!i->active)
2582 continue;
2583
2584 fb = c->primary->fb;
2585 if (!fb)
2586 continue;
2587
2588 obj = intel_fb_obj(fb);
2589 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2590 drm_framebuffer_reference(fb);
2591 goto valid_fb;
2592 }
2593 }
2594
2595 /*
2596 * We've failed to reconstruct the BIOS FB. Current display state
2597 * indicates that the primary plane is visible, but has a NULL FB,
2598 * which will lead to problems later if we don't fix it up. The
2599 * simplest solution is to just disable the primary plane now and
2600 * pretend the BIOS never had it enabled.
2601 */
2602 to_intel_plane_state(plane_state)->visible = false;
2603 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2604 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2605 intel_plane->disable_plane(primary, &intel_crtc->base);
2606
2607 return;
2608
2609 valid_fb:
2610 plane_state->src_x = 0;
2611 plane_state->src_y = 0;
2612 plane_state->src_w = fb->width << 16;
2613 plane_state->src_h = fb->height << 16;
2614
2615 plane_state->crtc_x = 0;
2616 plane_state->crtc_y = 0;
2617 plane_state->crtc_w = fb->width;
2618 plane_state->crtc_h = fb->height;
2619
2620 intel_state->src.x1 = plane_state->src_x;
2621 intel_state->src.y1 = plane_state->src_y;
2622 intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2623 intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2624 intel_state->dst.x1 = plane_state->crtc_x;
2625 intel_state->dst.y1 = plane_state->crtc_y;
2626 intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2627 intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2628
2629 obj = intel_fb_obj(fb);
2630 if (obj->tiling_mode != I915_TILING_NONE)
2631 dev_priv->preserve_bios_swizzle = true;
2632
2633 drm_framebuffer_reference(fb);
2634 primary->fb = primary->state->fb = fb;
2635 primary->crtc = primary->state->crtc = &intel_crtc->base;
2636 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2637 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2638 }
2639
2640 static void i9xx_update_primary_plane(struct drm_plane *primary,
2641 const struct intel_crtc_state *crtc_state,
2642 const struct intel_plane_state *plane_state)
2643 {
2644 struct drm_device *dev = primary->dev;
2645 struct drm_i915_private *dev_priv = dev->dev_private;
2646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2647 struct drm_framebuffer *fb = plane_state->base.fb;
2648 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2649 int plane = intel_crtc->plane;
2650 u32 linear_offset;
2651 u32 dspcntr;
2652 i915_reg_t reg = DSPCNTR(plane);
2653 unsigned int rotation = plane_state->base.rotation;
2654 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2655 int x = plane_state->src.x1 >> 16;
2656 int y = plane_state->src.y1 >> 16;
2657
2658 dspcntr = DISPPLANE_GAMMA_ENABLE;
2659
2660 dspcntr |= DISPLAY_PLANE_ENABLE;
2661
2662 if (INTEL_INFO(dev)->gen < 4) {
2663 if (intel_crtc->pipe == PIPE_B)
2664 dspcntr |= DISPPLANE_SEL_PIPE_B;
2665
2666 /* pipesrc and dspsize control the size that is scaled from,
2667 * which should always be the user's requested size.
2668 */
2669 I915_WRITE(DSPSIZE(plane),
2670 ((crtc_state->pipe_src_h - 1) << 16) |
2671 (crtc_state->pipe_src_w - 1));
2672 I915_WRITE(DSPPOS(plane), 0);
2673 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2674 I915_WRITE(PRIMSIZE(plane),
2675 ((crtc_state->pipe_src_h - 1) << 16) |
2676 (crtc_state->pipe_src_w - 1));
2677 I915_WRITE(PRIMPOS(plane), 0);
2678 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2679 }
2680
2681 switch (fb->pixel_format) {
2682 case DRM_FORMAT_C8:
2683 dspcntr |= DISPPLANE_8BPP;
2684 break;
2685 case DRM_FORMAT_XRGB1555:
2686 dspcntr |= DISPPLANE_BGRX555;
2687 break;
2688 case DRM_FORMAT_RGB565:
2689 dspcntr |= DISPPLANE_BGRX565;
2690 break;
2691 case DRM_FORMAT_XRGB8888:
2692 dspcntr |= DISPPLANE_BGRX888;
2693 break;
2694 case DRM_FORMAT_XBGR8888:
2695 dspcntr |= DISPPLANE_RGBX888;
2696 break;
2697 case DRM_FORMAT_XRGB2101010:
2698 dspcntr |= DISPPLANE_BGRX101010;
2699 break;
2700 case DRM_FORMAT_XBGR2101010:
2701 dspcntr |= DISPPLANE_RGBX101010;
2702 break;
2703 default:
2704 BUG();
2705 }
2706
2707 if (INTEL_INFO(dev)->gen >= 4 &&
2708 obj->tiling_mode != I915_TILING_NONE)
2709 dspcntr |= DISPPLANE_TILED;
2710
2711 if (IS_G4X(dev))
2712 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2713
2714 linear_offset = y * fb->pitches[0] + x * cpp;
2715
2716 if (INTEL_INFO(dev)->gen >= 4) {
2717 intel_crtc->dspaddr_offset =
2718 intel_compute_tile_offset(&x, &y, fb, 0,
2719 fb->pitches[0], rotation);
2720 linear_offset -= intel_crtc->dspaddr_offset;
2721 } else {
2722 intel_crtc->dspaddr_offset = linear_offset;
2723 }
2724
2725 if (rotation == BIT(DRM_ROTATE_180)) {
2726 dspcntr |= DISPPLANE_ROTATE_180;
2727
2728 x += (crtc_state->pipe_src_w - 1);
2729 y += (crtc_state->pipe_src_h - 1);
2730
2731 /* Finding the last pixel of the last line of the display
2732 data and adding to linear_offset*/
2733 linear_offset +=
2734 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2735 (crtc_state->pipe_src_w - 1) * cpp;
2736 }
2737
2738 intel_crtc->adjusted_x = x;
2739 intel_crtc->adjusted_y = y;
2740
2741 I915_WRITE(reg, dspcntr);
2742
2743 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2744 if (INTEL_INFO(dev)->gen >= 4) {
2745 I915_WRITE(DSPSURF(plane),
2746 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2747 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2748 I915_WRITE(DSPLINOFF(plane), linear_offset);
2749 } else
2750 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2751 POSTING_READ(reg);
2752 }
2753
2754 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2755 struct drm_crtc *crtc)
2756 {
2757 struct drm_device *dev = crtc->dev;
2758 struct drm_i915_private *dev_priv = dev->dev_private;
2759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2760 int plane = intel_crtc->plane;
2761
2762 I915_WRITE(DSPCNTR(plane), 0);
2763 if (INTEL_INFO(dev_priv)->gen >= 4)
2764 I915_WRITE(DSPSURF(plane), 0);
2765 else
2766 I915_WRITE(DSPADDR(plane), 0);
2767 POSTING_READ(DSPCNTR(plane));
2768 }
2769
2770 static void ironlake_update_primary_plane(struct drm_plane *primary,
2771 const struct intel_crtc_state *crtc_state,
2772 const struct intel_plane_state *plane_state)
2773 {
2774 struct drm_device *dev = primary->dev;
2775 struct drm_i915_private *dev_priv = dev->dev_private;
2776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2777 struct drm_framebuffer *fb = plane_state->base.fb;
2778 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2779 int plane = intel_crtc->plane;
2780 u32 linear_offset;
2781 u32 dspcntr;
2782 i915_reg_t reg = DSPCNTR(plane);
2783 unsigned int rotation = plane_state->base.rotation;
2784 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2785 int x = plane_state->src.x1 >> 16;
2786 int y = plane_state->src.y1 >> 16;
2787
2788 dspcntr = DISPPLANE_GAMMA_ENABLE;
2789 dspcntr |= DISPLAY_PLANE_ENABLE;
2790
2791 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2792 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2793
2794 switch (fb->pixel_format) {
2795 case DRM_FORMAT_C8:
2796 dspcntr |= DISPPLANE_8BPP;
2797 break;
2798 case DRM_FORMAT_RGB565:
2799 dspcntr |= DISPPLANE_BGRX565;
2800 break;
2801 case DRM_FORMAT_XRGB8888:
2802 dspcntr |= DISPPLANE_BGRX888;
2803 break;
2804 case DRM_FORMAT_XBGR8888:
2805 dspcntr |= DISPPLANE_RGBX888;
2806 break;
2807 case DRM_FORMAT_XRGB2101010:
2808 dspcntr |= DISPPLANE_BGRX101010;
2809 break;
2810 case DRM_FORMAT_XBGR2101010:
2811 dspcntr |= DISPPLANE_RGBX101010;
2812 break;
2813 default:
2814 BUG();
2815 }
2816
2817 if (obj->tiling_mode != I915_TILING_NONE)
2818 dspcntr |= DISPPLANE_TILED;
2819
2820 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2821 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2822
2823 linear_offset = y * fb->pitches[0] + x * cpp;
2824 intel_crtc->dspaddr_offset =
2825 intel_compute_tile_offset(&x, &y, fb, 0,
2826 fb->pitches[0], rotation);
2827 linear_offset -= intel_crtc->dspaddr_offset;
2828 if (rotation == BIT(DRM_ROTATE_180)) {
2829 dspcntr |= DISPPLANE_ROTATE_180;
2830
2831 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2832 x += (crtc_state->pipe_src_w - 1);
2833 y += (crtc_state->pipe_src_h - 1);
2834
2835 /* Finding the last pixel of the last line of the display
2836 data and adding to linear_offset*/
2837 linear_offset +=
2838 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2839 (crtc_state->pipe_src_w - 1) * cpp;
2840 }
2841 }
2842
2843 intel_crtc->adjusted_x = x;
2844 intel_crtc->adjusted_y = y;
2845
2846 I915_WRITE(reg, dspcntr);
2847
2848 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2849 I915_WRITE(DSPSURF(plane),
2850 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2851 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2852 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2853 } else {
2854 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2855 I915_WRITE(DSPLINOFF(plane), linear_offset);
2856 }
2857 POSTING_READ(reg);
2858 }
2859
2860 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2861 uint64_t fb_modifier, uint32_t pixel_format)
2862 {
2863 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2864 return 64;
2865 } else {
2866 int cpp = drm_format_plane_cpp(pixel_format, 0);
2867
2868 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2869 }
2870 }
2871
2872 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2873 struct drm_i915_gem_object *obj,
2874 unsigned int plane)
2875 {
2876 struct i915_ggtt_view view;
2877 struct i915_vma *vma;
2878 u64 offset;
2879
2880 intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2881 intel_plane->base.state->rotation);
2882
2883 vma = i915_gem_obj_to_ggtt_view(obj, &view);
2884 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2885 view.type))
2886 return -1;
2887
2888 offset = vma->node.start;
2889
2890 if (plane == 1) {
2891 offset += vma->ggtt_view.params.rotated.uv_start_page *
2892 PAGE_SIZE;
2893 }
2894
2895 WARN_ON(upper_32_bits(offset));
2896
2897 return lower_32_bits(offset);
2898 }
2899
2900 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2901 {
2902 struct drm_device *dev = intel_crtc->base.dev;
2903 struct drm_i915_private *dev_priv = dev->dev_private;
2904
2905 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2906 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2907 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2908 }
2909
2910 /*
2911 * This function detaches (aka. unbinds) unused scalers in hardware
2912 */
2913 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2914 {
2915 struct intel_crtc_scaler_state *scaler_state;
2916 int i;
2917
2918 scaler_state = &intel_crtc->config->scaler_state;
2919
2920 /* loop through and disable scalers that aren't in use */
2921 for (i = 0; i < intel_crtc->num_scalers; i++) {
2922 if (!scaler_state->scalers[i].in_use)
2923 skl_detach_scaler(intel_crtc, i);
2924 }
2925 }
2926
2927 u32 skl_plane_ctl_format(uint32_t pixel_format)
2928 {
2929 switch (pixel_format) {
2930 case DRM_FORMAT_C8:
2931 return PLANE_CTL_FORMAT_INDEXED;
2932 case DRM_FORMAT_RGB565:
2933 return PLANE_CTL_FORMAT_RGB_565;
2934 case DRM_FORMAT_XBGR8888:
2935 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2936 case DRM_FORMAT_XRGB8888:
2937 return PLANE_CTL_FORMAT_XRGB_8888;
2938 /*
2939 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2940 * to be already pre-multiplied. We need to add a knob (or a different
2941 * DRM_FORMAT) for user-space to configure that.
2942 */
2943 case DRM_FORMAT_ABGR8888:
2944 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2945 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2946 case DRM_FORMAT_ARGB8888:
2947 return PLANE_CTL_FORMAT_XRGB_8888 |
2948 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2949 case DRM_FORMAT_XRGB2101010:
2950 return PLANE_CTL_FORMAT_XRGB_2101010;
2951 case DRM_FORMAT_XBGR2101010:
2952 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2953 case DRM_FORMAT_YUYV:
2954 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2955 case DRM_FORMAT_YVYU:
2956 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2957 case DRM_FORMAT_UYVY:
2958 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2959 case DRM_FORMAT_VYUY:
2960 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2961 default:
2962 MISSING_CASE(pixel_format);
2963 }
2964
2965 return 0;
2966 }
2967
2968 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2969 {
2970 switch (fb_modifier) {
2971 case DRM_FORMAT_MOD_NONE:
2972 break;
2973 case I915_FORMAT_MOD_X_TILED:
2974 return PLANE_CTL_TILED_X;
2975 case I915_FORMAT_MOD_Y_TILED:
2976 return PLANE_CTL_TILED_Y;
2977 case I915_FORMAT_MOD_Yf_TILED:
2978 return PLANE_CTL_TILED_YF;
2979 default:
2980 MISSING_CASE(fb_modifier);
2981 }
2982
2983 return 0;
2984 }
2985
2986 u32 skl_plane_ctl_rotation(unsigned int rotation)
2987 {
2988 switch (rotation) {
2989 case BIT(DRM_ROTATE_0):
2990 break;
2991 /*
2992 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2993 * while i915 HW rotation is clockwise, thats why this swapping.
2994 */
2995 case BIT(DRM_ROTATE_90):
2996 return PLANE_CTL_ROTATE_270;
2997 case BIT(DRM_ROTATE_180):
2998 return PLANE_CTL_ROTATE_180;
2999 case BIT(DRM_ROTATE_270):
3000 return PLANE_CTL_ROTATE_90;
3001 default:
3002 MISSING_CASE(rotation);
3003 }
3004
3005 return 0;
3006 }
3007
3008 static void skylake_update_primary_plane(struct drm_plane *plane,
3009 const struct intel_crtc_state *crtc_state,
3010 const struct intel_plane_state *plane_state)
3011 {
3012 struct drm_device *dev = plane->dev;
3013 struct drm_i915_private *dev_priv = dev->dev_private;
3014 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3015 struct drm_framebuffer *fb = plane_state->base.fb;
3016 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3017 int pipe = intel_crtc->pipe;
3018 u32 plane_ctl, stride_div, stride;
3019 u32 tile_height, plane_offset, plane_size;
3020 unsigned int rotation = plane_state->base.rotation;
3021 int x_offset, y_offset;
3022 u32 surf_addr;
3023 int scaler_id = plane_state->scaler_id;
3024 int src_x = plane_state->src.x1 >> 16;
3025 int src_y = plane_state->src.y1 >> 16;
3026 int src_w = drm_rect_width(&plane_state->src) >> 16;
3027 int src_h = drm_rect_height(&plane_state->src) >> 16;
3028 int dst_x = plane_state->dst.x1;
3029 int dst_y = plane_state->dst.y1;
3030 int dst_w = drm_rect_width(&plane_state->dst);
3031 int dst_h = drm_rect_height(&plane_state->dst);
3032
3033 plane_ctl = PLANE_CTL_ENABLE |
3034 PLANE_CTL_PIPE_GAMMA_ENABLE |
3035 PLANE_CTL_PIPE_CSC_ENABLE;
3036
3037 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3038 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3039 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3040 plane_ctl |= skl_plane_ctl_rotation(rotation);
3041
3042 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3043 fb->pixel_format);
3044 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3045
3046 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3047
3048 if (intel_rotation_90_or_270(rotation)) {
3049 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3050
3051 /* stride = Surface height in tiles */
3052 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3053 stride = DIV_ROUND_UP(fb->height, tile_height);
3054 x_offset = stride * tile_height - src_y - src_h;
3055 y_offset = src_x;
3056 plane_size = (src_w - 1) << 16 | (src_h - 1);
3057 } else {
3058 stride = fb->pitches[0] / stride_div;
3059 x_offset = src_x;
3060 y_offset = src_y;
3061 plane_size = (src_h - 1) << 16 | (src_w - 1);
3062 }
3063 plane_offset = y_offset << 16 | x_offset;
3064
3065 intel_crtc->adjusted_x = x_offset;
3066 intel_crtc->adjusted_y = y_offset;
3067
3068 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3069 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3070 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3071 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3072
3073 if (scaler_id >= 0) {
3074 uint32_t ps_ctrl = 0;
3075
3076 WARN_ON(!dst_w || !dst_h);
3077 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3078 crtc_state->scaler_state.scalers[scaler_id].mode;
3079 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3080 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3081 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3082 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3083 I915_WRITE(PLANE_POS(pipe, 0), 0);
3084 } else {
3085 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3086 }
3087
3088 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3089
3090 POSTING_READ(PLANE_SURF(pipe, 0));
3091 }
3092
3093 static void skylake_disable_primary_plane(struct drm_plane *primary,
3094 struct drm_crtc *crtc)
3095 {
3096 struct drm_device *dev = crtc->dev;
3097 struct drm_i915_private *dev_priv = dev->dev_private;
3098 int pipe = to_intel_crtc(crtc)->pipe;
3099
3100 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3101 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3102 POSTING_READ(PLANE_SURF(pipe, 0));
3103 }
3104
3105 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3106 static int
3107 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3108 int x, int y, enum mode_set_atomic state)
3109 {
3110 /* Support for kgdboc is disabled, this needs a major rework. */
3111 DRM_ERROR("legacy panic handler not supported any more.\n");
3112
3113 return -ENODEV;
3114 }
3115
3116 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3117 {
3118 struct intel_crtc *crtc;
3119
3120 for_each_intel_crtc(dev_priv->dev, crtc)
3121 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3122 }
3123
3124 static void intel_update_primary_planes(struct drm_device *dev)
3125 {
3126 struct drm_crtc *crtc;
3127
3128 for_each_crtc(dev, crtc) {
3129 struct intel_plane *plane = to_intel_plane(crtc->primary);
3130 struct intel_plane_state *plane_state;
3131
3132 drm_modeset_lock_crtc(crtc, &plane->base);
3133 plane_state = to_intel_plane_state(plane->base.state);
3134
3135 if (plane_state->visible)
3136 plane->update_plane(&plane->base,
3137 to_intel_crtc_state(crtc->state),
3138 plane_state);
3139
3140 drm_modeset_unlock_crtc(crtc);
3141 }
3142 }
3143
3144 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3145 {
3146 /* no reset support for gen2 */
3147 if (IS_GEN2(dev_priv))
3148 return;
3149
3150 /* reset doesn't touch the display */
3151 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3152 return;
3153
3154 drm_modeset_lock_all(dev_priv->dev);
3155 /*
3156 * Disabling the crtcs gracefully seems nicer. Also the
3157 * g33 docs say we should at least disable all the planes.
3158 */
3159 intel_display_suspend(dev_priv->dev);
3160 }
3161
3162 void intel_finish_reset(struct drm_i915_private *dev_priv)
3163 {
3164 /*
3165 * Flips in the rings will be nuked by the reset,
3166 * so complete all pending flips so that user space
3167 * will get its events and not get stuck.
3168 */
3169 intel_complete_page_flips(dev_priv);
3170
3171 /* no reset support for gen2 */
3172 if (IS_GEN2(dev_priv))
3173 return;
3174
3175 /* reset doesn't touch the display */
3176 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
3177 /*
3178 * Flips in the rings have been nuked by the reset,
3179 * so update the base address of all primary
3180 * planes to the the last fb to make sure we're
3181 * showing the correct fb after a reset.
3182 *
3183 * FIXME: Atomic will make this obsolete since we won't schedule
3184 * CS-based flips (which might get lost in gpu resets) any more.
3185 */
3186 intel_update_primary_planes(dev_priv->dev);
3187 return;
3188 }
3189
3190 /*
3191 * The display has been reset as well,
3192 * so need a full re-initialization.
3193 */
3194 intel_runtime_pm_disable_interrupts(dev_priv);
3195 intel_runtime_pm_enable_interrupts(dev_priv);
3196
3197 intel_modeset_init_hw(dev_priv->dev);
3198
3199 spin_lock_irq(&dev_priv->irq_lock);
3200 if (dev_priv->display.hpd_irq_setup)
3201 dev_priv->display.hpd_irq_setup(dev_priv);
3202 spin_unlock_irq(&dev_priv->irq_lock);
3203
3204 intel_display_resume(dev_priv->dev);
3205
3206 intel_hpd_init(dev_priv);
3207
3208 drm_modeset_unlock_all(dev_priv->dev);
3209 }
3210
3211 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3212 {
3213 struct drm_device *dev = crtc->dev;
3214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3215 unsigned reset_counter;
3216
3217 reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
3218 if (intel_crtc->reset_counter != reset_counter)
3219 return false;
3220
3221 return !list_empty_careful(&to_intel_crtc(crtc)->flip_work);
3222 }
3223
3224 static void intel_update_pipe_config(struct intel_crtc *crtc,
3225 struct intel_crtc_state *old_crtc_state)
3226 {
3227 struct drm_device *dev = crtc->base.dev;
3228 struct drm_i915_private *dev_priv = dev->dev_private;
3229 struct intel_crtc_state *pipe_config =
3230 to_intel_crtc_state(crtc->base.state);
3231
3232 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3233 crtc->base.mode = crtc->base.state->mode;
3234
3235 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3236 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3237 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3238
3239 /*
3240 * Update pipe size and adjust fitter if needed: the reason for this is
3241 * that in compute_mode_changes we check the native mode (not the pfit
3242 * mode) to see if we can flip rather than do a full mode set. In the
3243 * fastboot case, we'll flip, but if we don't update the pipesrc and
3244 * pfit state, we'll end up with a big fb scanned out into the wrong
3245 * sized surface.
3246 */
3247
3248 I915_WRITE(PIPESRC(crtc->pipe),
3249 ((pipe_config->pipe_src_w - 1) << 16) |
3250 (pipe_config->pipe_src_h - 1));
3251
3252 /* on skylake this is done by detaching scalers */
3253 if (INTEL_INFO(dev)->gen >= 9) {
3254 skl_detach_scalers(crtc);
3255
3256 if (pipe_config->pch_pfit.enabled)
3257 skylake_pfit_enable(crtc);
3258 } else if (HAS_PCH_SPLIT(dev)) {
3259 if (pipe_config->pch_pfit.enabled)
3260 ironlake_pfit_enable(crtc);
3261 else if (old_crtc_state->pch_pfit.enabled)
3262 ironlake_pfit_disable(crtc, true);
3263 }
3264 }
3265
3266 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3267 {
3268 struct drm_device *dev = crtc->dev;
3269 struct drm_i915_private *dev_priv = dev->dev_private;
3270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3271 int pipe = intel_crtc->pipe;
3272 i915_reg_t reg;
3273 u32 temp;
3274
3275 /* enable normal train */
3276 reg = FDI_TX_CTL(pipe);
3277 temp = I915_READ(reg);
3278 if (IS_IVYBRIDGE(dev)) {
3279 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3280 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3281 } else {
3282 temp &= ~FDI_LINK_TRAIN_NONE;
3283 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3284 }
3285 I915_WRITE(reg, temp);
3286
3287 reg = FDI_RX_CTL(pipe);
3288 temp = I915_READ(reg);
3289 if (HAS_PCH_CPT(dev)) {
3290 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3291 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3292 } else {
3293 temp &= ~FDI_LINK_TRAIN_NONE;
3294 temp |= FDI_LINK_TRAIN_NONE;
3295 }
3296 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3297
3298 /* wait one idle pattern time */
3299 POSTING_READ(reg);
3300 udelay(1000);
3301
3302 /* IVB wants error correction enabled */
3303 if (IS_IVYBRIDGE(dev))
3304 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3305 FDI_FE_ERRC_ENABLE);
3306 }
3307
3308 /* The FDI link training functions for ILK/Ibexpeak. */
3309 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3310 {
3311 struct drm_device *dev = crtc->dev;
3312 struct drm_i915_private *dev_priv = dev->dev_private;
3313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3314 int pipe = intel_crtc->pipe;
3315 i915_reg_t reg;
3316 u32 temp, tries;
3317
3318 /* FDI needs bits from pipe first */
3319 assert_pipe_enabled(dev_priv, pipe);
3320
3321 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3322 for train result */
3323 reg = FDI_RX_IMR(pipe);
3324 temp = I915_READ(reg);
3325 temp &= ~FDI_RX_SYMBOL_LOCK;
3326 temp &= ~FDI_RX_BIT_LOCK;
3327 I915_WRITE(reg, temp);
3328 I915_READ(reg);
3329 udelay(150);
3330
3331 /* enable CPU FDI TX and PCH FDI RX */
3332 reg = FDI_TX_CTL(pipe);
3333 temp = I915_READ(reg);
3334 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3335 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3336 temp &= ~FDI_LINK_TRAIN_NONE;
3337 temp |= FDI_LINK_TRAIN_PATTERN_1;
3338 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3339
3340 reg = FDI_RX_CTL(pipe);
3341 temp = I915_READ(reg);
3342 temp &= ~FDI_LINK_TRAIN_NONE;
3343 temp |= FDI_LINK_TRAIN_PATTERN_1;
3344 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3345
3346 POSTING_READ(reg);
3347 udelay(150);
3348
3349 /* Ironlake workaround, enable clock pointer after FDI enable*/
3350 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3351 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3352 FDI_RX_PHASE_SYNC_POINTER_EN);
3353
3354 reg = FDI_RX_IIR(pipe);
3355 for (tries = 0; tries < 5; tries++) {
3356 temp = I915_READ(reg);
3357 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3358
3359 if ((temp & FDI_RX_BIT_LOCK)) {
3360 DRM_DEBUG_KMS("FDI train 1 done.\n");
3361 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3362 break;
3363 }
3364 }
3365 if (tries == 5)
3366 DRM_ERROR("FDI train 1 fail!\n");
3367
3368 /* Train 2 */
3369 reg = FDI_TX_CTL(pipe);
3370 temp = I915_READ(reg);
3371 temp &= ~FDI_LINK_TRAIN_NONE;
3372 temp |= FDI_LINK_TRAIN_PATTERN_2;
3373 I915_WRITE(reg, temp);
3374
3375 reg = FDI_RX_CTL(pipe);
3376 temp = I915_READ(reg);
3377 temp &= ~FDI_LINK_TRAIN_NONE;
3378 temp |= FDI_LINK_TRAIN_PATTERN_2;
3379 I915_WRITE(reg, temp);
3380
3381 POSTING_READ(reg);
3382 udelay(150);
3383
3384 reg = FDI_RX_IIR(pipe);
3385 for (tries = 0; tries < 5; tries++) {
3386 temp = I915_READ(reg);
3387 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3388
3389 if (temp & FDI_RX_SYMBOL_LOCK) {
3390 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3391 DRM_DEBUG_KMS("FDI train 2 done.\n");
3392 break;
3393 }
3394 }
3395 if (tries == 5)
3396 DRM_ERROR("FDI train 2 fail!\n");
3397
3398 DRM_DEBUG_KMS("FDI train done\n");
3399
3400 }
3401
3402 static const int snb_b_fdi_train_param[] = {
3403 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3404 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3405 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3406 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3407 };
3408
3409 /* The FDI link training functions for SNB/Cougarpoint. */
3410 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3411 {
3412 struct drm_device *dev = crtc->dev;
3413 struct drm_i915_private *dev_priv = dev->dev_private;
3414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3415 int pipe = intel_crtc->pipe;
3416 i915_reg_t reg;
3417 u32 temp, i, retry;
3418
3419 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3420 for train result */
3421 reg = FDI_RX_IMR(pipe);
3422 temp = I915_READ(reg);
3423 temp &= ~FDI_RX_SYMBOL_LOCK;
3424 temp &= ~FDI_RX_BIT_LOCK;
3425 I915_WRITE(reg, temp);
3426
3427 POSTING_READ(reg);
3428 udelay(150);
3429
3430 /* enable CPU FDI TX and PCH FDI RX */
3431 reg = FDI_TX_CTL(pipe);
3432 temp = I915_READ(reg);
3433 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3434 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3435 temp &= ~FDI_LINK_TRAIN_NONE;
3436 temp |= FDI_LINK_TRAIN_PATTERN_1;
3437 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3438 /* SNB-B */
3439 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3440 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3441
3442 I915_WRITE(FDI_RX_MISC(pipe),
3443 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3444
3445 reg = FDI_RX_CTL(pipe);
3446 temp = I915_READ(reg);
3447 if (HAS_PCH_CPT(dev)) {
3448 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3449 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3450 } else {
3451 temp &= ~FDI_LINK_TRAIN_NONE;
3452 temp |= FDI_LINK_TRAIN_PATTERN_1;
3453 }
3454 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3455
3456 POSTING_READ(reg);
3457 udelay(150);
3458
3459 for (i = 0; i < 4; i++) {
3460 reg = FDI_TX_CTL(pipe);
3461 temp = I915_READ(reg);
3462 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3463 temp |= snb_b_fdi_train_param[i];
3464 I915_WRITE(reg, temp);
3465
3466 POSTING_READ(reg);
3467 udelay(500);
3468
3469 for (retry = 0; retry < 5; retry++) {
3470 reg = FDI_RX_IIR(pipe);
3471 temp = I915_READ(reg);
3472 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3473 if (temp & FDI_RX_BIT_LOCK) {
3474 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3475 DRM_DEBUG_KMS("FDI train 1 done.\n");
3476 break;
3477 }
3478 udelay(50);
3479 }
3480 if (retry < 5)
3481 break;
3482 }
3483 if (i == 4)
3484 DRM_ERROR("FDI train 1 fail!\n");
3485
3486 /* Train 2 */
3487 reg = FDI_TX_CTL(pipe);
3488 temp = I915_READ(reg);
3489 temp &= ~FDI_LINK_TRAIN_NONE;
3490 temp |= FDI_LINK_TRAIN_PATTERN_2;
3491 if (IS_GEN6(dev)) {
3492 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3493 /* SNB-B */
3494 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3495 }
3496 I915_WRITE(reg, temp);
3497
3498 reg = FDI_RX_CTL(pipe);
3499 temp = I915_READ(reg);
3500 if (HAS_PCH_CPT(dev)) {
3501 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3502 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3503 } else {
3504 temp &= ~FDI_LINK_TRAIN_NONE;
3505 temp |= FDI_LINK_TRAIN_PATTERN_2;
3506 }
3507 I915_WRITE(reg, temp);
3508
3509 POSTING_READ(reg);
3510 udelay(150);
3511
3512 for (i = 0; i < 4; i++) {
3513 reg = FDI_TX_CTL(pipe);
3514 temp = I915_READ(reg);
3515 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3516 temp |= snb_b_fdi_train_param[i];
3517 I915_WRITE(reg, temp);
3518
3519 POSTING_READ(reg);
3520 udelay(500);
3521
3522 for (retry = 0; retry < 5; retry++) {
3523 reg = FDI_RX_IIR(pipe);
3524 temp = I915_READ(reg);
3525 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3526 if (temp & FDI_RX_SYMBOL_LOCK) {
3527 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3528 DRM_DEBUG_KMS("FDI train 2 done.\n");
3529 break;
3530 }
3531 udelay(50);
3532 }
3533 if (retry < 5)
3534 break;
3535 }
3536 if (i == 4)
3537 DRM_ERROR("FDI train 2 fail!\n");
3538
3539 DRM_DEBUG_KMS("FDI train done.\n");
3540 }
3541
3542 /* Manual link training for Ivy Bridge A0 parts */
3543 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3544 {
3545 struct drm_device *dev = crtc->dev;
3546 struct drm_i915_private *dev_priv = dev->dev_private;
3547 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3548 int pipe = intel_crtc->pipe;
3549 i915_reg_t reg;
3550 u32 temp, i, j;
3551
3552 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3553 for train result */
3554 reg = FDI_RX_IMR(pipe);
3555 temp = I915_READ(reg);
3556 temp &= ~FDI_RX_SYMBOL_LOCK;
3557 temp &= ~FDI_RX_BIT_LOCK;
3558 I915_WRITE(reg, temp);
3559
3560 POSTING_READ(reg);
3561 udelay(150);
3562
3563 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3564 I915_READ(FDI_RX_IIR(pipe)));
3565
3566 /* Try each vswing and preemphasis setting twice before moving on */
3567 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3568 /* disable first in case we need to retry */
3569 reg = FDI_TX_CTL(pipe);
3570 temp = I915_READ(reg);
3571 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3572 temp &= ~FDI_TX_ENABLE;
3573 I915_WRITE(reg, temp);
3574
3575 reg = FDI_RX_CTL(pipe);
3576 temp = I915_READ(reg);
3577 temp &= ~FDI_LINK_TRAIN_AUTO;
3578 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3579 temp &= ~FDI_RX_ENABLE;
3580 I915_WRITE(reg, temp);
3581
3582 /* enable CPU FDI TX and PCH FDI RX */
3583 reg = FDI_TX_CTL(pipe);
3584 temp = I915_READ(reg);
3585 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3586 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3587 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3588 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3589 temp |= snb_b_fdi_train_param[j/2];
3590 temp |= FDI_COMPOSITE_SYNC;
3591 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3592
3593 I915_WRITE(FDI_RX_MISC(pipe),
3594 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3595
3596 reg = FDI_RX_CTL(pipe);
3597 temp = I915_READ(reg);
3598 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3599 temp |= FDI_COMPOSITE_SYNC;
3600 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3601
3602 POSTING_READ(reg);
3603 udelay(1); /* should be 0.5us */
3604
3605 for (i = 0; i < 4; i++) {
3606 reg = FDI_RX_IIR(pipe);
3607 temp = I915_READ(reg);
3608 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3609
3610 if (temp & FDI_RX_BIT_LOCK ||
3611 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3612 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3613 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3614 i);
3615 break;
3616 }
3617 udelay(1); /* should be 0.5us */
3618 }
3619 if (i == 4) {
3620 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3621 continue;
3622 }
3623
3624 /* Train 2 */
3625 reg = FDI_TX_CTL(pipe);
3626 temp = I915_READ(reg);
3627 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3628 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3629 I915_WRITE(reg, temp);
3630
3631 reg = FDI_RX_CTL(pipe);
3632 temp = I915_READ(reg);
3633 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3634 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3635 I915_WRITE(reg, temp);
3636
3637 POSTING_READ(reg);
3638 udelay(2); /* should be 1.5us */
3639
3640 for (i = 0; i < 4; i++) {
3641 reg = FDI_RX_IIR(pipe);
3642 temp = I915_READ(reg);
3643 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3644
3645 if (temp & FDI_RX_SYMBOL_LOCK ||
3646 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3647 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3648 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3649 i);
3650 goto train_done;
3651 }
3652 udelay(2); /* should be 1.5us */
3653 }
3654 if (i == 4)
3655 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3656 }
3657
3658 train_done:
3659 DRM_DEBUG_KMS("FDI train done.\n");
3660 }
3661
3662 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3663 {
3664 struct drm_device *dev = intel_crtc->base.dev;
3665 struct drm_i915_private *dev_priv = dev->dev_private;
3666 int pipe = intel_crtc->pipe;
3667 i915_reg_t reg;
3668 u32 temp;
3669
3670 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3671 reg = FDI_RX_CTL(pipe);
3672 temp = I915_READ(reg);
3673 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3674 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3675 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3676 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3677
3678 POSTING_READ(reg);
3679 udelay(200);
3680
3681 /* Switch from Rawclk to PCDclk */
3682 temp = I915_READ(reg);
3683 I915_WRITE(reg, temp | FDI_PCDCLK);
3684
3685 POSTING_READ(reg);
3686 udelay(200);
3687
3688 /* Enable CPU FDI TX PLL, always on for Ironlake */
3689 reg = FDI_TX_CTL(pipe);
3690 temp = I915_READ(reg);
3691 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3692 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3693
3694 POSTING_READ(reg);
3695 udelay(100);
3696 }
3697 }
3698
3699 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3700 {
3701 struct drm_device *dev = intel_crtc->base.dev;
3702 struct drm_i915_private *dev_priv = dev->dev_private;
3703 int pipe = intel_crtc->pipe;
3704 i915_reg_t reg;
3705 u32 temp;
3706
3707 /* Switch from PCDclk to Rawclk */
3708 reg = FDI_RX_CTL(pipe);
3709 temp = I915_READ(reg);
3710 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3711
3712 /* Disable CPU FDI TX PLL */
3713 reg = FDI_TX_CTL(pipe);
3714 temp = I915_READ(reg);
3715 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3716
3717 POSTING_READ(reg);
3718 udelay(100);
3719
3720 reg = FDI_RX_CTL(pipe);
3721 temp = I915_READ(reg);
3722 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3723
3724 /* Wait for the clocks to turn off. */
3725 POSTING_READ(reg);
3726 udelay(100);
3727 }
3728
3729 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3730 {
3731 struct drm_device *dev = crtc->dev;
3732 struct drm_i915_private *dev_priv = dev->dev_private;
3733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3734 int pipe = intel_crtc->pipe;
3735 i915_reg_t reg;
3736 u32 temp;
3737
3738 /* disable CPU FDI tx and PCH FDI rx */
3739 reg = FDI_TX_CTL(pipe);
3740 temp = I915_READ(reg);
3741 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3742 POSTING_READ(reg);
3743
3744 reg = FDI_RX_CTL(pipe);
3745 temp = I915_READ(reg);
3746 temp &= ~(0x7 << 16);
3747 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3748 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3749
3750 POSTING_READ(reg);
3751 udelay(100);
3752
3753 /* Ironlake workaround, disable clock pointer after downing FDI */
3754 if (HAS_PCH_IBX(dev))
3755 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3756
3757 /* still set train pattern 1 */
3758 reg = FDI_TX_CTL(pipe);
3759 temp = I915_READ(reg);
3760 temp &= ~FDI_LINK_TRAIN_NONE;
3761 temp |= FDI_LINK_TRAIN_PATTERN_1;
3762 I915_WRITE(reg, temp);
3763
3764 reg = FDI_RX_CTL(pipe);
3765 temp = I915_READ(reg);
3766 if (HAS_PCH_CPT(dev)) {
3767 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3768 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3769 } else {
3770 temp &= ~FDI_LINK_TRAIN_NONE;
3771 temp |= FDI_LINK_TRAIN_PATTERN_1;
3772 }
3773 /* BPC in FDI rx is consistent with that in PIPECONF */
3774 temp &= ~(0x07 << 16);
3775 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3776 I915_WRITE(reg, temp);
3777
3778 POSTING_READ(reg);
3779 udelay(100);
3780 }
3781
3782 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3783 {
3784 struct intel_crtc *crtc;
3785
3786 /* Note that we don't need to be called with mode_config.lock here
3787 * as our list of CRTC objects is static for the lifetime of the
3788 * device and so cannot disappear as we iterate. Similarly, we can
3789 * happily treat the predicates as racy, atomic checks as userspace
3790 * cannot claim and pin a new fb without at least acquring the
3791 * struct_mutex and so serialising with us.
3792 */
3793 for_each_intel_crtc(dev, crtc) {
3794 if (atomic_read(&crtc->unpin_work_count) == 0)
3795 continue;
3796
3797 if (!list_empty_careful(&crtc->flip_work))
3798 intel_wait_for_vblank(dev, crtc->pipe);
3799
3800 return true;
3801 }
3802
3803 return false;
3804 }
3805
3806 static void page_flip_completed(struct intel_crtc *intel_crtc, struct intel_flip_work *work)
3807 {
3808 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3809
3810 list_del_init(&work->head);
3811
3812 if (work->event)
3813 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
3814
3815 drm_crtc_vblank_put(&intel_crtc->base);
3816
3817 wake_up_all(&dev_priv->pending_flip_queue);
3818 queue_work(dev_priv->wq, &work->unpin_work);
3819
3820 trace_i915_flip_complete(intel_crtc->plane,
3821 work->pending_flip_obj);
3822 }
3823
3824 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3825 {
3826 struct drm_device *dev = crtc->dev;
3827 struct drm_i915_private *dev_priv = dev->dev_private;
3828 long ret;
3829
3830 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3831
3832 ret = wait_event_interruptible_timeout(
3833 dev_priv->pending_flip_queue,
3834 !intel_crtc_has_pending_flip(crtc),
3835 60*HZ);
3836
3837 if (ret < 0)
3838 return ret;
3839
3840 if (ret == 0) {
3841 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3842 struct intel_flip_work *work;
3843
3844 spin_lock_irq(&dev->event_lock);
3845
3846 /*
3847 * If we're waiting for page flips, it's the first
3848 * flip on the list that's stuck.
3849 */
3850 work = list_first_entry_or_null(&intel_crtc->flip_work,
3851 struct intel_flip_work, head);
3852 if (work && !is_mmio_work(work)) {
3853 WARN_ONCE(1, "Removing stuck page flip\n");
3854 page_flip_completed(intel_crtc, work);
3855 }
3856 spin_unlock_irq(&dev->event_lock);
3857 }
3858
3859 return 0;
3860 }
3861
3862 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3863 {
3864 u32 temp;
3865
3866 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3867
3868 mutex_lock(&dev_priv->sb_lock);
3869
3870 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3871 temp |= SBI_SSCCTL_DISABLE;
3872 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3873
3874 mutex_unlock(&dev_priv->sb_lock);
3875 }
3876
3877 /* Program iCLKIP clock to the desired frequency */
3878 static void lpt_program_iclkip(struct drm_crtc *crtc)
3879 {
3880 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3881 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3882 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3883 u32 temp;
3884
3885 lpt_disable_iclkip(dev_priv);
3886
3887 /* The iCLK virtual clock root frequency is in MHz,
3888 * but the adjusted_mode->crtc_clock in in KHz. To get the
3889 * divisors, it is necessary to divide one by another, so we
3890 * convert the virtual clock precision to KHz here for higher
3891 * precision.
3892 */
3893 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3894 u32 iclk_virtual_root_freq = 172800 * 1000;
3895 u32 iclk_pi_range = 64;
3896 u32 desired_divisor;
3897
3898 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3899 clock << auxdiv);
3900 divsel = (desired_divisor / iclk_pi_range) - 2;
3901 phaseinc = desired_divisor % iclk_pi_range;
3902
3903 /*
3904 * Near 20MHz is a corner case which is
3905 * out of range for the 7-bit divisor
3906 */
3907 if (divsel <= 0x7f)
3908 break;
3909 }
3910
3911 /* This should not happen with any sane values */
3912 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3913 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3914 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3915 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3916
3917 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3918 clock,
3919 auxdiv,
3920 divsel,
3921 phasedir,
3922 phaseinc);
3923
3924 mutex_lock(&dev_priv->sb_lock);
3925
3926 /* Program SSCDIVINTPHASE6 */
3927 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3928 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3929 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3930 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3931 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3932 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3933 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3934 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3935
3936 /* Program SSCAUXDIV */
3937 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3938 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3939 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3940 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3941
3942 /* Enable modulator and associated divider */
3943 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3944 temp &= ~SBI_SSCCTL_DISABLE;
3945 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3946
3947 mutex_unlock(&dev_priv->sb_lock);
3948
3949 /* Wait for initialization time */
3950 udelay(24);
3951
3952 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3953 }
3954
3955 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3956 {
3957 u32 divsel, phaseinc, auxdiv;
3958 u32 iclk_virtual_root_freq = 172800 * 1000;
3959 u32 iclk_pi_range = 64;
3960 u32 desired_divisor;
3961 u32 temp;
3962
3963 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3964 return 0;
3965
3966 mutex_lock(&dev_priv->sb_lock);
3967
3968 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3969 if (temp & SBI_SSCCTL_DISABLE) {
3970 mutex_unlock(&dev_priv->sb_lock);
3971 return 0;
3972 }
3973
3974 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3975 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3976 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3977 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3978 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3979
3980 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3981 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
3982 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
3983
3984 mutex_unlock(&dev_priv->sb_lock);
3985
3986 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
3987
3988 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3989 desired_divisor << auxdiv);
3990 }
3991
3992 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3993 enum pipe pch_transcoder)
3994 {
3995 struct drm_device *dev = crtc->base.dev;
3996 struct drm_i915_private *dev_priv = dev->dev_private;
3997 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3998
3999 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4000 I915_READ(HTOTAL(cpu_transcoder)));
4001 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4002 I915_READ(HBLANK(cpu_transcoder)));
4003 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4004 I915_READ(HSYNC(cpu_transcoder)));
4005
4006 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4007 I915_READ(VTOTAL(cpu_transcoder)));
4008 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4009 I915_READ(VBLANK(cpu_transcoder)));
4010 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4011 I915_READ(VSYNC(cpu_transcoder)));
4012 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4013 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4014 }
4015
4016 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4017 {
4018 struct drm_i915_private *dev_priv = dev->dev_private;
4019 uint32_t temp;
4020
4021 temp = I915_READ(SOUTH_CHICKEN1);
4022 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4023 return;
4024
4025 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4026 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4027
4028 temp &= ~FDI_BC_BIFURCATION_SELECT;
4029 if (enable)
4030 temp |= FDI_BC_BIFURCATION_SELECT;
4031
4032 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4033 I915_WRITE(SOUTH_CHICKEN1, temp);
4034 POSTING_READ(SOUTH_CHICKEN1);
4035 }
4036
4037 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4038 {
4039 struct drm_device *dev = intel_crtc->base.dev;
4040
4041 switch (intel_crtc->pipe) {
4042 case PIPE_A:
4043 break;
4044 case PIPE_B:
4045 if (intel_crtc->config->fdi_lanes > 2)
4046 cpt_set_fdi_bc_bifurcation(dev, false);
4047 else
4048 cpt_set_fdi_bc_bifurcation(dev, true);
4049
4050 break;
4051 case PIPE_C:
4052 cpt_set_fdi_bc_bifurcation(dev, true);
4053
4054 break;
4055 default:
4056 BUG();
4057 }
4058 }
4059
4060 /* Return which DP Port should be selected for Transcoder DP control */
4061 static enum port
4062 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4063 {
4064 struct drm_device *dev = crtc->dev;
4065 struct intel_encoder *encoder;
4066
4067 for_each_encoder_on_crtc(dev, crtc, encoder) {
4068 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4069 encoder->type == INTEL_OUTPUT_EDP)
4070 return enc_to_dig_port(&encoder->base)->port;
4071 }
4072
4073 return -1;
4074 }
4075
4076 /*
4077 * Enable PCH resources required for PCH ports:
4078 * - PCH PLLs
4079 * - FDI training & RX/TX
4080 * - update transcoder timings
4081 * - DP transcoding bits
4082 * - transcoder
4083 */
4084 static void ironlake_pch_enable(struct drm_crtc *crtc)
4085 {
4086 struct drm_device *dev = crtc->dev;
4087 struct drm_i915_private *dev_priv = dev->dev_private;
4088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4089 int pipe = intel_crtc->pipe;
4090 u32 temp;
4091
4092 assert_pch_transcoder_disabled(dev_priv, pipe);
4093
4094 if (IS_IVYBRIDGE(dev))
4095 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4096
4097 /* Write the TU size bits before fdi link training, so that error
4098 * detection works. */
4099 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4100 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4101
4102 /* For PCH output, training FDI link */
4103 dev_priv->display.fdi_link_train(crtc);
4104
4105 /* We need to program the right clock selection before writing the pixel
4106 * mutliplier into the DPLL. */
4107 if (HAS_PCH_CPT(dev)) {
4108 u32 sel;
4109
4110 temp = I915_READ(PCH_DPLL_SEL);
4111 temp |= TRANS_DPLL_ENABLE(pipe);
4112 sel = TRANS_DPLLB_SEL(pipe);
4113 if (intel_crtc->config->shared_dpll ==
4114 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4115 temp |= sel;
4116 else
4117 temp &= ~sel;
4118 I915_WRITE(PCH_DPLL_SEL, temp);
4119 }
4120
4121 /* XXX: pch pll's can be enabled any time before we enable the PCH
4122 * transcoder, and we actually should do this to not upset any PCH
4123 * transcoder that already use the clock when we share it.
4124 *
4125 * Note that enable_shared_dpll tries to do the right thing, but
4126 * get_shared_dpll unconditionally resets the pll - we need that to have
4127 * the right LVDS enable sequence. */
4128 intel_enable_shared_dpll(intel_crtc);
4129
4130 /* set transcoder timing, panel must allow it */
4131 assert_panel_unlocked(dev_priv, pipe);
4132 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4133
4134 intel_fdi_normal_train(crtc);
4135
4136 /* For PCH DP, enable TRANS_DP_CTL */
4137 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4138 const struct drm_display_mode *adjusted_mode =
4139 &intel_crtc->config->base.adjusted_mode;
4140 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4141 i915_reg_t reg = TRANS_DP_CTL(pipe);
4142 temp = I915_READ(reg);
4143 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4144 TRANS_DP_SYNC_MASK |
4145 TRANS_DP_BPC_MASK);
4146 temp |= TRANS_DP_OUTPUT_ENABLE;
4147 temp |= bpc << 9; /* same format but at 11:9 */
4148
4149 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4150 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4151 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4152 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4153
4154 switch (intel_trans_dp_port_sel(crtc)) {
4155 case PORT_B:
4156 temp |= TRANS_DP_PORT_SEL_B;
4157 break;
4158 case PORT_C:
4159 temp |= TRANS_DP_PORT_SEL_C;
4160 break;
4161 case PORT_D:
4162 temp |= TRANS_DP_PORT_SEL_D;
4163 break;
4164 default:
4165 BUG();
4166 }
4167
4168 I915_WRITE(reg, temp);
4169 }
4170
4171 ironlake_enable_pch_transcoder(dev_priv, pipe);
4172 }
4173
4174 static void lpt_pch_enable(struct drm_crtc *crtc)
4175 {
4176 struct drm_device *dev = crtc->dev;
4177 struct drm_i915_private *dev_priv = dev->dev_private;
4178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4179 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4180
4181 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4182
4183 lpt_program_iclkip(crtc);
4184
4185 /* Set transcoder timing. */
4186 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4187
4188 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4189 }
4190
4191 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4192 {
4193 struct drm_i915_private *dev_priv = dev->dev_private;
4194 i915_reg_t dslreg = PIPEDSL(pipe);
4195 u32 temp;
4196
4197 temp = I915_READ(dslreg);
4198 udelay(500);
4199 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4200 if (wait_for(I915_READ(dslreg) != temp, 5))
4201 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4202 }
4203 }
4204
4205 static int
4206 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4207 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4208 int src_w, int src_h, int dst_w, int dst_h)
4209 {
4210 struct intel_crtc_scaler_state *scaler_state =
4211 &crtc_state->scaler_state;
4212 struct intel_crtc *intel_crtc =
4213 to_intel_crtc(crtc_state->base.crtc);
4214 int need_scaling;
4215
4216 need_scaling = intel_rotation_90_or_270(rotation) ?
4217 (src_h != dst_w || src_w != dst_h):
4218 (src_w != dst_w || src_h != dst_h);
4219
4220 /*
4221 * if plane is being disabled or scaler is no more required or force detach
4222 * - free scaler binded to this plane/crtc
4223 * - in order to do this, update crtc->scaler_usage
4224 *
4225 * Here scaler state in crtc_state is set free so that
4226 * scaler can be assigned to other user. Actual register
4227 * update to free the scaler is done in plane/panel-fit programming.
4228 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4229 */
4230 if (force_detach || !need_scaling) {
4231 if (*scaler_id >= 0) {
4232 scaler_state->scaler_users &= ~(1 << scaler_user);
4233 scaler_state->scalers[*scaler_id].in_use = 0;
4234
4235 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4236 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4237 intel_crtc->pipe, scaler_user, *scaler_id,
4238 scaler_state->scaler_users);
4239 *scaler_id = -1;
4240 }
4241 return 0;
4242 }
4243
4244 /* range checks */
4245 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4246 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4247
4248 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4249 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4250 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4251 "size is out of scaler range\n",
4252 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4253 return -EINVAL;
4254 }
4255
4256 /* mark this plane as a scaler user in crtc_state */
4257 scaler_state->scaler_users |= (1 << scaler_user);
4258 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4259 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4260 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4261 scaler_state->scaler_users);
4262
4263 return 0;
4264 }
4265
4266 /**
4267 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4268 *
4269 * @state: crtc's scaler state
4270 *
4271 * Return
4272 * 0 - scaler_usage updated successfully
4273 * error - requested scaling cannot be supported or other error condition
4274 */
4275 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4276 {
4277 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4278 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4279
4280 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4281 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4282
4283 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4284 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4285 state->pipe_src_w, state->pipe_src_h,
4286 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4287 }
4288
4289 /**
4290 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4291 *
4292 * @state: crtc's scaler state
4293 * @plane_state: atomic plane state to update
4294 *
4295 * Return
4296 * 0 - scaler_usage updated successfully
4297 * error - requested scaling cannot be supported or other error condition
4298 */
4299 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4300 struct intel_plane_state *plane_state)
4301 {
4302
4303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4304 struct intel_plane *intel_plane =
4305 to_intel_plane(plane_state->base.plane);
4306 struct drm_framebuffer *fb = plane_state->base.fb;
4307 int ret;
4308
4309 bool force_detach = !fb || !plane_state->visible;
4310
4311 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4312 intel_plane->base.base.id, intel_crtc->pipe,
4313 drm_plane_index(&intel_plane->base));
4314
4315 ret = skl_update_scaler(crtc_state, force_detach,
4316 drm_plane_index(&intel_plane->base),
4317 &plane_state->scaler_id,
4318 plane_state->base.rotation,
4319 drm_rect_width(&plane_state->src) >> 16,
4320 drm_rect_height(&plane_state->src) >> 16,
4321 drm_rect_width(&plane_state->dst),
4322 drm_rect_height(&plane_state->dst));
4323
4324 if (ret || plane_state->scaler_id < 0)
4325 return ret;
4326
4327 /* check colorkey */
4328 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4329 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4330 intel_plane->base.base.id);
4331 return -EINVAL;
4332 }
4333
4334 /* Check src format */
4335 switch (fb->pixel_format) {
4336 case DRM_FORMAT_RGB565:
4337 case DRM_FORMAT_XBGR8888:
4338 case DRM_FORMAT_XRGB8888:
4339 case DRM_FORMAT_ABGR8888:
4340 case DRM_FORMAT_ARGB8888:
4341 case DRM_FORMAT_XRGB2101010:
4342 case DRM_FORMAT_XBGR2101010:
4343 case DRM_FORMAT_YUYV:
4344 case DRM_FORMAT_YVYU:
4345 case DRM_FORMAT_UYVY:
4346 case DRM_FORMAT_VYUY:
4347 break;
4348 default:
4349 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4350 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4351 return -EINVAL;
4352 }
4353
4354 return 0;
4355 }
4356
4357 static void skylake_scaler_disable(struct intel_crtc *crtc)
4358 {
4359 int i;
4360
4361 for (i = 0; i < crtc->num_scalers; i++)
4362 skl_detach_scaler(crtc, i);
4363 }
4364
4365 static void skylake_pfit_enable(struct intel_crtc *crtc)
4366 {
4367 struct drm_device *dev = crtc->base.dev;
4368 struct drm_i915_private *dev_priv = dev->dev_private;
4369 int pipe = crtc->pipe;
4370 struct intel_crtc_scaler_state *scaler_state =
4371 &crtc->config->scaler_state;
4372
4373 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4374
4375 if (crtc->config->pch_pfit.enabled) {
4376 int id;
4377
4378 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4379 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4380 return;
4381 }
4382
4383 id = scaler_state->scaler_id;
4384 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4385 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4386 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4387 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4388
4389 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4390 }
4391 }
4392
4393 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4394 {
4395 struct drm_device *dev = crtc->base.dev;
4396 struct drm_i915_private *dev_priv = dev->dev_private;
4397 int pipe = crtc->pipe;
4398
4399 if (crtc->config->pch_pfit.enabled) {
4400 /* Force use of hard-coded filter coefficients
4401 * as some pre-programmed values are broken,
4402 * e.g. x201.
4403 */
4404 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4405 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4406 PF_PIPE_SEL_IVB(pipe));
4407 else
4408 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4409 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4410 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4411 }
4412 }
4413
4414 void hsw_enable_ips(struct intel_crtc *crtc)
4415 {
4416 struct drm_device *dev = crtc->base.dev;
4417 struct drm_i915_private *dev_priv = dev->dev_private;
4418
4419 if (!crtc->config->ips_enabled)
4420 return;
4421
4422 /*
4423 * We can only enable IPS after we enable a plane and wait for a vblank
4424 * This function is called from post_plane_update, which is run after
4425 * a vblank wait.
4426 */
4427
4428 assert_plane_enabled(dev_priv, crtc->plane);
4429 if (IS_BROADWELL(dev)) {
4430 mutex_lock(&dev_priv->rps.hw_lock);
4431 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4432 mutex_unlock(&dev_priv->rps.hw_lock);
4433 /* Quoting Art Runyan: "its not safe to expect any particular
4434 * value in IPS_CTL bit 31 after enabling IPS through the
4435 * mailbox." Moreover, the mailbox may return a bogus state,
4436 * so we need to just enable it and continue on.
4437 */
4438 } else {
4439 I915_WRITE(IPS_CTL, IPS_ENABLE);
4440 /* The bit only becomes 1 in the next vblank, so this wait here
4441 * is essentially intel_wait_for_vblank. If we don't have this
4442 * and don't wait for vblanks until the end of crtc_enable, then
4443 * the HW state readout code will complain that the expected
4444 * IPS_CTL value is not the one we read. */
4445 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4446 DRM_ERROR("Timed out waiting for IPS enable\n");
4447 }
4448 }
4449
4450 void hsw_disable_ips(struct intel_crtc *crtc)
4451 {
4452 struct drm_device *dev = crtc->base.dev;
4453 struct drm_i915_private *dev_priv = dev->dev_private;
4454
4455 if (!crtc->config->ips_enabled)
4456 return;
4457
4458 assert_plane_enabled(dev_priv, crtc->plane);
4459 if (IS_BROADWELL(dev)) {
4460 mutex_lock(&dev_priv->rps.hw_lock);
4461 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4462 mutex_unlock(&dev_priv->rps.hw_lock);
4463 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4464 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4465 DRM_ERROR("Timed out waiting for IPS disable\n");
4466 } else {
4467 I915_WRITE(IPS_CTL, 0);
4468 POSTING_READ(IPS_CTL);
4469 }
4470
4471 /* We need to wait for a vblank before we can disable the plane. */
4472 intel_wait_for_vblank(dev, crtc->pipe);
4473 }
4474
4475 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4476 {
4477 if (intel_crtc->overlay) {
4478 struct drm_device *dev = intel_crtc->base.dev;
4479 struct drm_i915_private *dev_priv = dev->dev_private;
4480
4481 mutex_lock(&dev->struct_mutex);
4482 dev_priv->mm.interruptible = false;
4483 (void) intel_overlay_switch_off(intel_crtc->overlay);
4484 dev_priv->mm.interruptible = true;
4485 mutex_unlock(&dev->struct_mutex);
4486 }
4487
4488 /* Let userspace switch the overlay on again. In most cases userspace
4489 * has to recompute where to put it anyway.
4490 */
4491 }
4492
4493 /**
4494 * intel_post_enable_primary - Perform operations after enabling primary plane
4495 * @crtc: the CRTC whose primary plane was just enabled
4496 *
4497 * Performs potentially sleeping operations that must be done after the primary
4498 * plane is enabled, such as updating FBC and IPS. Note that this may be
4499 * called due to an explicit primary plane update, or due to an implicit
4500 * re-enable that is caused when a sprite plane is updated to no longer
4501 * completely hide the primary plane.
4502 */
4503 static void
4504 intel_post_enable_primary(struct drm_crtc *crtc)
4505 {
4506 struct drm_device *dev = crtc->dev;
4507 struct drm_i915_private *dev_priv = dev->dev_private;
4508 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4509 int pipe = intel_crtc->pipe;
4510
4511 /*
4512 * FIXME IPS should be fine as long as one plane is
4513 * enabled, but in practice it seems to have problems
4514 * when going from primary only to sprite only and vice
4515 * versa.
4516 */
4517 hsw_enable_ips(intel_crtc);
4518
4519 /*
4520 * Gen2 reports pipe underruns whenever all planes are disabled.
4521 * So don't enable underrun reporting before at least some planes
4522 * are enabled.
4523 * FIXME: Need to fix the logic to work when we turn off all planes
4524 * but leave the pipe running.
4525 */
4526 if (IS_GEN2(dev))
4527 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4528
4529 /* Underruns don't always raise interrupts, so check manually. */
4530 intel_check_cpu_fifo_underruns(dev_priv);
4531 intel_check_pch_fifo_underruns(dev_priv);
4532 }
4533
4534 /* FIXME move all this to pre_plane_update() with proper state tracking */
4535 static void
4536 intel_pre_disable_primary(struct drm_crtc *crtc)
4537 {
4538 struct drm_device *dev = crtc->dev;
4539 struct drm_i915_private *dev_priv = dev->dev_private;
4540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4541 int pipe = intel_crtc->pipe;
4542
4543 /*
4544 * Gen2 reports pipe underruns whenever all planes are disabled.
4545 * So diasble underrun reporting before all the planes get disabled.
4546 * FIXME: Need to fix the logic to work when we turn off all planes
4547 * but leave the pipe running.
4548 */
4549 if (IS_GEN2(dev))
4550 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4551
4552 /*
4553 * FIXME IPS should be fine as long as one plane is
4554 * enabled, but in practice it seems to have problems
4555 * when going from primary only to sprite only and vice
4556 * versa.
4557 */
4558 hsw_disable_ips(intel_crtc);
4559 }
4560
4561 /* FIXME get rid of this and use pre_plane_update */
4562 static void
4563 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4564 {
4565 struct drm_device *dev = crtc->dev;
4566 struct drm_i915_private *dev_priv = dev->dev_private;
4567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4568 int pipe = intel_crtc->pipe;
4569
4570 intel_pre_disable_primary(crtc);
4571
4572 /*
4573 * Vblank time updates from the shadow to live plane control register
4574 * are blocked if the memory self-refresh mode is active at that
4575 * moment. So to make sure the plane gets truly disabled, disable
4576 * first the self-refresh mode. The self-refresh enable bit in turn
4577 * will be checked/applied by the HW only at the next frame start
4578 * event which is after the vblank start event, so we need to have a
4579 * wait-for-vblank between disabling the plane and the pipe.
4580 */
4581 if (HAS_GMCH_DISPLAY(dev)) {
4582 intel_set_memory_cxsr(dev_priv, false);
4583 dev_priv->wm.vlv.cxsr = false;
4584 intel_wait_for_vblank(dev, pipe);
4585 }
4586 }
4587
4588 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4589 {
4590 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4591 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4592 struct intel_crtc_state *pipe_config =
4593 to_intel_crtc_state(crtc->base.state);
4594 struct drm_device *dev = crtc->base.dev;
4595 struct drm_plane *primary = crtc->base.primary;
4596 struct drm_plane_state *old_pri_state =
4597 drm_atomic_get_existing_plane_state(old_state, primary);
4598
4599 intel_frontbuffer_flip(dev, pipe_config->fb_bits);
4600
4601 crtc->wm.cxsr_allowed = true;
4602
4603 if (pipe_config->update_wm_post && pipe_config->base.active)
4604 intel_update_watermarks(&crtc->base);
4605
4606 if (old_pri_state) {
4607 struct intel_plane_state *primary_state =
4608 to_intel_plane_state(primary->state);
4609 struct intel_plane_state *old_primary_state =
4610 to_intel_plane_state(old_pri_state);
4611
4612 intel_fbc_post_update(crtc);
4613
4614 if (primary_state->visible &&
4615 (needs_modeset(&pipe_config->base) ||
4616 !old_primary_state->visible))
4617 intel_post_enable_primary(&crtc->base);
4618 }
4619 }
4620
4621 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4622 {
4623 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4624 struct drm_device *dev = crtc->base.dev;
4625 struct drm_i915_private *dev_priv = dev->dev_private;
4626 struct intel_crtc_state *pipe_config =
4627 to_intel_crtc_state(crtc->base.state);
4628 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4629 struct drm_plane *primary = crtc->base.primary;
4630 struct drm_plane_state *old_pri_state =
4631 drm_atomic_get_existing_plane_state(old_state, primary);
4632 bool modeset = needs_modeset(&pipe_config->base);
4633
4634 if (old_pri_state) {
4635 struct intel_plane_state *primary_state =
4636 to_intel_plane_state(primary->state);
4637 struct intel_plane_state *old_primary_state =
4638 to_intel_plane_state(old_pri_state);
4639
4640 intel_fbc_pre_update(crtc);
4641
4642 if (old_primary_state->visible &&
4643 (modeset || !primary_state->visible))
4644 intel_pre_disable_primary(&crtc->base);
4645 }
4646
4647 if (pipe_config->disable_cxsr) {
4648 crtc->wm.cxsr_allowed = false;
4649
4650 /*
4651 * Vblank time updates from the shadow to live plane control register
4652 * are blocked if the memory self-refresh mode is active at that
4653 * moment. So to make sure the plane gets truly disabled, disable
4654 * first the self-refresh mode. The self-refresh enable bit in turn
4655 * will be checked/applied by the HW only at the next frame start
4656 * event which is after the vblank start event, so we need to have a
4657 * wait-for-vblank between disabling the plane and the pipe.
4658 */
4659 if (old_crtc_state->base.active) {
4660 intel_set_memory_cxsr(dev_priv, false);
4661 dev_priv->wm.vlv.cxsr = false;
4662 intel_wait_for_vblank(dev, crtc->pipe);
4663 }
4664 }
4665
4666 /*
4667 * IVB workaround: must disable low power watermarks for at least
4668 * one frame before enabling scaling. LP watermarks can be re-enabled
4669 * when scaling is disabled.
4670 *
4671 * WaCxSRDisabledForSpriteScaling:ivb
4672 */
4673 if (pipe_config->disable_lp_wm) {
4674 ilk_disable_lp_wm(dev);
4675 intel_wait_for_vblank(dev, crtc->pipe);
4676 }
4677
4678 /*
4679 * If we're doing a modeset, we're done. No need to do any pre-vblank
4680 * watermark programming here.
4681 */
4682 if (needs_modeset(&pipe_config->base))
4683 return;
4684
4685 /*
4686 * For platforms that support atomic watermarks, program the
4687 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4688 * will be the intermediate values that are safe for both pre- and
4689 * post- vblank; when vblank happens, the 'active' values will be set
4690 * to the final 'target' values and we'll do this again to get the
4691 * optimal watermarks. For gen9+ platforms, the values we program here
4692 * will be the final target values which will get automatically latched
4693 * at vblank time; no further programming will be necessary.
4694 *
4695 * If a platform hasn't been transitioned to atomic watermarks yet,
4696 * we'll continue to update watermarks the old way, if flags tell
4697 * us to.
4698 */
4699 if (dev_priv->display.initial_watermarks != NULL)
4700 dev_priv->display.initial_watermarks(pipe_config);
4701 else if (pipe_config->update_wm_pre)
4702 intel_update_watermarks(&crtc->base);
4703 }
4704
4705 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4706 {
4707 struct drm_device *dev = crtc->dev;
4708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4709 struct drm_plane *p;
4710 int pipe = intel_crtc->pipe;
4711
4712 intel_crtc_dpms_overlay_disable(intel_crtc);
4713
4714 drm_for_each_plane_mask(p, dev, plane_mask)
4715 to_intel_plane(p)->disable_plane(p, crtc);
4716
4717 /*
4718 * FIXME: Once we grow proper nuclear flip support out of this we need
4719 * to compute the mask of flip planes precisely. For the time being
4720 * consider this a flip to a NULL plane.
4721 */
4722 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4723 }
4724
4725 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4726 {
4727 struct drm_device *dev = crtc->dev;
4728 struct drm_i915_private *dev_priv = dev->dev_private;
4729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4730 struct intel_encoder *encoder;
4731 int pipe = intel_crtc->pipe;
4732 struct intel_crtc_state *pipe_config =
4733 to_intel_crtc_state(crtc->state);
4734
4735 if (WARN_ON(intel_crtc->active))
4736 return;
4737
4738 /*
4739 * Sometimes spurious CPU pipe underruns happen during FDI
4740 * training, at least with VGA+HDMI cloning. Suppress them.
4741 *
4742 * On ILK we get an occasional spurious CPU pipe underruns
4743 * between eDP port A enable and vdd enable. Also PCH port
4744 * enable seems to result in the occasional CPU pipe underrun.
4745 *
4746 * Spurious PCH underruns also occur during PCH enabling.
4747 */
4748 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
4749 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4750 if (intel_crtc->config->has_pch_encoder)
4751 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4752
4753 if (intel_crtc->config->has_pch_encoder)
4754 intel_prepare_shared_dpll(intel_crtc);
4755
4756 if (intel_crtc->config->has_dp_encoder)
4757 intel_dp_set_m_n(intel_crtc, M1_N1);
4758
4759 intel_set_pipe_timings(intel_crtc);
4760 intel_set_pipe_src_size(intel_crtc);
4761
4762 if (intel_crtc->config->has_pch_encoder) {
4763 intel_cpu_transcoder_set_m_n(intel_crtc,
4764 &intel_crtc->config->fdi_m_n, NULL);
4765 }
4766
4767 ironlake_set_pipeconf(crtc);
4768
4769 intel_crtc->active = true;
4770
4771 for_each_encoder_on_crtc(dev, crtc, encoder)
4772 if (encoder->pre_enable)
4773 encoder->pre_enable(encoder);
4774
4775 if (intel_crtc->config->has_pch_encoder) {
4776 /* Note: FDI PLL enabling _must_ be done before we enable the
4777 * cpu pipes, hence this is separate from all the other fdi/pch
4778 * enabling. */
4779 ironlake_fdi_pll_enable(intel_crtc);
4780 } else {
4781 assert_fdi_tx_disabled(dev_priv, pipe);
4782 assert_fdi_rx_disabled(dev_priv, pipe);
4783 }
4784
4785 ironlake_pfit_enable(intel_crtc);
4786
4787 /*
4788 * On ILK+ LUT must be loaded before the pipe is running but with
4789 * clocks enabled
4790 */
4791 intel_color_load_luts(&pipe_config->base);
4792
4793 if (dev_priv->display.initial_watermarks != NULL)
4794 dev_priv->display.initial_watermarks(intel_crtc->config);
4795 intel_enable_pipe(intel_crtc);
4796
4797 if (intel_crtc->config->has_pch_encoder)
4798 ironlake_pch_enable(crtc);
4799
4800 assert_vblank_disabled(crtc);
4801 drm_crtc_vblank_on(crtc);
4802
4803 for_each_encoder_on_crtc(dev, crtc, encoder)
4804 encoder->enable(encoder);
4805
4806 if (HAS_PCH_CPT(dev))
4807 cpt_verify_modeset(dev, intel_crtc->pipe);
4808
4809 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4810 if (intel_crtc->config->has_pch_encoder)
4811 intel_wait_for_vblank(dev, pipe);
4812 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4813 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4814 }
4815
4816 /* IPS only exists on ULT machines and is tied to pipe A. */
4817 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4818 {
4819 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4820 }
4821
4822 static void haswell_crtc_enable(struct drm_crtc *crtc)
4823 {
4824 struct drm_device *dev = crtc->dev;
4825 struct drm_i915_private *dev_priv = dev->dev_private;
4826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4827 struct intel_encoder *encoder;
4828 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4829 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4830 struct intel_crtc_state *pipe_config =
4831 to_intel_crtc_state(crtc->state);
4832
4833 if (WARN_ON(intel_crtc->active))
4834 return;
4835
4836 if (intel_crtc->config->has_pch_encoder)
4837 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4838 false);
4839
4840 if (intel_crtc->config->shared_dpll)
4841 intel_enable_shared_dpll(intel_crtc);
4842
4843 if (intel_crtc->config->has_dp_encoder)
4844 intel_dp_set_m_n(intel_crtc, M1_N1);
4845
4846 if (!intel_crtc->config->has_dsi_encoder)
4847 intel_set_pipe_timings(intel_crtc);
4848
4849 intel_set_pipe_src_size(intel_crtc);
4850
4851 if (cpu_transcoder != TRANSCODER_EDP &&
4852 !transcoder_is_dsi(cpu_transcoder)) {
4853 I915_WRITE(PIPE_MULT(cpu_transcoder),
4854 intel_crtc->config->pixel_multiplier - 1);
4855 }
4856
4857 if (intel_crtc->config->has_pch_encoder) {
4858 intel_cpu_transcoder_set_m_n(intel_crtc,
4859 &intel_crtc->config->fdi_m_n, NULL);
4860 }
4861
4862 if (!intel_crtc->config->has_dsi_encoder)
4863 haswell_set_pipeconf(crtc);
4864
4865 haswell_set_pipemisc(crtc);
4866
4867 intel_color_set_csc(&pipe_config->base);
4868
4869 intel_crtc->active = true;
4870
4871 if (intel_crtc->config->has_pch_encoder)
4872 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4873 else
4874 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4875
4876 for_each_encoder_on_crtc(dev, crtc, encoder) {
4877 if (encoder->pre_enable)
4878 encoder->pre_enable(encoder);
4879 }
4880
4881 if (intel_crtc->config->has_pch_encoder)
4882 dev_priv->display.fdi_link_train(crtc);
4883
4884 if (!intel_crtc->config->has_dsi_encoder)
4885 intel_ddi_enable_pipe_clock(intel_crtc);
4886
4887 if (INTEL_INFO(dev)->gen >= 9)
4888 skylake_pfit_enable(intel_crtc);
4889 else
4890 ironlake_pfit_enable(intel_crtc);
4891
4892 /*
4893 * On ILK+ LUT must be loaded before the pipe is running but with
4894 * clocks enabled
4895 */
4896 intel_color_load_luts(&pipe_config->base);
4897
4898 intel_ddi_set_pipe_settings(crtc);
4899 if (!intel_crtc->config->has_dsi_encoder)
4900 intel_ddi_enable_transcoder_func(crtc);
4901
4902 if (dev_priv->display.initial_watermarks != NULL)
4903 dev_priv->display.initial_watermarks(pipe_config);
4904 else
4905 intel_update_watermarks(crtc);
4906
4907 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4908 if (!intel_crtc->config->has_dsi_encoder)
4909 intel_enable_pipe(intel_crtc);
4910
4911 if (intel_crtc->config->has_pch_encoder)
4912 lpt_pch_enable(crtc);
4913
4914 if (intel_crtc->config->dp_encoder_is_mst)
4915 intel_ddi_set_vc_payload_alloc(crtc, true);
4916
4917 assert_vblank_disabled(crtc);
4918 drm_crtc_vblank_on(crtc);
4919
4920 for_each_encoder_on_crtc(dev, crtc, encoder) {
4921 encoder->enable(encoder);
4922 intel_opregion_notify_encoder(encoder, true);
4923 }
4924
4925 if (intel_crtc->config->has_pch_encoder) {
4926 intel_wait_for_vblank(dev, pipe);
4927 intel_wait_for_vblank(dev, pipe);
4928 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4929 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4930 true);
4931 }
4932
4933 /* If we change the relative order between pipe/planes enabling, we need
4934 * to change the workaround. */
4935 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4936 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4937 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4938 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4939 }
4940 }
4941
4942 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4943 {
4944 struct drm_device *dev = crtc->base.dev;
4945 struct drm_i915_private *dev_priv = dev->dev_private;
4946 int pipe = crtc->pipe;
4947
4948 /* To avoid upsetting the power well on haswell only disable the pfit if
4949 * it's in use. The hw state code will make sure we get this right. */
4950 if (force || crtc->config->pch_pfit.enabled) {
4951 I915_WRITE(PF_CTL(pipe), 0);
4952 I915_WRITE(PF_WIN_POS(pipe), 0);
4953 I915_WRITE(PF_WIN_SZ(pipe), 0);
4954 }
4955 }
4956
4957 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4958 {
4959 struct drm_device *dev = crtc->dev;
4960 struct drm_i915_private *dev_priv = dev->dev_private;
4961 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4962 struct intel_encoder *encoder;
4963 int pipe = intel_crtc->pipe;
4964
4965 /*
4966 * Sometimes spurious CPU pipe underruns happen when the
4967 * pipe is already disabled, but FDI RX/TX is still enabled.
4968 * Happens at least with VGA+HDMI cloning. Suppress them.
4969 */
4970 if (intel_crtc->config->has_pch_encoder) {
4971 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4972 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4973 }
4974
4975 for_each_encoder_on_crtc(dev, crtc, encoder)
4976 encoder->disable(encoder);
4977
4978 drm_crtc_vblank_off(crtc);
4979 assert_vblank_disabled(crtc);
4980
4981 intel_disable_pipe(intel_crtc);
4982
4983 ironlake_pfit_disable(intel_crtc, false);
4984
4985 if (intel_crtc->config->has_pch_encoder)
4986 ironlake_fdi_disable(crtc);
4987
4988 for_each_encoder_on_crtc(dev, crtc, encoder)
4989 if (encoder->post_disable)
4990 encoder->post_disable(encoder);
4991
4992 if (intel_crtc->config->has_pch_encoder) {
4993 ironlake_disable_pch_transcoder(dev_priv, pipe);
4994
4995 if (HAS_PCH_CPT(dev)) {
4996 i915_reg_t reg;
4997 u32 temp;
4998
4999 /* disable TRANS_DP_CTL */
5000 reg = TRANS_DP_CTL(pipe);
5001 temp = I915_READ(reg);
5002 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5003 TRANS_DP_PORT_SEL_MASK);
5004 temp |= TRANS_DP_PORT_SEL_NONE;
5005 I915_WRITE(reg, temp);
5006
5007 /* disable DPLL_SEL */
5008 temp = I915_READ(PCH_DPLL_SEL);
5009 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5010 I915_WRITE(PCH_DPLL_SEL, temp);
5011 }
5012
5013 ironlake_fdi_pll_disable(intel_crtc);
5014 }
5015
5016 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5017 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5018 }
5019
5020 static void haswell_crtc_disable(struct drm_crtc *crtc)
5021 {
5022 struct drm_device *dev = crtc->dev;
5023 struct drm_i915_private *dev_priv = dev->dev_private;
5024 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5025 struct intel_encoder *encoder;
5026 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5027
5028 if (intel_crtc->config->has_pch_encoder)
5029 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5030 false);
5031
5032 for_each_encoder_on_crtc(dev, crtc, encoder) {
5033 intel_opregion_notify_encoder(encoder, false);
5034 encoder->disable(encoder);
5035 }
5036
5037 drm_crtc_vblank_off(crtc);
5038 assert_vblank_disabled(crtc);
5039
5040 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5041 if (!intel_crtc->config->has_dsi_encoder)
5042 intel_disable_pipe(intel_crtc);
5043
5044 if (intel_crtc->config->dp_encoder_is_mst)
5045 intel_ddi_set_vc_payload_alloc(crtc, false);
5046
5047 if (!intel_crtc->config->has_dsi_encoder)
5048 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5049
5050 if (INTEL_INFO(dev)->gen >= 9)
5051 skylake_scaler_disable(intel_crtc);
5052 else
5053 ironlake_pfit_disable(intel_crtc, false);
5054
5055 if (!intel_crtc->config->has_dsi_encoder)
5056 intel_ddi_disable_pipe_clock(intel_crtc);
5057
5058 for_each_encoder_on_crtc(dev, crtc, encoder)
5059 if (encoder->post_disable)
5060 encoder->post_disable(encoder);
5061
5062 if (intel_crtc->config->has_pch_encoder) {
5063 lpt_disable_pch_transcoder(dev_priv);
5064 lpt_disable_iclkip(dev_priv);
5065 intel_ddi_fdi_disable(crtc);
5066
5067 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5068 true);
5069 }
5070 }
5071
5072 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5073 {
5074 struct drm_device *dev = crtc->base.dev;
5075 struct drm_i915_private *dev_priv = dev->dev_private;
5076 struct intel_crtc_state *pipe_config = crtc->config;
5077
5078 if (!pipe_config->gmch_pfit.control)
5079 return;
5080
5081 /*
5082 * The panel fitter should only be adjusted whilst the pipe is disabled,
5083 * according to register description and PRM.
5084 */
5085 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5086 assert_pipe_disabled(dev_priv, crtc->pipe);
5087
5088 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5089 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5090
5091 /* Border color in case we don't scale up to the full screen. Black by
5092 * default, change to something else for debugging. */
5093 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5094 }
5095
5096 static enum intel_display_power_domain port_to_power_domain(enum port port)
5097 {
5098 switch (port) {
5099 case PORT_A:
5100 return POWER_DOMAIN_PORT_DDI_A_LANES;
5101 case PORT_B:
5102 return POWER_DOMAIN_PORT_DDI_B_LANES;
5103 case PORT_C:
5104 return POWER_DOMAIN_PORT_DDI_C_LANES;
5105 case PORT_D:
5106 return POWER_DOMAIN_PORT_DDI_D_LANES;
5107 case PORT_E:
5108 return POWER_DOMAIN_PORT_DDI_E_LANES;
5109 default:
5110 MISSING_CASE(port);
5111 return POWER_DOMAIN_PORT_OTHER;
5112 }
5113 }
5114
5115 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5116 {
5117 switch (port) {
5118 case PORT_A:
5119 return POWER_DOMAIN_AUX_A;
5120 case PORT_B:
5121 return POWER_DOMAIN_AUX_B;
5122 case PORT_C:
5123 return POWER_DOMAIN_AUX_C;
5124 case PORT_D:
5125 return POWER_DOMAIN_AUX_D;
5126 case PORT_E:
5127 /* FIXME: Check VBT for actual wiring of PORT E */
5128 return POWER_DOMAIN_AUX_D;
5129 default:
5130 MISSING_CASE(port);
5131 return POWER_DOMAIN_AUX_A;
5132 }
5133 }
5134
5135 enum intel_display_power_domain
5136 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5137 {
5138 struct drm_device *dev = intel_encoder->base.dev;
5139 struct intel_digital_port *intel_dig_port;
5140
5141 switch (intel_encoder->type) {
5142 case INTEL_OUTPUT_UNKNOWN:
5143 /* Only DDI platforms should ever use this output type */
5144 WARN_ON_ONCE(!HAS_DDI(dev));
5145 case INTEL_OUTPUT_DISPLAYPORT:
5146 case INTEL_OUTPUT_HDMI:
5147 case INTEL_OUTPUT_EDP:
5148 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5149 return port_to_power_domain(intel_dig_port->port);
5150 case INTEL_OUTPUT_DP_MST:
5151 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5152 return port_to_power_domain(intel_dig_port->port);
5153 case INTEL_OUTPUT_ANALOG:
5154 return POWER_DOMAIN_PORT_CRT;
5155 case INTEL_OUTPUT_DSI:
5156 return POWER_DOMAIN_PORT_DSI;
5157 default:
5158 return POWER_DOMAIN_PORT_OTHER;
5159 }
5160 }
5161
5162 enum intel_display_power_domain
5163 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5164 {
5165 struct drm_device *dev = intel_encoder->base.dev;
5166 struct intel_digital_port *intel_dig_port;
5167
5168 switch (intel_encoder->type) {
5169 case INTEL_OUTPUT_UNKNOWN:
5170 case INTEL_OUTPUT_HDMI:
5171 /*
5172 * Only DDI platforms should ever use these output types.
5173 * We can get here after the HDMI detect code has already set
5174 * the type of the shared encoder. Since we can't be sure
5175 * what's the status of the given connectors, play safe and
5176 * run the DP detection too.
5177 */
5178 WARN_ON_ONCE(!HAS_DDI(dev));
5179 case INTEL_OUTPUT_DISPLAYPORT:
5180 case INTEL_OUTPUT_EDP:
5181 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5182 return port_to_aux_power_domain(intel_dig_port->port);
5183 case INTEL_OUTPUT_DP_MST:
5184 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5185 return port_to_aux_power_domain(intel_dig_port->port);
5186 default:
5187 MISSING_CASE(intel_encoder->type);
5188 return POWER_DOMAIN_AUX_A;
5189 }
5190 }
5191
5192 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5193 struct intel_crtc_state *crtc_state)
5194 {
5195 struct drm_device *dev = crtc->dev;
5196 struct drm_encoder *encoder;
5197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5198 enum pipe pipe = intel_crtc->pipe;
5199 unsigned long mask;
5200 enum transcoder transcoder = crtc_state->cpu_transcoder;
5201
5202 if (!crtc_state->base.active)
5203 return 0;
5204
5205 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5206 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5207 if (crtc_state->pch_pfit.enabled ||
5208 crtc_state->pch_pfit.force_thru)
5209 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5210
5211 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5212 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5213
5214 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5215 }
5216
5217 if (crtc_state->shared_dpll)
5218 mask |= BIT(POWER_DOMAIN_PLLS);
5219
5220 return mask;
5221 }
5222
5223 static unsigned long
5224 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5225 struct intel_crtc_state *crtc_state)
5226 {
5227 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5229 enum intel_display_power_domain domain;
5230 unsigned long domains, new_domains, old_domains;
5231
5232 old_domains = intel_crtc->enabled_power_domains;
5233 intel_crtc->enabled_power_domains = new_domains =
5234 get_crtc_power_domains(crtc, crtc_state);
5235
5236 domains = new_domains & ~old_domains;
5237
5238 for_each_power_domain(domain, domains)
5239 intel_display_power_get(dev_priv, domain);
5240
5241 return old_domains & ~new_domains;
5242 }
5243
5244 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5245 unsigned long domains)
5246 {
5247 enum intel_display_power_domain domain;
5248
5249 for_each_power_domain(domain, domains)
5250 intel_display_power_put(dev_priv, domain);
5251 }
5252
5253 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5254 {
5255 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5256
5257 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5258 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5259 return max_cdclk_freq;
5260 else if (IS_CHERRYVIEW(dev_priv))
5261 return max_cdclk_freq*95/100;
5262 else if (INTEL_INFO(dev_priv)->gen < 4)
5263 return 2*max_cdclk_freq*90/100;
5264 else
5265 return max_cdclk_freq*90/100;
5266 }
5267
5268 static void intel_update_max_cdclk(struct drm_device *dev)
5269 {
5270 struct drm_i915_private *dev_priv = dev->dev_private;
5271
5272 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5273 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5274
5275 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5276 dev_priv->max_cdclk_freq = 675000;
5277 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5278 dev_priv->max_cdclk_freq = 540000;
5279 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5280 dev_priv->max_cdclk_freq = 450000;
5281 else
5282 dev_priv->max_cdclk_freq = 337500;
5283 } else if (IS_BROXTON(dev)) {
5284 dev_priv->max_cdclk_freq = 624000;
5285 } else if (IS_BROADWELL(dev)) {
5286 /*
5287 * FIXME with extra cooling we can allow
5288 * 540 MHz for ULX and 675 Mhz for ULT.
5289 * How can we know if extra cooling is
5290 * available? PCI ID, VTB, something else?
5291 */
5292 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5293 dev_priv->max_cdclk_freq = 450000;
5294 else if (IS_BDW_ULX(dev))
5295 dev_priv->max_cdclk_freq = 450000;
5296 else if (IS_BDW_ULT(dev))
5297 dev_priv->max_cdclk_freq = 540000;
5298 else
5299 dev_priv->max_cdclk_freq = 675000;
5300 } else if (IS_CHERRYVIEW(dev)) {
5301 dev_priv->max_cdclk_freq = 320000;
5302 } else if (IS_VALLEYVIEW(dev)) {
5303 dev_priv->max_cdclk_freq = 400000;
5304 } else {
5305 /* otherwise assume cdclk is fixed */
5306 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5307 }
5308
5309 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5310
5311 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5312 dev_priv->max_cdclk_freq);
5313
5314 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5315 dev_priv->max_dotclk_freq);
5316 }
5317
5318 static void intel_update_cdclk(struct drm_device *dev)
5319 {
5320 struct drm_i915_private *dev_priv = dev->dev_private;
5321
5322 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5323 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5324 dev_priv->cdclk_freq);
5325
5326 /*
5327 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5328 * Programmng [sic] note: bit[9:2] should be programmed to the number
5329 * of cdclk that generates 4MHz reference clock freq which is used to
5330 * generate GMBus clock. This will vary with the cdclk freq.
5331 */
5332 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5333 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5334
5335 if (dev_priv->max_cdclk_freq == 0)
5336 intel_update_max_cdclk(dev);
5337 }
5338
5339 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5340 static int skl_cdclk_decimal(int cdclk)
5341 {
5342 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5343 }
5344
5345 static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5346 {
5347 uint32_t divider;
5348 uint32_t ratio;
5349 uint32_t current_cdclk;
5350 int ret;
5351
5352 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5353 switch (cdclk) {
5354 case 144000:
5355 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5356 ratio = BXT_DE_PLL_RATIO(60);
5357 break;
5358 case 288000:
5359 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5360 ratio = BXT_DE_PLL_RATIO(60);
5361 break;
5362 case 384000:
5363 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5364 ratio = BXT_DE_PLL_RATIO(60);
5365 break;
5366 case 576000:
5367 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5368 ratio = BXT_DE_PLL_RATIO(60);
5369 break;
5370 case 624000:
5371 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5372 ratio = BXT_DE_PLL_RATIO(65);
5373 break;
5374 case 19200:
5375 /*
5376 * Bypass frequency with DE PLL disabled. Init ratio, divider
5377 * to suppress GCC warning.
5378 */
5379 ratio = 0;
5380 divider = 0;
5381 break;
5382 default:
5383 DRM_ERROR("unsupported CDCLK freq %d", cdclk);
5384
5385 return;
5386 }
5387
5388 mutex_lock(&dev_priv->rps.hw_lock);
5389 /* Inform power controller of upcoming frequency change */
5390 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5391 0x80000000);
5392 mutex_unlock(&dev_priv->rps.hw_lock);
5393
5394 if (ret) {
5395 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5396 ret, cdclk);
5397 return;
5398 }
5399
5400 current_cdclk = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5401 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5402 current_cdclk = current_cdclk * 500 + 1000;
5403
5404 /*
5405 * DE PLL has to be disabled when
5406 * - setting to 19.2MHz (bypass, PLL isn't used)
5407 * - before setting to 624MHz (PLL needs toggling)
5408 * - before setting to any frequency from 624MHz (PLL needs toggling)
5409 */
5410 if (cdclk == 19200 || cdclk == 624000 ||
5411 current_cdclk == 624000) {
5412 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5413 /* Timeout 200us */
5414 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5415 1))
5416 DRM_ERROR("timout waiting for DE PLL unlock\n");
5417 }
5418
5419 if (cdclk != 19200) {
5420 uint32_t val;
5421
5422 val = I915_READ(BXT_DE_PLL_CTL);
5423 val &= ~BXT_DE_PLL_RATIO_MASK;
5424 val |= ratio;
5425 I915_WRITE(BXT_DE_PLL_CTL, val);
5426
5427 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5428 /* Timeout 200us */
5429 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5430 DRM_ERROR("timeout waiting for DE PLL lock\n");
5431
5432 val = divider | skl_cdclk_decimal(cdclk);
5433 /*
5434 * FIXME if only the cd2x divider needs changing, it could be done
5435 * without shutting off the pipe (if only one pipe is active).
5436 */
5437 val |= BXT_CDCLK_CD2X_PIPE_NONE;
5438 /*
5439 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5440 * enable otherwise.
5441 */
5442 if (cdclk >= 500000)
5443 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5444 I915_WRITE(CDCLK_CTL, val);
5445 }
5446
5447 mutex_lock(&dev_priv->rps.hw_lock);
5448 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5449 DIV_ROUND_UP(cdclk, 25000));
5450 mutex_unlock(&dev_priv->rps.hw_lock);
5451
5452 if (ret) {
5453 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5454 ret, cdclk);
5455 return;
5456 }
5457
5458 intel_update_cdclk(dev_priv->dev);
5459 }
5460
5461 static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv)
5462 {
5463 if (!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE))
5464 return false;
5465
5466 /* TODO: Check for a valid CDCLK rate */
5467
5468 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_REQUEST)) {
5469 DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power not requested\n");
5470
5471 return false;
5472 }
5473
5474 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) {
5475 DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power hasn't settled\n");
5476
5477 return false;
5478 }
5479
5480 return true;
5481 }
5482
5483 bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv)
5484 {
5485 return broxton_cdclk_is_enabled(dev_priv);
5486 }
5487
5488 void broxton_init_cdclk(struct drm_i915_private *dev_priv)
5489 {
5490 /* check if cd clock is enabled */
5491 if (broxton_cdclk_is_enabled(dev_priv)) {
5492 DRM_DEBUG_KMS("CDCLK already enabled, won't reprogram it\n");
5493 return;
5494 }
5495
5496 DRM_DEBUG_KMS("CDCLK not enabled, enabling it\n");
5497
5498 /*
5499 * FIXME:
5500 * - The initial CDCLK needs to be read from VBT.
5501 * Need to make this change after VBT has changes for BXT.
5502 * - check if setting the max (or any) cdclk freq is really necessary
5503 * here, it belongs to modeset time
5504 */
5505 broxton_set_cdclk(dev_priv, 624000);
5506
5507 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5508 POSTING_READ(DBUF_CTL);
5509
5510 udelay(10);
5511
5512 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5513 DRM_ERROR("DBuf power enable timeout!\n");
5514 }
5515
5516 void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
5517 {
5518 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5519 POSTING_READ(DBUF_CTL);
5520
5521 udelay(10);
5522
5523 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5524 DRM_ERROR("DBuf power disable timeout!\n");
5525
5526 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5527 broxton_set_cdclk(dev_priv, 19200);
5528 }
5529
5530 static const struct skl_cdclk_entry {
5531 unsigned int freq;
5532 unsigned int vco;
5533 } skl_cdclk_frequencies[] = {
5534 { .freq = 308570, .vco = 8640 },
5535 { .freq = 337500, .vco = 8100 },
5536 { .freq = 432000, .vco = 8640 },
5537 { .freq = 450000, .vco = 8100 },
5538 { .freq = 540000, .vco = 8100 },
5539 { .freq = 617140, .vco = 8640 },
5540 { .freq = 675000, .vco = 8100 },
5541 };
5542
5543 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5544 {
5545 unsigned int i;
5546
5547 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5548 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5549
5550 if (e->freq == freq)
5551 return e->vco;
5552 }
5553
5554 return 8100;
5555 }
5556
5557 static void
5558 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
5559 {
5560 int min_cdclk;
5561 u32 val;
5562
5563 /* select the minimum CDCLK before enabling DPLL 0 */
5564 if (vco == 8640)
5565 min_cdclk = 308570;
5566 else
5567 min_cdclk = 337500;
5568
5569 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
5570 I915_WRITE(CDCLK_CTL, val);
5571 POSTING_READ(CDCLK_CTL);
5572
5573 /*
5574 * We always enable DPLL0 with the lowest link rate possible, but still
5575 * taking into account the VCO required to operate the eDP panel at the
5576 * desired frequency. The usual DP link rates operate with a VCO of
5577 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5578 * The modeset code is responsible for the selection of the exact link
5579 * rate later on, with the constraint of choosing a frequency that
5580 * works with required_vco.
5581 */
5582 val = I915_READ(DPLL_CTRL1);
5583
5584 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5585 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5586 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5587 if (vco == 8640)
5588 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5589 SKL_DPLL0);
5590 else
5591 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5592 SKL_DPLL0);
5593
5594 I915_WRITE(DPLL_CTRL1, val);
5595 POSTING_READ(DPLL_CTRL1);
5596
5597 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5598
5599 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5600 DRM_ERROR("DPLL0 not locked\n");
5601 }
5602
5603 static void
5604 skl_dpll0_disable(struct drm_i915_private *dev_priv)
5605 {
5606 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5607 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5608 DRM_ERROR("Couldn't disable DPLL0\n");
5609 }
5610
5611 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5612 {
5613 int ret;
5614 u32 val;
5615
5616 /* inform PCU we want to change CDCLK */
5617 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5618 mutex_lock(&dev_priv->rps.hw_lock);
5619 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5620 mutex_unlock(&dev_priv->rps.hw_lock);
5621
5622 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5623 }
5624
5625 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5626 {
5627 unsigned int i;
5628
5629 for (i = 0; i < 15; i++) {
5630 if (skl_cdclk_pcu_ready(dev_priv))
5631 return true;
5632 udelay(10);
5633 }
5634
5635 return false;
5636 }
5637
5638 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5639 {
5640 struct drm_device *dev = dev_priv->dev;
5641 u32 freq_select, pcu_ack;
5642
5643 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", cdclk);
5644
5645 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5646 DRM_ERROR("failed to inform PCU about cdclk change\n");
5647 return;
5648 }
5649
5650 /* set CDCLK_CTL */
5651 switch (cdclk) {
5652 case 450000:
5653 case 432000:
5654 freq_select = CDCLK_FREQ_450_432;
5655 pcu_ack = 1;
5656 break;
5657 case 540000:
5658 freq_select = CDCLK_FREQ_540;
5659 pcu_ack = 2;
5660 break;
5661 case 308570:
5662 case 337500:
5663 default:
5664 freq_select = CDCLK_FREQ_337_308;
5665 pcu_ack = 0;
5666 break;
5667 case 617140:
5668 case 675000:
5669 freq_select = CDCLK_FREQ_675_617;
5670 pcu_ack = 3;
5671 break;
5672 }
5673
5674 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
5675 POSTING_READ(CDCLK_CTL);
5676
5677 /* inform PCU of the change */
5678 mutex_lock(&dev_priv->rps.hw_lock);
5679 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5680 mutex_unlock(&dev_priv->rps.hw_lock);
5681
5682 intel_update_cdclk(dev);
5683 }
5684
5685 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5686 {
5687 /* disable DBUF power */
5688 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5689 POSTING_READ(DBUF_CTL);
5690
5691 udelay(10);
5692
5693 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5694 DRM_ERROR("DBuf power disable timeout\n");
5695
5696 skl_dpll0_disable(dev_priv);
5697 }
5698
5699 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5700 {
5701 unsigned int vco;
5702
5703 /* DPLL0 not enabled (happens on early BIOS versions) */
5704 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5705 /* enable DPLL0 */
5706 vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5707 skl_dpll0_enable(dev_priv, vco);
5708 }
5709
5710 /* set CDCLK to the frequency the BIOS chose */
5711 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5712
5713 /* enable DBUF power */
5714 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5715 POSTING_READ(DBUF_CTL);
5716
5717 udelay(10);
5718
5719 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5720 DRM_ERROR("DBuf power enable timeout\n");
5721 }
5722
5723 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5724 {
5725 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5726 uint32_t cdctl = I915_READ(CDCLK_CTL);
5727 int freq = dev_priv->skl_boot_cdclk;
5728
5729 /*
5730 * check if the pre-os intialized the display
5731 * There is SWF18 scratchpad register defined which is set by the
5732 * pre-os which can be used by the OS drivers to check the status
5733 */
5734 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5735 goto sanitize;
5736
5737 /* Is PLL enabled and locked ? */
5738 if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5739 goto sanitize;
5740
5741 /* DPLL okay; verify the cdclock
5742 *
5743 * Noticed in some instances that the freq selection is correct but
5744 * decimal part is programmed wrong from BIOS where pre-os does not
5745 * enable display. Verify the same as well.
5746 */
5747 if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5748 /* All well; nothing to sanitize */
5749 return false;
5750 sanitize:
5751 /*
5752 * As of now initialize with max cdclk till
5753 * we get dynamic cdclk support
5754 * */
5755 dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5756 skl_init_cdclk(dev_priv);
5757
5758 /* we did have to sanitize */
5759 return true;
5760 }
5761
5762 /* Adjust CDclk dividers to allow high res or save power if possible */
5763 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5764 {
5765 struct drm_i915_private *dev_priv = dev->dev_private;
5766 u32 val, cmd;
5767
5768 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5769 != dev_priv->cdclk_freq);
5770
5771 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5772 cmd = 2;
5773 else if (cdclk == 266667)
5774 cmd = 1;
5775 else
5776 cmd = 0;
5777
5778 mutex_lock(&dev_priv->rps.hw_lock);
5779 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5780 val &= ~DSPFREQGUAR_MASK;
5781 val |= (cmd << DSPFREQGUAR_SHIFT);
5782 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5783 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5784 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5785 50)) {
5786 DRM_ERROR("timed out waiting for CDclk change\n");
5787 }
5788 mutex_unlock(&dev_priv->rps.hw_lock);
5789
5790 mutex_lock(&dev_priv->sb_lock);
5791
5792 if (cdclk == 400000) {
5793 u32 divider;
5794
5795 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5796
5797 /* adjust cdclk divider */
5798 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5799 val &= ~CCK_FREQUENCY_VALUES;
5800 val |= divider;
5801 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5802
5803 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5804 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5805 50))
5806 DRM_ERROR("timed out waiting for CDclk change\n");
5807 }
5808
5809 /* adjust self-refresh exit latency value */
5810 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5811 val &= ~0x7f;
5812
5813 /*
5814 * For high bandwidth configs, we set a higher latency in the bunit
5815 * so that the core display fetch happens in time to avoid underruns.
5816 */
5817 if (cdclk == 400000)
5818 val |= 4500 / 250; /* 4.5 usec */
5819 else
5820 val |= 3000 / 250; /* 3.0 usec */
5821 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5822
5823 mutex_unlock(&dev_priv->sb_lock);
5824
5825 intel_update_cdclk(dev);
5826 }
5827
5828 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5829 {
5830 struct drm_i915_private *dev_priv = dev->dev_private;
5831 u32 val, cmd;
5832
5833 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5834 != dev_priv->cdclk_freq);
5835
5836 switch (cdclk) {
5837 case 333333:
5838 case 320000:
5839 case 266667:
5840 case 200000:
5841 break;
5842 default:
5843 MISSING_CASE(cdclk);
5844 return;
5845 }
5846
5847 /*
5848 * Specs are full of misinformation, but testing on actual
5849 * hardware has shown that we just need to write the desired
5850 * CCK divider into the Punit register.
5851 */
5852 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5853
5854 mutex_lock(&dev_priv->rps.hw_lock);
5855 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5856 val &= ~DSPFREQGUAR_MASK_CHV;
5857 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5858 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5859 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5860 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5861 50)) {
5862 DRM_ERROR("timed out waiting for CDclk change\n");
5863 }
5864 mutex_unlock(&dev_priv->rps.hw_lock);
5865
5866 intel_update_cdclk(dev);
5867 }
5868
5869 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5870 int max_pixclk)
5871 {
5872 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5873 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5874
5875 /*
5876 * Really only a few cases to deal with, as only 4 CDclks are supported:
5877 * 200MHz
5878 * 267MHz
5879 * 320/333MHz (depends on HPLL freq)
5880 * 400MHz (VLV only)
5881 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5882 * of the lower bin and adjust if needed.
5883 *
5884 * We seem to get an unstable or solid color picture at 200MHz.
5885 * Not sure what's wrong. For now use 200MHz only when all pipes
5886 * are off.
5887 */
5888 if (!IS_CHERRYVIEW(dev_priv) &&
5889 max_pixclk > freq_320*limit/100)
5890 return 400000;
5891 else if (max_pixclk > 266667*limit/100)
5892 return freq_320;
5893 else if (max_pixclk > 0)
5894 return 266667;
5895 else
5896 return 200000;
5897 }
5898
5899 static int broxton_calc_cdclk(int max_pixclk)
5900 {
5901 /*
5902 * FIXME:
5903 * - set 19.2MHz bypass frequency if there are no active pipes
5904 */
5905 if (max_pixclk > 576000)
5906 return 624000;
5907 else if (max_pixclk > 384000)
5908 return 576000;
5909 else if (max_pixclk > 288000)
5910 return 384000;
5911 else if (max_pixclk > 144000)
5912 return 288000;
5913 else
5914 return 144000;
5915 }
5916
5917 /* Compute the max pixel clock for new configuration. */
5918 static int intel_mode_max_pixclk(struct drm_device *dev,
5919 struct drm_atomic_state *state)
5920 {
5921 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5922 struct drm_i915_private *dev_priv = dev->dev_private;
5923 struct drm_crtc *crtc;
5924 struct drm_crtc_state *crtc_state;
5925 unsigned max_pixclk = 0, i;
5926 enum pipe pipe;
5927
5928 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
5929 sizeof(intel_state->min_pixclk));
5930
5931 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5932 int pixclk = 0;
5933
5934 if (crtc_state->enable)
5935 pixclk = crtc_state->adjusted_mode.crtc_clock;
5936
5937 intel_state->min_pixclk[i] = pixclk;
5938 }
5939
5940 for_each_pipe(dev_priv, pipe)
5941 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
5942
5943 return max_pixclk;
5944 }
5945
5946 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5947 {
5948 struct drm_device *dev = state->dev;
5949 struct drm_i915_private *dev_priv = dev->dev_private;
5950 int max_pixclk = intel_mode_max_pixclk(dev, state);
5951 struct intel_atomic_state *intel_state =
5952 to_intel_atomic_state(state);
5953
5954 intel_state->cdclk = intel_state->dev_cdclk =
5955 valleyview_calc_cdclk(dev_priv, max_pixclk);
5956
5957 if (!intel_state->active_crtcs)
5958 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
5959
5960 return 0;
5961 }
5962
5963 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5964 {
5965 int max_pixclk = ilk_max_pixel_rate(state);
5966 struct intel_atomic_state *intel_state =
5967 to_intel_atomic_state(state);
5968
5969 intel_state->cdclk = intel_state->dev_cdclk =
5970 broxton_calc_cdclk(max_pixclk);
5971
5972 if (!intel_state->active_crtcs)
5973 intel_state->dev_cdclk = broxton_calc_cdclk(0);
5974
5975 return 0;
5976 }
5977
5978 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5979 {
5980 unsigned int credits, default_credits;
5981
5982 if (IS_CHERRYVIEW(dev_priv))
5983 default_credits = PFI_CREDIT(12);
5984 else
5985 default_credits = PFI_CREDIT(8);
5986
5987 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
5988 /* CHV suggested value is 31 or 63 */
5989 if (IS_CHERRYVIEW(dev_priv))
5990 credits = PFI_CREDIT_63;
5991 else
5992 credits = PFI_CREDIT(15);
5993 } else {
5994 credits = default_credits;
5995 }
5996
5997 /*
5998 * WA - write default credits before re-programming
5999 * FIXME: should we also set the resend bit here?
6000 */
6001 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6002 default_credits);
6003
6004 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6005 credits | PFI_CREDIT_RESEND);
6006
6007 /*
6008 * FIXME is this guaranteed to clear
6009 * immediately or should we poll for it?
6010 */
6011 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6012 }
6013
6014 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6015 {
6016 struct drm_device *dev = old_state->dev;
6017 struct drm_i915_private *dev_priv = dev->dev_private;
6018 struct intel_atomic_state *old_intel_state =
6019 to_intel_atomic_state(old_state);
6020 unsigned req_cdclk = old_intel_state->dev_cdclk;
6021
6022 /*
6023 * FIXME: We can end up here with all power domains off, yet
6024 * with a CDCLK frequency other than the minimum. To account
6025 * for this take the PIPE-A power domain, which covers the HW
6026 * blocks needed for the following programming. This can be
6027 * removed once it's guaranteed that we get here either with
6028 * the minimum CDCLK set, or the required power domains
6029 * enabled.
6030 */
6031 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6032
6033 if (IS_CHERRYVIEW(dev))
6034 cherryview_set_cdclk(dev, req_cdclk);
6035 else
6036 valleyview_set_cdclk(dev, req_cdclk);
6037
6038 vlv_program_pfi_credits(dev_priv);
6039
6040 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6041 }
6042
6043 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6044 {
6045 struct drm_device *dev = crtc->dev;
6046 struct drm_i915_private *dev_priv = to_i915(dev);
6047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6048 struct intel_encoder *encoder;
6049 struct intel_crtc_state *pipe_config =
6050 to_intel_crtc_state(crtc->state);
6051 int pipe = intel_crtc->pipe;
6052
6053 if (WARN_ON(intel_crtc->active))
6054 return;
6055
6056 if (intel_crtc->config->has_dp_encoder)
6057 intel_dp_set_m_n(intel_crtc, M1_N1);
6058
6059 intel_set_pipe_timings(intel_crtc);
6060 intel_set_pipe_src_size(intel_crtc);
6061
6062 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6063 struct drm_i915_private *dev_priv = dev->dev_private;
6064
6065 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6066 I915_WRITE(CHV_CANVAS(pipe), 0);
6067 }
6068
6069 i9xx_set_pipeconf(intel_crtc);
6070
6071 intel_crtc->active = true;
6072
6073 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6074
6075 for_each_encoder_on_crtc(dev, crtc, encoder)
6076 if (encoder->pre_pll_enable)
6077 encoder->pre_pll_enable(encoder);
6078
6079 if (IS_CHERRYVIEW(dev)) {
6080 chv_prepare_pll(intel_crtc, intel_crtc->config);
6081 chv_enable_pll(intel_crtc, intel_crtc->config);
6082 } else {
6083 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6084 vlv_enable_pll(intel_crtc, intel_crtc->config);
6085 }
6086
6087 for_each_encoder_on_crtc(dev, crtc, encoder)
6088 if (encoder->pre_enable)
6089 encoder->pre_enable(encoder);
6090
6091 i9xx_pfit_enable(intel_crtc);
6092
6093 intel_color_load_luts(&pipe_config->base);
6094
6095 intel_update_watermarks(crtc);
6096 intel_enable_pipe(intel_crtc);
6097
6098 assert_vblank_disabled(crtc);
6099 drm_crtc_vblank_on(crtc);
6100
6101 for_each_encoder_on_crtc(dev, crtc, encoder)
6102 encoder->enable(encoder);
6103 }
6104
6105 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6106 {
6107 struct drm_device *dev = crtc->base.dev;
6108 struct drm_i915_private *dev_priv = dev->dev_private;
6109
6110 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6111 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6112 }
6113
6114 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6115 {
6116 struct drm_device *dev = crtc->dev;
6117 struct drm_i915_private *dev_priv = to_i915(dev);
6118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6119 struct intel_encoder *encoder;
6120 struct intel_crtc_state *pipe_config =
6121 to_intel_crtc_state(crtc->state);
6122 enum pipe pipe = intel_crtc->pipe;
6123
6124 if (WARN_ON(intel_crtc->active))
6125 return;
6126
6127 i9xx_set_pll_dividers(intel_crtc);
6128
6129 if (intel_crtc->config->has_dp_encoder)
6130 intel_dp_set_m_n(intel_crtc, M1_N1);
6131
6132 intel_set_pipe_timings(intel_crtc);
6133 intel_set_pipe_src_size(intel_crtc);
6134
6135 i9xx_set_pipeconf(intel_crtc);
6136
6137 intel_crtc->active = true;
6138
6139 if (!IS_GEN2(dev))
6140 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6141
6142 for_each_encoder_on_crtc(dev, crtc, encoder)
6143 if (encoder->pre_enable)
6144 encoder->pre_enable(encoder);
6145
6146 i9xx_enable_pll(intel_crtc);
6147
6148 i9xx_pfit_enable(intel_crtc);
6149
6150 intel_color_load_luts(&pipe_config->base);
6151
6152 intel_update_watermarks(crtc);
6153 intel_enable_pipe(intel_crtc);
6154
6155 assert_vblank_disabled(crtc);
6156 drm_crtc_vblank_on(crtc);
6157
6158 for_each_encoder_on_crtc(dev, crtc, encoder)
6159 encoder->enable(encoder);
6160 }
6161
6162 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6163 {
6164 struct drm_device *dev = crtc->base.dev;
6165 struct drm_i915_private *dev_priv = dev->dev_private;
6166
6167 if (!crtc->config->gmch_pfit.control)
6168 return;
6169
6170 assert_pipe_disabled(dev_priv, crtc->pipe);
6171
6172 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6173 I915_READ(PFIT_CONTROL));
6174 I915_WRITE(PFIT_CONTROL, 0);
6175 }
6176
6177 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6178 {
6179 struct drm_device *dev = crtc->dev;
6180 struct drm_i915_private *dev_priv = dev->dev_private;
6181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6182 struct intel_encoder *encoder;
6183 int pipe = intel_crtc->pipe;
6184
6185 /*
6186 * On gen2 planes are double buffered but the pipe isn't, so we must
6187 * wait for planes to fully turn off before disabling the pipe.
6188 */
6189 if (IS_GEN2(dev))
6190 intel_wait_for_vblank(dev, pipe);
6191
6192 for_each_encoder_on_crtc(dev, crtc, encoder)
6193 encoder->disable(encoder);
6194
6195 drm_crtc_vblank_off(crtc);
6196 assert_vblank_disabled(crtc);
6197
6198 intel_disable_pipe(intel_crtc);
6199
6200 i9xx_pfit_disable(intel_crtc);
6201
6202 for_each_encoder_on_crtc(dev, crtc, encoder)
6203 if (encoder->post_disable)
6204 encoder->post_disable(encoder);
6205
6206 if (!intel_crtc->config->has_dsi_encoder) {
6207 if (IS_CHERRYVIEW(dev))
6208 chv_disable_pll(dev_priv, pipe);
6209 else if (IS_VALLEYVIEW(dev))
6210 vlv_disable_pll(dev_priv, pipe);
6211 else
6212 i9xx_disable_pll(intel_crtc);
6213 }
6214
6215 for_each_encoder_on_crtc(dev, crtc, encoder)
6216 if (encoder->post_pll_disable)
6217 encoder->post_pll_disable(encoder);
6218
6219 if (!IS_GEN2(dev))
6220 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6221 }
6222
6223 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6224 {
6225 struct intel_encoder *encoder;
6226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6227 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6228 enum intel_display_power_domain domain;
6229 unsigned long domains;
6230
6231 if (!intel_crtc->active)
6232 return;
6233
6234 if (to_intel_plane_state(crtc->primary->state)->visible) {
6235 WARN_ON(list_empty(&intel_crtc->flip_work));
6236
6237 intel_pre_disable_primary_noatomic(crtc);
6238
6239 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6240 to_intel_plane_state(crtc->primary->state)->visible = false;
6241 }
6242
6243 dev_priv->display.crtc_disable(crtc);
6244
6245 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n",
6246 crtc->base.id);
6247
6248 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6249 crtc->state->active = false;
6250 intel_crtc->active = false;
6251 crtc->enabled = false;
6252 crtc->state->connector_mask = 0;
6253 crtc->state->encoder_mask = 0;
6254
6255 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6256 encoder->base.crtc = NULL;
6257
6258 intel_fbc_disable(intel_crtc);
6259 intel_update_watermarks(crtc);
6260 intel_disable_shared_dpll(intel_crtc);
6261
6262 domains = intel_crtc->enabled_power_domains;
6263 for_each_power_domain(domain, domains)
6264 intel_display_power_put(dev_priv, domain);
6265 intel_crtc->enabled_power_domains = 0;
6266
6267 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6268 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6269 }
6270
6271 /*
6272 * turn all crtc's off, but do not adjust state
6273 * This has to be paired with a call to intel_modeset_setup_hw_state.
6274 */
6275 int intel_display_suspend(struct drm_device *dev)
6276 {
6277 struct drm_i915_private *dev_priv = to_i915(dev);
6278 struct drm_atomic_state *state;
6279 int ret;
6280
6281 state = drm_atomic_helper_suspend(dev);
6282 ret = PTR_ERR_OR_ZERO(state);
6283 if (ret)
6284 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6285 else
6286 dev_priv->modeset_restore_state = state;
6287 return ret;
6288 }
6289
6290 void intel_encoder_destroy(struct drm_encoder *encoder)
6291 {
6292 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6293
6294 drm_encoder_cleanup(encoder);
6295 kfree(intel_encoder);
6296 }
6297
6298 /* Cross check the actual hw state with our own modeset state tracking (and it's
6299 * internal consistency). */
6300 static void intel_connector_verify_state(struct intel_connector *connector)
6301 {
6302 struct drm_crtc *crtc = connector->base.state->crtc;
6303
6304 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6305 connector->base.base.id,
6306 connector->base.name);
6307
6308 if (connector->get_hw_state(connector)) {
6309 struct intel_encoder *encoder = connector->encoder;
6310 struct drm_connector_state *conn_state = connector->base.state;
6311
6312 I915_STATE_WARN(!crtc,
6313 "connector enabled without attached crtc\n");
6314
6315 if (!crtc)
6316 return;
6317
6318 I915_STATE_WARN(!crtc->state->active,
6319 "connector is active, but attached crtc isn't\n");
6320
6321 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6322 return;
6323
6324 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6325 "atomic encoder doesn't match attached encoder\n");
6326
6327 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6328 "attached encoder crtc differs from connector crtc\n");
6329 } else {
6330 I915_STATE_WARN(crtc && crtc->state->active,
6331 "attached crtc is active, but connector isn't\n");
6332 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6333 "best encoder set without crtc!\n");
6334 }
6335 }
6336
6337 int intel_connector_init(struct intel_connector *connector)
6338 {
6339 drm_atomic_helper_connector_reset(&connector->base);
6340
6341 if (!connector->base.state)
6342 return -ENOMEM;
6343
6344 return 0;
6345 }
6346
6347 struct intel_connector *intel_connector_alloc(void)
6348 {
6349 struct intel_connector *connector;
6350
6351 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6352 if (!connector)
6353 return NULL;
6354
6355 if (intel_connector_init(connector) < 0) {
6356 kfree(connector);
6357 return NULL;
6358 }
6359
6360 return connector;
6361 }
6362
6363 /* Simple connector->get_hw_state implementation for encoders that support only
6364 * one connector and no cloning and hence the encoder state determines the state
6365 * of the connector. */
6366 bool intel_connector_get_hw_state(struct intel_connector *connector)
6367 {
6368 enum pipe pipe = 0;
6369 struct intel_encoder *encoder = connector->encoder;
6370
6371 return encoder->get_hw_state(encoder, &pipe);
6372 }
6373
6374 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6375 {
6376 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6377 return crtc_state->fdi_lanes;
6378
6379 return 0;
6380 }
6381
6382 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6383 struct intel_crtc_state *pipe_config)
6384 {
6385 struct drm_atomic_state *state = pipe_config->base.state;
6386 struct intel_crtc *other_crtc;
6387 struct intel_crtc_state *other_crtc_state;
6388
6389 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6390 pipe_name(pipe), pipe_config->fdi_lanes);
6391 if (pipe_config->fdi_lanes > 4) {
6392 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6393 pipe_name(pipe), pipe_config->fdi_lanes);
6394 return -EINVAL;
6395 }
6396
6397 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6398 if (pipe_config->fdi_lanes > 2) {
6399 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6400 pipe_config->fdi_lanes);
6401 return -EINVAL;
6402 } else {
6403 return 0;
6404 }
6405 }
6406
6407 if (INTEL_INFO(dev)->num_pipes == 2)
6408 return 0;
6409
6410 /* Ivybridge 3 pipe is really complicated */
6411 switch (pipe) {
6412 case PIPE_A:
6413 return 0;
6414 case PIPE_B:
6415 if (pipe_config->fdi_lanes <= 2)
6416 return 0;
6417
6418 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6419 other_crtc_state =
6420 intel_atomic_get_crtc_state(state, other_crtc);
6421 if (IS_ERR(other_crtc_state))
6422 return PTR_ERR(other_crtc_state);
6423
6424 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6425 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6426 pipe_name(pipe), pipe_config->fdi_lanes);
6427 return -EINVAL;
6428 }
6429 return 0;
6430 case PIPE_C:
6431 if (pipe_config->fdi_lanes > 2) {
6432 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6433 pipe_name(pipe), pipe_config->fdi_lanes);
6434 return -EINVAL;
6435 }
6436
6437 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6438 other_crtc_state =
6439 intel_atomic_get_crtc_state(state, other_crtc);
6440 if (IS_ERR(other_crtc_state))
6441 return PTR_ERR(other_crtc_state);
6442
6443 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6444 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6445 return -EINVAL;
6446 }
6447 return 0;
6448 default:
6449 BUG();
6450 }
6451 }
6452
6453 #define RETRY 1
6454 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6455 struct intel_crtc_state *pipe_config)
6456 {
6457 struct drm_device *dev = intel_crtc->base.dev;
6458 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6459 int lane, link_bw, fdi_dotclock, ret;
6460 bool needs_recompute = false;
6461
6462 retry:
6463 /* FDI is a binary signal running at ~2.7GHz, encoding
6464 * each output octet as 10 bits. The actual frequency
6465 * is stored as a divider into a 100MHz clock, and the
6466 * mode pixel clock is stored in units of 1KHz.
6467 * Hence the bw of each lane in terms of the mode signal
6468 * is:
6469 */
6470 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6471
6472 fdi_dotclock = adjusted_mode->crtc_clock;
6473
6474 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6475 pipe_config->pipe_bpp);
6476
6477 pipe_config->fdi_lanes = lane;
6478
6479 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6480 link_bw, &pipe_config->fdi_m_n);
6481
6482 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6483 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6484 pipe_config->pipe_bpp -= 2*3;
6485 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6486 pipe_config->pipe_bpp);
6487 needs_recompute = true;
6488 pipe_config->bw_constrained = true;
6489
6490 goto retry;
6491 }
6492
6493 if (needs_recompute)
6494 return RETRY;
6495
6496 return ret;
6497 }
6498
6499 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6500 struct intel_crtc_state *pipe_config)
6501 {
6502 if (pipe_config->pipe_bpp > 24)
6503 return false;
6504
6505 /* HSW can handle pixel rate up to cdclk? */
6506 if (IS_HASWELL(dev_priv))
6507 return true;
6508
6509 /*
6510 * We compare against max which means we must take
6511 * the increased cdclk requirement into account when
6512 * calculating the new cdclk.
6513 *
6514 * Should measure whether using a lower cdclk w/o IPS
6515 */
6516 return ilk_pipe_pixel_rate(pipe_config) <=
6517 dev_priv->max_cdclk_freq * 95 / 100;
6518 }
6519
6520 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6521 struct intel_crtc_state *pipe_config)
6522 {
6523 struct drm_device *dev = crtc->base.dev;
6524 struct drm_i915_private *dev_priv = dev->dev_private;
6525
6526 pipe_config->ips_enabled = i915.enable_ips &&
6527 hsw_crtc_supports_ips(crtc) &&
6528 pipe_config_supports_ips(dev_priv, pipe_config);
6529 }
6530
6531 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6532 {
6533 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6534
6535 /* GDG double wide on either pipe, otherwise pipe A only */
6536 return INTEL_INFO(dev_priv)->gen < 4 &&
6537 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6538 }
6539
6540 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6541 struct intel_crtc_state *pipe_config)
6542 {
6543 struct drm_device *dev = crtc->base.dev;
6544 struct drm_i915_private *dev_priv = dev->dev_private;
6545 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6546
6547 /* FIXME should check pixel clock limits on all platforms */
6548 if (INTEL_INFO(dev)->gen < 4) {
6549 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6550
6551 /*
6552 * Enable double wide mode when the dot clock
6553 * is > 90% of the (display) core speed.
6554 */
6555 if (intel_crtc_supports_double_wide(crtc) &&
6556 adjusted_mode->crtc_clock > clock_limit) {
6557 clock_limit *= 2;
6558 pipe_config->double_wide = true;
6559 }
6560
6561 if (adjusted_mode->crtc_clock > clock_limit) {
6562 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6563 adjusted_mode->crtc_clock, clock_limit,
6564 yesno(pipe_config->double_wide));
6565 return -EINVAL;
6566 }
6567 }
6568
6569 /*
6570 * Pipe horizontal size must be even in:
6571 * - DVO ganged mode
6572 * - LVDS dual channel mode
6573 * - Double wide pipe
6574 */
6575 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6576 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6577 pipe_config->pipe_src_w &= ~1;
6578
6579 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6580 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6581 */
6582 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6583 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6584 return -EINVAL;
6585
6586 if (HAS_IPS(dev))
6587 hsw_compute_ips_config(crtc, pipe_config);
6588
6589 if (pipe_config->has_pch_encoder)
6590 return ironlake_fdi_compute_config(crtc, pipe_config);
6591
6592 return 0;
6593 }
6594
6595 static int skylake_get_display_clock_speed(struct drm_device *dev)
6596 {
6597 struct drm_i915_private *dev_priv = to_i915(dev);
6598 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6599 uint32_t cdctl = I915_READ(CDCLK_CTL);
6600 uint32_t linkrate;
6601
6602 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6603 return 24000; /* 24MHz is the cd freq with NSSC ref */
6604
6605 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6606 return 540000;
6607
6608 linkrate = (I915_READ(DPLL_CTRL1) &
6609 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6610
6611 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6612 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6613 /* vco 8640 */
6614 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6615 case CDCLK_FREQ_450_432:
6616 return 432000;
6617 case CDCLK_FREQ_337_308:
6618 return 308570;
6619 case CDCLK_FREQ_675_617:
6620 return 617140;
6621 default:
6622 WARN(1, "Unknown cd freq selection\n");
6623 }
6624 } else {
6625 /* vco 8100 */
6626 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6627 case CDCLK_FREQ_450_432:
6628 return 450000;
6629 case CDCLK_FREQ_337_308:
6630 return 337500;
6631 case CDCLK_FREQ_675_617:
6632 return 675000;
6633 default:
6634 WARN(1, "Unknown cd freq selection\n");
6635 }
6636 }
6637
6638 /* error case, do as if DPLL0 isn't enabled */
6639 return 24000;
6640 }
6641
6642 static int broxton_get_display_clock_speed(struct drm_device *dev)
6643 {
6644 struct drm_i915_private *dev_priv = to_i915(dev);
6645 uint32_t cdctl = I915_READ(CDCLK_CTL);
6646 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6647 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6648 int cdclk;
6649
6650 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6651 return 19200;
6652
6653 cdclk = 19200 * pll_ratio / 2;
6654
6655 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6656 case BXT_CDCLK_CD2X_DIV_SEL_1:
6657 return cdclk; /* 576MHz or 624MHz */
6658 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6659 return cdclk * 2 / 3; /* 384MHz */
6660 case BXT_CDCLK_CD2X_DIV_SEL_2:
6661 return cdclk / 2; /* 288MHz */
6662 case BXT_CDCLK_CD2X_DIV_SEL_4:
6663 return cdclk / 4; /* 144MHz */
6664 }
6665
6666 /* error case, do as if DE PLL isn't enabled */
6667 return 19200;
6668 }
6669
6670 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6671 {
6672 struct drm_i915_private *dev_priv = dev->dev_private;
6673 uint32_t lcpll = I915_READ(LCPLL_CTL);
6674 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6675
6676 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6677 return 800000;
6678 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6679 return 450000;
6680 else if (freq == LCPLL_CLK_FREQ_450)
6681 return 450000;
6682 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6683 return 540000;
6684 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6685 return 337500;
6686 else
6687 return 675000;
6688 }
6689
6690 static int haswell_get_display_clock_speed(struct drm_device *dev)
6691 {
6692 struct drm_i915_private *dev_priv = dev->dev_private;
6693 uint32_t lcpll = I915_READ(LCPLL_CTL);
6694 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6695
6696 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6697 return 800000;
6698 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6699 return 450000;
6700 else if (freq == LCPLL_CLK_FREQ_450)
6701 return 450000;
6702 else if (IS_HSW_ULT(dev))
6703 return 337500;
6704 else
6705 return 540000;
6706 }
6707
6708 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6709 {
6710 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6711 CCK_DISPLAY_CLOCK_CONTROL);
6712 }
6713
6714 static int ilk_get_display_clock_speed(struct drm_device *dev)
6715 {
6716 return 450000;
6717 }
6718
6719 static int i945_get_display_clock_speed(struct drm_device *dev)
6720 {
6721 return 400000;
6722 }
6723
6724 static int i915_get_display_clock_speed(struct drm_device *dev)
6725 {
6726 return 333333;
6727 }
6728
6729 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6730 {
6731 return 200000;
6732 }
6733
6734 static int pnv_get_display_clock_speed(struct drm_device *dev)
6735 {
6736 u16 gcfgc = 0;
6737
6738 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6739
6740 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6741 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6742 return 266667;
6743 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6744 return 333333;
6745 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6746 return 444444;
6747 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6748 return 200000;
6749 default:
6750 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6751 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6752 return 133333;
6753 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6754 return 166667;
6755 }
6756 }
6757
6758 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6759 {
6760 u16 gcfgc = 0;
6761
6762 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6763
6764 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6765 return 133333;
6766 else {
6767 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6768 case GC_DISPLAY_CLOCK_333_MHZ:
6769 return 333333;
6770 default:
6771 case GC_DISPLAY_CLOCK_190_200_MHZ:
6772 return 190000;
6773 }
6774 }
6775 }
6776
6777 static int i865_get_display_clock_speed(struct drm_device *dev)
6778 {
6779 return 266667;
6780 }
6781
6782 static int i85x_get_display_clock_speed(struct drm_device *dev)
6783 {
6784 u16 hpllcc = 0;
6785
6786 /*
6787 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6788 * encoding is different :(
6789 * FIXME is this the right way to detect 852GM/852GMV?
6790 */
6791 if (dev->pdev->revision == 0x1)
6792 return 133333;
6793
6794 pci_bus_read_config_word(dev->pdev->bus,
6795 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6796
6797 /* Assume that the hardware is in the high speed state. This
6798 * should be the default.
6799 */
6800 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6801 case GC_CLOCK_133_200:
6802 case GC_CLOCK_133_200_2:
6803 case GC_CLOCK_100_200:
6804 return 200000;
6805 case GC_CLOCK_166_250:
6806 return 250000;
6807 case GC_CLOCK_100_133:
6808 return 133333;
6809 case GC_CLOCK_133_266:
6810 case GC_CLOCK_133_266_2:
6811 case GC_CLOCK_166_266:
6812 return 266667;
6813 }
6814
6815 /* Shouldn't happen */
6816 return 0;
6817 }
6818
6819 static int i830_get_display_clock_speed(struct drm_device *dev)
6820 {
6821 return 133333;
6822 }
6823
6824 static unsigned int intel_hpll_vco(struct drm_device *dev)
6825 {
6826 struct drm_i915_private *dev_priv = dev->dev_private;
6827 static const unsigned int blb_vco[8] = {
6828 [0] = 3200000,
6829 [1] = 4000000,
6830 [2] = 5333333,
6831 [3] = 4800000,
6832 [4] = 6400000,
6833 };
6834 static const unsigned int pnv_vco[8] = {
6835 [0] = 3200000,
6836 [1] = 4000000,
6837 [2] = 5333333,
6838 [3] = 4800000,
6839 [4] = 2666667,
6840 };
6841 static const unsigned int cl_vco[8] = {
6842 [0] = 3200000,
6843 [1] = 4000000,
6844 [2] = 5333333,
6845 [3] = 6400000,
6846 [4] = 3333333,
6847 [5] = 3566667,
6848 [6] = 4266667,
6849 };
6850 static const unsigned int elk_vco[8] = {
6851 [0] = 3200000,
6852 [1] = 4000000,
6853 [2] = 5333333,
6854 [3] = 4800000,
6855 };
6856 static const unsigned int ctg_vco[8] = {
6857 [0] = 3200000,
6858 [1] = 4000000,
6859 [2] = 5333333,
6860 [3] = 6400000,
6861 [4] = 2666667,
6862 [5] = 4266667,
6863 };
6864 const unsigned int *vco_table;
6865 unsigned int vco;
6866 uint8_t tmp = 0;
6867
6868 /* FIXME other chipsets? */
6869 if (IS_GM45(dev))
6870 vco_table = ctg_vco;
6871 else if (IS_G4X(dev))
6872 vco_table = elk_vco;
6873 else if (IS_CRESTLINE(dev))
6874 vco_table = cl_vco;
6875 else if (IS_PINEVIEW(dev))
6876 vco_table = pnv_vco;
6877 else if (IS_G33(dev))
6878 vco_table = blb_vco;
6879 else
6880 return 0;
6881
6882 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6883
6884 vco = vco_table[tmp & 0x7];
6885 if (vco == 0)
6886 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6887 else
6888 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6889
6890 return vco;
6891 }
6892
6893 static int gm45_get_display_clock_speed(struct drm_device *dev)
6894 {
6895 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6896 uint16_t tmp = 0;
6897
6898 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6899
6900 cdclk_sel = (tmp >> 12) & 0x1;
6901
6902 switch (vco) {
6903 case 2666667:
6904 case 4000000:
6905 case 5333333:
6906 return cdclk_sel ? 333333 : 222222;
6907 case 3200000:
6908 return cdclk_sel ? 320000 : 228571;
6909 default:
6910 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6911 return 222222;
6912 }
6913 }
6914
6915 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6916 {
6917 static const uint8_t div_3200[] = { 16, 10, 8 };
6918 static const uint8_t div_4000[] = { 20, 12, 10 };
6919 static const uint8_t div_5333[] = { 24, 16, 14 };
6920 const uint8_t *div_table;
6921 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6922 uint16_t tmp = 0;
6923
6924 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6925
6926 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6927
6928 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6929 goto fail;
6930
6931 switch (vco) {
6932 case 3200000:
6933 div_table = div_3200;
6934 break;
6935 case 4000000:
6936 div_table = div_4000;
6937 break;
6938 case 5333333:
6939 div_table = div_5333;
6940 break;
6941 default:
6942 goto fail;
6943 }
6944
6945 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6946
6947 fail:
6948 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6949 return 200000;
6950 }
6951
6952 static int g33_get_display_clock_speed(struct drm_device *dev)
6953 {
6954 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6955 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6956 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6957 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6958 const uint8_t *div_table;
6959 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6960 uint16_t tmp = 0;
6961
6962 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6963
6964 cdclk_sel = (tmp >> 4) & 0x7;
6965
6966 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6967 goto fail;
6968
6969 switch (vco) {
6970 case 3200000:
6971 div_table = div_3200;
6972 break;
6973 case 4000000:
6974 div_table = div_4000;
6975 break;
6976 case 4800000:
6977 div_table = div_4800;
6978 break;
6979 case 5333333:
6980 div_table = div_5333;
6981 break;
6982 default:
6983 goto fail;
6984 }
6985
6986 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6987
6988 fail:
6989 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6990 return 190476;
6991 }
6992
6993 static void
6994 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6995 {
6996 while (*num > DATA_LINK_M_N_MASK ||
6997 *den > DATA_LINK_M_N_MASK) {
6998 *num >>= 1;
6999 *den >>= 1;
7000 }
7001 }
7002
7003 static void compute_m_n(unsigned int m, unsigned int n,
7004 uint32_t *ret_m, uint32_t *ret_n)
7005 {
7006 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7007 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7008 intel_reduce_m_n_ratio(ret_m, ret_n);
7009 }
7010
7011 void
7012 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7013 int pixel_clock, int link_clock,
7014 struct intel_link_m_n *m_n)
7015 {
7016 m_n->tu = 64;
7017
7018 compute_m_n(bits_per_pixel * pixel_clock,
7019 link_clock * nlanes * 8,
7020 &m_n->gmch_m, &m_n->gmch_n);
7021
7022 compute_m_n(pixel_clock, link_clock,
7023 &m_n->link_m, &m_n->link_n);
7024 }
7025
7026 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7027 {
7028 if (i915.panel_use_ssc >= 0)
7029 return i915.panel_use_ssc != 0;
7030 return dev_priv->vbt.lvds_use_ssc
7031 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7032 }
7033
7034 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7035 {
7036 return (1 << dpll->n) << 16 | dpll->m2;
7037 }
7038
7039 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7040 {
7041 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7042 }
7043
7044 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7045 struct intel_crtc_state *crtc_state,
7046 struct dpll *reduced_clock)
7047 {
7048 struct drm_device *dev = crtc->base.dev;
7049 u32 fp, fp2 = 0;
7050
7051 if (IS_PINEVIEW(dev)) {
7052 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7053 if (reduced_clock)
7054 fp2 = pnv_dpll_compute_fp(reduced_clock);
7055 } else {
7056 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7057 if (reduced_clock)
7058 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7059 }
7060
7061 crtc_state->dpll_hw_state.fp0 = fp;
7062
7063 crtc->lowfreq_avail = false;
7064 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7065 reduced_clock) {
7066 crtc_state->dpll_hw_state.fp1 = fp2;
7067 crtc->lowfreq_avail = true;
7068 } else {
7069 crtc_state->dpll_hw_state.fp1 = fp;
7070 }
7071 }
7072
7073 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7074 pipe)
7075 {
7076 u32 reg_val;
7077
7078 /*
7079 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7080 * and set it to a reasonable value instead.
7081 */
7082 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7083 reg_val &= 0xffffff00;
7084 reg_val |= 0x00000030;
7085 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7086
7087 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7088 reg_val &= 0x8cffffff;
7089 reg_val = 0x8c000000;
7090 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7091
7092 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7093 reg_val &= 0xffffff00;
7094 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7095
7096 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7097 reg_val &= 0x00ffffff;
7098 reg_val |= 0xb0000000;
7099 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7100 }
7101
7102 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7103 struct intel_link_m_n *m_n)
7104 {
7105 struct drm_device *dev = crtc->base.dev;
7106 struct drm_i915_private *dev_priv = dev->dev_private;
7107 int pipe = crtc->pipe;
7108
7109 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7110 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7111 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7112 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7113 }
7114
7115 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7116 struct intel_link_m_n *m_n,
7117 struct intel_link_m_n *m2_n2)
7118 {
7119 struct drm_device *dev = crtc->base.dev;
7120 struct drm_i915_private *dev_priv = dev->dev_private;
7121 int pipe = crtc->pipe;
7122 enum transcoder transcoder = crtc->config->cpu_transcoder;
7123
7124 if (INTEL_INFO(dev)->gen >= 5) {
7125 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7126 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7127 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7128 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7129 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7130 * for gen < 8) and if DRRS is supported (to make sure the
7131 * registers are not unnecessarily accessed).
7132 */
7133 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7134 crtc->config->has_drrs) {
7135 I915_WRITE(PIPE_DATA_M2(transcoder),
7136 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7137 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7138 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7139 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7140 }
7141 } else {
7142 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7143 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7144 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7145 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7146 }
7147 }
7148
7149 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7150 {
7151 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7152
7153 if (m_n == M1_N1) {
7154 dp_m_n = &crtc->config->dp_m_n;
7155 dp_m2_n2 = &crtc->config->dp_m2_n2;
7156 } else if (m_n == M2_N2) {
7157
7158 /*
7159 * M2_N2 registers are not supported. Hence m2_n2 divider value
7160 * needs to be programmed into M1_N1.
7161 */
7162 dp_m_n = &crtc->config->dp_m2_n2;
7163 } else {
7164 DRM_ERROR("Unsupported divider value\n");
7165 return;
7166 }
7167
7168 if (crtc->config->has_pch_encoder)
7169 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7170 else
7171 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7172 }
7173
7174 static void vlv_compute_dpll(struct intel_crtc *crtc,
7175 struct intel_crtc_state *pipe_config)
7176 {
7177 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7178 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7179 if (crtc->pipe != PIPE_A)
7180 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7181
7182 /* DPLL not used with DSI, but still need the rest set up */
7183 if (!pipe_config->has_dsi_encoder)
7184 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7185 DPLL_EXT_BUFFER_ENABLE_VLV;
7186
7187 pipe_config->dpll_hw_state.dpll_md =
7188 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7189 }
7190
7191 static void chv_compute_dpll(struct intel_crtc *crtc,
7192 struct intel_crtc_state *pipe_config)
7193 {
7194 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7195 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7196 if (crtc->pipe != PIPE_A)
7197 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7198
7199 /* DPLL not used with DSI, but still need the rest set up */
7200 if (!pipe_config->has_dsi_encoder)
7201 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7202
7203 pipe_config->dpll_hw_state.dpll_md =
7204 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7205 }
7206
7207 static void vlv_prepare_pll(struct intel_crtc *crtc,
7208 const struct intel_crtc_state *pipe_config)
7209 {
7210 struct drm_device *dev = crtc->base.dev;
7211 struct drm_i915_private *dev_priv = dev->dev_private;
7212 enum pipe pipe = crtc->pipe;
7213 u32 mdiv;
7214 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7215 u32 coreclk, reg_val;
7216
7217 /* Enable Refclk */
7218 I915_WRITE(DPLL(pipe),
7219 pipe_config->dpll_hw_state.dpll &
7220 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7221
7222 /* No need to actually set up the DPLL with DSI */
7223 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7224 return;
7225
7226 mutex_lock(&dev_priv->sb_lock);
7227
7228 bestn = pipe_config->dpll.n;
7229 bestm1 = pipe_config->dpll.m1;
7230 bestm2 = pipe_config->dpll.m2;
7231 bestp1 = pipe_config->dpll.p1;
7232 bestp2 = pipe_config->dpll.p2;
7233
7234 /* See eDP HDMI DPIO driver vbios notes doc */
7235
7236 /* PLL B needs special handling */
7237 if (pipe == PIPE_B)
7238 vlv_pllb_recal_opamp(dev_priv, pipe);
7239
7240 /* Set up Tx target for periodic Rcomp update */
7241 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7242
7243 /* Disable target IRef on PLL */
7244 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7245 reg_val &= 0x00ffffff;
7246 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7247
7248 /* Disable fast lock */
7249 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7250
7251 /* Set idtafcrecal before PLL is enabled */
7252 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7253 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7254 mdiv |= ((bestn << DPIO_N_SHIFT));
7255 mdiv |= (1 << DPIO_K_SHIFT);
7256
7257 /*
7258 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7259 * but we don't support that).
7260 * Note: don't use the DAC post divider as it seems unstable.
7261 */
7262 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7263 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7264
7265 mdiv |= DPIO_ENABLE_CALIBRATION;
7266 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7267
7268 /* Set HBR and RBR LPF coefficients */
7269 if (pipe_config->port_clock == 162000 ||
7270 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7271 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7272 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7273 0x009f0003);
7274 else
7275 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7276 0x00d0000f);
7277
7278 if (pipe_config->has_dp_encoder) {
7279 /* Use SSC source */
7280 if (pipe == PIPE_A)
7281 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7282 0x0df40000);
7283 else
7284 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7285 0x0df70000);
7286 } else { /* HDMI or VGA */
7287 /* Use bend source */
7288 if (pipe == PIPE_A)
7289 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7290 0x0df70000);
7291 else
7292 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7293 0x0df40000);
7294 }
7295
7296 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7297 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7298 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7299 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7300 coreclk |= 0x01000000;
7301 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7302
7303 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7304 mutex_unlock(&dev_priv->sb_lock);
7305 }
7306
7307 static void chv_prepare_pll(struct intel_crtc *crtc,
7308 const struct intel_crtc_state *pipe_config)
7309 {
7310 struct drm_device *dev = crtc->base.dev;
7311 struct drm_i915_private *dev_priv = dev->dev_private;
7312 enum pipe pipe = crtc->pipe;
7313 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7314 u32 loopfilter, tribuf_calcntr;
7315 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7316 u32 dpio_val;
7317 int vco;
7318
7319 /* Enable Refclk and SSC */
7320 I915_WRITE(DPLL(pipe),
7321 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7322
7323 /* No need to actually set up the DPLL with DSI */
7324 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7325 return;
7326
7327 bestn = pipe_config->dpll.n;
7328 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7329 bestm1 = pipe_config->dpll.m1;
7330 bestm2 = pipe_config->dpll.m2 >> 22;
7331 bestp1 = pipe_config->dpll.p1;
7332 bestp2 = pipe_config->dpll.p2;
7333 vco = pipe_config->dpll.vco;
7334 dpio_val = 0;
7335 loopfilter = 0;
7336
7337 mutex_lock(&dev_priv->sb_lock);
7338
7339 /* p1 and p2 divider */
7340 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7341 5 << DPIO_CHV_S1_DIV_SHIFT |
7342 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7343 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7344 1 << DPIO_CHV_K_DIV_SHIFT);
7345
7346 /* Feedback post-divider - m2 */
7347 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7348
7349 /* Feedback refclk divider - n and m1 */
7350 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7351 DPIO_CHV_M1_DIV_BY_2 |
7352 1 << DPIO_CHV_N_DIV_SHIFT);
7353
7354 /* M2 fraction division */
7355 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7356
7357 /* M2 fraction division enable */
7358 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7359 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7360 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7361 if (bestm2_frac)
7362 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7363 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7364
7365 /* Program digital lock detect threshold */
7366 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7367 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7368 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7369 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7370 if (!bestm2_frac)
7371 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7372 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7373
7374 /* Loop filter */
7375 if (vco == 5400000) {
7376 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7377 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7378 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7379 tribuf_calcntr = 0x9;
7380 } else if (vco <= 6200000) {
7381 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7382 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7383 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7384 tribuf_calcntr = 0x9;
7385 } else if (vco <= 6480000) {
7386 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7387 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7388 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7389 tribuf_calcntr = 0x8;
7390 } else {
7391 /* Not supported. Apply the same limits as in the max case */
7392 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7393 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7394 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7395 tribuf_calcntr = 0;
7396 }
7397 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7398
7399 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7400 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7401 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7402 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7403
7404 /* AFC Recal */
7405 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7406 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7407 DPIO_AFC_RECAL);
7408
7409 mutex_unlock(&dev_priv->sb_lock);
7410 }
7411
7412 /**
7413 * vlv_force_pll_on - forcibly enable just the PLL
7414 * @dev_priv: i915 private structure
7415 * @pipe: pipe PLL to enable
7416 * @dpll: PLL configuration
7417 *
7418 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7419 * in cases where we need the PLL enabled even when @pipe is not going to
7420 * be enabled.
7421 */
7422 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7423 const struct dpll *dpll)
7424 {
7425 struct intel_crtc *crtc =
7426 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7427 struct intel_crtc_state *pipe_config;
7428
7429 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7430 if (!pipe_config)
7431 return -ENOMEM;
7432
7433 pipe_config->base.crtc = &crtc->base;
7434 pipe_config->pixel_multiplier = 1;
7435 pipe_config->dpll = *dpll;
7436
7437 if (IS_CHERRYVIEW(dev)) {
7438 chv_compute_dpll(crtc, pipe_config);
7439 chv_prepare_pll(crtc, pipe_config);
7440 chv_enable_pll(crtc, pipe_config);
7441 } else {
7442 vlv_compute_dpll(crtc, pipe_config);
7443 vlv_prepare_pll(crtc, pipe_config);
7444 vlv_enable_pll(crtc, pipe_config);
7445 }
7446
7447 kfree(pipe_config);
7448
7449 return 0;
7450 }
7451
7452 /**
7453 * vlv_force_pll_off - forcibly disable just the PLL
7454 * @dev_priv: i915 private structure
7455 * @pipe: pipe PLL to disable
7456 *
7457 * Disable the PLL for @pipe. To be used in cases where we need
7458 * the PLL enabled even when @pipe is not going to be enabled.
7459 */
7460 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7461 {
7462 if (IS_CHERRYVIEW(dev))
7463 chv_disable_pll(to_i915(dev), pipe);
7464 else
7465 vlv_disable_pll(to_i915(dev), pipe);
7466 }
7467
7468 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7469 struct intel_crtc_state *crtc_state,
7470 struct dpll *reduced_clock)
7471 {
7472 struct drm_device *dev = crtc->base.dev;
7473 struct drm_i915_private *dev_priv = dev->dev_private;
7474 u32 dpll;
7475 bool is_sdvo;
7476 struct dpll *clock = &crtc_state->dpll;
7477
7478 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7479
7480 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7481 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7482
7483 dpll = DPLL_VGA_MODE_DIS;
7484
7485 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7486 dpll |= DPLLB_MODE_LVDS;
7487 else
7488 dpll |= DPLLB_MODE_DAC_SERIAL;
7489
7490 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7491 dpll |= (crtc_state->pixel_multiplier - 1)
7492 << SDVO_MULTIPLIER_SHIFT_HIRES;
7493 }
7494
7495 if (is_sdvo)
7496 dpll |= DPLL_SDVO_HIGH_SPEED;
7497
7498 if (crtc_state->has_dp_encoder)
7499 dpll |= DPLL_SDVO_HIGH_SPEED;
7500
7501 /* compute bitmask from p1 value */
7502 if (IS_PINEVIEW(dev))
7503 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7504 else {
7505 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7506 if (IS_G4X(dev) && reduced_clock)
7507 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7508 }
7509 switch (clock->p2) {
7510 case 5:
7511 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7512 break;
7513 case 7:
7514 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7515 break;
7516 case 10:
7517 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7518 break;
7519 case 14:
7520 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7521 break;
7522 }
7523 if (INTEL_INFO(dev)->gen >= 4)
7524 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7525
7526 if (crtc_state->sdvo_tv_clock)
7527 dpll |= PLL_REF_INPUT_TVCLKINBC;
7528 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7529 intel_panel_use_ssc(dev_priv))
7530 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7531 else
7532 dpll |= PLL_REF_INPUT_DREFCLK;
7533
7534 dpll |= DPLL_VCO_ENABLE;
7535 crtc_state->dpll_hw_state.dpll = dpll;
7536
7537 if (INTEL_INFO(dev)->gen >= 4) {
7538 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7539 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7540 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7541 }
7542 }
7543
7544 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7545 struct intel_crtc_state *crtc_state,
7546 struct dpll *reduced_clock)
7547 {
7548 struct drm_device *dev = crtc->base.dev;
7549 struct drm_i915_private *dev_priv = dev->dev_private;
7550 u32 dpll;
7551 struct dpll *clock = &crtc_state->dpll;
7552
7553 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7554
7555 dpll = DPLL_VGA_MODE_DIS;
7556
7557 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7558 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7559 } else {
7560 if (clock->p1 == 2)
7561 dpll |= PLL_P1_DIVIDE_BY_TWO;
7562 else
7563 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7564 if (clock->p2 == 4)
7565 dpll |= PLL_P2_DIVIDE_BY_4;
7566 }
7567
7568 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7569 dpll |= DPLL_DVO_2X_MODE;
7570
7571 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7572 intel_panel_use_ssc(dev_priv))
7573 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7574 else
7575 dpll |= PLL_REF_INPUT_DREFCLK;
7576
7577 dpll |= DPLL_VCO_ENABLE;
7578 crtc_state->dpll_hw_state.dpll = dpll;
7579 }
7580
7581 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7582 {
7583 struct drm_device *dev = intel_crtc->base.dev;
7584 struct drm_i915_private *dev_priv = dev->dev_private;
7585 enum pipe pipe = intel_crtc->pipe;
7586 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7587 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7588 uint32_t crtc_vtotal, crtc_vblank_end;
7589 int vsyncshift = 0;
7590
7591 /* We need to be careful not to changed the adjusted mode, for otherwise
7592 * the hw state checker will get angry at the mismatch. */
7593 crtc_vtotal = adjusted_mode->crtc_vtotal;
7594 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7595
7596 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7597 /* the chip adds 2 halflines automatically */
7598 crtc_vtotal -= 1;
7599 crtc_vblank_end -= 1;
7600
7601 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7602 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7603 else
7604 vsyncshift = adjusted_mode->crtc_hsync_start -
7605 adjusted_mode->crtc_htotal / 2;
7606 if (vsyncshift < 0)
7607 vsyncshift += adjusted_mode->crtc_htotal;
7608 }
7609
7610 if (INTEL_INFO(dev)->gen > 3)
7611 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7612
7613 I915_WRITE(HTOTAL(cpu_transcoder),
7614 (adjusted_mode->crtc_hdisplay - 1) |
7615 ((adjusted_mode->crtc_htotal - 1) << 16));
7616 I915_WRITE(HBLANK(cpu_transcoder),
7617 (adjusted_mode->crtc_hblank_start - 1) |
7618 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7619 I915_WRITE(HSYNC(cpu_transcoder),
7620 (adjusted_mode->crtc_hsync_start - 1) |
7621 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7622
7623 I915_WRITE(VTOTAL(cpu_transcoder),
7624 (adjusted_mode->crtc_vdisplay - 1) |
7625 ((crtc_vtotal - 1) << 16));
7626 I915_WRITE(VBLANK(cpu_transcoder),
7627 (adjusted_mode->crtc_vblank_start - 1) |
7628 ((crtc_vblank_end - 1) << 16));
7629 I915_WRITE(VSYNC(cpu_transcoder),
7630 (adjusted_mode->crtc_vsync_start - 1) |
7631 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7632
7633 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7634 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7635 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7636 * bits. */
7637 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7638 (pipe == PIPE_B || pipe == PIPE_C))
7639 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7640
7641 }
7642
7643 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7644 {
7645 struct drm_device *dev = intel_crtc->base.dev;
7646 struct drm_i915_private *dev_priv = dev->dev_private;
7647 enum pipe pipe = intel_crtc->pipe;
7648
7649 /* pipesrc controls the size that is scaled from, which should
7650 * always be the user's requested size.
7651 */
7652 I915_WRITE(PIPESRC(pipe),
7653 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7654 (intel_crtc->config->pipe_src_h - 1));
7655 }
7656
7657 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7658 struct intel_crtc_state *pipe_config)
7659 {
7660 struct drm_device *dev = crtc->base.dev;
7661 struct drm_i915_private *dev_priv = dev->dev_private;
7662 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7663 uint32_t tmp;
7664
7665 tmp = I915_READ(HTOTAL(cpu_transcoder));
7666 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7667 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7668 tmp = I915_READ(HBLANK(cpu_transcoder));
7669 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7670 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7671 tmp = I915_READ(HSYNC(cpu_transcoder));
7672 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7673 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7674
7675 tmp = I915_READ(VTOTAL(cpu_transcoder));
7676 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7677 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7678 tmp = I915_READ(VBLANK(cpu_transcoder));
7679 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7680 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7681 tmp = I915_READ(VSYNC(cpu_transcoder));
7682 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7683 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7684
7685 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7686 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7687 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7688 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7689 }
7690 }
7691
7692 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7693 struct intel_crtc_state *pipe_config)
7694 {
7695 struct drm_device *dev = crtc->base.dev;
7696 struct drm_i915_private *dev_priv = dev->dev_private;
7697 u32 tmp;
7698
7699 tmp = I915_READ(PIPESRC(crtc->pipe));
7700 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7701 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7702
7703 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7704 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7705 }
7706
7707 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7708 struct intel_crtc_state *pipe_config)
7709 {
7710 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7711 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7712 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7713 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7714
7715 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7716 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7717 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7718 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7719
7720 mode->flags = pipe_config->base.adjusted_mode.flags;
7721 mode->type = DRM_MODE_TYPE_DRIVER;
7722
7723 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7724 mode->flags |= pipe_config->base.adjusted_mode.flags;
7725
7726 mode->hsync = drm_mode_hsync(mode);
7727 mode->vrefresh = drm_mode_vrefresh(mode);
7728 drm_mode_set_name(mode);
7729 }
7730
7731 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7732 {
7733 struct drm_device *dev = intel_crtc->base.dev;
7734 struct drm_i915_private *dev_priv = dev->dev_private;
7735 uint32_t pipeconf;
7736
7737 pipeconf = 0;
7738
7739 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7740 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7741 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7742
7743 if (intel_crtc->config->double_wide)
7744 pipeconf |= PIPECONF_DOUBLE_WIDE;
7745
7746 /* only g4x and later have fancy bpc/dither controls */
7747 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7748 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7749 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7750 pipeconf |= PIPECONF_DITHER_EN |
7751 PIPECONF_DITHER_TYPE_SP;
7752
7753 switch (intel_crtc->config->pipe_bpp) {
7754 case 18:
7755 pipeconf |= PIPECONF_6BPC;
7756 break;
7757 case 24:
7758 pipeconf |= PIPECONF_8BPC;
7759 break;
7760 case 30:
7761 pipeconf |= PIPECONF_10BPC;
7762 break;
7763 default:
7764 /* Case prevented by intel_choose_pipe_bpp_dither. */
7765 BUG();
7766 }
7767 }
7768
7769 if (HAS_PIPE_CXSR(dev)) {
7770 if (intel_crtc->lowfreq_avail) {
7771 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7772 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7773 } else {
7774 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7775 }
7776 }
7777
7778 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7779 if (INTEL_INFO(dev)->gen < 4 ||
7780 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7781 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7782 else
7783 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7784 } else
7785 pipeconf |= PIPECONF_PROGRESSIVE;
7786
7787 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7788 intel_crtc->config->limited_color_range)
7789 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7790
7791 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7792 POSTING_READ(PIPECONF(intel_crtc->pipe));
7793 }
7794
7795 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7796 struct intel_crtc_state *crtc_state)
7797 {
7798 struct drm_device *dev = crtc->base.dev;
7799 struct drm_i915_private *dev_priv = dev->dev_private;
7800 const struct intel_limit *limit;
7801 int refclk = 48000;
7802
7803 memset(&crtc_state->dpll_hw_state, 0,
7804 sizeof(crtc_state->dpll_hw_state));
7805
7806 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7807 if (intel_panel_use_ssc(dev_priv)) {
7808 refclk = dev_priv->vbt.lvds_ssc_freq;
7809 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7810 }
7811
7812 limit = &intel_limits_i8xx_lvds;
7813 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) {
7814 limit = &intel_limits_i8xx_dvo;
7815 } else {
7816 limit = &intel_limits_i8xx_dac;
7817 }
7818
7819 if (!crtc_state->clock_set &&
7820 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7821 refclk, NULL, &crtc_state->dpll)) {
7822 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7823 return -EINVAL;
7824 }
7825
7826 i8xx_compute_dpll(crtc, crtc_state, NULL);
7827
7828 return 0;
7829 }
7830
7831 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7832 struct intel_crtc_state *crtc_state)
7833 {
7834 struct drm_device *dev = crtc->base.dev;
7835 struct drm_i915_private *dev_priv = dev->dev_private;
7836 const struct intel_limit *limit;
7837 int refclk = 96000;
7838
7839 memset(&crtc_state->dpll_hw_state, 0,
7840 sizeof(crtc_state->dpll_hw_state));
7841
7842 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7843 if (intel_panel_use_ssc(dev_priv)) {
7844 refclk = dev_priv->vbt.lvds_ssc_freq;
7845 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7846 }
7847
7848 if (intel_is_dual_link_lvds(dev))
7849 limit = &intel_limits_g4x_dual_channel_lvds;
7850 else
7851 limit = &intel_limits_g4x_single_channel_lvds;
7852 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7853 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7854 limit = &intel_limits_g4x_hdmi;
7855 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7856 limit = &intel_limits_g4x_sdvo;
7857 } else {
7858 /* The option is for other outputs */
7859 limit = &intel_limits_i9xx_sdvo;
7860 }
7861
7862 if (!crtc_state->clock_set &&
7863 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7864 refclk, NULL, &crtc_state->dpll)) {
7865 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7866 return -EINVAL;
7867 }
7868
7869 i9xx_compute_dpll(crtc, crtc_state, NULL);
7870
7871 return 0;
7872 }
7873
7874 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7875 struct intel_crtc_state *crtc_state)
7876 {
7877 struct drm_device *dev = crtc->base.dev;
7878 struct drm_i915_private *dev_priv = dev->dev_private;
7879 const struct intel_limit *limit;
7880 int refclk = 96000;
7881
7882 memset(&crtc_state->dpll_hw_state, 0,
7883 sizeof(crtc_state->dpll_hw_state));
7884
7885 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7886 if (intel_panel_use_ssc(dev_priv)) {
7887 refclk = dev_priv->vbt.lvds_ssc_freq;
7888 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7889 }
7890
7891 limit = &intel_limits_pineview_lvds;
7892 } else {
7893 limit = &intel_limits_pineview_sdvo;
7894 }
7895
7896 if (!crtc_state->clock_set &&
7897 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7898 refclk, NULL, &crtc_state->dpll)) {
7899 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7900 return -EINVAL;
7901 }
7902
7903 i9xx_compute_dpll(crtc, crtc_state, NULL);
7904
7905 return 0;
7906 }
7907
7908 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7909 struct intel_crtc_state *crtc_state)
7910 {
7911 struct drm_device *dev = crtc->base.dev;
7912 struct drm_i915_private *dev_priv = dev->dev_private;
7913 const struct intel_limit *limit;
7914 int refclk = 96000;
7915
7916 memset(&crtc_state->dpll_hw_state, 0,
7917 sizeof(crtc_state->dpll_hw_state));
7918
7919 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7920 if (intel_panel_use_ssc(dev_priv)) {
7921 refclk = dev_priv->vbt.lvds_ssc_freq;
7922 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7923 }
7924
7925 limit = &intel_limits_i9xx_lvds;
7926 } else {
7927 limit = &intel_limits_i9xx_sdvo;
7928 }
7929
7930 if (!crtc_state->clock_set &&
7931 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7932 refclk, NULL, &crtc_state->dpll)) {
7933 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7934 return -EINVAL;
7935 }
7936
7937 i9xx_compute_dpll(crtc, crtc_state, NULL);
7938
7939 return 0;
7940 }
7941
7942 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7943 struct intel_crtc_state *crtc_state)
7944 {
7945 int refclk = 100000;
7946 const struct intel_limit *limit = &intel_limits_chv;
7947
7948 memset(&crtc_state->dpll_hw_state, 0,
7949 sizeof(crtc_state->dpll_hw_state));
7950
7951 if (!crtc_state->clock_set &&
7952 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7953 refclk, NULL, &crtc_state->dpll)) {
7954 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7955 return -EINVAL;
7956 }
7957
7958 chv_compute_dpll(crtc, crtc_state);
7959
7960 return 0;
7961 }
7962
7963 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7964 struct intel_crtc_state *crtc_state)
7965 {
7966 int refclk = 100000;
7967 const struct intel_limit *limit = &intel_limits_vlv;
7968
7969 memset(&crtc_state->dpll_hw_state, 0,
7970 sizeof(crtc_state->dpll_hw_state));
7971
7972 if (!crtc_state->clock_set &&
7973 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7974 refclk, NULL, &crtc_state->dpll)) {
7975 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7976 return -EINVAL;
7977 }
7978
7979 vlv_compute_dpll(crtc, crtc_state);
7980
7981 return 0;
7982 }
7983
7984 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7985 struct intel_crtc_state *pipe_config)
7986 {
7987 struct drm_device *dev = crtc->base.dev;
7988 struct drm_i915_private *dev_priv = dev->dev_private;
7989 uint32_t tmp;
7990
7991 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7992 return;
7993
7994 tmp = I915_READ(PFIT_CONTROL);
7995 if (!(tmp & PFIT_ENABLE))
7996 return;
7997
7998 /* Check whether the pfit is attached to our pipe. */
7999 if (INTEL_INFO(dev)->gen < 4) {
8000 if (crtc->pipe != PIPE_B)
8001 return;
8002 } else {
8003 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8004 return;
8005 }
8006
8007 pipe_config->gmch_pfit.control = tmp;
8008 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8009 }
8010
8011 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8012 struct intel_crtc_state *pipe_config)
8013 {
8014 struct drm_device *dev = crtc->base.dev;
8015 struct drm_i915_private *dev_priv = dev->dev_private;
8016 int pipe = pipe_config->cpu_transcoder;
8017 struct dpll clock;
8018 u32 mdiv;
8019 int refclk = 100000;
8020
8021 /* In case of DSI, DPLL will not be used */
8022 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8023 return;
8024
8025 mutex_lock(&dev_priv->sb_lock);
8026 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8027 mutex_unlock(&dev_priv->sb_lock);
8028
8029 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8030 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8031 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8032 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8033 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8034
8035 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8036 }
8037
8038 static void
8039 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8040 struct intel_initial_plane_config *plane_config)
8041 {
8042 struct drm_device *dev = crtc->base.dev;
8043 struct drm_i915_private *dev_priv = dev->dev_private;
8044 u32 val, base, offset;
8045 int pipe = crtc->pipe, plane = crtc->plane;
8046 int fourcc, pixel_format;
8047 unsigned int aligned_height;
8048 struct drm_framebuffer *fb;
8049 struct intel_framebuffer *intel_fb;
8050
8051 val = I915_READ(DSPCNTR(plane));
8052 if (!(val & DISPLAY_PLANE_ENABLE))
8053 return;
8054
8055 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8056 if (!intel_fb) {
8057 DRM_DEBUG_KMS("failed to alloc fb\n");
8058 return;
8059 }
8060
8061 fb = &intel_fb->base;
8062
8063 if (INTEL_INFO(dev)->gen >= 4) {
8064 if (val & DISPPLANE_TILED) {
8065 plane_config->tiling = I915_TILING_X;
8066 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8067 }
8068 }
8069
8070 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8071 fourcc = i9xx_format_to_fourcc(pixel_format);
8072 fb->pixel_format = fourcc;
8073 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8074
8075 if (INTEL_INFO(dev)->gen >= 4) {
8076 if (plane_config->tiling)
8077 offset = I915_READ(DSPTILEOFF(plane));
8078 else
8079 offset = I915_READ(DSPLINOFF(plane));
8080 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8081 } else {
8082 base = I915_READ(DSPADDR(plane));
8083 }
8084 plane_config->base = base;
8085
8086 val = I915_READ(PIPESRC(pipe));
8087 fb->width = ((val >> 16) & 0xfff) + 1;
8088 fb->height = ((val >> 0) & 0xfff) + 1;
8089
8090 val = I915_READ(DSPSTRIDE(pipe));
8091 fb->pitches[0] = val & 0xffffffc0;
8092
8093 aligned_height = intel_fb_align_height(dev, fb->height,
8094 fb->pixel_format,
8095 fb->modifier[0]);
8096
8097 plane_config->size = fb->pitches[0] * aligned_height;
8098
8099 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8100 pipe_name(pipe), plane, fb->width, fb->height,
8101 fb->bits_per_pixel, base, fb->pitches[0],
8102 plane_config->size);
8103
8104 plane_config->fb = intel_fb;
8105 }
8106
8107 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8108 struct intel_crtc_state *pipe_config)
8109 {
8110 struct drm_device *dev = crtc->base.dev;
8111 struct drm_i915_private *dev_priv = dev->dev_private;
8112 int pipe = pipe_config->cpu_transcoder;
8113 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8114 struct dpll clock;
8115 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8116 int refclk = 100000;
8117
8118 /* In case of DSI, DPLL will not be used */
8119 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8120 return;
8121
8122 mutex_lock(&dev_priv->sb_lock);
8123 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8124 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8125 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8126 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8127 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8128 mutex_unlock(&dev_priv->sb_lock);
8129
8130 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8131 clock.m2 = (pll_dw0 & 0xff) << 22;
8132 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8133 clock.m2 |= pll_dw2 & 0x3fffff;
8134 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8135 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8136 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8137
8138 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8139 }
8140
8141 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8142 struct intel_crtc_state *pipe_config)
8143 {
8144 struct drm_device *dev = crtc->base.dev;
8145 struct drm_i915_private *dev_priv = dev->dev_private;
8146 enum intel_display_power_domain power_domain;
8147 uint32_t tmp;
8148 bool ret;
8149
8150 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8151 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8152 return false;
8153
8154 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8155 pipe_config->shared_dpll = NULL;
8156
8157 ret = false;
8158
8159 tmp = I915_READ(PIPECONF(crtc->pipe));
8160 if (!(tmp & PIPECONF_ENABLE))
8161 goto out;
8162
8163 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8164 switch (tmp & PIPECONF_BPC_MASK) {
8165 case PIPECONF_6BPC:
8166 pipe_config->pipe_bpp = 18;
8167 break;
8168 case PIPECONF_8BPC:
8169 pipe_config->pipe_bpp = 24;
8170 break;
8171 case PIPECONF_10BPC:
8172 pipe_config->pipe_bpp = 30;
8173 break;
8174 default:
8175 break;
8176 }
8177 }
8178
8179 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8180 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8181 pipe_config->limited_color_range = true;
8182
8183 if (INTEL_INFO(dev)->gen < 4)
8184 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8185
8186 intel_get_pipe_timings(crtc, pipe_config);
8187 intel_get_pipe_src_size(crtc, pipe_config);
8188
8189 i9xx_get_pfit_config(crtc, pipe_config);
8190
8191 if (INTEL_INFO(dev)->gen >= 4) {
8192 /* No way to read it out on pipes B and C */
8193 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8194 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8195 else
8196 tmp = I915_READ(DPLL_MD(crtc->pipe));
8197 pipe_config->pixel_multiplier =
8198 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8199 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8200 pipe_config->dpll_hw_state.dpll_md = tmp;
8201 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8202 tmp = I915_READ(DPLL(crtc->pipe));
8203 pipe_config->pixel_multiplier =
8204 ((tmp & SDVO_MULTIPLIER_MASK)
8205 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8206 } else {
8207 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8208 * port and will be fixed up in the encoder->get_config
8209 * function. */
8210 pipe_config->pixel_multiplier = 1;
8211 }
8212 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8213 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8214 /*
8215 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8216 * on 830. Filter it out here so that we don't
8217 * report errors due to that.
8218 */
8219 if (IS_I830(dev))
8220 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8221
8222 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8223 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8224 } else {
8225 /* Mask out read-only status bits. */
8226 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8227 DPLL_PORTC_READY_MASK |
8228 DPLL_PORTB_READY_MASK);
8229 }
8230
8231 if (IS_CHERRYVIEW(dev))
8232 chv_crtc_clock_get(crtc, pipe_config);
8233 else if (IS_VALLEYVIEW(dev))
8234 vlv_crtc_clock_get(crtc, pipe_config);
8235 else
8236 i9xx_crtc_clock_get(crtc, pipe_config);
8237
8238 /*
8239 * Normally the dotclock is filled in by the encoder .get_config()
8240 * but in case the pipe is enabled w/o any ports we need a sane
8241 * default.
8242 */
8243 pipe_config->base.adjusted_mode.crtc_clock =
8244 pipe_config->port_clock / pipe_config->pixel_multiplier;
8245
8246 ret = true;
8247
8248 out:
8249 intel_display_power_put(dev_priv, power_domain);
8250
8251 return ret;
8252 }
8253
8254 static void ironlake_init_pch_refclk(struct drm_device *dev)
8255 {
8256 struct drm_i915_private *dev_priv = dev->dev_private;
8257 struct intel_encoder *encoder;
8258 u32 val, final;
8259 bool has_lvds = false;
8260 bool has_cpu_edp = false;
8261 bool has_panel = false;
8262 bool has_ck505 = false;
8263 bool can_ssc = false;
8264
8265 /* We need to take the global config into account */
8266 for_each_intel_encoder(dev, encoder) {
8267 switch (encoder->type) {
8268 case INTEL_OUTPUT_LVDS:
8269 has_panel = true;
8270 has_lvds = true;
8271 break;
8272 case INTEL_OUTPUT_EDP:
8273 has_panel = true;
8274 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8275 has_cpu_edp = true;
8276 break;
8277 default:
8278 break;
8279 }
8280 }
8281
8282 if (HAS_PCH_IBX(dev)) {
8283 has_ck505 = dev_priv->vbt.display_clock_mode;
8284 can_ssc = has_ck505;
8285 } else {
8286 has_ck505 = false;
8287 can_ssc = true;
8288 }
8289
8290 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8291 has_panel, has_lvds, has_ck505);
8292
8293 /* Ironlake: try to setup display ref clock before DPLL
8294 * enabling. This is only under driver's control after
8295 * PCH B stepping, previous chipset stepping should be
8296 * ignoring this setting.
8297 */
8298 val = I915_READ(PCH_DREF_CONTROL);
8299
8300 /* As we must carefully and slowly disable/enable each source in turn,
8301 * compute the final state we want first and check if we need to
8302 * make any changes at all.
8303 */
8304 final = val;
8305 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8306 if (has_ck505)
8307 final |= DREF_NONSPREAD_CK505_ENABLE;
8308 else
8309 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8310
8311 final &= ~DREF_SSC_SOURCE_MASK;
8312 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8313 final &= ~DREF_SSC1_ENABLE;
8314
8315 if (has_panel) {
8316 final |= DREF_SSC_SOURCE_ENABLE;
8317
8318 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8319 final |= DREF_SSC1_ENABLE;
8320
8321 if (has_cpu_edp) {
8322 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8323 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8324 else
8325 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8326 } else
8327 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8328 } else {
8329 final |= DREF_SSC_SOURCE_DISABLE;
8330 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8331 }
8332
8333 if (final == val)
8334 return;
8335
8336 /* Always enable nonspread source */
8337 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8338
8339 if (has_ck505)
8340 val |= DREF_NONSPREAD_CK505_ENABLE;
8341 else
8342 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8343
8344 if (has_panel) {
8345 val &= ~DREF_SSC_SOURCE_MASK;
8346 val |= DREF_SSC_SOURCE_ENABLE;
8347
8348 /* SSC must be turned on before enabling the CPU output */
8349 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8350 DRM_DEBUG_KMS("Using SSC on panel\n");
8351 val |= DREF_SSC1_ENABLE;
8352 } else
8353 val &= ~DREF_SSC1_ENABLE;
8354
8355 /* Get SSC going before enabling the outputs */
8356 I915_WRITE(PCH_DREF_CONTROL, val);
8357 POSTING_READ(PCH_DREF_CONTROL);
8358 udelay(200);
8359
8360 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8361
8362 /* Enable CPU source on CPU attached eDP */
8363 if (has_cpu_edp) {
8364 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8365 DRM_DEBUG_KMS("Using SSC on eDP\n");
8366 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8367 } else
8368 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8369 } else
8370 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8371
8372 I915_WRITE(PCH_DREF_CONTROL, val);
8373 POSTING_READ(PCH_DREF_CONTROL);
8374 udelay(200);
8375 } else {
8376 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8377
8378 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8379
8380 /* Turn off CPU output */
8381 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8382
8383 I915_WRITE(PCH_DREF_CONTROL, val);
8384 POSTING_READ(PCH_DREF_CONTROL);
8385 udelay(200);
8386
8387 /* Turn off the SSC source */
8388 val &= ~DREF_SSC_SOURCE_MASK;
8389 val |= DREF_SSC_SOURCE_DISABLE;
8390
8391 /* Turn off SSC1 */
8392 val &= ~DREF_SSC1_ENABLE;
8393
8394 I915_WRITE(PCH_DREF_CONTROL, val);
8395 POSTING_READ(PCH_DREF_CONTROL);
8396 udelay(200);
8397 }
8398
8399 BUG_ON(val != final);
8400 }
8401
8402 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8403 {
8404 uint32_t tmp;
8405
8406 tmp = I915_READ(SOUTH_CHICKEN2);
8407 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8408 I915_WRITE(SOUTH_CHICKEN2, tmp);
8409
8410 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8411 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8412 DRM_ERROR("FDI mPHY reset assert timeout\n");
8413
8414 tmp = I915_READ(SOUTH_CHICKEN2);
8415 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8416 I915_WRITE(SOUTH_CHICKEN2, tmp);
8417
8418 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8419 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8420 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8421 }
8422
8423 /* WaMPhyProgramming:hsw */
8424 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8425 {
8426 uint32_t tmp;
8427
8428 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8429 tmp &= ~(0xFF << 24);
8430 tmp |= (0x12 << 24);
8431 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8432
8433 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8434 tmp |= (1 << 11);
8435 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8436
8437 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8438 tmp |= (1 << 11);
8439 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8440
8441 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8442 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8443 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8444
8445 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8446 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8447 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8448
8449 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8450 tmp &= ~(7 << 13);
8451 tmp |= (5 << 13);
8452 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8453
8454 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8455 tmp &= ~(7 << 13);
8456 tmp |= (5 << 13);
8457 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8458
8459 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8460 tmp &= ~0xFF;
8461 tmp |= 0x1C;
8462 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8463
8464 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8465 tmp &= ~0xFF;
8466 tmp |= 0x1C;
8467 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8468
8469 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8470 tmp &= ~(0xFF << 16);
8471 tmp |= (0x1C << 16);
8472 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8473
8474 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8475 tmp &= ~(0xFF << 16);
8476 tmp |= (0x1C << 16);
8477 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8478
8479 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8480 tmp |= (1 << 27);
8481 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8482
8483 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8484 tmp |= (1 << 27);
8485 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8486
8487 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8488 tmp &= ~(0xF << 28);
8489 tmp |= (4 << 28);
8490 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8491
8492 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8493 tmp &= ~(0xF << 28);
8494 tmp |= (4 << 28);
8495 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8496 }
8497
8498 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8499 * Programming" based on the parameters passed:
8500 * - Sequence to enable CLKOUT_DP
8501 * - Sequence to enable CLKOUT_DP without spread
8502 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8503 */
8504 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8505 bool with_fdi)
8506 {
8507 struct drm_i915_private *dev_priv = dev->dev_private;
8508 uint32_t reg, tmp;
8509
8510 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8511 with_spread = true;
8512 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8513 with_fdi = false;
8514
8515 mutex_lock(&dev_priv->sb_lock);
8516
8517 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8518 tmp &= ~SBI_SSCCTL_DISABLE;
8519 tmp |= SBI_SSCCTL_PATHALT;
8520 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8521
8522 udelay(24);
8523
8524 if (with_spread) {
8525 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8526 tmp &= ~SBI_SSCCTL_PATHALT;
8527 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8528
8529 if (with_fdi) {
8530 lpt_reset_fdi_mphy(dev_priv);
8531 lpt_program_fdi_mphy(dev_priv);
8532 }
8533 }
8534
8535 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8536 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8537 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8538 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8539
8540 mutex_unlock(&dev_priv->sb_lock);
8541 }
8542
8543 /* Sequence to disable CLKOUT_DP */
8544 static void lpt_disable_clkout_dp(struct drm_device *dev)
8545 {
8546 struct drm_i915_private *dev_priv = dev->dev_private;
8547 uint32_t reg, tmp;
8548
8549 mutex_lock(&dev_priv->sb_lock);
8550
8551 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8552 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8553 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8554 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8555
8556 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8557 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8558 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8559 tmp |= SBI_SSCCTL_PATHALT;
8560 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8561 udelay(32);
8562 }
8563 tmp |= SBI_SSCCTL_DISABLE;
8564 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8565 }
8566
8567 mutex_unlock(&dev_priv->sb_lock);
8568 }
8569
8570 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8571
8572 static const uint16_t sscdivintphase[] = {
8573 [BEND_IDX( 50)] = 0x3B23,
8574 [BEND_IDX( 45)] = 0x3B23,
8575 [BEND_IDX( 40)] = 0x3C23,
8576 [BEND_IDX( 35)] = 0x3C23,
8577 [BEND_IDX( 30)] = 0x3D23,
8578 [BEND_IDX( 25)] = 0x3D23,
8579 [BEND_IDX( 20)] = 0x3E23,
8580 [BEND_IDX( 15)] = 0x3E23,
8581 [BEND_IDX( 10)] = 0x3F23,
8582 [BEND_IDX( 5)] = 0x3F23,
8583 [BEND_IDX( 0)] = 0x0025,
8584 [BEND_IDX( -5)] = 0x0025,
8585 [BEND_IDX(-10)] = 0x0125,
8586 [BEND_IDX(-15)] = 0x0125,
8587 [BEND_IDX(-20)] = 0x0225,
8588 [BEND_IDX(-25)] = 0x0225,
8589 [BEND_IDX(-30)] = 0x0325,
8590 [BEND_IDX(-35)] = 0x0325,
8591 [BEND_IDX(-40)] = 0x0425,
8592 [BEND_IDX(-45)] = 0x0425,
8593 [BEND_IDX(-50)] = 0x0525,
8594 };
8595
8596 /*
8597 * Bend CLKOUT_DP
8598 * steps -50 to 50 inclusive, in steps of 5
8599 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8600 * change in clock period = -(steps / 10) * 5.787 ps
8601 */
8602 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8603 {
8604 uint32_t tmp;
8605 int idx = BEND_IDX(steps);
8606
8607 if (WARN_ON(steps % 5 != 0))
8608 return;
8609
8610 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8611 return;
8612
8613 mutex_lock(&dev_priv->sb_lock);
8614
8615 if (steps % 10 != 0)
8616 tmp = 0xAAAAAAAB;
8617 else
8618 tmp = 0x00000000;
8619 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8620
8621 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8622 tmp &= 0xffff0000;
8623 tmp |= sscdivintphase[idx];
8624 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8625
8626 mutex_unlock(&dev_priv->sb_lock);
8627 }
8628
8629 #undef BEND_IDX
8630
8631 static void lpt_init_pch_refclk(struct drm_device *dev)
8632 {
8633 struct intel_encoder *encoder;
8634 bool has_vga = false;
8635
8636 for_each_intel_encoder(dev, encoder) {
8637 switch (encoder->type) {
8638 case INTEL_OUTPUT_ANALOG:
8639 has_vga = true;
8640 break;
8641 default:
8642 break;
8643 }
8644 }
8645
8646 if (has_vga) {
8647 lpt_bend_clkout_dp(to_i915(dev), 0);
8648 lpt_enable_clkout_dp(dev, true, true);
8649 } else {
8650 lpt_disable_clkout_dp(dev);
8651 }
8652 }
8653
8654 /*
8655 * Initialize reference clocks when the driver loads
8656 */
8657 void intel_init_pch_refclk(struct drm_device *dev)
8658 {
8659 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8660 ironlake_init_pch_refclk(dev);
8661 else if (HAS_PCH_LPT(dev))
8662 lpt_init_pch_refclk(dev);
8663 }
8664
8665 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8666 {
8667 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8668 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8669 int pipe = intel_crtc->pipe;
8670 uint32_t val;
8671
8672 val = 0;
8673
8674 switch (intel_crtc->config->pipe_bpp) {
8675 case 18:
8676 val |= PIPECONF_6BPC;
8677 break;
8678 case 24:
8679 val |= PIPECONF_8BPC;
8680 break;
8681 case 30:
8682 val |= PIPECONF_10BPC;
8683 break;
8684 case 36:
8685 val |= PIPECONF_12BPC;
8686 break;
8687 default:
8688 /* Case prevented by intel_choose_pipe_bpp_dither. */
8689 BUG();
8690 }
8691
8692 if (intel_crtc->config->dither)
8693 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8694
8695 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8696 val |= PIPECONF_INTERLACED_ILK;
8697 else
8698 val |= PIPECONF_PROGRESSIVE;
8699
8700 if (intel_crtc->config->limited_color_range)
8701 val |= PIPECONF_COLOR_RANGE_SELECT;
8702
8703 I915_WRITE(PIPECONF(pipe), val);
8704 POSTING_READ(PIPECONF(pipe));
8705 }
8706
8707 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8708 {
8709 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8710 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8711 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8712 u32 val = 0;
8713
8714 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8715 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8716
8717 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8718 val |= PIPECONF_INTERLACED_ILK;
8719 else
8720 val |= PIPECONF_PROGRESSIVE;
8721
8722 I915_WRITE(PIPECONF(cpu_transcoder), val);
8723 POSTING_READ(PIPECONF(cpu_transcoder));
8724 }
8725
8726 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8727 {
8728 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8730
8731 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8732 u32 val = 0;
8733
8734 switch (intel_crtc->config->pipe_bpp) {
8735 case 18:
8736 val |= PIPEMISC_DITHER_6_BPC;
8737 break;
8738 case 24:
8739 val |= PIPEMISC_DITHER_8_BPC;
8740 break;
8741 case 30:
8742 val |= PIPEMISC_DITHER_10_BPC;
8743 break;
8744 case 36:
8745 val |= PIPEMISC_DITHER_12_BPC;
8746 break;
8747 default:
8748 /* Case prevented by pipe_config_set_bpp. */
8749 BUG();
8750 }
8751
8752 if (intel_crtc->config->dither)
8753 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8754
8755 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8756 }
8757 }
8758
8759 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8760 {
8761 /*
8762 * Account for spread spectrum to avoid
8763 * oversubscribing the link. Max center spread
8764 * is 2.5%; use 5% for safety's sake.
8765 */
8766 u32 bps = target_clock * bpp * 21 / 20;
8767 return DIV_ROUND_UP(bps, link_bw * 8);
8768 }
8769
8770 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8771 {
8772 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8773 }
8774
8775 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8776 struct intel_crtc_state *crtc_state,
8777 struct dpll *reduced_clock)
8778 {
8779 struct drm_crtc *crtc = &intel_crtc->base;
8780 struct drm_device *dev = crtc->dev;
8781 struct drm_i915_private *dev_priv = dev->dev_private;
8782 struct drm_atomic_state *state = crtc_state->base.state;
8783 struct drm_connector *connector;
8784 struct drm_connector_state *connector_state;
8785 struct intel_encoder *encoder;
8786 u32 dpll, fp, fp2;
8787 int factor, i;
8788 bool is_lvds = false, is_sdvo = false;
8789
8790 for_each_connector_in_state(state, connector, connector_state, i) {
8791 if (connector_state->crtc != crtc_state->base.crtc)
8792 continue;
8793
8794 encoder = to_intel_encoder(connector_state->best_encoder);
8795
8796 switch (encoder->type) {
8797 case INTEL_OUTPUT_LVDS:
8798 is_lvds = true;
8799 break;
8800 case INTEL_OUTPUT_SDVO:
8801 case INTEL_OUTPUT_HDMI:
8802 is_sdvo = true;
8803 break;
8804 default:
8805 break;
8806 }
8807 }
8808
8809 /* Enable autotuning of the PLL clock (if permissible) */
8810 factor = 21;
8811 if (is_lvds) {
8812 if ((intel_panel_use_ssc(dev_priv) &&
8813 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8814 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8815 factor = 25;
8816 } else if (crtc_state->sdvo_tv_clock)
8817 factor = 20;
8818
8819 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8820
8821 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8822 fp |= FP_CB_TUNE;
8823
8824 if (reduced_clock) {
8825 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8826
8827 if (reduced_clock->m < factor * reduced_clock->n)
8828 fp2 |= FP_CB_TUNE;
8829 } else {
8830 fp2 = fp;
8831 }
8832
8833 dpll = 0;
8834
8835 if (is_lvds)
8836 dpll |= DPLLB_MODE_LVDS;
8837 else
8838 dpll |= DPLLB_MODE_DAC_SERIAL;
8839
8840 dpll |= (crtc_state->pixel_multiplier - 1)
8841 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8842
8843 if (is_sdvo)
8844 dpll |= DPLL_SDVO_HIGH_SPEED;
8845 if (crtc_state->has_dp_encoder)
8846 dpll |= DPLL_SDVO_HIGH_SPEED;
8847
8848 /* compute bitmask from p1 value */
8849 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8850 /* also FPA1 */
8851 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8852
8853 switch (crtc_state->dpll.p2) {
8854 case 5:
8855 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8856 break;
8857 case 7:
8858 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8859 break;
8860 case 10:
8861 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8862 break;
8863 case 14:
8864 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8865 break;
8866 }
8867
8868 if (is_lvds && intel_panel_use_ssc(dev_priv))
8869 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8870 else
8871 dpll |= PLL_REF_INPUT_DREFCLK;
8872
8873 dpll |= DPLL_VCO_ENABLE;
8874
8875 crtc_state->dpll_hw_state.dpll = dpll;
8876 crtc_state->dpll_hw_state.fp0 = fp;
8877 crtc_state->dpll_hw_state.fp1 = fp2;
8878 }
8879
8880 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8881 struct intel_crtc_state *crtc_state)
8882 {
8883 struct drm_device *dev = crtc->base.dev;
8884 struct drm_i915_private *dev_priv = dev->dev_private;
8885 struct dpll reduced_clock;
8886 bool has_reduced_clock = false;
8887 struct intel_shared_dpll *pll;
8888 const struct intel_limit *limit;
8889 int refclk = 120000;
8890
8891 memset(&crtc_state->dpll_hw_state, 0,
8892 sizeof(crtc_state->dpll_hw_state));
8893
8894 crtc->lowfreq_avail = false;
8895
8896 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8897 if (!crtc_state->has_pch_encoder)
8898 return 0;
8899
8900 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8901 if (intel_panel_use_ssc(dev_priv)) {
8902 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8903 dev_priv->vbt.lvds_ssc_freq);
8904 refclk = dev_priv->vbt.lvds_ssc_freq;
8905 }
8906
8907 if (intel_is_dual_link_lvds(dev)) {
8908 if (refclk == 100000)
8909 limit = &intel_limits_ironlake_dual_lvds_100m;
8910 else
8911 limit = &intel_limits_ironlake_dual_lvds;
8912 } else {
8913 if (refclk == 100000)
8914 limit = &intel_limits_ironlake_single_lvds_100m;
8915 else
8916 limit = &intel_limits_ironlake_single_lvds;
8917 }
8918 } else {
8919 limit = &intel_limits_ironlake_dac;
8920 }
8921
8922 if (!crtc_state->clock_set &&
8923 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8924 refclk, NULL, &crtc_state->dpll)) {
8925 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8926 return -EINVAL;
8927 }
8928
8929 ironlake_compute_dpll(crtc, crtc_state,
8930 has_reduced_clock ? &reduced_clock : NULL);
8931
8932 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8933 if (pll == NULL) {
8934 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8935 pipe_name(crtc->pipe));
8936 return -EINVAL;
8937 }
8938
8939 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8940 has_reduced_clock)
8941 crtc->lowfreq_avail = true;
8942
8943 return 0;
8944 }
8945
8946 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8947 struct intel_link_m_n *m_n)
8948 {
8949 struct drm_device *dev = crtc->base.dev;
8950 struct drm_i915_private *dev_priv = dev->dev_private;
8951 enum pipe pipe = crtc->pipe;
8952
8953 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8954 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8955 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8956 & ~TU_SIZE_MASK;
8957 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8958 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8959 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8960 }
8961
8962 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8963 enum transcoder transcoder,
8964 struct intel_link_m_n *m_n,
8965 struct intel_link_m_n *m2_n2)
8966 {
8967 struct drm_device *dev = crtc->base.dev;
8968 struct drm_i915_private *dev_priv = dev->dev_private;
8969 enum pipe pipe = crtc->pipe;
8970
8971 if (INTEL_INFO(dev)->gen >= 5) {
8972 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8973 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8974 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8975 & ~TU_SIZE_MASK;
8976 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8977 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8978 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8979 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8980 * gen < 8) and if DRRS is supported (to make sure the
8981 * registers are not unnecessarily read).
8982 */
8983 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8984 crtc->config->has_drrs) {
8985 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8986 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8987 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8988 & ~TU_SIZE_MASK;
8989 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8990 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8991 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8992 }
8993 } else {
8994 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8995 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8996 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8997 & ~TU_SIZE_MASK;
8998 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8999 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9000 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9001 }
9002 }
9003
9004 void intel_dp_get_m_n(struct intel_crtc *crtc,
9005 struct intel_crtc_state *pipe_config)
9006 {
9007 if (pipe_config->has_pch_encoder)
9008 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9009 else
9010 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9011 &pipe_config->dp_m_n,
9012 &pipe_config->dp_m2_n2);
9013 }
9014
9015 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9016 struct intel_crtc_state *pipe_config)
9017 {
9018 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9019 &pipe_config->fdi_m_n, NULL);
9020 }
9021
9022 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9023 struct intel_crtc_state *pipe_config)
9024 {
9025 struct drm_device *dev = crtc->base.dev;
9026 struct drm_i915_private *dev_priv = dev->dev_private;
9027 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9028 uint32_t ps_ctrl = 0;
9029 int id = -1;
9030 int i;
9031
9032 /* find scaler attached to this pipe */
9033 for (i = 0; i < crtc->num_scalers; i++) {
9034 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9035 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9036 id = i;
9037 pipe_config->pch_pfit.enabled = true;
9038 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9039 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9040 break;
9041 }
9042 }
9043
9044 scaler_state->scaler_id = id;
9045 if (id >= 0) {
9046 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9047 } else {
9048 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9049 }
9050 }
9051
9052 static void
9053 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9054 struct intel_initial_plane_config *plane_config)
9055 {
9056 struct drm_device *dev = crtc->base.dev;
9057 struct drm_i915_private *dev_priv = dev->dev_private;
9058 u32 val, base, offset, stride_mult, tiling;
9059 int pipe = crtc->pipe;
9060 int fourcc, pixel_format;
9061 unsigned int aligned_height;
9062 struct drm_framebuffer *fb;
9063 struct intel_framebuffer *intel_fb;
9064
9065 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9066 if (!intel_fb) {
9067 DRM_DEBUG_KMS("failed to alloc fb\n");
9068 return;
9069 }
9070
9071 fb = &intel_fb->base;
9072
9073 val = I915_READ(PLANE_CTL(pipe, 0));
9074 if (!(val & PLANE_CTL_ENABLE))
9075 goto error;
9076
9077 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9078 fourcc = skl_format_to_fourcc(pixel_format,
9079 val & PLANE_CTL_ORDER_RGBX,
9080 val & PLANE_CTL_ALPHA_MASK);
9081 fb->pixel_format = fourcc;
9082 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9083
9084 tiling = val & PLANE_CTL_TILED_MASK;
9085 switch (tiling) {
9086 case PLANE_CTL_TILED_LINEAR:
9087 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9088 break;
9089 case PLANE_CTL_TILED_X:
9090 plane_config->tiling = I915_TILING_X;
9091 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9092 break;
9093 case PLANE_CTL_TILED_Y:
9094 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9095 break;
9096 case PLANE_CTL_TILED_YF:
9097 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9098 break;
9099 default:
9100 MISSING_CASE(tiling);
9101 goto error;
9102 }
9103
9104 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9105 plane_config->base = base;
9106
9107 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9108
9109 val = I915_READ(PLANE_SIZE(pipe, 0));
9110 fb->height = ((val >> 16) & 0xfff) + 1;
9111 fb->width = ((val >> 0) & 0x1fff) + 1;
9112
9113 val = I915_READ(PLANE_STRIDE(pipe, 0));
9114 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9115 fb->pixel_format);
9116 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9117
9118 aligned_height = intel_fb_align_height(dev, fb->height,
9119 fb->pixel_format,
9120 fb->modifier[0]);
9121
9122 plane_config->size = fb->pitches[0] * aligned_height;
9123
9124 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9125 pipe_name(pipe), fb->width, fb->height,
9126 fb->bits_per_pixel, base, fb->pitches[0],
9127 plane_config->size);
9128
9129 plane_config->fb = intel_fb;
9130 return;
9131
9132 error:
9133 kfree(fb);
9134 }
9135
9136 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9137 struct intel_crtc_state *pipe_config)
9138 {
9139 struct drm_device *dev = crtc->base.dev;
9140 struct drm_i915_private *dev_priv = dev->dev_private;
9141 uint32_t tmp;
9142
9143 tmp = I915_READ(PF_CTL(crtc->pipe));
9144
9145 if (tmp & PF_ENABLE) {
9146 pipe_config->pch_pfit.enabled = true;
9147 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9148 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9149
9150 /* We currently do not free assignements of panel fitters on
9151 * ivb/hsw (since we don't use the higher upscaling modes which
9152 * differentiates them) so just WARN about this case for now. */
9153 if (IS_GEN7(dev)) {
9154 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9155 PF_PIPE_SEL_IVB(crtc->pipe));
9156 }
9157 }
9158 }
9159
9160 static void
9161 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9162 struct intel_initial_plane_config *plane_config)
9163 {
9164 struct drm_device *dev = crtc->base.dev;
9165 struct drm_i915_private *dev_priv = dev->dev_private;
9166 u32 val, base, offset;
9167 int pipe = crtc->pipe;
9168 int fourcc, pixel_format;
9169 unsigned int aligned_height;
9170 struct drm_framebuffer *fb;
9171 struct intel_framebuffer *intel_fb;
9172
9173 val = I915_READ(DSPCNTR(pipe));
9174 if (!(val & DISPLAY_PLANE_ENABLE))
9175 return;
9176
9177 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9178 if (!intel_fb) {
9179 DRM_DEBUG_KMS("failed to alloc fb\n");
9180 return;
9181 }
9182
9183 fb = &intel_fb->base;
9184
9185 if (INTEL_INFO(dev)->gen >= 4) {
9186 if (val & DISPPLANE_TILED) {
9187 plane_config->tiling = I915_TILING_X;
9188 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9189 }
9190 }
9191
9192 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9193 fourcc = i9xx_format_to_fourcc(pixel_format);
9194 fb->pixel_format = fourcc;
9195 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9196
9197 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9198 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9199 offset = I915_READ(DSPOFFSET(pipe));
9200 } else {
9201 if (plane_config->tiling)
9202 offset = I915_READ(DSPTILEOFF(pipe));
9203 else
9204 offset = I915_READ(DSPLINOFF(pipe));
9205 }
9206 plane_config->base = base;
9207
9208 val = I915_READ(PIPESRC(pipe));
9209 fb->width = ((val >> 16) & 0xfff) + 1;
9210 fb->height = ((val >> 0) & 0xfff) + 1;
9211
9212 val = I915_READ(DSPSTRIDE(pipe));
9213 fb->pitches[0] = val & 0xffffffc0;
9214
9215 aligned_height = intel_fb_align_height(dev, fb->height,
9216 fb->pixel_format,
9217 fb->modifier[0]);
9218
9219 plane_config->size = fb->pitches[0] * aligned_height;
9220
9221 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9222 pipe_name(pipe), fb->width, fb->height,
9223 fb->bits_per_pixel, base, fb->pitches[0],
9224 plane_config->size);
9225
9226 plane_config->fb = intel_fb;
9227 }
9228
9229 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9230 struct intel_crtc_state *pipe_config)
9231 {
9232 struct drm_device *dev = crtc->base.dev;
9233 struct drm_i915_private *dev_priv = dev->dev_private;
9234 enum intel_display_power_domain power_domain;
9235 uint32_t tmp;
9236 bool ret;
9237
9238 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9239 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9240 return false;
9241
9242 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9243 pipe_config->shared_dpll = NULL;
9244
9245 ret = false;
9246 tmp = I915_READ(PIPECONF(crtc->pipe));
9247 if (!(tmp & PIPECONF_ENABLE))
9248 goto out;
9249
9250 switch (tmp & PIPECONF_BPC_MASK) {
9251 case PIPECONF_6BPC:
9252 pipe_config->pipe_bpp = 18;
9253 break;
9254 case PIPECONF_8BPC:
9255 pipe_config->pipe_bpp = 24;
9256 break;
9257 case PIPECONF_10BPC:
9258 pipe_config->pipe_bpp = 30;
9259 break;
9260 case PIPECONF_12BPC:
9261 pipe_config->pipe_bpp = 36;
9262 break;
9263 default:
9264 break;
9265 }
9266
9267 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9268 pipe_config->limited_color_range = true;
9269
9270 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9271 struct intel_shared_dpll *pll;
9272 enum intel_dpll_id pll_id;
9273
9274 pipe_config->has_pch_encoder = true;
9275
9276 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9277 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9278 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9279
9280 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9281
9282 if (HAS_PCH_IBX(dev_priv)) {
9283 /*
9284 * The pipe->pch transcoder and pch transcoder->pll
9285 * mapping is fixed.
9286 */
9287 pll_id = (enum intel_dpll_id) crtc->pipe;
9288 } else {
9289 tmp = I915_READ(PCH_DPLL_SEL);
9290 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9291 pll_id = DPLL_ID_PCH_PLL_B;
9292 else
9293 pll_id= DPLL_ID_PCH_PLL_A;
9294 }
9295
9296 pipe_config->shared_dpll =
9297 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9298 pll = pipe_config->shared_dpll;
9299
9300 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9301 &pipe_config->dpll_hw_state));
9302
9303 tmp = pipe_config->dpll_hw_state.dpll;
9304 pipe_config->pixel_multiplier =
9305 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9306 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9307
9308 ironlake_pch_clock_get(crtc, pipe_config);
9309 } else {
9310 pipe_config->pixel_multiplier = 1;
9311 }
9312
9313 intel_get_pipe_timings(crtc, pipe_config);
9314 intel_get_pipe_src_size(crtc, pipe_config);
9315
9316 ironlake_get_pfit_config(crtc, pipe_config);
9317
9318 ret = true;
9319
9320 out:
9321 intel_display_power_put(dev_priv, power_domain);
9322
9323 return ret;
9324 }
9325
9326 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9327 {
9328 struct drm_device *dev = dev_priv->dev;
9329 struct intel_crtc *crtc;
9330
9331 for_each_intel_crtc(dev, crtc)
9332 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9333 pipe_name(crtc->pipe));
9334
9335 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9336 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9337 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9338 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9339 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9340 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9341 "CPU PWM1 enabled\n");
9342 if (IS_HASWELL(dev))
9343 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9344 "CPU PWM2 enabled\n");
9345 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9346 "PCH PWM1 enabled\n");
9347 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9348 "Utility pin enabled\n");
9349 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9350
9351 /*
9352 * In theory we can still leave IRQs enabled, as long as only the HPD
9353 * interrupts remain enabled. We used to check for that, but since it's
9354 * gen-specific and since we only disable LCPLL after we fully disable
9355 * the interrupts, the check below should be enough.
9356 */
9357 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9358 }
9359
9360 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9361 {
9362 struct drm_device *dev = dev_priv->dev;
9363
9364 if (IS_HASWELL(dev))
9365 return I915_READ(D_COMP_HSW);
9366 else
9367 return I915_READ(D_COMP_BDW);
9368 }
9369
9370 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9371 {
9372 struct drm_device *dev = dev_priv->dev;
9373
9374 if (IS_HASWELL(dev)) {
9375 mutex_lock(&dev_priv->rps.hw_lock);
9376 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9377 val))
9378 DRM_ERROR("Failed to write to D_COMP\n");
9379 mutex_unlock(&dev_priv->rps.hw_lock);
9380 } else {
9381 I915_WRITE(D_COMP_BDW, val);
9382 POSTING_READ(D_COMP_BDW);
9383 }
9384 }
9385
9386 /*
9387 * This function implements pieces of two sequences from BSpec:
9388 * - Sequence for display software to disable LCPLL
9389 * - Sequence for display software to allow package C8+
9390 * The steps implemented here are just the steps that actually touch the LCPLL
9391 * register. Callers should take care of disabling all the display engine
9392 * functions, doing the mode unset, fixing interrupts, etc.
9393 */
9394 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9395 bool switch_to_fclk, bool allow_power_down)
9396 {
9397 uint32_t val;
9398
9399 assert_can_disable_lcpll(dev_priv);
9400
9401 val = I915_READ(LCPLL_CTL);
9402
9403 if (switch_to_fclk) {
9404 val |= LCPLL_CD_SOURCE_FCLK;
9405 I915_WRITE(LCPLL_CTL, val);
9406
9407 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9408 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9409 DRM_ERROR("Switching to FCLK failed\n");
9410
9411 val = I915_READ(LCPLL_CTL);
9412 }
9413
9414 val |= LCPLL_PLL_DISABLE;
9415 I915_WRITE(LCPLL_CTL, val);
9416 POSTING_READ(LCPLL_CTL);
9417
9418 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9419 DRM_ERROR("LCPLL still locked\n");
9420
9421 val = hsw_read_dcomp(dev_priv);
9422 val |= D_COMP_COMP_DISABLE;
9423 hsw_write_dcomp(dev_priv, val);
9424 ndelay(100);
9425
9426 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9427 1))
9428 DRM_ERROR("D_COMP RCOMP still in progress\n");
9429
9430 if (allow_power_down) {
9431 val = I915_READ(LCPLL_CTL);
9432 val |= LCPLL_POWER_DOWN_ALLOW;
9433 I915_WRITE(LCPLL_CTL, val);
9434 POSTING_READ(LCPLL_CTL);
9435 }
9436 }
9437
9438 /*
9439 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9440 * source.
9441 */
9442 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9443 {
9444 uint32_t val;
9445
9446 val = I915_READ(LCPLL_CTL);
9447
9448 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9449 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9450 return;
9451
9452 /*
9453 * Make sure we're not on PC8 state before disabling PC8, otherwise
9454 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9455 */
9456 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9457
9458 if (val & LCPLL_POWER_DOWN_ALLOW) {
9459 val &= ~LCPLL_POWER_DOWN_ALLOW;
9460 I915_WRITE(LCPLL_CTL, val);
9461 POSTING_READ(LCPLL_CTL);
9462 }
9463
9464 val = hsw_read_dcomp(dev_priv);
9465 val |= D_COMP_COMP_FORCE;
9466 val &= ~D_COMP_COMP_DISABLE;
9467 hsw_write_dcomp(dev_priv, val);
9468
9469 val = I915_READ(LCPLL_CTL);
9470 val &= ~LCPLL_PLL_DISABLE;
9471 I915_WRITE(LCPLL_CTL, val);
9472
9473 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9474 DRM_ERROR("LCPLL not locked yet\n");
9475
9476 if (val & LCPLL_CD_SOURCE_FCLK) {
9477 val = I915_READ(LCPLL_CTL);
9478 val &= ~LCPLL_CD_SOURCE_FCLK;
9479 I915_WRITE(LCPLL_CTL, val);
9480
9481 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9482 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9483 DRM_ERROR("Switching back to LCPLL failed\n");
9484 }
9485
9486 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9487 intel_update_cdclk(dev_priv->dev);
9488 }
9489
9490 /*
9491 * Package states C8 and deeper are really deep PC states that can only be
9492 * reached when all the devices on the system allow it, so even if the graphics
9493 * device allows PC8+, it doesn't mean the system will actually get to these
9494 * states. Our driver only allows PC8+ when going into runtime PM.
9495 *
9496 * The requirements for PC8+ are that all the outputs are disabled, the power
9497 * well is disabled and most interrupts are disabled, and these are also
9498 * requirements for runtime PM. When these conditions are met, we manually do
9499 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9500 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9501 * hang the machine.
9502 *
9503 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9504 * the state of some registers, so when we come back from PC8+ we need to
9505 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9506 * need to take care of the registers kept by RC6. Notice that this happens even
9507 * if we don't put the device in PCI D3 state (which is what currently happens
9508 * because of the runtime PM support).
9509 *
9510 * For more, read "Display Sequences for Package C8" on the hardware
9511 * documentation.
9512 */
9513 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9514 {
9515 struct drm_device *dev = dev_priv->dev;
9516 uint32_t val;
9517
9518 DRM_DEBUG_KMS("Enabling package C8+\n");
9519
9520 if (HAS_PCH_LPT_LP(dev)) {
9521 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9522 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9523 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9524 }
9525
9526 lpt_disable_clkout_dp(dev);
9527 hsw_disable_lcpll(dev_priv, true, true);
9528 }
9529
9530 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9531 {
9532 struct drm_device *dev = dev_priv->dev;
9533 uint32_t val;
9534
9535 DRM_DEBUG_KMS("Disabling package C8+\n");
9536
9537 hsw_restore_lcpll(dev_priv);
9538 lpt_init_pch_refclk(dev);
9539
9540 if (HAS_PCH_LPT_LP(dev)) {
9541 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9542 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9543 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9544 }
9545 }
9546
9547 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9548 {
9549 struct drm_device *dev = old_state->dev;
9550 struct intel_atomic_state *old_intel_state =
9551 to_intel_atomic_state(old_state);
9552 unsigned int req_cdclk = old_intel_state->dev_cdclk;
9553
9554 broxton_set_cdclk(to_i915(dev), req_cdclk);
9555 }
9556
9557 /* compute the max rate for new configuration */
9558 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9559 {
9560 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9561 struct drm_i915_private *dev_priv = state->dev->dev_private;
9562 struct drm_crtc *crtc;
9563 struct drm_crtc_state *cstate;
9564 struct intel_crtc_state *crtc_state;
9565 unsigned max_pixel_rate = 0, i;
9566 enum pipe pipe;
9567
9568 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9569 sizeof(intel_state->min_pixclk));
9570
9571 for_each_crtc_in_state(state, crtc, cstate, i) {
9572 int pixel_rate;
9573
9574 crtc_state = to_intel_crtc_state(cstate);
9575 if (!crtc_state->base.enable) {
9576 intel_state->min_pixclk[i] = 0;
9577 continue;
9578 }
9579
9580 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9581
9582 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9583 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9584 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9585
9586 intel_state->min_pixclk[i] = pixel_rate;
9587 }
9588
9589 for_each_pipe(dev_priv, pipe)
9590 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9591
9592 return max_pixel_rate;
9593 }
9594
9595 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9596 {
9597 struct drm_i915_private *dev_priv = dev->dev_private;
9598 uint32_t val, data;
9599 int ret;
9600
9601 if (WARN((I915_READ(LCPLL_CTL) &
9602 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9603 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9604 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9605 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9606 "trying to change cdclk frequency with cdclk not enabled\n"))
9607 return;
9608
9609 mutex_lock(&dev_priv->rps.hw_lock);
9610 ret = sandybridge_pcode_write(dev_priv,
9611 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9612 mutex_unlock(&dev_priv->rps.hw_lock);
9613 if (ret) {
9614 DRM_ERROR("failed to inform pcode about cdclk change\n");
9615 return;
9616 }
9617
9618 val = I915_READ(LCPLL_CTL);
9619 val |= LCPLL_CD_SOURCE_FCLK;
9620 I915_WRITE(LCPLL_CTL, val);
9621
9622 if (wait_for_us(I915_READ(LCPLL_CTL) &
9623 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9624 DRM_ERROR("Switching to FCLK failed\n");
9625
9626 val = I915_READ(LCPLL_CTL);
9627 val &= ~LCPLL_CLK_FREQ_MASK;
9628
9629 switch (cdclk) {
9630 case 450000:
9631 val |= LCPLL_CLK_FREQ_450;
9632 data = 0;
9633 break;
9634 case 540000:
9635 val |= LCPLL_CLK_FREQ_54O_BDW;
9636 data = 1;
9637 break;
9638 case 337500:
9639 val |= LCPLL_CLK_FREQ_337_5_BDW;
9640 data = 2;
9641 break;
9642 case 675000:
9643 val |= LCPLL_CLK_FREQ_675_BDW;
9644 data = 3;
9645 break;
9646 default:
9647 WARN(1, "invalid cdclk frequency\n");
9648 return;
9649 }
9650
9651 I915_WRITE(LCPLL_CTL, val);
9652
9653 val = I915_READ(LCPLL_CTL);
9654 val &= ~LCPLL_CD_SOURCE_FCLK;
9655 I915_WRITE(LCPLL_CTL, val);
9656
9657 if (wait_for_us((I915_READ(LCPLL_CTL) &
9658 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9659 DRM_ERROR("Switching back to LCPLL failed\n");
9660
9661 mutex_lock(&dev_priv->rps.hw_lock);
9662 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9663 mutex_unlock(&dev_priv->rps.hw_lock);
9664
9665 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
9666
9667 intel_update_cdclk(dev);
9668
9669 WARN(cdclk != dev_priv->cdclk_freq,
9670 "cdclk requested %d kHz but got %d kHz\n",
9671 cdclk, dev_priv->cdclk_freq);
9672 }
9673
9674 static int broadwell_calc_cdclk(int max_pixclk)
9675 {
9676 if (max_pixclk > 540000)
9677 return 675000;
9678 else if (max_pixclk > 450000)
9679 return 540000;
9680 else if (max_pixclk > 337500)
9681 return 450000;
9682 else
9683 return 337500;
9684 }
9685
9686 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9687 {
9688 struct drm_i915_private *dev_priv = to_i915(state->dev);
9689 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9690 int max_pixclk = ilk_max_pixel_rate(state);
9691 int cdclk;
9692
9693 /*
9694 * FIXME should also account for plane ratio
9695 * once 64bpp pixel formats are supported.
9696 */
9697 cdclk = broadwell_calc_cdclk(max_pixclk);
9698
9699 if (cdclk > dev_priv->max_cdclk_freq) {
9700 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9701 cdclk, dev_priv->max_cdclk_freq);
9702 return -EINVAL;
9703 }
9704
9705 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9706 if (!intel_state->active_crtcs)
9707 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
9708
9709 return 0;
9710 }
9711
9712 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9713 {
9714 struct drm_device *dev = old_state->dev;
9715 struct intel_atomic_state *old_intel_state =
9716 to_intel_atomic_state(old_state);
9717 unsigned req_cdclk = old_intel_state->dev_cdclk;
9718
9719 broadwell_set_cdclk(dev, req_cdclk);
9720 }
9721
9722 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9723 struct intel_crtc_state *crtc_state)
9724 {
9725 struct intel_encoder *intel_encoder =
9726 intel_ddi_get_crtc_new_encoder(crtc_state);
9727
9728 if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9729 if (!intel_ddi_pll_select(crtc, crtc_state))
9730 return -EINVAL;
9731 }
9732
9733 crtc->lowfreq_avail = false;
9734
9735 return 0;
9736 }
9737
9738 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9739 enum port port,
9740 struct intel_crtc_state *pipe_config)
9741 {
9742 enum intel_dpll_id id;
9743
9744 switch (port) {
9745 case PORT_A:
9746 pipe_config->ddi_pll_sel = SKL_DPLL0;
9747 id = DPLL_ID_SKL_DPLL0;
9748 break;
9749 case PORT_B:
9750 pipe_config->ddi_pll_sel = SKL_DPLL1;
9751 id = DPLL_ID_SKL_DPLL1;
9752 break;
9753 case PORT_C:
9754 pipe_config->ddi_pll_sel = SKL_DPLL2;
9755 id = DPLL_ID_SKL_DPLL2;
9756 break;
9757 default:
9758 DRM_ERROR("Incorrect port type\n");
9759 return;
9760 }
9761
9762 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9763 }
9764
9765 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9766 enum port port,
9767 struct intel_crtc_state *pipe_config)
9768 {
9769 enum intel_dpll_id id;
9770 u32 temp;
9771
9772 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9773 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9774
9775 switch (pipe_config->ddi_pll_sel) {
9776 case SKL_DPLL0:
9777 id = DPLL_ID_SKL_DPLL0;
9778 break;
9779 case SKL_DPLL1:
9780 id = DPLL_ID_SKL_DPLL1;
9781 break;
9782 case SKL_DPLL2:
9783 id = DPLL_ID_SKL_DPLL2;
9784 break;
9785 case SKL_DPLL3:
9786 id = DPLL_ID_SKL_DPLL3;
9787 break;
9788 default:
9789 MISSING_CASE(pipe_config->ddi_pll_sel);
9790 return;
9791 }
9792
9793 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9794 }
9795
9796 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9797 enum port port,
9798 struct intel_crtc_state *pipe_config)
9799 {
9800 enum intel_dpll_id id;
9801
9802 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9803
9804 switch (pipe_config->ddi_pll_sel) {
9805 case PORT_CLK_SEL_WRPLL1:
9806 id = DPLL_ID_WRPLL1;
9807 break;
9808 case PORT_CLK_SEL_WRPLL2:
9809 id = DPLL_ID_WRPLL2;
9810 break;
9811 case PORT_CLK_SEL_SPLL:
9812 id = DPLL_ID_SPLL;
9813 break;
9814 case PORT_CLK_SEL_LCPLL_810:
9815 id = DPLL_ID_LCPLL_810;
9816 break;
9817 case PORT_CLK_SEL_LCPLL_1350:
9818 id = DPLL_ID_LCPLL_1350;
9819 break;
9820 case PORT_CLK_SEL_LCPLL_2700:
9821 id = DPLL_ID_LCPLL_2700;
9822 break;
9823 default:
9824 MISSING_CASE(pipe_config->ddi_pll_sel);
9825 /* fall through */
9826 case PORT_CLK_SEL_NONE:
9827 return;
9828 }
9829
9830 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9831 }
9832
9833 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9834 struct intel_crtc_state *pipe_config,
9835 unsigned long *power_domain_mask)
9836 {
9837 struct drm_device *dev = crtc->base.dev;
9838 struct drm_i915_private *dev_priv = dev->dev_private;
9839 enum intel_display_power_domain power_domain;
9840 u32 tmp;
9841
9842 /*
9843 * The pipe->transcoder mapping is fixed with the exception of the eDP
9844 * transcoder handled below.
9845 */
9846 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9847
9848 /*
9849 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9850 * consistency and less surprising code; it's in always on power).
9851 */
9852 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9853 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9854 enum pipe trans_edp_pipe;
9855 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9856 default:
9857 WARN(1, "unknown pipe linked to edp transcoder\n");
9858 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9859 case TRANS_DDI_EDP_INPUT_A_ON:
9860 trans_edp_pipe = PIPE_A;
9861 break;
9862 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9863 trans_edp_pipe = PIPE_B;
9864 break;
9865 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9866 trans_edp_pipe = PIPE_C;
9867 break;
9868 }
9869
9870 if (trans_edp_pipe == crtc->pipe)
9871 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9872 }
9873
9874 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9875 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9876 return false;
9877 *power_domain_mask |= BIT(power_domain);
9878
9879 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9880
9881 return tmp & PIPECONF_ENABLE;
9882 }
9883
9884 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9885 struct intel_crtc_state *pipe_config,
9886 unsigned long *power_domain_mask)
9887 {
9888 struct drm_device *dev = crtc->base.dev;
9889 struct drm_i915_private *dev_priv = dev->dev_private;
9890 enum intel_display_power_domain power_domain;
9891 enum port port;
9892 enum transcoder cpu_transcoder;
9893 u32 tmp;
9894
9895 pipe_config->has_dsi_encoder = false;
9896
9897 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9898 if (port == PORT_A)
9899 cpu_transcoder = TRANSCODER_DSI_A;
9900 else
9901 cpu_transcoder = TRANSCODER_DSI_C;
9902
9903 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9904 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9905 continue;
9906 *power_domain_mask |= BIT(power_domain);
9907
9908 /*
9909 * The PLL needs to be enabled with a valid divider
9910 * configuration, otherwise accessing DSI registers will hang
9911 * the machine. See BSpec North Display Engine
9912 * registers/MIPI[BXT]. We can break out here early, since we
9913 * need the same DSI PLL to be enabled for both DSI ports.
9914 */
9915 if (!intel_dsi_pll_is_enabled(dev_priv))
9916 break;
9917
9918 /* XXX: this works for video mode only */
9919 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9920 if (!(tmp & DPI_ENABLE))
9921 continue;
9922
9923 tmp = I915_READ(MIPI_CTRL(port));
9924 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9925 continue;
9926
9927 pipe_config->cpu_transcoder = cpu_transcoder;
9928 pipe_config->has_dsi_encoder = true;
9929 break;
9930 }
9931
9932 return pipe_config->has_dsi_encoder;
9933 }
9934
9935 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9936 struct intel_crtc_state *pipe_config)
9937 {
9938 struct drm_device *dev = crtc->base.dev;
9939 struct drm_i915_private *dev_priv = dev->dev_private;
9940 struct intel_shared_dpll *pll;
9941 enum port port;
9942 uint32_t tmp;
9943
9944 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9945
9946 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9947
9948 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9949 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9950 else if (IS_BROXTON(dev))
9951 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9952 else
9953 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9954
9955 pll = pipe_config->shared_dpll;
9956 if (pll) {
9957 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9958 &pipe_config->dpll_hw_state));
9959 }
9960
9961 /*
9962 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9963 * DDI E. So just check whether this pipe is wired to DDI E and whether
9964 * the PCH transcoder is on.
9965 */
9966 if (INTEL_INFO(dev)->gen < 9 &&
9967 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9968 pipe_config->has_pch_encoder = true;
9969
9970 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9971 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9972 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9973
9974 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9975 }
9976 }
9977
9978 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9979 struct intel_crtc_state *pipe_config)
9980 {
9981 struct drm_device *dev = crtc->base.dev;
9982 struct drm_i915_private *dev_priv = dev->dev_private;
9983 enum intel_display_power_domain power_domain;
9984 unsigned long power_domain_mask;
9985 bool active;
9986
9987 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9988 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9989 return false;
9990 power_domain_mask = BIT(power_domain);
9991
9992 pipe_config->shared_dpll = NULL;
9993
9994 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9995
9996 if (IS_BROXTON(dev_priv)) {
9997 bxt_get_dsi_transcoder_state(crtc, pipe_config,
9998 &power_domain_mask);
9999 WARN_ON(active && pipe_config->has_dsi_encoder);
10000 if (pipe_config->has_dsi_encoder)
10001 active = true;
10002 }
10003
10004 if (!active)
10005 goto out;
10006
10007 if (!pipe_config->has_dsi_encoder) {
10008 haswell_get_ddi_port_state(crtc, pipe_config);
10009 intel_get_pipe_timings(crtc, pipe_config);
10010 }
10011
10012 intel_get_pipe_src_size(crtc, pipe_config);
10013
10014 pipe_config->gamma_mode =
10015 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10016
10017 if (INTEL_INFO(dev)->gen >= 9) {
10018 skl_init_scalers(dev, crtc, pipe_config);
10019 }
10020
10021 if (INTEL_INFO(dev)->gen >= 9) {
10022 pipe_config->scaler_state.scaler_id = -1;
10023 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10024 }
10025
10026 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10027 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10028 power_domain_mask |= BIT(power_domain);
10029 if (INTEL_INFO(dev)->gen >= 9)
10030 skylake_get_pfit_config(crtc, pipe_config);
10031 else
10032 ironlake_get_pfit_config(crtc, pipe_config);
10033 }
10034
10035 if (IS_HASWELL(dev))
10036 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10037 (I915_READ(IPS_CTL) & IPS_ENABLE);
10038
10039 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10040 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10041 pipe_config->pixel_multiplier =
10042 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10043 } else {
10044 pipe_config->pixel_multiplier = 1;
10045 }
10046
10047 out:
10048 for_each_power_domain(power_domain, power_domain_mask)
10049 intel_display_power_put(dev_priv, power_domain);
10050
10051 return active;
10052 }
10053
10054 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10055 const struct intel_plane_state *plane_state)
10056 {
10057 struct drm_device *dev = crtc->dev;
10058 struct drm_i915_private *dev_priv = dev->dev_private;
10059 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10060 uint32_t cntl = 0, size = 0;
10061
10062 if (plane_state && plane_state->visible) {
10063 unsigned int width = plane_state->base.crtc_w;
10064 unsigned int height = plane_state->base.crtc_h;
10065 unsigned int stride = roundup_pow_of_two(width) * 4;
10066
10067 switch (stride) {
10068 default:
10069 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10070 width, stride);
10071 stride = 256;
10072 /* fallthrough */
10073 case 256:
10074 case 512:
10075 case 1024:
10076 case 2048:
10077 break;
10078 }
10079
10080 cntl |= CURSOR_ENABLE |
10081 CURSOR_GAMMA_ENABLE |
10082 CURSOR_FORMAT_ARGB |
10083 CURSOR_STRIDE(stride);
10084
10085 size = (height << 12) | width;
10086 }
10087
10088 if (intel_crtc->cursor_cntl != 0 &&
10089 (intel_crtc->cursor_base != base ||
10090 intel_crtc->cursor_size != size ||
10091 intel_crtc->cursor_cntl != cntl)) {
10092 /* On these chipsets we can only modify the base/size/stride
10093 * whilst the cursor is disabled.
10094 */
10095 I915_WRITE(CURCNTR(PIPE_A), 0);
10096 POSTING_READ(CURCNTR(PIPE_A));
10097 intel_crtc->cursor_cntl = 0;
10098 }
10099
10100 if (intel_crtc->cursor_base != base) {
10101 I915_WRITE(CURBASE(PIPE_A), base);
10102 intel_crtc->cursor_base = base;
10103 }
10104
10105 if (intel_crtc->cursor_size != size) {
10106 I915_WRITE(CURSIZE, size);
10107 intel_crtc->cursor_size = size;
10108 }
10109
10110 if (intel_crtc->cursor_cntl != cntl) {
10111 I915_WRITE(CURCNTR(PIPE_A), cntl);
10112 POSTING_READ(CURCNTR(PIPE_A));
10113 intel_crtc->cursor_cntl = cntl;
10114 }
10115 }
10116
10117 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10118 const struct intel_plane_state *plane_state)
10119 {
10120 struct drm_device *dev = crtc->dev;
10121 struct drm_i915_private *dev_priv = dev->dev_private;
10122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10123 int pipe = intel_crtc->pipe;
10124 uint32_t cntl = 0;
10125
10126 if (plane_state && plane_state->visible) {
10127 cntl = MCURSOR_GAMMA_ENABLE;
10128 switch (plane_state->base.crtc_w) {
10129 case 64:
10130 cntl |= CURSOR_MODE_64_ARGB_AX;
10131 break;
10132 case 128:
10133 cntl |= CURSOR_MODE_128_ARGB_AX;
10134 break;
10135 case 256:
10136 cntl |= CURSOR_MODE_256_ARGB_AX;
10137 break;
10138 default:
10139 MISSING_CASE(plane_state->base.crtc_w);
10140 return;
10141 }
10142 cntl |= pipe << 28; /* Connect to correct pipe */
10143
10144 if (HAS_DDI(dev))
10145 cntl |= CURSOR_PIPE_CSC_ENABLE;
10146
10147 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10148 cntl |= CURSOR_ROTATE_180;
10149 }
10150
10151 if (intel_crtc->cursor_cntl != cntl) {
10152 I915_WRITE(CURCNTR(pipe), cntl);
10153 POSTING_READ(CURCNTR(pipe));
10154 intel_crtc->cursor_cntl = cntl;
10155 }
10156
10157 /* and commit changes on next vblank */
10158 I915_WRITE(CURBASE(pipe), base);
10159 POSTING_READ(CURBASE(pipe));
10160
10161 intel_crtc->cursor_base = base;
10162 }
10163
10164 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10165 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10166 const struct intel_plane_state *plane_state)
10167 {
10168 struct drm_device *dev = crtc->dev;
10169 struct drm_i915_private *dev_priv = dev->dev_private;
10170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10171 int pipe = intel_crtc->pipe;
10172 u32 base = intel_crtc->cursor_addr;
10173 u32 pos = 0;
10174
10175 if (plane_state) {
10176 int x = plane_state->base.crtc_x;
10177 int y = plane_state->base.crtc_y;
10178
10179 if (x < 0) {
10180 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10181 x = -x;
10182 }
10183 pos |= x << CURSOR_X_SHIFT;
10184
10185 if (y < 0) {
10186 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10187 y = -y;
10188 }
10189 pos |= y << CURSOR_Y_SHIFT;
10190
10191 /* ILK+ do this automagically */
10192 if (HAS_GMCH_DISPLAY(dev) &&
10193 plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10194 base += (plane_state->base.crtc_h *
10195 plane_state->base.crtc_w - 1) * 4;
10196 }
10197 }
10198
10199 I915_WRITE(CURPOS(pipe), pos);
10200
10201 if (IS_845G(dev) || IS_I865G(dev))
10202 i845_update_cursor(crtc, base, plane_state);
10203 else
10204 i9xx_update_cursor(crtc, base, plane_state);
10205 }
10206
10207 static bool cursor_size_ok(struct drm_device *dev,
10208 uint32_t width, uint32_t height)
10209 {
10210 if (width == 0 || height == 0)
10211 return false;
10212
10213 /*
10214 * 845g/865g are special in that they are only limited by
10215 * the width of their cursors, the height is arbitrary up to
10216 * the precision of the register. Everything else requires
10217 * square cursors, limited to a few power-of-two sizes.
10218 */
10219 if (IS_845G(dev) || IS_I865G(dev)) {
10220 if ((width & 63) != 0)
10221 return false;
10222
10223 if (width > (IS_845G(dev) ? 64 : 512))
10224 return false;
10225
10226 if (height > 1023)
10227 return false;
10228 } else {
10229 switch (width | height) {
10230 case 256:
10231 case 128:
10232 if (IS_GEN2(dev))
10233 return false;
10234 case 64:
10235 break;
10236 default:
10237 return false;
10238 }
10239 }
10240
10241 return true;
10242 }
10243
10244 /* VESA 640x480x72Hz mode to set on the pipe */
10245 static struct drm_display_mode load_detect_mode = {
10246 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10247 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10248 };
10249
10250 struct drm_framebuffer *
10251 __intel_framebuffer_create(struct drm_device *dev,
10252 struct drm_mode_fb_cmd2 *mode_cmd,
10253 struct drm_i915_gem_object *obj)
10254 {
10255 struct intel_framebuffer *intel_fb;
10256 int ret;
10257
10258 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10259 if (!intel_fb)
10260 return ERR_PTR(-ENOMEM);
10261
10262 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10263 if (ret)
10264 goto err;
10265
10266 return &intel_fb->base;
10267
10268 err:
10269 kfree(intel_fb);
10270 return ERR_PTR(ret);
10271 }
10272
10273 static struct drm_framebuffer *
10274 intel_framebuffer_create(struct drm_device *dev,
10275 struct drm_mode_fb_cmd2 *mode_cmd,
10276 struct drm_i915_gem_object *obj)
10277 {
10278 struct drm_framebuffer *fb;
10279 int ret;
10280
10281 ret = i915_mutex_lock_interruptible(dev);
10282 if (ret)
10283 return ERR_PTR(ret);
10284 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10285 mutex_unlock(&dev->struct_mutex);
10286
10287 return fb;
10288 }
10289
10290 static u32
10291 intel_framebuffer_pitch_for_width(int width, int bpp)
10292 {
10293 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10294 return ALIGN(pitch, 64);
10295 }
10296
10297 static u32
10298 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10299 {
10300 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10301 return PAGE_ALIGN(pitch * mode->vdisplay);
10302 }
10303
10304 static struct drm_framebuffer *
10305 intel_framebuffer_create_for_mode(struct drm_device *dev,
10306 struct drm_display_mode *mode,
10307 int depth, int bpp)
10308 {
10309 struct drm_framebuffer *fb;
10310 struct drm_i915_gem_object *obj;
10311 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10312
10313 obj = i915_gem_object_create(dev,
10314 intel_framebuffer_size_for_mode(mode, bpp));
10315 if (IS_ERR(obj))
10316 return ERR_CAST(obj);
10317
10318 mode_cmd.width = mode->hdisplay;
10319 mode_cmd.height = mode->vdisplay;
10320 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10321 bpp);
10322 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10323
10324 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10325 if (IS_ERR(fb))
10326 drm_gem_object_unreference_unlocked(&obj->base);
10327
10328 return fb;
10329 }
10330
10331 static struct drm_framebuffer *
10332 mode_fits_in_fbdev(struct drm_device *dev,
10333 struct drm_display_mode *mode)
10334 {
10335 #ifdef CONFIG_DRM_FBDEV_EMULATION
10336 struct drm_i915_private *dev_priv = dev->dev_private;
10337 struct drm_i915_gem_object *obj;
10338 struct drm_framebuffer *fb;
10339
10340 if (!dev_priv->fbdev)
10341 return NULL;
10342
10343 if (!dev_priv->fbdev->fb)
10344 return NULL;
10345
10346 obj = dev_priv->fbdev->fb->obj;
10347 BUG_ON(!obj);
10348
10349 fb = &dev_priv->fbdev->fb->base;
10350 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10351 fb->bits_per_pixel))
10352 return NULL;
10353
10354 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10355 return NULL;
10356
10357 drm_framebuffer_reference(fb);
10358 return fb;
10359 #else
10360 return NULL;
10361 #endif
10362 }
10363
10364 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10365 struct drm_crtc *crtc,
10366 struct drm_display_mode *mode,
10367 struct drm_framebuffer *fb,
10368 int x, int y)
10369 {
10370 struct drm_plane_state *plane_state;
10371 int hdisplay, vdisplay;
10372 int ret;
10373
10374 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10375 if (IS_ERR(plane_state))
10376 return PTR_ERR(plane_state);
10377
10378 if (mode)
10379 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10380 else
10381 hdisplay = vdisplay = 0;
10382
10383 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10384 if (ret)
10385 return ret;
10386 drm_atomic_set_fb_for_plane(plane_state, fb);
10387 plane_state->crtc_x = 0;
10388 plane_state->crtc_y = 0;
10389 plane_state->crtc_w = hdisplay;
10390 plane_state->crtc_h = vdisplay;
10391 plane_state->src_x = x << 16;
10392 plane_state->src_y = y << 16;
10393 plane_state->src_w = hdisplay << 16;
10394 plane_state->src_h = vdisplay << 16;
10395
10396 return 0;
10397 }
10398
10399 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10400 struct drm_display_mode *mode,
10401 struct intel_load_detect_pipe *old,
10402 struct drm_modeset_acquire_ctx *ctx)
10403 {
10404 struct intel_crtc *intel_crtc;
10405 struct intel_encoder *intel_encoder =
10406 intel_attached_encoder(connector);
10407 struct drm_crtc *possible_crtc;
10408 struct drm_encoder *encoder = &intel_encoder->base;
10409 struct drm_crtc *crtc = NULL;
10410 struct drm_device *dev = encoder->dev;
10411 struct drm_framebuffer *fb;
10412 struct drm_mode_config *config = &dev->mode_config;
10413 struct drm_atomic_state *state = NULL, *restore_state = NULL;
10414 struct drm_connector_state *connector_state;
10415 struct intel_crtc_state *crtc_state;
10416 int ret, i = -1;
10417
10418 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10419 connector->base.id, connector->name,
10420 encoder->base.id, encoder->name);
10421
10422 old->restore_state = NULL;
10423
10424 retry:
10425 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10426 if (ret)
10427 goto fail;
10428
10429 /*
10430 * Algorithm gets a little messy:
10431 *
10432 * - if the connector already has an assigned crtc, use it (but make
10433 * sure it's on first)
10434 *
10435 * - try to find the first unused crtc that can drive this connector,
10436 * and use that if we find one
10437 */
10438
10439 /* See if we already have a CRTC for this connector */
10440 if (connector->state->crtc) {
10441 crtc = connector->state->crtc;
10442
10443 ret = drm_modeset_lock(&crtc->mutex, ctx);
10444 if (ret)
10445 goto fail;
10446
10447 /* Make sure the crtc and connector are running */
10448 goto found;
10449 }
10450
10451 /* Find an unused one (if possible) */
10452 for_each_crtc(dev, possible_crtc) {
10453 i++;
10454 if (!(encoder->possible_crtcs & (1 << i)))
10455 continue;
10456
10457 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10458 if (ret)
10459 goto fail;
10460
10461 if (possible_crtc->state->enable) {
10462 drm_modeset_unlock(&possible_crtc->mutex);
10463 continue;
10464 }
10465
10466 crtc = possible_crtc;
10467 break;
10468 }
10469
10470 /*
10471 * If we didn't find an unused CRTC, don't use any.
10472 */
10473 if (!crtc) {
10474 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10475 goto fail;
10476 }
10477
10478 found:
10479 intel_crtc = to_intel_crtc(crtc);
10480
10481 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10482 if (ret)
10483 goto fail;
10484
10485 state = drm_atomic_state_alloc(dev);
10486 restore_state = drm_atomic_state_alloc(dev);
10487 if (!state || !restore_state) {
10488 ret = -ENOMEM;
10489 goto fail;
10490 }
10491
10492 state->acquire_ctx = ctx;
10493 restore_state->acquire_ctx = ctx;
10494
10495 connector_state = drm_atomic_get_connector_state(state, connector);
10496 if (IS_ERR(connector_state)) {
10497 ret = PTR_ERR(connector_state);
10498 goto fail;
10499 }
10500
10501 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10502 if (ret)
10503 goto fail;
10504
10505 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10506 if (IS_ERR(crtc_state)) {
10507 ret = PTR_ERR(crtc_state);
10508 goto fail;
10509 }
10510
10511 crtc_state->base.active = crtc_state->base.enable = true;
10512
10513 if (!mode)
10514 mode = &load_detect_mode;
10515
10516 /* We need a framebuffer large enough to accommodate all accesses
10517 * that the plane may generate whilst we perform load detection.
10518 * We can not rely on the fbcon either being present (we get called
10519 * during its initialisation to detect all boot displays, or it may
10520 * not even exist) or that it is large enough to satisfy the
10521 * requested mode.
10522 */
10523 fb = mode_fits_in_fbdev(dev, mode);
10524 if (fb == NULL) {
10525 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10526 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10527 } else
10528 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10529 if (IS_ERR(fb)) {
10530 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10531 goto fail;
10532 }
10533
10534 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10535 if (ret)
10536 goto fail;
10537
10538 drm_framebuffer_unreference(fb);
10539
10540 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10541 if (ret)
10542 goto fail;
10543
10544 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10545 if (!ret)
10546 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10547 if (!ret)
10548 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10549 if (ret) {
10550 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10551 goto fail;
10552 }
10553
10554 ret = drm_atomic_commit(state);
10555 if (ret) {
10556 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10557 goto fail;
10558 }
10559
10560 old->restore_state = restore_state;
10561
10562 /* let the connector get through one full cycle before testing */
10563 intel_wait_for_vblank(dev, intel_crtc->pipe);
10564 return true;
10565
10566 fail:
10567 drm_atomic_state_free(state);
10568 drm_atomic_state_free(restore_state);
10569 restore_state = state = NULL;
10570
10571 if (ret == -EDEADLK) {
10572 drm_modeset_backoff(ctx);
10573 goto retry;
10574 }
10575
10576 return false;
10577 }
10578
10579 void intel_release_load_detect_pipe(struct drm_connector *connector,
10580 struct intel_load_detect_pipe *old,
10581 struct drm_modeset_acquire_ctx *ctx)
10582 {
10583 struct intel_encoder *intel_encoder =
10584 intel_attached_encoder(connector);
10585 struct drm_encoder *encoder = &intel_encoder->base;
10586 struct drm_atomic_state *state = old->restore_state;
10587 int ret;
10588
10589 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10590 connector->base.id, connector->name,
10591 encoder->base.id, encoder->name);
10592
10593 if (!state)
10594 return;
10595
10596 ret = drm_atomic_commit(state);
10597 if (ret) {
10598 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10599 drm_atomic_state_free(state);
10600 }
10601 }
10602
10603 static int i9xx_pll_refclk(struct drm_device *dev,
10604 const struct intel_crtc_state *pipe_config)
10605 {
10606 struct drm_i915_private *dev_priv = dev->dev_private;
10607 u32 dpll = pipe_config->dpll_hw_state.dpll;
10608
10609 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10610 return dev_priv->vbt.lvds_ssc_freq;
10611 else if (HAS_PCH_SPLIT(dev))
10612 return 120000;
10613 else if (!IS_GEN2(dev))
10614 return 96000;
10615 else
10616 return 48000;
10617 }
10618
10619 /* Returns the clock of the currently programmed mode of the given pipe. */
10620 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10621 struct intel_crtc_state *pipe_config)
10622 {
10623 struct drm_device *dev = crtc->base.dev;
10624 struct drm_i915_private *dev_priv = dev->dev_private;
10625 int pipe = pipe_config->cpu_transcoder;
10626 u32 dpll = pipe_config->dpll_hw_state.dpll;
10627 u32 fp;
10628 struct dpll clock;
10629 int port_clock;
10630 int refclk = i9xx_pll_refclk(dev, pipe_config);
10631
10632 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10633 fp = pipe_config->dpll_hw_state.fp0;
10634 else
10635 fp = pipe_config->dpll_hw_state.fp1;
10636
10637 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10638 if (IS_PINEVIEW(dev)) {
10639 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10640 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10641 } else {
10642 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10643 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10644 }
10645
10646 if (!IS_GEN2(dev)) {
10647 if (IS_PINEVIEW(dev))
10648 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10649 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10650 else
10651 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10652 DPLL_FPA01_P1_POST_DIV_SHIFT);
10653
10654 switch (dpll & DPLL_MODE_MASK) {
10655 case DPLLB_MODE_DAC_SERIAL:
10656 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10657 5 : 10;
10658 break;
10659 case DPLLB_MODE_LVDS:
10660 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10661 7 : 14;
10662 break;
10663 default:
10664 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10665 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10666 return;
10667 }
10668
10669 if (IS_PINEVIEW(dev))
10670 port_clock = pnv_calc_dpll_params(refclk, &clock);
10671 else
10672 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10673 } else {
10674 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10675 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10676
10677 if (is_lvds) {
10678 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10679 DPLL_FPA01_P1_POST_DIV_SHIFT);
10680
10681 if (lvds & LVDS_CLKB_POWER_UP)
10682 clock.p2 = 7;
10683 else
10684 clock.p2 = 14;
10685 } else {
10686 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10687 clock.p1 = 2;
10688 else {
10689 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10690 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10691 }
10692 if (dpll & PLL_P2_DIVIDE_BY_4)
10693 clock.p2 = 4;
10694 else
10695 clock.p2 = 2;
10696 }
10697
10698 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10699 }
10700
10701 /*
10702 * This value includes pixel_multiplier. We will use
10703 * port_clock to compute adjusted_mode.crtc_clock in the
10704 * encoder's get_config() function.
10705 */
10706 pipe_config->port_clock = port_clock;
10707 }
10708
10709 int intel_dotclock_calculate(int link_freq,
10710 const struct intel_link_m_n *m_n)
10711 {
10712 /*
10713 * The calculation for the data clock is:
10714 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10715 * But we want to avoid losing precison if possible, so:
10716 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10717 *
10718 * and the link clock is simpler:
10719 * link_clock = (m * link_clock) / n
10720 */
10721
10722 if (!m_n->link_n)
10723 return 0;
10724
10725 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10726 }
10727
10728 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10729 struct intel_crtc_state *pipe_config)
10730 {
10731 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10732
10733 /* read out port_clock from the DPLL */
10734 i9xx_crtc_clock_get(crtc, pipe_config);
10735
10736 /*
10737 * In case there is an active pipe without active ports,
10738 * we may need some idea for the dotclock anyway.
10739 * Calculate one based on the FDI configuration.
10740 */
10741 pipe_config->base.adjusted_mode.crtc_clock =
10742 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10743 &pipe_config->fdi_m_n);
10744 }
10745
10746 /** Returns the currently programmed mode of the given pipe. */
10747 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10748 struct drm_crtc *crtc)
10749 {
10750 struct drm_i915_private *dev_priv = dev->dev_private;
10751 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10752 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10753 struct drm_display_mode *mode;
10754 struct intel_crtc_state *pipe_config;
10755 int htot = I915_READ(HTOTAL(cpu_transcoder));
10756 int hsync = I915_READ(HSYNC(cpu_transcoder));
10757 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10758 int vsync = I915_READ(VSYNC(cpu_transcoder));
10759 enum pipe pipe = intel_crtc->pipe;
10760
10761 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10762 if (!mode)
10763 return NULL;
10764
10765 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10766 if (!pipe_config) {
10767 kfree(mode);
10768 return NULL;
10769 }
10770
10771 /*
10772 * Construct a pipe_config sufficient for getting the clock info
10773 * back out of crtc_clock_get.
10774 *
10775 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10776 * to use a real value here instead.
10777 */
10778 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10779 pipe_config->pixel_multiplier = 1;
10780 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10781 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10782 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10783 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10784
10785 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10786 mode->hdisplay = (htot & 0xffff) + 1;
10787 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10788 mode->hsync_start = (hsync & 0xffff) + 1;
10789 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10790 mode->vdisplay = (vtot & 0xffff) + 1;
10791 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10792 mode->vsync_start = (vsync & 0xffff) + 1;
10793 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10794
10795 drm_mode_set_name(mode);
10796
10797 kfree(pipe_config);
10798
10799 return mode;
10800 }
10801
10802 void intel_mark_busy(struct drm_i915_private *dev_priv)
10803 {
10804 if (dev_priv->mm.busy)
10805 return;
10806
10807 intel_runtime_pm_get(dev_priv);
10808 i915_update_gfx_val(dev_priv);
10809 if (INTEL_GEN(dev_priv) >= 6)
10810 gen6_rps_busy(dev_priv);
10811 dev_priv->mm.busy = true;
10812 }
10813
10814 void intel_mark_idle(struct drm_i915_private *dev_priv)
10815 {
10816 if (!dev_priv->mm.busy)
10817 return;
10818
10819 dev_priv->mm.busy = false;
10820
10821 if (INTEL_GEN(dev_priv) >= 6)
10822 gen6_rps_idle(dev_priv);
10823
10824 intel_runtime_pm_put(dev_priv);
10825 }
10826
10827 static void intel_crtc_destroy(struct drm_crtc *crtc)
10828 {
10829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10830 struct drm_device *dev = crtc->dev;
10831 struct intel_flip_work *work;
10832
10833 spin_lock_irq(&dev->event_lock);
10834 while (!list_empty(&intel_crtc->flip_work)) {
10835 work = list_first_entry(&intel_crtc->flip_work,
10836 struct intel_flip_work, head);
10837 list_del_init(&work->head);
10838 spin_unlock_irq(&dev->event_lock);
10839
10840 cancel_work_sync(&work->mmio_work);
10841 cancel_work_sync(&work->unpin_work);
10842 kfree(work);
10843
10844 spin_lock_irq(&dev->event_lock);
10845 }
10846 spin_unlock_irq(&dev->event_lock);
10847
10848 drm_crtc_cleanup(crtc);
10849
10850 kfree(intel_crtc);
10851 }
10852
10853 static void intel_unpin_work_fn(struct work_struct *__work)
10854 {
10855 struct intel_flip_work *work =
10856 container_of(__work, struct intel_flip_work, unpin_work);
10857 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10858 struct drm_device *dev = crtc->base.dev;
10859 struct drm_plane *primary = crtc->base.primary;
10860
10861 if (is_mmio_work(work))
10862 flush_work(&work->mmio_work);
10863
10864 mutex_lock(&dev->struct_mutex);
10865 intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
10866 drm_gem_object_unreference(&work->pending_flip_obj->base);
10867
10868 if (work->flip_queued_req)
10869 i915_gem_request_assign(&work->flip_queued_req, NULL);
10870 mutex_unlock(&dev->struct_mutex);
10871
10872 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10873 intel_fbc_post_update(crtc);
10874 drm_framebuffer_unreference(work->old_fb);
10875
10876 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10877 atomic_dec(&crtc->unpin_work_count);
10878
10879 kfree(work);
10880 }
10881
10882 /* Is 'a' after or equal to 'b'? */
10883 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10884 {
10885 return !((a - b) & 0x80000000);
10886 }
10887
10888 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
10889 struct intel_flip_work *work)
10890 {
10891 struct drm_device *dev = crtc->base.dev;
10892 struct drm_i915_private *dev_priv = dev->dev_private;
10893 unsigned reset_counter;
10894
10895 reset_counter = i915_reset_counter(&dev_priv->gpu_error);
10896 if (crtc->reset_counter != reset_counter)
10897 return true;
10898
10899 /*
10900 * The relevant registers doen't exist on pre-ctg.
10901 * As the flip done interrupt doesn't trigger for mmio
10902 * flips on gmch platforms, a flip count check isn't
10903 * really needed there. But since ctg has the registers,
10904 * include it in the check anyway.
10905 */
10906 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10907 return true;
10908
10909 /*
10910 * BDW signals flip done immediately if the plane
10911 * is disabled, even if the plane enable is already
10912 * armed to occur at the next vblank :(
10913 */
10914
10915 /*
10916 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10917 * used the same base address. In that case the mmio flip might
10918 * have completed, but the CS hasn't even executed the flip yet.
10919 *
10920 * A flip count check isn't enough as the CS might have updated
10921 * the base address just after start of vblank, but before we
10922 * managed to process the interrupt. This means we'd complete the
10923 * CS flip too soon.
10924 *
10925 * Combining both checks should get us a good enough result. It may
10926 * still happen that the CS flip has been executed, but has not
10927 * yet actually completed. But in case the base address is the same
10928 * anyway, we don't really care.
10929 */
10930 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10931 work->gtt_offset &&
10932 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10933 work->flip_count);
10934 }
10935
10936 static bool
10937 __pageflip_finished_mmio(struct intel_crtc *crtc,
10938 struct intel_flip_work *work)
10939 {
10940 /*
10941 * MMIO work completes when vblank is different from
10942 * flip_queued_vblank.
10943 *
10944 * Reset counter value doesn't matter, this is handled by
10945 * i915_wait_request finishing early, so no need to handle
10946 * reset here.
10947 */
10948 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
10949 }
10950
10951
10952 static bool pageflip_finished(struct intel_crtc *crtc,
10953 struct intel_flip_work *work)
10954 {
10955 if (!atomic_read(&work->pending))
10956 return false;
10957
10958 smp_rmb();
10959
10960 if (is_mmio_work(work))
10961 return __pageflip_finished_mmio(crtc, work);
10962 else
10963 return __pageflip_finished_cs(crtc, work);
10964 }
10965
10966 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
10967 {
10968 struct drm_device *dev = dev_priv->dev;
10969 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10971 struct intel_flip_work *work;
10972 unsigned long flags;
10973
10974 /* Ignore early vblank irqs */
10975 if (!crtc)
10976 return;
10977
10978 /*
10979 * This is called both by irq handlers and the reset code (to complete
10980 * lost pageflips) so needs the full irqsave spinlocks.
10981 */
10982 spin_lock_irqsave(&dev->event_lock, flags);
10983 while (!list_empty(&intel_crtc->flip_work)) {
10984 work = list_first_entry(&intel_crtc->flip_work,
10985 struct intel_flip_work,
10986 head);
10987
10988 if (is_mmio_work(work))
10989 break;
10990
10991 if (!pageflip_finished(intel_crtc, work))
10992 break;
10993
10994 page_flip_completed(intel_crtc, work);
10995 }
10996 spin_unlock_irqrestore(&dev->event_lock, flags);
10997 }
10998
10999 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11000 {
11001 struct drm_device *dev = dev_priv->dev;
11002 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11004 struct intel_flip_work *work;
11005 unsigned long flags;
11006
11007 /* Ignore early vblank irqs */
11008 if (!crtc)
11009 return;
11010
11011 /*
11012 * This is called both by irq handlers and the reset code (to complete
11013 * lost pageflips) so needs the full irqsave spinlocks.
11014 */
11015 spin_lock_irqsave(&dev->event_lock, flags);
11016 while (!list_empty(&intel_crtc->flip_work)) {
11017 work = list_first_entry(&intel_crtc->flip_work,
11018 struct intel_flip_work,
11019 head);
11020
11021 if (!is_mmio_work(work))
11022 break;
11023
11024 if (!pageflip_finished(intel_crtc, work))
11025 break;
11026
11027 page_flip_completed(intel_crtc, work);
11028 }
11029 spin_unlock_irqrestore(&dev->event_lock, flags);
11030 }
11031
11032 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11033 struct intel_flip_work *work)
11034 {
11035 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11036
11037 /* Ensure that the work item is consistent when activating it ... */
11038 smp_mb__before_atomic();
11039 atomic_set(&work->pending, 1);
11040 }
11041
11042 static int intel_gen2_queue_flip(struct drm_device *dev,
11043 struct drm_crtc *crtc,
11044 struct drm_framebuffer *fb,
11045 struct drm_i915_gem_object *obj,
11046 struct drm_i915_gem_request *req,
11047 uint64_t gtt_offset)
11048 {
11049 struct intel_engine_cs *engine = req->engine;
11050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11051 u32 flip_mask;
11052 int ret;
11053
11054 ret = intel_ring_begin(req, 6);
11055 if (ret)
11056 return ret;
11057
11058 /* Can't queue multiple flips, so wait for the previous
11059 * one to finish before executing the next.
11060 */
11061 if (intel_crtc->plane)
11062 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11063 else
11064 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11065 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11066 intel_ring_emit(engine, MI_NOOP);
11067 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11068 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11069 intel_ring_emit(engine, fb->pitches[0]);
11070 intel_ring_emit(engine, gtt_offset);
11071 intel_ring_emit(engine, 0); /* aux display base address, unused */
11072
11073 return 0;
11074 }
11075
11076 static int intel_gen3_queue_flip(struct drm_device *dev,
11077 struct drm_crtc *crtc,
11078 struct drm_framebuffer *fb,
11079 struct drm_i915_gem_object *obj,
11080 struct drm_i915_gem_request *req,
11081 uint64_t gtt_offset)
11082 {
11083 struct intel_engine_cs *engine = req->engine;
11084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11085 u32 flip_mask;
11086 int ret;
11087
11088 ret = intel_ring_begin(req, 6);
11089 if (ret)
11090 return ret;
11091
11092 if (intel_crtc->plane)
11093 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11094 else
11095 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11096 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11097 intel_ring_emit(engine, MI_NOOP);
11098 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
11099 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11100 intel_ring_emit(engine, fb->pitches[0]);
11101 intel_ring_emit(engine, gtt_offset);
11102 intel_ring_emit(engine, MI_NOOP);
11103
11104 return 0;
11105 }
11106
11107 static int intel_gen4_queue_flip(struct drm_device *dev,
11108 struct drm_crtc *crtc,
11109 struct drm_framebuffer *fb,
11110 struct drm_i915_gem_object *obj,
11111 struct drm_i915_gem_request *req,
11112 uint64_t gtt_offset)
11113 {
11114 struct intel_engine_cs *engine = req->engine;
11115 struct drm_i915_private *dev_priv = dev->dev_private;
11116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11117 uint32_t pf, pipesrc;
11118 int ret;
11119
11120 ret = intel_ring_begin(req, 4);
11121 if (ret)
11122 return ret;
11123
11124 /* i965+ uses the linear or tiled offsets from the
11125 * Display Registers (which do not change across a page-flip)
11126 * so we need only reprogram the base address.
11127 */
11128 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11129 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11130 intel_ring_emit(engine, fb->pitches[0]);
11131 intel_ring_emit(engine, gtt_offset | obj->tiling_mode);
11132
11133 /* XXX Enabling the panel-fitter across page-flip is so far
11134 * untested on non-native modes, so ignore it for now.
11135 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11136 */
11137 pf = 0;
11138 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11139 intel_ring_emit(engine, pf | pipesrc);
11140
11141 return 0;
11142 }
11143
11144 static int intel_gen6_queue_flip(struct drm_device *dev,
11145 struct drm_crtc *crtc,
11146 struct drm_framebuffer *fb,
11147 struct drm_i915_gem_object *obj,
11148 struct drm_i915_gem_request *req,
11149 uint64_t gtt_offset)
11150 {
11151 struct intel_engine_cs *engine = req->engine;
11152 struct drm_i915_private *dev_priv = dev->dev_private;
11153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11154 uint32_t pf, pipesrc;
11155 int ret;
11156
11157 ret = intel_ring_begin(req, 4);
11158 if (ret)
11159 return ret;
11160
11161 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11162 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11163 intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
11164 intel_ring_emit(engine, gtt_offset);
11165
11166 /* Contrary to the suggestions in the documentation,
11167 * "Enable Panel Fitter" does not seem to be required when page
11168 * flipping with a non-native mode, and worse causes a normal
11169 * modeset to fail.
11170 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11171 */
11172 pf = 0;
11173 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11174 intel_ring_emit(engine, pf | pipesrc);
11175
11176 return 0;
11177 }
11178
11179 static int intel_gen7_queue_flip(struct drm_device *dev,
11180 struct drm_crtc *crtc,
11181 struct drm_framebuffer *fb,
11182 struct drm_i915_gem_object *obj,
11183 struct drm_i915_gem_request *req,
11184 uint64_t gtt_offset)
11185 {
11186 struct intel_engine_cs *engine = req->engine;
11187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11188 uint32_t plane_bit = 0;
11189 int len, ret;
11190
11191 switch (intel_crtc->plane) {
11192 case PLANE_A:
11193 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11194 break;
11195 case PLANE_B:
11196 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11197 break;
11198 case PLANE_C:
11199 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11200 break;
11201 default:
11202 WARN_ONCE(1, "unknown plane in flip command\n");
11203 return -ENODEV;
11204 }
11205
11206 len = 4;
11207 if (engine->id == RCS) {
11208 len += 6;
11209 /*
11210 * On Gen 8, SRM is now taking an extra dword to accommodate
11211 * 48bits addresses, and we need a NOOP for the batch size to
11212 * stay even.
11213 */
11214 if (IS_GEN8(dev))
11215 len += 2;
11216 }
11217
11218 /*
11219 * BSpec MI_DISPLAY_FLIP for IVB:
11220 * "The full packet must be contained within the same cache line."
11221 *
11222 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11223 * cacheline, if we ever start emitting more commands before
11224 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11225 * then do the cacheline alignment, and finally emit the
11226 * MI_DISPLAY_FLIP.
11227 */
11228 ret = intel_ring_cacheline_align(req);
11229 if (ret)
11230 return ret;
11231
11232 ret = intel_ring_begin(req, len);
11233 if (ret)
11234 return ret;
11235
11236 /* Unmask the flip-done completion message. Note that the bspec says that
11237 * we should do this for both the BCS and RCS, and that we must not unmask
11238 * more than one flip event at any time (or ensure that one flip message
11239 * can be sent by waiting for flip-done prior to queueing new flips).
11240 * Experimentation says that BCS works despite DERRMR masking all
11241 * flip-done completion events and that unmasking all planes at once
11242 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11243 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11244 */
11245 if (engine->id == RCS) {
11246 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
11247 intel_ring_emit_reg(engine, DERRMR);
11248 intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11249 DERRMR_PIPEB_PRI_FLIP_DONE |
11250 DERRMR_PIPEC_PRI_FLIP_DONE));
11251 if (IS_GEN8(dev))
11252 intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
11253 MI_SRM_LRM_GLOBAL_GTT);
11254 else
11255 intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
11256 MI_SRM_LRM_GLOBAL_GTT);
11257 intel_ring_emit_reg(engine, DERRMR);
11258 intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
11259 if (IS_GEN8(dev)) {
11260 intel_ring_emit(engine, 0);
11261 intel_ring_emit(engine, MI_NOOP);
11262 }
11263 }
11264
11265 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
11266 intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
11267 intel_ring_emit(engine, gtt_offset);
11268 intel_ring_emit(engine, (MI_NOOP));
11269
11270 return 0;
11271 }
11272
11273 static bool use_mmio_flip(struct intel_engine_cs *engine,
11274 struct drm_i915_gem_object *obj)
11275 {
11276 /*
11277 * This is not being used for older platforms, because
11278 * non-availability of flip done interrupt forces us to use
11279 * CS flips. Older platforms derive flip done using some clever
11280 * tricks involving the flip_pending status bits and vblank irqs.
11281 * So using MMIO flips there would disrupt this mechanism.
11282 */
11283
11284 if (engine == NULL)
11285 return true;
11286
11287 if (i915.use_mmio_flip < 0)
11288 return false;
11289 else if (i915.use_mmio_flip > 0)
11290 return true;
11291 else if (i915.enable_execlists)
11292 return true;
11293 else if (obj->base.dma_buf &&
11294 !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11295 false))
11296 return true;
11297 else
11298 return engine != i915_gem_request_get_engine(obj->last_write_req);
11299 }
11300
11301 static void intel_mmio_flip_work_func(struct work_struct *w)
11302 {
11303 struct intel_flip_work *work =
11304 container_of(w, struct intel_flip_work, mmio_work);
11305 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11306 struct drm_device *dev = crtc->base.dev;
11307 struct drm_i915_private *dev_priv = dev->dev_private;
11308 struct intel_plane *primary = to_intel_plane(crtc->base.primary);
11309 struct drm_i915_gem_object *obj = intel_fb_obj(primary->base.state->fb);
11310
11311 if (work->flip_queued_req)
11312 WARN_ON(__i915_wait_request(work->flip_queued_req,
11313 false, NULL,
11314 &dev_priv->rps.mmioflips));
11315
11316 /* For framebuffer backed by dmabuf, wait for fence */
11317 if (obj->base.dma_buf)
11318 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11319 false, false,
11320 MAX_SCHEDULE_TIMEOUT) < 0);
11321
11322 intel_pipe_update_start(crtc);
11323 primary->update_plane(&primary->base,
11324 crtc->config,
11325 to_intel_plane_state(primary->base.state));
11326 intel_pipe_update_end(crtc, work);
11327 }
11328
11329 static int intel_default_queue_flip(struct drm_device *dev,
11330 struct drm_crtc *crtc,
11331 struct drm_framebuffer *fb,
11332 struct drm_i915_gem_object *obj,
11333 struct drm_i915_gem_request *req,
11334 uint64_t gtt_offset)
11335 {
11336 return -ENODEV;
11337 }
11338
11339 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
11340 struct intel_crtc *intel_crtc,
11341 struct intel_flip_work *work)
11342 {
11343 u32 addr, vblank;
11344
11345 if (!atomic_read(&work->pending))
11346 return false;
11347
11348 smp_rmb();
11349
11350 vblank = intel_crtc_get_vblank_counter(intel_crtc);
11351 if (work->flip_ready_vblank == 0) {
11352 if (work->flip_queued_req &&
11353 !i915_gem_request_completed(work->flip_queued_req, true))
11354 return false;
11355
11356 work->flip_ready_vblank = vblank;
11357 }
11358
11359 if (vblank - work->flip_ready_vblank < 3)
11360 return false;
11361
11362 /* Potential stall - if we see that the flip has happened,
11363 * assume a missed interrupt. */
11364 if (INTEL_GEN(dev_priv) >= 4)
11365 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11366 else
11367 addr = I915_READ(DSPADDR(intel_crtc->plane));
11368
11369 /* There is a potential issue here with a false positive after a flip
11370 * to the same address. We could address this by checking for a
11371 * non-incrementing frame counter.
11372 */
11373 return addr == work->gtt_offset;
11374 }
11375
11376 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
11377 {
11378 struct drm_device *dev = dev_priv->dev;
11379 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11380 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11381 struct intel_flip_work *work;
11382
11383 WARN_ON(!in_interrupt());
11384
11385 if (crtc == NULL)
11386 return;
11387
11388 spin_lock(&dev->event_lock);
11389 while (!list_empty(&intel_crtc->flip_work)) {
11390 work = list_first_entry(&intel_crtc->flip_work,
11391 struct intel_flip_work, head);
11392
11393 if (is_mmio_work(work))
11394 break;
11395
11396 if (__pageflip_stall_check_cs(dev_priv, intel_crtc, work)) {
11397 WARN_ONCE(1,
11398 "Kicking stuck page flip: queued at %d, now %d\n",
11399 work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc));
11400 page_flip_completed(intel_crtc, work);
11401 continue;
11402 }
11403
11404 if (intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1)
11405 intel_queue_rps_boost_for_request(work->flip_queued_req);
11406
11407 break;
11408 }
11409 spin_unlock(&dev->event_lock);
11410 }
11411
11412 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11413 struct drm_framebuffer *fb,
11414 struct drm_pending_vblank_event *event,
11415 uint32_t page_flip_flags)
11416 {
11417 struct drm_device *dev = crtc->dev;
11418 struct drm_i915_private *dev_priv = dev->dev_private;
11419 struct drm_framebuffer *old_fb = crtc->primary->fb;
11420 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11422 struct drm_plane *primary = crtc->primary;
11423 enum pipe pipe = intel_crtc->pipe;
11424 struct intel_flip_work *work;
11425 struct intel_engine_cs *engine;
11426 bool mmio_flip;
11427 struct drm_i915_gem_request *request = NULL;
11428 int ret;
11429
11430 /*
11431 * drm_mode_page_flip_ioctl() should already catch this, but double
11432 * check to be safe. In the future we may enable pageflipping from
11433 * a disabled primary plane.
11434 */
11435 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11436 return -EBUSY;
11437
11438 /* Can't change pixel format via MI display flips. */
11439 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11440 return -EINVAL;
11441
11442 /*
11443 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11444 * Note that pitch changes could also affect these register.
11445 */
11446 if (INTEL_INFO(dev)->gen > 3 &&
11447 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11448 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11449 return -EINVAL;
11450
11451 if (i915_terminally_wedged(&dev_priv->gpu_error))
11452 goto out_hang;
11453
11454 work = kzalloc(sizeof(*work), GFP_KERNEL);
11455 if (work == NULL)
11456 return -ENOMEM;
11457
11458 work->event = event;
11459 work->crtc = crtc;
11460 work->old_fb = old_fb;
11461 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
11462
11463 ret = drm_crtc_vblank_get(crtc);
11464 if (ret)
11465 goto free_work;
11466
11467 /* We borrow the event spin lock for protecting flip_work */
11468 spin_lock_irq(&dev->event_lock);
11469 if (!list_empty(&intel_crtc->flip_work)) {
11470 struct intel_flip_work *old_work;
11471
11472 old_work = list_last_entry(&intel_crtc->flip_work,
11473 struct intel_flip_work, head);
11474
11475 /* Before declaring the flip queue wedged, check if
11476 * the hardware completed the operation behind our backs.
11477 */
11478 if (pageflip_finished(intel_crtc, old_work)) {
11479 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11480 page_flip_completed(intel_crtc, old_work);
11481 } else {
11482 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11483 spin_unlock_irq(&dev->event_lock);
11484
11485 drm_crtc_vblank_put(crtc);
11486 kfree(work);
11487 return -EBUSY;
11488 }
11489 }
11490 list_add_tail(&work->head, &intel_crtc->flip_work);
11491 spin_unlock_irq(&dev->event_lock);
11492
11493 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11494 flush_workqueue(dev_priv->wq);
11495
11496 /* Reference the objects for the scheduled work. */
11497 drm_framebuffer_reference(work->old_fb);
11498 drm_gem_object_reference(&obj->base);
11499
11500 crtc->primary->fb = fb;
11501 update_state_fb(crtc->primary);
11502 intel_fbc_pre_update(intel_crtc);
11503
11504 work->pending_flip_obj = obj;
11505
11506 ret = i915_mutex_lock_interruptible(dev);
11507 if (ret)
11508 goto cleanup;
11509
11510 intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11511 if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) {
11512 ret = -EIO;
11513 goto cleanup;
11514 }
11515
11516 atomic_inc(&intel_crtc->unpin_work_count);
11517
11518 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11519 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11520
11521 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11522 engine = &dev_priv->engine[BCS];
11523 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11524 /* vlv: DISPLAY_FLIP fails to change tiling */
11525 engine = NULL;
11526 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11527 engine = &dev_priv->engine[BCS];
11528 } else if (INTEL_INFO(dev)->gen >= 7) {
11529 engine = i915_gem_request_get_engine(obj->last_write_req);
11530 if (engine == NULL || engine->id != RCS)
11531 engine = &dev_priv->engine[BCS];
11532 } else {
11533 engine = &dev_priv->engine[RCS];
11534 }
11535
11536 mmio_flip = use_mmio_flip(engine, obj);
11537
11538 /* When using CS flips, we want to emit semaphores between rings.
11539 * However, when using mmio flips we will create a task to do the
11540 * synchronisation, so all we want here is to pin the framebuffer
11541 * into the display plane and skip any waits.
11542 */
11543 if (!mmio_flip) {
11544 ret = i915_gem_object_sync(obj, engine, &request);
11545 if (!ret && !request) {
11546 request = i915_gem_request_alloc(engine, NULL);
11547 ret = PTR_ERR_OR_ZERO(request);
11548 }
11549
11550 if (ret)
11551 goto cleanup_pending;
11552 }
11553
11554 ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11555 if (ret)
11556 goto cleanup_pending;
11557
11558 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11559 obj, 0);
11560 work->gtt_offset += intel_crtc->dspaddr_offset;
11561
11562 if (mmio_flip) {
11563 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
11564
11565 i915_gem_request_assign(&work->flip_queued_req,
11566 obj->last_write_req);
11567
11568 schedule_work(&work->mmio_work);
11569 } else {
11570 i915_gem_request_assign(&work->flip_queued_req, request);
11571 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11572 work->gtt_offset);
11573 if (ret)
11574 goto cleanup_unpin;
11575
11576 intel_mark_page_flip_active(intel_crtc, work);
11577
11578 i915_add_request_no_flush(request);
11579 }
11580
11581 i915_gem_track_fb(intel_fb_obj(old_fb), obj,
11582 to_intel_plane(primary)->frontbuffer_bit);
11583 mutex_unlock(&dev->struct_mutex);
11584
11585 intel_frontbuffer_flip_prepare(dev,
11586 to_intel_plane(primary)->frontbuffer_bit);
11587
11588 trace_i915_flip_request(intel_crtc->plane, obj);
11589
11590 return 0;
11591
11592 cleanup_unpin:
11593 intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11594 cleanup_pending:
11595 if (!IS_ERR_OR_NULL(request))
11596 i915_add_request_no_flush(request);
11597 atomic_dec(&intel_crtc->unpin_work_count);
11598 mutex_unlock(&dev->struct_mutex);
11599 cleanup:
11600 crtc->primary->fb = old_fb;
11601 update_state_fb(crtc->primary);
11602
11603 drm_gem_object_unreference_unlocked(&obj->base);
11604 drm_framebuffer_unreference(work->old_fb);
11605
11606 spin_lock_irq(&dev->event_lock);
11607 list_del(&work->head);
11608 spin_unlock_irq(&dev->event_lock);
11609
11610 drm_crtc_vblank_put(crtc);
11611 free_work:
11612 kfree(work);
11613
11614 if (ret == -EIO) {
11615 struct drm_atomic_state *state;
11616 struct drm_plane_state *plane_state;
11617
11618 out_hang:
11619 state = drm_atomic_state_alloc(dev);
11620 if (!state)
11621 return -ENOMEM;
11622 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11623
11624 retry:
11625 plane_state = drm_atomic_get_plane_state(state, primary);
11626 ret = PTR_ERR_OR_ZERO(plane_state);
11627 if (!ret) {
11628 drm_atomic_set_fb_for_plane(plane_state, fb);
11629
11630 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11631 if (!ret)
11632 ret = drm_atomic_commit(state);
11633 }
11634
11635 if (ret == -EDEADLK) {
11636 drm_modeset_backoff(state->acquire_ctx);
11637 drm_atomic_state_clear(state);
11638 goto retry;
11639 }
11640
11641 if (ret)
11642 drm_atomic_state_free(state);
11643
11644 if (ret == 0 && event) {
11645 spin_lock_irq(&dev->event_lock);
11646 drm_crtc_send_vblank_event(crtc, event);
11647 spin_unlock_irq(&dev->event_lock);
11648 }
11649 }
11650 return ret;
11651 }
11652
11653
11654 /**
11655 * intel_wm_need_update - Check whether watermarks need updating
11656 * @plane: drm plane
11657 * @state: new plane state
11658 *
11659 * Check current plane state versus the new one to determine whether
11660 * watermarks need to be recalculated.
11661 *
11662 * Returns true or false.
11663 */
11664 static bool intel_wm_need_update(struct drm_plane *plane,
11665 struct drm_plane_state *state)
11666 {
11667 struct intel_plane_state *new = to_intel_plane_state(state);
11668 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11669
11670 /* Update watermarks on tiling or size changes. */
11671 if (new->visible != cur->visible)
11672 return true;
11673
11674 if (!cur->base.fb || !new->base.fb)
11675 return false;
11676
11677 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11678 cur->base.rotation != new->base.rotation ||
11679 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11680 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11681 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11682 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11683 return true;
11684
11685 return false;
11686 }
11687
11688 static bool needs_scaling(struct intel_plane_state *state)
11689 {
11690 int src_w = drm_rect_width(&state->src) >> 16;
11691 int src_h = drm_rect_height(&state->src) >> 16;
11692 int dst_w = drm_rect_width(&state->dst);
11693 int dst_h = drm_rect_height(&state->dst);
11694
11695 return (src_w != dst_w || src_h != dst_h);
11696 }
11697
11698 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11699 struct drm_plane_state *plane_state)
11700 {
11701 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11702 struct drm_crtc *crtc = crtc_state->crtc;
11703 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11704 struct drm_plane *plane = plane_state->plane;
11705 struct drm_device *dev = crtc->dev;
11706 struct drm_i915_private *dev_priv = to_i915(dev);
11707 struct intel_plane_state *old_plane_state =
11708 to_intel_plane_state(plane->state);
11709 int idx = intel_crtc->base.base.id, ret;
11710 bool mode_changed = needs_modeset(crtc_state);
11711 bool was_crtc_enabled = crtc->state->active;
11712 bool is_crtc_enabled = crtc_state->active;
11713 bool turn_off, turn_on, visible, was_visible;
11714 struct drm_framebuffer *fb = plane_state->fb;
11715
11716 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11717 plane->type != DRM_PLANE_TYPE_CURSOR) {
11718 ret = skl_update_scaler_plane(
11719 to_intel_crtc_state(crtc_state),
11720 to_intel_plane_state(plane_state));
11721 if (ret)
11722 return ret;
11723 }
11724
11725 was_visible = old_plane_state->visible;
11726 visible = to_intel_plane_state(plane_state)->visible;
11727
11728 if (!was_crtc_enabled && WARN_ON(was_visible))
11729 was_visible = false;
11730
11731 /*
11732 * Visibility is calculated as if the crtc was on, but
11733 * after scaler setup everything depends on it being off
11734 * when the crtc isn't active.
11735 *
11736 * FIXME this is wrong for watermarks. Watermarks should also
11737 * be computed as if the pipe would be active. Perhaps move
11738 * per-plane wm computation to the .check_plane() hook, and
11739 * only combine the results from all planes in the current place?
11740 */
11741 if (!is_crtc_enabled)
11742 to_intel_plane_state(plane_state)->visible = visible = false;
11743
11744 if (!was_visible && !visible)
11745 return 0;
11746
11747 if (fb != old_plane_state->base.fb)
11748 pipe_config->fb_changed = true;
11749
11750 turn_off = was_visible && (!visible || mode_changed);
11751 turn_on = visible && (!was_visible || mode_changed);
11752
11753 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11754 plane->base.id, fb ? fb->base.id : -1);
11755
11756 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11757 plane->base.id, was_visible, visible,
11758 turn_off, turn_on, mode_changed);
11759
11760 if (turn_on) {
11761 pipe_config->update_wm_pre = true;
11762
11763 /* must disable cxsr around plane enable/disable */
11764 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11765 pipe_config->disable_cxsr = true;
11766 } else if (turn_off) {
11767 pipe_config->update_wm_post = true;
11768
11769 /* must disable cxsr around plane enable/disable */
11770 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11771 pipe_config->disable_cxsr = true;
11772 } else if (intel_wm_need_update(plane, plane_state)) {
11773 /* FIXME bollocks */
11774 pipe_config->update_wm_pre = true;
11775 pipe_config->update_wm_post = true;
11776 }
11777
11778 /* Pre-gen9 platforms need two-step watermark updates */
11779 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
11780 INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
11781 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11782
11783 if (visible || was_visible)
11784 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
11785
11786 /*
11787 * WaCxSRDisabledForSpriteScaling:ivb
11788 *
11789 * cstate->update_wm was already set above, so this flag will
11790 * take effect when we commit and program watermarks.
11791 */
11792 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
11793 needs_scaling(to_intel_plane_state(plane_state)) &&
11794 !needs_scaling(old_plane_state))
11795 pipe_config->disable_lp_wm = true;
11796
11797 return 0;
11798 }
11799
11800 static bool encoders_cloneable(const struct intel_encoder *a,
11801 const struct intel_encoder *b)
11802 {
11803 /* masks could be asymmetric, so check both ways */
11804 return a == b || (a->cloneable & (1 << b->type) &&
11805 b->cloneable & (1 << a->type));
11806 }
11807
11808 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11809 struct intel_crtc *crtc,
11810 struct intel_encoder *encoder)
11811 {
11812 struct intel_encoder *source_encoder;
11813 struct drm_connector *connector;
11814 struct drm_connector_state *connector_state;
11815 int i;
11816
11817 for_each_connector_in_state(state, connector, connector_state, i) {
11818 if (connector_state->crtc != &crtc->base)
11819 continue;
11820
11821 source_encoder =
11822 to_intel_encoder(connector_state->best_encoder);
11823 if (!encoders_cloneable(encoder, source_encoder))
11824 return false;
11825 }
11826
11827 return true;
11828 }
11829
11830 static bool check_encoder_cloning(struct drm_atomic_state *state,
11831 struct intel_crtc *crtc)
11832 {
11833 struct intel_encoder *encoder;
11834 struct drm_connector *connector;
11835 struct drm_connector_state *connector_state;
11836 int i;
11837
11838 for_each_connector_in_state(state, connector, connector_state, i) {
11839 if (connector_state->crtc != &crtc->base)
11840 continue;
11841
11842 encoder = to_intel_encoder(connector_state->best_encoder);
11843 if (!check_single_encoder_cloning(state, crtc, encoder))
11844 return false;
11845 }
11846
11847 return true;
11848 }
11849
11850 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11851 struct drm_crtc_state *crtc_state)
11852 {
11853 struct drm_device *dev = crtc->dev;
11854 struct drm_i915_private *dev_priv = dev->dev_private;
11855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11856 struct intel_crtc_state *pipe_config =
11857 to_intel_crtc_state(crtc_state);
11858 struct drm_atomic_state *state = crtc_state->state;
11859 int ret;
11860 bool mode_changed = needs_modeset(crtc_state);
11861
11862 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11863 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11864 return -EINVAL;
11865 }
11866
11867 if (mode_changed && !crtc_state->active)
11868 pipe_config->update_wm_post = true;
11869
11870 if (mode_changed && crtc_state->enable &&
11871 dev_priv->display.crtc_compute_clock &&
11872 !WARN_ON(pipe_config->shared_dpll)) {
11873 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11874 pipe_config);
11875 if (ret)
11876 return ret;
11877 }
11878
11879 if (crtc_state->color_mgmt_changed) {
11880 ret = intel_color_check(crtc, crtc_state);
11881 if (ret)
11882 return ret;
11883 }
11884
11885 ret = 0;
11886 if (dev_priv->display.compute_pipe_wm) {
11887 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11888 if (ret) {
11889 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11890 return ret;
11891 }
11892 }
11893
11894 if (dev_priv->display.compute_intermediate_wm &&
11895 !to_intel_atomic_state(state)->skip_intermediate_wm) {
11896 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11897 return 0;
11898
11899 /*
11900 * Calculate 'intermediate' watermarks that satisfy both the
11901 * old state and the new state. We can program these
11902 * immediately.
11903 */
11904 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
11905 intel_crtc,
11906 pipe_config);
11907 if (ret) {
11908 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11909 return ret;
11910 }
11911 } else if (dev_priv->display.compute_intermediate_wm) {
11912 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
11913 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
11914 }
11915
11916 if (INTEL_INFO(dev)->gen >= 9) {
11917 if (mode_changed)
11918 ret = skl_update_scaler_crtc(pipe_config);
11919
11920 if (!ret)
11921 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11922 pipe_config);
11923 }
11924
11925 return ret;
11926 }
11927
11928 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11929 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11930 .atomic_begin = intel_begin_crtc_commit,
11931 .atomic_flush = intel_finish_crtc_commit,
11932 .atomic_check = intel_crtc_atomic_check,
11933 };
11934
11935 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11936 {
11937 struct intel_connector *connector;
11938
11939 for_each_intel_connector(dev, connector) {
11940 if (connector->base.state->crtc)
11941 drm_connector_unreference(&connector->base);
11942
11943 if (connector->base.encoder) {
11944 connector->base.state->best_encoder =
11945 connector->base.encoder;
11946 connector->base.state->crtc =
11947 connector->base.encoder->crtc;
11948
11949 drm_connector_reference(&connector->base);
11950 } else {
11951 connector->base.state->best_encoder = NULL;
11952 connector->base.state->crtc = NULL;
11953 }
11954 }
11955 }
11956
11957 static void
11958 connected_sink_compute_bpp(struct intel_connector *connector,
11959 struct intel_crtc_state *pipe_config)
11960 {
11961 int bpp = pipe_config->pipe_bpp;
11962
11963 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11964 connector->base.base.id,
11965 connector->base.name);
11966
11967 /* Don't use an invalid EDID bpc value */
11968 if (connector->base.display_info.bpc &&
11969 connector->base.display_info.bpc * 3 < bpp) {
11970 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11971 bpp, connector->base.display_info.bpc*3);
11972 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11973 }
11974
11975 /* Clamp bpp to default limit on screens without EDID 1.4 */
11976 if (connector->base.display_info.bpc == 0) {
11977 int type = connector->base.connector_type;
11978 int clamp_bpp = 24;
11979
11980 /* Fall back to 18 bpp when DP sink capability is unknown. */
11981 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
11982 type == DRM_MODE_CONNECTOR_eDP)
11983 clamp_bpp = 18;
11984
11985 if (bpp > clamp_bpp) {
11986 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
11987 bpp, clamp_bpp);
11988 pipe_config->pipe_bpp = clamp_bpp;
11989 }
11990 }
11991 }
11992
11993 static int
11994 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11995 struct intel_crtc_state *pipe_config)
11996 {
11997 struct drm_device *dev = crtc->base.dev;
11998 struct drm_atomic_state *state;
11999 struct drm_connector *connector;
12000 struct drm_connector_state *connector_state;
12001 int bpp, i;
12002
12003 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12004 bpp = 10*3;
12005 else if (INTEL_INFO(dev)->gen >= 5)
12006 bpp = 12*3;
12007 else
12008 bpp = 8*3;
12009
12010
12011 pipe_config->pipe_bpp = bpp;
12012
12013 state = pipe_config->base.state;
12014
12015 /* Clamp display bpp to EDID value */
12016 for_each_connector_in_state(state, connector, connector_state, i) {
12017 if (connector_state->crtc != &crtc->base)
12018 continue;
12019
12020 connected_sink_compute_bpp(to_intel_connector(connector),
12021 pipe_config);
12022 }
12023
12024 return bpp;
12025 }
12026
12027 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12028 {
12029 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12030 "type: 0x%x flags: 0x%x\n",
12031 mode->crtc_clock,
12032 mode->crtc_hdisplay, mode->crtc_hsync_start,
12033 mode->crtc_hsync_end, mode->crtc_htotal,
12034 mode->crtc_vdisplay, mode->crtc_vsync_start,
12035 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12036 }
12037
12038 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12039 struct intel_crtc_state *pipe_config,
12040 const char *context)
12041 {
12042 struct drm_device *dev = crtc->base.dev;
12043 struct drm_plane *plane;
12044 struct intel_plane *intel_plane;
12045 struct intel_plane_state *state;
12046 struct drm_framebuffer *fb;
12047
12048 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12049 context, pipe_config, pipe_name(crtc->pipe));
12050
12051 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12052 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12053 pipe_config->pipe_bpp, pipe_config->dither);
12054 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12055 pipe_config->has_pch_encoder,
12056 pipe_config->fdi_lanes,
12057 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12058 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12059 pipe_config->fdi_m_n.tu);
12060 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12061 pipe_config->has_dp_encoder,
12062 pipe_config->lane_count,
12063 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12064 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12065 pipe_config->dp_m_n.tu);
12066
12067 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12068 pipe_config->has_dp_encoder,
12069 pipe_config->lane_count,
12070 pipe_config->dp_m2_n2.gmch_m,
12071 pipe_config->dp_m2_n2.gmch_n,
12072 pipe_config->dp_m2_n2.link_m,
12073 pipe_config->dp_m2_n2.link_n,
12074 pipe_config->dp_m2_n2.tu);
12075
12076 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12077 pipe_config->has_audio,
12078 pipe_config->has_infoframe);
12079
12080 DRM_DEBUG_KMS("requested mode:\n");
12081 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12082 DRM_DEBUG_KMS("adjusted mode:\n");
12083 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12084 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12085 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12086 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12087 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12088 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12089 crtc->num_scalers,
12090 pipe_config->scaler_state.scaler_users,
12091 pipe_config->scaler_state.scaler_id);
12092 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12093 pipe_config->gmch_pfit.control,
12094 pipe_config->gmch_pfit.pgm_ratios,
12095 pipe_config->gmch_pfit.lvds_border_bits);
12096 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12097 pipe_config->pch_pfit.pos,
12098 pipe_config->pch_pfit.size,
12099 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12100 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12101 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12102
12103 if (IS_BROXTON(dev)) {
12104 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12105 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12106 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12107 pipe_config->ddi_pll_sel,
12108 pipe_config->dpll_hw_state.ebb0,
12109 pipe_config->dpll_hw_state.ebb4,
12110 pipe_config->dpll_hw_state.pll0,
12111 pipe_config->dpll_hw_state.pll1,
12112 pipe_config->dpll_hw_state.pll2,
12113 pipe_config->dpll_hw_state.pll3,
12114 pipe_config->dpll_hw_state.pll6,
12115 pipe_config->dpll_hw_state.pll8,
12116 pipe_config->dpll_hw_state.pll9,
12117 pipe_config->dpll_hw_state.pll10,
12118 pipe_config->dpll_hw_state.pcsdw12);
12119 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12120 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12121 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12122 pipe_config->ddi_pll_sel,
12123 pipe_config->dpll_hw_state.ctrl1,
12124 pipe_config->dpll_hw_state.cfgcr1,
12125 pipe_config->dpll_hw_state.cfgcr2);
12126 } else if (HAS_DDI(dev)) {
12127 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12128 pipe_config->ddi_pll_sel,
12129 pipe_config->dpll_hw_state.wrpll,
12130 pipe_config->dpll_hw_state.spll);
12131 } else {
12132 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12133 "fp0: 0x%x, fp1: 0x%x\n",
12134 pipe_config->dpll_hw_state.dpll,
12135 pipe_config->dpll_hw_state.dpll_md,
12136 pipe_config->dpll_hw_state.fp0,
12137 pipe_config->dpll_hw_state.fp1);
12138 }
12139
12140 DRM_DEBUG_KMS("planes on this crtc\n");
12141 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12142 intel_plane = to_intel_plane(plane);
12143 if (intel_plane->pipe != crtc->pipe)
12144 continue;
12145
12146 state = to_intel_plane_state(plane->state);
12147 fb = state->base.fb;
12148 if (!fb) {
12149 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12150 "disabled, scaler_id = %d\n",
12151 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12152 plane->base.id, intel_plane->pipe,
12153 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12154 drm_plane_index(plane), state->scaler_id);
12155 continue;
12156 }
12157
12158 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12159 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12160 plane->base.id, intel_plane->pipe,
12161 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12162 drm_plane_index(plane));
12163 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12164 fb->base.id, fb->width, fb->height, fb->pixel_format);
12165 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12166 state->scaler_id,
12167 state->src.x1 >> 16, state->src.y1 >> 16,
12168 drm_rect_width(&state->src) >> 16,
12169 drm_rect_height(&state->src) >> 16,
12170 state->dst.x1, state->dst.y1,
12171 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12172 }
12173 }
12174
12175 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12176 {
12177 struct drm_device *dev = state->dev;
12178 struct drm_connector *connector;
12179 unsigned int used_ports = 0;
12180
12181 /*
12182 * Walk the connector list instead of the encoder
12183 * list to detect the problem on ddi platforms
12184 * where there's just one encoder per digital port.
12185 */
12186 drm_for_each_connector(connector, dev) {
12187 struct drm_connector_state *connector_state;
12188 struct intel_encoder *encoder;
12189
12190 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12191 if (!connector_state)
12192 connector_state = connector->state;
12193
12194 if (!connector_state->best_encoder)
12195 continue;
12196
12197 encoder = to_intel_encoder(connector_state->best_encoder);
12198
12199 WARN_ON(!connector_state->crtc);
12200
12201 switch (encoder->type) {
12202 unsigned int port_mask;
12203 case INTEL_OUTPUT_UNKNOWN:
12204 if (WARN_ON(!HAS_DDI(dev)))
12205 break;
12206 case INTEL_OUTPUT_DISPLAYPORT:
12207 case INTEL_OUTPUT_HDMI:
12208 case INTEL_OUTPUT_EDP:
12209 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12210
12211 /* the same port mustn't appear more than once */
12212 if (used_ports & port_mask)
12213 return false;
12214
12215 used_ports |= port_mask;
12216 default:
12217 break;
12218 }
12219 }
12220
12221 return true;
12222 }
12223
12224 static void
12225 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12226 {
12227 struct drm_crtc_state tmp_state;
12228 struct intel_crtc_scaler_state scaler_state;
12229 struct intel_dpll_hw_state dpll_hw_state;
12230 struct intel_shared_dpll *shared_dpll;
12231 uint32_t ddi_pll_sel;
12232 bool force_thru;
12233
12234 /* FIXME: before the switch to atomic started, a new pipe_config was
12235 * kzalloc'd. Code that depends on any field being zero should be
12236 * fixed, so that the crtc_state can be safely duplicated. For now,
12237 * only fields that are know to not cause problems are preserved. */
12238
12239 tmp_state = crtc_state->base;
12240 scaler_state = crtc_state->scaler_state;
12241 shared_dpll = crtc_state->shared_dpll;
12242 dpll_hw_state = crtc_state->dpll_hw_state;
12243 ddi_pll_sel = crtc_state->ddi_pll_sel;
12244 force_thru = crtc_state->pch_pfit.force_thru;
12245
12246 memset(crtc_state, 0, sizeof *crtc_state);
12247
12248 crtc_state->base = tmp_state;
12249 crtc_state->scaler_state = scaler_state;
12250 crtc_state->shared_dpll = shared_dpll;
12251 crtc_state->dpll_hw_state = dpll_hw_state;
12252 crtc_state->ddi_pll_sel = ddi_pll_sel;
12253 crtc_state->pch_pfit.force_thru = force_thru;
12254 }
12255
12256 static int
12257 intel_modeset_pipe_config(struct drm_crtc *crtc,
12258 struct intel_crtc_state *pipe_config)
12259 {
12260 struct drm_atomic_state *state = pipe_config->base.state;
12261 struct intel_encoder *encoder;
12262 struct drm_connector *connector;
12263 struct drm_connector_state *connector_state;
12264 int base_bpp, ret = -EINVAL;
12265 int i;
12266 bool retry = true;
12267
12268 clear_intel_crtc_state(pipe_config);
12269
12270 pipe_config->cpu_transcoder =
12271 (enum transcoder) to_intel_crtc(crtc)->pipe;
12272
12273 /*
12274 * Sanitize sync polarity flags based on requested ones. If neither
12275 * positive or negative polarity is requested, treat this as meaning
12276 * negative polarity.
12277 */
12278 if (!(pipe_config->base.adjusted_mode.flags &
12279 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12280 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12281
12282 if (!(pipe_config->base.adjusted_mode.flags &
12283 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12284 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12285
12286 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12287 pipe_config);
12288 if (base_bpp < 0)
12289 goto fail;
12290
12291 /*
12292 * Determine the real pipe dimensions. Note that stereo modes can
12293 * increase the actual pipe size due to the frame doubling and
12294 * insertion of additional space for blanks between the frame. This
12295 * is stored in the crtc timings. We use the requested mode to do this
12296 * computation to clearly distinguish it from the adjusted mode, which
12297 * can be changed by the connectors in the below retry loop.
12298 */
12299 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12300 &pipe_config->pipe_src_w,
12301 &pipe_config->pipe_src_h);
12302
12303 encoder_retry:
12304 /* Ensure the port clock defaults are reset when retrying. */
12305 pipe_config->port_clock = 0;
12306 pipe_config->pixel_multiplier = 1;
12307
12308 /* Fill in default crtc timings, allow encoders to overwrite them. */
12309 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12310 CRTC_STEREO_DOUBLE);
12311
12312 /* Pass our mode to the connectors and the CRTC to give them a chance to
12313 * adjust it according to limitations or connector properties, and also
12314 * a chance to reject the mode entirely.
12315 */
12316 for_each_connector_in_state(state, connector, connector_state, i) {
12317 if (connector_state->crtc != crtc)
12318 continue;
12319
12320 encoder = to_intel_encoder(connector_state->best_encoder);
12321
12322 if (!(encoder->compute_config(encoder, pipe_config))) {
12323 DRM_DEBUG_KMS("Encoder config failure\n");
12324 goto fail;
12325 }
12326 }
12327
12328 /* Set default port clock if not overwritten by the encoder. Needs to be
12329 * done afterwards in case the encoder adjusts the mode. */
12330 if (!pipe_config->port_clock)
12331 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12332 * pipe_config->pixel_multiplier;
12333
12334 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12335 if (ret < 0) {
12336 DRM_DEBUG_KMS("CRTC fixup failed\n");
12337 goto fail;
12338 }
12339
12340 if (ret == RETRY) {
12341 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12342 ret = -EINVAL;
12343 goto fail;
12344 }
12345
12346 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12347 retry = false;
12348 goto encoder_retry;
12349 }
12350
12351 /* Dithering seems to not pass-through bits correctly when it should, so
12352 * only enable it on 6bpc panels. */
12353 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12354 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12355 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12356
12357 fail:
12358 return ret;
12359 }
12360
12361 static void
12362 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12363 {
12364 struct drm_crtc *crtc;
12365 struct drm_crtc_state *crtc_state;
12366 int i;
12367
12368 /* Double check state. */
12369 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12370 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12371
12372 /* Update hwmode for vblank functions */
12373 if (crtc->state->active)
12374 crtc->hwmode = crtc->state->adjusted_mode;
12375 else
12376 crtc->hwmode.crtc_clock = 0;
12377
12378 /*
12379 * Update legacy state to satisfy fbc code. This can
12380 * be removed when fbc uses the atomic state.
12381 */
12382 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12383 struct drm_plane_state *plane_state = crtc->primary->state;
12384
12385 crtc->primary->fb = plane_state->fb;
12386 crtc->x = plane_state->src_x >> 16;
12387 crtc->y = plane_state->src_y >> 16;
12388 }
12389 }
12390 }
12391
12392 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12393 {
12394 int diff;
12395
12396 if (clock1 == clock2)
12397 return true;
12398
12399 if (!clock1 || !clock2)
12400 return false;
12401
12402 diff = abs(clock1 - clock2);
12403
12404 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12405 return true;
12406
12407 return false;
12408 }
12409
12410 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12411 list_for_each_entry((intel_crtc), \
12412 &(dev)->mode_config.crtc_list, \
12413 base.head) \
12414 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12415
12416 static bool
12417 intel_compare_m_n(unsigned int m, unsigned int n,
12418 unsigned int m2, unsigned int n2,
12419 bool exact)
12420 {
12421 if (m == m2 && n == n2)
12422 return true;
12423
12424 if (exact || !m || !n || !m2 || !n2)
12425 return false;
12426
12427 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12428
12429 if (n > n2) {
12430 while (n > n2) {
12431 m2 <<= 1;
12432 n2 <<= 1;
12433 }
12434 } else if (n < n2) {
12435 while (n < n2) {
12436 m <<= 1;
12437 n <<= 1;
12438 }
12439 }
12440
12441 if (n != n2)
12442 return false;
12443
12444 return intel_fuzzy_clock_check(m, m2);
12445 }
12446
12447 static bool
12448 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12449 struct intel_link_m_n *m2_n2,
12450 bool adjust)
12451 {
12452 if (m_n->tu == m2_n2->tu &&
12453 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12454 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12455 intel_compare_m_n(m_n->link_m, m_n->link_n,
12456 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12457 if (adjust)
12458 *m2_n2 = *m_n;
12459
12460 return true;
12461 }
12462
12463 return false;
12464 }
12465
12466 static bool
12467 intel_pipe_config_compare(struct drm_device *dev,
12468 struct intel_crtc_state *current_config,
12469 struct intel_crtc_state *pipe_config,
12470 bool adjust)
12471 {
12472 bool ret = true;
12473
12474 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12475 do { \
12476 if (!adjust) \
12477 DRM_ERROR(fmt, ##__VA_ARGS__); \
12478 else \
12479 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12480 } while (0)
12481
12482 #define PIPE_CONF_CHECK_X(name) \
12483 if (current_config->name != pipe_config->name) { \
12484 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12485 "(expected 0x%08x, found 0x%08x)\n", \
12486 current_config->name, \
12487 pipe_config->name); \
12488 ret = false; \
12489 }
12490
12491 #define PIPE_CONF_CHECK_I(name) \
12492 if (current_config->name != pipe_config->name) { \
12493 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12494 "(expected %i, found %i)\n", \
12495 current_config->name, \
12496 pipe_config->name); \
12497 ret = false; \
12498 }
12499
12500 #define PIPE_CONF_CHECK_P(name) \
12501 if (current_config->name != pipe_config->name) { \
12502 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12503 "(expected %p, found %p)\n", \
12504 current_config->name, \
12505 pipe_config->name); \
12506 ret = false; \
12507 }
12508
12509 #define PIPE_CONF_CHECK_M_N(name) \
12510 if (!intel_compare_link_m_n(&current_config->name, \
12511 &pipe_config->name,\
12512 adjust)) { \
12513 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12514 "(expected tu %i gmch %i/%i link %i/%i, " \
12515 "found tu %i, gmch %i/%i link %i/%i)\n", \
12516 current_config->name.tu, \
12517 current_config->name.gmch_m, \
12518 current_config->name.gmch_n, \
12519 current_config->name.link_m, \
12520 current_config->name.link_n, \
12521 pipe_config->name.tu, \
12522 pipe_config->name.gmch_m, \
12523 pipe_config->name.gmch_n, \
12524 pipe_config->name.link_m, \
12525 pipe_config->name.link_n); \
12526 ret = false; \
12527 }
12528
12529 /* This is required for BDW+ where there is only one set of registers for
12530 * switching between high and low RR.
12531 * This macro can be used whenever a comparison has to be made between one
12532 * hw state and multiple sw state variables.
12533 */
12534 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12535 if (!intel_compare_link_m_n(&current_config->name, \
12536 &pipe_config->name, adjust) && \
12537 !intel_compare_link_m_n(&current_config->alt_name, \
12538 &pipe_config->name, adjust)) { \
12539 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12540 "(expected tu %i gmch %i/%i link %i/%i, " \
12541 "or tu %i gmch %i/%i link %i/%i, " \
12542 "found tu %i, gmch %i/%i link %i/%i)\n", \
12543 current_config->name.tu, \
12544 current_config->name.gmch_m, \
12545 current_config->name.gmch_n, \
12546 current_config->name.link_m, \
12547 current_config->name.link_n, \
12548 current_config->alt_name.tu, \
12549 current_config->alt_name.gmch_m, \
12550 current_config->alt_name.gmch_n, \
12551 current_config->alt_name.link_m, \
12552 current_config->alt_name.link_n, \
12553 pipe_config->name.tu, \
12554 pipe_config->name.gmch_m, \
12555 pipe_config->name.gmch_n, \
12556 pipe_config->name.link_m, \
12557 pipe_config->name.link_n); \
12558 ret = false; \
12559 }
12560
12561 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12562 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12563 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12564 "(expected %i, found %i)\n", \
12565 current_config->name & (mask), \
12566 pipe_config->name & (mask)); \
12567 ret = false; \
12568 }
12569
12570 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12571 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12572 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12573 "(expected %i, found %i)\n", \
12574 current_config->name, \
12575 pipe_config->name); \
12576 ret = false; \
12577 }
12578
12579 #define PIPE_CONF_QUIRK(quirk) \
12580 ((current_config->quirks | pipe_config->quirks) & (quirk))
12581
12582 PIPE_CONF_CHECK_I(cpu_transcoder);
12583
12584 PIPE_CONF_CHECK_I(has_pch_encoder);
12585 PIPE_CONF_CHECK_I(fdi_lanes);
12586 PIPE_CONF_CHECK_M_N(fdi_m_n);
12587
12588 PIPE_CONF_CHECK_I(has_dp_encoder);
12589 PIPE_CONF_CHECK_I(lane_count);
12590
12591 if (INTEL_INFO(dev)->gen < 8) {
12592 PIPE_CONF_CHECK_M_N(dp_m_n);
12593
12594 if (current_config->has_drrs)
12595 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12596 } else
12597 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12598
12599 PIPE_CONF_CHECK_I(has_dsi_encoder);
12600
12601 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12602 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12603 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12604 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12605 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12606 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12607
12608 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12609 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12610 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12611 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12612 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12613 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12614
12615 PIPE_CONF_CHECK_I(pixel_multiplier);
12616 PIPE_CONF_CHECK_I(has_hdmi_sink);
12617 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12618 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12619 PIPE_CONF_CHECK_I(limited_color_range);
12620 PIPE_CONF_CHECK_I(has_infoframe);
12621
12622 PIPE_CONF_CHECK_I(has_audio);
12623
12624 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12625 DRM_MODE_FLAG_INTERLACE);
12626
12627 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12628 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12629 DRM_MODE_FLAG_PHSYNC);
12630 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12631 DRM_MODE_FLAG_NHSYNC);
12632 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12633 DRM_MODE_FLAG_PVSYNC);
12634 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12635 DRM_MODE_FLAG_NVSYNC);
12636 }
12637
12638 PIPE_CONF_CHECK_X(gmch_pfit.control);
12639 /* pfit ratios are autocomputed by the hw on gen4+ */
12640 if (INTEL_INFO(dev)->gen < 4)
12641 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12642 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12643
12644 if (!adjust) {
12645 PIPE_CONF_CHECK_I(pipe_src_w);
12646 PIPE_CONF_CHECK_I(pipe_src_h);
12647
12648 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12649 if (current_config->pch_pfit.enabled) {
12650 PIPE_CONF_CHECK_X(pch_pfit.pos);
12651 PIPE_CONF_CHECK_X(pch_pfit.size);
12652 }
12653
12654 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12655 }
12656
12657 /* BDW+ don't expose a synchronous way to read the state */
12658 if (IS_HASWELL(dev))
12659 PIPE_CONF_CHECK_I(ips_enabled);
12660
12661 PIPE_CONF_CHECK_I(double_wide);
12662
12663 PIPE_CONF_CHECK_X(ddi_pll_sel);
12664
12665 PIPE_CONF_CHECK_P(shared_dpll);
12666 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12667 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12668 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12669 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12670 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12671 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12672 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12673 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12674 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12675
12676 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
12677 PIPE_CONF_CHECK_X(dsi_pll.div);
12678
12679 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12680 PIPE_CONF_CHECK_I(pipe_bpp);
12681
12682 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12683 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12684
12685 #undef PIPE_CONF_CHECK_X
12686 #undef PIPE_CONF_CHECK_I
12687 #undef PIPE_CONF_CHECK_P
12688 #undef PIPE_CONF_CHECK_FLAGS
12689 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12690 #undef PIPE_CONF_QUIRK
12691 #undef INTEL_ERR_OR_DBG_KMS
12692
12693 return ret;
12694 }
12695
12696 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12697 const struct intel_crtc_state *pipe_config)
12698 {
12699 if (pipe_config->has_pch_encoder) {
12700 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12701 &pipe_config->fdi_m_n);
12702 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12703
12704 /*
12705 * FDI already provided one idea for the dotclock.
12706 * Yell if the encoder disagrees.
12707 */
12708 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12709 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12710 fdi_dotclock, dotclock);
12711 }
12712 }
12713
12714 static void verify_wm_state(struct drm_crtc *crtc,
12715 struct drm_crtc_state *new_state)
12716 {
12717 struct drm_device *dev = crtc->dev;
12718 struct drm_i915_private *dev_priv = dev->dev_private;
12719 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12720 struct skl_ddb_entry *hw_entry, *sw_entry;
12721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12722 const enum pipe pipe = intel_crtc->pipe;
12723 int plane;
12724
12725 if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
12726 return;
12727
12728 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12729 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12730
12731 /* planes */
12732 for_each_plane(dev_priv, pipe, plane) {
12733 hw_entry = &hw_ddb.plane[pipe][plane];
12734 sw_entry = &sw_ddb->plane[pipe][plane];
12735
12736 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12737 continue;
12738
12739 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12740 "(expected (%u,%u), found (%u,%u))\n",
12741 pipe_name(pipe), plane + 1,
12742 sw_entry->start, sw_entry->end,
12743 hw_entry->start, hw_entry->end);
12744 }
12745
12746 /* cursor */
12747 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12748 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12749
12750 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
12751 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12752 "(expected (%u,%u), found (%u,%u))\n",
12753 pipe_name(pipe),
12754 sw_entry->start, sw_entry->end,
12755 hw_entry->start, hw_entry->end);
12756 }
12757 }
12758
12759 static void
12760 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
12761 {
12762 struct drm_connector *connector;
12763
12764 drm_for_each_connector(connector, dev) {
12765 struct drm_encoder *encoder = connector->encoder;
12766 struct drm_connector_state *state = connector->state;
12767
12768 if (state->crtc != crtc)
12769 continue;
12770
12771 intel_connector_verify_state(to_intel_connector(connector));
12772
12773 I915_STATE_WARN(state->best_encoder != encoder,
12774 "connector's atomic encoder doesn't match legacy encoder\n");
12775 }
12776 }
12777
12778 static void
12779 verify_encoder_state(struct drm_device *dev)
12780 {
12781 struct intel_encoder *encoder;
12782 struct intel_connector *connector;
12783
12784 for_each_intel_encoder(dev, encoder) {
12785 bool enabled = false;
12786 enum pipe pipe;
12787
12788 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12789 encoder->base.base.id,
12790 encoder->base.name);
12791
12792 for_each_intel_connector(dev, connector) {
12793 if (connector->base.state->best_encoder != &encoder->base)
12794 continue;
12795 enabled = true;
12796
12797 I915_STATE_WARN(connector->base.state->crtc !=
12798 encoder->base.crtc,
12799 "connector's crtc doesn't match encoder crtc\n");
12800 }
12801
12802 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12803 "encoder's enabled state mismatch "
12804 "(expected %i, found %i)\n",
12805 !!encoder->base.crtc, enabled);
12806
12807 if (!encoder->base.crtc) {
12808 bool active;
12809
12810 active = encoder->get_hw_state(encoder, &pipe);
12811 I915_STATE_WARN(active,
12812 "encoder detached but still enabled on pipe %c.\n",
12813 pipe_name(pipe));
12814 }
12815 }
12816 }
12817
12818 static void
12819 verify_crtc_state(struct drm_crtc *crtc,
12820 struct drm_crtc_state *old_crtc_state,
12821 struct drm_crtc_state *new_crtc_state)
12822 {
12823 struct drm_device *dev = crtc->dev;
12824 struct drm_i915_private *dev_priv = dev->dev_private;
12825 struct intel_encoder *encoder;
12826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12827 struct intel_crtc_state *pipe_config, *sw_config;
12828 struct drm_atomic_state *old_state;
12829 bool active;
12830
12831 old_state = old_crtc_state->state;
12832 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12833 pipe_config = to_intel_crtc_state(old_crtc_state);
12834 memset(pipe_config, 0, sizeof(*pipe_config));
12835 pipe_config->base.crtc = crtc;
12836 pipe_config->base.state = old_state;
12837
12838 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
12839
12840 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12841
12842 /* hw state is inconsistent with the pipe quirk */
12843 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12844 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12845 active = new_crtc_state->active;
12846
12847 I915_STATE_WARN(new_crtc_state->active != active,
12848 "crtc active state doesn't match with hw state "
12849 "(expected %i, found %i)\n", new_crtc_state->active, active);
12850
12851 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12852 "transitional active state does not match atomic hw state "
12853 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12854
12855 for_each_encoder_on_crtc(dev, crtc, encoder) {
12856 enum pipe pipe;
12857
12858 active = encoder->get_hw_state(encoder, &pipe);
12859 I915_STATE_WARN(active != new_crtc_state->active,
12860 "[ENCODER:%i] active %i with crtc active %i\n",
12861 encoder->base.base.id, active, new_crtc_state->active);
12862
12863 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12864 "Encoder connected to wrong pipe %c\n",
12865 pipe_name(pipe));
12866
12867 if (active)
12868 encoder->get_config(encoder, pipe_config);
12869 }
12870
12871 if (!new_crtc_state->active)
12872 return;
12873
12874 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12875
12876 sw_config = to_intel_crtc_state(crtc->state);
12877 if (!intel_pipe_config_compare(dev, sw_config,
12878 pipe_config, false)) {
12879 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12880 intel_dump_pipe_config(intel_crtc, pipe_config,
12881 "[hw state]");
12882 intel_dump_pipe_config(intel_crtc, sw_config,
12883 "[sw state]");
12884 }
12885 }
12886
12887 static void
12888 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12889 struct intel_shared_dpll *pll,
12890 struct drm_crtc *crtc,
12891 struct drm_crtc_state *new_state)
12892 {
12893 struct intel_dpll_hw_state dpll_hw_state;
12894 unsigned crtc_mask;
12895 bool active;
12896
12897 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12898
12899 DRM_DEBUG_KMS("%s\n", pll->name);
12900
12901 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12902
12903 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12904 I915_STATE_WARN(!pll->on && pll->active_mask,
12905 "pll in active use but not on in sw tracking\n");
12906 I915_STATE_WARN(pll->on && !pll->active_mask,
12907 "pll is on but not used by any active crtc\n");
12908 I915_STATE_WARN(pll->on != active,
12909 "pll on state mismatch (expected %i, found %i)\n",
12910 pll->on, active);
12911 }
12912
12913 if (!crtc) {
12914 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
12915 "more active pll users than references: %x vs %x\n",
12916 pll->active_mask, pll->config.crtc_mask);
12917
12918 return;
12919 }
12920
12921 crtc_mask = 1 << drm_crtc_index(crtc);
12922
12923 if (new_state->active)
12924 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12925 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12926 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12927 else
12928 I915_STATE_WARN(pll->active_mask & crtc_mask,
12929 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12930 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12931
12932 I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
12933 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12934 crtc_mask, pll->config.crtc_mask);
12935
12936 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
12937 &dpll_hw_state,
12938 sizeof(dpll_hw_state)),
12939 "pll hw state mismatch\n");
12940 }
12941
12942 static void
12943 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12944 struct drm_crtc_state *old_crtc_state,
12945 struct drm_crtc_state *new_crtc_state)
12946 {
12947 struct drm_i915_private *dev_priv = dev->dev_private;
12948 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12949 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12950
12951 if (new_state->shared_dpll)
12952 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
12953
12954 if (old_state->shared_dpll &&
12955 old_state->shared_dpll != new_state->shared_dpll) {
12956 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
12957 struct intel_shared_dpll *pll = old_state->shared_dpll;
12958
12959 I915_STATE_WARN(pll->active_mask & crtc_mask,
12960 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12961 pipe_name(drm_crtc_index(crtc)));
12962 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
12963 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12964 pipe_name(drm_crtc_index(crtc)));
12965 }
12966 }
12967
12968 static void
12969 intel_modeset_verify_crtc(struct drm_crtc *crtc,
12970 struct drm_crtc_state *old_state,
12971 struct drm_crtc_state *new_state)
12972 {
12973 if (!needs_modeset(new_state) &&
12974 !to_intel_crtc_state(new_state)->update_pipe)
12975 return;
12976
12977 verify_wm_state(crtc, new_state);
12978 verify_connector_state(crtc->dev, crtc);
12979 verify_crtc_state(crtc, old_state, new_state);
12980 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
12981 }
12982
12983 static void
12984 verify_disabled_dpll_state(struct drm_device *dev)
12985 {
12986 struct drm_i915_private *dev_priv = dev->dev_private;
12987 int i;
12988
12989 for (i = 0; i < dev_priv->num_shared_dpll; i++)
12990 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12991 }
12992
12993 static void
12994 intel_modeset_verify_disabled(struct drm_device *dev)
12995 {
12996 verify_encoder_state(dev);
12997 verify_connector_state(dev, NULL);
12998 verify_disabled_dpll_state(dev);
12999 }
13000
13001 static void update_scanline_offset(struct intel_crtc *crtc)
13002 {
13003 struct drm_device *dev = crtc->base.dev;
13004
13005 /*
13006 * The scanline counter increments at the leading edge of hsync.
13007 *
13008 * On most platforms it starts counting from vtotal-1 on the
13009 * first active line. That means the scanline counter value is
13010 * always one less than what we would expect. Ie. just after
13011 * start of vblank, which also occurs at start of hsync (on the
13012 * last active line), the scanline counter will read vblank_start-1.
13013 *
13014 * On gen2 the scanline counter starts counting from 1 instead
13015 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13016 * to keep the value positive), instead of adding one.
13017 *
13018 * On HSW+ the behaviour of the scanline counter depends on the output
13019 * type. For DP ports it behaves like most other platforms, but on HDMI
13020 * there's an extra 1 line difference. So we need to add two instead of
13021 * one to the value.
13022 */
13023 if (IS_GEN2(dev)) {
13024 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13025 int vtotal;
13026
13027 vtotal = adjusted_mode->crtc_vtotal;
13028 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13029 vtotal /= 2;
13030
13031 crtc->scanline_offset = vtotal - 1;
13032 } else if (HAS_DDI(dev) &&
13033 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13034 crtc->scanline_offset = 2;
13035 } else
13036 crtc->scanline_offset = 1;
13037 }
13038
13039 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13040 {
13041 struct drm_device *dev = state->dev;
13042 struct drm_i915_private *dev_priv = to_i915(dev);
13043 struct intel_shared_dpll_config *shared_dpll = NULL;
13044 struct drm_crtc *crtc;
13045 struct drm_crtc_state *crtc_state;
13046 int i;
13047
13048 if (!dev_priv->display.crtc_compute_clock)
13049 return;
13050
13051 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13053 struct intel_shared_dpll *old_dpll =
13054 to_intel_crtc_state(crtc->state)->shared_dpll;
13055
13056 if (!needs_modeset(crtc_state))
13057 continue;
13058
13059 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13060
13061 if (!old_dpll)
13062 continue;
13063
13064 if (!shared_dpll)
13065 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13066
13067 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13068 }
13069 }
13070
13071 /*
13072 * This implements the workaround described in the "notes" section of the mode
13073 * set sequence documentation. When going from no pipes or single pipe to
13074 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13075 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13076 */
13077 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13078 {
13079 struct drm_crtc_state *crtc_state;
13080 struct intel_crtc *intel_crtc;
13081 struct drm_crtc *crtc;
13082 struct intel_crtc_state *first_crtc_state = NULL;
13083 struct intel_crtc_state *other_crtc_state = NULL;
13084 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13085 int i;
13086
13087 /* look at all crtc's that are going to be enabled in during modeset */
13088 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13089 intel_crtc = to_intel_crtc(crtc);
13090
13091 if (!crtc_state->active || !needs_modeset(crtc_state))
13092 continue;
13093
13094 if (first_crtc_state) {
13095 other_crtc_state = to_intel_crtc_state(crtc_state);
13096 break;
13097 } else {
13098 first_crtc_state = to_intel_crtc_state(crtc_state);
13099 first_pipe = intel_crtc->pipe;
13100 }
13101 }
13102
13103 /* No workaround needed? */
13104 if (!first_crtc_state)
13105 return 0;
13106
13107 /* w/a possibly needed, check how many crtc's are already enabled. */
13108 for_each_intel_crtc(state->dev, intel_crtc) {
13109 struct intel_crtc_state *pipe_config;
13110
13111 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13112 if (IS_ERR(pipe_config))
13113 return PTR_ERR(pipe_config);
13114
13115 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13116
13117 if (!pipe_config->base.active ||
13118 needs_modeset(&pipe_config->base))
13119 continue;
13120
13121 /* 2 or more enabled crtcs means no need for w/a */
13122 if (enabled_pipe != INVALID_PIPE)
13123 return 0;
13124
13125 enabled_pipe = intel_crtc->pipe;
13126 }
13127
13128 if (enabled_pipe != INVALID_PIPE)
13129 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13130 else if (other_crtc_state)
13131 other_crtc_state->hsw_workaround_pipe = first_pipe;
13132
13133 return 0;
13134 }
13135
13136 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13137 {
13138 struct drm_crtc *crtc;
13139 struct drm_crtc_state *crtc_state;
13140 int ret = 0;
13141
13142 /* add all active pipes to the state */
13143 for_each_crtc(state->dev, crtc) {
13144 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13145 if (IS_ERR(crtc_state))
13146 return PTR_ERR(crtc_state);
13147
13148 if (!crtc_state->active || needs_modeset(crtc_state))
13149 continue;
13150
13151 crtc_state->mode_changed = true;
13152
13153 ret = drm_atomic_add_affected_connectors(state, crtc);
13154 if (ret)
13155 break;
13156
13157 ret = drm_atomic_add_affected_planes(state, crtc);
13158 if (ret)
13159 break;
13160 }
13161
13162 return ret;
13163 }
13164
13165 static int intel_modeset_checks(struct drm_atomic_state *state)
13166 {
13167 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13168 struct drm_i915_private *dev_priv = state->dev->dev_private;
13169 struct drm_crtc *crtc;
13170 struct drm_crtc_state *crtc_state;
13171 int ret = 0, i;
13172
13173 if (!check_digital_port_conflicts(state)) {
13174 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13175 return -EINVAL;
13176 }
13177
13178 intel_state->modeset = true;
13179 intel_state->active_crtcs = dev_priv->active_crtcs;
13180
13181 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13182 if (crtc_state->active)
13183 intel_state->active_crtcs |= 1 << i;
13184 else
13185 intel_state->active_crtcs &= ~(1 << i);
13186
13187 if (crtc_state->active != crtc->state->active)
13188 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13189 }
13190
13191 /*
13192 * See if the config requires any additional preparation, e.g.
13193 * to adjust global state with pipes off. We need to do this
13194 * here so we can get the modeset_pipe updated config for the new
13195 * mode set on this crtc. For other crtcs we need to use the
13196 * adjusted_mode bits in the crtc directly.
13197 */
13198 if (dev_priv->display.modeset_calc_cdclk) {
13199 ret = dev_priv->display.modeset_calc_cdclk(state);
13200
13201 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
13202 ret = intel_modeset_all_pipes(state);
13203
13204 if (ret < 0)
13205 return ret;
13206
13207 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13208 intel_state->cdclk, intel_state->dev_cdclk);
13209 } else
13210 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13211
13212 intel_modeset_clear_plls(state);
13213
13214 if (IS_HASWELL(dev_priv))
13215 return haswell_mode_set_planes_workaround(state);
13216
13217 return 0;
13218 }
13219
13220 /*
13221 * Handle calculation of various watermark data at the end of the atomic check
13222 * phase. The code here should be run after the per-crtc and per-plane 'check'
13223 * handlers to ensure that all derived state has been updated.
13224 */
13225 static int calc_watermark_data(struct drm_atomic_state *state)
13226 {
13227 struct drm_device *dev = state->dev;
13228 struct drm_i915_private *dev_priv = to_i915(dev);
13229
13230 /* Is there platform-specific watermark information to calculate? */
13231 if (dev_priv->display.compute_global_watermarks)
13232 return dev_priv->display.compute_global_watermarks(state);
13233
13234 return 0;
13235 }
13236
13237 /**
13238 * intel_atomic_check - validate state object
13239 * @dev: drm device
13240 * @state: state to validate
13241 */
13242 static int intel_atomic_check(struct drm_device *dev,
13243 struct drm_atomic_state *state)
13244 {
13245 struct drm_i915_private *dev_priv = to_i915(dev);
13246 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13247 struct drm_crtc *crtc;
13248 struct drm_crtc_state *crtc_state;
13249 int ret, i;
13250 bool any_ms = false;
13251
13252 ret = drm_atomic_helper_check_modeset(dev, state);
13253 if (ret)
13254 return ret;
13255
13256 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13257 struct intel_crtc_state *pipe_config =
13258 to_intel_crtc_state(crtc_state);
13259
13260 /* Catch I915_MODE_FLAG_INHERITED */
13261 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13262 crtc_state->mode_changed = true;
13263
13264 if (!needs_modeset(crtc_state))
13265 continue;
13266
13267 if (!crtc_state->enable) {
13268 any_ms = true;
13269 continue;
13270 }
13271
13272 /* FIXME: For only active_changed we shouldn't need to do any
13273 * state recomputation at all. */
13274
13275 ret = drm_atomic_add_affected_connectors(state, crtc);
13276 if (ret)
13277 return ret;
13278
13279 ret = intel_modeset_pipe_config(crtc, pipe_config);
13280 if (ret) {
13281 intel_dump_pipe_config(to_intel_crtc(crtc),
13282 pipe_config, "[failed]");
13283 return ret;
13284 }
13285
13286 if (i915.fastboot &&
13287 intel_pipe_config_compare(dev,
13288 to_intel_crtc_state(crtc->state),
13289 pipe_config, true)) {
13290 crtc_state->mode_changed = false;
13291 to_intel_crtc_state(crtc_state)->update_pipe = true;
13292 }
13293
13294 if (needs_modeset(crtc_state))
13295 any_ms = true;
13296
13297 ret = drm_atomic_add_affected_planes(state, crtc);
13298 if (ret)
13299 return ret;
13300
13301 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13302 needs_modeset(crtc_state) ?
13303 "[modeset]" : "[fastset]");
13304 }
13305
13306 if (any_ms) {
13307 ret = intel_modeset_checks(state);
13308
13309 if (ret)
13310 return ret;
13311 } else
13312 intel_state->cdclk = dev_priv->cdclk_freq;
13313
13314 ret = drm_atomic_helper_check_planes(dev, state);
13315 if (ret)
13316 return ret;
13317
13318 intel_fbc_choose_crtc(dev_priv, state);
13319 return calc_watermark_data(state);
13320 }
13321
13322 static int intel_atomic_prepare_commit(struct drm_device *dev,
13323 struct drm_atomic_state *state,
13324 bool nonblock)
13325 {
13326 struct drm_i915_private *dev_priv = dev->dev_private;
13327 struct drm_plane_state *plane_state;
13328 struct drm_crtc_state *crtc_state;
13329 struct drm_plane *plane;
13330 struct drm_crtc *crtc;
13331 int i, ret;
13332
13333 if (nonblock) {
13334 DRM_DEBUG_KMS("i915 does not yet support nonblocking commit\n");
13335 return -EINVAL;
13336 }
13337
13338 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13339 ret = intel_crtc_wait_for_pending_flips(crtc);
13340 if (ret)
13341 return ret;
13342
13343 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13344 flush_workqueue(dev_priv->wq);
13345 }
13346
13347 ret = mutex_lock_interruptible(&dev->struct_mutex);
13348 if (ret)
13349 return ret;
13350
13351 ret = drm_atomic_helper_prepare_planes(dev, state);
13352 mutex_unlock(&dev->struct_mutex);
13353
13354 if (!ret && !nonblock) {
13355 for_each_plane_in_state(state, plane, plane_state, i) {
13356 struct intel_plane_state *intel_plane_state =
13357 to_intel_plane_state(plane_state);
13358
13359 if (plane_state->fence) {
13360 long lret = fence_wait(plane_state->fence, true);
13361
13362 if (lret < 0) {
13363 ret = lret;
13364 break;
13365 }
13366 }
13367
13368 if (!intel_plane_state->wait_req)
13369 continue;
13370
13371 ret = __i915_wait_request(intel_plane_state->wait_req,
13372 true, NULL, NULL);
13373 if (ret) {
13374 /* Any hang should be swallowed by the wait */
13375 WARN_ON(ret == -EIO);
13376 mutex_lock(&dev->struct_mutex);
13377 drm_atomic_helper_cleanup_planes(dev, state);
13378 mutex_unlock(&dev->struct_mutex);
13379 break;
13380 }
13381 }
13382 }
13383
13384 return ret;
13385 }
13386
13387 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
13388 {
13389 struct drm_device *dev = crtc->base.dev;
13390
13391 if (!dev->max_vblank_count)
13392 return drm_accurate_vblank_count(&crtc->base);
13393
13394 return dev->driver->get_vblank_counter(dev, crtc->pipe);
13395 }
13396
13397 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13398 struct drm_i915_private *dev_priv,
13399 unsigned crtc_mask)
13400 {
13401 unsigned last_vblank_count[I915_MAX_PIPES];
13402 enum pipe pipe;
13403 int ret;
13404
13405 if (!crtc_mask)
13406 return;
13407
13408 for_each_pipe(dev_priv, pipe) {
13409 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13410
13411 if (!((1 << pipe) & crtc_mask))
13412 continue;
13413
13414 ret = drm_crtc_vblank_get(crtc);
13415 if (WARN_ON(ret != 0)) {
13416 crtc_mask &= ~(1 << pipe);
13417 continue;
13418 }
13419
13420 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13421 }
13422
13423 for_each_pipe(dev_priv, pipe) {
13424 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13425 long lret;
13426
13427 if (!((1 << pipe) & crtc_mask))
13428 continue;
13429
13430 lret = wait_event_timeout(dev->vblank[pipe].queue,
13431 last_vblank_count[pipe] !=
13432 drm_crtc_vblank_count(crtc),
13433 msecs_to_jiffies(50));
13434
13435 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
13436
13437 drm_crtc_vblank_put(crtc);
13438 }
13439 }
13440
13441 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13442 {
13443 /* fb updated, need to unpin old fb */
13444 if (crtc_state->fb_changed)
13445 return true;
13446
13447 /* wm changes, need vblank before final wm's */
13448 if (crtc_state->update_wm_post)
13449 return true;
13450
13451 /*
13452 * cxsr is re-enabled after vblank.
13453 * This is already handled by crtc_state->update_wm_post,
13454 * but added for clarity.
13455 */
13456 if (crtc_state->disable_cxsr)
13457 return true;
13458
13459 return false;
13460 }
13461
13462 /**
13463 * intel_atomic_commit - commit validated state object
13464 * @dev: DRM device
13465 * @state: the top-level driver state object
13466 * @nonblock: nonblocking commit
13467 *
13468 * This function commits a top-level state object that has been validated
13469 * with drm_atomic_helper_check().
13470 *
13471 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13472 * we can only handle plane-related operations and do not yet support
13473 * nonblocking commit.
13474 *
13475 * RETURNS
13476 * Zero for success or -errno.
13477 */
13478 static int intel_atomic_commit(struct drm_device *dev,
13479 struct drm_atomic_state *state,
13480 bool nonblock)
13481 {
13482 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13483 struct drm_i915_private *dev_priv = dev->dev_private;
13484 struct drm_crtc_state *old_crtc_state;
13485 struct drm_crtc *crtc;
13486 struct intel_crtc_state *intel_cstate;
13487 int ret = 0, i;
13488 bool hw_check = intel_state->modeset;
13489 unsigned long put_domains[I915_MAX_PIPES] = {};
13490 unsigned crtc_vblank_mask = 0;
13491
13492 ret = intel_atomic_prepare_commit(dev, state, nonblock);
13493 if (ret) {
13494 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13495 return ret;
13496 }
13497
13498 drm_atomic_helper_swap_state(dev, state);
13499 dev_priv->wm.distrust_bios_wm = false;
13500 dev_priv->wm.skl_results = intel_state->wm_results;
13501 intel_shared_dpll_commit(state);
13502
13503 if (intel_state->modeset) {
13504 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13505 sizeof(intel_state->min_pixclk));
13506 dev_priv->active_crtcs = intel_state->active_crtcs;
13507 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13508
13509 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13510 }
13511
13512 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13514
13515 if (needs_modeset(crtc->state) ||
13516 to_intel_crtc_state(crtc->state)->update_pipe) {
13517 hw_check = true;
13518
13519 put_domains[to_intel_crtc(crtc)->pipe] =
13520 modeset_get_crtc_power_domains(crtc,
13521 to_intel_crtc_state(crtc->state));
13522 }
13523
13524 if (!needs_modeset(crtc->state))
13525 continue;
13526
13527 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13528
13529 if (old_crtc_state->active) {
13530 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13531 dev_priv->display.crtc_disable(crtc);
13532 intel_crtc->active = false;
13533 intel_fbc_disable(intel_crtc);
13534 intel_disable_shared_dpll(intel_crtc);
13535
13536 /*
13537 * Underruns don't always raise
13538 * interrupts, so check manually.
13539 */
13540 intel_check_cpu_fifo_underruns(dev_priv);
13541 intel_check_pch_fifo_underruns(dev_priv);
13542
13543 if (!crtc->state->active)
13544 intel_update_watermarks(crtc);
13545 }
13546 }
13547
13548 /* Only after disabling all output pipelines that will be changed can we
13549 * update the the output configuration. */
13550 intel_modeset_update_crtc_state(state);
13551
13552 if (intel_state->modeset) {
13553 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13554
13555 if (dev_priv->display.modeset_commit_cdclk &&
13556 intel_state->dev_cdclk != dev_priv->cdclk_freq)
13557 dev_priv->display.modeset_commit_cdclk(state);
13558
13559 intel_modeset_verify_disabled(dev);
13560 }
13561
13562 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13563 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13565 bool modeset = needs_modeset(crtc->state);
13566 struct intel_crtc_state *pipe_config =
13567 to_intel_crtc_state(crtc->state);
13568 bool update_pipe = !modeset && pipe_config->update_pipe;
13569
13570 if (modeset && crtc->state->active) {
13571 update_scanline_offset(to_intel_crtc(crtc));
13572 dev_priv->display.crtc_enable(crtc);
13573 }
13574
13575 if (!modeset)
13576 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13577
13578 if (crtc->state->active &&
13579 drm_atomic_get_existing_plane_state(state, crtc->primary))
13580 intel_fbc_enable(intel_crtc);
13581
13582 if (crtc->state->active &&
13583 (crtc->state->planes_changed || update_pipe))
13584 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
13585
13586 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13587 crtc_vblank_mask |= 1 << i;
13588 }
13589
13590 /* FIXME: add subpixel order */
13591
13592 if (!state->legacy_cursor_update)
13593 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13594
13595 /*
13596 * Now that the vblank has passed, we can go ahead and program the
13597 * optimal watermarks on platforms that need two-step watermark
13598 * programming.
13599 *
13600 * TODO: Move this (and other cleanup) to an async worker eventually.
13601 */
13602 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13603 intel_cstate = to_intel_crtc_state(crtc->state);
13604
13605 if (dev_priv->display.optimize_watermarks)
13606 dev_priv->display.optimize_watermarks(intel_cstate);
13607 }
13608
13609 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13610 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13611
13612 if (put_domains[i])
13613 modeset_put_power_domains(dev_priv, put_domains[i]);
13614
13615 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
13616 }
13617
13618 if (intel_state->modeset)
13619 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13620
13621 mutex_lock(&dev->struct_mutex);
13622 drm_atomic_helper_cleanup_planes(dev, state);
13623 mutex_unlock(&dev->struct_mutex);
13624
13625 drm_atomic_state_free(state);
13626
13627 /* As one of the primary mmio accessors, KMS has a high likelihood
13628 * of triggering bugs in unclaimed access. After we finish
13629 * modesetting, see if an error has been flagged, and if so
13630 * enable debugging for the next modeset - and hope we catch
13631 * the culprit.
13632 *
13633 * XXX note that we assume display power is on at this point.
13634 * This might hold true now but we need to add pm helper to check
13635 * unclaimed only when the hardware is on, as atomic commits
13636 * can happen also when the device is completely off.
13637 */
13638 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13639
13640 return 0;
13641 }
13642
13643 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13644 {
13645 struct drm_device *dev = crtc->dev;
13646 struct drm_atomic_state *state;
13647 struct drm_crtc_state *crtc_state;
13648 int ret;
13649
13650 state = drm_atomic_state_alloc(dev);
13651 if (!state) {
13652 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13653 crtc->base.id);
13654 return;
13655 }
13656
13657 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13658
13659 retry:
13660 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13661 ret = PTR_ERR_OR_ZERO(crtc_state);
13662 if (!ret) {
13663 if (!crtc_state->active)
13664 goto out;
13665
13666 crtc_state->mode_changed = true;
13667 ret = drm_atomic_commit(state);
13668 }
13669
13670 if (ret == -EDEADLK) {
13671 drm_atomic_state_clear(state);
13672 drm_modeset_backoff(state->acquire_ctx);
13673 goto retry;
13674 }
13675
13676 if (ret)
13677 out:
13678 drm_atomic_state_free(state);
13679 }
13680
13681 #undef for_each_intel_crtc_masked
13682
13683 static const struct drm_crtc_funcs intel_crtc_funcs = {
13684 .gamma_set = drm_atomic_helper_legacy_gamma_set,
13685 .set_config = drm_atomic_helper_set_config,
13686 .set_property = drm_atomic_helper_crtc_set_property,
13687 .destroy = intel_crtc_destroy,
13688 .page_flip = intel_crtc_page_flip,
13689 .atomic_duplicate_state = intel_crtc_duplicate_state,
13690 .atomic_destroy_state = intel_crtc_destroy_state,
13691 };
13692
13693 static struct fence *intel_get_excl_fence(struct drm_i915_gem_object *obj)
13694 {
13695 struct reservation_object *resv;
13696
13697
13698 if (!obj->base.dma_buf)
13699 return NULL;
13700
13701 resv = obj->base.dma_buf->resv;
13702
13703 /* For framebuffer backed by dmabuf, wait for fence */
13704 while (1) {
13705 struct fence *fence_excl, *ret = NULL;
13706
13707 rcu_read_lock();
13708
13709 fence_excl = rcu_dereference(resv->fence_excl);
13710 if (fence_excl)
13711 ret = fence_get_rcu(fence_excl);
13712
13713 rcu_read_unlock();
13714
13715 if (ret == fence_excl)
13716 return ret;
13717 }
13718 }
13719
13720 /**
13721 * intel_prepare_plane_fb - Prepare fb for usage on plane
13722 * @plane: drm plane to prepare for
13723 * @fb: framebuffer to prepare for presentation
13724 *
13725 * Prepares a framebuffer for usage on a display plane. Generally this
13726 * involves pinning the underlying object and updating the frontbuffer tracking
13727 * bits. Some older platforms need special physical address handling for
13728 * cursor planes.
13729 *
13730 * Must be called with struct_mutex held.
13731 *
13732 * Returns 0 on success, negative error code on failure.
13733 */
13734 int
13735 intel_prepare_plane_fb(struct drm_plane *plane,
13736 const struct drm_plane_state *new_state)
13737 {
13738 struct drm_device *dev = plane->dev;
13739 struct drm_framebuffer *fb = new_state->fb;
13740 struct intel_plane *intel_plane = to_intel_plane(plane);
13741 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13742 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13743 int ret = 0;
13744
13745 if (!obj && !old_obj)
13746 return 0;
13747
13748 if (old_obj) {
13749 struct drm_crtc_state *crtc_state =
13750 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13751
13752 /* Big Hammer, we also need to ensure that any pending
13753 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13754 * current scanout is retired before unpinning the old
13755 * framebuffer. Note that we rely on userspace rendering
13756 * into the buffer attached to the pipe they are waiting
13757 * on. If not, userspace generates a GPU hang with IPEHR
13758 * point to the MI_WAIT_FOR_EVENT.
13759 *
13760 * This should only fail upon a hung GPU, in which case we
13761 * can safely continue.
13762 */
13763 if (needs_modeset(crtc_state))
13764 ret = i915_gem_object_wait_rendering(old_obj, true);
13765 if (ret) {
13766 /* GPU hangs should have been swallowed by the wait */
13767 WARN_ON(ret == -EIO);
13768 return ret;
13769 }
13770 }
13771
13772 if (!obj) {
13773 ret = 0;
13774 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13775 INTEL_INFO(dev)->cursor_needs_physical) {
13776 int align = IS_I830(dev) ? 16 * 1024 : 256;
13777 ret = i915_gem_object_attach_phys(obj, align);
13778 if (ret)
13779 DRM_DEBUG_KMS("failed to attach phys object\n");
13780 } else {
13781 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13782 }
13783
13784 if (ret == 0) {
13785 if (obj) {
13786 struct intel_plane_state *plane_state =
13787 to_intel_plane_state(new_state);
13788
13789 i915_gem_request_assign(&plane_state->wait_req,
13790 obj->last_write_req);
13791
13792 plane_state->base.fence = intel_get_excl_fence(obj);
13793 }
13794
13795 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13796 }
13797
13798 return ret;
13799 }
13800
13801 /**
13802 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13803 * @plane: drm plane to clean up for
13804 * @fb: old framebuffer that was on plane
13805 *
13806 * Cleans up a framebuffer that has just been removed from a plane.
13807 *
13808 * Must be called with struct_mutex held.
13809 */
13810 void
13811 intel_cleanup_plane_fb(struct drm_plane *plane,
13812 const struct drm_plane_state *old_state)
13813 {
13814 struct drm_device *dev = plane->dev;
13815 struct intel_plane *intel_plane = to_intel_plane(plane);
13816 struct intel_plane_state *old_intel_state;
13817 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13818 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13819
13820 old_intel_state = to_intel_plane_state(old_state);
13821
13822 if (!obj && !old_obj)
13823 return;
13824
13825 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13826 !INTEL_INFO(dev)->cursor_needs_physical))
13827 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
13828
13829 /* prepare_fb aborted? */
13830 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13831 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13832 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13833
13834 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13835
13836 fence_put(old_intel_state->base.fence);
13837 old_intel_state->base.fence = NULL;
13838 }
13839
13840 int
13841 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13842 {
13843 int max_scale;
13844 struct drm_device *dev;
13845 struct drm_i915_private *dev_priv;
13846 int crtc_clock, cdclk;
13847
13848 if (!intel_crtc || !crtc_state->base.enable)
13849 return DRM_PLANE_HELPER_NO_SCALING;
13850
13851 dev = intel_crtc->base.dev;
13852 dev_priv = dev->dev_private;
13853 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13854 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13855
13856 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13857 return DRM_PLANE_HELPER_NO_SCALING;
13858
13859 /*
13860 * skl max scale is lower of:
13861 * close to 3 but not 3, -1 is for that purpose
13862 * or
13863 * cdclk/crtc_clock
13864 */
13865 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13866
13867 return max_scale;
13868 }
13869
13870 static int
13871 intel_check_primary_plane(struct drm_plane *plane,
13872 struct intel_crtc_state *crtc_state,
13873 struct intel_plane_state *state)
13874 {
13875 struct drm_crtc *crtc = state->base.crtc;
13876 struct drm_framebuffer *fb = state->base.fb;
13877 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13878 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13879 bool can_position = false;
13880
13881 if (INTEL_INFO(plane->dev)->gen >= 9) {
13882 /* use scaler when colorkey is not required */
13883 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13884 min_scale = 1;
13885 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13886 }
13887 can_position = true;
13888 }
13889
13890 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13891 &state->dst, &state->clip,
13892 min_scale, max_scale,
13893 can_position, true,
13894 &state->visible);
13895 }
13896
13897 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13898 struct drm_crtc_state *old_crtc_state)
13899 {
13900 struct drm_device *dev = crtc->dev;
13901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13902 struct intel_crtc_state *old_intel_state =
13903 to_intel_crtc_state(old_crtc_state);
13904 bool modeset = needs_modeset(crtc->state);
13905
13906 /* Perform vblank evasion around commit operation */
13907 intel_pipe_update_start(intel_crtc);
13908
13909 if (modeset)
13910 return;
13911
13912 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
13913 intel_color_set_csc(crtc->state);
13914 intel_color_load_luts(crtc->state);
13915 }
13916
13917 if (to_intel_crtc_state(crtc->state)->update_pipe)
13918 intel_update_pipe_config(intel_crtc, old_intel_state);
13919 else if (INTEL_INFO(dev)->gen >= 9)
13920 skl_detach_scalers(intel_crtc);
13921 }
13922
13923 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13924 struct drm_crtc_state *old_crtc_state)
13925 {
13926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13927
13928 intel_pipe_update_end(intel_crtc, NULL);
13929 }
13930
13931 /**
13932 * intel_plane_destroy - destroy a plane
13933 * @plane: plane to destroy
13934 *
13935 * Common destruction function for all types of planes (primary, cursor,
13936 * sprite).
13937 */
13938 void intel_plane_destroy(struct drm_plane *plane)
13939 {
13940 struct intel_plane *intel_plane = to_intel_plane(plane);
13941 drm_plane_cleanup(plane);
13942 kfree(intel_plane);
13943 }
13944
13945 const struct drm_plane_funcs intel_plane_funcs = {
13946 .update_plane = drm_atomic_helper_update_plane,
13947 .disable_plane = drm_atomic_helper_disable_plane,
13948 .destroy = intel_plane_destroy,
13949 .set_property = drm_atomic_helper_plane_set_property,
13950 .atomic_get_property = intel_plane_atomic_get_property,
13951 .atomic_set_property = intel_plane_atomic_set_property,
13952 .atomic_duplicate_state = intel_plane_duplicate_state,
13953 .atomic_destroy_state = intel_plane_destroy_state,
13954
13955 };
13956
13957 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13958 int pipe)
13959 {
13960 struct intel_plane *primary = NULL;
13961 struct intel_plane_state *state = NULL;
13962 const uint32_t *intel_primary_formats;
13963 unsigned int num_formats;
13964 int ret;
13965
13966 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13967 if (!primary)
13968 goto fail;
13969
13970 state = intel_create_plane_state(&primary->base);
13971 if (!state)
13972 goto fail;
13973 primary->base.state = &state->base;
13974
13975 primary->can_scale = false;
13976 primary->max_downscale = 1;
13977 if (INTEL_INFO(dev)->gen >= 9) {
13978 primary->can_scale = true;
13979 state->scaler_id = -1;
13980 }
13981 primary->pipe = pipe;
13982 primary->plane = pipe;
13983 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13984 primary->check_plane = intel_check_primary_plane;
13985 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13986 primary->plane = !pipe;
13987
13988 if (INTEL_INFO(dev)->gen >= 9) {
13989 intel_primary_formats = skl_primary_formats;
13990 num_formats = ARRAY_SIZE(skl_primary_formats);
13991
13992 primary->update_plane = skylake_update_primary_plane;
13993 primary->disable_plane = skylake_disable_primary_plane;
13994 } else if (HAS_PCH_SPLIT(dev)) {
13995 intel_primary_formats = i965_primary_formats;
13996 num_formats = ARRAY_SIZE(i965_primary_formats);
13997
13998 primary->update_plane = ironlake_update_primary_plane;
13999 primary->disable_plane = i9xx_disable_primary_plane;
14000 } else if (INTEL_INFO(dev)->gen >= 4) {
14001 intel_primary_formats = i965_primary_formats;
14002 num_formats = ARRAY_SIZE(i965_primary_formats);
14003
14004 primary->update_plane = i9xx_update_primary_plane;
14005 primary->disable_plane = i9xx_disable_primary_plane;
14006 } else {
14007 intel_primary_formats = i8xx_primary_formats;
14008 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14009
14010 primary->update_plane = i9xx_update_primary_plane;
14011 primary->disable_plane = i9xx_disable_primary_plane;
14012 }
14013
14014 ret = drm_universal_plane_init(dev, &primary->base, 0,
14015 &intel_plane_funcs,
14016 intel_primary_formats, num_formats,
14017 DRM_PLANE_TYPE_PRIMARY, NULL);
14018 if (ret)
14019 goto fail;
14020
14021 if (INTEL_INFO(dev)->gen >= 4)
14022 intel_create_rotation_property(dev, primary);
14023
14024 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14025
14026 return &primary->base;
14027
14028 fail:
14029 kfree(state);
14030 kfree(primary);
14031
14032 return NULL;
14033 }
14034
14035 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14036 {
14037 if (!dev->mode_config.rotation_property) {
14038 unsigned long flags = BIT(DRM_ROTATE_0) |
14039 BIT(DRM_ROTATE_180);
14040
14041 if (INTEL_INFO(dev)->gen >= 9)
14042 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14043
14044 dev->mode_config.rotation_property =
14045 drm_mode_create_rotation_property(dev, flags);
14046 }
14047 if (dev->mode_config.rotation_property)
14048 drm_object_attach_property(&plane->base.base,
14049 dev->mode_config.rotation_property,
14050 plane->base.state->rotation);
14051 }
14052
14053 static int
14054 intel_check_cursor_plane(struct drm_plane *plane,
14055 struct intel_crtc_state *crtc_state,
14056 struct intel_plane_state *state)
14057 {
14058 struct drm_crtc *crtc = crtc_state->base.crtc;
14059 struct drm_framebuffer *fb = state->base.fb;
14060 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14061 enum pipe pipe = to_intel_plane(plane)->pipe;
14062 unsigned stride;
14063 int ret;
14064
14065 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14066 &state->dst, &state->clip,
14067 DRM_PLANE_HELPER_NO_SCALING,
14068 DRM_PLANE_HELPER_NO_SCALING,
14069 true, true, &state->visible);
14070 if (ret)
14071 return ret;
14072
14073 /* if we want to turn off the cursor ignore width and height */
14074 if (!obj)
14075 return 0;
14076
14077 /* Check for which cursor types we support */
14078 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14079 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14080 state->base.crtc_w, state->base.crtc_h);
14081 return -EINVAL;
14082 }
14083
14084 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14085 if (obj->base.size < stride * state->base.crtc_h) {
14086 DRM_DEBUG_KMS("buffer is too small\n");
14087 return -ENOMEM;
14088 }
14089
14090 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14091 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14092 return -EINVAL;
14093 }
14094
14095 /*
14096 * There's something wrong with the cursor on CHV pipe C.
14097 * If it straddles the left edge of the screen then
14098 * moving it away from the edge or disabling it often
14099 * results in a pipe underrun, and often that can lead to
14100 * dead pipe (constant underrun reported, and it scans
14101 * out just a solid color). To recover from that, the
14102 * display power well must be turned off and on again.
14103 * Refuse the put the cursor into that compromised position.
14104 */
14105 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14106 state->visible && state->base.crtc_x < 0) {
14107 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14108 return -EINVAL;
14109 }
14110
14111 return 0;
14112 }
14113
14114 static void
14115 intel_disable_cursor_plane(struct drm_plane *plane,
14116 struct drm_crtc *crtc)
14117 {
14118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14119
14120 intel_crtc->cursor_addr = 0;
14121 intel_crtc_update_cursor(crtc, NULL);
14122 }
14123
14124 static void
14125 intel_update_cursor_plane(struct drm_plane *plane,
14126 const struct intel_crtc_state *crtc_state,
14127 const struct intel_plane_state *state)
14128 {
14129 struct drm_crtc *crtc = crtc_state->base.crtc;
14130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14131 struct drm_device *dev = plane->dev;
14132 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14133 uint32_t addr;
14134
14135 if (!obj)
14136 addr = 0;
14137 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14138 addr = i915_gem_obj_ggtt_offset(obj);
14139 else
14140 addr = obj->phys_handle->busaddr;
14141
14142 intel_crtc->cursor_addr = addr;
14143 intel_crtc_update_cursor(crtc, state);
14144 }
14145
14146 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14147 int pipe)
14148 {
14149 struct intel_plane *cursor = NULL;
14150 struct intel_plane_state *state = NULL;
14151 int ret;
14152
14153 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14154 if (!cursor)
14155 goto fail;
14156
14157 state = intel_create_plane_state(&cursor->base);
14158 if (!state)
14159 goto fail;
14160 cursor->base.state = &state->base;
14161
14162 cursor->can_scale = false;
14163 cursor->max_downscale = 1;
14164 cursor->pipe = pipe;
14165 cursor->plane = pipe;
14166 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14167 cursor->check_plane = intel_check_cursor_plane;
14168 cursor->update_plane = intel_update_cursor_plane;
14169 cursor->disable_plane = intel_disable_cursor_plane;
14170
14171 ret = drm_universal_plane_init(dev, &cursor->base, 0,
14172 &intel_plane_funcs,
14173 intel_cursor_formats,
14174 ARRAY_SIZE(intel_cursor_formats),
14175 DRM_PLANE_TYPE_CURSOR, NULL);
14176 if (ret)
14177 goto fail;
14178
14179 if (INTEL_INFO(dev)->gen >= 4) {
14180 if (!dev->mode_config.rotation_property)
14181 dev->mode_config.rotation_property =
14182 drm_mode_create_rotation_property(dev,
14183 BIT(DRM_ROTATE_0) |
14184 BIT(DRM_ROTATE_180));
14185 if (dev->mode_config.rotation_property)
14186 drm_object_attach_property(&cursor->base.base,
14187 dev->mode_config.rotation_property,
14188 state->base.rotation);
14189 }
14190
14191 if (INTEL_INFO(dev)->gen >=9)
14192 state->scaler_id = -1;
14193
14194 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14195
14196 return &cursor->base;
14197
14198 fail:
14199 kfree(state);
14200 kfree(cursor);
14201
14202 return NULL;
14203 }
14204
14205 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14206 struct intel_crtc_state *crtc_state)
14207 {
14208 int i;
14209 struct intel_scaler *intel_scaler;
14210 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14211
14212 for (i = 0; i < intel_crtc->num_scalers; i++) {
14213 intel_scaler = &scaler_state->scalers[i];
14214 intel_scaler->in_use = 0;
14215 intel_scaler->mode = PS_SCALER_MODE_DYN;
14216 }
14217
14218 scaler_state->scaler_id = -1;
14219 }
14220
14221 static void intel_crtc_init(struct drm_device *dev, int pipe)
14222 {
14223 struct drm_i915_private *dev_priv = dev->dev_private;
14224 struct intel_crtc *intel_crtc;
14225 struct intel_crtc_state *crtc_state = NULL;
14226 struct drm_plane *primary = NULL;
14227 struct drm_plane *cursor = NULL;
14228 int ret;
14229
14230 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14231 if (intel_crtc == NULL)
14232 return;
14233
14234 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14235 if (!crtc_state)
14236 goto fail;
14237 intel_crtc->config = crtc_state;
14238 intel_crtc->base.state = &crtc_state->base;
14239 crtc_state->base.crtc = &intel_crtc->base;
14240
14241 INIT_LIST_HEAD(&intel_crtc->flip_work);
14242
14243 /* initialize shared scalers */
14244 if (INTEL_INFO(dev)->gen >= 9) {
14245 if (pipe == PIPE_C)
14246 intel_crtc->num_scalers = 1;
14247 else
14248 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14249
14250 skl_init_scalers(dev, intel_crtc, crtc_state);
14251 }
14252
14253 primary = intel_primary_plane_create(dev, pipe);
14254 if (!primary)
14255 goto fail;
14256
14257 cursor = intel_cursor_plane_create(dev, pipe);
14258 if (!cursor)
14259 goto fail;
14260
14261 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14262 cursor, &intel_crtc_funcs, NULL);
14263 if (ret)
14264 goto fail;
14265
14266 /*
14267 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14268 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14269 */
14270 intel_crtc->pipe = pipe;
14271 intel_crtc->plane = pipe;
14272 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14273 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14274 intel_crtc->plane = !pipe;
14275 }
14276
14277 intel_crtc->cursor_base = ~0;
14278 intel_crtc->cursor_cntl = ~0;
14279 intel_crtc->cursor_size = ~0;
14280
14281 intel_crtc->wm.cxsr_allowed = true;
14282
14283 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14284 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14285 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14286 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14287
14288 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14289
14290 intel_color_init(&intel_crtc->base);
14291
14292 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14293 return;
14294
14295 fail:
14296 if (primary)
14297 drm_plane_cleanup(primary);
14298 if (cursor)
14299 drm_plane_cleanup(cursor);
14300 kfree(crtc_state);
14301 kfree(intel_crtc);
14302 }
14303
14304 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14305 {
14306 struct drm_encoder *encoder = connector->base.encoder;
14307 struct drm_device *dev = connector->base.dev;
14308
14309 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14310
14311 if (!encoder || WARN_ON(!encoder->crtc))
14312 return INVALID_PIPE;
14313
14314 return to_intel_crtc(encoder->crtc)->pipe;
14315 }
14316
14317 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14318 struct drm_file *file)
14319 {
14320 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14321 struct drm_crtc *drmmode_crtc;
14322 struct intel_crtc *crtc;
14323
14324 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14325
14326 if (!drmmode_crtc) {
14327 DRM_ERROR("no such CRTC id\n");
14328 return -ENOENT;
14329 }
14330
14331 crtc = to_intel_crtc(drmmode_crtc);
14332 pipe_from_crtc_id->pipe = crtc->pipe;
14333
14334 return 0;
14335 }
14336
14337 static int intel_encoder_clones(struct intel_encoder *encoder)
14338 {
14339 struct drm_device *dev = encoder->base.dev;
14340 struct intel_encoder *source_encoder;
14341 int index_mask = 0;
14342 int entry = 0;
14343
14344 for_each_intel_encoder(dev, source_encoder) {
14345 if (encoders_cloneable(encoder, source_encoder))
14346 index_mask |= (1 << entry);
14347
14348 entry++;
14349 }
14350
14351 return index_mask;
14352 }
14353
14354 static bool has_edp_a(struct drm_device *dev)
14355 {
14356 struct drm_i915_private *dev_priv = dev->dev_private;
14357
14358 if (!IS_MOBILE(dev))
14359 return false;
14360
14361 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14362 return false;
14363
14364 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14365 return false;
14366
14367 return true;
14368 }
14369
14370 static bool intel_crt_present(struct drm_device *dev)
14371 {
14372 struct drm_i915_private *dev_priv = dev->dev_private;
14373
14374 if (INTEL_INFO(dev)->gen >= 9)
14375 return false;
14376
14377 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14378 return false;
14379
14380 if (IS_CHERRYVIEW(dev))
14381 return false;
14382
14383 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14384 return false;
14385
14386 /* DDI E can't be used if DDI A requires 4 lanes */
14387 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14388 return false;
14389
14390 if (!dev_priv->vbt.int_crt_support)
14391 return false;
14392
14393 return true;
14394 }
14395
14396 static void intel_setup_outputs(struct drm_device *dev)
14397 {
14398 struct drm_i915_private *dev_priv = dev->dev_private;
14399 struct intel_encoder *encoder;
14400 bool dpd_is_edp = false;
14401
14402 intel_lvds_init(dev);
14403
14404 if (intel_crt_present(dev))
14405 intel_crt_init(dev);
14406
14407 if (IS_BROXTON(dev)) {
14408 /*
14409 * FIXME: Broxton doesn't support port detection via the
14410 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14411 * detect the ports.
14412 */
14413 intel_ddi_init(dev, PORT_A);
14414 intel_ddi_init(dev, PORT_B);
14415 intel_ddi_init(dev, PORT_C);
14416
14417 intel_dsi_init(dev);
14418 } else if (HAS_DDI(dev)) {
14419 int found;
14420
14421 /*
14422 * Haswell uses DDI functions to detect digital outputs.
14423 * On SKL pre-D0 the strap isn't connected, so we assume
14424 * it's there.
14425 */
14426 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14427 /* WaIgnoreDDIAStrap: skl */
14428 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14429 intel_ddi_init(dev, PORT_A);
14430
14431 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14432 * register */
14433 found = I915_READ(SFUSE_STRAP);
14434
14435 if (found & SFUSE_STRAP_DDIB_DETECTED)
14436 intel_ddi_init(dev, PORT_B);
14437 if (found & SFUSE_STRAP_DDIC_DETECTED)
14438 intel_ddi_init(dev, PORT_C);
14439 if (found & SFUSE_STRAP_DDID_DETECTED)
14440 intel_ddi_init(dev, PORT_D);
14441 /*
14442 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14443 */
14444 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14445 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14446 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14447 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14448 intel_ddi_init(dev, PORT_E);
14449
14450 } else if (HAS_PCH_SPLIT(dev)) {
14451 int found;
14452 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14453
14454 if (has_edp_a(dev))
14455 intel_dp_init(dev, DP_A, PORT_A);
14456
14457 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14458 /* PCH SDVOB multiplex with HDMIB */
14459 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14460 if (!found)
14461 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14462 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14463 intel_dp_init(dev, PCH_DP_B, PORT_B);
14464 }
14465
14466 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14467 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14468
14469 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14470 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14471
14472 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14473 intel_dp_init(dev, PCH_DP_C, PORT_C);
14474
14475 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14476 intel_dp_init(dev, PCH_DP_D, PORT_D);
14477 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14478 /*
14479 * The DP_DETECTED bit is the latched state of the DDC
14480 * SDA pin at boot. However since eDP doesn't require DDC
14481 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14482 * eDP ports may have been muxed to an alternate function.
14483 * Thus we can't rely on the DP_DETECTED bit alone to detect
14484 * eDP ports. Consult the VBT as well as DP_DETECTED to
14485 * detect eDP ports.
14486 */
14487 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14488 !intel_dp_is_edp(dev, PORT_B))
14489 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14490 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14491 intel_dp_is_edp(dev, PORT_B))
14492 intel_dp_init(dev, VLV_DP_B, PORT_B);
14493
14494 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14495 !intel_dp_is_edp(dev, PORT_C))
14496 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14497 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14498 intel_dp_is_edp(dev, PORT_C))
14499 intel_dp_init(dev, VLV_DP_C, PORT_C);
14500
14501 if (IS_CHERRYVIEW(dev)) {
14502 /* eDP not supported on port D, so don't check VBT */
14503 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14504 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14505 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14506 intel_dp_init(dev, CHV_DP_D, PORT_D);
14507 }
14508
14509 intel_dsi_init(dev);
14510 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14511 bool found = false;
14512
14513 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14514 DRM_DEBUG_KMS("probing SDVOB\n");
14515 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14516 if (!found && IS_G4X(dev)) {
14517 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14518 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14519 }
14520
14521 if (!found && IS_G4X(dev))
14522 intel_dp_init(dev, DP_B, PORT_B);
14523 }
14524
14525 /* Before G4X SDVOC doesn't have its own detect register */
14526
14527 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14528 DRM_DEBUG_KMS("probing SDVOC\n");
14529 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14530 }
14531
14532 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14533
14534 if (IS_G4X(dev)) {
14535 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14536 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14537 }
14538 if (IS_G4X(dev))
14539 intel_dp_init(dev, DP_C, PORT_C);
14540 }
14541
14542 if (IS_G4X(dev) &&
14543 (I915_READ(DP_D) & DP_DETECTED))
14544 intel_dp_init(dev, DP_D, PORT_D);
14545 } else if (IS_GEN2(dev))
14546 intel_dvo_init(dev);
14547
14548 if (SUPPORTS_TV(dev))
14549 intel_tv_init(dev);
14550
14551 intel_psr_init(dev);
14552
14553 for_each_intel_encoder(dev, encoder) {
14554 encoder->base.possible_crtcs = encoder->crtc_mask;
14555 encoder->base.possible_clones =
14556 intel_encoder_clones(encoder);
14557 }
14558
14559 intel_init_pch_refclk(dev);
14560
14561 drm_helper_move_panel_connectors_to_head(dev);
14562 }
14563
14564 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14565 {
14566 struct drm_device *dev = fb->dev;
14567 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14568
14569 drm_framebuffer_cleanup(fb);
14570 mutex_lock(&dev->struct_mutex);
14571 WARN_ON(!intel_fb->obj->framebuffer_references--);
14572 drm_gem_object_unreference(&intel_fb->obj->base);
14573 mutex_unlock(&dev->struct_mutex);
14574 kfree(intel_fb);
14575 }
14576
14577 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14578 struct drm_file *file,
14579 unsigned int *handle)
14580 {
14581 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14582 struct drm_i915_gem_object *obj = intel_fb->obj;
14583
14584 if (obj->userptr.mm) {
14585 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14586 return -EINVAL;
14587 }
14588
14589 return drm_gem_handle_create(file, &obj->base, handle);
14590 }
14591
14592 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14593 struct drm_file *file,
14594 unsigned flags, unsigned color,
14595 struct drm_clip_rect *clips,
14596 unsigned num_clips)
14597 {
14598 struct drm_device *dev = fb->dev;
14599 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14600 struct drm_i915_gem_object *obj = intel_fb->obj;
14601
14602 mutex_lock(&dev->struct_mutex);
14603 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14604 mutex_unlock(&dev->struct_mutex);
14605
14606 return 0;
14607 }
14608
14609 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14610 .destroy = intel_user_framebuffer_destroy,
14611 .create_handle = intel_user_framebuffer_create_handle,
14612 .dirty = intel_user_framebuffer_dirty,
14613 };
14614
14615 static
14616 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14617 uint32_t pixel_format)
14618 {
14619 u32 gen = INTEL_INFO(dev)->gen;
14620
14621 if (gen >= 9) {
14622 int cpp = drm_format_plane_cpp(pixel_format, 0);
14623
14624 /* "The stride in bytes must not exceed the of the size of 8K
14625 * pixels and 32K bytes."
14626 */
14627 return min(8192 * cpp, 32768);
14628 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14629 return 32*1024;
14630 } else if (gen >= 4) {
14631 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14632 return 16*1024;
14633 else
14634 return 32*1024;
14635 } else if (gen >= 3) {
14636 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14637 return 8*1024;
14638 else
14639 return 16*1024;
14640 } else {
14641 /* XXX DSPC is limited to 4k tiled */
14642 return 8*1024;
14643 }
14644 }
14645
14646 static int intel_framebuffer_init(struct drm_device *dev,
14647 struct intel_framebuffer *intel_fb,
14648 struct drm_mode_fb_cmd2 *mode_cmd,
14649 struct drm_i915_gem_object *obj)
14650 {
14651 struct drm_i915_private *dev_priv = to_i915(dev);
14652 unsigned int aligned_height;
14653 int ret;
14654 u32 pitch_limit, stride_alignment;
14655
14656 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14657
14658 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14659 /* Enforce that fb modifier and tiling mode match, but only for
14660 * X-tiled. This is needed for FBC. */
14661 if (!!(obj->tiling_mode == I915_TILING_X) !=
14662 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14663 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14664 return -EINVAL;
14665 }
14666 } else {
14667 if (obj->tiling_mode == I915_TILING_X)
14668 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14669 else if (obj->tiling_mode == I915_TILING_Y) {
14670 DRM_DEBUG("No Y tiling for legacy addfb\n");
14671 return -EINVAL;
14672 }
14673 }
14674
14675 /* Passed in modifier sanity checking. */
14676 switch (mode_cmd->modifier[0]) {
14677 case I915_FORMAT_MOD_Y_TILED:
14678 case I915_FORMAT_MOD_Yf_TILED:
14679 if (INTEL_INFO(dev)->gen < 9) {
14680 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14681 mode_cmd->modifier[0]);
14682 return -EINVAL;
14683 }
14684 case DRM_FORMAT_MOD_NONE:
14685 case I915_FORMAT_MOD_X_TILED:
14686 break;
14687 default:
14688 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14689 mode_cmd->modifier[0]);
14690 return -EINVAL;
14691 }
14692
14693 stride_alignment = intel_fb_stride_alignment(dev_priv,
14694 mode_cmd->modifier[0],
14695 mode_cmd->pixel_format);
14696 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14697 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14698 mode_cmd->pitches[0], stride_alignment);
14699 return -EINVAL;
14700 }
14701
14702 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14703 mode_cmd->pixel_format);
14704 if (mode_cmd->pitches[0] > pitch_limit) {
14705 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14706 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14707 "tiled" : "linear",
14708 mode_cmd->pitches[0], pitch_limit);
14709 return -EINVAL;
14710 }
14711
14712 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14713 mode_cmd->pitches[0] != obj->stride) {
14714 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14715 mode_cmd->pitches[0], obj->stride);
14716 return -EINVAL;
14717 }
14718
14719 /* Reject formats not supported by any plane early. */
14720 switch (mode_cmd->pixel_format) {
14721 case DRM_FORMAT_C8:
14722 case DRM_FORMAT_RGB565:
14723 case DRM_FORMAT_XRGB8888:
14724 case DRM_FORMAT_ARGB8888:
14725 break;
14726 case DRM_FORMAT_XRGB1555:
14727 if (INTEL_INFO(dev)->gen > 3) {
14728 DRM_DEBUG("unsupported pixel format: %s\n",
14729 drm_get_format_name(mode_cmd->pixel_format));
14730 return -EINVAL;
14731 }
14732 break;
14733 case DRM_FORMAT_ABGR8888:
14734 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14735 INTEL_INFO(dev)->gen < 9) {
14736 DRM_DEBUG("unsupported pixel format: %s\n",
14737 drm_get_format_name(mode_cmd->pixel_format));
14738 return -EINVAL;
14739 }
14740 break;
14741 case DRM_FORMAT_XBGR8888:
14742 case DRM_FORMAT_XRGB2101010:
14743 case DRM_FORMAT_XBGR2101010:
14744 if (INTEL_INFO(dev)->gen < 4) {
14745 DRM_DEBUG("unsupported pixel format: %s\n",
14746 drm_get_format_name(mode_cmd->pixel_format));
14747 return -EINVAL;
14748 }
14749 break;
14750 case DRM_FORMAT_ABGR2101010:
14751 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14752 DRM_DEBUG("unsupported pixel format: %s\n",
14753 drm_get_format_name(mode_cmd->pixel_format));
14754 return -EINVAL;
14755 }
14756 break;
14757 case DRM_FORMAT_YUYV:
14758 case DRM_FORMAT_UYVY:
14759 case DRM_FORMAT_YVYU:
14760 case DRM_FORMAT_VYUY:
14761 if (INTEL_INFO(dev)->gen < 5) {
14762 DRM_DEBUG("unsupported pixel format: %s\n",
14763 drm_get_format_name(mode_cmd->pixel_format));
14764 return -EINVAL;
14765 }
14766 break;
14767 default:
14768 DRM_DEBUG("unsupported pixel format: %s\n",
14769 drm_get_format_name(mode_cmd->pixel_format));
14770 return -EINVAL;
14771 }
14772
14773 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14774 if (mode_cmd->offsets[0] != 0)
14775 return -EINVAL;
14776
14777 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14778 mode_cmd->pixel_format,
14779 mode_cmd->modifier[0]);
14780 /* FIXME drm helper for size checks (especially planar formats)? */
14781 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14782 return -EINVAL;
14783
14784 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14785 intel_fb->obj = obj;
14786
14787 intel_fill_fb_info(dev_priv, &intel_fb->base);
14788
14789 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14790 if (ret) {
14791 DRM_ERROR("framebuffer init failed %d\n", ret);
14792 return ret;
14793 }
14794
14795 intel_fb->obj->framebuffer_references++;
14796
14797 return 0;
14798 }
14799
14800 static struct drm_framebuffer *
14801 intel_user_framebuffer_create(struct drm_device *dev,
14802 struct drm_file *filp,
14803 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14804 {
14805 struct drm_framebuffer *fb;
14806 struct drm_i915_gem_object *obj;
14807 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14808
14809 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14810 mode_cmd.handles[0]));
14811 if (&obj->base == NULL)
14812 return ERR_PTR(-ENOENT);
14813
14814 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14815 if (IS_ERR(fb))
14816 drm_gem_object_unreference_unlocked(&obj->base);
14817
14818 return fb;
14819 }
14820
14821 #ifndef CONFIG_DRM_FBDEV_EMULATION
14822 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14823 {
14824 }
14825 #endif
14826
14827 static const struct drm_mode_config_funcs intel_mode_funcs = {
14828 .fb_create = intel_user_framebuffer_create,
14829 .output_poll_changed = intel_fbdev_output_poll_changed,
14830 .atomic_check = intel_atomic_check,
14831 .atomic_commit = intel_atomic_commit,
14832 .atomic_state_alloc = intel_atomic_state_alloc,
14833 .atomic_state_clear = intel_atomic_state_clear,
14834 };
14835
14836 /**
14837 * intel_init_display_hooks - initialize the display modesetting hooks
14838 * @dev_priv: device private
14839 */
14840 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14841 {
14842 if (INTEL_INFO(dev_priv)->gen >= 9) {
14843 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14844 dev_priv->display.get_initial_plane_config =
14845 skylake_get_initial_plane_config;
14846 dev_priv->display.crtc_compute_clock =
14847 haswell_crtc_compute_clock;
14848 dev_priv->display.crtc_enable = haswell_crtc_enable;
14849 dev_priv->display.crtc_disable = haswell_crtc_disable;
14850 } else if (HAS_DDI(dev_priv)) {
14851 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14852 dev_priv->display.get_initial_plane_config =
14853 ironlake_get_initial_plane_config;
14854 dev_priv->display.crtc_compute_clock =
14855 haswell_crtc_compute_clock;
14856 dev_priv->display.crtc_enable = haswell_crtc_enable;
14857 dev_priv->display.crtc_disable = haswell_crtc_disable;
14858 } else if (HAS_PCH_SPLIT(dev_priv)) {
14859 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14860 dev_priv->display.get_initial_plane_config =
14861 ironlake_get_initial_plane_config;
14862 dev_priv->display.crtc_compute_clock =
14863 ironlake_crtc_compute_clock;
14864 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14865 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14866 } else if (IS_CHERRYVIEW(dev_priv)) {
14867 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14868 dev_priv->display.get_initial_plane_config =
14869 i9xx_get_initial_plane_config;
14870 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14871 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14872 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14873 } else if (IS_VALLEYVIEW(dev_priv)) {
14874 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14875 dev_priv->display.get_initial_plane_config =
14876 i9xx_get_initial_plane_config;
14877 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14878 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14879 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14880 } else if (IS_G4X(dev_priv)) {
14881 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14882 dev_priv->display.get_initial_plane_config =
14883 i9xx_get_initial_plane_config;
14884 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14885 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14886 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14887 } else if (IS_PINEVIEW(dev_priv)) {
14888 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14889 dev_priv->display.get_initial_plane_config =
14890 i9xx_get_initial_plane_config;
14891 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14892 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14893 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14894 } else if (!IS_GEN2(dev_priv)) {
14895 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14896 dev_priv->display.get_initial_plane_config =
14897 i9xx_get_initial_plane_config;
14898 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14899 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14900 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14901 } else {
14902 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14903 dev_priv->display.get_initial_plane_config =
14904 i9xx_get_initial_plane_config;
14905 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14906 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14907 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14908 }
14909
14910 /* Returns the core display clock speed */
14911 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
14912 dev_priv->display.get_display_clock_speed =
14913 skylake_get_display_clock_speed;
14914 else if (IS_BROXTON(dev_priv))
14915 dev_priv->display.get_display_clock_speed =
14916 broxton_get_display_clock_speed;
14917 else if (IS_BROADWELL(dev_priv))
14918 dev_priv->display.get_display_clock_speed =
14919 broadwell_get_display_clock_speed;
14920 else if (IS_HASWELL(dev_priv))
14921 dev_priv->display.get_display_clock_speed =
14922 haswell_get_display_clock_speed;
14923 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14924 dev_priv->display.get_display_clock_speed =
14925 valleyview_get_display_clock_speed;
14926 else if (IS_GEN5(dev_priv))
14927 dev_priv->display.get_display_clock_speed =
14928 ilk_get_display_clock_speed;
14929 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
14930 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
14931 dev_priv->display.get_display_clock_speed =
14932 i945_get_display_clock_speed;
14933 else if (IS_GM45(dev_priv))
14934 dev_priv->display.get_display_clock_speed =
14935 gm45_get_display_clock_speed;
14936 else if (IS_CRESTLINE(dev_priv))
14937 dev_priv->display.get_display_clock_speed =
14938 i965gm_get_display_clock_speed;
14939 else if (IS_PINEVIEW(dev_priv))
14940 dev_priv->display.get_display_clock_speed =
14941 pnv_get_display_clock_speed;
14942 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
14943 dev_priv->display.get_display_clock_speed =
14944 g33_get_display_clock_speed;
14945 else if (IS_I915G(dev_priv))
14946 dev_priv->display.get_display_clock_speed =
14947 i915_get_display_clock_speed;
14948 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
14949 dev_priv->display.get_display_clock_speed =
14950 i9xx_misc_get_display_clock_speed;
14951 else if (IS_I915GM(dev_priv))
14952 dev_priv->display.get_display_clock_speed =
14953 i915gm_get_display_clock_speed;
14954 else if (IS_I865G(dev_priv))
14955 dev_priv->display.get_display_clock_speed =
14956 i865_get_display_clock_speed;
14957 else if (IS_I85X(dev_priv))
14958 dev_priv->display.get_display_clock_speed =
14959 i85x_get_display_clock_speed;
14960 else { /* 830 */
14961 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
14962 dev_priv->display.get_display_clock_speed =
14963 i830_get_display_clock_speed;
14964 }
14965
14966 if (IS_GEN5(dev_priv)) {
14967 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14968 } else if (IS_GEN6(dev_priv)) {
14969 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14970 } else if (IS_IVYBRIDGE(dev_priv)) {
14971 /* FIXME: detect B0+ stepping and use auto training */
14972 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14973 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14974 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14975 }
14976
14977 if (IS_BROADWELL(dev_priv)) {
14978 dev_priv->display.modeset_commit_cdclk =
14979 broadwell_modeset_commit_cdclk;
14980 dev_priv->display.modeset_calc_cdclk =
14981 broadwell_modeset_calc_cdclk;
14982 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14983 dev_priv->display.modeset_commit_cdclk =
14984 valleyview_modeset_commit_cdclk;
14985 dev_priv->display.modeset_calc_cdclk =
14986 valleyview_modeset_calc_cdclk;
14987 } else if (IS_BROXTON(dev_priv)) {
14988 dev_priv->display.modeset_commit_cdclk =
14989 broxton_modeset_commit_cdclk;
14990 dev_priv->display.modeset_calc_cdclk =
14991 broxton_modeset_calc_cdclk;
14992 }
14993
14994 switch (INTEL_INFO(dev_priv)->gen) {
14995 case 2:
14996 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14997 break;
14998
14999 case 3:
15000 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15001 break;
15002
15003 case 4:
15004 case 5:
15005 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15006 break;
15007
15008 case 6:
15009 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15010 break;
15011 case 7:
15012 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15013 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15014 break;
15015 case 9:
15016 /* Drop through - unsupported since execlist only. */
15017 default:
15018 /* Default just returns -ENODEV to indicate unsupported */
15019 dev_priv->display.queue_flip = intel_default_queue_flip;
15020 }
15021 }
15022
15023 /*
15024 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15025 * resume, or other times. This quirk makes sure that's the case for
15026 * affected systems.
15027 */
15028 static void quirk_pipea_force(struct drm_device *dev)
15029 {
15030 struct drm_i915_private *dev_priv = dev->dev_private;
15031
15032 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15033 DRM_INFO("applying pipe a force quirk\n");
15034 }
15035
15036 static void quirk_pipeb_force(struct drm_device *dev)
15037 {
15038 struct drm_i915_private *dev_priv = dev->dev_private;
15039
15040 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15041 DRM_INFO("applying pipe b force quirk\n");
15042 }
15043
15044 /*
15045 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15046 */
15047 static void quirk_ssc_force_disable(struct drm_device *dev)
15048 {
15049 struct drm_i915_private *dev_priv = dev->dev_private;
15050 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15051 DRM_INFO("applying lvds SSC disable quirk\n");
15052 }
15053
15054 /*
15055 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15056 * brightness value
15057 */
15058 static void quirk_invert_brightness(struct drm_device *dev)
15059 {
15060 struct drm_i915_private *dev_priv = dev->dev_private;
15061 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15062 DRM_INFO("applying inverted panel brightness quirk\n");
15063 }
15064
15065 /* Some VBT's incorrectly indicate no backlight is present */
15066 static void quirk_backlight_present(struct drm_device *dev)
15067 {
15068 struct drm_i915_private *dev_priv = dev->dev_private;
15069 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15070 DRM_INFO("applying backlight present quirk\n");
15071 }
15072
15073 struct intel_quirk {
15074 int device;
15075 int subsystem_vendor;
15076 int subsystem_device;
15077 void (*hook)(struct drm_device *dev);
15078 };
15079
15080 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15081 struct intel_dmi_quirk {
15082 void (*hook)(struct drm_device *dev);
15083 const struct dmi_system_id (*dmi_id_list)[];
15084 };
15085
15086 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15087 {
15088 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15089 return 1;
15090 }
15091
15092 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15093 {
15094 .dmi_id_list = &(const struct dmi_system_id[]) {
15095 {
15096 .callback = intel_dmi_reverse_brightness,
15097 .ident = "NCR Corporation",
15098 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15099 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15100 },
15101 },
15102 { } /* terminating entry */
15103 },
15104 .hook = quirk_invert_brightness,
15105 },
15106 };
15107
15108 static struct intel_quirk intel_quirks[] = {
15109 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15110 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15111
15112 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15113 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15114
15115 /* 830 needs to leave pipe A & dpll A up */
15116 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15117
15118 /* 830 needs to leave pipe B & dpll B up */
15119 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15120
15121 /* Lenovo U160 cannot use SSC on LVDS */
15122 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15123
15124 /* Sony Vaio Y cannot use SSC on LVDS */
15125 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15126
15127 /* Acer Aspire 5734Z must invert backlight brightness */
15128 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15129
15130 /* Acer/eMachines G725 */
15131 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15132
15133 /* Acer/eMachines e725 */
15134 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15135
15136 /* Acer/Packard Bell NCL20 */
15137 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15138
15139 /* Acer Aspire 4736Z */
15140 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15141
15142 /* Acer Aspire 5336 */
15143 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15144
15145 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15146 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15147
15148 /* Acer C720 Chromebook (Core i3 4005U) */
15149 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15150
15151 /* Apple Macbook 2,1 (Core 2 T7400) */
15152 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15153
15154 /* Apple Macbook 4,1 */
15155 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15156
15157 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15158 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15159
15160 /* HP Chromebook 14 (Celeron 2955U) */
15161 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15162
15163 /* Dell Chromebook 11 */
15164 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15165
15166 /* Dell Chromebook 11 (2015 version) */
15167 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15168 };
15169
15170 static void intel_init_quirks(struct drm_device *dev)
15171 {
15172 struct pci_dev *d = dev->pdev;
15173 int i;
15174
15175 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15176 struct intel_quirk *q = &intel_quirks[i];
15177
15178 if (d->device == q->device &&
15179 (d->subsystem_vendor == q->subsystem_vendor ||
15180 q->subsystem_vendor == PCI_ANY_ID) &&
15181 (d->subsystem_device == q->subsystem_device ||
15182 q->subsystem_device == PCI_ANY_ID))
15183 q->hook(dev);
15184 }
15185 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15186 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15187 intel_dmi_quirks[i].hook(dev);
15188 }
15189 }
15190
15191 /* Disable the VGA plane that we never use */
15192 static void i915_disable_vga(struct drm_device *dev)
15193 {
15194 struct drm_i915_private *dev_priv = dev->dev_private;
15195 u8 sr1;
15196 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15197
15198 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15199 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15200 outb(SR01, VGA_SR_INDEX);
15201 sr1 = inb(VGA_SR_DATA);
15202 outb(sr1 | 1<<5, VGA_SR_DATA);
15203 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15204 udelay(300);
15205
15206 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15207 POSTING_READ(vga_reg);
15208 }
15209
15210 void intel_modeset_init_hw(struct drm_device *dev)
15211 {
15212 struct drm_i915_private *dev_priv = dev->dev_private;
15213
15214 intel_update_cdclk(dev);
15215
15216 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15217
15218 intel_init_clock_gating(dev);
15219 intel_enable_gt_powersave(dev_priv);
15220 }
15221
15222 /*
15223 * Calculate what we think the watermarks should be for the state we've read
15224 * out of the hardware and then immediately program those watermarks so that
15225 * we ensure the hardware settings match our internal state.
15226 *
15227 * We can calculate what we think WM's should be by creating a duplicate of the
15228 * current state (which was constructed during hardware readout) and running it
15229 * through the atomic check code to calculate new watermark values in the
15230 * state object.
15231 */
15232 static void sanitize_watermarks(struct drm_device *dev)
15233 {
15234 struct drm_i915_private *dev_priv = to_i915(dev);
15235 struct drm_atomic_state *state;
15236 struct drm_crtc *crtc;
15237 struct drm_crtc_state *cstate;
15238 struct drm_modeset_acquire_ctx ctx;
15239 int ret;
15240 int i;
15241
15242 /* Only supported on platforms that use atomic watermark design */
15243 if (!dev_priv->display.optimize_watermarks)
15244 return;
15245
15246 /*
15247 * We need to hold connection_mutex before calling duplicate_state so
15248 * that the connector loop is protected.
15249 */
15250 drm_modeset_acquire_init(&ctx, 0);
15251 retry:
15252 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15253 if (ret == -EDEADLK) {
15254 drm_modeset_backoff(&ctx);
15255 goto retry;
15256 } else if (WARN_ON(ret)) {
15257 goto fail;
15258 }
15259
15260 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15261 if (WARN_ON(IS_ERR(state)))
15262 goto fail;
15263
15264 /*
15265 * Hardware readout is the only time we don't want to calculate
15266 * intermediate watermarks (since we don't trust the current
15267 * watermarks).
15268 */
15269 to_intel_atomic_state(state)->skip_intermediate_wm = true;
15270
15271 ret = intel_atomic_check(dev, state);
15272 if (ret) {
15273 /*
15274 * If we fail here, it means that the hardware appears to be
15275 * programmed in a way that shouldn't be possible, given our
15276 * understanding of watermark requirements. This might mean a
15277 * mistake in the hardware readout code or a mistake in the
15278 * watermark calculations for a given platform. Raise a WARN
15279 * so that this is noticeable.
15280 *
15281 * If this actually happens, we'll have to just leave the
15282 * BIOS-programmed watermarks untouched and hope for the best.
15283 */
15284 WARN(true, "Could not determine valid watermarks for inherited state\n");
15285 goto fail;
15286 }
15287
15288 /* Write calculated watermark values back */
15289 for_each_crtc_in_state(state, crtc, cstate, i) {
15290 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15291
15292 cs->wm.need_postvbl_update = true;
15293 dev_priv->display.optimize_watermarks(cs);
15294 }
15295
15296 drm_atomic_state_free(state);
15297 fail:
15298 drm_modeset_drop_locks(&ctx);
15299 drm_modeset_acquire_fini(&ctx);
15300 }
15301
15302 void intel_modeset_init(struct drm_device *dev)
15303 {
15304 struct drm_i915_private *dev_priv = to_i915(dev);
15305 struct i915_ggtt *ggtt = &dev_priv->ggtt;
15306 int sprite, ret;
15307 enum pipe pipe;
15308 struct intel_crtc *crtc;
15309
15310 drm_mode_config_init(dev);
15311
15312 dev->mode_config.min_width = 0;
15313 dev->mode_config.min_height = 0;
15314
15315 dev->mode_config.preferred_depth = 24;
15316 dev->mode_config.prefer_shadow = 1;
15317
15318 dev->mode_config.allow_fb_modifiers = true;
15319
15320 dev->mode_config.funcs = &intel_mode_funcs;
15321
15322 intel_init_quirks(dev);
15323
15324 intel_init_pm(dev);
15325
15326 if (INTEL_INFO(dev)->num_pipes == 0)
15327 return;
15328
15329 /*
15330 * There may be no VBT; and if the BIOS enabled SSC we can
15331 * just keep using it to avoid unnecessary flicker. Whereas if the
15332 * BIOS isn't using it, don't assume it will work even if the VBT
15333 * indicates as much.
15334 */
15335 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15336 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15337 DREF_SSC1_ENABLE);
15338
15339 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15340 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15341 bios_lvds_use_ssc ? "en" : "dis",
15342 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15343 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15344 }
15345 }
15346
15347 if (IS_GEN2(dev)) {
15348 dev->mode_config.max_width = 2048;
15349 dev->mode_config.max_height = 2048;
15350 } else if (IS_GEN3(dev)) {
15351 dev->mode_config.max_width = 4096;
15352 dev->mode_config.max_height = 4096;
15353 } else {
15354 dev->mode_config.max_width = 8192;
15355 dev->mode_config.max_height = 8192;
15356 }
15357
15358 if (IS_845G(dev) || IS_I865G(dev)) {
15359 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15360 dev->mode_config.cursor_height = 1023;
15361 } else if (IS_GEN2(dev)) {
15362 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15363 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15364 } else {
15365 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15366 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15367 }
15368
15369 dev->mode_config.fb_base = ggtt->mappable_base;
15370
15371 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15372 INTEL_INFO(dev)->num_pipes,
15373 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15374
15375 for_each_pipe(dev_priv, pipe) {
15376 intel_crtc_init(dev, pipe);
15377 for_each_sprite(dev_priv, pipe, sprite) {
15378 ret = intel_plane_init(dev, pipe, sprite);
15379 if (ret)
15380 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15381 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15382 }
15383 }
15384
15385 intel_update_czclk(dev_priv);
15386 intel_update_cdclk(dev);
15387
15388 intel_shared_dpll_init(dev);
15389
15390 /* Just disable it once at startup */
15391 i915_disable_vga(dev);
15392 intel_setup_outputs(dev);
15393
15394 drm_modeset_lock_all(dev);
15395 intel_modeset_setup_hw_state(dev);
15396 drm_modeset_unlock_all(dev);
15397
15398 for_each_intel_crtc(dev, crtc) {
15399 struct intel_initial_plane_config plane_config = {};
15400
15401 if (!crtc->active)
15402 continue;
15403
15404 /*
15405 * Note that reserving the BIOS fb up front prevents us
15406 * from stuffing other stolen allocations like the ring
15407 * on top. This prevents some ugliness at boot time, and
15408 * can even allow for smooth boot transitions if the BIOS
15409 * fb is large enough for the active pipe configuration.
15410 */
15411 dev_priv->display.get_initial_plane_config(crtc,
15412 &plane_config);
15413
15414 /*
15415 * If the fb is shared between multiple heads, we'll
15416 * just get the first one.
15417 */
15418 intel_find_initial_plane_obj(crtc, &plane_config);
15419 }
15420
15421 /*
15422 * Make sure hardware watermarks really match the state we read out.
15423 * Note that we need to do this after reconstructing the BIOS fb's
15424 * since the watermark calculation done here will use pstate->fb.
15425 */
15426 sanitize_watermarks(dev);
15427 }
15428
15429 static void intel_enable_pipe_a(struct drm_device *dev)
15430 {
15431 struct intel_connector *connector;
15432 struct drm_connector *crt = NULL;
15433 struct intel_load_detect_pipe load_detect_temp;
15434 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15435
15436 /* We can't just switch on the pipe A, we need to set things up with a
15437 * proper mode and output configuration. As a gross hack, enable pipe A
15438 * by enabling the load detect pipe once. */
15439 for_each_intel_connector(dev, connector) {
15440 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15441 crt = &connector->base;
15442 break;
15443 }
15444 }
15445
15446 if (!crt)
15447 return;
15448
15449 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15450 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15451 }
15452
15453 static bool
15454 intel_check_plane_mapping(struct intel_crtc *crtc)
15455 {
15456 struct drm_device *dev = crtc->base.dev;
15457 struct drm_i915_private *dev_priv = dev->dev_private;
15458 u32 val;
15459
15460 if (INTEL_INFO(dev)->num_pipes == 1)
15461 return true;
15462
15463 val = I915_READ(DSPCNTR(!crtc->plane));
15464
15465 if ((val & DISPLAY_PLANE_ENABLE) &&
15466 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15467 return false;
15468
15469 return true;
15470 }
15471
15472 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15473 {
15474 struct drm_device *dev = crtc->base.dev;
15475 struct intel_encoder *encoder;
15476
15477 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15478 return true;
15479
15480 return false;
15481 }
15482
15483 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15484 {
15485 struct drm_device *dev = encoder->base.dev;
15486 struct intel_connector *connector;
15487
15488 for_each_connector_on_encoder(dev, &encoder->base, connector)
15489 return true;
15490
15491 return false;
15492 }
15493
15494 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15495 {
15496 struct drm_device *dev = crtc->base.dev;
15497 struct drm_i915_private *dev_priv = dev->dev_private;
15498 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15499
15500 /* Clear any frame start delays used for debugging left by the BIOS */
15501 if (!transcoder_is_dsi(cpu_transcoder)) {
15502 i915_reg_t reg = PIPECONF(cpu_transcoder);
15503
15504 I915_WRITE(reg,
15505 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15506 }
15507
15508 /* restore vblank interrupts to correct state */
15509 drm_crtc_vblank_reset(&crtc->base);
15510 if (crtc->active) {
15511 struct intel_plane *plane;
15512
15513 drm_crtc_vblank_on(&crtc->base);
15514
15515 /* Disable everything but the primary plane */
15516 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15517 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15518 continue;
15519
15520 plane->disable_plane(&plane->base, &crtc->base);
15521 }
15522 }
15523
15524 /* We need to sanitize the plane -> pipe mapping first because this will
15525 * disable the crtc (and hence change the state) if it is wrong. Note
15526 * that gen4+ has a fixed plane -> pipe mapping. */
15527 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15528 bool plane;
15529
15530 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15531 crtc->base.base.id);
15532
15533 /* Pipe has the wrong plane attached and the plane is active.
15534 * Temporarily change the plane mapping and disable everything
15535 * ... */
15536 plane = crtc->plane;
15537 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15538 crtc->plane = !plane;
15539 intel_crtc_disable_noatomic(&crtc->base);
15540 crtc->plane = plane;
15541 }
15542
15543 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15544 crtc->pipe == PIPE_A && !crtc->active) {
15545 /* BIOS forgot to enable pipe A, this mostly happens after
15546 * resume. Force-enable the pipe to fix this, the update_dpms
15547 * call below we restore the pipe to the right state, but leave
15548 * the required bits on. */
15549 intel_enable_pipe_a(dev);
15550 }
15551
15552 /* Adjust the state of the output pipe according to whether we
15553 * have active connectors/encoders. */
15554 if (crtc->active && !intel_crtc_has_encoders(crtc))
15555 intel_crtc_disable_noatomic(&crtc->base);
15556
15557 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15558 /*
15559 * We start out with underrun reporting disabled to avoid races.
15560 * For correct bookkeeping mark this on active crtcs.
15561 *
15562 * Also on gmch platforms we dont have any hardware bits to
15563 * disable the underrun reporting. Which means we need to start
15564 * out with underrun reporting disabled also on inactive pipes,
15565 * since otherwise we'll complain about the garbage we read when
15566 * e.g. coming up after runtime pm.
15567 *
15568 * No protection against concurrent access is required - at
15569 * worst a fifo underrun happens which also sets this to false.
15570 */
15571 crtc->cpu_fifo_underrun_disabled = true;
15572 crtc->pch_fifo_underrun_disabled = true;
15573 }
15574 }
15575
15576 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15577 {
15578 struct intel_connector *connector;
15579 struct drm_device *dev = encoder->base.dev;
15580
15581 /* We need to check both for a crtc link (meaning that the
15582 * encoder is active and trying to read from a pipe) and the
15583 * pipe itself being active. */
15584 bool has_active_crtc = encoder->base.crtc &&
15585 to_intel_crtc(encoder->base.crtc)->active;
15586
15587 if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15588 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15589 encoder->base.base.id,
15590 encoder->base.name);
15591
15592 /* Connector is active, but has no active pipe. This is
15593 * fallout from our resume register restoring. Disable
15594 * the encoder manually again. */
15595 if (encoder->base.crtc) {
15596 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15597 encoder->base.base.id,
15598 encoder->base.name);
15599 encoder->disable(encoder);
15600 if (encoder->post_disable)
15601 encoder->post_disable(encoder);
15602 }
15603 encoder->base.crtc = NULL;
15604
15605 /* Inconsistent output/port/pipe state happens presumably due to
15606 * a bug in one of the get_hw_state functions. Or someplace else
15607 * in our code, like the register restore mess on resume. Clamp
15608 * things to off as a safer default. */
15609 for_each_intel_connector(dev, connector) {
15610 if (connector->encoder != encoder)
15611 continue;
15612 connector->base.dpms = DRM_MODE_DPMS_OFF;
15613 connector->base.encoder = NULL;
15614 }
15615 }
15616 /* Enabled encoders without active connectors will be fixed in
15617 * the crtc fixup. */
15618 }
15619
15620 void i915_redisable_vga_power_on(struct drm_device *dev)
15621 {
15622 struct drm_i915_private *dev_priv = dev->dev_private;
15623 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15624
15625 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15626 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15627 i915_disable_vga(dev);
15628 }
15629 }
15630
15631 void i915_redisable_vga(struct drm_device *dev)
15632 {
15633 struct drm_i915_private *dev_priv = dev->dev_private;
15634
15635 /* This function can be called both from intel_modeset_setup_hw_state or
15636 * at a very early point in our resume sequence, where the power well
15637 * structures are not yet restored. Since this function is at a very
15638 * paranoid "someone might have enabled VGA while we were not looking"
15639 * level, just check if the power well is enabled instead of trying to
15640 * follow the "don't touch the power well if we don't need it" policy
15641 * the rest of the driver uses. */
15642 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15643 return;
15644
15645 i915_redisable_vga_power_on(dev);
15646
15647 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15648 }
15649
15650 static bool primary_get_hw_state(struct intel_plane *plane)
15651 {
15652 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15653
15654 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15655 }
15656
15657 /* FIXME read out full plane state for all planes */
15658 static void readout_plane_state(struct intel_crtc *crtc)
15659 {
15660 struct drm_plane *primary = crtc->base.primary;
15661 struct intel_plane_state *plane_state =
15662 to_intel_plane_state(primary->state);
15663
15664 plane_state->visible = crtc->active &&
15665 primary_get_hw_state(to_intel_plane(primary));
15666
15667 if (plane_state->visible)
15668 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15669 }
15670
15671 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15672 {
15673 struct drm_i915_private *dev_priv = dev->dev_private;
15674 enum pipe pipe;
15675 struct intel_crtc *crtc;
15676 struct intel_encoder *encoder;
15677 struct intel_connector *connector;
15678 int i;
15679
15680 dev_priv->active_crtcs = 0;
15681
15682 for_each_intel_crtc(dev, crtc) {
15683 struct intel_crtc_state *crtc_state = crtc->config;
15684 int pixclk = 0;
15685
15686 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15687 memset(crtc_state, 0, sizeof(*crtc_state));
15688 crtc_state->base.crtc = &crtc->base;
15689
15690 crtc_state->base.active = crtc_state->base.enable =
15691 dev_priv->display.get_pipe_config(crtc, crtc_state);
15692
15693 crtc->base.enabled = crtc_state->base.enable;
15694 crtc->active = crtc_state->base.active;
15695
15696 if (crtc_state->base.active) {
15697 dev_priv->active_crtcs |= 1 << crtc->pipe;
15698
15699 if (IS_BROADWELL(dev_priv)) {
15700 pixclk = ilk_pipe_pixel_rate(crtc_state);
15701
15702 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15703 if (crtc_state->ips_enabled)
15704 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15705 } else if (IS_VALLEYVIEW(dev_priv) ||
15706 IS_CHERRYVIEW(dev_priv) ||
15707 IS_BROXTON(dev_priv))
15708 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15709 else
15710 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15711 }
15712
15713 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15714
15715 readout_plane_state(crtc);
15716
15717 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15718 crtc->base.base.id,
15719 crtc->active ? "enabled" : "disabled");
15720 }
15721
15722 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15723 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15724
15725 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15726 &pll->config.hw_state);
15727 pll->config.crtc_mask = 0;
15728 for_each_intel_crtc(dev, crtc) {
15729 if (crtc->active && crtc->config->shared_dpll == pll)
15730 pll->config.crtc_mask |= 1 << crtc->pipe;
15731 }
15732 pll->active_mask = pll->config.crtc_mask;
15733
15734 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15735 pll->name, pll->config.crtc_mask, pll->on);
15736 }
15737
15738 for_each_intel_encoder(dev, encoder) {
15739 pipe = 0;
15740
15741 if (encoder->get_hw_state(encoder, &pipe)) {
15742 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15743 encoder->base.crtc = &crtc->base;
15744 encoder->get_config(encoder, crtc->config);
15745 } else {
15746 encoder->base.crtc = NULL;
15747 }
15748
15749 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15750 encoder->base.base.id,
15751 encoder->base.name,
15752 encoder->base.crtc ? "enabled" : "disabled",
15753 pipe_name(pipe));
15754 }
15755
15756 for_each_intel_connector(dev, connector) {
15757 if (connector->get_hw_state(connector)) {
15758 connector->base.dpms = DRM_MODE_DPMS_ON;
15759
15760 encoder = connector->encoder;
15761 connector->base.encoder = &encoder->base;
15762
15763 if (encoder->base.crtc &&
15764 encoder->base.crtc->state->active) {
15765 /*
15766 * This has to be done during hardware readout
15767 * because anything calling .crtc_disable may
15768 * rely on the connector_mask being accurate.
15769 */
15770 encoder->base.crtc->state->connector_mask |=
15771 1 << drm_connector_index(&connector->base);
15772 encoder->base.crtc->state->encoder_mask |=
15773 1 << drm_encoder_index(&encoder->base);
15774 }
15775
15776 } else {
15777 connector->base.dpms = DRM_MODE_DPMS_OFF;
15778 connector->base.encoder = NULL;
15779 }
15780 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15781 connector->base.base.id,
15782 connector->base.name,
15783 connector->base.encoder ? "enabled" : "disabled");
15784 }
15785
15786 for_each_intel_crtc(dev, crtc) {
15787 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15788
15789 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15790 if (crtc->base.state->active) {
15791 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15792 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15793 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15794
15795 /*
15796 * The initial mode needs to be set in order to keep
15797 * the atomic core happy. It wants a valid mode if the
15798 * crtc's enabled, so we do the above call.
15799 *
15800 * At this point some state updated by the connectors
15801 * in their ->detect() callback has not run yet, so
15802 * no recalculation can be done yet.
15803 *
15804 * Even if we could do a recalculation and modeset
15805 * right now it would cause a double modeset if
15806 * fbdev or userspace chooses a different initial mode.
15807 *
15808 * If that happens, someone indicated they wanted a
15809 * mode change, which means it's safe to do a full
15810 * recalculation.
15811 */
15812 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15813
15814 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15815 update_scanline_offset(crtc);
15816 }
15817
15818 intel_pipe_config_sanity_check(dev_priv, crtc->config);
15819 }
15820 }
15821
15822 /* Scan out the current hw modeset state,
15823 * and sanitizes it to the current state
15824 */
15825 static void
15826 intel_modeset_setup_hw_state(struct drm_device *dev)
15827 {
15828 struct drm_i915_private *dev_priv = dev->dev_private;
15829 enum pipe pipe;
15830 struct intel_crtc *crtc;
15831 struct intel_encoder *encoder;
15832 int i;
15833
15834 intel_modeset_readout_hw_state(dev);
15835
15836 /* HW state is read out, now we need to sanitize this mess. */
15837 for_each_intel_encoder(dev, encoder) {
15838 intel_sanitize_encoder(encoder);
15839 }
15840
15841 for_each_pipe(dev_priv, pipe) {
15842 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15843 intel_sanitize_crtc(crtc);
15844 intel_dump_pipe_config(crtc, crtc->config,
15845 "[setup_hw_state]");
15846 }
15847
15848 intel_modeset_update_connector_atomic_state(dev);
15849
15850 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15851 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15852
15853 if (!pll->on || pll->active_mask)
15854 continue;
15855
15856 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15857
15858 pll->funcs.disable(dev_priv, pll);
15859 pll->on = false;
15860 }
15861
15862 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15863 vlv_wm_get_hw_state(dev);
15864 else if (IS_GEN9(dev))
15865 skl_wm_get_hw_state(dev);
15866 else if (HAS_PCH_SPLIT(dev))
15867 ilk_wm_get_hw_state(dev);
15868
15869 for_each_intel_crtc(dev, crtc) {
15870 unsigned long put_domains;
15871
15872 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15873 if (WARN_ON(put_domains))
15874 modeset_put_power_domains(dev_priv, put_domains);
15875 }
15876 intel_display_set_init_power(dev_priv, false);
15877
15878 intel_fbc_init_pipe_state(dev_priv);
15879 }
15880
15881 void intel_display_resume(struct drm_device *dev)
15882 {
15883 struct drm_i915_private *dev_priv = to_i915(dev);
15884 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15885 struct drm_modeset_acquire_ctx ctx;
15886 int ret;
15887 bool setup = false;
15888
15889 dev_priv->modeset_restore_state = NULL;
15890
15891 /*
15892 * This is a cludge because with real atomic modeset mode_config.mutex
15893 * won't be taken. Unfortunately some probed state like
15894 * audio_codec_enable is still protected by mode_config.mutex, so lock
15895 * it here for now.
15896 */
15897 mutex_lock(&dev->mode_config.mutex);
15898 drm_modeset_acquire_init(&ctx, 0);
15899
15900 retry:
15901 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15902
15903 if (ret == 0 && !setup) {
15904 setup = true;
15905
15906 intel_modeset_setup_hw_state(dev);
15907 i915_redisable_vga(dev);
15908 }
15909
15910 if (ret == 0 && state) {
15911 struct drm_crtc_state *crtc_state;
15912 struct drm_crtc *crtc;
15913 int i;
15914
15915 state->acquire_ctx = &ctx;
15916
15917 /* ignore any reset values/BIOS leftovers in the WM registers */
15918 to_intel_atomic_state(state)->skip_intermediate_wm = true;
15919
15920 for_each_crtc_in_state(state, crtc, crtc_state, i) {
15921 /*
15922 * Force recalculation even if we restore
15923 * current state. With fast modeset this may not result
15924 * in a modeset when the state is compatible.
15925 */
15926 crtc_state->mode_changed = true;
15927 }
15928
15929 ret = drm_atomic_commit(state);
15930 }
15931
15932 if (ret == -EDEADLK) {
15933 drm_modeset_backoff(&ctx);
15934 goto retry;
15935 }
15936
15937 drm_modeset_drop_locks(&ctx);
15938 drm_modeset_acquire_fini(&ctx);
15939 mutex_unlock(&dev->mode_config.mutex);
15940
15941 if (ret) {
15942 DRM_ERROR("Restoring old state failed with %i\n", ret);
15943 drm_atomic_state_free(state);
15944 }
15945 }
15946
15947 void intel_modeset_gem_init(struct drm_device *dev)
15948 {
15949 struct drm_i915_private *dev_priv = to_i915(dev);
15950 struct drm_crtc *c;
15951 struct drm_i915_gem_object *obj;
15952 int ret;
15953
15954 intel_init_gt_powersave(dev_priv);
15955
15956 intel_modeset_init_hw(dev);
15957
15958 intel_setup_overlay(dev_priv);
15959
15960 /*
15961 * Make sure any fbs we allocated at startup are properly
15962 * pinned & fenced. When we do the allocation it's too early
15963 * for this.
15964 */
15965 for_each_crtc(dev, c) {
15966 obj = intel_fb_obj(c->primary->fb);
15967 if (obj == NULL)
15968 continue;
15969
15970 mutex_lock(&dev->struct_mutex);
15971 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
15972 c->primary->state->rotation);
15973 mutex_unlock(&dev->struct_mutex);
15974 if (ret) {
15975 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15976 to_intel_crtc(c)->pipe);
15977 drm_framebuffer_unreference(c->primary->fb);
15978 c->primary->fb = NULL;
15979 c->primary->crtc = c->primary->state->crtc = NULL;
15980 update_state_fb(c->primary);
15981 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15982 }
15983 }
15984
15985 intel_backlight_register(dev);
15986 }
15987
15988 void intel_connector_unregister(struct intel_connector *intel_connector)
15989 {
15990 struct drm_connector *connector = &intel_connector->base;
15991
15992 intel_panel_destroy_backlight(connector);
15993 drm_connector_unregister(connector);
15994 }
15995
15996 void intel_modeset_cleanup(struct drm_device *dev)
15997 {
15998 struct drm_i915_private *dev_priv = dev->dev_private;
15999 struct intel_connector *connector;
16000
16001 intel_disable_gt_powersave(dev_priv);
16002
16003 intel_backlight_unregister(dev);
16004
16005 /*
16006 * Interrupts and polling as the first thing to avoid creating havoc.
16007 * Too much stuff here (turning of connectors, ...) would
16008 * experience fancy races otherwise.
16009 */
16010 intel_irq_uninstall(dev_priv);
16011
16012 /*
16013 * Due to the hpd irq storm handling the hotplug work can re-arm the
16014 * poll handlers. Hence disable polling after hpd handling is shut down.
16015 */
16016 drm_kms_helper_poll_fini(dev);
16017
16018 intel_unregister_dsm_handler();
16019
16020 intel_fbc_global_disable(dev_priv);
16021
16022 /* flush any delayed tasks or pending work */
16023 flush_scheduled_work();
16024
16025 /* destroy the backlight and sysfs files before encoders/connectors */
16026 for_each_intel_connector(dev, connector)
16027 connector->unregister(connector);
16028
16029 drm_mode_config_cleanup(dev);
16030
16031 intel_cleanup_overlay(dev_priv);
16032
16033 intel_cleanup_gt_powersave(dev_priv);
16034
16035 intel_teardown_gmbus(dev);
16036 }
16037
16038 /*
16039 * Return which encoder is currently attached for connector.
16040 */
16041 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
16042 {
16043 return &intel_attached_encoder(connector)->base;
16044 }
16045
16046 void intel_connector_attach_encoder(struct intel_connector *connector,
16047 struct intel_encoder *encoder)
16048 {
16049 connector->encoder = encoder;
16050 drm_mode_connector_attach_encoder(&connector->base,
16051 &encoder->base);
16052 }
16053
16054 /*
16055 * set vga decode state - true == enable VGA decode
16056 */
16057 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16058 {
16059 struct drm_i915_private *dev_priv = dev->dev_private;
16060 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16061 u16 gmch_ctrl;
16062
16063 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16064 DRM_ERROR("failed to read control word\n");
16065 return -EIO;
16066 }
16067
16068 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16069 return 0;
16070
16071 if (state)
16072 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16073 else
16074 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16075
16076 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16077 DRM_ERROR("failed to write control word\n");
16078 return -EIO;
16079 }
16080
16081 return 0;
16082 }
16083
16084 struct intel_display_error_state {
16085
16086 u32 power_well_driver;
16087
16088 int num_transcoders;
16089
16090 struct intel_cursor_error_state {
16091 u32 control;
16092 u32 position;
16093 u32 base;
16094 u32 size;
16095 } cursor[I915_MAX_PIPES];
16096
16097 struct intel_pipe_error_state {
16098 bool power_domain_on;
16099 u32 source;
16100 u32 stat;
16101 } pipe[I915_MAX_PIPES];
16102
16103 struct intel_plane_error_state {
16104 u32 control;
16105 u32 stride;
16106 u32 size;
16107 u32 pos;
16108 u32 addr;
16109 u32 surface;
16110 u32 tile_offset;
16111 } plane[I915_MAX_PIPES];
16112
16113 struct intel_transcoder_error_state {
16114 bool power_domain_on;
16115 enum transcoder cpu_transcoder;
16116
16117 u32 conf;
16118
16119 u32 htotal;
16120 u32 hblank;
16121 u32 hsync;
16122 u32 vtotal;
16123 u32 vblank;
16124 u32 vsync;
16125 } transcoder[4];
16126 };
16127
16128 struct intel_display_error_state *
16129 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16130 {
16131 struct intel_display_error_state *error;
16132 int transcoders[] = {
16133 TRANSCODER_A,
16134 TRANSCODER_B,
16135 TRANSCODER_C,
16136 TRANSCODER_EDP,
16137 };
16138 int i;
16139
16140 if (INTEL_INFO(dev_priv)->num_pipes == 0)
16141 return NULL;
16142
16143 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16144 if (error == NULL)
16145 return NULL;
16146
16147 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16148 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16149
16150 for_each_pipe(dev_priv, i) {
16151 error->pipe[i].power_domain_on =
16152 __intel_display_power_is_enabled(dev_priv,
16153 POWER_DOMAIN_PIPE(i));
16154 if (!error->pipe[i].power_domain_on)
16155 continue;
16156
16157 error->cursor[i].control = I915_READ(CURCNTR(i));
16158 error->cursor[i].position = I915_READ(CURPOS(i));
16159 error->cursor[i].base = I915_READ(CURBASE(i));
16160
16161 error->plane[i].control = I915_READ(DSPCNTR(i));
16162 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16163 if (INTEL_GEN(dev_priv) <= 3) {
16164 error->plane[i].size = I915_READ(DSPSIZE(i));
16165 error->plane[i].pos = I915_READ(DSPPOS(i));
16166 }
16167 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16168 error->plane[i].addr = I915_READ(DSPADDR(i));
16169 if (INTEL_GEN(dev_priv) >= 4) {
16170 error->plane[i].surface = I915_READ(DSPSURF(i));
16171 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16172 }
16173
16174 error->pipe[i].source = I915_READ(PIPESRC(i));
16175
16176 if (HAS_GMCH_DISPLAY(dev_priv))
16177 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16178 }
16179
16180 /* Note: this does not include DSI transcoders. */
16181 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
16182 if (HAS_DDI(dev_priv))
16183 error->num_transcoders++; /* Account for eDP. */
16184
16185 for (i = 0; i < error->num_transcoders; i++) {
16186 enum transcoder cpu_transcoder = transcoders[i];
16187
16188 error->transcoder[i].power_domain_on =
16189 __intel_display_power_is_enabled(dev_priv,
16190 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16191 if (!error->transcoder[i].power_domain_on)
16192 continue;
16193
16194 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16195
16196 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16197 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16198 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16199 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16200 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16201 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16202 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16203 }
16204
16205 return error;
16206 }
16207
16208 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16209
16210 void
16211 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16212 struct drm_device *dev,
16213 struct intel_display_error_state *error)
16214 {
16215 struct drm_i915_private *dev_priv = dev->dev_private;
16216 int i;
16217
16218 if (!error)
16219 return;
16220
16221 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16222 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16223 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16224 error->power_well_driver);
16225 for_each_pipe(dev_priv, i) {
16226 err_printf(m, "Pipe [%d]:\n", i);
16227 err_printf(m, " Power: %s\n",
16228 onoff(error->pipe[i].power_domain_on));
16229 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16230 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16231
16232 err_printf(m, "Plane [%d]:\n", i);
16233 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16234 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16235 if (INTEL_INFO(dev)->gen <= 3) {
16236 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16237 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16238 }
16239 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16240 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16241 if (INTEL_INFO(dev)->gen >= 4) {
16242 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16243 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16244 }
16245
16246 err_printf(m, "Cursor [%d]:\n", i);
16247 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16248 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16249 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16250 }
16251
16252 for (i = 0; i < error->num_transcoders; i++) {
16253 err_printf(m, "CPU transcoder: %s\n",
16254 transcoder_name(error->transcoder[i].cpu_transcoder));
16255 err_printf(m, " Power: %s\n",
16256 onoff(error->transcoder[i].power_domain_on));
16257 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16258 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16259 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16260 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16261 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16262 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16263 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16264 }
16265 }
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