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drm/i915: rip out superflous is_dp&is_cpu_edp tracking
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47
48 typedef struct {
49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
58 } intel_clock_t;
59
60 typedef struct {
61 int min, max;
62 } intel_range_t;
63
64 typedef struct {
65 int dot_limit;
66 int p2_slow, p2_fast;
67 } intel_p2_t;
68
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t;
71 struct intel_limit {
72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 /**
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
77 * @crtc: current CRTC
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
84 *
85 * Returns true on success, false on failure.
86 */
87 bool (*find_pll)(const intel_limit_t *limit,
88 struct drm_crtc *crtc,
89 int target, int refclk,
90 intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
92 };
93
94 /* FDI */
95 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
96
97 int
98 intel_pch_rawclk(struct drm_device *dev)
99 {
100 struct drm_i915_private *dev_priv = dev->dev_private;
101
102 WARN_ON(!HAS_PCH_SPLIT(dev));
103
104 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
105 }
106
107 static bool
108 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
109 int target, int refclk, intel_clock_t *match_clock,
110 intel_clock_t *best_clock);
111 static bool
112 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
115
116 static bool
117 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
118 int target, int refclk, intel_clock_t *match_clock,
119 intel_clock_t *best_clock);
120 static bool
121 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
122 int target, int refclk, intel_clock_t *match_clock,
123 intel_clock_t *best_clock);
124
125 static bool
126 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
127 int target, int refclk, intel_clock_t *match_clock,
128 intel_clock_t *best_clock);
129
130 static inline u32 /* units of 100MHz */
131 intel_fdi_link_freq(struct drm_device *dev)
132 {
133 if (IS_GEN5(dev)) {
134 struct drm_i915_private *dev_priv = dev->dev_private;
135 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
136 } else
137 return 27;
138 }
139
140 static const intel_limit_t intel_limits_i8xx_dvo = {
141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 2, .max = 33 },
149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 4, .p2_fast = 2 },
151 .find_pll = intel_find_best_PLL,
152 };
153
154 static const intel_limit_t intel_limits_i8xx_lvds = {
155 .dot = { .min = 25000, .max = 350000 },
156 .vco = { .min = 930000, .max = 1400000 },
157 .n = { .min = 3, .max = 16 },
158 .m = { .min = 96, .max = 140 },
159 .m1 = { .min = 18, .max = 26 },
160 .m2 = { .min = 6, .max = 16 },
161 .p = { .min = 4, .max = 128 },
162 .p1 = { .min = 1, .max = 6 },
163 .p2 = { .dot_limit = 165000,
164 .p2_slow = 14, .p2_fast = 7 },
165 .find_pll = intel_find_best_PLL,
166 };
167
168 static const intel_limit_t intel_limits_i9xx_sdvo = {
169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
173 .m1 = { .min = 8, .max = 18 },
174 .m2 = { .min = 3, .max = 7 },
175 .p = { .min = 5, .max = 80 },
176 .p1 = { .min = 1, .max = 8 },
177 .p2 = { .dot_limit = 200000,
178 .p2_slow = 10, .p2_fast = 5 },
179 .find_pll = intel_find_best_PLL,
180 };
181
182 static const intel_limit_t intel_limits_i9xx_lvds = {
183 .dot = { .min = 20000, .max = 400000 },
184 .vco = { .min = 1400000, .max = 2800000 },
185 .n = { .min = 1, .max = 6 },
186 .m = { .min = 70, .max = 120 },
187 .m1 = { .min = 8, .max = 18 },
188 .m2 = { .min = 3, .max = 7 },
189 .p = { .min = 7, .max = 98 },
190 .p1 = { .min = 1, .max = 8 },
191 .p2 = { .dot_limit = 112000,
192 .p2_slow = 14, .p2_fast = 7 },
193 .find_pll = intel_find_best_PLL,
194 };
195
196
197 static const intel_limit_t intel_limits_g4x_sdvo = {
198 .dot = { .min = 25000, .max = 270000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 17, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 10, .max = 30 },
205 .p1 = { .min = 1, .max = 3},
206 .p2 = { .dot_limit = 270000,
207 .p2_slow = 10,
208 .p2_fast = 10
209 },
210 .find_pll = intel_g4x_find_best_PLL,
211 };
212
213 static const intel_limit_t intel_limits_g4x_hdmi = {
214 .dot = { .min = 22000, .max = 400000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 16, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 5, .max = 80 },
221 .p1 = { .min = 1, .max = 8},
222 .p2 = { .dot_limit = 165000,
223 .p2_slow = 10, .p2_fast = 5 },
224 .find_pll = intel_g4x_find_best_PLL,
225 };
226
227 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
228 .dot = { .min = 20000, .max = 115000 },
229 .vco = { .min = 1750000, .max = 3500000 },
230 .n = { .min = 1, .max = 3 },
231 .m = { .min = 104, .max = 138 },
232 .m1 = { .min = 17, .max = 23 },
233 .m2 = { .min = 5, .max = 11 },
234 .p = { .min = 28, .max = 112 },
235 .p1 = { .min = 2, .max = 8 },
236 .p2 = { .dot_limit = 0,
237 .p2_slow = 14, .p2_fast = 14
238 },
239 .find_pll = intel_g4x_find_best_PLL,
240 };
241
242 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
243 .dot = { .min = 80000, .max = 224000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 14, .max = 42 },
250 .p1 = { .min = 2, .max = 6 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 7, .p2_fast = 7
253 },
254 .find_pll = intel_g4x_find_best_PLL,
255 };
256
257 static const intel_limit_t intel_limits_g4x_display_port = {
258 .dot = { .min = 161670, .max = 227000 },
259 .vco = { .min = 1750000, .max = 3500000},
260 .n = { .min = 1, .max = 2 },
261 .m = { .min = 97, .max = 108 },
262 .m1 = { .min = 0x10, .max = 0x12 },
263 .m2 = { .min = 0x05, .max = 0x06 },
264 .p = { .min = 10, .max = 20 },
265 .p1 = { .min = 1, .max = 2},
266 .p2 = { .dot_limit = 0,
267 .p2_slow = 10, .p2_fast = 10 },
268 .find_pll = intel_find_pll_g4x_dp,
269 };
270
271 static const intel_limit_t intel_limits_pineview_sdvo = {
272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
274 /* Pineview's Ncounter is a ring counter */
275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
277 /* Pineview only has one combined m divider, which we treat as m2. */
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
284 .find_pll = intel_find_best_PLL,
285 };
286
287 static const intel_limit_t intel_limits_pineview_lvds = {
288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
298 .find_pll = intel_find_best_PLL,
299 };
300
301 /* Ironlake / Sandybridge
302 *
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
305 */
306 static const intel_limit_t intel_limits_ironlake_dac = {
307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 5 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 5, .max = 80 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 10, .p2_fast = 5 },
317 .find_pll = intel_g4x_find_best_PLL,
318 };
319
320 static const intel_limit_t intel_limits_ironlake_single_lvds = {
321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 118 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
331 .find_pll = intel_g4x_find_best_PLL,
332 };
333
334 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 127 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 56 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
345 .find_pll = intel_g4x_find_best_PLL,
346 };
347
348 /* LVDS 100mhz refclk limits. */
349 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 28, .max = 112 },
357 .p1 = { .min = 2, .max = 8 },
358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 },
360 .find_pll = intel_g4x_find_best_PLL,
361 };
362
363 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
371 .p1 = { .min = 2, .max = 6 },
372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
374 .find_pll = intel_g4x_find_best_PLL,
375 };
376
377 static const intel_limit_t intel_limits_ironlake_display_port = {
378 .dot = { .min = 25000, .max = 350000 },
379 .vco = { .min = 1760000, .max = 3510000},
380 .n = { .min = 1, .max = 2 },
381 .m = { .min = 81, .max = 90 },
382 .m1 = { .min = 12, .max = 22 },
383 .m2 = { .min = 5, .max = 9 },
384 .p = { .min = 10, .max = 20 },
385 .p1 = { .min = 1, .max = 2},
386 .p2 = { .dot_limit = 0,
387 .p2_slow = 10, .p2_fast = 10 },
388 .find_pll = intel_find_pll_ironlake_dp,
389 };
390
391 static const intel_limit_t intel_limits_vlv_dac = {
392 .dot = { .min = 25000, .max = 270000 },
393 .vco = { .min = 4000000, .max = 6000000 },
394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 22, .max = 450 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403 };
404
405 static const intel_limit_t intel_limits_vlv_hdmi = {
406 .dot = { .min = 20000, .max = 165000 },
407 .vco = { .min = 4000000, .max = 5994000},
408 .n = { .min = 1, .max = 7 },
409 .m = { .min = 60, .max = 300 }, /* guess */
410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417 };
418
419 static const intel_limit_t intel_limits_vlv_dp = {
420 .dot = { .min = 25000, .max = 270000 },
421 .vco = { .min = 4000000, .max = 6000000 },
422 .n = { .min = 1, .max = 7 },
423 .m = { .min = 22, .max = 450 },
424 .m1 = { .min = 2, .max = 3 },
425 .m2 = { .min = 11, .max = 156 },
426 .p = { .min = 10, .max = 30 },
427 .p1 = { .min = 2, .max = 3 },
428 .p2 = { .dot_limit = 270000,
429 .p2_slow = 2, .p2_fast = 20 },
430 .find_pll = intel_vlv_find_best_pll,
431 };
432
433 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
434 {
435 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
436
437 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
439 return 0;
440 }
441
442 I915_WRITE(DPIO_REG, reg);
443 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
444 DPIO_BYTE);
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
447 return 0;
448 }
449
450 return I915_READ(DPIO_DATA);
451 }
452
453 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
454 u32 val)
455 {
456 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
457
458 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
459 DRM_ERROR("DPIO idle wait timed out\n");
460 return;
461 }
462
463 I915_WRITE(DPIO_DATA, val);
464 I915_WRITE(DPIO_REG, reg);
465 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
466 DPIO_BYTE);
467 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
468 DRM_ERROR("DPIO write wait timed out\n");
469 }
470
471 static void vlv_init_dpio(struct drm_device *dev)
472 {
473 struct drm_i915_private *dev_priv = dev->dev_private;
474
475 /* Reset the DPIO config */
476 I915_WRITE(DPIO_CTL, 0);
477 POSTING_READ(DPIO_CTL);
478 I915_WRITE(DPIO_CTL, 1);
479 POSTING_READ(DPIO_CTL);
480 }
481
482 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
483 int refclk)
484 {
485 struct drm_device *dev = crtc->dev;
486 const intel_limit_t *limit;
487
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
489 if (intel_is_dual_link_lvds(dev)) {
490 if (refclk == 100000)
491 limit = &intel_limits_ironlake_dual_lvds_100m;
492 else
493 limit = &intel_limits_ironlake_dual_lvds;
494 } else {
495 if (refclk == 100000)
496 limit = &intel_limits_ironlake_single_lvds_100m;
497 else
498 limit = &intel_limits_ironlake_single_lvds;
499 }
500 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
501 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
502 limit = &intel_limits_ironlake_display_port;
503 else
504 limit = &intel_limits_ironlake_dac;
505
506 return limit;
507 }
508
509 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
510 {
511 struct drm_device *dev = crtc->dev;
512 const intel_limit_t *limit;
513
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
515 if (intel_is_dual_link_lvds(dev))
516 limit = &intel_limits_g4x_dual_channel_lvds;
517 else
518 limit = &intel_limits_g4x_single_channel_lvds;
519 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
520 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
521 limit = &intel_limits_g4x_hdmi;
522 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
523 limit = &intel_limits_g4x_sdvo;
524 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
525 limit = &intel_limits_g4x_display_port;
526 } else /* The option is for other outputs */
527 limit = &intel_limits_i9xx_sdvo;
528
529 return limit;
530 }
531
532 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
533 {
534 struct drm_device *dev = crtc->dev;
535 const intel_limit_t *limit;
536
537 if (HAS_PCH_SPLIT(dev))
538 limit = intel_ironlake_limit(crtc, refclk);
539 else if (IS_G4X(dev)) {
540 limit = intel_g4x_limit(crtc);
541 } else if (IS_PINEVIEW(dev)) {
542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
543 limit = &intel_limits_pineview_lvds;
544 else
545 limit = &intel_limits_pineview_sdvo;
546 } else if (IS_VALLEYVIEW(dev)) {
547 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
548 limit = &intel_limits_vlv_dac;
549 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
550 limit = &intel_limits_vlv_hdmi;
551 else
552 limit = &intel_limits_vlv_dp;
553 } else if (!IS_GEN2(dev)) {
554 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
555 limit = &intel_limits_i9xx_lvds;
556 else
557 limit = &intel_limits_i9xx_sdvo;
558 } else {
559 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
560 limit = &intel_limits_i8xx_lvds;
561 else
562 limit = &intel_limits_i8xx_dvo;
563 }
564 return limit;
565 }
566
567 /* m1 is reserved as 0 in Pineview, n is a ring counter */
568 static void pineview_clock(int refclk, intel_clock_t *clock)
569 {
570 clock->m = clock->m2 + 2;
571 clock->p = clock->p1 * clock->p2;
572 clock->vco = refclk * clock->m / clock->n;
573 clock->dot = clock->vco / clock->p;
574 }
575
576 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
577 {
578 if (IS_PINEVIEW(dev)) {
579 pineview_clock(refclk, clock);
580 return;
581 }
582 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
583 clock->p = clock->p1 * clock->p2;
584 clock->vco = refclk * clock->m / (clock->n + 2);
585 clock->dot = clock->vco / clock->p;
586 }
587
588 /**
589 * Returns whether any output on the specified pipe is of the specified type
590 */
591 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
592 {
593 struct drm_device *dev = crtc->dev;
594 struct intel_encoder *encoder;
595
596 for_each_encoder_on_crtc(dev, crtc, encoder)
597 if (encoder->type == type)
598 return true;
599
600 return false;
601 }
602
603 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
604 /**
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
607 */
608
609 static bool intel_PLL_is_valid(struct drm_device *dev,
610 const intel_limit_t *limit,
611 const intel_clock_t *clock)
612 {
613 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
614 INTELPllInvalid("p1 out of range\n");
615 if (clock->p < limit->p.min || limit->p.max < clock->p)
616 INTELPllInvalid("p out of range\n");
617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
618 INTELPllInvalid("m2 out of range\n");
619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
620 INTELPllInvalid("m1 out of range\n");
621 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
622 INTELPllInvalid("m1 <= m2\n");
623 if (clock->m < limit->m.min || limit->m.max < clock->m)
624 INTELPllInvalid("m out of range\n");
625 if (clock->n < limit->n.min || limit->n.max < clock->n)
626 INTELPllInvalid("n out of range\n");
627 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
628 INTELPllInvalid("vco out of range\n");
629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
631 */
632 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
633 INTELPllInvalid("dot out of range\n");
634
635 return true;
636 }
637
638 static bool
639 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
640 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock)
642
643 {
644 struct drm_device *dev = crtc->dev;
645 intel_clock_t clock;
646 int err = target;
647
648 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
649 /*
650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
653 */
654 if (intel_is_dual_link_lvds(dev))
655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
665 memset(best_clock, 0, sizeof(*best_clock));
666
667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
668 clock.m1++) {
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
671 /* m1 is always 0 in Pineview */
672 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
673 break;
674 for (clock.n = limit->n.min;
675 clock.n <= limit->n.max; clock.n++) {
676 for (clock.p1 = limit->p1.min;
677 clock.p1 <= limit->p1.max; clock.p1++) {
678 int this_err;
679
680 intel_clock(dev, refclk, &clock);
681 if (!intel_PLL_is_valid(dev, limit,
682 &clock))
683 continue;
684 if (match_clock &&
685 clock.p != match_clock->p)
686 continue;
687
688 this_err = abs(clock.dot - target);
689 if (this_err < err) {
690 *best_clock = clock;
691 err = this_err;
692 }
693 }
694 }
695 }
696 }
697
698 return (err != target);
699 }
700
701 static bool
702 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
703 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock)
705 {
706 struct drm_device *dev = crtc->dev;
707 intel_clock_t clock;
708 int max_n;
709 bool found;
710 /* approximately equals target * 0.00585 */
711 int err_most = (target >> 8) + (target >> 9);
712 found = false;
713
714 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
715 int lvds_reg;
716
717 if (HAS_PCH_SPLIT(dev))
718 lvds_reg = PCH_LVDS;
719 else
720 lvds_reg = LVDS;
721 if (intel_is_dual_link_lvds(dev))
722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
732 memset(best_clock, 0, sizeof(*best_clock));
733 max_n = limit->n.max;
734 /* based on hardware requirement, prefer smaller n to precision */
735 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
736 /* based on hardware requirement, prefere larger m1,m2 */
737 for (clock.m1 = limit->m1.max;
738 clock.m1 >= limit->m1.min; clock.m1--) {
739 for (clock.m2 = limit->m2.max;
740 clock.m2 >= limit->m2.min; clock.m2--) {
741 for (clock.p1 = limit->p1.max;
742 clock.p1 >= limit->p1.min; clock.p1--) {
743 int this_err;
744
745 intel_clock(dev, refclk, &clock);
746 if (!intel_PLL_is_valid(dev, limit,
747 &clock))
748 continue;
749 if (match_clock &&
750 clock.p != match_clock->p)
751 continue;
752
753 this_err = abs(clock.dot - target);
754 if (this_err < err_most) {
755 *best_clock = clock;
756 err_most = this_err;
757 max_n = clock.n;
758 found = true;
759 }
760 }
761 }
762 }
763 }
764 return found;
765 }
766
767 static bool
768 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
769 int target, int refclk, intel_clock_t *match_clock,
770 intel_clock_t *best_clock)
771 {
772 struct drm_device *dev = crtc->dev;
773 intel_clock_t clock;
774
775 if (target < 200000) {
776 clock.n = 1;
777 clock.p1 = 2;
778 clock.p2 = 10;
779 clock.m1 = 12;
780 clock.m2 = 9;
781 } else {
782 clock.n = 2;
783 clock.p1 = 1;
784 clock.p2 = 10;
785 clock.m1 = 14;
786 clock.m2 = 8;
787 }
788 intel_clock(dev, refclk, &clock);
789 memcpy(best_clock, &clock, sizeof(intel_clock_t));
790 return true;
791 }
792
793 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
794 static bool
795 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
796 int target, int refclk, intel_clock_t *match_clock,
797 intel_clock_t *best_clock)
798 {
799 intel_clock_t clock;
800 if (target < 200000) {
801 clock.p1 = 2;
802 clock.p2 = 10;
803 clock.n = 2;
804 clock.m1 = 23;
805 clock.m2 = 8;
806 } else {
807 clock.p1 = 1;
808 clock.p2 = 10;
809 clock.n = 1;
810 clock.m1 = 14;
811 clock.m2 = 2;
812 }
813 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
814 clock.p = (clock.p1 * clock.p2);
815 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
816 clock.vco = 0;
817 memcpy(best_clock, &clock, sizeof(intel_clock_t));
818 return true;
819 }
820 static bool
821 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
822 int target, int refclk, intel_clock_t *match_clock,
823 intel_clock_t *best_clock)
824 {
825 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
826 u32 m, n, fastclk;
827 u32 updrate, minupdate, fracbits, p;
828 unsigned long bestppm, ppm, absppm;
829 int dotclk, flag;
830
831 flag = 0;
832 dotclk = target * 1000;
833 bestppm = 1000000;
834 ppm = absppm = 0;
835 fastclk = dotclk / (2*100);
836 updrate = 0;
837 minupdate = 19200;
838 fracbits = 1;
839 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
840 bestm1 = bestm2 = bestp1 = bestp2 = 0;
841
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
844 updrate = refclk / n;
845 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
846 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
847 if (p2 > 10)
848 p2 = p2 - 1;
849 p = p1 * p2;
850 /* based on hardware requirement, prefer bigger m1,m2 values */
851 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
852 m2 = (((2*(fastclk * p * n / m1 )) +
853 refclk) / (2*refclk));
854 m = m1 * m2;
855 vco = updrate * m;
856 if (vco >= limit->vco.min && vco < limit->vco.max) {
857 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
858 absppm = (ppm > 0) ? ppm : (-ppm);
859 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
860 bestppm = 0;
861 flag = 1;
862 }
863 if (absppm < bestppm - 10) {
864 bestppm = absppm;
865 flag = 1;
866 }
867 if (flag) {
868 bestn = n;
869 bestm1 = m1;
870 bestm2 = m2;
871 bestp1 = p1;
872 bestp2 = p2;
873 flag = 0;
874 }
875 }
876 }
877 }
878 }
879 }
880 best_clock->n = bestn;
881 best_clock->m1 = bestm1;
882 best_clock->m2 = bestm2;
883 best_clock->p1 = bestp1;
884 best_clock->p2 = bestp2;
885
886 return true;
887 }
888
889 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
890 enum pipe pipe)
891 {
892 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
894
895 return intel_crtc->cpu_transcoder;
896 }
897
898 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
899 {
900 struct drm_i915_private *dev_priv = dev->dev_private;
901 u32 frame, frame_reg = PIPEFRAME(pipe);
902
903 frame = I915_READ(frame_reg);
904
905 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
906 DRM_DEBUG_KMS("vblank wait timed out\n");
907 }
908
909 /**
910 * intel_wait_for_vblank - wait for vblank on a given pipe
911 * @dev: drm device
912 * @pipe: pipe to wait for
913 *
914 * Wait for vblank to occur on a given pipe. Needed for various bits of
915 * mode setting code.
916 */
917 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
918 {
919 struct drm_i915_private *dev_priv = dev->dev_private;
920 int pipestat_reg = PIPESTAT(pipe);
921
922 if (INTEL_INFO(dev)->gen >= 5) {
923 ironlake_wait_for_vblank(dev, pipe);
924 return;
925 }
926
927 /* Clear existing vblank status. Note this will clear any other
928 * sticky status fields as well.
929 *
930 * This races with i915_driver_irq_handler() with the result
931 * that either function could miss a vblank event. Here it is not
932 * fatal, as we will either wait upon the next vblank interrupt or
933 * timeout. Generally speaking intel_wait_for_vblank() is only
934 * called during modeset at which time the GPU should be idle and
935 * should *not* be performing page flips and thus not waiting on
936 * vblanks...
937 * Currently, the result of us stealing a vblank from the irq
938 * handler is that a single frame will be skipped during swapbuffers.
939 */
940 I915_WRITE(pipestat_reg,
941 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
942
943 /* Wait for vblank interrupt bit to set */
944 if (wait_for(I915_READ(pipestat_reg) &
945 PIPE_VBLANK_INTERRUPT_STATUS,
946 50))
947 DRM_DEBUG_KMS("vblank wait timed out\n");
948 }
949
950 /*
951 * intel_wait_for_pipe_off - wait for pipe to turn off
952 * @dev: drm device
953 * @pipe: pipe to wait for
954 *
955 * After disabling a pipe, we can't wait for vblank in the usual way,
956 * spinning on the vblank interrupt status bit, since we won't actually
957 * see an interrupt when the pipe is disabled.
958 *
959 * On Gen4 and above:
960 * wait for the pipe register state bit to turn off
961 *
962 * Otherwise:
963 * wait for the display line value to settle (it usually
964 * ends up stopping at the start of the next frame).
965 *
966 */
967 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
968 {
969 struct drm_i915_private *dev_priv = dev->dev_private;
970 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
971 pipe);
972
973 if (INTEL_INFO(dev)->gen >= 4) {
974 int reg = PIPECONF(cpu_transcoder);
975
976 /* Wait for the Pipe State to go off */
977 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
978 100))
979 WARN(1, "pipe_off wait timed out\n");
980 } else {
981 u32 last_line, line_mask;
982 int reg = PIPEDSL(pipe);
983 unsigned long timeout = jiffies + msecs_to_jiffies(100);
984
985 if (IS_GEN2(dev))
986 line_mask = DSL_LINEMASK_GEN2;
987 else
988 line_mask = DSL_LINEMASK_GEN3;
989
990 /* Wait for the display line to settle */
991 do {
992 last_line = I915_READ(reg) & line_mask;
993 mdelay(5);
994 } while (((I915_READ(reg) & line_mask) != last_line) &&
995 time_after(timeout, jiffies));
996 if (time_after(jiffies, timeout))
997 WARN(1, "pipe_off wait timed out\n");
998 }
999 }
1000
1001 /*
1002 * ibx_digital_port_connected - is the specified port connected?
1003 * @dev_priv: i915 private structure
1004 * @port: the port to test
1005 *
1006 * Returns true if @port is connected, false otherwise.
1007 */
1008 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1009 struct intel_digital_port *port)
1010 {
1011 u32 bit;
1012
1013 if (HAS_PCH_IBX(dev_priv->dev)) {
1014 switch(port->port) {
1015 case PORT_B:
1016 bit = SDE_PORTB_HOTPLUG;
1017 break;
1018 case PORT_C:
1019 bit = SDE_PORTC_HOTPLUG;
1020 break;
1021 case PORT_D:
1022 bit = SDE_PORTD_HOTPLUG;
1023 break;
1024 default:
1025 return true;
1026 }
1027 } else {
1028 switch(port->port) {
1029 case PORT_B:
1030 bit = SDE_PORTB_HOTPLUG_CPT;
1031 break;
1032 case PORT_C:
1033 bit = SDE_PORTC_HOTPLUG_CPT;
1034 break;
1035 case PORT_D:
1036 bit = SDE_PORTD_HOTPLUG_CPT;
1037 break;
1038 default:
1039 return true;
1040 }
1041 }
1042
1043 return I915_READ(SDEISR) & bit;
1044 }
1045
1046 static const char *state_string(bool enabled)
1047 {
1048 return enabled ? "on" : "off";
1049 }
1050
1051 /* Only for pre-ILK configs */
1052 static void assert_pll(struct drm_i915_private *dev_priv,
1053 enum pipe pipe, bool state)
1054 {
1055 int reg;
1056 u32 val;
1057 bool cur_state;
1058
1059 reg = DPLL(pipe);
1060 val = I915_READ(reg);
1061 cur_state = !!(val & DPLL_VCO_ENABLE);
1062 WARN(cur_state != state,
1063 "PLL state assertion failure (expected %s, current %s)\n",
1064 state_string(state), state_string(cur_state));
1065 }
1066 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1068
1069 /* For ILK+ */
1070 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1071 struct intel_pch_pll *pll,
1072 struct intel_crtc *crtc,
1073 bool state)
1074 {
1075 u32 val;
1076 bool cur_state;
1077
1078 if (HAS_PCH_LPT(dev_priv->dev)) {
1079 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1080 return;
1081 }
1082
1083 if (WARN (!pll,
1084 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1085 return;
1086
1087 val = I915_READ(pll->pll_reg);
1088 cur_state = !!(val & DPLL_VCO_ENABLE);
1089 WARN(cur_state != state,
1090 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1091 pll->pll_reg, state_string(state), state_string(cur_state), val);
1092
1093 /* Make sure the selected PLL is correctly attached to the transcoder */
1094 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1095 u32 pch_dpll;
1096
1097 pch_dpll = I915_READ(PCH_DPLL_SEL);
1098 cur_state = pll->pll_reg == _PCH_DPLL_B;
1099 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1100 "PLL[%d] not attached to this transcoder %d: %08x\n",
1101 cur_state, crtc->pipe, pch_dpll)) {
1102 cur_state = !!(val >> (4*crtc->pipe + 3));
1103 WARN(cur_state != state,
1104 "PLL[%d] not %s on this transcoder %d: %08x\n",
1105 pll->pll_reg == _PCH_DPLL_B,
1106 state_string(state),
1107 crtc->pipe,
1108 val);
1109 }
1110 }
1111 }
1112 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1113 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1114
1115 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1117 {
1118 int reg;
1119 u32 val;
1120 bool cur_state;
1121 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122 pipe);
1123
1124 if (HAS_DDI(dev_priv->dev)) {
1125 /* DDI does not have a specific FDI_TX register */
1126 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1129 } else {
1130 reg = FDI_TX_CTL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & FDI_TX_ENABLE);
1133 }
1134 WARN(cur_state != state,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state), state_string(cur_state));
1137 }
1138 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1140
1141 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1143 {
1144 int reg;
1145 u32 val;
1146 bool cur_state;
1147
1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_ENABLE);
1151 WARN(cur_state != state,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154 }
1155 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1157
1158 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1159 enum pipe pipe)
1160 {
1161 int reg;
1162 u32 val;
1163
1164 /* ILK FDI PLL is always enabled */
1165 if (dev_priv->info->gen == 5)
1166 return;
1167
1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1169 if (HAS_DDI(dev_priv->dev))
1170 return;
1171
1172 reg = FDI_TX_CTL(pipe);
1173 val = I915_READ(reg);
1174 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1178 enum pipe pipe)
1179 {
1180 int reg;
1181 u32 val;
1182
1183 reg = FDI_RX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1186 }
1187
1188 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190 {
1191 int pp_reg, lvds_reg;
1192 u32 val;
1193 enum pipe panel_pipe = PIPE_A;
1194 bool locked = true;
1195
1196 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1197 pp_reg = PCH_PP_CONTROL;
1198 lvds_reg = PCH_LVDS;
1199 } else {
1200 pp_reg = PP_CONTROL;
1201 lvds_reg = LVDS;
1202 }
1203
1204 val = I915_READ(pp_reg);
1205 if (!(val & PANEL_POWER_ON) ||
1206 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1207 locked = false;
1208
1209 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1211
1212 WARN(panel_pipe == pipe && locked,
1213 "panel assertion failure, pipe %c regs locked\n",
1214 pipe_name(pipe));
1215 }
1216
1217 void assert_pipe(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
1219 {
1220 int reg;
1221 u32 val;
1222 bool cur_state;
1223 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1224 pipe);
1225
1226 /* if we need the pipe A quirk it must be always on */
1227 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1228 state = true;
1229
1230 if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1231 !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1232 cur_state = false;
1233 } else {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 }
1238
1239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
1241 pipe_name(pipe), state_string(state), state_string(cur_state));
1242 }
1243
1244 static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
1246 {
1247 int reg;
1248 u32 val;
1249 bool cur_state;
1250
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
1253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
1257 }
1258
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
1262 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264 {
1265 int reg, i;
1266 u32 val;
1267 int cur_pipe;
1268
1269 /* Planes are fixed to pipes on ILK+ */
1270 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1271 reg = DSPCNTR(pipe);
1272 val = I915_READ(reg);
1273 WARN((val & DISPLAY_PLANE_ENABLE),
1274 "plane %c assertion failure, should be disabled but not\n",
1275 plane_name(pipe));
1276 return;
1277 }
1278
1279 /* Need to check both planes against the pipe */
1280 for (i = 0; i < 2; i++) {
1281 reg = DSPCNTR(i);
1282 val = I915_READ(reg);
1283 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1284 DISPPLANE_SEL_PIPE_SHIFT;
1285 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1286 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1287 plane_name(i), pipe_name(pipe));
1288 }
1289 }
1290
1291 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293 {
1294 int reg, i;
1295 u32 val;
1296
1297 if (!IS_VALLEYVIEW(dev_priv->dev))
1298 return;
1299
1300 /* Need to check both planes against the pipe */
1301 for (i = 0; i < dev_priv->num_plane; i++) {
1302 reg = SPCNTR(pipe, i);
1303 val = I915_READ(reg);
1304 WARN((val & SP_ENABLE),
1305 "sprite %d assertion failure, should be off on pipe %c but is still active\n",
1306 pipe * 2 + i, pipe_name(pipe));
1307 }
1308 }
1309
1310 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1311 {
1312 u32 val;
1313 bool enabled;
1314
1315 if (HAS_PCH_LPT(dev_priv->dev)) {
1316 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1317 return;
1318 }
1319
1320 val = I915_READ(PCH_DREF_CONTROL);
1321 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1322 DREF_SUPERSPREAD_SOURCE_MASK));
1323 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1324 }
1325
1326 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1327 enum pipe pipe)
1328 {
1329 int reg;
1330 u32 val;
1331 bool enabled;
1332
1333 reg = TRANSCONF(pipe);
1334 val = I915_READ(reg);
1335 enabled = !!(val & TRANS_ENABLE);
1336 WARN(enabled,
1337 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1338 pipe_name(pipe));
1339 }
1340
1341 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1342 enum pipe pipe, u32 port_sel, u32 val)
1343 {
1344 if ((val & DP_PORT_EN) == 0)
1345 return false;
1346
1347 if (HAS_PCH_CPT(dev_priv->dev)) {
1348 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1349 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1350 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1351 return false;
1352 } else {
1353 if ((val & DP_PIPE_MASK) != (pipe << 30))
1354 return false;
1355 }
1356 return true;
1357 }
1358
1359 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1360 enum pipe pipe, u32 val)
1361 {
1362 if ((val & SDVO_ENABLE) == 0)
1363 return false;
1364
1365 if (HAS_PCH_CPT(dev_priv->dev)) {
1366 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1367 return false;
1368 } else {
1369 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1370 return false;
1371 }
1372 return true;
1373 }
1374
1375 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1376 enum pipe pipe, u32 val)
1377 {
1378 if ((val & LVDS_PORT_EN) == 0)
1379 return false;
1380
1381 if (HAS_PCH_CPT(dev_priv->dev)) {
1382 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1383 return false;
1384 } else {
1385 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1386 return false;
1387 }
1388 return true;
1389 }
1390
1391 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1392 enum pipe pipe, u32 val)
1393 {
1394 if ((val & ADPA_DAC_ENABLE) == 0)
1395 return false;
1396 if (HAS_PCH_CPT(dev_priv->dev)) {
1397 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1398 return false;
1399 } else {
1400 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1401 return false;
1402 }
1403 return true;
1404 }
1405
1406 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1407 enum pipe pipe, int reg, u32 port_sel)
1408 {
1409 u32 val = I915_READ(reg);
1410 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1411 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1412 reg, pipe_name(pipe));
1413
1414 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1415 && (val & DP_PIPEB_SELECT),
1416 "IBX PCH dp port still using transcoder B\n");
1417 }
1418
1419 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1420 enum pipe pipe, int reg)
1421 {
1422 u32 val = I915_READ(reg);
1423 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1424 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1425 reg, pipe_name(pipe));
1426
1427 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1428 && (val & SDVO_PIPE_B_SELECT),
1429 "IBX PCH hdmi port still using transcoder B\n");
1430 }
1431
1432 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1433 enum pipe pipe)
1434 {
1435 int reg;
1436 u32 val;
1437
1438 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1439 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1440 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1441
1442 reg = PCH_ADPA;
1443 val = I915_READ(reg);
1444 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1445 "PCH VGA enabled on transcoder %c, should be disabled\n",
1446 pipe_name(pipe));
1447
1448 reg = PCH_LVDS;
1449 val = I915_READ(reg);
1450 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1451 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1452 pipe_name(pipe));
1453
1454 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1455 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1456 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1457 }
1458
1459 /**
1460 * intel_enable_pll - enable a PLL
1461 * @dev_priv: i915 private structure
1462 * @pipe: pipe PLL to enable
1463 *
1464 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1465 * make sure the PLL reg is writable first though, since the panel write
1466 * protect mechanism may be enabled.
1467 *
1468 * Note! This is for pre-ILK only.
1469 *
1470 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1471 */
1472 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473 {
1474 int reg;
1475 u32 val;
1476
1477 /* No really, not for ILK+ */
1478 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1479
1480 /* PLL is protected by panel, make sure we can write it */
1481 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1482 assert_panel_unlocked(dev_priv, pipe);
1483
1484 reg = DPLL(pipe);
1485 val = I915_READ(reg);
1486 val |= DPLL_VCO_ENABLE;
1487
1488 /* We do this three times for luck */
1489 I915_WRITE(reg, val);
1490 POSTING_READ(reg);
1491 udelay(150); /* wait for warmup */
1492 I915_WRITE(reg, val);
1493 POSTING_READ(reg);
1494 udelay(150); /* wait for warmup */
1495 I915_WRITE(reg, val);
1496 POSTING_READ(reg);
1497 udelay(150); /* wait for warmup */
1498 }
1499
1500 /**
1501 * intel_disable_pll - disable a PLL
1502 * @dev_priv: i915 private structure
1503 * @pipe: pipe PLL to disable
1504 *
1505 * Disable the PLL for @pipe, making sure the pipe is off first.
1506 *
1507 * Note! This is for pre-ILK only.
1508 */
1509 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1510 {
1511 int reg;
1512 u32 val;
1513
1514 /* Don't disable pipe A or pipe A PLLs if needed */
1515 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1516 return;
1517
1518 /* Make sure the pipe isn't still relying on us */
1519 assert_pipe_disabled(dev_priv, pipe);
1520
1521 reg = DPLL(pipe);
1522 val = I915_READ(reg);
1523 val &= ~DPLL_VCO_ENABLE;
1524 I915_WRITE(reg, val);
1525 POSTING_READ(reg);
1526 }
1527
1528 /* SBI access */
1529 static void
1530 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1531 enum intel_sbi_destination destination)
1532 {
1533 u32 tmp;
1534
1535 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1536
1537 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1538 100)) {
1539 DRM_ERROR("timeout waiting for SBI to become ready\n");
1540 return;
1541 }
1542
1543 I915_WRITE(SBI_ADDR, (reg << 16));
1544 I915_WRITE(SBI_DATA, value);
1545
1546 if (destination == SBI_ICLK)
1547 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1548 else
1549 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1550 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1551
1552 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1553 100)) {
1554 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1555 return;
1556 }
1557 }
1558
1559 static u32
1560 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1561 enum intel_sbi_destination destination)
1562 {
1563 u32 value = 0;
1564 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1565
1566 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1567 100)) {
1568 DRM_ERROR("timeout waiting for SBI to become ready\n");
1569 return 0;
1570 }
1571
1572 I915_WRITE(SBI_ADDR, (reg << 16));
1573
1574 if (destination == SBI_ICLK)
1575 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1576 else
1577 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1578 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1579
1580 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1581 100)) {
1582 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1583 return 0;
1584 }
1585
1586 return I915_READ(SBI_DATA);
1587 }
1588
1589 /**
1590 * ironlake_enable_pch_pll - enable PCH PLL
1591 * @dev_priv: i915 private structure
1592 * @pipe: pipe PLL to enable
1593 *
1594 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1595 * drives the transcoder clock.
1596 */
1597 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1598 {
1599 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1600 struct intel_pch_pll *pll;
1601 int reg;
1602 u32 val;
1603
1604 /* PCH PLLs only available on ILK, SNB and IVB */
1605 BUG_ON(dev_priv->info->gen < 5);
1606 pll = intel_crtc->pch_pll;
1607 if (pll == NULL)
1608 return;
1609
1610 if (WARN_ON(pll->refcount == 0))
1611 return;
1612
1613 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1614 pll->pll_reg, pll->active, pll->on,
1615 intel_crtc->base.base.id);
1616
1617 /* PCH refclock must be enabled first */
1618 assert_pch_refclk_enabled(dev_priv);
1619
1620 if (pll->active++ && pll->on) {
1621 assert_pch_pll_enabled(dev_priv, pll, NULL);
1622 return;
1623 }
1624
1625 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1626
1627 reg = pll->pll_reg;
1628 val = I915_READ(reg);
1629 val |= DPLL_VCO_ENABLE;
1630 I915_WRITE(reg, val);
1631 POSTING_READ(reg);
1632 udelay(200);
1633
1634 pll->on = true;
1635 }
1636
1637 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1638 {
1639 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1640 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1641 int reg;
1642 u32 val;
1643
1644 /* PCH only available on ILK+ */
1645 BUG_ON(dev_priv->info->gen < 5);
1646 if (pll == NULL)
1647 return;
1648
1649 if (WARN_ON(pll->refcount == 0))
1650 return;
1651
1652 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1653 pll->pll_reg, pll->active, pll->on,
1654 intel_crtc->base.base.id);
1655
1656 if (WARN_ON(pll->active == 0)) {
1657 assert_pch_pll_disabled(dev_priv, pll, NULL);
1658 return;
1659 }
1660
1661 if (--pll->active) {
1662 assert_pch_pll_enabled(dev_priv, pll, NULL);
1663 return;
1664 }
1665
1666 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1667
1668 /* Make sure transcoder isn't still depending on us */
1669 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1670
1671 reg = pll->pll_reg;
1672 val = I915_READ(reg);
1673 val &= ~DPLL_VCO_ENABLE;
1674 I915_WRITE(reg, val);
1675 POSTING_READ(reg);
1676 udelay(200);
1677
1678 pll->on = false;
1679 }
1680
1681 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1682 enum pipe pipe)
1683 {
1684 struct drm_device *dev = dev_priv->dev;
1685 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1686 uint32_t reg, val, pipeconf_val;
1687
1688 /* PCH only available on ILK+ */
1689 BUG_ON(dev_priv->info->gen < 5);
1690
1691 /* Make sure PCH DPLL is enabled */
1692 assert_pch_pll_enabled(dev_priv,
1693 to_intel_crtc(crtc)->pch_pll,
1694 to_intel_crtc(crtc));
1695
1696 /* FDI must be feeding us bits for PCH ports */
1697 assert_fdi_tx_enabled(dev_priv, pipe);
1698 assert_fdi_rx_enabled(dev_priv, pipe);
1699
1700 if (HAS_PCH_CPT(dev)) {
1701 /* Workaround: Set the timing override bit before enabling the
1702 * pch transcoder. */
1703 reg = TRANS_CHICKEN2(pipe);
1704 val = I915_READ(reg);
1705 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1706 I915_WRITE(reg, val);
1707 }
1708
1709 reg = TRANSCONF(pipe);
1710 val = I915_READ(reg);
1711 pipeconf_val = I915_READ(PIPECONF(pipe));
1712
1713 if (HAS_PCH_IBX(dev_priv->dev)) {
1714 /*
1715 * make the BPC in transcoder be consistent with
1716 * that in pipeconf reg.
1717 */
1718 val &= ~PIPECONF_BPC_MASK;
1719 val |= pipeconf_val & PIPECONF_BPC_MASK;
1720 }
1721
1722 val &= ~TRANS_INTERLACE_MASK;
1723 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1724 if (HAS_PCH_IBX(dev_priv->dev) &&
1725 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1726 val |= TRANS_LEGACY_INTERLACED_ILK;
1727 else
1728 val |= TRANS_INTERLACED;
1729 else
1730 val |= TRANS_PROGRESSIVE;
1731
1732 I915_WRITE(reg, val | TRANS_ENABLE);
1733 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1734 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1735 }
1736
1737 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1738 enum transcoder cpu_transcoder)
1739 {
1740 u32 val, pipeconf_val;
1741
1742 /* PCH only available on ILK+ */
1743 BUG_ON(dev_priv->info->gen < 5);
1744
1745 /* FDI must be feeding us bits for PCH ports */
1746 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1747 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1748
1749 /* Workaround: set timing override bit. */
1750 val = I915_READ(_TRANSA_CHICKEN2);
1751 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1752 I915_WRITE(_TRANSA_CHICKEN2, val);
1753
1754 val = TRANS_ENABLE;
1755 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1756
1757 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1758 PIPECONF_INTERLACED_ILK)
1759 val |= TRANS_INTERLACED;
1760 else
1761 val |= TRANS_PROGRESSIVE;
1762
1763 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1764 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1765 DRM_ERROR("Failed to enable PCH transcoder\n");
1766 }
1767
1768 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1769 enum pipe pipe)
1770 {
1771 struct drm_device *dev = dev_priv->dev;
1772 uint32_t reg, val;
1773
1774 /* FDI relies on the transcoder */
1775 assert_fdi_tx_disabled(dev_priv, pipe);
1776 assert_fdi_rx_disabled(dev_priv, pipe);
1777
1778 /* Ports must be off as well */
1779 assert_pch_ports_disabled(dev_priv, pipe);
1780
1781 reg = TRANSCONF(pipe);
1782 val = I915_READ(reg);
1783 val &= ~TRANS_ENABLE;
1784 I915_WRITE(reg, val);
1785 /* wait for PCH transcoder off, transcoder state */
1786 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1787 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1788
1789 if (!HAS_PCH_IBX(dev)) {
1790 /* Workaround: Clear the timing override chicken bit again. */
1791 reg = TRANS_CHICKEN2(pipe);
1792 val = I915_READ(reg);
1793 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1794 I915_WRITE(reg, val);
1795 }
1796 }
1797
1798 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1799 {
1800 u32 val;
1801
1802 val = I915_READ(_TRANSACONF);
1803 val &= ~TRANS_ENABLE;
1804 I915_WRITE(_TRANSACONF, val);
1805 /* wait for PCH transcoder off, transcoder state */
1806 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1807 DRM_ERROR("Failed to disable PCH transcoder\n");
1808
1809 /* Workaround: clear timing override bit. */
1810 val = I915_READ(_TRANSA_CHICKEN2);
1811 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1812 I915_WRITE(_TRANSA_CHICKEN2, val);
1813 }
1814
1815 /**
1816 * intel_enable_pipe - enable a pipe, asserting requirements
1817 * @dev_priv: i915 private structure
1818 * @pipe: pipe to enable
1819 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1820 *
1821 * Enable @pipe, making sure that various hardware specific requirements
1822 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1823 *
1824 * @pipe should be %PIPE_A or %PIPE_B.
1825 *
1826 * Will wait until the pipe is actually running (i.e. first vblank) before
1827 * returning.
1828 */
1829 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1830 bool pch_port)
1831 {
1832 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1833 pipe);
1834 enum pipe pch_transcoder;
1835 int reg;
1836 u32 val;
1837
1838 if (HAS_PCH_LPT(dev_priv->dev))
1839 pch_transcoder = TRANSCODER_A;
1840 else
1841 pch_transcoder = pipe;
1842
1843 /*
1844 * A pipe without a PLL won't actually be able to drive bits from
1845 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1846 * need the check.
1847 */
1848 if (!HAS_PCH_SPLIT(dev_priv->dev))
1849 assert_pll_enabled(dev_priv, pipe);
1850 else {
1851 if (pch_port) {
1852 /* if driving the PCH, we need FDI enabled */
1853 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1854 assert_fdi_tx_pll_enabled(dev_priv,
1855 (enum pipe) cpu_transcoder);
1856 }
1857 /* FIXME: assert CPU port conditions for SNB+ */
1858 }
1859
1860 reg = PIPECONF(cpu_transcoder);
1861 val = I915_READ(reg);
1862 if (val & PIPECONF_ENABLE)
1863 return;
1864
1865 I915_WRITE(reg, val | PIPECONF_ENABLE);
1866 intel_wait_for_vblank(dev_priv->dev, pipe);
1867 }
1868
1869 /**
1870 * intel_disable_pipe - disable a pipe, asserting requirements
1871 * @dev_priv: i915 private structure
1872 * @pipe: pipe to disable
1873 *
1874 * Disable @pipe, making sure that various hardware specific requirements
1875 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1876 *
1877 * @pipe should be %PIPE_A or %PIPE_B.
1878 *
1879 * Will wait until the pipe has shut down before returning.
1880 */
1881 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1882 enum pipe pipe)
1883 {
1884 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1885 pipe);
1886 int reg;
1887 u32 val;
1888
1889 /*
1890 * Make sure planes won't keep trying to pump pixels to us,
1891 * or we might hang the display.
1892 */
1893 assert_planes_disabled(dev_priv, pipe);
1894 assert_sprites_disabled(dev_priv, pipe);
1895
1896 /* Don't disable pipe A or pipe A PLLs if needed */
1897 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1898 return;
1899
1900 reg = PIPECONF(cpu_transcoder);
1901 val = I915_READ(reg);
1902 if ((val & PIPECONF_ENABLE) == 0)
1903 return;
1904
1905 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1906 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1907 }
1908
1909 /*
1910 * Plane regs are double buffered, going from enabled->disabled needs a
1911 * trigger in order to latch. The display address reg provides this.
1912 */
1913 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1914 enum plane plane)
1915 {
1916 if (dev_priv->info->gen >= 4)
1917 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1918 else
1919 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1920 }
1921
1922 /**
1923 * intel_enable_plane - enable a display plane on a given pipe
1924 * @dev_priv: i915 private structure
1925 * @plane: plane to enable
1926 * @pipe: pipe being fed
1927 *
1928 * Enable @plane on @pipe, making sure that @pipe is running first.
1929 */
1930 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1931 enum plane plane, enum pipe pipe)
1932 {
1933 int reg;
1934 u32 val;
1935
1936 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1937 assert_pipe_enabled(dev_priv, pipe);
1938
1939 reg = DSPCNTR(plane);
1940 val = I915_READ(reg);
1941 if (val & DISPLAY_PLANE_ENABLE)
1942 return;
1943
1944 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1945 intel_flush_display_plane(dev_priv, plane);
1946 intel_wait_for_vblank(dev_priv->dev, pipe);
1947 }
1948
1949 /**
1950 * intel_disable_plane - disable a display plane
1951 * @dev_priv: i915 private structure
1952 * @plane: plane to disable
1953 * @pipe: pipe consuming the data
1954 *
1955 * Disable @plane; should be an independent operation.
1956 */
1957 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1958 enum plane plane, enum pipe pipe)
1959 {
1960 int reg;
1961 u32 val;
1962
1963 reg = DSPCNTR(plane);
1964 val = I915_READ(reg);
1965 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1966 return;
1967
1968 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1969 intel_flush_display_plane(dev_priv, plane);
1970 intel_wait_for_vblank(dev_priv->dev, pipe);
1971 }
1972
1973 static bool need_vtd_wa(struct drm_device *dev)
1974 {
1975 #ifdef CONFIG_INTEL_IOMMU
1976 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1977 return true;
1978 #endif
1979 return false;
1980 }
1981
1982 int
1983 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1984 struct drm_i915_gem_object *obj,
1985 struct intel_ring_buffer *pipelined)
1986 {
1987 struct drm_i915_private *dev_priv = dev->dev_private;
1988 u32 alignment;
1989 int ret;
1990
1991 switch (obj->tiling_mode) {
1992 case I915_TILING_NONE:
1993 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1994 alignment = 128 * 1024;
1995 else if (INTEL_INFO(dev)->gen >= 4)
1996 alignment = 4 * 1024;
1997 else
1998 alignment = 64 * 1024;
1999 break;
2000 case I915_TILING_X:
2001 /* pin() will align the object as required by fence */
2002 alignment = 0;
2003 break;
2004 case I915_TILING_Y:
2005 /* FIXME: Is this true? */
2006 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2007 return -EINVAL;
2008 default:
2009 BUG();
2010 }
2011
2012 /* Note that the w/a also requires 64 PTE of padding following the
2013 * bo. We currently fill all unused PTE with the shadow page and so
2014 * we should always have valid PTE following the scanout preventing
2015 * the VT-d warning.
2016 */
2017 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2018 alignment = 256 * 1024;
2019
2020 dev_priv->mm.interruptible = false;
2021 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2022 if (ret)
2023 goto err_interruptible;
2024
2025 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2026 * fence, whereas 965+ only requires a fence if using
2027 * framebuffer compression. For simplicity, we always install
2028 * a fence as the cost is not that onerous.
2029 */
2030 ret = i915_gem_object_get_fence(obj);
2031 if (ret)
2032 goto err_unpin;
2033
2034 i915_gem_object_pin_fence(obj);
2035
2036 dev_priv->mm.interruptible = true;
2037 return 0;
2038
2039 err_unpin:
2040 i915_gem_object_unpin(obj);
2041 err_interruptible:
2042 dev_priv->mm.interruptible = true;
2043 return ret;
2044 }
2045
2046 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2047 {
2048 i915_gem_object_unpin_fence(obj);
2049 i915_gem_object_unpin(obj);
2050 }
2051
2052 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2053 * is assumed to be a power-of-two. */
2054 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2055 unsigned int tiling_mode,
2056 unsigned int cpp,
2057 unsigned int pitch)
2058 {
2059 if (tiling_mode != I915_TILING_NONE) {
2060 unsigned int tile_rows, tiles;
2061
2062 tile_rows = *y / 8;
2063 *y %= 8;
2064
2065 tiles = *x / (512/cpp);
2066 *x %= 512/cpp;
2067
2068 return tile_rows * pitch * 8 + tiles * 4096;
2069 } else {
2070 unsigned int offset;
2071
2072 offset = *y * pitch + *x * cpp;
2073 *y = 0;
2074 *x = (offset & 4095) / cpp;
2075 return offset & -4096;
2076 }
2077 }
2078
2079 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2080 int x, int y)
2081 {
2082 struct drm_device *dev = crtc->dev;
2083 struct drm_i915_private *dev_priv = dev->dev_private;
2084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2085 struct intel_framebuffer *intel_fb;
2086 struct drm_i915_gem_object *obj;
2087 int plane = intel_crtc->plane;
2088 unsigned long linear_offset;
2089 u32 dspcntr;
2090 u32 reg;
2091
2092 switch (plane) {
2093 case 0:
2094 case 1:
2095 break;
2096 default:
2097 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2098 return -EINVAL;
2099 }
2100
2101 intel_fb = to_intel_framebuffer(fb);
2102 obj = intel_fb->obj;
2103
2104 reg = DSPCNTR(plane);
2105 dspcntr = I915_READ(reg);
2106 /* Mask out pixel format bits in case we change it */
2107 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2108 switch (fb->pixel_format) {
2109 case DRM_FORMAT_C8:
2110 dspcntr |= DISPPLANE_8BPP;
2111 break;
2112 case DRM_FORMAT_XRGB1555:
2113 case DRM_FORMAT_ARGB1555:
2114 dspcntr |= DISPPLANE_BGRX555;
2115 break;
2116 case DRM_FORMAT_RGB565:
2117 dspcntr |= DISPPLANE_BGRX565;
2118 break;
2119 case DRM_FORMAT_XRGB8888:
2120 case DRM_FORMAT_ARGB8888:
2121 dspcntr |= DISPPLANE_BGRX888;
2122 break;
2123 case DRM_FORMAT_XBGR8888:
2124 case DRM_FORMAT_ABGR8888:
2125 dspcntr |= DISPPLANE_RGBX888;
2126 break;
2127 case DRM_FORMAT_XRGB2101010:
2128 case DRM_FORMAT_ARGB2101010:
2129 dspcntr |= DISPPLANE_BGRX101010;
2130 break;
2131 case DRM_FORMAT_XBGR2101010:
2132 case DRM_FORMAT_ABGR2101010:
2133 dspcntr |= DISPPLANE_RGBX101010;
2134 break;
2135 default:
2136 BUG();
2137 }
2138
2139 if (INTEL_INFO(dev)->gen >= 4) {
2140 if (obj->tiling_mode != I915_TILING_NONE)
2141 dspcntr |= DISPPLANE_TILED;
2142 else
2143 dspcntr &= ~DISPPLANE_TILED;
2144 }
2145
2146 I915_WRITE(reg, dspcntr);
2147
2148 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2149
2150 if (INTEL_INFO(dev)->gen >= 4) {
2151 intel_crtc->dspaddr_offset =
2152 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2153 fb->bits_per_pixel / 8,
2154 fb->pitches[0]);
2155 linear_offset -= intel_crtc->dspaddr_offset;
2156 } else {
2157 intel_crtc->dspaddr_offset = linear_offset;
2158 }
2159
2160 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2161 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2162 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2163 if (INTEL_INFO(dev)->gen >= 4) {
2164 I915_MODIFY_DISPBASE(DSPSURF(plane),
2165 obj->gtt_offset + intel_crtc->dspaddr_offset);
2166 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2167 I915_WRITE(DSPLINOFF(plane), linear_offset);
2168 } else
2169 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2170 POSTING_READ(reg);
2171
2172 return 0;
2173 }
2174
2175 static int ironlake_update_plane(struct drm_crtc *crtc,
2176 struct drm_framebuffer *fb, int x, int y)
2177 {
2178 struct drm_device *dev = crtc->dev;
2179 struct drm_i915_private *dev_priv = dev->dev_private;
2180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2181 struct intel_framebuffer *intel_fb;
2182 struct drm_i915_gem_object *obj;
2183 int plane = intel_crtc->plane;
2184 unsigned long linear_offset;
2185 u32 dspcntr;
2186 u32 reg;
2187
2188 switch (plane) {
2189 case 0:
2190 case 1:
2191 case 2:
2192 break;
2193 default:
2194 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2195 return -EINVAL;
2196 }
2197
2198 intel_fb = to_intel_framebuffer(fb);
2199 obj = intel_fb->obj;
2200
2201 reg = DSPCNTR(plane);
2202 dspcntr = I915_READ(reg);
2203 /* Mask out pixel format bits in case we change it */
2204 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2205 switch (fb->pixel_format) {
2206 case DRM_FORMAT_C8:
2207 dspcntr |= DISPPLANE_8BPP;
2208 break;
2209 case DRM_FORMAT_RGB565:
2210 dspcntr |= DISPPLANE_BGRX565;
2211 break;
2212 case DRM_FORMAT_XRGB8888:
2213 case DRM_FORMAT_ARGB8888:
2214 dspcntr |= DISPPLANE_BGRX888;
2215 break;
2216 case DRM_FORMAT_XBGR8888:
2217 case DRM_FORMAT_ABGR8888:
2218 dspcntr |= DISPPLANE_RGBX888;
2219 break;
2220 case DRM_FORMAT_XRGB2101010:
2221 case DRM_FORMAT_ARGB2101010:
2222 dspcntr |= DISPPLANE_BGRX101010;
2223 break;
2224 case DRM_FORMAT_XBGR2101010:
2225 case DRM_FORMAT_ABGR2101010:
2226 dspcntr |= DISPPLANE_RGBX101010;
2227 break;
2228 default:
2229 BUG();
2230 }
2231
2232 if (obj->tiling_mode != I915_TILING_NONE)
2233 dspcntr |= DISPPLANE_TILED;
2234 else
2235 dspcntr &= ~DISPPLANE_TILED;
2236
2237 /* must disable */
2238 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2239
2240 I915_WRITE(reg, dspcntr);
2241
2242 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2243 intel_crtc->dspaddr_offset =
2244 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2245 fb->bits_per_pixel / 8,
2246 fb->pitches[0]);
2247 linear_offset -= intel_crtc->dspaddr_offset;
2248
2249 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2250 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2251 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2252 I915_MODIFY_DISPBASE(DSPSURF(plane),
2253 obj->gtt_offset + intel_crtc->dspaddr_offset);
2254 if (IS_HASWELL(dev)) {
2255 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2256 } else {
2257 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2258 I915_WRITE(DSPLINOFF(plane), linear_offset);
2259 }
2260 POSTING_READ(reg);
2261
2262 return 0;
2263 }
2264
2265 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2266 static int
2267 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2268 int x, int y, enum mode_set_atomic state)
2269 {
2270 struct drm_device *dev = crtc->dev;
2271 struct drm_i915_private *dev_priv = dev->dev_private;
2272
2273 if (dev_priv->display.disable_fbc)
2274 dev_priv->display.disable_fbc(dev);
2275 intel_increase_pllclock(crtc);
2276
2277 return dev_priv->display.update_plane(crtc, fb, x, y);
2278 }
2279
2280 void intel_display_handle_reset(struct drm_device *dev)
2281 {
2282 struct drm_i915_private *dev_priv = dev->dev_private;
2283 struct drm_crtc *crtc;
2284
2285 /*
2286 * Flips in the rings have been nuked by the reset,
2287 * so complete all pending flips so that user space
2288 * will get its events and not get stuck.
2289 *
2290 * Also update the base address of all primary
2291 * planes to the the last fb to make sure we're
2292 * showing the correct fb after a reset.
2293 *
2294 * Need to make two loops over the crtcs so that we
2295 * don't try to grab a crtc mutex before the
2296 * pending_flip_queue really got woken up.
2297 */
2298
2299 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2301 enum plane plane = intel_crtc->plane;
2302
2303 intel_prepare_page_flip(dev, plane);
2304 intel_finish_page_flip_plane(dev, plane);
2305 }
2306
2307 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2309
2310 mutex_lock(&crtc->mutex);
2311 if (intel_crtc->active)
2312 dev_priv->display.update_plane(crtc, crtc->fb,
2313 crtc->x, crtc->y);
2314 mutex_unlock(&crtc->mutex);
2315 }
2316 }
2317
2318 static int
2319 intel_finish_fb(struct drm_framebuffer *old_fb)
2320 {
2321 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2322 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2323 bool was_interruptible = dev_priv->mm.interruptible;
2324 int ret;
2325
2326 /* Big Hammer, we also need to ensure that any pending
2327 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2328 * current scanout is retired before unpinning the old
2329 * framebuffer.
2330 *
2331 * This should only fail upon a hung GPU, in which case we
2332 * can safely continue.
2333 */
2334 dev_priv->mm.interruptible = false;
2335 ret = i915_gem_object_finish_gpu(obj);
2336 dev_priv->mm.interruptible = was_interruptible;
2337
2338 return ret;
2339 }
2340
2341 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2342 {
2343 struct drm_device *dev = crtc->dev;
2344 struct drm_i915_master_private *master_priv;
2345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2346
2347 if (!dev->primary->master)
2348 return;
2349
2350 master_priv = dev->primary->master->driver_priv;
2351 if (!master_priv->sarea_priv)
2352 return;
2353
2354 switch (intel_crtc->pipe) {
2355 case 0:
2356 master_priv->sarea_priv->pipeA_x = x;
2357 master_priv->sarea_priv->pipeA_y = y;
2358 break;
2359 case 1:
2360 master_priv->sarea_priv->pipeB_x = x;
2361 master_priv->sarea_priv->pipeB_y = y;
2362 break;
2363 default:
2364 break;
2365 }
2366 }
2367
2368 static int
2369 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2370 struct drm_framebuffer *fb)
2371 {
2372 struct drm_device *dev = crtc->dev;
2373 struct drm_i915_private *dev_priv = dev->dev_private;
2374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2375 struct drm_framebuffer *old_fb;
2376 int ret;
2377
2378 /* no fb bound */
2379 if (!fb) {
2380 DRM_ERROR("No FB bound\n");
2381 return 0;
2382 }
2383
2384 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2385 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2386 intel_crtc->plane,
2387 INTEL_INFO(dev)->num_pipes);
2388 return -EINVAL;
2389 }
2390
2391 mutex_lock(&dev->struct_mutex);
2392 ret = intel_pin_and_fence_fb_obj(dev,
2393 to_intel_framebuffer(fb)->obj,
2394 NULL);
2395 if (ret != 0) {
2396 mutex_unlock(&dev->struct_mutex);
2397 DRM_ERROR("pin & fence failed\n");
2398 return ret;
2399 }
2400
2401 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2402 if (ret) {
2403 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2404 mutex_unlock(&dev->struct_mutex);
2405 DRM_ERROR("failed to update base address\n");
2406 return ret;
2407 }
2408
2409 old_fb = crtc->fb;
2410 crtc->fb = fb;
2411 crtc->x = x;
2412 crtc->y = y;
2413
2414 if (old_fb) {
2415 intel_wait_for_vblank(dev, intel_crtc->pipe);
2416 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2417 }
2418
2419 intel_update_fbc(dev);
2420 mutex_unlock(&dev->struct_mutex);
2421
2422 intel_crtc_update_sarea_pos(crtc, x, y);
2423
2424 return 0;
2425 }
2426
2427 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2428 {
2429 struct drm_device *dev = crtc->dev;
2430 struct drm_i915_private *dev_priv = dev->dev_private;
2431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2432 int pipe = intel_crtc->pipe;
2433 u32 reg, temp;
2434
2435 /* enable normal train */
2436 reg = FDI_TX_CTL(pipe);
2437 temp = I915_READ(reg);
2438 if (IS_IVYBRIDGE(dev)) {
2439 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2440 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2441 } else {
2442 temp &= ~FDI_LINK_TRAIN_NONE;
2443 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2444 }
2445 I915_WRITE(reg, temp);
2446
2447 reg = FDI_RX_CTL(pipe);
2448 temp = I915_READ(reg);
2449 if (HAS_PCH_CPT(dev)) {
2450 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2451 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2452 } else {
2453 temp &= ~FDI_LINK_TRAIN_NONE;
2454 temp |= FDI_LINK_TRAIN_NONE;
2455 }
2456 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2457
2458 /* wait one idle pattern time */
2459 POSTING_READ(reg);
2460 udelay(1000);
2461
2462 /* IVB wants error correction enabled */
2463 if (IS_IVYBRIDGE(dev))
2464 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2465 FDI_FE_ERRC_ENABLE);
2466 }
2467
2468 static void ivb_modeset_global_resources(struct drm_device *dev)
2469 {
2470 struct drm_i915_private *dev_priv = dev->dev_private;
2471 struct intel_crtc *pipe_B_crtc =
2472 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2473 struct intel_crtc *pipe_C_crtc =
2474 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2475 uint32_t temp;
2476
2477 /* When everything is off disable fdi C so that we could enable fdi B
2478 * with all lanes. XXX: This misses the case where a pipe is not using
2479 * any pch resources and so doesn't need any fdi lanes. */
2480 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2481 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2482 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2483
2484 temp = I915_READ(SOUTH_CHICKEN1);
2485 temp &= ~FDI_BC_BIFURCATION_SELECT;
2486 DRM_DEBUG_KMS("disabling fdi C rx\n");
2487 I915_WRITE(SOUTH_CHICKEN1, temp);
2488 }
2489 }
2490
2491 /* The FDI link training functions for ILK/Ibexpeak. */
2492 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2493 {
2494 struct drm_device *dev = crtc->dev;
2495 struct drm_i915_private *dev_priv = dev->dev_private;
2496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2497 int pipe = intel_crtc->pipe;
2498 int plane = intel_crtc->plane;
2499 u32 reg, temp, tries;
2500
2501 /* FDI needs bits from pipe & plane first */
2502 assert_pipe_enabled(dev_priv, pipe);
2503 assert_plane_enabled(dev_priv, plane);
2504
2505 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2506 for train result */
2507 reg = FDI_RX_IMR(pipe);
2508 temp = I915_READ(reg);
2509 temp &= ~FDI_RX_SYMBOL_LOCK;
2510 temp &= ~FDI_RX_BIT_LOCK;
2511 I915_WRITE(reg, temp);
2512 I915_READ(reg);
2513 udelay(150);
2514
2515 /* enable CPU FDI TX and PCH FDI RX */
2516 reg = FDI_TX_CTL(pipe);
2517 temp = I915_READ(reg);
2518 temp &= ~(7 << 19);
2519 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2520 temp &= ~FDI_LINK_TRAIN_NONE;
2521 temp |= FDI_LINK_TRAIN_PATTERN_1;
2522 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2523
2524 reg = FDI_RX_CTL(pipe);
2525 temp = I915_READ(reg);
2526 temp &= ~FDI_LINK_TRAIN_NONE;
2527 temp |= FDI_LINK_TRAIN_PATTERN_1;
2528 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2529
2530 POSTING_READ(reg);
2531 udelay(150);
2532
2533 /* Ironlake workaround, enable clock pointer after FDI enable*/
2534 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2535 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2536 FDI_RX_PHASE_SYNC_POINTER_EN);
2537
2538 reg = FDI_RX_IIR(pipe);
2539 for (tries = 0; tries < 5; tries++) {
2540 temp = I915_READ(reg);
2541 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2542
2543 if ((temp & FDI_RX_BIT_LOCK)) {
2544 DRM_DEBUG_KMS("FDI train 1 done.\n");
2545 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2546 break;
2547 }
2548 }
2549 if (tries == 5)
2550 DRM_ERROR("FDI train 1 fail!\n");
2551
2552 /* Train 2 */
2553 reg = FDI_TX_CTL(pipe);
2554 temp = I915_READ(reg);
2555 temp &= ~FDI_LINK_TRAIN_NONE;
2556 temp |= FDI_LINK_TRAIN_PATTERN_2;
2557 I915_WRITE(reg, temp);
2558
2559 reg = FDI_RX_CTL(pipe);
2560 temp = I915_READ(reg);
2561 temp &= ~FDI_LINK_TRAIN_NONE;
2562 temp |= FDI_LINK_TRAIN_PATTERN_2;
2563 I915_WRITE(reg, temp);
2564
2565 POSTING_READ(reg);
2566 udelay(150);
2567
2568 reg = FDI_RX_IIR(pipe);
2569 for (tries = 0; tries < 5; tries++) {
2570 temp = I915_READ(reg);
2571 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2572
2573 if (temp & FDI_RX_SYMBOL_LOCK) {
2574 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2575 DRM_DEBUG_KMS("FDI train 2 done.\n");
2576 break;
2577 }
2578 }
2579 if (tries == 5)
2580 DRM_ERROR("FDI train 2 fail!\n");
2581
2582 DRM_DEBUG_KMS("FDI train done\n");
2583
2584 }
2585
2586 static const int snb_b_fdi_train_param[] = {
2587 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2588 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2589 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2590 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2591 };
2592
2593 /* The FDI link training functions for SNB/Cougarpoint. */
2594 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2595 {
2596 struct drm_device *dev = crtc->dev;
2597 struct drm_i915_private *dev_priv = dev->dev_private;
2598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2599 int pipe = intel_crtc->pipe;
2600 u32 reg, temp, i, retry;
2601
2602 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2603 for train result */
2604 reg = FDI_RX_IMR(pipe);
2605 temp = I915_READ(reg);
2606 temp &= ~FDI_RX_SYMBOL_LOCK;
2607 temp &= ~FDI_RX_BIT_LOCK;
2608 I915_WRITE(reg, temp);
2609
2610 POSTING_READ(reg);
2611 udelay(150);
2612
2613 /* enable CPU FDI TX and PCH FDI RX */
2614 reg = FDI_TX_CTL(pipe);
2615 temp = I915_READ(reg);
2616 temp &= ~(7 << 19);
2617 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2618 temp &= ~FDI_LINK_TRAIN_NONE;
2619 temp |= FDI_LINK_TRAIN_PATTERN_1;
2620 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2621 /* SNB-B */
2622 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2623 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2624
2625 I915_WRITE(FDI_RX_MISC(pipe),
2626 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2627
2628 reg = FDI_RX_CTL(pipe);
2629 temp = I915_READ(reg);
2630 if (HAS_PCH_CPT(dev)) {
2631 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2632 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2633 } else {
2634 temp &= ~FDI_LINK_TRAIN_NONE;
2635 temp |= FDI_LINK_TRAIN_PATTERN_1;
2636 }
2637 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2638
2639 POSTING_READ(reg);
2640 udelay(150);
2641
2642 for (i = 0; i < 4; i++) {
2643 reg = FDI_TX_CTL(pipe);
2644 temp = I915_READ(reg);
2645 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2646 temp |= snb_b_fdi_train_param[i];
2647 I915_WRITE(reg, temp);
2648
2649 POSTING_READ(reg);
2650 udelay(500);
2651
2652 for (retry = 0; retry < 5; retry++) {
2653 reg = FDI_RX_IIR(pipe);
2654 temp = I915_READ(reg);
2655 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2656 if (temp & FDI_RX_BIT_LOCK) {
2657 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2658 DRM_DEBUG_KMS("FDI train 1 done.\n");
2659 break;
2660 }
2661 udelay(50);
2662 }
2663 if (retry < 5)
2664 break;
2665 }
2666 if (i == 4)
2667 DRM_ERROR("FDI train 1 fail!\n");
2668
2669 /* Train 2 */
2670 reg = FDI_TX_CTL(pipe);
2671 temp = I915_READ(reg);
2672 temp &= ~FDI_LINK_TRAIN_NONE;
2673 temp |= FDI_LINK_TRAIN_PATTERN_2;
2674 if (IS_GEN6(dev)) {
2675 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2676 /* SNB-B */
2677 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2678 }
2679 I915_WRITE(reg, temp);
2680
2681 reg = FDI_RX_CTL(pipe);
2682 temp = I915_READ(reg);
2683 if (HAS_PCH_CPT(dev)) {
2684 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2685 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2686 } else {
2687 temp &= ~FDI_LINK_TRAIN_NONE;
2688 temp |= FDI_LINK_TRAIN_PATTERN_2;
2689 }
2690 I915_WRITE(reg, temp);
2691
2692 POSTING_READ(reg);
2693 udelay(150);
2694
2695 for (i = 0; i < 4; i++) {
2696 reg = FDI_TX_CTL(pipe);
2697 temp = I915_READ(reg);
2698 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2699 temp |= snb_b_fdi_train_param[i];
2700 I915_WRITE(reg, temp);
2701
2702 POSTING_READ(reg);
2703 udelay(500);
2704
2705 for (retry = 0; retry < 5; retry++) {
2706 reg = FDI_RX_IIR(pipe);
2707 temp = I915_READ(reg);
2708 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2709 if (temp & FDI_RX_SYMBOL_LOCK) {
2710 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2711 DRM_DEBUG_KMS("FDI train 2 done.\n");
2712 break;
2713 }
2714 udelay(50);
2715 }
2716 if (retry < 5)
2717 break;
2718 }
2719 if (i == 4)
2720 DRM_ERROR("FDI train 2 fail!\n");
2721
2722 DRM_DEBUG_KMS("FDI train done.\n");
2723 }
2724
2725 /* Manual link training for Ivy Bridge A0 parts */
2726 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2727 {
2728 struct drm_device *dev = crtc->dev;
2729 struct drm_i915_private *dev_priv = dev->dev_private;
2730 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2731 int pipe = intel_crtc->pipe;
2732 u32 reg, temp, i;
2733
2734 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2735 for train result */
2736 reg = FDI_RX_IMR(pipe);
2737 temp = I915_READ(reg);
2738 temp &= ~FDI_RX_SYMBOL_LOCK;
2739 temp &= ~FDI_RX_BIT_LOCK;
2740 I915_WRITE(reg, temp);
2741
2742 POSTING_READ(reg);
2743 udelay(150);
2744
2745 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2746 I915_READ(FDI_RX_IIR(pipe)));
2747
2748 /* enable CPU FDI TX and PCH FDI RX */
2749 reg = FDI_TX_CTL(pipe);
2750 temp = I915_READ(reg);
2751 temp &= ~(7 << 19);
2752 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2753 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2754 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2755 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2756 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2757 temp |= FDI_COMPOSITE_SYNC;
2758 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2759
2760 I915_WRITE(FDI_RX_MISC(pipe),
2761 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2762
2763 reg = FDI_RX_CTL(pipe);
2764 temp = I915_READ(reg);
2765 temp &= ~FDI_LINK_TRAIN_AUTO;
2766 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2767 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2768 temp |= FDI_COMPOSITE_SYNC;
2769 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2770
2771 POSTING_READ(reg);
2772 udelay(150);
2773
2774 for (i = 0; i < 4; i++) {
2775 reg = FDI_TX_CTL(pipe);
2776 temp = I915_READ(reg);
2777 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2778 temp |= snb_b_fdi_train_param[i];
2779 I915_WRITE(reg, temp);
2780
2781 POSTING_READ(reg);
2782 udelay(500);
2783
2784 reg = FDI_RX_IIR(pipe);
2785 temp = I915_READ(reg);
2786 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2787
2788 if (temp & FDI_RX_BIT_LOCK ||
2789 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2790 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2791 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2792 break;
2793 }
2794 }
2795 if (i == 4)
2796 DRM_ERROR("FDI train 1 fail!\n");
2797
2798 /* Train 2 */
2799 reg = FDI_TX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2802 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2803 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2804 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2805 I915_WRITE(reg, temp);
2806
2807 reg = FDI_RX_CTL(pipe);
2808 temp = I915_READ(reg);
2809 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2810 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2811 I915_WRITE(reg, temp);
2812
2813 POSTING_READ(reg);
2814 udelay(150);
2815
2816 for (i = 0; i < 4; i++) {
2817 reg = FDI_TX_CTL(pipe);
2818 temp = I915_READ(reg);
2819 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2820 temp |= snb_b_fdi_train_param[i];
2821 I915_WRITE(reg, temp);
2822
2823 POSTING_READ(reg);
2824 udelay(500);
2825
2826 reg = FDI_RX_IIR(pipe);
2827 temp = I915_READ(reg);
2828 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2829
2830 if (temp & FDI_RX_SYMBOL_LOCK) {
2831 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2832 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2833 break;
2834 }
2835 }
2836 if (i == 4)
2837 DRM_ERROR("FDI train 2 fail!\n");
2838
2839 DRM_DEBUG_KMS("FDI train done.\n");
2840 }
2841
2842 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2843 {
2844 struct drm_device *dev = intel_crtc->base.dev;
2845 struct drm_i915_private *dev_priv = dev->dev_private;
2846 int pipe = intel_crtc->pipe;
2847 u32 reg, temp;
2848
2849
2850 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2851 reg = FDI_RX_CTL(pipe);
2852 temp = I915_READ(reg);
2853 temp &= ~((0x7 << 19) | (0x7 << 16));
2854 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2855 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2856 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2857
2858 POSTING_READ(reg);
2859 udelay(200);
2860
2861 /* Switch from Rawclk to PCDclk */
2862 temp = I915_READ(reg);
2863 I915_WRITE(reg, temp | FDI_PCDCLK);
2864
2865 POSTING_READ(reg);
2866 udelay(200);
2867
2868 /* Enable CPU FDI TX PLL, always on for Ironlake */
2869 reg = FDI_TX_CTL(pipe);
2870 temp = I915_READ(reg);
2871 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2872 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2873
2874 POSTING_READ(reg);
2875 udelay(100);
2876 }
2877 }
2878
2879 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2880 {
2881 struct drm_device *dev = intel_crtc->base.dev;
2882 struct drm_i915_private *dev_priv = dev->dev_private;
2883 int pipe = intel_crtc->pipe;
2884 u32 reg, temp;
2885
2886 /* Switch from PCDclk to Rawclk */
2887 reg = FDI_RX_CTL(pipe);
2888 temp = I915_READ(reg);
2889 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2890
2891 /* Disable CPU FDI TX PLL */
2892 reg = FDI_TX_CTL(pipe);
2893 temp = I915_READ(reg);
2894 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2895
2896 POSTING_READ(reg);
2897 udelay(100);
2898
2899 reg = FDI_RX_CTL(pipe);
2900 temp = I915_READ(reg);
2901 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2902
2903 /* Wait for the clocks to turn off. */
2904 POSTING_READ(reg);
2905 udelay(100);
2906 }
2907
2908 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2909 {
2910 struct drm_device *dev = crtc->dev;
2911 struct drm_i915_private *dev_priv = dev->dev_private;
2912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2913 int pipe = intel_crtc->pipe;
2914 u32 reg, temp;
2915
2916 /* disable CPU FDI tx and PCH FDI rx */
2917 reg = FDI_TX_CTL(pipe);
2918 temp = I915_READ(reg);
2919 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2920 POSTING_READ(reg);
2921
2922 reg = FDI_RX_CTL(pipe);
2923 temp = I915_READ(reg);
2924 temp &= ~(0x7 << 16);
2925 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2926 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2927
2928 POSTING_READ(reg);
2929 udelay(100);
2930
2931 /* Ironlake workaround, disable clock pointer after downing FDI */
2932 if (HAS_PCH_IBX(dev)) {
2933 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2934 }
2935
2936 /* still set train pattern 1 */
2937 reg = FDI_TX_CTL(pipe);
2938 temp = I915_READ(reg);
2939 temp &= ~FDI_LINK_TRAIN_NONE;
2940 temp |= FDI_LINK_TRAIN_PATTERN_1;
2941 I915_WRITE(reg, temp);
2942
2943 reg = FDI_RX_CTL(pipe);
2944 temp = I915_READ(reg);
2945 if (HAS_PCH_CPT(dev)) {
2946 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2947 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2948 } else {
2949 temp &= ~FDI_LINK_TRAIN_NONE;
2950 temp |= FDI_LINK_TRAIN_PATTERN_1;
2951 }
2952 /* BPC in FDI rx is consistent with that in PIPECONF */
2953 temp &= ~(0x07 << 16);
2954 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2955 I915_WRITE(reg, temp);
2956
2957 POSTING_READ(reg);
2958 udelay(100);
2959 }
2960
2961 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2962 {
2963 struct drm_device *dev = crtc->dev;
2964 struct drm_i915_private *dev_priv = dev->dev_private;
2965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2966 unsigned long flags;
2967 bool pending;
2968
2969 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2970 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2971 return false;
2972
2973 spin_lock_irqsave(&dev->event_lock, flags);
2974 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2975 spin_unlock_irqrestore(&dev->event_lock, flags);
2976
2977 return pending;
2978 }
2979
2980 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2981 {
2982 struct drm_device *dev = crtc->dev;
2983 struct drm_i915_private *dev_priv = dev->dev_private;
2984
2985 if (crtc->fb == NULL)
2986 return;
2987
2988 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2989
2990 wait_event(dev_priv->pending_flip_queue,
2991 !intel_crtc_has_pending_flip(crtc));
2992
2993 mutex_lock(&dev->struct_mutex);
2994 intel_finish_fb(crtc->fb);
2995 mutex_unlock(&dev->struct_mutex);
2996 }
2997
2998 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2999 {
3000 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3001 }
3002
3003 /* Program iCLKIP clock to the desired frequency */
3004 static void lpt_program_iclkip(struct drm_crtc *crtc)
3005 {
3006 struct drm_device *dev = crtc->dev;
3007 struct drm_i915_private *dev_priv = dev->dev_private;
3008 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3009 u32 temp;
3010
3011 mutex_lock(&dev_priv->dpio_lock);
3012
3013 /* It is necessary to ungate the pixclk gate prior to programming
3014 * the divisors, and gate it back when it is done.
3015 */
3016 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3017
3018 /* Disable SSCCTL */
3019 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3020 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3021 SBI_SSCCTL_DISABLE,
3022 SBI_ICLK);
3023
3024 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3025 if (crtc->mode.clock == 20000) {
3026 auxdiv = 1;
3027 divsel = 0x41;
3028 phaseinc = 0x20;
3029 } else {
3030 /* The iCLK virtual clock root frequency is in MHz,
3031 * but the crtc->mode.clock in in KHz. To get the divisors,
3032 * it is necessary to divide one by another, so we
3033 * convert the virtual clock precision to KHz here for higher
3034 * precision.
3035 */
3036 u32 iclk_virtual_root_freq = 172800 * 1000;
3037 u32 iclk_pi_range = 64;
3038 u32 desired_divisor, msb_divisor_value, pi_value;
3039
3040 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3041 msb_divisor_value = desired_divisor / iclk_pi_range;
3042 pi_value = desired_divisor % iclk_pi_range;
3043
3044 auxdiv = 0;
3045 divsel = msb_divisor_value - 2;
3046 phaseinc = pi_value;
3047 }
3048
3049 /* This should not happen with any sane values */
3050 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3051 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3052 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3053 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3054
3055 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3056 crtc->mode.clock,
3057 auxdiv,
3058 divsel,
3059 phasedir,
3060 phaseinc);
3061
3062 /* Program SSCDIVINTPHASE6 */
3063 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3064 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3065 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3066 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3067 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3068 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3069 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3070 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3071
3072 /* Program SSCAUXDIV */
3073 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3074 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3075 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3076 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3077
3078 /* Enable modulator and associated divider */
3079 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3080 temp &= ~SBI_SSCCTL_DISABLE;
3081 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3082
3083 /* Wait for initialization time */
3084 udelay(24);
3085
3086 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3087
3088 mutex_unlock(&dev_priv->dpio_lock);
3089 }
3090
3091 /*
3092 * Enable PCH resources required for PCH ports:
3093 * - PCH PLLs
3094 * - FDI training & RX/TX
3095 * - update transcoder timings
3096 * - DP transcoding bits
3097 * - transcoder
3098 */
3099 static void ironlake_pch_enable(struct drm_crtc *crtc)
3100 {
3101 struct drm_device *dev = crtc->dev;
3102 struct drm_i915_private *dev_priv = dev->dev_private;
3103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3104 int pipe = intel_crtc->pipe;
3105 u32 reg, temp;
3106
3107 assert_transcoder_disabled(dev_priv, pipe);
3108
3109 /* Write the TU size bits before fdi link training, so that error
3110 * detection works. */
3111 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3112 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3113
3114 /* For PCH output, training FDI link */
3115 dev_priv->display.fdi_link_train(crtc);
3116
3117 /* XXX: pch pll's can be enabled any time before we enable the PCH
3118 * transcoder, and we actually should do this to not upset any PCH
3119 * transcoder that already use the clock when we share it.
3120 *
3121 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3122 * unconditionally resets the pll - we need that to have the right LVDS
3123 * enable sequence. */
3124 ironlake_enable_pch_pll(intel_crtc);
3125
3126 if (HAS_PCH_CPT(dev)) {
3127 u32 sel;
3128
3129 temp = I915_READ(PCH_DPLL_SEL);
3130 switch (pipe) {
3131 default:
3132 case 0:
3133 temp |= TRANSA_DPLL_ENABLE;
3134 sel = TRANSA_DPLLB_SEL;
3135 break;
3136 case 1:
3137 temp |= TRANSB_DPLL_ENABLE;
3138 sel = TRANSB_DPLLB_SEL;
3139 break;
3140 case 2:
3141 temp |= TRANSC_DPLL_ENABLE;
3142 sel = TRANSC_DPLLB_SEL;
3143 break;
3144 }
3145 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3146 temp |= sel;
3147 else
3148 temp &= ~sel;
3149 I915_WRITE(PCH_DPLL_SEL, temp);
3150 }
3151
3152 /* set transcoder timing, panel must allow it */
3153 assert_panel_unlocked(dev_priv, pipe);
3154 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3155 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3156 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3157
3158 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3159 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3160 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3161 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3162
3163 intel_fdi_normal_train(crtc);
3164
3165 /* For PCH DP, enable TRANS_DP_CTL */
3166 if (HAS_PCH_CPT(dev) &&
3167 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3168 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3169 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3170 reg = TRANS_DP_CTL(pipe);
3171 temp = I915_READ(reg);
3172 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3173 TRANS_DP_SYNC_MASK |
3174 TRANS_DP_BPC_MASK);
3175 temp |= (TRANS_DP_OUTPUT_ENABLE |
3176 TRANS_DP_ENH_FRAMING);
3177 temp |= bpc << 9; /* same format but at 11:9 */
3178
3179 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3180 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3181 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3182 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3183
3184 switch (intel_trans_dp_port_sel(crtc)) {
3185 case PCH_DP_B:
3186 temp |= TRANS_DP_PORT_SEL_B;
3187 break;
3188 case PCH_DP_C:
3189 temp |= TRANS_DP_PORT_SEL_C;
3190 break;
3191 case PCH_DP_D:
3192 temp |= TRANS_DP_PORT_SEL_D;
3193 break;
3194 default:
3195 BUG();
3196 }
3197
3198 I915_WRITE(reg, temp);
3199 }
3200
3201 ironlake_enable_pch_transcoder(dev_priv, pipe);
3202 }
3203
3204 static void lpt_pch_enable(struct drm_crtc *crtc)
3205 {
3206 struct drm_device *dev = crtc->dev;
3207 struct drm_i915_private *dev_priv = dev->dev_private;
3208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3209 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3210
3211 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3212
3213 lpt_program_iclkip(crtc);
3214
3215 /* Set transcoder timing. */
3216 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3217 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3218 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
3219
3220 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3221 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3222 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3223 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3224
3225 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3226 }
3227
3228 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3229 {
3230 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3231
3232 if (pll == NULL)
3233 return;
3234
3235 if (pll->refcount == 0) {
3236 WARN(1, "bad PCH PLL refcount\n");
3237 return;
3238 }
3239
3240 --pll->refcount;
3241 intel_crtc->pch_pll = NULL;
3242 }
3243
3244 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3245 {
3246 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3247 struct intel_pch_pll *pll;
3248 int i;
3249
3250 pll = intel_crtc->pch_pll;
3251 if (pll) {
3252 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3253 intel_crtc->base.base.id, pll->pll_reg);
3254 goto prepare;
3255 }
3256
3257 if (HAS_PCH_IBX(dev_priv->dev)) {
3258 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3259 i = intel_crtc->pipe;
3260 pll = &dev_priv->pch_plls[i];
3261
3262 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3263 intel_crtc->base.base.id, pll->pll_reg);
3264
3265 goto found;
3266 }
3267
3268 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3269 pll = &dev_priv->pch_plls[i];
3270
3271 /* Only want to check enabled timings first */
3272 if (pll->refcount == 0)
3273 continue;
3274
3275 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3276 fp == I915_READ(pll->fp0_reg)) {
3277 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3278 intel_crtc->base.base.id,
3279 pll->pll_reg, pll->refcount, pll->active);
3280
3281 goto found;
3282 }
3283 }
3284
3285 /* Ok no matching timings, maybe there's a free one? */
3286 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3287 pll = &dev_priv->pch_plls[i];
3288 if (pll->refcount == 0) {
3289 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3290 intel_crtc->base.base.id, pll->pll_reg);
3291 goto found;
3292 }
3293 }
3294
3295 return NULL;
3296
3297 found:
3298 intel_crtc->pch_pll = pll;
3299 pll->refcount++;
3300 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3301 prepare: /* separate function? */
3302 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3303
3304 /* Wait for the clocks to stabilize before rewriting the regs */
3305 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3306 POSTING_READ(pll->pll_reg);
3307 udelay(150);
3308
3309 I915_WRITE(pll->fp0_reg, fp);
3310 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3311 pll->on = false;
3312 return pll;
3313 }
3314
3315 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3316 {
3317 struct drm_i915_private *dev_priv = dev->dev_private;
3318 int dslreg = PIPEDSL(pipe);
3319 u32 temp;
3320
3321 temp = I915_READ(dslreg);
3322 udelay(500);
3323 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3324 if (wait_for(I915_READ(dslreg) != temp, 5))
3325 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3326 }
3327 }
3328
3329 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3330 {
3331 struct drm_device *dev = crtc->dev;
3332 struct drm_i915_private *dev_priv = dev->dev_private;
3333 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3334 struct intel_encoder *encoder;
3335 int pipe = intel_crtc->pipe;
3336 int plane = intel_crtc->plane;
3337 u32 temp;
3338
3339 WARN_ON(!crtc->enabled);
3340
3341 if (intel_crtc->active)
3342 return;
3343
3344 intel_crtc->active = true;
3345 intel_update_watermarks(dev);
3346
3347 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3348 temp = I915_READ(PCH_LVDS);
3349 if ((temp & LVDS_PORT_EN) == 0)
3350 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3351 }
3352
3353
3354 if (intel_crtc->config.has_pch_encoder) {
3355 /* Note: FDI PLL enabling _must_ be done before we enable the
3356 * cpu pipes, hence this is separate from all the other fdi/pch
3357 * enabling. */
3358 ironlake_fdi_pll_enable(intel_crtc);
3359 } else {
3360 assert_fdi_tx_disabled(dev_priv, pipe);
3361 assert_fdi_rx_disabled(dev_priv, pipe);
3362 }
3363
3364 for_each_encoder_on_crtc(dev, crtc, encoder)
3365 if (encoder->pre_enable)
3366 encoder->pre_enable(encoder);
3367
3368 /* Enable panel fitting for LVDS */
3369 if (dev_priv->pch_pf_size &&
3370 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3371 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3372 /* Force use of hard-coded filter coefficients
3373 * as some pre-programmed values are broken,
3374 * e.g. x201.
3375 */
3376 if (IS_IVYBRIDGE(dev))
3377 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3378 PF_PIPE_SEL_IVB(pipe));
3379 else
3380 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3381 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3382 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3383 }
3384
3385 /*
3386 * On ILK+ LUT must be loaded before the pipe is running but with
3387 * clocks enabled
3388 */
3389 intel_crtc_load_lut(crtc);
3390
3391 intel_enable_pipe(dev_priv, pipe,
3392 intel_crtc->config.has_pch_encoder);
3393 intel_enable_plane(dev_priv, plane, pipe);
3394
3395 if (intel_crtc->config.has_pch_encoder)
3396 ironlake_pch_enable(crtc);
3397
3398 mutex_lock(&dev->struct_mutex);
3399 intel_update_fbc(dev);
3400 mutex_unlock(&dev->struct_mutex);
3401
3402 intel_crtc_update_cursor(crtc, true);
3403
3404 for_each_encoder_on_crtc(dev, crtc, encoder)
3405 encoder->enable(encoder);
3406
3407 if (HAS_PCH_CPT(dev))
3408 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3409
3410 /*
3411 * There seems to be a race in PCH platform hw (at least on some
3412 * outputs) where an enabled pipe still completes any pageflip right
3413 * away (as if the pipe is off) instead of waiting for vblank. As soon
3414 * as the first vblank happend, everything works as expected. Hence just
3415 * wait for one vblank before returning to avoid strange things
3416 * happening.
3417 */
3418 intel_wait_for_vblank(dev, intel_crtc->pipe);
3419 }
3420
3421 static void haswell_crtc_enable(struct drm_crtc *crtc)
3422 {
3423 struct drm_device *dev = crtc->dev;
3424 struct drm_i915_private *dev_priv = dev->dev_private;
3425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3426 struct intel_encoder *encoder;
3427 int pipe = intel_crtc->pipe;
3428 int plane = intel_crtc->plane;
3429
3430 WARN_ON(!crtc->enabled);
3431
3432 if (intel_crtc->active)
3433 return;
3434
3435 intel_crtc->active = true;
3436 intel_update_watermarks(dev);
3437
3438 if (intel_crtc->config.has_pch_encoder)
3439 dev_priv->display.fdi_link_train(crtc);
3440
3441 for_each_encoder_on_crtc(dev, crtc, encoder)
3442 if (encoder->pre_enable)
3443 encoder->pre_enable(encoder);
3444
3445 intel_ddi_enable_pipe_clock(intel_crtc);
3446
3447 /* Enable panel fitting for eDP */
3448 if (dev_priv->pch_pf_size &&
3449 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3450 /* Force use of hard-coded filter coefficients
3451 * as some pre-programmed values are broken,
3452 * e.g. x201.
3453 */
3454 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3455 PF_PIPE_SEL_IVB(pipe));
3456 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3457 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3458 }
3459
3460 /*
3461 * On ILK+ LUT must be loaded before the pipe is running but with
3462 * clocks enabled
3463 */
3464 intel_crtc_load_lut(crtc);
3465
3466 intel_ddi_set_pipe_settings(crtc);
3467 intel_ddi_enable_transcoder_func(crtc);
3468
3469 intel_enable_pipe(dev_priv, pipe,
3470 intel_crtc->config.has_pch_encoder);
3471 intel_enable_plane(dev_priv, plane, pipe);
3472
3473 if (intel_crtc->config.has_pch_encoder)
3474 lpt_pch_enable(crtc);
3475
3476 mutex_lock(&dev->struct_mutex);
3477 intel_update_fbc(dev);
3478 mutex_unlock(&dev->struct_mutex);
3479
3480 intel_crtc_update_cursor(crtc, true);
3481
3482 for_each_encoder_on_crtc(dev, crtc, encoder)
3483 encoder->enable(encoder);
3484
3485 /*
3486 * There seems to be a race in PCH platform hw (at least on some
3487 * outputs) where an enabled pipe still completes any pageflip right
3488 * away (as if the pipe is off) instead of waiting for vblank. As soon
3489 * as the first vblank happend, everything works as expected. Hence just
3490 * wait for one vblank before returning to avoid strange things
3491 * happening.
3492 */
3493 intel_wait_for_vblank(dev, intel_crtc->pipe);
3494 }
3495
3496 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3497 {
3498 struct drm_device *dev = crtc->dev;
3499 struct drm_i915_private *dev_priv = dev->dev_private;
3500 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3501 struct intel_encoder *encoder;
3502 int pipe = intel_crtc->pipe;
3503 int plane = intel_crtc->plane;
3504 u32 reg, temp;
3505
3506
3507 if (!intel_crtc->active)
3508 return;
3509
3510 for_each_encoder_on_crtc(dev, crtc, encoder)
3511 encoder->disable(encoder);
3512
3513 intel_crtc_wait_for_pending_flips(crtc);
3514 drm_vblank_off(dev, pipe);
3515 intel_crtc_update_cursor(crtc, false);
3516
3517 intel_disable_plane(dev_priv, plane, pipe);
3518
3519 if (dev_priv->cfb_plane == plane)
3520 intel_disable_fbc(dev);
3521
3522 intel_disable_pipe(dev_priv, pipe);
3523
3524 /* Disable PF */
3525 I915_WRITE(PF_CTL(pipe), 0);
3526 I915_WRITE(PF_WIN_SZ(pipe), 0);
3527
3528 for_each_encoder_on_crtc(dev, crtc, encoder)
3529 if (encoder->post_disable)
3530 encoder->post_disable(encoder);
3531
3532 ironlake_fdi_disable(crtc);
3533
3534 ironlake_disable_pch_transcoder(dev_priv, pipe);
3535
3536 if (HAS_PCH_CPT(dev)) {
3537 /* disable TRANS_DP_CTL */
3538 reg = TRANS_DP_CTL(pipe);
3539 temp = I915_READ(reg);
3540 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3541 temp |= TRANS_DP_PORT_SEL_NONE;
3542 I915_WRITE(reg, temp);
3543
3544 /* disable DPLL_SEL */
3545 temp = I915_READ(PCH_DPLL_SEL);
3546 switch (pipe) {
3547 case 0:
3548 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3549 break;
3550 case 1:
3551 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3552 break;
3553 case 2:
3554 /* C shares PLL A or B */
3555 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3556 break;
3557 default:
3558 BUG(); /* wtf */
3559 }
3560 I915_WRITE(PCH_DPLL_SEL, temp);
3561 }
3562
3563 /* disable PCH DPLL */
3564 intel_disable_pch_pll(intel_crtc);
3565
3566 ironlake_fdi_pll_disable(intel_crtc);
3567
3568 intel_crtc->active = false;
3569 intel_update_watermarks(dev);
3570
3571 mutex_lock(&dev->struct_mutex);
3572 intel_update_fbc(dev);
3573 mutex_unlock(&dev->struct_mutex);
3574 }
3575
3576 static void haswell_crtc_disable(struct drm_crtc *crtc)
3577 {
3578 struct drm_device *dev = crtc->dev;
3579 struct drm_i915_private *dev_priv = dev->dev_private;
3580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3581 struct intel_encoder *encoder;
3582 int pipe = intel_crtc->pipe;
3583 int plane = intel_crtc->plane;
3584 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3585 bool is_pch_port;
3586
3587 if (!intel_crtc->active)
3588 return;
3589
3590 is_pch_port = haswell_crtc_driving_pch(crtc);
3591
3592 for_each_encoder_on_crtc(dev, crtc, encoder)
3593 encoder->disable(encoder);
3594
3595 intel_crtc_wait_for_pending_flips(crtc);
3596 drm_vblank_off(dev, pipe);
3597 intel_crtc_update_cursor(crtc, false);
3598
3599 intel_disable_plane(dev_priv, plane, pipe);
3600
3601 if (dev_priv->cfb_plane == plane)
3602 intel_disable_fbc(dev);
3603
3604 intel_disable_pipe(dev_priv, pipe);
3605
3606 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3607
3608 /* Disable PF */
3609 I915_WRITE(PF_CTL(pipe), 0);
3610 I915_WRITE(PF_WIN_SZ(pipe), 0);
3611
3612 intel_ddi_disable_pipe_clock(intel_crtc);
3613
3614 for_each_encoder_on_crtc(dev, crtc, encoder)
3615 if (encoder->post_disable)
3616 encoder->post_disable(encoder);
3617
3618 if (is_pch_port) {
3619 lpt_disable_pch_transcoder(dev_priv);
3620 intel_ddi_fdi_disable(crtc);
3621 }
3622
3623 intel_crtc->active = false;
3624 intel_update_watermarks(dev);
3625
3626 mutex_lock(&dev->struct_mutex);
3627 intel_update_fbc(dev);
3628 mutex_unlock(&dev->struct_mutex);
3629 }
3630
3631 static void ironlake_crtc_off(struct drm_crtc *crtc)
3632 {
3633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3634 intel_put_pch_pll(intel_crtc);
3635 }
3636
3637 static void haswell_crtc_off(struct drm_crtc *crtc)
3638 {
3639 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3640
3641 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3642 * start using it. */
3643 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3644
3645 intel_ddi_put_crtc_pll(crtc);
3646 }
3647
3648 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3649 {
3650 if (!enable && intel_crtc->overlay) {
3651 struct drm_device *dev = intel_crtc->base.dev;
3652 struct drm_i915_private *dev_priv = dev->dev_private;
3653
3654 mutex_lock(&dev->struct_mutex);
3655 dev_priv->mm.interruptible = false;
3656 (void) intel_overlay_switch_off(intel_crtc->overlay);
3657 dev_priv->mm.interruptible = true;
3658 mutex_unlock(&dev->struct_mutex);
3659 }
3660
3661 /* Let userspace switch the overlay on again. In most cases userspace
3662 * has to recompute where to put it anyway.
3663 */
3664 }
3665
3666 /**
3667 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3668 * cursor plane briefly if not already running after enabling the display
3669 * plane.
3670 * This workaround avoids occasional blank screens when self refresh is
3671 * enabled.
3672 */
3673 static void
3674 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3675 {
3676 u32 cntl = I915_READ(CURCNTR(pipe));
3677
3678 if ((cntl & CURSOR_MODE) == 0) {
3679 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3680
3681 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3682 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3683 intel_wait_for_vblank(dev_priv->dev, pipe);
3684 I915_WRITE(CURCNTR(pipe), cntl);
3685 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3686 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3687 }
3688 }
3689
3690 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3691 {
3692 struct drm_device *dev = crtc->dev;
3693 struct drm_i915_private *dev_priv = dev->dev_private;
3694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3695 struct intel_encoder *encoder;
3696 int pipe = intel_crtc->pipe;
3697 int plane = intel_crtc->plane;
3698
3699 WARN_ON(!crtc->enabled);
3700
3701 if (intel_crtc->active)
3702 return;
3703
3704 intel_crtc->active = true;
3705 intel_update_watermarks(dev);
3706
3707 intel_enable_pll(dev_priv, pipe);
3708
3709 for_each_encoder_on_crtc(dev, crtc, encoder)
3710 if (encoder->pre_enable)
3711 encoder->pre_enable(encoder);
3712
3713 intel_enable_pipe(dev_priv, pipe, false);
3714 intel_enable_plane(dev_priv, plane, pipe);
3715 if (IS_G4X(dev))
3716 g4x_fixup_plane(dev_priv, pipe);
3717
3718 intel_crtc_load_lut(crtc);
3719 intel_update_fbc(dev);
3720
3721 /* Give the overlay scaler a chance to enable if it's on this pipe */
3722 intel_crtc_dpms_overlay(intel_crtc, true);
3723 intel_crtc_update_cursor(crtc, true);
3724
3725 for_each_encoder_on_crtc(dev, crtc, encoder)
3726 encoder->enable(encoder);
3727 }
3728
3729 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3730 {
3731 struct drm_device *dev = crtc->dev;
3732 struct drm_i915_private *dev_priv = dev->dev_private;
3733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3734 struct intel_encoder *encoder;
3735 int pipe = intel_crtc->pipe;
3736 int plane = intel_crtc->plane;
3737 u32 pctl;
3738
3739
3740 if (!intel_crtc->active)
3741 return;
3742
3743 for_each_encoder_on_crtc(dev, crtc, encoder)
3744 encoder->disable(encoder);
3745
3746 /* Give the overlay scaler a chance to disable if it's on this pipe */
3747 intel_crtc_wait_for_pending_flips(crtc);
3748 drm_vblank_off(dev, pipe);
3749 intel_crtc_dpms_overlay(intel_crtc, false);
3750 intel_crtc_update_cursor(crtc, false);
3751
3752 if (dev_priv->cfb_plane == plane)
3753 intel_disable_fbc(dev);
3754
3755 intel_disable_plane(dev_priv, plane, pipe);
3756 intel_disable_pipe(dev_priv, pipe);
3757
3758 /* Disable pannel fitter if it is on this pipe. */
3759 pctl = I915_READ(PFIT_CONTROL);
3760 if ((pctl & PFIT_ENABLE) &&
3761 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3762 I915_WRITE(PFIT_CONTROL, 0);
3763
3764 intel_disable_pll(dev_priv, pipe);
3765
3766 intel_crtc->active = false;
3767 intel_update_fbc(dev);
3768 intel_update_watermarks(dev);
3769 }
3770
3771 static void i9xx_crtc_off(struct drm_crtc *crtc)
3772 {
3773 }
3774
3775 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3776 bool enabled)
3777 {
3778 struct drm_device *dev = crtc->dev;
3779 struct drm_i915_master_private *master_priv;
3780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3781 int pipe = intel_crtc->pipe;
3782
3783 if (!dev->primary->master)
3784 return;
3785
3786 master_priv = dev->primary->master->driver_priv;
3787 if (!master_priv->sarea_priv)
3788 return;
3789
3790 switch (pipe) {
3791 case 0:
3792 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3793 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3794 break;
3795 case 1:
3796 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3797 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3798 break;
3799 default:
3800 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3801 break;
3802 }
3803 }
3804
3805 /**
3806 * Sets the power management mode of the pipe and plane.
3807 */
3808 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3809 {
3810 struct drm_device *dev = crtc->dev;
3811 struct drm_i915_private *dev_priv = dev->dev_private;
3812 struct intel_encoder *intel_encoder;
3813 bool enable = false;
3814
3815 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3816 enable |= intel_encoder->connectors_active;
3817
3818 if (enable)
3819 dev_priv->display.crtc_enable(crtc);
3820 else
3821 dev_priv->display.crtc_disable(crtc);
3822
3823 intel_crtc_update_sarea(crtc, enable);
3824 }
3825
3826 static void intel_crtc_disable(struct drm_crtc *crtc)
3827 {
3828 struct drm_device *dev = crtc->dev;
3829 struct drm_connector *connector;
3830 struct drm_i915_private *dev_priv = dev->dev_private;
3831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3832
3833 /* crtc should still be enabled when we disable it. */
3834 WARN_ON(!crtc->enabled);
3835
3836 intel_crtc->eld_vld = false;
3837 dev_priv->display.crtc_disable(crtc);
3838 intel_crtc_update_sarea(crtc, false);
3839 dev_priv->display.off(crtc);
3840
3841 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3842 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3843
3844 if (crtc->fb) {
3845 mutex_lock(&dev->struct_mutex);
3846 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3847 mutex_unlock(&dev->struct_mutex);
3848 crtc->fb = NULL;
3849 }
3850
3851 /* Update computed state. */
3852 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3853 if (!connector->encoder || !connector->encoder->crtc)
3854 continue;
3855
3856 if (connector->encoder->crtc != crtc)
3857 continue;
3858
3859 connector->dpms = DRM_MODE_DPMS_OFF;
3860 to_intel_encoder(connector->encoder)->connectors_active = false;
3861 }
3862 }
3863
3864 void intel_modeset_disable(struct drm_device *dev)
3865 {
3866 struct drm_crtc *crtc;
3867
3868 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3869 if (crtc->enabled)
3870 intel_crtc_disable(crtc);
3871 }
3872 }
3873
3874 void intel_encoder_destroy(struct drm_encoder *encoder)
3875 {
3876 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3877
3878 drm_encoder_cleanup(encoder);
3879 kfree(intel_encoder);
3880 }
3881
3882 /* Simple dpms helper for encodres with just one connector, no cloning and only
3883 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3884 * state of the entire output pipe. */
3885 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3886 {
3887 if (mode == DRM_MODE_DPMS_ON) {
3888 encoder->connectors_active = true;
3889
3890 intel_crtc_update_dpms(encoder->base.crtc);
3891 } else {
3892 encoder->connectors_active = false;
3893
3894 intel_crtc_update_dpms(encoder->base.crtc);
3895 }
3896 }
3897
3898 /* Cross check the actual hw state with our own modeset state tracking (and it's
3899 * internal consistency). */
3900 static void intel_connector_check_state(struct intel_connector *connector)
3901 {
3902 if (connector->get_hw_state(connector)) {
3903 struct intel_encoder *encoder = connector->encoder;
3904 struct drm_crtc *crtc;
3905 bool encoder_enabled;
3906 enum pipe pipe;
3907
3908 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3909 connector->base.base.id,
3910 drm_get_connector_name(&connector->base));
3911
3912 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3913 "wrong connector dpms state\n");
3914 WARN(connector->base.encoder != &encoder->base,
3915 "active connector not linked to encoder\n");
3916 WARN(!encoder->connectors_active,
3917 "encoder->connectors_active not set\n");
3918
3919 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3920 WARN(!encoder_enabled, "encoder not enabled\n");
3921 if (WARN_ON(!encoder->base.crtc))
3922 return;
3923
3924 crtc = encoder->base.crtc;
3925
3926 WARN(!crtc->enabled, "crtc not enabled\n");
3927 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3928 WARN(pipe != to_intel_crtc(crtc)->pipe,
3929 "encoder active on the wrong pipe\n");
3930 }
3931 }
3932
3933 /* Even simpler default implementation, if there's really no special case to
3934 * consider. */
3935 void intel_connector_dpms(struct drm_connector *connector, int mode)
3936 {
3937 struct intel_encoder *encoder = intel_attached_encoder(connector);
3938
3939 /* All the simple cases only support two dpms states. */
3940 if (mode != DRM_MODE_DPMS_ON)
3941 mode = DRM_MODE_DPMS_OFF;
3942
3943 if (mode == connector->dpms)
3944 return;
3945
3946 connector->dpms = mode;
3947
3948 /* Only need to change hw state when actually enabled */
3949 if (encoder->base.crtc)
3950 intel_encoder_dpms(encoder, mode);
3951 else
3952 WARN_ON(encoder->connectors_active != false);
3953
3954 intel_modeset_check_state(connector->dev);
3955 }
3956
3957 /* Simple connector->get_hw_state implementation for encoders that support only
3958 * one connector and no cloning and hence the encoder state determines the state
3959 * of the connector. */
3960 bool intel_connector_get_hw_state(struct intel_connector *connector)
3961 {
3962 enum pipe pipe = 0;
3963 struct intel_encoder *encoder = connector->encoder;
3964
3965 return encoder->get_hw_state(encoder, &pipe);
3966 }
3967
3968 static bool intel_crtc_compute_config(struct drm_crtc *crtc,
3969 struct intel_crtc_config *pipe_config)
3970 {
3971 struct drm_device *dev = crtc->dev;
3972 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3973
3974 if (HAS_PCH_SPLIT(dev)) {
3975 /* FDI link clock is fixed at 2.7G */
3976 if (pipe_config->requested_mode.clock * 3
3977 > IRONLAKE_FDI_FREQ * 4)
3978 return false;
3979 }
3980
3981 /* All interlaced capable intel hw wants timings in frames. Note though
3982 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3983 * timings, so we need to be careful not to clobber these.*/
3984 if (!pipe_config->timings_set)
3985 drm_mode_set_crtcinfo(adjusted_mode, 0);
3986
3987 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3988 * with a hsync front porch of 0.
3989 */
3990 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3991 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3992 return false;
3993
3994 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10) {
3995 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
3996 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8) {
3997 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
3998 * for lvds. */
3999 pipe_config->pipe_bpp = 8*3;
4000 }
4001
4002 return true;
4003 }
4004
4005 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4006 {
4007 return 400000; /* FIXME */
4008 }
4009
4010 static int i945_get_display_clock_speed(struct drm_device *dev)
4011 {
4012 return 400000;
4013 }
4014
4015 static int i915_get_display_clock_speed(struct drm_device *dev)
4016 {
4017 return 333000;
4018 }
4019
4020 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4021 {
4022 return 200000;
4023 }
4024
4025 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4026 {
4027 u16 gcfgc = 0;
4028
4029 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4030
4031 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4032 return 133000;
4033 else {
4034 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4035 case GC_DISPLAY_CLOCK_333_MHZ:
4036 return 333000;
4037 default:
4038 case GC_DISPLAY_CLOCK_190_200_MHZ:
4039 return 190000;
4040 }
4041 }
4042 }
4043
4044 static int i865_get_display_clock_speed(struct drm_device *dev)
4045 {
4046 return 266000;
4047 }
4048
4049 static int i855_get_display_clock_speed(struct drm_device *dev)
4050 {
4051 u16 hpllcc = 0;
4052 /* Assume that the hardware is in the high speed state. This
4053 * should be the default.
4054 */
4055 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4056 case GC_CLOCK_133_200:
4057 case GC_CLOCK_100_200:
4058 return 200000;
4059 case GC_CLOCK_166_250:
4060 return 250000;
4061 case GC_CLOCK_100_133:
4062 return 133000;
4063 }
4064
4065 /* Shouldn't happen */
4066 return 0;
4067 }
4068
4069 static int i830_get_display_clock_speed(struct drm_device *dev)
4070 {
4071 return 133000;
4072 }
4073
4074 static void
4075 intel_reduce_ratio(uint32_t *num, uint32_t *den)
4076 {
4077 while (*num > 0xffffff || *den > 0xffffff) {
4078 *num >>= 1;
4079 *den >>= 1;
4080 }
4081 }
4082
4083 void
4084 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4085 int pixel_clock, int link_clock,
4086 struct intel_link_m_n *m_n)
4087 {
4088 m_n->tu = 64;
4089 m_n->gmch_m = bits_per_pixel * pixel_clock;
4090 m_n->gmch_n = link_clock * nlanes * 8;
4091 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4092 m_n->link_m = pixel_clock;
4093 m_n->link_n = link_clock;
4094 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4095 }
4096
4097 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4098 {
4099 if (i915_panel_use_ssc >= 0)
4100 return i915_panel_use_ssc != 0;
4101 return dev_priv->lvds_use_ssc
4102 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4103 }
4104
4105 static int vlv_get_refclk(struct drm_crtc *crtc)
4106 {
4107 struct drm_device *dev = crtc->dev;
4108 struct drm_i915_private *dev_priv = dev->dev_private;
4109 int refclk = 27000; /* for DP & HDMI */
4110
4111 return 100000; /* only one validated so far */
4112
4113 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4114 refclk = 96000;
4115 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4116 if (intel_panel_use_ssc(dev_priv))
4117 refclk = 100000;
4118 else
4119 refclk = 96000;
4120 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4121 refclk = 100000;
4122 }
4123
4124 return refclk;
4125 }
4126
4127 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4128 {
4129 struct drm_device *dev = crtc->dev;
4130 struct drm_i915_private *dev_priv = dev->dev_private;
4131 int refclk;
4132
4133 if (IS_VALLEYVIEW(dev)) {
4134 refclk = vlv_get_refclk(crtc);
4135 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4136 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4137 refclk = dev_priv->lvds_ssc_freq * 1000;
4138 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4139 refclk / 1000);
4140 } else if (!IS_GEN2(dev)) {
4141 refclk = 96000;
4142 } else {
4143 refclk = 48000;
4144 }
4145
4146 return refclk;
4147 }
4148
4149 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4150 intel_clock_t *clock)
4151 {
4152 /* SDVO TV has fixed PLL values depend on its clock range,
4153 this mirrors vbios setting. */
4154 if (adjusted_mode->clock >= 100000
4155 && adjusted_mode->clock < 140500) {
4156 clock->p1 = 2;
4157 clock->p2 = 10;
4158 clock->n = 3;
4159 clock->m1 = 16;
4160 clock->m2 = 8;
4161 } else if (adjusted_mode->clock >= 140500
4162 && adjusted_mode->clock <= 200000) {
4163 clock->p1 = 1;
4164 clock->p2 = 10;
4165 clock->n = 6;
4166 clock->m1 = 12;
4167 clock->m2 = 8;
4168 }
4169 }
4170
4171 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4172 intel_clock_t *clock,
4173 intel_clock_t *reduced_clock)
4174 {
4175 struct drm_device *dev = crtc->dev;
4176 struct drm_i915_private *dev_priv = dev->dev_private;
4177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4178 int pipe = intel_crtc->pipe;
4179 u32 fp, fp2 = 0;
4180
4181 if (IS_PINEVIEW(dev)) {
4182 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4183 if (reduced_clock)
4184 fp2 = (1 << reduced_clock->n) << 16 |
4185 reduced_clock->m1 << 8 | reduced_clock->m2;
4186 } else {
4187 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4188 if (reduced_clock)
4189 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4190 reduced_clock->m2;
4191 }
4192
4193 I915_WRITE(FP0(pipe), fp);
4194
4195 intel_crtc->lowfreq_avail = false;
4196 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4197 reduced_clock && i915_powersave) {
4198 I915_WRITE(FP1(pipe), fp2);
4199 intel_crtc->lowfreq_avail = true;
4200 } else {
4201 I915_WRITE(FP1(pipe), fp);
4202 }
4203 }
4204
4205 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4206 {
4207 if (crtc->config.has_pch_encoder)
4208 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4209 else
4210 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4211 }
4212
4213 static void vlv_update_pll(struct drm_crtc *crtc,
4214 intel_clock_t *clock, intel_clock_t *reduced_clock,
4215 int num_connectors)
4216 {
4217 struct drm_device *dev = crtc->dev;
4218 struct drm_i915_private *dev_priv = dev->dev_private;
4219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4220 int pipe = intel_crtc->pipe;
4221 u32 dpll, mdiv, pdiv;
4222 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4223 bool is_sdvo;
4224 u32 temp;
4225
4226 mutex_lock(&dev_priv->dpio_lock);
4227
4228 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4229 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4230
4231 dpll = DPLL_VGA_MODE_DIS;
4232 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4233 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4234 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4235
4236 I915_WRITE(DPLL(pipe), dpll);
4237 POSTING_READ(DPLL(pipe));
4238
4239 bestn = clock->n;
4240 bestm1 = clock->m1;
4241 bestm2 = clock->m2;
4242 bestp1 = clock->p1;
4243 bestp2 = clock->p2;
4244
4245 /*
4246 * In Valleyview PLL and program lane counter registers are exposed
4247 * through DPIO interface
4248 */
4249 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4250 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4251 mdiv |= ((bestn << DPIO_N_SHIFT));
4252 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4253 mdiv |= (1 << DPIO_K_SHIFT);
4254 mdiv |= DPIO_ENABLE_CALIBRATION;
4255 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4256
4257 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4258
4259 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4260 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4261 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4262 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4263 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4264
4265 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4266
4267 dpll |= DPLL_VCO_ENABLE;
4268 I915_WRITE(DPLL(pipe), dpll);
4269 POSTING_READ(DPLL(pipe));
4270 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4271 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4272
4273 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4274
4275 if (intel_crtc->config.has_dp_encoder)
4276 intel_dp_set_m_n(intel_crtc);
4277
4278 I915_WRITE(DPLL(pipe), dpll);
4279
4280 /* Wait for the clocks to stabilize. */
4281 POSTING_READ(DPLL(pipe));
4282 udelay(150);
4283
4284 temp = 0;
4285 if (is_sdvo) {
4286 temp = 0;
4287 if (intel_crtc->config.pixel_multiplier > 1) {
4288 temp = (intel_crtc->config.pixel_multiplier - 1)
4289 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4290 }
4291 }
4292 I915_WRITE(DPLL_MD(pipe), temp);
4293 POSTING_READ(DPLL_MD(pipe));
4294
4295 /* Now program lane control registers */
4296 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4297 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4298 {
4299 temp = 0x1000C4;
4300 if(pipe == 1)
4301 temp |= (1 << 21);
4302 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4303 }
4304 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4305 {
4306 temp = 0x1000C4;
4307 if(pipe == 1)
4308 temp |= (1 << 21);
4309 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4310 }
4311
4312 mutex_unlock(&dev_priv->dpio_lock);
4313 }
4314
4315 static void i9xx_update_pll(struct drm_crtc *crtc,
4316 intel_clock_t *clock, intel_clock_t *reduced_clock,
4317 int num_connectors)
4318 {
4319 struct drm_device *dev = crtc->dev;
4320 struct drm_i915_private *dev_priv = dev->dev_private;
4321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4322 struct intel_encoder *encoder;
4323 int pipe = intel_crtc->pipe;
4324 u32 dpll;
4325 bool is_sdvo;
4326
4327 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4328
4329 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4330 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4331
4332 dpll = DPLL_VGA_MODE_DIS;
4333
4334 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4335 dpll |= DPLLB_MODE_LVDS;
4336 else
4337 dpll |= DPLLB_MODE_DAC_SERIAL;
4338
4339 if (is_sdvo) {
4340 if ((intel_crtc->config.pixel_multiplier > 1) &&
4341 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4342 dpll |= (intel_crtc->config.pixel_multiplier - 1)
4343 << SDVO_MULTIPLIER_SHIFT_HIRES;
4344 }
4345 dpll |= DPLL_DVO_HIGH_SPEED;
4346 }
4347 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4348 dpll |= DPLL_DVO_HIGH_SPEED;
4349
4350 /* compute bitmask from p1 value */
4351 if (IS_PINEVIEW(dev))
4352 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4353 else {
4354 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4355 if (IS_G4X(dev) && reduced_clock)
4356 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4357 }
4358 switch (clock->p2) {
4359 case 5:
4360 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4361 break;
4362 case 7:
4363 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4364 break;
4365 case 10:
4366 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4367 break;
4368 case 14:
4369 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4370 break;
4371 }
4372 if (INTEL_INFO(dev)->gen >= 4)
4373 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4374
4375 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4376 dpll |= PLL_REF_INPUT_TVCLKINBC;
4377 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4378 /* XXX: just matching BIOS for now */
4379 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4380 dpll |= 3;
4381 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4382 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4383 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4384 else
4385 dpll |= PLL_REF_INPUT_DREFCLK;
4386
4387 dpll |= DPLL_VCO_ENABLE;
4388 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4389 POSTING_READ(DPLL(pipe));
4390 udelay(150);
4391
4392 for_each_encoder_on_crtc(dev, crtc, encoder)
4393 if (encoder->pre_pll_enable)
4394 encoder->pre_pll_enable(encoder);
4395
4396 if (intel_crtc->config.has_dp_encoder)
4397 intel_dp_set_m_n(intel_crtc);
4398
4399 I915_WRITE(DPLL(pipe), dpll);
4400
4401 /* Wait for the clocks to stabilize. */
4402 POSTING_READ(DPLL(pipe));
4403 udelay(150);
4404
4405 if (INTEL_INFO(dev)->gen >= 4) {
4406 u32 temp = 0;
4407 if (is_sdvo) {
4408 temp = 0;
4409 if (intel_crtc->config.pixel_multiplier > 1) {
4410 temp = (intel_crtc->config.pixel_multiplier - 1)
4411 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4412 }
4413 }
4414 I915_WRITE(DPLL_MD(pipe), temp);
4415 } else {
4416 /* The pixel multiplier can only be updated once the
4417 * DPLL is enabled and the clocks are stable.
4418 *
4419 * So write it again.
4420 */
4421 I915_WRITE(DPLL(pipe), dpll);
4422 }
4423 }
4424
4425 static void i8xx_update_pll(struct drm_crtc *crtc,
4426 struct drm_display_mode *adjusted_mode,
4427 intel_clock_t *clock, intel_clock_t *reduced_clock,
4428 int num_connectors)
4429 {
4430 struct drm_device *dev = crtc->dev;
4431 struct drm_i915_private *dev_priv = dev->dev_private;
4432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4433 struct intel_encoder *encoder;
4434 int pipe = intel_crtc->pipe;
4435 u32 dpll;
4436
4437 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4438
4439 dpll = DPLL_VGA_MODE_DIS;
4440
4441 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4442 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4443 } else {
4444 if (clock->p1 == 2)
4445 dpll |= PLL_P1_DIVIDE_BY_TWO;
4446 else
4447 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4448 if (clock->p2 == 4)
4449 dpll |= PLL_P2_DIVIDE_BY_4;
4450 }
4451
4452 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4453 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4454 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4455 else
4456 dpll |= PLL_REF_INPUT_DREFCLK;
4457
4458 dpll |= DPLL_VCO_ENABLE;
4459 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4460 POSTING_READ(DPLL(pipe));
4461 udelay(150);
4462
4463 for_each_encoder_on_crtc(dev, crtc, encoder)
4464 if (encoder->pre_pll_enable)
4465 encoder->pre_pll_enable(encoder);
4466
4467 I915_WRITE(DPLL(pipe), dpll);
4468
4469 /* Wait for the clocks to stabilize. */
4470 POSTING_READ(DPLL(pipe));
4471 udelay(150);
4472
4473 /* The pixel multiplier can only be updated once the
4474 * DPLL is enabled and the clocks are stable.
4475 *
4476 * So write it again.
4477 */
4478 I915_WRITE(DPLL(pipe), dpll);
4479 }
4480
4481 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4482 struct drm_display_mode *mode,
4483 struct drm_display_mode *adjusted_mode)
4484 {
4485 struct drm_device *dev = intel_crtc->base.dev;
4486 struct drm_i915_private *dev_priv = dev->dev_private;
4487 enum pipe pipe = intel_crtc->pipe;
4488 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4489 uint32_t vsyncshift;
4490
4491 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4492 /* the chip adds 2 halflines automatically */
4493 adjusted_mode->crtc_vtotal -= 1;
4494 adjusted_mode->crtc_vblank_end -= 1;
4495 vsyncshift = adjusted_mode->crtc_hsync_start
4496 - adjusted_mode->crtc_htotal / 2;
4497 } else {
4498 vsyncshift = 0;
4499 }
4500
4501 if (INTEL_INFO(dev)->gen > 3)
4502 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4503
4504 I915_WRITE(HTOTAL(cpu_transcoder),
4505 (adjusted_mode->crtc_hdisplay - 1) |
4506 ((adjusted_mode->crtc_htotal - 1) << 16));
4507 I915_WRITE(HBLANK(cpu_transcoder),
4508 (adjusted_mode->crtc_hblank_start - 1) |
4509 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4510 I915_WRITE(HSYNC(cpu_transcoder),
4511 (adjusted_mode->crtc_hsync_start - 1) |
4512 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4513
4514 I915_WRITE(VTOTAL(cpu_transcoder),
4515 (adjusted_mode->crtc_vdisplay - 1) |
4516 ((adjusted_mode->crtc_vtotal - 1) << 16));
4517 I915_WRITE(VBLANK(cpu_transcoder),
4518 (adjusted_mode->crtc_vblank_start - 1) |
4519 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4520 I915_WRITE(VSYNC(cpu_transcoder),
4521 (adjusted_mode->crtc_vsync_start - 1) |
4522 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4523
4524 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4525 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4526 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4527 * bits. */
4528 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4529 (pipe == PIPE_B || pipe == PIPE_C))
4530 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4531
4532 /* pipesrc controls the size that is scaled from, which should
4533 * always be the user's requested size.
4534 */
4535 I915_WRITE(PIPESRC(pipe),
4536 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4537 }
4538
4539 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4540 int x, int y,
4541 struct drm_framebuffer *fb)
4542 {
4543 struct drm_device *dev = crtc->dev;
4544 struct drm_i915_private *dev_priv = dev->dev_private;
4545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4546 struct drm_display_mode *adjusted_mode =
4547 &intel_crtc->config.adjusted_mode;
4548 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4549 int pipe = intel_crtc->pipe;
4550 int plane = intel_crtc->plane;
4551 int refclk, num_connectors = 0;
4552 intel_clock_t clock, reduced_clock;
4553 u32 dspcntr, pipeconf;
4554 bool ok, has_reduced_clock = false, is_sdvo = false;
4555 bool is_lvds = false, is_tv = false;
4556 struct intel_encoder *encoder;
4557 const intel_limit_t *limit;
4558 int ret;
4559
4560 for_each_encoder_on_crtc(dev, crtc, encoder) {
4561 switch (encoder->type) {
4562 case INTEL_OUTPUT_LVDS:
4563 is_lvds = true;
4564 break;
4565 case INTEL_OUTPUT_SDVO:
4566 case INTEL_OUTPUT_HDMI:
4567 is_sdvo = true;
4568 if (encoder->needs_tv_clock)
4569 is_tv = true;
4570 break;
4571 case INTEL_OUTPUT_TVOUT:
4572 is_tv = true;
4573 break;
4574 }
4575
4576 num_connectors++;
4577 }
4578
4579 refclk = i9xx_get_refclk(crtc, num_connectors);
4580
4581 /*
4582 * Returns a set of divisors for the desired target clock with the given
4583 * refclk, or FALSE. The returned values represent the clock equation:
4584 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4585 */
4586 limit = intel_limit(crtc, refclk);
4587 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4588 &clock);
4589 if (!ok) {
4590 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4591 return -EINVAL;
4592 }
4593
4594 /* Ensure that the cursor is valid for the new mode before changing... */
4595 intel_crtc_update_cursor(crtc, true);
4596
4597 if (is_lvds && dev_priv->lvds_downclock_avail) {
4598 /*
4599 * Ensure we match the reduced clock's P to the target clock.
4600 * If the clocks don't match, we can't switch the display clock
4601 * by using the FP0/FP1. In such case we will disable the LVDS
4602 * downclock feature.
4603 */
4604 has_reduced_clock = limit->find_pll(limit, crtc,
4605 dev_priv->lvds_downclock,
4606 refclk,
4607 &clock,
4608 &reduced_clock);
4609 }
4610
4611 if (is_sdvo && is_tv)
4612 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4613
4614 if (IS_GEN2(dev))
4615 i8xx_update_pll(crtc, adjusted_mode, &clock,
4616 has_reduced_clock ? &reduced_clock : NULL,
4617 num_connectors);
4618 else if (IS_VALLEYVIEW(dev))
4619 vlv_update_pll(crtc, &clock,
4620 has_reduced_clock ? &reduced_clock : NULL,
4621 num_connectors);
4622 else
4623 i9xx_update_pll(crtc, &clock,
4624 has_reduced_clock ? &reduced_clock : NULL,
4625 num_connectors);
4626
4627 /* setup pipeconf */
4628 pipeconf = I915_READ(PIPECONF(pipe));
4629
4630 /* Set up the display plane register */
4631 dspcntr = DISPPLANE_GAMMA_ENABLE;
4632
4633 if (!IS_VALLEYVIEW(dev)) {
4634 if (pipe == 0)
4635 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4636 else
4637 dspcntr |= DISPPLANE_SEL_PIPE_B;
4638 }
4639
4640 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4641 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4642 * core speed.
4643 *
4644 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4645 * pipe == 0 check?
4646 */
4647 if (mode->clock >
4648 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4649 pipeconf |= PIPECONF_DOUBLE_WIDE;
4650 else
4651 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4652 }
4653
4654 /* default to 8bpc */
4655 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4656 if (intel_crtc->config.has_dp_encoder) {
4657 if (intel_crtc->config.dither) {
4658 pipeconf |= PIPECONF_6BPC |
4659 PIPECONF_DITHER_EN |
4660 PIPECONF_DITHER_TYPE_SP;
4661 }
4662 }
4663
4664 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4665 if (intel_crtc->config.dither) {
4666 pipeconf |= PIPECONF_6BPC |
4667 PIPECONF_ENABLE |
4668 I965_PIPECONF_ACTIVE;
4669 }
4670 }
4671
4672 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4673 drm_mode_debug_printmodeline(mode);
4674
4675 if (HAS_PIPE_CXSR(dev)) {
4676 if (intel_crtc->lowfreq_avail) {
4677 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4678 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4679 } else {
4680 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4681 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4682 }
4683 }
4684
4685 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4686 if (!IS_GEN2(dev) &&
4687 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4688 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4689 else
4690 pipeconf |= PIPECONF_PROGRESSIVE;
4691
4692 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4693
4694 /* pipesrc and dspsize control the size that is scaled from,
4695 * which should always be the user's requested size.
4696 */
4697 I915_WRITE(DSPSIZE(plane),
4698 ((mode->vdisplay - 1) << 16) |
4699 (mode->hdisplay - 1));
4700 I915_WRITE(DSPPOS(plane), 0);
4701
4702 I915_WRITE(PIPECONF(pipe), pipeconf);
4703 POSTING_READ(PIPECONF(pipe));
4704 intel_enable_pipe(dev_priv, pipe, false);
4705
4706 intel_wait_for_vblank(dev, pipe);
4707
4708 I915_WRITE(DSPCNTR(plane), dspcntr);
4709 POSTING_READ(DSPCNTR(plane));
4710
4711 ret = intel_pipe_set_base(crtc, x, y, fb);
4712
4713 intel_update_watermarks(dev);
4714
4715 return ret;
4716 }
4717
4718 static void ironlake_init_pch_refclk(struct drm_device *dev)
4719 {
4720 struct drm_i915_private *dev_priv = dev->dev_private;
4721 struct drm_mode_config *mode_config = &dev->mode_config;
4722 struct intel_encoder *encoder;
4723 u32 val, final;
4724 bool has_lvds = false;
4725 bool has_cpu_edp = false;
4726 bool has_pch_edp = false;
4727 bool has_panel = false;
4728 bool has_ck505 = false;
4729 bool can_ssc = false;
4730
4731 /* We need to take the global config into account */
4732 list_for_each_entry(encoder, &mode_config->encoder_list,
4733 base.head) {
4734 switch (encoder->type) {
4735 case INTEL_OUTPUT_LVDS:
4736 has_panel = true;
4737 has_lvds = true;
4738 break;
4739 case INTEL_OUTPUT_EDP:
4740 has_panel = true;
4741 if (intel_encoder_is_pch_edp(&encoder->base))
4742 has_pch_edp = true;
4743 else
4744 has_cpu_edp = true;
4745 break;
4746 }
4747 }
4748
4749 if (HAS_PCH_IBX(dev)) {
4750 has_ck505 = dev_priv->display_clock_mode;
4751 can_ssc = has_ck505;
4752 } else {
4753 has_ck505 = false;
4754 can_ssc = true;
4755 }
4756
4757 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4758 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4759 has_ck505);
4760
4761 /* Ironlake: try to setup display ref clock before DPLL
4762 * enabling. This is only under driver's control after
4763 * PCH B stepping, previous chipset stepping should be
4764 * ignoring this setting.
4765 */
4766 val = I915_READ(PCH_DREF_CONTROL);
4767
4768 /* As we must carefully and slowly disable/enable each source in turn,
4769 * compute the final state we want first and check if we need to
4770 * make any changes at all.
4771 */
4772 final = val;
4773 final &= ~DREF_NONSPREAD_SOURCE_MASK;
4774 if (has_ck505)
4775 final |= DREF_NONSPREAD_CK505_ENABLE;
4776 else
4777 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4778
4779 final &= ~DREF_SSC_SOURCE_MASK;
4780 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4781 final &= ~DREF_SSC1_ENABLE;
4782
4783 if (has_panel) {
4784 final |= DREF_SSC_SOURCE_ENABLE;
4785
4786 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4787 final |= DREF_SSC1_ENABLE;
4788
4789 if (has_cpu_edp) {
4790 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4791 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4792 else
4793 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4794 } else
4795 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4796 } else {
4797 final |= DREF_SSC_SOURCE_DISABLE;
4798 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4799 }
4800
4801 if (final == val)
4802 return;
4803
4804 /* Always enable nonspread source */
4805 val &= ~DREF_NONSPREAD_SOURCE_MASK;
4806
4807 if (has_ck505)
4808 val |= DREF_NONSPREAD_CK505_ENABLE;
4809 else
4810 val |= DREF_NONSPREAD_SOURCE_ENABLE;
4811
4812 if (has_panel) {
4813 val &= ~DREF_SSC_SOURCE_MASK;
4814 val |= DREF_SSC_SOURCE_ENABLE;
4815
4816 /* SSC must be turned on before enabling the CPU output */
4817 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4818 DRM_DEBUG_KMS("Using SSC on panel\n");
4819 val |= DREF_SSC1_ENABLE;
4820 } else
4821 val &= ~DREF_SSC1_ENABLE;
4822
4823 /* Get SSC going before enabling the outputs */
4824 I915_WRITE(PCH_DREF_CONTROL, val);
4825 POSTING_READ(PCH_DREF_CONTROL);
4826 udelay(200);
4827
4828 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4829
4830 /* Enable CPU source on CPU attached eDP */
4831 if (has_cpu_edp) {
4832 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4833 DRM_DEBUG_KMS("Using SSC on eDP\n");
4834 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4835 }
4836 else
4837 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4838 } else
4839 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4840
4841 I915_WRITE(PCH_DREF_CONTROL, val);
4842 POSTING_READ(PCH_DREF_CONTROL);
4843 udelay(200);
4844 } else {
4845 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4846
4847 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4848
4849 /* Turn off CPU output */
4850 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4851
4852 I915_WRITE(PCH_DREF_CONTROL, val);
4853 POSTING_READ(PCH_DREF_CONTROL);
4854 udelay(200);
4855
4856 /* Turn off the SSC source */
4857 val &= ~DREF_SSC_SOURCE_MASK;
4858 val |= DREF_SSC_SOURCE_DISABLE;
4859
4860 /* Turn off SSC1 */
4861 val &= ~DREF_SSC1_ENABLE;
4862
4863 I915_WRITE(PCH_DREF_CONTROL, val);
4864 POSTING_READ(PCH_DREF_CONTROL);
4865 udelay(200);
4866 }
4867
4868 BUG_ON(val != final);
4869 }
4870
4871 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4872 static void lpt_init_pch_refclk(struct drm_device *dev)
4873 {
4874 struct drm_i915_private *dev_priv = dev->dev_private;
4875 struct drm_mode_config *mode_config = &dev->mode_config;
4876 struct intel_encoder *encoder;
4877 bool has_vga = false;
4878 bool is_sdv = false;
4879 u32 tmp;
4880
4881 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4882 switch (encoder->type) {
4883 case INTEL_OUTPUT_ANALOG:
4884 has_vga = true;
4885 break;
4886 }
4887 }
4888
4889 if (!has_vga)
4890 return;
4891
4892 mutex_lock(&dev_priv->dpio_lock);
4893
4894 /* XXX: Rip out SDV support once Haswell ships for real. */
4895 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4896 is_sdv = true;
4897
4898 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4899 tmp &= ~SBI_SSCCTL_DISABLE;
4900 tmp |= SBI_SSCCTL_PATHALT;
4901 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4902
4903 udelay(24);
4904
4905 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4906 tmp &= ~SBI_SSCCTL_PATHALT;
4907 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4908
4909 if (!is_sdv) {
4910 tmp = I915_READ(SOUTH_CHICKEN2);
4911 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4912 I915_WRITE(SOUTH_CHICKEN2, tmp);
4913
4914 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4915 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4916 DRM_ERROR("FDI mPHY reset assert timeout\n");
4917
4918 tmp = I915_READ(SOUTH_CHICKEN2);
4919 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4920 I915_WRITE(SOUTH_CHICKEN2, tmp);
4921
4922 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4923 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4924 100))
4925 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4926 }
4927
4928 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4929 tmp &= ~(0xFF << 24);
4930 tmp |= (0x12 << 24);
4931 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4932
4933 if (!is_sdv) {
4934 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4935 tmp &= ~(0x3 << 6);
4936 tmp |= (1 << 6) | (1 << 0);
4937 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4938 }
4939
4940 if (is_sdv) {
4941 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4942 tmp |= 0x7FFF;
4943 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4944 }
4945
4946 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4947 tmp |= (1 << 11);
4948 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4949
4950 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4951 tmp |= (1 << 11);
4952 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4953
4954 if (is_sdv) {
4955 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4956 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4957 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4958
4959 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4960 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4961 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4962
4963 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
4964 tmp |= (0x3F << 8);
4965 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
4966
4967 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
4968 tmp |= (0x3F << 8);
4969 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
4970 }
4971
4972 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
4973 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4974 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
4975
4976 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
4977 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4978 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
4979
4980 if (!is_sdv) {
4981 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
4982 tmp &= ~(7 << 13);
4983 tmp |= (5 << 13);
4984 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
4985
4986 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
4987 tmp &= ~(7 << 13);
4988 tmp |= (5 << 13);
4989 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
4990 }
4991
4992 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
4993 tmp &= ~0xFF;
4994 tmp |= 0x1C;
4995 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
4996
4997 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
4998 tmp &= ~0xFF;
4999 tmp |= 0x1C;
5000 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5001
5002 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5003 tmp &= ~(0xFF << 16);
5004 tmp |= (0x1C << 16);
5005 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5006
5007 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5008 tmp &= ~(0xFF << 16);
5009 tmp |= (0x1C << 16);
5010 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5011
5012 if (!is_sdv) {
5013 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5014 tmp |= (1 << 27);
5015 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5016
5017 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5018 tmp |= (1 << 27);
5019 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5020
5021 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5022 tmp &= ~(0xF << 28);
5023 tmp |= (4 << 28);
5024 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5025
5026 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5027 tmp &= ~(0xF << 28);
5028 tmp |= (4 << 28);
5029 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5030 }
5031
5032 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5033 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5034 tmp |= SBI_DBUFF0_ENABLE;
5035 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5036
5037 mutex_unlock(&dev_priv->dpio_lock);
5038 }
5039
5040 /*
5041 * Initialize reference clocks when the driver loads
5042 */
5043 void intel_init_pch_refclk(struct drm_device *dev)
5044 {
5045 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5046 ironlake_init_pch_refclk(dev);
5047 else if (HAS_PCH_LPT(dev))
5048 lpt_init_pch_refclk(dev);
5049 }
5050
5051 static int ironlake_get_refclk(struct drm_crtc *crtc)
5052 {
5053 struct drm_device *dev = crtc->dev;
5054 struct drm_i915_private *dev_priv = dev->dev_private;
5055 struct intel_encoder *encoder;
5056 struct intel_encoder *edp_encoder = NULL;
5057 int num_connectors = 0;
5058 bool is_lvds = false;
5059
5060 for_each_encoder_on_crtc(dev, crtc, encoder) {
5061 switch (encoder->type) {
5062 case INTEL_OUTPUT_LVDS:
5063 is_lvds = true;
5064 break;
5065 case INTEL_OUTPUT_EDP:
5066 edp_encoder = encoder;
5067 break;
5068 }
5069 num_connectors++;
5070 }
5071
5072 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5073 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5074 dev_priv->lvds_ssc_freq);
5075 return dev_priv->lvds_ssc_freq * 1000;
5076 }
5077
5078 return 120000;
5079 }
5080
5081 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5082 struct drm_display_mode *adjusted_mode,
5083 bool dither)
5084 {
5085 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5087 int pipe = intel_crtc->pipe;
5088 uint32_t val;
5089
5090 val = I915_READ(PIPECONF(pipe));
5091
5092 val &= ~PIPECONF_BPC_MASK;
5093 switch (intel_crtc->config.pipe_bpp) {
5094 case 18:
5095 val |= PIPECONF_6BPC;
5096 break;
5097 case 24:
5098 val |= PIPECONF_8BPC;
5099 break;
5100 case 30:
5101 val |= PIPECONF_10BPC;
5102 break;
5103 case 36:
5104 val |= PIPECONF_12BPC;
5105 break;
5106 default:
5107 /* Case prevented by intel_choose_pipe_bpp_dither. */
5108 BUG();
5109 }
5110
5111 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5112 if (dither)
5113 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5114
5115 val &= ~PIPECONF_INTERLACE_MASK;
5116 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5117 val |= PIPECONF_INTERLACED_ILK;
5118 else
5119 val |= PIPECONF_PROGRESSIVE;
5120
5121 if (intel_crtc->config.limited_color_range)
5122 val |= PIPECONF_COLOR_RANGE_SELECT;
5123 else
5124 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5125
5126 I915_WRITE(PIPECONF(pipe), val);
5127 POSTING_READ(PIPECONF(pipe));
5128 }
5129
5130 /*
5131 * Set up the pipe CSC unit.
5132 *
5133 * Currently only full range RGB to limited range RGB conversion
5134 * is supported, but eventually this should handle various
5135 * RGB<->YCbCr scenarios as well.
5136 */
5137 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5138 {
5139 struct drm_device *dev = crtc->dev;
5140 struct drm_i915_private *dev_priv = dev->dev_private;
5141 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5142 int pipe = intel_crtc->pipe;
5143 uint16_t coeff = 0x7800; /* 1.0 */
5144
5145 /*
5146 * TODO: Check what kind of values actually come out of the pipe
5147 * with these coeff/postoff values and adjust to get the best
5148 * accuracy. Perhaps we even need to take the bpc value into
5149 * consideration.
5150 */
5151
5152 if (intel_crtc->config.limited_color_range)
5153 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5154
5155 /*
5156 * GY/GU and RY/RU should be the other way around according
5157 * to BSpec, but reality doesn't agree. Just set them up in
5158 * a way that results in the correct picture.
5159 */
5160 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5161 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5162
5163 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5164 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5165
5166 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5167 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5168
5169 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5170 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5171 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5172
5173 if (INTEL_INFO(dev)->gen > 6) {
5174 uint16_t postoff = 0;
5175
5176 if (intel_crtc->config.limited_color_range)
5177 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5178
5179 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5180 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5181 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5182
5183 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5184 } else {
5185 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5186
5187 if (intel_crtc->config.limited_color_range)
5188 mode |= CSC_BLACK_SCREEN_OFFSET;
5189
5190 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5191 }
5192 }
5193
5194 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5195 struct drm_display_mode *adjusted_mode,
5196 bool dither)
5197 {
5198 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5200 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5201 uint32_t val;
5202
5203 val = I915_READ(PIPECONF(cpu_transcoder));
5204
5205 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5206 if (dither)
5207 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5208
5209 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5210 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5211 val |= PIPECONF_INTERLACED_ILK;
5212 else
5213 val |= PIPECONF_PROGRESSIVE;
5214
5215 I915_WRITE(PIPECONF(cpu_transcoder), val);
5216 POSTING_READ(PIPECONF(cpu_transcoder));
5217 }
5218
5219 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5220 struct drm_display_mode *adjusted_mode,
5221 intel_clock_t *clock,
5222 bool *has_reduced_clock,
5223 intel_clock_t *reduced_clock)
5224 {
5225 struct drm_device *dev = crtc->dev;
5226 struct drm_i915_private *dev_priv = dev->dev_private;
5227 struct intel_encoder *intel_encoder;
5228 int refclk;
5229 const intel_limit_t *limit;
5230 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5231
5232 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5233 switch (intel_encoder->type) {
5234 case INTEL_OUTPUT_LVDS:
5235 is_lvds = true;
5236 break;
5237 case INTEL_OUTPUT_SDVO:
5238 case INTEL_OUTPUT_HDMI:
5239 is_sdvo = true;
5240 if (intel_encoder->needs_tv_clock)
5241 is_tv = true;
5242 break;
5243 case INTEL_OUTPUT_TVOUT:
5244 is_tv = true;
5245 break;
5246 }
5247 }
5248
5249 refclk = ironlake_get_refclk(crtc);
5250
5251 /*
5252 * Returns a set of divisors for the desired target clock with the given
5253 * refclk, or FALSE. The returned values represent the clock equation:
5254 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5255 */
5256 limit = intel_limit(crtc, refclk);
5257 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5258 clock);
5259 if (!ret)
5260 return false;
5261
5262 if (is_lvds && dev_priv->lvds_downclock_avail) {
5263 /*
5264 * Ensure we match the reduced clock's P to the target clock.
5265 * If the clocks don't match, we can't switch the display clock
5266 * by using the FP0/FP1. In such case we will disable the LVDS
5267 * downclock feature.
5268 */
5269 *has_reduced_clock = limit->find_pll(limit, crtc,
5270 dev_priv->lvds_downclock,
5271 refclk,
5272 clock,
5273 reduced_clock);
5274 }
5275
5276 if (is_sdvo && is_tv)
5277 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5278
5279 return true;
5280 }
5281
5282 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5283 {
5284 struct drm_i915_private *dev_priv = dev->dev_private;
5285 uint32_t temp;
5286
5287 temp = I915_READ(SOUTH_CHICKEN1);
5288 if (temp & FDI_BC_BIFURCATION_SELECT)
5289 return;
5290
5291 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5292 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5293
5294 temp |= FDI_BC_BIFURCATION_SELECT;
5295 DRM_DEBUG_KMS("enabling fdi C rx\n");
5296 I915_WRITE(SOUTH_CHICKEN1, temp);
5297 POSTING_READ(SOUTH_CHICKEN1);
5298 }
5299
5300 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5301 {
5302 struct drm_device *dev = intel_crtc->base.dev;
5303 struct drm_i915_private *dev_priv = dev->dev_private;
5304 struct intel_crtc *pipe_B_crtc =
5305 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5306
5307 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5308 intel_crtc->pipe, intel_crtc->fdi_lanes);
5309 if (intel_crtc->fdi_lanes > 4) {
5310 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5311 intel_crtc->pipe, intel_crtc->fdi_lanes);
5312 /* Clamp lanes to avoid programming the hw with bogus values. */
5313 intel_crtc->fdi_lanes = 4;
5314
5315 return false;
5316 }
5317
5318 if (INTEL_INFO(dev)->num_pipes == 2)
5319 return true;
5320
5321 switch (intel_crtc->pipe) {
5322 case PIPE_A:
5323 return true;
5324 case PIPE_B:
5325 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5326 intel_crtc->fdi_lanes > 2) {
5327 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5328 intel_crtc->pipe, intel_crtc->fdi_lanes);
5329 /* Clamp lanes to avoid programming the hw with bogus values. */
5330 intel_crtc->fdi_lanes = 2;
5331
5332 return false;
5333 }
5334
5335 if (intel_crtc->fdi_lanes > 2)
5336 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5337 else
5338 cpt_enable_fdi_bc_bifurcation(dev);
5339
5340 return true;
5341 case PIPE_C:
5342 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5343 if (intel_crtc->fdi_lanes > 2) {
5344 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5345 intel_crtc->pipe, intel_crtc->fdi_lanes);
5346 /* Clamp lanes to avoid programming the hw with bogus values. */
5347 intel_crtc->fdi_lanes = 2;
5348
5349 return false;
5350 }
5351 } else {
5352 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5353 return false;
5354 }
5355
5356 cpt_enable_fdi_bc_bifurcation(dev);
5357
5358 return true;
5359 default:
5360 BUG();
5361 }
5362 }
5363
5364 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5365 {
5366 /*
5367 * Account for spread spectrum to avoid
5368 * oversubscribing the link. Max center spread
5369 * is 2.5%; use 5% for safety's sake.
5370 */
5371 u32 bps = target_clock * bpp * 21 / 20;
5372 return bps / (link_bw * 8) + 1;
5373 }
5374
5375 void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5376 struct intel_link_m_n *m_n)
5377 {
5378 struct drm_device *dev = crtc->base.dev;
5379 struct drm_i915_private *dev_priv = dev->dev_private;
5380 int pipe = crtc->pipe;
5381
5382 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5383 I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5384 I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5385 I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5386 }
5387
5388 void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5389 struct intel_link_m_n *m_n)
5390 {
5391 struct drm_device *dev = crtc->base.dev;
5392 struct drm_i915_private *dev_priv = dev->dev_private;
5393 int pipe = crtc->pipe;
5394 enum transcoder transcoder = crtc->cpu_transcoder;
5395
5396 if (INTEL_INFO(dev)->gen >= 5) {
5397 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5398 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5399 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5400 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5401 } else {
5402 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5403 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5404 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5405 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5406 }
5407 }
5408
5409 static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
5410 {
5411 struct drm_device *dev = crtc->dev;
5412 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5413 struct drm_display_mode *adjusted_mode =
5414 &intel_crtc->config.adjusted_mode;
5415 struct intel_link_m_n m_n = {0};
5416 int target_clock, lane, link_bw;
5417 uint32_t bps;
5418
5419 /* FDI is a binary signal running at ~2.7GHz, encoding
5420 * each output octet as 10 bits. The actual frequency
5421 * is stored as a divider into a 100MHz clock, and the
5422 * mode pixel clock is stored in units of 1KHz.
5423 * Hence the bw of each lane in terms of the mode signal
5424 * is:
5425 */
5426 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5427
5428 if (intel_crtc->config.pixel_target_clock)
5429 target_clock = intel_crtc->config.pixel_target_clock;
5430 else
5431 target_clock = adjusted_mode->clock;
5432
5433 lane = ironlake_get_lanes_required(target_clock, link_bw,
5434 intel_crtc->config.pipe_bpp);
5435
5436 intel_crtc->fdi_lanes = lane;
5437
5438 if (intel_crtc->config.pixel_multiplier > 1)
5439 link_bw *= intel_crtc->config.pixel_multiplier;
5440 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5441 link_bw, &m_n);
5442
5443 intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
5444 }
5445
5446 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5447 intel_clock_t *clock, u32 fp)
5448 {
5449 struct drm_crtc *crtc = &intel_crtc->base;
5450 struct drm_device *dev = crtc->dev;
5451 struct drm_i915_private *dev_priv = dev->dev_private;
5452 struct intel_encoder *intel_encoder;
5453 uint32_t dpll;
5454 int factor, num_connectors = 0;
5455 bool is_lvds = false, is_sdvo = false, is_tv = false;
5456
5457 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5458 switch (intel_encoder->type) {
5459 case INTEL_OUTPUT_LVDS:
5460 is_lvds = true;
5461 break;
5462 case INTEL_OUTPUT_SDVO:
5463 case INTEL_OUTPUT_HDMI:
5464 is_sdvo = true;
5465 if (intel_encoder->needs_tv_clock)
5466 is_tv = true;
5467 break;
5468 case INTEL_OUTPUT_TVOUT:
5469 is_tv = true;
5470 break;
5471 }
5472
5473 num_connectors++;
5474 }
5475
5476 /* Enable autotuning of the PLL clock (if permissible) */
5477 factor = 21;
5478 if (is_lvds) {
5479 if ((intel_panel_use_ssc(dev_priv) &&
5480 dev_priv->lvds_ssc_freq == 100) ||
5481 intel_is_dual_link_lvds(dev))
5482 factor = 25;
5483 } else if (is_sdvo && is_tv)
5484 factor = 20;
5485
5486 if (clock->m < factor * clock->n)
5487 fp |= FP_CB_TUNE;
5488
5489 dpll = 0;
5490
5491 if (is_lvds)
5492 dpll |= DPLLB_MODE_LVDS;
5493 else
5494 dpll |= DPLLB_MODE_DAC_SERIAL;
5495 if (is_sdvo) {
5496 if (intel_crtc->config.pixel_multiplier > 1) {
5497 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5498 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5499 }
5500 dpll |= DPLL_DVO_HIGH_SPEED;
5501 }
5502 if (intel_crtc->config.has_dp_encoder &&
5503 intel_crtc->config.has_pch_encoder)
5504 dpll |= DPLL_DVO_HIGH_SPEED;
5505
5506 /* compute bitmask from p1 value */
5507 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5508 /* also FPA1 */
5509 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5510
5511 switch (clock->p2) {
5512 case 5:
5513 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5514 break;
5515 case 7:
5516 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5517 break;
5518 case 10:
5519 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5520 break;
5521 case 14:
5522 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5523 break;
5524 }
5525
5526 if (is_sdvo && is_tv)
5527 dpll |= PLL_REF_INPUT_TVCLKINBC;
5528 else if (is_tv)
5529 /* XXX: just matching BIOS for now */
5530 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5531 dpll |= 3;
5532 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5533 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5534 else
5535 dpll |= PLL_REF_INPUT_DREFCLK;
5536
5537 return dpll;
5538 }
5539
5540 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5541 int x, int y,
5542 struct drm_framebuffer *fb)
5543 {
5544 struct drm_device *dev = crtc->dev;
5545 struct drm_i915_private *dev_priv = dev->dev_private;
5546 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5547 struct drm_display_mode *adjusted_mode =
5548 &intel_crtc->config.adjusted_mode;
5549 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5550 int pipe = intel_crtc->pipe;
5551 int plane = intel_crtc->plane;
5552 int num_connectors = 0;
5553 intel_clock_t clock, reduced_clock;
5554 u32 dpll, fp = 0, fp2 = 0;
5555 bool ok, has_reduced_clock = false;
5556 bool is_lvds = false;
5557 struct intel_encoder *encoder;
5558 int ret;
5559 bool dither, fdi_config_ok;
5560
5561 for_each_encoder_on_crtc(dev, crtc, encoder) {
5562 switch (encoder->type) {
5563 case INTEL_OUTPUT_LVDS:
5564 is_lvds = true;
5565 break;
5566 }
5567
5568 num_connectors++;
5569 }
5570
5571 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5572 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5573
5574 intel_crtc->cpu_transcoder = pipe;
5575
5576 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5577 &has_reduced_clock, &reduced_clock);
5578 if (!ok) {
5579 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5580 return -EINVAL;
5581 }
5582
5583 /* Ensure that the cursor is valid for the new mode before changing... */
5584 intel_crtc_update_cursor(crtc, true);
5585
5586 /* determine panel color depth */
5587 dither = intel_crtc->config.dither;
5588 if (is_lvds && dev_priv->lvds_dither)
5589 dither = true;
5590
5591 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5592 if (has_reduced_clock)
5593 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5594 reduced_clock.m2;
5595
5596 dpll = ironlake_compute_dpll(intel_crtc, &clock, fp);
5597
5598 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5599 drm_mode_debug_printmodeline(mode);
5600
5601 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5602 if (intel_crtc->config.has_pch_encoder) {
5603 struct intel_pch_pll *pll;
5604
5605 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5606 if (pll == NULL) {
5607 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5608 pipe);
5609 return -EINVAL;
5610 }
5611 } else
5612 intel_put_pch_pll(intel_crtc);
5613
5614 if (intel_crtc->config.has_dp_encoder)
5615 intel_dp_set_m_n(intel_crtc);
5616
5617 for_each_encoder_on_crtc(dev, crtc, encoder)
5618 if (encoder->pre_pll_enable)
5619 encoder->pre_pll_enable(encoder);
5620
5621 if (intel_crtc->pch_pll) {
5622 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5623
5624 /* Wait for the clocks to stabilize. */
5625 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5626 udelay(150);
5627
5628 /* The pixel multiplier can only be updated once the
5629 * DPLL is enabled and the clocks are stable.
5630 *
5631 * So write it again.
5632 */
5633 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5634 }
5635
5636 intel_crtc->lowfreq_avail = false;
5637 if (intel_crtc->pch_pll) {
5638 if (is_lvds && has_reduced_clock && i915_powersave) {
5639 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5640 intel_crtc->lowfreq_avail = true;
5641 } else {
5642 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5643 }
5644 }
5645
5646 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5647
5648 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5649 * ironlake_check_fdi_lanes. */
5650 intel_crtc->fdi_lanes = 0;
5651 if (intel_crtc->config.has_pch_encoder)
5652 ironlake_fdi_set_m_n(crtc);
5653
5654 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5655
5656 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5657
5658 intel_wait_for_vblank(dev, pipe);
5659
5660 /* Set up the display plane register */
5661 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5662 POSTING_READ(DSPCNTR(plane));
5663
5664 ret = intel_pipe_set_base(crtc, x, y, fb);
5665
5666 intel_update_watermarks(dev);
5667
5668 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5669
5670 return fdi_config_ok ? ret : -EINVAL;
5671 }
5672
5673 static void haswell_modeset_global_resources(struct drm_device *dev)
5674 {
5675 struct drm_i915_private *dev_priv = dev->dev_private;
5676 bool enable = false;
5677 struct intel_crtc *crtc;
5678 struct intel_encoder *encoder;
5679
5680 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5681 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5682 enable = true;
5683 /* XXX: Should check for edp transcoder here, but thanks to init
5684 * sequence that's not yet available. Just in case desktop eDP
5685 * on PORT D is possible on haswell, too. */
5686 }
5687
5688 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5689 base.head) {
5690 if (encoder->type != INTEL_OUTPUT_EDP &&
5691 encoder->connectors_active)
5692 enable = true;
5693 }
5694
5695 /* Even the eDP panel fitter is outside the always-on well. */
5696 if (dev_priv->pch_pf_size)
5697 enable = true;
5698
5699 intel_set_power_well(dev, enable);
5700 }
5701
5702 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5703 int x, int y,
5704 struct drm_framebuffer *fb)
5705 {
5706 struct drm_device *dev = crtc->dev;
5707 struct drm_i915_private *dev_priv = dev->dev_private;
5708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5709 struct drm_display_mode *adjusted_mode =
5710 &intel_crtc->config.adjusted_mode;
5711 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5712 int pipe = intel_crtc->pipe;
5713 int plane = intel_crtc->plane;
5714 int num_connectors = 0;
5715 bool is_cpu_edp = false;
5716 struct intel_encoder *encoder;
5717 int ret;
5718 bool dither;
5719
5720 for_each_encoder_on_crtc(dev, crtc, encoder) {
5721 switch (encoder->type) {
5722 case INTEL_OUTPUT_EDP:
5723 if (!intel_encoder_is_pch_edp(&encoder->base))
5724 is_cpu_edp = true;
5725 break;
5726 }
5727
5728 num_connectors++;
5729 }
5730
5731 if (is_cpu_edp)
5732 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5733 else
5734 intel_crtc->cpu_transcoder = pipe;
5735
5736 /* We are not sure yet this won't happen. */
5737 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5738 INTEL_PCH_TYPE(dev));
5739
5740 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5741 num_connectors, pipe_name(pipe));
5742
5743 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5744 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5745
5746 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5747
5748 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5749 return -EINVAL;
5750
5751 /* Ensure that the cursor is valid for the new mode before changing... */
5752 intel_crtc_update_cursor(crtc, true);
5753
5754 /* determine panel color depth */
5755 dither = intel_crtc->config.dither;
5756
5757 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5758 drm_mode_debug_printmodeline(mode);
5759
5760 if (intel_crtc->config.has_dp_encoder)
5761 intel_dp_set_m_n(intel_crtc);
5762
5763 intel_crtc->lowfreq_avail = false;
5764
5765 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5766
5767 if (intel_crtc->config.has_pch_encoder)
5768 ironlake_fdi_set_m_n(crtc);
5769
5770 haswell_set_pipeconf(crtc, adjusted_mode, dither);
5771
5772 intel_set_pipe_csc(crtc);
5773
5774 /* Set up the display plane register */
5775 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5776 POSTING_READ(DSPCNTR(plane));
5777
5778 ret = intel_pipe_set_base(crtc, x, y, fb);
5779
5780 intel_update_watermarks(dev);
5781
5782 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5783
5784 return ret;
5785 }
5786
5787 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5788 int x, int y,
5789 struct drm_framebuffer *fb)
5790 {
5791 struct drm_device *dev = crtc->dev;
5792 struct drm_i915_private *dev_priv = dev->dev_private;
5793 struct drm_encoder_helper_funcs *encoder_funcs;
5794 struct intel_encoder *encoder;
5795 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5796 struct drm_display_mode *adjusted_mode =
5797 &intel_crtc->config.adjusted_mode;
5798 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5799 int pipe = intel_crtc->pipe;
5800 int ret;
5801
5802 drm_vblank_pre_modeset(dev, pipe);
5803
5804 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5805
5806 drm_vblank_post_modeset(dev, pipe);
5807
5808 if (ret != 0)
5809 return ret;
5810
5811 for_each_encoder_on_crtc(dev, crtc, encoder) {
5812 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5813 encoder->base.base.id,
5814 drm_get_encoder_name(&encoder->base),
5815 mode->base.id, mode->name);
5816 if (encoder->mode_set) {
5817 encoder->mode_set(encoder);
5818 } else {
5819 encoder_funcs = encoder->base.helper_private;
5820 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5821 }
5822 }
5823
5824 return 0;
5825 }
5826
5827 static bool intel_eld_uptodate(struct drm_connector *connector,
5828 int reg_eldv, uint32_t bits_eldv,
5829 int reg_elda, uint32_t bits_elda,
5830 int reg_edid)
5831 {
5832 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5833 uint8_t *eld = connector->eld;
5834 uint32_t i;
5835
5836 i = I915_READ(reg_eldv);
5837 i &= bits_eldv;
5838
5839 if (!eld[0])
5840 return !i;
5841
5842 if (!i)
5843 return false;
5844
5845 i = I915_READ(reg_elda);
5846 i &= ~bits_elda;
5847 I915_WRITE(reg_elda, i);
5848
5849 for (i = 0; i < eld[2]; i++)
5850 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5851 return false;
5852
5853 return true;
5854 }
5855
5856 static void g4x_write_eld(struct drm_connector *connector,
5857 struct drm_crtc *crtc)
5858 {
5859 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5860 uint8_t *eld = connector->eld;
5861 uint32_t eldv;
5862 uint32_t len;
5863 uint32_t i;
5864
5865 i = I915_READ(G4X_AUD_VID_DID);
5866
5867 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5868 eldv = G4X_ELDV_DEVCL_DEVBLC;
5869 else
5870 eldv = G4X_ELDV_DEVCTG;
5871
5872 if (intel_eld_uptodate(connector,
5873 G4X_AUD_CNTL_ST, eldv,
5874 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5875 G4X_HDMIW_HDMIEDID))
5876 return;
5877
5878 i = I915_READ(G4X_AUD_CNTL_ST);
5879 i &= ~(eldv | G4X_ELD_ADDR);
5880 len = (i >> 9) & 0x1f; /* ELD buffer size */
5881 I915_WRITE(G4X_AUD_CNTL_ST, i);
5882
5883 if (!eld[0])
5884 return;
5885
5886 len = min_t(uint8_t, eld[2], len);
5887 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5888 for (i = 0; i < len; i++)
5889 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5890
5891 i = I915_READ(G4X_AUD_CNTL_ST);
5892 i |= eldv;
5893 I915_WRITE(G4X_AUD_CNTL_ST, i);
5894 }
5895
5896 static void haswell_write_eld(struct drm_connector *connector,
5897 struct drm_crtc *crtc)
5898 {
5899 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5900 uint8_t *eld = connector->eld;
5901 struct drm_device *dev = crtc->dev;
5902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5903 uint32_t eldv;
5904 uint32_t i;
5905 int len;
5906 int pipe = to_intel_crtc(crtc)->pipe;
5907 int tmp;
5908
5909 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5910 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5911 int aud_config = HSW_AUD_CFG(pipe);
5912 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5913
5914
5915 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5916
5917 /* Audio output enable */
5918 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5919 tmp = I915_READ(aud_cntrl_st2);
5920 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5921 I915_WRITE(aud_cntrl_st2, tmp);
5922
5923 /* Wait for 1 vertical blank */
5924 intel_wait_for_vblank(dev, pipe);
5925
5926 /* Set ELD valid state */
5927 tmp = I915_READ(aud_cntrl_st2);
5928 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5929 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5930 I915_WRITE(aud_cntrl_st2, tmp);
5931 tmp = I915_READ(aud_cntrl_st2);
5932 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5933
5934 /* Enable HDMI mode */
5935 tmp = I915_READ(aud_config);
5936 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5937 /* clear N_programing_enable and N_value_index */
5938 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5939 I915_WRITE(aud_config, tmp);
5940
5941 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5942
5943 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5944 intel_crtc->eld_vld = true;
5945
5946 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5947 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5948 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5949 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5950 } else
5951 I915_WRITE(aud_config, 0);
5952
5953 if (intel_eld_uptodate(connector,
5954 aud_cntrl_st2, eldv,
5955 aud_cntl_st, IBX_ELD_ADDRESS,
5956 hdmiw_hdmiedid))
5957 return;
5958
5959 i = I915_READ(aud_cntrl_st2);
5960 i &= ~eldv;
5961 I915_WRITE(aud_cntrl_st2, i);
5962
5963 if (!eld[0])
5964 return;
5965
5966 i = I915_READ(aud_cntl_st);
5967 i &= ~IBX_ELD_ADDRESS;
5968 I915_WRITE(aud_cntl_st, i);
5969 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5970 DRM_DEBUG_DRIVER("port num:%d\n", i);
5971
5972 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5973 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5974 for (i = 0; i < len; i++)
5975 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5976
5977 i = I915_READ(aud_cntrl_st2);
5978 i |= eldv;
5979 I915_WRITE(aud_cntrl_st2, i);
5980
5981 }
5982
5983 static void ironlake_write_eld(struct drm_connector *connector,
5984 struct drm_crtc *crtc)
5985 {
5986 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5987 uint8_t *eld = connector->eld;
5988 uint32_t eldv;
5989 uint32_t i;
5990 int len;
5991 int hdmiw_hdmiedid;
5992 int aud_config;
5993 int aud_cntl_st;
5994 int aud_cntrl_st2;
5995 int pipe = to_intel_crtc(crtc)->pipe;
5996
5997 if (HAS_PCH_IBX(connector->dev)) {
5998 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5999 aud_config = IBX_AUD_CFG(pipe);
6000 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6001 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6002 } else {
6003 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6004 aud_config = CPT_AUD_CFG(pipe);
6005 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6006 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6007 }
6008
6009 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6010
6011 i = I915_READ(aud_cntl_st);
6012 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6013 if (!i) {
6014 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6015 /* operate blindly on all ports */
6016 eldv = IBX_ELD_VALIDB;
6017 eldv |= IBX_ELD_VALIDB << 4;
6018 eldv |= IBX_ELD_VALIDB << 8;
6019 } else {
6020 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6021 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6022 }
6023
6024 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6025 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6026 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6027 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6028 } else
6029 I915_WRITE(aud_config, 0);
6030
6031 if (intel_eld_uptodate(connector,
6032 aud_cntrl_st2, eldv,
6033 aud_cntl_st, IBX_ELD_ADDRESS,
6034 hdmiw_hdmiedid))
6035 return;
6036
6037 i = I915_READ(aud_cntrl_st2);
6038 i &= ~eldv;
6039 I915_WRITE(aud_cntrl_st2, i);
6040
6041 if (!eld[0])
6042 return;
6043
6044 i = I915_READ(aud_cntl_st);
6045 i &= ~IBX_ELD_ADDRESS;
6046 I915_WRITE(aud_cntl_st, i);
6047
6048 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6049 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6050 for (i = 0; i < len; i++)
6051 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6052
6053 i = I915_READ(aud_cntrl_st2);
6054 i |= eldv;
6055 I915_WRITE(aud_cntrl_st2, i);
6056 }
6057
6058 void intel_write_eld(struct drm_encoder *encoder,
6059 struct drm_display_mode *mode)
6060 {
6061 struct drm_crtc *crtc = encoder->crtc;
6062 struct drm_connector *connector;
6063 struct drm_device *dev = encoder->dev;
6064 struct drm_i915_private *dev_priv = dev->dev_private;
6065
6066 connector = drm_select_eld(encoder, mode);
6067 if (!connector)
6068 return;
6069
6070 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6071 connector->base.id,
6072 drm_get_connector_name(connector),
6073 connector->encoder->base.id,
6074 drm_get_encoder_name(connector->encoder));
6075
6076 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6077
6078 if (dev_priv->display.write_eld)
6079 dev_priv->display.write_eld(connector, crtc);
6080 }
6081
6082 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6083 void intel_crtc_load_lut(struct drm_crtc *crtc)
6084 {
6085 struct drm_device *dev = crtc->dev;
6086 struct drm_i915_private *dev_priv = dev->dev_private;
6087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6088 int palreg = PALETTE(intel_crtc->pipe);
6089 int i;
6090
6091 /* The clocks have to be on to load the palette. */
6092 if (!crtc->enabled || !intel_crtc->active)
6093 return;
6094
6095 /* use legacy palette for Ironlake */
6096 if (HAS_PCH_SPLIT(dev))
6097 palreg = LGC_PALETTE(intel_crtc->pipe);
6098
6099 for (i = 0; i < 256; i++) {
6100 I915_WRITE(palreg + 4 * i,
6101 (intel_crtc->lut_r[i] << 16) |
6102 (intel_crtc->lut_g[i] << 8) |
6103 intel_crtc->lut_b[i]);
6104 }
6105 }
6106
6107 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6108 {
6109 struct drm_device *dev = crtc->dev;
6110 struct drm_i915_private *dev_priv = dev->dev_private;
6111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6112 bool visible = base != 0;
6113 u32 cntl;
6114
6115 if (intel_crtc->cursor_visible == visible)
6116 return;
6117
6118 cntl = I915_READ(_CURACNTR);
6119 if (visible) {
6120 /* On these chipsets we can only modify the base whilst
6121 * the cursor is disabled.
6122 */
6123 I915_WRITE(_CURABASE, base);
6124
6125 cntl &= ~(CURSOR_FORMAT_MASK);
6126 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6127 cntl |= CURSOR_ENABLE |
6128 CURSOR_GAMMA_ENABLE |
6129 CURSOR_FORMAT_ARGB;
6130 } else
6131 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6132 I915_WRITE(_CURACNTR, cntl);
6133
6134 intel_crtc->cursor_visible = visible;
6135 }
6136
6137 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6138 {
6139 struct drm_device *dev = crtc->dev;
6140 struct drm_i915_private *dev_priv = dev->dev_private;
6141 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6142 int pipe = intel_crtc->pipe;
6143 bool visible = base != 0;
6144
6145 if (intel_crtc->cursor_visible != visible) {
6146 uint32_t cntl = I915_READ(CURCNTR(pipe));
6147 if (base) {
6148 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6149 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6150 cntl |= pipe << 28; /* Connect to correct pipe */
6151 } else {
6152 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6153 cntl |= CURSOR_MODE_DISABLE;
6154 }
6155 I915_WRITE(CURCNTR(pipe), cntl);
6156
6157 intel_crtc->cursor_visible = visible;
6158 }
6159 /* and commit changes on next vblank */
6160 I915_WRITE(CURBASE(pipe), base);
6161 }
6162
6163 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6164 {
6165 struct drm_device *dev = crtc->dev;
6166 struct drm_i915_private *dev_priv = dev->dev_private;
6167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6168 int pipe = intel_crtc->pipe;
6169 bool visible = base != 0;
6170
6171 if (intel_crtc->cursor_visible != visible) {
6172 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6173 if (base) {
6174 cntl &= ~CURSOR_MODE;
6175 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6176 } else {
6177 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6178 cntl |= CURSOR_MODE_DISABLE;
6179 }
6180 if (IS_HASWELL(dev))
6181 cntl |= CURSOR_PIPE_CSC_ENABLE;
6182 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6183
6184 intel_crtc->cursor_visible = visible;
6185 }
6186 /* and commit changes on next vblank */
6187 I915_WRITE(CURBASE_IVB(pipe), base);
6188 }
6189
6190 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6191 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6192 bool on)
6193 {
6194 struct drm_device *dev = crtc->dev;
6195 struct drm_i915_private *dev_priv = dev->dev_private;
6196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6197 int pipe = intel_crtc->pipe;
6198 int x = intel_crtc->cursor_x;
6199 int y = intel_crtc->cursor_y;
6200 u32 base, pos;
6201 bool visible;
6202
6203 pos = 0;
6204
6205 if (on && crtc->enabled && crtc->fb) {
6206 base = intel_crtc->cursor_addr;
6207 if (x > (int) crtc->fb->width)
6208 base = 0;
6209
6210 if (y > (int) crtc->fb->height)
6211 base = 0;
6212 } else
6213 base = 0;
6214
6215 if (x < 0) {
6216 if (x + intel_crtc->cursor_width < 0)
6217 base = 0;
6218
6219 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6220 x = -x;
6221 }
6222 pos |= x << CURSOR_X_SHIFT;
6223
6224 if (y < 0) {
6225 if (y + intel_crtc->cursor_height < 0)
6226 base = 0;
6227
6228 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6229 y = -y;
6230 }
6231 pos |= y << CURSOR_Y_SHIFT;
6232
6233 visible = base != 0;
6234 if (!visible && !intel_crtc->cursor_visible)
6235 return;
6236
6237 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6238 I915_WRITE(CURPOS_IVB(pipe), pos);
6239 ivb_update_cursor(crtc, base);
6240 } else {
6241 I915_WRITE(CURPOS(pipe), pos);
6242 if (IS_845G(dev) || IS_I865G(dev))
6243 i845_update_cursor(crtc, base);
6244 else
6245 i9xx_update_cursor(crtc, base);
6246 }
6247 }
6248
6249 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6250 struct drm_file *file,
6251 uint32_t handle,
6252 uint32_t width, uint32_t height)
6253 {
6254 struct drm_device *dev = crtc->dev;
6255 struct drm_i915_private *dev_priv = dev->dev_private;
6256 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6257 struct drm_i915_gem_object *obj;
6258 uint32_t addr;
6259 int ret;
6260
6261 /* if we want to turn off the cursor ignore width and height */
6262 if (!handle) {
6263 DRM_DEBUG_KMS("cursor off\n");
6264 addr = 0;
6265 obj = NULL;
6266 mutex_lock(&dev->struct_mutex);
6267 goto finish;
6268 }
6269
6270 /* Currently we only support 64x64 cursors */
6271 if (width != 64 || height != 64) {
6272 DRM_ERROR("we currently only support 64x64 cursors\n");
6273 return -EINVAL;
6274 }
6275
6276 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6277 if (&obj->base == NULL)
6278 return -ENOENT;
6279
6280 if (obj->base.size < width * height * 4) {
6281 DRM_ERROR("buffer is to small\n");
6282 ret = -ENOMEM;
6283 goto fail;
6284 }
6285
6286 /* we only need to pin inside GTT if cursor is non-phy */
6287 mutex_lock(&dev->struct_mutex);
6288 if (!dev_priv->info->cursor_needs_physical) {
6289 unsigned alignment;
6290
6291 if (obj->tiling_mode) {
6292 DRM_ERROR("cursor cannot be tiled\n");
6293 ret = -EINVAL;
6294 goto fail_locked;
6295 }
6296
6297 /* Note that the w/a also requires 2 PTE of padding following
6298 * the bo. We currently fill all unused PTE with the shadow
6299 * page and so we should always have valid PTE following the
6300 * cursor preventing the VT-d warning.
6301 */
6302 alignment = 0;
6303 if (need_vtd_wa(dev))
6304 alignment = 64*1024;
6305
6306 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6307 if (ret) {
6308 DRM_ERROR("failed to move cursor bo into the GTT\n");
6309 goto fail_locked;
6310 }
6311
6312 ret = i915_gem_object_put_fence(obj);
6313 if (ret) {
6314 DRM_ERROR("failed to release fence for cursor");
6315 goto fail_unpin;
6316 }
6317
6318 addr = obj->gtt_offset;
6319 } else {
6320 int align = IS_I830(dev) ? 16 * 1024 : 256;
6321 ret = i915_gem_attach_phys_object(dev, obj,
6322 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6323 align);
6324 if (ret) {
6325 DRM_ERROR("failed to attach phys object\n");
6326 goto fail_locked;
6327 }
6328 addr = obj->phys_obj->handle->busaddr;
6329 }
6330
6331 if (IS_GEN2(dev))
6332 I915_WRITE(CURSIZE, (height << 12) | width);
6333
6334 finish:
6335 if (intel_crtc->cursor_bo) {
6336 if (dev_priv->info->cursor_needs_physical) {
6337 if (intel_crtc->cursor_bo != obj)
6338 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6339 } else
6340 i915_gem_object_unpin(intel_crtc->cursor_bo);
6341 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6342 }
6343
6344 mutex_unlock(&dev->struct_mutex);
6345
6346 intel_crtc->cursor_addr = addr;
6347 intel_crtc->cursor_bo = obj;
6348 intel_crtc->cursor_width = width;
6349 intel_crtc->cursor_height = height;
6350
6351 intel_crtc_update_cursor(crtc, true);
6352
6353 return 0;
6354 fail_unpin:
6355 i915_gem_object_unpin(obj);
6356 fail_locked:
6357 mutex_unlock(&dev->struct_mutex);
6358 fail:
6359 drm_gem_object_unreference_unlocked(&obj->base);
6360 return ret;
6361 }
6362
6363 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6364 {
6365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6366
6367 intel_crtc->cursor_x = x;
6368 intel_crtc->cursor_y = y;
6369
6370 intel_crtc_update_cursor(crtc, true);
6371
6372 return 0;
6373 }
6374
6375 /** Sets the color ramps on behalf of RandR */
6376 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6377 u16 blue, int regno)
6378 {
6379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6380
6381 intel_crtc->lut_r[regno] = red >> 8;
6382 intel_crtc->lut_g[regno] = green >> 8;
6383 intel_crtc->lut_b[regno] = blue >> 8;
6384 }
6385
6386 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6387 u16 *blue, int regno)
6388 {
6389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6390
6391 *red = intel_crtc->lut_r[regno] << 8;
6392 *green = intel_crtc->lut_g[regno] << 8;
6393 *blue = intel_crtc->lut_b[regno] << 8;
6394 }
6395
6396 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6397 u16 *blue, uint32_t start, uint32_t size)
6398 {
6399 int end = (start + size > 256) ? 256 : start + size, i;
6400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6401
6402 for (i = start; i < end; i++) {
6403 intel_crtc->lut_r[i] = red[i] >> 8;
6404 intel_crtc->lut_g[i] = green[i] >> 8;
6405 intel_crtc->lut_b[i] = blue[i] >> 8;
6406 }
6407
6408 intel_crtc_load_lut(crtc);
6409 }
6410
6411 /* VESA 640x480x72Hz mode to set on the pipe */
6412 static struct drm_display_mode load_detect_mode = {
6413 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6414 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6415 };
6416
6417 static struct drm_framebuffer *
6418 intel_framebuffer_create(struct drm_device *dev,
6419 struct drm_mode_fb_cmd2 *mode_cmd,
6420 struct drm_i915_gem_object *obj)
6421 {
6422 struct intel_framebuffer *intel_fb;
6423 int ret;
6424
6425 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6426 if (!intel_fb) {
6427 drm_gem_object_unreference_unlocked(&obj->base);
6428 return ERR_PTR(-ENOMEM);
6429 }
6430
6431 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6432 if (ret) {
6433 drm_gem_object_unreference_unlocked(&obj->base);
6434 kfree(intel_fb);
6435 return ERR_PTR(ret);
6436 }
6437
6438 return &intel_fb->base;
6439 }
6440
6441 static u32
6442 intel_framebuffer_pitch_for_width(int width, int bpp)
6443 {
6444 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6445 return ALIGN(pitch, 64);
6446 }
6447
6448 static u32
6449 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6450 {
6451 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6452 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6453 }
6454
6455 static struct drm_framebuffer *
6456 intel_framebuffer_create_for_mode(struct drm_device *dev,
6457 struct drm_display_mode *mode,
6458 int depth, int bpp)
6459 {
6460 struct drm_i915_gem_object *obj;
6461 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6462
6463 obj = i915_gem_alloc_object(dev,
6464 intel_framebuffer_size_for_mode(mode, bpp));
6465 if (obj == NULL)
6466 return ERR_PTR(-ENOMEM);
6467
6468 mode_cmd.width = mode->hdisplay;
6469 mode_cmd.height = mode->vdisplay;
6470 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6471 bpp);
6472 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6473
6474 return intel_framebuffer_create(dev, &mode_cmd, obj);
6475 }
6476
6477 static struct drm_framebuffer *
6478 mode_fits_in_fbdev(struct drm_device *dev,
6479 struct drm_display_mode *mode)
6480 {
6481 struct drm_i915_private *dev_priv = dev->dev_private;
6482 struct drm_i915_gem_object *obj;
6483 struct drm_framebuffer *fb;
6484
6485 if (dev_priv->fbdev == NULL)
6486 return NULL;
6487
6488 obj = dev_priv->fbdev->ifb.obj;
6489 if (obj == NULL)
6490 return NULL;
6491
6492 fb = &dev_priv->fbdev->ifb.base;
6493 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6494 fb->bits_per_pixel))
6495 return NULL;
6496
6497 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6498 return NULL;
6499
6500 return fb;
6501 }
6502
6503 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6504 struct drm_display_mode *mode,
6505 struct intel_load_detect_pipe *old)
6506 {
6507 struct intel_crtc *intel_crtc;
6508 struct intel_encoder *intel_encoder =
6509 intel_attached_encoder(connector);
6510 struct drm_crtc *possible_crtc;
6511 struct drm_encoder *encoder = &intel_encoder->base;
6512 struct drm_crtc *crtc = NULL;
6513 struct drm_device *dev = encoder->dev;
6514 struct drm_framebuffer *fb;
6515 int i = -1;
6516
6517 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6518 connector->base.id, drm_get_connector_name(connector),
6519 encoder->base.id, drm_get_encoder_name(encoder));
6520
6521 /*
6522 * Algorithm gets a little messy:
6523 *
6524 * - if the connector already has an assigned crtc, use it (but make
6525 * sure it's on first)
6526 *
6527 * - try to find the first unused crtc that can drive this connector,
6528 * and use that if we find one
6529 */
6530
6531 /* See if we already have a CRTC for this connector */
6532 if (encoder->crtc) {
6533 crtc = encoder->crtc;
6534
6535 mutex_lock(&crtc->mutex);
6536
6537 old->dpms_mode = connector->dpms;
6538 old->load_detect_temp = false;
6539
6540 /* Make sure the crtc and connector are running */
6541 if (connector->dpms != DRM_MODE_DPMS_ON)
6542 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6543
6544 return true;
6545 }
6546
6547 /* Find an unused one (if possible) */
6548 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6549 i++;
6550 if (!(encoder->possible_crtcs & (1 << i)))
6551 continue;
6552 if (!possible_crtc->enabled) {
6553 crtc = possible_crtc;
6554 break;
6555 }
6556 }
6557
6558 /*
6559 * If we didn't find an unused CRTC, don't use any.
6560 */
6561 if (!crtc) {
6562 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6563 return false;
6564 }
6565
6566 mutex_lock(&crtc->mutex);
6567 intel_encoder->new_crtc = to_intel_crtc(crtc);
6568 to_intel_connector(connector)->new_encoder = intel_encoder;
6569
6570 intel_crtc = to_intel_crtc(crtc);
6571 old->dpms_mode = connector->dpms;
6572 old->load_detect_temp = true;
6573 old->release_fb = NULL;
6574
6575 if (!mode)
6576 mode = &load_detect_mode;
6577
6578 /* We need a framebuffer large enough to accommodate all accesses
6579 * that the plane may generate whilst we perform load detection.
6580 * We can not rely on the fbcon either being present (we get called
6581 * during its initialisation to detect all boot displays, or it may
6582 * not even exist) or that it is large enough to satisfy the
6583 * requested mode.
6584 */
6585 fb = mode_fits_in_fbdev(dev, mode);
6586 if (fb == NULL) {
6587 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6588 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6589 old->release_fb = fb;
6590 } else
6591 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6592 if (IS_ERR(fb)) {
6593 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6594 mutex_unlock(&crtc->mutex);
6595 return false;
6596 }
6597
6598 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6599 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6600 if (old->release_fb)
6601 old->release_fb->funcs->destroy(old->release_fb);
6602 mutex_unlock(&crtc->mutex);
6603 return false;
6604 }
6605
6606 /* let the connector get through one full cycle before testing */
6607 intel_wait_for_vblank(dev, intel_crtc->pipe);
6608 return true;
6609 }
6610
6611 void intel_release_load_detect_pipe(struct drm_connector *connector,
6612 struct intel_load_detect_pipe *old)
6613 {
6614 struct intel_encoder *intel_encoder =
6615 intel_attached_encoder(connector);
6616 struct drm_encoder *encoder = &intel_encoder->base;
6617 struct drm_crtc *crtc = encoder->crtc;
6618
6619 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6620 connector->base.id, drm_get_connector_name(connector),
6621 encoder->base.id, drm_get_encoder_name(encoder));
6622
6623 if (old->load_detect_temp) {
6624 to_intel_connector(connector)->new_encoder = NULL;
6625 intel_encoder->new_crtc = NULL;
6626 intel_set_mode(crtc, NULL, 0, 0, NULL);
6627
6628 if (old->release_fb) {
6629 drm_framebuffer_unregister_private(old->release_fb);
6630 drm_framebuffer_unreference(old->release_fb);
6631 }
6632
6633 mutex_unlock(&crtc->mutex);
6634 return;
6635 }
6636
6637 /* Switch crtc and encoder back off if necessary */
6638 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6639 connector->funcs->dpms(connector, old->dpms_mode);
6640
6641 mutex_unlock(&crtc->mutex);
6642 }
6643
6644 /* Returns the clock of the currently programmed mode of the given pipe. */
6645 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6646 {
6647 struct drm_i915_private *dev_priv = dev->dev_private;
6648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6649 int pipe = intel_crtc->pipe;
6650 u32 dpll = I915_READ(DPLL(pipe));
6651 u32 fp;
6652 intel_clock_t clock;
6653
6654 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6655 fp = I915_READ(FP0(pipe));
6656 else
6657 fp = I915_READ(FP1(pipe));
6658
6659 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6660 if (IS_PINEVIEW(dev)) {
6661 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6662 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6663 } else {
6664 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6665 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6666 }
6667
6668 if (!IS_GEN2(dev)) {
6669 if (IS_PINEVIEW(dev))
6670 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6671 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6672 else
6673 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6674 DPLL_FPA01_P1_POST_DIV_SHIFT);
6675
6676 switch (dpll & DPLL_MODE_MASK) {
6677 case DPLLB_MODE_DAC_SERIAL:
6678 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6679 5 : 10;
6680 break;
6681 case DPLLB_MODE_LVDS:
6682 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6683 7 : 14;
6684 break;
6685 default:
6686 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6687 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6688 return 0;
6689 }
6690
6691 /* XXX: Handle the 100Mhz refclk */
6692 intel_clock(dev, 96000, &clock);
6693 } else {
6694 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6695
6696 if (is_lvds) {
6697 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6698 DPLL_FPA01_P1_POST_DIV_SHIFT);
6699 clock.p2 = 14;
6700
6701 if ((dpll & PLL_REF_INPUT_MASK) ==
6702 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6703 /* XXX: might not be 66MHz */
6704 intel_clock(dev, 66000, &clock);
6705 } else
6706 intel_clock(dev, 48000, &clock);
6707 } else {
6708 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6709 clock.p1 = 2;
6710 else {
6711 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6712 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6713 }
6714 if (dpll & PLL_P2_DIVIDE_BY_4)
6715 clock.p2 = 4;
6716 else
6717 clock.p2 = 2;
6718
6719 intel_clock(dev, 48000, &clock);
6720 }
6721 }
6722
6723 /* XXX: It would be nice to validate the clocks, but we can't reuse
6724 * i830PllIsValid() because it relies on the xf86_config connector
6725 * configuration being accurate, which it isn't necessarily.
6726 */
6727
6728 return clock.dot;
6729 }
6730
6731 /** Returns the currently programmed mode of the given pipe. */
6732 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6733 struct drm_crtc *crtc)
6734 {
6735 struct drm_i915_private *dev_priv = dev->dev_private;
6736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6737 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6738 struct drm_display_mode *mode;
6739 int htot = I915_READ(HTOTAL(cpu_transcoder));
6740 int hsync = I915_READ(HSYNC(cpu_transcoder));
6741 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6742 int vsync = I915_READ(VSYNC(cpu_transcoder));
6743
6744 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6745 if (!mode)
6746 return NULL;
6747
6748 mode->clock = intel_crtc_clock_get(dev, crtc);
6749 mode->hdisplay = (htot & 0xffff) + 1;
6750 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6751 mode->hsync_start = (hsync & 0xffff) + 1;
6752 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6753 mode->vdisplay = (vtot & 0xffff) + 1;
6754 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6755 mode->vsync_start = (vsync & 0xffff) + 1;
6756 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6757
6758 drm_mode_set_name(mode);
6759
6760 return mode;
6761 }
6762
6763 static void intel_increase_pllclock(struct drm_crtc *crtc)
6764 {
6765 struct drm_device *dev = crtc->dev;
6766 drm_i915_private_t *dev_priv = dev->dev_private;
6767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6768 int pipe = intel_crtc->pipe;
6769 int dpll_reg = DPLL(pipe);
6770 int dpll;
6771
6772 if (HAS_PCH_SPLIT(dev))
6773 return;
6774
6775 if (!dev_priv->lvds_downclock_avail)
6776 return;
6777
6778 dpll = I915_READ(dpll_reg);
6779 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6780 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6781
6782 assert_panel_unlocked(dev_priv, pipe);
6783
6784 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6785 I915_WRITE(dpll_reg, dpll);
6786 intel_wait_for_vblank(dev, pipe);
6787
6788 dpll = I915_READ(dpll_reg);
6789 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6790 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6791 }
6792 }
6793
6794 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6795 {
6796 struct drm_device *dev = crtc->dev;
6797 drm_i915_private_t *dev_priv = dev->dev_private;
6798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6799
6800 if (HAS_PCH_SPLIT(dev))
6801 return;
6802
6803 if (!dev_priv->lvds_downclock_avail)
6804 return;
6805
6806 /*
6807 * Since this is called by a timer, we should never get here in
6808 * the manual case.
6809 */
6810 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6811 int pipe = intel_crtc->pipe;
6812 int dpll_reg = DPLL(pipe);
6813 int dpll;
6814
6815 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6816
6817 assert_panel_unlocked(dev_priv, pipe);
6818
6819 dpll = I915_READ(dpll_reg);
6820 dpll |= DISPLAY_RATE_SELECT_FPA1;
6821 I915_WRITE(dpll_reg, dpll);
6822 intel_wait_for_vblank(dev, pipe);
6823 dpll = I915_READ(dpll_reg);
6824 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6825 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6826 }
6827
6828 }
6829
6830 void intel_mark_busy(struct drm_device *dev)
6831 {
6832 i915_update_gfx_val(dev->dev_private);
6833 }
6834
6835 void intel_mark_idle(struct drm_device *dev)
6836 {
6837 struct drm_crtc *crtc;
6838
6839 if (!i915_powersave)
6840 return;
6841
6842 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6843 if (!crtc->fb)
6844 continue;
6845
6846 intel_decrease_pllclock(crtc);
6847 }
6848 }
6849
6850 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6851 {
6852 struct drm_device *dev = obj->base.dev;
6853 struct drm_crtc *crtc;
6854
6855 if (!i915_powersave)
6856 return;
6857
6858 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6859 if (!crtc->fb)
6860 continue;
6861
6862 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6863 intel_increase_pllclock(crtc);
6864 }
6865 }
6866
6867 static void intel_crtc_destroy(struct drm_crtc *crtc)
6868 {
6869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6870 struct drm_device *dev = crtc->dev;
6871 struct intel_unpin_work *work;
6872 unsigned long flags;
6873
6874 spin_lock_irqsave(&dev->event_lock, flags);
6875 work = intel_crtc->unpin_work;
6876 intel_crtc->unpin_work = NULL;
6877 spin_unlock_irqrestore(&dev->event_lock, flags);
6878
6879 if (work) {
6880 cancel_work_sync(&work->work);
6881 kfree(work);
6882 }
6883
6884 drm_crtc_cleanup(crtc);
6885
6886 kfree(intel_crtc);
6887 }
6888
6889 static void intel_unpin_work_fn(struct work_struct *__work)
6890 {
6891 struct intel_unpin_work *work =
6892 container_of(__work, struct intel_unpin_work, work);
6893 struct drm_device *dev = work->crtc->dev;
6894
6895 mutex_lock(&dev->struct_mutex);
6896 intel_unpin_fb_obj(work->old_fb_obj);
6897 drm_gem_object_unreference(&work->pending_flip_obj->base);
6898 drm_gem_object_unreference(&work->old_fb_obj->base);
6899
6900 intel_update_fbc(dev);
6901 mutex_unlock(&dev->struct_mutex);
6902
6903 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6904 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6905
6906 kfree(work);
6907 }
6908
6909 static void do_intel_finish_page_flip(struct drm_device *dev,
6910 struct drm_crtc *crtc)
6911 {
6912 drm_i915_private_t *dev_priv = dev->dev_private;
6913 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6914 struct intel_unpin_work *work;
6915 unsigned long flags;
6916
6917 /* Ignore early vblank irqs */
6918 if (intel_crtc == NULL)
6919 return;
6920
6921 spin_lock_irqsave(&dev->event_lock, flags);
6922 work = intel_crtc->unpin_work;
6923
6924 /* Ensure we don't miss a work->pending update ... */
6925 smp_rmb();
6926
6927 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6928 spin_unlock_irqrestore(&dev->event_lock, flags);
6929 return;
6930 }
6931
6932 /* and that the unpin work is consistent wrt ->pending. */
6933 smp_rmb();
6934
6935 intel_crtc->unpin_work = NULL;
6936
6937 if (work->event)
6938 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6939
6940 drm_vblank_put(dev, intel_crtc->pipe);
6941
6942 spin_unlock_irqrestore(&dev->event_lock, flags);
6943
6944 wake_up_all(&dev_priv->pending_flip_queue);
6945
6946 queue_work(dev_priv->wq, &work->work);
6947
6948 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6949 }
6950
6951 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6952 {
6953 drm_i915_private_t *dev_priv = dev->dev_private;
6954 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6955
6956 do_intel_finish_page_flip(dev, crtc);
6957 }
6958
6959 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6960 {
6961 drm_i915_private_t *dev_priv = dev->dev_private;
6962 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6963
6964 do_intel_finish_page_flip(dev, crtc);
6965 }
6966
6967 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6968 {
6969 drm_i915_private_t *dev_priv = dev->dev_private;
6970 struct intel_crtc *intel_crtc =
6971 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6972 unsigned long flags;
6973
6974 /* NB: An MMIO update of the plane base pointer will also
6975 * generate a page-flip completion irq, i.e. every modeset
6976 * is also accompanied by a spurious intel_prepare_page_flip().
6977 */
6978 spin_lock_irqsave(&dev->event_lock, flags);
6979 if (intel_crtc->unpin_work)
6980 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6981 spin_unlock_irqrestore(&dev->event_lock, flags);
6982 }
6983
6984 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
6985 {
6986 /* Ensure that the work item is consistent when activating it ... */
6987 smp_wmb();
6988 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
6989 /* and that it is marked active as soon as the irq could fire. */
6990 smp_wmb();
6991 }
6992
6993 static int intel_gen2_queue_flip(struct drm_device *dev,
6994 struct drm_crtc *crtc,
6995 struct drm_framebuffer *fb,
6996 struct drm_i915_gem_object *obj)
6997 {
6998 struct drm_i915_private *dev_priv = dev->dev_private;
6999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7000 u32 flip_mask;
7001 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7002 int ret;
7003
7004 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7005 if (ret)
7006 goto err;
7007
7008 ret = intel_ring_begin(ring, 6);
7009 if (ret)
7010 goto err_unpin;
7011
7012 /* Can't queue multiple flips, so wait for the previous
7013 * one to finish before executing the next.
7014 */
7015 if (intel_crtc->plane)
7016 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7017 else
7018 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7019 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7020 intel_ring_emit(ring, MI_NOOP);
7021 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7022 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7023 intel_ring_emit(ring, fb->pitches[0]);
7024 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7025 intel_ring_emit(ring, 0); /* aux display base address, unused */
7026
7027 intel_mark_page_flip_active(intel_crtc);
7028 intel_ring_advance(ring);
7029 return 0;
7030
7031 err_unpin:
7032 intel_unpin_fb_obj(obj);
7033 err:
7034 return ret;
7035 }
7036
7037 static int intel_gen3_queue_flip(struct drm_device *dev,
7038 struct drm_crtc *crtc,
7039 struct drm_framebuffer *fb,
7040 struct drm_i915_gem_object *obj)
7041 {
7042 struct drm_i915_private *dev_priv = dev->dev_private;
7043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7044 u32 flip_mask;
7045 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7046 int ret;
7047
7048 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7049 if (ret)
7050 goto err;
7051
7052 ret = intel_ring_begin(ring, 6);
7053 if (ret)
7054 goto err_unpin;
7055
7056 if (intel_crtc->plane)
7057 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7058 else
7059 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7060 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7061 intel_ring_emit(ring, MI_NOOP);
7062 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7063 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7064 intel_ring_emit(ring, fb->pitches[0]);
7065 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7066 intel_ring_emit(ring, MI_NOOP);
7067
7068 intel_mark_page_flip_active(intel_crtc);
7069 intel_ring_advance(ring);
7070 return 0;
7071
7072 err_unpin:
7073 intel_unpin_fb_obj(obj);
7074 err:
7075 return ret;
7076 }
7077
7078 static int intel_gen4_queue_flip(struct drm_device *dev,
7079 struct drm_crtc *crtc,
7080 struct drm_framebuffer *fb,
7081 struct drm_i915_gem_object *obj)
7082 {
7083 struct drm_i915_private *dev_priv = dev->dev_private;
7084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7085 uint32_t pf, pipesrc;
7086 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7087 int ret;
7088
7089 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7090 if (ret)
7091 goto err;
7092
7093 ret = intel_ring_begin(ring, 4);
7094 if (ret)
7095 goto err_unpin;
7096
7097 /* i965+ uses the linear or tiled offsets from the
7098 * Display Registers (which do not change across a page-flip)
7099 * so we need only reprogram the base address.
7100 */
7101 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7102 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7103 intel_ring_emit(ring, fb->pitches[0]);
7104 intel_ring_emit(ring,
7105 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7106 obj->tiling_mode);
7107
7108 /* XXX Enabling the panel-fitter across page-flip is so far
7109 * untested on non-native modes, so ignore it for now.
7110 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7111 */
7112 pf = 0;
7113 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7114 intel_ring_emit(ring, pf | pipesrc);
7115
7116 intel_mark_page_flip_active(intel_crtc);
7117 intel_ring_advance(ring);
7118 return 0;
7119
7120 err_unpin:
7121 intel_unpin_fb_obj(obj);
7122 err:
7123 return ret;
7124 }
7125
7126 static int intel_gen6_queue_flip(struct drm_device *dev,
7127 struct drm_crtc *crtc,
7128 struct drm_framebuffer *fb,
7129 struct drm_i915_gem_object *obj)
7130 {
7131 struct drm_i915_private *dev_priv = dev->dev_private;
7132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7133 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7134 uint32_t pf, pipesrc;
7135 int ret;
7136
7137 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7138 if (ret)
7139 goto err;
7140
7141 ret = intel_ring_begin(ring, 4);
7142 if (ret)
7143 goto err_unpin;
7144
7145 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7146 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7147 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7148 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7149
7150 /* Contrary to the suggestions in the documentation,
7151 * "Enable Panel Fitter" does not seem to be required when page
7152 * flipping with a non-native mode, and worse causes a normal
7153 * modeset to fail.
7154 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7155 */
7156 pf = 0;
7157 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7158 intel_ring_emit(ring, pf | pipesrc);
7159
7160 intel_mark_page_flip_active(intel_crtc);
7161 intel_ring_advance(ring);
7162 return 0;
7163
7164 err_unpin:
7165 intel_unpin_fb_obj(obj);
7166 err:
7167 return ret;
7168 }
7169
7170 /*
7171 * On gen7 we currently use the blit ring because (in early silicon at least)
7172 * the render ring doesn't give us interrpts for page flip completion, which
7173 * means clients will hang after the first flip is queued. Fortunately the
7174 * blit ring generates interrupts properly, so use it instead.
7175 */
7176 static int intel_gen7_queue_flip(struct drm_device *dev,
7177 struct drm_crtc *crtc,
7178 struct drm_framebuffer *fb,
7179 struct drm_i915_gem_object *obj)
7180 {
7181 struct drm_i915_private *dev_priv = dev->dev_private;
7182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7183 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7184 uint32_t plane_bit = 0;
7185 int ret;
7186
7187 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7188 if (ret)
7189 goto err;
7190
7191 switch(intel_crtc->plane) {
7192 case PLANE_A:
7193 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7194 break;
7195 case PLANE_B:
7196 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7197 break;
7198 case PLANE_C:
7199 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7200 break;
7201 default:
7202 WARN_ONCE(1, "unknown plane in flip command\n");
7203 ret = -ENODEV;
7204 goto err_unpin;
7205 }
7206
7207 ret = intel_ring_begin(ring, 4);
7208 if (ret)
7209 goto err_unpin;
7210
7211 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7212 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7213 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7214 intel_ring_emit(ring, (MI_NOOP));
7215
7216 intel_mark_page_flip_active(intel_crtc);
7217 intel_ring_advance(ring);
7218 return 0;
7219
7220 err_unpin:
7221 intel_unpin_fb_obj(obj);
7222 err:
7223 return ret;
7224 }
7225
7226 static int intel_default_queue_flip(struct drm_device *dev,
7227 struct drm_crtc *crtc,
7228 struct drm_framebuffer *fb,
7229 struct drm_i915_gem_object *obj)
7230 {
7231 return -ENODEV;
7232 }
7233
7234 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7235 struct drm_framebuffer *fb,
7236 struct drm_pending_vblank_event *event)
7237 {
7238 struct drm_device *dev = crtc->dev;
7239 struct drm_i915_private *dev_priv = dev->dev_private;
7240 struct drm_framebuffer *old_fb = crtc->fb;
7241 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7243 struct intel_unpin_work *work;
7244 unsigned long flags;
7245 int ret;
7246
7247 /* Can't change pixel format via MI display flips. */
7248 if (fb->pixel_format != crtc->fb->pixel_format)
7249 return -EINVAL;
7250
7251 /*
7252 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7253 * Note that pitch changes could also affect these register.
7254 */
7255 if (INTEL_INFO(dev)->gen > 3 &&
7256 (fb->offsets[0] != crtc->fb->offsets[0] ||
7257 fb->pitches[0] != crtc->fb->pitches[0]))
7258 return -EINVAL;
7259
7260 work = kzalloc(sizeof *work, GFP_KERNEL);
7261 if (work == NULL)
7262 return -ENOMEM;
7263
7264 work->event = event;
7265 work->crtc = crtc;
7266 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7267 INIT_WORK(&work->work, intel_unpin_work_fn);
7268
7269 ret = drm_vblank_get(dev, intel_crtc->pipe);
7270 if (ret)
7271 goto free_work;
7272
7273 /* We borrow the event spin lock for protecting unpin_work */
7274 spin_lock_irqsave(&dev->event_lock, flags);
7275 if (intel_crtc->unpin_work) {
7276 spin_unlock_irqrestore(&dev->event_lock, flags);
7277 kfree(work);
7278 drm_vblank_put(dev, intel_crtc->pipe);
7279
7280 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7281 return -EBUSY;
7282 }
7283 intel_crtc->unpin_work = work;
7284 spin_unlock_irqrestore(&dev->event_lock, flags);
7285
7286 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7287 flush_workqueue(dev_priv->wq);
7288
7289 ret = i915_mutex_lock_interruptible(dev);
7290 if (ret)
7291 goto cleanup;
7292
7293 /* Reference the objects for the scheduled work. */
7294 drm_gem_object_reference(&work->old_fb_obj->base);
7295 drm_gem_object_reference(&obj->base);
7296
7297 crtc->fb = fb;
7298
7299 work->pending_flip_obj = obj;
7300
7301 work->enable_stall_check = true;
7302
7303 atomic_inc(&intel_crtc->unpin_work_count);
7304 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7305
7306 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7307 if (ret)
7308 goto cleanup_pending;
7309
7310 intel_disable_fbc(dev);
7311 intel_mark_fb_busy(obj);
7312 mutex_unlock(&dev->struct_mutex);
7313
7314 trace_i915_flip_request(intel_crtc->plane, obj);
7315
7316 return 0;
7317
7318 cleanup_pending:
7319 atomic_dec(&intel_crtc->unpin_work_count);
7320 crtc->fb = old_fb;
7321 drm_gem_object_unreference(&work->old_fb_obj->base);
7322 drm_gem_object_unreference(&obj->base);
7323 mutex_unlock(&dev->struct_mutex);
7324
7325 cleanup:
7326 spin_lock_irqsave(&dev->event_lock, flags);
7327 intel_crtc->unpin_work = NULL;
7328 spin_unlock_irqrestore(&dev->event_lock, flags);
7329
7330 drm_vblank_put(dev, intel_crtc->pipe);
7331 free_work:
7332 kfree(work);
7333
7334 return ret;
7335 }
7336
7337 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7338 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7339 .load_lut = intel_crtc_load_lut,
7340 };
7341
7342 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7343 {
7344 struct intel_encoder *other_encoder;
7345 struct drm_crtc *crtc = &encoder->new_crtc->base;
7346
7347 if (WARN_ON(!crtc))
7348 return false;
7349
7350 list_for_each_entry(other_encoder,
7351 &crtc->dev->mode_config.encoder_list,
7352 base.head) {
7353
7354 if (&other_encoder->new_crtc->base != crtc ||
7355 encoder == other_encoder)
7356 continue;
7357 else
7358 return true;
7359 }
7360
7361 return false;
7362 }
7363
7364 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7365 struct drm_crtc *crtc)
7366 {
7367 struct drm_device *dev;
7368 struct drm_crtc *tmp;
7369 int crtc_mask = 1;
7370
7371 WARN(!crtc, "checking null crtc?\n");
7372
7373 dev = crtc->dev;
7374
7375 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7376 if (tmp == crtc)
7377 break;
7378 crtc_mask <<= 1;
7379 }
7380
7381 if (encoder->possible_crtcs & crtc_mask)
7382 return true;
7383 return false;
7384 }
7385
7386 /**
7387 * intel_modeset_update_staged_output_state
7388 *
7389 * Updates the staged output configuration state, e.g. after we've read out the
7390 * current hw state.
7391 */
7392 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7393 {
7394 struct intel_encoder *encoder;
7395 struct intel_connector *connector;
7396
7397 list_for_each_entry(connector, &dev->mode_config.connector_list,
7398 base.head) {
7399 connector->new_encoder =
7400 to_intel_encoder(connector->base.encoder);
7401 }
7402
7403 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7404 base.head) {
7405 encoder->new_crtc =
7406 to_intel_crtc(encoder->base.crtc);
7407 }
7408 }
7409
7410 /**
7411 * intel_modeset_commit_output_state
7412 *
7413 * This function copies the stage display pipe configuration to the real one.
7414 */
7415 static void intel_modeset_commit_output_state(struct drm_device *dev)
7416 {
7417 struct intel_encoder *encoder;
7418 struct intel_connector *connector;
7419
7420 list_for_each_entry(connector, &dev->mode_config.connector_list,
7421 base.head) {
7422 connector->base.encoder = &connector->new_encoder->base;
7423 }
7424
7425 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7426 base.head) {
7427 encoder->base.crtc = &encoder->new_crtc->base;
7428 }
7429 }
7430
7431 static int
7432 pipe_config_set_bpp(struct drm_crtc *crtc,
7433 struct drm_framebuffer *fb,
7434 struct intel_crtc_config *pipe_config)
7435 {
7436 struct drm_device *dev = crtc->dev;
7437 struct drm_connector *connector;
7438 int bpp;
7439
7440 switch (fb->pixel_format) {
7441 case DRM_FORMAT_C8:
7442 bpp = 8*3; /* since we go through a colormap */
7443 break;
7444 case DRM_FORMAT_XRGB1555:
7445 case DRM_FORMAT_ARGB1555:
7446 /* checked in intel_framebuffer_init already */
7447 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7448 return -EINVAL;
7449 case DRM_FORMAT_RGB565:
7450 bpp = 6*3; /* min is 18bpp */
7451 break;
7452 case DRM_FORMAT_XBGR8888:
7453 case DRM_FORMAT_ABGR8888:
7454 /* checked in intel_framebuffer_init already */
7455 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7456 return -EINVAL;
7457 case DRM_FORMAT_XRGB8888:
7458 case DRM_FORMAT_ARGB8888:
7459 bpp = 8*3;
7460 break;
7461 case DRM_FORMAT_XRGB2101010:
7462 case DRM_FORMAT_ARGB2101010:
7463 case DRM_FORMAT_XBGR2101010:
7464 case DRM_FORMAT_ABGR2101010:
7465 /* checked in intel_framebuffer_init already */
7466 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7467 return -EINVAL;
7468 bpp = 10*3;
7469 break;
7470 /* TODO: gen4+ supports 16 bpc floating point, too. */
7471 default:
7472 DRM_DEBUG_KMS("unsupported depth\n");
7473 return -EINVAL;
7474 }
7475
7476 pipe_config->pipe_bpp = bpp;
7477
7478 /* Clamp display bpp to EDID value */
7479 list_for_each_entry(connector, &dev->mode_config.connector_list,
7480 head) {
7481 if (connector->encoder && connector->encoder->crtc != crtc)
7482 continue;
7483
7484 /* Don't use an invalid EDID bpc value */
7485 if (connector->display_info.bpc &&
7486 connector->display_info.bpc * 3 < bpp) {
7487 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7488 bpp, connector->display_info.bpc*3);
7489 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7490 }
7491 }
7492
7493 return bpp;
7494 }
7495
7496 static struct intel_crtc_config *
7497 intel_modeset_pipe_config(struct drm_crtc *crtc,
7498 struct drm_framebuffer *fb,
7499 struct drm_display_mode *mode)
7500 {
7501 struct drm_device *dev = crtc->dev;
7502 struct drm_encoder_helper_funcs *encoder_funcs;
7503 struct intel_encoder *encoder;
7504 struct intel_crtc_config *pipe_config;
7505 int plane_bpp;
7506
7507 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7508 if (!pipe_config)
7509 return ERR_PTR(-ENOMEM);
7510
7511 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7512 drm_mode_copy(&pipe_config->requested_mode, mode);
7513
7514 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7515 if (plane_bpp < 0)
7516 goto fail;
7517
7518 /* Pass our mode to the connectors and the CRTC to give them a chance to
7519 * adjust it according to limitations or connector properties, and also
7520 * a chance to reject the mode entirely.
7521 */
7522 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7523 base.head) {
7524
7525 if (&encoder->new_crtc->base != crtc)
7526 continue;
7527
7528 if (encoder->compute_config) {
7529 if (!(encoder->compute_config(encoder, pipe_config))) {
7530 DRM_DEBUG_KMS("Encoder config failure\n");
7531 goto fail;
7532 }
7533
7534 continue;
7535 }
7536
7537 encoder_funcs = encoder->base.helper_private;
7538 if (!(encoder_funcs->mode_fixup(&encoder->base,
7539 &pipe_config->requested_mode,
7540 &pipe_config->adjusted_mode))) {
7541 DRM_DEBUG_KMS("Encoder fixup failed\n");
7542 goto fail;
7543 }
7544 }
7545
7546 if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7547 DRM_DEBUG_KMS("CRTC fixup failed\n");
7548 goto fail;
7549 }
7550 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7551
7552 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7553 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7554 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7555
7556 return pipe_config;
7557 fail:
7558 kfree(pipe_config);
7559 return ERR_PTR(-EINVAL);
7560 }
7561
7562 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7563 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7564 static void
7565 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7566 unsigned *prepare_pipes, unsigned *disable_pipes)
7567 {
7568 struct intel_crtc *intel_crtc;
7569 struct drm_device *dev = crtc->dev;
7570 struct intel_encoder *encoder;
7571 struct intel_connector *connector;
7572 struct drm_crtc *tmp_crtc;
7573
7574 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7575
7576 /* Check which crtcs have changed outputs connected to them, these need
7577 * to be part of the prepare_pipes mask. We don't (yet) support global
7578 * modeset across multiple crtcs, so modeset_pipes will only have one
7579 * bit set at most. */
7580 list_for_each_entry(connector, &dev->mode_config.connector_list,
7581 base.head) {
7582 if (connector->base.encoder == &connector->new_encoder->base)
7583 continue;
7584
7585 if (connector->base.encoder) {
7586 tmp_crtc = connector->base.encoder->crtc;
7587
7588 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7589 }
7590
7591 if (connector->new_encoder)
7592 *prepare_pipes |=
7593 1 << connector->new_encoder->new_crtc->pipe;
7594 }
7595
7596 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7597 base.head) {
7598 if (encoder->base.crtc == &encoder->new_crtc->base)
7599 continue;
7600
7601 if (encoder->base.crtc) {
7602 tmp_crtc = encoder->base.crtc;
7603
7604 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7605 }
7606
7607 if (encoder->new_crtc)
7608 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7609 }
7610
7611 /* Check for any pipes that will be fully disabled ... */
7612 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7613 base.head) {
7614 bool used = false;
7615
7616 /* Don't try to disable disabled crtcs. */
7617 if (!intel_crtc->base.enabled)
7618 continue;
7619
7620 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7621 base.head) {
7622 if (encoder->new_crtc == intel_crtc)
7623 used = true;
7624 }
7625
7626 if (!used)
7627 *disable_pipes |= 1 << intel_crtc->pipe;
7628 }
7629
7630
7631 /* set_mode is also used to update properties on life display pipes. */
7632 intel_crtc = to_intel_crtc(crtc);
7633 if (crtc->enabled)
7634 *prepare_pipes |= 1 << intel_crtc->pipe;
7635
7636 /* We only support modeset on one single crtc, hence we need to do that
7637 * only for the passed in crtc iff we change anything else than just
7638 * disable crtcs.
7639 *
7640 * This is actually not true, to be fully compatible with the old crtc
7641 * helper we automatically disable _any_ output (i.e. doesn't need to be
7642 * connected to the crtc we're modesetting on) if it's disconnected.
7643 * Which is a rather nutty api (since changed the output configuration
7644 * without userspace's explicit request can lead to confusion), but
7645 * alas. Hence we currently need to modeset on all pipes we prepare. */
7646 if (*prepare_pipes)
7647 *modeset_pipes = *prepare_pipes;
7648
7649 /* ... and mask these out. */
7650 *modeset_pipes &= ~(*disable_pipes);
7651 *prepare_pipes &= ~(*disable_pipes);
7652 }
7653
7654 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7655 {
7656 struct drm_encoder *encoder;
7657 struct drm_device *dev = crtc->dev;
7658
7659 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7660 if (encoder->crtc == crtc)
7661 return true;
7662
7663 return false;
7664 }
7665
7666 static void
7667 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7668 {
7669 struct intel_encoder *intel_encoder;
7670 struct intel_crtc *intel_crtc;
7671 struct drm_connector *connector;
7672
7673 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7674 base.head) {
7675 if (!intel_encoder->base.crtc)
7676 continue;
7677
7678 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7679
7680 if (prepare_pipes & (1 << intel_crtc->pipe))
7681 intel_encoder->connectors_active = false;
7682 }
7683
7684 intel_modeset_commit_output_state(dev);
7685
7686 /* Update computed state. */
7687 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7688 base.head) {
7689 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7690 }
7691
7692 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7693 if (!connector->encoder || !connector->encoder->crtc)
7694 continue;
7695
7696 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7697
7698 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7699 struct drm_property *dpms_property =
7700 dev->mode_config.dpms_property;
7701
7702 connector->dpms = DRM_MODE_DPMS_ON;
7703 drm_object_property_set_value(&connector->base,
7704 dpms_property,
7705 DRM_MODE_DPMS_ON);
7706
7707 intel_encoder = to_intel_encoder(connector->encoder);
7708 intel_encoder->connectors_active = true;
7709 }
7710 }
7711
7712 }
7713
7714 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7715 list_for_each_entry((intel_crtc), \
7716 &(dev)->mode_config.crtc_list, \
7717 base.head) \
7718 if (mask & (1 <<(intel_crtc)->pipe)) \
7719
7720 void
7721 intel_modeset_check_state(struct drm_device *dev)
7722 {
7723 struct intel_crtc *crtc;
7724 struct intel_encoder *encoder;
7725 struct intel_connector *connector;
7726
7727 list_for_each_entry(connector, &dev->mode_config.connector_list,
7728 base.head) {
7729 /* This also checks the encoder/connector hw state with the
7730 * ->get_hw_state callbacks. */
7731 intel_connector_check_state(connector);
7732
7733 WARN(&connector->new_encoder->base != connector->base.encoder,
7734 "connector's staged encoder doesn't match current encoder\n");
7735 }
7736
7737 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7738 base.head) {
7739 bool enabled = false;
7740 bool active = false;
7741 enum pipe pipe, tracked_pipe;
7742
7743 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7744 encoder->base.base.id,
7745 drm_get_encoder_name(&encoder->base));
7746
7747 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7748 "encoder's stage crtc doesn't match current crtc\n");
7749 WARN(encoder->connectors_active && !encoder->base.crtc,
7750 "encoder's active_connectors set, but no crtc\n");
7751
7752 list_for_each_entry(connector, &dev->mode_config.connector_list,
7753 base.head) {
7754 if (connector->base.encoder != &encoder->base)
7755 continue;
7756 enabled = true;
7757 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7758 active = true;
7759 }
7760 WARN(!!encoder->base.crtc != enabled,
7761 "encoder's enabled state mismatch "
7762 "(expected %i, found %i)\n",
7763 !!encoder->base.crtc, enabled);
7764 WARN(active && !encoder->base.crtc,
7765 "active encoder with no crtc\n");
7766
7767 WARN(encoder->connectors_active != active,
7768 "encoder's computed active state doesn't match tracked active state "
7769 "(expected %i, found %i)\n", active, encoder->connectors_active);
7770
7771 active = encoder->get_hw_state(encoder, &pipe);
7772 WARN(active != encoder->connectors_active,
7773 "encoder's hw state doesn't match sw tracking "
7774 "(expected %i, found %i)\n",
7775 encoder->connectors_active, active);
7776
7777 if (!encoder->base.crtc)
7778 continue;
7779
7780 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7781 WARN(active && pipe != tracked_pipe,
7782 "active encoder's pipe doesn't match"
7783 "(expected %i, found %i)\n",
7784 tracked_pipe, pipe);
7785
7786 }
7787
7788 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7789 base.head) {
7790 bool enabled = false;
7791 bool active = false;
7792
7793 DRM_DEBUG_KMS("[CRTC:%d]\n",
7794 crtc->base.base.id);
7795
7796 WARN(crtc->active && !crtc->base.enabled,
7797 "active crtc, but not enabled in sw tracking\n");
7798
7799 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7800 base.head) {
7801 if (encoder->base.crtc != &crtc->base)
7802 continue;
7803 enabled = true;
7804 if (encoder->connectors_active)
7805 active = true;
7806 }
7807 WARN(active != crtc->active,
7808 "crtc's computed active state doesn't match tracked active state "
7809 "(expected %i, found %i)\n", active, crtc->active);
7810 WARN(enabled != crtc->base.enabled,
7811 "crtc's computed enabled state doesn't match tracked enabled state "
7812 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7813
7814 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7815 }
7816 }
7817
7818 int intel_set_mode(struct drm_crtc *crtc,
7819 struct drm_display_mode *mode,
7820 int x, int y, struct drm_framebuffer *fb)
7821 {
7822 struct drm_device *dev = crtc->dev;
7823 drm_i915_private_t *dev_priv = dev->dev_private;
7824 struct drm_display_mode *saved_mode, *saved_hwmode;
7825 struct intel_crtc_config *pipe_config = NULL;
7826 struct intel_crtc *intel_crtc;
7827 unsigned disable_pipes, prepare_pipes, modeset_pipes;
7828 int ret = 0;
7829
7830 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
7831 if (!saved_mode)
7832 return -ENOMEM;
7833 saved_hwmode = saved_mode + 1;
7834
7835 intel_modeset_affected_pipes(crtc, &modeset_pipes,
7836 &prepare_pipes, &disable_pipes);
7837
7838 *saved_hwmode = crtc->hwmode;
7839 *saved_mode = crtc->mode;
7840
7841 /* Hack: Because we don't (yet) support global modeset on multiple
7842 * crtcs, we don't keep track of the new mode for more than one crtc.
7843 * Hence simply check whether any bit is set in modeset_pipes in all the
7844 * pieces of code that are not yet converted to deal with mutliple crtcs
7845 * changing their mode at the same time. */
7846 if (modeset_pipes) {
7847 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
7848 if (IS_ERR(pipe_config)) {
7849 ret = PTR_ERR(pipe_config);
7850 pipe_config = NULL;
7851
7852 goto out;
7853 }
7854 }
7855
7856 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7857 modeset_pipes, prepare_pipes, disable_pipes);
7858
7859 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7860 intel_crtc_disable(&intel_crtc->base);
7861
7862 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7863 if (intel_crtc->base.enabled)
7864 dev_priv->display.crtc_disable(&intel_crtc->base);
7865 }
7866
7867 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7868 * to set it here already despite that we pass it down the callchain.
7869 */
7870 if (modeset_pipes) {
7871 crtc->mode = *mode;
7872 /* mode_set/enable/disable functions rely on a correct pipe
7873 * config. */
7874 to_intel_crtc(crtc)->config = *pipe_config;
7875 }
7876
7877 /* Only after disabling all output pipelines that will be changed can we
7878 * update the the output configuration. */
7879 intel_modeset_update_state(dev, prepare_pipes);
7880
7881 if (dev_priv->display.modeset_global_resources)
7882 dev_priv->display.modeset_global_resources(dev);
7883
7884 /* Set up the DPLL and any encoders state that needs to adjust or depend
7885 * on the DPLL.
7886 */
7887 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7888 ret = intel_crtc_mode_set(&intel_crtc->base,
7889 x, y, fb);
7890 if (ret)
7891 goto done;
7892 }
7893
7894 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7895 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7896 dev_priv->display.crtc_enable(&intel_crtc->base);
7897
7898 if (modeset_pipes) {
7899 /* Store real post-adjustment hardware mode. */
7900 crtc->hwmode = pipe_config->adjusted_mode;
7901
7902 /* Calculate and store various constants which
7903 * are later needed by vblank and swap-completion
7904 * timestamping. They are derived from true hwmode.
7905 */
7906 drm_calc_timestamping_constants(crtc);
7907 }
7908
7909 /* FIXME: add subpixel order */
7910 done:
7911 if (ret && crtc->enabled) {
7912 crtc->hwmode = *saved_hwmode;
7913 crtc->mode = *saved_mode;
7914 } else {
7915 intel_modeset_check_state(dev);
7916 }
7917
7918 out:
7919 kfree(pipe_config);
7920 kfree(saved_mode);
7921 return ret;
7922 }
7923
7924 void intel_crtc_restore_mode(struct drm_crtc *crtc)
7925 {
7926 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7927 }
7928
7929 #undef for_each_intel_crtc_masked
7930
7931 static void intel_set_config_free(struct intel_set_config *config)
7932 {
7933 if (!config)
7934 return;
7935
7936 kfree(config->save_connector_encoders);
7937 kfree(config->save_encoder_crtcs);
7938 kfree(config);
7939 }
7940
7941 static int intel_set_config_save_state(struct drm_device *dev,
7942 struct intel_set_config *config)
7943 {
7944 struct drm_encoder *encoder;
7945 struct drm_connector *connector;
7946 int count;
7947
7948 config->save_encoder_crtcs =
7949 kcalloc(dev->mode_config.num_encoder,
7950 sizeof(struct drm_crtc *), GFP_KERNEL);
7951 if (!config->save_encoder_crtcs)
7952 return -ENOMEM;
7953
7954 config->save_connector_encoders =
7955 kcalloc(dev->mode_config.num_connector,
7956 sizeof(struct drm_encoder *), GFP_KERNEL);
7957 if (!config->save_connector_encoders)
7958 return -ENOMEM;
7959
7960 /* Copy data. Note that driver private data is not affected.
7961 * Should anything bad happen only the expected state is
7962 * restored, not the drivers personal bookkeeping.
7963 */
7964 count = 0;
7965 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7966 config->save_encoder_crtcs[count++] = encoder->crtc;
7967 }
7968
7969 count = 0;
7970 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7971 config->save_connector_encoders[count++] = connector->encoder;
7972 }
7973
7974 return 0;
7975 }
7976
7977 static void intel_set_config_restore_state(struct drm_device *dev,
7978 struct intel_set_config *config)
7979 {
7980 struct intel_encoder *encoder;
7981 struct intel_connector *connector;
7982 int count;
7983
7984 count = 0;
7985 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7986 encoder->new_crtc =
7987 to_intel_crtc(config->save_encoder_crtcs[count++]);
7988 }
7989
7990 count = 0;
7991 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7992 connector->new_encoder =
7993 to_intel_encoder(config->save_connector_encoders[count++]);
7994 }
7995 }
7996
7997 static void
7998 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7999 struct intel_set_config *config)
8000 {
8001
8002 /* We should be able to check here if the fb has the same properties
8003 * and then just flip_or_move it */
8004 if (set->crtc->fb != set->fb) {
8005 /* If we have no fb then treat it as a full mode set */
8006 if (set->crtc->fb == NULL) {
8007 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8008 config->mode_changed = true;
8009 } else if (set->fb == NULL) {
8010 config->mode_changed = true;
8011 } else if (set->fb->pixel_format !=
8012 set->crtc->fb->pixel_format) {
8013 config->mode_changed = true;
8014 } else
8015 config->fb_changed = true;
8016 }
8017
8018 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8019 config->fb_changed = true;
8020
8021 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8022 DRM_DEBUG_KMS("modes are different, full mode set\n");
8023 drm_mode_debug_printmodeline(&set->crtc->mode);
8024 drm_mode_debug_printmodeline(set->mode);
8025 config->mode_changed = true;
8026 }
8027 }
8028
8029 static int
8030 intel_modeset_stage_output_state(struct drm_device *dev,
8031 struct drm_mode_set *set,
8032 struct intel_set_config *config)
8033 {
8034 struct drm_crtc *new_crtc;
8035 struct intel_connector *connector;
8036 struct intel_encoder *encoder;
8037 int count, ro;
8038
8039 /* The upper layers ensure that we either disable a crtc or have a list
8040 * of connectors. For paranoia, double-check this. */
8041 WARN_ON(!set->fb && (set->num_connectors != 0));
8042 WARN_ON(set->fb && (set->num_connectors == 0));
8043
8044 count = 0;
8045 list_for_each_entry(connector, &dev->mode_config.connector_list,
8046 base.head) {
8047 /* Otherwise traverse passed in connector list and get encoders
8048 * for them. */
8049 for (ro = 0; ro < set->num_connectors; ro++) {
8050 if (set->connectors[ro] == &connector->base) {
8051 connector->new_encoder = connector->encoder;
8052 break;
8053 }
8054 }
8055
8056 /* If we disable the crtc, disable all its connectors. Also, if
8057 * the connector is on the changing crtc but not on the new
8058 * connector list, disable it. */
8059 if ((!set->fb || ro == set->num_connectors) &&
8060 connector->base.encoder &&
8061 connector->base.encoder->crtc == set->crtc) {
8062 connector->new_encoder = NULL;
8063
8064 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8065 connector->base.base.id,
8066 drm_get_connector_name(&connector->base));
8067 }
8068
8069
8070 if (&connector->new_encoder->base != connector->base.encoder) {
8071 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8072 config->mode_changed = true;
8073 }
8074 }
8075 /* connector->new_encoder is now updated for all connectors. */
8076
8077 /* Update crtc of enabled connectors. */
8078 count = 0;
8079 list_for_each_entry(connector, &dev->mode_config.connector_list,
8080 base.head) {
8081 if (!connector->new_encoder)
8082 continue;
8083
8084 new_crtc = connector->new_encoder->base.crtc;
8085
8086 for (ro = 0; ro < set->num_connectors; ro++) {
8087 if (set->connectors[ro] == &connector->base)
8088 new_crtc = set->crtc;
8089 }
8090
8091 /* Make sure the new CRTC will work with the encoder */
8092 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8093 new_crtc)) {
8094 return -EINVAL;
8095 }
8096 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8097
8098 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8099 connector->base.base.id,
8100 drm_get_connector_name(&connector->base),
8101 new_crtc->base.id);
8102 }
8103
8104 /* Check for any encoders that needs to be disabled. */
8105 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8106 base.head) {
8107 list_for_each_entry(connector,
8108 &dev->mode_config.connector_list,
8109 base.head) {
8110 if (connector->new_encoder == encoder) {
8111 WARN_ON(!connector->new_encoder->new_crtc);
8112
8113 goto next_encoder;
8114 }
8115 }
8116 encoder->new_crtc = NULL;
8117 next_encoder:
8118 /* Only now check for crtc changes so we don't miss encoders
8119 * that will be disabled. */
8120 if (&encoder->new_crtc->base != encoder->base.crtc) {
8121 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8122 config->mode_changed = true;
8123 }
8124 }
8125 /* Now we've also updated encoder->new_crtc for all encoders. */
8126
8127 return 0;
8128 }
8129
8130 static int intel_crtc_set_config(struct drm_mode_set *set)
8131 {
8132 struct drm_device *dev;
8133 struct drm_mode_set save_set;
8134 struct intel_set_config *config;
8135 int ret;
8136
8137 BUG_ON(!set);
8138 BUG_ON(!set->crtc);
8139 BUG_ON(!set->crtc->helper_private);
8140
8141 /* Enforce sane interface api - has been abused by the fb helper. */
8142 BUG_ON(!set->mode && set->fb);
8143 BUG_ON(set->fb && set->num_connectors == 0);
8144
8145 if (set->fb) {
8146 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8147 set->crtc->base.id, set->fb->base.id,
8148 (int)set->num_connectors, set->x, set->y);
8149 } else {
8150 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8151 }
8152
8153 dev = set->crtc->dev;
8154
8155 ret = -ENOMEM;
8156 config = kzalloc(sizeof(*config), GFP_KERNEL);
8157 if (!config)
8158 goto out_config;
8159
8160 ret = intel_set_config_save_state(dev, config);
8161 if (ret)
8162 goto out_config;
8163
8164 save_set.crtc = set->crtc;
8165 save_set.mode = &set->crtc->mode;
8166 save_set.x = set->crtc->x;
8167 save_set.y = set->crtc->y;
8168 save_set.fb = set->crtc->fb;
8169
8170 /* Compute whether we need a full modeset, only an fb base update or no
8171 * change at all. In the future we might also check whether only the
8172 * mode changed, e.g. for LVDS where we only change the panel fitter in
8173 * such cases. */
8174 intel_set_config_compute_mode_changes(set, config);
8175
8176 ret = intel_modeset_stage_output_state(dev, set, config);
8177 if (ret)
8178 goto fail;
8179
8180 if (config->mode_changed) {
8181 if (set->mode) {
8182 DRM_DEBUG_KMS("attempting to set mode from"
8183 " userspace\n");
8184 drm_mode_debug_printmodeline(set->mode);
8185 }
8186
8187 ret = intel_set_mode(set->crtc, set->mode,
8188 set->x, set->y, set->fb);
8189 if (ret) {
8190 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8191 set->crtc->base.id, ret);
8192 goto fail;
8193 }
8194 } else if (config->fb_changed) {
8195 intel_crtc_wait_for_pending_flips(set->crtc);
8196
8197 ret = intel_pipe_set_base(set->crtc,
8198 set->x, set->y, set->fb);
8199 }
8200
8201 intel_set_config_free(config);
8202
8203 return 0;
8204
8205 fail:
8206 intel_set_config_restore_state(dev, config);
8207
8208 /* Try to restore the config */
8209 if (config->mode_changed &&
8210 intel_set_mode(save_set.crtc, save_set.mode,
8211 save_set.x, save_set.y, save_set.fb))
8212 DRM_ERROR("failed to restore config after modeset failure\n");
8213
8214 out_config:
8215 intel_set_config_free(config);
8216 return ret;
8217 }
8218
8219 static const struct drm_crtc_funcs intel_crtc_funcs = {
8220 .cursor_set = intel_crtc_cursor_set,
8221 .cursor_move = intel_crtc_cursor_move,
8222 .gamma_set = intel_crtc_gamma_set,
8223 .set_config = intel_crtc_set_config,
8224 .destroy = intel_crtc_destroy,
8225 .page_flip = intel_crtc_page_flip,
8226 };
8227
8228 static void intel_cpu_pll_init(struct drm_device *dev)
8229 {
8230 if (HAS_DDI(dev))
8231 intel_ddi_pll_init(dev);
8232 }
8233
8234 static void intel_pch_pll_init(struct drm_device *dev)
8235 {
8236 drm_i915_private_t *dev_priv = dev->dev_private;
8237 int i;
8238
8239 if (dev_priv->num_pch_pll == 0) {
8240 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8241 return;
8242 }
8243
8244 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8245 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8246 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8247 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8248 }
8249 }
8250
8251 static void intel_crtc_init(struct drm_device *dev, int pipe)
8252 {
8253 drm_i915_private_t *dev_priv = dev->dev_private;
8254 struct intel_crtc *intel_crtc;
8255 int i;
8256
8257 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8258 if (intel_crtc == NULL)
8259 return;
8260
8261 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8262
8263 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8264 for (i = 0; i < 256; i++) {
8265 intel_crtc->lut_r[i] = i;
8266 intel_crtc->lut_g[i] = i;
8267 intel_crtc->lut_b[i] = i;
8268 }
8269
8270 /* Swap pipes & planes for FBC on pre-965 */
8271 intel_crtc->pipe = pipe;
8272 intel_crtc->plane = pipe;
8273 intel_crtc->cpu_transcoder = pipe;
8274 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8275 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8276 intel_crtc->plane = !pipe;
8277 }
8278
8279 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8280 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8281 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8282 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8283
8284 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8285 }
8286
8287 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8288 struct drm_file *file)
8289 {
8290 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8291 struct drm_mode_object *drmmode_obj;
8292 struct intel_crtc *crtc;
8293
8294 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8295 return -ENODEV;
8296
8297 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8298 DRM_MODE_OBJECT_CRTC);
8299
8300 if (!drmmode_obj) {
8301 DRM_ERROR("no such CRTC id\n");
8302 return -EINVAL;
8303 }
8304
8305 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8306 pipe_from_crtc_id->pipe = crtc->pipe;
8307
8308 return 0;
8309 }
8310
8311 static int intel_encoder_clones(struct intel_encoder *encoder)
8312 {
8313 struct drm_device *dev = encoder->base.dev;
8314 struct intel_encoder *source_encoder;
8315 int index_mask = 0;
8316 int entry = 0;
8317
8318 list_for_each_entry(source_encoder,
8319 &dev->mode_config.encoder_list, base.head) {
8320
8321 if (encoder == source_encoder)
8322 index_mask |= (1 << entry);
8323
8324 /* Intel hw has only one MUX where enocoders could be cloned. */
8325 if (encoder->cloneable && source_encoder->cloneable)
8326 index_mask |= (1 << entry);
8327
8328 entry++;
8329 }
8330
8331 return index_mask;
8332 }
8333
8334 static bool has_edp_a(struct drm_device *dev)
8335 {
8336 struct drm_i915_private *dev_priv = dev->dev_private;
8337
8338 if (!IS_MOBILE(dev))
8339 return false;
8340
8341 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8342 return false;
8343
8344 if (IS_GEN5(dev) &&
8345 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8346 return false;
8347
8348 return true;
8349 }
8350
8351 static void intel_setup_outputs(struct drm_device *dev)
8352 {
8353 struct drm_i915_private *dev_priv = dev->dev_private;
8354 struct intel_encoder *encoder;
8355 bool dpd_is_edp = false;
8356 bool has_lvds;
8357
8358 has_lvds = intel_lvds_init(dev);
8359 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8360 /* disable the panel fitter on everything but LVDS */
8361 I915_WRITE(PFIT_CONTROL, 0);
8362 }
8363
8364 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8365 intel_crt_init(dev);
8366
8367 if (HAS_DDI(dev)) {
8368 int found;
8369
8370 /* Haswell uses DDI functions to detect digital outputs */
8371 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8372 /* DDI A only supports eDP */
8373 if (found)
8374 intel_ddi_init(dev, PORT_A);
8375
8376 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8377 * register */
8378 found = I915_READ(SFUSE_STRAP);
8379
8380 if (found & SFUSE_STRAP_DDIB_DETECTED)
8381 intel_ddi_init(dev, PORT_B);
8382 if (found & SFUSE_STRAP_DDIC_DETECTED)
8383 intel_ddi_init(dev, PORT_C);
8384 if (found & SFUSE_STRAP_DDID_DETECTED)
8385 intel_ddi_init(dev, PORT_D);
8386 } else if (HAS_PCH_SPLIT(dev)) {
8387 int found;
8388 dpd_is_edp = intel_dpd_is_edp(dev);
8389
8390 if (has_edp_a(dev))
8391 intel_dp_init(dev, DP_A, PORT_A);
8392
8393 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8394 /* PCH SDVOB multiplex with HDMIB */
8395 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8396 if (!found)
8397 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8398 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8399 intel_dp_init(dev, PCH_DP_B, PORT_B);
8400 }
8401
8402 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8403 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8404
8405 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8406 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8407
8408 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8409 intel_dp_init(dev, PCH_DP_C, PORT_C);
8410
8411 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8412 intel_dp_init(dev, PCH_DP_D, PORT_D);
8413 } else if (IS_VALLEYVIEW(dev)) {
8414 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8415 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8416 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8417
8418 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8419 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8420 PORT_B);
8421 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8422 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8423 }
8424 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8425 bool found = false;
8426
8427 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8428 DRM_DEBUG_KMS("probing SDVOB\n");
8429 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8430 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8431 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8432 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8433 }
8434
8435 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8436 DRM_DEBUG_KMS("probing DP_B\n");
8437 intel_dp_init(dev, DP_B, PORT_B);
8438 }
8439 }
8440
8441 /* Before G4X SDVOC doesn't have its own detect register */
8442
8443 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8444 DRM_DEBUG_KMS("probing SDVOC\n");
8445 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8446 }
8447
8448 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8449
8450 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8451 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8452 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8453 }
8454 if (SUPPORTS_INTEGRATED_DP(dev)) {
8455 DRM_DEBUG_KMS("probing DP_C\n");
8456 intel_dp_init(dev, DP_C, PORT_C);
8457 }
8458 }
8459
8460 if (SUPPORTS_INTEGRATED_DP(dev) &&
8461 (I915_READ(DP_D) & DP_DETECTED)) {
8462 DRM_DEBUG_KMS("probing DP_D\n");
8463 intel_dp_init(dev, DP_D, PORT_D);
8464 }
8465 } else if (IS_GEN2(dev))
8466 intel_dvo_init(dev);
8467
8468 if (SUPPORTS_TV(dev))
8469 intel_tv_init(dev);
8470
8471 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8472 encoder->base.possible_crtcs = encoder->crtc_mask;
8473 encoder->base.possible_clones =
8474 intel_encoder_clones(encoder);
8475 }
8476
8477 intel_init_pch_refclk(dev);
8478
8479 drm_helper_move_panel_connectors_to_head(dev);
8480 }
8481
8482 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8483 {
8484 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8485
8486 drm_framebuffer_cleanup(fb);
8487 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8488
8489 kfree(intel_fb);
8490 }
8491
8492 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8493 struct drm_file *file,
8494 unsigned int *handle)
8495 {
8496 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8497 struct drm_i915_gem_object *obj = intel_fb->obj;
8498
8499 return drm_gem_handle_create(file, &obj->base, handle);
8500 }
8501
8502 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8503 .destroy = intel_user_framebuffer_destroy,
8504 .create_handle = intel_user_framebuffer_create_handle,
8505 };
8506
8507 int intel_framebuffer_init(struct drm_device *dev,
8508 struct intel_framebuffer *intel_fb,
8509 struct drm_mode_fb_cmd2 *mode_cmd,
8510 struct drm_i915_gem_object *obj)
8511 {
8512 int ret;
8513
8514 if (obj->tiling_mode == I915_TILING_Y) {
8515 DRM_DEBUG("hardware does not support tiling Y\n");
8516 return -EINVAL;
8517 }
8518
8519 if (mode_cmd->pitches[0] & 63) {
8520 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8521 mode_cmd->pitches[0]);
8522 return -EINVAL;
8523 }
8524
8525 /* FIXME <= Gen4 stride limits are bit unclear */
8526 if (mode_cmd->pitches[0] > 32768) {
8527 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8528 mode_cmd->pitches[0]);
8529 return -EINVAL;
8530 }
8531
8532 if (obj->tiling_mode != I915_TILING_NONE &&
8533 mode_cmd->pitches[0] != obj->stride) {
8534 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8535 mode_cmd->pitches[0], obj->stride);
8536 return -EINVAL;
8537 }
8538
8539 /* Reject formats not supported by any plane early. */
8540 switch (mode_cmd->pixel_format) {
8541 case DRM_FORMAT_C8:
8542 case DRM_FORMAT_RGB565:
8543 case DRM_FORMAT_XRGB8888:
8544 case DRM_FORMAT_ARGB8888:
8545 break;
8546 case DRM_FORMAT_XRGB1555:
8547 case DRM_FORMAT_ARGB1555:
8548 if (INTEL_INFO(dev)->gen > 3) {
8549 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8550 return -EINVAL;
8551 }
8552 break;
8553 case DRM_FORMAT_XBGR8888:
8554 case DRM_FORMAT_ABGR8888:
8555 case DRM_FORMAT_XRGB2101010:
8556 case DRM_FORMAT_ARGB2101010:
8557 case DRM_FORMAT_XBGR2101010:
8558 case DRM_FORMAT_ABGR2101010:
8559 if (INTEL_INFO(dev)->gen < 4) {
8560 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8561 return -EINVAL;
8562 }
8563 break;
8564 case DRM_FORMAT_YUYV:
8565 case DRM_FORMAT_UYVY:
8566 case DRM_FORMAT_YVYU:
8567 case DRM_FORMAT_VYUY:
8568 if (INTEL_INFO(dev)->gen < 5) {
8569 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8570 return -EINVAL;
8571 }
8572 break;
8573 default:
8574 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8575 return -EINVAL;
8576 }
8577
8578 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8579 if (mode_cmd->offsets[0] != 0)
8580 return -EINVAL;
8581
8582 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8583 intel_fb->obj = obj;
8584
8585 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8586 if (ret) {
8587 DRM_ERROR("framebuffer init failed %d\n", ret);
8588 return ret;
8589 }
8590
8591 return 0;
8592 }
8593
8594 static struct drm_framebuffer *
8595 intel_user_framebuffer_create(struct drm_device *dev,
8596 struct drm_file *filp,
8597 struct drm_mode_fb_cmd2 *mode_cmd)
8598 {
8599 struct drm_i915_gem_object *obj;
8600
8601 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8602 mode_cmd->handles[0]));
8603 if (&obj->base == NULL)
8604 return ERR_PTR(-ENOENT);
8605
8606 return intel_framebuffer_create(dev, mode_cmd, obj);
8607 }
8608
8609 static const struct drm_mode_config_funcs intel_mode_funcs = {
8610 .fb_create = intel_user_framebuffer_create,
8611 .output_poll_changed = intel_fb_output_poll_changed,
8612 };
8613
8614 /* Set up chip specific display functions */
8615 static void intel_init_display(struct drm_device *dev)
8616 {
8617 struct drm_i915_private *dev_priv = dev->dev_private;
8618
8619 if (HAS_DDI(dev)) {
8620 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8621 dev_priv->display.crtc_enable = haswell_crtc_enable;
8622 dev_priv->display.crtc_disable = haswell_crtc_disable;
8623 dev_priv->display.off = haswell_crtc_off;
8624 dev_priv->display.update_plane = ironlake_update_plane;
8625 } else if (HAS_PCH_SPLIT(dev)) {
8626 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8627 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8628 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8629 dev_priv->display.off = ironlake_crtc_off;
8630 dev_priv->display.update_plane = ironlake_update_plane;
8631 } else {
8632 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8633 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8634 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8635 dev_priv->display.off = i9xx_crtc_off;
8636 dev_priv->display.update_plane = i9xx_update_plane;
8637 }
8638
8639 /* Returns the core display clock speed */
8640 if (IS_VALLEYVIEW(dev))
8641 dev_priv->display.get_display_clock_speed =
8642 valleyview_get_display_clock_speed;
8643 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8644 dev_priv->display.get_display_clock_speed =
8645 i945_get_display_clock_speed;
8646 else if (IS_I915G(dev))
8647 dev_priv->display.get_display_clock_speed =
8648 i915_get_display_clock_speed;
8649 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8650 dev_priv->display.get_display_clock_speed =
8651 i9xx_misc_get_display_clock_speed;
8652 else if (IS_I915GM(dev))
8653 dev_priv->display.get_display_clock_speed =
8654 i915gm_get_display_clock_speed;
8655 else if (IS_I865G(dev))
8656 dev_priv->display.get_display_clock_speed =
8657 i865_get_display_clock_speed;
8658 else if (IS_I85X(dev))
8659 dev_priv->display.get_display_clock_speed =
8660 i855_get_display_clock_speed;
8661 else /* 852, 830 */
8662 dev_priv->display.get_display_clock_speed =
8663 i830_get_display_clock_speed;
8664
8665 if (HAS_PCH_SPLIT(dev)) {
8666 if (IS_GEN5(dev)) {
8667 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8668 dev_priv->display.write_eld = ironlake_write_eld;
8669 } else if (IS_GEN6(dev)) {
8670 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8671 dev_priv->display.write_eld = ironlake_write_eld;
8672 } else if (IS_IVYBRIDGE(dev)) {
8673 /* FIXME: detect B0+ stepping and use auto training */
8674 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8675 dev_priv->display.write_eld = ironlake_write_eld;
8676 dev_priv->display.modeset_global_resources =
8677 ivb_modeset_global_resources;
8678 } else if (IS_HASWELL(dev)) {
8679 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8680 dev_priv->display.write_eld = haswell_write_eld;
8681 dev_priv->display.modeset_global_resources =
8682 haswell_modeset_global_resources;
8683 }
8684 } else if (IS_G4X(dev)) {
8685 dev_priv->display.write_eld = g4x_write_eld;
8686 }
8687
8688 /* Default just returns -ENODEV to indicate unsupported */
8689 dev_priv->display.queue_flip = intel_default_queue_flip;
8690
8691 switch (INTEL_INFO(dev)->gen) {
8692 case 2:
8693 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8694 break;
8695
8696 case 3:
8697 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8698 break;
8699
8700 case 4:
8701 case 5:
8702 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8703 break;
8704
8705 case 6:
8706 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8707 break;
8708 case 7:
8709 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8710 break;
8711 }
8712 }
8713
8714 /*
8715 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8716 * resume, or other times. This quirk makes sure that's the case for
8717 * affected systems.
8718 */
8719 static void quirk_pipea_force(struct drm_device *dev)
8720 {
8721 struct drm_i915_private *dev_priv = dev->dev_private;
8722
8723 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8724 DRM_INFO("applying pipe a force quirk\n");
8725 }
8726
8727 /*
8728 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8729 */
8730 static void quirk_ssc_force_disable(struct drm_device *dev)
8731 {
8732 struct drm_i915_private *dev_priv = dev->dev_private;
8733 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8734 DRM_INFO("applying lvds SSC disable quirk\n");
8735 }
8736
8737 /*
8738 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8739 * brightness value
8740 */
8741 static void quirk_invert_brightness(struct drm_device *dev)
8742 {
8743 struct drm_i915_private *dev_priv = dev->dev_private;
8744 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8745 DRM_INFO("applying inverted panel brightness quirk\n");
8746 }
8747
8748 struct intel_quirk {
8749 int device;
8750 int subsystem_vendor;
8751 int subsystem_device;
8752 void (*hook)(struct drm_device *dev);
8753 };
8754
8755 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8756 struct intel_dmi_quirk {
8757 void (*hook)(struct drm_device *dev);
8758 const struct dmi_system_id (*dmi_id_list)[];
8759 };
8760
8761 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8762 {
8763 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8764 return 1;
8765 }
8766
8767 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8768 {
8769 .dmi_id_list = &(const struct dmi_system_id[]) {
8770 {
8771 .callback = intel_dmi_reverse_brightness,
8772 .ident = "NCR Corporation",
8773 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8774 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8775 },
8776 },
8777 { } /* terminating entry */
8778 },
8779 .hook = quirk_invert_brightness,
8780 },
8781 };
8782
8783 static struct intel_quirk intel_quirks[] = {
8784 /* HP Mini needs pipe A force quirk (LP: #322104) */
8785 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8786
8787 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8788 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8789
8790 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8791 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8792
8793 /* 830/845 need to leave pipe A & dpll A up */
8794 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8795 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8796
8797 /* Lenovo U160 cannot use SSC on LVDS */
8798 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8799
8800 /* Sony Vaio Y cannot use SSC on LVDS */
8801 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8802
8803 /* Acer Aspire 5734Z must invert backlight brightness */
8804 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8805
8806 /* Acer/eMachines G725 */
8807 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
8808
8809 /* Acer/eMachines e725 */
8810 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
8811
8812 /* Acer/Packard Bell NCL20 */
8813 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
8814
8815 /* Acer Aspire 4736Z */
8816 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
8817 };
8818
8819 static void intel_init_quirks(struct drm_device *dev)
8820 {
8821 struct pci_dev *d = dev->pdev;
8822 int i;
8823
8824 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8825 struct intel_quirk *q = &intel_quirks[i];
8826
8827 if (d->device == q->device &&
8828 (d->subsystem_vendor == q->subsystem_vendor ||
8829 q->subsystem_vendor == PCI_ANY_ID) &&
8830 (d->subsystem_device == q->subsystem_device ||
8831 q->subsystem_device == PCI_ANY_ID))
8832 q->hook(dev);
8833 }
8834 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8835 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8836 intel_dmi_quirks[i].hook(dev);
8837 }
8838 }
8839
8840 /* Disable the VGA plane that we never use */
8841 static void i915_disable_vga(struct drm_device *dev)
8842 {
8843 struct drm_i915_private *dev_priv = dev->dev_private;
8844 u8 sr1;
8845 u32 vga_reg = i915_vgacntrl_reg(dev);
8846
8847 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8848 outb(SR01, VGA_SR_INDEX);
8849 sr1 = inb(VGA_SR_DATA);
8850 outb(sr1 | 1<<5, VGA_SR_DATA);
8851 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8852 udelay(300);
8853
8854 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8855 POSTING_READ(vga_reg);
8856 }
8857
8858 void intel_modeset_init_hw(struct drm_device *dev)
8859 {
8860 intel_init_power_well(dev);
8861
8862 intel_prepare_ddi(dev);
8863
8864 intel_init_clock_gating(dev);
8865
8866 mutex_lock(&dev->struct_mutex);
8867 intel_enable_gt_powersave(dev);
8868 mutex_unlock(&dev->struct_mutex);
8869 }
8870
8871 void intel_modeset_init(struct drm_device *dev)
8872 {
8873 struct drm_i915_private *dev_priv = dev->dev_private;
8874 int i, j, ret;
8875
8876 drm_mode_config_init(dev);
8877
8878 dev->mode_config.min_width = 0;
8879 dev->mode_config.min_height = 0;
8880
8881 dev->mode_config.preferred_depth = 24;
8882 dev->mode_config.prefer_shadow = 1;
8883
8884 dev->mode_config.funcs = &intel_mode_funcs;
8885
8886 intel_init_quirks(dev);
8887
8888 intel_init_pm(dev);
8889
8890 intel_init_display(dev);
8891
8892 if (IS_GEN2(dev)) {
8893 dev->mode_config.max_width = 2048;
8894 dev->mode_config.max_height = 2048;
8895 } else if (IS_GEN3(dev)) {
8896 dev->mode_config.max_width = 4096;
8897 dev->mode_config.max_height = 4096;
8898 } else {
8899 dev->mode_config.max_width = 8192;
8900 dev->mode_config.max_height = 8192;
8901 }
8902 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
8903
8904 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8905 INTEL_INFO(dev)->num_pipes,
8906 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
8907
8908 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
8909 intel_crtc_init(dev, i);
8910 for (j = 0; j < dev_priv->num_plane; j++) {
8911 ret = intel_plane_init(dev, i, j);
8912 if (ret)
8913 DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
8914 i, j, ret);
8915 }
8916 }
8917
8918 intel_cpu_pll_init(dev);
8919 intel_pch_pll_init(dev);
8920
8921 /* Just disable it once at startup */
8922 i915_disable_vga(dev);
8923 intel_setup_outputs(dev);
8924
8925 /* Just in case the BIOS is doing something questionable. */
8926 intel_disable_fbc(dev);
8927 }
8928
8929 static void
8930 intel_connector_break_all_links(struct intel_connector *connector)
8931 {
8932 connector->base.dpms = DRM_MODE_DPMS_OFF;
8933 connector->base.encoder = NULL;
8934 connector->encoder->connectors_active = false;
8935 connector->encoder->base.crtc = NULL;
8936 }
8937
8938 static void intel_enable_pipe_a(struct drm_device *dev)
8939 {
8940 struct intel_connector *connector;
8941 struct drm_connector *crt = NULL;
8942 struct intel_load_detect_pipe load_detect_temp;
8943
8944 /* We can't just switch on the pipe A, we need to set things up with a
8945 * proper mode and output configuration. As a gross hack, enable pipe A
8946 * by enabling the load detect pipe once. */
8947 list_for_each_entry(connector,
8948 &dev->mode_config.connector_list,
8949 base.head) {
8950 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8951 crt = &connector->base;
8952 break;
8953 }
8954 }
8955
8956 if (!crt)
8957 return;
8958
8959 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8960 intel_release_load_detect_pipe(crt, &load_detect_temp);
8961
8962
8963 }
8964
8965 static bool
8966 intel_check_plane_mapping(struct intel_crtc *crtc)
8967 {
8968 struct drm_device *dev = crtc->base.dev;
8969 struct drm_i915_private *dev_priv = dev->dev_private;
8970 u32 reg, val;
8971
8972 if (INTEL_INFO(dev)->num_pipes == 1)
8973 return true;
8974
8975 reg = DSPCNTR(!crtc->plane);
8976 val = I915_READ(reg);
8977
8978 if ((val & DISPLAY_PLANE_ENABLE) &&
8979 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8980 return false;
8981
8982 return true;
8983 }
8984
8985 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8986 {
8987 struct drm_device *dev = crtc->base.dev;
8988 struct drm_i915_private *dev_priv = dev->dev_private;
8989 u32 reg;
8990
8991 /* Clear any frame start delays used for debugging left by the BIOS */
8992 reg = PIPECONF(crtc->cpu_transcoder);
8993 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8994
8995 /* We need to sanitize the plane -> pipe mapping first because this will
8996 * disable the crtc (and hence change the state) if it is wrong. Note
8997 * that gen4+ has a fixed plane -> pipe mapping. */
8998 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8999 struct intel_connector *connector;
9000 bool plane;
9001
9002 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9003 crtc->base.base.id);
9004
9005 /* Pipe has the wrong plane attached and the plane is active.
9006 * Temporarily change the plane mapping and disable everything
9007 * ... */
9008 plane = crtc->plane;
9009 crtc->plane = !plane;
9010 dev_priv->display.crtc_disable(&crtc->base);
9011 crtc->plane = plane;
9012
9013 /* ... and break all links. */
9014 list_for_each_entry(connector, &dev->mode_config.connector_list,
9015 base.head) {
9016 if (connector->encoder->base.crtc != &crtc->base)
9017 continue;
9018
9019 intel_connector_break_all_links(connector);
9020 }
9021
9022 WARN_ON(crtc->active);
9023 crtc->base.enabled = false;
9024 }
9025
9026 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9027 crtc->pipe == PIPE_A && !crtc->active) {
9028 /* BIOS forgot to enable pipe A, this mostly happens after
9029 * resume. Force-enable the pipe to fix this, the update_dpms
9030 * call below we restore the pipe to the right state, but leave
9031 * the required bits on. */
9032 intel_enable_pipe_a(dev);
9033 }
9034
9035 /* Adjust the state of the output pipe according to whether we
9036 * have active connectors/encoders. */
9037 intel_crtc_update_dpms(&crtc->base);
9038
9039 if (crtc->active != crtc->base.enabled) {
9040 struct intel_encoder *encoder;
9041
9042 /* This can happen either due to bugs in the get_hw_state
9043 * functions or because the pipe is force-enabled due to the
9044 * pipe A quirk. */
9045 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9046 crtc->base.base.id,
9047 crtc->base.enabled ? "enabled" : "disabled",
9048 crtc->active ? "enabled" : "disabled");
9049
9050 crtc->base.enabled = crtc->active;
9051
9052 /* Because we only establish the connector -> encoder ->
9053 * crtc links if something is active, this means the
9054 * crtc is now deactivated. Break the links. connector
9055 * -> encoder links are only establish when things are
9056 * actually up, hence no need to break them. */
9057 WARN_ON(crtc->active);
9058
9059 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9060 WARN_ON(encoder->connectors_active);
9061 encoder->base.crtc = NULL;
9062 }
9063 }
9064 }
9065
9066 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9067 {
9068 struct intel_connector *connector;
9069 struct drm_device *dev = encoder->base.dev;
9070
9071 /* We need to check both for a crtc link (meaning that the
9072 * encoder is active and trying to read from a pipe) and the
9073 * pipe itself being active. */
9074 bool has_active_crtc = encoder->base.crtc &&
9075 to_intel_crtc(encoder->base.crtc)->active;
9076
9077 if (encoder->connectors_active && !has_active_crtc) {
9078 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9079 encoder->base.base.id,
9080 drm_get_encoder_name(&encoder->base));
9081
9082 /* Connector is active, but has no active pipe. This is
9083 * fallout from our resume register restoring. Disable
9084 * the encoder manually again. */
9085 if (encoder->base.crtc) {
9086 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9087 encoder->base.base.id,
9088 drm_get_encoder_name(&encoder->base));
9089 encoder->disable(encoder);
9090 }
9091
9092 /* Inconsistent output/port/pipe state happens presumably due to
9093 * a bug in one of the get_hw_state functions. Or someplace else
9094 * in our code, like the register restore mess on resume. Clamp
9095 * things to off as a safer default. */
9096 list_for_each_entry(connector,
9097 &dev->mode_config.connector_list,
9098 base.head) {
9099 if (connector->encoder != encoder)
9100 continue;
9101
9102 intel_connector_break_all_links(connector);
9103 }
9104 }
9105 /* Enabled encoders without active connectors will be fixed in
9106 * the crtc fixup. */
9107 }
9108
9109 void i915_redisable_vga(struct drm_device *dev)
9110 {
9111 struct drm_i915_private *dev_priv = dev->dev_private;
9112 u32 vga_reg = i915_vgacntrl_reg(dev);
9113
9114 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9115 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9116 i915_disable_vga(dev);
9117 }
9118 }
9119
9120 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9121 * and i915 state tracking structures. */
9122 void intel_modeset_setup_hw_state(struct drm_device *dev,
9123 bool force_restore)
9124 {
9125 struct drm_i915_private *dev_priv = dev->dev_private;
9126 enum pipe pipe;
9127 u32 tmp;
9128 struct drm_plane *plane;
9129 struct intel_crtc *crtc;
9130 struct intel_encoder *encoder;
9131 struct intel_connector *connector;
9132
9133 if (HAS_DDI(dev)) {
9134 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9135
9136 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9137 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9138 case TRANS_DDI_EDP_INPUT_A_ON:
9139 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9140 pipe = PIPE_A;
9141 break;
9142 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9143 pipe = PIPE_B;
9144 break;
9145 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9146 pipe = PIPE_C;
9147 break;
9148 default:
9149 /* A bogus value has been programmed, disable
9150 * the transcoder */
9151 WARN(1, "Bogus eDP source %08x\n", tmp);
9152 intel_ddi_disable_transcoder_func(dev_priv,
9153 TRANSCODER_EDP);
9154 goto setup_pipes;
9155 }
9156
9157 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9158 crtc->cpu_transcoder = TRANSCODER_EDP;
9159
9160 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9161 pipe_name(pipe));
9162 }
9163 }
9164
9165 setup_pipes:
9166 for_each_pipe(pipe) {
9167 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9168
9169 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9170 if (tmp & PIPECONF_ENABLE)
9171 crtc->active = true;
9172 else
9173 crtc->active = false;
9174
9175 crtc->base.enabled = crtc->active;
9176
9177 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9178 crtc->base.base.id,
9179 crtc->active ? "enabled" : "disabled");
9180 }
9181
9182 if (HAS_DDI(dev))
9183 intel_ddi_setup_hw_pll_state(dev);
9184
9185 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9186 base.head) {
9187 pipe = 0;
9188
9189 if (encoder->get_hw_state(encoder, &pipe)) {
9190 encoder->base.crtc =
9191 dev_priv->pipe_to_crtc_mapping[pipe];
9192 } else {
9193 encoder->base.crtc = NULL;
9194 }
9195
9196 encoder->connectors_active = false;
9197 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9198 encoder->base.base.id,
9199 drm_get_encoder_name(&encoder->base),
9200 encoder->base.crtc ? "enabled" : "disabled",
9201 pipe);
9202 }
9203
9204 list_for_each_entry(connector, &dev->mode_config.connector_list,
9205 base.head) {
9206 if (connector->get_hw_state(connector)) {
9207 connector->base.dpms = DRM_MODE_DPMS_ON;
9208 connector->encoder->connectors_active = true;
9209 connector->base.encoder = &connector->encoder->base;
9210 } else {
9211 connector->base.dpms = DRM_MODE_DPMS_OFF;
9212 connector->base.encoder = NULL;
9213 }
9214 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9215 connector->base.base.id,
9216 drm_get_connector_name(&connector->base),
9217 connector->base.encoder ? "enabled" : "disabled");
9218 }
9219
9220 /* HW state is read out, now we need to sanitize this mess. */
9221 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9222 base.head) {
9223 intel_sanitize_encoder(encoder);
9224 }
9225
9226 for_each_pipe(pipe) {
9227 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9228 intel_sanitize_crtc(crtc);
9229 }
9230
9231 if (force_restore) {
9232 for_each_pipe(pipe) {
9233 struct drm_crtc *crtc =
9234 dev_priv->pipe_to_crtc_mapping[pipe];
9235 intel_crtc_restore_mode(crtc);
9236 }
9237 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9238 intel_plane_restore(plane);
9239
9240 i915_redisable_vga(dev);
9241 } else {
9242 intel_modeset_update_staged_output_state(dev);
9243 }
9244
9245 intel_modeset_check_state(dev);
9246
9247 drm_mode_config_reset(dev);
9248 }
9249
9250 void intel_modeset_gem_init(struct drm_device *dev)
9251 {
9252 intel_modeset_init_hw(dev);
9253
9254 intel_setup_overlay(dev);
9255
9256 intel_modeset_setup_hw_state(dev, false);
9257 }
9258
9259 void intel_modeset_cleanup(struct drm_device *dev)
9260 {
9261 struct drm_i915_private *dev_priv = dev->dev_private;
9262 struct drm_crtc *crtc;
9263 struct intel_crtc *intel_crtc;
9264
9265 drm_kms_helper_poll_fini(dev);
9266 mutex_lock(&dev->struct_mutex);
9267
9268 intel_unregister_dsm_handler();
9269
9270
9271 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9272 /* Skip inactive CRTCs */
9273 if (!crtc->fb)
9274 continue;
9275
9276 intel_crtc = to_intel_crtc(crtc);
9277 intel_increase_pllclock(crtc);
9278 }
9279
9280 intel_disable_fbc(dev);
9281
9282 intel_disable_gt_powersave(dev);
9283
9284 ironlake_teardown_rc6(dev);
9285
9286 if (IS_VALLEYVIEW(dev))
9287 vlv_init_dpio(dev);
9288
9289 mutex_unlock(&dev->struct_mutex);
9290
9291 /* Disable the irq before mode object teardown, for the irq might
9292 * enqueue unpin/hotplug work. */
9293 drm_irq_uninstall(dev);
9294 cancel_work_sync(&dev_priv->hotplug_work);
9295 cancel_work_sync(&dev_priv->rps.work);
9296
9297 /* flush any delayed tasks or pending work */
9298 flush_scheduled_work();
9299
9300 drm_mode_config_cleanup(dev);
9301
9302 intel_cleanup_overlay(dev);
9303 }
9304
9305 /*
9306 * Return which encoder is currently attached for connector.
9307 */
9308 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9309 {
9310 return &intel_attached_encoder(connector)->base;
9311 }
9312
9313 void intel_connector_attach_encoder(struct intel_connector *connector,
9314 struct intel_encoder *encoder)
9315 {
9316 connector->encoder = encoder;
9317 drm_mode_connector_attach_encoder(&connector->base,
9318 &encoder->base);
9319 }
9320
9321 /*
9322 * set vga decode state - true == enable VGA decode
9323 */
9324 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9325 {
9326 struct drm_i915_private *dev_priv = dev->dev_private;
9327 u16 gmch_ctrl;
9328
9329 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9330 if (state)
9331 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9332 else
9333 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9334 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9335 return 0;
9336 }
9337
9338 #ifdef CONFIG_DEBUG_FS
9339 #include <linux/seq_file.h>
9340
9341 struct intel_display_error_state {
9342 struct intel_cursor_error_state {
9343 u32 control;
9344 u32 position;
9345 u32 base;
9346 u32 size;
9347 } cursor[I915_MAX_PIPES];
9348
9349 struct intel_pipe_error_state {
9350 u32 conf;
9351 u32 source;
9352
9353 u32 htotal;
9354 u32 hblank;
9355 u32 hsync;
9356 u32 vtotal;
9357 u32 vblank;
9358 u32 vsync;
9359 } pipe[I915_MAX_PIPES];
9360
9361 struct intel_plane_error_state {
9362 u32 control;
9363 u32 stride;
9364 u32 size;
9365 u32 pos;
9366 u32 addr;
9367 u32 surface;
9368 u32 tile_offset;
9369 } plane[I915_MAX_PIPES];
9370 };
9371
9372 struct intel_display_error_state *
9373 intel_display_capture_error_state(struct drm_device *dev)
9374 {
9375 drm_i915_private_t *dev_priv = dev->dev_private;
9376 struct intel_display_error_state *error;
9377 enum transcoder cpu_transcoder;
9378 int i;
9379
9380 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9381 if (error == NULL)
9382 return NULL;
9383
9384 for_each_pipe(i) {
9385 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9386
9387 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9388 error->cursor[i].control = I915_READ(CURCNTR(i));
9389 error->cursor[i].position = I915_READ(CURPOS(i));
9390 error->cursor[i].base = I915_READ(CURBASE(i));
9391 } else {
9392 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9393 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9394 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9395 }
9396
9397 error->plane[i].control = I915_READ(DSPCNTR(i));
9398 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9399 if (INTEL_INFO(dev)->gen <= 3) {
9400 error->plane[i].size = I915_READ(DSPSIZE(i));
9401 error->plane[i].pos = I915_READ(DSPPOS(i));
9402 }
9403 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9404 error->plane[i].addr = I915_READ(DSPADDR(i));
9405 if (INTEL_INFO(dev)->gen >= 4) {
9406 error->plane[i].surface = I915_READ(DSPSURF(i));
9407 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9408 }
9409
9410 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9411 error->pipe[i].source = I915_READ(PIPESRC(i));
9412 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9413 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9414 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9415 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9416 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9417 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9418 }
9419
9420 return error;
9421 }
9422
9423 void
9424 intel_display_print_error_state(struct seq_file *m,
9425 struct drm_device *dev,
9426 struct intel_display_error_state *error)
9427 {
9428 int i;
9429
9430 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9431 for_each_pipe(i) {
9432 seq_printf(m, "Pipe [%d]:\n", i);
9433 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9434 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9435 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9436 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9437 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9438 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9439 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9440 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9441
9442 seq_printf(m, "Plane [%d]:\n", i);
9443 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9444 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9445 if (INTEL_INFO(dev)->gen <= 3) {
9446 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9447 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9448 }
9449 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9450 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9451 if (INTEL_INFO(dev)->gen >= 4) {
9452 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9453 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9454 }
9455
9456 seq_printf(m, "Cursor [%d]:\n", i);
9457 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9458 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9459 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9460 }
9461 }
9462 #endif
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