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drm/i915: move opregion asle request handling to a work queue
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 static void intel_increase_pllclock(struct drm_crtc *crtc);
45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
46
47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
51
52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
54
55
56 typedef struct {
57 int min, max;
58 } intel_range_t;
59
60 typedef struct {
61 int dot_limit;
62 int p2_slow, p2_fast;
63 } intel_p2_t;
64
65 typedef struct intel_limit intel_limit_t;
66 struct intel_limit {
67 intel_range_t dot, vco, n, m, m1, m2, p, p1;
68 intel_p2_t p2;
69 };
70
71 int
72 intel_pch_rawclk(struct drm_device *dev)
73 {
74 struct drm_i915_private *dev_priv = dev->dev_private;
75
76 WARN_ON(!HAS_PCH_SPLIT(dev));
77
78 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
79 }
80
81 static inline u32 /* units of 100MHz */
82 intel_fdi_link_freq(struct drm_device *dev)
83 {
84 if (IS_GEN5(dev)) {
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
87 } else
88 return 27;
89 }
90
91 static const intel_limit_t intel_limits_i8xx_dac = {
92 .dot = { .min = 25000, .max = 350000 },
93 .vco = { .min = 930000, .max = 1400000 },
94 .n = { .min = 3, .max = 16 },
95 .m = { .min = 96, .max = 140 },
96 .m1 = { .min = 18, .max = 26 },
97 .m2 = { .min = 6, .max = 16 },
98 .p = { .min = 4, .max = 128 },
99 .p1 = { .min = 2, .max = 33 },
100 .p2 = { .dot_limit = 165000,
101 .p2_slow = 4, .p2_fast = 2 },
102 };
103
104 static const intel_limit_t intel_limits_i8xx_dvo = {
105 .dot = { .min = 25000, .max = 350000 },
106 .vco = { .min = 930000, .max = 1400000 },
107 .n = { .min = 3, .max = 16 },
108 .m = { .min = 96, .max = 140 },
109 .m1 = { .min = 18, .max = 26 },
110 .m2 = { .min = 6, .max = 16 },
111 .p = { .min = 4, .max = 128 },
112 .p1 = { .min = 2, .max = 33 },
113 .p2 = { .dot_limit = 165000,
114 .p2_slow = 4, .p2_fast = 4 },
115 };
116
117 static const intel_limit_t intel_limits_i8xx_lvds = {
118 .dot = { .min = 25000, .max = 350000 },
119 .vco = { .min = 930000, .max = 1400000 },
120 .n = { .min = 3, .max = 16 },
121 .m = { .min = 96, .max = 140 },
122 .m1 = { .min = 18, .max = 26 },
123 .m2 = { .min = 6, .max = 16 },
124 .p = { .min = 4, .max = 128 },
125 .p1 = { .min = 1, .max = 6 },
126 .p2 = { .dot_limit = 165000,
127 .p2_slow = 14, .p2_fast = 7 },
128 };
129
130 static const intel_limit_t intel_limits_i9xx_sdvo = {
131 .dot = { .min = 20000, .max = 400000 },
132 .vco = { .min = 1400000, .max = 2800000 },
133 .n = { .min = 1, .max = 6 },
134 .m = { .min = 70, .max = 120 },
135 .m1 = { .min = 8, .max = 18 },
136 .m2 = { .min = 3, .max = 7 },
137 .p = { .min = 5, .max = 80 },
138 .p1 = { .min = 1, .max = 8 },
139 .p2 = { .dot_limit = 200000,
140 .p2_slow = 10, .p2_fast = 5 },
141 };
142
143 static const intel_limit_t intel_limits_i9xx_lvds = {
144 .dot = { .min = 20000, .max = 400000 },
145 .vco = { .min = 1400000, .max = 2800000 },
146 .n = { .min = 1, .max = 6 },
147 .m = { .min = 70, .max = 120 },
148 .m1 = { .min = 8, .max = 18 },
149 .m2 = { .min = 3, .max = 7 },
150 .p = { .min = 7, .max = 98 },
151 .p1 = { .min = 1, .max = 8 },
152 .p2 = { .dot_limit = 112000,
153 .p2_slow = 14, .p2_fast = 7 },
154 };
155
156
157 static const intel_limit_t intel_limits_g4x_sdvo = {
158 .dot = { .min = 25000, .max = 270000 },
159 .vco = { .min = 1750000, .max = 3500000},
160 .n = { .min = 1, .max = 4 },
161 .m = { .min = 104, .max = 138 },
162 .m1 = { .min = 17, .max = 23 },
163 .m2 = { .min = 5, .max = 11 },
164 .p = { .min = 10, .max = 30 },
165 .p1 = { .min = 1, .max = 3},
166 .p2 = { .dot_limit = 270000,
167 .p2_slow = 10,
168 .p2_fast = 10
169 },
170 };
171
172 static const intel_limit_t intel_limits_g4x_hdmi = {
173 .dot = { .min = 22000, .max = 400000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 16, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 5, .max = 80 },
180 .p1 = { .min = 1, .max = 8},
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 10, .p2_fast = 5 },
183 };
184
185 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
186 .dot = { .min = 20000, .max = 115000 },
187 .vco = { .min = 1750000, .max = 3500000 },
188 .n = { .min = 1, .max = 3 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 28, .max = 112 },
193 .p1 = { .min = 2, .max = 8 },
194 .p2 = { .dot_limit = 0,
195 .p2_slow = 14, .p2_fast = 14
196 },
197 };
198
199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
200 .dot = { .min = 80000, .max = 224000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 14, .max = 42 },
207 .p1 = { .min = 2, .max = 6 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 7, .p2_fast = 7
210 },
211 };
212
213 static const intel_limit_t intel_limits_pineview_sdvo = {
214 .dot = { .min = 20000, .max = 400000},
215 .vco = { .min = 1700000, .max = 3500000 },
216 /* Pineview's Ncounter is a ring counter */
217 .n = { .min = 3, .max = 6 },
218 .m = { .min = 2, .max = 256 },
219 /* Pineview only has one combined m divider, which we treat as m2. */
220 .m1 = { .min = 0, .max = 0 },
221 .m2 = { .min = 0, .max = 254 },
222 .p = { .min = 5, .max = 80 },
223 .p1 = { .min = 1, .max = 8 },
224 .p2 = { .dot_limit = 200000,
225 .p2_slow = 10, .p2_fast = 5 },
226 };
227
228 static const intel_limit_t intel_limits_pineview_lvds = {
229 .dot = { .min = 20000, .max = 400000 },
230 .vco = { .min = 1700000, .max = 3500000 },
231 .n = { .min = 3, .max = 6 },
232 .m = { .min = 2, .max = 256 },
233 .m1 = { .min = 0, .max = 0 },
234 .m2 = { .min = 0, .max = 254 },
235 .p = { .min = 7, .max = 112 },
236 .p1 = { .min = 1, .max = 8 },
237 .p2 = { .dot_limit = 112000,
238 .p2_slow = 14, .p2_fast = 14 },
239 };
240
241 /* Ironlake / Sandybridge
242 *
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
245 */
246 static const intel_limit_t intel_limits_ironlake_dac = {
247 .dot = { .min = 25000, .max = 350000 },
248 .vco = { .min = 1760000, .max = 3510000 },
249 .n = { .min = 1, .max = 5 },
250 .m = { .min = 79, .max = 127 },
251 .m1 = { .min = 12, .max = 22 },
252 .m2 = { .min = 5, .max = 9 },
253 .p = { .min = 5, .max = 80 },
254 .p1 = { .min = 1, .max = 8 },
255 .p2 = { .dot_limit = 225000,
256 .p2_slow = 10, .p2_fast = 5 },
257 };
258
259 static const intel_limit_t intel_limits_ironlake_single_lvds = {
260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 1760000, .max = 3510000 },
262 .n = { .min = 1, .max = 3 },
263 .m = { .min = 79, .max = 118 },
264 .m1 = { .min = 12, .max = 22 },
265 .m2 = { .min = 5, .max = 9 },
266 .p = { .min = 28, .max = 112 },
267 .p1 = { .min = 2, .max = 8 },
268 .p2 = { .dot_limit = 225000,
269 .p2_slow = 14, .p2_fast = 14 },
270 };
271
272 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 3 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 14, .max = 56 },
280 .p1 = { .min = 2, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 7, .p2_fast = 7 },
283 };
284
285 /* LVDS 100mhz refclk limits. */
286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 2 },
290 .m = { .min = 79, .max = 126 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
294 .p1 = { .min = 2, .max = 8 },
295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
297 };
298
299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 126 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 42 },
307 .p1 = { .min = 2, .max = 6 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
310 };
311
312 static const intel_limit_t intel_limits_vlv = {
313 /*
314 * These are the data rate limits (measured in fast clocks)
315 * since those are the strictest limits we have. The fast
316 * clock and actual rate limits are more relaxed, so checking
317 * them would make no difference.
318 */
319 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
320 .vco = { .min = 4000000, .max = 6000000 },
321 .n = { .min = 1, .max = 7 },
322 .m1 = { .min = 2, .max = 3 },
323 .m2 = { .min = 11, .max = 156 },
324 .p1 = { .min = 2, .max = 3 },
325 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
326 };
327
328 static void vlv_clock(int refclk, intel_clock_t *clock)
329 {
330 clock->m = clock->m1 * clock->m2;
331 clock->p = clock->p1 * clock->p2;
332 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
333 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
334 }
335
336 /**
337 * Returns whether any output on the specified pipe is of the specified type
338 */
339 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
340 {
341 struct drm_device *dev = crtc->dev;
342 struct intel_encoder *encoder;
343
344 for_each_encoder_on_crtc(dev, crtc, encoder)
345 if (encoder->type == type)
346 return true;
347
348 return false;
349 }
350
351 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
352 int refclk)
353 {
354 struct drm_device *dev = crtc->dev;
355 const intel_limit_t *limit;
356
357 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
358 if (intel_is_dual_link_lvds(dev)) {
359 if (refclk == 100000)
360 limit = &intel_limits_ironlake_dual_lvds_100m;
361 else
362 limit = &intel_limits_ironlake_dual_lvds;
363 } else {
364 if (refclk == 100000)
365 limit = &intel_limits_ironlake_single_lvds_100m;
366 else
367 limit = &intel_limits_ironlake_single_lvds;
368 }
369 } else
370 limit = &intel_limits_ironlake_dac;
371
372 return limit;
373 }
374
375 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
376 {
377 struct drm_device *dev = crtc->dev;
378 const intel_limit_t *limit;
379
380 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
381 if (intel_is_dual_link_lvds(dev))
382 limit = &intel_limits_g4x_dual_channel_lvds;
383 else
384 limit = &intel_limits_g4x_single_channel_lvds;
385 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
386 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
387 limit = &intel_limits_g4x_hdmi;
388 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
389 limit = &intel_limits_g4x_sdvo;
390 } else /* The option is for other outputs */
391 limit = &intel_limits_i9xx_sdvo;
392
393 return limit;
394 }
395
396 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
397 {
398 struct drm_device *dev = crtc->dev;
399 const intel_limit_t *limit;
400
401 if (HAS_PCH_SPLIT(dev))
402 limit = intel_ironlake_limit(crtc, refclk);
403 else if (IS_G4X(dev)) {
404 limit = intel_g4x_limit(crtc);
405 } else if (IS_PINEVIEW(dev)) {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
407 limit = &intel_limits_pineview_lvds;
408 else
409 limit = &intel_limits_pineview_sdvo;
410 } else if (IS_VALLEYVIEW(dev)) {
411 limit = &intel_limits_vlv;
412 } else if (!IS_GEN2(dev)) {
413 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
414 limit = &intel_limits_i9xx_lvds;
415 else
416 limit = &intel_limits_i9xx_sdvo;
417 } else {
418 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
419 limit = &intel_limits_i8xx_lvds;
420 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
421 limit = &intel_limits_i8xx_dvo;
422 else
423 limit = &intel_limits_i8xx_dac;
424 }
425 return limit;
426 }
427
428 /* m1 is reserved as 0 in Pineview, n is a ring counter */
429 static void pineview_clock(int refclk, intel_clock_t *clock)
430 {
431 clock->m = clock->m2 + 2;
432 clock->p = clock->p1 * clock->p2;
433 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
434 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
435 }
436
437 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
438 {
439 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
440 }
441
442 static void i9xx_clock(int refclk, intel_clock_t *clock)
443 {
444 clock->m = i9xx_dpll_compute_m(clock);
445 clock->p = clock->p1 * clock->p2;
446 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
447 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
448 }
449
450 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
451 /**
452 * Returns whether the given set of divisors are valid for a given refclk with
453 * the given connectors.
454 */
455
456 static bool intel_PLL_is_valid(struct drm_device *dev,
457 const intel_limit_t *limit,
458 const intel_clock_t *clock)
459 {
460 if (clock->n < limit->n.min || limit->n.max < clock->n)
461 INTELPllInvalid("n out of range\n");
462 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
463 INTELPllInvalid("p1 out of range\n");
464 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
465 INTELPllInvalid("m2 out of range\n");
466 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
467 INTELPllInvalid("m1 out of range\n");
468
469 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
470 if (clock->m1 <= clock->m2)
471 INTELPllInvalid("m1 <= m2\n");
472
473 if (!IS_VALLEYVIEW(dev)) {
474 if (clock->p < limit->p.min || limit->p.max < clock->p)
475 INTELPllInvalid("p out of range\n");
476 if (clock->m < limit->m.min || limit->m.max < clock->m)
477 INTELPllInvalid("m out of range\n");
478 }
479
480 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
481 INTELPllInvalid("vco out of range\n");
482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
484 */
485 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
486 INTELPllInvalid("dot out of range\n");
487
488 return true;
489 }
490
491 static bool
492 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
493 int target, int refclk, intel_clock_t *match_clock,
494 intel_clock_t *best_clock)
495 {
496 struct drm_device *dev = crtc->dev;
497 intel_clock_t clock;
498 int err = target;
499
500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
501 /*
502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
505 */
506 if (intel_is_dual_link_lvds(dev))
507 clock.p2 = limit->p2.p2_fast;
508 else
509 clock.p2 = limit->p2.p2_slow;
510 } else {
511 if (target < limit->p2.dot_limit)
512 clock.p2 = limit->p2.p2_slow;
513 else
514 clock.p2 = limit->p2.p2_fast;
515 }
516
517 memset(best_clock, 0, sizeof(*best_clock));
518
519 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
520 clock.m1++) {
521 for (clock.m2 = limit->m2.min;
522 clock.m2 <= limit->m2.max; clock.m2++) {
523 if (clock.m2 >= clock.m1)
524 break;
525 for (clock.n = limit->n.min;
526 clock.n <= limit->n.max; clock.n++) {
527 for (clock.p1 = limit->p1.min;
528 clock.p1 <= limit->p1.max; clock.p1++) {
529 int this_err;
530
531 i9xx_clock(refclk, &clock);
532 if (!intel_PLL_is_valid(dev, limit,
533 &clock))
534 continue;
535 if (match_clock &&
536 clock.p != match_clock->p)
537 continue;
538
539 this_err = abs(clock.dot - target);
540 if (this_err < err) {
541 *best_clock = clock;
542 err = this_err;
543 }
544 }
545 }
546 }
547 }
548
549 return (err != target);
550 }
551
552 static bool
553 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
554 int target, int refclk, intel_clock_t *match_clock,
555 intel_clock_t *best_clock)
556 {
557 struct drm_device *dev = crtc->dev;
558 intel_clock_t clock;
559 int err = target;
560
561 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
562 /*
563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
566 */
567 if (intel_is_dual_link_lvds(dev))
568 clock.p2 = limit->p2.p2_fast;
569 else
570 clock.p2 = limit->p2.p2_slow;
571 } else {
572 if (target < limit->p2.dot_limit)
573 clock.p2 = limit->p2.p2_slow;
574 else
575 clock.p2 = limit->p2.p2_fast;
576 }
577
578 memset(best_clock, 0, sizeof(*best_clock));
579
580 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
581 clock.m1++) {
582 for (clock.m2 = limit->m2.min;
583 clock.m2 <= limit->m2.max; clock.m2++) {
584 for (clock.n = limit->n.min;
585 clock.n <= limit->n.max; clock.n++) {
586 for (clock.p1 = limit->p1.min;
587 clock.p1 <= limit->p1.max; clock.p1++) {
588 int this_err;
589
590 pineview_clock(refclk, &clock);
591 if (!intel_PLL_is_valid(dev, limit,
592 &clock))
593 continue;
594 if (match_clock &&
595 clock.p != match_clock->p)
596 continue;
597
598 this_err = abs(clock.dot - target);
599 if (this_err < err) {
600 *best_clock = clock;
601 err = this_err;
602 }
603 }
604 }
605 }
606 }
607
608 return (err != target);
609 }
610
611 static bool
612 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
613 int target, int refclk, intel_clock_t *match_clock,
614 intel_clock_t *best_clock)
615 {
616 struct drm_device *dev = crtc->dev;
617 intel_clock_t clock;
618 int max_n;
619 bool found;
620 /* approximately equals target * 0.00585 */
621 int err_most = (target >> 8) + (target >> 9);
622 found = false;
623
624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
625 if (intel_is_dual_link_lvds(dev))
626 clock.p2 = limit->p2.p2_fast;
627 else
628 clock.p2 = limit->p2.p2_slow;
629 } else {
630 if (target < limit->p2.dot_limit)
631 clock.p2 = limit->p2.p2_slow;
632 else
633 clock.p2 = limit->p2.p2_fast;
634 }
635
636 memset(best_clock, 0, sizeof(*best_clock));
637 max_n = limit->n.max;
638 /* based on hardware requirement, prefer smaller n to precision */
639 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
640 /* based on hardware requirement, prefere larger m1,m2 */
641 for (clock.m1 = limit->m1.max;
642 clock.m1 >= limit->m1.min; clock.m1--) {
643 for (clock.m2 = limit->m2.max;
644 clock.m2 >= limit->m2.min; clock.m2--) {
645 for (clock.p1 = limit->p1.max;
646 clock.p1 >= limit->p1.min; clock.p1--) {
647 int this_err;
648
649 i9xx_clock(refclk, &clock);
650 if (!intel_PLL_is_valid(dev, limit,
651 &clock))
652 continue;
653
654 this_err = abs(clock.dot - target);
655 if (this_err < err_most) {
656 *best_clock = clock;
657 err_most = this_err;
658 max_n = clock.n;
659 found = true;
660 }
661 }
662 }
663 }
664 }
665 return found;
666 }
667
668 static bool
669 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *match_clock,
671 intel_clock_t *best_clock)
672 {
673 struct drm_device *dev = crtc->dev;
674 intel_clock_t clock;
675 unsigned int bestppm = 1000000;
676 /* min update 19.2 MHz */
677 int max_n = min(limit->n.max, refclk / 19200);
678 bool found = false;
679
680 target *= 5; /* fast clock */
681
682 memset(best_clock, 0, sizeof(*best_clock));
683
684 /* based on hardware requirement, prefer smaller n to precision */
685 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
686 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
687 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
688 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
689 clock.p = clock.p1 * clock.p2;
690 /* based on hardware requirement, prefer bigger m1,m2 values */
691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
692 unsigned int ppm, diff;
693
694 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
695 refclk * clock.m1);
696
697 vlv_clock(refclk, &clock);
698
699 if (!intel_PLL_is_valid(dev, limit,
700 &clock))
701 continue;
702
703 diff = abs(clock.dot - target);
704 ppm = div_u64(1000000ULL * diff, target);
705
706 if (ppm < 100 && clock.p > best_clock->p) {
707 bestppm = 0;
708 *best_clock = clock;
709 found = true;
710 }
711
712 if (bestppm >= 10 && ppm < bestppm - 10) {
713 bestppm = ppm;
714 *best_clock = clock;
715 found = true;
716 }
717 }
718 }
719 }
720 }
721
722 return found;
723 }
724
725 bool intel_crtc_active(struct drm_crtc *crtc)
726 {
727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
728
729 /* Be paranoid as we can arrive here with only partial
730 * state retrieved from the hardware during setup.
731 *
732 * We can ditch the adjusted_mode.crtc_clock check as soon
733 * as Haswell has gained clock readout/fastboot support.
734 *
735 * We can ditch the crtc->fb check as soon as we can
736 * properly reconstruct framebuffers.
737 */
738 return intel_crtc->active && crtc->fb &&
739 intel_crtc->config.adjusted_mode.crtc_clock;
740 }
741
742 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
743 enum pipe pipe)
744 {
745 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
747
748 return intel_crtc->config.cpu_transcoder;
749 }
750
751 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
752 {
753 struct drm_i915_private *dev_priv = dev->dev_private;
754 u32 frame, frame_reg = PIPEFRAME(pipe);
755
756 frame = I915_READ(frame_reg);
757
758 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
759 DRM_DEBUG_KMS("vblank wait timed out\n");
760 }
761
762 /**
763 * intel_wait_for_vblank - wait for vblank on a given pipe
764 * @dev: drm device
765 * @pipe: pipe to wait for
766 *
767 * Wait for vblank to occur on a given pipe. Needed for various bits of
768 * mode setting code.
769 */
770 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
771 {
772 struct drm_i915_private *dev_priv = dev->dev_private;
773 int pipestat_reg = PIPESTAT(pipe);
774
775 if (INTEL_INFO(dev)->gen >= 5) {
776 ironlake_wait_for_vblank(dev, pipe);
777 return;
778 }
779
780 /* Clear existing vblank status. Note this will clear any other
781 * sticky status fields as well.
782 *
783 * This races with i915_driver_irq_handler() with the result
784 * that either function could miss a vblank event. Here it is not
785 * fatal, as we will either wait upon the next vblank interrupt or
786 * timeout. Generally speaking intel_wait_for_vblank() is only
787 * called during modeset at which time the GPU should be idle and
788 * should *not* be performing page flips and thus not waiting on
789 * vblanks...
790 * Currently, the result of us stealing a vblank from the irq
791 * handler is that a single frame will be skipped during swapbuffers.
792 */
793 I915_WRITE(pipestat_reg,
794 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
795
796 /* Wait for vblank interrupt bit to set */
797 if (wait_for(I915_READ(pipestat_reg) &
798 PIPE_VBLANK_INTERRUPT_STATUS,
799 50))
800 DRM_DEBUG_KMS("vblank wait timed out\n");
801 }
802
803 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
804 {
805 struct drm_i915_private *dev_priv = dev->dev_private;
806 u32 reg = PIPEDSL(pipe);
807 u32 line1, line2;
808 u32 line_mask;
809
810 if (IS_GEN2(dev))
811 line_mask = DSL_LINEMASK_GEN2;
812 else
813 line_mask = DSL_LINEMASK_GEN3;
814
815 line1 = I915_READ(reg) & line_mask;
816 mdelay(5);
817 line2 = I915_READ(reg) & line_mask;
818
819 return line1 == line2;
820 }
821
822 /*
823 * intel_wait_for_pipe_off - wait for pipe to turn off
824 * @dev: drm device
825 * @pipe: pipe to wait for
826 *
827 * After disabling a pipe, we can't wait for vblank in the usual way,
828 * spinning on the vblank interrupt status bit, since we won't actually
829 * see an interrupt when the pipe is disabled.
830 *
831 * On Gen4 and above:
832 * wait for the pipe register state bit to turn off
833 *
834 * Otherwise:
835 * wait for the display line value to settle (it usually
836 * ends up stopping at the start of the next frame).
837 *
838 */
839 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
840 {
841 struct drm_i915_private *dev_priv = dev->dev_private;
842 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
843 pipe);
844
845 if (INTEL_INFO(dev)->gen >= 4) {
846 int reg = PIPECONF(cpu_transcoder);
847
848 /* Wait for the Pipe State to go off */
849 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
850 100))
851 WARN(1, "pipe_off wait timed out\n");
852 } else {
853 /* Wait for the display line to settle */
854 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
855 WARN(1, "pipe_off wait timed out\n");
856 }
857 }
858
859 /*
860 * ibx_digital_port_connected - is the specified port connected?
861 * @dev_priv: i915 private structure
862 * @port: the port to test
863 *
864 * Returns true if @port is connected, false otherwise.
865 */
866 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
867 struct intel_digital_port *port)
868 {
869 u32 bit;
870
871 if (HAS_PCH_IBX(dev_priv->dev)) {
872 switch(port->port) {
873 case PORT_B:
874 bit = SDE_PORTB_HOTPLUG;
875 break;
876 case PORT_C:
877 bit = SDE_PORTC_HOTPLUG;
878 break;
879 case PORT_D:
880 bit = SDE_PORTD_HOTPLUG;
881 break;
882 default:
883 return true;
884 }
885 } else {
886 switch(port->port) {
887 case PORT_B:
888 bit = SDE_PORTB_HOTPLUG_CPT;
889 break;
890 case PORT_C:
891 bit = SDE_PORTC_HOTPLUG_CPT;
892 break;
893 case PORT_D:
894 bit = SDE_PORTD_HOTPLUG_CPT;
895 break;
896 default:
897 return true;
898 }
899 }
900
901 return I915_READ(SDEISR) & bit;
902 }
903
904 static const char *state_string(bool enabled)
905 {
906 return enabled ? "on" : "off";
907 }
908
909 /* Only for pre-ILK configs */
910 void assert_pll(struct drm_i915_private *dev_priv,
911 enum pipe pipe, bool state)
912 {
913 int reg;
914 u32 val;
915 bool cur_state;
916
917 reg = DPLL(pipe);
918 val = I915_READ(reg);
919 cur_state = !!(val & DPLL_VCO_ENABLE);
920 WARN(cur_state != state,
921 "PLL state assertion failure (expected %s, current %s)\n",
922 state_string(state), state_string(cur_state));
923 }
924
925 /* XXX: the dsi pll is shared between MIPI DSI ports */
926 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
927 {
928 u32 val;
929 bool cur_state;
930
931 mutex_lock(&dev_priv->dpio_lock);
932 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
933 mutex_unlock(&dev_priv->dpio_lock);
934
935 cur_state = val & DSI_PLL_VCO_EN;
936 WARN(cur_state != state,
937 "DSI PLL state assertion failure (expected %s, current %s)\n",
938 state_string(state), state_string(cur_state));
939 }
940 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
941 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
942
943 struct intel_shared_dpll *
944 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
945 {
946 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
947
948 if (crtc->config.shared_dpll < 0)
949 return NULL;
950
951 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
952 }
953
954 /* For ILK+ */
955 void assert_shared_dpll(struct drm_i915_private *dev_priv,
956 struct intel_shared_dpll *pll,
957 bool state)
958 {
959 bool cur_state;
960 struct intel_dpll_hw_state hw_state;
961
962 if (HAS_PCH_LPT(dev_priv->dev)) {
963 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
964 return;
965 }
966
967 if (WARN (!pll,
968 "asserting DPLL %s with no DPLL\n", state_string(state)))
969 return;
970
971 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
972 WARN(cur_state != state,
973 "%s assertion failure (expected %s, current %s)\n",
974 pll->name, state_string(state), state_string(cur_state));
975 }
976
977 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
978 enum pipe pipe, bool state)
979 {
980 int reg;
981 u32 val;
982 bool cur_state;
983 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
984 pipe);
985
986 if (HAS_DDI(dev_priv->dev)) {
987 /* DDI does not have a specific FDI_TX register */
988 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
989 val = I915_READ(reg);
990 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
991 } else {
992 reg = FDI_TX_CTL(pipe);
993 val = I915_READ(reg);
994 cur_state = !!(val & FDI_TX_ENABLE);
995 }
996 WARN(cur_state != state,
997 "FDI TX state assertion failure (expected %s, current %s)\n",
998 state_string(state), state_string(cur_state));
999 }
1000 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1001 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1002
1003 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1004 enum pipe pipe, bool state)
1005 {
1006 int reg;
1007 u32 val;
1008 bool cur_state;
1009
1010 reg = FDI_RX_CTL(pipe);
1011 val = I915_READ(reg);
1012 cur_state = !!(val & FDI_RX_ENABLE);
1013 WARN(cur_state != state,
1014 "FDI RX state assertion failure (expected %s, current %s)\n",
1015 state_string(state), state_string(cur_state));
1016 }
1017 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1018 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1019
1020 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1021 enum pipe pipe)
1022 {
1023 int reg;
1024 u32 val;
1025
1026 /* ILK FDI PLL is always enabled */
1027 if (dev_priv->info->gen == 5)
1028 return;
1029
1030 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1031 if (HAS_DDI(dev_priv->dev))
1032 return;
1033
1034 reg = FDI_TX_CTL(pipe);
1035 val = I915_READ(reg);
1036 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1037 }
1038
1039 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1040 enum pipe pipe, bool state)
1041 {
1042 int reg;
1043 u32 val;
1044 bool cur_state;
1045
1046 reg = FDI_RX_CTL(pipe);
1047 val = I915_READ(reg);
1048 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1049 WARN(cur_state != state,
1050 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1051 state_string(state), state_string(cur_state));
1052 }
1053
1054 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1055 enum pipe pipe)
1056 {
1057 int pp_reg, lvds_reg;
1058 u32 val;
1059 enum pipe panel_pipe = PIPE_A;
1060 bool locked = true;
1061
1062 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1063 pp_reg = PCH_PP_CONTROL;
1064 lvds_reg = PCH_LVDS;
1065 } else {
1066 pp_reg = PP_CONTROL;
1067 lvds_reg = LVDS;
1068 }
1069
1070 val = I915_READ(pp_reg);
1071 if (!(val & PANEL_POWER_ON) ||
1072 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1073 locked = false;
1074
1075 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1076 panel_pipe = PIPE_B;
1077
1078 WARN(panel_pipe == pipe && locked,
1079 "panel assertion failure, pipe %c regs locked\n",
1080 pipe_name(pipe));
1081 }
1082
1083 static void assert_cursor(struct drm_i915_private *dev_priv,
1084 enum pipe pipe, bool state)
1085 {
1086 struct drm_device *dev = dev_priv->dev;
1087 bool cur_state;
1088
1089 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1090 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1091 else if (IS_845G(dev) || IS_I865G(dev))
1092 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1093 else
1094 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1095
1096 WARN(cur_state != state,
1097 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1098 pipe_name(pipe), state_string(state), state_string(cur_state));
1099 }
1100 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1101 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1102
1103 void assert_pipe(struct drm_i915_private *dev_priv,
1104 enum pipe pipe, bool state)
1105 {
1106 int reg;
1107 u32 val;
1108 bool cur_state;
1109 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1110 pipe);
1111
1112 /* if we need the pipe A quirk it must be always on */
1113 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1114 state = true;
1115
1116 if (!intel_display_power_enabled(dev_priv->dev,
1117 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1118 cur_state = false;
1119 } else {
1120 reg = PIPECONF(cpu_transcoder);
1121 val = I915_READ(reg);
1122 cur_state = !!(val & PIPECONF_ENABLE);
1123 }
1124
1125 WARN(cur_state != state,
1126 "pipe %c assertion failure (expected %s, current %s)\n",
1127 pipe_name(pipe), state_string(state), state_string(cur_state));
1128 }
1129
1130 static void assert_plane(struct drm_i915_private *dev_priv,
1131 enum plane plane, bool state)
1132 {
1133 int reg;
1134 u32 val;
1135 bool cur_state;
1136
1137 reg = DSPCNTR(plane);
1138 val = I915_READ(reg);
1139 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1140 WARN(cur_state != state,
1141 "plane %c assertion failure (expected %s, current %s)\n",
1142 plane_name(plane), state_string(state), state_string(cur_state));
1143 }
1144
1145 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1146 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1147
1148 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1149 enum pipe pipe)
1150 {
1151 struct drm_device *dev = dev_priv->dev;
1152 int reg, i;
1153 u32 val;
1154 int cur_pipe;
1155
1156 /* Primary planes are fixed to pipes on gen4+ */
1157 if (INTEL_INFO(dev)->gen >= 4) {
1158 reg = DSPCNTR(pipe);
1159 val = I915_READ(reg);
1160 WARN((val & DISPLAY_PLANE_ENABLE),
1161 "plane %c assertion failure, should be disabled but not\n",
1162 plane_name(pipe));
1163 return;
1164 }
1165
1166 /* Need to check both planes against the pipe */
1167 for_each_pipe(i) {
1168 reg = DSPCNTR(i);
1169 val = I915_READ(reg);
1170 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1171 DISPPLANE_SEL_PIPE_SHIFT;
1172 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1173 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1174 plane_name(i), pipe_name(pipe));
1175 }
1176 }
1177
1178 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1179 enum pipe pipe)
1180 {
1181 struct drm_device *dev = dev_priv->dev;
1182 int reg, i;
1183 u32 val;
1184
1185 if (IS_VALLEYVIEW(dev)) {
1186 for (i = 0; i < dev_priv->num_plane; i++) {
1187 reg = SPCNTR(pipe, i);
1188 val = I915_READ(reg);
1189 WARN((val & SP_ENABLE),
1190 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1191 sprite_name(pipe, i), pipe_name(pipe));
1192 }
1193 } else if (INTEL_INFO(dev)->gen >= 7) {
1194 reg = SPRCTL(pipe);
1195 val = I915_READ(reg);
1196 WARN((val & SPRITE_ENABLE),
1197 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1198 plane_name(pipe), pipe_name(pipe));
1199 } else if (INTEL_INFO(dev)->gen >= 5) {
1200 reg = DVSCNTR(pipe);
1201 val = I915_READ(reg);
1202 WARN((val & DVS_ENABLE),
1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204 plane_name(pipe), pipe_name(pipe));
1205 }
1206 }
1207
1208 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1209 {
1210 u32 val;
1211 bool enabled;
1212
1213 if (HAS_PCH_LPT(dev_priv->dev)) {
1214 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1215 return;
1216 }
1217
1218 val = I915_READ(PCH_DREF_CONTROL);
1219 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1220 DREF_SUPERSPREAD_SOURCE_MASK));
1221 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1222 }
1223
1224 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1225 enum pipe pipe)
1226 {
1227 int reg;
1228 u32 val;
1229 bool enabled;
1230
1231 reg = PCH_TRANSCONF(pipe);
1232 val = I915_READ(reg);
1233 enabled = !!(val & TRANS_ENABLE);
1234 WARN(enabled,
1235 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1236 pipe_name(pipe));
1237 }
1238
1239 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, u32 port_sel, u32 val)
1241 {
1242 if ((val & DP_PORT_EN) == 0)
1243 return false;
1244
1245 if (HAS_PCH_CPT(dev_priv->dev)) {
1246 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1247 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1248 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1249 return false;
1250 } else {
1251 if ((val & DP_PIPE_MASK) != (pipe << 30))
1252 return false;
1253 }
1254 return true;
1255 }
1256
1257 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1258 enum pipe pipe, u32 val)
1259 {
1260 if ((val & SDVO_ENABLE) == 0)
1261 return false;
1262
1263 if (HAS_PCH_CPT(dev_priv->dev)) {
1264 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1265 return false;
1266 } else {
1267 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1268 return false;
1269 }
1270 return true;
1271 }
1272
1273 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1274 enum pipe pipe, u32 val)
1275 {
1276 if ((val & LVDS_PORT_EN) == 0)
1277 return false;
1278
1279 if (HAS_PCH_CPT(dev_priv->dev)) {
1280 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1281 return false;
1282 } else {
1283 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1284 return false;
1285 }
1286 return true;
1287 }
1288
1289 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1290 enum pipe pipe, u32 val)
1291 {
1292 if ((val & ADPA_DAC_ENABLE) == 0)
1293 return false;
1294 if (HAS_PCH_CPT(dev_priv->dev)) {
1295 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1296 return false;
1297 } else {
1298 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1299 return false;
1300 }
1301 return true;
1302 }
1303
1304 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1305 enum pipe pipe, int reg, u32 port_sel)
1306 {
1307 u32 val = I915_READ(reg);
1308 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1309 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1310 reg, pipe_name(pipe));
1311
1312 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1313 && (val & DP_PIPEB_SELECT),
1314 "IBX PCH dp port still using transcoder B\n");
1315 }
1316
1317 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1318 enum pipe pipe, int reg)
1319 {
1320 u32 val = I915_READ(reg);
1321 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1322 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1323 reg, pipe_name(pipe));
1324
1325 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1326 && (val & SDVO_PIPE_B_SELECT),
1327 "IBX PCH hdmi port still using transcoder B\n");
1328 }
1329
1330 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1331 enum pipe pipe)
1332 {
1333 int reg;
1334 u32 val;
1335
1336 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1337 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1338 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1339
1340 reg = PCH_ADPA;
1341 val = I915_READ(reg);
1342 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1343 "PCH VGA enabled on transcoder %c, should be disabled\n",
1344 pipe_name(pipe));
1345
1346 reg = PCH_LVDS;
1347 val = I915_READ(reg);
1348 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1349 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1350 pipe_name(pipe));
1351
1352 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1353 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1354 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1355 }
1356
1357 static void intel_init_dpio(struct drm_device *dev)
1358 {
1359 struct drm_i915_private *dev_priv = dev->dev_private;
1360
1361 if (!IS_VALLEYVIEW(dev))
1362 return;
1363
1364 /*
1365 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1366 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1367 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1368 * b. The other bits such as sfr settings / modesel may all be set
1369 * to 0.
1370 *
1371 * This should only be done on init and resume from S3 with both
1372 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1373 */
1374 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1375 }
1376
1377 static void vlv_enable_pll(struct intel_crtc *crtc)
1378 {
1379 struct drm_device *dev = crtc->base.dev;
1380 struct drm_i915_private *dev_priv = dev->dev_private;
1381 int reg = DPLL(crtc->pipe);
1382 u32 dpll = crtc->config.dpll_hw_state.dpll;
1383
1384 assert_pipe_disabled(dev_priv, crtc->pipe);
1385
1386 /* No really, not for ILK+ */
1387 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1388
1389 /* PLL is protected by panel, make sure we can write it */
1390 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1391 assert_panel_unlocked(dev_priv, crtc->pipe);
1392
1393 I915_WRITE(reg, dpll);
1394 POSTING_READ(reg);
1395 udelay(150);
1396
1397 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1398 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1399
1400 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1401 POSTING_READ(DPLL_MD(crtc->pipe));
1402
1403 /* We do this three times for luck */
1404 I915_WRITE(reg, dpll);
1405 POSTING_READ(reg);
1406 udelay(150); /* wait for warmup */
1407 I915_WRITE(reg, dpll);
1408 POSTING_READ(reg);
1409 udelay(150); /* wait for warmup */
1410 I915_WRITE(reg, dpll);
1411 POSTING_READ(reg);
1412 udelay(150); /* wait for warmup */
1413 }
1414
1415 static void i9xx_enable_pll(struct intel_crtc *crtc)
1416 {
1417 struct drm_device *dev = crtc->base.dev;
1418 struct drm_i915_private *dev_priv = dev->dev_private;
1419 int reg = DPLL(crtc->pipe);
1420 u32 dpll = crtc->config.dpll_hw_state.dpll;
1421
1422 assert_pipe_disabled(dev_priv, crtc->pipe);
1423
1424 /* No really, not for ILK+ */
1425 BUG_ON(dev_priv->info->gen >= 5);
1426
1427 /* PLL is protected by panel, make sure we can write it */
1428 if (IS_MOBILE(dev) && !IS_I830(dev))
1429 assert_panel_unlocked(dev_priv, crtc->pipe);
1430
1431 I915_WRITE(reg, dpll);
1432
1433 /* Wait for the clocks to stabilize. */
1434 POSTING_READ(reg);
1435 udelay(150);
1436
1437 if (INTEL_INFO(dev)->gen >= 4) {
1438 I915_WRITE(DPLL_MD(crtc->pipe),
1439 crtc->config.dpll_hw_state.dpll_md);
1440 } else {
1441 /* The pixel multiplier can only be updated once the
1442 * DPLL is enabled and the clocks are stable.
1443 *
1444 * So write it again.
1445 */
1446 I915_WRITE(reg, dpll);
1447 }
1448
1449 /* We do this three times for luck */
1450 I915_WRITE(reg, dpll);
1451 POSTING_READ(reg);
1452 udelay(150); /* wait for warmup */
1453 I915_WRITE(reg, dpll);
1454 POSTING_READ(reg);
1455 udelay(150); /* wait for warmup */
1456 I915_WRITE(reg, dpll);
1457 POSTING_READ(reg);
1458 udelay(150); /* wait for warmup */
1459 }
1460
1461 /**
1462 * i9xx_disable_pll - disable a PLL
1463 * @dev_priv: i915 private structure
1464 * @pipe: pipe PLL to disable
1465 *
1466 * Disable the PLL for @pipe, making sure the pipe is off first.
1467 *
1468 * Note! This is for pre-ILK only.
1469 */
1470 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1471 {
1472 /* Don't disable pipe A or pipe A PLLs if needed */
1473 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1474 return;
1475
1476 /* Make sure the pipe isn't still relying on us */
1477 assert_pipe_disabled(dev_priv, pipe);
1478
1479 I915_WRITE(DPLL(pipe), 0);
1480 POSTING_READ(DPLL(pipe));
1481 }
1482
1483 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1484 {
1485 u32 val = 0;
1486
1487 /* Make sure the pipe isn't still relying on us */
1488 assert_pipe_disabled(dev_priv, pipe);
1489
1490 /* Leave integrated clock source enabled */
1491 if (pipe == PIPE_B)
1492 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1493 I915_WRITE(DPLL(pipe), val);
1494 POSTING_READ(DPLL(pipe));
1495 }
1496
1497 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1498 {
1499 u32 port_mask;
1500
1501 if (!port)
1502 port_mask = DPLL_PORTB_READY_MASK;
1503 else
1504 port_mask = DPLL_PORTC_READY_MASK;
1505
1506 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1507 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1508 'B' + port, I915_READ(DPLL(0)));
1509 }
1510
1511 /**
1512 * ironlake_enable_shared_dpll - enable PCH PLL
1513 * @dev_priv: i915 private structure
1514 * @pipe: pipe PLL to enable
1515 *
1516 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1517 * drives the transcoder clock.
1518 */
1519 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1520 {
1521 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1522 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1523
1524 /* PCH PLLs only available on ILK, SNB and IVB */
1525 BUG_ON(dev_priv->info->gen < 5);
1526 if (WARN_ON(pll == NULL))
1527 return;
1528
1529 if (WARN_ON(pll->refcount == 0))
1530 return;
1531
1532 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1533 pll->name, pll->active, pll->on,
1534 crtc->base.base.id);
1535
1536 if (pll->active++) {
1537 WARN_ON(!pll->on);
1538 assert_shared_dpll_enabled(dev_priv, pll);
1539 return;
1540 }
1541 WARN_ON(pll->on);
1542
1543 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1544 pll->enable(dev_priv, pll);
1545 pll->on = true;
1546 }
1547
1548 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1549 {
1550 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1551 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1552
1553 /* PCH only available on ILK+ */
1554 BUG_ON(dev_priv->info->gen < 5);
1555 if (WARN_ON(pll == NULL))
1556 return;
1557
1558 if (WARN_ON(pll->refcount == 0))
1559 return;
1560
1561 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1562 pll->name, pll->active, pll->on,
1563 crtc->base.base.id);
1564
1565 if (WARN_ON(pll->active == 0)) {
1566 assert_shared_dpll_disabled(dev_priv, pll);
1567 return;
1568 }
1569
1570 assert_shared_dpll_enabled(dev_priv, pll);
1571 WARN_ON(!pll->on);
1572 if (--pll->active)
1573 return;
1574
1575 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1576 pll->disable(dev_priv, pll);
1577 pll->on = false;
1578 }
1579
1580 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1581 enum pipe pipe)
1582 {
1583 struct drm_device *dev = dev_priv->dev;
1584 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1586 uint32_t reg, val, pipeconf_val;
1587
1588 /* PCH only available on ILK+ */
1589 BUG_ON(dev_priv->info->gen < 5);
1590
1591 /* Make sure PCH DPLL is enabled */
1592 assert_shared_dpll_enabled(dev_priv,
1593 intel_crtc_to_shared_dpll(intel_crtc));
1594
1595 /* FDI must be feeding us bits for PCH ports */
1596 assert_fdi_tx_enabled(dev_priv, pipe);
1597 assert_fdi_rx_enabled(dev_priv, pipe);
1598
1599 if (HAS_PCH_CPT(dev)) {
1600 /* Workaround: Set the timing override bit before enabling the
1601 * pch transcoder. */
1602 reg = TRANS_CHICKEN2(pipe);
1603 val = I915_READ(reg);
1604 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1605 I915_WRITE(reg, val);
1606 }
1607
1608 reg = PCH_TRANSCONF(pipe);
1609 val = I915_READ(reg);
1610 pipeconf_val = I915_READ(PIPECONF(pipe));
1611
1612 if (HAS_PCH_IBX(dev_priv->dev)) {
1613 /*
1614 * make the BPC in transcoder be consistent with
1615 * that in pipeconf reg.
1616 */
1617 val &= ~PIPECONF_BPC_MASK;
1618 val |= pipeconf_val & PIPECONF_BPC_MASK;
1619 }
1620
1621 val &= ~TRANS_INTERLACE_MASK;
1622 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1623 if (HAS_PCH_IBX(dev_priv->dev) &&
1624 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1625 val |= TRANS_LEGACY_INTERLACED_ILK;
1626 else
1627 val |= TRANS_INTERLACED;
1628 else
1629 val |= TRANS_PROGRESSIVE;
1630
1631 I915_WRITE(reg, val | TRANS_ENABLE);
1632 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1633 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1634 }
1635
1636 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1637 enum transcoder cpu_transcoder)
1638 {
1639 u32 val, pipeconf_val;
1640
1641 /* PCH only available on ILK+ */
1642 BUG_ON(dev_priv->info->gen < 5);
1643
1644 /* FDI must be feeding us bits for PCH ports */
1645 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1646 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1647
1648 /* Workaround: set timing override bit. */
1649 val = I915_READ(_TRANSA_CHICKEN2);
1650 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1651 I915_WRITE(_TRANSA_CHICKEN2, val);
1652
1653 val = TRANS_ENABLE;
1654 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1655
1656 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1657 PIPECONF_INTERLACED_ILK)
1658 val |= TRANS_INTERLACED;
1659 else
1660 val |= TRANS_PROGRESSIVE;
1661
1662 I915_WRITE(LPT_TRANSCONF, val);
1663 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1664 DRM_ERROR("Failed to enable PCH transcoder\n");
1665 }
1666
1667 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1668 enum pipe pipe)
1669 {
1670 struct drm_device *dev = dev_priv->dev;
1671 uint32_t reg, val;
1672
1673 /* FDI relies on the transcoder */
1674 assert_fdi_tx_disabled(dev_priv, pipe);
1675 assert_fdi_rx_disabled(dev_priv, pipe);
1676
1677 /* Ports must be off as well */
1678 assert_pch_ports_disabled(dev_priv, pipe);
1679
1680 reg = PCH_TRANSCONF(pipe);
1681 val = I915_READ(reg);
1682 val &= ~TRANS_ENABLE;
1683 I915_WRITE(reg, val);
1684 /* wait for PCH transcoder off, transcoder state */
1685 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1686 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1687
1688 if (!HAS_PCH_IBX(dev)) {
1689 /* Workaround: Clear the timing override chicken bit again. */
1690 reg = TRANS_CHICKEN2(pipe);
1691 val = I915_READ(reg);
1692 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1693 I915_WRITE(reg, val);
1694 }
1695 }
1696
1697 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1698 {
1699 u32 val;
1700
1701 val = I915_READ(LPT_TRANSCONF);
1702 val &= ~TRANS_ENABLE;
1703 I915_WRITE(LPT_TRANSCONF, val);
1704 /* wait for PCH transcoder off, transcoder state */
1705 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1706 DRM_ERROR("Failed to disable PCH transcoder\n");
1707
1708 /* Workaround: clear timing override bit. */
1709 val = I915_READ(_TRANSA_CHICKEN2);
1710 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1711 I915_WRITE(_TRANSA_CHICKEN2, val);
1712 }
1713
1714 /**
1715 * intel_enable_pipe - enable a pipe, asserting requirements
1716 * @dev_priv: i915 private structure
1717 * @pipe: pipe to enable
1718 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1719 *
1720 * Enable @pipe, making sure that various hardware specific requirements
1721 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1722 *
1723 * @pipe should be %PIPE_A or %PIPE_B.
1724 *
1725 * Will wait until the pipe is actually running (i.e. first vblank) before
1726 * returning.
1727 */
1728 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1729 bool pch_port, bool dsi)
1730 {
1731 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1732 pipe);
1733 enum pipe pch_transcoder;
1734 int reg;
1735 u32 val;
1736
1737 assert_planes_disabled(dev_priv, pipe);
1738 assert_cursor_disabled(dev_priv, pipe);
1739 assert_sprites_disabled(dev_priv, pipe);
1740
1741 if (HAS_PCH_LPT(dev_priv->dev))
1742 pch_transcoder = TRANSCODER_A;
1743 else
1744 pch_transcoder = pipe;
1745
1746 /*
1747 * A pipe without a PLL won't actually be able to drive bits from
1748 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1749 * need the check.
1750 */
1751 if (!HAS_PCH_SPLIT(dev_priv->dev))
1752 if (dsi)
1753 assert_dsi_pll_enabled(dev_priv);
1754 else
1755 assert_pll_enabled(dev_priv, pipe);
1756 else {
1757 if (pch_port) {
1758 /* if driving the PCH, we need FDI enabled */
1759 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1760 assert_fdi_tx_pll_enabled(dev_priv,
1761 (enum pipe) cpu_transcoder);
1762 }
1763 /* FIXME: assert CPU port conditions for SNB+ */
1764 }
1765
1766 reg = PIPECONF(cpu_transcoder);
1767 val = I915_READ(reg);
1768 if (val & PIPECONF_ENABLE)
1769 return;
1770
1771 I915_WRITE(reg, val | PIPECONF_ENABLE);
1772 intel_wait_for_vblank(dev_priv->dev, pipe);
1773 }
1774
1775 /**
1776 * intel_disable_pipe - disable a pipe, asserting requirements
1777 * @dev_priv: i915 private structure
1778 * @pipe: pipe to disable
1779 *
1780 * Disable @pipe, making sure that various hardware specific requirements
1781 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1782 *
1783 * @pipe should be %PIPE_A or %PIPE_B.
1784 *
1785 * Will wait until the pipe has shut down before returning.
1786 */
1787 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1788 enum pipe pipe)
1789 {
1790 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1791 pipe);
1792 int reg;
1793 u32 val;
1794
1795 /*
1796 * Make sure planes won't keep trying to pump pixels to us,
1797 * or we might hang the display.
1798 */
1799 assert_planes_disabled(dev_priv, pipe);
1800 assert_cursor_disabled(dev_priv, pipe);
1801 assert_sprites_disabled(dev_priv, pipe);
1802
1803 /* Don't disable pipe A or pipe A PLLs if needed */
1804 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1805 return;
1806
1807 reg = PIPECONF(cpu_transcoder);
1808 val = I915_READ(reg);
1809 if ((val & PIPECONF_ENABLE) == 0)
1810 return;
1811
1812 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1813 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1814 }
1815
1816 /*
1817 * Plane regs are double buffered, going from enabled->disabled needs a
1818 * trigger in order to latch. The display address reg provides this.
1819 */
1820 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1821 enum plane plane)
1822 {
1823 u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1824
1825 I915_WRITE(reg, I915_READ(reg));
1826 POSTING_READ(reg);
1827 }
1828
1829 /**
1830 * intel_enable_primary_plane - enable the primary plane on a given pipe
1831 * @dev_priv: i915 private structure
1832 * @plane: plane to enable
1833 * @pipe: pipe being fed
1834 *
1835 * Enable @plane on @pipe, making sure that @pipe is running first.
1836 */
1837 static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1838 enum plane plane, enum pipe pipe)
1839 {
1840 struct intel_crtc *intel_crtc =
1841 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1842 int reg;
1843 u32 val;
1844
1845 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1846 assert_pipe_enabled(dev_priv, pipe);
1847
1848 WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1849
1850 intel_crtc->primary_enabled = true;
1851
1852 reg = DSPCNTR(plane);
1853 val = I915_READ(reg);
1854 if (val & DISPLAY_PLANE_ENABLE)
1855 return;
1856
1857 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1858 intel_flush_primary_plane(dev_priv, plane);
1859 intel_wait_for_vblank(dev_priv->dev, pipe);
1860 }
1861
1862 /**
1863 * intel_disable_primary_plane - disable the primary plane
1864 * @dev_priv: i915 private structure
1865 * @plane: plane to disable
1866 * @pipe: pipe consuming the data
1867 *
1868 * Disable @plane; should be an independent operation.
1869 */
1870 static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1871 enum plane plane, enum pipe pipe)
1872 {
1873 struct intel_crtc *intel_crtc =
1874 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1875 int reg;
1876 u32 val;
1877
1878 WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1879
1880 intel_crtc->primary_enabled = false;
1881
1882 reg = DSPCNTR(plane);
1883 val = I915_READ(reg);
1884 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1885 return;
1886
1887 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1888 intel_flush_primary_plane(dev_priv, plane);
1889 intel_wait_for_vblank(dev_priv->dev, pipe);
1890 }
1891
1892 static bool need_vtd_wa(struct drm_device *dev)
1893 {
1894 #ifdef CONFIG_INTEL_IOMMU
1895 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1896 return true;
1897 #endif
1898 return false;
1899 }
1900
1901 int
1902 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1903 struct drm_i915_gem_object *obj,
1904 struct intel_ring_buffer *pipelined)
1905 {
1906 struct drm_i915_private *dev_priv = dev->dev_private;
1907 u32 alignment;
1908 int ret;
1909
1910 switch (obj->tiling_mode) {
1911 case I915_TILING_NONE:
1912 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1913 alignment = 128 * 1024;
1914 else if (INTEL_INFO(dev)->gen >= 4)
1915 alignment = 4 * 1024;
1916 else
1917 alignment = 64 * 1024;
1918 break;
1919 case I915_TILING_X:
1920 /* pin() will align the object as required by fence */
1921 alignment = 0;
1922 break;
1923 case I915_TILING_Y:
1924 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1925 return -EINVAL;
1926 default:
1927 BUG();
1928 }
1929
1930 /* Note that the w/a also requires 64 PTE of padding following the
1931 * bo. We currently fill all unused PTE with the shadow page and so
1932 * we should always have valid PTE following the scanout preventing
1933 * the VT-d warning.
1934 */
1935 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1936 alignment = 256 * 1024;
1937
1938 dev_priv->mm.interruptible = false;
1939 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1940 if (ret)
1941 goto err_interruptible;
1942
1943 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1944 * fence, whereas 965+ only requires a fence if using
1945 * framebuffer compression. For simplicity, we always install
1946 * a fence as the cost is not that onerous.
1947 */
1948 ret = i915_gem_object_get_fence(obj);
1949 if (ret)
1950 goto err_unpin;
1951
1952 i915_gem_object_pin_fence(obj);
1953
1954 dev_priv->mm.interruptible = true;
1955 return 0;
1956
1957 err_unpin:
1958 i915_gem_object_unpin_from_display_plane(obj);
1959 err_interruptible:
1960 dev_priv->mm.interruptible = true;
1961 return ret;
1962 }
1963
1964 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1965 {
1966 i915_gem_object_unpin_fence(obj);
1967 i915_gem_object_unpin_from_display_plane(obj);
1968 }
1969
1970 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1971 * is assumed to be a power-of-two. */
1972 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1973 unsigned int tiling_mode,
1974 unsigned int cpp,
1975 unsigned int pitch)
1976 {
1977 if (tiling_mode != I915_TILING_NONE) {
1978 unsigned int tile_rows, tiles;
1979
1980 tile_rows = *y / 8;
1981 *y %= 8;
1982
1983 tiles = *x / (512/cpp);
1984 *x %= 512/cpp;
1985
1986 return tile_rows * pitch * 8 + tiles * 4096;
1987 } else {
1988 unsigned int offset;
1989
1990 offset = *y * pitch + *x * cpp;
1991 *y = 0;
1992 *x = (offset & 4095) / cpp;
1993 return offset & -4096;
1994 }
1995 }
1996
1997 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1998 int x, int y)
1999 {
2000 struct drm_device *dev = crtc->dev;
2001 struct drm_i915_private *dev_priv = dev->dev_private;
2002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2003 struct intel_framebuffer *intel_fb;
2004 struct drm_i915_gem_object *obj;
2005 int plane = intel_crtc->plane;
2006 unsigned long linear_offset;
2007 u32 dspcntr;
2008 u32 reg;
2009
2010 switch (plane) {
2011 case 0:
2012 case 1:
2013 break;
2014 default:
2015 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2016 return -EINVAL;
2017 }
2018
2019 intel_fb = to_intel_framebuffer(fb);
2020 obj = intel_fb->obj;
2021
2022 reg = DSPCNTR(plane);
2023 dspcntr = I915_READ(reg);
2024 /* Mask out pixel format bits in case we change it */
2025 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2026 switch (fb->pixel_format) {
2027 case DRM_FORMAT_C8:
2028 dspcntr |= DISPPLANE_8BPP;
2029 break;
2030 case DRM_FORMAT_XRGB1555:
2031 case DRM_FORMAT_ARGB1555:
2032 dspcntr |= DISPPLANE_BGRX555;
2033 break;
2034 case DRM_FORMAT_RGB565:
2035 dspcntr |= DISPPLANE_BGRX565;
2036 break;
2037 case DRM_FORMAT_XRGB8888:
2038 case DRM_FORMAT_ARGB8888:
2039 dspcntr |= DISPPLANE_BGRX888;
2040 break;
2041 case DRM_FORMAT_XBGR8888:
2042 case DRM_FORMAT_ABGR8888:
2043 dspcntr |= DISPPLANE_RGBX888;
2044 break;
2045 case DRM_FORMAT_XRGB2101010:
2046 case DRM_FORMAT_ARGB2101010:
2047 dspcntr |= DISPPLANE_BGRX101010;
2048 break;
2049 case DRM_FORMAT_XBGR2101010:
2050 case DRM_FORMAT_ABGR2101010:
2051 dspcntr |= DISPPLANE_RGBX101010;
2052 break;
2053 default:
2054 BUG();
2055 }
2056
2057 if (INTEL_INFO(dev)->gen >= 4) {
2058 if (obj->tiling_mode != I915_TILING_NONE)
2059 dspcntr |= DISPPLANE_TILED;
2060 else
2061 dspcntr &= ~DISPPLANE_TILED;
2062 }
2063
2064 if (IS_G4X(dev))
2065 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2066
2067 I915_WRITE(reg, dspcntr);
2068
2069 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2070
2071 if (INTEL_INFO(dev)->gen >= 4) {
2072 intel_crtc->dspaddr_offset =
2073 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2074 fb->bits_per_pixel / 8,
2075 fb->pitches[0]);
2076 linear_offset -= intel_crtc->dspaddr_offset;
2077 } else {
2078 intel_crtc->dspaddr_offset = linear_offset;
2079 }
2080
2081 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2082 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2083 fb->pitches[0]);
2084 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2085 if (INTEL_INFO(dev)->gen >= 4) {
2086 I915_MODIFY_DISPBASE(DSPSURF(plane),
2087 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2088 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2089 I915_WRITE(DSPLINOFF(plane), linear_offset);
2090 } else
2091 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2092 POSTING_READ(reg);
2093
2094 return 0;
2095 }
2096
2097 static int ironlake_update_plane(struct drm_crtc *crtc,
2098 struct drm_framebuffer *fb, int x, int y)
2099 {
2100 struct drm_device *dev = crtc->dev;
2101 struct drm_i915_private *dev_priv = dev->dev_private;
2102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2103 struct intel_framebuffer *intel_fb;
2104 struct drm_i915_gem_object *obj;
2105 int plane = intel_crtc->plane;
2106 unsigned long linear_offset;
2107 u32 dspcntr;
2108 u32 reg;
2109
2110 switch (plane) {
2111 case 0:
2112 case 1:
2113 case 2:
2114 break;
2115 default:
2116 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2117 return -EINVAL;
2118 }
2119
2120 intel_fb = to_intel_framebuffer(fb);
2121 obj = intel_fb->obj;
2122
2123 reg = DSPCNTR(plane);
2124 dspcntr = I915_READ(reg);
2125 /* Mask out pixel format bits in case we change it */
2126 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2127 switch (fb->pixel_format) {
2128 case DRM_FORMAT_C8:
2129 dspcntr |= DISPPLANE_8BPP;
2130 break;
2131 case DRM_FORMAT_RGB565:
2132 dspcntr |= DISPPLANE_BGRX565;
2133 break;
2134 case DRM_FORMAT_XRGB8888:
2135 case DRM_FORMAT_ARGB8888:
2136 dspcntr |= DISPPLANE_BGRX888;
2137 break;
2138 case DRM_FORMAT_XBGR8888:
2139 case DRM_FORMAT_ABGR8888:
2140 dspcntr |= DISPPLANE_RGBX888;
2141 break;
2142 case DRM_FORMAT_XRGB2101010:
2143 case DRM_FORMAT_ARGB2101010:
2144 dspcntr |= DISPPLANE_BGRX101010;
2145 break;
2146 case DRM_FORMAT_XBGR2101010:
2147 case DRM_FORMAT_ABGR2101010:
2148 dspcntr |= DISPPLANE_RGBX101010;
2149 break;
2150 default:
2151 BUG();
2152 }
2153
2154 if (obj->tiling_mode != I915_TILING_NONE)
2155 dspcntr |= DISPPLANE_TILED;
2156 else
2157 dspcntr &= ~DISPPLANE_TILED;
2158
2159 if (IS_HASWELL(dev))
2160 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2161 else
2162 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2163
2164 I915_WRITE(reg, dspcntr);
2165
2166 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2167 intel_crtc->dspaddr_offset =
2168 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2169 fb->bits_per_pixel / 8,
2170 fb->pitches[0]);
2171 linear_offset -= intel_crtc->dspaddr_offset;
2172
2173 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2174 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2175 fb->pitches[0]);
2176 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2177 I915_MODIFY_DISPBASE(DSPSURF(plane),
2178 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2179 if (IS_HASWELL(dev)) {
2180 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2181 } else {
2182 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2183 I915_WRITE(DSPLINOFF(plane), linear_offset);
2184 }
2185 POSTING_READ(reg);
2186
2187 return 0;
2188 }
2189
2190 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2191 static int
2192 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2193 int x, int y, enum mode_set_atomic state)
2194 {
2195 struct drm_device *dev = crtc->dev;
2196 struct drm_i915_private *dev_priv = dev->dev_private;
2197
2198 if (dev_priv->display.disable_fbc)
2199 dev_priv->display.disable_fbc(dev);
2200 intel_increase_pllclock(crtc);
2201
2202 return dev_priv->display.update_plane(crtc, fb, x, y);
2203 }
2204
2205 void intel_display_handle_reset(struct drm_device *dev)
2206 {
2207 struct drm_i915_private *dev_priv = dev->dev_private;
2208 struct drm_crtc *crtc;
2209
2210 /*
2211 * Flips in the rings have been nuked by the reset,
2212 * so complete all pending flips so that user space
2213 * will get its events and not get stuck.
2214 *
2215 * Also update the base address of all primary
2216 * planes to the the last fb to make sure we're
2217 * showing the correct fb after a reset.
2218 *
2219 * Need to make two loops over the crtcs so that we
2220 * don't try to grab a crtc mutex before the
2221 * pending_flip_queue really got woken up.
2222 */
2223
2224 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2226 enum plane plane = intel_crtc->plane;
2227
2228 intel_prepare_page_flip(dev, plane);
2229 intel_finish_page_flip_plane(dev, plane);
2230 }
2231
2232 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2234
2235 mutex_lock(&crtc->mutex);
2236 if (intel_crtc->active)
2237 dev_priv->display.update_plane(crtc, crtc->fb,
2238 crtc->x, crtc->y);
2239 mutex_unlock(&crtc->mutex);
2240 }
2241 }
2242
2243 static int
2244 intel_finish_fb(struct drm_framebuffer *old_fb)
2245 {
2246 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2247 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2248 bool was_interruptible = dev_priv->mm.interruptible;
2249 int ret;
2250
2251 /* Big Hammer, we also need to ensure that any pending
2252 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2253 * current scanout is retired before unpinning the old
2254 * framebuffer.
2255 *
2256 * This should only fail upon a hung GPU, in which case we
2257 * can safely continue.
2258 */
2259 dev_priv->mm.interruptible = false;
2260 ret = i915_gem_object_finish_gpu(obj);
2261 dev_priv->mm.interruptible = was_interruptible;
2262
2263 return ret;
2264 }
2265
2266 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2267 {
2268 struct drm_device *dev = crtc->dev;
2269 struct drm_i915_master_private *master_priv;
2270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2271
2272 if (!dev->primary->master)
2273 return;
2274
2275 master_priv = dev->primary->master->driver_priv;
2276 if (!master_priv->sarea_priv)
2277 return;
2278
2279 switch (intel_crtc->pipe) {
2280 case 0:
2281 master_priv->sarea_priv->pipeA_x = x;
2282 master_priv->sarea_priv->pipeA_y = y;
2283 break;
2284 case 1:
2285 master_priv->sarea_priv->pipeB_x = x;
2286 master_priv->sarea_priv->pipeB_y = y;
2287 break;
2288 default:
2289 break;
2290 }
2291 }
2292
2293 static int
2294 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2295 struct drm_framebuffer *fb)
2296 {
2297 struct drm_device *dev = crtc->dev;
2298 struct drm_i915_private *dev_priv = dev->dev_private;
2299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2300 struct drm_framebuffer *old_fb;
2301 int ret;
2302
2303 /* no fb bound */
2304 if (!fb) {
2305 DRM_ERROR("No FB bound\n");
2306 return 0;
2307 }
2308
2309 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2310 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2311 plane_name(intel_crtc->plane),
2312 INTEL_INFO(dev)->num_pipes);
2313 return -EINVAL;
2314 }
2315
2316 mutex_lock(&dev->struct_mutex);
2317 ret = intel_pin_and_fence_fb_obj(dev,
2318 to_intel_framebuffer(fb)->obj,
2319 NULL);
2320 if (ret != 0) {
2321 mutex_unlock(&dev->struct_mutex);
2322 DRM_ERROR("pin & fence failed\n");
2323 return ret;
2324 }
2325
2326 /*
2327 * Update pipe size and adjust fitter if needed: the reason for this is
2328 * that in compute_mode_changes we check the native mode (not the pfit
2329 * mode) to see if we can flip rather than do a full mode set. In the
2330 * fastboot case, we'll flip, but if we don't update the pipesrc and
2331 * pfit state, we'll end up with a big fb scanned out into the wrong
2332 * sized surface.
2333 *
2334 * To fix this properly, we need to hoist the checks up into
2335 * compute_mode_changes (or above), check the actual pfit state and
2336 * whether the platform allows pfit disable with pipe active, and only
2337 * then update the pipesrc and pfit state, even on the flip path.
2338 */
2339 if (i915_fastboot) {
2340 const struct drm_display_mode *adjusted_mode =
2341 &intel_crtc->config.adjusted_mode;
2342
2343 I915_WRITE(PIPESRC(intel_crtc->pipe),
2344 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2345 (adjusted_mode->crtc_vdisplay - 1));
2346 if (!intel_crtc->config.pch_pfit.enabled &&
2347 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2348 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2349 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2350 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2351 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2352 }
2353 }
2354
2355 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2356 if (ret) {
2357 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2358 mutex_unlock(&dev->struct_mutex);
2359 DRM_ERROR("failed to update base address\n");
2360 return ret;
2361 }
2362
2363 old_fb = crtc->fb;
2364 crtc->fb = fb;
2365 crtc->x = x;
2366 crtc->y = y;
2367
2368 if (old_fb) {
2369 if (intel_crtc->active && old_fb != fb)
2370 intel_wait_for_vblank(dev, intel_crtc->pipe);
2371 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2372 }
2373
2374 intel_update_fbc(dev);
2375 intel_edp_psr_update(dev);
2376 mutex_unlock(&dev->struct_mutex);
2377
2378 intel_crtc_update_sarea_pos(crtc, x, y);
2379
2380 return 0;
2381 }
2382
2383 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2384 {
2385 struct drm_device *dev = crtc->dev;
2386 struct drm_i915_private *dev_priv = dev->dev_private;
2387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2388 int pipe = intel_crtc->pipe;
2389 u32 reg, temp;
2390
2391 /* enable normal train */
2392 reg = FDI_TX_CTL(pipe);
2393 temp = I915_READ(reg);
2394 if (IS_IVYBRIDGE(dev)) {
2395 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2396 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2397 } else {
2398 temp &= ~FDI_LINK_TRAIN_NONE;
2399 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2400 }
2401 I915_WRITE(reg, temp);
2402
2403 reg = FDI_RX_CTL(pipe);
2404 temp = I915_READ(reg);
2405 if (HAS_PCH_CPT(dev)) {
2406 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2407 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2408 } else {
2409 temp &= ~FDI_LINK_TRAIN_NONE;
2410 temp |= FDI_LINK_TRAIN_NONE;
2411 }
2412 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2413
2414 /* wait one idle pattern time */
2415 POSTING_READ(reg);
2416 udelay(1000);
2417
2418 /* IVB wants error correction enabled */
2419 if (IS_IVYBRIDGE(dev))
2420 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2421 FDI_FE_ERRC_ENABLE);
2422 }
2423
2424 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2425 {
2426 return crtc->base.enabled && crtc->active &&
2427 crtc->config.has_pch_encoder;
2428 }
2429
2430 static void ivb_modeset_global_resources(struct drm_device *dev)
2431 {
2432 struct drm_i915_private *dev_priv = dev->dev_private;
2433 struct intel_crtc *pipe_B_crtc =
2434 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2435 struct intel_crtc *pipe_C_crtc =
2436 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2437 uint32_t temp;
2438
2439 /*
2440 * When everything is off disable fdi C so that we could enable fdi B
2441 * with all lanes. Note that we don't care about enabled pipes without
2442 * an enabled pch encoder.
2443 */
2444 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2445 !pipe_has_enabled_pch(pipe_C_crtc)) {
2446 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2447 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2448
2449 temp = I915_READ(SOUTH_CHICKEN1);
2450 temp &= ~FDI_BC_BIFURCATION_SELECT;
2451 DRM_DEBUG_KMS("disabling fdi C rx\n");
2452 I915_WRITE(SOUTH_CHICKEN1, temp);
2453 }
2454 }
2455
2456 /* The FDI link training functions for ILK/Ibexpeak. */
2457 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2458 {
2459 struct drm_device *dev = crtc->dev;
2460 struct drm_i915_private *dev_priv = dev->dev_private;
2461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2462 int pipe = intel_crtc->pipe;
2463 int plane = intel_crtc->plane;
2464 u32 reg, temp, tries;
2465
2466 /* FDI needs bits from pipe & plane first */
2467 assert_pipe_enabled(dev_priv, pipe);
2468 assert_plane_enabled(dev_priv, plane);
2469
2470 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2471 for train result */
2472 reg = FDI_RX_IMR(pipe);
2473 temp = I915_READ(reg);
2474 temp &= ~FDI_RX_SYMBOL_LOCK;
2475 temp &= ~FDI_RX_BIT_LOCK;
2476 I915_WRITE(reg, temp);
2477 I915_READ(reg);
2478 udelay(150);
2479
2480 /* enable CPU FDI TX and PCH FDI RX */
2481 reg = FDI_TX_CTL(pipe);
2482 temp = I915_READ(reg);
2483 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2484 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2485 temp &= ~FDI_LINK_TRAIN_NONE;
2486 temp |= FDI_LINK_TRAIN_PATTERN_1;
2487 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2488
2489 reg = FDI_RX_CTL(pipe);
2490 temp = I915_READ(reg);
2491 temp &= ~FDI_LINK_TRAIN_NONE;
2492 temp |= FDI_LINK_TRAIN_PATTERN_1;
2493 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2494
2495 POSTING_READ(reg);
2496 udelay(150);
2497
2498 /* Ironlake workaround, enable clock pointer after FDI enable*/
2499 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2500 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2501 FDI_RX_PHASE_SYNC_POINTER_EN);
2502
2503 reg = FDI_RX_IIR(pipe);
2504 for (tries = 0; tries < 5; tries++) {
2505 temp = I915_READ(reg);
2506 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2507
2508 if ((temp & FDI_RX_BIT_LOCK)) {
2509 DRM_DEBUG_KMS("FDI train 1 done.\n");
2510 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2511 break;
2512 }
2513 }
2514 if (tries == 5)
2515 DRM_ERROR("FDI train 1 fail!\n");
2516
2517 /* Train 2 */
2518 reg = FDI_TX_CTL(pipe);
2519 temp = I915_READ(reg);
2520 temp &= ~FDI_LINK_TRAIN_NONE;
2521 temp |= FDI_LINK_TRAIN_PATTERN_2;
2522 I915_WRITE(reg, temp);
2523
2524 reg = FDI_RX_CTL(pipe);
2525 temp = I915_READ(reg);
2526 temp &= ~FDI_LINK_TRAIN_NONE;
2527 temp |= FDI_LINK_TRAIN_PATTERN_2;
2528 I915_WRITE(reg, temp);
2529
2530 POSTING_READ(reg);
2531 udelay(150);
2532
2533 reg = FDI_RX_IIR(pipe);
2534 for (tries = 0; tries < 5; tries++) {
2535 temp = I915_READ(reg);
2536 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2537
2538 if (temp & FDI_RX_SYMBOL_LOCK) {
2539 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2540 DRM_DEBUG_KMS("FDI train 2 done.\n");
2541 break;
2542 }
2543 }
2544 if (tries == 5)
2545 DRM_ERROR("FDI train 2 fail!\n");
2546
2547 DRM_DEBUG_KMS("FDI train done\n");
2548
2549 }
2550
2551 static const int snb_b_fdi_train_param[] = {
2552 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2553 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2554 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2555 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2556 };
2557
2558 /* The FDI link training functions for SNB/Cougarpoint. */
2559 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2560 {
2561 struct drm_device *dev = crtc->dev;
2562 struct drm_i915_private *dev_priv = dev->dev_private;
2563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2564 int pipe = intel_crtc->pipe;
2565 u32 reg, temp, i, retry;
2566
2567 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2568 for train result */
2569 reg = FDI_RX_IMR(pipe);
2570 temp = I915_READ(reg);
2571 temp &= ~FDI_RX_SYMBOL_LOCK;
2572 temp &= ~FDI_RX_BIT_LOCK;
2573 I915_WRITE(reg, temp);
2574
2575 POSTING_READ(reg);
2576 udelay(150);
2577
2578 /* enable CPU FDI TX and PCH FDI RX */
2579 reg = FDI_TX_CTL(pipe);
2580 temp = I915_READ(reg);
2581 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2582 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2583 temp &= ~FDI_LINK_TRAIN_NONE;
2584 temp |= FDI_LINK_TRAIN_PATTERN_1;
2585 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2586 /* SNB-B */
2587 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2588 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2589
2590 I915_WRITE(FDI_RX_MISC(pipe),
2591 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2592
2593 reg = FDI_RX_CTL(pipe);
2594 temp = I915_READ(reg);
2595 if (HAS_PCH_CPT(dev)) {
2596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2598 } else {
2599 temp &= ~FDI_LINK_TRAIN_NONE;
2600 temp |= FDI_LINK_TRAIN_PATTERN_1;
2601 }
2602 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2603
2604 POSTING_READ(reg);
2605 udelay(150);
2606
2607 for (i = 0; i < 4; i++) {
2608 reg = FDI_TX_CTL(pipe);
2609 temp = I915_READ(reg);
2610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2611 temp |= snb_b_fdi_train_param[i];
2612 I915_WRITE(reg, temp);
2613
2614 POSTING_READ(reg);
2615 udelay(500);
2616
2617 for (retry = 0; retry < 5; retry++) {
2618 reg = FDI_RX_IIR(pipe);
2619 temp = I915_READ(reg);
2620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621 if (temp & FDI_RX_BIT_LOCK) {
2622 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2623 DRM_DEBUG_KMS("FDI train 1 done.\n");
2624 break;
2625 }
2626 udelay(50);
2627 }
2628 if (retry < 5)
2629 break;
2630 }
2631 if (i == 4)
2632 DRM_ERROR("FDI train 1 fail!\n");
2633
2634 /* Train 2 */
2635 reg = FDI_TX_CTL(pipe);
2636 temp = I915_READ(reg);
2637 temp &= ~FDI_LINK_TRAIN_NONE;
2638 temp |= FDI_LINK_TRAIN_PATTERN_2;
2639 if (IS_GEN6(dev)) {
2640 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2641 /* SNB-B */
2642 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2643 }
2644 I915_WRITE(reg, temp);
2645
2646 reg = FDI_RX_CTL(pipe);
2647 temp = I915_READ(reg);
2648 if (HAS_PCH_CPT(dev)) {
2649 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2650 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2651 } else {
2652 temp &= ~FDI_LINK_TRAIN_NONE;
2653 temp |= FDI_LINK_TRAIN_PATTERN_2;
2654 }
2655 I915_WRITE(reg, temp);
2656
2657 POSTING_READ(reg);
2658 udelay(150);
2659
2660 for (i = 0; i < 4; i++) {
2661 reg = FDI_TX_CTL(pipe);
2662 temp = I915_READ(reg);
2663 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2664 temp |= snb_b_fdi_train_param[i];
2665 I915_WRITE(reg, temp);
2666
2667 POSTING_READ(reg);
2668 udelay(500);
2669
2670 for (retry = 0; retry < 5; retry++) {
2671 reg = FDI_RX_IIR(pipe);
2672 temp = I915_READ(reg);
2673 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2674 if (temp & FDI_RX_SYMBOL_LOCK) {
2675 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2676 DRM_DEBUG_KMS("FDI train 2 done.\n");
2677 break;
2678 }
2679 udelay(50);
2680 }
2681 if (retry < 5)
2682 break;
2683 }
2684 if (i == 4)
2685 DRM_ERROR("FDI train 2 fail!\n");
2686
2687 DRM_DEBUG_KMS("FDI train done.\n");
2688 }
2689
2690 /* Manual link training for Ivy Bridge A0 parts */
2691 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2692 {
2693 struct drm_device *dev = crtc->dev;
2694 struct drm_i915_private *dev_priv = dev->dev_private;
2695 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2696 int pipe = intel_crtc->pipe;
2697 u32 reg, temp, i, j;
2698
2699 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2700 for train result */
2701 reg = FDI_RX_IMR(pipe);
2702 temp = I915_READ(reg);
2703 temp &= ~FDI_RX_SYMBOL_LOCK;
2704 temp &= ~FDI_RX_BIT_LOCK;
2705 I915_WRITE(reg, temp);
2706
2707 POSTING_READ(reg);
2708 udelay(150);
2709
2710 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2711 I915_READ(FDI_RX_IIR(pipe)));
2712
2713 /* Try each vswing and preemphasis setting twice before moving on */
2714 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2715 /* disable first in case we need to retry */
2716 reg = FDI_TX_CTL(pipe);
2717 temp = I915_READ(reg);
2718 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2719 temp &= ~FDI_TX_ENABLE;
2720 I915_WRITE(reg, temp);
2721
2722 reg = FDI_RX_CTL(pipe);
2723 temp = I915_READ(reg);
2724 temp &= ~FDI_LINK_TRAIN_AUTO;
2725 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2726 temp &= ~FDI_RX_ENABLE;
2727 I915_WRITE(reg, temp);
2728
2729 /* enable CPU FDI TX and PCH FDI RX */
2730 reg = FDI_TX_CTL(pipe);
2731 temp = I915_READ(reg);
2732 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2733 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2734 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2735 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2736 temp |= snb_b_fdi_train_param[j/2];
2737 temp |= FDI_COMPOSITE_SYNC;
2738 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2739
2740 I915_WRITE(FDI_RX_MISC(pipe),
2741 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2742
2743 reg = FDI_RX_CTL(pipe);
2744 temp = I915_READ(reg);
2745 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2746 temp |= FDI_COMPOSITE_SYNC;
2747 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2748
2749 POSTING_READ(reg);
2750 udelay(1); /* should be 0.5us */
2751
2752 for (i = 0; i < 4; i++) {
2753 reg = FDI_RX_IIR(pipe);
2754 temp = I915_READ(reg);
2755 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2756
2757 if (temp & FDI_RX_BIT_LOCK ||
2758 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2759 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2760 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2761 i);
2762 break;
2763 }
2764 udelay(1); /* should be 0.5us */
2765 }
2766 if (i == 4) {
2767 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2768 continue;
2769 }
2770
2771 /* Train 2 */
2772 reg = FDI_TX_CTL(pipe);
2773 temp = I915_READ(reg);
2774 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2775 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2776 I915_WRITE(reg, temp);
2777
2778 reg = FDI_RX_CTL(pipe);
2779 temp = I915_READ(reg);
2780 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2781 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2782 I915_WRITE(reg, temp);
2783
2784 POSTING_READ(reg);
2785 udelay(2); /* should be 1.5us */
2786
2787 for (i = 0; i < 4; i++) {
2788 reg = FDI_RX_IIR(pipe);
2789 temp = I915_READ(reg);
2790 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2791
2792 if (temp & FDI_RX_SYMBOL_LOCK ||
2793 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2794 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2795 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2796 i);
2797 goto train_done;
2798 }
2799 udelay(2); /* should be 1.5us */
2800 }
2801 if (i == 4)
2802 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2803 }
2804
2805 train_done:
2806 DRM_DEBUG_KMS("FDI train done.\n");
2807 }
2808
2809 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2810 {
2811 struct drm_device *dev = intel_crtc->base.dev;
2812 struct drm_i915_private *dev_priv = dev->dev_private;
2813 int pipe = intel_crtc->pipe;
2814 u32 reg, temp;
2815
2816
2817 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2818 reg = FDI_RX_CTL(pipe);
2819 temp = I915_READ(reg);
2820 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2821 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2822 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2823 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2824
2825 POSTING_READ(reg);
2826 udelay(200);
2827
2828 /* Switch from Rawclk to PCDclk */
2829 temp = I915_READ(reg);
2830 I915_WRITE(reg, temp | FDI_PCDCLK);
2831
2832 POSTING_READ(reg);
2833 udelay(200);
2834
2835 /* Enable CPU FDI TX PLL, always on for Ironlake */
2836 reg = FDI_TX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2839 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2840
2841 POSTING_READ(reg);
2842 udelay(100);
2843 }
2844 }
2845
2846 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2847 {
2848 struct drm_device *dev = intel_crtc->base.dev;
2849 struct drm_i915_private *dev_priv = dev->dev_private;
2850 int pipe = intel_crtc->pipe;
2851 u32 reg, temp;
2852
2853 /* Switch from PCDclk to Rawclk */
2854 reg = FDI_RX_CTL(pipe);
2855 temp = I915_READ(reg);
2856 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2857
2858 /* Disable CPU FDI TX PLL */
2859 reg = FDI_TX_CTL(pipe);
2860 temp = I915_READ(reg);
2861 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2862
2863 POSTING_READ(reg);
2864 udelay(100);
2865
2866 reg = FDI_RX_CTL(pipe);
2867 temp = I915_READ(reg);
2868 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2869
2870 /* Wait for the clocks to turn off. */
2871 POSTING_READ(reg);
2872 udelay(100);
2873 }
2874
2875 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2876 {
2877 struct drm_device *dev = crtc->dev;
2878 struct drm_i915_private *dev_priv = dev->dev_private;
2879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2880 int pipe = intel_crtc->pipe;
2881 u32 reg, temp;
2882
2883 /* disable CPU FDI tx and PCH FDI rx */
2884 reg = FDI_TX_CTL(pipe);
2885 temp = I915_READ(reg);
2886 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2887 POSTING_READ(reg);
2888
2889 reg = FDI_RX_CTL(pipe);
2890 temp = I915_READ(reg);
2891 temp &= ~(0x7 << 16);
2892 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2893 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2894
2895 POSTING_READ(reg);
2896 udelay(100);
2897
2898 /* Ironlake workaround, disable clock pointer after downing FDI */
2899 if (HAS_PCH_IBX(dev)) {
2900 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2901 }
2902
2903 /* still set train pattern 1 */
2904 reg = FDI_TX_CTL(pipe);
2905 temp = I915_READ(reg);
2906 temp &= ~FDI_LINK_TRAIN_NONE;
2907 temp |= FDI_LINK_TRAIN_PATTERN_1;
2908 I915_WRITE(reg, temp);
2909
2910 reg = FDI_RX_CTL(pipe);
2911 temp = I915_READ(reg);
2912 if (HAS_PCH_CPT(dev)) {
2913 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2914 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2915 } else {
2916 temp &= ~FDI_LINK_TRAIN_NONE;
2917 temp |= FDI_LINK_TRAIN_PATTERN_1;
2918 }
2919 /* BPC in FDI rx is consistent with that in PIPECONF */
2920 temp &= ~(0x07 << 16);
2921 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2922 I915_WRITE(reg, temp);
2923
2924 POSTING_READ(reg);
2925 udelay(100);
2926 }
2927
2928 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2929 {
2930 struct drm_device *dev = crtc->dev;
2931 struct drm_i915_private *dev_priv = dev->dev_private;
2932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2933 unsigned long flags;
2934 bool pending;
2935
2936 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2937 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2938 return false;
2939
2940 spin_lock_irqsave(&dev->event_lock, flags);
2941 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2942 spin_unlock_irqrestore(&dev->event_lock, flags);
2943
2944 return pending;
2945 }
2946
2947 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2948 {
2949 struct drm_device *dev = crtc->dev;
2950 struct drm_i915_private *dev_priv = dev->dev_private;
2951
2952 if (crtc->fb == NULL)
2953 return;
2954
2955 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2956
2957 wait_event(dev_priv->pending_flip_queue,
2958 !intel_crtc_has_pending_flip(crtc));
2959
2960 mutex_lock(&dev->struct_mutex);
2961 intel_finish_fb(crtc->fb);
2962 mutex_unlock(&dev->struct_mutex);
2963 }
2964
2965 /* Program iCLKIP clock to the desired frequency */
2966 static void lpt_program_iclkip(struct drm_crtc *crtc)
2967 {
2968 struct drm_device *dev = crtc->dev;
2969 struct drm_i915_private *dev_priv = dev->dev_private;
2970 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
2971 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2972 u32 temp;
2973
2974 mutex_lock(&dev_priv->dpio_lock);
2975
2976 /* It is necessary to ungate the pixclk gate prior to programming
2977 * the divisors, and gate it back when it is done.
2978 */
2979 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2980
2981 /* Disable SSCCTL */
2982 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2983 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2984 SBI_SSCCTL_DISABLE,
2985 SBI_ICLK);
2986
2987 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2988 if (clock == 20000) {
2989 auxdiv = 1;
2990 divsel = 0x41;
2991 phaseinc = 0x20;
2992 } else {
2993 /* The iCLK virtual clock root frequency is in MHz,
2994 * but the adjusted_mode->crtc_clock in in KHz. To get the
2995 * divisors, it is necessary to divide one by another, so we
2996 * convert the virtual clock precision to KHz here for higher
2997 * precision.
2998 */
2999 u32 iclk_virtual_root_freq = 172800 * 1000;
3000 u32 iclk_pi_range = 64;
3001 u32 desired_divisor, msb_divisor_value, pi_value;
3002
3003 desired_divisor = (iclk_virtual_root_freq / clock);
3004 msb_divisor_value = desired_divisor / iclk_pi_range;
3005 pi_value = desired_divisor % iclk_pi_range;
3006
3007 auxdiv = 0;
3008 divsel = msb_divisor_value - 2;
3009 phaseinc = pi_value;
3010 }
3011
3012 /* This should not happen with any sane values */
3013 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3014 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3015 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3016 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3017
3018 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3019 clock,
3020 auxdiv,
3021 divsel,
3022 phasedir,
3023 phaseinc);
3024
3025 /* Program SSCDIVINTPHASE6 */
3026 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3027 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3028 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3029 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3030 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3031 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3032 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3033 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3034
3035 /* Program SSCAUXDIV */
3036 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3037 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3038 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3039 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3040
3041 /* Enable modulator and associated divider */
3042 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3043 temp &= ~SBI_SSCCTL_DISABLE;
3044 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3045
3046 /* Wait for initialization time */
3047 udelay(24);
3048
3049 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3050
3051 mutex_unlock(&dev_priv->dpio_lock);
3052 }
3053
3054 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3055 enum pipe pch_transcoder)
3056 {
3057 struct drm_device *dev = crtc->base.dev;
3058 struct drm_i915_private *dev_priv = dev->dev_private;
3059 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3060
3061 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3062 I915_READ(HTOTAL(cpu_transcoder)));
3063 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3064 I915_READ(HBLANK(cpu_transcoder)));
3065 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3066 I915_READ(HSYNC(cpu_transcoder)));
3067
3068 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3069 I915_READ(VTOTAL(cpu_transcoder)));
3070 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3071 I915_READ(VBLANK(cpu_transcoder)));
3072 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3073 I915_READ(VSYNC(cpu_transcoder)));
3074 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3075 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3076 }
3077
3078 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3079 {
3080 struct drm_i915_private *dev_priv = dev->dev_private;
3081 uint32_t temp;
3082
3083 temp = I915_READ(SOUTH_CHICKEN1);
3084 if (temp & FDI_BC_BIFURCATION_SELECT)
3085 return;
3086
3087 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3088 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3089
3090 temp |= FDI_BC_BIFURCATION_SELECT;
3091 DRM_DEBUG_KMS("enabling fdi C rx\n");
3092 I915_WRITE(SOUTH_CHICKEN1, temp);
3093 POSTING_READ(SOUTH_CHICKEN1);
3094 }
3095
3096 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3097 {
3098 struct drm_device *dev = intel_crtc->base.dev;
3099 struct drm_i915_private *dev_priv = dev->dev_private;
3100
3101 switch (intel_crtc->pipe) {
3102 case PIPE_A:
3103 break;
3104 case PIPE_B:
3105 if (intel_crtc->config.fdi_lanes > 2)
3106 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3107 else
3108 cpt_enable_fdi_bc_bifurcation(dev);
3109
3110 break;
3111 case PIPE_C:
3112 cpt_enable_fdi_bc_bifurcation(dev);
3113
3114 break;
3115 default:
3116 BUG();
3117 }
3118 }
3119
3120 /*
3121 * Enable PCH resources required for PCH ports:
3122 * - PCH PLLs
3123 * - FDI training & RX/TX
3124 * - update transcoder timings
3125 * - DP transcoding bits
3126 * - transcoder
3127 */
3128 static void ironlake_pch_enable(struct drm_crtc *crtc)
3129 {
3130 struct drm_device *dev = crtc->dev;
3131 struct drm_i915_private *dev_priv = dev->dev_private;
3132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3133 int pipe = intel_crtc->pipe;
3134 u32 reg, temp;
3135
3136 assert_pch_transcoder_disabled(dev_priv, pipe);
3137
3138 if (IS_IVYBRIDGE(dev))
3139 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3140
3141 /* Write the TU size bits before fdi link training, so that error
3142 * detection works. */
3143 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3144 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3145
3146 /* For PCH output, training FDI link */
3147 dev_priv->display.fdi_link_train(crtc);
3148
3149 /* We need to program the right clock selection before writing the pixel
3150 * mutliplier into the DPLL. */
3151 if (HAS_PCH_CPT(dev)) {
3152 u32 sel;
3153
3154 temp = I915_READ(PCH_DPLL_SEL);
3155 temp |= TRANS_DPLL_ENABLE(pipe);
3156 sel = TRANS_DPLLB_SEL(pipe);
3157 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3158 temp |= sel;
3159 else
3160 temp &= ~sel;
3161 I915_WRITE(PCH_DPLL_SEL, temp);
3162 }
3163
3164 /* XXX: pch pll's can be enabled any time before we enable the PCH
3165 * transcoder, and we actually should do this to not upset any PCH
3166 * transcoder that already use the clock when we share it.
3167 *
3168 * Note that enable_shared_dpll tries to do the right thing, but
3169 * get_shared_dpll unconditionally resets the pll - we need that to have
3170 * the right LVDS enable sequence. */
3171 ironlake_enable_shared_dpll(intel_crtc);
3172
3173 /* set transcoder timing, panel must allow it */
3174 assert_panel_unlocked(dev_priv, pipe);
3175 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3176
3177 intel_fdi_normal_train(crtc);
3178
3179 /* For PCH DP, enable TRANS_DP_CTL */
3180 if (HAS_PCH_CPT(dev) &&
3181 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3182 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3183 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3184 reg = TRANS_DP_CTL(pipe);
3185 temp = I915_READ(reg);
3186 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3187 TRANS_DP_SYNC_MASK |
3188 TRANS_DP_BPC_MASK);
3189 temp |= (TRANS_DP_OUTPUT_ENABLE |
3190 TRANS_DP_ENH_FRAMING);
3191 temp |= bpc << 9; /* same format but at 11:9 */
3192
3193 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3194 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3195 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3196 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3197
3198 switch (intel_trans_dp_port_sel(crtc)) {
3199 case PCH_DP_B:
3200 temp |= TRANS_DP_PORT_SEL_B;
3201 break;
3202 case PCH_DP_C:
3203 temp |= TRANS_DP_PORT_SEL_C;
3204 break;
3205 case PCH_DP_D:
3206 temp |= TRANS_DP_PORT_SEL_D;
3207 break;
3208 default:
3209 BUG();
3210 }
3211
3212 I915_WRITE(reg, temp);
3213 }
3214
3215 ironlake_enable_pch_transcoder(dev_priv, pipe);
3216 }
3217
3218 static void lpt_pch_enable(struct drm_crtc *crtc)
3219 {
3220 struct drm_device *dev = crtc->dev;
3221 struct drm_i915_private *dev_priv = dev->dev_private;
3222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3223 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3224
3225 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3226
3227 lpt_program_iclkip(crtc);
3228
3229 /* Set transcoder timing. */
3230 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3231
3232 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3233 }
3234
3235 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3236 {
3237 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3238
3239 if (pll == NULL)
3240 return;
3241
3242 if (pll->refcount == 0) {
3243 WARN(1, "bad %s refcount\n", pll->name);
3244 return;
3245 }
3246
3247 if (--pll->refcount == 0) {
3248 WARN_ON(pll->on);
3249 WARN_ON(pll->active);
3250 }
3251
3252 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3253 }
3254
3255 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3256 {
3257 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3258 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3259 enum intel_dpll_id i;
3260
3261 if (pll) {
3262 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3263 crtc->base.base.id, pll->name);
3264 intel_put_shared_dpll(crtc);
3265 }
3266
3267 if (HAS_PCH_IBX(dev_priv->dev)) {
3268 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3269 i = (enum intel_dpll_id) crtc->pipe;
3270 pll = &dev_priv->shared_dplls[i];
3271
3272 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3273 crtc->base.base.id, pll->name);
3274
3275 goto found;
3276 }
3277
3278 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3279 pll = &dev_priv->shared_dplls[i];
3280
3281 /* Only want to check enabled timings first */
3282 if (pll->refcount == 0)
3283 continue;
3284
3285 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3286 sizeof(pll->hw_state)) == 0) {
3287 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3288 crtc->base.base.id,
3289 pll->name, pll->refcount, pll->active);
3290
3291 goto found;
3292 }
3293 }
3294
3295 /* Ok no matching timings, maybe there's a free one? */
3296 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3297 pll = &dev_priv->shared_dplls[i];
3298 if (pll->refcount == 0) {
3299 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3300 crtc->base.base.id, pll->name);
3301 goto found;
3302 }
3303 }
3304
3305 return NULL;
3306
3307 found:
3308 crtc->config.shared_dpll = i;
3309 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3310 pipe_name(crtc->pipe));
3311
3312 if (pll->active == 0) {
3313 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3314 sizeof(pll->hw_state));
3315
3316 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3317 WARN_ON(pll->on);
3318 assert_shared_dpll_disabled(dev_priv, pll);
3319
3320 pll->mode_set(dev_priv, pll);
3321 }
3322 pll->refcount++;
3323
3324 return pll;
3325 }
3326
3327 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3328 {
3329 struct drm_i915_private *dev_priv = dev->dev_private;
3330 int dslreg = PIPEDSL(pipe);
3331 u32 temp;
3332
3333 temp = I915_READ(dslreg);
3334 udelay(500);
3335 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3336 if (wait_for(I915_READ(dslreg) != temp, 5))
3337 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3338 }
3339 }
3340
3341 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3342 {
3343 struct drm_device *dev = crtc->base.dev;
3344 struct drm_i915_private *dev_priv = dev->dev_private;
3345 int pipe = crtc->pipe;
3346
3347 if (crtc->config.pch_pfit.enabled) {
3348 /* Force use of hard-coded filter coefficients
3349 * as some pre-programmed values are broken,
3350 * e.g. x201.
3351 */
3352 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3353 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3354 PF_PIPE_SEL_IVB(pipe));
3355 else
3356 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3357 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3358 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3359 }
3360 }
3361
3362 static void intel_enable_planes(struct drm_crtc *crtc)
3363 {
3364 struct drm_device *dev = crtc->dev;
3365 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3366 struct intel_plane *intel_plane;
3367
3368 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3369 if (intel_plane->pipe == pipe)
3370 intel_plane_restore(&intel_plane->base);
3371 }
3372
3373 static void intel_disable_planes(struct drm_crtc *crtc)
3374 {
3375 struct drm_device *dev = crtc->dev;
3376 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3377 struct intel_plane *intel_plane;
3378
3379 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3380 if (intel_plane->pipe == pipe)
3381 intel_plane_disable(&intel_plane->base);
3382 }
3383
3384 void hsw_enable_ips(struct intel_crtc *crtc)
3385 {
3386 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3387
3388 if (!crtc->config.ips_enabled)
3389 return;
3390
3391 /* We can only enable IPS after we enable a plane and wait for a vblank.
3392 * We guarantee that the plane is enabled by calling intel_enable_ips
3393 * only after intel_enable_plane. And intel_enable_plane already waits
3394 * for a vblank, so all we need to do here is to enable the IPS bit. */
3395 assert_plane_enabled(dev_priv, crtc->plane);
3396 I915_WRITE(IPS_CTL, IPS_ENABLE);
3397
3398 /* The bit only becomes 1 in the next vblank, so this wait here is
3399 * essentially intel_wait_for_vblank. If we don't have this and don't
3400 * wait for vblanks until the end of crtc_enable, then the HW state
3401 * readout code will complain that the expected IPS_CTL value is not the
3402 * one we read. */
3403 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3404 DRM_ERROR("Timed out waiting for IPS enable\n");
3405 }
3406
3407 void hsw_disable_ips(struct intel_crtc *crtc)
3408 {
3409 struct drm_device *dev = crtc->base.dev;
3410 struct drm_i915_private *dev_priv = dev->dev_private;
3411
3412 if (!crtc->config.ips_enabled)
3413 return;
3414
3415 assert_plane_enabled(dev_priv, crtc->plane);
3416 I915_WRITE(IPS_CTL, 0);
3417 POSTING_READ(IPS_CTL);
3418
3419 /* We need to wait for a vblank before we can disable the plane. */
3420 intel_wait_for_vblank(dev, crtc->pipe);
3421 }
3422
3423 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3424 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3425 {
3426 struct drm_device *dev = crtc->dev;
3427 struct drm_i915_private *dev_priv = dev->dev_private;
3428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3429 enum pipe pipe = intel_crtc->pipe;
3430 int palreg = PALETTE(pipe);
3431 int i;
3432 bool reenable_ips = false;
3433
3434 /* The clocks have to be on to load the palette. */
3435 if (!crtc->enabled || !intel_crtc->active)
3436 return;
3437
3438 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3439 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3440 assert_dsi_pll_enabled(dev_priv);
3441 else
3442 assert_pll_enabled(dev_priv, pipe);
3443 }
3444
3445 /* use legacy palette for Ironlake */
3446 if (HAS_PCH_SPLIT(dev))
3447 palreg = LGC_PALETTE(pipe);
3448
3449 /* Workaround : Do not read or write the pipe palette/gamma data while
3450 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3451 */
3452 if (intel_crtc->config.ips_enabled &&
3453 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3454 GAMMA_MODE_MODE_SPLIT)) {
3455 hsw_disable_ips(intel_crtc);
3456 reenable_ips = true;
3457 }
3458
3459 for (i = 0; i < 256; i++) {
3460 I915_WRITE(palreg + 4 * i,
3461 (intel_crtc->lut_r[i] << 16) |
3462 (intel_crtc->lut_g[i] << 8) |
3463 intel_crtc->lut_b[i]);
3464 }
3465
3466 if (reenable_ips)
3467 hsw_enable_ips(intel_crtc);
3468 }
3469
3470 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3471 {
3472 struct drm_device *dev = crtc->dev;
3473 struct drm_i915_private *dev_priv = dev->dev_private;
3474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3475 struct intel_encoder *encoder;
3476 int pipe = intel_crtc->pipe;
3477 int plane = intel_crtc->plane;
3478
3479 WARN_ON(!crtc->enabled);
3480
3481 if (intel_crtc->active)
3482 return;
3483
3484 intel_crtc->active = true;
3485
3486 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3487 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3488
3489 for_each_encoder_on_crtc(dev, crtc, encoder)
3490 if (encoder->pre_enable)
3491 encoder->pre_enable(encoder);
3492
3493 if (intel_crtc->config.has_pch_encoder) {
3494 /* Note: FDI PLL enabling _must_ be done before we enable the
3495 * cpu pipes, hence this is separate from all the other fdi/pch
3496 * enabling. */
3497 ironlake_fdi_pll_enable(intel_crtc);
3498 } else {
3499 assert_fdi_tx_disabled(dev_priv, pipe);
3500 assert_fdi_rx_disabled(dev_priv, pipe);
3501 }
3502
3503 ironlake_pfit_enable(intel_crtc);
3504
3505 /*
3506 * On ILK+ LUT must be loaded before the pipe is running but with
3507 * clocks enabled
3508 */
3509 intel_crtc_load_lut(crtc);
3510
3511 intel_update_watermarks(crtc);
3512 intel_enable_pipe(dev_priv, pipe,
3513 intel_crtc->config.has_pch_encoder, false);
3514 intel_enable_primary_plane(dev_priv, plane, pipe);
3515 intel_enable_planes(crtc);
3516 intel_crtc_update_cursor(crtc, true);
3517
3518 if (intel_crtc->config.has_pch_encoder)
3519 ironlake_pch_enable(crtc);
3520
3521 mutex_lock(&dev->struct_mutex);
3522 intel_update_fbc(dev);
3523 mutex_unlock(&dev->struct_mutex);
3524
3525 for_each_encoder_on_crtc(dev, crtc, encoder)
3526 encoder->enable(encoder);
3527
3528 if (HAS_PCH_CPT(dev))
3529 cpt_verify_modeset(dev, intel_crtc->pipe);
3530
3531 /*
3532 * There seems to be a race in PCH platform hw (at least on some
3533 * outputs) where an enabled pipe still completes any pageflip right
3534 * away (as if the pipe is off) instead of waiting for vblank. As soon
3535 * as the first vblank happend, everything works as expected. Hence just
3536 * wait for one vblank before returning to avoid strange things
3537 * happening.
3538 */
3539 intel_wait_for_vblank(dev, intel_crtc->pipe);
3540 }
3541
3542 /* IPS only exists on ULT machines and is tied to pipe A. */
3543 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3544 {
3545 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3546 }
3547
3548 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3549 {
3550 struct drm_device *dev = crtc->dev;
3551 struct drm_i915_private *dev_priv = dev->dev_private;
3552 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3553 int pipe = intel_crtc->pipe;
3554 int plane = intel_crtc->plane;
3555
3556 intel_enable_primary_plane(dev_priv, plane, pipe);
3557 intel_enable_planes(crtc);
3558 intel_crtc_update_cursor(crtc, true);
3559
3560 hsw_enable_ips(intel_crtc);
3561
3562 mutex_lock(&dev->struct_mutex);
3563 intel_update_fbc(dev);
3564 mutex_unlock(&dev->struct_mutex);
3565 }
3566
3567 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3568 {
3569 struct drm_device *dev = crtc->dev;
3570 struct drm_i915_private *dev_priv = dev->dev_private;
3571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3572 int pipe = intel_crtc->pipe;
3573 int plane = intel_crtc->plane;
3574
3575 intel_crtc_wait_for_pending_flips(crtc);
3576 drm_vblank_off(dev, pipe);
3577
3578 /* FBC must be disabled before disabling the plane on HSW. */
3579 if (dev_priv->fbc.plane == plane)
3580 intel_disable_fbc(dev);
3581
3582 hsw_disable_ips(intel_crtc);
3583
3584 intel_crtc_update_cursor(crtc, false);
3585 intel_disable_planes(crtc);
3586 intel_disable_primary_plane(dev_priv, plane, pipe);
3587 }
3588
3589 /*
3590 * This implements the workaround described in the "notes" section of the mode
3591 * set sequence documentation. When going from no pipes or single pipe to
3592 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3593 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3594 */
3595 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3596 {
3597 struct drm_device *dev = crtc->base.dev;
3598 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3599
3600 /* We want to get the other_active_crtc only if there's only 1 other
3601 * active crtc. */
3602 list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3603 if (!crtc_it->active || crtc_it == crtc)
3604 continue;
3605
3606 if (other_active_crtc)
3607 return;
3608
3609 other_active_crtc = crtc_it;
3610 }
3611 if (!other_active_crtc)
3612 return;
3613
3614 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3615 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3616 }
3617
3618 static void haswell_crtc_enable(struct drm_crtc *crtc)
3619 {
3620 struct drm_device *dev = crtc->dev;
3621 struct drm_i915_private *dev_priv = dev->dev_private;
3622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3623 struct intel_encoder *encoder;
3624 int pipe = intel_crtc->pipe;
3625
3626 WARN_ON(!crtc->enabled);
3627
3628 if (intel_crtc->active)
3629 return;
3630
3631 intel_crtc->active = true;
3632
3633 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3634 if (intel_crtc->config.has_pch_encoder)
3635 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3636
3637 if (intel_crtc->config.has_pch_encoder)
3638 dev_priv->display.fdi_link_train(crtc);
3639
3640 for_each_encoder_on_crtc(dev, crtc, encoder)
3641 if (encoder->pre_enable)
3642 encoder->pre_enable(encoder);
3643
3644 intel_ddi_enable_pipe_clock(intel_crtc);
3645
3646 ironlake_pfit_enable(intel_crtc);
3647
3648 /*
3649 * On ILK+ LUT must be loaded before the pipe is running but with
3650 * clocks enabled
3651 */
3652 intel_crtc_load_lut(crtc);
3653
3654 intel_ddi_set_pipe_settings(crtc);
3655 intel_ddi_enable_transcoder_func(crtc);
3656
3657 intel_update_watermarks(crtc);
3658 intel_enable_pipe(dev_priv, pipe,
3659 intel_crtc->config.has_pch_encoder, false);
3660
3661 if (intel_crtc->config.has_pch_encoder)
3662 lpt_pch_enable(crtc);
3663
3664 for_each_encoder_on_crtc(dev, crtc, encoder) {
3665 encoder->enable(encoder);
3666 intel_opregion_notify_encoder(encoder, true);
3667 }
3668
3669 /* If we change the relative order between pipe/planes enabling, we need
3670 * to change the workaround. */
3671 haswell_mode_set_planes_workaround(intel_crtc);
3672 haswell_crtc_enable_planes(crtc);
3673
3674 /*
3675 * There seems to be a race in PCH platform hw (at least on some
3676 * outputs) where an enabled pipe still completes any pageflip right
3677 * away (as if the pipe is off) instead of waiting for vblank. As soon
3678 * as the first vblank happend, everything works as expected. Hence just
3679 * wait for one vblank before returning to avoid strange things
3680 * happening.
3681 */
3682 intel_wait_for_vblank(dev, intel_crtc->pipe);
3683 }
3684
3685 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3686 {
3687 struct drm_device *dev = crtc->base.dev;
3688 struct drm_i915_private *dev_priv = dev->dev_private;
3689 int pipe = crtc->pipe;
3690
3691 /* To avoid upsetting the power well on haswell only disable the pfit if
3692 * it's in use. The hw state code will make sure we get this right. */
3693 if (crtc->config.pch_pfit.enabled) {
3694 I915_WRITE(PF_CTL(pipe), 0);
3695 I915_WRITE(PF_WIN_POS(pipe), 0);
3696 I915_WRITE(PF_WIN_SZ(pipe), 0);
3697 }
3698 }
3699
3700 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3701 {
3702 struct drm_device *dev = crtc->dev;
3703 struct drm_i915_private *dev_priv = dev->dev_private;
3704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3705 struct intel_encoder *encoder;
3706 int pipe = intel_crtc->pipe;
3707 int plane = intel_crtc->plane;
3708 u32 reg, temp;
3709
3710
3711 if (!intel_crtc->active)
3712 return;
3713
3714 for_each_encoder_on_crtc(dev, crtc, encoder)
3715 encoder->disable(encoder);
3716
3717 intel_crtc_wait_for_pending_flips(crtc);
3718 drm_vblank_off(dev, pipe);
3719
3720 if (dev_priv->fbc.plane == plane)
3721 intel_disable_fbc(dev);
3722
3723 intel_crtc_update_cursor(crtc, false);
3724 intel_disable_planes(crtc);
3725 intel_disable_primary_plane(dev_priv, plane, pipe);
3726
3727 if (intel_crtc->config.has_pch_encoder)
3728 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3729
3730 intel_disable_pipe(dev_priv, pipe);
3731
3732 ironlake_pfit_disable(intel_crtc);
3733
3734 for_each_encoder_on_crtc(dev, crtc, encoder)
3735 if (encoder->post_disable)
3736 encoder->post_disable(encoder);
3737
3738 if (intel_crtc->config.has_pch_encoder) {
3739 ironlake_fdi_disable(crtc);
3740
3741 ironlake_disable_pch_transcoder(dev_priv, pipe);
3742 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3743
3744 if (HAS_PCH_CPT(dev)) {
3745 /* disable TRANS_DP_CTL */
3746 reg = TRANS_DP_CTL(pipe);
3747 temp = I915_READ(reg);
3748 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3749 TRANS_DP_PORT_SEL_MASK);
3750 temp |= TRANS_DP_PORT_SEL_NONE;
3751 I915_WRITE(reg, temp);
3752
3753 /* disable DPLL_SEL */
3754 temp = I915_READ(PCH_DPLL_SEL);
3755 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3756 I915_WRITE(PCH_DPLL_SEL, temp);
3757 }
3758
3759 /* disable PCH DPLL */
3760 intel_disable_shared_dpll(intel_crtc);
3761
3762 ironlake_fdi_pll_disable(intel_crtc);
3763 }
3764
3765 intel_crtc->active = false;
3766 intel_update_watermarks(crtc);
3767
3768 mutex_lock(&dev->struct_mutex);
3769 intel_update_fbc(dev);
3770 mutex_unlock(&dev->struct_mutex);
3771 }
3772
3773 static void haswell_crtc_disable(struct drm_crtc *crtc)
3774 {
3775 struct drm_device *dev = crtc->dev;
3776 struct drm_i915_private *dev_priv = dev->dev_private;
3777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3778 struct intel_encoder *encoder;
3779 int pipe = intel_crtc->pipe;
3780 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3781
3782 if (!intel_crtc->active)
3783 return;
3784
3785 haswell_crtc_disable_planes(crtc);
3786
3787 for_each_encoder_on_crtc(dev, crtc, encoder) {
3788 intel_opregion_notify_encoder(encoder, false);
3789 encoder->disable(encoder);
3790 }
3791
3792 if (intel_crtc->config.has_pch_encoder)
3793 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3794 intel_disable_pipe(dev_priv, pipe);
3795
3796 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3797
3798 ironlake_pfit_disable(intel_crtc);
3799
3800 intel_ddi_disable_pipe_clock(intel_crtc);
3801
3802 for_each_encoder_on_crtc(dev, crtc, encoder)
3803 if (encoder->post_disable)
3804 encoder->post_disable(encoder);
3805
3806 if (intel_crtc->config.has_pch_encoder) {
3807 lpt_disable_pch_transcoder(dev_priv);
3808 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3809 intel_ddi_fdi_disable(crtc);
3810 }
3811
3812 intel_crtc->active = false;
3813 intel_update_watermarks(crtc);
3814
3815 mutex_lock(&dev->struct_mutex);
3816 intel_update_fbc(dev);
3817 mutex_unlock(&dev->struct_mutex);
3818 }
3819
3820 static void ironlake_crtc_off(struct drm_crtc *crtc)
3821 {
3822 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3823 intel_put_shared_dpll(intel_crtc);
3824 }
3825
3826 static void haswell_crtc_off(struct drm_crtc *crtc)
3827 {
3828 intel_ddi_put_crtc_pll(crtc);
3829 }
3830
3831 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3832 {
3833 if (!enable && intel_crtc->overlay) {
3834 struct drm_device *dev = intel_crtc->base.dev;
3835 struct drm_i915_private *dev_priv = dev->dev_private;
3836
3837 mutex_lock(&dev->struct_mutex);
3838 dev_priv->mm.interruptible = false;
3839 (void) intel_overlay_switch_off(intel_crtc->overlay);
3840 dev_priv->mm.interruptible = true;
3841 mutex_unlock(&dev->struct_mutex);
3842 }
3843
3844 /* Let userspace switch the overlay on again. In most cases userspace
3845 * has to recompute where to put it anyway.
3846 */
3847 }
3848
3849 /**
3850 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3851 * cursor plane briefly if not already running after enabling the display
3852 * plane.
3853 * This workaround avoids occasional blank screens when self refresh is
3854 * enabled.
3855 */
3856 static void
3857 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3858 {
3859 u32 cntl = I915_READ(CURCNTR(pipe));
3860
3861 if ((cntl & CURSOR_MODE) == 0) {
3862 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3863
3864 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3865 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3866 intel_wait_for_vblank(dev_priv->dev, pipe);
3867 I915_WRITE(CURCNTR(pipe), cntl);
3868 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3869 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3870 }
3871 }
3872
3873 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3874 {
3875 struct drm_device *dev = crtc->base.dev;
3876 struct drm_i915_private *dev_priv = dev->dev_private;
3877 struct intel_crtc_config *pipe_config = &crtc->config;
3878
3879 if (!crtc->config.gmch_pfit.control)
3880 return;
3881
3882 /*
3883 * The panel fitter should only be adjusted whilst the pipe is disabled,
3884 * according to register description and PRM.
3885 */
3886 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3887 assert_pipe_disabled(dev_priv, crtc->pipe);
3888
3889 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3890 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3891
3892 /* Border color in case we don't scale up to the full screen. Black by
3893 * default, change to something else for debugging. */
3894 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3895 }
3896
3897 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3898 {
3899 struct drm_device *dev = crtc->dev;
3900 struct drm_i915_private *dev_priv = dev->dev_private;
3901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3902 struct intel_encoder *encoder;
3903 int pipe = intel_crtc->pipe;
3904 int plane = intel_crtc->plane;
3905 bool is_dsi;
3906
3907 WARN_ON(!crtc->enabled);
3908
3909 if (intel_crtc->active)
3910 return;
3911
3912 intel_crtc->active = true;
3913
3914 for_each_encoder_on_crtc(dev, crtc, encoder)
3915 if (encoder->pre_pll_enable)
3916 encoder->pre_pll_enable(encoder);
3917
3918 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3919
3920 if (!is_dsi)
3921 vlv_enable_pll(intel_crtc);
3922
3923 for_each_encoder_on_crtc(dev, crtc, encoder)
3924 if (encoder->pre_enable)
3925 encoder->pre_enable(encoder);
3926
3927 i9xx_pfit_enable(intel_crtc);
3928
3929 intel_crtc_load_lut(crtc);
3930
3931 intel_update_watermarks(crtc);
3932 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
3933 intel_enable_primary_plane(dev_priv, plane, pipe);
3934 intel_enable_planes(crtc);
3935 intel_crtc_update_cursor(crtc, true);
3936
3937 intel_update_fbc(dev);
3938
3939 for_each_encoder_on_crtc(dev, crtc, encoder)
3940 encoder->enable(encoder);
3941 }
3942
3943 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3944 {
3945 struct drm_device *dev = crtc->dev;
3946 struct drm_i915_private *dev_priv = dev->dev_private;
3947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3948 struct intel_encoder *encoder;
3949 int pipe = intel_crtc->pipe;
3950 int plane = intel_crtc->plane;
3951
3952 WARN_ON(!crtc->enabled);
3953
3954 if (intel_crtc->active)
3955 return;
3956
3957 intel_crtc->active = true;
3958
3959 for_each_encoder_on_crtc(dev, crtc, encoder)
3960 if (encoder->pre_enable)
3961 encoder->pre_enable(encoder);
3962
3963 i9xx_enable_pll(intel_crtc);
3964
3965 i9xx_pfit_enable(intel_crtc);
3966
3967 intel_crtc_load_lut(crtc);
3968
3969 intel_update_watermarks(crtc);
3970 intel_enable_pipe(dev_priv, pipe, false, false);
3971 intel_enable_primary_plane(dev_priv, plane, pipe);
3972 intel_enable_planes(crtc);
3973 /* The fixup needs to happen before cursor is enabled */
3974 if (IS_G4X(dev))
3975 g4x_fixup_plane(dev_priv, pipe);
3976 intel_crtc_update_cursor(crtc, true);
3977
3978 /* Give the overlay scaler a chance to enable if it's on this pipe */
3979 intel_crtc_dpms_overlay(intel_crtc, true);
3980
3981 intel_update_fbc(dev);
3982
3983 for_each_encoder_on_crtc(dev, crtc, encoder)
3984 encoder->enable(encoder);
3985 }
3986
3987 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3988 {
3989 struct drm_device *dev = crtc->base.dev;
3990 struct drm_i915_private *dev_priv = dev->dev_private;
3991
3992 if (!crtc->config.gmch_pfit.control)
3993 return;
3994
3995 assert_pipe_disabled(dev_priv, crtc->pipe);
3996
3997 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3998 I915_READ(PFIT_CONTROL));
3999 I915_WRITE(PFIT_CONTROL, 0);
4000 }
4001
4002 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4003 {
4004 struct drm_device *dev = crtc->dev;
4005 struct drm_i915_private *dev_priv = dev->dev_private;
4006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4007 struct intel_encoder *encoder;
4008 int pipe = intel_crtc->pipe;
4009 int plane = intel_crtc->plane;
4010
4011 if (!intel_crtc->active)
4012 return;
4013
4014 for_each_encoder_on_crtc(dev, crtc, encoder)
4015 encoder->disable(encoder);
4016
4017 /* Give the overlay scaler a chance to disable if it's on this pipe */
4018 intel_crtc_wait_for_pending_flips(crtc);
4019 drm_vblank_off(dev, pipe);
4020
4021 if (dev_priv->fbc.plane == plane)
4022 intel_disable_fbc(dev);
4023
4024 intel_crtc_dpms_overlay(intel_crtc, false);
4025 intel_crtc_update_cursor(crtc, false);
4026 intel_disable_planes(crtc);
4027 intel_disable_primary_plane(dev_priv, plane, pipe);
4028
4029 intel_disable_pipe(dev_priv, pipe);
4030
4031 i9xx_pfit_disable(intel_crtc);
4032
4033 for_each_encoder_on_crtc(dev, crtc, encoder)
4034 if (encoder->post_disable)
4035 encoder->post_disable(encoder);
4036
4037 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4038 vlv_disable_pll(dev_priv, pipe);
4039 else if (!IS_VALLEYVIEW(dev))
4040 i9xx_disable_pll(dev_priv, pipe);
4041
4042 intel_crtc->active = false;
4043 intel_update_watermarks(crtc);
4044
4045 intel_update_fbc(dev);
4046 }
4047
4048 static void i9xx_crtc_off(struct drm_crtc *crtc)
4049 {
4050 }
4051
4052 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4053 bool enabled)
4054 {
4055 struct drm_device *dev = crtc->dev;
4056 struct drm_i915_master_private *master_priv;
4057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4058 int pipe = intel_crtc->pipe;
4059
4060 if (!dev->primary->master)
4061 return;
4062
4063 master_priv = dev->primary->master->driver_priv;
4064 if (!master_priv->sarea_priv)
4065 return;
4066
4067 switch (pipe) {
4068 case 0:
4069 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4070 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4071 break;
4072 case 1:
4073 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4074 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4075 break;
4076 default:
4077 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4078 break;
4079 }
4080 }
4081
4082 /**
4083 * Sets the power management mode of the pipe and plane.
4084 */
4085 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4086 {
4087 struct drm_device *dev = crtc->dev;
4088 struct drm_i915_private *dev_priv = dev->dev_private;
4089 struct intel_encoder *intel_encoder;
4090 bool enable = false;
4091
4092 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4093 enable |= intel_encoder->connectors_active;
4094
4095 if (enable)
4096 dev_priv->display.crtc_enable(crtc);
4097 else
4098 dev_priv->display.crtc_disable(crtc);
4099
4100 intel_crtc_update_sarea(crtc, enable);
4101 }
4102
4103 static void intel_crtc_disable(struct drm_crtc *crtc)
4104 {
4105 struct drm_device *dev = crtc->dev;
4106 struct drm_connector *connector;
4107 struct drm_i915_private *dev_priv = dev->dev_private;
4108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4109
4110 /* crtc should still be enabled when we disable it. */
4111 WARN_ON(!crtc->enabled);
4112
4113 dev_priv->display.crtc_disable(crtc);
4114 intel_crtc->eld_vld = false;
4115 intel_crtc_update_sarea(crtc, false);
4116 dev_priv->display.off(crtc);
4117
4118 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4119 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4120 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4121
4122 if (crtc->fb) {
4123 mutex_lock(&dev->struct_mutex);
4124 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4125 mutex_unlock(&dev->struct_mutex);
4126 crtc->fb = NULL;
4127 }
4128
4129 /* Update computed state. */
4130 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4131 if (!connector->encoder || !connector->encoder->crtc)
4132 continue;
4133
4134 if (connector->encoder->crtc != crtc)
4135 continue;
4136
4137 connector->dpms = DRM_MODE_DPMS_OFF;
4138 to_intel_encoder(connector->encoder)->connectors_active = false;
4139 }
4140 }
4141
4142 void intel_encoder_destroy(struct drm_encoder *encoder)
4143 {
4144 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4145
4146 drm_encoder_cleanup(encoder);
4147 kfree(intel_encoder);
4148 }
4149
4150 /* Simple dpms helper for encoders with just one connector, no cloning and only
4151 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4152 * state of the entire output pipe. */
4153 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4154 {
4155 if (mode == DRM_MODE_DPMS_ON) {
4156 encoder->connectors_active = true;
4157
4158 intel_crtc_update_dpms(encoder->base.crtc);
4159 } else {
4160 encoder->connectors_active = false;
4161
4162 intel_crtc_update_dpms(encoder->base.crtc);
4163 }
4164 }
4165
4166 /* Cross check the actual hw state with our own modeset state tracking (and it's
4167 * internal consistency). */
4168 static void intel_connector_check_state(struct intel_connector *connector)
4169 {
4170 if (connector->get_hw_state(connector)) {
4171 struct intel_encoder *encoder = connector->encoder;
4172 struct drm_crtc *crtc;
4173 bool encoder_enabled;
4174 enum pipe pipe;
4175
4176 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4177 connector->base.base.id,
4178 drm_get_connector_name(&connector->base));
4179
4180 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4181 "wrong connector dpms state\n");
4182 WARN(connector->base.encoder != &encoder->base,
4183 "active connector not linked to encoder\n");
4184 WARN(!encoder->connectors_active,
4185 "encoder->connectors_active not set\n");
4186
4187 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4188 WARN(!encoder_enabled, "encoder not enabled\n");
4189 if (WARN_ON(!encoder->base.crtc))
4190 return;
4191
4192 crtc = encoder->base.crtc;
4193
4194 WARN(!crtc->enabled, "crtc not enabled\n");
4195 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4196 WARN(pipe != to_intel_crtc(crtc)->pipe,
4197 "encoder active on the wrong pipe\n");
4198 }
4199 }
4200
4201 /* Even simpler default implementation, if there's really no special case to
4202 * consider. */
4203 void intel_connector_dpms(struct drm_connector *connector, int mode)
4204 {
4205 /* All the simple cases only support two dpms states. */
4206 if (mode != DRM_MODE_DPMS_ON)
4207 mode = DRM_MODE_DPMS_OFF;
4208
4209 if (mode == connector->dpms)
4210 return;
4211
4212 connector->dpms = mode;
4213
4214 /* Only need to change hw state when actually enabled */
4215 if (connector->encoder)
4216 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4217
4218 intel_modeset_check_state(connector->dev);
4219 }
4220
4221 /* Simple connector->get_hw_state implementation for encoders that support only
4222 * one connector and no cloning and hence the encoder state determines the state
4223 * of the connector. */
4224 bool intel_connector_get_hw_state(struct intel_connector *connector)
4225 {
4226 enum pipe pipe = 0;
4227 struct intel_encoder *encoder = connector->encoder;
4228
4229 return encoder->get_hw_state(encoder, &pipe);
4230 }
4231
4232 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4233 struct intel_crtc_config *pipe_config)
4234 {
4235 struct drm_i915_private *dev_priv = dev->dev_private;
4236 struct intel_crtc *pipe_B_crtc =
4237 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4238
4239 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4240 pipe_name(pipe), pipe_config->fdi_lanes);
4241 if (pipe_config->fdi_lanes > 4) {
4242 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4243 pipe_name(pipe), pipe_config->fdi_lanes);
4244 return false;
4245 }
4246
4247 if (IS_HASWELL(dev)) {
4248 if (pipe_config->fdi_lanes > 2) {
4249 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4250 pipe_config->fdi_lanes);
4251 return false;
4252 } else {
4253 return true;
4254 }
4255 }
4256
4257 if (INTEL_INFO(dev)->num_pipes == 2)
4258 return true;
4259
4260 /* Ivybridge 3 pipe is really complicated */
4261 switch (pipe) {
4262 case PIPE_A:
4263 return true;
4264 case PIPE_B:
4265 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4266 pipe_config->fdi_lanes > 2) {
4267 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4268 pipe_name(pipe), pipe_config->fdi_lanes);
4269 return false;
4270 }
4271 return true;
4272 case PIPE_C:
4273 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4274 pipe_B_crtc->config.fdi_lanes <= 2) {
4275 if (pipe_config->fdi_lanes > 2) {
4276 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4277 pipe_name(pipe), pipe_config->fdi_lanes);
4278 return false;
4279 }
4280 } else {
4281 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4282 return false;
4283 }
4284 return true;
4285 default:
4286 BUG();
4287 }
4288 }
4289
4290 #define RETRY 1
4291 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4292 struct intel_crtc_config *pipe_config)
4293 {
4294 struct drm_device *dev = intel_crtc->base.dev;
4295 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4296 int lane, link_bw, fdi_dotclock;
4297 bool setup_ok, needs_recompute = false;
4298
4299 retry:
4300 /* FDI is a binary signal running at ~2.7GHz, encoding
4301 * each output octet as 10 bits. The actual frequency
4302 * is stored as a divider into a 100MHz clock, and the
4303 * mode pixel clock is stored in units of 1KHz.
4304 * Hence the bw of each lane in terms of the mode signal
4305 * is:
4306 */
4307 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4308
4309 fdi_dotclock = adjusted_mode->crtc_clock;
4310
4311 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4312 pipe_config->pipe_bpp);
4313
4314 pipe_config->fdi_lanes = lane;
4315
4316 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4317 link_bw, &pipe_config->fdi_m_n);
4318
4319 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4320 intel_crtc->pipe, pipe_config);
4321 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4322 pipe_config->pipe_bpp -= 2*3;
4323 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4324 pipe_config->pipe_bpp);
4325 needs_recompute = true;
4326 pipe_config->bw_constrained = true;
4327
4328 goto retry;
4329 }
4330
4331 if (needs_recompute)
4332 return RETRY;
4333
4334 return setup_ok ? 0 : -EINVAL;
4335 }
4336
4337 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4338 struct intel_crtc_config *pipe_config)
4339 {
4340 pipe_config->ips_enabled = i915_enable_ips &&
4341 hsw_crtc_supports_ips(crtc) &&
4342 pipe_config->pipe_bpp <= 24;
4343 }
4344
4345 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4346 struct intel_crtc_config *pipe_config)
4347 {
4348 struct drm_device *dev = crtc->base.dev;
4349 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4350
4351 /* FIXME should check pixel clock limits on all platforms */
4352 if (INTEL_INFO(dev)->gen < 4) {
4353 struct drm_i915_private *dev_priv = dev->dev_private;
4354 int clock_limit =
4355 dev_priv->display.get_display_clock_speed(dev);
4356
4357 /*
4358 * Enable pixel doubling when the dot clock
4359 * is > 90% of the (display) core speed.
4360 *
4361 * GDG double wide on either pipe,
4362 * otherwise pipe A only.
4363 */
4364 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4365 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4366 clock_limit *= 2;
4367 pipe_config->double_wide = true;
4368 }
4369
4370 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4371 return -EINVAL;
4372 }
4373
4374 /*
4375 * Pipe horizontal size must be even in:
4376 * - DVO ganged mode
4377 * - LVDS dual channel mode
4378 * - Double wide pipe
4379 */
4380 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4381 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4382 pipe_config->pipe_src_w &= ~1;
4383
4384 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4385 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4386 */
4387 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4388 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4389 return -EINVAL;
4390
4391 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4392 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4393 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4394 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4395 * for lvds. */
4396 pipe_config->pipe_bpp = 8*3;
4397 }
4398
4399 if (HAS_IPS(dev))
4400 hsw_compute_ips_config(crtc, pipe_config);
4401
4402 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4403 * clock survives for now. */
4404 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4405 pipe_config->shared_dpll = crtc->config.shared_dpll;
4406
4407 if (pipe_config->has_pch_encoder)
4408 return ironlake_fdi_compute_config(crtc, pipe_config);
4409
4410 return 0;
4411 }
4412
4413 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4414 {
4415 return 400000; /* FIXME */
4416 }
4417
4418 static int i945_get_display_clock_speed(struct drm_device *dev)
4419 {
4420 return 400000;
4421 }
4422
4423 static int i915_get_display_clock_speed(struct drm_device *dev)
4424 {
4425 return 333000;
4426 }
4427
4428 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4429 {
4430 return 200000;
4431 }
4432
4433 static int pnv_get_display_clock_speed(struct drm_device *dev)
4434 {
4435 u16 gcfgc = 0;
4436
4437 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4438
4439 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4440 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4441 return 267000;
4442 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4443 return 333000;
4444 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4445 return 444000;
4446 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4447 return 200000;
4448 default:
4449 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4450 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4451 return 133000;
4452 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4453 return 167000;
4454 }
4455 }
4456
4457 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4458 {
4459 u16 gcfgc = 0;
4460
4461 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4462
4463 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4464 return 133000;
4465 else {
4466 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4467 case GC_DISPLAY_CLOCK_333_MHZ:
4468 return 333000;
4469 default:
4470 case GC_DISPLAY_CLOCK_190_200_MHZ:
4471 return 190000;
4472 }
4473 }
4474 }
4475
4476 static int i865_get_display_clock_speed(struct drm_device *dev)
4477 {
4478 return 266000;
4479 }
4480
4481 static int i855_get_display_clock_speed(struct drm_device *dev)
4482 {
4483 u16 hpllcc = 0;
4484 /* Assume that the hardware is in the high speed state. This
4485 * should be the default.
4486 */
4487 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4488 case GC_CLOCK_133_200:
4489 case GC_CLOCK_100_200:
4490 return 200000;
4491 case GC_CLOCK_166_250:
4492 return 250000;
4493 case GC_CLOCK_100_133:
4494 return 133000;
4495 }
4496
4497 /* Shouldn't happen */
4498 return 0;
4499 }
4500
4501 static int i830_get_display_clock_speed(struct drm_device *dev)
4502 {
4503 return 133000;
4504 }
4505
4506 static void
4507 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4508 {
4509 while (*num > DATA_LINK_M_N_MASK ||
4510 *den > DATA_LINK_M_N_MASK) {
4511 *num >>= 1;
4512 *den >>= 1;
4513 }
4514 }
4515
4516 static void compute_m_n(unsigned int m, unsigned int n,
4517 uint32_t *ret_m, uint32_t *ret_n)
4518 {
4519 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4520 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4521 intel_reduce_m_n_ratio(ret_m, ret_n);
4522 }
4523
4524 void
4525 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4526 int pixel_clock, int link_clock,
4527 struct intel_link_m_n *m_n)
4528 {
4529 m_n->tu = 64;
4530
4531 compute_m_n(bits_per_pixel * pixel_clock,
4532 link_clock * nlanes * 8,
4533 &m_n->gmch_m, &m_n->gmch_n);
4534
4535 compute_m_n(pixel_clock, link_clock,
4536 &m_n->link_m, &m_n->link_n);
4537 }
4538
4539 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4540 {
4541 if (i915_panel_use_ssc >= 0)
4542 return i915_panel_use_ssc != 0;
4543 return dev_priv->vbt.lvds_use_ssc
4544 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4545 }
4546
4547 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4548 {
4549 struct drm_device *dev = crtc->dev;
4550 struct drm_i915_private *dev_priv = dev->dev_private;
4551 int refclk;
4552
4553 if (IS_VALLEYVIEW(dev)) {
4554 refclk = 100000;
4555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4556 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4557 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4558 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4559 refclk / 1000);
4560 } else if (!IS_GEN2(dev)) {
4561 refclk = 96000;
4562 } else {
4563 refclk = 48000;
4564 }
4565
4566 return refclk;
4567 }
4568
4569 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4570 {
4571 return (1 << dpll->n) << 16 | dpll->m2;
4572 }
4573
4574 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4575 {
4576 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4577 }
4578
4579 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4580 intel_clock_t *reduced_clock)
4581 {
4582 struct drm_device *dev = crtc->base.dev;
4583 struct drm_i915_private *dev_priv = dev->dev_private;
4584 int pipe = crtc->pipe;
4585 u32 fp, fp2 = 0;
4586
4587 if (IS_PINEVIEW(dev)) {
4588 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4589 if (reduced_clock)
4590 fp2 = pnv_dpll_compute_fp(reduced_clock);
4591 } else {
4592 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4593 if (reduced_clock)
4594 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4595 }
4596
4597 I915_WRITE(FP0(pipe), fp);
4598 crtc->config.dpll_hw_state.fp0 = fp;
4599
4600 crtc->lowfreq_avail = false;
4601 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4602 reduced_clock && i915_powersave) {
4603 I915_WRITE(FP1(pipe), fp2);
4604 crtc->config.dpll_hw_state.fp1 = fp2;
4605 crtc->lowfreq_avail = true;
4606 } else {
4607 I915_WRITE(FP1(pipe), fp);
4608 crtc->config.dpll_hw_state.fp1 = fp;
4609 }
4610 }
4611
4612 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4613 pipe)
4614 {
4615 u32 reg_val;
4616
4617 /*
4618 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4619 * and set it to a reasonable value instead.
4620 */
4621 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4622 reg_val &= 0xffffff00;
4623 reg_val |= 0x00000030;
4624 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4625
4626 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4627 reg_val &= 0x8cffffff;
4628 reg_val = 0x8c000000;
4629 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4630
4631 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4632 reg_val &= 0xffffff00;
4633 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4634
4635 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4636 reg_val &= 0x00ffffff;
4637 reg_val |= 0xb0000000;
4638 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4639 }
4640
4641 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4642 struct intel_link_m_n *m_n)
4643 {
4644 struct drm_device *dev = crtc->base.dev;
4645 struct drm_i915_private *dev_priv = dev->dev_private;
4646 int pipe = crtc->pipe;
4647
4648 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4649 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4650 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4651 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4652 }
4653
4654 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4655 struct intel_link_m_n *m_n)
4656 {
4657 struct drm_device *dev = crtc->base.dev;
4658 struct drm_i915_private *dev_priv = dev->dev_private;
4659 int pipe = crtc->pipe;
4660 enum transcoder transcoder = crtc->config.cpu_transcoder;
4661
4662 if (INTEL_INFO(dev)->gen >= 5) {
4663 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4664 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4665 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4666 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4667 } else {
4668 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4669 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4670 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4671 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4672 }
4673 }
4674
4675 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4676 {
4677 if (crtc->config.has_pch_encoder)
4678 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4679 else
4680 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4681 }
4682
4683 static void vlv_update_pll(struct intel_crtc *crtc)
4684 {
4685 struct drm_device *dev = crtc->base.dev;
4686 struct drm_i915_private *dev_priv = dev->dev_private;
4687 int pipe = crtc->pipe;
4688 u32 dpll, mdiv;
4689 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4690 u32 coreclk, reg_val, dpll_md;
4691
4692 mutex_lock(&dev_priv->dpio_lock);
4693
4694 bestn = crtc->config.dpll.n;
4695 bestm1 = crtc->config.dpll.m1;
4696 bestm2 = crtc->config.dpll.m2;
4697 bestp1 = crtc->config.dpll.p1;
4698 bestp2 = crtc->config.dpll.p2;
4699
4700 /* See eDP HDMI DPIO driver vbios notes doc */
4701
4702 /* PLL B needs special handling */
4703 if (pipe)
4704 vlv_pllb_recal_opamp(dev_priv, pipe);
4705
4706 /* Set up Tx target for periodic Rcomp update */
4707 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
4708
4709 /* Disable target IRef on PLL */
4710 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
4711 reg_val &= 0x00ffffff;
4712 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
4713
4714 /* Disable fast lock */
4715 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
4716
4717 /* Set idtafcrecal before PLL is enabled */
4718 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4719 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4720 mdiv |= ((bestn << DPIO_N_SHIFT));
4721 mdiv |= (1 << DPIO_K_SHIFT);
4722
4723 /*
4724 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4725 * but we don't support that).
4726 * Note: don't use the DAC post divider as it seems unstable.
4727 */
4728 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4729 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4730
4731 mdiv |= DPIO_ENABLE_CALIBRATION;
4732 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4733
4734 /* Set HBR and RBR LPF coefficients */
4735 if (crtc->config.port_clock == 162000 ||
4736 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4737 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4738 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4739 0x009f0003);
4740 else
4741 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4742 0x00d0000f);
4743
4744 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4745 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4746 /* Use SSC source */
4747 if (!pipe)
4748 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4749 0x0df40000);
4750 else
4751 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4752 0x0df70000);
4753 } else { /* HDMI or VGA */
4754 /* Use bend source */
4755 if (!pipe)
4756 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4757 0x0df70000);
4758 else
4759 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4760 0x0df40000);
4761 }
4762
4763 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
4764 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4765 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4766 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4767 coreclk |= 0x01000000;
4768 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
4769
4770 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
4771
4772 /* Enable DPIO clock input */
4773 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4774 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4775 /* We should never disable this, set it here for state tracking */
4776 if (pipe == PIPE_B)
4777 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4778 dpll |= DPLL_VCO_ENABLE;
4779 crtc->config.dpll_hw_state.dpll = dpll;
4780
4781 dpll_md = (crtc->config.pixel_multiplier - 1)
4782 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4783 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4784
4785 if (crtc->config.has_dp_encoder)
4786 intel_dp_set_m_n(crtc);
4787
4788 mutex_unlock(&dev_priv->dpio_lock);
4789 }
4790
4791 static void i9xx_update_pll(struct intel_crtc *crtc,
4792 intel_clock_t *reduced_clock,
4793 int num_connectors)
4794 {
4795 struct drm_device *dev = crtc->base.dev;
4796 struct drm_i915_private *dev_priv = dev->dev_private;
4797 u32 dpll;
4798 bool is_sdvo;
4799 struct dpll *clock = &crtc->config.dpll;
4800
4801 i9xx_update_pll_dividers(crtc, reduced_clock);
4802
4803 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4804 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4805
4806 dpll = DPLL_VGA_MODE_DIS;
4807
4808 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4809 dpll |= DPLLB_MODE_LVDS;
4810 else
4811 dpll |= DPLLB_MODE_DAC_SERIAL;
4812
4813 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4814 dpll |= (crtc->config.pixel_multiplier - 1)
4815 << SDVO_MULTIPLIER_SHIFT_HIRES;
4816 }
4817
4818 if (is_sdvo)
4819 dpll |= DPLL_SDVO_HIGH_SPEED;
4820
4821 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4822 dpll |= DPLL_SDVO_HIGH_SPEED;
4823
4824 /* compute bitmask from p1 value */
4825 if (IS_PINEVIEW(dev))
4826 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4827 else {
4828 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4829 if (IS_G4X(dev) && reduced_clock)
4830 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4831 }
4832 switch (clock->p2) {
4833 case 5:
4834 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4835 break;
4836 case 7:
4837 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4838 break;
4839 case 10:
4840 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4841 break;
4842 case 14:
4843 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4844 break;
4845 }
4846 if (INTEL_INFO(dev)->gen >= 4)
4847 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4848
4849 if (crtc->config.sdvo_tv_clock)
4850 dpll |= PLL_REF_INPUT_TVCLKINBC;
4851 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4852 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4853 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4854 else
4855 dpll |= PLL_REF_INPUT_DREFCLK;
4856
4857 dpll |= DPLL_VCO_ENABLE;
4858 crtc->config.dpll_hw_state.dpll = dpll;
4859
4860 if (INTEL_INFO(dev)->gen >= 4) {
4861 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4862 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4863 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4864 }
4865
4866 if (crtc->config.has_dp_encoder)
4867 intel_dp_set_m_n(crtc);
4868 }
4869
4870 static void i8xx_update_pll(struct intel_crtc *crtc,
4871 intel_clock_t *reduced_clock,
4872 int num_connectors)
4873 {
4874 struct drm_device *dev = crtc->base.dev;
4875 struct drm_i915_private *dev_priv = dev->dev_private;
4876 u32 dpll;
4877 struct dpll *clock = &crtc->config.dpll;
4878
4879 i9xx_update_pll_dividers(crtc, reduced_clock);
4880
4881 dpll = DPLL_VGA_MODE_DIS;
4882
4883 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4884 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4885 } else {
4886 if (clock->p1 == 2)
4887 dpll |= PLL_P1_DIVIDE_BY_TWO;
4888 else
4889 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4890 if (clock->p2 == 4)
4891 dpll |= PLL_P2_DIVIDE_BY_4;
4892 }
4893
4894 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4895 dpll |= DPLL_DVO_2X_MODE;
4896
4897 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4898 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4899 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4900 else
4901 dpll |= PLL_REF_INPUT_DREFCLK;
4902
4903 dpll |= DPLL_VCO_ENABLE;
4904 crtc->config.dpll_hw_state.dpll = dpll;
4905 }
4906
4907 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4908 {
4909 struct drm_device *dev = intel_crtc->base.dev;
4910 struct drm_i915_private *dev_priv = dev->dev_private;
4911 enum pipe pipe = intel_crtc->pipe;
4912 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4913 struct drm_display_mode *adjusted_mode =
4914 &intel_crtc->config.adjusted_mode;
4915 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4916
4917 /* We need to be careful not to changed the adjusted mode, for otherwise
4918 * the hw state checker will get angry at the mismatch. */
4919 crtc_vtotal = adjusted_mode->crtc_vtotal;
4920 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4921
4922 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4923 /* the chip adds 2 halflines automatically */
4924 crtc_vtotal -= 1;
4925 crtc_vblank_end -= 1;
4926 vsyncshift = adjusted_mode->crtc_hsync_start
4927 - adjusted_mode->crtc_htotal / 2;
4928 } else {
4929 vsyncshift = 0;
4930 }
4931
4932 if (INTEL_INFO(dev)->gen > 3)
4933 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4934
4935 I915_WRITE(HTOTAL(cpu_transcoder),
4936 (adjusted_mode->crtc_hdisplay - 1) |
4937 ((adjusted_mode->crtc_htotal - 1) << 16));
4938 I915_WRITE(HBLANK(cpu_transcoder),
4939 (adjusted_mode->crtc_hblank_start - 1) |
4940 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4941 I915_WRITE(HSYNC(cpu_transcoder),
4942 (adjusted_mode->crtc_hsync_start - 1) |
4943 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4944
4945 I915_WRITE(VTOTAL(cpu_transcoder),
4946 (adjusted_mode->crtc_vdisplay - 1) |
4947 ((crtc_vtotal - 1) << 16));
4948 I915_WRITE(VBLANK(cpu_transcoder),
4949 (adjusted_mode->crtc_vblank_start - 1) |
4950 ((crtc_vblank_end - 1) << 16));
4951 I915_WRITE(VSYNC(cpu_transcoder),
4952 (adjusted_mode->crtc_vsync_start - 1) |
4953 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4954
4955 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4956 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4957 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4958 * bits. */
4959 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4960 (pipe == PIPE_B || pipe == PIPE_C))
4961 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4962
4963 /* pipesrc controls the size that is scaled from, which should
4964 * always be the user's requested size.
4965 */
4966 I915_WRITE(PIPESRC(pipe),
4967 ((intel_crtc->config.pipe_src_w - 1) << 16) |
4968 (intel_crtc->config.pipe_src_h - 1));
4969 }
4970
4971 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4972 struct intel_crtc_config *pipe_config)
4973 {
4974 struct drm_device *dev = crtc->base.dev;
4975 struct drm_i915_private *dev_priv = dev->dev_private;
4976 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4977 uint32_t tmp;
4978
4979 tmp = I915_READ(HTOTAL(cpu_transcoder));
4980 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4981 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4982 tmp = I915_READ(HBLANK(cpu_transcoder));
4983 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4984 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4985 tmp = I915_READ(HSYNC(cpu_transcoder));
4986 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4987 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4988
4989 tmp = I915_READ(VTOTAL(cpu_transcoder));
4990 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4991 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4992 tmp = I915_READ(VBLANK(cpu_transcoder));
4993 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4994 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4995 tmp = I915_READ(VSYNC(cpu_transcoder));
4996 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4997 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4998
4999 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5000 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5001 pipe_config->adjusted_mode.crtc_vtotal += 1;
5002 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5003 }
5004
5005 tmp = I915_READ(PIPESRC(crtc->pipe));
5006 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5007 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5008
5009 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5010 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5011 }
5012
5013 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
5014 struct intel_crtc_config *pipe_config)
5015 {
5016 struct drm_crtc *crtc = &intel_crtc->base;
5017
5018 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5019 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
5020 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5021 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5022
5023 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5024 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5025 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5026 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5027
5028 crtc->mode.flags = pipe_config->adjusted_mode.flags;
5029
5030 crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
5031 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
5032 }
5033
5034 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5035 {
5036 struct drm_device *dev = intel_crtc->base.dev;
5037 struct drm_i915_private *dev_priv = dev->dev_private;
5038 uint32_t pipeconf;
5039
5040 pipeconf = 0;
5041
5042 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5043 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5044 pipeconf |= PIPECONF_ENABLE;
5045
5046 if (intel_crtc->config.double_wide)
5047 pipeconf |= PIPECONF_DOUBLE_WIDE;
5048
5049 /* only g4x and later have fancy bpc/dither controls */
5050 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5051 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5052 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5053 pipeconf |= PIPECONF_DITHER_EN |
5054 PIPECONF_DITHER_TYPE_SP;
5055
5056 switch (intel_crtc->config.pipe_bpp) {
5057 case 18:
5058 pipeconf |= PIPECONF_6BPC;
5059 break;
5060 case 24:
5061 pipeconf |= PIPECONF_8BPC;
5062 break;
5063 case 30:
5064 pipeconf |= PIPECONF_10BPC;
5065 break;
5066 default:
5067 /* Case prevented by intel_choose_pipe_bpp_dither. */
5068 BUG();
5069 }
5070 }
5071
5072 if (HAS_PIPE_CXSR(dev)) {
5073 if (intel_crtc->lowfreq_avail) {
5074 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5075 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5076 } else {
5077 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5078 }
5079 }
5080
5081 if (!IS_GEN2(dev) &&
5082 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5083 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5084 else
5085 pipeconf |= PIPECONF_PROGRESSIVE;
5086
5087 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5088 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5089
5090 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5091 POSTING_READ(PIPECONF(intel_crtc->pipe));
5092 }
5093
5094 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5095 int x, int y,
5096 struct drm_framebuffer *fb)
5097 {
5098 struct drm_device *dev = crtc->dev;
5099 struct drm_i915_private *dev_priv = dev->dev_private;
5100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5101 int pipe = intel_crtc->pipe;
5102 int plane = intel_crtc->plane;
5103 int refclk, num_connectors = 0;
5104 intel_clock_t clock, reduced_clock;
5105 u32 dspcntr;
5106 bool ok, has_reduced_clock = false;
5107 bool is_lvds = false, is_dsi = false;
5108 struct intel_encoder *encoder;
5109 const intel_limit_t *limit;
5110 int ret;
5111
5112 for_each_encoder_on_crtc(dev, crtc, encoder) {
5113 switch (encoder->type) {
5114 case INTEL_OUTPUT_LVDS:
5115 is_lvds = true;
5116 break;
5117 case INTEL_OUTPUT_DSI:
5118 is_dsi = true;
5119 break;
5120 }
5121
5122 num_connectors++;
5123 }
5124
5125 if (is_dsi)
5126 goto skip_dpll;
5127
5128 if (!intel_crtc->config.clock_set) {
5129 refclk = i9xx_get_refclk(crtc, num_connectors);
5130
5131 /*
5132 * Returns a set of divisors for the desired target clock with
5133 * the given refclk, or FALSE. The returned values represent
5134 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5135 * 2) / p1 / p2.
5136 */
5137 limit = intel_limit(crtc, refclk);
5138 ok = dev_priv->display.find_dpll(limit, crtc,
5139 intel_crtc->config.port_clock,
5140 refclk, NULL, &clock);
5141 if (!ok) {
5142 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5143 return -EINVAL;
5144 }
5145
5146 if (is_lvds && dev_priv->lvds_downclock_avail) {
5147 /*
5148 * Ensure we match the reduced clock's P to the target
5149 * clock. If the clocks don't match, we can't switch
5150 * the display clock by using the FP0/FP1. In such case
5151 * we will disable the LVDS downclock feature.
5152 */
5153 has_reduced_clock =
5154 dev_priv->display.find_dpll(limit, crtc,
5155 dev_priv->lvds_downclock,
5156 refclk, &clock,
5157 &reduced_clock);
5158 }
5159 /* Compat-code for transition, will disappear. */
5160 intel_crtc->config.dpll.n = clock.n;
5161 intel_crtc->config.dpll.m1 = clock.m1;
5162 intel_crtc->config.dpll.m2 = clock.m2;
5163 intel_crtc->config.dpll.p1 = clock.p1;
5164 intel_crtc->config.dpll.p2 = clock.p2;
5165 }
5166
5167 if (IS_GEN2(dev)) {
5168 i8xx_update_pll(intel_crtc,
5169 has_reduced_clock ? &reduced_clock : NULL,
5170 num_connectors);
5171 } else if (IS_VALLEYVIEW(dev)) {
5172 vlv_update_pll(intel_crtc);
5173 } else {
5174 i9xx_update_pll(intel_crtc,
5175 has_reduced_clock ? &reduced_clock : NULL,
5176 num_connectors);
5177 }
5178
5179 skip_dpll:
5180 /* Set up the display plane register */
5181 dspcntr = DISPPLANE_GAMMA_ENABLE;
5182
5183 if (!IS_VALLEYVIEW(dev)) {
5184 if (pipe == 0)
5185 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5186 else
5187 dspcntr |= DISPPLANE_SEL_PIPE_B;
5188 }
5189
5190 intel_set_pipe_timings(intel_crtc);
5191
5192 /* pipesrc and dspsize control the size that is scaled from,
5193 * which should always be the user's requested size.
5194 */
5195 I915_WRITE(DSPSIZE(plane),
5196 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5197 (intel_crtc->config.pipe_src_w - 1));
5198 I915_WRITE(DSPPOS(plane), 0);
5199
5200 i9xx_set_pipeconf(intel_crtc);
5201
5202 I915_WRITE(DSPCNTR(plane), dspcntr);
5203 POSTING_READ(DSPCNTR(plane));
5204
5205 ret = intel_pipe_set_base(crtc, x, y, fb);
5206
5207 return ret;
5208 }
5209
5210 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5211 struct intel_crtc_config *pipe_config)
5212 {
5213 struct drm_device *dev = crtc->base.dev;
5214 struct drm_i915_private *dev_priv = dev->dev_private;
5215 uint32_t tmp;
5216
5217 tmp = I915_READ(PFIT_CONTROL);
5218 if (!(tmp & PFIT_ENABLE))
5219 return;
5220
5221 /* Check whether the pfit is attached to our pipe. */
5222 if (INTEL_INFO(dev)->gen < 4) {
5223 if (crtc->pipe != PIPE_B)
5224 return;
5225 } else {
5226 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5227 return;
5228 }
5229
5230 pipe_config->gmch_pfit.control = tmp;
5231 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5232 if (INTEL_INFO(dev)->gen < 5)
5233 pipe_config->gmch_pfit.lvds_border_bits =
5234 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5235 }
5236
5237 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5238 struct intel_crtc_config *pipe_config)
5239 {
5240 struct drm_device *dev = crtc->base.dev;
5241 struct drm_i915_private *dev_priv = dev->dev_private;
5242 int pipe = pipe_config->cpu_transcoder;
5243 intel_clock_t clock;
5244 u32 mdiv;
5245 int refclk = 100000;
5246
5247 mutex_lock(&dev_priv->dpio_lock);
5248 mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
5249 mutex_unlock(&dev_priv->dpio_lock);
5250
5251 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5252 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5253 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5254 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5255 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5256
5257 vlv_clock(refclk, &clock);
5258
5259 /* clock.dot is the fast clock */
5260 pipe_config->port_clock = clock.dot / 5;
5261 }
5262
5263 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5264 struct intel_crtc_config *pipe_config)
5265 {
5266 struct drm_device *dev = crtc->base.dev;
5267 struct drm_i915_private *dev_priv = dev->dev_private;
5268 uint32_t tmp;
5269
5270 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5271 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5272
5273 tmp = I915_READ(PIPECONF(crtc->pipe));
5274 if (!(tmp & PIPECONF_ENABLE))
5275 return false;
5276
5277 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5278 switch (tmp & PIPECONF_BPC_MASK) {
5279 case PIPECONF_6BPC:
5280 pipe_config->pipe_bpp = 18;
5281 break;
5282 case PIPECONF_8BPC:
5283 pipe_config->pipe_bpp = 24;
5284 break;
5285 case PIPECONF_10BPC:
5286 pipe_config->pipe_bpp = 30;
5287 break;
5288 default:
5289 break;
5290 }
5291 }
5292
5293 if (INTEL_INFO(dev)->gen < 4)
5294 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5295
5296 intel_get_pipe_timings(crtc, pipe_config);
5297
5298 i9xx_get_pfit_config(crtc, pipe_config);
5299
5300 if (INTEL_INFO(dev)->gen >= 4) {
5301 tmp = I915_READ(DPLL_MD(crtc->pipe));
5302 pipe_config->pixel_multiplier =
5303 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5304 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5305 pipe_config->dpll_hw_state.dpll_md = tmp;
5306 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5307 tmp = I915_READ(DPLL(crtc->pipe));
5308 pipe_config->pixel_multiplier =
5309 ((tmp & SDVO_MULTIPLIER_MASK)
5310 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5311 } else {
5312 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5313 * port and will be fixed up in the encoder->get_config
5314 * function. */
5315 pipe_config->pixel_multiplier = 1;
5316 }
5317 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5318 if (!IS_VALLEYVIEW(dev)) {
5319 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5320 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5321 } else {
5322 /* Mask out read-only status bits. */
5323 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5324 DPLL_PORTC_READY_MASK |
5325 DPLL_PORTB_READY_MASK);
5326 }
5327
5328 if (IS_VALLEYVIEW(dev))
5329 vlv_crtc_clock_get(crtc, pipe_config);
5330 else
5331 i9xx_crtc_clock_get(crtc, pipe_config);
5332
5333 return true;
5334 }
5335
5336 static void ironlake_init_pch_refclk(struct drm_device *dev)
5337 {
5338 struct drm_i915_private *dev_priv = dev->dev_private;
5339 struct drm_mode_config *mode_config = &dev->mode_config;
5340 struct intel_encoder *encoder;
5341 u32 val, final;
5342 bool has_lvds = false;
5343 bool has_cpu_edp = false;
5344 bool has_panel = false;
5345 bool has_ck505 = false;
5346 bool can_ssc = false;
5347
5348 /* We need to take the global config into account */
5349 list_for_each_entry(encoder, &mode_config->encoder_list,
5350 base.head) {
5351 switch (encoder->type) {
5352 case INTEL_OUTPUT_LVDS:
5353 has_panel = true;
5354 has_lvds = true;
5355 break;
5356 case INTEL_OUTPUT_EDP:
5357 has_panel = true;
5358 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5359 has_cpu_edp = true;
5360 break;
5361 }
5362 }
5363
5364 if (HAS_PCH_IBX(dev)) {
5365 has_ck505 = dev_priv->vbt.display_clock_mode;
5366 can_ssc = has_ck505;
5367 } else {
5368 has_ck505 = false;
5369 can_ssc = true;
5370 }
5371
5372 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5373 has_panel, has_lvds, has_ck505);
5374
5375 /* Ironlake: try to setup display ref clock before DPLL
5376 * enabling. This is only under driver's control after
5377 * PCH B stepping, previous chipset stepping should be
5378 * ignoring this setting.
5379 */
5380 val = I915_READ(PCH_DREF_CONTROL);
5381
5382 /* As we must carefully and slowly disable/enable each source in turn,
5383 * compute the final state we want first and check if we need to
5384 * make any changes at all.
5385 */
5386 final = val;
5387 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5388 if (has_ck505)
5389 final |= DREF_NONSPREAD_CK505_ENABLE;
5390 else
5391 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5392
5393 final &= ~DREF_SSC_SOURCE_MASK;
5394 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5395 final &= ~DREF_SSC1_ENABLE;
5396
5397 if (has_panel) {
5398 final |= DREF_SSC_SOURCE_ENABLE;
5399
5400 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5401 final |= DREF_SSC1_ENABLE;
5402
5403 if (has_cpu_edp) {
5404 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5405 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5406 else
5407 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5408 } else
5409 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5410 } else {
5411 final |= DREF_SSC_SOURCE_DISABLE;
5412 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5413 }
5414
5415 if (final == val)
5416 return;
5417
5418 /* Always enable nonspread source */
5419 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5420
5421 if (has_ck505)
5422 val |= DREF_NONSPREAD_CK505_ENABLE;
5423 else
5424 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5425
5426 if (has_panel) {
5427 val &= ~DREF_SSC_SOURCE_MASK;
5428 val |= DREF_SSC_SOURCE_ENABLE;
5429
5430 /* SSC must be turned on before enabling the CPU output */
5431 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5432 DRM_DEBUG_KMS("Using SSC on panel\n");
5433 val |= DREF_SSC1_ENABLE;
5434 } else
5435 val &= ~DREF_SSC1_ENABLE;
5436
5437 /* Get SSC going before enabling the outputs */
5438 I915_WRITE(PCH_DREF_CONTROL, val);
5439 POSTING_READ(PCH_DREF_CONTROL);
5440 udelay(200);
5441
5442 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5443
5444 /* Enable CPU source on CPU attached eDP */
5445 if (has_cpu_edp) {
5446 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5447 DRM_DEBUG_KMS("Using SSC on eDP\n");
5448 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5449 }
5450 else
5451 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5452 } else
5453 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5454
5455 I915_WRITE(PCH_DREF_CONTROL, val);
5456 POSTING_READ(PCH_DREF_CONTROL);
5457 udelay(200);
5458 } else {
5459 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5460
5461 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5462
5463 /* Turn off CPU output */
5464 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5465
5466 I915_WRITE(PCH_DREF_CONTROL, val);
5467 POSTING_READ(PCH_DREF_CONTROL);
5468 udelay(200);
5469
5470 /* Turn off the SSC source */
5471 val &= ~DREF_SSC_SOURCE_MASK;
5472 val |= DREF_SSC_SOURCE_DISABLE;
5473
5474 /* Turn off SSC1 */
5475 val &= ~DREF_SSC1_ENABLE;
5476
5477 I915_WRITE(PCH_DREF_CONTROL, val);
5478 POSTING_READ(PCH_DREF_CONTROL);
5479 udelay(200);
5480 }
5481
5482 BUG_ON(val != final);
5483 }
5484
5485 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5486 {
5487 uint32_t tmp;
5488
5489 tmp = I915_READ(SOUTH_CHICKEN2);
5490 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5491 I915_WRITE(SOUTH_CHICKEN2, tmp);
5492
5493 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5494 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5495 DRM_ERROR("FDI mPHY reset assert timeout\n");
5496
5497 tmp = I915_READ(SOUTH_CHICKEN2);
5498 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5499 I915_WRITE(SOUTH_CHICKEN2, tmp);
5500
5501 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5502 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5503 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5504 }
5505
5506 /* WaMPhyProgramming:hsw */
5507 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5508 {
5509 uint32_t tmp;
5510
5511 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5512 tmp &= ~(0xFF << 24);
5513 tmp |= (0x12 << 24);
5514 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5515
5516 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5517 tmp |= (1 << 11);
5518 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5519
5520 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5521 tmp |= (1 << 11);
5522 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5523
5524 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5525 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5526 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5527
5528 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5529 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5530 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5531
5532 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5533 tmp &= ~(7 << 13);
5534 tmp |= (5 << 13);
5535 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5536
5537 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5538 tmp &= ~(7 << 13);
5539 tmp |= (5 << 13);
5540 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5541
5542 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5543 tmp &= ~0xFF;
5544 tmp |= 0x1C;
5545 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5546
5547 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5548 tmp &= ~0xFF;
5549 tmp |= 0x1C;
5550 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5551
5552 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5553 tmp &= ~(0xFF << 16);
5554 tmp |= (0x1C << 16);
5555 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5556
5557 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5558 tmp &= ~(0xFF << 16);
5559 tmp |= (0x1C << 16);
5560 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5561
5562 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5563 tmp |= (1 << 27);
5564 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5565
5566 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5567 tmp |= (1 << 27);
5568 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5569
5570 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5571 tmp &= ~(0xF << 28);
5572 tmp |= (4 << 28);
5573 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5574
5575 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5576 tmp &= ~(0xF << 28);
5577 tmp |= (4 << 28);
5578 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5579 }
5580
5581 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5582 * Programming" based on the parameters passed:
5583 * - Sequence to enable CLKOUT_DP
5584 * - Sequence to enable CLKOUT_DP without spread
5585 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5586 */
5587 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5588 bool with_fdi)
5589 {
5590 struct drm_i915_private *dev_priv = dev->dev_private;
5591 uint32_t reg, tmp;
5592
5593 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5594 with_spread = true;
5595 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5596 with_fdi, "LP PCH doesn't have FDI\n"))
5597 with_fdi = false;
5598
5599 mutex_lock(&dev_priv->dpio_lock);
5600
5601 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5602 tmp &= ~SBI_SSCCTL_DISABLE;
5603 tmp |= SBI_SSCCTL_PATHALT;
5604 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5605
5606 udelay(24);
5607
5608 if (with_spread) {
5609 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5610 tmp &= ~SBI_SSCCTL_PATHALT;
5611 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5612
5613 if (with_fdi) {
5614 lpt_reset_fdi_mphy(dev_priv);
5615 lpt_program_fdi_mphy(dev_priv);
5616 }
5617 }
5618
5619 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5620 SBI_GEN0 : SBI_DBUFF0;
5621 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5622 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5623 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5624
5625 mutex_unlock(&dev_priv->dpio_lock);
5626 }
5627
5628 /* Sequence to disable CLKOUT_DP */
5629 static void lpt_disable_clkout_dp(struct drm_device *dev)
5630 {
5631 struct drm_i915_private *dev_priv = dev->dev_private;
5632 uint32_t reg, tmp;
5633
5634 mutex_lock(&dev_priv->dpio_lock);
5635
5636 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5637 SBI_GEN0 : SBI_DBUFF0;
5638 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5639 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5640 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5641
5642 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5643 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5644 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5645 tmp |= SBI_SSCCTL_PATHALT;
5646 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5647 udelay(32);
5648 }
5649 tmp |= SBI_SSCCTL_DISABLE;
5650 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5651 }
5652
5653 mutex_unlock(&dev_priv->dpio_lock);
5654 }
5655
5656 static void lpt_init_pch_refclk(struct drm_device *dev)
5657 {
5658 struct drm_mode_config *mode_config = &dev->mode_config;
5659 struct intel_encoder *encoder;
5660 bool has_vga = false;
5661
5662 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5663 switch (encoder->type) {
5664 case INTEL_OUTPUT_ANALOG:
5665 has_vga = true;
5666 break;
5667 }
5668 }
5669
5670 if (has_vga)
5671 lpt_enable_clkout_dp(dev, true, true);
5672 else
5673 lpt_disable_clkout_dp(dev);
5674 }
5675
5676 /*
5677 * Initialize reference clocks when the driver loads
5678 */
5679 void intel_init_pch_refclk(struct drm_device *dev)
5680 {
5681 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5682 ironlake_init_pch_refclk(dev);
5683 else if (HAS_PCH_LPT(dev))
5684 lpt_init_pch_refclk(dev);
5685 }
5686
5687 static int ironlake_get_refclk(struct drm_crtc *crtc)
5688 {
5689 struct drm_device *dev = crtc->dev;
5690 struct drm_i915_private *dev_priv = dev->dev_private;
5691 struct intel_encoder *encoder;
5692 int num_connectors = 0;
5693 bool is_lvds = false;
5694
5695 for_each_encoder_on_crtc(dev, crtc, encoder) {
5696 switch (encoder->type) {
5697 case INTEL_OUTPUT_LVDS:
5698 is_lvds = true;
5699 break;
5700 }
5701 num_connectors++;
5702 }
5703
5704 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5705 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5706 dev_priv->vbt.lvds_ssc_freq);
5707 return dev_priv->vbt.lvds_ssc_freq * 1000;
5708 }
5709
5710 return 120000;
5711 }
5712
5713 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5714 {
5715 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5716 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5717 int pipe = intel_crtc->pipe;
5718 uint32_t val;
5719
5720 val = 0;
5721
5722 switch (intel_crtc->config.pipe_bpp) {
5723 case 18:
5724 val |= PIPECONF_6BPC;
5725 break;
5726 case 24:
5727 val |= PIPECONF_8BPC;
5728 break;
5729 case 30:
5730 val |= PIPECONF_10BPC;
5731 break;
5732 case 36:
5733 val |= PIPECONF_12BPC;
5734 break;
5735 default:
5736 /* Case prevented by intel_choose_pipe_bpp_dither. */
5737 BUG();
5738 }
5739
5740 if (intel_crtc->config.dither)
5741 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5742
5743 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5744 val |= PIPECONF_INTERLACED_ILK;
5745 else
5746 val |= PIPECONF_PROGRESSIVE;
5747
5748 if (intel_crtc->config.limited_color_range)
5749 val |= PIPECONF_COLOR_RANGE_SELECT;
5750
5751 I915_WRITE(PIPECONF(pipe), val);
5752 POSTING_READ(PIPECONF(pipe));
5753 }
5754
5755 /*
5756 * Set up the pipe CSC unit.
5757 *
5758 * Currently only full range RGB to limited range RGB conversion
5759 * is supported, but eventually this should handle various
5760 * RGB<->YCbCr scenarios as well.
5761 */
5762 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5763 {
5764 struct drm_device *dev = crtc->dev;
5765 struct drm_i915_private *dev_priv = dev->dev_private;
5766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5767 int pipe = intel_crtc->pipe;
5768 uint16_t coeff = 0x7800; /* 1.0 */
5769
5770 /*
5771 * TODO: Check what kind of values actually come out of the pipe
5772 * with these coeff/postoff values and adjust to get the best
5773 * accuracy. Perhaps we even need to take the bpc value into
5774 * consideration.
5775 */
5776
5777 if (intel_crtc->config.limited_color_range)
5778 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5779
5780 /*
5781 * GY/GU and RY/RU should be the other way around according
5782 * to BSpec, but reality doesn't agree. Just set them up in
5783 * a way that results in the correct picture.
5784 */
5785 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5786 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5787
5788 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5789 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5790
5791 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5792 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5793
5794 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5795 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5796 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5797
5798 if (INTEL_INFO(dev)->gen > 6) {
5799 uint16_t postoff = 0;
5800
5801 if (intel_crtc->config.limited_color_range)
5802 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5803
5804 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5805 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5806 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5807
5808 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5809 } else {
5810 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5811
5812 if (intel_crtc->config.limited_color_range)
5813 mode |= CSC_BLACK_SCREEN_OFFSET;
5814
5815 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5816 }
5817 }
5818
5819 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5820 {
5821 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5822 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5823 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5824 uint32_t val;
5825
5826 val = 0;
5827
5828 if (intel_crtc->config.dither)
5829 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5830
5831 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5832 val |= PIPECONF_INTERLACED_ILK;
5833 else
5834 val |= PIPECONF_PROGRESSIVE;
5835
5836 I915_WRITE(PIPECONF(cpu_transcoder), val);
5837 POSTING_READ(PIPECONF(cpu_transcoder));
5838
5839 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5840 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5841 }
5842
5843 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5844 intel_clock_t *clock,
5845 bool *has_reduced_clock,
5846 intel_clock_t *reduced_clock)
5847 {
5848 struct drm_device *dev = crtc->dev;
5849 struct drm_i915_private *dev_priv = dev->dev_private;
5850 struct intel_encoder *intel_encoder;
5851 int refclk;
5852 const intel_limit_t *limit;
5853 bool ret, is_lvds = false;
5854
5855 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5856 switch (intel_encoder->type) {
5857 case INTEL_OUTPUT_LVDS:
5858 is_lvds = true;
5859 break;
5860 }
5861 }
5862
5863 refclk = ironlake_get_refclk(crtc);
5864
5865 /*
5866 * Returns a set of divisors for the desired target clock with the given
5867 * refclk, or FALSE. The returned values represent the clock equation:
5868 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5869 */
5870 limit = intel_limit(crtc, refclk);
5871 ret = dev_priv->display.find_dpll(limit, crtc,
5872 to_intel_crtc(crtc)->config.port_clock,
5873 refclk, NULL, clock);
5874 if (!ret)
5875 return false;
5876
5877 if (is_lvds && dev_priv->lvds_downclock_avail) {
5878 /*
5879 * Ensure we match the reduced clock's P to the target clock.
5880 * If the clocks don't match, we can't switch the display clock
5881 * by using the FP0/FP1. In such case we will disable the LVDS
5882 * downclock feature.
5883 */
5884 *has_reduced_clock =
5885 dev_priv->display.find_dpll(limit, crtc,
5886 dev_priv->lvds_downclock,
5887 refclk, clock,
5888 reduced_clock);
5889 }
5890
5891 return true;
5892 }
5893
5894 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5895 {
5896 /*
5897 * Account for spread spectrum to avoid
5898 * oversubscribing the link. Max center spread
5899 * is 2.5%; use 5% for safety's sake.
5900 */
5901 u32 bps = target_clock * bpp * 21 / 20;
5902 return bps / (link_bw * 8) + 1;
5903 }
5904
5905 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5906 {
5907 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5908 }
5909
5910 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5911 u32 *fp,
5912 intel_clock_t *reduced_clock, u32 *fp2)
5913 {
5914 struct drm_crtc *crtc = &intel_crtc->base;
5915 struct drm_device *dev = crtc->dev;
5916 struct drm_i915_private *dev_priv = dev->dev_private;
5917 struct intel_encoder *intel_encoder;
5918 uint32_t dpll;
5919 int factor, num_connectors = 0;
5920 bool is_lvds = false, is_sdvo = false;
5921
5922 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5923 switch (intel_encoder->type) {
5924 case INTEL_OUTPUT_LVDS:
5925 is_lvds = true;
5926 break;
5927 case INTEL_OUTPUT_SDVO:
5928 case INTEL_OUTPUT_HDMI:
5929 is_sdvo = true;
5930 break;
5931 }
5932
5933 num_connectors++;
5934 }
5935
5936 /* Enable autotuning of the PLL clock (if permissible) */
5937 factor = 21;
5938 if (is_lvds) {
5939 if ((intel_panel_use_ssc(dev_priv) &&
5940 dev_priv->vbt.lvds_ssc_freq == 100) ||
5941 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5942 factor = 25;
5943 } else if (intel_crtc->config.sdvo_tv_clock)
5944 factor = 20;
5945
5946 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5947 *fp |= FP_CB_TUNE;
5948
5949 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5950 *fp2 |= FP_CB_TUNE;
5951
5952 dpll = 0;
5953
5954 if (is_lvds)
5955 dpll |= DPLLB_MODE_LVDS;
5956 else
5957 dpll |= DPLLB_MODE_DAC_SERIAL;
5958
5959 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5960 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5961
5962 if (is_sdvo)
5963 dpll |= DPLL_SDVO_HIGH_SPEED;
5964 if (intel_crtc->config.has_dp_encoder)
5965 dpll |= DPLL_SDVO_HIGH_SPEED;
5966
5967 /* compute bitmask from p1 value */
5968 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5969 /* also FPA1 */
5970 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5971
5972 switch (intel_crtc->config.dpll.p2) {
5973 case 5:
5974 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5975 break;
5976 case 7:
5977 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5978 break;
5979 case 10:
5980 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5981 break;
5982 case 14:
5983 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5984 break;
5985 }
5986
5987 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5988 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5989 else
5990 dpll |= PLL_REF_INPUT_DREFCLK;
5991
5992 return dpll | DPLL_VCO_ENABLE;
5993 }
5994
5995 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5996 int x, int y,
5997 struct drm_framebuffer *fb)
5998 {
5999 struct drm_device *dev = crtc->dev;
6000 struct drm_i915_private *dev_priv = dev->dev_private;
6001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6002 int pipe = intel_crtc->pipe;
6003 int plane = intel_crtc->plane;
6004 int num_connectors = 0;
6005 intel_clock_t clock, reduced_clock;
6006 u32 dpll = 0, fp = 0, fp2 = 0;
6007 bool ok, has_reduced_clock = false;
6008 bool is_lvds = false;
6009 struct intel_encoder *encoder;
6010 struct intel_shared_dpll *pll;
6011 int ret;
6012
6013 for_each_encoder_on_crtc(dev, crtc, encoder) {
6014 switch (encoder->type) {
6015 case INTEL_OUTPUT_LVDS:
6016 is_lvds = true;
6017 break;
6018 }
6019
6020 num_connectors++;
6021 }
6022
6023 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6024 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6025
6026 ok = ironlake_compute_clocks(crtc, &clock,
6027 &has_reduced_clock, &reduced_clock);
6028 if (!ok && !intel_crtc->config.clock_set) {
6029 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6030 return -EINVAL;
6031 }
6032 /* Compat-code for transition, will disappear. */
6033 if (!intel_crtc->config.clock_set) {
6034 intel_crtc->config.dpll.n = clock.n;
6035 intel_crtc->config.dpll.m1 = clock.m1;
6036 intel_crtc->config.dpll.m2 = clock.m2;
6037 intel_crtc->config.dpll.p1 = clock.p1;
6038 intel_crtc->config.dpll.p2 = clock.p2;
6039 }
6040
6041 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6042 if (intel_crtc->config.has_pch_encoder) {
6043 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6044 if (has_reduced_clock)
6045 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6046
6047 dpll = ironlake_compute_dpll(intel_crtc,
6048 &fp, &reduced_clock,
6049 has_reduced_clock ? &fp2 : NULL);
6050
6051 intel_crtc->config.dpll_hw_state.dpll = dpll;
6052 intel_crtc->config.dpll_hw_state.fp0 = fp;
6053 if (has_reduced_clock)
6054 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6055 else
6056 intel_crtc->config.dpll_hw_state.fp1 = fp;
6057
6058 pll = intel_get_shared_dpll(intel_crtc);
6059 if (pll == NULL) {
6060 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6061 pipe_name(pipe));
6062 return -EINVAL;
6063 }
6064 } else
6065 intel_put_shared_dpll(intel_crtc);
6066
6067 if (intel_crtc->config.has_dp_encoder)
6068 intel_dp_set_m_n(intel_crtc);
6069
6070 if (is_lvds && has_reduced_clock && i915_powersave)
6071 intel_crtc->lowfreq_avail = true;
6072 else
6073 intel_crtc->lowfreq_avail = false;
6074
6075 intel_set_pipe_timings(intel_crtc);
6076
6077 if (intel_crtc->config.has_pch_encoder) {
6078 intel_cpu_transcoder_set_m_n(intel_crtc,
6079 &intel_crtc->config.fdi_m_n);
6080 }
6081
6082 ironlake_set_pipeconf(crtc);
6083
6084 /* Set up the display plane register */
6085 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6086 POSTING_READ(DSPCNTR(plane));
6087
6088 ret = intel_pipe_set_base(crtc, x, y, fb);
6089
6090 return ret;
6091 }
6092
6093 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6094 struct intel_link_m_n *m_n)
6095 {
6096 struct drm_device *dev = crtc->base.dev;
6097 struct drm_i915_private *dev_priv = dev->dev_private;
6098 enum pipe pipe = crtc->pipe;
6099
6100 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6101 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6102 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6103 & ~TU_SIZE_MASK;
6104 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6105 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6106 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6107 }
6108
6109 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6110 enum transcoder transcoder,
6111 struct intel_link_m_n *m_n)
6112 {
6113 struct drm_device *dev = crtc->base.dev;
6114 struct drm_i915_private *dev_priv = dev->dev_private;
6115 enum pipe pipe = crtc->pipe;
6116
6117 if (INTEL_INFO(dev)->gen >= 5) {
6118 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6119 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6120 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6121 & ~TU_SIZE_MASK;
6122 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6123 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6124 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6125 } else {
6126 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6127 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6128 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6129 & ~TU_SIZE_MASK;
6130 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6131 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6132 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6133 }
6134 }
6135
6136 void intel_dp_get_m_n(struct intel_crtc *crtc,
6137 struct intel_crtc_config *pipe_config)
6138 {
6139 if (crtc->config.has_pch_encoder)
6140 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6141 else
6142 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6143 &pipe_config->dp_m_n);
6144 }
6145
6146 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6147 struct intel_crtc_config *pipe_config)
6148 {
6149 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6150 &pipe_config->fdi_m_n);
6151 }
6152
6153 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6154 struct intel_crtc_config *pipe_config)
6155 {
6156 struct drm_device *dev = crtc->base.dev;
6157 struct drm_i915_private *dev_priv = dev->dev_private;
6158 uint32_t tmp;
6159
6160 tmp = I915_READ(PF_CTL(crtc->pipe));
6161
6162 if (tmp & PF_ENABLE) {
6163 pipe_config->pch_pfit.enabled = true;
6164 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6165 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6166
6167 /* We currently do not free assignements of panel fitters on
6168 * ivb/hsw (since we don't use the higher upscaling modes which
6169 * differentiates them) so just WARN about this case for now. */
6170 if (IS_GEN7(dev)) {
6171 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6172 PF_PIPE_SEL_IVB(crtc->pipe));
6173 }
6174 }
6175 }
6176
6177 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6178 struct intel_crtc_config *pipe_config)
6179 {
6180 struct drm_device *dev = crtc->base.dev;
6181 struct drm_i915_private *dev_priv = dev->dev_private;
6182 uint32_t tmp;
6183
6184 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6185 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6186
6187 tmp = I915_READ(PIPECONF(crtc->pipe));
6188 if (!(tmp & PIPECONF_ENABLE))
6189 return false;
6190
6191 switch (tmp & PIPECONF_BPC_MASK) {
6192 case PIPECONF_6BPC:
6193 pipe_config->pipe_bpp = 18;
6194 break;
6195 case PIPECONF_8BPC:
6196 pipe_config->pipe_bpp = 24;
6197 break;
6198 case PIPECONF_10BPC:
6199 pipe_config->pipe_bpp = 30;
6200 break;
6201 case PIPECONF_12BPC:
6202 pipe_config->pipe_bpp = 36;
6203 break;
6204 default:
6205 break;
6206 }
6207
6208 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6209 struct intel_shared_dpll *pll;
6210
6211 pipe_config->has_pch_encoder = true;
6212
6213 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6214 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6215 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6216
6217 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6218
6219 if (HAS_PCH_IBX(dev_priv->dev)) {
6220 pipe_config->shared_dpll =
6221 (enum intel_dpll_id) crtc->pipe;
6222 } else {
6223 tmp = I915_READ(PCH_DPLL_SEL);
6224 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6225 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6226 else
6227 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6228 }
6229
6230 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6231
6232 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6233 &pipe_config->dpll_hw_state));
6234
6235 tmp = pipe_config->dpll_hw_state.dpll;
6236 pipe_config->pixel_multiplier =
6237 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6238 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6239
6240 ironlake_pch_clock_get(crtc, pipe_config);
6241 } else {
6242 pipe_config->pixel_multiplier = 1;
6243 }
6244
6245 intel_get_pipe_timings(crtc, pipe_config);
6246
6247 ironlake_get_pfit_config(crtc, pipe_config);
6248
6249 return true;
6250 }
6251
6252 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6253 {
6254 struct drm_device *dev = dev_priv->dev;
6255 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6256 struct intel_crtc *crtc;
6257 unsigned long irqflags;
6258 uint32_t val;
6259
6260 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6261 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6262 pipe_name(crtc->pipe));
6263
6264 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6265 WARN(plls->spll_refcount, "SPLL enabled\n");
6266 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6267 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6268 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6269 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6270 "CPU PWM1 enabled\n");
6271 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6272 "CPU PWM2 enabled\n");
6273 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6274 "PCH PWM1 enabled\n");
6275 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6276 "Utility pin enabled\n");
6277 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6278
6279 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6280 val = I915_READ(DEIMR);
6281 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6282 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6283 val = I915_READ(SDEIMR);
6284 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6285 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6286 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6287 }
6288
6289 /*
6290 * This function implements pieces of two sequences from BSpec:
6291 * - Sequence for display software to disable LCPLL
6292 * - Sequence for display software to allow package C8+
6293 * The steps implemented here are just the steps that actually touch the LCPLL
6294 * register. Callers should take care of disabling all the display engine
6295 * functions, doing the mode unset, fixing interrupts, etc.
6296 */
6297 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6298 bool switch_to_fclk, bool allow_power_down)
6299 {
6300 uint32_t val;
6301
6302 assert_can_disable_lcpll(dev_priv);
6303
6304 val = I915_READ(LCPLL_CTL);
6305
6306 if (switch_to_fclk) {
6307 val |= LCPLL_CD_SOURCE_FCLK;
6308 I915_WRITE(LCPLL_CTL, val);
6309
6310 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6311 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6312 DRM_ERROR("Switching to FCLK failed\n");
6313
6314 val = I915_READ(LCPLL_CTL);
6315 }
6316
6317 val |= LCPLL_PLL_DISABLE;
6318 I915_WRITE(LCPLL_CTL, val);
6319 POSTING_READ(LCPLL_CTL);
6320
6321 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6322 DRM_ERROR("LCPLL still locked\n");
6323
6324 val = I915_READ(D_COMP);
6325 val |= D_COMP_COMP_DISABLE;
6326 mutex_lock(&dev_priv->rps.hw_lock);
6327 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6328 DRM_ERROR("Failed to disable D_COMP\n");
6329 mutex_unlock(&dev_priv->rps.hw_lock);
6330 POSTING_READ(D_COMP);
6331 ndelay(100);
6332
6333 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6334 DRM_ERROR("D_COMP RCOMP still in progress\n");
6335
6336 if (allow_power_down) {
6337 val = I915_READ(LCPLL_CTL);
6338 val |= LCPLL_POWER_DOWN_ALLOW;
6339 I915_WRITE(LCPLL_CTL, val);
6340 POSTING_READ(LCPLL_CTL);
6341 }
6342 }
6343
6344 /*
6345 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6346 * source.
6347 */
6348 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6349 {
6350 uint32_t val;
6351
6352 val = I915_READ(LCPLL_CTL);
6353
6354 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6355 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6356 return;
6357
6358 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6359 * we'll hang the machine! */
6360 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6361
6362 if (val & LCPLL_POWER_DOWN_ALLOW) {
6363 val &= ~LCPLL_POWER_DOWN_ALLOW;
6364 I915_WRITE(LCPLL_CTL, val);
6365 POSTING_READ(LCPLL_CTL);
6366 }
6367
6368 val = I915_READ(D_COMP);
6369 val |= D_COMP_COMP_FORCE;
6370 val &= ~D_COMP_COMP_DISABLE;
6371 mutex_lock(&dev_priv->rps.hw_lock);
6372 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6373 DRM_ERROR("Failed to enable D_COMP\n");
6374 mutex_unlock(&dev_priv->rps.hw_lock);
6375 POSTING_READ(D_COMP);
6376
6377 val = I915_READ(LCPLL_CTL);
6378 val &= ~LCPLL_PLL_DISABLE;
6379 I915_WRITE(LCPLL_CTL, val);
6380
6381 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6382 DRM_ERROR("LCPLL not locked yet\n");
6383
6384 if (val & LCPLL_CD_SOURCE_FCLK) {
6385 val = I915_READ(LCPLL_CTL);
6386 val &= ~LCPLL_CD_SOURCE_FCLK;
6387 I915_WRITE(LCPLL_CTL, val);
6388
6389 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6390 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6391 DRM_ERROR("Switching back to LCPLL failed\n");
6392 }
6393
6394 dev_priv->uncore.funcs.force_wake_put(dev_priv);
6395 }
6396
6397 void hsw_enable_pc8_work(struct work_struct *__work)
6398 {
6399 struct drm_i915_private *dev_priv =
6400 container_of(to_delayed_work(__work), struct drm_i915_private,
6401 pc8.enable_work);
6402 struct drm_device *dev = dev_priv->dev;
6403 uint32_t val;
6404
6405 if (dev_priv->pc8.enabled)
6406 return;
6407
6408 DRM_DEBUG_KMS("Enabling package C8+\n");
6409
6410 dev_priv->pc8.enabled = true;
6411
6412 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6413 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6414 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6415 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6416 }
6417
6418 lpt_disable_clkout_dp(dev);
6419 hsw_pc8_disable_interrupts(dev);
6420 hsw_disable_lcpll(dev_priv, true, true);
6421 }
6422
6423 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6424 {
6425 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6426 WARN(dev_priv->pc8.disable_count < 1,
6427 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6428
6429 dev_priv->pc8.disable_count--;
6430 if (dev_priv->pc8.disable_count != 0)
6431 return;
6432
6433 schedule_delayed_work(&dev_priv->pc8.enable_work,
6434 msecs_to_jiffies(i915_pc8_timeout));
6435 }
6436
6437 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6438 {
6439 struct drm_device *dev = dev_priv->dev;
6440 uint32_t val;
6441
6442 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6443 WARN(dev_priv->pc8.disable_count < 0,
6444 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6445
6446 dev_priv->pc8.disable_count++;
6447 if (dev_priv->pc8.disable_count != 1)
6448 return;
6449
6450 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6451 if (!dev_priv->pc8.enabled)
6452 return;
6453
6454 DRM_DEBUG_KMS("Disabling package C8+\n");
6455
6456 hsw_restore_lcpll(dev_priv);
6457 hsw_pc8_restore_interrupts(dev);
6458 lpt_init_pch_refclk(dev);
6459
6460 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6461 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6462 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6463 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6464 }
6465
6466 intel_prepare_ddi(dev);
6467 i915_gem_init_swizzling(dev);
6468 mutex_lock(&dev_priv->rps.hw_lock);
6469 gen6_update_ring_freq(dev);
6470 mutex_unlock(&dev_priv->rps.hw_lock);
6471 dev_priv->pc8.enabled = false;
6472 }
6473
6474 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6475 {
6476 mutex_lock(&dev_priv->pc8.lock);
6477 __hsw_enable_package_c8(dev_priv);
6478 mutex_unlock(&dev_priv->pc8.lock);
6479 }
6480
6481 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6482 {
6483 mutex_lock(&dev_priv->pc8.lock);
6484 __hsw_disable_package_c8(dev_priv);
6485 mutex_unlock(&dev_priv->pc8.lock);
6486 }
6487
6488 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6489 {
6490 struct drm_device *dev = dev_priv->dev;
6491 struct intel_crtc *crtc;
6492 uint32_t val;
6493
6494 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6495 if (crtc->base.enabled)
6496 return false;
6497
6498 /* This case is still possible since we have the i915.disable_power_well
6499 * parameter and also the KVMr or something else might be requesting the
6500 * power well. */
6501 val = I915_READ(HSW_PWR_WELL_DRIVER);
6502 if (val != 0) {
6503 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6504 return false;
6505 }
6506
6507 return true;
6508 }
6509
6510 /* Since we're called from modeset_global_resources there's no way to
6511 * symmetrically increase and decrease the refcount, so we use
6512 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6513 * or not.
6514 */
6515 static void hsw_update_package_c8(struct drm_device *dev)
6516 {
6517 struct drm_i915_private *dev_priv = dev->dev_private;
6518 bool allow;
6519
6520 if (!i915_enable_pc8)
6521 return;
6522
6523 mutex_lock(&dev_priv->pc8.lock);
6524
6525 allow = hsw_can_enable_package_c8(dev_priv);
6526
6527 if (allow == dev_priv->pc8.requirements_met)
6528 goto done;
6529
6530 dev_priv->pc8.requirements_met = allow;
6531
6532 if (allow)
6533 __hsw_enable_package_c8(dev_priv);
6534 else
6535 __hsw_disable_package_c8(dev_priv);
6536
6537 done:
6538 mutex_unlock(&dev_priv->pc8.lock);
6539 }
6540
6541 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6542 {
6543 if (!dev_priv->pc8.gpu_idle) {
6544 dev_priv->pc8.gpu_idle = true;
6545 hsw_enable_package_c8(dev_priv);
6546 }
6547 }
6548
6549 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6550 {
6551 if (dev_priv->pc8.gpu_idle) {
6552 dev_priv->pc8.gpu_idle = false;
6553 hsw_disable_package_c8(dev_priv);
6554 }
6555 }
6556
6557 #define for_each_power_domain(domain, mask) \
6558 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
6559 if ((1 << (domain)) & (mask))
6560
6561 static unsigned long get_pipe_power_domains(struct drm_device *dev,
6562 enum pipe pipe, bool pfit_enabled)
6563 {
6564 unsigned long mask;
6565 enum transcoder transcoder;
6566
6567 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
6568
6569 mask = BIT(POWER_DOMAIN_PIPE(pipe));
6570 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6571 if (pfit_enabled)
6572 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6573
6574 return mask;
6575 }
6576
6577 void intel_display_set_init_power(struct drm_device *dev, bool enable)
6578 {
6579 struct drm_i915_private *dev_priv = dev->dev_private;
6580
6581 if (dev_priv->power_domains.init_power_on == enable)
6582 return;
6583
6584 if (enable)
6585 intel_display_power_get(dev, POWER_DOMAIN_INIT);
6586 else
6587 intel_display_power_put(dev, POWER_DOMAIN_INIT);
6588
6589 dev_priv->power_domains.init_power_on = enable;
6590 }
6591
6592 static void modeset_update_power_wells(struct drm_device *dev)
6593 {
6594 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
6595 struct intel_crtc *crtc;
6596
6597 /*
6598 * First get all needed power domains, then put all unneeded, to avoid
6599 * any unnecessary toggling of the power wells.
6600 */
6601 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6602 enum intel_display_power_domain domain;
6603
6604 if (!crtc->base.enabled)
6605 continue;
6606
6607 pipe_domains[crtc->pipe] = get_pipe_power_domains(dev,
6608 crtc->pipe,
6609 crtc->config.pch_pfit.enabled);
6610
6611 for_each_power_domain(domain, pipe_domains[crtc->pipe])
6612 intel_display_power_get(dev, domain);
6613 }
6614
6615 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6616 enum intel_display_power_domain domain;
6617
6618 for_each_power_domain(domain, crtc->enabled_power_domains)
6619 intel_display_power_put(dev, domain);
6620
6621 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
6622 }
6623
6624 intel_display_set_init_power(dev, false);
6625 }
6626
6627 static void haswell_modeset_global_resources(struct drm_device *dev)
6628 {
6629 modeset_update_power_wells(dev);
6630 hsw_update_package_c8(dev);
6631 }
6632
6633 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6634 int x, int y,
6635 struct drm_framebuffer *fb)
6636 {
6637 struct drm_device *dev = crtc->dev;
6638 struct drm_i915_private *dev_priv = dev->dev_private;
6639 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6640 int plane = intel_crtc->plane;
6641 int ret;
6642
6643 if (!intel_ddi_pll_mode_set(crtc))
6644 return -EINVAL;
6645
6646 if (intel_crtc->config.has_dp_encoder)
6647 intel_dp_set_m_n(intel_crtc);
6648
6649 intel_crtc->lowfreq_avail = false;
6650
6651 intel_set_pipe_timings(intel_crtc);
6652
6653 if (intel_crtc->config.has_pch_encoder) {
6654 intel_cpu_transcoder_set_m_n(intel_crtc,
6655 &intel_crtc->config.fdi_m_n);
6656 }
6657
6658 haswell_set_pipeconf(crtc);
6659
6660 intel_set_pipe_csc(crtc);
6661
6662 /* Set up the display plane register */
6663 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6664 POSTING_READ(DSPCNTR(plane));
6665
6666 ret = intel_pipe_set_base(crtc, x, y, fb);
6667
6668 return ret;
6669 }
6670
6671 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6672 struct intel_crtc_config *pipe_config)
6673 {
6674 struct drm_device *dev = crtc->base.dev;
6675 struct drm_i915_private *dev_priv = dev->dev_private;
6676 enum intel_display_power_domain pfit_domain;
6677 uint32_t tmp;
6678
6679 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6680 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6681
6682 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6683 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6684 enum pipe trans_edp_pipe;
6685 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6686 default:
6687 WARN(1, "unknown pipe linked to edp transcoder\n");
6688 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6689 case TRANS_DDI_EDP_INPUT_A_ON:
6690 trans_edp_pipe = PIPE_A;
6691 break;
6692 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6693 trans_edp_pipe = PIPE_B;
6694 break;
6695 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6696 trans_edp_pipe = PIPE_C;
6697 break;
6698 }
6699
6700 if (trans_edp_pipe == crtc->pipe)
6701 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6702 }
6703
6704 if (!intel_display_power_enabled(dev,
6705 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6706 return false;
6707
6708 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6709 if (!(tmp & PIPECONF_ENABLE))
6710 return false;
6711
6712 /*
6713 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6714 * DDI E. So just check whether this pipe is wired to DDI E and whether
6715 * the PCH transcoder is on.
6716 */
6717 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6718 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6719 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6720 pipe_config->has_pch_encoder = true;
6721
6722 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6723 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6724 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6725
6726 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6727 }
6728
6729 intel_get_pipe_timings(crtc, pipe_config);
6730
6731 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6732 if (intel_display_power_enabled(dev, pfit_domain))
6733 ironlake_get_pfit_config(crtc, pipe_config);
6734
6735 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6736 (I915_READ(IPS_CTL) & IPS_ENABLE);
6737
6738 pipe_config->pixel_multiplier = 1;
6739
6740 return true;
6741 }
6742
6743 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6744 int x, int y,
6745 struct drm_framebuffer *fb)
6746 {
6747 struct drm_device *dev = crtc->dev;
6748 struct drm_i915_private *dev_priv = dev->dev_private;
6749 struct intel_encoder *encoder;
6750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6751 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6752 int pipe = intel_crtc->pipe;
6753 int ret;
6754
6755 drm_vblank_pre_modeset(dev, pipe);
6756
6757 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6758
6759 drm_vblank_post_modeset(dev, pipe);
6760
6761 if (ret != 0)
6762 return ret;
6763
6764 for_each_encoder_on_crtc(dev, crtc, encoder) {
6765 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6766 encoder->base.base.id,
6767 drm_get_encoder_name(&encoder->base),
6768 mode->base.id, mode->name);
6769 encoder->mode_set(encoder);
6770 }
6771
6772 return 0;
6773 }
6774
6775 static struct {
6776 int clock;
6777 u32 config;
6778 } hdmi_audio_clock[] = {
6779 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
6780 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
6781 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
6782 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
6783 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
6784 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
6785 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
6786 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
6787 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
6788 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
6789 };
6790
6791 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
6792 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
6793 {
6794 int i;
6795
6796 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
6797 if (mode->clock == hdmi_audio_clock[i].clock)
6798 break;
6799 }
6800
6801 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
6802 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
6803 i = 1;
6804 }
6805
6806 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
6807 hdmi_audio_clock[i].clock,
6808 hdmi_audio_clock[i].config);
6809
6810 return hdmi_audio_clock[i].config;
6811 }
6812
6813 static bool intel_eld_uptodate(struct drm_connector *connector,
6814 int reg_eldv, uint32_t bits_eldv,
6815 int reg_elda, uint32_t bits_elda,
6816 int reg_edid)
6817 {
6818 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6819 uint8_t *eld = connector->eld;
6820 uint32_t i;
6821
6822 i = I915_READ(reg_eldv);
6823 i &= bits_eldv;
6824
6825 if (!eld[0])
6826 return !i;
6827
6828 if (!i)
6829 return false;
6830
6831 i = I915_READ(reg_elda);
6832 i &= ~bits_elda;
6833 I915_WRITE(reg_elda, i);
6834
6835 for (i = 0; i < eld[2]; i++)
6836 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6837 return false;
6838
6839 return true;
6840 }
6841
6842 static void g4x_write_eld(struct drm_connector *connector,
6843 struct drm_crtc *crtc,
6844 struct drm_display_mode *mode)
6845 {
6846 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6847 uint8_t *eld = connector->eld;
6848 uint32_t eldv;
6849 uint32_t len;
6850 uint32_t i;
6851
6852 i = I915_READ(G4X_AUD_VID_DID);
6853
6854 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6855 eldv = G4X_ELDV_DEVCL_DEVBLC;
6856 else
6857 eldv = G4X_ELDV_DEVCTG;
6858
6859 if (intel_eld_uptodate(connector,
6860 G4X_AUD_CNTL_ST, eldv,
6861 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6862 G4X_HDMIW_HDMIEDID))
6863 return;
6864
6865 i = I915_READ(G4X_AUD_CNTL_ST);
6866 i &= ~(eldv | G4X_ELD_ADDR);
6867 len = (i >> 9) & 0x1f; /* ELD buffer size */
6868 I915_WRITE(G4X_AUD_CNTL_ST, i);
6869
6870 if (!eld[0])
6871 return;
6872
6873 len = min_t(uint8_t, eld[2], len);
6874 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6875 for (i = 0; i < len; i++)
6876 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6877
6878 i = I915_READ(G4X_AUD_CNTL_ST);
6879 i |= eldv;
6880 I915_WRITE(G4X_AUD_CNTL_ST, i);
6881 }
6882
6883 static void haswell_write_eld(struct drm_connector *connector,
6884 struct drm_crtc *crtc,
6885 struct drm_display_mode *mode)
6886 {
6887 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6888 uint8_t *eld = connector->eld;
6889 struct drm_device *dev = crtc->dev;
6890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6891 uint32_t eldv;
6892 uint32_t i;
6893 int len;
6894 int pipe = to_intel_crtc(crtc)->pipe;
6895 int tmp;
6896
6897 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6898 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6899 int aud_config = HSW_AUD_CFG(pipe);
6900 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6901
6902
6903 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6904
6905 /* Audio output enable */
6906 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6907 tmp = I915_READ(aud_cntrl_st2);
6908 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6909 I915_WRITE(aud_cntrl_st2, tmp);
6910
6911 /* Wait for 1 vertical blank */
6912 intel_wait_for_vblank(dev, pipe);
6913
6914 /* Set ELD valid state */
6915 tmp = I915_READ(aud_cntrl_st2);
6916 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
6917 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6918 I915_WRITE(aud_cntrl_st2, tmp);
6919 tmp = I915_READ(aud_cntrl_st2);
6920 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
6921
6922 /* Enable HDMI mode */
6923 tmp = I915_READ(aud_config);
6924 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
6925 /* clear N_programing_enable and N_value_index */
6926 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6927 I915_WRITE(aud_config, tmp);
6928
6929 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6930
6931 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6932 intel_crtc->eld_vld = true;
6933
6934 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6935 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6936 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6937 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6938 } else {
6939 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
6940 }
6941
6942 if (intel_eld_uptodate(connector,
6943 aud_cntrl_st2, eldv,
6944 aud_cntl_st, IBX_ELD_ADDRESS,
6945 hdmiw_hdmiedid))
6946 return;
6947
6948 i = I915_READ(aud_cntrl_st2);
6949 i &= ~eldv;
6950 I915_WRITE(aud_cntrl_st2, i);
6951
6952 if (!eld[0])
6953 return;
6954
6955 i = I915_READ(aud_cntl_st);
6956 i &= ~IBX_ELD_ADDRESS;
6957 I915_WRITE(aud_cntl_st, i);
6958 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6959 DRM_DEBUG_DRIVER("port num:%d\n", i);
6960
6961 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6962 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6963 for (i = 0; i < len; i++)
6964 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6965
6966 i = I915_READ(aud_cntrl_st2);
6967 i |= eldv;
6968 I915_WRITE(aud_cntrl_st2, i);
6969
6970 }
6971
6972 static void ironlake_write_eld(struct drm_connector *connector,
6973 struct drm_crtc *crtc,
6974 struct drm_display_mode *mode)
6975 {
6976 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6977 uint8_t *eld = connector->eld;
6978 uint32_t eldv;
6979 uint32_t i;
6980 int len;
6981 int hdmiw_hdmiedid;
6982 int aud_config;
6983 int aud_cntl_st;
6984 int aud_cntrl_st2;
6985 int pipe = to_intel_crtc(crtc)->pipe;
6986
6987 if (HAS_PCH_IBX(connector->dev)) {
6988 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6989 aud_config = IBX_AUD_CFG(pipe);
6990 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6991 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6992 } else if (IS_VALLEYVIEW(connector->dev)) {
6993 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
6994 aud_config = VLV_AUD_CFG(pipe);
6995 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
6996 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
6997 } else {
6998 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6999 aud_config = CPT_AUD_CFG(pipe);
7000 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7001 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7002 }
7003
7004 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7005
7006 if (IS_VALLEYVIEW(connector->dev)) {
7007 struct intel_encoder *intel_encoder;
7008 struct intel_digital_port *intel_dig_port;
7009
7010 intel_encoder = intel_attached_encoder(connector);
7011 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7012 i = intel_dig_port->port;
7013 } else {
7014 i = I915_READ(aud_cntl_st);
7015 i = (i >> 29) & DIP_PORT_SEL_MASK;
7016 /* DIP_Port_Select, 0x1 = PortB */
7017 }
7018
7019 if (!i) {
7020 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7021 /* operate blindly on all ports */
7022 eldv = IBX_ELD_VALIDB;
7023 eldv |= IBX_ELD_VALIDB << 4;
7024 eldv |= IBX_ELD_VALIDB << 8;
7025 } else {
7026 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7027 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7028 }
7029
7030 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7031 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7032 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7033 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7034 } else {
7035 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7036 }
7037
7038 if (intel_eld_uptodate(connector,
7039 aud_cntrl_st2, eldv,
7040 aud_cntl_st, IBX_ELD_ADDRESS,
7041 hdmiw_hdmiedid))
7042 return;
7043
7044 i = I915_READ(aud_cntrl_st2);
7045 i &= ~eldv;
7046 I915_WRITE(aud_cntrl_st2, i);
7047
7048 if (!eld[0])
7049 return;
7050
7051 i = I915_READ(aud_cntl_st);
7052 i &= ~IBX_ELD_ADDRESS;
7053 I915_WRITE(aud_cntl_st, i);
7054
7055 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7056 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7057 for (i = 0; i < len; i++)
7058 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7059
7060 i = I915_READ(aud_cntrl_st2);
7061 i |= eldv;
7062 I915_WRITE(aud_cntrl_st2, i);
7063 }
7064
7065 void intel_write_eld(struct drm_encoder *encoder,
7066 struct drm_display_mode *mode)
7067 {
7068 struct drm_crtc *crtc = encoder->crtc;
7069 struct drm_connector *connector;
7070 struct drm_device *dev = encoder->dev;
7071 struct drm_i915_private *dev_priv = dev->dev_private;
7072
7073 connector = drm_select_eld(encoder, mode);
7074 if (!connector)
7075 return;
7076
7077 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7078 connector->base.id,
7079 drm_get_connector_name(connector),
7080 connector->encoder->base.id,
7081 drm_get_encoder_name(connector->encoder));
7082
7083 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7084
7085 if (dev_priv->display.write_eld)
7086 dev_priv->display.write_eld(connector, crtc, mode);
7087 }
7088
7089 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7090 {
7091 struct drm_device *dev = crtc->dev;
7092 struct drm_i915_private *dev_priv = dev->dev_private;
7093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7094 bool visible = base != 0;
7095 u32 cntl;
7096
7097 if (intel_crtc->cursor_visible == visible)
7098 return;
7099
7100 cntl = I915_READ(_CURACNTR);
7101 if (visible) {
7102 /* On these chipsets we can only modify the base whilst
7103 * the cursor is disabled.
7104 */
7105 I915_WRITE(_CURABASE, base);
7106
7107 cntl &= ~(CURSOR_FORMAT_MASK);
7108 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7109 cntl |= CURSOR_ENABLE |
7110 CURSOR_GAMMA_ENABLE |
7111 CURSOR_FORMAT_ARGB;
7112 } else
7113 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7114 I915_WRITE(_CURACNTR, cntl);
7115
7116 intel_crtc->cursor_visible = visible;
7117 }
7118
7119 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7120 {
7121 struct drm_device *dev = crtc->dev;
7122 struct drm_i915_private *dev_priv = dev->dev_private;
7123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7124 int pipe = intel_crtc->pipe;
7125 bool visible = base != 0;
7126
7127 if (intel_crtc->cursor_visible != visible) {
7128 uint32_t cntl = I915_READ(CURCNTR(pipe));
7129 if (base) {
7130 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7131 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7132 cntl |= pipe << 28; /* Connect to correct pipe */
7133 } else {
7134 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7135 cntl |= CURSOR_MODE_DISABLE;
7136 }
7137 I915_WRITE(CURCNTR(pipe), cntl);
7138
7139 intel_crtc->cursor_visible = visible;
7140 }
7141 /* and commit changes on next vblank */
7142 I915_WRITE(CURBASE(pipe), base);
7143 }
7144
7145 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7146 {
7147 struct drm_device *dev = crtc->dev;
7148 struct drm_i915_private *dev_priv = dev->dev_private;
7149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7150 int pipe = intel_crtc->pipe;
7151 bool visible = base != 0;
7152
7153 if (intel_crtc->cursor_visible != visible) {
7154 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7155 if (base) {
7156 cntl &= ~CURSOR_MODE;
7157 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7158 } else {
7159 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7160 cntl |= CURSOR_MODE_DISABLE;
7161 }
7162 if (IS_HASWELL(dev)) {
7163 cntl |= CURSOR_PIPE_CSC_ENABLE;
7164 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7165 }
7166 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7167
7168 intel_crtc->cursor_visible = visible;
7169 }
7170 /* and commit changes on next vblank */
7171 I915_WRITE(CURBASE_IVB(pipe), base);
7172 }
7173
7174 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7175 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7176 bool on)
7177 {
7178 struct drm_device *dev = crtc->dev;
7179 struct drm_i915_private *dev_priv = dev->dev_private;
7180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7181 int pipe = intel_crtc->pipe;
7182 int x = intel_crtc->cursor_x;
7183 int y = intel_crtc->cursor_y;
7184 u32 base = 0, pos = 0;
7185 bool visible;
7186
7187 if (on)
7188 base = intel_crtc->cursor_addr;
7189
7190 if (x >= intel_crtc->config.pipe_src_w)
7191 base = 0;
7192
7193 if (y >= intel_crtc->config.pipe_src_h)
7194 base = 0;
7195
7196 if (x < 0) {
7197 if (x + intel_crtc->cursor_width <= 0)
7198 base = 0;
7199
7200 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7201 x = -x;
7202 }
7203 pos |= x << CURSOR_X_SHIFT;
7204
7205 if (y < 0) {
7206 if (y + intel_crtc->cursor_height <= 0)
7207 base = 0;
7208
7209 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7210 y = -y;
7211 }
7212 pos |= y << CURSOR_Y_SHIFT;
7213
7214 visible = base != 0;
7215 if (!visible && !intel_crtc->cursor_visible)
7216 return;
7217
7218 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
7219 I915_WRITE(CURPOS_IVB(pipe), pos);
7220 ivb_update_cursor(crtc, base);
7221 } else {
7222 I915_WRITE(CURPOS(pipe), pos);
7223 if (IS_845G(dev) || IS_I865G(dev))
7224 i845_update_cursor(crtc, base);
7225 else
7226 i9xx_update_cursor(crtc, base);
7227 }
7228 }
7229
7230 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7231 struct drm_file *file,
7232 uint32_t handle,
7233 uint32_t width, uint32_t height)
7234 {
7235 struct drm_device *dev = crtc->dev;
7236 struct drm_i915_private *dev_priv = dev->dev_private;
7237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7238 struct drm_i915_gem_object *obj;
7239 uint32_t addr;
7240 int ret;
7241
7242 /* if we want to turn off the cursor ignore width and height */
7243 if (!handle) {
7244 DRM_DEBUG_KMS("cursor off\n");
7245 addr = 0;
7246 obj = NULL;
7247 mutex_lock(&dev->struct_mutex);
7248 goto finish;
7249 }
7250
7251 /* Currently we only support 64x64 cursors */
7252 if (width != 64 || height != 64) {
7253 DRM_ERROR("we currently only support 64x64 cursors\n");
7254 return -EINVAL;
7255 }
7256
7257 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7258 if (&obj->base == NULL)
7259 return -ENOENT;
7260
7261 if (obj->base.size < width * height * 4) {
7262 DRM_ERROR("buffer is to small\n");
7263 ret = -ENOMEM;
7264 goto fail;
7265 }
7266
7267 /* we only need to pin inside GTT if cursor is non-phy */
7268 mutex_lock(&dev->struct_mutex);
7269 if (!dev_priv->info->cursor_needs_physical) {
7270 unsigned alignment;
7271
7272 if (obj->tiling_mode) {
7273 DRM_ERROR("cursor cannot be tiled\n");
7274 ret = -EINVAL;
7275 goto fail_locked;
7276 }
7277
7278 /* Note that the w/a also requires 2 PTE of padding following
7279 * the bo. We currently fill all unused PTE with the shadow
7280 * page and so we should always have valid PTE following the
7281 * cursor preventing the VT-d warning.
7282 */
7283 alignment = 0;
7284 if (need_vtd_wa(dev))
7285 alignment = 64*1024;
7286
7287 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7288 if (ret) {
7289 DRM_ERROR("failed to move cursor bo into the GTT\n");
7290 goto fail_locked;
7291 }
7292
7293 ret = i915_gem_object_put_fence(obj);
7294 if (ret) {
7295 DRM_ERROR("failed to release fence for cursor");
7296 goto fail_unpin;
7297 }
7298
7299 addr = i915_gem_obj_ggtt_offset(obj);
7300 } else {
7301 int align = IS_I830(dev) ? 16 * 1024 : 256;
7302 ret = i915_gem_attach_phys_object(dev, obj,
7303 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7304 align);
7305 if (ret) {
7306 DRM_ERROR("failed to attach phys object\n");
7307 goto fail_locked;
7308 }
7309 addr = obj->phys_obj->handle->busaddr;
7310 }
7311
7312 if (IS_GEN2(dev))
7313 I915_WRITE(CURSIZE, (height << 12) | width);
7314
7315 finish:
7316 if (intel_crtc->cursor_bo) {
7317 if (dev_priv->info->cursor_needs_physical) {
7318 if (intel_crtc->cursor_bo != obj)
7319 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7320 } else
7321 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7322 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7323 }
7324
7325 mutex_unlock(&dev->struct_mutex);
7326
7327 intel_crtc->cursor_addr = addr;
7328 intel_crtc->cursor_bo = obj;
7329 intel_crtc->cursor_width = width;
7330 intel_crtc->cursor_height = height;
7331
7332 if (intel_crtc->active)
7333 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7334
7335 return 0;
7336 fail_unpin:
7337 i915_gem_object_unpin_from_display_plane(obj);
7338 fail_locked:
7339 mutex_unlock(&dev->struct_mutex);
7340 fail:
7341 drm_gem_object_unreference_unlocked(&obj->base);
7342 return ret;
7343 }
7344
7345 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7346 {
7347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7348
7349 intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7350 intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7351
7352 if (intel_crtc->active)
7353 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7354
7355 return 0;
7356 }
7357
7358 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7359 u16 *blue, uint32_t start, uint32_t size)
7360 {
7361 int end = (start + size > 256) ? 256 : start + size, i;
7362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7363
7364 for (i = start; i < end; i++) {
7365 intel_crtc->lut_r[i] = red[i] >> 8;
7366 intel_crtc->lut_g[i] = green[i] >> 8;
7367 intel_crtc->lut_b[i] = blue[i] >> 8;
7368 }
7369
7370 intel_crtc_load_lut(crtc);
7371 }
7372
7373 /* VESA 640x480x72Hz mode to set on the pipe */
7374 static struct drm_display_mode load_detect_mode = {
7375 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7376 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7377 };
7378
7379 static struct drm_framebuffer *
7380 intel_framebuffer_create(struct drm_device *dev,
7381 struct drm_mode_fb_cmd2 *mode_cmd,
7382 struct drm_i915_gem_object *obj)
7383 {
7384 struct intel_framebuffer *intel_fb;
7385 int ret;
7386
7387 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7388 if (!intel_fb) {
7389 drm_gem_object_unreference_unlocked(&obj->base);
7390 return ERR_PTR(-ENOMEM);
7391 }
7392
7393 ret = i915_mutex_lock_interruptible(dev);
7394 if (ret)
7395 goto err;
7396
7397 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7398 mutex_unlock(&dev->struct_mutex);
7399 if (ret)
7400 goto err;
7401
7402 return &intel_fb->base;
7403 err:
7404 drm_gem_object_unreference_unlocked(&obj->base);
7405 kfree(intel_fb);
7406
7407 return ERR_PTR(ret);
7408 }
7409
7410 static u32
7411 intel_framebuffer_pitch_for_width(int width, int bpp)
7412 {
7413 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7414 return ALIGN(pitch, 64);
7415 }
7416
7417 static u32
7418 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7419 {
7420 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7421 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7422 }
7423
7424 static struct drm_framebuffer *
7425 intel_framebuffer_create_for_mode(struct drm_device *dev,
7426 struct drm_display_mode *mode,
7427 int depth, int bpp)
7428 {
7429 struct drm_i915_gem_object *obj;
7430 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7431
7432 obj = i915_gem_alloc_object(dev,
7433 intel_framebuffer_size_for_mode(mode, bpp));
7434 if (obj == NULL)
7435 return ERR_PTR(-ENOMEM);
7436
7437 mode_cmd.width = mode->hdisplay;
7438 mode_cmd.height = mode->vdisplay;
7439 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7440 bpp);
7441 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7442
7443 return intel_framebuffer_create(dev, &mode_cmd, obj);
7444 }
7445
7446 static struct drm_framebuffer *
7447 mode_fits_in_fbdev(struct drm_device *dev,
7448 struct drm_display_mode *mode)
7449 {
7450 #ifdef CONFIG_DRM_I915_FBDEV
7451 struct drm_i915_private *dev_priv = dev->dev_private;
7452 struct drm_i915_gem_object *obj;
7453 struct drm_framebuffer *fb;
7454
7455 if (dev_priv->fbdev == NULL)
7456 return NULL;
7457
7458 obj = dev_priv->fbdev->ifb.obj;
7459 if (obj == NULL)
7460 return NULL;
7461
7462 fb = &dev_priv->fbdev->ifb.base;
7463 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7464 fb->bits_per_pixel))
7465 return NULL;
7466
7467 if (obj->base.size < mode->vdisplay * fb->pitches[0])
7468 return NULL;
7469
7470 return fb;
7471 #else
7472 return NULL;
7473 #endif
7474 }
7475
7476 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7477 struct drm_display_mode *mode,
7478 struct intel_load_detect_pipe *old)
7479 {
7480 struct intel_crtc *intel_crtc;
7481 struct intel_encoder *intel_encoder =
7482 intel_attached_encoder(connector);
7483 struct drm_crtc *possible_crtc;
7484 struct drm_encoder *encoder = &intel_encoder->base;
7485 struct drm_crtc *crtc = NULL;
7486 struct drm_device *dev = encoder->dev;
7487 struct drm_framebuffer *fb;
7488 int i = -1;
7489
7490 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7491 connector->base.id, drm_get_connector_name(connector),
7492 encoder->base.id, drm_get_encoder_name(encoder));
7493
7494 /*
7495 * Algorithm gets a little messy:
7496 *
7497 * - if the connector already has an assigned crtc, use it (but make
7498 * sure it's on first)
7499 *
7500 * - try to find the first unused crtc that can drive this connector,
7501 * and use that if we find one
7502 */
7503
7504 /* See if we already have a CRTC for this connector */
7505 if (encoder->crtc) {
7506 crtc = encoder->crtc;
7507
7508 mutex_lock(&crtc->mutex);
7509
7510 old->dpms_mode = connector->dpms;
7511 old->load_detect_temp = false;
7512
7513 /* Make sure the crtc and connector are running */
7514 if (connector->dpms != DRM_MODE_DPMS_ON)
7515 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7516
7517 return true;
7518 }
7519
7520 /* Find an unused one (if possible) */
7521 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7522 i++;
7523 if (!(encoder->possible_crtcs & (1 << i)))
7524 continue;
7525 if (!possible_crtc->enabled) {
7526 crtc = possible_crtc;
7527 break;
7528 }
7529 }
7530
7531 /*
7532 * If we didn't find an unused CRTC, don't use any.
7533 */
7534 if (!crtc) {
7535 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7536 return false;
7537 }
7538
7539 mutex_lock(&crtc->mutex);
7540 intel_encoder->new_crtc = to_intel_crtc(crtc);
7541 to_intel_connector(connector)->new_encoder = intel_encoder;
7542
7543 intel_crtc = to_intel_crtc(crtc);
7544 old->dpms_mode = connector->dpms;
7545 old->load_detect_temp = true;
7546 old->release_fb = NULL;
7547
7548 if (!mode)
7549 mode = &load_detect_mode;
7550
7551 /* We need a framebuffer large enough to accommodate all accesses
7552 * that the plane may generate whilst we perform load detection.
7553 * We can not rely on the fbcon either being present (we get called
7554 * during its initialisation to detect all boot displays, or it may
7555 * not even exist) or that it is large enough to satisfy the
7556 * requested mode.
7557 */
7558 fb = mode_fits_in_fbdev(dev, mode);
7559 if (fb == NULL) {
7560 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7561 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7562 old->release_fb = fb;
7563 } else
7564 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7565 if (IS_ERR(fb)) {
7566 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7567 mutex_unlock(&crtc->mutex);
7568 return false;
7569 }
7570
7571 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7572 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7573 if (old->release_fb)
7574 old->release_fb->funcs->destroy(old->release_fb);
7575 mutex_unlock(&crtc->mutex);
7576 return false;
7577 }
7578
7579 /* let the connector get through one full cycle before testing */
7580 intel_wait_for_vblank(dev, intel_crtc->pipe);
7581 return true;
7582 }
7583
7584 void intel_release_load_detect_pipe(struct drm_connector *connector,
7585 struct intel_load_detect_pipe *old)
7586 {
7587 struct intel_encoder *intel_encoder =
7588 intel_attached_encoder(connector);
7589 struct drm_encoder *encoder = &intel_encoder->base;
7590 struct drm_crtc *crtc = encoder->crtc;
7591
7592 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7593 connector->base.id, drm_get_connector_name(connector),
7594 encoder->base.id, drm_get_encoder_name(encoder));
7595
7596 if (old->load_detect_temp) {
7597 to_intel_connector(connector)->new_encoder = NULL;
7598 intel_encoder->new_crtc = NULL;
7599 intel_set_mode(crtc, NULL, 0, 0, NULL);
7600
7601 if (old->release_fb) {
7602 drm_framebuffer_unregister_private(old->release_fb);
7603 drm_framebuffer_unreference(old->release_fb);
7604 }
7605
7606 mutex_unlock(&crtc->mutex);
7607 return;
7608 }
7609
7610 /* Switch crtc and encoder back off if necessary */
7611 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7612 connector->funcs->dpms(connector, old->dpms_mode);
7613
7614 mutex_unlock(&crtc->mutex);
7615 }
7616
7617 static int i9xx_pll_refclk(struct drm_device *dev,
7618 const struct intel_crtc_config *pipe_config)
7619 {
7620 struct drm_i915_private *dev_priv = dev->dev_private;
7621 u32 dpll = pipe_config->dpll_hw_state.dpll;
7622
7623 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7624 return dev_priv->vbt.lvds_ssc_freq * 1000;
7625 else if (HAS_PCH_SPLIT(dev))
7626 return 120000;
7627 else if (!IS_GEN2(dev))
7628 return 96000;
7629 else
7630 return 48000;
7631 }
7632
7633 /* Returns the clock of the currently programmed mode of the given pipe. */
7634 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7635 struct intel_crtc_config *pipe_config)
7636 {
7637 struct drm_device *dev = crtc->base.dev;
7638 struct drm_i915_private *dev_priv = dev->dev_private;
7639 int pipe = pipe_config->cpu_transcoder;
7640 u32 dpll = pipe_config->dpll_hw_state.dpll;
7641 u32 fp;
7642 intel_clock_t clock;
7643 int refclk = i9xx_pll_refclk(dev, pipe_config);
7644
7645 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7646 fp = pipe_config->dpll_hw_state.fp0;
7647 else
7648 fp = pipe_config->dpll_hw_state.fp1;
7649
7650 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7651 if (IS_PINEVIEW(dev)) {
7652 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7653 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7654 } else {
7655 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7656 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7657 }
7658
7659 if (!IS_GEN2(dev)) {
7660 if (IS_PINEVIEW(dev))
7661 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7662 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7663 else
7664 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7665 DPLL_FPA01_P1_POST_DIV_SHIFT);
7666
7667 switch (dpll & DPLL_MODE_MASK) {
7668 case DPLLB_MODE_DAC_SERIAL:
7669 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7670 5 : 10;
7671 break;
7672 case DPLLB_MODE_LVDS:
7673 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7674 7 : 14;
7675 break;
7676 default:
7677 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7678 "mode\n", (int)(dpll & DPLL_MODE_MASK));
7679 return;
7680 }
7681
7682 if (IS_PINEVIEW(dev))
7683 pineview_clock(refclk, &clock);
7684 else
7685 i9xx_clock(refclk, &clock);
7686 } else {
7687 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7688
7689 if (is_lvds) {
7690 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7691 DPLL_FPA01_P1_POST_DIV_SHIFT);
7692 clock.p2 = 14;
7693 } else {
7694 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7695 clock.p1 = 2;
7696 else {
7697 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7698 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7699 }
7700 if (dpll & PLL_P2_DIVIDE_BY_4)
7701 clock.p2 = 4;
7702 else
7703 clock.p2 = 2;
7704 }
7705
7706 i9xx_clock(refclk, &clock);
7707 }
7708
7709 /*
7710 * This value includes pixel_multiplier. We will use
7711 * port_clock to compute adjusted_mode.crtc_clock in the
7712 * encoder's get_config() function.
7713 */
7714 pipe_config->port_clock = clock.dot;
7715 }
7716
7717 int intel_dotclock_calculate(int link_freq,
7718 const struct intel_link_m_n *m_n)
7719 {
7720 /*
7721 * The calculation for the data clock is:
7722 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7723 * But we want to avoid losing precison if possible, so:
7724 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7725 *
7726 * and the link clock is simpler:
7727 * link_clock = (m * link_clock) / n
7728 */
7729
7730 if (!m_n->link_n)
7731 return 0;
7732
7733 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7734 }
7735
7736 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7737 struct intel_crtc_config *pipe_config)
7738 {
7739 struct drm_device *dev = crtc->base.dev;
7740
7741 /* read out port_clock from the DPLL */
7742 i9xx_crtc_clock_get(crtc, pipe_config);
7743
7744 /*
7745 * This value does not include pixel_multiplier.
7746 * We will check that port_clock and adjusted_mode.crtc_clock
7747 * agree once we know their relationship in the encoder's
7748 * get_config() function.
7749 */
7750 pipe_config->adjusted_mode.crtc_clock =
7751 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7752 &pipe_config->fdi_m_n);
7753 }
7754
7755 /** Returns the currently programmed mode of the given pipe. */
7756 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7757 struct drm_crtc *crtc)
7758 {
7759 struct drm_i915_private *dev_priv = dev->dev_private;
7760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7761 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7762 struct drm_display_mode *mode;
7763 struct intel_crtc_config pipe_config;
7764 int htot = I915_READ(HTOTAL(cpu_transcoder));
7765 int hsync = I915_READ(HSYNC(cpu_transcoder));
7766 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7767 int vsync = I915_READ(VSYNC(cpu_transcoder));
7768 enum pipe pipe = intel_crtc->pipe;
7769
7770 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7771 if (!mode)
7772 return NULL;
7773
7774 /*
7775 * Construct a pipe_config sufficient for getting the clock info
7776 * back out of crtc_clock_get.
7777 *
7778 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7779 * to use a real value here instead.
7780 */
7781 pipe_config.cpu_transcoder = (enum transcoder) pipe;
7782 pipe_config.pixel_multiplier = 1;
7783 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7784 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7785 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
7786 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7787
7788 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
7789 mode->hdisplay = (htot & 0xffff) + 1;
7790 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7791 mode->hsync_start = (hsync & 0xffff) + 1;
7792 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7793 mode->vdisplay = (vtot & 0xffff) + 1;
7794 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7795 mode->vsync_start = (vsync & 0xffff) + 1;
7796 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7797
7798 drm_mode_set_name(mode);
7799
7800 return mode;
7801 }
7802
7803 static void intel_increase_pllclock(struct drm_crtc *crtc)
7804 {
7805 struct drm_device *dev = crtc->dev;
7806 drm_i915_private_t *dev_priv = dev->dev_private;
7807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7808 int pipe = intel_crtc->pipe;
7809 int dpll_reg = DPLL(pipe);
7810 int dpll;
7811
7812 if (HAS_PCH_SPLIT(dev))
7813 return;
7814
7815 if (!dev_priv->lvds_downclock_avail)
7816 return;
7817
7818 dpll = I915_READ(dpll_reg);
7819 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7820 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7821
7822 assert_panel_unlocked(dev_priv, pipe);
7823
7824 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7825 I915_WRITE(dpll_reg, dpll);
7826 intel_wait_for_vblank(dev, pipe);
7827
7828 dpll = I915_READ(dpll_reg);
7829 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7830 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7831 }
7832 }
7833
7834 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7835 {
7836 struct drm_device *dev = crtc->dev;
7837 drm_i915_private_t *dev_priv = dev->dev_private;
7838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7839
7840 if (HAS_PCH_SPLIT(dev))
7841 return;
7842
7843 if (!dev_priv->lvds_downclock_avail)
7844 return;
7845
7846 /*
7847 * Since this is called by a timer, we should never get here in
7848 * the manual case.
7849 */
7850 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7851 int pipe = intel_crtc->pipe;
7852 int dpll_reg = DPLL(pipe);
7853 int dpll;
7854
7855 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7856
7857 assert_panel_unlocked(dev_priv, pipe);
7858
7859 dpll = I915_READ(dpll_reg);
7860 dpll |= DISPLAY_RATE_SELECT_FPA1;
7861 I915_WRITE(dpll_reg, dpll);
7862 intel_wait_for_vblank(dev, pipe);
7863 dpll = I915_READ(dpll_reg);
7864 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7865 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7866 }
7867
7868 }
7869
7870 void intel_mark_busy(struct drm_device *dev)
7871 {
7872 struct drm_i915_private *dev_priv = dev->dev_private;
7873
7874 hsw_package_c8_gpu_busy(dev_priv);
7875 i915_update_gfx_val(dev_priv);
7876 }
7877
7878 void intel_mark_idle(struct drm_device *dev)
7879 {
7880 struct drm_i915_private *dev_priv = dev->dev_private;
7881 struct drm_crtc *crtc;
7882
7883 hsw_package_c8_gpu_idle(dev_priv);
7884
7885 if (!i915_powersave)
7886 return;
7887
7888 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7889 if (!crtc->fb)
7890 continue;
7891
7892 intel_decrease_pllclock(crtc);
7893 }
7894
7895 if (dev_priv->info->gen >= 6)
7896 gen6_rps_idle(dev->dev_private);
7897 }
7898
7899 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7900 struct intel_ring_buffer *ring)
7901 {
7902 struct drm_device *dev = obj->base.dev;
7903 struct drm_crtc *crtc;
7904
7905 if (!i915_powersave)
7906 return;
7907
7908 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7909 if (!crtc->fb)
7910 continue;
7911
7912 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7913 continue;
7914
7915 intel_increase_pllclock(crtc);
7916 if (ring && intel_fbc_enabled(dev))
7917 ring->fbc_dirty = true;
7918 }
7919 }
7920
7921 static void intel_crtc_destroy(struct drm_crtc *crtc)
7922 {
7923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7924 struct drm_device *dev = crtc->dev;
7925 struct intel_unpin_work *work;
7926 unsigned long flags;
7927
7928 spin_lock_irqsave(&dev->event_lock, flags);
7929 work = intel_crtc->unpin_work;
7930 intel_crtc->unpin_work = NULL;
7931 spin_unlock_irqrestore(&dev->event_lock, flags);
7932
7933 if (work) {
7934 cancel_work_sync(&work->work);
7935 kfree(work);
7936 }
7937
7938 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7939
7940 drm_crtc_cleanup(crtc);
7941
7942 kfree(intel_crtc);
7943 }
7944
7945 static void intel_unpin_work_fn(struct work_struct *__work)
7946 {
7947 struct intel_unpin_work *work =
7948 container_of(__work, struct intel_unpin_work, work);
7949 struct drm_device *dev = work->crtc->dev;
7950
7951 mutex_lock(&dev->struct_mutex);
7952 intel_unpin_fb_obj(work->old_fb_obj);
7953 drm_gem_object_unreference(&work->pending_flip_obj->base);
7954 drm_gem_object_unreference(&work->old_fb_obj->base);
7955
7956 intel_update_fbc(dev);
7957 mutex_unlock(&dev->struct_mutex);
7958
7959 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7960 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7961
7962 kfree(work);
7963 }
7964
7965 static void do_intel_finish_page_flip(struct drm_device *dev,
7966 struct drm_crtc *crtc)
7967 {
7968 drm_i915_private_t *dev_priv = dev->dev_private;
7969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7970 struct intel_unpin_work *work;
7971 unsigned long flags;
7972
7973 /* Ignore early vblank irqs */
7974 if (intel_crtc == NULL)
7975 return;
7976
7977 spin_lock_irqsave(&dev->event_lock, flags);
7978 work = intel_crtc->unpin_work;
7979
7980 /* Ensure we don't miss a work->pending update ... */
7981 smp_rmb();
7982
7983 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7984 spin_unlock_irqrestore(&dev->event_lock, flags);
7985 return;
7986 }
7987
7988 /* and that the unpin work is consistent wrt ->pending. */
7989 smp_rmb();
7990
7991 intel_crtc->unpin_work = NULL;
7992
7993 if (work->event)
7994 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7995
7996 drm_vblank_put(dev, intel_crtc->pipe);
7997
7998 spin_unlock_irqrestore(&dev->event_lock, flags);
7999
8000 wake_up_all(&dev_priv->pending_flip_queue);
8001
8002 queue_work(dev_priv->wq, &work->work);
8003
8004 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8005 }
8006
8007 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8008 {
8009 drm_i915_private_t *dev_priv = dev->dev_private;
8010 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8011
8012 do_intel_finish_page_flip(dev, crtc);
8013 }
8014
8015 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8016 {
8017 drm_i915_private_t *dev_priv = dev->dev_private;
8018 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8019
8020 do_intel_finish_page_flip(dev, crtc);
8021 }
8022
8023 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8024 {
8025 drm_i915_private_t *dev_priv = dev->dev_private;
8026 struct intel_crtc *intel_crtc =
8027 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8028 unsigned long flags;
8029
8030 /* NB: An MMIO update of the plane base pointer will also
8031 * generate a page-flip completion irq, i.e. every modeset
8032 * is also accompanied by a spurious intel_prepare_page_flip().
8033 */
8034 spin_lock_irqsave(&dev->event_lock, flags);
8035 if (intel_crtc->unpin_work)
8036 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8037 spin_unlock_irqrestore(&dev->event_lock, flags);
8038 }
8039
8040 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8041 {
8042 /* Ensure that the work item is consistent when activating it ... */
8043 smp_wmb();
8044 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8045 /* and that it is marked active as soon as the irq could fire. */
8046 smp_wmb();
8047 }
8048
8049 static int intel_gen2_queue_flip(struct drm_device *dev,
8050 struct drm_crtc *crtc,
8051 struct drm_framebuffer *fb,
8052 struct drm_i915_gem_object *obj,
8053 uint32_t flags)
8054 {
8055 struct drm_i915_private *dev_priv = dev->dev_private;
8056 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8057 u32 flip_mask;
8058 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8059 int ret;
8060
8061 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8062 if (ret)
8063 goto err;
8064
8065 ret = intel_ring_begin(ring, 6);
8066 if (ret)
8067 goto err_unpin;
8068
8069 /* Can't queue multiple flips, so wait for the previous
8070 * one to finish before executing the next.
8071 */
8072 if (intel_crtc->plane)
8073 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8074 else
8075 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8076 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8077 intel_ring_emit(ring, MI_NOOP);
8078 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8079 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8080 intel_ring_emit(ring, fb->pitches[0]);
8081 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8082 intel_ring_emit(ring, 0); /* aux display base address, unused */
8083
8084 intel_mark_page_flip_active(intel_crtc);
8085 __intel_ring_advance(ring);
8086 return 0;
8087
8088 err_unpin:
8089 intel_unpin_fb_obj(obj);
8090 err:
8091 return ret;
8092 }
8093
8094 static int intel_gen3_queue_flip(struct drm_device *dev,
8095 struct drm_crtc *crtc,
8096 struct drm_framebuffer *fb,
8097 struct drm_i915_gem_object *obj,
8098 uint32_t flags)
8099 {
8100 struct drm_i915_private *dev_priv = dev->dev_private;
8101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8102 u32 flip_mask;
8103 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8104 int ret;
8105
8106 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8107 if (ret)
8108 goto err;
8109
8110 ret = intel_ring_begin(ring, 6);
8111 if (ret)
8112 goto err_unpin;
8113
8114 if (intel_crtc->plane)
8115 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8116 else
8117 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8118 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8119 intel_ring_emit(ring, MI_NOOP);
8120 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8121 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8122 intel_ring_emit(ring, fb->pitches[0]);
8123 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8124 intel_ring_emit(ring, MI_NOOP);
8125
8126 intel_mark_page_flip_active(intel_crtc);
8127 __intel_ring_advance(ring);
8128 return 0;
8129
8130 err_unpin:
8131 intel_unpin_fb_obj(obj);
8132 err:
8133 return ret;
8134 }
8135
8136 static int intel_gen4_queue_flip(struct drm_device *dev,
8137 struct drm_crtc *crtc,
8138 struct drm_framebuffer *fb,
8139 struct drm_i915_gem_object *obj,
8140 uint32_t flags)
8141 {
8142 struct drm_i915_private *dev_priv = dev->dev_private;
8143 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8144 uint32_t pf, pipesrc;
8145 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8146 int ret;
8147
8148 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8149 if (ret)
8150 goto err;
8151
8152 ret = intel_ring_begin(ring, 4);
8153 if (ret)
8154 goto err_unpin;
8155
8156 /* i965+ uses the linear or tiled offsets from the
8157 * Display Registers (which do not change across a page-flip)
8158 * so we need only reprogram the base address.
8159 */
8160 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8161 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8162 intel_ring_emit(ring, fb->pitches[0]);
8163 intel_ring_emit(ring,
8164 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8165 obj->tiling_mode);
8166
8167 /* XXX Enabling the panel-fitter across page-flip is so far
8168 * untested on non-native modes, so ignore it for now.
8169 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8170 */
8171 pf = 0;
8172 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8173 intel_ring_emit(ring, pf | pipesrc);
8174
8175 intel_mark_page_flip_active(intel_crtc);
8176 __intel_ring_advance(ring);
8177 return 0;
8178
8179 err_unpin:
8180 intel_unpin_fb_obj(obj);
8181 err:
8182 return ret;
8183 }
8184
8185 static int intel_gen6_queue_flip(struct drm_device *dev,
8186 struct drm_crtc *crtc,
8187 struct drm_framebuffer *fb,
8188 struct drm_i915_gem_object *obj,
8189 uint32_t flags)
8190 {
8191 struct drm_i915_private *dev_priv = dev->dev_private;
8192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8193 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8194 uint32_t pf, pipesrc;
8195 int ret;
8196
8197 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8198 if (ret)
8199 goto err;
8200
8201 ret = intel_ring_begin(ring, 4);
8202 if (ret)
8203 goto err_unpin;
8204
8205 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8206 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8207 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8208 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8209
8210 /* Contrary to the suggestions in the documentation,
8211 * "Enable Panel Fitter" does not seem to be required when page
8212 * flipping with a non-native mode, and worse causes a normal
8213 * modeset to fail.
8214 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8215 */
8216 pf = 0;
8217 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8218 intel_ring_emit(ring, pf | pipesrc);
8219
8220 intel_mark_page_flip_active(intel_crtc);
8221 __intel_ring_advance(ring);
8222 return 0;
8223
8224 err_unpin:
8225 intel_unpin_fb_obj(obj);
8226 err:
8227 return ret;
8228 }
8229
8230 static int intel_gen7_queue_flip(struct drm_device *dev,
8231 struct drm_crtc *crtc,
8232 struct drm_framebuffer *fb,
8233 struct drm_i915_gem_object *obj,
8234 uint32_t flags)
8235 {
8236 struct drm_i915_private *dev_priv = dev->dev_private;
8237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8238 struct intel_ring_buffer *ring;
8239 uint32_t plane_bit = 0;
8240 int len, ret;
8241
8242 ring = obj->ring;
8243 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8244 ring = &dev_priv->ring[BCS];
8245
8246 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8247 if (ret)
8248 goto err;
8249
8250 switch(intel_crtc->plane) {
8251 case PLANE_A:
8252 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8253 break;
8254 case PLANE_B:
8255 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8256 break;
8257 case PLANE_C:
8258 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8259 break;
8260 default:
8261 WARN_ONCE(1, "unknown plane in flip command\n");
8262 ret = -ENODEV;
8263 goto err_unpin;
8264 }
8265
8266 len = 4;
8267 if (ring->id == RCS)
8268 len += 6;
8269
8270 ret = intel_ring_begin(ring, len);
8271 if (ret)
8272 goto err_unpin;
8273
8274 /* Unmask the flip-done completion message. Note that the bspec says that
8275 * we should do this for both the BCS and RCS, and that we must not unmask
8276 * more than one flip event at any time (or ensure that one flip message
8277 * can be sent by waiting for flip-done prior to queueing new flips).
8278 * Experimentation says that BCS works despite DERRMR masking all
8279 * flip-done completion events and that unmasking all planes at once
8280 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8281 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8282 */
8283 if (ring->id == RCS) {
8284 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8285 intel_ring_emit(ring, DERRMR);
8286 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8287 DERRMR_PIPEB_PRI_FLIP_DONE |
8288 DERRMR_PIPEC_PRI_FLIP_DONE));
8289 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8290 intel_ring_emit(ring, DERRMR);
8291 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8292 }
8293
8294 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8295 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8296 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8297 intel_ring_emit(ring, (MI_NOOP));
8298
8299 intel_mark_page_flip_active(intel_crtc);
8300 __intel_ring_advance(ring);
8301 return 0;
8302
8303 err_unpin:
8304 intel_unpin_fb_obj(obj);
8305 err:
8306 return ret;
8307 }
8308
8309 static int intel_default_queue_flip(struct drm_device *dev,
8310 struct drm_crtc *crtc,
8311 struct drm_framebuffer *fb,
8312 struct drm_i915_gem_object *obj,
8313 uint32_t flags)
8314 {
8315 return -ENODEV;
8316 }
8317
8318 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8319 struct drm_framebuffer *fb,
8320 struct drm_pending_vblank_event *event,
8321 uint32_t page_flip_flags)
8322 {
8323 struct drm_device *dev = crtc->dev;
8324 struct drm_i915_private *dev_priv = dev->dev_private;
8325 struct drm_framebuffer *old_fb = crtc->fb;
8326 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8328 struct intel_unpin_work *work;
8329 unsigned long flags;
8330 int ret;
8331
8332 /* Can't change pixel format via MI display flips. */
8333 if (fb->pixel_format != crtc->fb->pixel_format)
8334 return -EINVAL;
8335
8336 /*
8337 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8338 * Note that pitch changes could also affect these register.
8339 */
8340 if (INTEL_INFO(dev)->gen > 3 &&
8341 (fb->offsets[0] != crtc->fb->offsets[0] ||
8342 fb->pitches[0] != crtc->fb->pitches[0]))
8343 return -EINVAL;
8344
8345 work = kzalloc(sizeof(*work), GFP_KERNEL);
8346 if (work == NULL)
8347 return -ENOMEM;
8348
8349 work->event = event;
8350 work->crtc = crtc;
8351 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8352 INIT_WORK(&work->work, intel_unpin_work_fn);
8353
8354 ret = drm_vblank_get(dev, intel_crtc->pipe);
8355 if (ret)
8356 goto free_work;
8357
8358 /* We borrow the event spin lock for protecting unpin_work */
8359 spin_lock_irqsave(&dev->event_lock, flags);
8360 if (intel_crtc->unpin_work) {
8361 spin_unlock_irqrestore(&dev->event_lock, flags);
8362 kfree(work);
8363 drm_vblank_put(dev, intel_crtc->pipe);
8364
8365 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8366 return -EBUSY;
8367 }
8368 intel_crtc->unpin_work = work;
8369 spin_unlock_irqrestore(&dev->event_lock, flags);
8370
8371 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8372 flush_workqueue(dev_priv->wq);
8373
8374 ret = i915_mutex_lock_interruptible(dev);
8375 if (ret)
8376 goto cleanup;
8377
8378 /* Reference the objects for the scheduled work. */
8379 drm_gem_object_reference(&work->old_fb_obj->base);
8380 drm_gem_object_reference(&obj->base);
8381
8382 crtc->fb = fb;
8383
8384 work->pending_flip_obj = obj;
8385
8386 work->enable_stall_check = true;
8387
8388 atomic_inc(&intel_crtc->unpin_work_count);
8389 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8390
8391 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8392 if (ret)
8393 goto cleanup_pending;
8394
8395 intel_disable_fbc(dev);
8396 intel_mark_fb_busy(obj, NULL);
8397 mutex_unlock(&dev->struct_mutex);
8398
8399 trace_i915_flip_request(intel_crtc->plane, obj);
8400
8401 return 0;
8402
8403 cleanup_pending:
8404 atomic_dec(&intel_crtc->unpin_work_count);
8405 crtc->fb = old_fb;
8406 drm_gem_object_unreference(&work->old_fb_obj->base);
8407 drm_gem_object_unreference(&obj->base);
8408 mutex_unlock(&dev->struct_mutex);
8409
8410 cleanup:
8411 spin_lock_irqsave(&dev->event_lock, flags);
8412 intel_crtc->unpin_work = NULL;
8413 spin_unlock_irqrestore(&dev->event_lock, flags);
8414
8415 drm_vblank_put(dev, intel_crtc->pipe);
8416 free_work:
8417 kfree(work);
8418
8419 return ret;
8420 }
8421
8422 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8423 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8424 .load_lut = intel_crtc_load_lut,
8425 };
8426
8427 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8428 struct drm_crtc *crtc)
8429 {
8430 struct drm_device *dev;
8431 struct drm_crtc *tmp;
8432 int crtc_mask = 1;
8433
8434 WARN(!crtc, "checking null crtc?\n");
8435
8436 dev = crtc->dev;
8437
8438 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8439 if (tmp == crtc)
8440 break;
8441 crtc_mask <<= 1;
8442 }
8443
8444 if (encoder->possible_crtcs & crtc_mask)
8445 return true;
8446 return false;
8447 }
8448
8449 /**
8450 * intel_modeset_update_staged_output_state
8451 *
8452 * Updates the staged output configuration state, e.g. after we've read out the
8453 * current hw state.
8454 */
8455 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8456 {
8457 struct intel_encoder *encoder;
8458 struct intel_connector *connector;
8459
8460 list_for_each_entry(connector, &dev->mode_config.connector_list,
8461 base.head) {
8462 connector->new_encoder =
8463 to_intel_encoder(connector->base.encoder);
8464 }
8465
8466 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8467 base.head) {
8468 encoder->new_crtc =
8469 to_intel_crtc(encoder->base.crtc);
8470 }
8471 }
8472
8473 /**
8474 * intel_modeset_commit_output_state
8475 *
8476 * This function copies the stage display pipe configuration to the real one.
8477 */
8478 static void intel_modeset_commit_output_state(struct drm_device *dev)
8479 {
8480 struct intel_encoder *encoder;
8481 struct intel_connector *connector;
8482
8483 list_for_each_entry(connector, &dev->mode_config.connector_list,
8484 base.head) {
8485 connector->base.encoder = &connector->new_encoder->base;
8486 }
8487
8488 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8489 base.head) {
8490 encoder->base.crtc = &encoder->new_crtc->base;
8491 }
8492 }
8493
8494 static void
8495 connected_sink_compute_bpp(struct intel_connector * connector,
8496 struct intel_crtc_config *pipe_config)
8497 {
8498 int bpp = pipe_config->pipe_bpp;
8499
8500 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8501 connector->base.base.id,
8502 drm_get_connector_name(&connector->base));
8503
8504 /* Don't use an invalid EDID bpc value */
8505 if (connector->base.display_info.bpc &&
8506 connector->base.display_info.bpc * 3 < bpp) {
8507 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8508 bpp, connector->base.display_info.bpc*3);
8509 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8510 }
8511
8512 /* Clamp bpp to 8 on screens without EDID 1.4 */
8513 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8514 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8515 bpp);
8516 pipe_config->pipe_bpp = 24;
8517 }
8518 }
8519
8520 static int
8521 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8522 struct drm_framebuffer *fb,
8523 struct intel_crtc_config *pipe_config)
8524 {
8525 struct drm_device *dev = crtc->base.dev;
8526 struct intel_connector *connector;
8527 int bpp;
8528
8529 switch (fb->pixel_format) {
8530 case DRM_FORMAT_C8:
8531 bpp = 8*3; /* since we go through a colormap */
8532 break;
8533 case DRM_FORMAT_XRGB1555:
8534 case DRM_FORMAT_ARGB1555:
8535 /* checked in intel_framebuffer_init already */
8536 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8537 return -EINVAL;
8538 case DRM_FORMAT_RGB565:
8539 bpp = 6*3; /* min is 18bpp */
8540 break;
8541 case DRM_FORMAT_XBGR8888:
8542 case DRM_FORMAT_ABGR8888:
8543 /* checked in intel_framebuffer_init already */
8544 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8545 return -EINVAL;
8546 case DRM_FORMAT_XRGB8888:
8547 case DRM_FORMAT_ARGB8888:
8548 bpp = 8*3;
8549 break;
8550 case DRM_FORMAT_XRGB2101010:
8551 case DRM_FORMAT_ARGB2101010:
8552 case DRM_FORMAT_XBGR2101010:
8553 case DRM_FORMAT_ABGR2101010:
8554 /* checked in intel_framebuffer_init already */
8555 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8556 return -EINVAL;
8557 bpp = 10*3;
8558 break;
8559 /* TODO: gen4+ supports 16 bpc floating point, too. */
8560 default:
8561 DRM_DEBUG_KMS("unsupported depth\n");
8562 return -EINVAL;
8563 }
8564
8565 pipe_config->pipe_bpp = bpp;
8566
8567 /* Clamp display bpp to EDID value */
8568 list_for_each_entry(connector, &dev->mode_config.connector_list,
8569 base.head) {
8570 if (!connector->new_encoder ||
8571 connector->new_encoder->new_crtc != crtc)
8572 continue;
8573
8574 connected_sink_compute_bpp(connector, pipe_config);
8575 }
8576
8577 return bpp;
8578 }
8579
8580 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8581 {
8582 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8583 "type: 0x%x flags: 0x%x\n",
8584 mode->crtc_clock,
8585 mode->crtc_hdisplay, mode->crtc_hsync_start,
8586 mode->crtc_hsync_end, mode->crtc_htotal,
8587 mode->crtc_vdisplay, mode->crtc_vsync_start,
8588 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8589 }
8590
8591 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8592 struct intel_crtc_config *pipe_config,
8593 const char *context)
8594 {
8595 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8596 context, pipe_name(crtc->pipe));
8597
8598 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8599 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8600 pipe_config->pipe_bpp, pipe_config->dither);
8601 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8602 pipe_config->has_pch_encoder,
8603 pipe_config->fdi_lanes,
8604 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8605 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8606 pipe_config->fdi_m_n.tu);
8607 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8608 pipe_config->has_dp_encoder,
8609 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8610 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8611 pipe_config->dp_m_n.tu);
8612 DRM_DEBUG_KMS("requested mode:\n");
8613 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8614 DRM_DEBUG_KMS("adjusted mode:\n");
8615 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8616 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
8617 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8618 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8619 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8620 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8621 pipe_config->gmch_pfit.control,
8622 pipe_config->gmch_pfit.pgm_ratios,
8623 pipe_config->gmch_pfit.lvds_border_bits);
8624 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8625 pipe_config->pch_pfit.pos,
8626 pipe_config->pch_pfit.size,
8627 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8628 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8629 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8630 }
8631
8632 static bool check_encoder_cloning(struct drm_crtc *crtc)
8633 {
8634 int num_encoders = 0;
8635 bool uncloneable_encoders = false;
8636 struct intel_encoder *encoder;
8637
8638 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8639 base.head) {
8640 if (&encoder->new_crtc->base != crtc)
8641 continue;
8642
8643 num_encoders++;
8644 if (!encoder->cloneable)
8645 uncloneable_encoders = true;
8646 }
8647
8648 return !(num_encoders > 1 && uncloneable_encoders);
8649 }
8650
8651 static struct intel_crtc_config *
8652 intel_modeset_pipe_config(struct drm_crtc *crtc,
8653 struct drm_framebuffer *fb,
8654 struct drm_display_mode *mode)
8655 {
8656 struct drm_device *dev = crtc->dev;
8657 struct intel_encoder *encoder;
8658 struct intel_crtc_config *pipe_config;
8659 int plane_bpp, ret = -EINVAL;
8660 bool retry = true;
8661
8662 if (!check_encoder_cloning(crtc)) {
8663 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8664 return ERR_PTR(-EINVAL);
8665 }
8666
8667 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8668 if (!pipe_config)
8669 return ERR_PTR(-ENOMEM);
8670
8671 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8672 drm_mode_copy(&pipe_config->requested_mode, mode);
8673
8674 pipe_config->cpu_transcoder =
8675 (enum transcoder) to_intel_crtc(crtc)->pipe;
8676 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8677
8678 /*
8679 * Sanitize sync polarity flags based on requested ones. If neither
8680 * positive or negative polarity is requested, treat this as meaning
8681 * negative polarity.
8682 */
8683 if (!(pipe_config->adjusted_mode.flags &
8684 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8685 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8686
8687 if (!(pipe_config->adjusted_mode.flags &
8688 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8689 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8690
8691 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8692 * plane pixel format and any sink constraints into account. Returns the
8693 * source plane bpp so that dithering can be selected on mismatches
8694 * after encoders and crtc also have had their say. */
8695 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8696 fb, pipe_config);
8697 if (plane_bpp < 0)
8698 goto fail;
8699
8700 /*
8701 * Determine the real pipe dimensions. Note that stereo modes can
8702 * increase the actual pipe size due to the frame doubling and
8703 * insertion of additional space for blanks between the frame. This
8704 * is stored in the crtc timings. We use the requested mode to do this
8705 * computation to clearly distinguish it from the adjusted mode, which
8706 * can be changed by the connectors in the below retry loop.
8707 */
8708 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8709 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8710 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8711
8712 encoder_retry:
8713 /* Ensure the port clock defaults are reset when retrying. */
8714 pipe_config->port_clock = 0;
8715 pipe_config->pixel_multiplier = 1;
8716
8717 /* Fill in default crtc timings, allow encoders to overwrite them. */
8718 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
8719
8720 /* Pass our mode to the connectors and the CRTC to give them a chance to
8721 * adjust it according to limitations or connector properties, and also
8722 * a chance to reject the mode entirely.
8723 */
8724 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8725 base.head) {
8726
8727 if (&encoder->new_crtc->base != crtc)
8728 continue;
8729
8730 if (!(encoder->compute_config(encoder, pipe_config))) {
8731 DRM_DEBUG_KMS("Encoder config failure\n");
8732 goto fail;
8733 }
8734 }
8735
8736 /* Set default port clock if not overwritten by the encoder. Needs to be
8737 * done afterwards in case the encoder adjusts the mode. */
8738 if (!pipe_config->port_clock)
8739 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8740 * pipe_config->pixel_multiplier;
8741
8742 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8743 if (ret < 0) {
8744 DRM_DEBUG_KMS("CRTC fixup failed\n");
8745 goto fail;
8746 }
8747
8748 if (ret == RETRY) {
8749 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8750 ret = -EINVAL;
8751 goto fail;
8752 }
8753
8754 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8755 retry = false;
8756 goto encoder_retry;
8757 }
8758
8759 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8760 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8761 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8762
8763 return pipe_config;
8764 fail:
8765 kfree(pipe_config);
8766 return ERR_PTR(ret);
8767 }
8768
8769 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8770 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8771 static void
8772 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8773 unsigned *prepare_pipes, unsigned *disable_pipes)
8774 {
8775 struct intel_crtc *intel_crtc;
8776 struct drm_device *dev = crtc->dev;
8777 struct intel_encoder *encoder;
8778 struct intel_connector *connector;
8779 struct drm_crtc *tmp_crtc;
8780
8781 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8782
8783 /* Check which crtcs have changed outputs connected to them, these need
8784 * to be part of the prepare_pipes mask. We don't (yet) support global
8785 * modeset across multiple crtcs, so modeset_pipes will only have one
8786 * bit set at most. */
8787 list_for_each_entry(connector, &dev->mode_config.connector_list,
8788 base.head) {
8789 if (connector->base.encoder == &connector->new_encoder->base)
8790 continue;
8791
8792 if (connector->base.encoder) {
8793 tmp_crtc = connector->base.encoder->crtc;
8794
8795 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8796 }
8797
8798 if (connector->new_encoder)
8799 *prepare_pipes |=
8800 1 << connector->new_encoder->new_crtc->pipe;
8801 }
8802
8803 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8804 base.head) {
8805 if (encoder->base.crtc == &encoder->new_crtc->base)
8806 continue;
8807
8808 if (encoder->base.crtc) {
8809 tmp_crtc = encoder->base.crtc;
8810
8811 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8812 }
8813
8814 if (encoder->new_crtc)
8815 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8816 }
8817
8818 /* Check for any pipes that will be fully disabled ... */
8819 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8820 base.head) {
8821 bool used = false;
8822
8823 /* Don't try to disable disabled crtcs. */
8824 if (!intel_crtc->base.enabled)
8825 continue;
8826
8827 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8828 base.head) {
8829 if (encoder->new_crtc == intel_crtc)
8830 used = true;
8831 }
8832
8833 if (!used)
8834 *disable_pipes |= 1 << intel_crtc->pipe;
8835 }
8836
8837
8838 /* set_mode is also used to update properties on life display pipes. */
8839 intel_crtc = to_intel_crtc(crtc);
8840 if (crtc->enabled)
8841 *prepare_pipes |= 1 << intel_crtc->pipe;
8842
8843 /*
8844 * For simplicity do a full modeset on any pipe where the output routing
8845 * changed. We could be more clever, but that would require us to be
8846 * more careful with calling the relevant encoder->mode_set functions.
8847 */
8848 if (*prepare_pipes)
8849 *modeset_pipes = *prepare_pipes;
8850
8851 /* ... and mask these out. */
8852 *modeset_pipes &= ~(*disable_pipes);
8853 *prepare_pipes &= ~(*disable_pipes);
8854
8855 /*
8856 * HACK: We don't (yet) fully support global modesets. intel_set_config
8857 * obies this rule, but the modeset restore mode of
8858 * intel_modeset_setup_hw_state does not.
8859 */
8860 *modeset_pipes &= 1 << intel_crtc->pipe;
8861 *prepare_pipes &= 1 << intel_crtc->pipe;
8862
8863 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8864 *modeset_pipes, *prepare_pipes, *disable_pipes);
8865 }
8866
8867 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8868 {
8869 struct drm_encoder *encoder;
8870 struct drm_device *dev = crtc->dev;
8871
8872 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8873 if (encoder->crtc == crtc)
8874 return true;
8875
8876 return false;
8877 }
8878
8879 static void
8880 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8881 {
8882 struct intel_encoder *intel_encoder;
8883 struct intel_crtc *intel_crtc;
8884 struct drm_connector *connector;
8885
8886 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8887 base.head) {
8888 if (!intel_encoder->base.crtc)
8889 continue;
8890
8891 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8892
8893 if (prepare_pipes & (1 << intel_crtc->pipe))
8894 intel_encoder->connectors_active = false;
8895 }
8896
8897 intel_modeset_commit_output_state(dev);
8898
8899 /* Update computed state. */
8900 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8901 base.head) {
8902 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8903 }
8904
8905 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8906 if (!connector->encoder || !connector->encoder->crtc)
8907 continue;
8908
8909 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8910
8911 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8912 struct drm_property *dpms_property =
8913 dev->mode_config.dpms_property;
8914
8915 connector->dpms = DRM_MODE_DPMS_ON;
8916 drm_object_property_set_value(&connector->base,
8917 dpms_property,
8918 DRM_MODE_DPMS_ON);
8919
8920 intel_encoder = to_intel_encoder(connector->encoder);
8921 intel_encoder->connectors_active = true;
8922 }
8923 }
8924
8925 }
8926
8927 static bool intel_fuzzy_clock_check(int clock1, int clock2)
8928 {
8929 int diff;
8930
8931 if (clock1 == clock2)
8932 return true;
8933
8934 if (!clock1 || !clock2)
8935 return false;
8936
8937 diff = abs(clock1 - clock2);
8938
8939 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8940 return true;
8941
8942 return false;
8943 }
8944
8945 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8946 list_for_each_entry((intel_crtc), \
8947 &(dev)->mode_config.crtc_list, \
8948 base.head) \
8949 if (mask & (1 <<(intel_crtc)->pipe))
8950
8951 static bool
8952 intel_pipe_config_compare(struct drm_device *dev,
8953 struct intel_crtc_config *current_config,
8954 struct intel_crtc_config *pipe_config)
8955 {
8956 #define PIPE_CONF_CHECK_X(name) \
8957 if (current_config->name != pipe_config->name) { \
8958 DRM_ERROR("mismatch in " #name " " \
8959 "(expected 0x%08x, found 0x%08x)\n", \
8960 current_config->name, \
8961 pipe_config->name); \
8962 return false; \
8963 }
8964
8965 #define PIPE_CONF_CHECK_I(name) \
8966 if (current_config->name != pipe_config->name) { \
8967 DRM_ERROR("mismatch in " #name " " \
8968 "(expected %i, found %i)\n", \
8969 current_config->name, \
8970 pipe_config->name); \
8971 return false; \
8972 }
8973
8974 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8975 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8976 DRM_ERROR("mismatch in " #name "(" #mask ") " \
8977 "(expected %i, found %i)\n", \
8978 current_config->name & (mask), \
8979 pipe_config->name & (mask)); \
8980 return false; \
8981 }
8982
8983 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8984 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8985 DRM_ERROR("mismatch in " #name " " \
8986 "(expected %i, found %i)\n", \
8987 current_config->name, \
8988 pipe_config->name); \
8989 return false; \
8990 }
8991
8992 #define PIPE_CONF_QUIRK(quirk) \
8993 ((current_config->quirks | pipe_config->quirks) & (quirk))
8994
8995 PIPE_CONF_CHECK_I(cpu_transcoder);
8996
8997 PIPE_CONF_CHECK_I(has_pch_encoder);
8998 PIPE_CONF_CHECK_I(fdi_lanes);
8999 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9000 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9001 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9002 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9003 PIPE_CONF_CHECK_I(fdi_m_n.tu);
9004
9005 PIPE_CONF_CHECK_I(has_dp_encoder);
9006 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9007 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9008 PIPE_CONF_CHECK_I(dp_m_n.link_m);
9009 PIPE_CONF_CHECK_I(dp_m_n.link_n);
9010 PIPE_CONF_CHECK_I(dp_m_n.tu);
9011
9012 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9013 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9014 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9015 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9016 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9017 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9018
9019 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9020 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9021 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9022 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9023 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9024 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9025
9026 PIPE_CONF_CHECK_I(pixel_multiplier);
9027
9028 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9029 DRM_MODE_FLAG_INTERLACE);
9030
9031 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9032 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9033 DRM_MODE_FLAG_PHSYNC);
9034 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9035 DRM_MODE_FLAG_NHSYNC);
9036 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9037 DRM_MODE_FLAG_PVSYNC);
9038 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9039 DRM_MODE_FLAG_NVSYNC);
9040 }
9041
9042 PIPE_CONF_CHECK_I(pipe_src_w);
9043 PIPE_CONF_CHECK_I(pipe_src_h);
9044
9045 PIPE_CONF_CHECK_I(gmch_pfit.control);
9046 /* pfit ratios are autocomputed by the hw on gen4+ */
9047 if (INTEL_INFO(dev)->gen < 4)
9048 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9049 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9050 PIPE_CONF_CHECK_I(pch_pfit.enabled);
9051 if (current_config->pch_pfit.enabled) {
9052 PIPE_CONF_CHECK_I(pch_pfit.pos);
9053 PIPE_CONF_CHECK_I(pch_pfit.size);
9054 }
9055
9056 PIPE_CONF_CHECK_I(ips_enabled);
9057
9058 PIPE_CONF_CHECK_I(double_wide);
9059
9060 PIPE_CONF_CHECK_I(shared_dpll);
9061 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9062 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9063 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9064 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9065
9066 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9067 PIPE_CONF_CHECK_I(pipe_bpp);
9068
9069 if (!IS_HASWELL(dev)) {
9070 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9071 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9072 }
9073
9074 #undef PIPE_CONF_CHECK_X
9075 #undef PIPE_CONF_CHECK_I
9076 #undef PIPE_CONF_CHECK_FLAGS
9077 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9078 #undef PIPE_CONF_QUIRK
9079
9080 return true;
9081 }
9082
9083 static void
9084 check_connector_state(struct drm_device *dev)
9085 {
9086 struct intel_connector *connector;
9087
9088 list_for_each_entry(connector, &dev->mode_config.connector_list,
9089 base.head) {
9090 /* This also checks the encoder/connector hw state with the
9091 * ->get_hw_state callbacks. */
9092 intel_connector_check_state(connector);
9093
9094 WARN(&connector->new_encoder->base != connector->base.encoder,
9095 "connector's staged encoder doesn't match current encoder\n");
9096 }
9097 }
9098
9099 static void
9100 check_encoder_state(struct drm_device *dev)
9101 {
9102 struct intel_encoder *encoder;
9103 struct intel_connector *connector;
9104
9105 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9106 base.head) {
9107 bool enabled = false;
9108 bool active = false;
9109 enum pipe pipe, tracked_pipe;
9110
9111 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9112 encoder->base.base.id,
9113 drm_get_encoder_name(&encoder->base));
9114
9115 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9116 "encoder's stage crtc doesn't match current crtc\n");
9117 WARN(encoder->connectors_active && !encoder->base.crtc,
9118 "encoder's active_connectors set, but no crtc\n");
9119
9120 list_for_each_entry(connector, &dev->mode_config.connector_list,
9121 base.head) {
9122 if (connector->base.encoder != &encoder->base)
9123 continue;
9124 enabled = true;
9125 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9126 active = true;
9127 }
9128 WARN(!!encoder->base.crtc != enabled,
9129 "encoder's enabled state mismatch "
9130 "(expected %i, found %i)\n",
9131 !!encoder->base.crtc, enabled);
9132 WARN(active && !encoder->base.crtc,
9133 "active encoder with no crtc\n");
9134
9135 WARN(encoder->connectors_active != active,
9136 "encoder's computed active state doesn't match tracked active state "
9137 "(expected %i, found %i)\n", active, encoder->connectors_active);
9138
9139 active = encoder->get_hw_state(encoder, &pipe);
9140 WARN(active != encoder->connectors_active,
9141 "encoder's hw state doesn't match sw tracking "
9142 "(expected %i, found %i)\n",
9143 encoder->connectors_active, active);
9144
9145 if (!encoder->base.crtc)
9146 continue;
9147
9148 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9149 WARN(active && pipe != tracked_pipe,
9150 "active encoder's pipe doesn't match"
9151 "(expected %i, found %i)\n",
9152 tracked_pipe, pipe);
9153
9154 }
9155 }
9156
9157 static void
9158 check_crtc_state(struct drm_device *dev)
9159 {
9160 drm_i915_private_t *dev_priv = dev->dev_private;
9161 struct intel_crtc *crtc;
9162 struct intel_encoder *encoder;
9163 struct intel_crtc_config pipe_config;
9164
9165 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9166 base.head) {
9167 bool enabled = false;
9168 bool active = false;
9169
9170 memset(&pipe_config, 0, sizeof(pipe_config));
9171
9172 DRM_DEBUG_KMS("[CRTC:%d]\n",
9173 crtc->base.base.id);
9174
9175 WARN(crtc->active && !crtc->base.enabled,
9176 "active crtc, but not enabled in sw tracking\n");
9177
9178 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9179 base.head) {
9180 if (encoder->base.crtc != &crtc->base)
9181 continue;
9182 enabled = true;
9183 if (encoder->connectors_active)
9184 active = true;
9185 }
9186
9187 WARN(active != crtc->active,
9188 "crtc's computed active state doesn't match tracked active state "
9189 "(expected %i, found %i)\n", active, crtc->active);
9190 WARN(enabled != crtc->base.enabled,
9191 "crtc's computed enabled state doesn't match tracked enabled state "
9192 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9193
9194 active = dev_priv->display.get_pipe_config(crtc,
9195 &pipe_config);
9196
9197 /* hw state is inconsistent with the pipe A quirk */
9198 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9199 active = crtc->active;
9200
9201 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9202 base.head) {
9203 enum pipe pipe;
9204 if (encoder->base.crtc != &crtc->base)
9205 continue;
9206 if (encoder->get_config &&
9207 encoder->get_hw_state(encoder, &pipe))
9208 encoder->get_config(encoder, &pipe_config);
9209 }
9210
9211 WARN(crtc->active != active,
9212 "crtc active state doesn't match with hw state "
9213 "(expected %i, found %i)\n", crtc->active, active);
9214
9215 if (active &&
9216 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9217 WARN(1, "pipe state doesn't match!\n");
9218 intel_dump_pipe_config(crtc, &pipe_config,
9219 "[hw state]");
9220 intel_dump_pipe_config(crtc, &crtc->config,
9221 "[sw state]");
9222 }
9223 }
9224 }
9225
9226 static void
9227 check_shared_dpll_state(struct drm_device *dev)
9228 {
9229 drm_i915_private_t *dev_priv = dev->dev_private;
9230 struct intel_crtc *crtc;
9231 struct intel_dpll_hw_state dpll_hw_state;
9232 int i;
9233
9234 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9235 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9236 int enabled_crtcs = 0, active_crtcs = 0;
9237 bool active;
9238
9239 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9240
9241 DRM_DEBUG_KMS("%s\n", pll->name);
9242
9243 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9244
9245 WARN(pll->active > pll->refcount,
9246 "more active pll users than references: %i vs %i\n",
9247 pll->active, pll->refcount);
9248 WARN(pll->active && !pll->on,
9249 "pll in active use but not on in sw tracking\n");
9250 WARN(pll->on && !pll->active,
9251 "pll in on but not on in use in sw tracking\n");
9252 WARN(pll->on != active,
9253 "pll on state mismatch (expected %i, found %i)\n",
9254 pll->on, active);
9255
9256 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9257 base.head) {
9258 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9259 enabled_crtcs++;
9260 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9261 active_crtcs++;
9262 }
9263 WARN(pll->active != active_crtcs,
9264 "pll active crtcs mismatch (expected %i, found %i)\n",
9265 pll->active, active_crtcs);
9266 WARN(pll->refcount != enabled_crtcs,
9267 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9268 pll->refcount, enabled_crtcs);
9269
9270 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9271 sizeof(dpll_hw_state)),
9272 "pll hw state mismatch\n");
9273 }
9274 }
9275
9276 void
9277 intel_modeset_check_state(struct drm_device *dev)
9278 {
9279 check_connector_state(dev);
9280 check_encoder_state(dev);
9281 check_crtc_state(dev);
9282 check_shared_dpll_state(dev);
9283 }
9284
9285 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9286 int dotclock)
9287 {
9288 /*
9289 * FDI already provided one idea for the dotclock.
9290 * Yell if the encoder disagrees.
9291 */
9292 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9293 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9294 pipe_config->adjusted_mode.crtc_clock, dotclock);
9295 }
9296
9297 static int __intel_set_mode(struct drm_crtc *crtc,
9298 struct drm_display_mode *mode,
9299 int x, int y, struct drm_framebuffer *fb)
9300 {
9301 struct drm_device *dev = crtc->dev;
9302 drm_i915_private_t *dev_priv = dev->dev_private;
9303 struct drm_display_mode *saved_mode, *saved_hwmode;
9304 struct intel_crtc_config *pipe_config = NULL;
9305 struct intel_crtc *intel_crtc;
9306 unsigned disable_pipes, prepare_pipes, modeset_pipes;
9307 int ret = 0;
9308
9309 saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
9310 if (!saved_mode)
9311 return -ENOMEM;
9312 saved_hwmode = saved_mode + 1;
9313
9314 intel_modeset_affected_pipes(crtc, &modeset_pipes,
9315 &prepare_pipes, &disable_pipes);
9316
9317 *saved_hwmode = crtc->hwmode;
9318 *saved_mode = crtc->mode;
9319
9320 /* Hack: Because we don't (yet) support global modeset on multiple
9321 * crtcs, we don't keep track of the new mode for more than one crtc.
9322 * Hence simply check whether any bit is set in modeset_pipes in all the
9323 * pieces of code that are not yet converted to deal with mutliple crtcs
9324 * changing their mode at the same time. */
9325 if (modeset_pipes) {
9326 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9327 if (IS_ERR(pipe_config)) {
9328 ret = PTR_ERR(pipe_config);
9329 pipe_config = NULL;
9330
9331 goto out;
9332 }
9333 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9334 "[modeset]");
9335 }
9336
9337 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9338 intel_crtc_disable(&intel_crtc->base);
9339
9340 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9341 if (intel_crtc->base.enabled)
9342 dev_priv->display.crtc_disable(&intel_crtc->base);
9343 }
9344
9345 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9346 * to set it here already despite that we pass it down the callchain.
9347 */
9348 if (modeset_pipes) {
9349 crtc->mode = *mode;
9350 /* mode_set/enable/disable functions rely on a correct pipe
9351 * config. */
9352 to_intel_crtc(crtc)->config = *pipe_config;
9353 }
9354
9355 /* Only after disabling all output pipelines that will be changed can we
9356 * update the the output configuration. */
9357 intel_modeset_update_state(dev, prepare_pipes);
9358
9359 if (dev_priv->display.modeset_global_resources)
9360 dev_priv->display.modeset_global_resources(dev);
9361
9362 /* Set up the DPLL and any encoders state that needs to adjust or depend
9363 * on the DPLL.
9364 */
9365 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9366 ret = intel_crtc_mode_set(&intel_crtc->base,
9367 x, y, fb);
9368 if (ret)
9369 goto done;
9370 }
9371
9372 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9373 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9374 dev_priv->display.crtc_enable(&intel_crtc->base);
9375
9376 if (modeset_pipes) {
9377 /* Store real post-adjustment hardware mode. */
9378 crtc->hwmode = pipe_config->adjusted_mode;
9379
9380 /* Calculate and store various constants which
9381 * are later needed by vblank and swap-completion
9382 * timestamping. They are derived from true hwmode.
9383 */
9384 drm_calc_timestamping_constants(crtc);
9385 }
9386
9387 /* FIXME: add subpixel order */
9388 done:
9389 if (ret && crtc->enabled) {
9390 crtc->hwmode = *saved_hwmode;
9391 crtc->mode = *saved_mode;
9392 }
9393
9394 out:
9395 kfree(pipe_config);
9396 kfree(saved_mode);
9397 return ret;
9398 }
9399
9400 static int intel_set_mode(struct drm_crtc *crtc,
9401 struct drm_display_mode *mode,
9402 int x, int y, struct drm_framebuffer *fb)
9403 {
9404 int ret;
9405
9406 ret = __intel_set_mode(crtc, mode, x, y, fb);
9407
9408 if (ret == 0)
9409 intel_modeset_check_state(crtc->dev);
9410
9411 return ret;
9412 }
9413
9414 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9415 {
9416 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9417 }
9418
9419 #undef for_each_intel_crtc_masked
9420
9421 static void intel_set_config_free(struct intel_set_config *config)
9422 {
9423 if (!config)
9424 return;
9425
9426 kfree(config->save_connector_encoders);
9427 kfree(config->save_encoder_crtcs);
9428 kfree(config);
9429 }
9430
9431 static int intel_set_config_save_state(struct drm_device *dev,
9432 struct intel_set_config *config)
9433 {
9434 struct drm_encoder *encoder;
9435 struct drm_connector *connector;
9436 int count;
9437
9438 config->save_encoder_crtcs =
9439 kcalloc(dev->mode_config.num_encoder,
9440 sizeof(struct drm_crtc *), GFP_KERNEL);
9441 if (!config->save_encoder_crtcs)
9442 return -ENOMEM;
9443
9444 config->save_connector_encoders =
9445 kcalloc(dev->mode_config.num_connector,
9446 sizeof(struct drm_encoder *), GFP_KERNEL);
9447 if (!config->save_connector_encoders)
9448 return -ENOMEM;
9449
9450 /* Copy data. Note that driver private data is not affected.
9451 * Should anything bad happen only the expected state is
9452 * restored, not the drivers personal bookkeeping.
9453 */
9454 count = 0;
9455 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9456 config->save_encoder_crtcs[count++] = encoder->crtc;
9457 }
9458
9459 count = 0;
9460 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9461 config->save_connector_encoders[count++] = connector->encoder;
9462 }
9463
9464 return 0;
9465 }
9466
9467 static void intel_set_config_restore_state(struct drm_device *dev,
9468 struct intel_set_config *config)
9469 {
9470 struct intel_encoder *encoder;
9471 struct intel_connector *connector;
9472 int count;
9473
9474 count = 0;
9475 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9476 encoder->new_crtc =
9477 to_intel_crtc(config->save_encoder_crtcs[count++]);
9478 }
9479
9480 count = 0;
9481 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9482 connector->new_encoder =
9483 to_intel_encoder(config->save_connector_encoders[count++]);
9484 }
9485 }
9486
9487 static bool
9488 is_crtc_connector_off(struct drm_mode_set *set)
9489 {
9490 int i;
9491
9492 if (set->num_connectors == 0)
9493 return false;
9494
9495 if (WARN_ON(set->connectors == NULL))
9496 return false;
9497
9498 for (i = 0; i < set->num_connectors; i++)
9499 if (set->connectors[i]->encoder &&
9500 set->connectors[i]->encoder->crtc == set->crtc &&
9501 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9502 return true;
9503
9504 return false;
9505 }
9506
9507 static void
9508 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9509 struct intel_set_config *config)
9510 {
9511
9512 /* We should be able to check here if the fb has the same properties
9513 * and then just flip_or_move it */
9514 if (is_crtc_connector_off(set)) {
9515 config->mode_changed = true;
9516 } else if (set->crtc->fb != set->fb) {
9517 /* If we have no fb then treat it as a full mode set */
9518 if (set->crtc->fb == NULL) {
9519 struct intel_crtc *intel_crtc =
9520 to_intel_crtc(set->crtc);
9521
9522 if (intel_crtc->active && i915_fastboot) {
9523 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9524 config->fb_changed = true;
9525 } else {
9526 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9527 config->mode_changed = true;
9528 }
9529 } else if (set->fb == NULL) {
9530 config->mode_changed = true;
9531 } else if (set->fb->pixel_format !=
9532 set->crtc->fb->pixel_format) {
9533 config->mode_changed = true;
9534 } else {
9535 config->fb_changed = true;
9536 }
9537 }
9538
9539 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9540 config->fb_changed = true;
9541
9542 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9543 DRM_DEBUG_KMS("modes are different, full mode set\n");
9544 drm_mode_debug_printmodeline(&set->crtc->mode);
9545 drm_mode_debug_printmodeline(set->mode);
9546 config->mode_changed = true;
9547 }
9548
9549 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9550 set->crtc->base.id, config->mode_changed, config->fb_changed);
9551 }
9552
9553 static int
9554 intel_modeset_stage_output_state(struct drm_device *dev,
9555 struct drm_mode_set *set,
9556 struct intel_set_config *config)
9557 {
9558 struct drm_crtc *new_crtc;
9559 struct intel_connector *connector;
9560 struct intel_encoder *encoder;
9561 int ro;
9562
9563 /* The upper layers ensure that we either disable a crtc or have a list
9564 * of connectors. For paranoia, double-check this. */
9565 WARN_ON(!set->fb && (set->num_connectors != 0));
9566 WARN_ON(set->fb && (set->num_connectors == 0));
9567
9568 list_for_each_entry(connector, &dev->mode_config.connector_list,
9569 base.head) {
9570 /* Otherwise traverse passed in connector list and get encoders
9571 * for them. */
9572 for (ro = 0; ro < set->num_connectors; ro++) {
9573 if (set->connectors[ro] == &connector->base) {
9574 connector->new_encoder = connector->encoder;
9575 break;
9576 }
9577 }
9578
9579 /* If we disable the crtc, disable all its connectors. Also, if
9580 * the connector is on the changing crtc but not on the new
9581 * connector list, disable it. */
9582 if ((!set->fb || ro == set->num_connectors) &&
9583 connector->base.encoder &&
9584 connector->base.encoder->crtc == set->crtc) {
9585 connector->new_encoder = NULL;
9586
9587 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9588 connector->base.base.id,
9589 drm_get_connector_name(&connector->base));
9590 }
9591
9592
9593 if (&connector->new_encoder->base != connector->base.encoder) {
9594 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9595 config->mode_changed = true;
9596 }
9597 }
9598 /* connector->new_encoder is now updated for all connectors. */
9599
9600 /* Update crtc of enabled connectors. */
9601 list_for_each_entry(connector, &dev->mode_config.connector_list,
9602 base.head) {
9603 if (!connector->new_encoder)
9604 continue;
9605
9606 new_crtc = connector->new_encoder->base.crtc;
9607
9608 for (ro = 0; ro < set->num_connectors; ro++) {
9609 if (set->connectors[ro] == &connector->base)
9610 new_crtc = set->crtc;
9611 }
9612
9613 /* Make sure the new CRTC will work with the encoder */
9614 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9615 new_crtc)) {
9616 return -EINVAL;
9617 }
9618 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9619
9620 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9621 connector->base.base.id,
9622 drm_get_connector_name(&connector->base),
9623 new_crtc->base.id);
9624 }
9625
9626 /* Check for any encoders that needs to be disabled. */
9627 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9628 base.head) {
9629 list_for_each_entry(connector,
9630 &dev->mode_config.connector_list,
9631 base.head) {
9632 if (connector->new_encoder == encoder) {
9633 WARN_ON(!connector->new_encoder->new_crtc);
9634
9635 goto next_encoder;
9636 }
9637 }
9638 encoder->new_crtc = NULL;
9639 next_encoder:
9640 /* Only now check for crtc changes so we don't miss encoders
9641 * that will be disabled. */
9642 if (&encoder->new_crtc->base != encoder->base.crtc) {
9643 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9644 config->mode_changed = true;
9645 }
9646 }
9647 /* Now we've also updated encoder->new_crtc for all encoders. */
9648
9649 return 0;
9650 }
9651
9652 static int intel_crtc_set_config(struct drm_mode_set *set)
9653 {
9654 struct drm_device *dev;
9655 struct drm_mode_set save_set;
9656 struct intel_set_config *config;
9657 int ret;
9658
9659 BUG_ON(!set);
9660 BUG_ON(!set->crtc);
9661 BUG_ON(!set->crtc->helper_private);
9662
9663 /* Enforce sane interface api - has been abused by the fb helper. */
9664 BUG_ON(!set->mode && set->fb);
9665 BUG_ON(set->fb && set->num_connectors == 0);
9666
9667 if (set->fb) {
9668 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9669 set->crtc->base.id, set->fb->base.id,
9670 (int)set->num_connectors, set->x, set->y);
9671 } else {
9672 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9673 }
9674
9675 dev = set->crtc->dev;
9676
9677 ret = -ENOMEM;
9678 config = kzalloc(sizeof(*config), GFP_KERNEL);
9679 if (!config)
9680 goto out_config;
9681
9682 ret = intel_set_config_save_state(dev, config);
9683 if (ret)
9684 goto out_config;
9685
9686 save_set.crtc = set->crtc;
9687 save_set.mode = &set->crtc->mode;
9688 save_set.x = set->crtc->x;
9689 save_set.y = set->crtc->y;
9690 save_set.fb = set->crtc->fb;
9691
9692 /* Compute whether we need a full modeset, only an fb base update or no
9693 * change at all. In the future we might also check whether only the
9694 * mode changed, e.g. for LVDS where we only change the panel fitter in
9695 * such cases. */
9696 intel_set_config_compute_mode_changes(set, config);
9697
9698 ret = intel_modeset_stage_output_state(dev, set, config);
9699 if (ret)
9700 goto fail;
9701
9702 if (config->mode_changed) {
9703 ret = intel_set_mode(set->crtc, set->mode,
9704 set->x, set->y, set->fb);
9705 } else if (config->fb_changed) {
9706 intel_crtc_wait_for_pending_flips(set->crtc);
9707
9708 ret = intel_pipe_set_base(set->crtc,
9709 set->x, set->y, set->fb);
9710 }
9711
9712 if (ret) {
9713 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9714 set->crtc->base.id, ret);
9715 fail:
9716 intel_set_config_restore_state(dev, config);
9717
9718 /* Try to restore the config */
9719 if (config->mode_changed &&
9720 intel_set_mode(save_set.crtc, save_set.mode,
9721 save_set.x, save_set.y, save_set.fb))
9722 DRM_ERROR("failed to restore config after modeset failure\n");
9723 }
9724
9725 out_config:
9726 intel_set_config_free(config);
9727 return ret;
9728 }
9729
9730 static const struct drm_crtc_funcs intel_crtc_funcs = {
9731 .cursor_set = intel_crtc_cursor_set,
9732 .cursor_move = intel_crtc_cursor_move,
9733 .gamma_set = intel_crtc_gamma_set,
9734 .set_config = intel_crtc_set_config,
9735 .destroy = intel_crtc_destroy,
9736 .page_flip = intel_crtc_page_flip,
9737 };
9738
9739 static void intel_cpu_pll_init(struct drm_device *dev)
9740 {
9741 if (HAS_DDI(dev))
9742 intel_ddi_pll_init(dev);
9743 }
9744
9745 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9746 struct intel_shared_dpll *pll,
9747 struct intel_dpll_hw_state *hw_state)
9748 {
9749 uint32_t val;
9750
9751 val = I915_READ(PCH_DPLL(pll->id));
9752 hw_state->dpll = val;
9753 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9754 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9755
9756 return val & DPLL_VCO_ENABLE;
9757 }
9758
9759 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9760 struct intel_shared_dpll *pll)
9761 {
9762 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9763 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9764 }
9765
9766 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9767 struct intel_shared_dpll *pll)
9768 {
9769 /* PCH refclock must be enabled first */
9770 assert_pch_refclk_enabled(dev_priv);
9771
9772 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9773
9774 /* Wait for the clocks to stabilize. */
9775 POSTING_READ(PCH_DPLL(pll->id));
9776 udelay(150);
9777
9778 /* The pixel multiplier can only be updated once the
9779 * DPLL is enabled and the clocks are stable.
9780 *
9781 * So write it again.
9782 */
9783 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9784 POSTING_READ(PCH_DPLL(pll->id));
9785 udelay(200);
9786 }
9787
9788 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9789 struct intel_shared_dpll *pll)
9790 {
9791 struct drm_device *dev = dev_priv->dev;
9792 struct intel_crtc *crtc;
9793
9794 /* Make sure no transcoder isn't still depending on us. */
9795 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9796 if (intel_crtc_to_shared_dpll(crtc) == pll)
9797 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9798 }
9799
9800 I915_WRITE(PCH_DPLL(pll->id), 0);
9801 POSTING_READ(PCH_DPLL(pll->id));
9802 udelay(200);
9803 }
9804
9805 static char *ibx_pch_dpll_names[] = {
9806 "PCH DPLL A",
9807 "PCH DPLL B",
9808 };
9809
9810 static void ibx_pch_dpll_init(struct drm_device *dev)
9811 {
9812 struct drm_i915_private *dev_priv = dev->dev_private;
9813 int i;
9814
9815 dev_priv->num_shared_dpll = 2;
9816
9817 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9818 dev_priv->shared_dplls[i].id = i;
9819 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9820 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9821 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9822 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9823 dev_priv->shared_dplls[i].get_hw_state =
9824 ibx_pch_dpll_get_hw_state;
9825 }
9826 }
9827
9828 static void intel_shared_dpll_init(struct drm_device *dev)
9829 {
9830 struct drm_i915_private *dev_priv = dev->dev_private;
9831
9832 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9833 ibx_pch_dpll_init(dev);
9834 else
9835 dev_priv->num_shared_dpll = 0;
9836
9837 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9838 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9839 dev_priv->num_shared_dpll);
9840 }
9841
9842 static void intel_crtc_init(struct drm_device *dev, int pipe)
9843 {
9844 drm_i915_private_t *dev_priv = dev->dev_private;
9845 struct intel_crtc *intel_crtc;
9846 int i;
9847
9848 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
9849 if (intel_crtc == NULL)
9850 return;
9851
9852 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9853
9854 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9855 for (i = 0; i < 256; i++) {
9856 intel_crtc->lut_r[i] = i;
9857 intel_crtc->lut_g[i] = i;
9858 intel_crtc->lut_b[i] = i;
9859 }
9860
9861 /* Swap pipes & planes for FBC on pre-965 */
9862 intel_crtc->pipe = pipe;
9863 intel_crtc->plane = pipe;
9864 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9865 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9866 intel_crtc->plane = !pipe;
9867 }
9868
9869 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9870 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9871 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9872 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9873
9874 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9875 }
9876
9877 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9878 struct drm_file *file)
9879 {
9880 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9881 struct drm_mode_object *drmmode_obj;
9882 struct intel_crtc *crtc;
9883
9884 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9885 return -ENODEV;
9886
9887 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9888 DRM_MODE_OBJECT_CRTC);
9889
9890 if (!drmmode_obj) {
9891 DRM_ERROR("no such CRTC id\n");
9892 return -EINVAL;
9893 }
9894
9895 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9896 pipe_from_crtc_id->pipe = crtc->pipe;
9897
9898 return 0;
9899 }
9900
9901 static int intel_encoder_clones(struct intel_encoder *encoder)
9902 {
9903 struct drm_device *dev = encoder->base.dev;
9904 struct intel_encoder *source_encoder;
9905 int index_mask = 0;
9906 int entry = 0;
9907
9908 list_for_each_entry(source_encoder,
9909 &dev->mode_config.encoder_list, base.head) {
9910
9911 if (encoder == source_encoder)
9912 index_mask |= (1 << entry);
9913
9914 /* Intel hw has only one MUX where enocoders could be cloned. */
9915 if (encoder->cloneable && source_encoder->cloneable)
9916 index_mask |= (1 << entry);
9917
9918 entry++;
9919 }
9920
9921 return index_mask;
9922 }
9923
9924 static bool has_edp_a(struct drm_device *dev)
9925 {
9926 struct drm_i915_private *dev_priv = dev->dev_private;
9927
9928 if (!IS_MOBILE(dev))
9929 return false;
9930
9931 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9932 return false;
9933
9934 if (IS_GEN5(dev) &&
9935 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9936 return false;
9937
9938 return true;
9939 }
9940
9941 static void intel_setup_outputs(struct drm_device *dev)
9942 {
9943 struct drm_i915_private *dev_priv = dev->dev_private;
9944 struct intel_encoder *encoder;
9945 bool dpd_is_edp = false;
9946
9947 intel_lvds_init(dev);
9948
9949 if (!IS_ULT(dev))
9950 intel_crt_init(dev);
9951
9952 if (HAS_DDI(dev)) {
9953 int found;
9954
9955 /* Haswell uses DDI functions to detect digital outputs */
9956 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9957 /* DDI A only supports eDP */
9958 if (found)
9959 intel_ddi_init(dev, PORT_A);
9960
9961 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9962 * register */
9963 found = I915_READ(SFUSE_STRAP);
9964
9965 if (found & SFUSE_STRAP_DDIB_DETECTED)
9966 intel_ddi_init(dev, PORT_B);
9967 if (found & SFUSE_STRAP_DDIC_DETECTED)
9968 intel_ddi_init(dev, PORT_C);
9969 if (found & SFUSE_STRAP_DDID_DETECTED)
9970 intel_ddi_init(dev, PORT_D);
9971 } else if (HAS_PCH_SPLIT(dev)) {
9972 int found;
9973 dpd_is_edp = intel_dpd_is_edp(dev);
9974
9975 if (has_edp_a(dev))
9976 intel_dp_init(dev, DP_A, PORT_A);
9977
9978 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9979 /* PCH SDVOB multiplex with HDMIB */
9980 found = intel_sdvo_init(dev, PCH_SDVOB, true);
9981 if (!found)
9982 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9983 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9984 intel_dp_init(dev, PCH_DP_B, PORT_B);
9985 }
9986
9987 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9988 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9989
9990 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9991 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9992
9993 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9994 intel_dp_init(dev, PCH_DP_C, PORT_C);
9995
9996 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9997 intel_dp_init(dev, PCH_DP_D, PORT_D);
9998 } else if (IS_VALLEYVIEW(dev)) {
9999 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10000 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10001 PORT_B);
10002 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10003 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10004 }
10005
10006 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10007 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10008 PORT_C);
10009 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10010 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
10011 PORT_C);
10012 }
10013
10014 intel_dsi_init(dev);
10015 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10016 bool found = false;
10017
10018 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10019 DRM_DEBUG_KMS("probing SDVOB\n");
10020 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10021 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10022 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10023 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10024 }
10025
10026 if (!found && SUPPORTS_INTEGRATED_DP(dev))
10027 intel_dp_init(dev, DP_B, PORT_B);
10028 }
10029
10030 /* Before G4X SDVOC doesn't have its own detect register */
10031
10032 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10033 DRM_DEBUG_KMS("probing SDVOC\n");
10034 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10035 }
10036
10037 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10038
10039 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10040 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10041 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10042 }
10043 if (SUPPORTS_INTEGRATED_DP(dev))
10044 intel_dp_init(dev, DP_C, PORT_C);
10045 }
10046
10047 if (SUPPORTS_INTEGRATED_DP(dev) &&
10048 (I915_READ(DP_D) & DP_DETECTED))
10049 intel_dp_init(dev, DP_D, PORT_D);
10050 } else if (IS_GEN2(dev))
10051 intel_dvo_init(dev);
10052
10053 if (SUPPORTS_TV(dev))
10054 intel_tv_init(dev);
10055
10056 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10057 encoder->base.possible_crtcs = encoder->crtc_mask;
10058 encoder->base.possible_clones =
10059 intel_encoder_clones(encoder);
10060 }
10061
10062 intel_init_pch_refclk(dev);
10063
10064 drm_helper_move_panel_connectors_to_head(dev);
10065 }
10066
10067 void intel_framebuffer_fini(struct intel_framebuffer *fb)
10068 {
10069 drm_framebuffer_cleanup(&fb->base);
10070 WARN_ON(!fb->obj->framebuffer_references--);
10071 drm_gem_object_unreference_unlocked(&fb->obj->base);
10072 }
10073
10074 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10075 {
10076 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10077
10078 intel_framebuffer_fini(intel_fb);
10079 kfree(intel_fb);
10080 }
10081
10082 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10083 struct drm_file *file,
10084 unsigned int *handle)
10085 {
10086 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10087 struct drm_i915_gem_object *obj = intel_fb->obj;
10088
10089 return drm_gem_handle_create(file, &obj->base, handle);
10090 }
10091
10092 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10093 .destroy = intel_user_framebuffer_destroy,
10094 .create_handle = intel_user_framebuffer_create_handle,
10095 };
10096
10097 int intel_framebuffer_init(struct drm_device *dev,
10098 struct intel_framebuffer *intel_fb,
10099 struct drm_mode_fb_cmd2 *mode_cmd,
10100 struct drm_i915_gem_object *obj)
10101 {
10102 int aligned_height, tile_height;
10103 int pitch_limit;
10104 int ret;
10105
10106 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10107
10108 if (obj->tiling_mode == I915_TILING_Y) {
10109 DRM_DEBUG("hardware does not support tiling Y\n");
10110 return -EINVAL;
10111 }
10112
10113 if (mode_cmd->pitches[0] & 63) {
10114 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10115 mode_cmd->pitches[0]);
10116 return -EINVAL;
10117 }
10118
10119 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10120 pitch_limit = 32*1024;
10121 } else if (INTEL_INFO(dev)->gen >= 4) {
10122 if (obj->tiling_mode)
10123 pitch_limit = 16*1024;
10124 else
10125 pitch_limit = 32*1024;
10126 } else if (INTEL_INFO(dev)->gen >= 3) {
10127 if (obj->tiling_mode)
10128 pitch_limit = 8*1024;
10129 else
10130 pitch_limit = 16*1024;
10131 } else
10132 /* XXX DSPC is limited to 4k tiled */
10133 pitch_limit = 8*1024;
10134
10135 if (mode_cmd->pitches[0] > pitch_limit) {
10136 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10137 obj->tiling_mode ? "tiled" : "linear",
10138 mode_cmd->pitches[0], pitch_limit);
10139 return -EINVAL;
10140 }
10141
10142 if (obj->tiling_mode != I915_TILING_NONE &&
10143 mode_cmd->pitches[0] != obj->stride) {
10144 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10145 mode_cmd->pitches[0], obj->stride);
10146 return -EINVAL;
10147 }
10148
10149 /* Reject formats not supported by any plane early. */
10150 switch (mode_cmd->pixel_format) {
10151 case DRM_FORMAT_C8:
10152 case DRM_FORMAT_RGB565:
10153 case DRM_FORMAT_XRGB8888:
10154 case DRM_FORMAT_ARGB8888:
10155 break;
10156 case DRM_FORMAT_XRGB1555:
10157 case DRM_FORMAT_ARGB1555:
10158 if (INTEL_INFO(dev)->gen > 3) {
10159 DRM_DEBUG("unsupported pixel format: %s\n",
10160 drm_get_format_name(mode_cmd->pixel_format));
10161 return -EINVAL;
10162 }
10163 break;
10164 case DRM_FORMAT_XBGR8888:
10165 case DRM_FORMAT_ABGR8888:
10166 case DRM_FORMAT_XRGB2101010:
10167 case DRM_FORMAT_ARGB2101010:
10168 case DRM_FORMAT_XBGR2101010:
10169 case DRM_FORMAT_ABGR2101010:
10170 if (INTEL_INFO(dev)->gen < 4) {
10171 DRM_DEBUG("unsupported pixel format: %s\n",
10172 drm_get_format_name(mode_cmd->pixel_format));
10173 return -EINVAL;
10174 }
10175 break;
10176 case DRM_FORMAT_YUYV:
10177 case DRM_FORMAT_UYVY:
10178 case DRM_FORMAT_YVYU:
10179 case DRM_FORMAT_VYUY:
10180 if (INTEL_INFO(dev)->gen < 5) {
10181 DRM_DEBUG("unsupported pixel format: %s\n",
10182 drm_get_format_name(mode_cmd->pixel_format));
10183 return -EINVAL;
10184 }
10185 break;
10186 default:
10187 DRM_DEBUG("unsupported pixel format: %s\n",
10188 drm_get_format_name(mode_cmd->pixel_format));
10189 return -EINVAL;
10190 }
10191
10192 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10193 if (mode_cmd->offsets[0] != 0)
10194 return -EINVAL;
10195
10196 tile_height = IS_GEN2(dev) ? 16 : 8;
10197 aligned_height = ALIGN(mode_cmd->height,
10198 obj->tiling_mode ? tile_height : 1);
10199 /* FIXME drm helper for size checks (especially planar formats)? */
10200 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10201 return -EINVAL;
10202
10203 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10204 intel_fb->obj = obj;
10205 intel_fb->obj->framebuffer_references++;
10206
10207 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10208 if (ret) {
10209 DRM_ERROR("framebuffer init failed %d\n", ret);
10210 return ret;
10211 }
10212
10213 return 0;
10214 }
10215
10216 static struct drm_framebuffer *
10217 intel_user_framebuffer_create(struct drm_device *dev,
10218 struct drm_file *filp,
10219 struct drm_mode_fb_cmd2 *mode_cmd)
10220 {
10221 struct drm_i915_gem_object *obj;
10222
10223 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10224 mode_cmd->handles[0]));
10225 if (&obj->base == NULL)
10226 return ERR_PTR(-ENOENT);
10227
10228 return intel_framebuffer_create(dev, mode_cmd, obj);
10229 }
10230
10231 #ifndef CONFIG_DRM_I915_FBDEV
10232 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10233 {
10234 }
10235 #endif
10236
10237 static const struct drm_mode_config_funcs intel_mode_funcs = {
10238 .fb_create = intel_user_framebuffer_create,
10239 .output_poll_changed = intel_fbdev_output_poll_changed,
10240 };
10241
10242 /* Set up chip specific display functions */
10243 static void intel_init_display(struct drm_device *dev)
10244 {
10245 struct drm_i915_private *dev_priv = dev->dev_private;
10246
10247 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10248 dev_priv->display.find_dpll = g4x_find_best_dpll;
10249 else if (IS_VALLEYVIEW(dev))
10250 dev_priv->display.find_dpll = vlv_find_best_dpll;
10251 else if (IS_PINEVIEW(dev))
10252 dev_priv->display.find_dpll = pnv_find_best_dpll;
10253 else
10254 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10255
10256 if (HAS_DDI(dev)) {
10257 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10258 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10259 dev_priv->display.crtc_enable = haswell_crtc_enable;
10260 dev_priv->display.crtc_disable = haswell_crtc_disable;
10261 dev_priv->display.off = haswell_crtc_off;
10262 dev_priv->display.update_plane = ironlake_update_plane;
10263 } else if (HAS_PCH_SPLIT(dev)) {
10264 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10265 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10266 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10267 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10268 dev_priv->display.off = ironlake_crtc_off;
10269 dev_priv->display.update_plane = ironlake_update_plane;
10270 } else if (IS_VALLEYVIEW(dev)) {
10271 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10272 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10273 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10274 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10275 dev_priv->display.off = i9xx_crtc_off;
10276 dev_priv->display.update_plane = i9xx_update_plane;
10277 } else {
10278 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10279 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10280 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10281 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10282 dev_priv->display.off = i9xx_crtc_off;
10283 dev_priv->display.update_plane = i9xx_update_plane;
10284 }
10285
10286 /* Returns the core display clock speed */
10287 if (IS_VALLEYVIEW(dev))
10288 dev_priv->display.get_display_clock_speed =
10289 valleyview_get_display_clock_speed;
10290 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10291 dev_priv->display.get_display_clock_speed =
10292 i945_get_display_clock_speed;
10293 else if (IS_I915G(dev))
10294 dev_priv->display.get_display_clock_speed =
10295 i915_get_display_clock_speed;
10296 else if (IS_I945GM(dev) || IS_845G(dev))
10297 dev_priv->display.get_display_clock_speed =
10298 i9xx_misc_get_display_clock_speed;
10299 else if (IS_PINEVIEW(dev))
10300 dev_priv->display.get_display_clock_speed =
10301 pnv_get_display_clock_speed;
10302 else if (IS_I915GM(dev))
10303 dev_priv->display.get_display_clock_speed =
10304 i915gm_get_display_clock_speed;
10305 else if (IS_I865G(dev))
10306 dev_priv->display.get_display_clock_speed =
10307 i865_get_display_clock_speed;
10308 else if (IS_I85X(dev))
10309 dev_priv->display.get_display_clock_speed =
10310 i855_get_display_clock_speed;
10311 else /* 852, 830 */
10312 dev_priv->display.get_display_clock_speed =
10313 i830_get_display_clock_speed;
10314
10315 if (HAS_PCH_SPLIT(dev)) {
10316 if (IS_GEN5(dev)) {
10317 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10318 dev_priv->display.write_eld = ironlake_write_eld;
10319 } else if (IS_GEN6(dev)) {
10320 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10321 dev_priv->display.write_eld = ironlake_write_eld;
10322 } else if (IS_IVYBRIDGE(dev)) {
10323 /* FIXME: detect B0+ stepping and use auto training */
10324 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10325 dev_priv->display.write_eld = ironlake_write_eld;
10326 dev_priv->display.modeset_global_resources =
10327 ivb_modeset_global_resources;
10328 } else if (IS_HASWELL(dev)) {
10329 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10330 dev_priv->display.write_eld = haswell_write_eld;
10331 dev_priv->display.modeset_global_resources =
10332 haswell_modeset_global_resources;
10333 }
10334 } else if (IS_G4X(dev)) {
10335 dev_priv->display.write_eld = g4x_write_eld;
10336 } else if (IS_VALLEYVIEW(dev))
10337 dev_priv->display.write_eld = ironlake_write_eld;
10338
10339 /* Default just returns -ENODEV to indicate unsupported */
10340 dev_priv->display.queue_flip = intel_default_queue_flip;
10341
10342 switch (INTEL_INFO(dev)->gen) {
10343 case 2:
10344 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10345 break;
10346
10347 case 3:
10348 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10349 break;
10350
10351 case 4:
10352 case 5:
10353 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10354 break;
10355
10356 case 6:
10357 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10358 break;
10359 case 7:
10360 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10361 break;
10362 }
10363 }
10364
10365 /*
10366 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10367 * resume, or other times. This quirk makes sure that's the case for
10368 * affected systems.
10369 */
10370 static void quirk_pipea_force(struct drm_device *dev)
10371 {
10372 struct drm_i915_private *dev_priv = dev->dev_private;
10373
10374 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10375 DRM_INFO("applying pipe a force quirk\n");
10376 }
10377
10378 /*
10379 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10380 */
10381 static void quirk_ssc_force_disable(struct drm_device *dev)
10382 {
10383 struct drm_i915_private *dev_priv = dev->dev_private;
10384 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10385 DRM_INFO("applying lvds SSC disable quirk\n");
10386 }
10387
10388 /*
10389 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10390 * brightness value
10391 */
10392 static void quirk_invert_brightness(struct drm_device *dev)
10393 {
10394 struct drm_i915_private *dev_priv = dev->dev_private;
10395 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10396 DRM_INFO("applying inverted panel brightness quirk\n");
10397 }
10398
10399 /*
10400 * Some machines (Dell XPS13) suffer broken backlight controls if
10401 * BLM_PCH_PWM_ENABLE is set.
10402 */
10403 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10404 {
10405 struct drm_i915_private *dev_priv = dev->dev_private;
10406 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10407 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10408 }
10409
10410 struct intel_quirk {
10411 int device;
10412 int subsystem_vendor;
10413 int subsystem_device;
10414 void (*hook)(struct drm_device *dev);
10415 };
10416
10417 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10418 struct intel_dmi_quirk {
10419 void (*hook)(struct drm_device *dev);
10420 const struct dmi_system_id (*dmi_id_list)[];
10421 };
10422
10423 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10424 {
10425 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10426 return 1;
10427 }
10428
10429 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10430 {
10431 .dmi_id_list = &(const struct dmi_system_id[]) {
10432 {
10433 .callback = intel_dmi_reverse_brightness,
10434 .ident = "NCR Corporation",
10435 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10436 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10437 },
10438 },
10439 { } /* terminating entry */
10440 },
10441 .hook = quirk_invert_brightness,
10442 },
10443 };
10444
10445 static struct intel_quirk intel_quirks[] = {
10446 /* HP Mini needs pipe A force quirk (LP: #322104) */
10447 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10448
10449 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10450 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10451
10452 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10453 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10454
10455 /* 830 needs to leave pipe A & dpll A up */
10456 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10457
10458 /* Lenovo U160 cannot use SSC on LVDS */
10459 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10460
10461 /* Sony Vaio Y cannot use SSC on LVDS */
10462 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10463
10464 /*
10465 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10466 * seem to use inverted backlight PWM.
10467 */
10468 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
10469
10470 /* Dell XPS13 HD Sandy Bridge */
10471 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10472 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10473 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
10474 };
10475
10476 static void intel_init_quirks(struct drm_device *dev)
10477 {
10478 struct pci_dev *d = dev->pdev;
10479 int i;
10480
10481 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10482 struct intel_quirk *q = &intel_quirks[i];
10483
10484 if (d->device == q->device &&
10485 (d->subsystem_vendor == q->subsystem_vendor ||
10486 q->subsystem_vendor == PCI_ANY_ID) &&
10487 (d->subsystem_device == q->subsystem_device ||
10488 q->subsystem_device == PCI_ANY_ID))
10489 q->hook(dev);
10490 }
10491 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10492 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10493 intel_dmi_quirks[i].hook(dev);
10494 }
10495 }
10496
10497 /* Disable the VGA plane that we never use */
10498 static void i915_disable_vga(struct drm_device *dev)
10499 {
10500 struct drm_i915_private *dev_priv = dev->dev_private;
10501 u8 sr1;
10502 u32 vga_reg = i915_vgacntrl_reg(dev);
10503
10504 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10505 outb(SR01, VGA_SR_INDEX);
10506 sr1 = inb(VGA_SR_DATA);
10507 outb(sr1 | 1<<5, VGA_SR_DATA);
10508 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10509 udelay(300);
10510
10511 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10512 POSTING_READ(vga_reg);
10513 }
10514
10515 void intel_modeset_init_hw(struct drm_device *dev)
10516 {
10517 struct drm_i915_private *dev_priv = dev->dev_private;
10518
10519 intel_prepare_ddi(dev);
10520
10521 intel_init_clock_gating(dev);
10522
10523 /* Enable the CRI clock source so we can get at the display */
10524 if (IS_VALLEYVIEW(dev))
10525 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
10526 DPLL_INTEGRATED_CRI_CLK_VLV);
10527
10528 intel_init_dpio(dev);
10529
10530 mutex_lock(&dev->struct_mutex);
10531 intel_enable_gt_powersave(dev);
10532 mutex_unlock(&dev->struct_mutex);
10533 }
10534
10535 void intel_modeset_suspend_hw(struct drm_device *dev)
10536 {
10537 intel_suspend_hw(dev);
10538 }
10539
10540 void intel_modeset_init(struct drm_device *dev)
10541 {
10542 struct drm_i915_private *dev_priv = dev->dev_private;
10543 int i, j, ret;
10544
10545 drm_mode_config_init(dev);
10546
10547 dev->mode_config.min_width = 0;
10548 dev->mode_config.min_height = 0;
10549
10550 dev->mode_config.preferred_depth = 24;
10551 dev->mode_config.prefer_shadow = 1;
10552
10553 dev->mode_config.funcs = &intel_mode_funcs;
10554
10555 intel_init_quirks(dev);
10556
10557 intel_init_pm(dev);
10558
10559 if (INTEL_INFO(dev)->num_pipes == 0)
10560 return;
10561
10562 intel_init_display(dev);
10563
10564 if (IS_GEN2(dev)) {
10565 dev->mode_config.max_width = 2048;
10566 dev->mode_config.max_height = 2048;
10567 } else if (IS_GEN3(dev)) {
10568 dev->mode_config.max_width = 4096;
10569 dev->mode_config.max_height = 4096;
10570 } else {
10571 dev->mode_config.max_width = 8192;
10572 dev->mode_config.max_height = 8192;
10573 }
10574 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10575
10576 DRM_DEBUG_KMS("%d display pipe%s available.\n",
10577 INTEL_INFO(dev)->num_pipes,
10578 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10579
10580 for_each_pipe(i) {
10581 intel_crtc_init(dev, i);
10582 for (j = 0; j < dev_priv->num_plane; j++) {
10583 ret = intel_plane_init(dev, i, j);
10584 if (ret)
10585 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10586 pipe_name(i), sprite_name(i, j), ret);
10587 }
10588 }
10589
10590 intel_cpu_pll_init(dev);
10591 intel_shared_dpll_init(dev);
10592
10593 /* Just disable it once at startup */
10594 i915_disable_vga(dev);
10595 intel_setup_outputs(dev);
10596
10597 /* Just in case the BIOS is doing something questionable. */
10598 intel_disable_fbc(dev);
10599 }
10600
10601 static void
10602 intel_connector_break_all_links(struct intel_connector *connector)
10603 {
10604 connector->base.dpms = DRM_MODE_DPMS_OFF;
10605 connector->base.encoder = NULL;
10606 connector->encoder->connectors_active = false;
10607 connector->encoder->base.crtc = NULL;
10608 }
10609
10610 static void intel_enable_pipe_a(struct drm_device *dev)
10611 {
10612 struct intel_connector *connector;
10613 struct drm_connector *crt = NULL;
10614 struct intel_load_detect_pipe load_detect_temp;
10615
10616 /* We can't just switch on the pipe A, we need to set things up with a
10617 * proper mode and output configuration. As a gross hack, enable pipe A
10618 * by enabling the load detect pipe once. */
10619 list_for_each_entry(connector,
10620 &dev->mode_config.connector_list,
10621 base.head) {
10622 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10623 crt = &connector->base;
10624 break;
10625 }
10626 }
10627
10628 if (!crt)
10629 return;
10630
10631 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10632 intel_release_load_detect_pipe(crt, &load_detect_temp);
10633
10634
10635 }
10636
10637 static bool
10638 intel_check_plane_mapping(struct intel_crtc *crtc)
10639 {
10640 struct drm_device *dev = crtc->base.dev;
10641 struct drm_i915_private *dev_priv = dev->dev_private;
10642 u32 reg, val;
10643
10644 if (INTEL_INFO(dev)->num_pipes == 1)
10645 return true;
10646
10647 reg = DSPCNTR(!crtc->plane);
10648 val = I915_READ(reg);
10649
10650 if ((val & DISPLAY_PLANE_ENABLE) &&
10651 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10652 return false;
10653
10654 return true;
10655 }
10656
10657 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10658 {
10659 struct drm_device *dev = crtc->base.dev;
10660 struct drm_i915_private *dev_priv = dev->dev_private;
10661 u32 reg;
10662
10663 /* Clear any frame start delays used for debugging left by the BIOS */
10664 reg = PIPECONF(crtc->config.cpu_transcoder);
10665 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10666
10667 /* We need to sanitize the plane -> pipe mapping first because this will
10668 * disable the crtc (and hence change the state) if it is wrong. Note
10669 * that gen4+ has a fixed plane -> pipe mapping. */
10670 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10671 struct intel_connector *connector;
10672 bool plane;
10673
10674 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10675 crtc->base.base.id);
10676
10677 /* Pipe has the wrong plane attached and the plane is active.
10678 * Temporarily change the plane mapping and disable everything
10679 * ... */
10680 plane = crtc->plane;
10681 crtc->plane = !plane;
10682 dev_priv->display.crtc_disable(&crtc->base);
10683 crtc->plane = plane;
10684
10685 /* ... and break all links. */
10686 list_for_each_entry(connector, &dev->mode_config.connector_list,
10687 base.head) {
10688 if (connector->encoder->base.crtc != &crtc->base)
10689 continue;
10690
10691 intel_connector_break_all_links(connector);
10692 }
10693
10694 WARN_ON(crtc->active);
10695 crtc->base.enabled = false;
10696 }
10697
10698 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10699 crtc->pipe == PIPE_A && !crtc->active) {
10700 /* BIOS forgot to enable pipe A, this mostly happens after
10701 * resume. Force-enable the pipe to fix this, the update_dpms
10702 * call below we restore the pipe to the right state, but leave
10703 * the required bits on. */
10704 intel_enable_pipe_a(dev);
10705 }
10706
10707 /* Adjust the state of the output pipe according to whether we
10708 * have active connectors/encoders. */
10709 intel_crtc_update_dpms(&crtc->base);
10710
10711 if (crtc->active != crtc->base.enabled) {
10712 struct intel_encoder *encoder;
10713
10714 /* This can happen either due to bugs in the get_hw_state
10715 * functions or because the pipe is force-enabled due to the
10716 * pipe A quirk. */
10717 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10718 crtc->base.base.id,
10719 crtc->base.enabled ? "enabled" : "disabled",
10720 crtc->active ? "enabled" : "disabled");
10721
10722 crtc->base.enabled = crtc->active;
10723
10724 /* Because we only establish the connector -> encoder ->
10725 * crtc links if something is active, this means the
10726 * crtc is now deactivated. Break the links. connector
10727 * -> encoder links are only establish when things are
10728 * actually up, hence no need to break them. */
10729 WARN_ON(crtc->active);
10730
10731 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10732 WARN_ON(encoder->connectors_active);
10733 encoder->base.crtc = NULL;
10734 }
10735 }
10736 }
10737
10738 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10739 {
10740 struct intel_connector *connector;
10741 struct drm_device *dev = encoder->base.dev;
10742
10743 /* We need to check both for a crtc link (meaning that the
10744 * encoder is active and trying to read from a pipe) and the
10745 * pipe itself being active. */
10746 bool has_active_crtc = encoder->base.crtc &&
10747 to_intel_crtc(encoder->base.crtc)->active;
10748
10749 if (encoder->connectors_active && !has_active_crtc) {
10750 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10751 encoder->base.base.id,
10752 drm_get_encoder_name(&encoder->base));
10753
10754 /* Connector is active, but has no active pipe. This is
10755 * fallout from our resume register restoring. Disable
10756 * the encoder manually again. */
10757 if (encoder->base.crtc) {
10758 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10759 encoder->base.base.id,
10760 drm_get_encoder_name(&encoder->base));
10761 encoder->disable(encoder);
10762 }
10763
10764 /* Inconsistent output/port/pipe state happens presumably due to
10765 * a bug in one of the get_hw_state functions. Or someplace else
10766 * in our code, like the register restore mess on resume. Clamp
10767 * things to off as a safer default. */
10768 list_for_each_entry(connector,
10769 &dev->mode_config.connector_list,
10770 base.head) {
10771 if (connector->encoder != encoder)
10772 continue;
10773
10774 intel_connector_break_all_links(connector);
10775 }
10776 }
10777 /* Enabled encoders without active connectors will be fixed in
10778 * the crtc fixup. */
10779 }
10780
10781 void i915_redisable_vga(struct drm_device *dev)
10782 {
10783 struct drm_i915_private *dev_priv = dev->dev_private;
10784 u32 vga_reg = i915_vgacntrl_reg(dev);
10785
10786 /* This function can be called both from intel_modeset_setup_hw_state or
10787 * at a very early point in our resume sequence, where the power well
10788 * structures are not yet restored. Since this function is at a very
10789 * paranoid "someone might have enabled VGA while we were not looking"
10790 * level, just check if the power well is enabled instead of trying to
10791 * follow the "don't touch the power well if we don't need it" policy
10792 * the rest of the driver uses. */
10793 if (HAS_POWER_WELL(dev) &&
10794 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
10795 return;
10796
10797 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
10798 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10799 i915_disable_vga(dev);
10800 }
10801 }
10802
10803 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10804 {
10805 struct drm_i915_private *dev_priv = dev->dev_private;
10806 enum pipe pipe;
10807 struct intel_crtc *crtc;
10808 struct intel_encoder *encoder;
10809 struct intel_connector *connector;
10810 int i;
10811
10812 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10813 base.head) {
10814 memset(&crtc->config, 0, sizeof(crtc->config));
10815
10816 crtc->active = dev_priv->display.get_pipe_config(crtc,
10817 &crtc->config);
10818
10819 crtc->base.enabled = crtc->active;
10820 crtc->primary_enabled = crtc->active;
10821
10822 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10823 crtc->base.base.id,
10824 crtc->active ? "enabled" : "disabled");
10825 }
10826
10827 /* FIXME: Smash this into the new shared dpll infrastructure. */
10828 if (HAS_DDI(dev))
10829 intel_ddi_setup_hw_pll_state(dev);
10830
10831 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10832 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10833
10834 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10835 pll->active = 0;
10836 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10837 base.head) {
10838 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10839 pll->active++;
10840 }
10841 pll->refcount = pll->active;
10842
10843 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10844 pll->name, pll->refcount, pll->on);
10845 }
10846
10847 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10848 base.head) {
10849 pipe = 0;
10850
10851 if (encoder->get_hw_state(encoder, &pipe)) {
10852 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10853 encoder->base.crtc = &crtc->base;
10854 if (encoder->get_config)
10855 encoder->get_config(encoder, &crtc->config);
10856 } else {
10857 encoder->base.crtc = NULL;
10858 }
10859
10860 encoder->connectors_active = false;
10861 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
10862 encoder->base.base.id,
10863 drm_get_encoder_name(&encoder->base),
10864 encoder->base.crtc ? "enabled" : "disabled",
10865 pipe_name(pipe));
10866 }
10867
10868 list_for_each_entry(connector, &dev->mode_config.connector_list,
10869 base.head) {
10870 if (connector->get_hw_state(connector)) {
10871 connector->base.dpms = DRM_MODE_DPMS_ON;
10872 connector->encoder->connectors_active = true;
10873 connector->base.encoder = &connector->encoder->base;
10874 } else {
10875 connector->base.dpms = DRM_MODE_DPMS_OFF;
10876 connector->base.encoder = NULL;
10877 }
10878 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10879 connector->base.base.id,
10880 drm_get_connector_name(&connector->base),
10881 connector->base.encoder ? "enabled" : "disabled");
10882 }
10883 }
10884
10885 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10886 * and i915 state tracking structures. */
10887 void intel_modeset_setup_hw_state(struct drm_device *dev,
10888 bool force_restore)
10889 {
10890 struct drm_i915_private *dev_priv = dev->dev_private;
10891 enum pipe pipe;
10892 struct intel_crtc *crtc;
10893 struct intel_encoder *encoder;
10894 int i;
10895
10896 intel_modeset_readout_hw_state(dev);
10897
10898 /*
10899 * Now that we have the config, copy it to each CRTC struct
10900 * Note that this could go away if we move to using crtc_config
10901 * checking everywhere.
10902 */
10903 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10904 base.head) {
10905 if (crtc->active && i915_fastboot) {
10906 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10907
10908 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10909 crtc->base.base.id);
10910 drm_mode_debug_printmodeline(&crtc->base.mode);
10911 }
10912 }
10913
10914 /* HW state is read out, now we need to sanitize this mess. */
10915 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10916 base.head) {
10917 intel_sanitize_encoder(encoder);
10918 }
10919
10920 for_each_pipe(pipe) {
10921 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10922 intel_sanitize_crtc(crtc);
10923 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10924 }
10925
10926 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10927 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10928
10929 if (!pll->on || pll->active)
10930 continue;
10931
10932 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10933
10934 pll->disable(dev_priv, pll);
10935 pll->on = false;
10936 }
10937
10938 if (IS_HASWELL(dev))
10939 ilk_wm_get_hw_state(dev);
10940
10941 if (force_restore) {
10942 i915_redisable_vga(dev);
10943
10944 /*
10945 * We need to use raw interfaces for restoring state to avoid
10946 * checking (bogus) intermediate states.
10947 */
10948 for_each_pipe(pipe) {
10949 struct drm_crtc *crtc =
10950 dev_priv->pipe_to_crtc_mapping[pipe];
10951
10952 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10953 crtc->fb);
10954 }
10955 } else {
10956 intel_modeset_update_staged_output_state(dev);
10957 }
10958
10959 intel_modeset_check_state(dev);
10960
10961 drm_mode_config_reset(dev);
10962 }
10963
10964 void intel_modeset_gem_init(struct drm_device *dev)
10965 {
10966 intel_modeset_init_hw(dev);
10967
10968 intel_setup_overlay(dev);
10969
10970 intel_modeset_setup_hw_state(dev, false);
10971 }
10972
10973 void intel_modeset_cleanup(struct drm_device *dev)
10974 {
10975 struct drm_i915_private *dev_priv = dev->dev_private;
10976 struct drm_crtc *crtc;
10977 struct drm_connector *connector;
10978
10979 /*
10980 * Interrupts and polling as the first thing to avoid creating havoc.
10981 * Too much stuff here (turning of rps, connectors, ...) would
10982 * experience fancy races otherwise.
10983 */
10984 drm_irq_uninstall(dev);
10985 cancel_work_sync(&dev_priv->hotplug_work);
10986 /*
10987 * Due to the hpd irq storm handling the hotplug work can re-arm the
10988 * poll handlers. Hence disable polling after hpd handling is shut down.
10989 */
10990 drm_kms_helper_poll_fini(dev);
10991
10992 mutex_lock(&dev->struct_mutex);
10993
10994 intel_unregister_dsm_handler();
10995
10996 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10997 /* Skip inactive CRTCs */
10998 if (!crtc->fb)
10999 continue;
11000
11001 intel_increase_pllclock(crtc);
11002 }
11003
11004 intel_disable_fbc(dev);
11005
11006 intel_disable_gt_powersave(dev);
11007
11008 ironlake_teardown_rc6(dev);
11009
11010 mutex_unlock(&dev->struct_mutex);
11011
11012 /* flush any delayed tasks or pending work */
11013 flush_scheduled_work();
11014
11015 /* destroy backlight, if any, before the connectors */
11016 intel_panel_destroy_backlight(dev);
11017
11018 /* destroy the sysfs files before encoders/connectors */
11019 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
11020 drm_sysfs_connector_remove(connector);
11021
11022 drm_mode_config_cleanup(dev);
11023
11024 intel_cleanup_overlay(dev);
11025 }
11026
11027 /*
11028 * Return which encoder is currently attached for connector.
11029 */
11030 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11031 {
11032 return &intel_attached_encoder(connector)->base;
11033 }
11034
11035 void intel_connector_attach_encoder(struct intel_connector *connector,
11036 struct intel_encoder *encoder)
11037 {
11038 connector->encoder = encoder;
11039 drm_mode_connector_attach_encoder(&connector->base,
11040 &encoder->base);
11041 }
11042
11043 /*
11044 * set vga decode state - true == enable VGA decode
11045 */
11046 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11047 {
11048 struct drm_i915_private *dev_priv = dev->dev_private;
11049 u16 gmch_ctrl;
11050
11051 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
11052 if (state)
11053 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11054 else
11055 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11056 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
11057 return 0;
11058 }
11059
11060 struct intel_display_error_state {
11061
11062 u32 power_well_driver;
11063
11064 int num_transcoders;
11065
11066 struct intel_cursor_error_state {
11067 u32 control;
11068 u32 position;
11069 u32 base;
11070 u32 size;
11071 } cursor[I915_MAX_PIPES];
11072
11073 struct intel_pipe_error_state {
11074 u32 source;
11075 } pipe[I915_MAX_PIPES];
11076
11077 struct intel_plane_error_state {
11078 u32 control;
11079 u32 stride;
11080 u32 size;
11081 u32 pos;
11082 u32 addr;
11083 u32 surface;
11084 u32 tile_offset;
11085 } plane[I915_MAX_PIPES];
11086
11087 struct intel_transcoder_error_state {
11088 enum transcoder cpu_transcoder;
11089
11090 u32 conf;
11091
11092 u32 htotal;
11093 u32 hblank;
11094 u32 hsync;
11095 u32 vtotal;
11096 u32 vblank;
11097 u32 vsync;
11098 } transcoder[4];
11099 };
11100
11101 struct intel_display_error_state *
11102 intel_display_capture_error_state(struct drm_device *dev)
11103 {
11104 drm_i915_private_t *dev_priv = dev->dev_private;
11105 struct intel_display_error_state *error;
11106 int transcoders[] = {
11107 TRANSCODER_A,
11108 TRANSCODER_B,
11109 TRANSCODER_C,
11110 TRANSCODER_EDP,
11111 };
11112 int i;
11113
11114 if (INTEL_INFO(dev)->num_pipes == 0)
11115 return NULL;
11116
11117 error = kzalloc(sizeof(*error), GFP_ATOMIC);
11118 if (error == NULL)
11119 return NULL;
11120
11121 if (HAS_POWER_WELL(dev))
11122 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11123
11124 for_each_pipe(i) {
11125 if (!intel_display_power_enabled(dev, POWER_DOMAIN_PIPE(i)))
11126 continue;
11127
11128 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11129 error->cursor[i].control = I915_READ(CURCNTR(i));
11130 error->cursor[i].position = I915_READ(CURPOS(i));
11131 error->cursor[i].base = I915_READ(CURBASE(i));
11132 } else {
11133 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11134 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11135 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11136 }
11137
11138 error->plane[i].control = I915_READ(DSPCNTR(i));
11139 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11140 if (INTEL_INFO(dev)->gen <= 3) {
11141 error->plane[i].size = I915_READ(DSPSIZE(i));
11142 error->plane[i].pos = I915_READ(DSPPOS(i));
11143 }
11144 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11145 error->plane[i].addr = I915_READ(DSPADDR(i));
11146 if (INTEL_INFO(dev)->gen >= 4) {
11147 error->plane[i].surface = I915_READ(DSPSURF(i));
11148 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11149 }
11150
11151 error->pipe[i].source = I915_READ(PIPESRC(i));
11152 }
11153
11154 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11155 if (HAS_DDI(dev_priv->dev))
11156 error->num_transcoders++; /* Account for eDP. */
11157
11158 for (i = 0; i < error->num_transcoders; i++) {
11159 enum transcoder cpu_transcoder = transcoders[i];
11160
11161 if (!intel_display_power_enabled(dev,
11162 POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
11163 continue;
11164
11165 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11166
11167 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11168 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11169 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11170 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11171 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11172 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11173 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
11174 }
11175
11176 return error;
11177 }
11178
11179 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11180
11181 void
11182 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11183 struct drm_device *dev,
11184 struct intel_display_error_state *error)
11185 {
11186 int i;
11187
11188 if (!error)
11189 return;
11190
11191 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
11192 if (HAS_POWER_WELL(dev))
11193 err_printf(m, "PWR_WELL_CTL2: %08x\n",
11194 error->power_well_driver);
11195 for_each_pipe(i) {
11196 err_printf(m, "Pipe [%d]:\n", i);
11197 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
11198
11199 err_printf(m, "Plane [%d]:\n", i);
11200 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
11201 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
11202 if (INTEL_INFO(dev)->gen <= 3) {
11203 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
11204 err_printf(m, " POS: %08x\n", error->plane[i].pos);
11205 }
11206 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11207 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
11208 if (INTEL_INFO(dev)->gen >= 4) {
11209 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
11210 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
11211 }
11212
11213 err_printf(m, "Cursor [%d]:\n", i);
11214 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
11215 err_printf(m, " POS: %08x\n", error->cursor[i].position);
11216 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
11217 }
11218
11219 for (i = 0; i < error->num_transcoders; i++) {
11220 err_printf(m, "CPU transcoder: %c\n",
11221 transcoder_name(error->transcoder[i].cpu_transcoder));
11222 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
11223 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
11224 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
11225 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
11226 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
11227 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
11228 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
11229 }
11230 }
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