]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blob - drivers/gpu/drm/i915/intel_display.c
projects / mirror_ubuntu-hirsute-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/i915: introduce pipe_config->dither|pipe_bpp
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47
48 typedef struct {
49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
58 } intel_clock_t;
59
60 typedef struct {
61 int min, max;
62 } intel_range_t;
63
64 typedef struct {
65 int dot_limit;
66 int p2_slow, p2_fast;
67 } intel_p2_t;
68
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t;
71 struct intel_limit {
72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 /**
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
77 * @crtc: current CRTC
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
84 *
85 * Returns true on success, false on failure.
86 */
87 bool (*find_pll)(const intel_limit_t *limit,
88 struct drm_crtc *crtc,
89 int target, int refclk,
90 intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
92 };
93
94 /* FDI */
95 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
96
97 int
98 intel_pch_rawclk(struct drm_device *dev)
99 {
100 struct drm_i915_private *dev_priv = dev->dev_private;
101
102 WARN_ON(!HAS_PCH_SPLIT(dev));
103
104 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
105 }
106
107 static bool
108 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
109 int target, int refclk, intel_clock_t *match_clock,
110 intel_clock_t *best_clock);
111 static bool
112 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
115
116 static bool
117 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
118 int target, int refclk, intel_clock_t *match_clock,
119 intel_clock_t *best_clock);
120 static bool
121 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
122 int target, int refclk, intel_clock_t *match_clock,
123 intel_clock_t *best_clock);
124
125 static bool
126 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
127 int target, int refclk, intel_clock_t *match_clock,
128 intel_clock_t *best_clock);
129
130 static inline u32 /* units of 100MHz */
131 intel_fdi_link_freq(struct drm_device *dev)
132 {
133 if (IS_GEN5(dev)) {
134 struct drm_i915_private *dev_priv = dev->dev_private;
135 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
136 } else
137 return 27;
138 }
139
140 static const intel_limit_t intel_limits_i8xx_dvo = {
141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 2, .max = 33 },
149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 4, .p2_fast = 2 },
151 .find_pll = intel_find_best_PLL,
152 };
153
154 static const intel_limit_t intel_limits_i8xx_lvds = {
155 .dot = { .min = 25000, .max = 350000 },
156 .vco = { .min = 930000, .max = 1400000 },
157 .n = { .min = 3, .max = 16 },
158 .m = { .min = 96, .max = 140 },
159 .m1 = { .min = 18, .max = 26 },
160 .m2 = { .min = 6, .max = 16 },
161 .p = { .min = 4, .max = 128 },
162 .p1 = { .min = 1, .max = 6 },
163 .p2 = { .dot_limit = 165000,
164 .p2_slow = 14, .p2_fast = 7 },
165 .find_pll = intel_find_best_PLL,
166 };
167
168 static const intel_limit_t intel_limits_i9xx_sdvo = {
169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
173 .m1 = { .min = 8, .max = 18 },
174 .m2 = { .min = 3, .max = 7 },
175 .p = { .min = 5, .max = 80 },
176 .p1 = { .min = 1, .max = 8 },
177 .p2 = { .dot_limit = 200000,
178 .p2_slow = 10, .p2_fast = 5 },
179 .find_pll = intel_find_best_PLL,
180 };
181
182 static const intel_limit_t intel_limits_i9xx_lvds = {
183 .dot = { .min = 20000, .max = 400000 },
184 .vco = { .min = 1400000, .max = 2800000 },
185 .n = { .min = 1, .max = 6 },
186 .m = { .min = 70, .max = 120 },
187 .m1 = { .min = 8, .max = 18 },
188 .m2 = { .min = 3, .max = 7 },
189 .p = { .min = 7, .max = 98 },
190 .p1 = { .min = 1, .max = 8 },
191 .p2 = { .dot_limit = 112000,
192 .p2_slow = 14, .p2_fast = 7 },
193 .find_pll = intel_find_best_PLL,
194 };
195
196
197 static const intel_limit_t intel_limits_g4x_sdvo = {
198 .dot = { .min = 25000, .max = 270000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 17, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 10, .max = 30 },
205 .p1 = { .min = 1, .max = 3},
206 .p2 = { .dot_limit = 270000,
207 .p2_slow = 10,
208 .p2_fast = 10
209 },
210 .find_pll = intel_g4x_find_best_PLL,
211 };
212
213 static const intel_limit_t intel_limits_g4x_hdmi = {
214 .dot = { .min = 22000, .max = 400000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 16, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 5, .max = 80 },
221 .p1 = { .min = 1, .max = 8},
222 .p2 = { .dot_limit = 165000,
223 .p2_slow = 10, .p2_fast = 5 },
224 .find_pll = intel_g4x_find_best_PLL,
225 };
226
227 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
228 .dot = { .min = 20000, .max = 115000 },
229 .vco = { .min = 1750000, .max = 3500000 },
230 .n = { .min = 1, .max = 3 },
231 .m = { .min = 104, .max = 138 },
232 .m1 = { .min = 17, .max = 23 },
233 .m2 = { .min = 5, .max = 11 },
234 .p = { .min = 28, .max = 112 },
235 .p1 = { .min = 2, .max = 8 },
236 .p2 = { .dot_limit = 0,
237 .p2_slow = 14, .p2_fast = 14
238 },
239 .find_pll = intel_g4x_find_best_PLL,
240 };
241
242 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
243 .dot = { .min = 80000, .max = 224000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 14, .max = 42 },
250 .p1 = { .min = 2, .max = 6 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 7, .p2_fast = 7
253 },
254 .find_pll = intel_g4x_find_best_PLL,
255 };
256
257 static const intel_limit_t intel_limits_g4x_display_port = {
258 .dot = { .min = 161670, .max = 227000 },
259 .vco = { .min = 1750000, .max = 3500000},
260 .n = { .min = 1, .max = 2 },
261 .m = { .min = 97, .max = 108 },
262 .m1 = { .min = 0x10, .max = 0x12 },
263 .m2 = { .min = 0x05, .max = 0x06 },
264 .p = { .min = 10, .max = 20 },
265 .p1 = { .min = 1, .max = 2},
266 .p2 = { .dot_limit = 0,
267 .p2_slow = 10, .p2_fast = 10 },
268 .find_pll = intel_find_pll_g4x_dp,
269 };
270
271 static const intel_limit_t intel_limits_pineview_sdvo = {
272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
274 /* Pineview's Ncounter is a ring counter */
275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
277 /* Pineview only has one combined m divider, which we treat as m2. */
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
284 .find_pll = intel_find_best_PLL,
285 };
286
287 static const intel_limit_t intel_limits_pineview_lvds = {
288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
298 .find_pll = intel_find_best_PLL,
299 };
300
301 /* Ironlake / Sandybridge
302 *
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
305 */
306 static const intel_limit_t intel_limits_ironlake_dac = {
307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 5 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 5, .max = 80 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 10, .p2_fast = 5 },
317 .find_pll = intel_g4x_find_best_PLL,
318 };
319
320 static const intel_limit_t intel_limits_ironlake_single_lvds = {
321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 118 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
331 .find_pll = intel_g4x_find_best_PLL,
332 };
333
334 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 127 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 56 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
345 .find_pll = intel_g4x_find_best_PLL,
346 };
347
348 /* LVDS 100mhz refclk limits. */
349 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 28, .max = 112 },
357 .p1 = { .min = 2, .max = 8 },
358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 },
360 .find_pll = intel_g4x_find_best_PLL,
361 };
362
363 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
371 .p1 = { .min = 2, .max = 6 },
372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
374 .find_pll = intel_g4x_find_best_PLL,
375 };
376
377 static const intel_limit_t intel_limits_ironlake_display_port = {
378 .dot = { .min = 25000, .max = 350000 },
379 .vco = { .min = 1760000, .max = 3510000},
380 .n = { .min = 1, .max = 2 },
381 .m = { .min = 81, .max = 90 },
382 .m1 = { .min = 12, .max = 22 },
383 .m2 = { .min = 5, .max = 9 },
384 .p = { .min = 10, .max = 20 },
385 .p1 = { .min = 1, .max = 2},
386 .p2 = { .dot_limit = 0,
387 .p2_slow = 10, .p2_fast = 10 },
388 .find_pll = intel_find_pll_ironlake_dp,
389 };
390
391 static const intel_limit_t intel_limits_vlv_dac = {
392 .dot = { .min = 25000, .max = 270000 },
393 .vco = { .min = 4000000, .max = 6000000 },
394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 22, .max = 450 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403 };
404
405 static const intel_limit_t intel_limits_vlv_hdmi = {
406 .dot = { .min = 20000, .max = 165000 },
407 .vco = { .min = 4000000, .max = 5994000},
408 .n = { .min = 1, .max = 7 },
409 .m = { .min = 60, .max = 300 }, /* guess */
410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417 };
418
419 static const intel_limit_t intel_limits_vlv_dp = {
420 .dot = { .min = 25000, .max = 270000 },
421 .vco = { .min = 4000000, .max = 6000000 },
422 .n = { .min = 1, .max = 7 },
423 .m = { .min = 22, .max = 450 },
424 .m1 = { .min = 2, .max = 3 },
425 .m2 = { .min = 11, .max = 156 },
426 .p = { .min = 10, .max = 30 },
427 .p1 = { .min = 2, .max = 3 },
428 .p2 = { .dot_limit = 270000,
429 .p2_slow = 2, .p2_fast = 20 },
430 .find_pll = intel_vlv_find_best_pll,
431 };
432
433 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
434 {
435 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
436
437 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
439 return 0;
440 }
441
442 I915_WRITE(DPIO_REG, reg);
443 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
444 DPIO_BYTE);
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
447 return 0;
448 }
449
450 return I915_READ(DPIO_DATA);
451 }
452
453 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
454 u32 val)
455 {
456 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
457
458 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
459 DRM_ERROR("DPIO idle wait timed out\n");
460 return;
461 }
462
463 I915_WRITE(DPIO_DATA, val);
464 I915_WRITE(DPIO_REG, reg);
465 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
466 DPIO_BYTE);
467 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
468 DRM_ERROR("DPIO write wait timed out\n");
469 }
470
471 static void vlv_init_dpio(struct drm_device *dev)
472 {
473 struct drm_i915_private *dev_priv = dev->dev_private;
474
475 /* Reset the DPIO config */
476 I915_WRITE(DPIO_CTL, 0);
477 POSTING_READ(DPIO_CTL);
478 I915_WRITE(DPIO_CTL, 1);
479 POSTING_READ(DPIO_CTL);
480 }
481
482 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
483 int refclk)
484 {
485 struct drm_device *dev = crtc->dev;
486 const intel_limit_t *limit;
487
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
489 if (intel_is_dual_link_lvds(dev)) {
490 if (refclk == 100000)
491 limit = &intel_limits_ironlake_dual_lvds_100m;
492 else
493 limit = &intel_limits_ironlake_dual_lvds;
494 } else {
495 if (refclk == 100000)
496 limit = &intel_limits_ironlake_single_lvds_100m;
497 else
498 limit = &intel_limits_ironlake_single_lvds;
499 }
500 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
501 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
502 limit = &intel_limits_ironlake_display_port;
503 else
504 limit = &intel_limits_ironlake_dac;
505
506 return limit;
507 }
508
509 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
510 {
511 struct drm_device *dev = crtc->dev;
512 const intel_limit_t *limit;
513
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
515 if (intel_is_dual_link_lvds(dev))
516 limit = &intel_limits_g4x_dual_channel_lvds;
517 else
518 limit = &intel_limits_g4x_single_channel_lvds;
519 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
520 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
521 limit = &intel_limits_g4x_hdmi;
522 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
523 limit = &intel_limits_g4x_sdvo;
524 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
525 limit = &intel_limits_g4x_display_port;
526 } else /* The option is for other outputs */
527 limit = &intel_limits_i9xx_sdvo;
528
529 return limit;
530 }
531
532 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
533 {
534 struct drm_device *dev = crtc->dev;
535 const intel_limit_t *limit;
536
537 if (HAS_PCH_SPLIT(dev))
538 limit = intel_ironlake_limit(crtc, refclk);
539 else if (IS_G4X(dev)) {
540 limit = intel_g4x_limit(crtc);
541 } else if (IS_PINEVIEW(dev)) {
542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
543 limit = &intel_limits_pineview_lvds;
544 else
545 limit = &intel_limits_pineview_sdvo;
546 } else if (IS_VALLEYVIEW(dev)) {
547 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
548 limit = &intel_limits_vlv_dac;
549 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
550 limit = &intel_limits_vlv_hdmi;
551 else
552 limit = &intel_limits_vlv_dp;
553 } else if (!IS_GEN2(dev)) {
554 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
555 limit = &intel_limits_i9xx_lvds;
556 else
557 limit = &intel_limits_i9xx_sdvo;
558 } else {
559 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
560 limit = &intel_limits_i8xx_lvds;
561 else
562 limit = &intel_limits_i8xx_dvo;
563 }
564 return limit;
565 }
566
567 /* m1 is reserved as 0 in Pineview, n is a ring counter */
568 static void pineview_clock(int refclk, intel_clock_t *clock)
569 {
570 clock->m = clock->m2 + 2;
571 clock->p = clock->p1 * clock->p2;
572 clock->vco = refclk * clock->m / clock->n;
573 clock->dot = clock->vco / clock->p;
574 }
575
576 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
577 {
578 if (IS_PINEVIEW(dev)) {
579 pineview_clock(refclk, clock);
580 return;
581 }
582 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
583 clock->p = clock->p1 * clock->p2;
584 clock->vco = refclk * clock->m / (clock->n + 2);
585 clock->dot = clock->vco / clock->p;
586 }
587
588 /**
589 * Returns whether any output on the specified pipe is of the specified type
590 */
591 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
592 {
593 struct drm_device *dev = crtc->dev;
594 struct intel_encoder *encoder;
595
596 for_each_encoder_on_crtc(dev, crtc, encoder)
597 if (encoder->type == type)
598 return true;
599
600 return false;
601 }
602
603 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
604 /**
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
607 */
608
609 static bool intel_PLL_is_valid(struct drm_device *dev,
610 const intel_limit_t *limit,
611 const intel_clock_t *clock)
612 {
613 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
614 INTELPllInvalid("p1 out of range\n");
615 if (clock->p < limit->p.min || limit->p.max < clock->p)
616 INTELPllInvalid("p out of range\n");
617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
618 INTELPllInvalid("m2 out of range\n");
619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
620 INTELPllInvalid("m1 out of range\n");
621 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
622 INTELPllInvalid("m1 <= m2\n");
623 if (clock->m < limit->m.min || limit->m.max < clock->m)
624 INTELPllInvalid("m out of range\n");
625 if (clock->n < limit->n.min || limit->n.max < clock->n)
626 INTELPllInvalid("n out of range\n");
627 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
628 INTELPllInvalid("vco out of range\n");
629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
631 */
632 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
633 INTELPllInvalid("dot out of range\n");
634
635 return true;
636 }
637
638 static bool
639 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
640 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock)
642
643 {
644 struct drm_device *dev = crtc->dev;
645 intel_clock_t clock;
646 int err = target;
647
648 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
649 /*
650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
653 */
654 if (intel_is_dual_link_lvds(dev))
655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
665 memset(best_clock, 0, sizeof(*best_clock));
666
667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
668 clock.m1++) {
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
671 /* m1 is always 0 in Pineview */
672 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
673 break;
674 for (clock.n = limit->n.min;
675 clock.n <= limit->n.max; clock.n++) {
676 for (clock.p1 = limit->p1.min;
677 clock.p1 <= limit->p1.max; clock.p1++) {
678 int this_err;
679
680 intel_clock(dev, refclk, &clock);
681 if (!intel_PLL_is_valid(dev, limit,
682 &clock))
683 continue;
684 if (match_clock &&
685 clock.p != match_clock->p)
686 continue;
687
688 this_err = abs(clock.dot - target);
689 if (this_err < err) {
690 *best_clock = clock;
691 err = this_err;
692 }
693 }
694 }
695 }
696 }
697
698 return (err != target);
699 }
700
701 static bool
702 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
703 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock)
705 {
706 struct drm_device *dev = crtc->dev;
707 intel_clock_t clock;
708 int max_n;
709 bool found;
710 /* approximately equals target * 0.00585 */
711 int err_most = (target >> 8) + (target >> 9);
712 found = false;
713
714 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
715 int lvds_reg;
716
717 if (HAS_PCH_SPLIT(dev))
718 lvds_reg = PCH_LVDS;
719 else
720 lvds_reg = LVDS;
721 if (intel_is_dual_link_lvds(dev))
722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
732 memset(best_clock, 0, sizeof(*best_clock));
733 max_n = limit->n.max;
734 /* based on hardware requirement, prefer smaller n to precision */
735 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
736 /* based on hardware requirement, prefere larger m1,m2 */
737 for (clock.m1 = limit->m1.max;
738 clock.m1 >= limit->m1.min; clock.m1--) {
739 for (clock.m2 = limit->m2.max;
740 clock.m2 >= limit->m2.min; clock.m2--) {
741 for (clock.p1 = limit->p1.max;
742 clock.p1 >= limit->p1.min; clock.p1--) {
743 int this_err;
744
745 intel_clock(dev, refclk, &clock);
746 if (!intel_PLL_is_valid(dev, limit,
747 &clock))
748 continue;
749 if (match_clock &&
750 clock.p != match_clock->p)
751 continue;
752
753 this_err = abs(clock.dot - target);
754 if (this_err < err_most) {
755 *best_clock = clock;
756 err_most = this_err;
757 max_n = clock.n;
758 found = true;
759 }
760 }
761 }
762 }
763 }
764 return found;
765 }
766
767 static bool
768 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
769 int target, int refclk, intel_clock_t *match_clock,
770 intel_clock_t *best_clock)
771 {
772 struct drm_device *dev = crtc->dev;
773 intel_clock_t clock;
774
775 if (target < 200000) {
776 clock.n = 1;
777 clock.p1 = 2;
778 clock.p2 = 10;
779 clock.m1 = 12;
780 clock.m2 = 9;
781 } else {
782 clock.n = 2;
783 clock.p1 = 1;
784 clock.p2 = 10;
785 clock.m1 = 14;
786 clock.m2 = 8;
787 }
788 intel_clock(dev, refclk, &clock);
789 memcpy(best_clock, &clock, sizeof(intel_clock_t));
790 return true;
791 }
792
793 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
794 static bool
795 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
796 int target, int refclk, intel_clock_t *match_clock,
797 intel_clock_t *best_clock)
798 {
799 intel_clock_t clock;
800 if (target < 200000) {
801 clock.p1 = 2;
802 clock.p2 = 10;
803 clock.n = 2;
804 clock.m1 = 23;
805 clock.m2 = 8;
806 } else {
807 clock.p1 = 1;
808 clock.p2 = 10;
809 clock.n = 1;
810 clock.m1 = 14;
811 clock.m2 = 2;
812 }
813 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
814 clock.p = (clock.p1 * clock.p2);
815 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
816 clock.vco = 0;
817 memcpy(best_clock, &clock, sizeof(intel_clock_t));
818 return true;
819 }
820 static bool
821 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
822 int target, int refclk, intel_clock_t *match_clock,
823 intel_clock_t *best_clock)
824 {
825 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
826 u32 m, n, fastclk;
827 u32 updrate, minupdate, fracbits, p;
828 unsigned long bestppm, ppm, absppm;
829 int dotclk, flag;
830
831 flag = 0;
832 dotclk = target * 1000;
833 bestppm = 1000000;
834 ppm = absppm = 0;
835 fastclk = dotclk / (2*100);
836 updrate = 0;
837 minupdate = 19200;
838 fracbits = 1;
839 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
840 bestm1 = bestm2 = bestp1 = bestp2 = 0;
841
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
844 updrate = refclk / n;
845 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
846 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
847 if (p2 > 10)
848 p2 = p2 - 1;
849 p = p1 * p2;
850 /* based on hardware requirement, prefer bigger m1,m2 values */
851 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
852 m2 = (((2*(fastclk * p * n / m1 )) +
853 refclk) / (2*refclk));
854 m = m1 * m2;
855 vco = updrate * m;
856 if (vco >= limit->vco.min && vco < limit->vco.max) {
857 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
858 absppm = (ppm > 0) ? ppm : (-ppm);
859 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
860 bestppm = 0;
861 flag = 1;
862 }
863 if (absppm < bestppm - 10) {
864 bestppm = absppm;
865 flag = 1;
866 }
867 if (flag) {
868 bestn = n;
869 bestm1 = m1;
870 bestm2 = m2;
871 bestp1 = p1;
872 bestp2 = p2;
873 flag = 0;
874 }
875 }
876 }
877 }
878 }
879 }
880 best_clock->n = bestn;
881 best_clock->m1 = bestm1;
882 best_clock->m2 = bestm2;
883 best_clock->p1 = bestp1;
884 best_clock->p2 = bestp2;
885
886 return true;
887 }
888
889 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
890 enum pipe pipe)
891 {
892 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
894
895 return intel_crtc->cpu_transcoder;
896 }
897
898 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
899 {
900 struct drm_i915_private *dev_priv = dev->dev_private;
901 u32 frame, frame_reg = PIPEFRAME(pipe);
902
903 frame = I915_READ(frame_reg);
904
905 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
906 DRM_DEBUG_KMS("vblank wait timed out\n");
907 }
908
909 /**
910 * intel_wait_for_vblank - wait for vblank on a given pipe
911 * @dev: drm device
912 * @pipe: pipe to wait for
913 *
914 * Wait for vblank to occur on a given pipe. Needed for various bits of
915 * mode setting code.
916 */
917 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
918 {
919 struct drm_i915_private *dev_priv = dev->dev_private;
920 int pipestat_reg = PIPESTAT(pipe);
921
922 if (INTEL_INFO(dev)->gen >= 5) {
923 ironlake_wait_for_vblank(dev, pipe);
924 return;
925 }
926
927 /* Clear existing vblank status. Note this will clear any other
928 * sticky status fields as well.
929 *
930 * This races with i915_driver_irq_handler() with the result
931 * that either function could miss a vblank event. Here it is not
932 * fatal, as we will either wait upon the next vblank interrupt or
933 * timeout. Generally speaking intel_wait_for_vblank() is only
934 * called during modeset at which time the GPU should be idle and
935 * should *not* be performing page flips and thus not waiting on
936 * vblanks...
937 * Currently, the result of us stealing a vblank from the irq
938 * handler is that a single frame will be skipped during swapbuffers.
939 */
940 I915_WRITE(pipestat_reg,
941 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
942
943 /* Wait for vblank interrupt bit to set */
944 if (wait_for(I915_READ(pipestat_reg) &
945 PIPE_VBLANK_INTERRUPT_STATUS,
946 50))
947 DRM_DEBUG_KMS("vblank wait timed out\n");
948 }
949
950 /*
951 * intel_wait_for_pipe_off - wait for pipe to turn off
952 * @dev: drm device
953 * @pipe: pipe to wait for
954 *
955 * After disabling a pipe, we can't wait for vblank in the usual way,
956 * spinning on the vblank interrupt status bit, since we won't actually
957 * see an interrupt when the pipe is disabled.
958 *
959 * On Gen4 and above:
960 * wait for the pipe register state bit to turn off
961 *
962 * Otherwise:
963 * wait for the display line value to settle (it usually
964 * ends up stopping at the start of the next frame).
965 *
966 */
967 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
968 {
969 struct drm_i915_private *dev_priv = dev->dev_private;
970 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
971 pipe);
972
973 if (INTEL_INFO(dev)->gen >= 4) {
974 int reg = PIPECONF(cpu_transcoder);
975
976 /* Wait for the Pipe State to go off */
977 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
978 100))
979 WARN(1, "pipe_off wait timed out\n");
980 } else {
981 u32 last_line, line_mask;
982 int reg = PIPEDSL(pipe);
983 unsigned long timeout = jiffies + msecs_to_jiffies(100);
984
985 if (IS_GEN2(dev))
986 line_mask = DSL_LINEMASK_GEN2;
987 else
988 line_mask = DSL_LINEMASK_GEN3;
989
990 /* Wait for the display line to settle */
991 do {
992 last_line = I915_READ(reg) & line_mask;
993 mdelay(5);
994 } while (((I915_READ(reg) & line_mask) != last_line) &&
995 time_after(timeout, jiffies));
996 if (time_after(jiffies, timeout))
997 WARN(1, "pipe_off wait timed out\n");
998 }
999 }
1000
1001 /*
1002 * ibx_digital_port_connected - is the specified port connected?
1003 * @dev_priv: i915 private structure
1004 * @port: the port to test
1005 *
1006 * Returns true if @port is connected, false otherwise.
1007 */
1008 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1009 struct intel_digital_port *port)
1010 {
1011 u32 bit;
1012
1013 if (HAS_PCH_IBX(dev_priv->dev)) {
1014 switch(port->port) {
1015 case PORT_B:
1016 bit = SDE_PORTB_HOTPLUG;
1017 break;
1018 case PORT_C:
1019 bit = SDE_PORTC_HOTPLUG;
1020 break;
1021 case PORT_D:
1022 bit = SDE_PORTD_HOTPLUG;
1023 break;
1024 default:
1025 return true;
1026 }
1027 } else {
1028 switch(port->port) {
1029 case PORT_B:
1030 bit = SDE_PORTB_HOTPLUG_CPT;
1031 break;
1032 case PORT_C:
1033 bit = SDE_PORTC_HOTPLUG_CPT;
1034 break;
1035 case PORT_D:
1036 bit = SDE_PORTD_HOTPLUG_CPT;
1037 break;
1038 default:
1039 return true;
1040 }
1041 }
1042
1043 return I915_READ(SDEISR) & bit;
1044 }
1045
1046 static const char *state_string(bool enabled)
1047 {
1048 return enabled ? "on" : "off";
1049 }
1050
1051 /* Only for pre-ILK configs */
1052 static void assert_pll(struct drm_i915_private *dev_priv,
1053 enum pipe pipe, bool state)
1054 {
1055 int reg;
1056 u32 val;
1057 bool cur_state;
1058
1059 reg = DPLL(pipe);
1060 val = I915_READ(reg);
1061 cur_state = !!(val & DPLL_VCO_ENABLE);
1062 WARN(cur_state != state,
1063 "PLL state assertion failure (expected %s, current %s)\n",
1064 state_string(state), state_string(cur_state));
1065 }
1066 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1068
1069 /* For ILK+ */
1070 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1071 struct intel_pch_pll *pll,
1072 struct intel_crtc *crtc,
1073 bool state)
1074 {
1075 u32 val;
1076 bool cur_state;
1077
1078 if (HAS_PCH_LPT(dev_priv->dev)) {
1079 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1080 return;
1081 }
1082
1083 if (WARN (!pll,
1084 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1085 return;
1086
1087 val = I915_READ(pll->pll_reg);
1088 cur_state = !!(val & DPLL_VCO_ENABLE);
1089 WARN(cur_state != state,
1090 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1091 pll->pll_reg, state_string(state), state_string(cur_state), val);
1092
1093 /* Make sure the selected PLL is correctly attached to the transcoder */
1094 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1095 u32 pch_dpll;
1096
1097 pch_dpll = I915_READ(PCH_DPLL_SEL);
1098 cur_state = pll->pll_reg == _PCH_DPLL_B;
1099 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1100 "PLL[%d] not attached to this transcoder %d: %08x\n",
1101 cur_state, crtc->pipe, pch_dpll)) {
1102 cur_state = !!(val >> (4*crtc->pipe + 3));
1103 WARN(cur_state != state,
1104 "PLL[%d] not %s on this transcoder %d: %08x\n",
1105 pll->pll_reg == _PCH_DPLL_B,
1106 state_string(state),
1107 crtc->pipe,
1108 val);
1109 }
1110 }
1111 }
1112 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1113 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1114
1115 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1117 {
1118 int reg;
1119 u32 val;
1120 bool cur_state;
1121 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122 pipe);
1123
1124 if (HAS_DDI(dev_priv->dev)) {
1125 /* DDI does not have a specific FDI_TX register */
1126 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1129 } else {
1130 reg = FDI_TX_CTL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & FDI_TX_ENABLE);
1133 }
1134 WARN(cur_state != state,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state), state_string(cur_state));
1137 }
1138 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1140
1141 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1143 {
1144 int reg;
1145 u32 val;
1146 bool cur_state;
1147
1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_ENABLE);
1151 WARN(cur_state != state,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154 }
1155 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1157
1158 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1159 enum pipe pipe)
1160 {
1161 int reg;
1162 u32 val;
1163
1164 /* ILK FDI PLL is always enabled */
1165 if (dev_priv->info->gen == 5)
1166 return;
1167
1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1169 if (HAS_DDI(dev_priv->dev))
1170 return;
1171
1172 reg = FDI_TX_CTL(pipe);
1173 val = I915_READ(reg);
1174 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1178 enum pipe pipe)
1179 {
1180 int reg;
1181 u32 val;
1182
1183 reg = FDI_RX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1186 }
1187
1188 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190 {
1191 int pp_reg, lvds_reg;
1192 u32 val;
1193 enum pipe panel_pipe = PIPE_A;
1194 bool locked = true;
1195
1196 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1197 pp_reg = PCH_PP_CONTROL;
1198 lvds_reg = PCH_LVDS;
1199 } else {
1200 pp_reg = PP_CONTROL;
1201 lvds_reg = LVDS;
1202 }
1203
1204 val = I915_READ(pp_reg);
1205 if (!(val & PANEL_POWER_ON) ||
1206 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1207 locked = false;
1208
1209 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1211
1212 WARN(panel_pipe == pipe && locked,
1213 "panel assertion failure, pipe %c regs locked\n",
1214 pipe_name(pipe));
1215 }
1216
1217 void assert_pipe(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
1219 {
1220 int reg;
1221 u32 val;
1222 bool cur_state;
1223 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1224 pipe);
1225
1226 /* if we need the pipe A quirk it must be always on */
1227 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1228 state = true;
1229
1230 if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1231 !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1232 cur_state = false;
1233 } else {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 }
1238
1239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
1241 pipe_name(pipe), state_string(state), state_string(cur_state));
1242 }
1243
1244 static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
1246 {
1247 int reg;
1248 u32 val;
1249 bool cur_state;
1250
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
1253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
1257 }
1258
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
1262 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264 {
1265 int reg, i;
1266 u32 val;
1267 int cur_pipe;
1268
1269 /* Planes are fixed to pipes on ILK+ */
1270 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1271 reg = DSPCNTR(pipe);
1272 val = I915_READ(reg);
1273 WARN((val & DISPLAY_PLANE_ENABLE),
1274 "plane %c assertion failure, should be disabled but not\n",
1275 plane_name(pipe));
1276 return;
1277 }
1278
1279 /* Need to check both planes against the pipe */
1280 for (i = 0; i < 2; i++) {
1281 reg = DSPCNTR(i);
1282 val = I915_READ(reg);
1283 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1284 DISPPLANE_SEL_PIPE_SHIFT;
1285 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1286 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1287 plane_name(i), pipe_name(pipe));
1288 }
1289 }
1290
1291 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1292 {
1293 u32 val;
1294 bool enabled;
1295
1296 if (HAS_PCH_LPT(dev_priv->dev)) {
1297 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1298 return;
1299 }
1300
1301 val = I915_READ(PCH_DREF_CONTROL);
1302 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1303 DREF_SUPERSPREAD_SOURCE_MASK));
1304 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1305 }
1306
1307 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1308 enum pipe pipe)
1309 {
1310 int reg;
1311 u32 val;
1312 bool enabled;
1313
1314 reg = TRANSCONF(pipe);
1315 val = I915_READ(reg);
1316 enabled = !!(val & TRANS_ENABLE);
1317 WARN(enabled,
1318 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1319 pipe_name(pipe));
1320 }
1321
1322 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1323 enum pipe pipe, u32 port_sel, u32 val)
1324 {
1325 if ((val & DP_PORT_EN) == 0)
1326 return false;
1327
1328 if (HAS_PCH_CPT(dev_priv->dev)) {
1329 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1330 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1331 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1332 return false;
1333 } else {
1334 if ((val & DP_PIPE_MASK) != (pipe << 30))
1335 return false;
1336 }
1337 return true;
1338 }
1339
1340 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342 {
1343 if ((val & SDVO_ENABLE) == 0)
1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1348 return false;
1349 } else {
1350 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1351 return false;
1352 }
1353 return true;
1354 }
1355
1356 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358 {
1359 if ((val & LVDS_PORT_EN) == 0)
1360 return false;
1361
1362 if (HAS_PCH_CPT(dev_priv->dev)) {
1363 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1364 return false;
1365 } else {
1366 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1367 return false;
1368 }
1369 return true;
1370 }
1371
1372 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe, u32 val)
1374 {
1375 if ((val & ADPA_DAC_ENABLE) == 0)
1376 return false;
1377 if (HAS_PCH_CPT(dev_priv->dev)) {
1378 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1379 return false;
1380 } else {
1381 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1382 return false;
1383 }
1384 return true;
1385 }
1386
1387 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1388 enum pipe pipe, int reg, u32 port_sel)
1389 {
1390 u32 val = I915_READ(reg);
1391 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1392 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1393 reg, pipe_name(pipe));
1394
1395 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1396 && (val & DP_PIPEB_SELECT),
1397 "IBX PCH dp port still using transcoder B\n");
1398 }
1399
1400 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1401 enum pipe pipe, int reg)
1402 {
1403 u32 val = I915_READ(reg);
1404 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1405 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1406 reg, pipe_name(pipe));
1407
1408 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1409 && (val & SDVO_PIPE_B_SELECT),
1410 "IBX PCH hdmi port still using transcoder B\n");
1411 }
1412
1413 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1414 enum pipe pipe)
1415 {
1416 int reg;
1417 u32 val;
1418
1419 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1420 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1421 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1422
1423 reg = PCH_ADPA;
1424 val = I915_READ(reg);
1425 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1426 "PCH VGA enabled on transcoder %c, should be disabled\n",
1427 pipe_name(pipe));
1428
1429 reg = PCH_LVDS;
1430 val = I915_READ(reg);
1431 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1432 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1433 pipe_name(pipe));
1434
1435 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1436 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1437 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1438 }
1439
1440 /**
1441 * intel_enable_pll - enable a PLL
1442 * @dev_priv: i915 private structure
1443 * @pipe: pipe PLL to enable
1444 *
1445 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1446 * make sure the PLL reg is writable first though, since the panel write
1447 * protect mechanism may be enabled.
1448 *
1449 * Note! This is for pre-ILK only.
1450 *
1451 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1452 */
1453 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1454 {
1455 int reg;
1456 u32 val;
1457
1458 /* No really, not for ILK+ */
1459 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1460
1461 /* PLL is protected by panel, make sure we can write it */
1462 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1463 assert_panel_unlocked(dev_priv, pipe);
1464
1465 reg = DPLL(pipe);
1466 val = I915_READ(reg);
1467 val |= DPLL_VCO_ENABLE;
1468
1469 /* We do this three times for luck */
1470 I915_WRITE(reg, val);
1471 POSTING_READ(reg);
1472 udelay(150); /* wait for warmup */
1473 I915_WRITE(reg, val);
1474 POSTING_READ(reg);
1475 udelay(150); /* wait for warmup */
1476 I915_WRITE(reg, val);
1477 POSTING_READ(reg);
1478 udelay(150); /* wait for warmup */
1479 }
1480
1481 /**
1482 * intel_disable_pll - disable a PLL
1483 * @dev_priv: i915 private structure
1484 * @pipe: pipe PLL to disable
1485 *
1486 * Disable the PLL for @pipe, making sure the pipe is off first.
1487 *
1488 * Note! This is for pre-ILK only.
1489 */
1490 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1491 {
1492 int reg;
1493 u32 val;
1494
1495 /* Don't disable pipe A or pipe A PLLs if needed */
1496 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1497 return;
1498
1499 /* Make sure the pipe isn't still relying on us */
1500 assert_pipe_disabled(dev_priv, pipe);
1501
1502 reg = DPLL(pipe);
1503 val = I915_READ(reg);
1504 val &= ~DPLL_VCO_ENABLE;
1505 I915_WRITE(reg, val);
1506 POSTING_READ(reg);
1507 }
1508
1509 /* SBI access */
1510 static void
1511 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1512 enum intel_sbi_destination destination)
1513 {
1514 u32 tmp;
1515
1516 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1517
1518 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1519 100)) {
1520 DRM_ERROR("timeout waiting for SBI to become ready\n");
1521 return;
1522 }
1523
1524 I915_WRITE(SBI_ADDR, (reg << 16));
1525 I915_WRITE(SBI_DATA, value);
1526
1527 if (destination == SBI_ICLK)
1528 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1529 else
1530 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1531 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1532
1533 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1534 100)) {
1535 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1536 return;
1537 }
1538 }
1539
1540 static u32
1541 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1542 enum intel_sbi_destination destination)
1543 {
1544 u32 value = 0;
1545 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1546
1547 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1548 100)) {
1549 DRM_ERROR("timeout waiting for SBI to become ready\n");
1550 return 0;
1551 }
1552
1553 I915_WRITE(SBI_ADDR, (reg << 16));
1554
1555 if (destination == SBI_ICLK)
1556 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1557 else
1558 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1559 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1560
1561 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1562 100)) {
1563 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1564 return 0;
1565 }
1566
1567 return I915_READ(SBI_DATA);
1568 }
1569
1570 /**
1571 * ironlake_enable_pch_pll - enable PCH PLL
1572 * @dev_priv: i915 private structure
1573 * @pipe: pipe PLL to enable
1574 *
1575 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1576 * drives the transcoder clock.
1577 */
1578 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1579 {
1580 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1581 struct intel_pch_pll *pll;
1582 int reg;
1583 u32 val;
1584
1585 /* PCH PLLs only available on ILK, SNB and IVB */
1586 BUG_ON(dev_priv->info->gen < 5);
1587 pll = intel_crtc->pch_pll;
1588 if (pll == NULL)
1589 return;
1590
1591 if (WARN_ON(pll->refcount == 0))
1592 return;
1593
1594 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1595 pll->pll_reg, pll->active, pll->on,
1596 intel_crtc->base.base.id);
1597
1598 /* PCH refclock must be enabled first */
1599 assert_pch_refclk_enabled(dev_priv);
1600
1601 if (pll->active++ && pll->on) {
1602 assert_pch_pll_enabled(dev_priv, pll, NULL);
1603 return;
1604 }
1605
1606 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1607
1608 reg = pll->pll_reg;
1609 val = I915_READ(reg);
1610 val |= DPLL_VCO_ENABLE;
1611 I915_WRITE(reg, val);
1612 POSTING_READ(reg);
1613 udelay(200);
1614
1615 pll->on = true;
1616 }
1617
1618 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1619 {
1620 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1621 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1622 int reg;
1623 u32 val;
1624
1625 /* PCH only available on ILK+ */
1626 BUG_ON(dev_priv->info->gen < 5);
1627 if (pll == NULL)
1628 return;
1629
1630 if (WARN_ON(pll->refcount == 0))
1631 return;
1632
1633 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1634 pll->pll_reg, pll->active, pll->on,
1635 intel_crtc->base.base.id);
1636
1637 if (WARN_ON(pll->active == 0)) {
1638 assert_pch_pll_disabled(dev_priv, pll, NULL);
1639 return;
1640 }
1641
1642 if (--pll->active) {
1643 assert_pch_pll_enabled(dev_priv, pll, NULL);
1644 return;
1645 }
1646
1647 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1648
1649 /* Make sure transcoder isn't still depending on us */
1650 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1651
1652 reg = pll->pll_reg;
1653 val = I915_READ(reg);
1654 val &= ~DPLL_VCO_ENABLE;
1655 I915_WRITE(reg, val);
1656 POSTING_READ(reg);
1657 udelay(200);
1658
1659 pll->on = false;
1660 }
1661
1662 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1663 enum pipe pipe)
1664 {
1665 struct drm_device *dev = dev_priv->dev;
1666 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1667 uint32_t reg, val, pipeconf_val;
1668
1669 /* PCH only available on ILK+ */
1670 BUG_ON(dev_priv->info->gen < 5);
1671
1672 /* Make sure PCH DPLL is enabled */
1673 assert_pch_pll_enabled(dev_priv,
1674 to_intel_crtc(crtc)->pch_pll,
1675 to_intel_crtc(crtc));
1676
1677 /* FDI must be feeding us bits for PCH ports */
1678 assert_fdi_tx_enabled(dev_priv, pipe);
1679 assert_fdi_rx_enabled(dev_priv, pipe);
1680
1681 if (HAS_PCH_CPT(dev)) {
1682 /* Workaround: Set the timing override bit before enabling the
1683 * pch transcoder. */
1684 reg = TRANS_CHICKEN2(pipe);
1685 val = I915_READ(reg);
1686 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687 I915_WRITE(reg, val);
1688 }
1689
1690 reg = TRANSCONF(pipe);
1691 val = I915_READ(reg);
1692 pipeconf_val = I915_READ(PIPECONF(pipe));
1693
1694 if (HAS_PCH_IBX(dev_priv->dev)) {
1695 /*
1696 * make the BPC in transcoder be consistent with
1697 * that in pipeconf reg.
1698 */
1699 val &= ~PIPECONF_BPC_MASK;
1700 val |= pipeconf_val & PIPECONF_BPC_MASK;
1701 }
1702
1703 val &= ~TRANS_INTERLACE_MASK;
1704 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1705 if (HAS_PCH_IBX(dev_priv->dev) &&
1706 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1707 val |= TRANS_LEGACY_INTERLACED_ILK;
1708 else
1709 val |= TRANS_INTERLACED;
1710 else
1711 val |= TRANS_PROGRESSIVE;
1712
1713 I915_WRITE(reg, val | TRANS_ENABLE);
1714 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1715 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1716 }
1717
1718 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1719 enum transcoder cpu_transcoder)
1720 {
1721 u32 val, pipeconf_val;
1722
1723 /* PCH only available on ILK+ */
1724 BUG_ON(dev_priv->info->gen < 5);
1725
1726 /* FDI must be feeding us bits for PCH ports */
1727 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1728 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1729
1730 /* Workaround: set timing override bit. */
1731 val = I915_READ(_TRANSA_CHICKEN2);
1732 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1733 I915_WRITE(_TRANSA_CHICKEN2, val);
1734
1735 val = TRANS_ENABLE;
1736 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1737
1738 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1739 PIPECONF_INTERLACED_ILK)
1740 val |= TRANS_INTERLACED;
1741 else
1742 val |= TRANS_PROGRESSIVE;
1743
1744 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1745 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1746 DRM_ERROR("Failed to enable PCH transcoder\n");
1747 }
1748
1749 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1750 enum pipe pipe)
1751 {
1752 struct drm_device *dev = dev_priv->dev;
1753 uint32_t reg, val;
1754
1755 /* FDI relies on the transcoder */
1756 assert_fdi_tx_disabled(dev_priv, pipe);
1757 assert_fdi_rx_disabled(dev_priv, pipe);
1758
1759 /* Ports must be off as well */
1760 assert_pch_ports_disabled(dev_priv, pipe);
1761
1762 reg = TRANSCONF(pipe);
1763 val = I915_READ(reg);
1764 val &= ~TRANS_ENABLE;
1765 I915_WRITE(reg, val);
1766 /* wait for PCH transcoder off, transcoder state */
1767 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1768 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1769
1770 if (!HAS_PCH_IBX(dev)) {
1771 /* Workaround: Clear the timing override chicken bit again. */
1772 reg = TRANS_CHICKEN2(pipe);
1773 val = I915_READ(reg);
1774 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1775 I915_WRITE(reg, val);
1776 }
1777 }
1778
1779 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1780 {
1781 u32 val;
1782
1783 val = I915_READ(_TRANSACONF);
1784 val &= ~TRANS_ENABLE;
1785 I915_WRITE(_TRANSACONF, val);
1786 /* wait for PCH transcoder off, transcoder state */
1787 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1788 DRM_ERROR("Failed to disable PCH transcoder\n");
1789
1790 /* Workaround: clear timing override bit. */
1791 val = I915_READ(_TRANSA_CHICKEN2);
1792 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1793 I915_WRITE(_TRANSA_CHICKEN2, val);
1794 }
1795
1796 /**
1797 * intel_enable_pipe - enable a pipe, asserting requirements
1798 * @dev_priv: i915 private structure
1799 * @pipe: pipe to enable
1800 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1801 *
1802 * Enable @pipe, making sure that various hardware specific requirements
1803 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1804 *
1805 * @pipe should be %PIPE_A or %PIPE_B.
1806 *
1807 * Will wait until the pipe is actually running (i.e. first vblank) before
1808 * returning.
1809 */
1810 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1811 bool pch_port)
1812 {
1813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1814 pipe);
1815 enum pipe pch_transcoder;
1816 int reg;
1817 u32 val;
1818
1819 if (HAS_PCH_LPT(dev_priv->dev))
1820 pch_transcoder = TRANSCODER_A;
1821 else
1822 pch_transcoder = pipe;
1823
1824 /*
1825 * A pipe without a PLL won't actually be able to drive bits from
1826 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1827 * need the check.
1828 */
1829 if (!HAS_PCH_SPLIT(dev_priv->dev))
1830 assert_pll_enabled(dev_priv, pipe);
1831 else {
1832 if (pch_port) {
1833 /* if driving the PCH, we need FDI enabled */
1834 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1835 assert_fdi_tx_pll_enabled(dev_priv,
1836 (enum pipe) cpu_transcoder);
1837 }
1838 /* FIXME: assert CPU port conditions for SNB+ */
1839 }
1840
1841 reg = PIPECONF(cpu_transcoder);
1842 val = I915_READ(reg);
1843 if (val & PIPECONF_ENABLE)
1844 return;
1845
1846 I915_WRITE(reg, val | PIPECONF_ENABLE);
1847 intel_wait_for_vblank(dev_priv->dev, pipe);
1848 }
1849
1850 /**
1851 * intel_disable_pipe - disable a pipe, asserting requirements
1852 * @dev_priv: i915 private structure
1853 * @pipe: pipe to disable
1854 *
1855 * Disable @pipe, making sure that various hardware specific requirements
1856 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1857 *
1858 * @pipe should be %PIPE_A or %PIPE_B.
1859 *
1860 * Will wait until the pipe has shut down before returning.
1861 */
1862 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1863 enum pipe pipe)
1864 {
1865 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1866 pipe);
1867 int reg;
1868 u32 val;
1869
1870 /*
1871 * Make sure planes won't keep trying to pump pixels to us,
1872 * or we might hang the display.
1873 */
1874 assert_planes_disabled(dev_priv, pipe);
1875
1876 /* Don't disable pipe A or pipe A PLLs if needed */
1877 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1878 return;
1879
1880 reg = PIPECONF(cpu_transcoder);
1881 val = I915_READ(reg);
1882 if ((val & PIPECONF_ENABLE) == 0)
1883 return;
1884
1885 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1886 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1887 }
1888
1889 /*
1890 * Plane regs are double buffered, going from enabled->disabled needs a
1891 * trigger in order to latch. The display address reg provides this.
1892 */
1893 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1894 enum plane plane)
1895 {
1896 if (dev_priv->info->gen >= 4)
1897 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1898 else
1899 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1900 }
1901
1902 /**
1903 * intel_enable_plane - enable a display plane on a given pipe
1904 * @dev_priv: i915 private structure
1905 * @plane: plane to enable
1906 * @pipe: pipe being fed
1907 *
1908 * Enable @plane on @pipe, making sure that @pipe is running first.
1909 */
1910 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1911 enum plane plane, enum pipe pipe)
1912 {
1913 int reg;
1914 u32 val;
1915
1916 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1917 assert_pipe_enabled(dev_priv, pipe);
1918
1919 reg = DSPCNTR(plane);
1920 val = I915_READ(reg);
1921 if (val & DISPLAY_PLANE_ENABLE)
1922 return;
1923
1924 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1925 intel_flush_display_plane(dev_priv, plane);
1926 intel_wait_for_vblank(dev_priv->dev, pipe);
1927 }
1928
1929 /**
1930 * intel_disable_plane - disable a display plane
1931 * @dev_priv: i915 private structure
1932 * @plane: plane to disable
1933 * @pipe: pipe consuming the data
1934 *
1935 * Disable @plane; should be an independent operation.
1936 */
1937 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1938 enum plane plane, enum pipe pipe)
1939 {
1940 int reg;
1941 u32 val;
1942
1943 reg = DSPCNTR(plane);
1944 val = I915_READ(reg);
1945 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1946 return;
1947
1948 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1949 intel_flush_display_plane(dev_priv, plane);
1950 intel_wait_for_vblank(dev_priv->dev, pipe);
1951 }
1952
1953 static bool need_vtd_wa(struct drm_device *dev)
1954 {
1955 #ifdef CONFIG_INTEL_IOMMU
1956 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1957 return true;
1958 #endif
1959 return false;
1960 }
1961
1962 int
1963 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1964 struct drm_i915_gem_object *obj,
1965 struct intel_ring_buffer *pipelined)
1966 {
1967 struct drm_i915_private *dev_priv = dev->dev_private;
1968 u32 alignment;
1969 int ret;
1970
1971 switch (obj->tiling_mode) {
1972 case I915_TILING_NONE:
1973 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1974 alignment = 128 * 1024;
1975 else if (INTEL_INFO(dev)->gen >= 4)
1976 alignment = 4 * 1024;
1977 else
1978 alignment = 64 * 1024;
1979 break;
1980 case I915_TILING_X:
1981 /* pin() will align the object as required by fence */
1982 alignment = 0;
1983 break;
1984 case I915_TILING_Y:
1985 /* FIXME: Is this true? */
1986 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1987 return -EINVAL;
1988 default:
1989 BUG();
1990 }
1991
1992 /* Note that the w/a also requires 64 PTE of padding following the
1993 * bo. We currently fill all unused PTE with the shadow page and so
1994 * we should always have valid PTE following the scanout preventing
1995 * the VT-d warning.
1996 */
1997 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1998 alignment = 256 * 1024;
1999
2000 dev_priv->mm.interruptible = false;
2001 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2002 if (ret)
2003 goto err_interruptible;
2004
2005 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2006 * fence, whereas 965+ only requires a fence if using
2007 * framebuffer compression. For simplicity, we always install
2008 * a fence as the cost is not that onerous.
2009 */
2010 ret = i915_gem_object_get_fence(obj);
2011 if (ret)
2012 goto err_unpin;
2013
2014 i915_gem_object_pin_fence(obj);
2015
2016 dev_priv->mm.interruptible = true;
2017 return 0;
2018
2019 err_unpin:
2020 i915_gem_object_unpin(obj);
2021 err_interruptible:
2022 dev_priv->mm.interruptible = true;
2023 return ret;
2024 }
2025
2026 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2027 {
2028 i915_gem_object_unpin_fence(obj);
2029 i915_gem_object_unpin(obj);
2030 }
2031
2032 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2033 * is assumed to be a power-of-two. */
2034 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2035 unsigned int tiling_mode,
2036 unsigned int cpp,
2037 unsigned int pitch)
2038 {
2039 if (tiling_mode != I915_TILING_NONE) {
2040 unsigned int tile_rows, tiles;
2041
2042 tile_rows = *y / 8;
2043 *y %= 8;
2044
2045 tiles = *x / (512/cpp);
2046 *x %= 512/cpp;
2047
2048 return tile_rows * pitch * 8 + tiles * 4096;
2049 } else {
2050 unsigned int offset;
2051
2052 offset = *y * pitch + *x * cpp;
2053 *y = 0;
2054 *x = (offset & 4095) / cpp;
2055 return offset & -4096;
2056 }
2057 }
2058
2059 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2060 int x, int y)
2061 {
2062 struct drm_device *dev = crtc->dev;
2063 struct drm_i915_private *dev_priv = dev->dev_private;
2064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2065 struct intel_framebuffer *intel_fb;
2066 struct drm_i915_gem_object *obj;
2067 int plane = intel_crtc->plane;
2068 unsigned long linear_offset;
2069 u32 dspcntr;
2070 u32 reg;
2071
2072 switch (plane) {
2073 case 0:
2074 case 1:
2075 break;
2076 default:
2077 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2078 return -EINVAL;
2079 }
2080
2081 intel_fb = to_intel_framebuffer(fb);
2082 obj = intel_fb->obj;
2083
2084 reg = DSPCNTR(plane);
2085 dspcntr = I915_READ(reg);
2086 /* Mask out pixel format bits in case we change it */
2087 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2088 switch (fb->pixel_format) {
2089 case DRM_FORMAT_C8:
2090 dspcntr |= DISPPLANE_8BPP;
2091 break;
2092 case DRM_FORMAT_XRGB1555:
2093 case DRM_FORMAT_ARGB1555:
2094 dspcntr |= DISPPLANE_BGRX555;
2095 break;
2096 case DRM_FORMAT_RGB565:
2097 dspcntr |= DISPPLANE_BGRX565;
2098 break;
2099 case DRM_FORMAT_XRGB8888:
2100 case DRM_FORMAT_ARGB8888:
2101 dspcntr |= DISPPLANE_BGRX888;
2102 break;
2103 case DRM_FORMAT_XBGR8888:
2104 case DRM_FORMAT_ABGR8888:
2105 dspcntr |= DISPPLANE_RGBX888;
2106 break;
2107 case DRM_FORMAT_XRGB2101010:
2108 case DRM_FORMAT_ARGB2101010:
2109 dspcntr |= DISPPLANE_BGRX101010;
2110 break;
2111 case DRM_FORMAT_XBGR2101010:
2112 case DRM_FORMAT_ABGR2101010:
2113 dspcntr |= DISPPLANE_RGBX101010;
2114 break;
2115 default:
2116 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2117 return -EINVAL;
2118 }
2119
2120 if (INTEL_INFO(dev)->gen >= 4) {
2121 if (obj->tiling_mode != I915_TILING_NONE)
2122 dspcntr |= DISPPLANE_TILED;
2123 else
2124 dspcntr &= ~DISPPLANE_TILED;
2125 }
2126
2127 I915_WRITE(reg, dspcntr);
2128
2129 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2130
2131 if (INTEL_INFO(dev)->gen >= 4) {
2132 intel_crtc->dspaddr_offset =
2133 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2134 fb->bits_per_pixel / 8,
2135 fb->pitches[0]);
2136 linear_offset -= intel_crtc->dspaddr_offset;
2137 } else {
2138 intel_crtc->dspaddr_offset = linear_offset;
2139 }
2140
2141 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2142 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2143 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2144 if (INTEL_INFO(dev)->gen >= 4) {
2145 I915_MODIFY_DISPBASE(DSPSURF(plane),
2146 obj->gtt_offset + intel_crtc->dspaddr_offset);
2147 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2148 I915_WRITE(DSPLINOFF(plane), linear_offset);
2149 } else
2150 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2151 POSTING_READ(reg);
2152
2153 return 0;
2154 }
2155
2156 static int ironlake_update_plane(struct drm_crtc *crtc,
2157 struct drm_framebuffer *fb, int x, int y)
2158 {
2159 struct drm_device *dev = crtc->dev;
2160 struct drm_i915_private *dev_priv = dev->dev_private;
2161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2162 struct intel_framebuffer *intel_fb;
2163 struct drm_i915_gem_object *obj;
2164 int plane = intel_crtc->plane;
2165 unsigned long linear_offset;
2166 u32 dspcntr;
2167 u32 reg;
2168
2169 switch (plane) {
2170 case 0:
2171 case 1:
2172 case 2:
2173 break;
2174 default:
2175 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2176 return -EINVAL;
2177 }
2178
2179 intel_fb = to_intel_framebuffer(fb);
2180 obj = intel_fb->obj;
2181
2182 reg = DSPCNTR(plane);
2183 dspcntr = I915_READ(reg);
2184 /* Mask out pixel format bits in case we change it */
2185 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2186 switch (fb->pixel_format) {
2187 case DRM_FORMAT_C8:
2188 dspcntr |= DISPPLANE_8BPP;
2189 break;
2190 case DRM_FORMAT_RGB565:
2191 dspcntr |= DISPPLANE_BGRX565;
2192 break;
2193 case DRM_FORMAT_XRGB8888:
2194 case DRM_FORMAT_ARGB8888:
2195 dspcntr |= DISPPLANE_BGRX888;
2196 break;
2197 case DRM_FORMAT_XBGR8888:
2198 case DRM_FORMAT_ABGR8888:
2199 dspcntr |= DISPPLANE_RGBX888;
2200 break;
2201 case DRM_FORMAT_XRGB2101010:
2202 case DRM_FORMAT_ARGB2101010:
2203 dspcntr |= DISPPLANE_BGRX101010;
2204 break;
2205 case DRM_FORMAT_XBGR2101010:
2206 case DRM_FORMAT_ABGR2101010:
2207 dspcntr |= DISPPLANE_RGBX101010;
2208 break;
2209 default:
2210 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2211 return -EINVAL;
2212 }
2213
2214 if (obj->tiling_mode != I915_TILING_NONE)
2215 dspcntr |= DISPPLANE_TILED;
2216 else
2217 dspcntr &= ~DISPPLANE_TILED;
2218
2219 /* must disable */
2220 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2221
2222 I915_WRITE(reg, dspcntr);
2223
2224 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2225 intel_crtc->dspaddr_offset =
2226 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2227 fb->bits_per_pixel / 8,
2228 fb->pitches[0]);
2229 linear_offset -= intel_crtc->dspaddr_offset;
2230
2231 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2232 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2233 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2234 I915_MODIFY_DISPBASE(DSPSURF(plane),
2235 obj->gtt_offset + intel_crtc->dspaddr_offset);
2236 if (IS_HASWELL(dev)) {
2237 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2238 } else {
2239 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2240 I915_WRITE(DSPLINOFF(plane), linear_offset);
2241 }
2242 POSTING_READ(reg);
2243
2244 return 0;
2245 }
2246
2247 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2248 static int
2249 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2250 int x, int y, enum mode_set_atomic state)
2251 {
2252 struct drm_device *dev = crtc->dev;
2253 struct drm_i915_private *dev_priv = dev->dev_private;
2254
2255 if (dev_priv->display.disable_fbc)
2256 dev_priv->display.disable_fbc(dev);
2257 intel_increase_pllclock(crtc);
2258
2259 return dev_priv->display.update_plane(crtc, fb, x, y);
2260 }
2261
2262 void intel_display_handle_reset(struct drm_device *dev)
2263 {
2264 struct drm_i915_private *dev_priv = dev->dev_private;
2265 struct drm_crtc *crtc;
2266
2267 /*
2268 * Flips in the rings have been nuked by the reset,
2269 * so complete all pending flips so that user space
2270 * will get its events and not get stuck.
2271 *
2272 * Also update the base address of all primary
2273 * planes to the the last fb to make sure we're
2274 * showing the correct fb after a reset.
2275 *
2276 * Need to make two loops over the crtcs so that we
2277 * don't try to grab a crtc mutex before the
2278 * pending_flip_queue really got woken up.
2279 */
2280
2281 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2282 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2283 enum plane plane = intel_crtc->plane;
2284
2285 intel_prepare_page_flip(dev, plane);
2286 intel_finish_page_flip_plane(dev, plane);
2287 }
2288
2289 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2291
2292 mutex_lock(&crtc->mutex);
2293 if (intel_crtc->active)
2294 dev_priv->display.update_plane(crtc, crtc->fb,
2295 crtc->x, crtc->y);
2296 mutex_unlock(&crtc->mutex);
2297 }
2298 }
2299
2300 static int
2301 intel_finish_fb(struct drm_framebuffer *old_fb)
2302 {
2303 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2304 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2305 bool was_interruptible = dev_priv->mm.interruptible;
2306 int ret;
2307
2308 /* Big Hammer, we also need to ensure that any pending
2309 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2310 * current scanout is retired before unpinning the old
2311 * framebuffer.
2312 *
2313 * This should only fail upon a hung GPU, in which case we
2314 * can safely continue.
2315 */
2316 dev_priv->mm.interruptible = false;
2317 ret = i915_gem_object_finish_gpu(obj);
2318 dev_priv->mm.interruptible = was_interruptible;
2319
2320 return ret;
2321 }
2322
2323 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2324 {
2325 struct drm_device *dev = crtc->dev;
2326 struct drm_i915_master_private *master_priv;
2327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2328
2329 if (!dev->primary->master)
2330 return;
2331
2332 master_priv = dev->primary->master->driver_priv;
2333 if (!master_priv->sarea_priv)
2334 return;
2335
2336 switch (intel_crtc->pipe) {
2337 case 0:
2338 master_priv->sarea_priv->pipeA_x = x;
2339 master_priv->sarea_priv->pipeA_y = y;
2340 break;
2341 case 1:
2342 master_priv->sarea_priv->pipeB_x = x;
2343 master_priv->sarea_priv->pipeB_y = y;
2344 break;
2345 default:
2346 break;
2347 }
2348 }
2349
2350 static int
2351 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2352 struct drm_framebuffer *fb)
2353 {
2354 struct drm_device *dev = crtc->dev;
2355 struct drm_i915_private *dev_priv = dev->dev_private;
2356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2357 struct drm_framebuffer *old_fb;
2358 int ret;
2359
2360 /* no fb bound */
2361 if (!fb) {
2362 DRM_ERROR("No FB bound\n");
2363 return 0;
2364 }
2365
2366 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2367 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2368 intel_crtc->plane,
2369 INTEL_INFO(dev)->num_pipes);
2370 return -EINVAL;
2371 }
2372
2373 mutex_lock(&dev->struct_mutex);
2374 ret = intel_pin_and_fence_fb_obj(dev,
2375 to_intel_framebuffer(fb)->obj,
2376 NULL);
2377 if (ret != 0) {
2378 mutex_unlock(&dev->struct_mutex);
2379 DRM_ERROR("pin & fence failed\n");
2380 return ret;
2381 }
2382
2383 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2384 if (ret) {
2385 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2386 mutex_unlock(&dev->struct_mutex);
2387 DRM_ERROR("failed to update base address\n");
2388 return ret;
2389 }
2390
2391 old_fb = crtc->fb;
2392 crtc->fb = fb;
2393 crtc->x = x;
2394 crtc->y = y;
2395
2396 if (old_fb) {
2397 intel_wait_for_vblank(dev, intel_crtc->pipe);
2398 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2399 }
2400
2401 intel_update_fbc(dev);
2402 mutex_unlock(&dev->struct_mutex);
2403
2404 intel_crtc_update_sarea_pos(crtc, x, y);
2405
2406 return 0;
2407 }
2408
2409 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2410 {
2411 struct drm_device *dev = crtc->dev;
2412 struct drm_i915_private *dev_priv = dev->dev_private;
2413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2414 int pipe = intel_crtc->pipe;
2415 u32 reg, temp;
2416
2417 /* enable normal train */
2418 reg = FDI_TX_CTL(pipe);
2419 temp = I915_READ(reg);
2420 if (IS_IVYBRIDGE(dev)) {
2421 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2422 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2423 } else {
2424 temp &= ~FDI_LINK_TRAIN_NONE;
2425 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2426 }
2427 I915_WRITE(reg, temp);
2428
2429 reg = FDI_RX_CTL(pipe);
2430 temp = I915_READ(reg);
2431 if (HAS_PCH_CPT(dev)) {
2432 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2433 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2434 } else {
2435 temp &= ~FDI_LINK_TRAIN_NONE;
2436 temp |= FDI_LINK_TRAIN_NONE;
2437 }
2438 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2439
2440 /* wait one idle pattern time */
2441 POSTING_READ(reg);
2442 udelay(1000);
2443
2444 /* IVB wants error correction enabled */
2445 if (IS_IVYBRIDGE(dev))
2446 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2447 FDI_FE_ERRC_ENABLE);
2448 }
2449
2450 static void ivb_modeset_global_resources(struct drm_device *dev)
2451 {
2452 struct drm_i915_private *dev_priv = dev->dev_private;
2453 struct intel_crtc *pipe_B_crtc =
2454 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2455 struct intel_crtc *pipe_C_crtc =
2456 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2457 uint32_t temp;
2458
2459 /* When everything is off disable fdi C so that we could enable fdi B
2460 * with all lanes. XXX: This misses the case where a pipe is not using
2461 * any pch resources and so doesn't need any fdi lanes. */
2462 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2463 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2464 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2465
2466 temp = I915_READ(SOUTH_CHICKEN1);
2467 temp &= ~FDI_BC_BIFURCATION_SELECT;
2468 DRM_DEBUG_KMS("disabling fdi C rx\n");
2469 I915_WRITE(SOUTH_CHICKEN1, temp);
2470 }
2471 }
2472
2473 /* The FDI link training functions for ILK/Ibexpeak. */
2474 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2475 {
2476 struct drm_device *dev = crtc->dev;
2477 struct drm_i915_private *dev_priv = dev->dev_private;
2478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2479 int pipe = intel_crtc->pipe;
2480 int plane = intel_crtc->plane;
2481 u32 reg, temp, tries;
2482
2483 /* FDI needs bits from pipe & plane first */
2484 assert_pipe_enabled(dev_priv, pipe);
2485 assert_plane_enabled(dev_priv, plane);
2486
2487 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2488 for train result */
2489 reg = FDI_RX_IMR(pipe);
2490 temp = I915_READ(reg);
2491 temp &= ~FDI_RX_SYMBOL_LOCK;
2492 temp &= ~FDI_RX_BIT_LOCK;
2493 I915_WRITE(reg, temp);
2494 I915_READ(reg);
2495 udelay(150);
2496
2497 /* enable CPU FDI TX and PCH FDI RX */
2498 reg = FDI_TX_CTL(pipe);
2499 temp = I915_READ(reg);
2500 temp &= ~(7 << 19);
2501 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2502 temp &= ~FDI_LINK_TRAIN_NONE;
2503 temp |= FDI_LINK_TRAIN_PATTERN_1;
2504 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2505
2506 reg = FDI_RX_CTL(pipe);
2507 temp = I915_READ(reg);
2508 temp &= ~FDI_LINK_TRAIN_NONE;
2509 temp |= FDI_LINK_TRAIN_PATTERN_1;
2510 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2511
2512 POSTING_READ(reg);
2513 udelay(150);
2514
2515 /* Ironlake workaround, enable clock pointer after FDI enable*/
2516 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2517 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2518 FDI_RX_PHASE_SYNC_POINTER_EN);
2519
2520 reg = FDI_RX_IIR(pipe);
2521 for (tries = 0; tries < 5; tries++) {
2522 temp = I915_READ(reg);
2523 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2524
2525 if ((temp & FDI_RX_BIT_LOCK)) {
2526 DRM_DEBUG_KMS("FDI train 1 done.\n");
2527 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2528 break;
2529 }
2530 }
2531 if (tries == 5)
2532 DRM_ERROR("FDI train 1 fail!\n");
2533
2534 /* Train 2 */
2535 reg = FDI_TX_CTL(pipe);
2536 temp = I915_READ(reg);
2537 temp &= ~FDI_LINK_TRAIN_NONE;
2538 temp |= FDI_LINK_TRAIN_PATTERN_2;
2539 I915_WRITE(reg, temp);
2540
2541 reg = FDI_RX_CTL(pipe);
2542 temp = I915_READ(reg);
2543 temp &= ~FDI_LINK_TRAIN_NONE;
2544 temp |= FDI_LINK_TRAIN_PATTERN_2;
2545 I915_WRITE(reg, temp);
2546
2547 POSTING_READ(reg);
2548 udelay(150);
2549
2550 reg = FDI_RX_IIR(pipe);
2551 for (tries = 0; tries < 5; tries++) {
2552 temp = I915_READ(reg);
2553 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2554
2555 if (temp & FDI_RX_SYMBOL_LOCK) {
2556 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2557 DRM_DEBUG_KMS("FDI train 2 done.\n");
2558 break;
2559 }
2560 }
2561 if (tries == 5)
2562 DRM_ERROR("FDI train 2 fail!\n");
2563
2564 DRM_DEBUG_KMS("FDI train done\n");
2565
2566 }
2567
2568 static const int snb_b_fdi_train_param[] = {
2569 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2570 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2571 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2572 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2573 };
2574
2575 /* The FDI link training functions for SNB/Cougarpoint. */
2576 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2577 {
2578 struct drm_device *dev = crtc->dev;
2579 struct drm_i915_private *dev_priv = dev->dev_private;
2580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2581 int pipe = intel_crtc->pipe;
2582 u32 reg, temp, i, retry;
2583
2584 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2585 for train result */
2586 reg = FDI_RX_IMR(pipe);
2587 temp = I915_READ(reg);
2588 temp &= ~FDI_RX_SYMBOL_LOCK;
2589 temp &= ~FDI_RX_BIT_LOCK;
2590 I915_WRITE(reg, temp);
2591
2592 POSTING_READ(reg);
2593 udelay(150);
2594
2595 /* enable CPU FDI TX and PCH FDI RX */
2596 reg = FDI_TX_CTL(pipe);
2597 temp = I915_READ(reg);
2598 temp &= ~(7 << 19);
2599 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2600 temp &= ~FDI_LINK_TRAIN_NONE;
2601 temp |= FDI_LINK_TRAIN_PATTERN_1;
2602 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2603 /* SNB-B */
2604 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2605 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2606
2607 I915_WRITE(FDI_RX_MISC(pipe),
2608 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2609
2610 reg = FDI_RX_CTL(pipe);
2611 temp = I915_READ(reg);
2612 if (HAS_PCH_CPT(dev)) {
2613 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2614 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2615 } else {
2616 temp &= ~FDI_LINK_TRAIN_NONE;
2617 temp |= FDI_LINK_TRAIN_PATTERN_1;
2618 }
2619 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2620
2621 POSTING_READ(reg);
2622 udelay(150);
2623
2624 for (i = 0; i < 4; i++) {
2625 reg = FDI_TX_CTL(pipe);
2626 temp = I915_READ(reg);
2627 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2628 temp |= snb_b_fdi_train_param[i];
2629 I915_WRITE(reg, temp);
2630
2631 POSTING_READ(reg);
2632 udelay(500);
2633
2634 for (retry = 0; retry < 5; retry++) {
2635 reg = FDI_RX_IIR(pipe);
2636 temp = I915_READ(reg);
2637 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2638 if (temp & FDI_RX_BIT_LOCK) {
2639 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2640 DRM_DEBUG_KMS("FDI train 1 done.\n");
2641 break;
2642 }
2643 udelay(50);
2644 }
2645 if (retry < 5)
2646 break;
2647 }
2648 if (i == 4)
2649 DRM_ERROR("FDI train 1 fail!\n");
2650
2651 /* Train 2 */
2652 reg = FDI_TX_CTL(pipe);
2653 temp = I915_READ(reg);
2654 temp &= ~FDI_LINK_TRAIN_NONE;
2655 temp |= FDI_LINK_TRAIN_PATTERN_2;
2656 if (IS_GEN6(dev)) {
2657 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2658 /* SNB-B */
2659 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2660 }
2661 I915_WRITE(reg, temp);
2662
2663 reg = FDI_RX_CTL(pipe);
2664 temp = I915_READ(reg);
2665 if (HAS_PCH_CPT(dev)) {
2666 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2667 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2668 } else {
2669 temp &= ~FDI_LINK_TRAIN_NONE;
2670 temp |= FDI_LINK_TRAIN_PATTERN_2;
2671 }
2672 I915_WRITE(reg, temp);
2673
2674 POSTING_READ(reg);
2675 udelay(150);
2676
2677 for (i = 0; i < 4; i++) {
2678 reg = FDI_TX_CTL(pipe);
2679 temp = I915_READ(reg);
2680 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2681 temp |= snb_b_fdi_train_param[i];
2682 I915_WRITE(reg, temp);
2683
2684 POSTING_READ(reg);
2685 udelay(500);
2686
2687 for (retry = 0; retry < 5; retry++) {
2688 reg = FDI_RX_IIR(pipe);
2689 temp = I915_READ(reg);
2690 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2691 if (temp & FDI_RX_SYMBOL_LOCK) {
2692 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2693 DRM_DEBUG_KMS("FDI train 2 done.\n");
2694 break;
2695 }
2696 udelay(50);
2697 }
2698 if (retry < 5)
2699 break;
2700 }
2701 if (i == 4)
2702 DRM_ERROR("FDI train 2 fail!\n");
2703
2704 DRM_DEBUG_KMS("FDI train done.\n");
2705 }
2706
2707 /* Manual link training for Ivy Bridge A0 parts */
2708 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2709 {
2710 struct drm_device *dev = crtc->dev;
2711 struct drm_i915_private *dev_priv = dev->dev_private;
2712 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2713 int pipe = intel_crtc->pipe;
2714 u32 reg, temp, i;
2715
2716 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2717 for train result */
2718 reg = FDI_RX_IMR(pipe);
2719 temp = I915_READ(reg);
2720 temp &= ~FDI_RX_SYMBOL_LOCK;
2721 temp &= ~FDI_RX_BIT_LOCK;
2722 I915_WRITE(reg, temp);
2723
2724 POSTING_READ(reg);
2725 udelay(150);
2726
2727 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2728 I915_READ(FDI_RX_IIR(pipe)));
2729
2730 /* enable CPU FDI TX and PCH FDI RX */
2731 reg = FDI_TX_CTL(pipe);
2732 temp = I915_READ(reg);
2733 temp &= ~(7 << 19);
2734 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2735 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2736 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2737 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2738 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2739 temp |= FDI_COMPOSITE_SYNC;
2740 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2741
2742 I915_WRITE(FDI_RX_MISC(pipe),
2743 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2744
2745 reg = FDI_RX_CTL(pipe);
2746 temp = I915_READ(reg);
2747 temp &= ~FDI_LINK_TRAIN_AUTO;
2748 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2749 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2750 temp |= FDI_COMPOSITE_SYNC;
2751 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2752
2753 POSTING_READ(reg);
2754 udelay(150);
2755
2756 for (i = 0; i < 4; i++) {
2757 reg = FDI_TX_CTL(pipe);
2758 temp = I915_READ(reg);
2759 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2760 temp |= snb_b_fdi_train_param[i];
2761 I915_WRITE(reg, temp);
2762
2763 POSTING_READ(reg);
2764 udelay(500);
2765
2766 reg = FDI_RX_IIR(pipe);
2767 temp = I915_READ(reg);
2768 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2769
2770 if (temp & FDI_RX_BIT_LOCK ||
2771 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2772 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2773 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2774 break;
2775 }
2776 }
2777 if (i == 4)
2778 DRM_ERROR("FDI train 1 fail!\n");
2779
2780 /* Train 2 */
2781 reg = FDI_TX_CTL(pipe);
2782 temp = I915_READ(reg);
2783 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2784 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2785 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2786 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2787 I915_WRITE(reg, temp);
2788
2789 reg = FDI_RX_CTL(pipe);
2790 temp = I915_READ(reg);
2791 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2792 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2793 I915_WRITE(reg, temp);
2794
2795 POSTING_READ(reg);
2796 udelay(150);
2797
2798 for (i = 0; i < 4; i++) {
2799 reg = FDI_TX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2802 temp |= snb_b_fdi_train_param[i];
2803 I915_WRITE(reg, temp);
2804
2805 POSTING_READ(reg);
2806 udelay(500);
2807
2808 reg = FDI_RX_IIR(pipe);
2809 temp = I915_READ(reg);
2810 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2811
2812 if (temp & FDI_RX_SYMBOL_LOCK) {
2813 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2814 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2815 break;
2816 }
2817 }
2818 if (i == 4)
2819 DRM_ERROR("FDI train 2 fail!\n");
2820
2821 DRM_DEBUG_KMS("FDI train done.\n");
2822 }
2823
2824 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2825 {
2826 struct drm_device *dev = intel_crtc->base.dev;
2827 struct drm_i915_private *dev_priv = dev->dev_private;
2828 int pipe = intel_crtc->pipe;
2829 u32 reg, temp;
2830
2831
2832 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2833 reg = FDI_RX_CTL(pipe);
2834 temp = I915_READ(reg);
2835 temp &= ~((0x7 << 19) | (0x7 << 16));
2836 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2837 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2838 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2839
2840 POSTING_READ(reg);
2841 udelay(200);
2842
2843 /* Switch from Rawclk to PCDclk */
2844 temp = I915_READ(reg);
2845 I915_WRITE(reg, temp | FDI_PCDCLK);
2846
2847 POSTING_READ(reg);
2848 udelay(200);
2849
2850 /* Enable CPU FDI TX PLL, always on for Ironlake */
2851 reg = FDI_TX_CTL(pipe);
2852 temp = I915_READ(reg);
2853 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2854 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2855
2856 POSTING_READ(reg);
2857 udelay(100);
2858 }
2859 }
2860
2861 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2862 {
2863 struct drm_device *dev = intel_crtc->base.dev;
2864 struct drm_i915_private *dev_priv = dev->dev_private;
2865 int pipe = intel_crtc->pipe;
2866 u32 reg, temp;
2867
2868 /* Switch from PCDclk to Rawclk */
2869 reg = FDI_RX_CTL(pipe);
2870 temp = I915_READ(reg);
2871 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2872
2873 /* Disable CPU FDI TX PLL */
2874 reg = FDI_TX_CTL(pipe);
2875 temp = I915_READ(reg);
2876 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2877
2878 POSTING_READ(reg);
2879 udelay(100);
2880
2881 reg = FDI_RX_CTL(pipe);
2882 temp = I915_READ(reg);
2883 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2884
2885 /* Wait for the clocks to turn off. */
2886 POSTING_READ(reg);
2887 udelay(100);
2888 }
2889
2890 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2891 {
2892 struct drm_device *dev = crtc->dev;
2893 struct drm_i915_private *dev_priv = dev->dev_private;
2894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2895 int pipe = intel_crtc->pipe;
2896 u32 reg, temp;
2897
2898 /* disable CPU FDI tx and PCH FDI rx */
2899 reg = FDI_TX_CTL(pipe);
2900 temp = I915_READ(reg);
2901 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2902 POSTING_READ(reg);
2903
2904 reg = FDI_RX_CTL(pipe);
2905 temp = I915_READ(reg);
2906 temp &= ~(0x7 << 16);
2907 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2908 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2909
2910 POSTING_READ(reg);
2911 udelay(100);
2912
2913 /* Ironlake workaround, disable clock pointer after downing FDI */
2914 if (HAS_PCH_IBX(dev)) {
2915 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2916 }
2917
2918 /* still set train pattern 1 */
2919 reg = FDI_TX_CTL(pipe);
2920 temp = I915_READ(reg);
2921 temp &= ~FDI_LINK_TRAIN_NONE;
2922 temp |= FDI_LINK_TRAIN_PATTERN_1;
2923 I915_WRITE(reg, temp);
2924
2925 reg = FDI_RX_CTL(pipe);
2926 temp = I915_READ(reg);
2927 if (HAS_PCH_CPT(dev)) {
2928 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2929 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2930 } else {
2931 temp &= ~FDI_LINK_TRAIN_NONE;
2932 temp |= FDI_LINK_TRAIN_PATTERN_1;
2933 }
2934 /* BPC in FDI rx is consistent with that in PIPECONF */
2935 temp &= ~(0x07 << 16);
2936 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2937 I915_WRITE(reg, temp);
2938
2939 POSTING_READ(reg);
2940 udelay(100);
2941 }
2942
2943 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2944 {
2945 struct drm_device *dev = crtc->dev;
2946 struct drm_i915_private *dev_priv = dev->dev_private;
2947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2948 unsigned long flags;
2949 bool pending;
2950
2951 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2952 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2953 return false;
2954
2955 spin_lock_irqsave(&dev->event_lock, flags);
2956 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2957 spin_unlock_irqrestore(&dev->event_lock, flags);
2958
2959 return pending;
2960 }
2961
2962 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2963 {
2964 struct drm_device *dev = crtc->dev;
2965 struct drm_i915_private *dev_priv = dev->dev_private;
2966
2967 if (crtc->fb == NULL)
2968 return;
2969
2970 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2971
2972 wait_event(dev_priv->pending_flip_queue,
2973 !intel_crtc_has_pending_flip(crtc));
2974
2975 mutex_lock(&dev->struct_mutex);
2976 intel_finish_fb(crtc->fb);
2977 mutex_unlock(&dev->struct_mutex);
2978 }
2979
2980 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2981 {
2982 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2983 }
2984
2985 /* Program iCLKIP clock to the desired frequency */
2986 static void lpt_program_iclkip(struct drm_crtc *crtc)
2987 {
2988 struct drm_device *dev = crtc->dev;
2989 struct drm_i915_private *dev_priv = dev->dev_private;
2990 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2991 u32 temp;
2992
2993 mutex_lock(&dev_priv->dpio_lock);
2994
2995 /* It is necessary to ungate the pixclk gate prior to programming
2996 * the divisors, and gate it back when it is done.
2997 */
2998 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2999
3000 /* Disable SSCCTL */
3001 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3002 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3003 SBI_SSCCTL_DISABLE,
3004 SBI_ICLK);
3005
3006 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3007 if (crtc->mode.clock == 20000) {
3008 auxdiv = 1;
3009 divsel = 0x41;
3010 phaseinc = 0x20;
3011 } else {
3012 /* The iCLK virtual clock root frequency is in MHz,
3013 * but the crtc->mode.clock in in KHz. To get the divisors,
3014 * it is necessary to divide one by another, so we
3015 * convert the virtual clock precision to KHz here for higher
3016 * precision.
3017 */
3018 u32 iclk_virtual_root_freq = 172800 * 1000;
3019 u32 iclk_pi_range = 64;
3020 u32 desired_divisor, msb_divisor_value, pi_value;
3021
3022 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3023 msb_divisor_value = desired_divisor / iclk_pi_range;
3024 pi_value = desired_divisor % iclk_pi_range;
3025
3026 auxdiv = 0;
3027 divsel = msb_divisor_value - 2;
3028 phaseinc = pi_value;
3029 }
3030
3031 /* This should not happen with any sane values */
3032 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3033 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3034 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3035 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3036
3037 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3038 crtc->mode.clock,
3039 auxdiv,
3040 divsel,
3041 phasedir,
3042 phaseinc);
3043
3044 /* Program SSCDIVINTPHASE6 */
3045 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3046 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3047 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3048 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3049 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3050 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3051 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3052 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3053
3054 /* Program SSCAUXDIV */
3055 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3056 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3057 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3058 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3059
3060 /* Enable modulator and associated divider */
3061 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3062 temp &= ~SBI_SSCCTL_DISABLE;
3063 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3064
3065 /* Wait for initialization time */
3066 udelay(24);
3067
3068 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3069
3070 mutex_unlock(&dev_priv->dpio_lock);
3071 }
3072
3073 /*
3074 * Enable PCH resources required for PCH ports:
3075 * - PCH PLLs
3076 * - FDI training & RX/TX
3077 * - update transcoder timings
3078 * - DP transcoding bits
3079 * - transcoder
3080 */
3081 static void ironlake_pch_enable(struct drm_crtc *crtc)
3082 {
3083 struct drm_device *dev = crtc->dev;
3084 struct drm_i915_private *dev_priv = dev->dev_private;
3085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3086 int pipe = intel_crtc->pipe;
3087 u32 reg, temp;
3088
3089 assert_transcoder_disabled(dev_priv, pipe);
3090
3091 /* Write the TU size bits before fdi link training, so that error
3092 * detection works. */
3093 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3094 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3095
3096 /* For PCH output, training FDI link */
3097 dev_priv->display.fdi_link_train(crtc);
3098
3099 /* XXX: pch pll's can be enabled any time before we enable the PCH
3100 * transcoder, and we actually should do this to not upset any PCH
3101 * transcoder that already use the clock when we share it.
3102 *
3103 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3104 * unconditionally resets the pll - we need that to have the right LVDS
3105 * enable sequence. */
3106 ironlake_enable_pch_pll(intel_crtc);
3107
3108 if (HAS_PCH_CPT(dev)) {
3109 u32 sel;
3110
3111 temp = I915_READ(PCH_DPLL_SEL);
3112 switch (pipe) {
3113 default:
3114 case 0:
3115 temp |= TRANSA_DPLL_ENABLE;
3116 sel = TRANSA_DPLLB_SEL;
3117 break;
3118 case 1:
3119 temp |= TRANSB_DPLL_ENABLE;
3120 sel = TRANSB_DPLLB_SEL;
3121 break;
3122 case 2:
3123 temp |= TRANSC_DPLL_ENABLE;
3124 sel = TRANSC_DPLLB_SEL;
3125 break;
3126 }
3127 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3128 temp |= sel;
3129 else
3130 temp &= ~sel;
3131 I915_WRITE(PCH_DPLL_SEL, temp);
3132 }
3133
3134 /* set transcoder timing, panel must allow it */
3135 assert_panel_unlocked(dev_priv, pipe);
3136 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3137 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3138 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3139
3140 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3141 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3142 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3143 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3144
3145 intel_fdi_normal_train(crtc);
3146
3147 /* For PCH DP, enable TRANS_DP_CTL */
3148 if (HAS_PCH_CPT(dev) &&
3149 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3150 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3151 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3152 reg = TRANS_DP_CTL(pipe);
3153 temp = I915_READ(reg);
3154 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3155 TRANS_DP_SYNC_MASK |
3156 TRANS_DP_BPC_MASK);
3157 temp |= (TRANS_DP_OUTPUT_ENABLE |
3158 TRANS_DP_ENH_FRAMING);
3159 temp |= bpc << 9; /* same format but at 11:9 */
3160
3161 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3162 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3163 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3164 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3165
3166 switch (intel_trans_dp_port_sel(crtc)) {
3167 case PCH_DP_B:
3168 temp |= TRANS_DP_PORT_SEL_B;
3169 break;
3170 case PCH_DP_C:
3171 temp |= TRANS_DP_PORT_SEL_C;
3172 break;
3173 case PCH_DP_D:
3174 temp |= TRANS_DP_PORT_SEL_D;
3175 break;
3176 default:
3177 BUG();
3178 }
3179
3180 I915_WRITE(reg, temp);
3181 }
3182
3183 ironlake_enable_pch_transcoder(dev_priv, pipe);
3184 }
3185
3186 static void lpt_pch_enable(struct drm_crtc *crtc)
3187 {
3188 struct drm_device *dev = crtc->dev;
3189 struct drm_i915_private *dev_priv = dev->dev_private;
3190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3191 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3192
3193 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3194
3195 lpt_program_iclkip(crtc);
3196
3197 /* Set transcoder timing. */
3198 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3199 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3200 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
3201
3202 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3203 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3204 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3205 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3206
3207 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3208 }
3209
3210 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3211 {
3212 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3213
3214 if (pll == NULL)
3215 return;
3216
3217 if (pll->refcount == 0) {
3218 WARN(1, "bad PCH PLL refcount\n");
3219 return;
3220 }
3221
3222 --pll->refcount;
3223 intel_crtc->pch_pll = NULL;
3224 }
3225
3226 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3227 {
3228 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3229 struct intel_pch_pll *pll;
3230 int i;
3231
3232 pll = intel_crtc->pch_pll;
3233 if (pll) {
3234 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3235 intel_crtc->base.base.id, pll->pll_reg);
3236 goto prepare;
3237 }
3238
3239 if (HAS_PCH_IBX(dev_priv->dev)) {
3240 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3241 i = intel_crtc->pipe;
3242 pll = &dev_priv->pch_plls[i];
3243
3244 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3245 intel_crtc->base.base.id, pll->pll_reg);
3246
3247 goto found;
3248 }
3249
3250 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3251 pll = &dev_priv->pch_plls[i];
3252
3253 /* Only want to check enabled timings first */
3254 if (pll->refcount == 0)
3255 continue;
3256
3257 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3258 fp == I915_READ(pll->fp0_reg)) {
3259 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3260 intel_crtc->base.base.id,
3261 pll->pll_reg, pll->refcount, pll->active);
3262
3263 goto found;
3264 }
3265 }
3266
3267 /* Ok no matching timings, maybe there's a free one? */
3268 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3269 pll = &dev_priv->pch_plls[i];
3270 if (pll->refcount == 0) {
3271 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3272 intel_crtc->base.base.id, pll->pll_reg);
3273 goto found;
3274 }
3275 }
3276
3277 return NULL;
3278
3279 found:
3280 intel_crtc->pch_pll = pll;
3281 pll->refcount++;
3282 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3283 prepare: /* separate function? */
3284 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3285
3286 /* Wait for the clocks to stabilize before rewriting the regs */
3287 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3288 POSTING_READ(pll->pll_reg);
3289 udelay(150);
3290
3291 I915_WRITE(pll->fp0_reg, fp);
3292 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3293 pll->on = false;
3294 return pll;
3295 }
3296
3297 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3298 {
3299 struct drm_i915_private *dev_priv = dev->dev_private;
3300 int dslreg = PIPEDSL(pipe);
3301 u32 temp;
3302
3303 temp = I915_READ(dslreg);
3304 udelay(500);
3305 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3306 if (wait_for(I915_READ(dslreg) != temp, 5))
3307 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3308 }
3309 }
3310
3311 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3312 {
3313 struct drm_device *dev = crtc->dev;
3314 struct drm_i915_private *dev_priv = dev->dev_private;
3315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3316 struct intel_encoder *encoder;
3317 int pipe = intel_crtc->pipe;
3318 int plane = intel_crtc->plane;
3319 u32 temp;
3320
3321 WARN_ON(!crtc->enabled);
3322
3323 if (intel_crtc->active)
3324 return;
3325
3326 intel_crtc->active = true;
3327 intel_update_watermarks(dev);
3328
3329 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3330 temp = I915_READ(PCH_LVDS);
3331 if ((temp & LVDS_PORT_EN) == 0)
3332 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3333 }
3334
3335
3336 if (intel_crtc->config.has_pch_encoder) {
3337 /* Note: FDI PLL enabling _must_ be done before we enable the
3338 * cpu pipes, hence this is separate from all the other fdi/pch
3339 * enabling. */
3340 ironlake_fdi_pll_enable(intel_crtc);
3341 } else {
3342 assert_fdi_tx_disabled(dev_priv, pipe);
3343 assert_fdi_rx_disabled(dev_priv, pipe);
3344 }
3345
3346 for_each_encoder_on_crtc(dev, crtc, encoder)
3347 if (encoder->pre_enable)
3348 encoder->pre_enable(encoder);
3349
3350 /* Enable panel fitting for LVDS */
3351 if (dev_priv->pch_pf_size &&
3352 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3353 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3354 /* Force use of hard-coded filter coefficients
3355 * as some pre-programmed values are broken,
3356 * e.g. x201.
3357 */
3358 if (IS_IVYBRIDGE(dev))
3359 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3360 PF_PIPE_SEL_IVB(pipe));
3361 else
3362 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3363 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3364 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3365 }
3366
3367 /*
3368 * On ILK+ LUT must be loaded before the pipe is running but with
3369 * clocks enabled
3370 */
3371 intel_crtc_load_lut(crtc);
3372
3373 intel_enable_pipe(dev_priv, pipe,
3374 intel_crtc->config.has_pch_encoder);
3375 intel_enable_plane(dev_priv, plane, pipe);
3376
3377 if (intel_crtc->config.has_pch_encoder)
3378 ironlake_pch_enable(crtc);
3379
3380 mutex_lock(&dev->struct_mutex);
3381 intel_update_fbc(dev);
3382 mutex_unlock(&dev->struct_mutex);
3383
3384 intel_crtc_update_cursor(crtc, true);
3385
3386 for_each_encoder_on_crtc(dev, crtc, encoder)
3387 encoder->enable(encoder);
3388
3389 if (HAS_PCH_CPT(dev))
3390 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3391
3392 /*
3393 * There seems to be a race in PCH platform hw (at least on some
3394 * outputs) where an enabled pipe still completes any pageflip right
3395 * away (as if the pipe is off) instead of waiting for vblank. As soon
3396 * as the first vblank happend, everything works as expected. Hence just
3397 * wait for one vblank before returning to avoid strange things
3398 * happening.
3399 */
3400 intel_wait_for_vblank(dev, intel_crtc->pipe);
3401 }
3402
3403 static void haswell_crtc_enable(struct drm_crtc *crtc)
3404 {
3405 struct drm_device *dev = crtc->dev;
3406 struct drm_i915_private *dev_priv = dev->dev_private;
3407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3408 struct intel_encoder *encoder;
3409 int pipe = intel_crtc->pipe;
3410 int plane = intel_crtc->plane;
3411
3412 WARN_ON(!crtc->enabled);
3413
3414 if (intel_crtc->active)
3415 return;
3416
3417 intel_crtc->active = true;
3418 intel_update_watermarks(dev);
3419
3420 if (intel_crtc->config.has_pch_encoder)
3421 dev_priv->display.fdi_link_train(crtc);
3422
3423 for_each_encoder_on_crtc(dev, crtc, encoder)
3424 if (encoder->pre_enable)
3425 encoder->pre_enable(encoder);
3426
3427 intel_ddi_enable_pipe_clock(intel_crtc);
3428
3429 /* Enable panel fitting for eDP */
3430 if (dev_priv->pch_pf_size &&
3431 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3432 /* Force use of hard-coded filter coefficients
3433 * as some pre-programmed values are broken,
3434 * e.g. x201.
3435 */
3436 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3437 PF_PIPE_SEL_IVB(pipe));
3438 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3439 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3440 }
3441
3442 /*
3443 * On ILK+ LUT must be loaded before the pipe is running but with
3444 * clocks enabled
3445 */
3446 intel_crtc_load_lut(crtc);
3447
3448 intel_ddi_set_pipe_settings(crtc);
3449 intel_ddi_enable_transcoder_func(crtc);
3450
3451 intel_enable_pipe(dev_priv, pipe,
3452 intel_crtc->config.has_pch_encoder);
3453 intel_enable_plane(dev_priv, plane, pipe);
3454
3455 if (intel_crtc->config.has_pch_encoder)
3456 lpt_pch_enable(crtc);
3457
3458 mutex_lock(&dev->struct_mutex);
3459 intel_update_fbc(dev);
3460 mutex_unlock(&dev->struct_mutex);
3461
3462 intel_crtc_update_cursor(crtc, true);
3463
3464 for_each_encoder_on_crtc(dev, crtc, encoder)
3465 encoder->enable(encoder);
3466
3467 /*
3468 * There seems to be a race in PCH platform hw (at least on some
3469 * outputs) where an enabled pipe still completes any pageflip right
3470 * away (as if the pipe is off) instead of waiting for vblank. As soon
3471 * as the first vblank happend, everything works as expected. Hence just
3472 * wait for one vblank before returning to avoid strange things
3473 * happening.
3474 */
3475 intel_wait_for_vblank(dev, intel_crtc->pipe);
3476 }
3477
3478 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3479 {
3480 struct drm_device *dev = crtc->dev;
3481 struct drm_i915_private *dev_priv = dev->dev_private;
3482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3483 struct intel_encoder *encoder;
3484 int pipe = intel_crtc->pipe;
3485 int plane = intel_crtc->plane;
3486 u32 reg, temp;
3487
3488
3489 if (!intel_crtc->active)
3490 return;
3491
3492 for_each_encoder_on_crtc(dev, crtc, encoder)
3493 encoder->disable(encoder);
3494
3495 intel_crtc_wait_for_pending_flips(crtc);
3496 drm_vblank_off(dev, pipe);
3497 intel_crtc_update_cursor(crtc, false);
3498
3499 intel_disable_plane(dev_priv, plane, pipe);
3500
3501 if (dev_priv->cfb_plane == plane)
3502 intel_disable_fbc(dev);
3503
3504 intel_disable_pipe(dev_priv, pipe);
3505
3506 /* Disable PF */
3507 I915_WRITE(PF_CTL(pipe), 0);
3508 I915_WRITE(PF_WIN_SZ(pipe), 0);
3509
3510 for_each_encoder_on_crtc(dev, crtc, encoder)
3511 if (encoder->post_disable)
3512 encoder->post_disable(encoder);
3513
3514 ironlake_fdi_disable(crtc);
3515
3516 ironlake_disable_pch_transcoder(dev_priv, pipe);
3517
3518 if (HAS_PCH_CPT(dev)) {
3519 /* disable TRANS_DP_CTL */
3520 reg = TRANS_DP_CTL(pipe);
3521 temp = I915_READ(reg);
3522 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3523 temp |= TRANS_DP_PORT_SEL_NONE;
3524 I915_WRITE(reg, temp);
3525
3526 /* disable DPLL_SEL */
3527 temp = I915_READ(PCH_DPLL_SEL);
3528 switch (pipe) {
3529 case 0:
3530 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3531 break;
3532 case 1:
3533 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3534 break;
3535 case 2:
3536 /* C shares PLL A or B */
3537 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3538 break;
3539 default:
3540 BUG(); /* wtf */
3541 }
3542 I915_WRITE(PCH_DPLL_SEL, temp);
3543 }
3544
3545 /* disable PCH DPLL */
3546 intel_disable_pch_pll(intel_crtc);
3547
3548 ironlake_fdi_pll_disable(intel_crtc);
3549
3550 intel_crtc->active = false;
3551 intel_update_watermarks(dev);
3552
3553 mutex_lock(&dev->struct_mutex);
3554 intel_update_fbc(dev);
3555 mutex_unlock(&dev->struct_mutex);
3556 }
3557
3558 static void haswell_crtc_disable(struct drm_crtc *crtc)
3559 {
3560 struct drm_device *dev = crtc->dev;
3561 struct drm_i915_private *dev_priv = dev->dev_private;
3562 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3563 struct intel_encoder *encoder;
3564 int pipe = intel_crtc->pipe;
3565 int plane = intel_crtc->plane;
3566 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3567 bool is_pch_port;
3568
3569 if (!intel_crtc->active)
3570 return;
3571
3572 is_pch_port = haswell_crtc_driving_pch(crtc);
3573
3574 for_each_encoder_on_crtc(dev, crtc, encoder)
3575 encoder->disable(encoder);
3576
3577 intel_crtc_wait_for_pending_flips(crtc);
3578 drm_vblank_off(dev, pipe);
3579 intel_crtc_update_cursor(crtc, false);
3580
3581 intel_disable_plane(dev_priv, plane, pipe);
3582
3583 if (dev_priv->cfb_plane == plane)
3584 intel_disable_fbc(dev);
3585
3586 intel_disable_pipe(dev_priv, pipe);
3587
3588 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3589
3590 /* Disable PF */
3591 I915_WRITE(PF_CTL(pipe), 0);
3592 I915_WRITE(PF_WIN_SZ(pipe), 0);
3593
3594 intel_ddi_disable_pipe_clock(intel_crtc);
3595
3596 for_each_encoder_on_crtc(dev, crtc, encoder)
3597 if (encoder->post_disable)
3598 encoder->post_disable(encoder);
3599
3600 if (is_pch_port) {
3601 lpt_disable_pch_transcoder(dev_priv);
3602 intel_ddi_fdi_disable(crtc);
3603 }
3604
3605 intel_crtc->active = false;
3606 intel_update_watermarks(dev);
3607
3608 mutex_lock(&dev->struct_mutex);
3609 intel_update_fbc(dev);
3610 mutex_unlock(&dev->struct_mutex);
3611 }
3612
3613 static void ironlake_crtc_off(struct drm_crtc *crtc)
3614 {
3615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3616 intel_put_pch_pll(intel_crtc);
3617 }
3618
3619 static void haswell_crtc_off(struct drm_crtc *crtc)
3620 {
3621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3622
3623 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3624 * start using it. */
3625 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3626
3627 intel_ddi_put_crtc_pll(crtc);
3628 }
3629
3630 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3631 {
3632 if (!enable && intel_crtc->overlay) {
3633 struct drm_device *dev = intel_crtc->base.dev;
3634 struct drm_i915_private *dev_priv = dev->dev_private;
3635
3636 mutex_lock(&dev->struct_mutex);
3637 dev_priv->mm.interruptible = false;
3638 (void) intel_overlay_switch_off(intel_crtc->overlay);
3639 dev_priv->mm.interruptible = true;
3640 mutex_unlock(&dev->struct_mutex);
3641 }
3642
3643 /* Let userspace switch the overlay on again. In most cases userspace
3644 * has to recompute where to put it anyway.
3645 */
3646 }
3647
3648 /**
3649 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3650 * cursor plane briefly if not already running after enabling the display
3651 * plane.
3652 * This workaround avoids occasional blank screens when self refresh is
3653 * enabled.
3654 */
3655 static void
3656 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3657 {
3658 u32 cntl = I915_READ(CURCNTR(pipe));
3659
3660 if ((cntl & CURSOR_MODE) == 0) {
3661 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3662
3663 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3664 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3665 intel_wait_for_vblank(dev_priv->dev, pipe);
3666 I915_WRITE(CURCNTR(pipe), cntl);
3667 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3668 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3669 }
3670 }
3671
3672 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3673 {
3674 struct drm_device *dev = crtc->dev;
3675 struct drm_i915_private *dev_priv = dev->dev_private;
3676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3677 struct intel_encoder *encoder;
3678 int pipe = intel_crtc->pipe;
3679 int plane = intel_crtc->plane;
3680
3681 WARN_ON(!crtc->enabled);
3682
3683 if (intel_crtc->active)
3684 return;
3685
3686 intel_crtc->active = true;
3687 intel_update_watermarks(dev);
3688
3689 intel_enable_pll(dev_priv, pipe);
3690
3691 for_each_encoder_on_crtc(dev, crtc, encoder)
3692 if (encoder->pre_enable)
3693 encoder->pre_enable(encoder);
3694
3695 intel_enable_pipe(dev_priv, pipe, false);
3696 intel_enable_plane(dev_priv, plane, pipe);
3697 if (IS_G4X(dev))
3698 g4x_fixup_plane(dev_priv, pipe);
3699
3700 intel_crtc_load_lut(crtc);
3701 intel_update_fbc(dev);
3702
3703 /* Give the overlay scaler a chance to enable if it's on this pipe */
3704 intel_crtc_dpms_overlay(intel_crtc, true);
3705 intel_crtc_update_cursor(crtc, true);
3706
3707 for_each_encoder_on_crtc(dev, crtc, encoder)
3708 encoder->enable(encoder);
3709 }
3710
3711 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3712 {
3713 struct drm_device *dev = crtc->dev;
3714 struct drm_i915_private *dev_priv = dev->dev_private;
3715 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3716 struct intel_encoder *encoder;
3717 int pipe = intel_crtc->pipe;
3718 int plane = intel_crtc->plane;
3719 u32 pctl;
3720
3721
3722 if (!intel_crtc->active)
3723 return;
3724
3725 for_each_encoder_on_crtc(dev, crtc, encoder)
3726 encoder->disable(encoder);
3727
3728 /* Give the overlay scaler a chance to disable if it's on this pipe */
3729 intel_crtc_wait_for_pending_flips(crtc);
3730 drm_vblank_off(dev, pipe);
3731 intel_crtc_dpms_overlay(intel_crtc, false);
3732 intel_crtc_update_cursor(crtc, false);
3733
3734 if (dev_priv->cfb_plane == plane)
3735 intel_disable_fbc(dev);
3736
3737 intel_disable_plane(dev_priv, plane, pipe);
3738 intel_disable_pipe(dev_priv, pipe);
3739
3740 /* Disable pannel fitter if it is on this pipe. */
3741 pctl = I915_READ(PFIT_CONTROL);
3742 if ((pctl & PFIT_ENABLE) &&
3743 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3744 I915_WRITE(PFIT_CONTROL, 0);
3745
3746 intel_disable_pll(dev_priv, pipe);
3747
3748 intel_crtc->active = false;
3749 intel_update_fbc(dev);
3750 intel_update_watermarks(dev);
3751 }
3752
3753 static void i9xx_crtc_off(struct drm_crtc *crtc)
3754 {
3755 }
3756
3757 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3758 bool enabled)
3759 {
3760 struct drm_device *dev = crtc->dev;
3761 struct drm_i915_master_private *master_priv;
3762 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3763 int pipe = intel_crtc->pipe;
3764
3765 if (!dev->primary->master)
3766 return;
3767
3768 master_priv = dev->primary->master->driver_priv;
3769 if (!master_priv->sarea_priv)
3770 return;
3771
3772 switch (pipe) {
3773 case 0:
3774 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3775 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3776 break;
3777 case 1:
3778 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3779 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3780 break;
3781 default:
3782 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3783 break;
3784 }
3785 }
3786
3787 /**
3788 * Sets the power management mode of the pipe and plane.
3789 */
3790 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3791 {
3792 struct drm_device *dev = crtc->dev;
3793 struct drm_i915_private *dev_priv = dev->dev_private;
3794 struct intel_encoder *intel_encoder;
3795 bool enable = false;
3796
3797 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3798 enable |= intel_encoder->connectors_active;
3799
3800 if (enable)
3801 dev_priv->display.crtc_enable(crtc);
3802 else
3803 dev_priv->display.crtc_disable(crtc);
3804
3805 intel_crtc_update_sarea(crtc, enable);
3806 }
3807
3808 static void intel_crtc_disable(struct drm_crtc *crtc)
3809 {
3810 struct drm_device *dev = crtc->dev;
3811 struct drm_connector *connector;
3812 struct drm_i915_private *dev_priv = dev->dev_private;
3813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3814
3815 /* crtc should still be enabled when we disable it. */
3816 WARN_ON(!crtc->enabled);
3817
3818 intel_crtc->eld_vld = false;
3819 dev_priv->display.crtc_disable(crtc);
3820 intel_crtc_update_sarea(crtc, false);
3821 dev_priv->display.off(crtc);
3822
3823 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3824 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3825
3826 if (crtc->fb) {
3827 mutex_lock(&dev->struct_mutex);
3828 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3829 mutex_unlock(&dev->struct_mutex);
3830 crtc->fb = NULL;
3831 }
3832
3833 /* Update computed state. */
3834 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3835 if (!connector->encoder || !connector->encoder->crtc)
3836 continue;
3837
3838 if (connector->encoder->crtc != crtc)
3839 continue;
3840
3841 connector->dpms = DRM_MODE_DPMS_OFF;
3842 to_intel_encoder(connector->encoder)->connectors_active = false;
3843 }
3844 }
3845
3846 void intel_modeset_disable(struct drm_device *dev)
3847 {
3848 struct drm_crtc *crtc;
3849
3850 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3851 if (crtc->enabled)
3852 intel_crtc_disable(crtc);
3853 }
3854 }
3855
3856 void intel_encoder_destroy(struct drm_encoder *encoder)
3857 {
3858 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3859
3860 drm_encoder_cleanup(encoder);
3861 kfree(intel_encoder);
3862 }
3863
3864 /* Simple dpms helper for encodres with just one connector, no cloning and only
3865 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3866 * state of the entire output pipe. */
3867 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3868 {
3869 if (mode == DRM_MODE_DPMS_ON) {
3870 encoder->connectors_active = true;
3871
3872 intel_crtc_update_dpms(encoder->base.crtc);
3873 } else {
3874 encoder->connectors_active = false;
3875
3876 intel_crtc_update_dpms(encoder->base.crtc);
3877 }
3878 }
3879
3880 /* Cross check the actual hw state with our own modeset state tracking (and it's
3881 * internal consistency). */
3882 static void intel_connector_check_state(struct intel_connector *connector)
3883 {
3884 if (connector->get_hw_state(connector)) {
3885 struct intel_encoder *encoder = connector->encoder;
3886 struct drm_crtc *crtc;
3887 bool encoder_enabled;
3888 enum pipe pipe;
3889
3890 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3891 connector->base.base.id,
3892 drm_get_connector_name(&connector->base));
3893
3894 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3895 "wrong connector dpms state\n");
3896 WARN(connector->base.encoder != &encoder->base,
3897 "active connector not linked to encoder\n");
3898 WARN(!encoder->connectors_active,
3899 "encoder->connectors_active not set\n");
3900
3901 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3902 WARN(!encoder_enabled, "encoder not enabled\n");
3903 if (WARN_ON(!encoder->base.crtc))
3904 return;
3905
3906 crtc = encoder->base.crtc;
3907
3908 WARN(!crtc->enabled, "crtc not enabled\n");
3909 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3910 WARN(pipe != to_intel_crtc(crtc)->pipe,
3911 "encoder active on the wrong pipe\n");
3912 }
3913 }
3914
3915 /* Even simpler default implementation, if there's really no special case to
3916 * consider. */
3917 void intel_connector_dpms(struct drm_connector *connector, int mode)
3918 {
3919 struct intel_encoder *encoder = intel_attached_encoder(connector);
3920
3921 /* All the simple cases only support two dpms states. */
3922 if (mode != DRM_MODE_DPMS_ON)
3923 mode = DRM_MODE_DPMS_OFF;
3924
3925 if (mode == connector->dpms)
3926 return;
3927
3928 connector->dpms = mode;
3929
3930 /* Only need to change hw state when actually enabled */
3931 if (encoder->base.crtc)
3932 intel_encoder_dpms(encoder, mode);
3933 else
3934 WARN_ON(encoder->connectors_active != false);
3935
3936 intel_modeset_check_state(connector->dev);
3937 }
3938
3939 /* Simple connector->get_hw_state implementation for encoders that support only
3940 * one connector and no cloning and hence the encoder state determines the state
3941 * of the connector. */
3942 bool intel_connector_get_hw_state(struct intel_connector *connector)
3943 {
3944 enum pipe pipe = 0;
3945 struct intel_encoder *encoder = connector->encoder;
3946
3947 return encoder->get_hw_state(encoder, &pipe);
3948 }
3949
3950 static bool intel_crtc_compute_config(struct drm_crtc *crtc,
3951 struct intel_crtc_config *pipe_config)
3952 {
3953 struct drm_device *dev = crtc->dev;
3954 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3955
3956 if (HAS_PCH_SPLIT(dev)) {
3957 /* FDI link clock is fixed at 2.7G */
3958 if (pipe_config->requested_mode.clock * 3
3959 > IRONLAKE_FDI_FREQ * 4)
3960 return false;
3961 }
3962
3963 /* All interlaced capable intel hw wants timings in frames. Note though
3964 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3965 * timings, so we need to be careful not to clobber these.*/
3966 if (!pipe_config->timings_set)
3967 drm_mode_set_crtcinfo(adjusted_mode, 0);
3968
3969 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3970 * with a hsync front porch of 0.
3971 */
3972 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3973 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3974 return false;
3975
3976 return true;
3977 }
3978
3979 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3980 {
3981 return 400000; /* FIXME */
3982 }
3983
3984 static int i945_get_display_clock_speed(struct drm_device *dev)
3985 {
3986 return 400000;
3987 }
3988
3989 static int i915_get_display_clock_speed(struct drm_device *dev)
3990 {
3991 return 333000;
3992 }
3993
3994 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3995 {
3996 return 200000;
3997 }
3998
3999 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4000 {
4001 u16 gcfgc = 0;
4002
4003 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4004
4005 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4006 return 133000;
4007 else {
4008 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4009 case GC_DISPLAY_CLOCK_333_MHZ:
4010 return 333000;
4011 default:
4012 case GC_DISPLAY_CLOCK_190_200_MHZ:
4013 return 190000;
4014 }
4015 }
4016 }
4017
4018 static int i865_get_display_clock_speed(struct drm_device *dev)
4019 {
4020 return 266000;
4021 }
4022
4023 static int i855_get_display_clock_speed(struct drm_device *dev)
4024 {
4025 u16 hpllcc = 0;
4026 /* Assume that the hardware is in the high speed state. This
4027 * should be the default.
4028 */
4029 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4030 case GC_CLOCK_133_200:
4031 case GC_CLOCK_100_200:
4032 return 200000;
4033 case GC_CLOCK_166_250:
4034 return 250000;
4035 case GC_CLOCK_100_133:
4036 return 133000;
4037 }
4038
4039 /* Shouldn't happen */
4040 return 0;
4041 }
4042
4043 static int i830_get_display_clock_speed(struct drm_device *dev)
4044 {
4045 return 133000;
4046 }
4047
4048 static void
4049 intel_reduce_ratio(uint32_t *num, uint32_t *den)
4050 {
4051 while (*num > 0xffffff || *den > 0xffffff) {
4052 *num >>= 1;
4053 *den >>= 1;
4054 }
4055 }
4056
4057 void
4058 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4059 int pixel_clock, int link_clock,
4060 struct intel_link_m_n *m_n)
4061 {
4062 m_n->tu = 64;
4063 m_n->gmch_m = bits_per_pixel * pixel_clock;
4064 m_n->gmch_n = link_clock * nlanes * 8;
4065 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4066 m_n->link_m = pixel_clock;
4067 m_n->link_n = link_clock;
4068 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4069 }
4070
4071 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4072 {
4073 if (i915_panel_use_ssc >= 0)
4074 return i915_panel_use_ssc != 0;
4075 return dev_priv->lvds_use_ssc
4076 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4077 }
4078
4079 /**
4080 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4081 * @crtc: CRTC structure
4082 * @mode: requested mode
4083 *
4084 * A pipe may be connected to one or more outputs. Based on the depth of the
4085 * attached framebuffer, choose a good color depth to use on the pipe.
4086 *
4087 * If possible, match the pipe depth to the fb depth. In some cases, this
4088 * isn't ideal, because the connected output supports a lesser or restricted
4089 * set of depths. Resolve that here:
4090 * LVDS typically supports only 6bpc, so clamp down in that case
4091 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4092 * Displays may support a restricted set as well, check EDID and clamp as
4093 * appropriate.
4094 * DP may want to dither down to 6bpc to fit larger modes
4095 *
4096 * RETURNS:
4097 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4098 * true if they don't match).
4099 */
4100 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4101 struct drm_framebuffer *fb,
4102 unsigned int *pipe_bpp,
4103 struct drm_display_mode *mode)
4104 {
4105 struct drm_device *dev = crtc->dev;
4106 struct drm_i915_private *dev_priv = dev->dev_private;
4107 struct drm_connector *connector;
4108 struct intel_encoder *intel_encoder;
4109 unsigned int display_bpc = UINT_MAX, bpc;
4110
4111 /* Walk the encoders & connectors on this crtc, get min bpc */
4112 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4113
4114 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4115 unsigned int lvds_bpc;
4116
4117 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4118 LVDS_A3_POWER_UP)
4119 lvds_bpc = 8;
4120 else
4121 lvds_bpc = 6;
4122
4123 if (lvds_bpc < display_bpc) {
4124 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4125 display_bpc = lvds_bpc;
4126 }
4127 continue;
4128 }
4129
4130 /* Not one of the known troublemakers, check the EDID */
4131 list_for_each_entry(connector, &dev->mode_config.connector_list,
4132 head) {
4133 if (connector->encoder != &intel_encoder->base)
4134 continue;
4135
4136 /* Don't use an invalid EDID bpc value */
4137 if (connector->display_info.bpc &&
4138 connector->display_info.bpc < display_bpc) {
4139 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4140 display_bpc = connector->display_info.bpc;
4141 }
4142 }
4143
4144 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4145 /* Use VBT settings if we have an eDP panel */
4146 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4147
4148 if (edp_bpc && edp_bpc < display_bpc) {
4149 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4150 display_bpc = edp_bpc;
4151 }
4152 continue;
4153 }
4154
4155 /*
4156 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4157 * through, clamp it down. (Note: >12bpc will be caught below.)
4158 */
4159 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4160 if (display_bpc > 8 && display_bpc < 12) {
4161 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4162 display_bpc = 12;
4163 } else {
4164 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4165 display_bpc = 8;
4166 }
4167 }
4168 }
4169
4170 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4171 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4172 display_bpc = 6;
4173 }
4174
4175 /*
4176 * We could just drive the pipe at the highest bpc all the time and
4177 * enable dithering as needed, but that costs bandwidth. So choose
4178 * the minimum value that expresses the full color range of the fb but
4179 * also stays within the max display bpc discovered above.
4180 */
4181
4182 switch (fb->depth) {
4183 case 8:
4184 bpc = 8; /* since we go through a colormap */
4185 break;
4186 case 15:
4187 case 16:
4188 bpc = 6; /* min is 18bpp */
4189 break;
4190 case 24:
4191 bpc = 8;
4192 break;
4193 case 30:
4194 bpc = 10;
4195 break;
4196 case 48:
4197 bpc = 12;
4198 break;
4199 default:
4200 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4201 bpc = min((unsigned int)8, display_bpc);
4202 break;
4203 }
4204
4205 display_bpc = min(display_bpc, bpc);
4206
4207 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4208 bpc, display_bpc);
4209
4210 *pipe_bpp = display_bpc * 3;
4211
4212 return display_bpc != bpc;
4213 }
4214
4215 static int vlv_get_refclk(struct drm_crtc *crtc)
4216 {
4217 struct drm_device *dev = crtc->dev;
4218 struct drm_i915_private *dev_priv = dev->dev_private;
4219 int refclk = 27000; /* for DP & HDMI */
4220
4221 return 100000; /* only one validated so far */
4222
4223 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4224 refclk = 96000;
4225 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4226 if (intel_panel_use_ssc(dev_priv))
4227 refclk = 100000;
4228 else
4229 refclk = 96000;
4230 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4231 refclk = 100000;
4232 }
4233
4234 return refclk;
4235 }
4236
4237 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4238 {
4239 struct drm_device *dev = crtc->dev;
4240 struct drm_i915_private *dev_priv = dev->dev_private;
4241 int refclk;
4242
4243 if (IS_VALLEYVIEW(dev)) {
4244 refclk = vlv_get_refclk(crtc);
4245 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4246 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4247 refclk = dev_priv->lvds_ssc_freq * 1000;
4248 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4249 refclk / 1000);
4250 } else if (!IS_GEN2(dev)) {
4251 refclk = 96000;
4252 } else {
4253 refclk = 48000;
4254 }
4255
4256 return refclk;
4257 }
4258
4259 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4260 intel_clock_t *clock)
4261 {
4262 /* SDVO TV has fixed PLL values depend on its clock range,
4263 this mirrors vbios setting. */
4264 if (adjusted_mode->clock >= 100000
4265 && adjusted_mode->clock < 140500) {
4266 clock->p1 = 2;
4267 clock->p2 = 10;
4268 clock->n = 3;
4269 clock->m1 = 16;
4270 clock->m2 = 8;
4271 } else if (adjusted_mode->clock >= 140500
4272 && adjusted_mode->clock <= 200000) {
4273 clock->p1 = 1;
4274 clock->p2 = 10;
4275 clock->n = 6;
4276 clock->m1 = 12;
4277 clock->m2 = 8;
4278 }
4279 }
4280
4281 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4282 intel_clock_t *clock,
4283 intel_clock_t *reduced_clock)
4284 {
4285 struct drm_device *dev = crtc->dev;
4286 struct drm_i915_private *dev_priv = dev->dev_private;
4287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4288 int pipe = intel_crtc->pipe;
4289 u32 fp, fp2 = 0;
4290
4291 if (IS_PINEVIEW(dev)) {
4292 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4293 if (reduced_clock)
4294 fp2 = (1 << reduced_clock->n) << 16 |
4295 reduced_clock->m1 << 8 | reduced_clock->m2;
4296 } else {
4297 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4298 if (reduced_clock)
4299 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4300 reduced_clock->m2;
4301 }
4302
4303 I915_WRITE(FP0(pipe), fp);
4304
4305 intel_crtc->lowfreq_avail = false;
4306 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4307 reduced_clock && i915_powersave) {
4308 I915_WRITE(FP1(pipe), fp2);
4309 intel_crtc->lowfreq_avail = true;
4310 } else {
4311 I915_WRITE(FP1(pipe), fp);
4312 }
4313 }
4314
4315 static void vlv_update_pll(struct drm_crtc *crtc,
4316 intel_clock_t *clock, intel_clock_t *reduced_clock,
4317 int num_connectors)
4318 {
4319 struct drm_device *dev = crtc->dev;
4320 struct drm_i915_private *dev_priv = dev->dev_private;
4321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4322 struct drm_display_mode *adjusted_mode =
4323 &intel_crtc->config.adjusted_mode;
4324 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4325 int pipe = intel_crtc->pipe;
4326 u32 dpll, mdiv, pdiv;
4327 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4328 bool is_sdvo;
4329 u32 temp;
4330
4331 mutex_lock(&dev_priv->dpio_lock);
4332
4333 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4334 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4335
4336 dpll = DPLL_VGA_MODE_DIS;
4337 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4338 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4339 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4340
4341 I915_WRITE(DPLL(pipe), dpll);
4342 POSTING_READ(DPLL(pipe));
4343
4344 bestn = clock->n;
4345 bestm1 = clock->m1;
4346 bestm2 = clock->m2;
4347 bestp1 = clock->p1;
4348 bestp2 = clock->p2;
4349
4350 /*
4351 * In Valleyview PLL and program lane counter registers are exposed
4352 * through DPIO interface
4353 */
4354 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4355 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4356 mdiv |= ((bestn << DPIO_N_SHIFT));
4357 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4358 mdiv |= (1 << DPIO_K_SHIFT);
4359 mdiv |= DPIO_ENABLE_CALIBRATION;
4360 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4361
4362 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4363
4364 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4365 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4366 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4367 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4368 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4369
4370 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4371
4372 dpll |= DPLL_VCO_ENABLE;
4373 I915_WRITE(DPLL(pipe), dpll);
4374 POSTING_READ(DPLL(pipe));
4375 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4376 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4377
4378 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4379
4380 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4381 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4382
4383 I915_WRITE(DPLL(pipe), dpll);
4384
4385 /* Wait for the clocks to stabilize. */
4386 POSTING_READ(DPLL(pipe));
4387 udelay(150);
4388
4389 temp = 0;
4390 if (is_sdvo) {
4391 temp = 0;
4392 if (intel_crtc->config.pixel_multiplier > 1) {
4393 temp = (intel_crtc->config.pixel_multiplier - 1)
4394 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4395 }
4396 }
4397 I915_WRITE(DPLL_MD(pipe), temp);
4398 POSTING_READ(DPLL_MD(pipe));
4399
4400 /* Now program lane control registers */
4401 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4402 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4403 {
4404 temp = 0x1000C4;
4405 if(pipe == 1)
4406 temp |= (1 << 21);
4407 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4408 }
4409 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4410 {
4411 temp = 0x1000C4;
4412 if(pipe == 1)
4413 temp |= (1 << 21);
4414 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4415 }
4416
4417 mutex_unlock(&dev_priv->dpio_lock);
4418 }
4419
4420 static void i9xx_update_pll(struct drm_crtc *crtc,
4421 intel_clock_t *clock, intel_clock_t *reduced_clock,
4422 int num_connectors)
4423 {
4424 struct drm_device *dev = crtc->dev;
4425 struct drm_i915_private *dev_priv = dev->dev_private;
4426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4427 struct drm_display_mode *adjusted_mode =
4428 &intel_crtc->config.adjusted_mode;
4429 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4430 struct intel_encoder *encoder;
4431 int pipe = intel_crtc->pipe;
4432 u32 dpll;
4433 bool is_sdvo;
4434
4435 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4436
4437 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4438 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4439
4440 dpll = DPLL_VGA_MODE_DIS;
4441
4442 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4443 dpll |= DPLLB_MODE_LVDS;
4444 else
4445 dpll |= DPLLB_MODE_DAC_SERIAL;
4446
4447 if (is_sdvo) {
4448 if ((intel_crtc->config.pixel_multiplier > 1) &&
4449 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4450 dpll |= (intel_crtc->config.pixel_multiplier - 1)
4451 << SDVO_MULTIPLIER_SHIFT_HIRES;
4452 }
4453 dpll |= DPLL_DVO_HIGH_SPEED;
4454 }
4455 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4456 dpll |= DPLL_DVO_HIGH_SPEED;
4457
4458 /* compute bitmask from p1 value */
4459 if (IS_PINEVIEW(dev))
4460 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4461 else {
4462 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4463 if (IS_G4X(dev) && reduced_clock)
4464 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4465 }
4466 switch (clock->p2) {
4467 case 5:
4468 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4469 break;
4470 case 7:
4471 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4472 break;
4473 case 10:
4474 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4475 break;
4476 case 14:
4477 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4478 break;
4479 }
4480 if (INTEL_INFO(dev)->gen >= 4)
4481 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4482
4483 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4484 dpll |= PLL_REF_INPUT_TVCLKINBC;
4485 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4486 /* XXX: just matching BIOS for now */
4487 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4488 dpll |= 3;
4489 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4490 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4491 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4492 else
4493 dpll |= PLL_REF_INPUT_DREFCLK;
4494
4495 dpll |= DPLL_VCO_ENABLE;
4496 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4497 POSTING_READ(DPLL(pipe));
4498 udelay(150);
4499
4500 for_each_encoder_on_crtc(dev, crtc, encoder)
4501 if (encoder->pre_pll_enable)
4502 encoder->pre_pll_enable(encoder);
4503
4504 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4505 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4506
4507 I915_WRITE(DPLL(pipe), dpll);
4508
4509 /* Wait for the clocks to stabilize. */
4510 POSTING_READ(DPLL(pipe));
4511 udelay(150);
4512
4513 if (INTEL_INFO(dev)->gen >= 4) {
4514 u32 temp = 0;
4515 if (is_sdvo) {
4516 temp = 0;
4517 if (intel_crtc->config.pixel_multiplier > 1) {
4518 temp = (intel_crtc->config.pixel_multiplier - 1)
4519 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4520 }
4521 }
4522 I915_WRITE(DPLL_MD(pipe), temp);
4523 } else {
4524 /* The pixel multiplier can only be updated once the
4525 * DPLL is enabled and the clocks are stable.
4526 *
4527 * So write it again.
4528 */
4529 I915_WRITE(DPLL(pipe), dpll);
4530 }
4531 }
4532
4533 static void i8xx_update_pll(struct drm_crtc *crtc,
4534 struct drm_display_mode *adjusted_mode,
4535 intel_clock_t *clock, intel_clock_t *reduced_clock,
4536 int num_connectors)
4537 {
4538 struct drm_device *dev = crtc->dev;
4539 struct drm_i915_private *dev_priv = dev->dev_private;
4540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4541 struct intel_encoder *encoder;
4542 int pipe = intel_crtc->pipe;
4543 u32 dpll;
4544
4545 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4546
4547 dpll = DPLL_VGA_MODE_DIS;
4548
4549 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4550 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4551 } else {
4552 if (clock->p1 == 2)
4553 dpll |= PLL_P1_DIVIDE_BY_TWO;
4554 else
4555 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4556 if (clock->p2 == 4)
4557 dpll |= PLL_P2_DIVIDE_BY_4;
4558 }
4559
4560 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4561 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4562 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4563 else
4564 dpll |= PLL_REF_INPUT_DREFCLK;
4565
4566 dpll |= DPLL_VCO_ENABLE;
4567 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4568 POSTING_READ(DPLL(pipe));
4569 udelay(150);
4570
4571 for_each_encoder_on_crtc(dev, crtc, encoder)
4572 if (encoder->pre_pll_enable)
4573 encoder->pre_pll_enable(encoder);
4574
4575 I915_WRITE(DPLL(pipe), dpll);
4576
4577 /* Wait for the clocks to stabilize. */
4578 POSTING_READ(DPLL(pipe));
4579 udelay(150);
4580
4581 /* The pixel multiplier can only be updated once the
4582 * DPLL is enabled and the clocks are stable.
4583 *
4584 * So write it again.
4585 */
4586 I915_WRITE(DPLL(pipe), dpll);
4587 }
4588
4589 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4590 struct drm_display_mode *mode,
4591 struct drm_display_mode *adjusted_mode)
4592 {
4593 struct drm_device *dev = intel_crtc->base.dev;
4594 struct drm_i915_private *dev_priv = dev->dev_private;
4595 enum pipe pipe = intel_crtc->pipe;
4596 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4597 uint32_t vsyncshift;
4598
4599 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4600 /* the chip adds 2 halflines automatically */
4601 adjusted_mode->crtc_vtotal -= 1;
4602 adjusted_mode->crtc_vblank_end -= 1;
4603 vsyncshift = adjusted_mode->crtc_hsync_start
4604 - adjusted_mode->crtc_htotal / 2;
4605 } else {
4606 vsyncshift = 0;
4607 }
4608
4609 if (INTEL_INFO(dev)->gen > 3)
4610 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4611
4612 I915_WRITE(HTOTAL(cpu_transcoder),
4613 (adjusted_mode->crtc_hdisplay - 1) |
4614 ((adjusted_mode->crtc_htotal - 1) << 16));
4615 I915_WRITE(HBLANK(cpu_transcoder),
4616 (adjusted_mode->crtc_hblank_start - 1) |
4617 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4618 I915_WRITE(HSYNC(cpu_transcoder),
4619 (adjusted_mode->crtc_hsync_start - 1) |
4620 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4621
4622 I915_WRITE(VTOTAL(cpu_transcoder),
4623 (adjusted_mode->crtc_vdisplay - 1) |
4624 ((adjusted_mode->crtc_vtotal - 1) << 16));
4625 I915_WRITE(VBLANK(cpu_transcoder),
4626 (adjusted_mode->crtc_vblank_start - 1) |
4627 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4628 I915_WRITE(VSYNC(cpu_transcoder),
4629 (adjusted_mode->crtc_vsync_start - 1) |
4630 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4631
4632 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4633 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4634 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4635 * bits. */
4636 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4637 (pipe == PIPE_B || pipe == PIPE_C))
4638 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4639
4640 /* pipesrc controls the size that is scaled from, which should
4641 * always be the user's requested size.
4642 */
4643 I915_WRITE(PIPESRC(pipe),
4644 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4645 }
4646
4647 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4648 int x, int y,
4649 struct drm_framebuffer *fb)
4650 {
4651 struct drm_device *dev = crtc->dev;
4652 struct drm_i915_private *dev_priv = dev->dev_private;
4653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4654 struct drm_display_mode *adjusted_mode =
4655 &intel_crtc->config.adjusted_mode;
4656 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4657 int pipe = intel_crtc->pipe;
4658 int plane = intel_crtc->plane;
4659 int refclk, num_connectors = 0;
4660 intel_clock_t clock, reduced_clock;
4661 u32 dspcntr, pipeconf;
4662 bool ok, has_reduced_clock = false, is_sdvo = false;
4663 bool is_lvds = false, is_tv = false, is_dp = false;
4664 struct intel_encoder *encoder;
4665 const intel_limit_t *limit;
4666 int ret;
4667
4668 /* temporary hack */
4669 intel_crtc->config.dither =
4670 adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC;
4671
4672 for_each_encoder_on_crtc(dev, crtc, encoder) {
4673 switch (encoder->type) {
4674 case INTEL_OUTPUT_LVDS:
4675 is_lvds = true;
4676 break;
4677 case INTEL_OUTPUT_SDVO:
4678 case INTEL_OUTPUT_HDMI:
4679 is_sdvo = true;
4680 if (encoder->needs_tv_clock)
4681 is_tv = true;
4682 break;
4683 case INTEL_OUTPUT_TVOUT:
4684 is_tv = true;
4685 break;
4686 case INTEL_OUTPUT_DISPLAYPORT:
4687 is_dp = true;
4688 break;
4689 }
4690
4691 num_connectors++;
4692 }
4693
4694 refclk = i9xx_get_refclk(crtc, num_connectors);
4695
4696 /*
4697 * Returns a set of divisors for the desired target clock with the given
4698 * refclk, or FALSE. The returned values represent the clock equation:
4699 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4700 */
4701 limit = intel_limit(crtc, refclk);
4702 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4703 &clock);
4704 if (!ok) {
4705 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4706 return -EINVAL;
4707 }
4708
4709 /* Ensure that the cursor is valid for the new mode before changing... */
4710 intel_crtc_update_cursor(crtc, true);
4711
4712 if (is_lvds && dev_priv->lvds_downclock_avail) {
4713 /*
4714 * Ensure we match the reduced clock's P to the target clock.
4715 * If the clocks don't match, we can't switch the display clock
4716 * by using the FP0/FP1. In such case we will disable the LVDS
4717 * downclock feature.
4718 */
4719 has_reduced_clock = limit->find_pll(limit, crtc,
4720 dev_priv->lvds_downclock,
4721 refclk,
4722 &clock,
4723 &reduced_clock);
4724 }
4725
4726 if (is_sdvo && is_tv)
4727 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4728
4729 if (IS_GEN2(dev))
4730 i8xx_update_pll(crtc, adjusted_mode, &clock,
4731 has_reduced_clock ? &reduced_clock : NULL,
4732 num_connectors);
4733 else if (IS_VALLEYVIEW(dev))
4734 vlv_update_pll(crtc, &clock,
4735 has_reduced_clock ? &reduced_clock : NULL,
4736 num_connectors);
4737 else
4738 i9xx_update_pll(crtc, &clock,
4739 has_reduced_clock ? &reduced_clock : NULL,
4740 num_connectors);
4741
4742 /* setup pipeconf */
4743 pipeconf = I915_READ(PIPECONF(pipe));
4744
4745 /* Set up the display plane register */
4746 dspcntr = DISPPLANE_GAMMA_ENABLE;
4747
4748 if (!IS_VALLEYVIEW(dev)) {
4749 if (pipe == 0)
4750 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4751 else
4752 dspcntr |= DISPPLANE_SEL_PIPE_B;
4753 }
4754
4755 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4756 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4757 * core speed.
4758 *
4759 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4760 * pipe == 0 check?
4761 */
4762 if (mode->clock >
4763 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4764 pipeconf |= PIPECONF_DOUBLE_WIDE;
4765 else
4766 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4767 }
4768
4769 /* default to 8bpc */
4770 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4771 if (is_dp) {
4772 if (intel_crtc->config.dither) {
4773 pipeconf |= PIPECONF_6BPC |
4774 PIPECONF_DITHER_EN |
4775 PIPECONF_DITHER_TYPE_SP;
4776 }
4777 }
4778
4779 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4780 if (intel_crtc->config.dither) {
4781 pipeconf |= PIPECONF_6BPC |
4782 PIPECONF_ENABLE |
4783 I965_PIPECONF_ACTIVE;
4784 }
4785 }
4786
4787 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4788 drm_mode_debug_printmodeline(mode);
4789
4790 if (HAS_PIPE_CXSR(dev)) {
4791 if (intel_crtc->lowfreq_avail) {
4792 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4793 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4794 } else {
4795 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4796 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4797 }
4798 }
4799
4800 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4801 if (!IS_GEN2(dev) &&
4802 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4803 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4804 else
4805 pipeconf |= PIPECONF_PROGRESSIVE;
4806
4807 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4808
4809 /* pipesrc and dspsize control the size that is scaled from,
4810 * which should always be the user's requested size.
4811 */
4812 I915_WRITE(DSPSIZE(plane),
4813 ((mode->vdisplay - 1) << 16) |
4814 (mode->hdisplay - 1));
4815 I915_WRITE(DSPPOS(plane), 0);
4816
4817 I915_WRITE(PIPECONF(pipe), pipeconf);
4818 POSTING_READ(PIPECONF(pipe));
4819 intel_enable_pipe(dev_priv, pipe, false);
4820
4821 intel_wait_for_vblank(dev, pipe);
4822
4823 I915_WRITE(DSPCNTR(plane), dspcntr);
4824 POSTING_READ(DSPCNTR(plane));
4825
4826 ret = intel_pipe_set_base(crtc, x, y, fb);
4827
4828 intel_update_watermarks(dev);
4829
4830 return ret;
4831 }
4832
4833 static void ironlake_init_pch_refclk(struct drm_device *dev)
4834 {
4835 struct drm_i915_private *dev_priv = dev->dev_private;
4836 struct drm_mode_config *mode_config = &dev->mode_config;
4837 struct intel_encoder *encoder;
4838 u32 temp;
4839 bool has_lvds = false;
4840 bool has_cpu_edp = false;
4841 bool has_pch_edp = false;
4842 bool has_panel = false;
4843 bool has_ck505 = false;
4844 bool can_ssc = false;
4845
4846 /* We need to take the global config into account */
4847 list_for_each_entry(encoder, &mode_config->encoder_list,
4848 base.head) {
4849 switch (encoder->type) {
4850 case INTEL_OUTPUT_LVDS:
4851 has_panel = true;
4852 has_lvds = true;
4853 break;
4854 case INTEL_OUTPUT_EDP:
4855 has_panel = true;
4856 if (intel_encoder_is_pch_edp(&encoder->base))
4857 has_pch_edp = true;
4858 else
4859 has_cpu_edp = true;
4860 break;
4861 }
4862 }
4863
4864 if (HAS_PCH_IBX(dev)) {
4865 has_ck505 = dev_priv->display_clock_mode;
4866 can_ssc = has_ck505;
4867 } else {
4868 has_ck505 = false;
4869 can_ssc = true;
4870 }
4871
4872 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4873 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4874 has_ck505);
4875
4876 /* Ironlake: try to setup display ref clock before DPLL
4877 * enabling. This is only under driver's control after
4878 * PCH B stepping, previous chipset stepping should be
4879 * ignoring this setting.
4880 */
4881 temp = I915_READ(PCH_DREF_CONTROL);
4882 /* Always enable nonspread source */
4883 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4884
4885 if (has_ck505)
4886 temp |= DREF_NONSPREAD_CK505_ENABLE;
4887 else
4888 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4889
4890 if (has_panel) {
4891 temp &= ~DREF_SSC_SOURCE_MASK;
4892 temp |= DREF_SSC_SOURCE_ENABLE;
4893
4894 /* SSC must be turned on before enabling the CPU output */
4895 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4896 DRM_DEBUG_KMS("Using SSC on panel\n");
4897 temp |= DREF_SSC1_ENABLE;
4898 } else
4899 temp &= ~DREF_SSC1_ENABLE;
4900
4901 /* Get SSC going before enabling the outputs */
4902 I915_WRITE(PCH_DREF_CONTROL, temp);
4903 POSTING_READ(PCH_DREF_CONTROL);
4904 udelay(200);
4905
4906 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4907
4908 /* Enable CPU source on CPU attached eDP */
4909 if (has_cpu_edp) {
4910 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4911 DRM_DEBUG_KMS("Using SSC on eDP\n");
4912 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4913 }
4914 else
4915 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4916 } else
4917 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4918
4919 I915_WRITE(PCH_DREF_CONTROL, temp);
4920 POSTING_READ(PCH_DREF_CONTROL);
4921 udelay(200);
4922 } else {
4923 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4924
4925 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4926
4927 /* Turn off CPU output */
4928 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4929
4930 I915_WRITE(PCH_DREF_CONTROL, temp);
4931 POSTING_READ(PCH_DREF_CONTROL);
4932 udelay(200);
4933
4934 /* Turn off the SSC source */
4935 temp &= ~DREF_SSC_SOURCE_MASK;
4936 temp |= DREF_SSC_SOURCE_DISABLE;
4937
4938 /* Turn off SSC1 */
4939 temp &= ~ DREF_SSC1_ENABLE;
4940
4941 I915_WRITE(PCH_DREF_CONTROL, temp);
4942 POSTING_READ(PCH_DREF_CONTROL);
4943 udelay(200);
4944 }
4945 }
4946
4947 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4948 static void lpt_init_pch_refclk(struct drm_device *dev)
4949 {
4950 struct drm_i915_private *dev_priv = dev->dev_private;
4951 struct drm_mode_config *mode_config = &dev->mode_config;
4952 struct intel_encoder *encoder;
4953 bool has_vga = false;
4954 bool is_sdv = false;
4955 u32 tmp;
4956
4957 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4958 switch (encoder->type) {
4959 case INTEL_OUTPUT_ANALOG:
4960 has_vga = true;
4961 break;
4962 }
4963 }
4964
4965 if (!has_vga)
4966 return;
4967
4968 mutex_lock(&dev_priv->dpio_lock);
4969
4970 /* XXX: Rip out SDV support once Haswell ships for real. */
4971 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4972 is_sdv = true;
4973
4974 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4975 tmp &= ~SBI_SSCCTL_DISABLE;
4976 tmp |= SBI_SSCCTL_PATHALT;
4977 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4978
4979 udelay(24);
4980
4981 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4982 tmp &= ~SBI_SSCCTL_PATHALT;
4983 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4984
4985 if (!is_sdv) {
4986 tmp = I915_READ(SOUTH_CHICKEN2);
4987 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4988 I915_WRITE(SOUTH_CHICKEN2, tmp);
4989
4990 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4991 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4992 DRM_ERROR("FDI mPHY reset assert timeout\n");
4993
4994 tmp = I915_READ(SOUTH_CHICKEN2);
4995 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4996 I915_WRITE(SOUTH_CHICKEN2, tmp);
4997
4998 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4999 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5000 100))
5001 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5002 }
5003
5004 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5005 tmp &= ~(0xFF << 24);
5006 tmp |= (0x12 << 24);
5007 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5008
5009 if (!is_sdv) {
5010 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
5011 tmp &= ~(0x3 << 6);
5012 tmp |= (1 << 6) | (1 << 0);
5013 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
5014 }
5015
5016 if (is_sdv) {
5017 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5018 tmp |= 0x7FFF;
5019 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5020 }
5021
5022 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5023 tmp |= (1 << 11);
5024 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5025
5026 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5027 tmp |= (1 << 11);
5028 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5029
5030 if (is_sdv) {
5031 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5032 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5033 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5034
5035 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5036 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5037 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5038
5039 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5040 tmp |= (0x3F << 8);
5041 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5042
5043 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5044 tmp |= (0x3F << 8);
5045 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5046 }
5047
5048 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5049 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5050 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5051
5052 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5053 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5054 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5055
5056 if (!is_sdv) {
5057 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5058 tmp &= ~(7 << 13);
5059 tmp |= (5 << 13);
5060 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5061
5062 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5063 tmp &= ~(7 << 13);
5064 tmp |= (5 << 13);
5065 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5066 }
5067
5068 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5069 tmp &= ~0xFF;
5070 tmp |= 0x1C;
5071 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5072
5073 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5074 tmp &= ~0xFF;
5075 tmp |= 0x1C;
5076 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5077
5078 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5079 tmp &= ~(0xFF << 16);
5080 tmp |= (0x1C << 16);
5081 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5082
5083 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5084 tmp &= ~(0xFF << 16);
5085 tmp |= (0x1C << 16);
5086 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5087
5088 if (!is_sdv) {
5089 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5090 tmp |= (1 << 27);
5091 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5092
5093 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5094 tmp |= (1 << 27);
5095 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5096
5097 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5098 tmp &= ~(0xF << 28);
5099 tmp |= (4 << 28);
5100 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5101
5102 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5103 tmp &= ~(0xF << 28);
5104 tmp |= (4 << 28);
5105 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5106 }
5107
5108 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5109 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5110 tmp |= SBI_DBUFF0_ENABLE;
5111 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5112
5113 mutex_unlock(&dev_priv->dpio_lock);
5114 }
5115
5116 /*
5117 * Initialize reference clocks when the driver loads
5118 */
5119 void intel_init_pch_refclk(struct drm_device *dev)
5120 {
5121 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5122 ironlake_init_pch_refclk(dev);
5123 else if (HAS_PCH_LPT(dev))
5124 lpt_init_pch_refclk(dev);
5125 }
5126
5127 static int ironlake_get_refclk(struct drm_crtc *crtc)
5128 {
5129 struct drm_device *dev = crtc->dev;
5130 struct drm_i915_private *dev_priv = dev->dev_private;
5131 struct intel_encoder *encoder;
5132 struct intel_encoder *edp_encoder = NULL;
5133 int num_connectors = 0;
5134 bool is_lvds = false;
5135
5136 for_each_encoder_on_crtc(dev, crtc, encoder) {
5137 switch (encoder->type) {
5138 case INTEL_OUTPUT_LVDS:
5139 is_lvds = true;
5140 break;
5141 case INTEL_OUTPUT_EDP:
5142 edp_encoder = encoder;
5143 break;
5144 }
5145 num_connectors++;
5146 }
5147
5148 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5149 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5150 dev_priv->lvds_ssc_freq);
5151 return dev_priv->lvds_ssc_freq * 1000;
5152 }
5153
5154 return 120000;
5155 }
5156
5157 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5158 struct drm_display_mode *adjusted_mode,
5159 bool dither)
5160 {
5161 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5163 int pipe = intel_crtc->pipe;
5164 uint32_t val;
5165
5166 val = I915_READ(PIPECONF(pipe));
5167
5168 val &= ~PIPECONF_BPC_MASK;
5169 switch (intel_crtc->config.pipe_bpp) {
5170 case 18:
5171 val |= PIPECONF_6BPC;
5172 break;
5173 case 24:
5174 val |= PIPECONF_8BPC;
5175 break;
5176 case 30:
5177 val |= PIPECONF_10BPC;
5178 break;
5179 case 36:
5180 val |= PIPECONF_12BPC;
5181 break;
5182 default:
5183 /* Case prevented by intel_choose_pipe_bpp_dither. */
5184 BUG();
5185 }
5186
5187 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5188 if (dither)
5189 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5190
5191 val &= ~PIPECONF_INTERLACE_MASK;
5192 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5193 val |= PIPECONF_INTERLACED_ILK;
5194 else
5195 val |= PIPECONF_PROGRESSIVE;
5196
5197 if (intel_crtc->config.limited_color_range)
5198 val |= PIPECONF_COLOR_RANGE_SELECT;
5199 else
5200 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5201
5202 I915_WRITE(PIPECONF(pipe), val);
5203 POSTING_READ(PIPECONF(pipe));
5204 }
5205
5206 /*
5207 * Set up the pipe CSC unit.
5208 *
5209 * Currently only full range RGB to limited range RGB conversion
5210 * is supported, but eventually this should handle various
5211 * RGB<->YCbCr scenarios as well.
5212 */
5213 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5214 {
5215 struct drm_device *dev = crtc->dev;
5216 struct drm_i915_private *dev_priv = dev->dev_private;
5217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5218 int pipe = intel_crtc->pipe;
5219 uint16_t coeff = 0x7800; /* 1.0 */
5220
5221 /*
5222 * TODO: Check what kind of values actually come out of the pipe
5223 * with these coeff/postoff values and adjust to get the best
5224 * accuracy. Perhaps we even need to take the bpc value into
5225 * consideration.
5226 */
5227
5228 if (intel_crtc->config.limited_color_range)
5229 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5230
5231 /*
5232 * GY/GU and RY/RU should be the other way around according
5233 * to BSpec, but reality doesn't agree. Just set them up in
5234 * a way that results in the correct picture.
5235 */
5236 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5237 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5238
5239 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5240 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5241
5242 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5243 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5244
5245 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5246 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5247 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5248
5249 if (INTEL_INFO(dev)->gen > 6) {
5250 uint16_t postoff = 0;
5251
5252 if (intel_crtc->config.limited_color_range)
5253 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5254
5255 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5256 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5257 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5258
5259 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5260 } else {
5261 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5262
5263 if (intel_crtc->config.limited_color_range)
5264 mode |= CSC_BLACK_SCREEN_OFFSET;
5265
5266 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5267 }
5268 }
5269
5270 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5271 struct drm_display_mode *adjusted_mode,
5272 bool dither)
5273 {
5274 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5276 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5277 uint32_t val;
5278
5279 val = I915_READ(PIPECONF(cpu_transcoder));
5280
5281 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5282 if (dither)
5283 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5284
5285 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5286 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5287 val |= PIPECONF_INTERLACED_ILK;
5288 else
5289 val |= PIPECONF_PROGRESSIVE;
5290
5291 I915_WRITE(PIPECONF(cpu_transcoder), val);
5292 POSTING_READ(PIPECONF(cpu_transcoder));
5293 }
5294
5295 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5296 struct drm_display_mode *adjusted_mode,
5297 intel_clock_t *clock,
5298 bool *has_reduced_clock,
5299 intel_clock_t *reduced_clock)
5300 {
5301 struct drm_device *dev = crtc->dev;
5302 struct drm_i915_private *dev_priv = dev->dev_private;
5303 struct intel_encoder *intel_encoder;
5304 int refclk;
5305 const intel_limit_t *limit;
5306 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5307
5308 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5309 switch (intel_encoder->type) {
5310 case INTEL_OUTPUT_LVDS:
5311 is_lvds = true;
5312 break;
5313 case INTEL_OUTPUT_SDVO:
5314 case INTEL_OUTPUT_HDMI:
5315 is_sdvo = true;
5316 if (intel_encoder->needs_tv_clock)
5317 is_tv = true;
5318 break;
5319 case INTEL_OUTPUT_TVOUT:
5320 is_tv = true;
5321 break;
5322 }
5323 }
5324
5325 refclk = ironlake_get_refclk(crtc);
5326
5327 /*
5328 * Returns a set of divisors for the desired target clock with the given
5329 * refclk, or FALSE. The returned values represent the clock equation:
5330 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5331 */
5332 limit = intel_limit(crtc, refclk);
5333 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5334 clock);
5335 if (!ret)
5336 return false;
5337
5338 if (is_lvds && dev_priv->lvds_downclock_avail) {
5339 /*
5340 * Ensure we match the reduced clock's P to the target clock.
5341 * If the clocks don't match, we can't switch the display clock
5342 * by using the FP0/FP1. In such case we will disable the LVDS
5343 * downclock feature.
5344 */
5345 *has_reduced_clock = limit->find_pll(limit, crtc,
5346 dev_priv->lvds_downclock,
5347 refclk,
5348 clock,
5349 reduced_clock);
5350 }
5351
5352 if (is_sdvo && is_tv)
5353 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5354
5355 return true;
5356 }
5357
5358 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5359 {
5360 struct drm_i915_private *dev_priv = dev->dev_private;
5361 uint32_t temp;
5362
5363 temp = I915_READ(SOUTH_CHICKEN1);
5364 if (temp & FDI_BC_BIFURCATION_SELECT)
5365 return;
5366
5367 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5368 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5369
5370 temp |= FDI_BC_BIFURCATION_SELECT;
5371 DRM_DEBUG_KMS("enabling fdi C rx\n");
5372 I915_WRITE(SOUTH_CHICKEN1, temp);
5373 POSTING_READ(SOUTH_CHICKEN1);
5374 }
5375
5376 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5377 {
5378 struct drm_device *dev = intel_crtc->base.dev;
5379 struct drm_i915_private *dev_priv = dev->dev_private;
5380 struct intel_crtc *pipe_B_crtc =
5381 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5382
5383 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5384 intel_crtc->pipe, intel_crtc->fdi_lanes);
5385 if (intel_crtc->fdi_lanes > 4) {
5386 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5387 intel_crtc->pipe, intel_crtc->fdi_lanes);
5388 /* Clamp lanes to avoid programming the hw with bogus values. */
5389 intel_crtc->fdi_lanes = 4;
5390
5391 return false;
5392 }
5393
5394 if (INTEL_INFO(dev)->num_pipes == 2)
5395 return true;
5396
5397 switch (intel_crtc->pipe) {
5398 case PIPE_A:
5399 return true;
5400 case PIPE_B:
5401 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5402 intel_crtc->fdi_lanes > 2) {
5403 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5404 intel_crtc->pipe, intel_crtc->fdi_lanes);
5405 /* Clamp lanes to avoid programming the hw with bogus values. */
5406 intel_crtc->fdi_lanes = 2;
5407
5408 return false;
5409 }
5410
5411 if (intel_crtc->fdi_lanes > 2)
5412 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5413 else
5414 cpt_enable_fdi_bc_bifurcation(dev);
5415
5416 return true;
5417 case PIPE_C:
5418 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5419 if (intel_crtc->fdi_lanes > 2) {
5420 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5421 intel_crtc->pipe, intel_crtc->fdi_lanes);
5422 /* Clamp lanes to avoid programming the hw with bogus values. */
5423 intel_crtc->fdi_lanes = 2;
5424
5425 return false;
5426 }
5427 } else {
5428 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5429 return false;
5430 }
5431
5432 cpt_enable_fdi_bc_bifurcation(dev);
5433
5434 return true;
5435 default:
5436 BUG();
5437 }
5438 }
5439
5440 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5441 {
5442 /*
5443 * Account for spread spectrum to avoid
5444 * oversubscribing the link. Max center spread
5445 * is 2.5%; use 5% for safety's sake.
5446 */
5447 u32 bps = target_clock * bpp * 21 / 20;
5448 return bps / (link_bw * 8) + 1;
5449 }
5450
5451 static void ironlake_set_m_n(struct drm_crtc *crtc)
5452 {
5453 struct drm_device *dev = crtc->dev;
5454 struct drm_i915_private *dev_priv = dev->dev_private;
5455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5456 struct drm_display_mode *adjusted_mode =
5457 &intel_crtc->config.adjusted_mode;
5458 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5459 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5460 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5461 struct intel_link_m_n m_n = {0};
5462 int target_clock, lane, link_bw;
5463 bool is_dp = false, is_cpu_edp = false;
5464
5465 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5466 switch (intel_encoder->type) {
5467 case INTEL_OUTPUT_DISPLAYPORT:
5468 is_dp = true;
5469 break;
5470 case INTEL_OUTPUT_EDP:
5471 is_dp = true;
5472 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5473 is_cpu_edp = true;
5474 edp_encoder = intel_encoder;
5475 break;
5476 }
5477 }
5478
5479 /* FDI link */
5480 lane = 0;
5481 /* CPU eDP doesn't require FDI link, so just set DP M/N
5482 according to current link config */
5483 if (is_cpu_edp) {
5484 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5485 } else {
5486 /* FDI is a binary signal running at ~2.7GHz, encoding
5487 * each output octet as 10 bits. The actual frequency
5488 * is stored as a divider into a 100MHz clock, and the
5489 * mode pixel clock is stored in units of 1KHz.
5490 * Hence the bw of each lane in terms of the mode signal
5491 * is:
5492 */
5493 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5494 }
5495
5496 /* [e]DP over FDI requires target mode clock instead of link clock. */
5497 if (edp_encoder)
5498 target_clock = intel_edp_target_clock(edp_encoder, mode);
5499 else if (is_dp)
5500 target_clock = mode->clock;
5501 else
5502 target_clock = adjusted_mode->clock;
5503
5504 if (!lane)
5505 lane = ironlake_get_lanes_required(target_clock, link_bw,
5506 intel_crtc->config.pipe_bpp);
5507
5508 intel_crtc->fdi_lanes = lane;
5509
5510 if (intel_crtc->config.pixel_multiplier > 1)
5511 link_bw *= intel_crtc->config.pixel_multiplier;
5512 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5513 link_bw, &m_n);
5514
5515 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5516 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5517 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5518 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5519 }
5520
5521 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5522 intel_clock_t *clock, u32 fp)
5523 {
5524 struct drm_crtc *crtc = &intel_crtc->base;
5525 struct drm_device *dev = crtc->dev;
5526 struct drm_i915_private *dev_priv = dev->dev_private;
5527 struct intel_encoder *intel_encoder;
5528 uint32_t dpll;
5529 int factor, num_connectors = 0;
5530 bool is_lvds = false, is_sdvo = false, is_tv = false;
5531 bool is_dp = false, is_cpu_edp = false;
5532
5533 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5534 switch (intel_encoder->type) {
5535 case INTEL_OUTPUT_LVDS:
5536 is_lvds = true;
5537 break;
5538 case INTEL_OUTPUT_SDVO:
5539 case INTEL_OUTPUT_HDMI:
5540 is_sdvo = true;
5541 if (intel_encoder->needs_tv_clock)
5542 is_tv = true;
5543 break;
5544 case INTEL_OUTPUT_TVOUT:
5545 is_tv = true;
5546 break;
5547 case INTEL_OUTPUT_DISPLAYPORT:
5548 is_dp = true;
5549 break;
5550 case INTEL_OUTPUT_EDP:
5551 is_dp = true;
5552 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5553 is_cpu_edp = true;
5554 break;
5555 }
5556
5557 num_connectors++;
5558 }
5559
5560 /* Enable autotuning of the PLL clock (if permissible) */
5561 factor = 21;
5562 if (is_lvds) {
5563 if ((intel_panel_use_ssc(dev_priv) &&
5564 dev_priv->lvds_ssc_freq == 100) ||
5565 intel_is_dual_link_lvds(dev))
5566 factor = 25;
5567 } else if (is_sdvo && is_tv)
5568 factor = 20;
5569
5570 if (clock->m < factor * clock->n)
5571 fp |= FP_CB_TUNE;
5572
5573 dpll = 0;
5574
5575 if (is_lvds)
5576 dpll |= DPLLB_MODE_LVDS;
5577 else
5578 dpll |= DPLLB_MODE_DAC_SERIAL;
5579 if (is_sdvo) {
5580 if (intel_crtc->config.pixel_multiplier > 1) {
5581 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5582 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5583 }
5584 dpll |= DPLL_DVO_HIGH_SPEED;
5585 }
5586 if (is_dp && !is_cpu_edp)
5587 dpll |= DPLL_DVO_HIGH_SPEED;
5588
5589 /* compute bitmask from p1 value */
5590 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5591 /* also FPA1 */
5592 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5593
5594 switch (clock->p2) {
5595 case 5:
5596 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5597 break;
5598 case 7:
5599 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5600 break;
5601 case 10:
5602 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5603 break;
5604 case 14:
5605 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5606 break;
5607 }
5608
5609 if (is_sdvo && is_tv)
5610 dpll |= PLL_REF_INPUT_TVCLKINBC;
5611 else if (is_tv)
5612 /* XXX: just matching BIOS for now */
5613 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5614 dpll |= 3;
5615 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5616 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5617 else
5618 dpll |= PLL_REF_INPUT_DREFCLK;
5619
5620 return dpll;
5621 }
5622
5623 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5624 int x, int y,
5625 struct drm_framebuffer *fb)
5626 {
5627 struct drm_device *dev = crtc->dev;
5628 struct drm_i915_private *dev_priv = dev->dev_private;
5629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5630 struct drm_display_mode *adjusted_mode =
5631 &intel_crtc->config.adjusted_mode;
5632 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5633 int pipe = intel_crtc->pipe;
5634 int plane = intel_crtc->plane;
5635 int num_connectors = 0;
5636 intel_clock_t clock, reduced_clock;
5637 u32 dpll, fp = 0, fp2 = 0;
5638 bool ok, has_reduced_clock = false;
5639 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5640 struct intel_encoder *encoder;
5641 int ret;
5642 bool dither, fdi_config_ok;
5643
5644 for_each_encoder_on_crtc(dev, crtc, encoder) {
5645 switch (encoder->type) {
5646 case INTEL_OUTPUT_LVDS:
5647 is_lvds = true;
5648 break;
5649 case INTEL_OUTPUT_DISPLAYPORT:
5650 is_dp = true;
5651 break;
5652 case INTEL_OUTPUT_EDP:
5653 is_dp = true;
5654 if (!intel_encoder_is_pch_edp(&encoder->base))
5655 is_cpu_edp = true;
5656 break;
5657 }
5658
5659 num_connectors++;
5660 }
5661
5662 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5663 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5664
5665 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5666 &has_reduced_clock, &reduced_clock);
5667 if (!ok) {
5668 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5669 return -EINVAL;
5670 }
5671
5672 /* Ensure that the cursor is valid for the new mode before changing... */
5673 intel_crtc_update_cursor(crtc, true);
5674
5675 /* determine panel color depth */
5676 dither = intel_choose_pipe_bpp_dither(crtc, fb,
5677 &intel_crtc->config.pipe_bpp,
5678 adjusted_mode);
5679 intel_crtc->config.dither = dither;
5680 if (is_lvds && dev_priv->lvds_dither)
5681 dither = true;
5682
5683 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5684 if (has_reduced_clock)
5685 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5686 reduced_clock.m2;
5687
5688 dpll = ironlake_compute_dpll(intel_crtc, &clock, fp);
5689
5690 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5691 drm_mode_debug_printmodeline(mode);
5692
5693 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5694 if (!is_cpu_edp) {
5695 struct intel_pch_pll *pll;
5696
5697 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5698 if (pll == NULL) {
5699 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5700 pipe);
5701 return -EINVAL;
5702 }
5703 } else
5704 intel_put_pch_pll(intel_crtc);
5705
5706 if (is_dp && !is_cpu_edp)
5707 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5708
5709 for_each_encoder_on_crtc(dev, crtc, encoder)
5710 if (encoder->pre_pll_enable)
5711 encoder->pre_pll_enable(encoder);
5712
5713 if (intel_crtc->pch_pll) {
5714 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5715
5716 /* Wait for the clocks to stabilize. */
5717 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5718 udelay(150);
5719
5720 /* The pixel multiplier can only be updated once the
5721 * DPLL is enabled and the clocks are stable.
5722 *
5723 * So write it again.
5724 */
5725 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5726 }
5727
5728 intel_crtc->lowfreq_avail = false;
5729 if (intel_crtc->pch_pll) {
5730 if (is_lvds && has_reduced_clock && i915_powersave) {
5731 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5732 intel_crtc->lowfreq_avail = true;
5733 } else {
5734 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5735 }
5736 }
5737
5738 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5739
5740 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5741 * ironlake_check_fdi_lanes. */
5742 ironlake_set_m_n(crtc);
5743
5744 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5745
5746 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5747
5748 intel_wait_for_vblank(dev, pipe);
5749
5750 /* Set up the display plane register */
5751 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5752 POSTING_READ(DSPCNTR(plane));
5753
5754 ret = intel_pipe_set_base(crtc, x, y, fb);
5755
5756 intel_update_watermarks(dev);
5757
5758 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5759
5760 return fdi_config_ok ? ret : -EINVAL;
5761 }
5762
5763 static void haswell_modeset_global_resources(struct drm_device *dev)
5764 {
5765 struct drm_i915_private *dev_priv = dev->dev_private;
5766 bool enable = false;
5767 struct intel_crtc *crtc;
5768 struct intel_encoder *encoder;
5769
5770 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5771 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5772 enable = true;
5773 /* XXX: Should check for edp transcoder here, but thanks to init
5774 * sequence that's not yet available. Just in case desktop eDP
5775 * on PORT D is possible on haswell, too. */
5776 }
5777
5778 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5779 base.head) {
5780 if (encoder->type != INTEL_OUTPUT_EDP &&
5781 encoder->connectors_active)
5782 enable = true;
5783 }
5784
5785 /* Even the eDP panel fitter is outside the always-on well. */
5786 if (dev_priv->pch_pf_size)
5787 enable = true;
5788
5789 intel_set_power_well(dev, enable);
5790 }
5791
5792 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5793 int x, int y,
5794 struct drm_framebuffer *fb)
5795 {
5796 struct drm_device *dev = crtc->dev;
5797 struct drm_i915_private *dev_priv = dev->dev_private;
5798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5799 struct drm_display_mode *adjusted_mode =
5800 &intel_crtc->config.adjusted_mode;
5801 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5802 int pipe = intel_crtc->pipe;
5803 int plane = intel_crtc->plane;
5804 int num_connectors = 0;
5805 bool is_dp = false, is_cpu_edp = false;
5806 struct intel_encoder *encoder;
5807 int ret;
5808 bool dither;
5809
5810 for_each_encoder_on_crtc(dev, crtc, encoder) {
5811 switch (encoder->type) {
5812 case INTEL_OUTPUT_DISPLAYPORT:
5813 is_dp = true;
5814 break;
5815 case INTEL_OUTPUT_EDP:
5816 is_dp = true;
5817 if (!intel_encoder_is_pch_edp(&encoder->base))
5818 is_cpu_edp = true;
5819 break;
5820 }
5821
5822 num_connectors++;
5823 }
5824
5825 /* We are not sure yet this won't happen. */
5826 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5827 INTEL_PCH_TYPE(dev));
5828
5829 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5830 num_connectors, pipe_name(pipe));
5831
5832 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5833 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5834
5835 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5836
5837 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5838 return -EINVAL;
5839
5840 /* Ensure that the cursor is valid for the new mode before changing... */
5841 intel_crtc_update_cursor(crtc, true);
5842
5843 /* determine panel color depth */
5844 dither = intel_choose_pipe_bpp_dither(crtc, fb,
5845 &intel_crtc->config.pipe_bpp,
5846 adjusted_mode);
5847 intel_crtc->config.dither = dither;
5848
5849 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5850 drm_mode_debug_printmodeline(mode);
5851
5852 if (is_dp && !is_cpu_edp)
5853 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5854
5855 intel_crtc->lowfreq_avail = false;
5856
5857 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5858
5859 if (!is_dp || is_cpu_edp)
5860 ironlake_set_m_n(crtc);
5861
5862 haswell_set_pipeconf(crtc, adjusted_mode, dither);
5863
5864 intel_set_pipe_csc(crtc);
5865
5866 /* Set up the display plane register */
5867 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5868 POSTING_READ(DSPCNTR(plane));
5869
5870 ret = intel_pipe_set_base(crtc, x, y, fb);
5871
5872 intel_update_watermarks(dev);
5873
5874 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5875
5876 return ret;
5877 }
5878
5879 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5880 int x, int y,
5881 struct drm_framebuffer *fb)
5882 {
5883 struct drm_device *dev = crtc->dev;
5884 struct drm_i915_private *dev_priv = dev->dev_private;
5885 struct drm_encoder_helper_funcs *encoder_funcs;
5886 struct intel_encoder *encoder;
5887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5888 struct drm_display_mode *adjusted_mode =
5889 &intel_crtc->config.adjusted_mode;
5890 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5891 int pipe = intel_crtc->pipe;
5892 int ret;
5893
5894 if (IS_HASWELL(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5895 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5896 else
5897 intel_crtc->cpu_transcoder = pipe;
5898
5899 drm_vblank_pre_modeset(dev, pipe);
5900
5901 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5902
5903 drm_vblank_post_modeset(dev, pipe);
5904
5905 if (ret != 0)
5906 return ret;
5907
5908 for_each_encoder_on_crtc(dev, crtc, encoder) {
5909 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5910 encoder->base.base.id,
5911 drm_get_encoder_name(&encoder->base),
5912 mode->base.id, mode->name);
5913 if (encoder->mode_set) {
5914 encoder->mode_set(encoder);
5915 } else {
5916 encoder_funcs = encoder->base.helper_private;
5917 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5918 }
5919 }
5920
5921 return 0;
5922 }
5923
5924 static bool intel_eld_uptodate(struct drm_connector *connector,
5925 int reg_eldv, uint32_t bits_eldv,
5926 int reg_elda, uint32_t bits_elda,
5927 int reg_edid)
5928 {
5929 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5930 uint8_t *eld = connector->eld;
5931 uint32_t i;
5932
5933 i = I915_READ(reg_eldv);
5934 i &= bits_eldv;
5935
5936 if (!eld[0])
5937 return !i;
5938
5939 if (!i)
5940 return false;
5941
5942 i = I915_READ(reg_elda);
5943 i &= ~bits_elda;
5944 I915_WRITE(reg_elda, i);
5945
5946 for (i = 0; i < eld[2]; i++)
5947 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5948 return false;
5949
5950 return true;
5951 }
5952
5953 static void g4x_write_eld(struct drm_connector *connector,
5954 struct drm_crtc *crtc)
5955 {
5956 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5957 uint8_t *eld = connector->eld;
5958 uint32_t eldv;
5959 uint32_t len;
5960 uint32_t i;
5961
5962 i = I915_READ(G4X_AUD_VID_DID);
5963
5964 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5965 eldv = G4X_ELDV_DEVCL_DEVBLC;
5966 else
5967 eldv = G4X_ELDV_DEVCTG;
5968
5969 if (intel_eld_uptodate(connector,
5970 G4X_AUD_CNTL_ST, eldv,
5971 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5972 G4X_HDMIW_HDMIEDID))
5973 return;
5974
5975 i = I915_READ(G4X_AUD_CNTL_ST);
5976 i &= ~(eldv | G4X_ELD_ADDR);
5977 len = (i >> 9) & 0x1f; /* ELD buffer size */
5978 I915_WRITE(G4X_AUD_CNTL_ST, i);
5979
5980 if (!eld[0])
5981 return;
5982
5983 len = min_t(uint8_t, eld[2], len);
5984 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5985 for (i = 0; i < len; i++)
5986 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5987
5988 i = I915_READ(G4X_AUD_CNTL_ST);
5989 i |= eldv;
5990 I915_WRITE(G4X_AUD_CNTL_ST, i);
5991 }
5992
5993 static void haswell_write_eld(struct drm_connector *connector,
5994 struct drm_crtc *crtc)
5995 {
5996 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5997 uint8_t *eld = connector->eld;
5998 struct drm_device *dev = crtc->dev;
5999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6000 uint32_t eldv;
6001 uint32_t i;
6002 int len;
6003 int pipe = to_intel_crtc(crtc)->pipe;
6004 int tmp;
6005
6006 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6007 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6008 int aud_config = HSW_AUD_CFG(pipe);
6009 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6010
6011
6012 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6013
6014 /* Audio output enable */
6015 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6016 tmp = I915_READ(aud_cntrl_st2);
6017 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6018 I915_WRITE(aud_cntrl_st2, tmp);
6019
6020 /* Wait for 1 vertical blank */
6021 intel_wait_for_vblank(dev, pipe);
6022
6023 /* Set ELD valid state */
6024 tmp = I915_READ(aud_cntrl_st2);
6025 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6026 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6027 I915_WRITE(aud_cntrl_st2, tmp);
6028 tmp = I915_READ(aud_cntrl_st2);
6029 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6030
6031 /* Enable HDMI mode */
6032 tmp = I915_READ(aud_config);
6033 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6034 /* clear N_programing_enable and N_value_index */
6035 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6036 I915_WRITE(aud_config, tmp);
6037
6038 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6039
6040 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6041 intel_crtc->eld_vld = true;
6042
6043 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6044 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6045 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6046 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6047 } else
6048 I915_WRITE(aud_config, 0);
6049
6050 if (intel_eld_uptodate(connector,
6051 aud_cntrl_st2, eldv,
6052 aud_cntl_st, IBX_ELD_ADDRESS,
6053 hdmiw_hdmiedid))
6054 return;
6055
6056 i = I915_READ(aud_cntrl_st2);
6057 i &= ~eldv;
6058 I915_WRITE(aud_cntrl_st2, i);
6059
6060 if (!eld[0])
6061 return;
6062
6063 i = I915_READ(aud_cntl_st);
6064 i &= ~IBX_ELD_ADDRESS;
6065 I915_WRITE(aud_cntl_st, i);
6066 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6067 DRM_DEBUG_DRIVER("port num:%d\n", i);
6068
6069 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6070 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6071 for (i = 0; i < len; i++)
6072 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6073
6074 i = I915_READ(aud_cntrl_st2);
6075 i |= eldv;
6076 I915_WRITE(aud_cntrl_st2, i);
6077
6078 }
6079
6080 static void ironlake_write_eld(struct drm_connector *connector,
6081 struct drm_crtc *crtc)
6082 {
6083 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6084 uint8_t *eld = connector->eld;
6085 uint32_t eldv;
6086 uint32_t i;
6087 int len;
6088 int hdmiw_hdmiedid;
6089 int aud_config;
6090 int aud_cntl_st;
6091 int aud_cntrl_st2;
6092 int pipe = to_intel_crtc(crtc)->pipe;
6093
6094 if (HAS_PCH_IBX(connector->dev)) {
6095 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6096 aud_config = IBX_AUD_CFG(pipe);
6097 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6098 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6099 } else {
6100 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6101 aud_config = CPT_AUD_CFG(pipe);
6102 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6103 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6104 }
6105
6106 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6107
6108 i = I915_READ(aud_cntl_st);
6109 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6110 if (!i) {
6111 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6112 /* operate blindly on all ports */
6113 eldv = IBX_ELD_VALIDB;
6114 eldv |= IBX_ELD_VALIDB << 4;
6115 eldv |= IBX_ELD_VALIDB << 8;
6116 } else {
6117 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6118 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6119 }
6120
6121 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6122 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6123 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6124 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6125 } else
6126 I915_WRITE(aud_config, 0);
6127
6128 if (intel_eld_uptodate(connector,
6129 aud_cntrl_st2, eldv,
6130 aud_cntl_st, IBX_ELD_ADDRESS,
6131 hdmiw_hdmiedid))
6132 return;
6133
6134 i = I915_READ(aud_cntrl_st2);
6135 i &= ~eldv;
6136 I915_WRITE(aud_cntrl_st2, i);
6137
6138 if (!eld[0])
6139 return;
6140
6141 i = I915_READ(aud_cntl_st);
6142 i &= ~IBX_ELD_ADDRESS;
6143 I915_WRITE(aud_cntl_st, i);
6144
6145 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6146 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6147 for (i = 0; i < len; i++)
6148 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6149
6150 i = I915_READ(aud_cntrl_st2);
6151 i |= eldv;
6152 I915_WRITE(aud_cntrl_st2, i);
6153 }
6154
6155 void intel_write_eld(struct drm_encoder *encoder,
6156 struct drm_display_mode *mode)
6157 {
6158 struct drm_crtc *crtc = encoder->crtc;
6159 struct drm_connector *connector;
6160 struct drm_device *dev = encoder->dev;
6161 struct drm_i915_private *dev_priv = dev->dev_private;
6162
6163 connector = drm_select_eld(encoder, mode);
6164 if (!connector)
6165 return;
6166
6167 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6168 connector->base.id,
6169 drm_get_connector_name(connector),
6170 connector->encoder->base.id,
6171 drm_get_encoder_name(connector->encoder));
6172
6173 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6174
6175 if (dev_priv->display.write_eld)
6176 dev_priv->display.write_eld(connector, crtc);
6177 }
6178
6179 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6180 void intel_crtc_load_lut(struct drm_crtc *crtc)
6181 {
6182 struct drm_device *dev = crtc->dev;
6183 struct drm_i915_private *dev_priv = dev->dev_private;
6184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6185 int palreg = PALETTE(intel_crtc->pipe);
6186 int i;
6187
6188 /* The clocks have to be on to load the palette. */
6189 if (!crtc->enabled || !intel_crtc->active)
6190 return;
6191
6192 /* use legacy palette for Ironlake */
6193 if (HAS_PCH_SPLIT(dev))
6194 palreg = LGC_PALETTE(intel_crtc->pipe);
6195
6196 for (i = 0; i < 256; i++) {
6197 I915_WRITE(palreg + 4 * i,
6198 (intel_crtc->lut_r[i] << 16) |
6199 (intel_crtc->lut_g[i] << 8) |
6200 intel_crtc->lut_b[i]);
6201 }
6202 }
6203
6204 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6205 {
6206 struct drm_device *dev = crtc->dev;
6207 struct drm_i915_private *dev_priv = dev->dev_private;
6208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6209 bool visible = base != 0;
6210 u32 cntl;
6211
6212 if (intel_crtc->cursor_visible == visible)
6213 return;
6214
6215 cntl = I915_READ(_CURACNTR);
6216 if (visible) {
6217 /* On these chipsets we can only modify the base whilst
6218 * the cursor is disabled.
6219 */
6220 I915_WRITE(_CURABASE, base);
6221
6222 cntl &= ~(CURSOR_FORMAT_MASK);
6223 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6224 cntl |= CURSOR_ENABLE |
6225 CURSOR_GAMMA_ENABLE |
6226 CURSOR_FORMAT_ARGB;
6227 } else
6228 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6229 I915_WRITE(_CURACNTR, cntl);
6230
6231 intel_crtc->cursor_visible = visible;
6232 }
6233
6234 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6235 {
6236 struct drm_device *dev = crtc->dev;
6237 struct drm_i915_private *dev_priv = dev->dev_private;
6238 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6239 int pipe = intel_crtc->pipe;
6240 bool visible = base != 0;
6241
6242 if (intel_crtc->cursor_visible != visible) {
6243 uint32_t cntl = I915_READ(CURCNTR(pipe));
6244 if (base) {
6245 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6246 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6247 cntl |= pipe << 28; /* Connect to correct pipe */
6248 } else {
6249 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6250 cntl |= CURSOR_MODE_DISABLE;
6251 }
6252 I915_WRITE(CURCNTR(pipe), cntl);
6253
6254 intel_crtc->cursor_visible = visible;
6255 }
6256 /* and commit changes on next vblank */
6257 I915_WRITE(CURBASE(pipe), base);
6258 }
6259
6260 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6261 {
6262 struct drm_device *dev = crtc->dev;
6263 struct drm_i915_private *dev_priv = dev->dev_private;
6264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6265 int pipe = intel_crtc->pipe;
6266 bool visible = base != 0;
6267
6268 if (intel_crtc->cursor_visible != visible) {
6269 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6270 if (base) {
6271 cntl &= ~CURSOR_MODE;
6272 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6273 } else {
6274 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6275 cntl |= CURSOR_MODE_DISABLE;
6276 }
6277 if (IS_HASWELL(dev))
6278 cntl |= CURSOR_PIPE_CSC_ENABLE;
6279 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6280
6281 intel_crtc->cursor_visible = visible;
6282 }
6283 /* and commit changes on next vblank */
6284 I915_WRITE(CURBASE_IVB(pipe), base);
6285 }
6286
6287 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6288 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6289 bool on)
6290 {
6291 struct drm_device *dev = crtc->dev;
6292 struct drm_i915_private *dev_priv = dev->dev_private;
6293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6294 int pipe = intel_crtc->pipe;
6295 int x = intel_crtc->cursor_x;
6296 int y = intel_crtc->cursor_y;
6297 u32 base, pos;
6298 bool visible;
6299
6300 pos = 0;
6301
6302 if (on && crtc->enabled && crtc->fb) {
6303 base = intel_crtc->cursor_addr;
6304 if (x > (int) crtc->fb->width)
6305 base = 0;
6306
6307 if (y > (int) crtc->fb->height)
6308 base = 0;
6309 } else
6310 base = 0;
6311
6312 if (x < 0) {
6313 if (x + intel_crtc->cursor_width < 0)
6314 base = 0;
6315
6316 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6317 x = -x;
6318 }
6319 pos |= x << CURSOR_X_SHIFT;
6320
6321 if (y < 0) {
6322 if (y + intel_crtc->cursor_height < 0)
6323 base = 0;
6324
6325 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6326 y = -y;
6327 }
6328 pos |= y << CURSOR_Y_SHIFT;
6329
6330 visible = base != 0;
6331 if (!visible && !intel_crtc->cursor_visible)
6332 return;
6333
6334 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6335 I915_WRITE(CURPOS_IVB(pipe), pos);
6336 ivb_update_cursor(crtc, base);
6337 } else {
6338 I915_WRITE(CURPOS(pipe), pos);
6339 if (IS_845G(dev) || IS_I865G(dev))
6340 i845_update_cursor(crtc, base);
6341 else
6342 i9xx_update_cursor(crtc, base);
6343 }
6344 }
6345
6346 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6347 struct drm_file *file,
6348 uint32_t handle,
6349 uint32_t width, uint32_t height)
6350 {
6351 struct drm_device *dev = crtc->dev;
6352 struct drm_i915_private *dev_priv = dev->dev_private;
6353 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6354 struct drm_i915_gem_object *obj;
6355 uint32_t addr;
6356 int ret;
6357
6358 /* if we want to turn off the cursor ignore width and height */
6359 if (!handle) {
6360 DRM_DEBUG_KMS("cursor off\n");
6361 addr = 0;
6362 obj = NULL;
6363 mutex_lock(&dev->struct_mutex);
6364 goto finish;
6365 }
6366
6367 /* Currently we only support 64x64 cursors */
6368 if (width != 64 || height != 64) {
6369 DRM_ERROR("we currently only support 64x64 cursors\n");
6370 return -EINVAL;
6371 }
6372
6373 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6374 if (&obj->base == NULL)
6375 return -ENOENT;
6376
6377 if (obj->base.size < width * height * 4) {
6378 DRM_ERROR("buffer is to small\n");
6379 ret = -ENOMEM;
6380 goto fail;
6381 }
6382
6383 /* we only need to pin inside GTT if cursor is non-phy */
6384 mutex_lock(&dev->struct_mutex);
6385 if (!dev_priv->info->cursor_needs_physical) {
6386 unsigned alignment;
6387
6388 if (obj->tiling_mode) {
6389 DRM_ERROR("cursor cannot be tiled\n");
6390 ret = -EINVAL;
6391 goto fail_locked;
6392 }
6393
6394 /* Note that the w/a also requires 2 PTE of padding following
6395 * the bo. We currently fill all unused PTE with the shadow
6396 * page and so we should always have valid PTE following the
6397 * cursor preventing the VT-d warning.
6398 */
6399 alignment = 0;
6400 if (need_vtd_wa(dev))
6401 alignment = 64*1024;
6402
6403 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6404 if (ret) {
6405 DRM_ERROR("failed to move cursor bo into the GTT\n");
6406 goto fail_locked;
6407 }
6408
6409 ret = i915_gem_object_put_fence(obj);
6410 if (ret) {
6411 DRM_ERROR("failed to release fence for cursor");
6412 goto fail_unpin;
6413 }
6414
6415 addr = obj->gtt_offset;
6416 } else {
6417 int align = IS_I830(dev) ? 16 * 1024 : 256;
6418 ret = i915_gem_attach_phys_object(dev, obj,
6419 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6420 align);
6421 if (ret) {
6422 DRM_ERROR("failed to attach phys object\n");
6423 goto fail_locked;
6424 }
6425 addr = obj->phys_obj->handle->busaddr;
6426 }
6427
6428 if (IS_GEN2(dev))
6429 I915_WRITE(CURSIZE, (height << 12) | width);
6430
6431 finish:
6432 if (intel_crtc->cursor_bo) {
6433 if (dev_priv->info->cursor_needs_physical) {
6434 if (intel_crtc->cursor_bo != obj)
6435 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6436 } else
6437 i915_gem_object_unpin(intel_crtc->cursor_bo);
6438 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6439 }
6440
6441 mutex_unlock(&dev->struct_mutex);
6442
6443 intel_crtc->cursor_addr = addr;
6444 intel_crtc->cursor_bo = obj;
6445 intel_crtc->cursor_width = width;
6446 intel_crtc->cursor_height = height;
6447
6448 intel_crtc_update_cursor(crtc, true);
6449
6450 return 0;
6451 fail_unpin:
6452 i915_gem_object_unpin(obj);
6453 fail_locked:
6454 mutex_unlock(&dev->struct_mutex);
6455 fail:
6456 drm_gem_object_unreference_unlocked(&obj->base);
6457 return ret;
6458 }
6459
6460 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6461 {
6462 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6463
6464 intel_crtc->cursor_x = x;
6465 intel_crtc->cursor_y = y;
6466
6467 intel_crtc_update_cursor(crtc, true);
6468
6469 return 0;
6470 }
6471
6472 /** Sets the color ramps on behalf of RandR */
6473 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6474 u16 blue, int regno)
6475 {
6476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6477
6478 intel_crtc->lut_r[regno] = red >> 8;
6479 intel_crtc->lut_g[regno] = green >> 8;
6480 intel_crtc->lut_b[regno] = blue >> 8;
6481 }
6482
6483 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6484 u16 *blue, int regno)
6485 {
6486 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6487
6488 *red = intel_crtc->lut_r[regno] << 8;
6489 *green = intel_crtc->lut_g[regno] << 8;
6490 *blue = intel_crtc->lut_b[regno] << 8;
6491 }
6492
6493 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6494 u16 *blue, uint32_t start, uint32_t size)
6495 {
6496 int end = (start + size > 256) ? 256 : start + size, i;
6497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6498
6499 for (i = start; i < end; i++) {
6500 intel_crtc->lut_r[i] = red[i] >> 8;
6501 intel_crtc->lut_g[i] = green[i] >> 8;
6502 intel_crtc->lut_b[i] = blue[i] >> 8;
6503 }
6504
6505 intel_crtc_load_lut(crtc);
6506 }
6507
6508 /* VESA 640x480x72Hz mode to set on the pipe */
6509 static struct drm_display_mode load_detect_mode = {
6510 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6511 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6512 };
6513
6514 static struct drm_framebuffer *
6515 intel_framebuffer_create(struct drm_device *dev,
6516 struct drm_mode_fb_cmd2 *mode_cmd,
6517 struct drm_i915_gem_object *obj)
6518 {
6519 struct intel_framebuffer *intel_fb;
6520 int ret;
6521
6522 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6523 if (!intel_fb) {
6524 drm_gem_object_unreference_unlocked(&obj->base);
6525 return ERR_PTR(-ENOMEM);
6526 }
6527
6528 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6529 if (ret) {
6530 drm_gem_object_unreference_unlocked(&obj->base);
6531 kfree(intel_fb);
6532 return ERR_PTR(ret);
6533 }
6534
6535 return &intel_fb->base;
6536 }
6537
6538 static u32
6539 intel_framebuffer_pitch_for_width(int width, int bpp)
6540 {
6541 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6542 return ALIGN(pitch, 64);
6543 }
6544
6545 static u32
6546 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6547 {
6548 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6549 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6550 }
6551
6552 static struct drm_framebuffer *
6553 intel_framebuffer_create_for_mode(struct drm_device *dev,
6554 struct drm_display_mode *mode,
6555 int depth, int bpp)
6556 {
6557 struct drm_i915_gem_object *obj;
6558 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6559
6560 obj = i915_gem_alloc_object(dev,
6561 intel_framebuffer_size_for_mode(mode, bpp));
6562 if (obj == NULL)
6563 return ERR_PTR(-ENOMEM);
6564
6565 mode_cmd.width = mode->hdisplay;
6566 mode_cmd.height = mode->vdisplay;
6567 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6568 bpp);
6569 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6570
6571 return intel_framebuffer_create(dev, &mode_cmd, obj);
6572 }
6573
6574 static struct drm_framebuffer *
6575 mode_fits_in_fbdev(struct drm_device *dev,
6576 struct drm_display_mode *mode)
6577 {
6578 struct drm_i915_private *dev_priv = dev->dev_private;
6579 struct drm_i915_gem_object *obj;
6580 struct drm_framebuffer *fb;
6581
6582 if (dev_priv->fbdev == NULL)
6583 return NULL;
6584
6585 obj = dev_priv->fbdev->ifb.obj;
6586 if (obj == NULL)
6587 return NULL;
6588
6589 fb = &dev_priv->fbdev->ifb.base;
6590 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6591 fb->bits_per_pixel))
6592 return NULL;
6593
6594 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6595 return NULL;
6596
6597 return fb;
6598 }
6599
6600 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6601 struct drm_display_mode *mode,
6602 struct intel_load_detect_pipe *old)
6603 {
6604 struct intel_crtc *intel_crtc;
6605 struct intel_encoder *intel_encoder =
6606 intel_attached_encoder(connector);
6607 struct drm_crtc *possible_crtc;
6608 struct drm_encoder *encoder = &intel_encoder->base;
6609 struct drm_crtc *crtc = NULL;
6610 struct drm_device *dev = encoder->dev;
6611 struct drm_framebuffer *fb;
6612 int i = -1;
6613
6614 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6615 connector->base.id, drm_get_connector_name(connector),
6616 encoder->base.id, drm_get_encoder_name(encoder));
6617
6618 /*
6619 * Algorithm gets a little messy:
6620 *
6621 * - if the connector already has an assigned crtc, use it (but make
6622 * sure it's on first)
6623 *
6624 * - try to find the first unused crtc that can drive this connector,
6625 * and use that if we find one
6626 */
6627
6628 /* See if we already have a CRTC for this connector */
6629 if (encoder->crtc) {
6630 crtc = encoder->crtc;
6631
6632 mutex_lock(&crtc->mutex);
6633
6634 old->dpms_mode = connector->dpms;
6635 old->load_detect_temp = false;
6636
6637 /* Make sure the crtc and connector are running */
6638 if (connector->dpms != DRM_MODE_DPMS_ON)
6639 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6640
6641 return true;
6642 }
6643
6644 /* Find an unused one (if possible) */
6645 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6646 i++;
6647 if (!(encoder->possible_crtcs & (1 << i)))
6648 continue;
6649 if (!possible_crtc->enabled) {
6650 crtc = possible_crtc;
6651 break;
6652 }
6653 }
6654
6655 /*
6656 * If we didn't find an unused CRTC, don't use any.
6657 */
6658 if (!crtc) {
6659 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6660 return false;
6661 }
6662
6663 mutex_lock(&crtc->mutex);
6664 intel_encoder->new_crtc = to_intel_crtc(crtc);
6665 to_intel_connector(connector)->new_encoder = intel_encoder;
6666
6667 intel_crtc = to_intel_crtc(crtc);
6668 old->dpms_mode = connector->dpms;
6669 old->load_detect_temp = true;
6670 old->release_fb = NULL;
6671
6672 if (!mode)
6673 mode = &load_detect_mode;
6674
6675 /* We need a framebuffer large enough to accommodate all accesses
6676 * that the plane may generate whilst we perform load detection.
6677 * We can not rely on the fbcon either being present (we get called
6678 * during its initialisation to detect all boot displays, or it may
6679 * not even exist) or that it is large enough to satisfy the
6680 * requested mode.
6681 */
6682 fb = mode_fits_in_fbdev(dev, mode);
6683 if (fb == NULL) {
6684 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6685 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6686 old->release_fb = fb;
6687 } else
6688 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6689 if (IS_ERR(fb)) {
6690 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6691 mutex_unlock(&crtc->mutex);
6692 return false;
6693 }
6694
6695 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6696 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6697 if (old->release_fb)
6698 old->release_fb->funcs->destroy(old->release_fb);
6699 mutex_unlock(&crtc->mutex);
6700 return false;
6701 }
6702
6703 /* let the connector get through one full cycle before testing */
6704 intel_wait_for_vblank(dev, intel_crtc->pipe);
6705 return true;
6706 }
6707
6708 void intel_release_load_detect_pipe(struct drm_connector *connector,
6709 struct intel_load_detect_pipe *old)
6710 {
6711 struct intel_encoder *intel_encoder =
6712 intel_attached_encoder(connector);
6713 struct drm_encoder *encoder = &intel_encoder->base;
6714 struct drm_crtc *crtc = encoder->crtc;
6715
6716 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6717 connector->base.id, drm_get_connector_name(connector),
6718 encoder->base.id, drm_get_encoder_name(encoder));
6719
6720 if (old->load_detect_temp) {
6721 to_intel_connector(connector)->new_encoder = NULL;
6722 intel_encoder->new_crtc = NULL;
6723 intel_set_mode(crtc, NULL, 0, 0, NULL);
6724
6725 if (old->release_fb) {
6726 drm_framebuffer_unregister_private(old->release_fb);
6727 drm_framebuffer_unreference(old->release_fb);
6728 }
6729
6730 mutex_unlock(&crtc->mutex);
6731 return;
6732 }
6733
6734 /* Switch crtc and encoder back off if necessary */
6735 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6736 connector->funcs->dpms(connector, old->dpms_mode);
6737
6738 mutex_unlock(&crtc->mutex);
6739 }
6740
6741 /* Returns the clock of the currently programmed mode of the given pipe. */
6742 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6743 {
6744 struct drm_i915_private *dev_priv = dev->dev_private;
6745 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6746 int pipe = intel_crtc->pipe;
6747 u32 dpll = I915_READ(DPLL(pipe));
6748 u32 fp;
6749 intel_clock_t clock;
6750
6751 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6752 fp = I915_READ(FP0(pipe));
6753 else
6754 fp = I915_READ(FP1(pipe));
6755
6756 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6757 if (IS_PINEVIEW(dev)) {
6758 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6759 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6760 } else {
6761 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6762 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6763 }
6764
6765 if (!IS_GEN2(dev)) {
6766 if (IS_PINEVIEW(dev))
6767 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6768 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6769 else
6770 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6771 DPLL_FPA01_P1_POST_DIV_SHIFT);
6772
6773 switch (dpll & DPLL_MODE_MASK) {
6774 case DPLLB_MODE_DAC_SERIAL:
6775 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6776 5 : 10;
6777 break;
6778 case DPLLB_MODE_LVDS:
6779 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6780 7 : 14;
6781 break;
6782 default:
6783 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6784 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6785 return 0;
6786 }
6787
6788 /* XXX: Handle the 100Mhz refclk */
6789 intel_clock(dev, 96000, &clock);
6790 } else {
6791 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6792
6793 if (is_lvds) {
6794 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6795 DPLL_FPA01_P1_POST_DIV_SHIFT);
6796 clock.p2 = 14;
6797
6798 if ((dpll & PLL_REF_INPUT_MASK) ==
6799 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6800 /* XXX: might not be 66MHz */
6801 intel_clock(dev, 66000, &clock);
6802 } else
6803 intel_clock(dev, 48000, &clock);
6804 } else {
6805 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6806 clock.p1 = 2;
6807 else {
6808 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6809 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6810 }
6811 if (dpll & PLL_P2_DIVIDE_BY_4)
6812 clock.p2 = 4;
6813 else
6814 clock.p2 = 2;
6815
6816 intel_clock(dev, 48000, &clock);
6817 }
6818 }
6819
6820 /* XXX: It would be nice to validate the clocks, but we can't reuse
6821 * i830PllIsValid() because it relies on the xf86_config connector
6822 * configuration being accurate, which it isn't necessarily.
6823 */
6824
6825 return clock.dot;
6826 }
6827
6828 /** Returns the currently programmed mode of the given pipe. */
6829 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6830 struct drm_crtc *crtc)
6831 {
6832 struct drm_i915_private *dev_priv = dev->dev_private;
6833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6834 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6835 struct drm_display_mode *mode;
6836 int htot = I915_READ(HTOTAL(cpu_transcoder));
6837 int hsync = I915_READ(HSYNC(cpu_transcoder));
6838 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6839 int vsync = I915_READ(VSYNC(cpu_transcoder));
6840
6841 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6842 if (!mode)
6843 return NULL;
6844
6845 mode->clock = intel_crtc_clock_get(dev, crtc);
6846 mode->hdisplay = (htot & 0xffff) + 1;
6847 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6848 mode->hsync_start = (hsync & 0xffff) + 1;
6849 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6850 mode->vdisplay = (vtot & 0xffff) + 1;
6851 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6852 mode->vsync_start = (vsync & 0xffff) + 1;
6853 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6854
6855 drm_mode_set_name(mode);
6856
6857 return mode;
6858 }
6859
6860 static void intel_increase_pllclock(struct drm_crtc *crtc)
6861 {
6862 struct drm_device *dev = crtc->dev;
6863 drm_i915_private_t *dev_priv = dev->dev_private;
6864 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6865 int pipe = intel_crtc->pipe;
6866 int dpll_reg = DPLL(pipe);
6867 int dpll;
6868
6869 if (HAS_PCH_SPLIT(dev))
6870 return;
6871
6872 if (!dev_priv->lvds_downclock_avail)
6873 return;
6874
6875 dpll = I915_READ(dpll_reg);
6876 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6877 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6878
6879 assert_panel_unlocked(dev_priv, pipe);
6880
6881 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6882 I915_WRITE(dpll_reg, dpll);
6883 intel_wait_for_vblank(dev, pipe);
6884
6885 dpll = I915_READ(dpll_reg);
6886 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6887 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6888 }
6889 }
6890
6891 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6892 {
6893 struct drm_device *dev = crtc->dev;
6894 drm_i915_private_t *dev_priv = dev->dev_private;
6895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6896
6897 if (HAS_PCH_SPLIT(dev))
6898 return;
6899
6900 if (!dev_priv->lvds_downclock_avail)
6901 return;
6902
6903 /*
6904 * Since this is called by a timer, we should never get here in
6905 * the manual case.
6906 */
6907 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6908 int pipe = intel_crtc->pipe;
6909 int dpll_reg = DPLL(pipe);
6910 int dpll;
6911
6912 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6913
6914 assert_panel_unlocked(dev_priv, pipe);
6915
6916 dpll = I915_READ(dpll_reg);
6917 dpll |= DISPLAY_RATE_SELECT_FPA1;
6918 I915_WRITE(dpll_reg, dpll);
6919 intel_wait_for_vblank(dev, pipe);
6920 dpll = I915_READ(dpll_reg);
6921 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6922 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6923 }
6924
6925 }
6926
6927 void intel_mark_busy(struct drm_device *dev)
6928 {
6929 i915_update_gfx_val(dev->dev_private);
6930 }
6931
6932 void intel_mark_idle(struct drm_device *dev)
6933 {
6934 struct drm_crtc *crtc;
6935
6936 if (!i915_powersave)
6937 return;
6938
6939 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6940 if (!crtc->fb)
6941 continue;
6942
6943 intel_decrease_pllclock(crtc);
6944 }
6945 }
6946
6947 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6948 {
6949 struct drm_device *dev = obj->base.dev;
6950 struct drm_crtc *crtc;
6951
6952 if (!i915_powersave)
6953 return;
6954
6955 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6956 if (!crtc->fb)
6957 continue;
6958
6959 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6960 intel_increase_pllclock(crtc);
6961 }
6962 }
6963
6964 static void intel_crtc_destroy(struct drm_crtc *crtc)
6965 {
6966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6967 struct drm_device *dev = crtc->dev;
6968 struct intel_unpin_work *work;
6969 unsigned long flags;
6970
6971 spin_lock_irqsave(&dev->event_lock, flags);
6972 work = intel_crtc->unpin_work;
6973 intel_crtc->unpin_work = NULL;
6974 spin_unlock_irqrestore(&dev->event_lock, flags);
6975
6976 if (work) {
6977 cancel_work_sync(&work->work);
6978 kfree(work);
6979 }
6980
6981 drm_crtc_cleanup(crtc);
6982
6983 kfree(intel_crtc);
6984 }
6985
6986 static void intel_unpin_work_fn(struct work_struct *__work)
6987 {
6988 struct intel_unpin_work *work =
6989 container_of(__work, struct intel_unpin_work, work);
6990 struct drm_device *dev = work->crtc->dev;
6991
6992 mutex_lock(&dev->struct_mutex);
6993 intel_unpin_fb_obj(work->old_fb_obj);
6994 drm_gem_object_unreference(&work->pending_flip_obj->base);
6995 drm_gem_object_unreference(&work->old_fb_obj->base);
6996
6997 intel_update_fbc(dev);
6998 mutex_unlock(&dev->struct_mutex);
6999
7000 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7001 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7002
7003 kfree(work);
7004 }
7005
7006 static void do_intel_finish_page_flip(struct drm_device *dev,
7007 struct drm_crtc *crtc)
7008 {
7009 drm_i915_private_t *dev_priv = dev->dev_private;
7010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7011 struct intel_unpin_work *work;
7012 unsigned long flags;
7013
7014 /* Ignore early vblank irqs */
7015 if (intel_crtc == NULL)
7016 return;
7017
7018 spin_lock_irqsave(&dev->event_lock, flags);
7019 work = intel_crtc->unpin_work;
7020
7021 /* Ensure we don't miss a work->pending update ... */
7022 smp_rmb();
7023
7024 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7025 spin_unlock_irqrestore(&dev->event_lock, flags);
7026 return;
7027 }
7028
7029 /* and that the unpin work is consistent wrt ->pending. */
7030 smp_rmb();
7031
7032 intel_crtc->unpin_work = NULL;
7033
7034 if (work->event)
7035 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7036
7037 drm_vblank_put(dev, intel_crtc->pipe);
7038
7039 spin_unlock_irqrestore(&dev->event_lock, flags);
7040
7041 wake_up_all(&dev_priv->pending_flip_queue);
7042
7043 queue_work(dev_priv->wq, &work->work);
7044
7045 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7046 }
7047
7048 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7049 {
7050 drm_i915_private_t *dev_priv = dev->dev_private;
7051 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7052
7053 do_intel_finish_page_flip(dev, crtc);
7054 }
7055
7056 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7057 {
7058 drm_i915_private_t *dev_priv = dev->dev_private;
7059 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7060
7061 do_intel_finish_page_flip(dev, crtc);
7062 }
7063
7064 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7065 {
7066 drm_i915_private_t *dev_priv = dev->dev_private;
7067 struct intel_crtc *intel_crtc =
7068 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7069 unsigned long flags;
7070
7071 /* NB: An MMIO update of the plane base pointer will also
7072 * generate a page-flip completion irq, i.e. every modeset
7073 * is also accompanied by a spurious intel_prepare_page_flip().
7074 */
7075 spin_lock_irqsave(&dev->event_lock, flags);
7076 if (intel_crtc->unpin_work)
7077 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7078 spin_unlock_irqrestore(&dev->event_lock, flags);
7079 }
7080
7081 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7082 {
7083 /* Ensure that the work item is consistent when activating it ... */
7084 smp_wmb();
7085 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7086 /* and that it is marked active as soon as the irq could fire. */
7087 smp_wmb();
7088 }
7089
7090 static int intel_gen2_queue_flip(struct drm_device *dev,
7091 struct drm_crtc *crtc,
7092 struct drm_framebuffer *fb,
7093 struct drm_i915_gem_object *obj)
7094 {
7095 struct drm_i915_private *dev_priv = dev->dev_private;
7096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7097 u32 flip_mask;
7098 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7099 int ret;
7100
7101 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7102 if (ret)
7103 goto err;
7104
7105 ret = intel_ring_begin(ring, 6);
7106 if (ret)
7107 goto err_unpin;
7108
7109 /* Can't queue multiple flips, so wait for the previous
7110 * one to finish before executing the next.
7111 */
7112 if (intel_crtc->plane)
7113 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7114 else
7115 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7116 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7117 intel_ring_emit(ring, MI_NOOP);
7118 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7119 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7120 intel_ring_emit(ring, fb->pitches[0]);
7121 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7122 intel_ring_emit(ring, 0); /* aux display base address, unused */
7123
7124 intel_mark_page_flip_active(intel_crtc);
7125 intel_ring_advance(ring);
7126 return 0;
7127
7128 err_unpin:
7129 intel_unpin_fb_obj(obj);
7130 err:
7131 return ret;
7132 }
7133
7134 static int intel_gen3_queue_flip(struct drm_device *dev,
7135 struct drm_crtc *crtc,
7136 struct drm_framebuffer *fb,
7137 struct drm_i915_gem_object *obj)
7138 {
7139 struct drm_i915_private *dev_priv = dev->dev_private;
7140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7141 u32 flip_mask;
7142 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7143 int ret;
7144
7145 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7146 if (ret)
7147 goto err;
7148
7149 ret = intel_ring_begin(ring, 6);
7150 if (ret)
7151 goto err_unpin;
7152
7153 if (intel_crtc->plane)
7154 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7155 else
7156 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7157 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7158 intel_ring_emit(ring, MI_NOOP);
7159 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7160 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7161 intel_ring_emit(ring, fb->pitches[0]);
7162 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7163 intel_ring_emit(ring, MI_NOOP);
7164
7165 intel_mark_page_flip_active(intel_crtc);
7166 intel_ring_advance(ring);
7167 return 0;
7168
7169 err_unpin:
7170 intel_unpin_fb_obj(obj);
7171 err:
7172 return ret;
7173 }
7174
7175 static int intel_gen4_queue_flip(struct drm_device *dev,
7176 struct drm_crtc *crtc,
7177 struct drm_framebuffer *fb,
7178 struct drm_i915_gem_object *obj)
7179 {
7180 struct drm_i915_private *dev_priv = dev->dev_private;
7181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7182 uint32_t pf, pipesrc;
7183 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7184 int ret;
7185
7186 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7187 if (ret)
7188 goto err;
7189
7190 ret = intel_ring_begin(ring, 4);
7191 if (ret)
7192 goto err_unpin;
7193
7194 /* i965+ uses the linear or tiled offsets from the
7195 * Display Registers (which do not change across a page-flip)
7196 * so we need only reprogram the base address.
7197 */
7198 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7199 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7200 intel_ring_emit(ring, fb->pitches[0]);
7201 intel_ring_emit(ring,
7202 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7203 obj->tiling_mode);
7204
7205 /* XXX Enabling the panel-fitter across page-flip is so far
7206 * untested on non-native modes, so ignore it for now.
7207 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7208 */
7209 pf = 0;
7210 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7211 intel_ring_emit(ring, pf | pipesrc);
7212
7213 intel_mark_page_flip_active(intel_crtc);
7214 intel_ring_advance(ring);
7215 return 0;
7216
7217 err_unpin:
7218 intel_unpin_fb_obj(obj);
7219 err:
7220 return ret;
7221 }
7222
7223 static int intel_gen6_queue_flip(struct drm_device *dev,
7224 struct drm_crtc *crtc,
7225 struct drm_framebuffer *fb,
7226 struct drm_i915_gem_object *obj)
7227 {
7228 struct drm_i915_private *dev_priv = dev->dev_private;
7229 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7230 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7231 uint32_t pf, pipesrc;
7232 int ret;
7233
7234 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7235 if (ret)
7236 goto err;
7237
7238 ret = intel_ring_begin(ring, 4);
7239 if (ret)
7240 goto err_unpin;
7241
7242 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7243 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7244 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7245 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7246
7247 /* Contrary to the suggestions in the documentation,
7248 * "Enable Panel Fitter" does not seem to be required when page
7249 * flipping with a non-native mode, and worse causes a normal
7250 * modeset to fail.
7251 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7252 */
7253 pf = 0;
7254 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7255 intel_ring_emit(ring, pf | pipesrc);
7256
7257 intel_mark_page_flip_active(intel_crtc);
7258 intel_ring_advance(ring);
7259 return 0;
7260
7261 err_unpin:
7262 intel_unpin_fb_obj(obj);
7263 err:
7264 return ret;
7265 }
7266
7267 /*
7268 * On gen7 we currently use the blit ring because (in early silicon at least)
7269 * the render ring doesn't give us interrpts for page flip completion, which
7270 * means clients will hang after the first flip is queued. Fortunately the
7271 * blit ring generates interrupts properly, so use it instead.
7272 */
7273 static int intel_gen7_queue_flip(struct drm_device *dev,
7274 struct drm_crtc *crtc,
7275 struct drm_framebuffer *fb,
7276 struct drm_i915_gem_object *obj)
7277 {
7278 struct drm_i915_private *dev_priv = dev->dev_private;
7279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7280 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7281 uint32_t plane_bit = 0;
7282 int ret;
7283
7284 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7285 if (ret)
7286 goto err;
7287
7288 switch(intel_crtc->plane) {
7289 case PLANE_A:
7290 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7291 break;
7292 case PLANE_B:
7293 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7294 break;
7295 case PLANE_C:
7296 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7297 break;
7298 default:
7299 WARN_ONCE(1, "unknown plane in flip command\n");
7300 ret = -ENODEV;
7301 goto err_unpin;
7302 }
7303
7304 ret = intel_ring_begin(ring, 4);
7305 if (ret)
7306 goto err_unpin;
7307
7308 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7309 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7310 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7311 intel_ring_emit(ring, (MI_NOOP));
7312
7313 intel_mark_page_flip_active(intel_crtc);
7314 intel_ring_advance(ring);
7315 return 0;
7316
7317 err_unpin:
7318 intel_unpin_fb_obj(obj);
7319 err:
7320 return ret;
7321 }
7322
7323 static int intel_default_queue_flip(struct drm_device *dev,
7324 struct drm_crtc *crtc,
7325 struct drm_framebuffer *fb,
7326 struct drm_i915_gem_object *obj)
7327 {
7328 return -ENODEV;
7329 }
7330
7331 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7332 struct drm_framebuffer *fb,
7333 struct drm_pending_vblank_event *event)
7334 {
7335 struct drm_device *dev = crtc->dev;
7336 struct drm_i915_private *dev_priv = dev->dev_private;
7337 struct drm_framebuffer *old_fb = crtc->fb;
7338 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7340 struct intel_unpin_work *work;
7341 unsigned long flags;
7342 int ret;
7343
7344 /* Can't change pixel format via MI display flips. */
7345 if (fb->pixel_format != crtc->fb->pixel_format)
7346 return -EINVAL;
7347
7348 /*
7349 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7350 * Note that pitch changes could also affect these register.
7351 */
7352 if (INTEL_INFO(dev)->gen > 3 &&
7353 (fb->offsets[0] != crtc->fb->offsets[0] ||
7354 fb->pitches[0] != crtc->fb->pitches[0]))
7355 return -EINVAL;
7356
7357 work = kzalloc(sizeof *work, GFP_KERNEL);
7358 if (work == NULL)
7359 return -ENOMEM;
7360
7361 work->event = event;
7362 work->crtc = crtc;
7363 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7364 INIT_WORK(&work->work, intel_unpin_work_fn);
7365
7366 ret = drm_vblank_get(dev, intel_crtc->pipe);
7367 if (ret)
7368 goto free_work;
7369
7370 /* We borrow the event spin lock for protecting unpin_work */
7371 spin_lock_irqsave(&dev->event_lock, flags);
7372 if (intel_crtc->unpin_work) {
7373 spin_unlock_irqrestore(&dev->event_lock, flags);
7374 kfree(work);
7375 drm_vblank_put(dev, intel_crtc->pipe);
7376
7377 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7378 return -EBUSY;
7379 }
7380 intel_crtc->unpin_work = work;
7381 spin_unlock_irqrestore(&dev->event_lock, flags);
7382
7383 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7384 flush_workqueue(dev_priv->wq);
7385
7386 ret = i915_mutex_lock_interruptible(dev);
7387 if (ret)
7388 goto cleanup;
7389
7390 /* Reference the objects for the scheduled work. */
7391 drm_gem_object_reference(&work->old_fb_obj->base);
7392 drm_gem_object_reference(&obj->base);
7393
7394 crtc->fb = fb;
7395
7396 work->pending_flip_obj = obj;
7397
7398 work->enable_stall_check = true;
7399
7400 atomic_inc(&intel_crtc->unpin_work_count);
7401 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7402
7403 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7404 if (ret)
7405 goto cleanup_pending;
7406
7407 intel_disable_fbc(dev);
7408 intel_mark_fb_busy(obj);
7409 mutex_unlock(&dev->struct_mutex);
7410
7411 trace_i915_flip_request(intel_crtc->plane, obj);
7412
7413 return 0;
7414
7415 cleanup_pending:
7416 atomic_dec(&intel_crtc->unpin_work_count);
7417 crtc->fb = old_fb;
7418 drm_gem_object_unreference(&work->old_fb_obj->base);
7419 drm_gem_object_unreference(&obj->base);
7420 mutex_unlock(&dev->struct_mutex);
7421
7422 cleanup:
7423 spin_lock_irqsave(&dev->event_lock, flags);
7424 intel_crtc->unpin_work = NULL;
7425 spin_unlock_irqrestore(&dev->event_lock, flags);
7426
7427 drm_vblank_put(dev, intel_crtc->pipe);
7428 free_work:
7429 kfree(work);
7430
7431 return ret;
7432 }
7433
7434 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7435 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7436 .load_lut = intel_crtc_load_lut,
7437 };
7438
7439 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7440 {
7441 struct intel_encoder *other_encoder;
7442 struct drm_crtc *crtc = &encoder->new_crtc->base;
7443
7444 if (WARN_ON(!crtc))
7445 return false;
7446
7447 list_for_each_entry(other_encoder,
7448 &crtc->dev->mode_config.encoder_list,
7449 base.head) {
7450
7451 if (&other_encoder->new_crtc->base != crtc ||
7452 encoder == other_encoder)
7453 continue;
7454 else
7455 return true;
7456 }
7457
7458 return false;
7459 }
7460
7461 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7462 struct drm_crtc *crtc)
7463 {
7464 struct drm_device *dev;
7465 struct drm_crtc *tmp;
7466 int crtc_mask = 1;
7467
7468 WARN(!crtc, "checking null crtc?\n");
7469
7470 dev = crtc->dev;
7471
7472 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7473 if (tmp == crtc)
7474 break;
7475 crtc_mask <<= 1;
7476 }
7477
7478 if (encoder->possible_crtcs & crtc_mask)
7479 return true;
7480 return false;
7481 }
7482
7483 /**
7484 * intel_modeset_update_staged_output_state
7485 *
7486 * Updates the staged output configuration state, e.g. after we've read out the
7487 * current hw state.
7488 */
7489 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7490 {
7491 struct intel_encoder *encoder;
7492 struct intel_connector *connector;
7493
7494 list_for_each_entry(connector, &dev->mode_config.connector_list,
7495 base.head) {
7496 connector->new_encoder =
7497 to_intel_encoder(connector->base.encoder);
7498 }
7499
7500 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7501 base.head) {
7502 encoder->new_crtc =
7503 to_intel_crtc(encoder->base.crtc);
7504 }
7505 }
7506
7507 /**
7508 * intel_modeset_commit_output_state
7509 *
7510 * This function copies the stage display pipe configuration to the real one.
7511 */
7512 static void intel_modeset_commit_output_state(struct drm_device *dev)
7513 {
7514 struct intel_encoder *encoder;
7515 struct intel_connector *connector;
7516
7517 list_for_each_entry(connector, &dev->mode_config.connector_list,
7518 base.head) {
7519 connector->base.encoder = &connector->new_encoder->base;
7520 }
7521
7522 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7523 base.head) {
7524 encoder->base.crtc = &encoder->new_crtc->base;
7525 }
7526 }
7527
7528 static struct intel_crtc_config *
7529 intel_modeset_pipe_config(struct drm_crtc *crtc,
7530 struct drm_display_mode *mode)
7531 {
7532 struct drm_device *dev = crtc->dev;
7533 struct drm_encoder_helper_funcs *encoder_funcs;
7534 struct intel_encoder *encoder;
7535 struct intel_crtc_config *pipe_config;
7536
7537 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7538 if (!pipe_config)
7539 return ERR_PTR(-ENOMEM);
7540
7541 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7542 drm_mode_copy(&pipe_config->requested_mode, mode);
7543
7544 /* Pass our mode to the connectors and the CRTC to give them a chance to
7545 * adjust it according to limitations or connector properties, and also
7546 * a chance to reject the mode entirely.
7547 */
7548 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7549 base.head) {
7550
7551 if (&encoder->new_crtc->base != crtc)
7552 continue;
7553
7554 if (encoder->compute_config) {
7555 if (!(encoder->compute_config(encoder, pipe_config))) {
7556 DRM_DEBUG_KMS("Encoder config failure\n");
7557 goto fail;
7558 }
7559
7560 continue;
7561 }
7562
7563 encoder_funcs = encoder->base.helper_private;
7564 if (!(encoder_funcs->mode_fixup(&encoder->base,
7565 &pipe_config->requested_mode,
7566 &pipe_config->adjusted_mode))) {
7567 DRM_DEBUG_KMS("Encoder fixup failed\n");
7568 goto fail;
7569 }
7570 }
7571
7572 if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7573 DRM_DEBUG_KMS("CRTC fixup failed\n");
7574 goto fail;
7575 }
7576 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7577
7578 return pipe_config;
7579 fail:
7580 kfree(pipe_config);
7581 return ERR_PTR(-EINVAL);
7582 }
7583
7584 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7585 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7586 static void
7587 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7588 unsigned *prepare_pipes, unsigned *disable_pipes)
7589 {
7590 struct intel_crtc *intel_crtc;
7591 struct drm_device *dev = crtc->dev;
7592 struct intel_encoder *encoder;
7593 struct intel_connector *connector;
7594 struct drm_crtc *tmp_crtc;
7595
7596 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7597
7598 /* Check which crtcs have changed outputs connected to them, these need
7599 * to be part of the prepare_pipes mask. We don't (yet) support global
7600 * modeset across multiple crtcs, so modeset_pipes will only have one
7601 * bit set at most. */
7602 list_for_each_entry(connector, &dev->mode_config.connector_list,
7603 base.head) {
7604 if (connector->base.encoder == &connector->new_encoder->base)
7605 continue;
7606
7607 if (connector->base.encoder) {
7608 tmp_crtc = connector->base.encoder->crtc;
7609
7610 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7611 }
7612
7613 if (connector->new_encoder)
7614 *prepare_pipes |=
7615 1 << connector->new_encoder->new_crtc->pipe;
7616 }
7617
7618 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7619 base.head) {
7620 if (encoder->base.crtc == &encoder->new_crtc->base)
7621 continue;
7622
7623 if (encoder->base.crtc) {
7624 tmp_crtc = encoder->base.crtc;
7625
7626 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7627 }
7628
7629 if (encoder->new_crtc)
7630 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7631 }
7632
7633 /* Check for any pipes that will be fully disabled ... */
7634 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7635 base.head) {
7636 bool used = false;
7637
7638 /* Don't try to disable disabled crtcs. */
7639 if (!intel_crtc->base.enabled)
7640 continue;
7641
7642 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7643 base.head) {
7644 if (encoder->new_crtc == intel_crtc)
7645 used = true;
7646 }
7647
7648 if (!used)
7649 *disable_pipes |= 1 << intel_crtc->pipe;
7650 }
7651
7652
7653 /* set_mode is also used to update properties on life display pipes. */
7654 intel_crtc = to_intel_crtc(crtc);
7655 if (crtc->enabled)
7656 *prepare_pipes |= 1 << intel_crtc->pipe;
7657
7658 /* We only support modeset on one single crtc, hence we need to do that
7659 * only for the passed in crtc iff we change anything else than just
7660 * disable crtcs.
7661 *
7662 * This is actually not true, to be fully compatible with the old crtc
7663 * helper we automatically disable _any_ output (i.e. doesn't need to be
7664 * connected to the crtc we're modesetting on) if it's disconnected.
7665 * Which is a rather nutty api (since changed the output configuration
7666 * without userspace's explicit request can lead to confusion), but
7667 * alas. Hence we currently need to modeset on all pipes we prepare. */
7668 if (*prepare_pipes)
7669 *modeset_pipes = *prepare_pipes;
7670
7671 /* ... and mask these out. */
7672 *modeset_pipes &= ~(*disable_pipes);
7673 *prepare_pipes &= ~(*disable_pipes);
7674 }
7675
7676 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7677 {
7678 struct drm_encoder *encoder;
7679 struct drm_device *dev = crtc->dev;
7680
7681 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7682 if (encoder->crtc == crtc)
7683 return true;
7684
7685 return false;
7686 }
7687
7688 static void
7689 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7690 {
7691 struct intel_encoder *intel_encoder;
7692 struct intel_crtc *intel_crtc;
7693 struct drm_connector *connector;
7694
7695 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7696 base.head) {
7697 if (!intel_encoder->base.crtc)
7698 continue;
7699
7700 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7701
7702 if (prepare_pipes & (1 << intel_crtc->pipe))
7703 intel_encoder->connectors_active = false;
7704 }
7705
7706 intel_modeset_commit_output_state(dev);
7707
7708 /* Update computed state. */
7709 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7710 base.head) {
7711 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7712 }
7713
7714 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7715 if (!connector->encoder || !connector->encoder->crtc)
7716 continue;
7717
7718 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7719
7720 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7721 struct drm_property *dpms_property =
7722 dev->mode_config.dpms_property;
7723
7724 connector->dpms = DRM_MODE_DPMS_ON;
7725 drm_object_property_set_value(&connector->base,
7726 dpms_property,
7727 DRM_MODE_DPMS_ON);
7728
7729 intel_encoder = to_intel_encoder(connector->encoder);
7730 intel_encoder->connectors_active = true;
7731 }
7732 }
7733
7734 }
7735
7736 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7737 list_for_each_entry((intel_crtc), \
7738 &(dev)->mode_config.crtc_list, \
7739 base.head) \
7740 if (mask & (1 <<(intel_crtc)->pipe)) \
7741
7742 void
7743 intel_modeset_check_state(struct drm_device *dev)
7744 {
7745 struct intel_crtc *crtc;
7746 struct intel_encoder *encoder;
7747 struct intel_connector *connector;
7748
7749 list_for_each_entry(connector, &dev->mode_config.connector_list,
7750 base.head) {
7751 /* This also checks the encoder/connector hw state with the
7752 * ->get_hw_state callbacks. */
7753 intel_connector_check_state(connector);
7754
7755 WARN(&connector->new_encoder->base != connector->base.encoder,
7756 "connector's staged encoder doesn't match current encoder\n");
7757 }
7758
7759 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7760 base.head) {
7761 bool enabled = false;
7762 bool active = false;
7763 enum pipe pipe, tracked_pipe;
7764
7765 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7766 encoder->base.base.id,
7767 drm_get_encoder_name(&encoder->base));
7768
7769 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7770 "encoder's stage crtc doesn't match current crtc\n");
7771 WARN(encoder->connectors_active && !encoder->base.crtc,
7772 "encoder's active_connectors set, but no crtc\n");
7773
7774 list_for_each_entry(connector, &dev->mode_config.connector_list,
7775 base.head) {
7776 if (connector->base.encoder != &encoder->base)
7777 continue;
7778 enabled = true;
7779 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7780 active = true;
7781 }
7782 WARN(!!encoder->base.crtc != enabled,
7783 "encoder's enabled state mismatch "
7784 "(expected %i, found %i)\n",
7785 !!encoder->base.crtc, enabled);
7786 WARN(active && !encoder->base.crtc,
7787 "active encoder with no crtc\n");
7788
7789 WARN(encoder->connectors_active != active,
7790 "encoder's computed active state doesn't match tracked active state "
7791 "(expected %i, found %i)\n", active, encoder->connectors_active);
7792
7793 active = encoder->get_hw_state(encoder, &pipe);
7794 WARN(active != encoder->connectors_active,
7795 "encoder's hw state doesn't match sw tracking "
7796 "(expected %i, found %i)\n",
7797 encoder->connectors_active, active);
7798
7799 if (!encoder->base.crtc)
7800 continue;
7801
7802 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7803 WARN(active && pipe != tracked_pipe,
7804 "active encoder's pipe doesn't match"
7805 "(expected %i, found %i)\n",
7806 tracked_pipe, pipe);
7807
7808 }
7809
7810 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7811 base.head) {
7812 bool enabled = false;
7813 bool active = false;
7814
7815 DRM_DEBUG_KMS("[CRTC:%d]\n",
7816 crtc->base.base.id);
7817
7818 WARN(crtc->active && !crtc->base.enabled,
7819 "active crtc, but not enabled in sw tracking\n");
7820
7821 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7822 base.head) {
7823 if (encoder->base.crtc != &crtc->base)
7824 continue;
7825 enabled = true;
7826 if (encoder->connectors_active)
7827 active = true;
7828 }
7829 WARN(active != crtc->active,
7830 "crtc's computed active state doesn't match tracked active state "
7831 "(expected %i, found %i)\n", active, crtc->active);
7832 WARN(enabled != crtc->base.enabled,
7833 "crtc's computed enabled state doesn't match tracked enabled state "
7834 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7835
7836 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7837 }
7838 }
7839
7840 int intel_set_mode(struct drm_crtc *crtc,
7841 struct drm_display_mode *mode,
7842 int x, int y, struct drm_framebuffer *fb)
7843 {
7844 struct drm_device *dev = crtc->dev;
7845 drm_i915_private_t *dev_priv = dev->dev_private;
7846 struct drm_display_mode *saved_mode, *saved_hwmode;
7847 struct intel_crtc_config *pipe_config = NULL;
7848 struct intel_crtc *intel_crtc;
7849 unsigned disable_pipes, prepare_pipes, modeset_pipes;
7850 int ret = 0;
7851
7852 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
7853 if (!saved_mode)
7854 return -ENOMEM;
7855 saved_hwmode = saved_mode + 1;
7856
7857 intel_modeset_affected_pipes(crtc, &modeset_pipes,
7858 &prepare_pipes, &disable_pipes);
7859
7860 *saved_hwmode = crtc->hwmode;
7861 *saved_mode = crtc->mode;
7862
7863 /* Hack: Because we don't (yet) support global modeset on multiple
7864 * crtcs, we don't keep track of the new mode for more than one crtc.
7865 * Hence simply check whether any bit is set in modeset_pipes in all the
7866 * pieces of code that are not yet converted to deal with mutliple crtcs
7867 * changing their mode at the same time. */
7868 if (modeset_pipes) {
7869 pipe_config = intel_modeset_pipe_config(crtc, mode);
7870 if (IS_ERR(pipe_config)) {
7871 ret = PTR_ERR(pipe_config);
7872 pipe_config = NULL;
7873
7874 goto out;
7875 }
7876 }
7877
7878 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7879 modeset_pipes, prepare_pipes, disable_pipes);
7880
7881 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7882 intel_crtc_disable(&intel_crtc->base);
7883
7884 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7885 if (intel_crtc->base.enabled)
7886 dev_priv->display.crtc_disable(&intel_crtc->base);
7887 }
7888
7889 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7890 * to set it here already despite that we pass it down the callchain.
7891 */
7892 if (modeset_pipes) {
7893 crtc->mode = *mode;
7894 /* mode_set/enable/disable functions rely on a correct pipe
7895 * config. */
7896 to_intel_crtc(crtc)->config = *pipe_config;
7897 }
7898
7899 /* Only after disabling all output pipelines that will be changed can we
7900 * update the the output configuration. */
7901 intel_modeset_update_state(dev, prepare_pipes);
7902
7903 if (dev_priv->display.modeset_global_resources)
7904 dev_priv->display.modeset_global_resources(dev);
7905
7906 /* Set up the DPLL and any encoders state that needs to adjust or depend
7907 * on the DPLL.
7908 */
7909 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7910 ret = intel_crtc_mode_set(&intel_crtc->base,
7911 x, y, fb);
7912 if (ret)
7913 goto done;
7914 }
7915
7916 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7917 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7918 dev_priv->display.crtc_enable(&intel_crtc->base);
7919
7920 if (modeset_pipes) {
7921 /* Store real post-adjustment hardware mode. */
7922 crtc->hwmode = pipe_config->adjusted_mode;
7923
7924 /* Calculate and store various constants which
7925 * are later needed by vblank and swap-completion
7926 * timestamping. They are derived from true hwmode.
7927 */
7928 drm_calc_timestamping_constants(crtc);
7929 }
7930
7931 /* FIXME: add subpixel order */
7932 done:
7933 if (ret && crtc->enabled) {
7934 crtc->hwmode = *saved_hwmode;
7935 crtc->mode = *saved_mode;
7936 } else {
7937 intel_modeset_check_state(dev);
7938 }
7939
7940 out:
7941 kfree(pipe_config);
7942 kfree(saved_mode);
7943 return ret;
7944 }
7945
7946 void intel_crtc_restore_mode(struct drm_crtc *crtc)
7947 {
7948 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7949 }
7950
7951 #undef for_each_intel_crtc_masked
7952
7953 static void intel_set_config_free(struct intel_set_config *config)
7954 {
7955 if (!config)
7956 return;
7957
7958 kfree(config->save_connector_encoders);
7959 kfree(config->save_encoder_crtcs);
7960 kfree(config);
7961 }
7962
7963 static int intel_set_config_save_state(struct drm_device *dev,
7964 struct intel_set_config *config)
7965 {
7966 struct drm_encoder *encoder;
7967 struct drm_connector *connector;
7968 int count;
7969
7970 config->save_encoder_crtcs =
7971 kcalloc(dev->mode_config.num_encoder,
7972 sizeof(struct drm_crtc *), GFP_KERNEL);
7973 if (!config->save_encoder_crtcs)
7974 return -ENOMEM;
7975
7976 config->save_connector_encoders =
7977 kcalloc(dev->mode_config.num_connector,
7978 sizeof(struct drm_encoder *), GFP_KERNEL);
7979 if (!config->save_connector_encoders)
7980 return -ENOMEM;
7981
7982 /* Copy data. Note that driver private data is not affected.
7983 * Should anything bad happen only the expected state is
7984 * restored, not the drivers personal bookkeeping.
7985 */
7986 count = 0;
7987 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7988 config->save_encoder_crtcs[count++] = encoder->crtc;
7989 }
7990
7991 count = 0;
7992 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7993 config->save_connector_encoders[count++] = connector->encoder;
7994 }
7995
7996 return 0;
7997 }
7998
7999 static void intel_set_config_restore_state(struct drm_device *dev,
8000 struct intel_set_config *config)
8001 {
8002 struct intel_encoder *encoder;
8003 struct intel_connector *connector;
8004 int count;
8005
8006 count = 0;
8007 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8008 encoder->new_crtc =
8009 to_intel_crtc(config->save_encoder_crtcs[count++]);
8010 }
8011
8012 count = 0;
8013 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8014 connector->new_encoder =
8015 to_intel_encoder(config->save_connector_encoders[count++]);
8016 }
8017 }
8018
8019 static void
8020 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8021 struct intel_set_config *config)
8022 {
8023
8024 /* We should be able to check here if the fb has the same properties
8025 * and then just flip_or_move it */
8026 if (set->crtc->fb != set->fb) {
8027 /* If we have no fb then treat it as a full mode set */
8028 if (set->crtc->fb == NULL) {
8029 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8030 config->mode_changed = true;
8031 } else if (set->fb == NULL) {
8032 config->mode_changed = true;
8033 } else if (set->fb->depth != set->crtc->fb->depth) {
8034 config->mode_changed = true;
8035 } else if (set->fb->bits_per_pixel !=
8036 set->crtc->fb->bits_per_pixel) {
8037 config->mode_changed = true;
8038 } else
8039 config->fb_changed = true;
8040 }
8041
8042 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8043 config->fb_changed = true;
8044
8045 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8046 DRM_DEBUG_KMS("modes are different, full mode set\n");
8047 drm_mode_debug_printmodeline(&set->crtc->mode);
8048 drm_mode_debug_printmodeline(set->mode);
8049 config->mode_changed = true;
8050 }
8051 }
8052
8053 static int
8054 intel_modeset_stage_output_state(struct drm_device *dev,
8055 struct drm_mode_set *set,
8056 struct intel_set_config *config)
8057 {
8058 struct drm_crtc *new_crtc;
8059 struct intel_connector *connector;
8060 struct intel_encoder *encoder;
8061 int count, ro;
8062
8063 /* The upper layers ensure that we either disable a crtc or have a list
8064 * of connectors. For paranoia, double-check this. */
8065 WARN_ON(!set->fb && (set->num_connectors != 0));
8066 WARN_ON(set->fb && (set->num_connectors == 0));
8067
8068 count = 0;
8069 list_for_each_entry(connector, &dev->mode_config.connector_list,
8070 base.head) {
8071 /* Otherwise traverse passed in connector list and get encoders
8072 * for them. */
8073 for (ro = 0; ro < set->num_connectors; ro++) {
8074 if (set->connectors[ro] == &connector->base) {
8075 connector->new_encoder = connector->encoder;
8076 break;
8077 }
8078 }
8079
8080 /* If we disable the crtc, disable all its connectors. Also, if
8081 * the connector is on the changing crtc but not on the new
8082 * connector list, disable it. */
8083 if ((!set->fb || ro == set->num_connectors) &&
8084 connector->base.encoder &&
8085 connector->base.encoder->crtc == set->crtc) {
8086 connector->new_encoder = NULL;
8087
8088 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8089 connector->base.base.id,
8090 drm_get_connector_name(&connector->base));
8091 }
8092
8093
8094 if (&connector->new_encoder->base != connector->base.encoder) {
8095 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8096 config->mode_changed = true;
8097 }
8098 }
8099 /* connector->new_encoder is now updated for all connectors. */
8100
8101 /* Update crtc of enabled connectors. */
8102 count = 0;
8103 list_for_each_entry(connector, &dev->mode_config.connector_list,
8104 base.head) {
8105 if (!connector->new_encoder)
8106 continue;
8107
8108 new_crtc = connector->new_encoder->base.crtc;
8109
8110 for (ro = 0; ro < set->num_connectors; ro++) {
8111 if (set->connectors[ro] == &connector->base)
8112 new_crtc = set->crtc;
8113 }
8114
8115 /* Make sure the new CRTC will work with the encoder */
8116 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8117 new_crtc)) {
8118 return -EINVAL;
8119 }
8120 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8121
8122 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8123 connector->base.base.id,
8124 drm_get_connector_name(&connector->base),
8125 new_crtc->base.id);
8126 }
8127
8128 /* Check for any encoders that needs to be disabled. */
8129 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8130 base.head) {
8131 list_for_each_entry(connector,
8132 &dev->mode_config.connector_list,
8133 base.head) {
8134 if (connector->new_encoder == encoder) {
8135 WARN_ON(!connector->new_encoder->new_crtc);
8136
8137 goto next_encoder;
8138 }
8139 }
8140 encoder->new_crtc = NULL;
8141 next_encoder:
8142 /* Only now check for crtc changes so we don't miss encoders
8143 * that will be disabled. */
8144 if (&encoder->new_crtc->base != encoder->base.crtc) {
8145 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8146 config->mode_changed = true;
8147 }
8148 }
8149 /* Now we've also updated encoder->new_crtc for all encoders. */
8150
8151 return 0;
8152 }
8153
8154 static int intel_crtc_set_config(struct drm_mode_set *set)
8155 {
8156 struct drm_device *dev;
8157 struct drm_mode_set save_set;
8158 struct intel_set_config *config;
8159 int ret;
8160
8161 BUG_ON(!set);
8162 BUG_ON(!set->crtc);
8163 BUG_ON(!set->crtc->helper_private);
8164
8165 /* Enforce sane interface api - has been abused by the fb helper. */
8166 BUG_ON(!set->mode && set->fb);
8167 BUG_ON(set->fb && set->num_connectors == 0);
8168
8169 if (set->fb) {
8170 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8171 set->crtc->base.id, set->fb->base.id,
8172 (int)set->num_connectors, set->x, set->y);
8173 } else {
8174 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8175 }
8176
8177 dev = set->crtc->dev;
8178
8179 ret = -ENOMEM;
8180 config = kzalloc(sizeof(*config), GFP_KERNEL);
8181 if (!config)
8182 goto out_config;
8183
8184 ret = intel_set_config_save_state(dev, config);
8185 if (ret)
8186 goto out_config;
8187
8188 save_set.crtc = set->crtc;
8189 save_set.mode = &set->crtc->mode;
8190 save_set.x = set->crtc->x;
8191 save_set.y = set->crtc->y;
8192 save_set.fb = set->crtc->fb;
8193
8194 /* Compute whether we need a full modeset, only an fb base update or no
8195 * change at all. In the future we might also check whether only the
8196 * mode changed, e.g. for LVDS where we only change the panel fitter in
8197 * such cases. */
8198 intel_set_config_compute_mode_changes(set, config);
8199
8200 ret = intel_modeset_stage_output_state(dev, set, config);
8201 if (ret)
8202 goto fail;
8203
8204 if (config->mode_changed) {
8205 if (set->mode) {
8206 DRM_DEBUG_KMS("attempting to set mode from"
8207 " userspace\n");
8208 drm_mode_debug_printmodeline(set->mode);
8209 }
8210
8211 ret = intel_set_mode(set->crtc, set->mode,
8212 set->x, set->y, set->fb);
8213 if (ret) {
8214 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8215 set->crtc->base.id, ret);
8216 goto fail;
8217 }
8218 } else if (config->fb_changed) {
8219 intel_crtc_wait_for_pending_flips(set->crtc);
8220
8221 ret = intel_pipe_set_base(set->crtc,
8222 set->x, set->y, set->fb);
8223 }
8224
8225 intel_set_config_free(config);
8226
8227 return 0;
8228
8229 fail:
8230 intel_set_config_restore_state(dev, config);
8231
8232 /* Try to restore the config */
8233 if (config->mode_changed &&
8234 intel_set_mode(save_set.crtc, save_set.mode,
8235 save_set.x, save_set.y, save_set.fb))
8236 DRM_ERROR("failed to restore config after modeset failure\n");
8237
8238 out_config:
8239 intel_set_config_free(config);
8240 return ret;
8241 }
8242
8243 static const struct drm_crtc_funcs intel_crtc_funcs = {
8244 .cursor_set = intel_crtc_cursor_set,
8245 .cursor_move = intel_crtc_cursor_move,
8246 .gamma_set = intel_crtc_gamma_set,
8247 .set_config = intel_crtc_set_config,
8248 .destroy = intel_crtc_destroy,
8249 .page_flip = intel_crtc_page_flip,
8250 };
8251
8252 static void intel_cpu_pll_init(struct drm_device *dev)
8253 {
8254 if (HAS_DDI(dev))
8255 intel_ddi_pll_init(dev);
8256 }
8257
8258 static void intel_pch_pll_init(struct drm_device *dev)
8259 {
8260 drm_i915_private_t *dev_priv = dev->dev_private;
8261 int i;
8262
8263 if (dev_priv->num_pch_pll == 0) {
8264 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8265 return;
8266 }
8267
8268 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8269 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8270 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8271 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8272 }
8273 }
8274
8275 static void intel_crtc_init(struct drm_device *dev, int pipe)
8276 {
8277 drm_i915_private_t *dev_priv = dev->dev_private;
8278 struct intel_crtc *intel_crtc;
8279 int i;
8280
8281 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8282 if (intel_crtc == NULL)
8283 return;
8284
8285 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8286
8287 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8288 for (i = 0; i < 256; i++) {
8289 intel_crtc->lut_r[i] = i;
8290 intel_crtc->lut_g[i] = i;
8291 intel_crtc->lut_b[i] = i;
8292 }
8293
8294 /* Swap pipes & planes for FBC on pre-965 */
8295 intel_crtc->pipe = pipe;
8296 intel_crtc->plane = pipe;
8297 intel_crtc->cpu_transcoder = pipe;
8298 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8299 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8300 intel_crtc->plane = !pipe;
8301 }
8302
8303 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8304 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8305 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8306 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8307
8308 intel_crtc->config.pipe_bpp = 24; /* default for pre-Ironlake */
8309
8310 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8311 }
8312
8313 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8314 struct drm_file *file)
8315 {
8316 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8317 struct drm_mode_object *drmmode_obj;
8318 struct intel_crtc *crtc;
8319
8320 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8321 return -ENODEV;
8322
8323 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8324 DRM_MODE_OBJECT_CRTC);
8325
8326 if (!drmmode_obj) {
8327 DRM_ERROR("no such CRTC id\n");
8328 return -EINVAL;
8329 }
8330
8331 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8332 pipe_from_crtc_id->pipe = crtc->pipe;
8333
8334 return 0;
8335 }
8336
8337 static int intel_encoder_clones(struct intel_encoder *encoder)
8338 {
8339 struct drm_device *dev = encoder->base.dev;
8340 struct intel_encoder *source_encoder;
8341 int index_mask = 0;
8342 int entry = 0;
8343
8344 list_for_each_entry(source_encoder,
8345 &dev->mode_config.encoder_list, base.head) {
8346
8347 if (encoder == source_encoder)
8348 index_mask |= (1 << entry);
8349
8350 /* Intel hw has only one MUX where enocoders could be cloned. */
8351 if (encoder->cloneable && source_encoder->cloneable)
8352 index_mask |= (1 << entry);
8353
8354 entry++;
8355 }
8356
8357 return index_mask;
8358 }
8359
8360 static bool has_edp_a(struct drm_device *dev)
8361 {
8362 struct drm_i915_private *dev_priv = dev->dev_private;
8363
8364 if (!IS_MOBILE(dev))
8365 return false;
8366
8367 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8368 return false;
8369
8370 if (IS_GEN5(dev) &&
8371 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8372 return false;
8373
8374 return true;
8375 }
8376
8377 static void intel_setup_outputs(struct drm_device *dev)
8378 {
8379 struct drm_i915_private *dev_priv = dev->dev_private;
8380 struct intel_encoder *encoder;
8381 bool dpd_is_edp = false;
8382 bool has_lvds;
8383
8384 has_lvds = intel_lvds_init(dev);
8385 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8386 /* disable the panel fitter on everything but LVDS */
8387 I915_WRITE(PFIT_CONTROL, 0);
8388 }
8389
8390 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8391 intel_crt_init(dev);
8392
8393 if (HAS_DDI(dev)) {
8394 int found;
8395
8396 /* Haswell uses DDI functions to detect digital outputs */
8397 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8398 /* DDI A only supports eDP */
8399 if (found)
8400 intel_ddi_init(dev, PORT_A);
8401
8402 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8403 * register */
8404 found = I915_READ(SFUSE_STRAP);
8405
8406 if (found & SFUSE_STRAP_DDIB_DETECTED)
8407 intel_ddi_init(dev, PORT_B);
8408 if (found & SFUSE_STRAP_DDIC_DETECTED)
8409 intel_ddi_init(dev, PORT_C);
8410 if (found & SFUSE_STRAP_DDID_DETECTED)
8411 intel_ddi_init(dev, PORT_D);
8412 } else if (HAS_PCH_SPLIT(dev)) {
8413 int found;
8414 dpd_is_edp = intel_dpd_is_edp(dev);
8415
8416 if (has_edp_a(dev))
8417 intel_dp_init(dev, DP_A, PORT_A);
8418
8419 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8420 /* PCH SDVOB multiplex with HDMIB */
8421 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8422 if (!found)
8423 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8424 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8425 intel_dp_init(dev, PCH_DP_B, PORT_B);
8426 }
8427
8428 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8429 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8430
8431 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8432 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8433
8434 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8435 intel_dp_init(dev, PCH_DP_C, PORT_C);
8436
8437 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8438 intel_dp_init(dev, PCH_DP_D, PORT_D);
8439 } else if (IS_VALLEYVIEW(dev)) {
8440 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8441 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8442 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8443
8444 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8445 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8446 PORT_B);
8447 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8448 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8449 }
8450 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8451 bool found = false;
8452
8453 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8454 DRM_DEBUG_KMS("probing SDVOB\n");
8455 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8456 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8457 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8458 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8459 }
8460
8461 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8462 DRM_DEBUG_KMS("probing DP_B\n");
8463 intel_dp_init(dev, DP_B, PORT_B);
8464 }
8465 }
8466
8467 /* Before G4X SDVOC doesn't have its own detect register */
8468
8469 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8470 DRM_DEBUG_KMS("probing SDVOC\n");
8471 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8472 }
8473
8474 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8475
8476 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8477 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8478 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8479 }
8480 if (SUPPORTS_INTEGRATED_DP(dev)) {
8481 DRM_DEBUG_KMS("probing DP_C\n");
8482 intel_dp_init(dev, DP_C, PORT_C);
8483 }
8484 }
8485
8486 if (SUPPORTS_INTEGRATED_DP(dev) &&
8487 (I915_READ(DP_D) & DP_DETECTED)) {
8488 DRM_DEBUG_KMS("probing DP_D\n");
8489 intel_dp_init(dev, DP_D, PORT_D);
8490 }
8491 } else if (IS_GEN2(dev))
8492 intel_dvo_init(dev);
8493
8494 if (SUPPORTS_TV(dev))
8495 intel_tv_init(dev);
8496
8497 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8498 encoder->base.possible_crtcs = encoder->crtc_mask;
8499 encoder->base.possible_clones =
8500 intel_encoder_clones(encoder);
8501 }
8502
8503 intel_init_pch_refclk(dev);
8504
8505 drm_helper_move_panel_connectors_to_head(dev);
8506 }
8507
8508 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8509 {
8510 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8511
8512 drm_framebuffer_cleanup(fb);
8513 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8514
8515 kfree(intel_fb);
8516 }
8517
8518 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8519 struct drm_file *file,
8520 unsigned int *handle)
8521 {
8522 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8523 struct drm_i915_gem_object *obj = intel_fb->obj;
8524
8525 return drm_gem_handle_create(file, &obj->base, handle);
8526 }
8527
8528 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8529 .destroy = intel_user_framebuffer_destroy,
8530 .create_handle = intel_user_framebuffer_create_handle,
8531 };
8532
8533 int intel_framebuffer_init(struct drm_device *dev,
8534 struct intel_framebuffer *intel_fb,
8535 struct drm_mode_fb_cmd2 *mode_cmd,
8536 struct drm_i915_gem_object *obj)
8537 {
8538 int ret;
8539
8540 if (obj->tiling_mode == I915_TILING_Y) {
8541 DRM_DEBUG("hardware does not support tiling Y\n");
8542 return -EINVAL;
8543 }
8544
8545 if (mode_cmd->pitches[0] & 63) {
8546 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8547 mode_cmd->pitches[0]);
8548 return -EINVAL;
8549 }
8550
8551 /* FIXME <= Gen4 stride limits are bit unclear */
8552 if (mode_cmd->pitches[0] > 32768) {
8553 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8554 mode_cmd->pitches[0]);
8555 return -EINVAL;
8556 }
8557
8558 if (obj->tiling_mode != I915_TILING_NONE &&
8559 mode_cmd->pitches[0] != obj->stride) {
8560 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8561 mode_cmd->pitches[0], obj->stride);
8562 return -EINVAL;
8563 }
8564
8565 /* Reject formats not supported by any plane early. */
8566 switch (mode_cmd->pixel_format) {
8567 case DRM_FORMAT_C8:
8568 case DRM_FORMAT_RGB565:
8569 case DRM_FORMAT_XRGB8888:
8570 case DRM_FORMAT_ARGB8888:
8571 break;
8572 case DRM_FORMAT_XRGB1555:
8573 case DRM_FORMAT_ARGB1555:
8574 if (INTEL_INFO(dev)->gen > 3) {
8575 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8576 return -EINVAL;
8577 }
8578 break;
8579 case DRM_FORMAT_XBGR8888:
8580 case DRM_FORMAT_ABGR8888:
8581 case DRM_FORMAT_XRGB2101010:
8582 case DRM_FORMAT_ARGB2101010:
8583 case DRM_FORMAT_XBGR2101010:
8584 case DRM_FORMAT_ABGR2101010:
8585 if (INTEL_INFO(dev)->gen < 4) {
8586 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8587 return -EINVAL;
8588 }
8589 break;
8590 case DRM_FORMAT_YUYV:
8591 case DRM_FORMAT_UYVY:
8592 case DRM_FORMAT_YVYU:
8593 case DRM_FORMAT_VYUY:
8594 if (INTEL_INFO(dev)->gen < 5) {
8595 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8596 return -EINVAL;
8597 }
8598 break;
8599 default:
8600 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8601 return -EINVAL;
8602 }
8603
8604 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8605 if (mode_cmd->offsets[0] != 0)
8606 return -EINVAL;
8607
8608 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8609 intel_fb->obj = obj;
8610
8611 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8612 if (ret) {
8613 DRM_ERROR("framebuffer init failed %d\n", ret);
8614 return ret;
8615 }
8616
8617 return 0;
8618 }
8619
8620 static struct drm_framebuffer *
8621 intel_user_framebuffer_create(struct drm_device *dev,
8622 struct drm_file *filp,
8623 struct drm_mode_fb_cmd2 *mode_cmd)
8624 {
8625 struct drm_i915_gem_object *obj;
8626
8627 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8628 mode_cmd->handles[0]));
8629 if (&obj->base == NULL)
8630 return ERR_PTR(-ENOENT);
8631
8632 return intel_framebuffer_create(dev, mode_cmd, obj);
8633 }
8634
8635 static const struct drm_mode_config_funcs intel_mode_funcs = {
8636 .fb_create = intel_user_framebuffer_create,
8637 .output_poll_changed = intel_fb_output_poll_changed,
8638 };
8639
8640 /* Set up chip specific display functions */
8641 static void intel_init_display(struct drm_device *dev)
8642 {
8643 struct drm_i915_private *dev_priv = dev->dev_private;
8644
8645 if (HAS_DDI(dev)) {
8646 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8647 dev_priv->display.crtc_enable = haswell_crtc_enable;
8648 dev_priv->display.crtc_disable = haswell_crtc_disable;
8649 dev_priv->display.off = haswell_crtc_off;
8650 dev_priv->display.update_plane = ironlake_update_plane;
8651 } else if (HAS_PCH_SPLIT(dev)) {
8652 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8653 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8654 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8655 dev_priv->display.off = ironlake_crtc_off;
8656 dev_priv->display.update_plane = ironlake_update_plane;
8657 } else {
8658 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8659 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8660 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8661 dev_priv->display.off = i9xx_crtc_off;
8662 dev_priv->display.update_plane = i9xx_update_plane;
8663 }
8664
8665 /* Returns the core display clock speed */
8666 if (IS_VALLEYVIEW(dev))
8667 dev_priv->display.get_display_clock_speed =
8668 valleyview_get_display_clock_speed;
8669 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8670 dev_priv->display.get_display_clock_speed =
8671 i945_get_display_clock_speed;
8672 else if (IS_I915G(dev))
8673 dev_priv->display.get_display_clock_speed =
8674 i915_get_display_clock_speed;
8675 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8676 dev_priv->display.get_display_clock_speed =
8677 i9xx_misc_get_display_clock_speed;
8678 else if (IS_I915GM(dev))
8679 dev_priv->display.get_display_clock_speed =
8680 i915gm_get_display_clock_speed;
8681 else if (IS_I865G(dev))
8682 dev_priv->display.get_display_clock_speed =
8683 i865_get_display_clock_speed;
8684 else if (IS_I85X(dev))
8685 dev_priv->display.get_display_clock_speed =
8686 i855_get_display_clock_speed;
8687 else /* 852, 830 */
8688 dev_priv->display.get_display_clock_speed =
8689 i830_get_display_clock_speed;
8690
8691 if (HAS_PCH_SPLIT(dev)) {
8692 if (IS_GEN5(dev)) {
8693 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8694 dev_priv->display.write_eld = ironlake_write_eld;
8695 } else if (IS_GEN6(dev)) {
8696 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8697 dev_priv->display.write_eld = ironlake_write_eld;
8698 } else if (IS_IVYBRIDGE(dev)) {
8699 /* FIXME: detect B0+ stepping and use auto training */
8700 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8701 dev_priv->display.write_eld = ironlake_write_eld;
8702 dev_priv->display.modeset_global_resources =
8703 ivb_modeset_global_resources;
8704 } else if (IS_HASWELL(dev)) {
8705 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8706 dev_priv->display.write_eld = haswell_write_eld;
8707 dev_priv->display.modeset_global_resources =
8708 haswell_modeset_global_resources;
8709 }
8710 } else if (IS_G4X(dev)) {
8711 dev_priv->display.write_eld = g4x_write_eld;
8712 }
8713
8714 /* Default just returns -ENODEV to indicate unsupported */
8715 dev_priv->display.queue_flip = intel_default_queue_flip;
8716
8717 switch (INTEL_INFO(dev)->gen) {
8718 case 2:
8719 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8720 break;
8721
8722 case 3:
8723 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8724 break;
8725
8726 case 4:
8727 case 5:
8728 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8729 break;
8730
8731 case 6:
8732 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8733 break;
8734 case 7:
8735 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8736 break;
8737 }
8738 }
8739
8740 /*
8741 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8742 * resume, or other times. This quirk makes sure that's the case for
8743 * affected systems.
8744 */
8745 static void quirk_pipea_force(struct drm_device *dev)
8746 {
8747 struct drm_i915_private *dev_priv = dev->dev_private;
8748
8749 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8750 DRM_INFO("applying pipe a force quirk\n");
8751 }
8752
8753 /*
8754 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8755 */
8756 static void quirk_ssc_force_disable(struct drm_device *dev)
8757 {
8758 struct drm_i915_private *dev_priv = dev->dev_private;
8759 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8760 DRM_INFO("applying lvds SSC disable quirk\n");
8761 }
8762
8763 /*
8764 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8765 * brightness value
8766 */
8767 static void quirk_invert_brightness(struct drm_device *dev)
8768 {
8769 struct drm_i915_private *dev_priv = dev->dev_private;
8770 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8771 DRM_INFO("applying inverted panel brightness quirk\n");
8772 }
8773
8774 struct intel_quirk {
8775 int device;
8776 int subsystem_vendor;
8777 int subsystem_device;
8778 void (*hook)(struct drm_device *dev);
8779 };
8780
8781 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8782 struct intel_dmi_quirk {
8783 void (*hook)(struct drm_device *dev);
8784 const struct dmi_system_id (*dmi_id_list)[];
8785 };
8786
8787 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8788 {
8789 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8790 return 1;
8791 }
8792
8793 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8794 {
8795 .dmi_id_list = &(const struct dmi_system_id[]) {
8796 {
8797 .callback = intel_dmi_reverse_brightness,
8798 .ident = "NCR Corporation",
8799 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8800 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8801 },
8802 },
8803 { } /* terminating entry */
8804 },
8805 .hook = quirk_invert_brightness,
8806 },
8807 };
8808
8809 static struct intel_quirk intel_quirks[] = {
8810 /* HP Mini needs pipe A force quirk (LP: #322104) */
8811 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8812
8813 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8814 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8815
8816 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8817 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8818
8819 /* 830/845 need to leave pipe A & dpll A up */
8820 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8821 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8822
8823 /* Lenovo U160 cannot use SSC on LVDS */
8824 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8825
8826 /* Sony Vaio Y cannot use SSC on LVDS */
8827 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8828
8829 /* Acer Aspire 5734Z must invert backlight brightness */
8830 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8831
8832 /* Acer/eMachines G725 */
8833 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
8834
8835 /* Acer/eMachines e725 */
8836 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
8837
8838 /* Acer/Packard Bell NCL20 */
8839 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
8840
8841 /* Acer Aspire 4736Z */
8842 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
8843 };
8844
8845 static void intel_init_quirks(struct drm_device *dev)
8846 {
8847 struct pci_dev *d = dev->pdev;
8848 int i;
8849
8850 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8851 struct intel_quirk *q = &intel_quirks[i];
8852
8853 if (d->device == q->device &&
8854 (d->subsystem_vendor == q->subsystem_vendor ||
8855 q->subsystem_vendor == PCI_ANY_ID) &&
8856 (d->subsystem_device == q->subsystem_device ||
8857 q->subsystem_device == PCI_ANY_ID))
8858 q->hook(dev);
8859 }
8860 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8861 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8862 intel_dmi_quirks[i].hook(dev);
8863 }
8864 }
8865
8866 /* Disable the VGA plane that we never use */
8867 static void i915_disable_vga(struct drm_device *dev)
8868 {
8869 struct drm_i915_private *dev_priv = dev->dev_private;
8870 u8 sr1;
8871 u32 vga_reg = i915_vgacntrl_reg(dev);
8872
8873 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8874 outb(SR01, VGA_SR_INDEX);
8875 sr1 = inb(VGA_SR_DATA);
8876 outb(sr1 | 1<<5, VGA_SR_DATA);
8877 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8878 udelay(300);
8879
8880 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8881 POSTING_READ(vga_reg);
8882 }
8883
8884 void intel_modeset_init_hw(struct drm_device *dev)
8885 {
8886 intel_init_power_well(dev);
8887
8888 intel_prepare_ddi(dev);
8889
8890 intel_init_clock_gating(dev);
8891
8892 mutex_lock(&dev->struct_mutex);
8893 intel_enable_gt_powersave(dev);
8894 mutex_unlock(&dev->struct_mutex);
8895 }
8896
8897 void intel_modeset_init(struct drm_device *dev)
8898 {
8899 struct drm_i915_private *dev_priv = dev->dev_private;
8900 int i, ret;
8901
8902 drm_mode_config_init(dev);
8903
8904 dev->mode_config.min_width = 0;
8905 dev->mode_config.min_height = 0;
8906
8907 dev->mode_config.preferred_depth = 24;
8908 dev->mode_config.prefer_shadow = 1;
8909
8910 dev->mode_config.funcs = &intel_mode_funcs;
8911
8912 intel_init_quirks(dev);
8913
8914 intel_init_pm(dev);
8915
8916 intel_init_display(dev);
8917
8918 if (IS_GEN2(dev)) {
8919 dev->mode_config.max_width = 2048;
8920 dev->mode_config.max_height = 2048;
8921 } else if (IS_GEN3(dev)) {
8922 dev->mode_config.max_width = 4096;
8923 dev->mode_config.max_height = 4096;
8924 } else {
8925 dev->mode_config.max_width = 8192;
8926 dev->mode_config.max_height = 8192;
8927 }
8928 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
8929
8930 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8931 INTEL_INFO(dev)->num_pipes,
8932 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
8933
8934 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
8935 intel_crtc_init(dev, i);
8936 ret = intel_plane_init(dev, i);
8937 if (ret)
8938 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8939 }
8940
8941 intel_cpu_pll_init(dev);
8942 intel_pch_pll_init(dev);
8943
8944 /* Just disable it once at startup */
8945 i915_disable_vga(dev);
8946 intel_setup_outputs(dev);
8947
8948 /* Just in case the BIOS is doing something questionable. */
8949 intel_disable_fbc(dev);
8950 }
8951
8952 static void
8953 intel_connector_break_all_links(struct intel_connector *connector)
8954 {
8955 connector->base.dpms = DRM_MODE_DPMS_OFF;
8956 connector->base.encoder = NULL;
8957 connector->encoder->connectors_active = false;
8958 connector->encoder->base.crtc = NULL;
8959 }
8960
8961 static void intel_enable_pipe_a(struct drm_device *dev)
8962 {
8963 struct intel_connector *connector;
8964 struct drm_connector *crt = NULL;
8965 struct intel_load_detect_pipe load_detect_temp;
8966
8967 /* We can't just switch on the pipe A, we need to set things up with a
8968 * proper mode and output configuration. As a gross hack, enable pipe A
8969 * by enabling the load detect pipe once. */
8970 list_for_each_entry(connector,
8971 &dev->mode_config.connector_list,
8972 base.head) {
8973 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8974 crt = &connector->base;
8975 break;
8976 }
8977 }
8978
8979 if (!crt)
8980 return;
8981
8982 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8983 intel_release_load_detect_pipe(crt, &load_detect_temp);
8984
8985
8986 }
8987
8988 static bool
8989 intel_check_plane_mapping(struct intel_crtc *crtc)
8990 {
8991 struct drm_device *dev = crtc->base.dev;
8992 struct drm_i915_private *dev_priv = dev->dev_private;
8993 u32 reg, val;
8994
8995 if (INTEL_INFO(dev)->num_pipes == 1)
8996 return true;
8997
8998 reg = DSPCNTR(!crtc->plane);
8999 val = I915_READ(reg);
9000
9001 if ((val & DISPLAY_PLANE_ENABLE) &&
9002 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9003 return false;
9004
9005 return true;
9006 }
9007
9008 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9009 {
9010 struct drm_device *dev = crtc->base.dev;
9011 struct drm_i915_private *dev_priv = dev->dev_private;
9012 u32 reg;
9013
9014 /* Clear any frame start delays used for debugging left by the BIOS */
9015 reg = PIPECONF(crtc->cpu_transcoder);
9016 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9017
9018 /* We need to sanitize the plane -> pipe mapping first because this will
9019 * disable the crtc (and hence change the state) if it is wrong. Note
9020 * that gen4+ has a fixed plane -> pipe mapping. */
9021 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9022 struct intel_connector *connector;
9023 bool plane;
9024
9025 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9026 crtc->base.base.id);
9027
9028 /* Pipe has the wrong plane attached and the plane is active.
9029 * Temporarily change the plane mapping and disable everything
9030 * ... */
9031 plane = crtc->plane;
9032 crtc->plane = !plane;
9033 dev_priv->display.crtc_disable(&crtc->base);
9034 crtc->plane = plane;
9035
9036 /* ... and break all links. */
9037 list_for_each_entry(connector, &dev->mode_config.connector_list,
9038 base.head) {
9039 if (connector->encoder->base.crtc != &crtc->base)
9040 continue;
9041
9042 intel_connector_break_all_links(connector);
9043 }
9044
9045 WARN_ON(crtc->active);
9046 crtc->base.enabled = false;
9047 }
9048
9049 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9050 crtc->pipe == PIPE_A && !crtc->active) {
9051 /* BIOS forgot to enable pipe A, this mostly happens after
9052 * resume. Force-enable the pipe to fix this, the update_dpms
9053 * call below we restore the pipe to the right state, but leave
9054 * the required bits on. */
9055 intel_enable_pipe_a(dev);
9056 }
9057
9058 /* Adjust the state of the output pipe according to whether we
9059 * have active connectors/encoders. */
9060 intel_crtc_update_dpms(&crtc->base);
9061
9062 if (crtc->active != crtc->base.enabled) {
9063 struct intel_encoder *encoder;
9064
9065 /* This can happen either due to bugs in the get_hw_state
9066 * functions or because the pipe is force-enabled due to the
9067 * pipe A quirk. */
9068 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9069 crtc->base.base.id,
9070 crtc->base.enabled ? "enabled" : "disabled",
9071 crtc->active ? "enabled" : "disabled");
9072
9073 crtc->base.enabled = crtc->active;
9074
9075 /* Because we only establish the connector -> encoder ->
9076 * crtc links if something is active, this means the
9077 * crtc is now deactivated. Break the links. connector
9078 * -> encoder links are only establish when things are
9079 * actually up, hence no need to break them. */
9080 WARN_ON(crtc->active);
9081
9082 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9083 WARN_ON(encoder->connectors_active);
9084 encoder->base.crtc = NULL;
9085 }
9086 }
9087 }
9088
9089 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9090 {
9091 struct intel_connector *connector;
9092 struct drm_device *dev = encoder->base.dev;
9093
9094 /* We need to check both for a crtc link (meaning that the
9095 * encoder is active and trying to read from a pipe) and the
9096 * pipe itself being active. */
9097 bool has_active_crtc = encoder->base.crtc &&
9098 to_intel_crtc(encoder->base.crtc)->active;
9099
9100 if (encoder->connectors_active && !has_active_crtc) {
9101 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9102 encoder->base.base.id,
9103 drm_get_encoder_name(&encoder->base));
9104
9105 /* Connector is active, but has no active pipe. This is
9106 * fallout from our resume register restoring. Disable
9107 * the encoder manually again. */
9108 if (encoder->base.crtc) {
9109 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9110 encoder->base.base.id,
9111 drm_get_encoder_name(&encoder->base));
9112 encoder->disable(encoder);
9113 }
9114
9115 /* Inconsistent output/port/pipe state happens presumably due to
9116 * a bug in one of the get_hw_state functions. Or someplace else
9117 * in our code, like the register restore mess on resume. Clamp
9118 * things to off as a safer default. */
9119 list_for_each_entry(connector,
9120 &dev->mode_config.connector_list,
9121 base.head) {
9122 if (connector->encoder != encoder)
9123 continue;
9124
9125 intel_connector_break_all_links(connector);
9126 }
9127 }
9128 /* Enabled encoders without active connectors will be fixed in
9129 * the crtc fixup. */
9130 }
9131
9132 void i915_redisable_vga(struct drm_device *dev)
9133 {
9134 struct drm_i915_private *dev_priv = dev->dev_private;
9135 u32 vga_reg = i915_vgacntrl_reg(dev);
9136
9137 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9138 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9139 i915_disable_vga(dev);
9140 }
9141 }
9142
9143 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9144 * and i915 state tracking structures. */
9145 void intel_modeset_setup_hw_state(struct drm_device *dev,
9146 bool force_restore)
9147 {
9148 struct drm_i915_private *dev_priv = dev->dev_private;
9149 enum pipe pipe;
9150 u32 tmp;
9151 struct drm_plane *plane;
9152 struct intel_crtc *crtc;
9153 struct intel_encoder *encoder;
9154 struct intel_connector *connector;
9155
9156 if (HAS_DDI(dev)) {
9157 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9158
9159 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9160 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9161 case TRANS_DDI_EDP_INPUT_A_ON:
9162 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9163 pipe = PIPE_A;
9164 break;
9165 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9166 pipe = PIPE_B;
9167 break;
9168 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9169 pipe = PIPE_C;
9170 break;
9171 default:
9172 /* A bogus value has been programmed, disable
9173 * the transcoder */
9174 WARN(1, "Bogus eDP source %08x\n", tmp);
9175 intel_ddi_disable_transcoder_func(dev_priv,
9176 TRANSCODER_EDP);
9177 goto setup_pipes;
9178 }
9179
9180 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9181 crtc->cpu_transcoder = TRANSCODER_EDP;
9182
9183 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9184 pipe_name(pipe));
9185 }
9186 }
9187
9188 setup_pipes:
9189 for_each_pipe(pipe) {
9190 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9191
9192 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9193 if (tmp & PIPECONF_ENABLE)
9194 crtc->active = true;
9195 else
9196 crtc->active = false;
9197
9198 crtc->base.enabled = crtc->active;
9199
9200 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9201 crtc->base.base.id,
9202 crtc->active ? "enabled" : "disabled");
9203 }
9204
9205 if (HAS_DDI(dev))
9206 intel_ddi_setup_hw_pll_state(dev);
9207
9208 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9209 base.head) {
9210 pipe = 0;
9211
9212 if (encoder->get_hw_state(encoder, &pipe)) {
9213 encoder->base.crtc =
9214 dev_priv->pipe_to_crtc_mapping[pipe];
9215 } else {
9216 encoder->base.crtc = NULL;
9217 }
9218
9219 encoder->connectors_active = false;
9220 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9221 encoder->base.base.id,
9222 drm_get_encoder_name(&encoder->base),
9223 encoder->base.crtc ? "enabled" : "disabled",
9224 pipe);
9225 }
9226
9227 list_for_each_entry(connector, &dev->mode_config.connector_list,
9228 base.head) {
9229 if (connector->get_hw_state(connector)) {
9230 connector->base.dpms = DRM_MODE_DPMS_ON;
9231 connector->encoder->connectors_active = true;
9232 connector->base.encoder = &connector->encoder->base;
9233 } else {
9234 connector->base.dpms = DRM_MODE_DPMS_OFF;
9235 connector->base.encoder = NULL;
9236 }
9237 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9238 connector->base.base.id,
9239 drm_get_connector_name(&connector->base),
9240 connector->base.encoder ? "enabled" : "disabled");
9241 }
9242
9243 /* HW state is read out, now we need to sanitize this mess. */
9244 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9245 base.head) {
9246 intel_sanitize_encoder(encoder);
9247 }
9248
9249 for_each_pipe(pipe) {
9250 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9251 intel_sanitize_crtc(crtc);
9252 }
9253
9254 if (force_restore) {
9255 for_each_pipe(pipe) {
9256 struct drm_crtc *crtc =
9257 dev_priv->pipe_to_crtc_mapping[pipe];
9258 intel_crtc_restore_mode(crtc);
9259 }
9260 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9261 intel_plane_restore(plane);
9262
9263 i915_redisable_vga(dev);
9264 } else {
9265 intel_modeset_update_staged_output_state(dev);
9266 }
9267
9268 intel_modeset_check_state(dev);
9269
9270 drm_mode_config_reset(dev);
9271 }
9272
9273 void intel_modeset_gem_init(struct drm_device *dev)
9274 {
9275 intel_modeset_init_hw(dev);
9276
9277 intel_setup_overlay(dev);
9278
9279 intel_modeset_setup_hw_state(dev, false);
9280 }
9281
9282 void intel_modeset_cleanup(struct drm_device *dev)
9283 {
9284 struct drm_i915_private *dev_priv = dev->dev_private;
9285 struct drm_crtc *crtc;
9286 struct intel_crtc *intel_crtc;
9287
9288 drm_kms_helper_poll_fini(dev);
9289 mutex_lock(&dev->struct_mutex);
9290
9291 intel_unregister_dsm_handler();
9292
9293
9294 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9295 /* Skip inactive CRTCs */
9296 if (!crtc->fb)
9297 continue;
9298
9299 intel_crtc = to_intel_crtc(crtc);
9300 intel_increase_pllclock(crtc);
9301 }
9302
9303 intel_disable_fbc(dev);
9304
9305 intel_disable_gt_powersave(dev);
9306
9307 ironlake_teardown_rc6(dev);
9308
9309 if (IS_VALLEYVIEW(dev))
9310 vlv_init_dpio(dev);
9311
9312 mutex_unlock(&dev->struct_mutex);
9313
9314 /* Disable the irq before mode object teardown, for the irq might
9315 * enqueue unpin/hotplug work. */
9316 drm_irq_uninstall(dev);
9317 cancel_work_sync(&dev_priv->hotplug_work);
9318 cancel_work_sync(&dev_priv->rps.work);
9319
9320 /* flush any delayed tasks or pending work */
9321 flush_scheduled_work();
9322
9323 drm_mode_config_cleanup(dev);
9324
9325 intel_cleanup_overlay(dev);
9326 }
9327
9328 /*
9329 * Return which encoder is currently attached for connector.
9330 */
9331 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9332 {
9333 return &intel_attached_encoder(connector)->base;
9334 }
9335
9336 void intel_connector_attach_encoder(struct intel_connector *connector,
9337 struct intel_encoder *encoder)
9338 {
9339 connector->encoder = encoder;
9340 drm_mode_connector_attach_encoder(&connector->base,
9341 &encoder->base);
9342 }
9343
9344 /*
9345 * set vga decode state - true == enable VGA decode
9346 */
9347 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9348 {
9349 struct drm_i915_private *dev_priv = dev->dev_private;
9350 u16 gmch_ctrl;
9351
9352 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9353 if (state)
9354 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9355 else
9356 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9357 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9358 return 0;
9359 }
9360
9361 #ifdef CONFIG_DEBUG_FS
9362 #include <linux/seq_file.h>
9363
9364 struct intel_display_error_state {
9365 struct intel_cursor_error_state {
9366 u32 control;
9367 u32 position;
9368 u32 base;
9369 u32 size;
9370 } cursor[I915_MAX_PIPES];
9371
9372 struct intel_pipe_error_state {
9373 u32 conf;
9374 u32 source;
9375
9376 u32 htotal;
9377 u32 hblank;
9378 u32 hsync;
9379 u32 vtotal;
9380 u32 vblank;
9381 u32 vsync;
9382 } pipe[I915_MAX_PIPES];
9383
9384 struct intel_plane_error_state {
9385 u32 control;
9386 u32 stride;
9387 u32 size;
9388 u32 pos;
9389 u32 addr;
9390 u32 surface;
9391 u32 tile_offset;
9392 } plane[I915_MAX_PIPES];
9393 };
9394
9395 struct intel_display_error_state *
9396 intel_display_capture_error_state(struct drm_device *dev)
9397 {
9398 drm_i915_private_t *dev_priv = dev->dev_private;
9399 struct intel_display_error_state *error;
9400 enum transcoder cpu_transcoder;
9401 int i;
9402
9403 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9404 if (error == NULL)
9405 return NULL;
9406
9407 for_each_pipe(i) {
9408 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9409
9410 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9411 error->cursor[i].control = I915_READ(CURCNTR(i));
9412 error->cursor[i].position = I915_READ(CURPOS(i));
9413 error->cursor[i].base = I915_READ(CURBASE(i));
9414 } else {
9415 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9416 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9417 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9418 }
9419
9420 error->plane[i].control = I915_READ(DSPCNTR(i));
9421 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9422 if (INTEL_INFO(dev)->gen <= 3) {
9423 error->plane[i].size = I915_READ(DSPSIZE(i));
9424 error->plane[i].pos = I915_READ(DSPPOS(i));
9425 }
9426 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9427 error->plane[i].addr = I915_READ(DSPADDR(i));
9428 if (INTEL_INFO(dev)->gen >= 4) {
9429 error->plane[i].surface = I915_READ(DSPSURF(i));
9430 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9431 }
9432
9433 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9434 error->pipe[i].source = I915_READ(PIPESRC(i));
9435 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9436 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9437 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9438 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9439 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9440 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9441 }
9442
9443 return error;
9444 }
9445
9446 void
9447 intel_display_print_error_state(struct seq_file *m,
9448 struct drm_device *dev,
9449 struct intel_display_error_state *error)
9450 {
9451 int i;
9452
9453 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9454 for_each_pipe(i) {
9455 seq_printf(m, "Pipe [%d]:\n", i);
9456 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9457 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9458 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9459 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9460 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9461 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9462 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9463 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9464
9465 seq_printf(m, "Plane [%d]:\n", i);
9466 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9467 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9468 if (INTEL_INFO(dev)->gen <= 3) {
9469 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9470 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9471 }
9472 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9473 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9474 if (INTEL_INFO(dev)->gen >= 4) {
9475 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9476 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9477 }
9478
9479 seq_printf(m, "Cursor [%d]:\n", i);
9480 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9481 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9482 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9483 }
9484 }
9485 #endif
Ubuntu Hirsute Linux kernel mirror